[Journal] IEEE Transactions on Microwave Theory and Techniques. Vol. 64. No 4

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APRIL 2016

VOLUME 64

NUMBER 4

IETMAB

(ISSN 0018-9480)

MINI-SPECIAL ISSUE ON 2015 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM (RFIC 2015) Guest Editorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H. Xie

1017

MINI-SPECIAL ISSUE PAPERS

A Fully Integrated 60-GHz CMOS Direct-Conversion Doppler Radar RF Sensor With Clutter Canceller for Single-Antenna Noncontact Human Vital-Signs Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H.-C. Kuo, C.-C. Lin, C.-H. Yu, P.-H. Lo, J.-Y. Lyu, C.-C. Chou, and H.-R. Chuang A 65-nm CMOS Low-Power Impulse Radar System for Human Respiratory Feature Extraction and Diagnosis on Respiratory Diseases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S.-T. Tseng, Y.-H. Kao, C.-C. Peng, J.-Y. Liu, S.-C. Chu, G.-F. Hong, C.-H. Hsieh, K.-T. Hsu, W.-T. Liu, Y.-H. Huang, S.-Y. Huang, and T.-S. Chu Design and Optimization of Area-Constrained Wirelessly Powered CMOS UWB SoC for Localization Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . J. Kang, S. Rao, P. Chiang, and A. Natarajan Low-Power Injection-Locked Zero-IF Self-Oscillating Mixer for High Gbit/s Data-Rate Battery-Free Active RFID Tag at Millimeter-Wave Frequencies in 65-nm CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P. Burasa, N. G. Constantin, and K. Wu Dynamic Polarization Control of Two-Dimensional Integrated Phased Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A. Safaripour, S. M. Bowers, K. Dasgupta, and A. Hajimiri High-Performance E-Band Transceiver Chipset for Point-to-Point Communication in SiGe BiCMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . R. Levinger, R. B. Yishay, O. Katz, B. Sheinman, N. Mazor, R. Carmon, and D. Elad An Interference-Resilient Wideband Mixer-First Receiver With LO Leakage Suppression and I/Q Correlated Orthogonal Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C. Wu, Y. Wang, B. Nikoli´c, and C. Hull A Sub-1-V 194- W 31-dB FOM 2.3–2.5-GHz Mixer-First Receiver Frontend for WBAN With Mutual Noise Cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M. Rahman and R. Harjani A 0.4–6-GHz 17-dBm B1dB 36-dBm IIP3 Channel-Selecting Low-Noise Amplifier for SAW-Less 3G/4G FDD Diversity Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C. Luo, P. S. Gudem, and J. F. Buckwalter Analysis and Design of an E-Band Transformer-Coupled Low-Noise Quadrature VCO in 28-nm CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M. Vigilante and P. Reynaert A Multi-Frequency Multi-Standard Wideband FractionalPLL With Adaptive Phase-Noise Cancellation for Low-Power Short-Range Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Y. Zhang, J. H. Mueller, B. Mohr, L. Liao, A. Atac, R. Wunderlich, and S. Heinen

1018 1029 1042 1055 1066 1078 1088 1102 1110 1122 1133

(Contents Continued on Back Cover)

(Contents Continued from Front Cover) Design and Characterization of a 3-bit 24-GS/s Flash ADC in 28-nm Low-Power Digital CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G. Tretter, M. M. Khafaji, D. Fritsche, C. Carta, and F. Ellinger

1143

REGULAR PAPERS

EM Theory and Analysis Techniques Modal Theory for Waveguides With Anisotropic Surface Impedance Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . N. Raveu, B. Byrne, L. Claudepierre, and N. Capet A Novel -TEM Mixed-Mode Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . S. Peng, C. Yuan, T. Shu, X. Zhao, and Q. Zhang A Novel to Mode Converter Designed With Radially Loaded Dielectric Slabs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A. Chittora, S. Singh, A. Sharma, and J. Mukherjee A Miniaturized Uniplanar Metamaterial-Based EBG for Parallel-Plate Mode Suppression . . . . . . . S. Barth and A. K. Iyer Multiple Fano-Like Transmission Mediated by Multimode Interferences in Spoof Surface Plasmon Cavity-Waveguide Coupling System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F. F. Qin, J. J. Xiao, Z. Z. Liu, and Q. Zhang Devices and Modeling Dynamical Equivalent Circuit for 1-D Periodic Compound Gratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C. Molero, R. Rodríguez-Berral, F. Mesa, and F. Medina Surface Roughness Modeling of Substrate Integrated Waveguide in D-Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M. Yi, S. Li, H. Yu, W. Khan, C. Ulusoy, A. Vera-Lopez, J. Papapolymerou, and M. Swaminathan Modeling the Conductor Losses of Thick Multiconductor Coplanar Waveguides and Striplines: A Conformal Mapping Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F. Bertazzi, V. Camarchia, M. Goano, M. Pirola, and G. Ghione Synthesis of Multiport Networks Using Port Decomposition Technique and its Applications . . . . . . . . R. Sinha and A. De Passive Circuits Design of -Band Transition From Microstrip to Ridge Gap Waveguide Including Monte Carlo Assembly Tolerance Analysis . . . . . . . . . . . . . . . . . . A. Algaba Brazález, J. Flygare, J. Yang, V. Vassilev, M. Baquero-Escudero, and P.-S. Kildal A Flip-Chip Packaging Design With Waveguide Output on Single-Layer Alumina Board for E-Band Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Y. Zhang, D. Zhao, and P. Reynaert Synthesis and Design of Mixed Lumped and Distributed Low-Pass Filters/Low-Passing Impedance Transformers With Taylor Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . R. Zhang, S. Luo, and L. Zhu Hybrid and Monlithic RF Integrated Circuits Symmetrical Doherty Power Amplifier With Extended Efficiency Range . . . . . . . . . M. Özen, K. Andersson, and C. Fager A -Band 48-Gbit/s 64-QAM/QPSK Direct-Conversion I/Q Transceiver Chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S. Carpenter, D. Nopchinda, M. Abbasi, Z. S. He, M. Bao, T. Eriksson, and H. Zirath Instrumentation and Measurement Techniques Experimental Verification of Below-Cutoff Propagation in Miniaturized Circular Waveguides Using Anisotropic ENNZ Metamaterial Liners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . J. G. Pollock and A. K. Iyer Identifying Multiple Reflections in Distributed-Lumped High-Frequency Structures . . . . . . . . . . . . . M. Zyari and Y. Rolain RF Systems and Applications Multi-Way Lossless Outphasing System Based on an All-Transmission-Line Combiner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T. W. Barton, A. S. Jurkov, P. H. Pednekar, and D. J. Perreault Sensitive and Efficient RF Harvesting Supply for Batteryless Backscatter Sensor Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S. D. Assimonis, S.-N. Daskalakis, and A. Bletsas Analyzing Single Giant Unilamellar Vesicles With a Slotline-Based RF Nanometer Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Y. Cui, A. K. Kenworthy, M. Edidin, R. Divan, D. Rosenmann, and P. Wang

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CALLS FOR PAPERS

Special Issue on Emerging RF Measurement Techniques and Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Digital Object Identifier 10.1109/TMTT.2016.2547501

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 64, NO. 4, APRIL 2016

1017

Guest Editorial

T

HIS TRANSACTIONS’ Mini-Special Issue includes 12 papers from the 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC 2015) held in Phoenix, AZ, USA, May 17–19, 2015. The symposium is co-located with the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) International Microwave Symposium (IMS) each year and is a premier symposium of the IEEE MTT-S. Out of a total of 186 submissions, 91 papers were accepted (49% acceptance rate) for publication in the 2015 RFIC Symposium Digest. These papers have also been published online on IEEE Xplore. After the symposium, the conference committee nominated 17 papers presented at RFIC 2015 to submit expanded papers to this TRANSACTIONS’ Mini-Special Issue, while encouraging other authors of accepted papers to submit expanded papers as well. A total of 33 papers (including 12 papers nominated by the conference committee) were submitted and were reviewed by experts in respective areas. Based on the reviewer recommenda-

Digital Object Identifier 10.1109/TMTT.2016.2536903

tions after rigorous reviews, a total of 12 papers (including 4 papers nominated by the conference committee) were accepted for publication in this TRANSACTIONS’ Mini-Special Issue. I am deeply thankful to all the reviewers for sharing their time and expertise, and providing valuable feedback to the authors. This TRANSACTIONS’ Mini-Special Issue would not have been possible without the support and help of this TRANSACTIONS’ Editors-in-Chief, Prof. Jenshan Lin and Prof. Dominique Schreurs, and Associate Editor Prof. Tian-Wei Huang, as well as the support of the RFIC 2015 Chairs, Prof. Bertan Bakkaloglu and Prof. Albert Wang, who played key roles in organizing RFIC 2015. I am deeply thankful to them. On behalf of the conference Steering Committee, I also thank the authors of this TRANSACTIONS’ Mini-Special Issue and the RFIC Symposium for their valuable contributions. HAOLU XIE, Guest Editor Analog Products Group ZTE USA Austin, TX 78730 USA

Haolu Xie (S’06–M’07–SM’13) received the Bachelor degree from Zhejiang University, Hangzhou, China, in 1997, and the M.S. and Ph.D. degrees from the Illinois Institute of Technology at Chicago, Chicago, IL, USA, in 2004 and 2007, respectively. He is currently a Senior Director with the Analog Products Group, ZTE USA, Austin, TX, USA. He has authored or coauthored 35 publications. He holds 16 patents. His research interests are analog circuit design with an emphasis on RF and wireless communication applications, low-power design techniques, and high-performance A/D and D/A converters. Dr. Xie is a Member of the IEEE RFIC Symposium Steering Committee. He was a recipient of the IEEE Region 6 Young Engineer of the Year Award in 2011 in recognition of his distinguished technical leadership of transceiver design.

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A Fully Integrated 60-GHz CMOS Direct-Conversion Doppler Radar RF Sensor With Clutter Canceller for Single-Antenna Noncontact Human Vital-Signs Detection Hsin-Chih Kuo, Member, IEEE, Chien-Chih Lin, Student Member, IEEE, Chun-Han Yu, Student Member, IEEE, Pei-Hua Lo, Student Member, IEEE, Jhin-Ying Lyu, Student Member, IEEE, Chien-Chang Chou, Student Member, IEEE, and Huey-Ru Chuang, Senior Member, IEEE

Abstract—This paper presents a 60-GHz CMOS direct-conversion Doppler radar RF sensor with a clutter canceller for single-antenna noncontact human vital-signs detection. A high isolation quasi-circulator (QC) is designed to reduce the transmitting (Tx) power leakage (to the receiver). The clutter canceller performs cancellation for the Tx leakage power (from the QC) and the stationary background reflection clutter to enhance the detection sensitivity of weak vital signals. The integration of the 60-GHz RF sensor consists of the voltage-controlled oscillator, divided-by-2 frequency divider, power amplifier, QC, clutter canceller (consisting of variable-gain amplifier and 360 phase shifter), low-noise amplifier, in-phase/quadrature-phase sub-harmonic mixer, and three couplers. In the human vital-signs detection experimental measurement, at a distance of 75 cm, the detected heartbeat (1–1.3 Hz) and respiratory (0.35–0.45 Hz) signals can be clearly observed with a 60-GHz 17-dBi patch-array antenna. The RF sensor is fabricated in 90-nm CMOS technology with a chip size of 2 mm 2 mm and a consuming power of 217 mW. Index Terms—Clutter canceller, Doppler radar, human vital signs, millimeter-wave (MMW), noncontact, quasi-circulator (QC), RF sensor, 60 GHz.

I. INTRODUCTION

I

T HAS been decades since the research of Doppler radars for remotely detecting human vital signals have been reported [1]–[13]. Recently, for the wireless health-care application, the noncontact human vital-signs detection systems have Manuscript received August 10, 2015; revised December 08, 2015 and February 15, 2016; accepted February 20, 2016. Date of publication March 15, 2016; date of current version April 01, 2016. This work was supported by the National Science Council of Taiwan under Grant NSC 102-2220-E-006-011 and Grant NSC 102-2221-E-006-274-MY3. This paper is an expanded version from the IEEE RFIC Symposium, Phoenix, AZ, USA, May 17–19, 2015. H.-C. Kuo was with the Institute of Computer and Communication Engineering, Department of Electrical Engineering, National Cheng Kung University, Tainan 70101, Taiwan. He is now with the Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu 30075, Taiwan. C.-C. Lin, C.-H. Yu, P.-H. Lo, J.-Y. Lyu, C.-C. Chou, and H.-R. Chuang are with the Institute of Computer and Communication Engineering, Department of Electrical Engineering, National Cheng Kung University, Tainan 70101, Taiwan (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2536600

been studied extensively. It can avoid error detections caused by disconnection of electrode wires, reduce the inconvenience of long-term wearing of traditional electrocardiography (ECG) equipment, protect the privacy of the patient (without taking off clothes), and provide real-time monitoring of the life of burnt people (or those who cannot use an electrode) to medical personnel. In order to pursue the high-performance low-cost low-power radar sensor chip, extensive goal efforts to develop a fully integrated vital-signs Doppler radar RF sensor chip have been conducted and reported. From reported state-of-the-art chips, most works used 1.6-, 2.4-, or 5.8-GHz band [4]–[6], and the Ka-band [7]. Moreover, the 60-GHz millimeter-wave (MMW) frequency band for vitalsigns Doppler radar application has also been investigated. A 60-GHz MMW life detection system (MLDS) prototype constructed by using V-band MMW waveguide components has been reported [8]. Furthermore, the 60-GHz CMOS Doppler radar sensor chip with two- or single-antenna noncontact vitalsigns detection are reported [9], [10]. In this paper, which is the expansion over [10], we elaborate on the CMOS circuit design of this 60-GHz vital-signs radar sensor chip in much more detail. The mathematical model of RF signal and clutter for a single-antenna Doppler radar and quasi-circulator (QC) are also included. Besides, more circuit design details are addressed, including the transistor sizes for each block, standalone measurements performance, and some additional illustration figures. Moreover, in conjunction with [15], by using the spherical muscle heart model to compute the radar cross section (RCS) of the heart sphere and the vital-sign receiving power for different frequencies from the radar equation for simulation comparison. We discuss that for the higher frequency may have a higher value than the lower one (which is due to a much higher antenna gain, although with a larger path loss). Sensitivity is always one of the critical issues in the radar system. The radar RF transceiver front-end architecture plays an important role in reducing the noise, increasing detection sensitivity, and extending the vital-signs sensing range. For example, most reported radar RF transceivers share the same local oscillator (LO) signal to take the advantage of the range correlation effect [4], [5], [7], [8], [11]. It lets the high phase noise close to

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KUO et al.: FULLY INTEGRATED 60-GHz CMOS DIRECT-CONVERSION DOPPLER RADAR RF SENSOR

the dc frequency be greatly suppressed and not to greatly corrupt the detected vital signals, which are proximate to the dc frequency. In [11], the harmonic radar architecture is used to improve the detection sensitivity by increasing the signal-to-noise ratio (SNR). In [12], the vital-sign radar with a single channel receiver based on a self-injection-locked oscillator is proposed. However for the single-antenna Doppler radar system, as shown in Fig. 1, the transmitter (Tx) leakage signals (through the circulator) and the stationary background reflection clutter signals can also highly degrade the detecting sensitivity. For radar application, compared with the two-antenna system, single-antenna architecture [2], [8], [10], [11], [13] will have a smaller Doppler radar device size. The Tx leakage canceller in [13] is basically composed of four branch-line hybrid couplers, a 90 delay line, and a Wilkinson power combiner with high Tx-to-Rx isolation and wide bandwidth characteristics. Since the high isolation properties can suppress Tx leakage power, the sensitivity of the radar Rx and detection range can be further improved. However, the four planer branch-line couplers are of area inefficiency. In the CMOS single-antenna Doppler radar sensor, to integrate a high-isolation circulator with a competitive chip size will be a challenge. Hence, if the operating frequency goes up to MMW range such as 60 GHz, it will be easier to integrate more high-performance passive components with small size. Also with a fixed small size, an antenna can posses a higher gain at higher frequency as observed from the theoretical upper bond of the antenna gain [14], where is the antenna aperture diameter. For example, if cm, the antenna gain at 60 and 2.4 GHz are 25.5 and 2.5 dB, respectively. It is then noted that from the radar equation (where and are the transmitting and receiving power, is the RCS, is the distance, and is the antenna gain) -

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Fig. 1. Illustration of the simple diagram of a Doppler radar RF sensor with clutter canceller circuits for single-antenna noncontact human vital-signs detection.

where is the amplitude of the transmitting signal, is the oscillation frequency, and is the phase noise of the oscillator. The received signal can be represented as (3) where is the amplitude of the received signal, is the detection distance, and is the periodic movement induced by the chest by the breathing and heartbeat. However, in practice, the Tx leakage from the imperfect isolation of the circulator and the unwanted background-reflected clutter signal (together with the tiny vital signal) would be received at the same time. The total received signal can be rewritten as

(1) (4)

where the free-space two-way path loss, , at higher frequency is larger than that at lower frequency. However, the ratio of may still be higher for a small antenna size at higher frequency. As is proportional to and the antenna gain is proportional to [14]. Hence, is proportional to , assuming the RCS is similar to those in [15, Table I]. For example, the ratio of at 60 GHz theoretically may be 24 dB higher than that at 2.4 GHz [15]. Also, it becomes easier to integrate the antenna into the radar sensor module at much higher operation frequency (such as 60 GHz). The basic operation principle of a continuous wave (CW) radar has been depicted in [5]. As shown in Fig. 1, an MMW signal source produces a CW carrier and is fed into a directional coupler. One output of the directional coupler is amplified by a power amplifier (PA) and fed through a circulator to the antenna. The other output provides an LO signal for the receiver and clutter canceller. The single-tone transmitting signal is (2)

where and are the amplitude and phase of the Tx leakage signal and the stationary clutter signal, respectively. As observed, the large unwanted Tx leakage and clutter signals may saturate the radar receiver and interfere with normal radar operations. As illustrated in Fig. 2, in this work the clutter canceller circuit consists of a variable-gain amplifier (VGA) and a full 360 continuously adjustable phase shifter (PS). For comparison, Table I summaries the cancellation target of clutter noise components and used circuit topologies of the Tx leakage canceller and clutter canceller, respectively. This paper presents a 60-GHz fully integrated direct-conversion vital-signs Doppler radar RF sensor chip with a built-in clutter canceller circuit for single-antenna operation in 90-nm CMOS. Section II describes the radar RF transceiver architecture and the details of the circuit design for each block of the RF transceiver with a high isolation QC and clutter canceller circuits. Section III discusses the probe-station-based on-wafer CW test and human vital-signs detection experimental measurement and compare with the simulated results in detail.

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Fig. 2. Block diagram of 60-GHz CMOS direct-conversion Doppler radar RF sensor with clutter canceller circuits for single-antenna noncontact human vital-signs detection. Also shown in the figure (right) is the illustration of the concept of clutter cancellation.

II. CIRCUIT DESIGN Fig. 2 shows the detail block diagram of the proposed 60-GHz CMOS direct-conversion vital-signs Doppler radar RF sensor with a high isolation QC and a clutter canceller circuit for single-antenna operation. The 60-GHz radar chip consists of a voltage-controlled oscillator (VCO), divided-by-2 frequency divider (FD), PA, QC, clutter canceller (with a low phase-variation VGA and a full 360 continuously adjustable PS), low-noise amplifier (LNA), in-phase/quadrature-phase (I/Q) sub-harmonic mixer (SHM), and three directional couplers. To have a better understanding of the cancellation of Tx leakage (from QC), , and stationary background clutter, , the equivalent signal of these two signals can be derived as

(5) and are the amplitude and the related phase of where the equivalent summation signal, respectively, and , , , and are expressed as follows:

(6)

Note that if there are a number of stationary clutters, an equivalent sinusoidal clutter signal with the same frequency can still be formed from those stationary clutter signals. Hence, according to (5), to cancel the equivalent summation of the Tx leakage and clutter signal, the output signal of the clutter canceller should be (7) is to be combined with the receiving reflected signal (together with the Tx leakage and clutter) in the broadside coupler for clutter cancellation. The output of the broadside coupler

then merely contains the weak backscattered phase-modulated received signal (by the breathing and heartbeat) from the human body. It is then amplified by the LNA and mixed with the LO signal in an SHM. A. Tx Circuits Design The main part of the Tx consists of an LC-tank VCO and a PA. The VCO provides the CW signal to Tx and clutter canceller. It also serves to be the injection signal of the conventional divided-by-2 FD as the LO to the Rx SHM, which needs to have sufficient output power and good signal quality. Hence, the VCO should be optimized for the Rx and clutter canceller. As shown in Fig. 3, the VCO utilized NMOS cross-coupled pair to provide the required negative conductance and the resonator is formed by an inductor and a varactor. Moreover, in order to relax the startup condition and enhance phase noise performance at MMW frequency, the admittance-transforming technique [16] is applied. The high impedance thin-film microstrip (TFMS) lines ( and ) of 250- m length acts an inductor to mitigate the varactors loss. As shown in the equivalent circuit model for the LC tank, a better VCO performance can be obtained since the TFMS line and varactor can be modeled as a tunable inductor by using the admittance-transforming technique. The measured output power and phase noise of the standalone VCO are 7.3 dBm and 92 dBc/Hz @ 1-MHz offset [see Fig. 3(c)], respectively. For the PA design, as shown in Fig. 4, a three-stage cascode PA configuration is adopted to maximize the power gain. The transconductance transistor biased in class-A is to achieve a better linearity and higher output power. Since the first stage acts as a pre-amplifier, the size of the transistors by 24 fingers with each finger width of 3 m is selected to maintain a higher gain and a lower quiescent power for PAE improvement. Power transistors are selected to be 32 fingers with each finger width of 3 m for the third stage with a higher output power and sufficient power gain. The simulated PA gain, , and PAE are 22 dB, 8.5 dBm, and 10.5%, respectively. In addition to avoiding the unwanted coupling noise and spurs between the

KUO et al.: FULLY INTEGRATED 60-GHz CMOS DIRECT-CONVERSION DOPPLER RADAR RF SENSOR

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TABLE I Tx LEAKAGE CANCELLATION AND CLUTTER CANCELLER FUNCTION DESCRIPTION

Fig. 5. Concepts of the passive core of 60-GHz high isolation QC.

B. High-Isolation QC Design The on-chip high-isolation QC is a key component for the single-antenna radar. As shown in Fig. 5, the QC is realized by using three identical quadrature hybrids, which are built using the broadside microstrip coupled lines. Simultaneous transmitting and receiving are achieved by phase combination and cancellation [17]. For example, the input signal to the input port of the quadrature coupler #1, Fig. 3. 60-GHz VCO with admittance-transforming technique. (a) Circuit schematic. (b) Chip photograph. (c) Measured standalone phase noise.

(8) where is the amplitude of the input transmitting signal, is the phase of input transmitting signal, and the total transmitting signal at the antenna port by phase combination is

(9)

Fig. 4. Circuit schematic of the 60-GHz three-stage cascode PA.

VCO and PA from the substrate, the guard ring is used to alleviate the coupling effect.

where is the signal at the antenna port. The same rule applies to the receiving path, the receiving signal can be expressed as

(10)

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Fig. 6. Circuit schematic of the 60-GHz VGA.

Fig. 8. Gain and transmission phase of the VGA. (a) Simulated comparison transistors . (b) Simulated and measured of different size of the results. Fig. 7. Circuit schematic of the 60-GHz full 360 continuously adjustable PS.

where is the amplitude of the input signal at the antenna port and is the phase of that signal. Therefore, the signal can only pass one-way from the Tx to antenna port and antenna port to the Rx. As for Tx-to-Rx isolation, since the isolation performance of the MMW coupler is not quite high, the high isolation performance is achieved by phase cancellation instead of the isolation performance of each coupled-line couplers. The Tx-to-Rx isolation - can be derived as -

Fig. 9. Simulated and measured results of the gain and phase shift of the standalone clutter canceller.

(11) Therefore, the physical layout of each path should be carefully designed to maintain consistency. Also, compared to the edge coupling structure, the broadside coupled-line coupler can provide a lower insertion loss, a wider operation bandwidth, and a compact size. In this study, the ground plane is placed at the bottom metal, and the broadside coupled-line coupler is used by the top two metal layers. The QC simulated isolation is about 31 dB between the Tx and Rx ports at 60 GHz with a compact size of 0.34 mm 0.44 mm. The simulated result of the integrated transmitter indicates that the total Tx power

is 2 dBm at 60 GHz with a dc consumption of 165.5 mW. Note that is the VCO output power, is insertion loss of the coupler, is the gain of the PA, and is the insertion loss of the QC. C. Clutter Canceller Circuits Design As mentioned in Section I, the clutter canceller circuit consists of a VGA [18] and a full 360 continuously adjustable PS [19], [20]. Figs. 6 and 7 show the schematic of the low phase-variation VGA for gain tuning and a full 360 CMOS low-gain-variation PS for phase tuning. The VGA adopts the

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Fig. 10. Probe-station-based measurement setup for the radar RF sensor chip. (a) CW test. (b) Human vital-signs detection.

current steering structure for gain control. It also needs to maintain good phase flatness to reduce the burden of phase control capability of the PS. and are in charge of the values of peak gain, transmission output phase, and transconductance (for gain control range). Fig. 8(a) shows simulation analysis. It can be observed that the larger size of , the wider gain control range will be obtained with the higher transmission phase variation. In addition, the output transmission phase is also sensitive to the transistors . If the transmission phase of is proportional to the control voltage , the disproportional phase of should be chosen to compensate the phase flatness. With the considerations of gain control range and phase variation, with 20 fingers for the VGA and with 30 fingers for the current steering stage (each with m m per finger) were adopted. As plotted in Fig. 8(b), the measured gain, gain control range, and phase variation of the standalone VGA are 18 dB, 10.5 dB, and 10 from the control voltage of 1–1.6 V, respectively. The same concept applies to the PS, the gain variation should be as low as possible to maintain the VGA gain control function. The 360 PS is implemented by cascading a continuous 180 reflection-type phase shifter (RTPS) and a switchable 0 180 switch-type phase shifter (STPS). The RTPS is composed of a 3-dB quadrature broadside coupler and four reflective loads to . For the STPS, a transmission line is utilized to realize the 180 phase-control range. By adjusting the capacitance of the varactors in the reflective loads ( to ) and switching voltage , a range of 360 phase control can be obtained. It is noted that the gain variation of the PS is mainly affected by the change of (the real part of ).

to are placed in seTo reduce this effect, capacitances ries with two varactors. From the simulation results, the values of and are carefully designed to be 500 and 157 fF to obtain both the optimized phase control range and gain variation performance. For the integrated clutter canceller, the simulation results show that it can achieve a 20.4-dB cancellation while with a power consumption of 24 mW and a chip size of 0.5 mm 1 mm. Fig. 9 shows the measured gain variation of the standalone clutter canceller is less than 3 dB across 360 phase shift. D. Rx Circuits Design The vital-sign Doppler radar receiver consists of an LNA, a Wilkinson power divider, and two SHMs. A two-stage cascode structure with a common source (CS) buffer amplifier is used for the LNA core. The design tradeoffs between power gain and NF are considered for the first two stages of the LNA. Therefore, the gate-inductive gain-peaking technique and the inter-stage noise filtering scheme are adopted in the first and second amplifier stages to optimize the available gain and NF. In addition, the microstrip spiral inductors of approximate 170 pH in series with the signal path between the CS and common gate stages in each cascode structure are for noise reduction design. The measured LNA exhibited the best gain of 22 dB around 57.3 GHz and a minimum NF of 3.7 dB. To minimize the LO leakage and dc offset from the mixer, the SHM is adopted. Two Marchand baluns are integrated into the mixer at the input nodes for providing 180 phase signals. Also, two open stubs are used to improve RF-to-IF isolation. The simulated total receiver

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Fig. 14. Simulated and measured total Rx conversion gain.

Fig. 11. Chip micrograph chip size

mm

mm .

Fig. 15. Simulated and measured

of the Rx and standalone LNA.

Fig. 12. Simulated and measured Tx power (after QC).

Fig. 16. Simulated and measured QC isolation.

Fig. 13. Simulated and measured return loss of the antenna port.

gain and are 13.5 dB and 23 dBm with a power consumption of 31 mW. The related sub-circuit (LNA and mixer) performances have been described in [21]. III. SIMULATION AND EXPERIMENTAL MEASUREMENT The developed fully integrated 60-GHz CMOS direct-conversion Doppler radar RF sensor is fabricated in 90-nm CMOS with a chip size of 2 mm 2 mm (including the test pads and

dummy metal, see Fig. 11). The total power consumption is 217 mW. Fig. 10 illustrates the probe-station-based measurement setups for the developed vital-sign Doppler radar sensor chip. In the CW test [see Fig. 10(a)], the spectrum analyzers (Agilent E4440A), signal generators (Agilent E8257D), and oscilloscopes (Agilent DSO9000A) are used to measure the total Tx power, the total Rx gain, the QC isolation, as well as the clutter cancellation performance, respectively. In human vital-signs test, as shown in Fig. 10(b), the radar sensor chip is connected by a 7-dB-loss V-band cable and the RF probe to a 60-GHz patch-array antenna (17-dBi gain). The radiating 60-GHz CW from the antenna incidents the human subject and the reflected wave to the antenna is phase modulated by vital signs. The received signal through the QC and amplified by the LNA is down-converted by the SHM. The down-converted

KUO et al.: FULLY INTEGRATED 60-GHz CMOS DIRECT-CONVERSION DOPPLER RADAR RF SENSOR

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Fig. 17. Simulated and measured clutter cancellation performance. (a) Turning off and on clutter canceller and (b) clutter cancellation performance.

I- and Q-channel vital signals are then amplified by the operation amplifier (accompanied by a 5-Hz low-pass filter) and processed by LabVIEW with the NI 6009 multifunction data acquisition (DAQ) in sequence. In addition, the complex signal demodulation (CSD) [22] is used for the null point problem and resulted vital-signal is expressed as

TABLE II CW TEST AND VITAL-SIGNS DETECTION PERFORMANCE SUMMARY

(12) where and are the I- and Q-channel baseband signals (see Fig. 2). The CSD method is also insensitive to dc offsets existing in the I/Q channels and may not affect the measurement accuracy. Hence, the detection robustness is improved [22]. A. Analog CW Performance The measured result showing in Fig. 12 indicates that the VCO cover the frequency tuning range from 59.5 to 60.7 GHz and the total Tx power are 3 dBm at 60 GHz with a DC consumption of 165 mW. Fig. 13 shows that the measured output return loss is better than 10 dB from 55 to 63 GHz. As shown in Figs. 14 and 15, the measured Rx gain and are 10.5 dB and 23 dBm with a power consumption of 31 mW, where and are LNA gain and SHM conversion gain, respectively. Fig. 16 shows that Tx-to-Rx port isolation of the QC is about 30 dB of which the Tx leakage power can be estimated to satisfy the clutter cancellation planning. Fig. 17(a) illustrates the measured total equivalent clutter power when turning off and on the clutter canceller. Fig. 17(b) shows that the clutter power (calibrated out the external cable loss) can be reduced from 7.3 to below 30.8 dBm when the control voltage of the VGA and PS are set to 1.5 and 0.95 V (at mode-1, shown in Fig. 7), respectively. About 23.5-dB clutter cancellation performance is achieved with a power consumption of 21 mW. Table II lists the performance summary of the CW test (upper table). B. Human Vital-Signs Detection Performance Fig. 18 depicts that the detected time-domain vibrating waveform amplitude of the vibrating actuator. A 60-GHz 17-dBi patch-array antenna (with a size of 4 cm 2.2 cm on

an RT/Duroid substrate of a substrate thickness 0.127 mm and ) is used. The minimal detectable displacement is about 15–20 m at a distance of 30 cm. When turning off the clutter canceller, the total equivalent clutter signal of Tx leakage and stationary background reflection clutter power is about from 5 to 7 dBm. After turning on the clutter canceller, the total equivalent clutter signal is reduced to about 35 dBm. In Fig. 18(a), it can be observed that the detected waveform amplitude (by turning on the clutter canceller) is about four times larger than that at turning off state. In the frequency CSD spectrum, as shown in Fig. 18(b), it can be especially observed that the clutter canceller can highly reduce the Rx saturation problem caused by the Tx leakage and clutter power (which will radically decrease the LNA amplification of the vital-signs signal) and greatly increase Rx SNR and the detection sensitivity (about a 10 ratio for detected amplitude). Hence, with the clutter canceller, the time-domain signal and CSD frequency-domain spectrum would become clearer and much easier to recognize the tiny vibrating signal. For the human vital-signs detection test, Fig. 19 shows the time-domain waveforms and frequency CSD spectrums of the measured

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Fig. 18. Measured time-domain vibrating waveforms of the vibrating actuator when turning on and off the clutter canceller: (a) time-domain waveform and (b) CSD frequency spectrum.

Fig. 19. Measured breathing and heartbeat signals of the human subject at a distance of 75 cm: (a) time-domain I/Q signal of the heartbeat signal, (b) CSD frequency spectrum of the heartbeat signal, (c) time-domain I/Q signal of the breathing signal, and (d) CSD frequency spectrum of the breathing signal.

breathing and heartbeat (with the subject holding its breath) of a human subject at a distance of 75 cm. The measured heartbeat and respiration frequency are around 1.1 Hz (66 beats/min) and 0.4 Hz (24 breaths/min), respectively. It can be observed that the detected I- and Q-channel time-domain waveforms have a certain degree of difference due to the human target position [5], [22]. This is the advantage of the I/Q-channel receiver than the single-channel one of which the received signal may be in poor condition. Moreover, I and Q two-channel received signals can use CSD [see (12)] to achieve a good frequency spectrum of vital sign. Table II lists the performance summary of the vital-signs detection test (bottom table). It is noted that, due to the 7-dB-loss V-band cable, the effective Tx power to an-

tenna is reduced to

4 dBm and the received signal will have an extra 7-dB loss (from the antenna to QC). If the RF sensor chip can be directly mounted with the input port of the antenna, it can greatly reduce the equivalent 14-dB cable loss (transmitting and receiving path). According to the two-way path loss formula in (1), note that if the distance is doubled, the two-way path loss would be increased about 12 dB. In other word, the vital-signs detection distance can then be expected to be doubled for the developed radar sensor chip. From the above points, it should be able to conclude that for the CMOS radar sensor chip (with an I/Q two-channel receiver and a transmitting power dBm) the detection distance can

KUO et al.: FULLY INTEGRATED 60-GHz CMOS DIRECT-CONVERSION DOPPLER RADAR RF SENSOR

Fig. 20. Measurement scenarios for the vital-signs detection of the radar RF sensor chip.

TABLE III PERFORMANCE COMPARISON

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360 PS, has demonstrated the successful clutter cancellation to greatly increase the detecting sensitivity of weak human vital signals. The experimental measurements show clearly recorded waveforms of the heartbeat (1.1 Hz) and breathing signals (0.4 Hz) for a human subject 75 cm away, when the clutter is cancelled to a low power level 35 dBm . The measured results have been compared with the reported state-of-the-art work and show a good performance. It is also noted that if the RF sensor chip can be directly mounted with the input port of the antenna, it can greatly reduce the equivalent 14-dB cable loss (transmitting and receiving path) and the vital-signs detection distance can be expected to be much increased. The presented integrated 60-GHz CMOS vital-sign Doppler radar RF sensor can be incorporated into a handheld device (such as a smartphone), which will be very useful for the wireless healthcare application and remote physiological monitoring system. ACKNOWLEDGMENT The authors would like to thank the Chip Implementation Center (CIC), National Science Council, Hsin-Chu, Taiwan, for supporting the Taiwan Semiconductor Manufacturing Company (TSMC) CMOS process and Bo-Jiang Technology, Tainan, Taiwan, for supporting the 1.85-mm end-launch connectors. The authors are also grateful to Prof. T.-H. Huang, Deptartment of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan. and Prof. F.-L. Lin, Department of Electronic Engineering, Southern Taiwan University of Science and Technology, Tainan, Taiwan, for the valuable suggestions and measurement support. REFERENCES

increase to 1.5 m if without the 7-dB cable loss. Moreover, if the transmitting effective isotropic radiated power (EIRP) of 13 dBm is increased by 20 dB to 33 dBm (same as in [8]), the detection distance can be increased from 1.5 m to at least 3 m (possibly 5 m). Fig. 20 shows a photograph of measurement scenario for the human vital-signs detection of the radar RF sensor chip. Table III shows the performance comparison, a longer detection distance (75 cm with a 7-dB-loss connected cable) can be achieved, which is 2.5 longer than that (30 cm) of the previously reported state-of-the-art work [9]. IV. CONCLUSION This paper has presented a 60-GHz CMOS direct- conversion Doppler radar RF sensor fabricated in 90-nm technology for single-antenna noncontact human vital-signs detection. The sensor chip consumes 217 mW of dc power with a chip size of 2 mm 2 mm. The detailed circuit operation principles (including the high-isolation QC and clutter canceller) have also been addressed. A compact and high-isolation CMOS QC has been designed to mitigate the Tx leakage for the single-antenna radar purpose. The clutter canceller, consisted of a VGA and a

[1] K.-M. Chen, D. Misra, H. Wang, H.-R. Chuang, and E. Postow, “An X-band microwave life-detection system,” IEEE Trans. Biomed. Eng., vol. BME-33, no. 7, pp. 697–702, Jul. 1986. [2] H.-R. Chuang, Y.-F. Chen, and K.-M. Chen, “Automatic clutter-canceller for microwave life-detection system,” IEEE Trans. Instrum. Meas., vol. 40, no. 4, pp. 747–750, Aug. 1991. [3] K.-M. Chen, Y. Huang, J. Zhang, and A. Norman, “Microwave life-detection systems for searching human subjects under earthquake rubble and behind barrier,” IEEE Trans. Biomed. Eng., vol. 27, no. 1, pp. 105–114, Jan. 2000. [4] A. D. Droitcour, O. Boric-Lubecke, V. M. Lubecke, and J. Lin, “0.25 m CMOS and BiCMOS single-chip direct-conversion radars for remote sensing of vital signs,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2002, pp. 348–349. [5] A. D. Droitcour, O. Boric-Lubecke, V. M. Lubecke, J. Lin, and G. T. A. Kovacs, “Range correlation and I/Q performance benefits in single-chip silicon Doppler radars for noncontact cardiopulmonary monitoring,” IEEE Trans. Microw. Theory Techn., vol. 52, no. 3, pp. 838–848, Mar. 2004. [6] C. Li, X. Yu, C.-M. Lee, D. Li, L. Ran, and J. Lin, “High-sensitivity software-configurable 5.8-GHz radar sensor receiver chip in 0.13- m CMOS for noncontact vital sign detection,” IEEE Trans. Microw. Theory Techn., vol. 58, no. 5, pp. 1410–1418, May 2010. [7] J. H. Choi and D. K. Kim, “A remote compact sensor for the realtime monitoring of human heartbeat and respiration rate,” IEEE Trans. Biomed. Circuits Syst., vol. 3, no. 3, pp. 181–188, Jun. 2009. [8] H.-R. Chuang, H.-C. Kuo, F.-L. Lin, T.-H. Huang, C.-S. Kuo, and Y.-W. Ou, “60-GHz millimeter-wave life detection system (MLDS) for noncontact human vital-signal monitoring,” IEEE Sensors J., vol. 12, no. 3, pp. 602–609, Mar. 2012. [9] T.-Y. J. Kao, Y. Yan, T.-M. Shen, A. Y.-K. Chen, and J. Lin, “Design and analysis of a 60-GHz CMOS micro-radar system-in-package for vital-sign and vibration detection,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 4, pp. 1649–1659, Apr. 2013.

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[10] H.-C. Kuo, C.-C. Chou, C.-C. Lin, C.-H. Yu, T.-H. Huang, and H.-R. Chuang, “A 60-GHz CMOS direct-conversion radar RF sensor with clutter canceller for single-antenna noncontact human vital-signs detection,” in IEEE RFIC Tech. Dig., May 2015, pp. 35–38. [11] L. Chioukh, H. Boutayeb, D. Deslandes, and K. Wu, “Noise and sensitivity of harmonic radar architecture for remote sensing and detection of vital signs,” IEEE Trans. Microw. Theory Techn., vol. 62, no. 9, pp. 1847–1855, Sep. 2014. [12] F.-K. Wang et al., “A novel vital-sign sensor based on a self-injectionlocked oscillator,” IEEE Trans. Microw. Theory Techn., vol. 58, no. 12, pp. 4112–4120, Dec. 2010. [13] C.-Y. Kim, J.-G. Kim, and S. Hong, “A quadrature radar topology with TX leakage canceller for 24-GHz radar applications,” IEEE Trans. Microw. Theory Techn., vol. 55, no. 7, pp. 1438–1444, Jul. 2007. [14] C. A. Balanis, Advanced Engineering Eletromagnetics. New York, NY, USA: Wiley, 1989. [15] H.-C. Kuo and H.-R. Chuang, “Investigation of carrier frequency effect on detection performance of Doppler sensor systems for noncontact human vital-signs sensing,” in 8th Int. Med. Inform. Commun. Technol. Symp., Mar. 2014, pp. 1–4. [16] H.-H. Hsieh, Y.-H. Chen, and L.-H. Lu, “A millimeter-wave CMOS LC-tank VCO with an admittance-transforming technique,” IEEE Trans. Microw. Theory Techn., vol. 55, no. 9, pp. 1854–1861, Sep. 2007. [17] S. K. Cheung, T. P. Halloran, W. H. Weedon, and C. P. Caldwell, “MMIC-based quadrature hybrid quasi-circulators for simultaneous transmit and receive,” IEEE Trans. Microw. Theory Techn., vol. 58, no. 3, pp. 489–497, Mar. 2010. [18] S. Kim, H. -C. Kim, D. -H. Kim, S. Jeon, M. Kim, and J. -S. Rieh, “58–72 GHz CMOS wideband variable gain low-noise amplifier,” Electron. Lett., vol. 47, pp. 904–906, Aug. 2011. [19] H. Zarei, C. T. Charles, and D. J. Allstot, “Reflective-type phase shifters for multiple antenna transceivers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 8, pp. 1647–1656, Aug. 2007. [20] J.-C. Wu, T.-Y. Chin, S.-F. Chang, and C.-C. Chang, “2.45-GHz CMOS reflection-type phase-shifter MMICs with minimal loss variation over quadrants of phase-shift range,” IEEE Trans. Microw. Theory Techn., vol. 56, no. 10, pp. 2180–2189, Oct. 2008. [21] H.-C. Kuo, H.-L. Yue, Y.-W. Ou, C.-C. Lin, and H.-R. Chuang, “A 60-GHz CMOS sub-harmonic RF receiver with integrated on-chip artificial- magnetic-conductor Yagi-antenna and balun-bandpass-filter for very-short- range gigabit communications,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 4, pp. 1681–1691, Apr. 2013. [22] C. Li and J. Lin, “Random body movement cancellation in Doppler radar vital sign detection,” IEEE Trans. Microw. Theory Techn., vol. 56, no. 12, pp. 3143–3152, Dec. 2008. Hsin-Chih Kuo (S’10–M’15) received the B.S.E.E degree from Feng Chia University, Taichung, Taiwan, in 2006, and the M.S.E.E and Ph.D. degrees from National Cheng Kung University, Tainan, Taiwan, in 2008 and 2015, respectively. He is currently with the Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan, as a Principal Engineer. His research interests include millimeter-wave (MMW) RF integrated circuit (RFIC) design, microwave detection system, and RF system design. Dr. Kuo was a recipient of the Student Travel Grant Award (STGA) of the 2012 IEEE Solid-State Circuit Conference (ISSCC) and Honorable Mention Award of the Student Research Preview (SRP) of the 2015 IEEE ISSCC.

Chien-Chih Lin (S’11) received the B.S.E.E. degree from National University of Tainan, Tainan, Taiwan, in 2011, and the M.S.E.E. degree from National Cheng Kung University, Tainan, Taiwan, in 2014. His research interest is RF/millimeter-wave (MMW) power amplifier circuit design.

Chun-Han Yu (S’12) received the B.S.E.E. degree from the National University of Kaohsiung, Kaohsiung, Taiwan, in 2012, and the M.S.E.E. degree from National Cheng Kung University, Tainan, Taiwan, in 2014. His research interest is millimeter-wave (MMW) passive element circuit design.

Pei-Hua Lo received the B.S.E.E degree from National Chung Cheng University, Chiayi, Taiwan, in 2010, and the M.S.E.E degree from National Cheng Kung University, Tainan, Taiwan, in 2012. Her research interest is millimeter-wave (MMW) amplifier design.

Jhin-Ying Lyu received the B.S.E.E degree from National Kaohsiung University, Kaohsiung, Taiwan, in 2010, and the M.S.E.E degree from National Cheng Kung University, Tainan, Taiwan, in 2012. Her research interest is RF/millimete-wavwe (MMW) passive element circuit design.

Chien-Chang Chou (S’15) received the B.S.E.E. and M.S.E.E degrees from National Sun Yat-sen University, Kaohsiung, Taiwan, in 2004 and 2006, respectively, and is currently working toward the Ph.D. degree at National Cheng Kung University, Tainan, Taiwan. He is currently with the Department of Electrical Engineering, Institute of Computer and Communication Engineering, National Cheng Kung University. His research interests include millimeter-wave (MMW) RF integrated circuit (RFIC), antenna, and RF system design.

Huey-Ru Chuang (SM’06) received the B.S.E.E. and M.S.E.E. degrees from National Taiwan University, Taipei, Taiwan, in 1977 and 1980, respectively, and the Ph.D. degree in electrical engineering from Michigan State University, East Lansing, MI, USA, in 1987. From 1987 to 1988, he was a Post-Doctoral Research Associate with the Engineering Research Center, Michigan State University. From 1988 to 1990, he was with the Portable Communication Division, Motorola Inc., Ft. Lauderdale, FL, USA. Since 1991, he has been with the Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, where he is currently a Professor with the Institute of Computer and Communication Engineering, Department of Electrical Engineering, National Cheng Kung University. His research interests include microwave/millimeter-wave circuits and systems, RF integrated circuits (RFICs) and antenna design for wireless communications, electromagnetic computation and applications, and microwave/millimeter-wave communication and detection systems.

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A 65-nm CMOS Low-Power Impulse Radar System for Human Respiratory Feature Extraction and Diagnosis on Respiratory Diseases Shao-Ting Tseng, Yu-Hsien Kao, Chun-Chieh Peng, Jinn-Yann Liu, Shao-Chang Chu, Guo-Feng Hong, Chi-Hsuan Hsieh, Kung-Tuo Hsu, Wen-Te Liu, Yuan-Hao Huang, Member, IEEE, Shi-Yu Huang, Senior Member, IEEE, and Ta-Shun Chu, Member, IEEE

Abstract—This paper presents a radar system for extracting human respiratory features. The proposed radar chip comprises three major components: a digital-to-time converter (DTC), a transmitter, and a receiver. The all-digital standard cell-based DTC achieves a timing resolution of 10 ps on a 100-ns time scale, supporting a range-gated sensing process. The transmitter is composed of a digital pulse generator. The receiver comprises a direct-sampling passive frontend for achieving high linearity, an integrator for enhancing the signal-to-noise ratio, and a successive approximation register analog-to-digital converter for signal quantization. A fully integrated CMOS impulse radar chip was fabricated using 65-nm CMOS technology, and the total power consumption is 21 mW. In the backend, a real-time digital signal-processing platform captures human respiratory waveforms via the radar chip and processes the waveforms by applying a human respiratory feature extraction algorithm. Furthermore, a clinical trial was conducted for establishing a new diagnosis workflow for identifying respiratory diseases by the proposed wireless sensor system. The proposed system was validated by applying an adaptive network-based fuzzy inference system and support vector machine algorithm to the clinical trial results. These algorithms confirmed the effectiveness of the proposed system in diagnosing respiratory diseases. Index Terms—Biomedical applications, CMOS, digital signal processing (DSP), radar systems, sensors. Manuscript received July 31, 2015; revised December 05, 2015 and February 16, 2016; accepted February 20, 2016. This work was supported in part by the Ministry of Science and Technology, MOST 103–2220-E-007–005 and in part under a NOVATEK Doctoral Fellowship. This paper is an expanded version from the IEEE RFIC Symposium, Phoenix, AZ, USA, May 17–19, 2015. S.-T. Tseng, Y.-H. Kao, C.-C. Peng, J.-Y. Liu, S.-C. Chu, C.-H. Hsieh, Y.-H. Huang, S.-Y. Huang, and T.-S. Chu are with the Department of Electrical Engineering, National Tsing Hua University, Hsinchu City 300, Taiwan (e-mail: [email protected]). G.-F. Hong was with the Department of Electrical Engineering, National Tsing Hua University, Hsinchu City 300, Taiwan. He is now with Mediatek, Hsinchu City 300, Taiwan. K.-T. Hsu was with the Department of Electrical Engineering, National Tsing Hua University, Hsinchu City 300, Taiwan. He is now with the ASolid Technology Company Ltd., Hsinchu 300, Taiwan. W.-T. Liu is with the Division of Pulmonary Medicine, Department of Internal Medicine, Shuang Ho Hospital, Taipei Medical University, New Taipei City 235, Taiwan, the School of Respiratory Therapy, College of Medicine, Taipei Medical University, Taipei 110, Taiwan, the Department of Engineering Science, National Cheng Kung University, Tainan 701, Taiwan, the Sleep Research Center, Taipei Medical University Hospital, Taipei Medical University, Taipei 110, Taiwan, and also with the Sleep Center, Shuang Ho Hospital, Taipei Medical University, New Taipei City 235, Taiwan. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.

I. INTRODUCTION

R

ECENTLY, the prevalence of contactless monitoring systems, such as wireless sensing systems, in healthcare services is increasing. The main objective of this study was to develop a radar system for monitoring human respiratory activities, which reflect the status of the body and serve as indicators of major respiratory diseases. Human respiratory activities can be considered biomedical signals, and such activities can be observed directly by measuring the volume of flowing air by using spirometers or indirectly by measuring the respiratory-induced vibrations of the human body by using radar systems. Radar systems can be mainly divided into two categories: continuous-wave Doppler radar and impulse radio ultra-wideband (IR-UWB) radar systems. Continuous-wave Doppler radar systems are widely adopted in wireless sensor applications and can accurately detect the velocity of a target [1]. In previous experimental studies, a wireless heartbeat-sensing system and vital-sign detection system have been developed [2]–[6]. However, using continuous-wave radar systems for distinguishing respiration activities from more than one person is difficult. Frequency-modulated continuous-wave radar systems, which are improved continuous-wave radar systems, apply wide-bandwidth transceivers to sense both the position and velocity of targets [7], [8] according to the frequency deviation between transmitted and received signals. Compared with continuous-wave radar systems, IR-UWB radar systems are developed to sense both the position and vibration of targets [9]–[11]. Due to the superiority of short-duration pulses, impulse radar systems facilitate determining depth information and distinguishing among scattered waves reflected by various objects. IR-UWB radar systems comprise three detection schemes, namely, power detection [12]–[15], cross-correlation detection [16], [17], and waveform capture detection schemes. However, only the waveform capture detection scheme provides the most primitive respiratory waveforms for the backend digital signal processing (DSP). To provide full freedom in DSP, received signals should be captured completely. To capture waveforms, the simplest approach is to implement a direct Nyquist sampling topology with an extremely high sampling frequency [18], [19]. However, a Digital Object Identifier 10.1109/TMTT.2016.2536029

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high sampling frequency leads to high power dissipation, which is unfavorable for biomedical sensing applications. Therefore, equivalent sampling technology was adopted by reducing latency to mitigate the power consumption problem[9]–[11], [20] which is permissible in biomedical signal sensing applications. Moreover, because of the wide bandwidth feature of IR-UWB radar, receivers must have high linearity to endure interference from non-targeted sources. Therefore, a radar system involving passive frontend architecture and the equivalent sampling waveform capture detection scheme is proposed. For the proposed radar system containing a single receiver channel and equivalent sampling detection scheme, the timing circuitry plays a vital role in range sensing, and its timing resolution is used to determine the scanning range resolution. The timing circuitry of the proposed radar system is superior to those of previous designs [9], [10], achieving a 10-ps timing resolution at a 10-MHz repetition frequency, which corresponds to a range scanning resolution of 1.5 mm in radar operation. Moreover, the timing circuitry and transmitter demonstrate various advantages such as technology scalability and modularization because they are synthesized using an all-digital standard-cell design workflow. In the backend, a real-time DSP platform obtains human respiratory waveforms through data from a radar chip. This platform then processes the received waveforms by applying a human respiratory feature extraction algorithm to parameterize and compress them to mitigating data storage issues. Moreover, the parameterized waveforms were used in constructing a new diagnosis flow for respiratory diseases in clinical trials, and the proposed wireless sensing system was verified. The current study is an extension of a previous study [21]. In this study, emphasis was placed on system-level design parameters, noise calculation, and link budget analysis of the proposed impulse radar system; furthermore, the system operation and results of a clinical trial are presented. This paper is organized as follows. Section II presents a brief preview of the proposed radar system, and describes the system level design parameters, system noise analysis, and link budget. Section III presents the detailed design of the building blocks. Section IV briefly describes the backend DSP algorithm. The experimental and clinical trial results are summarized in Section V, and a conclusion is presented in Section VI. II. SYSTEM-LEVEL PARAMETERS Before the system parameter analysis and circuit implementation are described, a complete description of the radar system is presented to provide a clear basis for the following section. Fig. 1 shows the architecture of the proposed radar system. In the proposed radar chip, the timing circuitry provides two clock signals with programmable timing delays for the transmitter and receiver as trigger signals. To monitor human respiratory waveforms, the time of arrival (TOA) of a signal is measured by scanning timing delays to identify the position of a target. Subsequently, respiration-induced vibration waveforms of the human body are measured by the receiver and quantized by an analog-to-digital converter (ADC) and then subjected to backend DSP. Next, backend field-programmable

Fig. 1. Architecture of the proposed radar system.

gate-array (FPGA) hardware and a computer apply a human respiratory feature extraction algorithm to parameterize and compress the received waveform data. A. Scanning Range and Minimum RX Signal-to-Noise Ratio To meet the requirements for monitoring human respiratory features in an indoor space (e.g., bedroom or hospital consulting room), the scanning range of the radar system is set to 0.4–4 m. Furthermore, to minimize the power consumption to ensure long-term healthcare applications, the design was based on a tradeoff between power consumption and other parameters to lower the power consumption while maintaining the system in an effective operating mode within the target application range. To derive reliable quantized signals for backend DSP to extract human respiratory features, the minimum allowable signal-to-noise ratio at the ADC output is set to 10 dB, (1) The is calculated using (1), where is the carrier wavelength, is the range to the object, is the noise figure of the receiver chain, is the Boltzmann constant, is room temperature in Kelvin, is the frontend bandwidth, is the atmospheric loss, is the radar cross section of the object, and is the power transmitted by the transmitter; in addition, and are the transmitter and receiver antenna gain, respectively, and is the improvement in the signalto-noise ratio (SNR) at the output of the ADC, which is achieved by integrating received signals in several iterations [11]. In the denominator of (1), the value of parameter is approximately 173.8 dBm. Since the target range is set to 0.4–4 m and the carrier frequency of the transmitted pulse signal is 1 GHz, the path loss term ranges from 27.5 to 67.5 dB. Furthermore, because the receiver applies a direct-sampling technique, the frontend bandwidth of the designed direct sampler is set to 10 GHz (100 dB). The atmospheric loss term is assumed to be negligible (0 dB) in the target application because the signal paths are short. In the numerator of (1), the radar cross section of the object is nearly 10 dB 0.1 m for the surface area of an adult’s chest. The transmitter and receiver antenna gains, and , are approximately 5 dB. The power transmitted from the transmitter buffer is nearly 4 dBm. For , because

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Fig. 4. Lumped model of the direct sampler in the tracking mode.

Fig. 2. Link-budget analysis for tolerable

under 10-dB

(2)

.

C. Noise-Figure Calculation

Fig. 3. General link-budget analysis for

and

.

humans exhibit a low respiratory rate and because the target under test is quasi-static relative to the indoor environment, the SNR can be considerably improved by conducting an integration operation by the integrator without losing sensitivity to the target’s motion [11]. Thus, each ADC output signal is obtained by integrating the input signals by 1024 times, thus improving the SNR by 30.1 dB. As shown in Fig. 2, to ensure that the radar system operates effectively dB , the maximum tolerable receiver noise figure is set to approximately 22.4 dB. This provides enough margin in design tradeoffs between the noise figure and power, and between the noise figure and linearity to achieve a direct-sampling receiver architecture featuring low power, high linearity, and no frontend low-noise amplifier.

To enable radar systems to operate effectively in a target application range in addition to maintaining their power consumption at a low level, a design tradeoff among noise figure, linearity, and power consumption should be carefully evaluated. As presented in the following section, the noise figure of the proposed direct-sampling receiver was derived, and the following receiver chain design was based on the derived results. To derive the noise figure of the direct-sampling receiver, first consider a lumped model of a direct sampler operating in a tracking mode. Fig. 4 illustrates the first track-and-hold stage of the direct sampler, where is the source impedance of the antenna, is the input-matching inductor, is the shunt-peaking inductor, and is the track-and-hold capacitance; and are the track-and-hold switch and are used to perform input matching. When the sampler operates in the tracking mode, and act as resistors and , respectively. For simplicity, the inductors and are first ignored and is used to represent the sum of and in the derivation (3). Subsequently, the single-sided power spectral density (PSD) of thermal noise contributed by at is expressed as shown in (4), and the total integrated noise power is, thus, (5), (3) (4)

B. Link-Budget Analysis Fig. 3 illustrates a link-budget analysis. Since the full scale (FS) value at the ADC input power is 10 dBm, the dynamic range (DR) value for a 10-bit SAR ADC is 60 dB; therefore, the quantization noise (QN) level is 50 dBm. To render QN negligible compared with the thermal noise (less than 0.1-dB contribution), a 16-dB margin is reserved. The minimum power at the ADC input should thus be dBm dB dB dBm. Since the maximum power transmitted at the transmitter is 4 dBm and the target application range is 0.4–4 m, the minimum and maximum signal powers received by the receiver can be calculated by radar (2) and would be 71.5 and 31.5 dBm, respectively. Therefore, the minimum gain of the receiver chain is 41.5 dB and maximum gain is at least 47.5 dB,

(5) Equations (4) and (5) are derived for a scenario involving all-closed and , while the normal operation of a trackand-hold circuit comprises tracking and holding modes. Given the frequency of a sampling clock , period , and duty cycle for a tracking mode , the time interval for the tracking mode is and that for the holding mode is . In Fig. 5, the noise power distributed on in the entire operation of the track-and-hold circuit is separated into two parts: tracking mode noise and holding mode noise. For tracking mode noise , because the noise source is white noise and the track-and-hold circuit switches at a fixed frequency , the tracking mode noise PSD is a cyclostationary process that can

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Fig. 5. Noise power distributed on viewed as sum of tracking mode noise : noise with all-closed and , : impulse and holding mode noise. : tracking mode noise, : impulse-train sampled noise, : train, : sum of tracking and sampled noise. holding mode noise,

be calculated by multiplying (4) by a factor of the duty cycle (6), and the total noise power is (7), (6) (7) The holding mode noise can be regarded as noise sampled at the end of the tracking mode and held in the holding mode. First, consider an impulse-train sampling process with an impulse train , which results in the replicated PSD of aliasing together with a frequency interval of (Fig. 6). As shown in Fig. 6, the effective noise bandwidth is applied for approximating the aliasing effect and can be calculated by considering the area as a rectangular area with the height of the noise PSD at low frequency (8). Furthermore, the doublesided noise PSD (Fig. 6) is also derived for ensuing calculation. Subsequently, the aliasing effect can be calculated by approximating the average number of aliasing events within the frequency interval as (9), which also implies that the sampling process folds high-frequency noise into the baseband. Therefore, double-sided noise PSD from the impulsetrain sampling process can be approximated as times of at low frequency scaled by (10), and the single-sided form is shown in (11), (8) (9)

(10) (11) The holding mode noise can be obtained by reconstructing the sampled signal by applying a zeroth-order holding model according to the results of the impulse-train sampling process. Equation (12) shows the rectangular function used to reconstruct in both the time and frequency domains with a period

Fig. 6. Double-sided noise PSD with effective noise bandwidth with interval of sampling clock frequency .

aliasing

, pulse width , and unit height. The holding mode noise can be obtained by convoluting with the rectangular function, resulting in a multiplication in the frequency domain, as shown in (13), where is the holding mode noise PSD. Moreover, the total power is calculated as (14), if otherwise

(12)

(13) (14) According to the calculated tracking mode noise PSD and holding mode noise PSD , the total noise PSD contributed within the track-and-hold operation is the sum of and (15), and the total noise power is (16), which turns out to be identical to the result of all-closed and , (15) (16) The noise power contributed by on during the trackand-hold operation is calculated as (16). With similar calculation, the total noise power contributed by , , and on can be calculated as shown in (17), (17) The noise figure of the receiver chain can be calculated according to the preceding derivations. Fig. 7 illustrates blocks contributing primary noise to the receiver chain, where and are input-referred noise of the unit-gain buffer and programmable-gain amplifier, respectively. The receiver noise figure can thus be calculated as shown in (18),

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Fig. 7. Noise contribution in receiver chain. Fig. 8. Radar operation based on TOA measurement.

(18) Inductors and shown in Fig. 4 are ignored in the preceding derivation. In this case, the transfer function for the noise contributed by and is (19), and that for the noise contributed by is (20). The indefinite integrals of the two transfer functions (19) and (20) can be easily derived. However, if inductors and are included, (19) and (20) are expanded to (21) and (22), respectively, and the corresponding indefinite integrals cannot be derived intuitively. Therefore, the integrated noise power is calculated by applying numerical calculation to estimate the receiver noise figure,

(19)

Fig. 9. Block diagram of the proposed DTC, where buffers and control unit, control signals are omitted.

,

, and

are tri-state

and a target. The operation of the proposed radar system for extracting human respiratory features is mainly based on measuring the TOA of signals. To achieve high resolution in TOA measurements, timing circuits that can provide transmitter and receiver clock signals with programmable delays at high resolutions are required. Therefore, a digital-to-time converter (DTC) is implemented in the proposed radar system to satisfy this requirement, (23)

(20)

(21)

(22) With the designed parameters: pH, pH, , , and fF and both the in-band and are approximately 48 dBm, the calculated is approximately 19.3 dB, which is less than the maximum tolerable value of 22.4 dB. III. CIRCUIT SCHEMATIC AND IMPLEMENTATION A. Digital-to-Time Converter For impulse radar systems, TOA is an essential parameter that can be used to measure the distance between a radar system

As illustrated in Fig. 8, the DTC provides two triggering signals to TX and RX with a delay difference that can be adjusted at a tuning resolution of 10 ps on a time scale of 100 ns. The total 10 000 tuning delays can be split into 100 coarse codes with a 1-ns resolution and 100 fine codes with a 10-ps resolution. Fig. 9 shows a block diagram of the proposed DTC, which can be divided into two parts: coarse tuning blocks (for tuning coarse delays) and fine tuning blocks (for tuning fine delays). The total time delay is the sum of fine and coarse delays. The two parts are mainly composed of all-digital phase-locked loops (ADPLLs), frequency dividers, and a delay-locked loop (DLL). Moreover, the entire DTC was synthesized through a standard cell and APR process. A 100-MHz off-chip clock signal is used as the reference for the DTC. The DTC outputs are two 10-MHz clock signals for TX and RX, respectively. The delay between them is designed to have a 10-ps resolution on a 100-ns time scale. In the generation of a coarse delay, is locked by a reference signal to provide a 1-GHz signal to the coarse tuning block (Fig. 10). The coarse tuning block contains two counters counting up to 100; however, one of these counters initiates counting from 1, whereas the other initiates counting from a programmable number within the range of 1–100. The two counters act as frequency dividers of dividing number 100, and output two 10-MHz clock signals, namely, and , respectively. Therefore, various coarse tuning delays with multiples of the period (1 ns) between and

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Fig. 13. Total delay between clock signals to TX and RX. Fig. 10. Coarse tuning block diagram.

Fig. 14. Block diagram of the radar receiver.

Fig. 11. Generation of coarse delay by using different

values.

Fig. 12. Generation of fine delay.

can be generated by determining distinct initial counting points of , and the variable delay can be expressed as ns (Fig. 11). According to the preceding procedures, a programmable coarse delay with a 1-ns resolution on a 100-ns time scale can be achieved. For generating fine delays, a 1-GHz clock signal is derived from . As shown in Fig. 12, the 1-GHz signal is first sent to a frequency divider with dividing number that can be programmed from 100 to 200. Subsequently, the output of the frequency divider is sent to with a dividing number of 100 to generate . The output frequency of is thus 1 GHz . Accordingly, its period is 1 ns . Next, to generate a fine delay, is further used to lock a DLL. The DLL contains tunable delay elements (TDEs), a phase detector, and a controller used to lock the loop. As mentioned, the period of is 1 ns ; because can be programmed from 100 to 200, when the DLL is locked by , the TDEs demonstrate programmable delays ranging from 1 to 2 ns with a 10-ps resolution.

The proposed DTC has two operating phases, namely, a calibration phase and normal phase. In the calibration phase, the divider chain is programmed for fine tuning delays, and is activated to provide signals. Tristate buffer then delivers to calibrate the TDEs in the DLL, whereas and are turned off. Concurrently, the desired initial points at which a coarse delay is provided to the two triggering signals is determined through control logic. After the TDEs are calibrated, the controller turns off and turns on and , switching the converter into the normal operating phase. In the normal phase, the DLL is turned off, serving as delay elements with the delay defined in the calibration phase. Tristate buffer then delivers to the DLL, which further produces . Subsequently, and are used to activate TX and RX. As shown in Fig. 13, with the coarse tuning block, delay between and is ns, and with the TDEs of the DLL, delay between and is 1 ns . The total delay between and is thus the sum of the coarse and fine delays. Through a simple algebraic substitution, the total delay can be rewritten as ns. Thus, the DTC achieves a total delay with a 10-ps resolution on a 100-ns time scale. B. Receiver The receiver exhibits a passive sampler-first frontend architecture (Fig. 14). The passive frontend architecture features advantages of high linearity and low power consumption. In addition, because human body vibration signals generated during respiration are low-frequency signals, an equivalent sampling technique can be applied [9]–[11], [20] without distorting a target’s movement information. In signal reception operations, received signals are directly sampled by a sample-and-hold circuit comprising track-andhold circuits, buffers, and boot-strapped circuits. After the direct sampling process, a programmable gain amplifier (PGA)

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Fig. 16. Impulse waveform synthesized using pulse window. Fig. 15. Circuit schematic of the passive direct sampler.

provides adaptive gain to compensate for the frontend loss, and an integrator subsequently enhances the SNR. Finally, the ADC quantizes the sampled signals for use in backend DSP. Fig. 15 illustrates a passive direct sampler that operates in two modes: a tracking mode and holding mode. In the tracking mode, is high and the switches ( and ) act as resistors to perform input matching. Additional switches ( and ) are adopted to ease the tradeoff between insertion loss and input matching. In addition, inductors ( and ) are used to execute a shunt peaking technique to increase the bandwidth, and additional inductors ( and ) are used to enhance high-frequency input matching. There is an additional switch . This switch with the switch pairs before the integrator together implement a correlated double-sampling technique to remove the offset for ensuring the effective operation of the ADC. In the holding mode, is low and the previously sampled signals are retained and passed to the next stage of the track-and-hold circuit by a unit-gain buffer. A bootstrap circuit is also applied to further increase the linearity. Moreover, a dummy block with complementary timing control is included to ensure continual maintenance of the input matching condition (Fig. 15). Since the received signals are short-duration pulses, the design bandwidth of the first RF track-and-hold circuit is set to 10 GHz to meet the requirements for sensing short-duration pulses; this is achieved by using a shunt-peaking technique. To ensure the effective operation of the radar system within the target application range of 0.4–4 m, the maximum tolerable noise figure is set to 22.4 dB; moreover, is derived using the approach described in the previous section and can be approximated by conducting a numerical calculation. According to the noise figure, power, and tolerable settling time for the second track-and-hold circuit, the design bandwidth of the unit-gain buffer after the first RF track-and-hold circuit is set to 40 MHz (and vice versa for the following PGA). In addition, to meet the specifications for the maximum and minimum gain range described in the link-budget analysis and left margin for performance degradation of the ADC after the manufacturing process, the combined gain range of the PGA and integrator is set to 0–80 dB. In summary, the proposed receiver has a passive sampler-first frontend architecture and exhibits high linearity and low power consumption.

Fig. 17. Four segments of linear waves and one period of respiration.

C. Transmitter As illustrated in Fig. 16, to synthesize impulse waveforms, the 10-MHz signal from the proposed DTC is used as a reference signal in another ADPLL for generating a 1-GHz clock signal for the transmitter [22]. Consequently, a 1-ns pulse . The impulse waveform window can be obtained using is subsequently synthesized using this pulse window and the 1-GHz signal. The synthesized short-duration impulse waveform is transmitted through a buffer chain and antenna. IV. HUMAN RESPIRATORY FEATURE EXTRACTION ALGORITHM Human respiration comprises four stages, namely, inspiration, inhalation-holding, expiration, and exhalation-holding. Since the respiratory frequency in humans is low with uncomplicated waveforms, in the present study, the four stages of human respiration were parameterized in the DSP backend by using a human respiratory feature extraction algorithm [23]. The stages were parameterized using four segments of linear waves, which can provide sufficient respiratory features (Fig. 17). Parameterizing respiratory waveforms facilitates meeting data storage requirements because model-based compressed respiratory segments are stored instead of original sampled waveform data. Moreover, processing the parameterized waveforms in the DSP backend is easy, and the waveforms can be used in diagnosing respiratory diseases. Fig. 18 illustrates the backend DSP hardware architecture [23]. Digital signals from the radar chip are delivered to a Xilinx Spartan-6 LX150 FPGA board for data streaming in a real-time measurement environment. Subsequently, a chirp-z transform block estimates the signal frequency and sends one period of the respiration signal to the correlator block to conduct data compression and feature extraction by searching for the optimal

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Fig. 18. Waveform parameterization architecture in the DSP backend.

Fig. 20. DTC measurement setup.

Fig. 19. Chip microphotograph of the proposed radar system.

fitted linear segments by using an iterative correlation search algorithm. Next, a four-segment linear wave (FSLW) generator block generates various possible linear waveforms. The parameter generator block then provides the linear waveform feature parameters that characterize the slopes of the segments. The FSLW wave energy block and square-root/reciprocal block assists the correlator block in choosing the most suitable linear waveforms for analyzing the period of respiratory signals. V. MEASUREMENT RESULTS Fig. 19 shows a chip microphotograph of the fully integrated radar chip. It occupies a total area of 1.45 mm 1.4 mm and is fabricated using a 65-nm CMOS technology. Fig. 20 depicts the DTC measurement setup. The measurement was conducted using a Tektronix TDS7404 timing scope. In this measurement, a clock signal transmitted to RX as the trigger signal is probed at , and a clock signal sent to TX is probed at . Subsequently, the time difference, observed at rising edges, between and , was measured with different timing codes. The measured differential nonlinearity (DNL) 15 4 and integral nonlinearity (INL) 12 13 of the DTC are shown in Fig. 21, where the LSB is 10 ps. The measured DNL and INL are worse than previous works. The main reason lies in the nonlinearity of the TDEs in the DLL. The nonlinearity of the TDEs was caused by the asymmetric layout from the APR process, introducing non-ideal effects and nonlinearity to the TDEs. This might be eased by customizing the critical delay elements in the DLL

Fig. 21. Measured: (a) DNL where LSB is 10 ps.

15

4 and (b) INL

12

13 of the DTC

without the APR process. Another reason is clock frequency stability. Compared to the previous two PLL-based DTCs [9], [10], this work is based on the ADPLL, which naturally has worse jitter performance. Therefore, the DTC linearity might be degraded due to worse frequency stability. Fig. 22 shows the receiver signal-to-noise distortion ratio (SNDR) versus the various input power levels measured using an Agilent E440A with an integration time of 51.2 s corresponding to 512 pulses. The SNDR degraded after an input power of 20 dBm. This degradation was induced by the saturation of the PGA. Though linearity of this work should be better than previous works [9], [10] due to the adopted

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Fig. 22. SNDR versus different input power levels with 1-GHz input frequency and integration time of 51.2 s corresponding to 512 pulses for the receiver.

Fig. 23. Impulse waveform transmitted by the transmitter.

Fig. 25. Measured respiratory waveforms (blue solid line) and FSLW fitting curves (red dashed line) from different ranges: (a) 1, (b) 2, and (c) 4 m, where (a) and (b) are with a 68-dB RX gain and (c) is with an 80-dB RX gain.

Fig. 24. Power spectrum of the transmitted impulse waveforms measured with resolution bandwidth of 0.1 MHz.

passive frontend, the measured maximum receiver SNDR, 35 dB, is about 5 dB worse compared to previous works. This is caused by worse noise performance of the passive frontend compared to the active one. Thus, the SNDR, which takes both noise performance and linearity into account, would be worse. Fig. 23 illustrates the impulse waveform transmitted by the transmitter measured using the Tektronix TDS7404 timing scope, and Fig. 24 illustrates its power spectrum measured using the Agilent E440A with resolution bandwidth of 0.1 MHz. Fig. 25 shows the measured respiratory waveforms from 1 to 4 m. When the range was 1 and 2 m, the RX gain was set to 68 dB. The amplitude of the waveforms measured from 1 m

was 0.8 V, which is four times that measured from 2 m and consistent with the radar (2). When the range was 4 m, the RX gain was set to 80 dB. The amplitude of the measured waveforms was the same as that measured at the 2-m range, which is also consistent with the radar (2) with the additional 12-dB RX gain; however, the waveforms were not clear as those measured at the 2-m range because of the worse SNR. Fig. 25 also shows a comparison of the measured radar signal (blue solid lines) and the parameterized linear segments (red dash lines) mentioned in Section IV. The piecewise linear signals fit the measured respiration signal well. Thus, the data compression and feature extraction can reduce the required data storage space and provide sufficient respiratory feature in longterm respiration monitoring systems. Table I shows a summary of the performance of the implemented CMOS radar chip. Notably, the dc power consumption is clearly lower than that reported in previous works [9], [10]. Fig. 26 shows the radar system comprising the radar chip and DSP backend, radar chip on a PCB board, and TX/RX antenna. The radar chip senses the target and delivers the measured signals to the DSP platform for data compression. A computer

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TABLE I CMOS CHIP PERFORMANCE SUMMARY

Fig. 26. Radar system with radar chip, FPGA, and computer.

sends control signals to the radar chip and displays real-time processing results on a graphical user interface. An institutional review board approved the application of the system to a clinical trial experiment in the Shuang-Ho Hospital, New Taipei City, Taiwan, to verify the proposed system and algorithm. The main target of the project was to construct a new diagnosis flow for respiratory disease with the proposed wireless sensor system. In the original diagnosis flow, a subject must use a spirometer to measure the volume of air inspired and expired by the lungs [see Fig. 27(a)]. Next, the subject continually walks in a straight path back and forth for 6 min, called the 6-min walk test (6MWT), as shown in Fig. 27(b). This test is typically used to test exercise tolerance in chronic respiratory diseases and heart failure. After the 6MWT, the patient is again subjected to the same measurement as that before the 6MWT. Finally, according to the pre- and post-6MWT measurements, the doctor determines whether the patient has or is at a risk of having respiratory diseases. In the new diagnosis flow, the radar system plays the role of spirometer in the original diagnosis flow to monitor a subject’s respiratory activities [see Fig. 27(c)]. Therefore, a new index for diagnosis of respiratory diseases was modeled by a hospital researcher according to knowledge based on exercise physiology. The model reliability was verified by applying an adaptive network-based fuzzy inference system (ANFIS) [24] and support vector machine (SVM) classifier [25] to the original and new diagnosis indices.

Fig. 27. Diagnosis flow for respiratory diseases. (a) Monitoring respiratory activities using a spirometer. (b) 6MWT in a straight path. (c) Monitoring respiratory activities using the radar system.

Fig. 28 shows the clinical trial measurement results obtained using the new diagnosis index. The parameter in the -axis is the change in the respiration intensity before and after clinical patients perform a standard 6MWT, and the ratio in the -axis is the change in the ratios of the inhalation rate to the exhalation rate before and after the 6MWT. A total of 50 people were invited to participate in this clinical trial. Among the participants, 32 were subjects with bad respiratory function (red triangles), and the remaining participants were subjects with normal respiratory function (blue circles) diagnosed by the spirometer, respectively. The measurement results reveal that the features of the subjects with worse respiratory function tend to be distributed in the upper left region of the plot, whereas those of the people with normal respiratory function tend to be distributed in the bottom right region.

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to determine the hyper-plane and establish a wireless sensing home-care system for rapidly screening respiratory diseases. VI. CONCLUSION

Fig. 28. SVM verification for determining the classification ability of the radar system compared with the spirometer; accuracy is 73.3%.

This paper has described a low-power wireless sensor comprising a CMOS chip and a DSP platform for monitoring human respiratory activities. Human respiratory features can be extracted to provide intelligent wireless healthcare services. Moreover, clinical trial results and verification through the SVM and ANFIS algorithms proved the effectiveness of the proposed system in providing an inexpensive and easy solution for diagnosing respiratory diseases. Moreover, the proposed system has potential applicability in other healthcare applications, such as elderly falling detection, infant breath rate monitor, etc. REFERENCES

Fig. 29. ANFIS verification for predicting FEV1/FVC index measured by the spirometer by using trapezoidal membership functions, where the mean FEV1/FVC is 75.3, root-mean-square error is 11.35, correlation is 68%, and regression slope is 0.6.

Fig. 28 also illustrates an SVM-based verification of the classification ability of the radar system compared with that of the spirometer. In the verification process, the new diagnosis index was used to classify participants with normal and bad respiratory function diagnosed using the spirometer. The green line represents a hyper-plane drawn using the SVM algorithm. The results revealed that the classification accuracy was 73.3%, which is a moderately high value and implies that the new modeled index has the ability to classify subjects with normal and bad respiratory function. For the ANFIS verification, the radar system was used to predict an index, called the FEV1/FVC index, measured using the spirometer. This index is usually used to diagnose respiratory diseases. The verification was conducted using the ANFIS algorithm with trapezoidal membership functions through a leaveone-out cross-validation process in which Amp and ratio indices measured by the radar system were used as the input. Fig. 29 shows the results, indicating that the mean FEV1/FVC is 75.3, root-mean-square error is 11.35, correlation is 68%, and regression slope is 0.6, which are generally favorable results in the biomedical field. The SVM and ANFIS results confirmed the reliability of the radar system and new model index and proved their applicability in diagnosing respiratory diseases. As the project proceeds, more data can be collected to revise the model to complete the new diagnosis flow, and even SVM programming

[1] A. Droitcour, O. Boric-Lubecke, V. Lubecke, J. Lin, and G. Kovacs, “Range correlation and IQ performance benefits in single-chip silicon doppler radars for noncontact cardiopulmonary monitoring,” IEEE Trans. Microw. Theory Techn., vol. 52, no. 3, pp. 838–848, Mar. 2004. [2] C. Li, Y. Xiao, and J. Lin, “Experiment and spectral analysis of a low-power ka-band heartbeat detector measuring from four sides of a human body,” IEEE Trans. Microw. Theory Techn., vol. 54, no. 12, pp. 4464–4471, Dec. 2006. [3] F.-K. Wang et al., “A novel vital sign sensor based on a self-injectionlocked oscillator,” IEEE Trans. Microw. Theory Techn., vol. 58, no. 12, pp. 4112–4120, Dec. 2010. [4] C. Li, J. Ling, J. Li, and J. Lin, “Accurate doppler radar non-contact vital sign detection using the RELAX algorithm,” IEEE Trans. Instrum. Meas., vol. 59, no. 3, pp. 687–695, Mar. 2010. [5] P.-H. Wu, J.-K. Jau, C.-J. Li, T.-S. Horng, and P. Hsu, “Vital-sign detection doppler radar based on phase locked self-injection oscillator,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2012, pp. 1–3. [6] C. Li, V. Lubecke, O. Boric-Lubecke, and J. Lin, “A review on recent advances in Doppler radar sensors for noncontact healthcare monitoring,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 5, pp. 2046–2060, May 2013. [7] T. Mitomo, N. Ono, H. Hoshino, Y. Yoshihara, O. Watanabe, and I. Seto, “A 77 GHz 90 nm CMOS transceiver for FMCW radar applications,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 928–937, Apr. 2010. [8] J. Lee, Y.-A. Li, M.-H. Hung, and S.-J. Huang, “A fully-integrated 77-GHz FMCW radar transceiver in 65-nm CMOS technology,” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2746–2756, Dec. 2010. [9] Y.-H. Kao, C.-M. Lai, J.-M. Wu, P.-C. Huang, P.-H. Hsieh, and T.-S. Chu, “A frequency-defined vernier digital-to-time converter for impulse radar systems in 65 nm CMOS,” in Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2014, pp. 474–475. [10] C.-M. Lai, J.-M. Wu, P.-C. Huang, and T.-S. Chu, “A scalable direct-sampling broadband radar receiver supporting simultaneous digital multibeam array in 65 nm CMOS,” in Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2013, pp. 242–243. [11] T.-S. Chu, J. Roderick, S. Chang, T. Mercer, C. Du, and H. Hashemi, “A short-range UWB impulse-radio CMOS sensor for human feature detection,” in Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2011, pp. 294–296. [12] H. Moyer et al., “A low noise chipset for passive millimeter wave imaging,” in IEEE MTT Int. Microw. Symp. Dig, 2007, pp. 1363–1366. [13] J. Lynch et al., “Passive millimeter-wave imaging module with preamplified zero-bias detection,” IEEE Trans. Microw. Theory Techn., vol. 56, no. 7, pp. 1592–1600, Jul. 2008. [14] S. Geng, D. Liu, Y. Li, H. Zhuo, W. Rhee, and Z. Wang, “A 13.3 mW 500 Mb/s IR-UWB transceiver with link-margin enhancement technique for meter-range communications,” in Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2014, pp. 160–161. [15] B. Francois and P. Reynaert, “A transformer-coupled true-RMS power detector in 40 nm CMOS,” in Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2014, pp. 30–31.

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[16] T. Terada, S. Yoshizumi, M. Muqsith, Y. Sanada, and T. Kuroda, “A CMOS ultra-wideband impulse radio transceiver for 1-Mb/s data communications and 2.5-cm range finding,” IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 891–898, Apr. 2006. [17] D. Zito et al., “SoC CMOS UWB pulse radar sensor for contactless respiratory rate monitoring,” IEEE Trans. Biomed. Circuits Syst., vol. 5, no. 6, pp. 503–510, Dec. 2011. [18] S. Shahramian, S. Voinigescu, and A. Carusone, “A 30-GS/sec track and hold amplifier in 0.13- m CMOS technology,” in IEEE Custom Integr. Circuits Conf., Sep. 2006, pp. 493–496. [19] H. Orser and A. Gopinath, “A 20 GS/s 1.2 V 0.13 CMOS switched cascode track-and-hold amplifier,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 7, pp. 512–516, Jul. 2010. [20] C.-M. Lai, K.-W. Tan, Y.-J. Chen, and T.-S. Chu, “A UWB impulseradio timed-array radar with time-shifted direct-sampling architecture in 0.18- m CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 7, pp. 2074–2087, Jul. 2014. [21] S.-T. Tseng et al., “A 65 nm CMOS low power impulse radar for respiratory feature extraction,” in IEEE RFIC Symp., May 2015, pp. 251–254. [22] P.-Y. Chao, C.-W. Tzeng, S.-Y. Huang, C.-C. Weng, and S.-C. Fang, “Process-resilient low-jitter all-digital PLL via smooth code-jumping,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 12, pp. 2240–2249, Dec. 2013. [23] C.-H. Hsieh, Y.-F. Chiu, Y.-H. Shen, T.-S. Chu, and Y.-H. Huang, “A UWB radar signal processing platform for real-time human respiratory feature extraction based on four-segment linear waveform model,” IEEE Trans. Biomed. Circuits Syst., vol. 10, no. 1, pp. 219–230, Feb. 2016. [24] J.-S. Jang, “ANFIS: Adaptive-network-based fuzzy inference system,” IEEE Trans. Syst., Man, Cybern., vol. 23, no. 3, pp. 665–685, May/Jun. 1993. [25] B. Koley and D. Dey, “Real-time adaptive apnea and hypopnea event detection methodology for portable sleep apnea monitoring devices,” IEEE Trans. Biomed. Eng., vol. 60, no. 12, pp. 3354–3363, Dec. 2013. Shao-Ting Tseng was born in Pingtung County, Taiwan, in 1990. He received the B.S. degree in electrical engineering from National Tsing Hua University, Hsinchu, Taiwan, in 2012, and is currently working toward the Ph.D. degree in electrical engineering at National Tsing Hua University. His research interests are mainly focused on phaselocked loops and silicon-based RF and mixed-mode integrated circuit and system design. Mr. Tseng was the recipient of the NOVATEK Fellowship in 2015.

Yu-Hsien Kao received the B.S. degree in electrical engineering from National Tsing Hua University, Hsinchu, Taiwan, in 2012, and is currently working toward the Ph.D. degree at National Tsing Hua University. His research interests include CMOS RF, analog and mixed-signal integrated circuits design. Mr. Kao was the recipient of the NOVATEK Fellowship in 2015.

Chun-Chieh Peng received the B.S. degree in mechanical and electromechanical engineering from National Sun Yat-sen University, Kaohsiung City, Taiwan, in 2012, and is currently working toward the Ph.D. degree in integrated circuits and systems at National Tsing Hua University, Hsinchu, Taiwan. His research interests include high-speed analogto-digital converters and mixed-signal integrated-circuit design.

Jinn-Yann Liu received the B.S. degree in electrical engineering from National Chung Hsing University, Taichung, Taiwan, in 2011, and the M.S. degree in electrical engineering from National Tsing Hua University, Hsinchu, Taiwan, in 2014. His research interests include digital phase-locked loops and digital delay-locked loops with standardcell based design.

Shao-Chang Chu received the B.S. degree (under the double specialty program of management and technology) and M.S. degree in electrical engineering from National Tsing Hua University, Hsinchu, Taiwan, in 2011 and 2014, respectively. His research interests are mainly focused on alldigital-delay-locked loops, edge combiners, and digital frequency multiplier integrated circuit and system design.

Guo-Feng Hong received the B.S. degree in electrical engineering from National Chung Hsing University, Taichung, Taiwan, in 2010, and the M.S. degree in electrical engineering from National Tsing Hua University, Hsinchu, Taiwan, in 2014. Since 2015, he has been with Mediatek, Hsinchu City, Taiwan.

Chi-Hsuan Hsieh was born in Taipei City, Taiwan, in 1984. He received the B.S. degree in electrical engineering and M.S. degree in communications engineering from National Tsing Hua University, Hsinchu, Taiwan, in 2007 and 2009, respectively, and is currently working toward the Ph.D. degree at the Institute of Communications Engineering, National Tsing Hua University. His research interests include ultra-wideband communications, error correction coding, and biomedical signal processing.

Kung-Tuo Hsu was born in Miaoli County, Taiwan, in 1991. He received the B.S. degree in electrical engineering from Tunghai University, Taichung, Taiwan, in 2013, and the M.S. degree in electrical engineering from National Tsing Hua University, Hsinchu, Taiwan, in 2015. He is currently an Integrated Circuit (IC) Design Engineer with the ASolid Technology Company Ltd., Hsinchu, Taiwan.

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Wen-Te Liu received the M.D. (medical doctor) degree from the Faculty of Medicine, Taipei Medical University, Taipei, Taiwan, on 1996. From 1998 to 2011, he was with the Chang Gung Memorial Hospital for Fellowship training of pulmonology and later was an Attending Physician there. Since August 2011, he has been with the Department of Chest Medicine, Shuang Ho Hospital, New Taipei City, Taiwan, as an Attending Physician. In August 2012, he also joined the School of Respiratory Therapy, Taipei Medical University, as an Assistant Professor.

Yuan-Hao Huang (S’98–M’02) was born in Miaoli County, Taiwan, in 1973. He received the B.S. and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1995 and 2001, respectively. From 2001 to 2005, he was a Member of Technical Staff with the VXIS Technology Corporation, Hsinchu City, Taiwan. Since 2005. He has been with the Department of Electrical Engineering and the Institute of Communications Engineering, National Tsing-Hua University, Hsinchu, Taiwan, where he is currently an Associate Professor. His research interests include very large scale integration (VLSI) design for digital signal-processing systems and telecommunication systems. Dr. Huang is an Advisory Board Member of the IEEE Signal Processing Society Design and Implementation of Signal Processing Systems (DiSPS) Technical Committee. He is also a Member of the IEEE Circuits and Systems Society VLSI Systems and Applications (VSA) Technical Committee.

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Shi-Yu Huang (S’94–M’97–SM’12) received the B.S. and M.S. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1988 and 1992, respectively, and the Ph.D. degree in electrical and computer engineering from the University of California at Santa Barbara, Santa Barbara, CA, USA, in 1997. Since 1999, he has been a member of the faculty of the Electrical Engineering Department, National Tsing Hua University, Hsinchu, Taiwan. His research interests include very large scale integration (VLSI) design, automation, and testing with a current emphasis on all-digital phaselocked loop (ADPLL) design and its application in parametric fault testing and monitoring in three-dimensional (3-D) integrated circuits (ICs). Dr. Huang currently serves as an Associate Editor for the IEEE TRANSACTIONS ON COMPUTERS.

Ta-Shun Chu (S’06–M’10) received the B.S. degree in civil engineering and M.S. degree in applied mechanics from National Taiwan University, Taipei, Taiwan, in 2000 and 2002, respectively, and the Ph.D. degree in electrical engineering from the University of Southern California, Los Angeles, CA, USA, in 2010. In 2010, he joined the Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan, as an Assistant Professor. Dr. Chu was the recipient of the Alfred E. Mann Innovation in Engineering Doctoral Fellowship (2008–2009).

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Design and Optimization of Area-Constrained Wirelessly Powered CMOS UWB SoC for Localization Applications Jian Kang, Student Member, IEEE, Sujaya Rao, Patrick Chiang, Senior Member, IEEE, and Arun Natarajan, Member, IEEE

Abstract—This paper discusses the design of a batteryless wirelessly powered ultra-wideband (UWB) system-on-a-chip (SoC) tag for area-and-volume-constrained localization applications such as insect tracking. Key challenges for wirelessly powered operation at 10-m range include the design of high-sensitivity rectifiers and low-voltage high-efficiency UWB transmitters (TX). An antenna-rectifier co-design methodology is presented for sensitivity optimization under area constraints. A 300-nA power management unit (PMU) and low-voltage (0.8-V) UWB TX increases tag operating range by ensuring high rectifier sensitivity under loaded conditions and reducing required rectifier output voltage. The rectifier, PMU, and UWB TX are integrated in 65-nm CMOS, and the rectifier demonstrates state-of-the-art 30.7–dBm sensitivity for 1-V output voltage with only 1.3 cm antenna area, representing a 2.3 improvement in sensitivity over previously published work, at 2.6 higher frequency with 9 smaller antenna area, translating into a 50% longer range at the same frequency. The 0.8-V UWB TX consumes 64 pJ/pulse at 28-MHz pulse repetition rate and achieves 2.4 GHz 10-dB bandwidth. Wireless measurements demonstrate sub-10-cm range resolution at ranges exceeding 10 m. Tag measurements in typical office environments demonstrate 20-m-range RF-energy harvesting with 36-dBm effective-isotropic radiated power in the 2.4-GHz ISM band. Index Terms—Antenna, IR-UWB, localization, power management, RF energy harvesting, sensitivity, transmitter.

I. INTRODUCTION

W

IRELESSLY POWERED sensor networks are of interest for Internet-of-Things (IoT) applications due to their ability to operate without battery lifetime/replacement costs and constraints [1]–[6]. Moreover, high-levels of system-on-a-chip (SoC) integration imply that sensor tag weight, area, and volume are often limited by batteries and antennas [7]–[14]. Tracking the spatial position of miniature objects in three dimensions is important for many asset-tracking

Manuscript received August 10, 2015; revised December 12, 2015; accepted February 20, 2016. Date of publication March 17, 2016; date of current version April 01, 2016. This work was supported by the USDA NIFA . This paper is an expanded version from the IEEE RFIC Symposium, Phoenix, AZ, USA, May 17–19, 2015. J. Kang, P. Chiang, and A. Natarajan are with the School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR 97330 USA (e-mail: [email protected]; [email protected]; [email protected]). S. Rao is with the Department of Crop and Soil Science, Oregon State University, Corvallis, OR 97330 USA (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2536663

Fig. 1. Relative TDOA-based localization using wirelessly powered UWB TX SoC.

applications [15]–[19]. Spatial positioning tags are also useful in biological applications [20]–[23]—for instance, the foraging and pollination patterns of bumblebees are of great interest in the context of the key role that bees play in crop pollination and the unexplained fluctuations in bee-colony populations. Technical specifications for such insect-tracking tags are stringent, as these localization-capable sensors must achieve 10-cm resolution with extremely small form-factor and weight that minimize impact on insect flight. Similar to other volume-sensitive IoT applications, the targeted 100-mg weight, 1-cm dimensions, and 10-m range cannot be satisfied with batteries or piezoelectric/solar-harvesting. However, RF energy-harvesting from a beacon signal transmitted by a base-station can provide a robust, low-form factor/weight mechanism for powering the tag. Time-difference-of-arrival (TDOA) schemes provide reliable localization performance and are less sensitive to multipath. However, TDOA localization requires triangulation based on signals received at multiple base-stations (Fig. 1) as well as wide bandwidths to achieve high resolution [24], [25]. Therefore, ultra-wideband (UWB) systems with multi-GHz bandwidths are attractive for such applications. Increasing the tag range in such schemes enables the reduction in number of base-station nodes. The maximum range of wirelessly powered UWB sensor tags is limited by either the tag rectifier sensitivity, i.e., input power required to achieve targeted output voltage, or by the signal-to-noise ratio (SNR) achieved by the sensor

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Fig. 3. Circuit and antenna model used to codesign antenna and rectifier for area-constrained sensitivity optimization. Fig. 2. Wirelessly powered sensor operating range is limited by rectifier sensitivity rather than by the SNR required for the wireless data link between the sensor and base-station.

transmitter (TX) localization signal at the base-station receiver (RX). As shown in Fig. 2 [26], even if state-of-the-art rectifier sensitivity of 30 dBm and beacon TX effective isotropic radiated power (EIRP) of 1 W are assumed, the sensor tag range is limited by rectifier sensitivity rather than by sensor SNR at the base-station for typical applications. While range can be improved with higher sensor tag antenna gain, this reduces the tag field-of-view and causes an undesirable increase in tag size. Therefore, rectifier sensitivity optimization is critical for increasing sensor operating range. A wirelessly powered UWB SoC with rectifier–antenna codesign for sensitivity optimization was presented in [27], and system-level tradeoffs/approaches in the context of insect-localization application were described in [26]. In this paper, we present further details of the optimization approach underlying the codesign of the antenna and rectifier for area-constrained localization applications. A charge-conservation-based one-stage model that enables faster estimation of rectifier output voltage and charging times is also described in Section II. The one-stage model is used in the systematic codesign approach, detailed in Section II, that leads to state-of-the-art rectifier performance given area constraints. From a system perspective, rectifier sensitivity can also be improved by reducing rectifier load current and targeted output voltage. Section III details the design of the power-management unit (PMU) in [27] and presents the 8-GHz UWB pulse generation and PA design approach that operates with 0.8-V supply and directly matches UWB TX output to a compact loop antenna. Section IV describes the measured performance of the wirelessly powered UWB SoC including rectifier and UWB antennas, demonstrating state-of-the-art performance at range exceeding 10 m. Conclusions and areas of future research are discussed in Section V. II. ANTENNA–RECTIFIER CODESIGN FOR AREA-CONSTRAINED APPLICATIONS A. Weight/Area Budget and Design Challenges Our objective is a positioning sensor that is so small and lightweight that it permits insect flight with the sensor attached. This application limits sensor weight and size, precluding the

use of commercial batteries. On the other hand, RF energy harvesting from a beacon signal is lightweight since it only requires an antenna and is reliable if RF energy is present. Total sensor tag weight is targeted to be 100 mg—individual component weights are detailed in Section IV. For the RF-energy harvesting system, rectifier sensitivity in order to achieve a targeted operating range for rectifier output voltage sets for a given TX EIRP (Fig. 2). In the ISM band, the EIRP is limited to 4 W when antenna gain is less than 6 dBi [28]. Since the input power at the antenna is a function of path loss, the range increases for lower frequencies that have lower path loss (Fig. 2). However, lower frequencies result in antenna area larger than the targeted 1 cm . Based on iteration through the design procedure outlined in following sections for ISM frequencies at 900 MHz, 2.4 GHz, and 5.8 GHz, we target 2.4-GHz operation to balance antenna size and path loss. B. Rectifier State of the Art The RF energy available to the rectifier tained from [29]

can be ob-

(1) is RX antenna gain, is the wavelength, and is where TX–RX separation. High path loss at GHz frequencies requires the rectifier to operate from W signal levels—for example, 1-W TX EIRP at 2.4 GHz with 10-m TX-RX separation leads to 1- W for isotropic RX antenna. In the following, the energy-harvesting rectifier sensitivity is defined in terms of the power available to an isotropic RX antenna, [assuming in (1)] [30]. As shown in Fig. 3, the steady-state output voltage in an -stage rectifier, , (2) depends upon the input voltage swing , the rectifier drop voltage , which is also a function of , the transistor threshold voltage and the load resistance . The objective of rectifier design is to minimize the required to achieve a targeted . A lower results in a lower and reduces required . Therefore, several research efforts have focused on reducing effective to improve sensitivity. Rectifiers with zero-

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transistors have demonstrated 26.4-dBm sensitivity for 1-V output at 915 MHz [31]. Notably, improvements provided by zerothreshold are at the cost of increased number of fabrication masks and are limited by higher leakage in the transistors. Floating-gate devices have been proposed that reduce rectifier threshold voltage using passive means [32]. However, this strategy requires a pre-biasing scheme to inject charge on the floating gate to reduce the threshold. Internal threshold compensation can also reduce effective [33]. However, this increases input rectifier capacitance which degrades sensitivity, as discussed in Section II-F. Rectifier design in subthreshold has been analyzed in [34], leading to 32-dBm sensitivity with 50 stages. However, the resulting capacitance limits the use of electrically small antennas at high frequencies. Codesign of antenna and rectifier has been proposed for maximizing by increasing for a given in [30]. Such design techniques can potentially balance tradeoffs between antenna, matching network, rectifier architecture, and sizing to optimize . The device dimensions in [30] are chosen mainly based on charging time optimization which is a weak function of transistor sizing for large widths. Additionally, the antenna used in [30] occupies 12 cm making it unsuitable for small tags. Here, we extend the approach in [30] by proposing a systematic methodology to determine rectifier device sizing, number of stages as well as area-constrained antenna design methodology that leads to state-of-the-art rectifier sensitivity and therefore a significant increase in energy-harvesting range. C. Model for Rectifier–Antenna Codesign The input-swing at the antenna can be computed based on the model in Fig. 3, where the antenna is modeled as a voltage source in series with the radiation resistance, and loss of the antenna. The rectifier's input impedance is capacitive and can be modeled as a resistor in series with a capacitor . A high passive-boost translates a small input swing to a high voltage swing at the rectifier input . Matching the antenna directly to the rectifier input is desirable to avoid losses due to any additional passive components that realize the network. Since the rectifier is capacitive, an inductive antenna impedance is assumed in Fig. 3 [30]. Therefore, the effective quality factor ( ) of the network is given by

Fig. 4. Charge transfer in the steady state in an

Fig. 5. One-stage equivalent model to estimate -stage steady-state output, , and settling time for a given input swing, .

( ). Given the settling time associate with storage capacitor and the current (Fig. 3), rectifier design often involves long transient simulations with time steps dictated by the input RF frequency. Multiple rectifier stages further increase design complexity and simulation time. Therefore, a scalable model that predicts -stage rectifier behavior based on one-stage rectifier simulations can considerably simplify rectifier design while providing key insights. In the steady state, the capacitor dissipates a charge due to the load current in each RF cycle, and hence the rectifier stages must replenish on the storage capacitor. Fig. 4 outlines the charge transfer between multiple rectifier stages in each cycle. Ignoring leakage to the substrate, charge conservation requires that (5) for

(3) and, for high we have

, assuming antenna and rectifier resonance, (4)

where and . The antenna and rectifier parameters are related to targeted output voltage through (2) and (4), which serves as the basis for minimizing in the following sections. D. Multistage Rectifier Design Design parameters for a multistage rectifier in Fig. 4 include the number of stages , as well as rectifier device geometry

-stage rectifier.

(6) Therefore

(7)

Hence, each rectifier-stage current is the same, with the current compensating the charge loss due to and -stage rectifier leakage currents. This leads to the equivalent one-stage rectifier model in Fig. 5, which has the same load current as the -stage rectifier and can accurately estimate performance with faster simulations, as discussed below. From (2), predicting requires . While the subthreshold model used in [34] can be used to calculate from closed-form equations, [34] assumes no . The finite load current due to the PMU implies that even in subthreshold, the

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Fig. 7. Loop antenna parameters at 2.4 GHz used in the model in Fig. 3. Fig. 6. Comparison between simulated and estimated from one-stage model shows accuracy of approach.

rectifier voltage drop is affected by and . Therefore, simulations are required to accurately estimate . The one-stage model in Fig. 5 can be used to accurately determine for a given from simulated as follows: (8) and -stage output can be simply calculated from (2) and (8) for the model in Fig. 3. Hence, the one-stage model enables the for the -stage rectifier to be determined from faster one-stage rectifier simulations. Fig. 6 validates the assumption of negligible substrate leakage in (7), where the impact of leakage due to higher voltages in -stage rectifiers is ignored. The simulated -stage rectifier shown in dashed line matches estimation using onestage simulations for different and . The required for a targeted -stage output voltage can be determined from (2), (4), and (8) as follows:

the -stage case (Fig. 5). Since the -stage case has times higher voltage on , it takes times longer to achieve the steady state in the -stage case. A similar argument can also be constructed based on the -times smaller effective load resistance for the one-stage model, implying times larger charging time constant. Hence, the -stage charging time can be estimated from one-stage charging time as (11) F. Rectifier–Antenna Codesign Approach As discussed in Section II-C, directly resonating the antenna and the rectifier avoids losses associated with additional matching components. For resonance, we have (12) The model for the loop antenna wire radius and loop radius corresponding to Fig. 3 is given by [35]

(9) and the rectifier operating range (1) and (9) as follows:

(13)

can be computed from (14)

(10) The quality factor of the antenna is therefore As will be described in the following, the one-stage model can also be used to estimate charging times and simplifies systematic rectifer–antenna codesign and optimization. E. Rectifier Charging-Time Estimation Model Charging time , of the -stage rectifier is also an important parameter in some applications. It is defined as the 10%–90% time that the storage capacitor needs to reach steady state voltage and is dependent on rectifier and the load. From charge-transfer perspective, the charge transferred to the load in the one-stage case in each cycle is the same as in

(15) , , ,and of a loop Fig. 7 plots antenna at 2.4 GHz as a function of loop radius for wire radius 250 m. Notably, increases faster compared with as the loop circumferences gets closer to , leading to higher loop-antenna efficiency. However, as loop size becomes larger, increases faster than the reactance, resulting in lower . Since (9) shows that the output voltage depends on as well as , optimum sensitivity is achieved by

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Fig. 9. Rectifier and antenna quality factors following codesign approach in Fig. 8, satisfying 1-V output voltage target.

Fig. 8. Systematic rectifier–antenna codesign for optimizing rectifier sensitivity.

balancing these tradeoffs. Fig. 8 outlines the proposed systematic area-constrained antenna–rectifier codesign approach. 1) Rectifier–Antenna Codesign Procedure: 1) For a given rectifier device geometry , the one-stage model is used to determine as a function of . The large-signal input impedance of the one-stage rectifier for is computed using Fourier transform of the steadystate rectifier current, where (16) 2) For each of interest, one-stage can be used to estimate , which is the minimum required to achieve targeted steady-state output voltage . -stage rectifier input impedance is computed from (17) (18) (19) where represents the layout-dependent input wiring and pad parasitic capacitances ( 100 fF). 3) Given -stage input impedances, (12) and (13) determine loop antenna size. Therefore, and can be computed from (15). 4) Following this, the required to achieve for the given and can be determined from (9). The procedure is iterated across multiple stage number and devices sizes to determine the minimum sensitivity. This design procedure is summarized in Fig. 8 and is adopted in order to codesign a 2.4-GHz rectifier and loop antenna in 65-nm CMOS, with loop antenna radius limited to 6.5 mm.

Fig. 10. Required to achieve targeted 1-V output voltage across device width and number of rectifier stages.

Given (12) and (13), this sets a lower bound on and hence limits the permissible combinations of and . Differential cross-connected rectifier topology is adopted since it effectively reduces turn-on voltage[30]. Minimum channel length is chosen for all transistors to minimize device capacitances. Fig. 9 shows the antenna and rectifier at 2.4 GHz across for different , assuming a 1-V target, 100 nA, and resonance between loop antenna and rectifier. Increasing leads to higher and a steep reduction in , and gradual increase in as loop antenna radius decreases. Larger leads to higher due to presence of wiring and pad parasitics [ in (19)] that do not scale with . The increase in for larger also leads to smaller antenna size and higher . As described earlier, smaller antenna size leads to poorer that degrades sensitivity. The overall impact of these tradeoffs is shown in Fig. 10, which plots the sensitivity following the design procedure in Fig. 8. A small device size with provided the optimum sensitivity in simulation but can lead to long charging time. Increasing the device width in the rectifier leads to faster charging times. In order to balance sensitivity with practical charging

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Fig. 11. Wirelessly powered UWB TX SoC with 2.4-GHz rectifier, low-current PMU, and 0.8-V 8-GHz UWB TX.

time, a choice with 5 m is selected for this design since it reduces charging time by factor of three, albeit with a 1.8-dB poorer simulated sensitivity. The loop antenna corresponding to the selected rectifier size presents a simulated impedance of at the rectifier input, resonating rectifier capacitance. Including the rectifier, the simulated is 70 based on (3), corresponding to a bandwidth of 30 MHz. This approach of directly resonating antenna and rectifier does present smaller bandwidths since high- passive boost is targeted, however calibration (similar to [30]) can be used to ensure rectifier operation at desired frequency. A similar optimization approach is carried out at 900 MHz with the same antenna area constraint to determine the minimum and hence the rectifier operating range. Based on these simulations, an operating frequency of 2.4 GHz was selected for RF-energy harvesting. III. WIRELESSLY POWERED UWB TX SOC The wireless-energy rectifier outlined in Section II is used to power a UWB TX sensor node SoC shown in Fig. 11. Dutycycled operation is assumed where the rectifier charges a capacitance, ( in Fig. 11), and the UWB TX is enabled only when sufficient voltage has been built up on the capacitor. The UWB TX hence operates in bursts which is suited for low-data-rate sensors which do not require continuous transmission. Low-voltage operation is targeted to improve rectifier operating range. The sensor node consists of three integrated blocks: the RF energy harvester, PMU, and UWB transmitter. In power-up mode, wireless TX power from an external 2.4-GHz beacon is harvested and stored on capacitor . A lowcurrent PMU, based on a subthreshold bandgap reference, detects when the voltage on the storage capacitor exceeds a programmable threshold (nominally 1.1 V), after which the low-dropout regulator (LDO) is enabled and provides a constant supply voltage (nominally 0.78 V) to the UWB TX. The 0.8-V UWB TX operates in the higher UWB band with center

Fig. 12. Schematic of programmable PMU that draws

300 nA.

frequency at 8 GHz to ensure multi-GHz bandwidth with a compact loop antenna. A. Power Management Unit The PMU is shown in Fig. 12. The rectifier output voltage powers a bandgap circuit biased in subthreshold region[36]. The bandgap circuit consumes 150 nA when 1.5 V. The simulated variation in across 0 to 50 is 5 mV. The bandgap circuit requires a 0.5 V to achieve stable output voltage 1) Charging Phase: Diode-connected transistor ladder scales the input voltage to different levels. Initially, is connected to since is low. A comparator compares and the bandgap output voltage . As increases, increases, and, hence, toggles to high. While this nominally occurs when 1.1 V, and hence is programmable. When exceeds , enables the switch , and the LDO is activated to provide a stable supply voltage for the UWB transmitter. At the same time, is switched to higher .

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Fig. 13. Generation of UWB pulse with 500-ps pulse width and 8-GHz center frequency using edge combining.

2) Discharging Phase: The UWB-TX current discharges capacitor and hence . When is lower than (normally when is lower than 0.78 V), toggles to low. Switch is turned off, and the LDO is deactivated. The system returns to charging phase. Additionally, when exceeds 1.8 V, turns on to provide a current discharge path to ground, limiting and preventing breakdown. B. UWB Pulse Generation A four-stage differential ring oscillator, tunable from 100 to 400 MHz, provides the clock for the UWB TX (Fig. 11). The oscillator can also be injection-locked to an external input, enabling synchronization with other sensor nodes or base station. The ring oscillator clock is divided by 16 to generate the data clock, leading to on–off keying (OOK) modulated UWB pulses at data rates between 6–28 Mb/s. An on-chip pseudo-random bit-sequence (PRBS) generator is used to emulate coding on the sensor-tag pulses for individual tag identification. OOK modulation is adopted to ensure low-voltage pulse generation. Data are provided to a programmable current-starved delay chain in Fig. 13 that generates edges delayed by 62.5 ps in the case of the Data “1” state. Pulses are created by combining suitable delay edges. For example, delayed edges , , and are fed to the edge-combine branch to generate . Similarly, pulses (black) and (blue) are generated based on other edges of the inverter delay chain, creating eight pulses each with duration of 62.5 ps (Fig. 13). The choice of OOK modulation with an enable mask reduces the number of stacked devices in the pulse generator to four instead of six in [37], enabling 62.5-ps pulse generation from as low as a 0.7-V supply. C. PA Antenna Codesign The PA combines the and pulses from Fig. 13, creating a UWB pulse with 8-GHz center frequency and 500-ps duration (Fig. 11). The PA provides pulse-shaping for the UWB TX output by utilizing weighted transconductances and targets 0-dBm output power, consuming 14 mW when amplifying a pulse. The PA is duty-cycled by creating a PA-Enable mask (Fig. 11) that activates the PA when a pulse needs to be transmitted. The width of the PA-Enable signal is programmable to ensure appropriate settling time for the PA. Differential operation for the TX is critical due to the limited bypass and small ground plane of the area-constrained sensor. In this work, differential PA output-impedance matching to the antenna is achieved using an area-efficient

Fig. 14. Die photograph of wirelessly powered 8-GHz UWB TX implemented in 65-nm CMOS.

transformer-capacitor network that incorporates wirebonds, as shown in Fig. 14. The transformer also separates voltage bias of the PA from antenna. The transformer primary coil and secondary coil are implemented with metal 9 and metal 8 stacked together, occupying an area of 178 m 200 m. EM simulations, performed using Hyperlynx 3D EM (version 15), show transformer primary and secondary inductances of 340 and 360 pH, respectively, with a coupling factor of . The PA is matched to a compact 8-GHz loop antenna which is designed to resonate with bond-wire inductance. With an outer radius of only 0.57 cm, the loop antenna exhibits simulated impedance of at 8 GHz. The transformer-capacitor network is designed such that the PA creates a 0-dBm swing across the antenna radiation resistance. IV. MEASUREMENT RESULTS The wirelessly powered 8-GHz UWB TX SoC is implemented in a 65-nm CMOS process with 3.4- m-thick top-layer metal. The die area is 1 mm 0.8 mm, as shown in Fig. 14. The only off-chip components are compact loop antennas, surface mount (SMT) storage capacitor, and LDO stability capacitors, all of which have very small form factor. A compact chip-on-board package for RF testing is shown in Fig. 15(a). A simulated rectifier antenna pattern, using Ansys High Frequency Structure Simulator (HFSS) (version 15), is shown in Fig. 15(b), demonstrating a gain of 1.1 dBi with 90%

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Fig. 15. (a) UWB SoC packaged with dual planar loop-antennas for RF testing. (b) Simulated 2.4-GHz loop antenna gain. (c) Compact 3-D package for low form-factor and weight.

TABLE I COMPONENT MASS SUMMARY

Fig. 16. Measurement setup for characterizing rectifier performance—setup is initially calibrated to determine available power for the rectifier.

efficiency. Similar gain performance is observed for the 8-GHz UWB antenna with both antennas demonstrating low gain and wide field-of-view. The radius of the 2.4-GHz rectifier antenna is comparable to that of the 8-GHz UWB antenna since the inductive antenna is used to directly resonate the resonator, as was described in Section II-F. While the planar chip-on-board package is used for systematic testing, a small form-factor package with FR-4 as well as flex-PCB with vertical loop antennas has also been developed, as shown in Fig. 15(c). Typical component weights contributing to overall 100-mg sensor tag weight are shown in Table I. Rectifier measurements are carried out both in an anechoic chamber and in typical office environments. Wireless UWB TX performance is measured both in time and frequency domains. Relative time-of-flight (TOF) measurements demonstrate localization capabilities. A. Rectifier–Antenna Performance The rectifier measurement is calibrated using two identical 9-dBi-gain log-periodic antennas, as shown in Fig. 16. The rectifier sensitivity is defined as the available power from an isotropic receiving antenna with impedance and polarization matching, which can be determined from the setup

Fig. 17. Photograph of a 2.4-GHz rectifier–antenna measurement in an anechoic chamber.

in Fig. 16. The measured is consistent with the calculated received power from (1), validating setup calibration. The rectifier and antenna are characterized in an anechoic chamber as shown in Fig. 17. Sensitivity and charging transients under three load conditions of , 10 M , and 1 M were measured. As shown in Fig. 18(a), the implemented rectifier–antenna achieves state-of-the-art 30.7-dBm sensitivity for 1-V output voltage. Notably, this performance is achieved with only 1.3-cm of antenna area demonstrating the validity of the proposed optimization based on rectifier–antenna codesign. The measurements agree well (within 1 dB) with simulations in Fig. 10, and the relatively small difference (1 dB) between simulation and measurement most likely comes from inaccurate transistor models at subthreshold region (where rectifier transistors operate at sensitivity) and wirebond/antenna modeling inaccuracies. Fig. 18(b) shows the measured charging time under both 10 M and 1 M load when charging a 1-uF tantalum storage capacitor to 1-V . Rectifier power conversion efficiency (PCE) is defined as (20) is the power dissipated in the load resistance. where Fig. 18(c) shows measured PCE under both 10- and 1-M

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Fig. 18. Measured 2.4-GHz rectifier performance. (a) Rectifier sensitivity across target output voltage and 1 M and 10 M . capacitor. (c) Rectifier PCE across input power for

Fig. 19. Photograph of a 2.4-GHz rectifier-antenna characterization in a typical office conference room.

load conditions. For 1-M load, the maximum PCEis 37% at of 23 dBm. The rectifier and antenna are also measured in practical scenarios. In an office corrider, 1-V can be generated with a TX EIRP of 4 W at 20-m distance, which is consistent with 30-dBm sensitivity based on (10). However, multipath fading effects and increased sensitivity to antenna orientation and position was observed. Rectifier performance is also studied in a conference room, as shown in Fig. 19. The same setup is adopted here as in the anechoic chamber, and 10-M load is considered. The required TX EIRP for charging the to 1-V output is measured as shown in Fig. 20. The required EIRP gradually increases for larger separation between source and rectifier. However, the required EIRP is less than the 36-dBm FCC limit for several cases. B. PMU and UWB TX Performance Fig. 21(a) shows the measured bandgap output voltage across . The bandgap circuit can maintain output voltage as varies from 0.5 to 1.5 V. Fig. 21(b) shows measured LDO output voltage in both charging and discharging phases. It can be seen that the PMU

. (b) Rectifier charging time for 1- F storage

Fig. 20. Diagram of measured 2.4-GHz rectifier performance in a conference room demonstrating feasibility of wireless powering in typical office environments.

can switch on and off as expected and LDO can generate a constant 0.78-V supply voltage for the UWB TX block. As simulated, the PMU consumes 300nA. The UWB TX is characterized using a connectorized 100load and with wireless measurements. Since the antenna is designed to absorb a portion of the bond wire inductance, the loading in these two cases is not equivalent. Fig. 21(c) shows the simulated and measured UWB pulse using a connectorized 100- differential load. It can be seen that the measured waveform is consistent with simulations under appropriate loading conditions. Wireless UWB TX performances is measured with TX driving an 8-GHz loop antenna shown in Fig. 15. Note that the UWB TX wireless measurements are performed using external supply for simplicity. Nevertheless, UWB pulse generation with wireless powering has been verified in measurement. In the case of the wirelessly powered UWB TX, the rectifier is loaded by the PMU in charging phase ( 3.3 M ), implying a sensitivity of 25 dBm for the rectifier in this mode [Fig. 18(a)]. Wireless UWB signals are received using a 12-dBi gain 4–12-GHz wideband horn antenna followed by an LNA with 23-dB gain (including cable losses) driving a 25-GHz

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Fig. 21. Measured PMU and 8-GHz UWB TX performance. (a) Low-voltage bandgap operates with 0.5 V. (b) Measured LDO output demonstrating constant UWB TX voltage supply as well as appropriate enable/disable during charging and discharging phases. (c) Comparison of simulated and measured 8-GHz UWB pulse when UWB TX is characterized with connectorized 100- differential load.

Fig. 22. Wireless measurements of UWB TX in the (a) time domain and (b) frequency domain. Measurements are consistent with 0-dBm UWB TX radiated power. (c) UWB TX pulse achieves 15-dB SNR at 11-m range, demonstrating feasibility of operation beyond 10 m.

Fig. 23. Comparing output of on-chip PRBS which modulates UWB TX and wirelessly measured OOK UWB TX signal at 11-m range.

oscilloscope. Fig. 22(a) and (b) shows wireless measurement and UWB spectrum. Assuming 60-dB path loss (3 m at 8 GHz), the measured 13 dBm signal is equivalent to 0-dBm radiated power at the loop antenna, which is consistent with the simulated 750-mV peak–peak differential output. The low pulse-repetition frequency (6–28 MHz) ensures UWB spectral FCC mask compliance. When pulses are generated at 28 MHz, the UWB transmitter consumes 64 pJ per pulse (14 mW when radiating a pulse).

Fig. 24. Relative TOF measurement using the UWB TX. RX-2 provides baseline while the position of RX-1 is varied.

The choice of storage capacitance is dictated by desired UWB payloads. Given PMU thresholds for UWB TX

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TABLE II RECTIFIER PERFORMANCE COMPARED WITH THE STATE OF THE ART

TABLE III UWB TX PERFORMANCE SUMMARY

enable, 1.1 V, and UWB TX disable, 0.9 V [Fig. 21(b)], a 1- F capacitor implies 0.2- J energy is available from the capacitor in each charge–discharge cycle. At 64 pJ/pulse, this can support a payload with 3000 pulses. For long-distance wireless measurement, the UWB is received using an antenna/LNA setup with 3.5-dB noise figure (NF). The received signal is shown in Fig. 22(c) and achieves 15-dB SNR at 11-m range (limited by test setup). The OOK modulated data is generated by an on-chip PRBS. Fig. 23 compares the PRBS output from the chip with the wirelessly measured UWB pulse sequence, demonstrating OOK-modulated UWB TX performance at range exceeding 10 m. Localization using relative TOF triangulation is emulated using the setup shown in Fig. 24. Two identical receiving paths are used. RX-1 is moved to different locations away from the chip package while RX-2 works as a reference providing a fixed baseline in the testing. The received pulses from RX-1 and RX-2 are processed by a matched filter followed by envelop detection. For different RX-1 locations with 8-cm distance increment and TOF with RX-2 staying stationary, the normalized envelop amplitudes demonstrate sub-10-cm ranging resolution. The performance of the rectifier and UWB TX is summarized and compared with previous state of the art in Tables II and III. The rectifier achieves 2.3 improvement in sensitivity over the state of the art with 9 smaller antenna area ( 1.3 cm ). The 8-GHz UWB TX operates from a 0.8-V supply and consumes only 64 pJ to generate each UWB pulse while achieving 2.4-GHz 10-dB bandwidth at 8 GHz. V. CONCLUSION A batteryless wirelessly powered UWB SoC has been demonstrated that achieves state-of-the-art rectifier sensitivity while meeting size and weight constraints. The UWB SoC design is based on a rectifier modeling and systematic optimization methodology that is generally applicable across

other frequencies and rectifier applications, including wake-up receivers. Rectifier measurements in practical environments and sub-10-cm ranging using the UWB TX with a TDOA approach demonstrates feasibility of batteryless localization sensors with 10-m range while operating under FCC specifications. Future research efforts include further improvement of rectifier sensitivity and reduction in rectifier load currents during the charging phase. Ongoing efforts to deploy the UWB SoC for insect localization demonstrate the possibilities for miniaturized wirelessly powered positioning tags for Internet of Things applications. ACKNOWLEDGMENT The authors would like to thank A. Hazlehurst, Oregon State University, Corvallis, OR, USA, for his work on sensor attachment to insects, Keysight for access to test equipment, and R. Khanna and Intel for providing access to the anechoic chamber. REFERENCES [1] J. Yoo, L. Yan, S. Lee, Y. Kim, and H.-J. Yoo, “A 5.2 mW self-configured wearable body sensor network controller and a 12 W wirelessly powered sensor for a continuous health monitoring system,” IEEE J. Solid-State Circuits, vol. 45, no. 1, pp. 178–188, Jan. 2010. [2] Z. Safarian and H. Hashemi, “A wirelessly-powered passive RF CMOS transponder with dynamic energy storage and sensitivity enhancement,” in Proc. IEEE Radio Frequency Integr. Circuits Symp., Jun. 2011, pp. 1–4. [3] S. Mandal and R. Sarpeshkar, “Low-power CMOS rectifier design for RFID applications,” IEEE Trans. Circuits Syst.: I, Reg. Papers, vol. 54, no. 6, pp. 1177–1188, Jun. 2007. [4] Y.-J. Huang et al., “A self-powered cmos reconfigurable multi-sensor soc for biomedical applications,” IEEE J. Solid-State Circuits, vol. 49, no. 4, pp. 851–866, Apr. 2014. [5] H. Reinisch, S. Gruber, H. Unterassinger, M. Wiessflecker, G. Hofer, W. Pribyl, and G. Holweg, “An electro-magnetic energy harvesting system with 190 nW idle mode power consumption for a BAW based wireless sensor node,” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1728–1741, Jul. 2011.

KANG et al.: DESIGN AND OPTIMIZATION OF AREA-CONSTRAINED WIRELESSLY POWERED CMOS UWB SOC FOR LOCALIZATION APPLICATIONS

[6] A. Liberale, E. Dallago, and A. L. Barnabei, “Energy harvesting system for wireless body sensor nodes,” in Proc. IEEE Biomed. Circuits Syst. Conf., Oct. 2014, pp. 416–419. [7] Y.-T. Liao, H. Yao, A. Lingley, B. Parviz, and B. P. Otis, “A 3 W CMOS glucose sensor for wireless contact-lens tear glucose monitoring,” IEEE J. Solid-State Circuits, vol. 47, no. 1, pp. 335–344, Jan. 2012. [8] A. Yakovlev, D. Pivonka, T. Meng, and A. Poon, “A mm-sized wirelessly powered and remotely controlled locomotive implantable device,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2012, pp. 302–304. [9] M. Tabesh, N. Dolatsha, A. Arbabian, and A. M. Niknejad, “A powerharvesting pad-less millimeter-sized radio,” IEEE J. Solid-State Circuits, vol. 50, no. 4, pp. 962–977, Apr. 2015. [10] W. Lim, I. Lee, D. Sylvester, and D. Blaauw, “Batteryless sub-nW Cortex-M0+ processor with dynamic leakage-suppression logic,” in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2015, pp. 1–3. [11] Y. Zhang et al., “A batteryless 19 W MICS/ISM-band energy harvesting body sensor node SoC for ExG applications,” IEEE J. SolidState Circuits, vol. 48, no. 1, pp. 199–213, Jan. 2013. [12] J. Yin et al., “A system-on-chip EPC Gen-2 passive UHF RFID tag with embedded temperature sensor,” IEEE J. Solid-State Circuits, vol. 45, no. 11, pp. 2404–2420, Nov. 2010. [13] Y.-C. Shih, T. Shen, and B. P. Otis, “A 2.3 W wireless intraocular pressure/temperature monitor,” IEEE J. Solid-State Circuits, vol. 46, no. 11, pp. 2592–2601, Nov. 2011. [14] T. Akin, K. Najafi, and R. M. Bradley, “A wireless implantable multichannel digital neural recording system for a micromachined sieve electrode,” IEEE J. Solid-State Circuits, vol. 33, no. 1, pp. 109–118, Jan. 1998. [15] J.-O. Park, J.-J. Kim, S.-G. Kim, and M.-S. Jun, “Future store picking system using RFID and USN technique,” in Proc. IEEE Int. Comput. Sci. Convergence Inf. Technol., Nov. 2009, pp. 1071–1075. [16] R. Aliberti, E. Di Giampaolo, and G. Marrocco, “A model to estimate the RFID read-region in real environments,” in Proc. 38th IEEE Eur. Microw. Conf., Oct. 2008, pp. 1711–1714. [17] S. Gezici, Z. Tian, G. B. Giannakis, H. Kobayashi, A. F. Molisch, H. V. Poor, and Z. Sahinoglu, “Localization via ultra-wideband radios: A look at positioning aspects for future sensor networks,” IEEE Signal Processing Mag., vol. 22, no. 4, pp. 70–84, Jul. 2005. [18] C. Zhang, M. J. Kuhn, B. C. Merkl, A. E. Fathy, and M. R. Mahfouz, “Real-time noncoherent UWB positioning radar with millimeter range accuracy: Theory and experiment,” IEEE Trans. Microw. Theory Techn., vol. 58, no. 1, pp. 9–20, Jan. 2010. [19] M. R. Mahfouz, C. Zhang, B. C. Merkl, M. J. Kuhn, and A. E. Fathy, “Investigation of high-accuracy indoor 3-D positioning using UWB technology,” IEEE Trans. Microw. Theory Techn., vol. 56, no. 6, pp. 1316–1330, Jun. 2008. [20] Z.-M. Tsai et al., “A high-range-accuracy and high-sensitivity harmonic radar using pulse pseudorandom code for bee searching,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 1, pp. 666–675, Jan. 2013. [21] J. Kiriazi, J. Nakakura, V. Lubecke, and K. Hall, “Low profile harmonic radar transponder for tracking small endangered species,” in Proc. 29th IEEE Eng. Med. Biol. Soc. Conf., Aug. 2007, pp. 2338–2341. [22] B. G. Colpitts and G. Boiteau, “Harmonic radar transceiver design: Miniature tags for insect tracking,” IEEE Trans. Antennas Propag., vol. 52, no. 11, pp. 2825–2832, Nov. 2004. [23] M. R. Mahfouz, M. J. Kuhn, G. To, and A. E. Fathy, “Integration of UWB and wireless pressure mapping in surgical navigation,” IEEE Trans. Microw. Theory Techn., vol. 57, no. 10, pp. 2550–2564, Oct. 2009. [24] R. Ye, S. Redfield, and H. Liu, “High-precision indoor UWB localization: Technical challenges and method,” in Proc. IEEE Int. Ultra-Wideband Conf., Sep. 2010, vol. 2, pp. 1–4. [25] H. Soganci, S. Gezici, and M. B. Guldogan, “Enhancements to threshold based range estimation for ultra-wideband systems,” in Proc. IEEE Int. Ultra-Wideband Conf., Sep. 2014, pp. 1–6. [26] J. Kang, S. Rao, P. Chiang, and A. Natarajan, “Area-constrained wirelessly-powered UWB SoC design for small insect localization,” in Proc. IEEE Topical Conf. Wireless Sensors and Sensor Netw., Jan. 2016, pp. 18–20. [27] J. Kang, C. Patrick, and A. Natarajan, “A 3.6 cm wirelessly-powered dBm rectifier sensitivity and sub-10 cm range UWB SoC with resolution,” in Proc. IEEE Radio Frequency Integr. Circuits Symp., Jun. 2015, pp. 255–258.

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[28] M. Loy, R. Karingattil, and L. Williams, “ISM-band and short range device regulatory compliance overview,” 2005 [Online]. Available: http:/ /www.ti.com/lit/an/swra048/swra048.pdf [29] D. M. Pozar, Microwave Engineering. Hoboken, NJ, USA: Wiley, 2009. [30] M. Stoopman, S. Keyrouz, H. J. Visser, K. Philips, and W. A. Serdijn, “Co-design of a CMOS rectifier and small loop antenna for highly sensitive RF energy harvesters,” IEEE J. Solid-State Circuits, vol. 49, no. 3, pp. 622–634, Mar. 2014. [31] P. T. Theilmann, C. D. Presti, D. J. Kelly, and P. M. Asbeck, “A W complementary bridge rectifier with near zero turn-on voltage in SOS CMOS for wireless power supplies,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 9, pp. 2111–2124, Sep. 2012. [32] T. Le, K. Mayaram, and T. Fiez, “Efficient far-field radio frequency energy harvesting for passively powered sensor networks,” IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1287–1302, May 2008. [33] G. Papotto, F. Carrara, and G. Palmisano, “A 90-nm CMOS thresholdcompensated RF energy harvester,” IEEE J. Solid-State Circuits, vol. 46, no. 9, pp. 1985–1997, Sep. 2011. dBm sensitivity RF power har[34] S. Oh and D. D. Wentzloff, “A vester in 130 nm CMOS,” in Proc. IEEE Radio Frequency Integr. Circuits Symp., Jun. 2012, pp. 483–486. [35] C. A. Balanis, Antenna Theory: Analysis and Design. Hoboken, NJ, USA: Wiley, 2012. dBm [36] L. Xia, J. Cheng, N. E. Glover, and P. Chiang, “0.56 V RF-powered, multi-node wireless body area network system-on-a-chip with harvesting-efficiency tracking loop,” IEEE J. Solid-State Circuits, vol. 49, no. 6, pp. 1345–1355, Jun. 2014. [37] V. V. Kulkarni, M. Muqsith, K. Niitsu, H. Ishikuro, and T. Kuroda, “A 750 Mb/s, 12 pJ/b, 6-to-10 GHz CMOS IR-UWB transmitter with embedded on-chip antenna,” IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 394–403, Feb. 2009. [38] F. Chen, Y. Li, D. Liu, W. Rhee, J. Kim, D. Kim, and Z. Wang, “A 1 mW 1 Mb/s 7.75-to-8.25 GHz chirp-UWB transceiver with low peakpower transmission and fast synchronization capability,” in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2014, pp. 162–163. [39] J. K. Brown, K.-K. Huang, E. Ansari, R. R. Rogel, Y. Lee, and D. D. Wentzloff, “An ultra-low-power 9.8 GHz crystal-less UWB transceiver with digital baseband integrated in 0.18 m BiCMOS,” in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2013, pp. 442–443. [40] X. Wang et al., “A meter-range uwb transceiver chipset for around-thehead audio streaming,” in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2012, pp. 450–452. [41] S. Soldà, M. Caruso, A. Bevilacqua, A. Gerosa, D. Vogrig, and A. Neviani, “A 5 Mb/s UWB-IR transceiver front-end for wireless sensor networks in 0.13 CMOS,” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1636–1647, Jul. 2011. Jian Kang (S’15) received the B.S and M.S. degrees in electrical engineering from Shanghai Jiao Tong University, Shanghai, China, in 2006 and 2010, respectively. He is currently working toward the Ph.D. degree in electrical engineering at Oregon State University, Corvallis, OR, USA. His research interests include wireless transceivers, low-power biosensors, energy harvesting, localization, and antenna design.

Sujaya Rao received the Ph.D. degree in entomology from the University of Minnesota, St. Paul, MN, USA, in 1991. She conducted postdoctoral research at the University of Delaware and the University of California, Berkeley. She then became an Extension Advisor with the University of California, Davis, CA, USA, before moving to Oregon State University, Corvallis, OR, USA, where she is now a Professor engaged in research, teaching, and extension. Over the years, her research has focused on the behavioral and chemical ecology of plant–insect interactions in native habitats and in diverse cropping systems. Her current research is focused on examination of vision, foraging distances, pollination efficiencies, impacts of exposure to toxic chemicals, and conservation of native bumble bees.

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Dr. Rao was the recipient of the Fulbright Scholar Award and the Organization for Economic Cooperation and Development Fellowship for native bee research in Ecuador and Australia, respectively. She has integrated her research with educational programs which earned her the Distinguished Achievement in Teaching Award from the Entomological Society of America, the Distinction in Student Mentoring Award from the regional branch of the same society and the Hodson Alumnus Award from the University of Minnesota. She has served as the President of the Entomological Society of America and is now serving as a member of the Governing Board.

Patrick Chiang (SM’15) received the B.S. degree in electrical engineering and computer sciences from the University of California, Berkeley, CA, USA, in 1998, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, USA, in 2001, and 2007, respectively. He is currently a 1000-Talents Young Professor with Fudan University and a tenured Associate Professor with Oregon State University, Corvallis. OR, USA. He is a Cofounder of fabless-IC startup PhotonIC Technologies, Shanghai, China. He has published more than 130 conference/journal publications. He leads an international team in both China/USA on energy-efficient microelectronics, including optical transceivers and wearable biosensors-on-a-chip. Dr. Chiang was the recipient of a 2010 Department of Energy Early CAREER award and a 2012 National Science Foundation CAREER Award, for energyefficient interconnects and robust near-threshold computing. He is on the CICC and ASSCC Technical Program Committees.

Arun Natarajan (M’07) received the B.Tech. degree from the Indian Institute of Technology, Madras, India, in 2001, and the M.S. and Ph.D. degrees from the California Institute of Technology, Pasadena, CA, USA, in 2003 and 2007, respectively, all in electrical engineering. From 2007 to 2012, he was a Research Staff Member with IBM T. J. Watson Research Center, Yorktown Heights, NY, USA, where he worked on millimeter-wave (mm-wave) phased arrays for multi-Gb/s data links and airborne radar and on self-healing circuits for increased yield in submicrometer process technologies. In 2012, he joined Oregon State University, Corvallis, OR, USA, as an Assistant Professor with the School of Electrical Engineering and Computer Science. His current research is focused on RF, mm-wave and sub-mm-wave integrated circuits and systems for high-speed wireless communication and imaging. Dr. Natarajan was the recipient of the National Talent Search Scholarship from the Government of India [1995–2000], the Caltech Atwood Fellowship in 2001, the Analog Devices Outstanding Student IC Designer Award in 2004, the IBM Research Fellowship in 2005, the 2011 Pat Goldberg Memorial Award for Best Paper in CS/EE/Math in IBM Research and serves on the Technical Program Committee of the IEEE Radio-Frequency Integrated Circuits Conference, the IEEE Compound Semiconductor IC Symposium, and the 2013 IEEE International Microwave Symposium.

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Low-Power Injection-Locked Zero-IF Self-Oscillating Mixer for High Gbit/s Data-Rate Battery-Free Active RFID Tag at Millimeter-Wave Frequencies in 65-nm CMOS Pascal Burasa, Student Member, IEEE, Nicolas G. Constantin, Member, IEEE, and Ke Wu, Fellow, IEEE

Abstract—In this paper, a low-power zero-IF self-oscillating mixer (SOM) for a new generation of high data-rate battery-free, yet active RFID tag (a fully integrated RF identification tag on a single CMOS die with no external components, nor packaging) operating at millimeter-wave frequencies is proposed and demonstrated. It exploits, on one hand, the intrinsic mixing properties of an LC cross-coupled voltage-controlled oscillator, and on the other hand, the injection-locking properties in oscillators. By injection locking the SOM’s natural oscillation frequency to the reader’s carrier frequency (a frequency that bears information of the tag: reader-to-tag communication), it enables a direct-conversion to the baseband with no external local oscillator (LO) source (self-mixing), nor RF frequency conversion into IF frequency, therefore significantly reducing its power consumption. Up-link communication (tag-to-reader communication) is performed by up-converting the tag’s data using the same SOM. Furthermore, the in-phase injected energy stabilizes the self-generated LO and enhances the SOM phase noise, resulting into a low-phase noise baseband signal. Using a standard 65-nm CMOS process, a 40-GHz zero-IF SOM was designed, fabricated, and tested. Experimental results exhibit a conversion loss of about 30 dB under 38-dBm injected RF power with a power consumption of only 280 W during reader-to-tag communication, and 580 W during tag-to-reader communication. Index Terms—Battery-free active tag, CMOS, injection locking, millimeter-wave identification (MMID), millimeter-wave RF identification (RFID), millimeter-wave voltage-controlled ocillator (VCO), self-oscillating mixer (SOM), self-powered tag.

I. INTRODUCTION

D

RIVEN BY the ever-increasing needs, RF identification (RFID) has attracted much attention as evidenced by a large variety of its applications in our everyday life, ranging Manuscript received August 10, 2015; revised December 08, 2015; accepted February 05, 2016. This work was supported in part by the National Science and Engineering Research Council (NSERC) of Canada and in part by Fonds de Recherches du Québec-Nature et Technologies (FRQNT). This paper is an expanded version from the IEEE RFIC Symposium, Phoenix, AZ, USA, May 17–19, 2015. P. Burasa and K. Wu are with the Poly-Grames Research Center, École Polytechnique de Montréal, Montreal, QC, Canada H3T 1J4 (e-mail: [email protected]; [email protected]). N. G. Constantin is with the École de Technologie Supérieure (ETS), Montreal, QC, Canada H3C 1K3 (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2530717

from security, access control, monitoring, etc., to biomedical systems [1]–[4]. Typically, low RF frequencies (below 3 GHz) have been used for RFID communications and applications. The main factors impeding the evolution of RFID technology over these RF bands are the limited available bandwidth resources and the large tag size (mainly dominated by antenna size at these frequencies and by the battery if active tags are considered). However, the emerging millimeter-wave identification (MMID) technology is set out to exploit smaller antenna size and larger available bandwidths in order to alleviate these limitations [5], [6]. Integrating the tag’s antenna on a single-chip (feasible at millimeter-wave frequencies thanks to smaller antenna size), wirelessly harvesting sufficient dc power from incoming millimeter-wave signals (thereby providing an energy autonomy without the need of a battery and at the same time allowing miniaturization), and transmitting data to the reader over a large bandwidth at millimeter-wave frequencies will lead to the development of a new generation of high data-rate battery-free RFID technology for applications that cannot be made possible today. In parallel, this MMID concept is fully compatible with upcoming and future applications of millimeter-wave technology in wireless communications such as 5G technologies and systems that are being discussed and developed worldwide. Significant progress has been made for on-chip antennas with high gain [7]. Energy can now be efficiently and wirelessly harvested even at millimeter-wave frequencies, as demonstrated in [8]. In addition, extremely low-power CMOS circuit design and techniques for RFID applications have been extensively studied and reported [9]–[12]. However, ultra-low-power and low-complexity millimeter-wave CMOS transceivers relying only on a rectified dc power remain a challenging problem and are not demonstrated in the above-mentioned high data-rate MMID context. In our opinion, self-oscillating mixer (SOM) techniques present an adequate candidate for such low-power millimeter-wave transceivers since they combine both oscillator and mixer functionalities into a single device and under a single bias current. Thus far, published works on SOMs [13]–[16] convert, first of all, the RF frequency into an IF and thereafter filter out frequencies other than the IF signal. This requires extra dc power consumption associated to the IF processing. They are intended for applications with significantly higher power consumption than what is required in self-powered active MMIDs.

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Fig. 1. Block diagram of a recently proposed MMID system with a battery-free active tag on single chip.

On the basis of our previous work [17], more details and analysis of a zero-IF SOM that performs both millimeter-wave receiver and transmitter mixing functions using only one device is proposed and demonstrated. As illustrated in Fig. 1, which represents a newly proposed MMID reader-tag system [8], the proposed mixer is a key circuit block that renders possible the implementation of a battery-free active tag, fully integrated on single CMOS die. From Fig. 1, a reader simultaneously shines a tag or multiple tags with two tones at millimeter-wave frequencies. freq-1, a continuous wave (CW), goes to the millimeterwave-to-dc rectifier and supplies energy to the tag. The reader and the tag therefore exchange highly secured data at a high bit rate on the freq-2 carrier without compromising the tag’s energy, regardless of the type of modulation or coding. During readerto-tag communications, the SOM is injection locked to freq-2, enabling a direct-conversion to baseband without any external local oscillator (LO) source and no additional IF processing, thereby significantly reducing power consumption. Besides, the poor phase noise associated with the SOM’s low-bias current is mitigated by the injection-locking signal since the SOM’s phase noise follows that of the injected signal [18], [19]. For the tag-to-reader communication, the tag’s data are up-converted and transmitted using the same SOM as illustrated in Fig. 1. A measured conversion loss of about 30 dB under 38-dBm injected RF power, with only 580- W dc power consumption, supports the feasibility of the MMID reader-tag system proposed in this paper (Fig. 1). Section II of this paper presents the operating principles of the proposed SOM. Section III analyzes the mixing mechanism of the SOM, and Section IV presents and discusses the measurement setup and results. II. OPERATING PRINCIPLES OF THE PROPOSED ZERO-IF SOM CIRCUIT As illustrated in Fig. 2, during reader-to-tag communications, a reader sends an AM modulated signal , carrying information to either write in the tag or interrogate the tag. In addi-

tion, the signal accomplishes three key functions. First, having the same frequency as the natural oscillation frequency of the SOM, i.e., , injects an in-phase energy into the SOM, which relaxes the negative resistance required to compensate the SOM losses, and therefore triggers and starts LO oscillation with lower power consumption. Second, with , locks the LO to its carrier frequency , allowing a direct-conversion to baseband, given that the LO and are self-mixed. Third, by injection-locking the LO, maintains a phase coherence between both signals, which enhances the SOM phase noise, as well as the phase noise of the down-converted baseband signal. The mixing function is performed by the cross-coupled pair transistors M2 and M3, thanks to their time-varying transconductances , as illustrated in Fig. 4. The down-converted baseband is extracted at the common node . Ideally, even harmonics are in-phase and, therefore, sum up at , but are filtered out by capacitor , whose self-resonance suppresses entirely . The odd harmonics and the fundamental are out of phase and therefore cancel out each other at (self-filtering) [20]. Hence, is a virtual ground at RF frequencies. Note, however, that our circuit topology (Fig. 2) presents a high impedance at the baseband frequency, thus allowing a baseband amplification at the output for zero-IF mixing. This constitutes a fundamental circuit technique difference with other self-mixing oscillators proposed so far (e.g., [13]). During tag-to-reader communications, an injection locking of the SOM is maintained, but with a constant-amplitude millimeter-wave signal coming from the reader (Fig. 2). The tag injects its data (from its memory, sensor, etc.) into the mixer by summing the data signal with and varying the gate voltage and drain current of transistor M1 at the baseband frequency, hence varying the operating conditions of M2, M3 at the baseband frequency during the injection locking. It results in the modulation of the RF current intensities through M2, M3. This has the effect of a multiplication of the LO signal amplitude by the baseband information. The binary data is therefore

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Fig. 2. Operation principles of the proposed zero-IF SOM.

up-converted through ASK modulation. As illustrated in Fig. 2, the up-converted signal is sensed at the output node Vn by an RF buffer comprising Mb1, Mb2, Lb1, Lb2, and Cb1. The output is matched to 50 for measurements purposes, but is intended to be matched to the transmitting antenna. Unlike a symmetric injection-locked frequency divider where mixing function is mainly performed by the input transistor, the proposed SOM topology allows the input transistor (M1) to act as a transimpedance amplifier, therefore it can receive and inject a small signal into the tank. III. ANALYTICAL EXPRESSIONS ZERO-IF SOM OPERATION

FOR

In this section, we first analyze the SOM’s conversion gain as a function of circuit design parameters, dc power consumption, and the injected signal parameters such as the modulation index (during reader-to-tag communications), then we analyze the tradeoff between up-converted sidebands power levels and circuit design parameters, as well as the dc power consumption (during tag-to-reader communications). Fig. 3(a) depicts a simplified SOM model used in this section. Components are approximated as (1) (2) (3)

Fig. 3. (a) Zero-IF SOM simplified model. (b) Spectrum of the injected signal during reader-to-tag communication. (c) Spectrum of signal during tag-to-reader communication.

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(7) is the generated LO signal (the SOM natural oscillation frequency). and , and , and and are the amplitudes and frequencies for the above-defined signals. The received signal from the reader can be expressed as

Fig. 4. Operating condition of cross-coupled pair transistors when biased close to their threshold voltage and their respective parasitic capacitors.

(8) The received AM modulated signal (8) injects a current

(4)

(9)

where (the loading inductance) and (the loading capacitance) form the resonator, is the natural oscillation frequency of the SOM, represents the total tank losses, is the varactor capacitance, is the inductor series resistance, and represents the total parasitic capacitance that loads the tank. As illustrated in Fig. 4, the total parasitic capacitance is mainly dominated by parasitic capacitors of the cross-coupled pair transistors M2 and M3, and the parasitic capacitors of the loading transistor M1 and output buffer transistor Mb1 (Fig. 2). The negative transconductance performs two functions: first, it provides a negative resistance to compensate the tank losses and therefore allows a sustained oscillation. Second, as the cross-coupled pair transistors M2 and M3 act as switches, they intrinsically perform the mixing function (self-mixing). In the receiving mode (when the SOM is used to demodulate the millimeter-wave signal from the reader), corresponding to the frequency spectrum in Fig. 3(b), the injected current is an AM modulated signal, with a carrier frequency that locks the SOM and sidebands frequency contents ( ) bearing the information to be recovered by the tag ( is a modulation index). In the transmitting mode (when the SOM is used to up-convert the baseband information to be sent to the reader), the injected current is the sum of the RF signal from the reader at frequency for injection-locking and the data signal from the tag at baseband frequency . The corresponding frequency spectrum is illustrated in Fig. 3(c). In both modes, the modulating signals at baseband frequencies and are considered as sinusoidal signals to simplify the analyses in the next section.

into the tank through the transistor M1, which acts as a transimpedance amplifier, being its small signal transconductance. As illustrated in Fig. 4, the injected current (9) in return injects a voltage

A. Conversion Gain of SOM During Reader-to-Tag Communications Assuming that (5) is the injection-locking carrier signal from the reader, (6) is the data signal for the tag and

(10) across the tank. Assuming that the SOM is locked by since ,

) (11)

and (10) becomes (12) As shown in Fig. 4, the total voltage across the tank has two components: one is , at frequency , and which is generated by the SOM under injection locking, and the other is the AM modulated signal centered at . The modulated gate–source voltage periodically swings M2, M3 transistors forth and back between the saturation and triode regions. Frequency mixing occurs due to the modulation of transconductances of M2 and M3 transistors. The quiescent gate–source voltages of pair transistors M2 and M3 are close to the threshold voltage , a region where is the most sensitive (nonlinear variations) to the externally injected signal. Note that, to simplify the analysis, M2 and M3 junction capacitances are not taken into account since they have a small variation range. The output conductances are also neglected, given the fact that ,( being the saturation drain–source voltage of M2,M3), hence the output conductance has much less contribution to mixing over transconductances . It is also worth noting that, since and of (8) is considered as small signal, transistor M1 remains in the saturation region and permanently injects current of (9) into the tank. Drain current, for example, of M3, as illustrated in Fig. 4, can be expressed as (13)

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with (14) (15) is the transconductance parameter of M3, is the dc bias voltage at the common node (M2, M3 drains), and are defined in (12) and (7), respectively, and is the threshold voltage. Replacing (15) into (13), the drain current can be approximated as Fig. 5. Zero-IF current and loading condition.

(16) with the mixing term (17) Replacing

in (17) by (12), (18)

Replacing and in (18) by (8) and (7), respectively, the mixing term can be derived as

(23) As discussed earlier, the only voltage across the common node results from the zero-IF current component, expressed by (23). Therefore, Fig. 5 may be used as a small-signal output circuit representation. Any LO leakage due to the asymmetry in the differential outputs (due to layout and process variation) and the unfiltered RF signal at are considered as noise, and determine the lower detectable limit of the down-converted baseband. From Fig. 5, transistor M4 then operates simultaneously as a current source for the SOM and an active load for the down-converted baseband signal. Assuming that the parasitic capacitance at is small and has less impact on the baseband frequency, the zero-IF voltage can be defined as

(19) (24) By expanding (19) through trigonometric identities, it may be shown that, besides the down-converted baseband signal, the drain current also contains the fundamental, up-converted sidebands, and second-order harmonics of the RF signal. The resonator filters out higher order harmonics, and the virtual ground at in Fig. 2 filters out the second-order harmonic and its up-converted sidebands, but the circuit topology also allows a baseband signal amplification at the zero-IF output (at ). Accordingly, after the expansion of (19) and considering only the mixing terms that contain the information signal , (19) is simplified to

with (25)

(26) where is the channel-length modulation of the transistor M4. Combining (23) and (26), the down-converted zero-IF voltage of (24) can be written as (27)

(20) In (20), it can be observed that the down-converted baseband current (zero-IF current) is expressed as (21)

(28)

with (22) By replacing is derived as

Small tuning varactors are used only to compensate small frequency variations because of process and temperature variations. Hence, the tank quality factor is mainly dominated by the inductor losses, and we can approximate

in (21) by (22), the baseband current of (21)

in (27) by (28), the recovered baseband signal Replacing can be expressed as (29)

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Voltage conversion gain can be deduced from the ratio between the amplitude of the down-converted baseband and the amplitude of the injected carrier signal as (30) For the purpose of this analysis, we define the modulation index of the injected signal as (31) The conversion gain in (30) may then be estimated by

(32) According to (32), apart from the fact that increasing the inductor quality factor pushes the conversion gain up, this gain is also dependent on a design tradeoff, function of the channel length modulation coefficient of the PMOS current source (M4), its bias current, the bias current of M3 (through parameter ), and the amplitude of the oscillator’s signal (related to by (22)). For example: 1) to increase CG through , larger may be used, resulting in higher quiescent current , until the point where any further increase of will cause (which supplies M2,M3) to be high enough to start reducing CG again (besides, note that a larger induces more losses and that may cause the insufficient loop gain to start oscillation); 2) can be enhanced by increasing the overdrive voltage ( ) or larger , again implying a more power consumption; and 3) increasing implies an increase of dc power consumption as well. To the other extremity, a certain minimum of dc current is needed to guarantee sufficient in order to meet the SOM startup condition. Besides the tradeoffs between CG and dc power, (32) reveals that once bias conditions are set, the SOM conversion gain is proportional to the modulation index , as defined in (31) for the injected and modulated signal , independently of its carrier signal power. In other words, once the SOM is injection locked, any additional injected power, but with no increase in modulation index, does not improve the conversion gain. Fig. 6 illustrates the operating conditions of the SOM. An extremely low-power externally injected in-phase energy ( signal) is required to relax the negative transconductance ( ) and trigger oscillation. Fig. 7 shows the down-converted signal at the common node. When , the baseband signal is successfully recovered [see Fig. 7(a)]. However, when , the output is a noise of low-frequency components [see Fig. 7(b)]. B. Up-Converted Sideband Power of SOM During Tag-to-Reader Communications

Fig. 6. Simulated results that demonstrate the operating conditions of the SOM signal. with and without

Fig. 7. Simulated results of the recovered (down-converted) baseband signal at zero-IF output pad, when an AM signal, modulated by a random signal, is injected into the SOM.

The tag communicates back to the reader by up-converting its data

using the SOM mixing function. and are the amplitude and frequency of the baseband signal, respectively. In consistency with the frequency spectrum in Fig. 3(c), the injected signal can be expressed as

(33)

(34)

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Fig. 8. Die microphotograph of the fabricated SOM. Fig. 10. SOM phase noise measured at signal. of the injected

pad for different power levels

Fig. 11. (a) Spectrum of AM signal, modulated by a 10-kHz square wave pad (Res BW 4.7 kHz, VBW 4.7 signal, and injected into the SOM at kHz). (b) Recovered down-converted baseband signal measured at zero-IF pad. Fig. 9. (a) Measurement setup. (b) Photograph of measurement setup and the probe station.

where ) is, this time, a CW injection-locking signal transmitted by the reader in order to stabilize and keep phase coherence between and . Assuming a linear amplification by

M1, the associated CW drain current in M1 at will induce an RF voltage across the tank only, given the virtual ground at (Fig. 2). The baseband component of the drain current in M1 at will induce a voltage across M4 only, given the negligible reactance of L1 at . Therefore, the injected voltage

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Fig. 12. Measured conversion loss versus injected power for different modulation index.

Fig. 15. Spectrum of the SOM measured at the pad, when a 1-MHz sinus wave emulating the tag’s data to be transmitted is injected into the SOM (Res BW 39 kHz, VBW 39 kHz).

The mixing term that stems from a quadratic relation between versus may be derived similarly as for (13)–(17) and is expressed as (36) Replacing

in (36) by (35) yields (37)

By keeping only the second term that contains the information signal , (38) Fig. 13. Measured and simulated conversion loss versus carrier-to-sideband signal. power ratio of the injected

which can be expanded to

(39) Combining (22), (26), and (28) with (39), the up-converted signal can be approximated by

(40) Similar to (32), (40) shows that the sideband power can be enhanced by increasing inductor quality factor and dc power consumption. IV. CIRCUIT DESIGN AND EXPERIMENTAL RESULTS Fig. 14. Measured and simulated conversion loss versus frequency of the mod. ulating signal

across the gate–source terminals of M3 may be approximated as the sum of these voltages,

(35)

A. Chip Design and Measurement Setup The proposed SOM was fabricated using a standard 65-nm CMOS process. Fig. 8 shows the die microphotograph with an area of 0.4 0.6 mm including RF pads. For a low-power design, the layout was optimized to minimize parasitic capacitances and the free-running tuning range was designed to only compensate frequency variations due to process variations. The sizes of M1 and Mb1 transistors were chosen to maintain as much symmetry as possible at the differential

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TABLE I PERFORMANCE SUMMARY AND COMPARISON OF SOMs

Fig. 16. Power link-budget of the proposed MMID tag-reader system.

output . Measurements were carried out on-wafer, and Fig. 9(a) shows (at a conceptual level) the measurement setup used. In the receiving mode (during reader-to-tag communications), a power signal generator (Agilent E8257D) that emulates the reader’s transmitter sends an AM modulated signal. The recovered data (down-converted baseband) is read by a digital oscilloscope (Agilent DSO-X3034A) with 1-M input impedance (emulating a digital buffer input impedance). In the transmitting mode (during tag-to-reader communications), a CW signal from the same power signal generator (Agilent E8257D) injection locks the SOM, and another power signal generator (Hewlett-3000A) emulates the tag’s data to be transmitted by injecting its data as well via a combiner to the SOM. The up-converted signal is received by a signal analyzer (Agilent PXA N9030A), which emulates the reader’s receiver. Fig. 9(b) shows a photograph of the measurement setup. B. Zero-IF SOM Performances Measurements were taken under 350- A bias current and 800-mV supply voltage for the core section (280 W), while 500 A was drawn by the output buffer from a 600-mV supply. In order to evaluate the SOM injection-locking characteristics, a 40-GHz signal with variable RF power was injected into the SOM through pad (Fig. 2), and phase noise was measured at the output pad (Fig. 2).Fig. 10 shows that: 1) the SOM phase noise is reduced as the power level of increases, and tends to a comparable phase noise level to that of and

48 dBm 2) when the injected power becomes very weak ( in our case), the SOM is no longer locked to the injected signal. Fig. 10, therefore, confirms the feasibility of using an extremely low-power and low-complexity millimeter-wave SOM with poor free-running phase-noise performances to perform zero-IF down-conversion with significantly enhanced spectral purity performances under injection locking. This is suitable for transceivers in self-powered and fully integrated MMID tags (for short-range communications). Fig. 11(a) shows the spectrum of an injected AM signal, which is modulated by a 10-kHz square wave. Fig. 11(b) shows the measured baseband at the output of the SOM (at the zero-IF pad). The 10-kHz modulating signal has been successfully recovered. Fig. 12 shows the measured conversion loss when the SOM is injection locked by an AM modulated signal with 40-GHz carrier frequency with a variable power and a variable modulation index . As predicted by (32), the results in Fig. 12, on one hand show that once the SOM is injection locked, any additional injected RF power is converted into losses rather than enhancing the conversion gain. On the other hand, the results confirm that for a fixed injected power, the conversion loss can be improved by increasing the modulation index of the received AM signal. In addition, the higher the modulation index is, the better the sensitivity of the SOM is to detect and down-convert weak received signals (in our case, dBm when the carrier is 90% modulated). Fig. 13 shows the measured conversion loss versus the ratio between carrier power and sideband power in the injected AM signal. It reveals that conversion loss can be enhanced by increasing the sideband power, i.e., by increasing the modulation index. This is consistent with the results in Fig. 12. Fig. 14 shows the conversion loss when the frequency of the modulating signal increases. It can be seen that as the modulating frequency increases, parasitic capacitance at the common node takes effect and the conversion loss slightly increases. However, these results suggest that the tag can be written or interrogated at a high data rate. Note also that the removal of the pad parasitic capacitor (at the zero-IF pad), which is there for measurement purposes, would significantly lower the total capacitance at . To evaluate the SOM’s tag-to-reader communication capability, a 1-MHz signal emulating the tag’s data to be transmitted was injected into the SOM, while the SOM was injection locked by a 40-dBm CW RF signal. Fig. 15 shows the spectrum of

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the up-converted signal, measured at the output pad . The measured output power is about 36 dBm, and after de-embedding the cable losses @ 40 GHz, the actual output power is about 29 dBm. As a two-way communication system, the operating range of MMID is shorter between the reader-to-tag and the tagto-reader communication range. However, for a wirelessly powered device (battery-free MMID tag in our case), the operating range is mostly limited by the capacity of a tag to harvest sufficient energy for its functioning (reader-to-tag communication range), rather than the reader’s sensitivity (tag-to-reader communication range). Therefore, based on the previous published results on the millimeter-wave/dc rectifier [8], and on-chip antennas [7], Fig. 16 presents a possible link power budget of the proposed MMID tag. With a 3-cm communication range and a 24-GHz powering signal [8], about 850 W @ 1 V, is rectified, i.e., a power level that is largely above the required SOM’s dc power. As illustrated in Fig. 16, for the SOM to receive 40-dBm injection-locking power within 3 cm @ 40 GHz, it also requires the reader to transmit almost 18 dBm. In the other direction, with 29-dBm power transmitted by the tag, the reader receives almost 51 dBm. Note that, a 1-W effective isotropic radiated power (EIRP) only of transmitted power [8], as considered in Fig. 16, to power up the tag is a conservative analysis case. Hence, increasing the reader’s transmitted power or the antenna gain will automatically increase the communication range. Therefore, the link power budget in Fig. 16 confirms the feasibility of the battery-free on-chip MMID tag proposed in this work (Fig. 1). Table I summarizes and compares performances of the previous published self-oscillating mixers with the zero-IF self-oscillating mixer proposed in this paper. V. CONCLUSION A low-power zero-IF SOM suitable for a self-powered MMID tag is proposed and analyzed. In addition to the SOM injection locked to the reader’s carrier frequency, operating the SOM’s cross-coupled pair transistors in a region where their transconductances are the most sensitive to the externally injected signal and providing proper isolation between the millimeter-wave and the down-converted baseband signal are the key factors to enable a low-power zero-IF SOM. Besides, the analysis detailed in this work reveals that the conversion loss significantly depends on how much the injected carrier signal is modulated (the modulation index value) and the SOM power consumption. A 40-GHz zero-IF SOM was fabricated in a standard 65-nm CMOS process, and a measured conversion loss of about 30 dB under 38-dBm injected RF power with a power consumption of only 280 and 580 W during the reader-to-tag and the tag-to-reader communication, respectively, supports the feasibility of the MMID tag-reader system proposed in this work. These results contribute to the demonstration of a potential for high data-rate RFID fully integrated on a single CMOS die with no external components. ACKNOWLEDGMENT The authors would like to thank CMC Microsystems, Kingston, ON, Canada, for their technical support, design tools,

and chip fabrication. The authors also acknowledge and thank J. Gauthier, Poly-Grames Research Center, for his help with measurements.

REFERENCES [1] M. Brandl et al., “A low-cost wireless sensor system and its application in dental retainers,” IEEE Sensors J., vol. 9, no. 3, pp. 255–262, Mar. 2009. [2] L. Yang, L. J. Martin, D. Staiculescu, C. P. Wong, and M. M. Tentzeris, “Conformal magnetic composite RFID for wearable RF and bio-monitoring applications,” IEEE Trans. Microw. Theory Techn., vol. 56, no. 12, pp. 3223–3230, Dec. 2008. [3] S. Amendola, R. Lodato, S. Manzari, C. Occhiuzzi, and G. Marrocco, “RFID tchnology for IoT-based personal healthcare in smart spaces,” IEEE Internet Things J., vol. 1, no. 2, pp. 144–152, Apr. 2014. [4] A. Zaric, C. C. Caruz, A. M. de Matos, M. R. da Silva, J. R. Costa, and C. A. Fernandes, “RFID-based smart blood stock system,” IEEE Antennas Propag. Mag., vol. 57, no. 2, pp. 54–65, Apr. 2015. [5] P. Pursula et al., “Millimeter-wave identification, a new short-range radio system for low-power high data-rate applications,” IEEE Trans. Microw. Theory Techn., vol. 56, no. 10, pp. 2221–2228, Oct. 2008. [6] P. Pursula, F. Donzelli, and H. Seppä, “Passive RFID at millimeter-waves,” IEEE Trans. Microw. Theory Techn., vol. 59, no. 8, pp. 2151–2157, Aug. 2011. [7] H.-K. Chiou and I.-S. Chen, “High-efficiency dual-band on-chip rectenna for 35- and 94-GHz wireless power transmission in 0.13- m CMOS technology,” IEEE Trans. Microw. Theory Techn., vol. 58, no. 12, pp. 3598–3606, Dec. 2010. [8] P. Burasa, N. G. Constantin, and K. Wu, “High-efficiency wideband rectifier for single-chip batteryless active millimeter-wave identification (MMID) tag in 65-nm bulk CMOS technology,” IEEE Trans. Microw. Theory Techn., vol. 62, no. 4, pp. 1005–1011, Apr. 2014. [9] S. Farzeen, G. Ren, and C. Chen, “An ultra-low power ring oscillator for passive UHF RFID transponders,” in 53rd Int. Midwest Circuits Syst. Symp., 2010, pp. 558–561. [10] U. Karthaus and M. Fisher, “Fully integrated passive UHF RFID transponder IC with 16.7- W minimum RF input power,” IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1602–1608, Oct. 2003. [11] J.-P. Curty, N. Joehl, C. Dehollain, and M. J. Declercq, “Remotely powered addressable UHF RFID integrated system,” IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 2193–2202, Nov. 2005. [12] J. W. Lee, N. D. Phan, D. H. T. Vo, and V. H. Duong, “A fully integrated EPC gen-2 UHF-band passive tag IC using an efficient power management technique,” IEEE Trans. Ind. Electron., vol. 61, no. 6, pp. 2922–2932, Jun. 2014. [13] J. Y. Kim and W. Y. Choi, “30 GHz self-oscillating mixer for selfheterodyne receiver application,” IEEE Microw. Wireless Lett., vol. 20, no. 6, pp. 334–336, Jun. 2010. [14] A. Liscidini, A. Mazzanti, R. Tonietto, L. Vandi, P. Andreani, and R. Castello, “Single-stage low-power quadrature RF receiver frontend: The LMV cell,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2832–2841, Dec. 2006. [15] H. K. S. Stanley and S. E. Carlos, “A low-noise self-oscillating mixer using a balanced VCO load,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 8, pp. 1705–1711, Aug. 2011. [16] B. R. Jackson and C. E. Saavedra, “A dual-band self-oscillating mixer for C-band and X-band applications,” IEEE Trans. Microw. Theory Techn., vol. 58, no. 2, pp. 318–323, Feb. 2010. [17] P. Burasa, N. G. Constantin, and K. Wu, “Low-power injection-locked zero-IF self-oscillating mixer for self-powered millimeter-wave identification (MMID) active tag in 65-nm CMOS,” in IEEE Radio Freq. Integr. Circuits Symp., Phoenix, AZ, USA, May 17–19, 2015, pp. 259–262. [18] B. Razavi, “A study of injection locking and pulling in oscillators,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1415–1424, Sep. 2004. [19] I. Ali, A. Banerjee, A. Mukherjee, and B. N. Biswas, “Study of injection locking with amplitude perturbation and its effect on pulling of oscillator,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 1, pp. 137–147, Jan. 2012. [20] E. Hegazi, H. Sjoland, and A. A. Abidi, “A filtering technique to lower LC oscillator phase noise,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1921–1930, Dec. 2001.

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Pascal Burasa (S’13) received the B.Eng. and M.A.Sc. degrees in electrical engineering from the École Polytechnique de Montréal (University of Montreal), Montreal, QC, Canada, in 2006 and 2008, respectively, and is currently working toward the Ph.D. degree at the Poly-Grames Research Center, École Polytechnique de Montréal. During his master’s study, he was involved with CMOS color image sensors without optic filters. From 2008 to 2010, he was a Research Associate with the Microelectronic Research Group, École Polytechnique de Montréal, where he developed CMOS color image sensors free of optic filters. His research interests focus on millimeter-wave integrated circuits, antenna-on-chip/antenna-in-package solution, and CMOS-based fully integrated microsystems for millimeter-wave identification and millimeter-wave radar technology.

Nicolas G. Constantin (S’04–M’09) received the B.Eng. degree in electrical engineering from the École de technologie supérieure (ÉTS), University of Quebec, Montreal, QC, Canada, in 1989, the M.A.Sc. degree in electrical engineering from the École Polytechnique de Montréal, Montreal, QC, Canada, in 1994, and the Ph.D. degree in electrical engineering from McGill University, Montreal, QC, Canada, in 2009. He is currently an Associate Professor with ÉTS. From 1989 to 1992, he was involved with the design of microwave transceivers for point-to-point radio links. From 1996 to 1998, he was an RF Design Engineer with NEC, Melbourne, Australia, where he was involved with the development of RF and microwave transceivers for mobile telephony. From 1998 to 2002, he was a Senior Design Engineer with Skyworks Solutions, Inc., Newbury Park, CA, USA, where he developed GaAs HBT RF integrated circuit (RFIC) power amplifiers (PAs) for wireless communications. While with Skyworks Solutions Inc., he was also actively involved in research on smart biasing and efficiency improvement techniques for RFIC PAs. He holds three patents. His primary research interests are in the design and test of RF and millimeter-wave integrated circuits (ICs) and front-end modules for wireless communications. Dr. Constantin was the recipient of a Doctoral Scholarship from the Natural Science and Engineering Research Council (NSERC) of Canada and a Doctoral Scholarship from ÉTS.

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Ke Wu (M’87–SM’92–F’01) received the B.Sc. degree (with distinction) in radio engineering from the Nanjing Institute of Technology (now Southeast University), Nanjing, China, in 1982, and the D.E.A. and Ph.D. degrees in optics, optoelectronics, and microwave engineering (with distinction) from the Institut National Polytechnique de Grenoble (INPG), Grenoble, France, and the University of Grenoble, France, in 1984 and 1987, respectively. Dr. Wu is currently a Professor of electrical engineering, Tier-I Canada Research Chair in RF and Millimeter-Wave Engineering, and NSERC–Huawei Industrial Research Chair in Future Wireless Technologies with the École Polytechnique de Montréal, Montreal, QC, Canada. He has been the Director of the Poly-Grames Research Center. He was the founding Director of the Center for Radiofrequency Electronics Research of Quebec (Regroupement stratégique of FRQNT). He has also held guest, visiting, and honorary professorships with many universities around the world. He has authored or co-authored over 1000 referred papers and a number of books/book chapters. He has filed more than 30 patents. His current research interests involve substrate integrated circuits (SICs), antenna arrays, advanced computer-aided design (CAD) and modeling techniques, nonlinear wireless technologies, wireless power transmission and harvesting, and development of RF and millimeter-wave transceivers and sensors for wireless systems and biomedical applications. He is also interested in the modeling and design of microwave and terahertz photonic circuits and systems. Dr. Wu is a Fellow of the Canadian Academy of Engineering (CAE) and of the Royal Society of Canada (The Canadian Academy of the Sciences and Humanities). He is a Member of the Electromagnetics Academy, Sigma Xi, and URSI. He has held key positions in and has served on various panels and international committees including the chair of Technical Program Committees, international Steering Committees, and international conferences/symposia. In particular, he was the General Chair of the 2012 IEEE Microwave Theory and Techniques Society (IEEE MTT-S) International Microwave Symposium (IMS). He has served on the Editorial/Review Boards of many technical journals, transactions, proceedings, and letters, as well as scientific encyclopedia, including as an Editor or Guest Editor. He was the Chair of the joint IEEE chapters of MTT-S/APS/LEOS, Montreal, QC, Canada. He is currently the Chair of the newly restructured IEEE MTT-S Montreal Chapter. He was an elected IEEE MTT-S Administrative Committee (AdCom) Member (2006–2015) and has served as Chair of the IEEE MTT-S Transnational Committee, Member and Geographic Activities (MGA) Committee and Technical Coordinating Committee (TCC) among many other AdCom functions. He was an IEEE MTT-S Distinguished Microwave Lecturer (2009–2011). He is the 2016 IEEE MTT-S President. He is the inaugural three-year representative of North America as a Member of the European Microwave Association (EuMA) General Assembly. He was the recipient of many awards and prizes including the first IEEE MTT-S Outstanding Young Engineer Award, the 2004 Fessenden Medal of IEEE Canada, the 2009 Thomas W. Eadie Medal of the Royal Society of Canada, the Queen Elizabeth II Diamond Jubilee Medal in 2013, the 2013 FCCP Education Foundation Award of Merit, the 2014 IEEE MTT-S Microwave Application Award, the 2014 Marie-Victorin Prize (Prix du Quebec—the highest distinction of Québec in the natural sciences and engineering), the 2015 Prix d’Excellence en Recherche et Innovation of Polytechnique Montréal, and the 2015 IEEE Montreal Section Gold Medal of Achievement.

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Dynamic Polarization Control of Two-Dimensional Integrated Phased Arrays Amirreza Safaripour, Student Member, IEEE, Steven M. Bowers, Member, IEEE, Kaushik Dasgupta, Member, IEEE, and Ali Hajimiri, Fellow, IEEE

Abstract—Simultaneous two-dimensional (2-D) beam steering and dynamic polarization control (DPC) of the radiated electric field in 2-D phased arrays ensure polarization matching between the transmitter and receiver antennas in both fixed and mobile wireless systems. Polarization matching is maintained regardless of the polarization, orientation, and location of the receiver antenna in space within the 2-D steering range of the transmitter. This work implements a fully integrated 2 2 DPC phased-array transmitter in a 32-nm CMOS silicon-on-insulator process, radiating at 122.9 GHz. It achieves a maximum effective isotropic radiated power of 12.3 dBm in the broadside direction and enables polarization angle control of the radiated linear and elliptical polarizations across the full range of 0 to 180 with tunable axial ratio down to 1.2 dB to achieve circular polarization and the ability to steer the radiated beam up to 15 in both dimensions. Index Terms—Antenna theory and design, beam steering, CMOS integrated circuits, electromagnetic (EM) polarization, EM simulation, integrated radiators, millimeter-wave (mm-wave) integrated circuits, on-chip antennas, phased arrays.

I. INTRODUCTION

P

OLARIZATION of electromagnetic (EM) waves is a significant property in wave propagation, which can be utilized in many wireless applications such as communications, radar, sensing, and imaging [1]–[6]. In communication systems, this parameter can be used to transmit and receive information with different polarizations to increase the channel capacity over the same frequency band by adjusting the transmitting and/or receiving antennas for one or the other polarization(s). Polarization is also important in the transmission of radar pulses and reception of radar reflections due to the partially polarized nature of reflections from different objects. This additional information, which is carried by the polarization of the EM waves, can also be used in sensing and imaging applications.

Manuscript received August 10, 2015; revised December 10, 2015; accepted February 05, 2016. This paper is an expanded version from the IEEE RFIC Symposium, Phoenix, AZ, USA, May 17–19, 2015. A. Safaripour and A. Hajimiri are with the Department of Electrical Engineering, California Institute of Technology, Pasadena, CA 91125 USA (e-mail: [email protected]). S. M. Bowers was with the Department of Electrical Engineering, California Institute of Technology, Pasadena, CA 91125 USA. He is now with the Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA 22904 USA. K. Dasgupta was with the Department of Electrical Engineering, California Institute of Technology, Pasadena, CA 91125 USA. He is now with the PHY Research Laboratory, Intel Corporation, Hillsboro, OR 97124 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2530704

With recent advancements in silicon processes and scaling of transistors that enable designers to implement very high-frequency millimeter-wave (mm-wave) systems in silicon-based integrated circuits [7]–[10], a wide range of opportunities has opened up to integrate transmitting/receiving antennas on the same substrate as the wavelength becomes comparable to the dimensions of the chip at these frequencies. In addition to serving as an alternative to the traditional power transfer methods such as wirebond and flip chip that become increasingly lossy at high mm-wave frequencies [11], [12], this opportunity allows us to implement integrated transmitters and receivers at these frequencies [13]–[23] even beyond the frequency limit ( ) of the integrated circuit technology [24]–[28], which, in turn, allows implementation of such wireless systems that utilize polarization information on an integrated platform. Polarization of the EM waves is usually enforced by the transmitting and receiving antennas in the system since they are often intrinsically polarized based on their specific physical shape and particular orientation in space. On the other hand, the significance of polarization in the proper operation of wireless systems emphasizes both the importance of polarization control over the transmitted EM waves and the polarization matching between the transmitter and receiver antennas in the system. In a wireless link, any mismatch between the polarizations of the transmitter and receiver antennas results in additional power loss on top of propagation path loss of the radiated EM waves. One possible scenario where polarization mismatch could happen is when the transmitter and receiver antennas have inherently different polarizations. For example, the transmitted signal of a vertical linearly polarized antenna is only polarization matched to a vertical linearly polarized receiver antenna and if the receiver antenna has horizontal linear polarization or circular polarization, full polarization mismatch or partial polarization mismatch would happen, respectively. Additionally, even if the transmitter and receiver antennas are polarization matched, the receiver could still move with respect to the transmitter or change orientation and cause polarization mismatch. An example of this second scenario is a two-dimensional (2-D) phased array of the same vertical linearly polarized transmitter antennas that can track a vertical linearly polarized receiver with the correct polarization only if the receiver antenna remains aligned with the transmitting antennas. When the linearly polarized receiver changes its orientation as it moves around, the transmitter would no longer be able to match the polarization due to orientation mismatch. A 2-D phased array of dynamic polarization control (DPC) antennas [29] can solve both of these issues at the same time, as is shown in Fig. 1. A unit DPC antenna can radiate any

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Fig. 1. (a) DPC antenna ensures polarization matching between the transmitter and receiver regardless of receiver antenna type and (b) solves polarization mismatch in mobile systems when used in 2-D phased arrays.

polarization to match the receiver’s need and avoid additional power loss due to polarization mismatch. For instance, a DPC antenna can be used in the first scenario of the previous example to transmit vertical polarization, horizontal polarization, and circular polarization to ensure polarization matching for all three receiver antennas, as depicted in Fig. 1(a). Moreover, a 2-D phased array of DPC antennas, such as the one in Fig. 1(b), can steer the radiated beam in either dimension while simultaneously adjusting the transmitted polarization to follow both the location and the orientation of the receiver in space to maintain polarization match. This paper presents a fully integrated 2 2 DPC phased array radiating at 123 GHz fabricated in IBM’s 32-nm CMOS silicon-on-insulator (SOI) process. The 2 2 DPC array enables full control over the polarization of the radiated signal and 2-D beam steering at the same time. In addition to the details provided in [29], this paper covers extensive EM simulation results verifying the qualitative explanation of the design procedure for the modified DPC antenna. It also provides simulation results for the individual circuit blocks presented in [29], as well as the details of the design of the rest of the circuitry, including the locking network and actuators, supported with simulation results. Details of the measurement setup and measurement procedures including an expanded explanation of the optimization algorithm to find the desired polarization and beamsteering settings are also included. Additional measurement results representing simultaneous polarization control and 2-D beam-steering capability are also added for a better demonstration of the system’s performance. This paper is organized as follows. Section II presents the architecture of the system, simulation results, and the details of both EM and circuit design. After that, the measurement setup, procedures, and results for the fabricated chip are presented in Section III before this paper is concluded in Section IV. II. SYSTEM ARCHITECTURE AND DESIGN The simplified block diagram of the 2 2 DPC integrated phased array is shown in Fig. 2. It consists of four independent DPC antennas, meaning that each antenna element on its own is capable of DPC of its radiated EM waves, independent of the rest of the antennas in the array. Each individual DPC antenna

Fig. 2. Block diagram of the 2

2 DPC integrated phased array.

uses its own drive circuitry, running at 123 GHz, and incorporates two independent sets of phase and gain control units to set the desired phases and amplitudes for the antenna drives. Frequency synchronization of the four radiating antennas is performed by a central quadrature voltage-controlled oscillator (QVCO) that provides the reference quadrature signals, which are also used for phase control units in each core. These quadrature signals are distributed from the central QVCO to the four radiator cores by a locking network consisting of multiple buffer stages and transmission-line sections. A. DPC Antennas A DPC antenna is a multi-port driven (MPD) [20] ring antenna with four ports that are driven against a set of orthogonal ground spokes. The original structure of the DPC antenna, which was introduced in [30], is shown in Fig. 3. The drive circuitry that generates the four required excitation signals to drive the ring at the four ports is located in the center ground plane of the antenna. Each pair of opposing ports in the antenna is driven differentially as a subpart against their corresponding ground spokes, with adjustable amplitude and phase, which are independent of those of the other subpart pair of ports. This allows each DPC antenna to radiate two linear polarizations, aligned with the ground spokes and orthogonal in space, in the far field. The amplitudes and the relative phase difference of these two polarizations can be arbitrarily adjusted by the phase and gain control units of the antenna. Thus, the overall polarization of each DPC antenna is set by the superposition of these two orthogonal linear polarizations. The general form for this polarization is elliptical polarization, as depicted in Fig. 4(a), where the electric field travels in an elliptical trajectory. This ellipse is characterized by two parameters: Polarization Angle (P.A.), which is the angle of the major axis of the ellipse and Axial Ratio

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Fig. 3. Operation principle of the original DPC antenna based on superposition of two orthogonal linear polarizations.

Fig. 4. (a) Definitions of the polarization parameters for the general elliptical polarization and its realization with two orthogonal linear polarizations, as well as (b) graphical representation of the extreme cases of linear and (c) circular polarizations.

(A.R.) defined as the ratio of the major and minor axes. Shown in Fig. 4(a), any arbitrary choice of amplitudes and phases for the two subparts ( , , , and ) would result in a specific set of values for the polarization angle and axial ratio and determines the net polarization of each DPC antenna, which could range from linear polarization ( ) at any desired polarization angle, illustrated in Fig. 4(b), to circular polarization ( ), shown in Fig. 4(c), based on the relative phases and amplitudes of the two drive sets. Since the DPC antennas are used in a 2 2 array, proper operation of the entire radiator array is achieved when all four antennas radiate the same polarization, i.e., the same ratio of and the same phase difference of for the drive circuitry of all antennas. However, the relative phase differences between the four DPC antennas, as well as their relative amplitudes, can be arbitrarily adjusted to allow 2-D steering of the radiated beam. In a DPC array, in order to synchronize the frequency of operation and also to provide a phase reference for each element, central locking signals must be routed to the inside of each core. In [30], one of the four ground spokes was assigned to route the locking signals underneath the ground since the topside was

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Fig. 5. Modifications of the DPC antenna by adding two additional ground spokes to allow low-loss transmission lines for the locking signals while maintaining the symmetry of the structure.

already used for antenna feed lines. This requires use of thin low-metal layer lossy transmission lines for the locking signals. To alleviate this issue in this work, a 5th ground spoke dedicated to the distribution of the locking signals is added to allow routing thicker transmission lines above the ground spoke with less loss, as shown in Fig. 5. This spoke is still orthogonal to the antenna ring to minimize the mirror currents and the effects on the radiation pattern. However, the 5th spoke introduces some undesired asymmetry into the antenna structure. Thus, a 6th spoke is also added orthogonal to the 5th one and the ring to preserve the symmetry of the structure such that one polarization would not be favored over the other one. The DPC antennas are realized on the top 2.275- m-thick aluminum layer with 12- m-wide lines. The periphery of each antenna is 1730 m with 1400- m center-to-center separation between two adjacent antennas. The delay-matched feed lines within each antenna that connect the output stages to the four antenna ports extend an overall length of 420 m and are implemented with multiple transmission-line sections on the top three metal layers due to layout considerations. The four original ground spokes are 30 m wide while the 5th and the 6th spokes are 24 m wide and the ground plane is spaced 150 m away from each antenna. The radiator chip is designed to radiate from the topside. For this purpose, it is mounted on a printed circuit board (PCB) ground plane. Due to higher dielectric constant of the substrate, most of the power initially radiates down towards the lower ground plane and gets reflected back. However, the substrate is about a quarter-wavelength thick, which allows the reflected signal to add constructively with the initial topside radiated waves to form the overall topside radiation. The entire 2 2 radiator array is simulated with the ANSYS HFSS 3-D EM solver. Figs. 6 and 7 demonstrate the effects of the two additional ground spokes on the performance of the array in the broadside direction by comparing the simulated results for five- and six-spoke DPC antenna arrays against the theoretical superposition of two ideally expected orthogonal linear polarizations for different drive settings. It should be noted that these simulations solely evaluate the performance of the standalone EM design under ideal drive settings in the absence of drive circuit nonidealities. They investigate how close to ideal

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Fig. 8. Simulated antenna gain patterns for the 2 2 DPC radiator array in circularly polarized mode and linearly polarized mode for planes: (a) and (b) show maximum gain of 0.4 dBi in the broadside direction.

Fig. 6. Effects of the 5th and 6th ground spokes on polarization angle tuning. (a) Polarization angle is set by the drive settings and the (b) simulated polarization angle, (c) axial ratio, and (d) antenna array gain show more accuracy and symmetry for six-spoke DPC antennas.

Fig. 7. Effects of the 5th and 6th ground spokes on axial ratio tuning. (a) Axial ratio is set by the phase difference of the drive sets, and the (b) simulated polarization angle, (c) axial ratio, and (d) antenna array gain show more accuracy and symmetry for six-spoke DPC antennas.

the summation of two orthogonal linear polarizations is performed and how uniform the antenna array gain behaves for different settings. Fig. 6(a) shows a scenario where the relative amplitudes of and and the phase difference are set based on the theoretical summation for all four antennas to ideally achieve uniform polarization angle tuning from 0 to 180 with steps of 15 . In Fig. 6(b), the simulated polarization angles corresponding to these settings for the DPC arrays with five spokes and six spokes are plotted and compared with the ideal goal that is mathematically expected from these settings, which reveals the advantage of adding the 6th spoke to achieve more accuracy in polarization angle tuning due to more symmetry in the structure. Furthermore, the achieved axial ratios for the linear polarizations are much higher in the presence of the 6th spoke, as shown in Fig. 6(c), resulting in closer-to-ideal

linear polarizations where infinitely large axial ratios are expected. Also, the antenna gain variation for the entire 2 2 array is much smaller for the six-spoke antennas, as ideally uniform antenna gain is expected for all settings (i.e., all polarization angles). This can be seen in Fig. 6(d) where the simulated gain of the array for both cases of five- and six-spoke antennas is shown. A similar set of simulation results are shown in Fig. 7 where the phase difference is swept from 0 to 360 while the amplitudes and are kept equal. This would ideally result in tuning the axial ratio by changing the radiated polarization from linear polarization to circular polarization while keeping the polarization angle constant at 90 (for to ) and then from circular polarization back to linear polarization with a constant polarization angle of 0 (for to ). The reverse scenario with reverse handedness happens for to , as depicted in Fig. 7(a). Similar to the previous set of simulations, a comparison of the simulated polarization angle, axial ratio, and antenna gain for the five- and six-spoke DPC antenna arrays against the theoretically expected values, as shown in Fig. 7(b)–(d), proves that the 6th ground spoke improves the performance by achieving very accurate polarization angles and axial ratios and a uniform antenna gain for different values of with less than 0.1-dB variation. The maximum simulated gain of the 2 2 DPC array in the broadside direction for both linear and circular polarizations is 0.4 dBi with 7% radiation efficiency. However, it should be noted that all antenna feed lines, their crosses, and meandering for delay matching, as well as the matching networks for the output stages are all included in these EM simulations. The simulated gain patterns of the array for both linear and circular polarization modes are shown in Fig. 8. B. Antenna Drive Circuitry Fig. 9 demonstrates the details of the drive circuitry for each antenna element. The power is generated locally by two differential oscillators. The quadrature lines from the locking network drive two phase rotators and each phase rotator generates a differential current with the desired phase through proper weighted summation of in-phase (I) and quadrature (Q) components. This differential current is then injected into the corresponding oscillator to lock its frequency and control the phase. The differential output of each oscillator goes through a buffer chain with gain control before feeding the antenna at the corresponding

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Fig. 11. Simulated output power of the two oscillators of the drive circuitry as the phase difference between them is controlled form 0 to 180 by the phase rotators, as well as examples of time-domain waveforms for two cases.

Fig. 9. Detailed block diagram of the drive circuitry for each DPC antenna with independent phase and gain control units for the two subparts, as well as independent control for each antenna with respect to the other antennas in the array.

Fig. 12. Schematic of the buffer chain that controls the gain of each subpart in the antenna drive circuitry with a maximum simulated gain of 10.2 dB.

Fig. 10. Schematics of each phase rotator and its corresponding oscillator that m, m, and form the phase control mechanism ( m). The differential output current of the phase rotator is directly injected into the oscillator output nodes to lock the phase and frequency.

ports. The supply voltage for each core’s analog drive circuitry is 1.25 V. 1) Phase Control: Each phase rotator consists of two Gilbert cells whose outputs are added in the current domain to generate a differential current with the desired phase [31]. The differential current is directly injected into the output nodes of the differential cross-coupled oscillator and locks its output at the desired phase and frequency. The schematic of one phase rotator-oscillator pair is shown in Fig. 10. The plot in Fig. 11 shows the simulated output power of the two oscillators as the phase difference between them is controlled from 0 to 360 by the phase rotators. Time-domain waveforms for the two cases of 90 and 180 are also shown on the same plot. Each differential oscillator and its corresponding phase rotator draw 43 and 12 mA of dc current, respectively, in simulation. 2) Gain Control: Each oscillator of the core drive circuitry is followed by one buffer chain. This allows independent gain control for each subpart. It also provides isolation between the oscillators and the antenna, minimizing the effects of antenna

input impedance variation due to different drive settings on the frequency and the output power of the oscillators. The schematic of one buffer chain and its simulated gain are shown in Fig. 12. The buffer chain consists of three cascode stages with m, m, and m. The matching network inductors between the stages are realized with shorted transmission lines with lengths/widths of 80 m 4 m, 65 m 5 m, and 85 m 5 m for , , and , respectively, and the values for ac coupling capacitors, which also contribute to impedance matching are fF, fF, and fF. The overall gain of the chain is controlled by the bias adjustments of the input gates of the three stages through biasing resistors k . Simulations of different settings show a maximum gain of 10.2 dB for each chain when loaded with the nominal antenna impedance with the three buffers drawing 17-, 34-, and 51-mA dc currents, respectively, for the maximum gain case. Although the two subparts should ideally be completely isolated from each other to allow independent control over each subpart’s polarization, in practice their undesired interaction through the DPC antenna can cause imbalance both in their own circuitry and relative to each other, which, in turn, could introduce error to the overall polarization. To better demonstrate this phenomenon, we investigate the effects of such an

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Fig. 14. Block diagram of the locking network.

Fig. 13. Variations of the single-ended input impedances of the DPC antenna when and (b) when for: (a) .

interaction on the single-ended antenna input impedances for each subpart ( , , , and ) in one of the antennas. Since the feed lines for these four driving ports are routed in different ways (two of them cross each other while the other two do not), the input impedances behave slightly differently as the drive settings change. Fig. 13(a) shows how the simulated input impedances for each antenna port of one of the DPC antennas change on the Smith chart as the relative phase difference between the two subparts, , is swept from 0 to 360 by the phase rotators for all four antennas. In Fig. 13(b), the single-ended input impedances for the same DPC antenna are simulated when the two subparts are driven in phase, but their amplitude ratio, , is changed from 0.2 to 5 for all antennas. As can be seen in these figures, the variations in the drive settings would cause the antenna input impedances that load each subpart’s output stage to deviate from the optimal impedance, which, in turn, reduces the gain and the output power that is delivered to the antenna by each subpart. It should be noted that these two scenarios are not the only possible cases and, in practice, both the relative phases and the relative amplitudes could change while switching to a certain polarization and cause deviations from nominal impedances. In addition to the subparts’ interaction through the antenna, they could also affect each other through parasitic and EM coupling that happen in the drive circuitry and could potentially cause both gain and phase errors. Based on the implemented layout, the most likely location for the strongest coupling is the

center of each DPC antenna where the phase rotators and subparts’ oscillator are located close to each other. However, simulations show that the parasitic coupling between the two subparts ( ) at the output of the phase rotators is below 36 dB and the EM coupling between the oscillators’ inductors is also less than 51 dB for all combinations of , which are both negligible compared to the strength of the injected signal into the oscillator. C. Locking Network Generation and distribution of the reference quadrature signals to the radiator cores are performed by the locking network. It takes the quadrature signals from the central QVCO, distributes and splits them to feed the drive circuits of the four antennas. The amplification, distribution, and splitting are done in a distributed fashion through five stages of amplification, with two “T” splits after the first and third stages, as shown in Fig. 14. The buffer stages in this network are the same cascode stages as the ones used in each core’s buffer chain, and all transmission-line sections are realized on the top aluminum layer with 5- m-wide lines. Each transmission-line section between the amplifiers stages is used both for physical distribution to the fixed locations of the four radiator cores, as well as for impedance matching, with transmission-line stubs used at both the input and output of the amplifiers for matching and biasing, and metal ac coupling capacitors that allow independent dc voltages for the drains of the output transistors of each cascode stage and the gates of the input transistors of the following cascode stage. To minimize the dc power consumption of the initial amplifying stages while allowing for higher RF power on the later stages, the amplifying transistors scale up from the 1st to 5th amplifying stage, with 20- m-wide, 16- m-wide ( 2),

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Fig. 15. Schematic of the central QVCO and its simulated time-domain output waveforms.

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Fig. 16. Schematics of the 5-bit DACs with: (a) single-ended and (b) differential outputs, as well as the: (c) simulated output voltage for the single-ended DAC and (d) differential DAC .

D. Actuators 20- m-wide ( 2), 20- m-wide ( 4), and 40- m-wide ( 4) transistors used in the 1st through 5th amplifying stages, respectively, for each differential output of the QVCO, with 2 of the 2nd and 3rd stages, and 4 of the 4th and 5th stages due to the power-splitting “T” sections after the 1st and 3rd amplifying stages. The simulated dc current consumption for each of the 16-, 20-, and 40- m-wide buffers are 14, 17, and 34 mA, respectively. The input gate bias of the cascode stages can be controlled to adjust the gain such that enough power is delivered to saturate the inputs of the phase rotators within the radiating cores with some margin for additional losses due to variations or modeling inaccuracies that might cause slight impedance mismatches between stages. The quadrature signals that feed the distribution network are generated by the central QVCO. The schematic of the QVCO is shown in Fig. 15. It uses simultaneous coupling through the tail resistive network ( ) in addition to the basic quadrature coupling transistors ( with m), which are used in conventional QVCOs [32]. More details about the operation principle and advantages of this architecture can be found in [19]. The QVCO inductors are designed and modeled based on the technique introduced in [23] resulting in an equivalent tank inductance of pH, and the varactors are realized by 10- m-wide thick-oxide NMOS transistors. Simulated tuning range for oscillation frequency of the QVCO, which synchronizes all the elements in the array, is from 120.1 to 121.8 GHz (from 122.9 to 124.7 GHz in measurement) and it generates 7.4 dBm of output power per quadrature line while drawing 90 mA from the power supply. The simulated time-domain waveforms of the QVCO quadrature outputs are also shown in Fig. 15. The supply voltage for the QVCO and all the buffers in the locking network is 1.4 V.

Digital-to-analog converters (DACs) are used as actuators to set the control voltages for the gain and phase control units in the antenna drive circuitry, as well as for the biasing control in the locking network. 5-bit weighted current mirror based DACs were implemented for the gate voltage controls. Fig. 16(a) shows the circuit schematic of the single-ended DAC where cascode current mirrors are utilized for higher output resistance and to ensure monotonicity. The same architecture followed by a current-mode single-ended to differential converter is implemented to form DACs with differential outputs, as depicted in Fig. 16(b). The single-ended DACs were designed to be able to cover voltage ranges for both common-source, as well as any cascode devices that need bias control. Simulation results, shown in Fig. 16(c), reveal good linearity over a full range from 0 to 1.5 V and an average least significant bit (LSB) of 50 mV. Differential DACs were designed to be used for differential control of the Gilbert cell tail currents in the phase control units. The simulated output of the differential DACs is shown in Fig. 16(d). Both DACs use 1.8-V supplies. The differential DAC also uses 1.2-V supply for the single-ended to differential conversion. III. MEASUREMENTS A. Measurement Setup The 2 2 DPC radiator array is fabricated in IBM’s 32-nm CMOS SOI process and occupies an area of 2.85 2.85 mm . It is mounted on a PCB and is attached to a 2-D stepper motor to allow antenna pattern measurements, as shown in Fig. 17. The radiated signal is received by a 22.7-dBi gain horn antenna,

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Fig. 17. Measurement setup for the 2 2 DPC radiator array. A 2-D stepper motor on the transmitter side and a 1-D stepper motor on the receiver side allow independent polarization measurement of the radiated signal at any desired direction.

Fig. 19. Die photograph of the 2

Fig. 18. Definitions of the angles , , and that are controlled by the stepper motors. and are controlled by the 2-D stepper motor on the transmitter side and is controlled by the 1-D stepper motor on the receiver side.

which is mounted on another stepper motor to allow polarization measurement of the radiated signal by the linearly polarized horn antenna in any arbitrary direction that is set by the 2-D stepper motor on the transmitter side. The simplified diagram in Fig. 18 shows the definitions of the angles , , and that are controlled by these two stepper motors and are frequently used in the measurement results section. Angles and are set by the 2-D stepper motor and determine the direction at which the receiver antenna picks up the radiated signal and the angle is swept by the 1-D stepper motor on the receiver side to measure the polarization parameters of the transmitted EM waves by the linearly polarized receiver. The received signal is downconverted by a 10th harmonic mixer, and then amplified by IF amplifiers. The downconverted IF signal is then fed either to a spectrum analyzer or an IF power sensor for spectrum or power measurements, respectively. The entire setup is calibrated with a PM4 Erikson Calorimeter. The overall power consumption of the chip is 1.885 W with 1.726 W for the radiator analog circuitry from 1.25- and 1.4-V supplies and 159 mW for the DACs and the digital interface. The die photograph of the radiator is given in Fig. 19. B. Optimization Process In order to find the proper settings for the actuators of each antenna’s drive circuitry to radiate the desired polarization in the target direction, an off-chip gradient-descent-based optimization algorithm is used. With such an algorithm, possible deviations in the actuators’ values from the required theoretical

2 DPC radiator array.

settings that could happen due to process variations, delay mismatch between transmission lines, and modeling inaccuracy can be compensated for. The goal of the optimization process is to radiate the desired polarization in a specific direction. The target direction is set by the given and , which could be broadside ( ) or any off-axis direction within the 2-D steering range of the radiator array. Once the direction is set, two orthogonal planes of and are picked for antenna pattern measurement during the optimization process. Starting from an initial setting, each iteration includes measuring the polarization parameters (i.e., axial ratio and polarization angle), as well as the radiation patterns across these two orthogonal planes by sweeping from 0 to 180 and from 90 to 90 for and . In order to find the setting for the next iteration, all the actuators of the drive circuits of the four antennas are both increased and decreased one at a time by a predefined step size and the polarization parameters and radiation patterns are measured again and the setting, which results in the largest improvement in the goal function (depending on the desired polarization type and the target direction), is picked as the next state. The same procedure is done until no further improvements can be made by changing any of the DACs’ values. The step size of the actuators should be sufficiently large so that the change they introduce into the radiated polarization and radiation pattern can be reliably captured by the measurement setup so that the algorithm does not lose the optimization path due to the noise. For linear polarization as the target, the optimization goal is to maximize the axial ratio at the desired polarization angle and the radiated power in the desired direction. In this procedure, the goal function is defined as a combination of the axial ratio, the radiated power in the desired direction, the difference of the measured polarization angle from the desired angle, and the deviation of the radiated beam from the target direction based on the pattern measurements in the two chosen orthogonal planes. With such a goal function, even if during an iteration no setting results in the desired polarization angle and/or beam direction, still the closest angle and/or direction with the highest axial ratio

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Fig. 21. (a) Ideal scenario for polarization angle tuning of the linear polarization across the full 0 to 180 range and (b) measured axial ratio for the optimized linear polarizations at different polarization angle.

Fig. 20. (a) Measured calibrated spectrum of the radiated signal and (b) measured radiation patterns in two orthogonal planes show a tone at 122.88 GHz with a maximum EIRP of 12.3 dBm in the broadside direction.

and radiated power is picked as the next state, as long as it provides improvement over the current setting. For an elliptical polarization with a desired axial ratio, polarization angle, and direction, we start the optimization process with an already optimized linear polarization with the same polarization angle and beam direction as the initial point (to ensure not only the polarization angle and beam direction are correct, but also the radiated power is maximized initially) and define the optimization goal to minimize the difference between the measured and desired axial ratios during the iterations while maintaining the polarization angle and beam direction at their initial value by combining their deviation from the target values in the goal function, similar to the optimization for linear polarization. Finally, a circular polarization can also be achieved by starting with an already optimized linear polarization at any polarization angle and minimizing the axial ratio while keeping the beam in the correct direction in a similar way. C. Measurement Results Fig. 20(a) shows the measured spectrum of the radiated signal, which reveals a tone at 122.9 GHz with a maximum effective isotropic radiated power (EIRP) of 12.3 dBm in the broadside direction. The corresponding radiation patterns in the two orthogonal planes for this setting were also measured and are given in Fig. 20(b). The DPC radiator array is capable of transmitting linear polarizations at any polarization angle. The ideal scenario for tuning the polarization angle is demonstrated in Fig. 21(a) where three examples of linear polarization are shown as the polarization angle is controlled from 0 to 180 . This figure illustrates the normalized plots of the projected power for the ideal transmitted linear polarizations, measured by the linearly polarized receiver at different polarization angles as the angle is swept by the stepper motor on the receiver side. Measurement results for

Fig. 22. Axial ratio tuning of the transmitted polarization to obtain elliptical and circular polarization. Normalized plots of projected power at: (a) different polarization angles in broadside for expected target polarizations and (b) measured polarizations after optimization.

broadside radiation, shown in Fig. 21(b), confirm that linear polarizations with the full 0 to 180 range of polarization angle can be achieved with this design. In these measurements, the goals are set to achieve linear polarizations at different polarization angles and the optimization process is stopped when an axial ratio better than 14 dB is achieved. As can be seen, this design is even able to reach higher axial ratios if we continue the optimization process. The DPC radiator is also capable of controlling the axial ratio of the transmitted polarization to transmit elliptical polarization with a desired axial ratio and circular polarization. To demonstrate this capability, three arbitrary axial ratios of 4, 7, and 10 dB were selected as targets to achieve elliptical polarizations at two arbitrary polarization angles of 30 and 90 in broadside. In Fig. 22(a), the ideal expected elliptical polarizations as well as an ideal circular polarization are shown and the measured polarizations that correspond to the desired goals are plotted in Fig. 22(b). The results show that the axial ratios for the measured elliptical polarizations are within 0.5 dB of the target values and a circular polarization with an axial ratio as low as 1.2 dB is achieved. The 2-D array of DPC antennas can steer the beam in both of the two orthogonal planes ( and ) while controlling the polarization. Fig. 23(a) shows this scenario for

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TABLE I COMPARISON OF INTEGRATED RADIATING SOURCES IN SILICON WITHOUT EXTERNAL DIELECTRICS

Fig. 23. Radiation patterns corresponding to 2-D beam steering: (a) for the linear polarization mode, (b) simultaneous beam steering and polarization angle control, and (c) simultaneous beam steering and axial ratio control.

the linear polarization that corresponds to the setting for maximum EIRP. In this figure, the solid black curves in the radiation pattern plots are the same data for maximum EIRP in broadside radiation whose measured polarization together with the ideal target polarization are shown in Fig. 24(a). The dashed gray curves are the radiation patterns for the same polarization steered in plane by 15 and the dashed black curves are also the same polarization steered in the other orthogonal plane ( ), again by 15 . The next set of radiation patterns, shown in Fig. 23(b), corresponds to steering a linear polarization at a different polarization angle ( ) in one of the orthogonal planes by 10 , demonstrating simultaneous polarization angle tuning and beam steering, and Fig. 23(c) shows the steered beam of an elliptical polarization with the same polarization angle as the previous case, but with a lower axial ratio of 4 dB, steered in the other orthogonal plane, to demonstrate axial ratio control while beam steering. The measured polarizations and the ideal target polarizations for these two cases are plotted in Fig. 24(b) and (c).

Fig. 24. Measured and target polarizations corresponding to 2-D beam steering for the: (a) linear polarization mode, (b) simultaneous beam steering and polarization angle control, and (c) simultaneous beam steering and axial ratio control.

Table I shows the comparison of the 2 2 DPC radiator with the state-of-the-art, which includes integrated radiators without external lenses or superstrates. To the best of the authors’ knowledge, this DPC radiator and its previous version in [19] are the only integrated radiators with DPC capability while the other radiators transmit a fixed polarization. IV. CONCLUSION Dynamic polarization control (DPC) of the far-field radiated electric field of an integrated radiator combined with the simultaneous ability to steer the radiated beam in two dimensions when used in 2-D phased arrays, ensures polarization matching between the transmitter and receiver antennas in both fixed and mobile wireless systems. Polarization matching is maintained regardless of the polarization, orientation, and location of the receiving antenna in space, as long as it remains within the 2-D

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steering range of the 2-D phased array of DPC transmitting antennas. This work demonstrates a fully integrated 2 2 DPC transmitter phased array in IBM’s 32-nm CMOS SOI process. It radiates a maximum EIRP of 12.3 dBm at 122.9 GHz by synchronizing four individual DPC antennas with independent phase and gain control with respect to each other. The 2-D DPC phased array enables polarization angle control of the radiated linear and elliptical polarization across the complete tuning range of 0 to 180 and axial ratio control for the elliptical polarization down to 1.2 dB to achieve circular polarization with the ability to steer the radiated beam in both dimensions up to 15 . ACKNOWLEDGMENT The authors would like to thank A. Pai, California Institute of Technology, and B. Parker, formerly with IBM, for technical assistance, and S. Raman, formerly with the Defense Advanced Research Projects Agency (DARPA), T. Quach, Air Force Research Laboratory (AFRL), and D. Friedman, IBM, for support. REFERENCES [1] W. C. Y. Lee and Y. S. Yeh, “Polarization diversity for mobile radio,” IEEE Trans. Commun., vol. COM-20, no. 5, pp. 912–923, May 1972. [2] M. R. Andrews, P. P. Mitra, and R. deCarvalho, “Tripling the capacity of wireless communications using electromagnetic polarization,” Nature, vol. 409, pp. 316–318, Jan. 2001. [3] D. Giuli, “Polarization diversity in radars,” Proc. IEEE, vol. 74, no. 2, pp. 245–269, Feb. 1986. [4] H. A. Zebker and J. J. Van Zyl, “Imaging radar polarimetry: A review,” Proc. IEEE, vol. 79, no. 11, pp. 1583–1604, Nov. 1991. [5] A. G. Andreou and Z. K. Kalayjian, “Polarization imaging: Principles and integrated polarimeters,” IEEE Sensors J., vol. 2, no. 6, pp. 566–576, Dec. 2002. [6] M. Sarkar, D. San Segundo Bello, C. Van Hoof, and A. Theuwissen, “Integrated polarization analyzing CMOS image sensor for material classification,” IEEE Sensors J., vol. 11, no. 8, pp. 1692–1703, Aug. 2011. [7] S. M. Bowers, K. Sengupta, K. Dasgupta, B. D. Parker, and A. Hajimiri, “Integrated self-healing for mm-wave power amplifiers,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 3, pp. 1301–1315, Mar. 2013. [8] M. Varonen, M. Karkkainen, M. Kantanen, and K. A. I. Halonen, “Millimeter-wave integrated circuits in 65-nm CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 9, pp. 1991–2002, Sep. 2008. [9] A. Komijani, A. Natarajan, and A. Hajimiri, “A 24-GHz, 14.5-dBm fully integrated power amplifier in 0.18- m CMOS,” IEEE J. SolidState Circuits, vol. 40, no. 9, pp. 1901–1908, Sep. 2005. [10] K. Sengupta and A. Hajimiri, “A compact self-similar power combining topology,” in IEEE MTT-S Int. Microw. Symp. Dig., 2010, pp. 244–247. [11] Z. Feng, W. Zhang, B. Su, K. Gupta, and Y. Lee, “RF and mechanical characterization of flip-chip interconnects in CPW circuits with underfill,” IEEE Trans. Microw. Theory Techn., vol. 46, no. 12, pp. 2269–2275, Dec. 1998. [12] T. Krems, W. Haydl, H. Massler, and J. Rudiger, “Millimeter-wave performance of chip interconnections using wire bonding and flip chip,” in IEEE MTT-S Int. Microw. Symp. Dig., 1996, vol. 1, pp. 247–250. [13] S. Shahramian, Y. Baeyens, N. Kaneda, and Y.-K. Chen, “A 70–100 GHz direct-conversion transmitter and receiver phased array chipset demonstrating 10 Gb/s wireless link,” IEEE J. Solid-State Circuits, vol. 48, no. 5, pp. 1113–1125, May 2013. [14] A. Tang et al., “A 144 GHz 0.76 cm-resolution sub-carrier SAR phase radar for 3D imaging in 65 nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., 2012, pp. 264–266. [15] A. Natarajan, A. Komijani, X. Guan, A. Babakhani, and A. Hajimiri, “A 77-GHz phased-array transceiver with on-chip antennas in silicon: Transmitter and local LO-path phase shifting,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2807–2819, Dec. 2006.

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[16] Z. Chen, C.-C. Wang, H.-C. Yao, and P. Heydari, “A BiCMOS W-band 2 2 focal-plane array with on-chip antenna,” IEEE J. Solid-State Circuits, vol. 47, no. 10, pp. 2355–2371, Oct. 2012. [17] J.-D. Park, S. Kang, S. Thyagarajan, E. Alon, and A. Niknejad, “A 260 GHz fully integrated CMOS transceiver for wireless chip-to-chip communication,” in Proc. VLSI Circuits Symp., 2012, pp. 48–49. [18] R. Han and E. Afshari, “A CMOS high-power broadband 260-GHz radiator array for spectroscopy,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 3090–3104, Dec. 2013. [19] S. M. Bowers, A. Safaripour, and A. Hajimiri, “Dynamic polarization control,” IEEE J. Solid-State Circuits, vol. 50, no. 5, pp. 1224–1236, May 2015. [20] S. M. Bowers and A. Hajimiri, “Multi-port driven radiators,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 12, pp. 4428–4441, Dec. 2013. [21] Z. Wang, P.-Y. Chiang, P. Nazari, C.-C. Wang, Z. Chen, and P. Heydari, “A CMOS 210-GHz fundamental transceiver with OOK modulation,” IEEE J. Solid-State Circuits, vol. 49, no. 3, pp. 1224–1236, Mar. 2014. [22] K. Sengupta and A. Hajimiri, “Sub-THz beam-forming using near-field coupling of distributed active radiator arrays,” in IEEE Radio Freq. Integr. Circuits Symp. Dig., 2011, pp. 1–4. [23] S. M. Bowers, A. Safaripour, and A. Hajimiri, “An integrated slot-ring traveling-wave radiator,” IEEE Trans. Microw. Theory Techn., vol. 63, no. 4, pp. 1154–1162, Apr. 2015. [24] Y. Tousi and E. Afshari, “A high-power and scalable 2-D phased array for terahertz CMOS integrated systems,” IEEE J. Solid-State Circuits, vol. 50, no. 2, pp. 597–609, Feb. 2015. [25] K. Sengupta and A. Hajimiri, “A 0.28 THz power-generation and beam-steering array in CMOS based on distributed active radiators,” IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 3013–3031, Dec. 2012. [26] R. Han et al., “A 320 GHz phase-locked transmitter with 3.3 mW radiated power and 22.5 dBm EIRP for heterodyne THz imaging systems,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., 2015, pp. 15–17. [27] K. Sengupta, D. J. Seo, L. Yang, and A. Hajimiri, “Silicon integrated 280 GHz imaging chipset with 4 4 SiGe receiver array and CMOS source,” IEEE Trans. THz Sci. Technol., vol. 5, no. 3, pp. 427–437, May 2015. [28] U. Pfeiffer et al., “A 0.53 THz reconfigurable source array with up to 1 mW radiated power for terahertz imaging applications in 0.13 m SiGe BiCMOS,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., 2014, pp. 256–257. [29] A. Safaripour, S. M. Bowers, K. Dasgupta, and A. Hajimiri, “A 2 2 dynamic polarization-controlling integrated phased array,” in IEEE Radio Freq. Integra. Circuits Symp. Dig., 2015, pp. 219–222. [30] S. M. Bowers, A. Safaripour, and A. Hajimiri, “Dynamic polarization control of integrated radiators,” in IEEE Radio Freq. Integr. Circuits Symp. Dig., 2014, pp. 291–294. [31] M. Chua and K. Martin, “1 GHz programmable analog phase shifter for adaptive antennas,” in Proc. IEEE Custom Integr. Circuits Conf., 1998, pp. 71–74. [32] A. Rofougaran, J. Rael, M. Rofougaran, and A. Abidi, “A 900 MHz CMOS LC-oscillator with quadrature outputs,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., 1996, pp. 392–393.

Amirreza Safaripour (S’11) received the B.S. degree in electrical engineering from the Sharif University of Technology, Tehran, Iran, in 2010, the M.S. degree in electrical engineering from the California Institute of Technology, Pasadena, CA, USA, in 2012, and is currently working toward the Ph.D. degree at the California Institute of Technology. His research interests include high-frequency analog integrated circuits, millimeter-wave integrated transmitters and receivers, as well as novel electromagnetic design of integrated radiators for self-correcting and adaptive millimeter-wave power generation and radiation, targeting various applications in high-speed communication, sensing, and imaging. Mr. Safaripour was the recipient of the California Institute of Technology’s Atwood Fellowship (2010), Analog Devices’ Outstanding Student Designer Award (2012), and Iran’s National Elites Foundation Fellowship (2007–2010).

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Steven M. Bowers (S’08–M’14) received the B.S. degree in electrical engineering from the University of California at San Diego, La Jolla, CA, USA, in 2007, and the M.S. and Ph.D. degrees in millimeterwave circuits and systems from the California Institute of Technology, Pasadena, CA, USA, in 2009 and 2014, respectively. In August 2014, he joined the faculty of the Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA, where he is currently an Assistant Professor. His research interests include holistic integration of high-frequency analog circuits, advanced digital circuits, novel electromagnetic structures and integrated silicon photonics to enable the next generation of millimeter-wave applications, specifically in adaptive and self-healing millimeter-wave circuits and millimeter-wave power generation, radiation, and detection. Dr. Bowers is a member of IEEE HKN and TBP. He was the recipient of the California Institute of Technology’s Institute Fellowship (2007), the Analog Devices Outstanding Student Designer Award (2009), the IEEE RFIC Symposium Best Student Paper Award (2012), the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) International Microwave Symposium (IMS) Best Student Paper Award (2013), and the 2015 IEEE MTT-S Microwave Prize.

Kaushik Dasgupta (S’09–M’14) received the B.Tech and M.Tech degrees in electronics and electrical communication engineering from the Indian Institute of Technology, Kharagpur, India, in 2008, and the M.S. and Ph.D. degrees in electrical engineering from the California Institute of Technology, Pasadena, CA, USA, in 2010 and 2014, respectively. He is currently a Research Scientist with the PHY Research Laboratory, Intel Corporation, Hillsboro, OR, USA. During the summers of 2006 and 2007, he was a Research Intern with the System on Chip Laboratory, University of Washington, Seattle, WA, USA. His research interests include millimeter-wave integrated transmitters and receivers, high-frequency reconfigurable systems, as well as integrated circuits for biomedical applications. Dr. Dasgupta was the corecipient of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) Microwave Prize (2015), the IEEE RFIC Best Student Paper Award (2012), and Analog Devices’ Outstanding Student Designer Award (2009). He was also the recipient of the California Institute of Technology’s Atwood Fellowship (2008), the Jagadish Bose National Science Talent Scholarship (2003), and the Best Undergraduate Project of the E&ECE Department, IIT Kharagpur.

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Ali Hajimiri (F’10) received the B.S. degree in electronics engineering from Sharif University of Technology, Tehran, Iran, in 1994, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, USA, in 1996 and 1998, respectively. From 1993 to 1994, he was with Philips Semiconductors, where he was involved with a BiCMOS chipset for GSM and cellular units. In 1995, he was with Sun Microsystems, where he was involved with the UltraSPARC microprocessor’s cache RAM design methodology. During the summer of 1997, he was with Lucent Technologies (Bell Labs), Murray Hill, NJ, USA, where he investigated low-phase-noise integrated oscillators. In 1998, he joined the faculty of the California Institute of Technology, Pasadena, CA, USA, where he is currently the Thomas G. Myers Professor of Electrical Engineering and Director of the Microelectronics Laboratory. In 2002, he cofounded Axiom Microdevices Inc., whose fully integrated CMOS power amplifier (PA) has shipped close to 250 million units, and was acquired by Skyworks Inc. in 2009. He authored The Design of Low Noise Oscillators (Springer, 1999) and has authored or coauthored more than 150 refereed journal and conference technical articles. He holds more than 60 U.S. and European patents. His research interests are high-speed and high-frequency integrated circuits for applications in sensors, biomedical devices, photonics, and communication systems. Dr. Hajimiri has served on the Technical Program Committee of the IEEE International Solid-State Circuits Conference (ISSCC), as an Associate Editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS, an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, a Member of the Technical Program Committee, International Conference on Computer Aided Design (ICCAD), Guest Editor for the IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, and on the Guest Editorial Board of the Transactions of the Institute of Electronics, Information and Communication Engineers of Japan (IEICE). He is a Fellow of the National Academy of Inventors (NAI). He was selected to the TR35 Top Innovator’S List in 2004. He has served as a Distinguished Lecturer of the IEEE Solid-State Circuits Society and the IEEE Microwave Theory and Techniques Society (IEEE MTT-S). He was a recipient of the California Institute of Technology’s Graduate Students Council Teaching and Mentoring Award, as well as the Associated Students of California Institute of Technology’s Undergraduate Excellence in Teaching Award. He was the Gold Medal recipient of the National Physics Competition and the Bronze Medal recipient of the 21st International Physics Olympiad, Groningen, Netherlands. He was a corecipient of the IEEE JOURNAL OF SOLID-STATE CIRCUITS Best Paper Award (2004), the International Solid-State Circuits Conference (ISSCC) Jack Kilby Outstanding Paper Award, a two-time corecipient of the CICC Best Paper Award, and a three-time recipient of the IBM Faculty Partnership Award, as well as the National Science Foundation CAREER Award, Okawa Foundation Award, and the 2015 IEEE MTT-S Microwave Prize.

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High-Performance E-Band Transceiver Chipset for Point-to-Point Communication in SiGe BiCMOS Technology Run Levinger, Roee Ben Yishay, Oded Katz, Benny Sheinman, Nadav Mazor, Roi Carmon, and Danny Elad, Member, IEEE

Abstract—Two fully integrated chipsets covering the entire E-band frequency range, 71–76/81–86 GHz, have been demonstrated. These designs, which were implemented in 0.13- m SiGe BiCMOS technology, use a sliding IF superheterodyne architecture. The receiver (Rx) chips include an image-reject low-noise amplifier, RF-to-IF mixer, variable gain IF amplifier (IF VGA), quadrature IF-to-baseband (BB) de-modulator, tunable BB filter, phase-locked loop (PLL) synthesizer, and a frequency quadrupler. At room temperature the Rx chips achieve a maximum gain of 73 dB, 6-dB noise figure, better than 12-dBm input third-order intercept point, more than 65-dB dynamic range, and consume 600 mW for lower band (LB) (71–76 GHz) and higher band (HB) (81–86 GHz) alike. The transmitter (Tx) chips include a power amplifier, image reject driver, variable RF attenuators, power detector, IF-to-RF up-converting mixer, IF VGA, quadrature BB-to-IF modulator, PLL, and a frequency multiplier. The Tx chips achieve a power 1-dB compression point (P1dB) of 17.5/16.6 dBm, saturated power (Psat) of 20.5/18.8 dBm on a single-ended output, up to 39-dB gain with an analog controlled dynamic range of 30 dB, and consumes 1.75/1.8 W for the LB and HB, respectively. This state-of-the-art performance enables the usage of complex modulations and high-capacity transmission. Index Terms—E-band, point-to-point, SiGe, transceiver.

I. INTRODUCTION

T

HE DEMAND of broad bandwidth to support multi-gigabit data transmission has significantly increased over the past few years, particularly driven by the need to advance the capabilities of cellular back-haul links. An attractive frequency range for back-haul links is the E-band, 71–76 GHz, 81–86 GHz, mainly due to the wide bandwidth allocated to E-band, allowing the realization of high-capacity point-to-point wireless applications [1], [2]. Additionally, the E-band frequency range has lower atmospheric attenuation compared to the 57–66-GHz unlicensed band, which relaxes link budget requirements for a given targeted system performance. Perhaps an even more attractive advantage is that antennas with high

Manuscript received August 05, 2015; revised December 02, 2015; accepted February 04, 2016. This paper is an expanded version from the IEEE RFIC Symposium, Phoenix, AZ, USA, May 17–19, 2015. The authors are with IBM Haifa Research Laboratories, Haifa 31905, Israel (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2528981

gain and directivity are easily realizable with apertures less than 1 ft in the E-band frequency range [3]. Current E-band radio systems employ costly hybrid RF front-end components, while only a few recent publications [4]–[7] describe attempts to cover the lower or upper portion of the E-band spectrum with a silicon-based monolithic solution, here in a direct conversion architecture. The design of two separate chipsets, each covering its designated band, lower band (LB), 71–76 GHz, or higher band (HB), 81–86 GHz, allows full duplex throughput and is required in order to utilize the full potential of the E-band. In order to provide maximum flexibility, the transceiver is required to meet the criteria imposed by various modulation transmission formats, ranging from a constant envelope with high output power to high quadrature amplitude modulation (QAM) with lower power. Therefore, there is a strict demand for dynamic-range performance in such designs. We have recently published some aspects of our E-band transceiver [8]–[10]; however, in this paper, we present a complete and detailed description of our system, comprising two fully integrated high-performance SiGe—based transceiver chipsets covering the entire E-band frequency range. The chipsets include a receiver (Rx) and transmitter (Tx) in the lower and higher E-band frequency ranges. The chips were designed and fabricated in IBM 0.13- m SiGe technology. A superheterodyne architecture is used, which enables sharing the baseband (BB) and IF circuits of the two chipsets, while the RF front end components are tuned as needed for the targeted band. The chipsets allow multi-gigabit per second transmission using high-order modulation, up to 128-QAM with Tx gain of 39 dB and 19-dBm saturated output power. The Rx was designed to work with input signals in a wide dynamic range of more than 65 dB, having room-temperature maximum gain of 73 dB and minimum noise figure (NF) of 6 dB for low input level, and high linearity, dBm for high input level. This paper is organized as follows. Section II analyzes the transceiver architecture and design considerations. Section III describes the various transceiver components and their individual performance. Section IV shows experimental results and Section V concludes this paper. II. TRANSCEIVER ARCHITECTURE The E-band transceiver chipset employs a double conversion superheterodyne sliding-IF architecture, as depicted in Fig. 1.

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Fig. 1. Transceiver block diagram.

TABLE I TRANSCEIVER FREQUENCY PLAN

The local oscillator (LO) signal ( is 2/9 of the RF) is generated either from an internal sub-integer frequency synthesizer, or fed directly from an external source at the LO frequency, or fed through a frequency doubler from a source at half the LO frequency. A multiplexing LO amplifier is used to select the desired LO input. The LO signals for the RF and IF mixers are created by quadrupling, is 8/9th of the RF, and dividing, is 1/9th of the RF, respectively; the transceiver frequency plan can be seen in Table I. The Tx up-converts the BB signal to IF, amplifying the IF voltage amplitude by 5 dB and filtering before up-converting it with a 0-dB conversion-gain double-balanced Gilbert-cell mixer to the RF frequency. An integrated image reject filter at the driver–amplifier input suppresses the image by 30 dB, as the driver amplifies the RF signal by 20 dB. Finally, the RF signal is amplified by the power amplifier (PA), providing gain of 24 dB and maximum output power of 19 dBm. A series of variable analog-controlled attenuators along the BB to the RF transmit path are set to control the signal level at each stage. The BB and IF attenuators, which have a dynamic range of 10 dB each, are used to compensate for variation in the input level of the BB signal, as well as for the BB-modulator gain variation and IF amplifier gain variation over temperature. The next elements in the signal chain are two 25-dB dynamic-range analog-controlled RF attenuators placed at the driver–amplifier

input and output. The first attenuator helps to maintain the LO suppression level and enables dynamic compensation for gain variation over temperature. The second RF attenuator is used to enable a dynamic change between different modulation orders, by reducing the extra gain needed to drive the PA to OP1dB for quadrature phase-shift keying (QPSK) modulation to a 12-dB backoff used in 128 QAM. Since the transmitted noise is dominated by noise generated before the second RF attenuator, there is only a small degradation of the output signal-to-noise ratio ( 3 dB) for backoff of up to 12 dB, which allows the Tx to meet the ETSI spectrum mask required for high-modulation orders [2]. The rest of the RF attenuator’s dynamic range is used for transmit power control (TPC). The attenuator, which succeed the driver amplifier, will be used for the remote transmit power control (RTPC) (e.g., sub-range where the required spectrum mask is fulfilled), and the rest of the transmit chain attenuator will be used for the automatic transmit power control (ATPC) (e.g., sub range where the required spectrum mask is no longer fulfilled). For instance, when applying 64-QAM modulation, the RTPC will be greater than 10 dB, while the remaining attenuators dynamic range will result in ATPC of 15 dB. Correspondingly, at the Rx, the RF signal is amplified by 21 dB with an image-rejecting low-noise amplifier (LNA) incorporating internal variable attenuation of 17 dB, followed by a highly linear analog controlled variable attenuator (from 2 to 22 dB), and down-converted to , using a double-balanced mixer with a tuned IF load. The IF is amplified and filtered by a variable gain tuned-load amplifier (VGA), which has a 20-dB dynamic range. A pair of double-balanced mixers down-convert the signal, to create in-phase (I) and quadrature-phase (Q) BB signals, which are filtered using a tunable third-order active low-pass filter (LPF) and amplified by a 30-dB dynamic range VGA. The Rx was designed with a variable analog gain control to support 70-dB RF to BB gain and 6-dB NF for its minimum target input signal level of 85 dBm, and input third-order intercept point (IIP3) greater than 12 dBm for a fully attenuated (maximum input) signal. Using the analog controlled LNA integrated attenuator, RF linear attenuators, IF VGA, and BB VGA, the overall Rx dynamic range is greater than 65 dB, which allows highly flexible dynamic gain compensation for various input levels, linearity requirements, and temperature variations. III. TRANSCEIVER CIRCUITS In this section, a detailed description is given for the frequency synthesizer, LNA, PA, and mixers, including some standalone measurements of the aforementioned components. A small-signal S-parameter and large-signal compression point were measured using N5227A Agilent PNA-X. Frequency synthesizer and frequency multiplier spectra were taken with an N9030A Agilent PXA signal analyzer, also having phase-noise personality and NF personality. For NF measurements, a Sage Millimeter STZ12/L1 noise source was additionally used. A. Frequency Synthesizer The synthesizer is a type-II fourth-order PLL with a loop bandwidth of 100 kHz. Fig. 2 shows a block diagram of the synthesizer. It consists of a differential reference clock buffer, a CMOS static phase frequency detector (PFD), a differential

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Fig. 2. Block diagram of the integrated PLL-based synthesizer.

Fig. 5. Frequency quadrupler core schematic.

Fig. 3. Phase noise as a function of frequency measured at 16.8333 GHz, 25 C, 85 C, and 40 C.

Fig. 4. Block diagram of the elements in the quadrupler chain.

current steering CMOS charge pump, a third-order passive loop filter, a PMOS boosted Colpitts VCO detailed in [11], and a phase rotating pulse injection division region switching sub-integer frequency divider [12], [13]. The synthesizer can generate output over the full 15.584–19.273-GHz range required to cover the needs of both the LB and HB chipsets. The division ratio is adjustable from 280.5 to 344 in half integer steps, and can be used with a 55.5556-MHz reference clock to allow 125-MHz frequency bands at RF frequencies, in accordance with ITU requirements [14]. The synthesizer also supports an external control voltage mode, in which an external voltage can be applied directly to the VCO; this feature, used in combination with the synthesizer’s divide-by-8 output, lets the VCO be locked with an auxiliary PLL for testing or to implement alternate channelization schemes. Fig. 3 shows the PLL’s measured phase noise at 25 C, 85 C, and 40 C at 16.833 GHz. The PLL shows 112 and 133 dBc Hz phase noise at 1- and 10-MHz offsets, respectively; reference and sub-integer spurs are below 57 dBc. In both Rx and Tx chips, the LO signal may also be applied from an external source, while powering down the internal PLL. Since commercial low-noise sources are more common in the

Fig. 6. Measured frequency quadrupler output power and fifth harmonic rejection for: (a) LB and (b) HB E-band transceivers between 40 C and 85 C.

X-band range, a frequency doubler was integrated as well to enable use of a lower frequency external LO (9–9.6 GHz). The doubler is detailed in [15]. B. High Suppression Frequency Quadrupler The frequency quadrupler is designed to have high parasitic harmonic suppression, and especially, a sharp fifth harmonic suppression, which prevents double folding of the data to IF frequency range. The quadrupler chain, depicted in Fig. 4, consists of a quadrupler core, a balun that generates back a differential

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Fig. 7. Schematic diagrams of the LNA with embedded attenuator and image reject filter (left) and down-converting mixer (right).

output, a buffering amplifier, which is followed by a sharp LPF, and an amplifier stage, which saturates the output power. The quadrupler core, shown in Fig. 5 and detailed in [16], is implemented in a balanced cascode configuration; the chosen balanced topology provides broadband odd harmonic suppression. In addition, the transistors in cascode topology are used to insert a second harmonic filter between the common-emitter (CE) (Q1,Q2) and common-base (CB) (Q3,Q4) stages, and improve the multiplier frequency response. The filter includes two shunt open stubs connected by an inductive path, presenting a low-pass characteristic and a notch characteristic that, together, sharply reject adjacent frequency spurs. The filters for the upper and lower E-band chipsets were measured separately, achieving more than 11-dBc suppression at only 0.3 octave from the LO signal with insertion loss (IL) lower than 3 dB. The quadrupler chain was measured over temperature providing more than 9-dBm output power, and the fifth harmonic (78.5–84.5 and 90–95.5 GHz for the lower and upper bands, respectively) is rejected by more than 33 dBc over temperature, as seen in Fig. 6. The frequency quadrupler core consumes around 20 mA while in optimal operation, whereas the buffer and amplifier together consume 77 mA, all from a 2.7-V dc supply. C. LNA The LNA is shown in Fig. 7. It consists of six CE stages in the HB instantiation (five stages in the LB case) since the CE stage has an inherently more favorable noise measure (NM) per stage as compared with that of the CB stage configuration in this technology. Three CBEBC HBT transistors in parallel with a nominal current density of 0.33 mA m are used in the input stage. The matching of the CE stages utilize shielded microstrip transmission lines, thus minimizing interaction between adjacent components, and allowing dense layout while still maintaining good model-to-hardware correlation. A 17-dB dynamic range was achieved using analog-controlled shunt attenuators that consist of an HBT transistor placed after each CE stage, excluding the first one. In order to filter out the image frequency, only 7/9ths of the RF frequency, with minimum loss and maximum bandwidth, a fifth order high-pass elliptic filter is embedded in the LNA’s output matching network. In order to maximize the steepness

Fig. 8. Measured S-parameters and NF of the: (a) LB LNA and (b) HB LNA.

between the stopband and passband, the filter was implemented using four series metal–insulator–metal (MIM) capacitors and five shunt open stubs terminated with MIM capacitors. The MIM capacitor termination reduces transmission-line length, and improves the filter’s factor. As a desired side effect, the filter balances the LNA roll off. The image reject filter provides more than 27.8 dB of rejection at the image frequency range for the LB and 23.5 dB for the HB. The LNA NF is 5–6 dB for both the LB and HB, as shown in Fig. 8. The NF was extracted from NF measurements of a standalone mixer test site and an LNA–mixer combination test site, with measurements taken at 25 C. S-parameters show peak gain of 24/21 dB with 1.5/1-dB flatness across the LB/HB designs, respectively. At maximum gain for the LB/HB cases, the

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Fig. 9. Schematic diagrams of the LB PA.

Fig. 11. Measured output power and gain of the LB and HB PA.

Fig. 12. Measured mixer conversion gain and NF as a function of LO power.

D. PA

Fig. 10. Measured S-parameters of the: (a) LB PA and (b) HB PA.

measured IIP3 is 23 19 dBm, while at full attenuation the LNA achieves IIP3 better than 12 9 dBm. The LNA area is 620 530 m and it consumes 42 mA.

The PA consists of a balanced configuration in which two unit cells, shown in Fig. 9, are driven differentially and their outputs are summed using either a low-loss off-chip balun or an on-chip rat-race balun with IL of 1.5 dB and 25-dB portto-port isolation. The LB unit cell consists of five CE stages, while the HB version consists of six such stages. The first power combining is accomplished by dividing the final stage into two separated branches (36 m) and summing their power using a

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Fig. 13. HB Rx and Tx die photographs.

Fig. 15. Rx measured NF at 25 C and 85 C for: (a) LB and (b) HB.

Fig. 14. Rx measured gain at 25 C and 85 C for: (a) LB and (b) HB.

transmission-line impedance transformer that provide simultaneous power and impedance matching. The combiner also includes a parallel 100- resistor to preclude odd-mode oscillations. Each of the branches in the final stage consists of three parallel 12- m transistors. All stages are biased with current density of 0.7 mA m using digitally adjustable current mirrors, through a quarter-wave transmission line, shorted by a MIM capacitor at RF. This arrangement enables biasing of the CE stage above for improved linearity and allows better flexibility in layout placement of bias circuits [17]. The PA’s output is capacitivly coupled to a power detector [9] with programmable dynamic range. Fig. 10 shows the small-signal S-parameters of the singleended LB and HB PA unit cells, measured at 25 C. peaks at 24 dB at 84 GHz, with 3-dB bandwidth of 21 GHz (25%) and gain flatness of less than 0.25 dB in the 81–86-GHz range,

where both and are below 16 dB. The LB version achieves similar gain with 3-dB bandwidth of 20.8 GHz (28%) and gain flatness of 0.5 dB. Fig. 11 depicts the measured output power and gain of LB and HB PA unit cells under swept input power, using the PNA-X power sweep capabilities. A single-unit cell delivers an output power of 14.5–16 dBm (LB) and 14.5–15.2 dBm (HB) at the 1-dB compression point, while the measured saturated power is 17.5–18.5 and 16.5–17.5 dBm, respectively. A 1 phase variation was observed at 1-dB compression, suggesting the AM–PM mechanism is negligible when operating at high-order modulations. E. Down- and Up-Converting Mixers The up-converting mixer used is a double-balanced Gilbert cell with a degeneration inductor to increase mixer linearity. The mixer conversion gain is 0 dB and its output third-order intercept point (OIP3) is 3 dBm. A more detailed analysis of this mixer can be found in [18]. The down-converting mixer, shown in Fig. 7, is a double-balanced Gilbert cell, where the amplifying stage is CB instead of the commonly used CE [19]. The CB stage improves the linearity and noise matching of the mixer. The amplifying stage is driven by a Marchand balun that is also used as a dc ground connection for the CB stage, thus reducing the input loss to the mixer stage. Resonating transmission lines are placed between the amplifying and mixing stages to reduce the capacitive

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Fig. 18. Tx measured conversion gain, Psat, and P1dB at 25 C for HB.

Fig. 16. Rx measured IIP3 at 25 C and 85 C for: (a) LB and (b) HB.

Fig. 19. Tx spectra for various output power versus ETSI spectral efficiency classes, resolution bandwidth is set to 3 MHz.

Fig. 20. Modulation constellation and spectrum for: (a) class 5L at 5-dBm output power (b) class 5H at 0-dBm output power.

Fig. 17. Tx measured conversion gain, Psat, and P1dB at 25 C for LB.

loading of the mixing transistors, hence reducing the NF of the mixer while increasing its conversion gain. The LO signal (0 dBm) is buffered by two emitter–follower pairs, matched to 100 . The mixer attains 7.5-dB conversion gain and 11.5-dB single-sideband (SSB) NF at 25 C. The mixer conversion gain is flat over frequency, less than 1 dB, and so does the NF. Fig. 12 shows NF and conversion gain as a function of LO power measured at 25 C, 85 C, and 40 C. Further details about this mixer are found in [20]. An NMOS based

highly linear analog controlled attenuator is placed between the LNA and the mixer. It exhibits 2-dB IL, 20-dBm IIP3, and over 20-dB dynamic range. In conjunction with a mixer IIP3 of 0 dBm and the IL of the balun, the down-converting stages have 4-dBm IIP3. IV. TRANSCEIVER MEASUREMENTS The chipset was fabricated in a five-metal layer IBM SiGe BiCMOS process (SiGe8HP), and operates from a 2.7-V analog supply, a 1.2-V digital supply for the PLL and SPI, and dedicated 2- and 1.6-V supplies for the PA and LNA, respectively. Die photographs of the HB Tx (size 5.7 1.7 mm ) and HB Rx (size 3.6 1.7 mm ) are shown in Fig. 13.

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TABLE II COMPARISON TO OTHER STATE-OF-THE-ART E-BAND Txs AND Rxs

A. Rx Measurements The LB and HB Rx gain and NF were measured using a Sage Millimeter STZ12/L1 noise source and an N9030A Agilent PXA signal analyzer are shown in Figs. 14 and 15, respectively. For minimum attenuation, the conversion gain is 70–74 dB for both LB and HB Rxs at 25 C, and drops by up to 7 at 85 C. Part of the dynamic range of the attenuators along the receive chain can be used to compensate for the gain variation over temperature. The Rx NF is better than 7 dB for both LB and HB at 25 C, as shown in Fig. 16, and increases to 8.5 dB at 85 C and 86 GHz. Fig. 16 shows IIP3 for the LB and HB designs, which was measured using a two-tone method with two E-band HMC-T2270 Hittite sources. At maximum attenuation, the Rx gain drops to 12 dB and the resulting IIP3 is better than 10 and 12 dBm for the LB and HB Rxs, respectively. Naturally, IIP3 improves by 3–5 dB at 85 C due to reduced gain. The Rx consumes 220 mA from a 2.7-V supply, and 42 mA from a 1.6-V supply. B. Tx Measurements Figs. 17 and 18 show measured gain, saturated power (Psat), and output 1-dB compression point (P1dB) for the LB and HB Txs, respectively, which were measured using an Agilent 5183A analog signal generator, an Agilent N1914A power meter, and an N9030A Agilent PXA signal analyzer. The Tx’s show low power roll off over frequency as Psat varies between 18.8–20 dBm for the LB Tx, and ranges between 18–18.8 dBm for the HB Tx. Similarly, P1dB is better than 16 dBm for both the LB and HB Tx, and varies by less than 1.5 dB over the entire frequency range. The measured BB to RF conversion gain is 38 dB and rolls off by 2 dB toward the lower frequencies. When using the integrated digital controlled bias circuits and by adjusting the attenuators along the transmit chain the conversion gain variations over temperature and process can be fully compensated. The spurious response of the Tx showed a

25-dB image suppression, and the I/Q quadrature imbalance is 2 without any external phase mismatch cancellation. Transmitter error vector magnitude (EVM) and transmission spectrum ETSI mask compliance were measured using an Agilent M8190A AWG used to feed BB I/Q inputs, a M80/5X2B Spacek Labs direct conversion mixer, which down-converted the RF output to X-band for an Agilent VSA, and an Agilent DSA90804A digital signal analyzer. Fig. 19 shows the normalized output spectra for various output power levels at 83 GHz, where it can be observed that the Tx output spectrum meets all mask classes up to class 5H, which corresponds to a minimum modulation order of 128 QAM [2], at a maximum output power of 0 dBm. It is also evident that the transmitted spectrum meets the ETSI mask class 5L (minimum modulation order of 64 QAM) at maximum output power of 5 dBm. The RF attenuator, which succeeds the driver amplifier, the output power is backed off by 13 dB from P1dB in order to meet the mask linearity requirements, while achieving 48-dBc output signal-tonoise ratio (SNR). This RF attenuator can further attenuate the signal to an output power lower than 5 dBm, while achieving output SNR better than 45 dBc, as required by the ETSI mask for class 5L and above, which results in RTPC greater than 10 dB. EVM was measured with a symbol rate of 100 MBd (limited by the instrumentation). Fig. 20 shows the measured constellation and spectrum for 64- and 128-QAM modulations with an external LO. The EVM achieved at 64 QAM with output power of 5 dBm and at 128 QAM with output power of 0 dBm are 1.6% and 1.4%, respectively. When using the internal LO, the EVM degrades slightly to 2.8% and 3%, at 64 and 128 QAM, respectively. The Tx consumes 200 mA from a 2.7-V supply, and 400 mA from the PA 2-V supply at P1dB. Tx EVM and transmission spectrum ETSI mask compliance were measured using an Agilent M8190A AWG used to feed BB I/Q inputs, a M80/ 5X2B Spacek Labs direct conversion mixer, which down-converted the RF output to X-band for an Agilent VSA, and an Agilent DSA90804A digital signal analyzer. Fig. 19 shows the

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normalized output spectra for various output power levels at 83 GHz, where it can be observed that the Tx output spectrum meets all mask classes up to class 5H, which corresponds to a minimum modulation order of 128 QAM [2], at a maximum output power of 0 dBm. It is also evident that the transmitted spectrum meets the ETSI mask class 5L (minimum modulation order of 64 QAM) at maximum output power of 5 dBm. At the RF attenuator, which succeed the driver amplifier, the output power is backed off by 13 dB from P1dB in order to meet the mask linearity requirements, while achieving 48-dBc output SNR. This RF attenuator can further attenuate the signal to an output power lower than 5 dBm while achieving output SNR better than 45 dBc, as required by the ETSI mask for class 5L and above, which results in RTPC greater than 10 dB. Table II shows a comparison between this work and other published E-band Txs and Rxs at room temperature, showing that the chipsets reviewed in this paper outperform state-ofthe-art in terms of transmitted power, linearity, and SNR, as well as the received gain and NF. Additionally, the chipset has a high level of integration and is the only one that has a fully integrated synthesizer.

V. CONCLUSION Fully integrated Rx and Tx chipsets covering the entire E-band frequency range, 71–76 and 81–86 GHz, have been demonstrated in a 130-nm SiGe BiCMOS technology. The two chipsets exhibit very similar performance despite the difference in target frequency, therefore they can be utilized for a frequency division multiplexing (FDM) transmission that allows full frequency duplex throughput. These state-of-the-art E-band chipsets allow broadband communication at data rates of multi Gb/s, can support a significant variety of transmission modulations, and are ideal for communication back-haul applications.

ACKNOWLEDGMENT The authors wish to acknowledge the support and assistance of M. Rachman, A. Bruetbart, A. Golberg, N. Cahoon, and D. Friedman.

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[6] W.-H. Lin, H.-Y. Yang, J.-H. Tsai, T.-W. Huang, and H. Wang, “1024-QAM high image rejection E-band sub-harmonic IQ modulator and transmitter in 65-nm CMOS process,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 11, pp. 3974–3985, Nov. 2013. [7] S. Trotta et al., “A V- and E-band packaged direct-conversion transceiver chipset for mobile backhaul application in SiGe technology,” in Proc. Eur. Microw. Conf., 2014, pp. 1655–1658. [8] O. Katz et al., “High power high linearity SiGe-based transceiver chipset for broadband communication,” in Proc. Radio Freq. Integr. Circuits Symp., 2012, pp. 115–118. [9] R. Ben-Yishay et al., “High power SiGe E-band transmitter for broadband communication,” in Proc. Eur. Microw. Integr. Circuits Conf., 2013, pp. 73–76. [10] R. Ben-Yishay et al., “High-performance 81–86 GHz transceiver chipset for point-to-point communication in SiGe BiCMOS technology,” in Proc Radio Freq. Integr. Circuits Symp., 2015, pp. 417–420. [11] R. Levinger et al., “A robust low phase noise Ku band VCO with 23.3% tuning range for E-band and V-band backhaul transcivers,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., 2015, pp. 395–396. [12] R. Levinger, O. Katz, and D. Elad, “A system, a method and a computer program product for electronic sub-integer frequency division,” U.S. Patent 20140184281 A1, Jul. 3, 2014. [13] R. Levinger et al., “A low phase noise Ku-band sub-integer frequency synthesizer for E-band transceivers,” in IEEE MTT-S Int. Microw. Symp Dig., 2013, pp. 1–4. [14] Radio-Frequency Channel and Block Arrangements for Fixed Wireless Systems Operating in the 71–76 and 81–86 GHz Bands, ITU Recommendation F.2006, Mar. 2012. [15] N. Mazor et al., “A SiGe Ku-band frequency doubler with 50% bandwidth and high harmonic suppression,” in IEEE MTT-S Int. Microw. Symp Dig., 2014, pp. 1–4. [16] O. Katz, R. Ben-Yishay, R. Carmon, B. Sheinman, and D. Elad, “High conversion gain high suppression SiGe based balanced cascode frequency quadrupler at 60–77 GHz,” in Proc. Int. Microw., Commun., Antennas, Electron. Syst Conf., 2011, pp. 1–2. [17] U. R. Pfeiffer, S. K. Reynolds, and B. Floyd, “A 77 GHz power amplifier for potential applications in automotive radar systems,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., 2004, pp. 91–94. [18] B. Sheinman et al., “An active up conversion mixer covering the entire 71–86 GHz E band range in SiGe Technology,” in Proc. Int. Microw., Commun., Antennas, Electron. Syst. Conf., 2013, pp. 183–186. [19] B. A. Floyd, S. K. Reynolds, U. R. Pfeiffer, T. Zwick, T. Beukema, and B. Gaucher, “SiGe bipolar transceiver circuits operating at 60 GHz,” IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 156–167, Jan. 2005. [20] B. Sheinman et al., “A double balanced 81–86 GHz E band active down conversion mixer in SiGe technology,” in Proc. Bipolar/BiCMOS Circuits Technol. Meeting, 2013, pp. 183–186. [21] I. Nasr, B. L. K. Aufinger, G. Fischer, R. Weigel, and D. Kissinger, “A 70–90-GHz high-linearity multi-band quadrature receiver in 0.35- m SiGe technology,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 12, pp. 4600–4612, Dec. 2013. [22] S. Y. Kim, O. Inac, C.-Y. Kim, D. Shin, and G. M. Rebeiz, “A 76–84-GHz 16-element phased-array receiver with a chip-level built-in self-test system,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 8, pp. 3083–3098, Aug. 2013.

REFERENCES [1] J. Wells, “Faster than fiber: The future of multi-G/s wireless,” IEEE Microw. Mag., vol. 10, no. 3, pp. 104–112, May 2009. [2] “Fixed radio systems: Characteristics and requirements for point-topoint equipment and antennas,” ETSI, Sophia Antipolis, France, ETSI EN 302 217-2-2 V2.0.0, Sep. 2012. [3] D. Lockie and D. Peck, “High-data-rate millimeter-wave radios,” IEEE Microw. Mag., vol. 10, no. 5, pp. 75–83, Aug. 2009. [4] S. Shahramian, Y. Baeyens, and Y.-K. Chen, “70–100 GHz directconversion transmitter and receiver phased array chipset in 0.18 m SiGe BiCMOS technology,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., 2012, pp. 123–126. [5] I. Sarkas et al., “An 18-Gb/s, direct QPSK modulation SiGe BiCMOS transceiver for last mile links in the 70–80 GHz band,” IEEE J. SolidState Circuits, vol. 45, no. 10, pp. 1968–1980, Oct. 2010.

Run Levinger received the B.Sc. and M.Sc. degrees in electrical and electronics engineering from Tel-Aviv University, Tel Aviv, Israel, in 2012, and 2015 respectively. His research thesis focused on linearization techniques for integrated E-band transmitter circuits such as up-converting mixers and power detectors. In 2011, he joined the IBM Haifa Research Laboratories, Haifa, Israel, where he is currently a Research Staff Member with the mm-Wave Technologies Group. His research interests include the designing, measuring, and modeling of integrated RF and millimeter-wave voltage-controlled oscillators (VCOs), frequency synthesizers, frequency dividers, mixers, power detectors, and passives for communication, radar, and imaging applications.

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Roee Ben Yishay received the B.Sc. and M.Sc. degrees in electrical engineering from the Technion, Haifa, Israel, in 2006 and 2010, respectively. While with the Technion, he was involved in the research and development of integrated microelectromechanical systems (MEMS)-based RF integrated circuits (RFICs). In 2008, he joined IBM, and is currently a Research Staff Member with the IBM Haifa Research Laboratories, Haifa, Israel, where he is involved the field of millimeter-wave technologies research. His responsibilities have involved analog and RF integrated circuit (RFIC) circuits design for high-speed communication systems. He is currently engaged primarily in the development of millimeter-wave and sub-terahertz (100–300 GHz) RFICs for high data-rate wireless communication links, radar, and imaging systems.

Oded Katz was born in Tel-Aviv, Israel, in 1973. He received the Ph.D. degree in electrical engineering from the Technion–Israel Institute of Technology, Haifa, Israel, in 2005. During his doctraol studies, his research was focused on design, growth, and modeling of GaN-based HFETs for microwave and power circuits and transport properties under low dimensionality. In 2005, he joined IBM, where he was an Analog and RF Integrated Circuit (IC) designer involved with various IBM products, including, gaming processors, phase-locked loops (PLLs), inputs/outputs (I/Os), and RF communication. He has recently been involved with the development of silicon-based E- and V-band fully integrated transceiver chipsets for high data-rate wireless back-haul and other applications. He is currently a Research Staff Member with IBM Haifa Laboratories, Haifa, Israel. He has authored or coauthored over 40 technical papers. He holds 8 U.S patents.

Benny Sheinman received the B.Sc., M.Sc., and Ph.D. degrees in electrical engineering from the Technion–Israel Institute of Technology, Haifa, Israel, in 1991, 1998, and 2004 respectively. His Ph.D. research was focused on the design, growth, and modeling of InP-based HBTs and microwave optoelectronic circuits. In 2004, he joined IBM. He is currently a Research Staff Member with the IBM Haifa Research Laboratories, Haifa, Israel. He led the development of an automation tool for migration of analog- and mixed-

signal designs between technologies, the design of a fast flash ADC in advanced CMOS technology, and performed components design for communication and radar in 60 GHz and E-band systems. He has authored or coauthored over 30 papers. He holds over ten patents. His main research interests are device physics, analog circuits, and microwave design.

Nadav Mazor received the B.Sc. degree in electrical and computer engineering from Ben Gurion University, Beer Sheva, Israel, in 2010, and the M.Sc. degree from Tel-Aviv University, Tel Aviv, Israel, in 2013. He is currently a Research Staff Member with the mm-Wave Technology Group, IBM Haifa Research Laboratories, Haifa, Israel. His research is focused on designing and modeling frequency multipliers for communication and imaging applications.

Roi Carmon received the B.Sc. degree in electrical engineering from the Technion, Haifa, Israel, in 2004. In 2004, he joined the IBM Haifa Research Laboratories, Haifa, Israel, where he was involved with on-chip transmission line research. In 2007, he joined the Millimeter-Wave Technologies Group, IBM Haifa Research Laboratories, as a Research Staff Member, where he has been involved with analog and RF integrated circuit (RFIC) designs for high-speed communication systems. He developed a complimentary synthesis tool to support automated RFIC ground plane buildup. He is currently primarily engaged in the development of digital control circuits to support millimeter-wave transceivers.

Danny Elad (M’98) received the Ph.D. degree in quality assurance and reliability from the Technion Israel Institute of Technology, Haifa, Israel. He possesses more than 20 years of experience in the microwave field. His previous professional experience includes having been with Hewlett-Packard (now Agilent Technolgoies) and with Rafael Advanced Defense Systems, Haifa, Israel, where he was the Microwave Integration Group Leader and Advanced Packaging Researcher. He is currently the Manager of the mm-Wave Technologies Group, IBM Research Laboratories, Haifa, Israel.

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An Interference-Resilient Wideband Mixer-First Receiver With LO Leakage Suppression and I/Q Correlated Orthogonal Calibration Charles Wu, Student Member, IEEE, Yanjie Wang, Borivoje Nikolić, Senior Member, IEEE, and Christopher Hull, Senior Member, IEEE

Abstract—A mixer-first receiver design in 28-nm CMOS is discussed. An embedded 5-bit mixer digital-to-analog converter provides wideband tuneability to enhance device matching and, hence, suppress the multiple local oscillator (LO) harmonics as well as to improve the overall image rejection (IR) performance. Two-stage baseband amplifiers support a 50-MHz baseband bandwidth, which covers the entire channel for long-term evolution non-contiguous carrier aggregation. The proposed design effectively reduce multiple LO harmonics down to below 62 dBm. The system achieves 2.6-dB noise figure, 15-dBm out-of-band 66 dB with third-order input intercept point, and an IR ratio 60-mW power, including five on-chip low dropout regulators. Index Terms—Carrier aggregation (CA), image folding, image rejection (IR), image rejection ratio (IRR), in-phase/quadrature-phase correlated orthogonal calibration (I/Q-COC), intra-band, local oscillator (LO) leakage, long-term evolution (LTE), mixer digital-to-analog converter (MxDAC), mixer-first receivers (RXs).

I. INTRODUCTION

D

UE TO the scarcity of available wireless spectrum and never-ending demand for higher data rates, the concept of dynamic bandwidth allocation is gaining more traction. Some of the modern wireless standards such as long-term evolution advanced (LTE-A) [1] now have the capabilities to dynamically aggregate multiple frequency sub-channels to maximize spectral usage efficiency. Compared to other bandwidth reallocation techniques such as 802.11.ac’s channel bonding, LTE-A’s carrier aggregation (CA) is much more challenging for radio design since the sub-carriers might or might not be allocated in a continuous fashion. The receiver (RX) must be able to sense several desired and potentially weak signals in between strong undesired interferers. This results in unprecedented challenges on Manuscript received July 29, 2015; revised December 02, 2015; accepted February 05, 2016. This paper is an expanded version from the IEEE RFIC Symposium, Phoenix, AZ, USA, May 17–19, 2015. C. Wu and B. Nikolić are with the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94270 USA (e-mail: [email protected]; [email protected]). Y. Wang is with the Mobile Wireless Group, Intel Corporation, Hillsboro, OR 97124 USA (e-mail: [email protected]). C. Hull is with Intel Labs, Hillsboro, OR 97124 USA (e-mail: christopher.d. [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2532867

linearity and noise requirements in long-term evolution (LTE) RX design. Even though various concepts of software-defined radio systems have been demonstrated with great flexibility and tuneability such as [2] and [3], they cannot meet the stringent bandwidth, linearity, and noise requirements imposed by LTE-A, as discussed in [4]. A more conventional solution for LTE CA [5] would dedicate one narrowband RX and one synthesizer to each of the subcarriers. However, it suffers from a large power and area overhead. Moreover, the system design requires careful frequency and layout planning to avoid local oscillator (LO) pulling, due to the poor frequency separation between different sub-channels. An alterative is to downconvert the entire band with a super-hetesrodyne RX [6]. In this case, the first mixer moves the entire channel to baseband, and the second downconversion extracts the few desired sub-carriers with . While this architecture avoids the power and area penalties associated with the use of multiple RXs, it lacks the capability to scale with features and technology due to its inherent complexity. To improve the scalability of previous designs, a digitally assisted RX is proposed in [4], where the image rejection (IR) calibration is implemented on a field programmable gate array (FPGA). Due to complexities of the system having been pushed into the digital domain, the RX frontend could be fairly simple and, hence, has the lowest power number among all existing LTE CA designs. However, the complexity of its digital backend poses a significant disadvantage. This architecture requires dual fast Fourier transform (FFT) blocks and multiple rounds of calculations with irrational numbers with high precision, thus incurring a penalty of large digital power. Moreover, the image rejection ratio (IRR) is tied to the filter’s averaging time. This could result in high downlink latency and limits its application. Finally, a small in-phase/quadrature-phase (I/Q) signal may cause convergence difficulties for the image calibration because the I/Q signal power is the sole term in the denominators of the digital filter’s coefficients [4]. This work proposes a highly linear mixer-first RX to support LTE intra-band CA. A mixer-first design [7] offers superb linearity without a large power penalty. However, it suffers from LO leakage re-radiation because it lacks the backward isolation provided by a low-noise amplifier (LNA). Also, an LTE RX needs to maintain a high IRR to reject the in-band inferences in the scenario of noncontiguous CA noted in [4], whereas mixer-first designs can only achieve limited IRR. In this work, a

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5-bit mixer digital-to-analog converter (MxDAC) is integrated into every core mixer to provide calibration for LO leakage suppression. IRR is also improved by using a new mixed-signal calibration technique called I/Q correlated orthogonal calibration (I/Q-COC). The RX achieves a 2.6-dB noise figure (NF) and 15-dBm third-order input intercept point (IIP3) with 60 mW of power. This paper is an expansion from [9] with a focus on decoupling the noise optimization from impedance match for a mixer-first RX. References [7] and [15] establish an impedance-frequency-translation theory for input match of a mixer-first RX, but their NF is closely tied to the input impedance, which results in a dB. In Section II, we analyze three baseband designs from their impacts on the NF and input impedance and demonstrate that the baseband Op-Amp design is the key in decoupling its noise from its input impedance. Section III presents the detail of the proposed architecture in which the new IR calibration I/Q-COC is thoroughly discussed with its benefits and limitation. Moreover, an expansion about the flicker noise and a novel common-mode (CM) feedback scheme are included in Section III. The measurement results are presented in Section IV, in which we also take a closer look at the noise breakdown in the presence of a strong blocker. II. IMPEDANCE MATCH AND NF OPTIMIZATION To match or not to match is more than just a rhetorical question since input matching has a profound impact on the overall NF. According to [8], the NF of a two-port network can be described by (1)

Fig. 1. General design model for a mixer-first RX architecture.

Fig. 2. Minimum achievable

due to

alone.

match [2], [9]. The rest of this section discusses techniques for accomplishing this for a mixer-first RX shown in Fig. 1. From [7], the NF of a mixer-first RX with eight paths is

(3)

is the minimum achievable NF. and are the two-port model’s input impedance and source conductance, respectively. The minimum NF can be achieved by designing the optimum source admittance equal to a given source admittance . For simplicity, assuming there is no correlation between different noise sources, then

and is the antenna impedance. where The NF is then set by the mixer switch on-impedance , the feedback resistor , and amplifier noise . The input impedance of such an RX can also be described as

(2)

(4)

has nothing to do with 50 , but is instead related to the specific technology node and the architecture in use. This indicates that matching for noise instead of for power would yield a better NF. In [5], where the RF input is coming from a well-defined power splitter network, optimizing for noise match enables the low-band (LB) LNA to achieve an NF slightly above 1 dB, and the entire LB path has a total NF of 2.1 dB. However, an RX that requires the use of a specific external network is very inflexible and, hence, has very limited applications. Therefore, noise match will not be considered. If maximal power transfer is preferred, the NF is restricted by the impedance match, and it makes the NF inherently difficult to be optimized. Most of the RXs published in the literature with 3-dB NF manage to decouple the NF from impedance

where is the input impedance of the baseband trans-impedance amplifier (TIA). First of all, in (4) sets the minimum achievable NF , which is set by the first three terms in (3), (5) for various sizes of . It is easy to see Fig. 2 shows the from (1) that the NF is at least 3 dB for a , with an actual of 3.24 dB. The extra noise is because of noise folded down from high-order harmonics. Therefore, unless a noise cancellation technique like [2] is used, should be chosen to be as small as the particular technology node allows. For a shunt–shunt feedback system, can be described as

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TABLE I COMPARISON TABLE FOR DIFFERENT AMPLIFIER ARCHITECTURES

(6) and are the transconductance and the output where impedance of the amplifier, respectively. For an one-stage operational transconductance amplifier (OTA), due to its high output impedance , the amplifier is loaded by and, hence, (6) is reduced to (7) An Op-Amp, on the other hand, has a low output impedance , therefore, for a one-stage Op-Amp with a voltage gain ,

the third row of Table I. Their expressions are summarized in the fourth row of the table. Finally, the overall input impedances for RXs employing different amplifiers are derived by combining (4) and (7)–(9) and are listed in the last row of Table I. The and expressions of both the OTA and IA contain the inverses of their transconductances ( and ). This suggests that their baseband equivalent noise and input impedance are tied to each other. However, the Op-Amp’s is independent from . Furthermore, even though both the and of an Op-Amp include , the input impedance is primarily determined by . Therefore, an Op-Amp-based TIA succeeds in decoupling the noise optimization from input matching. From (4) and Table I, for an RX with single-stage OTA, (3) can be revised to

(8) Finally, for an inverter amplifier (IA), and lated to intrinsic small-signal device parameters as . With , (6) can then be rewritten as

are reand

(9) is the intrinsic small-signal gain. For CMOS devices with a certain channel length, is a technology constant. When , (9) reduces to , which is similar to (8). However, when , (9) is similar to (7) as . Table I compares the noise sources and input impedances of three types of amplifier structures. From [10], the noise due to the feedback resistors and the input-referred noise of the in the second row of Table I can be simplified amplifiers to two noise sources at the input of the amplifiers, as shown in

(10) Similarly, for an RX with one-stage Op-Amps,

(11) , the NF for an RX Moreover, when with IAs can be derived from (3), (4), and Table I,

(12)

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Fig. 3. NF for OTA, Op-Amp, and IA with . different size of

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and

with a

Fig. 3 shows the simulated NF for a range of values when different types of baseband amplifiers are adpoted. Without losing generality, , , and (for Op-Amp only) are set to 20 , 2/3, and 200 , respectively. From (7) and Table I, the OTA relies on for input matching when is reasonably large. The OTA’s equivalent noise resistor also contains , resulting in an NF that saturates 3 dB beyond a certain value of in Fig. 3. The NF asymptotically approaches 2.77 dB to be precise. It is 3 dB in this case because is assumed in this analysis. On the other hand, with a small , the IA behaves like the OTA in Fig. 3. However, since is a constant related to technology and the devices’ channel length, the IA cannot provide input matching for arbitrarily large . For instance, from Table I, for , and k , k . This can also been seen from (12), where the last term would be negative if . Hence, (12) will no longer be valid when is too large. When is relatively small, the Op-Amp requires a small to match to the ; therefore its NF suffers. On the other hand, as increases, has to be scaled up in proportion to maintain the same . As a result, as shown in Fig. 3, the input-referred noise of the TIA is improved, and the NF approaches the value of as predicted by (5). Interestingly, Fig. 3 shows that in theory both the IA and Op-Amp are able to achieve an NF less than 3 dB. However, in reality the IA requires a daunting value to push the NF below 3 dB, as demonstrated in Fig. 4. To reduce the NF of an IA with from 3.59 to 2.18 dB, the required increases from 81 to 333 mS. Furthermore, to achieve a 1.92-dB NF, the needs to exceed 1000 mS, which requires prohibitively large devices. It is clearly a rapidly diminishing return. Moreover, the RX system linearity would be severely degraded with such a large transconductance. On the other hand, an Op-Amp design does not rely on for the impedance match, therefore with a large , NF can penetrate 3 dB and asymptotically approach . However, to achieve a sub-3-dB NF, a large is required. Fig. 5 shows the NF and required for different values of for a one-stage Op-Amp. From Table I, both the and of an Op-Amp include . To achieve a better NF, it is preferable to have a

Fig. 4. Simulated NF and . with

required for different value of

for an IA

Fig. 5. Simulated NF and stage Op-Amp.

required for different value of

for a one-

large . However, as shown in Table I, a large needs to be compensated with a large to maintain input matching. This is why scales linearly with in Fig. 5. For k , needs to be as large as 50 dB, which is impractical for a one-stage design on a state-of-art CMOS technology with a limited 1-V supply. Fortunately, the above issue can be easily resolved with a two-stage (or multi-stage) Op-Amp design, where the smallsignal gain no longer sets a practical limit. As far as loop stability and system linearity are concerned, the baseband structure should remain as few stages as possible. One subtlety of a multi-stage design is that its is dominated by the noise associated with the first stage . The in a multi-stage design is always smaller than in a single-stage Op-Amp, but it can now be optimized independently of the required . Untangling from the required is crucial because it does not require an excessively large , as in the case of an IA, to achieve a good NF. From (3), (5), (8), and the analysis above, the expressions for the NF and gain of a multi-stage Op-Amp can be shown as

(13)

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For the sake of completeness, it is also important to address the limitations of the above analysis. Equation (10)–(13) do not cover the thermal and flicker noise from the clock generation and distribution circuit, nor do they include the flicker-noise component from the baseband amplifiers. The flicker-noise upconversion in the clock generation has been discussed in [11], and it will not be repeated here. As shall be further covered in Sections III and IV, at low frequency, the NF is dominated by flicker noise from the amplifier and the clock circuit, so it deviates from the value predicted by (13). Therefore, extensive simulations are always recommended and necessary to accurately model the NF of the RX. Lastly, used throughout the above analysis is 2/3, which is only true for long-channel devices in strong inversion. Hence, the results for short-channel transistors in the sub-threshold region could be worse. Nevertheless, the analysis above still serves as a good starting point for optimizing the NF of a mixer-first RX. III. CIRCUIT IMPLEMENTATION A. System Overview

Fig. 6. Simulation results for NF of one- and two-stage amplifiers. (a) Simu. (b) Design lated NF for one- and two-stage Op-Amps with different value values used in plotting (a). TABLE II SAMPLE SET OF DESIGN VALUES FOR A MIXER-FIRST RX WITH A TWO-STAGE OP-AMP TO BREAK THE 3-dB NF BARRIER

(14) Fig. 6(a) compares the simulated NF between a one-stage Op-Amp with that of a two-stage design for various based on (5), (11), and (13). For the two-stage design, is set to 100 mS regardless of the value of . Even though the two-stage Op-Amp saturates to a slightly higher NF with a large , the degradation is quite acceptable: for instance, for M the NF increases from 1.685 dB for a one-stage design to 2.08 dB for a two-stage amplifier. Most importantly, a mixer-first design can now finally break the 3-dB NF bottleneck with a set of practical design values of and . A sample set of such values and the estimated NF have been listed in Table II.

Fig. 7 shows an overview of the proposed RX system. A single-ended RF input signal is down-converted through eight different paths, each of which is controlled by a non-overlapping 12.5% duty-cycle clock. When the path outputs are combined with appropriate weights, the eight-phase down-conversion rejects the third and fifth harmonics. It also reduces the amount of noise folded down from higher order harmonics [7], [8]. Each of the mixer units consists of two parts: a core mixer and an additional 5-bit MxDAC to provide fine-tuning capability. Moreover, the baseband circuit is implemented with two stages of amplification of and to provide the desired large , as discussed in Section II. This allows the use of a large feedback resistor k that contributes very little noise. As shown in Fig. 7, serves as a transconductor, whereas is configured as a TIA. To provide a wide baseband bandwidth (50 MHz) and high slew rate while simultaneously maintaining low power consumption, the baseband low-noise amplifier (BLNA) is designed as an IA. Five low dropout regulators (LDOs) are implemented on chip for better isolation between different supplies. An on-chip clock divider generates all of the required clock phases from an external 4 LO. The digital core of I/Q-COC monitors the digital outputs and fine tunes the code words of MxDACs at start up. Finally, a digital least mean square (LMS) IR filter similar to the one reported in [12] further enhances the IRR during runtime prior to the digital downconversion. Two major issues with a mixer-first RX are LO leakage and limited IRR. LO leakage is a direct result of mismatches among the mixers and LO buffers. In this design, the embedded MxDAC can fine tune the mixer devices to alleviate this issue. Moreover, since the MxDAC improves the matching of the mixers, it improves the second-order input intercept point (IIP2) performance. High IRR, on the other hand, is desirable for an LTE RX since it can reduce image folding from other in-band subcarriers to the desired band. IRR is limited by the phase and the gain mismatches of different paths [12]. The gain mismatch can be calibrated by adjusting the baseband feedback

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Fig. 7. Architectural design and system overview of the proposed passive mixer-first LTE RX system.

resistor corrected.

, but the phase mismatch is more difficult to be

B. I/Q-COC

where and are the variances of the gain and phase mismatches respectively. Appendix A shows the derivation of a harmonic rejection (HR) RX’s IRR sensitivity. The results of (A14) and (A15) are repeated here for the readers’ convenience,

An in-depth discussion of IRR for a typical RX is included in [12], where is described as (15) The IRR sensitivity for a typical RX is thus shown to be (16) (17)

and are the variances of the gain and phase mismatches for an HR RX. Comparing (A14) and (A15) to (16) and (17), one can see that an HR RX has a slightly better IRR than a typical RX. For example, with 1% gain mismatch, (16) predicts that a typical RX will have an IRR of 46 dB, whereas (A14) suggests that an HR RX can be 3 dB better. On the other hand,

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Fig. 8. Basic principles of I/Q vector formation and uncalibrated I/Q vector generation. (a) HR vector summation. (b) 2 Pairs of vectors of HR. (c) Orthogonal vector reference generation. (d) Uncalibrated I\Q generation.

with 1% phase mismatch, (17) predicts a 46-dB IRR for a typical RX, while (A15) predicts a 52-dB IRR for an HR RX. Still, the marginal improvements from (A14) and (A15) are not enough to satisfy the stringent IRR required by LTE-A [4]. Fig. 8 demonstrates the principles of the I/Q vector formation. In an HR RX, as demonstrated in Fig. 8(a) and (b) , there are two pairs of orthogonal vectors (0 and 90 , 45 and 135 ). Also, as shown in Fig. 8(c), a pair of perfectly orthogonal references can be generated by the vector summation and subtraction of a pair of vectors. Reference [12] shows that phase mismatch alone can result in both phase and gain mismatches in the final I/Q products, and a graphical illustration of such a process for an HR RX is demonstrated in Fig. 8(d). To alleviate this issue, the concept of I/Q-COC is proposed by taking advantage of the eight downconverted paths in an HR system. As shown in Fig. 9(a), the pair of 0 and 90 signals can be first used to create the orthogonal references to calibrate the 45 and 135 pair. Afterwards, the calibrated 45 and 135 pair can, in turn, be used to correct the phase mismatch in the 0 and 90 pair. We are not trying to remove the phase mismatches to retain each vector’s absolute phase value, rather we only aim at preserving the 90 phase difference between each orthogonal pair. A complete vector formation after I/Q calibration is demonstrated in Fig. 9(b). The computations of vector summation and subtraction are implemented in the digital domain to avoid introducing additional errors (such as noise or nonlinearity) from an analog adder or subtractor. Finally although the phase values of different paths would change after I/Q-COC, as in Fig. 9(b), the IRR or error vector magnitude (EVM) performance would not be degraded because I/Q-COC only causes the final resulting signal constellation to rotate. This can easily to be re-adjusted in the digital domain. In theory, I/Q-COC reduces the phase mismatches of an HR RX and, hence, can improve both the IRR and harmonic rejection ratio (HRR) with additional calibration iterations on the I/Q

channels. In practice, however, this is not feasible, due to limitation in device matching of a modern CMOS technology. As shown in Fig. 10, for third-order harmonics, the resultant vectors of different downconversion paths rotate by 3 , resulting a 3 phase mismatch amplification. Similarly, to reject the fifth-order harmonic, the phase mismatch requirement would be 5 more stringent. Therefore, to achieve a 60-dB third- or fifth-order HR, the MxDAC has to be excessively large, which would limit the RX’s functional RF frequency range. C. Mixer and MxDAC Fig. 11 details the mixer design. The mixers are biased at 0.65 V. In this work, the mixer switch resistance is substantially reduced to 15 by utilizing 28-nm technology. 28-nm technology provides superior switches with significantly lower on-impedance, as well as reduced switching power. The MxDAC is unit weighted, with each unit cell sized approximately 1% the size of the mixer core, to ensure monotonicity across all DAC codes. D. BLNA The BLNA in Fig. 7 has an inverter-based thick oxide design to supply the required in (13) to achieve a good NF while maintaining high power efficiency. The details of the design are shown in Fig. 12. Table III compares simulated noise contributions from the mixer’s thermal noise and flicker noise from the BLNA and clock generation for different noise bandwidths. As discussed towards the end of Section II and supported by the data in Table III, flicker noise can have a major impact on the overall NF. At low frequencies, in addition to the mixer’s thermal noise, the flicker noises from the BLNA and the clock generation circuit are also significant. Therefore, a large amount of design effort has been invested towards balancing the

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Fig. 9. I/Q calibration procedure and a graphical representation of the vector formation process of I/Q-COC. (a) I\Q-COC calibration procedures. (b) Calibrated I\Q generation.

Fig. 12. Inverter-based baseband LNA

.

TABLE III NOISE CONTRIBUTION OF THE MIXER’ S THERMAL NOISE, FLICKER NOISE FROM THE BLNA, AND CLOCK GENERATION AT DIFFERENT NOISE BANDWIDTHS Fig. 10. Illustration showing why HR is more sensitive to mismatches.

amplifier. The LDO reference comes from a local replica bias. All LDOs operate at 1.5 V. Fig. 11. Mixer core and the 32 slices of the MxDAC.

E. Second-Stage Op-Amp

BLNA’s dimensions and its biasing conditions to achieve the optimum tradeoff between its , system linearity, and its flicker noise performance. Furthermore, to improve power supply rejection ratio (PSRR), the CM amplifier is designed as a low-dropout (LDO)

The second amplifier in Fig. 7 must be able to maintain a high gain and wide bandwidth, which is quite challenging with a 1-V supply. A two-stage design can meet the gain requirement with ease, but it has a limited bandwidth and slew rate due to the Cc’s large size. Moreover, a two-stage amplifier suffers from CM instability with a low supply. Figs. 13 and 14 demonstrate

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Fig. 15. Second-stage amplifier based on ACBC architecture.

Fig. 13. Illustration of the CM instability issue for a two- stage amplifier with a low supply. (a) Differential two-stage TIA with CMFB. (b) CM half circuit of the two-stage TIA.

Fig. 14. Simplified frequency responses (gain and phase) explaining how the undesired positive feedback is competing with the desired CM loop.

this issue. Fig. 13(a) shows a two-stage amplifier in shunt–shunt feedback used as a TIA. A CM amplifier senses the output CM voltage and adjusts the bias of the NMOS loads accordingly. With a 1-V supply, only limited headroom can be allocated for the tail current source, which leads to a poor . Also, due to limited headroom, the input pair and the tail current source are forced to operate with small overdrive voltages, which results in the need for large transistors and, hence, a large parasitic at the virtual ground. For the TIA in Fig. 13(a), the two inverting stages form an undesired wideband CM positive feedback loop, as highlighted in Fig. 13(b). Usually this undesired loop has a loop gain 1 because the input pair’s CM gain is heavily degenerated by the tail current source’s high output impedance [10]. However, in this case, the large together with small lower the output impedance of the current source so that the CM gain of the first stage is still high. This strong positive loop has a negative effect on the overall CM stability. In general, the desired negative CM loop is strong, but narrowband [10]. As shown in Fig. 14, the undesired positive loop will take over when the gain of the desired negative CM loop diminishes. As a result, the phase margin of the CM loop suffers, and the overall CM stability is degraded. An ac-boosting compensation (ACBC) scheme [13] provides a better alternative to the two-stage design in addressing CM stability. A major benefit of the ACBC design is its use of three inverting stages, guaranteeing that global CM feedback is always negative. As shown in Fig. 15, a PMOS input pair is adopted for better flicker noise performance. The input signal is also fed forward to the output stage to create a feed-forward zero, which allows for the use of smaller compensation capacitors and, hence, higher slew rate. The simulated unity-gain frequency of this design is beyond 1.2 GHz based on simulation. Finally, the output

Fig. 16. Chip microphotograph.

stage has a class-AB structure to enable further slew rate and linearity improvements. F. Calibration Procedure The calibration procedure begins with an iterative sweep through all codes of each MxDAC to achieve a balanced suppression of leakages from multiple LO harmonics. The gains of the baseband amplifiers are then fine tuned through to reduce the gain mismatches among different paths. Afterwards, I/Q-COC is applied to the system one orthogonal pair of channels at a time to fine tune the code word to each MxDAC. Finally, the digital LMS filter in the backend is enabled to further enhance the overall IRR in the background. IV. MEASUREMENT RESULTS The design is implemented in a general-purpose 28-nm technology with a 1-V supply and an active area of 460 m by 500 m, as shown in Fig. 16. Fig. 17 shows measured from 250 MHz to 3.5 GHz. This work maintains a good input matching over a wide frequency range, as compared to a noise cancelation RX [2] whose input matching is degraded due to additional loading at the RF terminal from the auxiliary path, To quantify the NF, the conversion gain is first measured at 35 dB. The output noise is then integrated with the off-chip losses are accurately de-embedded. Finally, the NF is extracted by dividing the output noise by the conversion gain. As shown

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Fig. 20. Noise breakdown based on noise simulation with a strong blocker.

Fig. 17. Measured

over wide frequency of operation.

Fig. 21. Measured IIP3 for various two-tone spacings.

Fig. 18. Measured NF from 250 MHz to 3.5 GHz.

Fig. 19. Measured NF with different blocker power level.

in Fig. 18, the measured double-sideband NF integrated up to 10 MHz varies from 2.4 to 2.6 dB. The spot NF for this work at 20-kHz offset is 7.5 dB. From Table III, we believe it is limited by the flicker noise from the BLNA and the clock generation. In comparison, the noise cancelation RX reported in [2] not only is able to achieve a 1.9-dB NF at 1-MHz offset, but also effectively suppresses the flicker noise to achieve a 3.5-dB NF at 20-kHz offset. Fig. 19 shows the measured NF in the presence of a singletone interferer injected 50 MHz from the band edge. The NF is 3.2 dB for a 10-dBm blocker and 6.5 dB for a 0-dBm blocker.

Fig. 20 breaks down simulated noise contribution for the RX in the presence of strong interference. Aside from reciprocal mixing, there are two causes for NF degradation. First, the RX fails to maintain its differentiality. Therefore, it is sensitive to the LDOs’ bias and CM noise. Second, the blocker disrupts mixers’ bias condition, which causes them to generate flicker noise during the large signal transient. In summary, to minimize the NF when strong interferers are present, noise contribution from all components must be considered. Hence we carefully modeled and optimized the noise performances of all LDOs, the bias network, and the CM circuit. NF under a strong blocker can be further enhanced by the noise cancellation technique, as [2] reports a 4.1-dB NF for a 0-dBm blocker. Fig. 21 shows the measured IIP3. The RX achieves an dBm IIP3 for a tone spacing larger than 50 MHz. The LO leakage calibration also improves the IIP2 performance. As shown in Fig. 22, the improvement in IIP2 from the three silicon samples is at least 9.3 dB. The IIP2 observed after calibration is in good agreement with the simulation results (mean value and its distribution), which are overlaid on top of the measurement results in Fig. 22. LO leakage measurements at 1.5-GHz operating frequency are detailed in Fig. 23. The calibration suppresses leakage at multiple LO harmonics from 48 dBm (fourth harmonic—worst case spur without calibration) down to 62 dBm (third harmonic—worst case spur after calibration). While the 10-bit dc tuning DACs in [14] reduce only the fundamental LO tone to 80 dBm, this work manages to suppress multiple LO harmonics all together. Additionally, Fig. 24 shows the IRR at an operating frequency of 2 GHz. The measured IRRs of three chip samples exceed 66 dB across the 100-MHz complex baseband bandwidth, which agrees with the simulation data (included on top of the IRR measurement results).

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most of the amplifier power is due to the requirement to achieve a wide baseband bandwidth (50 MHz) for LTE-A and to maintain system linearity. Overall, at 2 GHz of operation, the RX consumes 50 mW from the local 1-V supplies, or 60 mW from the global 1 and 1.5 V including all the LDOs. Finally, Table IV summarizes the RX performance and compares it with the other state-of-the-art designs. V. CONCLUSION

Fig. 22. Measured IIP2 before and after calibration.

This work has demonstrated a mixer-first RX designed in 28-nm CMOS. Its 5-bit MxDAC provides a wideband tunable match to suppress leakage from multiple LO harmonics. The baseband BLNA together with the ACBC amplifier provides a 50-MHz baseband bandwidth. It supports intra-band CA for LTE-A in a power-efficient manner. The circuit achieves 2.6-dB NF, 15-dBm IIP3, and 35-dB gain with 60-mW power accounting for five separate on-chip LDOs from the 1- and 1.5-V supplies. APPENDIX

Fig. 23. Measured LO leakage at 1.5 GHz for before and after calibration.

Firstly, analysis on the impact of the gain and phase mismatches on IRR for a conventional RX has been shown in [12]. This section analyzes the sensitivity of IRR to the gain and phase mismatch in an eight-path HR RX. If and are the gain mismatches in the 0 , 45 , and 45 paths and and denote the phase mismatches in the same three paths then (A1) (A2) (A3) (A4) Using (A1)–(A3) when the signals from the 0 , 45 , and 45 paths are weighted by , the I channel output can be expressed as

Fig. 24. Measured data for IRR at 2 GHz across three silicon samples.

(A5) Characterized by the same weighting factors, the signal at the Q channel can be constructed with 45 90 and 135 (where the inverted 45 is used instead) and it can then be written as Fig. 25. Power breakdown for the major circuit components at 2 GHz.

Fig. 25 shows a power breakdown of the RX. Up-sizing the clock generation circuitry and the mixer buffers in order to reduce their flicker noise contribution (listed in Table III) results in non-negligible dynamic power dissipation. Also,

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TABLE IV PERFORMANCE SUMMARY AND COMPARISON TABLE

(A6) Knowledge of the signal content in the positive sideband can be extracted from after substituting (A5) and (A6), resulting in

(A10) Output contained the desired signal at the positive half sideband is described by (A8), while (A10) is the undesired image leakage from the other sideband. If we assume that there are no mismatches, (A9) simply reduces to , while (A10) disappears. Therefore, (A11)

(A7) Due to the gain and phase mismatches, (A7) contains both the desired signal and the image leakage. By collecting the common terms, and (A7) can be rewritten as

(A8)

Recognizing the fact that the gain or the phase mismatches of different paths have the same variances for statistical distribution ( for gain and for phase), the sensitivity of the IRR to gain and phase mismatches can then be derived from (A9)–(A11) as

(A12)

(A9) (A13)

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(A14)

(A15)

ACKNOWLEDGMENT The authors would like to thank R. Sadhwani, S. Ramon, P. Schwendt, and O. Korobeynikov, all with the Intel Corporation, and B. Zimmer and N. Narevskey, both with the Berkeley Wireless Research Center, for technical support and discussion. The authors also appreciate A. Wang and C. Hu for their support. REFERENCES [1] 3 Generation Partnership Project (3GPP), Technical Specification Group Radio Access Network, Feasibility Study for Further Advancements for E_UTRA (LTE-Advanced) (Release 11), 3GPP TR 36 912 v11.0.0, Sep. 2012. [2] D. Murphy et al., “A blocker-tolerant, noise-cancelling receiver suitable for wideband wireless applications,” IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 2943–2963, Dec. 2012. [3] C. Wu and B. Nikolic, “A 0.4 GHz-4 GHz direct RF-to-digital multi-mode receiver,” in Proc. IEEE ESSCIRC, Sep. 2013, pp. 275–278. [4] S. Hwu and B. Razavi, “An RF receiver for intra-band carrier aggregation,” IEEE J. Solid-State Circuits, vol. 50, no. 4, pp. 946–961, Apr. 2015. [5] M. Mikhemar et al., “A rel-12 2G/3G/LTE-advanced 3CC receiver,” in IEEE RFIC Symp., May 2014, pp. 143–146. [6] L. Sundstorm et al., “A receiver for LTE rel-11 and beyond supporting non-contiguous carrier aggregation,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2013, pp. 336–337. [7] C. Andrews and A. C. Molnar, “A passive mixer-first receiver with digitally controlled and widely tunable RF interface,” IEEE J. SolidState Circuits, vol. 45, no. 12, pp. 2696–2708, Dec. 2010. [8] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuit. Cambridge, U.K.: Cambridge Univ. Press, 1998. [9] C. Wu, Y. Wang, B. Nikolic, and C. Hull, “A passive-mixer-first receiver with LO leakage suppression, 2.6 dB NF, 15 dBm wide-band IIP3 66 dB IRR supporting non-contiguous carrier aggregation,” in IEEE RFIC Symp., May 2015, pp. 155–158. [10] P. G. Grey, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuit, 5th ed. New York, NY, USA: Wiley, 2009. [11] C. Wu, E. Alon, and B. Nikolic, “A wideband 400 MHz-4 GHz direct RF-to-digital multi-mode receiver,” IEEE J. Solid-State Circuits, vol. 47, no. 6, pp. 1639–1652, May 2014. [12] C. Heng, M. Gupta, S. Lee, D. Kang, and B. Song, “A CMOS TV tuner/demodulator IC with digital image rejection,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2525–2535, Dec. 2005. [13] X. Peng and W. Sansen, “AC boosting compensation scheme for lowpower multistage amplifiers,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 2074–2079, Nov. 2004. [14] S. Jayasuriya, D. Yang, and A. Molnar, “A baseband technique for au80 dBm in wideband tomated LO leakage suppression achieving passive mixer-first receivers,” in IEEE Custom Integr. Circuits Conf., Sep. 2014, pp. 1–4. [15] C. Andrews and A. Molnar, “A passive-mixer-first receiver with base6 dB NF and 27 dBm band-controlled RF impedance matching wideband IIP3,” in IEEE Int. Solid-State Circuits Conf. Dig., 2010, pp. 46–47. [16] J. Borremans et al., “A 40 nm CMOS 0.4–0.6 GHz receiver resilient to out-of-band blockers,” in IEEE Int. Solid-State Circuits Conf. Dig., 2011, pp. 62–64.

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[17] I. Lu et al., “A SAW-less GSM/GPRS/EDGE receiver embedded in a 65 nm CMOS SoC,” in IEEE Int. Solid-State Circuits Conf. Dig., 2011, pp. 364–366. [18] D. Murphy et al., “A blocker-tolerant wideband noise-cancelling receiver with a 2 dB noise figure,” in IEEE Int. Solid-State Circuits Conf. Dig., 2012, pp. 74–75. [19] J. Park and B. Razavi, “A 20 mW GSM/WCDMA receiver with RF channel selection,” in IEEE Int. Solid-State Circuits Conf. Dig., 2014, pp. 356–357. [20] H. Chen and H. Hashemi, “Reconfigurable receiver with radio-frequency current-mode complex signal carrier aggregation,” IEEE J. Solid-State Circuits, vol. 50, no. 12, Dec. 2015. Charles Wu (S’09–M’14) received the B.S. and Ph.D. degree from the University of California at Berkeley, Berkeley, CA, USA, in 2007 and 2014, respectively. From 2007 to 2009, he was an Analog Designer with the Broadcom Corporation, where he designed analog front-ends modules and continuous-time sigma–delta ADCs for DSL cable modems and audio CODEX. In the summer of 2010, he was an Engineering Intern with the Agilent Corporation, where he explored ground-breaking techniques for high-speed ADC sampling front-ends. From 2011 to 2013, he was an Intern with the Intel Corporation, where he designed a next-generation receiver architecture intended for LTE-Advanced. His research interests include wide dynamic-range receiver design for software-defined radio application and high-speed ADC design techniques. Dr. Wu was the recipient of the Best Young Scientist Paper Award of the European Solid-State Circuits Conference in 2013.

Yanjie Wang received the B.Eng. degree in electrical engineering from Sichuan University, Sichuan, China, in 1995, the M.A.Sc. degree from Carleton University, Ottawa, ON, Canada, in 2002, and the Ph.D. degree from the University of Alberta, Edmonton, AB, Canada, in 2009. From 1999 to 2002, he was an ASIC Design Engineer with Nortel Networks and AMCC Canada, Ottawa, ON, Canada. In 2007, he was a Graduate Research Scholar with the Berkeley Wireless Research Center, University of California at Berkeley, Berkeley, CA, USA. Since 2008, he has been with the Mobile Wireless Group, Intel Corporation, Hillsboro, OR, USA. His main research interests are CMOS transceivers for WiFi/WiMAX and 60-GHz applications. Dr. Wang is a Member of the IEEE Solid-State Circuits Society and the IEEE Microwave Theory and Techniques Society (IEEE MTT-S). He serves on the Technical Program Committee of the IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

Borivoje Nikolić (S’93–M’99–SM’05) received the Dipl.Ing. and M.Sc. degrees in electrical engineering from the University of Belgrade, Belgrade, Serbia, in 1992 and 1994, respectively, and the Ph.D. degree from the University of California at Davis, Davis, CA, USA, in 1999. In 1999, he joined the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USa, where he is currently a National Semiconductor Distinguished Professor of Engineering. He coauthored Digital Integrated Circuits: A Design Perspective, 2nd Edition (Prentice-Hall, 2003). His research activities include digital, analog and RF integrated circuit design and very large scale integration (VLSI) implementation of communications and signal-processing systems. Dr. Nikolić was a Distinguished Lecturer of the IEEE Solid-State Circuits Society (2014–2015). He was the recipient of the National Science Foundation (NSF) CAREER Award in 2003, the College of Engineering Best Doctoral Dissertation Prize and Anil K. Jain Prize for the Best Doctoral Dissertation in Electrical and Computer Engineering of the University of California at Davis in 1999, and the City of Belgrade Award for the Best Diploma Thesis

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in 1992. For work with his students and colleagues, he has been the recipient of Best Paper Awards at of the IEEE International Solid-State Circuits Conference, Symposium on VLSI Circuits, IEEE International SOI Conference, European Solid-State Device Research Conference, European Solid-State Circuits Conference, S3S Conference, and the ACM/IEEE International Symposium of Low-Power Electronics.

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES

Christopher Hull (A’99–M’03–SM’12) received the Ph.D. degree from the University of California at Berkeley, Berkeley, CA, USA, in 1992. In 1992, he joined Rockwell Semiconductor Systems, Newport Beach, CA, USA. In 1998 he joined Silicon Wave, San Diego, CA, USA, In 2001, he joined Innocomm Wireless, which was subsequently acquired by National Semiconductor. In May 2003, he joined the Wireless Networking Group, Intel Corporation, San Diego, CA, USA. In June 2005, he moved to Hillsboro OR, USA. In 2013, he spent one year on international assignment in Munich, Germany, where he worked closely with his colleagues from Intel Mobile Communications on 4G cellular transceivers. In May 2015, he became the Director/Sr. Principal Engineer for Intel Labs, Hillsboro, OR, USA.

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A Sub-1-V 194- W 31-dB FOM 2.3–2.5-GHz Mixer-First Receiver Frontend for WBAN With Mutual Noise Cancellation Mustafijur Rahman, Student Member, IEEE, and Ramesh Harjani, Fellow, IEEE

Abstract—A low-power low-noise 0.7-V mixer-first RF frontend for an IEEE 802.15.6 narrowband receiver is presented, which uses frequency translated mutual noise cancellation based on passive coupling. Unlike traditional noise-cancelling techniques, we perform symmetrical noise cancellation of a fully differential structure where each path cancels the noise of the other at IF. This prototype design realized in TSMC’s 65-nm CMOS tackles the noise figure and power consumption problems of sub-1-V mixers. The figure of merit is 10 dB higher and the power consumption is 194 W, which is 0.5 lower than the state-of-the-art. The local oscillator power used is 14 dBm. Index Terms—802.15.6, low power, noise cancellation, receiver, RF, wireless body area network (WBAN).

I. INTRODUCTION

L

OW-POWER IEEE 802.15.6 standard based wireless body area network (WBAN) RF frontends are starting to proliferate as the standard matures [1]–[3]. A WBAN is a network of medical devices on, in, or around the human body employing wireless connectivity. WBAN promises to revolutionize health care in the near future. A typical WBAN scenario includes a network of medical sensors for monitoring vital statistics such as blood pressure, heart rate, and actuators such as insulin pumps, cardiac pacemakers, etc. By integrating these devices with a local base unit, e.g., a cell phone, WBAN will provide doctors with real time data and enable remote patient monitoring. This will lead to reduced health care cost and early detection and prevention of diseases. Remote patient monitoring will significantly benefit the aging population in regions where there is a scarcity of clinics and clinicians. Further, the wireless connectivity can facilitate untethered patient monitoring without limiting patient movement. However, all these devices require radios, which can transmit and receive Manuscript received August 01, 2015; revised December 16, 2015 and February 20, 2016; accepted February 23, 2016. Date of publication March 16, 2016; date of current version April 01, 2016. This work was supported by the Semiconductor Research Corporation (SRC) through the Texas Analog Center of Excellence at the University of Texas at Dallas (Task ID: 1836.98). This paper is an expanded version from the IEEE RFIC Symposium, Phoenix, AZ, USA, May 17–19, 2015. The authors are with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2536603

signals in order to maintain wireless connectivity. As most of these devices are likely to be powered by small batteries, their radios have to be extremely power efficient. The IEEE 802.15.6 standard provides the necessary specifications of these low-power radios [4]. As a significant percentage of these sensors and actuators have large digital content, the overall power is minimized via technology scaling and employing sub-1-V RF circuits. In this paper, a sub-1-V low-power low-noise RF downconverter for an IEEE 802.15.6 narrowband receiver that operates in all the three bands viz. industrial–scientific–medical (ISM), U.S. medical body area networks (MBANs), and European MBAN bands spanning 2.3–2.5 GHz is presented. The traditional bottleneck for sub-1-V operation has been the mixer. Existing low-voltage mixers can be classified as bulk injection, switching, or square law mixers. Bulk injection mixers need a large local oscillator (LO) and are sensitive to process variations [5]. Switching mixers require an even larger LO close to 0 dBm making them power hungry [6]–[8]. Recently proposed nonlinearity based [9] and transconductance based mixers [10] use smaller LOs. However, these mixers have relatively high noise figures (NFs) (11.2 dB [9], 19 dB [10]) and high power consumption (380 W [9], 1 mW [10]). A subset of this work has been presented in [11]. Here we have expanded on that work [11] in additional analysis, new simulation results, derivations of circuit-level specifications from the standard, the impact of process variation, and mismatch using Monte Carlo simulations and test setup details. Section II provides a system overview of the receiver. Section III discusses the wireless standard specifications and its implications for the receiver specifications. Section IV presents circuit design details. Section V discusses nominal circuit simulation results. Section VI describes the impact of process variation and mismatch. Section VII provides measurement results. Finally, Section VIII provides the overall conclusion. II. SYSTEM OVERVIEW A block diagram for a traditional switching mixer is shown in Fig. 1(a). This mixer requires a large LO to achieve a low-NF and good conversion gain not making it suitable for low VDD operation. However, active mixers have poor NF due to flicker noise and thermal noise folding [12], [13] and, therefore, a lownoise amplifier (LNA) preceding the mixer is traditionally employed at the cost of increased power. We propose an active

0018-9480 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

RAHMAN AND HARJANI: SUB-1-V 194- W 31-dB FOM 2.3–2.5-GHz MIXER-FIRST RECEIVER FRONTEND

Fig. 1. Block diagrams for: (a) traditional switching mixer and (b) traditional noise cancellation technique.

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MBAN band for medical devices. The MBAN frequency band is less crowded than ISM and, hence, is particularly suitable for medical applications where reliability is critical. The protocol has been designed for good reliability, security and quality of service, and support for multiple nodes, all of which are critical for medical devices. As compared to Bluetooth low energy (BLE) [17], this protocol has higher data throughput, a longer line of sight range, and supports a higher number of channels. We propose a low IF architecture for the receiver because a zero IF architecture suffers from flicker noise and requires dc offset correction. The system-level specifications for the receiver, as well as the circuit-level specifications that were derived, are discussed in the below. A. System-Level Specifications

Fig. 2. Block diagram for proposed design using FTMNC.

transconductance mixer that uses low LO power to achieve low VDD operation, as shown in Fig. 2. The output signal-to-noise ratio (SNR) of a system can be expressed as , where and is the output noise power. Low VDD operation decreases and, hence, increases the effective NF. Therefore, noise-cancellation techniques become critical at lower VDDs. As shown in Fig. 1(b), traditional noise-cancelling techniques [14], [15] use an auxiliary path to cancel the noise of the main signal path, but the noise of the auxiliary path still remains uncancelled. In this paper, a frequency translated mutual noise cancelling (FTMNC) mixer with subthreshold MOS operation is proposed. Unlike traditional techniques, we perform symmetrical noise cancellation of a fully differential structure where each path cancels the noise of the other side after downconversion to IF. The RF and LO is combined and applied to the mixer in differential form. A passive noise coupling mechanism couples the noise current of one side of the differential topology to the other side, thereby making it common mode, but retains the signal voltage in the differential mode. Each end has a transconductance mixer, which down converts the RF to baseband by generating in-phase IF signals, which are added at the baseband. Noise from each half, on the other hand, are common mode and gets down converted out of phase (by LO and LO) and, hence, gets cancelled due to the addition after frequency translation [15]. In this prototype, the RF and LO combination is done off-chip for testing ease. In the future, a passive zero power cyclic combiner used in [9] may be used for an on-chip implementation. III. RECEIVER SPECIFICATIONS The IEEE 802.15.6 narrowband protocol [16] includes the ISM band, as well as the new U.S. MBAN and European (EU)

The IEEE 802.15.6 narrowband standard [4] was recently ratified and, therefore, we enlist the system-level specifications for the receiver. In particular, we focus on the specifications that affect receiver RF circuit performance. In Section III-B, we translate these system-level specifications to circuit- and block-level specification for the receiver. • Modulation and frequency range: the standard specifies differential quadrature phase-shift keying (DQPSK) and DQPSK modulation operated at a symbol rate of 600 ks/s as the modulation schemes. The U.S. MBAN band spans from 2.36 to 2.4 GHz and the U.S. Federal Communications Commission (FCC) Part 15 unlicensed 2.4-GHz band spans from 2.4 to 2.4835 GHz with a 1-MHz channel spacing providing a total of 118 channels across both bands. The standard also includes the EU MBAN, which spans from 2.484 to 2.5 GHz. • Receiver sensitivity: the strictest sensitivity specification is 92 dBm at a data rate of 121.4 kb/s and the lowest is 83 dBm at data rate of 971.4 kb/s. • Adjacent channel rejection (ACR): the highest ACR specification is 17 dB for a 121.4-kb/s data rate and the lowest specification is 9 dB for a 971.4-kb/s data rate. B. Circuit-Level Specifications The circuit-level specifications for the receiver have been systematically derived from the system requirements specified by the IEEE 802.15.6 narrowband standard described in Section III-A. In particular, a detailed derivation for the receiver NF and linearity is described below. 1) NF: The required NF of the receiver can be evaluated using the following equation [18]: Sensitivity

(1)

is the NF, is the channel bandwidth i.e., 1 MHz, where and is the required SNR. At a data rate of 971.4 kb/s, the specified sensitivity is 92 dBm and the SNR needed is 11.2 dB. Using these values in (1) results in maximum NF of 19.2 dB. After considering all the acceptable data rates, this NF specification resulting from a data rate of 971.4 kb/s is the most stringent. We further provide margin for implementation loss in the RF frontend and digital baseband and, therefore, target a NF of about 10 dB.

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A. Signal Path Driven by the LO, the of transistors M1 and M2 are linear time variant and periodic with LO frequency and may be expressed as a Fourier series as follows: (4) (5) (6) (7) Fig. 3. Circuit diagram of the FTMNC mixer with signal addition.

2) Linearity: ACR is the ratio of the interfering signal’s power in the adjacent channel to the desired signal power. According to the 802.15.6 standard specification [4], the desired signal’s strength should be set 3 dB above the rate-dependent sensitivity and the power of the interfering signal should be raised until a 10% packet error rate has been achieved for physical layer service data unit (PSDU) length of 255 octets. At a data rate of 971.4 kb/s, the specified ACR is 9 dB, sensitivity is 83 dBm, and the SNR required is 11.2 dB. We provide a margin of 10 dB to account for other non-idealities and, therefore, target an SNR of 21.2 dB. This sets a limit for third-order intermodulation (IM3) corruption to be 21.2 dB. We represent the desired, adjacent, and alternate channel by , , and , respectively. Therefore, IM3 corruption[18] may be expressed as follows in (2): (2) dBm

(3)

dB and a sensitivity dBm in Using an (2), we find the value for . Using this value in (3) we find that the required input third-order intercept point (IIP3) is 55.9 dBm. After considering all the acceptable data rates, this IIP3 resulting at a data rate of 971.4 kb/s is the most stringent. Since the IIP3 value dictated by adjacent channel specifications is quite relaxed, we choose our target dBm to meet the more stringent out-of-band blocker specifications [2]. IV. CIRCUIT DESIGN The circuit-level implementation is shown in Fig. 3. The transconductance mixer is implemented by using an NMOS transistor in the common gate configuration with a resistive load. The transistor is self-biased via gate-to-drain resistive feedback and maintained in subthreshold for a V. The gate is ac grounded with a large capacitor. The input RF LO and RF LO is applied in true differential form using an on-chip matching network implemented with a center-tapped symmetric differential inductor, which also acts as a noise coupler, as discussed later. Further, the inductor tunes out the of the transistors and improves the transistor , which otherwise degrades in subthreshold. The circuit behavior with respect to signal and noise are discussed separately below.

As shown in (4) and (5), the fundamental harmonics of and are of opposite sign because the LO is applied in differential form. Since the RF signals are also applied in differential form, both and get down converted to the positive quantity at IF, as shown in (6) and (7). As shown in Fig. 3, the down-converted signals are in-phase and when summed together results in signal addition at the IF output. Due to the differential form of the input signal, the center-tapped symmetric inductor behaves as a differential inductor and forms a matching network at the input. B. Noise Path The noise of the transistors M1 and M2 is cyclostationary in nature, i.e., noise has a periodically time-varying statistics. This occurs due to the presence of a large periodically time-varying LO signal, which affects noise in two ways. First, M1 and M2 have a periodically time-varying operating point, which modulates the noise source and, second, the noise transfer function (NTF) from the noise source to the output is periodically time varying, which leads to aliasing in the frequency domain [19], [20]. Consequently there is a strong correlation in the noise power spectral density (PSD) at frequencies separated by integral multiples of . The equivalent circuit model for M1’s NTF is shown in Fig. 4. The wide sense stationary (WSS) noise current of M1 at A gets converted to cyclostationary noise at B due to the presence of LO resulting in strong correlation at frequencies separated by . This noise current acts as a single-ended excitation to the center-tapped symmetric inductor, which now behaves as a transformer. A simplified layout of the transformer and an equivalent direct model [21], [22] is shown in Fig. 5. entering terminal P of the primary side induces an opposite current in the adjacent secondary trace according to Faraday’s law, which, however, enters terminal S due to the interleaved winding pattern. Consequently, the noise current of M1 becomes common mode in both ends of the differential architecture. The induced current can be expressed as , where and are the mutual and self inductances of the secondary, respectively. Further, as shown in Fig. 4, the noise also gets bandpass filtered at RF frequency at point C due to the bandpass nature of the tuned transformer [21]. The bandpass filtered noise of M1 at C gets downconverted to IF at D, as shown in Fig. 4. However, being downconverted by LO, noise at D is negatively correlated with the noise at B. The noise at B and D when summed together results in noise cancellation at the IF output at E. Thus, the sign reversal of the LOs applied to the left and right provide the phase reversal needed

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Fig. 6. (a) M1’s single-ended noise current undergoing resistive division through the transformer. (b) Simplified model of the noise current division.

C. Noise-Cancellation Ratio

Fig. 4. Equivalent circuit model for M1’s current NTF and the flow diagram for the noise-cancellation mechanism.

As shown in Fig. 6(a), the noise current of M1 acts as a singleended excitation to the center-tapped differential inductor with its center tap connected to ground. Therefore, the inductor acts a transformer. The grounded center tap prevents the direct noise of M1 to flow to the secondary connected to M2. Instead, an induced noise current flows in the secondary by virtue of mutual inductance. The impedances on the secondary side, i.e., looking into M2 and the upconverted source resistance , are now visible at the primary side due via the mutual inductive coupling. Therefore, the noise current of M1 undergoes a resistive division in between of M1, of M2, upconverted source impedance of primary, and upconverted source impedance of secondary, as shown in the simplified circuit model in Fig. 6(b). In this design, , where is the source impedance. The ratio of noise currents i.e., or the noise-cancellation ratio (NCR) may be expressed as follows: (8)

Fig. 5. Simplified layout and circuit model for the center-tapped symmetric inductor acting as an inductor for differential signal, but as a transformer for single-ended noise current.

for noise cancellation. Note that there is mutual cancellation where the noise of M2 is cancelled in a similar fashion. This becomes possible because the transformer acting as noise coupler is a passive reciprocal network. Unlike active noise cancellation that uses an active, but noisy auxiliary path [14], [15], [23], our passive approach consumes zero power and has negligible noise contribution. The baseband adder is implemented using PMOS source followers (M3 and M4) with a resistive load to reduce flicker noise. The gates are biased to ground with resistors. The single-ended baseband output is buffered by an on-chip driver with 50- matched output to drive test instruments.

A perfect match at the front end will require leading to an NCR of 33.33%. However, if an of 10 dB is sufficient, then we may set and this will improve the NCR to 50%. Therefore, a tradeoff between input matching and the NCR can be made. In the theoretical limit, if , then the NCR becomes 100%. This is not practically viable because of the infinite requirement for the inductor. Fig. 7 shows the plot of the NCR versus the transformed value of the source resistance. The differential inductor has a simulated of 0.87 and of 17.6 at 2.4 GHz, as shown in Fig. 8(a). Fig. 8(b) shows the simulated mutual inductance ( ) as 2.8 nH and a self inductance ( ) as 3.2 nH. D. Noise Analysis The drain current of M1 and M2 biased in saturation in the subthreshold region [24] is given by the following expression: (9) where

,

are process-dependent parameters and . This mixer exploits the exponential dependence

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Fig. 7. Simulation of NCR versus upconverted source resistance ( ).

Fig. 9. (a) NTF paths from channel noise source of M1. (b) STF paths from PORT1. (c) NTF curves from channel noise source of M1. (d) STF curves from PORT1.

Since the noise of M1 and M2 are uncorrelated, the total noise voltage PSD at IF due to translation from RF is expressed as follows: Fig. 8. Simulation of coupling coefficient ( ), quality factor ( ), self inductance ( ), and mutual inductance ( ) of the center-tapped symmetric differential inductor versus frequency.

of drain current on and, therefore, the conversion gain of the mixer can be evaluated by using the second-order term in the Taylor-series expansion of the exponential in (9). The conversion gain of a single-ended stage excluding the matching network gain is expressed as follows: (10) The total conversion gain of the mixer including the matching network gain is expressed as follows: (11) The RF channel noise of a MOS biased in subthreshold consists of mainly shot noise where the current PSD may be expressed as [24]. The IF noise voltage at IF1 and IF2 due to translation of the RF channel noise of M1 can be expressed as follows: (12) (13) is the NCR, as expressed in (8). Since noise at IF1 where and IF2 due to M1 is negatively correlated, the total IF noise due to M1 can be evaluated by adding (12) and (13) as voltages as follows: (14)

(15) As shown in (14), the noise voltage of each MOS is reduced times its original noise after addition at IF and is voltage. As a result, as shown in (15), the total noise PSD of M1 and M2 is reduced after addition at IF and is times the original noise PSD. As discussed in Section IV-C, design values for the NCR vary between 0.33 to 0.5, leading to 4 reduction in the effective noise power at IF. V. NOISE CANCELLATION SIMULATIONS In order to verify the frequency translated mutual noise cancellation, SpectreRF PSS and PNOISE simulations were used to plot the NTF from the channel noise of transistor M1 at RF to nodes , , and at IF viz. NTF1, NTF2, and NTF, respectively, as shown in Fig. 9(a) and (b). The NTF is the difference between NTF1 and NTF2 verifying noise cancellation of M1. Similarly, the signal transfer function (STF) from PORT1 at RF to nodes , , and at IF viz. STF1, STF2, and STF, respectively, have been simulated using PSS and PAC, as shown in Fig. 9(c) and (d). The STF is the sum of STF1 and STF2 verifying signal addition. This noise cancellation and signal addition leads to an improved NF. The NF improvement is 3 dB in simulations for the circuit in Fig. 9. In this prototype, the simulated NCR is approximately 33%, as shown in Fig. 9(b). This is in close agreement with our analytical expression in (8), which shows that for a good match at input . VI. IMPACT OF PROCESS VARIATION Monte Carlo simulations were performed to quantify the effect of process variation and device mismatch on the NF and the gain of the receiver frontend. As shown in Fig. 10, the standard deviation of the NF at GHz is 0.086 dB due to process variation and 0.00076 dB due to device mismatch. As shown in Fig. 11, the standard deviation of the conversion gain

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Fig. 13. Die micrograph of the receiver frontend. Fig. 10. Monte Carlo simulation results of NF including process variation and device mismatch.

Fig. 14. Test setup of the receiver frontend. Fig. 11. Monte Carlo simulation results of gain including process variation and device mismatch.

Fig. 12. (left) Process corner simulation of gain and NF versus temperature. (right) Measured NF and gain over five samples.

Fig. 15. Measured and simulated conversion gain, frequency.

, and NF versus RF

at GHz is 0.073 dB due to process variation and is 0.005 dB due to device mismatch. Fig. 12 (left) shows simulated gain and NF versus temperature for TT, SS, and FF corners, and Fig. 12 (right) shows the measured variation of gain and NF over five samples. We note that the architecture performance is robust to process variation and device mismatch. VII. MEASUREMENT RESULTS The prototype was implemented in TSMC’s 65-nm CMOS and occupies an area of 0.45 mm . The die micrograph is shown in Fig. 13 and the test setup is shown in Fig. 14. The chip was tested by probing the die using RF probes. The RF LO and RF LO signals were generated using an offchip power combiner followed by an offchip balun. The LO was generated using Agilent’s 8257D signal generator. The measurements were done using an R&S ZVA67 vector network analyzer. The NF measurements were done using an Agilent 346C noise source and an R&S FSW43 spectrum analyzer with an NF personality. All losses have been de-embedded in the measurements provided here.

Fig. 16. Measured IIP3 and two-tone test output spectrum.

Fig. 15(a) shows the measured and simulated and conversion gain at a 20-MHz IF versus the RF frequency spanning 2.3–2.5 GHz. Fig. 15(b) shows the measured NF and simulated NFs with and without noise cancellation at a 20-MHz IF versus the RF frequency spanning 2.3–2.5 GHz. The measured NF curve tallies quite well with the simulated NF curve. The simulated NF is a spot NF at 20-MHz IF. The minimum NF of 6.55 dB occurs at 2.5-GHz RF with a conversion gain of 20.6 dB. The NF at lower IF is deteriorated by the flicker noise of the buffer

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TABLE I PERFORMANCE COMPARISON

The mixer has the lowest NF and power consumption and its FOM is 10 dB higher than the state-of-the-art. REFERENCES

Fig. 17. Chart comparing FOM, LO power, and NF.

and adder and also due to gain reduction by the IF coupling capacitance, which forms a high-pass filter. The simulated spot NF at 1-MHz IF is 15 dB. Fig. 16 shows a two-tone output with an IIP3 of 9.24 dBm meeting blocker specifications [2]. The performance of the prototype is summarized and compared in Table I. The proposed circuit has the lowest NF while consuming the lowest power of 194 W from a 0.7-V VDD. The proposed design has the highest figure of merit (FOM) of 31 dB, which is 10 dB higher than the state-of-the-art [9]. Fig. 17 shows a 3-D bar chart for the various designs displaying FOM, LO power, and NF. It is clearly visible that the proposed design improves on all three performance specifications. VIII. CONCLUSION We have proposed a frequency-translated mutual noise-cancellation technique that improves the NF and power consumption of transconductance mixers suitable for sub-1-V operation by exploiting the cyclostationary property of noise. Traditional noise-cancellation techniques employ active devices in the auxiliary path whose noise remain uncancelled. In contrast, the proposed noise-cancellation technique is mutual where one path cancels the noise of other and vice versa. This is achieved by employing a center-tapped symmetric differential inductor as a passive noise coupler, which enables coupling from both ends by virtue of its reciprocity. The noise coupler behaves as a differential inductor for differential input signal, thereby contributing in the input matching network, but as a transformer for singleended noise, thereby contributing in noise cancellation. Further, it consumes zero power and contributes negligible noise. The mixer is operational at 0.7 V with LO power of only 14 dBm.

[1] M. Rahman, M. Elbadry, and R. Harjani, “An IEEE 802.15.6 standard compliant 2.5 nJ/bit multiband WBAN transmitter using phase multiplexing and injection locking,” IEEE J. Solid-State Circuits, vol. 50, no. 5, pp. 1126–1136, May 2015. [2] Y. H. Liu et al., “A 1.9 nJ/b 2.4 GHz multistandard (Bluetooth low energy/Zigbee/IEEE802.15.6) transceiver for personal/body-area networks,” in IEEE Int. Solid-State Circuits Conf., Feb. 2013, pp. 446–447. [3] M. Rahman, M. Elbadry, and R. Harjani, “A 2.5 nJ/bit multiband (MBAN & ISM) transmitter for IEEE 802.15.6 based on a hybrid polyphase-MUX/ILO based modulator,” in IEEE Radio Freq. Integr. Circuits Symp., Jun. 2014, pp. 17–20. [4] IEEE Standard for Local and Metropolitan Area Networks – Part 15.6: Wireless Body Area Networks, IEEE Standard 802.15.6-2012, Feb. 2012, pp. 1–271. [5] K. H. Liang, H. Y. Chang, and Y. J. Chan, “A 0.5–7.5 GHz ultra low-voltage low-power mixer using bulk-injection method by 0.18- m CMOS technology,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 7, pp. 531–533, Jul. 2007. [6] C. Hermann, M. Tiebout, and H. Klar, “A 0.6-V 1.6-mW transformer-based 2.5-GHz downconversion mixer with 5.4-dB gain and 2.8-dBm IIP3 in 0.13- m CMOS,” IEEE Trans. Microw. Theory Techn., vol. 53, no. 2, pp. 488–495, Feb. 2005. [7] H. H. Hsieh and L. H. Lu, “Design of ultra-low-voltage RF frontends with complementary current-reused architectures,” IEEE Trans. Microw. Theory Techn., vol. 55, no. 7, pp. 1445–1458, Jul. 2007. [8] V. Vidojkovic, J. van der Tang, A. Leeuwenburgh, and A. H. M. van Roermund, “A low-voltage folded-switching mixer in 0.18- m CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1259–1264, Jun. 2005. [9] J. Deguchi, D. Miyashita, and M. Hamada, “A 0.6 V 380 W 14 dBm LO-input 2.4 GHz double-balanced current-reusing single-gate CMOS mixer with cyclic passive combiner,” in IEEE Int. Solid-State Circuits Conf., Feb. 2009, pp. 224–225. [10] M. A. Abdelghany, R. K. Pokharel, H. Kanaya, and K. Yoshida, “Lowvoltage low-power combined LNA-single gate mixer for 5 GHz wireless systems,” in IEEE Radio Freq. Integr. Circuits Symp., Jun. 2011, pp. 1–4. [11] M. Rahman and R. Harjani, “A 0.7 V 194 W 31 dB FOM 2.3–2.5 GHz RF frontend for WBAN with mutual noise cancellation using passive coupling,” in IEEE Radio Freq. Integr. Circuits Symp., May 2015, pp. 175–178. [12] H. Darabi and A. A. Abidi, “Noise in RF-CMOS mixers: A simple physical model,” IEEE J. Solid-State Circuits, vol. 35, no. 1, pp. 15–25, Jan. 2000. [13] W. Cheng, A. J. Annema, J. A. Croon, and B. Nauta, “Noise and nonlinearity modeling of active mixers for fast and accurate estimation,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 2, pp. 276–289, Feb. 2011. [14] S. C. Blaakmeer, E. A. M. Klumperink, D. M. W. Leenaerts, and B. Nauta, “Wideband balun-LNA with simultaneous output balancing, noise-canceling and distortion-canceling,” IEEE J. Solid-State Circuits, vol. 43, no. 6, pp. 1341–1350, Jun. 2008. [15] D. M. Murphy et al., “A blocker-tolerant, noise-cancelling receiver suitable for wideband wireless applications,” IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 2943–2963, Dec. 2012. [16] A. C. W. Wong et al., “A 1 V 5 mA multimode IEEE 802.15.6/Bluetooth low-energy WBAN transceiver for biotelemetry applications,” IEEE J. Solid-State Circuits, vol. 48, no. 1, pp. 186–198, Jan. 2013. [17] “Specification of the Bluetooth system v4.0,” Bluetooth SIG, Kirkland, WA, USA, 2010 [Online]. Available: www.Bluetooth.org [18] B. Razavi, RF Microelectronics, 2nd ed. New York, NY, USA: Prentice-Hall, 2011. [19] M. T. Terrovitis and R. G. Meyer, “Noise in current-commutating CMOS mixers,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 772–783, Jun. 1999. [20] C. Hull, “Analysis and optimization of monolithic RF downconversion receivers,” Ph.D. dissertation, Dept. Elect. Eng. Comput. Sci., Univ. California at Berkeley, Berkeley, CA, USA, 1992. [21] J. R. Long, “Monolithic transformers for silicon RF IC design,” IEEE J. Solid-State Circuits, vol. 35, no. 9, pp. 1368–1382, Sep. 2000.

RAHMAN AND HARJANI: SUB-1-V 194- W 31-dB FOM 2.3–2.5-GHz MIXER-FIRST RECEIVER FRONTEND

[22] M. Danesh and J. R. Long, “Differentially driven symmetric microstrip inductors,” IEEE Trans. Microw. Theory Techn., vol. 50, no. 1, pp. 332–341, Jan. 2002. [23] F. Bruccoleri, E. A. M. Klumperink, and B. Nauta, “Wide-band CMOS low-noise amplifier exploiting thermal noise canceling,” IEEE J. SolidState Circuits, vol. 39, no. 2, pp. 275–282, Feb. 2004. [24] C. C. Enz, F. Krummenacher, and E. A. Vittoz, “An analytical MOS transistor model valid in all regions of operation and dedicated to lowvoltage and low-current applications,” Analog Integr. Circuits Signal Process., vol. 8, no. 1, pp. 83–114, Jul. 1995. [25] H. Lee and S. Mohammadi, “A 500 W 2.4 GHz CMOS subthreshold mixer for ultra low power applications,” in IEEE Radio Freq. Integr. Circuits Symp., Jun. 2007, pp. 325–328. Mustafijur Rahman (S’09) received the B.Tech degree in electronics and communication engineering from the National Institute of Technology (NIT) Silchar, India, in 2009, the M.S. degree in electrical engineering from the University of Minnesota, Twin Cities, Minneapolis, MN, USA, in 2014, and is currently working toward the Ph.D. degree in electrical engineering at the University of Minnesota, Twin Cities, Minneapolis, MN, USA. From 2009 to 2011, he was a Scientist with Defense Electronics Research Laboratory, Hyderabad, India. In the summers of 2013 and 2015, he was an Intern with Texas Instruments Incorporated, Dallas, TX, USA, where he was involved in the design of receiver front-ends of small-cell basestation integrated circuits (ICs). His doctoral research is focused on low-power radio IC design for wireless body area networks. Mr. Rahman was the recipient of the University of Minnesota Doctoral Dissertation Fellowship 2015, Best in Session Awards at TECHCON 2014 and 2015, and Gold Medal for Best Engineering Graduate 2009 at NIT Silchar.

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Ramesh Harjani (S’87–M’89–SM’00–F’05) received the B.S. degree in electrical engineering from the Birla Institute of Technology and Science, Pilani, India, in 1982, the M.S. degree in electrical engineering from the Indian Institute of Technology, New Delhi, India, in 1984, and the Ph.D. degree in electrical engineering from Carnegie Mellon University, Pittsburgh, PA, USA, in 1989. He is currently the Edgar F. Johnson Professor with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USA. Prior to joining the University of Minnesota, he was with the Mentor Graphics Corporation, San Jose, CA, USA. In 2001, he cofounded Bermai Inc., a startup company that develops CMOS chips for wireless multimedia applications. He has been a Visiting Professor with Lucent Bell Labs, Allentown, PA, USA, and the Army Research Laboratories, Adelphi, MD, USA. His research interests include analog/RF circuits for communications. Dr. Harjani was an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING (1995–1997). He was Guest Editor for the International Journal of High-Speed Electronics and Systems and for Analog Integrated Circuits and Signal Processing in 2004 and a Guest Editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS (2009–2011). He was a Senior Editor for the IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS (2011–2013) and the Technical Program Chair for the IEEE Custom Integrated Circuits Conference (2013–2014). He was the Chair of the IEEE Circuits and Systems Society Technical Committee on Analog Signal Processing (1999–2000) and a Distinguished Lecturer of the IEEE Circuits and Systems Society (2001–2002). He was the recipient of the National Science Foundation Research Initiation Award (1991) and the Best Paper Award of the 1987 IEEE/ACM Design Automation Conference, the 1989 International Conference on Computer-Aided Design, 1998 GOMAC, and the 2007, 2010, and 2012 TECHCONs. His research group was the recipient of the SRC Copper Design Challenge (2000) and the recipient of the SRC SiGe challenge (2003).

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A 0.4–6-GHz 17-dBm B1dB 36-dBm IIP3 Channel-Selecting Low-Noise Amplifier for SAW-Less 3G/4G FDD Diversity Receivers Cheng-kai Luo, Student Member, IEEE, Prasad S. Gudem, Senior Member, IEEE, and James F. Buckwalter, Senior Member, IEEE

Abstract—A channel-selecting low-noise amplifier (CS-LNA) with blocker filtering is presented for a SAW-less diversity path receiver (RX) in frequency-division duplexing cellular systems. A hybrid -path bandpass filter/band-reject filter (BPF/BRF) feedback network is applied to the LNA to create close-in reject bands around the passband to suppress transmit leakage and improve the out-of-band (OOB) input-referred third-order intercept point (IIP3). Control of the frequency and depth of the reject bands is demonstrated with analysis and simulation. A cancellation linearization is applied to improve the in-band (IB) linearity. Adaptive LO swing and silicon-on-insulator (SOI) thick-oxide devices are demonstrated to improve the power-handling capability. The proposed CS-LNA is implemented in 32-nm CMOS SOI and operates from 0.4 to 6 GHz with the maximum rejection larger than 60 dB and power-handling capability up to 17 dBm. The prototype demonstrates an OOB IIP3 of 36 dBm and IB IIP3 of 10 dBm at 1 GHz. To the authors’ knowledge, this is the highest blocker rejection, power-handling capability, linearity, and the widest tuning range for an LNA with tunable filtering. Index Terms—Blocker suppression, CMOS, low-noise amplifier (LNA), -path filter, SAW-less RX.

Fig. 1. TX leakage suppression at the primary and diversity RX in 3G/4G FDD cellular systems with: (a) existing architecture with SAW filters and (b) proposed CS-LNA.

I. INTRODUCTION

G

ROWING demand for multi-band wireless systems has emphasized tunable highly linear filtering without sacrificing cost or form factor. The 3G/4G frequency-division duplex (FDD) cellular systems such as long-term evolution (LTE) are more prone to interference from strong blockers associated primarily with the co-located transmit signal. In an LTE receiver Manuscript received August 11, 2015; revised December 04, 2015; accepted February 05, 2016. This work was supported by the Center for Wireless Communications, University of California at San Diego and by the National Science Foundation under the Enhancing Access to Radio Spectrum (EARS) program. This paper is an expanded version from the IEEE RFIC Symposium, Phoenix, AZ, USA, May 17–19, 2015. C. Luo is with the Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92037 USA (e-mail: [email protected]). P. S. Gudem is with the Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92037 USA, and also with Qualcomm Inc., San Diego, CA 92121 USA (e-mail: [email protected]. com). J. F. Buckwalter is with the Department of Electrical and Computer Engineering, University of California at Santa Barbara, Santa Barbara, CA 93106 USA (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2529598

(RX), transmit leakage introduces a out-of-band (OOB) blocker at different frequency offsets to the primary and diversity RXs, as illustrated in Fig. 1(a). In a conventional transmitter (TX), the TX signal might be as strong as 27 dBm. At the RX port, the duplexer provides around 55 dB of isolation, which reduces the 27-dBm signal to 28 dBm at the input of the primary RX. The diversity antenna might offer only 15 dB of isolation from the TX to the RX [1] and the TX leakage at the diversity RX can be as high as 9 dBm, which imposes a 9-dB higher OOB blocker level compared to time-division duplex (TDD) systems such as GSM. The strong TX leakage in the diversity RXs places stringent linearity and power-handling capability requirements. As shown in Fig. 1(a), off-chip SAW filters reject the TX leakage by more than 40 dB, which significantly relaxes the input-referred third-order intercept point (IIP3) requirement for the low-noise amplifier (LNA) at the cost of frequency tunability. In conventional multi-band systems, a large number of SAW filters are used and single-pole multi-throw switches select the appropriate SAW filter for the desired channel. The cascaded insertion loss of the filter and switch is roughly 3 dB, imposing a significant noise performance degradation [2], [3]. Therefore, filtering solutions that are tunable, blocker tolerant, and highly linear are critical to extending multi-band schemes.

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Fig. 3. Cancellation in: (a)

Fig. 2. XMD between TX leakage and CW blocker in FDD LTE RXs.

In FDD cellular systems, cross-modulation of the TX leakage with signals in the receive band is a dominant source of distortion. Fig. 2 illustrates the conventional cross-modulation distortion (XMD) scenario. The duplex spacing is defined as , where and are the center frequency of the receive band and TX leakage, respectively. Future LTE bands cover from 0.7 to 3.6 GHz, requiring more than an octave tuning range with duplex spacing that varies from around 80–400 MHz at different bands. Note the transmit signal could be either lower or higher than the receive signal frequency. The linearity requirements are determined by in-band distortion created by cross modulation (XM) between the TX leakage and a close-in continuous wave (CW) blocker. The IIP3 requirement resulting from XMD are determined from , where and are the CW blocker and TX leakage power, respectively, while the is the power of the generated in-band distortion [4], [5]. Assuming the required RX sensitivity is 100 dBm and, consequently, the is 100 dBm, is 43 dBm, and is 9 dBm, XM IIP3 should be 35 dBm, an extremely difficult specification for a CMOS LNA. To avoid desensitization, the LNA should provide more than 40-dB tunable rejection on 9-dBm TX leakage. In this paper, a tunable CS-LNA is proposed with offset band-reject filtering to address TX leakage, as shown in Fig. 1(b). In Sections II and III, we discuss prior work on linearization of CMOS LNAs and filtering techniques, in particular inductorless CMOS-based -path filters [4], [6]–[10]. Based on the 9-dBm TX leakage, we demonstrate that transconductance cancellation and -path filters alone are incapable of suppressing the TX leakage. Furthermore, prior work has not demonstrated the blocker handling as strong as 9 dBm and the linearity to satisfy FDD diversity cellular RXs. In Section IV, CS-LNA with hybrid -path -network feedback is presented and features three key innovations to support 3G/4G FDD SAW-less cellular system requirements, which are not found in recent work, and which only meet requirements of 2G TDD systems [11]–[13]. These three features are the introduction of hybrid -path bandpass filter/band-reject filter (BPF/BRF) feedback to provide close-in reject bands for TX leakage interference suppression and XM IIP3 and OOB IIP3 improvement;

and (b)

.

the use of the dynamic clock swing and silicon-on-insulator (SOI) thick-oxide device for high power-handling capability, and cancellation linearization for high IB IIP3. In addition, an RLC model for the proposed CS-LNA with hybrid -path BPF/BRF feedback is also discussed in Section IV. Section V presents measurements for the 32-nm CMOS SOI prototype. This paper expands on earlier results to present a comprehensive circuit analysis of the generalized hybrid -path BPF/BRF feedback and presents extended measurement results that demonstrate the linearity, power handling, and blocker noise figure (BNF) [14]. II. CMOS WIDEBAND LINEARIZATION Wideband linearization is possible with cancellation of the nonlinear components of the transconductance, . If the transconductance is expanded as a third-order nonlinear polynomial, i.e., , the transconductance is linearized when the and components are minimized. For a CMOS push–pull amplifier, the overall and can be simultaneously minimized due to the opposite polarity of the and phase in main path and auxilary paths, as shown in Fig. 3. Conventional LNA linearization using cancellation works well within a limited input range. When the input signal swing exceeds the limited region of cancellation, the cancellation becomes ineffective. To improve large-signal linearity, the cancellation region should be extended. Multiple auxiliary paths can be used to widen the -cancellation region and the input voltage range is extended [15]. With multi-stage complementary cancellation, more than 10-dB IIP3 improvement could be achieved with around 9-dB improvement on 1-dB gain compression point while the process, voltage, and temperature (PVT) variation could be relieved by proper bias design [15]. However, the linearity and power-handling capability improvement from cancellation is still inadequate with the presence of a 9-dBm TX leakage due to the large voltage swing ( 0.9 V ), which is introduced by the blocker. Consequently, filtering the TX blocker before the LNA is required. III.

-PATH FILTERING

Interference filtering enhances the linearity and power-handling capability of the LNA. -path filters can be used to provide wide tuning range and high linearity [6]–[10]. Fig. 4 illustrates the -path BRF and BPF. In a BPF, the filter response is achieved by translating the baseband low-pass characteristic

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Fig. 4.

-path BPF and BRF and RLC models.

Fig. 5. LNA with

to an RF band through a shunt mixing element. The center frequency of the filtering is determined by the LO frequency. Both the BPF and BRF are, respectively, modeled as parallel and series RLC tank circuits [7], [16]. A. RLC Modeling The equivalent RLC circuit for the BRF and BPF is illustrated in Fig. 4. The RLC circuits are approximated around the switching frequency of with a series resistance , capacitance , and inductance in the case of the BRF [16], (1a) (1b) (1c) where is number of paths, is the switch resistance, is the source impedance, is the load impedance, and is the series capacitance. Note is 2 for a single-ended circuit and is 8 for a differential circuit. In the case of the BPF, the RLC model is a shunt parallel tank with series resistance , capacitance , and inductance [7], (2a) (2b) (2c) Here

is the shunt capacitor.

3

-path BRF feedback.

tion and is approximately 20 dB when and is 50 and 5 , respectively. To reach an OOB rejection of 30 dB with , the switch resistance must be less that . This requires large switch transistors, which substantially limit the tuning range. Moreover, more than 40-dB rejection on 9-dBm TX leakage is demanded. To increase the rejection, the -path BRF could be tuned to the TX leakage. In an -path BRF, the filter response is realized through the series mixing element where the reject band is controlled through the LO frequency. While the -path BRF can be tuned to TX leakage to provide typically 30-dB rejection, compared to -path BPF, -path BRF provides larger maximum rejection, but worse linearity, power-handling capability, and larger passband insertion loss [4]. Generally, filter characteristics such as the bandwidth, rejection, insertion loss, and roll-off are determined by the baseband load impedance. Therefore, -path filters offer tunability and -enhancement that is superior to other integrated tunable filtering techniques. By using the transistors as switches, the -path filter provides high linearity (IIP3 greater than 20 dBm) and blocker 1-dB compression point performance (B1dB greater than 0 dBm). However, further improvement in both linearity to 35 dBm and power-handling capability to 9 dBm are still demanded to handle 9-dBm blockers. Rather than applying the -path filter alone, the -path filter can be applied as feedback around an LNA to achieve better rejection. The LNA with a conventional -path BRF filter as a feedback loop shown in Fig. 5 increases the maximum rejection to 35 dB or less [11]–[13]. At the center frequency of the LO, the input impedance is (4)

B. OOB Rejection The maximum OOB rejection, sometimes referred to as the ultimate rejection (UR) of the BPF, is (3) is the source resistance. Large switches are desirable where in the -path filter to keep the switch resistance below 5 . The smaller on-resistance improves the maximum OOB rejec-

is a resistive feedback for matching. At the where offset frequency from the LO, the -path BRF filter shorts the input and output of the LNA by switches, resulting in low overall gain. Therefore, the rejection is improved. Compared with the conventional -path BPF, which only provides 20-dB maximum rejection, 10–15-dB additional rejection is achieved by the LNA with -path BRF feedback loop [12]. Still, more than 40-dB rejection for TX leakage filtering is demanded. In-

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Fig. 6. Simplified block diagram of the proposed CS-LNA.

creasing rejection leads to a tradeoff between , , and power consumption. Also, cascaded gain stages or/and cell in the feedback loop might be used to increase loop gain, both of which limits power-handling capability.

IV. PROPOSED HYBRID

Fig. 7. Cancellation in output current in: (a) cell with resistive feedback cell with frequency-selective feedback. (c) Hybrid -path BPF/BRF (b) feedback and cancellation-introduced reject bands in the proposed CS-LNA.

bands, as illustrated in Fig. 7(c). For a cell in the feedforward path with a resistive feedback illustrated in Fig. 7(a), the voltage gain is

(5)

-PATH BPF/BRF FEEDBACK LNA

The block diagram of the proposed hybrid -path BPF/BRF feedback LNA is shown in Fig. 6. A wideband LNA is tuned with a four-path filter driven by 25% duty cycle clocks. Earlier work demonstrated the -path BRF feedback concept [11]–[13]. The proposed LNA has three distinct features from the previous work. First, the combination of both series and shunt capacitors in the hybrid -path (BPF/BRF) network provides reconfigurable filtering with offset reject bands for TX leakage suppression and high OOB and XM IIP3. This feature provides two additional reject bands around the passband for TX leakage suppression. Second, adaptive clock swing and an SOI thick-oxide device is applied to achieve high B1dB to handle with 9-dBm TX leakage. Third, the cancellation is applied to the active devices in the LNA for IB IIP3 improvement. Here, the gain is defined as the amplification at the passband and attenuation as the suppression at the reject band where the rejection is defined as the distance between gain and attenuation.

A. Offset Reject Bands, OOB, and XM IIP3 While the conventional BPF provides around 20-dB UR, previous work about the LNA with an -path BRF feedback offers rejection of 35 dB or less. However, more than 40-dB rejection of the TX leakage is demanded, especially in LTE, where the TX leakage power is 9 dBm, 9 dB higher compared to GSM. Further rejection is achieved at a frequency offset through the inclusion of shunt capacitors in an -path BRF feedback. The introduction of shunt capacitors forms a -network and creates a condition whereby the signal is canceled through the active amplifier and the -path BPF/BRF feedback network at the reject

. This example Clearly, there exists a null when suggests one major problem: if this condition is applied, the zero is not frequency selective and there is no gain at any frequency. Therefore, a feedback loop with frequency response is applied instead, as shown in Fig. 7(b). With a frequency-selective feedback around the cell, voltage gain is (6) Generally, the two criteria for cancellation are (7a) and (7b) This ensures a zero will occur at the reject band frequency, , if the gain through the feedforward amplifier in the passband is 180 . If a conventional -path BRF filter is applied to the feedback and , the feedback transconductance is (8) Therefore, the phase condition can only hold when . However, the magnitude condition is only satisfied by and, again, the LNA has very low gain. To solve this problem, the -path -network feedback network is introduced as shown in Fig. 7(c). Two shunt capacitors, and , are introduced to form an -path -network, as shown in Fig. 7(c) and, equivalently, introduce two shunt RLC tanks on either side of the series RLC circuit.

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scale with . For the OOB blockers located at frequency offset to the passband frequency, , impedance of either inductors or capacitors is much smaller than the resistors in RLC tank circuits. Using these approximations, we express the feedback transconductance of the network,

(10) The voltage gain is now Fig. 8. Simplified half branch RLC model for the proposed differential CS-LNA.

Fig. 8 shows the simplified half-branch RLC model for the proposed differential CS-LNA. With the RLC model, the feedback transconductance of the -network is

(11a) We assume and for simplification. The attenuation is found in (12), shown at the bottom of this page, where (13a) (13b)

(9a) where

(9b) , , In the series RLC tank circuit, and , where , , and are found in (1a)–(1c), respectively. The factor of two accounts for the half-circuit representation of the differential circuit shown in Fig. 8. Furthermore, and we will assume that the two-shunt RLC tank circuits are identical in this case. In the shunt RLC circuits, , , and , where each shunt bandpass component is found from (2a)–(2c). We consider the shunt capacitors to be a factor of times the series capacitor, and . Note, however, that the relative values of the resistors and do not obviously

The reject band frequency, , is located where the phase condition in (7b) holds. For increasing , i.e., increasing , the reject band frequency offset decreases. When , which means no shunt capacitor is added, (10) degenerates into as the transconductance of -path BRF filter feedback with and . Fig. 9 presents a comparison of previous work, which incorporate only the BRF feedback, and the proposed CS-LNA with the BPF/BRF feedback. In the proposed work, the reject bands provide more than 15 dB of additional attenuation for TX leakage suppression compared to the LNA with an -path BRF feedback network. Note that the shunt capacitor is 25% of the series capacitor and the simulation shows that the reject band is around 260 and 290 MHz away from the passband. The difference between the depth of lower and higher reject band in simulation is controlled by . Fig. 10 is the simulated transfer function of the proposed CS-LNA for different . The reject bands shift with the value of where larger produces closer reject bands. Also, by tuning dc bias of the LO, , , as well as the cancellation condition is changed to favor lower or higher side reject band. The simulation result indicates that the attenuation of the reject band could be improved to more than 40 dB with certain , which could be controlled by . Note that the location of the reject band changes as well when changes.

(12)

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Fig. 9. Comparison of previous work and the proposed work: LNA with hybrid -path BPF/BRF feedback.

Fig. 11. Normalized frequency offset between the reject band and passband as a function of , the shunt capacitance size.

Fig. 12. Attenuation in the reject band as a function of the shunt capacitance size. Fig. 10. Simulated S-parameters with different

and

.

Also, when increases, the gain drops by less than 0.2 dB because the charge leakage between baseband capacitors in the -path filter and can be further released by reducing the overlap between LOs. Compared with conventional tunable filters, which are suffered from insertion loss, rejection level, and pole number tradeoff, the proposed LNA relaxes the tradeoff with cancellation in the hybrid -path BPF/BRF feedback. Fig. 11 shows the normalized frequency offset between reject band and passband, , as a function of in the RLC model with simulated results. For with , , , mS pF, , and GHz, simulations show two reject bands are located around 260 and 290 MHz away, respectively, while the RLC model indicates around 230and 300-MHz offset. As decreases, the frequency offset increases. The attenuation is shown in Fig. 12 as a function of in the RLC model and compared to simulated results. As changes, the attenuation changes accordingly depends on the current matching between feedback path and output of the cell and can be further adjusted by tuning , as shown in Fig. 10.

B. B1dB: Adaptive LO Swing and SOI Thick-Oxide Device A 9-dBm blocker introduces undesirable switch operation that increases the distortion. The large voltage swing due to blockers at the drain of the switch transistors forces the switches on or off independent of the LO clock at the gate. Distortion results from the resulting charge leakage from the baseband capacitor and unwanted signal distortion from the switch. To maintain a high-linearity -path filter, the LO clock swing must be appropriate to the maximum blocker level. The clock signal, , is increased over the signal swing by at least one threshold voltage, i.e., and . Fig. 13 shows the simulated B1dB result with a blocker located at 50-MHz offset. With 2-V supply voltage for buffers, the clock swing is 1.5 V to 0.5 V relative to dc bias of the input signal line, the signal compression is still less than 1 dB when the blocker power reaches 12 dBm indicating the proposed filter is robust to the OOB blocker. However, the B1dB is less than 5 dBm when the clock swing is from 1.5 to 0 V relative to dc bias of the signal lines. To handle large voltage swings, all the buffers in the LO generator and switches used in the -path filter are thick-oxide devices rather than regular thin-oxide (high ) devices. In the absence of a significant TX leakage, reduced LO swing

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Fig. 13. Simulated B1dB with different swing conditions.

7

Fig. 15. Monte Carlo simulation of LO leakage with PVT variations in 100 runs.

76 dBm, respectively. Furthermore, LO leakage suppression can be done by roughly 7 dB by using transistors with the same width-to-length ratio for similar , but smaller parasitic capacitors [4]. D. Circuit Implementation

Fig. 14. Monte Carlo simulation of rejection with PVT variations in 100 runs.

is used with lower buffer supply voltage for a power savings. The large voltage swing due to blockers at the drain of the switch transistors also cause leakage and distortion by changing the voltage-dependent drain junction capacitor dramatically. Compared with bulk device, the SOI device minimizes the voltage-dependent drain-bulk capacitance and provides better switch control in the presence of a large signal. C. PVT Variation on Rejection and LO Leakage Fig. 14 shows the Monte Carlo simulation of PVT variations on rejection in 100 runs. The rejection is 47 dB before PVT variation is applied. Across PVT corners, the mean and minimum simulated rejection in 100 runs are 45 and 28 dB, respectively, while 99% of simulated rejection results are greater than 35 dB. The degradation in the rejection is mainly caused by the increased in the -path filter. Using switches with larger width/length ratio for lower mitigates this mismatch. In addition, applying higher on the switches would lower with the help of digital calibration. Fig. 15 is the simulated PVT variation for the LO leakage. The mean and the worst simulated LO leakage is 84 and

The detailed schematic for the proposed circuit is illustrated in Fig. 16 and uses a fully differential scheme to reduce LO leakage and the impact of even harmonic distortion. First, a divide-by-2 frequency divider is driven by an external clock. The tuning range of the filter is primarily limited by frequency dividers. To further improve the tuning range, current mode latches are used in the frequency divider and the input frequency range of the frequency divider is up to 12 GHz. The frequency dividers are followed with NAND gates to convert the four 50% duty cycle phases into 25% duty cycle clocks. The clock is buffered and ac coupled to -path switches. Separate voltage supplies for clock buffers allow higher voltage swing for larger B1dB. Large switch size, m nm, reaches around 6 on-resistance. Increasing the switch size reduces the switch resistance, which improves the OOB rejection and increases the linearity at the expense of higher power consumption for the clock generator and reduced tuning range. Metal-stacked (fringe) capacitors are used rather than MOS capacitors to avoid capacitance change under large blocker conditions and also improve the IIP3. In the hybrid -path BPF/BRF feedback, the series capacitors, pF, and the shunt capacitors, and pF is chosen. A thick-oxide SOI device are used in switches of hybrid -path BPF/BRF feedback, all the buffers in the LO generator and cancellation LNA to handle large voltage swings. Also, because of the longer channel length compared regular thin-oxide (high ) device, applying thick-oxide device provides better linearity at the expanse of power consumption. An SOI device provides better linearity even with the presence of large voltage swing by reducing the parasitic voltage-dependent drain/source junction capacitor, which is one of the main distortion sources in MOSFETs.

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Fig. 16. Detailed schematic of the proposed filter.

Fig. 17. Chip photograph of the proposed CS-LNA.

TABLE I POWER CONSUMPTION 0.4 AND 6 GHz

Fig. 18. Measured S-parameters for passband is tuned to 1 GHz.

A. S-Parameters

V. MEASUREMENT RESULT The chip microphotograph is shown in Fig. 17. The total chip area is 0.88 mm while the active area is 0.21 mm . The power consumption is summarized in Table I at different center frequencies. With 2-V LO swing, the power consumption increases from 81 to 209 mW when the passband is tuned from 0.4 to 6 GHz. When the TX leakage power is negligible, the LO swing could be reduced for power saving. In addition, as shown in the table, the cancellation LNA consumes 60 mW for 10-dBm IB IIP3. While the IB IIP3 requirement is 10 dBm for SAW-less 3G/4G FDD cellular RXs rather than 10 dBm, the power consumption could be further reduced by decreasing bias current with acceptable IB IIP3 performance.

and are plotted in Fig. 18 when the The measured passband is tuned to 1 GHz and Fig. 19 shows the measured close-in and . The passband gain is around 11 dB and the 3-dB bandwidth is around 15 MHz with 9-MHz bandwidth when the input return loss is better than 10 dB. The reject bands are located on either side of the passband and demonstrate an UR larger than 40 dB. The measured factor is more than 7.3 at 1 GHz indicating that the circuit is unconditionally stable. The measured and at different LO frequencies is shown in Fig. 20 and indicates a tuning range from 0.4 to 6 GHz. When the center frequency increases, the passband gain decreases from 11.5 to 5.4 dB and the reject-band rejection is reduced. As the switching frequency increases, the rise and fall times of the LO clocks are a significant fraction of the overall pulse width and cause the duty cycle distortion. As a result, the higher effective jeopardizes cancellation and reject-band rejection decreases. Fig. 21 demonstrates selection of the lower or higher side reject band with different dc bias conditions for the LO. By tuning,

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Fig. 19. Measured close-in S-parameters for passband is tuned to 1 GHz.

Fig. 20. Measured

and

over a tuning range from 0.4 to 6 GHz.

9

Fig. 22. Measured OOB IIP3 and IB IIP3 at 1 GHz.

Fig. 23. Measured OOB IIP3, XM IIP3, and IB IIP3 over a tuning range from 0.4 to 6 GHz.

B. IB IIP3, OOB IIP3, and XM IIP3

Fig. 21. Measured 1 GHz.

with different

when the passband is tuned to

, , as well as the cancellation condition is changed to favor lower or higher side reject band.

Both IB IIP3 and OOB IIP3 is measured with two tones. For IB IIP3, both of the two tones are located in the passband to evaluate the impact from the IB signal or/and blockers. For OOB IIP3, the two tones are located out of band such that the thirdorder intermodulation (IM3) falls in band to evaluate the impact from OOB blockers on desired signals. On the other hand, XM IIP3, sometimes is called triple-beat (TB) IIP3, is measured with three tones to evaluate the impact from the XM between two OOB blockers and a close-in CW blocker. This measurement is most relevant to FDD systems. Fig. 22 plots IIP3 for two different scenarios at 1 GHz. In the first scenario, the OOB IIP3 is measured with two tones located at 900 and 949 MHz, respectively. In the second scenario, the IB IIP3 is measured for two tones located at 994 and 996 MHz. The IM3 tone of both scenarios is located at 998 MHz. The measurement demonstrates an OOB IIP3 of 36 dBm and an IB IIP3 of 10 dBm. Fig. 23 shows measured IB, OOB, and XM IIP3 at different center frequency from 0.4 to 6 GHz while Table II shows tones and results for IIP3 measurement.

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TABLE II TONES AND RESULTS OF IIP3 MEASUREMENT

Fig. 26. Measured NF over tuning range.

Fig. 24. Measured B1dB with different blocker frequency offset.

Fig. 27. Measured and simulated BNF with a blocker located at 200-MHz offset from center frequency.

Fig. 25. Measured blocker rejection compression.

Note that the power of three tones applied for XM IIP3 measurement is fixed and the XM IIP3 is evaluated with . The measured results indicate the IB IIP3 is relatively constant over the tuning range while the OOB IIP3 and XM IIP3 decrease when center frequency increases. For IB tones, the feedback loop is open and the linearity performance is determined by the cancellation LNA. The IB IIP3 performance is consequently almost the same over the tuning range. For OOB tones, the feedback loop provides a low impedance path to ground and cancellation determined by . As the effective increases, the maximum rejection, as well as OOB IIP3 and XM IIP3, decreases.

Fig. 28. Simulated BNF with 9-dBm blocker as a function of phase noise at 200-MHz offset from center frequency.

C. B1dB and Blocker Rejection Compression Fig. 24 shows the measured B1dB with a blocker frequency offset by 50, 100, and 200 MHz, respectively, at a center frequency is 1 GHz. The large TX leakage induces unwanted

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11

TABLE III PERFORMANCE SUMMARY AND COMPARISON

switch conduction and causes gain compression. With an appropriate clock swing, the switch is turned on and off based on the LO clock and the unwanted conduction is suppressed. From Fig. 24, the measured B1dB is higher than 11 dBm with a blocker offset by 50 MHz. When a blocker offset increases, the measured B1dB increases and the ultimate B1dB is higher than 17 dBm. Fig. 25 shows the rejection of the reject band as a function of the blocker power while the blocker is located at the center of the reject band. The measured result indicates the blocker rejection compression is 3 dB when the blocker power increases to 9 dBm. D. Noise Figure The noise figure (NF) at different LO frequencies is shown in Fig. 26. Signal-to-noise (SNR) requirements for LTE are set by 3GPP standards. For example, the SNR requirement, , for LTE with a 10-MHz channel is 1 dB at a sensitivity, , of 97 dBm (or a power spectral density of 167 dBm/Hz). Therefore, the RX NF requirements referred to the antenna is 8 dB. Over the tuning range, the measured NF increases from 3.6 to 4.9 dB. This is competitive compared to the equivalent losses of 3 dB for SAW filters and off-chip switches and the typical NF of LNA is around 2 dB. The blocker noise figure (BNF) is measured in the presence of a transmit signal located at 200-MHz offset and plotted in Fig. 27. When measuring BNF, a highly selective external filter is placed at the output of the signal generator to reduce the receive band noise. With a 9-dBm blocker, the NF increases to 17.4 dB. This matches the simulated BNF with an LO phase noise of 154 dBc/Hz at a 200-MHz offset. BNF could be further reduced by applying appropriate LO generator design with lower phase noise. Fig. 28 shows the simulated BNF with a 9-dBm blocker as a function of phase noise at a 200-MHz offset. At 167 dBc/Hz, the BNF with 9-dBm TX leakage does not exceed 7 dB. That is a challenging phase noise specification, but within reach of state-of-the-art references and CMOS frequency synthesizers. Finally, the LO leakage is measured at input and is less than 52 dBm. The main factors of higher measured LO leakage are coupling caused primarily by layout-related issues such as overlap between input/output lines and the clock lines and/or substrate [4], [7], [16]. A summary of the filter performance and comparison is shown in Table III. In [17], a large attenuator was applied before the -path BPFs and improves the linearity at the expense of noise performance. Cascading -path BPFs, such as [18], provides reasonable OOB IIP3, but reduces IB IIP3 and bandwidth.

Also, the tuning range in all prior work is not wide enough to cover all LTE bands. This work provides highest B1dB and is sufficient to address 9-dBm TX leakage. Compared with previously published integrated tunable filtering techniques, this work is the most promising for addressing the TX leakage with 9-dBm maximum power in multi-band systems to support 3G/4G SAW-less FDD cellular systems, such as advanced LTE, by providing the highest power-handling capability, linearity (both IB and OOB IIP3), rejection, and the widest tuning range. To the authors’ knowledge, this is the highest blocker-rejection power-handling capability, linearity, and the widest tuning range for an LNA with tunable filtering. VI. CONCLUSION A blocker-filtering CS-LNA for FDD cellular systems has been presented that can handle 9-dBm TX blockers. A 32-nm CMOS SOI prototype has demonstrated linearization to improve IB IIP3 and adaptive LO swing and SOI thick-oxide devices improve the power-handling capability. Additionally, the use of a hybrid -path BPF/BRF feedback network suppresses TX leakage and improves OOB and XM IIP3 through the addition of a double-sided reject band around the passband that can be selected for desired TX leakage rejection. The UR is larger than 60 dB at the reject band and the reject-band rejection decreases around 3 dB with a 9-dBm blocker located at the center of the reject band. The measured results demonstrate 36-dBm OOB IIP3 and 10-dBm IB IIP3, as well as more than 17-dBm B1dB with a tuning range from 0.4 to 6 GHz. ACKNOWLEDGMENT Fabrication has been provided through the Trusted Access Program Office (TAPO). REFERENCES [1] R. E. M. Haim, M. Weissman, and C. Holenstein, “Antenna interface circuits for carrier aggregation on multiple antennas,” Patent WO 2014 005 061 A1, Jan. 3, 2014. [2] S. Razafimandimby, C. Tilhac, A. Cathelin, A. Kaiser, and D. Belot, “An electronically tunable bandpass baw-filter for a zero-IF WCDMA receiver,” in Proc. 32nd Eur. Solid-State Circuits Conf., 2006, pp. 142–145. [3] D. Ruffieux et al., “A narrowband multi-channel 2.4 GHz MEMSbased transceiver,” IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 228–239, Jan. 2009. [4] C.-K. Luo, P. S. Gudem, and J. F. Buckwalter, “A 0.2–3.6-GHz 10-dBm B1dB 29-dBm IIP3 tunable filter for transmit leakage suppression in SAW-less 3G/4G FDD receivers,” IEEE Trans. Microw. Theory Techn., vol. 63, no. 10, pp. 3514–3524, Oct. 2015.

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[5] V. Aparin and L. Larson, “Analysis and reduction of cross-modulation distortion in CDMA receivers,” IEEE Trans. Microw. Theory Techn., vol. 51, no. 5, pp. 1591–1602, May 2003. [6] A. Mirzaei and H. Darabi, “Analysis of imperfections on performance of 4-phase passive-mixer-based high-Q bandpass filters in SAW-less receivers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 5, pp. 879–892, May 2011. [7] A. Ghaffari, E. Klumperink, M. Soer, and B. Nauta, “Tunable high-Q -path band-pass filters: Modeling and verification,” IEEE J. SolidState Circuits, vol. 46, no. 5, pp. 998–1010, May 2011. [8] M. Darvishi, R. van der Zee, and B. Nauta, “Design of active -path filters,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 2962–2976, Dec. 2013. [9] L. Chen, C. Wang, C. Li, L. Ye, H. Liao, and R. Huang, “A 21.2 dBm out-of-band IIP3 0.2–3 GHz RF front-end using impedance translation technique,” in IEEE Circuits Syst. Int. Symp., 2012, pp. 468–471. [10] A. Ghaffari, E. Klumperink, and B. Nauta, “8-path tunable RF notch filters for blocker suppression,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., 2012, pp. 76–78. [11] Z. Lin, P.-I. Mak, and R. Martins, “Analysis and modeling of a gainboosted -path switched-capacitor bandpass filter,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 9, pp. 2560–2568, Sep. 2014. [12] J. W. Park and B. Razavi, “Channel selection at RF using miller bandpass filters,” IEEE J. Solid-State Circuits, vol. 49, no. 12, pp. 3063–3078, Dec. 2014. [13] J. Zhu, H. Krishnaswamy, and P. R. Kinget, “Field-programmable LNAs with interferer-reflecting loop for input linearity enhancement,” IEEE J. Solid-State Circuits, vol. 50, no. 2, pp. 556–572, Feb. 2015. [14] C.-K. Luo, P. S. Gudem, and J. F. Buckwalter, “0.4-6 GHz, 17-dBm B1dB, 36-dBm IIP3 channel-selecting, low-noise amplifier for SAWless 3G/4G FDD receivers,” in Proc. IEEE RFIC Symp., May 2015, pp. 299–302. [15] B.-K. Kim, D. Im, J. Choi, and K. Lee, “A 1 GHz 1.3 dB NF 13 dBm output p1dB SOI CMOS low noise amplifier for SAW-less receivers,” in Proc. IEEE RFIC Symp., Jun. 2012, pp. 9–12. [16] A. Ghaffari, E. Klumperink, and B. Nauta, “Tunable -path notch filters for blocker suppression: Modeling and verification,” IEEE J. SolidState Circuits, vol. 48, no. 6, pp. 1370–1382, Jun. 2013. [17] M. Darvishi, R. van der Zee, E. Klumperink, and B. Nauta, “A 0.3bandpass filter with to-1.2 GHz tunable 4 -order switched 55 dB ultimate rejection and out-of-band IIP3 of 29 dBm,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., 2012, pp. 358–360. [18] M. Darvishi, R. van der Zee, and B. Nauta, “A 0.1-to-1.2 GHz tunable 6th-order -path channel-select filter with 0.6 dB passband ripple and 7 dBm blocker tolerance,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., 2013, pp. 172–173. Cheng-kai Luo (S’11) received the B.S. degree in electrical engineering from the National Central University, Taoyuan, Taiwan, in 2006, the M.S. degree in electrical engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2008, and is currently working toward the Ph.D. degree in electrical engineering at the University of California at San Diego (UCSD), La Jolla, CA, USA. He is currently an Intern with Qualcomm Inc., San Diego, CA, USA, where he designs RF front-ends for cellular applications. His research interests include

analog/RF integrated circuit (IC) design and silicon-on-insulator (SOI)/multigate devices.

Prasad S. Gudem (M’96) received the B.Tech. degree in electrical engineering from the Indian Institute of Technology, Madras, India, in 1988, and the Ph.D. degree in electrical engineering from the University of Waterloo, Waterloo, ON, Canada, in 1966. He is currently a Vice President of Engineering with the Analog/RF Integrated Circuit (IC) Design Group with Qualcomm Technologies Inc., San Diego, CA, USA, and an Adjunct Associate Professor with the Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA, USA. Since joining Qualcomm Inc., in 2002, he led the development of several generations of transceivers including the first integrated diversity receiver chip, the first integrated SAW-less receiver for CDMA2000, and the first 28-nm integrated carrier aggregation multi-mode mulit-band transceiver. Since 2000, he has taught several graduate-level classes and co-advised eight Ph.D. students in the area of RF integrated circuit (IC) design. Dr. Gudem was the recipient of the Graduate Teaching Award for the 2001–2002 academic year in recognition of his outstanding teaching of the ECE265 course sequence “Communication Circuit Design: I, II, and III.”

James F. Buckwalter (S’01–M’06–SM’13) received the Ph.D. degree in electrical engineering from the California Institute of Technology, Pasadena, CA, USA, in 2006. He is currently an Associate Professor of electrical and computer engineering with the University of California at San Diego (UCSD), La Jolla, CA, USA. From 1999 to 2000, he was a Research Scientist with Telcordia Technologies. During Summer 2004, he was with the IBM T. J. Watson Research Center, Yorktown Heights, NY, USA. In 2006, he joined Luxtera, Carlsbad, CA, USA. In July 2006, he joined the faculty of the UCSD, as an Assistant Professor. Dr. Buckwalter was the recipient of a 2004 IBM Ph.D. Fellowship, the 2007 Defense Advanced Research Projects Agency (DARPA) Young Faculty Award, and the 2011 National Science Foundation (NSF) CAREER Award.

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1

Analysis and Design of an E-Band Transformer-Coupled Low-Noise Quadrature VCO in 28-nm CMOS Marco Vigilante, Student Member, IEEE, and Patrick Reynaert, Senior Member, IEEE

Abstract—This paper presents an E-band quadrature voltagecontrolled oscillator implemented in 28-nm CMOS. Two fundamental oscillators are coupled by means of gate-to-drain transformers to realize accurate quadrature phases and switched coupled inductors are added for tuning extension. Closed-form expressions of the oscillation frequency and the tuning extension design parameters are derived. The time-variant nature of the circuit noise to phase noise (PN) of the presented topology is investigated, resulting in simple design guidelines for optimal design. Based on the proposed techniques, the realized prototype is tunable over two bands of almost 5 GHz each separated in frequency, while occupying only 0.031 mm . The peak measured PN at 10-MHz offset is 117.7 dBc/Hz from a 72.7-GHz carrier and 110 dBc/Hz from a 88.2-GHz carrier and varies less than 3.5 dB within each band. Index Terms—CMOS, E-band, impulse sensitivity function (ISF), millimeter-wave (mm-wave), phase noise (PN), quadrature voltage-controlled oscillator (QVCO), transformer, wide tuning range (TR).

I. INTRODUCTION

T

HE ever-increasing demand for higher data-rate and new applications poses unprecedented challenges for wireless systems. CMOS is the technology of choice for mass-production digital and is therefore playing a key role in this revolution. Recently, the U.S. Federal Communications Commission (FCC) and the European Conference of Postal and Telecommunications Administrations (CEPT) allocated two bands of 5 GHz each from 71 to 76 GHz and from 81 to 86 GHz (referred to as E-band) to enable a high-speed point-to-point wireless link for fiber replacement/extension over short-to-medium distances [1]. CMOS direct-conversion transceivers stand out for excellent linearity, power, and area efficiency also at millimeter wave (mm-wave) [2]–[4]. However, this architecture poses serious requirements on the local oscillator (LO), demanding a phase noise (PN) of at least 110 dBc/Hz at 10-MHz offset [2] while providing in-phase/quadrature (I/Q) outputs directly at the carrier frequency to enable a 16-QAM modulation. Automotive car Manuscript received July 24, 2015; revised December 01, 2015; accepted February 04, 2016. This work was supported by Analog Devices Inc., Limerick, Ireland. This paper is an expanded version from the IEEE RFIC Symposium, Phoenix, AZ, USA, May 17–19, 2015. The authors are with MICAS, Department of Electrical Engineering (ESAT), KU Leuven, B-3001 Leuven, Belgium (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2530703

radar in the frequency band that spans from 77 to 81 GHz is another application that rises a lot of interest and would benefit from integrated low-noise quadrature LO solutions [5]. The quadrature LO is therefore one of the main bottlenecks that limit the full integration of such radios. To tackle this problem, several solutions have been proposed in the literature, but not all of them are suitable for mm-wave applications, especially when a large tuning range (TR) is required. In [6], a voltage-controlled oscillator (VCO) running at the carrier frequency ( ) followed by a buffer and a poly-phase filter (PPF) is proposed. The down side of this solution stands in the high insertion loss of the PPF, demanding a power-hungry buffer to drive it. In [7], an injection-locked frequency tripler (ILFM3) is proposed, requiring a VCO that runs at plus a frequency multiplier by 2, a frequency divider by 2, two mixers, and two injection-locked VCOs. For such a topology, a large number of on-chip inductors are needed, resulting in a large silicon area and exacerbating the unwanted magnetic coupling from and to other circuits. Moreover, while solutions based on frequency multipliers shows wide TR, the work presented by Jani et al. in [8] points out that the improvement in terms of PN and power consumption is not obvious when the multiplication factor is limited to 2, 3, or 5. Another popular approach is based on coupling two identical oscillators running at to realize a fundamental quadrature voltage-controlled oscillator (QVCO). To overcome the well-known tradeoff between PN and phase error of the classical parallel-coupled QVCO [9], a number of alternative techniques have been recently investigated [10]–[14]. Due to the large impact of parasitics at high frequency, a coupling mechanism that does not require extra components is desirable and is therefore adopted in this work. In [15], we have shown that two fundamental VCOs can be coupled by means of gate-to-drain transformers and switched coupled inductors can be added for tuning extension. The prototype implemented in 28-nm CMOS is tunable over two bands of almost 5 GHz each separated in frequency, while showing state-of-the-art PN performance and consuming silicon area of only 0.031 mm . In this work, a solid theoretical background based on the time-variant nature of circuit-noise to phase-noise conversion [16] is presented. Closed-form expressions of the oscillation frequency and tuning extension design parameters are thoughtfully derived and the effect of tank mismatch over the phase error is investigated, yielding simple design guidelines to minimize PN and phase error at the same time. In Section II, the proposed transformer-coupled QVCO is presented. The de-

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Fig. 2. Lumped-element model of the proposed resonator and equivalent circuit based on the two-port admittance parameters matrix. Fig. 1. Schematic of the proposed dual-band QVCO based on gate-to-drain transformers with switched coupled inductors.

sign considerations at mm-wave and the details of the circuit implementation in deep-scaled 28-nm CMOS are discussed in Section III. Section IV presents the measured results, demonstrating that the prototype is tunable within two bands separated in frequency and achieves a peak PN at 10-MHz offset of 117.7 dBc/Hz from a 72.7-GHz carrier and 110 dBc/Hz from a 88.2-GHz carrier and varies less than 3.5 dB within each band. Conclusions follow in Section V. Fig. 3. Single-ended half-circuit negative-resistance ac model of the proposed QVCO.

II. PROPOSED TRANSFORMER-COUPLED QVCO A. Operating Principle Fig. 1 shows the schematic of the proposed quadrature oscillator, where two VCOs based on the topology proposed in [17] are coupled by means of two gate-to-drain transformers. To prevent the circuit to oscillate in common mode, a resistor can be added on the low current path through the center tap of , as depicted in Fig. 1. The LC tank at the source node is designed with a self-resonant frequency lower than the operating frequency of the VCO, it is therefore modeled as an ideal degeneration capacitor in parallel with an RF choke inductor . To gain insight into the principle of operation and simplify the following analysis, it is functional to replace the resonator with its single-ended two-port admittance parameters model, as in Fig. 2, where , , and accounts for the losses. By inspection, the following equations are derived:

, , , and ), it is possible to redraw the circuit in Fig. 1 as in Fig. 3 (see the Appendix for further details). From Kirchhoff’s phasor nodal equations, the following expressions are derived:

(3)

(4)

(1)

. This set of equations is verified if and only if Meaning that in the presence of perfectly matched components the two oscillators are forced to operate in quadrature. Furthermore, a perfect quadrature operation is realized even if .

(2)

B. Oscillation Frequency

In steady state due to the large-signal operation, the nonlinearity of the active device, and the passband behavior of the tank, it is possible to replace the transconductor with its describing function approximation [18]. By means of a Norton transformation and assuming differential operation (i.e.,

To derive a closed-form expression for the oscillation frequency, it is effective to rearrange the circuit as a tank of impedance in parallel with an energy-restoring element . By noting that the oscillator operates in quadrature, the circuit in Fig. 3 can be redrawn as shown in Fig. 4. By inspection, is derived as in (5), shown at the bottom of the following page.

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3

Fig. 5. Simplified lumped-element model of the gate-to-drain transformers with switched coupled inductors. Fig. 4. Rearrangement of the circuit in Fig. 3 under quadrature operation.

Assuming a high quality factor for the resonator ( ) and imposing the condition , the two resonant frequencies of the fourth-order tank are derived as

(6) where

, , , and . Noteworthy, this expression is similar to the one derived in [12] being the two QVCOs realized around similar fourth-order tanks (here, plays a role similar to in [12]). Moreover, in principle it is possible to use the second mode of oscillation to extend further the TR, provided that extra circuitry is added as already proposed for other oscillator topologies [12], [19], [20]. However, given the high target frequency of operation, in this work no effort is made to take advantage of the second resonance peak since adding extra components would lead to higher parasitic loading of the tank. Nevertheless, during the design phase it is important to ensure that the oscillator meets the Barkhausen’s criteria only in one mode. Condition easily achieved in a practical design at mm-wave frequencies when the magnetic coupling is designed large enough so that and the transconductors are not able to compensate for the tank losses in the second mode. C. Tuning Extension In LC oscillators, higher TR comes at the cost of lower spectral purity for a given power consumption. This tradeoff is exacerbated at mm-wave, where the impact of parasitics is larger and the quality factor of the tank is limited by the of capacitors and varactors rather than the one of inductors. For these reasons, several recent research works have been focused on alternative tuning extension techniques [21]–[23].

From (6), it is clear that the oscillation frequency is highly sensitive to the magnetic coupling coefficient and the inductance value . In this work, a third winding terminated on a switch is coupled to the gate-to-drain transformer to effectively change both and , as depicted in Fig. 5. Intuitively, when the switch is turned ON, the current induced in through and finds a low-impedance path. Whereas when is in the OFF state, is terminated on an infinite impedance and ideally no current is flowing. To gain deeper insight into the operation of the proposed transformer with switched coupled inductor and derive design guidelines, it is useful to refer to its three-port impedance parameter model shown in Fig. 6. By inspection, the following expressions are derived: (7) (8) (9) (10) (11) (12) , and ) in where the losses of each inductor ( , Fig. 5 are modeled by a series resistor (of value , , and , respectively). Since the third port is terminated on an impedance , it is possible to derive the equivalent two-port network, as depicted in Fig. 6, provided that (13) (14) where, for sake of space only, the expressions for the impedance and the transimpedance of the first winding are reported.

(5)

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Fig. 7. Simulated PN at 10-MHz offset from an 80-GHz carrier versus and .

Fig. 6. Transformer with switched coupled inductor three-port impedance parameters model (top) and its two-port equivalent circuit (bottom).

It is now possible to derive approximated equations to describe an equivalent two-port transformer. When is in the ON state and assuming , the equivalent series resistance and self-inductance of the primary winding and the equivalent magnetic coupling are (15) (16) (17) is in the When suming sions are derived:

OFF

state

and as, the following expres(18)

(19)

(20)

where is the self-resonance frequency of the third winding when terminated on the OFF capacitance of . From (15)–(20), several design considerations can be made. Fist, the ON resistance of severely limits the transformer losses and should be designed accordingly low enough. In addition, the current induced in the third winding effectively reduces both and through and . Another critical observation deals with the design of when is in the OFF state. To ensure a single solution of (19), should be higher than the oscillation frequency of the VCO, imposing an upper bound for the value of [21],

[23]. Moreover, in a practical design, the condition is not verified. Meaning that , , and increase with frequency and the change is sharper when proaches , demanding for a careful co-design of , , and .

ap,

D. PN The first step towards a design for minimum PN is to quantify the effect of two key design parameters (i.e., the equivalent magnetic coupling and the degeneration capacitance ) on the operation of the proposed quadrature oscillator. Fig. 7 shows the simulated PN at 10-MHz offset from an 80-GHz carrier as a function of and . The experiments were performed adopting ideal lumped-element components for passive devices where fF, is adjusted to keep the oscillation frequency equal to 80 GHz for fair comparison, and the losses are modeled with a shunt resistor assuming a quality factor equal to 4. The transconductors (W/L of 40 m/28 nm) were post-layout parasitic extracted to account for and (about 10 and 20 fF, respectively). is set to 100 to prevent oscillation in common mode. Clearly, the PN shows a weak dependency from , meaning that the proposed tuning extension technique can be effectively applied provided that the quality factor of the resonator is kept constant when is in the ON and OFF state. Moreover, the value of can be optimized for PN. To get deeper insight into the circuit-noise to phase-noise conversion mechanism of the proposed topology, it is useful to adopt the linear time-variant approach proposed by Hajimiri and Lee in [16]. By noting that in steady state the oscillation amplitude is limited by the compressing behavior of the transconductors, the amplitude noise is neglected and the PN at an angular frequency offset from a carrier can be expressed as (21) is the maximum charge displacement across the where tank capacitor and is the effective noise power of the th current noise source, defined as (22) is the impulse sensitivity function (ISF), dimenwhere sionless function of time periodic in , and is

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Fig. 8. Noise to PN conversion mechanism of the proposed oscillator. (a) Voltage waveforms and ) and channel conductance ( ) of . different nodes. (d) Instantaneous transconductance (

the power spectral density of the current noise produced by the th devices. The ratio is accurately estimated at different oscillator nodes by means of the periodic transfer function analysis (PXF), as proposed in [24] and reported in Fig. 8(c). In these experiments, and the optimum value of in Fig. 7 is selected. Most importantly, Fig. 8(c) shows that , meaning that the source node is the less sensitive to noise and the drain node is the most critical one. To optimize the PN performance is therefore important to design the transformer accordingly (i.e., the quality factor of the secondary winding should be maximized). Moreover, the output should be probed at the source to minimize the loading effect of the following stage. Fig. 8(a) shows the voltage waveforms across highlighting its regime of operation. Due to the large voltage amplitude, the transistor operates in all three regions (i.e., saturation, triode, and OFF), meaning that the active device: 1) contributes to losses through the channel conductance (referred in the literature as the loaded or effective -factor [25], [26]) and 2) injects more noise through and the larger

operation region. (b) ISF of

5

channel noise. (c) ISF at

. Although in theory this condition is not desirrequired able, in mm-wave oscillators realizing a high common-mode impedance at over the whole TR is not trivial [27], and the transconductors are allowed to ender (to some extend) the triode region to maximize the voltage amplitude. The noise contribution of the transistor can be expressed as [25] (23) where is the Boltzmann’s constant, is the absolute temperature, and is the transistor channel noise factor. Noteworthy, Fig. 8(b) and (d) show that when the transistor noise contribution is at its maximum, the associated is close to 0 yielding a negligible associated effective noise power during this laps of time. E. Phase Error In presence of mismatches in the circuit, (3) and (4) are not valid anymore and the two oscillators depart from quadrature. This result in amplitude imbalance and phase error. The focus of this section is the phase error since, in a practical system, the

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Fig. 11. 3-D layout view of the designed transistor

40 m/28 nm.

at this node (as clear from Fig. 8(c) and already discussed in Section II-D). III. DESIGN CONSIDERATIONS AT mm-WAVE CIRCUIT IMPLEMENTATION Fig. 9. Test circuit to evaluate the phase error in presence of mismatch.

Fig. 10. Simulated impact of error at different nodes against

mismatch among passives on the phase .

LO signals are normally fed to hard limiting buffers and an I/Q mixer that is almost insensitive to small amplitude imbalance (provided that the signal amplitude is large) [9], [11]. Deriving elegant closed-form expressions for the phase error at different tank nodes under the presence of mismatches for this QVCO topology is not trivial. Moreover, the simplified linear model in Fig. 3 when extended to describe mismatch due to the tank would not account for circuit nonlinearity that may play a significant role (as is the case for a QVCO that employs a passive nonlinear coupler [11]). To address this problem, it is functional to refer to the schematic depicted in Fig. 9. To gain a deeper understanding, a mismatch of is imposed among passives and the phase error is evaluated at different nodes. Fig. 10 shows that when the equivalent magnetic coupling is , the phase error at the source node is always , and most importantly, when , the condition is achieved. From the analysis above, we can draw two very important and perhaps unexpected conclusions: 1) probing the signal at the source leads to the same choice of optimal design parameters for both minimum PN (as in Fig. 7) and minimum phase error (Fig. 10) and 2) the loading effect of the buffer is minimal

AND

Thanks to the aggressive scaling of the gate length, today mm-wave circuits can enjoy active devices with a as high as 300 GHz in technology nodes as 28-nm CMOS [28]. However, when these transconductors with high intrinsic performance are used in LC oscillators, the effect of the parasitics due to the layout interconnects severely limits the improvement in terms of effective and yields large fixed capacitance making the TR versus PN tradeoff tighter [29]. Furthermore, in deep-scaled CMOS processes: 1) low-level metals get thinner and closer to the substrate, reducing the quality factor of metal–oxide–metal (MOM) capacitors; 2) high-level metals get closer to the substrate, lowering the achievable of inductors; and 3) the design rule check (DRC) imposes ever-increasing minimum metal density to be fulfilled in tighter area windows, limiting even further the maximum achievable -factor and self-resonance frequency of on-chip inductors [22], [30]. A number of design techniques are discussed in this section to tackle the aforementioned challenges for mm-wave LC oscillators. As a first step, we focus on the design and layout of the active core. The parasitic gate-to-drain capacitance plays an important role in the design of any LC oscillator, lowering the oscillation frequency and limiting the TR [31], and the presented topology is no exception. As a matter of fact, shown in Fig. 1 appears single-ended, lowering the oscillation frequency as clear from (6). This capacitance is kept minimum by adopting the transistor layout presented in [29] and shown in Fig. 11. Moreover, thanks to this layout, it is now possible to access directly the gate and drain of the transistor in higher metal, limiting the losses due to interconnections to the tank. The source node is accessed at both sides, minimizing the critical gain reduction due to the connection to this net and simplifying the routing to and , shown in Fig. 1. In this design, the trasistors are oversized to 40 m/28 nm to account for possible model inaccuracy. Another key aspect of any mm-wave LC oscillator is the design and layout of the tank. Fig. 12 shows the 3-D view of the layout of the proposed gate-to-drain transformer. A relatively high value of the magnetic coupling coefficient between the primary and secondary windings (see Fig. 5) is desirable so that it becomes the dominant factor in the expressions of equivalent magnetic coupling in the ON and OFF state (17), (20). Since the value of the required self-inductances is relatively low, to maximize the magnetic coupling and are realized as an

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Fig. 12. 3-D layout view of the designed transformer with switched coupled inductor.

overlay transformer in metal 9 and 8, respectively (see Fig. 12), with a metal width of 4 m and an outer diameter of 37.8 m. The switched coupled inductor in Fig. 5 is realized with an inner coil and an outer coil in both metal 8 and 9 with 2- m width, connected together in metal 7. The inner and outer spacing of from the primary and secondary windings (i.e., and ) are 2.9 and 3.5 m, respectively (as shown in Fig. 12). As discussed in Section II-C, the value of and of the switch proves critical. Since at mm-wave the inductor -factor is relatively high, the value of will dominate the losses of the transformer in the ON state, as predicted from (15). is therefore designed large, with a W/L of (39 3) m/28 nm. To further optimize the switch figure of merit (FOM) ( ), the source and drain connections of are layouted with a tapered via stack to minimize . Fig. 13 shows the proposed gate-to-drain transformer with switched coupled inductor simulated parameters when the switch is in the ON and OFF state. From electromagnetic simulation, the equivalent magnetic coupling coefficient [see Fig. 13(a)], self-inductances [see Fig. 13(b)], and quality factors [see Fig. 13(c)] of primary and secondary windings of the transformer when is OFF (ON) are (0.5), pH (82 pH), pH (75 pH), (6), and (9) at 73.5 GHz (83.5 GHz). It is worth mentioning that, as is clear from the discussion about circuit-noise to phase-noise conversion in Section II-D and shown in Fig. 13(c), the winding with the higher quality factor is reserved to . To compensate for the degradation of the tank in the higher band (i.e., when is in the ON state), in this work the value of the degeneration capacitance is designed for optimal PN in this mode of operation, aiming at an uniform noise FOM over the whole TR. To further tune the oscillator continuously within the two bands, two binary-weighted digitally controlled MOM capacitors and an accumulation-mode MOS (A-MOS) varactor are added to the tank. To minimize the flicker noise to PN up-conversion, a voltagebiased topology is adopted in this design. Removing the current control is a critical choice, common to several state-of-the-art low-noise mm-wave LC oscillators (such as [13], [22], [27], and [32]). In fact, the lack of ideal current sources is exacerbated at high frequencies by the larger effect of the parasitic capacitance to the substrate.

Fig. 13. Simulated characteristics of the gate-to-drain transformer with is ON (solid grey line) and OFF switched coupled inductor when (dashed black line) against frequency. (a) Equivalent magnetic coupling . and ). (b) Self-inductance of the primary and secondary winding ( and ). (c) Quality factor of the primary and secondary winding (

Fig. 14 shows the block diagram of the realized chip. For measurement purposes, two buffers and an I/Q double-balanced mixer are also implemented on-chip. The buffers are realized with pseudo-differential neutralized common source amplifiers, providing high input–output isolation, driving the 50- measurement equipment directly at mm-wave and controlling the on-chip mixer. The latter is based on a Gilbert cell, allowing the downconversion of the high-frequency on-chip quadrature signals to an IF, instrumental to measure I/Q amplitude and phase imbalance. IV. MEASUREMENT RESULTS Fig. 15 shows the die micrograph of the QVCO prototype fabricated in 28-nm bulk CMOS technology with no RF thick

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Fig. 14. Block diagram of the realized test chip.

Fig. 16. Measured PN from a: (a) 72.7-GHz carrier and (b) 88.2-GHz carrier.

Fig. 15. Die micrograph of the realized test chip (core dimensions: 120 m 262 m).

metal option. It occupies an active area of only 0.031 mm . All the measurements are performed on a high-frequency probe station. The mm-wave output of the QVCO after the buffer and the external LO input of the double balanced I/Q mixer (see Fig. 14) are directly accessed by ground–signal–ground (GSG) probes, while the dc and IF signal pads are wire-bonded to a printed circuit board (PCB). The QVCO consumes 35.6 mW from a 0.7-V supply. The oscillation frequency is tunable from 71.4 to 76.1 GHz when is OFF and from 85.6 to 90.7 GHz when is ON, corresponding to 9.8 GHz of total TR. By varying the A-MOS varactor voltage from 0 to 1.2 V and acting on the two binary-weighted digitally controlled MOM capacitors, the oscillator realizes continuous tuning within the two bands. Fig. 16(a) and (b) shows the measured PN from a 72.7- and 88.2-GHz carrier respectively. The signal is measured at the output of the buffer directly at mm-wave and downconverted with an external mixer. The prototype achieves a measured PN at 1 MHz and 10-MHz offset of 93.5 and 117.7 dBc/Hz from a 72.7-GHz carrier and 86.2 and 110 dBc/Hz from a 88.2-GHz carrier. The measured corner is 2 MHz. The same measurements are repeated over the TR and are summarized and compared against simulations in Fig. 17(a) at

Fig. 17. Measured and simulated: (a) PN and (b) noise FOM at 10-MHz offset from the carrier against frequency.

10-MHz offset, showing that the measured PN ranges from 114.2 to 117.7 dBc/Hz in the lower band and from 107 to 110 dBc/Hz in the higher one. The resulting measured noise FOM ranges from 176.3 to 179.4 dBc/Hz and from 170.2 to 173.4 dBc/Hz in the higher and lower band, respectively, as reported in Fig. 17(b), together with the expected results. No RF transistor model was available during the design phase, resulting in an inaccurate estimation of the ON resistance of , much larger than the other transistors by design, as explained in Section III. The measured oscillation frequency

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TABLE I COMPARISON WITH STATE-OF-THE-ART INTEGRATED QUADRATURE FREQUENCY GENERATION CIRCUITS IN THE 70/100-GHz BAND

Area

Fig. 18. Measured phase and amplitude imbalance of the I/Q signals downconverted to 260 MHz.

in the higher band therefore shows a shift of about 4.6 GHz toward higher frequencies, giving rise to a deviation from the optimal design point and a degradation of PN performance in this band. To measure the quadrature amplitude and phase imbalance, an external mm-wave signal is applied to the on-chip I/Q mixer driven by the QVCO. The resulting downconverted IF outputs are then measured with a sampling oscilloscope and shown in Fig. 18. Measurements repeated over the whole TR prove a phase error less than 1.5 in the lower band and less than 3.5 in the higher one. The amplitude error stays always below 1 dB in both bands. Noteworthy, in a practical system relatively simple on-chip calibration techniques may be adopted to compensate for such a limited phase error, allowing high-order modulation schemes as 64-QAM [4]. Table I summarizes and compares the measured performance of the QVCO prototype to state-of-the-art integrated quadrature frequency generation circuits in the 70–100-GHz band. Benefited by the presented design techniques, this work achieves the lowest power consumption while occupying the smaller silicon area, and showing a better or comparable PN that varies less than 3.5 dB within each band. To compare different designs, we adopt two noise FOMs defined as [11], [34] (24)

(25)

is the frequency offset where is the oscillation frequency, from the carrier, is the dc power consumption expressed in mW, and Area is expressed in mm . When such quadrature generation circuits are employed in direct-conversion transceivers, the LO feedthrough and PA pulling may become serious issues [4], [35]–[37]. It is therefore desirable to keep the number of on-chip inductors as small as possible and, in mm-wave CMOS design, area serves as a straightforward measure of this. Among the excellent designs in Table I, this work stands out for the lowest reported silicon area, without trading in power consumption or PN performance, leading to a measured between 3.6 and 12.8 dB higher than the best previously reported one. V. CONCLUSION A fundamental E-band QVCO based on gate-to-drain transformers to realize accurate quadrature phases and switched coupled inductors for tuning extension has been presented and analyzed. An in-depth discussion of the PN mechanism, adopted tuning extension technique, and phase error under tank mismatch has been reported, leading to optimal design for minimum PN and minimum phase error at the same time. Layout and implementation details relevant for mm-wave oscillators implemented in deep-scaled CMOS technology have been addressed. The QVCO prototype is tunable from 71.4 to 76.1 GHz in the lower band and from 85.6 to 90.7 GHz in the higher one, and shows low measured PN performance without trading in silicon area. The resulting across the TR advances the state-of-the-art between by 3.6 and 12.8 dB. APPENDIX Assuming differential quadrature operation, the equivalent ac large-signal model of the circuit schematic in Fig. 1 can be redrawn as in Fig. 19, where the ground reference is instrumentally shifted. Following the dissertation presented by Bevilacqua and Andreani in [38], in steady state it is now possible to replace the transconductor with its describing function approximation [18]. The resulting circuit is shown in Fig. 20. By applying the

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Fig. 19. Single-ended ac large-signal equivalent half circuit of the oscillator with an instrumental shift of the reference ground plane.

Fig. 20. Rearrangement of the circuit in Fig. 19 where the transconductor is replaced with its describing function approximation.

Norton’s theorem, the current source can be substituted with an equivalent current source in parallel with , as in Fig. 4, given (A.1) Since is in general a complex number (i.e., the current flowing through the transistor and are not in phase) and the transistor does enter the triode region, as discussed in Section II-D, the general result on PN stated in [39] and [25] does not apply. Therefore, in this work this simplified model is only used to get insight into the quadrature operation of the circuit and obtain an approximated expression of the oscillation frequency. ACKNOWLEDGMENT The authors are grateful to M. Keaveney, Analog Devices Inc. REFERENCES [1] J. Wells, Multigigabit Microwave and Millimeter-Wave Wireless Communications. Norwood, MA, USA: Artech House, 2010. [2] K. Okada et al., “Full four-channel 6.3-Gb/s 60-GHz CMOS transceiver with low-power analog and digital baseband circuitry,” IEEE J. Solid-State Circuits, vol. 48, no. 1, pp. 46–65, Jan. 2013. [3] H. Wu, N.-Y. Wang, Y. Du, and M.-C. Chang, “A blocker-tolerant current mode 60-GHz receiver with 7.5-GHz bandwidth and 3.8-dB minimum NF in 65-nm CMOS,” IEEE Trans. Microw. Theory Techn., vol. 63, no. 3, pp. 1053–1062, Mar. 2015. [4] D. Zhao and P. Reynaert, “A 40 nm cmos e-band transmitter with compact and symmetrical layout floor-plans,” IEEE J. Solid-State Circuits, vol. 50, no. 11, pp. 2560–2571, Nov. 2015. [5] S. Y. Kim, O. Inac, C.-Y. Kim, D. Shin, and G. Rebeiz, “A 76–84-GHz 16-element phased-array receiver with a chip-level built-in self-test system,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 8, pp. 3083–3098, Aug. 2013. [6] I. Nasr, B. Laemmle, K. Aufinger, G. Fischer, R. Weigel, and D. Kissinger, “A 70-90-GHz high-linearity multi-band quadrature receiver in 0.35 m SiGe technology,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 12, pp. 4600–4612, Dec. 2013.

[7] Z. Huang, H. Luong, B. Chi, Z. Wang, and H. Jia, “A 70.5-to-85.5 GHz 65 nm phase-locked loop with passive scaling of loop filter,” in Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2015, pp. 448–450. [8] C. Jany, A. Siligaris, J. Gonzalez-Jimenez, P. Vincent, and P. Ferrari, “A programmable frequency multiplier-by-29 architecture for millimeter wave applications,” IEEE J. Solid-State Circuits, vol. 50, no. 7, pp. 1669–1679, Jul. 2015. [9] A. Mazzanti, F. Svelto, and P. Andreani, “On the amplitude and phase errors of quadrature LC-tank CMOS oscillators,” IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1305–1313, Jun. 2006. [10] X. Yi, C. C. Boon, H. Liu, J. F. Lin, and W. M. Lim, “A 57.9-to-68.3 GHz 24.6 mW frequency synthesizer with in-phase injection-coupled QVCO in 65 nm CMOS technology,” IEEE J. Solid-State Circuits, vol. 49, no. 2, pp. 347–359, Feb. 2014. [11] N.-C. Kuo, J.-C. Chien, and A. Niknejad, “Design and analysis on bidirectionally and passively coupled QVCO with nonlinear coupler,” IEEE Trans. Microw. Theory Techn., vol. 63, no. 4, pp. 1130–1141, Apr. 2015. [12] M. Bajestan, V. Rezaei, and K. Entesari, “A low phase-noise wide tuning-range quadrature oscillator using a transformer-based dual-resonance LC ring,” IEEE Trans. Microw. Theory Techn., vol. 63, no. 4, pp. 1142–1153, Apr. 2015. [13] U. Decanis, A. Ghilioni, E. Monaco, A. Mazzanti, and F. Svelto, “A low-noise quadrature VCO based on magnetically coupled resonators and a wideband frequency divider at millimeter waves,” IEEE J. SolidState Circuits, vol. 46, no. 12, pp. 2943–2955, Dec. 2011. [14] M. Vigilante and P. Reynaert, “An E-band low-noise transformer-coupled quadrature VCO in 40 nm CMOS,” in Eur. Solid-State Circuits Conf., Sep. 2014, pp. 423–426. [15] M. Vigilante and P. Reynaert, “A dual-band E-band quadrature VCO with switched coupled transformers in 28 nm HPM bulk CMOS,” in IEEE Radio Freq. Integr. Circuits Symp. Dig., May 2015, pp. 119–122. [16] A. Hajimiri and T. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179–194, Feb. 1998. [17] L. Li, P. Reynaert, and M. Steyaert, “A Colpitts LC VCO with Millerenhancing and phase noise reduction techniques,” in capacitance Eur. Solid-State Circuits Conf., Sep. 2011, pp. 491–494. [18] T. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge, U.K.: Cambridge Univ. Press, 1998. [19] A. Bevilacqua, F. Pavan, C. Sandner, A. Gerosa, and A. Neviani, “A 3.4–7 GHz transformer-based dual-mode wideband VCO,” in Eur. Solid-State Circuits Conf., Sep. 2006, pp. 440–443. [20] G. Li, L. Liu, Y. Tang, and E. Afshari, “A low-phase-noise wide-tuning-range oscillator based on resonant mode switching,” IEEE J. Solid-State Circuits, vol. 47, no. 6, pp. 1295–1308, Jun. 2012. [21] M. Demirkan, S. Bruss, and R. Spencer, “Design of wide tuning-range CMOS VCOs using switched coupled-inductors,” IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1156–1163, May 2008. [22] E. Mammei, E. Monaco, A. Mazzanti, and F. Svelto, “A 33.6-to-46.2 GHz 32 nm CMOS VCO with 177.5 dBc/Hz minimum noise FOM using inductor splitting for tuning extension,” in Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2013, pp. 350–351. [23] J. Yin and H. Luong, “A 57.5–90.1-GHz magnetically tuned multimode CMOS VCO,” IEEE J. Solid-State Circuits, vol. 48, no. 8, pp. 1851–1861, Aug. 2013. [24] S. Levantino, P. Maffezzoni, F. Pepe, A. Bonfanti, C. Samori, and A. Lacaita, “Efficient calculation of the impulse sensitivity function in oscillators,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 10, pp. 628–632, Oct. 2012. [25] D. Murphy, J. Rael, and A. Abidi, “Phase noise in LC oscillators: A phasor-based analysis of a general result and of loaded ,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 6, pp. 1187–1203, Jun. 2010. [26] M. Babaie and R. Staszewski, “An ultra-low phase noise class-F2 CMOS oscillator with 191 dBc/Hz FoM and long-term reliability,” IEEE J. Solid-State Circuits, vol. 50, no. 3, pp. 679–692, Mar. 2015. [27] D. Murphy et al., “A low phase noise, wideband and compact CMOS PLL for use in a heterodyne 802.15.3c transceiver,” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1606–1617, Jul. 2011. [28] W. Sansen, “1.3 analog CMOS from 5 micrometer to 5 nanometer,” in Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2015, pp. 1–6. [29] D. Zhao and P. Reynaert, “A 60-GHz dual-mode class AB power amplifier in 40-nm CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 10, pp. 2323–2337, Oct. 2013. [30] J. Shi, K. Kang, Y. Z. Xiong, J. Brinkhoff, F. Lin, and X.-J. Yuan, “Millimeter-wave passives in 45-nm digital CMOS,” IEEE Electron Device Lett., vol. 31, no. 10, pp. 1080–1082, Oct. 2010.

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[31] B. Razavi, RF Microelectronics, 2nd ed. Upper Saddle River, NJ, USA: Prentice-Hall, 2011. [32] Z. Zong, M. Babaie, and R. B. Staszewski, “60 GHz 25% tuning range frequency generator with implicit divider based on third harmonic extraction with 182 dBc/Hz FoM,” in IEEE Radio Freq. Integr. Circuits Symp. Dig., May 2015, pp. 279–282. [33] E. Laskin et al., “Nanoscale CMOS transceiver design in the 90–170-GHz range,” IEEE Trans. Microw. Theory Techn., vol. 57, no. 12, pp. 3477–3490, Dec. 2009. [34] B. Soltanian, H. Ainspan, W. Rhee, D. Friedman, and P. Kinget, “An ultra-compact differentially tuned 6-GHz CMOS LC-VCO with dynamic common-mode feedback,” IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1635–1641, Aug. 2007. [35] A. Mirzaei, M. Mikhemar, and H. Darabi, “A pulling mitigation technique for direct-conversion transmitters,” in Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2014, pp. 374–375. [36] B. Razavi, “Design considerations for direct-conversion receivers,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 44, no. 6, pp. 428–435, Jun. 1997. [37] B. Razavi, “A study of injection locking and pulling in oscillators,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1415–1424, Sep. 2004. [38] A. Bevilacqua and P. Andreani, “Phase noise analysis of the tunedinput-tuned-output (TITO) oscillator,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 1, pp. 20–24, Jan. 2012. [39] A. Mazzanti and P. Andreani, “Class-C harmonic CMOS VCOs, with a general result on phase noise,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2716–2729, Dec. 2008.

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Marco Vigilante (S’14) was born in Carpi, Italy, in 1988. He received the B.S. and M.S. degrees in electrical engineering from the Università di Modena, Modena, Italy, in 2010 and 2012, respectively, and is currently working toward the Ph.D. degree on integrated circuit (IC) design for millimeter-wave (mm-wave) applications at KU Leuven, Leuven, Belgium. He is currently a Research Assistant with MICAS, KU Leuven.

Patrick Reynaert (SM’11) was born in Wilrijk, Belgium, in 1976. He received the Master of Industrial Sciences in Electronics (ing.) degree from the Karel de Grote Hogeschool, Antwerpen, Belgium, in 1998, and the Master of Electrical Engineering degree (ir.) and Ph.D. in Engineering Science degree (dr.) from KU Leuven, Leuven, Belgium, in 2001 and 2006, respectively. From 2006 to 2007, he was a Post-Doctoral Researcher with the University of California at Berkeley. During the summer of 2007, he was a Visiting Researcher with Infineon, Villach, Austria. Since October 2007, he has been an Associate Professor with the Department of Electrical Engineering (ESAT), KU Leuven, and a Staff Member of the ESAT-MICAS research group. His main research interests include mm-wave and THz CMOS circuit design, high-speed circuits, and RF power amplifiers. Dr. Reynaert is the Chair of the IEEE Solid-State Circuits Society Benelux Chapter. He serves or has served on the Technical Program Committees of several international conferences including ISSCC, ESSCIRC, RFIC, IEDM, and PRIME. He has served as an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS and as Guest Editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS. He was the recipient of the 2011 TSMCEuropractice Innovation Award and the 2014 Bell Labs Prize (2nd Prize).

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A Multi-Frequency Multi-Standard Wideband Fractional- PLL With Adaptive Phase-Noise Cancellation for Low-Power Short-Range Standards Ye Zhang, Member, IEEE, Jan Henning Mueller, Member, IEEE, Bastian Mohr, Member, IEEE, Lei Liao, Aytac Atac, Ralf Wunderlich, and Stefan Heinen, Fellow, IEEE

Abstract—This paper presents a wideband fractionalfrequency synthesizer design with a low-effort adaptive calibration quantization noise cancellation. After adopting technique for from the classical single-ended loop filter structure, this least mean square algorithm based calibration technique can precisely and efficiently adjust the noise cancellation digital–analog convertor current with high linearity and immunity. Besides, as long as the desired current is achieved, the calibration circuits are turned off and disconnected to save the power consumption and isolate from the signal paths. With the proposed phase-noise cancellation technique, small area and low power circuit design are achieved, meanwhile the fractional and reference spurs are highly attenuated, allowing the wideband direct frequency/phase modulation with high data rates. With low effort modification, it can be directly implemented as straightforward phase-noise enhancement for any wideband phase-locked loop applications. Index Terms—Adaptive noise cancellation, least mean square (LMS), low complexity, low power, multi-standard, frequency synthesizer, wideband.

I. INTRODUCTION

L

OW-POWER short-range wireless standards, namely, Bluetooth, Zigbee, smart network unity (SUN), and wireless body area network (WBAN) have been deployed in a rapidly increasing number of applications. The variety of their applications generates the demand of co-integration of a

Manuscript received July 31, 2015; revised November 30, 2015 and February 10, 2016; accepted February 20, 2016. This paper is an expanded version from the IEEE RFIC Symposium, Phoenix, AZ, USA, May 17–19, 2015. Y. Zhang was with the Chair of Integrated Analog Circuits and RF Systems, RWTH Aachen University, D-52062 Aachen, Germany. He is now with the Research and Development Center, Intel, D-47259 Duisburg, Germany (e-mail: [email protected]). J. Henning Mueller, R. Wunderlich, and S. Heinen are with the Chair of Integrated Analog Circuits and RF Systems, RWTH Aachen University, D-52062 Aachen, Germany. B. Mohr was with the Chair of Integrated Analog Circuits and RF Systems, RWTH Aachen University, D-52062 Aachen, Germany. He is now with the Research and Development Center, Intel, D-85579 Munich, Germany. L. Liao is with the Chair of Integrated Analog Circuits and RF Systems, RWTH Aachen University, D-52062 Aachen, Germany, and also with the Research and Development Center, Infineon, D-85579 Munich, Germany. A. Atac was with the Chair of Integrated Analog Circuits and RF Systems, RWTH Aachen University, D-52062 Aachen, Germany. He is now with E.ON, D-14467 Potsdam, Germany. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2536022

low-power low-cost transceiver. Meanwhile multiple standards with different carrier frequency bands, data rates, and modulation schemes are desired to be supported simultaneously. In the receiver side, it features multiple RF frontends and shared IF or baseband signal-processing circuits [1]. A sliding IF technique can realize the signals from multi-frequency bands downconversion with a single local oscillator (LO) generator [2], [3]. For example, a phase-locked loop (PLL) operating at a 1.6–1.8-GHz range can be used to cover a 2.4-GHz band with dual conversion, 400 MHz as well as a 900-MHz band with a frequency divider. In the transmitter side, it is more desirable to realize direct frequency/phase modulation rather than two-point modulation to reduce the circuit complexity. Thus, the fractional- PLL bandwidth needs to be extended to pass through the modulation signal to support fast frequency hopping [4]. In this case, the high-pass-shaped quantization noise and spurs caused by modulator limits the PLL phase-noise performance as they cannot be sufficiently suppressed by the loop filter anymore. Many efforts have been investigated to suppress the quantization noise impact in wideband PLL design. One methodology is to directly enhance the modulator resolution either with the multiphase interpolator at VCO output [5], [6] or the fractional frequency divider [7], [8]. However, very precise design is required to achieve the phase linearity in small step size at carrier frequencies, and a glitch is always an issue when realizing the true fractional division ratio. Another idea is to remove the quantization noise at the feedback clock signal: multiple frequency dividers with constant delay can be placed in parallel to realize the embedded finite impulse response averaging filter [9], [10]. The feedback signal can also flow into a nested PLL where the high-frequency noise is attenuated by its narrowband loop filter [11]. In this way its phase-noise performance greatly depends on the tap number of the averaging filter and nested PLL jitter performance. In addition, a large effort needs to be made in additional analog circuits design and stability analysis. One of the most popular solutions is to insert a noise cancellation path inside of the PLL loop, where the residue quantization error is digitally calculated, translated to compensation currents, and injected into the loop filter [12]–[14]. It also requires a very precise gain matching of the cancellation path [15]. A least mean square (LMS) algorithm is widely used in a low-IF receiver for image interference rejection

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and in-phase/quadrature-phase (I/Q) mismatch calibration [16]–[18]. For minimizing the cancellation path mismatch in wideband PLL design, it is firstly reported in [19]. By multiplying the mismatching error detected at loop filter output with a sign value of the residue quantization error, the DAC gain is adjusted according to the accumulator output in the digital domain. However, it causes long settling time since the dc offset at the loop filter output needs to be estimated and eliminated. The LMS calibration technique is improved with differential loop filter and integrator topologies to avoid the dc offset issues [20]. The sign multiplier is implemented as a pair of switches in front of the loop filter so that the mismatching error can be continuously fedback to the digital–analog convertor (DAC) in the analog domain. Hence, the settling time can be dramatically reduced. However, it brings potential issues: several common mode (CM) to differential mode (DM) and DM–CM convertors are needed for signal translation so the sensitivity and linearity of the PLL system, especially for the voltage-controlled oscillator (VCO), are influenced. The switches for sign multiplications are implemented inside of the signal loop. As they are triggered at the reference clock, additional spurs are generated at the PLL output. The focus of this work is a detailed assessment of the adaptive calibration technique for phase-noise cancellation, which has been demonstrated in [21]. Adopted from the classical loop filter structure, another low-pass output signal is generated inside of the loop filter as the reference for the LMS algorithm so that the whole PLL can stay in a single-ended topology without concerning dc offset issues. The cancellation path gain mismatch is detected and calibrated outside of the PLL loop so the nonlinearity issue is not introduced into the system. As long as the desired reference current is achieved, the calibration circuits are disabled and disconnected to other circuits. Thus, it will not influence the system performance. Compared to the previous works, the proposed technique provides a simple and straightforward structure for wideband PLL designs. Smaller area and lower power consumption are achieved with excellent phase-noise and spur performance. This paper is organized as follows. Section II briefly reviews the general signal flow in the wideband frequency synthesizer system and introduces the typical architecture for quantization noise cancellation based on the LMS algorithm. Section III describes the proposed frequency synthesizer architecture for adaptive noise cancellation, and its key circuit mechanism is explained in detail. The measurement results and performance comparison are shown in Section IV. Finally, conclusions are drawn in Section V. II.

QUANTIZATION NOISE CANCELLATION

Fig. 1. Wideband PLL with quantization noise cancellation path.

instantaneously the divider output will never be phase locked to the reference. The PLL acts on this sequence as a low-pass filter in the process of converting it to output phase noise. Therefore, spectral components of outside the bandwidth of the PLL are suppressed, but those inside the bandwidth of the PLL are amplified through the discrete-time integration and can add significantly to the overall phase noise [22]. At the charge pump (CP) output, the current pulses are always added to the subtracting charge from the loop filter, whose average charge added to the loop filter is zero. Thus, the CP pulse-width modulated (PWM) charge injected at each VCO period is expressed as

(1) denotes the accumulated quantization where error. The typical solution to suppress the PLL phase noise that would otherwise result from quantization noise has been addressed using a DAC cancellation path to suppress . By inserting a quantization noise cancellation path, the digital residue error is accumulated, translated to the DAC compensation current, and injected into the loop filter. The DAC converts the quantization error into a pulse-amplitude modulated (PAM) charge, which have a charge nominally equal in magnitude and opposite in sign to the CP charge (2) can cancel the From (1) and (2), the DAC current noise at the CP output corresponding to the residue quantization error if it has the correct gain

A. Overview Fig. 1 shows the fractional- frequency synthesizer architecture with a quantization noise cancellation path. In the fractional PLL, in order to realize the fractional division ratio, the integer value is modulated with a modulator, whose quantization noise is high-pass shaped. As it is only possible for the divider edge to occur after an integer multiple of the VCO period,

(3)

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However, the quantization noise and the compensation signals go through two different paths, the gain of the noise cancellation path cannot be perfectly matched to the signal path. Since the CP pulses have a fixed amplitude and variable widths, whereas the DAC pulses have a fixed width and variable amplitudes, generating the width-modulated DAC pulses corresponding to the modulation is difficult. The DAC pulses can be mismatched from the CP pulses due to static current mismatch or pulse-width mismatches. This results in a residual charge error remaining on the loop filter, limiting the achievable phase-noise cancellation. Besides, the compensation current is generated using digital error accumulator structures designed to ensure that the sum of is bounded. The resulting sequence tends to have a large dynamic range, a high spurious tone content, and significant spectral power within the PLL bandwidth. Therefore, excellent cancellation accuracy is required if is only partially canceled because of gain errors, distortion, or insufficient dynamic range in the DAC cancellation path. The remaining portion of contains in-band noise and spurious tones, which can contribute significant phase noise. A more recent technique that circumvents the DAC precision and gain matching problems uses a digital modulator to generate the compensation current such that has at least one zero at dc with most of its power concentrated at high frequencies, outside the passband of the PLL. must be nearly free of spurious tones, or else high gain accuracy would again be required in the DAC cancellation path to properly cancel the spurious tones. Hence, usually requantization and a segmented mismatch-shaping current pulse DAC are used to obtain a high DAC cancellation path dynamic range and linearity, and 1-bit dithering is used to eliminate spurious tones [23].

B. LMS Algorithm for DAC Gain Calibration The DAC gain mismatch can be continuously detected because it results in a fraction of the original charge being deposited into the loop filter in each reference period. The LMS algorithm can be used to minimize the mismatches by adjusting the DAC gain according to the errors at the loop filter output adaptively. Fig. 2 shows the ideal of the LMS algorithm based DAC gain calibration in [19]. In this work, two additional blocks are added to the conventional PLL system. The cancellation block compensates the divider ratio noise, and the correction block detects the CP/DAC gain mismatch error. Together they complete an adaptive zero forcing feedback based on a sign–sign LMS algorithm [24]. It relies on the direct correlation of the actual accumulated ratio error because of CP/DAC mismatch with the sign of the integrated phase error . The CP/DAC mismatch information is extracted from the loop filter and correlated with the accumulated quantization error. A modulator converts this correlation to a 1-bit stream, which is fed into the digital block for the low-pass filter. The strength of this algorithm lies in correction of CP/DAC mismatch based on the actual perturbations occurring at the loop filter.

PLL

3

Fig. 2. LMS algorithm for DAC gain calibration.

Fig. 3. Differential LMS gain calibration.

After the CP and DAC pulses occur, the loop filter voltages settle to a constant value related to this charge. The mismatch is estimated by multiplying this loop filter voltage with a binary correlation signal at each reference period. Therefore, if the DAC gain is greater or less than the CP gain, the correlated loop filter voltage will experience a net positive or negative dc value, respectively. This dc value is accumulated and used to modify the DAC gain by adjusting the DAC reference current. The feedback of the calibration loop as an adaptive filter adjusts the DAC gain to minimize the dc component of the correlated loop filter voltage

(4) However, the noise arising from the multiplication of the correlation signal with the dc loop filter voltage and quantization noise from the modulator must be filtered prior to adjust the DAC bias current. This results in a long transient response of the calibration circuit. Secondly, the buffer needs to provide isolation for the loop filter and, thus, requires a significant amount of power consumption. Finally, the dc loop filter voltage varies according to the different output frequencies. To further ensure that any remaining dc offset does not affect the update decisions, the sign sequence must be made to have a zero mean so that the dc component can be chopped and averaged out.

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Fig. 4. Top-level block diagram of the proposed synthesizer.

C. Differential Topology in LMS Error Detection The LMS calibration techniques is improved by modifying the loop filter and the VCO topologies [20]. As show in Fig. 3, analog continuous-time fully differential calibration circuits are utilized to reduce the noise from quantization and correlation of the dc loop filter voltage and to eliminate the sampling of the loop filter voltage. The issues mentioned in Section II-B, such as the calibration loop bandwidth limitation, and the loop filter dc voltage variation can be overcome. The VCO has two equal half-sized inputs, each of which is connected to a loop filter with identical component values. If both input terminals of the VCO are connected together, the VCO would have the identical characteristic as a normal singleinput VCO. In this way, the output frequency is proportional to the sum of the two input voltages, but insensitive to the difference between the two input voltages. Hence, the correlation signal is constant over the duration of a CP/DAC pulse, and it switches the CP/DAC currents between two equivalent loop filters. The accumulated quantization error is related to the CP/DAC charge, the switching of the CP/DAC current is equivalent in DM to multiply and by and results in a modulation in the DM voltage. In practice, and are large pulses of current occurring over a short duration. It causes a significant change at the input of the calibration loop during the DAC pulse, which results in a significant change in the DAC reference current during the duration of the DAC pulse. The differential low-pass filtered voltages in the calibration loop are used to smooth the variation in the DAC reference current for the duration of a DAC pulse. Therefore, it contains the correlated signal information necessary for calibration loop operation.

Similar to the VCO operation, the calibration loop is a differential circuit and can be designed to obtain very low sensitivity against the CM signal. In this way, the CM voltage is used in the PLL signal path, and the DM voltage is used in the calibration signal path. Therefore, the LMS calibration technique by differential topologies of the VCO, loop filter, and the integrator to reject the dc common voltage. The sign-bit multiplication is implemented as a pair of switches in front of the loop filter so that the mismatching error can be continuously fedback to the DAC in the analog domain. The settling time is dramatically shortened without the limitation of the calibration bandwidth. However, there are still several potential issues coming out: the mismatches in the two signal paths results in a CM–DM conversion in the calibration loop, and a DM–CM conversion in the signal path, which affect the PLL system sensitivity and linearity, especially for the VCO control voltage; the mismatches between the loop filter halves and between the varactor halves cause phase-noise performance degradation, high symmetric layout is required; the differential switches triggered at the reference clock are located inside the signal correlation path, generating additional spurs at the reference and its harmonic frequencies. III. PROPOSED WIDEBAND SYNTHESIZER ARCHITECTURE The top-level block diagram of the proposed wideband synthesizer with an adaptive noise-cancellation technique is shown in Fig. 4. Excluding the crystal, all the elements in the gray region are fully integrated as well as a three-wire configuration interface and a high-speed baseband data interface. Two functional blocks added to a conventional synthesizer are quantization noise cancellation and DAC gain calibration circuits. In the noise-cancellation path, the residue of the thid-stage quantizer

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in MASH-111 is directly truncated and differentiated in second order instead of another requantizer. In this way, the identical noise shaping is achieved with lower computation complexity, and at the same time the dynamic range of is limited with zero means, which will not lead to the stability issue [25], [26]. Subsequently the residue error from the quantizer is segmented aligned to control the two 32-bit DAC banks, respectively, for the coarse and the fine currents tuning. A fourth-order loop filter is adopted from the classical structure to generate the desired and reference signal for the LMS noise-cancellation process. The calibration circuits consist of a multiplier, an integrator, and a voltage-to-current (VC) converter between the modified loop filter and the DAC current reference. The 4-bit most significant bits (MSBs) of the residue error are differentially coded into the analog domain and connected to the calibration circuits for multiplication. If there is a gain mismatch between the signal path and noise cancellation path, a residue quantization error voltage will be left in the loop filter, which modulates the VCO and, hence, generates fractional spurs. Since each CP output pulse contains an error term proportional to the accumulated quantization noise, the DAC gain can be adjusted adaptively based on the LMS algorithm by multiplying the buffered loop filter voltage with the accumulated quantization error. However, the challenge of the calibration circuit is how to detect the small residue error accumulated in the loop filter with high sensitivity, and how to correlate it fast and precisely without disturbing the signal flow path. The key building blocks are illustrated in Sections III-A–III-C. A. Loop Filter Fig. 5 shows the structure and characteristic of the fourthorder loop filter. In the first stage, a switch triggered at the reference clock is used for spur cancellation. Since the CP pulses have a fixed amplitude and modulated width, whereas the DAC pulses have a fixed width and modulated amplitude, their occurring time cannot be exactly synchronized. The spur cancellation switch turns off when the CP or DAC current exist, keeping the integrated charging/discharging current errors away from the VCO control signal. Subsequently it turns on when neither CP, nor the DAC is enabled so that the total current pulses due to CP/DAC mismatch are smoothly converted into the voltage domain in the loop filter. The following stage contains a cascaded low-pass RC filter and generates two extra poles. The first extra pole is slightly lower than the reference frequency, thus it can pass through the modulated baseband signals. Therefore, the residue voltage resonated at the reference frequency according to the CP/DAC current mismatches can be obviously seen at the LPF1 port. This port is directly connected to the VCO. The second extra pole is located far below the reference frequency with a large RC filter so a flatter waveform is obtained at the LPF2 port. Since this port is directly used as the LMS reference voltage without any feedback loop, the PLL signal transfer function and calibration signal transfer function will not be affected. The group-delay difference between LPF1 and LPF2 can be ignorable compared with the reference clock. After subtracting the voltages at these

PLL

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Fig. 5. Proposed loop filter structure and characteristic.

Fig. 6. Proposed gain calibration circuits: multiplexer, integrator, and VC convertor.

Fig. 7. Adaptive calibration process.

two ports this residue cancellation error information can be extracted, as they share the same dc level voltage. B. Calibration Circuits Fig. 6 shows the schematic of the calibration circuits. In the first stage the residue errors are linearly copied by the source–followers. The differential 4-bit residue quantization errors and are connected to the gate voltages of the cross-coupled switches for multiplication. Instead of sign-bit multiplication in [19] and [20], faster settling time and higher

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Fig. 8. CP and DAC current generator.

accuracy are achieved in the error detection process. When the MOS switches operate in the linear region, their impedance are modulated linearly according to the gate voltage. Thus, the output voltage difference is proportional to the product of the input voltage difference and the residue quantization error (5) In the second stage, the RC integrator is used to accumulate the correlated signal information, which contains the CP/DAC mismatches. The operational amplifier has 80-dB dc gain to detect the small differential errors, and a wide input common range for the loop filter voltage variation over the PLL frequency range. Compared to the fully differential integrator, the input offset of the OP cannot lead to the DAC current mismatches since the static current offset will be calibrated by the feedback loop in the calibration process. When the reset switches are turned on, the integrator output is set as an initial value . The LMS filter bandwidth is determined by switched-capacitor arrays with a maximum value of 4 pF. The integrator output signal is expressed as (6) In the final stage, the integrated voltage is converted to a current and mirrored to the DAC reference current (7) With the same principle, the voltage offset in the VC convertor, the resistance variation, and the PVT mismatches are also

Fig. 9. PLL micrograph.

not harmful, as the final current will be calibrated in the feedback back loop according to the accumulated error. Fig. 7 shows the waveforms of the VCO control voltage and the DAC reference current in the calibration process based on Verilog-AMS models. After the PLL gets locked, it remains noisy because of the quantization error, and a large VCO control voltage modulation can be detected. The DAC is then enabled so that the default reference current is used for noise cancellation. The VCO control voltage variation is clearly reduced. It is assumed that still 10% current mismatches remains with the default setting. When the LMS is enabled, the DAC bias current gets converged after 20 s and reaches the desired current, meanwhile the VCO control voltage variation is decreased gradually. Finally, the hold on switch isolates the DAC bias current from the calibration circuits. At the same time, the multiplication and integration circuits are switched off, saving 1.2-mA current (14% of the system). In the end the DAC reference current stays constant and immune to other blocks.

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PLL

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Fig. 11. Reference spur performance.

Fig. 10. (a) Phase-noise comparison. (b) Spectral comparison.

Fig. 12. Modulation performance.

C. CP and DAC Banks As shown in Fig. 8, the CP and DAC are implemented in the same block because they are composed of the same unit cell and share the same biasing and output nodes. The MSB and LSB banks of the DAC are thermometer coded to achieve monotonicity. Inside the unit cell, the loads for differential control signals are equalized with one PMOS and one NMOS to compensate rising/falling timing mismatches and charge injection, as illustrated in [27]. A wide input range amplifier stabilizes the differential output voltages so that the common nodes in the CP and DAC can be pushed or pulled to the same level, making the currents of both paths identical over the PLL frequency range. A dummy capacitor is used to equalize the loads. With the symmetric topology of the CP and DAC, the fractional and reference spurs due to the charging/discharging current mismatches can be greatly improved. IV. MEASUREMENT RESULTS A 1.8-GHz fractionalsynthesizer was fabricated in 130-nm CMOS, where the mixed-signal and RF parts were full

Fig. 13. Polar transmitter based on dual conversion.

custom design and the digital block was synthesized using the standard logic cells. The die micrograph is shown in Fig. 9. It occupies 0.33 mm and consumes 8.3-mW core power, excluding a differential 3.5-mA current mode logic (CML) buffer to drive the PLL output. The PLL output frequency range is from 1.6 to 1.8 GHz, and its loop bandwidth is adjustable from 150 kHz to 1.5 MHz with a crystal reference clock of 32 MHz. The VCO is a symmetric LC oscillator with a nominal sensitivity of 75 MHz/V. The multi-modulus divider consists of a six-stage 2/3 prescaler resulting a division ratio from 64 to 127. Electrostatic discharge (ESD) protection diodes are implemented on all pins.

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TABLE I PERFORMANCE COMPARISON WITH PRIOR WORKS

Fig. 14. (a) Eye pattern of 1-Mb/s GFSK Bluetooth LE signal at 2.4-GHz variable gain amplifier (VGA) output. (b) Eye pattern of 200-kb/s 4FSK SUN signal at 2.4-GHz VGA output.

Fig. 10 shows the phase noise and spectral comparison, respectively, with the initial state, DAC enabled state, and calibration enabled state at 1.76-GHz carrier frequency. Starting from the initial state, it can be seen the quantization noise are suppressed after the DAC is turned on. The outband phase noise performance at 3-MHz offset is improved from 110 dBc Hz to 122 dBc Hz. When the CP/DAC gain calibration technique is enabled, the phase-noise performance is further improved, and the fractional and reference spurs are also greatly attenuated. In the final hold on state, the phase-noise performance at 3-MHz offset finally achieves 129 dBc Hz with the proposed technique. Fig. 11 shows the reference spur performance in fractional mode is 68 dBc. In the integer mode the spur performance is 72 dBc, which indicates good immunity of the PLL system to the modulated switching process. The fractional spur performance in the worst case is 56 dBc. Fig. 12 shows the PLL output spectral of 1-Mb/s data rate 250-kHz frequency deviation Gaussian frequency shift keying (GFSK) modulated Bluetooth LE baseband signal. When the loop filter bandwidth is set as 1 MHz, an obvious improvements

Fig. 15. (a) Constellation diagram of 1-Mb/s OQPSK ZigBee signal at -DQPSK 900-MHz VGA output. (b) Constellation diagram of 500-kb/s signal at 900-MHz VGA output.

can be seen when the proposed calibration technique is enabled. Comparing with the 300-kHz two-pint modulation technique, the proposed calibration technique with direct modulation demonstrates the same excellent performance. Fig. 13 shows the block diagram of a polar transmitter based on dual conversion topology. The proposed PLL output is connected to a frequency divider to obtain 900-MHz frequency band, and it is also mixed up with itself to obtain 2.4-GHz frequency band. Through the COordinate Rotation DIgital Computer (CORDIC), the polar amplitude component is connected to voltage gain amplifiers to adjust the output power, and the phase component is differentiated to a frequency modulation signal to control the PLL. Fig. 14 shows the eye patterns of a 1-Mb/s GFSK Bluetooth LE signal and 200-kb/s 4 frequency shift keying (4FSK) SUN signal at a 2.4-GHz unlicensed band. The eyes are clearly open so the transmitted signal can be successfully demodulated and decoded at the receiver side. Fig. 15 shows the constellation diagram of a 1-Mb/s offset quadrature phase shift keying (OQPSK) modulated signal for a ZigBee and SUN standard, and 500-kb/s differential quadrature frequency shift keying at a 900-MHz unlicensed

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band. In both cases the error vector magnitude (EVM) is below 5%. Obviously standards with lower data rates and less complicated modulation schemes can also be supported. Table I shows a comparison between the proposed design and other relevant prior art. The proposed approach exhibits the excellent phase noise and spur suppression performance with lower power consumption and smaller area. V. CONCLUSION A low-effort adaptive phase-noise cancellation calibration technique for the fully integrated wideband fractional- synthesizer based on the classical loop filter structure has been presented. This calibration technique demonstrates fast and precise settling, low spurs, and excellent phase-noise performance with low power consumption and small area. Due to its simplicity and flexibility, it can be directly added as a straightforward phase-noise enhancement technique for wideband PLLs, and also provides an easy and feasible solution of direct frequency/phase modulation for short-range wireless standards. REFERENCES [1] Y. Zhang, J. H. Mueller, B. Mohr, and S. Heinen, “Low-power lowcomplexity multi-standard digital receiver for joint clock recovery and carrier frequency offset calibration,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 12, pp. 3478–3486, Dec. 2014. [2] T. Cho, D. Kang, C.-H. Heng, and B.-S. Song, “A 2.4-GHz dual-mode 0.18 m CMOS transceiver for Bluetooth and 802.11b,” IEEE J. SolidState Circuits, vol. 39, no. 11, pp. 1916–1926, Nov. 2004. [3] L. Zhang et al., “A reconfigurable sliding-IF transceiver for 400 MHz/2.4 GHz IEEE 802.15.6/ZigBee WBAN Hubs with only 21% tuning range VCO,” IEEE J. Solid-State Circuits, vol. 48, no. 11, pp. 2705–2716, Nov. 2013. [4] P.-E. Su and S. Pamarti, “Fractional phase-locked-loop-based frequency synthesis: A tutorial,” IEEE Tran. Circuits Syst. II, Exp. Briefs, vol. 56, no. 12, pp. 881–885, Dec. 2009. [5] K. Takinami, R. Strandberg, P. C. P. Liang, G. Le Grand de Mercey, T. Wong, and M. Hassibi, “A distributed oscillator based all-digital PLL with a 32-phase embedded phase-to-digital converter,” IEEE J. Solid-State Circuits, vol. 46, no. 11, pp. 2650–2660, Nov. 2011. [6] P.-E. Su and S. Pamarti, “A 2.4 GHz wideband open-loop GFSK transmitter with phase quantization noise cancellation,” IEEE J. Solid-State Circuits, vol. 46, no. 3, pp. 615–626, Mar. 2011. [7] S. Pellerano, P. Madoglio, and Y. Palaskas, “A 4.75-GHz fractional frequency divider-by-1.25 with TDC-based all-digital spur calibration in 45-nm CMOS,” IEEE. J. Solid-State Circuits, vol. 44, no. 12, pp. 3422–3433, Dec. 2004. [8] Y. Zhang, R. Wunderlich, and S. Heinen, “An ultra low power frequency synthesizer based on multiphase fractional frequency divider,” in IEEE Int. Circuits Syst. Symp., 2012, pp. 2589–2592. [9] X. Yu, Y. Sun, W. Rhee, H. K. Ahn, B. Park, and Z. Wang, “A fractional- synthesizer with customized noise shaping for WCDMA/ HSDPA applications,” IEEE J. Solid-State Circuits, vol. 44, no. 8, pp. 2193–2201, Aug. 2009. [10] D. Jee, Y. Suh, H. Park, and J. Sim, “A FIR-embedded phase interpolator based noise filtering for wide-bandwidth fractional- PLL,” IEEE J. Solid-State Circuits, vol. 48, no. 11, pp. 2795–2804, Nov. 2013. [11] P. Park, D. Park, and S. Cho, “A 2.4 GHz fractional- frequency modulator and nested PLL,” IEEE J. synthesizer with high-OSR Solid-State Circuits, vol. 47, no. 10, pp. 2433–2443, Oct. 2012. [12] S. Pamarti, L. Jansson, and I. Galton, “A wideband 2.4-GHz PLL with 1-Mb/s in-loop modulation,” delta–sigma fractionalIEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 49–62, Jan. 2004. [13] E. Temporiti, G. Albasini, I. Bietti, R. Castello, and M. Colombo, “A 700-kHz bandwidth sigma-delta fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1446–1454, Sep. 2004.

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[14] S. Meninger and M. Perrott, “A 1-MHz bandwidth 3.6-GHz 0.18- m CMOS fractional- synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise,” IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 966–980, Apr. 2006. [15] S. Pamarti and I. Galton, “Phase-noise cancellation design tradeoffs in delta-sigma fractional- PLLs,” IEEE Tran. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 11, pp. 829–838, Nov. 2003. [16] Y. Zhang, Y. Wang, R. Wunderlich, and S. Heinen, “A novel low-effort demodulator for low power short range wireless transceivers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 9, pp. 2521–2532, Sep. 2013. [17] Y. Zhang, R. Wunderlich, and S. Heinen, “Low complexity image rejection demodulator for bluetooth LE applications,” in IEEE Int. Circuits Syst. Symp., 2013, pp. 341–344. [18] S. Lerstaveesin, M. Gupta, D. Kang, and B.-S. Song, “A 48–860 MHz CMOS low-IF direct-conversion DTV tuner,” IEEE J. Solid-State Circuits, vol. 43, no. 9, pp. 2013–2024, Sep. 2008. [19] M. Gupta and B.-S. Song, “A 1.8 GHz spur-cancelled fractionalfrequency synthesizer with LMS-based DAC gain calibration,” in Int. Solid-State Circuits Tech. Dig., 2006, pp. 1922–1931. [20] A. Swaminathan, K. Wang, and I. Galton, “A wide-bandwidth 2.4 GHz ISM band fractional- PLL with adaptive phase noise cancellation,” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2639–2650, Dec. 2007. [21] Y. Zhang et al., “A wideband fractional- synthesizer with low effort adaptive phase noise cancellation for low-power short-range standards,” in RF Integr. Circuits Symp., 2015, pp. 71–74. [22] H. Hedayati, B. Bakkaloglu, and W. Khalil, “Gain and phase error-free LINC transmitter,” IEEE Tran. Microw. Theory Techn., vol. 54, no. 10, pp. 3654–3663, Oct. 2006. [23] S. Pamarti, J. Welz, and I. Galton, “Statistics of the quantization noise in 1-bit dithered single-quantizer digital delta-sigma modulators,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 3, pp. 492–503, Mar. 2007. [24] S. Lerstaveesin and B.-S. Song, “A complex image rejection circuit with sign detection only,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2693–2702, Dec. 2006. [25] Y. Zhang, R. Wunderlich, and S. Heinen, “A low-complexity low-spurs digital architecture for wideband PLL applications,” Microelectronics J., vol. 45, no. 7, pp. 842–847, 2014. [26] H.-Y. Jian, Z. Xu, Y.-C. Wu, and M.-C. Chang, “A fractional- PLL for multiband (0.8–6 GHz) communications using binary-weighted D/a differentiator and offset-frequency delta–sigma modulator,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 768–780, Apr. 2010. [27] Y. Zhang et al., “A 2.4-GHz low power high performance frequency synthesizer based on current-reuse VCO and symmetric charge pump,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., 2013, pp. 119–122.

Ye Zhang (GSM’11–M’15) received the B.S. degree in electrical engineering from Zhejiang University, Zhejiang, China, in 2007, and the M.S. degree in communication engineering from RWTH Aachen, Aachen, Germany, in 2010. He was with the Chair of Integrated Analog Circuits, RWTH Aachen. Since 2015, he has been with the Research and Development Center, Intel, Duisburg, Germany. His research interests include frequency synthesizers and RF signal processing.

Jan Henning Mueller (M’05) received the Dipl.-Ing. degree in electrical and information engineering from RWTH Aachen University, Aachen, Germany, in 2009. After his studies, he joined the Department of Electrical Engineering, RWTH Aachen University. In December 2015, he joined Innsystec, a university spin-off that develops novel energy-efficient transmitters. His research interests are in the area of mixed-signal circuit design and RF systems.

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Bastian Mohr (S’10–A’14–M’16) studied electrical engineering and information technology at RWTH Aachen University, Aachen, Germany. He received the Diplom-Ingenieur degree from RWTH Aachen University, in 2009. He was the Chair of Integrated Analog Circuits and RF Systems at RWTH Aachen University. Since 2015, he has been with the Research and Development Center, Intel, Munich, Germany. His research interests include mobile transmitter architectures, digital signal processing, and RF frontends.

Lei Liao received the Diplom-Ingenieur degree in electrical engineering from RWTH Aachen University, Aachen, Germany, in 2008, and is currently working toward the Dr.-Ing degree at RWTH Aachen University. Since 2009 he has been with the Chair of Integrated Analog Circuits and RF Systems, RWTH Aachen University. Since 2014, he has been with the Research and Development Center, Infineon, Munich, Germany. His research interests involve low-power RF frontends for short-range communications and integrated dc/dc converters.

Aytac Atac received the M.S. degree from the Georgia Institute of Technology, Atlanta, GA, USA, in 2009. Since 2014, he has been with E.ON, Potsdam, Germany. Mr. Atac has contributed to organization of IEEE conferences as a secretary and local organizer.

Ralf Wunderlich received the Dipl.-Ing. and Dr.-Ing. degrees from the Technical University Dortmund (TUD), Dortmund, Germany, in 1997 and 2002, respectively. His doctoral research concerned the topic of an integrated CMOS-only Hall sensor system for precision length measurements. In 2002, he joined the Chair of Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany. He is currently involved in the Chair’s research activities and teaching and student concerns. As an Acting Manager, he is responsible for all organizational and professional affairs. He has authored or coauthored over 60 peer-reviewed papers.

Stefan Heinen (M’96–SM’05–F’07) received the Dipl.-Ing. and Dr.-Ing. degrees in electrical engineering, from Duisburg University, Duisburg, Germany, in 1988 and 1992, respectively. After completion of his doctoral degree on noise simulation in nonlinear circuits, he joined the Siemens Semiconductor Group in 1992. He founded and headed the Siemens Semiconductor RF Integrated Circuit (IC) Design Group, Duesseldorf, Germany, which today is a part of the Infineon Technologies Design Center NRW, Duisburg, Germany. His focus has been in the area of short-range wireless and cellular applications, where he has been the technical leader behind many commercial successful products for cordless phones and Bluetooth. In April 2002, he joined the Faculty of Electrical Engineering and Information Technology, RWTH Aachen University, Aachen, Germany, where he holds the Chair of Integrated Analog Circuits and is involved in the UMIC research cluster. His research interests are in the area of analog- and mixed-signal circuit design, as well as RF system design for wireless application. From 2006 to 2007, he was on leave from RWTH Aachen University, during which time he was a Fellow for RF Solutions with Infineon Technologies.

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Design and Characterization of a 3-bit 24-GS/s Flash ADC in 28-nm Low-Power Digital CMOS Gregor Tretter, Mohammad Mahdi Khafaji, David Fritsche, Corrado Carta, Member, IEEE, and Frank Ellinger, Senior Member, IEEE

Abstract—This paper presents the design and characterization of a 24-GS/s 3-bit single-core flash analog-to-digital converter (ADC) in 28-nm low-power digital CMOS. It shows the design study of the track-and-hold circuit and subsequent buffer stage and provides equations for bandwidth calculations without extensive circuit simulations. These results are used to target leading-edge speed performance for a single ADC core. The ADC is capable of achieving its full sampling rate without time interleaving, which makes it the fastest single-core ADC in CMOS reported to date to the best of our knowledge. With a power consumption of 0.4 W and an effective number of bits of 2.2 at 24 GS/s, the ADC achieves a figure of merit of 3.6 pJ per conversion step while occupying an active area of 0.12 mm . Due to its high sampling frequency this ADC can enable ultra-high-speed ADC systems when combined with moderate time interleaving. Index Terms—Analog-to-digital converter (ADC), flash ADC, non-time-interleaved, track-and-hold amplifier (THA) bandwidth, THA buffer.

I. INTRODUCTION

M

ODERN communication systems require data rates up to several tens of Gb/s. One particularly challenging case is the wireless board-to-board communication in supercomputers, where data throughput above 100 Gb/s is needed. Technically this can be achieved with carrier frequencies above 100 GHz, as large bandwidths up to tens of GHz are available in this case [1]. Systems with such large bandwidth are very challenging for the incorporated analog-to-digital converters (ADCs), which can easily become the bottleneck of the wireless link. Additionally, in order to enable systems-on-chip (SOCs) with digital signal processing and ADCs integrated on the same chip, it becomes a requirement for the ADC to be realized in a modern CMOS technology. Recently published CMOS ADCs show good power efficiency at sampling rates in the lower GHz range [2]–[5] with successive approximation register (SAR) ADCs being most popular. It is possible

Manuscript received July 21, 2015; revised December 02, 2015; accepted February 05, 2016. This work was supported by the German Research Foundation under the framework of Collaborative Research Center 912 “Highly Adaptive Energy-Efficient Computing” and by the Excellence Cluster Cool Silicon under the framework of the BMBF project Cool-RF-28. This paper is an expanded version from the IEEE RFIC Symposium, Phoenix, AZ, USA, May 17–19, 2015. The authors are with the Department of Electrical and Computer Engineering, Technische Universität Dresden, 01069 Dresden, Germany (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2529599

to reach higher sampling rates with the same basic circuit structures by applying time interleaving [6]–[8]. As long as the overhead of multi-phase clock generation is negligible, it is theoretically possible to increase the sampling rate with no penalty in terms of required energy per conversion. For this reason time-interleaving topologies are widely used for high-speed ADCs and have been “extensively exploited ( ) to achieve low figures of merit” [9], equivalent to low energy per conversion step in this context. Recently, sampling rates as high as 90 GS/s have been reported with ADC cores running at 1.4 GS/s [10]. Unfortunately it is not possible to use time interleaving at an arbitrary scale, as several problems limit the performance of heavily interleaved systems, such as jitter in multi-phase clock generation and distribution, clock transition times, input capacitance, requirements on the track-and-hold amplifiers (THAs), and latency [9], [11]–[13]. Further increases in sampling rate without exacerbating those problems can be achieved by implementing faster ADC cores. This relaxes the requirements on the multi-phase clock generation and reduces the latency, while enabling highest input bandwidth. The design goal for the presented ADC has been to achieve the highest possible sampling speed with a single ADC core. As a result, the flash ADC topology has been chosen. The presented ADC core is capable of working at sampling rates up to 24 GS/s , while being designed in a low-cost low-power digital CMOS technology. In addition to the topics presented in [14], this paper presents comprehensive design considerations for the analog input stages and gives insights into the circuit implementation of all ADC sub-blocks. Furthermore, it shows additional and more detailed measurement results, statically as well as at highest input frequencies. Section II shows the ADC architecture. As circuit implementations for such high frequencies require comprehensive design considerations, it is important to specify the bandwidth requirements for the critical circuit blocks, especially for the analog input stages. Section III investigates the track-and-hold (T/H) circuit and the subsequent buffer stage and provides a method to directly calculate the required bandwidth without extensive circuit simulations. Insights into the circuit implementation are given in Section IV, while Section V presents the chip characterization. II. ADC ARCHITECTURE Fig. 1 shows the system-level schematic of the presented ADC. For highest conversion speed, it relies on the flash topology. The schematic shows a T/H stage and subsequent buffer at the input, followed by a comparator (Cmp), further amplifiers, and latches (L) in each of the parallel

0018-9480 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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Fig. 1. ADC block diagram.

Fig. 3. Response of a T/H circuit in track mode to a step input, using the lowpass filter model of Fig. 2(b), as described by (1).

Fig. 2. (a) Basic SC T/H circuit. (b) T/H equivalent circuit during track phase.

data-processing paths. The binary output signals are generated by thermometer to binary conversion logic (T2B). By utilizing a modern CMOS process it is possible to achieve sampling rates of tens of GHz with circuit structure sizes in the range of hundreds of m. This requires RF design techniques including electromagnetic (EM) field simulations for lines and structures because the circuit size is no longer negligible. Special care needs to be taken of the bandwidth of the analog frontend consisting of the T/H buffer and the comparators. The time synchronization after the comparators is usually performed by a master–slave flip-flop, which is very challenging to design at frequencies of tens of GHz. In order to reduce the effective regeneration time, three latches and an amplifier have been combined to form a master–slave–master (MSM) flip-flop [15]. III. BANDWIDTH CONSIDERATIONS Circuit operation at highest speed requires careful bandwidth consideration. The input stages consisting of a T/H circuit and subsequent buffer pose the highest requirements because they work in the analog domain where the signals contain time and amplitude information. While it is a common approach to determine the required bandwidth by complex transistor-level simulations, this section presents practical equations based on simple models to directly calculate the target bandwidth. A. T/H Stage The most basic topology of a switched capacitor (SC) T/H circuit is shown in Fig. 2(a). The transistor controls the electrical connection between the input and output of the circuit. While input and output are isolated during the hold phase and the charge on the hold capacitor is preserved, the electrical

connection during the track phase should ideally be a short circuit. In this phase the impedance between input and output depends on the drain–source resistance of , which can be modeled as a resistor . This creates a first-order low-pass filter as a simple model for a SC T/H circuit in track mode, as illustrated in Fig. 2(b). For input frequencies close to the Nyquist frequency it is possible that two consecutive hold voltages are at the minimum and at the maximum of the input signal envelope. In this case the output signal of the T/H stage has to change from the minimum value to the maximum within one tracking period. This scenario can be modeled with a step at the input of the T/H stage with the amplitude , the peak-to-peak value of the T/H input voltage. The corresponding step response converges exponentially towards the input step value with a time constant of , as shown in Fig. 3, (1) At time

, the output of the T/H reaches . As we are interested in the change of the output voltage within one track period, we define as the duration of one track period, which is half of a sampling period : . The T/H deviation should be less or equal to half of a least significant bit (LSB) of the ADC, (2) represents the number of bits of the ADC. The definitions of and together with (1) give the required corner frequency for the T/H stage in track mode

(3) This means that the tracking bandwith for the T/H stage needs to exceed the sampling frequency for resolutions higher than 4 GHz bit. For the presented ADC the sampling rate is and the number of bits is , which results in a required tracking bandwidth of GHz.

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value of the ideal hold plateau just at the end of the hold phase. For all acceptable buffer bandwidths the corresponding signals are approximately parallel to the ideal signal at the beginning of the hold phase ( in Fig. 4), which means they have similar slopes. As long as this approximation holds, the voltage deviation can be understood as the result of a phase difference between the ideal signal and the output signal of the buffer, (4) , which is introduced by the low-pass beThe phase shift havior of the buffer stages, is much smaller than 45 because the buffer corner frequencies are much higher than the maximum signal frequency . can be expressed as Fig. 4. Simulated output waveforms of buffers with different bandwidth, which are fed by an ideal T/H circuit. The T/H input signal frequency is close to the . Low buffer bandwidths compromise the hold Nyquist frequency plateaus of the ideal T/H signal and thus defeat the purpose of the T/H stage.

(5) For small values of

at (6)

B. T/H Buffer Apart from designing the T/H stage it is also important to consider the bandwidth of the subsequent buffer. High bandwidth is difficult to achieve for this buffer because it has to drive all comparators, which create a large capacitive load. On the other hand, this buffer is especially important because if its bandwidth is too low it will substantially decrease the effective ADC resolution, as has been described in [16]. While in other designs this critical point is addressed empirically and only sometimes the resulting bandwidth specifications are given [17], this section describes a method to calculate the bandwidth requirements for the T/H buffer, which can be used for system-level specifications without extensive circuit simulation. The reason for the importance of the buffer are the hold plateaus, which are introduced by the T/H stage. They are formed by higher order harmonics. If the low-pass behavior of the buffer filters those harmonics, the plateaus are proportionally compromised. This effect is shown in Fig. 4, which depicts , the output signal of an ideal T/H stage being filtered by buffer stages, which are modeled as first-order low-pass filters with different corner frequencies . The corner frequencies vary between the Nyquist frequency and four times the Nyquist frequency. Additionally, the response of an ideal filter with infinite bandwidth is shown. The input signal of the ideal T/H stage is a sinusoidal signal of frequency and amplitude . During the track phase, the ideal buffer perfectly follows the output signal of the T/H stage and preserves the sinusoidal signal shape and the amplitude . At the time , the output signal of the ideal buffer changes from the sinusoidal waveform of the track mode to the hold plateau. Depending on the buffer bandwidth , the other signals need a longer time to follow the ideal filter signal. As can be seen in the given example, a buffer bandwidth of is clearly not sufficient because the resulting signal is no longer constant during the hold phase, which defeats the purpose of the T/H stage. The buffer output signal for is on the borderline with the signal reaching the

there is a maximum for

leading to (7) During the hold phase, the input signal of the buffer is constant at a value of and the output signal approaches this constant value exponentially over time, starting at , the beginning of the hold phase. The largest deviation happens if the hold phase starts at so that . In this case,

(8) Since the purpose of the T/H circuit is to keep the output voltage constant during the hold phase it is necessary to define a time after which the signal change for the rest of the hold phase can be neglected. Assuming less than a tenth of an LSB is negligible results in (9) Solving for

yields (10)

Applying (5) to (12) and considering the small-angle approxiand results in a simplified result, mation for both (11) This is shown in Fig. 5 for an input signal frequency of GHz, which is the nyquist frequency at 24-GS/s operation. The resolution is swept between 3–6 bits. To achieve a certain

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Fig. 5. Settling time at the output of the buffer versus buffer bandwidth , GHz, the number calculated using (11). The input signal frequency is of bits varies between 3 and 6.

settling time, higher bandwidth is required for higher resolutions because of the increased settling precision. While increasing the buffer bandwidth in order to reduce the settling time is very efficient as long as the values of are small, this tradeoff becomes more and more inefficient for higher bandwidths. The required bandwidth for the presented 3-bit 24-GS/s ADC can also be determined with Fig. 5. Buffer bandwidths below 20 GHz result in settling times larger than 20 ps, which are not sufficient for the presented ADC with a hold phase duration of ps. The required settling time depends on the system implementation, but values in the order of half of a hold phase are feasible. This corresponds to values of ps in this case and results in a minimum buffer bandwidth of 38 GHz for the presented ADC. IV. CIRCUIT IMPLEMENTATION A. Basic Considerations The presented ADC has been designed in a 28-nm low-power digital CMOS process, which offers transistors with a breakdown voltage of 1.1 V. The transit frequency and maximum frequency of oscillation of the process are both around 250 GHz for drain–source voltages of 1.1 V and below 200 GHz for operating points with drain–source voltages of 0.6 V. To achieve the highest possible sampling rates, all circuits employ source coupled logic (SCL). SCL circuits are differential and are suited for highest operating frequencies [18]. Moreover, SCL is robust against power-supply switching noise, which CMOS logic creates to a high extent [19]. In order to increase the transistor drain–source bias voltages and improve the device speed, the chip works with two custom supply voltage domains at 1.4 and 1.75 V. Careful SCL design ensures that no transistor exceeds its specified breakdown voltage. The 1.75-V domain is used only for the clock buffer stages that drive the THA so that high gate voltages can be supplied to control the THA. B. T/H Stage The T/H stage of the presented ADC is a differential SC circuit with clock feedthrough cancellation [20] (Fig. 6). The required hold capacitance depends on the sampling rate and

Fig. 6. T/H stage and buffer.

resolution of the ADC. Its size impairs the bandwidth [21], [22], droop, thermal noise [23], and signal coupling. The nodes that is connected to are also loaded by parasitic capacitances in the buffer input and wiring. A conservative approach is to completely implement the required value of with metal–insulator–metal (MIM) capacitors [21], [24], [25]. Alternatively the parasitic capacitances can be considered so that consists of MIM capacitors and parasitics, which reduces the size of the MIM capacitors [26]. Due to the high sampling rates and low resolution of the presented ADC the parasitic capacitances suffice and the approach of [27] is used, which has no physical capacitor implementation for , but relies solely on parasitics. The drain–source resistance of , , defines the electrical connection between the circuit input and the subsequent buffer and thus represents resistor , which has been introduced in the T/H model in Fig. 2(b). The gate–source voltage of , controls , which means for the given circuit implementation that changes with the input voltage, (12) For large input voltages, is decreased and increased, which results in the smallest bandwidth of the T/H circuit. The T/H stage has been designed for a track-mode bandwidth of 30 GHz under this worst case condition, which is still higher than the minimum required bandwidth of GHz according to (3). C. T/H Buffer As derived in Section III-B, a buffer bandwidth of 38 GHz is required to achieve a settling time of ps at the output of the T/H buffer. For additional design margin the implemented buffer has been over-constrained to a bandwidth of GHz, which results in a settling time of ps according to (11). Fig. 7 shows a typical waveform of transistorlevel simulations of the T/H circuit and buffer at the change between the T/H phase. Simulated at an input frequency of

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Fig. 8. Employed comparator circuit. Fig. 7. Simulated transistor-level waveforms at the output of the T/H stage and the subsequent buffer.

GHz and a sampling rate of GS/s it demonstrates the behavior close to the Nyquist frequency. The simulated settling time is 7.7 ps, which fits very well to the calculated value of 8.4 ps. In order to achieve the bandwidth of GHz, two peaking inductors pH have been employed. The 80- feedback resistor is required to increase the static linearity of the buffer stage. A 110-fF capacitor creates an additional pole-zero pair, which helps increasing the bandwidth of the buffer. Since the corner frequency of is above the Nyquist frequency, the buffer benefits from the improved linearity during the hold phases even though shorts the feedback resistor at higher frequencies GHz

(13)

D. Comparators and Offset Compensation The flash ADC topology uses a set of comparators to simultaneously compare the input signal to different reference voltages, as shown in the ADC block diagram in Fig. 1. Deviations due to device mismatch in the reference voltage generation, as well as in the comparator circuits, directly create static nonlinearities in the ADC transfer characteristics, which manifest in degradations of the integral nonlinearity (INL) and differential nonlinearity (DNL). Classic flash ADCs make use of resistive voltage divider ladders to create the required reference voltages [13]. Since this leaves no possibility to account for random process mismatch, different approaches have been shown to reduce static nonlinearity by means of adjustable offset compensation. While [28] adds a calibration circuit to a resistive reference ladder to generate the required voltages, [12], [17], [29] use on-chip DACs for reference voltage generation and offset compensation and [30] goes even one step further by integrating DACs, as well as redundant comparators on chip in order to increase the calibration range. While these approaches can effectively eliminate static nonlinearities, they also require further circuitry and increase the system complexity. The presented ADC requires 14 different reference voltages for the 7 differential comparators, which are needed for 3-bit resolution. By incorporating single-ended to differential conversion circuitry into each comparator, the number of different voltages can be halved to 7. This opens the possibility to create the required ref-

erence voltages off-chip, which gives a simple, yet efficient and versatile method to account for all static nonlinearity problems that can arise. The circuit implementation of the differential comparators is depicted in Fig. 8. The single-ended dc reference voltage is created off-chip and supplied to the chip via a bond-wire interface. Each SCL comparator uses a differential reference signal, which it generates from the single-ended version. The single-ended to differential conversion is shown on the left side of Fig. 8. The differential pair consisting of is degenerated by a 1-k feedback resistor , which leads to a differential output voltage adjustment range of 500 mV for input voltages between 820 mV and 1.18 V for a bias voltage V. The stabilization capacitors are used solely to isolate the differential reference voltage from the input voltages. For this purpose, capacitance values of 500 fF are sufficient, while enabling area-efficient integration of the capacitors into the layout of the comparator cell. In order to protect from ripples on the supply voltage or on the single-ended reference voltage , a separate dc voltage distribution network that employs zero-ohm lines is used. This design aspect is described in Section IV-H. E. Latches The circuit implementation of the latches is shown in Fig. 9. control the behavior during the While the transistors latch phase, are responsible for the regenerative recovery phase, which is achieved by cross-coupled feedback between both transistors. serve as buffers and level shifters for the clock signal . The bias voltage can be used to adjust the gain of the buffers. F. Clock Generation Supplying analog circuit blocks with clock signals at highest speeds is a very challenging task [16]. The ADC relies on two clock signals at full sampling rate, one for the latches and one for the T/H circuit. The structure for both clock generation circuits is the same. They consist of an active balun and two gain stages, all designed in SCL with inductive peaking for bandwidth optimization. A dc voltage distribution network based on zero-ohm lines is used to avoid crosstalk via the supply voltage between clock and data processing circuitry in the ADC core. G. Thermometer to Binary Conversion Logic The last circuit block in the signal path before the output buffers is the thermometer to binary conversion logic, which

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Fig. 9. Employed latch.

Fig. 11. ADC core area. Massive metal walls are used to guarantee the required metal density.

Fig. 10. Thermometer to binary conversion logic.

generates the full-speed binary output signals. It is based on the structure proposed in [31], which requires NAND and OR logic gates only and can prevent simple bubble errors. The logic gates have been designed in the SCL topology. Buffer stages with delay times close to those of the NAND and OR gates have been added so that the delay of the conversion logic is the same for all output bits. The resulting block diagram is shown in Fig. 10. H. DC Voltage Distribution DC voltage distribution is an important aspect of the design of integrated circuits at frequencies in the GHz range. It is closely connected to the circuit layout because the utilized decoupling capacitors oftentimes occupy significant portions of the chip area. The decoupling capacitors are required to stabilize on-chip dc voltages, which are supplied from external sources by bondwire interfaces. The goal is to have clean dc voltages without any high-frequency components in form of spikes or ripples. Furthermore, crosstalk between different circuits via the supply voltage domain is to be prevented. Both aspects can be met with large decoupling capacitors, which short high-frequency signals to ground. The problem in practical realizations is that any capacitor forms a resonance frequency together with a series inductance and no decoupling or stabilization takes place at this frequency. The inductance can, for example, originate from the bond-wire interface. Large capacitors can easily move the resonance frequency into regions, which are important for circuit operation. The possible consequences range from increased crosstalk to unintended circuit operation such as oscillation. A different dc voltage distribution method is the use of zero-ohm lines [32]. Metal–oxide–metal (MOM) capacitors are formed to the shape of a transmission line with very low wave impedance.

Fig. 12. Measurement setup.

Those structures offer high attenuation of high-frequency signals, which makes them fulfill the same purpose as decoupling capacitors. They can be modeled with the help of EM field solvers and simulated with transmission line models to predict the expected behavior. They are not susceptible to resonance with single series inductances. Furthermore, implementing the dc connections of different circuit blocks with zero-ohm lines offers a well-defined isolation between those blocks to prevent crosstalk. The zero-ohm line approach has been used for all externally supplied dc voltages including supply voltages and reference voltages. Special care has been taken to prevent crosstalk to the different reference voltages of the comparators and to isolate the dc voltages of the clock circuitry from the data-processing hardware. I. Layout Considerations Design rules in heavily scaled CMOS processes pose further restrictions on RF designs. One critical factor is the required metal density, which is 20% for tiles of 50 m 50 m area in the given technology. One way to prevent metal filling structures within critical RF structures such as transmission lines, inductors, or RF gain stages is to reduce the size of those components below 50 m and encompass them with metal filling structures. As a result, the maximum size of inductors used is 35 m. The circuit blocks in the ADC core area are surrounded by massive metal “walls” to fulfill the density requirements without increasing parasitic capacitances inside the circuit blocks due to metallic filling structures (Fig. 11).

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Fig. 13. Measured static transfer characteristics with and without dc offset compensation.

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Fig. 15. Chip photograph.

Fig. 16. Measured FFT of the ADC output for a 9.1-GHz input signal sampled at 24 GS/s.

signal frequency for this test setup. The two clock signals are created from one signal source in combination with a power divider and two phase shifters, which guarantees maximum measurement accuracy and flexibility. The output signals are captured with a real time oscilloscope (RTO) (Agilent DSA-X 96204Q), which offers four channels with 33-GHz input bandwidth so that the single-ended output of all bits can be evaluated simultaneously. B. Experimental Results

Fig. 14. Simulated and measured SNDR at different sampling rates. (a) 20GS/s. (b) 24 GS/s.

V. MEASUREMENTS A. Measurement Setup The presented ADC has been characterized with a hybrid measurement setup, which makes use of wire bonding and on-chip probing, as shown in Fig. 12. While all RF input and output signals have been connected using probes, the dc supply and control voltages have been generated on a dc printed circuit board (PCB) and have been supplied to the chip by a bond-wire interface to a daughter PCB. An off-chip balun has been used to generate the differential input signal from a single-ended source. Its bandwidth of 10 GHz limits the maximum input

The static behavior of the presented ADC is shown in Fig. 13. The target differential peak-to-peak input voltage amplitude is 800 mV. Without offset compensation for the dc reference voltages, large deviations from the ideal static transfer function are visible. The corresponding DNL of 0.8 has a sizeable impact on the overall circuit performance. To account for this, automatic script-driven offset compensation at circuit startup has been used. A control script running on a dedicated PC can access the ADC input signals, the RTO at the output, as well as the dc board to automatically determine and apply the compensation coefficients for the dc reference voltages. This leads to a reduction of the DNL below 0.05, which represents almost perfect static behavior. To describe the dynamic ADC performance, the measured signal-to-noise-and-distortion ratio (SNDR) is plotted in Fig. 14 for sampling rates of 20 and 24 GS/s in comparison to the simulated values. The measurements have been taken for normal circuit operation, as well as for a transparent THA

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TABLE I PERFORMANCE COMPARISON TO STATE-OF-THE-ART ADCs ABOVE 10 GS/s

stage, which means the THA clock signal is constantly high. For each data point the signal source power has been adjusted to compensate for the frequency behavior of the input balun, which at the highest frequencies is not sufficiently matched to 50 . At 20 GS/s, simulation predicts SNDR values close to the theoretical maximum of 20 dB for a 3-bit ADC. The measurements show slightly higher distortion resulting in a degradation of the SNDR to a minimum of 17 dB. Within measurement accuracy, both THA test scenarios show similar results. At 24 GS/s, both simulated and measured SNDR values decrease at high input signal frequencies. Furthermore, the difference between simulation and measurement is slightly increased in comparison to the 20-GS/s scenario. The minimum measured SNDR is 15 dB for both THA test cases, which corresponds to an effective number of bits (ENOB) of 2.2, as reported in [14] for the same hardware. Even though there is no visible advantage of the enabled THA circuit, the presence of a functional THA paves the way for moderate time interleaving with the same chip, which can enable an essential improvement in overall sampling speed. Fig. 16 shows the fast Fourier transform (FFT) of the ADC output of a 9.1-GHz signal, which is sampled at 24 GS/s. The chip photograph in Fig. 15 shows the hybrid setup. The size of the inductorless flash core is 0.06 mm . Due to the clock buffers, which make use of inductors, the overall active area increases to 0.12 mm . The complete die area is 2.4 mm . Table I compares the performance of the presented ADC to the state-of-the-art in ADCs above 10 GS/s. The table is split into two groups, considering CMOS ADC implementations and ADCs in SiGe semiconductor technologies featuring bipolar devices. While the SiGe circuits achieve highest single-core sampling rates , they suffer from high power consumption and have the distinct disadvantage that they cannot be integrated on a single chip together with large-scale digital circuits. For the CMOS ADCs, especially the implementations that rely heavily on time interleaving and make use of high-performance or SOI CMOS processes achieve good tradeoffs between performance and power, which manifests in low numbers for the Walden figure of merit (FOM) [12]. Since the presented ADC does not employ time interleaving, the single-core sampling rate is higher than that of interleaved implementations with comparable sampling rates. It is the highest single-core sampling rate in CMOS to the best of our knowledge and has been implemented in a low-power low-cost CMOS technology. In order to compare the

Fig. 17. Comparison of state-of-the-art of ADC designs based on their singlein (14). core performance as defined by

state-of-the-art of ADC designs based on their single-core performance, a FOM is required, which states the core performance without the impact of time interleaving. The FOM of a single core is better than that of the complete interleaved ADC system due to the additional power consumption in the interleaving circuitry. Based on the numbers given in [10], an overhead of 25% in terms of power consumption is assumed for all time-interleaved ADC systems, for interleaved ADCs for non-interleaved ADCs. (14) Fig. 17 shows the single-core performance comparison. It illustrates the high sampling rate and yet good FOM of the presented ADC core. The presented ADC can enable ultra-high sampling frequencies if combined with moderate time interleaving while preserving very low latency. To compare the dimensions of the delay between input and output, two-cycle conversions have been assumed for all listed ADCs. The resulting latency is shown in Table I and is superior for the presented ADC. VI. CONCLUSION A 3-bit single-core flash ADC in LP digital CMOS has been presented, achieving sampling rates up to 24 GS/s without time interleaving. This is the result of a design that aims at the highest possible sampling rate for a single ADC core. In order to achieve this goal, the bandwidth requirements for the ADC input stages have been investigated and evaluated in the form of simple math equations for efficient circuit implementation. Featuring the highest single-core sampling rate reported in

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CMOS up to now, the presented ADC enables communications with high data throughput and yet low latency and paves the way for ultra-high sampling rates by applying moderate time interleaving. ACKNOWLEDGMENT The authors thank Agilent Technologies for the assistance with high-speed real-time measurements. REFERENCES [1] D. Fritsche, C. Carta, and F. Ellinger, “A broadband 200 GHz amplifier with 17 dB gain and 18 mW DC power consumption 0.13 m SiGe BiCMOS,” IEEE Microw. Wireless Compon. Lett., vol. 24, no. 11, pp. 790–792, Nov. 2014. [2] L. Kull et al., “A 3.1 mW 8 b 1.2 GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 3049–3058, Dec. 2013. [3] C.-H. Chan, Y. Zhu, S.-W. Sin, S.-P. U, R. Martins, and F. Maloberti, capacitive-folding flash ADC in 65 nm “A 5 bit 1.25 GS/s 4 CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 9, pp. 2154–2169, Sep. 2013. [4] P. Harpe, B. Busze, K. Philips, and H. de Groot, “A 0.47–1.6 mW 5 bit 0.5–1 GS/s time-interleaved SAR ADC for low-power UWB radios,” IEEE J. Solid-State Circuits, vol. 47, no. 7, pp. 1594–1602, Jul. 2012. [5] B. Verbruggen, J. Craninckx, M. Kuijk, P. Wambacq, and G. V. der Plas, “A 2.6 mW 6 b 2.2 GS/s 4-times interleaved fully dynamic pipelined ADC in 40 nm digital CMOS,” in Int. Solid-State Circuits Conf., 2010, pp. 296–297. [6] L. Kull et al., “A 35 mW 8 b 8.8 GS/s SAR ADC with low-power capacitive reference buffers in 32 nm Digital SOI CMOS,” in VLSI Circuits Symp., 2013, pp. 260–261. [7] E. Tabasy, A. Shafik, K. Lee, S. Hoyos, and S. Palermo, “A 6 b 10 GS/s TI-SAR ADC with embedded 2-tap FFE/1-tap DFE in 65 nm CMOS,” in VLSI Circuits Symp., 2013, pp. 274–275. [8] J. Wu et al., “A 5.4 GS/s 12 b 500 mW pipeline ADC in 28 nm CMOS,” in VLSI Circuits Symp., 2013, pp. 92–93. [9] B. Razavi, “Design considerations for interleaved ADCs,” IEEE J. Solid-State Circuits, vol. 48, no. 8, pp. 1806–1817, Aug. 2013. [10] L. Kull et al., “A 90 GS/s 8 b 667 mW 64 interleaved SAR ADC in 32 nm digital SOI CMOS,” in Int. Solid-State Circuits Conf., 2014, pp. 378–379. [11] M. Chu, P. Jacob, J.-W. Kim, M. LeRoy, R. Kraft, and J. McDonald, “A 40 Gs/s time interleaved ADC using SiGe BiCMOS technology,” IEEE J. Solid-State Circuits, vol. 45, no. 2, pp. 380–390, Feb. 2010. [12] M. El-Chammas and B. Murmann, “A 12 GS/s 81 mW 5 bit time-interleaved flash ADC with background timing skew calibration,” IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 838–847, Apr. 2011. [13] B. Razavi, Principles of Data Conversion System Design. New York, NY, USA: Wiley, 1994. [14] G. Tretter, M. Khafaji, D. Fritsche, C. Carta, and F. Ellinger, “A 24 GS/s single-core flash ADC with 3 Bit resolution in 28 nm low-power digital CMOS,” in IEEE Radio Freq. Integr. Circuits Symp., May 2015, pp. 347–350. [15] W. Cheng et al., “A 3 b 40 GS/s ADC–DAC in 0.12 m SiGe,” in Int. Solid-State Circuits Conf., 2004, pp. 262–263. [16] S. Shahramian, S. Voinigescu, and A. Carusone, “A 35 GS/s, 4 Bit flash ADC with active data and clock distribution trees,” IEEE J. Solid-State Circuits, vol. 44, no. 6, pp. 1709–1720, Jun. 2009. [17] A. Varzaghani et al., “A 10.3 GS/s, 6 Bit flash ADC for 10G ethernet applications,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 3038–3048, Dec. 2013. [18] P. Heydari and R. Mohanavelu, “Design of ultrahigh-speed low-voltage CMOS CML buffers and latches,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 10, pp. 1081–1093, Oct. 2004. [19] M. Alioto and G. Palumbo, “Design strategies for source coupled logic gates,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 50, no. 5, pp. 640–654, May 2003. [20] G. Tretter, D. Fritsche, C. Carta, and F. Ellinger, “10 GS/s track and hold circuit in 28 nm CMOS,” in Int. Dresden–Grenoble Semicond. Conf., 2013, pp. 1–4.

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[21] D. Mattos et al., “An 8 Gsps, 65 nm CMOS wideband track-and-hold,” in Int. New Circuits Syst. Conf., 2011, pp. 321–324. [22] G. Tretter, D. Fritsche, C. Carta, and F. Ellinger, “Enhancing the input bandwidth of CMOS track and hold amplifiers,” in Int. Microw., Radar, Wireless Commun. Conf., 2014, pp. 1–4. [23] B. Sedighi, A. Huynh, and E. Skafidas, “A CMOS track-and-hold circuit with beyond 30 GHz input bandwidth,” in IEEE Int. Electron., Circuits. Syst. Conf., 2012, pp. 113–116. [24] D. Cascella, F. Cannone, G. Avitabile, and G. Coviello, “A 2.5 GS/s 62 dB THD SiGe track-and-hold amplifier with feedthrough cancellation technique,” in IEEE Int. Electron., Circuits, Syst. Conf., 2012, pp. 109–112. [25] X. Li, W.-M. L. Kuo, Y. Lu, R. Krithivasan, J. Cressler, and A. Joseph, “A 5 bit, 18 GS/sec SiGe HBT track-and-hold amplifier,” in Compound Semicond. Integr. Circuit Symp., 2005. [26] S. Shahramian, S. Voinigescu, and A. Carusone, “A 30 GS/sec track and hold amplifier in 0.13 m CMOS technology,” in IEEE Custom Integr. Circuits Conf., 2006, pp. 493–496. [27] H.-L. Chen, S.-C. Cheng, and B.-W. Chen, “A 5 GS/s 46 dBc SFDR track and hold amplifier,” in Int. Intell. Signal Process. Commun. Syst. Symp., 2012, pp. 636–639. [28] D. Ferenci, M. Groezing, F. Lang, and M. Berroth, “A 3 bit 20 GS/s flash ADC in 65 nm low power CMOS technology,” in IEEE Eur. Microw. Integr. Circuits Conf., 2010, pp. 214–217. [29] J. Lee and Y.-K. Chen, “A 50 GS/s 5 b ADC in 0.18 m SiGe BiCMOS,” in IEEE MTT-S Int. Microw. Symp. Dig., 2010, pp. 900–903. [30] S. Park, Y. Palaskas, and M. Flynn, “A 4 GS/s 4 bit flash ADC in 0.18 m CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 1865–1872, Sep. 2007. [31] Y.-J. Chuang, H.-H. Ou, and B.-D. Liu, “A novel bubble tolerant thermometer-to-binary encoder for flash A/D converter,” in Int. VLSI Design, Automat., Test Symp., 2005, pp. 315–318. [32] G. Tretter, D. Fritsche, C. Carta, and F. Ellinger, “Zero-ohm transmission lines for millimeter-wave circuits in 28 nm digital CMOS,” Electron. Lett., vol. 51, no. 11, pp. 845–847, 2015. [33] P. Ritter, S. Le Tual, B. Allard, and M. Möller, “Design considerations for a 6 bit 20 GS/s SiGe BiCMOS flash ADC without track-and-hold,” IEEE J. Solid-State Circuits, vol. 49, no. 9, pp. 1886–1894, Sep. 2014. [34] R. Kertis et al., “A 20 GS/s 5-bit SiGe BiCMOS dual-nyquist flash ADC with sampling capability up to 35 GS/s featuring offset corrected exclusive-or comparators,” IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2295–2311, Sep. 2009. [35] H.-C. Hong, Y.-S. Chen, and W.-C. Fang, “14 GSps four-bit noninterleaved data converter pair in 90 nm CMOS with built-in eye diagram testability,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, pp. 1238–1247, Oct. 2013. [36] D. Ferenci, S. Mauch, M. Grözing, F. Lang, and M. Berroth, “A 3 bit 36 GS/s flash ADC in 65 nm low power CMOS technology,” in Int. Integr. Circuits Symp., 2011, pp. 344–347. Gregor Tretter was born in Schweinfurt, Germany, in 1986. He received the Diploma degree in electrical engineering from the Technische Universität Dresden (TUD), Dresden, Germany in 2011, and is currently working toward the Ph.D. degree at TUD. His research interests lie in the area of integrated analog circuit design where he is focused on broadband circuit design in general and data converter structures in particular.

Mahdi Khafaji was born in Tehran, Iran, in 1982. He received the Ph.D. degree (with highest honors) from the Dresden University of Technology, Dresden, Germany, in 2015. From 2008 to 2012, he was with IHP Microelectronics, Frankfurt (Oder), Germany, where he was involved with high-speed digital-to-analog converters. He is currently with the Chair for Circuit Design and Network Theory, Technische Universität Dresden (TUD), Dresden, Germany. His research interests include high-speed data converters and broadband circuits for optical communication.

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David Fritsche was born in Bautzen, Germany, in 1986. He received the Diploma degree in electrical engineering from the Technische Universität Dresden (TUD), Dresden, Germany in 2011, and is currently working toward the Ph.D. degree at TUD. His main research interests are in the field of analog circuit design with a current focus on circuits in advanced semiconductor technologies and for operation at sub-terahertz frequencies.

Corrado Carta (S’02–M’05) was born in Cagliari, Italy. He received the Master degree in electrical engineering from the University of Cagliari, Cagliari, Italy, in 2000, and the Ph.D. degree from the Swiss Federal Institute of Technology (ETH) Zürich, Zürich, Switzerland, in 2006. From July 2000 to February 2006, he was with the Microwave Electronics Group, ETH Zürich, where his main research interests were in the field of silicon-based RF integrated circuit (RFIC) design for microwave wireless communications. From April 2006 to May 2008, he was with the High-Speed Electronics Group, Electrical and Computer Engineering Department, University of California at Santa Barbara, Santa Barbara, CA, USA, where his research was focused on the design of silicon-based integrated circuits for very large millimeter-wave phased arrays. In June 2008, he joined Sonos, Inc., where he led the RF engineering and compliance team and was involved in the development and characterization of the wireless interface of new and existing products. In March 2010, he joined the Chair for Circuit Design and Network Theory, Technische Universität Dresden

(TUD), Dresden, Germany, where he currently leads the mm-wave Integrated Circuit (IC) Design Group and the Beyond-Moore Electronics Group.

Frank Ellinger (S’97–M’01–SM’06) was born in Friedrichshafen, Germany, in 1972. He received the Diploma degree in electrical engineering from the University of Ulm, Ulm, Germany, in 1996, and the MBA and Ph.D. degree in electrical engineering and Habilitation degree in high-frequency circuit design from ETH Zürich (ETHZ), Zürich, Switzerland, in 2001 and 2004, respectively. Since 2006, he has been a Full Professor and Head of the Chair for Circuit Design and Network Theory, Technische Universität Dresden (TUD), Dreseden, Germany. From 2001 to 2006, he was Head of the RFIC Design Group, Electronics Laboratory, ETHZ, and a Project Leader of the IBM/ETHZ Competence Center for Advanced Silicon Electronics, hosted at IBM Research, Rüschlikon, Switzerland. He has been the Coordinator of the RESOLUTION, MIMAX, ADDAPT, and FLEXIBILITY projects funded by the European Union. He coordinates the cluster project FAST with more than 70 partners (most of them from industry) and the Priority Program FFlexCom of the German Research Foundation (DFG). He has authored or coauthored over 350 refereed scientific papers. He authored the lecture book Radio Frequency Integrated Circuits and Technologies (Springer, 2008). Prof. Ellinger has been a Member of the Management Board of the German Excellence Cluster Cool Silicon. He was an elected IEEE Microwave Theory and Techniques Society (MTT-S) Distinguished Microwave Lecturer (2009–2011). He was the recipient of several awards including the IEEE Outstanding Young Engineer Award, the ETH Medal, the Denzler Award, the Rohde&Schwarz/Agilent/GerotronEEEf-COM Innovation Award (twice), and the ETHZ Young Ph.D. Award.

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Modal Theory for Waveguides With Anisotropic Surface Impedance Boundaries Nathalie Raveu, Benedikt Byrne, Ludovic Claudepierre, and Nicolas Capet

Abstract—The modal theory for propagation in structures with constant anisotropic surface impedances as a boundary condition is developed for cylindrical waveguides and rectangular waveguides with vertical anisotropic surfaces. Dispersion diagrams for these waveguides are computed for various sets of surface impedances. The results are then validated by comparison, using commercial software. These results confirm a number of interesting properties of such waveguides with anisotropic surface impedances: the cutoff frequency can be drastically lowered, and left-handed mode propagation in a given frequency band can be obtained. The development of this theory can open the door to the development of new design tools for various applications using guided structures such as small waveguides, filters, positive phase shifters, or horns with excellent radiation properties. Index Terms—Anisotropic surface impedances, lower fundamental cutoff frequency, metamaterials, modal theory, waveguides.

I. INTRODUCTION

P

ROPAGATION of the waves in guided sections has been studied in depth for many years [1]–[4], and the knowledge thus gained, through modal analysis, has resulted in the development of efficient commercial software that can analyze and synthesize horns, filters, orthomode transducers, and septum polarizers [5], [6]. These mode-matching software applications are now widely used in industry and are well suited to the early and recent synthesis of these various types of equipment because of their relative speed and accuracy. With the arrival of metamaterials, which have now been widely studied for many years [7]–[11], it has become possible to create artificial materials with electromagnetic properties that are not available in natural materials. Designing crystallographic structures whose lattice period is very small compared to the wavelength makes it possible to obtain relative permittivity and/or permeability that is lower than one or negative. It has been demonstrated that both properties can be obtained independently and these materials are classified as double

Manuscript received January 21, 2015; revised April 24, 2015; accepted February 12, 2016. This work was by the CNES and made in collaboration between the CNES and the LAPLACE laboratory. N. Raveu is with the University of Toulouse, INPT, UPS, LAPLACE, ENSEEIHT, Toulouse 31071, France (e-mail: [email protected]). B. Byrne and L. Claudepierre are with the University of Toulouse, INPT, UPS, LAPLACE, ENSEEIHT, Toulouse 31071, France, and also with the Centre National d'Etude Spatiale (CNES), Toulouse 31400, France. N. Capet is with the Centre National d'Etude Spatiale (CNES), Toulouse 31400, France (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2533387

positive (DPS), single negative (SNG), or double negative (DNG) [12]. Other metamaterial structures can be used to create artificial magnetic conductors (AMCs) that exhibit a high surface impedance with a zero phase shift at the reflection interface such as Sievenpiper mushrooms [13]. Recently [14], metamaterial loading of waveguides has allowed changes in propagation characteristics, such as a reduction in cutoff frequency or a reduction in a cross section such as in miniaturized circular-waveguide probes [15]. Moreover, the introduction of metamaterials, with a permittivity lower than one, on the inner wall of horn antennas [16]–[18] permits to achieve hard and soft horns. These horns have excellent radiation properties with a low level of cross polarization on a wide bandwidth. Using such a technique results in the creation of a waveguided structure in which the boundary conditions can be seen as anisotropic surface impedances. In [14], circular waveguides with metamaterial walls are also studied to lower the cutoff frequency, however, results are obtained by homogenization of the metamaterial volume without consideration of the polarization anisotropy of the metamaterial. It has to be mentioned that only a limited number of works have focused their attention on the analytic modal theory in such guided structures with anisotropic walls [19], [20]. Moreover, the aforementioned excellent article of 1978, only studied the first order modes in circular waveguides, probably due to the lack of computation tools available at that time. [19] has the advantage of providing an analytical formulation of modes in cylindrical or rectangular waveguides compared with the Green function solution, which is used in [21]. Some interesting work about anisotropic impedance walls in waveguides is also presented in [22]. Here, the assumption is that there is a small perturbation on the walls, which is compared to the one of the perfect metallic case. The analysis of such an implementation, however, is far from identical to that of waveguides with metamaterial walls. In this paper, we propose to develop the modal theory for propagation in cylindrical as well as rectangular waveguides with anisotropic surface impedances as boundary conditions. In comparison to [19], in which only modes without angular variations are analyzed, the equations are developed here for every kind of mode index. Then, compared with [20], all kinds of boundary values are studied and not only some isotropic cases with only one surface impedance different from zero on each wall. By using this theory, properties of waveguides with anisotropic walls can be quickly analyzed. Even if the used surface impedances are firstly frequency independent, a margin of interesting anisotropic surface impedances can be highlighted. This is the purpose of this paper. Optimized real anisotropic surface impedances may later be achieved within a frequency

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bandwidth to meet the surface impedance range of interest. The complete waveguide structure, including anisotropic frequency dependent walls, may finally be analyzed with the same theory if the dispersive surface impedances are known. The technique may be applied indifferently to artificial soft and hard surfaces [18], graphene sheets [23], or metamaterial walls. A further stage of the work will consist of implementing the obtained modes propagating in different metamaterial waveguide sections into complete horn antennas by using the mode-matching method. As was done in [24], initial studies are already being conducted [25], [26]. Developments of the modal expansion theory were marginally proposed in [27] for the cylindrical case. In this paper, this theory is described in more details and validated by comparison with other numerical techniques. In Sections II and III, the electromagnetic problem is described and hybrid waves are defined for both cylindrical and rectangular waveguides with only a pair of anisotropic boundary conditions. In both cases, the expressions of transversal fields are then given and the dispersion equations obtained. A number of specific cases are investigated more closely. In Section IV, the dispersion properties obtained through the development of a specific code are presented and validated. In our case, all orders are plotted for various cases of anisotropic boundary conditions. Section V contains a conclusion on the potential of using the presented theoretical development. II. MODAL EXPANSION THEORY FOR CYLINDRICAL WAVEGUIDES WITH ANISOTROPIC WALLS In the following, the considered waveguides are invariant along the -axis, therefore, electric and magnetic fields have an dependence, for with the propagation constant along the -axis, which will be omitted in their further expression. Except for the TEM mode, the two Maxwell curl equations are rearranged to express the transverse field components, denoted with the index , in terms of the axial fields, denoted with the index , thanks to

Fig. 1. Cylindrical waveguide with anisotropic walls.

B. Hybrid Modes Definition and

are solutions of the Helmholtz equation (4) (5)

where , is the Bessel function of order , is a positive integer, and and are real constants. To express hybrid modes, coupling coefficients and are introduced. They link and , and therefore longitudinal fields and as (6) exists except for TE modes and except for TM modes. Finally, mode types are directly deduced from or observations. According to (4)–(6), implies a pure TM mode and a pure TE mode; otherwise the mode is hybrid. Considering [19], in the same conditions, therefore, if the hybrid mode is an EH mode, if it is an HE mode. This assumption is true except for the case , where has no significance and which is detailed later in a dedicated part. C. Electromagnetic Fields

(1)

Transversal fields' components are detailed in the cylindrical coordinate system

(2)

(7)

the vacuum permewhere is the waveguide permittivity, ability, and the cutoff propagation constant. In the following, the surface anisotropic impedances are supposed constant for all incident angles of the waves inside the waveguide. In cylindrical coordinates, see Fig. 1, the TEM mode does not exist, since two separated conductors do not exist.

(8)

(10) where is the free space impedance and wavenumber.

A. Boundary Conditions They are expressed at the cylinder limit (radius constant anisotropic surface impedances and :

(9)

) with

(3) and are complex since losses may be included, even if examples in this paper are developed in lossless cases.

is the free space

D. Dispersion Equation Boundary conditions (3) are introduced in (8) to obtain the expression of : (11)

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where . Finally, from (7)—(10), with the boundary conditions (3) and the coupling coefficient (11), the dispersion equation is deduced as follows:

Fig. 2. Rectangular waveguide with vertical anisotropic walls.

(12)

type TM. The global dispersion equation for the product of (18) and (24) as

is given by

E. Specific Case for In this particular case, has no significance and therefore modes cannot be identified with it, hence the dispersion equation has to be verified. Two different cases appear considering (4) and (5). For the first case, and . Only TE modes are obtained, and (7)–(10) become (13)

which corresponds to

(26)

(14)

It is noted that this last equation is strictly identical to (12) with .

(15)

F. Validation for Metallic and Magnetic Waveguides

(16)

The dispersion (12) of a metallic waveguide and a magnetic waveguide becomes

Concerning the boundary conditions (3), is always satisfied with independently of . However equation must be satisfied, which leads to: (17) (18) Equation (17) is simplified in (18), which is independent of as mentioned before. The second solution is obtained for and . Only TM modes are obtained, and (7)–(10) become (19) (20) (21) (22) In this case,

(25)

is always satisfied with independently of . However, the equation must be satisfied, which leads to (23) (24)

Equation (23) is simplified in (24), which also is independent of . Thus, for , the value is not significant for the determination of the mode type: if (18) is satisfied, the mode is of type TE; on the other hand, if (24) is satisfied, the mode is of

in both cases (27)

which corresponds exactly to the definition of the cutoff constants of TE and TM modes in metallic and magnetic waveguides. It validates the expression of the dispersion equation in these two cases. III. MODAL EXPANSION THEORY FOR RECTANGULAR WAVEGUIDES WITH ANISOTROPIC WALLS As in the previous section, (1) and (2) are considered. In the following, a Cartesian coordinate system (see Fig. 2) is considered. In the horizontal planes ( and ), walls are perfect conductors (PEC), while, in the vertical planes ( and ), constant anisotropic surface impedances are considered. Since boundary conditions may be different on the walls along and , the TEM mode may exist (two separated conductors). This mode will be qualified separately at the end of this section. A. Boundary Conditions They are expressed at the waveguide limits ( , , and ) with anisotropic surface impedances at the following. • The anisotropic vertical walls

, and

(28) (29)

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and are complex since losses may be included, even if examples in this paper are developed in lossless cases. • The metallic horizontal walls:

D. Dispersion Equation Field components defined in (38) and (33) are inserted in the boundary (28) to obtain

(30)

(41)

(31) (42) where the operation [

B. Hybrid Modes Definition and

are new solutions of the Helmholtz equation

. A definition of (41)–(42)]

is obtained by setting (43)

(32) (33)

In a same manner, field components defined in (32) and (40) are inserted in boundary (29) to obtain

where is the propagation constant along and is the propagation constant along . Furthermore, and are linked by

(44) (45)

(34) (35) and are imaginary complex constants and and are constants. To express hybrid modes, the coupling coefficients and are introduced to link and , and hence also the longitudinal fields and :

where the operation [

. A definition of (44)–(45)]

is obtained by setting (46)

The expression of and first definition of as

are replaced in (41) to obtain a

(36) As a consequence, exists except for TE modes and except for TM modes. Finally, modes are directly deduced from or observations. According to (32), (33), and (36), implies pure a TM mode and a pure TE mode; otherwise the mode is hybrid. Considering [19], in the same conditions; therefore, if the hybrid mode is an EH mode, if , it is an HE mode [19]. This assumption is true except for , which is detailed later in a dedicated part. C. Electromagnetic Fields

(47) and . The same operawhere tion is done with (42) to obtain a second definition of as (48) By equating the two equations of , the dispersion equation is obtained as

Transversal fields' components are detailed in rectangular coordinates system from (1), (2), (32), and (33) as follows:

(37) (49)

(38) where and (39)

(40)

and

are the normalized impedances, .

,

E. Specific Case for In this particular case, has no significance and therefore modes cannot be identified with it, and the dispersion equation has to be verified. In this case, and and the

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mode is therefore of TE type (or TEM). From (37)–(40), the electromagnetic fields are deduced as follows:

(65)

(51)

This corresponds exactly to the TE and TM modes in a metallic and magnetic/metallic waveguide, since .

(53) As for the cylindrical waveguide, is not relevant for the determination of the mode type. Since , , and , the dispersion equation is independent of . Only the following equation must be satisfied: (54)

G. TEM Mode Particular attention must be paid to the TEM mode, since this mode cannot be qualified with (1)–(2) that are the first equations used to lead the previous theory. If the TEM mode exists, the electric field is deduced from the Poisson equation. Since metallic walls are defined at and , the electric field components are consequently (66)

with (55)

where is a constant. The magnetic field components are deduced from the Maxwell equations as

(56)

(67)

(57) (58) By introducing these equations in (54), we have (59) (60) is deduced as (61) From (60), a second expression of

and can be inserted in (49), which in both cases results in

(50)

(52)

From (59), a first expression of

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is deduced as (62)

Equations (61) and (62) are equated to obtain the dispersion equation (63) By simplifying (63), the dispersion equation for

is finally (64)

in (49) with (since Now, by introducing ), (64) is validated in this particular case. However, is not relevant to qualify the type of mode, but, in this case, from observation of , the mode type can be determined: if the mode is of TEM type, otherwise it is a TE mode. F. Validation for Metallic and Magnetic/Metallic Waveguides The dispersion (49) is validated in the metallic waveguide with and in the magnetic/metallic waveguide with

Within these expressions and the boundary conditions (29), no is always satisfied conditions are imposed on , since for the TEM mode. Since and for the TEM mode, the boundary condition (28) is satisfied only if . As a conclusion, the TEM mode exists only if . The TEM mode is characterized by and . IV. RESULTS From the waveguide modal expansion theory presented in the previous part, a specific code that can compute the dispersion properties of waveguides with constant anisotropic surface impedance as boundary conditions has been developed. In this part, we present a summary of the results obtained for both cylindrical and rectangular waveguide cases. In this summary, the dispersion diagrams illustrate the effective permittivity as a function of the , with the cylinder radius or the rectangular waveguide width. Three approaches have been used to validate the results obtained for a number of specific values of surface impedances. For PEC boundary conditions , the results obtained are compared with the well-known analytical solutions. Furthermore, a validation of the dispersion curves is obtained by using two commercial solvers for electromagnetic structures: ANSYS High Frequency Structure Simulator (HFSS) and the RF module of COMSOL Multiphysics. The latter has been used for anisotropic surfaces on cylindrical waveguides, since HFSS is not able to use anisotropic impedance values on curved surfaces. For the validation with HFSS, dispersion diagrams have been obtained from a section of a given waveguide using periodic boundary conditions, as shown in Fig. 3. For a given propagation constant, which is a function of the phase delay between two periodic boundary conditions and the distance between them, the eigenmode solver of HFSS returns the frequency of each solution. By varying the phase delay between the two periodic boundary conditions from 0 to 180 ,

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Fig. 3. Cylindrical and rectangular representation of waveguides with periodic boundary conditions and anisotropic surface impedances simulated in HFSS.

Fig. 5. Relative error of surface impedances as function of incidence angles. Fig. 4. Waveguide used in COMSOL for modal analysis.

the complete dispersion diagram of the guided structure can be obtained. For some values of surface impedances, computing the dispersion diagram of the first modes can take up to several hours using this technique. The validation with COMSOL has only been used for anisotropic cylindrical cases, that can not be validated with HFSS. A 2-D modal analysis has been achieved in the waveguide presented in Fig. 4. The inner cylinder of radius is the one to qualify. The anisotropic boundary condition is achieved by inserting another cylinder of radius of variable relative permeability and bordered by a perfectly metallic condition. The permeability is calculated to approximate the required surface impedance at under normal incidence, assuming that small variations are obtained under other incidence since is chosen very small. Under normal incidence the surface impedance seen from the interface is defined by (68) where is the media impedance, is the relative permeability of the media, is the relative permittivity of the media, and is the propagation constant in this media. For a thin distance , may be considered very small, and therefore a first-order development of the term is used. Moreover, the incidence on the surface can be considered close to the normal one (thin layer), and consequently (69) (70) By changing at each frequency point of simulation, the required surface impedance is achieved at , and the propagation constant is determined under COMSOL with a modal analysis. According to the permeability definition, is ruled by while is ruled by and .

To demonstrate and, at the same time, clarify this approach with the help of an example, let us consider the case and , for which the dispersion diagram is illustrated in Fig. 6. More precisely, let us have a look at the dispersion point at , which corresponds to one of the lowest values of the relative permeability of the mode. A study of the surface impedances is achieved with an HFSS Floquet mode analysis. These surface impedances and are obtained from the diffraction of the magnetic layer surrounding a perfect conducting plane at the height 100 m under several incidences. As can be seen in Fig. 5, the relative error of TE and TM surface impedances increases, as expected, with the angle of incidence. The relative error is defined by the absolute difference between the exact surface impedance obtained at each incidence angle and the surface impedance at normal incidence divided by the exact surface impedance. However, since the layer is thin, these errors remain lower than 0.002% and 2% for TE and TM surface impedances, respectively. This analysis justifies the hypothesis of normal incidence angle to evaluate the relative permeability value and leads to a surface impedance value that is not so far from the expected one whatever the incidence angle. In Fig. 6, the dispersion diagrams obtained with our code for a cylindrical waveguide of radius 30 mm are illustrated for various anisotropic surface impedances (blue dots). For isotropic surface impedances, the dispersion diagrams obtained analytically (red stars) or using the HFSS Eigenmode solver (black circles) are superposed. Given that with HFSS it is not possible to use anisotropic surface impedances on cylindrical waveguides, the RF module of COMSOL is used with 100 m and the results (green triangles) are added to the ones obtained with the code. Here, the mesh is choosen extremely fine. First, we can notice excellent agreement between our results and the ones calculated by the other three methods. The slight discrepency between the code and the validation with COMSOL for the anisotropic cases is probably due to the fact that the magnetic layer is not infinitely thin. The thinner this domain is, the closer the results become. However, the mesh

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Fig. 6. Dispersion diagrams of a cylindrical waveguide for various anisotropic surface impedances . The curves illustrated with blue dots are obtained with the code, curves with black circles and green triangles are obtained with HFSS and COMSOL, respectively, and the curves represented by red stars are the analytical dispersion curves.

generated by COMSOL is easier to manipulate than the one in HFSS with the driven modal solver, therefore, COMSOL has been used in these anisotropic cases. It can also be seen that, in some specific cases, such as , the cutoff frequency of the first mode is divided by 2.23 compared with the cutoff frequency of the classical first mode of the metallic waveguide. It can also be observed that areas of combinations of surface impedances, such as the area with and , result in dispersion diagrams with cutoff frequencies of the fundamental mode much lower than the one of the equivalent metallic waveguide, by maintaining a large single-mode bandwidth. To lower the cutoff frequency and keep a large single-mode bandwidth, the metamaterial surface impedances should therefore be in these ranges within the frequency band of interest. The propagation of modes below the fundamental mode cutoff frequency of the metallic waveguide has already been shown in [14] for a thin metamaterial liner with a particular permittivity and is confirmed here for specific surface impedances. The analytical method also makes it possible to use negative surface impedances, which could reveal other interesting properties. In Fig. 7, such an example is shown. The combination on the wall of a waveguide with the

Fig. 7. Dispersion diagram of cylindrical waveguide with negative isotropic , obtained with the code (blue surface impedances dots) and validated by HFSS (black circles).

same dimensions as in Fig. 6 has been calculated by the code and superposed with HFSS results. The result is the same as for the positive equivalent, i.e., , which is in accordance with the definition of dual modes in [19]. Thus the cutoff frequency of the fundamental mode is likewise reduced by the factor 2.23 compared with the metallic waveguide.

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Fig. 8. Dispersion diagrams of rectangular waveguide for various anisotropic surface impedances , the curves illustrated with blue dots are obtained with the code, curves with black circles are obtained with HFSS and the curves represented by red stars are the analytical dispersion curves.

In Fig. 8, the dispersion diagrams obtained with our code for a rectangular waveguide with the dimensions 22.86 mm and 10.16 mm are illustrated for various anisotropic surface impedances on the vertical walls (blue dots). The dispersion diagrams obtained analytically (red stars) or using the HFSS eigenmode solver (black circles) are superposed. Compared to Fig. 6, it is possible in this case to validate all of the chosen surface impedance pairs, including the anisotropic ones, with HFSS. Here again, we can notice excellent agreement between our results and the ones obtained with the other two methods. It can also be seen that, in some specific cases, for example , the first mode cutoff frequency is divided by 1.99 compared with classical first mode cutoff frequency of the metallic waveguide. Here again, a large area of combinations of surface impedances can be easily found to reduce the cutoff frequency of the fundamental mode without shortening the single-mode bandwidth: and . To lower the cutoff frequency and keep a large single-mode bandwidth, the metamaterial surface impedances of rectangular waveguide should therefore be in these mentioned ranges within the frequency band of interest. As for the cylindrical case, an example of dispersion diagram of a rectangular waveguide with negative surface impedances and the same dimensions as in Fig. 8 is given in Fig. 9. The

Fig. 9. Dispersion diagram of a rectangular waveguide with negative isotropic on the vertical walls, obtained surface impedances with the code (blue dots) and validated by HFSS (black circles).

combination is calculated by the code and superposed with HFSS results. It can be seen that the fundamental mode is a left-handed one. For information, backward-wave propagation by left-handed modes has already been observed in the Clarricoats–Waldron

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waveguides presented in [28] and [29]; however, compared with the lined waveguides of this paper, the Clarricoats–Waldron waveguides are filled with a dielectric core. For both rectangular and circular waveguides with anisotropic surface impedances, it can be concluded from the obtained results that choosing a particular set of surface impedances makes it possible to reduce the cutoff frequency of the fundamental mode, but also that left-handed mode propagation can be obtained for the conception of positive phase shifters as well as for CLRH transmission lines [11]. It should be pointed out that these surface impedances have not been optimized in order to find the balanced hybrid condition, as has been suggested in literature on anisotropic surfaces in horn antennas [16], [17]. In any case, Figs. 6 and 8 emphasize that the required surface impedances in relation to the desired performances can be obtained by means of the modal theory. Using the expressions given in this article, the field repartition of the modes in the waveguide can be computed. The anisotropic surface impedances can thus be optimized to obtain the desired electromagnetic field repartition of a mode in order to design high-efficiency horns. V. CONCLUSION In this paper, the modal theory for propagation in structures with constant anisotropic surface impedances as boundary conditions has been developed for cylindrical waveguides and rectangular waveguides with vertical anisotropic surfaces. Based on these theoretical developments, dispersion diagrams have been computed for waveguides with various sets of surface impedances and . These results have been validated by comparing results obtained with well-known analytical expressions of the classical metallic waveguide and results obtained with HFSS and COMSOL. It should be noted, incidentally, that at present no commercial tool allows the computation of the dispersion properties for waveguides either with negative anisotropic surface impedances or with positive anisotropic surface impedances for cylindrical waveguides. However, this should be possible with the method introduced in this paper. Finally, interesting properties of such waveguides with anisotropic surface impedances have been highlighted: by choosing a particular set of surface impedances, it is possible to drastically reduce the lower cutoff frequency compared to classical waveguides or to obtain left-handed mode propagation in a given frequency range, allowing new kinds of phase shifters in guided sections. Thanks to this study, surface impedance ranges that allow particular waveguide properties (e.g., left-handed modes or lower cutoff frequency of fundamental mode) may be highlighted. Metamaterial surface impedances should then be designed along the frequency band of interest to meet these impedance ranges. The surface impedance dispersion is not considered in this paper, the anisotropic impedances are considered frequency independent. The theoretical dispersion equations, presented in this paper, are still verified if the surface impedance dispersion is known. Further work must be achieved to qualify realistic metamaterial waveguides with consideration of these dispersion properties. Subsequently, the waveguide presenting these dispersive metamaterial walls should fit the required specifications. Such waveguides may then be analyzed

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with the same method by replacing and at each frequency with the computed dispersive surface impedances of TE and TM modes obtained with HFSS. The development of this theory can open the door to the design of new guided structures, such as small waveguides, new types of filters, positive phase shifters, and horns with excellent radiation properties. REFERENCES [1] A. Wexler, “Solution of waveguide discontinuities by modal analysis,” IEEE Trans. Microw. Theory Techn., vol. MTT-15, no. 9, pp. 508–517, Sep. 1967. [2] W. J. English, “The circular waveguide step-discontinuity mode transducer,” IEEE Trans. Microw. Theory Techn., vol. MTT-21, no. 10, pp. 633–636, Oct. 1973. [3] G. L. James, “On the problem of applying mode-matching techniques in analyzing conical waveguide discontinuities,” IEEE Trans. Microw. Theory Techn., vol. MTT-31, no. 9, pp. 718–723, Sep. 1983. [4] H. Aubert and H. Baudrand, “L'électromagnétisme par les schémas équivalents,” in 2004 Cépaduès-éditions (in French). [5] R. Beyer and U. Rosenberg, “CAD of magic tee with interior stepped post for high performance designs,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 8-13, 2003, vol. 2, pp. 1207–1210. [6] F. Arndt, “WASP-NET: Recent advances in fast full 3D EM CAD of waveguide feeds and aperture antennas,” in Proc. IEEE Int. Symp. Antennas Propag., Jul. 3-8, 2011, pp. 2724–2727. [7] V. G. Veselago, “The electrodynamics of substances with simultaneously negative values of and ,” Sov. Phys. Usp., vol. 10, no. 4, pp. 509–514, 1968. [8] D. R. Smith, W. J. Padilla, D. C. Vier, S. C. Nemat-Nasser, and S. Schultz, “Composite medium with simultaneously negative permeability and permittivity,” Phys. Rev. Lett., vol. 84, no. 18, pp. 4184–4187, May 2000. [9] R. W. Ziolkowski and E. Heyman, “Wave propagation in media having negative permittivity and permeability,” Phys. Rev. E, vol. 64, no. 5, , pp. 1–15, 2001, Art. ID 056625. [10] R. A. Shelby, D. R. Smith, and S. Schultz, “Experimental verification of a negative index of refraction,” Sci., vol. 292, no. 5514, pp. 77–79, 2001. [11] C. Caloz and T. Itoh, Electromagnetic Metamaterials. New York, NY, USA: Wiley-IEEE Press, 2005. [12] A. Alu and N. Engheta, “Guided modes in a waveguide filled with a pair of single-negative (SNG), double-negative (DNG), and/or doublepositive (DPS) layers,” IEEE Trans. Microw. Theory Techn., vol. 52, no. 1, pp. 199–210, Jan. 2004. [13] D. Sievenpiper, L. Zhang, F. Romulo, J. Broas, N. G. Alexopolous, and E. Yablonovitch, “High impedance electromagnetic surfaces with a forbidden frequency band,” IEEE Trans. Microw. Theory Techn., vol. 47, no. 11, pp. 2059–2074, Nov. 1999. [14] J. G. Pollock and A. K. Iyer, “Below-cutoff propagation in metamaterial-lined circular waveguides,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 9, pp. 3169–3178, Sep. 2013. [15] J. G. Pollock and A. K. Iyer, “Miniaturized circular-waveguide probe antennas using metamatial liners,” IEEE Trans. Antennas Propag., vol. 63, no. 1, pp. 428–433, Jan. 2015. [16] E. Lier, “Review of soft and hard horn antennas, including metamaterial-based hybrid-mode horns,” IEEE Antennas Propagat. Mag., vol. 52, no. 2, pp. 31–39, Apr. 2010. [17] E. Lier and R. K. Shaw, “Design and simulation of metamaterial-based hybrid-mode horn antennas,” Electron. Lett., vol. 44, no. 25, pp. 1444–1445, Dec. 2008. [18] P. S. Kildal, “Artificially soft and hard surfaces in electromagnetics and their application to antenna design,” in Proc. 23rd Eur. Microw. Conf., Sep. 1993, pp. 30–33. [19] B. M. Thomas and H. C. Minnett, “Modes of propagation in cylindrical waveguides with anisotropic walls,” Proc. IEE, vol. 125, no. 10, pp. 929–932, Oct. 1978. [20] R. B. Dybdal, L. Peters Jr., and W. H. Peake, “Rectangular waveguides with impedance walls,” IEEE Trans. Microw. Theory Techn., vol. MTT-19, no. 1, pp. 2–9, Jan. 1971. [21] M. G. Andreasen, “Scattering from cylinders with arbitrary surface impedance,” Proc. IEEE, vol. 53, no. 8, pp. 812–817, Aug. 1965. [22] A. E. Karbowiak, “Theory of imperfect waveguides: the effect of wall impedance,” Proc. Inst. Electr. Eng.—Radio Electron. Eng., vol. 102, no. 5, pp. 698–708, Sep. 1955.

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[23] G. Lovat, “Equivalent circuit for electromagnetic interaction and transmission through graphene sheets,” IEEE Trans. Electromagn. Compatibil., vol. 54, no. 1, pp. 101–109, Feb. 2012. [24] L. Shafai and J. E. Hansen, “Matrix formulation of corrugated feeds by using impedance boundary conditions,” Electron. Lett., vol. 13, no. 11, pp. 310–311, May 1977. [25] N. Capet, B. Byrne, L. Claudepierre, and N. Raveu, “Metamaterial waveguide with reduced cross section,” in Proc. 7th Eur. Conf. of Antennas Propag., Apr. 8–12, 2013, pp. 2155–2157. [26] B. Byrne, N. Capet, and N. Raveu, “Dispersion properties of corrugated waveguides based on the modal theory,” in Proc. 8th Eur. Conf. Antennas Propag., Apr. 6–11, 2014, pp. 1–3. [27] L. Claudepierre, N. Raveu, and N. Capet, “Modal analysis of anisotropic cylindrical waveguides,” in Proc. Asia–Pacific Microwave Conf., Dec. 2012, pp. 4–7. [28] P. J. B. Clarricoats and R. A. Waldron, “Non-periodic slow-wave and backward-wave structures,” Int. J. Electron., vol. 8, no. 6, pp. 455–458, 1960. [29] A. Salandrino and D. N. Christodoulides, “Negative index Clarricoats–Waldron waveguides for terahertz and far infrared applications,” Opt. Exp., vol. 18, no. 4, pp. 3626–3631, Feb. 2010. Nathalie Raveu received the M.S. degree in electronics and signal processing in 2000 and the Ph.D. degree in 2003. She is a Professor with the National Polytechnic Institute of Toulouse (INPT) and a Research Fellow with the LAPLACE—CNRS (LAboratory of PLAsma and Energy Conversion). Her research topics are oriented toward development of efficient numerical techniques to address innovative microwave circuits. During the last years, she has developed a new method for SICs study, metamaterial horns, and plasma cavity.

Benedikt Byrne was born in Luxembourg, Luxembourg, in 1986. He received the Dipl.-Ing. degree in electronic engineering from the Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany, in 2013. He is currently working toward the Ph.D. degree in electromagnetism and microwaves at the University of Toulouse, Toulouse, France. His research interests are in the areas of metamaterials, electromagnetic wave propagation, and antennas.

Ludovic Claudepierre was born in Conde-sur-l’Escaut, France, in 1990. He received the Engineer degree from Ecole Nationale Superieure d’Electrotechnique, Electronique, Informatique, Hydraulique et Telecommunication, Toulouse, France, in 2012, and the Ph.D. degree in electronic and high-frequency systems from the University of Toulouse, Toulouse, France, in 2015. His research topics are electromagnetic modelling and wind turbine intereferences on VHF systems.

Nicolas Capet received the degree in electronic engineering and hyperfrequencies from the Ecole National d'Aviation Civile (ENAC), Toulouse, France, in 2007, and the Ph.D. degree in electromagnetism and microwaves from Toulouse University, Toulouse, France, in 2010. Since 2010, he has been working with the Telecom Division, Antenna Department, Centre National d'Etude Spatiale (CNES), Toulouse, France. In charge of antennas innovation for future applications, he was part of the project ownership for the antenna developments of ATHENA program and led multiple antenna studies for preparation of future missions. He is in charge of multiple Research and Development and Ph.D. studies for the development of new space technologies. His research interests include metamaterials applied to antennas (electromagnetic bandgap materials, reflectarrays, absorbers, metasurface antennas, metamaterial horns), propagation of waves carrying orbital angular momentum, passive intermodulation products (PIMP), innovative space telecommunication antennas, ground terminals for satellite on the move (SOTM) applications, and GNSS antennas and antennas' technological developments for competitiveness.

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A Novel

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-TEM Mixed-Mode Converter

Shengren Peng, Chengwei Yuan, Ting Shu, Xuelong Zhao, and Qiang Zhang

Abstract—Overmoded relativistic backward wave oscillators cannot preserve output mode purity, generating a number of modes in general. Until now, terminations for high power microwave (HPM) devices are only matched to a single operating mode. It is quite difficult to properly radiate a combination of modes using HPM antennas. In this paper, a novel efficient –TEM-mode converter is proposed. With the method of , power dividing and field matching described, a mixture of , and modes generated by an HPM device can be successfully converted into a pure coaxial circular waveguide TEM mode utilizing the outer and inner coaxial waveguide structure with an efficiency of over 99% at the center frequency. Such a mode transition will greatly improve the radiation efficiency of HPM antennas. Index Terms—High power microwave (HPM), Ku-band, mode mixed modes. converter,

I. INTRODUCTION

R

ELATIVISTIC backward wave oscillators (RBWOs) driven by relativistic electron beams are attractive for their high stability in generating gigawatt (GW)-class microwaves [1]–[3]. In order to enhance the factor, scaling the RBWOs to a higher frequency range, such as Ku-band, is a major focus in pushing the technology of RBWOs [4]. Since dimensions of single-mode HPM generators scale with wavelength, such devices will be quite small at Ku-band frequencies. With such small structures and power levels, pulse shortening occurs caused by RF breakdown [5], [6]. To overcome pulse-shortening issues, an overmoded slow wave structure (SWS) may be used to reduce the power density and lengthen the output pulse width [7]–[9]. Unfortunately, overmoded RBWOs often produce other unwanted modes, particularly modes [3], [10], [11]. Since most radiating antennas at the output of HPM generators are designed for a single mode [12]–[16], it is necessary to design a mode converter to transform the mixture of modes produced by the RBWO. The mode purity of coaxial waveguide tapers by using the scattering matrix formulation has been studied [17]. This paper will focus on modes specifically since those modes dominate at the output of most Manuscript received June 18, 2015; revised September 23, 2015 and January 07, 2016; accepted February 20, 2016. Date of publication March 08, 2016; date of current version April 01, 2016.This work was supported in part by the Innovation Fund of the Graduate School of the National University of Defense Technology under Grant B140705 and in part by the National Natural Science Foundation of China under Grant 61401485. (Corresponding author: Shengren Peng.) The authors are with the College of Optoelectric Science and Engineering, National University of Defence Technology, Hunan 410073, China (e-mail: [email protected]; [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2535276

RBWOs. The paper presents a novel -TEM mixed-mode converter, utilizing outer coaxial waveguide (OCWG) and inner coaxial waveguide (ICWG) to achieve mode conversion in short length. This approach is applied to the Ku-band RBWO reported in [10] to convert a mixture , , and modes to a pure TEM mode. This paper is organized as follows. In Section II, the design approach of the -TEM mixed-mode converter is analyzed in detail. In Section III, experimental investigations are utilized to verify the proposed method. Finally, a summary and conclusion are given in Section IV. II. DESIGN OF THE

-TEM MIXED-MODE CONVERTER

As reported in [10], an overmoded klystron-like RBWO operating at 12.3-GHz produced GW-level microwaves with 42% electronic efficiency when the focusing magnetic field was 0.48 T. However, the device produced a combination of , , and modes, as detected at the output port. The power distribution was 27.8% , 69.3% , and 2.9% . It is quite difficult to design an HPM antenna to radiate such a mixture with high radiation and aperture efficiency, and thus the practical use of the RBWO device becomes limited. In previous works [15], [16], we proposed an HPM radial line slot antenna (RLSA), which can be operated at high frequency and high efficiency, while remaining compact and with high power-handling capability. However, this design was limited to the coaxial TEM mode. For the RLSA to function properly with the RBWO, a mixed-mode converter is necessary to transform the , , and modes to a single TEM mode. The principle of operation of the proposed mixed-mode converter consists of two steps, which are: 1) power dividing and 2) field matching. These steps will be presented in detail in Sections II-A–II-C. A. Power Dividing Fig. 1 shows the structure of the prototype -TEM mixed-mode converter. The , , and mixed-mode input is on the left side of the mode converter, as shown in Fig. 1 (Region A). The phase of each mode relative to each other is 0 . In region B, an OCWG is composed of an outer cylinder and inner sleeve. This configuration ensures that only the TEM mode can propagate in this volume, while higher order coaxial modes are attenuated. The input microwaves in the modes are divided into the OCWG propagating the TEM mode, and the sleeve interior ( is cutoff in this region), which propagates the and mode mixture in region B, as shown in Figs. 2 and 3. Further computations could be done with a scattering matching code. In region C, an ICWG is created, which has the sleeve as an outer conductor and an inner conductor on-axis. This region is

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Fig. 3. Scattering parameters of the power dividing in Fig. 2.

Fig. 1. Structure of the novel -TEM mixed-mode converter. (a) Axial view. (b) Longitudinal section of the converter marked in (a).

Fig. 4. Simulated electric field distribution of the power dividing region with total input power of 0.5 W.

B. Field Matching

Fig. 2. Simulated electric field distribution of the power dividing in region B with total input power of 0.5 W.

also designed such that only the TEM mode propagates with the higher order coaxial modes attenuated. The and modes inside the sleeve in region B are therefore transformed into the TEM mode in region C. A slot is placed on the surface of the inner conductor to cancel reflections due to discontinuity between regions B and C. A large-diameter coaxial TEM mode propagates in the OCWG and a small-diameter coaxial TEM mode propagates in the ICWG. This is illustrated by a model simulation created in CST Microwave Studio in Figs. 4 and 5. From these results, the ratio of the amplitude in the OCWG to the one in the ICWG is 3.61, with a phase difference between the two modes of 64.7 . After this power division, the conversion efficiency of the , , and modes to the two TEM modes is over 99% at the center frequency of 12.3 GHz.

For transitioning to a single pure TEM mode in region E, as shown in Fig. 1, it is necessary to combine the inner and outer TEM modes of region C. For high efficiency, this requires that the phases of the two modes are equal at the export in region D, and the radial field amplitudes match the TEM mode in region E. For ensuring the phase condition, plates are inserted symmetrically into the OCWG with the same length. The coaxial waveguide is therefore separated into several sector waveguides (SWGs) in azimuthal regions that are identical. To avoid the generation of reflected higher order modes in the OCWG, the number of the plates should meet the following requirement: (1) where is the cutoff frequency of the coaxial mode and GHz is the operation frequency. For a radius of 40 mm (matching the output radius of the RBWO in [10]), and mm, (1) is satisfied when . The TEM mode in the OCWG is transferred to 12 SWGs, each of which then propagates the SWG mode. Since the phase velocity of the SWG mode in the SWG is different from the TEM mode in the ICWG, the length of plates can then be

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Fig. 6. Simulated electric field distribution of the field matching region with total input power of 0.5 W.

Fig. 7. Phase of the Fig. 5. Scattering parameters of the power dividing region in Fig. 4. (a) Mag. nitude of the scattering parameters. (b) Phase of the

optimized to match phase between waves in the outer and inner regions. For matching the radial field amplitudes of the two TEM modes in region D to the single TEM mode in region E, it is noted that the field, , is proportional to the inverse of the radial distance from the axis (2) where is the radial distance to the axis of the converter. Changing the cross section of the sleeve of the converter in region D of the OCWG and ICWG will change the field intensity along the radial direction. In this manner, the fields of the two TEM modes of the converter can be matched to the TEM mode in region E. This is illustrated using simulations, as shown in Figs. 6 and 7. These results show that the phase of the TEM mode propagating in the OCWG is equal to the one in the ICWG at the output of region D, and the field intensities of the two TEM modes along the radial direction match at the output, following the relation of (2). C. Overall Geometry As an example, we have designed a mixed-mode to TEM-mode converter for the overmoded klystron-like RBWO

at the output of region D in Fig. 6.

reported in [10] using simulations to verify the output of the proposed approach in the previous sections. Given the initial phase differences of each mode as 0 (the initial phase differences between the modes are not mentioned in [10]), the parameters of the converter are as follows: GHz, mm, mm, mm, mm, mm, and . The electromagnetic behavior of the entire structure is simulated by CST Microwave Studio. Fig. 8 shows the simulated electric field distribution at the center frequency, 12.3 GHz. The initial mixture of modes is used as the input at region A. The microwaves are then divided by region B, with two TEM modes propagating in regions C and D. By meeting the field phase and amplitude matching conditions, a pure TEM output mode is realized in region E, as shown in Fig. 8(c). The total length of the converter is less than , where is the center wavelength in free space. The simulated conversion efficiency and reflection of the converter are plotted in Fig. 9. The conversion efficiency is defined as (3) where is the power of the output TEM mode in region E and is the total input power in region A. From these simulations, the conversion efficiency from , , and to the TEM mode is more than 98% in the range from 12.0 to 12.6 GHz. The reflection is also small over that frequency band. The power-handling capability can also be estimated by

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Fig. 10. Experimental structure in longitudinal section.

Fig. 8. Simulated electric field distribution of the converter with total input power of 0.5 W: (a) in the longitudinal section of the whole converter, (b) in the cross section in region C, (c) in the cross section in region E. Fig. 11. Fabricated mode converter.

Fig. 9. Scattering parameters of the whole converter in Fig. 8.

the electric field distribution of the simulated converter. When the simulated converter is fed with 0.5 W at the input, the maximum electric field strength is less than 1030 V/m, as shown in Fig. 8. Generally, the converter will be under a high vacuum state for HPM applications, in which the RF field breakdown threshold is greater than 1.0 MV/cm [18]. According to conservative estimates, we assume the RF electric breakdown strength is about 700 kV /cm in the all-metal structure. This has been confirmed in recent HPM experiments [8], [19]. Therefore, it can be inferred that the maximum input power for this device is GW at GHz. The power capacity of the klystron-like RBWO in [10] is 2 GW. III. EXPERIMENTAL INVESTIGATIONS OF THE CONVERTER The mode converter is verified by measuring the far-field radiation pattern of the mode mixture from the input side of the converter as produced by injecting a pure TEM mode at the output side, as shown in Fig. 10. A TEM-mode adapter is

Fig. 12. Experimental setup. (a) Diagram. (b) Photograph.

used to match impedances between the output port of the mode converter and the coaxial TEM line for the injected signal. Experimentally measuring mode content and phase of a mixture of modes is difficult. Therefore, the far-field radiation patterns are used for qualitative determination of the launched

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Fig. 14. Simulated scattering parameters of the TEM-mode adapter.

Fig. 15. Reflection coefficient at the input port of the TEM-mode adapter.

Fig. 13. Far-field radiation pattern of the output waveguides at 12.3 GHz: (a) connected with output waveguide A (length of 20 mm), (b) connected with output waveguide B (length of 70 mm), and (c) connected with output waveguide C (length of 100 mm).

modes from a waveguide [20]–[24] by comparing with simulated patterns. Experimental investigations are carried out in an anechoic chamber with an antenna test system. The fabricated mode converter is connected with output waveguides of different lengths, as shown in Figs. 11 and 12. The distance between output waveguides and the horn satisfies the far-field condition ( is about 3 m). Fig. 13 illustrates that the measured patterns of the output waveguides fed by the converter’s input port are in good agreement with the simulated patterns of the output waveguides excited by the proper mode mixtures.

This indicates that the input port of the mode converter launches nearly the same mode mixture as the output mode content of the RBWO described in [10], the power percentage of which is 27.8%, 69.3%, and 2.9%, respectively. And the relative phase of the mode content is 0 . The reflections of the experimental setups shown in Fig. 10 are plotted in Figs. 14 and 15, high transmission efficiency of TEM mode for the TEM-mode adapter is observed, and as the reflected TEM mode at the input port of the TEM-mode adapter is less than 22 dB at the center frequency of 12.3 GHz, we conclude that the mode conversion efficiency of the TEM mode to the mixture is greater than 99%, which retroactively verify the mode converter transforms the mixed modes to pure TEM mode with quite high efficiency. Furthermore, for general applicability, we can also modify the design if the composition of the input , , and modes and their relative phase differences are changed. First, changing the distance between the imports of cylinder and sleeve or the radius of the import of sleeve in region B can change the ratio of the amplitude of TEM mode in the OCWG to the one in the ICWG. Second, modifying the length of plates in region C could tune the phase difference between the two TEM modes. Finally, changing the cross section of the sleeve of the converter in region D of the OCWG and ICWG will

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change the field intensity along the radial direction to realized field matching. IV. CONCLUSION By using a simple method of power dividing and field matching, we can design a high conversion efficiency -TEM mixed-mode converter. Simulations of a converter for an overmoded klystron-like RBWO [10] show high conversion efficiency. The simulations are further verified experimentally by looking at the radiation pattern of the mode mixtures resulting from feeding a TEM mode on the output side of the device. As simulated and demonstrated experimentally, the device can be used to transform the mixture output from an RBWO to a single TEM mode. A simple antenna can then be designed for radiating this propagating TEM mode. This mode converter will therefore greatly enhance the performance and expand the utility of the RBWO device. ACKNOWLEDGMENT The authors would like to express their gratitude to the anonymous reviewers of this paper for their valuable comments.

[15] C. W. Yuan et al., “Designs and experiments of a novel radial line slot antenna for high-power microwave application,” IEEE Trans. Antennas Propag., vol. 61, no. 10, pp. 4940–4946, Oct. 2013. [16] S. R. Peng, C. W. Yuan, and T. Shu, “Analysis of a high power microwave radial line slot antenna,” Rev. Sci. Instrum., vol. 84, pp. 074701–074701-7, 2013. [17] O. Hoechtl, “ Numerical analysis of mode conversion in coaxial waveguide components [R],” Kernforschungszentrum Karlsruhe GmbH , Karlsruhe, Germany, Projekt Kernfusion, 1994O. Hoechtl, “Numerical analysis of mode conversion in coaxial waveguide components,” Ph.D. dissertation, DEPT. OF ???, NAME OF UNIVERSITY, CITY, STATE/COUNTRY, 1994, kfk-5298. [18] J. B. Robert and S. Edl, High-Power Microwave Sources and Technologies. Piscataway, NJ, USA: IEEE Press, 2001. [19] Y. W. Fan et al., “Recent progress of the improved magnetically insulated transmission line oscillator,” Rev. Sci. Instrum., vol. 79, no. 3, pp. 034703–034703-4, 2008. (Gaussian[20] J. L. Doane, “Mode converters for generating the in a circular waveguide,” Int. J. Electron., vol. like) mode from 53, no. 6, pp. 573–585, 1982. [21] R. J. Vernon et al., “Mode content determination in over-mode circular waveguides by open-end radiation pattern measurement,” Antennas Propag. Soc. Int Symp., vol. 25, pp. 222–225, 1987. mode converter,” IEEE Mi[22] C. W. Yuan et al., “A novel TEMcrow. Wireless Compon. Lett., vol. 15, no. 8, pp. 513–515, Aug. 2005. [23] Q. Zhang, C. W. Yuan, and L. Liu, “T-junction waveguide-based combining high power microwave beams,” Phys. Plasmas, vol. 18, no. 8, pp. 083110–083110-4, 2011. [24] D. P. Wu et al., “Mode composition analysis on experimental results of a gigawatt-class Ka-band overmoded Cerenkov oscillator,” Phys. Plasmas, vol. 21, pp. 073105–073105-5, 2014.

REFERENCES [1] Y. Choyal and K. P. Maheshwari, “Excitation of electromagnetic waves in a relativistic backward wave oscillator with end reflectors,” Phys. Plasmas, vol. 2, no. 1, pp. 319–324, 1995. [2] X. J. Ge et al., “An L-band coaxial relativistic backward wave oscillator with mechanical frequency tenability,” Appl. Phys. Lett., vol. 97, no. 10, pp. 101503–101503-3, 2010. mode from a [3] H. Zhang et al., “Gigawatt-class radiation of ku-band overmoded cerenkov-type high-power microwave generator,” IEEE Trans. Plasma Sci., vol. 42, no. 6, pp. 1567–1572, Apr. 2014. [4] J. Benford, J. Swegle, and E. Schamiloglu, High Power Microwaves, 2nd ed. New York, NY, USA: CRC Press, 2007. [5] K. Hahn, M. I. Fuks, and E. Schamiloglu, “Initial studies of a longpulse relativistic backward-wave oscillator utilizing a disk cathode,” IEEE Trans. Plasma Sci., vol. 30, no. 3, pp. 1112–1119, Jun. 2002. [6] S. D. Korovin et al., “Pulsewidth limitation in the relativistic backward wave oscillator,” IEEE Trans. Plasma Sci., vol. 28, no. 3, pp. 485–495, Jun. 2000. [7] J. Zhang, H. H. Zhong, and L. Luo, “A novel overmoded slow-wave high-power microwave (HPM) generator,” IEEE Trans. Plasma Sci., vol. 32, no. 6, pp. 2236–2242, Dec. 2004. [8] J. Zhang et al., “Recent advance in long-pulse HPM sources with repetitive operation in S-, C-, and X-bands,” IEEE Trans. Plasma Sci., vol. 39, no. 6, pp. 1438–1445, Apr. 2011. [9] D. Zhang et al., “Analysis of the mode composition of an X-band overmoded O-type cerenkov high-power microwave oscillator,” Phys. Plasmas, vol. 19, pp. 103102–103102-8, 2012. [10] R. Z. Xiao et al., “A high-efficiency overmoded klystron-like relativistic backward wave oscillator with low guiding magnetic field,” Phys. Plasmas, vol. 19, pp. 093102–093102-5, 2012. [11] X. Z. Li et al., “Analysis of electromagnetic modes excited in overmoded structure terahertz source,” Phys. Plasmas, vol. 20, pp. 083105–083105-6, 2013. [12] C. M. Knop and L. F. Libelo, “Achievement of pencil-beam rradiation mode circular waveguide source,” IEEE Trans. Antennas from a Propag., vol. 42, no. 8, pp. 1188–1192, Aug. 1994. [13] C. C. Courtney, “Design and numerical simulation of coaxial beamrotating antenna lens,” Electron. Lett., vol. 38, no. 11, pp. 496–498, 2002. [14] X. Q. Li et al., “A GW level high-power radial line helical array antenna,” IEEE Trans. Antennas Propag., vol. 56, no. 9, pp. 2943–2948, Sep. 2008.

Shengren Peng was born in Guangxi, China, in June 1987. He received the B.E. degree in physical electronics from the South China University of Technology, Guangzhou, China, in 2010, and the M.S. degree in physical electronics from the National University of Defence Technology, Changsha, China, in 2012. He is currently with the College of Optoelectric Science and Engineering, National University of Defence Technology. His current research interests include antenna and microwave mode conversion.

Chengwei Yuan was born in Henan, China, in May 1974. He received the B.E. degree in applied physics, M.S. degree in optoelectronics engineering, and Ph.D. degree in physical electronics from the National University of Defence Technology, Changsha, China, in 1997, 2002, and 2006, respectively. He is currently with the College of Optoelectric Science and Engineering, National University of Defence Technology. His current research interests include antenna and microwave components.

Ting Shu was born in Jiangxi, China, in September 1965. He received the M.S. and Ph.D. degrees in optoelectric engineering from the National University of Defence Technology, Changsha, China, in 1989 and 1998, respectively. Since 1998, he has been with the National University of Defence Technology, where he was with the Department of Applied Physics, and is currently a Professor with the College of Optoelectric Science and Engineering. His current research interests include high-power microwaves and high-power microwave radiation measurement.

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Xuelong Zhao received the Master’s degree in physical electronics from the National University of Defense Technology, Changsha, China, in 2012, and is currently working toward the Ph.D. degree at the College of Optoelectronic Science and Engineering, National University of Defense Technology. His current research interests include antenna and microwave mode conversion.

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Qiang Zhang was born in Henan, China, in August 1984. He received the B.E. degree in optoelectronics engineering, and M.S. degree and Ph.D. degree in physical electronics from the National University of Defense Technology, Changsha, China, in 2006, 2008, and 2012, respectively. He is currently with the College of Optoelectronic Science and Engineering, National University of Defense Technology. His current research interests include antenna and microwave components.

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1

A Novel to Mode Converter Designed With Radially Loaded Dielectric Slabs Ashish Chittora, Graduate Student Member, IEEE, Sandeep Singh, Archana Sharma, and Jayanta Mukherjee, Senior Member, IEEE

Abstract—A novel linear shaped to mode converter having high efficiency and wide bandwidth is proposed. The design consists of a circular waveguide sectored by a horizontal metallic plate partition, and dielectric slabs radially attached in the lower semicircular waveguide. The mode converter is designed and simulated at an operating frequency of 3 GHz. A maximum bandwidth of 504 MHz (2.81–3.35 GHz) with conversion efficiency greater than 90% is achieved when three Polytetrafluoroethylene (PTFE/Teflon) slabs are placed radially in the mode converter. The mode convertor was fabricated and experiments were performed with PTFE as the dielectric slab material. The mode conversion was verified by measuring the far-field radiation pattern. The proposed mode converter is symmetric, compact, linear, and easy to fabricate. It can be used for S-band high-power microwave applications where wide bandwidth of mode conversion is required. Index Terms—Dielectric materials, high-power microwaves (HPMs), mode converters, mode transducers, waveguide mode matching.

I. INTRODUCTION

H

IGH-POWER microwave (HPM) sources emit axially symmetric modes (TEM or ) as output, and cannot radiate the microwave power along the axis. Direct radiation of mode through horn antenna results in a minimum along the propagation axis (or boresight) at far-field distance. For efficient radiation there should be a maximum along the axis, hence it is necessary to convert the mode to mode before being launched into the free space. A mode converter is the device used for this purpose. Serpentine shaped mode converter designs (symmetric [1]–[5] and asymmetric [6]–[8]) have been extensively reported in the literature, but linearly shaped designs are more convenient in terms of compactness and ease of fabrication. Bandwidth of mode conversion is also an important factor due to the instability in the frequency of operation of the HPM sources [9]. A tapered baffle at the center of a linear Manuscript received May 16, 2015; revised August 11, 2015 and January 08, 2016; accepted February 13, 2016. This work was supported by the Board of Research in Nuclear Sciences (BRNS), Board of Research in Nuclear Sciences (DAE), Department of Science and Technology (DST), Indian Space Research Organisation (ISRO), and Tata Center, Indian Institute of Technology (IIT) Bombay. A. Chittora and J. Mukherjee are with the Department of Electrical Engineering, Indian Institute of Technology Bombay, Powai, Mumbai 400076, India (e-mail: [email protected]). S. Singh and A. Sharma are with the Accelerator and Pulse Power Division (APPD), Bhabha Atomic Research Centre (BARC), Mumbai 400085, India. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2536031

profile waveguide is reported in [10] for the mode conversion. There are no clearly defined intermediate modes in these mode converters. In addition to the dual-bend mode converters, many linear shaped mode converters [11]–[13], [20] are reported and they employ intermediate modes (e.g., TEM, , and sectoral) for to mode conversion. In recent literature [13]–[21], a different approach, based on 180 phase shift in half of the mode pattern, is reported for mode conversion. Metallic plates of different lengths are loaded in [13]–[16] to provide the phase shift for – (circularly polarized) mode conversion. A dielectric lens at the end of a horn is employed in [17] and [18] for the mode conversion and gives (circularly polarized) as the output mode. A metallic photonic crystal loading is used in one half of the waveguide for the mode conversion [19]. A cross-shaped mode converter is reported in [20], which employs rectangular waveguide sections of different path lengths around the center conductor to convert the modes. The output is a circularly polarized mode. Uniform loading of the dielectric in the lower part of the coaxial section of waveguide for mode conversion is also reported in [21]. The mode converter proposed in this paper is a novel and compact solution for HPM applications (designed at 3 GHz), which require a linear profiled mode converter for compactness and wide bandwidth of mode conversion. In Section II, design and configuration of the proposed mode converter is explained along with the principle of operation. In Section III, simulation and experimental results are presented in detail. II. DESIGN AND CONFIGURATION The mode pattern of the mode consists of a radially diverging electric field ( ) from the waveguide axis towards the wall. A phase shift of 180 in one half section of the mode pattern with respect to the other half section, results in a -like mode pattern [13], [21]. The dielectric slab loading is an effective way to provide the phase shift in a waveguide [22], [23]. A similar concept of dielectric slab or septum loading for phase shift is also reported in [24] and [25] to design a circular waveguide (CWG) polarizer. A CWG is partitioned with a metallic plate into two halves or semicircular waveguides (SWGs). Placing the dielectric slab in one SWG section (in our case, the lower one) with the slab plane parallel to the radial electric field ( ) will result in strong perturbation in the propagation constant ( ) of the lower SWG. On the other hand, there is no change in the propagation constant ( ) of the upper SWG, as there is no dielectric loading in the upper half. Let the length traveled by the wave in upper and lower SWGs be

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Fig. 3. Configuration of the mode converter from hollow and dielectric slab (symmetrically) loaded waveguide sections. Fig. 1. Design of the proposed mode converter with three dielectric slabs: (a) front view, (b) side view, and (c) process of mode conversion.

Fig. 2. Propagation of

-field through the mode converter.

and , respectively. If the length ( ) of the dielectric slabs is chosen such that 180 phase shift is provided in the lower SWG with respect to the upper SWG, then the electric field lines will meet in phase at the end of the metallic partition (or SWG section). The output will be a like mode of the CWG, as shown in Figs. 1(c) and 2. If the lower SWG is loaded with symmetrically placed dielectric slabs of dielectric constant , then the length of the mode converter section (or dielectric slabs) can be calculated using the following relation: (1) mode is divided by metallic partiThe input CWGtion into two halves and enters into upper and lower SWGs as out-of-phase SWGmodes. Dielectric slabs of length ( ), calculated from (1), in the lower SWG provides the necessary phase shift of 180 for mode conversion. Since the lower SWG is inhomogeneously filled with the dielectric, the propagating wave does not retain its pure TE character and takes the form of a hybrid mode. The hollow SWGmode is one half of the pattern of the hollow CWGmode, and the propagation constant of the two modes are equal [26]. With the increase in the number of slabs in the lower SWG, the effective dielectric constant and the propagation constant ( ) of the lower SWG also increases and, therefore, the length ( ) calculated from (1) decreases. This effect and corresponding results are discussed in Section III. III. SIMULATIONS AND EXPERIMENTAL RESULTS The parameters that affect the performance of the proposed mode converter are the number, length, thickness, mutual orien-

tation (angle ), and material of the dielectric slabs. The mode conversion efficiency (defined as ), bandwidth, reflection at input port, and power-handling capability are the measures of performance of the mode converter. The proposed mode converter is designed and simulated in CST Microwave Studio at the operating frequency of 3 GHz. Diameter of the CWG is taken as 9 cm so that only the first two modes ( and ) can propagate through the waveguide and the next higher modes are attenuated [27]. A metal plate of thickness 0.2 cm is inserted horizontally to divide the CWG into two SWGs, as shown in Fig. 1. Dielectric slabs of PTFE/Teflon ( ), each of thickness cm, are placed radially in the lower SWG. Due to the mathematical difficulties in obtaining an exact theoretical solution of the proposed design, the propagation constant of the dielectric slab loaded lower SWG is calculated at 3 GHz using the time-domain solver of CST Microwave Studio. With an increasing number of slabs, the fraction of dielectric in the lower SWG increases, which results in smaller length of the mode converter according to (1). The corresponding length ( ) of the slabs is calculated using (1) and simulations are performed for the mode converter design. A. Effect of the Number of Dielectric Slabs A dielectric slab in a waveguide introduces phase shift in the propagating -field components parallel to the slab plane, as in the case of polarizer design [25]. The mode has an azimuthally symmetric -field equally distributed in the azimuth direction. The dielectric slab loaded in the lower SWG in the proposed mode converter can be considered as the one half taken from a CWG symmetrically ( ) loaded with -dielectric slabs, as shown in Fig. 3. The propagation constant of the slab loaded waveguide is higher than the hollow waveguide. Using (1), the appropriate length of the slab loaded waveguide section can be calculated to design the mode converter. The effect of the number of slabs in the lower half of the mode converter is presented in Table I and Fig. 4. In the final design, the number of slabs is chosen taking into consideration the mode conversion bandwidth, maximum efficiency, compactness, dielectric losses, and ease of fabrication. Maximum mode conversion efficiency (98.9%) and bandwidth (2.81–3.35 GHz) is observed with three slabs (and angle

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TABLE I EFFECT OF THE NUMBER OF SLABS ON MODE CONVERSION BANDWIDTH

Fig. 5. Simulated conversion efficiency of the mode converter for as the input excitation signal.

COMPARISON OF

mode

TABLE II – MODE CONVERTERS

Fig. 4. Effect of the number of dielectric slabs on the simulated mode conversion efficiency.

60 between them) in the lower half of the mode converter, therefore triple slab loading is used in the fabricated design of the mode converter. The corresponding simulated insertion loss is below 0.5 dB in the operating bandwidth. B. Simulation and Experiment With Triple PTFE-Slabs Loading PTFE/Teflon is chosen as the slab material with angle between the consecutive slabs ( ). Propagation constants are calculated at 3 GHz separately for the hollow and slab loaded SWGs as rad m and rad m, respectively. Using these values in (1), the longitudinal length of dielectric slabs is calculated to be cm. The conversion efficiencies from the input mode to different modes for the optimized mode converter are shown in Fig. 5. It is observed that efficiency of transmission of the mode and conversion to the mode are less than 0.02% and 0.01%, respectively, in 2.81–3.35-GHz band. Thus, there is little possibility that the mode will be generated at the output. On the other hand, the mode may be excited at the input side and contaminate or transmit through the mode converter. Therefore, for the mode converter to work properly, the input mode should be a pure mode. The monotonic decline after the discontinuity (at 3.24 GHz) in the – conversion efficiency is due to the increase in conversion and transmission to and modes, respectively. The size (length and diameter) and bandwidth of the proposed mode converter is compared with the reported work in the literature and summarized in Table II. The first reference (Lee et

al. [3]) in Table I is a dual bent waveguide mode converter and others are linear profile CWG mode converters. The mode converter with optimized design parameters is fabricated with PTFE as the slab material, as shown in Fig. 6. Metallic parts of the mode converter are made of aluminium for light weight, low cost, and ease of fabrication. Low-power experiments are performed by exciting the input port with a mode signal. To excite a narrowband mode signal, a probe is applied at the axis of the waveguide input port [28]. In our case, the mode excitation is needed over a wide bandwidth (2.5–4 GHz). The mode is generated for wide bandwidth by extending the center conductor of a coaxial line as a monocone [29], [30], as shown in Fig. 7(a). The simulated and measured S-parameters for the mode feed are shown in Fig. 7(b). The mode feed is applied at the input port of the fabricated mode converter to measure the reflection coefficient. The corresponding simulated and measured results are shown in

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Fig. 6. Fabricated mode converter and radiation pattern measurement setup.

Fig. 9. Radiation pattern: (a) without mode converter section and (b) with mode mode at the frequency of 3 GHz. converter section for input

Fig. 7. (a) Monocone (with inverted cone on top) feed designed for mode excitation and (b) corresponding simulated and measured S-parameters.

The mode conversion is verified by measuring and plotting the far-field radiation pattern [2]. First the mode feed is applied at the input of a hollow waveguide with a horn antenna and the radiation pattern is measured in an anechoic chamber. The measured radiation pattern has a minimum below 20 dB at the center, as shown in Fig. 9(a). The mode feed is then applied at the axis of the mode converter with a horn connected at the output, as shown in Fig. 6. The simulated and measured radiation patterns are shown in Fig. 9(b). A maximum is observed at the center of the radiation pattern, therefore it is verified that the input mode signal is successfully converted to the mode at the output aperture of the mode converter. C. Power-Handling Capability and Dielectric Losses

Fig. 8. Reflection coefficient at the input port of the mode converter.

Fig. 8. Both the simulated and measured reflection coefficients are below 10 dB over 2.80–3.38-GHz bandwidth.

Power-handling capability is calculated by exciting a megawatt-level microwave signal at the input port of the mode converter. If dry air at 1-atm pressure is used as a medium, maximum electric field inside the mode converter is 93 kV/cm on a metal surface and 20 kV/cm on a dielectric (PTFE) surface for the 100-MW input signal. These field values are within the breakdown limits of air and dielectric (PTFE), respectively [31]–[33]. Therefore, the proposed mode converter can be used in HPM systems [34]–[37], which require power-handling capability up to 100-MW peak power. In order to improve the breakdown strength, an medium can be used in the waveguide. This analysis is also performed and shown in Fig. 10. A maximum electric field of 195 kV/cm

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wide bandwidth with a comparatively compact-linear structure is essential. REFERENCES

Fig. 10. Simulated electric field inside the mode converter with in place of air and the corresponding color map.

medium

on the metal surface and 88 kV/cm on the dielectric surface is observed for 300-MW input power. The observed fields are smaller than the breakdown limits for the air and dielectric [31]–[33]. Therefore, using instead of air as the medium in the mode converter increases the power-handling capability by almost three times. Other materials with high dielectric strength can also be used for the slab to improve the power-handling capability, while taking care of the tradeoff between bandwidth, breakdown strength, and compactness. Dielectric loss is also an important factor to consider while using the dielectric in the waveguide as loading. These losses can vary with the frequency of operation, material type, dielectric constant, loss tangent, filling fraction, shape, and size. The advantages with dielectric loading are compactness and increased bandwidth [38]. Analysis of dielectric losses in a waveguide is reported in [39]. The loss tangent decreases as the frequency of operation is reduced. The loss tangent of PTFE (0.0002) is relatively smaller than other materials, e.g., Nylon (0.0027) and quartz (0.0004) for the frequency range of operation. The calculated attenuation factor is below 0.01 dB/cm due to the dielectric loading (assuming uniform PTFE loading). The dielectric losses are already taken into account in the simulated results (Figs. 4 and 5) for the mode converter. In the mode converter, dielectric loading is in the form of slabs and exists only in the lower SWG. The total length of the dielectric material ( cm) is also small, total dielectric losses will also be small and within an acceptable limit. Therefore, PTFE is a suitable choice for slab material due to its high power-handling capability and low dielectric losses. IV. CONCLUSION A novel design of a – mode converter with radial loading of dielectric slabs has been proposed in this paper. Analysis is presented for a different number of dielectric slabs for designing the mode converter. With an increase in the number of slabs, longitudinal length of the mode converter decreases. However, an optimum mode conversion efficiency and bandwidth is achieved in simulation when three dielectric slabs are used. The mode converter is fabricated with the loading of three PTFE slabs and experiments are performed to verify the mode conversion and input reflection coefficient. The mode conversion bandwidth is 16.8% at the operating frequency of 3 GHz and power-handling capability is up to 300 MW. The structure has aligned ports, is symmetric, is compact in terms of length (32.48 cm) and diameter (9 cm), and no bend is required in the waveguide. Therefore, it is easy to fabricate. Therefore, the proposed mode converter is useful for the HPM systems, where

[1] W. S. Lee, K. S. Park, B. M. Lee, Y. J. Yoon, J. H. So, and W. Y. Song, – mode converter,” in IEEE Antennas Propag. “X-band Soc. Int. Symp., 2004, vol. 2, pp. 1531–1534. – [2] B. M. Lee, W. S. Lee, Y. J. Yoon, and J. H. So, “X-band mode converter with short length for high power,” Electron. Lett., vol. 40, no. 18, pp. 1126–1127, 2004. [3] S. H. Lee, B. M. Lee, J. Ahn, Y. J. Yoon, and J. H. So, “The design – mode converter with of X-band non-constant serpentine short length,” in Proc. Asia–Pacific Microw. Conf., 2005, vol. 1, pp. 4–7. – [4] C. W. Yuan, H. H. Zhong, and B. L. Qian, “Tri-bend mode converter with input and output aligned on the same axis,” High Power Laser Part. Beams, vol. 18, no. 11, pp. 1864–1868, 2006. [5] Q. Zhang, C. W. Yuan, and L. Liu, “A dual-band coaxial waveguide mode converter for high-power microwave applications,” Chin. Phys. Lett., vol. 28, no. 6, pp. 068401-1–068401-3, 2011. mode genera[6] G. S. Ling and J. J. Zhou, “Converters for the vircator at 4 GHz,” Chin. Phys. Lett., vol. 18, pp. tion from 1285–1285, 2001. [7] G. S. Ling and J. J. Zhou, “Design of mode converters for generating mode from vircator at 4 GHz,” Int. J. Electron., vol. the 89, no. 12, pp. 925–930, 2003. [8] K. S. S. Prasad, S. A. Singh, S. S. Shanmukha, R. Seshadri, and M. V. – circular bend mode converter Kartikeyan, “Design of a operating at 3 GHz,” in IEEE Int. Vacuum Electron. Conf., 2011, pp. 177–178. [9] A. Roy et al., “Oscillation frequency of a reflex-triode virtual cathode oscillator,” IEEE Trans. Electron Devices, vol. 58, no. 2, pp. 553–561, Feb. 2011. [10] A. Chittora, S. Singh, A. Sharma, and J. Mukherjee, “A tapered metallic to mode converter with mode transmisbaffle sion capability,” IEEE Microw. Wireless Compon. Lett., vol. 25, no. 10, pp. 633–635, Oct. 2015. to mode converter,” [11] R. L. Eisenhart, “A novel wideband in IEEE MTT-S Int. Microw. Symp. Dig., 1998, vol. 1, pp. 249–252. [12] A. Tribak, J. Zbitou, A. Mediavilla, and N. A. Touhami, “Ultra-broadband high efficiency mode-converter,” Progr. Electromagn. Res. C, vol. 36, pp. 145–158, 2013. [13] C. W. Yuan, Q. X. Liu, H. H. Zhong, and B. L. Qian, “A novel TEM mode converter,” IEEE Microw. Wireless Compon. Lett., vol. 15, no. 8, pp. 513–515, Aug. 2005. [14] C. W. Yuan, H. H. Zhong, Q. X. Liu, and B. L. Qian, “A novel to Circularly Polarized (CP) mode converter,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 8, pp. 455–457, Aug. 2006. [15] C. W. Yuan, Y. W. Fan, H. H. Zhong, Q. X. Liu, and B. L. Qian, “A novel mode-transducing antenna for high-power microwave application,” IEEE Trans. Antennas Propag., vol. 54, no. 10, pp. 3022–3025, Oct. 2006. – transmission [16] C. W. Yuan and Q. Zhang, “Design of a line for high-power microwave applications,” IEEE Trans. Plasma Sci., vol. 37, no. 10, pp. 1908–1915, Oct. 2009. [17] S. H. Min et al., “Mode conversion of high-power electromagnetic microwave using coaxial-beam rotating antenna in relativistic backward-wave oscillator,” IEEE Trans. Plasma Sci., vol. 38, no. 6, pp. 1391–1397, Jun. 2010. [18] H. C. Jung et al., “Transmission of gigawatt-level microwave using a beam-rotating mode converter in a relativistic backward wave oscillator,” Appl. Phys. Lett., vol. 96, 2010, Art. no. 131502. [19] D. Wang, F. Qin, S. Xu, and M. Shi, “A metallic photonic crystal high power microwave mode converter,” Appl. Phys. Lett., vol. 102, no. 24, pp. 244107–244107-3, 2013. [20] S. Peng, C. Yuan, H. Zhong, and Y. Fan, “Design and experiment of a cross-shaped mode converter for high-power microwave applications,” Rev. Sci. Instrum., vol. 84, no. 12, pp. 124703–124703-6, 2013. [21] A. Chittora, S. Singh, A. Sharma, and J. Mukherjee, “Dielectric loaded to mode converter for S-band applications,” IEEE Trans. Dielectr. Electr. Insul., vol. 22, no. 4, pp. 2057–2063, Aug. 2015. [22] F. Arndt, F. Andreas, W. Manfred, and W. Rainer, “Double dielectric-slab-filled waveguide phase shifter,” IEEE Trans. Microw. Theory Techn., vol. MTT-33, no. 5, pp. 373–381, May 1985.

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[23] F. Arndt, J. Bornemann, and R. Vahldieck, “Design of multisection impedance-matched dielectric-slab filled waveguide phase shifters,” IEEE Trans. Microw. Theory Techn., vol. MTT-32, no. 1, pp. 34–39, Jan. 1984. [24] W. Che and E. K. N. Yung, “90 dielectric polariser in circular waveguide,” Electron. Lett., vol. 36, no. 9, pp. 794–795, 2000. [25] S. W. Wang, C. H. Chien, C. L. Wang, and R. B. Wu, “A circular polarizer designed with a dielectric septum loading,” IEEE Trans. Microw. Theory Techn., vol. 52, no. 7, pp. 1719–1723, Jul. 2004. [26] A. Elsherbeni, D. Kajfez, and S. Zeng, “Circular sectoral waveguides,” IEEE Antennas Propag. Mag., vol. 33, no. 6, pp. 20–27, Dec. 1991. [27] D. M. Pozar, Microwave Engineering, Third ed. New York, NY, USA: Wiley, 2004. [28] R. H. MacPhie, M. Opie, and C. R. Ries, “Input impedance of a coaxial mode,” IEEE line probe feeding a circular waveguide in the Trans. Microw. Theory Techn., vol. 38, no. 3, pp. 334–337, Mar. 1990. [29] S. S. Sandler and R. W. P. King, “Compact conical antennas for wideband coverage,” IEEE Trans. Antennas Propag., vol. 42, no. 3, pp. 436–439, Mar. 1994. [30] J. L. McDonald and D. S. Filipovic, “On the bandwidth of monocone antennas,” IEEE Trans. Antennas Propag., vol. 56, no. 4, pp. 1196–1201, Apr. 2008. [31] R. J. Barker and E. Schamiloglu, High Power Microwave Sources and Technologies. Piscataway, NJ, USA: IEEE Press, 2001. [32] Q. Zhang, S. Peng, C. Yuan, and L. Liu, “Waveguide-based combining S-band high power microwaves,” IET Microw., Antennas, Propag., vol. 8, no. 10, pp. 770–774, 2014. [33] L. K. Warne, R. E. Jorgenson, J. M. Lehr, Z. R. Wallace, and K. C. Hodge, “Surface interactions involved in flashover with high density electronegative gases,” U.S. Dept. Energy, Sandia Nat. Lab., Rep. SAND2010-0268, Jan. 2010. [34] D. M. Goebel, R. W. Schumacher, and R. L. Eisenhart, “Performance and pulse shortening effects in a 200-kV PASOTRON™ HPM source,” IEEE Trans. Plasma Sci., vol. 26, no. 3, pp. 354–365, Jun. 1998. [35] Y. Ziqiang, G. Chengliang, and L. Zheng, “An unmagnetized plasmaloaded relativistic backward-wave oscillator: Experiment and simulation,” Int. J. Infrared Millim. Waves, vol. 21, no. 11, pp. 1887–1896, 2000. [36] D. M. Goebel, J. M. Butler, R. W. Schumacher, J. Santoru, and R. L. Eisenhart, “High-power microwave source based on an unmagnetized backward-wave oscillator,” IEEE Trans. Plasma Sci., vol. 22, no. 5, pp. 547–553, Oct. 1994. [37] J. T. Krile, L. McQuage, G. F. Edmiston, J. Walter, and A. Neuber, “Short-pulse high-power microwave surface flashover at 3 GHz,” IEEE Trans. Plasma Sci., vol. 37, no. 11, pp. 2139–2145, Nov. 2009. [38] W. P. Ayres, P. H. Vartanian, and A. L. Helgesson, “Propagation in dielectric slab loaded rectangular waveguide,” IRE Trans. Microw. Theory Techn., vol. MTT-6, no. 2, pp. 215–222, Feb. 1958. [39] P. J. B. Clarricoats, “Propagation along unbounded and bounded dielectric rods,” Proc. Inst. Elect. Eng., C: Monographs, vol. 108, no. 13, pp. 170–176, 1961. Ashish Chittora (GSM’14) received the B.E. degree in electronics and communication engineering from the Engineering College, Kota, India, in 2009, the M.E. degree in electronics and communication engineering from the Delhi College of Engineering, Delhi, India, in 2011, and is currently working toward the Ph.D. degree at the Indian Institute of Technology Bombay, Mumbai, India. He was an Assistant Professor with Amity University, Noida, India. His research interests include high-power microwave passive devices.

Sandeep Singh received the B.Tech. degree in electronics engineering from the Harcourt Butler Technological Institute (HBTI), Kanpur, India, in 2004, and the M.Tech. degree in RF and microwave engineering from the Indian Institute of Technology (IIT) Kharagpur, Kharagpur, India, in 2012. He is currently a Scientific Officer with the Accelerator and Pulse Power Division (APPD), Bhabha Atomic Research Centre (BARC), Mumbai, India. His research interests include high-power microwave diagnostics, antenna design, electromagnetic interference–electromagnetic compatibility (EMI–EMC), and pulse power systems.

Archana Sharma received the B.E. degree in electrical engineering from the Regional Engineering College, Bhopal, India, in 1987, and the M.Sc. (Engg.) and Ph.D. degrees from the Indian Institute of Science, Bangalore, India, in 1994 and 2003, respectively. She is currently a Senior Scientific Officer with the Accelerator and Pulse Power Division (APPD), Bhabha Atomic Research Centre (BARC), Mumbai, India. Her specialization is in the design and development of single shot and repetitive pulsed electron beam generators based on Marx generator and linear induction accelerators. Her research interest also includes compact pulse power systems for HPM, FXR, and industrial applications.

Jayanta Mukherjee (M’07–SM’13) received the B.Eng. degree in electrical and electronics engineering from the Birla Institute of Technology, Mesra, India, and the M.S. and Ph.D. degrees from The Ohio State University, Columbus, OH, USA. He is currently an Associate Professor with the Department of Electrical Engineering, Indian Institute of Technology, Bombay, India. From 2001 to 2004, he was a Fellow with Texas Instruments Incorporated. From 2002 to 2003, he was an Intern with Thomson Multimedia, Princeton, NJ, USA. He has authored or coauthored more than 50 research papers in peer-reviewed journals and conferences. He also authored three books on RF oscillators and antennas. His research interests include antennas, RF integrated circuit (RFIC) design, and biomedical very large scale integration (VLSI) circuits. Dr. Mukherjee was the recipient of the Gold Medal on the basis of the order of merit from the Birla Institute of Technology.

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A Miniaturized Uniplanar Metamaterial-Based EBG for Parallel-Plate Mode Suppression Stuart Barth, Graduate Student Member, IEEE, and Ashwin K. Iyer, Senior Member, IEEE

Abstract—The suppression of parallel-plate modes is difficult to control over electrically short lengths. The use of electromagnetic bandgap (EBG) technology allows for a large suppression with controllable bandwidth, but traditional EBGs are often too electrically large to be used in practice. Moreover, in some forms they require several metallization layers and/or interconnecting vias. We introduce a metamaterial-based EBG that is miniaturized, uniplanar, and fully printable for the suppression of signals carried by the parallel-plate mode. We also present a corresponding multiconductor transmission-line analysis for accurate modeling of the EBG’s dispersive properties, which arise from the coupling of contradirected forward and backward modes. The theory is supported by full-wave finite-element-method simulations and verified by measurements of a fabricated EBG. To demonstrate the practical value of the metamaterial-based EBG, we propose an alternate implementation that extends the one-dimensional structure to a two-dimensional radial EBG suitable for the suppression of high-frequency parallel-plate noise coupled between adjacent via interconnects. The simulation and measurement results for this device were found to be in agreement with each other and with the predicted bandgap. Index Terms—Backward waves, dispersion engineering, electromagnetic bandgap (EBG) structures, metamaterials, mode suppression, multiconductor transmission-line (MTL) theory, parallel-plate waveguide (PPW), periodic structures.

I. INTRODUCTION

P

ARALLEL-PLATE modes arise in planar environments that are effectively shielded by metallic conductors. Examples of such environments include high-frequency multilayered printed circuit boards (PCBs), where multiple ground, power, and signal planes may be interconnected with vias [1], or in closely spaced substrate-integrated-waveguide (SIW) components interacting due to leakage into the surrounding parallel-plate medium [2], [3], or in the introduction of shielding planes to suppress backward radiation in aperture-coupled patch antennas [4]. In these situations, the unwanted excitation of parallel-plate modes can cause interference and false signaling, as well as reduction of antenna radiation efficiencies, degrading the overall performance of these systems.

Manuscript received April 21, 2015; revised July 13, 2015 and December 07, 2015; accepted February 12, 2016. Date of publication March 10, 2016; date of current version April 01, 2016. This work was supported by NovAtel Inc. and by the Natural Sciences and Engineering Research Council (NSERC) of Canada under a Collaborative Research and Development (CRD) Grant. The authors are with the Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada T6G 2V4 (e-mail: iyer@ece. ualberta.ca). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2532870

Suppression of noise in the form of parallel-plate modes has been studied extensively in the literature. Decoupling capacitors have been used to give noise signals a low-impedance path through which to propagate away from sensitive circuit elements [5], [6]; however, these generally require fairly large dimensions and are limited to relatively low-frequency applications. Newer methods include simple gaps or defects in the ground plane, commonly known as defected-ground structures (DGSs) [7], [8]. However, the application of these techniques is often not guided by any general theory or rigorous analysis. One popular technology employs cascaded periodic structures know as electromagnetic bandgap (EBG) structures [9], [10], which have been used to prevent the propagation of parallel-plate modes in certain frequency bands and directions by employing periodically arranged resonators [11]–[13]. In such structures, it is often required that the physical size of the EBG be on the order of one-quarter to one-half of a guided wavelength, which can be a considerable and expensive amount of space in high-density circuits once multiple EBG periods are taken into account. These structures may also employ a large number of vias that complicate their design. Therefore, a miniaturized uniplanar implementation is highly desired. One method for the miniaturization of EBGs is the application of transmission-line metamaterial (TL-MTM) techniques. TL-MTMs have been used extensively for the miniaturization of a number of microwave-circuit components, and their capacity for precise control of passband and bandgap properties has been well documented [14]–[16]. TL-MTMs operate on the principle that the introduction of reactive loading components (e.g., capacitors and inductors or additional resonators [17], [18]) in series or shunt into a regular transmission line (TL) allows one to engineer the phase shift per unit length, with the potential to mimic the behavior of much longer unloaded TLs. Since TL theory is well understood, it proves useful in obtaining analytical expressions for the propagation characteristics of the entire TL-MTM system. Multiconductor EBGs can also be modeled to a high degree of accuracy as TL-MTMs through a multiconductor transmission-line (MTL) analysis [13]. Another advantage of TL-MTMs is that they can support a backward-wave propagation characteristic (also referred to as “left-handed” or “negative refractive index”), in which the desired mode incurs phase advance as it propagates [19]–[21]. In this case, the phase and group velocities possess opposite signs, where the group velocity represents power flow in an isotropic medium. When this backward mode interacts with a traditional forward mode, contradirectional coupling causes the formation of a bandgap. Importantly, this behavior can be realized when

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BARTH AND IYER: MINIATURIZED UNIPLANAR METAMATERIAL-BASED EBG FOR PARALLEL-PLATE MODE SUPPRESSION

the size of the EBG unit cell is extremely sub-wavelength [13], [22]. This paper is organized as follows. In Section II, a metamaterial-inspired EBG structure based on a shielded conductor-backed coplanar waveguide (S-CBCPW) for coupling with the parallel-plate mode is introduced. Its dispersive properties are analyzed in detail by means of an MTL equivalent-circuit model, and are compared to a system of isolated modes in order to understand the origins of the coupled dispersion properties. In Section III, a simple, one-dimensional (1-D) EBG for suppression of the parallel-plate waveguide (PPW) mode from 2.4 to 6.0 GHz is designed and its bandgap properties are confirmed by matching the MTL equivalent-circuit model to dispersion data computed by Ansys HFSS. Simulated and measured data demonstrate excellent agreement, and validate the predicted bandgap. In Section IV, a novel two-dimensional (2-D) radial EBG is created by cascading 1-D EBG unit cells in the azimuthal direction, and is used to demonstrate the suppression of parallel-plate-mode coupling between vias in a two-layer PCB at X-band. A prototype was manufactured and characterized, and the resulting suppression was found to be in good agreement with simulations. Other potential applications are discussed.

1177

Fig. 1. Host S-CBCPW structure. (a) Cross-sectional side view (conductors numbered as discussed in Section II-A). (b) Middle layer as viewed from the top with the coordinate axes as indicated.

II. THEORY A. Host Medium and MTL Model MTMs afford the ability to control dispersion properties such as the phase velocity and attenuation constant for each supported mode, subject to the physical constraints imposed by causality [23]. TL-MTMs, a sub-class of a large variety of MTMs, can be realized by periodically inserting shunt inductors and series capacitors into a host TL structure. The host TL selected for this work is the S-CBCPW, which is shown in Fig. 1(a) and (b). Since both the series and shunt loading components can be inserted into the three coplanarwaveguide (CPW) conductors on the same plane [conductors 2–4 in Fig. 1(a)], this host TL enables a fully uniplanar design without the need for vias. Furthermore, the presence of the conductor backing (conductor 1) and shield (conductor 5) allow for the interaction of the CPW mode with PPW modes, supported between these conductors and those of the CPW. The two parallel-plate modes, corresponding to fields above or below the CPW conductors in Fig. 1(a), will be referred to as the upper and lower PPW modes, respectively. When the upper PPW region is air-filled ( ) and its height is sufficiently large (typically ), it has been found that the upper PPW mode can be an effective low-frequency model for a loosely bound surface-wave (SW) mode. It should be noted that this MTL system not only supports the PPW and CPW modes, but also a coupled slot-line (CSL) mode. The electric-field lines corresponding to these modes are depicted in Fig. 2(a)–(c). With respect to the symmetry plane indicated by the white dashed lines, the PPW, CPW, and SW modes are even modes, whereas the CSL mode is odd. MTL theory can be used to model this system. The host TL properties are determined by extracting the per-unit-length capacitance

Fig. 2. Quasi-TEM modes supported by the S-CBCPW structure. (a) PPW, only the lower PPW mode shown. (b) CPW. (c) CSL. The white dashed line represents the symmetry plane for the definition of even and odd modes. Propagation is in the -direction with the coordinate axes as indicated.

Fig. 3. MTL equivalent-circuit model of the unit cell. Propagation is in the -direction, as indicated. Conductor numbering is to be read as consistent with the labels in Fig. 1(a).

and inductance from finite-element-method (FEM) simulations [assuming perfect magnetic conductor (PMC) boundaries on the transverse edges of the S-CBCPW TL, as indicated by the dashed lines in Fig. 1(a)], from which propagation constants and characteristic impedances are derived [24]. The TL-MTM unit cell is created by periodically loading the S-CBCPW structure with series capacitors and shunt inductors, as shown in the MTL equivalent circuit in Fig. 3. B. Dispersion Properties The dispersive properties of the TL-MTM can be analyzed by assuming an infinite cascade of unit cells. Firstly, the unit-cell equivalent circuit in Fig. 3 is generalized to an transmission network, in which the input field quantities (currents and

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Fig. 4. Example dispersion diagram. (a) Coupled even modes. (b) Isolated even modes. Solid (red) curves represent the phase incurred per unit cell ( ), dashed (blue) curves represent the attenuation per unit cell ( ).

voltages) of the th unit cell are related to those at the output as follows:

(1) Bloch’s theorem [25] has been invoked to relate the input and output circuit quantities between the ports as indicated, where is the physical length of the unit cell imparted by the host TL. The propagation constants represent the complex coupled Bloch-mode solutions supported by this system. Using (1) and the commutative property of the sub-matrix components of the symmetric reciprocal transmission network, the Bloch modes can be simply expressed as the solution to the characteristic equation (2) An example 1-D dispersion diagram derived from the equivalent circuit in Fig. 3 is shown in Fig. 4(a) and (b), which, respectively, present the dispersions of the coupled and corresponding isolated modes. These diagrams will be used to explain several notable features. Since the odd (CSL) mode does not couple with the other modes, its dispersion curves have been omitted for clarity. The dashed–dotted black line represents the vacuum light line, while the dotted line represents propagation in the substrate dielectric or, equivalently, the dispersion of the isolated PPW mode. The solid (red) lines correspond to , while the dashed (blue) lines correspond to . Generally, the sign of the slope at any point of the curves on this diagram indicates the direction of the mode’s group velocity (hence, direction of power flow) relative to its phase velocity. Since this work excites the coupled system using a PPW mode, we establish the reference that power flows into the system in the forward direction. Therefore, for the purposes of the present discussion, a positive slope corresponds to a power flow in the positive direction, and likewise a negative slope, indicates power flow in the negative direction. It is worth noting that the attenuation constants shown in Fig. 4 do not correspond to resistive losses, which were not considered in the analytical derivation of these modes,

but rather represent reactive attenuation due to two distinct mechanisms. The first mechanism arises from a mode being cut off, which is to say that the propagation constant exhibits . This describes an evanescent mode, in which power is reflected due to an inability of the system to support propagation. The second mechanism arises from contradirectional forward-backward coupling as described in [13]. In this case, attenuation results from the coupling of power from one mode traveling in one direction into another mode traveling in the opposite direction, such that there is no net transmission of power for the infinite periodic structure. Since propagation occurs simultaneously with attenuation, the coupled mode is a complex mode exhibiting a complex propagation constant with . The presence of either form of attenuation may be exploited to suppress modes of interest. To begin, it is worthwhile considering the dispersions of the isolated (even) modes, which are determined by removing the unnecessary conductors from the MTL equivalent-circuit model. The TL properties, however, are computed assuming that these conductors exist, but serve only as parasitic elements. The origin of these modes is evident from the unit cell in Fig. 1(b) and its MTL equivalent-circuit model in Fig. 3. In particular, it can be seen that the shunt capacitors and series inductors serve to load the CPW mode, such that it exhibits a backward characteristic. The forward characteristic of the PPW modes are largely unaffected by the loading. Coupling between these isolated modes has two criteria, which are: 1) mode matching of the transverse fields and 2) phase matching in the longitudinal direction [26], [27]. The CPW and PPW modes exhibit a large degree of field overlap, and this satisfies the first criterion. The second criterion is satisfied where the two isolated-mode dispersion curves intersect on the dispersion diagram. Recognizing these features in the coupled system of Fig. 4, several regions may be identified. At low frequencies, only the PPW modes propagate. As frequency increases towards 2.4 GHz, the lower PPW mode becomes increasingly dispersive as it couples more strongly with the backward CPW mode. At 2.4 GHz, the CPW mode starts to propagate; however, since it is strongly coupled with the lower PPW mode, the contradirectional power flow between the forward lower PPW mode and the reactively loaded backward CPW mode results in a complex mode bandgap from 2.4 to 5.0 GHz. It should be noted that the portion of the attenuation ( ) curve above 5.0 GHz, which exists between 60 and 90 , corresponds to the cutoff CPW mode, and is not part of a complex-mode system with the propagating lower PPW mode above 6 GHz. From 5.0 to 6.0 GHz, the lower PPW and CPW modes start to decouple, after which propagation of the lower PPW mode begins to be restored (identified by the slope of the asymptote at higher frequencies). The CPW mode’s propagation is not restored until well above 10 GHz. Lastly, there is weak coupling between the forward lower PPW mode and forward upper PPW mode near 6.5 GHz. Although this work shall focus exclusively on the even modes, it is worth noting that the odd CSL mode has a bandgap between 6.5 and 7.0 GHz and is cut off below 3.2 GHz. It is unaffected by the coupled system since being odd it does not directly couple with any other supported mode.

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Fig. 5. Layout of the top surface of the printed EBG unit cell.

III. 1-D EBG A. Design In this section, the theory presented in Section II is validated using a proof-of-concept design, which possesses a 1-D layout for ease of design, fabrication, and characterization. The EBG is designed for fabrication on a single substrate, and as an initial goal of the design, suppression of the (lower) parallel-plate mode, is sought between 2.4 and 6.0 GHz. A unit cell is designed with use of the equivalent-circuit model to be electrically small and to employ low-valued loading, which enables its realization in a fully printed fashion. Theoretically, this topology can be modeled using the conditions previously given for the modeling of the SW mode, i.e., the upper dielectric may be assigned a relative permittivity of 1, and the shield height ( ) may be made sufficiently large (100 mm is used in this case). The layout of the -loaded CPW layer of the designed unit cell is shown in Fig. 5; the dimensions of the design are the unit cell period mm, width mm, the CPW strip line width mm, the CPW gap width mm, loading capacitor length mm, and loading inductor width mm. A minimum feature size of 0.2 mm is used for the interdigitated capacitor’s finger and gap widths for ease of fabrication using standard etching processes. The printed loading components are designed (estimated using empirical formulas [28], [29] and then mildly tuned in simulation) to provide loading values of pF and nH. The properties of the dielectric ( mm, , , and 1-oz copper cladding on both sides with a bulk conductivity of 5.8 10 S m) are determined by the preselected substrate (Rogers RO-4350). B. Simulation The EBG’s dispersive properties were confirmed by performing an eigenmode simulation in HFSS. This simulation setup involves embedding the unit cell in a vacuum box with a perfectly matched layer, master/slave, and PMC boundaries applied to the top surface, longitudinal faces, and transverse faces, respectively. These support the necessary fields to simulate an infinite array of unit cells in the transverse direction. The results of this simulation for the even-mode solutions are shown in Fig. 6, along with the curves obtained from the MTL equivalent-circuit model. Generally, they demonstrate excellent agreement, but there is a moderate divergence between these data towards larger values. This is attributed to the fact that

Fig. 6. MTL equivalent-circuit model (solid curves) and HFSS dispersion data (large dots).

the printed loading components cannot strictly be regarded as lumped, as assumed by the equivalent-circuit model; indeed, they are frequency dependent, and this attribute is most evident when they are responsible for generating large phase shifts per unit cell. The weak interaction between modes near 6.5 GHz validates the previous statement that the vacuum-filled upper PPW mode with a relatively large height (as was modeled in Section II) can be a good approximation for the loosely bound SW mode since an open boundary condition, rather than a shield conductor, was used above the EBG layer in this simulation. This is a behavior that could potentially be exploited in the formation of SW bandgaps, such as in the design of SW-suppressing ground planes for antenna applications, but which will not be further investigated in this work. The parallel-plate-mode suppression ability of the EBG structure was examined by simulating the scattering parameters of the PPW mode. Using HFSS, nine EBG unit cells were cascaded and the (lower) PPW mode was excited using waveports. PMC boundary conditions were again used on the transverse faces, and a radiation boundary was used on the remaining faces above the unit cells. A 25-mm section of unloaded PPW was used to interface the waveports to the EBG. The results of this simulation are shown by the solid (red) and dashed (blue) curves in Fig. 7. The 10-dB insertion-loss points indicate a bandgap region from approximately 2.6 to 6.4 GHz, which is very close to the design criteria, and also very close to the dispersion data given by the HFSS eigenmode simulation. These results validate the accuracy and utility of the equivalent-circuit approach in predicting and designing the EBG bandgap properties. C. Experiment To confirm the simulation results, a PCB containing the designed fully printed EBG was fabricated. Using a 1.524-mmthick Rogers RO-4350 substrate, a 5 9 grid of unit cells was connected to a PPW in order to sufficiently approximate the simulation setup. This PPW was then linearly tapered to a 50microstrip (MS) line for ease of measurement. The fabricated structure is shown in Fig. 8(a), along with the appropriate dimensions. The total length of the EBG is 45 mm, and the total width is 50 mm. The length of the PPW region on either side

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Fig. 7. Simulated PPW mode and measured scattering parameters.

large taper and MS sections, which were not included in the simulation model. Indeed, in both data the bandgap behavior of the EBG is clearly visible between 2.6 and 6.4 GHz, as indicated by the dashed vertical lines. It should be noted that the resonant behavior below the bandgap region is owed to Fabry–Perot resonances of the highly dispersive coupled PPW-CPW mode. Discrepancies in the upper passband may be attributed to the frequency response of the MS and taper sections in the fabricated device. It is worth noting that the electrical size of the unit cell over the designed bandgap region ranges from approximately to , where is the wavelength in the dielectric. This demonstrates the strong degrees of miniaturization possible with the TL-MTM approach, which can be further appreciated by noting that the strength of the loading components (and hence, miniaturization) is only limited by the minimum feature size of the manufacturing process. IV. 2-D RADIAL EBG A. Design

Fig. 8. Fabricated PCB: (a) with MS, taper, and PPW regions of dimensions as indicated. (b) Experimental setup.

of the EBG is 10 mm, and the MS sections are 20 mm long and 3.3 mm wide. The linear tapers connecting the PPW and MS were 50 mm long. SMA connectors were used to interface an Agilent Technologies N5244A vector network analyzer (VNA) with the PCB to perform the measurements, as shown in the experimental setup of Fig. 8(b). The measured data are plotted in Fig. 7 along with the simulated data, and it is clear that they exhibit very good general agreement, despite the finite width of the EBG section and the

The validation of the bandgap properties of the 1-D EBG prompts us to examine whether it may be straightforwardly extended to a more general and realistic case of parallel-plate mode suppression in multilayer 2-D applications. For example, parallel-plate noise is detrimental to signal integrity in high-speed PCBs, which contain multiple ground and/or power layers. This noise can be created by the routing of signal paths between layers with the use of vias, and the resulting noise propagates away radially through parallel-plate modes. In order to suppress this noise, a 2-D solution is required. The EBG proposed in this work can be constructed in radial form to decrease coupling between two parallel vias, as shown in Fig. 9(a) (top view) and Fig. 9(b) (side view). This EBG is composed of trapezoidal sections, which are slightly distorted sections of cascaded 1-D unit cells that have been arranged side-by-side in order to form a complete circle. This setup is similar to that used in [12], which compared the transmission between two vias in a bi-layer medium with and without a Sievenpiper mushroom EBG, in order to determine its effects. The Sievenpiper structure operates extremely well as an EBG, but its construction is complicated by the requirement for a via for each unit cell. The proposed radial EBG enables the suppression of signals coupled into the parallel-plate mode through 2-D cylindrical waves, while maintaining its simplistic 1-D uniplanar design approach. To demonstrate the versatility of the design procedure and exploit its fully printed nature, this EBG is designed to present a bandgap around X-band, where discrete (surface-mount) inductors and capacitors cannot be used due to their typically low self-resonance frequencies. The EBG is designed to suppress the upper parallel-plate mode supported by a mm RO-3010 ( , ) substrate. The EBG is realized on the bottom metallization layer and the unit cell has the following properties in keeping with the symbols previously introduced: mm, mm (average), mm, mm, mm, mm, with the interdigitations each 0.1 mm wide and spaced 0.1 mm apart. The EBG is interfaced with

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Fig. 10. Simulated scattering parameters of a single radial section of the proposed 2-D EBG.

Fig. 9. Example setup for two-layer via-induced PPW-noise-suppressing radial EBG. (a) Top view. (b) Side view.

a mm FR-4 ( , ) layer placed below the RO-3010 layer, which serves as a low-cost shielded substrate. The EBG comprises three unit cells in the radial direction, and in its full radial form, employs 36 unit cells around the azimuth. The vias, which are used for both excitation and detection, and which were designed to be connected to 50- Teflonfilled SMA connectors, are separated by 20 mm. The distance between the center of the excitation via and the inner radius of the EBG is 7.5 mm. It should be noted that the theory proposed in Section II allows these dimensions to be considerably reduced if necessary through various design choices such as using a smaller number of unit cells (at the expense of suppression ability), or using an etching process that could produce reduced feature sizes, which would allow for increased loading component values and, hence, a smaller period and/or increased bandgap width. These techniques would prove advantageous where space is limited, e.g., in systems with densely packed vias. B. Simulation—Absorbing Boundaries The case of an effectively unbounded PPW medium was investigated first in order to establish the realistic suppression ability of the EBG unobscured by multiple reflections that would be introduced by finiteness of the simulation domain. This was accomplished by placing absorbing boundaries around the edges of the finite PPW medium in simulation. The transmission response of this EBG, as measured through the upper layer RO-3010 dielectric, was simulated over a single radial section [as indicated in Fig. 9(a)] with PMC transverse boundary conditions. The resulting scattering parameters are

Fig. 11. Simulated scattering-parameter magnitudes of the structure with ab. sorbing boundaries and via excitations with and without the EBG. (a) . (b)

shown in Fig. 10, which reveal a suppression of around 20 dB over the 7.5 mm extent of the EBG. The resulting scattering parameters of the complete EBG are shown in Fig. 11(a) and (b). Suppression across the X-band by up to 50 dB is observed when the EBG is present. Resonant interactions caused by coupling between the vias and the 2-D EBG structure are observed at some frequencies (e.g., at 7.0 and 11.3 GHz). These resonant frequency points were investigated and found to depend on a number of factors, such as the radius of the exciting vias, the inner radius of the EBG, and the number of EBG unit cells employed radially—as such, they could likely be mitigated through a number of design choices which vary some or all of these parameters. Nevertheless, even with these resonances, the suppression maintains significant improvement over the case without the EBG at all frequencies.

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(a)

the complex current-density magnitudes (plotted on an identical logarithmic scale) on the metallization layer at the boundary between the RO-3010 and FR-4 dielectrics, which contains the EBG [the same layer shown in Fig. 9(a)]. The excitation via is on the left-hand side surrounded by the EBG. At 9 GHz, the EBG effects a drop in the field level by approximately two orders of magnitude (40 dB), confirming the suppression suggested by the scattering parameters. The null between the EBG and the excitation via is evidence of the standing wave created by the signal being reflected by the EBG, and is noticeably absent at 5 GHz, where the EBG essentially completely transmits the (upper) PPW mode. The corresponding cross-sectional complex magnitudes of the electric fields (also plotted on an identical logarithmic scale) are shown in Fig. 12(c) and (d), in which it can be seen that the field decay primarily takes place inside the EBG region as expected. There is some field leakage into the FR-4 layer, but it appears to be confined within the EBG region and is relatively small in magnitude (approximately 10 dB lower than the maximum fields in the RO-3010 dielectric). At 5 GHz, the fields are still constrained by the EBG (the currents must still pass through the thin CPW strips), but there is much less suppression as indicated by the field strengths over the outer-most unit cells. There is also slightly less leakage into the lower dielectric, indicating that the PPW mode in the upper dielectric is better guided by the EBG at this frequency. C. Simulation—Open Boundaries

(b)

(c)

(d) Fig. 12. Simulated complex surface-current-density magnitudes on the EBG layer at: (a) 9 GHz and b) 5 GHz, and complex electric-field magnitudes in the cross section (figure dimensions scaled vertically for clarity) at: (c) 9 GHz and (d) 5 GHz.

Fig. 12(a) and (b) examines the simulated fields at 9 GHz (the frequency exhibiting maximum parallel-plate-mode suppression) and 5 GHz (outside the EBG bandgap). They detail

To enable comparison to a fabricated prototype, which would possess finite dimensions, the EBG was also simulated with open boundaries, with both layers of size 60 mm 80 mm and embedded in vacuum. Fig. 13(a) and (b) shows the resulting simulated scattering parameters, for which up to approximately 40 dB of suppression and a corresponding improvement in return loss is observed over the frequency range of 7.5–11.5 GHz, corresponding to up to roughly 67 dB per guided wavelength of suppression. This is slightly lower, but comparable with previously reported results for Sievenpiper EBGs, e.g., [12], which reported suppression of up to roughly 75 dB per guided wavelength for a similar two-layer setup, or roughly 95 dB per guided wavelength for a UC-EBG [30]. Other suppression mechanisms such as high dielectric-constant rodded photonic crystals have reported up to roughly 92 dB per guided wavelength [31], and circular high-impedance surfaces have been reported to obtain up to roughly 100 dB per guided wavelength [32]. However, it should be recalled that our proposed unit cell is uniplanar, and therefore much easier to fabricate, as well as having a bandgap that may be accurately designed using MTL theory, both of which provide clear advantages over these other devices. The apparent noise in the resulting data is due to the fact that the open boundaries of the finite-sized PPW (which is electrically large at X-band) create reflections that establish a large number of 2-D resonances (cavity modes). D. Experiment The PPW with EBG was fabricated by LPKF Laser & Electronics AG using a high-resolution laser-based PCB prototyping system, and is depicted in Fig. 14. The vias were realized with the use of flush-mount SMA connectors attached to the top face

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Fig. 13. Simulated scattering parameter magnitudes of the structure with open and (b) . boundaries and via excitations with and without the EBG: (a)

Fig. 15. Experimental setup for measurement of the EBG. (a) Side view. (b) Top view. (c) Complete experimental setup. Fig. 14. Fabricated EBG on the middle layer (as defined in this work) printed on a 0.254-mm Rogers RO-3010 substrate. The center conductors of SMA connectors are inserted into the holes and serve as the exciting vias.

of the upper conductor, for which the center pin was clipped and soldered to the back side of the middle conductor. The two layers (FR-4 and RO-3010) were compressed together using two clamps. The pressure was distributed with the use of a hard plastic spacer with a rectangular aperture (approximately 25 mm thick) and a layer of firm styrofoam (approximately 14 mm thick). The entire assembly is shown in Fig. 15(a) (side view) and Fig. 15(b) (top view), and a photograph of the complete experimental setup is shown in Fig. 15(c). A layer of masking tape was used to hold the two dielectrics together and prevent them from sliding laterally.

The measured results are indicated in Fig. 16(a) and (b). These data exhibit a frequency up-shift relative to the simulated case, which could be attributed to a slightly lower resulting from substrate tolerances and possibly from a small air gap between layers (since the layers were not bonded by any means, but rather manually compressed together during measurement). It was found that if the simulation was re-run assuming an average dielectric constant of and an average air gap of 50 m between layers, then the simulated and measured data sets matched reasonably well, as shown in the figures. The proposed EBG could prove useful in mitigating the effects of PPW-mode excitation in several applications noted at the beginning of this work, including coupling reduction between adjacent SIW circuits [33], reduction of parasitic PPW

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mount) elements, which makes it both low-cost and suitable for high-frequency applications. The dispersion of the supported modes was verified by full-wave simulation, and the transmission properties of the PPW mode were confirmed by simulation and in experiment. All of these results demonstrated very good agreement, validating the accuracy of the MTL equivalent-circuit model. The suppression of radially propagating PPW-mode noise in multilayer PCBs between vias was suggested as a practical application and also validated in simulation and experiment. The 1-D EBG was radially arranged around a via, and this was found to suppress the radially propagating PPW mode in two dimensions by approximately 50 dB at X-band over a length of just 7.5 mm. Several applications of the proposed EBG were suggested. ACKNOWLEDGMENT The authors would like to thank Dr. A. Chamseddine and J. Freestone, both with NovAtel Inc., Calgary, AB, Canada, for stimulating discussions, the Rogers Corporation for providing donations of substrate materials, and LPKF Laser & Electronics AG for providing the 2-D radial EBG prototype. REFERENCES

Fig. 16. Measured and simulated (assuming average and a 50- m air gap between layers) scattering parameter magnitudes with and without the . (b) . EBG. (a)

coupling in conductor-backed aperture-coupled patch antennas [4], and even the design of miniaturized and/or multiband patch antennas [34]. SW applications of the EBG are suggested by the observed coupling between the SW mode and the even modes of the S-CBCPW structure. This coupling may be exploited in many applications, including the mitigation of multipath interference in global navigation satellite system (GNSS) antennas [35], affording additional degrees of freedom in steering surface waves on SW antennas and launchers [36], and generally in miniaturizing SW components. Incidentally, the odd CSL mode could be used to couple with TE SW modes, creating odd-mode bandgaps. Furthermore, the coupling between the even modes (odd modes) and the TM (TE) SW modes results in dispersion features inside the light line, which could be used in combination towards the design of miniaturized dual-polarized or circularly polarized leaky-wave antennas [37]. V. CONCLUSION A uniplanar EBG and MTL equivalent-circuit model have been proposed for the suppression of parallel-plate modes. This EBG is based on the TL-MTM and operates on the principle of contradirectional coupling between one of the forward PPW modes and the backward CPW mode of an S-CBCPW structure, providing a large controllable stopband. This allows for a uniplanar printable design without any vias or discrete (surface-

[1] R. Abhari, G. V. Eleftheriades, and T. E. van Deventer-Perkins, “Physics-based CAD models for the analysis of vias in parallel-plate environments,” IEEE Trans. Microw. Theory Techn., vol. 49, no. 10, pp. 1697–1707, Oct. 2001. [2] M. Pasian, M. Bozzi, and L. Perregrini, “Crosstalk in substrate integrated waveguides,” IEEE Trans. Electromagn. Compat., vol. 57, no. 1, pp. 80–86, Feb. 2015. [3] D. Deslandes and K. Wu, “Accurate modeling, wave mechanisms, and design considerations of a substrate integrated waveguide,” IEEE Trans. Microw. Theory Techn., vol. 54, no. 6, pp. 2516–2526, Jun. 2006. [4] A. Bhattacharyya, O. Fordham, and Y. Liu, “Analysis of stripline-fed slot-coupled patch antennas with vias for parallel-plate mode suppression,” IEEE Trans. Antennas Propag., vol. 46, no. 4, pp. 538–545, Apr. 1998. [5] A. Madou and L. Martens, “Electrical behavior of decoupling capacitors embedded in multilayered PCBs,” IEEE Trans. Electromagn. Compat., vol. 43, no. 4, pp. 549–556, Nov. 2001. [6] J. Hobbs et al., “Simultaneous switching noise suppression for high speed systems using embedded decoupling,” in Proc. Electron. Compon. Technol. Conf., Orlando, FL, USA, May 2001, pp. 339–343. [7] S. Wu, C. Tsai, T. Wu, and T. Itoh, “A novel wideband common-mode suppression filter for gigahertz differential signals using coupled patterned ground structure,” IEEE Trans. Microw. Theory Techn., vol. 57, no. 4, pp. 848–855, Apr. 2009. [8] A. B. Abdel-Rahman, “Coupling reduction of antenna array elements using small interdigital capacitor loaded slots,” Progr. Electromagn. Res. C, vol. 27, pp. 15–26, 2012. [9] D. Sievenpiper, L. Zhang, R. F. J. Broas, N. G. Alexopolous, and E. Yablonovitch, “High-impedance electromagnetic surfaces with a forbidden frequency band,” IEEE Trans. Microw. Theory Techn., vol. 47, no. 11, pp. 2059–2074, Nov. 1999. [10] F. Yang and Y. Rahmat-Samii, Electromagnetic Band Gap Structures in Antenna Engineering. Cambridge, U.K.: Cambridge Univ. Press, 2009. [11] F. Yang, K. Ma, Y. Qian, and T. Itoh, “A uniplanar compact photonic-bandgap (UC-PBG) structure and its applications for microwave circuits,” IEEE Trans. Microw. Theory Techn., vol. 47, no. 8, pp. 1509–1514, Aug. 1999. [12] R. Abhari and G. V. Eleftheriades, “Metallo-dielectric electromagnetic bandgap structures for suppression and isolation of the parallel-plate noise in high-speed circuits,” IEEE Trans. Microw. Theory Techn., vol. 51, no. 6, pp. 1629–1639, Jun. 2003. [13] F. Elek and G. V. Eleftheriades, “Dispersion analysis of the shielded Sievenpiper structure using multiconductor transmission-line theory,” IEEE Microw. Wireless Compon. Lett., vol. 14, no. 9, pp. 434–436, Sep. 2004.

BARTH AND IYER: MINIATURIZED UNIPLANAR METAMATERIAL-BASED EBG FOR PARALLEL-PLATE MODE SUPPRESSION

[14] G. V. Eleftheriades and K. G. Balmain, Negative-Refraction Metamaterials: Fundamental Principles and Applications. Hoboken, NJ, USA: Wiley, 2005. [15] C. Caloz and T. Itoh, Electromagnetic Metamaterials: Transmission Line Theory and Microwave Applications. Hoboken, NJ, USA: Wiley, 2005. [16] R. Marques, F. Martin, and M. Sorolla, Metamaterials with Negative Parameters: Theory, Design and Microwave Applications. Hoboken, NJ, USA: Wiley, 2008. [17] J. Naqui, M. Duran-Sindreu, A. Fernandez-Prieto, F. Mesa, F. Medina, and F. Martin, “Multimode propagation and complex waves in CSRR-based transmission-line metamaterials,” IEEE Antennas Wireless Propag. Lett., vol. 11, pp. 1024–1027, 2012. [18] J. Naqui, A. Fernandez-Prieto, F. Mesa, F. Medina, and F. Martin, “Effects of inter-resonator coupling in split ring resonator loaded metamaterial transmission lines,” J. Appl. Phys., vol. 115, 2014, Art. no. 194903. [19] G. V. Eleftheriades, A. K. Iyer, and P. C. Kremer, “Planar negative refractive index media using periodically LC loaded transmission lines,” IEEE Trans. Microw. Theory Techn., vol. 50, no. 12, pp. 2702–2712, Dec. 2002. [20] A. Grbic and G. V. Eleftheriades, “Dispersion analysis of a microstrip-based negative refractive index periodic structure,” IEEE Microw. Wireless Compon. Lett., vol. 13, no. 4, pp. 155–157, Apr. 2003. [21] C. Caloz and T. Itoh, “Transmission line approach of left-handed (LH) materials and microstrip implementation of an artificial LH transmission line,” IEEE Trans. Antennas Propag., vol. 52, no. 5, pp. 1159–1166, May 2004. [22] S. Barth and A. K. Iyer, “A miniaturized uniplanar metamaterial-based EBG for parallel-plate switching noise suppression,” in Proc. IEEE Int. Antennas Propag. Symp./USNC/URSI Nat. Radio Sci. Meeting, Vancouver, BC, Canada, Jul. 2015, pp. 1586–1587. [23] M. Mojahedi, K. J. Malloy, G. V. Eleftheriades, J. Woodley, and R. Y. Chiao, “Abnormal wave propagation in passive media,” IEEE J. Sel. Topics Quantum Electron., vol. 9, pp. 30–39, Jan.–Feb. 2003. [24] C. R. Paul, Analysis of Multiconductor Transmission-Lines. Hoboken, NJ, USA: Wiley, 1994. [25] R. E. Collin, Foundations for Microwave Engineering, 2nd ed. Hoboken, NJ, USA: Wiley, 2000. [26] A. Hardy and W. Streifer, “Coupled mode theory of parallel waveguides,” J. Lightw. Technol., vol. 3, no. JLT-5, pp. 1135–1146, Oct. 1985. [27] S. E. Miller, “Coupled wave theory and waveguide applications,” Bell Syst. Tech. J., vol. 23, no. 3, pp. 661–719, 1954. [28] J. K. A. Everard and K. K. M. Cheng, “High performance direct coupled bandpass filters on coplanar waveguide,” IEEE Trans. Microw. Theory Techn., vol. 41, no. 9, pp. 1568–1573, Sep. 1993. [29] G. D. Alley, “Interdigital capacitors and their application to lumpedelement microwave integrated circuits,” IEEE Trans. Microw. Theory Techn., vol. MTT-18, no. 12, pp. 1028–1033, Dec. 1970. [30] D. Lin, K. C. Hung, C. T. Wu, and C. S. Chang, “Partial uniplanar compact electromagnetic bandgap combined with high-impedance surface to suppress simultaneous switching noise,” Electron. Lett., vol. 45, no. 16, pp. 829–830, 2009. [31] T. Wu and S. Chen, “A photonic crystal power/ground layer for eliminating simultaneously switching noise in high-speed circuit,” IEEE Trans. Microw. Theory Techn., vol. 54, no. 8, pp. 3398–3406, Aug. 2006. [32] M. M. Bait-Suwailam and O. M. Ramahi, “Simultaneous switching noise mitigation in high-speed circuits using coamplementary split-ring resonators,” Electron. Lett., vol. 46, no. 8, pp. 563–564, 2010. [33] E. Ghahramani, R. A. Sadeghzadeh, B. Boroomandisorkhabi, and M. Karami, “Reducing mutual coupling of SIW slot array antenna using uniplanar compact EBG (UC-EBG) structure,” in Proc. Eur. Antennas Propag. Conf., The Hague, The Netherlands, Apr. 2014, pp. 2002–2004.

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[34] B. Smyth, S. Barth, and A. K. Iyer, “Design of multi-band microstrip patch antennas using miniaturized 1D metamaterial-based EBGs,” in Proc. Joint USNC-URSI Radio Sci. Meeting/IEEE AP-S Symp., Vancouver, BC, Canada, Jul. 2015, p. 24. [35] R. Baggen, M. Martinez-Vazquez, J. Leiss, S. Holzwarth, L. S. Drioli, and P. de Maagt, “Low profile GALILEO antenna using EBG technology,” IEEE Trans. Antennas Propag., vol. 56, no. 3, pp. 667–674, Mar. 2008. [36] S. K. Podilchak, A. P. Freundorfer, and Y. M. M. Antar, “Planar surface-wave sources and metallic grating lenses for controlled guidedwave propagation,” IEEE Antennas Wireless Propag. Lett., vol. 8, pp. 371–374, 2009. [37] A. Grbic and G. V. Eleftheriades, “Leaky CPW-based slot antenna arrays for millimeter-wave applications,” IEEE Trans. Antennas Propag., vol. 50, no. 11, pp. 1494–1504, Nov. 2002.

Stuart Barth (S’07–GSM’11) received the B.Sc. and M.Sc. degrees in electrical engineering from the University of Alberta, Edmonton, AB, Canada, in 2012 and 2015, respectively, and is currently working toward the Ph.D. degree at the University of Alberta. His current research interests include the study of multiconductor transmission-line RF/microwave circuits, dispersion engineering of periodic structures, fundamental electromagnetic theory, antenna radiation-pattern shaping, and the design of artificial materials for use in communications networks. Mr. Barth serves as an officer of the IEEE Northern Canada Section MTT-S/ AP-S Joint Chapter. He was the recipient of the IEEE AP-S Pre-Doctoral Research Award in 2014 for his ongoing research into electromagnetic-bandgap structures for GPS antenna applications.

Ashwin K. Iyer (S’01–M’09–SM’14) received the BASc. (Hons.), MASc., and Ph.D. degrees in electrical engineering from the University of Toronto, Toronto, ON, Canada in 2001, 2003, and 2009 respectively. While with the University of Toronto, he was involved with the discovery and development of the negative-refractive-index transmission-line (NRI-TL) approach to metamaterial design and the realization of metamaterial lenses for free-space microwave subdiffraction imaging. He is currently an Associate Professor with the Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada, where he leads a team of graduate students in the investigation of novel RF/microwave circuits and techniques, fundamental electromagnetic theory, antennas, and engineered metamaterials, with an emphasis on their applications to microwave and optical devices, defense technologies, and biomedicine. He has coauthored a number of highly cited papers and four book chapters on the subject of metamaterials. Dr. Iyer currently serves as an Associate Editor for the IEEE TRANSACTIONS ON ANTENNAS AND PROPAGATION. He is Co-Chair of the IEEE Northern Canada Section’s Joint Chapter of the Antennas and Propagation Society (AP-S) and Microwave Theory and Techniques Society (MTT-S). He is a Registered Member of the Association of Professional Engineers and Geoscientists of Alberta (APEGA). He was the recipient of several awards, including the 2008 R. W. P. King Award and the 2015 Donald G. Dudley Jr. Undergraduate Teaching Award, both presented by the IEEE AP-S. His students were also recipients of several major national and international awards for their research.

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Multiple Fano-Like Transmission Mediated by Multimode Interferences in Spoof Surface Plasmon Cavity-Waveguide Coupling System Fei Fei Qin, Jun Jun Xiao, Zhen Zhen Liu, and Qiang Zhang

Abstract—Many efforts have been devoted to the design of photonic microcavities and the utilization of them in optical sensing, imaging, optomechanics, lasing, and micromanipulation. Cavities supporting spectrally close multiple resonance modes can favor energy exchange among the modes and the ambient, enabling nontrivial coherent dynamics that are useful in wave manipulation. Coupling between multimode cavities with multiple waveguides is a significant theme for optical, terahertz, and microwave signal control, but remains largely unexplored. Here we present a phenomenological modeling based on the coupled mode theory (CMT) that fully accounts for the interplays between such a cavity and surrounding waveguide structures in a generic situation with asymmetric coupling rates between the guiding channels and the resonant modes. It is shown that the waveguide-cavity couplings are crucial for the energy steering between the modes and their farfield radiation and provide flexible control over waveguide transmission featured with a multiple Fano line profile. Numerical simulations were conducted for a spoof plasmonic cavity waveguides system working at sub-GHz band to demonstrate these effects. The results are in good agreement with the CMT prediction. Index Terms—Integrated optics, optical waveguides, surface plasmons.

I. INTRODUCTION

R

ESONANT cavities, and their interactions with various ambient electromagnetic (EM) media or structures, have been a topic of interest through the study of optical, photonic, terahertz, and microwave signal manipulation [1], [2]. EM fields are confined in the resonant cavity with spatial pattern governed by the resonant mode symmetry, and temporally with a finite decay rate as the energy leaks out via near-field coupling or radiation, as well as intrinsic absorption [3], [4]. Dissipation is ubiquitous in dynamical systems encountered in nature because no

Manuscript received May 27, 2015; revised August 26, 2015 and January 05, 2016; accepted February 16, 2016. This work was supported by the Natural Science Foundation of China under Grant 11274083 and Grant 61575051, by the Natural Science Foundation of Guandong Province under Grant 2015A030313748, and by the Shenzhen Municiple Science and Technology Plan under Grant JCYJ20150513151706573, Grant KQCX20120801093710373, and Grant JSGG20150529153336124. (Corresponding author: Jun Jun Xiao.) The authors are with the College of Electronic and Information Engineering, Shenzhen Graduate School, Harbin Institute of Technology, Guangdong Province, Shenzhen 518055, Guangdong, China (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2533381

finite system is fully isolated from its environment. Once continuous leaky energy channels, e.g., propagating waves in free space or guiding modes in single-mode waveguides, are coupled aside to such resonant cavities, the coherent processes between different energy states and channels interference, giving rise to quantum-analog phenomena, such as Fano resonance [5]–[7] and electromagnetically induced transparency [8]. The features are usually manifested in the scattering or transmission spectra, or as a shift in the cavity resonant frequencies [9]. A lot of experimental and computational studies have been reported on such characteristics [10]–[12]. As well, theoretically, coupled mode theory (CMT) [2], [13]–[16] and coupled oscillator model [17]–[20] have been exploited to understand various coherent processes [21]–[24]. However, most studies in the literature focus only on the situation of single-mode cavity. When the cavity supports multiple resonances that are spectrally close to each other, the effects by simultaneous interplays between near-field coupling and far-field coupling to multiple external channels, particularly to both guiding and radiating ones, remain elusive. In contrast to Lorentzian resonance, Fano resonance is characterized by a distinct asymmetric line profile, which was first discussed in the atomic absorption spectrum [4]. The interaction of a discrete energy state and continuous energy state leads to an absorption spectrum or a transmission spectrum with asymmetrical shape. Analogies of Fano resonance have been found to be ubiquitous in classical optics and photonics, within plasmonic nanostructures and metamaterials [22], [25], [26]. For instance, optical extraordinary transmission through an array of sub-wavelength holes can be understood in a Fano resonance scenario. Recently, Fano resonance using artificial structures have been attracting a great deal of attention due to its very high sensitivity to the local environments, which can be used in applications as sensing [22], optical switching, and modulation [25], and as a surface plasmon coupler [26]. Fano resonance affected transmission was reported in a lot of systems based on plasmonic slot waveguide, for example, in stub-waveguide [16] and in waveguide-resonator configurations [27]. To this end, among the various classical physics fields where Fano resonance analogy has been explored, plasmonic structures are the most celebrated and attractive ones. However, since surface plasmon polariton (SPP) is basically electron oscillation on the noble metal surface, the operating frequency is limited to the visible and near-infrared. Meanwhile, intrinsically high loss of metal in these bands has been a major hinder towards

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applications. At much low frequencies, for example in the THz and GHz range, noble metals resemble a perfect electric conductor (PEC) and do not support SPP waves since the plasmon frequency, ( the charge and mass of electron, the free electron number, and the vacuum dielectric function) usually lies in the ultraviolet. To overcome that, Pendry et al. [28] and Garcia-Vidal et al. [29] have presented a new concept of structured surface with an array of holes or grooves in the surface that can be engineered to support surface bounded modes. With these so-called “spoof” or “designer” SPPs, the surface plasmon frequency and SPP-like dispersion relation could be tailored by the surface geometry well down to the terahertz and microwave region [30], [31]. Recently, ultra-thin spoof surface plasmon polariton (SSPP) structures, which were fabricated on a nearly zero-thickness metallic surface have been proposed [32]. Conformal propagation and localized surface plasmons (LSPs) were experimentally measured using the designer plasmonic metamaterials [33]–[35]. In this way, all the capabilities of nature LSPs in the optical regime can be transferred to much lower frequencies where electronic plasmon excitation is essentially absent and the Joule loss can be avoided. In this paper, we present a multimode CMT from the quantum optics analogue. The CMT fully accounts for the dynamics of the multiple resonant modes and their couplings to external waveguides. Therefore it provides intuitive perspective to the mode interplay. As an example, we analyze the Fano resonance arising from the strong symmetrical and asymmetrical couplings between two spoof–insulator–spoof (SIS) waveguides and a spoof LSP resonator that supports electric dipole, quadruple, and hexapole resonances in the sub-GHz regime. It is found that the LSP quadruple mode radiates more efficiently than both the dipole and hexapole modes due to the matched field pattern symmetry and coupling to the waveguides. The theoretical predications are verified by full-wave EM simulations. The results, arguably, can be applied to the THz and optical regime as well. Our approach therefore provides a practical and intuitive guidance for designing cavity-associated microwave and photonics devices. In Section II, we present the CMT for a multimode cavity that is evanescently coupled to multiple channels. Application of such theory to a spoof surface plasmon waveguide system is shown in Section III and the multimode interference effects are discussed. Section IV shows the analytical and explicit Fano profile from the CMT for a single-mode system. Finally, conclusions are presented in Section V.

are denoted by . Using the quantum optics theory, we can describe the system by the following Hamiltonian [36]:

(1) where the first two terms are the free Hamiltonians of the cavity and the waveguide modes, respectively, and the last term indicates the coupling between them. In (1), is the imaginary unit, and is the annihilation (creation) operator associated with the th cavity mode of resonance frequency ; denotes the intrinsic dissipation rate of the th cavity mode, both in the absence of the waveguide. Notice that possible loss and radiation from the mode are both included. Similarly, and denote the annihilation and creation operator for the waveguide mode, respectively. The coefficient describes the coupling between the th cavity mode and the th waveguide. The Heisenberg equations of motion for the cavity resonant mode and the waveguide modes read

(2) (3) Integrating the time-dependent first-order differential equation (3) yields

Here, th waveguide at

is the amplitude . By (2) and (4), we can get

(4) of the

(5)

II. CMT FOR A MULTIMODE CAVITY ARBITRARITY COUPLED TO MULTIPLE CHANNELS Without loss of generality and to keep the analysis simple, we consider the situation where a cavity supporting modes is coupled to waveguides (see Fig. 1). The normalized amplitudes of the modes

Invoking approximation [36], into

, and the first Markov , (5) can be simplified

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Fig. 1. Schematic of a multimode cavity asymmetrically coupled to multiple waveguides.

(6) The input field is . Notice that the second term in the summation accounts for the energy exchange between the th mode and the th mode, which is absent (or negligibly weak) for the isolated cavity in free space. In other words, this intermode coupling term originates from the emission of photon from one mode in the cavity and its recapturing by another mode, mediated strongly via the waveguide channel and slightly via the free-space channels. We stress that direct energy transfer between them is prohibited, yet indirect coupling can be established via near-field interaction with the ambient waveguides or through backscattering of radiation to the free space. Accounting for the energy conservation in the microcavity-waveguide system, one can write (7) where is a complex-valued coefficient that accounts for the direct coupling between the th waveguide to the th waveguide, and represent the output and input field amplitude in the th waveguide. Using (6) and (7) and the input–output geometry configuration, it is easy to obtain the transmission and reflection in all the waveguide ports. Suppose that the coupling from each individual cavity mode is equally coupled to all the surrounding waveguides , i.e., in the symmetry case, (7) can be reduced to

(8) This reduces the dynamic equation for a single multimode stub resonator [37]. While the theoretical formalism is fully general and can be applied to arbitrary multimode cases, much of our attention in the following is focused on the case of two-waveguide and three-mode or two-mode systems, which capture the essential physics originated from the mode radiation couplings and the intermode interactions and energy exchanging. We note that as the coupling constants are

Fig. 2. Spoof LSP multimode resonator coupled to two SIS waveguides. (a) SIS waveguide comprising two counter-facing structure separated by an air gap of height . (b) LSP resonator made of 2-D textured metallic disk. (c) Coupling geometry of two SIS waveguides and the spoof LSP resonator.

physically determined by the spatial and spectral overlap between the modal fields in the waveguide and the resonator, it is usually hard to obtain them from the “first-principle” EM calculations. The present CMT is therefore a phenomenological theory with parameters that need to be extracted via fitting to numerical or experimental data. III. MULTIMODE INTERFERENCE IN SPOOF PLASMONIC WAVEGUIDE-CAVITY SYSTEM To illustrate the multimode coupling dynamics, we choose a two-dimensional (2-D) spoof plasmon waveguide-resonator coupled system as schematically shown in Fig. 2. Note that the physics are basically the same in three-dimensional (3-D) systems of finite thickness as the spoof surface plasmon waves are essentially bounded to the metal surface. Not like plasmonic structures, the spoof plasmon structures are easier to tune and essentially without Joule loss, therefore enabling contribution to with only radiation to the free space. Before discussing the Fano resonance arising from the interactions between the SIS waveguides and the spoof LSP resonator, it is instructive to consider the individual characteristics of each of these two parts. In both cases, we assume that the metal is highly conductive at the frequency of interest and can be simply treated as a PEC, i.e., the dielectric function in the numerical modeling. A. EM Properties of the SIS Waveguide and the Spoof LSP Cavity We firstly focus on the properties of an EM wave propagating in the SIS waveguide. Fig. 2(a) shows the detailed structure: two metallic surfaces are separated by an air gap and periodically corrugated with grooves of width , period , and depth . The geometry structures create artificial boundary conditions at the PEC surfaces with field penetration into the grooves, supporting

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shown here). It is interesting to note that water is characterized by such a refractive index at temperatures below 100 C in the microwave band [40], enabling possible sensing application of our structure when the grooves are filled with water. This provides an easy way to ensure the fundamental and low-order resonant modes having their resonance frequency below the cutoff frequency. B. CMT for the Spoof Plasmonic Waveguide-Cavity System

Fig. 3. Characteristics of the SIS waveguide and the LSP resonator. (a) SIS waveguide dispersion. (b) SCS of the 2-D textured metallic disk. Insert shows the magnified part and the corresponding resonant states.

SSPP with asymptotical frequency at around , where is the groove mode order. The dispersion relation of the SIS waveguide is of similar form to that of a metal–dielectric–metal slot waveguide [22]. By applying the mode expansion and the transfer matrix method, Kats et al. recently presented a close-form dispersion relation of the SIS waveguides [38]. Although there are higher order modes of the SSPPs in the SIS waveguide [22], we only concern the fundamental one in this work. Fig. 3(a) shows the dispersion relation of a 2-D SIS waveguide with mm, mm, mm, and mm. We note that in this length scale, the asymptotical frequency lies at GHz, which could be at THz if the length unit is scaled to a micrometer and the metal still behaves like a PEC. We then consider the 2-D textured metallic disk that sustains the planar LSP resonance [31], [32]. The structured disk is schematically shown in Fig. 2(b). It consists of an infinitely long metallic cylinder of radius mm corrugated with a periodic array. The circumference period is with grooves of parallel walls. The groove depth in the radial direction is and the width . To match the working frequency to the SIS waveguide, the grooves are filled with a dielectric material of refractive index . The transcendental equation of the resonance condition [32] for the individual mode in this resonator is , is the Hankel function of the first kind, where is the mode number, and . Fig. 3(b) shows the scattering cross section (SCS) of the LSP resonator under normal incidence for transverse magnetic polarization . The results are obtained by a full-wave EM solver of the finite-element method (FEM) software [39] that a driven solver was used by impinging a plan wave and the total LSP resonator is surrounded by perfectly matched layers to eliminate the artificial reflections. The SCSs are obtained by integrating the normal scattered Poynting vector on a closed curve that encloses the resonator. The calculations further showed that as the dielectric material of refractive index varies from 7.96 to 8.03, the SCS peak of the LSP structure exhibits obvious blue shift (figure not

Now we consider making a structure by combing the SIS waveguide and the LSP resonator, as shown in Fig. 2(c). In addition to , the geometry parameters of the two parts (i.e., the SIS waveguides and the LSP resonator) can be adjusted separately to ensure that the LSP resonance frequency falls below the cutoff frequency of the SIS fundamental guiding mode. The total gap between the SIS waveguides is mm (approximately a quarter of the operating wavelength 600 mm), and the LSP resonator off-center position denoted by , e.g., represents equal distances to the two waveguides. The length of the SIS waveguide in one side is set as mm. Port type excitation, which is the coming TM-polarized wave propagating along the axis, was launched at the left SIS terminal and the transmission is measured at the opposing port in the right SIS terminal. This complex structure is surrounded by a scattering boundary condition. In all the FEM simulations, the mesh is generated automatically, which in 2-D cases are triangular meshes with resolution small than 0.5 mm. The resonance modes in the LSP resonator are evanescently coupled to the SIS guiding mode. Let us consider input signal at the left waveguide (label with ) and take into account the lowest three modes , , and , the equations of motion are

(9)

(10)

(11) (12) Note that here runs over and representing, respectively, the coupling between the modes and . It is then straightforward to obtain the transmission coefficient (13) The transmission over the total system is defined as , where characterizes the direct coupling

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strength and phase between the left waveguide to the right waveguide, and we would assume approximately for waveguides separated at a distance well below the operating wavelength. In (13), the effective modal amplitude that delivers the photon into the output waveguide reads as (14)–(16), shown at the bottom of this page. In the above equations, , , , , , , , and . C. Numerical Results and Analysis Based on CMT Fig. 4 shows the numerically calculated transmission of the waveguide-resonator coupled system for mm (green line with triangle dots), mm (red line with square dots), and mm (black line with circular dots), respectively. The excitation is launched from the left waveguide labeled as “1.” In the case of , the resonator is of equal distance to the two waveguides, indicating symmetric coupling . Transmission spectra for the case in absence of the LSP resonator (blue long dashed line) and for the case of off-resonance with (pink dashed–dotted line) are superimposed in Fig. 4. In these two cases, the transmission is at the level of , showing that a small amount of incident wave can be directly transferred across the gap. Furthermore, the SCS of the individual LSP resonator is also shown in Fig. 4 (right -axis). It is clearly seen that the LSP resonances, e.g., the dipole mode and quadruple mode, give rise to dramatically enhanced transmission when the LSP is incorporated into the gap of the cut waveguide. More specifically, the transmission profile shows strong Fano-like asymmetric features with the LSP resonance peak appearing at the low-frequency side of the corresponding SCS resonance . We note that for the hexapole resonance at frequency GHz, the SCS spectrum contains no obvious feature due to the weak excitation by the plane wave. However, since the wave is evanescently coupled to the resonator from the waveguide, the excitation efficiency is strongly enhanced and the transmission peaks induced by the three fundamental resonance modes are all visibly significant. The transmission spectrum in Fig. 4 visually has multiple Fano profiles, which are resulted from the interference of microwave transmitted through two paths: 1) direct transfer between the two waveguides and 2) resonant tunneling assisted by the resonant modes. We have used the CMT [see (13)] to fit

Fig. 4. Transmission of the waveguide-resonator system (left -axis) and SCS (right -axis) of the individual LSP resonator. There are three resonant peaks GHz, in the transmission while the SCS spectrum peaks are at GHz and GHz, respectively. Transmissions in absence of (pink the resonator (blue long dashed line) and for a resonator with dashed–dotted line) are also shown.

the numerical results and the curves are very similar, as shown in Fig. 5(a). Notice that the fitted value of agrees quite well with the background transmission (i.e., the case in absence of the resonator). More interestingly, Fig. 5(b) shows the extinction , which, in the spoof case is only contributed by radiation, is unexpectedly large for the quadruple mode. The spectrum of is confirmed by numerical integration of the outgoing power flux (circles in Fig. 5) over the upper and lower boundaries of the gap region. Naively, one would expect more efficient radiation from the dipole resonance than the other two, when the resonator is in free space [41]. However, Fig. 5(b) shows unambiguously that the radiation from the quadruple resonance mode dominates overwhelmingly over the other two. The presence of the two waveguides in the proximity of the resonator must mediate its radiation spectrum, depending on the excitation efficiency of the modes and their modal field symmetry with respect to the geometry configuration. Intuitively, one would perceive that the quadruple mode pattern has two poles pointing to the two waveguides, and the other two poles pointing vertically, permitting strong radiation out of the gap region. This is indeed the truth. Fig. 6 shows the near field for different frequencies as marked in Fig. 5 by “a,” “b,” “c,” “d,” “e,” and “f,” respectively, for the peak and dip positions. Connecting the LSP resonator to the two waveguide

(14) (15) (16)

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Fig. 5. Symmetrically coupled waveguide-LSP resonator mm . (a) FEM calculated transmission (red dots) fitted by the CMT (blue solid line). (b) Reflection (black solid), and extinction (green dashed–dotted) spectrum. Circles are the outgoing power flux integration over the horizontal boundaries of the gap, representing the radiation to free space.

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Fig. 7. Asymmetrically coupled waveguide-LSP resonator with mm. (a) Transmission spectrum fitted by the CMT formula (13). (b) Transmission, reflection, and radiation spectra.

can couple the wave efficiently to waveguide “2” since the wave field are mostly in-phase across the gap, assisted by the strong local field around the LSP resonator. On the contrary, when the frequency is tuned to the Fano dip, for example, at point “b” of GHz, the direct outgoing wave and the resonant amplitude field is out-of-phase [see Fig. 6(b)]. Similarly, the same applies to quadruple and hexapole resonance at GHz [see Fig. 6(c)] and GHz [see Fig. 6(e)]. Quite intuitively, it is seen that at the quadruple resonance the field around the LSP resonator has two “poles” directed right perpendicular to the gap [see Fig. 6(c)]. While at the dipole resonance and the hexapole resonance, the near-field pattern around the LSP resonator does not have any “pole” right perpendicular to the gap. In particular, for the dipole resonance [see Fig. 6(a)], the magnetic fields are well confined in between the two waveguides, yielding relatively small radiation, which is measured by , shown as the green dashed–dotted line in Fig. 5(b). The radiation increases abruptly at the quadrupole resonance and the hexapole resonance, however, it remains more intensive in the former case due to the orthogonal relationship between the mode pattern and the geometry configuration. D. Coupling Coefficients Fig. 6. Field pattern for excitation at different frequencies from the left waveguide. Both (a)–(f) symmetrically and (g)–(j) asymmetrically coupled sys, and (l) the case without the tems. (k) For off-resonance resonator of resonator. The frequency is shown in each panel. Arrows are for the power flux.

has lifted the mode degeneracy and the mod excitation depends on the incoming wave from the SIS waveguide. Fig. 6(a), (c), and (e) corresponds to the resonant peak of the dipole, quadrupole, and hexapole resonances, respectively, whereas Fig. 6(b), (d), and (f) corresponds to the Fano dips. Clearly, when the resonance modes are excited (e.g., at GHz) by the incoming wave from waveguide “1,” they

The previous results are for the case of symmetric coupling where the two waveguides are coupled in equal efficiency for all the resonance modes. However, when the resonator is moved in plane, the coupling coefficient between the three modes to the two waveguides must vary. Fig. 7 presents the results for shifting the LSP resonator horizontally to mm. The results remain largely the same to the symmetric case and can be fitted well by the CMT. Typical near-field patterns are shown in Fig. 6(g)–(j). It is seen that the transmitted field phases are varied, which leads to small changes in the transmission amplitude [see Figs. 5(a) and 7(a)]. Notice that for the off-resonance case [see Fig. 6(k)] and for

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Fig. 8. Two-mode CMT fitting to the transmission spectra for various offcenter distances . (a) Dashed curves are from the FEM calculation and solid curves are the two-mode CMT fitting. For clarity, the curves are shifted vertically by the amount of 0.5 in sequence. Phenomenological coupling coefficients vary as a function of the LSP resonator position for the: (b) fundamental mode and (c) quadruple mode.

the case in absence of the LSP resonator [see Fig. 6(l)], the microwave field simply tunnels from waveguide “1” to waveguide “2” since the total gap is around a quarter of the wavelength. Though the multimode and the three-mode CMT can demonstrate the coherent dynamics in a rather complete form, they contain too much free parameters, which prevents accurate capturing of the relationship between the coupling coefficients and the geometry. As a matter of fact, the hexapole mode coupling coefficients are an order of magnitude lower than those of the quadrupole , which are, in turn, an order of magnitude lower than those of the dipole mode . To illustrate the strong multimode interference processes, we decided to retain the two lower order modes (by setting for ) and do the fitting to the numerical results for frequencies below . Fig. 8(a) shows that the two-mode CMT fitting can indeed reproduce the numerical results more accurately. Very importantly, as the LSP resonator moves towards the waveguide “1,” i.e., as increases from 0 to 24 mm, both the dipole mode and the quadrupole mode induced transmission peaks descend. This is partially due to the mismatching of the mode coupling to waveguides “1” and “2.” Fig. 8(b) shows the variation of the coupling coefficients and associated to the dipole mode, as a function of the displacement . Fig. 8(c) is for the coupling coefficients and associated to the quadrupole mode. Apparently the coupling coefficients associated with the dipole mode are nearly one order of magnitude larger than those associated with the quadruple mode [notice the -axis scale in Fig. 8(b) and (c)]. Furthermore, for one particular resonant mode, as the resonator-waveguide distance varies, the coupling coefficient changes accordingly. More specifically, Fig. 8(b) shows that goes up while descends when the LSP resonator is moved away from the symmetric position to the left (towards waveguide “1”). The same trends are observed in Fig. 8(c) for the quadrupole mode, despite the absolute value. In both figures, the coupling coefficients belonging to the left waveguide increase faster than the coupling coefficients bearing

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to the right waveguide. We note that none of them behaves exponentially as a function of . This may be attributed to the fact that the resonator couples not only to the two waveguides, but also to the free-space radiation channels. In other words, the resonator is in both near- and far-field interactions with its ambient. Besides, the presence of the two waveguides can enhance the energy exchange between the two modes. The CMT we developed already illustrates the underlying mechanism by the intermode coupling term . It is important to remark that for even more accurate and faithful description, the coupling coefficients must be considered as complex valued, and the transmission coefficient , also being complex valued, shall be the fitting target. We note that recently a meromorphic function modeling with singular points in the complex frequency plane has been successfully applied to interpret Fano resonance in plasmonic clusters [42] and the fidelity of the fitting by different models must be quantified as well [43]. IV. SINGLE-MODE CMT ANALYTICAL DESCRIPTION OF THE FANO PROFILE Single-mode CMT analytical description of the Fano profile: though the generic forms of CMT can describe the system in a quite appropriate and suitable way, they cannot provide explicit understanding of the relationship between the Fano feature and the geometry quantities (e.g., the horizontal off-central displacement of the LSP resonator). To gain more insights into the Fano interference effect induced by the cavity mode and its interaction to the waveguide mode, we consider the case where only the leading LSP mode in the spoof resonator is asymmetrically coupled to the two waveguides. The CMT equations then simplify to

(17) (18) (19) where is the resonance amplitude of the leading mode, is the resonant frequency, and is the extrinsic loss rate describing radiation. In the above equations, and are the external leakage rate due to the coupling of the resonance to the two waveguides in the left and the right, and and are the incident and reflected waveguide mode amplitudes, respectively. The reflection and transmission coefficients and are for the beaked SIS waveguide in the absence of the LSP structure. They are both constants with a constraint . The transmission of the system describe by (17)–(19) reads (20) With Fano profile [7]

, (20) transforms to an explicit

(21)

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where (22) Equation (22) represents the asymmetry parameter describing the Fano line shape, which explicitly depends on the geometry parameters, as well as the decay rates , , , and the background transmission coefficient . All of them would crucially depend on the resonator-waveguide gap , and the respective resonant properties. V. CONCLUSION In summary, we have shown that in a multimode cavity, which is coupled both in near- and far-field ways to the ambient, by either radiation to free space or evanescently to nearby waveguides, the canonically orthogonal mode can exchange their energy indirectly via their respective interactions with the ambient. A multimode temporal CMT accounting for such an ingredient has been developed and presented in this work. The theory can be flexibly applied to cavity-waveguide coupling systems and is used to explain multiple Fano profiles in a kind of spoof plasmon waveguide–resonator–waveguide structure. Numerical results by the FEM agree quite well with the theoretical prediction by carefully examining the phenomenological coupling coefficients and accounting appropriately the leading modes. It is worth mentioning that the SSPP associated properties are basically similar in both 2-D and finite-thick 3-D samples [44]. Our results are extendable to finite-thick 3-D systems, which can be readily fabricated by using aluminum foil or a printable circuit board [45]. Although the presented prototype structure works in sub-GHz, our analysis and results can also be useful in GHz, THz, and the optical regime, enabling efficient and accurate modeling for optical antenna design and optical sensing engineering. REFERENCES [1] , A. B. Matsko, Ed., Practical Applications of Microresonators in Optics and Photonics. Boca Raton, FL, USA: CRC Press, 2009. [2] H. A. Haus, Waves and Fields in Optoelectronics. Englewood Cliffs, NJ, USA: Prentice-Hall, 1983. [3] M. Ghulinyan et al., “Inter-mode reactive coupling induced by waveguide-resonator interaction,” Phys. Rev. A, Gen. Phys., vol. 90, pp. 053811-1–053811-5, Jul. 2014. [4] Q. Zhang, J. J. Xiao, X. M. Zhang, D. Han, and L. Gao, “Core-shell structured dielectric-metal circular nanodisk antenna: Gap plasmon assisted magnetic toroid-like cavity modes,” ACS Photon., vol. 2, no. 60, pp. 1–17, 2014. [5] U. Fano, “Effects of configuration interaction on intensities and phase shifts,” Phys. Rev., vol. 124, no. 6, pp. 1866–1878, Dec. 1961. [6] A. E. Miroshnichenko, S. Flach, and Y. S. Kivshar, “Fano resonances in nanoscale structures,” Rev. Mod. Phys, vol. 82, no. 3, pp. 2257–2298, Aug. 2010. [7] B. Luk’yanchuk et al., “The Fano resonance in plasmonic nanostructures and metamaterials,” Nat. Mater., vol. 9, no. 9, pp. 707–715, Sep. 2010. [8] M. Fleischhauer, A. Imamoglu, and J. P. Marangos, “Electromagnetically induced transparency: Optics in coherent media,” Rev. Mod. Phys, vol. 77, no. 2, pp. 633–673, Apr. 2005. [9] C. H. Dong, C. L. Zou, Y. F. Xiao, J. M. Cui, Z. F. Han, and G. C. Guo, “Modified transmission spectrum induced by two-mode interference in a single silica microsphere,” J. Phys. B, At. Mol. Opt. Phys., vol. 42, pp. 215401-1–215401-5, Sep. 2009.

[10] D. Yelin, D. Oron, S. Thiberge, E. Moses, and Y. Silberberg, “Multiphoton plasmon-resonance microscopy,” Opt. Exp., vol. 11, no. 12, pp. 1385–1391, Jun. 2003. [11] X. Piao, S. Yu, S. Koo, K. Lee, and N. Park, “Fano-type spectral asymmetry and its control for plasmonic metal-insulator-metal stub structures,” Opt. Exp., vol. 19, no. 11, pp. 10907–10912, May 2011. [12] Q. Zhang, J. J. Xiao, X. M. Zhang, Y. Yao, and H. Liu, “Reversal of optical binding force by Fano resonance in plasmonic nanorod heterodimer,” Opt. Exp., vol. 21, no. 5, pp. 6601–6608, Mar. 2013. [13] C. L. Zou, F. J. Shu, F. W. Sun, Z. J. Gong, Z. F. Han, and G. C. Guo, “Theory of free space coupling to high-Q whispering gallery modes,” Opt. Exp., vol. 21, no. 8, pp. 9982–9995, Apr. 2013. [14] P. K. Jha et al., “Interacting dark resonances with plasmonic metamolecules,” Appl. Phys. Lett., vol. 105, pp. 111109-1–111109-5, Sep. 2014. [15] W. Suh, Z. Wang, and S. Fan, “Temporal coupled-mode theory and the presence of non-orthogonal modes in lossless multimode cavities,” IEEE J. Quantum. Electron., vol. 40, no. 10, pp. 1511–1518, Oct. 2004. [16] Z. Z. Liu, J. J. Xiao, Q. Zhang, X. M. Zhang, and K. Y. Tao, “Collective dark states controlled transmission in plasmonic slot waveguide with a stub coupled to a cavity dimer,” Plasmonics, vol. 10, no. 5, pp. 1057–1062, Jan. 2015. [17] C. W. Hsu, B. G. DeLacy, S. G. Johnson, J. D. Joannopoulos, and M. Soljačic, “Theoretical criteria for scattering dark states in nanostructured particles,” Nano. Lett., vol. 14, no. 5, pp. 2783–2788, May 2014. [18] J. C. Soric, R. Fleury, A. Monti, A. Toscano, F. Bilotti, and A. Alù, “Controlling scattering and absorption with metamaterial covers,” IEEE Trans. Antennas Propag., vol. 56, no. 2, pp. 416–424, Aug. 2008. [19] H. M. Bernety and A. B. Yakovlev, “Reduction of mutual coupling between neighboring strip dipole antennas using confocal elliptical metasurface cloaks,” IEEE Trans. Antennas Propag., vol. 63, no. 4, pp. 1554–1563, Apr. 2015. [20] Q. Zhang and J. J. Xiao, “Multiple reversals of optical binding force in plasmonic disk-ring nanostructures with dipole-multipole Fano resonances,” Opt. Lett., vol. 38, no. 20, pp. 4240–4243, Oct. 2013. [21] Y. F. Xiao, L. He, J. Zhu, and L. Yang, “Electromagnetically induced transparency-like effect in a single polydimethylsiloxane-coated silica microtoroid,” Appl. Phys. Lett, vol. 94, pp. 231115-1–231115-3, Jun. 2009. [22] B. B. Li et al., “Experimental observation of Fano resonance in a single whispering-gallery microresonator,” Appl. Phys. Lett., vol. 98, pp. 021116-1–021116-3, Jan. 2011. [23] J. Zhou et al., “Transfer matrix’ method for direct and indirect coupling of cascaded cavities in resonator-waveguide systems,” Opt. Commun., vol. 329, pp. 88–91, May 2014. [24] J. S. White et al., “Extraordinary optical absorption through subwavelength slits,” Opt. Lett., vol. 34, no. 5, pp. 686–688, 2009. [25] A. Alù and N. Engheta, “Wireless at the nanoscale: optical interconnects using matched nanoantennas,” Phys. Rev. Lett., vol. 104, pp. 213902-1–213902-4, May 2010. [26] S. Zhang, C. Gu, and H. Xu, “Single nanoparticle couplers for plasmonic waveguides,” Small, vol. 10, no. 21, pp. 4264–4269, Feb. 2014. [27] H. Lu, X. M. Liu, and D. Mao, “Plasmonic analog of electromagnetically induced transparency in multinanoresonator-coupled waveguide systems,” Phys. Rev. A, Gens. Phys., vol. 85, no. , pp. 0538031–053803-7, May 2012. [28] J. B. Pendry, L. Martín-Moreno, and F. J. Garcia-Vidal, “Mimicking surface plasmons with structured surfaces,” Science, vol. 305, no. 5685, pp. 847–848, Aug. 2004. [29] F. J. Garcia-Vidal, L. Martín-Moreno, and J. B. Pendry, “Surfaces with holes in them: New plasmonic metamaterials,” J. Opt. A, Pure Appt. Opt., vol. 7, no. 2, pp. S97–S101, Jan. 2005. [30] I. R. Hopper, B. Tremain, J. A. Dockrey, and A. P. Hibbins, “Massively sub-wavelength guiding of electromagnetic waves,” Sci. Rep., vol. 4, no. 7495, pp. 1–5, Dec. 2014. [31] A. Pors, E. Moreno, L. Martin-Moreno, J. B. Pendry, and F. J. Garcia-Vidal, “Localized spoof plasmons arise while texturing closed surfaces,” Phys. Rev. Lett., vol. 108, pp. 223905-1–223905-5, Jun. 2012. [32] P. A. Huidobro et al., “Magnetic localized surface plasmons,” Phys. Rev. X, vol. 4, pp. 021003-1–021003-7, Apr. 2014. [33] X. Shen, T. J. Cui, D. Martin-Cano, and F. J. Garcia-Vidal, “Conformal surface plasmons propagating on ultrathin and flexible films,” Proc. Nat. Acad. Sci. USA, vol. 110, no. 1, pp. 40–45, Jun. 2013.

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[34] X. Shen and T. J. Cui, “Ultrathin plasmonic metamaterial for spoof localized surface plasmons,” Laser Photon. Rev., vol. 1, pp. 137–145, Jan. 2014. [35] F. Gao, Z. Gao, X. Shi, Z. Yang, X. Lin, and B. Zhang, “Dispersiontunnable designer-plasmonic resonator with enhanced high-order resonances,” Opt. Exp., vol. 23, no. 5, pp. 6896–6902, Mar. 2015. [36] D. F. Walls and G. J. Milburn, Quantum Optics. Berlin, Germany: Springer, 1994. [37] G. Cao, H. Li, Y. Deng, S. Zhan, Z. He, and B. Li, “Plasmon-induced transparency in a single multimode stub resonator,” Opt. Exp., vol. 22, no. 21, pp. 25215–25223, Oct. 2014. [38] M. A. Kats, D. Woolf, R. Blanchard, N. Yu, and F. Capasso, “Spoof plasmon analogue of metal-insulator-metal waveguides,” Opt. Exp., vol. 2, no. 2, pp. 246–255, Jan. 2011. [39] W. B. Zimmerman, Multiphysics Modeling With Finite Element Methods (Series on Stability, Vibration and Control of Systems, Serie), ser. Stability, Vibration, Control Syst.. Singapore: World Sci., 2006. [40] M. V. Rybin, D. S. Filonov, P. A. Belov, Y. S. Kivshar, and M. F. Limonov, “Switching from visibility to invisibility via Fano resonances: Theory and experiment,” Sci. Rep., vol. 5, no. 8774, pp. 1–6, Mar. 2015. [41] J. D. Jackson, Classical Electrodynamics, 3rd ed. New York, NY, USA: Wiley, 1998. [42] S. Bakhti, N. Destouches, and A. V. Tishchenko, “Coupled mode modeling to interpret hybrid modes and Fano resonances in plasmonic systems,” ACS Photon., vol. 2, no. 2, pp. 246–255, Jan. 2015. [43] B. Peng, S. K. Ozdemir, W. Chen, F. Nori, and L. Yang, “What is and what is not electromagnetically induced transparency in whisperinggallery microcavities,” Nat. Commun., vol. 5, no. 5082, pp. 1–32, Oct. 2014. [44] Q. Zhang, J. J. Xiao, D. Han, F. F. Qin, X. M. Zhang, and Y. Yao, “Microwave band gap and cavity mode in spoof–insulator–spoof waveguide with multiscale structred surface,” J. Phys. D, Appl. Phys., vol. 48, Mar. 2015, Art. no. 205103. [45] H. Xiang et al., “Spoof surface plasmon polaritons on ultrathin metal strips with tapered grooves,” Opt. Commun., vol. 356, pp. 59–63, Jul. 2015. Fei Fei Qin is currently working toward the Ph.D. degree at the College of Electronic and Information Engineering, Shenzhen Graduate School, Harbin Institute of Technology, Shenzhen, Guangdong, China. Her research interests are focused on nanophotonics, artificial electromagnetic materials, and microwave antenna.

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Jun Jun Xiao received the B.S. and M.S. degrees in condensed matter physics from Lanzhou University, Lanzhou, China in 1999 and 2002, respectively, and the Ph.D. in physics from the Chinese University of Hong Kong (CUHK), Hong Kong, in 2006. From 2006 to 2007, he was a Research Associate with CUHK. He was then a Visiting Scholar with the Department of Physics, Hong Kong University of Science and Technology, until 2009. He is currently a Professor with the Shenzhen Graduate School, Harbin Institute of Technology, Shenzhen, Guangdong, China, where he has been studying nanophotonics, metamaterials, and plasmonics. He has authored or coauthored over 60 papers in various international journals. He coauthored a chapter in Plasmons: Theory and Applications (Nova Sci., 2011). His research interests include nanoantenna, photonics, and metamaterials.

Zhen Zhen Liu is currently working toward the Ph.D. degree at the College of Electronic and Information Engineering, Shenzhen Graduate School, Harbin Institute of Technology, Shenzhen, Guangdong, China. His research interests include metamaterials, electromagnetic modeling, and numerical simulation.

Qiang Zhang is currently working toward the Ph.D. degree at the College of Electronic and Information Engineering, Shenzhen Graduate School, Harbin Institute of Technology, Shenzhen, Guangdong, China. His research interests include metamaterials, nanophotonics, and plasmonics.

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Dynamical Equivalent Circuit for 1-D Periodic Compound Gratings Carlos Molero, Raúl Rodríguez-Berral, Francisco Mesa, Fellow, IEEE, and Francisco Medina, Fellow, IEEE

Abstract—Metallic compound gratings are studied in this work by means of an analytical equivalent circuit approach in order to obtain its transmission and reflection properties when illuminated by a TM-polarized plane wave. A compound grating consists of the periodic repetition of a finite number of slits carved out of a thick metal slab (reflection grating) or connecting two separated open regions through groups of slits in the metal slab (transmission grating). The equivalent circuit is rigorously obtained starting from a simplified version of the integral equation for the electric field at the slits apertures. That equivalent circuit involves transmission-line sections that account for the fundamental and lowest order diffracted modes (which does give the “dynamical” nature to the present equivalent circuit), and lumped components to model the effect of all the higher order diffracted modes. All the relevant and complex features of the spectra can be satisfactorily explained in terms of the topology and characteristics of the equivalent circuit. In contrast with some previously reported circuit models, all the dynamical and quasi-static circuit elements are analytically and explicitly obtained in terms of the geometric and electrical parameters of the grating. The accuracy of the approximate circuit model is very good over a very wide band, as it is demonstrated by comparison with full-wave data computed with commercial electromagnetic solvers. Index Terms—Compound gratings, electromagnetic modeling, equivalent circuits, periodic structures, scattering problems.

I. INTRODUCTION

A

LTHOUGH THE study of the optical and electromagnetic properties of periodically structured metallic surfaces has a long tradition [1]–[4], the interest on the subject was recently spurred by the discovery of the extraordinary optical transmission (EOT) at the end of the 1990s [5]. Since then, hundreds of papers have been devoted to the explanation of the physical grounds of such phenomenon and to the study of a variety of situations where some exotic behaviors can be observed. Several Manuscript received September 27, 2015; revised January 19, 2016; accepted February 12, 2016. This work was supported by the Spanish Ministerio de Economía y Competitividad and European Union FEDER funds under Project TEC2013-41913-P and by the Spanish Consejería de Innovación, Ciencia y Empresa, Junta de Andalucía under Project P12-TIC-1435. C. Molero, R. Rodríguez-Berral, and F. Mesa are with the Microwaves Group, Department of Applied Physics 1, ETS de Ingeniería Informática, University of Sevilla, 41012 Seville, Spain (e-mail: [email protected]; [email protected]; [email protected]). F. Medina is with the Faculty of Physics, Department of Electronics and Electromagnetism, University of Sevilla, 41012 Seville, Spain (e-mail: medina@us. es). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2531663

authoritative papers have been published reporting comprehensive and exhaustive reviews about this topic [6]–[9]. Most of the material published during the last 15 years deals with 2-D arrays of holes in metal or dielectric screens. However, the study of the properties of 1-D periodic systems (such as arrays of narrow slits or strips in metal screens) has also been carried out in the frame of the analysis of EOT phenomena [10], [11]. Indeed, extraordinary transmission through free-standing infinite arrays of closely spaced metallic bars can be appreciated in the transmission curves published in a couple of Ukrainian papers [12], [13] almost 50 years ago. In spite of this long interest, the study of 1-D periodic gratings is an attractive research topic even today [14]–[26]. Roughly speaking, EOT and other mechanisms of enhanced transmission (such as Fabry–Pérot (FP) resonances occurring in 1-D periodic distributions of slits in thick metal gratings) have been linked to the interaction of impinging uniform planar waves with the so-called spoof (or designer) plasmons [27], [28], which basically are surface waves supported by periodically structured surfaces (for the 1-D periodic case the reader can be referred to the well-known Collin textbook on guided waves [29]). This point of view directly connects the transmission or reflection spectra with the dispersion diagrams of the surface/leaky modes. However, the obtaining of these dispersion diagrams is generally more cumbersome than directly computing the transmission or reflection curves. Fortunately, at least for frequencies well below the optical regime (when metals can be modeled as perfect or quasi-perfect conductors), an alternative model was proposed some years ago leading to a circuit-like description that explains the measured or calculated enhanced transmissivities [30]. The methodology originally introduced in [30] was later applied to a number of periodic structures of interest in the fields of optics (metal gratings) and microwave technology (frequency-selective surfaces, artificial magnetic conductors, and so on). Some instances of this research can be found in [14], [16], and [31]–[35], and an interesting overview focused on frequency-selective surfaces has recently been reported in [36]. Metallic compound gratings are interesting examples of systems that have attracted the attention of researchers in the past [12], [13], [37] and more recently in [38]–[45]. The interest on this kind of structures mainly lies on their rich-full electrical responses. The cross sections of these 1-D periodic structures are sketched in Fig. 1(a) and 1(b) for the reflection- and transmission-type versions, respectively. They exhibit extremely narrowband phase resonances due to the interactions between neighbor slits, which are accompanied by a strong magnetic field enhancement at the apertures [46]–[48]

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Fig. 1. Cross sections of the type of structures analyzed in this paper. (a) Reflection compound grating and (b) transmission compound grating. The groups of slits are periodically repeated along the vertical direction. The slits might be different in width, depth, and filling, but each unit-cell group must have an horizontal symmetry plane.

that depend on the groove depth and size and the distance between cavities. During the last few years, accurate circuit models for the simplest case involving a single slit per period have been developed in [14] and [49]–[51]. Those models incorporate dynamical effects in such a way that the extraordinary transmission and the diffraction regimes are taken into account very accurately. However, to the authors’ knowledge, no dynamical circuit model has been proposed for the more interesting case of compound grating involving three or more slits per period [41]. A quasi-static analytical circuit model was proposed by some of the authors in [14]. However, the derivation of that circuit made use of a rather heuristic approach that proposed a network of edge capacitors to approximately incorporate the interactions (through diffracted fields) between the transmission lines that modeled the slits in the unit cell. These interactions were shown to be essential to understand the behavior of the structure, especially to explain the appearance of deep narrowband transmission dips inside the FP transmission bands. Those dips had been explained before in terms of the so-called phase resonances [41]. Due to the quasi-static nature of the equivalent circuit in [14], our results were expected to be accurate provided the transmission dips took place at frequencies well below the onset of the diffraction regime (marked by the first Rayleigh–Wood (RW)’s anomaly frequency point). Actually, the model qualitatively predicted the existence of the transmission dips, but its quantitative results worsen considerably at frequencies relatively close to the onset of such a regime. Obviously, the quasi-static model could not take into account the operation of the structure beyond the first RW anomaly. Interestingly, reflection-like compound gratings exhibit their most relevant effects (specular reflection points associated with the phase resonances) within the diffraction regime [38], [39], i.e., at frequencies above the onset of the first RW anomaly. The analytical model proposed in [14] was then meaningless to explain the most interesting properties of the compound reflection gratings. The purpose of this paper is to improve the circuit model presented in [14] so as to take into account the dynamical high-frequency effects. The details of the derivation of

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Fig. 2. (a) Example of a three-grooves per period reflection structure. This is the simplest symmetrical compound grating exhibiting phase resonances under normal TM incidence conditions. (b) Half unit cell bounded by virtual electric is the groove depth of the th cavity walls. The period of the structure is ; ; is the distance from the horizontal symmetry plane to the center is the slit width; are the relative permittivities of the of the side slits; media filling the slits; is the conductivity of the metal.

the dynamic circuit model using an ab initio approach are presented in Section II. Apart from making it possible to explore the electrical response within the diffraction regime, the enhanced model will yield more accurate results below the diffraction regime, including extraordinary transmission effects for the compound grating case that were not accounted for by the quasistatic model in [14]. In particular, the interesting results reported in [38] and [39] can now be explained by the analytical model. Several numerical studies confirming the suitability of the proposed model are provided in Section III. Note that all the electrical parameters appearing in the proposed circuit model are analytically derived, in contrast with the calculation of the edge capacitances in [14], which were numerically computed using a finite-element Laplace’s solver. The accuracy of the results obtained with our circuit model have been systematically checked against numerical data generated with a commercial full-wave solver or against experimental results, when available. II. DERIVATION OF THE CIRCUIT MODEL Let us consider a 1-D compound grating with a symmetrical unit cell composed by three slits per period. An example of a reflection grating with these characteristics is sketched in Fig. 2(a). This is the simplest symmetrical 1-D compound grating exhibiting phase resonances under normal incidence [14], [41]. The structure is illuminated with a plane wave at normal incidence and with its electric field polarized along the -direction (perpendicular to the slits). As a consequence of the invariance along the -direction and the polarization of the incident wave, only TM fields are present. (The TE problem could have been considered by following very similar lines. Actually this TE problem was treated in [49] for simple gratings, but it has no major interest in the context of the present study of compound gratings). Due to the periodicity and symmetry of the structure, the analysis can be restricted to the half unit-cell problem depicted in Fig. 2(b). The TEM incident wave can be considered to propagate along a parallel-plate waveguide bounded by virtual electric walls, which can be modeled as a transmission line whose characteristic admittance ( to ratio) per unit length in the -direction is given by

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the reflection coefficient for the impinging zeroth-order wave, and (6) (7) (8) being the th mode cutoff wavenumber, the with free-space wavenumber, is the wavenumber of the th TM mode, and is its wave admittance. In particular, (9) Fig. 3. (a) Generalized waveguide discontinuity problem associated with the half unit cell. (b) Circuit model of the discontinuity. The goal is to derive the topology of the equivalent circuit that models the discontinuity with analytical expressions for all of its parameters.

Similarly, the fields in the slits at could be represented using a modal expansion in terms of the corresponding parallel-plate waveguide modes. However, since the slits are narrow in comparison with the working wavelength, we only take into account the fundamental TEM mode, namely, (10)

(1) (11) with being the intrinsic impedance of free space. The two slits are also parallel-plate waveguides, which can similarly be modeled by two TEM transmission lines with characteristic admittances (2)

where (12) is the intrinsic admittance of the medium inside slit . Note that (13)

(3) Our first goal is to derive a circuit model for the discontinuity that couples the input line to the two output slit transmission lines, as illustrated in Fig. 3. This derivation is presented in Section II-A. Sections II-B and II-C then show the complete models for both the reflection and transmission compound gratings based on the previously derived discontinuity model. For simplicity, the structures are considered lossless in the previous analyses, and the effect of losses in the circuit parameters are introduced in Section II-D. A. Circuit Model for the Generalized Waveguide Discontinuity The tangential (to the screen) components of the fields at the left of the discontinuity can be expanded in terms of the parallel-plate waveguide modes in the following way: (4) (5) where all the terms have been normalized to the amplitude of the is the th modal coefficient, represents impinging wave,

To proceed with the derivation, the aperture field at the disconis assumed to have the following form: tinuity plane (14) where the frequency and the spatial dependence of the fields being the proposed field pattern at are factorized with the th slit aperture. This implies that the spatial field profiles at the apertures are considered independent of frequency, although their complex amplitudes and may vary strongly with frequency. As will be discussed later, this approximation is very accurate for electrically narrow slits. Moreover, it can be checked that the effect of a slight variation of the aperture field profile does not have a significant effect on the transmission/reflection behavior of the structure due to the variational nature of the problem. In this work, the field at the apertures is assumed to be uniform, in slit

elsewhere

(15)

which is consistent with the fact that only the fundamental TEM mode is considered inside the slits. Other aperture field profiles that took into account the correct edge behavior at the metal corners could have been employed, but, in our experience, the differences in the final results are almost negligible (as a general

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qualitative estimate of the limit of validity of this approximation, it has been found that the model provides reliable results for ). The and amplitudes of the field profiles can readily be related to the coefficients of the modal expansion by making use of standard Fourier analysis. Thus, projecting (4) and (14) over the modal profiles in the half unit-cell problem we have

Fig. 4. Topology of the circuit model derived for the discontinuity that couples the impinging wave (input line) to the slit transmission lines.

and where the

current, given by (28)

(16)

is the current flowing into the circuit at the input port. Similarly, using (23) we can obtain

from which (17) (18) where with from (10)–(14) it is clear that

(29) with (30)

. Also, (19)

We can now use (21) to eliminate from (29) to obtain

(20)

from (25), as well as (31)

which allow us to rewrite (17) as

(32) (21)

is the voltage drop at the input port of the equivalent where circuit in Fig. 3(b) and is the voltage drop at the output port corresponding to slit . The next step in the derivation is to impose the continuity of the power flux through the slit apertures. Due to the uniform electric field profile assumed at the apertures, it reduces to require the continuity of the magnetic field in weak (integral) form (22) (23) Introducing (5) and (10) into (22) yields (24) Using (18), (9) and (13), this last equation can be rewritten as (25) with (26) (27)

where (33) A closer inspection of (31) and (32) already reveals the actual topology of the equivalent circuit. These equations tell us that the current flowing into the circuit follows two paths. One portion of the current flows through the admittance with a total voltage drop . The remaining current flows through the parallel connection of the admittance and the transmission line corresponding to slit 1 (with voltage drop ), which is series connected to the parallel connection of the admittance and the second slit line (voltage drop with ). The corresponding circuit topology is shown in Fig. 4. As a consistency check, (21), (25), and (29) can be combined to find the ratio , which corresponds to the equivalent load admittance, , met by the impinging wave. Thus, after some algebraic manipulations, can be expressed as (34) which is fully consistent with the circuit topology in Fig. 4. A similar derivation can be carried out for a compound grating having two different slits per period, and also for a structure with four slits per period distributed symmetrically in the unit cell. Clearly, the unit-cell and half unit-cell problems corresponding to these two latter structures are very similar to the case treated in detail above, with two output slit waveguides. Hence, the topology of their equivalent circuits would be the same as the

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one shown in Fig. 4 with only minor differences in the expressions of the circuit admittances, which are explicitly reported in Appendix A. Although all the circuit parameters are obtained in analytical form, the expressions in (26), (27), and (30) involve infinite series, which is neither convenient from a computational point of view, nor to gain physical insight from the model. Following the guidelines proposed in [16], this drawback can be overcome by considering separately the contribution of the lowand high-order modes to the circuit parameters, as explained next. For evanescent modes (high-order modes), the modal admittances in (8) are imaginary and can be written as (35) where is the cutoff angular frequency of the th mode ( is the speed of light in free space). For those modes whose cutoff frequency is significantly above the frequency range of interest, it is found that and, therefore, their contribution to the equivalent circuit admittances can be well approximated as a frequency-independent capacitance . Assuming that this approximation is valid for modes with order higher than a given , the admittances in (26), (27), and (30) can thus be split into the following two contributions: (36) admittances represent the dynamical where the low-order (i.e., with the complete nonlinear frequency dependence) contribution of the first modes to the infinite series, and the capacitances are given by (37) (38) (39) According to (33), it is apparent that this decomposition translates directly to the admittances in the model, namely, (40) with (41) dynamical admittances. The and a similar relation for the resulting equivalent circuit is represented in Fig. 5. In regards to the value of , our experience says that can often be chosen as the number of high-order propagative modes at the highest frequency of interest. However, as a general criterion for the systematic application of the model, it is advised to incorporate also the first evanescent mode into the low-order dynamical admittances. According to this general criterion, we will take when working below the onset of the first

5

Fig. 5. Circuit model in Fig. 4, but now showing the separate contribution of the low-order (lo), i.e., propagative or close to cutoff, modes and the frequency-independent capacitances that incorporate the global contribution of all the remaining high-order evanescent modes.

higher order mode (nondiffraction regime), for frequencies within the first diffraction order regime (the first higher order mode is propagative, but the second is still evanescent), and so on. It is important to recall that the values of the capacitances involved in the proposed model are independent of frequency. Therefore, when performing a frequency sweep in order to obtain the transmission/reflection spectrum of the structure in a given frequency range, the computation of the infinite series is carried out only once. If desired, the numerical series can be quickly computed using the methods reported, for instance, in [29, App. A]. The above considerations certainly makes the proposed dynamical equivalent circuit very efficient from a computational point of view. Here it is interesting to point out that, for frequencies well below the onset of the first grating lobe, all the higher order modes can actually be incorporated into the capacitances (which is equivalent to take ). It leads to an equivalent circuit with all its lumped parameters being frequency-independent capacitances. In this way we recover the quasi-static capacitive network proposed in [14] by some of the authors. However, it should be noted that [14] did not provide any derivation of the circuit model, but rather a heuristic proposal where the values of the capacitances had to be extracted from an external quasi-static and relatively complex numerical calculation. In contrast, a rigorous derivation is now given, which results in analytical expressions for all the circuit parameters. Moreover, the model derived here is easily applicable to high frequencies well beyond the diffraction limit thanks to the fact that the expressions found for the circuit parameters incorporate analytically the dynamical frequency dependence of the higher order modes as they approach (and eventually exceed) their cutoff frequencies. When working within the diffraction regime, the modal admittances of the propagative higher order modes is real and can be written as (42) In consequence, the contributions of each propagative higher order mode to the admittances in the equivalent circuit are frequency-dependent resistances, and the power dissipated in these resistances can be interpreted as the power transferred to the corresponding grating lobe. When the operation frequency is below the onset of the first grating lobe, although not far from this limit, all the lumped admittances are purely imaginary, but the equivalent capacitors exhibit a frequency dependence that is essential to explain extraordinary transmission effects. The use of purely

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Fig. 6. Complete circuit model for a reflection compound grating such as that in Fig. 2.

quasi-static values for those capacitors [14] cannot accurately account for the behavior of the compound grating at frequencies close to the first RW anomaly.

Fig. 7. Sketch of a transmission compound grating with three slits per period distributed symmetrically in the unit cell. The structure is symmetric with respect to the vertical middle plane.

B. Equivalent-Circuit Model for Reflection Structures Once the equivalent circuit of the discontinuity that couples the impinging wave to the slits is known, the complete models for a reflection structure as that sketched in Fig. 2 can be obtained quite straightforwardly after incorporating the termination of the slits into the model. This is achieved by simply placing a short-circuit termination at the corresponding distance from the discontinuity in each slit transmission line, as shown in Fig. 6. The equivalent load admittance met by the impinging wave is then given by

(43) is the input admittance to the short-circuited length where of transmission line corresponding to slit ; namely, (44) with

interpretation of that model is not straightforward and it will not be considered in this paper. C. Equivalent-Circuit Model for Transmission Structures For the case of a transmission grating such as that sketched in Fig. 7, it is possible to take advantage of the symmetry of the structure with respect to the vertical middle plane of the screen to decompose the problem into even- and odd-excitation (with respect to the middle plane) half problems. For the even excitation case, the middle plane behaves as a virtual magnetic wall. This magnetic-wall condition at the middle of the screen translates into open-circuit terminations of the slit transmission lines at a distance from the discontinuity ( is the screen thickness). For the odd excitation case, the middle plane behaves as a virtual electric wall corresponding to short-circuit terminations. Taking into account these considerations, the circuit models for the even- and odd-excitation half problems are depicted in Fig. 8. The equivalent load admittance for the even/odd excitation circuits, , is thus given by (43), after replacing the input admittances with the following ones corresponding to the circuits in Fig. 8:

(45)

even excitation

being the wavenumber of the th slit TEM mode. The reflection coefficient is finally obtained using standard transmission-line theory as

odd excitation.

(46) At this point, it is worth mentioning that the previous derivations have been carried out assuming normal incidence. The consideration of oblique incidence has some relevant consequences. Even though a similar analytical description with compact and simple expressions for the involved admittances can be derived, it turns out that a circuit topology like that in Fig. 4 could not account for the obtained linear relations between the relevant electrical quantities. Another equivalent circuit could still be drawn if voltage-controlled current sources were used (the authors have verified that this model for oblique incidence fulfills fundamental requirements such as power conservation and reciprocity). However, the physical

(47)

The reflection coefficients for the even/odd excitations half problems are then computed from (48) Finally, the reflection and transmission coefficients for the complete structure are obtained as (49) (50) D. Introduction of Losses Material losses are separately considered (as usual) as dielectric losses in the media filling the slits and ohmic losses in

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Fig. 9. Sketch of the circuit model for a lossy reflection grating, showing the complex load admittances at the termination of the slit lines.

Fig. 8. Circuit models for the: (a) even and (b) odd excitation of the transmission structure in Fig. 7. The models differ in the open/short-circuit terminations , which correspond to the middle of the slit transmission lines at a distance plane behaving as a virtual magnetic/electric wall.

the metallic screen. The dielectric losses are accounted for by simply taking their corresponding complex-valued permittivities

are introduced in the model just by replacing and with and in (47). In their corresponding complex values the case of a reflection grating, the losses at the bottom wall of the slits can also be accounted for by terminating the slit transmission line with imperfect short loads, as sketched in Fig. 9. Including these loads is important because high current density levels can appear in the short-circuit termination of the slits at resonance. Under strong skin effect, the values of the load admittances are given by (55) where

(51)

(56)

where is the dielectric loss tangent of the medium inside slit . From a practical point of view, dielectric losses are rigorously incorporated in the model by introducing the complex permittivities into the expressions of the slit characteristic admittances (2) and (3), and wavenumbers (45). Although high-conductivity metals behave almost as perfect conductors at microwave frequencies, ohmic losses may be significant at the frequencies of interest when resonances appear. In order to incorporate ohmic losses in the present circuit model, the basic ideas in [33] can similarly be applied here. In brief, the slits are now considered lossy parallel-plate waveguides with complex wavenumbers, which, under the good conductor approximation and strong skin effect conditions, are given by

is the surface impedance of the metal. In consequence, the input admittances in (44) have to be replaced with

(52) is the wavenumber for the lossless structure and is the skin penetration depth into the metallic walls ( is the screen conductivity). The characteristic admittances of the slit transmission lines are then given by where

(53)

(57) It should be pointed out that the above considerations take into account ohmic losses in all the slit walls, but not in the metallic surfaces out of the slits. This effect could be approximately introduced by adding appropriate resistors. However, as already mentioned above, this contribution can be neglected for good conductors (e.g., metals at microwave frequencies) since ohmic losses are significant only under specific resonance conditions where most of the power is dissipated inside the slits. As a final comment it should be noted that, even though the analytical developments in this paper have been carried out for the case of three slits per period, the procedure can easily be extended to more complex structures having a higher number of slits per period. Details for a five (or six) slits per cell are given in Appendix B. Once again, an analytical circuit is obtained, although with a more cumbersome topology. Also, one example involving a structure with five slits per period has been included in the results section together with the sketch of the associated equivalent circuit in Appendix B.

with III. NUMERICAL AND ANALYTICAL RESULTS (54) being the complex value of the wave admittance of the fundamental mode in slit . For a transmission grating, ohmic losses

This section presents some results to check the validity and accuracy of the proposed dynamical model for compound gratings as well as the advantages of this model over the previously reported quasi-static version [14].

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match the HFSS results within the diffraction region . The above results then show that the dynamical circuit model is advantageous when used at relatively high frequencies to characterize transmission-like compound gratings, and it is indispensable for frequencies around and above the first RW anomaly. In particular, the quasi-static model cannot account for the existence of RW anomalies, as well as the extraordinary transmission phenomenon. Actually, the quasi-static model for compound structures [14] is useful only for the modeling of FP-like resonances. Note that the nature of extraordinary transmission peaks is completely different, being related to the periodicity of the structure rather than the thickness of the metal slab [6], [19]. Fig. 10. Comparison of the transmission coefficients (magnitude) computed with HFSS (red solid line) with the quasi-static [14] (old model) approximation (black dashed line) and with the dynamical circuit proposed in this paper (blue circles). The considered structure is the three slits per period compound grating mm; metal slab thickness, analyzed in [14, Fig. 5]. Dimensions: period, mm, mm, and separation between the centers of the slits of 1.6 mm.

A. Compound Transmission Gratings As a first example, the transmission-like compound gratings analyzed in [14, Fig. 5] are considered. In that paper it was shown that the quasi-static model was suitable to explain the existence of narrow transmission dips inside the FP transmission bands for compound gratings based on groups of three or more slits per period (normal incidence case). This phenomenon is closely related to the so-called classical electromagnetically induced transparency. In [14, Fig. 5], it could be seen that the quantitative agreement between the heuristic circuit model predictions and full-wave simulations (HFSS) was quite good for the FP resonance occurring at frequencies for which where is the free-space wavelength. However, the quantitative agreement significantly deteriorates as the operation frequency approaches the onset of the diffraction regime . A detailed exploration of this frequency range for the three slits per period structure in [14, Fig. 5] is now shown in Fig. 10. In this figure, numerical (HFSS) results are compared with the predictions of the quasi-static model [14] (old model) and with the dynamical model introduced in this paper. From the figure it is clear that the quasi-static model still predicts the existence of the transmission dip in the middle of the FP resonance , but its quantitative accuracy is very poor. In contrast, the results obtained with the dynamical model are indistinguishable from numerical data. This good matching is caused by the incorporation of the frequency-dependent behavior of the capacitances in the model, which is quite relevant in that frequency region. These capacitances exhibit a singular behavior around the RW frequency , in such a way that an extraordinary transmission peak followed by a Rayleigh transmission zero (Fano-like resonance) is predicted. This fact is in perfect agreement with the numerical calculation (see region around in Fig. 10), but it is completely lost by the quasi-static model. The results provided by the quasi-static model above the diffraction threshold are completely meaningless, while the data computed with the new dynamical model perfectly

B. Compound Reflection Gratings The case of reflection gratings is of special interest in the context of this paper because their most interesting properties appear in the diffraction regime. For lossless structures within the sub-diffraction regime, nothing relevant is expected in the magnitude of the reflection coefficient although its phase experiences fast variations around certain frequency points. In this sub-diffraction regime, the proposed dynamical model substitutes the static capacitors of the heuristic model [14] by other suitable capacitors whose static capacitances are not the ones given by the corresponding solution of Laplace’s equation. The new static capacitors account for the capacitive effects linked to high (enough)-order evanescent TM modes. If the operation frequency is sufficiently close to the onset of any high-order mode, the corresponding previously taken static capacitor should now incorporate a frequency-dependent contribution associated with the involved TM mode. This contribution is singular at cutoff and explains, in the frame of the circuit model, the observation of perfect specular reflection at the RW anomaly frequency points. (Specular reflection is the reflection corresponding to the zeroth-order impinging mode according to the terminology of the equivalent waveguide problem used in this paper.) Note that RW anomalies of the grating correspond to the onset of TM modes in the waveguide model. Thus, perfect specular reflection at RW anomalies is trivially explained, in the frame of the circuit model, by the singular behavior of the frequencydependent capacitors. Moreover, the model also accounts for the transfer of power to the successive diffraction orders by means of frequency-dependent conductances (resistances) that are shunt connected to the capacitors. For lossless conductors and below the onset of the first grating lobe, it is obvious that the magnitude of the specular reflection coefficient must be unity. However, above the first RW frequency, the specular reflection coefficient drastically drops because a significant part of the impinging power is transferred to nonspecular grating lobes. This is what happens with simple gratings (one slit per period) in all the frequency span between any two successive RW points. However, in the case of compound gratings, narrow peaks of perfect specular reflection have been reported at some frequency points between RW anomalies [38], [39]. These peaks were attributed to the existence of phase resonance phenomena. Our circuit model can also provide a simple explanation to this effect. In the case of a lossless system involving three slits per period, the pertinent equivalent circuit is the one in Fig. 6. The

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which was obtained using a mode-matching scheme. Note that a perfect specular reflection peak appears at about . This peak is associated with the existence of a zero of the real part of the equivalent admittance [see (43)] loading the transmission line that represents the impinging uniform plane wave. This zero always appears in the range of frequencies defined by the resonances of the individual resonators composed by the short-circuited slits with their associated external edge capacitances. These resonances are marked in Fig. 11(c) with circles and correspond to the points where the imaginary parts of the overall admittances (dashed lines) associated with slits 1 and 2 are null. The real part of (43) is represented in the same figure as a solid line. It can be observed that this quantity vanishes at around . Therefore, at certain frequency point, all the impinging power is specularly reflected and no transfer of power to grating lobes is allowed, as it was numerically predicted in [38]. Our circuit model provides an analytical explanation for this fact. C. Ohmic Losses In the previous examples, perfect electric conductors have been assumed. However, our model can also deal with lossy materials (metal and dielectric). Fig. 12 shows the magnitude and phase of the reflection coefficient of the structure studied in Fig. 11, but including metal losses (aluminum is considered in this example). Note that normalized frequency values should not be used in this case. A specific choice has been done for the dimensions (maintaining their relative values) and thus a specific frequency range must be explored. It can be appreciated that circuit-model and numerical (HFSS) results agree very well over the whole analyzed frequency band. As can be observed in Fig. 12(a), the specular reflection peak is greatly affected by metal losses (the magnitude of is now about 0.84 instead of 1). A small transmission dip in the magnitude of can also be recognized close to the onset of the diffraction regime. This dip is related to both phase resonance and extraordinary transmission and it is again accurately reproduced with our dynamical circuit model. In this example the phase of the reflection coefficient has also been plotted in Fig. 12(b) to show the good performance of our model even for phase calculations. D. Structures With Five Slits Per Period Fig. 11. (a) Magnitude of (specular efficiency) for the three slits per period compound reflection grating considered in [38, Fig. 2(b)] (see inset for , , . unit cell). Normalized dimensions: (b) Transmission to the first diffraction order (magnitude). (c) Dashed lines: imaginary parts of the admittances associated with the resonant circuits involved in the modeling of the two independent slits. Solid line: real part of the overall equivalent admittance loading the input transmission line [see (43)].

results provided by HFSS and our dynamical circuit model for the specular efficiency pattern of the three-slits per period reflection compound grating analyzed in [38, Fig. 2(b)] are shown in Fig. 11(a). The transmission from the impinging wave to the first diffraction order is plot in Fig. 11(b). Normalized frequency is used as in [38]. Very good agreement between analytical and numerical data can be observed. Similar good agreement has been verified with the curve reported in [38, Fig. 2(b)],

Although the analytical details in Section II have been presented for the simplest case exhibiting exotic behavior under normal incidence conditions (three symmetrically placed slits per period), the procedure employed in this paper can easily be extended to any number of slits. Thus, the analytical model described in Appendix B has been used to generate the data reported in [39, Fig. 2(a)] (five slits per period). These data are shown in Fig. 13(a) (note that normalized frequencies are used, as in [39]). Agreement with full-wave computations is very good and the two expected specular reflection points are reproduced very accurately. The reason for the existence of those points can be appreciated in Fig. 13(b), where two zeros of the real part of the loading equivalent admittance can be clearly noticed. Note that those zeros are again around the resonance region of the three slits of the irreducible unit cell. The equivalent

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Fig. 12. (a) Magnitude of the reflection coefficient versus frequency. (b) Phase of the reflection coefficient versus frequency. Structure parameters: mm, mm, mm, mm, mm, , Al S/m.

circuit allows us to predict again the existence of such zeros and the perfect specular reflection peaks. E. Comparison With Experimental Results As a final example, the compound grating with experimental data reported in [42] is considered in Fig. 14. This figure clearly shows that our model matches the measured transmission coefficients very accurately. For the given values of the groove depth, the two explored frequency regions plotted in Fig. 14(a) and (b) correspond to FP-like resonances, which could have been reasonably reproduced with the quasi-static model reported in [14]. Nevertheless, the dynamical-circuit results shown in these figures show a better quantitative matching with the additional advantage that the static capacitances used in the model have been generated using analytical expressions rather than running a finite-element Laplace’s solver [14]. Although all the examples reported in this section have involved air-filled slits, many other structures with dielectric-filled slits have also been simulated with HFSS and compared with our proposed model showing similar good agreement. These examples have not been included to save space and only examples showing interesting phenomena have been shown. To have an idea about the computational savings

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Fig. 13. Results obtained for a compound grating with five identical slits per period. (a) Magnitude of the reflection coefficient and (b) imaginary parts (dashed lines) of the admittances of the individual independent slits and real part (solid line) of the admittance loading the input transmission line. Dimensions: mm, mm, mm, mm.

achieved with the use of the analytical approach, it must be said that HFSS computations required from several minutes to a couple of hours, depending on the complexity of the structure and the number of points employed to draw a given curve. The analytical CPU times were always below 1s in the same computer platform. IV. CONCLUSION An equivalent-circuit model has been rigorously deduced for compound gratings with an arbitrary number of slits per unit cell when illuminated with a TM-polarized normally impinging uniform plane wave. The equivalent circuit incorporates dynamical features that were absent in previous circuit models reported in the literature. All the parameters of the newly proposed circuit model can easily be computed using analytical expressions in such a way that a very low numerical effort is required. Moreover, the equivalent circuit provides an alternative easy way to understand the complex behavior of compound gratings working both in transmission and in reflection. Material losses have also been added to the model in a straightforward way. Analytical data agree very well with HFSS simulations and with previously reported measured results.

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Fig. 15. (a) Half unit-cell problem for a reflection grating with four slits per period, distributed symmetrically within the unit cell. (b) Unit cell with two different slits. Due to the absence of symmetry, in this case the boundary walls of the cell are not virtual electric walls, but periodic boundary conditions.

Fig. 16. (a) Generalized waveguide discontinuity problem associated with the half unit cell of a structure with five slits per period and symmetric unit cell.

since the irreducible problem is the complete unit cell. As for the admittances that define the elements of the equivalent circuit, according to (33) it is obtained

(60) Fig. 14. Transmissivitty versus frequency for two different FP bands of the compound grating experimentally studied in [42]. The red solid line corresponds to the analytical results and the circles are samples of the experimental results mm, mm, in [42]. Structure parameters: mm, mm, , S/m.

(61) for the symmetrical case in Fig. 15(a), and

APPENDIX A The half unit-cell problem for a structure with four slits symmetrically distributed within the unit cell is shown in Fig. 15(a), whereas Fig. 15(b) shows the unit cell for a structure with two different slits per period. In both cases, there are two slits in the irreducible (half) unit-cell problem. Thus, the topology of the circuit model for the discontinuity is the same as shown in Fig. 4. The specific expressions of the circuit parameters for either case are given next. In both cases, the characteristic admittances of the transmission lines associated with the slits are

(58) The input line admittance is the same as in (1) for the symmetrical problem, whereas, for the nonsymmetrical case, it does not include the factor 2; namely,

(59)

(62) (63) for the nonsymmetrical case in Fig. 15(b). APPENDIX B This appendix presents the generalization of the circuit model to structures with more than two slits in the irreducible unit-cell or half unit-cell problem. Consider, for instance, a structure with five slits per period distributed symmetrically within the unit cell. The corresponding generalized waveguide discontinuity associated to the half unit-cell problem is depicted in Fig. 16. By following the same line of reasoning as in Section II-A, (21) for the voltages at the ports naturally becomes

(64)

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At the light of the above derivation, the generalization to a compound grating whose irreducible unit-cell or half unitcell problem comprises slits is rather straightforward. The topology of the circuit model is the natural extension of that in Fig. 17 with coupling levels (from 0 to ). The barred admittances are defined as

(77)

Fig. 17. Topology of the equivalent circuit for a structure in which the irreducible unit cell (or half unit cell) problem has three slits.

and for the current at the input port we now have the following three equations with a similar structure as (25) and (29): (65) (66) (67) Now consider the topology shown in Fig. 17, which is the natural extension of the topology previously derived in Section II-A. In this equivalent circuit we can distinguish three coupling orders: a first coupling order represented by the and admittances, which accounts for the interaction between adjacent slits (nearest neighbors); a second-order coupling represented by (second nearest neighbor interaction); and a zeroth-order coupling (self reaction) associated with the admittances. The current flowing downward through a longitudinal cut placed at the height of the transmission line corresponding to slit 1 can be written as (68) Similarly, the current flowing through longitudinal cuts at slits 2 and 3 are

(69) (70) Substituting (64) into these last three equations and identifying them with (65)–(67), respectively, it is obtained (71) (72) (73) (74) (75) (76) of a given element in the cirIn other words, the admittance cuit is given by the corresponding barred admittance, , minus the admittances of all the elements of higher order coupling that cover the element between their connections.

for structures with a nonsymmetrical unit cell, and (78) for structures with a symmetrical unit cell (in this case, if the unit cell has an odd number of slits, in the above formula the parameter of the central slit is taken as zero, and its parameter corresponds to half its width). The admittances of the elements in the equivalent circuit are given by

with (79)

REFERENCES [1] J. Fraunhofer, “Kurtzer bericht von den resultaten neuerer versuche über die sesetze des lichtes, und die theorie derselbem,” Annu. D, Phys., vol. 74, pp. 337–378, 1823. [2] R. W. Wood, “On a remarkable case of uneven distribution of light in a diffraction grating spectrum,” Proc. Phys. Soc. Lond., vol. 18, pp. 269–275, Jun. 1902. [3] L. Rayleigh, “Note on the remarkable case of diffraction spectra described by prof. Wood,” Philos. Mag., vol. 14, no. 79, pp. 60–65, 1907. [4] L. Rayleigh, “On the dynamical theory of gratings,” Proc. R. Soc. Lond., vol. 79, pp. 399–416, Aug. 1907. [5] T. W. Ebbesen, H. J. Lezec, H. F. Ghaemi, T. Thio, and P. A. Wolff, “Extraordinary optical transmission through sub-wavelength hole arrays,” Nature, vol. 391, pp. 667–669, Feb. 1998. [6] F. J. García-de-Abajo, “Colloquium: Light scattering by particle and hole arrays,” Rev. Mod. Phys., vol. 79, pp. 1267–1290, Oct.–Dec. 2007. [7] C. Genet and T. W. Ebbesen, “Light in tiny holes,” Nature, vol. 445, pp. 39–46, Jan. 2007. [8] F. J. García-Vidal, L. Martín-Moreno, T. W. Ebbesen, and L. Kuipers, “Light passing through subwavelength apertures,” Rev. Mod. Phys., vol. 82, pp. 729–787, Jan.–Mar. 2010. [9] R. Gordon, A. G. Brolo, D. Sinton, and K. L. Kavanagh, “Resonant optical transmission through hole-arrays in metal films: Physics and applications,” Laser Photon. Rev., vol. 4, pp. 311–335, Mar. 2010. [10] J. A. Porto, F. J. García-Vidal, and J. B. Pendry, “Transmission resonances on metallic gratings with very narrow slits,” Phys. Rev. Lett., vol. 83, no. 14, pp. 2845–2848, Oct. 2010. [11] M. M. J. Treacy, “Dynamical diffraction explanation of the anomalous transmission of light through metallic gratings,” Phys. Rev. B, Condens. Matter, vol. 66, Nov. 2002, Art. no. 195105. [12] V. G. Sologub, V. P. Schestopalov, and G. G. Polovnikov, “Diffraction of electromagnetic waves on the grating with narrow slits,” J. Tech. Phys., vol. 37, pp. 667–679, Apr. 1967. [13] V. G. Sologub and V. P. Schestopalov, “The resonance phenomena at the diffraction of the h-polarized waves on the gratings of metal bars,” J. Tech. Phys., vol. 38, pp. 667–679, Sep. 1968. [14] F. Medina, F. Mesa, and D. C. Skigin, “Extraordinary transmission through arrays of slits: A circuit theory model,” IEEE Trans. Microw. Theory Techn., vol. 58, no. 1, pp. 105–115, Jan. 2010.

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[15] A. Alù, G. D’Aguanno, N. Mattiucci, and M. J. Bloemer, “Plasmonic brewster angle: Broadband extraordinary transmission through optical gratings,” Phys. Rev. Lett., vol. 106, Mar. 2011, Art. no. 123902. [16] R. Rodríguez-Berral, C. Molero, F. Medina, and F. Mesa, “Analytical wideband model for strip/slit gratings loaded with dielectric slabs,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 12, pp. 3908–3918, Dec. 2012. [17] C. Qiu, S. Li, R. Chen, B. Hou, F. Li, and Z. Liu, “Deep subwavelength electromagnetic transparency through dual metallic gratings with ultranarrow slits,” Phys. Rev. B, Condens. Matter, vol. 87, May 2013, Art. no. 205129. [18] Y. Gong, X. Liu, K. Li, J. Huang, J. J. Martínez, D. Rees-Whippey, S. Carver, L. Wang, W. Zhang, T. Duan, and N. Copner, “Coherent emission of light using stacked gratings,” Phys. Rev. B, Condens. Matter, vol. 87, May 2013, Art. no. 205121. [19] T. L. Zinenko, M. Marciniak, and A. I. Nosich, “Accurate analysis of light scattering and absorption by an infinite flat grating of thin silver nanostrips in free space using the method of analytical regularization,” IEEE J. Sel. Top. Quantum Electron., vol. 19, no. 3, May/Jun. 2013, Art. no. 9000108. [20] O. V. Shapoval, A. I. Nosich, and J. Ctyrokyb, “Resonance effects in the optical antennas shaped as finite comb-like gratings of noble-metal nanostrips,” Proc. SPIE, vol. 8781, pp. 87810U–(1–8), 2013. [21] X. Zhou, J. Fang, D. Yang, X. Zhao, B. Tang, and Z. Liu, “Optical transmission through compound gold surface relief slit arrays,” Opt. Exp., vol. 22, pp. 1085–1092, Jan. 2014. [22] J. Zhou and J. Guo, “Transition from a spectrum filter to a polarizer in a metallic nano-slit array,” Sci. Rep. U.K., vol. 4, Jan. 2014, Art. no. 3614. [23] C. Tardieu, T. Estruch, G. Vincent, J. Jaeck, N. Bardou, S. Collin, and R. Haidar, “Extraordinary optical extinctions through dual metallic gratings,” Opt. Lett., vol. 40, pp. 661–664, Feb. 2015. [24] S.-H. Chang and Y.-L. Su, “Mapping of transmission spectrum between plasmonic and nonplasmonic single slits. I: Resonant transmission,” J. Opt. Soc. Amer. B, Opt. Phys., vol. 32, pp. 38–44, Jan. 2015. [25] S.-H. Chang and Y.-L. Su, “Mapping of transmission spectrum between plasmonic and nonplasmonic single slits. II: Nonresonant transmission,” J. Opt. Soc. Amer. B, Opt. Phys., vol. 32, pp. 45–51, Jan. 2015. [26] O. V. Shapoval, “Comparison of refractive-index sensitivities of optical-mode resonances on a finite comb-like grating of silver nanostrips,” IEEE J. Quantum Electron., vol. 51, no. 4, Apr. 2015, Art. no. 7200108. [27] J. B. Pendry, L. Martín-Moreno, and F. J. García-Vidal, “Mimicking surface plasmons with structured surfaces,” Science, vol. 305, pp. 847–848, Aug. 2004. [28] A. P. Hibbins, B. R. Evans, and J. R. Sambles, “Experimental verification of designer surface plasmons,” Science, vol. 308, pp. 670–672, Apr. 2005. [29] R. E. Collin, Field Theory of Guided Waves. Piscataway, NJ, USA: IEEE Press, 1991. [30] F. Medina, F. Mesa, and R. Marqués, “Extraordinary transmission through arrays of electrically small holes from a circuit theory perspective,” IEEE Trans. Microw. Theory Techn., vol. 56, no. 12, pp. 3108–3120, Dec. 2008. [31] M. García-Vigueras, F. Mesa, F. Medina, R. Rodríguez-Berral, and J. L. Gómez-Tornero, “Simplified circuit model for metallic arrays of patches sandwiched between dielectric slabs under arbitrary incidence,” IEEE Trans. Antennas Propag., vol. 60, no. 10, pp. 4637–4649, Oct. 2012. [32] R. Rodríguez-Berral, F. Medina, F. Mesa, and M. García-Vigueras, “Quasi-analytical modeling of transmission/reflection in strip/slit gratings loaded with dielectric slabs,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 3, pp. 405–418, Mar. 2012. [33] C. Molero, R. Rodríguez-Berral, F. Mesa, and F. Medina, “Analytical circuit model for 1-D periodic T-shaped corrugated surfaces,” IEEE Trans. Antennas Propag., vol. 62, no. 2, pp. 794–803, Feb. 2014. [34] F. Mesa, M. García-Vigueras, F. Medina, R. Rodríguez-Berral, and J. R. Mosig, “Circuit model analysis of frequency selective surfaces with scatterers of arbitrary geometry,” IEEE Antennas Wireless Propag. Lett., vol. 14, pp. 135–138, 2015.

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[35] F. Mesa, R. Rodríguez-Berral, M. García-Vigueras, F. Medina, and J. R. Mosig, “Simplified modal expansion to analyze frequency selective surfaces: An equivalent circuit approach,” IEEE Trans. Antennas Propag., to be published. [36] F. Costa, A. Monorchio, and G. Manara, “An overview of equivalent circuit modeling techniques of frequency selective surfaces and metasurfaces,” ACES J., vol. 29, no. 14, pp. 960–976, Dec. 2014. [37] S. A. Masalov and Y. K. Sirenko, “The solution of the problem of the plane wave diffraction on the knife-type grating with compound structure of a period,” (in Russian) Radioteknica Elektron., vol. 23, no. 3, pp. 481–487, 1978. [38] A. N. Fantino, S. I. Grosz, and D. C. Skigin, “Resonant effects in periodic gratings comprising a finite number of grooves in each period,” Phys. Rev. E, Stat. Phys. Plasmas Fluids Relat. Interdiscip. Top., vol. 64, Jun. 2001, Art. no. 016605. [39] S. I. Grosz, D. C. Skigin, and A. N. Fantino, “Resonant effects in compound diffraction gratings: Influence of the geometrical parameters of the surface,” Phys. Rev. E, Stat. Phys. Plasmas Fluids Relat. Interdiscip. Top., vol. 65, May 2002, Art. no. 056619. [40] D. C. Skigin, V. V. Veremey, and R. Mittra, “Superdirectivity radiation from finite gratings of rectangular grooves,” IEEE Trans. Antennas Propag., vol. 47, no. 2, pp. 376–383, Feb. 1999. [41] D. C. Skigin and R. A. Depine, “Transmission resonances of metallic compound gratings with subwavelength slits,” Phys. Rev. Lett., vol. 95, Nov. 2005, Art. no. 217402. [42] A. P. Hibbins, I. R. Hooper, M. I. Lockyear, and J. R. Sambles, “Microwave transmission of a compound gratings,” Phys. Rev. Lett., vol. 96, Jun. 2006, Art. no. 257402. [43] Y. G. Ma, X. S. Rao, G. F. Zhang, and C. K. Ong, “Microwave transmission modes in compound metallic gratings,” Phys. Rev. B, Condens. Matter, vol. 76, Aug. 2007, Art. no. 085413. [44] M. Navarro-Cía, D. C. Skigin, M. Beruete, and M. Sorolla, “Experimental demonstration of phase resonances in metallic compound gratings with subwavelength slits in the milimeter wave regime,” Appl. Phys. Lett., vol. 94, Mar. 2009, Art. no. 091107. [45] I. M. Mandel, A. B. Golovin, and D. T. Crouse, “Analytical description of the dispersion relation for phase resonances in compound transmission gratings,” Phys. Rev. A, Gen. Phys., vol. 87, May 2013, Art. no. 053833. [46] J. R. Andrewartha, J. R. Fox, and I. J. Wilson, “Resonance anomalies in the lamellar gratings,” Opt. Acta, vol. 26, no. 1, pp. 69–89, 1979. [47] A. Wirgin and A. A. Maradudin, “Resonant enhancement of the electric field in the grooves of bare metallic gratings exposed s-polarized light,” Phys. Rev. B, Condens. Matter, vol. 31, no. 8, pp. 5573–5576, Apr. 1985. [48] D. C. Skigin and R. A. Depine, “Resonant enhancement of the field within a single ground-plane cavity: Comparison of different rectangular shapes,” Phys. Rev. E, Stat. Phys. Plasmas Fluids Relat. Interdiscip. Top., vol. 59, no. 3, pp. 3661–3668, Mar. 1999. [49] A. Khavasi and K. Mehrany, “Circuit model for lamellar metallic gratings in the sub-wavelength regime,” IEEE J. Quantum Electron., vol. 47, no. 10, pp. 1330–1335, Oct. 2011. [50] D. W. Woo, S. J. Muhn, and W. S. Park, “Simple analytical model of propagation through thick periodic slot,” IEEE Trans. Antennas Propag., vol. 60, no. 1, pp. 5329–5335, Nov. 2012. [51] E. Yarmoghaddam, G. K. Shirmanesh, A. Khavasi, and K. Mehrany, “Circuit model for a periodic array of slits with multiple propagating diffracted orders,” IEEE Trans. Antennas Propag., vol. 62, no. 8, pp. 4041–4048, Aug. 2014. Carlos Molero was born in Las Navas, Seville, Spain, in 1987. He received the Licenciado degree in physics from the University of Sevilla, Seville, Spain, in 2011, and is currently working toward the Ph.D. degree in applied physics at the University of Sevilla. He is currently with the Department of Applied Physics 1, University of Sevilla. Mr. Molero was the recipient of a Research Scholarship from the Spanish Ministerio de Economía y Competitividad.

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Raúl Rodríguez-Berral was born in Casariche, Seville, Spain, in 1978. He received the M.Sc. (Licenciado) and Ph.D. degrees in physics from the University of Sevilla, Seville, Spain, in 2001 and 2008, respectively. He is currently an Associate Professor with the Department of Applied Physics 1, University of Sevilla. His research interests include the study of the spectrum and the excitation of periodic and nonperiodic planar structures and high-frequency circuit modeling.

Francisco Mesa (M’93–SM’11–F’14) was born in Cádiz, Spain. He received the Licenciado and Doctor degrees in physics from the University of Sevilla, Seville, Spain. He is currently a Professor with the Department of Applied Physics, University of Sevilla. His research interests are focused on electromagnetic propagation/ radiation in planar structures. Prof. Mesa has been an Associate Editor for the IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES since 2013.

Francisco Medina (M’90–SM’01–F’10) was born in Puerto Real, Cádiz, Spain, in November 1960. He received the Licenciado (M.Sc.) and Doctor (Ph.D.) degrees in physics from the University of Sevilla, Seville, Spain, in 1983 and 1987 respectively. He is currently a Professor of electromagnetism with the Department of Electronics and Electromagnetism, University of Sevilla, and Head of the Microwaves Group. His research interests include analytical and numerical methods for planar structures, anisotropic materials, and artificial media modeling. Prof. Medina has been an Associate Editor for the International Journal of Microwave and Wireless Technologies since 2015.

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Surface Roughness Modeling of Substrate Integrated Waveguide in D-Band Ming Yi, Student Member, IEEE, Sensen Li, Huan Yu, Wasif Khan, Student Member, IEEE, Cagri Ulusoy, Member, IEEE, Aida Vera-Lopez, Student Member, IEEE, John Papapolymerou, Fellow, IEEE, and Madhavan Swaminathan, Fellow, IEEE

Abstract—In this paper, surface roughness models for a substrate integrated waveguide (SIW) are proposed. Frequency-dependent conductivity is introduced to model the conductor loss due to surface roughness. To be specific, two models, namely, the modified Huray model and the rigorous waveguide model, are developed. Both models take into account the mode-dependent loss. Formulations for enhancement factor are derived for both models to calculate the frequency-dependent conductivity. Key parameters of the analytical models are extracted from the surface profile measurement. A D-band (110–170 GHz) SIW structure is fabricated using a liquid crystal polymer substrate. The simulated results are correlated with measured data of the fabricated SIW, which shows the accuracy of the proposed methods. Index Terms—Analytical model, frequency-dependent conductivity, substrate integrated waveguide (SIW), surface roughness.

I. INTRODUCTION

A

S THE operating frequency reaches hundreds of gigahertz, traditional planar transmission lines, such as microstrip and stripline, begin to show limitations in loss, crosstalk, and power-handling capacity. A substrate integrated waveguide (SIW) (Fig. 1) has been proposed and is considered as a promising alternative to traditional transmission lines due to its miniaturized size for millimeter-wave applications, immunity to crosstalk, and large power-handling capacity [1]. However, since a large amount of metal carries the current in the SIW at high frequencies, the transmission loss can be significantly affected by conductor surface roughness. Hence, developing computationally efficient and accurate models for surface roughness in the SIW is important. The impact of surface roughness on transmission-line loss has been investigated for decades. The early attempts generalize the rough surface into a two-dimensional (2-D) periodic distribution of simple shapes. In [2], the rough surface is modeled by 2-D rectangular and triangular periodic grooves from which an analytical solution is derived. Empirical and analytical formulas of the roughness enhancement factor have been developed based on this type of model [3], [4]. However, it has been Manuscript received May 23, 2015; revised August 17, 2015 and January 10, 2016; accepted February 20, 2016. The authors are with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332 USA (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2535290

Fig. 1. Schematics of: (a) rectangular waveguide and (b) SIW. Via fence are used in SIW to replace the side walls of the rectangular waveguide, whereas two metal planes serve as top and bottom metal walls.

demonstrated that the enhancement factor developed in [5] saturates at frequencies at around 10 GHz, making it inapplicable for high-frequency simulation. Other methods based on the 2-D roughness distribution for different applications have also been developed [6]. To more accurately model surface roughness, the random roughness is represented by periodic three-dimensional (3-D) simple geometries. In [7], surface roughness is modeled by conducting hemispheres sitting on the surface of a metal plane. Analytical solution of the conductivity enhancement factor is derived by applying the plane wave scattering theory. This method is demonstrated to be accurate in modeling loss of microstrip lines up to 30 GHz and later has been extended to stripline interconnects [8]. To overcome the early saturation of enhancement factor using the method in [7], the rough surface is modeled by conducting sphere bundles sitting on the conductor surfaces, creating a “hemispheroid-like” structure [5]. Other attempts have also been made including introducing an effective conductivity layer on the rough surfaces [9]. Another type of modeling scheme involves direct tackling of the roughness without generalizing roughness distribution into equivalent shapes or surfaces. The most straightforward solution is to create 3-D structures with roughness details and simulate using commercial full-wave solvers [10]. However, this method is computationally inefficient. Modified full-wave solutions are proposed with decreased computational time [11]. In [12], the roughness is considered as Gaussian distributed and a 2-D waveguide problem is investigated. The second-order small perturbation method is applied to derive a close-form expression for the coherent wave propagation and power loss. The derived result is expressed in terms of a double Sommerfeld integral. This method was later extended to 3-D problems [13]. However, the implementation of this method is still complex and time consuming. It is important to note that all the aforementioned surface roughness models are developed for transmission lines supporting quasi-transverse electromagnetic (TEM) or TEM

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modes such as microstrip lines and coaxial lines. Since transmission loss is mode dependent, accurate and efficient models need to be developed for the SIW. In [14], the effect of surface roughness on the cutoff frequencies of rectangular waveguides have been analyzed. The authors assume a periodic rectangular, triangular, sinusoidal, and Gaussian inner rough surface and model it numerically. In this paper, we use a different technique where the rough surface is approximated using spheres without any assumptions on periodicity. In addition, the method described in this paper is general and can be applied in any electromagnetic solver to account for the surface roughness. In addition, we show experimental validation and operate the waveguide at much higher frequencies to ensure compactness. In this paper, surface roughness models for SIW operating in D-band (SIW) are proposed for the first time. Frequency-dependent conductivity is introduced to model the conductor loss due to surface roughness. To calculate the frequency-dependent conductivity, formulations for conductivity enhancement factor are derived using two different models. The derived enhancement factor is completely different from that derived for the TEM type of transmission line since it takes into account the mode-dependent loss. Key parameters of the analytical models are extracted from the surface profile measurement. This paper is organized in the following manner. In Section II, two models have been proposed where the derivation and formulation for enhancement factor is discussed. In Section III, numerical results are presented and correlated with measurement of the fabricated sample. In Section IV, the conclusion is summarized.

Fig. 2. Contour plot of: (a) field distribution and (b) energy density distribution mode. in a rectangular waveguide in

in one bundle, the enhancement factor can be calculated. The Huray model evaluates the loss of a sphere from energy density without dealing with the real current distribution on the surface. This model has good accuracy, but needs to be modified for the SIW. When the Huray model in [5] is suitably modified and applied to the SIW as described in this paper, it has been called as the modified Huray model. In a rectangular waveguide, the field components for the mode is given by (3)

II. PROPOSED METHODS A. Modified Huray Model

(4)

Due to surface roughness of the conductor, the difference in conductor loss of a transmission line with a smooth and rough surface tends to increase as frequency increases. Therefore, it is convenient to introduce a frequency-dependent conductivity term, which incorporates the extra surface roughness loss as

(5)

(1) where is the frequency-dependent enhancement factor and is the constant conductivity (a conductivity of 5.6 10 S m for copper was used). The enhancement factor should be greater than one across all the frequencies of interest since the rough surface is always more lossy than a smooth surface. For a fixed design, the enhancement factor can be expressed as follows: (2) where is the power loss of a rough surface and is the power loss of the corresponding smooth surface. To obtain , a 3-D equivalent surface can be introduced to represent a surface with random roughness. The Huray model [5] represents the surface roughness using conducting sphere bundles sitting on smooth metal tiles. By calculating the loss due to a single sphere and summarizing the loss of all the spheres

where is the width of the waveguide, is the propagating constant, and is the magnitude constant for the mode. Note that, in this paper, only the formulations for the mode are discussed. The absolute value of the Poynting vector associated with the mode can be expressed as (6) Fig. 2(a) shows the electric and magnetic fields distribution in a rectangular waveguide for the mode. Fig. 2(b) shows the absolute value of the Poynting vector in the waveguide. It is obvious that the absolute value of the Poynting vector here is position dependent, which is different from the mode propagating on TEM transmission lines. The loss of a single sphere on a smooth metal tile (Fig. 3) can be calculated by multiplying (6) and the total cross section of the sphere [7] (7) where (8)

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Fig. 3. Conducting sphere sitting on a smooth metal surface. Fig. 4. Conducting sphere sitting on the bottom wall of a rectangular waveguide.

in which (9)

The reflection coefficient of a single sphere sitting on the wall of a rectangular waveguide (Fig. 4) can be calculated as [15]

(10) , is the radius of the sphere, and is the skin depth. The power loss of the smooth metal tile beneath the sphere is

where

(11) where is the tangential magnetic field at the center of the tile and is the area of the tile. Therefore, the enhancement factor can be calculated using

(12)

where is the total number of tiles and is the total number of spheres associated with one tile. This modified Huray model takes into account the power density inside the waveguide. However, the total cross section is derived from the plane wave incident model, which is not rigorous for waveguide propagation. B. Rigorous Waveguide Model In a transmission line, the power loss due to the surface roughness mainly consists of two parts: first, since the surface roughness can be considered as protrusions out of a smooth surface, energy will be reflected back to the source; second, the enhanced surface area of protrusions will absorb power, making it a major source of power loss. It is important to note that radiation loss can be associated with the SIW because of the non-completeshielding via fence structure. However, if designed properly, the radiation loss at high frequencies can be negligible compared to conductor loss and, hence, is not included here. For a SIW, any power that is not transmitted is considered as power loss, which, therefore, satisfies (13) where and are the reflection and transmission coefficient, respectively. Thus, and correspond to the aforementioned reflection power and absorption power, respectively.

(14) where is

. The position-dependent power loss of a sphere (15)

is the power flux of the waveguide, which is exwhere pressed as (16) For a conducting sphere sitting on the bottom of a waveguide, the field strength will be low in the “shade region” between the sphere and smooth plane [15]. This almost field free region makes the equivalent surface area of the conducting sphere to be incremented by approximately half the sphere surface area. The relationship of skin depth and the radius of the sphere should also be taken into consideration, which results in the power loss due to energy absorption taking the form (17) where is a correction factor taking into account the ratio between skin depth and radius of the sphere, which can be expressed as (18) From (18), for surface roughness height equal to or less than the skin depth of the conductor, the energy loss due to the increment of current path has no effect. For surface roughness height much larger than skin depth, the correction factor is approximately one, making the equivalent surface area equal to half of a sphere surface. Hence, during modeling the radius of the sphere close to (but larger than the skin depth) is preferred to account for the loss accurately, as shown in Fig. 14. Therefore, the new enhancement factor can be calculated as

(19)

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Fig. 5. Schematic of a 2-D conductor surface roughness profile and key parameters related to roughness.

C. Implementation Strategy and Parameter Extraction The loss due to a single sphere protrusion can be calculated analytically using aforementioned models. Based on the loss of a single sphere, the enhancement factor is obtained by taking into account the loss of all the spheres, as shown in (12) and (19). In practice, this requires the rough surface of copper to be discretized into square cells. The area of each cell equals the area of the metal tile in the model. Conducting sphere bundles sitting on each tile form a “tooth shape” protrusion approximated by a hemispheroid. Fig. 5 shows the schematic of a 2-D conductor surface roughness profile. Three key parameters related to the roughness, namely, the root mean square (rms) of the distance between peaks of hemispheroid , the base length of the hemispheroid , and the height of the hemispheroid need to be extracted from the 2-D profile measurement. It is convenient to make the cell edge length in accordance with . The number of spheres associated with each tile is determined by and . Using a equivalent volume concept, is calculated as

Fig. 6. Fabrication process of the SIW on LCP substrate.

Fig. 7. Fabricated SIW with CPW-to-microstrip and microstrip-to-SIW transitions. (a) Top view of the entire fabricated structure. (b) Cross-sectional view of the SIW. (c) Top view the copper surface near a via structure. (b) and (c) are captured by Hitachi 3700 variable-pressure SEM.

(20) where is the volume of a single sphere and volume of the hemispheroid expressed as

is the

(21)

III. FABRICATION OF SIW A D-band (110–170 GHz) SIW was fabricated based on liquid crystal polymer (LCP) substrate. The LCP is widely used in high-frequency applications due to its low-loss property and commercial feasibility. The dielectric constant, loss tangent, and thickness of the LCP substrate are , , and mm, respectively [21]. The length, width, via pitch, and via diameter are 2.1, 0.925, 0.1258, and 0.0508 mm, respectively. Coplanar waveguide (CPW)-to-microstrip and microstrip-to-SIW transitions are designed to facilitate the measurement with minimum return loss. The fabrication process is summarized in Fig. 6. First, the bottom copper layer is etched out, leaving 9- m-thick copper on the top side. Second, the sample is processed with micrometer laser drill for forming the alignment vias at each edge of the sample. The vias for the SIW sidewall are also laser drilled through the

LCP substrate and stopped at the top side copper. Third, vias are metallized and a 9- m-thick copper layer is sputtered on the bottom side of the sample. Last, the SIW and all the other related structures are patterned on both sides of the substrate. Fig. 7(a) shows the top view of the fabricated SIW structure. Fig. 7(b) shows the cross-sectional view of the SIW captured using a scanning electron microscope (SEM). Roughness can be observed at the copper–LCP interface. Fig. 7(c) shows the SEM top view of the copper surface near a via. Sphere-like roughness can be observed on the copper surface, which validates the assumption of modeling the roughness using conductor sphere bundles. To ensure accuracy with measurements we performed two sets of measurements, one with line-reflect-reflect-match (LRRM) and the other with multi-line thru-relfect-line (TRL) calibration. Both calibrations were compared and gave similar results in terms of loss/mm so accuracy was verified by two sets of completely different calibration standards (custom standard on LCP for TRL and purchased standards from Cascade MicroTech on Alumina for LRRM). LRRM calibrations moves the reference plane to the probe tip and a multi-line TRL moves to the edge of the SIW–microstrip transition. The accuracy is limited by the vector network analyzer (VNA) error. However, as the loss measurement is acquired using different lengths of

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Fig. 8. Measured 2-D surface roughness profile. Data collected by Dektak profilometer.

Fig. 10. Measured and simulated return loss of the fabricated structure.

Fig. 9. Enhancement factor calculated by both models.

lines, especially for multi-line TRL calibration, the results are very accurate. IV. NUMERICAL RESULTS The 2-D surface roughness profile was measured using a DekTak profilometer with a precision of 4 Å. Measurement result is shown in Fig. 8. Key parameters , , and were extracted from the measurement data and the values are 10, 10, and 1.0 m, respectively. Cell edge length and number of spheres in one cell was calculated using the method discussed earlier with sphere radius of 0.5 m. Fig. 9 shows the enhancement factor calculated by both models. The frequency-dependent conductivity was calculated using (1) and was imported into a commercial solver: ANSYS High Frequency Structure Simulator (HFSS). It is important to note that the frequency-dependent conductivity can be easily incorporated into other full-wave solvers, which are capable of handling conductor loss [16]–[20]. As can be seen in Fig. 9, the rigorous waveguide model provides an increased enhancement factor at lower frequencies and converges to the modified Huray model at higher frequencies. The reason for this is that although the modified Huray model takes into consideration the TE mode power density distribution inside the SIW, the total cross-section term (8) used to calculate sphere loss is still derived in a TEM-like manner [7], which does not guarantee accuracy across the entire frequency range. The resulting difference in the enhancement factor affects the insertion loss of the SIW, as later shown in Fig. 11. Figs. 10 and 11 show the simulated and measured -parameters of the SIW structure. The measurement setup is

Fig. 11. Measured and simulated insertion loss of the fabricated structure.

shown in Fig. 12. An Agilent E8361C VNA with N5260A (mm-wave controller) and V06VNA2 (WR06 frequency extension modules) were used to measure the SIW lines in D-band. The measurements were taken using 75- m-pitch Cascade MicroTech Infinity D-band probes. Two different calibration methods were used to take measurements. The reference plane was set to the probe tips using LRRM calibration with Cascade 138-356 impedance standard substrate (ISS). Microstrip-line TRL calibration was also used, which helped move the reference plane to the end of the microstrip section. For comparison, the same SIW with a smooth conductor surface was also simulated. It can be observed from Fig. 10 that surface roughness does not have a major impact on the return loss of the SIW. However, it is observed from Fig. 11 that the surface roughness has a significant influence on the insertion loss of the SIW. The magnitude difference of the insertion loss between a simulated SIW with a smooth conductor surface and measurement indicates that the loss effect cannot be modeled by a smooth surface. It is obvious that by modeling the surface roughness using the proposed methods, the conductor loss in the SIW is more accurately captured. Moreover, although for 170 GHz the insertion loss has good correlation with the measurement using both models, at lower frequencies, the rigorous waveguide model has more accuracy. SIWs with different rms heights of the surface roughness were investigated using the rigorous waveguide model. Fig. 13 shows the insertion loss of the SIW with different

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Fig. 12.

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-parameters measurement setup for the fabricated SIW structure. Fig. 14. Effect of sphere radius on insertion loss.

Fig. 13. Simulated insertion loss of the SIW with different rms roughness height.

surface roughness heights. Three scenarios are considered, namely, the rms of the surface roughness height of 0.1, 0.25, and 0.5 m, respectively. It can be observed from the results that larger roughness height results in higher loss, as expected. This is because the equivalent length of the current path is longer for larger roughness cases. To be noted, roughness height rms of 0.1 m or below has little impact on the overall insertion loss of the SIW. This is because the roughness height is close to skin depth at the frequency of interest, resulting in a limited increment of equivalent length of the current path as frequency increases. The radius of the sphere chosen to model surface roughness depends on both skin depth and the surface being approximated. Fig. 14 shows the effect of the radius of the sphere on the insertion loss of the SIW. As the radius of the sphere is decreased, the insertion loss converges. However, as mentioned earlier, the sphere radius needs to be close to, but larger than, the skin depth for the loss to be computed accurately. It is important to note that the surface roughness of vias in the SIW is not modeled in this paper since vias are not expected to be a major loss factor. Fig. 15 shows the insertion loss of the SIW with two simulation scenarios. One scenario considers the conductivity of vias the same as rough copper. The other scenario treats vias as perfect electric conductors (PECs). It can be observed from Fig. 15 that the difference between the two curves across the D-band is small, which indicates that vias have little impact on the total loss of the SIW. This is because the current density on the surface of the vias is not high and the surface area of the vias is small for the structures considered.

Fig. 15. Simulated insertion loss of the SIW with different conductivity of vias.

V. CONCLUSION Two analytical surface roughness models for the SIW in D-band have been proposed for the first time by introducing frequency-dependent conductivity. Formulations for the enhancement factor are derived to calculate the frequency-dependent conductivity. Both models, namely, the modified Huray model and rigorous waveguide model, are developed by taking into account the mode-dependent loss. Good agreement between the simulation results and measurements were achieved. The rigorous waveguide model shows better results in modeling the loss for the entire D-band. REFERENCES [1] D. Deslandes and K. Wu, “Integrated microstrip and rectrangular waveguide in planar form,” IEEE Microw. Wireless Compon. Lett., vol. 11, no. 2, pp. 68–70, Feb. 2001. [2] S. Morgan, “Effect of surface roughness on eddy current losses at microwave frequencies,” J. Appl. Phys., vol. 20, no. 4, pp. 352–362, Apr. 1949. [3] E. Hammerstad and F. Bekkadal, “Microstrip Handbook,” ELAB, Trondheim, Norway, ELAB Rep., 1975. [4] C. Holloway and E. Kuester, “Power loss associated with conducting and superconducting rough interfaces,” IEEE Trans. Microw. Theory Techn., vol. 48, no. 10, pp. 1601–1603, Oct. 2000. [5] S. Hall and H. Heck, Advance Signal Integrity for High-Speed Digital Designs. Hoboken, NJ, USA: Wiley, 2009. [6] M. Lukic and D. Filipovic, “Modeling of 3-D surface roughness effects with application to -coaxial lines,” IEEE Trans. Microw. Theory Techn., vol. 55, no. 3, pp. 518–525, Mar. 2007. [7] S. Hall et al., “Multigigahertz causal transmission line modeling methodology using a 3-D hemispherical surface roughness approach,” IEEE Trans. Microw. Theory Techn., vol. 55, no. 12, pp. 2614–2624, Dec. 2007.

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[8] X. Guo, D. Jackson, M. Koledintseva, S. Hinaga, J. Drewniak, and J. Chen, “An analysis of conductor surface roughness effects on signal propagation for stripline interconnects,” IEEE Trans. Electromagn. Compat., vol. 56, no. 3, pp. 707–714, Jun. 2014. [9] X. Ma, J. Ochoa, and A. Cangellaris, “A method for modeling the impact of conductor surface roughness on waveguiding properties of interconnects,” in Proc. IEEE Electr. Perform. Electron. Packag. Syst. Conf., Oct. 2013, pp. 11–14. [10] A. Sain and K. Melde, “Broadhand characterization of coplanar waveguide interconnects with rough conductor surfaces,” IEEE Trans. Compon., Packag., Manuf. Technol., vol. 3, no. 6, pp. 1038–1046, Jun. 2013. [11] Q. Chen, H. Choi, and N. Wong, “Robust simulation methodology for surface-roughness loss in interconnect and package modelings,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 28, no. 11, pp. 1654–1665, Nov. 2009. [12] R. Ding, L. Tsang, and H. Braunisch, “Wave propagation in a randomly rough parallel-plate waveguide,” IEEE Trans. Microw. Theory Techn., vol. 57, no. 5, pp. 1216–1223, May 2009. [13] R. Ding, L. Tsang, H. Braunisch, and W. Chang, “Wave propagation in parallel plate metallic waveguide with finite conductivity and three dimensional roughness,” IEEE Trans. Antennas Propag., vol. 60, no. 12, pp. 5867–5880, Dec. 2012. [14] B. Huang, J. Chen, and W. Jiang, “Effects of surface roughness on TE modes in rectangular waveguide,” J. Infrared, Millim., Terahertz Waves, vol. 30, no. 7, pp. 717–726, 2009. [15] J. Hinken, “Conducting spheres in rectangular waveguide,” IEEE Trans. Microw. Theory Techn., vol. MTT-28, no. 7, pp. 711–714, Jul. 1980. [16] M. Yi and M. Swaminathan, “Skin effect modeling of interconnects using the Laguerre-FDTD scheme,” in Proc. IEEE Electron. Perform. Electron. Packag. Syst. Conf., Oct. 2012, pp. 236–239. [17] M. Yi, M. Ha, Z. Qian, A. Aydiner, and M. Swaminathan, “Skin-effectincorporated transient simulation using the Laguerre-FDTD scheme,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 12, pp. 4029–4039, Dec. 2013. [18] M. Yi, Z. Qian, A. Aydiner, and M. Swaminathan, “Transient simulation of multiscale structures using the nonconformal domain decomposition Laguerre-FDTD method,” IEEE Trans. Compon., Packag., Manuf. Technol., vol. 5, no. 4, pp. 532–540, Apr. 2015. [19] K. S. Oh and J. Schutt-Aine, “An efficient implementation of surface impedance boundary conditions for the finite-difference time-domain method,” IEEE Trans. Antennas Propag., vol. 43, no. 7, pp. 660–666, Jul. 1995. [20] R. Makinen and M. Kivikoski, “Incorporation of conductor loss in unconditionally stable ADI-FDTD method,” IEEE Trans. Antennas Propag., vol. 56, no. 7, pp. 2023–2030, Jul. 2008. [21] W. T. Khan, C. A. Donado, A. Cagri Ulusoy, and J. Papapolymerou, “Characterization of liquid crystal polymer (LCP) from 110 GHz to 170 GHz,” in IEEE Radio Wireless Symp., Newport Beach, CA, USA, Jan. 19–22, 2014, pp. 157–159.

Ming Yi (S’14) received the B.S. degree in electrical and computer engineering from the Wuhan University of Technology, Wuhan, China, in 2008, the M.S. degree in electrical and computer engineering from Shanghai Jiao Tong University, Shanghai, China, in 2011, the M.S. degree in electrical and computer engineering from Georgia Institute of Technology, Atlanta, GA, USA, in 2011, and is currently working toward the Ph.D. degree in electrical and computer engineering at the Georgia Institute of Technology. His research interest includes electromagnetic modeling, 3-D multiscale chip-package co-simulation, and optimization.

7

Sensen Li received the B. Eng. and B.A. degrees from Zhejiang University, Hangzhou, China, in 2013, and is currently working toward the Ph.D degree in electrical and computer engineering at the Georgia Institute of Technology, Atlanta, GA, USA. His current research interests include millimeterwave integrated circuits and packages and antenna and phased-array systems.

Huan Yu received the B.S. degree from Zhejiang University, Hangzhou, China, in 2014, in electrical and computer engineering, and is currently working toward the Ph.D. degree in electrical and computer engineering at the Georgia Institute of Technology, Atlanta, GA, USA. His research interest includes electromagnetic modeling, simulation, and optimization.

Wasif Khan (S’10) received the B.Sc. degree in electrical engineering from the University of Engineering and Technology, Lahore, Pakistan, in 2005, the M.S. degree in electrical and computer engineering from the Georgia Institute of Technology, Atlanta, GA, USA, in 2010, and is currently working toward the Ph.D. degree at the Georgia Institute of Technology. His areas of interests include RF and microwave system design, millimeter-wave circuit and package design, multi-layer organic packaging, on-chip and off-chip antenna design, and phased-array systems.

Cagri Ulusoy (S’09–M’11) received the B.S. degree in electronics engineering from Istanbul Technical University, Istanbul, Turkey, in 2005, and the M.S. degree and Ph.D. degree (summa cum laude) from Ulm University, Ulm, Germany, in 2008 and 2012, respectively. His research interests include integrated circuit (IC) design for ultra-wideband and millimeter-wave communication and radar systems, packaging aspects related to such systems, planar passive circuit design, system-level approaches for multi-gigabit/s communication systems, and hybrid high-power amplification techniques.

Aida Vera-Lopez (S’10) received the B.S. degree (suma cum laude) in electrical engineering from the University of Puerto Rico, Mayagüez, PR, USA, in 2006, the M.S. degree in electrical and computer engineering from the Georgia Institute of Technology, Atlanta, GA, USA, in 2009, and is currently working toward the Ph.D. degree at the Georgia Institute of Technology. Her research focuses on the design, integration, and characterization of millimeter-wave passive components and packaging on organics for point-to-point communications.

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John Papapolymerou (S’90–M’99–SM’04–F’11) received the B.S.E.E. degree from the National Technical University of Athens, Athens, Greece, in 1993, and the M.S.E.E. and Ph.D. degrees from The University of Michigan at Ann Arbor, Ann Arbor, MI, USA, in 1994 and 1999, respectively. From 1999 to 2001, he was an Assistant Professor with the Department of Electrical and Computer Engineering, University of Arizona, Tucson, AZ, USA. During the summers of 2000 and 2003, he was a Visiting Professor with The University of Limoges, Limoges, France. From 2001 to 2005 and 2005 to 2009, he was an Assistant Professor and Associate Professor, respectively, with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA, where he is currently the Ken Byers Professor. He has authored or coauthored over 340 publications in peer-reviewed journals and conferences. His research interests include the implementation of micromachining techniques and microelectromechanical systems (MEMS) devices in microwave, millimeter-wave, and terahertz circuits and the development of both passive and active planar circuits and antennas on semiconductor (Si/SiGe, GaAs) and organic substrates [liquid crystal polymer (LCP), low-temperature co-fired ceramic (LTCC)] for system-on-a-chip (SOC)/system-on-a-package (SOP) RF front ends. Dr. Papapolymerou is currently Editor-in-Chief of IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS. He was an Associate Editor for the IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES (2010–2012). He was Chair for Commission D, U.S. National Committee, URSI (2009–2011). He was also an Associate Editor for IEEE MICROWAVE AND WIRELESS COMPONENT LETTERS (2004–2007) and the IEEE TRANSACTIONS ANTENNAS AND PROPAGATION (2004–2010). During 2004, he was the Chair of the IEEE Microwave Theory and Techniques (MTT)/Antennas and Propagation (AP) Atlanta Chapter. He was the recipient of the 2012 IEEE Antennas and Propagation Society (AP-S) H. A. Wheeler Prize Paper Award, the 2010 IEEE AP-S John Kraus Antenna Award, the 2009 IEEE Microwave Theory and Techniques Society (IEEE MTT-S) Outstanding Young Engineer Award, the 2009 School of Electrical and Computer Engineering Outstanding Junior Faculty Award, the 2004 Army Research Office (ARO) Young Investigator Award, the 2002 National Science Foundation (NSF) CAREER Award, the Best Paper Award of the 3rd IEEE International Conference on Microwave

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and Millimeter-Wave Technology (ICMMT2002), Beijing, China, and the 1997 Outstanding Graduate Student Instructional Assistant Award presented by the American Society for Engineering Education (ASEE), The University of Michigan at Ann Arbor Chapter. His students have also been recipients of several awards including the Best Student Paper Award presented at the 2004 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, the 2007 IEEE MTT-S Graduate Fellowship, and the 2007/2008 and 2008/2009 IEEE MTT-S Undergraduate Scholarship/Fellowship.

Madhavan Swaminathan (M’95–SM’98–F’06) received the M.S. and Ph.D. degrees in electrical engineering from Syracuse University, Syracuse, NY, USA, in 1989 and 1991, respectively. He is the John Pippin Chair in Electromagnetics with the School of Electrical and Computer Engineering and the Director of the Interconnect and Packaging Center, Georgia Institute of Technology, Atlanta, GA, USA, and the Founder and Chief Technical Officer (CTO) of E-System Design, which is a company that is focused on the development of computer-aided design (CAD) tools for achieving signal and power integrity in integrated 3-D microsystems and nanosystems. He is the co-founder of Jacket Micro Devices (acquired by the AVX Corporation), a company that specialized in integrated RF modules and substrates for wireless applications. He was Joseph M. Pettit Professor in Electronics with the School of Electrical and Computer Engineering and the Deputy Director of the National Science Foundation (NSF) Microsystems Packaging Center, Georgia Institute of Technology. Prior to joining the Georgia Institute of Technology, he was with IBM, where he was involved with packaging for supercomputers. He has authored or coauthored more than 400 technical papers and three book chapters. He holds 29 patents. He is the primary author and coeditor of Power Integrity Modeling and Design for Semiconductors and Systemsa (Prentice-Hall, 2007), Introduction to System on Package (SOP) (McGraw-Hill, 2008), and Design and Modeling for 3D ICs and Interposers (World Scientific, 2013). Dr. Swaminathan has served as a Distinguished Lecturer for the IEEE Electromagnetic Compatibility (EMC) Society.

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Modeling the Conductor Losses of Thick Multiconductor Coplanar Waveguides and Striplines: A Conformal Mapping Approach Francesco Bertazzi, Vittorio Camarchia, Senior Member, IEEE, Michele Goano, Member, IEEE, Marco Pirola, Member, IEEE, and Giovanni Ghione, Fellow, IEEE

Abstract—A conformal-mapping approach to model the skin-effect conductor losses of thick multiconductor coplanar waveguides and multiconductor coplanar strips is proposed. The model allows for arbitrary strip or slot number and widths and is accurate for conductor thicknesses up to around 40% of the minimum strip and slot width. Examples are presented to demonstrate the accuracy of the approach when compared to the results from a finite-element method numerical code. Index Terms—Conformal mapping (CM), coplanar lines, finiteelement method (FEM), Schwarz–Christoffel (SC) mapping, skineffect losses.

I. INTRODUCTION

M

ULTICONDUCTOR coplanar lines (MCLs), i.e., multiconductor coplanar waveguides (MCPWs), and multiconductor coplanar strips (MCPSs) (see Fig. 1), are building blocks in analog and digital circuits [1], [2]. Relevant examples are interdigitated MCPW couplers in coplanar microwave monolithic integrated circuits (MMICs) [3] and high-speed MCPS interconnects [4]. The analysis of MCL conductor losses can be carried out at an arbitrary frequency through full-wave and quasi-static electromagnetic (EM) approaches based on differential formulations, like the finite-element method (FEM) [5], [6]. The entire domain, including the conductors’ interior, must be discretized and the analysis of open structures requires large computational boxes to avoid artifacts from boundary conditions. In the high-frequency skin-effect regime, conductor losses can be approximated by integrating the square of the surface longitudinal current density , and taking advantage of the surface impedance concept [7, eq. (26)]. A perturbative approach is often adopted, evaluating in the presence of perfect conductors. The surface current density can be, in turn, computed through the moment method (MoM) solution of the quasi-static [7], [8] or full-wave integral formulation of the EM problem [9], [10].

Manuscript received October 13, 2015; revised January 26, 2016; accepted February 16, 2016. F. Bertazzi and M. Goano are with the Dipartimento di Elettronica e Telecomunicazioni and the IEIIT-CNR, Politecnico di Torino, 10129 Turin, Italy. V. Camarchia, M. Pirola, and G. Ghione are with the Dipartimento di Elettronica e Telecomunicazioni, Politecnico di Torino, 10129 Turin, Italy (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2535395

Fig. 1. MCLs. (a) MCPW. (b) MCPS. The strip thickness is , define the line geometry. eters ,

and the param-

While numerical techniques offer the greatest flexibility in terms of line geometry and materials, they may become too CPU intensive or inaccurate when the number of strips is large or with extreme form factors, as in low-crosstalk MCPSs, see the geometry in [4, Sec. 3.5.4]. In FEM solvers not adopting impedance boundary conditions [11], the design of a properly dense mesh also becomes critical when , where is the skin penetration depth. Moreover, such techniques often are too computationally expensive to be easily used in inverse or optimization problems. Conformal mapping (CM) is a computationally efficient tool to evaluate the longitudinal current density of MCLs, that can be approximated, in the presence of ideal conductors, by the static surface charge distribution [12]. An early example of the CM loss evaluation for a rectangular conductor, together with a discussion of the accuracy of the surface resistance approach when conductors with sharp rectangular edges are considered, is presented in [13]. On the basis of the CM approximation of the surface current density, closed-form expressions have been presented for the losses of coplanar waveguides (CPWs) and coplanar striplines (CPSs) [14]–[17] and of symmetrical CPW couplers [18]. Expressions for the CPW attenuation were also presented in [19, Sec. 7.4.2], based on Wheeler’s incremental inductance rule [20], and in [21], where a stopping-distance formulation is adopted that leads, in the high-frequency limit, to the result in [14]. The loss analysis of MCLs with conductors plus a ground plane, where and no symmetries exist that allow for even- and odd-mode excitations [18], requires to introduce a set of linearly independent mappings, corresponding to suitable line excitations. This technique, first proposed in [22] for the evaluation of the capacitance matrix of zero-thickness multicon-

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ductor striplines, was extended in [23] to the case of zero-thickness MCPWs and MCPSs. For MCPWs, a suitable set of mappings corresponds to boundary conditions where, in mapping , the ground planes are at zero potential, strip is at potential 1, and strips have zero total charge. For MCPSs, a suitable dual set for mapping is given by strips being at potential 1, while all other strips and the rightmost ground plane are at zero potential. In the presence of thick strips, however, an intermediate mapping is needed to transform the thick line into a zero-thickness one. Such a mapping has a dual purpose: 1) to lead to a much more accurate approximation of the capacitance matrix in the presence of thick conductors and 2) to introduce a square-integrable representation of the surface current density. The total surface current density can be approximated as a superposition of linearly independent excitations associated to the mappings; this enables to directly express, through the surface resistance , the dissipated power density, and to estimate the per-unit-length (p.u.l.) resistance matrix by integrating it on the line and ground plane peripheries. A partial preliminary report on MCL skin-effect losses was presented in [24]. The analytical approximations discussed are consistent with the results in [14]–[16] in the thin strip limit, but the present formulation not only applies to an arbitrary number of conductors, but provides a more accurate estimate of the p.u.l. resistance, inductance, and capacitance (matrices) for thick lines. The examples shown suggest that the technique is accurate even for a strip thickness as large as 40% of the minimum slot and strip width. This paper is organized as follows. Section II reports a summary of the CM procedure for the lossless case, extending the treatment to finite-thickness lines. Section III is devoted to the loss analysis, whose results are reported in Sections III-A and III-B for the MCPW and MCPS, respectively. Section IV briefly introduces the characteristic modal parameters for an MCL supported by a semi-infinite dielectric substrate. Analytical details on the thick-to-thin strip transformation are reported in the Appendix, Section A. Section V is devoted to some numerical examples, while conclusions are drawn in Section VI.

II. CM ANALYSIS Let us summarize the CM procedure introduced in [23] focusing the analysis of the line in vacuo, which is the basis for the evaluation of the p.u.l. resistance matrix of the MCL. As already recalled, the high-frequency current density distribution of the line corresponds to the static charge distribution. Since this distribution is not square integrable in a line with infinitely thin conductors, we extend, as a first step, the analysis of zero-thickness MCLs [23] to lines with conductors having finite thickness . To this aim, an additional Schwarz–Christoffel (SC) mapping is introduced. The mapping, defined in (1), transforms the upper half of the finite thickness structure ( -plane, line half thickness

Fig. 2. Thick-to-thin mapping for the MCPW (upper half space). (a) -plane. (b) Transformed plane.

Fig. 3. Thick-to-thin mapping for the MCPS (upper half space). (a) -plane. (b) Transformed plane.

) into the upper half of the zero-thickness structure ( -plane) (see Figs. 2 and 3 for the MCPW and MCPS case, respectively). For both lines, the mapping reads

(1) If is suitably smaller than the strip and slot widths, (1) can be approximately integrated on the strip lateral sides, strip tops, and slots (see the Appendix, Section A). This enables to define the strip and slot coordinates in the plane in terms of strip and slot width corrections. Physically, the extra capacitance introduced by the thick strips translates into an increase of the strip widths and decrease of the slot widths in the transformed zero-thickness structure having the same capacitance. Consider first an MCPW with strips; the coordinate index in the and planes goes from 1 to . The -plane coordinates are defined in terms of the strip widths ( ) and the slot widths ( ) as (2) (3) (4) The plane coordinates can be now recovered adopting the strip side length and width corrections reported in (14) and (15), respectively, and the slot width correction in (16), (5) (6) (7)

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where the strip side correction results to be approximately independent on the strip index. Similarly, for an MCPS with strips and a lateral ground plane (strip ), the plane coordinates read

3

(17)

(8) (9) (10) while for the

plane coordinates, we have (18) (11) (12) (13)

where the MCPS strip side length and width corrections are reported in (14) and (17), respectively, and the slot width correction is in (18). Expressions for the parameters , , and are discussed in the Appendix, Section A; the expressions for and are novel and more accurate than those previously available in the literature (cf. [14, p. 51, eqs. (18) and (19)] and [19, Sec. 7.3.3]). We have for both the MCPW and the MCPS, independent of the strip (or ground) side considered, (14) see (60) and (61). Following the discussion presented in the Appendix, Section A, the MCPW strip and slot corrections read

Using (14)—(18), the finite-thickness MCPW or MCPS can be mapped on the corresponding zero-thickness structures in the plane. From the zero-thickness structure we evaluate the line parameters following [23] (see Sections II-A and II-B). Since a system with strips plus ground plane supports independent excitations, the analysis of the p.u.l. capacitance matrix in vacuo , where is the capacitance matrix of the upper half of the line, requires a system of SC mappings (see [23, Sec. 2.1 and 2.2]. In Sections II-A and II-B, we will summarize the CM procedure for MCPWs (Section II-A) and MCPSs (Section II-B) following the matrix notation of [23] and only reporting results relevant to loss analysis. A. MCPW

(15)

To evaluate the upper half-space in vacuo capacitance of the MCPW, , a set of SC mappings is introduced transforming the upper half -plane into the interior of a rectangle in the -plane; an example with is shown in Fig. 4. In the th mapping, the th line is on top of the rectangle, the ground plane, extending to infinity in the and -planes, is at the bottom of the rectangle, and all remaining strips are folded on the rectangle sides, parallel to the top and bottom sides. Defining , the th mapping reads (19)

(16)

or, equivalently, the coefficients of The parameters the polynomial expansion can be determined imposing that the th strip is unfolded in the -plane while the others are folded in point ; this corresponds to the conditions

(20) For the MCPS, we similarly have (21) (22)

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Fig. 4. (a)–(c) Set of SC mappings for a three-conductor symmetric MCPW. The ground planes are drawn as black segments, white segments are magnetic walls, the th conductor is dark grey, while the other ones are pale grey. The , . right-hand side planes are to scale, assuming The normalized static charge, i.e., the high-frequency surface current density distribution, is shown in the left side (above) for each mapping. All strips but one have zero total charge (current), while the charge (current) carried by the unfolded strip has opposite sign with respect to the one in the ground plane.

where the integral is extended to strip and the rectangle width can be scaled arbitrarily without affecting the value of the capacitance or resistance p.u.l. matrices. From (19), conditions (20) and (22) can be written as (23) where (24) On defining the matrices , , , the above set can be expressed in compact form for all mappings ( ) as ; therefore, (25) which defines the coefficients of all sets of CMs. Following the procedure in [23, Sec. 2.1], we finally obtain the half-space capacitance matrix of the MCPW as (26) where the elements of Kronecker delta, and

are

,

is the

(27) The hyperelliptic integrals in (24) and (27) can be efficiently evaluated through Gauss–Chebyshev quadrature formulas as discussed in [23, Sec. 3]. For and for (symmetrical lines only), and can be expressed in terms of complete elliptic integrals.

Fig. 5. (a)–(c) Set of SC mappings for a three-conductor symmetric MCPS. Slots are drawn as white segments, the equipotential strips from 1st to th strip are pale grey, all other zero-potential strips are dark grey and the ground ) is black. White segments also denote magnetic walls. The plane (strip , . The right-hand side planes are to scale, assuming normalized static charge, i.e., the high-frequency surface current density distribution, is shown on the left side (above) for each mapping.

B. MCPSs In the complementary structure (MCPS), we have strips, the last one being the ground plane, separated by slots. To compute the in vacuo capacitance of the upper half of the MCPS, , we adopt the same set of SC mappings already introduced for the MCPW. In the th mapping, the outer slot (extending to ) is at the bottom of the rectangle in the -plane, the th one lies on top of the rectangle, and all other slots are folded. The width of the unfolded slot can be chosen arbitrarily. All strips are on the right-hand side of the rectangle, while those for are on the left-hand side. A convenient boundary condition, leading to a parallel-plate geometry, is as follows: all strips mapped on the right-hand side of the rectangle in the plane ( ) have potential , all strips on the left-hand side ( ), including the ground ( ) are grounded. As an example, the mappings for a three-slot MCPS are shown in Fig. 5. By imposing the folding and unfolding conditions, one can again derive the polynomial coefficient matrix as , where . Integration along strips [23, p. 71, left column, around eq. (26)] yields for the th mapping the strip widths in the transformed plane. On defining , we have (28) for the MCPW, can be [see (24) and (27)]. Note that , as scaled arbitrarily. Following the analysis in [23, Sec. 2.1], we finally obtain the half-space capacitance matrix in vacuo of the MCPW as (29) where . Note that the ground reference can be easily moved from strip to another one by defining the so-called augmented capacitance matrix .

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Introducing the potential of strip analysis yields for the elements of

, straightforward circuit

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A. MCPW Conductor Losses For the MCPW, mapping yields a total nonzero current in strip only and in the ground planes. Therefore, using (20)–(22) in (33), the total strip and ground planes currents in the th mapping can be expressed as

(30) By cancelling column and row , the capacitance matrix with the ground at strip is obtained. The same approach can be used if a set of strips is grounded to minimize coupling and crosstalk, as in MCPS interconnects with shield lines [25]. III. EVALUATING THE SKIN-EFFECT CONDUCTOR LOSSES For both the MCPW and MCPS, the square-integrable normalized (dimensionless) surface current density distribution in the plane is expressed, for the th mapping [see (19) and (1)] as

(31) taking into account that the current density in the th strip in the transformed plane is uniform due to the parallel-plate geometry. The real ( ) and imaginary ( ) parts apply to the MCPW and MCPS case, respectively. The surface current density in the upper half-space, , induced by an arbitrary excitation, can be represented as the superposition, with weights (unit A/m) of the resulting from all linearly independent mappings, (32) , The total current in the th line ( corresponds to the ground plane) is obtained from integration as

(34) Deriving and using (32), the surface current density resulting from the superposition of all mappings is (35) The total power dissipated p.u.l. on all lines and the ground plane can now be expressed as follows:

(36) where is the surface resistance, being the metal conductivity and the skin penetration depth. In (36), the integral on the th line (or on the ground plane for ) refers to the upper half space, and is the p.u.l. resistance matrix element that can thus be expressed as (37) derives from integration on strip , or on the where ground plane for . Taking into account the and mappings in (31), we have (38)

(33) where the integral refers to the strip upper half and the factor 2 takes into account the strip lower half. We will now evaluate the line current and the dissipated power for the MCPW (Section III-A) and the MCPS (Section III-B) case.

where the integral will be referred to as the loss integral of strip . The present treatment generalizes the analysis in [14], [15], and [18]; details of the evaluation of the loss integrals are omitted since the procedure closely follows [15]. The same result is obtained by integration of the edge-singular loss integrand of the zero-thickness line using the Lewin–Vainshtein (LV) high-frequency limit as the stopping distance [21]. The loss integral expressions can be extended down to the frequency range where by replacing the LV limit with the stopping distance , i.e., by setting [17] in (39), (40), (54), and (55), and by replacing with the generalized resistance defined in [21, eq. (8)]. In the high-frequency limit we obtain

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and, from (32), the upper half-plane surface current density reads (50) The total power dissipated on all lines and the ground plane can be expressed as a quadratic form of the strip total currents as follows: (39)

(40)

(51)

(41)

where the integral on the th line, or on the ground plane for , refers to the upper half space. Thus, the elements of the p.u.l. resistance matrix of the MCPS are expressed as in (37) with ,

where

(42)

(52) (43) plane, the

The resistance matrix elements can obtained from (37).

derives from integration on strip . Taking into account the mappings we have

or on the ground mapping and

B. MCPS Conductor Losses in (33) correspond In the MCPS case the terms to lines, while to the rightmost ground plane. Taking into account that integration of the MCPS th mapping yields

(53)

(44) (45)

Following an approach similar to the MCPW case, we obtain

(46) the line and ground plane currents can be expressed as (47) (54) (48) Equation (47) is a linear system with matrix (28); define , with elements ; inverting (47), one has (49)

(55)

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where , , and are again defined in (41)–(43), respectively. On defining the matrices , , , and , we have from (52) and (53) that the resistance matrix of the MCPS can be evaluated as (56) where . Notice that the reference ground can be moved from strip to an arbitrary strip by transforming the resistance matrix into the corresponding conductance matrix and deriving the augmented conductance matrix , following the same rule as for the capacitance matrix [see (30)]. From , the conductance matrix with ground at strip is recovered by canceling row and column ; inversion finally yields the desired with ground at strip . The same approach holds for an MCPS with a set of grounded shield lines.

Fig. 6. Conductor normalized attenuation of a symmetric CPW ( ) in vacuo as a function of line thickness with different values of the line width and slot width : numerical CM (diamonds) from [29]; present approach (black solid lines), formulas from [14] (blue dashed lines).

IV. CHARACTERISTIC p.u.l. PARAMETERS, MODAL IMPEDANCES, AND COMPLEX PROPAGATION CONSTANTS We refer to an MCL on an infinitely thick dielectric substrate with relative permittivity and conductivity . Given the in vacuo capacitance matrix of the upper half space , we have for the capacitance matrix, for the inductance matrix accounting for the skin-effect internal inductance, and for the conductance matrix associated to parallel substrate losses, where is the velocity of light in vacuo. Notice that the assumptions and only approximately hold for very thick lines, where the dielectric does not exactly fill one half space; thus the approximation signs. From the above matrices and , the p.u.l. impedance and admittance matrices can be evaluated as and . The modal complex propagation constants can be finally derived as the square roots of the eigenvalues of the product . The modal characteristic impedances according to the so-called power-current (PI), voltage-current (VI), and power-voltage (PV) definitions can be finally recovered through the eigenvector matrices of and [26]. V. EXAMPLES A few examples are discussed to test the consistency of the present approach with previously published quasi-static formulas and its accuracy versus quasi-static and full-wave EM formulations. We will also use as a reference solution the numerical SC solver discussed in [27] and [28] and used in [29] to evaluate the impedance and skin-effect losses of CPWs with arbitrarily shaped electrodes. In the examples shown the imaginary part of the characteristic impedance is negligible versus the real part, simply denoted as “characteristic impedance.” In all computations shown, the number of integration samples in the quadrature formulas [23, Sec. 3] is 20. Fig. 6 compares the normalized attenuation of a symmetric CPW in vacuo (MCPW with ) from the Owyang and Wu formula [14] with the present approach and the exact numerical CM solution from

) in vacuo as a Fig. 7. Characteristic impedance of a symmetric CPW ( function of line thickness with different values of the line width and slot width : numerical CM (diamonds) from [29]; present approach (black solid lines).

[29]. The present solution is in excellent agreement with the numerical CM also for line thickness as large as 40% of the strip or slot width, and provides a better approximation than the formulas in [14]. Fig. 7 compares the characteristic impedance of the same symmetric CPW in vacuo evaluated in the present approach and as in [29]; the agreement is again very good also for line thickness as large as 40% of the strip or slot width. Notice that in the approach of [14] the thick strip correction of the impedance is not considered. Fig. 8 compares, for the attenuation of a CPS (MCPS with ), the analytical expressions in [15] with the present approach and the exact numerical CM solution from [29]. As in the following examples, the frequency is GHz and the metal conductivity S/m. The present solution virtually coincides with the numerical CM and provides a better approximation than the formulas in [18], above all for low line spacing, as expected. Comparisons concerning the modal attenuations and characteristic impedances, respectively, between the present approach and a full-wave and quasi-static FEM solution are presented in Figs. 9 and 10 for a five-conductor MCPW in vacuo. The present closed-form approach clearly yields an accurate estimate of both

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Fig. 8. Conductor attenuation of an asymmetric CPS ( ) in vacuo as a m) or width (with m): function of line spacing (with present approach (black solid lines), formulas from [15] (blue dashed lines), m and numerical CM (diamonds) from [29]. The ground width is m. the conductor thickness is

Fig. 9. Modal in vacuo conductor attenuations of a uniform symmetric fiveconductor MCPW as a function of the line thickness: comparison between the present approach (black solid lines), quasi-static FEM (circles) [6], and fullwave FEM (diamonds) [5]. The line and slot widths are 50 m.

the attenuation and the modal impedances. Notice that the skin penetration depth at the operating frequency is nm; as is well known, the skin-effect approximation is, in this case, expected to be increasingly inaccurate for strip thickness with . To the authors’ best knowledge, no experimental data on the attenuation of MCLs are available; however, an indirect comparison can be made from the data on the attenuation of finite-ground CPWs on a lossy Si substrate reported in [30]. Fig. 11 shows a comparison between the measured and simulated total attenuation as a function of frequency for two sets of lines, with strip and slot widths of 25 and 50 m, respectively, and varying finite ground widths (only the extreme values are simulated). The substrate losses were taken into account, and a satisfactory fit with measurements was obtained with an average conductivity of the composite metallization S/cm. The accuracy of the simulation degrades at lower frequencies where the strip thickness becomes comparable to the skin penetration depth. The parameters of the finite-ground CPW were obtained from those of an MCPS with two conductors plus ground, by grounding the left-most strip.

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Fig. 10. Modal in vacuo characteristic impedances of a uniform symmetric five-conductor MCPW as a function of the line thickness: comparison between the present approach (black solid lines), quasi-static FEM (circles) [6], and fullwave FEM (diamonds) [5]. The line and slot widths are 50 m.

Fig. 11. Attenuation of a finite-ground CPW as a function of frequency for different values of the strip, slot, and finite-extent ground plane width. The cm and metal thickness is 3 m, the substrate is Si with resistivity 2500 . The measured curves from [30, Fig. 3(a) and (b)] are for ground widths between the two extremes considered in the simulation, namely, m (upper set, simulations with blue for m (lower set, and red dashed lines), and simulations with blue and red continuous lines). The measured and simulated . attenuation decreases with increasing

Figs. 12 and 13 compare the attenuation and effective refractive index of a five-conductor (plus ground) MCPS in vacuo with the results of quasi-static FEM as a function of frequency. Notice that the effective refractive index variation versus the in vacuo value, entirely related to conductor losses, is accurately reproduced by the analytical model. The modal patterns shown in the figure insets are qualitative only, due to the asymmetry of the structure. VI. CONCLUSIONS We have presented computationally efficient accurate closedform expressions for the conductor losses and the modal impedances of thick MCLs. With respect to already available expressions for single and coupled lines, the present approach provides an estimate of the line characteristic parameters that is accurate even for line thicknesses of the order of 40% of the minimum slot or strip width. The results compare favorably with numerical CM implementations and with quasi-static and full-wave FEM simulations.

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(57) i.e., (58) Fig. 12. Modal in vacuo conductor attenuations of a uniform five-conductor (plus ground) MCPS as a function of frequency: comparison between the present approach (black solid lines) and quasi-static FEM (circles) [6]. The line, slot, m. The and ground plane widths are 50 m. The conductor thickness is S/m. metal conductivity is

because (59) Similar results are obtained for the MCPW strip sides of even index and for the MCPS. It follows that each strip edge (including the ground planes) should be extended in plane by an amount that, in the first approximation, does not depend on the strip or ground plane width

(60) (61)

Fig. 13. Modal in vacuo effective refractive index of the five-conductor (plus ground) MCPS (see Fig. 12) as a function of frequency: comparison between the present approach (black solid lines) and quasi-static FEM (circles) [6].

Let us consider integrating transformation (1) on the strip tops. For simplicity, let us confine the detailed treatment to the MCPW strips and slots. We have (62)

APPENDIX Strip Side, Strip, and Slot Width Corrections due to Finite Conductor Thickness: The transformation (1) cannot be inverted explicitly; however, if , we can approximately invert the transformation for each strip side, strip top, and each slot, accounting for the effect of nearby strips and slots. Let us consider first the correction related to the thick conductor (strip or ground plane) side. Consider first the MCPW case; we have ( )

(63) The strip integral (62) can be approximated as follows:

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The integral in (67) can be solved exactly in terms of complete elliptic integrals of the second kind [31, p. 308, eq. (14)], and further approximated through the formulas in [31, Sec. 8.114, eq. (3)], assuming ; this leads to the result (64) where is the average coordinate of strip in the plane, which is approximated, to make the expression explicit, as , where (65) The integral in (64) can be solved exactly in terms of complete elliptic integrals of the first and second kind [31, p. 308, eq. (10)] and further approximated through the formulas in [31, Sec. 8.113, eq. (3) and Sec. 8.114, eq. (3)] under the assumption , leading to the result

(69) Combining (69) with (67) and in the assumption of small , we obtain (16). The treatment of the MCPS strip and slot corrections is similar, leading to the results reported in (17) and (18). Notice that no strip or slot corrections are applied when the strip or slot has infinite extent. REFERENCES

(66) Combining (66) with (64) and under the assumption of small , we finally obtain (15). Similarly, the slot integral (63) can be approximated as follows:

(67) where (68)

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[17] M. Duyar, V. Akan, E. Yazgan, and M. Bayrak, “Analytical attenuation calculation of asymmetrical coplanar waveguide with finite-extent ground planes for coplanar waveguide mode,” Microw. Opt. Technol. Lett., vol. 49, no. 9, pp. 2082–2087, 2007. [18] G. Ghione and M. Goano, “A closed-form CAD-oriented model for the high-frequency conductor attenuation of symmetrical coupled coplanar waveguides,” IEEE Trans. Microw. Theory Techn., vol. 45, no. 7, pp. 1065–1070, Jul. 1997. [19] K. C. Gupta, R. Garg, I. Bahl, and P. Bhartia, Microstrip Lines and Slotlines, 2nd ed. Norwood, MA, USA: Artech House, 1996. [20] H. A. Wheeler, “Formulas for the skin effect,” Proc. IRE, vol. 30, no. 8, pp. 412–424, Sep. 1942. [21] C. L. Holloway and E. F. Kuester, “A quasi-closed form expression for the conductor loss of CPW lines, with an investigation of edge shape effects,” IEEE Trans. Microw. Theory Techn., vol. 43, no. 12, pp. 2695–2701, Dec. 1995. [22] L. J. P. Linnér, “A method for the computation of the characteristic immittance matrix of multiconductor striplines with arbitrary widths,” IEEE Trans. Microw. Theory Techn., vol. MTT-22, no. 11, pp. 930–937, Nov. 1974. [23] G. Ghione, “An efficient, CAD-oriented model for the characteristic parameters of multiconductor buses in high-speed digital GaAs ICs,” Analog Integr. Circuits Signal Process., vol. 5, no. 1, pp. 67–75, Jan. 1994, (also in M. S. Nakhla and Q. J. Zhang, Modeling and Simulation of High Speed VLSI Interconnects, Berlin, Germany: Springer, 1994, pp. 67–74. [24] G. Ghione, M. Goano, and C. U. Naldi, “A CAD-oriented model for the ohmic losses of multiconductor coplanar lines in hybrid and monolithic MIC’s,” in Gallium Arsenide Appl. Symp., Paris, France, Jun. 1996, p. 8A2. [25] Interconnect Noise Optimization in Nanometer Technologies, M. A. Elgamel and M. A. Bayoumi, Eds. Berlin, Germany: Springer, 2006. [26] C. R. Paul, Analysis of Multiconductor Transmission Lines, 2nd ed. New York, NY, USA: Wiley, 2007. [27] T. A. Driscoll, “Algorithm 756: A MATLAB toolbox for Schwarz–Christoffel mapping,” ACM Trans. Math. Softw., vol. 22, no. 2, pp. 168–186, Jun. 1996. [28] T. A. Driscoll and L. N. Trefethen, Schwarz–Christoffel Mapping. Cambridge, U.K.: Cambridge Univ. Press, 2002. [29] M. Goano, F. Bertazzi, P. Caravelli, G. Ghione, and T. A. Driscoll, “A general conformal-mapping approach to the optimum electrode design of coplanar waveguides with arbitrary cross section,” IEEE Trans. Microw. Theory Techn., vol. 49, no. 9, pp. 1573–1580, Sep. 2001. [30] G. E. Ponchak, L. P. B. Katehi, and E. M. Tentzeris, “Finite ground coplanar (FGC) waveguide: Its characteristics and advantages for use in RF and wireless communication circuits,” in 3rd Int. Wireless Commun. Conf. Dig., Nov. 1998, pp. 75–83. [31] I. S. Gradshteyn and I. M. Ryzhik, Tables of Integrals, Series, and Products, A. Jeffrey, Ed., 5th ed. San Diego, CA, USA: Academic, 1994. Francesco Bertazzi received the Laurea and Ph.D. degrees in electronics engineering from the Politecnico di Torino, Turin, Italy, in 2000 and 2003, respectively. From 2004 to 2008, he was Visiting Scholar with Boston University. Since 2008, he has been a Professor with the Dipartimento di Elettronica e Telecomunicazioni, Politecnico di Torino. His research activity is focused on the modeling of electronic transport in nanodevices by means of full-band Monte Carlo and nonequilibrium Green’s function techniques. His interests also include recombination mechanisms in light emitters, electromagnetic propagation, and noise in microwave devices. Vittorio Camarchia (S’01–M’04–SM’14) received the Laurea degree in electronic engineering and Ph.D. degree in electronic and communications engineering from the Politecnico di Torino, Turin, Italy, in 2000 and 2003, respectively. In 2001, 2002, and 2003, he was a Visiting researcher with the Electrical and Computer Engineering (ECE) Department, Boston University, Boston, MA, USA. He is currently an Associate Professor with the Dipartimento di Elettronica e Telecomunicazioni, Politecnico di Torino. His

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research is focused on RF device modeling, simulation, and characterization, both linear and nonlinear, and power amplifier design. Dr. Camarchia was the recipient of the 2002 Young Graduated Research Fellowship presented by the Gallium Arsenide application Symposium (GAAS) Association. Michele Goano (M’98) received the Laurea and Ph.D. degrees in electronic engineering from the Politecnico di Torino, Turin, Italy, in 1989 and 1993, respectively. In 1994 and 1994, he was a Post-Doctoral Fellow with the Département de Génie Physique, École Polytechnique de Montréal, Montréal, QC, Canada. In 1998 and 1999, he was a Visiting Scholar with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA. In 2000 and 2001, he was a Visiting Scholar with the Department of Electrical and Computer Engineering, Boston University, Boston, MA, USA. Since 1996, he has been with the Dipartimento di Elettronica e Telecomunicazioni, Politecnico di Torino, Turin, initially as a Research Assistant and, since 2005, as an Associate Professor. His current research activity is focused on the simulation of (opto)electronic devices based on narrow- and wide-bandgap semiconductor materials. Marco Pirola (M’97) was born in Velezzo Lomellina, Italy, in 1963. He received the Laurea degree in electronic engineering and Ph.D. degree from the Politecnico di Torino, Turin, Italy, in 1987 and 1992 respectively. In 1992 and 1994, he was a Visiting Researcher with the Microwave Technology Division, HewlettPackard, Santa Rosa, CA, USA. Since 1992, he has been with the Electronic Department of Politecnico di Torino, initially as a Researcher and, since 2000, as an Associate Professor. His current research concerns the simulation, modeling, and measurements of microwave devices and systems. Giovanni Ghione (M’87–SM’94–F’07) received the Laurea degree in electronic engineering (cum laude) from the Politecnico di Torino, Turin, Italy in 1981. He is currently a Full Professor of electronics with the Politecnico di Torino. He has authored or coauthored more than 300 research papers and five books. His research activity has been mainly concerned with high-frequency electronics and optoelectronics. He has contributed to the physics-based modeling of compound semiconductor devices with a particular interest in the numerical noise modeling in small- and large-signal regimes, in the thermal modeling of devices and integrated circuits, and in the modeling of widegap semiconductors devices and materials. He has also performed research in the field of microwave electronics with contributions in the modeling of passive elements, in particular coplanar components, and in the design of power monolithic microwave integrated circuits (MMICs). Since 1985, he has been actively engaged in research on optoelectronic devices with application to the modeling and design of near and far-infrared (far-IR) photodetectors, electrooptic, and electroabsorption modulators, and GAN-based LEDs. Prof. Ghione has been a Member of the QPC Subcommitee, IEDM (1997–1998 and 2006–2007) and Chair (2008). From 2009 to 2010, he was the EU Arrangement Co-Chair of IEDM. From 2010 to 2015, he was Chair of the EDS Committee on Compound Semiconductor Devices and Circuits. From 2007 to 2015, he was the Head of the Department of Electronics and Telecommunications, Politecnico di Torino. He is currently the Editor-in-Chief of the IEEE TRANSACTION ON ELECTRON DEVICES (2016–2018).

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Synthesis of Multiport Networks Using Port Decomposition Technique and its Applications Rakesh Sinha and Arijit De, Member, IEEE

Abstract—A systematic approach to synthesize multiport ( -port) network with desired characteristics, for a given network topology, has been proposed. The heart of the algorithm lies with a novel port decomposition technique introduced here, wherein a reduced two-port network (2PN) is obtained by short-circuiting ports of the original topology. This reduced the remaining network is easily analyzed in terms of its unknown design parameters and can be compared with the known characteristics to provide a subset of design equations. Iteratively proceeding with this approach, one can obtain the required synthesis equations for any multiport network, even when there exists no plane of symmetry. Utilizing this algorithm, four theorems pertaining to multiport network synthesis have been proposed. The first and second theorems establish the synthesis guidelines of an arbitrary-phased rat-race and branch-line type coupler having unequal (or equal) power division at the output ports, with a ring type topology consisting of arbitrary building blocks. The third theorem deals with the synthesis of a five-port network, and the final one provides the design equations for arbitrary phase difference coupler involving coupled lines. Index Terms—Arbitrary phase coupler, asymmetric two-port network, branch-line coupler, coupled lines, directed graph, five-port network, multiport network, network synthesis, port decomposition, rat-race coupler, unequal power division.

I. INTRODUCTION

I

N microwave and millimeter-wave regimes multiport networks are fundamental components of a wireless communication or a radar system. Examples of three-port networks like those in power dividers (PDs), four-port like in rat-race couplers (RRCs) and branch-line couplers (BLCs) to provide appropriate phase difference between the output ports, and five-/sixport networks for complex impedance measurement have been studied extensively. Traditionally, most of these networks have a defined plane of symmetry which enables the derivation of design equations using efficient even–odd-mode-based decomposition. However, in recent literature [1]–[5], several such circuits have been proposed, where plane of symmetry is difficult to define or may not even exist at all, and hence appropriate design equations cannot be derived easily using the conventional approach. One such case is for a power divider having unequal Manuscript received April 09, 2015; revised June 22, 2015; accepted February 13, 2016. (Corresponding author: Rakesh Sinha.) The authors are with the Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur 721302, India (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2532868

power division at the two output ports, which was analyzed by Cheng and Li in [4], using a variant of the traditional even–odd mode-based decomposition but with unequal excitations. The approach, though interesting, is difficult to extend for multiport networks like the case of RRCs and BLCs as in [1]–[3], [5] with existing asymmetry. To tackle this problem, Ahn et al. proposed a technique to decompose the four-port networks like the RRC [1], [3] and the BLC [2], [3] into simpler three-port power dividers. The underlying principle was the invariance of the scattering parameters corresponding to the excitation at the input port, when the isolation port is terminated by arbitrary load impedance. Reduction of the four-port to a three-port was carried out by directly removing the isolation port and its associated connectivity. It has been shown here, that such removal of the isolation circuit as a whole is incorrect. An alternate correct approach involving decomposition of the isolation circuit has been provided by short-circuiting the isolation port instead of removing the isolation circuit as a whole. This proposed technique has been referred to here as the port-decomposition method. Though the principle behind the port-decomposition has been established through the examples of the isolation port of the above-mentioned RRC and BLC, this technique can be simultaneously applied to any number of ports (not only isolation port), as discussed in this paper. Considering the fact that the topology of any multiport network can be viewed as an interconnection of multiple two-port network building blocks (TPN) or otherwise, an algorithm has been proposed to synthesize any such multiport network with a given scattering matrix, using the proposed port-decomposition technique. Given an N-port network topology, it can be reduced to a simple 2-port network (2PN) by decomposing the rest of the ports. This 2PN can be analyzed easily in terms of the unknown network parameters of the TPNs. Correspondingly, a new set of two-port scattering parameters can be calculated from the given N-port S-parameters using [8], (8). One can obtain a subset of desired design equations by equating the unknown 2PN parameters with the calculated one. Performing these operations iteratively, the entire set of design equations can be obtained. This provides a robust and systematic method for obtaining the design equations for a multiport network, without the use of plane of symmetry or otherwise. The multiport network synthesis algorithm has been applied to synthesize a generalized RRC (GRRC), a generalized BLC (GBLC), a rotationally symmetric five-port network (5PN) having ring topology consisting of generalized building block and an generalized phase-difference coupler (GPDC) consisting of

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Fig. 1. (a) Three-element dipole array fed by three identical phase (conventional 90 ) RRC and additional different phases (60 , 90 and 120 ) using DLs. (b) Three-element dipole array fed by three different transmission phase (60 , 90 , and 120 ) RRC.

coupled lines. The term “generalized” is used in the sense that the couplers exhibit both arbitrary transmission phase shift and unequal power division at the output ports. The absolute transmission phase of an RRC [6] has not been considered previously in literature. It has been shown here that one can design such couplers to provide arbitrary phase shift. The arbitrary transmission phase branch-line type coupler [7] is a generalized version of the conventional BLC and provides a phase difference other than 90 between the two output ports. The importance of transmission phase can be demonstrated through an example shown in Fig. 1(a) and (b). Consider a three-dipole array differentially fed through three identical conventional RRCs (each having 90 transmission phases). In order to steer the beam in the desired direction, appropriate phase differences are introduced among the array elements using three different (60 , 90 , and 120 ) delay lines (DLs), as shown in Fig. 1(a). In another configuration shown in Fig. 1(b), three different transmission phase shift based RRCs (60 , 90 and 120 ) described here, can be used to simultaneously provide a differential feed and the desired phase difference among the array elements, thus getting away with additional delay lines. This shows the merit of the transmission phase and its incorporation in design equations. Four theorems have been proposed to provide the design equations of the GRRC, GBLC, 5PN using arbitrary TPNs and GPDC consisting of coupled lines. The theorems have been established using the multiport synthesis algorithm. The conditions stated in the theorems along with proper parameterization leads to multiple choices of design parameters. A special case arises when the choice of TPNs are restricted to single-stage transmission lines (TLs). The design equations obtained henceforth have been validated with those in the existing literature as [5], [6], [9], [10] for RRC, [7], [11] for BLC, [12] for the 5PN, and [13] for the GPDC. A prototype GRRC has been designed and fabricated, and its measured results have been found to be close agreement with the desired one. This proves the usefulness of the proposed theorems. The remainder of this paper is organized as follows. The background behind the proposed port decomposition technique is established in Section II with appropriate examples. Section III describes the algorithm for synthesis of a multiport network utilizing the port decomposition technique. Finally, applications of the above algorithm have been laid down in the form of four Theorems in Section IV, followed by experimental verification in Section V.

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Fig. 2. (a) -electrical length RRC with input at port-1 and the isolation port (port-4) terminated by arbitrary load. (b) Equivalent circuit (as in [1]) of (a) for port-1 excitation.

II. CONCEPT OF PORT DECOMPOSITION Here, two examples have been demonstrated showing the failure of the previous method as in [1]–[3]. The correct approach of reduction of a circuit topology to lower the number of ports for efficient analysis by appropriate port decomposition has been discussed for each case. A. Arbitrary Phase RRC An arbitrary-phase RRC with port impedances of all of the four ports being has been shown in Fig. 2(a). The RRC consists of four TLs with characteristic impedance , three of them with electrical length , and the last one of . is given by [6] (1) The four-port scattering parameters of this RRC at the resonance frequency can be written as (2a)

where is the absolute phase shift with zero reference phase at the ports, which was not considered in literature [6]. The phase shift related to electrical length using the following relationship: (2b) The input signal incident at port-1 will be equally divided at port-2 and port-3 with same phase shift of . Port-4 remains isolated with respect to the incident input signal. When port-4 is terminated by arbitrary load impedance as shown in Fig. 2(a), the three-port -parameters (RRC3P) can be written using (A2) as

(3) It is clear from (3) that the -parameters for excitation at port-1 (i.e., , , and ) are independent of the load reflection coefficient . Utilizing this concept in [1], the TLs associated with port-4 (isolation network) were removed and the reduced

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3

Fig. 3. (a) Arbitrary-phase RRC with input at port-1 and the isolation port (port-4) short-circuited. (b) Equivalent circuit of (a).

TABLE I PERFORMANCE COMPARISON OF THE DECOMPOSITION AS IN [2] AND THE PROPOSED APPROACH FOR RRC

Fig. 4. (a) Arbitrary-phase BLC with its isolation port (port-4) terminated by . (b) Equivalent circuit (as in [2]) of (a) for port-1 excitation. load

the RRC with -TL only, although the proposed concept of removing the isolation network as a whole was incorrect. B. Arbitrary-Phase BLC

power-divider type network as shown in Fig. 2(b) was claimed to be equivalent to the RRC3P of (3). However, claiming such equivalence was a fundamental mistake, because was uncorrelated to port-1 excitation due to presence of the isolation network only. If the isolation network is removed from the RRC, the -parameters corresponding to the excitation at port-1 will not remain the same as those in (3). Consider the PD shown in Fig. 2(b), whose -parameters can be written as

Another example of a coupler with equal power division but unequal phase shifts at the two output ports has been shown in Fig. 4(a). It consists of two -TLs with characteristic impedances and two others of electrical lengths and with characteristic impedance . For the general case, and can be given using [7] as (5a) (5b) The four-port scattering parameters of this arbitrary-phase BLC at the resonance frequency can be written as

(4a) (6a) (4b) It can be clearly observed that the port-1 -parameters of (3) and (4) are identical only when (i.e., a -TL) and not true in general for other values of . A correct approach of the decomposition will henceforth be described. The isolation network connected at port-4 of the RRC can be decomposed only when signal excited at port-1 transmitted to port-2 (3) through path P12 (P13) only and no transmission through path P132 (P123). The transmission through the path P132 (P123) will be zero only when port-4 is terminated by short circuit as a special case of arbitrary load termination. The three-port network for short-circuited termination can be redrawn as in Fig. 3(a), where the TL connected to port-4 is decomposed into two short-circuited shunt stubs connected to port-2 and port-3, respectively. The reduced form of the circuit, where shunt stubs are replaced by shunt impedances and is shown in Fig. 3(b). The scattering parameters of the original RRC3P shown in Fig. 2(a), the equivalence claimed in [1] Fig. 2(b), and the proposed equivalence as in Fig. 3(b) for has been calculated and tabulated in Table I. For the special case of , and become infinite, and Fig. 3(b) boils down to that in Fig. 2(b). This explains why the proposed methodology in [1] was valid for the design of

and The phase shifts at the output ports at port-1 are and 180 , respectively, with

with excitation given by (6b)

Port-4 remains isolated with respect to the incident input signal. As in the case of the RRC3P, when this port is terminated by arbitrary port impedance , its three-port -parameters (BLC3P) can be written as

(7) Following the principle depicted in [1], the reduced PD-type network [2] was arrived at in Fig. 4(b), the -parameters for port-1 excitation of which can be written as (8a) (8b) (8c)

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Fig. 6. General (asymmetric or symmetric) TPN used as building block and its directed representation in a network topology.

Fig. 5. (a) Arbitrary-phase BLC with input at port-1 and its isolation port (port-4) short circuited. (b) Equivalent circuit of (a).

TABLE II PERFORMANCE COMPARISON OF THE DECOMPOSITION AS IN [3] AND THE PROPOSED APPROACH FOR BLC

Fig. 7. (a) Five-port network with arbitrary topology. (b) Reduced 2PN of (a) when port-2, -4, and -5 are short-circuited.

The -parameters of the BLC3P as given in (7) and Fig. 4(b) as in (8) are the same only when (i.e., -TL) and differs for other values of . One thus arrives at a similar conclusion as before, and the equivalence by removing the isolation network is hence incorrect. The correct approach of isolation port decomposition using the philosophy discussed before is only possible when the isolation port of the coupler is terminated by short circuit and the signal traverses through the path P12 (P123), as shown in Fig. 4(a). The reduced form of the circuit is shown in Fig. 5, where the shunt stub connected across port-1 is open-circuited at port-1 and that across port-3 is represented by the shunt impedance . For the conventional BLC with , the proposed decomposition in Fig. 5(b) reduces to that of Fig. 4(b). A comparison of the -parameters for port-1 excitation for is shown in Table II. The theory established above for four-port couplers can be extended to any arbitrary complicated multiport network, as discussed in Section III.

in Fig. 6, where the arrow head indicates port-2 and the arrow tail indicates port-1 of the TPN with the ABCD parameters shown in Fig. 6. As an example, consider a 5PN whose topology is shown in Fig. 7(a), consisting of an interconnection of six sets of TPNs represented by arrow with alphabets . Note that the topology is a directed graph in order to accommodate the asymmetry of the TPNs. The ports are represented by circles with integer numbers 1–5. The principle of the algorithm is to decompose the 5PN into several feasible 2-port networks (2PNs) at each step via port decomposition, as discussed in the previous section. For example, one can choose port-1 and port-3 as the part of the 2PN and decompose the rest of the ports, viz. port-2, -4, and -5 by short-circuiting them. Therefore, the TPNs and can be removed in the reduced network, as both the ports corresponding to and are short=circuited. The TPNs and whose port-2 (refer to Fig. 7) and whose port-1 have been short-circuited can be converted into equivalent shunt admittance, the values of which are given by

III. MULTIPORT NETWORK SYNTHESIS USING PORT DECOMPOSITION

(9a)

The principle behind the decomposition of a port has been established in the previous section. Note that, though the examples were chosen to illustrate the port decomposition corresponding to the isolation circuit, the approach can necessarily be applied to any multiple numbers of ports (not necessarily an isolation port) of a multiport network, and hence one can obtain a reduced network to facilitate systematic analysis and formulation of design equations. The algorithm to synthesize a multiport network using the port-decomposition approach is discussed here, and its applications are illustrated in the following sections. In order to illustrate the algorithm, it is assumed that a large multiport network consists of interconnections of several two-port building blocks (TPN). Later, it will be shown that the method is applicable to complicated building blocks with a larger number of ports. In general, the TPNs can be asymmetric in nature and hence are best represented with an arrow shown

(9b) Here, the subscript-1 (2) refers to the case where port-2 (1) of the TPN has been short-circuited. The reduced 2PN is shown in Fig. 7(b). Such smaller networks are feasible in the sense that there exists transmission between the two ports and they can be analyzed easily with the unknown design parameters, and one can generate sets of design equations facilitating the synthesis of the larger complex network. Note that, if one chooses port-1 and port-2 as part of the 2PN and decomposes the rest of the ports, viz. port-3, -4, and -5 by short-circuiting, the reduced network has no signal transmission between the ports and would be infeasible. The systematic way to derive the design equations for a complicated multiport ( -port) network with known scattering matrix of dimension is given here.

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Step 1) Choose appropriate topology of the -port network consisting of two-port building blocks (TPN) with their ABCD parameters

,

The ABCD parameters of the reduced 2PN shown in Fig. 7(b) is given as

belonging

to the set , where such that there always exists a path between any two pair of nodes. As an example the 5PN shown in Fig. 7(a), consists of interconnections of six TPNs belonging to the set . Step 2) Choose two arbitrary ports among the -ports and decompose the rest of the -2 ports by short-circuiting them, such that after decomposition the reduced network is feasible. In other words, there exists a transmission between the ports. For the previous example, one can choose port-1 and port-3 as a part of the reduced set and decompose port-2, port-4, and port-5 by short-circuiting them. Step 3) Calculate the reduced set scattering parameters of the decomposed network from the known with the load reflection coefficient at the -2 ports being using [8]. Here, is the identity matrix of dimension . For the given example, the 5PN can be calculated using [8] as

(10) denotes the calculated scattering paramwhere eters between ports and . Here, and represents port-1 and port-3 of the original 5PN as in Fig. 7(a). Note that the calculated -parameters are known quantities. Step 4) Convert the 2-port scattering parameters (calculated in step 3) into a suitable two-port representation as an example, with the corresponding ABCD parameters given by

(11) Step 5) Determine the reduced 2PN by removing those TPN blocks with both its ports short-circuited and converting TPN blocks whose single ports are short-circuited into equivalent shunt admittance using (9). Determine the ABCD parameters of the 2PN in terms of the unknown parameters belonging to the set . In the previous example, the TPNs and are removed and , and are converted into the equivalent shunt admittance as discussed before.

(12) Note that these ABCD parameters are a function of the unknown network parameters of the building blocks belonging to the set . Step 6) Equating the ABCD parameters derived in step 5) to those calculated in step 4), one can obtain a subset of the required design equations. Step 7) Repeat steps 2)–6) with a different choice of two ports as part of 2PN, until a unique and complete set of design equations is obtained. This is illustrated using four examples in the following section. In Section IV, we will discuss four theorems on the design equations of a generalized RRC and BLC, a 5PN with equal power division at the output ports, using general asymmetric TPNs as building blocks and a generalized phase-difference coupler consisting of coupled lines. The theorems have been established based on the above algorithm for multiport network synthesis. IV. APPLICATION OF MULTIPORT NETWORK SYNTHESIS It is a common misconception that symmetrical multiport networks can be synthesized using symmetrical transmission line (or equivalent symmetric two-port building blocks). However, it has been shown in [5], that an asymmetric two port building block can be used to synthesize a symmetric four port network (the conventional 90 RRC), even though the building blocks are themselves not electrically symmetric. Here, we will extend this idea to the design of symmetric four-port and five-port networks using asymmetric TPNs, thereby laying down the synthesis equations for the more general case using the port decomposition approach. Further we will show the efficacy of the procedure for solving complex examples like those involving coupled lines. Such general forms of the design equations are not yet available in existing literature. A. Generalized RRC A conventional RRC provides and transmission phase between the input and the output for sum port and difference port excitation. The arbitrary-phase RRC [6] shown in Fig. 2(a), whose four-port scattering parameters are provided in Fig. 2(a) provides a transmission phase shift of and for port-1 and port-4 excitation. The arbitrary-phase RRC can be further generalized to having unequal power division [9] at the output ports and is referred to as GRRC. Herein, we consider synthesis of such GRRCs with general building blocks (TPNs) instead of the conventional transmission lines as in Fig. 2(a). The four-port network topology arranged in ring configuration, using two identical asymmetric TPNs and two different TPNs and is shown in Fig. 8(a). As the network is lossless passive and reciprocal, the ABCD parameters corresponding to TPNs , , and are defined as (13)

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Fig. 9. Various TPNs. (a) Asymmetric tapered line. (b) Asymmetric steppedimpedance line. (c) Asymmetric T-Network. (d) Asymmetric II-Network.

Fig. 8. (a) Generalized RRC with asymmetric TPNs as its building block. (b)-(d) Reduced 2PN of (a) with port- and port- short-circuited and portand port- of the GRRC being represented by port-1 and port-2 of the 2PN with , , , (c) , , , , and (d) , (b) , , .

with and the subscript . This type of lossless reciprocal TPNs block with network parameter as in (13) can be implemented by any of the following 2PN shown in Fig. 9. As an example, design equations of asymmetric-T are discussed in Appendix B. For the corresponding four-port network to electrically represent the GRRC, the TPNs need to satisfy certain criteria specified in the theorem below. Theorem 1: A four-port network arranged in a directed ring topology shown in Fig. 8(a) is electrically identical with a GRRC having arbitrary transmission phase and unequal power division (1: n) at the output ports, with its scattering parameters given as

such iteration as Iter-i, Iter-ii and Iter-iii and finally combine the obtained subsets to prove the above-mentioned theorem. Iter-i: One can initially consider ports-1 and -3 of the GRRC as a part of the 2PN (with respective ports as and ) and decompose port-2 and port-4 by short-circuiting them as given in steps 1)–3) of the mentioned algorithm. Note that choice of such port-1 and -3 in Fig. 8(a) leads to a feasible 2PN as shown in Fig. 8(b). The scattering parameters of this new 2PN can be written in terms of the given GRRC (14) using (A3) as (16a) (16b) The above -parameters can be converted into the ABCD parameters using step 4) and (11) as (17) Following step 5) and (12) of the algorithm, the ring topology shown in Fig. 8(a) can be reduced to the 2PN shown in Fig. 8(b), and its corresponding ABCD parameters can be derived as

(14) provided the elements of the four-port ring network satisfy (15a) (15b)

(18) One can now equate (18) with (17) as in step 6) of the algorithm and obtain a subset of the design equation as (19a)

(15c) (15d) Proof: The heart of the proof lies with the algorithm sketched in the previous section for synthesis of a multiport network using port-decomposition approach. Note that there are three unknown TPNs indicated by . Hence, as described in step 7) of the algorithm, we choose three different sets of reduced 2PNs by appropriate decomposing of the respective ports and repeating steps 2)–6) of the algorithm, obtaining subsets of the design equations after each iteration. We label each

(19b) Iter-ii: We now choose port-1 and port-2 as a part of 2PN (with respective ports as and ) and decompose port-3 and port-4 by short circuiting them. The scattering parameters of this reduced 2PN can be written as (20a) (20b)

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7

Comparing (28a) and (28c), we have and . Using the above relations (28) and those in (19b) and (27b), one thus establishes

Converting the above into its ABCD parameters we have

(21) The ABCD parameters of the reduced 2PN show in Fig. 8(c) can be derived as

(29)

(22) Equating (22) with (21), one thus obtains another subset as

The inter-relationship between the TPNs , , and has been derived in (28a) and (29). This establishes the conditions stated in the above theorem for a GRRC. There exists an infinite set of solutions for and , , which satisfies the condition (15a) stated in the theorem. It is therefore convenient to parameterize and in terms of an angular variable , with as

(23a)

(30a)

(23b)

(30b)

Iter-iii: Choosing port-2 and port-4 as part of 2PN and decomposing port-1 and port-3, the scattering parameters can be given as

Utilizing Theorem 1, the network parameters of the TPNs can be expressed in terms of the above parameterization as (31a)

(24a) (24b)

(31b)

Converting them into the ABCD parameters, one has (31c) (25) The ABCD Fig. 8(d) canparameters be derivedofasthe reduced 2PN shown in

(26) Equating (26) with (25), one obtains the final subset as

(27a)

with . The above (31a)–(31c) are design equations of a GRRC with general TPNs as its building block. It is interesting to note that when , all the TPN blocks are symmetric in nature. Hence it is not possible to have a mixture of symmetric and asymmetric blocks to realize a GRRC. In most of the existing literature [6], [9], [10] the RRCs are implemented using transmission lines (symmetric) as the TPN building block. We first consider here a symmetric TL-based GRRC shown in Fig. 10(a), with the TPNs , and consisting of TLs with characteristic impedance , and of electrical lengths , and respectively. Equating (31a)–(31c) with the ABCD parameters of the respective transmission line, we have

(27b) (32a) We thus have expressed , of the TPNs, in terms of the power division ratio , transmission phase shift , and the port impedance as stated in the theorem. The inter-relation between the TPNs can now be obtained by substituting (19b), (23b), and (27b) into (19a), (23a), and (27a), yielding (28a)

(32b) (32c) (32d) (32e)

(28b) (28c)

(32f)

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Fig. 10. (a) Arbitrary phase ( ; ) and unequal power division ( ; ) RRC consisting of single section of transmission lines as its building block. (b) ; ) Arbitrary phase ( ; ) BLC and unequal power division ( consisting of single section of transmission line as its building block.

Fig. 11. (a) Conventional RRC having unequal power division with different line impedances. (b) RRC having phase shift with unequal power division with equal line impedance but different electrical lengths.

sisting of quarter wavelength transmission lines (i.e., as shown in Fig. 11(a). Using (33a)–(33d), we thus have

The solution of the above equation can be expressed in terms of the transmission phase , the power division ratio and the electrical length corresponding to the TL- as

(36a) (36b)

(33a)

(36c)

(33b)

(36d)

(33c) (33d) There exists infinite sets of possible designs of GRRC which provides similar response, for various choices of , provided lies in the region given by (34a) where

)

where (36a)–(36d) are the desired design equations as in [9]. 3) Case-3 [10]: We consider here a different philosophy of the unequal power division (i.e., ) RRC shown in Fig. 11(b). While in the previous case the transmission line lengths were fixed and impedance was a function of the power division ratio , thereby leading to extremely high impedances for high power-division ratio, making it difficult to realize in practice. We consider here a different approach as in [10] where the lines consist of equal characteristic impedance (i.e., ), but different electrical lengths depending on . Following (33a)–(33d), one arrives at

(34b) (37a)

(34c) We will now study some specific cases as in the existing literature and compare the usefulness of the theorem with the results provided there. 1) Case-1 [6]: We consider a small ( less than 90 ) electrical length RRC shown in Fig. 2(a), where both the element and consist of equal electrical length transmission lines of length (i.e., ) and equal power division at the output ports (i.e., ). Following (33a)–(33d), we thus have (35a) (35b) The design equations of the small electrical length coupler have thus been established with the help of the proposed Theorem-1, and agree with that in [6]. In addition, (35a) provides an idea of the transmission phase due to the coupler. 2) Case-2 [9]: Here we consider the conventional (i.e., ) RRC, but with unequal power division (i.e., ), con-

(37b) Solution of the above pair of equations leads to

(38a) (38b) Utilizing (38a) and (38b), one can rewrite (33a) as (39) which is same as that in [10]. In addition, one can obtain an estimate of the transmission phase due to such RRC. So far, we have considered RRCs with symmetrical transmission lines based building blocks. The conditions proposed in Theorem 1 encompass a much broader set of TPNs which

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Fig. 12. (a) Conventional RRC wavelength transmission line. (b) Equivalent RRC identical asymmetric TPNs.

9

with six identical quarter with six

can be symmetric or asymmetric in nature as illustrated by an example below. 4) Case-4 [5]: We consider here an asymmetric structurebased RRC with equal power division at the output ports i.e., , a transmission phase the same as in a conventional RRC (Fig. 12(a)) i.e., , with identical (but asymmetric) building blocks replacing each of the six quarter-wavelength TLs of the conventional RRC. The equivalent network topology of the asymmetric structure-based RRC is shown in Fig. 12(b). As the building blocks are identical, we have the network parameters of the TPNs and to be same, i.e., (40) Using Theorem 1, the conditions for the TPNs to represent the RRC are given as (41a) (41b) (41c) It is interesting to note that cascade of two lossless passive asymmetric TPNs satisfying the conditions given in (41a) is nothing but a 180 phase-shifter. In a mathematical notation, we have

Fig. 13. (a) GBLC with asymmetric TPN as its building block. (b)-(d) Reduced 2PN of (a) with port-i and port-j short-circuited and port-k and port-l of the , GBLC being represented by port-1 and port-2 of the 2PN with (b) , , (c) , , , , and (d) , , , .

and -3) for port-1 excitation and of for port-4 excitation. The arbitrary-phase BLC can be further generalized to having unequal power division at the output ports and is referred to here as a generalized BLC. Herein, we consider synthesis of such GBLCs with general building blocks (TPNs) instead of the conventional transmission lines as in Fig. 10(b). The four-port ring-type network topology using two identical asymmetric TPNs and two different TPNs and is shown in Fig. 13(a). Note that the topology is similar to that of the GRRC as described earlier [Fig. 8(a)], with the only difference being the notation of the ports. As the network is lossless passive and reciprocal, the ABCD parameters corresponding to TPNs , and are defined as in (13). The conditions for the ring shown in Fig. 13(a) to electrically represent a GBLC is specified via the following theorem. Theorem 2: A four-port network arranged in a directed ring topology shown in Fig. 13(a) is electrically identical with a GBLC having arbitrary transmission phase and unequal power division (1: n) at the output ports, with its scattering parameters given as

(42) Hence, (41c) can be expressed as a cascade of three identical (yet asymmetric) blocks as

(43) Thus, the obtained design equations using Theorem 1 are similar to those proposed in [5].

(44)

, provided, the with elements of the four-port ring network satisfies (45a)

B. Generalized BLC A conventional BLC provides transmission phase between the input and the output for both port-1 and port-4 excitation. The arbitrary-phase BLC [7] shown in Fig. 3(a), with its four-port scattering parameters as in Fig. 6(a), provides a transmission phase shift of at the two output ports (port-2

(45b) (45c) (45d)

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Proof: The theorem can be proved by the synthesis procedure of a multiport network using port-decomposition approach, in a similar fashion as in Theorem 1 for the case of GRRC. We perform the port-decomposition in three iterations labeled as Iter-i, Iter-ii and Iter-iii and finally combine them to prove the above mentioned theorem. Iter-i: If port-3 and port-4 of the GBLC are short circuited and port-1( ) and port-2( ) are considered to be part of the reduced 2PN, its scattering parameters can be calculated using (44) and (A3) as (46a)

It is required to equate (52) with (51) to obtain the second subset of the design equations. Hence, we have (53a) (53b) Iter-iii: Finally port-3( ) and port-4( ) are selected as part of the 2PN and rest of the port-1 and -2 are shorted. Then, the -parameters of the 2PN can be derived from the four-port -parameters (44) using (A3) as (54a)

(46b) One can convert the above set of scattering parameters into the ABCD parameters as

(47) The ABCD parameters of the reduced 2PN shown in Fig. 13(b) can be derived using the unknown parameters of TPN and as

(48) Equating (48) with (47), one can obtain the first subset of desired design equations as

(54b) The ABCD parameters can be obtained as

(55) After port decomposition, the ABCD parameters of the reduced II-type 2PN shown in Fig. 13(d) can be written in terms of unknown TPN parameters ( and ) as

(56) One can now equate (56) with (55) to get the final subset as

(49a) (49b)

(57a)

Iter-ii: In the case, we consider port-1 ( ) and port-4 ( ) as part of the reduced 2PN and port-2 and port-3 as shortcircuited. Then, the scattering parameters of the 2PN are

(57b)

(50a)

One can obtain the entire set of design equations after combining (49), (53) and (57) thus obtaining an inter-relationship between the TPNs ( , and ) stated in the Theorem-2 as

(50b) (58a) (50c) (58b)

The ABCD parameters of the above set are given as

(58c)

(51) The decomposed circuit can be redrawn as in Fig. 13(c) and the ABCD parameter of this circuit can be written in terms of unknown TPNs ( , and ) as

Note that, as before, it is convenient to parameterize in terms of an angular variable , with

and as (59a)

(52)

(59b)

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Utilizing Theorem 2, the general set of the network parameters of the TPNs can be expressed in terms of the above parameterization as

11

The solution of the above equation can be given as (63a)

(60a)

(63b) (63c)

(60b)

(63d)

with (63e) and

(60c)

For given transmission phase shift and power-division ratio , there exist an infinite number of possible designs of GBLC which gives the similar response, for various choices of , provided lies in the region given by

with . With the special choice of , we observe that, like before, all of the TPN blocks are symmetric in nature. In the existing literature [7], [10], most of the BLCs are implemented using a single section of a TL as its building block. Symmetry, i.e., does not necessarily imply that the TPNs can be implemented by a single section of a TL. It should be noted that the TPN blocks can be implemented by TLs (symmetric) provided satisfies the condition given by (61a) where (61b) The design equations for such TL-based GBLCs can be derived using the design equations of the general asymmetric (or symmetric) TPNs based GBLC as in (60). We consider here a symmetric TL based GBLC as shown in Fig. 10(b), with the TPNs , , and consisting of TLs of characteristic impedance , and and corresponding electrical lengths of , and . Equating (60a)–(60c) with the respective ABCD parameters of the transmission line, we have (62a) (62b)

(64a) where (64b) We will now study some specific cases as in the existing literature and compare the usefulness of the theorem with the results provided there. 1) Case-1 [11]: Consider a conventional (i.e., ) BLC with unequal power division (i.e., ) consisting of arbitrary length transmission lines. Then (63a)–(63d) reduces to the design equations as in [11] (65a) (65b) (65c) , the design equations are similar to that of the When conventional branch line coupler with unequal power division. 2) Case-2, [7]: We consider an arbitrary-phase (i.e., ) BLC with unequal power division (i.e., ) consisting of transmission lines with same characteristic impedance corresponding to element and (i.e., ). Then (63a)–(63d) reduce to the design equations as in [7] and are given as (66a) (66b)

(62c) (62d)

(66c) (66d)

(62e)

(66e)

(62f)

, these equations are similar to those as in (5a) and When (5b). We now try to address a complicated 5PN and establish the

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Fig. 15. Reduced circuit of Fig. 14(b) with ports-3, -4, and -5 as short-circuited. Fig. 14. (a) TL-based five-port equal power-division network. (b) Topology of a TPN-based five-port equal power-division network.

usefulness of the port decomposition approach, for a case even when no isolation port is present. C. Five-Port Network In the previous examples, we have demonstrated the application of the port decomposition algorithm for synthesis of GRRC and GBLC, both of which had isolation ports. It is to be noted that the port decomposition is not limited to such networks with isolation ports only. Here, we provide an example of an equal power-division rotational symmetric 5PN [12]. Such type of 5PN is generally implemented by five sections of identical transmission line with and as shown in Fig. 14(a). Following the philosophy of [5], it will be shown that such a complicated network can be implemented by five identical asymmetric TPNs- orientated identically as shown in Fig. 14(b), provided the network parameters of TPN- as in (13) satisfies the conditions stated in the following theorem. Theorem 3: A 5PN arranged in a directed ring topology shown in Fig. 14(b) is electrically identical with a conventional equal power-division 5PN as shown in Fig. 12(a), with its scattering parameters given as

The ABCD parameters of the above set can be written as (70) The ABCD parameters of the reduced 2PN shown in Fig. 15 can be expressed in terms of the unknown parameters of the TPNas (71) Equating (71) with (70), we obtain the desired conditions as stated in Theorem 3. This establishes the proof of the theorem. As discussed in the earlier cases, it is convenient to parameterize and in terms of an angular variable , with as (72a) (72b) Utilizing Theorem 3, the general set of the network parameters of the TPN can be expressed in terms of the above parameterization as (73)

(67) provided the elements of the 5PN network satisfies (68a)

The TPN will be symmetric when . With such a choice, one can implement the 5PN by a single section of a TL. By equating (73) with the ABCD parameters of a single section of TL of electrical length and characteristic impedance , one can obtain the desired design equations of a single TL-based 5PN as in [12]

(68b) Proof: Theorem 3 can easily be proved by multiport decomposition algorithm as discussed before. As all of the TPNs are identical, only a single iteration is enough to prove the above theorem. Consider port-1 and port-2 as part of the reduced 2PN denoted by ports and in Fig. 15, with the remaining ports 3, 4 and 5 being decomposed by short circuiting them. The scattering parameters of 2PN can be derived using (10) and (67) as (69a) (69b)

(74a) (74b) The versatility of the port decomposition approach will now be established for much more complex network topology consisting of coupled lines as building blocks. D. Generalized Phase-Difference Coupler A generalized phase-difference coupler (GPDC) can be realized using coupled lines as proposed in [13] and shown in

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13

Fig. 16. (a) Coupled line based DPC. (b) Topology of a symmetric-FPN and TPN-based DPC.

Fig. 16(a). It consists of a coupled line which can be represented as a four-port network (FPN) and two C-section coupled lines ( and ) represented as two-port networks (TPN). The GPDC provides a transmission phase shift of at the two output ports (port-2 and -3) for port-1 excitation and of for port-4 excitation. The phase difference between the two ports for a GPDC is thus and for port-1 and port-4 excitation, respectively, where it is and for the case of GBLC. Furthermore, for GBLC while is not restricted to 180 for GPDC; hence the GPDC can achieve arbitrary phase at the output. In [13], was chosen to be 90 and for ease of derivation; here we have considered the more general case where the electrical lengths are not limited to 90 . The DPC shown in Fig. 16(a) can be equivalently represented as a combination of TPN and FPN as shown in Fig. 16(b) provided the building blocks satisfies the following theorem. Theorem 4: A four-port network topology shown in Fig. 16(b) consist of a symmetric FPN and two symmetric TPN ( and ), is electrically identical with a GPDC having arbitrary transmission phase , phase difference , and unequal power division (1: n) at the output ports, with its scattering parameters given as

Fig. 17. Reduced 2PN of Fig. 16(b) with port-i and port-j short circuited and port-k and port-l of the GDPC being represented by port-1 and port-2 of the 2PN , , and (b) , , , . (c) with (a) , , , ; (d) , , , .

where

Proof: The theorem can be proved by the synthesis procedure of a multiport network using the port-decomposition approach. We perform the port-decomposition in four iterations labeled as Iter-i, Iter-ii, Iter-iii and Iter-iv, and finally combine them to prove the above-mentioned theorem. Iter-i: If port-3 and port-4 of the GPDC are short-circuited and port-1( ) and port-2( ) are considered to be part of the reduced 2PN, its scattering parameters can be calculated using (75) and (A3) as (77a) (77b)

(75) with , provided, the TPN and FPN elements of the network satisfies

One can convert the above set of scattering parameters into the admittance parameters as (78a)

(76a)

(78b)

(76b)

The -parameters of the reduced 2PN shown in Fig. 17(a) can be derived using the unknown parameters of TPN and the subset of the -parameters of the FPN , corresponding to port-1 and -2 (since port-3 and -4 are shorted) as

(76c) (76d)

(79a)

(76e)

(79b)

(76f)

Equating (79) with (78), one can obtain the first subset of desired design (76a) and (76b).

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Iter-ii: Consider now the port-4( ) and port-3( ) as part of the 2PN and rest of the ports-1 and -2 are shorted. The -parameter of the 2PN can be derived from the four-port -parameters (75) using (A3) as

(86a) (86b)

(80a) (80b) The

-parameters can be obtained as

(86c) The above scattering parameters can be converted to ABCD parameters given as

(81a) (81b) After port decomposition, the Y-parameters of the reduced II-type 2PN shown in Fig. 17(b) can be written in terms of unknown TPN parameters and the subset of the symmetric Y-parameters of the FPN , corresponding to port-3 and 4 (since port-1 and 2 are shorted) as (82a) (82b) One can now equate (82) with (81) to get the second subset of the design (76c) and (76d). Iter-iii: In the case we consider port-1( ) and port-3( ) as part of the reduced 2PN and port-2 and port-4 as short-circuited. Then the scattering parameters of the 2PN are

(87) The decomposed circuit redrawn in Fig. 17(d) with its ABCD parameters expressed in terms of the unknown ( , , ) as (88) It is required to equate (88) with (87) to obtain the final design (76f). If the FPN is implemented by a four-port coupled line and the TPNs are implemented by a two-port C-section coupled line, then the design equation of GPDC can be obtained by comparing the -parameters (C1) and (C3) with (76) as (89a)

(83a)

(89b)

(83b)

(89c)

(83c)

(89d)

The ABCD parameters of the above set are given as (89e)

(89f) (84) The decomposed circuit can be redrawn as in Fig. 17(c) and the ABCD parameters of this circuit can be written in terms of unknown TPNs ( , and ) as (85) It is required to equate (85) with (84) to obtain the design (76e). Iter-iv: Finally, we consider port-1( ) and port-3( ) as part of the reduced 2PN by short-circuiting port-2 and port-4. Then the scattering parameters of the 2PN are

where (90a) (90b) For given phase difference , power-division ratio , and , there exist an infinite number of possible designs of GDPC which gives the similar response, for various choices of , provided lies in the region given by (91a)

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TABLE III ABCD PARAMETERS OF THE ELEMENTARY TPNS

15

TABLE IV ELECTRICAL PARAMETERS OF THE ELEMENTARY T-STRUCTURES

where

(91b) The above result has been obtained considering (89c) and (89d) to be non-negative. Choosing , , and , one can obtain the desired design equations of the specific case discussed in [13]. The strength of the port-decomposition technique has thus been demonstrated with four examples leading to appropriate generalized design equations using arbitrary building blocks, laid down as Theorems for each such cases. Special choice of parameters reduces such generalized design equations to those in the existing literature. This shows the versatility of the approach in synthesizing complex networks (even without a plane of symmetry) which would not have been possible in such a systematic way by using even-odd mode based decomposition or otherwise. In Section V, we design and implement a prototype GRRC using Theorem 1 and validate it using full-wave simulations and measurement.

Fig. 18. Layout of (a) elementary T-structure and (b) GRRC constituted using the elementary building blocks with dimensions shown in Table V.

V. EXPERIMENTAL VERIFICATION In the previous section, we established four theorems dealing with GRRC, GBLC, a 5PN, and GPDC. Here, we design a GRRC with transmission phase and 3.0-dB amplitude imbalance (i.e., ) at the output ports, using asymmetric TPN. The ABCD parameters of TPN [see Fig. 8(a)] obtained using (15d) of Theorem 1, can be rewritten in terms of the mirror image of the TPN and quarter-wavelength TLs of characteristic impedance as

(92) with . The asymmetric parameters and as defined in (30) can be chosen to be 0 and 15 , and the ABCD parameters of the elementary TPNs , and (i.e., the quarter wavelength TL with characteristic impedance ) calculated using (31) and (92) are tabulated in Table III. These TPNs have been implemented using the T-structure as shown in Fig. 9(c), with the main line impedance and the shunt line impedance . The electrical parameters of the T-structures can be calculated using Table III, (B2), and (B3a) and are tabulated in Table IV. The GRRC has been implemented using microstrip technology at the center frequency of 1.0 GHz on an FR4 substrate

Fig. 19. Experimental setup for measurement of the fabricated GRRC with the fabricated prototype shown in inset.

TABLE V PHYSICAL DIMENSIONS OF THE ELEMENTARY T-STRUCTURES

of thickness 1.58 mm and dielectric constant 4.4. The physical dimensions of the elementary T-structures shown in Fig. 18(a) are provided in Table V. The physical layout of the GRRC as a whole has been shown in Fig. 18(b). The full-wave simulation of the four-port network shown in Fig. 18(b) has been simulated using ADS/Momentum. The fabricated prototype and the experimental setup are depicted in Fig. 19. Fig. 20 discusses the measured results of the fabricated GRRC which agree quite closely with the simulation. The measured amplitude imbalances at the center frequency of 1.0 GHz for port-1 and port-4 excitations are 3.2 dB and 3.03 dB, respectively, and the measured transmission phase , , and are 59.53 , 62.45 , 60.57 , and 56.88 respectively. The measured results deviate slightly from the desired amplitude imbalance of 3.0 dB and transmission phase of 60 probably due to the effect of the junction discontinuities at the excitation ports.

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Fig. 20. Full-wave simulation (black line) and measured (grey line with circular markers) results of GRRC shown in Fig. 18(b). (a) Scattering parameters for port-1 excitation. (b) Amplitude imbalance for port-1 and port-4 excitations. (c) Transmission phase response for port-1 and port-4 excitations.

VI. CONCLUSION A novel concept of decomposing a port has been introduced to reduce a large complicated network into smaller and simpler ones by terminating some of the ports of the original network by short circuit. This decomposition technique is general and can be simultaneously applied to any port (coupled or isolation) and to any number (one or many) of them. A multiport network synthesis algorithm has been proposed to systematically derive the design equations. This algorithm can be applied to any type of multiport networks like the symmetric or asymmetric, perfectly matched or unmatched, lossy, or lossless. An idea of designing lossless passive couplers using generalized two-port building blocks (symmetric or asymmetric) instead of a conventional single section of a TL (or waveguide) has been introduced here. Four theorems have been laid down which provides the conditions for realization of generalized RRCs and BLCs, a 5PN using such TPN building blocks, and an arbitrary phase-difference coupler. The proposed method is in general quite powerful and can be applied to analyze and derive design equations for any kind of couplers and power dividers or any complicated multiport network, even with choice of asymmetric building blocks and/or coupled lines. In particular, a case of such networks when the building blocks consist of a single-section TL has been derived based on the proposed theorems, and the design equations have been validated with those in the existing literature. A prototype of a generalized coupler has been developed using asymmetric building blocks and measured results are in close agreement with the desired one.

Fig. 21. (a) Arbitrary 4PN with port-4 being terminated by load and port-4 of the four-port network being short-circuited.

. (b) Port-2

(A2) where . If port-2 and 4 of the 4PN are short-circuited and port-1 and port-3 are part of the newly formed 2PN with its ports denoted by and , respectively, as shown in Fig. 21(b), then the new -parameters of 2PN can be given as

(A3)

APPENDIX B IMPLEMENTATION OF TPN BY ASYMMETRIC-T The 2PN parameters of an asymmetric-T shown in Fig. 9(c) is given as

APPENDIX A

(B1a)

FOUR-PORT NETWORK TERMINATED BY AN ARBITRARY LOAD

(B1b)

An arbitrary 4PN is shown in Fig. 21(a) whose scattering parameters is given as

(B1c)

(A1) and If port-4 of the 4PN is terminated by an arbitrary load port-1( ), 2( ) and 3( ) are part of the new three-port network (3PN) as shown in Fig. 21(a), then the new 3PN scattering parameters can be given as [8]

(B1d) Given the ABCD parameters, one can synthesize the two-port network (TPN) by expressing the shunt susceptance and the electrical lengths in terms of the given and the characteristic impedance of the main line as (B2a) (B2b)

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Fig. 22. (a) Four-port coupled line. (b) Two-port C-section coupled line.

(B2c) (B2d) (B2e) Depending upon the sign of , one can have two solutions for the shunt susceptance: capacitive when +ve and inductive when -ve. The capacitive-type susceptance can be implemented by an open stub of electrical length and characteristic impedance or by a lumped capacitor of capacitance . We thus have (B3a) (B3b) Similarly, the inductive-type suceptance can be implemented by short-circuited stub of electrical length and characteristic impedance or by a lumped inductor of inductance . We thus have (B4a) (B4b)

APPENDIX C -PARAMETER OF A COUPLED LINE The four-port -parameter of a coupled line shown in Fig. 22(a) can be written as (C1)

17

[2] H.-R. Ahn and I. Wolff, “Asymmetric four-port and branch-line hybrids,” IEEE Trans. Microw. Theory Techn., vol. 48, no. 9, pp. 1585–1588, Sep. 2000. [3] H.-R. Ahn, Asymmetric Passive Components in Microwave Integrated Circuits. New York: Wiley, 2006. [4] K.-K. M. Cheng and P.-W. Li, “A novel power-divider design with unequal power-dividing ratio and simple layout,” IEEE Trans. Microw. Theory Techn., vol. 57, no. 6, pp. 1589–1594, Jun. 2009. [5] R. Sinha, A. De, and S. Sanyal, “A theorem on asymmetric structure based rat-race coupler,” IEEE Microw. Wireless Compon. Lett., vol. 25, no. 3, pp. 145–147, Mar. 2015. [6] B.-H. Murgulescu, E. Moisan, P. Legaud, E. Penard, and I. Zaquine, circumference 180 hybrid ring coupler,” “New wideband, Electron. Lett., vol. 30, no. 4, pp. 299–300, Feb. 1994. [7] Y. Wu, J. Shen, and Y. Liu, “Comments on quasi-arbitrary phase difference hybrid coupler,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 4, pp. 1725–1727, Apr. 2013. [8] T. Y. Otoshi, “On the scattering parameters of reduced multiport,” IEEE Trans. Microw. Theory Techn., vol. 17, no. 9, pp. 722–724, Sep. 1969. [9] C. Y. Pon, “Hybrid-ring directional coupler for arbitrary power divisions,” IRE Trans. Microw. Theory Techn., vol. 9, no. 11, pp. 529–535, Nov. 1961. [10] M.-J. Park and B. Lee, “Design of ring couplers for arbitrary power division with 50 lines,” IEEE Microw. Wireless Compon. Lett., vol. 21, no. 4, pp. 185–187, Apr. 2011. [11] C. Toker, M. Saglam, and M. Ozme, “Branch-line couplers using un-equal line lengths,” IEEE Trans. Microw. Theory Techn., vol. 49, no. 4, pp. 718–721, Apr. 2001. [12] E. R. B. Hanson and G. P. Riblet, “An ideal six-port network consisting of a matched reciprocal lossless five-port and a perfect directional coupler,” IEEE Trans. Microw. Theory Techn., vol. MTT-31, no. 3, pp. 284–288, Mar. 1983. [13] Y. Wu, J. Shen, Y. Liu, S.-W. Leung, and Q. Xue, “Miniaturized arbitrary phase-difference couplers for arbitrary coupling coefficients,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 6, pp. 2317–2324, Jun. 2013.

Rakesh Sinha received the B.Tech degree in electronics and communication engineering from Kalyani Government Engineering College, Kalyani, India, in 2008, and the M.Tech degree in RF and microwave engineering from the Indian Institute of Technology, Kharagpur, India, in 2011, where he is currently working toward the Ph.D. degree in electrical and communication engineering. From 2008 to 2009, he was with the Department of Robotics and Automation, Central Mechanical Engineering Research Institute, Durgapur, India, as a Junior Research Fellow. His current research interests are in the area of multiport network synthesis, impedance matching, coupling and decoupling networks, and computational electromagnetics.

(C2a) (C2b) (C2c) (C2d) The two-port -parameter of a C-section coupled line shown in Fig. 22(b) can be written as (C3) (C4a) (C4b) REFERENCES [1] H.-R. Ahn, I. Wolff, and I. S. Chang, “Arbitrary termination impedances, arbitrary power division, and small-sized ring hybrids,” IEEE Trans. Microw. Theory Techn., vol. 45, no. 12, pp. 2241–2247, Dec. 1997.

Arijit De (S'04–M'11) received the B.Tech. degree (with honors) in electronics and electrical communication engineering from the Indian Institute of Technology, Kharagpur, India, in 2004, and the Ph.D. degree from Syracuse University, Syracuse, NY, USA, in 2010. In the summer of 2003, he was an Intern with the Centre of Excellence Embedded DSP, Tata Consultancy Services, where he was involved with the design and implementation of 802.11g Wireless LAN. From 2004 to 2005, he was a Research Consultant with the Advanced VLSI Design Laboratory, Indian Institute of Technology (IIT), Kharagpur, India, working on the development of next-generation analog CAD tools for National Semiconductor Corporation, Santa Clara, CA, USA. Currently, he is an Assistant Professor with the Department of Electronics and Electrical Communication Engineering, IIT, Kharagpur. His current research interest deal with mathematical modelling and computational techniques applied to problems arising in the area of electromagnetics and signal processing. Prof. De. was the recipient of the URSI Young Scientist Award in 2011 at the XXXth URSI General Assembly held at Istanbul, Turkey.

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1245

Design of -Band Transition From Microstrip to Ridge Gap Waveguide Including Monte Carlo Assembly Tolerance Analysis Astrid Algaba Brazález, Jonas Flygare, Jian Yang, Senior Member, IEEE, Vessen Vassilev, Mariano Baquero-Escudero, Member, IEEE, and Per-Simon Kildal, Fellow, IEEE

Abstract—This paper describes the design and realization of a transition from a microstrip line to a ridge gap waveguide operating between 95 and 115 GHz. The study includes simulations, measurements, and a Monte Carlo analysis of the assembly tolerances. The purpose of this tolerance study is to identify the most critical misalignments that affect the circuit performance and to provide guidelines about the assembly tolerance requirements for the proposed transition design. Index Terms—Artificial magnetic conductor, assembly, -band, microstrip, millimeter-waves, Monte Carlo, ridge gap waveguide, tolerance, transition.

I. INTRODUCTION

T

HE fast development that wireless communication is currently experiencing and the need to fulfill higher capacity demands have motivated the urge to investigate new low-loss technologies that can replace conventional microstrips, coplanar waveguides (CPW), striplines, and standard waveguides at high frequencies. High functionality, performance, and integration of active and passive components in minimal volumes set a big challenge for emerging millimeter-wave (mm-wave) technologies. There is need for three-dimensional (3-D) vertically integrated circuits to constitute low-volume RF modules [1], but traditional technologies such as microstrip and CPW experience a clear degradation in performance as the frequency increases due to presence of surface waves, radiation problems, and other parasitic coupling issues. Standard waveguides do not constitute a cost-effective and easy-to-integrate approach for large corporate feed networks of array antennas at mm-waves because it is very Manuscript received May 22, 2015; revised September 21, 2015; accepted February 13, 2016. Date of publication March 17, 2016; date of current version April 01, 2016. This work was supported in part by the Swedish Research Council VR, the Swedish Governmental Agency for Innovation Systems VINNOVA via a project within the VINN Excellence center Chase, and the European Research Council (ERC) under Grant ERC-2012-ADG-20120216. A. Algaba Brazález, J. Yang, and P.-S. Kildal are with the Department of Signals and Systems, Chalmers University of Technology, SE-41296 Gothenburg, Sweden. J. Flygare is with Onsala Space Observatory, Chalmers University of Technology, SE-41296 Gothenburg, Sweden. V. Vassilev is with the Department of Microtechnology and Nanoscience (MC2), Chalmers University of Technology, SE-41296 Gothenburg, Sweden. M. Baquero-Escudero is with the Instituto de Telecomunicaciones y Aplicaciones Multimedia (ITEAM), Universidad Politécnica de Valencia (UPV), 46022 Valencia, Spain. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2535334

difficult to have a good metal contact between the upper and lower blocks, where the E-plane split-block waveguide technology [2] cannot be used. The recently introduced gap waveguide in [3] and [4] constitutes a new approach for mm-wave frequency ranges since it is able to overcome those critical issues of traditional technologies. Gap waveguides are based on the field cutoff established by two parallel perfect electric conductor (PEC) and perfect magnetic conductor (PMC) layers which are separated by an air-gap smaller than a quarter wavelength. Any electromagnetic wave is forbidden to propagate between these two layers, with the exception of local waves that can follow strips, ridges, or grooves embedded within the parallel PEC-PMC. The PMC condition can be obtained by an Artificial Magnetic Conductor (AMC) in the form of a periodic surface and, together with a PEC layer, ensures the removal of any surface waves and parallel-plate modes. The frequency band in which this cutoff is effective is called the stopband and has been thoroughly investigated in [5] by applying different types of AMC. The cutoff principle ensures a greater application potential of the gap waveguide than standard waveguides and microstrip lines at mm-waves. First, there is no requirement for good mechanical contact between the metal blocks composing the gap waveguide circuits. Second, this technology has lower loss than microstrip lines since no dielectric material is needed [6]. Third, the surface waves from which microstrip lines usually suffer are efficiently suppressed by the gap waveguide. Moreover, a gap waveguide has been also applied as a suitable technique for suppressing radiation from microstrip passive components and increase the isolation between microwave modules [7]–[9], i.e., as a packaging structure. A simple transition from ridge gap waveguide to coaxial connector was developed and presented in [10] in order to allow measurements of a -band ridge gap waveguide demonstrator described in [11]. This type of transition has been employed in most of our ridge and groove gap waveguide prototypes operating at microwave frequencies. However, new versions of gap waveguide transitions are required as the frequency increases. Several suitable transitions working at 60 GHz have been already studied and experimentally validated [12], [13]. In addition, some investigations on transitions between a ridge gap waveguide and standard rectangular waveguides at 0.3 THz have been also initiated. Difficulties to perfectly align the ridge gap circuit and the waveguide flange via an inline transition

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designed by means of steps, which significantly degraded the measurement results, motivated the need of identifying other transition alternatives. Thereby, we decided to investigate transitions from planar structures (coplanar waveguide [14] and microstrip [15]) to a ridge gap waveguide operating in -band (90–140 GHz). The reason to choose this frequency band is that we have available “on-wafer” probe stations operating up to 125 GHz, which allows us to test those transition designs. As mentioned, any misalignment between the blocks composing a mm-wave circuit can cause a serious perturbation on its performance. Due to the small wavelengths at frequencies above 100 GHz, the tolerance requirements on manufacturing and assembly are stricter than at lower frequencies. Therefore, it is important to know the effect of tolerances on the performance of mm-wave devices in order to impose a proper tolerance requirement. The assembly of a gap waveguide circuit involves an unavoidable human factor that makes this process extremely critical in terms of tolerances. This fact motivates the tolerance study presented in this paper, which is based on a Monte Carlo analysis applied on the designed transition. The cumulative distribution function (CDF) of a random combination of different assembly misalignments for the reflection coefficient of the transition has been extracted. This provides a good guideline for imposing the assembly requirement. Sections II and III deal with the design of an -band transition between microstrip and ridge gap waveguide. This design is a continuation of a preliminary one introduced in [15], which has been suitably improved now. Sections IV and V focus on the Monte Carlo assembly tolerance analysis to identify the most critical assembly misalignments. II. GEOMETRY AND DESIGN OF -BAND MICROSTRIP TO RIDGE GAP WAVEGUIDE TRANSITION A transition design between microstrip and ridge gap waveguide based on mechanical pressure contact was reported in [16], with a measured return loss of 14 dB over 55% relative bandwidth at -band. The pressure contact approach becomes quite complex to be realized at frequencies above 100 GHz because the height of the air gap in the gap waveguide must be kept equal to the thickness of the substrate. It is also difficult to control the pressure contact area due to the small dimensions of our components at mm-wave frequencies. This motivated the investigation of a new transition approach. The first step in the design of gap waveguide components is to determine the dimensions of the pin surface to ensure the stopband that covers the operating frequency band. The dimensions of our gap waveguide geometry as well as its dispersion diagram are shown in Fig. 1(a) and (b), respectively. The dispersion diagram was simulated by using CST Eigenmode solver and considering periodic boundary conditions in both and directions. The obtained stopband covers the range of frequencies between 70 and 135.8 GHz where only a quasi-TEM mode is allowed to propagate along the path settled by the ridge. In our transition design, the transformation of the quasi-TEM mode of a microstrip line into the quasi-TEM mode of the ridge gap waveguide is obtained via electromagnetic field coupling. This interconnection approach was introduced in [17] and [18], for the design of mm-wave transitions between

Fig. 1. (a) Dimensions of ridge gap waveguide. (b) Resulting dispersion diagram.

microstrip lines and coplanar waveguides and proposed as an alternative to bond-wires when interconnecting mm-wave monolithic integrated circuits (MMICs) to a carrier substrate. This coupling principle consists of overlapping quarter-wavelength transmission line segments, where matching elements can be also included to improve the transition performance. Another successful employment of this interconnection method is presented in [19], where a vertical CPW-to-microstrip transition operating in the -band shows wideband and low loss performance. Our -band transition composed of two layers is illustrated in Fig. 2. The first layer is a metal plate that contains the ridge gap waveguide interface. The second layer is a printed circuit board (PCB) that includes a microstrip circuit, and the ground plane of the PCB is soldered into the bottom metal plate. The employed substrate is alumina with thickness 0.127 mm, dielectric constant and loss tangent (evaluated at 10 GHz according to the material supplier). As shown in Fig. 2, the ridge gap waveguide is placed upside down in the upper metal plate, whilst the PCB positioned in the bottom metal layer is facing upwards towards the ridge. All metallic parts are gold-plated. The transition from ridge gap waveguide to microstrip is achieved via the electromagnetic coupling established when overlapping a ridge section with a microstrip-line segment. These transmission-line segments are not in physical contact, i.e., constituting a contactless transition. Therefore, the coupling is achieved through the existent air gap between the ridge and the microstrip line. Since the gap between the bottom side

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Fig. 4. Top view of PCB and design details of CPW-microstrip circuit. TABLE I DIMENSIONS OF PCB LAYER

Fig. 2. Different layers of

-band transition.

Fig. 3. Front view of complete transition geometry.

of the pin surface and the lower metal plate is 0.2 mm [as represented in Fig. 1(a)], considering the thickness of the substrate and the thickness of the metal strips in the PCB (10 m), the separation between the ridge and the microstrip segment is then 63 m as illustrated in Fig. 3. The distance between the top side of the substrate and the bottom face of the pin is 73 m. There are two circuits placed at both sides of the PCB (see Fig. 4) in order to analyze the transitions in back-to-back configuration. Each of these circuits is composed of two sections. First, a transition between CPW and microstrip is needed since the measurements will be performed by using ground–signal–ground (GSG) wafer probes. The dimensions of the coplanar waveguide have been chosen in such a way that an input impedance of 50 is ensured as well as the pitch in the CPW circuit is kept below 100 m. The transition from CPW to microstrip is designed by means of an intermediate tapered section whose width is gradually increased to match the width of a 50- microstrip line allowing a smooth field transformation. We have included via holes that connect the ground pads

of the CPW to the ground plane in order to suppress potential parallel plate modes. The second part of the transition is a 50microstrip line terminated by a rectangular patch. This patch constitutes a matching section that overlaps a certain ridge segment, which is located in the upper layer. Therefore, the complete transition geometry includes a CPW-to-microstrip interface and a microstrip-to-ridge gap waveguide transition. Fig. 4 shows that a certain central area of the PCB has been cut out, allowing the electromagnetic fields to propagate along and between the ridge gap waveguide and the lower metal plate through air media. At the same time, we keep both circuits that constitute the back-to-back transitions in the same PCB instead of having two separate PCBs. This ensures that we get a better mechanical alignment between the two circuits, since different boards would need to be soldered separately and that involves a higher risk to get poor alignment. The dimensions of the CPW-microstrip circuits are summarized in Table I. The ridge is composed of three sections: a central ridge with length equal to 11.6 mm (approximately at 100 GHz) and two additional side ridge sections that overlap the microstrip patches of the PCB layer. One side ridge section receives the signal coupled from the microstrip patch, the main ridge guides the signal to the output, and then the second side ridge section couples the signal to the second microstrip patch. The length of the microstrip patch and the side ridge section have been initially set as and respectively (where 1.12 mm and 3 mm for 100 GHz). Afterwards, a parametric sweep

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Fig. 6. Simulated -parameters of transition geometry with straight ridge gap waveguide. Fig. 5. Top view of transition prototype (top metal lid is hidden to allow visualization of design details).

of that length, the width of the microstrip segments, and the width of the side ridges is performed in order to improve the matching. We have observed that we get best transition performance when the width of the side ridges follows the shape of the microstrip patch. Fig. 5 illustrates the top view of the complete geometry, as well as the overlapped area between the microstrip section and the ridge gap waveguide. We have also placed two extra pins before and after the ridge with the aim to maintain the microstrip line properly packaged avoiding possible radiation. III. SIMULATION AND MEASUREMENT RESULTS The proposed transition geometry has been numerically analyzed in terms of -parameters by using CST Microwave Studio. The simulation result of this structure is presented in Fig. 6. The simulation shows that return loss is larger than 15 dB in about 23.6% relative bandwidth for the gap waveguide prototype. The resulting insertion loss is lower than 1.3 dB over this bandwidth, which implies 0.65 dB for a single transition. Note that the contribution from the transition from CPW to microstrip is included but the actual objective is to design a transition from microstrip to ridge gap waveguide. Therefore, the insertion loss of our transition is lower if we exclude the loss of the CPW-microstrip section, which is possible by applying a thru-reflect-line (TRL) de-embedding method. The gap waveguide layers have been manufactured by using a computer numerical control (CNC) milling machine. Milling is a very precise manufacturing technique and the tolerance in the pin/ridge size, height and period has been found to be of the order of 1 m. The PCBs have been fabricated by standard photolithography process. According to the specifications from the PCB manufacturer (CoorsTek), the dimensions of the etched strips as well as the existent gaps between the ground pads and signal pad that constitute the CPW, show a tolerance of 2.54 m (verified by using a microscope). The via holes of the CPW ground pads have been realized by laser drilling and are gold-plated. The central area of the PCB has been cut out

Fig. 7. Straight ridge gap waveguide and corresponding PCB soldered into metal layer.

by laser as well. The most critical tolerances regarding the PCB manufacturing have been found to be the corresponding ones to the via hole drilling (hole diameter and hole location have a tolerance of 51 m), and the overall substrate dimensions ( 25.4 m). The substrate is actually 18 m thicker than the selected standard one, the metal strip is 6 m thinner, and the ground plane is 5 m thicker. These tolerance values are quite significant compared to the overall circuit dimensions and the wavelength value at the frequency of operation. Therefore, tolerances will certainly have an impact on the circuit performance. A photograph of the manufactured prototype including soldered PCB to the metal plate is shown in Fig. 7. The assembly of the metal blocks is done by using four screws. The PCB needs to be suitably attached to a metal plate as illustrated in Fig. 8. The PCB is placed between two side steps of thickness equal to 0.5 mm that, together with the side steps of the upper metal plate (of thickness equal to 0.47 mm), contribute to keep the required gap constant. During this assembly process, it is difficult to keep the air-gap distance constant because the soldering liquid might add up to several tens of micrometers of thickness below the

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Fig. 8. Description of assembly of mechanical parts for the straight ridge gap waveguide prototype.

Fig. 9. Measurement setup for -band prototype on wafer-probe station. Full setup view is shown to the left and the probes are shown to the right.

PCB, thus lifting the board in an uneven way which results in a smaller air-gap at some points of the prototype. A decrease in the air-gap constitutes a change in the transition performance since the coupling between the microstrip patch and the ridge section becomes different. One solution to counteract this effect is to increase the depth of the groove of the bottom metal plate that exists between the side steps (see Fig. 8) where the PCB is soldered, and estimate in advance how much thickness the soldering liquid might add. However, there is an unavoidable human factor on the soldering process and it is difficult to achieve exactly 73 m of constant gap. After soldering, the straight ridge gap waveguide prototype shows a gap of 50 m at both sides. The fabricated -band prototypes have been measured by employing wafer-probe stations equipped with coplanar launchers and a vector network analyzer (VNA) together with two frequency extension modules as shown in Fig. 9. A comparison between simulated and experimental transmission properties is plotted in Fig. 10. In order to achieve a fairer comparison, we have introduced the known data regarding tolerances (via hole diameter, substrate and metal strips characteristics, ground plane thickness, and obtained air-gaps after soldering) in our CST model. The first observation on the comparison between simulations and measurements is a degradation on the prototype performance with respect to the simulation results presented in Fig. 6, clearly caused by the PCB manufacturing and assembly tolerances. In the obtained experimental results shown in Fig. 10(a), we can identify a resonance peak at 93 GHz that has been observed in all measurements. One reason that could explain the origin of the resonance is that the ground pads of the CPW behave as two patch antennas with a coplanar feed along one side of

Fig. 10. (a) Simulated and measured -parameters of back-to-back transition between microstrip and straight ridge gap waveguide. (b) Zoomed -parameters to visualize insertion loss.

each patch. This resonance phenomena was studied in [20] and [21], where an expression to obtain the resonance frequencies is given. The resonance frequency depends on the width and length of the CPW ground pad. Using that expression and our corresponding pad dimensions, we obtain the first resonance at 91.8 GHz, which is very close to the measured resonance. Thereby, it could be possible that the ground CPW pads radiate energy causing the resonance. In spite of this resonance peak and a small frequency shift of about 3 GHz, simulated and measured return loss are about same level between 98 and 119 GHz. Fig. 10(b) represents a zoomed view of the simulated and measured parameter. By extracting the mismatch factor to the values, we obtain the dissipative contribution of the loss, which is smaller than 1.9 dB for both simulations and measurements in the frequency interval 98–119 GHz. IV. MONTE CARLO TOLERANCE ANALYSIS Measurement results show a degradation of the transition performance most likely due to PCB manufacturing and prototype assembly tolerances. For mechanical design purpose and manufacturing specifications, it is exemplified in related areas [22]–[24] that Monte Carlo-based tolerance analysis is a useful

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approach in multiparameter analysis [25]. Our measurement results indicate that misalignments in the air gap between the ridge and the PCB during the assembly of the prototype is of distinct importance. Furthermore, the horizontal displacement of the PCB with respect to the ridge gap waveguide caused during the soldering process could also be a critical factor that affects the transition performance. Our aim is to identify the most critical parameters in order to give suitable guidelines on designing the mechanical parts of gap waveguides at mm-wave frequencies. A MATLAB/CST code is created to emulate these misalignment factors on our transition design over a large set of samples. The MATLAB script modifies the CST model tolerance parameters for each sample and logs the output results for statistical analysis. We implement the Monte Carlo technique to draw random values from specified distributions for all displacement parameters under test independently of each other. Uniform distribution is considered to efficiently evaluate a worst case scenario and identify the most critical tolerance parameter. CST Microwave Studio is a finite-difference time-domain (FDTD) electromagnetic solver, and, therefore, the mesh resolution is important to consider in order to have a valid tolerance analysis. The random misalignment change must be larger than the smallest mesh step in the model. This will be detailed in Section IV-B. A. Tolerance Parameters Under Test Three types of assembly misalignments are included in this analysis: 1) the gap misalignment between the top PCB surface and the bottom of the pins at each port with respect to the nominal air gap of 73 m [Fig. 11(a)]; 2) PCB horizontal translational misalignment [Fig. 11(b)]; and 3) PCB rotational misalignment around the center point of the horizontal face [Fig. 11(c)]. We describe the gap waveguide performance as a function of these five tolerance parameters

Fig. 11. Misalignment illustrations for tolerance parameter definitions. (a) Side . (b) Top view of PCB horizontal transview of gap misalignment and . Top lid and pins are hidden for allowing lational misalignments and . ridge and PCB visualization. (c) Top view of PCB rotational misalignment Top lid and pins are hidden for allowing ridge and PCB visualization. Misalignment is exaggerated for illustration purpose.

(1) and are random gap misalignments at ports 1 where and 2, respectively, and are the PCB translational misalignments along and directions, respectively, and is the angle of the PCB rotational misalignment. represents the reflection and transmission coefficient output. B. Mesh and Tolerance Resolution To be confident that the misalignment under test is meshed properly, the smallest tolerance step (smallest misalignment) in the simulation must be larger than the smallest mesh step in the mesh grid. The importance of this is illustrated in Fig. 12. To ensure that simulated tolerances in this study were valid, a large set of pre-samples were created. From these we evaluated that 2.3 m or smaller for all the samples. This means that with 3 m that was used, we are confident that the simulations are valid. C. Tolerance Intervals Under Test The tolerance intervals under test have been extracted from our own observations when assembling the manufactured prototypes. The most extreme gap misalignment was measured to be in the interval 23,47 m from nominal gap

Fig. 12. (a) Mesh resolution is good and the object (yellow rectangle) is completely covered. (b) Object is extended with an extra column. The grid covers the entire object again and simulation would still be valid. (c) Object is extended but not enough and falls between grid lines, this particular simulation cannot be guaranteed to give accurate results.

distance of 73 m. The PCB is soldered within a groove that is 20 m wider than the PCB width, therefore PCB translational misalignment in the interval 20,20 m and rotational ( ) within from the nominal design were considered for investigation. The smallest tolerance step was, as mentioned previously, set to 3 m for the gap and translational PCB tolerance parameters. The step of the rotational misalignment is set as 0.01 by considering the misaligned size at the ridge ends due to the linear scaling along the length of the waveguide. V. TOLERANCE ANALYSIS RESULTS The -parameters obtained from 719 samples, which constitutes the complete simulation set, is represented with upper and lower (nominal) limit in Fig. 13. The corresponding tolerance

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TABLE II DISTRIBUTION STATISTICS OF THE FIVE TOLERANCE PARAMETERS FOR THE 719 SIMULATION SAMPLES OF FIG. 13. PARAMETERS ARE DISPLAYED AS MISALIGNMENT FROM NOMINAL VALUE

Fig. 13. Full sample set of 719 simulation samples represented with upper and lower (nominal) limit of -parameters. Black dotted line represents the nominal performance.

Fig. 15. Plot of 242 simulation samples out of 719 ( ) shows 15 dB from 95 to 115 GHz, here represented with upper and lower (nominal) limit of -Parameters. Black dotted line represents the nominal performance.

Fig. 14. Histogram distribution of the five tolerance parameters, for the 719 simulation samples of Fig. 13. Parameters are displayed as misalignment from . (b) . (c) . (d) . (e) . nominal value. (a)

parameter distributions in histogram form are shown in Fig. 14. Table II represents a summary of the tolerance intervals for each

parameter under study and the mean, standard deviation (STD) and root mean square (RMS) of the parameter distributions extracted from the obtained sample data shown in Fig. 13. If we set the requirement for 15 dB over 95–115 GHz, 242 samples out of the total 719 fulfill it. Figs. 15 and 16 show the reflection and transmission coefficients represented by upper and lower (nominal) limit and the tolerance parameter distribution of the 242 cases that fulfilled the previous condition, respectively. We can observe in Fig. 16 that , and are approximately uniform distributed over the tolerance interval under test (Section IV-C), whilst and show a Gaussian distribution over 23, 28 m, with a STD of 11 m approximately (see Table III). This means that and are the two most critical tolerance parameters for the assembly tolerance. We have also identified that the tolerance interval 23, 28 m for and does not guarantee a reflection coefficient below 15 dB; there are 445 samples with and within 23, 28 m. This means that approximately 54% of the samples with , within 23,28 m (together with some random combination of the other three misalignments , , and ) achieve the requirement of 15 dB. Therefore, we have extracted several CDF curves for different and tolerance intervals, as shown in Fig. 17. If we set the tolerance interval of , to 10, 10 m together with the other misalignment

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Fig. 17. Each CDF curve represents obtained samples when both gaps misalignment have values within the interval specified in the legend. The curves pershow the percentage of these samples (within each interval) where formance is better than a certain decibel level ( -axis) for the frequency band of 95–115 GHz. The red dashed–dotted curve represents all the samples and hence the largest misalignment interval.

Fig. 16. Histogram distribution of the five tolerance parameters, for the 242 simulation samples of Fig. 15. Parameters are displayed as misalignment from . (b) . (c) . (d) . (e) . nominal value. (a)

TABLE III DISTRIBUTION STATISTICS OF THE FIVE TOLERANCE PARAMETER HISTOGRAMS FOR THE 242 SIMULATION SAMPLES OF FIG. 15. PARAMETERS ARE DISPLAYED AS MISALIGNMENT FROM NOMINAL VALUE

tolerances (as defined in Section IV-C), the possibility to fulfill the requirement of 15 dB is 98%, close to 100%. VI. CONCLUSION We have proposed an -band transition from standard microstrip to ridge gap waveguide via electromagnetic coupling. The transition has been numerically analyzed in back-to-back structure, showing return loss larger than 15 dB over more than 23% relative bandwidth and insertion loss lower than 1.3 dB. Assembly and PCB manufacturing tolerances degrade the transition performance as seen in the presented comparison between

simulations and measurements. Still, we could achieve a reasonably good agreement between simulated/measured return loss and dissipation factor in about 15% relative bandwidth. The presented Monte Carlo tolerance analysis establishes guidelines and requirements for the assembly process. It is clear from this study that the misalignment in the gap distance is the most important tolerance factor that affects the -parameter performance. We can conclude that a tolerance interval for gap misalignment within 10,10 m (which implies in terms of wavelength), PCB translational misalignment in both horizontal directions within 20,20 m ( ) and PCB rotational misalignment within during assembly gives a possibility close to 100% to fulfill the performance requirement 15 dB over the frequency band of 95–115 GHz. Another relevant conclusion from this work is that this transition prototype is assembled in such a way that gap misalignments are very probable to happen. Therefore, the assembly process should be considered in advance when designing high frequency gap waveguide prototypes in order to mitigate the misalignments as much as possible by paying special attention to how to stabilize the air gap. In spite of the observed issues related to the assembly tolerances, this proposed transition becomes an interesting solution for integrating MMICs with ridge gap waveguide circuits. The gap waveguide interface keeps the active components suitably packaged and provides electrical isolation among adjacent RF chips avoiding any possible interference or coupling. The next step of this work will constitute the investigation of the employment of the presented transition to interconnect an amplifier to a ridge gap waveguide. ACKNOWLEDGMENT The authors would like to thank the precision mechanician C.-M. Kihlman from the Microtechnology and Nanoscience (MC2) Department, Chalmers University, for fabricating the gap waveguide blocks, as well as helping us during the assembly of the gap waveguide prototypes. The authors also

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want to thank Prof. Enoksson and Lic. Eng. Rahiminejad from MC2 Department, Dr. U. Zaman from the Signals and Systems Department, and Dr. Haasl for their useful feedback during the project meetings.

REFERENCES [1] K. J. Herrick, Y. Jong-Gwan, and L. P. B. Katehi, “Microtechnology in the development of three-dimensional circuits,” IEEE Trans. Microw. Theory Techn., vol. 46, no. 11, pp. 1832–1844, Nov. 1998. [2] A. V. Raisanen, D. Choudhury, R. J. Dengler, J. E. Oswald, and P. H. Siegel, “A novel split-waveguide mount design for millimeterand submillimeter-wave frequency multipliers and harmonic mixers,” IEEE Microw. Guided Wave Lett., vol. 3, no. 10, pp. 369–371, Oct. 1993. [3] P.-S. Kildal, E. Alfonso, A. Valero-Nogueira, and E. Rajo-Iglesias, “Local metamaterial-based waveguides in gaps between parallel metal plates,” IEEE Antennas Wireless Propag. Lett., vol. 8, no. 1, pp. 84–87, Jan. 2009. [4] P.-S. Kildal, “Three metamaterial-based gap waveguides between parallel metal plates for mm/submm waves,” in Proc. 3rd Eur. Conf. Antennas Propag., Berlin, Germany, Mar. 23–27, 2009, pp. 28–32. [5] E. Rajo-Iglesias and P.-S. Kildal, “Numerical studies of bandwidth of parallel plate cut-off realized by bed of nails, corrugations and mushroom-type ebg for use in gap waveguides,” IET Microw., Antennas & Propagation, vol. 5, no. 3, pp. 282–289, Mar. 2011. [6] E. Pucci, A. U. Zaman, E. Rajo-Iglesias, P.-S. Kildal, and A. Kishk, “Study of -factors of ridge and groove gap waveguide resonators,” IET Microw,, Antennas & Propagation, vol. 7, no. 11, pp. 900–908, 2013. [7] E. Rajo-Iglesias, A. U. Zaman, and P.-S. Kildal, “Parallel plate cavity mode suppression in microstrip circuit packages using a lid of nails,” IEEE Microw. Wireless Components Lett., vol. 20, no. 1, pp. 31–33, Dec. 2010. [8] A. Algaba Brazález, A. U. Zaman, and P.-S. Kildal, “Improved microstrip filters using PMC packaging by lid of nails,” IEEE Trans. Compon., Packag. Manuf. Technol., vol. 2, no. 7, pp. 1075–1084, Jul. 2012. [9] A. U. Zaman, T. Vukusic, M. Alexanderson, and P.-S. Kildal, “Gap Waveguide PMC packaging for improved isolation of circuit components in high frequency microwave modules,” IEEE Trans. Compon., Packag. Manuf. Technol., vol. 1, no. 9, pp. 16–25, Sep. 2012. [10] A. U. Zaman, E. Rajo-Iglesias, E. Alfonso, and P.-S. Kildal, “Design of transition from coaxial line to ridge gap waveguide,” in Proc. IEEE Antennas Propag. Soc. Int. Symp., 2009, pp. 1–4. [11] P.-S. Kildal, A. U. Zaman, E. Rajo-Iglesias, E. Alfonso, and A. ValeroNogueira, “Design and experimental verification of ridge gap waveguides in bed of nails for parallel plate mode suppression,” IET Microw., Antennas & Propag., vol. 5, no. 3, pp. 262–270, Mar. 2011. [12] H. Raza, J. Yang, P.-S. Kildal, and E. Alfonso, “Microstrip-ridge gap waveguide—Study of losses, bends and transition to WR-15,” IEEE Trans. Microw. Theory Techn., vol. 62, no. 9, pp. 1943–1952, Sep. 2014. [13] A. Algaba Brazález, E. Rajo-Iglesias, J.-L. Vazquez-Roy, A. Vosoogh, and P.-S. Kildal, “Design and validation of microstrip gap waveguides and their transitions to rectangular waveguide, for millimeter-wave applications,” IEEE Trans. Microw. Theory Techn., vol. 63, no. 12, pp. 4035–4050, Dec. 2015. [14] A. Algaba Brazález, A. U. Zaman, and P.-S. Kildal, “Design of a coplanar waveguide-to-ridge gap waveguide transition via capacitive coupling,” in Proc. 6th Eur. Conf. Antennas Propag., Prague, Czech Republic, Mar. 26–30, 2012, pp. 3524–3528. [15] A. Algaba Brazález, A. U. Zaman, and P.-S. Kildal, “Investigation of a Microstrip-to-Ridge Gap Waveguide transition by electromagnetic coupling,” in Proc. IEEE Antennas Propag. Soc. Int. Symp., 2012, pp. 1–2. [16] A. U. Zaman, T. Vukusic, M. Alexanderson, and P.-S. Kildal, “Design of a simple transition from microstrip to ridge gap waveguide suited for mmic and antenna integration,” IEEE Antennas Wireless Propag. Lett., vol. 12, pp. 1558–1561, 2013. [17] R. W. Jackson and D. W. Matolak, “Surface-to-surface transition via electromagnetic coupling of coplanar waveguides,” IEEE Trans. Microw. Theory Techn., vol. 35, no. 11, pp. 1027–1032, Nov. 1987.

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[18] G. Strauss and W. S. Menzel, “Millimeter-wave monolithic integrated circuit interconnects using electromagnetic field coupling,” IEEE Trans. Compon., Packag., Manuf. Technol., vol. 19, no. 2, pp. 278–282, May 1996. [19] T. J. Ellis, J. P. Raskin, L. P. B. Katehi, and G. M. Rebeiz, “A wideband CPW-to-microstrip transition for millimeter-wave packaging,” in IEEE MTT-S Int. Microw. Symp. Dig., 1999, vol. 2, pp. 629–632. [20] W. H. Haydl, “Resonance phenomena and power loss in conductorbacked coplanar structures,” IEEE Microw. Guided Wave Lett., vol. 10, no. 12, pp. 514–516, Dec. 2000. [21] W. H. Haydl, “On the use of vias in conductor-backed coplanar circuits,” IEEE Trans. Microw. Theory Techn., vol. 50, no. 6, pp. 1571–1577, Jun. 2002. [22] J. Bornemann, U. Rosenberg, S. Amari, and R. Vahldieck, “Tolerance analysis of bypass-, cross- and direct coupled rectangular waveguide band-pass filters,” Proc. Inst. Electr. Eng.—Microw., Antennas Propag., vol. 152, no. 3, pp. 167–170, Jun. 2005. [23] A. Gonzalez and Y. Uzawa, “Tolerance analysis of ALMA band 10 corrugated horns and optics,” IEEE Trans. Antennas Propag., vol. 60, no. 7, pp. 3137–3145, Jul. 2012. [24] M. Candotti, Y. Uzawa, S. V. Shitov, Y. Fujii, and K. Kaneko, “ALMA band 10 optics tolerance analysis,” in Proc. 19th Int. Symp. Space THz Technol., Groningen, The Netherlands, Apr. 2008, pp. 521–527. [25] A. Hammar, M. Whale, P. Forsberg, A. Murk, A. Emrich, and J. Stake, “Optical tolerance analysis of the multi-beam limb viewing instrument STEAMR,” IEEE Trans. THz Sci. Technol., vol. 4, no. 6, pp. 714–721, Nov. 2014. Astrid Algaba Brazález was born in Alicante, Spain, in 1983. She received the Telecommunication Engineering degree from Miguel Hernández University of Elche, Alicante, Spain, in 2009, and the Licentiate of Engineering and Ph.D. degrees from Chalmers University of Technology, Gothenburg, Sweden, in 2013 and 2015, respectively. She joined Ericsson Research, Ericsson AB, Gothenburg, Sweden, in November 2014. Her main research interests include the development of gap waveguide technology for millimeter and sub-millimeter wave applications, microwave passive gap waveguide components, packaging of microstrip filters, design of high-frequency transitions between gap waveguide and other technologies, and metamaterials.

Jonas Flygare was born in Molndal, Sweden, in 1988. He received both the B.Sc. and M.Sc. degrees in engineering physics from Chalmers University of Technology, Gothenburg, Sweden, in 2016. In 2012, he was a Test Technician with CBRITE Inc., Goleta, CA, USA, where he was developing thin-film-transistor technology for next-generation flat screens. In 2014, he was with the Antenna Group, Signals and Systems Department, Chalmers University of Technology, Gothenburg, Sweden, working with ridge gap waveguide tolerances. Since October 2014, he has been a Project Assistant with the Onsala Space Observatory, Onsala, Sweden, operated by Chalmers University. He is mainly involved with antenna design, simulation, and optimization for the Square Kilometre Array project (SKA).

Jian Yang (SM’10) received the B.Sc. degree in electrical engineering from the Nanjing University of Science and Technology, Nanjing, China, in 1982, the M.Sc. degree in electrical engineering from the Nanjing Research Center of Electronic Engineering, Nanjing, in 1985, and the Swedish Licentiate and Ph.D. degrees from Chalmers University of Technology, Gothenberg, Sweden, in 1998 and 2001, respectively. From 1985 to 1996, he was with the Nanjing Research Institute of Electronics Technology, Nanjing, China, as a Senior Engineer. From 1999 to 2005, he was with the Department of Electromagnetics, Chalmers University of Technology, Gothenberg, Sweden,

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as a Research Engineer. During 2005 and 2006, he was with COMHAT AB as a Senior Engineer. From 2006 to 2010, he was an Assistant Professor and, since 2010, he has been an Associate Professor with the Department of Signals and Systems, Chalmers University of Technology. His research interests include 60–120-GHz antennas, terahertz antennas, MIMO antennas, ultrawideband (UWB) antennas and UWB feeds for reflector antennas, UWB radar systems, UWB antennas in near-field sensing applications, hat-fed antennas, reflector antennas, radome design, and computational electromagnetics.

Vessen Vassilev received the M.Sc. degree in radio communications from the Sofia Technical University, Sofia, Bulgaria, in 1995, and the M.Sc. degree in digital communications and Ph.D. degree from Chalmers University of Technology, Gothenberg, Sweden, in 1998 and 2003, respectively. Between 1998 and 2008, he was working with the development of millimeterwave receivers for applications in radio astronomy and space sciences. Instruments designed by him are currently in operation at the Atacama Pathfinder Experiment (APEX) telescope and at the Onsala Space Observatory. Since 2008, he has been with the Microwave Electronics Laboratory, Department of Microtechnology and Nanoscience, Chalmers University of Technology, Gothenberg, Sweden. His current interests are in the development mm-wavelength sensors based on monolithic microwave microwave integrated circuit technologies.

Mariano Baquero-Escudero (M’87) was born in Murcia, Spain, on January 11, 1962. He received the degree in telecommunications engineering from the Polytechnic University of Catalonia, Barcelona, Spain, in 1986, and the Ph.D. degree from the Polytechnic University of Valencia, Valencia, Spain, in 1994. He was with the Antennas, Microwave and Radar Group, Polytechnic University of Catalonia, Barcelona, Spain, from 1986 to 1988, where he worked on the development of a cylindrical

near-field facility to measure a 3-D radar antenna in CESELSA. Since 1989, he has been with the Polytechnic University of Valencia, Valencia, Spain, where he became a Full Professor in 2003. During 1995, he held a postdoctoral grant at the Joint Research Centre, European Commission, Ispra, Italy, where he developed high-resolution algorithms for radar applications. From April 1996 to February 1998, he was a Vice-Dean of the Telecommunications Engineering School of Valencia. He is currently with the Communications Department and into the Institute of Telecommunications and Multimedia Application of the Polytechnic University of Valencia. His main research interests include microwave circuit and antenna analysis, design, and measurement.

Per-Simon Kildal (F’95) received the M.Sc. degree in engineering and two Ph.D. degrees from the Norwegian Institute of Technology, Trondheim, Norway. He has been a Professor with Chalmers University of Technology, Gothenburg, Sweden, since 1989, where he now heads the Division of Antenna Systems of the Department of Signals and Systems. He has authored an antenna textbook and more than 150 journal articles and letters. He has designed two very large antennas, including the Gregorian dual-reflector feed of the Arecibo radiotelescope. He has invented several reflector antenna feeds, the latest being the so-called “Eleven antenna.” He is the originator of the concept of soft and hard surfaces, recently resulting in the gap waveguide, a new low-loss metamaterial-based transmission line advantageous in particular above 30 GHz. He has received large individual grants from the Swedish research council VR and from the European Research Council ERC for research on gap waveguides. His research group has pioneered the reverberation chamber into an accurate measurement tool for antennas and wireless terminals subject to Rayleigh fading. This has been successfully commercialized in Bluetest AB. Prof Kildal was the recipient of two Best Paper Awards for articles published in the IEEE TRANSACTIONS ON ANTENNAS AND PROPAGATION, and he was the recipient of the 2011 Distinguished Achievements Award of the IEEE Antennas and Propagation Society.

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A Flip-Chip Packaging Design With Waveguide Output on Single-Layer Alumina Board for E-Band Applications Yang Zhang, Student Member, IEEE, Dixian Zhao, Member, IEEE, and Patrick Reynaert, Senior Member, IEEE

Abstract—This paper presents a millimeter-wave (mm-wave) packaging design for E-band long-haul point-to-point communications. A broadband flip-chip interconnect with standard 75 m pad pitch is developed on an alumina substrate. To meet the application requirement, a microstrip line to WR-12 waveguide (WG) transition is proposed. The transition has no back-short cavity or modified WG involved. A back-to-back transition measurement is conducted to characterize the performance. Results show that the working bandwidth is from 69.5 to 87 GHz and the insertion loss at 77 GHz is less than 0.5 dB. A 40-nm CMOS power amplifier is packaged and measured with the proposed packaging design. The entire packaging loss is only 2.5 dB from pads to WG, including the loss of a 10-mm microstrip line. The simulated and measured results are in good agreement. The gain and peak output power are 13.4 dB and 17.6 dBm. The silicon temperature is measured as 44.4 C after saturated output for 30 min. The performance is close to probe measurement after deembedding the packaging loss. Comparison between bondwire and flip-chip packaging is discussed and both are verified in mm-wave packaging design. Index Terms—CMOS, E-band, flip-chip, millimeter-wave (mmwave), packaging, power amplifier (PA), rectangular waveguide (RWG), wideband transition.

I. INTRODUCTION

A

PPLICATIONS in millimeter-wave (mm-wave) range, such as high data-rate personal area networks (60 GHz), automobile radar systems (77 GHz), high-resolution imaging systems (94 GHz), and E-band long-haul point-to-point communications (71–76 and 81–86 GHz) have drawn great attention in recent years [1]–[5]. Advanced CMOS technology manifests itself in high yield, high integration density, and low cost in production volume, which are essential to the population of realizing compact commercial systems for these mm-wave application areas [6]–[10]. To implement fully functional system integration, system-on-chip (SoC) is widely chosen, as it avoids Manuscript received June 14, 2015; revised November 07, 2015 and February 15, 2016; accepted February 20, 2016. Date of publication March 14, 2016; date of current version April 01, 2016. Y. Zhang and P. Reynaert are with the Department of Electrical Engineering, Micro-Electronics and Sensors (ESAT-MICAS), University of Leuven, B-3001 Leuven, Belgium (e-mail: [email protected]; [email protected]). D. Zhao is with the National Mobile Communication Research Laboratory, Southeast University, Nanjing 210018, China (e-mail: [email protected]. cn). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2536602

the lossy interconnect. However, on-chip passive components such as antennas are still bulky in mm-wave range, and suffer from performance deterioration caused by the lossy silicon substrate and inter-metal-layer space limitation. On the other hand, system-in-package (SiP) is a more appropriate approach in mm-wave applications. Instead of building everything on a single die, bulky components and functional units are designed on different carriers, thus flexibilities are introduced into design and high performance could be achieved. Among the solutions available, embedded wafer-level packaging and embedded wafer-level ball grid array (eWLB) are attractive for mm-wave applications [11]–[13]. They enable high-level system integration when numerous I/O pins are used. The high integration is achieved by utilizing redistribution layers (RDLs) and through silicon vias (TSVs). However, the RF signal interconnections still remain challenging. RF signals are quite sensitive to the surroundings and the parasitics of the interconnection will affect the performance dramatically. The matching design and parasitics modeling are not mentioned in [11]. Also, extra interconnect would add more loss. For example, 0.8-dB loss is added due to transferring channel [12]. Wire-bonding is an interconnect technology that is widely used in mm-wave system packaging solutions. By designing matching network to compensate for the parasitic inductance of connecting wires, a good interconnect between chip and printed circuit board (PCB) can be obtained [14]–[23]. However, the performance is relatively narrowband and lossy. Reference [15] proposed a dc–84-GHz interconnect by introducing an impedance transition on the chip. In this method, extra chip area is occupied and excessive grounded wires are used. The self-resonance frequency of the bondwire is also not mentioned. References [18] and [23] proposed a new L–C–L structure to compensate for the bond-wire influence. This design has the potential to achieve wideband interconnect above 100 GHz, but extra matching wires have to be used. References [19] and [20] demonstrated a bond-wire interconnection with wideband (67–110 GHz) and low-loss performance. The chip is placed into a cavity to reduce the wire length and characteristic impedance of the TL is chosen as 83 to improve the matching. On the other hand, flip-chip technology is an alternative option that has proven itself as the most promising solution for compact, low-loss, and broadband packaging technology [24]–[27]. The parasitic effect is much smaller than bond-wires. Characterization of the flip-chip interconnect has been verified at 120 GHz in [25]. Reference [27] proposed a

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high-impedance coplanar waveguide (CPW) matching network for W-band applications. Another important issue is wideband transmission line (TL) to rectangular waveguide (RWG) transition. RWG is an important signal carrier for the mm-wave system due to its low loss, simple topology, and high power-handing capability. It has been chosen as the type of testing ports of most of the measurement equipment. A good transition enables easy measurement setup for device testing. More importantly, in E-band communication systems, the antennas used in both transmitter and receiver sides should have a gain around 50 dBi (minimum 43 dBi) to overcome the attenuation while extending the link distance and minimize the interference to other users [6]. To meet the gain requirement, reflector antennas with a WG feed port are typically used. Therefore, a good TL to RWG transition is needed. Recently, various RWG transitions have been published in the literature. A V-band substrate integrated waveguide (SIW) to RWG transition with more than 35% bandwidth (BW) is reported in [28]. The SIW is a competitive planar signal carrier in mm-wave applications as the smaller dimension enables compact system integration. Also, it avoids using very thin metal lines and electromagnetic interference (EMI) problem because the signal is shielded. Since the SIW is a substrate-filled WG and realized with PCB technology, given a fixed substrate thickness, it is difficult to tune its impedance and low-loss material should be used. Reference [29] proposed a vertical transition from coupled microstrip line to RWG with 14.5-GHz BW (center frequency 96 GHz). References [19] and [20] presented a 67–110-GHz CPW to RWG transition. Reference [30] presented a W-band low-temperature co-fired ceramic (LTCC) transition from microstrip line to RWG. Reference [31] presented a microstrip line to RWG transition with 15% BW in E-band. These transitions show excellent performance within the working frequency range. However, either a multiple-layer process or modified WG flanges or back-short cavity have to be used. Additional fabrication errors are inevitable due to complex installation. In this paper, a flip-chip packaging design from bond-pad to standard RWG (WR-12) port is proposed for E-band long-haul communication systems. This work is an expansion of [21]. The cross-section view of the architecture is shown in Fig. 1. The proposed packaging is realized on a single-layer alumina board. The first part is a broadband flip-chip interconnect to microstrip line. The on-chip ground–signal–ground (G–S–G) pads have the same 75- m standard pitch as the 110-GHz probe so the chip characteristics could be measured with a probe station before packaging. The second part is a microstrip line to WR-12 standard RWG transition. The working frequency range is improved to cover the entire 71–86-GHz BW by suppressing higher order mode. There is no back-short cavity or modified WG involved. At last, a 40-nm CMOS E-band power amplifier (PA) assembled with the proposed design is measured. The measurements agree well with simulation, which verifies the validity of the design. Including loss of the 10-mm micristrip line, from chip side to WG output port, measurement shows an insertion loss of 2.5 dB, which satisfies the packaging loss requirement and leaves 5-dB margins for transmitter and receiver antenna alignment loss [6]. This paper is arranged as follows: The flip-chip to microstrip interconnect analysis is in Section II. The microstrip line to

Fig. 1. Cross-section view of the proposed mm-wave packaging design from chip to WR-12 RWG.

standard WR-12 waveguide (WG) transition and BW enhancement design are discussed in Section III. Measurement results of a packaged E-band PA are presented in Section IV. Comparison between flip-chip and bondwire packaging is discussed in Section V. A final conclusion is given in Section VI. II. CHIP PACKAGING WITH FLIP-CHIP INTERCONNECT A. Flip-Chip to Microstrip Interconnect Compared with the bond-wire interconnect, the flip-chip is more promising thanks to its smaller parasitic effects. An intuitive sense is that the width and spacing of the PCB trace is limited by the pad dimension. As in the work in [32], a good interconnect can be realized if the impedance of the PCB TL and pad impedance are close to each other 50 . However, the liquid crystal polymer (LCP) substrate thickness in [32] has to be reduced down to 50 m to satisfy both conditions at the same time. Although a good matching is achieved, the sample is soft and vulnerable. In other cases, the first step is to estimate the parasitic elements of the bumps and extract the equivalent circuit for further matching. Secondly, according to the moving track of the impedance at the target frequencies, design a matching network to bring the impedance point back to the center 50 of the Smith chart, which usually could be achieved by using a certain length of high impedance TL [26], [27]. In this design, the alumina is chosen to be carrier substrate based on the following considerations: 1) standard fabrication process; 2) mechanical strength and thermal stability to endure flip-chip process; and 3) excellent performance at high frequencies. The thickness, permittivity, and loss tangent of the alumina substrate are 254 m, 9.5, and 0.004 at 80 GHz, respectively. These would enable the width and gap of the 50- CPW line close to the pad dimensions, which have the size of 40 m by 50 m and a standard pitch of 75 m. The flip-chip interconnect design is performed in the High Frequency Structure Simulator (HFSS), as shown in Fig. 2. The chip is replaced by 300- m-thick silicon and the active circuit on the chip is replaced by a lumped port, which is connected to the G–S–G pads with the help of a short perfect conductor. The ground beneath the chip is removed to avoid an undesired impact on the on-chip passive components. Grouped metal-filled vias on each side connect the top and bottom ground together. These vias are placed as such to form a wideband transition from grounded

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Fig. 5. Performance against bump radius variation when bump height is set as 20 m. (a) S11. (b) S21. Fig. 2. Simulation model of flip-chip interconnect in HFSS and gold bump photograph before flipping.

Fig. 3. Equivalent circuit of flip-chip bumps.

Fig. 6. Performance against bump height variation when bump radius is set as 20 m. (a) S11. (b) S21.

Fig. 7. Performance against different underfill materials. (a) S11. (b) S21.

Fig. 4. Simulated S-parameters of flip-chip interconnect from on-chip G–S–G bond pads to microstrip line.

CPW to microstrip line and also enhance the heat dissipation to the bottom metal ground. The microstrip line output goes into the WG transition. The height and radius of gold bumps are both set as 20 and 30 m in simulation. The equivalent circuit of the bump interconnect is shown in Fig. 3. Since the characteristic impedance of both the bond pad and grounded CPW line is 50 , a good interconnect is achieved without a compensation network [32]. The resonant peak between 80 and 100 GHz is due to the grounded CPW to microstrip line transition. Simulated S-parameters are shown in Fig. 4. Return loss is lower than 14 dB up to 100 GHz and insertion loss is 0.5 dB at 77 GHz.

then keep one constant and sweep the other one. The results are shown in Figs. 5 and 6. It is clear that the performance is improved when the radius and height decrease. A similar result is achieved with [32]. In this design, the pad size is 40 m by 50 m with 75 m pitch (70 m by 70 m with 90- m pitch in [32]). Since the signal-ground gap is larger and the pad is smaller, the capacitance effect is small and overruled by the inductance effect. Fig. 7 shows the simulated S-parameters with different underfill materials. The main influence of using different underfill materials in flip-chip design is changing the equivalent permittivity of the environment [33]. The impedance of the TL will be changed accordingly. As seen from the result, better performance is achieved with low permittivity. III. MICROSTRIP TO WG TRANSITION

B. Parametric Analysis

A. Simulation Model and Mode Analysis

To analyze the effect of the bump variation to the interconnect performance, the dimensions of the G–S–G bumps are swept in simulation. The radius and height are both set as 20 m,

The proposed single-layer microstrip line to WR-12 WG transition is shown in Fig. 8(a) and the dimensions are given in Fig. 8(b). Fig. 9 illustrates the mode transition from the QTEM

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Fig. 9. Mode transformation from QTEM to

mode.

Fig. 8. Geometry of the proposed microstrip to RWG transition on alumina board: (a) overview and (b) parameters, unit in m.

mode to mode. The microstrip line connecting to the flipchip packaging is located on the top metal layer of the alumina substrate. Two coupling patch elements are placed at the bottom metal layer facing to the WG, which is mounted to the substrate by screws. Metallized vias are placed around the transition area to connect top and bottom grounds and form a good shielding. As shown in Fig. 10, the simulated return loss is better than 15 dB from 71 to 86 GHz. Since there is no back-short cavity to shield the signal, the backside radiation leakage might be an issue to deteriorate the transition performance. The radiation loss is simulated when the signal is fed from the microstrip port and WG port. As shown in Fig. 11, within the targeted frequency range only around 5% of the signals get radiated out. It also means that the transition is practically not affected by any metal appearing behind the PCB. From 70.15 to 87.2 GHz, the average insertion loss is less than 0.5 dB. Traditional design for WG transition on single-layer substrate is using a rectangular patch element facing to the WG [34]. The signals get coupled from the top CPW to bottom patch. Between this patch and the rest of the ground, two slots are formed to radiate into the WG. Unfortunately, this method is not suitable for transition design on a substrate with high permittivity. Due to the high-permittivity property, the substrate wavelength becomes much shorter (1.22 mm at 80 GHz). The phase of the

Fig. 10. Simulated S-parameters of the microstrip line to RWG transition.

Fig. 11. Backside radiation loss of the proposed transition.

-field in the two slots are reversed to each other, thus instead of the mode, the TM mode will be excited. Since the TM mode has a cutoff frequency higher than 90 GHz, strong reflection occurs at the microstrip line port. To take advantage of the

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short wavelength in the alumina substrate, in the proposed design, the rectangular patch is split into two parts. One extra slot is introduced into the interface between the two patches. By sizing the two patches, this new slot creates proper phase shift between the other two slots and, thus, the -fields of these three slots are in-phase. Therefore, the fundamental mode is excited into the WG. The design procedure is as follows: 1) set the width of these three slots constant; 2) aiming the center frequencies at 77 GHz, move the position of the middle slot, i.e., sweep the width of the two patches; and 3) finally optimize the length of the two patches. Simulation shows that better performance is achieved when the middle slot width is larger than the other two. It should be mentioned that although a rectangular slot is a resonant structure with narrow working BW, the combination of the three slots enables a wideband operation in this design. B. BW Optimization The initial model shows the lower limit of working frequency is 73.3 GHz, which is not adequate for the application. In order to realize a WG transition, which covers the entire 71–86 GHz, the magnitude distributions of the -field at the WG interface is studied, as shown in Fig. 12. As can be seen in the left plot of Fig. 12(a), the mode is excited at the interface, which could not propagate in WR-12 WG (cutoff frequency higher than 90 GHz). A strong reflection thus occurs at the frequencies below 73.3 GHz. This phenomenon is a result of that the wavelength in the alumina substrate is much smaller. The size of the standing wave is smaller than the long side of the RWG, and therefore, an induced traveling current occurs along the boundary. The mode can be compressed by shrinking the dimension of the transition interface and blocking its induced current on the boundary. The improved WG interface is shown in Fig. 12(b). Firstly, the long boundary of the interface is shortened from standard 3.988 to 2.5 mm to reduce the electrical length of the interface and to form a good standing wave. A line of choke slots (teeth) are then placed along the two short boundaries to further block the induced current. The second technique is a typical method used in planar tapered slot antenna design, which suffers from sidelobe radiation due to the boundary current. By placing choke slots along the boundary, the traveling current is reduced [35]. The “teeth” dimension can be calculated according to operating frequency in antenna design. In this design, the dimension is swept and the optimized “teeth” width and slot width are chosen as 120 and 245 m. Fig. 12(b) shows the electrical field comparison with/without choke slots at 71 GHz. The mode is compressed at the boundaries and the fundamental mode is formed by the coupling patches. The simulated S-parameters of the transition before and after modifying the coupling interface are presented in Fig. 13. As can be seen, the lower working frequency moves from 73.3 to 70.15 GHz. The simulated S-parameters of the final design are shown in Fig. 10. A promising microstrip to WR-12 WG transition covering the targeted frequency range from 70.15 to 87.2 GHz is achieved. The insertion loss at 77 GHz is less than 0.5 dB. The co-simulation model of the entire G–S–G pads to RWG transition is shown in Fig. 14. To keep the chip away from the actual WG flange (otherwise flange metal will affect the performance of the chip), a 10-mm microstrip line is used. The

Fig. 12. BW enhancement: (a) transition interface and (b) comparison at 71 GHz.

-field distribution

Fig. 13. Comparison of simulated S-parameters of BW improvement.

simulated S-parameters are shown in Fig. 15. As can be seen, a G–S–G pads to WR-12 standard RWG transition is achieved from 70 to 87 GHz, with an average insertion loss of 2.5 dB. IV. FABRICATION AND MEASUREMENT RESULT ANALYSIS A. Microstrip to WR-12 WG Transition To verify the performance of the transition, a back-to-back configuration (WG-to-WG) was fabricated and measured.

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Fig. 14. Simulated model of G–S–G pads to RWG transition.

Fig. 16. Photograph of the fabricated back-to-back transition board.

Fig. 15. Simulated S-parameters of G–S–G pads to RWG transition, including 12-mm microstrip line.

Fig. 16 shows a photograph of a back-to-back WG to microstrip transition board. The result will also be used for estimating the loss in the packaged PA measurement. The S-parameter measurement was conducted using an R&S vector network analyzer with E-band extenders. The measurement WG ports were screwed to the bottom of the board with the help of two 90 WR-12 bends. A WG through-open-short-match (TOSM) calibration was performed to the output port of the bends. Simulated and measured S-parameters are presented by dashed and solid lines in Fig. 17. Measured result indicates that the proposed transition has a return loss better than 10 dB from 69.5 to 87 GHz. Both simulation and measurement results show the insertion loss is 2.5 dB at 77 GHz. Since the simulated transmission loss of the 20-mm microstrip between two transitions is 1.7 dB, the insertion loss of a single transition should be better than 0.5 dB. The proposed design utilizes standard WG and expensive modified WG components or back-short cavity is avoided, therefore, the cost is reduced. In the meantime, minimization of fabrication errors and complexity are achieved. Table I gives a performance comparison of WG transitions among the literature.

Fig. 17. Simulated and measured S-parameters of the back-to-back transition.

TABLE I COMPARISON

B. Packaged CMOS PA A 40-nm CMOS PA is packaged and measured with the proposed design. The gold bumps were placed on the pads, and then the chip was flipped onto the substrate. During the flip-chip process, the chip was pressed with 3-N force for 300 ms and the operating temperature is 80 C. The chip was glued to the board

for protection using EPO-TEK H54 (permittivity 3.21, loss tangent 0.003 at 1 kHz) and there is no underfill material beneath the chip. After pressing the chip for adhesion, bump radius is around 30 m, leaving only a 10- m gap between each other.

ZHANG et al.: FLIP-CHIP PACKAGING DESIGN WITH WG OUTPUT ON SINGLE-LAYER ALUMINA BOARD

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Fig. 20. Simulated and measured S-parameters of the packaged PA.

Fig. 18. Packaged PA measurement. (a) S-parameter measurement. (b) Temperature measurement.

Fig. 21. Comparison of measured peak output power among bare die, bondwire packaging, and flip-chip packaging [6], [21].

Fig. 19. Photograph of flip-chip packaged PA with WG transition.

To avoid short connection, two ground bumps were placed deviating the pad center and the metal trace on the PCB was therefore extended. By doing this the bump parasitic capacitance was increased [32]. To ensure the matching, the impedance of the CPW line is correspondingly increased [26]. S-parameters and temperature measurement setup are shown in Fig. 18. A photograph of a flip-chip packaged E-band CMOS PA board is shown in Fig. 19. The PA has a supply voltage of 0.9 V. The simulated and measured S-parameter results are presented in Fig. 20. A simulation result was obtained by combining -matrices of the chip and two G–S–G to WG transitions in Agilent Technologies’ Advanced Design System (ADS). Excellent agreement is achieved between simulated and measured results. A good

matching is obtained within the 71–86-GHz range and is lower than 30 dB in the entire E-band. Probe measurement shows the chip has a peak gain of 18.1 dB and packaging measurement achieves 13.4 dB. Considering the loss of two flip-chip interconnects, 20-mm microstrip line, and two WG transitions, the difference is less than 1 dB. The output power is measured using the Aglient E4418B power meter. The measured peak power versus frequency is presented in Fig. 21. The maximum output power is 17.6 dBm at 75 GHz. Since the chip performance is strongly affected by the increasing temperature, and to test the dissipation performance of the packaging, the packaged PA was set under saturation output condition, 77 GHz, in a 25 C environment for 30 min. A sensor is placed on top of the silicon substrate to collect the temperature information. The output power and consuming current keep stable during the entire test time. The temperature on the silicon surface is measured as 44.4 C.

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Fig. 22. Comparison of gain performance among bare die, bond-wire packaging, and flip-chip packaging [6], [21].

V. COMPARISON WITH BONDWIRE PACKAGING A bond-wire packaging design using the same CMOS PA chip was presented in [21]. The chip was placed into a cavity on the board to reduce the wire length. The equivalent inductance of the bond-wire interconnect is calculated and compensated with TLs. Although the wire length is carefully controlled, it is still a bit longer than expected. Gain and peak output power comparisons are shown in Figs. 21 and 22, respectively. Sample photographs of the bondwire and flip-chip interconnects with the same chip are presented in Fig. 23. The bondwire packaging achieves peak gain and output power of 11.7 dB and 16.3 dBm, respectively, in measurement. According to the measurement results, bond-wire interconnection shows a good performance and the wire-bonding packaging performance is mainly limited by the WG transition. In this work, the WG transition is optimized to achieve good performance from 69.5 to 87 GHz. Both flip-chip and bond-wire interconnects are verified to be valid in millimeter-wave packaging design. As frequency goes higher, the parasitic element of the connection becomes dominant and will significantly impact the system performance. In mm-wave bond-wire packaging design, the wire length is preferred to be reduced, usually by eliminating the height difference between the chip and substrate [20]. Although the equivalent inductance of the bond-wire can be modeled and calculated, it is still not sufficient to support the interconnect design. Firstly, the wire landing point on the substrate can be accurately controlled, but the actual wire length still suffers from fabrication inconsistency. Secondly, PCB details should be included in simulation environment. The ground terminal of the TL and via distribution have a severe influence on the practical wire model. Therefore, a set of simulations should be run to enhance the design stability. Another issue is that the wire self-resonant frequency should be away from the target frequency range or a more complex model should be provided. To design a good flip-chip packaging there are some matters that need to be considered: since the output power is large, input and output RF grounds need to be sepa-

Fig. 23. Photograph of packaged chip: (a) chip with bumps before packaging (left), X-ray photograph of packaged PA (right), (c) bond-wire interconnect in [21].

rated from each other to avoid feedback current and, thus, the circuit stability is improved. Remove the metal below the chip to avoid a detuning effect of the on-chip passive components. The overlap between the pads and connecting trace needs to be minimized to reduce parasitic capacitance. Smaller connecting bumps are preferred to achieved better performance and interconnect design should be able to endure bump size variation. A carrier substrate is preferred to enable the impedance of the connecting trace close to 50 , and have good thermal stability to endure the flip-chip process. VI. CONCLUSION A flip-chip packaging design with an RWG output port has been implemented on a single-layer alumina substrate, which is suitable for E-band long-haul communications. A broadband flip-chip interconnect is designed with standard 75- m pitch. To satisfy the application requirement, a single-layer microstrip line to WR-12 RWG transition is theoretically and experimentally studied. Its working BW covers from 69.5 to 87 GHz. By eliminating the TL loss, the insertion is less than 0.5 dB at 77 GHz. The packaging design utilizes a standard process and components. The proposed solution is verified by measuring a 40-nm CMOS E-band PA chip. Simulated and experimental results are in good agreement. The chip temperature is measured after operating at peak output state for 30 min. The packaged PA achieves a peak gain and peak power of 13.4 dB and 17.6 dBm, respectively. After deembedding the loss, the measured result achieves similar performance with probe measurement. Finally, a comparison between flip-chip and bond-wire packaging is discussed and both are verified in a mm-wave packaging design. ACKNOWLEDGMENT The authors would like to thank F. Daenen and N. Gaethofs for their great support in the measurement.

ZHANG et al.: FLIP-CHIP PACKAGING DESIGN WITH WG OUTPUT ON SINGLE-LAYER ALUMINA BOARD

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[21] Y. Zhang, D. Zhao, and P. Reynaert, “Millimeter-wave packaging on alumina board for E-band CMOS power amplifiers,” in Proc. IEEE Power Amplifier Wireless Radio Appl. Top. Conf., Jan. 2015, pp. 1–3. [22] T. Krems, W. Haydl, L. Verweyen, M. Schlechtweg, H. Massler, and J. Rudiger, “Coplanar bond wire interconnections for millimeter-wave applications,” in Electr. Perform. Electron. Packag., Oct. 1995, pp. 178–180. [23] V. Valenta, H. Schumacher, T. Spreng, V. Ziegler, D. Dancila, and A. Rydberg, “Experimental evaluation of differential chip-to-antenna bondwire interconnects above 110 GHz,” in Proc. 44th Eur. Microw. Conf., Oct. 2014, pp. 1008–1011. [24] C.-C. Kuo, H.-C. Lu, P.-A. Lin, C.-F. Tai, Y.-M. Hsin, and H. Wang, “A fully sip integrated V-band Butler matrix end-fire beam-switching transmitter using flip-chip assembled CMOS chips on LTCC,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 5, pp. 1424–1436, May 2012. [25] S. Beer, H. Gulan, C. Rusch, and T. Zwick, “Integrated 122-GHz antenna on a flexible polyimide substrate with flip chip interconnect,” IEEE Trans. Antennas Propag., vol. 61, no. 4, pp. 1564–1572, Apr. 2013. [26] A. Jentzsch and W. Heinrich, “Theory and measurements of flip-chip interconnects for frequencies up to 100 GHz,” IEEE Trans. Microw. Theory Techn., vol. 49, no. 5, pp. 871–878, May 2001. [27] H.-C. Lu et al., “Flip-chip-assembled W-band CMOS chip modules on ceramic integrated passive device with transition compensation for millimeter-wave system-in-package integration,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 3, pp. 766–777, Mar. 2012. [28] Y. Li and K.-M. Luk, “A broadband V-band rectangular waveguide to substrate integrated waveguide transition,” IEEE Microw. Wireless Compon. Lett., vol. 24, no. 9, pp. 590–592, Sep. 2014. [29] Z. Tong and A. Stelzer, “A vertical transition between rectangular waveguide and coupled microstrip lines,” IEEE Microw. Wireless Compon. Lett., vol. 22, no. 5, pp. 251–253, May 2012. [30] B. Cao, H. Wang, Y. Huang, J. Wang, and W. Sheng, “A W-band lowloss and wideband LTCC transition from waveguide to microstrip,” IEEE Microw. Wireless Compon. Lett., vol. 23, no. 11, pp. 572–574, Nov. 2013. [31] E. Topak, J. Hasch, and T. Zwick, “Compact topside millimeter-wave waveguide-to-microstrip transitions,” IEEE Microw. Wireless Compon. Lett., vol. 23, no. 12, pp. 641–643, Dec. 2013. [32] W. Khan, A. Lopez, A. Ulusoy, and J. Papapolymerou, “Packaging a W-band integrated module with an optimized flip-chip interconnect on an organic substrate,” IEEE Trans. Microw. Theory Techn., vol. 62, no. 1, pp. 64–72, Jan. 2014. [33] Z. Feng, W. Zhang, B. Su, K. Gupta, and Y. Lee, “RF and mechanical characterization of flip-chip interconnects in CPW circuits with underfill,” IEEE Trans. Microw. Theory Techn., vol. 46, no. 12, pp. 2269–2275, Dec. 1998. [34] H. Iizuka, K. Sakakibara, and N. Kikuma, “Millimeter-wave transition from waveguide to two microstrip lines using rectangular patch element,” IEEE Trans. Microw. Theory Techn., vol. 55, no. 5, pp. 899–905, May 2007. [35] G. Teni, N. Zhang, J. Qiu, and P. Zhang, “Research on a novel miniaturized antipodal vivaldi antenna with improved radiation,” IEEE Antennas Wireless Propag. Lett., vol. 12, pp. 417–420, 2013.

Yang Zhang (S’15) received the M.Sc. degree in electromagnetic field and microwave technology from the Harbin Institute of Technology, Harbin, China, in 2013, and is currently working toward the Ph.D. degree at the University of Leuven (KU Leuven), Leuven, Belgium. His current research interests include millimeterwave CMOS circuits, packaging, and interface design.

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Dixian Zhao (S’10–M’15) received the B.Sc. degree in microelectronics from Fudan University, Shanghai, China, in 2006, the M.Sc. degree in microelectronics from the Delft University of Technology (TU Delft), Delft, The Netherlands, in 2009, and the Ph.D. degree from the University of Leuven (KU Leuven), Leuven, Belgium, in 2015. From late 2005 to 2007, he was with the Auto-ID Laboratory, Fudan University, where he developed nonvolatile memory for passive RF identification (RFID) tags. From 2008 to 2009, he was an Intern with Philips Research, Eindhoven, The Netherlands, where he designed a 60-GHz beamforming transmitter for presence detection radar. From 2009 to 2010, he was with TU Delft, where he designed a 94-GHz wideband receiver for imaging radar. From 2010 to 2015, he was a Research Associate with KU Leuven, where he was involved with 60-GHz and E-band transmitters and power amplfiers. Since April 2015, he has been an Associate Professor with Southeast University, Nanjing, China. His current research interests include RF and millimeter-wave integrated transceiver and power amplifier for wireless communications. Dr. Zhao was the recipient of the IEEE Solid-State Circuits Society Predoctoral Achievement Award (2014), the Chinese Government Award for Outstanding Students Abroad (2013), the Top-Talent Scholarship from TU Delft (2007 and 2008), and the Samsung Fellowship (2005).

Patrick Reynaert (SM’11) was born in Wilrijk, Belgium, in 1976. He received the Master of Industrial Sciences in Electronics (ing.) degree from the Karel de Grote Hogeschool, Antwerpen, Belgium, in 1998, and the Master of Electrical Engineering (ir.) and Ph.D. in Engineering Science (dr.) degrees from the University of Leuven (KU Leuven), Leuven, Belgium in 2001 and 2006, respectively. From 2006 to 2007, he was a Post-Doctoral Researcher with the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA. During the summer of 2007, he was a Visiting Researcher with Infineon, Villach, Austria. Since October 2007, he has been a Professor with the Department of Electrical Engineering (ESAT-MICAS), KU Leuven. His main research interests include millimeter-wave and terahertz CMOS circuit design, high-speed circuits, and RF power amplifiers. Dr. Reynaert is a Chair of the IEEE Solid-State Circuits Society (SSCS) Benelux Chapter. He serves or has served on the Technical Program Committees of several international conferences including ISSCC, ESSCIRC, RFIC, PRIME, and IEDM. He has served as an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, and as a Guest Editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS. He was the recipient of a BAEF Francqui Fellowship. He was also the recipient of the 2011 TSMC-Europractice Innovation Award, the ESSCIRC-2011 Best Paper Award, and the 2014 2nd Bell Labs Prize.

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1

Synthesis and Design of Mixed Lumped and Distributed Low-Pass Filters/Low-Passing Impedance Transformers With Taylor Series Runqi Zhang, Member, IEEE, Sha Luo, Member, IEEE, and Lei Zhu, Fellow, IEEE

Abstract—In this paper, a synthesis method by applying the Taylor series is proposed to design a variety of low-pass mixed lumped and distributed circuit networks, including the low-pass filters and low-passing impedance transformers. First, the principle of applying the Taylor polynomials for these mixed circuit networks is discussed. Herein, the trigonometric functions, commonly used to characterize distributed circuits, are expressed in the form of polynomials by the application of Taylor polynomials. Therefore, the transfer function of the mixed networks is simplified from a multivariable to a polynomial form. Following this, a generic circuit structure is proposed to design either a low-pass filter or a low-passing impedance transformer with specified port impedances. The desired filtering function uses the similar method to transform the trigonometric function into a format of polynomials. Under the equalization of the transfer function and filtering function, all the unknown design parameters are obtained. As two examples, a low-pass filter and a low-passing impedance transformer are synthesized, designed, and fabricated to experimentally verify the proposed design approach. Index Terms—Low-pass filter, low-passing impedance transformer, mixed lumped and distributed circuit networks, synthesis and design.

I. INTRODUCTION

L

OW-PASS filters and low-passing impedance transformers have been widely used in wireless communication systems. Both of the two-port microwave circuits share certain common circuit geometries and design techniques. A classic impedance transformer design method is usually executed by cascading several transmission lines with equal lengths in order to form a short-step transformer, as introduced in [1]. Some other circuit structures of cascading transmission lines have been discussed in [2] to realize impedance transformers. For instance, a nonsynchronous noncommensurate impedance transformer has been designed in [3] using the design table. However, there are several issues needed to be

Manuscript received June 03, 2015; revised September 20, 2015 and February 18, 2016; accepted by February 23, 2016. R. Zhang and S. Luo are with the Department of Electrical and Computer Engineering, National University of Singapore, Singapore (e-mail: rzhang1@e. ntu.edu.sg; [email protected]). L. Zhu is with the Faculty of Science and Technology, Department of Electrical and Computer Engineering, University of Macau, Macau SAR, China (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2536598

considered while using this kind of circuit structure. The first one is its difficulty of realizing a large impedance ratio as it is sometimes practically impossible to match a very high or low impedance, as discussed in [4]. As the second issue, several step discontinuities involved in multi-stage transformers unfortunately introduce parasitic junction effects as equivalent shunt capacitors. In this aspect, they are rigorously modeled as a mixed lumped and distributed problem, as presented in [5]. The third issue is that its circuit structure is too large to be implemented in some practical applications, as discussed in [6]. To circumvent these problems, some new design methods have been proposed. In [7], a circuit prototype with shunt open stubs has been analyzed for low-pass filters. An even more compact short-step-stub transformer has been proposed in [6]. In the meantime, as pointed out and summarized in [8], a mixed lumped and distributed impedance transformer can provide several advantages, such as compact circuit size, large impedance ratio, etc. In [9], a low-pass filter is designed by parallel connecting a lumped capacitor on the two sides of a distributed transmission line. In this way, a compact size and sharply rejected operating band are both achieved. Replacing the shunt open stubs by the capacitors has successfully led to the design of a few low-pass filters and low-passing impedance transformers, as reported in [2] and [5]. However, it still lacks a direct linkage between the transfer function and the filtering function. In [8], a concept of the generalized unit element has been proposed to treat the mixed circuit as a section of generalized transmission line. However, the electrical length and characteristic impedance of the generalized transmission line are all frequency dependent, which limits its application up to a certain frequency. Thus, the prescribed bandwidth of the presented transformer cannot be guaranteed. Another technique is to use tapered lines by successively applying the Kuroda transformation as in [10] and [11]. However, this method requires complicated design and manufacture procedures. From the discussions above, the formulation of a mixed circuit network is needed to characterize the multivariable problem. As usual, most of the filtering functions are represented either by the trigonometric functions or by the polynomial variables, while the transfer function of a mixed circuit incorporates both of these two situations. Some reported works have tried to solve this problem, such as an optimization method, as proposed in [12] and [13], and the equivalent circuit method to model the mixed circuit as inverters in [14]. However, as far as the authors’ knowledge, little work has

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been extensively done so far in design of a mixed lumped and distributed circuit based on the relationship between the transfer function and the filtering function for the synthesis and design purpose. In this paper, the application of the Taylor series is proposed towards the synthesis and design of low-pass filters and low-passing impedance transformers using mixed lumped and distributed circuit structures. The trigonometric functions in both transfer and filtering functions are replaced by their polynomial forms with Taylor polynomials. By equating these two functions, the design parameters can be obtained. The validation of this method is based on the following two aspects. The first one is that the Taylor series is expanded at zero to gain a close approximation near the low-passing band. Therefore, the band-edge frequencies and ripple factors can be closely represented by the derived polynomials. The second aspect is that the distributed prototype circuit is transformed to its mixed circuit structure. Its transfer function is also expressed by the polynomials with the Taylor series. To verify the proposed design method, a low-pass filter and impedance transformer are designed, fabricated, and measured. The low-pass filter achieves a size reduction by about 34% compared with its quarter-wavelength distributed or mixed lumped and distributed counterparts. The low-passing impedance transformer achieves size a reduction by about 75% compared with its quarter-wavelength counterpart. Both the circuits actually push the first harmonic passbands up to or beyond the ones of the distributed circuits, thereby improving the out-of-band rejection or widening the upper stopband as usually demanded. Primary advantages of the proposed synthesis method and generic circuit network are summarized as follows. 1) Proposed mixed circuits can realize an even more compact structure than the classical quarter-wavelength structure by introducing a transmission-line scaling factor. 2) Harmonic passbands are pushed away from the desired low passband so as to enhance the out-of-band rejection. 3) In-band circuit responses are made closely enough to the theoretical filtering responses, thus facilitating the synthesis procedure. II. TAYLOR SERIES FOR APPLICATION IN MIXED CIRCUIT The application of Taylor series in the mixed circuit starts with the study on a single section of transmission-line circuit. A single section of transmission line is shown in the inset of

Fig. 1. Frequency responses of the practical circuit and their counterparts with Taylor polynomials of degree 1 and 3. (a) Transmission line ( and rad/s). (b) Mixed circuit of a scaled transmission line and two , capacitors shunt on the two sides of the transmission line ( , , and F).

Fig. 1(a), whereas its counterpart with two capacitors shunted at its two ends is illustrated in Fig. 1(b). As discussed in [4], [7], [15], and [16], the capacitive loading transmission line is a wellknown circuit structure used for miniaturization of many planar circuits, inclusive of filters, impedance transformers, couplers, and power dividers. However, the respective analysis is executed under the restriction of one frequency point so this approach is only valid for a narrow bandwidth case. One motivation of this work is to apply the Taylor series as discussed below towards solving this problem. The matrices of these circuit networks can be simply expressed as (1a) and (1b), shown at the bottom of this page, where and are the electrical lengths of the two transmission

(1a)

(1b)

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. ZHANG et al.: SYNTHESIS AND DESIGN OF MIXED LUMPED AND DISTRIBUTED LOW-PASS FILTERS/LOW-PASSING IMPEDANCE TRANSFORMERS

lines, respectively, and are the characteristic impedances, and is the capacitor. Under the normalized condition, the transfer functions of these two circuit structures are calculated by as

3

(5b) where

(2a)

(2b) As seen from (2b), characterizing the mixed circuit is a multivariable problem where both the transmission line and lumped elements are taken into consideration. In the synthesis approach, the most difficult task is to make these two transfer functions equal to each other. In this situation, the capacitors contribute to a semi-polynomial form, as and , and they cannot be directly incorporated into the trigonometric calculation. To get a direct linkage between these two transfer functions, a direct method is proposed to initially equate them at a single frequency point, which is normally selected as the center frequency of the bandpass filter and the edge frequency of the low-pass filter. Herein, the Taylor series is used to expand the trigonometric functions in polynomial forms. Some commonly used trigonometric functions and the ones used herein are expanded at the point of zero as [17]

(3) where is a variable representing either or , and is the Bernoulli numbers. A scale factor is introduced to scale the electrical length to its counterpart in the mixed circuit as (4) This is an extra degree of freedom in controlling the length of the transmission line in the mixed circuit. When is chosen to be larger than 1, the circuit structure size is reduced and the out-of-band rejection is improved, as to be discussed later. The two functions in (2a) and (2b) are represented by the sum of infinite terms so the number of terms needs to be chosen for a practical analysis and calculation. The larger the number of terms, the closer the polynomial will represent the original function, but more calculation efforts will be required and a consideration of convergence will be examined. As an example, a degree of 5 is chosen here to truncate the transfer functions as (5a) where

and represents the factor of scaling the frequency electrical length as

to the (5c)

The analysis of (5a) and (5b) covers the following two aspects. The first one is that, after the replacement, the format of the two polynomials is similar, which is in the same degree (five degree and without the even degree terms) and the same variable . Therefore, there is a possibility to equate these two polynomials. The other is the relationship among the four transfer functions before and after the application of the Taylor series [see (2a)–(2b) and (5a)–(5b)]. According to the feature of the Taylor polynomials, the more degree of the polynomial used, the closer approximation it can achieve at its expansion point. Fig. 1 shows the plots of the original transfer function and their Taylor polynomials with degree 1 and 3, respectively, which supports this regulation. In the meantime, comparing between the frequency responses from the different transfer functions, but in the form of the polynomials of the same degree, they can be made similar to each other, when properly selecting their parameters. Based on these two factors, it can be concluded that it is possible to establish the relationship between the two transfer functions in a multivariable form by applying the Taylor series. First, all the trigonometric functions are replaced by their polynomial counterparts. Next, their coefficients of the same term are found to be equal. After the enforced equating, the frequency responses of the practical mixed circuits are made close to each other at the expansion point. Fig. 2 plots the obtained values of and through the proposed method. As increases, the electrical length of the mixed circuit becomes smaller. According to the analysis in [2], it can be figured out that this mixed circuit can achieve compact circuit size and push the harmonic resonances further away. III. SYNTHESIS OF FILTERS AND TRANSFORMER CIRCUITS From the above discussions, the proposed technique in application of the Taylor series is suitable for the design of low-pass filters and low-passing impedance transformers. As well implemented so far, the band-edge frequencies and the ripple factor are the critical design parameters in regulating the low-pass filtering responses. The Taylor series expanded at zero is used to closely approximate this part of the frequency responses. At the same time, the out-of-band rejection is represented by the filtering responses in the upper frequency range. Thus, the transfer function in a form of polynomials is still approximately used to estimate the design requirements. Before introducing the synthesis procedure, a generic circuit structure is discussed. The prototype of the distributed circuit of

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Fig. 2. Variations of and under different scaling factor (the characterand the electrical length istic impedance of the transmission line at the frequency of rad/s).

a short-step-stub structure is shown in Fig. 3(a), where the input and output impedances are normalized to 1 and , respectively. As illustrated in Fig. 3(b), the addition of the lumped capacitors are introduced. Herein, the open stub is replaced by the shunt capacitors, and the transmission line between the two stubs is replaced by a scaled transmission line with two shunt capacitors at the two sides. When incorporating all the shunt capacitors at the same node point, the mixed circuit is obtained as shown in Fig. 3(c). When this mixed circuit is used for the low-pass filter design, it is symmetrical with respect to the two ports and . As for the low-passing impedance transformers, the circuit structure is asymmetrical. However, it is noted that the design parameters in Fig. 3(c) cannot be obtained by replacing the open-circuited stubs/transmission line with their mixed circuits. It is because the proposed method focuses on the transfer function of the overall filter, but not an equivalent expression of any sub-circuit network. In the following, the synthesis of the low-pass filters and the low-passing impedance transformers will be discussed.

Fig. 3. Development of the mixed-circuit structure from the distributed circuit. (a) Distributed circuit of transmission-line structure. (b) Mixed circuit of replacing the open stub with a capacitor and the transmission line with a scaled length one with two capacitors shunt on the two sides. (c) Mixed circuit of incorporating the capacitors on the same node.

A. Synthesis of Low-Pass Filters The flowchart for the proposed synthesis procedure is illustrated in Fig. 4. First, the design specifications need to be prescribed, and they include the reference frequency , cutoff frequency , ripple factor , the number of the transmission-line elements , the number of the nonredundant stubs , transmission-line scale factor , and the degree of Taylor polynomial . The selection of will be discussed in the latter part. Next, the filtering function is derived based on the circuit structure with the selected and the cutoff electrical length , and it is expressed in the general form (6) where

For a special case of

, the filtering function becomes

Fig. 4. Flowchart of the synthesis procedure for the low-pass filter of mixed circuit structure.

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TABLE I STEPS IN SYNTHESIS AND RESULTS FOR LOW-PASS FILTER

(7) is the th-order Chebyshev polynomial, and the exwhere pressions of and are the even degree of the sine function as and , respectively. Therefore, the filtering function is derived as the multiplication of the tangent function of one degree and sine function of degree. Once the filtering function is derived, the transfer function of the low-pass filter can be calculated under the normalized condition (8) The expression of (8) actually indicates a multivariable problem. In the next step, all the trigonometric functions in the filtering and transfer functions will be replaced by their relative Taylor polynomial counterparts. The number of degrees to truncate the polynomial needs to be seriously discussed. If each trigonometric function is replaced with its one-degree polynomial, the transfer function in (8) would be a degree polynomial. This is a lowest number required to represent the frequency responses. In addition, the parameters and the transfer function are related through . As such, the degree of a polynomial for calculating the power of the parameters is . To make an accurate calculation, the degree of the Taylor polynomial is chosen as . In this way, the polynomial of degree going through the operation of will have the adequate influence on the lowest degree of the polynomial. Next, as reported in [18] and [19], these two transfer functions in the form of the polynomials are enforced to be equal to each other. The optimization tool available in the Toolbox of MATLAB (ver. R2010b) is used to solve this nonlinear equation. The selection of the initial value will affect the convergence when solving the nonlinear equations. A straightforward method is to find the lumped value evaluated at the cutoff frequency of the low-pass filter . The values of shunt capacitors to replace the shunt open stubs are estimated as (9) The capacitors, shunted on the two sides of the transmission line, are estimated as

(10) is estimated as . where Based on the above discussion, a low-pass filter is designed as an example to demonstrate our presented synthesis approach. The detailed steps in synthesis procedure is provided in Table I. Fig. 5 plots the comparison of frequency

Fig. 5. Comparison in frequency responses among the three synthesis approaches for low-pass filters of distributed and mixed-circuit networks.

responses from the classical distributed circuit, the previously reported mixed circuit in [4] and the proposed one in this work. Table II summarizes the calculated design parameters for these three distinctive circuits. It needs to be noted that the in-band frequency responses of these three circuits are almost identical, but their upper stopband responses become different in total. The distributed circuit has the largest out-of-band bandwidth and sharpest roll-off rejection skirt, but it has the largest circuit size among all of the three circuits. The mixed circuit, reported in [4], minimizes the overall circuit size, but it narrows the upper stopband. For the proposed circuit structure, it has the advantage in selecting the transmission-line scaling factor, privileging it in further minimizing the circuit size.

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TABLE II DESIGN PARAMETERS FOR THREE LOW-PASSING CIRCUITS*

TABLE III STEPS IN SYNTHESIS AND RESULTS FOR TRANSFORMER

Furthermore, the rejection-band performance is maintained as almost the same as that of the initial distributed circuit. B. Synthesis of Low-Passing Impedance Transformers Following a similar synthesis procedure as stated above, the low-passing impedance transformers with two unequal port impedances will be further discussed in this section. Different from the low-pass filter, the input and output normalized port impedances of an impedance transformer are set to be 1 and , respectively. Due to its unsymmetrical property, additional design parameters need to be involved in design of this transformer, and its relevant transfer function is (11) For most distributed circuits, their transfer function can be simplified as the anti-metric case of . However, for the cases discussed here, the general calculation, as given in (11), is discussed, which includes more unknown cases, but does not burden the calculation of polynomials. The filtering function, as referenced in [1], is used for the lumped-element quasi-low-passing impedance transformers as (12) where and are band-edge frequencies of a desired passband. The in-band ripple factor is directly dominated by the prescribed impedance transformation ratio such that (13) Similarly to the above procedure, the trigonometric function in the transfer function is replaced by its polynomial form, whereas the filtering function is derived as its polynomial form. As (12) is applied to define the degree of a polynomial, the number of degrees to truncate the Taylor series can be fixed. For an -order filtering response, is of degree, and is of degree, which asks for a number of to truncate the Taylor series. Table III shows the key steps in synthesis of the low-passing impedance transformer. For comparison, Fig. 6 is plotted to show the frequency responses from the distributed mixed circuit, as discussed in [7] and the one proposed here. It is seen that by shortening the length of the transmission line, the circuit size has been minimized and the first harmonic passband has been pushed upwards to a higher frequency. Thus, its out-of-band rejection has been improved. In Table IV, the design parameters of these circuit cases have been illustrated.

Fig. 6. Comparison in frequency responses among the three synthesis approaches for low-passing impedance transformers of distributed and mixed-circuit networks. TABLE IV LOW-PASSING IMPEDANCE-TRANSFORMER DESIGN PARAMETERS*

IV. RESULTS AND DISCUSSION In this section, the prototype low-pass filter and low-passing impedance transformer are designed and implemented by using the microstrip-line structure and the RF lumped capacitors.

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Fig. 7. (a) Photograph of the fabricated low-pass filter with the dimensions labeled. (b) Three sets of frequency responses derived from the synthesis approach, simulation, and measurement.

All the design specifications, synthesis procedure, and final design parameters are described before, and they are tabulated in Tables I and III, respectively. The substrate (RO4003C) with a dielectric constant of 3.55, loss tangent of 0.0027, thickness of 60 mil, and copper thickness of 0.035 mm is used in the design. The RF lumped capacitors are Murata GJM15 highseries of the 0402 package whose tolerances are mostly around 5% of their capacitances. A commercial full-wave simulator on the method of moment (MoM) in Advanced Design System (ADS), ver. 2005a is employed herein for simulation of the entire circuit layouts of these two filtering circuits. An Agilent network analyzer has been used to measure the scattering parameter of both the low-pass filters and the low-passing impedance transformers. In the practical implementation, the step-discontinuity effects happened at the interface of the two dissimilar microstrip lines with different characteristic impedances modeled as an equivalent shunt capacitor [20]. When considering this extra capacitor, the previously calculated capacitor in the above synthesis approach needs to be accordingly reduced. In addition, a packaged capacitor itself may have its limited quality factor, self-resonance frequency (SRF), etc., while the via-hole, used to ground the lumped element, may introduce an additional parasitic effects [21]. A. Results for Low-Pass Filter The photograph of the fabricated low-pass filter with all the dimensions denoted is provided in Fig. 7(a). As the immediate observation, the overall size of the proposed filter has been reduced by about 34% compared with the work in [5]. The measured results show that the 3-dB cutoff or band-edge frequency is 0.83 GHz, and the insertion loss (IL) is lower than 0.4 dB in the realized low passband, as can be seen in Fig. 7(b). The three sets of the results from the synthesis, simulation, and measurement, plotted in Fig. 7(b), are found in good agreement with each other over a wide frequency range.

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Fig. 8. (a) Photograph of the fabricated back-to-back transformer. (b) Frequency responses from the synthesis, EM simulation, and measurement.

B. Results for Low-Passing Impedance Transformer Herein, a low-passing impedance transformer with the two dissimilar port impedances, i.e., 50 and 10 , is designed using the above discussed synthesis method. In order to facilitate the microwave measurement, a back-to-back impedance transformer with input and output characteristic impedance of 50 at its two sides is fabricated. Fig. 8(a) shows its photograph with all the labeled dimensions. Compared with [4], the overall size of this transformer has been significantly reduced by about 75%. In Fig. 8(b), the three sets of results from the synthesis, electromagnetic (EM) simulation, and measurement are plotted together, and they agree well with each other again. The measured results show that the 10-dB reflection coefficient occupies an operating frequency band from 0.69 and 1.48 GHz, over which the minimum IL is 0.6 dB. The spikes as seen in Fig. 8(b) are caused by the back-to-back structure, which is introduced by a new resonant condition. Their different locations are caused by the frequency variant capacitance of the RF lumped capacitors and their fabrication tolerance. V. CONCLUSION A method of applying the Taylor series for synthesis and design of the mixed circuit has been proposed. The validation of applying the Taylor polynomials for the design of a generic low-passing mixed circuit has been conducted by a section of transmission line and its mixed circuit counterpart. Next, this generic circuit structure has been presented for the synthesis and design of a low-pass filter and a low-passing impedance transformer. The key idea in this proposed technique is to replace the trigonometric function in both the filtering function and the transfer function to a polynomial function. By equating these functions, all the design parameters can be explicitly determined. In the final section, the two design examples are provided to verify the proposed method in experiment.

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REFERENCES [1] G. L. Matthaei, “Short-step Chebyshev impedance transformers,” IEEE Trans. Microw. Theory Techn., vol. MTT-14, no. 8, pp. 372–383, Aug. 1966. [2] V. P. Meschanov, I. A. Rasukova, and V. D. Tupikin, “Stepped transformers on TEM-transmission lines,” IEEE Trans. Microw. Theory Techn., vol. 44, no. 6, pp. 793–798, Jun. 1996. [3] V. Zhurbenko and K. Kim, “Nonsynchronous noncommensurate impedance transformers,” Progr. Electromagn. Res. B, vol. 42, pp. 405–424, Jul. 2012. [4] R. Levy, “Synthesis of mixed lumped and distributed impedance-transforming filters,” IEEE Trans. Microw. Theory Techn., vol. MTT-20, no. 3, pp. 223–233, Mar. 1972. [5] R. Levy, “A generalized design technique for practical distributed reciprocal ladder networks,” IEEE Trans. Microw. Theory Techn., vol. MTT-21, no. 8, pp. 519–526, Aug. 1973. [6] P. W. Van Der Walt, “Short-step-stub chebyshev transformers impedance,” IEEE Trans. Microw. Theory Techn., vol. MTT-34, no. 8, pp. 863–868, Aug. 1986. [7] R. Levy, “A new class of distributed prototype filters with applications to mixed lumped/distributed component design,” IEEE Trans. Microw. Theory Techn., vol. MTT-18, no. 12, pp. 1064–1071, Dec. 1970. [8] L. Zhu and L. J. P. Linne’r, “Mixed lumped and distributed network applied to superconducting thin-film broadband impedance transforming,” IEEE Trans. Appl. Supercond., vol. 3, no. 4, pp. 3066–3074, Dec. 1993. [9] J.-W. Sheen, “A compact semi-lumped low-pass filter for harmonics and spurious suppression,” IEEE Microw. Guided Wave Lett., vol. 10, no. 3, pp. 92–93, Mar. 2000. [10] K. Kobayashi, Y. Nemoto, and R. Sato, “Kuroda’s identity for mixed lumped and distributed circuits and their application to nonuniform transmission lines,” IEEE Trans. Microw. Theory Techn., vol. MTT-29, no. 2, pp. 81–86, Feb. 1981. [11] A. Ghiasi and A. Gopinath, “Novel wide-bandwidth matching technique for laser diodes,” IEEE Trans. Microw. Theory Techn., vol. 38, no. 5, pp. 673–675, May 1990. [12] H. J. Carlin and O. P. Gupta, “Computer design of filters with lumpeddistributed elements or frequency variable terminations,” IEEE Trans. Microw. Theory Techn., vol. MTT-17, no. 8, pp. 598–604, Aug. 1969. [13] K. W. Iobst and K. A. Zaki, “An optimization technique for lumped-distributed two ports,” IEEE Trans. Microw. Theory Techn., vol. MTT-30, no. 12, pp. 2167–2171, Dec. 1982. [14] B. E. Carey-Smith, P. A. Warr, M. A. Beach, and T. Nesimoglu, “Wide tuning-range planar filters using lumped-distributed coupled resonators,” IEEE Trans. Microw. Theory Techn., vol. 53, no. 2, pp. 777–785, Feb. 2005. [15] T. Hirota, A. Minakawa, and M. Muraguchi, “Reduced-size branchline and rat-race hybrids for uniplanar MMIC’s,” IEEE Trans. Microw. Theory Techn., vol. 38, no. 3, pp. 270–275, Mar. 1990. [16] M. C. Scardelletti, G. E. Ponchak, and T. M. Weller, “Miniaturized wilkinson power dividers utilizing capacitive loading,” IEEE Microw. Wireless Compon. Lett., vol. 12, no. 1, pp. 6–8, Jan. 2002. [17] M. Abramowitz and I. A. Stegun, Handbook of Mathematical Functions with Formulas, Graphs, and Mathematical Tables. New York, NY, USA: Dover, 1972. [18] R. Zhang and L. Zhu, “Synthesis and design of wideband dual-band bandpass filters with controllable in-band ripple factor and dual-band isolation,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 5, pp. 1820–1828, May 2013. [19] R. Zhang and L. Zhu, “Synthesis of dual-wideband bandpass filters with source-load coupling network,” IEEE Trans. Microw. Theory Techn., vol. 62, no. 3, pp. 441–449, Mar. 2014. [20] J.-S Hong and M. J. Lancaster, Microstrip Filters for RF/Microwave Applications. New York, NY, USA: Wiley, 2001. [21] A. Hardock, H.-D. Bruns, and C. Schuster, “Chebyshev filter design using vias as quasi-transmission lines in printed circuit boards,” IEEE Trans. Microw. Theory Techn., vol. 63, no. 3, pp. 976–985, Mar. 2015.

Runqi Zhang (S’11–M’15) received the B. Eng. and M. Eng. degrees in the electromagnetic field and radio technology from the University of Electronic Science and Technology of China (UESTC), Chengdu, China, in 2007 and 2010, respectively, and the Ph.D. degree from the School of Electrical and Electronic Engineering, Nanyang Technological University (NTU), Singapore, in 2015. From 2014 to 2015, he was a Research Associate with the Centre for Infocomm Technology, NTU. Since 2015, he has been a Research Engineer and now a Research Fellow with the Satellite and Airborne Radar Systems Laboratory, National University of Singapore (NUS), Singapore. His research interests include the satellite communication, synthesis and design of RF/microwave passive devices and low-temperature co-fired ceramic (LTCC) application in RF/microwave circuits.

Sha Luo (S’06–M’11) received the B.Eng. and Ph.D. degrees from the School of Electrical and Electronic engineering, Nanyang Technological University, Singapore, in 2006 and 2011, respectively. From 2006 to 2007, he was a Research Engineer with the Satellite Research Center, Singapore. Since August 2011, he has been a Lecturer with the School of Electrical and Computer Engineering, National University of Singapore. Her research interests include microwave and millimeter-wave circuits and satellite technologies.

Lei Zhu (S’91–M’93–SM’00–F’12) received the B.Eng. and M.Eng. degrees in radio engineering from the Nanjing Institute of Technology (now Southeast University), Nanjing, China, in 1985 and 1988, respectively, and the Ph.D. degree in electronic engineering from the University of Electro-Communications, Tokyo, Japan, in 1993. From 1993 to 1996, he was a Research Engineer with Matsushita-Kotobuki Electronics Industries Ltd., Tokyo, Japan. From 1996 to 2000, he was a Research Fellow with the École Polytechnique de Montréal, Montréal, QC, Canada. From 2000 to 2013, he was an Associate Professor with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore. Since August 2013, he has been a Full Professor with the Faculty of Science and Technology, University of Macau, Macau SAR, China. Since September 2014, he has been the Head of the Department of Electrical and Computer Engineering, University of Macau. He has authored or coauthored more than 290 papers in international journals and conference proceedings. His papers have been cited more than 3580 times with an H-index of 33 (source: ISI Web of Science). His research interests include microwave circuits, guided-wave periodic structures, antennas, and computational electromagnetic techniques. Dr. Zhu was the Associate Editors for the IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES (2010–2013) and IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS (2006–2012). He served as a General Chair of the 2008 IEEE Microwave Theory and Techniques Society (IEEE MTT-S) International Microwave Workshop Series on the Art of Miniaturizing RF and Microwave Passive Components, Chengdu, China, and as a Technical Program Committee Co-Chair of the 2009 Asia–Pacific Microwave Conference, Singapore. He served as a Member of the IEEE MTT-S Fellow Evaluation Committee (2013–2015) and has been a Member of the IEEE Antennas and Propagation Society (IEEE AP-S) Fellows Committee (2015–present). He was the recipient of the 1997 Asia–Pacific Microwave Prize Award, the 1996 Silver Award of Excellent Invention from Matsushita–Kotobuki Electronics Industries Ltd., and the 1993 First-Order Achievement Award in Science and Technology from the National Education Committee, China.

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Symmetrical Doherty Power Amplifier With Extended Efficiency Range Mustafa Özen, Member, IEEE, Kristoffer Andersson, and Christian Fager, Senior Member, IEEE

Abstract—A symmetrical Doherty power amplifier (PA) with an extended efficiency range is proposed. This paper proves the existence of a class of symmetrical Doherty PAs having efficiency peaks for back-off levels larger than 6 dB. A design technique is developed that maintains the full voltage and current swings of both the main and auxiliary transistors. The concept is experimentally verified in a 1.95-GHz 25-W circuit demonstrator fabricated using identical GaN HEMT devices. An average power-added efficiency of 50% and adjacent power leakage ratio of 49 dBc is obtained with 9-dB peak-to-average power-ratio 20-MHz long-term evolution test signals. Index Terms—Combiner synthesis, Doherty power amplifier (PA), efficiency.

I. INTRODUCTION

T

HE CLASSICAL Doherty power amplifier (PA) ideally consists of two identical class-B biased devices combined with a quarter-wave transformer [1]–[3]. Both inputs are controlled individually to achieve the required current profiles. Such configuration may provide the ideal peak efficiency (78.5%) of class-B PA at both the peak power level and at 6-dB output power back-off. However, modern communications standards often employ signals with peak-to-average-power-ratios (PAPRs) larger than 6 dB. The asymmetrical Doherty PA is a generalized version of the classical configuration where the second efficiency peak can be placed at any desired back-off level [4]. This level will be denoted with symbol through this paper. The asymmetrical Doherty PA uses the same load network topology as the classical configuration, but with different circuit element values. Further, for the asymmetrical Doherty, the ratio of auxiliary and main transistor device peripheries, , scales with the parameter [4] (1) for dB, corresponding to the classical For instance, Doherty configuration, and 2.98 for of 12 dB, meaning that Manuscript received August 13, 2015; revised December 22, 2015; accepted January 29, 2016. This research was carried out at the GigaHertz Centre under a joint project supported by the Swedish Governmental Agency for Innovation Systems (VINNOVA), Chalmers University of Technology, Ericsson, Gotmic, Infineon, National Instruments, Ampleon, and SAAB. M. Özen and C. Fager are with the Department of Microtechnology and Nanoscience, Chalmers University of Technology, SE-412 96 Göteborg, Sweden (e-mail: [email protected]; [email protected]). K. Andersson is with Ericsson Research AB, 417 56 Göteborg, Sweden (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2529601

the auxiliary transistor should have almost three times larger size (maximum current) compared to the main transistor. It is important to mention that derivation of the equation above assumes that both cells are class-B biased. The ideal Doherty theory used above assumes individual control of the main and auxiliary transistor branches. This independent control can be achieved in the digital domain, however, at the cost of needing two complete RF signal generation chains. Another approach, which is commonly used in practice, is to use an analog input signal splitter. In that case the main cell is biased for class-B operation while the auxiliary transistor is biased for class-C operation. By choosing an appropriate class-C bias point, the auxiliary cell can be made to shut off automatically at dB back-off. Such a single input Doherty is self-managing and therefore has a very simple configuration from the system point of view. It is thus a very suitable candidate for low/medium-power systems, such as small base stations, microwave links, and handset transmitters [5]. However, on the other hand, the class-C current waveform contains a smaller fundamental tone component compared to class-B mode. A larger input power is also required for class-C operation. It therefore provides significantly lower gain than class-B mode. Hence, the class C biased auxiliary cell has a strong influence on the overall gain in Doherty PAs [3]. In particular, for large values of , the class-C cell will be much larger than the main cell and its gain will dominate, severely degrading the power-added efficiency (PAE). As mentioned previously, the class-C current waveform contains less fundamental tone component than the class-B waveform, which was assumed when deriving the expression for in (1). The ratio between the auxiliary and main transistor peripheries will therefore become even higher than given by , thus further amplifying the problem. The use of a very large class-C cell also causes practical limitations on realization of the analog input signal splitter. For instance, the power division ratio of the splitter becomes 7 dB for of 9 dB [3]. In general, if the power division ratio of a splitter is very uneven, the resulting transmission lines become very thin and/or thick, putting a practical limitation on the realization of the splitter [6]. In some cases, even attenuators are used to achieve the right power division ratio, further degrading the PAE [7]. In addition to performance limitations, when considering designs using discrete transistors, two different transistors are required for the asymmetrical Doherty case. This directly increases the semiconductor manufacturing, device characterization, packaging, and assembly costs. Use of symmetrical

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devices is therefore also desired from an economical point of view. In recent years there has been an increased interest in realizing Doherty PAs with a large efficiency range using symmetrical devices since it enables reduced manufacturing costs in high-power radio transmitters [8]–[10]. One of the techniques proposed is to use a lower drain supply for the main branch [9], [11]–[13]. The power delivered by the auxiliary cell is thereby relatively larger, which enables a larger efficiency range. However, this approach reduces the power utilization factor and also increases the complexity by requiring dual power supplies. In [8], it was proposed to reduce the power delivered to the main cell in a symmetrical Doherty to achieve the required current profiles for a large efficiency range. However, this approach also reduces the power utilization factor. In [14], the authors have shown that the efficiency range of the symmetrical Doherty PA can be improved by dynamically adjusting the amplitude and phase of the branch drive signals. However, the complexity is then increased significantly since two complete RF signal generation chains are required for individual control of main- and aux-branch input signals. Recently, the authors proposed a novel symmetrical Doherty PA in [15] where it was shown that high efficiency over large dynamic ranges also can be achieved using symmetrical devices, while still maintaining full voltage and current utilization of both transistor cells. This is achieved by modifying the combiner instead of reducing voltage/current of the main cell, thus still a high power utilization factor is maintained. In this paper, the theory behind the operation is presented. Furthermore, the design procedure of the proposed symmetrical Doherty PA is thoroughly explained. Based on the proposed technique, the design of a 2.14-GHz GaN PA is also presented and evaluated with realistic modulated signals. The state-of-the art results obtained further demonstrate its usefulness in future wireless applications. This paper is organized as follows. In Section II, the basic principles of the novel symmetrical Doherty PA are introduced. Section III describes the combiner network parameters that are derived from transistor load–pull data. Section IV covers the realization of the combiner network for the proposed PA. Idealized simulation results are presented and discussed in Section V. The design of the prototype PA is presented in Section VI. The experimental results are presented and evaluated in Section VII. Finally, conclusions are given in Section VIII. II. SYMMETRICAL DOHERTY PA In this section, the Doherty combiner network parameters will be derived assuming arbitrary and equally sized devices. First, the two-port combiner network parameters, , will be calculated assuming that the two-port is reciprocal and lossy, i.e., the load is included inside, see Fig. 1. It is then verified that the two-port combiner network parameters can be realized with a three-port lossless reciprocal network terminated with a purely resistive load, , see Fig. 2. The three-port lossless combiner is represented by two two-port lossless networks, as seen in the figure. Realization of the lossless two-port network parameters, and , will be treated later on in the following section.

Fig. 1. Schematic used for the derivation of the two-port combiner network paand denotes the fundamental tone impedances experienced by rameters. and denotes the transistors, where is the harmonic index. the fundamental tone component of the drain voltage and current waveforms.

Fig. 2. Lossless three-port combiner network terminated with a purely resistive load.

A. Assumptions and Boundary Conditions It will hereafter be assumed that the same drain bias is used for both cells, and that their voltage and current capabilities are fully utilized. It is further assumed that the phase offset between the main and auxiliary branches is rad. Note that assuming an arbitrary value for the phase offset creates an additional degree of freedom for the analysis. In previous similar Doherty PA analyses in the literature [16], [17], was typically assumed to be equal to rad. Finally, the following boundary conditions are used for the derivation. 1) Optimal load is presented to the class-B cell (main transistor) at the peak power level. 2) Optimal load is presented to the class-C cell (auxiliary transistor) at the peak power level. 3) Optimal load is presented to the class-B cell at a desired back-off level, e.g., at the PAPR of the signal. Optimal load implies that the available voltage swing, , is fully utilized. The boundary conditions and ensures that at the peak input drive level both devices see the optimal impedances and thus generate maximum output power. Since the and are lossless, the sum of the powers generated by the devices will be equal to the power delivered to the load. First, the network parameters are derived assuming ideal current sources as transistors. Later it is shown that the combiner network parameters can also be calculated using the waveforms of a realistic transistor, e.g., using the optimal fundamental tone voltage and current components obtained from load–pull simulations or measurements. The current flowing through the main device is defined as otherwise with and

(2)

being the normalized input signal, , , is the maximum current capability of the transistor.

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The current flowing through the class-C biased auxiliary device is defined as

3

are in-phase. Conditions #1 and #2 from the previous section therefore yield the following equalities: (10)

(3) otherwise

(11)

where . Note that conduction angle of the class-C cell at peak power then follows as (4) Observe that the auxiliary current phase lags the main current phase by rad and turns off when . The term will later be solved in terms of and also determines the gate bias of the class-C transistor, such that

The third condition relates to optimal matching of the class-B cell at dB back-off. This condition results in the following equality noting that is then equal to zero: (12) Now we have three equations and three unknowns to be solved. The solution set is given by

(5) is the maximum allowed gate voltage and is where the threshold voltage of the transistor. In order to calculate network parameters of the combiner, currents at the fundamental tone have to be known. The fundamental tone Fourier component of follows as

(13) where

(6) Similarly, the fundamental tone Fourier component of lows as

fol-

(7) As mentioned previously, the parameter depends on the design variable . In order to solve in terms of , the following equation is given from the fact that only the main cell is active when the output power is backed off by a factor of : (8) , , and where is the maximum available voltage swing of the transistor. Analytical solution of from (8) above is somewhat cumbersome. However, a numerical solution for a given can easily be found. Now all the necessary fundamental tone waveforms to calculate the network parameters are obtained. B. Derivation of Network Parameters Assuming Ideal Current Sources

Note that the phase offset between the branches is now a free parameter. However, in Section IV we will show that can only attain a limited set of values in order for the combiner to be realized as a lossless three-port. However, before that, is also derived in terms of the fundamental tone waveforms of a realistic transistor. III. DERIVATION OF COMBINER NETWORK PARAMETERS FROM LOAD–PULL DATA At microwave frequencies the device parasitics and nonlinearities affect the circuit operation significantly. A load–pullbased combiner design approach is therefore necessary to fully utilize the device capabilities. Considering that, using a similar approach to the above, the combiner -parameters may also be derived using the optimal fundamental tone voltage and current components from load–pull simulations together with the class-C cell off-state output impedance . At the peak power level, the fundamental tone voltages and currents are related as (14)

The fundamental tone device voltages and currents shown in Fig. 1 are related by the impedance parameter matrix , (9) Note that since the network is reciprocal. Ideally class-B and class-C should be terminated with purely real loads—thus the voltage and current components

(15) is the The subscript refers to the peak power level, e.g., fundamental tone of the auxiliary current at the peak power. When the auxiliary cell shuts off, the second port of the combiner will be terminated by the output impedance of the class-C cell, . This yields the following equality: (16)

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Similarly, the subscript refers to the back-off power level, e.g., is the fundamental tone of the main current at the back-off power level. Using the three equations above, the combiner network parameters are found as (17), shown at the bottom of this page, where

The optimal output impedances and output power typically obtained in load–pull characterization can easily be converted to the voltages and currents needed in (17) by the following relationships:

Fig. 3. Phase-offset value between the main and auxiliary branch waveforms, , versus the back-off efficiency peak level, .

(18) (19) It should also be stressed that, in a realistic transistor case, the phase delays of the main and auxiliary cells might be different due to different biasing and different matching networks used. The length of the input phase shifter should be adjusted in a way to compensate for these effects and to ensure that the desired phase offset of is achieved between the output waveforms. Finally, it is also worth mentioning that analysis presented in this section has been further extended to outphasing PA combiner design in [18].

numerically using (17) and (20). Once the value of is known, is also fully known. In Fig. 3, is plotted versus . As seen from the figure, for dB as expected from the classical Doherty theory and it approaches zero with increasing . Our numerical evaluations suggest that a physical solution, i.e., a real root, is always found independent of . However, similar to the conventional asymmetrical Doherty case the efficiency drop between the two peaks will increase with increasing . Next, practical realization of with a lossless three-port combiner and a resistive load is treated. A. Realization of Lossless Combiner

IV. CONVERSION TO THREE-PORT In the previous sections, the network parameters of two-port lossy combiner seen in Fig. 1 are derived in terms of optimal load impedances and . It should also be verified that the calculated two-port network parameters can be realized with a threeport lossless reciprocal network terminated with a purely resistive load, , see Fig. 2. In Appendix, Section A, using the conditions for being a lossless reciprocal three-port network, it is shown that the following condition is necessary as well as sufficient for this transformation to be possible: (20) The condition given above is satisfied for four different values. Each solution ideally provides the same efficiency versus back-off profile, but yields different network parameters. For the ideal current source case, the solution set for has the form of and the value of depends on the selected . The roots are, however, not symmetrical for the realistic transistor case, as will be shown in Section VI. It is a difficult task to derive an analytical expression for in terms of . However, for a known , the value of is easily found

As mentioned previously, the three-port lossless combiner can be presented using two lossless two-ports, see Fig. 2, denoted as main and auxiliary networks. The network parameters of these lossless networks, and , should be derived in terms of the calculated and load resistance . The network parameters will be presented in -parameter format for the sake of convenience in this derivation. The lossy two-port combiner network parameters and the main and auxiliary network parameters will still be denoted with subscripts , , and , respectively. It is further assumed that the calculated lossy two-port network parameters have the following form: (21) According to the schematics in Figs. 1 and 2,

(22)

(17)

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Fig. 4. - and T-network realization of a two-port network. Each element represent a reactive component, i.e., a capacitor or an inductor.

where and are network parameters of the main and auxiliary two-port networks seen in Fig. 2. Observe that purely real values are assigned to the diagonal elements, while purely imaginary values are assigned to the off-diagonal elements for and . This structure is due to the fact that the main and auxiliary networks are assumed to be lossless and reciprocal. The matrix equality above and the fact that the two-ports are reciprocal yields seven equations in total, while there are eight unknowns in total. This means the system is over-determined. One of the unknowns can therefore be selected freely. In this case, is chosen as the free design variable. The solution set then follows as

(23) (24) (25) (26) (27) (28) (29) With the equations above, a full description of the lossless main and auxiliary two-port networks are obtained. Note from (25) that there are two sets of solutions for the network parameters. A lumped-element realization of a two-port network is straightforward using - or T-networks, see Fig. 4. Admittance/reactance values seen in the schematics are easily calculated using well-known formulas found in textbooks [19]. As one can independently select a - or T-network realization for main and auxiliary networks, four different realizations are possible for a given solution. Considering that there are also two solutions sets for the network parameters, in total eight different realization of the combiner exist. The realization that gives the best compromise in terms of losses and size should be selected. Moreover, the value of should also be determined for the realization. In principle, should also be optimized to achieve lowest losses in the combiner. Our experience with various designs is that around unity typically yields the lowest losses. This makes sense since reduces the

5

Fig. 5. Example of synthesized combiner for a symmetrical Doherty PA with dB.

number of elements from two to three in both - and T-network realizations of the main network. At microwave frequencies, distributed transmission-line realizations are often preferred over lumped-element ones. In the schematics seen in Fig. 4, the shunt components are easily realized using open- or short-circuited transmission-line stubs. In Appendix, Section B, a methodology is further provided on how to exactly realize a series reactance using only transmission lines. Below, following the approach above, an idealized extended efficiency range symmetrical Doherty PA is designed to illustrate the complete design procedure. Ideal current sources and ideal passive components are used for the design to be able to assess the intrinsic performance of the novel Doherty PA presented. V. VERIFICATION OF EXTENDED EFFICIENCY RANGE SYMMETRICAL DOHERTY PA A. Ideal Design Example For the design, the first step is to calculate two-port combiner network parameters from (13). Assuming that dB, V, and A, is calculated as (30) Using (30) and (20), the roots of are found as 41 139 . Obviously a lower phase shift is desired for a smaller circuit size and lower losses. This immediately reduces the number of options from four to two. For the ideal current source case, selecting the positive root or negative root, i.e., 41 41 , does not effect the efficiency performance. However, this matters for the realistic transistor case and the issue will be discussed further in the next section. In this particular example we preferred the root . The next step is to calculate the lossless two-port network parameters of main and auxiliary networks seen in Fig. 2 using (23)–(29). Once the network parameters of main and auxiliary networks are known, a lumped-element combiner can be realized using - or T-networks. In this example, the T-network topology is used both for main and auxiliary network realization since it gives lower losses and yield a more compact realization. It should also be mentioned that the positive root is used for in (25). The resulting lumped-element realization is shown in Fig. 5. This network is easily converted to transmission-line networks using the conversion technique presented in Appendix, Section B, see Fig. 6.

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Fig. 6. Transmission-line equivalent of the combiner shown in Fig. 5.

Fig. 8. Gain of the novel symmetrical and the conventional asymmetrical DodB. herty PAs for

Fig. 7. Ideal efficiencies of the proposed symmetrical and conventional asymdB. metrical Doherty PAs with

The simulated efficiency results using ideal current sources and the synthesized load network is shown in Fig. 7. Harmonic currents are terminated with short circuits in the simulations using ideal filters. Incorporation of the harmonic tuning circuitry into the combiner is, however, treated in the prototype demonstrator section that follows. As expected from the theoretical derivations, efficiency peaks are achieved at peak power and 9-dB back-off level, thereby fully confirming the theory. For the conventional asymmetrical Doherty PA, the drain efficiency of the class-C auxiliary cell 78.5 dominates at high power levels since the auxiliary cell is much larger. The theoretical overall drain efficiency of the conventional asymmetrical topology is therefore higher than the proposed symmetrical Doherty PA at high power levels, as seen in the figure. The achieved power utilization factor is equal to 0.120 for this particular solution, i.e., dB. The asymmetrical Doherty PA [3] would provide power utilization of 0.113 for the same . In Fig. 8, simulated gain results of the proposed symmetrical and conventional asymmetrical PAs are shown. In this simulations, the gate of the transistor is modeled with an network where the drain side is kept as an ideal voltage-controlled current source to compare the intrinsic performances. A gain of 16 dB is assumed for class-A operation in the simulations from the transistor data sheet (Cree CGH60015D). As seen from the figure, the novel proposed solution provides a significantly higher gain than the conventional asymmetrical Doherty PA solution. The improvement is due to fact that a smaller class-C is used in the symmetrical Doherty and therefore the overall Doherty gain is less effected by the inherent low gain of the class-C operation. The gain of the proposed symmetrical Doherty PA compresses as the output power increases, as seen from the graphs. In practice, gain saturation is a typical behavior for any

Fig. 9. Load impedance trajectories experienced by main and auxiliary transisdB for all four roots of . The output tors versus output power assuming power changes from the peak power level to zero output.

Fig. 10. Auxiliary transistor voltage magnitude at the turn-off moment for the proposed symmetrical and the conventional asymmetrical Doherty PAs, normalized with the drain supply.

kind of PA. It is therefore not obvious if the inherent gain compression behavior of the concept is an important limitation for the linearity. It will further be experimentally verified that the proposed Doherty PA can be linearized using low-complexity digital pre-distortion (DPD) algorithms. In Fig. 9, load trajectories presented to the devices are shown for all roots of . As seen from the figure, the main cell transistor experiences a purely real impedance trajectory. On the other

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7

TABLE I LOAD–PULL SIMULATION DATA

hand, complex impedance trajectories are presented to the auxiliary cell. This does, however, not cause any significant drop between the two efficiency peaks as seen from Fig. 7. In Section V-B, we will briefly discuss how the output losses at back-off in the symmetrical Doherty and the conventional asymmetrical solutions compare. B. Transistor Losses at Back-Off

2.14 GHz

2% and 0.8% of the total dc power consumption, respectively, for dB. Thus far, the theory of the novel extended efficiency range Doherty PA is presented and verified with idealized simulations. In Section VI, a prototype is also designed for experimental verification. VI. PROTOTYPE DEMONSTRATOR DESIGN

Although the proposed symmetrical and the conventional asymmetrical Doherty PAs theoretically provide the same drain efficiency at dB back-off, in practice the performance might differ due to differences in transistor losses. A drawback of the proposed solution is that the main cell is backed-off more compared to the conventional solution. This is obviously a penalty for the back-off drain efficiency. However, it is not a significant limitation for the final performance as it will be demonstrated in the prototype design section (Section VI). In a Doherty PA, even if the output impedance of the auxiliary cell is open circuited, there will still be voltage across the auxiliary transistor output capacitance that will cause losses. The amount of power lost in the auxiliary transistor at the turned-off state should be compared for the conventional and proposed solutions. For this analysis, it is assumed that the output capacitance and the parasitic resistance scales ideally, i.e., the output capacitance -factor is constant. The voltage across the auxiliary transistor is given by (31) When the class-C is turned off, we know that thus,

AT

A 2.14-GHz 25-W symmetrical Doherty PA, optimized for 8–10-dB PAPR signals, is realized using two 15-W bare-die GaN HEMTs (Cree CGH60015D) based on the design approach presented. For the design, first the optimal fundamental and second harmonic load impedances are found at the peak power level and back-off through load–pull simulations. It was observed that, fortunately, the optimal second harmonic impedance at the peak power level and back-off levels are quite similar and is around . Optimal fundamental tone impedances and corresponding efficiency numbers are presented in Table I. Using the fundamental tone drain waveforms, (17) and (20), roots of are found as 50 153 . Although each solution provides the same efficiency for the ideal current case, it is different for the realistic transistor case. Note also that the roots are not symmetrical for the realistic transistor case. It has been observed that the solutions exhibit significant efficiency drop between the efficiency peaks compared to the other two roots. The root is therefore selected for the best efficiency. The corresponding follows as

,

(34)

(32)

The combiner should present the above network parameters at the second harat the fundamental tone and present monic frequency at the drain terminals. The harmonic control circuitry is implemented using an open-circuited stub that has a length of at and a transmission line to transform short-circuit impedance to . By this topology, it is ensured that what is after the stub will not effect the second harmonic impedance seen at the device terminals. The effect of harmonic tuning circuity can be de-embedded from the calculated combiner network parameters using the matrix representations

Normalized auxiliary cell drain voltage at the turn-off moments is plotted versus in Fig. 10. It is easy to show that the output losses in the proposed symmetrical and asymmetrical Doherty PA are related by (33) In practical designs, as will also be shown in Section VI, the power that is consumed in the auxiliary transistor in the off-state is, however, not very significant both for the conventional asymmetrical and the proposed symmetrical Doherty PAs. For a Cree CGH60015D device, the power loss in the case of the conventional and the proposed solutions corresponds to approximately

(35) represents the network parameters of the where harmonic control circuitry at the fundamental frequency, see

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' T2P

THC P1

E1=36o Z1=43 Ω E2=45o Z2=29 Ω

o

E4=11 Z4=28 Ω E3=90o Z3=28 Ω C1

Harmonic control circuitry

VDD

THC o

E6=33 Z6=28 Ω E5=71o Z5=53 Ω

E8=36o Z8=46 Ω P2 E7=45o Z7=29 Ω

C2

50 Ω

Fig. 11. Combiner realized using load–pull waveform data. Capacitors are 8.2 pF.

and

Fig. 11. Now our task is to realize using the approach presented in the previous section. For the realization, T-networks are used for both main and auxiliary networks. It should also be mentioned that the positive root is selected in (25). The lumped-element main and auxiliary networks are then converted to transmission-line networks using the approach presented in Appendix, Section B. The resulting final combiner is shown in Fig. 11. Furthermore, in Fig. 12, the design recipe presented in this work is summarized using a flowchart. The input network used is similar to conventional input networks used for Doherty PAs. Double-stub impedance-matching networks are used for matching of the main and auxiliary inputs. A 50- transmission line is used as a phase shifter at the input of the main cell. The length of the transmission line is adjusted such that the output waveforms of the main cell is phase-delayed 50 compared to the auxiliary waveforms. An equal power split branch-line coupler is used as the power divider. The efficiency and gain simulation results using a transistor model provided by the vendor are shown in Figs. 13 and 14. Comparison of these final simulated efficiency results with the load–pull data shown in Table I clearly prove that the combiner design approach enables the highest possible efficiency and output power from the device both at peak power and at back-off power levels. As mentioned previously, the power lost in the class-C transistor when it is turned off corresponds to 2% of the dc power, which is not very significant. The gain compression is around 3 dB, which is similar to the amount of compression for the ideal current source case. However, the gain is nonmonotonic for the realistic transistor case. It was observed that the input impedance of the class-C cell varies significantly with output power. This is due to facts that a large voltage swing is applied across the nonlinear input capacitance and the load impedance varies versus the input power level. It was also observed that the shape of the gain curve strongly depends on the class-C biasing. This could indicate that the nonideal class-C operation is the major cause for the nonmonotonic gain response. Simulated small-signal gain versus frequency is plotted in Fig. 15. The PA presents a fairly flat gain response from 1.85–2.5 GHz and the gain is above 10 dB.

Fig. 12. Design procedure for realization of a Doherty PA based on the derivations in this work.

Fig. 13. Simulated efficiency results of the prototype symmetrical Doherty PA at 2.14 GHz. Drain bias is 28 V. Main and auxiliary gate biases are 3.1 and 8 V, respectively.

VII. EXPERIMENTAL RESULTS The combiner network shown in Fig. 11 is implemented on a Duroid 5870 substrate that has a relative dielectric constant of 2.3 and thickness of 15 mil. Electromagnetic simulations of the transmission lines and the bond wires were also performed using Keysight’s Momentum and finite-element method (FEM) simulators, respectively, to guarantee good agreement between measurements and simulations.

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Fig. 14. Simulated gain of the prototype symmetrical Doherty PA at 2.14 GHz. Drain bias is 28 V. Main and auxiliary gate biases are 3.1 and 8 V, respectively.

Fig. 17. Measured PAE and drain efficiency versus output power at 1.95 GHz. Drain bias is 28 V. Main and auxiliary gate biases are 3.1 and 7 V, respectively.

Fig. 15. Small-signal gain simulation results of the prototype symmetrical Doherty PA versus frequency. Drain bias is 28 V. Main and auxiliary gate biases are 3.1 and 8 V, respectively.

Fig. 18. Measured gain versus output power at 1.95 GHz. Drain bias is 28 V. Main and auxiliary gate biases are 3.1 and 7 V, respectively.

Fig. 16. Photograph of the fabricated extended efficiency range symmetrical Doherty PA prototype. The dimensions are 10 cm 9.5 cm.

Finally, the manufactured driver boards, the GaN HEMT dies, and the combiner network are mounted on a brass fixture. A photograph of the prototype PA is shown in Fig. 16. Although the PA was designed at 2.14 GHz, the best back-off efficiency was achieved at 1.95 GHz. It is suspected that the inaccuracy of the model for class-C operation caused this frequency shift. In simulations, a gate bias of V was used for the auxiliary cell. In measurements, it is found that the gate bias should be raised to V to achieve a

better agreement with the simulations. This could indicate that the model is not as accurate for class-C operation compared to the class-AB case, which is more commonly used. It is worth mentioning that similar observations were also made in [9] and [20]. Recently, we have also performed load–pull measurements on another 6-W GaN device (Cree CGHV1F006S0) [21]. We observed a significant discrepancy between the simulated and measured class-C input impedance. Although for a different device this indicates that the modeling of the input impedance may be inaccurate in the class-C bias point. Assuming a similar behavior for the Cree CGH60015D transistor can to a large extent explain the discrepancy observed here. Measured efficiency and gain results versus back-off at 1.95 GHz are presented in Figs. 17 and 18. As seen from the figures, a very distinct Doherty PA efficiency profile is achieved for a large dynamic range. The PAE remains above 50% for more than 9 dB of the output power dynamic range. This result experimentally prove that high efficiency over large dynamic ranges (6 dB) can also be achieved using symmetrical devices in Doherty PAs. In Figs. 19 and 20, the measured efficiency results are presented versus frequency for different output power back-off levels. The PA exhibits drain efficiency of higher than 47% and PAE of higher than 40% across 1.9–2.2 GHz at 9-dB back-off. The measured gain and output power results versus frequency are presented in Fig. 21. The output power and the saturated gain is above 43.8 dBm and 7.3 dB, respectively, across the 1.9–2.3-GHz frequency band.

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Fig. 19. Measured drain efficiency versus frequency at different output power levels relative to maximum output power. Fig. 22. Normalized power spectral density before and after DPD correction. DPD operates at a sampling rate of 100 MSa/s.

the pre-distorted signal was larger than the maximum sampling rate of the DACs used, 100 MS/s [23]. The modulated measurement results are summarized and compared with state-of-the-art Doherty PAs in Table II. As seen from the table, the efficiency and linearity performance of the proposed PA stand out. In the table, results from the authors’ previous conference paper [15] is also included, which describes design of a 3.5-GHz extended efficiency-range Doherty PA developed using the theory presented in this paper. Fig. 20. Measured PAE versus frequency at different output power levels relative to maximum output power.

VIII. CONCLUSIONS

Fig. 21. Measured peak output power level and small-signal gain versus frequency.

A novel symmetrical Doherty PA has been developed that can provide high efficiency over large dynamic ranges 6 dB . The use of smaller class-C cells compared to asymmetrical Doherty PAs brings the advantages of higher gain and improved PAE performance. Furthermore, using identical devices in both branches yields a more even power split ratio at the input. This simplifies the design of the input splitter. The proposed symmetrical Doherty PA also provides a better power utilization factor than the conventional asymmetrical Doherty PA. These distinct advantages together with the proposed load–pull-based design procedure enabled a symmetrical Doherty PA with an excellent efficiency performance, which opens for its use in various applications where high efficiency and low manufacturing costs are demanded. APPENDIX

The PA prototype has also been evaluated with a 9-dB PAPR 20-MHz LTE signal scenario together with a low complexity DPD linearization algorithm [22]. The behavioral model used for the DPD is a 16-region vector-switched generalized memory polynomial model with a nonlinear order of , memory depth of , and cross-term memory length of . The PA provides PAE of 50.2% and adjacent channel leakage ratio (ACLR) of 24.4 dB at an average output power of 35.21 dBm. After applying DPD, the measurements resulted in a PAE of 50% and ACLR of 49 dB at an average output power of 35.16 dBm. Measured gain before and after DPD are 10.2 and 10.1 dB, respectively. As seen from the output spectrum in Fig. 22, there is a significant spectral regrowth at the alternate channel. This was due to fact that the bandwidth of

A. Condition for the Three-Port Conversion In Section II, the two-port combiner network parameters are derived in terms of the phase offset at peak power level , assuming that the two-port is lossy and reciprocal. It is desired to realize the two-port network parameters with a lossless reciprocal three-port network terminated with a resistive load, . Depending on , only certain values allow such a realization as it will be proven in this section. The three-port network parameters are denoted with lower case letters, , and the two-port network parameters are denoted with capital letters, . It is assumed that the -parameters of the three-port network are

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TABLE II COMPARISON WITH RECENT GaN DOHERTY PAs

(36) Since the three-port network is assumed to be reciprocal, , , and . Terminating the third port with a resistive load will result in a two-port network. The -parameters of this two-port network in terms of the three-port network parameters are given by (37) (38) (39) are purely imaginary since it is assumed that The elements the three-port network is lossless. The real parts of the two-port network parameters are thus given by (40) (41) (42)

Fig. 23. Realization of a two-port serial reactive element with a transmission line and two shunt reactive elements. Parameter represents the susceptance and are the characteristic impedance and electrical of the shunt elements. length of the transmission line, respectively.

B. Serial Reactance Realization Using Transmission Line Networks A serial connected reactive element can be realized using a transmission line and two shunt reactive elements, as illustrated in Fig. 23. The shunt elements, denoted with , can be implemented using short- or open-circuited transmission-line stubs. The circuit element values, , are derived by equating the network parameters of the two two-port networks seen in Fig. 23. Although this transformation may seem somewhat familiar, the authors have not noticed a similar derivation in the recent literature, nor in the standard microwave text books. There are two set of solutions for the element values,

where

(45) (43) (46)

The equalities (40)–(42) show that the following conditions is necessary as well as sufficient for realization of the calculated two-port network parameters with a three-port lossless reciprocal network terminated with a resistive load (44) The condition given in (44) is satisfied for four different values. For the ideal current source case, the solution set for has the form of and the value of depends on the value. It is a difficult task to derive an analytical expression for in terms of . However, for a known , the value of is easily found numerically.

where is in the same quadrant as the point second solution set follows as

. The

(47) (48) . It is worth where is in the same quadrant as the point mentioning that the second solution typically yields a smaller value and, therefore, is more preferable for typical applications.

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ACKNOWLEDGMENT The authors acknowledge Modelithics Inc., for providing models under their University License Program. R. Abdoelgafoer, R. Jos, and J. Gajadharsing, all with AMPLEON, are acknowledged for fruitful discussions and their assistance in characterization of the 3.5-GHz prototype.

REFERENCES [1] W. Doherty, “A new high efficiency power amplifier for modulated waves,” Proc. IRE, vol. 24, no. 9, pp. 1163–82, Sep. 1935. [2] F. H. Raab, “Efficiency of Doherty RF power-amplifier systems,” IEEE Trans. Broadcast., vol. BC-33, no. 3, pp. 77–83, Sep. 1987. [3] J. Mietzner et al., “The AB-C Doherty power amplifier. Part I: Theory,” Int. J. RF Microw. Comput.-Aided Eng., vol. 19, no. 3, pp. 293–306, Nov. 2009. [4] M. Iwamoto et al., “An extended Doherty amplifier with high efficiency over a wide power range,” IEEE Trans. Microw. Theory Techn., vol. 49, no. 12, pp. 2472–79, Dec. 2001. [5] V. Camarchia et al., “The Doherty power amplifier: Review of recent solutions and trends,” IEEE Trans. Microw. Theory Techn., vol. 63, no. 2, pp. 559–571, Feb. 2015. [6] R. E. Collin, Foundations for Microwave Engineering, 2nd ed. Piscatway, NJ, USA: IEEE Press, 2000. [7] J. Kim et al., “Optimum operation of asymmetrical-cells-based linear Doherty power amplifiers—Uneven power drive and power matching,” IEEE Trans. Microw. Theory Techn., vol. 53, no. 5, pp. 1802–09, May 2005. [8] Y.-S. Lee, M.-W. Lee, and Y.-H. Jeong, “Advanced design of an extended GaN HEMT Doherty amplifier using uneven saturation power for WiMAX applications,” in IEEE Radio Wireless Symp., 2009, pp. 268–271. [9] T. Yamamoto, T. Kitahara, and S. Hiura, “50% drain efficiency Doherty amplifier with optimized power range for W-CDMA signal,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2007, pp. 1263–66. [10] X. Fang and K.-K. Cheng, “Extension of high-efficiency range of Doherty amplifier by using complex combining load,” IEEE Trans. Microw. Theory Techn., vol. 62, no. 9, pp. 2038–47, Sep. 2014. [11] D. Gustafsson, C. Andersson, and C. Fager, “A modified Doherty power amplifier with extended bandwidth and reconfigurable efficiency,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 1, pp. 533–542, Jan. 2013. [12] D. Gustafsson et al., “A GaN MMIC modified Doherty PA with large bandwidth and reconfigurable efficiency,” IEEE Trans. Microw. Theory Techn., vol. 62, no. 12, pp. 3006–16, Dec. 2014. [13] J. Pang et al., “Design of a post-matching asymmetric Doherty power amplifier for broadband applications,” IEEE Microw. Wireless Compon. Lett., vol. 26, no. 1, pp. 52–54, Jan. 2016. [14] R. Darraji and F. M. Ghannouchi, “Digital Doherty amplifier with enhanced efficiency and extended range,” IEEE Trans. Microw. Theory Techn., vol. 59, no. 11, pp. 2898–2909, Nov. 2011. [15] M. Özen and C. Fager, “Symmetrical Doherty amplifier with high efficiency over large output power dynamic range,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2014, pp. 1–4. [16] W. Neo et al., “A mixed-signal approach towards linear and efficient -way Doherty amplifiers,” IEEE Trans. Microw. Theory Techn., vol. 55, no. 5, pp. 866–879, May 2007. [17] S. C. Cripps, Advanced Techniques in RF Power Amplifier Design. Norwood, MA, USA: Artech House, 2002. [18] M. Pampin-Gonzalez et al., “Outphasing combiner synthesis from transistor load pull data,” in IEEE MTT-S Int. Microw. Symp. Dig., May 2015, pp. 1–4. [19] D. M. Pozar, Microwave Engineering. New York, NY, USA: Wiley, 2012. [20] J. Rubio et al., “A 22W 65% efficiency GaN Doherty power amplifier at 3.5 GHz for WiMAX applications,” in Integr. Nonlinear Microw. Millim.-Wave Circuits Workshop, Apr. 2011, pp. 1–4. [21] A. Sandström, “Design and realization of a 6 GHz Doherty power amplifier from load–pull measurement data,” M.S. thesis, Dept. Microtech. Nanosci., Chalmers Univ. Technol., Göteborg, Sweden, 2015.

[22] S. Afsardoost, T. Eriksson, and C. Fager, “Digital predistortion using a vector-switched model,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 4, pp. 1166–74, Apr. 2012. [23] J. Cahuana et al., “Linearization of dual-input Doherty power amplifiers,” in Int. Integr. Nonlinear Microw. Millim.-Wave Circuits Workshop, 2014, pp. 1–3. [24] M. Pelk et al., “A high-efficiency 100-W GaN three-way Doherty amplifier for base-station applications,” IEEE Trans. Microw. Theory Techn., vol. 56, no. 7, pp. 1582–91, Jul. 2008. [25] J. Son et al., “A highly efficient asymmetric Doherty power amplifier with a new output combining circuit,” in IEEE Int. Microw., Commun., Antennas, Electron. Syst. Conf., Nov. 2011, pp. 1–4. [26] H. Deguchi et al., “A 2.6 GHz band 537 W peak power GaN HEMT asymmetric Doherty amplifier with 48% drain efficiency at 7 dB,” in IEEE MTT-S Int. Microw. Symp. Dig., 2012, pp. 1–3. [27] Y.-S. Lee, M.-W. Lee, and Y.-H. Jeong, “Unequal-cells-based GaN HEMT Doherty amplifier with an extended efficiency range,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 8, pp. 536–38, Aug. 2008. [28] J. Xia et al., “High-efficiency GaN Doherty power amplifier for 100-MHz LTE-Advanced application based on modified load modulation network,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 8, pp. 2911–21, Aug. 2013.

Mustafa Özen (GSM’10–M’15) received the Ph.D. degree from the Chalmers University of Technology, Göteborg, Sweden, in 2014. He is currently a Postdoctoral Research Fellow with the Microwave Electronics Laboratory, Department of Microtechnology and Nanoscience (MC2), Chalmers University of Technology. His research interests include design and analysis of high-efficiency transmitter architectures for wireless systems. Dr. Özen was the recipient of the 2011 Best Paper Award of the IEEE Wireless and Microwave Technology Conference.

Kristoffer Andersson received the M.Sc. degree and Ph.D. degree in electrical engineering from the Chalmers University of Technology, Göteborg, Sweden, in 2001 and 2006, respectively. Until 2013, he was an Assistant Professor with the Microwave Electronics Laboratory, Department of Microtechnology and Nanoscience (MC2), Chalmers University, during which time he was involved with the modeling and characterization of gallium–nitride high-frequency transistors. Since 2013, he has been a Senior Researcher with Ericsson Research AB, Göteborg, Sweden, where he is involved with gallium–nitride monolithic microwave integrated circuits (MMICs) and millimeter-wave 5G front-ends.

Christian Fager (S’98–M’03–SM’15) received the M.Sc. and Ph.D. degrees from the Chalmers University of Technology, Göteborg, Sweden, in 1998 and 2003, respectively. Since 2015, he has been a Professor with the Microwave Electronics Laboratory, Chalmers University of Technology. He has authored or coauthored more than 100 papers in international journals and conferences. His research interests include the design and modeling of linear and energy-efficient transmitters for future wireless systems. Dr. Fager was the recipient of the 2002 Best Student Paper Award of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) International Microwave Symposium (IMS). He is currently an Associate Editor for IEEE Microwave Magazine.

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A -Band 48-Gbit/s 64-QAM/QPSK Direct-Conversion I/Q Transceiver Chipset Sona Carpenter, Student Member, IEEE, Dhecha Nopchinda, Student Member, IEEE, Morteza Abbasi, Member, IEEE, Zhongxia Simon He, Member, IEEE, Mingquan Bao, Thomas Eriksson, Member, IEEE, and Herbert Zirath, Fellow, IEEE

Abstract—This paper presents design and characterization of single-chip 110–170-GHz ( -band) direct conversion in-phase/quadrature-phase (I/Q) transmitter (TX) and receiver (RX) monolithic microwave integrated circuits (MMICs), realized in a 250-nm indium phosphide (InP) double heterojunction bipolar transistor (DHBT) technology. The chipset is suitable for low-power ultrahigh-speed wireless communication and can be used in both homodyne and heterodyne architectures. The TX consists of an I/Q modulator, a frequency tripler, and a broadband three-stage power amplifier. It has single sideband (SSB) conversion gain of 25 dB and saturated output power of 9 dBm. The RX includes an I/Q demodulator with -band amplifier and 3 multiplier chain at the LO port. The RX provides a conversion gain of 26 dB and has noise figure of 9 dB. A 48-Gbit/s direct quadrature phase-shift keying (QPSK) data transmission using a 144-GHz millimeter-wave carrier signal is demonstrated with and energy efficiency of a bit error rate (BER) of 2.3 10 7.44 pJ/bit. An 18-Gbit/s 64-quadrature amplitude modulation (QAM) signal was transmitted in heterodyne mode with measured TX-to-RX error vector magnitude (EVM) of less than 6.8% and spectrum efficiency of 3.6 bit/s/Hz. The TX and RX have dc power consumption of 165 and 192 mW, respectively. The chip area of each TX and RX circuit is 1.3 0.9 mm . Index Terms—Bit error rate (BER), direct conversion, I/Q transceiver, millimeter-wave (mmW) integrated circuits, monolithic microwave integrated circuits (MMICs), mmW wireless communication, quadrature amplitude modulation (QAM), quaternary phaseshift keying (QPSK), wireless link.

F

I. INTRODUCTION

ROM the last few years, the increasing need for multigigabit data capacity not only for wired access networks but also for wireless environments has led to extension of carrier

Manuscript received August 10, 2015; revised January 15, 2016; accepted February 11, 2016. Date of publication March 14, 2016; date of current version April 01, 2016. This work was supported by VR “D0582301-Gigabits at Terahertz frequencies” and the Swedish Foundation for Strategic research (SSF) through the projects “RE07-0076- System on Chip solutions for future high speed communication” and “SE13-0020-Solutions for high datarate wireless communication.” S. Carpenter, D. Nopchinda, Z. S. He, T. Eriksson, and H. Zirath are with the Department of Microtechnology and Nanoscience, MC2, Chalmers University of Technology, 41296, Göteborg, Sweden (e-mail: [email protected]). M. Bao is with the Department of Microtechnology and Nanoscience, MC2, Chalmers University of Technology, 41296 Göteborg, Sweden, and also with Microwave System Radio Access Technologies, Ericsson AB, 41756 Göteborg, Sweden. M. Abbasi was with the Department of Microtechnology and Nanoscience, MC2, Chalmers University of Technology, 41296 Göteborg, Sweden. He is now with the Electrical and Computer Engineering Department, North Carolina State University, Raleigh, NC 27606 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2533491

frequency to millimeter and submillimeter waves [1]. This unoccupied bandwidth can be used for future 10–100-Gbit/s wireless short-range communication. Currently, the most focus is on 60-GHz wireless communication [2]–[5] with data rates up to 11 Gbit/s and -band for wireless backhaul in mobile communication [6]. The frequency band from 110 to 170 GHz ( -band) has a low atmospheric attenuation window between two high attenuation points at 118 GHz (resonance of O molecule) and at 183 GHz (resonance of H O molecule). This window from 120 to 160 GHz has attenuation below 1 dB/km, making it suitable for medium-distance backhaul gigabit communications [7]. Compared with the -band and lower frequencies, the antenna size can be significantly decreased (assuming the same beam width), with the smaller antenna size making -band links therefore more attractive for dense urban small cell areas. The 141–148.5-GHz frequency band is allocated by the Federal Communication Commission (FCC) for fixed and mobile communication [8]. Alternatively, gigabit-rate wired communication can be performed in the -band, using, for instance, dielectric waveguide as a transmission medium. Millimeter-wave (mmW) wireless link transmission distance is limited by atmospheric attenuation, transmitter (TX) output power, and receiver (RX) sensitivity. The typical noise figures of 8.5–14 dB in [9]–[14] were reported for RXs operating in the -band. The maximum transmitted power of 10.6 dBm in [14] at 150–168 GHz and 10.2 dBm in [11] at 144 GHz were reported for mmW TXs. A 13.5-dBm output power at 301 GHz for a power amplifier (PA) in 250-nm InP technology is published in [15]. In order to fulfill the increasing need for high-speed communication, various kinds of mmW wireless communications system demonstrators have been developed. Most of them use simple modulation schemes such as amplitude shift keying (ASK) [16], [17], on–off keying (OOK) [18], or binary phase-shift keying (BPSK). A BPSK of 40 Gbit/s at 240 GHz was reported in [19], and 12.5 Gbit/s at 220 GHz was demonstrated in [20]. The modulation format is simple and reliable, but the end result is low spectrum efficiency ( 1 bit/s/ Hz). The spectral efficiency can be increased by using more complicated modulation techniques, such as multilevel phase shift keying (PSK) or multilevel quadrature amplitude modulation (QAM). A quaternary PSK (QPSK) of 20 Gbit/s at 120 GHz in a laboratory environment with 1 b/s/Hz of spectrum efficiency is demonstrated in [21] and [22]. A 16-QAM 10-Gb/s at 140 GHz with 2.86-b/s/Hz spectral efficiency was demonstrated in [23]. A 256-QAM with 14 Mb/s is demonstrated by [24] at 220 GHz.

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Fig. 1. The fabricated chip photo and block diagram of direct conversion (a) I/Q TX and (b) I/Q RX. The chip area of each TR and RX is 1.3

This paper describes the design and implementation of a fully integrated ultra-wideband direct conversion in-phase/quadrature-phase (I/Q) TX and RX chipset for a high-data-rate wireless communication system. The chipset consists of a 3 LO frequency multiplier [25] integrated with an I/Q modulator [26] or I/Q demodulator [27], and a low-noise amplifier (LNA) or PA. This integration allows us to design the oscillator at one third of the fundamental -band LO frequency. The chosen design simplifies the packaging of the TX/RX chips and hence reduces the cost. A 110–170-GHz RF amplifier is used to improve noise figure of the RX chip and to increase the gain and transmitted power for the TX chip. In addition, we have demonstrated data transmission on-chipset with multiple modulation schemes, including QPSK and multiple-order QAM up to 48 Gb/s. The chipset can be used both in homodyne and heterodyne architectures. This paper is organized as follows. Section II describes the architecture of the TX/RX chipset with the description of each building block. Details of the measurement setup and results of the TX and RX chips are described in Section III. We have demonstrated a QAM transmission link and evaluated the spectral efficiency and error vector magnitude (EVM) in heterodyne mode in Section IV. Direct transmission experiment is reported in Section V. Finally, Section VI summarizes the results and compares them with other published works. II. FULL INTEGRATION OF TRANSMITTER CHIPSET IN THE -BAND

AND

RECEIVER

The TX and RX are designed in an InP-based double-heterojunction bipolar transistor (DHBT) technology with 250-nm emitter width at Teledyne Scientific Company. The process offers unity gain cutoff frequency ( ) of 350 GHz and power gain

0.9

.

) of 650 at a collector current density of cutoff frequency ( 8 mA m for a 4 m 0.25 m emitter transistor. This section presents a brief description of the circuits and their principle of operation. In both TX and RX, each individual circuit is initially designed for standalone operation and then tuned in the complete TX and RX circuit simulation to optimize the performance. The presented circuits are designed by using ADS from Keysight, and the electromagnetic performance of critical layout parts are simulated with Momentum. A. I/Q Transmitter The block diagram and simplified schematic diagram of the TX are shown in Figs. 1(a) and 2, respectively. It consists of an I/Q modulator, a 3 multiplier for the LO, and a three-stage PA as shown in Fig. 1(a). The modulator is presented in [26] with full details and consists of two double-balanced Gilbert cell mixers interconnected with a differential LO phase shifter. An external 36–560-GHz signal is used as the LO, and its frequency is multiplied by three by an on-chip frequency multiplier to cover the entire -band. The multiplier is similar to the one presented in [25] and consists of two stages. The first stage operates in class B to provide first and second harmonics of the signal to the second stage. The second stage is biased in class C and mixes the two harmonics to generate the third harmonic of the input signal. A bandpass Chebyshev filter is used at the output to remove all unwanted harmonics of the signal and provide the modulator with a clean sinusoidal at three times the input frequency. The RF amplifier is a three-stage common emitter design and buffers the modulator output from the external load. It provides 20-dB gain and saturated output power of 10 dBm. Amplifier design is of “lossy match” type, utilizing resistively loaded stubs at the input and output of each amplifier stage, to

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Fig. 2. Simplified schematic of direct conversion I/Q TX.

Fig. 3. Simplified schematic of direct conversion I/Q RX.

achieve a very wide bandwidth coverage. The output from the chip is a single-ended modulated signal, and inputs to the chip are a single-ended LO and differential I and Q signals which are dc coupled. The single-ended LO and RF signals are converted to differential by on-chip Marchand baluns. Bias voltages are shown in Fig. 2. The dc bias feed lines are properly RF decoupled to avoid unwanted feedback and combined to reduce the number of dc pads. The optimum operation condition is set by providing proper base currents to the amplifier and frequency multiplier, while the current of modulator is set by of the current mirror. Fig. 1(a) shows a photograph of the fabricated TX MMIC. The chip size is 1.3 0.9 mm .

The demodulator is presented in detail in [27]. The LO multiplier is identical to the transmitter, and the RF amplifier is also based on the same design as described above with dc bias optimized for minimizing the noise figure. The outputs from the chip are dc coupled differential I and Q signals and inputs are single-ended LO and RF signals which are converted to differential before the demodulator. The amplitude and phase balance of this conversion is critical for providing isolation between different ports of the receiver. Fig. 1(b) shows a photograph of the fabricated RX MMIC. The chip size is 1.3 0.9 mm .

B. I/Q Receiver

This section presents the characterization of I/Q transmitter and receiver chips as a single sideband (SSB) frequency up-converter and image reject frequency down-converter, respectively. The performance of the chipset is examined by data transmission experiments in Section IV for heterodyne mode and in Section V for homodyne mode.

The block diagram and simplified circuit diagram of the I/Q RX are shown in Figs. 1(b) and 3, respectively. As can be seen, many of the circuit blocks and footprints are reused from the transmitter chip.

III. MEASUREMENT OF THE TRANSMITTER AND RECEIVER

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Fig. 4. Simplified block diagram of measurement setup for characterization of the (a) TX MMIC and (b) RX MMIC.

A. Test Setup The chips are measured on a probe station with wafer probes. On the RF port, a GSG probe with 75- m pitch and WR6.5 waveguide interface and on the LO port, a 100- m GSG probe with V-type coaxial connector are used. For the differential baseband input/output signals, a quad GSSGSSG probe with 125- m pitch is used. In the direct conversion TX and RX mode, the four baseband signals are applied as differential I and Q baseband signals. In SSB and image reject frequency converter mode, however, they represent four phases of the IF signal. Additional 90 and 180 hybrids are used to connect these ports to the signal generator for testing the TX and a spectrum analyzer for testing the RX. Assuming that amplitude and phase balance of these hybrids are ideal, the measured sideband suppression and image rejection ratio are indicative of amplitude and phase balance of the transmitter and receiver chips. However, these external components and connecting cables are not ideal and contribute to the measured imbalance. Imperfections of the external hybrids are specified by the manufacturer to be 0.6 dB and 10 , respectively, from 1 to 18 GHz. This error is embedded in the presented results of the chipset. The TX output power is measured by using a -band harmonic mixer and a Rohde and Schwarz spectrum analyzer. To ensure linear operation of this mixer, an attenuator is connected at its input, and the combination is calibrated with a total power meter, in this case an Erikson calorimeter. For the receiver setup, the RF CW input signal is generated by an external 4 frequency multiplier driven by an E8257D HP signal generator. A variable attenuator is inserted after the multiplier in order to control the input power and to minimize possible VSWR mismatch at the port. For both the TX and RX setups, the LO is provided from an Agilent E8257D synthesizer. B. Transmitter Results The TX is characterized in single side band mode, and parameters like the conversion gain at upper and lower sidebands, LO power requirement, LO to RF isolation, output power compression and saturated output power is presented in this section. An input IF signal of 1 GHz with 28 dBm is applied to IF port. The LO input signal with 4-dBm power is varied from 36 to

Fig. 5. Transmitter measured and simulated conversion gain of upper and lower sidebands versus LO frequency at fixed 1-GHz input signal. The applied LO frequency to chip is one third of it.

56 GHz. The LO leakage and spectral components at two sidebands were measured at the RF port. The simulated and measured conversion gain for the upper and lower sidebands gains versus LO frequency are shown in Fig. 5. A conversion gain of 23 2 dB is achieved from 120 to 155 GHz. The unwanted sideband is suppressed by 18–25 dBc. As mentioned in the previous subsection, the sideband suppression is related to amplitude and phase mismatch by [28]

(1) where is amplitude and is phase imbalance. From (1), it follows that the measured 25 dB of sideband suppression at 1-GHz input signal is due to a maximum of 1.5 dB of amplitude imbalance or 10 of phase imbalance or a combination. The IF bandwidth is measured by varying input signal frequency from 1 to 18 GHz at a fixed LO of 48 GHz. The measured conversion gain variation is shown in Fig. 6. The transmitter is providing relatively flat gain up to 18 GHz at LSB where the gain drops by 4 dB. This is believed to be dominant due to the upper frequency limitation of the external hybrids and not the chip itself.

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Fig. 6. Transmitter measured and simulated conversion gain of upper and lower sidebands versus IF frequency at fixed 48-GHz LO.

To study the conversion gain dependency on LO power, a 1-GHz, 28-dBm CW signal is applied at the IF with LO power at 47 GHz swept from 0 to 7 dBm. The results are plotted in Fig. 7(a), showing a maximum gain of 26 dB at an LO power of 4 dBm or higher. The LO to RF isolation, defined as the measured power of the signal at LO frequency at the RF port divided by the applied LO power is shown in Fig. 7(b) for swept LO frequency and fixed IF of 1 GHz. The isolation is as high as 27 dB and remains better than 20 dB over a large part of the frequency band. Fig. 7(c) shows the output power and conversion gain at 153 GHz versus input power at 1 GHz. It can be seen from Fig. 8, that the maximum output power is 9 dBm from 125 to 138 GHz and drops to 5.5 dBm at 153 GHz. The TX chip consumes 165 mW of dc power. Table I summarizes the presented performance of the transmitter circuit. C. RX Results The SSB conversion gain of the receiver chip is measured at an input RF signal power of 30 dBm and the frequency is varied from 100 to 170 GHz. The LO signal is swept together with the RF signal frequency to maintain a fixed IF of 1 GHz. The input LO power is 4 dBm. At each RF frequency, the LO frequency is switched above and below the RF in order to measure conversion gain in both lower and upper sidebands. The measured and simulated results are shown in Fig. 9. As can be seen, the measured conversion gain varies from 20 to 25 dB between 115–155 GHz. The 5-dB RF bandwidth extends over 40 GHz. The ratio of the two output powers is defined as the image rejection ratio (IRR) and is 24 dB for most of the RF frequencies. Similar to sideband suppression in (1), the imbalance in the RX can be calculated leading to 0.7 dB of amplitude imbalance or 5 degrees of phase imbalance or a combination. These imbalance errors can increase the bit error rate of a communication system and depending on the system requirements, additional analog and digital methods may be applied for this systematic correction [29]. The measured and simulated conversion gain versus IF frequency is shown in Fig. 10 for a fixed LO frequency of 49 GHz.

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The measured 5-dB IF bandwidth of the RX is 18 GHz which is again believed to be limited by the external hybrid network. Fig. 11 shows the measured output power and conversion gain at 1 GHz versus input power at 140 GHz. The receiver can provide up to 4-dBm output power at 1-dB compression point. The maximum output power at 1 GHz versus RF frequency is shown in Fig. 12 and is as high as 4 dBm from 120 to 155 GHz. The sensitivity of the receiver is an important parameter affecting the maximum data rate for different modulation schemes. The simulated noise figure and gain of the complete receiver chip over RF frequency is shown in Fig. 13. It has 0.5 dB of noise figure variation from 9.1 to 9.6 dB between 115–170 GHz. The simulated noise figure versus IF frequency is shown in Fig. 14 for an LO frequency of 45 GHz. A noise figure of 9.5 dB was measured at 145 GHz RF and 1 GHz IF. The total dc power dissipation is 192 mW. Table II shows measured performance summary. IV. TRANSMISSION CHARACTERISTICS CONFIGURATION

IN

HETERODYNE

Here, we describe data transmission experiments in a heterodyne architecture using I/Q TX and I/Q RX as a SSB TX and IF RX, respectively. Digital signal processing of IF output signal is also demonstrated in this section. The data transmission test under homodyne configuration will be presented in the next section. A. Test Setup The TX and RX MMICs are probed “on wafer” using two probe stations, and a 1-m -band dielectric waveguide is used to feed the RF signal from TX to RX. The TX and RX share a common 53-GHz LO source through a power splitter, and the available power to the TX and RX is less than 1 dBm. As shown in Fig. 15, an Arbitrary Waveform Generator (Tektronix AWG70002A) is used to generate high order QAM signals centered at 5 GHz IF. The generated signal is fed to the SSB TX which up-converts the IF input signal to RF range around 164 GHz. A variable attenuator is inserted between the TX and RX in order to attenuate the RF signal to the RX preventing the RX to saturate. The RX down-converts the incoming RF signal to IF before sampling by a real-time oscilloscope (Tektronix MSO72504DX) with a fixed 100-GSamples/s sampling rate. A digital RX is implemented utilizing MATLAB code. B. QAM Signal Generation The diagram of the signal process flow for generating the QAM test signal is shown in Fig. 15. Using Tektronix's RFXpress software, a pseudorandom binary sequence (PRBS-9) was used as test pattern. The binary stream is differentially encoded before mapping to gray-coded QAM symbols, ( ). The QAM symbols are then oversampled times and pulse shaped with root-raised cosine filter (RRC) with roll-off factor of 0.7. The baseband signals are then digital up converted (DUC) to a 5-GHz IF by multiplication with discrete-time sinusoid carriers sequence as in (2)

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Fig. 7. Transmitter measured and simulated. (a) Conversion gain versus input LO power at LO frequency of 47 GHz and Input IF at 1 GHz. (b) LO to RF isolation over RF frequency for input at 1 GHz. (c) Output power and conversion gain at 153 GHz versus input power at 1 GHz.

Fig. 8. Measured and simulated saturated output power of the transmitter versus RF output frequency at an input frequency of 1 GHz.

TABLE I MEASURED PERFORMANCE SUMMARY OF TRANSMITTER Fig. 9. Receiver measured and simulated conversion gain of upper and lower sidebands over LO frequency at 1-GHz output of receiver. The applied LO to chip is one third of it.

where is the sample index. The up-converted signal fed to the AWG can be described as (3a) (3b) The AWG sampling rate is chosen to be with 10-b resolution.

24.296 GHz

C. RX-End's Signal Processing The block diagram of the digital process flow is depicted in Fig. 15. The input signal passes through an automatic-gain control block which regulates the amplitude level of the received signal. The sampled signal is low-pass filtered using Hamming-

Fig. 10. RX measured and simulated conversion gain of upper and lower sidebands over IF frequency at 49 GHz LO.

windowed linear FIR filter with 256 taps and a cutoff frequency of 20 GHz to suppress out-of-band noise. The filtered signal is then down-sampled to 20 GSamples/s.

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Fig. 14. RX simulated noise figure and conversion gain versus IF frequency at 45 GHz LO. Fig. 11. RX output power and conversion gain at 1 GHz versus input power at 140 GHz.

TABLE II MEASURED PERFORMANCE SUMMARY OF RECEIVER

equalize the recovered symbols before error-vector-magnitude (EVM) measurement. D. RX-End Implementation of Symbol Time, Carrier and Phase Recovery Fig. 12. RX saturated output power at 1 GHz IF over RF frequency.

Fig. 13. RX simulated noise figure and gain versus RF frequency at 2-GHz output.

Digital down conversion (DDC) is implemented by mixing the down-sampled signal with an internal LO controlled by the carrier and phase recovery block. The resulting I/Q baseband signal is filtered with a matching RRC filter. To recover the transmitted QAM symbols, a symbol time recovery (STR) block, described in Section IV-D, is used to find optimal sampling position of the I/Q baseband signal. Analysis of transmitted and received symbols are performed to obtain frequency-domain channel estimation. The estimated channel is used to control a 256-tap FIR equalizer used to

The process inside “Match Filter RRC” and “STR & down sample” blocks of the digital RX in Fig. 15 is depicted in Fig. 16. After DDC, the I/Q baseband signal is up-sampled using sincfunction interpolation to obtain a better representation of the received signal. This interpolation technique is particularly suitable since the transmitted signal is pulse-shaped by an RRC filter. The up sampled signal then goes through a matching RRC filter to obtain raised-cosine spectral response at the RX. The filtered discrete-time complex signal then goes through an autocorrelator to find the best sampling point. The received QAM symbols are then QPSK-partitioned [30] by selecting the symbols largest amplitude of constellation points. The partitioned symbols are then used for carrier recovery by removal of modulation through the Viterbi and Viterbi Fourth Power Estimator [31]. The unmodulated symbols can then be used to obtain phase information which is fed to the DDC’s LO. At the sinc-function interpolation block shown in Fig. 16, the oversampling rate affects the overall system performance. To reduce system complexity, the minimum up-sampling rate requirement is found to be 10 samples-per-symbol. This oversampling rate is justified by observing Fig. 17(a), where the EVM prior to equalization of 4 Gbaud 16 QAM is shown as a function of the sampling rate. It can be seen that the performance gain of increasing the sampling rate beyond ten samples-per-symbol, in contrast, deterioration can be observed for lower sampling rate ( ).

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Fig. 15. Illustration of the measurement set-up used to transmit QAM modulated data over the -band using TX/RX in heterodyne configuration. The block diagram of MATLAB implemented digital QAM demodulator based on data from a real-time oscilloscope is also shown.

in Table III along with the resulting constellation diagrams containing 39,200 symbols. After equalization, EVM of 10.83% for 16 QAM, 10.59% for 32 QAM, and 6.85% for 64 QAM were obtained. Fig. 17(b) shows EVM versus symbol rate for 16-, 32-, 64-QAM modulation formats. Fig. 16. Symbol time recovery mechanism.

Fig. 17. (a) EVM of unequalized 4-Gbaud 16-QAM versus Sinc interpolator's output sampling rate. (b) TX-to-RX EVM versus symbol rate for 16-, 32-, and 64-QAM modulation formats.

E. Test Result With the described implementation of the digital RX, a spectral representation of the signal can be obtained at any point along the process chain in Fig. 15. The power spectral density of the received 16-, 32-, and 64-QAM IF signal is shown

V. TRANSMISSION CHARACTERISTIC CONFIGURATION

IN

HOMODYNE

To validate the functionality and effectiveness of the presented TX/RX chipset in direct-modulation, zero-IF architecture, a transmit–receive wireless link was demonstrated in the lab. This demonstration also verifies the broadband performance of antenna in the -band for future real-time data transmission test. The data transmission through dielectric waveguide was presented in [32]. Illustration of the experimental setup is shown in Fig. 18. A signal quality analyzer (MP1800A) from Anritsu is used for PRBS generation as an input to the TX. An oscilloscope (Teledyne Lecroy 65Zi) is used to evaluate constellation, eye diagram, and BER at the output of RX, which were calculated from time-domain measurement by a built-in software of the oscilloscope. The TX and RX share a common 48-GHz LO source through a power splitter, and the available power to the TX and RX is less than 1 dBm. The TX chip modulates, up-converts, and amplifies the input signal. The output RF signal from the TX IC is connected to the antenna through a 1-m-long dielectric waveguide. The transmitted wireless signal is received by

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TABLE III MEASURED CONSTELLATION, IF BANDWIDTH, DATA RATE, EVM AND SPECTRAL EFFICIENCY IN DATA TRANSMISSION EXPERIMENT

Fig. 18. Illustration of measurement setup for wireless direct QPSK data transmission over the

-band.

Fig. 19. Photograph of the experiment setup for wireless direct QPSK data transmission over the -band.

another similar antenna which is connected to receiver through another 1-m dielectric waveguide. The wireless distance is 1.8 m. The gain of each antenna is 40 and has a beam width of 3 degrees. The RX amplifies, demodulates, and down-converts the RF signal to a baseband signal. No external IF amplifier is needed and consequently is not used in the measurement. Fig. 20(a)–(c) shows the measured eye diagrams for 15-, 20-, and 22-Gb/s QPSK signals on the channel of

Fig. 20. Measured eye diagram obtained at the RX output for wireless. (a) 30-Gb/s QPSK (15 Gbaud) with a BER of 4.4 10 . (b) 40-Gb/s QPSK (20 Gbaud) with a BER of 2.1 10 . (c) 44-Gb/s QPSK (22 Gbaud) with a BER of 4.8 10 . (d) 48-Gb/s QPSK (24 Gbaud) with a BER of 10 .

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TABLE IV PERFORMANCE COMPARISON

OF

RECEIVERS

TABLE V PERFORMANCE COMPARISON OF TRANSMITTERS

the RX output. The data rate up to 48 Gb/s (24 Gb/s on each and channel) was transmitted with a BER of 2.3 10 , as shown in Fig. 20(d). VI. CONCLUSION AND PERFORMANCE COMPARISON A TX/RX chipset for high-data-rate -band wireless links is demonstrated utilizing a 250-nm InP DHBT technology. The chipset can be used in both homodyne and heterodyne architecture. We have demonstrated 48-Gb/s direct wireless QPSK data transmission with a BER of 2.3 and energy efficiency of 7.44 pJ/b. In heterodyne architecture, 64-QAM was transmitted for data rate up to 18 Gb/s with a measured TX-to-RX EVM of 6.8% and spectral efficiency of 3.6 b/s/Hz. Tables IV and V show the comparison of mm-wave TX/RXs. The presented chipset has largest RF bandwidth and IF bandwidth and consume low dc and LO power among published mm-wave TX/RXs operating in the -band and -band (90–140 GHz). ACKNOWLEDGMENT The authors would like to thank the Technology Department, Teledyne Scientific Company, for fabrication of the chip. REFERENCES [1] D. Lockie and D. Peck, “High-data-rate millimeter-wave radios,” IEEE Microw. Mag., vol. 10, no. 5, pp. 75–83, Aug. 2009.

[2] K. Okada et al., “A 60-GHz 16-QAM/8PSK/QPSK/BPSK direct-conversion transceiver for IEEE802.15.3c,” in Proc. IEEE Int. Solid-State Circuit Conf., Feb. 2011, pp. 160–161. [3] S. Emami et al., “A 60 GHz CMOS phased-array transceiver pair for multi-Gbit/s wireless communications,” in Proc. IEEE Int. Solid-State Circuit Conf., Feb. 2011, pp. 164–165. [4] K. Okada et al., “A full 4-channel 6.3 Gbit/s 60 GHz direct-conversion transceiver with low-power analog and digital baseband circuitry,” in Proc. IEEE Int. Solid-State Circuit Conf., Feb. 2012, pp. 218–219. [5] A. Oncu and M. Fujishima, “19.2 mW 2 Gbit/s CMOS pulse RX for 60 GHz band wireless communication,” in Proc. Symp. VLSI Circuits, Jun. 2008, pp. 158–159. [6] R. Taori and A. Sridharan, “Point-to-multipoint in-band mmwave backhaul for 5G networks,” IEEE Commun. Mag., vol. 53, no. 1, pp. 195–201, Jan. 2015. [7] F. T. Ulaby, R. K. Moore, and A. K. Fung, Microwave Remote Sensing—Active and Passive. Norwood, MA, USA: Artech House, 1981, vol. I. [8] “Table of frequency allocations,” FCC, Washington, DC, USA, Tech. Rep. FCC05-70, 2015. [9] K. Schmalz, W. Winkler, J. Borngraber, W. Debski, B. Heinemann, and J. Scheytt, “A Subharmonic RX in SiGe technology for 122 GHz sensor applications,” IEEE J. Solid-State Circuits, vol. 45, no. 9, pp. 1644–1656, Sep. 2010. [10] I. Sarkas, J. Hasch, A. Balteanu, and S. Voinigescu, “A fundamental frequency 120-GHz SiGe BiCMOS distance sensor with integrated antenna,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 3, pp. 795–812, Mar. 2012. [11] A. Tang et al., “A 144 GHz 0.76 cm-resolution subcarrier SAR phase radar for 3D imaging in 65 nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig., 2012, pp. 264–266. [12] U. Pfeiffer, E. Ojefors, and Y. Zhao, “A SiGe I/Q transmitter and RX chipset for emerging high-frequency applications at 160 GHz,” in IEEE Int. Solid-State Circuits Conf. Dig., 2010, pp. 416–417.

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[13] E. Ojefors, F. Pourchon, P. Chevalier, and U. Pfeiffer, “A 160-GHz lownoise downconverter in a SiGe HBT technology,” in Proc. Eur. Microw. Conf., Sep. 2010, pp. 521–524. [14] Y. Zhao, E. Ojefors, K. Aufinger, T. Meister, and U. Pfeiffer, “A 160-GHz subharmonic transmitter and RX chipset in an SiGe HBT technology,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 10, pp. 3286–3299, Oct. 2012. [15] K. Jungsik, J. Sanggeun, K. Moonil, M. Urteaga, and J. Jinho, “H-band power amplifier integrated circuits using 250-nm InP HBT technology,” IEEE Trans. THz Sci. Technol., vol. 5, no. 2, pp. 215–222, Mar. 2015. [16] A. Hirata et al., “120-GHz-band wireless link technologies for outdoor 10-Gbit/s data transmission,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 3, pp. 881–895, Mar. 2012. [17] A. Hirata et al., “5.8-km 10-Gbps data transmission over a 120-GHzband wireless link,” in Proc. IEEE Int. Wireless Inf. Technol. Syst. Conf., 2010, pp. 1–4. [18] Z. Bo, X. Yong-Zhong, W. Lei, and H. Sanming, “A switch-based ASK modulator for 10 Gbps 135 GHz communication by 0.13 m MOSFET,” IEEE Microw. Wireless Compon. Lett., vol. 22, no. 8, pp. 415–417, Aug. 2012. [19] D. Lopez-Diaz et al., “A 240 GHz I/Q RX and transmitter for data transmission up to 40 Gbit/s,” in Proc. Eur. Microw. Conf., 2013, pp. 1411–1414. [20] M. Abbasi et al., “Single-chip 220 GHz active heterodyne RX and transmitter MMICs with on-chip integrated antenna,” IEEE Trans. Microw. Theory Techn., vol. 59, no. 2, pp. 466–478, Feb. 2011. [21] H. Takahashi et al., “120 GHz band 20 Gbit/s transmitter and receiver MMIC using I/Q phase shift keying,” in Proc. 7th Eur. Microw. Integr. Circuits Conf., Oct. 2012, pp. 313–316. [22] T. Kosugi, H. Takahashi, A. Hirata, and K. Murata, “Broadband InP MMICs for 120 GHz wireless data communication,” in Proc. IEEE Radio and Wireless Symp., 2013, pp. 49–51. [23] C. Wang, C. Lin, Q. Chen, B. Lu, X. Deng, and J. Zhang, “A 10-Gbit/s wireless communication link using 16-QAM modulation in 140-GHz band,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 7, pp. 2737–2746, Jul. 2013. [24] F. Boes et al., “Experimental validation of adverse weather effects on a 240 GHz multi-gigabit wireless link,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 1–6, 2014, pp. 1–3. [25] M. Bao, R. Kozhuharov, and H. Zirath, “A high power-efficiency D-band frequency tripler MMIC with gain up to 7 dB,” IEEE Microw. Compon. Lett., vol. 24, no. 2, pp. 123–125, Feb. 2014. [26] S. Carpenter, M. Abbasi, and H. Zirath, “A 115–155 GHz I/Q up-converting MMIC mixer in InP DHBT technology,” in Proc. Eur. Microw. Integr. Circuits Conf., Oct. 6–8, 2013, pp. 113–116. [27] S. Carpenter, M. Abbasi, and H. Zirath, “Fully integrated D-band Direct Carrier Quadrature (I/Q) modulator and demodulator circuits in InP DHBT technology,” IEEE Trans. Microw. Theory Techn., vol. 63, no. 5, pp. 1666–1675, May 2015. [28] B. Razavi, “Design considerations for direct-conversion receivers,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 44, no. 6, pp. 428–435, Jun. 1997. [29] A. Wiesbuer and G. Temes, “On-line digital compensation of analog circuit imperfections for cascaded sigma delta modulators,” in Proc. IEEE-CAS Region 8 Analog and Mixed IC Design Workshop, Sep. 1996, pp. 92–97. [30] I. Fatadin, D. Ives, and S. J. Savory, “Laser linewidth tolerance for 16-QAM coherent optical systems using QPSK partitioning,” IEEE Photon. Technol. Lett., vol. 22, no. 9, pp. 631–633, May 2010. [31] A. Viterbi, “Nonlinear estimation of PSK-modulated carrier phase with application to burst digital transmission,” IEEE Trans. Inf. Theory, vol. IT-29, no. 4, pp. 543–551, Jul. 1983. [32] S. Carpenter, H. Zhongxia, B. Mingquan, and H. Zirath, “A highly integrated chipset for 40 Gbps wireless D-band communication based on a 250 nm InP DHBT technology,” in Proc. IEEE Compound Semicond. Integr. Circuits Symp., Oct. 2014, pp. 1–4. [33] S. Koch, M. Guthoerl, I. Kallfass, P. Leuther, and S. Saito, “A 120–145 GHz heterodyne receiver chipset utilizing the 140 GHz atmospheric window for passive millimeter-wave imaging applications,” IEEE J. Solid-State Circuits, vol. 45, no. 10, pp. 1961–1967, Oct. 2010. [34] D. Sandstrom, M. Varonen, M. Karkkainen, and K. Halonen, “A W-band 65 nm CMOS transmitter front-end with 8 GHz IF bandwidth and 20 dB IR- ratio,” in IEEE Int. Solid-State Circuits Conf. Dig., 2010, pp. 418–419.

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Sona Carpenter (S'13) received the M.E. (Hons.) degree in electronics and telecommunication from the S. G. S. Institute of Technology and Science, Indore, India, in 2008. She is currently working toward the Ph.D. degree at the Chalmers University of Technology, Göteborg, Sweden. In 2007, she joined the Satellite Payload Technology Area, Indian Space Research Organization, Ahmedabad, India, where she was a Scientist/Engineer involved with research and development of microwave circuits and subsystems for the Indian national and geostationary communication satellite payload receivers. She is currently with the Microwave Electronic Laboratory, Chalmers University of Technology, Göteborg, Sweden. Her current research interests include the design of millimeter-wave integrated circuits and systems with a focus on millimeter-wave high-speed wireless communication. Ms. Carpenter was a recipient of the 2013 GaAs Association Ph.D. Student Fellowship Award.

Dhecha Nopchinda (S'12) was born in Bangkok, Thailand, in 1991. He received the B.Eng degree (with first-class honors) in electronics and communication engineering from the Sirindhorn International Institute of Technology, Thammasat University, Bangkok, Thailand, in 2013, and the M.Sc degree (with distinction) in electronic and electrical engineering from University College London, London, U.K., in 2014. He is currently working toward the Ph.D. degree at the Chalmers University of Technology, Göteborg, Sweden. In 2015, he joined the Microwave Electronics Laboratory, Department of Microtechnology and Nanoscience, Chalmers University of Technology, Göteborg, Sweden, where his research is focused on signal processing and system-level design of high-speed microwave and optical communication systems. Mr. Nopchinda was the recipient of a scholarship to study at the School of Information, Computer, and Communication Technology, Sirindhorn International Institute of Technology, Thammasat University, in 2009.

Morteza Abbasi (M'07) received the M.Sc. and Ph.D. degrees in electrical engineering from the Chalmers University of Technology, Göteborg, Sweden, in 2007 and 2012, respectively. From 2008 to 2010, he held an internship with NXP Semiconductor Research, Eindhoven, The Netherlands, where he designed 60-GHz power amplifier and transmitter circuits in CMOS technology. Since 2014, he has been a Research Scholar with the Electrical and Computer Engineering Department, North Carolina State University, Raleigh, NC, USA. His research is focused on the design of millimeter- and submillimeter-wave integrated circuits and systems in silicon and III–V technologies, as well as nonlinear device characterization and modeling. Dr. Abbasi was the recipient of the 2009 Silver Prize of the Student Paper Contest of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) Asia–Pacific Microwave Conference and the 2008 GaAs Association Ph.D. Student Fellowship Award.

Zhongxia Simon He (M'09) received the M.Sc. degree from Beijing Institute of Technology, Beijing, China, in 2008, and the Ph.D. degree from Chalmers University of Technology, Göteborg, Sweden, in 2014. He is currently an Assistant Professor with the Microwave Electronics Laboratory, Department of Microtechnology and Nanoscience (MC2), Chalmers University, Göteborg, Sweden. His current research interests include high data rate wireless communication, modulation and demodulation, mixed-signal integrated circuit design, radar, and packaging.

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Mingquan Bao was born in 1962. He received the B.S. and M.S. degrees in electrical engineering from Zhejiang University, Hangzhou, China, in 1985 and 1988, respectively, and the Ph.D. degree in radar remote sensing from the University of Hamburg, Hamburg, Germany, in 1995. From 1995 to 1997, he was with the Institute of Oceanography, University of Hamburg. From 1997 to 2000, he was with the Center for Remote Imaging Sensing and Processing, University of Singapore, Singapore. From 2000 to 2001, he was with the German Aerospace Center (DLR), Kö\ln , Germany, where his research was focused on interferometric radar remote sensing. Since 2001, he has been with Microwave System, Radio Access Technologies, Ericsson Research, Ericsson AB, Göteborg, Sweden. He has authored over 50 papers in refereed journals and conferences. He holds 27 U.S., European, Japanese, and Chinese patents. His research interests include RF integrated circuit designs such as low-noise amplifiers, mixers, frequency multipliers, power detectors, and voltage-controlled oscillators in silicon, GaAs, GaN technologies.

Thomas Eriksson (M’00) received the Ph.D. degree in information theory from Chalmers University of Technology, Göteborg, Sweden, in 1996. From 1990 to 1996, he was with Chalmers. In 1997 and 1998, he was at AT&T Labs – Research in Murray Hill, NJ, USA, and in 1998 and 1999 he was at Ericsson Radio Systems AB, Kista, Sweden. Since 1999, he has been with Chalmers University, University of Technology, Göteborg, Sweden, where he is a Professor in communication systems. Further, he was a Guest Professor with Yonsei University, South Korea, in 2003–2004. He has authored and coauthored more than 200 journal and conference papers and holds seven patents. His

research interests include communication, data compression, and modeling and compensation of non-ideal hardware components (e.g., amplifiers, oscillators, modulators in communication transmitters and receivers, including massive MIMO). He is currently Vice Head of the Department of Signals and Systems, Chalmers University, where he is responsible for undergraduate and graduate education.

Herbert Zirath (M'86–SM'08–F'11) was born in Göteborg, Sweden, on March 20, 1955. He received the M.Sc. and Ph.D. degree in electrical engineering from Chalmers University, Göteborg, Sweden, in 1980 and 1986, respectively. From 1986 to 1996, he was a Researcher with the Radio and Space Science, Chalmers University, Göteborg, Sweden, where he was engaged in developing a GaAs and InP-based HEMT technology, including devices, models and circuits. In the spring and summer of 1998, he was a Research Fellow with the California Institute of Technology, Pasadena, CA, USA, where he was engaged in the design of MMIC frequency multipliers and Class-E power amplifiers. Since 1996, he has been a Professor of high-speed electronics with the Department of Microtechnology and Nanoscience, MC2, Chalmers University. He became the head of the Microwave Electronics Laboratory 2001. At present, he is leading a group of approximately 40 researchers in the area of high-frequency semiconductor devices and circuits. His main research interests include monolithic microwave integrated circuit designs for wireless communication and sensor applications based on III-V, III-N, Graphene, and silicon devices. He has authored and coauthored more than 570 refereed journal/conference papers, h-index of 37, and holds five patents. He is a Research Fellow with Ericsson AB, leading the development of a -band (110–170 GHz) chipset for high-data-rate wireless communication. He is a cofounder of Gotmic AB, a company developing highly integrated frontend MMIC chip-sets for 60-GHz and -band wireless communication.

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Experimental Verification of Below-Cutoff Propagation in Miniaturized Circular Waveguides Using Anisotropic ENNZ Metamaterial Liners Justin G. Pollock, Student Member, IEEE, and Ashwin K. Iyer, Senior Member, IEEE

Abstract—This paper presents experimental verification of below-cutoff transmission through miniaturized waveguides whose interior is coated with a thin anisotropic metamaterial liner possessing epsilon-negative and near-zero properties. These liners are realized using a simple printed-circuit implementation based on inductively loaded wires, and introduce an mode well below the natural cutoff frequency. The inclusion of the liner is shown to substantially improve the transmission between two embedded shielded-loop sources. A homogenization scheme is developed to characterize the liner’s anisotropic effective-medium parameters, which is shown to accurately describe a set of frequency-reduced cutoffs. The fabrication of the lined waveguide is discussed, and the experimental and simulated transmission results are shown to be in agreement. Index Terms—Backward wave, below-cutoff propagation, circular waveguides, effective medium, epsilon-near-zero (ENZ), homogenization, inhomogeneous waveguides, metamaterials, miniaturization, negative permittivity, printed circuits.

I. INTRODUCTION

M

ETALLIC waveguides are attractive at high frequencies for their low propagation loss, moderate bandwidths, shielding properties, and excellent power-handling capability. Hollow versions prove useful in several applications, including fluid-density measurements in the oil/gas industry [1], microwave heating of fluids [2], the observation of exotic radiation in particle physics [3], and low-loss infrared transmission of CO -laser light [4]. However, these waveguides lack the capability to be miniaturized without additional loading, due to the strict dependence of their cutoff frequencies on their transverse dimensions. Inhomogeneously filling the waveguide with dielectric regions relaxes this condition, retains access to their interiors, and can introduce new propagation phenomena, such as frequency-reduced propagating bands with forward- or backward-wave behavior [5]. With the advent of metamaterial loading of waveguides, it is possible to obtain intriguing propagation phenomena through

Manuscript received March 30, 2015; revised June 22, 2015 and December 11, 2015; accepted February 12, 2016. This work was supported in part by the Natural Sciences and Engineering Research Council (NSERC) of Canada. The authors are with the Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada T6G1H9 (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2532872

engineering the metamaterial’s effective permittivity and permeability. For instance, below-cutoff propagation occurs in waveguides loaded by arrays of subwavelength electric and magnetic scatters that exhibit negative permittivity and/or permeability at low frequencies [6], [7]. It was recently shown that the inclusion of thin metamaterial liners into perfect electric conductor (PEC) circular waveguides can permit propagation well below the unlined waveguide’s fundamental-mode cutoff [8]. Modeling the liner as isotropic and homogeneous, a frequency-reduced backward-wave band corresponding to a hybrid electric mode was shown to occur in the frequency regime in which the liner exhibited dispersive epsilon-negative and near-zero (ENNZ) properties. This backward-wave band was over 42% below the waveguide’s fundamental-mode cutoff frequency, in which transmission occurred through multiple resonant peaks corresponding to Fabry–Pérot-type resonant phase conditions over the waveguide’s length. Although narrowband and dispersive, it was suggested in [8] that these waveguides may enable several emerging applications, including traveling-wave imaging in magnetic resonance imaging (MRI) scanner bores [9], characterization of the properties of small quantities of fluids [10], and in novel particle-beam experiments [11]—all of which require access to the waveguide interior and can benefit greatly from miniaturization. Complementing these transmission studies, the frequency-reduced mode in a metamaterial-lined open-ended waveguide (OEWG) probe antenna was shown in simulation to yield substantial gain improvements over a similarly sized hollow and below-cutoff waveguide probe [12]. In each of these works, the subwavelength waveguide dimensions and the stark contrast between the metamaterial and vacuum permittivities produced an -mode field profile with uniform fields in the inner-vacuum region and discontinuously strong fields in the outer-liner region. While these initial studies examined the instructive case in which the liner is modeled as an effective medium with an isotropic and homogeneous permittivity, practical metamaterials are naturally anisotropic. For instance, optical fibers loaded using radially emanating silver-coated nanopores [13] exhibit plasmonic-like behavior. In these waveguides, the metamaterial’s permittivity is anisotropic and may be modeled by a diagonalized tensor ( ) in a cylindrical coordinate system with elements that assume negative values for the directions corresponding to the nanopore axes. In the microwave regime, these negative permittivities may be achieved using arrays of

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case in which the metamaterial liner has an anisotropic permittivity and permeability described by tensors diagonalized in a cylindrical coordinate system. Taking the coordinate axis to coincide with the waveguide axis, the material tensors take the form and , in which is the identity tensor. After substantial mathematical manipulation, the resulting anisotropic metamaterial-lined circular waveguide’s dispersion relation takes the following form: (1a) (1b)

Fig. 1. Cutoff frequencies of the , , and modes , of the anisotropic dielectric liner versus the relative permittivity, of the host PEC circular waveguide. The dispersion defined in Section II is shown. profile of

inductively loaded thin wires, which can be implemented in printed-circuit form [12], [14]. Although homogenization of such metamaterials can be carried out through field averaging [15] or inversion of the scattering properties of a metamaterial sample [16], these approaches have difficulty modeling strong spatial dispersion [17], bianisotropy [18], and non-TEM propagation, all of which may be observed in thin-wire media. This is further complicated in cylindrical geometries. An approach for the accurate homogenization of cylindrically anisotropic metamaterials might bring significant clarity to intriguing phenomena recently observed in metamaterial-loaded waveguides [11]. The layout of this paper is as follows. Section II explores the dispersion of several new modes supported by metamaterial-lined circular waveguides whose liner is modeled as an anisotropic and homogeneous effective medium, developing relationships between individual material parameters and the cutoff frequencies of modes of interest. Section III develops a printed-circuit implementation of the ENNZ metamaterial liner and introduces a novel homogenization approach that gives insight into the metamaterial’s effective-medium parameters based on the dispersions of frequency-reduced modes supported by the liner and their similarity to the transmission-line (TL) modes of TL metamaterials. An experimental prototype is developed, and parametric studies are performed to gauge the impact of fabrication tolerances on the dispersion of frequency-reduced modes. In Section IV, the metamaterial-lined waveguide is placed between two embedded shielded loops, and the transmission features are investigated through full-wave simulations and experiments. II. THEORY The inset in Fig. 1 presents the geometry of the metamaterial-lined circular waveguide (radius ) under consideration. An inner-core vacuum region (radius ) of permittivity and permeability is surrounded by a metamaterial layer of thickness , backed by a PEC waveguide wall. In contrast to [8], we investigate here the more complex, but more realistic,

(1c) is the complex waveguide propagation conHere, stant in the (axial) direction, , , and we define the following quantities: (2a) (2b) is a Bessel function of integer order , and are combinations of Bessel ( ) and Neumann ( which can be expressed as follows:

and ) functions,

(3a) (3b) Their orders are generally complex and are defined as follows: (4a) The roots of (1b) and (1c) respectively provide the cutoffs of and modes. Whereas the resulting dispersion relathe tion is capable of treating fully biaxial liners, the focus of this work is on modes, with field polarizations similar to their counterparts in a homogeneously filled waveguide with no longitudinal electric-field component at their cutoff frequencies. Hence, we look at several frequency-reduced modes that can be potentially supported by the simplifying case of a liner that has a biaxial permittivity (i.e., ) with and a nonmagnetic response (i.e., ). In this case, after applying the cutoff frequency condition (i.e., ), (2b) and (4a) reduce to and , respectively. When applied to (1b), this reveals that the modes’ cutoffs are independent of , but vary with and . However, it should be noted from (1b) that appears in the order of the Bessel functions while appears in the argument; thus, the modes’ cutoff frequencies are far more sensitive to than to . Due to this weak dependence on , for the remainder of the work we assume a

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. POLLOCK AND IYER: EXPERIMENTAL VERIFICATION OF BELOW-CUTOFF PROPAGATION IN MINIATURIZED CIRCULAR WAVEGUIDES

uniaxial transverse permittivity . This assumption will aid in the theoretical analysis of the modes since the Bessel-function order becomes purely real. A. Cutoff-Frequency Dependence Consider a metamaterial-lined waveguide with dimensions mm and mm. Fig. 1 presents the dependence of the dielectric-lined circular waveguide’s (black solid curve), (dark grey solid curve), and (light grey solid curve) modes’ cutoff frequencies on . The cutoff frequencies are only marginally decreased for , which corroborates the result in [8] for isotropic liners. As , termed the epsilon-near-zero (ENZ) regime, the cutoff frequencies vary rapidly. For epsilon-positive and near-zero (EPNZ) values, all cutoff frequencies are strongly increased. However, as (i.e., the ENNZ regime), the cutoff frequencies are drastically decreased. All the above properties for all higher azimuthal-order modes are confirmed in (1), which suggests that practical anisotropic metamaterial liners may introduce a useful diversity of frequency-reduced modes. In fact, as will be shown below for a particular ENNZ permittivity value, each mode’s cutoff frequency can, in theory, be reduced to arbitrarily low frequencies for a particular ENNZ permittivity value. Furthermore, as the azimuthal order increases, the required to effect this reduction tends to increasingly negative values. Therefore, for a sufficiently negative , the cutoff frequency of the mode is lower than those of the and modes. This is opposite to the vacuum-filled case in which, as increases, the cutoff frequency of the mode increases. To enable design of the -mode cutoffs, we apply smallargument approximations to (1b). This yields an approximate, but useful relation between the cutoff frequency, , and the waveguide’s dimensions and liner properties (5a) where (5b) This simple relationship constitutes a generalized design equation for all modes for . The particular small-angle approximations that were used in deriving this expression are not valid for , but for these modes is most easily obtained numerically from (1). By setting , (5a) captures the behavior of the cutoff frequency tending to zero in Fig. 1, which if applied to (5b) yields (6) In this expression, specifies the maximum ENNZ value required by the anisotropic liner to arbitrarily lower the cutoff frequency, which is strictly dependent on the waveguide’s and liner’s dimensions. Equation (6) explicitly captures the action of the ENNZ liners in that as (i.e., the liner is of infinitesimal thickness), and, therefore, , must more closely approach zero to restore propagation. It should be noted

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that (5) becomes increasingly accurate both as (hence, ) and as increases. Furthermore, (6) highlights the shift of to more negative values as increases and in the limit , . This suggests a crowding of higher azimuthal-order modes at . B. Dispersion of Frequency-Reduced Modes Whereas Fig. 1 aids in choosing the value of to yield a desired set of cutoff frequencies, the task of realizing ENNZ values requires that material dispersion for the liner be taken into account. For this reason, the liner’s complex permittivity dispersion is described by a Drude model with in which GHz is the plasma frequency and MHz is the damping frequency establishing the liner’s loss. This dispersion profile (dark grey circle curve) is overlaid on the cutoff-frequency curves in Fig. 1. The intersections yield the corresponding , , and cutoff frequencies for which their frequency-reduced intersections occur for ENNZ and the higher frequency intersections occur near their natural cutoffs (since approaches unity at these frequencies). Although Fig. 1 does not indicate the equivalent modes’ intersections, in general the cutoff frequencies are weakly dependent on . Therefore, they would also occur at their natural cutoffs. However, for the mode, satisfies (1c); this corresponds to the intersection of the vertical axis with in Fig. 1. The resulting important implication is the cutoff of this frequency-reduced mode occurs precisely at the Drude plasma frequency of . This condition is independent of the dimensions and remaining material parameters, and occurs in addition to its high-frequency natural cutoff. Fig. 2 focuses on the frequency-reduced and modes. The normalized propagation ( ) and attenuation ( ) constants are indicated by solid and dashed lines, respectively. The frequency-reduced mode (light grey curves) is described by a backward-wave band and, as mentioned earlier, a cutoff frequency . The anisotropic metamaterial-lined waveguide supports multiple highly dispersive frequency-reduced propagating bands for . In addition to the waveguide-type modes, there also exist corresponding surface-type modes that are bound to the metamaterial-vacuum interface [19]. These may be differentiated by their radial wavenumbers, . The waveguide-type modes exhibit a standing-wave distribution in the transverse plane due to an imaginary (i.e., propagating) . The surface-type modes, on the other hand, decay evanescently into vacuum from the interface, and are characterized by real (i.e., attenuating) values of . To retain clarity, Fig. 2 presents only the solutions. In the observed range, the dispersion relation (1) reveals both the mode’s waveguide-type (black curves) and surface-type (dark grey circle curves) solutions, each exhibiting complex-mode regions for GHz. Near , both solutions have comparable and values. This creates the potential for the backward-wave and complex bands to couple, and allows for regions of forward-wave propagation near cutoff. It is found that this effect may be mitigated by reducing the liner’s thickness, increasing the degree of miniaturization, and choosing a lower loss metamaterial. Below , the two

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Fig. 2. Dispersion of (dashed curves) and (solid curves) for the fol(light grey curves), lowing modes of the metamaterial-lined waveguide: waveguide-type (black curves), and surface-type (dark grey circle curves). All curves are obtained from (1).

solutions rapidly become distinct, such that one can be classified as an evanescent band and another as a backward-wave propagating band. It is in this region that the metamaterial-lined waveguide shall be operated for transmission of the mode.

Fig. 3. (a) Representative printed-circuit implementation of an ENNZ metamaand (b) dispersion of its frequency-reduced terial liner of thickness modes. (c) Evolution of a TL description of the printed-circuit implementation.

III. REALIZATION OF THE ENNZ LINER From the theoretical analysis in Section II, the frequency-reduced mode’s passband occurs when achieves ENNZ values. This work realizes this ENNZ condition through the plasmonic-like interaction of arrays of thin wires [20]. Fig. 3(a) presents a printed circuit board (PCB) implementation of a single layer of the thin-wire metamaterial liner. Each layer consists of an orthogonal grid of radially and azimuthally directed thin copper traces loaded by discrete inductances and capacitive gaps modeled by discrete capacitances , respectively. Layers are then stacked axially with a periodicity . Although only a single period is used, the strong field confinement from the discrete inductors provides the desired miniaturization while allowing the liner to remain thin. The purpose of the discrete capacitors will be discussed in further detail shortly. Further details on the metamaterial design may be found in [12]. A. Homogenization In general, this arrangement of thin wires can be modeled by a biaxial permittivity tensor whose transverse components ( and ) are dispersive [21]. To model the impact of the transversely oriented current-carrying traces on the mode’s longitudinal magnetic field, must also be determined. Due to the absence of longitudinal wires and the small effect has on the mode’s dispersion, we assign . Since it has further been established that has a minimal impact on the cutoffs of modes, we retain the uniaxial assumption employed in Section II (i.e., ) to aid in the homogenization. The PCB implementation is also assumed to have a nonmagnetic transverse response (i.e., ). We now describe a first-order homogenization procedure that may be used to determine the nature of and , following which (1) may be used to predict the modes’ cutoffs.

It was shown in Section II that a frequency-reduced mode cutoff frequency is introduced when . Observation of the fields in the practical metamaterial-lined waveguide reveals that, although they are predominantly -like in the vacuum region, the use of discrete inductive loading to realize a strongly near-zero permittivity and the introduction of azimuthally directed current-carrying copper traces results in a strong radial electric field and axial magnetic field in the liner region. These can be described as those of an azimuthally oriented TL mode supported between the copper trace and the waveguide wall. Here, this fact will be used to develop an equivalent-circuit model for the metamaterial liner based on TL metamaterial theory from which its effective permittivity and permeability shall be extracted. The field polarizations of the TL mode suggest that these extracted parameters are intrinsically related to and of the liner. Fig. 3(c), (i) shows a curved circuit description of multiple TL unit cells, in which may be taken as an effective azimuthal periodicity. This is described by the equivalent-circuit model in Fig. 3(c), (ii), which consists of a shunt inductor and series capacitor loading a host TL of periodicity . In the effective-medium regime, the per-unit-length series impedance ( ) and shunt admittance ( ) of Fig. 3(c), (iii) represent, respectively, the distributed inductance and capacitance of an effective TL describing the azimuthal TL mode. Here, may be related to the liner’s effective (assumed real), whose frequency response is Drude-like in the vicinity of its plasma frequency , where achieves a zero value [22] where

(7)

is the intrinsic permittivitiy of the host In this expression, TL segments and is a geometrical parameter relating the TL

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mode’s characteristic impedance to the wave impedance of the intrinsic medium. Similarly, yields a response for that is Drude-like in the vicinity of its own magnetic plasma frequency, . However, the typically narrowband magnetic response of metamaterials is often better approximated by a single- or multi-pole Lorentz dispersion, as in the split-ring resonator [23], [24], particularly at frequencies well below . In fact, although the proposed first-order homogenization scheme considered a single metamaterial layer in isolation, such additional resonances in may result from the magnetic coupling between adjacent metamaterial layers. A more sophisticated equivalent-circuit model may look to multiconductor transmission line (MTL) theory to include this mutual coupling to produce a more accurate dispersion profile for . In the interest of conciseness, this shall be left for a future work. In the present model, the use of a gap capacitance that is diminutive in comparison to the strong inductive loading ensures that ; the assumption of a Lorentz-like dispersion therefore implies that at is near unity. It should be recalled that the frequency-reduced mode’s cutoffs are dominated by ’s ENNZ response for thin liners, and are therefore not strongly affected by moderate deviations in from this assumption. To validate the proposed homogenization procedure, the representative design in Fig. 3(a) with 0.3- and 0.6 mm-wide radial and azimuthal copper traces, respectively, printed on a Rogers/ Duroid 5880 substrate, is assigned the following parameters: mm, mm, nH, pF, , and mm. To determine the parameters of the host TL, a flattened, unloaded, and similarly oriented copper trace of the same geometrical dimensions was simulated, revealing that and , and both parameters vary weakly with frequency. For the specified loading values, exhibits GHz. The homogenized liner and waveguide share the same physical dimensions as the PCB implementation ( mm and mm). Using these values, the above homogenization procedure predicts frequency-reduced , , , and modes with cutoff frequencies of GHz, GHz, GHz, and GHz, respectively. That (i.e., where ) makes physical sense from a TL perspective since this implies an infinite wavelength condition in the TL mode, which is only satisfied for no azimuthal variation (i.e., ). Fig. 3(b) presents the dispersion of the axial phase incurred per unit cell ( ) obtained from HFSS’s eigenmode simulator for the frequency-reduced (black dashed curve), (black solid curve), (dark grey solid curve), and (light grey solid curve) modes whose respective cutoff frequencies are GHz, GHz, GHz, and GHz, respectively. These are found to be within 1.2%, 0.08%, 4.8%, and 7.8%, respectively, of those predicted by the homogenization method. Interestingly, there remains a good agreement between the HFSS and homogenization results for the higher azimuthal-order cutoffs, even though their associated large azimuthal phase variation significantly perturbs the assumption of homogeneity. Although not shown, the homogenization results exhibit the

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Fig. 4. (a) Simulation model and (b) fabricated prototype of the designed printed-circuit metamaterial based on inductively and capacitively loaded copper traces on a dielectric substrate.

same salient features as the HFSS data away from cutoff (backward-wave trends, cutoff frequencies decreasing with increasing azimuthal order, forward-backward coupling of the mode). However, the latter appear less dispersive than the former. Here, it should be noted that the above homogenization approach only seeks to match the cutoff frequencies of the and modes, and not the full dispersion profile away from cutoff, for several reasons. Most significantly, the effective-medium approximation disregards the perturbations introduced by axial periodicity, which result in the coupling of forward and backward spatial harmonics at the band edges. Furthermore, the longitudinal electric fields become more pronounced away from cutoff, which deviates from the assumed TL-mode polarizations and also contributes to stronger spatial dispersion. Both effects break down the assumed Drude dispersion profile for [21]. B. Fabricated Metamaterial Liner Fig. 4(a) presents a version of the printed-circuit metamaterial that is amenable to standard PCB fabrication. A small radial gap

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TABLE I LINER DIMENSIONS

Fig. 5. Dispersion of the frequency-reduced , , modes as obtained from full-wave eigenmode simulations.

, and

of width and an outer -directed trace of width are introduced. The outer trace replaces the waveguide wall’s function in establishing a continuous azimuthal current path between adjacent -directed inductors. This eases the fabrication challenge of soldering to the waveguide wall, which was required in the previous design, and enables the ENNZ liner to be modular. In this design, Coilcraft ultra-high- 0806SQ-6N0 inductors were chosen. Their inductance of nH and quality factor at GHz were extrapolated outside the frequency range presented in their data sheets. Due to the larger concentration of fields around each inductor, the value of is a pivotal factor in defining the mode’s propagation loss. The traces are printed on a Rogers/Duroid 5880 substrate of 1.575-mm thickness, which, with the chosen inductor’s height, gives mm. The remaining design dimensions shown in Fig. 4(a) are listed in Table I, and were chosen to provide a reasonably close match to the cutoffs of the previous design shown in Fig. 3(a). A photograph of the fabricated PCB metamaterial is shown in Fig. 4(b). Full-wave eigenmode simulations of this structure reveal that it supports frequency-reduced , , , and modes, as shown in Fig. 5, with cutoff frequencies of GHz, GHz, GHz, and GHz, respectively. However, these simulated data do not include the impact of fabrication tolerances imposed through milling, etching, and component placement. Fig. 6(a)–(d) presents the dispersion curves of the frequencyreduced mode for varying , , , and values, respectively. Since the loading inductance, , primarily controls the location of the frequency-reduced mode cutoffs, it is instructive to look at the impact of their listed tolerances of up to 5% (0.414 nH). Furthermore, precise measurements of each the fabricated layers’ reveal tolerances of up to 15% (0.45 mm) per layer. Lastly, the metamaterial’s extremely fine features push the limits of the milling and etching process and this leads to tolerances of up to 50% (50 m) in and . Each figure shares the nominal case (solid black curve) whose dimensions were presented in Table I. While all the observed parameters shift the band up or down, commands the greatest change

Fig. 6. Variation of the dispersion of the frequency-reduced , (b) , (c) , and (d) . (a)

mode with:

in the cutoff frequency. The cutoff is only moderately impacted by and and only minutely by . The dispersion profile’s shape is dependent on and is more dispersive when the unit cells are stacked closer together. It is worth noting that, despite the tolerance levels of each parameter, the mode’s cutoff frequency always remains within 3% of its designed value of GHz. IV. NUMERICAL AND EXPERIMENTAL VERIFICATION Fig. 7(a)–(c) presents the full-wave-simulation and experimental setup, respectively, which consist of two vacuum-filled excitation waveguides of radius mm and a cutoff frequency of 5.857 GHz that are smoothly connected to an intermediate metamaterial-lined waveguide. In simulation studies describing the liner as isotropic and homogeneous, the transmission through a below-cutoff waveguide was significantly improved [8]. In this work, the PCB metamaterial presented in Fig. 4(a) and (b) is arranged into a stack of 11 layers along the intermediate waveguide’s length of mm. To efficiently excite the mode without strongly exciting the and other higher order frequency-reduced modes, two balanced shielded loops [25] are embedded within the closed evanescent waveguide sections of length mm at a distance mm from a PEC back wall. Details of the design for each shielded loop (radius mm and gap ) can be found in [12]. A. Transmission Simulations Without the metamaterial liner, the unloaded vacuum-filled intermediate waveguide is within its natural evanescent region for frequencies below GHz. The dashed grey curve in Fig. 8(a) presents the insertion loss obtained from simulations for this case, and verifies that the intermediate waveguide under cutoff strongly attenuates the mode. The insertion loss achieves a minimum of 34 dB at GHz. Now, according to Fig. 5, introducing the PCB metamaterial layers should enable propagation below GHz by way of a frequency-reduced backward-wave band. HFSS full-wave simulations show that the insertion loss [black dashed curve in Fig. 8(a)] has a passband whose upper band edge is

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Fig. 8. (a) Insertion loss and (b) return loss as obtained from simulation and measurements for the transmission setup depicted in Fig. 7(a)–(c).

Fig. 7. (a) Full-wave simulation model, (b) fabricated experimental prototype of the metamaterial-lined waveguide showing one of two shielded-loop-antenna sources, and (c) experimental transmission setup.

roughly situated near and which demonstrates improvements in the transmission by up to 25.4 dB (at GHz). The dashed curves in Fig. 8(b) show the return loss of the simulated metamaterial-lined waveguide. It should be noted that the metamaterial layers are not symmetrical since the shielded loops at ports 1 and 2, respectively, face the inductor or the substrate dielectric. This asymmetry translates to unequal return loss profiles at Port 1 (grey dashed curves) and Port 2 (black dashed curves). Nevertheless, the return loss of both ports is described by several resonant peaks, and achieves maximum values of 18.7 dB at GHz (Port 1) and 7.2 dB at GHz (Port 2). Fig. 9 shows the simulated electric-field vectors at GHz located at the following cross sections: the excitation shielded loop, the center of the metamaterial-lined region, and the receiving shielded loop. The field patterns confirm that the shielded loop strongly excites and receives the mode, which is coupled from the input to output waveguide sections through the mode in the metamaterial-lined waveguide. Fig. 10(a)–(d) presents the simulated complex electric-field magnitudes for the transmission setup of Fig. 7(a) at the first four transmission peaks located at GHz, GHz,

Fig. 9. Simulated complex electric-field vectors at different planes at GHz showing excitation and detection of modes coupled through mode supported by the metamaterial-lined waveguide. an

Fig. 10. Simulated complex electric-field magnitudes shown in the metamaterial-lined waveguide at the following transmission peaks in the frequency-reGHz, (b) GHz, duced backward-wave passband: (a) GHz, and (d) GHz. (c)

GHz, and GHz, respectively. It is instructive to compare these field data to those presented in [8] for the isotropic homogeneous ENNZ liner. They are similar in that each successive peak corresponds to a Fabry–Pérot-type resonance of the mode in which an integer number of

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half-wavelengths is supported by the lined waveguide section over its length. Indeed, the resonant nature of the transmission is readily observed in Fig. 10(a)–(d). However, they differ in that the PCB metamaterial exhibits an electric field that is more evenly distributed across the waveguide’s cross section and an overall reduced bandwidth of the passband. These differences are attributed to the periodic nature of the PCB implementation, which relaxes the strict boundary conditions enforced on the electric fields at the metamaterial-vacuum interfaces. Furthermore, as noted in Section III-A, the finite periodicity results in a flattening of the dispersion, which therefore limits the lower edge of the propagating band. Nevertheless, across the PCB metamaterial liner’s backward-wave band, the level of transmission is generally better than that of the homogeneous ENNZ liners. This improvement can be attributed to the decreased insertion loss over the shorter waveguide length and an improvement in matching owed to the use of the shielded-loop excitation. B. Transmission Measurements A Keysight PNA-X N5244A network analyzer was used to measure the response of the experimental prototype, as shown in Fig. 7(b)–(c). For the unloaded vacuum-filled waveguide, the measured insertion loss [solid grey curve in Fig. 8(a)] shows a general agreement with simulations with a minimum of 32 dB at GHz. This 4.8% upshift in its optimal transmission frequency with respect to simulations is attributed to the fabricated shielded loop’s slightly smaller radius ( ) and tolerances in realizing the gap ( ) by hand. The modular nature of the multi-layered PCB metamaterial allows it to now be easily inserted into the intermediate waveguide. Pins are used to ensure the position and alignment is kept consistent with the simulation model, and are removed before measurements. The measured insertion loss (solid black curve) shows a very good agreement with simulations in which both data exhibit the same salient features. These include an anti-resonance at frequencies above an appreciable passband, below which there is a moderate roll-off in the insertion loss. This passband achieves an insertion loss as low as 15.0 dB at GHz, which is only a 4.8 dB decrease and 0.8% frequency upshift with respect to the optimal transmission in simulations. This represents a 19-dB enhancement in transmission over the unloaded waveguide. It should be noted that, at this frequency, the metamaterial-lined waveguide’s cross-sectional area is 60% smaller than that of a vacuum-filled circular waveguide operating at cutoff. This is a representative example of the even more extreme miniaturizations that may be achieved with ENNZ metamaterial liners. The measured return loss in Fig. 8(b) for Port 1 (solid black curve) and Port 2 (solid grey curve) generally agree with those from simulations in the passband, but achieve better performance. Port 1 and Port 2 achieve a maximum return loss of 18.7 dB at GHz and 7.2 dB at GHz, respectively, and 10-dB bandwidths of 3.3% and 7.0%, respectively. The general agreement of the passband region between simulations and measurements occurs despite the fabrication tolerances imposed on the shielded loop and PCB metamaterial. This is to be expected from the discussion in Section III, which

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highlights that, for the expected tolerances on , , , and , the mode’s dispersion remains roughly unchanged. However, the cumulative effect of these imperfections imposed on the multilayered stack will increase insertion loss due to decreased coupling between layers, particularly at lower frequencies in the backward-wave band where the unit cells lose their homogeneity. Furthermore, the inductor’s loaded quality factor in the fabricated unit cell may have been lower than approximated in simulations, which increases the insertion loss in the passband while preserving its general profile. Although more accurate simulations would have lowered the discrepancy, the computational intensity to achieve this was not feasible. It is expected that the observed transmission may be improved by reducing the loss in the liner region using either higher inductors or increasing liner thickness to minimize field confinement. Of course, as the liner becomes thicker (i.e., ), the waveguide becomes homogeneously ENNZ filled and transmission is expected to become independent of its geometry [26]. It may also be possible to improve the return-loss’s bandwidth by developing novel feeding structures that are electrically connected to the unit cell [27]. V. CONCLUSION The propagation characteristics of a miniaturized circular waveguide containing an anisotropic metamaterial liner have been analyzed theoretically, numerically, and experimentally. A full anisotropic treatment of the liner reveals that a spectrum of frequency-reduced modes is introduced well below its natural cutoff frequency, where the liner’s transverse permittivity assumes negative and near-zero values. It was shown how the cutoff frequency of the modes may be designed using the dimensions and permittivities of the liner and waveguide, while the cutoff frequency of the mode occurs at the liner’s plasma frequency. A practical PCB-based metamaterial based on inductively loaded metallic traces is shown to yield dispersion and miniaturization properties that are consistent with those observed for homogeneous anisotropic metamaterial liners. A first-order homogenization procedure used to model the PCB implementation employs an effective anisotropic permittivity and is shown to accurately match the cutoff frequencies of the lowest order frequency-reduced modes. Full-wave simulations and experimental results were presented for a waveguide lined with 11 metamaterial layers and excited by two shielded-loop sources. The data are in good agreement, and reveal a frequency-reduced passband demonstrating an enhancement of transmission of up to 19 dB as compared to a similarly excited vacuum-filled waveguide. ACKNOWLEDGMENT The authors would like to acknowledge the generosity of the Rogers Corporation in providing donations of substrate materials. REFERENCES [1] A. Penirschke and R. Jakoby, “Microwave mass flow detector for particulate solids based on spatial filtering velocimetry,” IEEE Trans. Microw. Theory Techn., vol. 56, no. 12, pp. 3193–3199, Dec. 2008.

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[2] P. Ratanadecho, K. Aoki, and M. Akahori, “A numerical and experimental investigation of the modeling of microwave heating for liquid layers using a rectangular wave guide (effects of natural convection and dielectric properties),” Appl. Math. Model., vol. 26, no. 3, pp. 449–472, 2002. [3] Y.-Z. Yin, “The cyclotron autoresonance maser with a large-orbit electron ring in a dielectric-loaded waveguide,” Int. J. Infrared Millim. Waves, vol. 14, no. 8, pp. 1587–1600, 1993. [4] R. K. Nubling and J. A. Harrington, “Hollow-waveguide delivery systems for high-power, industrial CO lasers,” Appl. Opt., vol. 35, no. 3, pp. 372–380, 1996. [5] P. J. B. Clarricoats and B. C. Taylor, “Evanescent and propagating modes of dielectric-loaded circular waveguide,” Proc. Inst. Elect. Eng., vol. 111, no. 12, pp. 1951–1956, Dec. 1964. [6] S. Hrabar, J. Bartolic, and Z. Sipus, “Waveguide miniaturization using uniaxial negative permeability metamaterial,” IEEE Trans. Antennas Propag., vol. 53, no. 1, pp. 110–119, Jan. 2005. [7] F. Y. Meng, Q. Wu, D. Erni, and L. W. Li, “Controllable metamaterialloaded waveguides supporting backward and forward waves,” IEEE Trans. Antennas Propag., vol. 59, no. 9, pp. 3400–3411, Sep. 2011. [8] J. G. Pollock and A. K. Iyer, “Below-cutoff propagation in metamaterial-lined circular waveguides,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 9, pp. 3169–3178, Sep. 2013. [9] J. G. Pollock, N. De Zanche, and A. K. Iyer, “Travelling wave MRI at field strengths using metamaterial liners,” in Proc. Int. Soc. lower Magn. Reson. Med., 2012, vol. 20, p. 2792. [10] A. Alu and N. Engheta, “Dielectric sensing in -near-zero narrow waveguide channels,” Phys. Rev. B, Condens. Matter, vol. 78, no. 4, 2008, Art. no. 045102. [11] Z. Duan, B. I. Wu, S. Xi, H. Chen, and M. Chen, “Research progress in reversed cherenkov radiation in double-negative metamaterials,” Progr. Electromagn. Res., vol. 90, pp. 75–87, 2009. [12] J. G. Pollock and A. K. Iyer, “Miniaturized circular-waveguide probe antennas using metamaterial liners,” IEEE Trans. Antennas Propag., vol. 63, no. 1, pp. 428–433, Jan. 2015. [13] D. Pratap, S. A. Ramakrishna, J. G. Pollock, and A. K. Iyer, “Anisotropic metamaterial optical fibers,” Opt. Exp., vol. 23, no. 7, pp. 9074–9085, Apr. 2015. [14] J. G. Pollock and A. K. Iyer, “Realization of -negative-near-zero metamaterial liners for circular waveguides,” in 4th Appl. Electron. Conf., Bhubaneswar, Orissa, India, Dec. 2013, pp. 99–100. [15] D. R. Smith and J. B. Pendry, “Homogenization of metamaterials by field averaging,” J. Opt. Soc. Amer. B, Opt. Phys., vol. 23, no. 3, pp. 391–403, 2006. [16] D. Smith, D. Vier, T. Koschny, and C. Soukoulis, “Electromagnetic parameter retrieval from inhomogeneous metamaterials,” Phys. Rev. E, Stat. Phys. Plasmas Fluids Relat. Interdiscip. Top. , vol. 71, no. 3, 2005, Art. no. 036617. [17] J. Elser, V. A. Podolskiy, I. Salakhutdinov, and I. Avrutsky, “Nonlocal effects in effective-medium response of nanolayered metamaterials,” Appl. Phys. Lett., vol. 90, no. 19, 2007, Art. no. 191109. [18] A. Alù, “First-principles homogenization theory for periodic metamaterials,” Phys. Rev. B, Condens. Matter, vol. 84, no. 7, pp. 075 153–075 154, 2011. [19] L. Novotny and C. Hafner, “Light propagation in a cylindrical waveguide with a complex, metallic, dielectric function,” Phys. Rev. E, Stat. Phys. Plasmas Fluids Relat. Interdiscip. Top., vol. 50, no. 5, pp. 4094–4106, 1994. [20] J. B. Pendry, A. J. Holden, W. J. Stewart, and I. Youngs, “Extremely low frequency plasmons in metallic mesostructures,” Phys. Rev. Lett., vol. 76, no. 25, pp. 4773–4776, 1996. [21] A. Demetriadou and J. Pendry, “Taming spatial dispersion in wire metamaterial,” J. Phys, Condens. Matter, vol. 20, no. 29, 2008, Art. no. 295222. [22] G. V. Eleftheriades, A. K. Iyer, and P. C. Kremer, “Planar negative refractive index media using periodically L–C loaded transmission lines,” IEEE Trans. Microw. Theory Techn., vol. 50, no. 12, pp. 2702–2712, Dec. 2002. [23] J. B. Pendry, A. J. Holden, D. Robbins, and W. Stewart, “Magnetism from conductors and enhanced nonlinear phenomena,” IEEE Trans. Microw. Theory Techn., vol. 47, no. 11, pp. 2075–2084, Nov. 1999.

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[24] G. V. Eleftheriades, O. Siddiqui, and A. K. Iyer, “Transmission line models for negative refractive index media and associated implementations without excess resonators,” IEEE Microw. Wireless Compon. Lett., vol. 13, no. 2, pp. 51–53, Feb. 2003. [25] H. Whiteside and R. King, “The loop antenna as a probe,” IEEE Trans. Antennas Propag., vol. AP-12, no. 3, pp. 291–297, Mar. 1964. [26] M. G. Silveirinha and N. Engheta, “Tunneling of electromagnetic energy through subwavelength channels and bends using -near-zero materials,” Phys. Rev. Lett., vol. 97, 2006, Art. no. 157403. [27] Q. Tang, F.-Y. Meng, Q. Wu, and J.-C. Lee, “A balanced composite backward and forward compact waveguide based on resonant metamaterials,” J. Appl. Phys., vol. 109, no. 7, 2011, Art. no. 07A319.

Justin G. Pollock (S’10) received the B.Sc. degree in electrical engineering (with distinction) from the University of Alberta, Edmonton, AB, Canada, in 2011, and is currently working toward the Ph.D. degree in electrical engineering (in both the Department of Electrical and Computer Engineering) at the University of Alberta. His current research interests include the study of RF, microwave, and terahertz propagation in bounded and unbounded media, fundamental electromagnetic theory, numerical methods in electromagnetics, and dispersion engineering of artificial materials for applications in imaging, security, sensing, and communication. Mr. Pollock currently serves as Chapter Treasurer for the IEEE Northern Canada Section Antennas and Propagation Society (AP-S) and Microwave Theory and Techniques Society (MTT-S) Joint Chapter. In 2013, he was the recipient of the IEEE MTT-S Graduate Fellowship, the Alberta Innovates Graduate Student Scholarship, the University of Alberta’s President’s Doctoral Prize of Distinction, and the Natural Sciences and Engineering Research Council (NSERC) of Canada Canadian Graduate Scholarship Doctoral Level. In 2011, he was the recipient of the IEEE MTT-S Undergraduate/Pre-Graduate Award and the IEEE AP-S Pre-Doctoral Research Award.

Ashwin K. Iyer (S’01–M’09–SM’14) received the BASc. (Hons.), MASc., and Ph.D. degrees in electrical engineering from the University of Toronto, Toronto, ON, Canada in 2001, 2003, and 2009 respectively. While with the University of Toronto, he was involved with the discovery and development of the negative-refractive-index transmission-line (NRI-TL) approach to metamaterial design and the realization of metamaterial lenses for free-space microwave subdiffraction imaging. He is currently an Associate Professor with the Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada, where he leads a team of graduate students in the investigation of novel RF/microwave circuits and techniques, fundamental electromagnetic theory, antennas, and engineered metamaterials, with an emphasis on their applications to microwave and optical devices, defense technologies, and biomedicine. He has coauthored a number of highly cited papers and four book chapters on the subject of metamaterials. Dr. Iyer currently serves as an Associate Editor for the IEEE TRANSACTIONS ON ANTENNAS AND PROPAGATION. He is Co-Chair of the IEEE Northern Canada Section’s Joint Chapter of the Antennas and Propagation Society (AP-S) and Microwave Theory and Techniques Society (MTT-S). He is a Registered Member of the Association of Professional Engineers and Geoscientists of Alberta (APEGA). He was the recipient of several awards, including the 2008 R. W. P. King Award and the 2015 Donald G. Dudley Jr. Undergraduate Teaching Award, both presented by the IEEE AP-S. His students were also recipients of several major national and international awards for their research.

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Identifying Multiple Reflections in DistributedLumped High-Frequency Structures Maral Zyari, Student Member, IEEE, and Yves Rolain, Fellow, IEEE

Abstract—A method for precise identification of reflections in mixed distributed-lumped high-frequency structures is proposed. The system structure that can be described by this model class is a cascade of transmission lines tapped by lumped elements. Here, multiple reflections are allowed to occur and they are identified. Reflections can be closely spaced and there is no restriction imposed by the model on the magnitude of the reflections. Note that most models in the literature are restricted to reflections with small magnitudes. Using a finite sum of delayed damped complex exponentials (Cisoids) to attain the initial delay values and modeling each reflection with a rational model allows to identify reflections with high values of magnitude. When applied on a measurement example, the method identifies all the reflections that are present, whereas the order of the model remains reasonably low. Index Terms—Cisoids, distributed lumped, multiple reflections, reflection identification.

I. INTRODUCTION

L

OCALIZING the reflections in a mixed transmission-line–lumped-elements structure has always been a noteworthy concern. Many methods such as time-domain reflectometry (TDR), frequency-domain reflectometry (FDR) [1], [2], time-gating methods [3], and identification of moderate reflections using transmissions and reflections measurements [4] have been proposed to localize the reflections and fully characterize the behavior of such structures. Most of these methods can only be applied under certain assumptions. The most common assumption is that the reflections must have small amplitudes [4], [5]. Other method-dependent restrictions are imposed like limitations on the structure of the terminations of the circuit [2]. When incident waves are traveling in these types of structures, they scatter at the junctions of the lumped elements. The measured reflected wave at the port of the system under test contains useful data about the type, size, and the position of the discontinuities. These discontinuities are then appearing as peaks in the reflectogram [5]. Necessity of identifying reflections is not just a concern limited to the

Manuscript received June 16, 2015; revised September 07, 2015 and January 20, 2016; accepted February 18, 2016. This work was supported by the Research Council of the Vrije Universiteit Brussel, by the Research Foundation Flanders (FWO-Vlaanderen), by the Flemish Government under Methusalem Fund METH1, and by the Belgian Federal Government under Interuniversity Attraction Poles Programme IAP VII. The authors are with the ELEC Department, Vrije Universiteit Brussel (VUB), Brussels 1050, Belgium (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2535301

high-frequency society as it is also vastly used in many other areas such as geophysics [6], mine-field detections [7], and civil engineering [8], [9]. In these areas, methods such as ground penetrating radars (GPRs) and super-resolution TDR are used to model the reflections while mainly identifying the positions of the reflections rather than complete shape of the echoes [9], [10]. These measurements are performed in the time domain. In this work, the measurements are done in the frequency domain. Measuring in the frequency domain has the advantage of having high-frequency resolution for the measurements over a very wide (50 GHz) bandwidth if necessary and a very high signal-to-noise ratio (SNR) (up to 90 dB) as the vector network analyzer (VNA) measures one frequency at a time. To obtain a similar resolution and SNR in the time domain, a very fast and very accurate sampling with huge buffer length is needed, which is not easy to achieve and practically restricts the SNR and complicates the calibration of the setup. This means that the accuracy of the measurements performed in the frequency domain is higher than the ones performed in the time domain. As for this work, we seek a complete signal model, this is a big advantage. One more difference is that in the method of this paper we are working with continuous time data rather than the discrete time data. In general, conventional TDR methods that aim at a full signal model are not able to account for the reflected signal components due to multiple reflections that occur when the magnitude of the reflection is large [1]. Besides, considering other methods such as time gating, the full signal cannot be modeled at once as the reflections should be gated and modeled separately. Applying time gating would not go smooth notably in the cases that the dispersion of the signal is high, as distinguishing between the reflections will not be easy. Hence, the proposed method in this paper has the advantage of modeling the full signal in one step even if a significant level of dispersion is present. In this work a model is proposed that enables one to localize and separate also closely spaced large reflections. There is no need here to assume that the magnitude of the reflections is moderate or small, as it will be shown that the model is capable of offering a precise estimate of the reflection with a high magnitude of the lumped reflection factor of up to 0.9. The modeling procedure starts by approximating the system reflections by a finite sum of delayed damped complex exponentials (Cisoids). In the next step, the delays as obtained in the first step enable the extraction of a full rational model with multiple delays. This results in an accurate estimation of the reflections. However, there is a cost to this approach too. Since the multiple reflections are allowed to occur, the one-to-one relationship between the physical structure of the network and the shape of the reflectogram is lost. The reflectogram will look identical for

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For a single reflection, the system can be described in the time and frequency domains as (1) (2) Fig. 1. Schematic of a general structure that can be modeled using the proposed model. The circuit is formed by cascaded of transmission lines tapped by lumped elements. The multiple reflections are illustrated. This happens when the incident wave traveling through the system reflects back and forth. and are incident and reflected waves.

a set of two detectable small reflections and one big reflection leading to multiple reflections on the line. The other concern that should be taken care of is the bandwidth of the measurement, as it should be sufficient to cover the bandwidth of the transmission line to be modeled. The proposed model is introduced in Section II, next the noise model is discussed in Section III and the analysis and processing of the noise are shown. To estimate the model accurately, an estimator is chosen in Section IV. The initial values for the parameters of the model also influence the precision of the estimation of the model. Therefore, the procedure of finding the proper initial values for the parameters is explained in Section V. In Section VI, the proposed method is applied on simulation and measurement examples to show that the model is capable of identifying small and large reflections in simulation and real life. The results are illustrated and discussed.

II. MODEL The proposed model is applicable when dealing with mixed distributed-lumped system structures where the lumped elements are the sources of the reflections. A general schematic diagram of the studied structure is depicted in Fig. 1. In the case of moderate and big reflections (when the magnitude of the reflection becomes equal or bigger than 0.2), multiple reflections can occur. Multiple reflections in high-frequency structures occur when a source of discontinuity or a mismatch causes the incident wave traveling through the system to reflect off towards the source. If this backward reflected signal is reflected forward again it will become an interfering reflected signal. This signal is smaller in amplitude, and delayed in time with an additional phase shift compare to the original incident wave [11]. An example of multiple reflection is illustrated in Fig. 1, where the incident and reflected waves are also depicted. In this work, multiple reflections are not ruled out by assumptions and their effect is not eliminated, but rather identified. The complete impulse response of the system consists of delayed impulse responses, where the reflections appear as the delayed echoes and the delays are caused by the transmission lines. In order to model a system consisting of a cascade of transmission lines tapped with lumped elements, a model that mimics the echoes present in the system’s impulse response is proposed.

with and being the output and input waves, respectively, being the delay introduced by the transmission lines, being is the impulse response of the system in the time domain, and being the frequency response function (FRF) of the system. A model for is introduced next that describes the mixed distributed-lumped nature of the system in the case of multiple reflections, (3) (4) This is an FRF model where is the number of the delays to be estimated and represents the reflections introduced by the lumped part of the system. is a rational model defined as (5) and are the numerator and the denominator of the where th rational model, respectively. The FRF of the wave response of the system is measured. When working at high frequencies, the wave FRF of the system is known as S-parameters and is defined as the ratio of the input–output wave spectra (6) This FRF of a lumped system can be approximated arbitrarily well by a rational form of finite order over a finite frequency band because the transcendental ratio of wave spectra is a meromorphic complex function [12]. The rational form (5) becomes (7) with the and numerator and denominator of the rational model associated to reflection . Here we are just focusing on the modeling of one single S-parameter. In identification terms, this is single-input single-output (SISO) linear system. A generalized model extension for a multiple-input multiple-output (MIMO) system using the same method is possible. III. NOISE MODEL In all practical applications, we have to deal with measurement noise. To be able to fully characterize the stochastic behavior of the measurement, prior knowledge about the probability density function (PDF) of the noise is required. As we consider that measurements of the S-parameters are taken, the

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Fig. 2. Schematic of the measurement setup to obtain the connection repeatability error. Reconnection implies connecting, measuring, and then disconnecting the DUT. During each measurement a new data set is obtained.

noise properties are determined directly on the S-parameters itself. However, we also know that a VNA measures waves and calculates the S-parameters as a ratio. Theoretically speaking, this means that the mean value and the standard deviation (STD) of the S-parameter do not exist when Gaussian noise is present on the measured wave spectra because of its infinite tails. This topic was investigated in detail in [13] and as soon as the SNR of the wave measurement is in excess of 10 dB, the moments of the S-parameters can safely be assumed to exist and the PDF to be Gaussian. It is, hence, sufficient to know the variance of the noise over frequency to characterize the noise perturbations of the measurements. In this framework we have the incorporate prior knowledge of the noise on the S-parameters in our estimation. Two different noise and error sources are considered. The first one is the measurement noise discussed above, the other is the connection repeatability error. The latter is caused by connecting the device-under-test (DUT) to the measurement device. The schematic of the measurement setup to measure the reconnection error is illustrated in Fig. 2. To reduce the measurement noise, the resolution bandwidth of the measurement device is set to 100 Hz. The lowest possible resolution bandwidth of the device is 1 Hz, but to limit the measurement time and obtain a good SNR simultaneously, a value of 100 Hz is chosen as an adequate compromise for the following measurements. When dealing with the measurement noise, it is assumed that the real and imaginary part of the measured signal ( ) at each frequency have an equal are uncorrelated. The correlation of the measurements in between the frequencies can then be neglected. As the measurement device (VNA) is today equipped with a fully digital IF system, it is very likely to use a discrete Fourier transform (DFT) based measurement. For spectra obtained by a DFT, these noise assumptions are met asymptotically for the number of measurement samples tending to infinity [14]. It worth noting that the calibration residuals are being neglected as they are assumed to be sufficiently low compared to the measured S-parameters. For the connection repeatability error, a correlation over the frequency is expected to be present. The real and imaginary parts of the measured reconnection variability for 20 measurements after reconnection at one frequency (4 GHz) are shown in Fig. 3. The absence of a clear preferential direction in and the similar size of the spread of the reflection factor supports uncorrelated equally distributed connection repeatability errors. The covariance matrix of the connection repeatability error over the fre-

Fig. 3. Real and imaginary parts of the measured complex reflection factor at 4 GHz for 20 reconnections. The reflection factor has no dimension.

quency then becomes a dense weighting matrix. An estimator that takes this correlation into account is a full square matrix with a size equal to number of frequencies rather than the diagonal matrix used here and leading to the simplified form of the estimator (8) as a single sum over the frequency. Considering this estimator will render the calculations much more complex and calculation time will hence increase significantly. Here we assume that the off-diagonal elements of the matrix are negligible. This hypothesis appears to be acceptable as the result of the estimated signal model turns out to be quite precise, as will be shown later in the paper. In general, violating the assumption will result in an increase of variability of the estimates. The sequel of that is that the estimate become suboptimal and may have a variability that exceeds the minimally attainable bound (Cramér Rao lower bound) [14]. The exact standard deviation (STD) of the noise is not available here as prior knowledge. A measured estimate of the variance will be obtained instead. As the sample variance over a set of repeated measurements can be evaluated, this is used as an estimate. The measurement noise is obtained over the frequency by repeating the measurement 50 times without reconnection and calculating the STD. The sample STD is shown in Fig. 4(b). In order to measure the connection repeatability error, the DUT is connected to the VNA, the measurement is performed, and then the DUT is disconnected. This procedure is repeated 20 times to obtain 20 data sets. The STD of these reconnected measurements is shown in Fig. 4(a). We expect the connection repeatability error to be an order of magnitude larger than the measurement noise [15]. Comparing the STD of connection repeatability error and measurement noise (Fig. 4) shows that the connection repeatability error is a few dB bigger than the measurement noise. Hence, the measurement noise may still be used as an estimate of the uncertainty of the measurement. To wrap up, it is assumed that the measurement noise and the reconnection noise are circular complex Gaussian and independent over frequency here with zero mean and the STD of . IV. ESTIMATOR A. Maximum Likelihood Estimator We choose an estimator for the parameters based on the available statistical properties of the measured data. The max-

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MLE. It can be shown that the SMLE is still consistent, but that there is a small loss in the efficiency [17]. In layman terms, this means that adding measurements will lead to parameter values that get closer to the real value, but that the spread of these estimation parameters will slightly increase above the minimum attainable variance. V. INITIAL VALUES AND THE NONLINEAR OPTIMIZATION OF THE FINAL MODEL

Fig. 4. STD of the reflection factor over frequency for: (a) connection repeatability error for 20 reconnections and (b) measurement noise for 50 repeated measurements. This shows that the connection repeatability error is a few dB larger than the measurement noise.

imum likelihood estimator (MLE) is a good candidate as it has good statistical properties: it is asymptotically efficient, consistent, and meanwhile provides a framework that can includes the available knowledge about the distortion in the estimation. The cost function is defined as (8) is the variance of output error. The prior knowlwhere edge of the sample variance of the noise available as discussed in Section III replaces . The sample maximum likelihood estimator (SMLE) results. This still has most of the good properties of the MLE and it can profit from the prior knowledge to improve the estimation. B. SMLE The SMLE is a logical choice as it weighs S-parameters measurement with its uncertainty [14]. Using SMLE, we can get an estimate of the model parameters. The sample likelihood estimator differs from the likelihood estimator. In this case the cost function is defined as (9) where represents the sample of the noise variance over the repeated measurements, as explained in Section III, and it is defined as [16]

(10) with , where represents the number of repeated measurements, and is 20 in this particular case. In this cost function (9), the uncertainty on the measurements plays the role of weighting for the equation error. An important concern is the stochastic quality of the SML estimator with respect to the

It is a well-known issue that linearity in the parameters is very important in estimation of the models, as it has a strong impact on the complexity of the estimator [14]. If we have a linear least squares (LLSs) problem there is no need to have initial values for parameters to start up the estimation because the estimation results in a convex minimization problem. However, here the model is nonlinear in the parameters [see (7)]. The cost function is therefore a non-convex problem to solve. The Levenberg–Marquardt algorithm is chosen as the nonlinear optimization method to solve the nonlinear least squares problem. This iterative algorithm behaves like a gradient descent method and when the solution is close to a local minima, it behaves like a Gauss–Newton method. In both cases the convergence is guaranteed, but it has a slow and a fast convergence for gradient descent and the Gauss–Newton method, respectively [18]. Proper initial values for the parameters are required. Therefore, linearization of the cost function behavior with respect to the parameters is needed to obtain a convex cost function that can be solved conveniently. The linearization is needed as a systematic approach to attain starting values that are sufficiently close to the true values to start the final nonlinear optimization. Considering (7) initial values for both the delays and the coefficients of the polynomials ( and ) are needed. The way to obtain these values is explained in detail in this section. A. Initial Values for the Delays To start up the optimization of the SMLE cost function (9) we need to have the proper initial values. For the delays the best is to find a model that imitates the behavior of the system, which is a sum of impulse responses with different delays and amplitudes, and further leads to a self-starting method. Looking into the literature, we propose to use a sum of delayed damped complex exponentials (Cisoids). The superposition of Cisoids resembles a sum of delayed simplified impulse responses. Cisoids have been successfully used to model tapped delay lines, but under two significant assumptions. First, the reflections must be small in magnitude (less than 0.3). Second, the discontinuities are required to be distinguishable and have a certain minimum separation distance [2]. This work extends what exists in the literature and demonstrates it is possible to have an accurate estimation with Cisoids despite disobeying the first assumption. Reflections with a high magnitude (even up to 0.9) can be estimated precisely. This is done at the price of an increase in the complexity of the model and likewise an increase in the order of the model. The time resolution is best set to a high enough value not to miss the delays that are placed close to each other. Delayed echoes can be estimated individually [2]. The measured reflection coefficient is modeled with modulated cisoids as [5]

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(11) is the real-valued amplitude parameter of each cisoid, is a complex-valued modulation function that describes the nature of each discontinuity, is the complex frequency-dependent propagation constant, and is the electrical length of the transmission lines. In this work the modulation function is defined as a second-order model to start with

where

Fig. 5. Schematic of the simulated structure. The circuit is formed by three cascaded transmission lines with different lengths tapped by lumped elements. and transmission lines are illustrated as . Lumped elements are shown as In this simulation example, the lumped elements are inductors.

(12) Increasing the order model of the modulation function, more complex reflections are possible and this is an advantage compared to what exists in the literature. Using cisoids in the current state-of-the-art, the type of the discontinuities (as the source of the reflections) is limited to certain value of order 1. It is shown in Section VI that using the initial delay values obtained by cisoids, precise estimates can be achieved. B. Initial Values for the Coefficients of the Polynomials As is already shown in (7) the proposed model is nonlinear in parameters. The expanded model is defined as (13) To linearize the model with respect to denominator parameters, it is assumed that the FRF has a common denominator for each reflection, where the common denominator is (14) then (13) becomes (15) as the common denominator contains the poles of all the sub-models. This means an increase in the order of the model, which is a price to pay to have a model linearized in the parameters in order to obtain proper initial values. Note that the initial values for the delays are obtained in the previous step and therefore they are fixed in this step. The model in now linearized in the parameters of and , which allows to obtain initial parameter values with a LLS estimator.

Fig. 6. Dimensionless impulse response of the simulation example circuit. Three reflections are to be identified, which are located at time samples of 11, 121, and 300. The dashed lines show the positions of the estimated delays. The absolute value of the estimation error is shown in the time domain. The error is shown close to the reflections. The level of the error is at the level of MATLAB precision.

of the delays to three. The FRF is simulated first in the frequency domain and then is converted to the time domain. The resulting impulse response is shown in Fig. 6. As expected there are three main reflections located at the exact delays of 11, 121, and 300 samples. To start with the estimation, the number of the delays to be estimated is set to three in the model and the order of the numerator and denominator in the rational model is set to two. The estimated delays obtained from the final optimized model are shown in Fig. 6 on top of the impulse response of the system. The error of the estimated model is illustrated in Fig. 6 in the time domain around the reflections. The error is defined as (16)

VI. EXAMPLES A. A Simulation Example A circuit formed by three transmission lines tapped by three lumped elements is used to show that the proposed model is indeed able to estimate the parameters accurately. In this structure, the reflections are introduced by the lumped elements, which are inductors in this example, and the ideal transmission lines impose only a delay in the traveling waves. Hence, the simulated structure is in the model class used by the estimators. A schematic diagram of the example structure to be modeled is illustrated in Fig. 5. Having three lumped elements, three reflections are expected and three transmission lines sets the number

Observing the range of the vertical axis of the error in Fig. 6 shows that the level of the error is extremely low and it is approximately at the level of MATLAB precision. B. Measurement Example As a practical application of the introduced estimator, a wideband electromechanical slide screw impedance tuner is identified to check the validity of the proposed estimator in the presence of nonidealities. Here the system does not follow the model class completely. For this purpose, a focus tuner is used as the DUT [19]. One probe of this four harmonic impedance tuner is

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Fig. 7. Dimensionless impulse response of the measurement example. Three reflections are to be identified. The position of the estimated delays are illustrated by dashed lines. The magnitude of the reflection is 0.1. The absolute value of the estimation error is shown in the time domain. The error is shown close to the reflections.

used to generate a lumped perturbations along the line. This results in a setup that approximates the model class well. Two-port measurements of the tuner are performed for different vertical positions of the probe as the vertical movement of the probe generates reflections with different magnitudes. The waves traveling through the tuner are measured by a VNA. The measurement setup is shown in Fig. 9. The scattering matrix of the DUT is obtained from the measured waves, while measurements are performed between 1 and 9 GHz with a frequency resolution of 2 MHz by an Agilent E8364B VNA. The VNA was calibrated using an electronic calibration module (Agilent ECal N4693–60002) for the frequency band of interest. Here we are just considering a SISO model so, in the scattering matrix, only is considered. Two sets of measurements for different values of the lumped reflections are discussed here to show that using the proposed model all types of reflections (“big” up to 0.9 and “small” low as 0.1 in the magnitude) can be estimated precisely. The measured frequency data is converted to the time domain using the fast Fourier transform (FFT) and the data is shown in the time domain to expose the reflections. First the probe is positioned to create a reflection with a small magnitude of 0.1. The measured time-domain data is shown in Fig. 7. In this figure, three small reflections are recognizable. The order of the rational model is set to two for both the numerator and denominator and the number of delays to be estimated is set to three. The estimated delays are also shown in Fig. 7. The error (16) of the estimation in the time domain around the reflections is shown in Fig. 7. In this case, the relative root mean square (rms) error is 57% . This relative rms error is calculated as (17)

Fig. 8. Dimensionless impulse response of the measurement example. Three reflections are to be identified. The limitation on the vertical axis is different from the Fig. 7. Note the two small reflections, which are estimated along the main reflection. Positions of the 12 estimated delays are illustrated by dashed lines. Here the magnitude of the reflection is 0.9. The absolute value of the estimation error is shown in the time domain. The error is shown close to the reflections for both small reflections and the big reflection.

Fig. 9. Measurement setup used for the measurements examples of this paper. The VNA is used to measure the FRF of the tuner.

with being the number of points of the signal. Fig. 8 illustrates the measurement result when the probe is closer to the center conductor of the tuner, hence the magnitude of the reflection is 0.9. There are again three reflections to be identified. It is clear that the main reflection is larger in magnitude compared to the result shown in Fig. 7. The price to pay when a big reflection is to be estimated is that the number of the delays to be estimated in the model increases. This is due to complexity of the main reflection, which is expanded into multiple small reflections. Thus, more delays are devoted to estimate the main reflection in order to have an accurate estimation. For the estimation of the reflection with a high magnitude of 0.9, the order of the model is set to 3 for the numerators and denominators and the number of delays to be estimated is set to 12. These 12 estimated delays are shown in Fig. 8. It is seen that most of the delays are devoted to estimate the complex main reflection. The

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absolute value of the error is illustrated in Fig. 8 in the time domain. The error is shown around the three reflections. The relative rms error (17) for this case is 22.09%. Compared to what exists in the literature, the proposed model has the advantage of estimating large reflections (even up to 0.9), as well as small reflections (as low as 0.1) at the price of increasing the number of delays, while the order of the model remains fairly low (three for the large reflection).

VII. CONCLUSIONS A new algorithm for the identification of multiple delayed echoes in a mixed distributed-lumped structure operating at high frequencies has been proposed. The method has the advantage of identifying reflections with high magnitude (up to 0.9) using an SMLE. The modeling strategy is based on using a finite sum of delayed damped complex exponentials (Cisoids) to obtain the initial values for the delays in the first step. Each of the echoes is then modeled with a rational model. When applied to a measurement example, the order of the model remains reasonably low even for modeling large reflections in the price of devoting more delays to be able to estimate the complex reflections accurately.

ACKNOWLEDGMENT The authors would like to thank Dr. C. Tsironis and Focus Microwaves for providing the equipment that was used for the measurements of this paper.

REFERENCES [1] C.-W. Hsue and T.-W. Pan, “Reconstruction of nonuniform transmission lines from time-domain reflectometry,” IEEE Trans. Microw. Theory and Techn., vol. 45, no. 1, pp. 32–38, Jan. 1997. [2] H. van Hamme, “High resolution frequency-domain reflectometry,” IEEE Trans. Instrum. Meas., vol. 39, no. 2, pp. 369–375, Apr. 1990. [3] J. Dunsmore, N. Cheng, and Y.-x. Zhang, “Characterizations of asymmetric fixtures with a two-gate approach,” in IEEE Microw. Meas. Conf., Jun. 2011, pp. 1–6. [4] T. V. Veijola and M. E. Valtonen, “Identification of cascaded microwave circuits with moderate reflections using reflection and transmission measurements,” IEEE Trans. Microw. Theory Techn., vol. 36, no. 2, pp. 418–423, Feb. 1988. [5] H. van Hamme, “High-resolution frequency-domain reflectometry by estimation of modulated superimposed complex sinusoids,” IEEE Trans. Instrum. Meas., vol. 41, no. 6, pp. 762–767, Dec. 1992. [6] R. L. Van Dam and W. Schlager, “Identifying causes of ground-penetrating radar reflections using time-domain reflectometry and sedimentological analyses,” Sedimentology, vol. 47, no. 2, pp. 435–449, Apr. 2000. [7] L. Carin, N. Geng, M. McClure, J. Sichina, and L. Nguyen, “Ultrawide-band synthetic-aperture radar for mine-field detection,” IEEE Antennas Propag. Mag., vol. 41, no. 1, pp. 18–33, Feb. 1999.

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[8] U. Spagnolini and V. Rampa, “Multitarget detection/tracking for monostatic ground penetrating radar: Application to pavement profiling,” IEEE Trans. Geosci. Remote Sens., vol. 37, no. 1, pp. 383–394, Jan. 1999. [9] C. Le Bastard, V. Baltazart, Y. Wang, and J. Saillard, “Thin-pavement thickness estimation using GPR with high-resolution and superresolution methods,” IEEE Trans. Geosci. Remote Sens., vol. 45, no. 8, pp. 2511–2519, Sep. 2007. [10] H. Xing et al., “GPR reflection position identification by STFT,” in IEEE Int. Ground Penetrating Radar Conf., Jun. 2004, vol. 1, pp. 311–314. [11] F. Ascarrunz, T. Parker, and S. Jefferts, “Pseudo-random code correlator timing errors due to multiple reflections in transmission lines,” DTIC, Reston, VA, USA, DTIC Doc. Tech. Rep, Dec. 1998. [12] P. Henrici, Applied and Computational Complex Analysis, Discrete Fourier Analysis, Cauchy Integrals, Construction of Conformal Maps, Univalent Functions. New York, NY, USA: Wiley, 1993, vol. 3. [13] R. Pintelon, Y. Rolain, and W. Van Moer, “Probability density function for frequency response function measurements using periodic signals,” in IEEE Instrum. Meas. Technol. Conf., 2002, vol. 2, pp. 869–874. [14] R. Pintelon and J. Schoukens, System Identification: A Frequency Domain Approach. New York, NY, USA: Wiley, 2012. [15] S. S. Agili, A. W. Morales, J. Li, and M. Resso, “Finding the probability distribution functions of S-parameters and their Monte Carlo simulation,” IEEE Trans. Instrum. Meas., vol. 61, no. 11, pp. 2993–3002, Nov. 2012. [16] T. Söderström, M. Hong, J. Schoukens, and R. Pintelon, “Accuracy analysis of time domain maximum likelihood method and sample maximum likelihood method for errors-in-variables and output error identification,” Automatica, vol. 46, no. 4, pp. 721–727, Apr. 2010. [17] M. Van Berkel, G. Vandersteen, E. Geerardyn, R. Pintelon, H. Zwart, and M. De Baar, “Frequency domain sample maximum likelihood estimation for spatially dependent parameter estimation in PDEs,” Automatica, vol. 50, no. 8, pp. 2113–2119, Aug. 2014. [18] R. Fletcher, Practical Methods of Optimization. New York, NY, USA: Wiley, 2013. [19] C. Tsironis, B. Hosein, R. Jallad, and J. Slanik, “A four harmonic wideband impedance tuner,” in IEEE Asia–Pacific Microw. Conf., Dec. 2009, pp. 1727–1730. Maral Zyari (GSM’14) was born in Tehran, Iran, in 1986. She received the Master’s degree of Engineering in electronics and information processing Vrije Universiteit Brussel (VUB), Brussels, Belgium, in 2013, and is currently working toward the Ph.D. degree at VUB. Since September 2013, she has been with the ELEC Department, VUB. Her research interests include RF circuit design, measurement, and modeling of high-frequency measurement equipment.

Yves Rolain (M’90–SM’96–F’06) received the Burgerlijk Ingenieur in electrical engineering degree, Master’s degree in computer sciences, and Doctor’s degree in applied sciences from the Vrije Universiteit Brussel (VUB), Brussels, Belgium, in 1984, 1986, and 1993), respectively. He currently teaches high-frequency electronics and electrical measurement techniques with the Engineering Faculty, ELEC Department, VUB. His main research interests are nonlinear microwave measurements, applied digital signal processing, and parameter estimation/system identification. Dr. Rolain was the recipient of the 2005 IEEE Instrumentation and Measurement Society Award.

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Multi-Way Lossless Outphasing System Based on an All-Transmission-Line Combiner Taylor W. Barton, Member, IEEE, Alexander S. Jurkov, Student Member, IEEE, Prathamesh H. Pednekar, Student Member, IEEE, and David J. Perreault, Fellow, IEEE

Abstract—A lossless power-combining network comprising cascaded transmission-line segments in a tree structure is introduced for a multi-way outphasing architecture. This architecture addresses the suboptimal loading conditions in Chireix outphasing transmitters while offering a compact and microwave-friendly implementation compared to previous techniques. In the proposed system, four saturated power amplifiers (PAs) interact through an all-TL power-combining network to produce nearly ideal resistive load modulation of the branch PAs over a 10:1 range of output powers. This work focuses on the operation of the combining network, deriving analytical expressions for input-port admittance characteristics and an outphasing control strategy to modulate output power while minimizing reactive loading of the saturated branch amplifiers. A methodology for combiner design is given, along with a combiner design example for compact layout. An experimental four-way outphasing amplifier system operating at 2.14 GHz demonstrates the technique with greater than 60% drain efficiency for an output power range of 6.2 dB. The system demonstrates a W-CDMA modulated signal with a 9.15-dB peak-to-average power ratio with 54.5% average modulated efficiency at 41.1-dBm average output power. Index Terms—Base stations, Chireix, LINC, load modulation, outphasing, power amplifier (PA), wideband code division multiple access (W-CDMA).

I. INTRODUCTION

P

OWER amplifiers (PAs) are often required to provide wide-range dynamic output power control while maintaining high efficiency. The requirement of efficiency over a wide range of power levels is at odds with the dominant characteristics of most classes of PAs, which tend to have peak efficiency only under highly saturated peak output power operation. In order to maintain high efficiency over a wide dynamic range, then, a promising approach is to exploit the saturated efficiency characteristic by continuing to operate in a saturated mode even as output power is modulated. Output power of a saturated PA can be controlled for example by modulating either the drain terminal, as in polar and envelope-tracking

Manuscript received February 23, 2015; revised June 26, 2015, January 02, 2016, and January 09, 2016; accepted February 12, 2016. T. W. Barton and P. H. Pednekar are with the Department of Electrical Engineering, The University of Texas at Dallas, Dallas, TX 75080 USA (e-mail: [email protected]; [email protected]). A. S. Jurkov and D. J. Perreault are with the Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA 02139 USA (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2531691

techniques [1]–[3], modulation of the effective load impedance as in Doherty [4]–[6], outphasing [7]–[38], or direct load modulation [39]–[41] architectures, or through a combination of these approaches [42], [43]. In principle, the average modulated efficiency of these techniques is directly related to the extent to which saturated operation can be maintained. Of these architectures, therefore, outphasing with saturated PAs (or, in the ideal limit, switched-mode PAs) may represent the most readily achievable path to high efficiency over a wide power range, due to the wide operating range over which the multiple branch PAs can operate in saturation. The outphasing approach employs phase-shift control of multiple branch amplifiers to modulate the power delivered to the load. When realized with a lossless power-combining network [7]–[31], the branch PAs interact such that variations in their relative phases modulate the effective loading impedances, enabling phase control of overall system output power. This technique is able to realize a wide dynamic range over which all branch PAs remain in an efficient saturated mode of operation. A significant limitation in traditional approaches to outphasing, including in its original formulation proposed in the 1930s [7], is the substantial variation in the reactive component of the branch PAs’ loading impedance that occurs across the outphasing range. This is an undesirable byproduct of the outphasing and power-combining mechanism (which controls output power through modulation of the real component of the branch PA loading impedances). Subjecting the branch PAs to variable reactive loading tends to degrade efficiency performance due to both the sensitivity to loading conditions exhibited by most RF amplifiers (including switched-mode RF PAs), and added conduction losses associated with the reactive currents [17]. In order to address the suboptimal loading conditions of conventional outphasing formulations, a multi-way power-combining and outphasing amplifier has been introduced that provides branch PA loading conditions that are almost entirely resistive over a wide output power range [8], [9]. Four-way implementations of this approach have been demonstrated using all lumped elements in a tree structure [9], [10], and by incorporating microstrip lines with ground-referenced shunt reactive elements [11], [12]. In [12], it was shown that these various realizations of the multi-way combining approach could be related through network transformations and shown to have identical theoretical port relationships. The preferred implementation for a particular application will therefore depend on power level and carrier frequency, and availability of appropriate passive components.

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Fig. 1. Diagram of the four-way power-combining network based on TL elements. The phase relationship among the four inputs to the PAs are also shown. The ideal voltage sources represent the four-branch PAs.

This work introduces a multi-way non-isolating power-combining structure composed of transmission-line (TL) sections connected in a tree structure. By using only power-path TLs, this structure eliminates the need for reactive elements, reducing parasitic effects due to ground return paths and allowing for more compact layout compared to the radial stub implementation in [12]. The proposed outphasing system is broadly related to those in [8]–[12], although it cannot be directly derived from them and has very different design and control considerations. The proposed approach shares the benefits of power-combining techniques based on non-isolating TL combiners [20], [26], [44], [45] while significantly reducing the reactive loading of the PAs. This paper expands on the preliminary demonstration of this approach in [46] with a complete theoretical analysis of the TL-combining network. This work introduces the derivation of the input-port admittance characteristics and outphasing control strategies. We discuss the reasoning for the choice of base electrical length in the combiner design, and show a compact layout of the approach. Section II presents the underlying theory for the proposed approach, including derivation of the input-port impedance and output power control characteristics of the multi-way TL combining network, development of and a network design methodology. Section III presents two design examples of the network used in simulation-based and experimental validation of the approach. The remaining system components and experimental validation results of the four-way 2.14-GHz prototype are described in Section IV. Section V concludes this paper. II. THEORY The four-way TL-based power-combining network is shown in Fig. 1. Eight-way and higher order versions can be realized by extension of the techniques described in this work, but we have selected the four-branch version as having a balance of improved PA loading conditions and broad usefulness. As indicated in Fig. 1, the characteristic impedances of the branch TLs are and , respectively. Each TL pair has a base length with a specified offset ( or ) from that base length. In other words, the TL lengths are chosen to have a increment/decrement in length from the base length. Although an arbitrary base

length is possible, the base length is chosen here to be a quarteror half-wavelength, as this allows for symmetric length increments and simplifies the combiner analysis. Practical considerations for selecting the base TL length are discussed in Section III. Throughout the following analysis we will assume that the four-branch PAs operate as ideal voltage sources, as this is the ideal condition for outphasing systems [32]. In practice, candidate PA classes for implementation include those producing a constant output voltage amplitude independent of input amplitude; e.g., class-E, saturated class-B, or class-F amplifiers. We also make the simplifying assumption that the PA operating efficiency is directly proportional to the power factor of its effective loading impedance, as shown in [8], for ideal saturated class-B PAs. As a result, this work seeks to maximize efficiency by minimizing the reactive component of the loading seen by the branch PAs. It is also noted that some types of switching amplifiers (including class-E amplifiers) can be designed to work well across variable resistive loads, as described, for example, in [28] and [47]. A consequence of this design goal is that the matching among the loading conditions of all four PAs is maximized. We note that if an alternate loading trajectory provides improved efficiency for a practical branch PA, the resistive loading trajectory presented in this work could be transformed in such a way that all four-branch PAs operate as closely to that desired trajectory as possible. A. Input-Port Admittance Characteristics Understanding the input-port admittance characteristics of the TL combiner of Fig. 1 is important for its design and analysis. In other words, it is of interest to the designer to know how the effective loading of the PAs (due to the combiner) changes with outphasing. One convenient approach for determining these characteristics is to first describe the TL combiner with a multi-port admittance matrix relating the combiner input-port voltages to its respective input-port currents. Such a matrix captures the behavior of the combiner and allows one to easily derive the effective PA loading at any of the combiner input ports for an arbitrary set of PA outphasing angles. In the case of the four-way combiner of Fig. 1, this reduces to a four-port admittance matrix relating the four input-port voltages to the respective input-port currents. Note that one can also describe the four-way combiner with a five-port admittance matrix, where the fifth port corresponds to the combiner’s output port. In the following theoretical discussion, however, we choose to treat the output port along with its terminating load as part of the combiner network, as it requires considerably less algebraic manipulation to arrive at the result. To derive the admittance matrix of the four-way combiner, consider first the three-port network of Fig. 2. Both lines have impedance and their base length can be selected as an integer multiple of a quarter wavelength. Furthermore, an integer number of half-wavelengths may be added to without changing the port characteristics. This three-port network of Fig. 2 can be thought of as a fundamental building block of multi-port TL combiners such as the one in Fig. 1. Conventional TL analysis methods can be employed to show that the port voltages and currents for the three-port network of

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two-way combiner with half-wavelength base length, where and , (3)

Fig. 2. Three-port network that represents a fundamental building block of the TL-based combiner of Fig. 1. The two TLs each have a characteristic impedance and a base line length , which may be selected as an integer multiple of a quarter wavelength.

Furthermore, if one assumes that the PAs driving the two-way combiner are outphased according to the phasor diagram in Fig. 3, and the combiner input-port voltages have identical magnitude (at the operating frequency at which the combiner is designed to operate), then (3) can be solved to yield the effective combiner input admittances and , i.e., the admittance that each of the PAs sees looking into the combiner with all sources being active. It can be shown that and are complex conjugate pairs and are given by (4), where ,

(4)

Fig. 3. TL implementation of a two-way power combiner, showing the phase and . The base length is serelationship of the input port voltages lected as an integer multiple of a quarter wavelength. The characteristic line and the length increment are design parameters. is the efimpedance fective load as seen by the combiner and includes the effect of any additional impedance transformation stages.

Fig. 2 with a half-wavelength base line length related according to (1), where and the admittance matrix of the three-port network

are denotes

(1) This admittance matrix can be employed in deriving the input-port admittance characteristics for multi-port TL combiners. For example, consider the two-way TL combiner of Fig. 3 driving a load , in which the branch PAs are treated as ideal voltage sources and . The sources are outphased as illustrated in the phasor diagram of Fig. 3. We can express the port voltages and currents using the matrix representation given by (2), where is the admittance matrix (1) for the three-port network of Fig. 2, (2) Solving (2) yields the relationship between the input-port voltand and currents and given by (3) for the ages

It can be shown for the two-way combiner of Fig. 3 that, for a given PA output amplitude , maximum power is delivered to the load when and are 180 out-of-phase, i.e., . Interestingly, as can be seen from the admittance matrix (1) of this combining network, the load current is independent of and is only a function of the input port voltages and the length of the TLs. This suggests that one can also regard the two-way combining network as an impedance transformation network with a differential input and a single-ended output that converts a differential input voltage to an output current according to (1). This network acts as a differential-input single-ended-output immittance converter in that it converts an input voltage to an output current (or an input current to an output voltage). In this regard it is similar to other impedance transformation networks such as the well-known quarter-wavelength transformer and its equivalent lumped-element counterparts [48]. Similar to other impedance transformation networks, the power loss exhibited by the network in Fig. 3 (owing to parasitic resistance, dielectric loss, etc.) also increases with the impedance transformation ratio. An approach analogous to the one used for the two-way combiner can be employed for deriving the input-port characteristic of the four-way TL combiner. Consider Fig. 4 representing the four-way combiner of Fig. 1 as a cascade of three-port networks, each with its respective admittance matrix and . The node voltages and branch currents along with the load voltage and current can be related according the linear system of (5a)–(5d), which can, in turn, be solved to yield the input-port admittance matrix for the four-way combiner with a half-wavelength line base length as given by (6), where , , , and , (5a)

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(6e)

Fig. 4. TL-based four-way power combiner of Fig. 1 represented as a cascade of the three-port networks shown in Fig. 2. Each of the three-port networks is completely characterized by its corresponding admittance matrix . This is one possible approach for deriving the input-port admittance characteristic of the four-way combiner, and it can be similarly employed in the analysis of combiners with more than four input ports.

(5b)

(5c) (5d) (6a)

Note that the admittance matrix in (6) provides a complete description of the input-port characteristics of the four-way combiner of Fig. 1. It allows one to determine the input-port currents for any arbitrary set of input-port voltages and vice versa. For the four-way combiner of Fig. 1, if one further assumes that the PAs are outphased according the phasor relationship in Fig. 1 with all input-port voltages having the same magnitude (at the combiner operating frequency), then one can solve (6) for the effective admittance each of the PAs sees looking into the combiner as a function of the outphasing angles and with all other PAs active. As can be seen from (7), shown at the bottom of this page, and , as well as and , are complex conjugate pairs. It is important to note that (7) gives the effective input admittance at the combiner’s input ports assuming that the PAs are outphased according to Fig. 1 and the PA output voltages have equal magnitudes. Furthermore, (7) is derived for a four-way combiner with TLs having half-wavelength base length ( in Fig. 1). An identical approach can be used to arrive at the effective input admittance equations for a combiner constructed with TLs having quarter-wavelength base length (see Appendix A) shown in (7a)–(7d). B. Output Power Control

(6b)

(6c) (6d)

Control of the output power delivered by the combiner to the load can be achieved either by adjusting the signal amplitudes of the combiner inputs (through modulation of the PA drive amplitudes and/or their supply voltages), by controlling the phase shift between the PAs (phase modulation), or by a combination of both of these methods. To derive an expression for the power at the output of the combiner as a function of the phase shift between the PAs and their output voltage amplitudes,

(7a)

(7b)

(7c)

(7d)

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consider again Fig. 4. It can be readily shown through conventional TL theory that for the four-way combiner with half-wavelength TL base length, the load current depends on the branch currents and , as per (8), where (see Fig. 1), (8) Furthermore, from (1), (5a), and (5b), one can express the branch currents and in terms of the combiner’s input-port voltages according to (9), where , (9)

can Combining (8) and (9), the combiner’s load current be written as per (10). Note that (10) allows one to calculate the combiner’s load current (for in Fig. 1) for an arbitrary set of input-port voltages . Furthermore, by assuming that all of the the PAs have equal output voltage amplitudes and phase relationships as per Fig. 1, (10) can be simplified to obtain the combiner’s load current (11) in terms of the PA outphasing angles and , and their output amplitude , (10) (11) delivered by the combiner to the load The output power can be easily calculated from (11), and is given by (12) for the four-way combiner of Fig. 1 with half-wavelength TL base length. is the characteristic impedance of the input-branch TLs, is the effective combiner load (after any impedance transformation stages), and are the PA outphasing angles, and and are given by and , respectively. Using a similar approach, the output power equation in the case of a combiner with quarter-wavelength TL base length can be developed (see Appendix A). Note that (12) relies on the assumption that the combiner’s input-port voltages are purely sinusoidal (at the frequency at which the combiner is designed to operate) with identical amplitudes as per the phasor representation shown in Fig. 1, (12) As can be seen from (12), one can indeed modulate the output power by either controlling the PA outphasing angles and , and/or by modulating the output voltage amplitude of the PAs. The output signal’s phase is simply controlled by applying a common phase offset to all four of the inputs . The variation of output power as a function of the outphasing angles is shown in the contour plot of Fig. 5. This figure highlights that a given output power can be produced by multiple outphasing angle pairs , allowing for design freedom in how the control angles are chosen. This observation forms the basis of the outphasing control strategy described in Section II-C, in which we use additional criteria (e.g., minimizing reactive

Fig. 5. Output power contours (normalized to peak power, lines 2 dB apart), when the outphasing control angles are varied. Since a given output power can be generated by multiple combinations of phase control angles, we can impose additional design criteria on how the control angles are selected. In this work, we choose to minimize the reactive component of the effective loading impedance on the four-branch PAs, thus maximizing efficiency. The outphasing angle trajectory corresponding to this control law is shown.

loading components) to select the control law. The characteristics of this combiner are further explored in Appendix B. C. Outphasing Control Strategies As can be seen from the output power relation derived in (12) and Fig. 5, there exist an infinite number of PA outphasing angle pairs for a given combiner output power . This extra degree of freedom allows us to impose additional criteria on the input-port characteristics of the combiner so as to achieve the specified branch PA loading conditions with modulation of output power. In this paper, we choose to minimize the reactive loading through selection of an optimal susceptance (OS) control law: the PA outphasing angles and are chosen such that the peak imaginary part of the load admittance is minimized over a specified output power operating range. The OS control angles for a given combiner output power level can be calculated by employing (12) and simultaneously minimizing the susceptive components of the combiner’s effective input admittances given in (7). Interestingly, it can be shown that for a given output power , minimizing the susceptive components of the combiner’s effective input admittances corresponds to all four susceptive components having identical magnitudes, i.e., . Thus, to determine the OS control angles, we must solve the output power relation in (12) for and while simultaneously forcing identical susceptive magnitudes of the combiner’s effective input admittances given by (7). For the four-way combiner of Fig. 1 with half-wavelength TL base lengths, these two conditions reduce to the system of equations in (13), where (13a) follows from requiring identical input susceptance magnitudes, while (13b) is a rearranged form of (12), (13a) (13b) The system of equations in (13) can be further solved to yield the OS control angles and for the four-way combiner of Fig. 1 with as per (14) and (15), where

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Fig. 6. Loading conditions for the branch PAs calculated at the input to the , , and four-way TL combiner with and , , , and (see topology in Fig. 1). Power is normalized to the power delivered when all four PAs drive 50- loads.

, , and by the combiner to the load

Fig. 7. Comparison of loading conditions, for example, outphasing systems, implemented with conventional Chireix combining, lumped-element four-way (this work). [12], and TL-based four-way combining with

is the output power delivered , (14) (15)

The calculated load admittances seen by the four-branch PAs are shown in Fig. 6 for an example design with a 10:1 operating power range and . Indeed, as can be seen from Fig. 6, the magnitude of the susceptive loading of all four PAs is identical, which is in agreement with the criteria on which the derivation of OS control is based. Furthermore, as predicted by (7), the loading admittance of PA pairs A and D and B and C are complex conjugates. Referring to Fig. 6, one can notice that due to the OS control, the four PAs are loaded with nearly identical conductances and, hence, they contribute evenly to the overall power delivered to the load. Although different, this TL-based multi-way outphasing system has properties that are somewhat analogous to those with the multi-way combining network in [8] and [9] and its variations [11], [12]. A comparison of the theoretical effective loading conditions for Chireix combining, lumped-element four-way [10], and TL-based four-way combining is shown in Fig. 7 for example combiner designs of similar dynamic ranges. It can be seen that when these systems are synthesized with PAs sensitive to loading reactance, there is a substantial advantage to four-way combining. Selection between the TL four-way combiner and the discrete four-way combiner (and its microstrip variations) will depend primarily on ease of implementation (e.g., with respect to carrier frequency, loss, and layout considerations). D. Combining Network Design The combining network is designed based on a specification of its load resistance and its operating output power range. For this analysis, we consider the operating output power range to be delineated by the highest and lowest output power values at which the imaginary component of the effective load impedances seen at the combiner input are zero. For instance, for the example values given in Fig. 6, the output power range is 10

Fig. 8. Design curves showing the output power range (solid) and peak susceptance (dashed) for the proposed TL combiner with TL characteristic impedances selected as two, three, and ten times . The peak susceptance axis ; to denormalize, multiply values by shows values normalized to .

dB, based on the separation (in normalized output power) between the two zero-susceptance points. In practice, the usable operating range may be slightly larger than this value; for instance, in Fig. 6 the susceptance to below 4-dB normalized output power is still below the peak susceptance level over the nominal operating range. The ratio of the TL impedances to the load resistance determines the magnitude of the load susceptance variations seen by the branch PAs, and the overall range over which the combiner can optimally operate. Generally, these impedances should be chosen to be at least twice to limit the variation in loading susceptance. The larger the ratio of and to , the smaller the range of susceptance, but the output power range over which susceptance stays small is also reduced. Conversely, for smaller ratios, a larger power range can be achieved, but at the expense of greater susceptive components. Practical considerations and implementation details may further constrain the range of possible values for and . The design curves in Fig. 8 are used to determine appropriate values for and based on a desired load resistance , output power range (in dB), and peak susceptance for a specified design. Note that these curves assume equal values for the TL impedances and . An intermediate (unitless) design parameter uniquely characterizing the combiner is denoted as . Given a desired output power range, the value for can be found by tracing across from the “Output Power Range” axis to the appropriate black (solid) curve corresponding to the desired

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ratio to . The abcissa then denotes the appropriate value for the design. Based on this value, the resulting peak susceptive PA loading can be read off the right axis (red, dashed curves). Having selected the value for , the length increments and are computed according to (16) and (17) for the combiner having a base-length . For the combiner with base length, inverse cosine functions replace the the inverse sine functions in these equations, (16) (17) The load resistance used in the combiner network design may represent a different load value connected via an impedance transformer such as the , line indicated in Fig. 1. This impedance transformer stage provides an additional degree of control over the TL characteristic impedances, for example, to improve the manufacturability of the design. As shown in Fig. 1, we denote the actual load resistance as , and the design resistance as .

Fig. 9. Layout of the compact four-way power combiner. The PCB is designed for a 2.14-GHz carrier frequency and measures 52.8 mm 67.3 mm, with the core combiner layout only 39.1 mm wide.

III. COMBINER DESIGN AND IMPLEMENTATION This section presents two design examples of the four-way combining network, both for implementation on a Rogers 4350 substrate and operation at 2.14 GHz with an approximately 10-dB power range for outphasing control. Both designs utilize due to practical layout limitations associated with the required and values. TL and load impedances are likewise selected based on manufacturability considerations. The first example is designed for a compact layout, while the second accommodates port spacing requirements specific to the experimental system. A. Compact Layout Example Following the methodology outlined in Section II, we select a value of for the design parameter based on the curve in Fig. 8 and a specified 10-dB power range. This compact layout example is designed for a 20-mil-thick Rogers 4350 substrate so, in order for the values of and to result in practical dimensions, we have chosen values and . The design resistance is matched to the desired 50- load through a quarter-wave line with . The TL length increments for this design are computed according to (16) and (17) as and , where mil at 2.14 GHz for this substrate. With these values determined, the layout is implemented and simulated using Agilent Technologies’ Advanced Design System (ADS) software. Mitered bends are used to create the compact serpentine layout shown in Fig. 9, and spacing between the branches is kept above 3 the microstrip line widths to minimize coupling among the branches [49]. An additional design constraint is to locate all four inputs on a single edge of the printed circuit board (PCB) opposite to the single output port, as shown. The compact combiner PCB for a 2.14-GHz carrier measures only

Fig. 10. Simulated loading impedances when the extracted layout is driven using ideal voltage sources.

52.8 mm 67.3 mm, with the core combiner layout (i.e., omitting the 50- interconnects) only 39.1 mm wide. The compact combiner is characterized in simulation by using Momentum RF to extract an EM model of the core layout. When this extracted layout model is simulated as a combining structure driven by four ideal branch PAs and with an ideal 50- load, the simulated loading conditions are as shown in Fig. 10. The performance closely matches that of the ideal system (see Fig. 6), with the magnitude of the imaginary component of the load remaining under 5 mS over the range of operation. The extracted combiner was fabricated on 20-mil-thick Rogers 4350 substrate and its port relationships were characterized using a four-port Rohde & Schwarz ZVA67. Figs. 11 and 12 show the simulated and measured frequency response of the four transmission coefficients (where port 5 is the output/combining port) and the output port reflection coefficient when all ports are 50 terminated. The phase

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Fig. 11. Comparison of simulated (dashed) and measured (solid) transmission coefficient magnitudes for the compact combiner layout when all ports are 50 terminated.

Fig. 12. Comparison of simulated and measured reflection coefficient at the combiner output port when all ports are 50 terminated.

Fig. 13. Relative phases measured at the compact combiner’s input ports when all ports are 50 terminated and the output port is driven. The expected relative phases at 2.14 GHz based on the outphasing control law used in this work are indicated by the horizontal dashed lines.

of transmission coefficients is shown in Fig. 13; the relative phases at the four ports corresponds to the expected outphasing relationship for this design (shown as dashed lines) at 2140 MHz within 1.5 . From these measured results, it can be seen that operation of this compact combiner design should be possible over at least 200-MHz bandwidth. B. Experimental Prototype Layout The experimental system has physical constraints that prevent the use of the compact layout described in Section III-A. In particular, the branch PAs are mounted on carriers that require spacing of at least 81.3 mm between input ports. In order to experimentally validate the approach (using the same PAs as for previous outphasing systems [10]–[12] for comparison purposes), therefore, a second prototype combiner was designed using the “T” structure layout shown in Fig. 14. This design uses , , , and . (Note that the related conference paper [46] indicated values and in

Fig. 14. Photograph of the 100-W 2.14-GHz experimental system. The branch PAs, also used in the experimental system of [12], are based on [5]. The PA carriers in this connectorized prototype require spacing of at least 81.3 mm between the input ports, causing the relatively large combining network layout shown.

error; the lengths and were used.) A quarter-wave transformer with functions as an impedance transformer between the design resistance and the actual load. A 1.52-mm RO4350 substrate was selected as yielding manufacturable dimensions sizes for the 100- and 40.8- lines. The combiner’s “T” junction structure was chosen to accommodate the larger layout requirements (specifically, the spacing between PAs evident in Fig. 14). Note, however, that the asymmetry in the input paths with respect to the T junctions is not ideal and that the compact layout version above will perform more closely to the ideal combiner due to the symmetry of the junctions. An additional practical constraint relates to the net electrical length of the RF path connecting the PA (specifically, the drain of the device) and the combiner. In order for the resistive load modulation at the combiner to appear resistive at the device, this net electrical length must be an integer multiple of quarter wavelengths. Additional 50- lines are included on the combiner board to augment the microstrip lengths on the PA PCB and the interconnects themselves to reach the desired total length. The final dimensions of this combiner implementation are 212 mm 102 mm, substantially larger than the compact version described in Section III-A. Detailed dimensions of the experimental combining network are given in Fig. 15. As described in [10], multi-way combiners may be characterized through reverse drive (operating the combiner as a splitter and measuring the response). When the system was measured by driving the output port (with the four input ports terminated with 50 ), the port magnitude match was found to be within 5% in voltage amplitude of an ideal (even) split, and the phase within 3 of the expected values. The measured transmission coefficients are shown in Fig. 16.

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Fig. 15. Annotated layout of the experimental combining network, with dimensions given in millimeters. The board is implemented on 1.52-mm-thick Rogers 4350 substrate (figure reproduced from [46]).

9

Fig. 17. Block diagram of the experimental measurement setup.

As becomes larger, the terms inside the parentheses for (16) and (17) become smaller. In the half-wavelength-based combiner, this means that as increases, the difference lengths and become small, and may present a different kind of manufacturing challenge in distinguishing between the two different path lengths. In this case, the quarter-wavelength-based design may be preferred if the operating frequency allows for lengths corresponding to small fractions of a wavelength. IV. MEASURED SYSTEM PERFORMANCE A. Experimental Setup

Fig. 16. Measured transmission coefficients at the input ports of the combiner used in the experimental setup, when all ports are 50 terminated and the combiner output port is driven.

C. Quarter-Wave Base Length Design Example As described in Section II, it is possible to select either a quarter-wavelength or half-wavelength as the base length for the power combining network. Since a shorter TL length will have lower insertion loss, it may seem preferable to use a quarterwavelength base. For our design constraints, however (operating frequency, desired loading impedance for the branch PAs, design choice for ), we found that the quarter-wavelength results in impractically short line lengths. Consider, for example, implementing a combiner as in the compact layout example in Section III-A with , , and design load resistance value . Replacing the inverse sine functions in (16) and (17) and evaluating with the above values yields and . The long and short line lengths for stages 1 and 2 are, therefore, (18) (19) For our substrate, the shortest of these four lengths would be on the order of 3.6 mm, compared to the longest, which is approximately 25.8 mm, making layout challenging.

Fig. 14 shows a photograph of the experimental RF outphasing amplifier. The branch PAs are based on the inverse class-F design in [5], discussed in greater detail in [11]. Signal component separation is performed in MATLAB on a PC, and a field-programmble gate array (FPGA) provides an interface between the PA and four digital-to-RF upconverting paths based on Analog Devices’ AD9779A DACs and ADL5735 IQ modulators, as shown in the block diagram in Fig. 17. (Note that an analog signal component separation approach could also be realized in place of the multiple digital-to-RF paths, as described in [30] and [31], though that was not done in this work.) Output power is measured with a Rohde & Schwarz NRT-Z44 through power meter. The setup allows for continuous wave (CW) measurements of the four-way power-combining system output power and drain efficiency. Due to memory limitations on the FPGA, however, the testbench has limited ability to perform modulated tests (as described in greater detail in [12]). A recreation of the experimental testbench is shown in Fig. 18. B. CW System Performance The system CW outphasing performance is characterized by varying both amplitude and relative phases of the four CW branch PA inputs. As in the related system described in [12], the signal component separation algorithm to determine the four-branch PA’s input signals is based on a combination of the OS control law and amplitude modulation. This mixed-mode control law has three regions of operation, as indicated in Fig. 19. At the highest output power levels, the PA drive power is maximized and output power is controlled using outphasing only [according to the ideal OS control law, see (14) and (15)].

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Fig. 20. CW measurement of output power as a function of power command , using control phases determined by the outphasing control law in (14) and (15), in the pure outphasing and outphasing plus back-off regions (see Fig. 19). dB power point corresponds to a nominal loading impedance on The the four PAs of 50 .

Fig. 18. Photograph of an approximation of the experimental setup, recreated to show the test bench.

Fig. 20 shows the CW output power as a function of commanded power [see (14) and (15)] when the system is operated in the outphasing and outphasing plus backoff regimes. The nonlinearity near 0-dB commanded power is due to the experimentally determined drive back-off characteristic, which has been chosen for a good efficiency characteristic rather than to optimize linearity. It is clear from this result that some amount of linearization [digitial predistortion (DPD)] would be necessary for this architecture to be used in a modern communications system. C. Modulated Performance

Fig. 19. CW measurements of the drain efficiency and output power when the outphasing angles are swept, and comparison to measurements of the radial stub combining network in [12].

In the region labeled “Outphasing plus drive backoff,” a combination of drive amplitude and phase control is used, with the input drive amplitude backed off so that the branch PAs are not over-driven. The drive levels are determined experimentally for highest efficiency while still saturating the branch PAs. At low output power levels, i.e., more than 7 dB below peak output power, the amplitude is modulated alone (with constant outphasing angles). This mixed-mode approach extends the system’s output range down to zero. The peak CW drain efficiency of the system is 72% with efficiency remaining above 60% over the 7-dB outphasing range. Also shown in Fig. 19 are the CW measurements of a four-way outphasing system using the same PAs, but with a four-way radial-stub-based combiner [12]. The two combining networks demonstrate comparable performance and insertion loss with the slightly compressed efficiency curve in the TL version most likely explained by its “T” layout that introduces asymmetry in the design. The compact layout described in Section III could not be measured experimentally because of the large dimensions of the PAs (simply using cables to connect the PAs and combiner board is complicated by the sensitivity of the system to electrical length between the branch PAs and the combiner reference plane). For a practical, compact, and most efficient version, the PAs and combiner should be integrated on a single PCB.

Since the bandwidth and linearity of the baseband signal decomposition setup was limited, this work does not focus on the linearizability of the approach. Nonetheless, the system was tested with a 3.84-MHz W-CDMA signal having a 9.15-dB (measured) peak-to-average power ratio (PAPR), for which the average drain efficiency was 54.5%. Limited DPD was applied based on a memoryless lookup table (LUT) and the use of an oscilloscope as an observation receiver. The 34.2-dBc adjacent channel leakage power ratio (ACLR) under these conditions is comparable to the 37.7-dBc ACLR produced from one of the IQ modulators in the signal component separator (SCS) (the SCS design is described in further detail in [12]). The low ACLR of the experimental setup is a result of the short (repeated) test waveform. Table I summarizes the performance of this outphasing amplifier in comparison to other state-of-the-art works having similar technology and output power levels. Compared to the authors’ previous demonstrations of four-way outphasing techniques, this TL implementation shows comparable efficiency and shares the power-handling capability of the all-microstrip radial stub combiner [12]. The compact TL combiner introduced in this work has an area advantage over the radial combiner, and is expected to scale better (in size and frequency) than previous techniques. V. CONCLUSION Outphasing PA systems are attractive solutions to achieve efficiency over a wide dynamic range due to their use of saturated-mode operation. In this work we have investigated the

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TABLE I COMPARISON TO OTHER WORKS: W-CDMA PERFORMANCE

given by (20a)–(20e), where , and ,

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,

,

(20a)

(20b) (20c)

(20d) (20e) operation and design of an outphasing architecture that provides nearly ideal resistive load modulation of branch amplifiers, while enabling use of a microwave-friendly all-TL combining network. The new all-TL multi-way lossless power combining network is effective for compact microwave PA systems. In order to enable implementation of this idea, we have derived theoretical expressions for branch PA loading conditions and system output power. We present both a design approach and an outphasing control strategy to minimize the variation in susceptive loading impedances for a specified load resistance and output power range. A design example of a compact layout shows that the combining network, operating at a 2.14-GHz carrier frequency, can be fit within a 39.1 mm 52.8 mm area. Measurements of this network indicate a close match to the theoretical analysis. The approach is experimentally verified in a 100-W experimental prototype operating at 2.14 GHz, which demonstrates peak CW drain efficiency of 72% and efficiency above 60% over a 7-dB range. When compared directly to the measured results of a related power-combining network based on microstrip lines and radial stub elements, the all-TL combining system has nearly the same CW performance. It is anticipated, however, that the TL version of this approach will have better potential to scale to higher frequency applications due to its tree structure.

Assuming that the PAs are outphased according to the phasor relationship in Fig. 1 with all input-port voltages having the same magnitude , then one can solve (20) for the effective admittance each of the PAs sees looking into the combiner as a function of the outphasing angles and (21) with all other PAs active. Note that the expressions in (21) are quite similar to the expressions derived for the effective admittances of the four-way combiner with given by (7),

(21a)

(21b) APPENDIX A In Section II, we presented a derivation of the input-port admittance characteristics of the four-way combiner of Fig. 1 for a half-wavelength TL base length . By employing an analogous approach, it can be shown that the four-port admittance matrix relating the combiner’s input port voltages and currents for a four-way combiner implemented with a quarter-wavelength base length is

Furthermore, it can be shown that the output power delivered by the four-way combiner to the load in the case of is given by (22), where and are the PA outphasing angles, and is the PA output amplitude according to the phasor diagram in Fig. 1, (22) It can be further shown that the OS control angles and for the case of the four-way combiner with are given by

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(23) and (24), where , , and is the output power delivered by the combiner to a load , (23) (24)

APPENDIX B In this Appendix, we further consider the characteristics of the combiner, including its output power control characteristic. Interestingly, one can notice from (12) that the output power delivered to the load is independent of the characteristic impedance of the output branch TLs in the four-way combiner of Fig. 1. To gain insight into this fact, consider again the three-port TL network shown in Fig. 2. Suppose that we short-circuit ports 1 and 2, i.e., and . Looking into port three, one sees the parallel combination of the two TLs connected to ground. Due to the differential increment in their length, the two TLs behave as the parallel combination of a conjugate pair of purely imaginary impedances to ground (assuming that the TLs are lossless), hence resulting in infinite net impedance when looking into port 3 (with ports 1 and 2 short-circuited). Due to the linearity of the three-port network in Fig. 2, we can conclude that the port 3 input current is independent of and is entirely determined by , , and . This is also accordingly reflected by the three-port admittance matrix in (1). This result is valid for any , provided that the base length of the TLs is an integer multiple of a quarter wavelength, and the TLs are treated as lossless. Selecting the TL base length to be other than an integer multiple of a quarter wavelength results in a non-infinite impedance (at the operating frequency) when looking into port 3 with ports 1 and 2 short circuited, implying a dependence of on . Redirecting our attention to the case of the four-way combiner and applying the above reasoning to Fig. 4, we can now see that the branch currents and are independent of the respective node voltages and and the characteristic impedance of the output branch TLs. From (8), the load current and, hence, output power , depends solely on and and the length of the output-branch TLs, but not on their characteristic impedance . It is important to note, however, that although the output power may be independent of , one must carefully select both TL impedances and as their values are both of great importance to the overall performance of the combiner and its input-port admittance characteristic (e.g., see Fig. 8). It is also worth clarifying that selecting to be zero does not result in infinite output power as may be counterintuitively suggested by (12) for the four-way combiner of Fig. 4 with . In reality, choosing equal to zero corresponds to a degenerate case of the four-way combiner (see Fig. 4) in which each of the input branch TLs is a half-wavelength long. Suppose that all four input ports of the combiner are driven with ideal voltage sources with zero output impedance according to the phasor diagram in Fig. 1. One can represent each of the input branches (comprising a half-wavelength-long TL

and ideal voltage source driver) with its Thevenin equivalent having zero Thevenin impedance and a Thevenin voltage that is 180 out of phase with the respective terminal input voltage . This effectively results in connecting the PAs that are driving terminals A and B (C and D) in parallel. Practically, this is only possible if terminal pairs A/B and C/D are driven in phase, i.e., in Fig. 1( and ), or if the output amplitude of all PAs is zero, i.e., in (12). In the former case, the four-way combiner is reduced to a two-way combiner, while in the latter case no power is delivered to the output. As Section II-D describes in detail, selection a smaller value for and results in smaller variation of the combiner’s input susceptance over its operating power range. As a tradeoff, however, smaller values for and require TL characteristic impedances and that are relatively high with respect to the combiner’s load. The ability to practically implement TLs with high characteristic impedances limits how small one can choose and . REFERENCES [1] L. Kahn, “Single-sideband transmission by envelope elimination and restoration,” Proc. IRE, vol. 40, no. 7, pp. 803–806, Jul. 1952. [2] D. Kimball et al., “High-efficiency envelope-tracking W-CDMA basestation amplifier using GaN HFETs,” IEEE Trans. Microw. Theory Techn., vol. 54, no. 11, pp. 3848–3856, Nov. 2006. [3] H. Tango, T. Hashinaga, K. Totani, H. Kuriyama, Y. Hamada, and T. Asaina, “A 60% efficient envelope tracking power amplifier for 40W, 2.6 GHz LTE base station with in/output harmonic tuning,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2013, pp. 1–4. [4] M. Pelk, W. Neo, J. Gajadharsing, R. Pengelly, and L. de Vreede, “A high-efficiency 100-W GaN three-way Doherty amplifier for base-station applications,” IEEE Trans. Microw. Theory Techn., vol. 56, no. 7, pp. 1582–1591, Jul. 2008. [5] A. Grebennikov, “A high-efficiency 100-W four-stage Doherty GaN HEMT power amplifier module for WCDMA systems,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2011, pp. 1–4. [6] H. Deguchi, N. Watanabe, A. Kawano, N. Yoshimura, N. Ui, and K. Ebihara, “A 2.6 GHz band 537W peak power GaN HEMT asymmetric Doherty amplifier with 48% drain efficiency at 7 dB,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2012, pp. 1–3. [7] H. Chireix, “High power outphasing modulation,” Proc. IRE, vol. 23, no. 11, pp. 1370–1392, Nov. 1935. [8] D. Perreault, “A new power combining and outphasing modulation system for high-efficiency power amplification,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 8, pp. 1713–1726, Aug. 2011. [9] A. Jurkov, L. Roslaniec, and D. Perreault, “Lossless multi-way power combining and outphasing for high-frequency resonant inverters,” IEEE Trans. Power Electron., vol. 29, no. 4, pp. 1894–1908, Apr. 2014. [10] T. W. Barton, J. L. Dawson, and D. J. Perreault, “Experimental validation of a four-way outphasing combiner for microwave power amplification,” IEEE Microw. Wireless Compon. Lett., vol. 23, no. 1, pp. 28–30, Jan. 2013. [11] T. W. Barton, J. L. Dawson, and D. J. Perreault, “Four-way lossless outphasing and power combining with hybrid microstrip/discrete combiner for microwave power amplification,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2013, pp. 1–4. [12] T. Barton and D. Perreault, “Four-way microstrip-based power combining for microwave outphasing power amplifiers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 10, pp. 2987–2998, Oct. 2014. [13] A. Jurkov and D. Perreault, “Design and control of lossless multi-way power combining and outphasing systems,” in Midwest Circuits Syst. Symp., Aug. 2011, pp. 1–4. [14] A. Jurkov, L. Roslaniec, and D. Perreault, “Lossless multi-way power combining and outphasing for high-frequency resonant inverters,” IEEE Trans. Power Electron., vol. 29, no. 4, pp. 1894–1908, Apr. 2014. [15] T.-P. Hung, D. Choi, L. Larson, and P. Asbeck, “CMOS outphasing class-D amplifier with Chireix combiner,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 8, pp. 619–621, Aug. 2007.

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[16] S. Lee and S. Nam, “A CMOS outphasing power amplifier with integrated single-ended Chireix combiner,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 6, pp. 411–415, Jun. 2010. [17] F. Raab, “Efficiency of outphasing RF power-amplifier systems,” IEEE Trans. Commun., vol. 33, no. 10, pp. 1094–1099, Oct. 1985. [18] A. Birafane and A. Kouki, “On the linearity and efficiency of outphasing microwave amplifiers,” IEEE Trans. Microw. Theory Techn., vol. 52, no. 7, pp. 1702–1708, Jul. 2004. [19] F. Raab et al., “Power amplifiers and transmitters for RF and microwave,” IEEE Trans. Microw. Theory Techn., vol. 50, no. 3, pp. 814–826, Mar. 2002. [20] I. Hakala, D. Choi, L. Gharavi, N. Kajakine, J. Koskela, and R. Kaunisto, “A 2.14-GHz Chireix outphasing transmitter,” IEEE Trans. Microw. Theory Techn., vol. 53, no. 6, pp. 2129–2138, Jun. 2005. [21] N. Singhal, H. Zhang, and S. Pamarti, “A zero-voltage-switching contour-based outphasing power amplifier,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 6, pp. 1896–1906, Jun. 2012. [22] M. El-Asmar, A. Birafane, M. Helaoui, A. Kouki, and F. Ghannouchi, “Analytical design methodology of outphasing amplification systems using a new simplified Chireix combiner model,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 6, pp. 1886–1895, Jun. 2012. [23] P. Landin, J. Fritzin, W. Van Moer, M. Isaksson, and A. Alvandpour, “Modeling and digital predistortion of class-D outphasing RF power amplifiers,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 6, pp. 1907–1915, Jun. 2012. [24] T. Ni and F. Liu, “A new impedance match method in serial Chireix combiner,” in Asia–Pacific Microw. Conf., 2008, pp. 1–4. [25] W. Gerhard and R. Knoechel, “Improved design of outphasing power amplifier combiners,” in German Microw. Conf., 2009, pp. 1–4. [26] R. Beltran, F. Raab, and A. Velazquez, “HF outphasing transmitter using class-E power amplifiers,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2009, pp. 757–760. [27] M. van der Heijden, M. Acar, J. Vromans, and D. Calvillo-Cortes, “A 19W high-efficiency wide-band CMOS-GaN class-E Chireix RF outphasing power amplifier,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2011, pp. 1–4. [28] D. Calvillo-Cortes, M. van der Heijden, and L. de Vreede, “A 70W package-integrated class-E Chireix outphasing RF power amplifier,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2013, pp. 1–3. [29] T. Barton and D. Perreault, “An RF-input outphasing power amplifier with RF signal decomposition network,” in IEEE MTT-S Int. Microw. Symp. Dig., May 2015, pp. 1–4. [30] T. Barton and D. Perreault, “Theory and implementation of RF-input outphasing power amplification,” IEEE Trans. Microw. Theory Techn., vol. 63, no. 12, pp. 4273–4283, Dec. 2015. [31] N. Faraji and T. Barton, “An RF-input Chireix outphasing power amplifier,” in IEEE Radio Wireless Symp., Jan. 2016, pp. 1–3. [32] J. Yao and S. Long, “Power amplifier selection for LINC applications,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 8, pp. 763–767, Aug. 2006. [33] F. Raab et al., “RF and microwave power amplifier and transmitter technologies—Part 3,” High Freq. Electron., vol. 2, no. 5, pp. 34–48, Sep. 2003. [34] R. Langridge, T. Thornton, P. Asbeck, and L. Larson, “A power re-use technique for improved efficiency of outphasing microwave power amplifiers,” IEEE Trans. Microw. Theory Techn., vol. 47, no. 8, pp. 1467–1470, Aug. 1999. [35] X. Zhang, L. Larson, P. Asbeck, and R. Langridge, “Analysis of power recycling techniques for RF and microwave outphasing power amplifiers,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 49, no. 5, pp. 312–320, May 2002. [36] P. Godoy, D. Perreault, and J. Dawson, “Outphasing energy recovery amplifier with resistance compression for improved efficiency,” IEEE Trans. Microw. Theory Techn., vol. 57, no. 12, pp. 2895–2906, Dec. 2009. [37] D. Cox, “Linear amplification with nonlinear components,” IEEE Trans. Commun., vol. COM-23, no. 12, pp. 1942–1945, Dec. 1974. [38] T. Barton, “Not just a phase: Outphasing power amplifiers,” IEEE Microw. Mag., vol. 17, no. 2, pp. 18–31, Feb. 2016. [39] F. Raab, “High-efficiency linear amplification by dynamic load modulation,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2003, pp. 1717–1720. [40] F. Raab, “Electronically tuned power amplifier,” U.S. Patent 7,202,734, Apr. 10, 2007.

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[41] H. Nemati, C. Fager, U. Gustavsson, R. Jos, and H. Zirath, “Design of varactor-based tunable matching networks for dynamic load modulation of high power amplifiers,” IEEE Trans. Microw. Theory Techn., vol. 57, no. 5, pp. 1110–1118, May 2009. [42] Y. Chen, K. Jheng, A. Wu, H. Tsao, and B. Tzeng, “Multilevel LINC system design for wireless transmitters,” in Int. VLSI Design, Automat., Test Symp., 25–27, 2007, pp. 1–4. [43] P. A. Godoy, S. Chung, T. W. Barton, D. J. Perreault, and J. L. Dawson, “A 2.4-GHz, 27-dBm asymmetric multilevel outphasing power amplifier in 65-nm CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 10, pp. 2372–2384, Oct. 2012. [44] W. Gerhard and R. Knoechel, “Novel transmission line combiner for highly efficient outphasing RF power amplifiers,” in Eur. Microw. Conf., 2007, pp. 1433–1436. [45] R. Beltran and F. Raab, “Simplified analysis and design of outphasing transmitters using class-E power amplifiers,” in IEEE Power Amplifiers for Wireless and Radio Appl. Top. Meeting, Jan. 2015, pp. 16–18. [46] T. W. Barton, A. S. Jurkov, and D. J. Perreault, “Transmission-linebased multi-way lossless power combining and outphasing system,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2014, pp. 1–4. [47] L. Roslaniec, A. Jurkov, A. Al Bastami, and D. Perreault, “Design of single-switch inverters for variable resistance/load modulation operation,” IEEE Trans. Power Electron., vol. 30, no. 6, pp. 3200–3214, Jun. 2015. [48] M. Borage, M. V. Nagesh, M. S. Bhatia, and S. Tiwari, “Resonant immittance converter topologies,” IEEE Trans. Ind. Electron., vol. 58, no. 3, pp. 971–978, Mar. 2011. [49] G. Kompa, Practical Microstrip Design and Applications. Norwood, MA: Artech House, 2005. Taylor W. Barton (S’07–M’12) received the Sc.B., M.Eng., E.E., and Sc.D degrees from the Massachusetts Institute of Technology (MIT), Cambridge, MA, USA. In 2014 she joined The University of Texas at Dallas (UT Dallas), Dallas, TX, USA, where she is currently an Assistant Professor. Prior to joining UT Dallas, she was a Postdoctoral Associate with the Microsystems Technology Laboratories, MIT. Her research interests include high-efficiency RF, power, analog circuit design, and classical control theory.

Alexander S. Jurkov (S’07) received the B.S. degree in electrical engineering and computer science from the University of Calgary, Calgary, AB, Canada, in 2010, the S.M. degree in electrical engineering from the Massachusetts Institute of Technology (MIT), Cambridge, MA, USA, in 2012, and is currently working toward the Ph.D. degree in the area of power electronics and RF system design at MIT. He is currently with the Laboratory of Electronic and Electromagnetic Systems, MIT. In 2012, he was with Analog Devices Inc., Woburn, MA, USA, where he was involved with the design of integrated high-speed data buffers and their realization with a 24-nm technology. His research interests include RF power converters, amplifiers, combiners, and mixed-signal and embedded system design.

Prathamesh H. Pednekar (S’15) received the B.E. degree in electronics and telecommunication from the University of Mumbai, Mumbai, India, in 2012, and is currently working toward the M.S. degree from The University of Texas at Dallas (UT Dallas), Dallas, TX, USA. Prior to joining UT Dallas in 2014, he was a Research Scientist with the Society for Applied Microwave Electronic Engineering and Research, Mumbai, India. His research interests include RF power amplifier design, passive microwave components, and phased-array radar.

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David J. Perreault (S’91–M’97–SM’06–F’13) received the B.S. degree from Boston University, Boston, MA, USA, and the S.M. and Ph.D. degrees from the Massachusetts Institute of Technology (MIT), Cambridge, MA, USA. In 1997, he joined the Laboratory for Electromagnetic and Electronic Systems, MIT, as a Postdoctoral Associate, and became a Research Scientist in 1999. In 2001, he joined the Department of Electrical Engineering and Computer Science, MIT, where he is currently a Professor and the Associate Department

Head. He also consults in industry and is co-founder of Eta Devices, a startup company that focuses on high-efficiency RF power amplifiers. His research interests include design, manufacturing, and control techniques for power electronic systems and components, and in their use in a wide range of applications. Dr. Perreault was the recipient of the Richard M. Bass Outstanding Young Power Electronics Engineer Award, the R. David Middlebrook Achievement Award, the Office of Naval Research (ONR) Young Investigator Award, and the Society of Automotive Engineers (SAE) Ralph R. Teetor Educational Award. He has also coauthored seven IEEE prize papers.

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Sensitive and Efficient RF Harvesting Supply for Batteryless Backscatter Sensor Networks Stylianos D. Assimonis, Spyridon-Nektarios Daskalakis, Student Member, IEEE, and Aggelos Bletsas, Senior Member, IEEE

Abstract—This work presents an efficient and high-sensitivity radio frequency (RF) energy harvesting supply. The harvester consists of a single-series circuit with one double diode on a low-cost, lossy FR-4 substrate, despite the fact that losses decrease RF harvesting efficiency. The design targeted minimum reflection coefficient and maximum rectification efficiency, taking into account not only the impedance matching network, but also the rectifier microstrip trace dimensions and the load. The simulated and measured rectenna efficiency was 28.4% for 20-dBm power input. In order to increase sensitivity, i.e., ability to harvest energy and operate at low power density, rectennas were connected in series configuration (voltage summing), forming rectenna arrays. The proposed RF harvesting system ability was tested at various input power levels, various sizes of rectenna arrays, with or without a commercial boost converter, allowing operation at RF power density as low as 0.0139 W/cm . It is emphasized that the boost converter, whenever used, was self-started, without any additional external energy. The system was tested in supplying a scatter radio sensor, showing experimentally the effect of input power density on the operational cold start duration and duty cycle of the sensor. Index Terms—Energy harvesting, rectennas, rectifiers.

I. INTRODUCTION

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VEN though an ocean of electromagnetic waves surrounds us, most of that ambient electromagnetic energy remains unused. Moreover, the number of radio frequency (RF) emitters has been rapidly increasing over the last few decades, due to the development of new wireless technologies such as cellular networks, Wifi, digital TV, and wireless sensor networks (WSNs). Hence, there is an engineering challenge to collect unused ambient RF energy and supply with power small electrical devices, such as backscatter radio sensor networks [1]–[3]. Three decades ago, Brown proposed a system obtained from an antenna and a rectifier—the rectenna—for Manuscript received June 06, 2015; revised November 16, 2015; accepted February 10, 2016. This work was supported by the ERC04-BLASE project, executed in the context of the “Education & Lifelong Learning” Operational Program of the National Strategic Reference Framework (NSRF), General Secretariat for Research & Technology (GSRT), funded through European Union-European Social Fund and Greek national funds. S. D. Assimonis was with the School of Electronic and Computer Engineering, Technical University of Crete, GR-73100 Chania, Greece. He is now with the School of Electronics, Electrical Engineering and Computer Science, Queen's University Belfast, Belfast BT7 1NN U.K. (e-mail: [email protected]). S.-N. Daskalakis and A. Bletsas are with the School of Electronic and Computer Engineering, Technical University of Crete, GR-73100 Chania, Greece (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2533619

transformation of RF energy to dc [4]. Since then, RF energy harvesting has gained increasing interest, especially during the last few years. An important parameter in a rectenna system is the efficiency, i.e., the ratio of the dc power output to the RF power input. Nowadays, significant research effort has been directed towards high-efficiency rectennas. However, most prior designs operate optimally at high input power, e.g., greater than 0 dBm [5]–[9]. In [5], an antenna array was used, and efficiency was 65% for 25-dBm power input. In [6], authors used a rectenna array and efficiency of 20% was achieved for power density 62 W cm or equivalently for power input 13.27 dBm (for rectenna geometric area of 342.25 cm ). In [7], maximum efficiency of 77.8% was achieved for 10 dBm input. In [8], efficiency of 54% was obtained for power density 200 W cm or for 9.54 dBm power input (assuming rectenna geometric area of 45 cm ). Finally, the rectenna in [9] was designed with analytical models and closed-form expressions, with obtained efficiency of 40% for 0 dBm. Considerable research effort has been also made towards high-efficiency rectennas for low power input, e.g., less than 0 dBm [10]–[22]. In [10], authors harvested energy from a TV station tower 6.3 km away, and a maximum efficiency of 21% was achieved for 4.74-dBm power input. A multiband harvesting system was presented in [11]; a single wideband antenna was connected to multiple narrowband rectifier paths. The rectifier outputs were joined together adding the dc voltages, and the maximum obtained efficiency was approximately 27% for 10-dBm power input. In order to further increase the efficiency, substrates with low losses [12]–[15] have been proposed, increasing the total cost, however. In [12], a multiband rectenna was used, operating at 900 and 1750 MHz, with measured efficiency of 44.5% and 34.5%, for power input 8.77 and 16.27 dBm, respectively. In [13], the rectenna operated at 900 MHz with 33% efficiency for 10-dBm input power. In [14], efficiency was increased to 50% for 17.2 dBm at 2.4 GHz. A circular polarized rectenna was presented in [15] with 15.3% and 11.3% efficiency for vertical and horizontal polarization, respectively. In [16], authors proposed a hybrid harvesting system consisting of both a rectenna and a solar panel. The rectenna was dual-band (850 MHz, 1850 MHz) with 15% efficiency at both frequency bands, for 20-dBm power input. In [17] and [18], emphasis was on the required impedance matching circuit inductances, while minimizing the reflection coefficient, with attained efficiency of 17% and 20.5%, respectively, for 20-dBm power input. However, single (and

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TABLE I RF-TO-DC CONVERSION EFFICIENCY VERSUS POWER INPUT/DENSITY AND FREQUENCY

not double) rectification was exploited, while the optimization process did not have load or rectenna microstrip dimensions as optimization degrees of freedom (as in this work), while cost function included reflection coefficient only and excluded efficiency (as opposed to this work). Furthermore, [17] used no boost converter and no rectenna array, while the work in [18] utilized a custom boost converter and added the rectenna array currents (and not voltages, as in this work). In [19], energy was harvested from a digital TV station with efficiency of 18.2% for 20 dBm. In [20], ambient RF power was collected, and the end-to-end (rectenna and boost converter) efficiency was estimated in normal operation, without considering the startup time (i.e., the time needed to start charging from 0 V). Furthermore, the harvesting system in [21] operated at 20-dBm RF input power and stored 5.8 J into a rechargeable battery within 1 h, while submicrometer CMOS technology was used in [22], and the harvesting system supplied a wireless sensor node from 19.7-dBm power input. Table I offers summary of achieved efficiency versus input power (or power density) and frequency, for various prior art designs. Another critical parameter in RF energy harvesting is the rectenna dc output voltage. A typical rectenna is designed to supply with energy small electrical devices, which usually operate only above a cutoff voltage level. Hence, the rectenna output voltage should support such design requirement. In RF-to-dc rectification, the number of diodes—or, equivalently, the number of voltage multiplier stages—affects the rectifier efficiency and the rectified dc output voltage [23]; for low power input, when the number of diodes is decreased, efficiency will be increased and output voltage will be decreased; when the number of diodes is increased, the opposite happens.

Therefore, in order to increase voltage, the authors in [10] used a five-stage Dickson RF-to-dc voltage multiplier. The output voltage across a 1-M load was 5 V for 4.74-dBm power input, while the efficiency was 21%. In [11], the authors proposed a hybrid multistage and multiband RF harvesting system with one directional, log-periodic, wideband antenna. For power input 10 dBm, the maximum efficiency was 27% and was decreased to 20% when the number of frequency bands where RF harvesting takes place, or equivalently the number of diodes, was increased from 2 to 5. Moreover, the output voltage across a 100-k load was 2.3 and 2.5 V, when power input was 12.76 and 12.04 dBm, respectively. In order to overcome the problem of multiple diodes, two other solutions have been proposed. The first is the multiple branches approach [13]; one branch is used for the start-up stage and the other for the boost converter, with achieved output voltage of 2 V for 15.5-dBm power input. The second solution is a rectenna-area design in which multiple rectennas are combined at the dc area, while operating at the same or different frequency band. In [20], the authors tested two configurations: 1) multiple rectennas, which harvest energy from different frequency bands, sharing one boost converter, with obtained end-to-end efficiency of 15% and 2) multiple rectennas, sharing multiple boost converters, with obtained end-to-end efficiency of 13%. At both cases, RF input power was 12 dBm.1 The output voltage from the rectenna array at both cases was over 330 mV, which was adequate to start the boost converter. The latter's open-circuit output voltage reached 2.84 V. In [18], the authors used a 1 2 rectenna array with rectennas operating at the same frequency. The rectenna array output voltage across a 5-k load was 110 mV for 20-dBm power input. Next, the load was removed and the rectenna was connected to a boost converter; the open-circuit voltage at the output of the rectenna array and the boost converter was 298 mV and 1.4 V, respectively. Given the nonlinear output impedance of rectennas and their variable efficiency at different input power density levels, it has become apparent that power management circuitry designs should be carefully designed; work in [24] designed a power management circuit between rectenna and energy storage, with discrete components, for maximum power point tracking and operation as low as 10–100 W, targeting RF harvesting from cellular base stations; the latter offer energy that can easily vary by two orders of magnitude, within 24 h of operation. For input power below 100 W, losses of quiescent operation become challenging. The work in [25] presents a custom power management integrated circuit (IC) with resistor emulation technique, which can operate at low power of the order of 1 W, requiring external power at start-up, however, in addition to the RF-harvested power. The work in [26] discussed joint designs of rectenna and power conversion management in order to supply a wireless transceiver using power management circuitry principles as in [24] and [25] and power input densities as low as 1.74 W cm (corresponding to 12 dBm for a 6 6 cm patch antenna), while work in [27] offered designs for input 1It is noted that the presented efficiency for [20] on Table I refers to the maximum end-to-end efficiency for only one rectenna (not rectenna array).

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power densities as low as 0.62 W cm , exploiting power management circuitry, rectenna arrays in various connection configurations, and large antenna gain for the startup circuit. This work operates a scatter radio duty-cycle sensor with input power level densities as low as 0.0139–0.1 W cm , using careful rectenna design methodology and certain modifications on a commercial power management boost converter. Specifically, the goals of this work are as follows. 1) Design an efficient and sensitive rectification system (i.e., operation at low power input), e.g., around or below 20 dBm. 2) Maximize the rectified dc output voltage. 3) Offer a complete supply solution for scatter radio, dutycycle WSN nodes with RF harvesting, without any utilization of additional external power (e.g., for starting the boost converter). In sharp contrast to prior designs, it was shown that minimization of the reflection coefficient only was not sufficient for maximization of the RF-to-dc efficiency. Specifically, in contrast to prior art (e.g., [17] and [18]), the design procedure of this work formulated a multi-objective optimization problem with two goals, i.e., minimization of reflection coefficient and maximization of RF-to-dc efficiency. Moreover, it was shown that all rectifier trace dimensions (e.g., the distance between diode and load) and not only the matching network trace dimensions and lumped elements (e.g., inductances), affect the RF-to-dc efficiency. Hence, during the rectifier design/optimization: • the optimization variables, i.e., the degrees of freedom were not only the matching network parameters but also all other trace dimensions (e.g., the distance between diode and load, the diode and the port input); • load was also a degree of freedom; • minimum reflection coefficient and maximum RF-to-dc efficiency were simultaneously targeted. Based on this design procedure, the proposed harvesting system is both analytically and experimentally shown to offer high efficiency and high sensitivity (i.e., it can operate at low input power density). Furthermore, in contrast to prior designs, the proposed harvesting system can supply continuously, without a boost converter or use of any energy tank (e.g., big capacitor), at low input power density of 0.1103 W cm , a battery less backscatter sensor node, which consumes power on the order of 100 W and operates with voltage greater than 1.6 V. Moreover, whenever a boost converter was needed (e.g., for extra low-power density, below 0.1 W cm ), the latter was self-started, using the designs of this work, without utilization of any additional external power source. The proposed harvesting system is not only of high sensitivity, but also of high efficiency, compared with the state of the art: for low-power input, e.g., for dBm, rectifier offers 28.4% RF-to-dc efficiency, while for dBm the efficiency is 43.77%. This paper is organized as follows. The rectifier is presented in Section II, with description of geometry, design/optimization procedure, reflection coefficient, and RF-to-dc efficiency, including measurements. Section III presents the design of the rectenna, including measurements of RF-to-dc efficiency. Multiple rectennas are also combined, forming rectenna arrays and

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Fig. 1. Microstrip rectifier design (top layer).

the open-circuit voltage is measured for various input power levels. Section IV presents the end-to-end RF harvesting supply system for a custom scatter radio, duty-cycle WSN node. Finally, Section V concludes this work. II. RECTIFIER A single-series circuit with a double diode was designed, analyzed, optimized, and fabricated. The obtained rectifier offers high efficiency (i.e., greater than 28%) for low power input (i.e., below 20 dBm) or equivalently for low power density (i.e., below 0.07 W cm ), low complexity, and low cost. The latter was achieved using the widely used but lossy FR-4 substrate, despite the fact that losses decrease efficiency. In order to increase efficiency, emphasis was given on the optimization process, as explained bellow. The whole geometry is depicted in Fig. 1. The RF power input is converted to dc power through the low-cost Schottky double-diode “HSMS285C”. The matching circuit reduces the reflection losses of the incoming wave, while the capacitors and were introduced in order to stabilize the obtained dc voltage. Finally, the output power supplies load . A. Analysis and Optimization The rectifier was designed to operate at 868 MHz, taking into account the UHF RFID frequencies in Europe. Initially, full electromagnetic analysis with the method of moments was applied to the microstrip trace only, in order to estimate the losses from the low-cost FR-4 and copper, the fringing fields, and the electromagnetic coupling between ports. The FR-4 was modeled with , , copper thickness 35 m, and substrate height 1.5 mm. Next, harmonic-balance and largesignal analysis was employed, taking into account the nonlinear behavior of the rectifier due to the diode. In this work, a new design procedure is proposed in order to enhance the rectifier efficiency and sensitivity, for low power input. First, the goal was not only the minimization of reflection coefficient (1)

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TABLE II OPTIMIZED TRACE DIMENSIONS (MM)

at the rectifier input port (assuming antenna impedance of 50 ), but also the maximization of the RF-to-dc efficiency

(2) and are the power input and output, respectively, where and is the voltage across . Second, the optimization degrees of freedom were not only the matching network microstrip dimensions ( , and lumped elements, , in Fig. 1), but also the microstrip dimensions of the whole rectifier, including distance: • between the diode and capacitor , • between the diode and via, • as shown in Fig. 1, • between the diode and the load, • between the diode and capacitor . Third, the load was also a design parameter. It is noted that dimensions parameters , can take continuous values, while , , and can take only discrete values. On the other hand, the capacitances and , the power input , and the frequency were fixed at 100 pF, 20 dBm, and 868 MHz, respectively.2 Hence, in contrast to prior art (e.g., [17] and [18]), the design procedure is a multi-objective optimization problem (i.e., two simultaneous goals) with multiple (i.e., ten) degrees of freedom. Finally, a genetic algorithm was applied to solve this optimization problem. After such optimization methodology (denoted as “optimization no. 1”), the obtained lumped elements were 12 nH, 1.2 nH, and 9530 , while the optimized trace dimensions are tabulated in Table II. The simulated is depicted in Fig. 2. It is shown that the rectifier's reflection coefficient is below 10 dB for between 35.7 and 7.8 dBm, i.e., for low-power input. Fig. 3 depicts versus . According to simulated results, the efficiency is equal to 43.5% and 7.31% for equal to 10 dBm and 30 dBm, respectively, and 26.77% for 20 dBm. It is known that the efficiency is a function of frequency, as well as load and power input, due to the diode nonlinearity. Such nonlinear relation is examined subsequently. The simulated efficiency versus frequency for various power input levels and load fixed at 9530 , is depicted in Fig. 4. It is shown that the rectifier operates optimally at 868 MHz for 20 dBm, as expected. For 10 dBm input power, the maximum efficiency of 45.9% is achieved at 889 MHz, while for 30 dBm, maximum efficiency of 7.4% is found at 858.5 MHz. Fig. 5 depicts the relation between the efficiency and the load for various power input levels, with the frequency fixed at this time at 868 MHz. For 20 dBm, 2Operational bandwidth in the UHF 900-MHz regime is also examined subsequently.

Fig. 2. Simulated reflection coefficient at 868 MHz versus power input. The rectifier operates from 35.7 to 7.8 dBm.

Fig. 3. Simulated and measured rectifier efficiency versus power input at 868 MHz.

Fig. 4. Simulated rectifier efficiency versus frequency for different power input levels. Load is fixed at 9530 .

maximum 26.77 occurs when 9530 , as expected due to the optimization process. For 10 dBm and 30 dBm, maximum efficiency is equal to 43.77% and 7.34% for 8.17- and 10.96-k load, respectively. Both efficiencies are close to the respective ones for 9530 (the latter is the selected value for 20 dBm). In order to show that microstrip trace dimensions affect the efficiency and minimization of reflection coefficient only does

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input was varied from 40 dBm to 10 dBm; load was fixed at 9530 and the voltage across was measured. The RF-to-dc efficiency was estimated via (2), and the measured results are depicted in Fig. 3. Agreement between simulations and measurement can be observed; for 20 dBm, the measured efficiency is 27.1%, while for 10 dBm and 30 dBm, and , respectively. III. RECTENNA

Fig. 5. Simulated rectifier efficiency versus load for different power input levels at 868 MHz.

Fig. 6. Simulated RF-to-dc efficiency versus input power for various optimization/design procedures.

not guarantee RF-to-dc efficiency maximization, two additional rectifiers were designed. In “optimization no. 2”, parameters to be optimized were matching network inductance ( , ) and load ( ), while minimizing reflection coefficient only. In “optimization no. 3”, optimization parameters were again matching network inductance ( , ) and load ( ), while minimizing reflection coefficient and maximizing efficiency, simultaneously. Other parameters were fixed: 3 mm, where and 100 pF. Fig. 6 depicts the resulted efficiency. It is evident that the maximum RF-to-dc efficiency took place only when the approach of this work (“optimization no. 1”) was applied. The latter can be explained as follows. Reflection coefficient quantity shows the amount of reflected power due to the impedance mismatch between the source and the rectifier. Minimizing reflection coefficient leads to maximizing the rectifiers power input, but does not guarantee that the whole amount of this power will be transformed to dc power (e.g., minimization of reflection coefficient does not take into account losses on substrate). On the other hand, efficiency shows the rectifier's ability to convert the input RF power to dc power, and, hence, it takes into account possible losses (e.g., substrate and diode losses). B. Measurements The rectifier was fabricated with a CNC milling method (Fig. 3, inset). A signal generator was connected to the rectifier. The frequency was fixed at 868 MHz and the power

Initially, a monopole antenna was designed, analyzed, fabricated, and merged with the rectifier, forming a rectenna. The latter's efficiency was measured with a specific methodology explained below. A critical rectenna parameter, except from the RF-to-dc efficiency, is the offered power to the load and the rectenna dc output voltage, as already mentioned. The latter requirement is obtained from the fact that usually the rectifier is connected to a dc-to-dc boost converter, which only operates above a cutoff voltage and current level. On the other hand, ambient power density is usually below 1 W cm [10], [19], [20]. Hence, it is an engineering challenge to harvest as much power as possible and increase the rectenna dc output voltage for low-power density. Prior work has used multiband rectennas with multiple diodes [10], [11], multiple branches [13], and rectenna arrays operating on same [6] or different [20] frequency bands in order to increase the rectified dc-power and output voltage. However, most of these designs operate optimally for power input greater than 12 dBm. In this work, the goal was to implement a harvesting system for low power input and power density, less that 20 dBm and 0.07 W cm , respectively. Hence, a rectenna and rectenna array topology was implemented and tested in terms of radiation pattern, efficiency, output power, and open-circuit voltage. The ability of one rectenna or rectenna array scheme, combined with a commercial dc-to-dc converter, to provide energy to a backscatter sensor node for low-power density was also examined. A. Antenna A microstrip monopole antenna was merged with the proposed microstrip rectifier, in order to obtain a plane rectenna. Specifically, a hybrid microstrip monopole bow-tie-inspired antenna was designed to operate at RFID band in Europe (around 868 MHz). The two arms of a conventional bow-tie were placed on different sides of FR-4 substrate, in a symmetric manner. A copper trace was connected with one of the two arms, forming a feeding microstrip line with the other arm. The obtained antenna was first simulated and then fabricated. Good agreement between simulation and measurement results is shown in Fig. 7. The latter also shows the antenna gain at horizontal plane; gain is equal to 1.7 dB and 2 dB at and , respectively, and 1.8 dB for ; thus, the antenna is appropriate for ambient power harvesting due to its almost omnidirectional radiation pattern.3 3The radiation pattern is not perfectly omnidirectional due to fabrication defects.

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Fig. 7. Bow-tie-inspired monopole antenna reflection coefficient and radiation ) in terms of gain (in dB). The pattern (inset, right) at horizontal plane ( fabricated antenna is also shown (inset, left).

Fig. 9. Rectenna RF-to-dc efficiency measurement two-phase methodology.

levels with a log-periodic antenna at 868 MHz (“phase 1”). A calibrated antenna was placed at far-field distance, at “point b” (a commercial monopole with gain 1.8 dB). The monopole was connected to a spectrum analyzer and received power was measured. Next, the calibrated antenna and the spectrum analyzer were removed, the proposed rectenna was placed at exactly the same location (“point b”) and voltage across load was measured (“phase 2”). The rectenna RF-to-dc efficiency is estimated by (4) where is the power density of the incident to the rectenna plane wave and the total antenna effective area given by Fig. 8. Antenna to rectifier matching bandwidth for different power input levels.

B. Rectenna Performance In this section the hybrid bow-tie-inspired monopole was connected to the rectifier, forming the rectenna. The latter's operation bandwidth depends on input power and load. Assuming that and is the antenna and rectifier input impedance, respectively, the rectenna operational bandwidth (i.e., matching bandwidth) is defined where: 10 dB

(3)

. Fig. 8 shows the where { } denotes the conjugate of matching bandwidths for various input power levels at fixed load of 9530 . For 10, 20, and 30-dBm input power, the rectenna operates within 862.8–939.3, 842.2–912.1, and 844.1–881.4 MHz, respectively. Hence, the proposed rectenna can capture and convert RF to dc power not only at 868 MHz but also within GSM 850 and GSM 900 cellular bands. Nevertheless, the rectenna was tested for a single frequency, i.e., at 868 MHz only, for a fair comparison with prior art designs. The proposed rectenna RF-to-dc efficiency was estimated with the measurement topology of Fig. 9. Initially, a signal generator was placed at “point a”, transmitting at different power

(5) where is wavelength at 868 MHz and is the rectenna gain. The rectenna was placed in parallel to the transmitter and thus, 1.8 dB according to Fig. 7, inset. Hence, from (5), 143.67 cm . The power density is calculated by (6) after measuring and using 1.8 dB (i.e., the gain of the commercial monopole). The measured RF-to-dc efficiency is calculated from (4)–(6) and shown in Fig. 10. Measured rectifier efficiency (without antenna in Fig. 3) and rectifier simulation results are also depicted. Good agreement can be observed. Specifically, for 20 dBm, , while for 30 dBm and 10 dBm, is 9% and 44.2%, respectively. Fig. 11 shows the measured voltage values across the 9530- load. It can be observed that 164.5 mV for 20 dBm, while for 30 dBm and 10 dBm the voltage is 29.3 and 649 mV, respectively. The measured and simulated rectenna efficiency versus power density are depicted in Fig. 12, showing again good agreement. For 1 W cm the efficiency is 44.8%, while for 0.1 W cm and 0.01 W cm , is 30.2% and 9.57%, respectively. It is noted that for 0.0696 W cm

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Fig. 13. Diagram of the 1 2 rectenna array topology: “horizontal” (left) and “vertical” (right) -alignment. The 1 3 topology was also tested.

Fig. 10. Measured rectenna efficiency versus power input. Measurement and simulation results of the rectifier are also depicted. Inset: the fabricated rectenna.

Fig. 14. Radiation pattern at horizontal plane ( ) in terms of gain (in dB) for 1 2 (left) and 1 3 (right) rectenna array, at “horizontal” (solid line) and “vertical” (dashed line) alignment.

Fig. 11. Measured rectenna output voltage across the 9530-

load.

Fig. 12. Measured rectenna efficiency versus ambient power density.

and rectenna gain dBm and

1.8 dB, according to (4), (5) .

C. Rectenna Array The input power in a rectifier system is proportional to the rectenna effective area or equivalently to the rectenna gain. Hence, according to (4), in a rectifier system with given efficiency, the offered power to the load will be increased if the rectenna gain is increased (although such increment does not guarantee that dc output voltage will be also increased).

On the other hand, antenna gain increase could potentially lead to complex rentenna designs with directional radiation pattern, which may not be desirable for ambient harvesting. Another approach increases the number of rectennas, where each rectenna is considered as a dc voltage source. The latter approach was used in this work. Two rectenna array topologies with two alignments were tested, depicted in Fig. 13: antennas were placed alongside the -axis (“horizontal”-alignment) or alongside -axis (“vertical”-alignment). At both alignments, rectenna plane was parallel to -plane. Due to the rectennas proximity, the rectenna array radiation pattern should be estimated. Rectennas were placed at or equivalently 17.5 cm (Fig. 13) in order to maximize gain [28] and keep mutual coupling between rectennas at low level, i.e., less than 10 dB. The whole geometry was analyzed at 868 MHz, with one antenna radiating and the other/others (with the rectifier/rectifiers) acting as parasitic elements. The final radiation pattern resulted from the combination of the constituting individual rectennas. Fig. 14 depicts the gain (in dB) for “horizontal” and “vertical” alignment for 1 2 and 1 3 rectenna array. In “horizontal” alignment, the maximum gain was 4.67 dB and 6.43 dB for 1 2 and 1 3, respectively, and (i.e., at horizontal plane) and . Radiation pattern was omnidirectional for “vertical” alignment; the gain was 4.36 and 6.1 dB for 1 2 and 1 3 rectenna array, respectively. At all cases, reflection coefficient and mutual coupling was less than 18 dB. Rectennas were electrically connected in series configuration (voltage summing) in order to increase the offered to the load power and the output voltage. The obtained rectenna arrays were placed at far-field distance from a transmitter and the dc open-circuit voltage was measured. The efficiency measurement procedure was similar to that followed for one rectenna.

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Fig. 17. Boost converter schematic with the low-power “bq25504.”

Fig. 15. Measured open-circuit voltage versus power density for one, two or three rectennas at horizontal alignment.

Fig. 18. Measurement setup with DAQ instrument.

Fig. 16. Measured open-circuit voltage versus number of rectennas at horizontal alignment for 0.1- W cm power density.

Fig. 15 (inset) illustrates the measurement setup; a signal generator with one log-periodic antenna was the transmitter. The rectenna array at horizontal alignment was placed at far-field distance and the open-circuit voltage was measured through a voltmeter. The power density, which was dependent on the transmitted power, varied from 0.01 to 1 W cm . The measurement results are depicted in Fig. 15. It is observed that as the number of the rectennas increases, the dc voltage is also increased. The open-circuit voltage was 0.515, 1.15, and 1.97 V when one, two, and three rectennas harvest energy for W cm , respectively. Fig. 16 depicts the open-circuit voltage versus the number of rectennas placed at horizontal alignment for 0.1- W cm power density. It is evident that voltage is the linear addition of each rectenna or, equivalently, rectenna addition offers close to addition of rectified signals. Additional theoretical work is further needed, left for future work. IV. SUPPLYING A BACKSCATTER SENSOR NETWORK NODE This section studies the ability of the proposed rectenna to supply with power a duty-cycle backscatter sensor node for low-power density. Again, a log-periodic antenna, connected to a signal generator, transmits power at 868 MHz. A rectenna scheme, placed at the far field, harvests and converts RF energy to dc voltage. The rectenna array output is connected to

the backscatter sensor node presented in [3], which consumes power of the order of 100 W and operates with voltage greater than 1.6 V. According to Fig. 15, when 1 3 rectenna array is used, the open-circuit voltage is greater than 1.9 V for over than 0.1 W cm . Hence, it is possible to directly and continuously supply with energy the backscatter sensor node [3] without use of any boost converter. Thus, the 1 3 rectenna array was placed at far-field in horizontal alignment. Rectennas were connected in series configuration and the output was directly connected to the sensor node. More specifically, the power density was 0.1103 W cm or, equivalently, 18 dBm, given 1.8 dB and 13.37 dBm, according to (7). Input voltage to sensor was 1.69 V, while the open-circuit voltage was about 2 V (Fig. 15). In order to validate the backscatter operation of the sensor node, a conventional monopole antenna was connected to a spectrum analyzer and the received spectrum band depicted the obtained peak at frequency and the subcarrier peaks at , due to sensor switching its antenna between two states at frequency . According to Fig. 15, only one rectenna offers open-circuit voltage greater than 1.6 V, when is greater than 0.9346 W cm . Similarly, for 1 2 and 1 3 rectenna array, voltage is greater than 1.6 V when is greater than 0.1866 W cm and 0.0721 W cm , respectively. Hence, a boost converter is needed for the sensor of [3], when is less than 0.1 W cm and one or two rectennas are used. In this work, the low-power boost converter “bq25504” was utilized [29]. The latter is an integrated circuit with maximum power point tracking (MPPT), minimum cold start voltage and typical input power of 330 mV and 10 W, respectively, and low quiescent current ( nA). Hence, for minimum voltage of 330 mV and typical power of 10 W, the boost converter input impedance is 10890 , which is close to 9530 (i.e.,

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Fig. 19. Voltage across rectenna ouput (boost converter input ) and 100- F capacitor (boost converter output— ) for various levels of RF power 0.1103 W cm . (b) One rectenna (1 1 rectenna array) for 0.0876 W cm . (c) Two rectennas density. (a) One rectenna (1 1 rectenna array) for 0.0439 W cm . (d) Two rectennas (1 2 rectenna array) for 0.0220 W cm . (e) Three rectennas (1 3 rectenna array) (1 2 rectenna array) for 0.0220 W cm . (f) Three rectennas (1 3 rectenna array) for 0.0139 W cm . for

the load value for optimum RF-to-dc efficiency of the proposed rectenna). However, due to the MPPT function (which aims to extract the maximum power from the rectenna output), as well as the fact that the boost converter has two main operational modes (one for cold-start operation and one after cold-start, with the main boost charger enabled), the input impedance does not remain constant. The MPPT functionality includes periodic sampling of the input (open) voltage signal, after disabling the charger for a limited duration of time (on the order of 256 ms every 16 s); the cold start charger is an unregulated, hysteretic

boost converter with lower efficiency compared to the main boost charger and provides the initial power so that the latter can start its operation. This work measured experimentally the end-to-end input-output relationship of the whole system, as described below. Initially, only one rectenna was connected to the analog backscatter sensor node through the “bq25504”. Fig. 17 depicts the circuit schematic topology. Rectenna voltage ( ) was boosted ( ) and a 100- F capacitor was charged from 0 V. It is noted that the boost converter was

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self-started (cold start) and no external energy was used. Digital signal output ( ) is set to high and low, when the capacitor voltage reaches a pre-defined upper and lower limit, respectively. In this work, the boost converter was designed to have low and upper voltage thresholds of 2.4 V and 2.8 V, respectively. An external PMOS (“BSH207”) was placed between the sensor node and the pin. The inverted signal (through the open drain NMOS “BSH105”) was used to drive the gate of the PMOS. While is lower than 2.8 V, PMOS stays off (zero current) and the boost converter charges the capacitor. Next, when the reaches 2.8 V, PMOS turns on and energy flows from the capacitor to the sensor. The latter operates and voltage squared pulses ( ) are produced that control the backscatter RF transistor of the sensor [3]. Next, capacitor is discharged and when 2.4V, PMOS turns off again and current stops flowing to the sensor. Then, the capacitor is charged again until 2.8 V and the procedure is repeated. A data acquisition (DAQ NI USB-6356) instrument was used in order to measure the voltage across the rectenna output ( ) and the capacitor ( ). The measurement setup is depicted in Fig. 18. Fig. 19(a) illustrates the measurement voltages for one rectenna at 0.1103 W cm . This power density corresponds to 18 dBm, given 1.8 dB. It is observed that the 100- F capacitor needs 530 s to be charged from 0 V (cold start) to 2.8 V. Then, the sensor node, operates every 25 s. For less power density, i.e., 0.0876 W cm or, equivalently, for 19 dBm the capacitor is charged after 1498 s and sensor operates every 44 s [Fig. 19(b)]. Next, two rectennas were connected in series configuration at the dc-area, according to horizontal alignment. The obtained 1 2 rectenna array was connected to the sensor node through the “bq25504” boost converter. Power density was 0.0439 W cm , corresponding to 22 dBm, given 1.8 dB. From (5)–(6), we have (7) According to Fig. 14, 4.67 dB in this case, hence 19.3 dBm. The first time charging duration and the operating period were 938 s and 30 s, respectively [Fig. 19(c)]. Then, power density was further decreased to 0.0220 W cm or equivalently, 25 dBm and 22.13 dBm. Capacitor was charged after 1655 s and the sensor node operated every 49 s [Fig. 19(d)]. Next, the number of the rectennas were increased to three. For the same power density, the capacitor was charged after 679 s and the node operated every 22 s [Fig. 19(e)]. Hence, the first time charging duration was decreased by a factor of 2.4 and the operating period by a factor of 2.2. It is noted that now 6.43 dB and thus 20.37 dBm. Then, power density was further decreased to 0.0139 W cm , corresponding to 27 dBm and 22.37 dBm. The capacitor was charged after 1687 s, while the sensor operating period was 43 s [Fig. 19(f)]. Again, it is emphasized that the boost converter was

Fig. 20. Voltage across 100- F capacitor ( ), backscatter sensor node ), and output ( ) for one rectenna at 0.1103 W cm input ( or equivalently for 18 dBm.

self-started and no external power was used for all of the above cases. The latter was due to the fact that “bq25504” exhibits low cold start voltage (330 mV) and quiescent current ( 330 nA). At all cases where this boost converter was used, the above two requirements were fulfilled, hence there was no need for external energy support. For example, at the case with one rectenna and power input 19 dBm, rectenna efficiency is about 30%, offering maximum transferred power to boost converter of about 3.8 W. According to Fig. 19(b), is 360 mV, so maximum current input at boost converter is approximately 10.5 A, which is much greater than lower quiescent current. It is noted that for Fig. 19 different power density levels (and equivalently power input ) were selected based on the measured power via the spectrum analyzer: and power density are obtained through (6) and (7), given , while takes values from 18 to 27 dBm. Fig. 20 depicts voltages , , and for one operating period. For the shake of simplicity, only the case of one rectenna at 0.1103 W cm is presented [Fig. 19(a)]. It is observed that the backscatter sensor node produces voltage squared pulses ( ) for approximately 1 s (operating duration) every 25 s (“operating period”). The produced pulses are also shown. It is noted that the operating duration remains constant for all cases, while operating period varies, as already shown. Finally, Fig. 21(a) and (b) depicts the first time charging duration and operating period, respectively, versus power density and size of rectenna array. It is observed that when the power density is decreased, both times are increased rapidly (i.e., logarithmically), as expected, while when power density is increased, e.g., for 0.5 W cm , rectenna arrays have similar operation in terms of first time charging duration and operating period. At all cases, 330 mV, so that the boost converter can start operating without any utilization of additional external power source. Hence, 1 1, 1 2 and 1 3 rectenna array starts capturing power when is greater than 0.0876, 0.0220 and 0.0139 W cm , respectively. The fact that 330 mV can be also observed at Fig. 19 for all illustrated cases.

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REFERENCES

Fig. 21. (a) First time charging duration and (b) operating period versus power density for 1 1, 1 2 and 1 3 rectenna array.

V. CONCLUSION This work presented the design, implementation, and measurement of an efficient and sensitive RF harvesting supply, for low-power input. The proposed low-complexity and cost rectifier system consists of a single-series circuit with a double diode on a low-cost, lossy FR-4 substrate. It was shown that rectifier microstrip trace dimensions are important optimization parameters, which could improve efficiency when addressed properly in the design methodology. Furthermore, RF harvesting sensitivity can be increased using rectennas connected in series configuration and placed in specific topologies, forming rectenna arrays. In that way, sensor nodes can be powered even without commercial boost-converters. If the latter is utilized, sensitivity can be further increased, i.e., the supply can operate in smaller input power densities and specific duty-cycle scatter radio sensor examples were provided, requiring no other external power source.

ACKNOWLEDGMENT The authors would like to thank E. Alimpertis, N. FasarakisHilliard, K. Tzedaki, and G. Theodorakis for their help in various steps throughout this work.

[1] G. Vannucci, A. Bletsas, and D. Leigh, “A software-defined radio system for backscatter sensor networks,” IEEE Trans. Wireless Commun., vol. 7, no. 6, pp. 2170–2179, 2008. [2] E. Kampianakis, S. D. Assimonis, and A. Bletsas, “Network demonstration of low-cost and ultra-low-power environmental sensing with analog backscatter,” in Proc. IEEE Top. Conf. Wireless Sensors and Sensor Networks, Newport Beach, CA, USA, Jan. 2014, pp. 61–63. [3] S.-N. Daskalakis, S. D. Assimonis, E. Kampianakis, and A. Bletsas, “Soil moisture wireless sensing with analog scatter radio, low power, ultra-low cost and extended communication ranges,” in Proc. IEEE Sensors Conf., Valencia, Spain, Nov. 2014, pp. 122–125. [4] W. C. Brown, “The history of power transmission by radio waves,” IEEE Trans. Microw. Theory Techn., vol. MTT-32, no. 9, pp. 1230–1242, Sep. 1984. [5] J. Zbitou, M. Latrach, and S. Toutain, “Hybrid rectenna and monolithic integrated zero-bias microwave rectifier,” IEEE Trans. Microw. Theory Techn., vol. 54, no. 1, pp. 147–152, Jan. 2006. [6] J. A. Hagerty, F. B. Helmbrecht, W. H. McCalpin, R. Zane, and Z. B. Popović, “Recycling ambient microwave energy with broad-band rectenna arrays,” IEEE Trans. Microw. Theory Techn., vol. 52, no. 3, pp. 1014–1024, Mar. 2004. [7] J.-Y. Park, S.-M. Han, and T. Itoh, “A rectenna design with harmonicrejecting circular-sector antenna,” IEEE Antennas Wireless Propag. Lett., vol. 3, no. 1, pp. 52–54, Jan. 2004. [8] E. Falkenstein, M. Roberg, and Z. Popović, “Low-power wireless power delivery,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 7, pp. 2277–2286, Jul. 2012. [9] J. Akkermans, M. Van Beurden, G. Doodeman, and H. Visser, “Analytical models for low-power rectenna design,” IEEE Antennas Wireless Propag. Lett., vol. 4, pp. 187–190, 2005. [10] R. J. Vyas, B. B. Cook, Y. Kawahara, and M. M. Tentzeris, “E-WEHP: A batteryless embedded sensor-platform wirelessly powered from ambient digital-TV signals,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 6, pp. 2491–2505, Jun. 2013. [11] A. N. Parks and J. R. Smith, “Sifting through the airwaves: Efficient and scalable multiband RF harvesting,” in Proc. IEEE Int. RFID Conf., Orlando, FL, USA, Apr. 2014, pp. 74–81. [12] A. Costanzo, A. Romani, D. Masotti, N. Arbizzani, and V. Rizzoli, “RF/baseband co-design of switching receivers for multiband microwave energy harvesting,” Sens. Actuat. A, Phys., vol. 179, pp. 158–168, 2012. [13] D. Masotti, A. Costanzo, P. Francia, M. Filippi, and A. Romani, “A load-modulated rectifier for RF micropower harvesting with start-up strategies,” IEEE Trans. Microw. Theory Techn., vol. 62, no. 4, pp. 994–1004, Apr. 2014. [14] H. Sun, Y.-X. Guo, M. He, and Z. Zhong, “Design of a high-efficiency 2.45-GHz rectenna for low-input-power energy harvesting,” IEEE Antennas Wireless Propag. Lett., vol. 11, pp. 929–932, 2012. [15] A. Georgiadis, G. Andia, and A. Collado, “Rectenna design and optimization using reciprocity theory and harmonic balance analysis for electromagnetic (EM) energy harvesting,” IEEE Antennas Wireless Propag. Lett., vol. 9, pp. 444–446, 2010. [16] A. Collado and A. Georgiadis, “Conformal hybrid solar and electromagnetic (EM) energy harvesting rectenna,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 8, pp. 2225–2234, Aug. 2013. [17] S. D. Assimonis and A. Bletsas, “Energy harvesting with a low-cost and high efficiency rectenna for low-power input,” in Proc. IEEE Radio Wireless Sympos., Newport Beach, CA, USA, Jan. 2014, pp. 229–231. [18] S. D. Assimonis, S.-N. Daskalakis, and A. Bletsas, “Efficient RF harvesting for low-power input with low-cost lossy substrate rectenna grid,” in Proc. IEEE Int. RFID-Technol. Appl. Conf., Tampere, Finland, Sep. 2014, pp. 1–6. [19] C. Mikeka, H. Arai, A. Georgiadis, and A. Collado, “DTV band micropower RF energy-harvesting circuit architecture and performance analysis,” in Proc. IEEE Int. RFID-Technol. Appl. Conf., Sitges, Spain, 2011, pp. 561–567. [20] M. Piñuela, P. D. Mitcheson, and S. Lucyszyn, “Ambient RF energy harvesting in urban and semi-urban environments,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 7, pp. 2715–2726, Jul. 2013. [21] K. Gudan, S. Chemishkian, J. J. Hull, S. Thomas, J. Ensworth, and M. Reynolds, “A 2.4 GHz ambient RF energy harvesting system with dBm minimum input power and NiMH battery storage,” in Proc. IEEE Int. RFID-Technol. Appl. Conf., Tampere, Finland, Sep. 2014, pp. 7–12.

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[22] H. Reinisch, S. Gruber, H. Unterassinger, M. Wiessflecker, G. Hofer, W. Pribyl, and G. Holweg, “An electro-magnetic energy harvesting system with 190 nW idle mode power consumption for a BAW based wireless sensor node,” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1728–1741, Jul. 2011. [23] P. Nintanavongsa, U. Muncuk, D. R. Lewis, and K. R. Chowdhury, “Design optimization and implementation for RF energy harvesting circuits,” IEEE Trans. Emerg. Sel. Topics Circuits Syst., vol. 2, no. 1, pp. 24–33, Mar. 2012. [24] A. Dolgov, R. Zane, and Z. Popović, “Power management system for online low power RF energy harvesting optimization,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 7, pp. 1802–1811, Jul. 2010. [25] T. Paing, E. A. Falkenstein, R. Zane, and Z. Popović, “Custom IC for ultra-low power RF energy harvesting,” IEEE Trans. Power Electron., vol. 26, no. 6, pp. 1620–1626, Jun. 2011. [26] Z. Popović, E. A. Falkenstein, D. Costinett, and R. Zane, “Low-power far field wireless powering for wireless sensors,” Proc. IEEE, vol. 101, no. 6, pp. 1397–1409, Jun. 2013. [27] Z. Popović et al., “Scalable RF energy harvesting,” IEEE Trans. Microw. Theory Techn., vol. 62, no. 4, pp. 1046–1056, Apr. 2014. [28] C. A. Balanis, Antenna Theory: Analysis and Design, 3rd ed. Hoboken, NJ, USA: Wiley, 2005. [29] “Ultra low-power boost converter with battery management for energy harvester applications,” in Texas Instruments SLUSAH0B Datasheet, Oct. 2011, bq25504.

Stylianos D. Assimonis was born in Thessaloniki, Greece. He received the Diploma/M.Eng. and Ph.D. degrees in electrical and computer engineering from the Aristotle University of Thessaloniki, Thessaloniki, Greece, in 2005 and 2011, respectively. From 2012 to 2015, he was with the Technical University of Crete and the Radiocommunication Laboratory, School of Physics, Aristotle University of Thessaloniki (AUTh), working as a Postdoctoral Researcher. He is currently a Senior Research Fellow with Queen's University Belfast, U.K. His research interests span over a broad range of areas including electromagnetics, metamaterials, antennas, RF harvesting, wireless power transfer, RF sensing, and RF front-end design. Dr. Assimonis was the recipient of the Postdoctoral Scholarship for Excellence from the Research Committee of AUTh in 2012, as well as the corecipient of the Metamaterials 2013 Best Paper Award (3rd place), the 2014 IEEE RFID-TA Best Student Paper competition finalist and the 2015 5th COST IC1301Workshop Best Student Paper award (3rd prize).

Spyridon-Nektarios Daskalakis (S’15) was born in Heraklion, Greece, in 1991. He received the Engineering Diploma (with honors) in electronic and computer engineering from the Technical University of Crete, Chania, Greece, in 2014, where he is currently working toward the M.Sc. degree. His current research interests include low-cost wireless sensor networks and RF energy harvesting. Particularly, he focuses on scatter radio networking, batteryless sensors, PCB design, low-cost software-defined radio, environmental sensing, and RF energy harvesting design. Mr. Daskalakis was the recipient of a fellowship award for his project ”Aristeos” (olive fly detection and monitoring with wireless sensor network) by the Clinton Global Initiative University 2014, Phoenix, AZ, USA.

Aggelos Bletsas (S'03–M'05–SM'14) received the Diploma degree (with honors) in electrical and computer engineering from the Aristotle University of Thessaloniki, Thessaloniki, Greece in 1998, and the S.M. and Ph.D. degrees from the Massachusetts Institute of Technology, Cambridge, MA, USA, in 2001 and 2005, respectively. He was with Mitsubishi Electric Research Laboratories (MERL), Cambridge, MA, USA, as a Postdoctoral Fellow and with Radiocommunications Laboratory, Department of Physics, Aristotle University of Thessaloniki, Thessaloniki, Greece, as a Visiting Scientist. He joined the School of Electronic and Computer Engineering, Technical University of Crete, Chania, Greece, in the summer of 2009, as an Assistant Professor and was promoted to Associate Professor at the beginning of 2014. He holds two patents from USPTO. His research interests span the broad area of scalable wireless communication and networking, with emphasis on relay techniques, backscatter communications and RFID, energy harvesting, radio hardware/software implementations for wireless transceivers, and low-cost sensor networks. His current vision and focus is on single-transistor front-ends and backscatter sensor networks, for large-scale environmental sensing. He is the Principal Investigator (PI) of project BLASE: Backscatter Sensor Networks for Large-Scale Environmental Sensing, funded from the General Secretariat of Research & Technology Action Proposals evaluated positively from the 3rd European Research Council (ERC) Call. Dr. Bletsas was the corecipient of IEEE Communications Society 2008 Marconi Prize Paper Award in Wireless Communications, received Best Paper distinction at ISWCS 2009, Siena, Italy, Second Best Student Paper Award in the IEEE RFID-TA 2011, Sitges, Barcelona, Spain, Best Paper distinction at the IEEE Sensors Conference (SENSORS), November 2013, Baltimore, MD, USA and Best Student Paper award at IEEE ICASSP 2015, April 2015, Brisbane, Australia. Two of his undergraduate advisees were winners of the 2009–2011 and 2011–2012 best Diploma Thesis contest, respectively, among all Greek Universities on “Advanced Wireless Systems”, awarded by IEEE VTS/AES joint Greek Chapter. In 2013, he was the recipient of the Technical University of Crete 2013 Research Excellence Award. He is also Management Committee (MC) member and National Representative in the European Union COST Action IC1301 Wireless Power Transmission for Sustainable Electronics (WiPE). He has been an associate editor of the IEEE WIRELESS COMMUNICATION LETTERS since its foundation, an associate editor of the IEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS, and Technical Program Committee (TPC) member of flagship IEEE conferences.

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Analyzing Single Giant Unilamellar Vesicles With a Slotline-Based RF Nanometer Sensor Yan Cui, Anne K. Kenworthy, Michael Edidin, Ralu Divan, Daniel Rosenmann, and Pingshan Wang

Abstract—Novel techniques that enable reagent free detection and analysis of single cells are of great interest for the development of biological and medical sciences, as well as point-of-care health service technologies. Highly sensitive and broadband RF sensors are promising candidates for such a technique. In this work, we present a highly sensitive and tunable RF sensor, which is based on interference processes and built with a 100-nm slotline structure. The highly concentrated RF fields, up to 1.76 10 V m, enable strong interactions between giant unilamellar vesicles (GUVs) and fields for high-sensitivity operations. We also provide two modeling approaches to extract cell dielectric properties from measured scattering parameters. GUVs of different molecular compositions are synthesized and analyzed with the RF sensor at 2, 2.5, and 2.8 GHz with an initial of 100 dB. Corresponding GUV dielectric properties are obtained. A one-dimensional scanning of single GUV is also demonstrated. Index Terms—Complex dielectric permittivity, conformal mapping, giant unilamellar vesicles (GUVs), microfluidics, microwave sensor.

I. INTRODUCTION

R

EAGENT-FREE detection and analysis of single biological cells in solution at low cost are important for the development of biology, medicine, and point-of-care (POC) service [1]–[3]. Hence, reagent-free sensing and identification of the molecular composition and structure of cell membranes and organelles, as well as a cell cytoplasmic matrix, are of great interest. Nevertheless, these goals are still elusive partly due to the lack of techniques sensitive enough to obtain such information. Optical methods, which have dominated whole cell studies, are usually not sensitive enough to be used label free, though stimulated Raman scattering (SRS) microscopy of single cells has been reported [4]. Additionally, optics is not compatible

Manuscript received May 01, 2015; revised August 19, 2015 and January 13, 2016; accepted February 22, 2016. Date of publication March 11, 2016; date of current version April 01, 2016. This work was supported by the National Institutes of Health (NIH) under Grant 1K25GM100480-01A1. Use of the Center for Nanoscale Materials was supported by the U.S. Department of Energy, Office of Science, Office of Basic Energy Sciences under Contract DE-AC0206CH11357. Y. Cui and P. Wang are with the Department of Electrical and Computer Engineering, Clemson University, Clemson, SC 29634 USA (e-mail: [email protected]). A. K. Kenworthy is with the Department of Molecular Physiology and Biophysics, Vanderbilt University Medical Center, Nashville, TN 37232 USA. M. Edidin is with the Department of Biology, The Johns Hopkins University, Baltimore, MD 21218 USA. R. Divan and D. Rosenmann are with the Center for Nanoscale Materials, Argonne National Laboratory, Argonne, IL 60439 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2016.2536021

with complementary metal–oxide–semiconductor (CMOS) processes, which enable inexpensive and easy-to-use electronic systems. Therefore, various electrical approaches have been actively pursued to characterize the physical properties of single cells, identify the potential electrical markers of the cells, and develop high-performance electronic systems for reagent-free analysis of the cells. Dielectric spectroscopy (DS) [1], usually referred to as impedance spectroscopy [1] at low frequencies, emerges as a primary technique with significant progress, including label-free monitoring of stem cell differentiation [5], label-free analysis of leukocyte subpopulations [6], and of cancer cells [7]. However, most DS efforts, as well as electromechanical methods that also exploit cell electrical properties (e.g., electrophoresis (DEP) and electrorotation [8], [9]), operate at relatively low frequencies. High frequencies are expected to be necessary to probe cell interiors [10], [11] while broad frequency coverage is essential to uncover cell characteristics. Unfortunately, DS sensitivity is often compromised at high frequencies [1]. The use of resonators [12], [13] and interferometers [14], [15] helps address this issue, but at single frequency points. Broadband [16] and multiple frequency DS [17] are reported with single cell sensitivities. These techniques require immobile cells. Recently, we have developed RF sensors of different forms with very high and tunable sensitivity over wide frequency ranges [18]–[21]. These sensors promise to be effective tools for the characterization and examination of single cells. In this work, we report our efforts on the design and operation of an RF interferometer that is based on nanometer slotlines (NSLs). NSLs strongly concentrate RF fields and improve interferometer sensitivity. We apply the interferometer as well as data extraction algorithms, which are developed in this work, to characterizing giant unilamellar vesicles (GUVs) of defined compositions. GUVs are biologically relevant models that are often used to study cell membrane structures, such as liquid rafts and microdomains [22], [23]. They are also used to study cells, such as red blood cells [24]–[26]. GUV molecular compositions and interior solutions can be controlled and GUV domain structures are well documented. Thus, GUVs are a good model system for cell sensor examinations. We find that we can detect GUV over a range of GHz frequencies and that complex permittivities of GUV extracted from measured -parameters imply differences in membrane organization among GUVs of different lipid compositions. This paper is organized as follows. Section II discusses RF sensor design. Section III presents algorithms for extracting RF permittivity from measured -parameters. Section IV describes

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Fig. 1. (a) Schematic of the RF sensor. (b) Top and (c) cross-section views of the sensing zone in (a) with single GUV (circle), where dimensions nm (gap), nm (Ti/Au), m (channel height), mm (substrate), mm (PDMS cover), m m. The dimension for the CPW is 0.1 (channel width), and mm/1.5 mm/0.1 mm (gap/signal line/gap). Abbreviations MUT and REF represent material-under-test and reference branches, respectively. Coefficients , will be used to describe effects of indicated components. and represent phase shifters and attenuators, respectively. The Cartesian coordinate systems are marked for (b) and (c). Mismatch interfaces for impedance are marked by red dash lines in (b).

Fig. 2.

-parameters of the nanometer RF sensing structure.

GUV synthesis and measurement results. Section V presents our discussions and conclusions. II. SLOTLINE-BASED RF SENSOR DESIGN Fig. 1(a) shows the schematic of the RF sensor. Similar to the highly sensitive and tunable RF interferometers in [18]–[21], two broadband quadrature hybrids (QHs) are used for RF probing signal division and combination. Off-chip tuning components, phase shifters ( ), and attenuators ( ) are introduced to tune the sensor sensitivity as well as the operating frequency. A slotline-based sensing structure, shown in Fig. 1(b) and (c), is used to probe single GUVs. Unlike coplanar waveguide (CPW) transmission lines used in [18]–[21], slotlines are designed to yield higher RF fields for the same gap dimension [see Fig. 1(c)], which is often limited by fabrication techniques. Thus, stronger interactions between RF fields and GUVs [27] can be obtained for higher sensor sensitivities. Furthermore, better one-dimensional (1-D) spatial resolution can be achieved since a slotine has only one gap, unlike a CPW with two gaps and a signal line. Baluns for NSL to CPW transitions [28] are shown in Fig. 1(a). CPWs are convenient for measurements. The RF structures, including the slotline and the baluns, are integrated on a fused-silica substrate through conventional micro-fabrication procedures. Lift-off processes are used for the deposition of Ti/Au (20 nm/200 nm) films. A focused ion beam (FIB) is used to form the 100-nm slotline. Fig. 2 shows the simulated and measured performance of the RF structure around the designed center frequency, 3 GHz, around which the measurement will be performed. The simulation is conducted with the High Frequency Structural Simulator (HFSS). Low return loss and insertion loss are achieved for sensor operations [21]. Factors that cause discrepancies between measurements and simulations include metal line dimension and cross-section deviations from layout, which is used for simulations. SMA

Fig. 3. Simulated distribution of electric field intensity (unit: V/m) around the sensing zone [axis origin corresponds to the gap in Fig. 1(c)].

female connectors and conductive epoxy used for measurement connection are also not taken into consideration in simulation. Compared with our previous sensors that have millimeter (mm) and micrometer ( m) gaps [18]–[21], the RF electric fields of the 100-nm slotline are concentrated to achieve much stronger GUV-RF field interactions. Fig. 3 depicts the electric field distribution at 3 GHz around the gap obtained with HFSS simulation. Minor asymmetry may be caused by simulation meshes, for which we used 0.5 m as the maximum length of mesh elements due to a compromise between simulation accuracy and simulation time. For 5-dBm input power (used in our measurements), the electric field intensity is up to 1.76 10 V m around the sensing zone. In comparison, for the sensors with mm and m gaps [18]–[21], the maximum electric field intensities are 1.33 10 and 1.73 10 V m, respectively. Thus, the absolute sensitivity of the sensor is significantly improved, as illustrated by (22) and (24). A polydimethylsiloxane (PDMS) microfluidic channel with a cross section of 50 m 50 m is built and incorporated with the slotline in the MUT branch, as shown in Fig. 4. The GUV solution is injected into and extracted from the channel through two soft plastic tubes (not shown in Figs. 1 and 4) that are attached to the circular openings of the channel. The introduction of a GUV particle, Fig. 1(c), will change the effective permittivity of the overall slotline structure and its -parameters measured by the vector network analyzer (VNA). As a result, the particle properties can be obtained with the models presented in Section III.

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Fig. 5. Configurations of partial capacitances: (a) . and (d)

of four partial capacitances shown in Fig. 5 [29]. and

,

, (b)

, (c)

,

, , and , as can then be obtained through

Fig. 4. Slotline-based sensor with PDMS microfluidic channel.

III. GUV DIELECTRIC PROPERTY EXTRACTION

(5)

A. Conformal-Mapping Method

(6)

The transmission -parameter recorded by the VNA in Fig. 1(a) can be expressed as

(1) Subscript indicates solution. The propagation constant of the slotline section is with a physical length of . The coefficients and describe the effects of all the other sensor components, including cables, attenuators, and phase shifters. also includes the slotline, and can be measured independently using a calibrated VNA, as illustrated in Fig. 1(a). When a GUV flows above the slotline gap, the strong interaction between the electric field and GUV causes to be

refers to the substrate, e.g., where the subscript for fused silica, while the subscript stands for the carrier solution of the particle. Only the dielectric loss coming from the solution is considered in (6). The expressions for the capacitances in (5) and (6) are (7) (8) (9)

(10) The functions in (7)–(10) are incomplete elliptic integral of the first kind with variable as (2) where the subscript is for solution with a single GUV particle, as shown in Fig. 1(c). It is proven that for solutions with and without a single GUV, which have close permittivity values, can be solved using (1) and (2) when mismatches at the interfaces, as shown in Fig. 1(b), between microfluidic channel section of MUT/REF branch and transmission lines, are ignored [21]. For a solution with known permittivity, the propagation constant can be obtained from

(11) where metal film thickness is assumed to be negligible, is the gap width of the slotline, are thicknesses of substrate, solution, and PDMS layers, and a semiempirical expression for the quasi-static non-frequency-dependent approximation of distance is [29] (12)

(3) (4) The capacitance of a uniform slotline with the cross section shown in Fig. 1(c) can be approximated as the superposition

and . The obtained from (1) and (2) is used to extract the complex permittivity of the particle, where the expression for and are the same as (3) and (4) with different subscripts. The partial capacitances in (5) and (6) have to be modified to include the dielectric and physical properties of single particles. As shown in Fig. 6, the carrier solution layer

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is split into upper and bottom layers (subscripts: and ), and a particle-solution layer (subscript: ), where we assume that the particle can be treated as a cylinder to acquire the unit length capacitance using the conformal-mapping method. The validity of this assumption will be discussed in the third last paragraph of this section. Thus, and should be rewritten as

Fig. 6. Partition of the carrier layer (horizontal dash line), and magnetic wall (vertical dash line) with single GUV (solid circle with two meshed circles marked as microdomains on it).

(13) (14) where is the complex permittivity of the particle, and the expressions for the capacitances, and , are (15)

Fig. 7. Two-dimensional conformal mapping of particle-solution layer ( plane).

(16) The variables

and

in (15) and (16) are

(17)

(18) where and are the spherical-center coordinate and radius of the particle, respectively. It can be found from Fig. 6 that and with shown in Fig. 6. For the particle-solution layer, dielectrics in the mapped capacitance consist of two parts: the particle and carrier solution, as shown in Fig. 7. Transforms (1) and (2) in [29] are used to map the particle-solution layer from the plane to the plane. Capacitance is in the form of

where also a function of the angle

, and the coefficient

(19) is

(20)

In (19), the terms and represent the dielectric thicknesses for par-

Fig. 8. and case #1, m,

versus for: case #0, nm, m, m.

nm, m; case #2,

m,

m; nm,

ticle and solution, i.e., and in Fig. 7, respectively, corresponding to a given . Fig. 8 shows normalized and versus (from to ) for different ’s and ’s. The parameters for Case #0 in Fig. 8 will be used to extract complex permittivity in Section IV-C. Based on this, for Case #1 and #2 we changed and , respectively, to demonstrate their independent effect on and . Fig. 8 shows that: 1) the vertical position has a more significant effect than the radius through Case #0 and #1 and 2) the dielectric thickness in Fig. 7 increases with increased radius for the same vertical position through Case #1 and Case #2. The GUV sphere is treated as a cylinder, which may cause significant errors, partly due to increased volume. A coefficient fitting factor , which is also the volume ratio of the sphere and the approximated cylinder, is introduced to revise as . Thus, the dielectric property of the measured particle can be obtained. Fig. 9 summarizes the algorithm to obtain GUV permittivity values from -parameters.

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TABLE I PARAMETERS USED FOR ESTIMATING

Fig. 9. Algorithm to obtain GUV permittivity values from -parameters.

Fig. 10. Cross-sectional distributions of EM fields. Red semi-circle clusters: electric field; blue parabola clusters: magnetic field. The bold green circle indicates the location of the GUV particle ( – plane corresponding to the cross section in Fig. 1, and the origin is selected at the center of the gap).

The conformal-mapping method gives an intuitive and closed-form model for analyzing GUV permittivity from measured -parameters. Yet, conformal mapping is rigorous for the analysis of two-dimensional (2-D) dc systems or RF transverse-electromagnetic (TEM) systems. Although the slotline in Fig. 1 may be approximated as a quasi-TEM system for the targeted frequency band, which is relatively narrow, GUVs are, in fact, three-dimensional (3-D) objects. Therefore, the validity of the above model needs to be examined. This is accomplished by the experimental results presented in Section IV and by using a second modeling approach, discussed below. B. Perturbation Method We assume that the GUV particle in Fig. 1(c) only slightly perturbs the RF electric and magnetic fields of the slotline. Therefore, the unperturbed RF fields can be used to calculate the interactions between the GUV and the RF fields. As a result, the new propagation constants of the slotline section, in (1) and (2), can be obtained. So can the GUV properties. This assumption is reasonable since the RF properties of GUVs are expected to be close to those of the carrier liquids. It is possible to obtain an approximate, closed-form analytical solution of slotline RF fields (without GUVs). The fields can also be obtained using simulation tools, such as COMSOL Multiphysics tools. The time cost of a single simulation is acceptable. Fig. 10 shows the distributions of RF fields at the cross section in Fig. 1(c) with the dimensions given in Table I (only a part of the channel is shown), where (glucose-water solution at 2.8 GHz [30]). The green circle indicates the location of a GUV, which is not included in the simulation for Fig. 10.

Fig. 11. Approximating a 10- m-diameter sphere with 4999 cubes ( – plane corresponding to the cross section in Fig. 1).

With the obtained RF field data and [27, eqs. (2.17)–(2.20)], equivalent circuit parameters , , , and of the GUV loaded slotline can be obtained with a priori GUV properties. Corresponding and -parameters are obtained. This process is iterated with new GUV property values until the best match between the calculated and measured -parameters is achieved. The time cost of this numerical iteration approach is significantly lower than that of full wave simulations of RF fields for each iteration step. The following are the main considerations. The 10- m-diameter GUV sphere is divided into smaller elements (Fig. 11), which has 4999 cubes with a side length of 0.5 m, and 21 cubes along the diameter direction. A similar division is made for the carrier solution, not shown in Fig. 11. Along the -axis direction, there are 21 layers. For layer , the corresponding parameters , , , and can be calculated once their and are given,

(21)

(22) (23)

(24) where and are RF field intensities in the – plane, which are assumed to be uniform within one element; parameters and are the length and area of one element; the

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TABLE II ESTIMATED MINIMUM REQUIRED

subscript describes a GUV element while subscript for any non-GUV element, including solution, substrate, channel, PDMS, and air; parameter is determined by the boundary lines on conductors in Fig. 1(c). In this example, m, m , (two 800- m-long conductors), and for the first layer, (countable in Fig. 11), channel part (for a 1600 m 50 m channel); for other layers, and can also be found accordingly. The definitions for other parameters are the same as those in [27]. The propagation constant for each layer can then be solved by , and in Section III-A for the microfluidic channel with a single GUV can be considered as a set of . Thus the term in (2) can be expressed as (25) is the length of layer along the -axis, e.g., 0.5 m where in this example. The results from (25) are compared with measured results until the following conditions are satisfied with a set of , (26) (27) where , e.g., 0.0001, represents the error tolerance. In addition to extracting cell particle properties, the models above can also be used to rapidly predict the required for a given RF interferometer to measure a given particle using (28) Table II summarizes the estimations for different dielectric properties, where we choose (glucose–water solution at 2.8 GHz [30]), and is changed from to . The other parameters are given in Table I. The results indicate reasonable agreement between HFSS full-wave simulation and model analysis. The effects of particle radius and vertical position on the required can also be evaluated. It should be pointed out that higher sensitivity (or lower ) in actual measurements is always required because of system losses [i.e., in (2)], which is not considered in the above estimation. For Model #2, the RF electric and magnetic fields, as shown in Fig. 10, are simulated without the GUV. In reality, the GUV tends to change the field distribution around it due to the dielectric property difference between the GUV and the carrier solution. Thus, calculated using Model #2 is always lower than that using Model #1. Moreover, both Models #1 and #2

Fig. 12. Images of synthesized GUVs at different molecular compositions POPC/SM/Chol shown on a ternary composition diagram (hollow circle, I: 2/1/1; solid circle, II: 1/2/2; solid square, III: 8/1/1). Liquid-disordered phase : red; liquid-ordered phase : green.

are based on the assumption of quasi-static TEM while HFSS is based on full-wave analysis. They tend to obtain different results. The advantage of Model #2 is that there are no complex transformation expressions for conformal mapping, like (1) and (2) in [29]. The finite-element method (FEM)-based dc simulation to obtain the electric and magnetic fields and is relatively easy, even for some more complex structures for which there are no transformation expressions for conformal mapping. However, no closed-form analytical expression is obtained for Model #2 to describe the effect of every design parameter, e.g., , , , and in Fig. 1. IV. GUV SYNTHESIS AND RF MEASUREMENTS A. GUV Synthesis We adopt the electroformation method [31] for GUV synthesis. Chol (Cholesterol), POPC (16:0–18:1 PC 1-palmitoyl-2oleoyl-sn-glycero-3-phosphocholine), and SM (16:0 Egg Sphingomyelin) in chloroform are mixed at different mole fractions to form coexisting liquid-ordered phase and liquid-disordered phase (Group I), liquid-ordered phase (Group II), and liquid-disordered phase (Group III) [32], as shown in Fig. 12 obtained with an epi-fluorescence microscope with an ET-FITC/CY3 filter. Two fluorescent labels, Rho-PE(2dioleoyl-sn-glycero-3-phosphoethanolamine-N-(lissamine rhodamine B sulfonyl) (ammonium salt)) and DioC18 (3,3 -Dioctadecyloxacarbocyanine Percholorate) are used for liquid-disordered phase and liquid-ordered phase domains, respectively. Three groups of GUV particles are synthesized with different molecular compositions (molar fraction) of POPC/SM/ Chol: 2/1/1 (I), 1/2/2 (II), and 8/1/1 (III). The main electroformation steps are the following. After dropping 80- L Chol/lipids/labels mixture chloroform solution on a vacuum-desiccated indium tin oxide (ITO) glass, the liquid is spread out uniformly. An O-ring rubber is then placed on the glass, and sucrose-water solution at a 0.1-M concentration level is dropped in the O-ring area, which is sealed to form a chamber using a second vacuum-desiccated ITO glass. The rubber-glass chamber is placed into an incubator at a miscibility transition temperature of 60 C. A 1-V 10-Hz sinusoidal wave is applied across the ITO electrodes. Lipid bilayers are formed. They will spontaneously vesiculate in 2 h. GUVs are then suctioned up from the chamber and dropped into a 3-mL 0.1-M glucose-water solution for measurement.

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Fig. 13. Measurement setup for single GUVs.

Fig. 15. Time-dependent and corresponding when single GUV passing through the slotline gap.

(

GHz)

different for each set of GUV particles due to their different radii and vertical positions in the channel. C. RF Dielectric Properties of Single GUVs

Fig. 14. Measured

for Group I at

GHz.

B. RF Measurements of Single GUVs Glucose-water solutions at a 0.1-M concentration level with GUV particles are first injected into the PDMS channel in Fig. 1. The sensor is tuned to a desired sensitivity at each target frequency , i.e., a desired level before a GUV passes through the gap. A syringe pump is then used to drive the GUV through the channel and the slotline gap. The solutions are in a laminar flow and potential swirls of the fluid in the channel contributing to possible tumbling motion of the GUV can be neglected. A fluorescent microscope is used to observe the labeled GUV simultaneously. The measurement setup is shown in Fig. 13. The GUV induced -parameter changes are recorded by the VNA. The -parameter will return to the initial after the GUV moves away from the slotline. Fig. 14 shows two pairs (#1 and #2) of typical measurement results for Group I at 2.8 GHz. In each of the pairs, both the initial and maximally changed (corresponding to the GUV right above the gap) are shown together. The value of and its corresponding frequency changes with time, i.e., GUV position, are shown in Fig. 15. The figures show that our sensor is capable of detecting a single GUV with good sensitivity. In Fig. 15, the maximum response occurs when the GUV appears above the gap. Multiple frequency measurements can be achieved to analyze GUV dielectric properties at different frequencies by adjusting phase shifters and attenuators. The initial are adjusted between 100 and 105 dB. The maximum responses are

Fig. 16 shows the extracted real and imaginary permittivity components of different GUV particles for each group at 2, 2.5, and and 2.8 GHz. Both models in Section III are used to obtain the permittivity values. The parameters for the calculations are listed in Table I. We choose 5 and 6 m as the GUV radius and vertical center position, respectively. The 5- m average GUV radius value is estimated by comparing GUVs with the 50- m-wide PDMS channel observed under microscope. From microscope observations, it is also estimated that these GUVs are close to the slotline surface because the microscope is focused on the surface plane before the GUVs pass through the gap. The measured -parameters are then recorded when a GUV is observed to be close to the surface. The error bars indicate the distributions of five repeated, but separate, measurements. In each group of the GUVs with the same compositions, the GUVs are synthesized and then measured on the same day. It shows that: 1) the permittivity values of GUV particles are close to that of 0.1-M sucrose-water solution ( (at 2 GHz), (at 2.5 GHz), (at 2.8 GHz) through [33]), which is reasonable and serves to verify the validity of the proposed extraction method; 2) roughly the same results are obtained using the proposed Model #1 and #2 (the differences between the models have been further reduced with the use of ); and 3) the average and also vary with frequencies, which may carry molecular dynamic process information. Further work is needed to understand the details. The permittivity extraction and error range in Fig. 16 are from measuring five independent GUVs, which may have different diameters and vertical positions in the microfluidic channel. For each individual GUV particle, e.g., the one measured for Fig. 15, GUV size and vertical position are constant in the measurement process since the GUV only travels a very short distance. Using the measured -parameters at each time moment (i.e., longitudinal location), the obtained GUV permittivity with Model #2 is shown in Table III. The almost identical GUV permittivity values, which are expected because GUV radius and vertical

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TABLE IV EXTRACTED PERMITTIVITIES WHEN DIFFERENT R’s, SC’s, AND ’s ARE USED (UNIT: m FOR R’s, SC’s, AND ’s)

Fig. 16. Obtained real and imaginary permittivities and , of GUV particles for: (a) Group I (POPC/SM/Chol: 2/1/1), (b) Group II (POPC/SM/Chol: 1/2/2), and (c) Group III (POPC/SM/Chol: 8/1/1) at different frequencies (blue bold lines and small caps are for Model #1; red thin lines and big caps are for Model #2). TABLE III EXTRACTED PERMITTIVITIES AT DIFFERENT TIMES IN FIG. 15

Fig. 15 shows that the RF sensor can be used to perform a 1-D scanning of a GUV particle, hence, a biological cell in the future. The scanning process may be further investigated to provide GUV surface domain structure information at high spatial resolution (e.g., 100 nm) since GUV vertical position can be approximated as a constant therein. A potential issue with the system in Fig. 1 is the strong RF field effects on GUV lipids, e.g., thermal effect, which can be estimated by use of equations [27, eq. (2.95)] and [34, eq. (3)]. The results show a 432 C/s temperature change rate, which is probably not realistic. This needs to be explored in the future. In our measurement, we observed that GUV shapes do not change before and after passing though the slotline gap, which is consistent with the results in Fig. 15. Moreover, it was proven that the high fields do not damage GUVs (hence, cells) appreciably [35]. V. CONCLUSIONS

position do not induce relative error, further verify the validity of the model. D. Discussion The high intensity electric field of the NSL strongly interacts with GUV particles so that significant changes of in magnitude and phase can be observed. High sensitivity operations enable high measurement accuracies, which are critical for detecting and observing subtle biological and physical processes in cells and GUVs as well as for identifying potential markers. Nevertheless, a few factors, such as the uncertainties of GUV radius, shape, and vertical position (i.e., in Fig. 6), need to be addressed in the future. The estimated effects of these factors are listed in Table IV. The data show that the GUV vertical position has more significant effects than the uncertain radius on the interaction.

We have presented an interferometer based RF sensor with 100-nm slotlines. The sensor is highly sensitive and tunable in both operating frequency and sensitivity. Models are established and verified to obtain the RF properties of particles in carrier solution from measured scattering parameters. GUVs with different molecular compositions are synthesized, tested, and analyzed with the sensor. The results show that the sensor can detect and scan GUVs at multiple frequency points, and the average dielectric properties of the GUV particles extracted with the two models agree with each other reasonably well. It is expected that the sensor can be further developed, including measurement accuracy improvement, for GUV and cell investigations. ACKNOWLEDGMENT The authors appreciate Dr. C. A. Day and Dr. P. J. Barrett, both with Vanderbilt University, for helping in GUV synthesis, and Dr. T. Darroudi, Clemson University, for helping in FIB etching. REFERENCES [1] T. Sun and H. Morgan, “Single-cell microfluidic impedance cytometry: A review,” Microfluid Nanofluid, vol. 8, no. 4, pp. 423–443, Mar. 2010.

CUI et al.: ANALYZING SINGLE GUVs WITH SLOTLINE-BASED RF NANOMETER SENSOR

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Yan Cui, photograph and biography not available at the time of publication.

Anne K. Kenworthy, photograph and biography not available at the time of publication.

Michael Edidin, photograph and biography not available at the time of publication.

Ralu Divan, photograph and biography not available at the time of publication.

Daniel Rosenmann, photograph and biography not available at the time of publication.

Pingshan Wang, photograph and biography not available at the time of publication.

Digital Object Identifier 10.1109/TMTT.2016.2547499

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