Electronic Devices and Circuits [5 ed.] 9780195693409, 019569340X

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5lectronic Devices and Circuits Fifth Edition

DAVID A. BELL

OXFORD UNIVERSITY

PRESS

OXFORD UNIVERSITY

PRESS

Oxford University Press is a department of the University of Oxford. It furthers the University’s objective of excellence in research, scholarship,

and, education by publishing worldwide. Oxford is a registered trademark of Oxford University Press in the UK and in certain other countries. Published in India by Oxford University Press

Ground Floor, 2/11, Ansari Road, Daryaganj, New Delhi, 110 002, India

Original fifth edition published by and © Oxford University Press, 70 Wynford Drive, Don Mills, Ontario, Canada.

Previous editions published by Prentice-Hall, Inc. This adapted edition first published in 2008 by Oxford University Press, India © Oxford University Press 2008 The moral rights of the author/s have been asserted. First published 2008

23™ impression 2017 All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, without the prior permission in writing of Oxford University Press, or as expressly permitted by law, by licence, or under terms agreed with the appropriate reprographics rights organization. Enquiries concerning reproduction outside the scope of the above should be sent to the Rights Department, Oxford University Press, at the address above. You must not circulate this book in any other form

and you must impose this same condition on any acquirer.

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PREFACE An

understanding

of electronic

achieved by learning how

devices

and

circuits can most

easily be

to design circuits. Practical circuit design is

usually quite simple, much simpler than some methods of circuit analysis.

The objectives of this book, therefore, are to provide clear explanations of the operation of all the important electronic devices generally available today, to show how each device is used in appropriate circuits, and to demonstrate

_ how such circuits are designed. About the Book

This fifth edition is intended for undergraduate

engineering courses in

electrical and electronics, instrumentation and control, and electronics and

instrumentation as well as a reference text for practising professionals. Beginning with basic semiconductor and pn junction theory, the book explains how each device operates, discusses device characteristics and parameters, and presents appropriate circuit applications. Circuit design and

analysis methods are extensively treated, using currently available devices, standard-value components, and parameters from device manufacturers’ data sheets. The text includes many practical examples. The circuit design procedure mostly involves determining appropriate current and voltage levels, and then applying Ohm’s law and the capacitor

impedance equation. All circuits can be laboratory tested (and/or computer analyzed) to check the authenticity of the design process. Conventional current direction is used because it is the direction normally employed by device

and

integrated

graphic symbol direction.

circuit

manufacturers;

uses an arrowhead

also,

because

every

that indicates conventional

device

current

To reinforce application-based learning and help students assimilate the

concepts, each chapter contains numerous section-wise practice problems, review questions, and problems. The book also provides answers to all practice problems and selected end-chapter problems. New to the Fifth Edition

The text has been revised based on the syllabuses of various universities throughout the world, including those in India. A major addition is a new chapter on active filters, treating low-pass and high-pass, band-pass, notch,

all-pass, state variable, and switched capacitor filters. The chapter covers filter types, circuits, and characteristics as well as filter design examples.

iv

Preface

This edition also covers BJT switching time improvements, the 555 timer as a pulse generator, circuit testing and troubleshooting methods, RC and LC power supply filters, tuned circuit amplifiers, photomultiplier tube, and the laser diode.

class

C

amplifiers,

the

Coverage and Organization | The text has been organized into 22 chapters. Chapter 1 presents the basic semiconductor and pn-junction theory necessary for an understanding of the operation of electronic devices. Chapter 2 covers the operation, characteristics, parameters, and specifi-

cations of semiconductor diodes. Diode load line analysis, ac models, power

dissipation derating, and testing methods are also treated. The Zener diode

is introduced, explained.

and

its operation,

characteristics,

and

parameters

are

Chapter 3 presents diode applications such as half-wave and full-wave

rectification, RC and LC filters and L-input filters for dc power supplies, Zener diode voltage regulators, clipping and clamping

circuits, voltage

multipliers, and diode logic circuits. The calculation of the required filter

capacitor ‘and inductor values for a given rectifier power supply output voltage, load, and ripple is demonstrated with practical design examples. The chapter also includes examples to show how to determine component values for basic voltage regulators, clipping circuits, etc. DC power supply performance and testing are also covered. Chapter 4 introduces the bipolar junction transistor (BJT), and treats BJT

operation, currents, voltages, current amplification, voltage amplification, switching, and testing. Common base, common emitter, and common collector characteristics are also explained.

Chapter 5 completely demystifies practical BJT bias circuit design and

analysis. The chapter includes bias circuit design (for linear and switching circuits), dc load line analysis, thermal stability, and troubleshooting. _ Chapter 6 explains coupling. and bypass capacitors and ac load line analysis for BJT circuits. The three basic BJT circuit configurations are analyzed using h-parameters to derive equations for voltage gain, input impedance, and output impedance. The Ebers-Moll model is also treated in

this chapter. Chapter 7 explains manufacturing methods for diodes, transistors, and integrated circuits, and the effect of the fabrication method on device performance (frequency, switching, power

dissipation). Device packaging

and terminal identifications are also treated. Chapter 8 covers BJT data sheets, decibels and half-power points, device and circuit frequency response, switching times, circuit noise, device power

dissipation, and heat sink selection.

Preface

v

Chapter 9 explains the operation and construction of JFETs and MOSFETs. FET characteristics and parameters for n-channel and p-channel devices are

also covered, as well as FET amplification and switching. Chapter 10 demonstrates practical JFET and MOSFET bias circuit design and analysis, using graphical and calculation methods

and the universal

transfer characteristic. DC load line analysis and FET bias circuit troubleshooting are also treated. Chapter 11 commences with coverage of coupling and bypass capacitors and ac load line analysis for FET circuits, then treats FET models and parameters. The three basic FET circuits are analyzed for voltage gain, input

impedance, and output impedance. Chapter

12

offers

a

thorough

treatment

of

small-signal

amplifiers.

Complete design and analysis examples are presented, including the determination of all resistor and capacitor values and the selection of standard-value components. The circuits studied include the single-stage common-emitter BJT amplifier, single-stage common-source FET amplifier,

two-stage capacitor-coupled and direct-coupled BJT and BIFET amplifiers, differential amplifier, BJT cascode amplifier, and tuned circuit amplifiers. Chapter 13 explains the use of series voltage negative feedback (NFB), emitter current NFB, and parallel current NFB. The effects of NFB on amplifier gain, input and output impedance, bandwidth, etc., are all treated. The application of NFB in a variety of amplifier circuits is demonstrated in many practical circuit examples. Chapter 14 explains op-amp basics, parameters, and biasing considerations for both bipolar and BIFET op-amps. The voltage follower, noninverting amplifier, and inverting amplifier are all thoroughly covered as well as: summing amplifier, difference amplifier, instrumentation amplifier, voltage level detector, and Schmitt trigger. Chapter 15 covers op-amp circuit instability due to feedback, and discusses op-amp gain/frequency and phase/frequency responses and compensation methods. Also treated are: gain/bandwidth product, full

power bandwidth, slew rate, and the effects of stray and load capacitance.

Chapter 16 explains (op-amp and BJT) phase-shift, Colpitts, Hartley, and Wein bridge oscillators, and demonstrates how to design oscillator circuits for a given frequency. Oscillator amplitude stabilization methods are also treated as well as the use of crystals for frequency stabilization. Square wave

and triangular wave generators and the use of the 555 timer as a pulse generator are covered. Chapter 17 treats filter types and characteristics and design methods for

the following op-amp active filters: first-order, second-order and third-order low-pass

and

high-pass,

switched-capacitor.

band-pass,

notch,

allpass,

state-variable,

and

vi

Preface

yChapter

18 explains

the

operation

and

design

of BJT

series

voltage

regulators using a simple circuit with two transistors and a Zener diode through

highly

stable

adjustable

output

circuits

with

pre-regulators,

overload protection, and output current limiting. The operation and advantages of step-up, step-down, and inverting switching regulators are also covered. Chapter

19 treats class A, class B, class AB,

and

class

C

transformer-

coupled, capacitor-coupled, and direct-coupled (BJT and MOSFET) power amplifiers, and shows how to analyze and design such circuits. The chapter also explains the application of a variety of integrated circuit power amplifiers. >,Chapter 20 covers important thyristor devices and their circuit applications including the SCR, DIAC, TRIAC, SUS, SBS, GTO, UJT, and PUT. The operation, characteristics, parameters, and circuit applications of each device are explained. Chapter 21 covers light-emitting diodes, photoconductive cells, photo-

diodes, solar cells, phototransistors, optocouplers, photomultiplier tube, and laser diodes. Chapter 22 covers the VVC diode, thermistor, tunnel diode, Schottky diode, PIN diode, and current limiting diode. Appendix A covers device data sheets, Appendix B gives standard-value components, and Appendix C provides answers to odd-numbered problems.

Iam always grateful for suggestions that might improve my presentation of the material, or for additional topics that should be treated. Comments concerning this book would be very welcome. DAVID

BELL

CONTENTS Preface Chapter 1 1-1 1-2

Basic Semiconductor and pn-Junction Theory

Atomic Theory The Atom 2; Electron Orbits and Energy Levels 3; Conduction in Solids Electron Motion and Hole Transfer 5;

Energy Bands 5

Conventional Current and

Electron Flow 7 1-3

Conductors, Semiconductors, and Insulators

Bonding Forces between Atoms 8; 1-4

Energy Bands in Different Materials 9 10

n-Type and p-Type Semiconductors

Doping 10; n-Type Material 11; p-Type Material 11; Majority and Minority Charge Carriers 12; Effects of Heat and Light 13; Charge Carrier Density 14 1-5 Semiconductor Conductivity Drift Current 16;

Diffusion Current 17;

16

Charge Carrier Velocity 17;

Conductivity 18 20

The pn-Junction

Junction of p-Type and n-Type 20; 1-7

Barrier Voltage 21;

Depletion

Region 21; Summary 22 Biased Junctions Reverse-Biased Junction 23;

23 Forward-Biased Junction 24;

Junction

Temperature Effects 25 Junction Currents and voltages

Shockley Equation 27; Chapter 2 2-1 2-2 2-3

27

Junction Current 28;

29 33

Semiconductor Diodes

pn-Junction Diode

34

Characteristics and Parameters Forward and Reverse Characteristics 35;

35 Diode Parameters 37

Diode Approximations

39

Ideal Diodes and Practical Diodes 39; DC Equivalent Circuits 41 2-4

Junction Voltage

Piecewise Linear Characteristic 40;

DC Load Line Analysis DC Load Line 42;

Q-Point 44;

42. Calculating Load Resistance and

Supply Voltage 44 2-5

Temperature Effects Diode Power Dissipation 47; Resistance 49

47

Forward Voltage Drop 48;

Dynamic

vill_Contents 2-6

Diode AC Models

i

Junction Capacitances 50;

_ Forward-Biased) 51;

50

AC Equivalent Circuits (Reverse-Biased and

Reverse Recovery Time 52

2-7 Diode Specifications

53

Diode Data Sheets 53;

Low-Power Diodes 55;

‘2-8 Diode Testing

Ohmmeter Tests 56;

Use of a Digital Meter 57;

Characteristics 57 , 2-9

tics and Parameters 61;

59

Circuit Symbol and Package 60;

Data Sheet 62;

Characteris-

Equivalent Circuit 64

Diode Applications

3-1 Half-Wave Rectification Positive Half-Wave Rectifier 72; 3-2

56

Plotting Diode

a?

Zener Diodes Junction Breakdown 59;

Chapter 3

Rectifier Diodes 55

Full-Wave Rectification Two-Diode Full-Wave Rectifier 75; Rectifier Circuits 79

71 72 Negative Half-Wave Rectifier 74 Bridge Rectifier 77;

More Bridge

3-3 Half-Wave Rectifier Power Supply Capacitor Filter Circuit 80; Ripple Amplitude and Capacitance 81; Approximate Calculations 82; Capacitor Selection 83; Capacitor Polarity 84;

Diode Specification 86;

~ 3-4 Full-Wave Rectifier Power Supply

75

80

Transformer Selection 88

90

Transformer Selection 94 3-5

3-6

RC AND LC POWER SUPPLY FILTERS RC 7 FILTER 95; LC 7 Filter 97; L-Input Filter 99;

95 Advantages and

Disadvantages 102 Power Supply Performance and Testing Source Effect 103;

Load Effect 104;

Circuits and Open Circuits 105;

Test Procedure 104;

103 Short

Possible Faults and Remedies 106;

Using an Oscilloscope 106 3-7

108

Zener Diode Voltage Regulators

Regulator Circuit with No Load 108; Loaded Regulator 109; Regulator Performance 110 3-8 Series Clipping Circuits Series Clipper 113; Current Level Selection 115; Series Noise Clipper 115 . . 3-9 Shunt Clipping Circuits Shunt Clipper 116; Shunt Noise Clipper 117; Biased Shunt Clipper 118; Zener Diode Shunt Clipper 119 . 3-10 Clamping Circuits Negative and Positive Voltage Clamping Circuits 121; Output Slope 122; Component Determination 123;

Biased Clamping Circuit 125;

Diode Clamping Circuit 127 3-11

DC Voltage Multipliers Voltage Doubler 128; Multi-Stage Voltage Multipliers 131

113 116

121

Zener

128

Contents

3-12

Diode Logic Circuits AND

Gate 132;

Chapter 4 4-1

ix

132

OR Gate 133

Bipolar Junction Transistors

143

4-2

BJT Operation pnp and npn Transistors 144; npn Transistor Operation 145; pnp Transistor Operation 148; Bipolar Devices 148; Summary 149 BJT Voltages and Currents

150

4-3

Terminal Voltages 150; BJT Amplification

154

Transistor Currents 151

Current Amplification 154;

Voltage Amplification 155

4-4

BJT Switching

4-5

Diode-Connected BJT 158; BJT Saturation 159 Common-Base Characteristics Common-Base Circuit 161; Common-Base Input Characteristics 162;

158

Common-Base Output Characteristics 162; Gain Characteristics 164 4-6

144

; 161

Common-Base Current

Common-Emitter Characteristics

166

Common-Emitter Circuit 166; Common-Emitter Input Characteristics 166; Common-Emitter Output Characteristics 167; Common-Emitter 4-7

4-8

Current Gain Characteristics 169 Common-Collector Characteristics Output and Current Gain Characteristics 170;

170 Common-Collector

Circuit 171; Common-Collector Input Characteristics 171 Transistor Testing

172

In-Circuit Testing 172; Ohmmeter and Digital Multimeter Tests 172; Characteristic Plotting 173 Chapter 5

5-1

181 Selection of Q-point

Effect of Emitter Resistor 187

188

Base Bias

Circuit Operation and Analysis 188; 5-3

180

DC Load Line and Bias Point DC Load Line 181; DC Bias Point (Q-Point) 183; 185;

5-2

BJT Biasing

Base Bias Using a Collector-to-Base Circuit Operation Collector-to-Base

Effect of Apg(max) and hpE(min) 189;

pnp Transistor 190 Bias and Analysis 192; Effect of hpgamaxy) and MFE(min) 193; Bias Using a pnp Transistor 195

5-4 Voltage-Divider Bias Circuit Operation 196;

Circuit Analysis 198; 5-5 Comparison of Basic 5-6 Troubleshooting BJT Voltage Measurement

Approximate Circuit Analysis 197;

196

Precise

Voltage-Divider Bias Using a pnp Transistor 202 Bias Circuits Bias Circuits 205; Common Errors 205; Open-Circuited and

Short-Circuited Components 205; Base Bias 206; Bias 206; Voltage-Divider Bias 207

192

Collector-to-Base

203 205

x,

Contents

5-7

Bias-Circuit Design

207

Base Bias Circuit Design 207; Collector-to-Base Bias Circuit Design 209; Voltage-Divider Bias Circuit Design 210; Designing with Standard Resistor Values 212: 5-8

More Bias Circuits Base Bias and Collector-to-Base Bias with Emitter Resistors 213;

Voltage-Divider and Collector-to-Base Combination 213; Current Bias 215 Thermal Stability of Bias Circuits Vee and Icgo Variations 218; Stability Factor 219;

213

Emitter218

Effect of Vg

Changes 222; Diode Compensation 223 5-10 Biasing BJT Switching Circuits _ Direct-Coupled Switching Circuit 224; Capacitor-Coupled Switching Circuit 227; Switching Circuit Design 228 Chapter 6 6-1

AC Analysis of BUT Circuits

238

Coupling and Bypassing Capacitors Coupling Capacitors 239; AC Degeneration 241; Capacitor Polarity 242

239

Emitter Bypassing 241;

AC Load Lines

243

AC Equivalent Circuits 243; AC Load Lines 243; Swing 246 Transistor Models and Parameters T-Equivalent Circuit 246; 247;

6-4

224

h-Parameters 248;

r-Parameters 247;

The Output Voltage 246

Determination of re

Tp Equivalent Circuit 249;

Definition of

h-Parameters 249;

Common-Base and Common-Collector

h-Parameters 252;

Parameter Relationships 252 254

Common-Emitter Circuit Analysis Common-Emitter Circuit 254;

h-Parameter Equivalent Circuit 254;

Input Impedance 255; Output Impedance 256; Voltage Gain 256; Current Gain 257; Power Gain 258; Summary of Typical CE Circuit Performance 258 CE Circuit with Unbypassed Emitter Resistor

h-Parameter Equivalent Circuit 259; Impedance 261; Voltage Gain 261;

259

Input Impedance 260; Output Performance Summary for CE

Circuit with Unbypassed Rx 261 6-6

263

Common-Collector Circuit Analysis

Common-Collector Circuit 263; Input Impedance 264;

f-Parameter Equivalent Circuit 264;

Output Impedance 265;

Voltage Gain 266;

Summary of CC Circuit Performance 266 6-7

Common-Base Circuit Analysis Common-Base Circuit 268; h-Parameter Equivalent Circuit 269;

Impedance 270;

Output Impedance 270;

Effect of Unbypassed Base Resistors 271;

Performance 271

Voltage Gain 270

Summary of CB Circuit

268

Input

Contents

6-8

Comparison of CE, CC, and CB Circuits

xi

274

Impedance at the Transistor Base 275; Impedance at the Transistor Emitter 275; Impedance at the Transistor Collector 276; Voltage gain 276 6-9

Ebers-Moll BJT MODEL

Chapter 7 7-1

278

Fabrication of Semiconductor Devices andiCs

Processing of Semiconductor Materials

288 289

Preparation of Silicon and Germanium 289;

Diffusion 289;

Epitaxial

Growth 290

7-2 Diode Fabrication and Packaging 7-3

Alloy and Diffused Diodes 290; Diode Packaging 291 Transistor Construction and Performance Current Gain 292;

High Power 293;

Switching Transistors 293; 7-4

290

Frequency Response 293;

Breakdown and Punch-Through 293

Transistor Fabrication

294

Alloy Transistors 294;

Microalloy Transistors 295;

Diffused Transistors 295;

Diffused Mesa 296;

Diffused Planar Transistor 297;

Microalloy-

Epitaxial Mesa 296;

Annular Transistor 297

7-5 Integrated Circuits IC Types 298; Monolithic Integrated Circuits 298; 7-6

292

298 Thin Film 298;

Thick Film 299; Hybrid 300 IC Components and Circuits Transistors and Diodes 300;

300

Circuits 301;

Resistors 302;

Capacitors 302

7-7 Transistor and IC Packaging

303

Discrete Transistor Packaging 303; Chapter 8

IC Packages 304

BJT Specifications and Performance

307

8-1

Transistor Data Sheets

308

8-2

Decibels and Half-Power Points

311

Power Measurement in Decibels 311;

8-3

BJT Cutoff Frequency and Capacitances Device Cutoff Frequency 314;

8-4

Half-Power Points 313;

Junction Capacitances 314;

on CE and CB Circuits 318;

Follower 320;

317

Input-Capacitance Effect

Input-Capacitance Effects on Emitter

Stray Capacitance 320 322

Transistor Switching Times Turn-On Times 322;

Frequency 324; 8-6 8-7

Miller Effect 316

BJT Circuit Frequency Response

Coupling and Bypass Capacitor Effects 317;

8-5

314

Turn-Off Times 323;

Rise Time and Cutoff

Switching Time Improvement 324 327 332

Transistor Circuit Noise Transistor Power Dissipation

Maximum Power Dissipation 332;

Maximum Power Dissipation

Curve 334 8-8

Heat Sinking

336

xii_

Contents

Chapter 9 9-1

Field Effect Transistors

Junction Field Effect Transistors n-Channel JFET 346; p-Channel JFET 347;

Packaging 348 9-2, JFET Characteristics ~~ Depletion regions 349;

345 346 JFET Fabrication and 349

Drain Characteristics with Vos = 0 350;

Characteristics with External Bias 351; p-Channel JFET Characteristics 355

Drain

Transfer Characteristics 354;

9-3 JFET Data Sheets and Parameters Maximum Ratings 356; Saturation Current and Pinch-off Voltage 357; Forward Transfer Admittance 360; Output Admittance 362; DrainSource on Resistance 363; Gate Cutoff Current and Input Resistance 363;

Breakdown Voltage 363;

Noise Figure 363

Capacitances 364

9-4 FET Amplification and Switching Amplification 364; FET Switching 366

9-5 MOSFETs

356

364

|

367

Enhancement MOSFET 367; Depletion-Enhancement MOSFET 369; VMOSFET 371; Comparison of n-Channel and p-Channel FETs 374;

Handling MOSFETs 375 Chapter 10 10-1 10-2

380

FET Biasing

DC Load Line and Bias Point DC Load Line 381; Bias Point (Q-Point) 382; Gate Bias Circuit Operation 385;

Effect of Source Resistor 384

Circuit Analysis 386

Gate Bias for a p-Channel JFET 388 10-3 Self-bias Circuit Operation 388; Circuit Analysis 389;

Self-Bias for a p-Channel

JFET 391

10-4

Voltage-Divider Bias Circuit Operation 392;

Circuit Analysis 392;

Voltage-Divider Bias for

a p-Channel JFET 395 10-5 Comparison of Basic JFET Bias Circuits 10-6 Troubleshooting JFET Bias Circuits Common Voltage Measurement 397; Voltage-Divider Bias 398 Bias 398;

10-7

Errors 397;

395 397 Gate Bias 397;

399

JFET Bias Circuit Design

Circuit Design Approach 399; Gate Bias Circuit Design 400; Self-Bias with Design 402; Voltage-Divider Bias Circuit Design 404; Designing Standard-Value Resistors 407

10-8

10-9

Self-

More JFET Bias Circuits Use of Plus/Minus Supplies 408; Current Bias 410

408 Drain Feedback 408;

Constant-

Use of Universal Transfer Characteristic Universal Transfer Characteristic 413; Circuit Analysis 414

413

Contents

xiii

10-10 MOSFET Biasing

417

DMOS Bias Circuits 417; EMOS Bias Circuits 418 10-11 Biasing FET Switching Circuits

421

JFET Switching 421;

Direct-Coupled JFET Switching Circuit 421;

Capacitor-Coupled JFET Switching Circuits 422;

MOSFET

Switching 423 Chapter 11

=AC Analysis of FET Circuits

435

11-1

Coupling, Bypassing, and AC Load Lines Coupling Capacitors 436; Bypassing Capacitors 436; AC Load Lines 436 11-2 FET Models and Parameters FET Equivalent Circuit 438; Equivalent Circuit Parameters 439 11-3 Common-Source Circuit Analysis Common-Source Circuit 439; Common-Source Equivalent Circuit 440; Input Impedance 440; Output Impedance 441; Voltage Gain 442; Summary of Typical CS Circuit Performance 442 11-4 CS Circuit with Unbypassed Source Resistor Equivalent Circuit 444; 445; Voltage Gain 446;

436 438 439

444

Input Impedance 444; Output Impedance Summary of Performance of CS Circuit with

Unbypassed Rs 447 11-5

Common-Drain Circuit Analysis

Common-Drain Circuit 448; Input Impedance 450;

448

Common-Drain Equivalent Circuit 449;

Output Impedance 450;

Voltage Gain 451;

Summary of CD Circuit Performance 451 11-6

Common-Gate Circuit Analysis Common-Gate Circuit 452;

452

Common-Gate Equivalent Circuit 453;

Input Impedance 454; Output Impedance 454; Voltage Gain 454; Effect of Unbypassed Gate Resistors 455; Summary of CG Circuit Performance 456

.

11-7 Comparison of FET and BJT Circuits CS, CD, and CG Circuit Comparison 457; Gate 457; Drain 458;

11-8

457 Impedance at the FET

Impedance at the FET Source 458; Impedance at the FET Voltage Gain 458; FET-BJT Circuit Comparison 460

Frequency Response of FET Circuits Low-Frequency Response 460; High-Frequency Response 461

Chapter 12

469

=Small-Signal Amplifiers

470

12-1 Single-Stage Common-Emitter Amplifier Specification 470;

Selection of Ic, Rc, and Rg 470;

Bypass Capacitor 472; Coupling Capacitors 475; 476; Design Calculations 476 12-2 Single-Stage Common-Source Amplifier Specification 479;

Capacitors 481;

Selection of Ip, Rp, and Rg 479;

Design Calculations 483

460

Bias Resistors 471;

Shunting Capacitors 479 Bias Resistors 481;

xiv_

12-3 12-4

Contents.

.Capacitor-Coupled Two-Stage CE Amplifier Circuit 485; Circuit Design 486; | Circuit Analysis 487

485

Direct-Coupled Two-Stage Circuits

490

Direct-Coupled Circuit 490; Circuit Design 490; 493;. Use of Complementary Transistors 495 12-5

Circuit Analysis

Two-Stage Circuit with Emitter Follower Output Circuit 496

496

12-6 DC Feedback Pair DC Feedback Pair with Two Amplification Stages 500; DC Feedback ~ Pair with Emitter Follower Output 502 12-7 BIFET Circuits BJT-FET Considerations 505; Capacitor-Coupled BIFET Amplifier 505; Direct-Coupled BIFET Amplifier 506; Design Calculations 507 12-8 Differential Amplifier Differential Amplifier Circuit 510; AC Operation 512; Voltage Gain 512; Input and Output Impedances 514; DC Amplification 514; Design Calculations 515 12-9 Small-Signal High-Frequency Amplifiers Common-Base Amplifier 518;

Cascode Amplifier 519;

505

510

518

Design

Calculations 520; Differential Amplifier as a High-Frequency Amplifier 523 12-10 TUNED CIRCUIT AMPLIFIERS Tuned Amplifiers 524; Tuned Amplifier with a Capacitor-Coupled Load 524; Tank Circuit Component Selection 527; Inductively Coupled. Load with Tuned Primary 527; Amplifier with Tuned Primary and Tuned Secondary 529 12-11 Amplifier Testing Preparation 532; Instability 532; DC Voltage Measurements 533, AC Testing 534; Input and Output Impedances 535 Chapter 13

500

524

532

544

Amplifiers with Negative Feedback

Series Voltage Negative Feedback Negative Feedback Concept 545; Voltage Gain 546; Input Impedance 548; Input Impedance with Bias Resistors 549, Output Impedance 550;

545

Two-Stage CE Amplifier with Series Voltage Negative Feedback Negative Feedback Amplifier Circuit 553; Negative Feedback Amplifier Design 556 ack a. 3 More Amplifiers with Series Voltage Negative Feedb 559; DC — ack Complementary Direct-Coupled Circuit with Feedb tage Circuit Feedback Pair Using Negative Feedback 561; BIFET Two-S Cutoff wita Negative Feedback 561; Setting the Circuit Upper

553

13-1

Output Impedance with a Collector Resistor 551

13-2

requency 562

4

Differential Amplifier with Negative Feedback ‘lwo-Stage Differential Amplifier 563; Operation 564;

Circuit Design 565;

DC Bias Conditions 563;

aso

2

5 AC

Modification for Reduced Zout 567

Contents

13-5

Emitter Current Feedback Emitter Current Feedback Circuit 569;

xv

569 Circuit Design 571;

Two-Stage

Circuit with Emitter Current Feedback 572

13-6 Parallel Current Negative Feedback Current Feedback Circuit 576;

Impedances 578; 13-7

576

Current Gain 577;

Output and Input

Circuit Design 579

Additional Effects of Negative Feedback Decibels of Feedback 581; Attenuation Distortion 584;

Bandwidth 581; Phase Shift 584;

581 Harmonic Distortion 583; Noise 586;

Circuit

Stability 586

Chapter 14

‘IC Operational Amplifiers and Basic

592

Op-Amp Circuits 14-1 Integrated Circuit Operational Amplifiers Circuit Symbol and Packages 593; Basic Internal Circuit 593; Important Parameters 594

593

14-2 Biasing Operational Amplifiers Biasing Bipolar Op-amps 595; Biasing BIFET Op-amps 599

595

14-3

600

14-4

Voltage Follower Circuits Direct-Coupled Voltage Follower 600; Follower 602 Non-inverting Amplifiers

Capacitor-Coupled Voltage

Direct-Coupled Non-Inverting Amplifier 604; 14-5

14-6 14-7

14-8

Capacitor-Coupled

Non-Inverting Amplifier 607 Inverting Amplifiers Direct-Coupled Inverting Amplifier 608; Capacitor-Coupled Inverting Amplifier 610 Summing Amplifier Difference Amplifier Circuit Operation 613; Input Resistances 614; Common-Mode Voltages 616 Instrumentation Amplifier

Circuit Operation 617; 14-9

604

608

611 613

617

Voltage Gain 618

Voltage Level Detectors

621

Op-amps in Switching Applications 621; Zero Crossing Detector 622 14-10 Schmitt Trigger Circuits Inverting Schmitt Trigger 624; Triggering Points 625; Input/Output

624

Characteristic 625; Circuit Design 626; Adjusting the Trigger Points 627; Non-Inverting Schmitt Trigger 628

14-11 Testing and Troubleshooting Op-amp Circuits DC Voltages 631; AC Gain and Frequency Response 632; Circuits 632

631 Switching

xvi

Contents

Chapter 15 15-1

15-2

15-3

Operational Amplifier Frequency Response and Compensation

Operational Amplifier Circuit Stability Loop Gain and Loop Phase Shift 640; Uncompensated Gain and Phase Response 641; Compensated Op-amp Gain and Phase Response 642; Amplifier Stability and Gain 643 Frequency Compensation Methods Phase-Lag and Phase-Lead Compensation 646; Manufacturer’s Recommended Compensation 647; Miller-Effect Compensation 648 Op-amp Circuit Bandwidth and Slew Rate Low Cutoff Frequency 649; High Cutoff Frequency 650; Gain-Bandwidth Product 651; Full-Power Bandwidth and Slew Rate 653 Stray Capacitance Effects Load Capacitance Effects

15-4 15-5 15-6 Circuit Stability Precautions Power Supply Decoupling 660; Chapter 16 16-1

16-3

BJT Phase Shift Oscillator 670

Op-Amp Colpitts Oscillator Design 675

BJT Hartley Oscillator 677

Oscillator Amplitude Stabilization

684;

657

Op-Amp Phase Shift Oscillator

Wein Bridge Oscillator

Oscillator 681;

655

666

Hartley Oscillators

Output Amplitude 681;

649

665

BJT Phase Shift Oscillator 669;

Op-Amp Hartley Oscillator 675; 16-4 16-5

646

660

Phase Shift Oscillators Op-Amp Phase Shift Oscillator 666;

Design 670 16-2 Colpitts Oscillators Op-Amp Colpitts Oscillator 670; 672; BJT Colpitts Oscillator 674

640

Stability Precautions 660

Signal Generators

Design 667;

639

678 681

Diode Stabilization Circuit for a Phase Shift

Diode Stabilization Circuit for a Wein Bridge Oscillator

FET Stabilization Circuit for a Wein Bridge Oscillator 684;

Design of a FET Stabilization Circuit 686 16-6 Square Wave Generator 16-7 555 Pulse Generator

688 690

Component Values Pulse Generator 692; Timer Block Diagram 690; Voltage-Controlled Square Wave Generator 694; 693; Duty Cycle 694;

Oscillator 696 16-8

Triangular Wave Generator Integrator 697;

Integrator Combined with Schmitt Trigger 698;

Circuit Design 699 16-9

697

Oscillator Frequency Stabilization Frequency Stability 701; Piezoelectric Crystals 701; Crystal Equivalent Circuit 702; Crystals Control of Oscillators 703

701

Contents

Chapter 17 17-1

17-2

711

= Active Filters

712

Filter Types and Characteristics

Low-Pass 712;

xvii

High-Pass 713;

Band-Pass 713;

Notch 713;

Filter

Characteristics 714 First-Order Active Filters

717

First-Order Low-Pass Filter 717; First-Order High-Pass Filter 718 17-3 Higher-Order Active Filters Falloff Rate 720; Filter Design Categories 721; Second-Order Low-

720

Pass Active Filter 722 17-4 17-5

Second-Order High-Pass Active Filters Third-Order Active Filters

Third-Order Low-Pass filter 728; 17-6

125 728

Third-Order High-Pass Filters 729 731

Band-Pass Filters Multi-Stage Band-Pass Filter 731; Single-Stage Band-Pass Filter 731; Bandwidth 735; Narrow-Band Single-Stage Band-Pass Filter 736

17-8

Notch Filters All-Pass Filters

17-9

Phase-Lag Circuit 740; State-Variable Filters

17-7

738 740 Phase-Lead Circuit 743 744

17-10 IC Switched-Capacitor Filters

746

Switched-Capacitor Resistor Simulation 746; 17-11 Filter Testing and Troubleshooting Chapter 18 18-1

18-2

Transistor Series Regulator Basic Circuit 758; Regulator with Error Amplifier 759; Regulator Performance 760; Regulator Design 762

7357 758

Series

Improving Regulator Performance

Error Amplifier Gain 764;

18-4

751

Linear and Switching Voltage Regulators

764

Output Voltage Adjustment 764;

Output-Current Circuit 766; 18-3

IC Filter Circuits 748

Preregulation 767;

High-

Constant-Current

Source 769; Differential Amplifier 770 Current Limiting Short-Circuit Protection 772; Fold-Back Current Limiting 774 Op-amp Voltage Regulators Voltage-Follower Regulator 776;

772 776

Adjustable Output Regulator 777;

Current Limiting with an Op-amp Regulator 779 18-5

IC Linear Voltage Regulators

723 IC Regulator 780; 18-6

LM340

Regulators 785 Switching Regulator Basics

Switching Regulator Operation 786; Switching Regulators 787 18-7

780

LM317 and LM337 IC Regulators 784;

786

Comparison of Linear and

Step-Down, Step-Up, and Inverting Converters

Step-Down Converter 790; Step-Down Converter Equations 791; Step-Up Converter 793; Inverting Converter 795

790

xwiii

18-8

Contents

IC Controller for Switching Regulators

796

Function Block Diagram 796; Step-Down Converter Using an MC35063 797; Variable Off-Time Modulator 798; Catch Diode Selection 800; Diode Snubber 800; High-Power Converters 800

Chapter 19 19-1

Power Amplifiers

807

Transformer-Coupled Class A Amplifier

808

Class A Circuit 808;

DC and AC Loads 809; 811; Efficiency of a Class A Amplifier 812

19-2

19-3

Collector Voltage Swing

Transformer-Coupled Class B and Class AB Amplifiers Class B Amplifiers 815; Cross-Over Distortion 818; Class AB Amplifier 818; Efficiency of Class B and Class AB Amplifiers 819 Transformer-Coupled Amplifier Design

815

822

19-4 Capacitor-Coupled and Direct-Coupled Output Stages

825

Complementary Emitter Follower 825; Capacitor-Coupled Class AB Output Stage 826; Class AB Capacitor-Coupled Amplifier Design 827; Direct-Coupled Class AB Output Stage 832 19-5 Modifications to Improve Power Amplifier Performance Darlington-Connected Output Transistors 833 Quasi-Complementary Output Stage 835; Output Current Limiting 836; Vgz Multiplier 837; Power Supply Decoupling 839; Increased Voltage Gain and Negative Feedback 840; Load Compensation 840 19-6 BJT Power Amplifier with Differential Input Stage Amplifier Circuit 841; Amplifier Design 842 19-7 Complementary MOSFET Common-Source Power Amplifier Advantages of MOSFETs 846; Power Amplifier with MOSFET Output Stage 847; MOSFET Power Amplifier Design 848 19-8

BJT Power Amplifier with Op-Amp Driver

Circuit Operation 851; 19-9

250 mW

Bridge-Tied Load Amplifier 873;

846

Design

Procedure 855 MOSFET Power Amplifier with OP-Amp Driver Stage

IC Power Amplifier Driver 869;

841

851

Use of Bootstrapping Capacitors 852;

Basic Circuit Operation 858; Bias Control 861; 863; Complete Amplifier Circuit 866 19-10 Integrated Circuit Power Amplifiers

833

858

Output Voltage Swing 869

IC Power Amplifier 872;

7 W IC Power Amplifier 875;

68 W IC Power Amplifier 876 19-11 Class C Amplifier Class C Circuit and Waveforms 877;

877 Efficiency 879;

Bandwidth 881;

Component Selection 882 Chapter 20 20-1

893

= Thyristors

Silicon-Controlled Rectifier (SCR) SCR Operation 894; Specification 899

SCR Characteristics and Parameters 896;

894 SCR

Contents

20-2

SCR Control Circuits Pulse Control 900; 90° Phase Control 903;

900 180° Phase Control 907

More SCR Applications SCR Circuit Stability 908; Zero-Point Triggering 909; Crowbar Circuit 910; Heater Control Circuit 911 20-4 TRIAC and DIAC TRIAC Operation and Characteristics 912; TRIAC Triggering 914; The DIAC 915 20-5 TRIAC Control Circuits

20-3

TRIAC Phase Control Circuit 916;

917;

xix

908

912

916

TRIAC Zero-Point Switching Circuit

The IC Zero Voltage Switch 919

20-6

SUS, SBS, GTO, and SIDAC The SUS 920; TheSBS921; The GTO 925 The SIDAC 925

920

20-7

Unijunction Transistor (UJT)

927

UJT Operation 927; UJT Characteristics 928; UJT Packages 930; UJT Parameters 930; UJT Relaxation Oscillator 932; UJT Control of an SCR 934 20-8 Programmable Unijunction Transistor (PUT) PUT Operation 935; PUT Characteristics 935; PUT Parameters 936; PUT Applications 937

Chapter 21 21-1

Optoelectronic Devices

945

Light Units

946

21-2 Light-Emitting Diodes (LED)

21-3

21-4

935

948

LED Operation and Construction 948; Characteristics and Parameters 949; LED Circuits 950 Seven-Segment Displays LED Seven-Segment Display 952; Liquid Crystal Cells 953; LCD Seven-Segment Displays 954 Photoconductive Cells Cell Construction 955;

952

955

Characteristics and Parameters 956;

Applications 957 21-5

960

Photodiodes and Solar Cells

Photodiode Operation 960;

Characteristics 961;

Photodiode Applications 963;

21-6

Construction 963; Phototransistors Phototransistor (BJT) 967; Applications 969;

Specification 962; Solar Cells 964 967

Characteristics and Specification 968;

Photo-Darlingtons 970;

Photo-FET 970 971

21-7 Optocouplers

Operation and Construction 971;

973; 21-8

Specification 972;

Applications

Other Optocouplers 974

975

Photomultiplier Tube Operation 975; Divider 978

Characteristics 976;

Circuit Diagrams 976;

Voltage

xx.

Contents

21-9

Laser Diode

981

Operation 981; 983;

Chapter 22 22-1

Characteristics and. Parameters 982;

Modulation 984

Drive Circuits

:

Miscellaneous Devices

Voltage-Variable Capacitor Diodes Equivalent Circuit 995; VVC Operation 994;

993 994 Specification and

Characteristics 995; Applications 996 22-2 Thermistors Thermistor Operation 998; Characteristics and Specifications 999; Applications 1000 22-3

Tunnel Diodes

Tunnel Diode Operation 1002; Characteristics and Parameters 1003; Parallel Amplifier 1006 22-4 Schottky, PIN, and Current-Limiting Diodes The Schottky Diode 1009; PIN Diode 1011; Current-Limiting Diode 1012 Appendices Appendix A Appendix B Appendix C

Index

998

1002

1009

1018 Device Data Sheets = Standard-Value Components Answers to Odd-Numbered Problems

1018 1050 1053

‘1060

CHAPTER 1 = asic Semiconductor and pn-Junction Theory Objectives You will be able to:

diagram to show its compo-

Explain how n-type and p-type semiconductor materials are cre-

nents.

ated, and discuss the differences

Explain energy levels and energy bands relating to electrons,

between the two types. Sketch a pn-junction, and explain the origin of the junction

1 Describe an atom, and sketch a

and define valence band and

depletion region.

conduction band.

Draw diagrams to show the effects of forward biasing and

Describe how electric current

flow occurs by electron motion and by hole transfer. Explain conventional current direction and direction of electron flow. Sketch a diagram to show the

relationship between covalently bonded atoms. Discuss the differences between conductors, insulators, and semiconductors.

reverse biasing a pn-junction. 10

Sketch the current/voltage characteristics for forward-bi-

ased and reverse-biased pnjunctions. 11 Discuss temperature effects on conductors, insulators, semiconductors, and

pn-junctions. IZ Calculate current and voltage

levels at a pn-junction.

INTRODUCTION An electronic device controls the movement of electrons. The study of electronic devices requires a basic understanding of the relationship between electrons and the other components of an atom. The movement of electrons within

a solid and the bonding forces between atoms can then be investigated. This leads to a knowledge of the differences between conductors, insulators, and

semiconductors, and to an understanding of p-type and n-type semiconductor material.

2

Electronic Devices and Circuits

Junctions of p-type and n-type material (pn-junctions) are basic to all but a very few semiconductor devices. Forces act upon electrons that are adjacent to a pn-junction, and these forces are altered by the presence of an external

bias voltage.

1-1 ATOMIC THEORY The Atom The atom can be thought of as consisting of a central nucleus surrounded by orbiting electrons (see Fig. 1-1). It may be compared to a planet with orbiting

satellites. Just as satellites are held in orbit by the attractive force of gravity due to the mass of the planet, so each electron is held in orbit by an electrostatic force of attraction between it and the nucleus.

os Electron

f

Nucleus (positively charged)

7

(negatively

e

charged)

Nf

Figure 1-1 The atom consists of a central nucleus

surrounded by orbiting Ne

electrons. The electrons have a negative charge,

&

and the nucleus contains protons that are positively charged.

Eachelectronhasa negative electrical charge of 1.602 X 107~!? Coulombs (C), and some particles within the nucleus have a positive charge of the same magnitude. Because opposite charges attract, a force of attraction exists between the oppositely charged electron and nucleus. Compared to the mass of the nucleus, electrons are relatively tiny particles of almost negligible mass. In fact, they can be considered to be little particles of negative electricity having no mass at all.

The nucleus of an atom (Fig. 1-2) is largely a clus-

Protons

ter of two types of particles, protons and neutrons. Protons have a positive electrical charge, equal in magni-

O° es

tude (but opposite in polarity) to the negative charge :

on an electron. A neutron has no charge at all. Protons and neutrons each have masses about 1800 times the mass of an electron. For a given atom, the number of

Neutrons

Figure 1-2 The nucleus chanson te lagiand cluster of protons neutrons.

protons in the nucleus normally equals the number

of orbiting electrons. Because ’

the

equal in number

protons and

and

equal

orbital

and

electrons

opposite

are

in charge,

Chapter 1

Basic Semiconductor and pn-Junction Theory

3

they neutralize each other electrically. For this reason, all atoms are normally

electrically neutral. If an atom loses an electron, it has lost some negative charge. Consequently, it becomes positively charged and is referred to as a positive ion (see Fig. 1-3a). Similarly, if an atom gains an additional electron, it

becomes negatively charged and is termed a negative ion (Fig. 1-3b). The differences between atoms consist largely of dissimilar numbers and arrangements of the three basic types of particle. However, all electrons are Additional electron Hole

"
> Na, n >> p

From Eq. 1-6,

n= Np-Na = 3X 104-0.5 x 104 = 2.5 x 10"

and, from Eq. 1-3,

p=nz/n= (1.5 X 10!%/(2.5 x 10) = 0.9 X 10° holes /cm?

Section 1-4 Review 1-4.1 Draw a sketch

to illustrate donor doping.

1-4.2 Draw a sketch to illustrate acceptor doping. 1-4.3 Define n-type material, p-type material, minority charge carriers, major-

_.. “>

ity charge carriers, positive temperature coefficient, negative temperature coefficient, and dark resistance.

‘ice2 Problems , Determine the number of free alkene and holes in a sample of silicon

h is doped. with aX in donor:mitered em? and 3.3 x 10" accepatoms. / cm?

Bite

‘

j

at Problem 1-4.1 fora germanium sample if the electron density in

intrinsic germanium is.2.5 x 10. 1-5 SEMICONDUCTOR CONDUCTIVITY Drift Current In free space, an electric field will accelerate electrons in a straight line from

the negative terminal to the positive terminal of the applied voltage. In a conductor or semiconductor at 25°C, a free electron under the influence of an

electric field will move toward the positive terminal of the applied voltage, but will continually collide with atoms along the way. The situation is illustrated in Fig. 1-17. Each time the electron strikes an atom, it rebounds in —

a random direction. The presence of the electric field does not stop the collisions and random motion, but it does cause the electrons to drift in the direction of the positive terminal. Consequently, current produced in this way is termed as drift current, and it is the usual kind of current flow that occurs in conductors and semiconductors.

Chapter ‘1

Basic Semiconductor and pn-Junction Theory

17

Electron path when no electric field is present |

Electron path when the electric field is present

o

+

———

Electron drift due to electric field

d 7

_

Conductor or

We

semiconductor

Figure

1-17

e

toms

Drift current is the type of current flow that occurs in conductors and

semiconductors when a voltage is applied. Electrons cannot travel in a straight line, but instead drift along, bouncing from one atom to another.

Diffusion Current Figure 1-18 illustrates another type of current that occurs in semiconductors. Suppose a concentration of one type of charge carriers appears at one end of a piece of semiconductor material, as the result of a charge carrier injection

from an external source. Because the charge carriers are either all electrons or all holes they have the same polarity, and thus there is a force of repulsion between them. This produces a tendency for the electrons to move gradually, or diffuse, away from the locality of high concentration toward one of low concentration until they are eventually distributed throughout the material.

The movement of charge carriers constitutes an electric current, and so this type of current is known as a diffusion current. Diffusion current

Charge

he

i carrier

—WH-————_»

aes

6.

o-

e

e

concentration ————>-

e*

@

eon eo eG @

e-

»6-

ee , . @Ore

e'= >

gi Bi aoa,

ee

Figure

1-18

Diffusion

current

-

occurs

o-

when

eeo.

-

oe ;

charge

carriers

diffuse

from

a point

of

concentration to spread uniformly throughout the material.

Charge Carrier Velocity Recall from Section 1-2 that electrons have greater mobility than holes. The mobility constants (see Table 1-1) determine the electron and hole (drift

18

Electronic Devices and Circuits

current) velocities under the influence of an electric field. For electron velocity (0,) and hole velocity (Up)

and

: Up = Up 6

(1-8)

where fn and pp are the electron and hole mobility constants, and © is the electric field strength. The minus sign in Eq. 1-7 indicates that the electrons move from negative to positive, opposite to conventional current direction.

Example 1-2 Calculate the drift current velocity for electrons and for holes in a 1 mm length of silicon at 27°C when the terminal voltage is 10 V. Solution

Eq. 1-7:

Un = —UnE/1 =-1500 cm? X 10 V/1 mm = -1500 m/s

Eq. 1-8:

Up= MpE/1 = 500 cm? X 10 V/1 mm = 500 m/s

Conductivity Recall from basic electrical studies that the resistance of a conductor is given by the equation R= pl/a

(1-9)

where p is the resistivity of the material (in 0.m), ! is the length, and a is the cross-sectional area. This can be rewritten as

R= 1/(oa)

(1-10)

where ois the material conductivity (the reciprocal of resistivity) (Q.m)7!.

For doped semiconductor having n free electrons and p holes, the conducti-

vity is given by

o= q(npn + Pp) where q is the electronic charge (1.602 x 10°" C).

(1-11)

Chapter 1

Basic Semiconductor and pn-Junction Theory

Example 1-3 A cylindrically shaped section of n-type silicon has a 1 mm 0.1 mm?

cross-sectional

area. Calculate

its conductivity

and

19

length and resistance

(a) when it is purely intrinsic material, and (b) when it has a free electron

density of n = 8 X 10'3/cm’. Solution

1=1mm=0.1

cmanda=0.1 mm? = 107° cm?

(a) From Table 1-1, the electron and hole density for intrinsic silicon is n; = 1.5 X 10!°/cm?3 and the mobility constants are

Un = 1500 cm2/V.s

Eq. 1-11:

and pp =500cm’/Vs

= G(NUn + Pep) = (1.6 X 107)[(1.5 X 10" x 1500) + (1.5 x 10! x 500)] = 48 X 10-°(Q.cm)7!

From Eg. 1-10, R =1/(o a) = 0.1/(4.8 X 107° (Q.cm)~! x 107% cm’) = 20.8 MQ. (b) For doped material

Eq. 1-3:

p=nz?/n= (1.5 X 10)?/(8 x 10%) = 2.8 x 10°

Eq. 1-11:

o = q(Nn + Pp)

= (1.6 X 107!)[(8 x 10% x 1500) + (2.8 X 10° x 500)]

= 0.019 (Q.cm)7! From Eq. 1-10, R =1/(oa) = 0.1 cm/(0.019 Q/cm X 107 cm?) = 5.26 kD

20 Eledtronic Davices and’Gircuits

e Pr oblems

es

7

Iculate the free electron density i ina 1 mm cube of n-type silicon if its ssurcd resistance iis 35 Dei

1-6 THE pn-JUNCTION Junction of p-Type and n-Type Two blocks of semiconductor material are represented in Fig. 1-19: one block

is p-type material, and the other is n-type. The small circles in the p-type material represent holes, which are the major-

Electrons

Holes

ity charge carriers in p-type. The dots in the

n-type material represent the majority charge carrier free electrons within that material. Normally, the holes are uniformly distributed throughout the volume of the p-type semiconductor and the electrons are uniformly distribFigure 1-19 p-typeandn-type —_ uted in the n-type.

salable

lcama

Electrons cross from

haw-side to fill holes

In

Fig.

1-20,

p-type

and

re

‘

;

5

a pn-junction. Minority

ee

charge carriers

92085 0.

0

Oe Oo.

Or O° o 2

o

O

00

Layer of

negative

positive ions

ions

+

barrier

barrier voltage

voltage

Figure 1-20

ae

Junction

Junction =

h Majority Cc.

; Atapn-junction,

arge

carriers

The barrier Figure 1-21 voltage at a pn-junction

electrons cross from the

assists the flow of minority

on the p-side close to the

opposes the flow of majority

n-side to fill holes in a layer

junction.

semi-

conductor materials are shown side by side, representing

in the p-side

Fr

n-type

charge carriers and

charge carriers.

‘

Since

holes

and

Chapter 1

Basic Semiconductor and pn-Junction Theory

21

electrons are close together at the junction, some free electrons from the n-

side are attracted across the junction to fill adjacent holes on the p-side. They are said to diffuse across the junction from a region of high carrier concentration to one of low concentration. The free electrons crossing the

junction create negative ions on the p-side by giving some atoms one more electron than their total number of protons. The electrons also leave positive

ions (atoms with one fewer electron than the number of protons) behind them on the n-side.

Barrier Voltage The n-type and p-type materials are both electrically neutral before the charge carriers diffuse across the junction. When negative ions are created on the p-side, the portion of the p-side close to the junction acquires a negative voltage (Fig. 1-20). Similarly, the positive ions created on the n-side give the n-side a positive voltage close to the junction. The negative voltage on the p-side tends to repel additional electrons crossing from the n-side. Also (thinking of the holes as positive particles), the positive voltage on the n-side tends to repel any movement of holes from the p-side. So, the initial diffusion of charge carriers creates a barrier voltage at the junction, which is negative on the p-side and positive on the n-side. The transfer of charge carriers and the

resultant creation of the barrier voltage occur when the pn-junctions are formed during the manufacturing process (see Chapter 7). The magnitude of the barrier voltage at a pn-junction can be calculated from a knowledge of the doping densities, electronic charge, and junction temperature. Typical barrier voltages at 25°C are 0.3 V for germanium junctions and 0.7 V for silicon. It has been explained that the barrier voltage at the junction opposes both

the flow of electrons from the n-side and the flow of holes from the p-side. Because electrons are the majority charge carriers in the n-type material, and

holes are the majority charge carriers in the p-type, it is seen that the barrier voltage opposes the flow of majority carriers across the pn-junction (see Fig. 1-21). Any free electrons generated by thermal energy on the p-side of the junction are attracted across the positive barrier to the n-side. Similarly, thermally generated holes on the n-side are attracted to the p-side through the negative barrier presented to them at the junction. Electrons on the p-side and holes on the n-side are minority charge carriers. Therefore, the barrier voltage assists the

flow of minority carriers across the junction (Fig. 1-21).

Depletion Region The movement of charge carriers across the junction leaves a layer on each side that is depleted of charge carriers. This is the depletion region shown in

Fig. 1-22a. ‘On the n-side, the depletion region consists of donor impurity

atoms ‘that, having. lost ‘the free electron associated with them, have become

22

Electronic Devices and Circuits

Depletion region wider

Depletion region

p-type

n-type

"00 6 0le Oi

puis

lio

29

°

0

‘

Diyas of A negative ions

n-type

00,0" .0..6

Sle

0.0

Os: 9 9

p-type

1.0 On)

0'e, D Je a

on lightly doped side

9,0

006

40" 0.

OF

Layer of positive

Layer of i negative

ions

ions

Equal number of ions on each side

(a) Equal doping densities

ee

\ ayer of positive ions

Equal number of ions on each side

(b) Unequal doping densities

Figure 1-22 Charge carrier diffusion across a pn-junction creates a region that is depleted of charge carriers and that penetrates deepest into the more lightly doped side.

positively charged. The depletion region on the p-side is made up of acceptor impurity atoms that have become negatively charged by losing the hole associated with them. (The hole has been filled by an electron.)

On each side of the junction, equal numbers of impurity atoms are involved in the depletion region. If the two blocks of semiconductor material have equal doping densities, the depletion layers on each side have equal - widths (Fig. 1-22a). If the p-side is more heavily doped than the n-side, as illustrated in Fig. 1-22b, the depletion region penetrates more deeply into the n-side in order to include an equal number of impurity atoms on each side of the junction. Conversely, when the n-side is more heavily doped, the depletion region penetrates deeper into the p-type material. Summary e

A region depleted of charge carriers spreads across both pn-junction, penetrating farther into the less doped side.

sides

of a

¢ The depletion region contains an equal number of ionized atoms on opposite sides of the junction. e A barrier voltage is created by the charge carrier depletion effect, positive on the n-side and negative on the p-side. e

The barrier voltage opposes majority charge carrier flow and assists the

flow of minority charge carriers across the junction.

Section 1-6 Review

1-6.1 Sketch a pn-junction showing the depletion region. Briefly explain how "2 the depletion region is created. 1-6.2 Explain the origin of the barrier voltage at a pn-junction. Discuss the _ effect of the barrier voltage on minority and majority charge carriers.

Chapter 1

1-7

Basic Semiconductor and pn-Junction Theory

23

BIASED JUNCTIONS

Reverse-Biased Junction When an external bias voltage is applied to a pn-junction, positive to the n-side and negative to the p-side, electrons from the n-side are attracted to the positive terminal, and holes from the p-side are attracted to the negative terminal. As shown in Fig. 1-23, holes on the p-side of the junction are attracted away from the junction and electrons are attracted away from the junction on the n-side. This causes the depletion region to be widened and the barrier voltage to be increased, as illustrated. With the barrier voltage increase, there is no possibility of a majority charge carrier current flow across the junction, and the junction is said to be reverse biased. Because there is only a very small reverse current, a reverse-biased pn-junction can be said to have a high resistance. Reverse bias

c_ _

a Depletion region is widened by the

— +

reverse bias

ptype

te

0.

0.0.0. 920 10 “0. 6 aO Oa ale 0°20

_

—| _

Ons:

° oO

077°

so

OB

oO

Oo

02

°. OCO°

00

5

~rO

Le

O

Unbiased junction

barri rrier voltag' ltage

as

4.M4+

junetion baxtiee ; voltage is increased by

"

Reverse biased

junction barrier — voltage \ ~

NX

|

reverse bias

Figure 1-23 A reverse bias applied i toa pn -j junction i (positive iti on the n-side, negative on the p-side) causes the depletion

region to widen and increases

the barrier voltage. Only a very small reverse current flows across the junction.

Although there is no possibility that a majority charge carrier current can

flow across a reverse-biased junction, minority carriers generated on each side can still cross the junction. Electrons in the p-side are attracted across the junction to the positive voltage on the n-side. Holes on the n-side may flow

across to the negative voltage on the p-side. This is shown by the junction reverse characteristic, or the graph of reverse current (Ip) versus reverse voltage (Vp) (Fig. 1-24). Since only a very small reverse-bias voltage is

necessary to direct all available minority carriers across the junction, further increases in bias voltage do not increase the current level. This current is referred to as a reverse saturation current.

24

Electronic Devices and Circuits

VR (Vv)

-5 -4

-3 -2

0

-1

0 1 =2

IR

—3 —4

Figure 1-24

~

tic for a reverse-biased pn-junction.

(yA)

'

Forward bias

;

A

0

Depletion region is

+

p-type

barrier voltage Forward-biased

junction barrier

”

narrowed by the forward bias

Unbiased junction

Current-versus-voltage characteris-

n-type

Junction ‘unction

mt

Forward biasing a Figure 1-25 pn-junction (positive on the p-side, negative on the n-side) narrows

bart Darrier ed

aoe aoe bias Tplge by forward

voltage

.

.

depletion region, the R reduces the barrier voltage, and 7

causes a relatively large current to flow

across the junction.

» The reverse saturation current is normally a very small quantity, ranging from nanoamps to microamps, depending on the junction area, temperature,

and semiconductor material.

Forward-Biased Junction Consider the effect of an external bias voltage applied with the polarity shown in Fig. 1-25: positive on the p-side and negative on the n-side. The

holes on the p-side, being positively charged particles, are repelled from the positive terminal and driven toward the junction. Similarly, the electrons on

the n-side are repelled from the negative terminal toward the junction. The

result is that the width of the depletion region and the barrier potential are

both reduced. When the applied bias voltage is progressively increased from zero, the barrier voltage gets smaller until it effectively disappears and charge carriers easily flow across the junction. Electrons from the n-side are now attracted across to the positive bias terminal on the p-side, and holes from the p-side

Chapter 1

Basic Semiconductor and pn-Junction Theory

25

flow across to the negative terminal on the n-side (thinking of holes as positively charged particles). A majority carrier current flows, and the junction is said to be forward biased.

The graph in Fig. 1-26 shows the forward current (Ip) plotted against forward voltage (Vf) for typical germanium and silicon pn-junctions. In each

case, the graph is known as the forward characteristic of the junction. It is seen that there is very little forward current until Vp exceeds the junction barrier voltage (0.3 V for germanium, 0.7 V for silicon). When Vx is increased from zero toward the knee of the characteristic, the barrier voltage is progressively overcome, allowing more majority charge carriers to flow across the junction. Above the knee of the characteristic, Ip increases almost linearly with increase in Vp. The level of current that can be made to flow across a forward-

biased pn-junction largely depends on the area of the junction. (mA) 5 4 Ge

heh

Silicon

3

Ip

Figure 1-26 2 | y

1 0

0

O01

02

7

ance 03

forward characteristics. Germanium junctions are forward biased

|

4 a

04

| 05

pn-junction

at approximately 0.3 V. A

06

07

silicon junction requires

08

Ve

approximately 0.7 V for forward bias.

Junction Temperature Effects As already discussed,

the reverse

consists

charge

of

minority

saturation

carriers.

When

current

the

semiconductor material is raised, increasing numbers

(I,) at a pn-junction

temperature

of

the

of electrons break

away from their atoms. This generates additional minority charge carriers, causing I, to increase as the junction temperature rises. When I, is known for a given temperature (Tj), it can be calculated for another temperature level (T2) from the following equation: MS,

Seo

(1-12)

Example 1-4 demonstrates that I, approximately doubles for each 10°C rise in temperature (Fig. 1-27a).

Example 1-4 Determine the levels of reverse saturation current at temperatures of 35°C and 45°C for a junction which has I, = 30 nA at 25°C.

26

Electronic Devices and Circuits.

Solution Eq. 1-12:

ora) © Tory (272 ~ 7/10)

ol”. Aras":

Tease)

© 30 nA X (25

_

25)/10)

~ 60 nA oc. At 45°C:

Iyasic) © ' 30 nA X (245 ~= 25)/10) ~120nA

“5B -4

(Vv) >

Vr =38 =2

=1

mA

9

es

0 ont

IR at 25°C

-2

Tp at 35°C

Ip=3mA

Ip

| ais

p at 25°C

-4

Tp at 45°C

'

—5

(vA)

(a) Reverse current approximately doubles with each 10°C

0

01 02 03 04 05 06 0.7 08 V.

(V)

F

(b) Forward voltage-drop changes by approximately —2 mV/°C

temperature increase Figure 1-27

Junction reverse current and forward voltage drop are affected by tempera-

ture change.

The junction forward voltage drop (Vr) is also affected by temperature. The horizontal line (at 3 mA) on Fig. 1-27b shows that, if Iz is held constant

while the junction temperature is changing, the forward voltage decreases with rising junction temperature. This means that Vz has a negative temperature coefficient. It is found that the temperature coefficient for the forward voltage of a pn-junction is approximately —1.8 mV/°C for a silicon junction and —2.02 mV/°C for germanium. A figure of —-2 mV/°C is normally used as an approximation.

Summary ¢

A pn-junction is reverse-biased when a voltage is applied positive to the

n-side and negative to the p-side.

Chapter 1

Basic Semiconductor and pn-Junction Theory

27

e Areverse-biased junction has a wide depletion region. e

Avery small minority charge carrier current (Ip) flows across a reverse-bi-

e

ased junction. The junction reverse characteristic is the graph of I, versus Vp.

e

The reverse saturation current (Ij) tends to be constant regardless of the

reverse bias voltage (Va). e The reverse current approximately doubles with every 10°C rise in junction temperature.

¢ A pn-junction is forward-biased when a voltage is applied positive to the p-side and negative to the n-side. e A forward-biased junction has a narrow depletion region. e A majority charge carrier current (Ip) flows across a forward-biased junction. e

The junction forward characteristic is the graph of Ip versus Vr.

e

The forward current (Ip) depends on the level of forward bias voltage (Vp).

¢ Typical junction forward voltage drops are 0.3 V for germanium and 0.7 V for silicon. e The junction forward voltage drop changes by approximately —2 mV/°C as the junction temperature increases.

Section 1-7 Review 1-7.1 Sketch typical voltage/current characteristics for a forward-biased silicon pn-junction: Briefly explain. 1-7.2 Sketch typical voltage/current characteristics for a reverse-biased

pn-junction. Briefly explain. 1-7.3 Discuss the effects of temperature change on forward- and reversebiased pn-junctions.

Practice Problem 1-7.1

The reverse current for a semiconductor diode is measured as 25 nA at

25°C, and as 75 nA at a temperature T2. Calculate T».

1-8

JUNCTION CURRENTS AND VOLTAGES

Shockley Equation The equation relating pn-junction current and voltage levels is called the

Shockley equation. Ip =1, [evo /"Vr —1]

(1-13)

28

Electronic Devices and Circuits

where Ip is the junction current, I, is the reverse saturation current (see Sec-

tion 1-7), Vp is the junction voltage, and n is a constant which is usually taken

as 1 for germanium and 2 for silicon. Vr depends upon temperature “A

By

{

(1.4

(4-14)

where k is Boltzman's constant (1.38 X 10~*), T is absolute temperature, and

q is the electronic charge (1.6 x 10719). When T = 300 K (or 27°C), Eq. 1-14 gives Vr = 26mV

Junction Current The current level at a forward-biased junction can be calculated from Eq, 1-13 for a given applied voltage and temperature. A table of corresponding current and voltage levels could be determined for plotting the junction

forward characteristic. However, the characteristics will not be completely accurate because the Shockley equation does not allow for the resistance of the semiconductor material, and for the surface leakage current that adds to the ‘reverse saturation current. At a reverse-biased junction, the current always equals the reverse saturation current.

Example 1-5 A silicon pn-junction has a reverse saturation current of I, = 30 nA ata temperature of 300 K. Calculate the junction current when the applied voltage is (a) 0.7 V forward bias, (b) 10 V reverse bias. Solution

(a) Forward bias Vp/(n Vz) = 0.7 V/(2 X 26 mV) = 13.46 Ip = 4, [e"D/"Vr ~1]=30 nA

Eq. 4-13:

=21mA

(b) Reverse bias

Vp/(nV>z) = -10 V/(2 X 26 mV) =~192

= —30nA

[e346 - 1]

Chapter 1

Basic Semiconductor.and pn-Junction Theory

29

Junction Voltage Equation 1-13 can be rewritten to give an equation for the junction voltage for a given forward current. Here again it should be remembered that the equation is not completely accurate.

Vp=(@ Va) In Ub/Ie)

(1-15)

Example 1-6 For the silicon pn-junction in Ex. 1-5, calculate the junction forward-bias voltage required to produce a current of (a) 0.1 mA, (b) 10 mA. Solution (a) Ip=0.1mA Eg. 1-15:

Vp = (n V5) In (Ip/Io) = 2X 26mV X In (0.1 mA/30 nA) = 422 mV

(b) b=10mA Eq. 1-15:

Vp = (n Vz) In (Ip /Io)

= 2X26 mV X In(10 mA/30 nA) = 661 mV

‘Practice Problems -4-8.1 A silicon pn-junction has a reverse saturation current of 20 nA at 25°C - and 80 nAcat 45°C. Calculate the current at both temperatures when the

forward bias voltage is'0.69.V. - 4-8.2 Calculate the reverse saturation current for a silicon pn-junction which sc ‘passes a current of 15 mA at 27°C when the forward bias voltage is

680 mV. Review Questions . ‘Section 1-1 1-1

‘Describe'the atom, and draw a two-dimensional diagram to illustrate your de-

scription. Compare the atom to a planet with orbiting satellites. 1-2 1-3

Define nucleus, electron, electronic charge, proton, neutron, shell, positive ion, and negative ion. Sketch two-dimensional diagrams of silicon and germanium atoms. Describe

the valence shell of each atom.

30

Electronic Devices and Circuits

1-4

Explain atomic number

1-5

atomic weight for silicon. Explain what is meant by energy levels and energy bands. Sketch an energy

and atomic weight. State the atomic number

and

band diagram, and define conduction band, valence band, and forbidden gap.

Section 1-2 1-6

Draw a sketch to show the process of current flow by electron motion. Briefly

1-7

explain. Draw sketches to show the process of current flow by hole transfer. Which have greater mobility, electrons or holes? Explain why.

1-8

Define conventional current direction and direction of electron flow. State why

each is important.

Section 1-3 1-9

Name the three kinds of bonds that hold atoms together in a solid. What kind

of

bonding

might

be

found

in

(a) conductors,

(b)

insulators,

and

(c) semiconductors?

1-10

Draw sketches to illustrate metallic bonding and ionic bonding. Explain what

1-11

happens in each case. Draw a sketch to illustrate covalent bonding. Explain the bonding process.

1-12

Draw energy band diagrams for conductors, insulators, and semiconductors. Explain the reasons for the differences between the diagrams.

Section 1-4 1-13 Define acceptor doping, and draw a sketch to illustrate the process. Explain. 1-14 Define donor doping, and draw a sketch to illustrate the process. Explain. 1-15 State the names given to acceptor-doped material and donor-doped material. 1-16

Explain. What is meant by majority charge carriers and

minority

charge

carriers?

1-18

Which are majority carriers and why in (a) donor-doped material, and (b) acceptor-doped material? Explain what happens to resistance with increasing temperature in the case of (a) a conductor, (b) a semiconductor, and (c) a heavily doped semiconductor. What do you think would happen to the resistance of an insulator with increasing temperature? Why? Explain hole-electron pair generation and recombination.

1-19 1-20

Discuss the effects that light can produce on semiconductor materials. Define n-type material, p-type material, majority charge carriers, minority

1-17

charge

positive temperatiire resistance. dark and coefficient,

1-21

carriers,

coefficient,

negative

temperature

Discuss the relationship between the density of holes and electrons in doped and undoped semiconductor material.

Section 1-5 1-22

Draw a diagram to illustrate drift current in a semiconductor material. Briefly

explain.

Chapter 1

Basic Semiconductor and pn-Junction Theory

31

1-23

Draw a diagram to illustrate diffusion current in a semiconductor material.

1-24

Briefly explain. Define resistivity and conductivity.

Section 1-6 1-25

Using illustrations, explain how the depletion region and barrier voltage are produced ata pn-junction. List the characteristics of the depletion region.

1-26

Draw a sketch to show the depletion region and barrier voltage pn-junction with unequal doping of each side. Briefly explain.

at a

Section 1-7 1-27 Abias is applied toa pn-junction, positive to the p-side, negative to the n-side.

Show, by a series of sketches, the effect of this bias on depletion region width, barrier voltage, minority carriers, and majority carriers. Briefly explain the

effect in each case. 1-28 1-29

Repeat Question 1-27 for a bias applied negative to the p-side and positive to the n-side. Sketch the voltage/current characteristics for a pn-junction (a) with forward bias

and

(b) with

reverse bias. Show

how

temperature

change

affects

th:

characteristics.

1-30 1-31

State typical values of barrier voltage for silicon and germanium junctions. Discuss the resistances of forward-biased and reverse-biased pn-junctions. State typical reverse saturation current levels for pn-junctions. Explain the origin of reverse saturation current.

Section 1-8 1-32 1-33

Write the Shockley equation for junction current in terms of junction voltage and other quantities. Define each quantity in the equation. From the Shockley equation for junction current (for Question 1-32), derive the junction voltage equation.

Problems Section 1-4 1-1

Determine

1-2. 1-3.

0.6 X 10!5 donor atoms/cm? and 10'° acceptor atoms/cm‘. Repeat Problem 1-1 for germanium. A sample of silicon is doped with 3 X 10'° acceptor atoms/cm® and 4 X 10'5 donor atoms/cm’. Determine the density of free electrons and holes

1-4

the

density

of

free

electrons

in

silicon

when

doped

with

in the sample. Asilicon sample is to have a free electron density of 5 X 10'° per cm? and a much smaller hole density. Calculate the required doping density for electrons if the material is already doped with 10'° acceptor atoms per cm’.

92

Electronic Devices and Circuits

Section 1-5 1-5

The drift current velocity in a germanium sample is estimated as 12.9 cm/s, and the terminal voltage is 14.5 V, Calculate the length of the sample.

1-6

Determine the conductivity and resistance of a 3 mm cube of germanium, (a) when it is purely intrinsic, and (b) when it has a hole density of p = 5 x 10'4 / cm’,

1-7

A-sample of n-type silicon is 1.5 mm long with a cross-sectional area of 0.02 mm?. Determine the free electron density if its resistance is measured as 28 k{),

1-8

Calculate the resistance of a5 mm cube of silicon described in Problem 1-1.

1-9

Determine the resistivity of the silicon described in Problem 1-3.

Section 1-7 1-10

The reverse saturation current (I,) for a pn-junction is 25 nA at 25°C. Calculate I, at temperatures of 30°C, 33°C, and 37°C,

1-11

The level of I, for a pn-junction is measured as 60 nA at 30°C. Calculate I, at

1-12

ao hs A pn-junction has I, = 35 nA at 25°C. Determine the junction temperature that will produce I, = 55 nA.

Section 1-8 1-13

1-14 1-15 1-16

A forward-biased silicon junction has its current held constant at 33 mA. Calculate the junction voltage at 25°C and 50°C if the reverse saturation current is 50 nA at 25°C. Calculate the forward current for a silicon pn-junction which has 0.65 V forward bias. The reverse saturation current is 100 nA at 25°C. Determine the voltage change required to double the forward current for the junction in Problem 1-14. Repeat Problem 1-14 for a silicon junction with 0.29 V forward bias.

Practice Problem Answers 1-41

0.7 X

10!4,3.2 x 10°

1-4.2 15.1

3.93 X 105, 1.59 x 10% 12x10"

1-7.1

40.85°C

1-8.1

13.2 mA, 23.7 mA

CHAPTER 2 Semiconductor

Diodes

Objectives You will be able to: 1 Sketch a diode circuit symbol, identify the terminals, and discuss diode circuit behavior. 2 Explain diode forward and reverse characteristics. 3 List important diode parameters and determine parameter values from the characteristics. 4 Sketch approximate diode characteristics and dc equivalent circuits, and apply them to circuit analysis.

7 Sketch diode ac equivalent circuits and calculate junction capacitance and switching times. 8 Determine diode parameter values from device data sheets. 9 Test diodes, and plot the forward and reverse characteristics. 10 Sketch a Zener diode circuit symbol, identify the terminals, and explain the characteristics. 11 Determine Zener diode parameter values from device

5 Draw dc load lines on diode

characteristics and from data

characteristics to precisely analyze diode circuits. 6 Determine maximum diode

sheets. 12 Analyze basic Zener diode circuits.

power dissipations and forward voltages at various temperatures.

INTRODUCTION The term diode refers to a two-electrode, or two-terminal, device. A semiconductor diode is simply a pn-junction with a connecting lead on each

side. A diode is a one-way device, offering a low resistance when forward-biased, and behaving almost as an open switch when reverse-biased. An approximately constant voltage drop occurs across a forward-biased diode, and this

simplifies diode circuit analysis. Diode forward and reverse characteristics are graphs of corresponding current and voltage levels. For precise circuit

analysis, dc load lines are drawn on the diode forward characteristic. Some diodes are low-current devices for use in switching circuits. Highcurrent diodes are most often used as rectifiers for ac to dc conversion. Zener

34

Electronic Devices and Circuits

diodes are operated in reverse breakdown because they have a very stable

breakdown voltage.

2-1 pn-JUNCTION DIODE As explained in Sections 1-5 and 1-6, a pn-junction permits substantial current flow when forward biased, and blocks current when reverse-biased, Thus, it can be used as a switch: on when forward-biased and off when biased in reverse. A pn-junction provided with copper wire connecting leads

becomes an electronic device known as a diode (see Fig. 2-1).

The circuit symbol (or graphic symbol) for a

diode is an arrowhead and bar (Fig. 2-2). The

ptype

arrowhead indicates the conventional direction of current flow when the diode is forward-biased (from the positive terminal through the device to the negative terminal). The p-side of the diode is always the positive

!

n-type

§ —— \

_—_—_ Ve

Conductor Figure 2-1 A semiconductor

terminal for forward bias and is termed the ; ‘ anode. The n-side, called the cathode, is the

a is a pn-junction with the junction for connecting

negative terminal when the device is forward-

the device to a circuit.

conductors on each side of

biased.

A pn-junction diode can be destroyed if a high level of forward current overheats the device. It can also be destroyed if a large reverse voltage causes

the junction to break down. The maximum forward current and reverse voltage for diodes are specified on the manufacturer’s data sheets (see Section 2-

7). In general, physically large diodes pass the largest currents and survive the largest reverse voltages. Small diodes are limited to low current levels and low reverse voltages. Figure 2-3 shows

the appearance

of low-, medium-,

and

high-current

diodes. Since the body of the low-current device in Fig. 2-3a may be only 0.3 cm long, the cathode is usually identified by a coloured band. This type of Positive terminal

for forward bias

Ip ee

N

Anode

(p-type)

Negative terminal

for forward bias

|

fe

Cathode

(n-type) Arrowhead indicates conventional current direction

Figure 2-2

Diode circuit symbol. Current flows in the arrowhead direction when the diode

is forward-biased: positive (+) on the anode and negative (—) on the cathode.

Chapter 2

Cathode | lant (a) Low-current diode

35

diode is usually capable of passing a maximum forward current of approximately 100 mA. It can also survive about 75 V reverse bias without breaking

Cathode

Semiconductor Diodes

down,

and

its reverse

cur-

rent is usually less than 1 wA at 25°C.

The medium-current diode shown in Fig. 23b can usually pass a forward current of about (b) Medium-current diode

Cathode J

(c) High-current diode

Figure 2-3 The size and appecsamsotetinda depen upon the level of forward current that the device is

designed to pass.

400 mA and survive over 200 V reverse bias.

The anode and cathode terminals may be indicated by a diode symbol on the side of the device.

Low-current and medium-current diodes are usually mounted by soldering the connecting leads to terminals. Power dissipated in the device is then carried away by air convection aad by heat conduction along the connecting5 leads.

High-current

diodes,

or power

diodes

(see

Fig. 2-3c), generate a lot of heat. So air convec-

tion would be completely inadequate. Such devices are designed to be connected mechanically to a metal heat sink. Power diodes can pass forward currents of many amperes and can survive several hundred volts of reverse bias.

2-2 CHARACTERISTICS AND PARAMETERS Forward and Reverse Characteristics The semiconductor diode is essentially a pn-junction, and its characteristics

are those discussed in Chapter 1. Figures 2-4 and 2-5 show typical forward

and reverse characteristics for low-current silicon and germanium diodes. From the silicon diode characteristics in Fig. 2-4, it is seen that the forward current (Ip) remains very low (less than 100 A) until the diode forward-bias

voltage (Vp) exceeds approximately 0.7 V. At Vr levels greater than 0.7 VTr increases almost linearly. Because the diode reverse current (Ip) is very much smaller than its for-

ward current, the reverse characteristics are plotted with expanded current scales. For a silicon diode, Ip is normally less than 100 nA, and it is almost

completely independent of the reverse-bias voltage. As already explained in Chapter 1, Ip is largely a minority charge carrier reverse saturation current. A small increase in Ip can occur with increasing reverse-bias voltage, as a result

of minority charge carriers leaking along the junction surface. For a diode

with the characteristics in Fig. 2-4, the reverse current is usually less than

36

Electnonic'Devices and Cirauits

(mA)

(nA) Figure 2-4 Typical forward and reverse characteristics for a silicon diode. There is a sub‘stantial forward current (I-) when the forward voltage (Vr) exceeds approximately 0.7 V.

LOW

|

Qn.

Reverse breakdown!

I .

voltage

~ +.

saad xe

!

iV)

F

—50

j

AD

VR

he

'

AS

+

(V) 02

03

O04

2

y

0.1

;

F

1A £0

1

4: LW

(A) ‘Figure 2-5

‘Typical forward and reverse characteristics

fora germanium diode. Substantial forward current (Ir)

“flows when ‘the ‘forward voltage (V-) exceeds approxi‘mately: 0.3 V.

11/10.000 of ‘the ‘lowest normal forward current level. Therefore, Ip is quite negligible‘when compared to Jp, and a reverse-biased diode may be treated almost.as:an open switch. This is investigated further in Ex. '2-1.

Chapter2

Semiconductor Diodes

37

Example 2-1 Calculate the forward and reverse resistances offered by a silicon diode with

the characteristics in Fig. 2.4 at Ip = 100 mA and at Vp = 50 V. Solution

At Ip = 100 mA, Vp ¥ 0.75 V

0.75V Rs Ve = —P= 7 viens , Pee =750, At Vg = 50V, Ip*100nA Ve = 50V Rp= R= 7 = Goona (See = 500 MO

Fig. 2-6 Bee)

Fig.Fig: 2-6b 2-60)

When the diode reverse voltage (Vg) is sufficiently increased, the device goes into reverse breakdown. For the characteristics shown in Fig. 2-4, this “ : occurs where Vp = 75 V. Reverse breakdown can S Rp= iz

ly

Ky ~

(a) Forward resistance I

x’ }y n|

_f

_ Vp

down is usefully applied in Zener diodes, which are introduced in Section 2-9. The characteristics of a germanium diode

R''Tgp

are similar to those of a silicon diode but with

Se ®

(b) Reverse resistance

Clos

destroy a diode unless the current is limited by a suitable series-connected resistor. Reverse break-

lone

reverse resistance.

a

some important differences (see Fig. 2-5). The forward voltage drop of a germanium diode is typically 0.3 V, compared to 0.7 V for silicon. For a germanium device, the reverse saturation current

at 25°C may be about 1 wA, which is much larger than the reverse current for a silicon diode. Finally, the reverse breakdown voltage for germanium devices is likely to be

substantially lower than that for silicon devices. The lower forward voltage drop for germanium diodes can be a distinct

advantage. However, the lower reverse current and higher reverse breakdown voltage of silicon diodes make them preferable to germanium devices for most applications.

Diode Parameters The diode parameters of greatest interest are

Ve

forward voltage drop

38

Electronic Devices and Circuits

te

reverse saturation current

VBR

ff

reverse breakdown voltage

ta

Tpmax)

dynamic resistance Maximum forward current

The values of these parameters are normally listed on the diode data sheet provided by device manufacturers (see Section 2-7). Some of the parameters can also be deter-

mined directly from the diodé characteristics.

For the silicon diode characteristics in Fig . 2-4,

|

Ve ~ 0.7 V, IR = 100 nA, and Vp = 75 r V.

The forward resistance calculated in Ex. 2-1

=—= Figure 2-7

Determination of

is a static quantity. It is the constant resistance

Se

(or dc resistance) of the diode at a particular constant forward current. The dynamic resistance of the diode is the resistance offered to

shesanesistles

uEaaneaaee |

changing levels of forward voltage. The dynamic resistance, also known as the

incremental resistance or ac resistance, is the reciprocal of the slope of the forward characteristics beyond the knee. Referring to Figs 2-4 and 2-7,

| _ Avs

Be

ohh

(2-1)

:

The dynamic resistance can also be calculated from the rule-of-thumb equation

t

a 26 mV

Ip

(2-2)

where If is the de forward current. Thus, for example, the dynamic resistance

for a diode passing a 1 mA forward current is rg = 26 mV/1 mA = 26 0. Equation 2-2 shows that the diode dynamic resistance changes with the level of dc forward current. Since this is not shown in Figs 2-4 and 2-5, the

characteristics are approximations of the actual device characteristics. It should also be noted that Eq. 2-2 gives the ac resistance only for the junction. It does not include the dc resistance of the semiconductor material, which

might be as large as 2 depending on the design of the device. The resistance derived from the slope of the device characteristic does include the semiconductor dc resistance. So rq (from the characteristic) should be slightly larger than rj calculated from Eq. 2-2.

Chapter 2

Semiconductor Diodes

39

Example 2-2 Determine the dynamic resistance at a forward current of 70 mA for the diode characteristics given in Fig. 2-4. Using Eq. 2-2, estimate the diode dynamic resistance. Solution In Fig. 2-4 at Ip = 70 mA, Alp=60mA Ea. q 2-1:

rg =

AVE A i.

and _

AV,#0.025 V

0.025 V 60 mA

oD.2-7) (see Fig.

= 0.42 0, Eq. 2-2:

#4 = 26 mV

_ 26 mV

Ip

70mA

= 0.37 0,

Practice Problems 2-2.1 Calculate the resistances offered by a diode with the characteristics in Fig. 2.5 at 30 V reverse bias and at 60 mA of forward current. 2-2.2 Determine the dynamic resistance at a 50 mA forward current for a

diode with the characteristics in Fig. 2-5. Use Eq. 2-2 to estimate the

_ diode dynamic resistance. 2-3

DIODE APPROXIMATIONS

Ideal Diodes and Practical Diodes As already explained, a diode is essentially a one-way device, offering a low resistance

when

forward-biased

and

a high

resistance

when

biased

in

reverse. An ideal diode (or perfect diode) would have zero forward resistance and zero forward voltage drop. It would also have an infinitely high reverse resistance, which would result in zero reverse current. Figure 2-8a shows the current/voltage characteristics of an ideal diode. Although an ideal diode does not exist, there are many applications where diodes can be assumed to be near-ideal devices. In circuits with supply voltages much larger than the diode forward voltage drop, Vr can be assumed to be constant without introducing any serious error. Also, the diode reverse

current is normally so much smaller than the forward current that the reverse current

can

be

ignored.

These

assumptions

lead

to the

approximate, characteristics for silicon and germanium

near-ideal,

or

diodes shown in

Figs 2-8b and c. Example 2-3 investigates a situation where the diode Vs is

assumed to be constant.

40

Electronic Devices and Circuits

~t

Ver

Vr ml

ty

a

Var

Vr

0.7V

Ik

0.4V

Ip

Ip

R

fee fener

KR

le

t

Ve>

,

Vr

{

t

(a) Ideal diode characteristics _ (b) Germanium diode approximate characteristics

_(c) Silicon diode approximate characteristics

be treated as 2-8 An ideal diode has V; = 0 and Ip = 0. Practical diodes can Figure near-ideal devices if the forward voltage drop is taken into account.

Example 2-3 A silicon diode is used in the circuit shown in Fig. 2-9. Calculate the diode current. Solution E=

Ig Ry

+

Vr

E-Vp

15V-O07V

Ry

4.7kO,

E

=

V7

= 3.04mA

Figure 2-9

Circuit for Ex. 2-3.

Piecewise Linear Characteristic When the forward characteristic of a diode is not

(mA)

available, a straight-line approximation called

the piecewise linear characteristic may be em-

7%”

ployed. To construct the piecewise linear characteristic, Vp is first marked on the horiz-

160

ontal axis, as shown in Fig. 2-10. Then, from Vz,a_

straight line is drawn with a slope equal to the

diode

dynamic

resistance.

Example

2-4

{1 dynamic a silicon diode which has a 0.25 i

current.

|

Ir |

y 40

Al

|

02

04

wy

0.6 08

Ve

Construct the piecewise linear characteristic for resistance

tq

0

Example 2-4 Bina

~fB +H

0

demonstrates the process.

x

(Vg + AVR)

pF

a

and

a 200 mA

maximum ;

forward

Figure 2-10

Diode piece-

aa ee a

r straight-line approxima-

tion of the diode forward characteristic.

Chapter2

Semiconductor Diodes

41

Solution

Plot point A on the horizontal axis at Ve =0.7V

(see Fig. 2-10)

AVz = Alp X rg = 200 mA X 0.25 0 = 0.05 V Plot point B (on Fig. 2-10) at

Ip=200mA

and

Vp = (0.7V + 0.05 V)

Draw the characteristic through points A and B.

DC Equivalent Circuits An equivalent circuit for a device is a circuit that represents the device behavior. Usually, the equivalent circuit is made up of anumber of components, such as resistors and voltage cells. A diode equivalent circuit may be substituted for the device when VE investigating a circuit containing the diode. — —— Equivalent circuits may also be used as device (a) Basic de equivalent circuit models for computer analysis. In Ex. 2-3, a forward-biased diode is assumed . oy Meal

to have a constant forward voltage drop (Vr) and

a

fe

a

negligible series resistance. In this case the diode

equivalent circuit is assumed to be a voltage cell with a voltage Vx (see Fig. 2-11a). This simple dc equivalent circuit is quite suitable for a great .

oer

(6) Complete de equivalent _— Figure 2-11

DC equivalent

circuits for a junction diode.

many diode applications. . A more accurate equivalent circuit includes the diode dynamic resistance (ra) in series with the voltage cell, as shown in Fig. 2-11b. This takes account of the small variations in Vp that occur with change in forward current. An ideal

diode is also included to show that current flows only in one direction. The equivalent circuit without rg assumes that the diode has the approximate characteristics illustrated in Fig. 2-8b or c. With rg included, the equivalent circuit represents a diode with the type of piecewise linear characteristic shown in Fig. 2-10. Consequently, the circuit in Fig. 2-11b is termed the piecewise linear equivalent circuit.

Example 2-5 Calculate Ip for the diode circuit in Fig. 2-12a assuming that the diode has Vg = 0.7 V and rg = 0. Then recalculate the current taking rq = 0.25 ©.

42

Electronic Devices and Circuits

.

Solution

Substituting Vy as the diode equivalent circuit (Fig. 2-12b), Ip

_E-Vp_15V-07V 100

Ry = 80mA

Substituting Vp and rq as the diode equivalent circuit (Fig. 2-12c), Ip

_E-Vp_ Ri +7rg

15V-07V 1092+0.250

= 78 mA

Ry E

i

100

Ve (a) Diode circuit Figure 2-12

7

(b) Diode replaced with voltage cell

(c) Diode replaced with r, and V;

Diode circuits for Ex. 2-5.

1 nected silicon diodes. aum forward current of 100 mA anda

ent when the diode in Problem 2-3.2 is forwith a 15Q resistor and a 3 V battery.

2-4 DC LOAD LINE ANALYSIS DC Load Line Figure 2-13a shows a diode in series with a 100 © resistor (R;) and a supply

voltage (E). The polarity of E is such that the diode is forward-biased, so that there is a diode forward current (Ip). As already discussed, the circuit current can be determined approximately by assuming a constant diode

forward voltage drop (Vg). When the precise levels of the diode current and voltage must be calculated, graphical analysis (also termed dc load line analysis) is employed.

Chapter 2

Semiconductor Diodes

43

(mA)

50N%e 40

Q

30

DC toadjtine =}

Ip

Y 20

NO

—

+— Diode 10

0

|

characteristic

lA 0

1

2)

3

4

5

6

E> (V)

Ve (a) Diode-resistor series circuit

(b) Plotting the dc load line on the

diode characteristics Figure 2-13

Drawing a dc load line on the diode characteristic.

For graphical analysis, a dc load line is drawn on the diode forward characteristics (Fig. 2-13b). This is a straight line that illustrates all dc conditions that could exist within the circuit. Because the load line is always straight, it

can be constructed by plotting any two corresponding current and voltage points and then drawing a straight line through them. To determine two points on the load line, an equation relating voltage, current, and resistance

is first derived for the circuit. From Fig. 2-13a,

E=

(Ip R)

a

Ve

(2-3)

Any two convenient levels of Ip can be substituted into Eq. 2-3 to calculate corresponding Vy levels, or vice versa. As demonstrated in Ex. 2-6, it is convenient to calculate Vp when Ip = 0, and to determine Ig when Vz = 0.

Example 2-6 Draw the dc load line for the circuit in Fig. 2-13a on the diode forward char-

acteristic given in Fig. 2-13b. Solution Substitute Ip = 0 into Eq. 2-3, E or

Ve

=

(Ip Ri)

+

Vp

=

=E=5V

Plot point A on the diode characteristic at Ip =O and

Vp

=

5 V

04+

Ve

44

Electronic Devices and Circuits;

Now substitute Vp = 0 into Eq. 2-3,

E = (Ip Ry) +0 vin

BIVINS

be EH = 2

FR

1000

= 50 mA

Plot point B on the diode characteristic at Ip = 50 mA and

Vz = 0

Draw the dc load line through points A and B.

Q-Point The relationship between the diode forward voltage and current in the circuit in Fig. 2-13a is defined by the device characteristic. Consequently,

there is only one point on the dc load line where the diode voltage and current are compatible with the circuit conditions. That is point Q, termed the quiescent point or dc bias point, where the load line intersects the characteristic. This may be checked by substituting the levels of Ip and Vf at point Q into Eq. 2-3. From the Q point on Fig. 2-13b, Ip = 40 mA and Vx = 1 V. Equation 2-3

states that E = (Ip Ri) + Vz. Therefore, E =(40mA X 1009) +1V

=5v So, with E = 5 V and R, = 100 0, the only levels of Ip and Vx that can satisfy

Eq. 2-3 on the diode characteristics in Fig. 2-13b are 40 mA and 1 V. Note that, although 0 and 5 V were used for Vp when the dc load line was drawn in Ex. 2-6, no functioning semiconductor diode would have a 5 V forward voltage drop. This is simply a convenient theoretical level for

plotting the dc load line.

Calculating Load Resistance and Supply Voltage Ina diode series circuit (see Fig. 2-14a), resistor R; dictates the slope of the dc load line, and supply voltage E determines point A on the load line. So the circuit conditions can be altered by changing either Rj or E. When designing a diode circuit, it may be necessary to use a given supply

voltage and set up a specified forward current. In this case, points A and Q are first plotted and the load line is drawn. Resistor R; is then calculated from the slope of the load line. The problem could also occur in another way. For example, R; and the required Ip ate known, and the supply voltage is to be

Chapter 2

Semiconductor Diodes

45

(mA) 4 Ba

|

40 30

Q

Ik

DC lpad line NZ

AZ ‘i

E

20

10

70

NN

1

2

3

Na 4 5

Wy) 6

Ve (a) Diode-resistor circuit Figure 2-14

(b) Resistor determination

Determination of the required circuit series resistance R; from the slope of the

dc load line.

determined. This problem is solved by plotting point Q and drawing the load line with slope 1/R;. The supply voltage is then read at point A.

Example 2-7 Using the device characteristics in Fig. 2-14b, determine the required load resistance for the circuit in Fig. 2-14a to give Ip = 30 mA. Solution

From Eq. 2-3, Substituting

Vp = E — (Ip Ri) Ip = 0,

Vr =E-0=5V

Plot point A on the diode characteristic in Fig. 2-14b at

Ip=OandVp=5V Now plot point Q in Fig. 2-14b at Ip = 30mA Draw the dc load line through points A and Q. From the load line,

AV,

5V

R,= = —_—_ ‘Alp 37.55mA = 133 0

46

Electronic Devices and Circuits

Example 2-8 Determine a new supply voltage for the circuit in Fig. 2-14a to give a 50 ma diode forward current when R; = 100 0.

Solution

Plot point Q on the diode characteristic in Fig. 2-15 at Ip = 50 mA From the characteristic, read

VR=11V From Eq. 2-3,

Ve =E-—

(Ig Rj)

When Ir changes from 50 mA to 0, Alp = 50 mA and

(see Fig. 2-15)

AVz = Ip Ry = 50 mA X 100 0

(see Fig. 2-15)

=5V The new supply voltage is E=Vpet+AVp=11V+5V =6.1V Point A may now be plotted (on Fig. 2-15) at Ip = 0 and E = 6.1 V, and the

new dc load line may be drawn through points A and Q. (mA) 60 50+—6IN

AVE

40

\

te 30

DQ load line

AS

Alp

20

S

10

0

"

0

i

J

2

3

4

Nu. 5

6

(Vv)

11V

Determination of the required supply voltage for a diode-resistor circuit with Figure 2-15 a given resistor and a specified load current.

Chapter 2

Semiconductor Diodes

47

7%

2-5 TEMPERATURE

EFFECTS

Diode Power Dissipation The power dissipation in a diode is simply calculated as the device terminal voltage multiplied by the current level: P= Ve Tp

(2-4)

Device manufacturers specify a maximum power dissipation for each type of diode. If the specified level is exceeded, the device will overheat and may

short-circuit or open-circuit. The maximum power that may be dissipated in a diode (or any other electronic device) is normally specified for an ambient temperature of 25°C or, sometimes, for a 25°C case temperature. When the

temperature exceeds this level, the device maximum power dissipation must be derated. Figure 2-16 shows the type of power-versus-temperature graph provided

on device data sheets. The maximum power dissipation for any temperature (mW)

1004

“

-

80

—

60 P

,

AP

erating factor|= >>

AT

“NY

AP.

PS

40

~ T

20

0

(°C) 0

10

20

30

40

50

60

70

80

90

100

T Figure 2-16 A power-versus-temperature graph shows how the maximum power dissipation of a device must be derated with

increasing temperature.

48

Electronic Devices and Circuits

is simply read from the graph; then the maximum forward current level is calculated from Eq. 2-4. Instead of a power-versus-temperature graph, some rectifier diode data sheet have a current-versus-temperature graph, which directly gives the maximum forward current at any temperature in the range

of operation. As an alternative to power or current graphs, a derating factor is often listed on device data sheets. The derating factor defines the slope of the power.

versus-temperature graph (see Fig. 2-16); it can be employed to draw the graph or used directly without reference to the graph. The equation for the maximum power dissipation when the temperature changes involves the specified power at the specified temperature (P; at T;), the derating factor (D), and the temperature change (AT). P5

—

(P; at T1)

=

(D

x

AT)

(2-5)

Example 2-9 A diode with 700 mW maximum power dissipation at 25°C has a5 mW/°C derating factor. If the forward voltage drop remains constant at 0.7 V, calculate the maximum forward current at 25°C and at 65°C. Solution At 25°C: From Eq. 2-4,

Ip = >.

F

= a

E

=1A At 65°C: Pz = (P; at T;) — (D X AT)

Kgq. 2-5:

= 700 mW — [5mW/°C &X (65°C — 25°C)] = 500 mW From Eq. 2-4,

I, = BD VY

“a 0.7 V

= 714mA

Forward Voltage Drop Sometimes

it is important to know

the precise level of a diode

forward

voltage drop. In these cases, the graphical analysis techniques discussed it Section 2-4 can be used. However, as explained in Section 1-6 and illustrated

Chapter 2

Semiconductor Diodes

49

(mW) 100

|

jor

60 .

40

|

20 0

/ a 0

04

05

06

ie 07

Figure 2-17

The forward voltage drop

i across a diode decreases b by approx i-

O8

mately 2 mV/°C as the device temperature VE

increases.

in Fig. 2-17, the voltage drop across a forward-biased pn-junction changes with temperature by approximately —1.8 mV/°C for a silicon device and by —2.02 mV/°C for germanium. A diode forward voltage drop at any temperature

can

be

calculated

from

a knowledge

temperature (Vp, at T;,), the temperature voltage /temperature coefficient (AVp/°C).

of

change

Vp

at the

(AT),

| Vin= (Varat Ti) + [AT (AVe/°O)]

starting

and

the

(2-6)

Dynamic Resistance Equation 2-2 for calculating the dynamic resistance of a forward-biased diode is correct only for a junction temperature of 25°C. For higher or lower temperatures, the equation must be modified to

26 mV (4 + a

OS

ke

298°C

(2-7)

where T is the junction temperature in degrees Celsius.

Example 2-10 A silicon diode with a 0.7 V forward voltage drop at 25°C is to be operated with a constant forward current up to a temperature of 100°C. Calculate the diode Vp at 100°C. Also, determine the junction dynamic resistance at 25°C

and at 100°C if the forward current is 26 mA. Solution

Eq. 2-6:

Veo = (V1 at Ti) + [AT (AVg/°C)] = 0.7 V + [(100°C — 25°C)(-1.8 mV/°C)] = 0.565 V (at 100°C)

50

Electronic Devices and Circuits

At 25°C: Eq. q 2-7:

26 mV [T + 273°C _——_— a ie | 298°C |

typo R

WW

a

Vet A

—_—*

Ww

o—

-___}

—

If VN

Con

Cy

(a) Equivalent circuit for

Ca

(b) Equivalent circuit for

a reverse-biased diode

Figure 2-19

-—

|}

(c) AC equivalent circuit for

a forward-biased diode

a forward-biased diode

Equivalent circuits (or models) for reverse-biased and forward-biased diodes,

Reverse Recovery Time

In many applications, diodes must switch rapidly between forward and reverse bias. Most diodes switch very quickly into the forward-biased condition, however, there is a longer turnoff time owing to the junction diffusion capacitance. Vr

| Forward bias

Vp

Reverse

Ve

Forward

bias

bias Ve

Ik

Reverse bias

; ~> t,,.

Figure 2-20 illustrates the effect of a voltage pulse on the diode forward current. When the pulse switches from positive to negative, the diode conducts.in reverse instead of switching off sharply (see Fig. 2-20a). The reverse current (Ig) initially equals the forward current (Ig); then it gradually decreases toward zero. The high level of reverse current occurs because at the instant

of reverse

bias

there

are

charge

carriers

crossing

the

junction

depletion region, and these must be removed. (This is the same effect that produces diffusion capacitance.) The reverse recovery time (t,,) is the time required for the current to decrease to the reverse saturation current level.

Chapter 2

Semiconductor Diodes

53

Typical values of f,, for switching diodes range from 4 ns to 50 ns. The diode

reverse current can be kept to a minimum if the fall time (t,) of the applied voltage pulse is much larger than the diode reverse recovery time. This is illustrated in Fig. 2-20b. Typically Emin) =

10 ib

(2-9)

Example 2-12 Calculate the minimum fall times for voltage pulses applied to a circuit using 1N915 and 1N917 diodes to keep the diode reverse current to a minimum. Solution From diode data sheets,

tr = 10ns for the 1N915

and

t, =3ns for the 1N917

For the 1N915:

Eq..2-9:

ttomin) = 10 trr = 10 X 10 ns = 100 ns

For the 1N917: Rq. 2-9:

tmin) = 10 ty = 10 X 3 ns

= 30 ns

Practice Problems

:

-2-6.1 Determine the maximum reverse recovery time for satisfactory operation of a diode with an applied voltage pulse which has a 0.5 ys fall time:

2-6.2

Estimate a suitable minimum fall time for a pulse which switches a diode from on to off if the reverse recovery time of the diode is 15 ns. 2-6.3. Determine the charge carrier, transit time for a silicon diode which has a capacitance of 11 nF when the forward current is Ip = 50 mA.

2-7

DIODE SPECIFICATIONS

Diode Data Sheets

To select a suitable diode for a particular application, the data sheets, or specifications, provided by device manufacturers must be consulted. Portions of typical diode data sheets are shown in Fig. 2-21 and as data sheets 1 to 3 in Appen-

dix A.

54

Electronic Devices and Circuits oy

Type 1N914 Through 1N917 Silicon Switching Diodes 0.085

| Mechanical ee

0.042

T|r 0165”! 0.220 dimensions in inches

1N916 | 1N917 |

Vp__ I,

Reverse voltage Average rectified forward current

Term

P

Unit

75

50 75

75 75

30 50

Vv mA

Repetitive peak forward current

225

225

225

150

mA

Power dissipation

250

250

250

250

mW

Figure 2-21

Part of data sheet for type 1N914 to 1N917 diodes.

Most data sheets start with the device type number at the top of the page, such as ‘1N914 through 1N917’ or ‘1N5391 through 1N5399’. The 1 (one) in the type number signifies a one-junction device: a diode. This is followed by a short descriptive title, for example, silicon switching diode or silicon rectifier. Mechanical data are also given, usually in the form of an illustration showing the shape and dimensions of the package. The maximum ratings at 25°C are then listed (see Fig. 2-21). The maximum ratings are the maximum voltages, currents, and so on, that

can be applied without destroying the device. It is very important that these ratings not be exceeded; otherwise the diode is quite likely to fail. For reliability, the

maximum ratings should not even be approached. If a diode is to survive a 50 V reverse bias, a device that has a 75 V peak reverse voltage should be selected. Ifthe diode peak forward current is to be 100 mA, a device that can handle 150 mA should be used. It is also important to note that the maximum ratings must be adjusted downward for operation at temperatures greater than 25°C (see Sec-

tion 2-5). A list of other electrical characteristics for the device normally follows the maximum ratings. An understanding of all the parameters specified on a data

sheet will not be achieved

until the data

sheets

have

been

consulted

frequently. However, some of the most important parameters are considered

below. Vror Verm

Peak reverse voltage (also termed peak inverse voltage and dc blocking voltage). This is the maximum reverse voltage that

may be applied across the diode.

Chapter 2

I, or Ip(avy)

Semiconductor Diodes

55

Steady-state forward current. The maximum current that may be

passed continuously through the diode. Igsm

Non-repetitive peak surge current. This current may be passed

for a specified time. The non-repetitive surge current is very much higher than the normal maximum forward current. It is a current that may be allowed to flow briefly when a circuit is first switched on. IgRmM

Ve

Repetitive peak surge current. Peak current that may be repeated over and over again, for example, during each cycle of a recti-

fied waveform. Static forward voltage drop. The maximum forward volt drop for a given forward current and device temperature.

P

Continuous power dissipation at 25°C. The maximum power that the device can safely dissipate continuously in free air. This rating must be downgraded at higher temperatures (see Section 2-5).

Low-Power Diodes The data sheet portion in Fig. 2-21 identifies the 1N914 to 1N917 devices as switching diodes. The average rectified forward current is listed as 75 mA (except for the 1N917). Maximum reverse voltage ranges from 30 V to 75 V. Thus, these diodes are intended for relatively low-current, low-voltage applications, in which they may be required to switch rapidly between on and off states.

Rectifier Diodes The low-power rectifier data sheets (see Appendix A, data sheets A-2 and A-3)

show that the 1N4000 range of rectifiers can pass an average forward current of 1 A, and that the 1N5390 range can pass 1.5 A. Both types have maximum reverse voltages ranging from 50 V to 1000 V. Unlike data sheet A-1, for switching diodes, the rectifier data sheet does not list the reverse recovery

time. Rectifier diodes are generally intended for low-frequency applications

(60 Hz to perhaps 400 Hz) in which switching time is not important. Example 2-13 Referring to Fig. 2-21, determine the following quantities for a 1N915 diode: peak reverse voltage, steady-state forward current, peak repetitive forward

current and power dissipation. Solution For the 1N915: PIV = Ve =50V IlL=75mA

56

Electronic Devices and Circuits

Igrm = 225 mA

P =250 mW

tice’Problems’

. | Referring, to Appendix A, ae

for a 1N5397

2-8 DIODE TESTING

Ohmmeter Tests Diode failure is usually the result of passing excessive forward current through the device, or application of excessive reverse voltage. Both situations can result in devices that offer either an open circuit or a short circuit. Several methods are available for testing diodes. One of the simplest and quickest tests can be made

by using

an ohmmeter

to measure

the

forward and reverse resistance (see Fig. 2-22a). The diode should offer a low

resistance when forward-biased and a high resistance when reverse-biased. A diode is short-circuited when it displays a low resistance for both forward

: Cathode

(a) Testing a diode with

an ohmmeter

Cathode

(b) Testing a diode with

a digital multimeter

Figure 2-22 Analog or digital multimeters may be used for diode testing. When forwardbiased, the diode should display a low resistance, or the typical forward voltage drop. When reverse biased, it should indicate a high reverse resistance.

Chapter 2

Semiconductor Diodes

57

and reverse bias, and open-circuited if a high resistance is measured with

both bias polarities. In the case of an analog ohmmeter with a 1.5 V battery, the low resistance indicated is normally about half the selected range. It is

important to note that when some multi-function instruments are used as ohmmeters, the voltage polarity at the terminals may not be the same as the polarity marked on the instrument. A voltmeter can be used

to check the ohmmeter

terminal polarity.

Use of a Digital Meter Many portable multi-function digital instruments have a diode-testing facility which displays the diode forward voltage when the terminals are connected positive to the anode and negative to the cathode (see Fig. 2-22b). The meter function switch should be set to the diode symbol, as illustrated. When

reverse-connected, a functioning diode produces either an OL display or an

indication of the meter internal voltage.

Plotting Diode Characteristics The forward characteristics of a diode can be obtained by use of the circuit illustrated in Fig. 2-23a. The diode voltage is set at a series of convenient levels, and the corresponding current levels are measured and recorded. The characteristics are then plotted from the resulting table of quantities. The reverse characteristics can be derived in the same way, except that a very sensi-

tive microammeter is required in order to measure the reverse current (Fig. 223b). The microammeter must be connected directly in series with the diode, as shown; otherwise the voltmeter current may introduce a serious error.

Ona (a) Circuit for obtaining diode forward characteristics

we (b) Circuit for obtaining diode reverse characteristics

Figure 2-23 Diode characteristics can be plotted from a table of corresponding current and voltage measurements, obtained by varying the applied voltage in steps and measuring V and I at each step.

Figure 2-24 shows a method of using an XY recorder for drawing the forward characteristics of a diode. The resistor voltage (V1) is directly proportional to the diode forward current (Ir). So Vr; is applied to the vertical input

terminals of the XY recorder, as illustrated. The diode forward voltage (Vp) goes to the horizontal input terminals. When the power supply voltage is slowly increased from zero, the diode forward characteristic is traced out by the pen on the XY recorder.

$8

Electronic Devices and Circuits XY recorder +

Vri { Vertical input

a

Horizontal input Ve {

Figure 2-24

Ry |

Tp

+

a+ o—

Power supply

dD,

An XY recorder can be used for directly plotting diode

characteristics.

If Rj in Fig. 2-24 is a 1 kQ resistor, there is a1 V drop across it for every 1 mA of diode current. Therefore, with the vertical scale of the XY recorder set to

1 V/cm, the (vertical) current coordinate of the graph is 1 mA/cm. A convenient scale for the (horizontal) voltage coordinate is 0.1 V/cm. Diode characteristics can also be investigated by means of a curve tracer, and by computer

graphic analysis software. Example 2-14 The arrangement shown in Fig. 2-24 is to be used to plot the characteristics of a 1N914 diode. Select a suitable resistor for R1, and determine appropriate V/cm scales for the XY recorder. Solution From Fig. 2-21,

56 =75mA

(for the 1N914)

Select a vertical scale of 5 mA/cm for the characteristic so that 75>mA

Vertical scale length (for Ip) = Badia = 15cm Select a vertical scale of 1 V/cm for the XY recorder, so that 15 cm represents 15 V as well as 75 mA. 15 V

Rt = 5 mA = 200 0

and

Pri(max) = (I(max))? Ri = (75 mA)? x 200 O =11W

Chapter2

Semiconductor Diodes

59

Vz might be as large as 0.8 V, so select a horizontal scale of 0.1 V/cm so that

‘ 0.8 V Hi orizontal tal scalescal length (for Vz) i a 01V/em =8cm

Practice Problems _ 2-8.1

/

are

©|

Plot the forward. characteristics for a silicon diode

Sreereaenval data;

bi eit

toy ihe follawiae

apahed ache

28 2 ‘An XY. sagen’ is used ne in Fig. 2-24) tto slat silicon diode forward characteristics to approximately fill a 10 cm by 10 cm square. If the - maximum forward current is to be 100 mA, select suitable V/cm scales . for the recorder and a suitable resistance for Rj.

2-9 ZENER DIODES Junction Breakdown When a junction diode is reverse-biased, there is normally only a very small reverse saturation current: Is on the reverse characteristic in Fig. 2-25a. When

the reverse voltage is sufficiently increased, the junction breaks down and a large reverse current flows. If the reverse current is limited by means of a suitable series-connected resistor (R; in the circuit in Fig. 2-25b), the power

dissipation in the diode can be kept to a level that will not destroy the device. In this case, the diode may be operated continuously in reverse breakdown. The reverse current returns to its normal level when the voltage is reduced below the reverse breakdown level. Ver VR Figure 2-25 A diode can be operated in reverse breakdown if the current is limited by means of a seriesconnected resistor. Zener diodes are designed for operation

(a) Diode reverse characteristic

in reverse break-

(b) Diode-resistor circuit

down.

60

Electronic Devices:and Circuits

Diodes designed for operation in reverse breakdown are found to have a breakdown voltage that remains extremely stable over a wide range of current

levels. This property gives the breakdown diode many useful applications as a voltage reference source. There are two mechanisms that cause breakdown in

a reverse biased pn-junction. With a very narrow depletion region, the electric field strength (volts/width) produced by a reverse bias voltage can be very high. The high-intensity electric field causes electrons to break away from their atoms, thus converting the depletion region from an insulating material into a

conductor. This is ionization by electric field, also called Zener breakdown, and it

usually occurs with reverse bias voltages less than 5 V. In cases where the depletion region is too wide for Zener breakdown, the electrons in the reverse saturation current can be given sufficient energy to cause other electrons to break free when they strike atoms within the deple-

tion region. This is termed ionization by collision. The electrons released in this way collide with other atoms to produce more free electrons in an avalanche effect. Avalanche breakdown is normally produced by reverse voltage levels above 5 V. Although Zener and avalanche are two different types of breakdown, the name Zener diode is commonly applied to all breakdown diodes.

Circuit Symbol and Package

.

The circuit symbol for a Zener diode in Fig. 2-26a is the same as that for an ordinary diode but with the cathode bar approximately in the shape of a letter Z. The arrowhead on the symbol still points in the (conventional) direction of forward current when the device is forward-biased. As illustrated, for operation in reverse bias, the voltage drop (Vz) is positive (+) on the cathode and negative (—) on the anode. Arrowhead indicates Negative terminal for

Zener operation \

conventional current direction when the device is forward-biased

Anode

YSs/

Cathode

Positive terminal for

Zener operation L

(a) Circuit symbol Anode

Cathode

(b) Low-current Zener diode

Figure 2-26 package.

Zener diode circuit symbol and low-current Zener diode

Chapter 2

Semiconductor Diodes

61

Low-power Zener diodes are available in a variety of packages. For the device package shown in Fig. 2-26b, the coloured band identifies the cathode terminal, as in the case of an ordinary low-current diode. High-current Zener diodes are also available in the type of package that allows for mounting on a heat sink.

Characteristics and Parameters The typical characteristics of a Zener diode are shown in detail in Fig. 2-27. Note that the forward characteristic is simply that of an ordinary forward-biased diode. Some important points on the reverse characteristic are Vz

Zener breakdown voltage

Izy Izx

‘Test current for measuring Vz Reverse current near the knee of the characteristic, the minimum

reverse current to sustain breakdown

Iza

Maximum Zener current, limited by the maximum power dissipation j

t Vz

yy

I

“R

_—7

-§

(v) =

-4

yi

=~

-3

-3

1

characteristic

[+

c

Reverse

Ix

Vp—> |

~

|

|

Forward

|

|

characteristic 10

i

tV0

|

| 15

}

tO r

AT

20.

Oty,

ZU

|

| | |

i |

I

|

TZ |

OR Za

|

|

J

|

VN ave

|

30

1

Oe.

VI

40Lt

AB

}

|

L Eee

|

|

rs

(mA)

Figure 2-27

Typical characteristics for a Zener diode. The most im-

portant parameters are the Zener voltage Vz, the knee current Izx, the test current Iz7, and the maximum current Izm.

The dynamic impedance (Zz) is another important parameter that may be

derived from the characteristics:

62

Electronic Devices:and Circuits

ve,

ie eg

,

As illustrated in Fig. 2-27, Zz defines how Vz changes with variations jp diode reverse current. When measured at Izr, the dynamic impedance js designated (Zzr). The dynamic impedance measured at the knee of the

characteristic (Zzx) is substantially larger than Zzr. The Zener diode may be operated at any (reverse) current level between

Izx and Iz. For greatest voltage stability, the diode is normally operated at the test current (Izy). Many low-power Zener diodes have a test curren} specified as 20 mA; however, some devices have lower test currents.

Data Sheet A portion of a data sheet for low-power Zener diodes with voltages ranging

from 3.3 V to 12 V is shown in Fig. 2-28. (See also data sheet A-4 for 2.4 V to 110 V Zener diodes in Appendix A.) Note in Fig. 2-28 that the Vz tolerance is stated as +5% or +10%. This means that the devices can be purchased with either a +5% or +10% tolerance on Vz. For a 1N753 with a +10% tolerance, the actual Vz is 6.2 V +10%, or 5.58 V to 6.82 V. The Zener voltage remains stable

at whatever it happens to be within this range.

_ Type 1N 746 Through 1N759 Silicon Zener Diodes

3.3 V to 12 V (+5% or +10%)

3

Py = 400 mW (derate linearly above 50°C at 3.2 mW/°C). - Electrical characteristics at 25°C ambient temperature Type _ | number (

Nominal Zener

Test current

voltage

Iz (mA)

Zener impedance Zz (Q)

Leakage current

Reverse temperature

Tr (wA)

coefficient

Vz (V)

az (%/°C)_|

IN746 IN747

3.3 3.6

20 20

28 24

10 10

—0.062 —0.055

IN753 IN755

6.2 7.5

20 20

7 6

0.1 0.1

+0.022 +0.045

IN757

9.1

20

10

0.1

+0.056

IN759

12.0

20

30

0.1

+0.060

Figure 2-28

Portions of a data sheet for low-power Zener diodes.

The data sheet also lists the dynamic impedance

(Zz7); reverse leakag

current (Ip), which is the reverse current before breakdown;

and the temper

Chapter2

Semiconductor Diodes

63

ature coefficient (az) for the Vz of each device. The Zener voltages at any

temperature can be calculated as follows:

Temperature-compensated Zener diodes are also available with extremely low temperature coefficients. Low-power Zener diodes are generally limited to a maximum power

dissipation of 400 mW (Pp in Fig. 2-28). Higher power devices are available. All of the power dissipations must be derated with temperature increase, exactly as explained in Section 2-5. When the maximum Zener current is not listed on the device data sheet, it may be calculated from the power dissipation equation:

Pp = Vala :

(2-12)

Example 2-15 Calculate the maximum

current that may be allowed to flow through

a

1N755 Zener diode at device temperatures of 50°C and 100°C. Solution

From data sheet A-4 in Appendix A, it can be seen that for the 1N755 Zener diode, Vz = 7.5 V, Pp = 400 mW at 50°C, and the derating factor = 3.2 mW/°C.

At 50°C:

.

From Eq. 2-12,

Pp _ 400mV

Izm = Ve

75V

= 53.3mA

At 100°C: Eq. 2-5:

Pz = (P; at T;) — [AT X derating factor] = 400 mW

— [(100°C — 50°C) X 3.2 mW/°C]

= 240 mW

fois pacer de Fore ae

Eg a

2Ve, «== = 32mA

TV

64

Electronic Devices and Circuits

Example 2-16 For the Zener diode circuit in Fig. 2-29, E = 20 V, and Ri = 620 (1. The Zener diode is a 1N755. Cal-

culate the diode current and power dissipation.

Solution

Figure 2-29

Circuit for Ex. 2-16

From the data sheet in Fig. 2-28, it is seen that for the 1N755 Zener diode, Vz = 7.5 V Var

=

B—

Vz'=20V

-7.5.V

=125V

Ip = Ip, = VSL = SV ZU

TRTRR, ~~ 6200

= 20.16 mA Pp = Vzlz = 7.5 V

X 20.16mA

= 151 mW

Equivalent Circuit The de equivalent circuit for a Zener diode is simply a voltage cell with a voltage Vz, as in Fig. 2-30a. This is the complete equivalent circuit for the device for all de calculations. For the ac equivalent circuit (Fig. 2-30b), the dy-

namic impedance is included in series with the voltages cell. The ac equivalent circuit is used in situations where the Zener current is varied by small amounts. It must be understood that

——|

Vz -—

(a) DC equivalent circuit Vz

—

Zy

rA\—

(b) AC equivalent circuit cieewese peaachGent: valarieciesaes tara Barer

these equivalent circuits apply only when the diszia. Zener diode is maintained in reverse breakdown. If the device becomes for-

ward-biased, then the equivalent circuit for a forward-biased diode must be used.

Example 2-17

|

A Zener diode with Vz = 4.3 V has Zz equal to 22 O when Iz = 20 mA. Cal culate the upper and lower limits of Vz when Iz changes by +5 mA. Solution

AVz = +(Alz X Zz) = +(5 mA X 22.0)

Chapter 2

Semiconductor Diodes

65

= 4110 mV Vitex) = Vz + AVz =43V + 110 mV =441V

Vaumin) = Vz — AVz = 4.3V - 110 mV = 4.19V Practice Problems 2-9. 1, Calculate the maximum

.

current for a IN753 Zener diode at device

_ temperatures. of 50°C and 100°C.

2-9, 2 A1N749 Zener diode is connected in series with an 820 0 resistor and

a 12,V supply. Calculate the diode current and power dissipation. Review Questions Section 2-1 2-1.

Sketch the symbol for a semiconductor diode, labelling the anode and cathode and showing the polarity and current direction for forward bias. Show the direction of movement of charge carriers when the device is (a) forward-biased and (b) reverse-biased.

2-2

Draw sketches to show the appearance of low-current and medium-current diodes, and show how the cathode is identified in each case.

Section 2-2 2-3.

Sketch typical forward and reverse characteristics for a germanium diode and

2-4

for a silicon diode. Discuss the characteristics, and compare silicon and germanium diodes. —_— For diodes, define forward voltage drop, maximum forward current, dynamic resistance, reverse saturation current, and reverse breakdown voltage.

2-5

Show how the diode dynamic resistance can be determined from the forward characteristics. Write an equation for calculating the dynamic resistance from the de forward current.

Section 2-3 2-6

Sketch the characteristics for an ideal diode and the approximate characteris-

2-7

tics for practical diodes. Briefly explain each characteristic. Draw the dc equivalent circuit for a diode and the piecewise linear equivalent

circuit. Discuss the application of each. Section 2-4 2-8 Explain the purpose of a dc load line. Write the equation for drawing a dc load line for a series circuit consisting of a supply voltage (E), a resistor (R,), and a

diode (D}).

66

Electronic Devices and Circuits

2-9

Define the Q-point in a diode circuit, and explain how it is related to the diode characteristics and the dc load line.

Section 2-5

2-10

Sketch and explain a power-versus-temperature graph for a diode. Define the power-derating factor for a diode.

2-11

Discuss how temperature change affects diode forward voltage drop.

Section 2-6 2-12 2-13

Explain the origins of depletion layer capacitance and diffusion capacitance, and discuss the importance of each. Sketch the complete equivalent circuits for forward-biased and reverse-biased

diodes. Sketch the ac equivalent circuit for a forward-biased diode. Briefly 2-14

explain each circuit. Define reverse recovery time. Sketch waveforms to show the effect of reverse recovery time on a diode switched rapidly from on to off. Explain each waveform.

Section 2-7 2-15 2-16

Discuss the major differences between switching diodes and rectifier diodes. Define the following diode quantities: peak reverse voltage, repetitive peak surge current, and steady-state forward current.

Section 2-8 2-17 Describe how an ohmmeter and a digital multimeter may be used for testing 2-18 2-19

diodes. Sketch circuits for obtaining diode forward and reverse characteristics by measuring corresponding current and voltage levels. Explain. Draw asketch to show how the forward characteristics of a diode may be plotted on an XY recorder.

Section 2-9 2-20

2-21 2-22

Discuss the different types of junction breakdown that can occur in a reverse-

biased diode. Sketch the circuit symbol for a Zener diode, and briefly explain Zener diode operation. Sketch typical characteristics for a Zener diode. Explain the shape of the characteristics, and identify the important points. Sketch the equivalent circuit for a Zener diode. Briefly explain.

Problems Section 2-2 2-1

Calculate

the

static

forward

resistance

for

the

characteristics

in

Fig. 2-31 at a 200 mA forward current. Determine the reverse resistance at 4 75 V reverse voltage.

Chapter 2

Semiconductor Diodes

67

(mA) AAD YUU

QEQ LIU

—25

;

!

r (V) y

r

—50

R

—100 -75

Ha

oI

(v)

ND. L009

es]

4

(wA) Figure 2-31 and 2-9.

2-2 2-3

Diode

characteristics

for Problems

2-1,

2-2,

Determine the dynamic resistance at a 150 mA forward current for a diode with the characteristics shown in Fig. 2-31. Calculate the static forward resistance for the diode characteristics shown in Fig. 2-32 at a 25 mA forward current. Also, determine the dynamic resistance for the device at Ip = 25 mA, using the characteristic and using Eq. 2-2.

Section 2-3 2-4

Calculate the forward current in a circuit consisting of a germanium diode connected in series with a 9 V battery and a 3.3 kQ resistor.

(mA) 60 50 40 Iz

30

20 10

0

0

02

04

06

08

10

12

14

16

18

(V)

VE Figure 2-32 2-11.

Diode characteristics for Problems 2-3, 2-10, and

B 68

Electronic Devices and Circuits

A silicon diode in series with a 2.7 kQ resistor and a battery is to have an Ir of

1.96 mA. Calculate the battery voltage.

Draw the piecewise linear characteristics for a silicon diode 0.6 © dynamic resistance and a.75 mA maximum forward current. Draw a straight-line approximation of the forward characteristic for a

with

a

silicon

diode that has a 0.5 0 dynamic resistance and a maximum forward current of 300 mA. Section 2-4

2-8

2-9

2-10

2-11

A diode with the characteristics in Fig. 2-13b is to pass a 35 mA current froma 9.5 V supply. Draw the dc load line and calculate the required series resistance value. Determine the new current level when the supply is reduced to 3.5 V, A diode with the forward characteristic in Fig. 2-31 is connected in series with a 30 © resistance and a 6 V supply. Determine the diode current, and find the new current when the resistance is changed to 20 0. A diode which has the characteristics shown in Fig. 2-32 is to pass a 20 mA for-

ward current when the supply is 12 V. Determine the value of resistance that must be connected in series with the diode. Calculate the new supply voltage for the circuit in Problem 2-10 to give a 15 mA current level.

Section 2-5

2-12

2-13

2-14 2-15

A diode with a maximum power dissipation of 1000 mW at 25°C is to pass an average forward current of 500 mA. The forward voltage drop for the device is 0.8 ‘V, and the power derating factor is 10 mW/°C. Calculate the maximum temperature at which the diode may be safely operated. The diode specified in Problem 2-12 is to be operated at a temperature of 75°C. Calculate the maximum level of average forward current that the diode can safely pass. Draw the power dissipation-versus-temperature graph for the diode specified in Problem 2-12. A diode with a 0.9 V forward drop has a 1.5 W maximum power dissipation at 25°C. If the device derating factor is 7.5 mW/°C, calculate the maximum for-

ward current level at 25°C and at 75°C. Assume that Vp remains constant. 2-16

Estimate the forward voltage drop at 75°C of the silicon diode in Problem 2-15. Determine the junction dynamic resistances at the temperature extremes if [Fis

2-17

20 mA. A5 V supply is applied via a 150 © resistor to a silicon diode and a germanium diode that are connected in series. Determine the diode current at 25°C and at 100°C.

Section 2-6 2-18 Calculate the minimum fall time reverse recovery time of (a) 6 ns 2-19 A diode has an applied voltage maximum reverse recovery time

for a voltage pulse applied to a diode witha and (b) 50 ns. with a 200 ns fall time. Determine the diode for satisfactory operation.

Chapter 2

2-20 2-21

Semiconductor Diodes

69

Calculate a suitable minimum fall time for a switching waveform applied to a diode that has a 12 ns reverse recovery time. Calculate the minimum fall time for a voltage pulse applied to a circuit with a 1N914 diode.

Section 2-7

2-22

2-23

A diode connected in series with a 560 © resistor has a supply voltage that alternates between peak levels of +150 V and —150 V. Select a suitable device from the data sheets A-1 and A-2 in Appendix A. Referring to data sheet A-3 in Appendix A, determine the peak reverse voltage and average rectified forward current for a 1N5398 diode.

2-24

A rectifier diode has to pass an average current of 55 mA and survive a 40 V peak reverse voltage. Select a suitable device from data sheets A-1 to A-3 in Appendix A.

Section 2-8 2-25

The arrangement shown in Fig. 2-24 is to be used to plot the forward characteristics of a 1N917 diode. Determine a resistance value for Ri, and select appropriate

2-26

V/cm scales for the horizontal and vertical inputs of the XY recorder. The graph should be approximately 20 cm x 20cm. Plot the forward characteristics of a diode from the following experimental data:

30. Section 2-9 2-27

Determine the maximum current that may be used with a 1N757 Zener diode

2-28

at temperatures of 25°C and 80°C. A 1N750 Zener diode is connected in series with an 470 © resistor and a 10 V supply voltage. Calculate the diode current and power dissipation.

Practice Problem 2-2.1 2-2.2 2-3.1 2-3.2 2-3.3 2-4.1 2-4.2 2-4.3 2-5.1 2-5.2

Answers

5.5 0, 30 MQ, 0.5 0,050 2.89 mA (Point A: 0 mA, 0.3 V), (Point B: 100 mA, 0.35 V) 174 mA 20 mA 500 3.45 V 154 mA, 61.5mA 267 mV, 421 mV, 1.23 0, 1.54 2

70

2-5.3 2-6.1 2-6.2 2-6.3 2-7.1 2-7,2 2-8.2 2-9.1 2-9.2

Electronic Devices and Circuits

780 mV 50 ns 150 ns 154 ns 600 V,1.5A,50A 1N5392

Vertical 1 V/cm, Horizontal 0.1 V/cm, 100 0 64.5 mA, 38.7 mA

40.4 mW

CHAPTER 3 Diode Applications Objectives You will be able to:

1 Sketch various diode half-wave and full-wave rectifier circuits and their input and output waveforms. Explain the operation of each circuit. 2 Sketch basic dc power supply circuits using rectifiers and capacitor filters. Discuss the operation and performance of each circuit. 3 Design dc power supply circuits and analyze them to determine diode current and voltage levels, output ripple voltage, line and load effects, and line and load regulation. 4 Sketch Zener diode voltage regulator circuits, and explain their operation. 5 Design and analyze RC and LC m-input and L-input filters for dc power supplies.

6 Design and analyze Zener diode voltage regulator circuits. 7 Draw diagrams for series and shunt clipping circuits and sketch their input and output waveforms. Explain the operation of each circuit. 8 Design and analyze series and shunt clipping circuits. 9 Draw diagrams for clamping circuits and dc voltage multipliers. Sketch the input and output waveforms, and explain the circuit operation. 10 Design and analyze clamping circuits and dc voltage multipliers. 11 Sketch diode AND and OR gate circuits, and explain their

operation. Calculate circuit current and voltage levels.

INTRODUCTION One of the most important applications of diodes is rectification: conversion of a sinusoidal ac waveform into single-polarity half cycles. Rectification may be performed by half-wave or full-wave rectifier circuits. A dc power supply converts a sinusoidal ac supply to dc by rectification and filtering. The filtering process normally involves the use of a large reservoir capacitor, which charges to the peak input voltage level to produce the dc output. The capacitor partially discharges between peaks of the rectified waveform, and this results in a ripple voltage on the output. The ripple can be reduced by the

72

Electronic Devices and Circuits

use of RC or LC filters. Power supplies are specifiedyaccording to the dc output voltage, load current, and ripple voltage. Power supply performance is defined in terms of the output voltage stability when the input voltage o; the load current changes. Other important diode applications include clipping, clamping, de volt. age multiplication, and logic circuits. Diode clipping circuits are used for clipping off an unwanted portion of a waveform. Clamping circuits change the dc voltage level of a waveform without affecting the wave shape. Dc voltage multipliers are applied to change the level of a dc voltage source to a desired higher level. Logic circuits produce a high or low output voltage, depending upon the voltage levels at several input terminals.

3-1

HALF-WAVE RECTIFICATION

Positive Half-Wave Rectifier A diode positive half-wave rectifier circuit is shown in Fig. 3-1a. An alternating input voltage is applied via a transformer (T;) to a single diode connected in series with a load resistor Ri. The transformer is normally necessary to dcisolate the rectifier circuit from the ac supply. The diode is forward-biased

during the during the during the half cycles, waveform ing voltage

positive half cycles of the input waveform, and reverse-biased negative half cycles. Substantial current flows through Ry only positive half cycles of the input. For the duration of the negative the diode behaves almost as an open switch. The output voltage developed across Ry, is a series of positive half cycles of alternatwith intervening very small negative voltage levels produced by

the diode reverse saturation current. When the diode is forward-biased (see Fig. 3-1b), the voltage drop across itis

Vz, and the output voltage is (input voltage) — Vp. So, the peak output voltage is : Vo

ae

Vi

aN

Ve

(3-1)

Note that Vp; = 1.414Vi, where V; is the rms level of the sinusoidal input voltage to the rectifier circuit (from the transformer output).

The diode peak forward current is ee

During the negative half-cycle of the input (Fig. 3-1c), the reverse-biased diode offers a very high resistance. So there is only a very small reverse cu! rent (Ip), giving an output voltage Mort

Ip Ry

(3-3)

Chapter 3

Input waveform

Diode Applications

73

Dy T -

Output waveform

(a) Transformer-coupled half-wave rectifier circuit

ipa waveform

V,pi

+

z, Ve

_

D,

1

V;

Output waveform

i

Ry

a

||*

\*

S

Vo

NL V,

V; po
iF

Oo——uNXOro

V, =i

/

Ry

Cy

+

(c) Effect of negative input

(d) Use of a reservoir capacitor

Positive half-wave rectifier circuit. The diode is forward-biased during the posiFigure 3-1 tive half-cycle of the applied waveform and reverse biased during the negative half-cycle.

While the diode is reverse-biased, the peak voltage of the negative half-cycle of the input is applied to its terminals. Thus the peak reverse voltage, or peak inverse voltage (PIV), applied to the diode is Ve

=

PIV= Voi

(3-4)

The average and rms values of the half-wave rectified waveform can be determined as Voyave) = 0.318 Vpo and Voams) = 0.5 Vpo. However, most rectifier circuits use a reservoir capacitor at the output terminals to smooth the rec-

tified voltage wave into direct voltage (see Fig. 3-1d). It is very important to note that the presence of the capacitor changes the output waveform and that it sub-

stantially affects the load current and voltage and the diode current and voltage. This is discussed in Sections 3-2 and 3-3. Example 3-1

A diode with Vp = 0.7 V is connected as a half-wave rectifier. The load resistance is 500 Q, and the (rms) ac input is 22 V. Determine the peak output voltage, the peak load current, and the diode peak reverse voltage.

74 _ Electronic Devices and Circuits

Solution Vpi = 1.414 V; = 1.414 X 22 V

=311V

Vo = Voi — Vp = 311V -0.7V

Ege

= 30.4V t=

Eq. 3-2:

V’po _ 30.4V

PR,

5000

= 60.8mA

Eq. 3-4:

PIV = V,i = 31.1V

Negative Half-Wave Rectifier Figure 3-2a shows the effect of reversing the diode polarity in the circuit of Fig. 3-1. The negative half-cycle of the ac input waveform (instead of the positive half-cycle) is passed to the load resistor. Consequently, the peak output voltage and current are negative quantities.

Figure 3-2b shows a positive half-wave rectifier circuit with the positive output terminal grounded. This is possible because, as already discussed, the ac input to the rectifier circuit is normally derived from the secondary of a transformer. Either of the two output terminals may be grounded so long as there is no other grounded point in the circuit. Now, when the transformer output waveform is at its peak positive level, the load waveform is actually a peak

Ty

3 TY -

Output waveform

+

(a) Negative rectification by reversing the diode polarity Variac

Ty

Packs

3||

Output waveform

115V

60 Hz E

(b) Negative rectification by grounding the positive output terminal

|

3| wn

Isolation transformer

(c) An isolation transformer should be used when the power supply transformer is not available

Figure 3-2 Negative half-wave rectification is performed when the diode is forward-biased during the negative half-cycle of the input. Negative output half-cycles can also be derived from a positive half-wave rectifier if the positive output terminal is grounded. Rectifier circuit should be transformer-coupled for dc isolation from the input.

Chapter 3

Diode Applications

75

negative quantity, as shown, because output terminal B is negative with respect to the grounded terminal A. The diode is reverse-biased during the negative half-cycle of the transformer output, and so the load voltage is zero. Thus, a

negative half-wave rectified waveform can be generated simply by grounding the positive output terminal of a positive rectifier circuit. It is important to note that one of the rectifier circuit output terminals may be grounded only when the transformer is present to provide complete dc isolation from the ac supply. If a variable transformer (autotransformer or variac) is used without a power supply transformer, a 1:1 isolation transformer must be substituted for the power supply transformer to provide the required dc isolation (see Fig. 3-2c).

Practice Problems 3-1.1 A half-wave rectifier circuit has a15° V ac input and a 330 2 load resistance. Calculate the peak output voltage, the peak load current, and the diode maximum reverse voltage. 3-1.2 A half-wave rectifier (as in Fig. 3-1) produces a 40 mA peak load cur-

rent through a 1.2 kQ resistor. If the diode is silicon, calculate the rms a ee voller and the diode PIV.

3-2 FULL-WAVE RECTIFICATION Two-Diode Full-Wave Rectifier The full-wave rectifier circuit in Fig. 3-3 uses two diodes, and its input voltage is supplied from a transformer (Tj) with a centre-tapped secondary winding. The circuit is essentially a combination

of two half-wave

rectifier circuits,

each supplied from one half of the transformer secondary. When the transformer output voltage is positive at the top, as illustrated in

Fig. 3-4a, the anode of D is positive, and the centre tap of the transformer is connected to the cathode of D; by Ri. Consequently, D, is forward-biased, and load current (I) flows from the top of the transformer secondary through Dj,

through R;, from top to bottom, and back to the transformer centre tap. During this time, the polarity of the voltage from the bottom half of the transformer secondary causes diode Dz to be reverse-biased, as illustrated. For the duration of the negative half-cycle of the transformer output, the polarity of the transformer secondary voltage causes D; to be reverse-biased and D> to be forward-biased (see Fig. 3-4b). I, flows from the bottom terminal

of the transformer secondary through diode D2, through R, from top to bottom, and back to the transformer centre tap. The output waveform is the

combination of the two half-cycles, that is, a continuous series of positive halfcycles of sinusoidal waveform. This is positive full-wave rectification. Figure 3-5 shows that if the polarity of the diodes is reversed, the output waveform is a series of sinusoidal negative half-cycles: negative full-wave

76

Electronic Devices and Circuits

Output waveform

Pr

T,

eee

i

D,

Input waveform

V.

I

O,

Rt = | u¢Vo

=

P

;

«3 mo Dy Figure 3-3

Full-wave rectification can be performed by two diodes used with a trans-

former that has a centre-tapped secondary. The diodes are connected to conduct during positive half-cycles of the transformer output to give a positive output waveform.

Forward-biased

Reverse-biased

+ OO

oF

all

mS|k Vo

V,

Output waveform

=

Output waveform

We

Veo

=) *

=

D,

- Reverse-biased

Forward-biased

(a) D, forward-biased, D, reverse-biased

(b) D, reverse-biased, D, forward-biased

Ina two-diode full-wave rectifier circuit, diodes D; and D2 conduct alternately. Figure 3-4 When D, is forward-biased, Dz is reverse-biased, and vice versa.

Output waveform Input waveform

D,

|__l@q —_ Figure 3-5

Two-diode negative full-wave rectification is produced by connecting the

diodes to conduct during negative half-cycles of the transformer output.

°

Chapter 3

Diode Applications

77

rectification. The centre tap of the transformer is normally grounded, as shown in Fig. 3-5, and so the only way to obtain a negative output from this type of circuit is to reverse the diode polarity.

Bridge Rectifier The centre-tapped transformer used in the circuit of Fig. 3-3 is usually more expensive and requires more space than additional diodes. So a bridge rectifier is the circuit most frequently used for full-wave rectification. The bridge rectifier circuit in Fig. 3-6 is seen to consist of four diodes con-

nected with their arrowhead symbols all pointing toward the positive output terminal of the circuit. Diodes D, and D> are series-connected, as are D3 and D4. The ac input terminals are the junction of D, and D2 and the junction of D3 and Dy. The positive output terminal is at the cathodes of D; and D3, and the negative output is at the anodes of D2 and D4.

During the positive half-cycle of input voltage, diodes D, and Dy are in series with Rj, as illustrated in Figs 3-7a and b. Load current (J,,) flows from

the positive irput terminal through D; to R,, and then through R;, and D, back to the negative input terminal. Note that the direction of the load current through Ry is from top to bottom. During this time, the positive input terminal is applied to the cathode of D2 and the negative output is at the D2 anode (see Fig. 3-7a). So D2 is reverse-biased during the positive half-cycle of the input. Similarly, D3 has the negative input at its anode and the positive Input waveform

Figure 3-6

Output waveform

A full-wave bridge rectifier circuit uses four diodes and a transformer with a

single secondary winding.

output at its cathode during the positive input half-cycle, causing D3 to be reverse-biased. Figures 3-7c and d show that diodes D2 and D3 are forward-biased during the negative half-cycle of the input waveform, while D, and Dy are reverse-

biased. Although the input terminal polarity is reversed, I, again flows through R;, from top to bottom, via D3 and Dp. It is seen that during both half-cycles of the input, the output terminal polarity is always positive at the top of Ry and negative at the bottom. Both

positive and negative half-cycles of the input are passed to the output. The negative half-cycles are inverted, so that the output is a continuous series of

positive half-cycles of sinusoidal voltage.

78.

Electronic Devices and Gircuits)

(b) D, and D, forward-biaseg

+

D3 Ry

| I,

D2 (c) Effect of negative half-cycle of input Figure 3-7

(d) D3 and D, forward-biased

Ina bridge rectifier circuit, diodes D, and D4 are forward-biased during the

positive half cycle of the input, while Dz and Dg are reverse-biased. During the input negative half-cycle, D2 and D, are forward-biased and D, and D, are reversed. In each case current flows through load resistor RA. in the same direction (from top to bottom).

A full-wave derived from a circuit will not However, given

bridge rectifier circuit always requires that the input be transformer that provides dc isolation from the supply. The function correctly if one of its input terminals is grounded. the required dc isolation between supply and output, either

output terminal may be grounded to provide a positive or negative output voltage.

The bridge rectifier has two forward-biased diodes in series with the supply voltage and the load. Because each diode has a forward voltage drop (Vz), the peak output voltage is Vo

= Voi

— 2Vr

(3-5)

The average and rms values of the full-wave rectified waveform can be determined as follows: Voaye) = 0.637Vpo and Voums) = 0.707V5. However, once again it should be noted that most rectifier circuits use a reservoir capacito! to smooth the rectified voltage wave into direct voltage, and the presence of the capacitor changes the output waveform and substantially affects the load current ald voltage and the diode current and voltage. See Sections 3-2 and 3-3.

Chapter 3

Diode Applications

79

Example 3-2 Determine the peak output voltage and current for the bridge rectifier circuit in Fig. 3-7 when Vj = 30 V, Ry, = 300 Q, and the diodes have Vp = 0.7 V.

Solution

Vpi = 1.414V; = 1.414 x 30 V = 42.42 V Vo = Vpi — 2Vr = 42.42 V — (2 X 0.7 V) =41V

Eq. 3-5:

Eq. 3-2:

[=

Vo

41 V “aa

= 137 mA

More Bridge Rectifier Circuits Figure 3-8 shows two common methods of drawing a bridge rectifier circuit. Although they both look more complex than the circuit in Fig. 3-7, they are exactly the same circuit. The cathodes of D; and Ds in all three circuits are connected to the positive output terminal, and the anodes of D2 and Dy, are con-

nected to the negative output terminal. The ac input is applied to the junction of D; and D, and to the junction of D3 and Dy.

Figure 3-8

Two additional ways of drawing a

bridge rectifier circuit diagram.

Both of these circuits have the diodes conn cted exactly as in Fig. 3-6.

Practice Problems

3-2.1 Determine the peak load voltage, peak current, and power dissipation in a 470 load resistor connected to a bridge rectifier circuit that has a 3-2.2

24 V ac input. The rectifier diodes are germanium. A bridge rectifier with silicon diodes and a 680 © load resistor has an 18 V peak output. Calculate the power dissipated in the load resistor

and the rms input voltage.

so

Electronic Devices and Circuits

3-3 HALF-WAVE RECTIFIER POWER SUPPLY Capacitor Filter Circuit When. a sinusoidal alternating voltage is rectified (see Sections 3-1 and 3-2), the resulting output waveform is a series of positive (or negative) half.

cycles of the input; it is not direct voltage. To convert to direct voltage (dc voltage), a smoothing circuit or filter must be employed. Figure 3-9a shows a half-wave rectifier circuit with a single capacitor filter (Ci) and a load resistor (Ri), and Fig. 3-9b shows the output waveform. The capacitor, termed a reservoir capacitor, is charged almost to the peak level of the circuit input voltage when the diode is forward-biased. This occurs at V)j, as

illustrated in Fig. 3-9c, giving a peak capacitor voltage:

(3-6)

Ve =Vpi — Ve Direct voltage

owt

with ripple

Input waveform

+-

Ve

Ve

Rectified wave

Current pulse (a) Half-wave rectifier circuit with a reservoir capacitor

a

(ry

:

(b) Output waveform

Reverse-biased

Pe

o—p|—

+a Voi

— i+

Voi —eon ey

D, pVc=Vpi- Ve

Ga. Gaerne”

|

(c) Gq is charged to V,; — Vp Figure 3-9

x

o—p}

aa.

-Pr a

PO

Cree

oOo}

~

(d) D, is reverse-biased when Vj falls below V,,;

A reservoir capacitor smooths the output from a rectifier circuit by charging

to the peak output voltage and retaining most of its charge between

peaks.

When the instantaneous level of input voltage (at the diode anode) falls

below V>i, the diode becomes reverse-biased because the capacitor voltage (Vc) (at the diode cathode) remains close to (Vpi — Vg) (see Fig. 3-9d). With the diode reverse-biased, there is no capacitor charging current, and th capacitor begins to discharge through the load resistor (Ry). So Ve fall slowly, as shown by the capacitor voltage waveform in Fig. 3-9b.

Chapter 3

—

Diode Applications

81

The diode remains reverse-biased (as Vc decreases) throughout the rest of

the input positive half-cycle, the negative half-cycle, and the first part of the positive half-cycle again until the instantaneous level of Vj becomes greater

than Vc once more. At this point, current flows through the diode to recharge the capacitor, causing the capacitor voltage to return to (Vp; — Vr). The charge

and discharge of the capacitor cause the small increase and decrease in the capacitor voltage, which is also the circuit output voltage. It is seen that the circuit output is a direct voltage with a small ripple voltage waveform superimposed (Fig. 3-9b).

Ripple Amplitude and Capacitance The amplitude of the ripple voltage is affected by the load current, the reservoir capacitor value, and the capacitor discharge time. The discharge time

depends upon the frequency of the ripple waveform, which is the same as the ac input frequency in the case of a half-wave rectifier. With a constant load current, the ripple amplitude is inversely proportional to the capaci-

tance: the largest capacitance produces the smallest ripple.

The ripple amplitude can be calculated from the capacitor value, the load current, and the capacitor discharge time. Consider the circuit output voltage waveform illustrated in Fig. 3-10a. The waveform quantities are as follows:

Eave

average dc output voltage

Eomax)

Maximum output voltage

Eoin)

Minimum output voltage

V, T

ripple voltage peak-to-peak amplitude time period of the ac input waveform

ty

capacitor discharge time

ty

capacitor charge time

0; 0,

phase angle of the input wave from zero to Eocmin) phase angle of the input wave from Eoimin) tO Eoqnax) Direct voltage J with ripple

| V,

= \

+

ae

Ey max

a

PE

|

L

mee t

Current | 90 pulse

\

si_.°

180 ty

°

0;

|

co

J ~
=

Vor

Ro + Rp

Vcg=20V =

20V 4.9k0

= 4.08 mA

Figure 6-7

_

Voltage-divider

bias circuit with a bypassed

emitter resistor. The dc load

is (Rc + Re), and the ac load

is Rc when there is no ca-

Plot point Bat

Ic = 4.08 mA and Vcz = 0

pacitor-coupled load.

Chapter6

AC Analysis of BUT Circuits

20 Ip= ~

0

2

4

6

8

10

12

*

OpA

k=

14C6 18 20

(V)

——-,—-Y

Vor

Figure 6-8

AVcpg

The ac load line for a transistor circuit is drawn through the Q-point.

Draw the dc load line through points A and B.

_ Veo X Rp __ 20V X 82kO R,

+ Ro

18kQ

+ 8.2kO

=63V Vi= Vp— Vez= 6.3V—-0.7V =5.6V ed = Ve _ 5.6V Re 27k = 2.07mA Mark the Q-point on the dc load line at Ic = 2.07 mA Drawing the ac load line: When there is no external Ri, Ryd = Re = 2.2 kO When Ic changes by Alc = 2.07 mA, AVcg = Alc X Rc = 2.07 mA X 2.2kO =455V Plot point C at Alc = 2.07 mA and AVcg = 4.55 V from the Q-point. Draw the ac load line through points C and Q.

245

246

Electronic Devices and Circuits

The Output Voltage Swing In Section 5-1 it was explained that the maximum symmetrical output voltage swing (+Vo(max)) from a common-emitter circuit depends upon the Q-point position on the dc load line. In the case of a circuit with a bypassed emitter resistor or a capacitor-coupled load, the maximum symmetrical output swing depends upon the Q-point position on the ac load line. For the ac load line shown in Fig. 6-8, V

o(max)

x

+4.5

V

Practice Problem 6-2.1. Draw the new ac load line for the transistor circuit in Ex. 6-2 when a 5.6 kQ, external load is capacitor-coupled to the circuit output. Determine the new maximum possible symmetrical output voltage swing.

6-3 TRANSISTOR MODELS AND PARAMETERS T-Equivalent Circuit Because

a transistor consists of two pn-junctions with a common

centre

block, it should be possible to use two pn-junction ac equivalent circuits as the transistor model. Figure 6-9 shows the ac equivalent circuit for a transistor connected in common-base configuration. Resistor r. represents the BE junction resistance, r- represents the CB junction resistance, and 1, represents

the

resistance

of the

base

region

which

is common

to both

junctions. Junction capacitances Cgp and Cpe are also included. If the transistor equivalent

circuit is simply

left as a combination

of

resistances and capacitances, it could not account for the fact that most of the emitter current flows out of the collector terminal as collector current. To

5

Input

i

Cc

T ; |Ib

utput tp

(a) CB connected transistor

Input

1%

Cac

Output

{1,

(b) CB equivalent circuit

Figure 6-9 The T-equivalent circuit, or r-parameter equivalent circuit, for a transistor is essentially a combination of two pn-junction equivalent circuits.

Chapter6

= AC Analysis of BUT Circuits

247

represent this, a current generator is included in parallel with r, and Cgc. The

current generator is given the value ale, where a = I,/Ie. The complete circuit is known as the T-equivalent circuit, or the r-parameter

equivalent circuit. The equivalent circuit can be rearranged in common-emitter or common-collector configuration. The currents in Fig. 6-9 are designated I, I., and J, (instead of Ip, Ic, and Ig) to indicate that they are ac quantities rather than dc. The circuit parameters

To To, Te, aNd @ are also ac quantities. r-Parameters

In Fig. 6-9, r. represents the ac resistance of the forward-biased BE junction, it has a low resistance value (typically 25 (). The resistance of the reverse-

biased CB junction (r,) is high (typically 100 kN to 1 MQ). The base region resistance (r,) depends upon the doping density of the base material. Usu-

ally, rp ranges from 100 © to 300 2. Cpe is the capacitance of a forward-biased pn-junction, and Cgc is that of a reverse-biased junction (see Section 2-6). At medium and low frequencies the

junction capacitances may be neglected. Instead of the current generator (a/.) in parallel with r,, a voltage generator (al.r,) may be used in series with 7.

wo

yn te

Input

a

oc 1,

th 2

Output

Bo—

OB

Bo—

(a) Using current source Figure 6-10

(b) Using voltage source

Transistor low-frequency r-parameter ac equivalent circuits.

Two transistor r-parameter models are shown in Fig. 6-10, one using a current generator and the other using a voltage generator.

Determination of Fr. Because fz is the ac resistance of the BJT forward-biased base-emitter junction, it can be determined from a plot of Ig versus Vz. As illustrated in Fig. 6-11, ig

re This is similar to the determination forward-biased

diode

AVE

dele

(6-1)

of the dynamic resistance (rg) for a

(see Section 2-2). As in the case of a diode,

the ac

248

Electronic Devices and Circuits

(mA)

resistance for the transistor BE junction can be

10+—_—__——

fo

calculated in terms of the current crossing the

gt] , —AVe e

Ig

junction:

Alp

4 nn aon 4 2

0

nt

05

Vor

t—++

0.7 08

26anV

(6-2)

Tp ‘

!

Vee

06

r', =

Ip -

|

04

py:

|

'

.

;

5

5

Like rg for a diode, ri. does not include the resisa ° tance of the device semiconductor material. boa. Consequently, rz is slightly smaller than the ac-

(V)

tual measured value of r. for a given transistor.

Figure 6-11

Determination of = Equation 6-2 applies only to transistors at a

r. from the transistor base-

J

Soe

i!

emitter junction forward

temperature of 25°C. For determination of 1, at

characteristic.

higher or lower temperatures, the equation must be modified.

1 — 26mV 7 +

j

Ip

|

9

298°C

:

h-Parameters It has been shown that transistor circuits can be represented by an /-parameter or T-equivalent circuit. In circuits involving more than a single transistor, analysis by r-parameters can be virtually impossible. The hybrid parameters (or h-parameters) are much more convenient for circuit analysis. These are

used only for ac circuit analysis, although dc current gain factors are also expressed as /-parameters. Transistor h-parameter models

simplify

transistor

circuit analysis by separating the input and output stages of a circuit to be an-

alyzed. In Fig. 6-12, a common-emitter h-parameter equivalent circuit is compared with a common-emitter r-parameter circuit. In each case an external collector

resistor (Rc) is included, as well as a signal source voltage (v,) and source al,

=

Bl,

(a) CE r-parameter equivalent circuit Figure 6-12 circuits.

(b) CE h-parameter equivalent circuit

Comparison of common-emitter r-parameter and h-parameter equivalent

Chapter6

= AC Analysis of BUT Circuits

249

resistance (r,). Note that the output current generator in the r-parameter circuit has a value of al., which equals Bl. The input to the h-parameter circuit is represented as an input resistance (hie) in series with a voltage source (hyeUce): Looking at the r-parameter circuit, it is seen that a change in output current I, causes a voltage variation across

fe. This means that a voltage is fed back from the output to the input. In the

h-parameter circuit, this feedback voltage is represented as the portion hye of the output voltage v¢. The parameter My. is appropriately termed the reverse voltage transfer ratio. The output of the h-parameter circuit is represented as an output resistance (1/hoe) in parallel with a current generator (hjelp), where I is the (input) base current. So, hgelp is produced by the input current [,, and it divides between the device output resistance 1/ho- and the collector resistor Rc. I, is the

current passed to Rc. This compares with the r-parameter equivalent circuit, where some of the generator current (6],) flows through r,. The current generator parameter (hfe) is termed the forward transfer current ratio. The output conductance is hoe, so that 1/ho. is a resistance.

r,, Equivalent Circuit An approximate h-parameter model for a transistor CE circuit is shown in Fig. 6-13a. In this case, the feedback generator (yeUce in Fig. 6-12b) is omitted. The effect of hye is normally so small that it can be neglected for most

practical purposes. The approximate h-parameter circuit is reproduced in Fig. 6-13b with the components labelled as r-parameters: 1, = Nie, Bly = hjelp, and r- = 1/Noe-. This

circuit, known

as a hybrid-m model,

is sometimes

used

instead

of the

h-parameter circuit.

OE

(a) CE h-parameter transistor model Figure 6-13

(b) CE r,, transistor model

Transistor h-parameter and r, equivalent circuits.

Definition of h-Parameters The e in the subscript of hie identifies the parameter

as a common-emitter

quantity, and the i signifies that it is an input resistance. Common-base and common-collector input resistances are designated hj, and h;,, respectively. As an ac input resistance, hie can be defined as the ac input voltage di-

vided by the ac input current.

250

Electronic Devices and Circuits

Vb Rie

a

I,

This is usually stated as V hie aa

a

Tb

(6-4)

|Veg

This means that the collector-emitter voltage

(iA)

(Vcg) must remain constant when hij. is measured. :

.

a

‘

The input resistance can also be defined in terms of changes in dc levels: AY

he =—

Alp

oot

(6-5)

lve

80 +

I

=: AV pe

Nie= TF

60 + ” 40 4

204

|

0

(V)

Equation 6-5 can be used for determining hie VBE

from the transistor common-emitter input characteristics. As illustrated in Fig. 6-14, AVpg

Figure 6-14

and Alp are measured at one point on the char-

teristics,

.

Derivation of hj.

from the CE input charac-

acteristics, and hie is calculated.

The reverse transfer ratio /y. can also be defined in terms of ac quantities, or as the ratio of dc current changes from a plot of Vgg versus Vcr. In both cases, the input current (Ig) must be held constant.

Nee

_ AVpe AV cg

(6-6) Tz

The forward current transfer ratio hye can similarly be defined in terms of

ac quantities, or as the ratio of dc current changes. In both cases, the output voltage (Vcr) must be held constant.

I he= 7

bl

or

AI he = —— Alp

Vex

|vcp

(6-7)

(6-8)

Chapter6

Von = 45V an)

1 \

Me~

rs

(uA) + 80

8

the CE current gain characteristics. Figure 6-15

7

shows the measurement of Alc and Alg at one point on the characteristics for the hg. calcula-

6

tion.

4

The output conductance, hoe, is the ratio of ac collector current to ac collector-emitter voltage, and its value can be determined from the com-

60

40

Ig

\

mon-emitter output characteristics (see Fig. 6-16). 2

Alc ||\

P| Me = AT

i

= 20

254

Equation 6-8 can be used to determine hy. from

+S —t4 \

AC Analysis of BUT Circuits

QO

hoe ==

0

ce

( 6-9)

{Ip

Ip Figure 6-15

Derivation of hr.

from the CE current gain

5

characteristics.

0

=2.

=-4

[=6

-6 Ve:

-I0

Pewee

r

ate

oe ~ AV ck

-12

—-45V

-—i4

|i,

(6-10)

(V) Figure 6-16

Derivation of ho. from

the CE output characteristics.

Example 6-3 Determine hye and Moe for Vcg = 4.5 V and Ig = 40 wA from the transistor

characteristics in Figs 6-15 and 6-16. Solution From the current gain characteristics at Vcg = 4.5 V and Ip = 40 pA, Alc =4mA

and Algp® 30pA

252

Electronic Devices and Circuits

Al he. = Alc

Eq. 6-8: *

fe

4mA

Alp

30 pA

= 133 From the output characteristics at Vcg = 4.5 V and Ip = 40 pA, Alc

Eq. 69:

= 400

pA

and

fy SS es AV cE

AVcE

=6V

6V

= 33.3 wS (micro Siemens)

1 Vi. == [Moe 33.3 1S = 30k

Common-Base and Common-Collector h-Parameters The common-base and common-collector /-parameters are defined similarly to common-emitter h-parameters. They may also be derived from the CB and CC characteristics. Common-base parameters are identified as hiv, ha, etc., and common-collector parameters are designated hic, hj, and so on. Com-

mon-emitter, common-base, and common-collector h-parameter equivalent

circuits are further investigated in Sections 6-4 to 6-8. Parameter Relationships Device manufacturers do not list the values of all parameters on transistor data sheets. Usually, only the CE h-parameters are stated. However, CB and CC h-parameters can be determined from the CE h-parameters. 7-Parameters

can also be calculated from the CE /-parameters. Table 6-1 shows the parameter relationships. Table 6-1

Conversion from CE h-parameters to CB and CC h-parameters and to r-parameters

CE to CB

h-parameters x

hie —

hw

ro)

1

h

=

a

oe

4s Nie

Nfe

1 + Ige

CE h-parameters

h-parameters

to r-parameters

h,.

hin ~ TF he Nie Noe

CE to CC

—h re

= h;

cos

h,=1Tc

Nee

=

]

Ne |e ee

at

+

1 + Ni

h re

Cc

=

hfe

i=

TL

1 + hg Noe

Nie

£ digs

h hop

~

ve

Nise

me

Rese

Yb

=

hie

1 + hye

=

=

7!

Ne(1 + aMfe ) Mre(1 Noe

tr B

= —

hie hte

Chapter6

= AC Analysis of BUT Circuits

253

Example 6-4 Calculate hfc, hop, and a from the parameters determined in Ex. 6-3.

Solution

From Table 6-1:

hee = 1 + he = 1 + 133 = 134 her ee

Drees OU 1+hp

33.3 S 1+ 133

= 249 nS eae Nee

_

l+k.

133

1+ 136

= 0.993

Example 6-5 A transistor in a circuit has its current levels measured as follows: Ip = 20 pA and Ic = 1 mA. Estimate the CE input resistance. Determine r, and . Solution , _26mV fe = Th

Eq. 6-2:

_ 26mV imA

= 260,

hig 8

Ic

imA

Ip

20pA

= 50

hie = (1 + hye) re = (1 + 50) X 26 0 = 1.33 kO Va = hie

=

133 kO0

B = I = 50

Practice Problems 6-3.1 6-3.2 6-3.3

Determine hy. and Moe at Vcr = 6 and Ip = 20 pA from the commonemitter output and current gain characteristics in Fig. 4-30. Calculate a and r, from the h-parameter values determined in Problem 6-3.1. Calculate h;. for a transistor at a temperature of 50°C when the emitter current is 1.3 mA and hj. = 80.

254

Electronic Devices and Circuits

6-4 COMMON-EMITTER CIRCUIT ANALYSIS Common-Emitter Circuit

Consider the transistor amplifier circuit shown in Fig. 6-17. When the capacitors are regarded as ac short circuits, it is seen that the circuit input terminals are the transistor base and emitter, and the output terminals are the collector and the emitter.

So, the emitter terminal is common to both input and output, and the circuit termed common-emitter (CE).

configuration

is

The current and voltage waveforms for the CE circuit in Fig. 6-17 are illustrated in Fig. 6-18. It is seen that there is a 180° phase shift between the input and output waveforms. This can be understood by considering the effect of a positive-going input signal. When vg increases in a Figure 6-17 Transistor common-emitter amplifier with coupling and bypass capacitors.

f5*

input

positive direction, it increases the transistor base-emitter voltage (Vgz). The increase in Vp;

raises the level of Ic, thereby increasing the voltage drop across Rc, and thus reducing the level

of the collector voltage (Vc). The changing level of Vc is capacitor-coupled to the circuit output to produce the ac output voltage (v,). As uv, increases in a positive direction, 0, goes in a negative direction, as illustrated. Similarly, when »,

changes in a negative direction, the resullant decrease in Vpg reduces the Ic level, thereby

re-

ducing Vec and producing a positive-going oulput. The circuit in Fig. 6-17 has an input impedance

(Z\), and an output impedance (Z,). These can cause voltage division of the circuit input and output

voltages, as illustrated

in Fig. 6-19. So,

for most transistor circuits, Z; and Z, are important parameters.

The circuit voltage

amplifica-

tion (A,), or voltage gain, depends on the transistor parameters and on resistors Rc and R;.

h-Parameter Equivalent Circuit Figure 6-18

Voltage and cur-

rent waveforms in a common-emitter amplifier.

The first step in ac analysis of a transistor circuil is to draw the ac equivalent circuit, by substituting short-circuits in place of the power

Chapter6G

=

hei

255

supply and capacitors. When this is done for the circuit in Fig. 6-17, it gives the ac equivalent circuit shown in Fig. 6-20a (reproduced from Fig.

VU,X Z;

@

AC Analysis of BUT Circuits

Zi

6-6b).

The

h-parameter

circuit is now

drawn

simply by replacing the transistor in the ac equivalent circuit with its h-parameter

model

(from Fig. 6-12b). This gives the CE h-parameter equivalent circuit in Fig. 6-20b. Note that the feedback voltage generator (h;eVc) in Fig. 6-12b

is omitted in Fig. 6-20b. As discussed, the effect of hyed, in a CE circuit is unimportant for most practical purposes. The current directions and voltage polarities in Fig. 6-20b are those that occur when the in-

(b) Division of output voltage Figure 6-19 Circuit input and output voltages are divided

stantaneous level of the input voltage is moving

in a positive direction.

by the effects of Z; and Z.

(a) ac equivalent circuit for CE transistor circuit

Transistor h-parameter equivalent circuit

I

i.e

B

Ry

©

I

Nie Zp

I

wets

wilt Re

ES

Hise

=

holy

E

Z.

RL |

© (b) h-parameter equivalent circuit for CB circuit with unbypassed base

Figure 6-37 AC equivalent circuit and h-parameter circuit for a CB amplifier with an unbypassed base resistor.

272

Electronic Devices and Circuits

(Fig. 6-37b). The presence of the unbypassed base resistors can substantially affect the transistor input impedance and the circuit voltage gain. Analysis

of the h-parameter circuit shows that Ze = hip + Rp(1

Abe

and

— Np)

(6-33)

hep(Re|| Rx) ee hy + Rp

(6-34)

— App)

Comparing Eq. 6-33 to Eq. 6-28 (Ze with C; present), it is seen that Rp(1 — hp) is added to hy to give Ze without C; present. Equation 6-34 is similar to Eq. 6-32 (A, with C; present), except that Rp(1 — /ig) is again

added to hj, to give the CB circuit voltage gain without C; (Eq. 6-34). Typically hg = 0.99 and (1 — hg) = 0.01. Summary of CB Circuit Performance With the base bypassed to ground: Device input impedance

Ze = hip

Circuit input impedance

Z, = Ze||Re

.

z

1

Device output impedance

Leg= >

Circuit output impedance

Zo * Re

Circuit voltage gain

Nob

he(Rc||R

Ay =mala ib

With the base unbypassed:

Device input impedance

cpt eaten

ircuit voltage gain

Ze = hin + Rp(1 — hp) OS

_flRellR) Hy

Rall

= kad

impedance, ACB circuit has good voltage gain and relatively high output imlike a CE circuit. But unlike a CE circuit, a CB circuit has a very low input e amplifier applica pedance, and this makes it unsuitable for most voltag

The tran tions. It is normally employed only as a high-frequency amplifier.

be bypassed sistor base terminal in a CB circuit should always

to ground,

voltage am When this is not done, the input impedance is increased and the plification is substantially reduced.

Chapter6

AC Analysis of BUT Circuits

273

Example 6-10 The transistor in the CB circuit in Fig. 6-38 has the following parameters:

hie= 2.1 KO and hfe= 75. Caleulate the circuit input and output impedances and voltage gain.

- Solution _ 2.1k0

hie

hy =

From Table 6-1,

7s

L

1 + hye

= 27.60, 75

Nye

hy =

and

1+75

Ll+hp

= 0.987

Vee

12V

fo——— C.

R,

"s

82 kO

Figure 6-38

CB circuit for Ex. 6-10.

Z; = hp||Re = 27-6 0||4.7 ko = 2740,

Zo = (1/hop)||Re* Re

Eq. 6-31:

= 3.9kO A, =

Eq. 6-32:

(Rc||Ri)

hi

0.987 (3.9 kQ ||82 kQ)

a eee

= 133 Example 6-11

circuit in Ex. 6-10 Calculate the input impedance and voltage gain for the CB when capacitor C; is disconnected. Solution

Eq. 6-33:

Ze = hip+ Rp(1 — hw)= 27-6 0 + (68 kQ||56 kQ)(1 — 0.987)

274

Electronic Devices and Circuits

Eq. 6-29:

Eg. 634

= 426.80 Zi = Ze||Re = 426.8 04.7 kO = 3910 he(Rel|R

A, =m hiy +

ORell Ry) _ Rg(1 — hp)

987

27.6 D

—_ + (68

(3.9 kQ||82 ko

Me

kO||56 kQ)(1 — 0.987)

= 8.6 Practice Problems 6-7.1

Calculate Z;, Z,, and A, for a CB circuit (as in Fig. 6-38) with the follow-

ing component values and parameters:

Rj =56

kO, R) = 39 kQ,

Re = 5.6 kO, Rg = 3.3.kO, Ry = 47 kO, hie = 1 kO, and he = 100.

6-7.2 Determine Z; and A, for the circuit in Problem 6-7.1 when capacitor C, is disconnected.

6-8

COMPARISON

OF CE, CC, AND CB CIRCUITS

Table 6-2 compares Zi, Zo, and Ay for CE, CC, and CB circuits. As already dis-

cussed, the CE circuit has high voltage gain, medium input impedance, high output impedance, and a 180° phase shift from input to output. The CC circuit has high input impedance, low output impedance, a voltage gain of 1,

and no phase shift. The CB circuit offers low input impedance, high output impedance, high voltage gain, and no phase shift. Table 6-2.

Comparison of Common-emitter, Common-collector, and Commonbase Circuits

Circuit Configuration

Zo

Ay

Phase Shift

eC

medium high

® Re low

high ~1

180° 0

CB

low

= Re

high

0

CE

Zi

Device manufacturers normally only list the CE h-parameters on a transis-

tor data sheet. Although these can be converted to CC and CB parameters, it is convenient to use CE parameters for all three types of circuits. Table 6-3

gives the circuit impedance equations in terms of CE h-parameters. In the case of input and output impedances, it is helpful to think in terms of the terminal being looked into.

Chapter 6

Table 6-3

275

Common-emitter, Common-collector, and Common-base Circuit

Equations

Using CE h-parameters

“Circuit Configuration CE

CE

AC Analysis of BUT Circuits

with

Zz

iy iy Wigs

hie

—=

17 Noe

—

1 / Nee

hie + Rg(1

+ hfe)

Zz.

unbypassed Rg

CC

Nieie +

CB

hie (Re||Rx)(1

ae

hte)

_

hie 1

CB with

unbypassed Rp

+ Rp

aNye

1+

a

+

= 1 + he

Nee

Nee

hie + Rg

1 + hie

1 + hfe

Hoe

Impedance at the Transistor Base

2 > = hig + Rg(1 + Age)

= hi, (with Cg)

ce,

Consideration of each type of circuit shows that the input impedance (Z;) depends upon which transistor terminal is involved. In both the CE and CC circuits, the input signal is applied to

Lt

the transistor base terminal. So, Z; is the imped-

T Ce ane

ance ‘looking into’ the base. Figure 6-39 shows that, for a CE circuit with an unbypassed emit-

= Figure 6-39

ter resistor, Zp = Nie + Re(1 + hye)

Impedance at

the transistor base terminal.

When Rg is bypassed, the Rg(1 + hye) portion can be treated as zero, so that Ly = hie

The CC equations for Z; are almost identical to the CE equations, except that they use hj. and hj, which are essentially equal to hie and hfe (see Table 6-3). A rough approximation for the base input impedance of any transistor circuit

with an unbypassed emitter resistor is Zp © Mye(impedance in series with the emitter) The circuit input impedance for both CE and CC configurations is Z, in parallel with the bias resistors: A= Zp||Ral|Re

Impedance at the Transistor Emitter The transistor emitter is the output terminal for a CC circuit and the input terminal for a CB circuit. So, the device impedance in both cases is the

276

Electronic Devices and Circuits

impedance ‘looking into’ the transistor emitter terminal (Ze). Although the Z, equations for the two circuits look different, they can be shown to give exactly the same result in similar situations. For a CC circuit or a CB circuit with an unbypassed base (using CE parameters),

z.

= hie + Rg ©

1+

Nfe

where Rg is the impedance when ‘looking back’

from the transistor base. As shown in Fig. 6-40, Rg includes the signal source resistance (/s) fora

CC circuit. A CB circuit normally has its base bypassed as shown, so that the impedance at the emitter is hie

fe

Tt the

For all circuit arrangements, the impedance at the transistor emitter terminal is With CC

With CB

Figure 6-40

Impedance in series with the base

7

circuit

circuit

Impedance at the

e

transistor emitter terminal.

1+h

fe

Vig

Impedance at the Transistor Collector The output for CE and CB circuits is taken from the transistor collector terminal. So, the imped-

Re

ance ‘looking into’ the collector is the device output impedance. This is normally a very large quantity at low and medium signal frequencies.

As illustrated in Fig. 6-41, the circuit output impedance at the collector is essentially Zo™ Re

Figure 6-41

Impedance at the

transistor collector terminal.

Voltage gain In the case of a circuit with an unbypassed emitter resistor, the ac voltage al the emitter follows the ac input at the transistor base. So, a CC circuit (an

emitter follower) has a voltage gain of 1. With both CE and CB circuits, the ac input (vj) is developed across the

base-emitter junction, and the ac output (v9) is produced at the transistor col-

lector terminal (see Fig. 6-42). Thus (as discussed in Section 6-7), the magnitude of the voltage gain is the same for CB and CE circuits with similar component values and transistor parameters. The CE voltage gain equation can

be used for the CB circuit, with the omission of the minus sign that indicates

Chapter6

AC Analysis of BUT Circuits

277

CE phase inversion. Although the voltage gains are equal for similar CB and CE circuits, the low input impedance of the CB circuit can substantially attenuate the signal voltage, and result in a low amplitude output. This is demon-

strated in Ex. 6-12.

Ap —

~

Mele

|

R

L)

1e

— Figure 6-42

CE and CB voltage gain.

Figure 6-43

Circuit for Ex. 6-12.

Example 6-12 A 50 mV signal with a 600 (© source resistance is applied to the circuit in Fig. 6-43. Calculate v, for (a) CE circuit operation with v, at the transistor

base and Rx bypassed, and (b) CB circuit operation with v, at the emitter and the base resistors bypassed. The transistor parameters are je = 1.5 kQ and Ne =

100.

Solution

(a) CE circuit

— Ige(Re||Rt) _ 100 (5.6 kO||33 kO) Vv

—

= Zp = Z; = =

Ne

1.5 ko

319 hie = 1kO Zp||Ri||R2 = 1 kQ|]100 kQ|]47 ka 970.0,

_ 0.x Zi _ 50mvV x 970 0 % + Z; 6000 + 9700 = 30.9 mV

Uy = Av X 0; = 319 X 30.9 mV =99V

278

Electronic Devices and Circuits

(b) CB circuit

Ru) _ 319 Ay = hre(Rell hie

From Table 6-3,

Z, = —“#e_ = 15k 1+ hy = 14.850

1+ 100

Zi = Z.||Re = 14.85 0||5.6 kO = 14.810

5 ota

2, _ Kim k Lal @

r,+Z, =12mvV

6009 + 14.810

Up = AyX 4 = 319 X 1.2mV = 383 mV

Practice Problems 6-8.1 Using the appropriate CE equations from Table 6-3, calculate Z;, Z,, and A, for a CB circuit (as in Fig. 6-38) with the following component values and parameters: Ri = 56 kQ, Rp = 39 kQ, Rc = 5.6 kQ, Re = 3.3 kQ, Ry = 47 kO, hie = 1 kQ, and hy. = 100. 6-8.2

Determine 2, for the circuit in Problem 6-8.1 when a 30 mV

ac signal

with r, = 400 2 is capacitor-coupled to the transitor emitter.

6-9 EBERS-MOLL BJT MODEL Figure 6-44a shows the Ebers-Moll transistor model which is used in some computer programs, and also used as a large-signal model. The npn BJT model illustrated consists of two diodes with parallel-connected dependent current generators. Diodes Dg and Dc represent the base-emitter and basecollector junctions, respectively, and each generator produces a current that

is dependent on the current in the opposite diode. I,}=apIpg

and

I2=apglpc

The diode currents (Ipc and Ipg) can be calculated from the Shockley equation (Eq. 1-13). When

the BJT is biased for normal operation, Ipc = Ico, the

junction reverse saturation current, and Ip, is the current flowing across 4 forward-biased junction. The forward current gain factor ag can be thought

of as the relationship between Ic and Ig, and this is typically 0.99, making the collector current almost equal to the emitter current (see Section 4-2). The

Chapter 6

AC Analysis of BUT Circuits

279

reverse current gain factor ag determines the relationship between emitter and collector currents when the voltage polarities are reversed, so that the collector behaves as an emitter and the emitter is operating as a collector. Because the BJT is fabricated with an emitter-base junction area much smaller than the area of the collector-base junction, the emitter performs poorly as a

collector. Consequently, ag is typically 0.5. For a transistor biased for normal operation, i

(Ipc = Ico) SR

x

are

315

Se

Characteristic

Symbol |

Small-Signal Characteristics

_

ae

Current-gain-bandwidth product

fr

(Ic = 10 mA de, Veg = 20 V, f = 100 MHz)

Min

Max

i

Unit

, MHz

2N3903 2N3904

250 300

—_ _—

Figure 8-6 Specification of transistor cutoff frequency on the 2N3903 data sheet.

and 2N3904

an input capacitance (Cibo), which corresponds

Vee

to Cpe. It should be noted that in both cases, the

capacitance values are specified for reversebiased junctions with zero current levels. Cop. varies when Vcg is altered; however, the

changes are usually a maximum of approximately +3 pF. Cjp. changes substantially from the specified capacitance when the baseemitter junction is forward biased (as it always is for linear BJT operation).

Characteristic

Symbol |

Output capacitance (Veg

=5 Vdc,

Ik

= 0,

f=

Figure 8-7

All transistors

have junction capacitances.

Min

Max

Unit

Cas

_

4.0

pF

Cre

=

8.0

pF

1.0 MHz)

Input capacitance (Vpp = 0.5 Vde, Ic = 0, f = 1.0 MHz)

Figure 8-8

Junction capacitance specifications for 2N3903 and 2N3904 transistors.

When an emitter current flows across the BE junction, there is a diffusion

capacitance (see Section 2-6) at the junction. This is directly proportional to the current level. It can be shown that

_ 61g

er

(8-8)

316

Electronic Devices and Circuits

Miller Effect Figure 8-9 shows an input signal (+AVj) applied to the base of a transistor connected in CE configuration. If the circuit voltage amplification is —Ay, then the collector voltage change is AV,

=

—Ale

x

AV;

Meg Re

Ravi ce

(a) AV, and —A,AV;, change Vc Figure 8-9

(b) Cin = Cue + (1 + Ag)Cic

Because of the Miller effect, the input capacitance for a

common-emitter amplifier is Cin = Cpe + (1 + Av)Core-

Note that, because of the phase reversal between input and output, the collector voltage is reduced by (A, AV;) when the base voltage is increased by AV;. The increase in Vg and decrease in V¢ result in a total collector-base volt-

age reduction of AVcp

=

AV; + A,AV;

This voltage change appears across the collector-base capacitance. From the equation Q = C X AV, it is found that the charge supplied to the input of the circuit is Q = Cre X AV{(1 + Aj) or

Q=

(1 + Ap)Cre X AV;

appears to be Therefore, ‘looking into’ the base, the collector-base capacitance

(1 + A,)Chc. So the capacitance is amplified by a factor of (1 + A,). This is

known as the Miller effect. lel The total input capacitance (Cin) to the transistor is (1 + Ay)C). in paral with the base-emitter capacitance (Cpe):

Cn. = Che. FP

AV ebe

(8-9)

It should be noted that the Miller effect occurs only with amplifiers that have a 180° phase shift between input and output (an inverting amplifier). Consequently, it occurs with CE circuits but not with CB and emitter-follower circuits.

Chapter 8

BUT Specifications and Performance

317

Example 8-4 The transistor in the circuit in Fig. 8-10 has Ic = 1 mA, hye = 50, hie = 1.3 kQ, fr = 250 MHz, and C,, = 5 pF. Calculate the input capacitance'when the circuit is operated as a CE amplifier with Rg bypassed.

Figure 8-10 The upper cutoff frequency for a transistor circuit can be limited by the input capacitance.

Solution From Eq. 6-12,

re

_ 50 x (8.2 kQ||100 kQ)

hge(Rc||Rz) hie.

-

1.3kO

= 291

ee:

s

(

6.11

be

fp

Be pups

6.1 X 1mA

«250 MHz

= 24.4 pF Cin = Che + (1 + Av)Cprc = 24.4 pF + [(1 + 291) X 5 pF]

Eq. 8-9:

= 1.48 nF

Practice Problem

8-3.1 A CE circuit with a voltage gain of 100 has Ic = 0.75 mA, Cyc = 3 pF, and fr = 300 MHz. Calculate Cin when a 45 pF capacitor is connected across the collector-base terminals.

8-4 BJT CIRCUIT FREQUENCY RESPONSE Coupling and Bypass Capacitor Effects Consider the typical transistor amplifier frequency response illustrated in Fig. 8-5, As explained in Section 8-2, the amplifier voltage gain is constant

over a middle range of signal frequencies, and it falls at the low and high ends of the frequency range.

318

Electronic Devices and Circuits

The gain fall-off at low signal frequencies is due to the effect of coupling and bypass capacitors. Recall that the reactance of a capacitor is X¢ = 1/(2nfC). At medium and high frequencies, the factor f makes Xc very small, so that all coupling and bypass capacitors behave as ac short circuits. At low frequencies, Xc is large enough to divide the voltages across the capacitors and series resistances (see Fig. 8-11). As the signal frequency gets lower, the capacitive reactance increases, more of the signal is lost across the capacitors, and the circuit gain continues to fall. Coupling and bypass capacitors are further investigated in Section 12-1.

Signal lost across X¢,

=

Signal lost across Xc

Figure 8-11 The low-frequency fall-off in voltage gain in a transistor amplifier is due to signal loss across coupling and bypass capacitors.

Input-Capacitance Effect on CE and CB Circuits The input capacitance of an amplifier (discussed in Section 8-3) reduces the circuit gain by 3 dB

when the capacitive impedance equals the resistance in parallel with the input (see Fig. 8-12). That is when

Xq = Zillts Thus

all circuits

(8-10)

have

an

input-capacitance-

Beco

limited upper cutoff frequency (fri). As already explained, the input capacitance of a CE circuit is amplified by the Miller effect, but Miller effect

does

not

occur

in a CB

circuit.

Figure 8-12 ta

The input resis-

(Z;

i | 7 ae : : lees parallel with the circuit input capacitance (Ci,).

Consequently, a CB circuit operates to a much higher signal frequency than a similar CE circuit.

Chapter 8

BUT Specifications and Performance

319

Example 8-5 Calculate the input-capacitance-limited upper cutoff frequency for the circuit

in Fig. 8-13 (reproduced from Fig. 8-10): (a) when the circuit is used in CE

configuration with Rg bypassed, and (b) when operating as a CB circuit with the base bypassed to ground. As in Ex. 8-4, Che =5 pF and Cre = 24.4 pF.

Also, hfe = 50, hie = 1.3 kO, hi, = 24.5 0 (= 1’), and rs = 600 2.

Figure 8-13

Circuit that may be connected to

function in either CE or CB configuration.

Solution

(a) Common emitter circuit:

Z; = Ri||Rol|hie = 100 kQ||47 kO||1.3 kO = 1.20 kD

rs||Z; = 600 O||1.25 kO = 405

From Ex. 8-4,

Cin = 1.48nF

(due to Miller effect) 1

yen

fatiy = mee

~ On X 1.48 nF X 405 0

= 266 kHz

(b) Common base circuit:

Z, = Re||hp = 4.7 kO||24.5 0 = 2440 r,||Z; = 600 0||24.4 0

= 23.40 Cin = Che + Coc = 24.4 pF +5 pF = 29.4 pF

320

Electronic Devices and Circ uits

From Eq.q. 8-10,

1 F240)i) = QmCin(relZ;)

1 = 20 X 29.4 pF Xx 23.4.0

= 231 MHz Input-Capacitance Effects on Emitter Follower

When a transistor is used as an emitter follower, its BE junction voltage is not significantly altered by the ac input signal, because virtually all of 4; appears at the emitter as vp (see Fig. 8-14). Since there is no Miller effect to amplify C,., the input capacitance is Cp9||Copo. So the input-capacitancelimited cutoff frequency for an emitter follower is very much higher than that for a CE circuit.

See

Stray Capacitance Figure 8-15 illustrates the fact that stray capacitances (C,, and C,,) exist in all transistor circuits.

This is capacitance between connecting wires and ground, and normally it is extremely small. The stray capacitance at the device base is usu-

ally much smaller than the input capacitance at

Figure 6-14. ‘Thera leno Miller effect input-capacitance amplification with an

emitter follower circuit.

the base, so that it can usually be neglected. When this is not the case, the stray capacitance must be included with the input capacitance for CE circuit cutoff-frequency calculations.

Figure 8-15

Stray capacitance can cause a

reduction in the transistor amplifier gain at high frequencies.

At the circuit output, the impedance of the stray capacitance (C,,) is very

high at low and medium signal frequencies, so that it has no effect on the gain. At high frequencies, the stray capacitive impedance becomes small enough to shunt away some of the output current, and thus it reduces the circuit gain. In Fig. 8-15, it can be seen that the circuit ac load consists of the output stray capacitance (Co) in parallel with Rc and R,.. Rewriting the voltage gain equation for CE and CB circuits gives

Chapter 8 —_ BUT Specifications and Performance

|Ayl =

321

hge(Re | Ry | X cso) Hie

If the transistor cutoff frequency has not caused the gain to fall off at a lower

frequency, then the gain falls by 3 dB when X¢so = Rc||Rz. This is an outputcapacitance-limited cutofffrequency (f2(0)). If the voltage gain falls by 3 dB at fue because of the transistor, and by 3 dB at the same frequency because of the stray capacitance, then the gain is down

by 6 dB (see point A

in Fig. 8-16). Consequently, the amplifier upper cutoff

frequency is lower than fe. This is illustrated by point B in Fig. 8-16.

As discussed, there is an additional 3 dB attenuation when Xcso = Re | Ry. If

Xcso = 2(Re l|Rx) at fae, the additional attenuation can be shown to be 1 dB. With Xcso = 5(Re|| Rr) at foe, there is only a 0.2 dB additional attenuation (point C). In some circumstances it is desirable to set the upper cutoff frequency of a

circuit well below the transistor cutoff frequency (see point D in Fig. 8-16). This is done simply by connecting a capacitor from the collector terminal to ground exactly as C,, is shown in Fig. 8-15. The capacitance value is calcu-

lated at the desired cutoff frequency to give

Xo =Re l Rp

(8-11)

oO oie

V,

=f

NG

a

G

°

—3 dB

\

—5

“6

\

fo

—7

fo.

+

fy selected

Soe

by an external capacitor by

Cas

or

“are

f,2when ».

=

(Re

at

fore

I Ry)

upper cutFigure 8-16 The BJT cutoff frequency (fr) determines the output the of off frequency of a circuit so long as the impedance

stray capacitance (C.0) is much larger than Re||RL. When Xeso is

much smaller than Re||R., the circuit upper cutoff frequency is determined by Cso-

322

Electronic Devices and Circuits

Example 8-6

A transistor with fr = 50 MHz and he = 50 is employed in the CE amplifier

in Fig. 8-17. Determine the upper 3 dB frequency for the device. Calculate the capacitance required for Cy to give a 60 kHz upper cutoff frequency. Assume that Ri >> Rc.

Figure 8-17

Solution From Eq. 8-7,

From Eq. 8-11,

;

f

T

fae = Nee ~

50 MH 50

Circuit for Ex. 8-6.

7

= 1 MHz 1

4 = OafaeRe 2X

1

X 60kHz x 10KO

= 265 pF

Practice Problems 8-4.1

In a CE amplifier circuit, Rc = 5.6 kO and Ry = 56 k). The transistor

used has hye = 60, hie = 1.5 kD, Coe = 192 pF, source resistance is 1 kQ,, and the voltage R, = 82 kO and Ro = 39 kM. Determine the upper cutoff frequency. 8-4.2 A transistor in a single-stage CE amplifier

and C,. = 6 pF. The signal divider bias resistors are input-capacitance-limited has hy = 75 and f; = 12

MHz. The load resistance is Rc||R_ = 20k. Determine the upper 3 dB frequency (2) for the circuit. Also, calculate the output stray capacitance

that will produce an additional 3 dB attenuation at fy.

8-5 TRANSISTOR SWITCHING TIMES Turn-On Times For transistor switching circuits (see Sections 4-4 and

5-10), the switching

speed of the device can be an important quantity. Consider the circuit in Fig. 8-18a. When the base input current is applied, the transistor does not

Chapter 8

BUT Specifications and Performance

323

switch on immediately. Like frequency response, the switching time is affected by junction capacitance and the transit time of electrons across the junc-

tions. The time between the application of the input pulse and the beginning of collector current flow is termed the delay time (tg) (see Fig. 8-18b). Even when the transistor begins to switch on, a finite time elapses before Ic reaches

its maximum level. This is known as the rise time (t,). The rise time is specified as the time required for Ic to go from 10% to 90% of its maximum level. As il-

lustrated, the turn-on time (ton) is the sum of tg and t,.

Turn-Off Times When the input current is switched off, Ic does not go to zero until after a turn-off time, tor, made up of a storage time (t,) and a fall time (t,), as illustrated. The fall time is specified as the time required for Ic to go from 90% to 10% of

‘ Ic 90% Ie tinax)

10% Ic (max)

At

marr LI

vt

role tfon

—

ee tort —>1

_ (a) Transistor base and

|

(b) Current waveform relationships

collector currents

Figure 8-18

The turn-on time for a switching transistor is the sum of the delay time (ty)

and the rise time (,). The transistor turn-off time is the sum of the storage time (t,) and the fall time (t)).

its maximum level. The storage time is the result of charge carriers being trapped in the depletion region when a junction polarity is reversed. When a

transistor is in a saturated on condition (see Section 5-10), both the collectorbase and emitter-base junctions are forward biased. At switch-off, both junctions are reverse biased. Before Ic begins to fall, the stored charge carriers

must be withdrawn ot made to recombine with opposite-type charge carriers. For a fast-switching transistor, ton and fog must be of the order of nanoseconds. The excerpt from a 2N3904 transistor data sheet in Fig. 8-19 specifies the following switching times: ta = 35 ns, tr = 35 ns, ts = 200 ns, and t, = 50 ns.

324

Electronic Devices and Circuits

Characteristic

Symbol |

Switching Characteristics (2N3904) Delay time

Voc

=3V,

Ver

Min

Max

Unit |

e =05V,

ly

—

35

ns

Rise time

Ic =10mA, Ip; = 1 mA

b,

~

35

ns

Storage time

Vcc = 3 V,I¢ = 10 mA,

bs

—

200

ns

Fall

Ip,

ty

—_—

50

ns

time

Figure 8-19

=

Tp2

=lmA

Transistor switching times, as specified on a data sheet.

Example 8-7 The circuit shown in Fig. 8-18a uses a 2N3904 transistor and has an input pulse with a 5 pis pulse width (PW). Determine the time from the beginning

of Ic until the transistor turns off. Solution

Ic begins at ty (at 10% of Ic(max)) after the start of the input pulse, and ceases at (t; + ts) (at 10% of Ic(max)) after the end of the input pulse. t= PW

-tgt+t,+tp=5 ws — 35ns+ 200 ns + 50 ns

= 5.215 ps

Rise Time and Cutoff Frequency Just how fast a circuit can switch from off to on is related to its upper cutoff

frequency (fy). It can be shown that 0.35

a

(8-12)

r

So, for example, if the output pulse from the circuit in Fig. 8-18a has a rise time of 100 ns and the input pulse has a very much smaller rise time,

==

fa = 100 ns

95

2

It should be noted that in this case fj; is the same as fe, because a common-

emitter circuit is involved (see Section 8-3). Pulse testing can be used for

rapidly determining the upper cutoff frequency of a circuit or device. Switching Time Improvement The turn-on time can be shortened by overdriving the transistor, that is, applying a larger base current than required for transistor saturation. However,

BUT Specifications and Performance

Chapter 8

325

a larger Ip level produces an increased storage time and thus lengthens the

device turn-off time. Turn-off time can be reduced by the application of a

large negative input voltage to rapidly discharge the forward-biased junctions at switch-off. But the effect of this would be to make the turn-on time longer, because the transistor base would have to be raised from its negative

level before switch-on can begin.

Ideally for fast switching, the transistor base-emitter voltage should start

at zero, and Ip should be large at switch-on but should rapidly settle down to level required for transistor saturation. Also, a large negative

the minimum

voltage should be applied for switch-off to rapidly discharge the forward-bi-

ased junctions, but this voltage should quickly return to zero. These desirable conditions are achieved by connecting a capacitor (C;) in parallel with the base resistor, as in Fig. 8-20a.

Capacitor C1, known as a speed-up capacitor, short-circuits Rp when a positive input (+Vs) is applied, and thus the initial level of base current is

Vir

ios LORY OV

en

= Vs

—

-23V

(b) Waveforms showing effect of

(a) Switching circuit with

the speed-up capacitor

speed-up capacitor C;

Figure 8-20 capacitor.

J

OV

Vs

Vec

p—

p Transistor switching times can be improved by the use of a speed-u

the base increased to shorten the switch-on time. Without C, in the circuit, current is calculated from

Eq. 5-26: With Cy, The

capacitor-charging

Fig. 8-20b).

n=

i

ly = current

Vs — VBE

aoe Re

Vs — Ver

spike

(8-13)

Re

flows

into

the

base

terminal

(see

326

Electronic Devices and Circuits

When the capacitor is completely charged, I, returns to the normal Ig level

for Q; saturation, and the capacitor voltage is then Vai= TpRp

At switch-off, Vs goes to zero and —Vc; is applied to the transistor base,

thus improving Q; switch-off time. After switch-off, Vci returns to zero (discharged by Rg), so that there is no negative base-emitter voltage to affect the turn-on time. A suitable speed-up capacitance value is calculated by allowing C, to

charge by 60% during the specified transistor turn-on time. This will keep |, close to its maximum level during a reduced turn-on time, so as to turn Q; on as quickly as possible. C, charges via the signal source resistance (Rs), and it can be shown that for a 60% charge, ton = RgCy

_

giving

_ fon

CoS

(8-14)

Rs

Capacitor C; has the undesirable effect of limiting the maximum signal frequency that may be used with the circuit. After Q; switches on, C, has to be completely charged before switch-off begins. Also, after Q; switches off, C; has to be completely discharged to near zero volts before another switch-on pulse can be applied. A capacitor will charge or discharge by more than 99% in a time period of 5CR. Charge to C; is via Rs and discharge is via Rs. The time between switch-on and switch-off is the pulse width (PW) (see Fig.

8-20b), and this should not be less than PWomin) = 5RsCy

(8-15)

The time between switch-off and switch-on is the space width (SW) (Fig. 8-20b), which should be a minimum of

SWenin) = 5RpCy

(8-16)

The maximum signal frequency that may be used with a given switching circuit is dictated by the sum of the minimum pulse and space widths: T= PW+SW

giving

1

Ff (max) = PWian) +teeWieas SWea

(8-17)

Example 8-8 The circuit in Fig. 8-20a uses a transistor with a 100 ns turn-on time. Calculate

a suitable speed-up capacitor value, and determine

frequency that may be used with the circuit.

the maximum

signal

Chapter 8

BUT Specifications and Performance

327

Solution

= 8

Eq. 8-14:

= 167 pF (use 160 pF standard value) Eq. 8-15:

PWmin)= 5 Rs Ci= 5 X 600 0. X 160 pF

= 0.48 ys Eq. 8-16:

SW (min) = 5 Rp Cy; = 5 X 4.7kO, X 160 pF = 3.76 us fmax) = ll

Eq. 8-17:

1

PWomin) + SWanin)

_

1

0.48 ps + 3.76 ps

236 kHz

Practice Problems 8-5.1 Calculate the turn-on time and turn-off time for a transistor with tq =10ns,t, = 12ns,t, = 15 ns, and tf; = 12 ns. Also determine the time

from the beginning of a 100 ns input pulse to the end of the BJT on time. 85. 2 The upper cutoff frequency for a switching circuit (as in Fig. 8-18) is measured as 1.7 MHz. Calculate the rise time of the output when a pulse with negligible rise time is applied as input. 8-5.3 A direct-coupled switching circuit using a 2N3904 BJT has a 12 kO base resistance and a 350 {) source resistance. Determine a suitable speedup capacitor value. Calculate the minimum input pulse width and space width that should be used with the circuit.

8-6 TRANSISTOR

CIRCUIT NOISE

Unwanted signals at the output of an electronics system are termed noise. The noise amplitude may be large enough to severely distort or completely swamp the wanted signals. Conse-

A *°7

+ SSS

quently, the noise level dictates the minimum

signal amplitude that can be handled. Noise originates as atmospheric noise from outside the system and as circuit noise generated within resistors and devices. Consider a conductive material at room tem-

_ bo en AAA f Figoreé-24 Noleswoleaues

perature (Fig. 8-21). The motion of free electrons

are generated within a re-

drifting around in the material constitutes a flow of many tiny random electric currents.

sistor by random movements of electrons.

328

Electronic Devices and Circuits

These currents cause minute voltage drops, which appear across the ends (or terminals) of the material. Because the number of free electrons available and the random motion of the electrons both increase as temperature rises, the generated voltage amplitude is proportional to temperature. This unwanted, randomly varying voltage is termed thermal noise. Thermal noise is generated in resistors, and when the resistors are at the input stage of an amplifier, the noise is amplified and produced as an output. Noise from other resistors is not amplified as much as that from the resistors right at the input; consequently, only the input stage resistors need be considered in noise calculations. Noise is also generated within a transistor, and like

resistors, the input stage transistor of an amplifier is the most

important

because its noise is amplified more than that from any other stage. Because thermal noise is an alternating quantity, its rms output level from

any amplifier is dependent upon the bandwidth of the amplifier. It can be shown that the rms noise voltage generated in a resistance is

e, =V4kTBR

where

(8-18)

k = Boltzmann’s constant = 1.374 x 10°" J/K (i.e., joules per degree K)

T = absolute temperature (K) R = resistance (Q)

B = circuit bandwidth

(a) Common-emitter amplifier circuit

(b) Equivalent noise input circuit

Thermal noise at the input of an amplifier depends upon the Figure 8-22 equivalent resistance of the bias and signal source resistances.

In the circuit shown in Fig. 8-22a, R; and R2 are the bias resistors and ¢, is a signal voltage with source resistance rs. The total noise-generating resis-

tance (Rc) in parallel with the amplifier input terminal is

Rg = re||RillRo

(8-19)

Chapter 8

BUT Specifications and Performance

329

In the noise equivalent circuit (Fig. 8-22b), e, is the noise voltage generated

by Re. If the device input resistance is Rj, then the noise voltage is divided: soit Bisel

Rac Rj + Re

If the amplifier voltage gain is A,, the output noise due to Rg is no = Aveni

21)

With a circuit collector resistance Rc and load resistance R,, the noise output

power produced by Rg is 2 P=

Daal

(8-22)

eno

on

\|Ry

To specify the amount of noise generated by a transistor, manufacturers usually quote a noise figure. To arrive at this figure, the transistor noise output is measured under specified bias conditions and with a specified source resistance, temperature, and noise bandwidth. The noise figure defines the

amount of noise added by the transistor to the noise generated by the specified resistance (Rc) at the input. Recall that Rg is the combined bias and signal source resistances, as seen from the amplifier input.

Noise Characteristics (2N4104) Test conditions

Parameter

Veg = 5 V, Ic = 30 pA,

Rg = 10k, f= 10 Hz

Veg = 5V, Ic = 30 pA, NE Spot noise figure

Max

15 dB

0, f = 100 Hz Rg == 10k0,f

4 dB

Veg =5V, Ic =5 pA, Rg = 50kQ, f = 1 kHz

1dB

Veg

1dB

=5 Vi

Ic

=

5 pA,

Rg = 50 kO, f = 10 kHz

Figure 8-23

Min

Data sheet specification of noise characteristics for a 2N4104 transistor.

330

Electronic Devices and Circuits

The section of data sheet in Fig. 8-23 specifies spot noise figures for a 2N4104

transistor. This means that the noise has been measured for a bandwidth of 1 Hz. The bias conditions are listed because the transistor noise can be affected by Vcg and Ic. Note that the specified Ic levels are very low (5 1A to 30 1A),

because transistor noise increases with increasing current levels.

The noise factor (F) is the total circuit noise power output divided by noise

output power from the source resistor.

Be Po

(8-23)

Pac

The noise figure (NF) is the decibel value of F:

NF=10log,, F

(8-24)

Ideally, a transistor would add no noise to the circuit, and its noise figure would be zero. Obviously, the smallest possible transistor noise figure is the

most desirable. If the circuit in which the transistor is employed does not have the source resistance and the bias conditions specified, the specified noise figure does not apply. In this case the noise figures can still be used to compare transistors, but for accurate estimations of noise, a new measurement

of the noise

figure must be made. From Eq. 8-23, the total noise output power due to Rc and the input transistor is Pus

=F

XK Pag

(8-25)

Example 8-9 Calculate the noise output voltage for the amplifier

in Fig. 8-24 if the

transistor is completely noiseless. The circuit voltage gain is 600, the base

input resistance is 3 kQ, and the cutoff frequencies are f, = 100 Hz and fo = 40 kHz. The circuit temperature is 25°C.

Figure 8-24

Circuit for Examples

8-9 and 8-10.

Chapter 8 = BUT Specifications and Performance 331

Solution

Eq. 8-19:

Rg = rs||Ri||Ro = 30 kQ||30 kO||30 ka = 10k0 T = 25°C = (273 + 25) K = 298 K (degrees Kelvin)

B= fy — f, = 40 kHz — 100 Hz = 39.9 kHz Eq. 8-18:

€, = VAKTBR

= V4 Xx 137 x 10773 x 298 x 39.9 kHz X 10kO = 2.6 pV

Eq. 8-20:

4

R; Kk —— 1

=e,

= 9;

3kO —__

eri = On X RR, = ORV X BE + 10K = 0.59 pV

Eq. 8-21:

Eno = Ay eni = 600 X 0.59 LV

= 354 nV Example 8-10 The circuit in Ex. 8-9 uses a 2N4104 transistor with the following bias conditions: Ic = 30 pA and Vcg = 5 V. Calculate the total noise output voltage for

the amplifier. Solution From Fig. 8-23,

NE = 4 dB

F =antilog ( ~

From Eq. 8-24,

10

= antilog (

225

(°C)

Te Figure 8-27

Power derating graph for 2N3055 transistor.

Plot point B at Pp = 0 and T = 197°C. Draw the power derating graph through points A and B. From the graph, at T = 100°C,

Pp = 65 W

Maximum

Power Dissipation Curve

When the maximum power that may be dissipated ina transistor is determined, the maximum Ic level may be calculated for any given V cg, or vice versa. The

corresponding voltage and current levels may be more easily determined by drawing a maximum power dissipation curve on the transistor output characteris-

tics. To draw this curve, the greatest power that may be dissipated at the operat-

ing temperature is first calculated. Then, the corresponding collector current levels for the maximum power dissipation are calculated, using convenient

collector-emitter voltages. The curve on the device characteristics is plotted, using these current and voltage levels. Example 8-13 demonstrates the process.

Chapter 8

BUT Specifications and Performance

335

The transistor voltage and current conditions must at all times be mainta ined

in the portion of the characteristics below the maximum power dissipation curve. This means, for example, that all point on load lines must be below the curve.

Example 8-13 Draw

a maximum

power

dissipation curve for Pp = 80 W

on the Ic/ Vcr

characteristics in Fig. 8-28. (A) 10

0

0

10

20

30

40

50

60

Veg Figure 8-28 Transistor maximum power dissipation curve drawn on the Ic/Vce characteristics.

Solution

When en Vcz "CE = 60V, , TL

=

eee C "Vee (60V =

OO

Os

=13A

Plot point 1 on the characteristics at VcE

=60V

80 W

When Vcg = 40 V,

le = Foy

When Vcr = 20V,

80 W Ic = DOV

and

724

Ic =13A

(point 2)

. 4A (point 3)

(V)

336

Electronic Devices and Circuits

When Vcg = 10V,

Ic =

80 W = 8A 10V

(point 4)

Draw the maximum power dissipation curve through the points on the graph. a sk

edznis

with Ppvsc)= 310 mw

‘ ad the device maximum power dissipation at 7

v, deen

he four suitable points for drawing

"the maximum power. dissipation curve for the transistor in the above problem when Te; = 75°C.

8-8 HEAT SINKING When power is dissipated in a transistor, the heat generated must flow from

the collector-base junction to the case and then to the surrounding atmosphere. When only a very small amount of power is involved, as in a small-signal transistor, the surface area of the transistor case is normally large enough to allow all of the heat to escape. For the large power dissipations that can occur in high-power transistors, the transistor surface area is not large enough. Heat sinks must be used to increase the area in contact with the atmosphere. For small transistors, the clip-on star-type heat sinks illustrated in Fig. 8-29a may be used. For higher-power transistors, sheet-metal and aluminum-extrusion heat sinks are available, as illustrated

in Figs 8-29b and c.

(a) Clip-on type heat sink with TO-18 transistor enclosure

(b) Sheet-metal heat sink with TO-220 transistor

Figure 8-29

Heat sinks

are used to conduct heat from a transistor case so that the device will not

overheat when power is (c) Aluminum extrusion heat sink with TO-3 transistor

dissipated.

Chapter8

BUT Specifications and Performance

337

Figure 8-30a shows the cross-section of a high-power transistor fastened to a heat sink. The heat generated at the collector-base junction must flow from the junction to the transistor case, then from the case to the heat sink, :

Junction

+

+

7

Case

+

/

Collector-base junction Mica gasket

T;—-Ta

Te—Ts

_ :

Transistor ame

. Heat sink 6

Ts—Ta

. (a) Transistor and heat sink

Shs

SA

~

Air

(b) Thermal resistance circuit

Figure 8-30 The thermal resistances between the collector-base junction of a transistor and the air surrounding the transistor heat sink constitute a series thermal circuit. The thermal equivalent of Ohm’s law may be applied for circuit analysis.

and finally from the heat sink to the surrounding air. In many cases, a mica gasket is inserted between the transistor case and the heat sink for electrical insulation (see Fig. 8-30a). Each part of the path that the heat must pass

through has a thermal resistance. These are: 6;-—junction-to-case thermal resistance @cs—case-to-sink thermal resistance @sa—sink-to-air thermal resistance

Figure 8-30b shows the thermal equivalent circuit for the transistor and heat

sink. This consists of the three thermal resistances connected in series. The size of heat sink required for a transistor with a given power dissipation may be determined from the thermal equivalent circuit. The temperature difference between the transistor collector-base junction

and the air surrounding the heat sink (Tj — T,) causes the dissipated power

(Q) to flow through each of the thermal resistances in turn. The thermal resistance series circuit is analogous to an electrical series resistive circuit. The

power flow in the thermal circuit is similar to the current flow in the electrical circuit. Also, the temperature drop across each thermal resistance is analogous to the voltage drop across each electrical resistance (see Fig. 8-30b). Ohm’s law may be applied toa thermal series circuit exactly as in the case of

an electrical series circuit.

338

Electronic Devices and Circuits

For an electrical series resistive circuit,

= E/R or

voltage difference

current flow = ————_____—— total resistance For a series thermal resistance circuit,

P

ower flow

=

temperature difference total thermal resistance

aT

or

ope oh jc

(8-27)

+ O0cs + Osa

When the temperatures are in degrees Celsius (°C) and the thermal resistances are in degrees Celsius per watt (°C/W), Q is the power dissipated in watts (W).

The value of 0c depends upon the transistor case style, and it is usually specified on the data sheet. See the excerpt from a 2N3055 data sheet in Fig. 8-31. 8cs is dependent on the transistor case and on the mechanical contact between the case and the heat sink. The contact may be dry, have a layer of heatconducting compound, or have an insulating gasket. Table 8-1 shows typical cs values for three case styles and three contact conditions. 6s, is determined

by the size and style of the heat sink (see Table 8-2 and Appendix A-10). Thermal Characteristic (2N3055) Characteristic

Junction-to-case thermal resistance

Ic

Max

Unit

1.52

°C/W

Figure 8-31 Section of 2N3055 data sheet showing the transistor junction-to-case thermal resistance.

Table 8-1

Typical Case-to-sink Thermal Resistances for Various Mechanical

Connections

|

Acs (°C/W)

8cs (°C/W)

Transistor = .Case

Dry

TO-220

1.2

0.7

1.0

TO-3

0.6

0.4

0.5

TO-66

1.5

0.5

23

Metal-to-Metal With Compound

With Mica Insulator and Compound

Chapter 8

Table 8-2

BUT Specifications and Performance

339

Typical Sink-to-air Thermal Resistances for Various Heat Sinks

“aa Heat Sink Style

sige __Wakefield Transistor Case _ Heat Sink Type

Star-type clip-on

_

Natural Convection Osa Osa

TO-18

201

65°C/W

65°C @1 W

Sheet metal with fins

TO-220

289

25°C/W

50°C @2 W

Aluminum extrusion

TO-3

401

2/°CIW

80°C @ 30 W

=

a

”

403

1.8°C/W

55°C @ 30 W

id

o

”

421

1.2°C/W

58°C @ 50 W

it

#

”

423

0.94°C/W

47°C @50 W

i

2

”

44]

0.59°C/W

47°C @ 80 W

ve

.

“

621

5°C/W

75°C @15W

Equation 8-27 may be used to calculate 4s, when all other quantities are known. The smallest heat sink with a thermal resistance equal to or lower than the calculated value is then selected. Alternatively, when a given heat

sink is used, Eq. 8-27 may be applied to calculate the transistor junction temperature.

Another method used to specify heat sink thermal resistances is shown in

Table 8-2. For the Wakefield 621 heat sink, Os, is listed as 75°C at 15 W

for

natural convection. This means that the maximum temperature difference between the case and the surrounding air will be 75°C when the heat sink is dissipating 15 W. This can be redefined as _ dok

"8A ~ 15 W

= 5°C/W

Example 8-14 A transistor with

Vcg = 20 V and Ic = 1 A has a 1°C/W

thermal resistance. The TO-3 case is fastened directly conducting compound is used. Calculate the thermal sink that will keep the maximum junction temperature bient temperature is 25°C. Select a suitable heat sink

junction-to-case

to the heat sink, and resistance for a heat at 90°C when the amfrom Appendix A-10.

Solution Q=Vcgle =20VX1A = 20 W From Table 8-1, @cs = 0.4°C/W From Eq. 8-27,

Osa =

Ty — Ta a

(TO-3 case, direct contact with compound)

— (Ac + 4s)

340

Electronic Devices and Circuits

25°C _ 90=°C 20 W

~ (1°C/W + 0.4°C/W)

= 1.85°C/W

From Table 8-2 (and Appendix A-10), the 403, 421, 423, and 441 all have 65, less than 1.85°C/W for natural convection. Select the smallest and least expensive of the three—the 403.

Practice Problems 8-8.1

A 2N6121 transistor (see Appendix A-9) is fastened to a heat sink with

the use of a mica insulator and compound. Calculate the thermal resistance of a suitable heat sink if the device is to dissipate 10 W and the maximum junction temperature temperature is 25°C.

is to be 100°C.

The

ambient

8-8.2 A TO-3 style transistor with Tymay = 140°C and 6jc = 0.6°C/W is fastened

dry

to a heat

sink

with

a Oc, = 1.3°C/W.

Determine

the

maximum power that may be dissipated when T, = 40°C.

Review Questions Section 8-1 8-1 Define the following BJT quantities listed on a device data sheet: Vcno, Vcro. Vepo, and Vc£(sat)8-2 Define the following BJT quantities: Ic, Icgo, Ico, Mre, and hye. Section 8-2

8-3

Write the equations for determining power gains and power level changes in decibels (a) when

8-4

two power levels are measured

and

(b) when

two voltage

levels are measured. Sketch a typical frequency response graph for an amplifier, and identify the upper and lower cutoff frequencies and the bandwidth. Briefly explain.

Section 8-3 8-5

Define fue, fab, and ft for a BJT. Briefly explain.

8-6

Explain CB and CE junction capacitances, and identify the quantities that determine junction capacitance values.

8-7

Describe the Miller effect, and derive an equation for the input capacitance of

an inverting amplifier. Section 8-4 8-8

Identify the quantities that cause the gain of an amplifier to fall off at low frequencies. Briefly explain.

8-9

Discuss

the quantities that cause

frequencies.

the gain of an amplifier

to fall off at high

Chapter 8

BUT Specifications and Performance

341

Section 8-5 8-10

Sketch the waveforms of input and output currents for a switching transistor. Show the various switching times involved and explain the origin of each.

8-11

Draw the diagram of a direct-coupled BJT switching circuit using a speed-up capacitor. Explain how the capacitor affects the device switching times, and discuss the limits of input pulse width and space width that can be used with the circuit,

Section 8-6 8-12

Explain thermal noise, and discuss the effect of resistor noise at the input of a

transistor. Define noise figure and noise factor for a transistor.

Section 8-7 8-13 8-14

Sketch a typical power-temperature derating graph for a transistor. Briefly explain. Describe how a transistor maximum power dissipation graph may be drawn on the Ic/ Vcr characteristics.

Section 8-8 8-15

Sketch the cross-section of a power transistor and heat sink. Label the thermal resistances in the power dissipation path.

8-16

Write the equation thermal resistance.

e at ret egrets ities 85 NOMB

Draw the thermal resistance equivalent circuit for a transistor and heat sink. relating power

dissipation, temperature difference, and

Problems Section 8-1 8-1

From Appendix A-9, determine the following quantities for a 2N6125 transistor: maximum

Vcg, maximum

collector current, maximum

Vee, HEE max), and

hrg(min) atIc = 1.5A.

8-2

From the 2N3055 data sheet A-8 in Appendix A, determine the following quantities: maximum collector-base voltage, maximum collector current, maximum emitter-base voltage, hpg minimum, and /ipg maximum at Ic = 4A.

Section 8-2

8-3

The output power from an amplifier is 100 mW when the signal frequency is 1 kHz. When the signal frequency is increased to 25 kHz, the output power falls to 75.mW. Calculate the decibel change in output power.

8-4

8-5

Calculate the power gain for an amplifier resistances when v; = 100 mV and v, = 3 V.

with

equal

input

and

load

The output voltage of an amplifier is 2 V when the signal frequency is 1 kHz. Calculate the new output voltage when it has fallen by 4 dB.

342

Electronic Devices and Circuits

Section 8-3 8-6 The input capacitance of a CE circuit is measured

as 800

pF.

The

circuit

has Rc = 7 kQ, and the device has the following parameters: Mj. = 60 and hie = 1.5 kQ. If the base-emitter capacitance is 15 pF, calculate the collector8-7

8-8

base capacitance. A transistor with hj = 100, hie = 2.2 kN, Ca, = 3 pF, Ic = 1.2 mA, and fr; = 4 MHz is connected as a CE amplifier with Re||Ri = 6.8 kQ. Calculate the amplifier input capacitance.

= Calculate the new value of Ci, for the amplifier in Problem 8-7 when a 100 pF capacitor is connected (a) between emitter and base and (b) between collector and base.

8-9

For acommon

emitter amplifier, A, = 50, Cin = 414 pF, and C,. = 8 pF. Calcu-

late the base-emitter capacitance.

Section 8-4 8-10

The circuit in Problem 8-7 uses voltage-divider bias with R; = 56 kf) and Rz = 15 kO. The signal source resistance is 3.3 k. Calculate the input-capaci-

8-11 8-12

tance-limited upper cutoff frequency for the circuit. Repeat Problem 8-10 for the circuit connected to function as a CB amplifier. A voltage-divider bias circuit (as in Fig. 8-24) has the following components: R, = 68 kQ, R2 = 47 kQ, Rc = 5.6 kO, Re = 4.7 kQ.. The supply voltage is 12 V,

8-13 8-14

and the transistor has ff = 35 MHz and C,, = 3.5 pF. Calculate the input-capacitance-limited upper cutoff frequency when the circuit is connected as a CE amplifier with Rg bypassed. The signal source resistance is 1.5 k{. Repeat Problem 8-12 for the circuit employed as a CB amplifier with the transistor base bypassed to ground. The circuit in Problem 8-12 is modified to function as an emitter follower with Rc shorted and the output taken from the emitter. Determine capacitance-limited upper cutoff frequency for the circuit.

8-15

the

input-

A transistor employed in an amplifier has My. = 75 and f4, = 12 MHz. The collector load is Re|| Ri = 20 kO, and there is 100 pF stray capacitance at the out-

8-16

put. Determine the stray-capacitance-limited upper 3 dB frequency. Atransistor amplifier with Re|| R, equal to 15kO hasa75 kHz upper 3 dB frequency. Assuming that f; is determined by the stray capacitance at the transistor collector

terminal, calculate the value of the stray capacitance.

Section 8-5 8-17

Determine the turn-on and turn-off times for a switching circuit with a 2N3251

transistor (see Appendix A-7). 8-18

If the circuit in Problem 8-17 has a 2 kHz square wave input at the transistor base, calculate the time from the instant that the collector current first reaches 90°» of its

maximum level until it falls to 10% of maximum. 8-19

A switching circuit is to be turned on and off by a 1 MHz

square wave input.

The output rise and fall times are not to exceed 10% of the transistor o/! time.

Determine the maximum value for f, and f;.

Chapter 8

BUT Specifications and Performance

343

—__—

8-20

A direct-coupled

switching circuit in which Rp = 4.7 kQ uses a BJT with

ton = 150 ns. The signal source resistance is Rs = 400 . Determine a suitable

value of speed-up quency.

8-21

capacitor, and

calculate the maximum

pulse input fre-

Determine a suitable value of speed-up capacitor for the BJT switching circuit in Fig. 5-56. Assume that the signal source resistance is 500 and that the transistor has ton = 200 ns. Calculate the minimum input pulse width that can be used with the circuit.

Section 8-6

8-22

An amplifier with a 2N4104 input transistor (see Fig. 8-23) has 3 dB points at 2 kHz and 10 kHz, respectively. The transistor bias conditions are: Vcg = 5 V and

Ic = 5 pA; the amplifier voltage gain is 40. Calculate the noise output voltage at 25°C if Rc = 50 kO and R; = 10 kQ. 8-23

A transistor amplifier where A, = 100, B = 15 kHz, and Rj = 12 kQ has input

bias resistors equivalent to Rg = 33 k©. If the maximum noise voltage at the output is not to exceed 100 ,V, determine the largest tolerable noise figure for the input transistor. 8-24

An amplifier with B = 10 kHz, Rg = 5 kQ, and Rj = 3.3 kO has a maximum

output noise of 150 1V. Assuming that the transistor is noiseless, determine the amplifier voltage gain. Section 8-7 8-25 Calculate the maximum ambient temperature for a transistor with a 200 mW

power dissipation if Ppy2sec) = 310 mW and D = 2.81 mW/°C. 8-26

The device in Problem 8-25 is to be operated at 80°C maximum ambient with a 5 mA collector current. Determine the maximum

8-27

Vc¢ level that may be used.

Referring to Appendix A-9, draw a power derating graph for a 2N6121 transistor and determine the maximum power dissipation at a case temperature of

8-28 8-29

7°C. Calculate the maximum case temperature for a 2N3251 transistor when its power dissipation is 0.25 W. A2N3055 transistor is to be operated at a maximum case temperature of 125°C. Construct a suitable Ic/Vcg graph, and draw the maximum power dissipation

curve for the device at this temperature. 8-30

For the Pp = 80 W maximum power dissipation curve in Fig. 8-28, draw the de

load line for the smallest possible value of Rc when the circuit supply voltage is 50 V. Determine the value of Rc(min).

Section 8-8

8-31

A 2N3055 transistor has a Vcg of 10 V and an Ic of 500 mA. The case temperature is not to exceed 30°C when the ambient temperature is 25°C. The device is

fastened to a heat sink by means of a mica gasket and compound. Calculate the maximum

sink-to-air thermal resistance for a suitable heat sink.

Electronic Devices and Circuits

8-32

A 2N3055 transistor dissipating 9 W is directly fastened to a NC403 heat sink by means

of compound

(see Appendix A-10). If the ambient

temperature is

25°C, calculate the transistor case temperature and junction temperature.

8-33

A 2N4900 transistor has a specified maximum power dissipation of 25 W ata

case temperature of 25°C, and a derating factor of 0.143 W/°C. If the transistor is to dissipate 20 W, determine its maximum

case temperature and calculate

the maximum sink-to-air thermal resistance for a suitable heat sink. Assume

that the TO-66 case is directly connected to the heat sink with compound. 8-34

A TO-220 case style transistor with a Vcg of 30 V and an Ic of 500 mA is fastened to a heat sink with a mica gasket and compound.

mum

Calculate the maxi-

sink-to-air thermal resistance for a suitable heat sink if the transistor

maximum junction temperature is 150°C and the junction-to-case thermal resistance is 2.7°C/W.

Practice Problem Answers 8-1.1 8-2.1 8-3.1 8-4.1 8-4.2 8-5.1 8-5.2 8-5.3 8-6.1 8-6.2 8-7.1 8-7.2 8-8.1 8-8.2

90, 100, 40 V, 5 V,6 dB —12 dB 4.86 nF 191 kHz 49.7 pF 22 ns, 27 ns, 127 ns

206 ns 200 pF, 0.35 ys, 12 ps

2.14mV 4.28 mV (310 mW, 25°C), (0, 135°C) (40 V, 4.24 mA), (30 V, 5.65 mA), (20 V, 8.48 mA), (10 V, 16.95 mA) 3.38°C/W 40 W

CHAPTERS Field Effect Transistors Objectives

You will be able to:

1 Explain the operation of nchannel and p-channel junction field effect transistors (JFETs). Draw typical JFET

characteristics. Identify the

regions of the characteristics and all important current and voltage levels. For JFETs, define saturation current, pinch-off voltage, forward transfer admittance,

output admittance, and drainsource on resistance. Determine JFET parameter

values from manufacturers’

data sheets. From the data sheet information, draw the maximum and minimum

transfer characteristics for any given JFET type number. 6 Solve problems involving JFET characteristics and parameters.

7 Show how a JFET can be used

for voltage amplification and for switching. 8 Explain the operation of enhancement-mode and depletion-enhancement-mode MOSFETs.

Draw typical drain and transfer characteristics for MOSFETs, and discuss the differences between MOSFETs and JFETs. 10 Solve problems involving MOSFET characteristics and parameters.

11 Explain the operation of

VMOSFETs, sketch typical characteristics, and discuss the advantages of VMOS. 12 Sketch circuit symbols for JFETs, MOSFETs, and VFETs.

Identify all terminals, current directions, and voltage polarities.

INTRODUCTION A field effect transistor (FET) is a voltage-operated device that can be used in amplifiers and switching circuits, similar to a bipolar transistor. Unlike a BJT, a FET requires virtually no input current. This gives it an extremely high input resistance, which is its most important advantage over a BJT. There are

two major categories of field effect transistors: junction FETs and MOSFETs.

These are further subdivided into p-channel and n-channel devices.

346

Electronic Devices and Circuits

9-1

JUNCTION FIELD EFFECT TRANSISTORS

n-Channel JFET The operating principle of an n-channel junction field effect transistor (JFET) is illustrated by the block representation in Fig. 9-1a. A piece of n-type semiconductor material, referred to as the channel, is sandwiched between two smaller pieces of p-type (the gates). The ends of the channel are designated the drain (D) and the source (S), and the two pieces of p-type material are connected together and their terminal is named the gate (G). With the gate left unconnected and a drain-source voltage (Vp) applied (positive at the drain, negative at the source), a drain current (Ip) flows, as

shown in Fig. 9-1a. When a gate-source voltage (Vcs) is applied with the gate negative with respect to the source (Fig. 9-1b), the gate-channel pn-junctions

are reverse biased. The channel is more lightly doped than the gate material, so the depletion regions penetrate deep into the channel. Because the depletion regions are regions depleted of charge carriers, they behave as insulators. The result is that the channel is narrowed, its resistance is increased, and Ip is reduced. When the negative gate-source bias voltage is further increased, the depletion regions meet

at the centre of the channel

(Fig. 9-1c), and Ip is cut off.

+Vp

Drain

oe

Drain (D)

+p

WiyPS

channel

tap

55

b

current

Depletion

£P. letion

regions

regions

meet \ Fi

.

Vv, GS

p-type 74

gates (G)

V Gs

Voss cst fe

Source (S)

(a) No gate-source

(b) Small negative gate-

Ip De) +~—_ Pinch-off region

8

24

0

0

Le

!

ft

}

|

|

|

!

6+

44

Vos = 0

|

|

fgg =

Ip

|

||

o Li

|

|| |

-—}-—_+—__+—_}+—__}+—__+—__ 12 14 8 10 6 4 2 Vos Vp

++ 16 18

(v)

f Breakdown

voltage Figure 9-8

Ip/Vps characteristic for an n-channel JFET with Vos = 0.

Chapter9 =

Field Effect Transistors

351

voltage drop along the channel. This results in some depletion penetration of the channel (as explained for Fig. 9-6), but it is so small that it has no signifi-

cant effect on the channel resistance. With further small increases in Vpg, the drain current increase is approximately linear and the channel behaves as an almost constant-value resistance (see Fig. 9-8).

The channel continues to behave as a fixed-value resistance until the voltage drops along it become large enough to produce considerable depletion region penetration. At this stage the channel resistance begins to be affected by the depletion regions. Further increases in Vps now produce smaller Ip increases, as shown by the curved part of the characteristic. The increased Ip

levels, in turn, cause more depletion region penetration and greater channel resistance. Eventually, a saturation level of Ip is reached where further Vps increase seems to have no effect on Ip.

At the point on the characteristic where Ip levels off, the drain current is referred to as the drain-source saturation current (Ipss) (10 mA in Fig. 9-8). The

shape of the depletion regions in the channel at the Ipss level is such that they appear to pinch off the channel (see Fig. 9-6). Thus, the drain source voltage at this point is termed the pinch-off voltage (Vp) (4.5 V in Fig. 9-8.) The region of th.

characteristic where Ip is constant is called the pinch-off region, as illustrated. The channel mostly behaves like a resistance between the points where Vps = 0 and Vps = Vp;so this part of the characteristic is referred to as the channel ohmic region. If Vps is continuously increased (in the pinch-off region), a voltage is

reached at which the (reverse-biased) gate-channel junctions break down (see Fig. 9-8). When this happens, Ip increases rapidly and the device may be destroyed. The pinch-off region of the characteristic is the normal operating region for the FET.

Drain Characteristics with External Bias A circuit for obtaining the Ip/Vps characteristics for an n--channel JFET when

an external gate-source bias (Vgs) is applied is shown in Fig. 9-9. In this case, Ves is set to a convenient (negative) level (such as —1 V). Vps is increased in steps, and

the corresponding level of Ip is noted at each Vps step. The Ip/Vps characteristic for a Veg of

—1 Vis then plotted, as illustrated in Fig. 9-10. When a —1 V external gate-source bias voltage is applied, the gate-channel junctions are reverse Vps = 0,

biased the

even

when

depletion

Ip = 0. So when

regions

are

already

Figure 9-9 Circuit for obtaining the Ip/Vps characteristic

penetrating to: some depth into the channel. Because of this, a smaller voltage drop along

for an n-channel junction field effect transistor with vadoustete-aenmes tins

the channel (smaller than when Ves = 0) will

voltages.

352

Electronic Devices and Circuits

increase the depletion regions to the point at which they produce channel pinch-off. Consequently, when Vcg = —1 V the pinch-off voltage is reached at a lower Ip level than when Vos = 0. The Ves = —1 V characteristic in Fig. 9-10 has Vp = 3.5 V. (mA)

Rt Ipss

—

10

Saturation

4] 4 Veogss0 | GS

- | |1

dens

| Liste

Vcgs = -1V

—-1V

it

|

|

|

|

1 |

|

Ip

|

'

eer

Ves

current for

7 :

ff

—__|

|

ei

| |

fy

|

—

|

) |

14

|

|| |

| te

16

18

1] | 0

a 0

2

4

6

8

Vp

10

12

Vps

14

(V)

Breakdown

:

voltage for

Pinch-off

Veg = -1V

voltage for Figure 9-10

[,/Vps characteristics for Ves = 0 and Ves = —1 for an n-channel! JFET.

A family of drain characteristics can be obtained by using several levels of negative gate-source bias voltage (see Fig. 9-11). If a positive Veg is used, a

higher level of Ip can be produced, as shown by the characteristic for Ves = +0.5

V. However,

Vcs is normally

kept

negative

to avoid

the

possibility of forward-biasing the gate-channel junctions. The dashed line from the zero point on the characteristics in Fig. 9-11

is

drawn through the points at which Ip saturates for each level of gatesource bias voltage. When Vcs=0, Ip saturates at Ipss, and_ the characteristic shows Vp = 4.5 V. When a —1 V external bias is applied, the

gate-channel junctions still require —4.5 V to achieve pinch-off. This means that a drop of 3.5 V instead of 4.5 V is now required along the channel, and the lower voltage drop is achieved with a lower Ip. Similarly,

when Ves = —2 V and —3 V, pinch-off is achieved with 2.5 V and 1.5 V, respectively, along the channel. The 2.5 V and 1.5 V drops are, of course,

obtained with further reduced Ip levels. Suppose a —4.5 V gate-source bias is applied to a device with the

characteristics shown in Fig. 9-11. This is a Vgs level equal to the pinch-

off voltage Vp. Without any additional channel voltage drop produced by Ip, the depletion regions penetrate so deep into the channel

that they

Chapter9

10 1.5 V3.5 25V45V Figure 9-11

V,

Field Effect Transistors

122

#144

«6

#18

353

(V)

iS

Family of Ip/Vps characteristics for an n-channel JFET

with various levels of Vgs.

meet in the middle, completely cutting Ip off. So, a gate-source bias equal to

the pinch-off voltage reduces Ip to zero. The bias voltage required to do this is termed the gate cutoff voltage (Vcsiorm), and, as explained,

Vesvoty = Ve.

Note in Fig. 9-11 that the drain-source voltage at which breakdown occurs is reduced as the negative gate-source bias voltage is increased. because — Vcs adds to the reverse bias at the junctions.

This

is

Example 9-1 Plot the Ip/ Vps characteristic for a JFET from the following table of values obtained with Vcs = 0. Determine Ipss and Vp from the characteristics.

Solution On Fig. 9-12, plot point 1 where Vps = 0 and Ip = 0.

Plot point 2 at Vps = 1 V and Ip = 3 mA, Vps = 9 V and Ip = 8 mA. and so on through Draw the drain characteristic for Vcs = 0 through points 1 to 10. From the characteristic, Ipsg = 8 mA and Vp = 3.75 V.

354

Electronic Devices and Circuits

(mA) 12 10

(V)

Figure 9-12

FET characteristics for Ex. 9-1.

Transfer Characteristics The transfer characteristics for an n-channel JFET are a plot of Ip versus Vs. The gate-source voltage of an FET controls the level of the drain current; so the transfer characteristic shows how Ip is controlled by Vcs. As illustrated

in Fig. 9-13a, the transfer characteristic extends from Ip = Ipss at Vcs = 0, to Ip = 0 at Ves = —Vos(orpFigure 9-13b shows a circuit for determining experimentally

a table of

quantities for plotting the transfer characteristic of a given FET. The drain-

-5 -4 -3 -2 -1

0

i

Ves(ott)

(a) Transfer characteristic Figure 9-13

(b) Circuit for determining

the transfer characteristic

The transfer characteristics for a FET are a plot of Ip versus Ves.

source voltage is maintained constant, Vcsis adjusted in convenient steps, and the corresponding levels of Vs and Ip are recorded.

Chapter 9

The

transfer

characteristic

for a FET

Field Effect Transistors

can be derived

from

355

the drain

characteristics. A line is drawn vertically on the drain characteristics to represent a constant Vps level. The corresponding Ip and Vgs values along this line

are noted

and

then

used

to plot the transfer

characteristic.

The

process is demonstrated in Ex. 9-2.

Example 9-2 Derive

the

transfer

characteristic

for

Vps=8

V

from

the

FET

drain

characteristics in Fig. 9-11. Solution

On Fig. 9-11, draw a vertical line at Vps = 8 V. From the intersection of the line and the char-

acteristics, read the following quantities:

On Fig. 9-14, plot point 1 at Vcg=0 Ip = 10 mA.

> 10

and

Plot point 2 at Ves = —1 V and

Ip = 7 mA, and so on through Ves = —4 V and Ip = 0.5 mA. Draw the transfer characteristic through these points.

p-Channel JFET Characteristics

Ves Figure 9-14 Transfer characteristics for Ex. 9-2.

Figure 9-15 shows a circuit for obtaining the

characteristics of a p-channel JFET. Note the direction of the arrowhead on the FET symbol, and the drain current direction. Note also the supply voltage polarity and the polarity of the gate-source bias voltage. The drain terminal is negative with respect to the source, and the gate

terminal is positive with respect to the source.

of quantities wefor plotting a To obtain a table . Sf

drain characteristic, Vcs is maintained constant

ee ining

Glroult fordeter-

the characteristics of

a p-channel JFET.

at the desired (positive) level, — Vps is increased in steps from zero, and the Ip levels are noted at each step.

Typical p-channel JFET drain characteristics and transfer characteristics are shown in Fig. 9-16. It is seen that these are similar to the characteristics for an

356

Electronic Devices and Circuits

Transfer characteristic 4

(mA)

Drain characteristics

wet

-Veg= =0.5-VSS

|

Figure 9-16

_

|

bs = 9

Transfer and drain characteristics for a p-channel JFET.

n-channel JFET, except for the voltage polarities. In Fig. 9-16, when

Vcs = 0,

Ipss = 15 mA, and progressively more positive levels of Vcs reduce |p toward cutoff Vesory) = +6 V. Using Ves of —0.5 V produces a higher Ip than when Vcs = 0. As in the case of the n-channel JFET, forward bias at the gate-channel

junctions should be avoided; consequently, negative Vcs levels are normally

not used with a p-channel JFET. The transfer characteristic for a p-channel device can be obtained experi-

mentally or can be derived from the drain characteristics, just as for an n-channel FET.

Practice Problem 9-2.1

The following table of Ip/Vps values for a FET was obtained with a Vcs

of 0. Plot the drain characteristic and determine Ipss and Vp. 10 ae }

12 SS

9-3 JFET DATA SHEETS AND PARAMETERS Maximum Ratings

Typical FET data sheets A-11 and A-12 are shown in Appendix A, and part of a FET data sheet is reproduced in Fig. 9-17. As with other device data sheets, a

device type number and brief description are usually given at the top. Maximum ratings follow, and then the electrical characteristics are stated for

Chapter9 _

FieldEffect Transistors

357

25457, 2N5458, 2N5459 (Silicon) ~ N-Channel FET Silicon N-channel junction field-effect transistors _ designed fot general-purpose audio and switching

applications. j

Bae

|

Maximum ratings

(TO-92)

omige

cinain andl ponte

Symbol | Value |

g

may be interchanged: Drain-source voltage

Drain-gate voltage | Reverse gate-source voltage | 2 Gate current ~

a?

Figure 9-17

‘2

if tA

‘

Unit

Vos

25

Vac

Vpc

25

Vac

Vegi)

25

Vite

Ig

10

mA

>

Part of data sheet for n-channel JFET.

specific bias conditions. From Fig. 9-17, the maximum drain-source voltage

(Vpg) for the 2N5457 to 2N5459 devices is 25 V, and the maximum drain-gate

urce voltage (Vpc) is also 25 V. This means, for example, that if a —5 V gate-so bias is used, the drain-source voltage should not exceed

Vos= Vpcimax) — Ves = 25V —5V =20V

is Note in Fig. 9-17 that the maximum reverse gate-source voltage (Vos) specified as 25 V. This is considerably greater than the (typically 5 V) maximum base-emitter reverse voltage for a BJT.

No maximum drain current is specified in Fig. 9-17, but this can be calcu-

ed lated from the maximum power dissipation and the Vps level. The specifi eel

ons gate current (Ic) is the maximum gate current if the gate-channel juncti

become forward biased. Saturation Current and Pinch-off Voltage

Voesiotf) The drain-source saturation current (Ipss) and the pinch-off voltage (Vp or

have already been discussed in Section 9-2. Values for these are listed in the excerpt from a JFET data sheet showing the ‘off characteristics’ and ‘on characteristics’ in Fig. 9-18. It can be seen that Vso for a 2N5457 (underline) ranges

from a minimum of —0.5 V to a maximum of —6 V. Also, the Ipss level for a

5 mA. 2N5457 (dashed underline) is a minimum of 1 mA and a maximum of

nana ORR Rees

Se

nyeeraslagte em 24:

The FET transfer characteristic approximately follows the equation:

Ip

=

Ipss

1

a

Ves 7 V cscoff)

(9-1)

358

Electronic Devices and Circuits 2N5457, 2N5458, 2N5459

Off Characteristics Characteristic

Symbol}

Gate-source cutoff voltage (Vps

=15V

dc, Ip

=

10 nA

Min

Typ

Max

Vegs(ofh)

Unit

Wale

dc)

2N5457

0.5 | —

2N5458

1.0

2N5459

—

2.0

=

60 ae

0

On Characteristics Zero gate voltage drain current (Vps

=15V

dc,

Vos

=

Ipss

mate

0)

2N5457

1.0

2N5459

4.0

2N5458

3.0

|

5.0__|

a9.0 | 16.0 ee

Figure 9-18 Gate-source cutoff voltage and drain-source saturation current specifications for n-channel JFETs.

When Ipss and Vegi) are known, a table of corresponding values of Ip and Vgs can be determined from Eq. 9-1. These may be used to construct the

FET transfer characteristic. Because of the wide range of specified values for Ipss and Vesiof, the transfer characteristic can differ substantially from one device to another one with the same type number. This creates a problem in FET bias circuits (see Chapter 10).

Example 9-3 Using the information provided on the data sheet (Fig. 9-18), construct the minimum and maximum transfer characteristics for a 2N5459 JFET. Solution

From Fig. 9-18,

Vos(ott) = —2 V (min), —8 V (max)

and

Ipss = 4 mA (min), 16 mA (max)

To construct the minimum

transfer characteristic, substitute Voes(otf(miny and

Ipss(min) into Eq. 9-1, together with convenient levels of Vs.

Eq. 9-1: For Vg = 0,

Ip = Ios Ip =4mA[I

-

Vos

i

Voes(off)

— (0/2 V) PF =4mA

Chapter 9

Field Effect Transistors

359

transfer characteristic on Fig. 9-19 at Ves = 0

Plot point 1 for the minimum and Ip = 4mA. For Ves = 0.25 Vesvors),

Ip = 2.25 mA:

point 2

For Ves = 0.5 Vescotf,

Ip = 1 mA:

point 3

For Ves = 0.75 Ves(ort,

Ip = 0.25 mA:

point 4

For Ves = Vascoff),

Ip = 0:

point 5

The minimum transfer characteristic is now drawn through points 1 to 5. For the maximum transfer characteristic, the above process is repeated using Ves(of = —8 V and Ipss = 16 mA.

ForVcs=0,

— (0/8 V)/? =16mA

Ip=16mA[l

Plot point 6 for the maximum transfer characteristic on Fig. 9-19 at Ves = 0 and

Ip

=

16mA.

For Ves = 0.25 Vescote),

Ip = 9 mA:

point 7

For Vos = 0.5. Vescorty,

Ip = 4mA:

point 8

For Ves = 0.75 Ves(otp,

Ip = 1 mA:

point 9

For Ves = Ves(off),

In = 0:

point 10

Draw the maximum transfer characteristic through points 6 to 10. (mA) tis 6 /

16

Ipss(max)

14

ee nm

Mem: MeAR

N

12

Figure 9-19 0

Maximum and mini-

mum transfer characteristic for a 2N5459 JFET constructed for

Ex. 9-3.

360

Electronic Devices and Circuits

Forward Transfer Admittance

The forward transfer admittance (Y¢.), which is also known as the trans conductance (gm Or grs), for a FET defines how the drain current is controlled by the gate-source voltage.

Y=

ManaGon in Ip

(when Vp. remains constant)

variation in Veg

Vis

ai

Ailip

(9-2)

AVcs|Vps

The units used for Y;, are microSiemens (wS), which can be restated as

microamps per volt (uA/V). MilliSiemens (mS), or milliamps/volt (mA/V) may also be used. For a FET with Y;, = 2 mA/V, Ip changes by 2 mA when

V¢z is al-

tered by 1 V. In the portion of a FET data sheet in Fig. 9-20, the Y;, units are ywmhos. The mho (ohm written backwards) is another (older) name for the Siemens, the unit of conductance. For the 2N5457 (underlined) the value of Vn

is specified as a minimum of 1000 wmhos, and a maximum of 5000 wmhos. An

inverted ohm symbol is also sometimes used instead of the Siemens symbol. 2N5457, 2N5458, 2N5459

Dynamic Characteristics Characteristic

Symbol}

Forward Transfer Admittance (Vps

= 15 V dc,

Vos

= 0, f=

Typ

Max

Ye

Unit

pavthos

1 kHz)

2N5457 2N5458 2N5459 Figure 9-20

Min

1000 1500 2000

3000 4000 4500

5000 5500 6000

JFET forward transfer admittance specification.

Because Y;, defines the relationship between Ip and Vgg, it can be determined from the slope of the FET transfer characteristic. This is demonstrated in Ex. 9-4 and illustrated in Fig. 9-21.

Example 9-4 Determine Y;, at Vcg = —1 V and Vgs = —4 V from the 2N5459 FET transfer

characteristic in Fig. 9-21. Solution At Ves

Eq. 9-2:

=

-1V,

y, - Alp _ 43mA AVee

125

= 3.4mA/V = 3400 pS

Chapter 9

Field Effect Transistors

361

(mA) 18

vey

4.3\mA
Yop

ay

R 4.7 MO

Using the FET universal transfer characteristic, determine Ip(max) and Vpgiminy for the voltage-

divider bias circuit in Fig. 10-48:

| Ip =

Solution

(EF

From data sheet A-11 in Appendix A, the 2N5458

RI / 5458

has Ipss(max) = 9 mA and Vos(otf(max) = 7 V.

:

Bq. 10-7:

: Ve=

X Rp Vpp

"GR ER,

Ry

X 1MO, 22V

=

1MQ

47M + 1MQ

=3.9V -

_

="

Figure 10-48

When Ves = 0, — Ves/Vescot) = 0

and

Voltage-divider

bias circuit for Ex. 10-13.

IpRs = Vo

Vo

39V

===

°°

ID = —

ace

Ipss_

7

=

27kO

=14mA

= 0.16

9mA

Plot point X on the universal transfer characteristic in Fig. 10-45 at Ip/Ipss = 0.16 When Ves/ Veso

= 0.5,

and

Ve¢s/Vesor) = 0

Ves = 0.5Ves(or) = 0.5 X (—7 V)

=-3.5V From Eq. 10-6,

IpRs = Ve — Ves = 3.9V — (-3.5 V) =74AV

so

_IpRs

Ip = Ip

:

Ipsg

74V

Rs

-O7KQ

2.7mA ss

9mA

|

2

mA

0.3

Plot point Y on the universal transfer characteristic where Ip/Ipss =03

and

Vos/Ves(ots)

= 0.5

Draw the voltage-divider bias line through points X and Y, and where the bias line intersects the universal transfer characteristic, read Ip/ Ipss

giving

=

0.29

Ip = 0.29Ipsg = 0.29 X 9mA = 2.61mA

Chapter 10

—

_FET Biasing

417

Vps = Vpp — Ip(Rp + Rs) = 22V — 2.61 mA(2.7 kQO + 2.7 kQ) =7.9V

i: Riokrsal ‘tasted Sqnin) for the circuit.

avackidugt

to determine Bias and

10-9:2, Using the FET ‘universal transfer characteristic, analyze the circuit in Visi 10-6:to ene ae

V;; Wee = =4. 5 V, and Rp = sc 7 kQ. Use the: FET universal

ens

a _ transfer characteristic to determine Ipimax) and. Vps(min)ae ae

ee

als

Sn

10-10 MOSFET BIASING DMOS Bias Circuits DMOS bias circuits are similar to JFET bias circuits. Any of the FET bias circuits already discussed can be used to produce a negative Vas level for an

n-channel MOSFET or a positive Vag for a p-channel device. In this case, both

devices would be operating in the depletion mode, just like JFETs. To operate an n-channel DMOS

in the enhancement mode, the gate terminal must be

made positive with respect to the source. A p-channel DMOS in the enhancement mode requires the gate to be negative with respect to the source. Consider the four MOSFET bias circuits shown in Fig. 10-49, and assume that each device has the transfer characteristics in Fig. 10-50. In Fig. 10-49a, the OVpp

Rp

:

(a) Zero gate bias

Figure 10-49

(b) Positive bias

Various DMOS bias circuits.

(c) Self-bias

(d) Voltage-divider bias

418

Electronic Devices and Circuits

gate-source bias voltage is zero, so the bias line is drawn vertically on the

transfer characteristics at Vcg = 0, as shown in Fig 10-50. The FET in Fig. 10-49b has a positive gate-source bias voltage; consequently, its bias line must be drawn vertically at Veg = +Vg. The self-bias circuit in Fig. 10-49c has its

bias line drawn from Ip = 0 and Vgg = 0 at a slope determined by Rs, exactly as for a JFET self-bias circuit. Similarly, the bias line for the voltage divider

bias circuit in Fig. 10-49d is drawn from the point where

Ip = 0 and

Vcs = +Vg with a slope set by Rs.

As always, Ipiminy and Ipimax) for any circuit are indicated by the bias line

intersections with the maximum

and minimum

transfer characteristics.

Figure 10-50 shows that in some cases the FET is operating in depletion mode,

and in other cases it is operating in enhancement mode. Analysis and design procedures for these circuits are essentially the same as for similar JFET bias circuits.

MOSFETs can also be used discussed in Section 10-8.

with

a plus/minus

supply

voltage,

as

(mA)

46 t | Biad line

for_

Maximum transfer

|

charact

Fig. 10-49a

391A.

Bias line for

jf

NY

Bias line for

A

|

Minimum tran ser characteristic

~

Fig. L0-49¢

~

[

Fig. 10-49b f4_.

/

ristic

|

yf

yh Ma

L

-6

SL

LT

(V) « -5

-4 _

/

aS

-3 —Ves

Ve

A409

Pe

-2

10-50

Na

Bias line|for

Fig. 10-49d

PS

-1

0

1

2

{

Vo Figure

| NY

3 + Vos

Vo

|

sac

Ps 4

P>—+ 5

(V) 6

—_—__—

Vo

DMOS transfer characteristics and bias lines for the circuits in Fig. 10-49.

EMOS Bias Circuits Enhancement MOSFETs (such as the VMOS and TMOS devices discussed in Section 9-5) must have positive gate-source bias voltages in the case of n-channel devices, and negative Vcs levels for ap-channel FET. Thus, the gate bias circuit in

Fig. 10-49b and the voltage-divider bias circuit in Fig. 10-49d are suitable for EMOS devices. In each case, the bias line is drawn exactly as already discussed.

g FET Biasiniy

ap ter 10 Chap

419

Vp

—

Example 10-14

a

the bias circuit in Determine Ip and Vps for the device has the Fig. 10-51, assuming that Fig. 10-52. transfer characteristic in

Ri 5.6 MQ

|!

Solution

:

_ Vpp X Ra _ 40V X 1MQ 56MO+1MO R,+R, G7

Ry 1MQ

= 6.06V ally on the transfer Draw the bias line vertic . = 6.06 V (see Fig. 10-52) characteristic at Vcs

line intersects From the point where the bias

= Figure 10-51

EMOS gate

bias circuit for Ex. 10-14

the transfer characteristic,

Ip =62

A

Q) 40V — (6.2mA X 4.7 = Rp Ip — p Vp = Vps =109V (A)

204 18-

8.6 A

|

0 6.7V Figure 10-52

s lines. racteristic and bia EMOS transfer cha

f+ (v)

420

Electronic Devices and Circuits

The drain-to-gate bias circuit shown in Fig. 10-53 is uniquely suitable for an

EMOSFET. The FET gate is directly connected to the drain terminal via resistor Rg, so that Ves = Vps. If the drain current is higher than the design level,

a higher voltage drop is produced across Rp. This tends to reduce Ves and thus reduce Ip back toward the design level. Similarly, a lower Ip than intended produces a lower IpRp voltage drop. This results in a higher Vcg, which drives Ip back up toward the desired current. Corresponding levels of Ip and Vgs can be calculated and plotted on the device transfer characteris-

tics to draw the circuit bias line. Vop

Example 10-15

2V

Analyze the bias circuit in Fig. 10-53 to determine the typical levels of Ip and Vpg. Figure 10-52 shows the typical transfer characteristic for the device.

3 DS

Solution When

Ves

ie

=

Vps

=

10 V,

Figure 10-53

Vpp — Vas _ 20V — 10V

a

Ry

EMOS

to-gate bias circuit.

150

drain-

=6.7A

Plot point A on Fig. 10-52 at Veg = 10 Vand Ip = 6.7A When

Ves

= 0,

_Vpp = Ves _ 20V — 0 Ip =

Rp

~

150

=13A Plot point B on Fig. 10-52 at Ves = 0 and Ip = 13 A. Draw the bias line for Rp = 1.5 0 through points A and B. Where the bias line intersects the transfer characteristics,

Ip=86A Vps

= Ves

and

Vgs=67V

=6.7V

Practice Problems

10-10.1 The MOSFET voltage-divider bias circuit in Fig. 10-49d has Vpp= 30 V, Roos 330. kO, Ro=

150 kQ, and Rp= Rs = 680 Q. The FET has

the transfer characteristics in Fig. 10-50. Analyze the circuit to deter-

mine Vpg(miny and Vps(max)-

10-10. 2 A drain-to-gate bias circuit, as in Fig. 10-53, has Vpp = 35 V, and a MOSFET with the transfer characteristics in Fig. 10-52. Calculate an approximate resistance for Rp to give Vps = 5 V.

__

Chapter 10

10-11

FET Biasing

421

BIASING FET SWITCHING CIRCUITS

JFET Switching A field-effect transistor in a switching circuit is normally in an off state with zero drain current, or in an on state with a very small drain-source voltage.

When the FET is off, there is a drain-source leakage current so small that it can almost always be neglected. When the device is on, the drain-source volt-

age drop depends on the channel resistance (7pgjo,)) and the drain current (Ip):

(10-20)

Voston) = Iptps(on)

Field-effect transistors designed specifically for switching applications have very low channel resistances. For example, the 2N4856 has rps(on) = 25 2 (see

data sheet A-12 in Appendix A). With low Ip levels, Vpsion) can be much smaller than the 0.2 V Vcxisat) typical for a BJT. This is an important advantage of a FET switch over a BJT switch.

Direct-Coupled JFET Switching Circuit A direct-coupled JFET switching circuit is shown in Fig. 10-54a, and the circuit waveforms are illustrated in Fig. 10-54b. When V; = 0, the FET gate and source voltages are equal, and there is no depletion region penetration into the channel. The output voltage is now V, = Vpsion), aS expressed by

Eq. 10-20. When Vj exceeds the FET gate-source cutoff voltage, the device is switched off, and the output voltage goes to Vpp, as illustrated.

|

tl lL

Vpp

:

s

Input

{to

_

Vi > Ves(ott)

| *

Vpp

—O

+

Rg V;

he 0

Qi)

4

Output > |

_

Y

D!Ds\on)

reo

Seas

(a) Direct-coupled JFET switch Figure 10-54

\

(b) Circuit waveforms

Direct-coupled JFET switching circuit and the waveform of

the circuit input and output voltages.

Assuming that Vpsion) is very small, the drain current level is determined

from the equation Vpp

as)

IpRp

(10-21)

422

Electronic Devices and Circuits

Equation 10-21 can be used to calculate Rp when Vpp and Ip are specified, or to calculate Ip when

Rp is known.

The Ip level can then be employed

to

determine Vpg(on). The lowest drain current that can be used must be very much greater than the drain-source leakage current specified for the device. To switch the FET off, V; should exceed the maximum gate-source cutoff

voltage. However, V; must not be so large that the drain-gate voltage (Vpg = Vpp + Vi) approaches the breakdown voltage. A rule of thumb is to select the off input voltage 1 V larger than Ves(otfmax)-

The gate resistor (Rg) in the circuit in Fig. 10-54 is provided solely to limit any gate current in the event that the gate-source junctions become forward-bi-

ased. The circuit might operate satisfactorily with an Rg of 1 MQ; however, high-value resistors can slow the switching speed of the circuit. Thus, much smaller resistance values are often used for Rc.

Example 10-16 Design the JFET switching circuit in Fig. 10-54 to have Vpsion) not greater

than 200 mV. A 2N4856 FET is to be used with a 12 V supply. Solution

From data sheet A-12 in Appendix A, rps(on) = 25 2. and Vesiory = 10 V (max) F

eae

Eg. 10-20, ek

Ip

_ Vpsen) _ 200 mV D

=

DS(on)

25 0

=8mA From Eq. 10-21,

Rp &

Vpp _ Ip

12V

= BMA

= 1.5 kO (standard value)

Eq. 10-22:

Vi = —(Vesctmax) + 1 V) = —(10 V + 1 V) =-11V

Capacitor-Coupled JFET Switching Circuits Two capacitor-coupled JFET switching circuits are shown in Fig. 10-55. The FET in Fig. 10-55a is normally on because it has Veg = 0, and the device in Fig. 10-55b is normally off with —Vgs greater than the pinch-off voltage. In both circuits, the FET is switched on or off by a capacitor-coupled input

pulse. The design procedure for these circuits uses the equations already discussed for the direct-coupled JFET switching circuit.

FET Biasing 423

Chapter 10

—_—_—— Vpp

Rp

Cc

|

OVpp

{to C

2)

oy

Y Ves

Rg

Rg O— Ve

(a) Normally-on circuit

Figure 10-55

(b) Normally-off circuit

Normally-on and normally-off capacitor-

coupled JFET switching circuits.

MOSFET Switching

Figure 10-56 shows two capacitor-coupled MOSFET switching circuits. In Fig. 10-56a, the FET is biased off because Vs = 0. A positive-going input

signal is required to turn the device on. The FET in Fig. 10-56b is biased on by the positive Vcg provided by the voltage divider (R; and R2). In this case,

a negative-going

input

voltage

must

be applied

to turn the FET

off.

Equations 10-20 and 10-21 can be applied to these circuits to calculate Ip and Vps(on). To set the device on to a desired level of drain current, the transfer characteristics can be employed for determining Ves if they are available.

Alternatively, Eq. 9-5 can be used to estimate the required gate-source bias voltage, as explained in Section 9-5. To ensure that the FET is off, the gatesource voltage must be driven below the minimum threshold voltage for the device.

Vos

(a) Normally-off circuit Figure

10-56

(b) Normally-on circuit

MOSFET normally-on and normally-off capaci-

tor-coupled switching circuits.

424

Electronic Devices and Circuits

Example 10-17 The MOSFET in the switching circuit in Fig. 10-56b is to be biased on to have the smallest possible Vps(on). Determine suitable resistances for R; and R3, and calculate Vpgion). The device has the transfer characteristics shown in Fig. 10-52, and its drain-source on resistance is 0.25 . Solution

From Eq. 10-21,

i

Vpp

_ 50V =F

=5A

From the transfer characteristics in Fig. 10-52, atIp =5A,

Vos ¥ 5.7 V

Select

Ro = 1MQ

FromEq.10-13,

R, = “= =

nay,

ene = cay si

= 7.7 MQ, (use 6.8 MO, to make Vcs > 5.7 V to ensure that the FET is biased on)

Eg. 10-20:

Vps(on) = Iprps(on) = 5 A X 0.25 0 =1.25V

Practice Problems

_

10-11.1 A normally-off JFET switching circuit, as in Fig. 10-55b, is to use a

2N4861 FET with a 30 V supply, and is to have an Ipgnax) of 10 mA.

Calculate Rp, Vps(ony, and the required Vc level. 10-11.2 The normally-off MOSFET switching circuit in Fig. 10-56a is to be

employed to pass 15 A through a 3 C0) resistor. The device used has the transfer characteristics shown in Fig. 10-52, and rps(on) = 0.2 0.

Calculate approximate levels for the supply and input voltages.

Review Questions Section 10-1 10-1 Identify the components that constitute the de load in a FET bias circuit. Explain the procedure for drawing the dc load line on the FET drain characteristics.

10-2

Explain the selection of a Q-point on a FET dc load line, and discuss the limitations on the output voltage swing.

Chapter 10 _- FET Biasing

-——

425

Section 10-2 10-3

Sketch a gate bias circuit using an n-channel JFET. Identify the polarities of Vpp,

Vos, Vc, and Ves. Show the Ip direction. Briefly explain the circuit operation.

10-4

Repeat Question 10-3 for a gate bias circuit using a p-channel JFET.

10-5

Write equations for Vpsimax) and Vpsimin) for a JFET gate bias circuit.

10-6

State a typical maximum resistance for gate resistor Rg in a gate bias circuit.

10-7

Briefly explain. Explain why the device maximum and minimum should be used in FET bias circuit analysis.

transfer characteristics

Section 10-3 10-8 Sketch a self-bias circuit using an n-channel JFET. Identify the polarities of Vpo; Vos, Vs, Vc, and Ves. Briefly explain the circuit operation. 10-9 Repeat Question 10-8 for a self-bias circuit using a p-channel JFET. 10-10 Write equations for Vps(max) and Vpsmin) for a FET self-bias circuit. Write the

equation used for drawing the circuit bias line on the transfer characteristics. Section 10-4.

|

10-11 Sketch a voltage-divider bias circuit using an n-channel JFET. Identify the po-

larities of Vpp, Vps, Vs, Vc, and Veg. Briefly explain the circuit operation. 10-12 Repeat Question 10-11 for a voltage-divider bias circuit using a p-channel JFET.

10-13 Write equations for Vpsimax) and Vpsimin) for a FET voltage-divider bias circuit.

Write the equation used for drawing the circuit bias line on the transfer characteristics. Section 10-5 10-14 Compare the performance of the three basic JFET bias circuits in terms of the differences between Ipimax) and Ipgmin) in each circuit and the predictability of circuit Q-points. Section

10-6

10-15 Briefly explain the procedure for testing a FET bias circuit. List common errors made when bias circuits are tested.

10-16 List possible errors in a JFET bias circuit with Vp ~ Vpp in the case of (a) gate bias; (b) self-bias, and (c) voltage-divider bias. 10-17 List possible errors in a JFET bias circuit with Vps~ 0 in the case of (a) gate bias,

(b) self-bias, and (c) voltage-divider bias.

Section 10-7 10-18 Write the equation for calculating Rp in a gate bias circuit. 10-19 Explain why the FET maximum drain characteristics should be used when designing a JFET bias circuit.

426

Electronic Devices and Circuits

10-20 Write the equation for calculating Rp and Rs in a JFET self-bias circuit. 10-21 Write the equation for determining Rp, Rs, Ri, and R2 ina JFET voltage-divider bias circuit.

Section 10-8 10-22 Sketch an n-channel JFET voltage-divider bias circuit using a plus/minus sup-

ply. Identify the polarities of Vpp, Vps, Vs, Vc, and Ves. Briefly explain the circuit operation.

10-23 Repeat Question 10-22 for a similar circuit using a p-channel JFET. 10-24

Sketch an n-channel JFET drain feedback bias circuit. Identify all voltage polar-

ities, and explain the circuit operation. 10-25 Repeat Question 10-24 for a drain feedback bias circuit using a p-channel JFET.

10-26 Sketch an n-channel JEET constant-currenf bias circuit using voltage-divider bias at the gate. Identify all voltage polarities and current directions, and explain the circuit operation.

10-27 Repeat Question 10-26 for a constant-current bias circuit using a p-channel JFET. 10-28 Sketch an n-channel JFET constant-current bias circuit using a plus/ minus

supply. Label all voltage polarities and current directions, and explain the circuit operation. 10-29 Repeat Question 10-28 for a constant-current bias circuit using a p-channel

JFET.

Section 10-9 10-30 Write the equation used for constructing a JFET universal transfer characteristic. Briefly explain the universal transfer characteristic and its application.

Section 10-10 10-31 Sketch n-channel DMOS gate bias circuits using (a) Vcs = 0, (b) Ves = +Ve. Identify all voltage polarities and current directions, and explain the operation of each circuit.

10-32 Draw the diagram of a self-bias circuit using an n-channel DMOS transistor. Show all voltage polarities and current directions, and explain the circuit operation.

10-33 Draw a voltage-divider bias circuit using an n-channel DMOSFET. Show all voltage polarities and current directions, and explain the circuit operation. 10-34 Sketch approximate maximum and minimum transfer characteristics for a DMOSFET. On the transfer characteristics, draw typical bias lines for the circuits in Questions 10-31 to 10-33. Briefly explain. 10-35 Draw a circuit diagram for a drain-to-gate bias circuit using an n-channel EMOSEFET. Explain the circuit operation. 10-36 Draw a circuit diagram for a drain-to-gate bias circuit using a p-channel EMOSFET. Explain.

Chapter 10

FET Biasing

427

Section 10-11 10-37 Sketch a circuit diagram for a direct-coupled switching circuit using an nchannel JFET. Sketch input and output waveforms, and explain the circuit

operation. 10-38 Draw circuit diagrams JFET switching circuits. 10-39 Sketch circuit diagrams switching circuits using

for normally-on and normally-off capacitor-coupled Explain the operation of each circuit. for normally-on and normally-off capacitor-coupled EMOSFETs. Explain the operation of each circuit.

Problems Section 10-1

10-1

The circuit in Fig. 10-57 has a JFET with the characteristics in Fig. 10-58. Draw the dc load line for the cir-

10-2

10-3

10-4 10-5

cuit, and select a suitable gate voltage to give the maximum possible symmetrical output voltage swing. Estimate the maximum possible symmetrical output voltage swing for the circuit in Problem 10-1 when Vg = -2V. A JFET circuit like the one in Fig. 10-57 is to have Vps = 10 Vand Ip = 2 mA. If Vpp = 18 V, draw the de load line on the drain characteristics in Fig. 10-58, and determine the required resistance for Rp. Using the drain characteristics in Fig. 10-58, draw the dc load line for the circuit in Fig. 10-59.

Figure 10-57

Determine the Ip and Vps levels for the circuit in Problem 10-4 if the gate-

source voltage is —1.5 V.

(mA)

Ves =0

2

4

6

8

10

12

14

16

18

20 22

(Vv)

Vos Figure 10-58

Figure 10-59

428

10-6

Electronic Devices and Circuits

A JFET circuit as in Fig. 10-57 has Rp = 4.7 kQ.. The

ce

bias conditions are to be Vps = 8 V and Ip = 1.5 mA.

Rp

Draw the dc load line on the drain characteristics in

3.3 kO

Fig. 10-58, and determine a suitable supply voltage.

Ip | e—O

Section 10-2 10-7 The gate bias circuit in Fig. 10-60 has a JFET with the transfer characteristics in Fig. 10-61. Analyze the circuit to calculate Vpg(maxy and Vps(min): 10-8 Repeat Problem 10-7 using Eq. 9-1 instead of the transfer characteristics.

Qi ” 1 MO »,

= iD Vv

Figure 10-60

(mA)

I

/\

ar

An A wv)

-6

-5

-4

-3

-2

-1

|

0

/

18

1

ees View

2

3

4

45

i

6

(v)

o> Figure 10-61

10-9

The JFET used in a gate bias circuit has the transfer characteristics in Fig. 10-61. If Rp = 2.2 kO, Vpp = 20 V, and Vg = —2 V, draw

the bias line and calculate

Vps(max) and Vps(min)10-10 Repeat Problem 10-9 using Eq. 10-8 instead of the transfer characteristics. 10-11 Analyze the circuit in Fig. 10-62 to determine Vpsimax) and Vps(min): Section 10-3 10-12 Determine the maximum and minimum levels of Vps for the JFET self-bias circuit in Fig. 10-63. Assume that the device has the transfer characteristics in Fig. 10-61.

_FET Biasing

Chapter 10

429

> Vp +25 V

Ry 3.3 MQ, O

fe Ry 1MO

Figure 10-62

Figure 10-63

Figure 10-64

10-13 AJFET self-bias circuit (as in Fig. 10-63) has Vpp = 30 V, Rp = 4.7 kQ, Rs = 8200, and Rg = 1 MQ. If the FET is a 2N5457, calculate the minimum level of Vps.

10-14 Recalculate Vpg(min) for the circuit in Problem 10-13 when the device is changed to a 2N5458.

Section 10-4 10-15 Assuming that the JFET in the voltage-divider bias circuit in Fig. 10-64 has the transfer characteristics in Fig. 10-61, determine the maximum and minimum Vpgs levels.

10-16 A JFET

Vpp = 20 V,

voltage-divider bias circuit (as in Fig. 10-64) has

Rp = Rs = 2.7kQ, R; = 7.7 MQ, and R2 = 1 MQ. Using the JFET transfer characteristics in Fig. 10-61, determine the maximum

and minimum

Vps levels.

10-17 A JFET with the transfer characteristics in Fig. 10-61 is connected in a voltagedivider bias circuit with Vpp = 22 V. The circuit components 3.9 kQ, Ri = 7.8 MQ,

and R2 = 1 MQ. Calculate Vps(max) and

are: Rp = Rs =

Vos min):

10-18 A 2N5457 JFET is used in a voltage-divider bias circuit with Vpp = 20 V. The circuit components are: Rp = 4.7 kQ, Rs = 3.9kQ, Ry = 1.2 MO, and R2 =300 kf. Determine Vpsmin):

Section 10-7

10-19 A JFET gate bias circuit is to have Ipmax) = 5.5 mA and Vpgimin) = 7 V. The supply voltage is 25 V, and the FET transfer characteristics are shown in Fig. 10-61.

Determine the required bias voltage and suitable resistor values. 10-20 Design a gate bias circuit using a 2N5457 JFET. The circuit is to. have Ipimax) = 45 mA and Vps(min) = 7-5 V, and the supply voltage is to be 20 V.

430

Electronic Devices and Circuits

10-21 A JFET self-bias circuit is to have Vpp = 25 V, Ip(max) = 2.5 mA, and Vpsmin) = 7 V. Using the FET transfer characteristics shown in Fig. 10-61, design the circuit.

10-22 Design a self-bias circuit using a 2N5457 JFET with Vpp = 20 V, Ip(max) = 2mA, and Vpsimin) = 7.5 V. 10-23

A JFET voltage-divider bias circuit is to have Vpp = 25 V, Ipymax) = 2.5 mA, and

Vps(min) = 7 V. Using the device transfer characteristics shown in Fig. 10-61, design the circuit.

10-24 Design a JFET voltage-divider bias circuit to have Vpp = 20 V, Ipqmax) = 2 mA,

and Vps(min) = 7.5 V. Use a 2N5457 JFET. 10-25 A JFET voltage-divider bias circuit is to have Vpp = 22 V, Ipimax) = 1.5 mA, and Vps¢min) = 9 V. Using the device transfer characteristics in Fig. 10-61, design the circuit.

10-26 A JFET with the device transfer characteristics in Fig. 10-61 is used in a voltagedivider bias circuit with Vpp = 20 V and Rp = 4.7 kQ.. Determine suitable val-

ues for R,, Rz, and Rg to maintain Ip within the limits of 1 mA to 1.3 mA. Section 10-8 10-27 Using the transfer characteristics in Fig. 10-61, design the circuit shown in Fig. 10-65. 10-28 Analyze the circuit designed for Problem 1027. to determine the levels of Vpsimax) and Vps¢nin)-

10-29 A JFET circuit like the one in Fig. 10-65 is to

have the following voltage and current levels: Vpp

=

20 V,

Vg

=

-10 V,

Ip(«max)

=1.5 mA,

and Vpg(nin) = 8 V. Design the circuit to use a 2N5458 JFET. Select suitable standard-value

resistors.

10-30 Analyze the circuit designed for Problem 1029 to determine Vpsmin).

Figure 10-65

10-31 Design the circuit shown in Fig. 10-66 using the JFET transfer characteristics in Fig. 10-37. Select suitable standard-value resistors.

10-32 Analyze the circuit designed for Problem 10-31 to determine Vps(min)-

Vpsimax) and

10-33 A JFET circuit like the one in Fig. 10-66 is to have the following voltage and current levels: Vpp = 22 V, Ip(max) = 1.5 mA, and Vps(min) = 9 V. Design the circuit to use a JFET with the transfer characteristics in Fig. 10-61. Select suitable standard-value resistors.

10-34 Analyze the circuit designed for Problem 10-33 to determine the maximum and minimum levels of Vps.

10-35 Design the JFET circuit shown in Fig. 10-67

Vpp +24 V

using the transfer characteristics in Fig. 10-61. Select suitable standard-value resistors.

Ip

10-36 Analyze the circuit designed for Problem 10-

> | 2.5 mA(max)

35 to determine all voltage and current levels. Section

431

FET Biasing

Chapter 10

oO

rr

10-9

3)

}

8 V(min)

10-37 Use the FET universal transfer characteristic in

Fig. 10-45 to determine Vpsimin) for the gate bias circuit in Fig. 10-62. 10-38 Use the FET universal transfer characteristic in Fig. 10-45 to determine Vpsimin) for the circuit

=

in Fig. 10-63. The actual device transfer characteristics are shown in Fig. 10-61. 10-39 Assuming that a 2N5458 JFET is connected in the voltage-divider bias circuit in Fig. 10-64, determine

Vpsimin)

using

the FET

universal

transfer characteristic in Fig. 10-45. Section 10-10 10-40 The MOSFET in the gate bias circuit in Fig. 10-68 has the transfer characteristics in Fig. 10-69. Draw

the bias line and calculate

Vps(max) and Vos min):

10-41 Using the transfer characteristics in Fig. 10-69, design the MOSFET gate bias circuit shown in Fig. 10-70. Select suitable standard-value resistors.

Figure 10-67

‘

10-42 Analyze the circuit designed for Problem 10-

Vien

41 to determine all voltage and current maxi-

Rp go 20V

mum and minimum levels.

1.5kO

10-43 Design the MOSFET voltage-divider bias circuit shown in Fig. 10-71 using the transfer characteristics in Fig. 10-69. Select suitable standard-value

| ——

resistors.

Ee)

10-44 Analyze the circuit designed for Problem 10-43 to determine all voltage and current maximum and minimum levels. the transfer characteristics in Fig. 10-52, Using 10-45

determine

suitable resistors for the MOSFET

Ro 1MQ

i Figure 10-68

432.

Electronic Devices and Circuits

f

(V)

x

——[ -12

-10 ~+—

-8

-6

(Vv) -4

-2

0

2

4

Ves

6

8

Ves

———-

10

12

Figure 10-69

drain-to-gate bias circuit in Fig. 10-72. Calculate the drain-source voltage.

Section 10-11 10-46 Calculate Vps for the direct-coupled JFET switching circuit in Fig. 10-73 when the FET

is off and when it is on. Data sheet A-12 in Appendix A shows the data sheet for the 2N4861. 10-47 A direct-coupled JFET switching circuit (as in Fig. 10-73) is to be designed to use a 2N4861, and Vpp = 18 V. Vps is not to exceed 100 mV when the device is on. Determine suitable re-

_

Figure 10-70

sistor values and a suitable input voltage amplitude. 10-48 The JFET switching circuit in Fig. 10-74 is to have Vps ~ 50 mV when the de-

vice is on. Select a FET from the 2N4856 to 2N4861 range, calculate appropriate resistor values, and determine a suitable input voltage amplitude. 10-49 The switching circuit in Fig. 10-75 is required to pass 5 A through a 5 1 resistance. Calculate a suitable rpsion) for the device. Determine a suitable input voltage amplitude from the transfer characteristic in Fig. 10-52.

FET Biasing

Chapter 10

433

Figure 10-72

Vpp .

12 V

Rp

e—O

Qi

Rg b ate — =

Figure 10-73

Figure 10-74

10-50 The MOSFET in the switching circuit in Fig. 10-76 has the transfer characteristic in Fig. 10-52 and rpg(on) = 0.2 2. Calculate Vpp 28 V the required drain current and suitable values for resistors R; and R2.

Practice Problem

Rp

50

e—O

Answers

EP)

E

10-1.1 10-1.2 10-2.1 10-2.2 10-3.1 10-4,1 10-7.1 10-7.2

8V £5 V 8.4 V, 17.6 12.7 V 8.8 V, 16.1 V 14 V, 18.7 V —1.7 V, 1 MOQ, 4.7 kQ 1 MQ, 3.9 kQ, 1.5 kO

Ip 5A

tr

o—)

a Re

Figure 10-75

434

Electronic Devices and Circuits

10-7.3 10-8.1 10-8.2 10-8.3 10-9.1 10-9.2 10-9.3 10-10.1 10-10.2 10-11.1 10-11.2

4.7 MQ, 1 MO, 5.6 kQ, 5.6 ko 1 MQ, 3.3 kQ, 8.3 kO 1 MQ, 10 kQ, 5.6 ka (2.2 MQ + 220 kQ), 1 MQ, 2.7 kO, 2.7 kO 12.4V | 10 V 14.1V 9.6 V,12.3V 120 3.3 kQ, 0.6V, -5V 48 V,8.6V Figure

10-76

CHAPTER 11 AC Analysis of FET Circuits 4

4S

Objectives You will be able to:

common-drain, and common-

1 Explain the need for coupling and bypass capacitors in FET

gate circuits.

circuits, and draw ac equivalent circuits for FET circuits

4 Analyze various CS, CD, and CG FET circuits to determine input resistance, output

containing capacitors.

resistance, and voltage gain. 5 Compare the performance of

2 Draw ac load lines for basic FET

CS, CD, and CG circuits, and

circuits.

compare FET and BJT circuits.

3 Sketch ac equivalent circuits for

6 Calculate the cutoff frequencies

various FET common-source,

for FET circuits.

INTRODUCTION Like BJT circuits, FET amplifiers have ac signals capacitor-coupled circuit input, and loads capacitor-coupled to the output terminals. capacitors are also employed both in FET and BJT circuits to maximum. ac voltage gains. Because of the ac-coupled load and

to the Bypass ensure the ac-

bypassed components, the ac load for a given circuit is different from the de

load; consequently, the ac load line is different from the dc load line. There are three basic FET circuit configurations: common-source, common-drain, and common-gate. emitter,

common-collector,

and

These are similar to the BJT common-

common-base

circuits,

respectively.

The

common-source circuit is capable of voltage amplification, and it has a high input impedance. The common-drain circuit is a buffer amplifier, with a voltage gain of approximately one, high input impedance, and low output impedance. The common-gate circuit has voltage gain, low input impedance,

and good high-frequency performance.

436

Electronic Devices and Circuits

11-1

COUPLING, BYPASSING, AND AC LOAD LINES

Coupling Capacitors | This subject is treated for BJT circuits in Section 6-1, and the discussion there applies equally to FET circuits. As explained, coupling capacitors are required at a circuit input to couple a signal source to the circuit without affecting the bias conditions. Similarly, loads are capacitor-coupled to the circuit output to

avoid the change in bias conditions produced by direct coupling. Input and output coupling capacitors (C; and C3) are shown in the FET circuit in Fig. 11-1. Vop Coupling

capacitor

Coupling

= R

~—

capacitor aP

Bypass capacitor Figure 11-1

FET circuit with coupling

and bypass capacitors.

Bypassing Capacitors Bypass capacitors are also just as necessary in FET circuits as in BJT circuits.

Bypass capacitor C) in Fig. 11-1 provides an ac short-circuit across resistor Rs. As will be shown, if C2 is not present, Rs substantially reduces the ac voltage gain of the circuit. | OVpp Figure 11-2 illustrates another situation where bypassing capacitor is required. The MOSFET drainto-gate bias circuit shown would have its voltage

gain reduced by feedback from the drain to the gate via Rg (ac degeneration) if capacitor C2 were not present. The feedback is eliminated by splitting Rg into two equal resistors and ac shorting the junction to ground via C2.

=

AC Load Lines

Once again, this is a subject that applies equally to ah

cea

‘

f

BJT and FET circuits (see Section 6-2). The de load for the FET circuit in Fig. 11-1 is (Rp + Rs). With Rs

Figure 11-2

MOSFET

circuit with bypass

Capatiterte eliminate ac degeneration.

ac-bypassed and R;, absent, the ac load is Rp. With the capacitor-coupled load present in Fig. 11-1, the ac load is Rp||Ry. The dc load line is drawn in the usual way, and the Q-point is marked;

then the ac load

through the Q-point, as shown in Fig. 11-3.

line is drawn

AC Analysis of FET Circuits

Chapter 11

-

12

Figure

11-3

437

14

FET circuit dc and ac load lines.

Yop y

Example 11-1 Draw the de and ac load lines for the transistor circuit in Fig. 11-4 using the FET drain

a 1.5

characteristics in Fig. 11-3, and identifying the

Ip} ©

Q-point current as Ip =2 mA.

°) 1

Solution DC load line:

Re 1MQaS

Rude) = Rp + Rg = 1.5 kO + 1.5kO

Figure

The equation for Vps is

Vps = Vpp — Ip (Rp + Rs) Ip =

0,

Plot point A at

Vps =

Vpp

=

Ip = 0 and

18 V

Vps = 18 V

Vpp

When Vos = 0,

D> RO + Rs

_

18V

3kO

=6mA

Plot point B at

Cs =

=3kO

When

Rs 15k0

= 0 Ip = 6mAand Vps

Draw the dc load line through points A and B.

Mark the Q-point on the dc load line at Ip = 2 mA.

11-4 Circuit for Ex 11 -1.

438

Electronic Devices and Circuits

AC load line: Ric) = Rp = 1.5 kO (when Rs is bypassed)

When Ip changes 2 mA, AVps= Alp X Rp. = 2mA

X 1.5 kO

=3V Plot point C at

Alp = 2mA and AVps = 3 V from the Q-point.

Draw the ac load line through points C and Q.

Practice | roblem

11-1.1 In the circuit in Fig 141, Toe= 2.2kQ, Rs = 1.8 kO, Ry = 15 kO, and -Vpp= 20'V. Determine the de and ac load resistances, and draw both load lines on the characteristic in Fig 11-3. Assume that the Q-point is -drain current is 2.5.mA.

11-2

FET MODELS AND PARAMETERS

FET Equivalent Circuit The complete equivalent circuit for a field effect transistor is shown It is seen that the source terminal is common to both input Therefore this is a common-source equivalent circuit. Resistor Rgs gate and source terminals is the resistance of the reverse-biased

in Fig. 11-5a. and output. between the gate-source

junction, and C,, is the junction capacitance. So a signal applied to the input ‘sees’ Reg in parallel with C,..

The output stage of the equivalent circuit is represented as a current source (Ys Ugs) supplying current to the drain resistance (rg). Since Y;, is the forward

transfer admittance for the FET, and v,, is the ac signal voltage developed

Sts Cc gd

8

Ig

7T

{

gs « Cog al Ss

Vf,

Res

Ugs

|

"4 :

$40

“A Iq

Ye

i

(a) Complete equivalent circuit

Figure 11-5

g %gs < Res S

o—

Ugs

"d $—o

S

S

(b) Low-frequency and mediumfrequency equivalent circuit

The complete equivalent circuit for a FET includes capacitances between

terminals. For low- and medium-frequency operations, the capacitances are omitted.

Chapter 11 = AC Analysis of FET Circuits

meetin

439

across the gate-source terminals, the ac drain current is (Y¢s Ugs). The drain-

source capacitance (Cy.) appears in parallel with rg, and the gate-drain capacitance (C,q) is shown connected between the input and output stages. For low- and medium-frequency operations the capacitances can be neglected, and the equivalent circuit is then as shown in Fig. 11-5b. This is the FET model (or equivalent circuit) normally used in ac circuit analysis.

Equivalent Circuit Parameters The parameters used in the equivalent circuit are discussed in Section 9-3. As explained above, Rgg is a junction reverse resistance with a 10’ O typical value for a JFET. Because its resistance is so high, Rcg is often regarded as an open circuit. Instead of Rcs being listed on a device data sheet, the gate-

source reverse current is usually specified, and a value for Res can be calculated from this quantity. The forward transfer admittance (Yj, or gj) varies widely for different types of FET. For a small-signal or switching JFET, Y‘, typically ranges from 1000 xS to 5000 wS. For an EMOSFET, Y;, might be 2.9 S. The drain resistance (rg) shown in the equivalent circuit is the ac resistance offered between the drain and source terminals of the FET when operating in the pinch-off region of the drain characteristics. This quantity is usually defined in terms of an output admittance (Y.s) which equals Li Pas

Typical values of rg range from 20 kQ to 100 kO for a JFET.

ent

y all components, list typical component values, and briefly

ES » explain how the equivalent circuit represents the device.

CIRCUIT

11-3 COMMON-SOURCE ANALYSIS

Common-Source Circuit The circuit of a FET common-source amplifier is shown in Fig. 11-6. With the capacitors treated

as

ac

short-circuits,

the

circuit

input

terminals are the gate and source, and the output terminals are the drain and the source.

So the source terminal is common to both input

Figure 11-6

= FET common-

SONS AIP RTSE CHOU

and output, and the circuit configuration is known as common-source (CS). The current and voltage waveforms for the

CS circuit in Fig. 11-6 are illustrated in Fig. 11-7.

Electronic Devices and Circuits

increases the FET gate-source voltage (Vas), thus raising the level of Ip and increasing the voltage drop across Rp. This produces a decrease in the level of the drain voltage (Vp), which is capacitor-coupled to the circuit output as

v, {\_ J 2cinput »

A

The 180° phase shift between the input and output waveforms can be understood by considering the effect of a positive-going input signal. An increase in Vs

ccm

440

() =, 4-4-4~Vv

a negative-going ac output voltage (vo). Consequently,

negative direction, as illustrated. Conversely, when vs; changes in a negative direction, the resultant decrease in

Ves reduces Ip and produces a positive-going output.

=

as Us increases in a positive direction, vo changes in a

09 aoa

Vp

J

The circuit in Fig. 11-6 has an input impedance (Z;), an

output impedance (Z,), anda voltage gain (Ay). Equations

oe

for these quantities can be determined by ac analysis of (\

the circuit.

Common-Source Equivalent Circuit The first step in ac analysis of a FET (or BJT) circuit is to draw the ac equivalent circuit, by substituting ac shortcircuits in place of the power supply and capacitors. When

aL

this is done for the circuit in Fig. 11-6, the ac

equivalent circuit shown in Fig. 11-8a is created. For ac

% |-4-- Soniye aa \ Figure 11-7 Voltage and

Surent

analysis, the FET equivalent circuit (from Fig. 11-5b) is eS eeee common-source now substituted. in place of the device. This results in circuit. the CS ac equivalent circuit in Fig. 11-8b. The current directions and voltage polarities in Fig. 11-8b are those that occur when the instantaneous level of the input voltage is moving in a positive direction.

Input Impedance Considering the input section of the equivalent circuit in Fig. 11-8b we can see that the input impedance at the FET terminals is

2g

= Res

(11-1)

Recall that a typical value of R,, for a low-current JFET is 10° ©. At the circuit input terminals, resistors R; and R2 are seen to be in parallel with Z,. So the circuit input impedance is

Zi = Ril[RallZ,

(11-2)

441

AC Analysis of FET Circuits

Chapter 11

_—

—e —=

(a) ac equivalent circuit for FET CS circuit

FET equivalent circuit

7

Se

: Ry

Is

%4 Ds

Ry

2 —

Zs, oe

Yés 0gs

A

Rg.

fr

pats

=

BD

Eee

R

Rp

re

7%

Jo

os,

Bt

+

S (b) Substitution of the FET equivalent circuit into the CS ac equivalent circuit

Figure 11-8

A common-source ac equivalent circuit is drawn by first replacing the power

of supply and all capacitors with short-circuits. Then the FET model is substituted in place

the device.

is almost

always

Secs

Because Z, is so large, the circuit input impedance determined by the bias resistors.

(11-3)

—

me

Zi = Ryl|Ro So the input impedance

of a FET circuit can usually be determined simply by

calculating the equivalent resistance of the bias resistors. However, as already pointed out, very high input resistance is one of the most important properties of a FET. When it is necessary to achieve the highest possible input resistance, the signal source may be directly connected in series with the gate terminal, and in this case Zj ~ Z,.

In the case of the self-biased circuit in Fig. 11-4, the circuit input impedance is equal to the gate bias resistor Kg. Output Impedance

‘Looking into’ the output of the CS equivalent circuit in Fig. 11-8b, the output impedance at the FET drain terminal is

Za =a

(11-4)

At the circuit output terminals, resistor Rp is in parallel with Zg. So the circuit

output impedance is

Zo = Rpllra

(11-5)

442

Electronic Devices and Circuits

Because rq is usually 100 kQ, and Rp is usually much lower than 50 kQ), the

circuit

output

impedance

is approximately

equal

to

Rp.

With: this

information, the output impedance of a CS circuit can be discovered simply

by reading the resistance of Rp.

Ze XoRp

(11-6)

Voltage Gain Amplifier voltage gain is given by the equation

A ax a From Fig. 11-8b, and sO

Uo = Iq (ral|Rp||Rx) Ig = —Yfp 0;

-Y%50i(rall Rp | Rx) Ay = —-— Oj

or

Ay = —Y¢(rall Rp|| Ri)

(11-7)

The minus sign in Eq. 11-7 indicates that v, is 180° out of phase with v;. (When

dj increases, Vp decreases, and vice versa.) It is seen that the voltage gain of a common source amplifier is directly proportional to the Y;, of the FET. If the appropriate Y;, value and the resistance of Rp and Ry, are known, the voltage gain of a CS circuit can be quickly estimated. For Y;, = 5000 pS and Rp = 4.7 kQ, and with Ry >> Rp and rg >> Rp, the voltage gain is —23.5.

The voltage gain of a FET common-source amplifier is typically about one-tenth of the gain of a BJT common-emitter circuit. Low voltage gain, caused by the low Yj, value, is the major disadvantage of JFET circuits compared to BJT circuits. The same is generally true of MOSFET circuits,

except for EMOSFET devices (VMOS and TMOS), which have much larger Y¢s values. However, EMOSFETs use relatively large drain currents, and they are normally unsuitable for small-signal applications.

Summary of Typical CS Circuit Performance Device input impedance

Z, = Rg,

Circuit inputimpedance

—_Zj = Rj ||R2||Z,~ Ri||Ro

Device output impedance

Za = Trg

Circuit output impedance

Z, = Rp||ra* Rp

Circuit voltage gain

Ay = ~Y¢(ra||Rp||Rx)

Chapter 11 = AC Analysis of FET Circuits

—e

443

The common-source circuit has voltage gain, 180° phase shift, high input impedance, and relatively high output impedance.

Example 11-2 Using the FET typical parameters, calculate the input impedance, output impedance, and voltage gain for the common-source circuit in Fig. 11-9.

Figure 11-9

Circuit for Ex. 11-2.

Solution From the 2N5457 data sheet,

os

and Eq. 11-3: Eq. 11-5: Eg. 11-7:

Le

= 100 kO Yfs = 3000 pS Z;, = Ry||Ro = 1 MQ||5.6 MO = 848 kO Zo = Rp||ra = 2.7 kQ||100 kO = 2.63 kO Ay = —Y¢(ra||Rp|| RL) = —3000 pS (100 kQ||2.7 kQ)

= -79 Practice Problems 11-3.1 Calculate

the typical

input impedance,

output

impedance,

and

_,, _ Voltage gain for the circuit in Fig. 11-4 if the FET is a 2N5458. 11-3.2 A circuit similar to the one in Fig. 11-4 has Rg= 470 kQ, Rp = 3.9 kQ, and a 2N5457 FET. Determine the typical input impedance, output _ impedance, and voltage gain for the circuit.

444

Electronic Devices and Circuits

11-4 CS CIRCUIT WITH UNBYPASSED

SOURCE RESISTOR

Equivalent Circuit When an unbypassed source resistor (Rs) is present ina FET common-source

circuit, as shown in Fig. 11-10a, it also appears in the ac equivalent circuit (Fig. 11-10b). In the complete equivalent circuit, Rs must be shown connected

between the FET source terminal and the circuit common input-output terminal (Fig. 11-11). As with the previous equivalent circuit, the current directions and voltage polarities shown in Fig. 11-11 are those that occur when the instantaneous input voltage is positive-going. The presence of Rg

without a bypass capacitor significantly affects the circuit voltage gain.

: (a) Circuit with unbypassed Rg

+

(b) ac equivalent circuit

Figure 11-10 FET common-source circuit with unbypassed source resistor and ac equivalent circuit. I

Figure 11-11

An unbypassed source resistor in a FET circuit must be included in the

complete ac equivalent circuit.

Input Impedance An equation for the input impedance at the FET gate can be determined from vy; and I,. From Fig. 11-11, Uj = Ugs+ Ig Rg = gs + YisgsRs = Ugs(1 + YiRs)

Chapter 11

AC Analysis of FET Circuits

445

Vv

an d

I, — Res

-

Zs

_

Oo

» _

Oodl gs(

I, or

+ Yar fs s)

Ugs/ Res

Ze = Res (1 + Y‘eRs)

(11-8)

Equation 11-8 gives the input impedance at the FET gate terminal. The circuit input impedance is again given by Eq. 11-2: Zi = Ry||Rol|Z,

In this case, since Z, is much larger than R;||R», the circuit input impedance is determined by the gate bias resistors.

Eq. 11-3:

Zi

Ri||Ro

Output Impedance To calculate the circuit output impedance, the ac signal voltage (Vs) is assumed to be zero, and an ac voltage (v,) is applied at the output (see Fig. 11-12a). The ac output current (Iq) is calculated in terms of Vo; then Zo is

determined as v, divided by Ig. Figure 11-12a shows that when 4, is zero, the ac voltage across source resistor Rs is applied as a gate-source voltage: Ugs

= IgRs

Actually, IgRs is divided across rg | | Rgand R,,. However, Rgs > 1s ||Rc, so that

all of IgRs is effectively applied as a gate-source voltage. The v,, produced in this way generates an ac drain current which opposes the drain current

produced by vo, [=

—Yg0gs

= —Y¢(IaRs)

Uo

(a) Circuit output stage with input shorted

Figure 11-12

(b) Current source replaced with a voltage source

Analysis of the output impedance of a common-source circuit with an

unbypassed source resistor.

446

Electronic Devices and Circuits

Converting the current generator (Yj¥g. in parallel with ra) ta voltage generator (Y;,0,.rq in series with rg) gives the equivalent circuit in Fig. 11-12b,

The equation for the voltage drops around this circuit is la(ra + Rs)

giving

=p

— (Yts Ig Rs Ta)

Up = Ia(tg + Rg + YisRsra)

and

Za = a = tq + Rg + YRsra d

or

Za = tq + Rg + YeeRsra

(11-9)

The circuit output impedance is

Eq. 11-5:

Zo = Rp||Za

Because the output impedance at the FET drain terminal is much larger than the drain resistor (Rp), the output unbypassed source resistor is still Eq.

11-6:

impedance

of

the

circuit

with

the

Ls yy Rp

Voltage Gain From the derivation of the input impedance equation, Uj = Ugs(1 + YsRs) Neglecting rq,

0 = Ia(Rp|| Rt) = —Yis0g5(Rv|| Rx) Vo

so

Ay = = Oj

ivi

SIVINE

Usually,

so

~ Y¢s0gs(Rp| [Rr)

= — Ugs(1

+ Y¢5Rs)

—Y¢(RpllRx)

Ao

enya eT

1+

Y¢Rs

11-10)

YsRg >> 1

~(Rpl|R

Ay = aRelo

(11-11)

The voltage gain of a FET common-source circuit with an unbypassed source resistor can be quickly estimated from Eq. 11-11. For the circuit in Fi g. 11-10a with Rp = 4.7 kO, Rs = 2.2 kO, and Ry >> Rp, Ap¥ —2.1.

Chapter 11

AC Analysis of FET Circuits

447

Summary of Performance of CS Circuit with Unbypassed Rs Device input impedance

Z,=R,,(1 + Y¢Rs)

Circuitinput impedance

Zj = Rg||Z,~ Ri ||Ro

Circuit output impedance

Z,.~Rp

iti voltage ga Circu i

in

A

i

—Y¢( is Rp||Rr)

»

ass ge ee

—(Rpj||R © e Aym s

Circuit voltage gain

The most significant feature of the performance of a CS circuit with an unbypassed source resistor is that its voltage gain is much lower than that for aCS circuit with Rs bypassed. Example 11-3 For the common-source circuit in Fig. 11-13, calculate the gate input impedance, the drain output impedance, the circuit input and output impedances, and the voltage gain. Use the typical parameters for the FET. Vpp +25 V

Rp 4.7

QO,

C;

Cy

2N 2)

5458

R,

°s

33k

Re 1MQ

Rs

's

3.3kO

aL Figure 11-13

Circuit for Ex. 11-3.

Solution From the 2N5458 data sheet,

fq = —

D

1

Fise

= 100k0

Yi = 4000 pS and So

Ig =1nA_ Res

a

Ves we Ig

when Veg = 15V EN15V

1nA

=15x10°0

448

Electronic Devices and Circuits

Eq. 11-8:

Zg = Res(1 + 'YisRs) = 15 X 10° O1 + (4mS x 3.3kM)] = 2.13 10"

From Eq. 11-3,

Zi = Rg = 1M

Eq. 11-9:

Za = tat Rg + (YisRsra)

= 100kO + 3.3k0 + (4mS x 3.3kO x 100 kQ) ~1.4MO,

Eq. 11-5:

Zo = Rp||Za= 4.7 kO||1.4 MO = 4.68 kO

=

2 Ys (Rp||Ri) Ao 1+ Y;.Rs 1 + (4mS X 3.3 kQ) = -1.16 —(Rp|[Rt) 4.7 kQ||33 ko ap Rs 3.3 kO = —1.24

. 11-10;

E

=

< 1

-]1:

y

=

arin!

: Practice Problem: UR OE T1-4.1 Calculate the gate input

pedis drain output impedance, circuit

input and output impedance, and voltage gain for the circuit in Fig. 11-4

when the. source

pe

cap citor i is removed. Assume that the FET is

a QN5458 5: a. | 11-4.2 Determine ‘the items listed in . Problem 11-4.1 for the circuit in _ Fig. 119 when the s source ‘bypass capacitor is removed.

~°Ypo

( |

R,

Rg aa

Figure 11-14

in Fig.

11-14 has the output voltage developed across the source resistor (Rs). The external load (Ri)

co R,

CIRCUIT

Common-Drain Circuit The FET common-drain circuit shown

Q;

Nel” =

44-5 COMMON-DRAIN ANALYSIS

= Common-drain

is capacitor-coupled to the source terminal of the FET, and the gate bias voltage (Vg) is

derived from Vpp by means of voltage-divider resistors R; and Ro. No resistor is connected in series with the drain terminal, and no source

circuit, also called a source follower. The ac input is

invpassxaiacifor: 1 PPase hepaneens ENub

the output is taken fromthe sours semnnay.

Fig. 11-14, note that the dc gate volta ge (Vc) isa constant quantity and that the source voltage is

applied to the FET gate, and

a

ed.

;

To understand the operation of the circuit in

Vs=Vot Ves

Chapter 11

AC Analysis of FET Circuits

449

—_

When an ac signal is applied to the gate via capacitor C;, the gate voltage is increased and. decreased as the instantaneous level of the signal voltage rises and falls. Also, Vcs remains substantially constant, so the source voltage increases and decreases with the gate voltage. (See the waveforms in Fig. 11-15.) Thus, the ac

output voltage is closely equal to the ac input voltage, and the circuit can be said to have unity gain. AC analysis of the circuit shows that vp is slightly smaller than v;. Because the output voltage at the source terminal follows the signal voltage at

the gate, the common-drain circuit is also known as a source follower. Common-Drain Equivalent Circuit As in the case of other circuits, the supply voltage and

a ftps rr)

coupling capacitors in Fig. 11-14 must be replaced with

° |” (+

short-circuits performance.

in order to study the circuit This gives the common-drain

ac ac

} “c Ty yi

equivalent circuit in Fig. 11-16a. The input terminals of the ac equivalent circuit are seen to be the FET gate and drain, and the output terminals are the source and drain.

%s {4-3 -

Because the drain terminal is common to both input and output,

the

circuit .

°

configuration *

is named

.

common-

.

_

an

drain (CD). The complete CD ac equivalent circuit is drawn by substituting the FET model into the ac equivalent circuit (Fig.

11-16b).

The

voltage polarities

indicated

are, once

current

again,

directions

those

that

and

are

produced by a positive-going signal voltage. LA

~

°

= , -Y_ o

_|acoutput Y

Figure 11-15 Voltage waveforms in a common-drain

circuit.

b

Qy Re

R, | Ry

“&

V.

=%

(a) ac equivalent circuit for FET CD circuit

FET equivalent circuit gs lg

m——

+

*% 4) Zic>

Rik

G

Ro

20>

0)

—

A

‘

*

Rs Y fs Ups

CG) w=

Rg

+

(Rg ||r,), effectively all of v is applied as an

ac gate-source voltage. Therefore, I; = YtsVo an

d

Zep = 2 = — 2

or

Log

and

Es =

se

YU

11-17)

1g.

-

6

1/Ye

Zn = Zeal lra

Therefore Equation

(ge Fig.

SS

6

= (1/55) lta 11-13

gives

the device

output

(11-13)

impedance.

The

circuit

output

impedance also involves Rs.

Zo = (1/Y¢)||Rs|lra

r.I|Re =

Yps%ps(4)

>

Zs

ee

Vy

eo

Lia

a

~

o

Zi

Yo

_

Rgs

=

ps

+

G

>

(b) Complete common-gate ac equivalent circuit Figure 11-21 A common-gate ac equivalent circuit is drawn by first replacing the power supply and all capacitors with short-circuits; then

a

ee

the FET model is substituted for the device.

Ry

454

Electronic Devices and Circuits

circuit are seen to be the FET source and gate, and the output terminals are

the drain and gate. Since the gate terminal is common to both input and output, the circuit is named common-gate. The complete CG ac equivalent circuit is drawn by substituting the FET model into the ac equivalent circuit (Fig. 11-21b). As always, the current directions and voltage polarities indicated are those produced by a positivegoing signal voltage.

Input Impedance ‘Looking into’ the source and

gate

terminals of

the CG circuit in Fig. 11-21b is similar to ‘looking into’ the output of a common-drain circuit, Therefore, the equation for the common-gate device input impedance (Z;) is derived in the same way as the equation for Z, in the commonFigure 11-22

Because a

drain circuit.

common-gate circuit

ha as low

input

|

impedance, some of

Ze = 1/Y%

(11-17)

the signal voltage is

lost when it is divided

across r, and Z;.

So

The circuit input impedance is Rs in parallel with

the device input impedance.

Z = 0/5) | Rs

(11-18)

With a typical Y;, of 5000 pS, the input impedance of a common-gate circuit is around 200 ©. Low input impedance is the major disadvantage of the common-gate circuit, because the signal voltage is divided across r; and Z; (see Fig. 11-22). (11-19)

Output Impedance The output of a common-gate circuit is taken from the drain terminal, as in the case of a common-source circuit. So the common-gate output impedance is the same as the common-source output impedance. At the drain terminal: Eq. 11-4:

Za = tq

and the circuit output impedance is given by

Eq. 11-5:

Zo = Rp||ra

Voltage Gain From Fig. 11-21b,

U = Ia(Rp||Rt) = Yg0;(Ro|| Rr)

Chapter 11

and

Ay =

or

Ay =

AC Analysis of FET Circuits

455

Yq _ Ytsvi(Rp Il Rr) Oj

Oj (11-20)

Y(Rp|| Ry)

Equation 11-20 is similar to Eq. 11-7 for the voltage gain of a common-source circuit, except that there is no minus sign in Eq. 11-20. So the voltage gain for a common-gate circuit is the same as the voltage gain for a common-source circuit with the same component values. As already discussed, there is no phase shift between the input and output of a common-gate circuit; hence the

absence of the minus sign in Eq. 11-20.

Qi

Effect of Unbypassed Gate Resistors If capacitor C; is not present in the CG circuit in

°

Rs

Fig. 11-19, the FET gate is not ac-short-circuited to 2, @

Rp

nS

Res

ground. So a resistance (Rg = Rj||Rz) must be included in the ac equivalent circuit (see Fig. 11-23)

=

and in the complete CG ac equivalent circuit. The Figure 11-23 When the gate _ presence’ of the unbypassed gate resistors affects the circuit input impedance and voltage gain.

ae tie sivalent m resistance of the gate bias

Analysis of the equivalent circuit shows that

resistors (Rg) must be

:

oe o

a2 yk

and that Bete f 4v ~~

Re

included for circuit analysis.

+

(11-21)

Res

. (11-22)

(Rp||R L) pape Re + Res

4 fs\4ND

When R,, >> Rg (which is usually the case), Eq.

11-21 gives Zi = 1/Y{, and Eq. 11-22 gives Ay = Y;(Rp||Ri), which are the equations for a CG circuit with the gate bypassed to ground. The Z; and A, effects occur only in situations where very high-value bias resistors are used in a CG

bo

circuit. Figure 11-24 shows a CG circuit that uses self-bias. In this case, Rc is omitted because there

is no signal applied at the gate input; the gate is 11-24 =A commondirectly grounded and no gate bypass capacitor Figure gate circuit that uses self‘

aed

is required.

bias can have its gate directly grounded.

456

Electronic Devices and Circuits

Summary of CG Circuit Performance With the gate bypassed to ground: Device inputimpedance

Z,=1/Y¢%

Circuit input impedance

Z; = (1/Y¢)||Rs

Device outputimpedance

Zg= Trg

Circuit output impedance

Z, = Rp|lra

Circuit voltage gain With the gate unbypassed:

Ay = Y5 (Rp ||Rx)

Circuit inputimpedance

Z; = (1/Y¢,)

out Rg

+ Rgs

RR gs

Fath Circuit voltage gain

gs Ay = Y¢5(Rp|| Rr) Re + Ry

A common-gate circuit has a voltage gain, no phase shift between input and output, low input impedance, and relatively high output impedance.

Example 11-5 The common-gate circuit in Fig. 11-24 has a FET with Y;, = 3000 wS and r, =

50 kO. Determine the device and circuit input and output impedances, and the circuit voltage gain. Calculate the overall voltage gain if the signal source impedance is r, = 600 0.

Solution

Eq. 11-17:

Zs = 1/Y = 1/3000 pS = 333.0

Eq. 11-18:

Zi = (1/Y%)||Rs = 333 0||3.3 kO

= 302.0

Eq. 11-4:

Za = tq = 50kO

Eq. 11-5:

Zo = Rp||ra = 4.7 kQ||50 ko

Eq. 11-20:

= 43k | Av = Ys(Rp||Rt) = 3000 pS X (4.7 kQ||50 kQ) = 129

If Eqs 11-19 and 11-20 are combined, the overall voltage gain is

igs Y¢s(Rp|| Rr)Z; i.

Pt = 4.3

+Z

129 * 302.0

6002 + 302 0

AC Analysis of FET Circuits 457

Chapter 11 BS A

I

GS

ir i

we

n Fig. ‘1-19 has the following components: 10, Rp

= 33

KO,

Rg = 1.5

kQ,

and

Ree

be 5 m8 and tae2170 ko, and the signal source

ae voltage gain, and the bite

voltage gain.

aan 11-6. 1 has Rg, = 10 MO, determine the circuit

11-7 COMPARISON

OF FET AND BJT CIRCUITS

CS, CD, and CG Circuit Comparison Table 11-1 compares Z;, Z,, and A, for CS, CD, and CG circuits. The CS circuit has voltage gain, high input impedance, high output impedance, and a 180° phase shift from input to output. The CD circuit has high input impedance, low output impedance, a voltage gain of approximately 1, and no phase shift. Table 11-1

Comparison of Common-source, Common-drain, and Common-gate Circuits Z

Zo.

Ay

Phase. Shift

cs

Ro

Rp

—Ys(RollRx)

180°

CG

=1/Y¢,

—_-Yg(RpilRu)

0

=Rp

The CG circuit offers low input impedance, high output impedance, voltage gain, and no phase shift. Impedance at the FET Gate Consideration of each type of circuit shows that the input or output impedance depends upon

which

device

terminal

is involved.

In

both the CS and CD circuits, the input signal is applied to the FET gate terminal, and so Z; is

the impedance when ‘looking into’ the gate.

Figure 11-25 shows that for CS and CD circuits

the gate input impedance is

and the circuit input impedance is

Figure 11-25

FET circuit

impedance at the gate

4i= Re||Res

terminal.

458

Electronic Devices and Circuits

where Rg is the equivalent resistance of the bias resistors. Because the reverse-biased gate-source resistance (Rgs) is so large, an unbypassed source resistor has no significant effect on Z; at the gate. The circuit input impedance

is largely determined by Rg in both the CS and CD circuits. Zi* Ro = R,||Rz (in the case of voltage-divider bias)

impedance at the FET Source

(Fe

The FET source is the output terminal for a CD circuit and the input terminal for a CG circuit. The device impedance in each case is the impedance seen on looking into the source (see

4 OZ

=(1/Yg) I R

Rs

Fig. 11-26):

Z,=s=

1.

1/Ye

The circuit impedance at the source terminal must include the source resistor:

Figure 11-26 FET circuit impedance at the source

terminal.

OV,

Zor Zo = (1/Ys)||Rs

“

Rp

Impedance at the FET Drain The output for CS and CG circuits is produced at the FET drain terminal. So the impedance seen when looking into the drain is the device output impedance (ra). As

illustrated

in Fig.

11-27, the circuit output

impedance for any circuit with the output taken from the FET drain terminal is

> Voz, Vg will be only slightly affected

by any variation

in Vpg

(due to temperature change or other effects).

Consequently, Ig and Ic remain fairly stable at Ic ~ Ip = Ve /Rz. A minimum Vg of 5 V gives good bias stability in most circumstances (see Fig. 12-2a). With

supply voltages less than 10 V, Vz might have to be reduced to 3 V to allow for reasonable levels of Vcg and Vrc. Normally, an emitter-resistor voltage drop

less than 3 V is likely to produce poor bias stability. Once Vx, Vcr, and Ic are selected, Vac is determined: Vac = Vee — Vez — Ve Then, Rc and Rx are calculated: V Rc = —RE Ie

and

V Rg & —* Ic

(see Fig. 12-2b)

Bias Resistors As explained in Section 5-7, selection of the voltage divider current (Iz) as

Ic/10 gives good bias stability and reasonably high input resistance. Where the input resistance is not important, I, may be made equal to Ic for excellent

bias stability. The bias resistors are calculated as follows: . Vcc — Va

472

Electronic Devices and Circuits

|

Selecting R2 = 10Rg gives Ip ~ Ic/10 (Fig. 12-2b). The precise level of Iz can be

calculated as Ip = Vg/R», and this can be used in the equation for R;.

Bypass Capacitor All capacitors should be selected to have the smallest possible capacitance

value, both to minimize the physical size of the circuit and for economy (large capacitors are the most expensive). Because each capacitor has its highest impedance at the lowest operating frequency, the capacitor values are

calculated at the lowest signal frequency that the circuit is required to amplify.

This frequency is the circuit lower cutoff frequency, or low 3 dB frequency (fi) (see Fig. 12-3).

Bypass capacitor C2 in Fig. 12-1 is normally the largest capacitor in the circuit because it has the smallest resistance in series with it (rz) (see Section

8-4). So C2 is selected to set f; at the desired frequency. Equation 6-21 (for voltage gain) was developed for a CE circuit with an unbypassed emitter resistor (Rx). Rewriting the equation to include X; in parallel with Rg gives

7

—hge(Re|| Rt)

v

hie

10

20

40

100

200

+

400

(1

et he)(Rx|| Xco)

1k

2k

4k

10k

fark

|

f, 1

t

Norimally selected by

emitter bypass capacitor Figure 12-3

Typical frequency response for a transistor amplifier.

20k

40k

f f. 2

100k

(Hz)

Chapter 12

—

Small-Signal Amplifiers

473

Since normally Re >> X~, Rg can be omitted. Also, Xc2 is capacitive; therefore

—hre(Re|| Ri)

y=

(12-2)

V hd + [1 + Me) Xca)¥")

When hie = (1 + hfe) Xco, —he(Rc||Ri) _= mid-frequency gain |A,| _=

V2

+

"he

= (mid-frequency gain) — 3 dB Therefore, at fi,

Nie = (1 + hfe) Xc2 =

xX

or

h: 1e

t

1 + hye a

ce

fi

From Table 6-1 (in Section 6-3), h;

hip =

ea

jopck

1 + hye

(12-3)

Xc2 = hip at fy

So

,

= (impedance seen on ‘looking into the emitter)

> Zo, and often Zj >> rs, so that Zo and r, can be omitted in Eqs 12-4 and

12-5. Once

again, the equations give minimum

capacitance

values, so that the next larger standard values should always be chosen for

C, and C3. Equations 12-4 and 12-5 give an impression that approximately 10% of the signal and output voltages are lost across C; and C3. This would be true if the

476.

Electronic Devices and Circuits

quantities were resistive. However, Xci and Xc3 are capacitive while Z; and R, are usually resistive. So, when the actual loss is calculated, it is found to

be only about 0.5% for each capacitor. Another approach to the selection of coupling capacitors is to make Xc, equal to Z; at two octaves below fi. Thus,

Xey= Ziat fi/4

(12-6)

The output coupling capacitor is then determined by making the impedance of C3 equal to Ry at two octaves below fil4:

Xc3 = Ryat fi/16.

(12-7)

es

When Egs 12-6 and 12-7 are used to determine the values of the coupling capacitors, it can be shown that the capacitor attenuations are less than 5% of Ay.

Shunting Capacitors Sometimes an amplifier is required to have a particular upper cutoff frequency (f2 in Fig. 12-3). The transistor must be selected to have a much higher cutoff frequency than fo. The upper cutoff frequency for the circuit can then be set by connecting a small capacitor from the transistor Figure 12-7

collector terminal to ground (C4 in Fig. 12-7). The

effect of the : shunt

capacitance :

;

oe

at the

= A shunting

can be used at

S Santcircuit Ge toSEInGlemitter select the

transistor collector is discussed in Section 8-4.

upper 3 dB frequency.

Design Calculations

Vie

Example 12-2 Calculate

suitable

resistor

values

for

the

™ = Re

common-emitter amplifier in Fig. 12-8. Cy

as

oH

Solution

Select

Re & Ry 5 Ry,

Rc = 70

mS Rr

ith ka

120k Ts

= 12 kQ, (standard value)

Figure 12-8

Common-

emitter amplifier for Ex.12-2.

Chapter 12 = Small-Signal Amplifiers Select

Ve=5Vand

Vcp

477

=3V

Vere = Vcc — Veg — Vg = 24V-3V—-—5V =16V Vre le = eS Re

=

16V 12 kO

=13mA

VE Rr

a

5V

i

Ic

1.3mA

=3.75kV

(usea3.9 kO standard value to make Ic a little less than the

design level, thus ensuring that Vcr is not less than 3 V.)

Ry = 10Rg = 10 X 3.9kO = 39 kQ (standard value) I

_VetVpp

5V+07V

Ry

39 kO

~ 146 pA Veco —~ Vp Ry

=

I

24V-5.7V =

146 pA

125 kO (use 120 kO standard value)

Example 12-3 Determine suitable capacitor values for the CE amplifier in Ex. 12-2. The signal source resistance is 600 ©, and the lower cutoff frequency is to be 100 Hz.

Solution From data sheet A-5 in Appendix A for the 2N3904,

hge = 100 Bg. 6-2:

—

26mV Ig

= 200

Eq. 12-3:

Xc2 = re at fi

_ 26mV 1.3mA

478

Electronic Devices and Circuits

Therefore,

ae

2

as

1

=

TfiKe

1

Zw X 100 X 200

= 79.5 wF (use 80 wF standard value) hie = (1 + he) re = (1 + 100) X 200

~2kO,

:

Z; = Ril|Ro ||hie = 120 kQ||39 kQ||2 0 = 187kO From Eq. 12-4,

Cy

i

~ Qarfx(Zi + 15)/10 1 Qar X 100 Hz X (1.87 kO + 600 Q)/10 = 6.4 pF (use 6.8 wF standard value)

F

Eq. 12-5, a

q

6

———

1

27 f1(Re ao

R,)/10

1 ~ Qer X 100 Hz X (12kO + 120k)/10 = 0.12 wF (standard value) The complete common-source circuit designed in Examples 12-2 and 12-3 is

shown in Fig. 12-9.

Figure 12-9 CE amplifier circuit designed in Examples 12-2 and 12-3.

Chapter 12

Small-Signal Amplifiers

479

practice Problems 12-1.1 Determine suitable resistor values for a CE amplifier (see Fig. 12-9) that uses a 20'V supply and has a 68 kQ capacitor-coupled load.

12-1.2 Determine suitable capacitor values for the circuit in Problem 12-1.1

to have a 40 Hz lower cutoff frequency and to use a 2N3903 transistor. Assume that r, = 500 (2.

12-2 SINGLE-STAGE COMMON-SOURCE

AMPLIFIER

Specification Bias circuit design for the common-source amplifier in Fig. 12-10 is treated in Chapter 10, and ac analysis of FET circuits is covered in Chapter 11. As with the common-emitter BJT circuit in Section 12-1, the design begins with specification of the supply voltage, amplification, frequency response, load impedance, and so on.

Ry

rs

|

Rs

T

Ry

Cy

.

Figure 12-10

Design of a common-source

Circuit design begins with a specification for the circuit performance.

Selection of /p, Rp, and Rs Since the circuit shown in Fig. 12-10 has no provision for negative feedback, it should be designed to achieve the largest possible gain. From Eq. 11-7, the voltage gain of a CS circuit is Av = —Y¢s (Ro||Ri)

Because A, is directly proportional to Rp||R., a design for the greatest

voltage gain normally requires that the largest possible drain resistance be chosen. However, a very large value of Rp might make the drain current too

480

Electronic Devices and Circuits

small for satisfactory FET operation. Also, low Ip levels give small Y;, values,

which result in lower ac voltage gain. Furthermore, Rp should normally be much smaller than Rr, so that Ry, will have little effect on the circuit voltage gain.

For a given Ip, the largest possible voltage drop across Rp gives the greatest Rp value (Rp = Vrp/Ip). To make Vp as large as possible, Vps and Vs should be held to a minimum (see Fig. 12-11a). The drain-source voltage should usually be Vpsqnin) = (Vas(ofmax) + 1 V). This is large enough to

ensure that the FET operates in the pinch-off region of its characteristics. It also allows for a drain voltage swing of +1 V, which is usually adequate for a small-signal amplifier. If the gate-source bias voltage (Vgs) is other than zero, then, as illustrated in Fig. 12-11a, the minimum Vps should be calculated as follows:

Vidsuniny = Vieswtpiiex) +1 VY — Veg O

(12-8)

Vop

Vep ~ (Vpp — Vps)/2

bi

=~ Ves(off\(max) +

1 V

_

Vos

Vs = (Vpp — Vps)/2

(a) Voltage and current selection Figure 12-11 circuit.

(b) Resistor determination

Voltage and current selection and resistor determination for a CS amplifier

Recall from Chapter 10 that for good bias stability, the source resistor voltage drop (Vs) should be as large as possible. Where the supply voltage is

small, Vs may be reduced to a minimum to allow for the minimum level of Vps. A reasonable approach for most FET circuits is to calculate the the sum of Vs and Vprp from the equation

Vs + Vrp = Vop — Vos (min) and then make

Vs = Van= Se

(12-9)

Chapter 12

Small-Signal Amplifiers

484

—_—_~or

Once Vs, ‘oan. and Ip are selected, Rp and Rg are calculated:

Rp ==u

and Rg w— (ee Fig. 12-11b)

D

Ip

As already discussed in Section 10-4, a bias line should be drawn upon the FET transfer characteristics to determine a suitable gate bias voltage (Vc). The maximum

drain current selected (Ipimax)) is plotted on the maximum

transfer characteristics for the FET used. The bias line is then drawn through

this point with a slope of 1/Rs. The gate bias voltage is read from the intersection of the bias line and the Vg scale. As an alternative to drawing the bias line, Ves can be read from the transfer characteristic when Ipimax) is

plotted. Then, Vg = Vs — Vas

Instead of using the FET transfer characteristics, Vcs(ofp(max) and [pss(max) Can be substituted into Eq. 10-8 to calculate the Vgg level.

Bias Resistors With a voltage-divider bias circuit (as in Fig. 12-11b), Ro is usually selected as

1 MQ, or less. Smaller resistance values may be used where a lower input impedance is acceptable. Larger resistance values may also be used; however, as explained in Section 10-7, there are distinct disadvantages to using resistances higher than 1 MQ.

With R» determined, R; is calculated

from R» and the ratio of Vr; to Vro

i= —

(12-10)

Capacitors As for a BJT capacitor-coupled circuit, coupling and bypass capacitors should be selected to have the smallest possible capacitance values. The largest capacitor in the circuit (source bypass capacitor C2 in Fig. 12-10) sets the circuit low 3 dB frequency (f1). Equation 11-10 was developed for the voltage gain of a common-source circuit with an unbypassed source resistor

(Rs). Rewriting the equation to include X¢ in parallel with Rs gives

_ _~Yis(Rol} Ru) "1

+ Y¢(Rsl|Xca)

Normally Rg >> Xc2, so Rg can be omitted. And since X¢ is capacitive,

A

~Y¢(Rp||Ri)

TU

= ——[—[—==——S—

VEb +t (YeXeo)"]

(12-11)

482

Electronic Devices and Circuits

When Y%.Xc2 = 1,

|A,| =

—Y;,(Rp||Ri) | mid-frequency gain =

V(1 + 1)

V2

= (mid-frequency gain) — 3 dB

Therefore, at fi, Ye Xc2

or

Xe

=1

hee Ys fi

(12-12)

From Section 11-7,

Zs -

So, at fi,

Vg

= (impedance seen on ‘looking into’ the FET source)

Xc2 = (impedance ‘looking into’ the source terminal)

= (impedance in series with Xc2) (see Fig. 12-12)

Equation 12-12 gives the smallest value for the source bypass capacitor. When a standard

Qy

value is selected, the next larger capacitance value should be chosen. This will give a cutoff

\\_|

frequency slightly lower than thef, valueusedin

Rs

the calculations. As explained in Section 12-1, it is important to note that the bypass capacitor is calculated in terms of the resistance seen when looking into the device terminal (the resistance in series

C2). The capacitance . value is not determined with : in terms of the parallel resistor (Rs).

A Eg L CG

xX,

i Figure 12-12 InaCs amplifier circuit, the signal voltage can be divided

across the source bypass

Capacitor and the source

resistance (1/Y;.).

The input and output coupling capacitors should have almost zero effect on the circuit frequency response. In Section 12-1 it is explained that Xc; in series with Z; and Xc3 in series with Ry constitute voltage dividers that can attenuate the ac input and output voltages. To minimize the attenuation, the reactance of each coupling capacitor is selected to be approximately one-tenth of the impedance in series with it at the lowest operating frequency for the circuit

(fi). Equations 12-4 and 12-5 apply once again for the calculation of the

minimum C; and C? values.

Eq. 12-4:

Li'+ f,

Xa == 0 = at Fy

Chapter 12

Eq.

12-5:

Xo

=

———

Small-Signal Amplifiers

483

at fii

As in BJT circuits, Ry is usually much larger than Z,, and Z; is often much

larger than r,; therefore Z, and r, can often be omitted in Eqs 12-4 and 12-5. As always, since the equations give minimum capacitance values, the next larger standard values should always be chosen for C; and C3. Alternatively, as explained in Section 12-1, Equations 12-6 and 12-7 may

be used for determining coupling capacitor values. Design Calculations Example 12-4 Calculate suitable resistor values for the common-source circuit in Fig. 12-13. Vpp

Ri s

ne

Cy FI

Ry

120 kO

5) Ry I,

| Rg

T Cy Figure 12-13 Common-source amplifier circuit for Ex. 12-4.

é +

Solution

Refer to the 2N5459 transfer characteristics in Fig. 9-19. A reasonable level of Ip(max) might be 1.5 mA. Y;, becomes smaller at lower Ip levels.

Ves = Vesior [1 — V Up/Ipss)]

Eq. 10-8:

Using Ves(otf(max) ANd Ipsg(max) from data sheet A-11 in Appendix A (and from

Fig. 9-19) gives

Vog = 8V[1 — V(1.5 mA/16 mA)] =5.6V Eq. 12-8:

Vps(min) = Ves(off\(max) FIV

—Vese=8V+1V—56V

=34V

Vop — Vostmi Eq.

12-9:

Vs

—

Vero

=

2

24V -3.4V ee

==

2

=

484

Electronic Devices and Circuits

=103V

_. _ Vero _ 10.3V Rs= Rp= Ip 15mA = 6.87 kO (use 6.8 kO, standard value) Rp should be Rg

hg

(13-14)

Cc

This quantity is modified by negative feedback according to (a rewritten) Eq. 13-6: Lay=

Ze 1 + Aye

Then, as always, the circuit output impedance is given by Eq. 13-7, which

must also be rewritten for the circuit in Fig. 13-23: Zout = Zo | Ro

An emitter follower output stage can be added to any of the amplifiers previously discussed. However, the combination of an emitter follower out-

put stage with a differential amplifier has a particular significance that will be explained in Chapter 14. Example 13-9 Calculate the output impedance for the circuit modification in Fig. 13-23, assuming that hic = hie = 2 kO, and hg = hfe = 100. Also

25 000 and B = 1/33.4, as for Examples 13-7 and 13-8. Solution

Big, 13-14

Zz, = Nie 7 Rg _ 2kO + 10 kO = 1200

Eq. 13-6:

Zo =

—_— 1+ A,B

as 1 + (25 000/33.4)

= 0.162 Eq. 13-7:

Zot = Rg |Z. = 10 kO|]0.16 © = 0.160

assume

that A, =

Chapter 13

Amplifiers with Negative Feedback

569

My ‘o-stage differential amplifier with negative feedback, as in Fig. 13-22,

134.0 A

‘ is to use 2N3904 and 2N3906 BJTs with a +15 V supply. The closed-loop ~ gain is to be 50. Determine suitable resistor values. 13-42 Calculate the minimum open-loop gain for the circuit in Problem

mee 13-41. Determine Z;, and Zou.

sks

eA

Baers 2

43-5 EMITTER CURRENT FEEDBACK Emitter Current Feedback Circuit Emitter current feedback is produced by connecting an unbypassed resistor (termed a swamping resistor) in series with the emitter terminal of a transistor, as shown in Fig. 13-24a. The effects of an unbypassed emitter resistor in a CE

circuit were analyzed in Section 6-5, where it was shown that the circuit impedances and voltage gains are as follows:

Eq. 6-20; —

Zp = hie + Rex(1 + hye)

Eq. 6-12:

Zin = Ri||Re||Zp

Eq. 6-14:

Zout = (1/Noe) || Rce*Re

Bg, 6-21:

|

—h,.(Rc||R fe(Rc||

Rr)

hie + Rey(1 + Age)

Eq. 6-22:

Ry

120 kO = C

ails 0.15 pF Ry =

39 kQ a Emitter current

A

Ys

feedback resistor

(swamping resistor)

(a) Emitter current feedback circuit

Figure

13-24

(b) Signal, input, and feedback voltages

Single-stage CE amplifier using emitter current feed-

back. The voltage gain is A, ~ (Ro||R/Res-

570

Electronic Devices and Circuits

Equation 6-20 shows that the input impedance at the base of a transistor

with an unbypassed emitter resistor is considerably increased above its normal value without feedback (h;-). This raises the circuit input impedance, as

defined by Eq. 6-12. Therefore, emitter current feedback increases the circuit input impedance. Figure 13-24b shows that the circuit feedback loop is from the transistor base to the emitter, then back to the base again. The collector resistor is outside the feedback loop. The circuit output impedance remains approximately equal to Rc (see Eq. 6-14). So, emitter current feedback has no effect on the circuit output impedance (see Section 6-5). The precise voltage gain for the circuit in Fig. 13-24a is given by Eq. 6-21, and Eq. 6-22 can be used for calculation of the approximate

voltage

gain.

Equation 6-22 is derived from Eq. 6-21 by assuming that hie> r¢, so the capacitor can be calculated from

(13-15)

Xco = Re at fy Example 13-11

Modify the CE amplifier circuit designed in Examples 12-2 and 12-3 to use emitter current feedback to give Ay = 70 (see Fig. 13-25). The lower cutoff frequency is 100 Hz, and the signal source resistance is 600 (2.

Figure 13-25 Emitter current feedback circuit for Ex. 13-11.

Solution

From Eq. 6-22,

Re|[RL _ 12kO|}120 ka

Ren “Ay

70

= 156 © (use 150 © standard value) Reo = Re - Re = 3.9 kO — 150 0 = 3.75 kO (use 3.9 kQ)

572

Eq.

Electronic Devices and Circuits 6-20:

Z (min) = hie + Rgy(1 af hfe) =2kQ0

Eq. 6-12:

+

150 Od

+

100)

= 17.2kO Zin = Ri ||Ro|| Zp = 120 kO||39 kO || 17.2 kO = 10.8kO 1

Eq.

12-4:

Ci

=

arf, (Zp, +7,

/10

1 ~ 2arx 100 Hz x (10.8 kQ + 600 )/10 =14 pF Eq.

13-15:

(use 1.5 uF standard value)

Xc2 = Rr at fi

Co

_

2: *! 1 Qa fiRe, 27x100Hzx 1500

= 10.6 pF (use 10 pF standard value)

Two-Stage Circuit with Emitter Current Feedback All of the two-stage amplifiers discussed in Chapter 12 can be designed to use

emitter current feedback for voltage gain stabilization and increased input impedance. The design procedures are essentially those already discussed. Consider the two-stage, capacitor-coupled circuit in Fig. 13-26. The volt-

age gain for stage 1 is calculated as follows:

From Eq. 6-22,

Agi ©

and for stage 2,

Ay =

RallZing

Re

— RgllRy R

9

(13-16)

(13-17)

The overall voltage gain is Ay = Ay

X Ay

When designing a two-stage circuit with emitter current feedback, the gain

of each stage is determined as

Au = Ay = VA,

(13-18)

Although the two stages can be designed for identical gains, R3|| Zing is un-

likely to equal Rg||Rz. So Ry and Rg are likely to be unequal.

—

Amplifiers with Negative Feedback

Chapter 13

.

573

© Vec

|

Cy

as Figure 13-26 Two-stage, capacitor-coupled BUT amplifier using emitter current feedback in each stage.

For the reasons discussed in Section 12-3, the emitter bypass capacitors

are determined from

Xc4=0.65R, at f,

and

(13-20)

The circuit input impedance is, once again, given by Eqs 6-20 and 6-12, and the output impedance is simply the collector resistor in the second stage (see Eq. 6-14). Example 13-12 The circuit in Fig. 13-25 is to be modified for use as each stage of the circuit in Fig. 13-27. The overall voltage gain is to be 1000, and the lower cutoff frequency is to be 100 Hz. Determine suitable emitter resistor values. Assume transistor parameters of lie = 2kQ and hye = 100.

Solution

Ay

Eq. 13-18:

= Aw = VA,

. ine

= 31.6

From Eq. 13-17,

Roe Rg|[Ru _ 12 kO|[120 ko |

Aw

31.6

= 345 © (use 330 2 standard value) Rio = Rg — Ro =

3.9 kO — 330.0

= 3.57 kO (use 3.9 kQ)

574

Electronic Devices and Circuits

R3

Re

12kQ

_ 120k9

Rg

220 0,

Ry

39 kO

Figure 13-27 Emitter current feedback amplifier circuit for Examples 13-12 and 13-13.

Ay2 becomes

_Rsl[Ri Re

12 kO||120 ko 330 2

~33 Therefore,

From Eq. 6-20,

Avy — 1000 An®— Ay = —— 33 = 30.3 Zp2 = Hie + Ro(1 + hee)

= 2k + 330.A(1 + 100) = 35.3 kO From Eq. 6-12,

Zin = Ro||R7||Zv2 = 120 kO||39 kO|/35.3 kA = 16kO

From Eq. 13-16,

_R3llZing _ 12kO.|[16 kO a 30.3 = 220 2 (use 220 0 standard value) Rs = Rg — Rg =3.9kO — 2200 = 3.68 kQ, (use 3.9 kQ)

Example 13-13 Calculate suitable capacitor values for the two-stage circuit in Ex. 13-12. Solution

Eq. 6-20: = 24.2 kO

Chapter 13 — Amplifiers with Negative Feedback

——_—

575

Eg. 6-12: Zina = Ri ||Ro||Zv1 = 120 kQ|]39 kO||24.2 kO = 13.3k0 Eq. 12-4:

=

Cy

1

1

2Qarfi(Zint + emitter).

Chapter 13

Amplifiers with Negative Feedback

577

Figure 13-30 AC equivalent for the current feedback circuit Fig. 13-29, showing ac voltages and currents.

Thus, some of the signal current is diverted away from the base of Q). This means that the output current (i,2) is less than it would be if there were no

current feedback; consequently, the circuit current gain is reduced.

2 ei

iene

eeN

emit,

9, co

Current Gain To determine the effect of negative feedback on the circuit current gain, first

investigate the current gain without feedback (the open-loop current gain). Suppose that Rr in Fig. 13-30 has a bypass capacitor connected across it so that there is no negative feedback. Assuming that the resistance of Rp; is very much larger than the Q; input impedance (hie), virtually all of i, enters the base of Q; (See Fig. 13-30).

So and

ig ¥ iy gy © Niger 11

Current i,; divides between R; and Zj2. Using the current divider equation,

ig X Ry Rh + ee

2 een

ig = 1c2 = yer ive

a

i, = Nfer tea Ry - Nor Mfer ii Ra Ry + Zi Ry + Zia

The open-loop current gain is i A,

==

i

—_ hfen fer Ra

578

Electronic Devices and Circuits

Now derive an equation for the current gain with negative feedback. Referring to Fig. 13-30, it is seen that i, (in the emitter circuit of Q2) divides between Rp; and Rr, giving ‘ _

lo *

Rp

_

iB

Rpt + Reo where

Rpg

Le

Rr, + Rep

Also, and

ig = i, + ig = ij + (0B

ip= Aji; Therefore, ig= i; + (Aj 4B) = (1 + A;B) The closed-loop current gain is

(CL)

oe

i,

(1 + A,B)

(13-22)

heap:

If A;B >> 1, then

ee

AaaOs Bia BAG)

a

Rei

Re

Re

(13-23 )

It is seen that

parallel current negative feedback stabilizes circuit current gain. It should be noted that, in the current gain equations, the ac output current is taken as the current in the collector circuit of transistor Q,. How this current divides between a capacitor-coupled external load (R,) and the Q> collector resistor (R3) depends on the values of Ry, and R3.

Output and Input Impedances In the circuit shown in Figs 13-29 and 13-30, the Q> collector resistor (R>) is

outside the feedback loop. Therefore, like the case of emitter current feedback, the output impedance of this circuit is largely unaffected by feedback. (It can be shown that the impedance ‘looking into’ the collector of Q> is increased by current feedback.) So the circuit output impedance is Zo

Ro

Assuming that Rp; >> hiei, the circuit input impedance without feedback

is given by

UD;

Zi © hier = >

Ss

Chapter 13

= Amplifiers with Negative Feedback

579

As already shown, with negative feedback, is = i,+ ig = i;(1 + AjB)

1,

i(1 oe

AjB)

jes Eero es

or

,

1+

(13-24)

A,B

Therefore, parallel-current negative feedback reduces circuit input impedance by a factor of (1 + A;B).

Another way

of looking at the circuit input impedance is in terms of the

feedback resistor Ry; and the voltage gain of the first stage. It can be shown that R

(13-25)

Zi = Nea | = v1

Circuit Design As with other negative feedback circuits, the designing of a parallel current negative feedback amplifier is approached by first ignoring the ac negative

feedback components. Resistors Rg) and Rs in Fig. 13-29 are calculated as a single emitter resistor (Rg = Rp) + Rs) to fulfil the desired de conditions. Also, Rp is calculated (as for other dc feedback bias circuits) to provide the required base current to Q;. Rp is then calculated from Eq. 13-23. Usually, the resis-

tance of Rr; is very large, and this results in a calculated resistance for Rr larger than (Rp2 + Rs)! In this case, the base resistor for Q; should be made up of two resistors, one of which is bypassed: see (Rz = Rp, + Rz) in Fig. 13-31. Rp; is the unbypassed portion of R2, and this is calculated in relation to Rpo.

2.2kQ

Rg1000

150k

Ry Cc

Rs

2.2 kO.

18 uF as

Figure 13-31

Current feedback

circuit with part of Re bypassed. The current gain is given by Aicy ~ (Re + Ra)/Ra-

580

Electronic Devices and Circuits

Bypass capacitor C (in Fig. 13-31) is calculated to give Xcz = Rp» at the desired lower cutoff frequency. Because the signal is derived from a current source, the impedance of the input coupling capacitor (C;) at f, should be much smaller than the (normally high) impedance of the signal source. Capacitor C3 is determined by making Xc3 very much smaller than Rp; at f..

Example 13-14 Analyze the circuit in Fig. 13-31 to determine the current gain and the input impedance. Assume transistor parameters of hje = 100 and hie = 2 kO.

Solution From Eq. 6-20,

Zi2 = Nieg + (1 + hfer)Rg = 2kO + (1 + 100)100 1 = 12.1k0

Open-loop current gain: hfe hfegRy _ 100 x 100 X 5.6kD

Eq. q 13-21:

AiR + Zp = 3164 Ry

From Eq. 13-23,

-5.6kO + 121 KO 100 O

B= Ret+Rg

2.2k0 +1000

_i 23 Closed-loop current gain:

Eq. . 13-22 13-22:

(CL) MCO-

Aj

=

Ty AB

3164

~

1+ (3164/23)

= 228 Act)© (Re + Ra)/Ra. Z.=

Eq. 13-24:

hieie

1+AB

2k on, ee

1+ (3164/23)

= 1460 Practice Problems 13-6.1 Modify the dc feedback pair circuit shown in Fig. 12-25a to give violas “Ae =

162

55 and ih

80 Hz. Assume that r, = 12 kQ.

Assuming transistor parameters of hie = 1kO and hg. = 50, calculate

= Zand Axctyf for the circuit in Problem 13-6.1.

Chapter 13

pins siesta

~_—__

13-7

Amplifiers with Negative Feedback

581

ADDITIONAL EFFECTS OF NEGATIVE FEEDBACK

Decibels of Feedback Negative feedback can be measured in decibels. A statement that 40 dB of feedback has been applied to an amplifier means that the amplifier gain has been reduced by 40 dB (that is, by a factor of 100). Thus, Act == Ay — 40 dB

== Be 100

Bandwidth Consider the typical gain-frequency response of an amplifier, as illustrated in Fig. 13-32. Without negative feedback, the amplifier open-loop gain (A,) falls

off to its lower 3 dB frequency ( fi1)), as illustrated. This is usually due to the impedance of bypass capacitors increasing as the frequency decreases. Similarly, the open-loop upper cutoff frequency (f2(o1)) is produced by transistor

cutoff, by shunting capacitance, or by a combination of both. As discussed in Section 8-2, the circuit open-loop bandwidth is given by BWox = f2o1) — fio1) Now look at the typical frequency response for the same amplifier when negative feedback is used. The closed-loop gain (Act) is much smaller than the open-loop gain, and Ac, does not begin to fall off (at high or low frequen-

40

100

200

400

1k 2k 4k = f (Hz) ——

10k

20k

100

BWo) fou

fuct

fou)

fact)

Figure 13-32 Amplifier frequency response with and without negative feedback. Negative feedback extends the amplifier bandwidth.

582

Electronic Devices and Circuits

cies) until A, (open-loop gain) falls substantially. Consequently, f1(c1) is much lower than fio1), and fucty is much higher than f2o1). So the circuit band-

width with negative feedback (the closed-loop bandwidth) is much greater

than the bandwidth without negative feedback.

BWat = fac — fcr) From Eq. 13-2, Aq, =

Ay 1 + A,B

It can be shown that there is a 90° phase shift associated with the openloop gain at frequencies below fio1) and above f201). Thus, Eq. 13-2 must be rewritten as =jAy

Act, =

1 — jA,B Ay

“

Mal = Ts ay

When A,

= 1/B,

1/B

Act

Mel = Fay A

v2

a

= Ac. — 3 dB Thus, for a negative feedback amplifier designed to have the widest possible bandwidth,

the cutoff frequencies would

occur when

the open-loop

gain

falls to the equivalent of 1/B. Thus, faci) occurs when Ay = 1/B®

Aq,

(13-26)

So, for example, the cutoff frequencies for a negative feedback amplifier designed for a closed-loop gain of 100 would occur when the open-loop gain falls to 100. It is seen that

negative feedback increases amplifier bandwidth. The upper cutoff frequency

for an amplifier is usually

greater than

20 kHz, and the lower cutoff frequency is around 100 Hz or lower. So fy >> fi,

and consequently,

This means that the amplifier bandwidth is essentially equal to the upper cutoff frequency. Now refer to Fig. 13-32 once again. The amplifier gain multiplied by the upper cutoff frequency is a constant quantity. This is known as the gainbandwidth product. Therefore,

Chapter 13

Amplifiers with Negative Feedback

583

Act X fact = Av X far)

or

Ay f 2(OL)

Fact) =

(13-27)

Aci

Thus the closed-loop upper cutoff frequency for a negative feedback amplifier can be calculated from the open-loop upper cutoff frequency, the open-

loop gain, and the closed-loop gain.

Harmonic Distortion Harmonic distortion occurs when a transistor or other device is driven beyond

the linear range of its characteristics. Figure 13-33 shows the Ic/Vpg characteristics of a transistor biased to a base-emitter voltage Vz. As illustrated,

when the base-emitter voltage changes (+vp-) are very small, the collector current changes by equal positive and negative amounts (+i,). When +0p¢ is

large, the change in +7, is greater than the change in —i¢. This is because of the nonlinearity in the Ic/Vgg characteristics. The result is harmonic distor-

tion (or non-linear distortion) in the waveform of i, and in the amplifier outThe distorted waveform can be shown to consist of a fundamental frequency waveform and a number of smaller amplitude harmonic components (see Fig. 13-34). The fundamental waveform is the amplified signal, or ampli-

inne

aa

Hh

ee mee

itaalewtS Saeee

put.

V

iL

A

r+

10.8

B

(V)

Fundamental

|

(v

te)

|

Harmonics (v4) + Ube

Hf

|

+VUbe

—Ube

Figure 13-33

Harmonic distortion in the output ofan

amplifier is caused by non-linearity in transistor characteristics. Negative feedback reduces this type of distortion by a factor of (1 + A,B).

Figure 13-34

Harmonic dis-

tortion in an amplifier is reduced by negative feedback.

584

Electronic Devices and Circuits

fier output voltage (v,), and the harmonics are unwanted voltage components

(vy). The harmonic distortion is the rms value of vy expressed as a percentage of the rms value of v,. The harmonics (generated within the feedback loop) are reduced by negative feedback by a factor of (1 + AyB). Thus,

% distortion with NFB =

% distortion without NFB

(13-28)

(1 4.A,B)

Therefore,

negative feedback reduces harmonic distortion.

Attenuation Distortion Attenuation distortion occurs when different frequencies are amplified by dif-

ferent amounts. This type of distortion is the result of the amplifier open-loop gain being frequency-dependent (see Fig. 13-35). When negative feedback is used, the closed-loop gain is a constant quantity largely independent of signal frequency within the circuit bandwidth. Like harmonic distortion, attenuation distortion is reduced by a factor of (1 + AyB) by negative feedback. Equation

13-28 applies. Thus, negative feedback reduces attenuation distortion.

i (Hz)-——+> Figure 13-35

Attenuation distortion, resulting from different signal

frequencies being amplified by different amounts,

is reduced

by

negative feedback.

Phase Shift Input signals to an amplifier go through phase shifts from the input to the output. The waveforms in Fig. 13-36 show that, ina two-stage circuit, there is

a 180° phase shift from v; to v1, and a further 180° shift from vo; to Vo2. In

Chapter 13 — Amplifiers with Negative Feedback

—

some

cases,

an

amplifier

can

produce

585

different

hase shifts for different signal frequencies. For

example,

higher

frequency

signals

might

be

shifted by more than 180° at each stage, resulting

mae

in an undesirable

phase difference (¢) between

input and output, as illustrated. Audio (and other) signals at an amplifier input

are usually made up of a combination of component waveforms with different amplitudes and different frequencies. Consequently, any variation in amplifier-introduced phase shift will create distor-

tion in the output waveform that is not present in the input. To investigate the effect of negative feedback

Phase

on amplifier phase shift, assume that the openloop gain has a phase shift angle of ¢,and that the n ift isi shift phase d-loop sata:

and

.

P

ac waveforms

‘

Pc. ihe

T

shift Figure 13-36 Undesirable ifts ini amp lifier phase shifts

open-loop gain = A,/¢

Aci [Ga

=

iv

ewe

Ald ~ 1+ A,B/p

=o-

ene

are re-

duced by negative feedback.

A,B sin b = ; ‘ 1+ A,Bcos¢ + jA,B sin d

=

A,Bsind

_,

a

(

1+A,B cos

Oe

13-29

)

Thus,

negative feedback reduces amplifier phase shift by an angle of

tan!

an

A,B sin

1 + A,Boos ¢

Example 13-15 A negative feedback amplifier has an open-loop gain of 60 000 and a closedloop gain of 300. If the open-loop upper cutoff frequency is 15 kHz, estimate

the closed-loop upper cutoff frequency. Also, calculate the total harmonic distortion with feedback if there is 10% harmonic distortion without feedback. Solution Av f1(0L)

Eq. 13-27:

facy =

4 a

= 3 MHz

Eq. 13-28:

_ 60000

x 15 kHz

300

586

Electronic Devices and Circuits

distortij on withi NEB

% di

% distortion without NFB _ =

(1+ A.B)

~

10%

1+ (60000/300

= 0.05%

Noise Circuit noise generated within the feedback loop of an amplifier is reduced by

a factor of (1 + A,B) in the same way that unwanted harmonics are reduced.

It should be noted that only the noise generated within the feedback loop is reduced by feedback. Noise produced by bias resistors outside the feedback

loop will not be affected by feedback.

Negative feedback reduces circuit noise.

Circuit Stability In Chapter 16, it is explained that, for a circuit to oscillate, the loop phase shift must be 360° when the loop gain is 1. The loop phase shift is the phase shift around the loop from the amplifier input to the output, and back via the feedback network to the input. Similarly, the loop gain is the product of the amplifier open-loop gain and the feedback network attenuation (A,B).

The loop phase shift of an amplifier can approach 360° as the gain falls off at the high end of the bandwidth. In this case, the amplifier might oscillate, and it is said to be unstable. The usual method of combating this kind of instability is to include small shunting capacitors from the transistor collector terminals to ground. These tend to cause the loop gain to fall below 1 before

the loop phase shift approaches 360°. Amplifier instability and compensation techniques are further covered in Chapter 15.

Practice Problems 13-7.1 The amplifier in Ex. 13-15 has a 15° open-loop phase shift at high signal frequencies. Calculate the phase shift with negative feedback. 13-7.2

A negative feedback amplifier with a closed-loop gain of 250 has

a 4 MHz upper cutoff frequency. Calculate the open-loop cutoff frequency if the open-loop gain is 200 000.

Review Questions Section 13-1 13-1

13-2

Draw a

sketch to illustrate the principle of series voltage negative feedback,

and briefly explain. List the major effects of negative feedback on an amplifier.

Derive an equation for the voltage gain of an amplifier that uses series voltage

negative feedback.

Chapter 13 — Amplifiers with Negative Feedback

13-3

13-4 13-5

587

Derive an equation for the input impedance of an amplifier that uses series voltage negative feedback. Derive an equation for the output impedance of an amplifier that uses series voltage negative feedback. Discuss the effect of input bias resistors on the input impedance of a negative feedback amplifier, and the effect of a collector resistor at the output of a BJT negative feedback amplifier.

Section 13-2 13-6

Sketch the circuit of a two-stage, capacitor-coupled BJT amplifier that uses series voltage negative feedback. Briefly explain how the feedback operates, and write an equation for the voltage gain in terms of the feedback components.

13-7

Briefly discuss the procedure for determining the negative feedback components for the circuit in Question 13-6.

13-8

For the circuit in Question 13-6, write equations for the input impedance and

output impedance in terms of the circuit components and transistor parameters.

Section 13-3 13-9

Sketch the circuit of a direct-coupled, two-stage BJT amplifier that uses series

voltage negative feedback. Q; should be an npn device, and Q2 should be a pnp transistor. Briefly explain the feedback operation, and write the equation for voltage gain in terms of the circuit components. 13-10 For the circuit in Question 13-9, write equations for Zin and Zou in terms of the transistor parameters and the circuit components.

13-11 Briefly discuss the design procedures for the circuit in Question 13-9. 13-12 Sketch the circuit of a dc feedback pair that uses series voltage negative feedback. Explain the operation of the feedback network, and write an equation for the voltage gain in terms of the circuit components. 13-13 For the circuits in Question 13-12, write equations for Zin and Zin

terms of

the transistor parameters and the circuit components. 13-14 Briefly discuss the design procedures for the circuit in Question 13-12.

13-15 Sketch the circuit of a direct-coupled, two-stage BIFET amplifier that uses series

voltage negative feedback. Explain the operation of the circuit, and write an equation for the voltage gain in terms of the circuit components. 13-16 For the circuits in Question 13-15, write equations for Zj, and Zou; in terms of the transistor parameters and the circuit components.

13-17 Briefly discuss the design procedures for the circuit in Question 13-15.

Section 13-4 13-18 Sketch the circuit of a two-stage, direct-coupled negative feedback amplifier that uses a two-transistor, emitter-coupled input stage. Explain the operation of the circuit.

588

Electronic Devices and Circuits

13-19 Write equations for Avct), Zin, ANA Zout for the circuit in Question 13-18. 13-20 Briefly discuss the design procedures for the circuit in Question 13-18.

Section 13-5 13-21 Sketch the circuit of a single-stage common emitter amplifier that uses emitter current feedback. Briefly explain the operation of the circuit. 13-22 For the single-stage circuit sketched for Question 13-21, write equations for

AyCLy Zin, and Zout13-23 Briefly explain the design procedure for the circuit in Question 13-21. 13-24 Sketch a two-stage, capacitor-coupled BJT amplifier that uses emitter current feedback in each stage. Briefly explain the operation of the circuit. 13-25 Discuss the design procedure for the two-stage circuit in Question 13-24. 13-26 Sketch the circuit of a direct-coupled, two-stage, BJT amplifier that uses emitter current feedback. Q; should be an npn device, and Q2 should be a pup transistor. 13-27 Write equations for A,c1), Zin, aNd Zox¢ for the circuit in Question 13-26.

Section 13-6 13-28 Sketch a direct-coupled dc feedback pair amplifier that uses parallel current

negative feedback. Briefly explain the operation of the circuit, and discuss its performance characteristics. 13-29 Write equations for Aic1), Zin, and Zou for the circuit in Question 13-28.

13-30 Discuss the design procedure for the two-stage circuit in Question 13-28.

Section 13-7 13-31 Using illustrations, explain the effects of negative feedback on the bandwidth of an amplifier. Discuss the effect of open-loop gain reduction on the closedloop gain.

13-32 Draw sketches to explain how harmonic distortion occurs in an amplifier. Discuss the effects of negative feedback on harmonic distortion. 13-33 Explain attenuation distortion, and discuss the effects of negative feedback on attenuation distortion.

13-34 Explain how phase shift distortion occurs in an amplifier, and discuss how negative feedback affects phase shift. 13-35 Discuss the effect of negative feedback on circuit noise.

13-36 Briefly discuss amplifier stability with negative feedback.

Problems Section 13-1 13-1 A two-stage BJT amplifier has an open-loop voltage gain of 224 000 when the transistors have a maximum hf. value, and 14 000 when the transistor /1 fe Val-

ues are a minimum. Calculate the closed-loop gain for both cases when negative feedback is used with a feedback factor of 1/125.

Chapter 13 — Amplifiers with Negative Feedback

—_—_——

13-2

589

The amplifier in Problem 13-1 has an input impedance of 1.2 kO at the base of

the input transistor when negative feedback is not used. Voltage divider bias with R; = 150 kO and R2 = 56 kO is used at the input transistor. Calculate the

circuit input impedance (with negative feedback) at both hy. extremes.

13-3

The output transistor in the amplifier in Problem 13-1 has 1/hoe 80 kO. and a 5.6 kO collector resistor. Calculate the circuit output impedance at both h¢extremes.

13-4

The closed-loop gain of a negative feedback amplifier is measured as 99.7 when the feedback factor is 1/100, and as 297 when a feedback factor of 1/300

is used. Determine the open-loop gain.

Section 13-2 13-5

The circuit in Fig. 13-16 is to be modified to have an overall voltage gain of 50 and a lower cutoff frequency of 150 Hz. Calculate the new values for Rr, Rrz, Co and

13-6

13-7

Cri.

Analyze the negative feedback input and output impedances. hie = 800 2, hfe = 60, and 1/hoe A two-stage, capacitor-coupled

amplifier in Problem 13-5 to determine the Assume that the transistor parameters are = 90 kO. The open-loop gain is 97 000. BJT amplifier as in Fig. 12-15 has the following

components: R; = 150 kO, Rz = 56 kQ, R3 = 4.7 kQ, Rg = 5.6 kQ, Rs = 150 kO,

Re = 56 kQ, Ry = 4.7 kO, Rg = 5.6 kQ, Ry = 47 kO, C) = 10 pE Co = 180 pF

C3 = 10 pE, and Cy = 180 uF. Modify the circuit to use series voltage negative feedback.

13-8

The voltage gain is to be 180, and the required lower cutoff fre-

quency is 90 Hz. Calculate the input and output impedances for the circuit in Problem 13-7. Assume

that

the

transistor

parameters

are

hje= 1.2

kQ,

hte = 90,

and

1/Roe = 75 kQ.

Section 13-3 13-9

A two-stage, direct-coupled BJT amplifier as in Fig. 12-20 has the following components: R; = 100 kQ, R2 = 39 kQ, R3 = 3.9 kO, Ra = 3.9 kQ, Rs = 2.7 kQ,

Re = 3.9kO, Ry, = 33 kQ, Cy = 8 pF Cp = 150 wE,C3 = 150 pF. Modify the circuit to use series voltage negative feedback to give a gain of 75 and a lower cutoff

frequency of 60 Hz. 13-10 Calculate the input and output impedances for the circuit in Problem 13-9 if the transistor parameters are Itie = 1 kQ,, hfe = 120, and 1/Nge = 100 kO.

13-11 The two-stage, direct-coupled BJT amplifier designed in Examples 12-8 and 12-9 (and analyzed in Ex. 12-10) is to be converted into a negative feedback amplifier with a voltage gain of 120 and a lower cutoff frequency of 20 Hz. Make the necessary modifications and determine the new component values. 13-12 A two-stage, direct-coupled amplifier with complementary transistors is to be designed to use negative feedback, as in Fig. 13-17. The overall voltage gain is to be 150, and the lower 3 dB frequency is to be 200 Hz. Calculate suitable values for Rpy, Rp2, and C2.

590

Electronic Devices and Circuits

13-13 A dc feedback pair using negative feedback (as in Fig. 13-18) is to have Ayct = 80, f1 = 120 Hz, and fz = 50 kHz. Calculate suitable component values for the feedback network. 13-14 Calculate Zi, and Zou: for the circuit in Fig. 13-18. Use the component values

shown and the transistor parameters hie = 1.2 kO,, hfe = 90, and 1/hoe = 95 kQ, 13-15 A two-stage, negative feedback BIFET amplifier, as in Fig. 13-19, is to have Ao(ct) = 19 and f; = 400 Hz. Calculate suitable values for Rri, Rr2, and Cry.

13-16 Calculate the direct current through the feedback networks in the circuits in Figs 13-17 and 13-19 when the feedback network is directly connected instead

of capacitor-coupled. Section 13-4 13-17 The circuit in Fig. 13-21 is to be designed to have Ayci) = 175. Using Vec = +12.5 V, select suitable current and voltage levels, and calculate resistor values.

Use 2N3904 and 2N3906 transistors. ' 13-18 Calculate the minimum values of Ay c1), Zin, and Zout for the circuit in Problem 13-17.

13-19 A two-stage differential amplifier circuit (as in Fig. 13-21) is to be designed to amplify a 10 mV input to 750 mV. The amplifier supply is +9 V, and the transistors to be used have hp = Age = 150, hie = 1.5 kO, and 1/A oe = 150 kf. Determine suitable resistor values.

13-20 Calculate Z; and Z, for the circuit in Problem 13-19.

Section 13-5 13-21 Design a single-stage BJT common-emitter amplifier with emitter current feedback. The circuit has the following specifications: Q; = 2N3906, Vec = —-18 V,

Ry = 150 kO, A, = 45, and f; = 50 Hz. 13-22 Analyze the circuit designed for Problem 13-21 to determine A>, Zin, Zou, and fi.

13-23 A common-emitter amplifier as in Fig. 12-1 has the following components: Ry = 120 kO, Ro= 33 kO, Rc = 6.8k0, Rg = 3.3 kO, and Ry = 68 kQ. Modify

the circuit to use emitter current feedback. The voltage gain is to be 23, and the required lower cutoff frequency is 60 Hz. The transistor parameters are

the following: hie = 1.2 kO, hie = 90,1/hoe = 95kO, andr, = 13 2. 13-24 Calculate Ay, Zin, and Zou: for the circuit in Problem 13-23. 13-25 Two stages of the circuit in Problem 13-23 are to be connected in cascade to give an overall voltage gain of approximately 1600 and a lower cutoff frequency of 50 Hz. Determine the necessary modifications. 13-26 An amplifier is to be designed using two stages of the circuit designed for Problem 13-21. The overall voltage gain is to be 900 and the lower cutoff frequency is to be 100 Hz. Determine the necessary modifications.

13-27 Analyze the circuit designed for Problem 13-25 to determine Ay, Zin, and Zout: 13-28 Analyze the circuit designed for Problem 13-26 to determine A,, Zin, and Zout: 13-29 A dc feedback pair (as in Fig. 12-25a) is to be modified to use emitter current feedback. The circuit specifications are Vcc = 15 V, R, = 80 kQ, A, = 400, and fi = 70 Hz. Design the circuit to use 2N3904 BJTs.

Chapter 13

Amplifiers with Negative Feedback

591

13-30 Analyze the circuit designed for Problem 13-29 to determine Ap, Zin, and ZoutSection 13-6 13-31 A dc feedback pair is to be designed to use parallel current negative feedback, as in Fig. 13-29. Using Vcc = 22 V and transistors with Mrz = hfe = 75 and

hie = 2.2 kO, design the circuit to have Ic = 0.9 mA, Aj = 22, and f; = 200 Hz. 13-32 Calculate A; and Z;,, for the circuit in Problem 13-31. 13-33 A dc feedback pair as in Fig. 12-25a has the following components: R; = 12 kQ, Rg = 330 kO, R3 = 4.7 kO, Ra = 2.7 kQ, and Cy = 240 pF. Determine the neces-

sary modification to give Aj = 30 and ff = 75 Hz. 13-34 Analyze the circuit designed for Problem 13-33 to determine Aj and Zin. Assume

that h¢e, = hgeo = 100 and that hier

= Aieg = 1 kO.

Section 13-7 13-35 The amplifier in Example 13-4 has 5% total harmonic distortion in its output waveform when negative feedback is not used. Calculate the new distortion

content with negative feedback. 13-36 If the amplifier in Example 13-4 has a 17° open-loop phase shift at high frequencies, determine the phase shift with negative feedback. 13-37 The negative feedback amplifier in Examples 13-7 and 13-8 has a 30 kHz openloop upper cutoff frequency. Calculate the upper cutoff frequency with negative feedback. 13-38 A negative feedback amplifier with B = 1/105 produces a 2 V output when the input is 20 mV. Distortion content in the output is 1%. Find the new sig-

nal level to give 2 V output when the negative feedback is disconnected. Also, determine the new distortion content in the output.

Practice Problem

13-1.1 13-2.1 13-2.2 13-3.1 13-3.2 13-4.1 13-4.2 13-5.1 13-5.2 13-6.1 13-6.2 13-7.1 13-7.2

Answers

1.42 kQ, 5.2 kO, 26.3 kQ, 28 , 134.9 100 0, 3.9 kO, 33 pF, 10 kO, 33 wF 27.5kQ, 113.0 3300, 68kQ, 171 pA 150 0, 2.7kQ, 5.6 pF, 30 pF, 3000 pF 4.7kQ, 10 kQ, 6.8 kQ, 10 kM, (220k + 1 kQ), 4.7 kO, 4.7 kO, 15 kO 4.7k0, 34.90 (68 kO + 10k), 47 kQ, 4.7 kQ, 120 Q, 4.7 kO, 2.7 kQ, 150 0, 3.9 kO 2.7 pF, 27 pE, 22 pF, 0.47 pF 100 9, 5.6 kO, 1.8 pF, 20 pF, 39 pF 610,878 0.08° 5 kHz

CHAPTER

14

IC Operational Amplifiers

and Basic Op-Amp Circuits Objectives You will be able to:

1 Sketch and briefly explain an operational amplifier circuit symbol and the basic input and output stages, and identify all terminals.

2 List and discuss the most important op-amp parameters.

3 Design op-amp bias circuits, and show how to null the output offset. 4 Sketch the following linear op-amp circuits in directcoupled and capacitor-coupled configuration and explain the operation of each: ° voltage follower ¢ non-inverting amplifier ¢ inverting amplifier 5 Analyze and design circuits of the type listed in Objective 4 above.

Sketch the following linear opamp circuits and explain the

operation of each: * summing amplifier ¢ difference amplifier ¢ instrumentation amplifier

Analyze and design circuits of the type listed in Objective 6 above. Sketch the following nonlinear op-amp circuits and explain the operation of each: * zero crossing detector

¢ inverting Schmitt trigger circuit

° non-inverting Schmitt trigger Analyze and design circuits of the type listed in Objective 8 above.

INTRODUCTION An operational amplifier is a high-gain amplifier circuit with two highimpedance input terminals and one low-impedance output. The inputs are identified as inverting input and non-inverting input. The basic circuit consists

of a differential amplifier input stage and an emitter follower output stage. The voltage gains of integrated circuit (IC) operational amplifiers are extremely high, typically 200000. Because of this high voltage gain, externally connected resistors must be employed to provide negative feedback. Design of IC op-amp circuits involves determination of suitable

Chapter 14 values

for

the external

components.

(C Operational Amplifiers

593

The design calculations are usually

much simpler than for discrete-component circuits.

14-1

INTEGRATED CIRCUIT OPERATIONAL AMPLIFIERS

Circuit Symbol and Packages Figure 14-1a shows the triangular circuit symbol for an operational amplifier (op-amp). As illustrated, there are two input terminals, one output terminal, and two supply terminals. The inputs are identified as the inverting input

(— sign) and the non-inverting input (+ sign). A positive-going voltage at the inverting input produces a negative-going (inverted) voltage at the output terminal. Conversely, a positive-going voltage at the non-inverting input generates an output which is also positive-going (non-inverted). Plus /minus supplies are normally used with op-amps, and so the supply terminals are identified as +Vcc and —Vgp. Non-inverting

Yee

input

14

8

Inverting

2% 34 Al

7 6 5

mE

oO —VeEE

(a) Op-amp circuit symbol

Top view (b) Terminal connections

for DIP package

Top view (c) Terminal connections

for metal can package

Operational amplifier circuit symbol! and terminal connections. The + and Figure 14-1 — signs identify the non-inverting and inverting input terminals, respectively.

Two typical op-amp packages are illustrated in Figs 14-1b and c. For both the dual-in-line plastic (DIP) package and the metal can package, terminals 2 and 3 are the inverting and non-inverting inputs, respectively, terminal 6 is the output, and terminals 7 and 4 are the + and — supply terminals.

Basic Internal Circuit The basic circuit of an IC operational amplifier is essentially as shown in Fig. 13-23 and further illustrated in Figs 14-2a and b. (The actual op-amp

internal circuitry is much more complex.) The differential-amplifier input stage has two (inverting and non-inverting) high-impedance input terminals, and the emitter follower output stage has a low impedance. An intermediate stage between the input and output stages is largely responsible for the op-amp high voltage gain. Figure 14-2a shows a BJT input stage, while Fig. 14-2b has a FET input stage. Op-amps that exclusively use BJTs are termed bipolar op-amps, and those that use a FET input stage with . BJT additional stages are referred to as BIFET op-amps.

594

Electronic Devices and Circuits

Iz GaP

vad

Ole cs Iz

(a) Basic input and output stages for a bipolar op-amp

Figure 14-2

(b) Basic input and output stages for a BIFET op-amp

Input and output stages for bipolar and BIFET operational amplifiers. The

FET gate current is very much smaller than the BUT base current.

Important Parameters Some of the most important parameters for the 741 operational amplifier (one of the most commonly used) are listed in the data sheet portion shown

in Fig. 14-3. The large-signal voltage gain (Ay), also called the open-loop gain (Ayov)), for the 741 is listed as 50 000 minimum and 200 000 typical. This means that a

signal applied as a voltage difference between the two input terminals is amplified by a factor of at least 50 000. The typical amplification is 200 000, and the maximum amplification can be considerably greater. This is similar to the

situation with

the hy of a BJT, where

the

manufacturer

specifies

minimum, typical, and maximum values. Electrical characteristics (Ve = 415 V, T, = 25°C unless otherwise specified)

Parameters

Largesignal Palace cainitA,)

Conditions

~ V0RL =2kQ, = +10V

Min

Rg = 10 kO.

Input offset current (Io)

| Input resistance (r;)

Output resistance (79)

Figure 14-3

Max |

Unit

80

500 |

nA

1.0

5.0 | mV

20

200

50.000 | 200000

Input bias current (Ijp) Input offset voltage (Vio)

Typ

Portion of data sheet for a 741 op-amp.

0.3

nA

2

MQ

75

a

Chapter 14

—_‘|C Operational Amplifiers

595

The input bias current (Ig) is the base current for the op-amp input stage

transistors. In Fig. 14-3, pg is listed as 80 nA typical and 500 nA maximum.

Ideally, the input stage transistors should be perfectly matched, so that zero voltage difference between the two input (base) terminals should produce a zero output voltage. In practice, there is always some difference

between the base-emitter voltages of the transistors, and this results in an

input offset voltage (Vio), that might be as large as 5 mV for a 741 op-amp. Similarly, because of mismatch of input transistors, there is also an input offset current (Io). For the 741 Ito is a maximum of 200 nA. The input resistance (r;) and the output resistance (ro) are the resistances at

the op-amp terminals when no feedback is involved. Since virtually all opamp

applications

use negative

feedback,

these

(resistance)

quantities

are

modified in practical circuits. The de supply voltage for electronic circuits can vary when the supply current changes, and in some cases there is an ac ripple voltage superimposed

on the dc. The supply voltage changes can be passed to the output of an amplifier. Ideally, the supply voltage variations should have no effect on the circuit output. How good the amplifier is at attenuating supply voltage variations is determined by the power supply voltage rejection ratio (PSRR). This is usually specified in decibel form. Common mode inputs are voltage changes that are applied simultaneously to both input terminals of an operational amplifier. Common-mode input voltages can be passed to the output. The common-mode rejection ratio (CMRR) (expressed in dB) defines how good the amplifier is at attenuating commonmode input voltages.

Practice Problems 14-1.1 Determine the following parameter values from the LM108 op-amp data sheet A-14 in Appendix A: large signal voltage gain, input bias current, input offset voltage, and input resistance. 14-1.2 Repeat Problem 14-1.1 for the LF353 op-amp data sheet A-15 in Appendix A.

14-2

BIASING OPERATIONAL AMPLIFIERS

Biasing Bipolar Op-amps Like other electronic devices, operational amplifiers must be correctly biased if they are to function properly. As already explained, the inputs of an operational amplifier are the base terminals of the transistors in a differential amplifier. Base currents must flow into these terminals for the transistors to Operate. Consequently, the input terminals must be directly connected to

suitable dc bias voltage sources.

596

Electronic Devices and Circuits

|

The most appropriate dc bias voltage for op-amp inputs is approximately halfway between the positive and negative supply voltages. One of the two input terminals is usually connected in some TV Ge way to the op-amp output to facilitate negative

fu

ground via a signal source (see Fig. 14-4). Base

pal

3 5

feedback. Where a plus/minus supply is used, the other input might be biased directly to thas

vo. pe

current Ip; flows into the op-amp non-inverting

input via the signal source, while Ip2 flows from = _L the output into the inverting input, as Figure 14-4 Op-amp circuit illustrated. with one input terminal

Figure 14-5 shows a situation in which one .

;

.

input is connected via resistor R; to ground, and the other is connected via R2 to the op-amp output.

Once

grounded via a signal generator, and the other

input directly connected to the output.

again base current for the input

stage transistors flows into both input terminals. Resistors R; and R» should have equal values, so that voltage drops JpgiR1 and Ip2R2 are approximately

equal. Any difference in these two voltage drops appears as an op-amp dc input voltage, which may be amplified to produce a dc offset at the output. + Vee

Cy

Tp, —_—_—_—_—

o-) Us

3 Ri

I,

in the circuit in

Fig. 14-5, then a very small input resistance (Ri) would

be offered to a

capacitor-coupled signal source. On the other hand, if Rj and R» are very

large, the voltage drops Ip1R; and Ip2R2 may be ridiculously high. An acceptable maximum voltage drop across these resistors must be very much smaller than the typical Vpg level for a forward-biased base-emitter junction.

(This is also discussed in Section 5-8.) Vri © Vpz/10

—

Rigmax) = Vri/Tp(max)

and Upe

Therefore,

PS

nBh a Bo 1) Py

Rigas) =

Vv.

‘

_\BE

0D grax)

_

—_‘|C Operational Amplifiers

Chapter 14

597

Figure 14-6 shows a voltage divider (R; and R) providing an input terminal bias voltage derived from the supply voltages. The voltage-divider

current I, should be very much larger than the input bias current. This is to ensure that Ip has a negligible effect upon the bias voltage. Usually, the minimum Ip is selected as . Io¢nin)

=

100

(14-2)

TB (max)

Then R; and Rare simply calculated as Vz;/In and Vpo/ In, respectively. Resistor R3 in Fig. 14-6 should be approximately equal to Ri ||R2 to

minimize any difference between Igi(Rj||Ro) and Ip2R3 that could act as a de input voltage.

Figure 14-6

Op-amp circuit using a voltage-

divider bias circuit.

Example 14-1 Calculate the maximum resistance for R; and Rp» in Fig. 14-7a if a 741 op-amp is used. Determine suitable resistances for Ri, Rz, and R3 in Fig. 14-7b to give

Vp = 0 when the supply voltages are +15 V. —O

+ Vee

Ry IBl

-

| Ih

VB

NJ iy

6

3|°

—O

4

R,

= %

al, —Veg (a) Grounded input circuit

Figure 14-7

(b) Voltage-divider bias

Op-amp circuits for Ex. 14-1.

598.

Electronic Devices and Circuits

Solution Fig. 14-7a:

Vez

0.7 V (for op-amps with BJT input stages)

From the 741 data sheet A-13 in Appendix A,

Eq

VBE

Ruma) = 19 Ty¢nany =

* 14-1:

=

0.7 V

10 X 500 nA

= 140 kO (use 120 kO standard value) Ry = Ry

=

120 kD

Fig. 14-7b: Eq. 14-2:

Ip = 100 Ipq@nax) = 100 X 500 nA = 50 pA Vri

=

Vro =15V

_,

Ry = Ro =

. Vr

15V

In 50pA

= 300 kO (use 270 kO standard value)

R3 = Ry||Rz = 270 kO||270 kO = 135 kO (use 120 kO standard value)

A single-polarity supply voltage can be used with an operational amplifier. For example, a 741 could use a +30 V (as illustrated in Fig. 14-8) instead of a +15 V supply. Resistors Rj and R2 are normally selected to set Vp = Vec/2. The input offset voltage referred to in Section 14-1 and the resulting output offset can be reduced or eliminated in the circuit shown in Fig. 14-6 by making one of the resistors adjustable. Similarly, if R3 in Fig. 14-8 is a variable

+Voc Ry

i \h

Vp

Ro ot

3 i

6

“ei

LANA,

—1

‘ Figure 14-8

Op-amp circuit using a sing lepolarity supply.

599

_|C Operational Amplifiers

Chapter 14

resistor, it could be adjusted to reduce the op-amp output offset voltage. The

process is termed voltage offset nulling. Figure

offset

14-9 shows

nulling

with

another method

of voltage

a 741

A

op-amp.

10

+ Vee

kQ

potentiometer is connected to the differential amplifier input stage via terminals 1 and 5, as illustrated. With the moving contact connected to

° 3 0—Z i

—Vzx, the potentiometer can be adjusted to null the

>

10 kQ

output offset voltage.

O —Veg

Biasing BIFET Op-amps The input bias current for a BIFET op-amp is

Figure 14-9 Output oe aie a 7%

typically 50 pA, which is very much smaller that

op-amp with a 10 kO

that for a bioplar op-amp. So the bias resistor selection method already discussed would produce

potentiometer Sia c d5

very high

This is undesirable

resistor values.

terminals"

ee™"

because electric charges can accumulate at the FET gates and thus make the bias levels unstable. Also, stray capacitance becomes

more

effective with

high-value bias resistors, possibly resulting in unwanted circuit oscillations. Furthermore, large resistors at an amplifier input can produce unacceptable levels of thermal noise output (see Section 8-6). To combat these effects, the largest resistor in a BIFET op-amp bias circuit should normally not exceed 1 MQ. Because there is virtually no input current with a BIFET op-amp, there is no need for equal resistance values at the inverting and non-inverting input

terminals.

Example 14-2 Determine suitable resistor values for the type of circuit shown in Fig. 14-7b when a BIFET op-amp is used. The supply is +9 V and the output is to be

biased to +3 V. Solution

Select

Ry = 1 MQ (standard value) Va=V,=t+3V Vero = Va —- Vez =3V

— (-9 V)

=12V Vri

=

Vec

— Vs

=9V-3V

=6V ;

Vro_

2 RR,

12V

1MO

600

Electronic Devices and Circuits

Vix:

RS

6.

pA

= 500 kO, (use 470 kO. + 33 kQ) R3 =0

Practice Problems = 14-2.1 A

Le

eins

{ f

741 op-amp is used with a +24 V supply in the type of circuit

shown in Fig. 14-8. Determine suitable bias resistor values. 14-2.2 Repeat eee 14-2,1 to bias the input to +10 V.

14-3

VOLTAGE FOLLOWER CIRCUITS

Direct-Coupled Voltage Follower The IC operational amplifier can be employed for an infinite variety of applications. The very simplest application is the direct-coupled voltage follower shown in Fig. 14-10a. The output terminal is connected directly to the inverting input terminal, the signal is applied to the non-inverting input, and the load is directly coupled to the output. {

+Vee

O+Vcc

External connection ‘

(b) Basic op-amp circuit connected as a voltage follower Figure 14-10 Ina voltage follower circuit, the output terminal is directly connected to the inverting input terminal. As the input voltage changes, the output follows the input to keep the inverting input terminal voltage equal to the non-inverting terminal voltage.

Chapter 14 —=— IC Operational Amplifiers

—

601

Figure 14-10b shows the basic op-amp circuit connected as a voltage follower. With the differential amplifier input stage (see Sections 12-8 and

13-4), V2 (which equals V,) must equal V;. When V2 is higher or lower than V,, the voltage difference is amplified to move the output back to equality

with the input. Suppose V, were slightly higher than V;. The voltage at Q» base (terminal 2) would be higher than that at Q; base (terminal 3); therefore Ic2 would be increased above its normal level. This would cause an increase in the voltage drop across Rc, thus reducing Vp3 and driving Vo back to

equality with Vj. Similarly, when V, is lower than Vj, Q2 base voltage is lower than that at Q; base and Ic is reduced, thus reducing Vrc, increasing Vp3, and driving V, back up toward Vj. This is, of course, negative feedback

as described in Section 13-4.

When the input voltage (at terminal 3) is increased or decreased, the feedback effect causes the output to follow the input almost perfectly. The actual difference between the input and output voltage is easily calculated from the output voltage level and the op-amp open-loop voltage gain. Like an emitter follower, the voltage follower has a high input impedance, a low output impedance, and a voltage gain of 1. However,

follower

performance

demonstrated

is superior

to that of the emitter

the voltage

follower.

As

in Ex 14-3, the typical difference between input and output

voltage with a voltage follower is only 5 .V when the input amplitude is 1 V. With an emitter follower, there is a 0.7 V dc voltage difference between input

and output. The voltage follower also has a much higher input impedance and a much lower output impedance than the emitter follower. The actual values of Zin and Zo. can be calculated from the negative feedback equations

derived in Chapter 13.

Example 14-3 Calculate the typical difference between the input and output voltage for a voltage follower using a 741 op-amp with a 1 V input, as in Fig. 14-11. Also, determine typical Zin and Zour values.

Solution From data sheet A-13 in Appendix A, typical parameters are:

open-loop voltage gain (Aor or Ay) = 200 000, rj = 2 MQ, ro = 75 0 +Vec

7 +O

7 i

vgth 3) 2

a

+

lke

741

6

io +

4

%

—Ver

_

Figure 14-11 Ex. 14-3.

Voltage follower circuit for

602

Electronic Devices and Circuits

Va = V,-V; V5 1V Y%,=—2 Ay 200000 =5 pV

;

Z, = (1 + ApB)r; = [1 + (200 000 x 1)] x 2MQ

From Eq. 13-4,

= 400000 MO

From Eq. 13-6,

z.

75 0

ae

~ 1+A,B 1+ (200000 x 1) = 0.375 x 107° 0

Capacitor-Coupled Voltage Follower When

a voltage follower is to have capacitor-coupled

input

and

output

terminals, the non-inverting input must be grounded via a resistor (Rj in Fig. 14-12). As explained in Section 14-2, the resistor is required for passing bias current to the non-inverting input terminal. It also offers an input resistance to the signal source, rather than a short-circuit. Because

coupled,

the

dc

output

offset voltage

might

seem

the load

to

be

is capacitor-

unimportant.

However, the dc offset voltage at the op-amp output terminal can limit the amplitude of the ac output voltage. So a resistor (Rz) equal to R; should be included in series with the inverting input terminal to equalize the IpR,

voltage drops and thus minimize output offset voltage. Designing the capacitor-coupled circuit in Fig. 14-12 involves the calculation of Ry, Cy, and C). The circuit input impedance is Rj || Z;; however, Z; is always much larger than Rj. So the circuit input impedance is simply taken as

Ain = Ry

(14-3)

Figure 14-12 A Capacitor-coupled voltage follower must have the opamp non-inverting terminal grounded via a resistor to provide a path for input bias current.

—

Chapter 14

—_‘|C Operational Amplifiers

603

Normally, the load resistance R, is much smaller than R,, and consequently, the smallest capacitor values are calculated when C> is selected

to set the circuit lower cutoff frequency, f,. Therefore, Xe

= (Z, + Ry) at fi

(14-4)

Capacitor C; should then be calculated from the equation Xc1 = (Zin + rs)/10 at f;, so that it has no significant effect on the circuit lower cutoff frequency: Xc

= (Ry + r,)/10 at fi

(14-5)

Coupling capacitor equations are discussed in Section 12-1.

Example 14-4 Design a capacitor-coupled voltage follower using a 741 op-amp. The circuit lower cutoff frequency is to be 70 Hz, the load resistance is 4 kQ, and the signal source resistance is much smaller than Rj. Solution See Fig. 14-13. From data sheet A-13 in Appendix A, Tpqmax) = 500 nA Eq.

14-1:

Ry (max)

=

VBE _ 0.7 V 10 Ip@max) 10 X 500nA

= 140 kO (use 120 kO standard value) Ro = R, = 120k0 From Eq. 14-4,

Co

ae

wl _ . 2rf,;R, 2m X 70Hz X 4kO

~ 0.56 wF (standard value)

From Eq. 14-5,

Cy

_

1 2mf,R1/10

_

1 2m X 70Hz X 120k0/10

0.19 pF (use 0.2 F standard value) Cy

C 9

0.2 wF Ri

0.56 pF

120k.

RL

4kQ =

Figure 14-13 Capacitor-coupled voltage follower for Ex. 14-4.

604

Electronic Devices and Circuits

Abiapret al

oe Ppbies n pe

. 10 kQj is to hove os ne Hz. ae Determine coupling Capi

a

Mohlower with 75 ~ 22 KO and’R) = ne suitable capacitor values. or values for the circuit in part (b)o

Ex 11 woe = * 600 0, Ry = 8.2kO, and f, = 20 Hz. ximum de offset voltage that might be produced at of the

aoe ne | 1a

circui designed i in part (a) of Ex. 14-1 when R, is

el

14-4 NON-INVERTING AMPLIFIERS Direct-Coupled Non-Inverting Amplifier The non-inverting amplifier circuit in Fig. 14-14 behaves similarly to a voltage follower circuit with one major difference. Instead of all of the output voltage being fed directly back to the inverting input terminal (as in a voltage follower), only a portion of V, is fed back. The output voltage is divided by

resistors R2 and Rs, and the voltage across R3 is applied to the inverting input terminal. As in the case of the voltage follower, the output voltage changes as necessary to keep the inverting input terminal voltage equal to that at the noninverting input. Thus, the voltage Vr3 always equals Vj, and the output voltage is then determined by the resistances of R2 and R3. ig Vee

Figure 14-14

Op-amp non-inverting

amplifier circuit. The signal is applied to

the non-inverting input terminal. The circuit voltage gain is Ac. = (Ro + R3)/R3.

Because the signal voltage is applied to the op-amp non-inverting input

terminal, the output always has the same polarity as the input. A positivegoing

input produces

a positive-going

output,

and

vice versa.

Thus,

the

input is not inverted (at the output), and the circuit is identified as a non-

inverting amplifier. The voltage-divider current (12) is always selected to be very much larger

than the operational amplifier imput bias current, and

bea= Vi SDR,

(14-6)

Chapter 14

—_‘[C Operational Amplifiers

605

Also, in Fig. 14-14 it is seen that

eo

(14-7)

Ry + R3

The circuit voltage gain is

An

= Vo _ Ip(Rz + R3) cL => = Vi Ty Rg

Therefore,

Ro

+

Ac, = “8

(14-8)

3

Figure 14-15 shows a non-inverting amplifier circuit with a resistor (R1) connected in series with the non-inverting input terminal. As other op-amp circuits, this is done to equalize the resistor produced by the input bias currents. In this case, Ri is approximately equal to the resistance ‘seen looking out of’

in the case of voltage drops chosen to be the inverting

input terminal. Thus,

Ry'= Ro||R3

(14-9)

Figure 14-15

Non-inverting

amplifier circuit with a resistor R, in series with the input. R; is

selected to be approximately equal to Ro||R3.

The input and output impedances for a non-inverting amplifier are easily determined from the negative feedback equations in Chapter 13. Design of a non-inverting amplifier mostly involves determining suitable voltage-divider resistors (Rz and Rs). So, as explained in Section 14-2, design begins with the selection of a voltage divider current that is much larger than

the op-amp input bias current. Example 14-5

Design a direct-coupled non-inverting amplifier (as in Fig. 14-15) to use a 741 op-amp. The output voltage is to be 2 V when the input is 50 mV.

606

Electronic Devices and Circuits

Solution

From the 741 data sheet A-13 in Appendix A, T3(max)

From Eq. 14-2,

=

500 nA

Tognin) = 100 Ip(max) = 100 X 500 nA = 50 pA

From Eq. 14-6,

poe In

50

pA

= 1kO (standard resistor value)

From

Eq. 14-7,

aes

V =—=

+R,

a

SS

Ro

2V

= 40kO, Ro = (Ro + R3) — Rg = 40 kO — 1kO

= 39 kO (standard value)

From Eq. 14-9,

Ry = Ra||R3 = 39 kQ||1 kO 1k

(use 1 kO standard value)

Example 14-6 Calculate

typical

input

and

output

impedances

for

the

amplifier designed in Ex. 14-5. Solution From data sheet A-13 in Appendix A, typical parameters are Ay = 200 000, 7, = 2 MQ, ro = 75 0 Also,

Rs Ro+R3

B

1ka 39k +1kO

4 40 200 000 From

Eq.

13-4,

Zi =

ol

10

FromEq.136,

o

A,B) B=

i

+

40

000 MQ.

to

20-7 > aR 14 0.015 0

75 0,

(200 000/40)

xX

2MQO

non-inverting

Chapter 14

——_——

_—[C Operational Amplifiers

607

Capacitor-Coupled Non-Inverting Amplifier

hae plete

| apnesare =

When a non-inverting amplifier is to have a signal capacitor coupled to its

input, the op-amp non-inverting input terminal must be grounded via a resistor to provide a path for the input bias current. This is illustrated in Fig. 14-16, where R; allows for the passage of Ipi. As in the case of the

capacitor-coupled voltage follower, the input resistance is essentially equal to R; for the capacitor-coupled non-inverting amplifier. + Vee

—

Figure 14-16 A capacitor-coupled noninverting amplifier circuit must have the

se.

able amg

non-inverting input terminal grounded via a resistor to provide a path for the input bias current.

Resistors R1, R2, and R3 in the capacitor-coupled circuit are determined

exactly as for a direct-coupled non-inverting amplifier. The capacitor values are calculated in the same way as for a capacitor-coupled voltage follower.

Example 14-7 Calculate the voltage gain and lower cutoff frequency for the capacitorcoupled non-inverting amplifier circuit in Fig. 14-17. Solution

~_ ig, lee

An

= Rp + R3 _ 50kM + 2.2kO R3

eh

22kO,

era hae

aaranlin

= 26.5

Figure 14-17 Capacitor-coupled noninverting amplifier circuit for Ex. 14-7.

608

Electronic Devices and Circuits

Yeo

From Eq. 14-4,

1

fAi= QmCoRy 2a

X 8.2 pF Xx 600 2

' = 32.3 Hz *,

1

Practice Problems _ Uh, ub eon 8X4 14-41 A direct-coupled non-inverting deuplitier using a 741 op-amp is to have a 100 mV input voltage amplitude and a voltage gain of 40, Select suitable resistor values.

14-4.2 Design a capacitor-coupled non-inverting amplifier using a 741 opamp to have a+5 V output amplitude when the input is +250 mV. The 14-43

load resistance is 820 , and the lower cutoff frequency is to be 20 Hz. Redesign the circuit in Problem 14-4.1 to use a BIFET op-amp.

14-5

INVERTING AMPLIFIERS

Direct-Coupled Inverting Amplifier The circuit in Fig. 14-18 is termed an inverting amplifier because, with V, applied via R; to the inverting input terminal, the output goes negative when the input goes positive, and vice versa. Note that the non-inverting input terminal is grounded via resistor R3. With the non-inverting terminal

grounded, the voltage at the op-amp inverting input terminal remains close to ground. Any increase or decrease in the (very small) difference in voltage between the two input terminals is amplified by the op-amp open-loop gain and fed back via Rz and R; to correct the change. Because the inverting input terminal is not grounded but remains close to ground,

the inverting input

terminal in this application is termed a virtual ground or virtual earth. The circuit input current in Fig. 14-18 can be calculated as

1 = VR 1

Ri

Vee

G7

W= Ry

uf Vri

"

+Voc

Ry Zi

Js

Virtual

Vi

aN

=] i

+

ground

|

Figure 14-18 Op-amp inverting amplifier. The

6 +

m

3-74

go

yy

~

Rs

|: —

BE

i

Signal voltage is

applied via resistor Ri

16 29 NR

to the inverting input

terminal. The circuit voltage gain is Aci

=

—Ro/R3.

Chapter 14

—_—_—

[COperational Amplifiers

609

The input voltage is applied to one end of Rj, and the other end of R; is at

ground level. Consequently, Vai = Vj

and

V;

k=

(14-10)

Ry

I, is always selected to be very much larger than the op-amp input bias current (Ip). So virtually all of I; flows through resistor Rz (see Fig. 14-18), and

the voltage drop across R> is Vro

=

IR

The left side of Ry is connected to the op-amp inverting input terminal, which, as discussed, is always at ground level. This means that the right side of R2 (the output terminal) is Vo below ground. So

Vo = -LRo

on, lilt ass

From Eq. 14-10,

VY, = Ry

Therefore the circuit voltage gain is Vo

ten ncRNA

A

amen

(14-11)

or

=

Ac, =

—I1R2

—

SO

Vi

==K

Ry

GR

2

(14-12)

If the input of the inverting amplifier is grounded, the circuit is seen to be exactly the same as a non-inverting amplifier with R3 as the input resistor and zero input voltage. Thus, negative feedback occurs (as in a non-inverting amplifier) to maintain the op-amp inverting input terminal at the same voltage level as the non-inverting input terminal. The output impedance of an inverting amplifier is calculated in exactly the same way as for a non-inverting amplifier (using Eq. 13-6). As in the case

of the non-inverting amplifier, the output impedance is very low for an inverting amplifier. The input impedance of an inverting amplifier is easily determined by recalling that the right side of Rj (in Fig. 14-18) is always at ground level and

that the signal is applied to the left side of Ri. Therefore, Zi

a

Ry

(14-13)

Design of an inverting amplifier is very simple. Voltage-divider current I;

is selected to be very much

larger than the op-amp

input bias current.

610

Electronic Devices and Circuits

Resistors R; and R2 are calculated from Eqs 14-10 and 14-11, or 14-12, and R3 is chosen to be approximately equal to Ri || Ro.

Example 14-8 Designa direct-coupled inverting amplifier, as in Fig. 14-19, to use a 741 Op-amp.

The input voltage amplitude is 20 mV and the voltage gain is to be 144. R, WW

56kQ I; +Vec

oya

ee

390 0

-——o

+

3-74 R

390.0 =

—-V,

mE Figure 14-19

~

Ex. 14-8.

Inverting amplifier for

Solution For the 741, Select

TB(max) = 500 nA Tyqnin) = 100 Ipgmaxy = 100 X 500 nA

= 50 pA

F rom Eq. . 14-10, 14-10

V;

Ry == i,

20mvV

50pA

= 400 O (use 390 0 standard value) From. Eq. 14-12,

Ro = Aci Ry = 144 x 3900

= 56.2 kO (use 56 kO standard value)

R3 = Ry||Rz = 390 Q||56 kO = 390 QO (use 390 Q)

Capacitor-Coupled Inverting Amplifier A capacitor-coupled inverting amplifier circuit is shown in Fig. 14-20. In this case, the bias current to the op-amp inverting input terminal flows (from the output) via resistor Ro, so that the input coupling capacitor does not interrupt the input bias current. A voltage drop IgR2 is produced at the inverting input by the bias current flow, and this must be equalized by the IpR3 voltage drop

atthe non-inverting inverting circuit,

input.

Therefore,

R3 = Ry

for

the

capacitor-coupled

non-

(14-14)

Chapter 14

—

IC Operational Amplifiers

Figure 14-20

Ry

644

Capacitor-coupled

inverting amplifier circuit. Note

:

that the flow of bias current is not interrupted by capacitor C}.

Apart from the choice of Rs, the circuit is designed exactly as the directcoupled circuit, and the capacitor values are calculated in the same way as

for a cqpaaitor-toupled non-inverting amplifier.

Practice

Problems

14-5.1 A di ect-coupled inverting amplifier using a 741 op-amp is to have a 300 mv input voltage amplitude and a voltage gain of 15. Calculate Suitable resistor values. 14-5.2: The circuit in Problem 14-5.1 is to have a 1 kQ capacitor-coupled load

and a 600 Q capacitor-coupled signal source. Determine suitable capacitor values for a 20 Hz lower cutoff frequency. ee 3 Redesign ie circuit in Problem 14-5.1 to use a BIFET op-amp.

14-6 SUMMING

AMPLIFIER

The summing amplifier circuit in Fig. 14-21 is simply a direct-coupled inverting amplifier with two inputs applied to two resistors (R; and R2). With Vax

~S

+o Ay Ry

+o

R

Veo cS

Vin

iA

hy he

AWm7

= |

Vin

_

Figure 14-21 voltages.

Virtual

_

ground

~

B

An op-amp summing amplifier amplifies the sum of two, or more, input

612

Electronic Devices and Circuits

two input voltages (Vj; and Vj2) there are two input currents (J; and I). Also,

because the op-amp inverting input terminal behaves as a virtual ground (as for an inverting amplifier), the input currents are =17

Via

Vip I, 2 =—* Rs

Ry’

All of I; and Ip flows through resistor R3, giving

Vo=—| “

Vin LZ

=|/—

°

With

Ry =

+ bh) Rs va R, |

+—!IR

°

Rz,

—R Vo

sy mm

(Vii

+ Vi2)

(14-15)

1

When R3 = R; = Roz, the output voltage is the direct (inverted) sum of the two inputs. When R3 is greater of the sum of the inputs. Asumming amplifier is number of inputs, and the amplifiers are designed in

than R; and R2, the output is an amplified version not limited to two inputs. There can be almost any output remains the sum of the inputs. Summing the same way as ordinary inverting amplifiers.

Example 14-9 Design a three-input summing araplifien

as in Fig. 14-22, to use a BIFET

op-amp and to have a voltage gain of 3. Calculate the resistor currents and the output voltage when all three inputs are 1 V.

R3

4,

o—\W

ce + Ve

—Veg

ohn

Figure 14-22

it

Three-input summing

amplifier for Ex. 14-9.

Solution

Select

Ry =1MO, 7

From Eq. 14-12,

R

1 == %Ry

=

R

Rg

3 ==Act

=

1MQ

3

= 333 kO (use 330 kO standard value)

Chapter 14

te

3

V;

_|C Operational Amplifiers

613

1V

R330 KO

= 3.03 pA Ig =], + h + 5 = 3.03 pA + 3.03 pA + 3.03 pA

= 9,09 pA Vo = —Iy Ry = —9.09 pA X 1 MO, = —9.09 V

Or, from Eq. 14-15,

Vv.

o=

—R, R,

(

-1MO, (1V+1V +1V) V,,+-V,,+V,3)=——— il + i2 is) 330 kQ (

= —9,09 V

Practice Problems 14-6.1 A two-input summing amplifier is to be designed to produce a 5 V output from two 0.25 V inputs. Calculate suitable resistor values for a circuit using a 741 op-amp. 14-6.2 If the circuit designed in Ex. 14-9 has 0.75 V, 1.5 V, and 1.25 V inputs,

J determine Vo, ha, bb, Is, and Ts.

14-7

DIFFERENCE AMPLIFIER

Circuit Operation A difference amplifier amplifies the difference between two inputs. The circuit shown in Fig. 14-23 is a combination of inverting and non-inverting amplifiers. Resistors Ri, R2, and the op-amp constitute an inverting amplifier for a voltage (Vii) applied to Rj. The same components (Rj, R2, and the op-

amp) also function as a non-inverting amplifier for a voltage (Vp) at the nonRy

—\W\-

V,

Figure 14-23 An op-amp difference amplifier amplifies the difference between two input voltages.

614

Electronic Devices and Circuits

inverting input terminal. It is seen that Vrs is derived from input voltage V,,

by the voltage divider R3 and Rs. To understand the circuit operation,

consider the output produced by each input voltage when the other input is zero. —R

With V;j2 = 0,

Vol

With V;; = 0,

Vo = “1

R,

ae

VR

Therefore With

R3

Vo2 =

Ry and

= =

Rg

=

xX Vin

1

+R

Ry

Rg = ———

x Vra

ROR,

X J;

R; + Ro

Bact Ry + Ry EY

ye R

Rg

i2

Ro,

Ro X V; Von 02 = = Ry i2 When both inputs are present, Vo = Von + Vor

R

= z Vig + 1

Therefore

—R

ze

Vin

Ro

Vo= z (Viz — Vin)

(14-16)

1

When R2 = R1, the output voltage (as calculated by Eq. 14-16) is the direct

difference between the two inputs. With R2 greater than Rj, the output becomes an amplifier version of (Viz — Vii).

Input Resistances Consider the input portion of the difference amplifier circuit reproduced in Fig. 14-24. The resistance at input terminal 1 is the same as the input impedance for an inverting amplifier: Zi) = R;. The input resistance at the op-amp non-inverting input terminal is very high (as in the case of a noninverting amplifier), and this is in parallel with

resistor

R4.

So

the input

impedance at terminal 2 in Fig. 14-24 is Zi2 = R3 + Rq. Equation 14-16 was derived by assuming that R3 = Ry and Ry = Ro. It can be shown that the same result is obtained when the ratio R4/R3 equals R2/R1,

so that the actual resistor values do not have

to be

equal.

For

equal

resistances at the two input terminals, select

Rg + Rg = Ry

(14-17)

Chapter 14 =‘ (C Operational Amplifiers

a,

615

© Ma

|

Figure 14-24

Difference

amplifier circuit input impedances.

=

Then, calculate the resistances of R3 and R4 from

a Rz

(14-18)

Ry

A simple rule of thumb can be used for determining suitable resistance values for R3 and R4 when the two input resistances do not have to be exactly equal. Select Ra = R2/Act, which always makes Ry = R,. Then, calculate R3 as R3 = R, / Act:

Example 14-10 A difference amplifier is to be designed to amplify the difference between two voltages by a factor of 10. The inputs each approximately equal 1 V. Determine

suitable resistor values for a circuit using a 741 op-amp

Fig. 14-25). Solution Select

I, ~ 100 Ip = 100 X 500 nA = 50 pA Rg

AWN

R 1

I1

Ry Vir

+

2

iv

Ip |

741

P

Vi2

OL] R

ok

=

4

I—o —

a

Vy, - VEE

iL =

te

.

‘

Figure 14-25 Difference amplifier circuit for Ex. 14-10.

(see

616

Electronic Devices and Circuits

a, = Ya __1V Ty 50pA = 20 kO (use 18 kO standard value) Ro = Ac,

Ri

=

10

x

18 kQ

= 180 kQ (standard values) Rg

— R,

R3

=

=

Ry AcL

18kO

= s

18 kX 10

= 1.8 kO (standard value)

Common-Mode Voltages A common-mode input voltage is a signal voltage (dc or ac) applied to both input terminals at the same time. This is illustrated in Fig. 14-26, where Vj, Viz, and the common-mode voltage (V,) are all represented as inputs from de

sources. As shown, the input voltages at terminals 1 and 2 are changed from Vii and

Viz to (Va

2 Vi) and

(Vai

+ Viz).

R,

WW

+3 1

Bi 2

V, n + V; il

,&

va i Vio

—

V n

L

Vat Vig

Figure 14-26

-

>

mode

Common-

input voltage applied

to a difference amplifier.

Equation 14-16 shows that the output voltage is the amplified difference between the two input voltages. So, R

Vy = R [Viz + Va) — (Vir + V,)I Ro = Ri (Vio — Vin) This shows that the common-mode input is completely cancelled. However,

recall that the gain equation depends upon the resistor ratios (Ry/R3 and

R2/Rj) being equal. If the ratios are not exactly equal, one input will undergo a larger amplification than the other. Moreover, the common-mode voltage at

Chapter 14

IC Operational Amplifiers

one input terminal will be amplified by a larger amount

By

than that applied to the other input

terminal. In this case, common-mode

WwW

inputs

will not be completely cancelled. Because it is difficult to match resistor ratios Bi perfectly (especially for standard-value com- oN — ponents), some common-mode output voltage is almost certain to be produced where a common-

+Vec

~ Vex

mode input exists. Figure 14-27 shows a circuit

modification

for

minimizing

common-mode

6417

Ry

outputs from a difference amplifier. Resistor Ry is

Common-mode

adjustment

made up of a fixed-value resistor and a smallvalue adjustable resistor connected in series.

This provides adjustment of the ratio Ry/R3 to match R2/R1,so that common-mode outputs can

ras dike

sil

nulled by adjustment of R4.

be nulled to zero.

Practice Problems 14-7.1 If the circuit designed in Ex. 14-10 has Vi = 0.75 V and Vi2 = 1.5 V, determine

Vg

Tr, Tro, Ip3, and

Vera.

14-7.2 ‘A 500 © resistor is connected in series with Ry in the circuit designed “in Ex. 14-10. Calculate the common-mode gain. 14-7.3 A difference amplifier is to be designed to produce a 3 V output when ~ the inputs are 1.5 V ard 2 V. Determine suitable resistor values for a

circuit using a BIFET op-amp. 14-8 INSTRUMENTATION AMPLIFIER Circuit Operation At first

glance,

the

instrumentation amplifier circuit in Fig. 14-28 looks complex, but when considered section by section it is found to be quite simple. First, note that the second stage (consisting of op-amp A3 and resistors R4 to R7) is a difference amplifier that operates exactly as described in Section 14-7. Next, look at A; and resistors Rj and R2; this is a noninverting amplifier. Similarly, Az, combined with resistors R2 and R3, constitutes another non-inverting amplifier. Because the first-stage circuits share a single resistor, their operation is slightly different from the usual non-

inverting amplifier operation. The first stage accepts a differential input voltage (Vicait)), and produces a differential output voltage (Voqait)). The differential input could be the

618

Electronic Devices and Circuits Interconnected non-invertin g amplifiers

.

Difference amplifier

+Voe

_.

!

!

Rs

—WW—

| | l | I

Ry Vicaif) J

Vea

Re

l

i | |

i |

Ry

-

| | ! |

—Ver

|

Figure 14-28 An instrumentation amplifier has two interconnected non-inverting amplifiers as the first stage, and a difference amplifier as the second stage.

difference between two grounded inputs (Vj; and

Viz), as illustrated. But

often a differential ungrounded input voltage is derived, for example, from two voltage monitoring electrodes connected to a human body for medical purposes. In this case, there could be a large common-mode

input voltage,

which can be shown to pass to the output of the first stage without amplification. The difference amplifier second stage accepts V air) from the first stage as an input and produces an output to a grounded load, as shown on the circuit diagram. As explained in Section 14-7, the difference amplifier tends to reject common-mode voltages, and the circuit can also have an adjustment for reducing common-mode outputs to zero. The instrumentation amplifier is now seen to be a circuit with two highimpedance input terminals and one low-impedance output. The differential input voltage is amplified and converted to a single-ended output, and common-mode inputs are attenuated.

Voltage Gain Recall that, with a non-inverting amplifier, the feedback voltage to the op-

amp inverting input terminal always equals the input voltage to the noninverting input terminal. Therefore, the voltage at the R,R» junction equals

Via, and that at the R2R3 junction equals Vir. Consequently, the voltage drop across R2 equals the difference between the two input voltages. That also

_|C Operational Amplifiers

Chapter 14

619

means that Vp equals the differential input voltage (Via). The current ah a eelniildeneeee +

through R2 can now be calculated as

b= Viqait)

RD

The voltage drop across R,, R2, and R3 is the differential output voltage of the

kt er

first stage (Vovaiey): Vowdin

= Ip (Ri + Ro + Rs)

ne

Vera: = —

Ry

ee,

+

Ro

+ R3)

The (closed-loop) voltage gain of the differential input-differential output first stage is Aci =

Ry

Voit) _

Vicaif)

+

Ro

+

R3

Ry

Normally, Ri and R3 are always equal. So, the first stage gain can be written as +

(14-19)

Agia = = Ry

From Eq. 14-16, the second-stage gain is

a. cL2 =~ BsR

The overall voltage gain is Act

= Acu

x Aci2

The second stage is often designed for a gain of one, so that the overall voltage gain can be calculated from Eq. 14-19. Note that, as shown in Fig. 14-28, R> can be a variable resistor for adjustment of the circuit overall

voltage gain.

Example 14-11 Calculate

the

overall

voltage

gain

for the instrumentation

amplifier

in

Fig. 14-29. Determine the current and voltage levels throughout the circuit when a +1 V common-mode input (V,) is present along with +10 mV signals. Solution From Eqs 14-16 and 14-19,

2R, + Ro, Rs x Ry AcL 2a Ry

620

Electronic Devices and.Circuits

Rs

WW 15 kO

Rg

I,

Wr

I5kQ

R,

NS

“

-

4”

-

f

15 kQ

Veg

15 mS

Figure 14-29

Instrumentation amplifier circuit for Ex. 14-11.

_ (2X 33 kQ)

+ 300 O

300 2,

x

15. kO 15kQ

= 221

At the junction of R; and Rz, Vp

=

Vi

+

Vn

=

10mMV

+1V

= +1.01 V

At the junction of R2 and R3, Ve=

V2 + Va = -10mMV+1V

= +0.99V

The current through Roz, b=

2

Va = Ve _ 1.01V — 0.99V

Ry

300 2

= 66.67 pA

At the output of A, V, = Vp + (2 X Ry) = 1.01 V + (66.67 pA X 33 kQ) = +3.21 V

At the output of A2,

Va = Ve — (In X Rs) = 0.99 V — (66.67 pA X 33 kQ) =-121V

_IC Operational Amplifiers

Chapter 14

—

At the junction of Re and R;,

Ve= Vax

ee

621

.

R

ee

Rt

x

15kQ,

cae + Tk

= —0.605 V At the junction of R4 and Rs, Ve = Ve = —0.605 V The current through R4,

i= Va-Ve _ 3.21 V — (-0.605 V) Rg

15 kO

= 254.3 pA At the output of A3,

Vz = Ve — (Ig X Rs) = —0.605 V — (254.3 pA X 15 k®) = -4.42V

practlee Problem

14-8. 1 An instrumentation amplifier is to be designed to produce a 4.75 V output when the differential input is 50 mV. Using 741 op-amps, etermine suitable resistor values.

14-9 VOLTAGE LEVEL DETECTORS Op-amps in Switching Applications ‘Operational amplifiers are often used in circuits in which the output is switched between the positive and negative saturation voltages +Voicaty and

—Voyeat). The actual voltage change that occurs is known as the output voltage swing. For many op-amps (such as a 741), the output saturation voltages are

typically the supply voltage levels minus 1 V. Thus, as illustrated in Fig. 1430, the typical output voltage swing is 2

For many

(Vcc

—1 V)

a (VEE

+

1V)

(14-20)

op-amps the output can be switched from one supply level to

the other (there is no 1 V drop), so that AV = Vcc — Vee

This is referred to as rail-to-rail operation.

(14-21)

622

Electronic Devices and Circuits

Output waveform

+Vec

—

tVosat)~ tVe-1V

Vejen Figure

14-30

— Verh 1V

An operational amplifier used in a switching application produces an

output voltage that switches between positive and negative saturation levels.

The switching speed, or rate of change, of the op-amp

output voltage is

termed the slew rate (SR). Refering to Fig. 14-30,

SR

=

AV a

14(14-22)

—

Suppose the output changes from —10 to +10 V; the voltage change AV is 20 V. If the transition time (or rise time, see Section 8-5) is At = 1 us, the slew rate is 20 V/s. Another integrated circuit known as a voltage comparator is often used in

place of an operational amplifier in switching applications. Voltage comparators are similar to op-amps in that they have two input terminals (inverting and non-inverting) and one output terminal. However, comparators

are designed exclusively for switching,

and

they

have slew

to be

simply an

and

the signal

rates much faster that those available with op-amps.

Zero Crossing Detector The

zero crossing detector circuit in Fig. 14-31a

is seen

operational amplifier with the inverting input grounded

applied to the non-inverting input. When the input is above ground level, the

output is saturated at its positive maximum, and when the input is below ground, the output is at its negative maximum level. This is illustrated by the input and output waveforms, which show that the output voltage changes from one extreme to the other each time the input voltage crosses zero. The input waveform could have any shape (sinusoidal, pulse, ramp, and so on),

but the output will always be a rectangular-type wave. The actual input voltage that causes the output to switch is not precisely zero, but some very small voltage above or below zero, depending upon the

op-amp open-loop gain. If the op-amp non-inverting input is grounded and the signal is applied to the inverting input in Fig. 14-31a, the output is negative when the input is

Chapter 14

—‘|C Operational Amplifiers ils

=

or

V o(sat)

= ie

|

623

a

7\

|

Oo

T1350

feria

\

moe

40

\L

—90°

—225

Phase hift

°™

FEOP

—225°

20 +18 dB/octave —> 100

"

10k

100 k

1M

Soa

fos

Soi

> (kHz)

Signal frequency

Figure 15-2

The three stages of an op-amp (internal) circuit each has its own gain/

frequency response with a 6 dB/octave fall-off, and its own

phase shift/frequency

response with a maximum phase shift of 90°. These responses combine to give the overall op-amp A,/f and 6/f responses.

loop phase shift is in addition to the —180° phase shift that normally occurs from the op-amp inverting input terminal to the output. Thus, the total loop phase shift (¢,) at f,1 is (—45° — 180°) = —225°; atfpa, bt. = (—135°

— 180°) =

—315°; and at f3, o, = (—225° — 180°) = —405°. As already pointed out, oscillations occur when the loop gain equals or exceeds 1 and the loop phase shift is 360°. In fact, the phase shift does not have to be exactly 360° for oscillation to occur. A phase shift of 330° at A,B = 1 can make the circuit unstable. To avoid oscillations, the total loop phase shift must not be greater than 315° when A,B = 1. The difference

between 360° and the actual loop phase shift at A,B= 1 is referred to as the phase margin (¢m). Thus, for circuit stability, the phase margin minimum

should bea

of Om = 360° — 315° = 45°

Compensated Op-amp Gain and Phase Response The open-loop gain/frequency and phase/frequency responses for two internally compensated operational amplifiers are shown in Figs 15-3 and 15-4. The 741 frequency response graph in Fig. 15-3 shows that the gain starts at 100 dB and falls by 20 dB/decade over most of its frequency range. The phase shift remains —90° or less for most of the frequency range. The openloop gain falls off to 1 (0 dB) at a frequency of approximately 800 kHz. The 741 is known as a general purpose operational amplifier for use in relatively

low-frequency applications.

Chapter 15 = Operational Amplifier Frequency Response (dB) :

pees

culs

100+

—r

807

0°

+ 4

Voltage gain

643

+ —45°

607

ccocamal ah

4

404

Phase shift

—90°

50+

eee

sl

qf 0

1

10

Pet

100

1k

10k

100k

Frequency

Figure 15-3

+

(Hz)

{1M

800 kHz

Approximate gain/frequency and phase/frequency

responses for a 741 op-amp.

The AD843 frequency response in Fig. 15-4 shows an open-loop gain of 90 dB at low frequencies, falling off at 20 dB per decade to A, = 1 at 34 MHz. Instead of the open-loop phase shift, the phase margin is plotted versus frequency. The phase margin is close to 90° over much of the frequency range, starts to become

and falls to approximately

smaller around 3 MHz,

40° at

f =34MHz.

Amplifier Stability and Gain From Eq. 13-3, the overall voltage gain of an amplifier with negative feedback is 1

Act * 5 (dB)

Voltage

100

100°

80

80°

60

60°

40

40°

20

20°

gain

0°

0

Figure

Phase margin

100

15-4

1k

10k

100k 1M Frequency

10M]100M 34 MHz

(Hz)

Approximate gain/frequency and phase-

op-amp. margin/frequency response for an AD843

644

Electronic Devices and Circuits

and the loop gainfa is

Ae A,B ©~ Aen

So the loop gain (A,B) equals 1 when Aci = Ay

This is one of the conditions required for circuit oscillation. To determine if oscillation will occur in a given circuit, it is necessary first to find the frequency at which Aci, ~ Av, and then to determine

the op-amp

phase

margin at that frequency.

Example 15-1 The inverting amplifier in Fig. 15-5 is to be investigated for stability. Determine the frequency at which the loop gain equals 1, and estimate the phase margin if the operational amplifier is (a) one with the gain/frequency characteristics in Fig. 15-2, (b) a 741, and (c) an

AD843. Figure

Solution

15-5

Inverting

amplifier circuit for Ex. 15-1.

(a) Refer to the A,/f and 6/ f graphs reproduced in Fig. 15-6 (from Fig. 15-2). Act = Ry _ 560 kO Ry 18k0 = 311

or

Act = 20 log 311

~50 dB Draw a horizontal line on the frequency response graph at A, = Ac, = 50 dB (Fig. 15-6). Draw a vertical line where the horizontal line intersects the A,/f

graph. The frequency at this point is identified as f2. f2® 150 kHz (logarithmic scale) From the 6/f graph, the op-amp phase shift at fy is

= —165° The loop phase shift is

di = 8 — 180° = —165° — 180° = —345°

and

$m = 360° — py = 360° — 345° = 15°

Chapter 15

_—— (dB)

t

104 100

a

a

90

PN

80

oN

gain

1

A"

N

70 loop

+ —45°

os

T _o9¢ IN

60

_I

AN

N

50

—180°

7 a |

30

se

GR

+

|

;

§

4+ -135°

L Oe eee cies ee

op

a0" smn: stance

645

Operational Amplifier Frequency Response

+ ~295°

N

i

20 |

100

Figure 15-6

1k

10k 100k Signal frequency h

(kHz)

1M

A,/f and 6/f characteristics for the op-amp in Ex. 15-1a.

Because the phase margin is less than 45°, the circuit is likely to be unstable. (b) For a 741:

A horizontal line at 50 dB on the frequency response in Fig. 15-3 gives fp¥1.5kHz and @*—90°

dy, = —90° — 180° = -270° bm = 360° — 270°

and

= 90° (stable circuit) (c) For an AD843:

Ahorizontal line at 50 dB on the frequency response in Fig. 15-4 gives

fx 90 kHz

|

$m * 90° (stable circuit)

and

50 dB A circuit with the frequency response in Fig. 15-6 and with Ac, =

= 70 dB, reconsideration was shown to be unstable. If the amplifier had Aci

shows that it is stable. That is, an amplifier with a high closed-loop gain is more likely to be stable than one with the lower gain. Low-gain amplifiers are more difficult to stabilize than high-gain circuits. The voltage follower

s to (with a closed-loop gain of 1) can be one of the most difficult circuit

stabilize.

646

Electronic Devices and Circuits

Some internally compensated op-amps are specified as being stable to closed-loop

gains

as

low

as

5.

In

this

case,

external

compensating

components must be used with lower gain circuits.

Practice Problem 15-1.1 Investigate the stability of an inverting amplifier with a closed-loop gain of 60 dB if the operational amplifier is (a) one with the gain/ frequency characteristics in Fig. 15-2, (b) a 741, and (c) an AD843.

15-2

FREQUENCY COMPENSATION

METHODS

Phase-Lag and Phase-Lead Compensation Lag compensation stabilize op-amp additional phase still so small that

and lead compensation are two methods often employed to circuits. The phase-lag network in Fig. 15-7a introduces lag at some low frequency where the op-amp phase shift is additional phase lag has no effect. It can be shown that at

frequencies where Xc; >> R», the voltage v2 lags behind v; by as much as 90°.

At higher frequencies where Xc

“< R2, no significant phase lag occurs, and

the lag network merely introduces some attenuation. The effect of this attenuation is that the A,/f graph is moved to the left, as illustrated in Fig. 15-7b. Thus, the frequency (fa) at which A,B = 1 [for a given closed-loop Ry

Wr

R,

CG

Cy Oh

02

v7

R2

v2

Ry

(a) Lag compensation network

(c) Lead compensation network

ecco

e

|

Pw | psec

|

“(Compen sated | — 45° BF Fesporise

as

f

~ Uncompens

ted 7

_ofrespins f

fa

x1

(b) Effect of lag compensation

Figure 15-7

0°

|

tN

ia

—90°

Ps.

—_

Be

0

¥

(d) Effect of lead compensation

A phase-lag network reduces an amplifier open-loop gain, so that the phase

shift at AB = 1 is too small for instability. A phase-lead network cancels phase lag.

Chapter 15 — Operational Amplifier Frequency Response __6 47

gain (Act)] is moved to a lower frequency (f,2), as shown. Because fxz is less than f,1, the phase shift at fo is less than that at f,; and the circuit is likely to be stable. The network in Fig 15-7c introduces a phase lead. In this network, when

Xci >> R1, the voltage v2 leads v,. This phase lead cancels some of the unwanted phase lag in the operational amplifier 0/f graph (see Fig. 15-7d),

thus rendering the circuit more stable. Phase-lag and phase-lead networks

are both used internally to compensate op-amp circuits. Both types of circuit

can also be used externally.

Manufacturer’s Recommended Compensation Most currently available operational amplifiers contain internal compensating components and do not require additional external components. Some have internal compensating resistors and need only a capacitor connected externally to complete a compensating network. For those that require

compensation,

IC

component

recommended

list

manufacturers

values and connection methods on the op-amp data sheet. An example of this is illustrated in Fig. 15-8 for the LM108.

(dB) 120

100+—%p

2 RiX30PF ¢, (a) Phase lag compensation

80 --— Voltage

60

gain 40 +--+

20 +

0 (b) Alternate phase lag

1

leon se

she Nhe

ses a Bh

10

100

NL

2

1k 10k Frequency

_

100k

+>

1M

(Hz)

(c) Approximate gain/frequency response

compensation Figure 15-8

quency Manufacturer’s recommended compensation methods and gain/fre

response for the LM108 op-amp. (Reproduced with permission of National Semiconductor Corp.)

648

Electronic Devices and Circuits

When

standard

value

compensating

R, —W\y——

capacitors are selected, the next larger values should be used. This is termed over-

" compensation and it results in better amplifier oN R

2

stability, but it also produces a smaller circuit

bandwidth.

: R

Example 15-2 The inverting amplifier in Fig. 15-9 is required to amplify a 200 mV input by a factor of 4.5. Determine suitable component values.

E

a Figure 15-9

—Vap Cy Op-amp circuit

for Ex. 15-2.

Solution

Because the LM108 has a very low input bias current (see data sheet A-14 in Appendix A), it should be treated as a BIFET op-amp. Select

R, = 1MQ Ry

=

Rg Aci

1I1MQ 4.5

eS

= 222 kO, (use 220 kO standard value) R3 = Ri||Ro = 220 kQ||1 MO = 180 kO, (standard value)

From

ie 158 Fig.

c, — RX 30pF _ 220k0 x 30 pF

15-8,

fR,

+R.

220kQ0 +1MQ

= 5.4 pF (use 10 pF standard value for over-compensation)

Connect C; between terminals 1 and 8, as shown in Fig. 15-9. Miller-Effect Compensation Miller effect (discussed in Section 8-3) involves capacitance between the output

and

input

terminals

of

an

inverting

amplifier.

Miller-effect

compensation of an op-amp circuit is very simple, and it is often the only external method

available for stabilizing a circuit where

the

op-amp

is

internally compensated. A capacitor (C;) is connected across the feedback

resistor (R¢), as shown in Figs 15-10a and b. The capacitor value is calculated to have an impedance equal to the feedback resistor value at the desired

signal cutoff frequency (f2):

Xcp= Reat f.

(15-1)

Chapter 15

Operational Amplifier Frequency Response

(a) Inverting amplifier with Miller-

(b) Non-inverting amplifier with

effect compensation Figure 15-10

649

Millér-effect compensation

Miller-effect frequency compensation for amplifier circuits.

This reduces the closed-loop gain by 3 dB at the selected frequency. So long as the op-amp is stable at this frequency, the circuit will not oscillate. The opamp used should have an upper cutoff frequency much higher than f2.

Example 15-3 Calculate a suitable Miller-effect capacitor to stabilize the circuit in Fig. 15-10a at fo = 35 kHz.

Solution

From

Eq. 15-1 er

(eg £ OnfyR;

: X 68kO 2m X 35kHz

~ 67 pF (use 68 pF standard value)

Pract

em:

15-2.1 The components

of the lag and

lead

compensation

network

in

"Fig. 15-7 are Rj = 6.8 kO, Rp = 390 0, and C; = 500 pF Calculate the

| 15-2.2 Calculate a suitable Miller-effect capacitor to stabilize the circuit in

Fig, 15-10b at fo = 50 kHz.

-mee-—

- ew ew

-

oes “approximate phase lag and phase lead at a frequency of 50 kHz.

15-3

OP-AMP

CIRCUIT BANDWIDTH

AND

SLEW RATE

Low Cutoff Frequency Operational amplifiers are direct-coupled internally, and so where they are

employed in direct-coupled applications, the circuit lower cutoff frequency (ft)

is zero.

In

capacitor-coupled

circuits,

the

lower

cutoff

frequency

is

650

Electronic Devices and Circuits

determined by the selection of coupling capacitors. The circuit high cutoff

frequency (f2) is, of course, dependent on the frequency response of the operational amplifier.

High Cutoff Frequency In Section 13-7 it is shown that for a negative feedback amplifier the high cutoff frequency occurs when the amplifier open-loop gain approximately

equals the circuit closed-loop gain:

Eq. 13-26:

:

Ao® Act

So, the circuit high cutoff frequency (f2) can be found simply by drawing a horizontal

line at A, ~ Ac,

on

the op-amp

open-loop

gain/ frequency

response graph. Because the op-amp low cutoff frequency (f;) is zero (as explained above), the circuit bandwidth is BW

=f.

-fi

=fr Consequently, the op-amp high cutoff frequency is often referred to as the

circuit bandwidth. The frequency response graphs published on manufacturer’s data sheets are typical for each particular type of operational amplifier. Like all typical device characteristics, the precise frequency response differs from one op-

amp to another. All frequencies derived from the response graphs should be taken as typical quantities. The process of determining circuit cutoff frequency from the op-amp frequency response graph is demonstrated in Ex. 15-4.

Example 15-4 Determine the typical upper cutoff frequency for the inverting amplifier in Fig. 15-11 when

the compensating

capacitor

(C;) value is (a) 30 pF and

(b) 3 pF. The A,/f graph for the LM108 is shown in Fig. 15-12. Solution

“0 KO AWN

— Rg _ 100k

Act = RS

TKO

= 100 = 40 dB

fr occurs at (a) For Cr = 30 pF:

Ay = Act= 40 dB ;

R

oN

+Meos 2

F

kt

3

ine R

“Veg

tt

Draw a horizontal line on the A,/f graph at

Ay = 40 dB.

Figure 15-11 for Ex. 15-4.

Amplifier circuit

Chapter 15

—

6511

= Operational Amplifier Frequency Response

(db) 120

100 80 Voltage gain

60 40

20} 10

100 1k Frequency

10k 8kHz

100k

1M

(Hz)

StraightFigure 15-12 line approximation of

LM108 gain/frequency response.

80kHz

Where the line cuts the A,/f characteristic for C; = 30 pF, read fr

8 kHz

(b) For Ce = 3 pF: Where the A, = 40 dB line cuts the A,/f characteristic for C; = 3 pF, read

fo 80 kHz Gain-Bandwidth Product The gain-bandwidth product (GBW), or unity-gain bandwidth, of an operational amplifier is the open-loop gain at a given frequency multiplied by the frequency. Referring to the A,/f response for the 741 reproduced in Fig. 15-13, itis seen that at Ayia) = 104, the frequency is fia) + 80 Hz. Thus,

GBW = Aya) X fia) = 10* x 80 Hz =8xX10°

Similarly, at Aw) = 10, fo) © 80 kHz, again giving GBW = 8 x 10°. Also, at

Ayo = 1, fig * 800 kHz, once more giving GBW=8

x 10°. This last

determination explains the term unity-gain bandwidth, because the GBW is

simply equal to the frequency at which A, = 1. Because the high cutoff frequency for an op-amp circuit occurs when the closed-loop gain equals the open-loop gain, the circuit upper cutoff frequency can be calculated by dividing the gain-bandwidth product by the

closed-loop gain: GBW

haa

(15-2)

652

Electronic Devices and Circuits

(dB) +

120

105 + 100

Aya)

19 +

80

103+

60

an

102 +

40

Aro)

10 + 20

Voltage

|

bI

| Aye)

—>

i+

0

(Hz)

100 1k 10k Frequency ——>-

i) Figure 15-13

{100k

fey

|1M

fro

The gain-bandwidth product (GBW) for an operationa! amplifier can be

used to determine the cutoff frequency for any closed-loop gain.

It is important to note that Eq. 15-2 applies only to operational amplifiers that have a gain/frequency response that falls off to the unity-gain frequency at 20 dB/decade. Where the A,/f response falls off at some other rate, Eq. 15-2

cannot be used.

Example 15-5. Using the gain-bandwidth product, determine the cutoff frequencies for the circuit in Ex. 15-4 (reproduced in Fig. 15-14) when the compensating capacitor is (a) 30 pF and (b) 3 pF. Solution

(a) For C; = 30 pF: Referring to the LM108 A,/f graph for C; = 30 pF in Fig. 15-12, we see that

GBW = fat A, = 1 800 kHz

Eq. 15-2:

Bx GBW _ 800 kHz 2 Ags 100

Figure 15-14

for Ex. 15-5.

Amplifier circuit

Chapter 15

Operational Amplifier Frequency Response

653

= 8 kHz (b) For C¢ = 3 pF:

Referring to the LM108 A,/f graph for C; = 3 pF in Fig. 15-12, we see that

at Ay = 20 dB = 10, f=: 800 kHz

GBW =f X A, = 800 kHz x 10 = 8 MHz

152.

—g_GBW _8MHz

Ege

2

"Aa

100

= 80 kHz Full-Power Bandwidth and Slew Rate The A,/f response graphs, upper cutoff frequencies, and GBW specified on op-amp data sheets normally refer to the operational amplifier performance as a small-signal amplifier. In this case, the measurements are usually made for output amplitudes not exceeding 100 mV peak-to-peak. Where an amplifier

circuit has to pruduce a large output voltage, the op-amp full-power bandwidth (fp) must be used. The AD843 operational amplifier, for example, is specified as having a typical unity gain bandwidth of 34 MHz for an output amplitude of 90 mV peak-to-peak, and a typical full power bandwidth of 3.9 MHz when the output amplitude is 20 V p-to-p. The op-amp slew rate (SR) (see Section 14-9) can be used to calculate the

full-power bandwidth for a given output amplitude. For a sinusoidal voltage waveform, the fastest rate-of-change of voltage occurs at the point where the waveform crosses from its negative half-cycle to its positive half-cycle, and vice versa. This is illustrated in Fig. 15-15a. It can be shown that the voltage rate-of-change at this point is AV /At = 21 f Vp (volts/second)

The maximum rate-of-change of the waveform is limited by the maximum slew rate of the op-amp used. Where the waveform amplitude or frequency

AV

At

Maximum rate-of-change

(a) Sine wave maximum rate-of-change Figure 15-15

(b) Sine wave distortion caused by the slew rate

The op-amp slew-rate limits the upper cutoff frequency of an op-amp

circuit and the output amplitude at a given frequency.

654

Electronic Devices.and Circuits

is higher than the limits imposed by the slew rate, distortion will occur as illustrated in Fig. 15-15b. The slew rate can be equated to the sine wave rate-of-change:

SR = 27f,V,

(15-3)

where fp is the slew-rate limited frequency, or full-power bandwidth, and V, is the peak level of the circuit output voltage. Equation 15-3 can be used to determine the full-power bandwidth of an op-amp circuit for a given Output voltage amplitude. Sometimes Eq. 15-3 gives an fp value greater than that

determined from the A,/f graph or the GBW product. In these cases, the

circuit bandwidth is still dictated by the A,/f graph or the GBW product. Example 15-6 (a) Calculate the full-power bandwidth for an

AD843 op-amp circuit (Fig. 15-16), given a 1 V peak input and op-amp slew rate of 250 V/s. (b) Determine

the

maximum

peak

output

voltage obtainable from a 741 op-amp circuit with a 100 kHz signal frequency. (SR = 0.5 V/s for a 741.)

Solution

Figure 15-16

(a) For the AD843:

siliaalaathes

Ry+ Rs

Yee

Amplifier circuit

ong

Mie

_ 39kO + 4.7kO

azeg

TV

=93V

_

From Eq. 15-3,

SR

Po 2nV,

_ 250V/ps

20X93V

= 4.2 MHz

(b) For a 741: From Eq. 15-3,

0.5 V/s V= SR P 24 fo ~ 2a X 100 KHz =0.79V

Practice Problems,

:

15-3. 1 Determine the typical upper

:

cutoff

frequency

for

an

inverting

amplifier with a closed-loop gain of 15 using a 741 op-amp. The A,/f “graph for the 741 is shown in Fig, 15-13.

Chapter 15 —

Operational Amplifier Frequency Response

655

15-3.2 Using the gain-bandwidth product, calculate the cutoff frequencies

for an inverting amplifier with a closed-loop gain of 30 when the Oop-amp used is (a) 741 and (b) an AD843.

15-3.3 Calculate the full-power bandwidth for an LF353 op-amp circuit with

a4 V peak-to-peak output voltage. 15-4 STRAY CAPACITANCE EFFECTS Stray capacitance (C,) at the input terminals of an operational amplifier

effectively introduces an additional phase-lag network in the feedback loop (see Fig. 15-17), thus making the op-amp circuit unstable. Stray capacitance problems can be avoided by good circuit construction techniques that keep the stray to a minimum. The effects of stray capacitance also depend upon the resistor values used in the feedback network. High resistance values make it easier for small stray capacitances to produce phase lag. With low resistances, small stray capacitances normally have little effect on the circuit

stability. Ry

W\id Vee

Rj + (Ry + fs) | Ro

“T

—Ver

(b) C, and its series resistance

(a) Stray capacitance (C,) at amplifier input Figure 15-17

Stray capacitance can cause instability in an op-amp circuit by introducing

additional phase lag in the feedback network.

Analysis of an RC phase-lag circuit shows that the capacitor voltage lags behind the input voltage by 45° when the capacitor impedance (Xc) equals the series resistance (R). Also, when Xc = 10R, the phase lag is approximately 10°; it is this 10° of additional phase lag that might make the circuit oscillate if its phase margin is already close to the minimum for stability. If the phase margin is known to be large at the frequency where A,B = Ac, (the

frequency at which the circuit is likely to oscillate), the stray capacitance may be unimportant. Where the phase margin is small, for circuit stability the opamp input stray capacitance should normally be much less than 1

Cs = dr F(1OR)

(15-4)

656

Electronic Devices and Circuits

where R

with

is the equivalent resistance in series

the

stray

capacitance.

In

Fig.

2

15-17,

I :

R = R3 + (Ri + 7,)||Ro.

|

AAA}

From Eq. 15-4 it is seen that (as already

2

mentioned) the larger the resistor values, the

cc

smaller the stray capacitance that can produce

circuit

instability.

If the

signal

source

+—|-

is

ate

disconnected from the circuit, R becomes equal to (Ro + Rs), which is much larger than

L =p

[Re + (fs +Ri)|[R2].

In

this

situation,

an

extremely small stray capacitance can make the circuit unstable.

=

figure 15-18

ile

2 ~Veg

Use of Miller

effect compensation for

stray Capacitance at the

Miller-effect compensation can be used to

re

al

compensate for stray capacitance at an op-amp

input, as shown in Fig. 15-18. To eliminate the phase shift introduced by the stray capacitance,

the division

of the output

voltage produced by C, and C) in series should be equal to the division produced by R, and R>. Therefore,

Kea By This gives

Xeo

R,

C2R2

= CSR

(15-5)

Note that Eq. 15-5 does not allow for r, or R3 in Fig. 15-17. Where r, is not very much smaller than Rj, it must be added to R;. Also, resistor R3 could be

bypassed with another capacitor to reduce the total series resistance.

Example 15-7 Calculate the op-amp input terminal. stray capacitance that might cause instability in the circuit of Fig. 15-19 if the amplifier cutoff

frequency is 800 kHz. Determine a suitable Miller-effect compensating capacitor value. Solution

Stray capacitance: Eq. 15-4:

Gy

1

~ Qa X 10[(rz + Ry)|| Ral

Figure 15-19

Op-amp

amplifier circuit for Ex. 15-7.

Chapter 15

Operational Amplifier Frequency Response

657

1 ~ 2a X 800 kHz X 10[(600 2 + 1kQ)|}10 kQ]

= 14.4 pF Compensation:

hes

c ee. Ry

14.4

pFx (6000 ee 10 kO

+ 1kO

= 23 pF

Practice Problems 15-4.1 Determine the op-amp

input stray sapacitaxgen that might cause

instability in an inverting amplifier with Ry= 1.8 kOQ, Ro= 560 kQ, and f, = 600 kHz (a) when the signal source is open-circuited, and (b) when 7, = 600 O and Rj and R2 are reduced by a factor of 10.

15-4.2 Determine a suitable Miller-effect compensating capacitor value for the circuit in part (b) of Problem 15-4.1.

15-5

LOAD CAPACITANCE EFFECTS

Capacitance connected at the output of an operational amplifier is termed load capacitance (C_). Figure 15-20 shows that C_ is in series with the op-amp output resistance (ro), so that C, and r, constitute a phase-lag circuit in the

feedback network. As in the case of stray capacitance, another 10° of phase lag introduced by Cy and r, could cause circuit instability where the phase margin is already small. The equation for calculating the load capacitance that might cause instability is similar to that for stray capacitance: it

1-5 f(10r,) i :

cc

~1LE Figure 15-20

Load capacitance at an op-amp output can cause instability by

introducing additional phase lag in the feedback network.

(15-6)

658

Electronic Devices and Circuits

In Eq. 15-6, f is the frequency at which A,B = Act. If fo is reduced, Eq. 15-6 gives a larger C, value. Thus, an op-amp with a low output resistance can tolerate more load capacitance than one with a higher output resistance.

One method often used to counter instability caused by load capacitance

is shown in Fig. 15-21a. A resistor (R,), usually ranging from 12 2 to 400 0, is connected in series with the load capacitance. The presence of R, (with R,

connected at the op-amp output) can severely reduce the phase lag produced by ro and C,. However, R, also has the undesirable effect of increasing the circuit output impedance to approximately the resistance of Ry. A Miller-effect capacitor (C2) connected across feedback resistor R, may be

used to compensate for the load capacitance (see Fig. 15-21b). In this case, C, introduces some phase lead in the feedback network

to counter the phase

lag. The equation for calculating a suitable capacitance for C) is, once again, similar to that for stray capacitance: CoR>

=

CLLo

(15-7)

C2

=} | 71

Ry

WW, - Vee

Ry

ot v

Cy

(b) Miller-effect compensation for C;

Ry Cy +Voc

oN

R

ig R3

= Ver

“LT |

(c) Inverting amplifier with combination of R, and C, for C, compensation

Figure 15-21

ty (d) Non-inverting amplifier with R, and C, combination for Cy compensation

Compensation methods for load capacitance.

Chapter 15

Operational Amplifier Frequency Response

659

A modified form of Miller-effect compensation for load capacitance is shown in Fig. 15-21c. An additional resistor (Rx) is included in series with Cy

to reduce the phase lag. But now, R2 is connected at the junction of Rx and C_,

so that (because of feedback) R, has no significant effect on the circuit output impedance. Also, C2 is connected from the op-amp output terminal to the

inverting input. With this arrangement, Eq. 15-7 is modified to

CR. = Ciro +R)

(15-8)

It should be noted from Eqs 15-7 and 15-8 that, as for stray capacitance, smaller resistance values for R give larger, more convenient compensating

capacitor values.

Example 15-8 Calculate the load capacitance that might cause instability in the circuit of Fig. 15-22a if the amplifier cutoff frequency is 2 MHz and its output resistance is 25 Q. Determine a suitable compensating capacitor value for the circuit as modified in Fig. 15-22b with a 0.1 wF load capacitance. Solution Load capacitance: i Eq.

15-6:

Cr

~ Qnf(l0r,) = 318 pF

(a) Non-inverting amplifier with

load capacitance (C;) Figure 15-22

Circuits for Ex. 15-8.

i

2a X 2MHz x 10 x 250

(b) Amplifier compensated with

R, and C,

J

660

_Flectronic Devices and Circuits

/ Compensation:

, Eq. 15-8:

ar_

(25.0 + 25 0) City + Ry rin_ 0.1 pF X aca

= 500 PF —

a)

Practice Problems | 15-5.1

Calculate the load capacitance that might cause instability in the

circuit in Ex. 15-7 if the op-amp output resistance is 20 9. Determine

___ asuitable Miller-effect compensating capacitor value.

15-5. 2° The circuit in Problem 15-5.1 is modified as in Fig. 15-21c with R, = 8) Ro and Cy, = 0.5 pE. Calculate the required C value.

15-6

CIRCUIT STABILITY PRECAUTIONS

Power Supply Decoupling Feedback along supply lines is another source of op-amp circuit instability.

This can be minimized by connecting 0.01 wF high-frequency capacitors from

each supply terniinal to ground (see Fig. 15-23). The capacitors must be

connected as closely as possible to the IC terminals. Sometimes larger-value

Capacitors are required.

a Vee

Supply decoupling capacitors

Signal

source connected

Small-value resistors

Figure 15-23 For op-amp et 5 : circuit stability, keep resistor values to a minimum, use the recommended compensating componenis, bypass the supply terminals to ground, and keep the signal source connected.

Stability Precautions The following precautions should be observed for circuit stability:

1. Where low-frequency performance is required, use an internally compensated op-amp. Alternatively, use Miller-effect compensation to give the lowest acceptable cutoff frequency. 2. Use small-value resistors in the feedback network if possible, instead of

using the largest possible resistor values.

oe .

t

ated

'

3. With an. op-amp wut by Mot components

4, Keep all component

2rational Amplifier Frequency Response

resistorOr ;

. pF

ca

|

ck

Sey

acitors

‘

|

© circuit in Fig. 15-10a if the op-amp has the

of ‘the op-amp vg@. amp is: a 741.

Connect these capa

5

citors close to the? jney for the circuit in Fig. 15-19 if the op-amp is (a)

have a signal

6, Always

663

.

apa e

body r i

should have the eerie 0.1 ;

5, Use

ib)

as

Jeads as

t placement

iti

nt

*

.

ce col

sou” ting” product, determine the upper cutoff frequencies for

Alternatively, ground the circu

"A's 1,

small stray capacitances can causftn product to determine the upper cutoff frequencies

7. Do not connect

and b if they both have LM108 op-amps with C; =

ia

oti

terminals. Instrument input ¢

A if a dicuit is unstable aft/£xamples

observed, reduce the va

for

14-5 and

14-8 use 741

op-amps.

Use

,

the gain-

ncy for each circuit. the upper cutoff f frequency i duct to detetermine / Fig. 15-11 has the LM108 replaced with an LF353, use the gain-

resistors). Also, reduce product to determine the upper cutoff frequency.

the full-power bandwidth for an amplifier using a 741 op-amp if the

; ._./Oltage is to be (a) 5 V peak-to-peak and (b) 1 V peak-to-peak. Review Questio late the full-power lease each _ in eaviem 15-15 if the 741 yiaced with an LF353.

Section 15-1

culate the full-power bandwidth

for the circuit in Ex. 14-5 if the peak

15-1 Show howtput is to be 2 V. Determine the maximum peak output voltage that can be Explain throduced by the circuit at the cutoff frequency calculated in Problem 15-13. 15-2 Show fi Calculate the slew-rate limited cutoff frequency for the circuit in Ex. 14-8 if the Insta vaamaplengetti yin

os60>

aa

-

= peak input is 20 mV. Determine the maximum

peak output voltage at the

circuit cutoff frequency calculated in Problem 15-13.

Section 15-4

ah

15-19 A circuit as in Fig. 15-10a with C; removed has a cutoff frequency of 600 kHz. 1

Determine

the op-amp

input stray capacitance

that might

cause

instability

(a) when the signal source is open-circuited and (b) when a 300 Q signal source is connected.

15-20 Determine the input stray capacitance that might make the circuit in Fig. 15-10b become unstable when a 300 2 signal source is connected. Assume that the circuit cutoff frequency is 30 kHz and that C; is removed. 15-21 Calculate the Miller-effect capacitor value required to compensate for 250 pF of

input stray capacitance in the circuitry of Problem 15-19b. 15-22

Calculate the Miller-effect capacitor value required to compensate for 90 pF of

stray capacitance in the circuit of Problem 15-20.

15-23 An inverting amplifier (as in Figs 15-19) uses an LF353 op-amp and has r, = 600 , R; = 220 kQ, Rz = 2.2 MO, fo = 18 kHz. Calculate the input stray capacitance that might make the circuit unstable; (a) when the signal source is connected and (b) when the signal source is open-circuited.

15-24 Repeat Problem 15-23 when R; and R; are each reduced by a factor of 10.

‘ational Amplifier Frequency Response

ds component placem:

ent. A | res js

|

Y circuit in Fig. 15-10a if the op-amp has the

should have the resistor bod

5, Use 0,01 uF capacitors (of “amp (0! supply terminals of the oe a neil

ig.

itors clo

ct thes

come the sourcece |‘a a nena "ys 10) Alternatively, ground the circu!

“i 6 ,ii Always

small stray capacitances can cause

663

and 15-4. response graphs in Figs 15-3

Product to determine the upper cu toff frequencies for

ct oscilloscopes 9>-10a and b if they both have LM108 op-amps with C; = Do not conne 7, terminals. Instrument input ¢ 8. If a circuit is unstable a sbserved :

-xamples

14-5 and

14-8 use 741 op-amps.

Use the gain-

reduce the ¥ yf to determine the upper cutoff frequency for each circuit. ” Fig. 15-11 has the LM108 replaced with an LF353, use the gain-

resistors). Also, reduce Broduct to determine the upper cutoff frequency. the full-power bandwidth for an amplifier using a 741 op-amp if the .

:

Review Que stio

Bectiog 161 = 15-1

oltage is to be (a) 5 V peak-to-peak and (b) 1 V peak-to-peak.

late the full-power bandwidth in each case in Problem 15-15 if the 741 faced with an LF353.

ulate the full-power bandwidth for the circuit in Ex. 14-5 if the peak

Show how tput is to be 2 V. Determine the maximum peak output voltage that can be

Explainthroduced by the circuit at the cutoff frequency calculated in Problem 15-13. 2 Show f Calculate the slew-rate limited cutoff frequency for the circuit in Ex. 14-8 if the instal

Ry rd

peak input is 20 mV. Determine the maximum

peak output voltage at the

circuit cutoff frequency calculated in Problem 15-13.

Section 15-4

15-19 A circuit as in Fig. 15-10a with C; removed has a cutoff frequency of 600 kHz. 1

Determine the op-amp input stray capacitance that might cause instability (a) when the signal source is open-circuited and (b) when a 300 Q signal source is connected.

15-20 Determine the input stray become unstable when a circuit cutoff frequency is 15-21 Calculate the Miller-effect input stray capacitance in 15-22

capacitance that might make the circuit in Fig. 15-10b 300 2 signal source is connected. Assume that the 30 kHz and that C; is removed. capacitor value required to compensate for 250 pF of the circuitry of Problem 15-19b.

Calculate the Miller-effect capacitor value required to compensate for 90 pF of

stray capacitance in the circuit of Problem 15-20. 15-23 An inverting amplifier (as in Figs 15-19) uses an LF353 op-amp and has rs = 600 0, Ri = 220 kM, Ro = 2.2 MQ, fp = 18 kHz. Calculate the input stray capacitance that might make the circuit unstable; (a) when the signal source is connected and (b) when the signal source is open-circuited.

15-24 Repeat Problem 15-23 when R; and R; are each reduced by a factor of 10.

Chapter 15 — Operational Amplifier Frequency Response

663

Section 15-3 15-9 Determine the bandwidth of the circuit in Fig. 15-10a if the op-amp has the

gain/ frequency response graph in Fig. 15-2. Determine the bandwidth of the circuit in Fig. 15-10b if the op-amp is a 741. 15-10 Find the upper cutoff frequency for the circuit in Fig. 15-19 if the op-amp is (a) a 741 and (b) an AD843. Use the response graphs in Figs 15-3 and 15-4. 15-11 Using the gain-bandwidth product, determine the upper cutoff frequencies for

the circuits in Problem 15-10. 15-12 Use the gain-bandwidth product to determine the upper cutoff frequencies for

the circuits in Figs 15-10a and b if they both have LM108 op-amps with C; = 30 pF. 15-13 The circuits in Examples 14-5 and 14-8 use 741 op-amps. Use the gainbandwidth product to determine the upper cutoff frequency for each circuit. 15-14 If the circuit in Fig. 15-11 has the LM108 replaced with an LF353, use the gainbandwidth product to determine the upper cutoff frequency. 15-15 Calculate the full-power bandwidth for an amplifier using a 741 op-amp if the output voltage is to be (a) 5 V peak-to-peak and (b) 1 V peak-to-peak.

15-16 Recalculate the full-power bandwidth in each case in Problem 15-15 if the 741 is replaced with an LF353. 15-17 Calculate the full-power bandwidth for the circuit in Ex. 14-5 if the peak output is to be 2 V. Determine the maximum peak output voltage that can be

produced by the circuit at the cutoff frequency calculated in Problem 15-13. 15-18 Calculate the slew-rate limited cutoff frequency for the circuit in Ex. 14-8 if the peak input is 20 mV. Determine the maximum

peak output voltage at the

circuit cutoff frequency calculated in Problem 15-13.

Section 15-4 15-19 A circuit as in Fig. 15-10a with C; removed has a cutoff frequency of 600 kHz.

Determine the op-amp input stray capacitance that might cause instability (a) when the signal source is open-circuited and (b) when a 300 2 signal source

is connected. 15-20 Determine the input stray capacitance that might make the circuit in Fig. 15-10b become unstable when a 300 2 signal source is connected. Assume that the circuit cutoff frequency is 30 kHz and that C; is removed. 15-21 Calculate the Miller-effect capacitor value required to compensate for 250 pF of

input stray capacitance in the circuitry of Problem 15-19b, 15-22 Calculate the Miller-effect capacitor value required to compensate for 90 pF of stray capacitance in the circuit of Problem 15-20. 15-23 An inverting amplifier (as in Figs 15-19) uses an LF353 op-amp and has ts = 600 Q, Ry = 220 kO, Ro = 2.2 MQ, fp = 18 kHz. Calculate the input stray capacitance that might make the circuit unstable; (a) when the signal source is connected and (b) when the signal source is open-circuited. 15-24 Repeat Problem 15-23 when R; and R2 are each reduced by a factor of 10.

664

Electronic Devices and Circuits

Section 15-5 15-25 Determine the load capacitance that might cause instability in the circuit in

Fig. 15-10a with C; removed, if the circuit cutoff frequency is 600 kHz and fo = 100 0.

.

15-26 An inverting amplifier (as in Fig. 15-19) uses an op-amp with a 300 ©, output resistance,

and

has

R; = 220

kM

and

Rz=2.2

MQ.

Calculate

the load

capacitance that might make the circuit unstable. 15-27 Calculate the Miller-effect capacitor value required to compensate fora 0.1 pF load capacitance in the circuit of Fig. 15-10a if f, = 600 kHz. 15-28 Calculate the Miller-effect capacitor value required to compensate for the load capacitance in Problem 15-26.

a

a

15-29 Determine the load capacitance that might cause instability in the circuit in Fig. 15-22a if the cutoff frequency is 400 kHz, and the op-amp has an r, of 150 ©.

.

.

15-30 The circuit in Problem 15-29 is rearranged as in Fig. 15-22b with R, = 107.. Calculate the required C2 value to compensate for a 5000 pF load capacitance.

Practice Problem Answers 15-1.1 15-2.1

45°, 90°, 90° —48.5°, 415°

15-2.2

82pF

15-3.1 15-3.2 15-3.3

50 kHz 27 kHz, 1.13 MHz 296 kHz

15-4.2

0.5 pF

15-4.1

15-5.1 15-5.2

,

0.05 pF, 34.5 pF 995 pF, 2 pF 6000 pF

CHAPTER 16 Signal Generators Objectives You will be able to:

1 Draw the following types of sine wave oscillator circuits and explain the operation of each:

Analyze square and triangular waveform generators to determine the amplitude and

phase-shift, Colpitts, Hartley,

frequency of the output

and Wein bridge. 2 ceoaly2e

an a the above

ciara boten .

8 Design square and triangular

oscillator circuits to determine the oscillation frequency.

waveform generators to

3 Design each of the above

produce a specified output

oscillator circuits to produce a

amplitude and frequency.

specified output frequency. 4 Sketch oscillator amplitude stabilization circuits and explain their operation.

Design circuits to limit oscillator outputs to a specified amplitude. Draw square-wave and triangular-wave generator circuits. Sketch the circuit waveforms, and explain the operation of each circuit.

9 Analyze and design pulse generator circuits using 555 IC timers. 10 Explain piezoelectric crystals

and sketch the crystal equivalent circuit and the crystal impedance/frequency graph. 1

Show how crystals may be used for oscillator frequency stabilization, and design crystalcontrolled oscillators.

INTRODUCTION A sinusoidal oscillator usually consists of an amplifier and a phase-shifting network. The amplifier receives the output from the network, amplifies it, phase-shifts it by 180°, and applies it to the network input. The network

phase shifts the amplifier output by a further 180° and attenuates it before feeding it back to the amplifier input. When the amplifier gain equals the inverse of the network attenuation, and the amplifier phase shift equals the

network phase shift, the circuit is amplifying an input to produce an output

666

Electronic Devices and Circuits

which is attenuated to become the input. The circuit is generating its own

input signal, and a state of oscillation exists. Some signal generators produce square or triangular waveforms. These normally use non-linear circuits and resistor-capacitor charging circuits.

16-1

PHASE SHIFT OSCILLATORS

Op-Amp Phase Shift Oscillator Figure 16-1 shows the circuit of a phase shift oscillator, which consists of an inverting amplifier and an RC phase-shifting network. The amplifier phaseshifts its input by —180°, and the RC phase-lead network phase-shifts the amplifier output by a +180°, giving a total loop phase shift of zero. The attenuated feedback signal (at the amplifier input) is amplified to reproduce

the output. In this condition the circuit is generating its own input signal; consequently, it is oscillating. The output and feedback voltage waveforms in Fig. 16-1 illustrate the circuit operation.

For a state of oscillation to be sustained in any sinusoidal oscillator circuit, certain conditions, known as the Barkhausen criteria, must be fulfilled:

The loop gain must be equal to (or greater than) one.

The loop phase shift must be zero. The RC phase-lead network in Fig. 16-1 consists of three equal-value resistors and three equal-value capacitors. Resistor R; functions as the last feioaa

ee

|

Inverting

| amplifier

pss |

ie

Ry

I

Hy if

|

| L

| |

_

!

|

|

! |

!

|

SS

7

| (Rs |

Le

| | om

ee

ee

Se

z

~=4--4__ U%

Output voltage

fYols

"0 —

=

U¢

_tI__

a

ag

NX voltage

oo, I | | | | |

Figure 16-1

A phase shift oscillator consists of an inverting amplifier and an RC phase

shifting feedback network. The RC network attenuates the output and phase-shifts it by

180°. The amplifier amplifies the network output and phase-shifts it through a further 180°.

Chapter 16 _— Signal Generators

667

resistor in the RC network and as the amplifier input resistor. A phase-lag network would give a total loop phase shift of —360°, and so it would work

just as well as the phase-lead network. The frequency of the oscillator output depends upon the component values in the RC network. The circuit can be analyzed to show that the phase shift is 180° when Xc

=

V6R

This gives an oscillation frequency: f

—

(16-1)

Pee Se

QaRCV6

As well as phase-shifting the amplifier output, the RC network attenuates the output. It can be shown that, when the required 180° phase shift is

produced, the feedback factor (B) is always 1/29. This means that the amplifier must have a closed-loop voltage gain (Acz) of at least 29 to give a loop gain (BAc_) of one; otherwise the circuit will not oscillate. For example,

if the amplifier output voltage is 10 V, the feedback voltage is vg = Buy = 10 V/29 To reproduce the 10 V output, v; must be amplified by 29: Vo = Ac Ug = 29 X (10 V/29)

=10V

If the amplifier voltage gain is much greater than 29, the output waveform

will be distorted. When the gain is slightly greater than 29, a reasonably pure sine wave output can be expected. The gain is usually designed to be just over 29 to ensure that the circuit oscillates. The output voltage amplitude normally

peaks

at +(Vcc — 1 V) unless a

rail-to-rail op-amp

is used

(see

Section 14-9).

Op-Amp Phase Shift Oscillator Design Design of a phase shift oscillator begins with design of the amplifier to have a closed-loop gain just greater than 29. The resistor values for the RC network are then selected to be equal to the amplifier input resistor (R,), and the capacitor values are calculated from Eq. 16-1. In some cases, this procedure might produce

capacitor values not much larger than stray capacitance. So,

alternatively, the design might start with selection of convenient capacitor

values. Equation 16-1 is then used to calculate the resistance of R (and Rj). Finally, Rz is calculated to give the required amplifier gain.

668

Electronic Devices and Circuits

Example 16-1 Using a 741 op-amp witha +10 V supply, design the phase shift oscillator in

Fig. 16-2 to produce a 1 kHz output frequency.

B 180 ka Vec

5:6 kO

R3

Ver

180 kO

-10V

0.01 pF 0.01 pF 0.01 pF

‘Figure 16-2

Ex. 16-1.

Phase shift oscillator circuit for

Solution

Select

I, © 100 X Ipinaxy = 100 X 500 nA = 50 pA

Up ®H(Vec — 1 V)¥4(10V - 1 V) ~wt9V me

Y%

'

Ac

_

+9V

29

= 40.31 V _%

031V

11,

50pA

= 6.2 kO, (use 5.6 kO standard value) '

IRo = AcuRy = 29 X 5.6kO,

& 162: kO (use 180 kQ. to give Ac; > 29)

Rg = Ro = 180 kQ, (the de path through R, is interrupted by C) R=R, =5.6kQ

Chapter 16 —‘ Signal Generators

From Eq. 16-1:

C=

1

2aRFV6

669

1

_

2a x 5.6kO X 1kHz x V6

0.01 wF (standard value) Although the 741 op-amp used in Ex. 16-1 is likely to be quite suitable for the particular circuit, some care should always be taken when selecting an operational amplifier. It should be recalled (from Chapter 15) that when a

large output voltage swing is required, the op-amp full-power bandwidth is involved. This must be considered when selecting an operational amplifier

for an oscillator circuit.

A phase shift oscillator using a single BJT amplifier is shown in Fig. 16-3. Once again, the amplifier and phase shift network each produce 180° of phase shift, the BJT amplifies the network output, and the network attenuates the amplifier output. First thoughts about this circuit (in comparison to the op-amp phase shift oscillator) would suggest that a BJT amplifier with a voltage gain of 29 is required. An attempt to design such a

circuit reveals that in many cases the

amplifier output is overloaded by the phase shift network, or else the network output is overloaded by the amplifier input. The problem can be solved by including an emitter follower in the circuit. However, the circuit Sry | Inverting | amplifier, |

| a

Output voltage

%

et

ae Seete

pag Nea #> tee aaeestninee prepasted

LE maith

merge > Xc)).

a 40 kHz

output

frequency. Use a 100 mH inductor and an op-amp with a +10 V supply. R

2

270 kO AM\+10V

Ry 27 kO

, R3

27ko
> Z, of the amplifier Sen =

1

_

2afC,

1 2a X 40 kHz

x 1500 pF

= 2.65 kO,

Ri >

Xca

Ry = 10Xq = 10 X 2.65 kO,

Select

= 26.5 kO (use 27 kO standard value)

From Eq. 16-6,

C,

1500 pF

Aci(min) = CG

180 pF

= 8.33

Rp = ActRi = 8.33 X 27 kO

= 225 kQ, (use 270 kO standard value)

Rg = Ry||Ro = 27 kO||270 kO = 24.5 kQ (use 27 kO standard value) when The op-amp full-power bandwidth (fp) must be a minimum of 40 kHz

0% 49 V and Act = 8.33.

From Eq. 15-2,

fr = Aci

fo = 8.33 X 40 kHz

= 333 kHz

674

Electronic Devices and Circuits

From Eq. 15-3,

SR = 2nfpUp = 20 X 40 kHz X 8V =2V/yus

BJT Colpitts Oscillator A Colpitts oscillator using a single BJT amplifier is shown in Fig. 16-6a. This

is the basic circuit, and its similarity to the op-amp Colpitts oscillator is fairly obvious. A more complex version of the circuit is shown in Fig. 16-6b. Components

Qi, Ri, Rz, Rg, and Cg in (b) are unchanged

from

collector resistor Rc is replaced with inductor L;. A radio frequency

(a), but choke

(RFC) is included in series with Vcc and L;. This allows dc collector current

(Ic) to pass but offers a very high impedance at the oscillating frequency, so that the top of L; is ac isolated from Vcc and ground. The output of the LC network (L;, Cy, C2) is coupled via Cc to the amplifier input. The circuit

output voltage (v,) is derived from a secondary winding (Lz) coupled to L;. As in the case of the BJT phase shift oscillator, the transistor current gain is

important. Circuit analysis gives Eq. 16-4 for frequency. For current gain, Kein e(min) =

ov.

amplifier

"ma

f—-— a —a—ar

Inverting

(16-7)

BS Re

Ve e

R,

RFC

Ce

— FI

se

Ly Ts. -4----------

(a) Basic circuit Figure 16-6 network.

Ci Cs

4

Q;

(b) Practical circuit

Colpitts oscillator using an inverting BUT amplifier and an LC feedback

675

Chapter 16 —_ Signal Generators

Practice Problems 16-2.1 Design a Colpitts oscillator circuit to produce a 12 kHz, +10 V output.

Use a 741 op-amp.

—

6 V p-to-p 16-22 Design the oscillator in Fig. 16-6a to produce a 20 kHz, output. Use.a10 mH inductor and assume that the BJT has hp» ~ 26 0

and hie ¥ 1.5 kQ.

16-3 HARTLEY OSCILLATORS Op-Amp Hartley Oscillator

The Hartley oscillator circuit is similar to the Colpitts oscillator, except that the feedback network consists of two inductors and a capacitor instead of two capacitors and an inductor. Figure 16-7a shows the Hartley oscillator circuit,

and Fig. 16-7b illustrates the fact that L; and L, may be wound on a

single

core so that there is mutual inductance (M) between the two windings. In this

case, the total inductance is Ly = L} + L, + 2M

(16-8)

Oscillation occurs at the feedback network resonance frequency: 1

* LVS

| Inverting

eS

(16-9)

2a V (CyL7) F?.C~*~=C—s=sSN

| amplifier

Cy UE

bf (b) L; and L, wound (a) Oscillator circuit

“igure 16-7

ona single core

Hartley oscillator circuit using an op-amp inverting amplifier and an LC

feedback network.

676

Electronic Devices and Circuits

The attenuation of the feedback network is

ax

Xi — Xc1 It can be shown that the required 180° phase shift occurs when

Xia = Xn — Xa The loop gain must be a minimum of one, giving L AcL(min) = ies

(16-10)

Design procedure for a Hartley oscillator circuit

is similar

to

that

for

a Colpitts

oscillator.

Example 16-3

a

Design the Hartley oscillator in Fig. 16-8 to

i eO

produce a 100 kHz output frequency with

an amplitude of approximately +8 V. For

Rs

simplicity, assume that there is no mutual inductance between L; and Ly».

=

Solution Vec®Up +1V =4H(8V+1V) Zt9V X12 >> Z, of the amplifier

Figure 16-8

Hartley oscillator

circuit for Ex. 16-3.

Select

Xr %1kO I,

= Xr2

a

1kQO

Qf

2a X 100 kHz

= 1.59 mH (use 1.5 mH standard value) Ly

Select

Ly

=

10

1.5 mH

=

10

= 150 wH (standard value)

Ly = Ly + Lz = 1.5mH + 150 pH (assuminMg = 0) = 165mH

Chapter 16 _ Signal Generators

Cy ae

From Eq. 16-9,

677

1

4m’ f?Ly

4a? x (100 kHz)? x 1.65 mH

= 1535 pF (use 1500 pF with additional parallel

capacitance, if necessary)

C; >> stray capacitance

Xi = 2afLy = 2m X 100 kHz X 150 pH = 94.20, Ry > Xiu

Select

R,; = 1 kQ (standard value)

From Eq. 16-10,

fee

2 _ 1.5mH 1

150 pH

= 10

R2 = ActRi= 10 X 1 kO, = 10 kO (standard value)

Rg = Ry||Rp = 1kQ|[10kO = 909 © (use 1 kO standard value) The op-amp full-power bandwidth when U, © +8 V and Ac, = 10. From Eq. 15-2,

(fp) must be a minimum

of 100 kHz

fox = Act X f = 10 X 100 kHz = 1 MHz

From Eq. 15-3,

SR = 2mfpvp = 2m X 100 kHz X 8V =5V/ps

BJT Hartley Oscillator Figure 16-9 shows the circuit of a Hartley oscillator using a BJT amplifier. The basic circuit in Fig. 16-9a is similar to the op-amp Hartley oscillator, and its

operation is explained in the same way as for the op-amp circuit. Note that coupling capacitors Cc and Cy are required in order to avoid dc-grounding the transistor base and collector terminals through L; and Ly». In the practical BJT Hartley oscillator circuit shown in Fig. 16-9b Ly, Lz, and C; constitute the phase shift network. In this case, the inductors are directly connected in place of the transistor collector resistor (Rc). The circuit

output is derived from the additional inductor winding (L3). The radio

678

Electronic Devices and Circuits

(a) Basic circuit

Figure 16-9

(b) Practical circuit

Hartley oscillator consisting of a BUT inverting amplifier and an LC feedback

network.

frequency choke (RFC) passes the direct collector current, but ac isolates the upper terminal of L; from the power supply. Capacitor C2 couples the output of the feedback network back to the amplifier input. Capacitor C4 at the BJT

collector in Fig. 16-9a is not needed in Fig. 16-9b, because L» is connected directly to the collector terminal. The junction of L; and L2 must now be capacitor-coupled to ground (via C3) instead of being direct-coupled.

Practice Problems

=

16-3.1 A Hartley oscillator circuit using a 741 op-amp is to produce a 7 kHz,

+10 V output. Determine suitable component values. 16-3.2 Analyze the BJT Hartley oscillator in Fig. 16-9b to determine the oscillating frequency. The important component values are: yer ack = Ly = 47 mH, C; = 600 pE, and C2 = C3 = 0.03 pF. The mutual

_. inductance between Ly and L3 is 100 wH.

16-4 WEIN BRIDGE OSCILLATOR The Wein bridge is an ac bridge that balances only at a particular supply frequency. In the Wein bridge oscillator (Fig. 16-10), a Wein bridge circuit is used as a feedback network between the amplifier output and input. The bridge

is made

up of all of the resistors

and

capacitors.

The

operational

Chapter 16 _

679

Signal Generators

a Vo

Output voltage

Feedback volta ge

Figure 16-10

Wein bridge oscillator circuit uses an operational amplifier and a Wein

bridge that balances at a particular frequency.

amplifier

together

with

Ry, constitute

R3; and

resistors

a non-inverting

amplifier. The feedback network from the amplifier output to its noninverting input terminal is made up of components Cj, Ri, C2, and Ra. At the balance frequency of the Wein bridge, the feedback voltage is in

phase with the amplifier output. This (in-phase) voltage is amplified

to

reproduce the output. At all other frequencies, the bridge is off balance; that

is, the feedback and output voltages do not have the correct phase relationship to sustain oscillations. The Barkhausen requirement for zero loop phase shift is fulfilled in this circuit by the amplifier and feedback network both having zero phase shift at the oscillation frequency. Analysis of the bridge circuit shows that balance is obtained when two equations are fulfilled:

R3

a

and

20f

f

=

Rh

eG

G

1

(RyCyRoC2)

(16-11)

16-12)

If RiC, = R2C2, Eq. 16-12 yields ee

1

27R\Cy

(16-13)

680

Electronic Devices and Circuits

For simplicity, the components are often selected as R; = R2 and causing Eq. 16-11 to give

C, = C,,

Ry ='2R4

(16-14)

In this case, the amplifier closed-loop gain is Ac = 3. Sometimes it is preferable to have an amplifier voltage gain substantially

greater than 3; then the relationship between

the component

values js

determined by Egs 16-11 and 16-12. Design of a Wein bridge oscillator can be started by selecting a current level for each arm of the bridge. This should be much larger than the op-amp input bias current. Resistors R; and Ry can

then

be calculated

from the

estimated output voltage and the closed-loop gain. After that, the other component values can be determined from Eqs 16-11 to 16-14. An alternative design approach is to start by choosing a convenient value for the smallest capacitor in the circuit. The other component values are then calculated from the equations.

Example 16-4 Design the Wein bridge oscillator in Fig. 16-11 to produce a 100 kHz, +9 V output. Design the amplifier to have a closed-loop gain of 3.

Figure 16-11 Wein bridge oscillator circuit for Ex. 16-4.

Solution

Vec® Vy +1V) =+9V + 1V) =+10V

For Act = 3,

R, = Rpand C; = Cy

Also,

R3=2R,

Select

C; = 1000 pF (standard value)

Chapter 16

Signal Generators

681

C2 = C; = 1000 pF

q

]

1

1

2nfC,

2m X 100 kHz x 1000 pF

= 1.59 kQ (use 1.5 kO standard value)

Rz = Ry = 1.5k0 Select

Ry = Ro = 1.5kQ (standard value) Rg = 2Ry = 2 X1.5k0 = 3 kO (use 3.3 kO standard value)

The op-amp must have a minimum when 0, ~ £9 V and Ac, = 3. From Eq. 15-2,

full-power bandwidth

(fp) of 100 kHz

fp = Aci X f= 3 X 100 kHz

= 300 kHz From Eq. 15-3,

SR= 2m)

=27 X 100kHz x9 V

=5,.7V/ps

Practice Problems 16-4.1

Resistors R; and Ro in Fig. 16-11 are switched to (a) 15 kO and (b) 5.6 k®.

Calculate the new oscillating frequency in each case. 16-4.2 A Wein bridge oscillator using an op-amp is to produce a 15 kHz, +14 V output. Design the circuit with the amplifier having Ac, = 11.

16-5 OSCILLATOR AMPLITUDE STABILIZATION Output Amplitude For all of the oscillator circuits discussed, the output voltage amplitude

is

determined by the amplifier maximum output swing. The output waveform may also be distorted by the output saturation limitations. To minimize distortion and reduce the output voltage to an acceptable level, amplitude stabilization circuitry must be employed. Amplitude stabilization operates by ensuring that oscillation is not sustained if the output exceeds a predetermined level.

Diode Stabilization Circuit for a Phase Shift Oscillator The phase shift oscillator discussed in Section 16-1 must have a minimum

amplifier gain of 29 for the circuit to oscillate. Consider the oscillator circuit in Fig. 16-12a that has part of resistor R, bypassed by series-parallel connected

diodes.

When

the output amplitude is low, the diodes do not

682

Electronic Devices and Circuits

(a) Phase shift oscillator with

(b) Use of adjustable resistor

amplitude stabilization

for distortion control

Figure 16-12 The output amplitude of a phase shift oscillator can be limited by using diodes to modify the amplifier gain.

become forward biased, and so they have no effect on the circuit. At this time, the amplifier voltage gain is Ac. = R2 /R;. As always for a phase shift oscillator, Ac, is designed to exceed the critical value of 29. When the output amplitude becomes large enough to forward bias either D; and D3, or D3 and

Du, resistor Rg is short-circuited and the amplifier gain becomes R5/R,. This is designed to be too small to sustain oscillations. So, this circuit cannot oscillate with a high-amplitude output; however it can (and does) oscillate with a low-amplitude output. In the design of the amplitude stabilization circuit, the inverting amplifier is designed in the usual manner with one important difference. The current (I) used in calculating the resistor values must be large enough to forward bias the diodes into the near-linear region of their characteristics. This usually requires a minimum current around 1 mA. The resistor values are

calculated as follows:

Ro 1

V_/29

a

Ro = 29R,

(16-15)

(16-16)

Chapter 16 _

683

Signal Generators

The diodes should become forward biased just when the output voltage is at the desired maximum level. At this time, I; produces a voltage drop of 2V; across Rg. Therefore

Ry © =

and

Rs

=

Rp

—

(16-17)

1 Rg

The resulting component values should give (Ry + Rs)/R; slightly greater than 29, and Rs5/R; less than 29. Some distortion of the waveform can occur if (Rq + Rs)/Ri is much larger

than 29; however, attempts to make the gain close to 29 can cause the circuit to stop oscillating. Making a portion of Rs adjustable, as illustrated in Fig. 16-12b,

provides for gain adjustment to give the best possible output waveform.

Usually Rg should be approximately 40% of the calculated value of Rs, and R7

should be 80% of Rs. This gives a +20% adjustment of Rs. The diodes should be low-current switching devices. The diode reverse

breakdown maximum

voltage

should

exceed

the circuit supply

voltage,

and

the

reverse recovery time (ty(max)) Should be about one-tenth of the

time period of the oscillation frequency: rT trr(max) = 70

(16-18)

Example 16-5 Design the phase shift oscillator in Fig. 16-13 to produce a 5 kHz, +5 V output waveform.

Rp ——— Rg

Re

Rz

Figure 16-13 Amplitude-controlled phase shift oscillator circuit for

Ex. 16-5.

684

Electronic Devices and Circuits

Solution

Select

Eq. 16-15:

q

I, ~1 mA when Uoipeak) = 5 V

Vo/29.

5 V/29

==

AT

mA

= 170 0 (use 150 2) Eq. 16-16:

Ry = 29R; = 29 X 1500 744k0

Fq

. 16-17:

2V,

R,=—t = |

2x07V 1mA

= 1.4k0 (use 1.5 kO standard value) Rs = Ry — Ry = 4.4kQ— 1.5kO = 2.9k0 Re = 0.4Rs = 0.4 X 2.9kO = 1.16 0 (use 1 kO adjustable) R7 = 0.8Rs5 = 0.8 X 2.9 kO = 2.32 kO (use 2.7 kD standard value) R3® Ry = 4.4 kO (use 4.7 kO standard value) R=R,= 1500 From Eq. 16-1,

c=

,

2aRfFV6

=

:

a

2a X 1502 X 5kHz x V6

= 0.087 F (use 0.082 wF standard value)

Diode Stabilization Circuit for a Wein Bridge Oscillator Figures 16-14 and 16-15 show two output amplitude stabilization methods that can be used with a Wein bridge oscillator. These can also be applied to other oscillator circuits because they all operate by limiting the amplifier

voltage gain. The circuit in Fig. 16-14 uses diodes and operates in the same way as the amplitude control for the phase shift oscillator. Resistor Rg becomes shorted by the diodes when the output amplitude exceeds the design level, thus rendering the amplifier gain too low to sustain oscillations.

FET Stabilization Circuit for a Wein Bridge Oscillator The circuit in Fig. 16-15 is slightly more complex

than

the diode circuit:

however, like other circuits, it stabilizes the oscillator Output amplitude by controlling the amplifier gain. The channel resistance (rps) of the p-channel

Chapter 16 —

Signal Generators

685

Figure 16-14 Wein bridge oscillator with its output amplitude stabilized by a diode circuit that modifies the amplifier gain.

Figure 16-15

Wein bridge oscillator with the output amplitude stabilized by a FET

voltage-controlled resistance circuit.

FET (Q)) is in parallel with resistor Ry. Capacitor C3 ensures that Q; has no effect on the amplifier dc conditions. The amplifier voltage gain is

_ Rs + Rallros a

>

Rallrps

: 16-19)

The FET gate-source bias voltage is derived from the amplifier ac output. The output voltage is divided across resistors Rs and Ry and rectified by diode D,. Capacitor C4 smooths the rectified waveform to give the FET dc bias voltage (Vcs). The polarity shown on the circuit diagram reverse-biases

the gate-source of the p-channel device. When the output amplitude is low,

686

Electronic Devices and Circuits

Vgs is low and this keeps the FET drain-source resistance (rps) low. When the

output gets larger, Vos is increased, causing rps to increase. The increase

in rps reduces Ac,, thus preventing the circuit from oscillating with a high output voltage. It is seen that the FET is behaving as a voltage variable resistance (VVR).

Design of a FET Stabilization Circuit To design the FET amplitude stabilization circuit, knowledge of a possibly

suitable FET is required; in particular, the channel resistance at various gatesource voltages must be known. Suppose the circuit is to oscillate when rps = 6 kN. at Vcs = 1 V, and that the peak output is to be Voipk) = 6 V. Resistors Rs and Rg should be selected to give Vcs = 1 V when Vopk) = 6 V, allowing for Vy across the diode. Capacitor

C4 smooths the half-wave rectified waveform and discharges via Rg during the time interval between peaks of the output waveform. The capacitance of C4 is calculated to allow perhaps a 10% discharge during the time period of the oscillating frequency. The voltage-divider current (I5) should be a minimum of about 100 A for satisfactory diode operation. C3 is a coupling capacitor; its impedance at the oscillating frequency should be much smaller than the 7ps of the FET.

Resistors

R3 and Ry are

calculated from Eq. 16-19 to give the required amplifier voltage gain when rps =

6 kQ.

Example 16-6 Design the FET output amplitude stabilization circuit in Fig. 16-16 to limit the output amplitude of the Wein bridge oscillator in Ex. 16-4 to +6 V. Assume that the rg; = 600 9 at Ves = 1 V, and 800 2 at Ves = 3 V.

C,

1000 pF T.

Figure 16-16

Wein bridge oscillator circuit for Ex. 16-6.

Chapter 16

Signal Generators 687

Solution Select

R4* rpg at Veg = 1 V = 600 2 (use 560 2)

Ral|ros = 560 0||600.0 290 2, For Aci = 3,

R3 = 2 (R,||rps) = 2 X 290.0

= 580 2 (use 680 2) Select

I5 + 200 A when Vopeak) = 6 V R, = VSS

6

_

Is

1V

200 pA

= 5 kO (use 4.7 k) Voipeak) — (Vcs + Voi) Rs

=

Is

6V — (1V + 0.7V) 7

200 pA

= 21.5 kO (use 22 kD)

C4 discharge voltage: AVc = 0.1

Ve5

= 0.1

X1V=0.1V

C4 discharge time:

She

1

P= | = 100 KHz = 10us

Ic =

V Re

8 & Is = 200 pA _ 200 pA

= IcT

&,

4

AVe

X 10 ps

0.1V

= 0.02 wF (standard value) Xo3 = a

at the oscillating frequency

1

_

1

C3 = 27 f rps/10 ~ 2m X 100 kHz Xx 500 2/10

= 0.032 pF (use 0.03 LF) D, should be a low-current switching diode with a ty,

(17-26)

Chapter 17 _ Active Filters

737

R, =2QX at f,

(17-27)

2 _ Rit Ry 2Ry

(17-28)

Modified Figure 17-20 stage band-pass filter. addition of resistor R4 circuit to be designed

singleThe allows the for a

narrow-band A,/f response.

Design of the circuit is approached in the usual way by first selecting a suitable resistance value for R2 (considering the op-amp input bias current), and then calculating C. As always, if this produces a capacitance value that

might be affected by stray capacitance, then a suitable value for C is first selected, and R» is determined from C. Other determined from the appropriate equations.

components

are

then

Example 17-10 Calculate the centre frequency and bandwidth of the band-pass filter

in Fig. 17-20. Solution

Be

. 17-28:

liae

F rom Eq.17-27, 72,

Eq. 17-23:

Ri + Ry 60.4k0 + 1.21k0 Q 2R4 = 2X 121kO = 25,46 Q = V25.46 = 5.05 —

Q 5.05 = = fo = FoR, a X 0.012 pF X 121kQ = 1.1kHz pw ae = tt kHe “Q 5.05

738

Electronic Devices and Circuits

Practice Problems 17-6.1 A single-stage band-pass filter, as in Fig. 17-16, has the following component values: R; = Rz = 7.5 kQ, R3 = 6.8 kQ,, Ci = 8200 pF, and

C) = 750 pF. Determine the circuit bandwidth, centre frequency, and Q factor. 17-6.2 The band-pass circuit in Fig. 17-20 is to have a 1 kHz centre frequency and a 200 Hz bandwidth. Using a 741 op-amp, determine the required component values.

17-7

NOTCH

FILTERS

A notch filter is the inverse of a band-pass filter; its function is to block a band of signal frequencies. Other names are band-stop and band-reject filter. Figure 17-21a shows how a notch filter can be constructed

by the use of

low-pass and high-pass filters. The circuit inputs are connected in parallel, __|

Low-pass filter

| Summing

O

circuit

v;

ee

High-pass filter

:

:) vo

wie

ook (a) Low-pass and high-pass filters combined to produce a notch response

(dB)

Low-pass band

Stop band Ld

é 0

| |

High-pass band —

!

|

a

=

\

A, —i0

ny

—

i

| / |

f— f

(10 kHz)

,

f

hh

(100 kHz)

(b) Notch gain/frequency response Figure 17-21 A notch filter can be constructed by parallel-connecting the inputs of lowpass and high-pass filters, and summing the outputs.

Chapter 17

Active Filters

739

and the outputs are applied to a summing circuit (see Section 14-6). The summing circuit is necessary because the filters would overload each other if

the outputs were directly connected in parallel. Suppose that the low-pass circuit has a cutoff frequency of 10 kHz and that the cutoff frequency of the high-pass circuit is 100 kHz. The low-pass circuit will attenuate signal frequencies above 10 kHz, while the high-pass circuit will attenuate

frequencies below 100 kHz. The result is a stop band of 10 kHz to 100 kHz, as shown in Fig. 17-21b. Note that the frequency limits of the stop band are those frequencies at which the signal is —3 dB from its normal output level. The low-pass and high-pass filters can be first-order, second-order, or higher, for any desired roll-off rate of the notch frequency response. Another method of creating a notch filter is to sum the output of a bandpass filter with its own input signal, as shown in Fig. 17-22. In this case, the band-pass filter must have a voltage gain of 1, and it must invert the input

signal (or else an inverting amplifier must be included). During the pass band of the band-pass circuit, its output Upp equals —v;, and so the two inputs to the summing circuit cancel each other, giving zero output voltage. Above

and below the pass band of the band-pass circuit, vgp is very much smaller than v;. This causes the summing circuit output to equal v;, and the combination has a notch frequency response. Band-pass filter

v BP

|

Figure 17-22

tL

Anotch

filter can be

Summing circuit

constructed by Io a

summing the input and output of a band-pass filter. The notch filter

cutoff frequencies are the same as those of

|

LT

the band-pass filter.

The band-pass filter circuit in Fig. 17-18 (designed in Ex. 17-8) can be converted into a single-stage notch filter by the addition of resistor Ry, as shown in Fig. 17-23. R4 should be chosen to be equal to Rj and R2, and resistor R3 should also be made precisely equal to Rz (instead of approximately

equal). The circuit now functions as a difference amplifier (see Section 14-7) with only one input (0). For signal frequencies between f, and fs, the input

voltage (applied to both R; and Ry) produces positive-going and negativegoing equal outputs that cancel each other. For signals above and below the cutoff frequencies, input voltages applied via R; are attenuated, and those

applied via Ry are passed to the output. Thus, the circuit functions as a notch filter.

740

Electronic Devices and Circuits

Cy YI T

1000 P pF

Ry 5.36 kO

R

+Vec

WV

,

°

+=

5.36 kQ

Cy

R

0.1 pF

VT

+

Figure

4

7

AM 5.36 kO,

a

ie R; 5.36 kQ-

% EE ah =

LL

17-23

A single-

stage notch filter can be constructed by the addition of a resistor (R4) to a single-stage band-pass filter.

Practice Problem 17-7.1

A single-stage notch filter, as in Fig. 17-23, is to be designed to havea stop band

ranging from

200 Hz

to 20

kHz.

Determine

suitable

component values for the circuit.

17-8 ALL-PASS FILTERS Phase-Lag Circuit An all-pass filter is a circuit that will pass all frequencies without attenuation but with phase shifts that vary with the signal frequency. A phase lag can also

be termed a phase delay, so an all-pass phase-lag circuit is also known as a delay filter. Figure 17-24a shows an all-pass circuit, and Fig. 17-24b shows its phase/frequency response graph. The circuit is similar to a difference amplifier (see Section 14-7) except that capacitor C; replaces a resistor. Also,

the two input terminals are connected together so that v; is applied to both. The procedure used in the analysis of the difference amplifier can be used to investigate the all-pass filter. With the inputs separated, terminal 2 grounded, and _v; applied to terminal 1: Vo1

With

Ry = Rz

_=

_&

Ri

XK 0;

V1 = Uj

With terminal 1 grounded, and 9; applied to terminal 2, Ry + Ry

Yon = a With R; = Ro,

Vo2 = 2Uc1

1

* UI

Chapter 17__

Active Filters

7441

Figure 17-24 An all-pass phase-lag circuit passes the input signals with no attenuation but with a phase lag

dependent on the signal

frequency.

(b) Phase/ frequency response

%c1 =

and

anhlchgives

0j(-jXe1)

R3 — jXc1_ Vo = Voi — Vo2

_ =

;

Uj

1 + j(R3/Xc1)

Yo = [2 tan (Ry/ Xe)

(17-29)

It is seen that the output voltage amplitude is always equal to the input,

regardless of the signal frequency. Also, the output lags behind the input by an angle of

o = —2 tan* (R3/Xc1) When Xc; = R3,

ob = —90°

At high signal frequencies, when Xc1 > Rs,

x0?

(17-30)

742

Electronic Devices and Circuits

The above quantities are illustrated by the #/f response graph in Fig. 17-24b. An all-pass circuit is designed by first choosing suitable values for resistors R, and R» as for an inverting amplifier with a gain of 1. This requires R; = Ro. Resistor R3 is then selected to be approximately equal to Ry | Ro, and C

is calculated to give Xci = R3 at the desired 90° frequency. If

an uncompensated op-amp is used, it should inverting amplifier with a gain of 1.

be

compensated

as an

Example 17-11 Using a 741 op-amp, design an all-pass filter to have a phase lag adjustable from 80° to 100°. The signal amplitude is 1 V and its frequency is 5 kHz. Solution

See Fig. 17-25, ly > Ipmax) Select

i, =50 pA

= 7 ~ 5 3 = 20 kO (use 20 kN. + 1% standard value)

Ro = Ry = 20kO

R3*R,|| Ro = 10kO For a 90° phase shift,

Xci = Rs or

Cy

:

~ QnfR3

A

2X 7 X 5kHz X 10kO

= 3183 pF (use 3300 pF standard value)

-

” kQ

Ro¥

6.8kO

=al a

Figure 17-25 All-pass phase-lag circuit designed in Ex. 17-11.

Chapter 17

Active Filters

743

For an 80° phase shift,

Eq. 17-30:

d@ = —2 arctan (R3/Xc1)

.

Ry = 2/2) 2afC;

tang80"/2) 2X + X 5kHz X 3300 pF

~ 8.1 kO For a 100° phase shift, Ry = tan(p/2) _

QnfC;

tan(1 00°/2)

|

2X a X 5kHz X 3300 pF

= 11.5kO0 For R3, use a 6.8 k) fixed value +10% resistor in series with a 5 kQ variable

resistor to give a total resistance adjustable from 6.8 kO to 11.8 k.

Phase-Lead Circuit The phase-lead circuit in Fig. 17-26 is similar to the phase-lag circuit, except that R3 and C, are interchanged. This has the effect of causing the output to Ry

Ry Oo—¢ \] Vt

Uj

Up

Gi

R3

a 180°

[

-

=

t

150°

120°

$ 90°}

—_ _ ;—_ _ _ {}_ _ Peng

60°

—_f—$—————_

a

fe) LL

0°

Figure 17-26

An all-pass

phase-lead circuit

ai

Passes the input signals {

—_—

Xcy = Ry (b) Phase/ frequency response

with no attenuation but

with a phase lead dependent on the signal frequency.

744

Electronic Devices and Circuits

lead the input by a phase angle dependent on the relationship between Xc;

and R3. The design procedure for this circuit is similar to that for the phase-lag circuit.

Practice Problem 17-8.1 An all-pass filter using a BIFET op-amp is to have a phase lead adjustable from 75° to 90°. The input signal has 1 V amplitude and a frequency of 1 kHz. Determine suitable component values for the circuit.

17-9 STATE-VARIABLE FILTERS The circuit shown in Fig. 17-27, known as a state-variable filter, consists of amplifier A; and two integrators, Az and A3. Another arrangement of the

Figure 17-27 State-variable filter circuit consisting of amplifier stage A; and integrator stages Az and As. The circuit functions as a band-pass filter when the output is taken from Ap.

circuit is named a biquad filter. Both are termed universal filters because they

can function as low-pass, high-pass, band-pass, all-pass, or notch filters. The circuit in Fig. 17-27 is intended to operate as a band-pass filter with the output taken from Ap. Amplifier A, together with resistors Ry, Rz, R3, and R,, functions as a difference amplifier. (In a slightly different circuit configuration, Aj is

connected as a summing amplifier.) A. and A3 and their associated components are integrators, which introduce 90° phase shifts. The input to A, is applied via R, to its non-inverting terminal, but A, output is inverted by Az and fed back to Aj via resistor Ro. Consequently, A; and A» together with R, and R; constitute an inverting amplifier, which is effective only for signal

frequencies close to the filter centre frequency.

Chapter 17

Active Filters

745

At low frequencies, capacitors C; and C, have high impedances compared to the resistances of Rs and Rg, and so the stage gains of A2 and A3 are very large. In this case, the negative feedback from A3 to R, tends to reduce the A and A» outputs to nearly zero. At high-signal frequencies, the impedances of C, and C2 are small compared to Rs and Rg, so that the Ay and A3 gains are very small (an attenuation). In this condition, the output from Az is again quite small. At the centre frequency, or critical frequency (fo), for the circuit, Xci = Rs

and Xc2 = Re. The Az and A; stages each have a voltage gain of 1 at f,, as well as a 90° phase shift. So, the voltage fed from A3 to Ry is equal to, and in antiphase with, the output of A;. Thus, A; has a very large gain from its non-

inverting input terminal to its output, Az has a gain of 1, and resistors Rz and R; become effective as a feedback network. The voltage gain from 0; to v,2 at the centre of the pass band is then R2/R:.

Analysis of the equation for Q:

state-variable

filter circuit produces

——

which gives

Because

a very

R, + Ro OR,

17-3 (17-31)

Ry = R,(2Q — 1)

the circuit is designed

simple

(17-32)

so that at the centre frequency

of the

bandwidth (fo), Xc1 = Xc2 = Rs = Ro,

1 fo = 27 CRs Designing

this

circuit

begins

with

the

(17-33)

selection

of

a

convenient

capacitance value for C; and Cj. Then Rs and Rg are calculated from Eq. 17-33. Resistors R3 and R4 should give an A; stage gain of 1. So R3 equals Ry, and these can also be made equal to Rs and R¢. Furthermore, R; can be made equal to the common value of the other resistors, leaving R2 to be determined from Eq. 17-32. Only Rs and Re need to have precise resistance values in relation to C; and C> (to set fo). The design procedure is seen to consist of only three steps: (1) select a

convenient capacitance value for C; and C;, (2) use Eq. 17-33 to determine the common value for all resistors except Rz, (3) calculate R2 from Eq. 17-32.

Example 17-12 Design a state-variable band-pass filter to have f, = 10.3 kHz and f, =10.9 kHz.

746

Electronic Devices and Circuits

Solution

Select

C, = C) = 1000 pF

Eq. 17-24:

fo= (Af) = J10.3 kHz x 10.9 kHz = 10.6 kHz

Eq. 17-33:

Rs

1

~ DafyC,

1

2X m7 X 10.6kHz X 1000 pF

= 15.01 kO (use 15 kO +1% standard value)

Ry = Rg = Rg = Rs = Re = 15 kO.

From Eqs 17-22 and 17-23, Q=

fo

10.6 kHz

fo-fi

10.9kHz — 10.3 kHz

= 17.7 Eq. 17-32:

= Ry = R,(2Q — 1) = 15 kQ[(2 x 17.7) —1] = 515 kO, (use 301 kO and 215 kO +1% in series)

Practice Problem 17-9.1

A state-variable band-pass filter (as in Fig. 17-27) has the following components: Ry = R3 = Rg = Rs = Re = 12 kO, Ro = 180 kQO, and

C; = Cp = 1500 pF. Determine the centre frequency and bandwidth for the circuit.

17-10

IC SWITCHED-CAPACITOR

FILTERS

Switched-Capacitor Resistor Simulation A major problem with constructing filters in integrated circuit form is that size restrictions allow only very small capacitance values to be fabricated: a

maximum of approximately 100 pF. Small-value capacitances require relatively large-value resistors for the critical frequencies in filters. For example, a critical frequency of 1 kHz with a 100 pF capacitance requires a 1.59 MO, resistor. Here again there is a problem

because

such

resistance

values require more space than is available on an IC chip. The difficulties are overcome by the use of small-value capacitors and MOSFET

switches, which

are easily fabricated in IC form. The combination of capacitor and switch can

be employed to simulate a resistor. Figure 17-28a shows an integrator stage as used in a state-variable filter circuit. In Fig.17-28b, the integrator resistor (R2) is replaced with a capacitor (C1) and a switch (S;) that alternately connects C, to the input voltage (vj) at terminal 1 and to the junction of C; and the op-amp inverting input at

terminal 2. When S, is set to terminal 1, capacitor Cy charges to v;. When 5; is

Chapter 17

Active Filters

747

eo C,

el.

= (a) Integrator circuit

—, >

5 1 \

eh

Tt

2

=

[|

=

Li

(c) Clock switching waveform

(b) Integrator with a switched

capacitor substituted for R A resistor can be simulated by a switched capacitor, which passes charge Figure 17-28 at the same rate as the resistor. Switched capacitors are more easily fabricated than resistors in integrated circuits.

switched from terminal 1 to terminal 2, C; passes its charge to C2. Now assume that S; is controlled by the clock waveform shown in Fig. 17-28c. The charge passed during one cycle of the clock is

or

Q

=

Cy;

1 Tx

=

C10;

.

a

5 which gives

i=

Cy0;

Tek

Referring to Fig. 17-28a again, the current passed to C) is

ee i= Ro For equal input current levels via Ry and via S; and Cy, Tk

Ro = C,

Oo Tr

R

qe

|

Fea

= (17-34)

It is seen that resistance R» is simulated by C; and switch S;. The resistance

value depends upon the capacitance of C; and upon the switching (clock) frequency (fcx). Increasing fcx reduces the simulated resistance; reducing fex

748

Electronic Devices and Circuits

increases the resistance. A clock frequency acitance simulate a resistance value of

1

of 50 kHz

and

a 100 pF cap-

1

Ra= faeC1

50 kHz X 100 pF

= 200kO Recall from Section 17-9 that the critical frequency of the filter occurs when the integrator resistors equal the capacitive impedance:

1

fo = QarCoR> Substituting for Ro, Fa

fo= OmCs

(17-35)

Equation 17-35 shows that the critical frequency now depends upon the ratio of capacitors C, and C2 as well as on the clock frequency. Although integrated circuit capacitors cannot be fabricated with very accurate absolute values, they can be created with accurate capacitance ratios (usually + 0.1%), and

this is good for f, accuracy. Also, because f, is directly proportional to fy, the

critical frequency can be altered by variation of f-x.

IC Filter Circuits Integrated circuit switched-capacitor filters generally use the state-variable (universal)

filter

circuit

configuration

(see

Section

17-9),

because

the

connections can easily be arranged to give all five filter functions (low-pass, high-pass,

band-pass,

all-pass, and

capacitive component values are not the clock frequency determines the the filter critical frequency is set connections are usually provided:

notch).

internal

IC

resistive and

listed on a data sheet. Instead, because (switched-capacitor) resistance values, by the clock frequency. Two clock one for f. = f./50, and the other for

fo = fex/100. So, for fo = 1 kHz, for example,

100 kHz might be used. The critical frequency for a given highest signal frequency. An these are readily available in

The

a clock of either 50 kHz or

clock frequency must be much higher than the filter design, and it should be at least twice the external clock source is normally required, and IC form.

The MF10 is an integrated circuit containing two switched-capacitor statevariable filter sections which can be operated independently as two secondorder filters, or cascaded to make one fourth-order filter. One-half of the MF10

block diagram is shown in Fig. 17-29. The

amplifier, a summing

circuit, and

two

circuit is made

integrators.

An

external

up of an

clock is

Active Filters

Chapter 17

N/AP/HP, = Sla

3

INV, (-——_—_—_

01

2

Integrator

Summer

4

LPs

BP 4

5

749

Integrator

15 AGND (}

CLK,

| LEVEL [NON OVERL

apigemeee T |e

CLOCK

SHIFT |

a 12

50/100/CL (+

CONTROL

LIA Sa,

9 Lea tce——— Figure 17-29

Block diagram of one-half of an MF10 switched-capacitor IC filter.

(Reprinted with permission of National Semiconductor Corporation. Not authorized for

use as Critical components in a life support system.)

required, and with only two to four external resistors, any filter function can be performed. The connecting pins shown are identified as follows:

LSh 50/100/CL

Shifts the dc level of the clock input Sets the ratio of fex/fo

CLKa

Clock input

AGND

Analog ground terminal

INVa

N/AP/HP,

Op-amp inverting input terminal

Notch, all-pass, and high-pass output, and summer non-inverting input

Sla BPs LP,

Summer inverting input Band-pass output Low-pass output

SAB

Sets the internal switch to an inverting input of the summer stage

The f-./fo ratio is 50/1 when the 50/100/CL pin is connected to the positive supply, and 100/1 when it is connected to ground. When Sag is connected to the positive supply, the switch is set to the right to connect the second integrator output (LP, output) to the summing stage. With Sap connected to

the negative supply, the summing stage inverting input is grounded. Figure 17-30 shows one-half of an MF10 connected in Mode 1 to function as a notch, band-pass, or low-pass filter. The design equations are also

shown. Six possible modes of operation are listed on the manufacturer’s

750

Electronic Devices and Circuits BP, L] 2

LPs 1

Oj

Sap

6

15

&

ke

=O

=

7

Rg

+

v

fc

Mode 1

fe =

ts ™~ 1400 or “50

B®a

Q=

Footch = fo

Hop

__R = Ry

RB Hopp

Ry asfy —~ Hon = "R,

=

R,

Oand as f, —~

fox >

Figure 17-30 One-half of an MF10 connected in Mode 7 to function as a notch, bandpass, or low-pass filter. (Reprinted with permission of National Semiconductor Corporation. Not authorized for use as critical components in a life support system.)

data sheet, some subdivided into A and B. The Ho equations refer to the

voltage gains at the critical frequency (f,) from the input to each of the outputs. For example, Hopp refers to the gain from v; to the band-pass output terminal (BP,).

Example 17-13 Determine the required resistance values to operate one-half of an MF10asa

band-pass filter with f; = 10.3 kHz, fp = 10.9 kHz, and a voltage gain of 34. (Note that this is the same frequency limit as for Ex. 17-12.) Solution

Eq. 17-24:

fo = (fifa) V = V0.3 kHz x 10.9 kHz) = 10.6 kHz

Equations 17-22 and 17-23:

o-—__ fo- fi

10.6 kHz 10.9kHz — 10.3 kHz

=177 Select

R3* 120 kQ (use 121 kN. +1% standard value)

Chapter 17

Active Filters

754

From the MF10 design equations, —2=—R3

=

Q

121 kO

177

= 6.83 kO, (use 6.81 kQ +1% standard value) and

Rk,

R;

=

121k

= 3.6 kO (use 3.57 kOQ +1% standard value)

fx = 50 X fy = 50 X 10.6 kHz = 530 kHz Practice Problem 17-10.1

A notch filter using one-half of an MF10 is to have fi = 1.7 kHz, fo = 2.35 kHz, and a voltage gain of 10. Determine suitable component

values and select an appropriate clock frequency.

17-11

FILTER TESTING AND TROUBLESHOOTING

The common errors listed in Section 5-6 should be referred to once again. They apply to filter circuits constructed on a laboratory breadboard, just as they do to all circuits. The discussion in Section 14-11 concerning op-amp circuit testing is applicable to active filters, and the op-amp circuit stability treatment in Section 15-6 is very important. Once

it is determined

that the circuit is not oscillating and that the dc

voltage levels are acceptable, testing for A,/f and $/f responses can begin. The amplifier ac testing procedure in Section 12-11 can be followed. The first

signal frequency should be well within the filter-pass band; then fairly large frequency steps can be made while the response is flat. The frequency should be changed in small steps around the cutoff frequencies, to obtain sufficient readings for accurately plotting the graphs. Because of component tolerances, filter cutoff frequencies are unlikely to be precisely as calculated.

If a measured

cutoff frequency is far from the expected frequency, the

component values should be rechecked, especially the color-coded resistor values. A common mistake is the selection of a resistor in error by a factor of 10. When filter falloff rates are less than expected, one possibility is that the feedback portion of the circuit is not functioning correctly. For example, suppose

the

two-pole

filter in Fig. 17-9 behaves

like a single-pole

filter

(20 dB/decade falloff rate instead of 40 db/ decade). In this case it is most likely that the feedback capacitor (C2) is not correctly connected, or perhaps that the

capacitance value is much smaller than required.

752

Electronic Devices and Circuits

Higher-order

filters

consisting

of

several

sections

may

need

to be

separated into individual sections for testing if the overall circuit does not

perform as expected. The same remarks apply to band-pass and notch filters that contain low-pass and high-pass sections. Review

Questions

Section 17-1 17-1

Sketch ideal and practical gain/ frequency response graphs for low-pass, highpass, band-pass, and notch filters. Explain the function of each type of filter,

17-2 17-3

Sketch the circuit of a basic RC low-pass filter and explain its operation. Sketch typical gain/frequency and phase/frequency response graphs for a low-pass filter. Identify the cutoff frequency, and

17-4

explain

the shape of the

graphs. Define cutoff frequency, bandwidth, pass band, stop band, attenuation band, transition band, insertion loss, and transfer function.

Section 17-2 17-5

Sketch the circuit of a first-order active low-pass filter, and explain how the

circuit operates. Discuss the function of the operational amplifier. 17-6

Sketch the circuit of a first-order active high-pass filter, and explain how the

circuit operates. 17-7

Sketch typical gain/frequency and phase/frequency

response graphs for a

first-order active high-pass filter, and explain the shape of the graphs. Section 17-3 17-8

Define single-pole, two-pole,

17-9

formances of each. Identify the major types of filter circuit design, and discuss the differences in their gain/ frequency and phase/frequency response graphs.

17-10 Sketch

and

three-pole

the circuit of a second-order

low-pass

filters, and

active

describe

filter, and

the per-

explain

its

operation.

17-11 Sketch typical A,/f and ¢/f response graphs for a second-order low-pass active filter. Discuss the shape of the graphs. Section 17-4 17-12 Sketch the circuit of a second-order high-pass active filter, and explain its operation. | 17-13 Sketch typical A,/f and $/f response graphs for a second-order high-pass

active filter. Discuss the shape of the graphs. Section 17-5 17-14 Sketch

a circuit

for

a third-order

low-pass

active

filter,

and

explain

its

explain

its

operation. Discuss the required cutoff frequency for each stage. 17-15 Sketch a circuit for a third-order high-pass active filter, and operation. Discuss the required cutoff frequency for each stage.

Chapter 17 _ Active Filters

753

17-16 Sketch typical A./f and /f response graphs for third-order low-pass and high-pass active filters. Discuss the shape of the graphs.

Section 17-6 17-17 Show how a band-pass filter can be constructed by the use of a low-pass and a

high-pass filter. Sketch the expected A,/f response graph and explain the filter operation. 17-18 Sketch the circuit of a single-stage band-pass active filter. Explain the circuit operation.

17-19 Sketch typical A,/f response graphs for wide-band and narrow-band bandpass filters, and discuss the differences between them. Write equations for bandwidth, Q factor, and centre frequency.

17-20 Show how the circuit of a single-stage wide-band band-pass filter can be modified for narrow-band operation. Briefly explain.

Section 17-7 17-21 Sketch a block diagram to show how a notch filter can be constructed using a low-pass and a high-pass filter. Sketch the expected A,/f response graph and explain the filter operation. 17-22 Explain by the use of a block diagram how a band-pass filter and a summing circuit can be used as a notch filter. Sketch the expected A,/f response graph.

17-23 The band-pass circuit in Fig. 17-16 can be modified to convert it to a notch filter. Show the modification and explain how the notch response is obtained.

Section 17-8 17-24 Draw a circuit diagram for an all-pass phase-lag filter. Sketch the typical phase/ frequency response and explain the circuit operation. 17-25 Write the input/output equation for an all-pass phase-lag circuit. Explain how the phase lag may be made adjustable. 17-26 Draw a

circuit diagram for an all-pass phase-lead filter. Sketch the typical

phase /frequency response and explain the circuit operation.

Section 17-9 17-27 Draw the circuit of a state-variable filter. Briefly explain the circuit operation and write equations for Q and fo.

Section 17-10 17-28 Show how a

switched capacitor can be used to simulate a resistor, and discuss

the advantages of this process in integrated circuit applications. 17-29 Explain how the critical frequency of an integrator with a switched-capacitor

simulated resistor can be controlled by a clock. 17-30 Sketch the basic block diagram for one-half of an MF10 integrated circuit filter. Identify the components and briefly explain the function of each. Show how

external resistors may be connected to have the IC function as a band-pass filter.

754

Electronic Devices and Circuits

Section 17-11 17-31 Prepare a point-form list of items to be checked before testing a laboratoryconstructed filter circuit. 17-32 Prepare a point-form list of the procedure for testing a filter circuit to

determine its A,/fand ¢/f responses.

Problems Section 17-1 17-1 Calculate the cutoff frequency for a basic RC low-pass filter with R; = 18 kQ) and C; = 1000 pF. Determine the circuit bandwidth,

and

estimate

the signal

attenuation at f ~ 35.4 kHz. 17-2

A basic

low-pass

filter with

C; = 0.015

pF

is

to

attenuate

20

kHz

signal

frequencies by approximately 23 dB. Determine the required cutoff frequency, and calculate a suitable resistance value for Rj. 17-3

Calculate the new cutoff frequency and insertion loss for the filter in Problem

17-4

Abasic low-pass filter with C; = 0.01 uF has R; consisting of a 3.3 kQ resistor

17-2 when a 60 kQ load resistance is connected to the output. in series with a 1 kQ variable resistor. Calculate the maximum

and minimum

cutoff frequency. 17-5

Calculate the insertion loss for the filter in Problem 17-1 when a 100 kQ load resistance is connected to the output. Determine the effect of the load on the

circuit cutoff frequency. Section 17-2 17-6 A first-order active low-pass filter is to have a cutoff frequency of 3 kHz. First, design

17-7

the circuit with

a bipolar

op-amp,

then

redesign

op-amp. Modify each of the circuits designed for Problem

it with

17-6 to make

a BIFET

the cutoff

frequency adjustable from 2 kHz to 4 kHz. 17-8

17-9 A

Using a BIFET op-amp, design a first-order active high-pass filter to have a 15 kHz cutoff frequency. Determine the circuit bandwidth if the op-amp has a

1.2 MHz unity gain frequency. first-order active high-pass filter has Rj = 56 kQ and C; = 600 pF. If the circuit uses a 741 op-amp, determine the cutoff frequency and the highest signal frequency that can be passed.

Section 17-3 17-10 Using a 741 op-amp, design a second-order active low-pass

filter to have a

5 kHz cutoff frequency with a Butterworth response. 17-11 Redesign the filter in Problem 17-10 to use a 108 op-amp.

17-12 A second-order active low-pass Butterworth filter has the following component values: Ri = Rz = 56k, Rs = 120 kQ,, C; = 600 pE, and C2 = 1200 pk Calculate the circuit cutoff frequency.

Chapter 17 _

Active Filters

755

17-13 A second-order active low-pass filter is to attenuate 7 kHz signals by 15 dB. Design the circuit to use a BIFET op-amp and to have a Butterworth response.

Section 17-4 17-14 Design

cutoff

a second-order

frequency.

Use

active high-pass

a 353

op-amp

Butterworth

and

a 7 kHz

filter to have

determine

the

highest

has

the

signal

frequency that can be passed. 17-15 A

second-order

active

high-pass

Butterworth

filter

following

component values: R; = 28 kOQ, Ro = 56 kN, and C; = C2 = 1000 pF. Calculate the circuit cutoff frequency. 17-16 A second-order active high-pass filter is to attenuate signal frequencies below 1.2 kHz by a minimum of 15 dB. Design the circuit to use a 741 op-amp and to have a Butterworth response. Calculate the circuit bandwidth.

17-17 Redesign the filter in Problem 17-16 to use a BIFET op-amp.

Section 17-5 17-18 A third-order active low-pass filter is to attenuate all signals above 9 kHz by a minimum

of 21 dB. Design the circuit to use BIFET op-amps and to have a

Butterworth response. 17-19 Using 741 op-amps, design a third-order Butterworth active low-pass filter to have an 18 kHz cutoff frequency. 17-20 A third-order Butterworth active high-pass filter is to pass all signal frequencies above 8 kHz. Design the circuit to use 108 op-amps.

17-21 Determine the bandwidth of the circuit designed for Problem 17-20. Estimate the attenuation of a 2 kHz signal.

Section 17-6 17-22 A bandpass filter using low-pass and high-pass circuits (as in Fig. 17-15) is to have a bandwidth extending from 400 Hz to 30 kHz. Using 741 op-amps,

design suitable second-order stages. 17-23 Design a single-stage band-pass filter to have cutoff frequencies of 1 kHz and

50 kHz and a voltage gain of 1. 17-24 A single-stage band-pass filter (as in Fig. 17-16) has the following component values: R; = R2 = R3 = 3.9 kO, Cy = 0.12 pF, and C2 = 600 pE. Calculate the

circuit cutoff frequencies. 17-25 A single-stage narrow-band band-pass filter (as in Fig. 17-20) is to be designed

to use an op-amp with 1A input bias current. The centre frequency is to be 3.3 kHz with a bandwidth of approximately 500 kHz. Determine suitable component values. 17-26 Redesign the filter in Problem 17-25 to use a BIFET op-amp. Section 17-7 17-27 The notch filter in Fig. 17-21 is to have a stop band from 10 kHz to 100 kHz. The signal amplitude is 1 V. Design the complete circuit to use first-order high-pass

and low-pass filters. 17-28 The notch filter in Fig. 17-22 is to be used to attenuate an unwanted 120 Hz input. Design the circuit to have a bandwidth of 20 Hz.

756

Electronic Devices and Circuits

17-29 Design a single-stage notch filter (as in Fig. 17-23) to have f; = 1.3 kHz and fz = 54 kHz.

Section 17-8 17-30 An all-pass filter circuit is to have a phase lag adjustable from 70° to 100°. The 3.3 kHz input voltage has a3 V amplitude. Design the circuit using a BIFET op-

amp. 17-31 An all-pass phase-lead circuit with a 2.V, 1.5 kHz input is to have a phase lead adjustable from 90° to 130°. Design the circuit to use a bipolar op-amp.

Section 17-9 17-32 A state-variable band-pass filter (as in Fig. 17-27) has the following component

values: Ry = 12 kQ, Ry = 560 kQ, R3 = Rq = 27 kO, Rs = Ro = 33 kQ, and C, = C2 = 1200 pF. Calculate the width of the pass-band. 17-33 A band-pass filter is to pass 2 kHz to 2.5 kHz signal frequencies. Design a suitable state-variable circuit. 17-34 A state-variable band-pass filter is to have f. = 3.3 kHz and BW ~ 200 Hz. Design the circuit using a BIFET op-amp.

Section 17-10 17-35

A band-pass filter with a voltage gain of 20, f, = 3 kHz, and/; = 4 kHz is to be

constructed using an MF10. Determine suitable resistance values and clock frequency. 17-36 Determine suitable resistance values and clock frequency for an MF10 notch

filter which is to have a voltage gain of 15, f, = 2 kHz and fy = 2.9 kHz.

Practice Problem Answers 17-1.1 17-1.2

19.65 kHz, 23 dB 1.1 dB, 22.29 kHz

17-2.1

1000 pF, 10.5 kQ

17-2.2

752 kHz

17-3.1 17-3.2

1000 pF, 2000 pF, 75 kQ, 75 kQ, 150 kQ, 1.5 kHz 1000 pF, 2000 pF, 18.7 kO, 18.7 kO, 39 kQ, 6.02 kHz

17-4.1

3000 pF, 3000 pF, 60.4 kQ, 121 kQ, 120 kQ, 621 Hz

17-5.1 17-5.2

1000 pF, 10.2 kQ, 10 kO; 1000 pF, 2000 pF, 9.09 kQ, 9.09 kQ, 18 kO 1000 pF, 37.4kQ, 39 kQ; 1000 pF, 1000 pF, 21 k®, 42.2 kQ2, 39 kA

17-6.1

25.7 kHz, 8.56 kHz, 0.33

17-6.2

60.4k0, 121 kO, 120 kO, 1.21 kO, 0.012 wF, 0.012 wF

17-4.2

1000 pE, 1000 pF, (3.01 kO. + 1.5 kQ), 9.09 kQ, 10 kO

17-7.1

9100 pF, 1000 pF, (4 x 26.1 kQ)

17-8.1 17-9.1 17-10.1

243 kO, 243 kO, (120 kO fixed +50 kO variable), 1000 pF 8.84 kHz, 1.1 kHz 3,92 kO, 40.2 kO, 121 kQ, 100 kHz

CHAPTER

18

Linear and Switching Voltage Regulators Objectives You will be able to:

i Sketch transistor series

regulator circuits and explain their operation. Show how regulator circuits may

be improved by the use of error amplifiers, additional series-pass transistors, preregulation, etc., and how the output voltage may be adjusted. Design transistor series regulator circuits to fulfill a given specification. Analyze transistor series

Sketch and explain the basic circuit of a 723 IC voltage regulator, and design circuits

using 723 ICs.

Sketch IC regulator block diagrams and determine external component values for various applications.

Sketch the block diagram and waveforms for a switching regulator and explain its operation. 10 Sketch circuits and waveforms

effect, load effect, line

for step-down, step-up, and inverting converters, and

regulation, load regulation, and

explain their operation.

regulators to determine source

ripple reduction.

Sketch operational amplifier series regulator circuits and explain their operation. Design op-amp series regulator

11 Design LC filter circuits for various switching converters. 2 Show how an IC controller circuit is used with switching

converters, and calculate values

circuits to fulfill a given

for the externally connected

specification.

components.

INTRODUCTION Almost all electronic circuits require a direct voltage supply. This is usually

derived from the standard industrial or domestic ac supply by transformation, rectification, and filtering. The resultant raw dc is not stable

758

Electronic Devices and Circuits

enough for most purposes, and it usually contains an unacceptably large ac ripple waveform. Voltage regulator circuits are employed to render the

voltage more constant and to attenuate the ripple. Unregulated power supplies and Zener diode regulators are discussed in

Chapter 3. Zener diode regulators are normally used only where the load current does not exceed 25 mA. A transistor operating as an emitter follower circuit may be connected to a Zener diode regulator to supply larger load currents. The regulator circuit performance is tremendously improved when an error amplifier is included, to detect and amplify the difference between the output and the voltage reference source, and to provide feedback to correct the difference. A variety of voltage regulator circuits are available in integrated circuit form.

18-1

TRANSISTOR SERIES REGULATOR

Basic Circuit When a low-power Zener diode is used in the simple regulator circuit described in Section 3-7, the load current is limited by the maximum diode current. A high-power Zener used in such a circuit can supply higher levels of load current, but much power is wasted when the load is light. The emitter

follower regulator shown in Fig. 18-1 is an improvement on the simple regulator circuit because it draws a large current from the supply only when required by the load. In Fig. 18-1a, the circuit is drawn in the form of the common collector amplifier (emitter follower) discussed in Section 6-6. In

Fig. 18-1b, the circuit is shown in the form usually referred to as a series regulator. Transistor Q is termed a series-pass transistor. The output voltage V, from the series regulator in Fig. 18-1 is Vz — Veg,

and the maximum load current IL(max) can be the maximum emitter current

>V,

“O

(a) Emitter follower voltage regulator

Figure 18-1

~)

(b) Series voltage regulator circuit

To supply a large output current from a Zener diode voltage regulator, a transistor

(Q,) is connected as an emitter follower. This converts the circuit into a series voltage regulator.

Chapter 18

Linear and Switching Voltage Regulators

759

that Q; is capable of passing. For a 2N3055 transistor (specification in data sheet A-8 in Appendix A), I, could approach 15 A. When I, is zero, the current drawn from the supply is approximately Iz + Ic(min), where Ic(min) is the minimum collector current to keep Q; operational. The Zener diode

circuit (R; and D;) has to supply only the base current of the transistor. The series voltage regulator is, therefore, much more efficient than a simple Zener

diode regulator.

Regulator with Error Amplifier A series regulator using an additional transistor as an error amplifier is shown in Fig. 18-2. The error amplifier improves the line and load regulation of the circuit (see Section 3-6). The amplifier also makes it possible to have an output voltage greater than the Zener diode voltage. Resistor Rzand diode D, are the Zener diode reference source. Transistor Q» and its associated components

constitute the error amplifier, which controls the series-pass transistor Q). The output voltage is divided by resistors R3and Ry and is compared to the Zener voltage level (Vz). C; is a large-value capacitor, usually 50 wF to 100 wF, which is connected at the output to suppress any tendency of the regulator to

oscillate. Tey

(+0

Q:

—

°

Oo +)

rvs,

~)

L=-©

Figure 18-2

Series voltage regulator circuit with an error

amplifier. The error amplifier improves the regulator line and load regulation and gives an output voltage greater

than the Zener diode voltage.

When the circuit output voltage changes, the change is amplified by transistor Q) and fed back to the base of Q; to correct the output voltage level. Suppose that the circuit is designed for a V, of 12 V and that the supply

voltage is Vs = 18 V. In this case a suitable Zener diode voltage might be Vz=6 V. For this Vz level, the base voltage of Q, must be Va2 = Vz + Vopr = 6.7 V. So resistors R3 and Ryare selected to give Vp) = 6.7 V and

V, = 12 V. The voltage at the base of Q; is Vgi = Vo + Vpp) = 12.7 V.

Also, Va; = Vs — Vp = 5.3 V. The current through R; is largely the collector current of Qo.

760

Electronic Devices and Circuits

Now suppose the output voltage drops slightly for some reason. When Vo

decreases, Vp decreases. Because the emitter voltage of Q> is held at Vz, any decrease in Vp appears across the base-emitter of Qo. A reduction in Ver

causes Ic) to be reduced. When Ic: falls, Vri is reduced, and the voltage at the

base of Q; rises (Vpi = Vs — Vri) causing the output voltage to increase. Thus, a decrease in V, produces a feedback effect which causes V, to increase

back toward its normal level. Similarly, a rise in V. above its normal level produces a feedback effect that pushes V, down again toward its normal

level.

When the input voltage changes, the voltage across resistor R, changes in order to keep the output constant. This change in Vp; is produced by a change in Ic2, which itself is produced by a small change in V4. Therefore, a

supply voltage change (AVs) produces a small output voltage chan ge (AV,).

The relationship between AVs and AV, depends upon the amplification of

the error amplifier. Similarly, when the load current (J;,) changes, Ip; alters as necessary to increase or decrease Ip. The Ip; variation is produced by a

change in Ico, which, once again, is the result of an output volta ge variation AV,.

Series Regulator Performance The performance of a series regulator without an error amplifier (Fig. 18-1) is

similar to that of a Zener diode regulator (see Section 3-7), except in the case

of the load effect. The series-pass transistor tends to improve the regulator

load effect by a factor equal to the transistor /ipp.

The error amplifier in the regulator in Fig 18-3 (reproduced from Fig. 18-2) improves all aspects of the circuit performance by anamount directly related to

the amplifier voltage gain (A,). When Vs changes by AVg, the output change is Me

i=

AV,

(18-1)

~

Figure 18-3

Voltage

variations at the input of

a regulator with an error amplifier are reduced by

a factor equal to the ©

amplifier voltage gain.

Chapter 18

Linear and Switching Voltage Regulators

761

If AVs is produced by a variation in the ac supply voltage, the power supply source effect is reduced by a factor of Ay. AVs might also be the result of an increase or decrease in load current that causes a change in the average

level of the dc supply voltage. Thus, the load effect of the power supply is reduced by a factor of Ay.

Now

consider the effect of supply voltage ripple on the circuit in

Fig. 18-3. The ripple waveform appears at the collector of transistor Qi. If there were no negative feedback, it would also be present at Q: base and at the regulator output. However, like supply voltage changes, the input ripple is reduced by a factor of A, when it appears at the output. The ripple rejection ratio is calculated as the decibel ratio of the input and output ripple voltages.

Example 18-1

The supply voltage for the regulator in Fig. 18-3 has Vs = 21 V on no load, and Vs = 20 V when It(maxy = 40 mA. The output voltage is Vo = 12 V, and the regulator has an error amplifier with a gain of 100. Calculate the source effect, load effect, line regulation, and load regulation for the complete power supply. Also determine the ripple rejection ratio in decibels. Solution

Eq. 3-25: :

—

wi:

Source effect = AV, (for AVs = 10%) AV,

°

=

AVs

Ay

—

10% of 21 V

100

= 21mV

Eq. 3-27:

Eq. 18-1: :

Load effect = AVo for Altimax)

20V 21V-—20V = AVs _ stv

AV. °

100

Ay

=10mV

Eq. 3-26:

S = ) xx 100%of, e ffect) Line regulation = (Source oO

_ 2 mV 12Vx 100% = 0.175%

Eq. 3-28:

eff Load Load regulation = Cond ae) * 100% oO

_ 10mV

x 100% 12V

%,

762

Electronic Devices and Circuits

= 0.08% Ripple rejection = 20 log (1/Ay) = 20 log (1/100) = —40 dB

Regulator Design To design a series regulator circuit (as in Fig. 18-3), the Zener diode is selected to have Vz less than the output voltage. A Zener diode Voltage approximately equal to 0.75 V, is usually suitable. Appropriate current levels

are chosen for each resistor, and the resistor values are calculated using Ohm’s law. Transistor Q, is selected to pass the required load current and to survive

the necessary power dissipation. A heat sink (see Section 8-8) is normally

required for the series-pass transistor in a regulator that supplies large load currents. As has been explained, a large capacitor is usually connected across the output to ensure amplifier ac stability (C; in Fig. 18-3).

The difference between the regulator input and output voltages is the collector-emitter voltage of the series-pass transistor (Q;), and this voltage must be large enough to keep the transistor operational. The minimum level

of Vcr (known as the dropout voltage) occurs at the lowest point in the ripple waveform of raw dc input (rectified and filtered). If Veg) is too small for correct operation at this point, a large-amplitude ripple waveform appears at

the regulator output. Example 18-2 Design the voltage regulator circuit in Fig. 18-4 to produce V, = 12 V and Timax) = 40 mA. The supply voltage is Vs = 20 V.

Figure 18-4 Voltage regulator circuit for

Ex. 18-2.

Solution Select

Vz~0.75 V, =0.75 X 12 V

=9V

For D,, use a 1N757 Zener diode with Vz = 9.1 V (see data sheet A-4 in Appendix A)

Linear and Switching Voltage Regulators

Chapter 18

763

For minimum D, current, select Tro

=

Ry =

10

mA

Vo-Vz

=

12V-91V

TR

10 mA

= 290 0 (use 270 0 standard value)

Te1max) © IL(max) + Ir2 = 40 mA + 10 mA =50mA

Specification for Qi: VcE1(max) oe Vs

=20V =50mA

leagmax) ~ Ftd

Ppanax)

Vo) X TEa(max)

—

= (Vs

=

-

(20V

12 V)

= 400 mW Assuming

hegimin) = 50 I

_

ana

TE1 (max)

HEE 1 (min)

_

50 mA

50

=l1mA leo > TBi(max)

Select

Io = 5 mA

Ve—Veaq

Ry

~ Teo + Ip

20V

—-G2V

+0.7¥)

5mA +1mA

= 1.21 kO (use 1.2 kO standard value)

Iz = Ik. + IR2=5mA+10mA =15mA

I, >> Ipi(max) Select

Ig=1mA

R=

Vz + Ver _ 9.1V + 0.7V

‘

I4

1lmA

= 9.8 kQ (use 10 kO standard value) 7

a

Vo — Vra

&

_ 2V-98V

1mA

= 2.2 kO (standard value)

X

50mA

764

Electronic Devices and Circuits

Practice Problems 18-1.1

A 12 V de power supply has an 18 V filter circuit. There is a 1 V drop in Vs regulator has an error amplifier with effect; load effect, line regulation, and

input (Vs) from a rectifier and from no load to full load. If the A, = 70, calculate the source load regulation.

18-1.2 A voltage regulator circuit as in Fig. 18-4 has Vs = 25 V, and is to produce

V, = 15 V with Kmax)

= 60 mA.

Design

the circuit and

specify the series transistor. Assume /tpei(min) = 100.

18-2 IMPROVING REGULATOR PERFORMANCE Error Amplifier Gain The performance of a regulator is dependent on the voltage gain of the error amplifier (see Eq. 18-1). A higher-gain amplifier gives better line and load regulation. So anything that improves the amplifier voltage gain will improve the regulator performance. Two possibilities for increasing A, are: use a transistor with a high hpg value for Qo, and use the highest possible

resistance value for Rj.

Output Voltage Adjustment Regulator circuits such as the one designed in Ex. 18-2 are unlikely to have Vo exactly as specified. This is because of component tolerances,

as well

as, perhaps,

not

finding

standard values close to the calculated values. Hence, some form of adjustment is required to

enable the output voltage to be set to the desired level. In Fig. 18-5, the potentiometer (Rs) connected between

provides output adjustment. The maximum output

voltage

level

oO —)

resistors R3 and Ry,

is produced

when

the

potentiometer moving contact is at the bottom

Figure 18-5

Use ofa

Pelenuemeter to provide regulator output voltage

adjustment.

of Rs:

Kae

Rai + Ry + Rs

Ry

xX Veo

(18-2)

Minimum V, occurs when the moving contact is at the top of Rs:

Vopnin) =

R3 + Rg + Rs

Ra eR,

VB

(18-3)

Chapter 18

Example

Linear and Switching Voltage Regulators

765

18-3

Modify the voltage regulator circuit in Ex. 18-2 (as in Fig. 18-6) to make V,

adjustable from 11 V to 13 V.

rVe

V54

Figure 18-6 Adjustable output regulator circuit for Ex. 18-2.

Solution Select

I4qnin) = 1 mA

For Vo = 11 V (moving contact at top of Rs),

_Vo- Vm _ UV -98V

Re

= :

T4(min)

lmA

= 1.2 kO (standard value) Rg

+

Rs

V

=

9.8V

Bs

T4(min)

7

imA

= 9.8kO

For V, = 13 V (moving contact at bottom of Rs), ok fs = Vo _ 13 V 4 becomes 4 Rg + Ra+ Rs 1.2k0+98k0

=1.18mA Veo 98V emA Ig =1.18

hy =

= 8.3 kO (use 8.2 kQO standard value)

Rs = (Ra+ Rs) — Ra= 9.8 kO — 8.2 kO, = 2.6 kO (use 2.5 kO standard value potentiometer)

766

Electronic Devices and Circuits

High-Output-Current Circuit For the circuit in Fig. 18-6 to function correctly, the collector current of Q2 must be larger than the maximum base current flowing into Q). In regulators that supply a large output current, Ip; can be too large for Ic2 to control. In this case, an additional transistor (Q3) should be connected at the base of Q; to forma Darlington circuit (or Darlington pair), as in Fig. 18-7. Transistor Q; is

usually a high-power BJT requiring a heat sink (see Section 8-8), and Q; is a low-power device. The Q; base current is

Tp

= +Ty

3

(18-4)

Neer X pes

The current gain for the Darlington is Mpg, X hpg3, and Ip3 is low enough that Ic2 may easily be made much greater than Ip3. In Fig. 18-7 note resistor Rg, which is included to provide a suitable minimum Q; operating current when

I, is very low. Darlington

ges

Ry S

pair

oy Q

on YS

Tey

I,

Ia|

| Ip3

Q,

7

Figure 18-7

.

An additional

transistor (Q3) connected at the base of Q; to constitute a

D;

Re

:

Ry

Darlington circuit allows a voltage regulator to supply a

=

O-——

,

me

higher output current.

Darlington transistors consisting of a pair of BJTs (low-power and high-

power) fabricated together and packaged as a single device are available. These are usually referred to as power Darlingtons. The 2N6039 is an npn

power Darlington with an hg specified as 750 minimum, 18 000 maximum. Resistor Rg in Fig. 18-7 is not required when a power Darlington is used.

Example 18-4 Modify the voltage regulator circuit in Ex. 18-2 to change the load current to 200 mA. Use a Darlington circuit (as in Fig. 18-7), and assume that /ipg1 = 20 and that hgg3 = 50. Specify transistor Q).

Chapter 18

Linear and Switching Voltage Regulators

767

Solution

Te1(max) © Tmax) + Io = 200 mA + 10mA = 210 mA

—

Te1(max) _ 210 mA hep

20

= 10.5mA

Frovesauy = Te1(max) _ 10.5 mA Nps

50

= 0.21 mA

Ic2 > Tp3qmax) Select

Ico = 1 mA

_ Ve-Vg3 _ 20V-(12V+07V+0.7V) Tetlps mA +021mA = 5.45 k© (use 5.6 kQ standard value) Select

Ig = 0.5 mA

_Vo+ Vpn

12V+07V

og

(5 mA

= 25.4 kQ (use 22 kO standard value) Specification for Q::

Veei(max) ¥ Vs = 20 V Te1qmax) © Te1¢max) = 210 mA

Ppimax) = (Vs — Vo) X Teiqmax) = (20 V — 12 V) X 210 mA = 1.68 W

Preregulation Refer to Fig. 18-8, which is a partial reproduction of Fig. 18-2. Note that resistor Rj is supplied from the regulator input, and consider what happens

when the supply voltage drops by 1 V. If Ic does not change, the voltage across R; remains constant, and the 1 V drop also occurs at the base of Q,; and

at the output of the regulator. This does not happen, of course. Instead, Ic2

changes to reduce the voltage across R; and thus keep the output voltage close to its normal level. The change in Ic: is produced by a small change in the output voltage. If Ry is connected to a constant-voltage source instead of

the input, the change in Ic. would not be required when Vs changes, and consequently the output voltage change would not occur.

768

Electronic Devices and Circuits

o~

Figure 18-8 A change in a regulator supply voltage (AVs) produces an output change (AV, = AVs/A\).

6

Now look at Fig. 18-9a where R; is shown connected

to another Zener

diode voltage source (R7 and D2). This arrangement is called a pre-regulator, When

Vs changes, the change in Vz2 is negligible compared

to AVs. Thus,

virtually no change is required in Icz and V,. A preregulator substantially

connected

across transistor Q;. This gives an R; supply

voltage of V;

lly

improves the line and the load regulation of a regulator circuit. The minimum voltage drop across R; should typically be 3 V. (Small values of R; give low amplifier voltage gain.) A minimum of perhaps 6 V is also required across R7 to keep a reasonably constant current level through D>. Figure 18-9b shows another preregulator circuit that has R7 and D,

(Vo + Vz2).

Preregulator

Qa

ES

o—

aeMES Ls

(a) Preregulator at the input Figure 18-9

(b) Preregulator connected between input and output

A preregulator circuit improves the performance of a voltage regulator.

Chapter 18

Linear and Switching Voltage Regulators

769

Example 18-5 Determine suitable component values for a preregulator circuit as in Fig. 18-9a for the voltage regulator modified in Ex. 18-4. Solution Select

Vrimin) = 3 V

R,

= _Vri :

~~ 3V

Ico + Ign

= 1 mA

+ 0.21 mA

= 2.5 kO (use 2.7 kO, standard value) Vz2=

Vo + Vee + Ver3 + Vai

=12V+07V+07V4+3V

= 16.4 V (use a IN966A with Vz = 16 V. Alternatively, use a 1N753 and a 1N758 connected in series.

See data sheet A-4 in Appendix A). Ir7 >> I, and Iz2 > (Izx for Zener diode D2) Select

Ir7=5mA

Vs—-Vz Ro

=

;

20V-—16V =

I R77

5mA

= 800 2 (use 820 0 standard value)

Constant-Current Source The constant-current source shown in Fig. 18-10 may be used in place of resistor R; as an alternative to a preregulator circuit. This arrangement passes all the required current to Q3 base and Q) collector, but it behaves as a very

°

Constant-current source

we

Qi

ne

|

Q,

Ry ¢

od

Figure 18-10 A constant-current source can be used as an alternative to a

preregulator circuit to improve regulator performance.

770

Electronic Devices and Circuits

high resistance (1/hoe4) at the collector of transistor Qo. Consequently, it increases

the

error

amplifier

voltage

gain

and

results

in

a

substantial

improvement in the regulator performance. To design the constant-current source,

Vcg4 should

typically be a minimum

of 3 V. The

various voltage

drops and current levels are then easily determined for component selection,

Differential Amplifier Figure 18-11 shows a regulator that uses a differential amplifier or difference amplifier (see Section 12-8). In this circuit, Zener diode Dy is the voltage reference source, and D, is used only to provide an appropriate voltage level Q

—O

+

\ pL I

(+ o-

L—o Figure 18-11

Use of a differential amplifier (Qs and Q¢) improves the regulator

performance by improving the gain of the error amplifier and by using D2 as a stable voltage reference source.

at the emitter of transistor Q2. Vo is divided to provide Vx¢, which is compared to Vz. Any difference in these two voltages is amplified by Qs, Q., Q., and the associated components, and is then applied to the base of Q; to

change the output in the required direction. The performance of the regulator is improved

by the increased voltage

gain of the error amplifier. However, the performance is also improved in

another way. In the regulator circuit in Figs 18-2 and 18-7, when Ic; changes,

the current through D, is also changed (Iz; = Ir2 + Iz). This causes the Zener

voltage to change by a small amount, and this change in Vz; produces a change in output voltage. In the circuit in Fig. 18-11, the current through the reference diode (D2) remains substantially constant because it is supplied from the regulator output. Therefore, there is no change in output voltage

due to a change in the reference voltage. Example 18-6 Design the differential amplifier stage for the regulator in Fig. 18-11. Use the

Q:, Qo, Q3 stage already designed in Examples 18-2 and 18-4. The output voltage is to be adjustable from 10 V to 12 V. (See Fig. 18-12.)

Chapter 18

—_Linear and Switching Voltage Regulators

771

| Tro

Ro

3.3kQ

Ry

ue

Differential amplifier Figure 18-12 circuit for Ex. 18-6.

5.6kQ

+—_—©o

Solution Vos

Select

=

Voces

Veo

=

9.8

V

—

Vers =9.8V-3V

=3V

Vro

=

Vos

= 6.8 V Vzo =

Vro + Vegs = 6.8V+0.7V

= 7.5 V (use a 1N755 Zener diode)

Ic5 >> Ip Select

Ickg =1mA

R=

Vi Veo _ DY, - 98V los

ImA

= 2.2 kQO (standard value) Ipgp ¥2

X Ic¢g = 2mA

Vero Rg

=

OO

68V Ss

Trg

2mA

= 3.4 kO, (use 3.3 kO standard value) Iz >> Ips and Iz2 > (Izx for the Zener diode)

Select

Iz2 = 10mA R=

V.— Vz

7

Iz

_ IV

=75V

10 mA

= 450 2 (use 470 2 standard value) I, >

Ip

772 = Electronic Devices and Circuits

Select

-

I4j= 1 mA V6

=

Vz

=7.5V

When V, = 11 V (moving contact at the top of Ks), Vo~ Vege TV - 7BV Rg

SOS

[4

1mA

= 3.5 kO (use 3.3 kQ standard value)

I, becomes

I4

_Vo~ Ves _ UV3.3 ~75V 7 Rg mA = 1.06 mA

Veg

7.5 V

Ra + Rs = & ~ 1.06 mA = 7.07 kO, When V, = 13 V (moving contact at the bottom of Ks),

I, becomes

I,

Vo ~ Ry + Ry + Rs

-

13V 3.3k0 + 7.07kO

=1.25mA R4

=

Ves ‘Ty

7.5V 1.25mA

= 6.25 kO (use 5.6 kQ standard value) Rs = (Rq + Rs) — Rg = 7.07 kO — 5.6 kO. = 1.47 kO (use 1.5 kO standard value potentiometer)

Practice Problems 18-2.1

A voltage regulator circuit as in Fig. 18-6 uses a 6.2 V Zener diode. Determine suitable resistor values for R3, R4, and Rs to produce an

output adjustable from 9 V to 12 V. 18-2.2 A voltage regulator has an 18 V supply, a 10 V output, and a 150 mA

load current. The circuit uses Darlington connected transistors, as in Fig. 18-7. Calculate suitable resistor values, and specify transistor Q). Assume that fe; = 20 and Mp3 = 50.

18-2.3 Determine’ suitable components for the constant-current circuit in Fig. 18-10. Assume that the supply voltage is 20 V, the output is 12 V, and that Ip3 is 100 wA.

18-3

CURRENT LIMITING

Short-Circuit Protection Power supplies used in laboratories are subject to overloads and short circuits. Short-circuit protection by means of current-limiting circuits is

Chapter 18

Linear and Switching Voltage Regulators

773

necessary in such equipment to prevent the destruction of components when an overload occurs. Transistor Q7 and resistor Rig in Fig. 18-13a constitute a current-limiting circuit. When the load current ([,) flowing through resistor Rio is below the maximum design level, the voltage drop Vaio is not large enough to forward-bias the base-emitter junction of Qy. In this case, Q7 has

no effect on the regulator performance. When the load current reaches the selected maximum (I,(max)), Vaio biases Q, on. Current Ic7 then produces a voltage drop across resistor R, that drives

the output voltage down to nearly zero. The voltage/current characteristic of the regulator is shown in Fig. 18-13b. It is seen that output voltage remains constant as the load current increases up to IL(max). Beyond It(max), Vo drops to zero, and a short-circuit current (Isc) slightly greater than It(max) flows at the output. Under these circumstances, series-pass transistor Q; is carrying all of the short-circuit current and has

R 10

—>

Thpax)

Isc

(b) V,/I, characteristic of current-limiting circuit Figure 18-13

Regulator overload protection circuit. When I, increases to a maximum

pulls Q; base down, causing V, to be design level, Vaio causes Q; to conduct, and this

reduced to almost zero.

774

Electronic Devices and Circuits

virtually all of the supply voltage developed across its terminals. So the power dissipation in Q; is

Obviously, a Q; must be selected to survive this power dissipation.

Design

of the current-limiting

circuit

in Fig.

18-13

is very

|

simple.

Assuming that Q; is a silicon transistor, it should begin to conduct when Vrio ¥ 0.5 V. Therefore, Rio is calculated as

Rio ©

0.5 V

(18-6)

TL max)

Fold-Back Current Limiting A problem with the simple short-circuit protection method just discussed is that there is a large amount of power dissipation in the series-pass transistor while the regulator remains short-circuited. The fold-back current-limiting circuit in Fig. 18-14a minimizes this transistor power dissipation. The graph

(a) Fold-back current-limiting circuit

Normal V, —

| 4

oO

hse Isc

I L(max)

(b) Characteristic of fold-back current-limiting circuit

Figure 18-14

Fold-back current limiting. The short-circuit current (Isc) is less than Imax:

and thus the power dissipation in Q; is minimized.

Chapter 18

Linear and Switching Voltage Regulators

775

of Vo/IL in Fig. 18-14b shows that the regulator output voltage remains constant until IL(max) is approached. Then the current reduces (or folds back) to a lower short-circuit current level (Isc). The lower level of Isc produces a

lower power dissipation in Q,. To understand how the circuit in Fig. 18-14 operates, first note that when the output is shorted, V, equals zero. Consequently, the voltage drop across resistor Ry is almost zero. The voltage across Rio is Isc X Rio, and (as in the simple short-circuit protection circuit) this is designed to just keep transistor

Q, biased on. When the regulator is operating normally with J, less than Iumax), the voltage drop across Ry; is

Vriu ©

Vo

X

Run

Ry + Rig

To turn Q; on, the voltage drop across R1y must become larger than Vai; by

enough to forward-bias the base-emitter junction of Q7. Using Vpg7 ~ 0.5 V and making Vai ~ 0.5 V gives Fi anax) Rio

=05V+

0.5 V=1

V

With IscRip = 0.5 V, TLimax) © 2 Isc (See Fig. 18-14 b)

If Vex is selected as 1 V,

Tmax Rip = 05V+1V=15V and

Tuqmax) © 31Isc The fold-back current-limiting circuit is designed by first calculating Ry

to give the desired level of Isc. Then, the voltage-divider resistors (Ri, and

Ri) are calculated to provide the necessary voltage drop across Ry for the required relationship between Isc and It (max):

Example 18-7 Design a fold-back current-limiting circuit for a voltage regulator with a 12 V output. The maximum output current is to be 200 mA, and the short-circuit

current is to be 100 mA. (See Fig. 18-15.) Solution Isc

Select

=

100mA

Vrio © 0.5 V at short circuit Verio

0.5 V

Rio = F50 SC ~ 100mA = 5 Q (use 4.7 © standard value)

776

Electronic Devices and Circuits

4.70

Rio

Wz

” Ven

>

I,

=)

4 R10

$

Ry

4700 Hin

r Vo

Ry

Figure 18-15 _|

At Ih(maxy

Fold-back curreni-limiting

circuit for Ex. 18-7.

Vrio = Iugmax) X Rio = 200mA

X 4.7 O

= 0.94 V

Vani = (It(maxyRio) — 0.5 V = 0.44 V Ty, >> [pz Select

Iy =1mA

Ry =

Ven

044V

Ty

1mA

= 440 2 (use 470 © standard value)

p,, = vot Ve - Ven _ 12V + 0.94V — 044V bi 1mA = 12.5 kO (use 12 kO standard value)

Practice Problems 18-3.1 A short-circuit protection circuit, as in Fig. 18-13, is to be designed to limit the output of a 15.V regulator to 400 mA. Select a suitable value for Rip and specify Qi. Assume that Vs = 25 V.

18-3.2 Modify the circuit designed for Problem 18-3.1 to convert it to a foldback current-limiting circuit with a 150 mA short-circuit current.

18-4 OP-AMP VOLTAGE REGULATORS Voltage-Follower Regulator Refer once again to the voltage regulator circuit in Fig. 18-11. The complete error amplifier has two input terminals at the bases of Qs and Qg and one output at the collector of Q). Transistor Qs base is an inverting input, and Q: base is a non-inverting input. The error amplifier circuit is essentially an

Chapter 18

Linear and Switching Voltage Regulators

777

operational amplifier. Thus, IC operational amplifiers with their extremely

high open-loop voltage gain are ideal for use as error amplifiers in dc voltage regulator circuits. Normally, an internally compensated op-amp (such as the 741) is quite suitable for most voltage regulator applications. A simple voltage-follower regulator circuit is illustrated in Fig. 18-16. In

this circuit, the op-amp output voltage always follows the voltage at the noninverting terminal; consequently, V, remains constant at Vz. The only design calculations are those required for the design of the Zener diode voltage reference circuit (RK; and D,) and for the specification of Qi. +0

Vs

—0O

Figure 18-16 Operational amplifier connected as a voltagefollower regulator. The output voltage is held constant at V2.

Adjustable Output Regulator The circuit in Fig. 18-17 is that of a variable-output, highly stable dc voltage regulator. As in the transistor circuit in Fig. 18-11, the reference diode in

Fig. 18-17 is connected at the amplifier non-inverting input, and the output voltage is divided and applied to the inverting input. The operational amplifier positive supply terminal has to be connected to the regulator supply voltage. If it were connected to the regulator output, the op-amp output voltage

(at Qo base) would have to be approximately

than its positive supply terminal, and this is impossible.

YS

—-oO

— | -2—O

Highly stable, adjustable-output voltage Figure 18-17 regulator using an operational amplifier.

1.4 V higher

778

Electronic Devices and Circuits

Design of the regulator circuit in Fig. 18-17 involves selecting R; and Dj, design of the voltage-divider network (Ks, R4, and Rs), and specification of

transistors Q; and Q>. Clearly, an op-amp voltage regulator is more easily designed than a purely transistor regulator circuit. Example 18-8 Design the voltage regulator circuit in Fig. 18-18 to give an output voltage

adjustable from 12 V to 15 V. The maximum output current is to be 250 mA, and

the supply voltage is 20 V. Assuming

that hrm,

=

20 and

Mp

estimate the op-amp maximum output current.

Figure 18-18

Op-amp voltage regulator for Ex. 18-8.

Solution Vz * 0.75 Vorminy = 0.75 X 12'V =9V Use a 1N757 diode with Vz = 9.1 V Iz >> (op-amp Ipmmax)) and Iz > (Izx for the diode) Select

Iz=10mA

Vowmin) R,

Vz _ 12V—-9.1V

= Iz

10 mA

= 290 Q (use 270 © standard value)

I3¢@min) => (Op-amp Ip(max)) Select

I3(mnin) =1mA

When V, = 12 V (moving contact at top of Rs)

R, = oz _ BV-91V 3

Ts¢nin)

1mA

= 50,

_Linear and Switching Voltage Regulators

Chapter 18

779

= 2.9 kO, (use 2.7 kO standard value)

= 21V

2

Ry+ Rp=

I3¢min)

1 mA

=91kO

When V, = 15 V (moving contact at bottom of Rs), I; becomes

15 V

I; = —Vo

R3+ Rat Rs

2.7kQ + 9.1k2

= 1.27mA Rg

=

Vz

91V

I;

1.27mA

= 7.16 kO (use 6.8 kO standard value)

Rs = (Rg+ Rs) — Rg= 9.1k0 — 6.8 kD. = 2.3 kO (use 2.5 kO potentiometer) Select

Ir6 = 0.5mA

Re

_ vo _ WV Tre

0.5

mA

= 24 kQ (use 22 kO standard value)

Op-amp output current:

me. =

oe

Tu@max)

_ 250mA

lie te | 2K BO = 0.25 mA

Current Limiting with an Op-amp Regulator When a large output current is to be supplied by an operational amplifier voltage regulator, one of the current-limiting circuits described in Section 18-3 may be used with one important modification. Figure 18-19 shows the

modification. A resistor (R13) must be connected between the op-amp output terminal and the junction of Qog and Q7c. When an overload causes the regulator output voltage to go to zero, the op-amp output goes high (close to Vs) as it attempts to return V, to its normal level. Consequently, because the

op-amp normally has a very low output resistance, Rj3 is necessary to allow Ic7 to drop the voltage at Q. base to near ground level. The additional resistor at the op-amp output is calculated as R13 ~ Vs/Ic7. Resistor R13 must not be so large that there is an excessive voltage drop across it when the regulator is supposed to be operating normally.

780

Electronic Devices and Circuits

rn a os

ee

WA Rio

L

ON

|

\— OFigure 18-19 When current limiting is used with an op-amp regulator, a resistor (R;3) must be included in series with the op-amp output.

Practice Problems 18-4.1

Design

an

op-amp

voltage-regulator

circuit

as

in

Fig.

18-17 to

produce an output adjustable from 15 V to 18 V, with a 300 mA maximum load current. The supply voltage is 25 V.

18-4.2 Design

a fold-back current-limiting

circuit

for

the

regulator in

Problem 18-4.1, to give IL(maxy = 300 mA and Isc = 200 mA when [a

15.

18-5

IC LINEAR VOLTAGE REGULATORS

723 IC Regulator The basic circuit of a 723 IC voltage regulator in a dual-in-line package is

shown in Fig. 18-20. This IC has a voltage reference source (Dj), an error amplifier (Aj), a series pass transistor (Q:), and a current-limiting transistor (Q2), all contained in one small package. An additional Zener diode (D)) is 14

13 mM

+Vec 12 4

Ve 11 I

Output 10 ry

9

8 m

Figure 18-20 The 7231C voltage regulator contains a reference diode (D,), an error amplifier (A;), a seriespass transistor (Q;), a

current-limiting transistor

(Qa), and a voltage-dropping diode (D2).

Chapter 18

Linear and Switching Voltage Regulators

784

included for voltage dropping in some applications. The IC can be connected

to function as a positive or negative voltage regulator with an output voltage

ranging from 2 V to 37 V and output current levels up to 150 mA. The maximum supply voltage is 40 V, and the line and load regulations are each specified as 0.01%. A partial specification for the 723 regulator is given in

data sheet A-16 in Appendix A. Figure 18-21 shows a 723 connected to function as a positive voltage regulator. The complete arrangement (including the internal circuitry

shown in Fig. 18-20) is similar to the op-amp regulator circuit in Fig. 18-17.

One difference between

the two circuits is the 100 pF capacitor

(Ci)

connected to the error amplifier output and its inverting input terminal.

This capacitor is used instead of a large capacitor at the output terminals to prevent the regulator from oscillating. (Sometimes both capacitors are required.) By appropriate selection of resistors R; and R in Fig. 15-21, the

regulator output can be set to any level between 7.15 V (the reference

voltage) and 37 V. A potentiometer can be included between Ky and R2 to

make the output voltage adjustable.

re

wlllls Go

V.

s

4

723 14

—-

Rs Wr

Tt 1 f

4

1

1

!

|

I

|

|

=

|2

! Sh

!

I

I

I

_ ference

o-

Figure 18-21

!

!I

| LIZ

|

|

|

—o +)

|

|

Li

°

1 S* T_.~*

Voltage regulator circuit using a 723 IC regulator. The

output voltage range is 7 V to 37 V.

The dashed lines (in Fig. 18-21) show connections for simple (non-foldback) current limiting. Fold-back current limiting can also be used with the

723. It is important to note that, as for all linear regulator circuits, the supply voltage at the lowest point on the ripple waveform should be at least 3 V

greater than the regulator output; otherwise a high-amplitude output ripple might occur. The total power dissipation in the regulator should be calculated to ensure that it does not exceed the specified maximum.

The

specification lists 1.25 W as the maximum power dissipation at a free air

782

Electronic Devices and Circuits

temperature of 25°C for a DIP package. This must be derated at 10 mW/°C for higher temperatures. For a metal can package, Ppymax) = 1 W at 25°C free air temperature, and the derating factor is 6.6 mW /°C. An external series-

pass transistor may be Darlington-connected to (internal transistor) Q; to enable a 723 regulator to handle a larger load current. This is illustrated in

Fig. 18-22.

100 pF

a

+ a

Figure 18-22 An external series-pass transistor may be added to a 723 IC voltage regulator to supply higher load currents than the 723 can normally handle.

A regulator output voltage less than the 7.15 V reference level can be obtained by using a voltage divider across the reference source (terminals 6 and 7 in Fig. 18-20). Terminal 5 is connected to the reduced reference voltage,

instead of to terminal 6. Example 18-9 The regulator circuit in Fig. 18-23 is to have an output of 10 V. Calculate resistor values for R; and R2, select a suitable input voltage, and determine the maximum load current that may be supplied if Ppgmax) = 1000 mW.

Solution Ip > Select

(error amplifier input bias current)

Ih=1mA

Vro = Vrep = 7.15 V

p= 2"

bb

et

EY

ImA

= 7.15 kQ (use 6.8 kO standard value, and recalculate I»)

Chapter 18

Linear and Switching Voltage Regulators *

(+0

Ry 7 2.7kO

15V

/

=(10V

its Tr

uF Figure 18-23

Ilbecomes

e

[,

|

2

=

Veeg —= Ro

Regulator circuit for Ex. 18-9.

7.15V -6.8kO

= ——

= 1.05mA

a,

8 :

Veep _ 10V — 7.15V h 1.05 mA

= 2.85 kO, (use 2.7 kO standard value) For satisfactory operation of the series pass transistor,

Select

Vs—V,=5V

V5 =Vo+5V=10Vt5V =15V The internal circuit current is

SeenON

erste

aoa

Istandby) + ret © 25 mA

The 723 internal power dissipation on no-load is

P, = Vg X (Iistandby) + Jret) = 15 V X 25 mA = 375 mW Maximum power dissipated in the (internal) series-pass transistor:

Pp = (specified Ppimax)) — Pi = 1000 mW

eck Be satan

ee

= 625 mW Maximum load current: Pp TL(max) = Vs—Vo =125mA

_ 625mW ~ 5V

— 375 mW

783

784

Electronic Devices and Circuits

LM317 and LM337 IC Regulators The LM317

and LM337

IC regulators are three-terminal

devices

that are

extremely easy to use. The 317 is a positive voltage regulator (Fig. 18-24a), and

the 337 is a negative voltage regulator (Fig. 18-24b). In each case, input and output terminals are provided for supply and regulated output voltage, and an adjustment terminal (ADJ) is included for output voltage selection. The

output voltage range is 1.2 V to 37 V, and the maximum load current ranges from 300 mA to 2 A, depending on the type of device package. Typical line and load regulations are specified as 0.01% /(volt of V,), and 0.3%/(volt of Vo),

respectively. The internal reference voltage for the 317 and 337 regulators is typically 1.25 V, and Viet appears across the ADJ and output terminals. Consequently, the regulator output voltage is

Vo

=

2

x

VREF

(18-7)

LM337

O +

O— (a) LM317 positive voltage regulator

Figure 18-24

_

In

Out

Coal

9

O—)

|

+0 (b) LM337 negative voltage regulator

Application of the LM317 and LM337 integrated circuit voltage regulators.

The internal reference voltage appears across resistor Rj.

To determine suitable values for R; and R2 for a desired output voltage,

first choose a voltage-divider current (I;) that is much larger than the current that flows in the ADJ terminal of the device. This is specified as 100 pA maximum

on the device data sheet. The resistors are calculated from the

relationship in Eq. 18-7. Note the capacitors included in the regulator circuits. Capacitor Cin is

necessary only when the regulator is not located close to the power supply

filter circuit. Cj, eliminates the oscillatory tendencies that can occur with long connecting leads between the filter and regulator. Capacitor C, improves the transient response of the regulator and ensures ac stability, and Cau; improves the ripple rejection ratio.

Chapter 18

Linear and Switching Voltage Regulators

785

Figure 18-25 shows the terminal connections for

ae.

Mae

LM317 and LM337 regulators in 221 A-type packages.

cMat?

LM337

O

O

Example 18-10 An LM317 regulator is to provide a 6 V output from a 15 V supply. The load current is 200 mA.

|

Determine suitable resistance values for R, and R2 (Fig. 18-24), and calculate the regulator power dissipation. Solution

Figure 18-25

Vin Vo

AD!

connections

I, >> Iapy

Terminal for

LM317 and LM337 IC

regulators contained

b=1mA

Select

ALY

ry ADT Vom Vin

in 221A packages.

Ri =

1.25 V pop es

Viet

I;

1mA

= 1.25 kO (use 1.2 kO standard value) Va R»

—

Ve¢ —

I,

6V—-135V 1mA

= 4,75 kO (use 4.7 kO standard value)

Pp = (Vs — Vo) X ILimaxy = (15 V — 6 V) X 200 mA =1.8W

LM340 Regulators LM340 devices are three-terminal positive voltage regulators with fixed output voltages ranging from a low of 5 V toa high of 23 V. The regulator is selected for the desired output voltage and then simply provided with a voltage (Vs) from a power supply filter circuit, as illustrated in Fig. 18-26. Here again, capacitor C, is required only when the regulator is not close to the

filter. The LM340

data sheet specifies the regulator performance for an output

current of 1 A. The tolerance on the output voltage is + 2%, the line regulation is 0.01% per output volt, and the load regulation is 0.3% per amp of load current.

LM340

|

Gnd Cy

Vo

Figure 18-26

«= O36

_

:

The LM3840 is a fixed output

IC voltage regulator with an output selectable from 5 V to 23 V.

786

Electronic Devices and Circuits

The IC includes current limiting and a thermal shutdown circuit that protects

against excessive internal power dissipation. As with all series regulators, a heat sink must be used when high power dissipation is involved.

Practice Problems 18-5.1 Design the regulator circuit in Fig. 18-22 to have an 18 V, 200 mA output. Include short-circuit protection, and specify Q>.

18-5.2

Using an LM317, design a 9 V, 150 mA voltage regulator. Select a

supply voltage, and calculate the regulator power dissipation.

18-6

SWITCHING

REGULATOR

BASICS

Switching Regulator Operation A switching regulator can be thought of as similar to a linear regulator but with the series-pass transistor operating as a switch that is either off or switched on (in a saturated state). The output voltage from the switch is a pulse waveform which is smoothed into a dc voltage by the action of an LC filter. Switching regulators can be classified as ¢ step-down converter (output voltage lower than input); e step-up converter (output higher than input); or ¢ inverting converter (output polarity opposite to input).

The basic block diagram of a step-down switching regulator in Fig. 18-27 consists of a BJT switch (Q:) (also termed a power switch), an oscillator, a voltage

comparator, a voltage reference source, a diode (D;), and a filter. The switch, oscillator, comparator, and reference source are all usually contained within Integrated circuit controller

Switch (+

Oo—

Ss

Input

Oscillator

V; : 4

A +)

Filter

=

Sy

Voltage comparator

Ry

U4

| Output

Sh

f

Va

—_ A D,

7

Ry

0

Reference voltage EO

Figure 18-27

oO

=,

A switching regulator has a switch (contained in an IC controller), a

filter,

and a diode. The switch converts the dc input into a pulse waveform, and the filter smooths the pulse wave into a direct voltage with a ripple waveform.

Chapter 18

Linear and Switching Voltage Regulators

an integrated circuit controller, as illustrated. The filter usually consists of an inductor and capacitor. The operation of the regulator is as

787

Input voltage yj

follows: e

Oscillator output

Refer to the waveforms in Fig. 18-28. The de

input voltage (Vj) is converted into a pulse FL waveform

(Va) by the action of the switch

!

(Qi) turning on and off. ¢

]

The oscillator switches Q; on, causing current to flow to the filter and the output

voltage to rise. e The voltage comparator

|

output

[|

VA |

compares

the

al

output voltage (divided by R; and R2) to the

En

t—

4

|

reference voltage, and it holds Q; on until Vro equals Vier. Then, Q; is turned off again. e A pulse waveform (Va) is produced at the

input of the filter by Q; turning on and off. a dc output voltage (V.) with a

ripple waveform (V;,).

lott —~1

Output

| os

| | | | | |

ace

te fa bene pH

Vo! Po

Figure 18-28

e The filter smooths the pulse waveform to produce

Switch

: "s

Switching

ae ee

per oa aa tiee

output is a de voltage with a

e The ripple waveform is the result of the filter capacitor charging via the inductor

ripple.

during fon, and then discharging to the load during fog via Dy. (Thise is explained further in Section 18-7.)

In the operation described above, the controller can be thought of as a pulse width modulator; the on time of Q; (pulse width of its output) is increased or decreased as necessary to supply the output current required. Other systems involve control of the switch off time.

Comparison of Linear and Switching Regulators The power

dissipated in the series-pass transistor in a linear regulator is

wasted power. This is not very important when the load current is lower than 500

mA.

With

high

current

levels,

the

regulator

efficiency

becomes

important, and there can also be serious heat dissipation problems.

In a switching regulator, the power dissipation in the switching transistor (whether it is on or off) is very much smaller than in the series-pass transistor of a linear regulator with a similar output voltage and load current. Thus, a switching regulator is more efficient than a linear regulator.

The approximate efficiency of a linear regulator can be calculated by

assuming that the only wasted power (Pp) is that dissipated in the seriespass transistor (see Fig. 18-29a).

788

Electronic Devices and Circuits Vor

Vcr (sat)

a

ath I,

4)

Ger tos)

‘

x

oT

9

Q;

Filter

D Amplifier

Vj

Vv,

reference

V;

o-

[

circuit with

Load

source

V,,

reference

1

source

low

O Pp

Vcr

5

x I,

Pp ce

(a) Linear regulator Figure 18-29

i Vy

Control

and

/-
0 = P__OR, (43.vP_ 21000 =1W

Design Procedure The amplifier in Fig. 19-44 uses four diodes to forward-bias the base-emitter junctions

of the Darlington

output

exactly the same as in Fig. 19-43.

transistors. Otherwise,

the circuit is

856

Electronic Devices and Circuits

Darlington

is Darlington

Ts . Figure 19-44 and 19-17.

—Veg

Power amplifier circuit for Examples 19-16

As always, the peak output voltage and current are calculated from the specified output power and load resistance. The supply voltage is determined using Eq. 19-22, and the emitter resistors for the output stage are typically selected as 0.1R,. The bias network current (J4) should be larger than the peak base current for Q; and Q>. The resistance of R4 (which equals

Rg + Ro) is calculated from I, and the circuit dc voltage drops. Rg should typically be selected as 0.5 Rg, and then Ro, Rio, and Ry, are all equal to Rg.

R, and R3 are equal-value resistors that bias the op-amp input terminals. R> is calculated from R3 to give the required voltage gain. C2 is selected to

have its impedance equal to R; at the desired lower cutoff frequency (f;). The bootstrapping capacitors are calculated in terms of the resistance in series with them: Xc3 = Xc4 = 0.1(Rg||Ro) at fi. The op-amp must have a suitable full power bandwidth (see Section 15-3) to produce the peak output voltage

at the desired upper cutoff frequency for the amplifier.

Example 19-16 The circuit in Fig. 19-44 uses a BIFET op-amp. Ry = 8 2, P, is to be 6 W, and v, = +0.1 V. Q; and Qzare Darlingtons with hpggminy = 1000 and Vex(sat) = 2 V. Determine a suitable supply voltage and resistor values. Also, calculate the

minimum op-amp slew rate to give fz = 50 kHz.

Power Amplifiers

Chapter 19

Solution

From Eq. 19-8,

Vp = V2Rz, Po) =

V2 X 80

X 6W)

=98V

1, =P _ 98V PR,

80

=12A Select

Re

= Ry® 0.1Ry,

=0.1

x 80

20.8 0 Eq, 19-22:

Vec = +[V, + IpnRg + Verxsat)]

=+[98V + (12AX 0.80) +2 V] ~+12.8 V (use £13 V)

1

_/p _12A

Bl(peak)

"ee;

1000

=12mA

I > Ip3(peak) Select

If=2mA

R,

= Vee —Vn—

*

Ym

13V-07V

Li

-07V

2mA

= 5.8kO Rg

= Ro

=

Rio =

Ru

=

0.5 Rg

= 0.5 X 5.8kO = 2.9 kO (use 2.7 kO standard value) Acq

= U9 _ 9.8 V (peak) cL

v,

0.1 V (peak)

= 98

Srdect

R, = R3 = 100 kQ (See BIFET in Section 14-2) R3 Ry = ——

100 kO =

= 1.03 kO (use 1 kQ) Eq. 15-3:

SR = 2nf2Vp = 27 X 50 kHz X 9 V = 2.8 V/ps

857

858

Electronic Devices and Circuits

Example 19-17 Calculate capacitor values for the circuit in Ex. 19-16. The lower cutoff frequency is to be 50 Hz.

Solution Xci

=

0.1R,

C

at fy

1 2arf,XO1R,

—

= 0.318 uF Xoo

=—

1 27X50Hzx0.1X100kO

(use 0.33 F)

= Ro at fi

1

C=

_

QafiRo = 3.18 pF

1

=

2a X 50Hz X 1kO

(use 3.3 wF)

Xc3 = Xcq = 0.1(Rgl|Ro) at fj = 0.1 (2.7 kO||2.7 kQ)

= 1352

1

1

* 2af,Xc, 2mX50Hz 13500 = 23.6 wF (use 25 wF)

Practice Problems 19-8.1 Calculate V,(ouy and P, for the circuit in Fig. 19-39 when Vin = +£0.54 V. Also, determine f; when a 741 op-amp is used. 19-8.2 Calculate the supply voltage for an amplifier as in Fig. 19-44 to deliver 3 W to a 12 © load. Assume that hppqnin)= 1500 and VE (at) = 2 V for Q, and Q>. Determine the op-amp minimum

give fp = 65 kHz.

slew rate to

)

19-9 MOSFET POWER AMPLIFIER WITH OP-AMP DRIVER STAGE Basic Circuit Operation The class AB power amplifier circuit in Fig. 19-45a consists of an operational amplifier (A;), two MOSFETs (Q3 and Q,), and several resistors. The op-amp, together with resistors Ra, Rs, and R¢ and capacitor C2 constitutes a noninverting amplifier. The two MOSFETs are a complementary common-source output stage, like the output stage for the circuit discussed in Section 19-7.

Chapter 19

Power Amplifiers

859

Ri

—O

— VEE

- Ver

(b) Op-amp

(a) Basic circuit of common-source

amplifier

output stage controls

Ves3 and Vegas

Figure 19-45 Complementary common-source power amplifier using an opamp driver stage and a MOSFET output stage.

The gate-source bias voltages for Q3 and Q, are provided by the voltage

drops across resistors R7 and Rs, which are in series with the op-amp supply

terminals. So the op-amp supply currents (Isi+) and Isi-)) determine the levels of Voes3 and

Vesa:

Ves3

and

= Is¢+)

xX Rz

(19-23)

Vesa = Is(-) X Rg

(19-24)

Suitable gate-source threshold voltages (Vestn) to bias the output transistors for class AB operation, and typical op-amp supply currents (Is) can be determined from the device data sheets. Figure 19-45b shows that the op-amp supply currents are largely the collector currents in the op-amp output stage BJTs (Qs and Qe). Thus, R7 and Rs are collector resistors for Qs and Qs. When the base voltage for Qs and Q, is in-

creased in a positive direction, Qs collector current (Is,.)) increases, causing Vcs3 to increase and thus increasing the MOSFET drain current Ip3. At the same time, the Q, collector current (Is-)) decreases, reducing Vggy and drain current Ips. The resulting Ip3 flows through R,, producing a positive output voltage swing (+V,). Note that the op-amp output voltage is also positive at this time.

When

the base voltage at Qs and Qs is negative-going, Ig;_) increases,

causing an increase in Vgsa and in Ip4. During this time, Is;+) decreases, re-

ducing Voss and Ip3. Thus, Ips flows through R,, producing a negative output voltage swing (—V.). The op-amp output voltage is also going negative while Q, is creating the negative output voltage across R,.

860

Electronic Devices and Circuits

It is seen that BJTs Qs and Q, operate as common-emitter amplifier and that MOSFETs Q3 and Q, function as common-source circuits. Both produce voltage gain, which should. be multiplied with the op-amp loop gain to determine the total open-loop gain for the circuit. If typical tities are used, the overall open-loop gain can be shown to be around 4

stages stages openquanx 10°.

Returning to Fig. 19-45a, the complete (basic) circuit operates as a non-

inverting amplifier with a closed-loop voltage gain:

Aq. = —

(19-25)

Example 19-18 Determine the MOSFET gate-source bias voltages for the complementary common-source power amplifier in Fig. 19-46. Calculate the peak output voltage, peak output current, and output power if the ac input is +100 m’V. es Vec

O15

V

-15V —Vep

Figure 19-46 Power amplifier circuit for Ex. 19-18.

Solution From the LF351 op-amp data sheet:

Supply current:

Is =1.8mAto3.4mA

Ves3 = Vesa = Is X R7 Vos(min) = Is(min) X R7 = 1.8 mA

X 820 O

215V

Vostmax) = Istmax) X Ry = 3.4 mA X 820 0 2.9 V

Eq. 19-25:

Act _ Rst+ Re _ 3900 + 18kO Rs

~ 47.2

390 O

Chapter 19

Power Amplifiers

861

Vp = Act, X V; = 47.2 X 100 mV =472V

Vplp — 4.72V x 472mA =

T

EEE

=

P,=-—

Bias Control As previously explained, the bias current in the output transistors of a power amplifier should be adjustable. Control over the bias current flowing in transistor Q3 in Fig. 19-47a can be effected by using a variable resistor for R7, as illustrated. This allows Ip3 to be adjusted by varying Voss. When Ip3 is increased and the additional drain current flows through Ri, the dc feedback

(via Re in Fig. 19-46) keeps the V, equal to zero. The feedback produces the necessary change in Vesa to make Ip, closely follow Ip3. Thus, adjustment of resistor R7 controls the level of Ins as well as Ips.

A disadvantage of using R7 to adjust the bias current is that the voltage gains produced by Qs and Qs become unequal when Rz and Rg have different

resistances. This can be overcome by the negative feedback; however, the bias resistors can be kept equal by using the variable current source shown in

Fig. 19-47b. In the variable current source, transistor Q; is biased from the emitter of Q>, and the Q, base is connected to the collector of Q;. The collector-emitter

voltage of Q; is Vce1 = Ver + Vee2 = 2V pe Assuming that Ipz < Ici, the Q, collector current is

_ Vec ~ 2 Ver

Ri

fe =

(19-26)

With Ip;

Vy Ry

_

Vrpion))

Maximum undistorted output

-

Rg

jv

=

(Vez — Vrpon))

—O —Vip

(b) Voltage divider Ry and Ryo allows the output swing to go to +(Vee - Verpwon))

Figure 19-49

The common-source amplifier circuit can be modified to produce an out-

put swing larger than the op-amp maximum output.

Chapter 19

Power Amplifiers

865

Rg and Ro also provide negative feedback that controls the gain of the stage made

up of the op-amp

output BJTs and the common-source

MOS-

FETs. This is illustrated in Fig. 19-50. A further function of Ro and Rig is that

they can be selected to limit the op-amp output current in the event that R is short-circuited.

Feedback voltage

Figure 19-50

Negative feedback to the emit-

ters of Qs and Qg controls the gain of the

O-Ver

(Qs — Qe) — (Q3 — Qa) stage.

Example 19-20 The circuit in Fig. 19-51 has MOSFETs with gs, = 2.5 S and Rpwon) = 0.5 ©.

Determine the maximum peak output voltage, the minimum supply voltage at op-amp terminals, and the op-amp peak output voltage when the circuit is producing maximum output power. 4

t Vcc

“© aV Ry 820 0

— Qs Is

2mA

|!

Ryo Ay

4

S-

{} 2mA

Hol

Rg

1kQ

Ry

1kQ

109 aa (Fe

"=

Rg 820 2

—Ver -12V

Figure 19-51

Circuit for Ex. 19-20.

866

Electronic Devices and Circuits

Solution

Eg.19-31:

V

Vec

X Ry,

_

P Rowen + RL

12V

x

100

052+100

= 11.43V

7 =e 2 14sV PRL

100

=114A Eq. 19-29:

Ip

114A

AVgs = _ =e = 0.46 V

Verdc) = Is X Ry = 2 mA X 8200 =1.64V Eq. 19-30:

Vsqniny = +(Vcc — Verde) — AVos) = +(12 V — 1.64 V — 0.46 V) =+9.9V

The op-amp peak output voltage is

_VpX Ro

11.43 V X 1kO

Ro +R

1k0+1kO

Complete Amplifier Circuit The complete circuit of the common-source power amplifier is shown in Fig. 19-52. Note the inclusion of resistors Ry, and Riz and capacitors C3 and C4. Resistors Ry, and Riz are typically 100 0. They have no effect on the circuit dc conditions, but they help to reduce the possibility of oscillations in the

output stage. The additional stage of voltage gain constituted by the MOSFETs and the op-amp (common-emitter) output transistors increases the pos-

sibility of circuit instability. Capacitor C3 helps to ensure frequency stability by acting with resistor Ro to introduce a phase lead in the output stage feedback loop (see Section 15-2). The phase lead cancels some of the phase lag in the overall circuit. The additional stage of amplification extends the high cutoff frequency of

the amplifier above the cutoff frequency of the op-amp operating alone. If the op-amp (full-power) upper cutoff frequency for an overall voltage gain of 20 (or 26 dB) is 200 kHz, and the additional stage has a gain of 2 (or 6 dB), the circuit cutoff frequency is 400 kHz. For audio applications, it is normal to in-

clude capacitor C, (see Fig. 19-52), which is usually selected to set the amplifier upper cutoff frequency around 50 kHz or lower.

Chapter 19

Power Amplifiers

867

~—0 +Vec

Figure 19-52

Complete circuit of class AB common-source power amplifier.

Example 19-21 Analyze the circuit in Fig. 19-53 to determine the op-amp minimum supply voltage (Vs(dcimin)) and the MOSFET maximum gate-source voltage

(Ves(max)). The op-amp supply current is 0.5 mA. +Vecc

2 BY Ry

15kO Ry 1009

\IEXQ

5

sf

C3

Rg 1000 15kO Common-source power amplifier circuit for Figure 19-53 Examples 19-21 and 19-22.

868

Electronic Devices and Circuits

Solution From Eq. 19-27,

V, Ic2¢max) = RB

0.7 V = 700

~1.5mA Icoqmin) =

VBE. R, +R;

ca : 47004+1k0

= 476 pA Eg. 19-28:

Vos max) = Us(max) + Ic2qnax)] R7 = (0.5 mA

+ 1.5 mA)

X 15kQ

=3V Vs(dey(min) = (Vcc — Vr7) = +(15 V — 3 V) =+12V Example 19-22 Analyze the circuit in Fig. 19-53 to determine Poimax, Act, fi, and fy. The

op-amp supply current is 0.5 mA, and the MOSFETs have Rpjon) = 0.3 ©. Solution Power output:

Eq. 19-31:

_ Vcc X Ry "Ro ah

_ 15V x 150 ~~ 030+150 =14.7V Vp _147V

RR 150 = 980 mA Volp Pounax)

=

2

14.7V xX 980mA =

9

=7.2W Voltage gain:

Ay

_ Rs t+Ro _ 2.2kO + 33k0 Rs 2.2 kO = 16

Chapter 19

Power Amplifiers

869

Cutoff frequencies:

f-—1_InCoRg

1 27 X 3.9 pF X 2.2kO

= 18.5 Hz

fr

1 ~

27C4Re

1 ~

In

X 100 pF X 33kQ

= 48.2 kHz

Practice Problems 19-9.1 A complementary common-source power amplifier is to deliver 5 W to a 12 © load. The available MOSFETs have Rpn) = 0.6 2, Vin = 1.2 V,

and gf, = 3S. The op-amp to be used has 1 mA supply currents and a

maximum output of 20 mA. Design the output stage of the circuit as shown in Fig. 19-51. 19-9.2 Design a BJT current source bias control circuit for the amplifier in Problem 19-9.1 to adjust the Ves of Q3 and Qs by +20%.

19-9.3 The amplifier in Problem 19-9.1 is to have fj = 20 Hz and f. = 40 kHz. If the ac input is +600 mV, determine suitable values for Ry, Rs, Re, C1, Co, and C4 (see Fig. 19-52). Use a BIFET op-amp.

19-10

INTEGRATED

CIRCUIT POWER AMPLIFIERS

IC Power Amplifier Driver The LM391 integrated circuit audio power driver contains amplification ver stages for controlling an externally connected class AB output stage ing 10 W to 100 W. The voltage gain and bandwidth are set by additional nents. Internal circuitry is included for overload and thermal protection

and dridelivercompoand for

protection of the (externally connected) amplifier output transistors. The circuit is designed for very low distortion, so that it can be used for high-fidelity amplifiers. Figure 19-54 illustrates the use of the device as an audio amplifier. The output stage in Fig. 19-54 is seen to be a complementary emitter fol-

lower with the low-power and high-power

transistor pairs connected

in

quasi-complementary form. The IC output at terminal 9 is connected to the amplifier output, and the output stage transistors are controlled from current

source terminal 8 and current sink terminal 5. The circuit uses a plus-minus supply, and the non-inverting input terminal of the IC is biased to ground.

The inverting input terminal receives feedback from the output, so that the complete circuit operates as a non-inverting amplifier. Resistors Ra and Kp are connected to an internal transistor (via terminals 5, 6, and 7) to constitute a Vee multiplier for controlling the bias voltage to the

870

Electronic Devices and Circuits

amplifier output stage (see Fig. 19-55a). Capacitor Cap by-passes the Vpz multiplier circuit to improve the amplifier high-frequency response. Capaci-

tor Cr helps to reject power supply ripple, and Cc is a compensation capaci-

tor for frequency stability. Components Ro, Co, Lxand R, are included for load compensation (see Section 19-5).

The LM3391 has an internal transistor that can shut the circuit down when turned on by a thermal switch (Fig. 19-55b). This allows the device to be pro-

LM391 14 33 kO Thermal

switch (a) Vgp multiplier Figure 19-55

20 WF T

(b) Thermal shut-down

Bias control and shut-down circuits for the LM391.

(c) Soft turn-on

Chapter 19

Power Amplifiers

874

tected from the overheating that might occur with an excessive load current demand. This same transistor can be employed for soft turn-on of the circuit (Fig. 19-55c). If the amplifier supply voltage is switched on at the instant that

a peak input signal is applied, a high-level output is passed to the speaker, causing a sharp unpleasant noise. Soft turn-on causes the output to increase

slowly, thus eliminating the speaker noise. The circuit in Fig. 19-55c holds the amplifier in a shut-down condition until the capacitor charges. Overload protection transistors are included

in the LM391, as shown in Fig. 19-56. These transistors turn on when excessive voltage drops occur across the emitter resistors (Rp3 and Regs) in

the output stage (see Section 19-5). The output stage components in Fig. 19-54 are selected in the same way as for other directcoupled class AB amplifiers. The minimum supply voltages are calculated by adding 5 V to the peak output voltage.

Vec = +(Vp + 5V)

(19-32)

The input resistance at terminal

LM391

1 of the

is extremely high and so the circuit

input resistance is set by resistor Rin, which is

typically selected as 100 kQ. Feedback resistors Rr and Rp set the amplifier closed-loop voltage

gain. The

feedback network components

are

determined in exactly the same way as for

Figure 19-56

Overload pro-

tection for the LM391.

other feedback amplifiers. Rr is made equal to Rin to minimize output offset, and Ry is calculated from Rp to give the desired voltage gain. Capacitor C; is determined in terms of Ry, to set the low

cutoff frequency.

Example 19-23 Determine the maximum output power, the voltage gain, and the low cutoff frequency for the circuit shown in Fig. 19-54, if the supply is +23 V. Solution From Eq. 19-32,

Vp = Vcc — 5V=2V=5V =18V

> = Vp _ (sv)? °

2R,

2x80

872

Electronic Devices and Circuits

Rg

Ac =

+ Re

_

100 kQ

RS

+ 5.6kO

5.6ka = 18.9

Bt fi = QnC;Ry 2X

1 a7 X 1 pF X 5.6k0

= 28 Hz

250 mW IC Power Amplifier The LM386 is a complete power amplifier circuit capable of delivering 250 mW to an 8 © load without any additional components. The supply

voltage range is 5 V to 18 V, and the (inverting and non-inverting) input terminals are biased to ground or to a negative supply via internal 50 kO resistors. The output is automatically centred at half the supply voltage. Feedback resistors are also provided internally to set the voltage gain to 20. The pin connections for the LM386 are shown in Fig. 19-57a, and the circuit

connections for functioning as an amplifier with a gain of 20 are illustrated in

part b. Figure 19-57c shows how a capacitor and resistor can be connected at pins 1 and 8

to achieve a larger voltage gain. With the 10 wF capacitor alone,

a maximum gain of 200 is obtained. The resistor in series with the capacitor allows the voltage gain to be set anywhere between 20 and 200.

(b) Amplifier with Ac, = 20

(a) LM386 pin connections

Vcc

10pF

12k

(c) Amplifier with Ac, = 50 Figure 19-57 The LM386 IC power amplifier can be connected to have a closed-loop gain from 20 to 200.

Chapter 19

Power Amplifiers

873

single-ended

(SE),

Bridge-Tied Load Amplifier All

the power

amplifiers

already

discussed

have

been

meaning that they provide power to a load that has one terminal grounded

and the other terminal connected to the amplifier output. These amplifiers either use a plus-minus supply with directly-coupled loads or have a capacitorcoupled load and a single-polarity supply. A bridge-tied load (BTL) amplifier uses a single-polarity supply and a direct-coupled load. Figure 19-58a shows the basic circuit of a BTL amplifier. The two op-amps

are connected to function as inverting amplifiers, but note from the resistor values that A; has a voltage gain of 10 and that Az has a gain of 1. Each am-

plifier has a single-polarity supply (Vcc), and a voltage divider (Rs and Re) provides a bias voltage of 0.5Vcc to the op-amp non-inverting input terminals. The load resistor (R1) is connected from the output of A, to the output

of Ao. This is the bridge-tied load configuration. Amplifier A,

Amplifier A»

Ry

100 kQ

10kO

+Vec

Gy

%F-WA+Vec

ok

22 V

-

Y

Rs 100 kO.

Rot 100 kQ

+1V

+21V

10k

9

Yy

tL

~

+11V

Led V l

5

20 V Vo 20 V

ae (a) BTL amplifier circuit

Figure 19-58

ileal

R,

22V

x ph —$WWv— '

10 kQO

+1V

+21 V

x

+Vce

22V

Ry

Y; |

Ry

(b) Circuit waveforms

A bridge-tied load (BTL) amplifier uses two op-amp Circuits with their out-

puts connected to opposite ends of the load.

When no ac signal is applied, the de voltage at the load terminals (X and Y) is

0.5 Vcc, in this case, 11 V for a 22 V supply. As illustrated by the waveforms in Fig. 19-58b, a +1 V ac input to Ai produces a —10 V change at load terminal X. This (—10 V) is also applied to the input of A», resulting ina +10 V change at load terminal Y. Thus, a peak of 20 V, negative at X and positive at Y, is developed across the load. When the ac input goes to —1 V, a 20 V peak load voltage

is again produced but with the load polarity reversed. So, although a singlepolarity +22 V supply is used, the output is 40 V peak-to-peak, and no load-coupling capacitor is required. A (similar performance) single-ended amplifier producing a 40 V peak-to-peak output would require either a +22 V supply for a direct-coupled load ora +44.V supply for a capacitor-coupled load.

874

Electronic Devices and Circuits

Figure 19-59 shows the pin connections and typical application of a TPA4861, 1 W integrated circuit BTL audio power amplifier. The load is connected across the two output terminals (5 and 8), external resistors R; and Rp

set the voltage gain, and the signal is coupled to R; via C;. The supply volt-

age (Vpp) is internally divided to bias the op-amp non-inverting terminals to 0.5Vpp. The bias point is externally accessible so that it can be bypassed

to

ground (via Cg) for soft start-up and to minimize noise. A TPA4861 using a +5 V supply can dissipate 1 W in an 8 ( load. The overall voltage gain for the (BTL) amplifier is twice the gain of the inverting

amplifier stage: Act,

_2Ry

(19-33)

m

Because the signal is applied to an inverting amplifier, the input resistance is set by resistor R;. The IC manufacturer recommends that R; should be selected in the range of 5 kO to 20 kQ. Also, if Rp exceeds 50 kQ,, a small capacitor (Cp = 5 pF) should be connected in parallel with it for ac stability. The input capacitor (C1) sets the circuit low cutoff frequency. So, Xc, = Ry at fy

(19-34)

The internal voltage-divider resistance (50 kQ||50 kQ) is connected in series with the bypass capacitor (Cg). The impedance of Cg should usually be onetenth of the series resistance: XcB

=

2.5kQ

at fi

(19-35)

|e, 15kQ ww "4 a — 50kQ | 50k0 4 sHw—+4 a eels fl

6

1

5.6kO

pa SEN

|

3

ate

46 kQ.

WV

ne

80

—VWA\—

a

46 kO,

Speaker

—+

1

fc, Figure 19-59

V

TPA4861 bridge-tied load IC amplifier.

8

Bias

control.

Z

|

|

Chapter 19

Audio Power Amplifiers

875

Example 19-24 Analyze the circuit in Fig. 19-59 to determine the load power dissipation when a +0.5 V signal is applied at the input. Solution

15k Ac. = 2ReRy = 2X5.6k0,

Eq, 19-33;

Z5A

Vo = Aci X Vs = £5.4 X 0.5V =12.7V

i Vp _ @7vP ©

2R;

2X80

=~ 0.46 W

7 W IC Power Amplifier The LM383 can deliver 7 W to a 4 2 load. No additional output transistors are required because the amplifier can produce a 3.5 A peak output current.

Ae

Overload protection circuitry is included, and internal bias is provided for

(a) LM383 five-lead TO-220 package Figure 19-60

(b) Connection for amplifier with Pg = 7 W

LM383 IC power amplifier connected to dissipate 7 W in a 4 Q load.

876

Electronic Devices and Circuits

the input terminals. The single-polarity supply voltage ranges from 5 V to 20 V. Amplifier voltage gain can be programmed by means of external components. The circuit bandwidth is 30 kHz at a gain of 40 dB. Figure 19-60 shows an LM383

(in a 5-pin TO-220 package) connected to

function as a non-inverting audio amplifier. Capacitors C; and C4 couple the

signal and load. Resistors R, and R» are feedback components that set the circuit voltage gain, and capacitor C2 couples the feedback voltage to the inverting input terminal. Other components provide circuit stability. Note that

the resistance of Rp is 2.2 0. This is because the inverting input terminal is connected

(internally)

to a transistor emitter terminal

that has

an input

resistance of about 20 ©. Capacitor Cz must be very large to couple the feedback voltage to the low-resistance inverting input. The circuit functions as a non-inverting amplifier.

68 W IC Power Amplifier Figure 19-61 shows a power amplifier circuit using an LM3886 IC audio amplifier. The LM3886 can deliver 68 W to a 4 2 load using a +28 V supply. Alternatively, it can be used to dissipate 38 W in an 8 2 load, again using a +28 V supply. The circuit operates as a non-inverting amplifier with the

closed-loop gain set by resistors R3 and R4 and the low cutoff frequency set by capacitor C;. Potentiometer R; allows the signal amplitude to be adjusted.

Switch S; is a mute control.

t +Vcc

T Ni45

Laseas!8

LM3886

R3

rs

20Ryka

Cy 10 pF

Figure 19-61

M3886, 68 W audio power amplifier.

L, 0.7 pH

WW

R, 109

Chapter 19

Audio Power Amplifiers

877

Practice Problems 19-10.1 A power amplifier using an LM391 driver (as in Fig. 19-54) has a

+20 V supply, a 50 © load, and power Darlington output BJTs with hge = 600. Calculate the maximum output power and the peak output current from the integrated circuit. 19-10.2

Calculate the efficiency of the circuit in Fig. 19-59 when delivering

1 W to the speaker. The quiescent current for the TPA4861 is speci-

fied as 2.5 mA. 19-10.3

Determine the signal amplitude for the circuit in Fig. 19-60 to dissipate 7 W in the load. Calculate the low cutoff frequency.

19-11 CLASS C AMPLIFIER Class C Circuit and Waveforms In the basic class C amplifier circuit shown in Fig. 19-62a the BJT base is biased to a negative voltage level (— Vg) via inductor L) to keep the device in _a normally off state. The circuit waveforms in Fig. 19-62b show that Qi conducts when the signal voltage (v,) becomes sufficiently positive to drive ¥ SNE

po Vec :

I

L

L

‘

, ¥,

iH

—-

C,

4

(a) Class C power amplifier circuit

(b) Circuit waveforms

Figure 19-62 Basic class C amplifier circuit and waveforms. Tank circuit components C2 off.and pulsed on briefly and L» resonate at the signal frequency. Transistor Q, is biased

tank circuit. during each signal time period to recharge the

878

Electronic Devices and Circuits

the transistor base above the level of the grounded emitter terminal. The base

and collector currents flow only during a portion of the entire cycle of the signal waveform. The tank circuit (LzC2) connected to the collector is tuned to

resonate at the signal frequency, and because the waveform across a resonant circuit is sinusoidal, the circuit output voltage (vo) is a sine wave despite the

pulsed condition of the transistor.

Some of the energy stored in the tank circuit is dissipated in the load, and is replaced by the current pulse each time the transistor switches on. The process is sometimes referred to as the flywheel effect. A flywheel that gets a kick to keep it turning once in every cycle will rotate indefinitely. Similarly, a tank circuit that receives a (large enough) current pulse once a cycle will oscillate indefinitely. The tank circuit can be tuned to resonate at a harmonic of the signal frequency, instead of being tuned to the fundamental frequency. In this case, the output frequency is the selected harmonic frequency, and the circuit functions as a frequency multiplier. The circuit peak-to-peak output voltage (vp) is shown as 2Vcc in Fig. 19-62b. This effect (also discussed in Section 12-10) is due to the inductor opposing

any change in current flow. Figure 19-63a shows that when Q; is saturated, the voltage across Lz and C) is

Vp = Voc — Vee¢at) The polatrity of V, is positive (+) at the top of Lz and negative (—) at the bottom. When Q,; is off, as in Fig. 19-63b, the inductor voltage reverses to keep I, flowing, and V, is now: negative (—) at the top of Lz and positive (+) at the bottom. (The presence of C2 in parallel with Lz prevents any sudden

switch in the inductor voltage polarity.) So, the circuit peak-to-peak output +

ot Vic

———9+Vic we

V,

=

Voc

reversed polarity ~ Vegat)

Voc +V, ¥2V,

(a)Q, onin saturation

(b) QO, off

Figure 19-63 When Q; is on, the output voltage is —V, = (Voc — Veejeat)). When Q; switches off, the output oscillates up to +V, = (Vcc — Vce(say). This gives a peak-to-peak output amplitude of approximately 2Vec.

Chapter 19

Audio Power Amplifiers

879

voltage is 2V,. However, because Vcxisat) is very much smaller than Vcc,

Vovp-p) is taken as approximately 2Vcc. This also means that the BJT collectoremitter voltage can approach 2Vcc.

The output voltage amplitude from a class C circuit is not linearly related to the input amplitude, so the circuit cannot be employed as a linear amplifier. A class C circuit is normally used to amplify a high-frequency signal to the maximum possible output amplitude. Inductor L; in Fig. 19-62a has a high impedance at the signal frequency. This avoids loading the signal source, and isolates the bias voltage source from signal frequency currents. The winding resistance of L; is likely to be less than 20 ©, so the dc bias at the QQ; base is securely held at — Vz.

Efficiency When no signal is applied to a class C amplifier, the transistor is off. Also, when on, the device is driven into saturation and conducts only for a portion of the positive half-cycle of the signal waveform. Thus, the transistor power dissipation is a minimum, and the only other wasted power is a very smal] power dissipation in the inductor winding resistance. This gives the class C amplifier a very high efficiency. The maximum ac power delivered to the load is, P, =

giving

Po =

(Vins)

Rk

_ (V, / V2)’

&

(Vp 2R,

(19-36)

The dc voltage applied to the tank circuit when Q; is on is Vp, as already discussed. If this voltage was applied continuously to deliver P, to the tank circuit, the average direct current would be

The dc input power can be calculated from

P; = Voc X lac and the circuit efficiency is (from Eq. 19.4)

n= Fo x 100% P.

1

To determine the peak current supplied by the transistor, consider the pulse waveform illustrated in Fig. 19-64. This is represented as having a rec-

tangular wave shape for calculation simplicity. To produce the average current I4,a pulse amplitude of

880

Electronic Devices and Circuits

T lp = Igo X

7

(19-37)

is required where T is the time period of the signal frequency and ft is the device on time. The transistor on time can also be expressed as a conduction angle (8): t

6= — X 360°

(19-38)

=

Figure 19-64 Approximate representation of the repetitive current pulse that charges the tank circuit in a class

T

C amplifier.

The power that must be supplied to the tank circuit equals the output

power (Po), which can be expressed as

Py = (Ip X Vp) X 7

(19-39)

Example 19-25 The basic class C amplifier circuit in Fig. 19-65 has Vcc = 10 V, Ry = 1 kQ, f=3MHz, Ip = 25 mA, Vexat) = 0.3 V. Calculate the ac output power, dc input

power, conduction angle, and efficiency. t+Vec

10V C,

28 nH

=

L

2

1000 pF

~

= =

Figure 19-65 Class C amplifier circuit analyzed in Ex. 19-25.

Solution Vp= Vec — Ver¢at) = 10 V — 0.3 V

=9.7V

Chapter 19

2

Eq. 19-36:

881

2

p,= “e) _ @7V) 2R,

Audio Power Amplifiers

2x1kO

=~ 47 mW

T= 1/f=1/(3 MHz) = 0.33 ps From Eq.

19-39:

_

F

x

_ 47 mW

[, XV,

x 0.33 [wS

25 mA

x 9.7 V

= 64 ns

Eq. 19-38:

oo tx 360° = OFS 300_ z

1/(3MHz)

=~ 70° P|

lac =

V,

47mW

a

«9.7V

=485mA P;=

Vec X Ige= 10 V

X 4.85 mA

= 48.5 mW EP

Eq. 19-4:

47 mW

= — x 100% =————-_ x 100%

.

a”

48.5 mW

= 96.9%

The calculation of efficiency in Ex. 19-9 does not take into account the power dissipated in the inductor. This can be determined from the inductor rms current (I,) and the winding resistance (Ry): V I

and

SS

0.707 V. P

Py = Ty? Rw

Bandwidth The equations relating to the bandwidth for the small-signal tuned amplifier (Eqs 12-30 through 12-35) also apply to the class C circuit. Recall that the

bandwidth is determined from Eq. a 12-35: where Q, is given by

f B= Q, =*

882

Electronic Devices and Circuits

Eq. 12-33:

Qp= FeriR o™p

Remember that Eq. 12-33 is correct only when Q;, >> Qp.

Component Selection The transistor used in a class C amplifier must be able to survive 2Vcc, as discussed. It must also be able to provide the necessary pulse of collector current to the tank circuit, and its switching times must be much smaller than

the required on time (t). Because the transistor is off for most of the signal time period, the tank circuit in a class C amplifier operates as a power source for the load. So, the energy stored in the tank circuit should be many times the output energy provided to the load during each cycle. If the components are too small, the

tank circuit will be incapable of supplying the required output power. The inductance and capacitance values can be determined in terms of the energy stored. However, suitable values can also be calculated by simply selecting

the impedance of L and C as very much smaller than the load resistance. Example 19-26 demonstrates this.

Example 19-26 The class C amplifier in Fig. 19-66 has a 1 MHz signal frequency. Determine suitable tank circuit component values. Also, calculate the required transistor peak current if the conduction angle is 100°. Assume Vcr (at) = 0.5 V. ot Vec 30 V

Figure 19-66 Class C 19-26 and 19-27.

Solution Xc= XL

K

‘Cathode 6 K

(a) SCR 4-layer construction

Figure 20-1

OK

(b) SCR circuit

(c) Two-transistor

symbol

construction

(d) Two-transistor equivalent circuit

The silicon-controlled rectifier (SCR) is a four-layer device that can be

explained in terms of a two-transistor equivalent circuit.

Chapter 20

Thyristors

895

possible to think of pi, Ma, Poa as a pnp transistor, and 1p, P2b, M2 as an npn

transistor. Replacing the transistor block representations in Fig. 20-lc with the pnp and npn BJT circuit symbols gives the two-transistor equivalent circuit in Fig. 20-1d. It is seen that the Q, collector is connected to the Q2 base, and

the Q» collector is commoned with the Q; base. The Q; emitter is the SCR anode terminal, the Q2 emitter is the cathode, and the junction of the Q;

collector and the Q> base is the SCR gate terminal. To forward-bias an SCR, a voltage (Vax) is applied positive on the anode (A) and negative on the cathode (K), as shown in Fig. 20-2a. If the gate (G) is

left unconnected, only small leakage currents (Ico) flow, and both transistors remain off. Figure 20-1a shows that the leakage currents are the result of junction Jz being reverse biased when A is positive and K is negative.

When

a negative gate-cathode voltage (—Vc) is applied, the Q2 base-

emitter junction is reverse biased, and only small leakage currents continue to flow, so both Q; and Q» remain off. A positive gate-cathode voltage

forward-biases the Q, base-emitter junction, causing a gate current (Ic = [p2) collector current (Ic). (See Fig. 20-2b.) Because Ic;

to flow and producing a Q

is the same as Ipi, Q; also switches on and Ic; starts to flow, providing base

current Ip. Each collector current provides much more base current than needed by the transistors, and even when Ic is switched off, the transistors remain on, conducting heavily with only a small anode-to-cathode voltage

drop. The ability of the removed is referred to as To switch the SCR on, switched on, the gate has

SCR to remain on when the triggering current is latching. only a brief pulse of gate current is required. Once no further control and the device remains on until

Vax is reduced to near zero.

+

y

of

Hie

Ico G om

7 Vax

7 Q

J K

(a) Leakage current when the gate is open-circuited

(b) Gate current triggers the SCR on

Figure 20-2 When the SCR gate current is zero, the device normally remains off. The flow of gate current (Ig) triggers the SCR on.

g96

Electronic Devices and Circuits

Consider Fig. 20-la again. With a forward (anode-to-cathode) bias, junctions J, and J3 are forward-biased, while Jz is reverse biased. When Vx is

made large enough, J2 will break down and the resulting current flow across the junction constitutes collector current in each transistor. Each collector

current flows into the base of the other transistor, causing both transistors to switch on. Thus, the SCR can be triggered on with the gate open-circuited.

SCR Characteristics and Parameters Figure 20-3a shows an SCR with a reverse-bias anode-to-cathode voltage (—Vax) (negative on A, positive on K). Note that the gate terminal is opencircuited. Figure 20-3b shows that the reverse bias voltage causes junction J> to be forward biased and J; and J3 to be reverse -biased. When — Vax is small, a reverse leakage current (Ipx) flows. This is plotted as the reverse characteristic

(—Vax versus Ip) on Fig. 20-3c. IRx is typically around 100 pA, and is sometimes referred to as the reverse blocking current. When —Vax is increased, Ipx remains approximately constant until the reverse breakdown voltage is reached. At this point the reverse-biased junctions (J; and J3) break down and the reverse current (Ip) increases very rapidly. If Ip is not limited (by additional circuit components), the device will

be destroyed by excessive current flow. The region of the reverse characteristics before breakdown is termed the reverse blocking region. An SCR with a forward-bias anode-to-cathode voltage (positive on A,

negative on K) is shown in Fig. 20-4a. Here again, the gate terminal is opencircuited. As illustrated in Fig. 20-4b, +Vax forward-biases J, and J3 and

reverse-biases J2. With low levels of +Vax, a small forward leakage current (Ipx) flows. This is actually the reverse leakage current at junction Jz, and so (like Ipx), it is typically around 100 pA. Also like Ipx, zx remains substantially Reverse breakdown

voltage AQ-

—Vax

““+— Jy forwardbiased

=|

.~—J3 reversebiased

(a) Reverse-bias

(b) Junction bias polarity

(c) SCR reverse characteristic

Figure 20-3. When Vax is negative, Jz is forward biased, and J, and Js are reverse biased. A small reverse leakage current flows while —Vax is less than the breakdown voltage.

Chapter 20

_—iThyristors

897

. Py

4:

ees)

mt; A

Gor

pr

+—J, forward-

|

+——

biased Jo reverse-

biased _~—J3 forward-

. No

y

biased

K

(a) Forward-bias

Figure 20-4

FX

VE Ko-

4

f

;

+

+Vax

=

G

+— +

_

|

—_(b) Junction bias polarity

Forward breakover voltage

(c) SCR forward characteristic

When Vax is positive, J. is reverse-biased and J, and Jz are forward-biased.

A small forward leakage current flows while +Vax is less than the forward breakover

voltage.

constant until +Vax is made large enough to cause (reverse biased) Jz to break down. The applied voltage at this point is termed the forward breakover voltage (Vp@o)). This is illustrated by the forward characteristics (Ip versus +Vax) in Fig. 20-4c. When Vygo) is reached, the component transistors (Q; and Q)) are immediately switched on into saturation as already explained, and the anode-to-cathode voltage falls rapidly to the

forward conduction voltage Vg. The device is now into the forward conduction region, and Ip must be limited to protect the SCR from excessive current levels. So far, the SCR forward characteristics have been discussed only for the case of Ig = 0. Now consider the effect of Ig levels greater than zero

(Fig. 20-5a). As already shown, when + Vax is less than Veo) and Ig is zero,

a small leakage current flows. This current is too small to have any effect on the level of +V,x that causes SCR switch on. When Ic is made just slightly larger than the junction leakage currents, it still has a negligible effect on the level of +Vx for switch-on. Now consider the opposite extreme. When Ic is made larger than the minimum base current required to switch Q, on, the SCR switches on when + Vax forward-biases the base-emitter junctions of Q; and Q» (Figs 20-5b and 20-6).

The complete forward characteristics for an SCR are shown in Fig. 20-6.

Note that when Ig = Ica, switch-on occurs with + Vax at a relatively low level (V4). Gate currents between Ico and Ica permit device switch on at voltages

greater than V4 and less than Vrgo). The region of the forward characteristics

g98

Electronic Devices and Circuits

(a) SCR with gate current Figure 20-5

(b) SCR voltage drops when on

A gate current (Ig) can cause the SCR to switch on at a low Vax level. Forward

conduction region

pee

eg

A

faa pad Soop eg

be

i

To

’

ese aa

|

ly Wy |

a

Forward blocking region

|

+Vax

—_—_—>

f

f |

v;

VE(Bo) Figure 20-6

Forward characteristics for an SCR. Higher levels of gate current (Ig) cause

the SCR to conduct at lower anode-to-cathode voltages (+Vax). before switch-on is known as the forward blocking region, and the region after switch-on is termed the forward conduction region, as illustrated. In the forward conduction region, the SCR behaves as a forward-biased rectifier. The forward (anode-to-cathode) voltage (Vp) when the device is on is

typically 1.7 V. To switch an SCR off, the forward current (Ip) must be reduced below the holding current (I;3) (see Fig. 20-6). The holding current is the minimum level of Iz that maintains SCR ‘conduction: If'a gate current greater than zero is maintained while the SCR is on, lower levels of holding current (I¢41, [y2, etc.)

are possible.

Chapter 20

__siThyristors

899

SCR Specification As in the case of most electronic devices, the SCR maximum

voltage and

current are important for any given application. The forward breakover voltage and reverse breakdown voltage have already been discussed. The maximum forward voltage that may be applied without causing the SCR to

conduct is termed the forward blocking voltage (Vprm). Similarly, the maximum reverse voltage that may be applied is the reverse blocking voltage (Vrrm)-

The maximum SCR current is variously specified as the average current (Iqcavy), the rms current (Iq¢amsy), and the peak non-repetitive surge current (Its). The first two of these need no explanation. The third is a relatively large

current that can normally be permitted to flow for a maximum of a half-cycle of a 60 Hz sine wave. The circuit fusing rating (/’t) is another parameter that defines the maximum non-repetitive forward current. This can be used to

calculate the maximum duration of a given forward current surge. In many circuit applications the SCR current is limited by a series-connected load, so

there is usually no need to consider surge-current levels, except in the case of capacitive loads. Some of the range of available SCRs is illustrated by the partial specifications and packages shown in Fig. 20-7. With 800 mA rms current and 2N5060

2N6396

30 V

200 V

960 V

0.8A

12A

35 A

Forward on voltage (Vm)

1.7V

L7'V

2V

Holding current (I) Gate trigger current (Icr)

5mA 200 pA

6mA 12mA

100 mA 6mA

0.8 V

0.9 V

3V

5V

5V

5V

' Peak forward and reverse voltage

C35N

- (Vprm and Ver) “Maximum rms current (It(Rms))

Gate trigger voltage (Vcr) Gate reverse voltage (Vcrm)

2N6396 (TO-220)

2N5060 (TO-92)

Figure 20-7

Partial specifications and packages for three SCRs for different voltage and

current levels.

gG0

Electronic Devices and Circuits

30 V forward and reverse blocking voltage, the 2N5060 is a relatively low-

current, low-voltage device. This is packaged in the typical plastic TO-92 transistor-type enclosure. Note that the peak reverse gate voltage (VcrM) is 5 V. The 2N6396 SCR is capable of handling a maximum rms current of 12 A, and has forward and reverse blocking voltage of 200 V. The package is a TO-220 plastic enclosure with a metal tab for mounting on a heat sink. For the C35N, the peak forward and reverse voltage is 960 V, and maximum rms current is

35 A. The device package is designed for bolt-mounting to a heat sink.

Section 20-1 Review 20-1. 1 Sketch the four-layer construction of an SCR and the two-transistor equivalent circuit. Explain the device operation. 20-1.2 Sketch SCR forward and reverse characteristics. Briefly explain.

20-2

SCR CONTROL CIRCUITS

Pulse Control The simplest of SCR control circuits is shown in Fig. 20-8a. If SCR; were an ordinary rectifier, the ac supply voltage would be half-wave-rectified and only the positive half-cycles would appear across the load (R,). The same would be true if the SCR gate had a continuous bias voltage to keep it on when the anode-cathode voltage goes positive. A trigger pulse applied to the gate can switch the device on at any time during the positive half-cycle of the supply voltage. The SCR continues to conduct during the rest of the positive half-cycle, and then it switches off when the instantaneous level of the supply approaches zero. The resulting load waveform is a portion of the positive half-cycle starting at the instant that the SCR is triggered (Fig. 20-8b).

| | )

even

Trigger pulse

| |

|

I

| _ Load waveform

|

| ihe

Trigger | |

on

Vo

pulse

off

jon

lake Fe eon

angle (a) SCR pulse control circuit Figure 20-8

(b) Circuit waveforms

An SCR can be triggered on by a pulse applied to the gate. Once triggered,

the device remains on until the load current falls below the holding current.

Chapter 20‘

Resistor Rg holds the gate-cathode voltage at zero when no trigger input is present. Load

waveforms

being switched

that result from

0° 90°180°

Thyristors

901

—0”_-90°180°

rrr ott tt

the SCR

on at different points

in the

positive half-cycle of the supply voltage are shown in Fig. 20-9. It is seen that the average load

current

is

determined

by

the

SCR

conduction angle. Thus, the load power dissipation can be varied by adjusting the SCR switch-on point. It should be noted that the

ee

ee

SCR cannot be triggered precisely at the 0° Ns rneili 5th thea y controlling point in the waveform because the anode-toconduction angle. cathode voltage must be at least equal to the forward on voltage (V7) for the device. Also, the SCR will switch off before the 180° point when the load current falls below the holding current. The instantaneous level of the load voltage is the instantaneous supply

voltage (és) minus the SCR forward voltage (V7): Vi

= Ge =

Vu

(20-1)

The load current (I,) can be calculated from V;, and R,, and the SCR anode current (Ia) is, of course, the same as the load current. At the instant of triggering, the device cathode current (Ix) is actually the sum of the gate current (Ic) and the anode current. However, Ic is very much smaller than Ia, so the SCR anode and cathode currents can be assumed to be the same quantity, just as in the case of a diode. The instantaneous supply voltage (¢.(0)) that causes the SCR to switch off

can be determined from Vry, Rt, and the holding current: eso) = Vim + UpRt)

(20-2)

For any given application, the SCR selected must have forward and reverse blocking voltages greater than the peak supply voltage. Its specified

maximum rms current must also be greater than the rms load current. When

designing the circuit, the gate current used should be at least three times the Ig specified for the device. Note that the required triggering current (I7) for

the circuit in Fig. 20-8 is the sum of Ig and the resistor current Ipc, as

illustrated.

go02

Electronic Devices and Circuits

Example 20-1 Select a suitable SCR for the circuit in Fig. 20-8a if the rms supply voltage is 24 V and the load resistance is 25 ©. Calculate the instantaneous supply voltage that causes the SCR to switch off.

Solution Peak supply voltage:

Vapk) = 1.414 X V, = 1.414 x 25V = 33.9 V SCR forward and reverse blocking voltage: Vprm & Vero > 33.9 V Reference to the partial specification for the 2N5060 to 2N5064 range of SCRs in Fig. 20-10 shows that the 2N5060 has Vprm = 30 V and the 2N5061 has Vprm = 60 V. So the 2N5060 would

not be suitable, whereas

the 2N5061

would seem to be a suitable device.

Vspk) — Vim

33.9V -1.7V

Tip) = Ri = 4.29.4 i ENED

~

te ANOS

ie

\

/2N5061 “-2N5062 ~

TD

I

" Maximum mms curren

OO

‘\Forward-on voltage Vand)

a ae

Holding current (In)

ae

ee a Figure 20-10

ST”.

agus)

2N5063. IN5004

200 V

lke oe

17V

ai

“5mA Pedecalbyers

For a half-wave rectified sinusoidal waveform,

So, the 2N5061 is a suitable SCR.

150 V

0.8A

Partial specification for 2N5060 to 2N5064 SCRs.

The 2N5061 has Iryms) = 0.8 A.

~

ee

BS

= 0.64A

60V 00'V

bo Bape

ae

Tams) = 0.5 Tip)

30 V

ont060 "|"

vee

7

25 0

= 0.5

129A

200 pA

Chapter 20

903

_‘Thyristors

Switch-off voltage:

From Eq. 20-2,

eso) = Vim + (In X Rt)

=17V+(5mA X25) 1.8V

90° Phase Control In the 90° phase-control circuit shown in Fig. 20-11, the gate triggering voltage is derived from the ac supply via resistors R,, R2, and R3. When the moving contact is set to the top of R2, the SCR can be triggered on almost immediately

at the beginning of the positive half-cycle of the input. When the moving contact is set to the bottom of R», the SCR might not switch on until the peak of the positive half-cycle. Between these two extremes, the device can be

switched on somewhere between the zero level and the peak of the positive half-cycle (between 0° and 90°). If the triggering voltage (Vr) is not large

enough to trigger the SCR at 90°, then the device will not trigger on at all, because Vr is greatest at the supply voltage peak and falls off past the peak. Diode D, in Fig. 20-11 is included in the circuit to protect the SCR gate from the negative voltage that would otherwise be applied to it during the negative half-cycle of the ac supply. The load for an SCR phase-control circuit could be a permanent magnet motor, so that the circuit controls the motor speed. Or the load may be a heater or a light, and in this case the circuit controls the heater temperature or the light intensity. The voltage divider (R; R R3) in Fig. 20-11 is designed in the usual way for

the required range of adjustment of Vr. The voltage-divider current (Ij) is selected much larger than the SCR gate current. The instantaneous triggering voltage at switch-on is , Vr

a

Vo1

2

Ve

(20-3)

ac voltage @ source

= (a) 90° phase-control circuit Figure 20-11

be

Control

Control

range

range

(b) Circuit waveforms

SCR 90° phase-control circuit. The SCR can be triggered on anywhere

between 0° and 90°.

g04

Electronic Devices and Circuits

Figure 20-12 shows a 90° phase-control circuit with its ac voltage source full-wave-rectified. This gives a larger maximum

power dissipation in the

load than a non-rectified source. Diode D; in Fig. 20-11 is not required in

Fig. 20-12 because the SCR gate does not become reverse-biased. Ry

SCR,

0°

90°

II

Ro

Z|T |

|

Ry

Ry

0° a

90°

!

|

yf

0°

mr ! | bw |

90° |

I \

a Control

| (a) 90° phase-control circuit with

range (b) Circuit waveforms

full-wave-rectified supply Figure 20-12

SCR 90° phase-control circuit with a full-wave-rectified supply.

In the circuit in Fig. 20-13a, the two SCRs are connected in inverse parallel and they operate independently as 90° phase-control circuits. SCR; controls the load current during the positive half-cycle of the supply voltage, and SCR, controls the current during the negative half-cycle. The triggering voltage for each SCR is set by the voltage divider network R; to Rg and adjusted by variable resistor R3. Diodes D; and D2 protect the gate terminals

of each SCR from excessive reverse voltage. During the supply voltage positive half-cycle, D2 is forward-biased and current flows through R2, Rs, and Ry. The voltage drop across Ry, triggers SCR; at the desired point in the positive half-cycle. When triggered, the SCR forward voltage switches to a low level and remains there until the instantaneous supply voltage approaches zero. During the supply negative half-cycle, D; is forward-biased to produce current flow through Ri, R2, and R3. With R, equal to Ry, the voltage drop across R; triggers SCR; at the same 0°

90°

180° 270° 360° |

voltage

(a) 90° full-wave phase-control circuit

Figure.20-13 SCRs.

(b) Load current waveform

90° full-wave phase-control circuit using two inverse-parallel connected

Chapter 20

point

in

the

negative

half-cycle

as

SCR;

in

the

Thyristors

positive

905

half-cycle.

The resulting 90° full-wave phase-controlled load waveform is shown in

Fig. 20-13b.

Example 20-2 The SCR in Fig. 20-14 is to be triggered on between 5° and 90° during the positive half-cycle of the 30 V supply. The gate triggering current and voltage

are 200 A and 0.8 V. Determine suitable resistance values for Ri, Rz, and Rs.

Ry 30 V Ay)

fh

SCR,

Ry

Figure 20-14

Rs

SCR 90° phase-control

circuit for Ex. 20-2.

Solution Peak supply voltage:

Veipk) = 1.414 X V, = 1.414 x 30 V =424V At5®,

es = Vek) Sin 5° = 42.4 V sin 5° =3.7V

At 90°, Eq.

20-3:

és = Vr

V s(pk) = 42.4V

= Vpi

+

Vg

= 0.7V

+ 0.8 V

=15V

To trigger at e, = 3.7 V, the Rz moving contact is at the top. So and

Vro + Vrx3 = Vr = 15 Vv Va

=@-

VrRa3s7V-15V

=22V Timin) =

Select

(Ig = 200 pA)

Timin) = 1 mA

906

Electronic Devices and Circuits

= 2.2 kO, (standard value)

Rp + Ry == = 190 1

1mA

= 15kO

To trigger at e, = 42.4 V, the R2 moving contact is at the bottom. So

Vre3 = Vr =15V

anil

i, =

é, R,

_

+ Ro

+ Rg

4A24V 2.2kQ0

4+ 1.5kO,

¥11.5mA

|

Vr

LSV

I;

11.5 mA

= 1300

(use 120 0 standard value)

Rp= (Ro + R3) — R3= 1.5kO — 120 © = 138k

(use 1.5 kO, standard value potentiometer)

Example 20-3 Analyze the circuit designed in Ex. 20-2 to determine the SCR anode-cathode

voltage at the instant of switch-on when the moving contact of potentiometer R is set to (a) its centre position and (b) its zero (bottom) position. Solution (a) With R2 contact at centre: ' The SCR will trigger when Vy = 1.5 V.

y= Vr (Rit Rp +Rs) _ 15 V2.2 kO+1.5k0 + 120 0) AK R3 + 0.5Ry 8700 =6.6V (a) With R2 contact at zero:

vy,

- Va (Ri+Ro+Rs) _ 1.5 V(2.2kO +1.5k0 + 120 0) = R, 1200 = 47.85 V

Because the peak supply voltage is 42.4 V, the SCR will not trigger with Rz at the zero position.

Chapter 20 0°

)

0°

| range ja

:

180°

‘Control |

| Control

SCR, R

180°

907

Thyristors

!

range |

|

voltage source

(b) Circuit waveforms

(a) 180° phase-control circuit

Figure 20-15

SCR 180° phase-control circuit. R; adjustment allows the SCR triggering

point to be set anywhere between 0° and 180” in the positive half-cycle of the ac supply

voltage.

180° Phase Control In the circuit shown in Fig. 20-15, resistor R, and capacitor C; determine the point in the supply voltage cycle where the SCR switches on. During the negative half-cycle of the supply, C; is charged via diode D; to the negative

peak of the supply voltage. When the negative peak is passed, Dj is reversebiased because its anode (connected to C;) is more negative than its cathode. With D; reversed, C; begins to discharge via R;. While C; voltage remains

negative, D2 is reverse-biased and the gate voltage cannot go positive to trigger the SCR on. Depending on the values of C; and R;, the capacitor might

be completely discharged at the beginning of the positive half-cycle of the supply, allowing SCR, to switch on. Alternatively, C; might retain some negative charge past the end of positive half-cycle, keeping SCR; off. Resistor Ro is included in the circuit to restrict the level of the gate current.

Designing the 180° phase-control circuit can begin with selection of a capacitor much larger than stray capacitance. A maximum resistance for R; should then be calculated to discharge the capacitor voltage to zero during the time from the negative peak of the supply voltage to the 180°

point

in

the

positive

half-cycle.

The

capacitor voltage does not decrease linearly as Fig. 20-16 implies. However, the maximum resistance for R; can be most easily calculated

by assuming a linear discharge. The average value

of the discharging voltage

(E) is first

determined. Figure 20-16 shows that E is —0.636V 4px) for 0.25T, and +0.636Vs(pk) for 0.5T, which averages out to approximately 0.2V.(px) for the total discharge time of 0.75T.

Kigame 20-46 ‘Diech times and Sotteoe ate the circuit in Fig. 20-15.

on

908

Electronic Devices and Circuits

Now the equation for discharge of a capacitor to zero volts via a resistor may

be applied:

t = RC In [(E — Eo)/E] Substituting the appropriate quantities into the equation gives

Kw OEE PUT ERG

(20-4)

Practice Problems’ 20-2-1 ‘The 90° phase-control circuit in Fig. 20-11 has a 115 V, 60 Hz supply, arid Ry = 50'(. Specify the required SCR, and calculate suitable resiStor values for switch on between 7° and 90°.

20-2.2 The 180° phase-control circuit in Fig. 20-15 has a 50 V, 60 Hz supply, and the SCR has Ve.= 0.5 V and Ig= 100 pA. Determine suitable _ values for Ry and C. Calculate a resistance for R2 to limit the gate

current to a maximum of 50. mA. 20-3

MORE

SCR APPLICATIONS

SCR Circuit Stability: An SCR circuit is stable when it operates correctly, switching on and off only

at the desired instants. Unwanted triggering (also called false triggering) can be produced by noise voltages at the gate, transient voltages at the anode terminal, or very fast voltage changes at the anode (termed dv/dt triggering). Obviously, gate noise voltages may be large enough to forward-bias the gate-cathode junction and cause false triggering. Anode voltage transients (produced by other devices connected to the same ac supply) can exceed the SCR breakover voltage and thus trigger it into conduction. The dv/dt effect

occurs when the anode voltage changes instantaneously, such as when the supply is switched on at its peak voltage level. The SCR capacitance is charged very quickly, and the charging current is sufficient to trigger the device. Gate noise problems can be minimized by keeping the gate connecting

leads short and by the use of a gate bias resistor (Rg in Fig. 20-17a). This should be connected as closely as possible to the SCR gate-cathode terminals, because conductors connected between Rg and the device could pick up noise that may cause triggering. Biasing the gate negative with respect to the

cathode can also be effective in combating noise. Capacitor C; in Fig. 20-17b can be used to short-circuit gate noise voltages. C, also operates in conjunction with the anode-gate capacitance as a voltage divider that

Thyristors

Chapter 20

r)

10 kQ




0.1 wF

|

C | 0.1 LF

¥)

309

Cy

ge

i

r “S (a) Gate resistor

Figure 20-17

Ry = (b) Gate capacitor

Ry (c) Snubber circuit

Unwanted gate noise triggering can be prevented by Rg or C; at the gate-

cathode terminals. The use of a snubber circuit prevents triggering by transients at ihe anode terminal.

reduces the possibility of dv/dt triggering. C; is usually in the 0.01 LF to 0.1 pF range, a. d like Rg, it should be connected close to the SCR terminals.

An RC snubber circuit can be used to prevent triggering by anode terminal transients (Fig. 20-17c). A snubber is usually necessary for inductive loads

and may also be required for resistive loads. With an ac supply, there is a phase difference between an inductive load current and the supply voltage, and this can cause loss of SCR control. Also, the current through an inductor

with a de supply will not go to zero immediately when the SCR switches off. A snubber circuit is necessary in both cases.

Zero-Point Triggering When an SCR is switched on while the instantaneous level of the supply voltage is greater than zero, surge currents occur that generate electromagnetic interference (EMI). The EMI can interfere with other nearby circuits and equipment, and the switching transients can affect control of the SCR. Circuits can be designed to trigger an SCR on at the instant the ac supply is crossing the zero voltage point from the negative half-cycle to the positive half-cycle. This is called zero-point triggering, and it effectively eliminates the

EMI and the switching transients. The zero-point triggering circuit in Fig. 20-18a shows two inverse-parallel connected SCRs that each have RC triggering circuits: C, and R, for SCR, and Cy and R>2 for SCR2. SCR; is held off while switch S; is closed, and because

capacitor C2 is uncharged, SCR: remains off. With S; open, positive triggering current (Ic1) begins to flow when the supply voltage begins to go positive. As illustrated, Ig; flows via C; and R; to the gate of SCR),

triggering it into

conduction at the zero-crossing point. SCR; provides a path for (positive) load current (i, +).

910.

Electronic Devices and Circuits

circuit

(a) Zero-point —

. AD AD D DA NA CA WYODOODGUSGGSG \

GS

|

SCRs on S; open

|

1D »

» >

|Load waveform |

SCRs off 5S; closed

SCRs on S; open

SCRs off S, closed

(b) Circuit waveforms Figure 20-18

In.an SCR zero-point triggering circuit the devices

are switched on only when the supply waveform crosses the zero-voltage point.

With SCR; on, capacitor C2 charges (with the polarity shown) almost to the

peak of the supply voltage. When the supply voltage crosses zero from the positive half-cycle to the negative half-cycle, SCR; switches off. D; becomes reverse-biased,

and

the charge

on

C; provides

triggering

current

(Ic)

to

SCR2. Thus, SCR, is switched on at the start of the supply negative half-cycle, providing a path for (negative) load current (i,-). Both SCRs continue to switch on and off at the zero-crossing points while

S; remains open, and both stay off when S; is closed. SCR cannot switch on unless

SCR,

has

first been

on,

and

because

of this

the

arrangement

is

sometimes termed a master-slave circuit, SCR; being the master and SCR; the

slave. The waveforms in Fig. 20-18b show that power is supplied to the load for several cycles of the supply

while

S; is open,

dissipation occurs for several cycles while S; remains

and

no

closed.

load power The

switch

might be controlled by a temperature sensor or other device.

Crowbar Circuit A crowbar circuit (also known as an overvoltage protection circuit) is illustrated in Fig. 20-19. This circuit protects a sensitive load against an excessive dc

supply voltage. When the supply (Vs) is at its normal voltage level, it is too

Chapter 20

Thyristors

9114

Currentlimited

Load

sees source

Figure 20-19

An SCR crowbar

circuit (or overvoltage protection circuit) short-circuits the load when the supply voltage exceeds a pre-determined level.

—

low to cause the Zener diode (Dj) to conduct. Consequently, there is no current through the gate bias resistor (R;) and no voltage drop across R;. The gate voltage (Vg) remains equal to zero, and the SCR remains off. When

the

supply voltage exceeds Vz, D; conducts, and the resultant voltage drop across R; triggers the SCR into conduction. The voltage across the load is

now reduced to the SCR forward voltage drop. The voltage across Vz and R, is also reduced to the SCR forward voltage, and the dc voltage source is

short-circuited by the SCR. The voltage source must have a current-limiting circuit to protect the source and to minimize SCR power dissipation. The supply must be switched off for the SCR to cease conducting.

Example 20-4 The de voltage source in the SCR crowbar circuit in Fig. 20-19 has Vs = 5 V and Itmnax) = 300 mA. The load voltage is not to exceed 7 V. Select suitable

components for D; and Rj, and specify the SCR. Assume that Vc = 0.8 V. Solution Vz = Vigmaxy — Vo = 7 V — 0.8V =62V For Dy, select a 1N753 with Vz = 6.2 V

Select

Iz7(min) = 1 mA

a = WGIz = O8V 1mA = 800 © (use 820 © standard value)

SCR specification: Vorm > 7 V, Itjav) > 300 mA

Heater Control Circuit The circuit in Fig. 20-20 uses a temperature-sensitive control element (R2).

The resistance of R2 decreases when the temperature increases, and increases

912

Electronic Devices and-Circuits

Heater =

Temperature sensitive device

3

4 ey,

SCR,

Figure 20-20

SCR heater

control circuit. The SCR is triggered on when the temperature is below a specified level and held off

2

when the temperature is satisfactory.

when

the temperature falls. Diode D; keeps capacitor C; charged

to the

supply voltage peak, and C; together with resistor R; behaves as a constanteurrent source for Ro. When R; is raised to the desired temperature, Vg drops

to a level that keeps the SCR from triggering. When the temperature drops, the resistance of R2 increases, causing Vg to increase to the SCR triggering

level. The result is that the load power is turned off when

the desired

temperature is reached, and turned on again when the temperature falls to a

predetermined level. Rectifier D. might be included, as illustrated, to pass the negative half-cycle of the supply waveform to the load.

Practice Problem 20-3.1 The SCRin the circuit in Fig. 20-20 triggers when Vg is 0.8 V or higher, but..will not trigger when Vg is 0.6 V. The temperature-sensing -element (R>) has a resistance of 400 0 at 95°C and 300 © at 100°C.

. Determine suitable values for R; and C; that will trigger the SCR at

95°C and leave it untriggered at 100°C. 20-4

TRIAC AND DIAC

TRIAC Operation and Characteristics The basic construction, equivalent circuit, and graphic symbol for a TRIAC are shown in Fig. 20-21. The TRIAC behaves as two inverse-parallel connected SCRs with a single gate terminal. Sections 11, p2, 13, and p3 in Fig.

20-21a form one SCR that can be represented by transistors Q; and Q> in Fig. 20-21b. Similarly,

Pir Ny Pr, and

n4 form

another

SCR

with

the transistor

equivalent circuit Q3 and Qy. Layer p2, common to the two SCRs, functions as a gate for both sections of the device. The two outer terminals cannot be identified as anode and cathode; instead they are designated main terminal 1 (MT1) and main terminal 2 (MT2), as illustrated. The TRIAC circuit symbol is composed of two inverse-parallel connected SCR symbols (Fig. 20-21c). When MT2 is positive with respect to MT1, transistors Q3 and Q, can be triggered on (Fig. 20-21b), In this case the current flow is from MT2 to MT1.

Thyristors

Chapter 20

913

MT2

MT1

O

O

MT1

MT]

(a) Basic TRIAC construction

Figure 20-21

(b) Equivalent circuit

(c) Circuit symbol

Basic construction, equivalent circuit, and graphic symbol for a TRIAC.

When MT1 is positive with respect to MT2, Q; and Q2 can be switched on. Now current flow is from MT1 to MT2. It is seen that the TRIAC can be made

to conduct in either direction. Regardless of the MT2/MT1 voltage polarity, the characteristics for the TRIAC are those of a forward-biased SCR. This is

illustrated by the typical TRIAC characteristics shown in Fig. 20-22.

Figure 20-22 TRIAC characteristics. These are similar to the characteristics of two inverse-parallel connected SCRs.

914

Electronic Devices and Circuits

TRIAC Triggering

The characteristics and circuit symbol in Fig. 20-22 show that when MT2 is positive with respect to MT1, the TRIAC can be triggered on by application of a positive gate voltage. Similarly, when MT2 is negative with respect to MT1, a negative gate voltage triggers the device into conduction. However, a negative gate voltage can also trigger the TRIAC when MT72 is positive, and

a positive gate voltage can trigger the device when MT72 is negative. Figure 20-23 shows the triggering conditions for a 2N6346, 8 A, 200 V TRIAC. The voltage polarity for MT2 is identified as MT2(+) or MT2(— ), and the gate polarity is listed as G(+) or G(—). From the first line of the specifications, it is seen that with MT2

positive, the device

gate triggering

voltage is +0.9 V minimum and +2 V maximum. From the second line, still

with MT2 positive, triggering can be produced by a negative gate voltage: —0.9 V to —2.5 V. The third line shows MT2 negative and the gate trigger voltage as —1.1 V to —2 V. Also, with MT2 negative (fourth line), triggering

can be effected by a positive gate voltage: +1.4 V to +2.5 V. 2N6346 TRIAC

Ver Min

Max

MT2(+), G(+)

0.9-V

MT2(+), G(—)

0.9V

2.5V

MT2(—), G(-)

PTY

2V

14V

25V

MT2(—), G(+)

“

2

;

Figure 20-23

.

Partial

specification showing the

triggering conditions fora

2N6346 TRIAC.

The TRIAC triggering conditions are further illustrated by the diagram in Fig. 20-24. The vertical line identifies MT2 as positive or negative, and the horizontal line shows the gate voltage as positive or negative. The TRIAC is

defined as operating in one of the four quadrants: I, II, III, or IV. In quadrant I, MT2 is positive, the gate voltage is positive, and current flow is from MT2

to MT1, as shown. When MT2 is positive and the device is triggered by a negative gate voltage, the TRIAC is operating in quadrant II. In this case, current flow is still from MT2 to MT1. Quadrant III operation occurs when

MT2

is negative and the gate voltage is negative. Current flow is now from

MT1 to MT2. In quadrant IV, MT2 is again negative, the gate voltage is positive, and current flow is from MT1 to MT2. Normally, a TRIAC is operated in either quadrant I or quadrant III. When this is the desired condition, it may be necessary to design the circuit to avoid quadrant II or quadrant IV triggering.

Chapter 20

_siThyristors

915

+

+

MT2 MT2

|r G

=

Ic -

6mm G

Quadrant II | Quadrant I

G

+

Quadrant III | Quadrant IV

© MT2

© MT2

(

oe

Ig

l

G

v i .

cout MT2

teen

Figure 20-24

Quadrant

diagram illustrating the

TRIAG four-quadrant

operating conditions.

The DIAC A DIAC is simply a low-current TRIAC without a gate terminal. Switch-on is effected by raising the applied voltage to the breakover voltage. Two different DIAC symbols in general use are shown in Fig. 20-25a, and typical DIAC characteristics are illustrated in Fig. 20-25b. Note that the terminals are

Ay

A2

(a) Two DIAC symbols

Figure 20-25

(b) DIAC characteristics

The DIAC is essentially a low-current TRIAC without a gate terminal.

916

Electronic Devices and Circuits

_ DIACs

a

Ws

|

Min

HS-10 |

ew

123

56V

Figure 20-26

labelled

|

Pp

Max

Tg

HS-60

Igmax)

400pA |

70 V

250mW

50 pA

250 mW

Partial specifications for two DIACs.

anode

2

(Az)

and

anode

1

(A,).

Figure

20-26

shows

partial

specifications for two DIACs. The HS-10 has a switching voltage that ranges from a minimum

of 8 V to a maximum

of 12 V. Switching current is a

maximum of 400 A. The HS-60 switching voltage is 56 V to 70 V, and maximum switching current is 50 wA. Both devices have a 250 mW power dissipation, and each is contained in a cylindrical low-current diode- type package. DIACs are most often applied in triggering circuits for SCRs and TRIACs.

Section 20-4 Review 20-4.1 Sketch the construction and transistor equivalent circuit of a TRIAC.

Explain the device operation.

20-4. 2. Sketch TRIAC characteristics. Briefly explain.

20-5 TRIAC CONTROL CIRCUITS TRIAC Phase-Control Circuit

A TRIAC circuit that allows approximately 180° of phase control is shown in Fig. 20-27a. The waveforms in Fig. 20-27b illustrate the circuit operation. With the TRIAC (Q)) off at the beginning of the supply voltage positive half-cycle, 0°

180°

0°

180°

| k

ey

ea .Qy conduction

~t

off

\

|

ton

|

angle

| \

(a) Phase-control circuit

(b) Circuit waveforms

Figure 20-27 TRIAC phase-control circuit and circuit waveforms. Q, is switched on when the capacitor charges to D; breakover voltage.

Chapter 20

Thyristors

917

capacitor C; is charged positively via resistors R; and Rz, as shown. When Vey reaches the DIAC switching voltage plus the Q, gate triggering voltage, D, conducts passing gate current to trigger Q, on. C; discharges until the

discharge current falls below the D; holding current level. The TRIAC switches off at the end of the supply positive half-cycle, and then the process is repeated during the supply negative half-cycle. The rate of charge of C; is set by variable resistor R,, so that the Q; conduction angle is controlled by

adjustment of Rj. Example 20-5 Estimate the smallest conduction angle for Q; for the circuit in Fig. 20-27a. The supply is 115 V, 60 Hz, and the components are R; = 25 KO, Ro = 2.7 kQ,

and C; = 3 pF. The D, breakover voltage is 8 V and Vg = 0.8 V for Qi. Solution At Q; switch-on,

Va

= Vp

+ Vo =8V

+08 V

= 8.8V Assume the average charging voltage is

E = 0.636 X Vacpk) = 0.636 X 1.414 x 115 V ~103 V

Average charging current,

_—

Ic ~

Ry + Rp

25kQO

ae

+ 2.7kO

3.7 mA tr =

Charging time:

a e

—

V

= 7.1ms

T=

Q; switch-on point:

; = aE

= 16.7 ms

t X 360°

7.1ms X 360°

aes

a

= 153° Gorduetion angle:

a=

180° —

= 180° — 153°

= 27°

TRIAC Zero-Point Switching Circuit The

TRIAC

zero-point switching circuit in Fig. 20-28a

produces

a load

waveform similar to that for the SCR zero-point circuit in Fig. 20-18. The load

918

Electronic Devices and Circuits

@

ac voltage source

D,

(b) With Q, on, Q, is held off Figure 20-28

Dz

(c) Ig flows when Q, is off

(d) Vc, triggers Q,

Zero-point switching circuit for a TRIAC. While Q; is on, Q2 cannot switch

on. With Q; off, Q2 starts to conduct at the beginning of the supply positive half-cycle.

power dissipation is controlled by switching the TRIAC on for several cycles of the supply voltage and off for several cycles, with switch-on occurring only at the negative-to-positive zero crossing point of the supply waveform, and switch-off taking place at the positive-to-negative zero point. Q, is a low-

current SCR that controls the switching point of Qo. With switch S; closed, Q, is on, and the Q, forward voltage drop is below the level required for triggering Q) (Va2 + Vp + Vp2) (see Fig. 20-28b). Thus, no gate current flows to Q2, and no conduction occurs. Q; switches off when Si is opened, so that Ic flows to Q2 gate via C1, Rx, Dy, and D> to trigger Q> into conduction (Fig. 20-28c). With Q, conducting, capacitor C2 is charged via D3

almost to the positive peak of the load voltage (Fig. 20-28d). The TRIAC switches off at the end of the positive half-cycle. Then, the charge on C2

(applied to the gate via D2) triggers Qo on again just after the zero-crossing point into the negative half-cycle. (It should be noted this is quadrant IV

triggering.)

Chapter 20

__‘Thyristors

919

The initial Q; switch-on occurs only at the beginning of the positive halfcycle of the supply voltage. If S, is opened during the supply positive halfcycle, Q; continues to conduct until the end of the half-cycle, thus keeping Q> off. With Qs off, C2 remains uncharged, and so it cannot trigger Q» on during the supply negative half-cycle. Q, triggering now occurs at the beginning of

the next positive cycle. If S; is opened during the supply negative half-cycle, Q2 cannot be triggered into conduction, again because of the lack of charge on Cp. It is seen that Q2 conduction can start only at the beginning of the positive half-cycle of the supply voltage. Once triggered, Q2 conduction continues until the end of

the cycle. To design the circuit in Fig. 20-28, the TRIAC is first selected to pass the

required load current and to survive the peak supply voltage. Resistor Rp is a low-resistance component calculated to limit the peak surge current to the Q> gate in the event that the peak supply voltage is applied to the circuit without

Q; being on. Capacitor C; has to supply triggering current (Ic) to Q2 at the zero crossing point of the supply waveform when Q; is off. Usually Ic2 is

chosen to be about three times the specified Ic¢¢max) for Qz, and C; is then calculated from the simple equation for capacitor charge: C = (J x #)/AV. In this case AV /t can be replaced by the rate of change of the supply voltage at the zero crossing point, which is 27 fV,. So the C; equation is

Cc,

Igo

=-=— Z 27fV>

(20-5)

Resistor R; can now be determined by using the selected gate current for Q» (Ig2) as the peak anode current for Q;: Ri = V,/Ic2. The Qi gate resistor (R3) is calculated from the Q; triggering current and the voltage of the dc source:

Ry

=

(E =

Vo1)/Ici.

The Q, gate current is again used in the calculation of Ry and C). To trigger

Q, at the start of the supply negative half-cycle, Ig. must flow from C) into the Q» gate; so Ry © V,p/Ic2. A suitable capacitance for Cz is now calculated by again using the simple capacitance equation C2 = (Ic2 X t)/AV. In this case, time t is selected much larger than the Q) turn-on time, and AV is

approximately 0.1 Vp. SCR Q; must pass the selected anode current (Ig2) and survive the peak supply voltage. The diodes must each survive the peak supply voltage and

pass the Q, triggering current.

The IC Zero Voltage Switch The functional block diagram for a typical integrated circuit TRIAC driver,

known as a zero voltage switch, is shown in Fig. 20-29. The device contains a voltage limiter and a dc power supply, so that it operates directly from the ac

920

Electronic Devices and Circuits

a

Wenger.

[

Bower

| limiter

| ‘supply

1

O°

|

Zero crossing detector

ac, source

TRIAC drive stage

7

On-off sensing

_jamplifier,

Figure 20-29

Functional block diagram for an integrated circuit zero voltage switch, or

TRIAG driver.

supply

to the load to be controlled. There is also a zero crossing detector

(see Section 14-9) that provides an output pulse each time the supply waveform crosses the zero level. The zero crossing detector output is fed to an AND gate (see Section 3-11), and the AND gate output goes to the TRIAC drive stage that produces the current pulse to the TRIAC

sensing amplifier is used

to sense the voltage level from

gate. An

on-off

an externally

connected transducer; for example, a temperature-sensing transducer would

be, used if the load is a heater. When the temperature drops to a predetermined level, the on-off sensing amplifier provides an input to the AND gate. The gate triggering pulse from the TRIAC drive stage occurs at the

supply zero-crossing points only when the temperature is below the desired level. The circuit load waveforms are similar to those shown in Fig. 20-18.

Practice Problem 20-5, A, Determine ‘suitable components for the TRIAC zero-point switching _. circuit in Fig. 20-28, given the following parameters: for Q,, Ig =

200 pA, Vr = 2 V; for Qo, Ic. = 30 mA, Icom = 1A, ton = 100 ps; E = 4... 6N;and ac source= 115 V,.60. Hz.

20-6

SUS, SBS, GTO, AND SIDAC

The SUS The silicon unilateral switch (SUS), also known as a four-layer diode and as % a Schokley diode, can be treated as a low-current SCR without a gate terminal.

Chapter 20

___Thyristors

921

SUS circuit symbol and Figure 20-30 forward characteristics.

Vs

20-30

Figure

the

shows

circuit

SUS

symbol

typical

and

forward

characteristics. The device tri ggers into conduction when a forward switching

voltage (Vs) is applied. At this point a minimum switching current (Is) must flow. The voltage falls to a forward conduction voltage (Vp) at switch-on, and conduction continues until the current level falls below the /iolding current

(Iq). The 2N4988 SUS has Vs ranging from 7.5 V to 9 V, Is = 150 pA, and ly

=

0.5 mA.

characteristics:

SUS a

reverse

very

small

characteristics reverse

are

current

similar flows

to SCR

reverse

the

reverse

until

breakdown voltage is reached.

The SBS It is convenient to think of a silicon bilateral switch (SBS) as two SUS with a

gate terminal, or as a low-current TRIAC. However, the SBS is not simply another four-layer device. Silicon bilateral switches are actually integrated circuits

constructed

of

matched

transistors,

diodes,

and

resistors.

This

produces better parameter stability than is possible with four-layer devices.

The SBS equivalent circuit in Fig. 20-31a is similar to the TRIAC equivalent circuit with the addition of resistors Ry and R2 and Zener diodes D; and D>.

The device circuit symbol in Fig. 20-31b is seen to be composed of inverseparallel connected SUS symbols with a gate terminal added. Note that the terminals are referred to as anode 1 (A1), anode 2 (Az), and gate (G). The typical

SBS characteristics shown in Fig. 20-31c are essentially the same shape as TRIAC characteristics. Returning to the equivalent circuit, the SBS switches on when a positive AjA: voltage is large enough to cause D2 to break down. This produces base current in Qy;, resulting ina Qi collector current that switches Q> on. Similarly,

a negative A;A2 voltage causes D, to break down, producing base current in Q, that turns Qs and Qs on. The switching voltage is the sum of the Zener diode voltage and the transistor base-emitter voltage (Vs = Vz + Vpr). The

922

Electronic Devices and Circuits

Ay

G

OA,

As

(a) Equivalent circuit

(b) Symbol

+I

Vig

—s| Ten

Vso

——-v nee

Fie

—_—

7 _

ih. ae p--L_j- ta

Jv wr

T

Dinas

~hL

Igo

[oo

|

apseb

+V—>-

T

t

>

I

Vs

Vp2

=]

’ (c) Characteristics

Figure 20-31 Equivalent circuit, symbol, and characteristics for the silicon bilateral switch (SBS).

Zener diode has a positive temperature coefficient (TC) and the transistor base-

emitter voltage has a negative TC. This results in a very small TC for the SBS switching voltage.

The partial specification for a MBS4991 SBS in Fig. 20-32 shows a switching voltage that ranges from 6 V to 10 V. Note also that the switching

Chapter 20 MBS4991

Switching voltage (Vs)

Min

Typ

Max

6V

8V

10 V

175 pA 0.3 V

500 pA 0.5 V

14V

100 pA 100 pA 1.7V

Switching current differential Gate trigger current (Icp) Forward-on voltage (Vp) Partial specification for the MBS4991

silicon bilateral switch.

voltage differential (the difference between the switching voltages in opposite directions) (Vs; — Vs2), is 0.5 V maximum. The maximum switching current is a 500 wA, and the differential (Is, — Isz) is 100 pA.

923

SBS

Switching current (Is) Switching voltage differential

Figure 20-32

_Thyristors

switching

current

SBS devices are frequently used with the gate

D

open-circuited, so that they simply break down to

the forward voltage drop when the applied voltage increases

to

the

switching

voltage

level.

The

switching voltage can be reduced by connecting Zener diodes with Vz lower than 6.8 V between the gate and the anodes, as shown in Fig. 20-33a. The

(a) Vg modification by external Zeners

new switching voltage is approximately (Vz + 0.7 V).

The switching voltage can also be modified by the use of external

resistors

(Fig. 20-33b).

Taking the

gate current into account, it can be shown that the two 22 kO resistors reduce Vs to approximately

D

3.6 V. The use of an SBS in a TRIAC phase-control circuit is illustrated in Fig. 20-34. This is essentially the same as the circuit using a DIAC in Fig. 20-27.

The SBS turns on and triggers the TRIAC when the capacitor voltage equals the SBS switching voltage plus the TRIAC gate triggering voltage.

For an SBS to switch on, the total resistance

(b) Vs modification by external resistors

Figure 20-33 The switching voltage for an SBS can be modified by externally connected Zener diodes or

resistors. in series with it must have a maximum value that allows the switching current to flow. If the resistance is so large that it restricts the current to a level below the SBS

switching current, the device will not switch on. The series resistance must

not be so small that it allows the holding current to flow when the SBS is supposed to switch off. These restrictions also apply to SCRs, TRIACs,

924

@)

Electronic Devices and Circuits

ac voltage

Ry

source

R, Figure 20-34

Use of an SBS in a TRIAC phase-

control circuit. The TRIAC

oe

is triggered by the

current surge when the SBS switches on.

DIACs, and other similar switching devices. Switch-off is usually no problem in thyristor circuits with ac supplies, because the devices normally switch off when the instantaneous supply voltage reduces to zero. With de supplies, more care must be taken with resistor sizes. Figure 20-35 shows a simple circuit that requires careful design to ensure

that the SBS switches on and off as required. The circuit is a relaxation oscillator that produces an exponential output waveform, as illustrated. Capacitor C, is charged via resistor R,; from the de supply voltage (E). When the capacitor voltage (Vc) reaches the SBS switching voltage (Vs), D, switches on and rapidly discharges the capacitor to the D; forward voltage (Vp). Then D,

_switches off, and the capacitor begins to.charge again. The SBS will not switch off if the D, holding current (Jj) continues to flow through R; when Vc equals

Vp. SBS switch-on will normally occur when Vc equals Vs regardless of the R, resistance, because the capacitor discharge should provide the switching current (Is). However, it is best to select Rj small enough to allow Is to flow at D, switch-on.

cecil

Port C, charge | time

(a) Relaxation oscillator circuit

Figure 20-35

C, discharge time

(b) Circuit waveforms

SBS relaxation oscillator. C, charges via R, to the

‘SBS switching voltage. D; switches on-at that point and rapidly

discharges C;.

F

Chapter 20

Thyristors

The approximate oscillation frequency can be determined

925

from the

capacitor charging time (f), and the equation for t is derived from the RC charging equation.

t=

CR in|

E-—Vp

Y, ———-

(20-6)

|

Example 20-6 The SBS in the circuit in Fig. 20-35 has the following parameters: V>=10V, Ve = 1.7 V, Is = 500 pA, and [yy = 1.5 mA. Calculate the maximum and minimum

resistances

for R;

for correct

circuit

operation

when

E

=

30 V.

Determine the capacitor charging time when Ry = 27 kQ. and C; = 0.5 pF. Solution

Ruma) =

B=

%0v=—10V

= 500 nA

= 40 kO _E-Vp Ra(min) = ly

30V-17V 15mA

= 18.9kO

Eq. 20-6:

t= CRIn

E-Vr E—Ve

= 0.5 pF X 27kQ In

30V — ae 30V

-— 10V

= 4.7 ms

The GTO When an SCR is triggered into conduction by application of a gate current, the

gate loses control and the device continues to conduct until the forward current falls below

the holding current. A gate turn-off (GTO)

device

is

essentially an SCR designed to be switched on and off by an applied gate signal. The circuit symbol for a GTO is shown in Figs 20-36a, and the two-

transistor equivalent circuit for the device is illustrated in Fig 20-36b and c. Note that at switch-on, the gate current has got to be just large enough to supply base current to transistor Qo. However, at switch-off, the Q; collector current has to be diverted through the gate terminal in order to turn Q> off.

Consequently, for device turn-off, relative large levels of gate current are

involved, approaching half the GTO forward current. The SIDAC The

SIDAC

is a two-terminal

thyristor designed

mainly

for use in over-

voltage protection situations. As a bilateral device with no gate terminal, it

926

Electronic Devices and Circuits

Anode

Gate

| | Turn-on

Cathode

Turn-off

pulse

(a) Symbol

pulse

(b) Switch-on

(c) Switch-off

Figure 20-36 The gate turn-off device GTO is effectively an SCR that can be switched off by a voltage applied to the gate.

simply breaks down to its forward voltage drop when the applied terminal

voltage (of either polarity) rises to the breakover voltage level. Like other

thyristors, there is a minimum current that must flow to latch the SIDAC into

an on state. When it is switched on, conduction continues until the current falls below a holding current level. The circuit symbol and typical characteristics for a SIDAC are shown in Fig. 20-37. Available devices have breakover voltages ranging from 110 V to 280 V. Usually, on state voltage is 1.1 V, rms current is 1 A, and

holding

current is 100 mA.

Eh J

Tiny

4—-y'

Laks

=

Ss

4 ~~ IBo

Ly =e

\

MT1

Vio)

Pp

|

ff

MT2 (a) Symbol Figure 20-37

(b) Characteristics Circuit symbol and characteristics for a SIDAC.

Chapter 20

__—iThyristors

927

Figure 20-38 shows a SIDAC used to protect a de power supply from ac line transients. Normally, the SIDAC will behave as an open-circuit. A voltage transient on the ac line will cause it to break down to its forward voltage level, so that it essentially short-circuits the transformer output. This

will cause a fuse to blow or a circuit breaker to trip, thus interrupting the ac

supply.

e# Ot

Voltage regulator

Figure 20-38 SIDAC used for protecting a dc power supply against transients on the supply line.

Practice Problem 20-6.1

The SBS in the circuit in Fig. 20-34 has Vs ~ 4 V, Is = 500 pA, and

In(max) = 200 mA. The ac supply is 115 V, and R3 = Ry = 22 kO. Determine suitable resistances for R, and Ro.

20-7

UNIJUNCTION TRANSISTOR (UJT)

UJT Operation The unijunction transistor (UJT) consists of a bar of lightly doped n-type silicon with a block of p-type material on one side (see Fig. 20-39a). The end terminals of the bar are identified as Base 1 (B,) and Base 2 (Bz), and the p-type

block is named the emitter (E).

B, E

By (a) Basic construction

Figure 20-39

(b) Equivalent circuit

(c) Circuit symbol

A unijunction transistor (UJT) is made up of a p-type emitter joined to a bar

of n-type semiconductor.

928

Electronic Devices and Circuits

Figure 20-39b shows

the UJT equivalent circuit. The resistance of the n-

type silicon bar is represented as two resistors, rp; from By; to point C, and rp, from Bz to C,.as illustrated. The sum of rg and and rpz is called Rgp. The p-

type emitter forms a pn-junction with the n-type silicon bar, and this junction

is shown as a diode (D;) in the equivalent circuit.

With a voltage Vgipo applied as illustrated, the voltage at the junction point C is

Vi = Veip2 X

os

BB

Note that V; is also the voltage at the cathode of the diode in the equivalent circuit. With the emitter terminal open-circuited, the resistor current is

Ipo =

VB1B2 Rpp

(20-7)

If the emitter terminal is grounded, the pn-junction is reverse-biased and there

is a small emitter reverse current (Ix). Now consider what happens when the emitter voltage (Vegpi) is slowly increased from zero. When

Vp: equals V1, the emitter current is zero. (With

equal voltage levels on each side of the diode, neither reverse nor forward current flows.) A further increase in Vgpi forward-biases the pn-junction and causes a forward current (Ig) to flow from the p-type emitter into the s-type silicon bar. When this occurs, charge carriers are injected into the rg; region.

Since the resistance of the semiconductor material is dependent on doping, the

additional

charge

carriers

cause

the

resistance

of

the

rs;

region

to

decrease rapidly. The decrease in resistance reduces the voltage drop across rei, and so the pn-junction is more heavily forward-biased. This in turn results in a greater emitter current and more charge carriers that further

reduce the resistance of the rgi region. (The process is termed regenerative.) The input voltage is pulled down, and the emitter current (Ig) is increased to a

limit determined by the V¢pi source resistance. The device remains in this on condition until the emitter input is open-circuited, or until Ig is reduced to a

very low level. The circuit symbol for a UJT is shown in Fig. 20-39c. As always, the

arrowhead points in the conventional current direction for a forward-biased junction. In this case it points from the p-type emitter to the n-type bar.

UJT Characteristics A plot of emitter voltage Vegi versus emitter current I; gives the UJT emitter characteristics. Refer to the UJT terminal voltages and currents shown

in

Fig. 20-40a and to the equivalent circuit in Fig. 20-39b. Note that when

__iThyristors

Chapter 20 Cutoff region

‘(a)'UJT voltages and currents

Negative resistance region

929

Saturation region

6

Vest (sat) ——. Vy

aw

0

~" of

1

2

3

4 (mA)

Point1 P

(V) desc 1

| |

dat 14 fr \ i”

12}44

1}

“AL

coral ,V

ye

= 20V

Vpip2 7 15'V

|

Vpip2 = 10 vo

(c) Family of UJT characteristics Figure 20-40

The UJT characteristics show that the device triggers on at various levels

of emitter voltage Veg1, depending upon the level of supply voltage Vpip2.

Veip2 = 0, Ipo = Oand V; = 0. If Vegi is now increased from zero, the resultant plot of Vgp; and Ig is simply the characteristic of a forward-biased diode with some series resistance. This is the characteristic for Iz = 0 in Fig. 20-40b. When Vpip2 is 20 V, the level of V; (Fig. 20-39b) might be around 15 V, depending on the resistances of rg; and ’p2. With Vgip2 = 20 V and Vgpi = 0, the emitter junction is reverse-biased and the emitter reverse current Igo

flows, as shown at point 1 on the Vgip2 = 20 V characteristic in Fig. 20-40b.

930

Electronic Devices and Circuits

Increasing Vgpi until it equals V; gives Iz = 0; point 2 on the characteristic. A further increase in Vgpi forward-biases the emitter junction, and this gives the peak point on the characteristic (point 3). At the peak point, Vgp) is identified as the peak voltage (Vp) and Ig is termed the peak current (Ip). Up until the peak point, the UJT is said to be operating in the cutoff region of its characteristics. When

Vp

arrives at the peak voltage, charge carriers

are injected from the emitter to decrease the resistance of rpi, as already explained. The device enters the negative resistance region, rp falls rapidly to a saturation resistance (rs), and Vxp; falls to the valley voltage (Vy), (point 4 on the characteristic in Fig. 20-40b). Ip also increases to the valley current (Iy) at this time. A further increase in Ig causes the device to enter the saturation region, where V¢pi equals the sum of Vp and Ig X rs.

Starting with Vgip2 lower than 20 V gives a lower peak point voltage and a different characteristic. Thus, by using various levels of Vpip2, a family of

Vepi/Ig characteristics can be plotted for a given UJT, as shown in Fig. 20-40c.

UJT Packages Two

typical UJT

packages

with

the terminal

identified

are shown

in

Fig. 20-41. These are similar to low-power BJT packages.

B, EB,

E

B, Bottom view

By Bottom view

B, EB,

By p By

(a) Resin-encapsulated UJT

Figure 20-41

(b) UJT in a metal can

UJT packages

ane Nernlnate.

UJT Parameters Interbase Resistance (Rpg): This is the sum of rg; and rg2 when Ig is zero. Consider Fig. 20-42, which shows a portion of the manufacturer’s data sheet for 2N4949 UJT. Rgp is specified as 7 kO typical, 4 kO minimum, and 12 kO

maximum. The value of Rpp, together with the maximum power dissipation Pp, determines the maximum voltage Vg1p2 that may be used. When Iz = 0,

V51B2(max) = V (Rep Pp) , Like

all other

temperatures.

devices,

the

Pp

of the

UJT

must

(20-8) be

derated

for

higher

Chapter 20

Thyristors

931

2N4949 UJT

Min Interbase resistance (Rpp)

OD sci.DASE tt

4kO,

7kO

12 kQ 0.86

0.74

Intrinsic standoff ratio (7)

Emitter saturation voltage (Vepi (sat)

25V

3V

Peak point current (Ip)

0.6 pA

1pA

Valley point current (Iy) Figure 20-42

2mA

4mA

Partial specification for a 2N4949 UUT.

Example 20-7 AUJT has Rgpimin) = 4 kO, Pp = 360 mW at 25 °C, and a power derating factor

D = 2.4 mW/°C. Calculate the maximum temperature of 100°C.

Vgip2 that should be used at a

Solution Ppaoo) = Pps») — [D (T2 - 25°)|

Eq. 8-26:

= 360 mW

— [2.4mW/°C (100° — 25°)|

= 180 mW

Verpotmey = V(RppPp) = V4 «2 X 180 mW)

Eq. 20-8:

= 26.8 V

Intrinsic Standoff Ratio (): The intrinsic standoff ratio is simply the ratio of rgi to Rpg. The peak point voltage is determined

from

7, the supply

voltage, and the diode voltage drop: Vp

= Vp

+ nVpiB2

Emitter Saturation Voltage (Vepi(say)):

(20-9)

This is the emitter voltage when the

UJT is operating in the saturation region of its characteristics; the minimum Vzp level. Because it is affected by the emitter current and voltage, Vepiat) is specified for given Ig and V3ip2 levels.

the supply

Example 20-8 Determine UJT with

the maximum Vp1B2

=

and minimum

triggering voltages for a 2N4949

25V.

Solution

From Fig. 20-42,

= 0.74 minimum, 0.86 maximum

982

Electronic Devices and Circuits

Vptmax) = Vo + (max Vein2) = 0.7 V + (0.86 X 25 V) = 222

Eq, 20-9:

Vpcniny = Vo + (nmin Vere) = 0.7V + (0.74 X 25 V) =192V Peak Point Emitter Current (Ip): Ip is important as a lower limit to the

emitter current. If the emitter voltage source resistance is so high that Is is not greater than Ip, the UJT will simply not trigger into the on state. The maximum emitter voltage source resistance is

Regan) =

Vep — Vp Ip

(20-10)

where Vp is the circuit supply voltage.

Valley Point Current (Ty): ly is important in some circuits as an upper limit to the emitter current. If the emitter voltage source resistance is so low that Ip is equal to or greater than Ivy, the UJT will remain on once it is triggered; it will not switch off. So the minimum emitter voltage source resistance is

Vep 7 VEBisat) Reqmin)

7

(20-11)

Ivy

UJT Relaxation Oscillator The

relaxation

oscillator circuit

in Fig.

20-43a

consists

of

a UJT

and

a

capacitor (C;) charged via resistance Rg. When the capacitor voltage (Vc)

reaches Vp, the UJT fires and rapidly discharges Ci to Vepiyat. The device Slams

|


to the UJT firing voltage, and the SCR is triggered by the voltage drop across

R3. By adjusting R2, the charging rate of C; and the UJT firing time can be selected. The waveforms in Fig. 20-44b show that 180° of SCR phase control is possible. D,

0° Supply waveform

Ry

180° j

|

Load

waveform

I

T

Q,

rhb | end

|

angle

| l | |

Capacitor

waveform

i

a

t

f~

| | |

| |

; | | | |

1

R3 waveform 1—_+ i (a) UJT control circuit for SCR

|

ee a

conduction

180°

|

tay

off

0° 1

I | |

i —?,

| ! | |

=I

Vi

P| |

\ Vr3

(b) Circuit waveforms

Figure 20-44 UJT 180° phase-control circuit for an SCR. Resistor R2 controls the C; charging rate and the SCR firing point.

Practice Problems 20-7.1 A 2N4870 UJT

has the following parameters: Pp = 300 mW

at 25°C,

“D=3mW/°C, n = 0.56 to 0.75, Rep = 4kO to 9.1 kO, Vapieay = 2.5 V, Ip = 1 pAto 5 pA, and ly = 2mAto5 mA. Determine the maximum _ Vpip2 that may be used: at 75°C.

20-7.2. Calculate the Vpgmax) and Vpdmin) for a 2N4870 when Vpp = 30 V. 20-7.3 A 2N4870 is used in the circuit in Fig. 20-44. If D, has Vz = 30 V, determine the maximum and minimum resistance values for Ro.

Chapter 20

20-8

PROGRAMMABLE

Thyristors

935

UNIJUNCTION TRANSISTOR (PUT)

PUT Operation The programmable unijunction transistor (PUT) is actually an SCR-type device used to simulate a UJT. The interbase resistance (Rpg) and the intrinsic standoff ratio (n) can be programmed to any desired values by selecting two resistors.

This means that the device firing voltage (the peak voltage Vp) can also be

programmed. Consider

Fig.

20-45a,

which

shows

a four-layer device with its gate connected to the junction of resistors Ry and R2. Note that the gate terminal is close to the anode of the device, instead of the cathode as for an SCR. The

anode-gate junction becomes forward-biased when

the anode is positive

with respect to the gate. When this occurs, the device is triggered on. The anode-to-cathode voltage then drops to a low level, and the PUT conducts heavily until the current becomes too low to sustain conduction. To simulate

the UJT performance, the anode of the device acts as the UJT emitter, and R, Vp are and R2 operate as rp; and rp, respectively. Parameters Rpp, 7, and

programmed by the selection of Rj and R2. The four-layer block diagram is replaced with the PUT graphic symbol in Fig. 20-45b. Note that this is the same as the SCR symbol except that the gate terminal is at the anode.

PUT Characteristics The typical PUT characteristic (Vax plotted versus I4) shown in Fig. 20-46 is seen to be very similar to UJT characteristics. A small gate reverse current (Iago) flows while the anode-gate junction is reverse-biased. At this point the PUT is in the cutoff region of the characteristics. When the anode voltage is raised sufficiently above the gate voltage (Vc in Fig. 20-45), the PUT is triggered into the negative resistance region of its characteristics and the

(a) PUT four-layer construction

Figure 20-45

(b) PUT circuit

The programmable unijunction transistor (PUT) is an SCR-type device that

can be connected to function like a UJT.

936

Electronic Devices and Circuits

Cutoff

| Negative resistance

region,

region

Saturation region

Figure 20-46 The typical Vax/I, characteristics for a PUT are similar to UJT characteristics.

anode-cathode voltage falls rapidly to the valley voltage (Vy). A further increase in I, causes the device to operate in its saturation region. PUT Parameters The intrinsic standoff ratio for the PUT is

Ry

Re Be

(20-13)

Vo = 1Vep

(20-14)

Vp = Vp + 1V pp

(20-15)

The gate voltage is simply

and the peak voltage is

|

where Vp is the anode-gate junction voltage, typically 0.7 V. The gate source resistance (Rc) is an important quantity because it affects the peak current and valley current for the PUT. Rg is the resistance at the

junction of voltage divider R; and Rp (Fig. 20-45): Rg

= Rill Ry

(20-16)

Refer to the partial specification for a 2N6027 PUT in Fig. 20-47, and note the

typical quantities. With Rg = 1 MQ, Ip = 1.25 pA and Iy = 18 A; with Rc = 10 kO, Ip = 4 pA and Iy = 150 pA.

Chapter 20

937

i Thyristors

2N6027 PUT Peak current (Ip) Valley current (Iy) Forward voltage (Vp) Figure 20-47

Typ

Max

1 MQ) 10 kf) 1 MQ) 10 kQ)

1.25 pA 4A 18 pA 150 pA

2 pA 5A 50 pA -

(Ip = 50 mA)

0.8 V

(Rg (Rg (Ro (Rg

= = = =

15V

Partial specification for a programmable unijunction transistor.

PUT Applications A PUT can be applied in any circuit where a UJT might be used. Figure 20-48 shows

a PUT

relaxation

oscillator

used

to control

an SCR.

This

circuit

operates in essentially the same way as the UJT circuit in Fig. 20-44. It should be noted that there are upper and lower limits to the resistance that can be connected in series with the PUT anode for correct operation of the device. This is similar to the Re(min) and ReGnaxy Fequirement for the UJT.

Figure 20-48 SCR phase-conirol circuit using a PUT relaxation oscillator.

A battery charger circuit using a PUT (Q:) and an SCR (Q>) is shown in Fig. 20-49. The ac supply voltage is full-wave-rectified and applied via current-limiting resistor Rs to the anode of the SCR. The SCR is triggered into conduction by the PUT output coupled via transformer T;. The PUT gate voltage (Va) is set by the voltage divider (R3, Ry, and Rs). While Vc is lower than the Zener diode voltage (Vz), capacitor C; is charged via R; to the PUT

peak voltage. At this point the PUT fires and triggers the SCR on. As the battery charges, its voltage (Eg) increases, and thus Vg also increases. The increased Vg raises the Vp of the PUT and causes C; to take a longer time to charge. Consequently, the SCR is held off for a longer portion of

the ac supply half-cycle. This means that the average charging current is gradually reduced as the battery approaches full charge. When Eg is fully charged, Vc is raised to the Vz level, so that Dg conducts and stops the C; voltage from firing the PUT. Thus, the SCR remains off and battery charging stops. The circuit will not operate if the battery is connected with the wrong

polarity.

938

Electronic Devices and Circuits

(ye lis

NWN Rs

YS

r

Ry 1kO

\

Ry

Rg

100 kO

6.8 kO,

D 6

ac voltage

r

Ry

10 kA, +

source

i

pax 2

Ex

ls

ve

2)

1

*Ps

4

1N5240 |

+ o. Battery under charge

Rs

0.

33 kA

yh yd

Figure 20-49

SCR battery charger using a PUT control circuit.

Example 20-10 Calculate

Vpgmax) and

Vpimin) for the PUT

in the circuit in Fig. 20-49 when

Eg = 12 V. Determine the gate bias resistance Rc, and calculate the maximum and minimum resistances for R> if the PUT is a 2N6027. Solution

Eq. q 20-13:

11 (max)

=

R

° Rg+Rygt+R,

=

33k0,

6.8k0+10kN+33kO0,

= 0.86

Rs

“Neris) RZ+R,+R;

33k0,

68kK0+10kK0+33kO

= 0.66

Eq. 20-15: Vp(may = Vo + (mmax) Van) = 0.7 V + (0.86 X 12 V) =11V

Vpimin) = Vp + (max) Ves) = 0.7V + (0.66 X 12 V) = 8.6V Kq. 20-16:

Rg = (R3 + 0.5 Ra) II (Rs + 0.5 Ra) = (6.8 kO + 5) 11 (33 kO + 5 kQ) =9kO

_E—Vpmaxy _12V—11V = 250 kO

Chapter 20

Roqmin) =

ly

Thyristors

939

150 pA

= 740,

Practice Problems 20-8.1 The circuit in Fig. 20-48 has Vpp = 15 V, R2 = 12 kO, and R3 = 18 kQ.

The PUT has Ip = 10 wA, Iy = 100 pA, and Vz = 1 V. Calculate Rg, n, 20-8.2

Vp, and the maximum and minimum resistances for Ri. Determine the voltage that the battery will be charged to in Fig. 20-49

when the moving contact is at the middle point on Ry. Assume that the PUT will stop firing when Vac is reduced to 0.5 V.

Review Questions

Section 20-1 20-1

20-2

20-3

Sketch the construction of a silicon-controlled rectifier. Sketch the twotransistor equivalent circuit and show how it is derived from the SCR construction. Label all terminals and explain how the device operates. Sketch typical SCR forward and reverse characteristics. Identify all regions of the characteristics and all important current and voltage levels. Explain the shape of the characteristics in terms of the SCR twotransistor equivalent circuit. List the most important SCR parameters and state typical quantities for low-, medium-, and high-current devices.

Section 20-2 20-4 Draw the circuit diagram to show how an SCR can be triggered by the application of a pulse to the gate terminal. Sketch the circuit waveforms and explain its operation. 20-5 Sketch a 90° phase-control circuit for an SCR. Draw the load waveform and explain the operation of the circuit. Show the circuit and load waveforms when the ac supply is full-wave-rectified.

20-6

Draw the diagram for a 90° phase-control circuit using two SCRs for full-wave phase control. Draw the load waveforms and briefly explain the circuit operation.

20-7

Sketch a 180° phase conirol for an SCR. Draw the load waveform and

explain the circuit operation. Section 20-3 20-8 Briefly discuss SCR circuit stability and draw methods that can be used to improve stability.

diagrams

to show

940

20-9

Electronic Devices and Circuits

Draw the diagram for anSCR zero-point triggering circuit.

Ex plain the

circuit operation and advantages and draw the load waveform. 20-10 Sketch a circuit that uses an SCR to protect a load from excessive dc

supply voltage. Briefly explain. 20-11 Draw a diagram for an SCR heater control circuit using a temperature-

sensitive device. Explain the circuit operation. Section 20-4 20-12 Draw sketches to show the construction, equivalent circuit, and characteristics of a TRIAC. Identify all important voltage and current

levels on the characteristics and explain the operation of the device. 20-13 Using diagrams, explain the four quadrant operating conditions for a TRIAC. 20-14 Draw

the

typical

characteristics

for

a

DIAC.

Explain

the

DIAC

operation, and sketch the two circuit symbols used for the device.

Section 20-5 20-15 Draw the diagram for a TRIAC 180° phase-control circuit. Draw all

waveforms and explain the circuit operation.

20-16 Draw the diagram for an TRIAC zero-point triggering circuit and carefully explain its operation. 20-17 Sketch the functional block diagram for an IC zero voltage switch for TRIAC control. Discuss the components of the block diagram. Section 20-6 20-18 Using diagrams, briefly explain a silicon unilateral switch (SUS). Draw

the device circuit symbol. 20-19 Sketch the equivalent circuit and characteristics for a silicon bilateral switch (SBS). Explain how the device construction differs from that of other thyristors. Discuss the device operation, state typical parameters, and show how the switching voltage can be modified. 20-20 Sketch a relaxation oscillator circuit using an SBS. Draw the output

waveform, and explain the circuit operation. 20-21 Draw the circuit symbol and equivalent circuit for a gate turnoff device (GTO) and discuss its operation. 20-22 Draw

the circuit symbol

and

typical characteristics

for a SIDAC.

Discuss its operation and applications. Section 20-7 20-23 Draw sketches to show the basic construction and equivalent circuit of

a unijunction transistor (UJT). Briefly explain the device operation. 20-24 Sketch typical UJT Vepi /Tg characteristics for Ip, = 0, Vpip2 = 20 V, and

Veip2 = 10 V. Identify each region and all important points on the characteristics, and explain the shape of the characteristics.

Chapter 20

Thyristors

941

20-25 Define the following UJT parameters: intrinsic standoff ratio, interbase resistance, emitter saturation voltage, peak point current, and valley

point current. 20-26 Draw the circuit of a UJT

relaxation oscillator with

provision

for

frequency adjustment and spike waveform. Show all waveforms, and explain the circuit operation. 20-27 Sketch a UJT circuit for controlling an SCR. Draw all waveforms, and briefly explain how the circuit operates. Section 20-8 20-28 Draw the basic block diagram and basic circuit for a programmable unijunction transistor (PUT); explain the device operation. 20-29 Sketch typical PUT characteristics, explain how the intrinsic stand-off ratio may be programmed, and identify the most important PUT parameters.

20-30 Draw a basic PUT circuit for controlling an SCR; explain its operation. 20-31 Draw the circuit diagram of a battery charger using a PUT and an SCR. Explain the circuit operation.

Problems Section 20-1 20-1 Consult 2N6167

and 2N1595

SCR

specifications to determine

the

typical values for Vorm, Jt, Viw, In, Jor, and Ver.

Section 20-2 20-2 Choose a suitable SCR from Fig. 20-10 for a circuit with a 115 V ac supply. Calculate the minimum load resistance that can be supplied, and determine the instantaneous voltage level when the SCR switches

off. 20-3

A 33 ( resistor is supplied from an ac source with a 60 V peak level. Current to the load is to be switched on and off by an SCR. Select a

suitable device from the specifications in data sheet A-17 in Appendix A, and determine

the instantaneous supply voltage at which

the SCR

switches off. 20-4

An SCR with a 115 V ac supply controls the current through a 150 0 load resistor. A 90° phase-control circuit (as in Fig. 20-11) is employed

to trigger the SCR between 12° and 90°. The gate trigger current is 50 20-5

wA, and the trigger voltage is 0.5 V. Calculate suitable resistor values. The circuit in Fig. 20-12 has a 50 V ac supply and Ry,= 20 0. Determine suitable resistance values for Ri, R2, and R3 such that the SCR will be

triggered anywhere between 7.5° and 90°. The gate trigger current and

voltage are 500 pA and 0.6 V.

942

20-6

Electronic Devices and Circuits

The circuit in Problem 20-5 uses a 2N5170 SCR (see data sheet A-17 in Appendix A). Calculate the instantaneous supply voltage level when

the SCR switches off. 20-7 Design the circuit in Fig. 20-13 for 10° to 90° phase control; specify the SCRs. The ac supply is 115 V, R, = 12 0, and the SCRs have Vc = 0.6 V and Ig = 100 pA. 20-8 A180° phase-control circuit as in Fig. 20-15 has a 40 V, 400 Hz ac supply and

Ry = 22 Q.. The SCR has

Ve

= 0.5 V, Ig =

60 pA,

and

lcm

=

20 mA.

Determine suitable resistor and capacitor values, and specify the SCRs and the diodes. Section 20-3 20-9

An SCR crowbar circuit (as in Fig. 20-19) is connected to a 12 V de

supply with a 200 mA current limiter. Design the crowbar circuit to protect the load from voltage levels greater than 13.5 V. Assume that Vc = 0.7 V for the SCR.

20-10 A zero-point triggering circuit (as in Fig. 20-18) is to control the power dissipation in a 12 ©, load resistor with a 115 V, 60 Hz ac supply. Assuming

that

the

SCRs

have

Vg

=

0.5

V

and

Igmmin)

=

10

mA,

determine suitable capacitor and resistor values. 20-11 An SCR heater control circuit (as in Fig. 20-20) is to switch on at 68°C

and off at 71°C. The circuit is to operate from a 50 V, 60 Hz supply, and the available temperature-sensitive device has a resistance of 500 © at 68°C and 350 O at 71°C. The load resistance is Ry = 2.5 O and the SCR

has Vc = 0.6 V. Determine suitable component values, and calculate the SCR gate voltage at 71°C. 20-12 Specify the SCRs required for the circuits in Problems 20-9, 20-10, and 20-11 in terms of maximum anode-cathode voltage and maximum anode current. Section 20-4 20-13 Consult specifications for 2N6071

and 2N6343 TRIACs

to determine

the maximum supply voltage, maximum rms current, and the typical quadrant I gate triggering voltage. Section 20-5

20-14 A light dimmer uses a TRIAC 180° phase-control circuit, as in Fig. 2027. The ac supply is 220 V, 60 Hz, and the total load is 750 W. The TRIAC has triggering current Ig = 200 A, maximum gate current Ign

= 50 mA, and Vg = 0.7 V. The DIAC has Vs = 9.2 V and Is = 400 pA.

Determine suitable component values. 20-15 The TRIAC control circuit in Fig. 20-27 has the following components: Ry = 100 Q, Ry = 10 kQ, R2 = 500 0, C; = 3.9 wR The DIAC has Vz =

Chapter 20

Thyristors

943

7 V, and

the TRIAC has Vo = 1V. The ac supply is 60 V, 60 Hz. Determine the minimum conduction angle for the TRIAC. 20-16 Specify the TRIACs required for the circuits in Problems 20-14 and

20-15. 20-17 The TRIAC zero-point switching circuit in Fig. 20-28 uses an SCR with

Ig = 100 pA and Vz = 1.5 V. The TRIAC has Ig = 5 mA, Ic = 500 mA, and fon = 50 us. The control voltage is E = 5 V, the ac source is 60 V,

60 Hz, and the load is Rj = 15 Q. Determine suitable component values. Section 20-6 20-18 A relaxation oscillator (as in Fig. 20-35) uses an SBS with Vs = 8 V, Ve = 1 V, Is = 300 pA, and fy = 1 mA. The dc supply is E = 40 V. Calculate maximum and minimum R values for correct operation of

the circuit. 20-19 A relaxation oscillator (as in Fig. 20-35) has a 25 V supply, a 1 pF

capacitor, and a 12 kQ series resistor. The capacitor is to charge up to 15 V and then discharge to approximately 1 V. Specify the required SBS in terms of forward conduction voltage, switching voltage, switching

current, and holding current. 20-20 The phase-control circuit in Fig. 20-34 has the following components: Ry = 18 0, Ry = 12 kO, Rp = 470 0, and C; = 10 wF. Resistors R3 and R,

are replaced with 3.3 V Zener diodes, and the TRIAC triggering voltage is Vo = 1 V. The ac supply is 115 V, 60 Hz. Determine the TRIAC minimum conduction angle. Section 20-7 20-21 Determine the maximum

power dissipation for a 2N2647 UJT at an

ambient temperature of 70°C. Calculate the maximum V3}p2 that may be used at 70°C. Data sheet A-18 in Appendix A gives partial specification for the 2N2647.

20-22 Calculate the minimum and maximum Vp; triggering levels for a 2N2647 UJT when Vpip2 = 20 V. 20-23 A relaxation oscillator (as in Fig. 20-43) uses a 2N2647 UJT with Vpp = 25 V. Calculate the typical oscillation frequency if C, = 0.5 uF and Rg = 3.3 ki. 20-24 Calculate the maximum and minimum charging resistance values that can be used in the circuit of Problem 20-23. 20-25 The UJT phase-control circuit in Fig. 20-44 has a 115 V, 60 Hzac supply,

and an SCR with Vg = 1 V and Icgm = 25 mA. Design the circuit to use a 2N2647 UJT and a Zener diode with Vz ~ 15 V.

944

Electronic Devices and Circuits

Section 20-8 20-26 A PUT operating from a 25 V supply has Vp = 1.5 V and Ig = 50 pA. Determine values for R; and R2 program 7 to 0.75. Calculate Vp, Vy, Rgp,

and

Ro.

20-27 A PUT relaxation oscillator (as in Fig. 20-48) has a 0.68 wF capacitor. The PUT has Vg = 1 V and Ig = capacitor voltage is to be 5 V and the oscillating 300 Hz. Determine suitable resistor values. 20-28 The UJT in Problem 20-23 is to be replaced with

20 V supply and a 100 pA. The peak frequency is to be a PUT.

Determine

suitable resistance values for the gate bias voltage divider. 20-29 A PUT has a forward voltage of Vp = 0.9 V and Ig = 200 wA.

The

device is to be programmed to switch on at Vg = 15 V when operating from a 24 V supply. Determine values for R; and Ro, and calculate Vp, Vv, Rpg, and Rc.

Practice Problem Answers

20-2.1 20-2.2 20-3.1 20-51 20-6.1 20-71 20-7.2 20-7.3 20-8.1 20-8.2

163 V,1.6A, 18 kO, 1.5 kO; 180.0 10 kQ, 0.82 pF 1.5kO (68kQ + 12k), 4 uF 1k0,1800,5.6k0,1kO, 2.5 pF 1 pF 500kQ, 3200 24.5V 23.2V,17.5V 1.36 MO, 6.25 kO. 7.2 kQ, 0.6, 9.7 V, 530 kQ, 140 kO 13.4V

CHAPTER 21 Optoelectronic Devices Objectives You will be able to:

Explain solar cells, and design

1 Define important illumination

units and calculate illumination

solar cell battery charger circuits.

intensity at a given distance

from a source. Explain the fabrication and operation of a light-emitting

Explain the operation of a phototransistor, sketch phototransistor characteristics, and discuss its parameters.

diode (LED), discuss its

parameters, and design LED circuits.

Explain the operation of liquid crystal displays (LCDs), show how LCDs and LEDs are used in seven-segment numerical

Explain photodarlingtons and photo-FETs. 10 Design phototransistor circuits

for energizing relays, triggering SCRs, and so on.

Explain the construction and

displays, and calculate power dissipations in each type of display. Explain the construction and operation of a photoconductive cell, sketch the device

11

characteristics, and discuss its parameters.

different supply voltages. 13 Explain the construction and operation of a photomultiplier

Design photoconductive cell circuits to bias BJTs on or off,

energize relays, trigger Schmitt circuits, and so on. Explain the construction and operation of a photodiode, sketch photodiode characteristics, and discuss its parameters.

Design photodiodes into circuits where they operate as a photoconductive devices and as photovoltaic devices.

operation of optocouplers, and discuss optocoupler parameters. 12 Design optocoupler circuits for

coupling pulse-type and linear signals between systems with

tube, and discuss its

characteristics and parameters. Design voltage dividers for biasing photomultiplier tube

electrodes. 14 Explain the operation of a laser diode. Discuss the device characteristics and parameters.

Design and analyze laser diode control circuits.

946

Electronic Devices and Circuits

INTRODUCTION Optoelectronic devices emit light, modify light, have their resistance affected by light, or produce currents and voltages proportional to light intensity. Light-emitting diodes (LEDs) produce light and are generally used as indicating lamps and in numerical displays. Liquid crystal displays (LCDs), which modify light, are also used as numerical displays. Photoconductive cells have a resistance that depends upon illumination intensity. They are used in circuits designed to produce an output change when the light level changes. The current and voltage levels in photodiodes and phototransistors are affected by illumination. These devices are also used in circuits that have their conditions altered by changes in light levels. Illumination is converted into electrical energy by means of solar cells, and this energy is often used to charge storage batteries. Optocouplers combine LEDs and phototransistors to provide a means of coupling between circuits that have different supply

voltages while maintaining a high level of electrical insolation.

21-1

LIGHT UNITS

The total light energy output, or luminous flux (¢,), from a source can be measured in milliwatts (mW) or in lumens (lm), where 1 lm = 1.496 mW. The luminous intensity (E,) (also termed illuminance) of a light source is defined as

the luminous flux density per unit solid angle (or cone) emitting from the source (see Fig. 21-1a). This is measured in candelas (cd), where one candela

is equal to one lumen per unit solid angle (assuming a point source that emits light evenly in all directions).

E, = 5

(21-1)

The light intensity (Eq) on an area at a given distance from the source is

determined

from

the surface

area

of a sphere

surrounding

the source

Mer Né AWS Soe I. Point light

solid angle

source (a) Flux per unit solid angle Figure 21-1

area.

Point light

Unitarea

source (b) Flux per unit area

Light intensity can be expressed in flux per unit solid angle or in flux per unit

Chapter 21 _— Optoelectronic Devices

947

(Fig. 21-1b). At a distance of r metres, the luminous flux is spread over a

spherical area of 47r* square metres. Therefore, Eq = os

(21-2)

Agry*

When

the total flux is expressed in lumens, Eq. 21-2 gives the luminous

intensity in !umens per square meter (lm/ m7’), also termed /ux (Ix). Comparing Eq. 21-2 to Eq. 21-1, shows that the luminous intensity per unit area at any

distance r from a point source is determined by dividing the source intensity

by 7. Luminous intensity can also be measured in milliwatts per square centimetre (mW/cm?), or lumens per square foot (Im/ft?), also known as a foot candle (fc), where 1 fc = 10.764 Ix.

The light intensity of sunlight approximately 107 640 lx, or 161 lamp is approximately 4.8 X 10° At a distance of 2 m, this is 1.2 x

on the earth at noon on a clear day is W/m7?. The light intensity from a 100 W cd (allowing for a 90% lamp efficiency). 10° Ix. An indicating lamp with a 3 med

output can be clearly seen at a distance of several metres in normal room lighting conditions.

Example 21-1 Calculate the light intensity 3 m from a lamp that emits 25 W of light energy.

Determine the total luminous flux striking an area of 0.25 m’ at 3 m from the lamp. Solution

Eq. 21-2:

Ea =

25 W

Pe

Am ~~ dor X (3m)?

= 0.221 W/m?2 = 221 mW/m? Total flux = Ea X area = 221 mW/m?

X 0.25 m?

~55 mW

Example 21-2 Determine the light intensity at a distance of 2 m from a 10 mcd source. Solution

_ E, (ed) _ 10mcd A

2

= 2.5 mlx

72

948

Electronic Devices and Circuits

Light energy is electromagnetic radiation; that is, it is in the form of electromagnetic waves. Thus it can be defined in terms of frequency or

wavelength, as well as intensity. Wavelength, frequency, and velocity are

related by the equation

c= fA where

(21-3)

c = velocity = 3 x 10° m/s for electromagnetic waves f = frequency in Hz A = wavelength in metres

The wavelength of visible light ranges from violet at approximately 380 nm (nanometres) to red at 720 nm. From Eq. 21-3, the frequency extremes are f

_¢ violet

—

_3*x

10° m/s

Xr

380 nm

~8 x 10!* Hz

tyes ree

3 x 108 m/s

A

720 nm

4

Practice Problems 21-1.1 » » -21-1.2. 21-1.3

A lamp is required to produce a light intensity of 213 lx at a distance of 5 m. Calculate the total light energy output of the lamp in watts. Calculate the frequency of yellow light with a 585 nm wavelength. Determine the light intensity 3.3 m from an 8 mcd lamp, and the total

luminous flux striking a 4 cm? area at that location.

21-2

LIGHT-EMITTING DIODES (LED)

LED Operation and Construction _ Charge

carrier recombination

occurs

at a forward-biased

pn-junction

as

electrons cross from the n-side and recombine with holes on the p-side. Free

electrons have a higher energy level than holes, and some of this energy is dissipated in the form of heat and light when recombination takes place. If the semiconductor material is translucent, the light is emitted and the junction

becomes a light source, that is, a light-emitting diode (LED). A cross-sectional view of an LED junction is shown

semiconductor

material

is gallium

arsenide

(GaAs),

in Fig. 21-2a. The

gallium

arsenide

phosphide (GaAsP), or gallium phosphide (GaP). An n-type epitaxial layer is grown upon a substrate, and the p-region is created by diffusion. Since charge carrier recombinations occur in the p-region, the p-region is kept uppermost to allow the light to escape. The metal film anode connection is

Chapter 21

Optoelectronic Devices

949

Solid plastic |

gr

Light

Light

canted

emitted

.

\\

Anode

pn-junction

// Charge carrier recombination

\ O+0+0+0+0+0+

-

|

AN

|+—

7

Reflector

p-type

|= type

Anode

sg

Cathode

of

Cathode

(a) LED junction

(b) Typical construction

(c) Graphic symbol

Figure 21-2 A light-emitting diode (LED) produces energy in the form of light when charge carrier recombination occurs at the pn-junction.

patterned to allow most of the light to be emitted. A gold film is applied to the bottom of the substrate to reflect as much light as possible toward the surface of the device and to provide a cathode connection. LEDs made from GaAs emit infrared (invisible) radiation. GaAsP material produces either red

light or yellow light, while red or green light can be created by using GaP. Through the use of various materials, LEDs can be manufactured to produce

light of virtually any color. Figure 21-2b shows the typical construction of a LED. The pn-junction is

mounted on a cup-shaped reflector, wires are provided for anode and cathode connection, and the device is encapsulated in an epoxy lens. The lens can be colorless or colored, and (when not energized), the lens color

identifies the LED light color. The color of the light emitted by the energized LED is determined solely by the pn-junction material. Some LEDs have glass particles embedded in the epoxy lens to diffuse the emitted light and

increase the viewing angle of the device. The LED circuit symbol is shown in Fig. 21-2c. Note that the arrow directions indicate emitted light.

Characteristics and Parameters LED characteristics are similar to those of other semiconductor diodes, except that (as shown in the partial specification in Fig. 21-3) the typical forward

voltage drop is 1.6 V. Note also that the reverse breakdown voltage can be as low as 3 V. Insome circuits it is necessary to include a diode with a high reverse breakdown voltage in series with a LED. The forward current used with a LED is usually in the 10 mA to 20 mA range, but (depending on the particular

device) the peak current can be as high as 90 mA. LED luminous intensity depends on the forward current level; it is usually specified at 20 mA. The peak wavelength of the light output is also normally listed on the specification.

950.

Electronic Devices and Circuits

Typical LED Specification

Min

Typ

Luminous intensity (Iy at 20 mA)

4 med

8 mcd

Forward voltage (Vx)

14V

1.6 V

Reverse breakdown voltage (Vgpr) | 3 V

10 V

Peak forward current (Izmax))

90 mA

Average forward current (Ip(av))

20 mA

Power dissipation (Pp)

20 '¥

100 mW

Response speed (ts)

90 ns

Peak wavelength (Ap) Figure 21-3

Max

:

660 nm

Partial specification for a typical light-emitting diode.

LED Circuits

As explained, an LED is a semiconductor diode that emits light when a forward current is passed through the device. A single LED might be employed simply as a supply voltage on/off indicator, as illustrated in Fig. 21-4a. A series-connected resistor (Ri) must be included

to limit the

current to the desired level. Figure 21-4b shows an LED connected at the output of a comparator to indicate a high output voltage. As well as the current-limiting resistor (Ri), an ordinary semiconductor diode (D;) is connected in series with the LED to protect it from an excessive reverse

voltage when the comparator output is negative. + Vec

Comparator + Vee

(a) LED as on /off indicator Figure 21-4

(b) LED as high output voltage indicator

Light-emitting diode indicator circuits.

LEDs are often controlled by a BJT, as illustrated in Figs 21-5a and b. Transistor Q; in Fig. 21-5a is switched into saturation by the input voltage (Vp). Resistor R limits the transistor base current, and R limits the LED current. In Fig. 21-5b, the emitter resistor (R;) limits the LED current to (Vp — Vpr)/R1.

Chapter 21

Optoelectronic Devices

951

VE (sat)

(a) Rz controls Ip, Q, is saturated Figure 21-5

(b) R, controls Ig, Q, is not saturated

BUT control circuits for light-emitting diodes.

Example 21-3 The LED in Fig. 21-5a is to have a forward current of approximately 10 mA. The circuit voltages are Vcc = 9 V, Vg = 1.6 V, and Vg = 7 V; and Q, has

hrg(min) = 100. Calculate suitable resistance values for R; and Ro. Solution ee

= Veco — Vg — Vex (sat) _ 9V-16V-02V

a

Ie

10 mA

= 720 O (use 680 0 standard value) Ic becomes

= Veco — Ve ~ Vega) 9V-16V -—02V c~ Ry 680 2 =106mA In

=

8

Ic

_

hee¢nin)

10.6 mA

100

= 106 pA

Rp = —

te

106 pA

= 59 kQ (use 56 kQ standard value)

952

Electronic Devices and Circuits

Practice Problems 21-2.1

The LED in the circuit in Fig. 21-5b is to pass a 20 mA current. The circuit voltages are Vcc = 15 V, Vp = 1.9 V, and Vg = 5 V. Determine a

suitable resistance for Ry, and calculate Vcg for Q). 21-2.2

Determine suitable resistances for the circuits in Fig. 21-4 to give Ig = 15 mA. The LEDs have Vx = 1.8 V. Also, Vcc = 6 V in Fig 21-4a,

and in Fig. 21-4b the op-amp output is V, = +9 V. 21-3

SEVEN-SEGMENT

DISPLAYS

so

. Pull-up resistor R2 isnecessary to ensure that

the load terminal is held at the 5 V supply level when Qz; is off. tVecy od

24V 97

Ry

yal)

1D, \

+VeCee

5V

=

Load

:

=

Oo

SS

=

3

Figure 21-37

Octocoupler used for coupling a signal from a 24 V

system to a 5 V system.

Example 21-11 The optocoupler in Fig. 21-37 is required to sink a 2 mA load current when Q2 is in saturation and If; = 10 mA. The optocoupler has the specification in

Fig. 21-36. Determine suitable resistor values. Solution From the specification: Ic¢2 = 5 mA when Ipp; = 10 mA

Tro = Ie. - Ip =SmMA-—2mA =3mA Fine 2

Vcc2

— VcR(sat) Tro

eV

=02¥V 3 mA

= 1.6 kO (use 1.8 kO to ensure Q) saturation)

7 ,

Veci — Vepi — Vick at) _ 24V-15V-02V Trp1 10 mA = 2.23 kQ (use 2.2 kQ)

A linear application of an optocoupler is shown

in Fig. 21-38. The 5 V

supply provides a dc bias current to D, via Ro, and the ac signal coupled via C,; and R; increases and decreases the diode current. Transistor Q, is biased into an on state by the direct current through Dj, and its emitter current is

increased and decreased by the variation in light level produced by the alternating current in D,. An output voltage is developed across R3.

974

Electronic Devices, and Circuits

+Vec Ry

390.0

+ Ve

[Tea

IBV.

i

1

i ig "l

43

es ae

=

47kQ

4

| TE(de) Rg

2.2 kO

t i, |

Figure 21-38

Linear signal

coupling by means of an octocoupler.

Other Optocouplers Other types of optocouplers involve different types of output stage. The three types illustrated in Fig. 21-39 are (a) Darlington-output type, (b) SCRoutput, and (c) TRIAC-output. In (a), the photo-darlington output stage provides much higher CTR than a BJT phototransistor output stage

LO 5

2

3 Oe

301g

(a) Darlington output Figure 21-39

ptO4

(b) SCR output

Los

x

205

89 304—

Lo4

(c) TRIAC output

Octocouplers are available with various types of output stage.

(typically 500%), but it also has a slower response time. The output stages in

(b) and (c) are a light-activated SCR and a light-activated TRIAC, respectively. They are used with the kind of control circuits discussed in Chapter 20, where high electrical isolation between the triggering circuit and the control

device is an additional requirement. CTR does not apply to SCR and TRIAC

output stages; instead, the LED current needed to trigger the thyristor is of interest.

Optocoupler output Maximum

stages are not designed for high load currents.

current levels for Darlington outputs are about

150 mA,

and

300 mA is typical for SCR and TRIAC outputs. When high-load currents are

to be switched, the optocoupler output

high-power device.

stage is used as a trigger circuit for a

Optoelectronic Devices

Chapter 24

975

Practice Problems 21-7.1 An octocoupler with the specification in Fig. 21-36 is to control a 10 mA relay with a 30 V supply. The input stage is connected via a resistor (Ri) toa5 V supply. Calculate a suitable resistance for R.

21-7.2

Analyze

the circuit in Fig. 21-38 to determine

the dc bias current

through D; and the ac signal current peaks. Calculate the maximum and minimum de and ac output voltages. The octocoupler used has a diode with Vp = 1.5 V, and a CTR ranging from 20% to 70%.

21-8 PHOTOMULTIPLIER TUBE Operation Although many semiconductor photoelectric devices are currently available,

the photomultiplier tube is still widely used, essentially because it is an Figure

device.

ultra-fast

and

sensitive

extremely

21-40

illustrates

the

principle of the photomultiplier tube. It consists of an evacuated glass cylinder containing a photocathode, an anode, and several additional electrodes known as dynodes. Note that the anode and cathode are at opposite ends of the tube, and that the anode is at a very high positive voltage with respect to the cathode. The dynodes are biased to voltage levels distributed between the cathode and anode voltages. ; Incident

+100 V

+500 V

|

|

1 Dynode |

illumination %,

+300 V

D,

D;

4

+700 V

\\

/

4

WY, iji}

N

Emitted electron

Cathode

Secondary

I electrons OV

Figure 21-40

|

4

Dynode 2

+200 V




Figure 21-41 Typical photomultiplier tube t/voltage characteristics. The dark

curren ‘ current occurs when there is zero cathode

illumination, and the anode current increases

with increased illumination levels.

electrodes. The sensitivity and spectral response are largely dependant on the cathode material. The spectral responses available range from 200 nm to 800 nm. As well as being very sensitive, photomultiplier tubes respond in nanoseconds to illumination changes. Hence they are appropriate for the detection of very fast low-level occurrences.

Circuit Diagrams Figure 21-42a shows a circuit diagram employing a common photomultiplier

graphic symbol. Note that the cathode has a high negative voltage supply,

Chapter 21

and that

the dynode

voltages

Optoelectronic Devices

by a multi-resistor

are provided

977

voltage

divider connected between the cathode and ground. Thus, the dynodes are at progressively higher positive voltage levels moving from the cathode to

the anode. The anode is connected via a resistor to a level more positive than ground, and also to the input of an amplifier. The use of a negative cathode voltage enables the anode output to be relatively close to ground, which is convenient for connecting to an amplifier input or to measuring instruments. Another photomultiplier graphic symbol sometimes used in circuit diagrams is shown in Fig. 21-42b. EB PP +200 V

72

Cathode (K)

#

Dynode: aa7

Anode (P) 8

\

\

\

~

~ Amplifier

wr)

~

(a) Photomultiplier circuit

_— Dynodes

~~ Anode Cathode

(b) Alternative photomultiplier circuit symbol Figure 21-42

Photomultiplier circuit and alternative graphic symbol. In this circuit the

cathode is supplied from a —2 kV source and the anode has a +200 V supply. A voltage divider is used to bias the dynodes to levels between ground and —2 kV.

In some circumstances it might not be convenient to apply a negative high-voltage supply to the cathode (as shown in Fig. 21-42). For example, if a grounded light source is in direct physical contact with the glass at the cathode, the high voltage can produce a leakage current that affects the performance of the photomultiplier. In this situation it is preferable to ground the cathode and connect the anode to a positive high-voltage source, as shown in Fig. 21-43. The output from the anode is coupled via a high-

voltage capacitor (Ci) to subsequent measurement or amplification stages.

978

Electronic Devices and Circuits

D,

D,

=" _

i,t

D

= Lt

= Ll

rE =

R,

R,

R,

Vv, +2kV

Figure 21-43

Photomultiplier circuit with the cathode grounded and the anode supplied

by a +2 kV source. Because of the high anode voltage the output has to be capacitor

coupled. The dynodes have to supply the currents of electrons that pass from one dynode to another inside the tube. For dynode voltage stability, the voltage divider Current (/p) should be much larger than the maximum

anode current.

Voltage Divider The design of the voltage divider circuit for biasing the dynodes is a very

important part of the application of photomultipliers. Normally, the design process simply involves selecting a suitable current and then calculating each resistor value in terms of its voltage drop and the voltage divider current. However, the current that flows between successive dynodes in the form of incident and secondary electrons has to be supplied by the voltage divider, as illustrated in Fig. 21-43. If it is assumed that each incident electron

striking a dynode produces two secondary electrons, then the current levels in Fig. 21-43 would be progressively doubled between successive dynodes, (Iz = 2h, Iz = 2, etc.). Working backwards from D6, Ig ~ 2 I, /3, Is © Ix /3, I, = Iy/6 etc. In fact, the current ratio between successive dynodes could be

much greater than 2:1. However, it is clear that the dynodes closest to the

anode have the highest current levels, and the last dynode before the anode

has a higher current than the rest.

The best approach to voltage divider design would seem to be to select a resistor current very much larger than the anode current, so that the dynode

voltages remain substantially constant regardless of the anode current level. However, a high current can produce heating of the volta ge divider resistors, and because the resistors are likely to be located close to the photomultiplier

tube, the device performance can be affected by the heating; for example, the dark current will be increased. In practical circuit applications the volta ge divider current should be at least 20 times the maximum anode current, and for best performance the ratio should be 100. Example 21-12 demonstrat es

that high power dissipation resistors are required for a voltage divider.

Chapter 21

Optoelectronic Devices

979

O

42 kV (a) Zener diode stabilization of dynode voltages

TF +2 kV

(b) Capacitor stabilization of dynode voltages Figure 21-44

Dynode voltage stabilization using Zener diodes and parallel-connected

capacitors. The capacitors are most effective for a photomultiplier tube with a pulsed illumination input.

Example 21-12 Calculate suitable resistor values for the voltage divider illustrated in Fig. 21-43. Assume that the maximum anode current is 2 mA. Solution

Vaz Vak _2kV 7

7

= 285.7 V Select,

Ipn= 20 X Tacenax) =20X2mA

=40mA

R= VR_285.7V Ip

40mA

= 7.14 kQ (use 6.8 kO)

Pee (VR) _ (285.7 V)" RR

6.8 kO,

= 12 W (use 15 W) R, to R7 = 6.8 kQ, 15 W

980

Electronic Devices and Circuits

Two methods used for dynode voltage stabilization are shown in Fig. 21-44. The Zener diodes shown in Fig. 21-44a hold the voltages constant at the three dynodes closest to the anode. The Zener diodes should obviously be selected to have a breakdown voltage (Vz) equal to the calculated resistor voltage

drop, and the voltage divider current (Ip) must be large enough to keep the diodes operating during breakdown. An Ip level larger than the diode test current (It) is satisfactory. Also, Ip must not exceed the specified maximum Zener diode current (Iz).

Figure 21-44b shows capacitors connected in parallel with the three voltage divider resistors closest to the anode. This arrangement is suitable for photomultiplier tubes that are subject to pulse operation (illumination input

in the form of pulses). The capacitors supply the required dynode current pulses while holding the voltage levels nearly constant. The capacitance values are usually calculated by allowing no more than a 1% capacitor voltage change due to the dynode currents during the input pulse on time. Example 21-13 Determine suitable capacitance values to be connected resistors Rs, Re, and R7 in the voltage divider designed

in parallel

with

in Ex. 21-12, if the

light input has a pulse duration of 100 ps. Solution Assume that

Ig% In, 15~I4/2, and Ig I4/4 and allow that AVc7 ~ Vr/100

Cy=

I, Xt

2 2mAX100 ps AVoy 285.7V/100

= 0.07 pF (use 0.068 pF) /2)Xt_Cy C _ Uy a

= 0.034 pF (use 0.039 1F)

C

_ (In /4)Xt_Cy

"AV, = 0.017 pF (use 0.018 pF)

Note that all three capacitors have to survive approximately 300 V.

Example 21-14 Select suitable Zener diodes to replace resistors Rs, Rg, and Ry in the voltage divider designed in Ex. 21-12.

Optoelectronic Devices

Chapter 21

981

Solution

Vz = Van = Vz3 = 285.7 V Each diode can be made up of two series-connected 140 V Zener diodes. Izy




40 mA

Use 1N3010, 140 V, 10 W Zener diodes with Izp = 18 mA and Izy = 68 mA,

Practice Problems 21-8.1 Determine suitable resistor values to provide the electrode voltages shown in Fig. 21-40. Assume that the maximum anode current is 3 mA. 21-8.2A photomultiplier tube with six dynodes is to be biased as shown in Fig. 21-42a, with a —1400 V supply connected to the cathode and a +100 V anode supply. The maximum anode current is 1.5 mA.

Determine suitable voltage divider resistor values and specify the Zener diodes that could be used to replace Rg and Kz.

21-9 LASER DIODE Operation Laser is an acronym for light amplification by stimulated emission of radiation. A laser emits radiation with a single wavelength or a very narrow band of wavelengths.

This

means

that the

emitted

light

has

a single

color

(is

monochromatic). Laser light is referred to as coherent light, as opposed to light made up of a wide band of wavelengths, which is termed incoherent. A

unique property of light generated by a laser is that the emission is in the form of a very narrow beam; typically 1 ym

to 100 ym

in width. Some

applications of the laser beam are reading bar codes, playing music from a

compact disc, and fibre-optic communication. The operating principle of a laser diode is illustrated in Fig. 21-45. A pn junction of gallium arsenide (GaAs), or GaAs combined with other materials, is manufactured with a precisely defined length (L) related to the wavelength

of the light to be emitted. The ends of the junction are each polished to a mirror surface and usually have an additional reflective coating. One end is only partially reflective so that light can pass through when

lasing occurs.

Consider the effect of charge carriers entering (injected into) the depletion

region of the forward-biased junction, as illustrated in Fig. 21-45. The charge carriers excite the atoms they strike, causing random emission of photons of energy, as electrons are raised to a higher energy level and then fall back to a

lower level. Eventually several photons strike one of the reflective ends of the

junction perpendicularly so that they are reflected back along their original (incident) path. These reflected photons are then reflected back again from

982

Electronic Devices and Circuits

the other end of the junction. The reflection back and forth continues over and over again, and the photons

increase in number,

as they cause other

similar photons to be emitted from atoms. The process of reflection and generation of increasing numbers of photons leads to amplification of the initial reflected light photons. The beam of coherent light emerges from the partially reflective end of the junction. Because of its high-energy density, a laser beam can be quite dangerous. Eye protection must be worn when working with devices employing laser beams. — —

L

— =

Charge carriers Reflected photons Depletion region

Laser beam

Ri eflecti ve end

>

Semi-re j flectivj e end

Charge carriers

Figure 21-45 A

laser diode is basically a pn junction with reflective ends. Photons

reflected from end to end emerge as a narrow beam of coherent light.

Characteristics and Parameters A typical laser diode package is illustrated in Fig. 21-46a and the device characteristics are shown in Fig. 21-46b. The characteristics are a plot of optical power output (P.) versus diode forward current (Ip). Note that the output

power does not increase significantly until Ip exceeds the threshold current (In), which is the level of forward current at which lasing commences. The

output power increases approximately linearly with current increase above the threshold current. At current levels below the threshold, the laser diode

emits incoherent light, just like an LED. The maximum output of typical low-power laser diodes lies in the range

of 2 mW to 10 mW, with threshold currents ranging from 30 mA to 60 mA and operating currents (op) around 60 mA to 150 mA. The forward voltage drop, also termed the operating voltage (Vop), typically ranges from 1.2 V to 2.4 V and the maximum reverse voltage (Vaqpy) is around 2 V. The available

output wavelengths are currently 260 nm to 1800 nm.

Chapter 21

Optoelectronic Devices

983

5 mm

\

(a) Typical laser diode

40 \ 60

20

0

package

—

80

100mA

Threshold current

Ip —

(b) Output power versus forward current characteristic Figure 21-46 Laser diode package and characteristics. Significant power output does not occur until the diode forward current exceeds the threshold current at which lasing commences.

Drive Circuits As seen in Fig. 21-46b, laser diodes are very temperature sensitive. They are also subject to thermal runaway—current increase causing temperature increase, leading to further current increase—which can very rapidly destroy the device. Temperature increase can also cause the laser output wavelength

to jump to another wavelength, a phenomenon termed mode hopping or mode jumping. Consequently, it is very important to operate the device within its specified current range.

Two generally used laser diode drive methods are constant current drive and constant power drive. As the name implies, constant current drive uses a constant current source, such as the circuit illustrated in Fig. 21-47a. Operational amplifier A; has its non-inverting input terminal biased to an adjustable reference voltage (Vier). The output of A; provides the base current to transistor Q:, and the voltage at the emitter of Q: is stabilized at Vy.¢ by feedback diode

to the amplifier’s non-inverting

current

(Ip) substantially

equals

the

input Q;

terminal. emitter

Thus,

current,

the laser which

is

Vet /Rq. A constant power drive circuit, also known as automatic power control (APC), relies on a photodiode included inside many laser diode packages. The photodiode monitors the laser diode light output and produces a current

proportional to the laser output power. The APC circuit in Fig. 21-47b uses

984

Electronic Devices and Circuits

the photodiode current (Ip2) to provide negative feedback to the amplifier. Any increase in laser output power above the design level produces a photodiode current increase, which results in an increase in the voltage drop across Rs. This raises the voltage at the A; inverting input terminal and causes a decrease in the amplifier output. The decrease in A; output voltage reduces the Q; base voltage and results in a decrease in the laser diode current. The decreased level of Ip produces a reduced light output power, which brings Ip2 down to its original level. Thus, the laser diode power

output is stabilized at a constant level. +Vic

412V R

ot Mec

+V

+12'V

Hey diode

Laser

diode

(39 kO +39 kQ)

Laser

|r

R,

20 kO R, (47 kO + 3.3 kO)

(a) Laser diode with a constant current circuit

Figure 21-47

(b) Laser diode with automatic power control

A laser diode can be destroyed by excessive power dissipation. Two

methods of controlling the device forward current and power dissipation are, constant

current and automatic power control.

Modulation Figure 21-48 shows analog and digital modulation methods for laser diodes used in fibre-optic communication equipment. The analog input in

Fig. 21-48a is coupled via capacitor C; to circuit. Capacitor C2 short circuits the ac resistor Re offers a higher impedance otherwise be provided by the A; output.

the base of transistor Q; in an APC feedback from the photodiode, and to the input signal than would The circuit in Fig. 21-48b uses an on

biased switching transistor (Q.) to provide some direct current (Ic) through the laser diode. The required level of Ip is then the sum of Ic, and Ic. The current through Q; is adjusted to the desired level for a constant D, power

output by feedback from D2. The digital input via capacitor C; rapidly switches the Q» collector current between higher and lower levels, thus modulating the laser diode current and its light output power. Because Q> is not switched on and off, its switching speed is not limited by turn-on and turn-off times (see Section 8-5).

Chapter 21

—_ Optoelectronic Devices

985

tVq +12 V

Photo-

diode

Laser diode

\r,

ry

Digital signal

, 10kQ +

ey Analog signal

(a) Analog modulation of laser diode

(b) Digital modulation of laser diode

Output power

Figure 21-48

output power

For fibre-optic communication applications, laser diode power output levels

can be modulated by analog or digital inputs.

Example 21-15 Analyze the constant current circuit shown in Fig. 21-47a to determine the laser diode output power if Vyer is set at 4.9 V. Assume that D, has the P,/Ir

characteristics shown in Fig. 21-46b and that its temperature is 25°C. Solution V.

rR, =~ 60 mA

4.9V

820 \

From the P,/Ip characteristic at Ip = 60 mA, Po 5mW

Example 21-16 The photodiode shown in Fig. 21-47b produces a current of 0.5 mA when the laser diode output is 4 mW. Assuming that D) has the P,/Ig characteristics at 25°C shown in Fig. 21-46b, calculate the required level of Vier and determine the op-amp output voltage when D; is generating 4 mW. Solution Viet= Vrs =Ip2 X R5=0.5mAX 10kO =5V

986

Electronic Devices and Circuits

From the P,/Ig characteristic at P, = 4 mW, Ip= 55mA Vya1 = Vee + (Ip X Rg) = 0.7 V + (55 mA X 82 OD) m52V

Practice Problems | 21-9.1 If Vref is adjusted to 6 V in the circuit shown in Fig. 21-47a, calculate the required resistance for Ry to produce a 6 mW output from D;. Assume that the laser diode has the characteristics at 25°C shown in Fig. 21-46.

21-9.2 Calculate the amplitude of the analog input voltage that should be applied to the base of Q +1 mW

in the circuit shown in Fig. 21-48a to produce a

output from D). Assume that D; has the P,/Ip characteristics at

29°C shown in Fig. 21-46b.

Review Questions Section 21-1 21-1

State measurement

units for luminous

flux and

luminous

intensity.

Using

diagrams, explain flux per unit solid angle. 21-2

Define candela, lumen, and foot candle.

Section 21-2 21-3 21-4 21-5

Sketch diagrams to show the operation and construction of a LED. Briefly explain. For a LED, state typical values of forward current, forward voltage, and reverse breakdown voltage. Draw circuit diagrams showing LEDs used to indicate (a) a de supply voltage switched on and (b) a high output level from an op-amp. Explain each circuit.

21-6

The current level in a LED is to be controlled by the use of a BJT. Sketch two possible circuits, and explain the operation of each.

21-7

An op-amp is to be used to control the current level in a LED. Draw a suitable circuit diagram and explain its operation.

Section 21-3 21-8

Sketch a seven-segment LED display. Explain common-anode and commoncathode connections. Discuss total current numeral, seven-segment display.

21-9

requirements

for a LED

four-

Using illustrations, explain the operation of liquid crystal cells. Discuss the difference between reflective-type and transmittive-type cells.

21-10 Sketch a seven-segment LCD and show the waveforms involved in controlling the cells. Explain.

Chapter 21 _ Optoelectronic Devices

Section 21-4 21-11 Sketch the

typical

construction

and

illumination

characteristics

987

for

a

photoconductive cell. Explain its operation. 21-12 Draw circuit diagrams to show how a photoconductive cell can be used for (a) biasing a pnp transistor off when the cell is illuminated and (b) biasing an npn transistor on when the cell is illuminated. Explain how each circuit operates.

21-13 Draw circuit diagrams to show a photoconductive cell used for (a) triggering an op-amp Schmitt trigger circuit and (b) energizing a relay when the cell is illuminated. Explain the operation of each circuit.

Section 21-5 21-14 Sketch the cross-section of a typical photodiode and explain its operation. Sketch typical photodiode characteristics and discuss their shape.

21-15 For a photodiode, define dark current, light current, and sensitivity. State typical values for each quantity.

21-16 Explain how a solar cell differs from a photodiode. Sketch typical solar cel] characteristics, and discuss the best operating point on the characteristics. 21-17 Sketch the circuit diagram for an array of solar cells employed as a battery charger. Briefly explain.

Section 21-6 21-18 Sketch characteristics for a phototransistor, and

explain how

the device

operates.

21-19 Draw a circuit diagram to show how a phototransistor can be used to energize a relay when the incident illumination is increased to a given level. Explain the circuit operation.

21-20 Modify the circuit drawn for Question 21-19 to have the relay energized until the illumination is increased to a given level. Explain. 21-21 Draw a circuit diagram for phototransistor control of an SCR that triggers on

when the incident illumination falls to a low level. Explain how the circuit operates.

21-22 Sketch a circuit diagram for a photo-darlington. Compare the performance of

photo-darlingtons to phototransistors. 21-23 Sketch a circuit diagram to show the operation of a photo-FET circuit. Briefly

explain the principle of the device. Section 21-7 21-24 Draw the circuit diagram of an optocoupler with a BJT output stage. Sketch a cross-section to show the construction of an optocoupler. Explain the device

operation. 21-25 Discuss the most important parameters of optocouplers.

21-26 Draw a circuit diagram to show how an optocoupler can use a pulse signal from a low-voltage source to control a circuit with a high-voltage supply, or vice versa. Explain how the circuit operates. 21-27 Draw

a circuit diagram to show how

an optocoupler can be used to pass a

linear signal between two circuits with different supply Wolkapes the circuit operates.

Explain how

988

Electronic Devices and Circuits

21-28 Sketch circuit diagrams

for optocouplers with Darlington,

SCR, and TRIAC

outputs. Briefly discuss each optocoupler.

Section 21-8 21-29 Draw a sketch to show the operation of a photomultiplier tube. Briefly explain. 21-30 Define the following: photocathode, anode, dynode, secondary emission, and dark current. 21-31 Sketch and explain typical anode current/voltage characteristics for a photomultiplier tube. 21-32 Draw the circuit diagram of a photomultiplier tube with eight dynodes. Show the cathode biased to a high negative voltage and the anode grounded via a resistor. Explain the circuit operation. 21-33 Briefly discuss the factors involved in voltage divider design for a photomultiplier tube.

Section 21-9 21-34 Using a drawing of a pn junction, briefly describe the operation of a laser diode.

21-35 Sketch the typical P,/Ip characteristics for a laser diode and discuss their shape and the effect of temperature increase. 21-36 Draw a constant current drive circuit for a laser diode and explain its operation. 21-37 Draw an automatic power control circuit for a laser diode and explain its operation.

21-38 Show how a laser diode automatic power modulated. Explain the circuit operation. 21-39 Show how a

control circuit can be analog

digital input can be applied to modulate the output power of a

laser diode. Explain the circuit operation.

Problems Section 21-1 21-1

The total luminous flux striking a 4 cm? photocell at 7 m from a lamp is to be

80 mlm. Determine the required energy output from the lamp in watts. 21-2.

Calculate the total luminous flux striking the surface of a solar cell located 4.5 m

21-3

from a lamp with a 509 W output. The surface area of the solar cell is 5 cm?. Calculate the frequency of the light output from red, yellow, and green LEDs with the following peak wavelengths: 635 nm, 583 nm, 565 nm.

Section 21-2 21-4

An LED with Ip = 20 mA current and Vz = 1.4 V is to indicate when a 25 V supply is switched on. Sketch a suitable circuit and make all necessary calculations.

21-5

Two series-connected LEDs are to be controlled by a 2N3903 transistor with a

12 V supply and Vg = 5 V. The diode current is to be approximately 15 mA. Design a suitable circuit.

Chapter 21

21-6

Optoelectronic Devices

989

An op-amp Schmitt trigger circuit with Voc = +15 V is to have the state of its output indicated by LEDs. A green LED is to indicate high, and a red LED is to

indicate low. Design the circuit for 10 mA diode currents. Include reverse91-7

voltage protection diodes in series with each LED. The BJT-LED circuit in Fig. 21-5a has Vg = 5 V, Vcc = 20 V, and Mg min) = 40 for

Qs). Design the circuit to give a 20 mA LED current with Vp = 2 V.

Section 21-3 21-8

Calculate the maximum power used by a three-and-a-half digit seven-segment

LED display with a5 V supply and 10 mA LED currents. Determine the power dissipated in each LED series resistor if the LEDs have Vf = 1.4 V.

21-9

Determine the maximum power consumed by a three-and-a-half digit sevensegment LCD display with a 15 V peak square-wave supply and 1 ~A LCD segment currents.

Section 21-4 21-10 A

pnp

BJT

is

to

be

biased

on

when

the

level

of

illumination

on

a

photoconductive cell is greater than 100 Ix, and off when the cell is dark. A+5 V supply is to be used, and the BJT collector current is to be 10 mA when on. Design a suitable circuit to use a BJT with hpg = 50 and a photo-conductive cell

with the characteristics in Fig. 21-11. 21-11 An inverting Schmitt trigger circuit has Vec = +12 V and UTP/LTP = +5 V. The Schmitt output is to switch positively when the illumination level exceeds

30 Ix on a photo-conductive cell with the characteristics in Fig. 21-11. Design the

circuit,

and

estimate

the

light level

that

causes

the

output

to switch

negatively.

21-12 A photoconductive cell with the characteristics in Fig. 21-11 is connected in series with an 820 () resistor and a 12 V supply. Determine the illumination level when the circuit current is approximately 6.5 mA, and when it is 1.1 mA.

21-13 A photoconductive cell circuit for controlling the current in a LED (as in Fig. 21-16) has Vcc = 9 V, Ro = 3.3 kO, R3 = 270 Q. The photoconductive cell has a dark resistance of 100 kM, and Rc = 3 kO at 10 lx. Determine the LED current

at light levels of 3 lx and 30 Ix. 21-14 The circuit in Fig. 21-14a has Vcc = +5 V, Ri = 12 kQ, and a photoconductive cell with the specification in Fig. 21-12. Calculate the transistor maximum and

minimum base voltage at 10 lx.

Section 21-5 21-15 A photodiode with the illumination characteristics in Fig. 21-23 is connected in series with a resistance and a 1 V reverse-bias supply. The diode is to produce

a +0.2 V output when illuminated with 20 mW/cm?. Calculate the required series resistance value, and

determine

the device voltage

and current at a

15 mW/cm’ illumination level. 21-16 A photodiode with the characteristics in Fig. 21-23 is connected in series with a 1.2 V reverse-bias supply and a 100 1 resistance. Determine the resistance

offered by the photodiode 20 mW/cm?.

at illumination

levels

of 15

mW/cm?

and

$90

Electronic Devices and Circuits

21-17 Two photodiodes that each have a 100 2 series resistor are connected to a 0.5 V reverse-bias supply. A voltmeter is connected to measure the voltage difference between the diode cathodes. Assuming that each photodiode has the characteristics illustrated in Fig. 21-23, determine the voltmeter reading when the illumination level is 10 mW/cm?

on one diode and 15 mW/cm?

on

the other. 21-18 Six photodiodes with the characteristics in Fig. 21-23 are connected in series.

Determine the maximum output current and voltage at illumination levels of

15 mW/cm? and 12 mW/cm?. 21-19 A highway sign uses 6 V rechargeable batteries that supply an average current of 50 mA. The batteries are recharged from an array of solar cells, each with the characteristics in Fig. 21-25. The average level of sunshine is 50 mW/cm? for 10 hours of each 24-hour period. Calculate the number of solar cells required. 21-20 The roof of a house has an area of 200 m? and is covered with solar cells that are each 2cm X 2 cm. If the cells have the output characteristics shown in Fig. 21-25, determine how they should be connected to provide an output voltage of approximately 120 V. Take the average daytime level of illumination as 100 mW/cm7?. If the sun shines for an average of 12 hours in every 24 hours, calculate the energy in kilowatt-hours generated by the solar cells each day.

Section 21-6 21-21 The phototransistor circuit in Fig. 21-27b has a 25 V supply, and the device has the output characteristics in Fig. 21-29. Determine the collector resistance required to give Vcg = 10 V when the illumination level is 20 mW/cm?. 21-22 Estimate Vcg for the circuit in Problem 21-21 at a5 mW/cm’? illumination level.

If the phototransistor has the specification in Fig. 21-30, calculate the Vcr

variation produced by a +0.5 mW/cm? illumination change. 21-23 A phototransistor with the characteristics in Fig. 21-29 is connected in series with a 600 © relay coil. The coil current is to be 8 mA when the illumination level is 15 mW/cm7*. Determine the required supply voltage. Estimate the coil

current at 10 mW/cm?. 21-24 A phototransistor circuit for controlling an SCR (as in Fig. 21-32) is to be designed. The SCR has triggering conditions of Vg = 0.7 V and Ig = 50 pA, and the phototransistor

has

the specification in Fig. 21-30.

Calculate

suitable

resistor values if the SCR is to switch on when the light level drops to

5 mW/cm?. The supply voltage is Vcc = 12 V. Section 21-7 21-25 An optocoupler with the specification in Fig. 21-36 is to control a 12 mA load that has a 6 V supply. The input is a 10 V square wave connected via a resistor (R;). Determine a suitable resistance for Rj.

21-26 A25 V, 0.5 W lamp is to be switched on and off by an BJT circuit with Vec = 9 V and Ic = 6 mA. Design a suitable optocoupler circuit and estimate the required CTR. 21-27 An optocoupler circuit has its input connected via a 820 O resistor (Rj) to a pulse source. Its output transistor has a 5 V collector supply and a 470 0

Chapter 21

Optoelectronic Devices

991

emitter resistor (R2). The gate-cathode terminals of an SCR are connected

across R,. The SCR requires Vg = 1.1 V and Ic = 500 pA for triggering. If the

optocoupler has CTR = 40%, calculate the required

amplitude

of the pulse

input to trigger the SCR.

21-28 A optocoupler linear circuit, such as in Fig. 21-38, has Veci = 15 V, Vec2 = 25 V, vs = +0.1 V, Ri = 100 0, Rp = 1.2 kQ, R3 = 1.5 kM. Calculate the de and ac

output voltages and the overall voltage gain. The optocoupler has CTR = 30%. 21-29 An optocoupler switching circuit, as in Fig. 21-37, has Veci = 18 V, Vec2 = 3 V, Ri = 1.8 kO, Rp = 820 Q, and J, = 1 mA. Analyze the circuit to determine [f1, Ic, and CTR.

Section 21-8 21-30 A photomultiplier tube circuit as illustrated in Fig. 21-42a has the following components and voltage levels: R; through R7 = 4.7 kQ, Rg = 22 k0, cathode voltage Exx = ~—2.i kV, and anode supply voltage Epp = +100 V. Determine the suitable maximum

anode current, calculate the anode output

voltage, and determine the power dissipation in all resistors.

21-31 If the photomultiplier tube in Problem 21-30 is subject to 80 ps illumination pulses, determine suitable capacitor values for connecting in parallel with Rs,

R¢, and R; to stabilize the dynode voltages. 21-32 A photomultiplier tube with eight dynodes is to have its anode supplied with +1.5 kV and its cathode grounded. The dynodes are to be biased via a voltage divider connected between the anode supply and ground, and the anode is to be capacitor-coupled to the output. Draw

the circuit diagram

and calculate

suitable voltage divider resistor values if the maximum anode current is 3 mA. 21-33 The voltage divider designed for Problem 21-32 is to have the three resistors

closest to the anode replaced with Zener diodes. Specify suitable devices. 21-34 The circuit described in Problem 21-30 has capacitors connected in parallel with the three resistors closest to the anode. The capacitor values are Cs = 0.03 pF,

Co = 0.06 pF, and C7 = 0.12 pF If the input light level to the photomultiplier tube is pulsed, determine the maximum

pulse duration that should be used.

Section 21-9 21-35 Analyze the constant current circuit in Fig. 21-47a to determine the maximum and minimum laser diode output power. Assume that the device has the P,/Ir characteristics shown in Fig. 21-46b at 25°C. 21-36 A constant current circuit, as illustrated in Fig. 21-47a, is to be designed to

produce an output power adjustable from 4 mW to 6 mW. The diode has the P,/Ip characteristics shown in Fig. 21-46b and is operating at a temperature of

50°C. If the circuit has a 15 V supply, calculate suitable resistor values.

21-37 The laser diode constant power circuit in Fig 21-47b is to be used to stabilize the output power at 6 mW.

If the laser diode requires a forward current of

80 mA, and the photodiode current is 0.56 mA at P, = 6 mW, calculate the

required level of Vyet, and the amplifier output voltage.

992

Electronic Devices and Circuits

21-38 A constant power circuit, as illustrated in Fig. 21-47b, is to be designed to produce a5 mW output from a laser diode that requires Ip = 75 mA and has a 0.45 mA photodiode current at P, = 5 mW. The circuit is to operate from an 18 V supply. Select a suitable reference voltage and determine the required resistor values. 21-39 The circuit designed for Problem 21-38 is to be modulated by an analog input signal, as illustrated in Fig. 21-48a. Determine a suitable resistance for Rg, and

the required input voltage amplitude to modulate the laser diode forward current by +7.5 mA.

21-40 The automatic power control circuit analyzed in Ex. 21-16 is to be modified for digital modulation as shown

in Fig. 21-48b. If the collector current of Q> is

20 mA, calculate the change in Ip) to keep the output of D; stabilized at 4 mW. Assume that A; has an open-loop gain of 100 000.

Practice Problem 21-1.1

Answers

100W

21-1.2

5.13 x 10!4 Hz

21-1.3 21-2.1 21-2.2

0.73 mlx, 0.29 lm 2200,84V 2700,3900

21-3.1

1.84mW

21-4.2 21-4.3 21-5.1 21-5.2 21-6.1

33kQ04+2.2k0 301lx,151lx +0.19V 48 2.5 V,13.9V

21-4.1

21-6.2 21-7.1 21-7.2

422 A, 968 pA, 1.2mA

13mW/cm? 1500 9mA,+638mA,

(3.96 V to 13.9 V), (£0.27 V to £0.98 V)

21-81

7 xX (15kQ, 10 W)

21-8.2

(5.6 kQ, 10 W), (200 V, Izr < 30 mA < Iz)

21-9.1

920

21-9.2

+290 mV

CHAPTER 22 Miscellaneous

Devices

Objectives You will be able to:

1 Explain the construction and

operation of voltage-variable capacitor diodes (VVCs). Sketch

using thermistors for

temperature level detection. 5 Explain the construction and

typical VVC voltage/

operation of tunnel diodes.

capacitance characteristics, draw the equivalent circuits, and discuss typical VVC

Sketch typical forward and reverse characteristics for a tunnel diode, explain their shape, and identify the

parameters. 2 Design and analyze resonance circuits using VVCs for frequency tuning. 3 Discuss the construction and operation of thermistors, sketch

typical thermistor resistance/ temperature characteristics, and discuss typical thermistor parameters.

4 Calculate thermistor resistance

important points and regions of the characteristics. 6 Draw tunnel diode piecewise linear characteristics and analyze tunnel diode parallel

7 amplifier circuits. Explain the be: Seapine

characteristics, parameters, and applications of Schottky, PIN,

at various temperatures from the data sheet information.

and current-limiting diodes. Design and analyze circuits

Design and analyze circuits

involving these devices.

INTRODUCTION VVCs are pn-junction devices designed to produce a substantial change in junction capacitance when the reverse-bias voltage is adjusted. They can be applied to tune resonant circuits over a range of frequencies. The resistance of a thermistor changes significantly with change in temperature, so its major application is control of circuits that must respond to temperature change. The tunnel diode is a two-terminal negative-resistance device that can function as an oscillator, an amplifier, or a switch. Low forward voltage and fast turn-off time are features of the Schottky diode that make it suitable for preventing

994

Electronic Devices and Circuits

saturation in switching BJTs. The PIN diode behaves as a variable resistance at high frequencies, and the current-limiting diode is used in constant-current applications.

22-1

VOLTAGE-VARIABLE CAPACITOR DIODES

VVC Operation Voltage-variable capacitor diodes (VVCs) are also known as varicaps, varactors, and tuning diodes. Basically, a VVC is a reverse-biased diode, and its capacitance is the junction capacitance. Recall that the width of the depletion region at a pn-junction depends upon the reverse-bias voltage (Fig. 22-1). A large reverse-bias produces a wide depletion region, and a small reverse bias gives a narrow depletion region. The depletion region acts as a dielectric between two conducting plates; thus the junction behaves as a capacitor. The depletion layer capacitance (Cp,) is proportional to the junction area and inversely proportional to the width of the depletion region. Because the width of the depletion region is proportional to the reverse-bias voltage, C,, is inversely proportional to the reverse-bias voltage. This is not a direct proportionality; instead C,, is proportional to 1/V", where V is the reversebias voltage and n depends upon doping density. Depletion region width -— > Large reverse-bias Small reverse-bias

" Dielectric Conducting plates

Figure 22-1 A voltage variable capacitor diode (VVC) is essentially a . . . .

1 = VE

. . depletion region and reduces the

Reverse-bias

reverse-biased pn-junction. Increasing the reverse voltage widens the

capacitance.

Figure 22-2 shows the doping profiles for two types of VVC classified as abrupt junction and hyperabrupt junction devices. In the abrupt junction VVC, the semiconductor material is uniformly doped, and it changes abruptly

from. p-type to.n-type at the junction. The hyperabrupt junction device has the doping density increased. close to the junction. This increasing density produces a narrower depletion region, and so it results in a larger junction capacitance. It also causes the width of the depletion region to be more sensitive to bias, voltage variations; thus it produces the largest capacitance

Miscellaneous Devices

Chapter 22

Doping

995

Doping |

density | PtyPe

Fy | Devine

(————

"¥

densi a

Doping density

TEXY PE

density

(b) Hyperabrupt junction

(a) Abrupt junction

Doping profiles for abrupt junction and hyperabrupt junction

Figure 22-2 VCs.

change for a given voltage variation. VVCs are packaged just like ordinary low-current diodes. Equivalent Circuit The complete equivalent circuit for a VVC is shown in Fig. 22-3a, and a simplified version is given in Fig. 22-3b. In the complete circuit, the junction capacitance (Cj) is shunted by the junction reverse leakage resistance (Rj). The resistance of the semiconductor material is represented by Rs, the terminal inductance is Ls, and the capacitance of the terminals (or the device

package) is Cc. Because Ls is normally very small and ky is very large, the equivalent circuit can be simplified (Fig. 22-3b) to Rg in series with Cr, where Cr is the sum of the junction and terminal capacitances (Cr = Cy + Cc). The Q-factor for a VVC can be as high as 600 at a 50 MHz frequency. However,

since the Q-factor varies with bias voltage and frequency, it is used only as a figure of merit for comparing the performance of different VVCs. om

Ls

Rs

Cy

—O Rs

Ce

_\I }i-

Cr

Ry

(a) Complete equivalent circuit

(b) Simplified equivalent circuit

Figure 22-3 The complete equivalent circuit of a VVC has five components. The simplified circuit is made up of the semiconductor

resistance Rs and the total capacitance Cy.

Specification and Characteristics A wide selection of VVC capacitances is available, ranging approximately

from 6 pF to 700 pF. The capacitance tuning ratio (TR) is the ratio of Cy at a small

reverse

voltage to Cr at a large reverse voltage.

In the partial

specification for a VVC shown in Fig, 22-4, the tuning ratio is listed as C,/Cu1o. This is the ratio of the device capacitance at a 1 V reverse bias to that ata 10 V reverse bias. The 400 pF minimum capacitance (Cp) listed for a 1 V bias is

996)

Electronic Devices and Circuits

Typical VVC Specification

Cr Ve

=1V,f=1MHz

min

Ci /Ci9

max

400 pF

f=

1 MHz | Ve = 1

600 pF

Figure 22-4

QO

Vif = 1 MHz

14

200

Vmax)

TR¢max)

15V

100 nA | 200 mA

Teqnax)

Partial specification for a voltage-variable capacitor diode (VVC).

changed to 400 pF/14 when the bias is 10 V. The specification also lists the Qfactor, as well as maximum reverse voltage, reverse leakage current, and the

maximum forward current that can be passed when the device is forward biased. A typical graph of capacitance (Cr) versus reverse-bias voltage (VR) for a hyperabrupt junction VVC is reproduced in Fig. 22-5 together with the VVC circuit symbol. It is seen that Cr varies (approximately) from 500 pF to 25 pF when Vx is changed from 1 V to 10 V. It should be noted from the specification in Fig. 22-4 that the nominal capacitance has a large tolerance (400 pF to 600 pF), and this must be taken into account when the Cr/VR graphs are used. (pF)

1000 400 200

Cr

100

40 20

10 0

1

2

3

4

5

6

7

8

9

10

(V)

Figure 22-5 Capacitance/voltage characteristic for a hyperabrupt junction VVC and VVC circuit symbol.

Applications The major application of VVCsis as tuning capacitors to adjust the frequency of

resonance circuits. An example of this is the circuit shown in Fig. 22-6, which is an amplifier with a tuned circuit load. The amplifier produces an output at the

resonance frequency

of the tuned

circuit. The VVC (D;) provides

the

capacitance (Cr) of the resonant circuit, and this can be altered by adjusting the diode (reverse) bias voltage (Vp). So the resonance frequency of the circuit can

Miscellaneous Devices

Chapter 22

Figure 22-6

997

Amplifier stage with an LC tank circuit load.

The resonance frequency of the LC circuit can be varied by adjusting the VVC reverse-bias voltage.

be varied. C; is a coupling capacitor with a capacitance much larger than that of the VVC, and R> limits the VVC forward current in the event that it becomes forward biased.

Example 22-1 Determine the maximum and minimum resonance frequency for the circuit in Fig. 22-6. Assume that D, has the Cr/ Vz characteristic in Fig. 22-5.

Solution

ye

=

VecX Re

_

9V Xx 4.7kO

Dimin) “" R3 + Rat Rs

47k04+5k0

+ 47kO

=2.9V

2

_ Vec(R3 + Ry) _ 9V X (4.7kO + 5kO) Dimax)"Rg + Ra tRs 47k04+5k0 + 47kO ~6.1V

From Fig. 22-5, at Vp = 2.9 V, Cr

1

Foie) = SAV EGR)

250 pF:

_

1

2m V (00 mH & 250 pF)

= 1 MHz From Fig. 22-5, at Vp = 6.1 V, Cr 1

f (min) = Qa V(LCt) =~ 1.9 MHz

70 pF: 1

24V(100 pH X 70 pF)

998

Electronic Devices and Circuits

Practice Problem

a

oo

22-1.1 A tuned amplifier circuit as in Fig. 22-6 is to have a resonance

frequency adjustable from

MHz to 2.5 MHz. A 12 supply is used, cana he inductor (Li) is 80 1.5 H, the VVC (D;) has the V charac teristics in Fig. 22-5 and the specification in Fig. 22-4. Determine suitab le resistance values for Rs, Ra, and Rs.

22-2 THERMISTORS Thermistor Operation The word thermistor is a combination of thermal and resistor. A thermistor is

a resistor with definite thermal characteristics. Most thermistors have a negative temperature coefficient (NTC), but positive temperature coefficient (PTC) devices are also available. Thermistors are widely applied for measurement

and control of temperature, liquid level, gas flow, and so on.

Silicon and germanium are not normally used for thermistor manufacture, because larger and more predictable temperature coefficients are available with metallic oxides. Various mixtures of manganese, nickel, cobalt, copper,

iron, and uranium are pressed into desired shapes and sintered (or baked) ata

high temperature to form thermistors. Electrical connections are made either by including fine wires during the shaping process or by silvering the surfaces after sintering (see Fig. 22-7a). Thermistors are made in the shape of beads, probes, discs, washers, and so on (Fig. 22-7b). Beads may be glass-coated or enclosed in evacuated or gas-filled glass envelopes for protection against corrosion.

Thermistor material

Contacts

Encapsulating material

Contact leads

(a) Thermistor construction

(b) Some thermistor shapes

Figure 22-7 Thermistors are resistors that are very sensitive to temperature.

Chapter 22

Miscellaneous Devices

999

Characteristics and Specifications The

typical

shows

thermistor

that

the

resistance/ temperature

device

resistance

characteristic in Fig. 22-8 decreases substantially when its

(R)

temperature is raised. At 0°C, R ~ 1.5 kQ; and at 60°C, R70 ©. Current flow

through a thermistor causes power dissipation that can raise its temperature and

change

its resistance.

This

could

introduce errors in the application, so device currents are normally kept to a minimum. 10 000

thermistor

-——~

4000 =~

2000 |. R(Q)

40

=

a

—40 T (°C) Figure 22-8

Typical resistance/temperature characteristics for a negative

temperature coefficient (NTC) thermistor.

Figure 22-9 shows partial specifications for two thermistors with widely different resistance values. Both devices have the resistance specified at 25°C

as the zero power resistance. This, of course, means that there must be zero power dissipation in the thermistor to give this resistance value. The dissipation

constant

is

the

device

power

dissipation

that

can

raise

its

temperature through 1°C. The dissipation constant in both cases is specified Typical Thermistor Specifications

Zero power | Resistance resistance ratio _Thermistor |

at25°C

B

Maximum working | Dissipation

| 25°C/125°C | (0 to 50°C) | temperature |

Batra _-44002A

300:

15.15

3118

° 100°C

"44008

30k

29.15

3810

50°

constant

1 mW/°C ait, 8 mW in/°C instill

"| Powis Hquia

Figure 22-9 Partial specifications for two thermistors, one with a 300 0 25°C resistance, and the other with a 30 kO 25°C resistance.

1000

Electronic Devices and Circuits

as 1 mW/°C in still air, and 8 mW/°C in moving liquid. Thus, a thermistor located in still air conditions could have its temperature increased by 1°C if its current produces 1 mW of power dissipation. An indication of how much the thermistor resistance changes is given by the resistance ratio at 25/125°C. Clearly, with this ratio specified as 15.15, the resistance at 25°C is divided by 15.15 to determine the resistance at 125°C. Note that maximum working temperatures are listed for both devices. The resistance change with temperature is also defined by the constant beta ({),

this time for the range 0°C to 50°C. This constant is used in an equation that relates resistance values at different temperatures: R OE ge Ro

(# id i) T, To

(22-1)

In Eq. 22-1, R; is the resistance at temperature T,, and Rz is the resistance T). It is important to note that T, and T> are absolute (or Kelvin) temperature values: (°C + 273) K.

Example 22-2 Calculate the resistance of the 300 9 thermistor specified in Fig. 22-9 at temperatures of 20°C and 30°C. Solution For T = 20°C, and

Ty = 25°C

+ 273 = 298K

To = 20°C

+ 273 = 293 K Ry

From Eq. 22-1,

300 2

Ry = pBA/TI=1/T2) — _,3118(1/298-1/293) = 358 0

For T = 30°C, and

From Eq. 22-1,

Ty = 25°C

+ 273 = 298K

To = 30°C

+ 273 = 303 K

Ry 300 2 Ry = (BU/TI-1/T2) — ,3118(1/298—-1/303) = 252 ©

Applications Figure 22-10 shows

a thermistor connected

as a feedback

resistor in an

inverting amplifier circuit. (Note the device circuit symbol.) In this case, the thermistor is supplied with a constant current determined by R; and V;j. The

output voltage is directly proportional to the thermistor resistance, and so V, varies with temperature change.

Miscellaneous Devices

Chapter 22

Figure 22-10

ah The

“Vg circuit in Fig.

22-11

Use of an inverting

amplifier to produce a constant current through a thermistor.

oO

illustrates

1001

how

a thermistor

can

be

used

for

triggering a Schmitt circuit at a predetermined temperature. This could be air temperature or the temperature of a liquid or perhaps the temperature of some type of heating appliance. When the thermistor resistance (Rr) is increased by the device temperature decrease, the Schmitt input voltage is raised to the upper trigger point, causing the output to switch negatively.

Example 22-3 Calculate Vj for the Schmitt circuit in Fig. 22-11 at 25°C and at 28°C if the

thermistor is the 300 © device specified in Fig. 22-9.

Figure 22-11 Schmitt trigger circuit using a thermistor input stage for temperature level detection.

Solution At.25°C,

Rr = 300 0,

V; = Veco X Rr _ R, + Rr

5 VX 3000 47kQ

= 31.7mV For T = 28°C,

Ti = 25°C + 273 = 298K

and

Tz = 28°C + 273 = 301K

+ 300 0

1002

Electronic Devices and Circuits

rom F tom

—

Eq. 22-1,

Rk

3009

Rp = pAUL/TI-1/T2) —_,3118(1/298—1/301) = 2700

y, -VecX Rr i>

Ri+ Rr

__5V x 2700 = 47k9

+2700

= 28.6 mV

_ Practice Problems _ 22-2.1 Calculate the output voltage from the circuit in Fig. 22-10 at 25°C and

' 28°C if the 30 kM thermistor specified in Fig. 22-9 is used. 22-2.2 If the Schmitt circuit in Fig. 22-11 has UTP = 1 V, calculate a suitable resistance value for Rj for the circuit to trigger at 18°C. The thermistor _ used is'the ot Q, device specified in Fig. 22-9.

22-3

TUNNEL DIODES

Tunnel Diode Operation A tunnel diode (sometimes called an Esaki diode

Depletion region

after its inventor, Leo Esaki) is a two-terminal

negative resistance device that can be employed as an amplifier, an oscillator, or a switch. Recall from Chapter 1 that the width of the depletion region at a pn-junction depends

upon the doping density of the semiconductor

oo dsped _ p-type

(@) 4 heavily oop ef ver

material. Lightly doped material has a wide depletion

region,

whereas

heavily

oka depletion cred

doped

material has a narrow region. A tunnel diode uses very heavily doped semiconductor material, so the depletion region is extremely narrow. This is illustrated in Fig. 22-12 along with three tunnel diode circuit symbols.

The

depletion

region

is an

cross

it only

(b) Tunnel diode circuit symbols

insulator

because it lacks charge carriers, and usually charge

carriers

can

when

the

5

55.49 A tunnel diode

has a heavily doped pn-

junction, which results in a

external bias is large enough to overcome the very narrow depletion region. barrier potential. However, because the depletion region in a tunnel diode is so narrow, it does not constitute a large barrier to electron flow. Consequently,

a small forward

or reverse

bias

(not large enough to overcome the barrier potential) can give charge carriers sufficient energy to cross the depletion region. When this occurs, the charge carriers are said to be tunnelling through the barrier.

Chapter 22

Miscellaneous Devices

1003

When a tunnel diode junction is reverse-biased (negative on the p-side, positive on the n-side), substantial current flow occurs because of the

tunnelling effect (electrons moving from the p-side to the n-side). Increasing levels of reverse-bias voltage produce more tunnelling and a greater reverse current. So, as shown in Fig. 22-13, the reverse characteristic of a tunnel diode is linear, just like that of a resistor. Negative resistance region

it bp eT

Tht

HA Jae

:

i

tr} |

|

Forward

iH _|

characteristi¢

Ip

Si Ep

4

Reverse | characteristic rt

Figure 22-13 Tunnel diode characteristics. The current increases to a peak level (Ip) as the forward bias is increased, and then falls off to a valley current (Jy) with

increasing bias voltage.

A forward-biased

tunnel diode initially behaves

like a reverse-biased

device. Electron tunnelling occurs from the n-side to the p-side, and the forward current (Ip) continues to increase with increasing levels of forward voltage (Ep). Eventually, a peak level of tunnelling is reached, and then further increase in Ep actually causes Ip to decrease. (See the forward

characteristic in Fig. 22-13.) The decrease in Ip with increasing E continues until the normal process of current flow across a forward-biased junction begins to take over when the bias voltage becomes large enough to overcome the barrier potential. Ip now starts to increase with increasing levels of Er, so that the final portion of the tunnel diode forward characteristics is similar to that for an ordinary pn-junction. The shape of the tunnel diode characteristics

can be explained in terms of energy band diagrams for the semiconductor material.

Characteristics and Parameters

Fig. 22-14. Consider the typical tunnel diode forward characteristics shown in

gnized on the The peak current (Ip) and valley current (Iy) are easily reco of [Ip before the s level and minimum forward characteristic as the maximum

peak voltage (Vp) is the level of junction is completely forward-biased. The

1004

Electronic Devices and Circuits

Negative resistance region

Figure 22-14 Typical forward characteristic for a tunnel diode. Note that the negative resistance region exists between forward-

bias voltages of approximately 50 mV and 325 mV.

forward bias voltage (Ep) corresponding to Ip, and the valley voltage (Vy) is the Ex level at Iy. Vz is the forward voltage drop when the device is completely forward-biased. The dashed line at the bottom of the forward characteristic shows the characteristic for an ordinary forward-biased diode. It is seen that this joins the tunnel diode characteristic as Vp is approached. When a voltage is applied to a resistance, the current normally increases as the applied voltage is increased. Between Ip and Iy on the tunnel diode characteristic, Ip actually decreases as Ey is increased. So this region of the characteristic is named the negative resistance region, and the negative resistance (Rp) of the tunnel diode is its most important property. The negative resistance value can be determined as the reciprocal of the slope of the characteristic in the negative resistance region. From Fig. 22-14, it can be seen that the negative resistance is Rp = AVy/Alg, and the negative

conductance is Gp = Alp/AVz. If Rp is measured at different points on the negative resistance portion of the characteristic, slightly different values will be obtained at each point because the slope is not constant. Therefore, Rp is usually specified at the centre of the negative resistance region. Figure 22-15 lists typical tunnel diode parameters. Typical Tunnel Diode Parameters

Ip(mA)

| Ve(mV) |

1to 100. | Figure 22-15

50 to 200

Iv (mA)

Vy (nV)

0.1 to 5

350. to.500

Ve (V)

Rp (Q)

Q,5to1 |. =10 te —200

Tunnel diode specification data showing the range of parameters.

Chapter 22 = Miscellaneous Devices

1005

It is shown in Chapter 2 that a straight-line approximation of diode characteristics can sometimes be conveniently employed. For a tunnel diode, the piecewise linear characteristics can usually be constructed from data

provided by the device manufacturer.

Example 22-4 Construct the piecewise linear characteristics and determine Rp for a 1N3712

tunnel diode from the following data: Ip = 1 mA, ly = 0.12 mA, Vp = 65 mV, Vy = 350 mV, and Vp = 500 mV at Ip = Ip.

Solution Refer to Fig. 22-16. Plot point 1 at

Ip=1mA

and

Vp=65mV

Plot point 2 at

Iyv=012mA

and

Vy = 350mV

(mA)

12}

—________—

0.8

5

htt

0.2 | vy —}--74--0 ! 0 100

(mV)

Vp Figure 22-16

Piecewise linear characteristics for a tunnel diode,

drawn from information provided on the device specification.

Draw the first portion of the characteristic from the zero point to point 1. Draw the negative resistance portion between points 1 and 2. Plot point 3 at

Ip=Ip

and

Vp=500mV

Draw the final portion of the characteristics at the same slope as the line

between point 0 and point 1. Draw the horizontal part of the characteristic from point 2 to the final portion.

AV,

350mV—65mV

KK

Rp= a7 > =GmA —0.12mA) = -3240

1006

Electronic Devices and Circuits

Parallel Amplifier For operation as an amplifier, a tunnel diode must be biased to the centre of

its negative resistance region. Figure 22-17a shows the basic circuit of a tunnel diode parallel amplifier. Load resistor Ry, is connected in parallel with diode D, and supplied with current from voltage source Eg and signal source e;. Figure 22-17b uses the tunnel diode piecewise linear characteristics to show the de conditions of the diode when the signal voltage is zero (e; = 0) and when e, = +100 mV. The operation of the circuit is explained by the analysis in Ex. 22-5, which also demonstrates that a parallel amplifier has current gain but no voltage gain.

Example 22-5 Assuming that Eg and e, have zero source resistance, calculate the current gain and voltage gain for the tunnel diode parallel amplifier in Fig. 22-17a. The device piecewise linear characteristics are given in Fig. 22-17b. IB

Eg

Ip 1

lL L

|

200 mV

R

ED goa +100

= @ mV

Eri

D, (a) Basic parallel amplifier circuit

0

0

100

Ep —>

200 {

300

400

> (mV)

Vig

(b) Circuit current and voltage levels

Figure 22-17

Abasic tunnel diode parallel amplifier has a load

resistance in parallel with the diode and the (seriesconnected) bias and signal sources applied directly to the

diode and load.

Miscellaneous Devices

Chapter 22

Solution

When e, = 0:

Epg = Eg = 200 mV (point Q on Fig. 22-17b) Ipg = 2mA

At the Q-point,

Erto = Ex = 200 mV a ERE _ 200mV re 800 RL. LO

Also,

=25mA

+ Ip = 2.5mA+ 2mA Iso = In. =45mA When

e, =

+100 mV:

Eg + es = 200 mV

+ 100 mV

= 300 mV

Ep = Era) = 300 mV (point A on Fig. 22-17b) Ipiay = 1 mA

and. Also,

I

Be)

Eryay

oo

=

OR

=

300mV

80 O

= 3.75 mA

Tpay = Iria) + Inia) = 3.75 mA + 1 mA = 4.75 mA When e; = —100 mV: Eg + e, = 200 mV — 100 mV = 100 mV

Ep = Erp) = 100 mV (point B on Fig. 22-17b) Ip)

and

Also,

I

=3mA =

RL) ~

Erte)

——

Ry

=

= 1.25mA

100 mV

80 2

‘

In) = Ire) + Inq) = 1.25 mA + 3mA = 4.25mA

Total load current change: Alet = Irwa) — Inve) = 3.75 mA — 1.25 mA =2.5mA

1007

1008

Electronic Devices and Circuits

Total signal current change: Alg = Ipca) — Ip) = 4.75 mA

— 4.25 mA

= 0.5mA Teak Aly _= 2.5mA Ay = Alp,

i Current gain:

=5 AE

= BY

Ap ekes

Voltage gain:

+100 mV

sd

The current gain equation for a tunnel diode parallel amplifier can be shown to be

A = >

(22-2)

Note that Rp is already taken as negative in Eq. 22-2, so that only the absolute value should be used in calculating Aj. For Rp= 100 0 and R;= 80 Q, as in Ex. 22-5, 100

“= T00-800~° From Eq. 22-2, it can be seen that when Ry, > Rp, Aj < 1; and when R;, = Rp, Aj = ©. A current gain of infinity means that the circuit is likely to oscillate. For maximum stable current gain, R, should be

selected to be just slightly less than Rp. Figure 22-18 shows the circuit of a practical tunnel diode parallel amplifier. The signal voltage e, and load resistor Ry are capacitor-coupled to the diode, while dc bias is provided by source voltage Ex and voltage divider

R, and Ry». Inductor L; and capacitor C; isolate the bias supply from ac signals.

Ry

we

—VWy— 2.2kO

Ez

>

Rvy

Ry

470

.

C3

1J

| Omi oc Pe

imi

0.3 pF

Goin vy.

.

Ry,

300 0

—

Figure 22-18

Ina practical sc

ail

amplifier circuit, the load and signal

source are capacitor-coupled to the tunnel diode.

e

°

Chapter 22 _— Miscellaneous Devices

1009

A tunnel diode series amplifier can be constructed. In this case the device

is connected in series with the load, and voltage amplification is obtained instead of current amplification. Oscillators and switching circuits can also be constructed with tunnel diodes.

Practice Problem 22-3.1 Draw the dc and ac equivalent circuits for the tunnel diode parallel amplifier in Fig. 22-18. Calculate the current gain.

22-4 SCHOTTKY, PIN, AND CURRENT-LIMITING

DIODES

The Schottky Diode The

Schottky

diode

(also known

as a hot-carrier

diode)

has

a metal-to-

semiconductor junction instead of a pn-junction. This gives the device a lower forward voltage drop and faster reverse recovery than a pn-junction diode. Figure 22-19a illustrates the basic structure of the device. An n-type epitaxial layer is created on a low-resistance n-type substrate (see Chapter 7), and

a metal

film

(the barrier metal)

is deposited

on

the epitaxial

layer.

Additional layers of metal are deposited on the outer surfaces for anode and cathode connections, as illustrated. The type of metal used at the junction affects the device performance. The metal side of the junction has an abundance of free electrons, and

there are no holes in either the metal or the n-type material. Thus there are no minority charge carriers and there is virtually no depletion region. This means that when the junction is switched from forward to reverse bias, there are no charge carriers to be withdrawn from a depletion region (see Section 2-6), and there is no charge carrier recombination. Consequently, the reverse recovery time is extremely small—on the order of picoseconds. The typical forward characteristic in Fig. 22-19b show a voltage drop (Vp) ranging from 0.2 V at a 10 mA forward current to about 0.4 V at 1 A. As illustrated, the reverse current is approximately 0.5 mA at 25 °C, which is substantially greater than for most pn-junction diodes. Another disadvantage

is that the 50 V typical reverse breakdown voltage is lower than for other types of diodes. The two important advantages of Schottky diodes over pn-junction diodes are the lower forward voltage drop and the much faster turn-off Figure 22-20 shows the use of a Schottky diode in an application where of these advantages are employed: clamping a switched BJT to keep it saturating. Without the diode, Q; saturation voltage would be Vexieaty¥

time. both from 0.2 V,

which gives Vac ¥ 0.5 V (Fig. 22-20a). If D, in Fig. 22-20b has Vr = 0.2 V, then

the collector is clamped to 0.2 V below the base voltage. Thus, the minimum

1010

Electronic Devices and Circuits

Anode terminal

metal Schottky

n-type

barrier

epitaxial ——" layer

metal n-type

—

substrate Cathode terminal metal

(a) Basic structure of a Schottky diode (mA) 1000 4 ee

|

100

Tp

6 @— OUTPUT

Q15

R10 50

017 a6

a10

OFFSET NULL

:

5_ OFFSET iy

. Ri 1K

020

Q22

ait

Qs 6S RS. : & 50K

SR2 S1K :

R4 5K

4 50K :

:

Ri1

50

=