Electronic devices and circuits [3 ed.] 9781259006418, 1259006417

Table of contents :
Title
Contents
1 Physical Properties of Elements
2 Passive Circuit Components
3 Electron Ballistics
4 Semiconductor Diodes
5 Special Diodes
6 Biplor Junction Transistor
7 Field Effect Transistor
8 Thyristors
9 Midband Analysis of Small Signal Amplifiers
10 Multistage Amplifiers
11 Frequency Response of Amplifiers
12 Large Signal Amplifiers
13 Tuned Amplifiers
14 Feedback Amplifiers
15 Oscillators
16 Wave Shaping and Multivibrator Circuts
17 Blocking Oscillators and Time Base Generators
18 Rectifiers, Filters and Power Supplies
19 Integrated Circuit Fabrication
20 Operational Amplifiers
21 Transducers
22 Optoelectronic Devices
23 Measuring Instruments
24 Digital Circuits
25 Memories and Microprocessors
Appendix A
Appendix B
Index

Citation preview

S Salivahanan is the Principal of SSN College of Engineering, Chennai. He obtained his B.E. degree in Electronics and Communication Engineering from PSG College of Technology, Coimbatore, M.E. degree in Communication Systems from NIT, Trichy, and Ph.D. in the area of Microwave Integrated Circuits from Madurai Kamaraj University. He has over three decades of teaching, research, administration and industrial experience, both in India and abroad, with stints at NIT, Trichy, A.C. College of Engineering and Technology, Karaikudi; R.V. College of Engineering, Bangalore; Dayananda Sagar College of Engineering, Bangalore; Mepco Schlenk Engineering College, Sivakasi; and Bannari Amman Institute of Technology, Sathyamangalam. Dr Salivahanan served as a mentor for the M.S. degree under the distance-learning programme offered by Birla Institute of Technology and Science, Pilani. He has industrial experience as Scientist/Engineer at Space Applications Centre, ISRO, Ahmedabad; Telecommunication Engineer at State Organisation of Electricity, Iraq; and Electronics Engineer at Electric Dar Establishment, Kingdom of Saudi Arabia. He is the author of 26 popular books which include Basic Electrical, Electronics and Computer Engineering; Electronic Devices and Circuits and Linear Integrated Circuits, all published by TMH, and Digital Signal Processing by TMH and McGraw-Hill International which has also been translated into Mandarin, the most popular version of the Chinese language. He has published several papers at national and international levels. Professor Salivahanan is the recipient of Bharatiya Vidya Bhavan National Award for Best Engineering College Principal for 2011 from ISTE, and IEEE Outstanding Branch Counsellor and Advisor Award in the Asia-Pacific region for 1996–97. He was the Chairman of IEEE Madras Section for two years, 2008 and 2009, and Syndicate Member of Anna University. He is a Senior Member of IEEE, Fellow of IETE, Fellow of Institution of Engineers (India), Life Member of ISTE and Life Member of Society for EMC Engineers. He is also a member of IEEE Societies in Microwave Theory and Techniques, Communications, Signal Processing, and Aerospace and Electronics. N Suresh Kumar is the Principal of Velammal College of Engineering and Technology, Madurai. He received his B.E. degree in Electronics and Communication Engineering from Thiagarajar College of Engineering, Madurai; M.E. degree in Microwave and Optical Engineering from A.C. College of Engineering Technology, Karaikudi; and Ph.D. degree in the field of EMI/EMC from Madurai Kamaraj University. He has over two decades of teaching, administration and research experience and has authored 8 books, all published by TMH. He has published and presented many research papers in international journals and conferences. His areas of interest include Microwave Communication, Optical Communication and Electromagnetic Compatibility. He is a life member of IETE and ISTE.

S Salivahanan Principal SSN College of Engineering Chennai, Tamil Nadu N Suresh Kumar Principal Velammal College of Engineering and Technology Madurai, Tamil Nadu

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Foreword Preface

xv xvii

1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8

Introduction 1 Atomic Structure 1 Hydrogen Atom 2 Bohr Atom Model 3 Atomic Energy Level Diagram 5 Electronic Configuration of Elements 6 Energy-Band Theory of Crystals 8 Energy-Band Structures and Conduction in Insulators, Semiconductors and Metals 10 1.9 Practical Semiconductor Materials 13 1.10 Electron Emission from Metals 13 Review Questions 15 2.1 2.2 2.3 2.4

Introduction 16 Resistors 16 Capacitors 23 Inductors 42 Review Questions 45

3.1 Introduction 47 3.2 Charged Particles 47 3.3 Force, Field Intensity, Potential, and Energy 47

3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12

Two-Dimensional Motion of Electron 50 Force in a Magnetic Field 55 Motion in a Magnetic Field 55 Parallel Electric and Magnetic Fields 58 Perpendicular Electric and Magnetic Fields 59 Electrostatic Deflection in Cathode Ray Tube 62 Magnetic Deflection in Cathode Ray Tube 66 Magnetic Focusing 68 Comparison between Electric and Magnetic Deflection Systems 69 Review Questions 70

4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23 4.24

Introduction 72 Classification of Semiconductors 72 Conductivity of Semiconductor 75 Energy Distribution of Electrons 76 Carrier Concentration in Intrinsic Semiconductor 78 Mass-Action Law 83 Properties of Intrinsic Semiconductors 89 Variation in Semiconductor Parameters with Temperature 89 Drift and Diffusion Currents 91 Carrier Life Time 93 Continuity Equation 95 Theory of PN Junction Diode 98 Energy Band structure of Open Circuited PN Junction 105 Quantitative Theory of PN Diode Currents 107 Diode Current Equation 110 Ideal Versus Practical–Resistance Levels (Static and Dynamic) 112 Transition or Space Charge (or Depletion Region) Capacitance (CT ) 116 Diffusion (or Storage) Capacitance (CD) 119 Temperature Dependence of V-I Characteristics of Diodes 120 Junction Diode Switching Characteristics 124 Breakdown in PN Junction Diodes 127 Diode as a Circuit Element 128 Piecewise Linear Diode Model 131 PN Diode Applications 132 Review Questions 132

5.1 Introduction 135 5.2 Zener Diode 135

5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14

Backward Diode 138 Varactor Diode 138 Step Recovery Diode 139 Point-Contact Diode 140 Metal–Semiconductor Junctions 140 Tunnel Diode 147 Gunn Diode 150 Impatt Diode 152 PIN Diode 154 PIN Photodiode 155 Avalanche Photo Diode (APD) 155 Laser Diode 156 Review Questions 157

6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13

Introduction 159 Construction 159 Transistor Biasing 159 Operation of NPN Transistor 160 Operation of PNP Transistor 161 Types of Configuration 163 Transistor as an Amplifier 171 Large signal, d.c. and Small Signal CE values of Current Gain 171 Breakdown in Transistors 181 Ebers–Moll Model 183 Bias Stability 184 Methods of Transistor Biasing 191 Bias Compensation 214 Review Questions 217

7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10

Introduction 219 Construction of N-Channel JFET 219 Operation of N-Channel JFET 220 Characteristic Parameters of the JFET 222 Expression for Saturation Drain Current 226 Slope of the Transfer Characteristic at IDSS 227 Comparison of JFET and BJT 228 Applications of JFET 229 Metal Oxide Semiconductor Field Effect Transistor (MOSFET) 229 Enhancement MOSFET 229

7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.22

Depletion MOSFET 231 Comparison of MOSFET with JFET 233 Handling Precautions for MOSFET 233 Comparison of N- with P-Channel MOSFETs 235 Comparison of N- with P-Channel FETs 235 Use of JFET as Voltage-Variable Resistor 235 Applications of MOSFET in CMOS Circuits 236 Advantages of BJT over MOSFET 237 Biasing the FET 238 Biasing the MOSFET 241 Charge Transfer Devices (CTDs) 251 Review Questions 255

8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10

Introduction 257 PNPN Diode (Shockley Diode) 257 SCR (Silicon Controlled Rectifier) 258 Thyristor Ratings 260 Rectifier Circuits using SCR 260 LASER (Light Activated SCR) 265 TRIAC (Triode a.c. Switch) 265 DIAC (Diode a.c. Switch) 267 Gate Turn-Off (GTO) Thyristors 267 Thyristor Protection 271 Review Questions 273

9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 9.12 9.13 9.14

Two-Port Devices and Network Parameters 274 The Hybrid Model for Two-Port Network 277 Analysis of a Transistor Amplifier Circuit using h-Parameters 280 Simplified CE Hybrid Model 288 Analysis of CE Configuration using Approximate Model 289 Analysis of CC Amplifier using the Approximate Model 292 Analysis of CB Amplifier using the Approximate Model 294 The “re” Model of Transistor 298 BJT Amplifiers 302 Single Stage Amplifiers 303 Small Signal Analysis of Single Stage BJT Amplifiers 307 Distortion in Amplifiers 332 Miller’s Theorem and its Dual 333

9.15 9.16 9.17 9.18

Design of Single Stage RC Coupled Amplifier using BJT 334 FET Amplifiers 340 The FET Small-Signal Model 346 Differential Amplifiers 348 Review Questions 370

10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9

Introduction 373 Different Coupling Schemes used in Amplifiers 373 General Analysis of Cascade Amplifier 376 Choice of Transistor Configuration in Cascade Amplifier Two Stage RC Coupled Amplifier 386 Transformer Coupled Amplifier 398 Direct Coupled (d.c.) Amplifiers 404 Darlington Amplifier 407 Cascode Amplifier 413 Review Questions 416

11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 11.13 11.14 11.15

12.1 12.2 12.3 12.4 12.5

385

Introduction 418 Logarithms 418 Decibels 419 General Shape of Frequency Response of Amplifiers 422 General Frequency Considerations (Low Frequency Analysis) 424 Transient Response 428 Low Frequency Response of Transistor Amplifier 430 Effect of Coupling Capacitor CC on Low Frequency Response 434 High Frequency Model for a Transistor 435 Emitter Follower at Higher Frequencies 450 FET Model at High Frequency 453 Frequency Response of FET Amplifier 457 Frequency Response of Multistage Amplifiers 458 RF Amplifiers 460 Video Amplifiers 460 Review Questions 465 Introduction 466 Classification Based on Biasing Condition 466 Class A Large Signal Amplifiers 467 Second Harmonic Distortion 468 Higher-Order Harmonic Generation 470

12.6 12.7 12.8 12.9 12.10 12.11 12.12 12.13 12.14 12.15 12.16 12.17 12.18 12.19

Transformer Coupled Class A Audio Power Amplifier 471 Efficiency of Class A Amplifiers 473 Class B Amplifier 476 Efficiency of Class B Amplifier 476 Push-Pull Amplifier (Class-B) 478 Distortion in Power Amplifiers 479 Complementary Symmetry (Class B) Push-Pull Amplifier 480 Phase Inverters 483 Class AB Amplifier 484 Class C Power Amplifier 484 Class D Amplifier 486 Class S Amplifier 487 MOSFET Power Amplifiers 488 Thermal Stability and Heat Sink 489

13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 13.10

Introduction 493 Q-Factor 494 Small Signal Tuned Amplifiers 497 Effect of Cascading Single Tuned Amplifiers on Bandwidth 512 Effect of Cascading Double Tuned Amplifiers on Bandwidth 513 Stagger Tuned Amplifiers 514 Comparison of Tuned Amplifiers 515 Large Signal Tuned Amplifiers 516 Stability of Tuned Amplifiers 519 Neutralization 521 Review Questions 529

14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 14.9 14.10 14.11

Introduction 530 Classification of Basic Amplifiers 530 Basic Concept of Feedback 532 Transfer Gain with Feedback 535 General Characteristics of Negative-feedback Amplifiers 536 Effect of Negative Feedback on Input Resistance 545 Effect of Negative Feedback on Output Resistance 548 Method of Identifying Feedback Topology and Feedback Factor 553 Voltage-Series Feedback 553 Current-Series Feedback 561 Current-Shunt Feedback 566

14.12 Voltage-Shunt Feedback 570 14.13 Stability of Feedback Amplifier 574 Review Questions 576 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 15.9 15.10 15.11 15.12 15.13 15.14 15.15 15.16 15.17 15.18 15.19 15.20 15.21

16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8

Introduction 578 Classification of Oscillators 578 Conditions for Oscillation (Barkhausen Criterion) 579 General form of an LC Oscillator 580 Hartley Oscillator 582 Colpitts Oscillator 585 Clapp Oscillator 590 Franklin Oscillator 591 Armstrong Oscillator 591 Tuned Collector Oscillator 592 RC Oscillators 593 RC Phase-shift Oscillator using FET 603 Wien-Bridge Oscillator 605 Twin-T-Oscillator 607 Crystal Oscillators 609 Miller Oscillator 612 Pierce Crystal Oscillator 612 Frequency Range of RC and LC Oscillators 612 Frequency Stability of Oscillator 613 Negative-Resistance Oscillators 614 Oscillators using FET 614 Review Questions 616 Introduction 618 Waveform Shaping Circuits 618 Diode Clippers 626 Diode Comparator 638 Clampers 638 Multivibrators 641 Triggering Methods for Bistable Multivibrators 659 Schmitt Trigger 660 Review Questions 664

17.1 Introduction 668 17.2 UJT (Unijunction Transistor) Relaxation Oscillator 668

17.3 17.4 17.5 17.6 17.7 17.8

Pulse Transformers 672 Blocking Oscillator 681 Free Running Blocking Oscillator 681 Triggered Blocking Oscillator 686 Time Base Circuits 691 Linearization Through Adjustment of Driving Waveform 694 Review Questions 696

18.1 Introduction 698 18.2 Linear Mode Power Supply 698 18.3 Switched Mode Power Supply (SMPS) 750 Review Questions 758 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 19.10 19.11 19.12 19.13 19.14 19.15

20.1 20.2 20.3 20.4 20.5 20.6 20.7 20.8

Introduction 761 Manufacturing Processes of Monolithic ICs 763 Construction of a Monolithic Bipolar Transistor 771 PNP Transistors 775 Schottky Barrier Diode 777 Schottky Transistor 778 Monolithic Diodes 779 Integrated Resistors 779 Monolithic Capacitors 782 Inductors 782 Transformation of a Hypothetical Electronic Circuit into Monolithic Form 782 Fabrication of Field Effect Transistors 782 Thin and Thick Film Technology 789 Gallium Arsenide Devices 791 Recent Trends in IC Technology 795 Review Questions 796 Introduction 798 Ideal Operational Amplifier 798 Operational Amplifier Stages 799 Operational Amplifier Parameters 801 Equivalent Circuit of Op-Amp 806 Ideal Voltage Transfer Curve 807 Open-Loop Op-Amp Configurations 807 Closed-Loop Op-Amp Configurations 809

20.9 20.10 20.11 20.12

Bandwidth with Feedback 812 Noise 813 Frequency Response and Compensation 814 Op-Amp Applications 816 Review Questions 844

21.1 21.2 21.3 21.4 21.5 21.6 21.7 21.8 21.9 21.10 21.11 21.12 21.13

Introduction 846 Capacitive Transducer 848 Inductive Transducer 849 Linear Variable Differential Transformer (LVDT) 849 Oscillation Transducer 850 Potentiometric Transducer 850 Electrical Strain Gauges 851 Resistance Thermometer 853 Thermistor 854 Thermocouple 855 Hall Effect 856 Piezoelectric Transducer 858 Photoelectric Transducer 859 Review Questions 860

22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 22.9 22.10 22.11 22.12 22.13

Introduction 861 Spectral Response of Human Eye 862 Photoconductive Sensors 863 Photovoltaic Sensors 869 Photoemissive Sensors 871 Light Emitters 874 Liquid Crystal Display (LCD) 876 Nixie Tube 878 Alphanumeric Displays 880 LCD Panels 881 Plasma Display Panels 884 Optocoupler 885 Fiber Optics 887 Review Questions 890

23.1 Introduction 892 23.2 Cathode Ray Oscilloscope (CRO) 893 23.3 Ammeter 901

23.4 23.5 23.6 23.7 23.8 23.9 23.10 23.11 23.12 23.13 23.14 23.15 23.16

d.c. Voltmeter 903 Vacuum Tube Voltmeter (VTVM) 905 Digital Voltmeter 906 Ohmmeter 908 Digital Multimeter (DMM) 911 Measurement of R, L, C and Q 912 Frequency Meter 920 Time Meter 921 Energy Meter 922 Power Meter 923 Watt Meter 924 Spectrum Analyser 925 Distortion Meter 927 Review Questions 929

24.1 24.2 24.3 24.4 24.5 24.6 24.7 24.8 24.9 24.10 24.11 24.12 24.13

Introduction 931 Number System 931 Binary Arithmetic 936 1’s and 2’s Complements 939 Binary Coded Decimal 944 Boolean Algebra 946 Logic Gates 955 Combinational Logic Design 963 Karnaugh Map Representation of Logical Functions 964 Some Common Combinational Circuits 967 Sequential Circuits 976 A/D and D/A Converter Circuits 987 Logic Families 991 Review Questions 999

25.1 25.2 25.3 25.4

Introduction 1004 Semiconductor Memories 1004 Introduction to Microprocessors 1011 Introduction to Computers 1028 Review Questions 1028

It gives me immense pleasure to write a foreword for Electronic Devices and Circuits authored by Prof. S Salivahanan, and Prof. N Suresh Kumar of Mepco Schlenk Engineering College, Sivakasi, whom I have known very well for many years. Electronics has made rapid advances over the last few decades. Its importance has become more specific with rapid development of solid state devices and circuits. Electronic Devices and Circuits is one of the important core subjects in the field of Electronics, Electrical, Computer Science, Instrumentation and Mechanical Engineering. There has been an increase in the demand for a suitable textbook on this subject. The contents of the book are presented in a simple, precise and systematic manner. Numerous solved examples, self-explanatory sketches and a large number of exercise problems with answers have been presented in each chapter to aid conceptual understanding of the subject. This is an outcome of several years of teaching experience of the authors. Professor S Salivahanan has vast experience in teaching various courses in the industry and engineering colleges, both in India and abroad. Prof. Suresh Kumar too has considerable experience in teaching the subjects over a number of years. Having been myself a teacher in the field of Electronics and Communication Engineering for more than three decades, I am sure that this book will enrich students’ knowledge in the subject and would be welcomed by teachers and students of all engineering institutions. I strongly recommend this book to every Electronics, Electrical, Computer Science, Instrumentation and Mechanical Engineering student and wish the authors a grand success. DR P BALAKRISHNAN Director of Technical Education Government of Tamil Nadu Chennai

Explosive development and exciting progress have occurred in the field of electronics in the past few decades. A large number of solid-state devices and integrated circuits incorporating millions of active devices on a single chip have been invented. The past four decades have witnessed several unprecedented and exciting developments in the field of electronics. Hence, Electronic Devices and Circuits has become an important core subject in the field of Electronics, Electrical, Computer Science, Instrumentation and Mechanical Engineering. The study of electronic devices and circuits provides an opportunity to explore the operation of electronic devices, mainly diodes and transistors, two of the most important building blocks in electronic circuits. A single textbook covering all aspects of semiconductor devices and circuits satisfying the requirements of engineering college teachers and students is the need of the day. We have made a sincere attempt to bring out such a textbook.

The text is based on a series of lecture courses given to electronics, electrical and computer engineering undergraduates in their first, second and (part of) third years and, hence, the coverage of the subject has been organised in a more logically acceptable manner. The language used in explaining the various concepts is extremely simple. Since a proper understanding of the subject would involve a serious attempt to solve a variety of problems, a wide variety of problems with step-by-step solutions are provided for every concept. The third edition has been revised further and a number of new topics, solved examples and questions have been added. This text gives detailed description of the operation and characteristics of modern electronic devices. The revised edition contains descriptions on important topics like Filters and Regulators, MESFET, MISFET, Small Signal Amplifiers LDR and Photodiodes for enhanced coverage.

The book will serve the purpose of a text to the engineering students of degree, diploma, AMIE and graduate IETE courses and be a useful reference for those preparing for competitive examinations. Also, it will meet the pressing need of interested readers who wish to gain a sound knowledge and understanding of the principles of electronic devices and circuits. Practicing engineers will find the content of significant relevance in their day-to-day functioning.

Prerequisite knowledge for this course includes exposure to complex numbers, differential equations and a background in calculus. Students wishing to continue pursuing this subject can later opt for advanced courses in Analog Electronics, Digital Electronics, Electromagnetic Field Theory, Network Analysis and Synthesis, VLSI and MPs.

Contents span the entire sequence of courses on Electronics Focus on discussions on device operations and analyses Exceptional coverage of Oscillators, Frequency Analysis and Power Amplifiers Discussion on h-parameters of almost all biasing techniques New to this Edition: Colour Coding of Capacitors Cycloidal Path, Cycloidal Helical Motion, Straight Line Path in Perpendicular Electric and Magnetic Fields Temperature Dependence on V-I Characteristics of Diodes Zener Resistances and Zener Diode Ratings Effect of Temperature on Zener Diode Compensation Against Variation in VBE and ICO Derivation for Pinch-off Voltage, VP Applications of MOSFET in CMOS Circuits and Fixed Bias Fixing the Q-point and Fixed Bias in Biasing the FET Derivation of equations for Input Impedance, Output Impedance, Voltage Gain and Current Gain of a CC Amplifier or Emitter Amplifier Design of Single-stage RC coupled amplifier using BJT Logarithms and Decibels Hybrid Conductances and Hybrid Capacitances Phase Inverters Class AB Amplifiers Class C Power Amplifiers Comparison of Tuned Amplifiers 337 Solved Examples 1037 Review Questions 850 Diagrams

This book is divided into 25 chapters. Chapter 1 introduces the physical propertie of elements. Chapter 2 covers the passive circuit components, resistors, capacitors and inductors. Colour coding of capacitors has been added in this chapter.

Chapter 3 deals with electron ballistics. Here, the additions comprise derivation of path of an electron and magnetic focusing. Chapter 4 is devoted to semiconductor diodes and their applications. This has been updated with energy distribution of electrons, diode ratings, step-graded junction and temperature dependance on V-I characteristics. Chapter 5 explains various types of special diodes including metal-semiconductor junctions. The new additions are Zener resistance and Zener diode ratings and effect of temperature on Zener diode. Chapters 6 deals with bipolar junction transistors with the inclusion of enhancement of need of biasing. Chapter 7 is on Field Effect Transistors, which now includes new topics like pinch-off voltage, application of MOSFET in CMOS circuits and advantages of BJT over MOSFET. Chapter 8 describes the different members of the thyristor family such as PNPN diode, SCR, LASER, TRIAC, DIAC and GTO. Chapter 9 deals with midband analysis of small signal amplifiers. Chapter 10 explains the multistage amplifiers with additional topics like Darlington pair and cascode amplifier. Chapter 11 concentrates on frequency response of amplifiers with additional inputs on logarithms, decibels, hybrid pi conductances and capacitances. Chapter 12 is devoted to large signal amplifiers with a new topic on enhancement of different classes of amplifiers. Chapter 13 covers the tuned amplifiers and their comparison. Chapter 14 introduces feedback amplifiers. Chapter 15 deals with oscillators and their amplitude stability. Chapter 16 describes wave shaping and multivibrator circuits. Chapter 17 gives a brief description on UJT, pulse transformers, blocking oscillators and time base generators. Chapter 18 explains various types of rectifiers, filters, power supplies, harmonic components in a rectifier circuit and comparison of filters. Chapter 19 is devoted to integrated circuit fabrication. Chapter 20 deals with operational amplifiers and their applications. Chapter 21 covers different types of transducers. Chapter 22 contains a detailed study of opto-electronic devices including LCD panels and plasma display panels. Chapter 23 discusses a variety of electrical and electronic measuring instruments. Chapter 24 deals with digital circuits including 9’s complement, 10’s complement, EX-OR and Ex-NOR gates. Chapter 25 presents a study of memories, microprocessors and microcontrollers.

All the topics have been profusely illustrated with diagrams for easy understanding. Equal emphasis has been laid on mathematical derivations as well as their physical interpretations. Illustrative examples are discussed to emphasise the concepts and typical applications. Review questions and exercises have been given at the end of each chapter with a view to help readers enhance their understanding of the subject and to encourage further reading.

We sincerely thank the managements of SSN College of Engineering, Chennai, and Velammal College of Engineering and Technology, Madurai, for their constant encouragement, and for providing necessary facilities for completing this project. We express our deep gratitude to Dr. P. Balakrishnan, Former Director of Directorate of Technical Education, Government of Tamil Nadu, for giving a Foreword to the first edition of this book. We express thanks to our colleagues for their useful comments, which have improved the book considerably over the previous edition. We are thankful to Mr. S. Karthiec alias Ayyadurai, Assistant Professor, SSN College of Engineering, for his help in the preparation of additional material and proof correction. We are highly appreciative of Mr. S. Sankar Kumar for efficiently word processing the manuscript of the first edition. Our thanks are also due to Mr. R. Gopalakrishnan for word processing the additional manuscript. We are grateful to the editorial and production teams including Mrs. Vibha Mahajan, Mr. Ebi John Amos and Ms. Koyel Ghosh of Tata McGraw Hill Education Private Limited for their initiation and support to bring out this revised edition in a short span of time. We would also like to take this opportunity to thank the numerous reviewers for their useful comments and suggestions. Their names are given below: Gargi Khanna

National Institute of Technology, Hamirpur, Himachal Pradesh

Najeeb-Ud-Din

National Institute of Technology, Srinagar, Jammu and Kashmir

Ritu Tewari

Indian Institute of Technology and Management, Gwalior, Madhya Pradesh

Naveen Babu

Jaypee Institute of Information Technology, Noida, Uttar Pradesh

Bhavna Jharia

Jabalpur Engineering College, Jabalpur, Madhya Pradesh

Kumud Ranjan Jha

Shri Mata Vaishno Devi University, Katra, Jammu and Kashmir

Naresh Chandra Agarwal Shambhunath Institute of Engineering and Technology, Allahabad, Uttar Pradesh Naim Kidwai

Integral University, Lucknow, Uttar Pradesh

Shila Ghosh

B P Poddar Institute of Management and Technology (BPPIMT), Kolkata

Asha Elizabeth

Cochin University of Science and Technology (CUSAT), Cochin, Kerala

Sanjit K Dash

Krupajal Engineering College, Bhubaneswar, Orissa

Bharath Kumar

Dr. D. Y. Patil College of Engineering, Pune, Maharashtra

Sambaji Namdeo Kadam Lokmanya Tilak College of Engineering, Navi Mumbai, Maharashtra Manish Deshmukh

Shrama Sadhana Bombay Trust’s College of Engineering and Technology, Jalgaon, Maharashtra

Prakash Baviskar

SSVPS’s Bapusaheb Shivajirao Deore College of Engineering, Dhule, Maharashtra

Barnali Dey

Sikkim Manipal University, Sikkim

S Gomathi

K S Rangasamy College of Technology, Thiruchengode, Tamil Nadu

R Kousalya

Sri Venkateswara College of Engineering, Sriperumbudur, Tamil Nadu

T J Jeyapraba

Sri Venkateswara College of Engineering, Sriperumbudur, Tamil Nadu

B H Raghunath

Acharya Institute of Technology, Bangalore

G Ramakrishna

Vaishnavi Institute of Technology, Chittoor, Andhra Pradesh

A Hazrathiah

Narayana Engineering College, Nellore, Andhra Pradesh

P Rajesh Kumar

University College of Engineering, Vishakhapatnam, Andhra Pradesh

M E Paramasivam

Sona College of Technology, Coimbatore, Tamil Nadu

Professor Salivahanan is greatly thankful to his wife, Kalavathy, and sons Santhosh Kanna and Subadesh Kanna; Professor Suresh Kumar expresses his heartfelt thanks to his wife, Andal, and daughters Sree Naga Gowri and Sree Naga Vani for their spirit of self-denial and enormous patience during the preparation of this book. We welcome suggestions for the improvement of the book. S. SALIVAHANAN N. SURESH KUMAR

Do you have any feedback? We look forward to receive your views and suggestions for improvement. The same can be sent to [email protected], mentioning the title and author’s name in the subject line.

Electronics has been defined as that branch of science and technology which relates to the conduction of electricity through vacuum by electrons alone or through gases by electrons and ions. Basically, it is a study of electron devices and their utilization. An electron device is that in which electrons flow through a vacuum or gas or semiconductor. In the beginning of 20th century, electronics began to take technological shape and it has enjoyed an explosive development in the last four decades. Electronics has a wide range of applications, such as rectification, amplification, power generation, industrial control, photo-electricity, communications and so on. The electronic industry turns out a variety of items in the range of consumer electronics, control and industrial electronics, communication and broadcasting equipments, biomedical equipments, calculators, computers, microprocessors, aerospace and defence equipments and components. Initially, the discovery of electricity motivated research that has led to the present day concept of an atom. Michael Faraday studied the passage of electricity through liquid solutions. The next step in the study of the electrical nature of matter was made by J.J. Thomson. He focused his attention on the passage of electricity through gases. The studies by Thomson of the electrical discharge through gases at low pressure established that an atom is composed of charged particles—electrons and protons. Historically, the study of electrical discharge through gases and the discovery of cathode rays marked the beginning of a new branch of Physics called Atomic Physics.

An atom is the smallest particle of a chemical element possessing the chemical properties of the element. The first model of an atom was given by J.J. Thomson. His model explained an atom as a sphere of positively charged matter in which electrons were embedded. This model could not explain all features of optical spectra of hydrogen and other elements. In 1911, Rutherford established that an atom consists of a positively charged nucleus and a number of negatively charged electrons which revolve around the nucleus in various orbits. The nucleus consists of a number of neutral particles called neutrons and a number of positively charged particles called protons. The charge of the nucleus is positive and equal to the number of protons contained in it. The charge of a proton is 1.602 × 10–19 coulomb

and that of an electron is –1.602 × 10–19 coulomb. Each atom is ordinarily electrically neutral. Hence, in a neutral atom the number of revolving electrons must equal the number of protons in the nucleus. The mass of an electron is 9.107 × 10–31 kg, while that of a proton or neutron is about 1836 times that of the electron. Thus, almost the entire mass of an atom is concentrated in the nucleus. The radius of an atom is of the order of 1 Angstrom (10–10 m).

The first modern picture of an atom was put forward by Rutherford in 1911. Such an atom has a central nucleus of small dimensions around which move a number of electrons. The electron orbits are of atomic dimensions, i.e. of the order of 10–8 cm. The Centrifugal nucleus carries a charge to counteract the combined charge force of the electrons. Almost all of the mass of the atom resides in the nucleus. The Rutherford model of the hydrogen atom is Coulomb r force shown in Fig. 1.1. The hydrogen atom consists of one proton and one electron revolving around the centre nucleus in a +q Nucleus circular orbit of radius r. An electron in the circular orbit experiences a centripetal acceleration. According to electromagnetic theory, an accelerated electrical charge must radiate energy in the form of electromagnetic waves. The total energy of an electron in any orbit is the sum of its kinetic and potential energies. The potential energy of an electron is considered to be zero when it is at an infinite distance from the nucleus. The relation between the total energy possessed by an electron and the radius of the circular orbit r, is given below. W = potential energy + kinetic energy Zq2 – Zq2 – Zq2 W = _____ + _____ = _____ 4p e0r 8p e0r 8p e0r

(1.1)

where Z is the atomic number (Z = 1 for hydrogen); q, the charge of an electron = 1.602 × 10–19 coulomb; and e0, the permittivity of free space = 8.854 × 10–12 Farad/m. If the accelerated electron loses energy by radiation, the total energy of the electron continuously decreases and it must spiral down into the nucleus. Thus, the hydrogen atom cannot be stable. But most of the atoms are stable. According to classical electromagnetic theory, an accelerating electron must radiate energy at a frequency equal to the mechanical frequency of the orbiting electron and hence proportional to the angular velocity of the electron. Therefore, as the electron spirals toward the nucleus, the angular velocity tends to infinity and hence, the frequency of the emitted energy will tend to infinity. This will result in a continuous spectrum with all possible wavelengths. But, many atoms like hydrogen emit line spectra of fixed wavelengths only. The above two points are contradicting to what is normally happening in an atom. These two phenomena could not be explained using the Rutherford atomic model and are considered to be the main drawbacks of Rutherford model of an atom.

Bohr atom model could successfully explain many of the atomic phenomena. Bohr took the Rutherford model of the atom and tried to overcome the defects of the model. Bohr proposed that the laws of classical mechanics and electromagnetics broke down within the atom. The basic postulates of Bohr’s theory are a combination of the ideas of classical theory and Planck’s quantum theory of radiation.

Bohr postulated three fundamental laws to overcome the inconsistency in the Rutherford model. Electrons cannot occupy states at all energy levels as given by classical mechanics; electrons can occupy states at only certain discrete energy levels. When an electron occupies a state at one of these discrete energy levels, the electron does not emit radiation and is said to be in stationary or non-radiating state. When an electron moves one stationary state corresponding to energy W2 to another stationary state with lower energy W1, there results emission of radiation at a frequency f given by (W2 – W1) f = _________ (1.2) h –34 where f is the frequency of radiation in Hertz; h, the Planck’s constant = 6.626 × 10 Joules; and W1 and W2 are energies in Joules. Any stationary or non-radiating state is determined by the condition that the angular momentum of the electron in this state is quantized and must be an integral multiple of h/2p. Thus, nh mvr = ___ (1.3) 2p where n is an integer. The radii of the various stationary orbits is given by e0h2n2 rn = ______2 (1.4) p mq = 0.527 × 10–10n2 m

(1.5)

The total energy of electron in stationary states in Joules is given by – mq4 Wn = _______ 8e 20 h2n2

(1.6)

The total energy of electron in stationary states in electron volts is given by – mq3 Wn = _______ 8e 20 h2n2

(1.7)

–13.6 = _____ eV n2 It should be noted that the energy is negative and therefore, the energy of an electron in its orbit increases as n increases. The above expression for the energy of the electron suggests that to remove an electron from the first orbit (n = 1) of the hydrogen atom to outside of the atom, that is to ionise the atom, the energy required is 13.6 eV. This is known as the ionisation energy or the ionisation potential of the atom.

The least energy, expressed in electron volts, required to excite a free neutral atom from its ground state to a higher state is called critical potential of the atom. It is usual to distinguish two kinds of critical potentials, namely, excitation potential and ionisation potential. The energy in electron volts required to raise an atom from its normal state into an excited state is called excitation potential of the state. It is also called as radiation potential or resonance potential. It is defined as the energy required to remove an electron from a given orbit to an infinite distance from the nucleus. For example, the energy associated with an electron in nth orbit of the hydrogen atom is En = –13.6/n2 eV. Thus the energies of the first, second, third, ..., orbits are respectively –13.6, –3.4, –1.51, ..., 0 eV. The energy required to raise the atom from the ground state (n = 1) to the first excited state is (13.6 – 3.4) = 10.2 eV. The energy required to raise it to the second excited state is (13.6 – 1.51) = 12.09 eV and so on. It is clear that 10.2 eV, 12.09 eV are excitation potentials, while 13.6 eV is the ionisation potential of the hydrogen atom. The number of ionisation potential depends on the number of electrons in an atom. For hydrogen atom, there is only one ionisation potential and several excitation potentials. The energy required for the removal of the outermost valence electrons is called the first ionisation potential. The energy required for the removal of the second electron from the influence of the nucleus is called the second ionisation potential and this will be higher than the first ionisation potential.

Calculate the radii of the first, second and third permitted electron orbits in a Bohr’s hydrogen atom.

Solution

2 2 0h n Radius of the nth orbit for hydrogen, rn = ______ mq2 (8.854 × 10–12) (6.62 × 10–34)2 n2 = ____________________________ (9.1 × 10–31) (1.6 × 10–19)2

Therefore, the radius of the first orbit is, r1 = 5.27 × 10–11 × 12 m = 5.27 × 10–11 m = 0.527 A.U. The radius of the second orbit is,

r2 = 5.27 × 10–11 × 22 = 2.108 A.U.

The radius of the third orbit is,

r3 = 5.27 × 10–11 × 32 = 4.743 A.U.

When an electron jumps from higher orbits to lower orbits, radiation of energy takes place at particular frequencies. When an electron jumps from second, third, ... etc. orbits to the first orbit, the spectral lines are in the ultraviolet region. This is identified as Lyman series. When an electron jumps from outer orbits to the second orbit, the series is called Balmer series and lies in the visible region of the spectrum. When the transition of an electron is from outer orbits to the third orbit, the series is Paschen series and lie in the near infrared region. The transition from outer orbits to fourth and fifth orbits are respectively called Brackett series and Pfund series. The spectral lines for these two series lie in the very far infrared region of the hydrogen spectrum.

In the energy level diagram, the discrete energy states are represented by horizontal lines, and the height of the line represents the total energy En as calculated from Eqn. (1.7). Figure 1.2 shows the energy level diagram for hydrogen. The number immediately to the right of a line gives the value of integer n, while the number to the left of each line gives the energy to this level in electron volts. The lowest energy level E1 is called the normal or the ground state of the atom and the higher energy levels E2, E3, E4, ... are called the excited states. As n increases, the energy levels crowd and tend to form a continuum. En (eV) 0

n=4

Brackett series

n=3

Paschen series

n=2

– 0.85 – 1.5

– 3.4 Balmer series

n=1

–13.6

Lyman series

Sometimes, it is more convenient to specify the emitted radiation by its wavelength, Equation (1.2) can be rewritten as, 12, 400 = _______ E2 – E1

in Angstroms. (1.8)

where E2 and E1 are the energy levels in electron volts.

Find the wavelength of the photon emitted when a hydrogen atom goes from n = 10 state to the ground state.

Solution

The wavelength in Angstrom units is given by,

12, 400 = _______ E2 – E1

Since the hydrogen atom goes from n = 10 state to the ground state, –13.6 The energy of the 10th state is E10 = _____ = – 0.136 eV. 102

12, 400 = _______ E10 – E1

The energy in the ground state is E1 = – 13.6 eV. 12, 400 Thus the wavelength of the emitted photon = _______________ = 920.97 Å – 0.136 – (– 13.6)

Calculate the wavelength of the Balmer series limit.

Solution When an electron jumps from outer orbits to the second orbit, the series is called Balmer series. Using Eqn. (1.8), the wavelength limit for the Balmer series can be found by calculating the wavelength of the radiation due to the transition of electron from the infinite orbit to the second orbit. 12, 400 = _______ E• – E2 –13.6 Energy of the electron at the infinite orbit, E• = _____ =0 •2 – 13.6 Energy of the electron at the second orbit, E2 = _____ = – 3.4 22 12, 400 12, 400 Therefore, the wavelength limit = ________ = ______ = 3647 A.U. E• – E2 3.4 Wavelength of the Balmer series limit

In order to understand the location and energy of each electron in an atom, four quantum numbers are required. The four quantum numbers are identified as follows: This number characterises the average distance of an electron from the nucleus and corresponds to the principal energy level in which the electron resides. It gives some idea about the position of the electron around the nucleus. The allowed values of this quantum number n are positive integers starting from 1. Thus n can have values 1, 2, 3, ... . The principal energy levels or shells having different values of n are also represented by the letters K, L, M, N and so on. The maximum number of electrons that can reside in a shell corresponding to the principal quantum number n is equal to 2n2. This quantum number is also called as the orbital angular momentum quantum number. The quantum number l gives a measure of the angular momentum of an electron in this orbit. Physically, this number indicates the shape of the classical orbit. For a given value of n, the azimuthal quantum number l can take all positive integral values from 0 to (n – l ). The particular 1 value defines the subshell. The subshells with l = 0, 1, 2 ... are designated s, p, d, f, g, h, k, ..., respectively. For a given principal quantum number, the energies of the various subshells are in the order s < p < d < f .... Thus, an electron in the s subshell has lower energy than that in the______ p subshell with the same principal quantum number. The magnitude of this angular momentum is h ÷l(l + 1) /2p. This is also called as orbital magnetic number. The magnetic moment of an electron due to its orbital motion gives rise to a magnetic field which can interact with an external magnetic field. Under the influence of the external magnetic field, the electrons orient themselves in certain preferred region of space around the nucleus. The magnetic quantum number ml determines the preferred orientation of the orbitals in space with respect to an applied magnetic field. For a given value of l, magnetic quantum number can take integral values between –1 to +1 including 0. For a given value of l, the total allowed values of ml are (2l + 1). The magnitude of the component of angular momentum along the direction of the magnetic field is ml (h/2p).

This number is concerned with the spinning of the electron about its own axis. This spin produces a spin magnetic moment, which can be either parallel or antiparallel to the surrounding magnetic field. Thus, there are two spin states for an electron. Hence, the spin quantum 1 1 number can take only two possible values, + __ or – __. 2 2 The position of an electron in an atom is completely described by these four quantum numbers. Pauli’s exclusion principle, states that in an atom no two electrons can exist in the same quantum state. In other words, there cannot be two electrons in an atom with the same value of all the four quantum numbers. Using Pauli’s exclusion principle, the configuration of electrons can be written. All the electrons with the same value of n constitute a shell and a shell can have a maximum of 2n2 electrons. The energy state capacity of different shells and subshells are considered hereunder: K-shell corresponds to n = 1 and has only one subshell, namely, 1s. The 1s subshell corresponds to n = 1, l = 0, ml = 0 ms = ±1/2 and has 2 states. L-shell corresponds to n = 2 and has two subshells, namely, 2s and 2p. The 2s subshell corresponds to n = 2, l = 0, ml = 0 and has 2 states. The 2p subshell corresponds to n = 2, l = 1, ml = 0, ±1, and has 6 states. M-shell corresponds to n = 3 and has three subshells namely 3s, 3p and 3d. The 3s subshell corresponds to n = 3, l = 0, ml = 0, and has 2 states. The 3p subshell corresponds to n = 3, l = 1, ml = 0, ±1, and has 6 states. The 3d subshell corresponds to n = 3, l = 2, ml = 0, ±1, ±2 and has 10 states. N-shell corresponds to n = 4 and has four subshells namely 4s, 4p, 4d and 4f. The 4s subshell corresponds to n = 4, l = 0, ml = 0, and has 2 states. The 4p subshell corresponds to n = 4, l = 1, ml = 0, ±1, and has 6 states. The 4d subshell corresponds to n = 4, l = 2, ml = 0, ±1, ±2, and has 10 states. The 4f subshell corresponds to n = 4, l = 3, ml = 0, ±1, ±2, ±3 and has 14 states. Table 1.1 gives the electronic configuration in an atom taking into consideration the Pauli’s exclusion principle. Actually, seven shells are required to account for all the chemical elements, but only the first four are indicated in the table.

Shell

K

L

M

N

n

1

2

3

4

l

0

0

1

0

1

2

0

1

2

3

Subshell

s

s

p

s

p

d

s

p

d

f

No. of electrons

2

2

6

2

6

10

2

6

10

14

The electrons in the innermost shells are very strongly attached to the atom and cannot be easily separated, i.e. the electrons that are very near to the nucleus are most tightly bound and hence have the lowest energy. The atoms that have electrons in the closed shells will have very stable configurations. The atomic number Z gives the number of electrons orbiting about the nucleus. Superscripts are used to designate the number of electrons in a particular subshell. For silicon, the atomic number Z is 14 and it has an electronic configuration designated by 1s22s22p63s23p2. Note that silicon has only two electrons in the outermost subshell which can actually accommodate 6 electrons. Hence, the silicon

atom needs four more electrons to have a completely filled outermost subshell. Silicon is classified as a tetravalent element, i.e. it has a valency of 4. This property is also possessed by carbon (C), germanium (Ge), tin (Sn) and lead (Pb) whose electronic configuration is given in Table 1.2. This accounts for the fact that these elements are in the same group (IVA) in the periodic table. However, carbon in crystalline form is an insulator, silicon and germanium are semiconductors, and tin and lead are metals. The reason for this behaviour can be understood from the study of energy band theory of crystals.

Element

Atomic number

Electronic configuration

C

6

1s22s22p2

Si

14

1s22s22p63s23p2 2

2

Ge

32

1s 2s 2p6 3s2 3p63d104s24p2

Sn

50

1s22s22p63s23p63d104s24p64d105s25p2

Pb

82

1s22s22p63s23p63d104s24p64d104f145s25p65d106s26p2

The crystalline structure is common among most of the metals and semiconductors. Any crystal is made up of a space array of atoms of molecules in regular repetition in three dimensions of some fundamental building block. For a gaseous element, the electronic energy levels are the same as for a single free atom because the individual atoms in a gas are well apart and has negligible influence on each other. However, in a crystal the individual atoms are so closely packed that the resulting energy levels are modified due to interaction between the atoms. When atoms form crystals, the energy levels of the inner-shell electrons are not appreciably affected, however, the levels of the outer-shell electrons are considerably altered as these electrons are shared by the adjacent atoms in the crystal. As a result of this interaction between the outer-shell elecIsolated atoms trons, the energy levels spread up to form 2N electrons a band of energy as shown in Fig. 1.3. 6N states

2N electrons 6N p states

Energy

In order to understand the formation of energy bands in a crystal, let us consider a silicon crystal made up of N atoms. We shall also assume that the interatomic spacing can be varied without affecting the fundamental crystal structure. For very large interatomic spacing, say ‘a’ in Fig. 1.3, the interaction between adjacent atoms is negligible, and the energy levels are same as that of isolated atoms. In silicon, the outermost subshells, namely, 3s and 3p contain 2 electrons each. Hence, in a silicon crystal consisting of N atoms, the outermost subshells 3s and 3p consist of 2N electrons each. Thus, the 3s subshell has 2N electrons completely occupying the

Energy gap

2N electrons 2N s states

2N electrons 2N states Lower energy levels unaffected by crystal formation

a Interatomic spacing

available 2N states, and the 3p subshell has only 2N electrons partially occupying the available 6N states, all at the same energy level. If the interatomic spacing is gradually decreased, i.e., moving from right to left in Fig. 1.3, there will be a gradual increase in the interaction between the neighbouring atoms. Due to this interaction, the atomic wave functions overlap, and the crystal becomes an electronic system which should obey the Pauli’s exclusion principle. Hence, the 2N s states spread out to form a band of energy. Actually, the separation between levels is small but since N is very large, of the order of 1023 cm–3, the total spread between the minimum and maximum energy levels becomes large. This spread will have several electron volts of energy and is referred to as energy band and is indicated by the lower shaded region in Fig. 1.3. The 2N states in this band are completely filled with 2N electrons. Similarly, at the same value of interatomic spacing at p-level, 6N p states spread up to form a band. This band is shown as the upper shaded region in Fig. 1.3. Though a total of 6N states are available in this band, only 2N states are occupied and 4N states remain unoccupied. An energy gap exists between the two energy bands. This energy gap is called as forbidden energy gap, as no electrons can occupy states in this gap. This forbidden energy gap decreases as the atomic spacing is decreased and becomes zero with further reduction in the interatomic spacing, say at ‘b’, as shown in Fig. 1.4. That is, the two energy bands will overlap when the interatomic spacing is small enough. Under such circumstances, the 6N p states in the upper band merge with the 2N s states in the lower band, giving a total of 8N states. Half of these 8N states are occupied by the 4N available electrons. These 4N electrons now no longer belong to either p subshell or s subshell but belong to the crystal as a whole. Thus, at this interatomic spacing, each atom in the crystal can contribute 4 electrons to the crystal. The band occupied by these contributed electrons is called the valence band.

Energy

If the interatomic spacing is reduced further, say ‘c’ as shown in Fig. 1.4, the interaction between the atoms becomes extremely large, 4 N states and the energy band structure 0 electrons Conduction band assumes the shape shown in Fig. 1.4. The exact energy band structure depends upon (i) the orientation of the atoms relative to 0 one another in space, and (ii) the states Eg atomic number of the atom, and may be obtained from solution of Schrodinger’s wave equation. For spacing ‘c’, 4N states in the valence band are completely 4 N states filled by 4N electrons and this 4 N electrons valence band is separated from Valence band the upper unfilled or empty band by a forbidden energy gap Crystal lattice spacing Eg. The forbidden energy gap contains no allowed states. The c b Interatomic spacing upper band has 4N unfilled states and is referred to as the conduction band.

A very poor conductor of electricity is called an insulator; an excellent conductor is a metal; and a material whose conductivity lies between these two extremes is a semiconductor. A material may be classified as one of these three depending upon its energy-band structure.

An insulator is a material having extremely poor electrical conductivity. The energy-band structure of Fig. 1.4 at the normal lattice spacing is indicated schematically in Fig. 1.5(a). The forbidden energy gap is large; for diamond the gap energy is about 6 eV. If additional energy is given to an electron in the upper level of valence band, this electron attempts to cross the forbidden energy gap and enter the conduction band. However in an insulator, the additional energy which may ordinarily be given to an electron is, in general, much smaller than this high value of forbidden energy gap. Hence no electrical conduction is possible. The number of free electrons in an insulator is very small, roughly about 107 electrons/m3. Conduction band Free electrons

Eg = 6 eV

CB Forbidden band

Eg = 1 eV

VB

Holes Valence band (a)

(b)

(c)

The conduction in metals is only due to the electrons. A metal has overlapping valence and conduction bands. The valence band is only partially filled and the conduction band extends beyond the upper end of filled valence band. The outer electrons of an atom are as much associated with one ion as with another, so that the electron attachment to any individual atom is almost zero. The band occupied by the valence electrons may not be completely filled and that there are no forbidden levels at higher energies. Depending upon the metal, at least one, and sometimes two or three, electrons per atom are free to move throughout the interior of the metal under the action of applied fields. When an electric field is applied, few electrons may acquire enough additional energy and move to higher energy within the conduction band. Thus the electrons become mobile. Since the additional energy required for transfer of electrons from valence band to conduction band is extremely small, the conductivity of metal is excellent.

In electron-gas theory description of a metal, the metal is visualized as a region containing a periodic three-dimensional array of heavy, tightly bound ions permeated with a swarm of electrons that may move about quite freely. According to this theory, the electrons in a metal are continuously moving and the direction of flight changes whenever the electron collides with other electrons. The average distance travelled by an electron between successive collisions is called as mean-free-path of an electron. In the absence of any applied potential, the average current in a metal is zero because the number of electrons passing through unit area in any direction is almost same as the number of electrons passing through the same unit area in the opposite direction. This can be attributed to the random nature of motion of electrons. When a constant electric field E (volts per metre) is applied to a metal, the electrons would be accelerated and the velocity would increase indefinitely with time. However, because of collision of electrons, electrons lose energy and a steady-state condition is reached where a finite value of drift velocity vd is attained. The drift velocity, vd is in the direction opposite to that of the electric field and its magnitude is proportional to E. Thus vd = mE

(1.9)

2

where m = mobility of the electron, m /volt-second. Due to the applied field, a steady-state drift velocity has been superimposed upon the random thermal motion of the electrons. Such a directed flow of electrons constitutes a current. If the concentration of free electrons is n (electrons per cubic meter), the current density J (amperes per square metre) is where

J = nqvd = nqmE = sE

(1.10)

s = nqm

(1.11) –1

s is the conductivity of the metal in (ohm-metre) . For a good conductor n is very large, approximately, 1028 electrons/m3. Equation (1.10) can be recognized as Ohm’s law which states that the conduction current density is proportional to the applied electric field. The energy acquired by the electrons from the applied field is given to the lattice ions as a result of collisions. Hence, power is dissipated within the metal by the electrons, and the power density (Joule heat) is given by JE = sE 2 watts/metre3

(1.12)

The conductivity of a material is proportional to the concentration of free electrons. The number of free electrons in a semiconductor lies between 107 and 1028 electrons/m3. Thus, a semiconductor has conductivity much greater than that of an insulator but much smaller than that of a metal. Typically, semiconductor has forbidden energy gap of about 1 eV. The most important practical semiconductor materials are germanium and silicon, which have values of Eg of 0.785 and 1.21 eV, respectively, at 0 degree Kelvin. Energies of this magnitude normally cannot be acquired from an applied field. At low temperatures the valence band remains full, the conduction band empty, and these materials are insulators at low temperatures. The conductivity of these materials increases with temperature and hence these materials are called as intrinsic semiconductors. As the temperature is increased, some of the electrons in the valence band acquire thermal energy greater than the gap energy and move into the conduction band. These electrons are now free to move about under the influence of even a small applied field. These free electrons, also called as conduction electrons, constitute for conduction and the material becomes slightly conducting. The current density due to the motion of electrons is given by

Jn = nmnqE = snE

(1.13)

where, mn is the electron mobility, and the suffix ‘n’ represents that the respective terms are due to motion of electrons. The absence of an electron in the valence band is represented by a small circle and is called a hole. The hole may serve as a carrier of electricity whose effectiveness is comparable with the free electron. The hole conduction current density is given by Jp = pmpqE = spE

(1.14)

where mp is the hole mobility and p is the hole concentration. Hence, the total current density J in a semiconductor is given by J = (nmn + pmp)qE = sE

(1.15)

where s = (nmn + pmp)q is the total conductivity of a semiconductor. For a pure semiconductor (intrinsic semiconductor), the number of free electrons is exactly same as the number of holes. Thus, the total current density is J = ni(mn + mp) qE

(1.16)

where ni = n = p is the intrinsic concentration of a semiconductor. The conductivity of an intrinsic semiconductor can be increased by introducing certain impurity atoms into the crystal. This results in allowable energy states which lie in the forbidden energy gap and these impurity levels also contribute to the conduction. Such a semiconductor material is called an extrinsic semiconductor. An electron travelling through a crystal under the influence of an externally applied field hardly notices the electrostatic field of the ions making up the lattice, i.e. it behaves as if the applied field were the only one present. This is the basis of the electron gas approximation and the assumption will now be looked at a little more closely. If the electrons were to experience only the applied field, E, then immediately after a collision it would accelerate in the direction of the field with an acceleration a, proportional to the applied force, i.e. qE = ma

(1.17)

where the constant of proportionality is the electron mass, m. When quantum theory is applied to the problem of an electron moving through a crystal lattice, it predicts that under the action of an applied field the electron acceleration will indeed be proportional to the field, but that the constant of proportionality will be different from the normal mass of an electron: qE = mna

(1.18)

The field due to the lattice ions can, therefore, be ignored providing we treat the electrons inside the crystal as if they had a slightly different mass to the real electron mass or, to put it another way, the effect of the lattice ions on an electron is to make it behave as if it had a different mass. This new mass is called the effective mass of the electron, mn, and the effective mass of a hole, mp, can be similarly defined. In general, mn and mp are not the same. Usually, mn is of the same order as m; in germanium, for instance, mn = 0.2 m and in silicon, mn = 0.4 m. The value of effective mass is an important parameter for any semiconductor, especially from the device point of view. Certain semiconductors, for instance, have low electron effective mass and hence high electron mobility. This makes them very suitable for high-frequency devices. The III-V semicon-

ductor GaAs comes into this category and some of the best microwave transistors are made from this material.

All semiconductors have crystalline structure. The most commonly used semiconductor materials, germanium, silicon and gallium arsenide have practical applications in Electronics. The most frequently used semiconductors are germanium and silicon because the energy required to break their covalent bonds and release a free electron from their valence bands is lesser than that required for gallium arsenide. The energy required for releasing an electron from the valence band is 0.66 eV for germanium, 1.08 eV for silicon and 1.58 eV for gallium arsenide. Germanium can be purified relatively well and crystallised easily. Germanium is an earth element and it is obtained from the ash of the certain coals or from the flue dust of the zinc smelters. The recovered germanium is in the form of germanium dioxide powder which is then reduced to pure germanium. Germanium diodes are used as infrared detectors in fibre-optic communication system because of narrower energy gap. Silicon is an element found in most of the common rocks. Sand is silicon dioxide which is then reduced to 100% pure silicon. Silicon dioxide is a natural insulator which is useful in the fabrication of semiconductor devices and integrated circuits. Silicon is largely preferred to germanium because of its large gap energy, which produces improved device properties at high temperatures. Silicon is a better thermal conductor and is required to remove unavoidable heat developed in the device. Gallium arsenide has higher electron mobility, mn which leads to faster switching capabilities. It has high temperature operating capabilities because of its larger energy gap.

Electron emission is the process by which the free electrons escape from the surface of a substance. Metals are used for electron emission because a metal is made up of atoms bound in crystal lattices, of electrons bound to the atoms, and of many free electrons which are not bound to any particular location in the metal. The free electrons are always in motion and travel more or less freely throughout the body of the metal. However, these electrons are free only to the extent that they may transfer from one atom to another within the metal but they cannot leave the metal surface. If a certain amount of external energy is given to a free electron, its kinetic energy is increased and thus electron will cross over the surface barrier to escape from the metal. This amount of kinetic energy required at absolute zero temperature is known as work function of that metal. It is denoted by Ew, and expressed in electron-volt (eV). One eV, equal to 1.602 × 10–19 Joule, is the amount of energy acquired by an electron when it is accelerated through a potential difference of one volt (1 V). The work function of pure metals varies approximately from 2 to 6 eV. The metal used for electron emission should have low work function so that a small amount of external energy is required to cause emission of electrons. Work function of a metal is principally determined by the spacing between its atoms. Wider spacing usually give lower values of work function. The work functions of some of the common metals are given in Table 1.3.

Metal

Work function in eV

Metal

Work function in eV

Ag

4.60

K

1.90

Al

3.00

Li

2.21

Ba

2.52

Na

2.00

Ca

3.00

Ni

5.00

Cs

1.67

Rb

1.82

Cu

4.30

Th

3.50

Fe

4.74

Zn

3.44

The four basic methods of obtaining electron emission from the surface of a metal are classified according to the type of additional energy (equal to the work function of the metal) supplied from the sources such as heat energy, energy stored in electric field, light energy and kinetic energy of the electric charges bombarding the metal surface, as discussed below: When a metal is heated to sufficient temperature, enough thermal energy is imparted to electrons to enable them to escape from the metal surface. The higher the temperature, the greater is the emission of electrons. This method is known as thermionic emission and is employed in vacuum tubes. Richardson, and later on Dushman, on the thermodynamic basis, derived the equation for thermionic emission at a certain temperature, T. This equation is given by Ith = SAoT 2 e – Ew/kT where

Ith S Ao T k Ew

(1.19)

= thermionic emission current in amperes = area of filament in m2 = constant = absolute temperature, K = Boltzmann constant, eV/K = work function, eV.

At high temperatures, the electrons are literally being ‘boiled’ from the metal surface. This is analogous to the boiling of water. The commonly used thermionic emitters with low Ew, as given in Table 1.4, are tungsten in high voltage (kV) tubes, thoriated tungsten in high power (KW) tubes and oxide coated metals in low power electron tubes and Cathode Ray Tubes (CRT).

Thermionic emitter

Work function in eV

Range of operating temperature in K

Emission efficiency in mA/W

Tungsten

4.52

2500 – 2600

2 – 10

Thoriated tungsten

2.63

1900 – 2000

50 – 100

Oxide-coated

1.10

900 – 1100

100 – 1000

When the potential difference between two electrodes is extremely high, electrons are emitted from the negative electrode, even at ordinary temperatures. If the electric field at the metallic surface of the negative electrode is of the order of 106 volts per metre, electrons are quite easily pulled out from the surface. This process of electron emission is known as field emission. Field emission does not depend on the temperature of the surface. This type of emission is employed in cold cathode devices and mercury and rectifier tube. When the surface of certain metals are illuminated by a beam of light, electrons are ejected out of the metal by the light photons incident on the metal surface. Such an electron emission is known as photo-electric emission and is used in photo-electric cell. The greater the intensity of light beam falling on the metal surface, the greater is photo-electric emission. When a beam of high velocity electrons strike a metal surface, the free electrons are ejected out of the metal. This process is known as secondary emission.

A passive component is one that contributes no power gain (amplification) to a circuit or system. It has no control action and does not require any input other than a signal to perform its function. The most commonly used passive circuit components in electronic and electrical applications are resistors, capacitors and inductors. The constructional features, characteristics and applications of these components are discussed in this chapter.

Physical materials resist the flow of electrical current to some extent. Certain materials such as copper offer very low resistance to current flow, and hence they are called conductors. Other materials such as ceramic which offer extremely high resistance to current flow are called insulators. In electric and electronic circuits, there is a need for materials with specific values of resistance in the range between that of a conductor and an insulator. These materials are called resistors and their values of resistance are expressed in ohms (W). The resistance R of a given material is proportional to its length L and inversely proportional to its area of cross section A. Thus R varies as L/A and R = r(L/A), where r is the constant of the material known as its specific resistance or resistivity. The various types of resistors are given in Table 2.1.

Fixed resistors

Variable resistors

Carbon composition

Potentiometer

Carbon film

Rheostat

Metal film

Trimmer

Wire wound

This is the most widely used fixed resistor in discrete circuits. The construction of the carbon composition resistor is shown in Fig. 2.1. The carbon resistors are made of finely divided carbon mixed with a powdered insuSolid resistance lating material such as resin or clay in element the proportions needed for the desired resistance value. These are then placed in a casing (moulded plastic) with lead Embedded lead wires of tinned copper. Resistances Solder coated lead of this type are available in the range from few ohms to hundred megaoColour coding hms and typical power ratings of 1/8 to 2 W. This is yet another Moulded type of carbon resistor. Its basic strucbody ture is shown in Fig. 2.2. It is manufactured by depositing a carbon film on a ceramic substrate. In this process only approximate values of resistance are obtained by either trimming the layer thickness or by cutting helical grooves of suitable pitch along its length. During this process, the value of the resistance is monitored constantly. Cutting of grooves is stopped as soon as the desired value of resistance is obtained. Contact caps are fitted at both ends, and then the lead wires made of tinned copper are welded to these end caps. This type of resistors are available commercially in the range of 10 W to 10 MW with a power rating of up to 2 W. Carbon film resistors are less noisy than carbon composition resistors and they are of low cost. Grooved carbon film

Leads End cap

Ceramic core (a)

(b)

Construction of this type of resistor is similar to the carbon film resistors, the only difference being the material used for constructing the film. In metal film resistors, the film usually consists of an alloy of tin and antimony metals. Metal film resistors are available as thin and thick film type components. The resistance element in this type is a film having a thickness of the order of one-millionth of an inch. Typically, the thin film is deposited on a ceramic substrate under a high vacuum and this technique is called vacuum deposition. Metals used for deposition include nickel and

chromium. This type of resistors are available in the range of 10 W to 1 MW with a power rating of up to 5 W. The resistance element in this type is a film having a thickness greater than onemillionth of an inch. Four different types of thick film resistors are available, viz. tin oxide, metal-glaze, cermet and bulk film resistors. In this type of resistors, tin oxide in vapour form is usually deposited on a ceramic substrate under high temperature. The vapour reacting with the substrate, which is heated, results in a tightly formed resistance film. This type of resistor is available in the range of a few ohms to 2.5 MW with a power rating of up to 2 W. In this type, a powdered glass and fine metal particle (palladium and silver) mixture is deposited on a ceramic substrate. This combination is then heated to a high temperature, typically 800 °C. This results in a fusion of metal particles to the substrate. This type of resistors are manufactured in the range of a few ohms to 1.5 MW with a power rating of up to 5 W. A cermet film resistor is made by screening a mixture of precious metals and binder materials on a ceramic substrate. The word ‘cermet’ is derived from ceramic and metal. As in the case of metal glaze resistor, the combination is then heated to a high temperature. It is available in the range of 10 W to 10 MW with a maximum power rating of 3 W. In this type, the metal film is etched on a glass substrate. As metal film and glass have unequal coefficients of expansion, the metal film is compressed slightly by the glass substrate. The compressed film has a negative temperature coefficient which cancels out the inherent positive temperature coefficient of the film. As a result, the bulk film resistor has a temperature coefficient close to zero. This type of resistor is available in the range of 30 W to 600 kW with a maximum power rating of 1 W. It has a wide range of applications. It is used as an ultra precision resistor in instrumentation and a power resistor in industrial applications. Wire wound resistors are manufactured in two types: (i) Power style wire wound resistor, and (ii) Precision style wire wound resistor. It is made by winding a single layer length of special alloy wire, in the form of a coil around an insulating core. The ends of the winding are attached to metal pieces inserted in the core. Tinned copper wire leads are attached to metal pieces. The unit is then covered with a coating, such as vitreous enamel (an inorganic glass like moisture) or silicone. This coating protects the winding against moisture and breakage. The resistance wire lead must have carefully controlled resistance per unit length of wire and low temperature coefficient, and be able to operate at high temperatures. Alloys used include nickel-chromium-aluminium and nickel-chromium-iron (Nichrome). The cylindrical core is ceramic, steatite or a vitreous material. This type of resistor is available in the range from less than an ohm to greater than a megaohm with a power rating as high as 1500 W. To increase its power rating, the resistor is sometimes placed in a metal housing such as aluminium. They are wound on ceramic (steatite) tubes or sometimes epoxy moulded tubes as shown in Fig. 2.3. The wire is wound in alternate directions in the adjacent p-sections to minimise inductive effect at high frequencies. This type of winding is referred to as ‘bifilar’. Wires of low temperature

p-sections

coefficient alloys (e.g., Manganin) are employed. The leads are usually anchored to the tubes firmly and joined to the wire ends by brazing. The unsealed type of resistors are impregnated with varnish while the sealed types are given a dip of epoxy resin or encased in ceramic or glass tubes. Yet another type of construction in which the inductance is virtually reduced to zero is shown in Fig. 2.4. Here, a thick film serpentine pattern is deposited on a ceramic core. Similar in behaviour to biflilar winding opposite to magnetic fields produced by current flowing in adjacent resistance paths cancel each other, thus reducing the inductance to zero. Precision style wire wound resistors are available in the range of a fraction of an ohm to 10 MW with a power rating of the order of 2 W.

These are the resistors whose resistance can be changed between zero and a certain maximum value. They are used in electronic circuits to adjust the value of voltages and currents. For example, they are used as volume control in radio and brightness control in television. Variable resistors can be broadly classified into three types, viz. Potentiometer, Rheostat, Trimmer. It is a variable resistor either of carbon or wire wound type. It is smaller in size compared to a rheostat and is usually referred to as “pot.” The construction of carbon potentiometer is shown in Fig. 2.5. These are manufactured either in film or moulded track types. Both consist of an annular ring of carCarbon track bon resistance, formed on a plastic base, over which a movable contact can slide. There is a slip ring (a continuous metal ring) which is also contacted by the movable contact. Three terminals are provided, two of them connected to Slip ring the ends of the carbon track and one to the slip ring. A shaft runs through a bush in the center of the base to which the movable contact Wiping contact is attached. The assembly is enclosed by a case of sheet metal over which the resistance value and taper are also engraved. The taper refers to variation in resistance along the track which may be a logarithmic or linear variation. The track may be either the film type or a moulded type. In the film type, a mixture of carbon, graphite and resin in the form of a paste is sprayed on to a plastic (phenolic) sheet, with suitable marks in the form of rings. If a nonlinear taper is required, the ring width may be varied circumferentially or the spray may be made from different composition mixtures along the track length.

In the moulded track type, the resistance material and the base plate are moulded together with the slip ring, the terminals and the bushing all being inserted in the moulding operation. The integral moulding of base, track and terminals gets rid of solders, rivets, welds and provides good humidity resistance and fewer mechanical joints. They are of two types: (a) Single turn, and (b) Multiturn. As shown in Fig. 2.6(a), on a flat strip of insulating card made of flexible plastics or anodised aluminium (aluminium oxide formed on aluminium), the resistance wire, usually copper alloy wire for low resistance pots and the nickel chromium for high resistance pots, is wound and then the strip is bent round a cylindrical surface. Contact by means of a slider metal or beryllium copper, which is spring loaded, is made on the inside periphery or the outer edge. Contact from the slider is made through a slip ring or by a coiled spring. The winding is usually of two or three linear resistance sections to approximate ideal taper (such as log). Single turn pots are available in the range from 50 W to 5 MW and in power ratings of 2 to 3 W. It is commonly used as a gain control element in an amplifier and as brightness and contrast controls in TV receivers. Multiturn or helical pots are used in applications that require precise setting of a resistance value. An example is the setting of coefficients in an analog computer. Commonly, they have up to 10 turns. As shown in Fig. 2.6(b), the resistance element is wound on a long strip and then formed into a helix and held in a plane using silicone varnish. The contact is of precision metal and has multiple “fingers”. Usually, the groove between the helical turns of the element may be used to guide the contact. Because of its construction, the wire wound pot has appreciable stray inductance and capacitance which may be a problem at high frequency operation. They are available in the range from 50 W to 250 kW with a power rating of up to 5 W.

Resistance wire

T1 T2

T3 (a)

Strip of insulating card

Insulating card wound as a helix (b)

A wire wound pot that can dissipate more than 5 W is referred to as a rheostat. As shown in Fig. 2.7, the resistance wire is wound on an open tube of ceramic which is covered with vitreous enamel, except for the track of the movable contact. The rheostat is capable of withstanding temperatures up to 300 °C. It is used to control motor speed, X-ray tube voltages, welding current, ovens and in many other high power applications. Movable contact

Winding

Fixed contact Fixed contact

Ceramic tube

A trimmer or trimming potentiometer is used where the resistance must be adjustable but not continuously variable. It finds a very important place in calibration and balancing of electronic equipments. These are screw activated and the resistance Resistive can be adjusted by a screw driver. Figure 2.8 shows coating Screw the commonly used rotary trimmer. Here, the resistance track is made of carbon and cermet. The car- adjustment bon track along with the movable slide is housed in a steel casing. Typically, their resistance range is from a few ohms to 5 MW and the power rating is 1 W.

In the manufacture of resistors where thousands of resistors are made in a day, it is not possible to adjust every ordinary resistor to an exact value. The term tolerance denotes the acceptable deviation in the resistance value of a resistor. The usual specified tolerances are 5%, 10% and 20% for ordinary resistors, while precision resistors have a tolerance close to 0.1%. For example, the resistance marked as 1 kW with a 10% tolerance can have any value between 900 W–1100 W. Table 2.2 gives the tolerance values for the various types of resistors.

Type of resistor

Tolerance

Fixed 1. Carbon composition

5% or above

2. Carbon film

5% or above

3. Metal film (a) Thin film (b) Thick film (i) (ii) (iii) (iv)

< 0.5%

Tin oxide Metal-glaze Cermet type Bulk film

< 1% < 1% 1% 0.005%

4. Wire wound (a) Power style (b) Precision style

5% to 20% < 0.5%

Variable 1. Potentiometer (a) Carbon type (b) Wire wound

10% to 20%

(i) Single turn (ii) Multi turn

10% to 20% 3%

2. Trimmer

10% ABCD

Resistors are coded to indicate the resistance value and tolerance. As shown in Fig. 2.9, there are four colour bands (A, B, C and D), one by the side of the another starting from the left end. The first two bands (A and B) denote the first and second digits of the resistance value and the third band (C) indicates how many zeros follow the first two digits. Tolerance is given by the fourth band (D). Figure 2.9 shows the colour code and tolerance values for the various colours. For example, a resistor with the following colour bands sequence Yellow-Violet-Orange-Gold denotes a 47000 W with 5% tolerance resistor.

First band-1st digit Second band-2nd digit Color Black Brown Red Orange Yellow Green Blue Violet Gray White Gold Silver No color

Digit 0 1 2 3 4 5 6 7 8 9 — — —

Multiplier 1 10 100 1000 10000 100000 1000000 10000000 — — 0.1 — —

Tolerance — ±1% ±2% — — — — — — — ±5% ±10% ±20%

Figure 2.10 shows n fixed resistors connected in series. The current I flowing through each resistor is the same in a series circuit. The total equivalent resistance of the series circuit RTS is equal to the sum of the individual resistances, i.e. R = R + R + .... + R TS

1

2

n

When all resistors have equal value, then RTS = nR R1

R2

R

I RTs

RTP

R1

R2

R3

Figure 2.11 shows n fixed resistors connected in parallel. Here, the voltage V across each resistor is the same. The total equivalent resistance of the parallel circuit RTP can be calculated by 1 1 1 1 ____ = ___ + ___ + ......... + ___ RTP R1 R2 R2 Considering two resistors R1 and R2 connected in parallel, the total equivalent resistance of the parallel circuit RTP is equal to their product divided by their sum, i.e. R1R2 RTP = _______ R1 + R2 R When all resistances are equal, then RTP = __ n.

Next to resistors, capacitors are the most widely used passive elements in circuits. Capacitors are the devices which can store electric charge. Capacitors may be used to build up sufficient electric charge to fire, for example, flash tube or a laser. They are used in tuned circuits, timing circuits, filters, amplifier circuits, oscillator circuits and relay circuits. They are also used for power factor correction and for starting single phase motors. The reactance of a capacitor of capacitance C at frequency f is given by 1 XC = _____ W 2p fC The capacitive reactance (XC) varies inversely with the frequency of the applied a.c. voltage. Therefore, the capacitor allows higher frequency currents more easily than lower frequency currents. For d.c. voltages, i.e. f = 0, XC = •. Hence, a capacitor blocks (cannot conduct) the d.c. voltage or current.

A capacitor essentially consists of two conducting plates separated by a dielectric material as shown in Fig. 2.12. The capacitance of a parallel-plate capacitor is given by A C = e0 er __ d where A = area of each plate in m2 d = distance between parallel plates in m 10–9 eo = dielectric constant (permittivity) of free space = ____ F/m 36p = 8.854 × 10–12 F/m er = relative dielectric constant (permittivity).

Dielectric

Conducting plates (+)

Rs

C (–) (a)

(b)

(c)

For large capacitance, the area A and the value of the relative permittivity of the dielectric er, must be large, while d must be very small. Larger capacitances can be obtained by using high permittivity dielectrics of smaller thickness. When a voltage V is applied across the capacitor plates, the electrons accumulate on the side of the capacitor connected to the negative terminal of the voltage source. The plate connected to the positive terminal of the voltage source loses electrons. This accumulation of electrons produces a negative charge on one side of the capacitor, while the opposite side has a positive charge. Thus, with the application of voltage, the electrons are simply redistributed from one side of the capacitor to the other. This redistribution process of the electrons is called the charging of the capacitor. The charging continues until the potential difference across the capacitor is equal to the applied voltage. The more the applied voltage, the stronger is the electric field and more charge is stored in the dielectric. The amount of charge q stored in the capacitor is, therefore, proportional to the applied voltage. Also, a large capacitance can store more charge. These relations can be mathematically expressed as Q = CV coulombs where Q = charge stored in the dielectric, V = voltage across the capacitor, and C = capacitance of the capacitor. From the above equation, when one coulomb is stored in the dielectric with a potential difference of one volt, the capacitance is one farad. In order to store a given charge, more voltage is needed for a small capacitor and less voltage for a large capacitor. The maximum voltage that can be impressed across a

capacitor, without causing irreparable damage depends on the dielectric used and the separation d of the plates. In a capacitor, the dielectric strength is the ability of a dielectric to withstand a potential difference without breakdown. This voltage rating is very important because breakdown of the insulator provides a conducting path through the dielectric. Since the breakdown voltage increases with greater thickness, capacitors of higher voltage ratings have more distance between the plates. The increased distance between the plates reduces the capacitance. A charged capacitor has energy stored in the electric field existing between its plates. The expression for stored energy is 1 W = __ CV2 2 The typical values of dielectric constant and dielectric strength of various dielectric materials are shown in Table 2.3.

Material

Dielectric constant

Dielectric strength volts/mil (breakdown)

Air or vacuum

1

20

Plastic film

2–3.5

1000–5000

Oil

2–5

500–1000

Paper

2.5–6

500–1000

Mica

3–8

600–1500

Glass

4–7

10 pF

Black

0

Brown

1

Red

2

0

×1

± 20%

± 2.0 pF

1

×10

± 1%

± 0.1 pF

– 33 × 10–6

2

×100

± 2%

± 0.25 pF

– 75 × 10–6

Orange

3

3

×1000

± 3%

Yellow

4

4

×10 k

± 100%

Tolerance Temperature T < 10 pF Coefficient TC

– 150 × 10

Working voltage V

250 V

–6

– 220 × 10–6

400 V

– 330 × 10–6

100 V

– 470 × 10

–6

630 V

– 750 × 10

–6

– 0% Green Blue

5 6

5 6

Violet

7

7

Grey

8

8

×100 k

± 5%

×1m

× 0.01

± 0.5 pF

+80% – 20%

White

9

9

× 0.1

± 10%

Figure 2.23 shows a coding system used A B with film-type capacitors. The first two digits of the code indicate the D first two digits in the numerical value of the capacitance. The third V digit is the multiplier included to the right, which will yield the value in pF. For example, if a capacitor is with 563J marked on it, then 10 nF, 20% 100 V the first two digits are 56 and the third digit 3 represents three zeros to be appended to the right as 56000 pF, which is equal to 56 nF or 0.056 mF. The last letter ‘J’ at the right indicates the capacitor tolerance of ± 5%.

A B D T V 47 nF, 10% 240 V

The capacitance of the disc ceramic capacitors is labeled either as a whole number or as a decimal fraction as shown in Fig. 2.24. In order to calculate the value of colour-coded tantalum capacitors, they are colour coded as resistors as given in the Table 2.7. The first and second bands of capacitors are the significant number bands, the third is the multiplier, followed by the percentage tolerance band, through not all tantalum caps have a tolerance band, and the voltage band. If there are only four colours, then the last is the voltage and there is no tolerance ID.

Film-type capacitors First digit of value

5 6 3

Tolerance

Second digit of value

J

Multiplier

Multiplier

Tolerance of capacitor

For the number

Multiplier

Letter

10 pF or less

0 1

1 10

B C

± 0.1 pF ± 0.25 pF

2 3

100 1,000

D F

± 0.5 pF ± 1.0 pF

4 5

10,000 100,000

G H

± 2.0 pF

Over 10 pF

± 1% ± 2% ± 3%

8

0.00

J K

± 5% ± 10%

9

0.1

M

± 20%

Mica capacitors are coded using coloured dots to represent the value of the capacitance in pF. Mica capacitor coding system is given in Table 2.8. Three different coding systems for mica capacitors are described below: The colour dots must be read in the correct sequence (A, B, C) from left to right in order to correctly interpret the colour code. In order to make certain that the capacitor will be held in the proper position while the dots are being read, manufactures have adopted several 3-dot marking arrangements. The capacitor must be held so that the name of the manufacturer appears right side up, as shown. Then the dot will be read in the proper sequence if they are read from left to right. Another common arrangement is to have the three coloured dots stamped on an arrow molded in the capacitor case. The arrow always points to the correct direction of reading. Example

Red, Green, Black = 25 pF = 0.000025 mF

Two extra colour dots are included in five-dot colour-coded capacitors, on the face or on the reverse side of the molded case. The colour of the fourth dot (D) indicates the d.c. voltage rating. No colour in this position implies a voltage rating of 500 volts d.c.

Ceramic Disk Capacitors Manufacturer’s code Capacitance value Tolerance *Working voltage Temperature range *If no voltage marked, generally 500 V d.c.

ABC 100J NPO

ABC .0022 K 1kV Z5F

(a) Typical ceramic disk capacitor markings 1

0

0

1st & 2nd Fig. of capacitance

J

Letter Multiplier Numerical Tolerance on symbol capacitance symbol 0 1 2 3 4 5 — — 8 9

1 10 100 1,000 10,000 100, 000

0.01 0.1

± 5% ± 10% ± 20% + 100%, – 0% + 80%, – 20%

J K M P Z

(b) Capacity value and tolerance of ceramic disk capacitors Z

Low Letter temp. symbol ± 10°C – 30°C – 55°C

Z Y X

High temp. ± 45°C ± 65°C ± 85°C ± 105°C ± 125°C

5

F

Max. Numerical capacitance Letter symbol change over symbol temp. range ± 1.0% 2 A 4 ± 1.5% B 5 C ± 1.1% 6 ± 3.3% D 7 E ± 4.7% F ± 7.5% P ± 10.0% R ± 15.0% S ± 22.0% ± 22%, – 33% T ± 22%, – 56% U ± 22%, – 82% V

(c) Temperature range identification of ceramic disk capacitors

Colour

Capacitance in pF 1st figure 2nd figure

Multiplier (No. of zeros)

Rated voltage

Black

0

0

–

4

Brown

1

1

1

6

Red

2

2

2

10

Orange

3

3

3

15

Yellow

4

4

4

20

Green

5

5

5

25

Blue

6

6

7

35

Violet

7

7

7

50

Grey

7

8

–

–

White

9

9

–

3

1st significant figure Multiplier 2nd significant figure Voltage

Colour

A First figure

B Second figure

C Number of zeros

D Voltage rating

E Tolerance

Black

0

0

0

Brown

1

1

1

100

1%

Red

2

2

2

200

2%

Orange

3

3

3

300

3%

Yellow

4

4

4

400

4%

Green

5

5

5

500

5%

Blue

6

6

6

600

6%

Violet

7

7

7

700

7%

Grey

8

8

8

800

8%

White

9

9

9

900

9%

Gold

1000

5%

Silver

2000

10%

500

20%

No Colour

The colour of the fifth dot (E) indicates the percent of tolerance on the accuracy of the capacity rating. No colour in this position indicates a tolerance of ± 20% in the capacity value. A 6-dot colour code is employed when there are three significant figures in the capacity value and the voltage rating and tolerance information is also to be represented. When six dots are marked on capacitors, the upper three (A, B, B1) indicate the capacity and the lower right hand dot (C) indicates the number of zeros to be added. The remaining two dots (D) and (E) indicate the d.c. working voltage rating and the capacity tolerance respectively, as shown in the illustration.

Example Brown, Red, Green, Orange, Green, Brown = 1250 pF, 300 d.c. working voltage ± 5%, tolerance Chip capacitors or surface mount capacitors do not have leads. They are used in aerospace, automotive, general-purpose, high voltage, high frequency, microwave, and telecommunication applications. Most chip capacitors are packed in tape reel assemblies, carbon-powder trays or rails, and shipping tubes or stick magazines. Bulk pack parts are distributed as individual products. Some chip capacitors are polarized or self-healing. There are three popular colour coding systems used by the different manufacturers of chip capacitors. The values represented in all three systems are in pF. As shown in Fig. 2.25 a two-place system in which a letter indicates first and second digits of the capacitance value and a number indicates the multiplier (number of zeros to be appended). Thirtythree symbols consisting of 24 upper case letters and 9 lower case letters are used to represent the two significant figures. For example, L3 represents 2700 pF. Value (33 Value Symbols) – Upper and Lowercase Letters

Multiplier

A = 1.0

H–2.0

b–3.5

f–5.0

X–7.5

0 = × 1.0

B = 1.1

J–2.2

P–3.6

T–5.1

t–8.0

1 = × 10

C = 1.2

K–2.4

Q–3.9

U–5.6

Y–8.2

2 = × 100

D = 1.3

a–2.5

d–4.0

m–6.0

y–8.0

3 = × 1000

E = 1.5

L–2.7

R–4.3

V–6.2

Z–9.1

F = 1.6

M–3.0

e–4.5

W–6.8

5 = × 100000

G = 1.8

N–3.3

S–4.7

n–7.0

etc.

L3

= 2.7 × 1000 = 2700pF Multiplier (0-9) st

nd

Value of 1 and 2 digits

4 = × 10000

As shown in Fig. 2.26, values below 100 pF are marked using two numbers from which the capacitance value is read directly. The values above 100 pF are indicated by a letter and a number. In this system, only 24 upper case letters are used to represent the first two digits in the capacitance value and the number represents the number of zeros to be appended. For example, U1 represents 560 pF and J3 represents 22000 pF. Value (24 Value Symbols) – Uppercase Letters Only

Multiplier

A–10

F–16

L–27

R–43

W–68

1 = × 10

B–11

G–18

M–30

S–47

X–75

2 = × 100

C–12

H–20

N–33

T–51

Y–82

3 = × 1000

D–13

J–22

P–36

U–56

Z–91

4 = × 10000

E–15

K–24

G–39

V–62

5 = × 100000 etc.

08

= 8 pF

68

= 68 pF

(a) Values below 100 pF value read directly

U1

= 56 × 10 = 560 pF

J3

= 22 × 1000 = 22000 pF = 0.022 mF Multiplier (0-9) st

nd

Value of 1 and 2

digits

(b) Values of 100 pF and above letter/Number code

As shown in Fig. 2.27, a single letter or number is used to designate the first two digits in the capacitance value. The multiplier is determined by the colour of the letter. For example, a green coloured W represents a capacitance of 470 pF. Similarly, an orange coloured R represents 33 pF and a blue coloured 7 represents 8200 pF.

Figure 2.28 shows n capacitors connected in parallel. Here, as the effective area of the plates increases, the total equivalent capacitance of the parallel circuit CTP increases with plate area (more charge is stored in the capacitor). Hence, CTP is equal to the sum of the individual capacitances, i.e., CTP = C1 + C2 + º + Cn When all capacitors are equal, then CTP = nC. The relationship for CTP is similar to that for resistors in series.

Value (24 Value Symbols) – Uppercase Letters and Numerals

Multiplier

A–1.0

H–1.6

N–2.7

V–4.3

3–6.8

Orange = × 1.0

B–1.1

I–1.8

O–3.0

W–4.7

4–7.8

Black = × 10

C–1.2

J–2.0

R–3.3

X–5.1

7–8.2

Green = × 100

D–1.3

K–2.2

S–3.6

Y–5.6

9–9.1

Blue = × 1000

E–1.5

L–2.4

T–3.9

Z–6.2

Violet = × 10000 Red = × 100000 etc.

Green W

= 4.7 × 100 = 470 pF Colour multiplier Symbol value

CTP C1

C2

Cn

Figure 2.29 shows n capacitors connected in series. Here, as the separation of the outer plates of the combination increases, the total equivalent capacitance of the series circuit CTS will be less than the smallest capacitance of the individual capacitors. The value of CTS can be calculated by 1 1 1 1 ____ = ___ + ___ + º + ___ CTS C1 C2 Cn The relationship for CTS is similar to that for resistors in parallel. Considering two capacitors, C1 and C2, connected in series, the total equivalent capacitance of the series circuit CTS is equal to their product divided by their sum, i.e., C1 C2 CTS = _______ C1 + C2 C When equal valued capacitors are connected in series, then CTS = __ n.

C1 C2 CTS

The characteristics and applications of various types of capacitors are summarised in Table 2.9.

Cn

Aluminium electrolytic

Tantalum electrolytic

Silvered ceramic

Ceramic with high dieletric constant

Polyesterene

Polyester

Stacked mica

Silvered mica

Tubular rolled paper

Metallised paper

Air/polystyrene variable capacitance

Mica trimmers and padders

Air trimmers

1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

11.

12.

13.

Type

8 pF – 100 pF

4 pF – 70 pF 100pF – 600pF

—

—

1000.0

0.005 – 0.015

0.005 mF – 25% 15 pF – 500 pF

0.004 – 0.01

0.005 mF – 10 – 20%

0.005

0.005 – 2 mF – 10 – 20% 0.001 – 0.005

0.002

100 pF – 0.5 mF – 1/2 – 5%

0.001 – 0.005

0.001

50 pF – 0.01 mF 20%

50 pF – 0.01 mF – 2 – 20%

0.001

2 pF – 0.001 mF 1 – 20%

10 pF – 0.1 mF – 1/2 – 20%

6 – 150

-do-

500

1000

400

1000

1000

2000

500

125 – 500

350

350

50 – 200 -do-

600

1 mF – 2000 mF – 2.5%

0.02 – 0.2

(i) 2 mF – 100 mF – 15%

Maximum working voltage (in volts)

(ii) 50 mF – 1000 mF – 15%

Power factor

Approximate capacitance range and tolerance

-do-

80°C

-do-

-do-

85°C – 125°C

85°C – 150°C

85°C – 120°C

65°C – 125°C

65°C – 85°C

-do-

85°C – 150°C

-do-

-do-

85°C – 125°C

Operating temperature

-do-

Tracking and alignment of receivers

Tuning circuits in receivers and transmitters

-do-

a.f. coupling and decoupling, bypass, filter, motor-start

r.f. resonant and measuring circuits

r.f. coupling, bypassing circuits

Coupling, decoupling, smoothing and d.c. applications

Resonant, coupling, measuring and a.c. applications

-do-

r.f. amplifiers, r.f. bypass, decoupling and resonant circuit

Coupling, decoupling, bypassing in amplifiers

Decoupling and bypassing in a.f.

Rectifier filters and smoothing

Typical applications

This is the third passive component used in electronic circuits. It stores energy in the form of magnetic field and delivers it as and when required. Whenever current passes through a conductor, lines of magnetic flux are generated around it. This magnetic flux opposes any change in current due to the induced e.m.f. This opposition to the change in current is known as inductance and the component producing inductance is known as inductor. The unit of inductance is Henry (symbol H). The induced e.m.f. is actually given by di e = – L __ dt where e = induced e.m.f. in volts at any instant, L = inductance in Henry, and di/dt = rate of change of current. The negative sign in the above equation indicates that the induced e.m.f. opposes the cause for the change in current. An inductor is usually a coil of copper wire wound around a core made up of a ferromagnetic material, as shown in Fig. 2.30. The inductance (L) of the coil is given by mo mr A N2 L = _________ H l where mo = permeability of free space = 4p × 10–7 H/m = 1.257 × 10–6 H/m

N-Turns

A

mr = relative permeability of the core material A = area of cross-section of the core N = number of turns of the coil l = length of the core. Hence, the value of the inductor depends upon the following factors: (i) number of turns, (ii) permeability of the core material, and (iii) size of core. Inductors can be divided into two categories: (i) fixed inductors and (ii) variable inductors.

Fixed type inductors can be further divided into three categories depending on the type of core used. They are (i) air core inductors, (ii) iron core inductors, and (iii) ferrite core inductors. These three types of inductors are shown in Fig. 2.31.

m

l

In radio frequency applications where very low values of inductance (from a fraction of a mH to a few mH) is required, air core inductors are generally used. Air core inductors consist of a few turns of wire wound on a hollow former. They have a coil containing a number of turns of copper wire wound on a hallow former and the core material passes through the former in such a way that it forms a closed magnetic path for the magnetic flux. The former is made up of paper or plastic material. The core is generally made up of silicon steel (a ferromagnetic material having high permeability) in the form of thin laminated sheets. Laminated sheets are used instead of solid mass to reduce the hysteresis and eddy current losses. Iron core transformers are used in low frequency applications such as filter circuits in power supplies, chokes in fluorescent tubes or as a reactive element in a.c. circuits. The value of inductors are generally in the order of a few Henries. Iron core inductors are not suitable for high frequency applications (because of enormous increase in hysteresis and eddy current losses). This difficulty is overcome by the use of ferrite materials as the core. A ferrite is basically an insulator having very high permeability. Ferrite is made up of non-metallic compounds consisting mainly of ferric oxide in combination with one or two bivalent metal oxides. They are hard, dense ceramics and because of their high resistivity they can be used in the form of solid cores. The values of such inductors is in the range of few mH to few mH. The typical applications of ferrite core inductors are in (i) r.f. chokes for supply decoupling purposes, (ii) switching regulated type d.c. power supplies, and (iii) various types of filters used in communication equipment.

In certain applications such as tuned circuits, it is required to vary the inductance from a minimum value to a maximum value. Ferrite core variable inductors are generally used for this purpose. In such inductors the hollow former on which the coil is wound has screw threads in the inner hollow portion. Similar matching threads are provided on the ferrite core which can be screwed in or out of the former. Because of the change of the position of the ferrite core the value of the inductance changes. It is maximum when the ferrite core is fully in. The variable ferrite core inductor is shown in Fig. 2.32.

The reactance of an inductor of inductance L at frequency f is given by XL = 2p f L The value of inductive reactance offered by a coil is not constant but depends on frequency of the alternating current passing through it. At higher frequencies, the inductive reactance XL is large and at lower frequencies, XL is small. For d.c. current, i.e. at f = 0, XL = 0. Therefore, the inductor allows very low frequency currents more easily than higher frequency currents. Also, for a given frequency, XL depends directly on coil inductance L.

In an inductor, the strength of the magnetic flux is directly proportional to the amount of current flowing through it. If the current flowing through an inductor increases, the strength of the magnetic

flux also increases. This increase in flux represents energy taken from the circuit or the applied voltage source. When the current flowing through the inductor decreases, the magnetic flux also decreases. The decrease in magnetic flux returns energy stored in the magnetic field to the circuit. The amount of energy stored is 1 W = __ L I2 (Joules) 2 where L = self-inductance of an inductor, and I = current flowing through an inductor. The inductor does not dissipate power like resistor. Only when the value of current flowing through the inductor changes, the energy storage in the inductor takes place.

Though there is no power loss in an ideal inductor, losses do occur in a practical inductor. These losses are of two types (i) I2R loss (ohmic loss in the copper wire), and (ii) hysteresis and eddy current losses in the core.

_________

Ls

Rs

An equivalent circuit of a practical inductor is shown in Fig. 2.33 in which Rs is the effective resistance of the inductor which accounts for the total losses. The value of impedance (Z) of the practical inductor is given by __________

Z = ÷R2s + XL2s = ÷R2s + w2 L2s

wLs Q = ____ Rs which is the ratio of the inductive reactance (wLs) to the effective resistance is known as the Q of an inductor. This is also called as the Quality factor or figure of merit of an inductor. The quantity

When two coils are placed very near to each other as shown in Fig. 2.34, the changing magnetic flux of one coil, linking with the other, produces an induced e.m.f. in the other coil. These two coils are then set to have mutual inductance (M), which is expressed Magnetic flux in Henries (H). mo mr A N1 N2 M = ____________ l where l is the length of the magnetic path. Let the rate of current change through the first coil di be __. This changing current will produce a changdt ing magnetic flux through it which will link partly or fully with the second coil. Hence, an induced e.m.f. e2 will be produced in the second coil, which is given by di e2 = M __ dt

i

e1

Coil-1 (L1)

N1

N2

M

Coil-2 (L2)

e2

The mutual inductance of a coil depends upon the self-inductances of the coils and the coefficient of coupling between them. The mutual inductance (M) between the two coils can be computed from the equation _____

M = k ÷L1 L2

where k = coupling coefficient (there are no units for k), L1 = self-inductance of coil 1, and L2 = selfinductance of coil 2. From the above equation, we get the coupling coefficient, M _____ k = ______ ÷L1 L2 If the maganetic flux produced by one coil does not link with the other coil, then k = 0. If all the flux produced by one coil links with the other, then k = 1. A coupling coeffcient of 1, or 100 per cent coupling is approached only in well-designed iron-core transformers and chokes. In air-core transformers and coils it is very much less but increases in transformers with iron-power and ferrite cores. Air-core coils have k value of 0.05 to 0.3.

The combined inductance of any two coils connected in series aiding and having self-inductances of L1 and L2, respectively, will be given by L = L1 + L2 + 2M But if the coils are connected in series opposing, their combined inductance will be L = L1 + L2 – 2M If two coils are connected in parallel with fields aiding, then 1 ________ 1 1 __ = + ________ L (L1 + M) (L2 + M) And for two coils in parallel with fields opposing, then 1 ________ 1 1 __ = + ________ L (L1 – M) (L2 – M)

The operation of an electronic device depends upon the motion of electrons under the influence of electric and magnetic fields. The behaviour of an electron under the influence of these fields is termed as electron ballistics. This chapter deals with the study of basic properties of matter. This chapter starts with simple definitions, motion of particles in simple paths under uniform fields to complex paths under varying fields.

Electron forms the most fundamental charged particle. An electron is negatively charged; its magnitude is 1.602 × 10–19 Coulomb. The number of electrons per coulomb is 6 × 1018 and 1 A of current represents the motion of 6 × 1018 electrons per second. The mass of an electron is 9.107 × 10–31 kg. A direct measurement of mass of an electron is not possible but the ratio of electron’s charge to mass can be determined by a number of experiments and found to be 1.759 × 1011 C/kg. The mass of an electron can be deduced from this value. The positive ion possesses a charge that is an integral multiple of the charge of an electron and is positive. If a positive ion is singly ionized, it has a charge equal to that of an electron and if it is doubly ionized, its charge is twice that of an electron. The mass of a hypothetical atom of atomic weight unity is, as per definition, taken as one-sixteenth of the mass of monoatomic oxygen and has been calculated to be 1.660 × 10–27 kg. Hence, the mass of any atom, in kilogram, can be calculated by multiplying the atomic weight of the atom by 1.660 × 10–27 kg. The radius of an electron is very small. It is estimated to be much closer to 3.8 × 10–10 m. The radius of an atom is estimated as 10–10 m. These dimensions being very small, all charges are considered to be mass points.

Charles Coulomb stated that the force between two very small objects separated by a distance which is large compared to their size is proportional to the charge on each and inversely proportional to the square of the distance between them, or

Q1Q2 F = k _____ (3.1) d2 where Q1 and Q2 are the charges, d the separation, and k the proportionality constant. In SI units, Q is measured in Coulombs (C), d in metres, and the force should be in Newtons (N). This will be achieved if the constant of proportionality k is written as 1 k = _____ (3.2) 4p eo where eo is the permittivity of free space and has a value of 8.854 × 10–12 F/m. Coulomb’s law shows that the force between two charges of 1 C each, separated by one metre, is 8.9 × 109 N and that between two electrons is 230 × 10–13 N. The electric field intensity is defined as the force on a unit positive charge, intensity E at that point. The unit of electric field intensity is volts per metre (V/m). If a charge is moved against the electric field, a force equal to and opposite to the force exerted by the field is needed, and this requires expending energy or doing work. On the other hand, if the charge is moved in the direction of the field, the energy expenditure turns out to be negative; we do not do the work, the field does. When a charge q is moved in an electric field E, the force on q due to the electric field is Fq = qE

(3.3)

The path of a charged particle in an electric field can be calculated by relating the force, given by Eqn. (3.3), to the mass and the acceleration of the particle by Newton’s second law of motion. Thus, dV Fq = qE = ma = m ___ dt where m = mass, kg; a = acceleration, m/s2; and V = velocity, m/s.

(3.4)

The solution of this equation with appropriate initial conditions gives the path of the particle resulting from the action of the electric forces. Consider a parallel-plate capacitor as shown in Fig. 3.1. A difference of potential is applied between the two plates as shown. The separation between the two plates is much smaller in comparison with the dimensions of the plates. This ensures uniform electric field between the plates, the lines of force pointing along negative Z-direction. At time t = 0, the initial velocity vz is equal to zero. Since there is no force along the X or Y directions, the acceleration along these directions is zero and since the initial velocity is zero, the particle will not move in these axes. By definition, the potential V (in volts) of point Z with respect to point Zo is the work done against the field in taking a unit positive charge from Zo to Z.

Z

z

+ V –

d

z0

X

Y

z

V = – Ú E ◊ dz

Thus,

(3.5)

zo

The integral in Eqn. (3.5) can be evaluated to the form z

– Ú Ez ◊ dz = – Ez (z – zo) = V

(3.6)

zo

V V __ Ez = – _____ (3.7) z – zo = – d Thus, from Eqn. (3.7), the electric field intensity is negative of the ratio of applied potential difference between the two plates to the separation between the two plates. Equation (3.7) is valid for uniform electric fields; however, for fields varying with distance between the plates the field is given by dV Ez = – ___ (3.8) dz The negative sign in Eqn. (3.8) signifies that the orientation of the electric field is from higher potential point to lower potential point. For an electron between two parallel plates, the Newton’s second law can be applied. Then, – q Ez = ma

(3.9)

dvz q ___ – __ m Ez = dt

(3.10)

The velocity of the particle in Z direction is defined as the rate of change of displacement of the particle in Z direction, i.e., dz vz = ___ dt dz = vz dt

(3.11)

Multiplying Eqn. (3.10) by Eqn. (3.11) and integrating, z

v

z

v

o

oz

z dvz q ___ – __ E dz = ◊ vz ◊ dt Ú Ú mz z voz dt o z q – __ E dz = vz ◊ dvz Ú Ú z mz v

By virtue of Eqn. (3.5), Eqn. (3.12) integrates to q 1 2 2 __ __ m V = 2 ( vz – voz ) 1 2 qV = __ m ( v2z – voz ) 2 where the energy qV is expressed in Joules.

(3.12)

(3.13)

Considering any two points A and B in space, with B at a higher potential than A by VBA, Eqn. (3.13) can be stated in a more general form, 1 1 q VBA = __ m V 2A – __ m V 2B (3.14) 2 2

where q is the charge in Coulombs, qVBA in Joules, and VA and VB are the initial and final velocities in metres per second. By definition, the potential energy between two points equals the potential multiplied by the charge. Equation (3.14) is a statement of Law of Conservation of Energy. The left-hand side of Eqn. (3.14) is the rise in potential energy from A to B and the right-hand side is drop in kinetic energy from A to B. Thus, the rise in potential energy equals the drop in kinetic energy. Equation (3.14) is not valid for time-varying fields.

Find the speed and the kinetic energy of an electron after it has moved through a potential difference of 5000 V. ______________________

____

Solution

The speed of the electron, v =

÷

÷

2qV 2 × 1.602 × 10–19 × 5000 ____ _____________________ = = 4.2 × 107 m/s m 9.1 ×10–31

The kinetic energy = q × V = 1.602 × 10–19 × 5000 = 8 × 10–16 J = 5000 eV

A charged particle having mass equal to 1000 times of an electron and a charge same as that of an electron is accelerated through a potential difference of 1000 V. Calculate the velocity attained by the charged particle and kinetic energy in terms of electron volts and joules.

Solution

The mass of the charged particle = 1000 times the mass of an electron = 1000 × 9.1 × 10–31 = 9.1 × 10–28 kg

The charge of the particle Therefore, the velocity, m s–1 Kinetic energy

= 1.602 × 10–19 C ____

v=

÷

_______________________

÷

2qV 2_______________________ × 1.602 × 10–19 × 1000 ____ = = 0.596 ×106 m 9.1 × 10–28

=q×V =1.602 × 10–19 × 1000 = 1.6 × 10–16 J = 1000 eV

The following assumptions are made in the following analysis: (i) the charge density is low enough so that the mutual repulsive force may be neglected. (ii) the movement of the charged particle is in high vacuum so that no collision with gas atoms or ions occur, and (iii) the mass of the charged particle is extremely small so that the gravitational force may be neglected as compared to the forces exerted by the fields. Consider a parallel plate capacitor with uniform electric field in between the plates. If an electron enters the region between the two plates with an initial velocity in the +X direction, the electron is made to move in a parabolic path. Referring to Fig. 3.2, the electric field E is in the –Y direction, and no other fields are existing in other directions.

Y

The initial conditions, at t = 0, are

l

vx = vox, x = 0 vy = 0,

y =0

vz = 0,

z =0

+

vox

Let us analyse the fields in the different axes.

d

X

vd

Since no field is present in this direction, force is also zero (since F = e E). As the force is zero, the e – acceleration along the Z-direction is also zero (since F = ma). The zero acceleration means no change in the velocity component in Z-direction. Since the initial velocity vz = 0, the final velocity must also be zero. Hence, there is no movement of electron in the Z-direction. The electron moves with a constant velocity of vox in the X-direction, for the same reasons given above. The field is in the –Y-direction, which is uniform. Hence, F is also uniform and constant, which makes the electrons to have a constant acceleration along the Y-direction. The motion in the Y-direction is given by 1 y = __ ayt2 2

vy = ayt

(3.15)

where ay is the acceleration along the Y-direction, and using Newton’s second law, Ey qVd ____ ay = – q ___ m = md

(3.16)

where Vd is the potential across the plates and d is the separation. The above equations indicate an upward motion of the electron in the region between the plates. The velocity component vy changes from point to point, whereas the velocity component vx remains unchanged. The distance covered by an electron along the X-direction is given by x = vox t

(3.17)

Combining Eqs (3.15) and (3.17), x 1 1 y __ ayt2 = __ ay ___ vox 2 2

( )

2

1 ay 2 y = __ ___ x 2 2 vox

( )

y = kx2

1 ay where k = __ ___ 2 2 vox

( )

(3.18)

Equation (3.18) shows that the electron moves in a parabolic path in the region between the plates.

In a parallel plate diode, anode is made 350 V positive with respect to the cathode and is 6 mm from it. An electron is emitted from the cathode with an initial velocity of 3 × 106 m/s in the direction of the anode. Calculate the velocity and the time of travel of the electron (i) when it is midway between cathode and anode, and (ii) on reaching the anode.

Solution

V = 350 V, d = 6 mm, vox = 3 × 106 m/s

Given

E = V/d = 350/(6 × 10–3) = 58.33 × 103 V/m

Therefore,

ax = qE/m = 1.026 × 1016 m/s2 We know that, x = voxt + 0.5 at2 vx = vox + axt –3

(i) Consider x = 3 × 10 m 3 × 10–3 = 3 × 106t + 5.13 × 1015 t2 t2 + 5.85 × 10–10 t – 5.85 × 10–19 = 0 Solving this equation, t = 5.26 × 10–10 s vx = vox + ax t = 3 × 106 + 1.026 × 1016 (5.264 × 10–10)

Therefore,

= 8.4 × 106 m/s (ii) Consider x = 6 × 10–6 m t2 + 5.85 × 10–10 t – 1.17 × 10–18 = 0 t = 8.28 × 10–10 s

Solving this equation,

vx = 3 × 106 + 8.28 × 10–10 (1.026 × 1016) = 11.5 × 106 m/s

Therefore,

In a parallel diode, the cathode and anode are spaced 5 mm apart and the anode is kept at 200 V d.c. with respect to cathode. Calculate the velocity and the distance travelled by an electron after a time of 0.5 nsec, when (a) the initial velocity of an electron is zero and (b) the initial velocity is 2 × 106 m/sec in the

direction towards the anode. Solution

Given V = 200 V, d = 5 mm, Time of travel by an electron, t = 0.5 nsec.

Therefore,

We know that

V 103 V 200 E = __ = _______ = 40 × _____ m –3 d 5 × 10 qE _____________________ 1.602 × 10–19 × 40 × 103 = 70.33 × 1014 m/sec2 ax = ___ = m 9.1 × 10–31

Velocity of an electron,

vx = vox + axt

Distance travelled by an electron, x = vox + 0.5at2 (a) When the initial velocity of an electron is zero vx = vox + axt = 0 + 70.33 × 1014 × 0.5 × 10–9 = 3.5165 × 106 m/sec x = voxt + 0.5 at2 = 0 + 0.5 × 70.33 × 1014 × (0.5 × 10–9)2 = 0.879 × 10–3 m 106 m (b) When the initial velocity of an electron is vox = 2 × ______ sec vx = vox + axt = 2 × 106 + 70.33 × 1014 × 0.5 × 10–9 = 5.51 × 106 m/sec x = voxt + 0.5 at2 = 2 × 106 × 0.5 × 10–9 + 0.5 × 70.33 × 1014 × (0.5 × 10–9)2 = 1.879 × 10–3 m

Two plane parallel plates A and B are placed 3 mm apart and potential of B is made 200 V positive with respect to plate A. An electron starts from rest from plate A. Calculate (i) the velocity of the electron on reaching plate B, (ii) time taken by the electron to travel from plate A to plate B, and (iii) kinetic energy of the electron on reaching the plate B.

Solution (i) The electron starts from rest at plate A, therefore, the initial velocity is zero. The velocity of the electron on reaching plate B is, _____

__________________

÷

2 qV 2(1.602 × 10–19) 200 _________________ v = _____ = = 8.38 × 106 m/s m (9.1 × 10–31)

÷

(ii) Time taken by the electron to travel from plate A to plate B can be calculated from the average velocity of the electron in transit. The average velocity is Initial velocity + Final velocity 0 + 8.38 × 106 vaverage = ___________________________ = _____________ = 4.19 × 106 m/s 2 2 Therefore, the time taken for travel is Separation between the plates 3 × 10–3 Time = __________________________ = _________6 = 0.71 × 10–9 s. Average velocity 4.19 × 10 (iii) Kinetic energy of the electron on reaching the plate B is Kinetic energy = q V = (1.602 × 10–19) 200 = 3.2 × 10–17 J

Two plane parallel plates A and B are placed 8 mm apart and plate B is 300 V more positive than plate A. The electron travels from plate A to plate B with an initial velocity of 1 × 106 m/s. Calculate the time of travel.

Solution

The speed acquired by the electron due to the applied voltage is, ___________

÷

2qV v = v2initial + ____ m ____________________________

÷

2(1.602 × 10–19) 300 = (1 × 106)2 + _________________ 9.1 × 10–31 = 10.33 × 106 m/s The average velocity, vinitial + vfinal 1 × 106 + 10.33 × 106 vaverage = ___________ = ___________________ = 5.665 × 106 m/s 2 2 Therefore, the time for travel separation between plates __________ 8 × 10–3 = ______________________ = = 1.4 × 10–9 s vaverage 5.665 × 106 An infinitely large parallel plane plates are spaced 0.8 cm apart. The voltage at one of the plates is raised from 0 to 5 V in 1 ns at a uniform rate, with respect to the other. After duration, the potential difference between the plates is suddenly dropped to 0 V and remains the same thereafter. Find (i) the position of the electron, which started with zero initial velocity from the negative plate, when the potential difference drops to zero volt, (ii) the total time of transit of the electron from the cathode to the anode.

Solution

The electric field intensity, 5t 5t E = – ______ = – _____________ = 5 × 1011 t (for 0 < t < t1) 10–9 d 10–9 × 1 ×10–2

(for t1 < t < •) qE x The velocity of electron, vx = – Ú ____ m d t + C (C is the initial velocity) q = Ú 5 × 1011 __ m t dt q __ t2 = 5 × 1011 __ m◊ 2 The distance travelled by the electron, q __ t2 d = Ú vx dt = Ú 5 × 1011 __ m ◊ 2 dt + C (C = 0) q __ t2 = 5 × 1011 __ m◊ 2 (i) The position of the electron after 1 ns, (1 × 10–9)3 d = (5 × 1011) ◊ (1.76 × 1011) ◊ _________ 6 –6 = 14.7 × 10 m = 14.7 mm =0

(ii) The rest of the distance to be covered by the electron = 0.8 cm – 14.7 mm = 0.799 cm Since, the potential difference drops to zero volt, after 1 ns, the electron will travel the distance of 0.799 cm with a constant velocity of

q __ (1 × 10–9)3 t2 11 11 _________ vx = 5 × 1011 __ ◊ = (5 × 10 ) ◊ (1.76 × 10 ) ◊ m 2 6 3 = 44 × 10 m/s Therefore, the time

0.799 × 10–2 d ___________ t2 = __ = = 1.816 × 10–7 s vx 44 × 103

The total time of transit of electron from cathode to anode = 1 × 10–9 + 1.816 × 10–7 = 1.826 × 10–7 s

The force acting on a conductor kept in a magnetic field is given by fm = B I L

(3.19)

where fm: B: I: L:

force acting on the conductor, N magnetic flux density, Wb/m2 current in the conductor, A length of the conductor, m.

fm

The direction of force is perpendicular to the plane consisting of the components of B and I that are mutually perpendicular, and is directed along the advance of a right-handed screw as illustrated in Fig. 3.3.

v

–

o

If an electron takes T seconds to travel a distance of L metres in the + l or v conductor, the total number of electrons passing through any crosssection of conductor in unit time is N/T, where N is the total number of electrons contained in the conductor. Thus the total charge per second crossing any point, i.e. the current is Nq I = ___ T BNqL fm = BIL = ______ T The factor L/T is the drift speed v m/s of the electrons. Hence, the force per electron is fm = qBv

B

(3.20) (3.21) (3.22)

If the particle is a positive ion, the direction of current and drift velocity are the same. If the particle is electron, the direction of the current is opposite to that of the drift velocity.

The magnetic force acting on a charged particle in a uniform magnetic field can be expressed as _

__

_

fm = a B × v

(3.23)

fm = qBv sin j

(3.24)

where j is the angle between the direction of the magnetic field and the direction of motion of the particle. From Eqn. (3.24), we see that the magnitude of the magnetic force is proportional to the charge of the particle, the magnetic flux density, the speed of the charged particle and the angle between the directions of motion of the charged particle and the magnetic flux density. If an electron is placed in a uniform magnetic field with zero initial velocity, then the magnetic force on the electron is zero, in accordance with Eqn. (3.24). If the electron moves along the direction of magnetic flux density, then the angle is zero and the magnetic force is zero. A particle whose initial velocity has no component normal to a uniform magnetic field will continue to move with constant velocity along the lines of flux since the magnetic force on the particle is zero. The magnetic force acting on an electron moving perpendicularly to the direction of the magnetic flux density is illustrated in Fig. 3.4. The magnetic field is perpendicular to the plane of paper and directed towards the reader. The electron is shown to enter the magnetic field from no-field region with an initial velocity vo. The direction of the current is opposite to that of the motion. Hence, the magnetic force is upwards and the electron will have a change in its direction of motion. At every point in the magnetic field, force acts on the electron and the resultant direction will be perpendicular to both the magnetic field and the direction of motion of electron at that point. At every instant the force fm is perpendicular to the direction of the particle and no work is done on the electron. This means that the kinetic energy is unaltered and the speed remains the same.

fm A¢

fm

r fm

No-field region

Magnetic field emanating from paper

fm

Vo A fm

This type of force makes an electron to move in a circular path with uniform speed. As shown in the figure, the direction of the magnetic force is always towards the centre, O, of the circle. This force is same as the centripetal force which always tries to push the electron towards the centre. Then mv2 ____ r = qBv where ‘r’ is the radius of circular path of the electron. From Eqn. (3.25),

mv2 mv r = ____ = ___ qBv qB

The angular velocity of the electron in radians per second is given by v qB w = __r = ___ m The time for one revolution is 2p _____ 2p m , T = ___ w = qB seconds

(3.25)

(3.26)

(3.27) (3.28)

The time taken by the particle to complete one revolution is also called the period. We see from Eqn. (3.26) that the radius is directly proportional to the velocity of the particle. The particles that move faster will traverse in larger circles and if the velocity is less the particles will be bent sharply in smaller circular paths. Whenever a charged particle enters a uniform magnetic field, with an initial velocity, v, not perpendicular to the magnetic field but makes an angle with the direction of field, as shown in Fig. 3.5, then the velocity can be resolved into two components, v sin j, the velocity component perpendicular to the field and v cos j, parallel to the field. These two velocity components make the particle to move simultaneously in two directions.

Z

V sin j j V cos j

Y

V

X

The velocity component parallel to the direction of flux makes the particle to move linearly along the direction of flux with no change in velocity. The perpendicular component of velocity makes the particle to move in a circular path as discussed above, with no change in the speed. The net effect, due to these concurrent motion, is that the electron takes a helical path as shown. The pitch of the helix is defined as the distance travelled by an electron along the direction of the magnetic field in one revolution, and is given by p = voy T

(3.29)

where T is the time for one revolution and voy is the initial velocity in the Y-direction. From Eqn. (3.28), 2pm p = _____ voy (3.30) qB An electron is accelerated through a potential of 40 V before it enters a magnetic field density of 0.91 Wb/m2 at an angle of 30 degrees with the field. Find the position of the electron after which it has completed one revolution in the field. _____

÷

2qVa 6 The velocity of the electron is = _____ m = 3.68 × 10 m/s 2pm The time taken for one revolution is T = _____ = 4 × 10–11 s Bq The pitch = T v cos q = 1.27 × 10–4 m Solution

Thus the electron has travelled 1.27 × 10–4 m.

A charged particle having charge thrice that of an electron and mass twice that of an electron is accelerated through a potential difference of 50 V before it enters a uniform magnetic field of flux density of 0.02 Wb/m2 at an angle of 25° with the field. Find (i) the velocity of the charged particle before entering the field, (ii) radius of the helical path, and (iii) time of one revolution.

Solution

The charge of the particle is, Q = 3 q and the mass of the particle is, M = 2 m.

(i) The velocity of the charged particle before entering the field is, ____ _______

____

6qV 2aV 2(3q) V v = ____ _______ = ____ M 2m (2m) _____________________

6 × (1.602 × 10–19) × 50 = _____________________ 2 × 9.1 × 10–31 = 5.14 × 106 m/s. (ii) The radius of the helical path is, Mv sin 2 mv sin r = ________ = _________ QB 3 qB –31 2 × 9.1 × 10 × 5.14 × 106 × sin 25° = ________________________________ 0.02 × 3 × 1.602 × 10–19 = 0.411 mm. (iii) Time for one revolution,

2 M 2 (2m) T = ______ = ________ BQ B (3q) 4 × 9.1 × 10–31 = _____________________ 0.02 × 3 × 1.602 × 10–19 = 1.19 × 10–9 s

35.5 When an electron is placed in a magnetic field with a period of rotation T = ____ × 10–12 s, so that the B trajectory of an electron is a circle.

(i) What is the radius described by an electron placed in a magnetic field, perpendicular to its motion, when the accelerating potential is 900 V, and B = 0.01 Wb/m2? (ii) What is the time period of rotation? Solution Therefore,

Given

35.5 T = ____ × 10–12 s, B = 0.01 Wb/m2, Va = 900 V B T = 3.55 × 10–9 s _____

Velocity, Radius,

__________________ 2qVa v = _____ = 2× 1.76 × 1011 × 900 = 17.799 × 106 m/s m 17.799 × 106 v mv r = ___ = ______ = ________________ = 10.11 mm qB (q/m)B 1.76 × 1011 × 0.01

When both electric and magnetic fields act simultaneously on an electron, no force is exerted due to the magnetic field and the motion of the electron is only due to the electric field intensity E. The electron

moves in a direction parallel to the fields with a constant acceleration. If the electric field is along the Y axis and magnetic field is along the –Y axis, the motion of the electron is specified by vy = voy – a t Integating Eg. (3.31), we get y 1 = voy t – __ at2 2 where a = qE/m is the magnitude of the acceleration.

(3.31)

If a component of velocity vox perpendicular to the magnetic field exists, initially, this component along with the magnetic field will set the electron in a circular motion. The radius of the circular path is independent of the electric field, but the velocity along the field changes with time. As a result of this, the electron travels in a helical path with the pitch changing with time.

Consider an electron starting from rest at the origin. Let the magnetic field be directed along the –Y direction and the electric field be directed along the –X direction. The electron is directed along the –X axis due to the electric field. The force due to the magnetic field is always normal to B, and there is no component of force along the Y direction, and the Y component of acceleration is zero. Thus, the motion along Y is given by fy = 0

vy = voy

y = voy t

(3.32)

assuming that the electron starts at the origin. Since the initial velocity is zero, the initial magnetic force is zero and due to the electric field the electron is directed along the +X axis. As the electron is accelerated in +X direction, the force due to the magnetic field is no longer zero. There will be a component of this force which is proportional to the X component of velocity and will be directed along the +Z axis. The path will thus bend away from the +X direction towards the +Z direction. The electric and magnetic forces interact with one another and the net force will finally make the electron to travel in a cycloidal path. __

__

The force due to electric field E is eE along the +X direction. The force due to magnetic field B is eBvx __ in the +Z direction and eBvz in the – X direction. Since B is in the Y direction, there is no force on the electron due to vy. From Newton’s law, the force in terms of three components is expressed by dvx fx = m ___ = eE – eBvz dt fy = 0 dvz fz = m ___ = eBvx dt eB E ___ __ Letting w = m and u = , we get B dvx ___ = wu – wvz dt dvz ___ = + wvx dt

(3.33) (3.34)

Differentiating the Eqn. (3.33) and combining with Eqn. (3.34), we get d 2vx dvz ____ = –w ___ = – w2 vx 2 dt dt Solving this linear differential equation, with the initial conditions vx = vz = 0, we get vx = u sin wt vz = u – u cos wt Integrating each of the above equations, with initial conditions x = z = 0, we get the coordinates x and z as u x = __ w (1 – cos wt) u z = ut – __ w sin wt u, Letting q = wt and Q = __ w then x = Q (1 – cos q)

(3.35)

z = Q ( 1 – sin q)

(3.36)

The parametric Eqns. (3.35) and (3.36) of a common cycloid are defined as the path generated by a point on the circumference of a circle of radius Q which rolls along a straight line, the Z-axis. This is shown in Fig. 3.6. In Fig. 3.6, P is the position of the electron at any time along the coordinates x and z (y = 0), Q is the radius of the rolling circle, q is the number of Q rotations through which the circle has rotated and x Q cos q w is the angular velocity of rotation of the rolling z X P circle. O From Fig. 3.6, it can be written as

Qq

x = Q – Q cos q

q

Q sin q C¢

Rolling circle C

z = Q q – Q sin q where these equations are similar to Eqns. (3.35) and (3.36). As illustrated in Fig. 3.6, 2Q is the maximum distance that the electron covers along X-axis, and it is equal to the diameter of the rolling circle. 2pQ is the distance covered along Z-axis, and it is equal to the circumference of the rolling circle.

The particle will have a constant velocity normal to plane through the projection of the path remains cycloid, when an initial velocity exists and it is directed parallel to the magnetic field. This path is called cycloidal helical motion.

2pQ

2Q

Z

Cycloidal path

When the electron is directed perpendicular to both the magnetic and electric fields, and if the total force on electron is zero, it moves only along Z-axis. Therefore, vox = 0, voy = 0, voz π 0 fx = 0 eE – eBvoz = 0 E Therefore, voz = __ u. B The velocity u does not depend on the charge or mass of the ions. The perpendicular electric and magnetic fields act as some sort of velocity filter, and only the particles having the velocity ratio of E/B get selected.

The magnetic flux density B = 0.02 Wb/m2 and electric field strength E = 105 V/m are uniform fields, perpendicular to each other. A pure source of an electron is placed in a field. Determine the minimum distance from the source at which an electron with 0 V will again have 0 V in its trajectory under the influence of combined Electric and magnetic fields.

Solution

Given,

B = 0.02 Wb/m2, E = 105 V/m

The initial velocity, vo = 0 Referring to Fig. 3.6, the minimum distance from the source at which an electron with 0 V will again have 0 V in its trajectory under the influence of combined electric and magnetic fields is given by u where Q = __ w and

2p u 2pQ = ____ w

w is the angular velocity of rotation of the rolling circle q is the number of radians through which the circle has rotated Q is the radius of the rolling circle u is the velocity of translation of the center of the rolling circle Here,

eB E __ w = ___ m and u = B

We know that,

e = 1.602 × 10–19 C and m = 9.109 × 10–31 kg = 9.109 × 10–28 g

Therefore,

1.602 × 10–19 × 0.02 eB __________________ w = ___ = = 3.5174 × 109 rad/sec m 9.109 × 10–28

and

E 105 u = __ = ____ = 5 × 106 m/sec B 0.02

Hence the minimum distance traveled by an electron in perpendicular electrical magnetic fields when the initial velocity is 0 is given by

2p u ____________ 2p × 5 × 106 ____ –3 w = 3.5174 × 109 = 8.932 × 10 m

The electrostatic deflection system uses a pair of deflection plates as shown in Fig. 3.7. The deflecting voltages are applied between the two plates. For deflecting the beam in the horizontal and vertical directions, two sets of plates are required. The horizontal deflection plates are kept vertically and the vertical deflection plates are kept horizontally, however, the plane of the plates are kept parallel to the axis of the Cathode ray tube. The electrons are attracted towards the positive plates and when they leave the region below the plates they travel in straight line, at an angle with the axis. Then the electron beam strikes the screen at a point. Vertical-deflecting plates D2

Anode

+ Vd

+ q

Cathode, K

d Vox

Va

A

C

D1

B

l

L x Fluorescent screen

Electrostatic deflection sensitivity of a pair of deflection plates of a CRT is defined as the amount of deflection (in mm or inch) of electron spot produced when a voltage of 1V d.c. is applied between the corresponding deflection plates. The deflection sensitivity may be different for X-X and Y-Y plates. The amount of deflection produced may be calculated knowing (i) the dimensions of the tube components and (ii) deflecting voltage. Figure 3.7 shows the configuration of the electrostatic deflection system in a CRT. Two plates of length l and spacing d are kept at a distance x from the screen. Let the voltage applied between the plates be Vd volts, vox be the velocity of an electron on entering the field of deflection plates. _______

Then,

÷

___ 2q 5 vox = ___ m ◊ Va = 5.94 × 10 ÷Va m/s

where Va is the final anode voltage (in volts), q is the charge of an electron in coulombs and m is the mass of an electron in kilograms. As the beam passes through the field of the deflection plates, the electrons are attracted towards the positive plate by a force equal to Vd ◊ q F = _____ d The force produces an acceleration of ‘a’ m/s2 and is equal to the force divided by mass m of an electron. This mass may be supposed to be the mass at rest because the deflecting voltage is hardly even greater than 2000 V.

Vd ◊ q a = _____ dm The forward motion however continues at velocity vox. The time taken by an electron to traverse the field of the plates is then l/vox s. The upward velocity attained by an electron in this time interval l/vox is vy. Then, Vd ◊ q l l _____ ___ vy = ___ vox ◊ a = vox ◊ dm Then the ratio of upward velocity to forward velocity at the instant the electron leaves the field is vy Vd ◊ q ◊ l ___ _______ vox = dm v2 ox

The electron follows a curved path from A, the point of entrance, to point B, the point leaving the field. Let the vertical displacement during this be D1. Then D1 is given by 2

( )

l 1 D1 = __ a ___ vox 2

2 1 Vd ◊ q ◊ l = __ ◊ ________ 2 2 dm vox

If q is the angle with the axis that the electron beam makes after emerging out from the field of the deflection plates, then vy D2 ___ tan q = ___ vox = x (or) vy Vd q 1 ___ __ ___ D2 = L ◊ ___ vox = d ◊ m ◊ v2 ◊ x ox Vd ◊ ql [l/2 + x] _______ Vd ◊ qlL Total deflection D = D1 + D2 = _____________ = 2 2 dm vox dm vox The total deflection of the spot will be same as like electron travelling straight line path at angle q from Vd ql L 1 point C instead of B. Since L = __ + x, D = _______ . 2 dm v2ox But,

2qVa v2ox = _____ m

where Va is the final anode voltage. Vd lL D = ___ × ___ Va 2d For a given CRT, the quantities l, L and d are fixed. Hence the deflection, ‘D’ of the spot can be Vd changed only by changing the ratio ___. The electrostatic deflection sensitivity of a CRT is defined as Va the deflection in metres on the screen per volt of deflecting voltage. Deflection sensitivity,

lL D S = ___ = _____, cm/V Vd 2dVa

(3.37)

where

l = length of the deflecting plates, m L = distance from the centre of the plate to the screen, m Va = accelerating potential, V d = separation between the two plates, m

The deflection sensitivity is (i) directly proportional to the length of the deflection plates l, (ii) directly proportional to the distance L between the screen and the centre of the deflection plates, (iii) inversely proportional to the spacing d between the deflection plates and inversely proportional to the final anode voltage Va.

An electrostatic cathode ray tube has a final anode voltage of 600 V. The deflection plates are 3.5 cm long and 0.8 cm apart. The screen is at a distance of 20 cm from the centre of plates. A voltage of 20 V is applied to the deflection plates. Calculate (i) velocity of electron on reaching the field, (ii) acceleration due to deflection field, (iii) deflection produced on the screen in cm, and (iv) deflection sensitivity in cm/V.

Solution

Given

Va = 600 V, l = 3.5 cm, d = 0.8 cm, L = 20 cm, Vd = 20 V _____

÷

2qVa 6 –1 (i) The velocity of the elctron, v = _____ m = 14.5 × 10 ms (ii) ma = qE Thus, acceleration, a = qE/m = (q/m)(Vd /d) = 43.95 × 1013 ms–2 (iii) The deflection on the screen, D = ILVd /2Vad = 1.45 cm (iv) Deflection sensitivity = D/Vd = 0.0725 cm/V.

In a CRT, the deflection plates are 2 cm long and are spaced 0.5 cm apart. The screen is 20 cm away from the centre of the deflecting plates. The final anode voltage is 800 V. Calculate (i) the velocity of the beam on emerging from the field and (ii) the voltage that must be applied to the deflecting plates to have a displacement of 1 cm.

Solution

Given

Va = 800 V, l = 2 cm, d = 0.5 cm, L = 20 cm, D = 1 cm _____

÷

_____________________

÷

2qVa 2 × 1.602 × 10 –19 × 800 _____________________ (i) The velocity of the beam, v = _____ m = 9.1 × 10 –31 = 16.8 × 106 m/s lLVd (ii) The deflection of the beam, D = _____ 2dVa i.e.,

2 × 10–2 × 20 × 10–2 × Vd 1 × 10–2 = ______________________ 2 × 0.5 × 10–2 × 800

Therefore, the voltage that must be applied to the plates, Vd = 20 V

In an electrostatic deflecting CRT, the length of the deflection plate is 2 cm and spacing between deflecting plates is 0.5 cm. The distance from the centre of the deflecting plate to the screen is 20 cm and the deflecting voltage is 25 V. Find the deflection sensitivity, the angle of deflection and velocity of the beam. Assume final anode potential is 1000 V.

Solution

Given, in an electrostatic deflecting CRT,

Length of deflection plate, l = 2 cm Spacing between deflecting plates, d = 0.5 cm Distance from center of deflecting plate to screen, L = 20 cm Deflecting potential, Vd = 25 V Anode potential, Va = 1000 V

_____

÷

______________________

÷

2qVa 2 × 1.602 × 10–19 × 1000 _____________________ (i) Velocity of beam, v = _____ m = 9.1 × 10–31 = 18.75 × 106 ms–1 D (ii) Deflection sensitivity = ___ Vd ILVd 2 × 10–2 × 20 × 10–2 × 25 D = _____ = ______________________ = 10–2 cm 2Va d 2 × 1000 × 0.5 × 10–2

where

10–2 Therefore, the deflection sensitivity = ____ = 0.0004 cm/V 25 (iii) To find the angle of deflection, q : 10–2 10–2 D tan q = ______ = ______ = ____ 18 (L – 1) 20 – 2 Therefore,

(

)

1 q = tan–1 _____ = 0.0318° 1800

An electron with a velocity of 3 × 105 ms–1 enters an electric field of 910 V/m making an angle of 60° with the positive direction. The direction of the electric field is in the positive y direction. Calculate the time required to reach its maximum height.

Solution

Given

v0 = 3 × 105 m/s

y E

E = 910 V/m

v0

q = 60° q

The electron starts moving in the +y direction, but, since acceleration is along the –y direction, its velocity is reduced to zero at time t = t¢. 5

x

6

v0y = v0 cos q = 3 × 10 × cos 60° = 0.15 × 10 m/s

z

qE ____________ 1.602 × 10–19 14 2 ay = ___ m = 9.109 × 10–31 × 910 = 1.5984 × 10 m/s v0y 0.15 × 106 ____________ –10 t ¢ = ___ = ay 1.5984 × 1014 = 9.384 × 10 s = 0.938 ns

The applied magnetic field is perpendicular to the direction of the electron beam. The force exerted on the electron beam by the magnetic field bends the electron beam in a direction perpendicular to both the field and the direction of electron movement. Figure 3.9 shows the magnetic deflection system in a CRT. In the region of the uniform magnetic field, the electron experiences a force qBv, where v is the speed. The path OM is the arc of a circle whose center is at Q. The velocity of the charged particles before entering into the field remains constant, which is given by _____

÷

2qVa v = vcx = _____ m Y

(3.38) Magnetic field out of paper

Q

P¢

R j

Anode

M

Cathode, K O

D j P

O¢

X

Va L l

Fluorescent screen

The small angle of deflection j is equal to the length of the arc OM divided by R, the radius of the circle. Then, 1 j ª __ (3.39) R The magnetic field continues to deflect the electron beam at right angles to its movement and hence the path taken by the electron beam within the magnetic field is a part of a circle whose radius, R, is given by mv R = ___ qB where B is the magnetic flux density, Wb/m2 v is velocity of the electron beam, m/s m is the mass of an electron, kg, and q is the charge of an electron, C

(3.40)

Usually L is far greater than l, so that small error will be made in assuming that the straight line MP¢, if projected backward, will pass through the center O¢ of the region of the magnetic field. Then D ª L tan j ª Lj

(3.41)

Using Eqs (3.38) to (3.40), the above equation becomes ____

q lL lLqB ____ lLB ___ ____ D ª Lj = ___ = _____ mv = V 2m R ÷ a

÷

The magnetic deflection sensitivity of a CRT is defined as the ratio of the deflection to the unit magnetic field intensity. The magnetic deflection sensitivity is given by ___

q lL D ____ __ = ___ ___ mm/Wb/m2 B ÷Va 2m

÷

(3.42)

The magnetostatic deflection sensitivity is also defined as the amount of deflection of the spot caused by a current of 1 mA through the deflection of coil. Thus, magnetostatic deflection sensitivity can also be expressed in cm/mA. The magnetostatic deflection sensitivity is independent of B. The electrostatic deflection sensitivity varies inversely with the anode voltage, whereas the magnetic deflection sensitivity varies inversely with the square root of the anode voltage. The sensitivity increases with L and hence, for maximum sensitivity, the deflecting coils are placed as far down the neck of the cathode ray tube as possible.

In a CRT, the distance of the screen from the centre of the magnetic field is 20 cm. The deflecting magnetic field of flux density 1 × 10– 4 Wb/m2 extends for a length of 2 cm along the tube axis. The final anode voltage is 800 V. Calculate the deflection of the spot.

Solution

The deflection of the spot, _____________

____

q lBL 2 × 10–2 × 1 ×____ 10–4 × 20 × 10–2 ___ ____ = ___________________________ D = ____ 2m ÷800 ÷

÷

÷

1.602 × 10–19 _____________ = 0.42 cm. 2 × 9.1 × 10–31

The electron beam in a CRT is displaced vertically by a magnetic field of flux density 2 × 10–4 Wb/m2. The length of the magnetic field along the tube axis is the same as that of the electrostatic deflection plates. The final anode voltage is 800 V. Calculate the voltage which should be applied to the Y-deflection plates 1 cm apart, to return the spot back to the centre of the screen. ___

Solution

q lBL ___ ___ The magnetostatic deflection, D = ____ ÷Va 2m

The electrostatic deflection,

÷

lLVd D = _____ 2 dVa

For returning the beam back to the centre, the electrostatic deflection and the magnetostatic deflection must be equal, i.e.,

___

lLVd ____ lBL q _____ = ___ ___ 2dVa ÷Va 2m

÷

______

Therefore,

_____________________

÷

÷

2Va q 2 × 800 × 1.602 × 10–19 ____________________ –2 –4 Vd = dB _____ m = 1 × 10 × 2 × 10 × 9.1 × 10–31 = 33.56 V.

Consider a cathode-ray tube placed in a constant longitudinal magnetic field such that the axis of the tube coincides with the direction of the magnetic field. A magnetic field is obtained through the use of a long solenoid placed within the coil. Figure Y 3.10 shows the helical path of an electron in magnetic field in which the axis of the cathode-ray tube is O¢ along Y axis, origin ‘O’ is the point at which the electrons emerge from the anode, vo is the velocity at the origin, vox is the initial transverse velocity due to the mutual repulsion of the electrons. The resultant B path is a helix whose axis is parallel to the Y axis and vo displaced by a distance ‘r’ along the Z axis, as shown in Fig. 3.10. The pitch of the helix, defined as the distance traveled along the direction of the magnetic field in one revolution, is given by 2pm p = ____ voy qB

Electron path

uox

uoy O

X f = quox B

muox When the applied magnetic field is zero, the electron g= qB beam is defocused and a smudge is seen on the screen. Z This results in the formation of a broad, faintly illuminated area instead of a bright point on the screen. As the magnetic field is increased from zero, the electrons take helical paths of different radius since the velocity vox that controls the radius of the path will be different for different electrons. But the time to trace the electron path is independent of vox, and so the period will be the same for all electrons. If the distance from the anode to the screen is made equal to one pitch, all the electrons will be brought back to the Y axis (the point O¢ in Fig. 3.10), since they all will have made just one revolution. Under these conditions, an image of the anode hole will be observed on the screen.

As the field is increased from zero, the smudge on the screen will contract and will become a tiny sharp spot when a critical value of the field is reached. This critical field is that which makes the pitch of the helical path just equal to the anode-screen distance. The pitch of the helix decreases by increasing the strength of the field beyond this critical value and the electrons travel through more than one complete revolution. The electrons then strike the screen at various points, so that a defocused spot is again visible. A magnetic field strength will ultimately be reached at which the electrons make two complete revolutions in their path from the anode to the screen, and once again the spot will be focused on the screen.

If the screen is perpendicular to the Y axis at a distance ‘L’ from the point of emergence of the electron beam from the anode, then, the electron beam will come to a focus at the center of the screen provided that L is an integral multiple of p. ______

÷

2q Va By substituting voy = _____ m and L = np in the previous equation and simplifying, we get 8p 2V a n2 q ________ __ = m L2 B2 where n is an integer representing the order of the focus, B is the magnetic field and Va is the anode cathode potential. This arrangement is used to measure the ratio q/m for electrons very accurately. But, this method of employing a longitudinal magnetic field over the entire length of a commercial tube is not too practical. For accurate focusing of the electron beam, a short coil is wound around the neck of the tube in a commercial tube. A radial component of B exists in addition to the component along the tube axis due to the fringing of the magnetic lines of flux. Hence there are two components of force on the electron, one due to the axial component of velocity and the radial component of the field, and the other due to the radial component of the velocity and the axial component of the field. It can be understood that the motion will be rotation about the axis of the tube and the electron on leaving the region of the coil may be turned sufficiently so as to move in a line toward the center of the screen. A rough adjustment of the focus is obtained by positioning the coil properly along the neck of the tube. The fine adjustment of focus is done by controlling coil current and the electron can be focused accurately towards the centre of the screen by this method.

The electrostatic and magnetostatic deflection systems possess different properties and each has its own merits and demerits. Magnetic deflection uses coils resulting in losses and also require large currents for deflections. On the other hand, the electrostatic deflection uses plates and require very little power. Generally, the magnetic flux density is directly proportional to the current flowing, and deflection produced is a direct function of the current in the coils. The current in a coil is a function of time integral of the applied voltage and because of this reason, the magnetic deflection cannot be used for direct visual display of the applied voltage. The electrostatic deflection can be used at much higher frequencies and, therefore, preferred for high frequency instruments. The electrostatic deflection sensitivity decreases more rapidly with increased anode voltage than in the case of the magnetic deflection. Therefore, the accelerating potential can be increased to give brighter spot with small decrease in sensitivity for magnetic deflection than for electric deflection. In electrostatic deflection, the degree of deflection is proportional to square of electron velocity. In contrast, in tubes using magnetostatic deflection system, the deflection is inversely proportional to electron velocity. Hence, the electrostatic deflection suffers deflection defocusing when the beam is bent through a large angle. For these reasons, the magnetic deflection is preferred in cathode ray tube used in television because large permissible angle of deflection reduces the length of the tube for a given diameter.

When an electron beam is deflected from the axial direction, the spot on the fluorescent screen tends to distort and enlarge. This phenomenon is commonly referred to as deflection defocusing. This may be due to (i) non-uniform distance between the electron gun and the different parts of the screen, (ii) non-uniform electric and magnetic deflection fields, and (iii) unequal velocities of electrons in the beam. With non-uniform deflecting fields, the part of the beam which passes through region of weaker field is less deflected than the part of the beam which passes through region of stronger field. If the electrons are emitted from cathode with unequal initial velocities, as the degree of deflection is also a function of the electron velocity, electrons with different velocities are deflected differently which forms a blurred elliptical spot on the screen.

The PN junction diode is one of the semiconductor devices with two semiconductor materials in physical contact, one with excess of holes (P-type) and other with excess of electrons (N-type). A PN junction diode may be formed from a single-crystal intrinsic semiconductor by doping part of it with acceptor impurities and the remaining with donors. Such junctions can form the basis of very efficient rectifiers. The most important characteristic of a PN junction is its ability to allow the flow of current in only one direction. In the opposite direction, it offers very high resistance. The highvacuum diode has largely been replaced by silicon and selenium rectifiers. Semiconductor diodes find wide applications in all phases of electronics, viz. radio and TV, optoelectronics, power supplies, industrial electronics, instrumentation, computers, etc.

Semiconductors are classified as (i) intrinsic (pure) and (ii) extrinsic (impure) types. The extrinsic semiconductors are of N-type and P-type. A pure semiconductor is called intrinsic semiconductor. As already explained in the first chapter, even at room temperature, some of the valence electrons may acquire sufficient energy to enter the conduction band to form free electrons. Under the influence of electric field, these electrons constitute electric current. A missing electron in the valence band leaves a vacant space there, which is known as a hole, as shown in Fig. 4.1. Holes also contribute to electric current.

Free electron Energy in eV

CB (Conduction Band)

Hole

VB (Valence Band)

In an intrinsic semiconductor, even at room temperature, electron-hole pairs are created. When electric field is applied across an intrinsic semiconductor, the current conduction takes place due to free electrons and holes. Under the influence of electric field, total current through the semiconductor is the sum of currents due to free electrons and holes.

Holes X

Y –

–

–

Free electrons

Though the total current inside the semiconductor is due to free electrons and holes, the current in the external wire – + is fully by electrons. In Fig. 4.2, holes being positively charged move towards the negative terminal of the battery. As the holes reach the negative terminal of the battery, electrons enter the semiconductor near the terminal (X ) and combine with the holes. At the same time, the loosely held electrons near the positive terminal (Y ) are attracted towards the positive terminal. This creates new holes near the positive terminal which again drift towards the negative terminal. Due to the poor conduction at room temperature, the intrinsic semiconductor as such, is not useful in the electronic devices. Hence, the current conduction capability of the intrinsic semiconductor should be increased. This can be achieved by adding a small amount of impurity to the intrinsic semiconductor, so that it becomes impure or extrinsic semiconductor. This process of adding impurity is known as doping. The amount of impurity added is extremely small, say 1 to 2 atoms of impurity for 106 intrinsic atoms. A small amount of pentavalent impurities such as arsenic, antimony or phosphorus is added to the pure semiconductor (germanium or silicon crystal) to get N-type semiconductor. Germanium atom has four valence electrons and antimony has five valence electrons. As shown in Fig. 4.3, each antimony atom forms a covalent bond with surrounding four germanium atoms. Thus, four valence electrons of antimony atom form covalent bond with four valence electrons of individual germanium atom and fifth valence electron is left free which is loosely bound to the antimony atom. This loosely bound electron can be easily excited from the valence band to the conduction band by the application of electric field or increasing the thermal energy. Thus every antimony atom contributes one conduction electron without creating a hole. Such pentavalent impurities are called donor impurities because it donates one electron for conduction. On giving an electron for conduction, the donor atom becomes positively charged ion because it loses one electron. But it cannot take part in conduction because it is firmly fixed in the crystal lattice. Thus, the addition of pentavalent impurity (antimony) increases the number of electrons in the conduction band thereby increasing the conductivity of N-type semiconductor. As a result of doping, the number of free electrons far exceeds the number of holes in an N-type semiconductor. So electrons are called majority carriers and holes are called minority carriers.

A small amount of trivalent impurity such as aluminium or boron is added to the pure semiconductor to get the p-type semiconductor. Germanium (Ge) atom has four valence electrons and boron has three valence electrons as shown in Fig. 4.4. Three valence electrons in boron form covalent bond with four surrounding atoms of Ge leaving one bond incomplete which gives rise to a hole. Thus trivalent impurity (boron) when added to the intrinsic semiconductor (germanium) introduces a large number of holes in the valence band. These positively charged holes increase the conductivity of P-type semiconductor. Trivalent impurities such as boron is called acceptor impurity because it accepts free electrons in the place of holes. As each boron atom donates a hole for conduction, it becomes a negatively charged ion. As the number of holes is very much greater than the number of free electrons in a P-type material, holes are termed as majority carriers and electrons as minority carriers.

P

In a pure semiconductor, the number of holes is equal to the number of electrons. Thermal agitation continues to produce new electron-hole pairs and the electron-hole pair disappears because of recombination. With each electron-hole pair created, two charge-carrying particles are formed. One is negative which is the free electron with mobility m n. The other is positive, i.e. the hole with mobility mp. The electrons and holes move in opposite directions in an electric field E, but since they are of opposite sign, the current due to each is in the same direction. Hence the total current density J within the intrinsic semiconductor is given by J = Jn + Jp = q ◊ n ◊ mn E + q ◊ p ◊ mp ◊ E = (nm n + pmp)qE = sE where

(4.1)

Jn = electron drift current density Jp = hole drift current density n = number of electrons per unit volume, i.e. magnitude of free-electron (negative) concentration p = number of holes per unit volume, i.e. magnitude of hole (positive) concentration E = applied electric field strength, V/m q = charge of electron or hole, Coulomb

Hence, s is the conductivity of a semiconductor which is equal to (n m n + p mp)q. The resistivity (r) of 1 a semiconductor is the reciprocal of conductivity, i.e. r = __ s. It is evident from the above equation that current density within a semiconductor is directly proportional to the applied electric field. For pure (intrinsic) semiconductor, n = p = ni, where ni is the intrinsic carrier concentration. Therefore,

J = ni (m n + mp) qE

and conductivity of an intrinsic semiconductor is si = q ◊ ni (m n + mp). Hence it is clear that conductivity of an intrinsic semiconductor depends upon its intrinsic concentration (ni) and the mobility of electrons (m n) and holes (mp). The intrinsic conductivity of germanium and silicon increase by approximately 5 per cent per °C and 7 per cent per °C rise in temperature respectively due to the influence of ni. The conductivity of an intrinsic semiconductor, si = q ◊ ni(mn + mp) = q ◊ (n mn + pmp) For N-type semiconductor, as n>>p, then the conductivity, s = q ◊ n ◊ mn. For P-type semiconductor, as p>>n, the conductivity, s = q ◊ p ◊ mp.

(4.2)

The mobility of free electrons and holes in pure germanium are 3800 and 1800 cm2 /V-s respectively. The corresponding values for pure silicon are 1300 and 500 cm2/V-s, respectively. Determine the values of intrinsic conductivity for both germanium and silicon. Assume ni = 2.5 × 1013 cm–3 for germanium and ni = 1.5 × 1010 cm–3 for silicon at room temperature.

Solution

(i) The intrinsic conductivity for germanium, i

= qni (

n

+

p) –19

= (1.602 × 10

) (2.5 × 1013) (3800 + 1800)

= 0.0224 S/cm (ii) The intrinsic conductivity for silicon, i

= qni (

n

+

p) –19

= (1.602 × 10

) (1.5 × 1010) (1300 + 500)

= 4.32 × 10 –6 S/cm

An electron inside the metal must possess an energy level that is at least greater than the surface barrier energy EB, so as to escape to a higher level. It is therefore important to know about the energies possessed by the electrons in a metal. This is given by the energy distribution function. The distribution in energy of the free electrons in a metal is given by dn = dE where dn is the number of electrons per cubic meter whose energies lie in the energy interval dE and is the density of electrons in a given energy interval. It is assumed that there are no potential variations within the metal, since only free electrons are considered. Hence there must be the same number of electrons in each cubic metre of the metal. That is, the density in space (electrons per cubic metre) is a constant. However, there will be electrons having all possible energies within each unit volume of the metal. This distribution in energy is expressed by = f (E) N(E) where N(E) is the density of states in the conductance band, and f (E) is the probability that a quantum state with energy ‘E’ is occupied by an electron. Therefore, 1 __

N(E) = E 2 Here, is a constant defined by

3 3 __ __ 4 = ___3 (2m) 2 (1.602 × 10 – 19) 2 = 6.82 × 1027 h

3 – __ 2

where the dimensions of g are (m – 3) (eV) constant in Joule-second.

, m is the mass of the electron in kg and h is the Planck’s

The Fermi-Dirac probability function f (E) specifies the fraction of all states at energy E (in eV) occupied under conditions of thermal equilibrium. From quantum physics, 1 f (E) = ___________ 1 + e(E – EF)/kT where k is the Boltzman constant in eV/K, T is the temperature in K and EF is the Fermi level or characteristic energy for the crystal in eV. The Fermi level represents the energy state with 50% probability of being filled if no forbidden band 1 exists. That is, if E = EF , then f (E) = __ for any value of temperature. 2 The plots of f (E) Vs (E – EF) and (E – EF) Vs f (E) are shown in Fig. 4.5(a) and Fig. 4.5(b) respectively for T = 0°K and larger values of temperature. E – EF, eV T=0K

f (E ) 1.0

T = 300 K

0.8

T = 2500 K

0.6 0.4 0.2 0 – 1.0 – 0.6 – 0.2 0 0.2

0.6

1.0 E – EF, eV

1.0 0.8 0.6 0.4 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 – 1.0

T = 2500 K T = 300 K T=0K

0

0.2 0.4 0.6 0.8 1.0 f (E )

(a)

(b)

At T = 0K, the following conditions exist: (i) If E > EF, the exponential term becomes infinite and f (E) = 0. Consequently, there is no probability of finding an occupied quantum state of energy greater than EF at absolute zero temperature. (ii) If E < EF, the exponential becomes zero and f (E) = 1. All quantum levels with energies less than EF will be occupied at T = 0K. From the above equations, we get at absolute zero temperature, 1 __

g E 2 ; for E < EF r = 0 ; for E > EF It implies that there are no electrons at 0K which have energies in excess of EF. Therefore, the Fermi energy is the maximum energy that any electron may possess at absolute zero temperature.

The relationship given by the above equation is called the completely degenerate energy distribution function. In fact, all particles should have zero energy at 0K. Based on Pauli's exclusion principle, it is also to be mentioned that, since no two electrons has the same set of quantum numbers, not all the electrons can have the same energy even at 0K. An expression for EF may be obtained on the basis of the completely degenerate function. The total number of free electrons is given by E

F 3 1 __ __ 2 n = Ú g E 2 dE = __ g EF 2 3 0 2 3n __3 ___ EF = , where g = 6.82 × 1027 2g

( )

i.e.

2 __

EF = 3.64 × 10–19 n 3

Therefore,

Since the density of free electrons, n, varies from metal to metal, EF will also vary among metals. Generally, the numerical value of EF is less than 10 eV.

To calculate the conductivity of a semiconductor, the concentration of free electrons n and the concentration of free holes p must be known. dn = N(E) f(E) dE where dn represents the number of conduction electrons per cubic meter whose energies lie between E and E + dE and N(E) is the density of states. In a semiconductor, the lowest energy in the conduction band is EC and hence, N(E) = g (E – EC )1/2 The Fermi Dirac probability function f (E) is given by 1 f (E ) = ____________ 1 + e(E – EF)/kT where EF is the Fermi level or characteristic energy for the crystal in eV. The concentration of electrons in the conduction band is, •

n = Ú N(E) f (E) dE EC

For E

EC , E – EF

kT, f (E ) =

–(E – EF)/kT •

and

1 __

n = Ú g (E – EC) 2 e–(E – EF)/kT dE EC

Substitute At

(E – Ec) = x2 i.e. E = x2 + Ec and dE = 2xdx x = 0, E = Ec,

At

x = •, E = •

Therefore,

n = Ú 0 g xe

(

•

x2 + Ec – EF – ___________ kT

(

x ) Ú• x2e – ___ kT dx

Ec – EF – _______ kT

= 2g e We know that,

• __ 2n! a 2 2 Ú 0 x2n e – x /a dx = ÷p ___ __ n! 2

) [2xdx] 2

0

2n+ 1

( )

___

Here, n = 1 and a = ÷kT Therefore,

n =

(

Ec – EF – _______ 2g e kT

___

÷kT 3 ) × 2 ÷__p ( ____ )

2

3 __ )2

3 __ 4p g = ___3 (2mn (1.602 × 10 – 19) 2 , we have h 3 __ __ 3 3 __ __ ÷p (kT) 2 4p – ___ ________ – 19 n = 2 × 3 (2mn) 2 (1.602 × 10 ) 2 × ×e 4 h

Substituting

E –E ( _______ kT )

(

2mnpkT = 2 _______ h2

3 __ 2

)

3 __

× (1.602 ×10 – 19) 2 e

(

Ec – EF – _______ kT

c

F

E –E ) = Nc e – ( _______ kT ) c

F

3 2pmnkT __3 __ 2 (1.602 × 10 – 19) 2 , where m is the effective mass of an electron. where Nc = 2 _______ n 2 h When the maximum energy in the valence band is EV, the density of states is given by

(

)

N(E) = g (EV – E )1/2 The Fermi function of a hole is [1 – f (E )] and is given by e(E – EF)/kT 1 – f (E) = ____________ = e–(EF – E)/kT 1 + e(E – EF)/kT where EF – E >> kT for E £ EV. The concentration of holes in the valence band is, EV

p = Ú g (EV – E)1/2 e–(EF – E)/kT dE –•

This integral evaluates to p = NV e– (EF – EV)/kT where

(

2pmp kT NV = 2 ________ h2 a hole.

)

3/2

(1.602 × 10–19)3/2, where mp is the effective mass of

In the case of intrinsic material, the crystal must be electrically neutral. n i = pi Therefore,

NC e–(EC – EF)/kT = NV e–(EF – EV)/kT

Taking the logarithm on both sides, EC + EV – 2EF NC ln ____ = _____________ NV kT EC + EV kT NC EF = ________ – ___ ln ___ NV 2 2 If the effective masses of a free electron and hole are the same, NC = NV EC + EV EF = ________ 2 From the above equation, at the centre of the forbidden energy band, Fermi level is present. Then,

If a pentavalent substance (antimony, phosphorous or arsenic) is added as an impurity to pure germanium, four of the five valance electrons of the impurity atoms will occupy covalent bonds and the fifth electron will be available as a carrier of current. These impurities donate excess electron carriers and are hence called donor or N-type impurities. If a trivalent impurity (boron, gallium or indium) is added to an intrinsic semiconductor, only three covalent bonds are filled, and the vacancy in the fourth bond constitutes a hole. These impurities are known as acceptor or P-type impurities. The Fermi level in an N-type material is given by

NC EF = EC – kT ln ___

where ND = NC e – (EC – EF)/kT, the concentration of donor atoms. The Fermi level in a P-type material is given by NV EF = EV + kT ln ___ NA where NA = NV e–(EF – EV)/kT, the concentration of acceptor atoms. The change in the position of Fermi level in N- and P-type semiconductors is shown in Fig. 4.6. In an N-type semiconductor, as temperature T increases, more number of electron-hole pairs are formed. At very high temperature T, the concentration of thermally generated electrons in the conduction band will be far greater than the concentration of donor electrons. In such a case, as concentration of electrons and holes become equal, the semiconductor becomes essentially intrinsic and EF returns to the middle of the forbidden energy gap. Hence, it is concluded that as the temperature of the P-type and N-type semiconductor increases, EF progressively moves towards the middle of the forbidden energy gap.

Conduction band

EC

Conduction band

EC

Energy

ED EF

EG

EF EV

EA

EV Valence band

0

0.5 f (E ) (a)

Valence band 1.0

0

0.5 f (E ) (b)

1.0

In an N-type semiconductor, the Fermi level is 0.3 eV below the conduction level at a room temperature of 300 K. If the temperature is increased to 360 K, determine the new position of the Fermi level.

The Fermi level in an N-type material is given by NC EF = EC – kT ln ___ ND NC Therefore, (EC – EF ) = kT ln ___ ND NC At T = 300 K, 0.3 = 300 k ln ___ ND NC Similarly, E C – EF1 = 360 k ln ___ ND Solution

(1) (2)

Eqn. (2) divided by Eqn. (1) gives EC – EF1 ____ 360 ________ = 0.3 300 360 ____ Therefore, EC – EF1 = × 0.3 = 0.36 eV 300 Hence, the new position of the Fermi level lies 0.36 eV below the conduction level.

In a P-type semiconductor, the Fermi level is 0.3 eV above the valance band at a room temperature of 300 K. Determine the new position of the Fermi level for temperatures of (a) 350 K and (b) 400 K.

Solution

The Fermi level in a P-type material is given by NV EF = EV + kT ln ___ NA

NV (EF – EV) = kT ln ___ NA N V At T = 300 K, 0.3 = 300 k ln ___ NA NV (a) At T = 350 K, (EF1 – EV) = 350k ln ___ NA Hence, from the above equation Therefore,

EF1 – EV ____ 350 ________ = 0.3 300 350 ____ Therefore, EF1 – EV = × 0.3 = 0.35 eV 300 NV (b) At T = 400 K, (E F2 – EV) = 400 k ln ___ NA Hence, from the above equation,

Therefore,

EF2 – EV ____ 400 ________ = 0.3 300 400 EF2 – EV = ____ × 0.3 = 0.4 eV 300

In an N-type semiconductor, the Fermi level lies 0.2 eV below the conduction band. Find the new position of Fermi level if the concentration of donor atoms is increased by a factor to (a) 4 and (b) 8. Assume kT = 0.025 eV.

Solution

In an N-type material, the concentration of donor atoms is given by ND = NC e–(EC – EF)/kT

Let initially ND = NDO, EF = EFO and EC – EFO = 0.2 eV Therefore, NDO = NC e –0.2/0.025 = NC e –8 (a) When ND = 4NDO and E F = EF1, then 4NDO = NC e– (EC – EF )/0.025 = NC e–40 (EC – EF ) 1

Therefore,

–8

4 × NC e

–40(EC – EF1)

= NC e

Therefore, 4 = e–40 (EC – EF1) + 8 Taking natural logarithm on both sides, we get ln 4 = – 40 (EC – EF1) + 8 1.386 = – 40(EC – EF1) + 8 Therefore,

EC – EF1 = 0.165 eV

(b) When ND = 8NDO and EF = EF2, then ln 8 = – 40 (EC – EF2) + 8 Therefore,

2.08 = – 40 (EC – EF2) + 8 EC – EF2 = 0.148 eV

1

In a P-type semiconductor, the Fermi level lies 0.4 eV above the valence band. Determine the new position of Fermi level if the concentration of acceptor atoms is multiplied by a factor of (a) 0.5 and (b) 4. Assume kT = 0.025 eV.

Solution

In a P-type material, the concentration of acceptor atoms is given by NA = NV e–(EF – EV)/kT

Let initially NA = NAO, EF = EFO and EFO – EV = 0.4 eV Therefore,

NAO = NV e – 0.4/0.025 = NV e –16

(a) When NA = 0.5, NAO and EF = EF1, then 0.5NAO = NV e–(EF1 – EV)/0.025 = NV e–40 (EF1 – EV) Therefore, Therefore,

0.5 × NV e–16 = NV e–40(EF1 – EV) 0.5 = e–40 (EF1 + EV) + 16

Taking natural logarithm on both sides, we get ln (0.5) = – 40(EF1 – EV) + 16 Therefore,

EF1 – EV = 0.417 eV

(b) When NA = 4NAO and EF = EF2, then ln 4 = – 40(EF2 – EV) + 16 Therefore,

EF2 – EV = 0.365 eV

If a pure semiconductor is doped with N-type impurities, the number of electrons in the conduction band increases above a level and the number of holes in the valence band decreases below a level, which would be available in the intrinsic (pure) semiconductor. Similarly, the addition of P-type impurities to a pure semiconductor increases the number of holes in the valence band above a level and decreases the number of electrons in the conduction band below a level, which would have been available in the intrinsic semiconductor. This is because the rate of recombination increases due to the presence of a large number of free electrons (or holes). Further, the experimental results state that under thermal equilibrium for any semiconductor, the product of the number of holes and the number of electrons is constant and is independent of the amount of donor and acceptor impurity doping. This relation is known as mass-action law and is given by n.p = ni2

(4.3)

where n is the number of free electrons per unit volume, p the number of holes per unit volume and ni the intrinsic concentration. While considering the conductivity of the doped semiconductors, only the dominant majority charge carriers have to be considered.

The law of mass-action has given the relationship between free electron concentration and hole concentration. These concentrations are further related by the law of Electrical Neutrality as explained below. Let ND be the concentration of donor atoms in an N-type semiconductor. In order to maintain the electric neutrality of the crystal, we have nN = ND + pN ª ND where nN and pN are the electron and hole concentration in the N-type semiconductor. The value of pN is obtained from the relations of mass-action law as n2i pN = ___ nN n2i ___ ª , which is NA, then the semiconductor is converted from a P-type to N-type. Similarly, a large number of acceptor atoms added to an N-type semiconductor can convert it to a P-type semiconductor if NA >> ND. This concept is precisely used in the fabrication of PN junction, which is an essential part of semiconductor devices and integrated circuits.

Find the conductivity of silicon (a) in intrinsic condition at a room temperature of 300 K, (b) with donor impurity of 1 in 108, (c) with acceptor impurity of 1 in 5 × 107 and (d) with both the above impurities present simultaneously. Given that ni for silicon at 300 K is 1.5 × 1010 cm–3, mn = 1300 cm2/V-s, mp = 500 cm2/V-s, number of Si atoms per cm3 = 5 × 1022.

Solution

(a) In intrinsic condition, n = p = ni

Hence,

si = qni (mn + mp) = (1.602 × 10–19) (1.5 × 1010) (1300 + 500) = 4.32 × 10–6 S/cm

(b) Number of silicon atoms/cm3 = 5 × 1022 Hence,

5 × 1022 ND = _______ = 5 × 1014 cm–3 108

Further,

n ª ND

Therefore,

n2i n2i ___ p = __ ª n ND (1.5 × 1010)2 = ___________ = 0.46 × 106 cm–3 5 × 1014

Thus, p > n. Hence n may be neglected while calculating the conductivity. Hence,

s = pqmP = NAqmP = (1015 × 1.602 × 10–19 × 500) = 0.08 S/cm.

(d) With both types of impurities present simultaneously, the net acceptor impurity density is, N¢A = NA – ND = 1015 – 5 × 1014 = 5 × 1014 cm–3 Hence,

s = N¢A qmp = (5 × 1014) (1.602 × 10–19) (500) = 0.04 S/cm.

Determine the resistivity of germanium (a) in instrinsic condition at 300 K (b) with donor impurity of 1 in 107 (c) with acceptor impurity of 1 in 108 (d) with both the above impurities simultaneously. Given that for germanium at room temperature ni = 2.5 × 1013/cm3, mn = 3800 cm2/V-Vs, mp = 1800 cm2/V-Vs and a number of Germanium atoms/cm3 = 4.4 × 1022.

Solution

(a) n = p = ni = 2.5 × 1013 cm–3

Therefore, conductivity,

s = qni(mn + mp) = (1.602 × 10–19)(2.5 × 1013)(3800 + 1800)

Hence, resistivity, (b) Also, Therefore,

= 0.0224 S/cm 1 ______ 1 r = __ s = 0.0224 = 44.64 W-cm 4.4 × 1022 ND = _________ = 4.4 × 1015 cm–3 107 n = ND n2i n2i ___ p = __ = n ND

(2.5 × 1013)2 = ___________ = 1.42 × 1011 holes/cm3 4.4 × 1015 Here, as n >> p, p can be neglected. Therefore, conductivity,

Hence, resistivity, (c) Also, Therefore,

s = nqmn = NDqmn = (4.4 × 1015) (1.602 × 10–19) (3800) = 2.675 S/cm 1 _____ 1 r = __ s = 2.675 = 0.374 W-cm 4.4 × 1022 NA = _________ = 4.4 × 1014 cm–3 108 p = NA n2i n2i ___ n = ___ = p NA

(2.5 × 1013)2 = ___________ = 1.42 × 1012 electrons/cm3 4.4 × 1014 Here, as p >> n, n may be neglected. Then Conductivity,

s = pqmp = NAqmp = (4.4 × 1014) (1.602 × 10–19) (1800) = 0.1267 S/cm

1 ______ 1 r = __ s = 0.1267 = 7.89 W-cm (d) with both p and n type impurities present, Hence resistivity,

ND = 4.4 × 1015 cm–3 and NA = 4.4 × 1014 cm–3

Therefore, the net donor density N¢D is N¢D = (ND – NA) = (4.4 × 1015 – 4.4 × 1014) = 3.96 × 1015 cm–3 Therefore, effective n = N¢D = 3.96 × 1015 cm–3 n2i (2.5 × 1013)2 p = ____ = ___________ N¢D 3.96 × 1015 = 1.578 × 1011 cm–3

( )

Here again p =

n2i ____

N¢D effective conductivity. Therefore,

Hence, resistivity

is very small compared with ND ¢ and may be neglected in calculating the

s = N¢D qmn = (3.96 × 1015) (1.6 × 10 –19) (3800) = 2.408 S/cm 1 _____ 1 r = __ s = 2.408 = 0.415 W-cm

A sample of silicon at a given temperature T in intrinsic condition has a resistivity of 25 × 104 W-cm. The sample is now doped to the extent of 4 × 1010 donor atoms/cm3 and 1010 acceptor atoms/cm3. Find the total conduction current density if an electric field of 4 V/cm is applied across the sample. Given that mn = 1250 cm2/V-s, mp = 475 cm2/V-s at the given temperature.

Solution Therefore,

1 si = qni (mn + mp) = ________4 25 × 10 si 1 ni = _________ = _________________________________ q(mn + mp) (25 × 104) (1.602 × 10–19) (1250 + 475) = 1.45 × 1010 cm–3

Net donor density

ND (= n) = (4 × 1010 – 1010) = 3 × 1010 cm–3

Hence,

n2i (1.45 × 1010)2 ____ p = = ____________ = 0.7 × 1010 cm–3 10 ND 3 × 10

Hence,

s = q(nmn + pmp) = (1.602 × 10 –19) (3 × 1010 × 1250 + 0.7 × 1010 × 475) = 6.532 × 10 –6 S/cm

Therefore, total conduction current density, J = sE = 6.532 × 10 –6 × 4 = 26.128 × 10 –6 A/cm2

Find the concentration (densities) of holes and electrons in N-type Silicon at 300 K, if the conductivity is 300 S/cm. Also find these values for P-type silicon. Given that for Silicon at 300 K, ni = 1.5 × 1010/cm3, 2 2 n = 1300 cm /V-s and p = 500 cm /V-s.

Solution (a) Concentration in N-type Silicon The conductivity of an N-type silicon is = qn n Concentration of electrons, n = ____ q n 300 = ___________________ = 1.442 × 1018 cm–3 (1.602 × 10–19) (1300) Hence concentration of holes,

n2i (1.5 × 1010)2 __ p = n = ___________ = 1.56 × 102 cm–3 1.442 × 1018

(b) Concentration in P-type silicon The conductivity of a P-type silicon is = qp Hence, concentration of holes p = ____ q p

p

300 = __________________ = 3.75 × 1018 cm–3 (1.602 × 10–19) (500) n2i (1.5 × 1010)2 ___________ 2 –3 and concentration of electrons, n = __ p = 3.75 × 1018 = 0.6 × 10 cm

A specimen of pure germanium at 300 K has a density of charge carriers 2.5 × 1019/m3. It is doped with donor impurity atoms at the rate of one impurity atom every 106 atoms of germanium. All impurity atoms are supposed to be ionised. The density of germanium atom is 4.2 × 1028 atoms/m3. Calculate the resistivity of the doped germanium if electron mobility is 0.38 m2/V-s. If the Germanium bar is 5 × 10–3 m long and has a cross sectional area of (5 × 10–6)2 m2, determine its resistance and the voltage drop across the semiconductor bar for a current of 1 A flowing through it.

Solution

Also, Therefore,

Density of added impurity atoms is 4.2 × 1028 ND = _________ = 4.2 × 1022 atoms/m3 106 n ND n2i n2i __ ___ p = n = ND (2.5 × 1019)2 = ___________ = 1.488 × 106 m–3 4.2 × 1022

Here, as p 0 = 0, elsewhere where is the space charge density, as indicated in Fig. 4.9(c)(i). The axes have been chosen in Fig. 4.9(e) in such a way that V1 and X1 have negative values. The potential variation in the space charge region can be calculated by using Poission’s equation, which is given by 2

(x, y, z) V = – ________ 0 r

where is

r

is the relative permittivity. The relevant equation for the required one-dimensional problem

d2 V ____ = – ____ 0 r dx2 Applying the above equation to the P-side of the junction, we get qNA d2 V ____ ____ = 2 0 r dx Integrating twice, we get qNAx2 V = ______ + Cx + D 2 0 r

where C and D are the constants of integration. From the Fig. 4.9(e), we have V = 0 at x = 0, and hence D = 0. When x < X1 on the P-side, the potential dV is constant, so that ___ = 0 at x = X1 Hence, dx

qNA C = – _____ X1 o r

Therefore,

qNA x2 qNA V = _______ – ____ X1 x 2 o r o r

i.e.

qNA x2 V = ____ __ – X1 x o r 2

(

)

As V = V1 at x = X1, we have qNA V1 = – _____ X12 2 o r If we apply the same procedure to the N-side, we get qND V2 = _____ X22 2 o r Therefore, the total built-in potential or the contact potential is Vo, where q Vo = V2 – V1 = _____ ( NA X12 + ND X22 ) 2 o r We know the fact that the positive charge on the N-side must be equal in magnitude to the negative charge on the P-side for the neutral specimen. Hence, NAX1 = – NDX2 and substituting this relationship in the above equation and using the fact that X1 is a negative quantity, we get

[

2 o r Vo X1 = – _____________ NA qNA 1 + ___ ND

(

)

]

1/2

Similarly,

[

2 o r Vo X2 = _____________ ND qND 1 + ___ NA

(

)

]

1/2

The total depletion width, W = X2 – X1 and hence, W2 =X21 + X22 – 2X1 X2, and then substituting for X1 and X2 from the above equations, we find

[

2 o r Vo ________ NA + N D W = ________ q NA ND

(

)]

1/2

Here, in an alloy junction, the depletion width W is proportional to (Vo)1/2. In a Grown Junction, the charge density ( ) varies linearly with distance (x) as shown in Fig. 4.9(c)(ii). If a similar analysis is carried for this junction, it is found that W varies as (Vo)1/3 instead of (Vo)1/2.

When positive terminal of the battery is connected to the P-type and negative terminal to the N-type of the PN junction diode, the bias applied is known as forward bias. Holes flow As shown in Fig. 4.10, the applied P N potential with external battery acts in opposition + + + – – – + + + + – – – – to the internal potential barrier and disturbs the + + + + + + + – – – – equilibrium. As soon as equilibrium is disturbed + + + by the application of an external voltage, the Fermi + + + + – – – – level is no longer continuous across the junction. Electrons flow Under the forward bias condition, the applied W + – positive potential repels the holes in P-type region so that the holes move towards the junction and the applied negative potential repels the electrons in the N-type region and the electrons move towards the junction. Eventually, when the applied potential is more than the internal barrier potential, the depletion region and internal potential barrier disappear.

Under forward bias condition, the V–I characteristics of a PN unction diode are shown in Fig. 4.11. As the forward voltage (VF ) is increased, for VF < VO, the forward IF(mA ) current IF is almost zero (region OA) because the potential barrier Ge Si prevents the holes from P-region and electrons from N-region to B flow across the depletion region in the opposite direction. For VF > VO, the potential barrier at the junction completely disappears and hence, the holes cross the junction from P-type to N-type and the electrons cross the junction in the opposite direction, resulting in relatively large current flow in the external circuit.

A 0.3 V

0

VF(V )

0.7 V

A feature worth to be noted in the forward characteristics shown in Fig. 4.11 is the cut in or threshold voltage (Vr) below which the current is very small. It is 0.3 V and 0.7 V for germanium and silicon, respectively. At the cut in voltage, the potential barrier is overcome and the current through the junction starts to increase rapidly.

P

When the negative terminal of the battery is connected to the P-type and positive terminal of the battery is connected to the N-type of the PN junction, the bias applied is known as reverse bias. Under applied reverse bias as shown in Fig. 4.12, holes which form the majority carriers of the P-side move towards the negative terminal of the battery and electrons which form the majority carrier of the N-side are attracted towards the

–

N

+

+

–

+

+

–

+

+

–

Holes + V

–

+

+

–

–

–

+

+

–

–

–

+

+

–

–

W

Electrons

IF positive terminal of the battery. Hence, the width of the depletion region which is depleted of mobile charge carriers increases. Thus, the electric field produced by applied reverse bias, is in the same direction as the electric field of the potential barrier. Hence, the resultant VF potential barrier is increased which prevents the flow of majority VR carriers in both directions; the depletion width, W, is proportional 0 ___ to ÷Vo under reverse bias. Therefore, theoretically no current should Breakflow in the external circuit. But in practice, a very small current of down voltage the order of a few microamperes flows under reverse bias as shown in Fig. 4.13. Electrons forming covalent bonds of the semiconductor IR(mA ) atoms in the P- and N-type regions may absorb sufficient energy from heat and light to cause breaking of some covalent bonds. Hence electron–hole pairs are continually produced in both the regions. Under the reverse bias condition, the thermally generated holes in the P-region are attracted towards the negative terminal of the battery and the electrons in the N-region are attracted towards the positive terminal of the battery. Consequently, the minority carriers, electrons in the P-region and holes in the N-region, wander over to the junction and flow towards their majority carrier side giving rise to a small reverse current. This current is known as reverse saturation current, Io. The magnitude of reverse saturation current mainly depends upon junction temperature because the major source of minority carriers is thermally broken covalent bonds.

For large applied reverse bias, the free electrons from the N-type moving towards the positive terminal of the battery acquire sufficient energy to move with high velocity to dislodge valence electrons from semiconductor atoms in the crystal. These newly liberated electrons, in turn, acquire sufficient energy to dislodge other parent electrons. Thus, a large number of free electrons are formed which is commonly called as an avalanche of free electrons. This leads to the breakdown of the junction leading to very large reverse current. The reverse voltage at which the junction breakdown occurs is known as Breakdown Voltage, VBD.

Figure 4.14 shows the current-voltage characteristics of PN junction. The characteristics of the PN junction vary enormously depending upon the polarity of the applied voltage. For a forward-bias voltage, the current increases exponentially with the increase of voltage. A small change in the forwardbias voltage increases the corresponding forward-bias current by orders of magnitude and hence the forward-bias PN junction will have a very small resistance. The level of IF (mA) current flowing across a forward4 biased PN junction largely depends upon the junction area. In the reverse3 bias direction, the current remains 2 small, i.e., almost zero, irrespective of the magnitude of the applied 1 voltage and hence the reverse-bias PN junction will have a high resitance. VR(V ) VF(V ) IR = – Io – 1.0 1.0 The reverse bias current depends on the area, temperature and type of semiconductor material.

The semiconductor device that displays these I-V characteristics is called a PN junction diode. Figure 4.15 shows the PN junction diode with forward-bias and reverse-bias and their circuit symbols. The metal contacts are indicated with which the homogeneous P-type and N-type materials are provided. Thus two metal-semiconductor junctions, one at each end of the diode, are introduced. The contact potential across these junctions is approximately independent of the direction and magnitude of the current. A contact of this type is called an ohmic contact, which has low resistance. In the forward-bias, a relatively large current is produced by a fairly small applied voltage. In the reverse-bias, only a very small current, ranging from nanoamps to microamps is produced. The diode can be used as a voltage controlled switch, i.e., OFF for a reverse-bias voltage and ON for a forward-bias voltage. Metal ohmic contacts

Metal contacts

I P

I

N

+

P

–

–

+

V

V (a)

N

–

+

–

V

+

V (b)

When a diode is reverse-biased by atleast 0.1V, the diode current is IR = – Io. As the current is in the reverse direction and is a constant, it is called the diode reverse saturation current. Real diodes exhibit reverse-bias current that are considerably larger than Io. This additional current is called a generation current which is due to electrons and holes being generated within the space-charge region. A typical value of I0 may be 10 – 14 A and a typical value of reverse-bias current may be 10 – 9 A.

A PN junction diode is a two terminal device that is polarity sensitive. When the diode is forward biased, the diode conducts and allows current to flow through it without any resistance, i.e. the diode is ON. When the diode is reverse biased, the diode does not conduct and no current flows through it, i.e. the diode is OFF, or providing a blocking function. Thus an ideal diode acts as a switch, either open or closed, depending upon the polarity of the voltage placed across it. The ideal diode has zero resistance under forward bias and infinite resistance under reverse bias.

The PN junction diode will perform satisfactorily only if it is operated within certain limiting values. They are the following: It is the highest instantaneous current under forward bias condition that can flow through the junction. It is the maximum reverse voltage that can be applied to the PN junction. If the voltage across the junction exceeds PIV, under reverse bias condition, the junction gets damaged. It is the maximum power that can be dissipated at the junction without damaging the junction. Power dissipation is the product of voltage across the junction and current through the junction.

It is usually given at a special temperature, usually 25°C, (77°F) and refers to the maximum amount of average current that can be permitted to flow in the forward direction. If this rating exceeds its limit, then the structure breakdown can occur. It is the maximum peak current that can be permitted to flow in the forward direction in the form of recurring pulses. The limiting value of this current is 450 mA. It is the maximum current permitted to flow in the forward direction in the form of nonrecurring pulses. The current should not equal this value for more than a few milliseconds. The above diode rating are subject to change with temperature variations. If the operating temperature is more than that stated for the rating, then the ratings must be decreased.

Consider that a PN junction has P-type and N-type materials in close physical contact at the junction on an atomic scale. Hence, the energy band diagrams of these two regions undergo relative shift to equalise the Fermi level. The Fermi level EF should be constant throughout the specimen at equilibrium. The distribution of electrons or holes in allowed energy states is dependent on the position of the Fermi level. If this is not so, electrons on one side of the junction would have an average energy higher than those on the other side, and this causes transfer of electrons and energy until the Fermi levels on the two sides get equalised. However, such a shift does not disturb the relative position of the conduction band, valence band and Fermi level in any region. Equalisation of Fermi levels in the P and N materials of a PN junction is similar to equalisation of levels of water in two containers on being joined together.

P region

Space charge region

Conduction band

N region

Conduction band

Ecp 1/2EG

1/2EG

E0 EF

Ecn

E1

Evp E0

E2

E0

Valence band

EF 1/2 E G

1/2 EG Evn Valence band

The energy band diagram for a PN junction is shown in Fig. 4.16, where the Fermi level EF is closer to the conduction band edge Ecn in the N-type material while it is closer to the valence band edge Evp in the P-type material. It is clear that the conduction band edge Ecp in the P-type material is higher than the conduction band edge Ecn in the N-type material. Similarly, the valence band edge Evp in the P-type material is higher than the valence band edge Evn in the N-type material. As illustrated in Fig. 4.16, E1 and E 2 indicate the shifts in the Fermi level from the intrinsic conditions in the P and N materials respectively. Then the total shift in the energy level E 0 is given by E 0 = E1 + E 2 = Ecp – Ecn = Evp – Evn This energy E 0 (in eV) is the potential energy of the electrons at the PN junction, and is equal to qV0, where V0 is the contact potential (in volts) or contact difference of potential or the barrier potential. A contact difference of potential exists across an open circuited PN junction. We now proceed to obtain an expression for E 0. From Fig. 4.16, we find that 1 EF – Evp = __ EG – E1 (4.6) 2 1 Ecn – EF = __ EG – E 2 (4.7) 2 Combining Eqs (4.6) and (4.7), we get E 0 = E1 + E 2 = EG – (Ecn – EF ) – (EF – Evp)

(4.8)

We know that np = NC NV e–EG /kT and np = n2i (Mass-action law) From the above equations, we get NC NV EG = kT ln ______ n2i

(4.9)

NC We know that for N-type material EF = EC – kT ln ___ . Therefore, from this equation, we get ND N NC C ___ Ecn – EF = kT ln ___ nn = kT ln ND NV Similarly for P-type material EF = EV + kT ln ___. Therefore, from this equation, we get NA NV NV ___ EF – Evp = kT ln p = kT ln ___ NA p Substituting from Eqs (4.9), (4.10) and (4.11) into Eqn. (4.8), we get

[

NC NV NV NC E 0 = ln ______ – ln ___ – ln ___ 2 N NA D ni

[

NC NV ___ ND ___ ND = kT ln ______ × – 2 N NV C ni

]

]

(4.10)

(4.11)

ND NA = kT ln ______ n2i

(4.12)

As E 0 = qVo, then the contact difference of potential or barrier voltage is given by ND NA kT ______ Vo = ___ q ln n 2 i In the above equations, Es in electron volts and k is in electron volt per degree Kelvin. The contact difference of potential Vo is expressed in volt and is numerically equal to E 0. From Eqn. (4.12) we note that Eo (hence Vo) depends upon the equilibrium concentrations and not on the charge density in the transition region. n2i An alternative expression for E 0 may be obtained by substituting the equations of nn ª ND, pn = ___, ND n2i nn pp = n2i , pp ª NA and np = ____ into Eqn. (4.12). Then we get NA ppo nno ___ E0 = kT ln ___ (4.13) pno = kT ln npo where subscript 0 represents the thermal equilibrium condition.

(a) The resistivities of the P-region and N-region of a germanium diode are 6 W-cm and 4W-cm, respectively. Calculate the contact potential Vo and potential energy barrier Eo. (b) If the doping densities of both P and N-regions are doubled, determine Vo and Eo. Given that q = 1.602 × 10–19 C, ni = 2.5 × 1013/cm3, mp = 1800 cm2/V-s, mn = 3800 cm2 /V-s and VT = 0.026 V at 300 K.

Solution

(a) Resistivity,

1 _______ 1 r = __ s = NA qmp 6 W – cm

Therefore,

1 1 NA = _____ = _____________________ = 0.579 × 1015/cm3 6qmp 6 × 1.602 × 10–19 × 1800

Similarly,

1 1 ND = _____ =_____________________ = 0.579 × 1015/cm3 4qmn 4 × 1.602 × 10–19 × 3800

Therefore,

ND NA 0.579 × 0.411 × 1030 V0 = VT ln ______ = 0.026 ln __________________ = 0.1545 V 2 ni (2.5 × 1013)2

Hence

E 0 = 0.1545 eV

(b)

2 × 0.579 × 1015 × 2 × 0.411 × 1015 V0 = 0.026 ln ______________________________ = 0.1906 V (2.5 × 1013)2

Therefore,

E 0 = 0.1906 eV

Let us now derive the expression for the total current as a function of applied voltage assuming that the width of the depletion region is zero. When a forward bias is applied to a diode, holes are

injected from the P-side into the N-side. Due to this, the concentration of holes in the N-side (pn) is increased from its thermal equilibrium value (pno) and injected hole concentration [Pn (x)] decreases exponentially with respect to distance (x). Pn (x) = pn – pno = Pn (0) e–x/Lp where Lp is the diffusion length for holes in the N-material. pn (x) = pno + Pn (0) e–x/Lp

(4.14)

Injected hole concentration at x = 0 is Pn (0) = pn (0) – pno

(4.15)

These several components of hole concentration in the N-side of a forward biased diode are shown in Fig. 4.7, in which the density pn (x) decreases exponentially with distance (x). Let pp and pn be the hole concentration at the edges of the space charge in the P-and N-sides, respectively. Let VB (= Vo – V) be the effective barrier potential across the depletion layer. Then pp = Pn eVB /V

T

(4.16)

where V T is the volt-equivalent of temperature. This is the Boltzmann’s relation of kinetic gas theory. This equation is valid as long as the hole current is small compared with diffusion or drift current. This condition is called low level injection. Under open circuit condition (i.e. V = 0), pp = ppo, pn = pno and VB = Vo. Equation (4.11) can be changed into ppo = pno eVo /VT

(4.17)

Under forward bias condition let V be the applied voltage, then the effective barrier voltage VB = Vo – V The hole concentration throughout the P-side is constant and equal to the thermal equilibrium value (pp = ppo). The hole concentration varies exponentially with distance into the N-side. At x = 0, pn = pn (0) Equation (4.16) can be changed into ppo = pn (0) e(Vo – V) /VT

(4.18)

Comparing Eqs (4.17) and (4.18), pn(0) = pno eV /VT This boundary condition is called the law of the junction. Substituting this into Eq. (4.15), we get Pn(0) = pno ( eV/VT – 1 ) The diffusion hole current in the N-side is

dpn(x) Ipn (x) = – Ae Dp______ dx d = – Ae Dp ___ [ pno + Pn(0) e–x/Lp ] dx

(4.19)

AeDp Pn(0) = __________ e–x/Lp Lp From this equation, it is evident that the injected hole current decreases exponentially with distance. The hole current crossing the junction into the N-side with x = 0 is AeDp Pn(0) AeDp pno Ipn(0) = __________ = ________ ( eV/VT – 1 ) Lp Lp The electron current crossing the junction into the P-side with x = 0 is AeDn Np(0) AeDn npo Inp(0) = __________ = ________ (eV/VT – 1) Ln Ln The total diode current, I = Ipn (0) + Inp (0) = Io ( eV/VT – 1 ) Ae Dp pno AeDn npo where Io = _________ + ________ = reverse saturation current. Lp Ln If we consider carrier generation and recombination in the space-charge region, the general equation of the diode current is approximately given by I = Io [ e(V/h VT) – 1 ] where V = external voltage applied to the diode, and h = a constant, 1 for germanium and 2 for silicon. 2 n2i i We know that pn = ___ and np = ___. Applying these relationships in ND NA the above equation of reverse saturation current, Io, we get

[

]

Dp Dn Io = Ae ______ + ______ n2i Lp ND Ln NA where 2i = Ao T3 e–EGo /kT = Ao T3 e–VGo/VT, where VGo is a voltage which is numerically equal to the forbidden gap energy EGo in electron volts. For a germanium diode, the diffusion constants Dp and Dn vary approximately inversely proportional to T. Hence, the temperature dependence of Io is –VGo _____ VT

Io = K1 T 2 e

where K1 is a constant independent of temperature. For a silicon diode, Io is proportional to ni instead of n2i . Hence, 3 __

–VGo _____

Io = K2 T 2 e 2VT where K 2 is a constant independent of temperature.

The diode current equation relating the voltage V and current I is given by I = Io [ e(V/hVT) – 1 ] where

where

I= Io = V= h = VT =

diode current diode reverse saturation current at room temperature external voltage applied to the diode a constant, 1 for germanium and 2 for silicon kT/q= T/11600, volt-equivalent of temperature, i.e., thermal voltage,

k = Boltzmann’s constant (1.38 × 10 –3 J/K) q = charge of the electron (1.602 × 10 –19 C) T = temperature of the diode junction (K) = (°C + 273°)

At room temperature, (T = 300 K), V T = 26 mV. Substituting this value in the current equation, we get I = Io [e (40 V/h) – 1] Therefore, for germanium diode, I = Io [e40V – 1], since h = 1 for germanium. For silicon diode, I = Io [e20V – 1], since h = 2 for silicon. If the value of applied voltage is greater than unity, then the equation of diode current for germanium, I = Io (e40V) and for silicon,

I = Io (e20V)

When the diode is reverse biased, its current equation may be obtained by changing the sign of the applied voltage V. Thus, the diode current with reverse bias is I = Io [ e(–V/h VT) – 1 ] If V >> V T, then the term e(–V/h VT) > Io in the vertical-slope section of the characteristics. Therefore, dI ____ I ___ @ dV hVT Therefore,

hVT dV ___ = rf = ____ I dI

hVT The dynamic resistance varies inversely with current, i.e. rf = ____, where VT = T/1600, the volt I equivalent of temperature (T) of the diode junction (K) and h is a constant whose value is equal to 1 for Germanium and 2 for Silicon diodes. At room temperature VT = 26 mV. a.c. resistance of a diode is the sum of bulk resistance rb and junction resistance rj. Bulk resistance (rb) is the sum of ohmic resistance of the P-and N-type semiconductors.

It is the resistance associated with the device for the region if the input signal is sufficiently large to produce a wide range of the characteristics as shown in Fig. 4.19. Therefore,

IF (mA)

20

15

rav

DV = ___ point to point DI

|

DI

10

As with the d.c. and a.c. resistance levels, the lower the level of currents used to determine the average, the higher is the resistance level.

5

It is the resistance offered by the PN junction diode under reverse bias condition. It is very large compared to the forward resistance, which is in the range of several MW.

0 0.1 0.20.3 0.4 0.5 0.6 0.7 0.8 0.9 1 VF (V )

Determine the forward resistance of a PN junction diode when the forward current is 5 mA at T = 300 K. Assume silicon diode.

Solution

Given For a silicon diode, the forward current, I = 5 mA, T = 300 K

hVT T Forward resistance of a PN junction diode, rf = ____, where VT = ______ and h = 2 for silicon I 11,600 T 2 × ______ 11,600 2 × 300 rf = __________ = ________________ = 10.34 W 5 × 10 – 3 11,600 × 5 × 10 – 3

Therefore,

Find the value of dc resistance and ac resistance of a germanium junction diode at 25°C with Io = 25 mA and at an applied voltage of 0.2 V across the diode.

Solution

Given

Io = 25 mA, T = 25°C = 298 K and V = 0.2 Volts

(

)

V 0.2 I = Io _______ = 25 × 10 – 6 __________ = 54.79 mA –3 hVT 26×10 e –1 e –1 d.c. resistance

(

V 0.2 RF = __ = ___________ = 3.65 W I 54.79 × 10 – 3

For germanium,

KT h = 1, VT = ___ q = 25.71 mV

a.c. resistance

hVT 25.71 × 10 – 3 rF = ____ = ___________ = 0.47 W I 54.79 × 10 – 3

)

Calculate the dynamic forward and reverse resistance of a PN junction diode when the applied voltage is 0.25 V at T = 300 K given Io = 2 mA.

Solution

Given

At

V = 0.25 V, T = 300 K, Io = 2 mA T = 300 K, VT = 26 mV.

Assuming it to be silicon diode, h = 2

(

V

)

____ 0.25 I = Io e hVT – 1 = 2 × 10 – 6 _____________ = 0.24 mA 2 × 26 × 10 – 3 e –1

Therefore,

(

)

hVT 2 × 26 × 10 – 3 rF = ____ = ____________ = 216.67 W I 0.24 × 10 – 3 For germanium diode,

h = 1.

(

Reverse resistance

)

(

)

V 0.25 = 2 × 10 – 6 __________ = 0.03 A I = Io _______ 26×10 – 3 ehVT – 1 e –1 hVT 26 × 10 – 3 rF = ____ = _________ = 0.867 W I 0.03 V 0.25 __ = ________ = 125 kW Io 2 × 10 – 6

A PN-junction diode has a reverse saturation current of 30 mA at a temperature, of 125°C. At the same temperature, find the dynamic resistance for 0.2 V bias in forward and reverse directions.

Solution

Given The reverse saturation current, Io = 30 × 10 – 6 A and V = 0.2 V

hVT We know that the dynamic resistance = _______ IoeV/hVT 125 + 273 T Here, h = 1 for germanium and VT = ______ = _________ = 34.3 mV 11,600 11,600 34.3 × 10 – 3 Therefore, forward dynamic resistance rf = ____________________ – 3 = 3.356 W 30 × 10 – 6 (e0.2/34.3×10 ) hVT 34.3 × 10 – 3 Reverse dynamic resistance, rr = ________ = ______________________ – 3 = 389.5 kW – V/hVT Ioe 30 × 10 – 6 (e – 0.2/34.3 × 10 )

If two similar Germanium diodes are connected back to back and the voltage V is impressed upon, calculate the voltage across each diode and current through each diode. Assume similar value of Io = 1 mA for both the diodes and h = 1.

Solution

The arrangement is shown in the Fig. 4.20.

As D1 is reverse biased, the total current flowing in the circuit is I0 = 1mA. The diode D2 is forward biased and its forward current is equal to the reverse current I0 = 1mA, which can flow as D1 is reverse biased.

I0

D1

D2

VD

VD

For diode D2, I = I0 = 1 mA and voltage across D2 is VD2.

2

+ – V

I = I0 [eV/hVT – 1]

Therefore,

VD /hVT

or Hence,

1

I0 = I0 [e

2

– 1]

VD /hVT

e

=1+1=2 V D2 ____ = ln 2 hVT 2

VD2 = hVT × ln 2 = 1 × 26 × 10 – 3 × 0.6931 = 0.01802 V Therefore,

VD1 = V – VD2 = V – 0.01802 V

The current through the diodes D1 and D2 is I = I0 = 1 mA

Determine the forward resistance of a PN junction diode, when the forward current is 5 mA at T = 300 K. Assume Silicon diode.

Solution

Given: For a silicon diode, the forward current, I = 5 mA. T = 300 K

hVT T Forward resistance of a PN junction diode, rf = ____ where VT = ______ and h = 2 for silicon I 11,600

Therefore,

T 2 × ______ 11,600 2 × 300 rf = __________ = ________________ = 10.34 W –3 5 × 10 – 3

Under reverse bias condition, the majority carriers move away from the junction, thereby uncovering more immobile charges. Hence the width of the space–charge layer at the junction increases with reverse voltage. This increase in uncovered charge with applied voltage may be considered a capacitive effect. The parallel layers of oppositely charged immobile ions on the two sides of the junction form the capacitance, CT, which is expressed as

| |

dQ CT = ___ dV

where dQ is the increase in charge caused by a change in voltage dV. A change in voltage dV in a time dt will result in a current I = dQ/dt given by dV I = CT ___ m dt

Therefore CT is important while considering a diode or a transistor as a circuit element. The quantity CT is called the transition, space–charge, barrier or depletion region capacitance.

A PN junction is formed from a single-crystal intrinsic semiconductor by doping part of it with acceptor impurities and the remaining with donors. A junction between P-type and N-type materials may be fabricated in a variety of ways. The change in impurity concentration from P to N-type semiconductor occurs in a very short length, typically much less than 1 mm. In an abrupt PN junction, there is a sudden step change from acceptor ions on one side to donor ions on the other side. Such a junction is fabricated by placing trivalent indium against N-type germanium and heating the combination to a high temperature for a short time. Since some of the indium dissolves into the germanium, the N-type germanium is changed into P-type at the junction. Such a step-graded junction is called an alloy, or fussion junction. A step-graded junction is also formed between emitter and base of an integrated transistor. A diffused junction is graded in which case the donor and acceptor concentrations are functions of distance across the junction. Then the acceptor density, NA, gradually decreases and the donor density, ND, gradully increases till NA = ND is reached. Therefore, ND increases and NA decreases to zero. It is not necessary for the abrupt junction to be symmetrical, that is, the doping concentrations at either side of the junction are dissimilar. As shown in Fig. 4.21, consider a PN diode which is asymmetrically doped at the junction. Since the net charge is zero, then eNAWp = eNDWn. If NA >> ND , then Wp > Io for a forward characteristics, we have I = Io eV/hVT Substituting Eq. 4.24 into Eq. 4.25, we get I = KT m e – VGO /hVT ◊ eV/hVT

(4.25)

= KT m e(V–VGO)/hVT

(4.26)

Since VT = kT, where k is Boltzmann’s constant, I = KT m e(V – VGO)/h kT For a constant diode current, dI/dT = 0. Hence, differentiating the above equation with respect to T, we get dI d V – VGo ___ = K mT m – 1 e(V – VGo)/hkT + Tm e (V – VGo)/hkT ◊ ___ _______ dT dT hkT

[

=Ke

)]

(

(V – VGo)/hkT

[

mT

m–1

(

dV T ___ – (V – VGo) × 1 dT Tm __________________ ___ + hk T2

dV mTm Tm = K e(V–VGo)/hkT _____ + _____2 T ___ – (V – VGo T dT hkT

[

(

)]

)]

Note that VGo is forbidden energy gap at 0K and hence it is a constant from differentiation point of view. Taking Tm outside and rearranging the above equation, we get

[

(

)

dV mhkT + T ___ – (V – VGo) dT dI ___ (V–VGo)/hkT m ________________________ =Ke ×T dT hkT 2

]

dV Tm = K e (V – VGo)/hkT × _____2 mhkT + T ___ – (V – VGo) dT hkT

)]

dV dI T m–1 ___ = K e (V – VGo)/hkT × _____ mhVT + T ___ – (V – VGo) hVT dT dT

)]

[

(

Replacing kT with VT, we get

[

(

dI Now ___ = 0 for constant diode current. Hence, equating the above equation to zero, we get dT dV mhVT + T ____ – (V – VGo) = 0 dT dV T ___ = V – VGo – mhVT dT V – (VGo – mhVT) dV ___ = ________________ T dT This is the required change in voltage necessary to keep diode current constant. Hence for germanium, at cut-in voltage V = Vg = 0.2 V and with m = 2, h = 1, T = 30 K and VGo = 0.785 V in the above equation, we get

0.2 – (0.785 + 2 × 1 × 26 × 10 – 3) dV ___ = ____________________________ = – 2.12 mV/°C for Ge 300 dT The negative sign indicates that the voltage must be reduced at a rate of 2.12 mV per degree change in temperature to keep diode current constant. dV Similarly, ___ = – 2.3 mV/°C, for Si dT dV Practically, the value of ___ is assumed to be –2.5 mV/°C for either Ge or Si at room temperature. dT dV ___ = – 2.5 mV/°C Thus, (4.27) dT The negative sign indicates that dV/dT decreases with increase in temperature.

To study by what rate Io changes with respect to temperature, consider Eq. (4.24) again. That is, Io = KTm e–VGo/

VT

Taking logarithm on both sides, we get ln (Io) = ln (KTm e – VGo/

VT)

VGo = ln K + ln Tm – ____ VT VGo = ln K + m ln T – ____ VT Substituting VT = kT, we get VGo ln (Io) = ln K + m ln T – ____ kT Differentiating this equation with respect to T, we get VGo d ln (Io) m VGo – 1 m _______ = 0 + __ – ____ ___ = __ + _____2 2 T T dT k T kT Replacing kT with VT we have

( )

VGo d [ln Io] __ m _______ = + ______ T TVT dT For germanium, substituting the values of various terms terms at room temperature, we get d [ln Io] ____ 0.785 2 _______ + __________________ = 0.11 per °C = 300 1 × 300 × 26 × 10 – 3 dT This indicates that Io increases by 11 % per degree rise in temperature. For silicon, we get d [ln Io] _______ = 0.08 per °C dT

This indicates that Io increases by 8 % per degree rise in temperature. Practically it is found that the reverse saturation current Io increases by 7 % per °C change in temperature for both silicon and germanium diodes. If at T°C is 1 A, then at (T + 1) °C, it becomes 1.07 A and so on. From this, it can be concluded that reverse saturation current approximately doubles i.e 1.0710 for every 10°C rise in temperature. The above result can be mathematically represented as,

(

T2 – T1 _______ 10

I02 = 2

)I

01

( ___T )

= 2 10 I01

where I02 is the, reverse saturation current at T2 and I01 is the reverse saturation current at T1.

The rise in temperature increases the generation of electron–hole pairs in semiconductors and increases their conductivity. As a result, the current through the PN junction diode increases with temperature as given by the diode current equation, I = Io [e(V/

VT)

– 1]

The reverse saturation current Io of diode increases approximately 7 percent/°C for both germanium and silicon. Since (1.07)10 2, reverse saturation current approximately doubles for every 10°C rise in temperature. Hence, if the temperature is incrcased at fixed voltage, the current I increases. To bring the current I to its original value, the voltage V has to be reduced. It is found that at room temperature dV for either germanium or silicon, ___ dT value.

– 2.5 mV/°C in order to maintain the current I to a constant IF (mA)

At room temperature, i.e. at 300 K, the value of barrier voltage or cut-in voltage is about 0.3 V for germanium and 0.7 V for silicon. The barrier voltage is temperature dependent and it decreases by 2 mV/°C for both germanium and silicon. This fact may be expressed in mathematical form, which is given by

75° C

VR (volts)

VF (volts) 0

Io2 = Io1 × 2 (T2 – T1)/10 where Io1 = saturation current of the diode at temperature (T1), and I02 = saturation current of the diode at temperature (T2). Figure 4.22 shows the effect of increased temperature on the characteristic curve of a PN junction diode. A germanium diode can be used up to a maximum of 75 °C and a silicon diode to a maximum of 175 °C.

25° C

25° C

75° C

IR ( A)

The voltage across a silicon diode at room temperature (300 K) is 0.7 Volts when 2 mA current flows through it. If the voltage increases to 0.75 V, calculate the diode current (assume VT = 26 mV).

Solution

Given data

Room temperature = 300 K Voltage across a silicon diode, VD1 = 0.7 V Current through the diode ID1 = 2 mA When the voltage increases to 0.75 V, VD2, then Io (eVD2/VTh – 1) ________________ ID2 ______________ e0.75/26 × 10 × 2 – 1 ___ = = = 2.615 –3 ID1 I (eVD1/VTh – 1) e0.7/26×10 × 2 – 1 o ID2 = 2.615 × ID1 = 2.615 × 2 × 10 – 3 = 5.23 mA –3

Therefore,

A silicon diode has a saturation current of 7.5 mA at room temperature 300 K. Calculate the saturation current at 400 K.

Solution

Given Io1 = 7.5 × 10 – 6 A at T1 = 300 K = 27°C and T2 = 400 K = 127°C

Therefore, the saturation current at 400 K is Io2 = Io1 × 2(T2 – T1)/10 = 7.5 × 10 – 6 × 2(127 – 27)/10 = 7.5 × 10 – 6 × 210 = 7.68 mA

The reverse saturation current of the Ge transistor is 2 mA at room temperature of 25°C and increases by a factor of 2 for each temperature increase of 10°C. Find the reverse saturation current of the transistor at a temperature of 75°C.

Solution

Given Io1 = 2 mA at T1 = 25°C, T2 = 75°C

Therefore, the reverse saturation current of the transistor at T2 = 75°C is Io2 = Io1 × 2(T2 – T1)/10 = 2 × 10 – 6 × 2(

75 – 25 ______ 10

)

= 2 × 10 – 6 × 25 = 64 mA

Diodes are often used in a switching mode. When the applied bias voltage to the PN diode is suddenly reversed in the opposite direction, the diode response reaches a steady state after an interval of time, called the recovery time. The forward recovery time, tfr, is defined as the time required for forward

voltage or current to reach a specified value (time interval between the instant of 10% diode voltage to the instant this voltage reaches within 10% of its final value) after switching diode from its reverse- to forward-biased state. Fortunately, the forward recovery time possess no serious problem. Therefore, only the reverse recovery time, trr, has to be considered in practical applications. When the PN junction diode is forward biased, the minority electron concentration in the P-region is approximately linear. If the junction is suddenly reverse biased, at t1, then because of this stored electronic charge, the reverse current (IR) is initially of the same magnitude as the forward current (IF ). The diode will continue to conduct until the injected or excess minority carrier density (p – po) or (n – no) has dropped to zero. However, as the stored electrons are removed into the N-region and the contact, the available charge quickly drops to an equilibrium level and a steady current eventually flows corresponding to the reverse bias voltage as shown in Fig. 4.23(c). As shown in Fig. 4.23(b), the applied voltage Vi = VF for the time up to t1 is in the direction to forward-bias the diode. The resistance R L is large so that the drop across R L is large when compared VF to the drop across the diode. Then the current is I ª ___ = IF. Then, at time t = t1, the input voltage RL is suddenly reversed to the value of – VR. Due to the reasons explained above, the current does not VR become zero and has the value I = ___ = – IR until the time t = t2. At t = t2, when the excess minority RL carriers have reached the equilibrium state, the magnitude of the diode current starts to decrease, as shown in Fig. 4.23(d). During the time interval from t1 to t2, the injected minority carriers have remained stored and hence this time interval is called the storage time (ts). After the instant t = t2, the diode gradually recovers and ultimately reaches the steady-state. The time interval between t2 and the instant t3 when the diode has recovered nominally, is called the transition time, tt. The recovery is said to have completed (i) when even the minority carriers remote from the junction have diffused to the junction and crossed it, and (ii) when the junction transition capacitance, CT, across the reverse-biased junction has got charged through the external resistor R L to the voltage –VR. The reverse recovery time (or turn-off time) of a diode, trr, is the interval from the current reversal at t = t1 until the diode has recovered to a specified extent in terms either of the diode current or of the diode resistance, i.e. trr = ts + tt. For commercial switching type diodes the reverse recovery time, trr, ranges from less than 1 ns up to as high as 1 ms. This switching time obviously limits the maximum operating frequency of the device. If the time period of the input signal is such that T = 2 ◊ trr, then the diode conducts as much in reverse as in the forward direction. Hence it does not behave as a one way device. In order to minimise the effect of the reverse current, the time period of the operating frequency should be a minimum of approximately 10 times trr. For example, if a diode has trr of 2 ns, its maximum operating frequency is 1 1 1 fmax = __ = _______ = ____________ = 50 MHz T 10 × trr 10 × 2 × 10–9 The trr can be reduced by shortening the length of the P-region in a PN junction diode. The stored charge and, consequently, the switching time can also be reduced by introduction of gold impurities into the junction diode by diffusion. The gold dopant, some times called a life timekiller, increases

+

+ Vi

V

–

i

RL

– (a) Vi VF

t

0

–VR (b) pn – pno at junction t

(c) i IF =

VF RL I0 0

– IR =

t

VF RL (d) v

t

0

–VR

t1 Forward bias

Minority carrier storage ts

t2

Transition interval, tt

Reverse recovery time, trr (e)

t3

the recombination rate and removes the stored minority carriers. This technique is used to produce diodes and other active devices for high speed applications.

The diode equation predicts that, under reverse bias conditions, a small constant current, the saturation current, Io, flows due to minority carriers, which is independent of the magnitude of the bias voltage. But this prediction is not entirely true in practical diodes. There is a gradual increase of reverse current with increasing bias due to the ohmic leakage currents around the surface of the junction. Also, there is a sudden increase in reverse current due to some sort of breakdown, when IF (mA)

VR

VBD, A

VBD, Z

O

+VF

Avalanche breakdown Zener breakdown

IR(mA)

the reverse bias voltage approaches a particular value called breakdown voltage, VBD, as shown in Fig. 4.24. Once breakdown occurs, the diode is no longer blocking current and the diode current can be controlled only by the resistance of the external circuit. The breakdown occurs due to avalanche effect in which thermally generated minority carriers cross the depletion region and acquire sufficient kinetic energy from the applied potential to produce new carriers by removing valence electrons from their bonds. These new carriers will in turn collide with other atoms and will increase the number of electrons and holes available for conduction. This multiplication effect of free carriers may be represented by the following equation: 1 M = __________n V ____ 1– VBD

( )

where M = carrier multiplication factor, which is the ratio of the total number of electrons leaving the depletion region to the number entering the region V = applied reverse voltage VBD = reverse breakdown voltage n = empirical constant, which depends on the lattice material and the carrier type, for N-type silicon, n ª 4 and for P-type, n ª 2 It is evident from the above equation that M is being very small for V = 0.9 VBD. But when V > 0.9 VBD, M is very large and the resulting reverse current is given by IR = MIo, where Io is the reverse saturation current before breakdown. As V approaches the breakdown voltage VBD, the value of M will become infinite and there is a rapid increase in carrier density and a corresponding increase in current. Because of the cumulative increase in carrier density after each collision, the process is known as avalanche breakdown. Even if the initially available carriers do not gain enough energy to disrupt bonds, it is possible to initiate breakdown through a direct rupture of the bonds because of the existence of strong electric field. Under these circumstances the breakdown is referred to as Zener breakdown. Voltage reference diodes that utilise the almost constant voltage characteristics in the breakdown region are also called avalanche diodes or sometimes Zener diodes. The Zener effect is in diodes with breakdown voltage below 6 V. The operating voltage in avalanche breakdown are from several volts to several hundred volts with power ratings up to 50 W. True Zener diode action displays a negative temperature coefficient, i.e, breakdown voltage decreases with increasing temperature. True avalanche diode action exhibits a positive temperature coefficient, i.e. breakdown voltage increases with increasing temperature. It is clear that the breakdown voltage for a particular diode can be controlled during manufacture by altering the doping levels in the junction. The breakdown voltage for silicon diodes can be made to occur at a voltage as low as 5 V with 1017 impurity atoms per cubic cm or as high as 1000 V when doped to a level of only 1014 impurity atoms per cubic cm.

The PN junction diode is considered as a circuit element. The basic diode circuit shown in Fig. 4.25 consists of a d.c. voltage VS which is supplied across a resistor and a diode. In order to find the instantaneous diode voltage V and current I, the circuit can be analysed when the instantaneous source voltage is VS. From Kirchhoff’s voltage law (KVL), the instantaneous diode voltage is

which can be expressed as

VS = IR + V

(4.28)

VS V I = ___ – __ R R

(4.29)

The ideal diode current equation relating the diode voltage VD and the current ID is I = I0 [ e(V/hVT) – 1 ]

(4.30)

where I 0 is the diode reverse saturation current at room temperature, is a constant (1 for Ge and T 2 for Si) and V T is the thermal voltage, i.e., VT = ______ in which T is the temperature of the diode 11,600 junction (300 K) or V T = 26 mV at room temperature. Substituting Eq. (4.30) into Eq. (4.28), we get VS = I0 R[ e(V/

VT )

– 1] + V

(4.31)

which has only one unknown variable V. Since Eq. (4.31) is a transcendental equation, this equation cannot be solved directly. As these equations contain both linear and exponential terms, it is difficult to solve by hand. The iteration (trial and error) technique can be used to find a solution to this equation. The graphical analysis technique involves plotting two simultaneous equations and locating their point of intersection, which is called the quiescent point, or the Q-point.

The use of the load line construction allows the graphical analysis of many circuits including devices which are much more complicated than the PN diode. Two plots are needed to determine the operating point of the diode. One plot is drawn using Kirchhoff's current and voltage laws and other is by plotting the volt–ampere characteristic of the diode. VR From KCL, I = IR and from KVL, V + VR = VS as shown in Fig. 4.25. The relationship between diode current I and voltage R + V V is obtained from the diode characteristics curve as shown in Vs + I = IR – – Fig. 4.26(a). From Ohm’s law, the current through the resistor and the voltage across the resistor are linearly related as shown in Fig. 4.26(b). Current

Current

+ = Vs

Diode Resistor

IR

I =

V (a)

Voltage

VR (b)

Voltage

To draw the load line, flip the resistor curve horizontally such that the slope of the curve is –1/R and push the two curves, as shown in Figs 4.27(a) and 4.27(b), together horizontally until the y-axes are VS apart.

Current

push

Current

push

“flipped” resistor line Slope = – 1 R

Diode I

IR

Voltage

V

Voltage add to Vs

(a)

VR

(b)

The intersection point of the flipped resistor line called load line and the diode static characteristics curve is the operating point of the device, as shown in Fig. 4.28. Current

Operating point or quiescent point

Load line I

IR

Voltage V

VR VS

In the second method to draw the load line, I is determined when the device is short-circuited and V is determined when the device is open-circuited, so that the point B(V = 0, I = VS /R) and A(V = VS, I = 0) lies somewhere on the Current y-axis and x-axis respectively of the (V = 0, I = VS /R) diode characteristics curve as shown B in Fig. 4.29. Thus a straight line drawn Diode characteristic connecting the points A and B is called the load line. This load line intersects Operating point the diode characteristics at some point which is chosen as operating point for Load line the device. The operating point provides the diode voltage V, appearing across (V =VS, I = 0) the diode and the current I, flowing A Voltage through the diode.

As the volt–ampere relationship of the diode is non-linear, the analysis of circuits containing diodes is difficult. With the help of piecewise linear approximation model of the diode, the results can easily be obtained. The particular regions of operation of the volt–ampere characteristics of the diode are broken into linear segments and the concept of a diode cut-in voltage is also used in this piecewise linear model. If the reverse resistance R r is included in the diode characteristics, then the piecewise linear and continuous volt–ampere characteristic is obtained. Piecewise linear model is used when a more accurate model than ideal-diode model is needed but not resorted to nonlinear equation or graphical technique. The piecewise linear model for diode is obtained by using following steps: 1. Approximate the actual V–I characteristics by straight-line segments. 2. Model each section (forward and reverse characteristics) with a resistance in series with a constant voltage source. The simple piecewise linear equivalent for the diode is shown in Fig. 4.30. Current

Rf

= open circuit =

Vg

Rr

Voltage Vg

Since the diode is a binary device, it can exist in only one of two possible states, i.e., the diode is either in ON or OFF state at a given time. If the voltage applied across the diode exceeds the cut-in voltage, Vg , the diode is forward biased and is said to be in ON state with diode forward resistance Rf. For a reverse bias, the diode is open circuited and is said to be in OFF state with infinitely large reverse resistance R r. The piecewise linear model is used for analysis of the diode circuits. Consider a circuit containing several diodes, resistors and power supplies. This type of circuit is analyzed by assuming the state of the diode. For ON state, the diode is replaced with Rf value and for the OFF state, the diode is replaced with R r value. After replacing the diode with this piecewise model, the entire circuit is linear and now by using Kirchhoff’s voltage and current laws, the entire current and voltage in the circuit and be calculated. The assumption that a diode is ON can be verified by observing the sign of the current through it. If the current is in forward direction, then the assumption of the diode is justified.

However, if the current is in the reverse direction, then the diode assumption is incorrect. Under this circumstance, the analysis must begin again with the diode assumed to be OFF. Similar to the above trial-and error method, the diode OFF condition is tested by finding the voltage across it. If the voltage is either in the reverse direction or in the forward direction with a voltage less than Vg , the turn-on or cut-in voltage of the diode, then the diode assumption is correct. However, if the diode voltage is in the forward direction with voltage greater than Vg , the condition of the diode is ON and the original assumption is not correct. Under this circumstance, the analysis must begin again with the diode assumed to be ON.

An ideal PN junction diode is a two terminal polarity sensitive device that has zero resistance (diode conducts) when it is forward biased and infinite resistance (diode does not conduct) when reverse biased. Due to this characteristic the diode finds number of applications as given below. (i) rectifiers in d.c. power supplies (ii) switch in digital logic circuits used in computers (iii) clamping network used as d.c. restorer in TV receivers and voltage multipliers (iv) clipping circuits used as wave shaping circuits used in computers, radars, radio and TV receivers (v) demodulation (detector) circuits. The same PN junction with different doping concentration finds special applications as follows: (i) idetectors (APD, PIN photo diode) in optical communication circuits (ii) Zener diodes in voltage regulators (iii) varactor diodes in tuning sections of radio and TV receivers (iv) light emitting diodes in digital displays (v) LASER diodes in optical communications (vi) Tunnel diodes as a relaxation oscillator at microwave frequencies.

In addition to the PN junction diode, other types of diodes are also manufactured for specific applications. These special diodes are two terminal devices with their doping levels carefully selected to give the desired characteristics.

When the reverse voltage reaches breakdown voltage in normal PN junction diode, the current through the junction and the power dissipated at the junction will be high. Such an operation is destructive and the diode gets damaged. Whereas diodes can be designed with adequate power dissipation capabilities to operate in the breakdown region. One such diode is known as Zener diode. Zener diode is heavily doped than the ordinary diode. From the V–I characteristics of the Zener diode, shown in Fig. 5.1, it is found that the operation of Zener diode is same as that of ordinary PN diode under forward-biased condition. Whereas under reverse-baised condition, breakdown of the junction occurs. The breakdown voltage depends upon the amount of doping. If the diode is heavily doped, depletion layer will be thin and, consequently, breakdown occurs at lower reverse voltage and further, the breakdown IF (mA) voltage is sharp. Whereas a lightly doped diode has a higher breakdown voltage. Thus breakdown voltage can be selected with the amount of doping. The sharp increasing current under breakdown conditions are due to the following two mechanisms. (1) Avalanche breakdown (2) Zener breakdown.

As the applied reverse bias increases, the field across the junction increases correspondingly. Thermally generated carriers while

VR

VZ

VF A

0

B IR (mA)

traversing the junction acquire a large amount of kinetic energy from this field. As a result the velocity of these carriers increases. These electrons disrupt covalent bond by colliding with immobile ions and create new electron-hole pairs. These new carriers again acquire sufficient energy from the field and collide with other immobile ions thereby generating further electron–hole pairs. This process is cumulative in nature and results in generation of avalanche of charge carriers within a short time. This mechanism of carrier generation is known as Avalanche multiplication. This process results in flow of large amount of current at the same value of reverse bias.

When the P and N regions are heavily doped, direct rupture of covalent bonds takes place because of the strong electric fields, at the junction of PN diode. The new electron–hole pairs so created increase the reverse current in a reverse biased PN diode. The increase in current takes place at a constant value of reverse bias typically below 6 V for heavily doped diodes. As a result of heavy doping of P and N regions, the depletion region width becomes very small and for an applied voltage of 6 V or less, the field across the depletion region becomes very high, of the order of 107 V/m, making conditions suitable for Zener breakdown. For lightly doped diodes, Zener breakdown voltage becomes high and breakdown is then predominantly by Avalanche multiplication. Though Zener breakdown occurs for lower breakdown voltage and Avalanche breakdown occurs for higher breakdown voltage, such diodes are normally called Zener diodes.

Let us consider two resistances of the Zener diode (i) d.c. or static resistance and (ii) a.c. or dynamic resistance. It is the ratio of total Zener diode voltage to total diode curVZQ rent measured at the given operating point, i.e. RZ = ____. For more precise calculation, a Zener IZQ diode can be replaled by an ideal battery in series with a small Zener resistance RZ. It is defined as voltage difference divided by current difDVZ ference at the given operating point, i.e. rZ = ____. If the dynamic resistance is less, then the Zener DIZ diode will be better as a voltage regulator. The Zener diode will perform satisfactorily only if it is operated within certain limiting values. They are the following: It is the minimum reverse current where the breakdown becomes stable. If a Zener diode has to remain in the breakdown region the current through it has to be more than IZ min. It is related to the power rating PZ max as PZ max IZ max = ______ VZ

where VZ is the Zener voltage. This parameter gives the maximum current a Zener diode can The power dissipation of a Zener diode equals the product of its Zener voltage and current, i.e. PZ = VZ ◊ IZ. As long as PZ is less than the maximum power rating PZ max, the Zener diode can operate in the breakdown region without being destroyed. The Zener voltage VZ changes with the temperature. The percentage change in the Zener voltage VZ for every °C change in temperature is called temperature coefficient (TC) of a Zener diode. It is denoted as TC and expressed as % / °C. Mathematically it can be defined as DVZ TC = ___________ × [100] % / °C VZ (T1 – T0) where T1 is the final temperature of junction while T0 is generally 25°C at which normal Zener voltage VZ is specified. DVZ is the resulting change in the Zener voltage due to the temperature variation. A positive value of TC indicates that there is an increase in VZ due to increases in temperature or decrease in VZ due to decrease in temperature. The negative value of TC indicates that there is an increase in VZ due to decrease in temperature or decrease in VZ due to increase in temperature. From Eqn. (1), we have VZ TC (T1 – T0) VZ TC DT DVZ = ______________ = _________ 100 100 where DT is the change in temperature. Sometimes TC for a Zener diode is expressed in mV/°C and in such a case, the corresponding change in VZ can be obtained as DVZ = TC (T1 – T0) = TC × DT For a Zener diode with VZ less than 6 V, the temperature coefficient is negative and hence VZ decreases as temperature increases. While for a Zener diode with VZ greater than 6 V, the temperature coefficient is positive and hence VZ increases as temperature increases. From the Zener characteristics shown in Fig. 5.1, under the reverse bias condition, the voltage across the diode remains almost constant although the current through the diode increases as shown in region IL R + AB. Thus, the voltage across the Zener diode serves IZ as a reference voltage. Hence, the diode can be used as a voltage regulator. Vin RL Vo VZ In Fig. 5.2 it is required to provide constant voltage across load resistance RL, whereas the input voltage may be varying over a range. As shown, Zener diode is reverse biased and as long as the input voltage

(a) – (b)

does not fall below VZ (Zener breakdown voltage), the voltage across the diode will be constant and hence the load voltage will also be constant.

Zener diodes are normally used under the reverse bias condition. Their breakdown voltages are normally greater than 2 V. Forward conduction occurs in the voltage around 0.7 V (Si). The breakdown, i.e. Zener effect under the reverse bias condition can also be obtained near zero (around 0.1 V). i Figure 5.3 shows the characteristics of a backward diode. It is called a backward diode because it conducts better in the reverse than in the forward direction. Figure 5.4 shows the low level rectifier circuit using a backward diode. Consider a sine wave with a peak of 0.5 V is given as the input to the backward diode. This voltage (0.5 V) is not enough to forward bias the diode into conduction, but it is enough to breakdown the diode. Hence, the output is a rectified half wave signal with a peak of 0.4 V (0.1 V is lost across the diode). Backward diodes are used to rectify weak signals whose peak amplitudes are between 0.1 and 0.7 V.

0.5 V (peak)

–0.1 V V

0.7 V

0.4 V (peak)

The varactor, also called a varicap, tuning or voltage variable capacitor diode, is a junction diode with a small impurity dose at its junction, which has the useful P N property that its junction or transition capacitance is easily + + + – – + – – varied electronically. When any diode is reverse biased, a depletion region is formed, as seen in Fig. 5.5. The larger the reverse bias applied across the diode, the width of the depletion layer “W ” becomes wider. Conversely, by decreasing the reverse bias voltage, the depletion region width “W” becomes narrower. This depletion region is devoid of majority carriers and acts like an insulator preventing conduction between the N and P regions of the diode, just like a dielectric, which separates the two plates of a capacitor. The varactor diode with its symbol is shown in Fig. 5.6(a).

+

+

–

–

+

+

–

–

+

+

–

–

+

+

–

–

W Holes

Electrons –

+ V

As the capacitance is inversely proportional to the distance between the plates (CT 1/W), the transition capacitance CT varies inversely with the reverse voltage as shown in Fig. 5.6(b). Consequently, an increase in reverse bias voltage will result in an increase in the depletion region width and a subsequent decrease in transition capacitance CT. At zero volt, the varactor depletion region W is small and the capacitance is large at approximately 600 pF. When the reverse bias voltage across the varactor is 15 V, the capacitance is 30 pF.

A

K (a)

CT (pF)

Reverse –15 bias, V

–10 (b)

The varactor diodes are used in FM radio and TV receivers, AFC circuits, self adjusting bridge circuits and adjustable bandpass filters. With improvement in the type of materials used and construction, varactor diodes find application in tuning of LC resonant circuit in microwave frequency multipliers and in very low noise microwave parametric amplifiers.

–5

0

A Step recovery diode, also known as snap-off varactor, is a silicon or gallium arsenide PN junction diode with a construction similar to that of varactor diode. It is an epitaxial diffused junction diode having a graded doping profile, where doping density decreases near the junction as shown in Fig. 5.7, designed to store charge, when it is conducting under forward bias. At low frequencies, it works as an ordinary diode, conducting in the forward direction but not in the reverse direction, i.e. it recovers immediately from the ON state to the OFF state. However, when a high frequency signal (above a few mega Hertz) is applied the diode does not recover immediately. Even during the negative half cycle of the input signal, it keeps conducting for a while, after which the reverse current ceases abruptly in one step. This reverse conduction for a brief period is due to the fact that charges stored in the depletion region under forward bias condition take time to drain away from the junction. Hence, the diode very briefly discharges this stored energy in the form of a sharp pulse under reverse bias condition as shown in Fig. 5.8. The step or sudden recovery from reverse current ON to reverse current OFF, gives the diode its name. Doping density

P

O N

Step recovery diode

vin

vo

10 MHz t

+

t

vo

–

T

T

The sharp pulse in the reverse direction is very rich in harmonics. The duration of this pulse is 100 to 1000 ps. A tuned circuit connected at the output operated at the wanted harmonic will give a frequency multiplication depending upon the harmonic, that is selected.

It consists of N-type germanium or silicon wafer about 1.25 mm square by 0.5 mm thick, one face of which is soldered to a metallic base, by radio frequency heating, so that an external ohmic contact can be made. The point contact is made simply by pressing a tungsten or phosphor bronze wire of a few micro meter diameter, called Cat’s whisker, against the exposed surface of the crystal. The contact area may be much smaller than the area of Phosphor bronze Si wafer the wire. After the whisker is in place, (or) Tungston the whole assembly is encapsulated in a ceramic or glass envelope to give it mechanical strength. A typical diode structure is shown in Fig. 5.9. The S shaped bend in the whisker gives it mechanical stability and also springlike property for maintaining good electrical contact. To form the rectifying junction at the contact point, electrical forming process is used which consists of passing Ceramic or Glass envelope a large current pulse of 100–200 mA amplitude and of 1–100 ms duration, while the crystal face with wire point is kept positive. The heat so produced drives away some of the electrons from the atoms in the small region around the point of contact thereby leaving holes behind. This small region of N-type material is converted to P-type material as shown in Fig. 5.10. The small area of the PN junction results in very low junction capacitance (0.1 to 1pF) that makes it suitable for operation at frequencies as high as 10 GHz or more and for applications in pulse circuits.

Metal–semiconductor junctions are very common in all semiconductor devices and have very high importance. Depending upon the doping concentration, materials, and the characteristics of the

Band to allow for heat expansion Cat’s whisker P

N

interface, the metal–semiconductor junctions can act as either an ohmic contact or as a Schottky barrier. An analysis of metal–semiconductor junction is presented in this section.

A metal–semiconductor junction, as the name indicates, consists of a metal in contact with a piece of semiconductor. The structure of a typical metal–semiconductor junction is shown in Fig. 5.11. The active junction is the interface between the metal, which acts as an anode, and the semiconductor. The other interface between the semiconductor and the metal, which acts as a cathode, is an Ohmic contact and there is no potential drop at this junction.

The energy band diagram helps in identifying the barrier between the metal and the semiconductor. In order to understand the energy band structure at a metal–semiconductor junction, first let us consider the energy bands in metal and semiconductors separately, as shown in Fig. 5.12(a). The energy bands are aligned at the same vacuum level. When the metal and semiconductor are brought together, the Fermi levels do align themselves at thermal equilibrium. The condition that exists just before the thermal equilibrium is reached is depicted in Fig. 5.12(b). Let us define, FB, the barrier height as the potential difference between the Fermi level of the metal and the band edge where the majority carriers exist. For an N-type semiconductor, the barrier height is given by the difference between the metal work function (FM) and the electron affinity (c). FBN = FM – c

(5.1)

The work function, FM varies depending upon surface preparation. For P-type semiconductor, the barrier height is given by the difference between the valence band level and the Fermi level in the metal,

Evacuum

Metal

Semiconductor

Evacuum

Metal

qc

Semiconductor

qc EC EF

q FM

q FB

Ei

EFM

EC EF

q FM

Ei

EFM Ev (a)

Ev (b)

Eg FBP = c + ___ q – FM

(5.2)

where Eg is the energy gap between the conduction and valence bands. The sum of the barrier heights on N-type and P-type substrate is expected to be equal to the energy gap, Eg i.e., (FBN + FBP) q = Eg. In a metal-semiconductor junction, a barrier is formed if the Fermi level of the metal is somewhere between the valence and conduction band edges of the semiconductor, as shown in Fig. 5.12(b). Let us also define a built-in potential (F1) as the difference between the Fermi level of the metal and the Fermi level of the semiconductor, For an N-type semiconductor, the barrier height is given by FBN = FM – c EC – EF EC – EF FIN = FBN – _______ = FM – c – _______ q q

(5.3)

For a P-type semiconductor, the Fermi level is closer to the valence band and the built-in potential is given by EF – EV FIP = c + _______ – FM (5.4) q The Fermi level in an N-type semiconductor is given by NC EF = EC – kT ln ___ ND

(5.5)

and the Fermi level in a P-type semiconductor is given by NV EF = EV + kT ln ___ NA

(5.6)

Substitution Eq. (5.5) and Eq. (5.6) in Eq. (5.3) and Eq. (5.4), respectively, would give expressions for built in potentials in terms of the barrier height and doping concentration, as follows.

and

EC – EF NC kT ___ FIN = FBN – _______ = FBN – ___ q q ln ND for N-type semiconductor

(5.7)

EF – EV NV kT ___ FIP = FBP – _______ = FBP – ___ q q ln NA for P-type semiconductor

(5.8)

After the metal and semiconductor have been brought into contact, electrons start to flow from the semiconductor into the metal, and as a result, a depletion region of width xd, with uncompensated donors (positive charge) is formed. Electrons continue to flow into the metal until the Fermi energy levels of metal and semiconductor align with each other. In metal, the electron current forms a negative surface charge layer. This results in an electric field and the band edges are lowered in the semiconductor (Fig. 5.13). E

q Fi

q FB EFM

EC EF

– +++++ – – – – – –

Ei Ev

xd

Metal

Semiconductor

Table 5.1 gives the work function (FM) and electron affinity (c) of some commonly used metals and semiconductors.

Element

Work function, FM (V)

Aluminium, Al

4.28

Silver, Ag

4.26

Gold, Au

5.1

Chromium, Cr

4.5

Nickel, Ni

5.15

Platinum, Pt

5.65

Titanium, Ti

4.33 Table Contd.

Table Contd.

Tungsten, W

4.55 Electron affinity, c (Volt)

Silicon, Si

4.01

Germanium, Ge

4.13

Gallium Arsenide, GaAs

4.07

A metal–semiconductor junction is made of silver and silicon with ND = 4 ¥ 1017 cm–3. Calculate the barrier height and the built-in potential.

Solution The work function (FM) and electron affinity (c) for silver and silicon are 4.26 V and 4.01 V, respectively (from Table 5.1). The barrier height for N-type material, from Eq. (5.1), is given by FBN = FM – c = 4.26 – 4.01 = 0.25 V The built-in potential is given by Eq. (5.7) i.e., NC 1.38 × 10–23 × 300 _________ 2.8 × 1025 kT ___ ________________ FIN = FBN – ___ q ln ND = 0.25 – 1.602 × 10–19 ln 4 × 1017 = 0.47 V (The density of state at conduction band edge, NC = 2.8 ¥ 1025 from Table 4.1) When an external bias is applied, the metal-to-semiconductor barrier remains unchanged, whereas, the semiconductor-to-metal barrier is either decreased (forward bias) or increased (reverse bias). When the metal is connected to a positive bias with respect to the semiconductor. The Fermi energy level of the metal is lowered from its equilibrium level. The depletion region is narrowed, and the potential barrier in the semiconductor is reduced. The number of electrons that diffuse from semiconductor to metal is now more than the number of electrons that drift from metal into the semiconductor. Thus, there will be a positive current through the device. Figure 5.14 illustrates a metal–semiconductor junction under forward-bias condition. If the metal is connected to a negative bias with respect to the semiconductor, the metal is charged even more negatively than without any bias. The Fermi energy level of the metal is raised. The electrons in the semiconductor are repelled even

E

q FB

q( Fi – Va)

qVa

EC EF Ei Ev

Metal

Semiconductor

more. The depletion region becomes wider and the potential barrier on semiconductor side is further increased, as shown in Fig. 5.15. However, the barrier on the metal side remains unchanged and limits the flow of electrons. A small current flows as a result of a few electrons in the metal acquiring enough thermal energy to overcome barrier.

E

q FB q( Fi – Va) qVa EC EF

Schottky barrier diode is an extension of the oldEi est semiconductor device that is the point contact diode. Here, the metal–semiconductor interface is Ev a surface, the Schottky barrier rather than a point contact. The Schottky diode is formed when a metal, such as Aluminum, is brought into contact Metal Semiconductor with a moderately doped N-type semiconductor as shown in Fig. 5.16. It is a unipolar device because it has electrons as majority carriers on both sides Metal of the junction. Hence, there is no depletion layer formed near the junction. It shares the advantage + – N type of point contact diode in that there is no significant (a) (b) current from the metal to the semiconductor with reverse bias. Thus, the delay present in the junction diodes due to hole–electron recombination time is absent here. Hence, because of the large contact area between the metal and semiconductor than in the point contact diode, the forward resistance is lower, and so is noise. The forward current is dominated by electron flow from semiconductor to metal, and the reverse current is mainly due to electron flow from metal to semiconductor. As there is very little minority carrier injection from semiconductor into metal, Schottky diodes are also said to be majority carrier devices. The diode is also referred to as hot carrier diode because when it is forward biased, conduction of electrons on the N side gains sufficient energy to cross the junction and enter the metal. Since these electrons plunge Current into the metal with large energy, they are commonly called as hot carriers. Figure 5.17 shows the V-I characteristics of a Schottky diode and a PN junction diode. The current in a PN junction diode is controlled by the diffusion of minority carriers whereas the current in the Schottky diode results from the flow of majority carriers over the potential barrier at the metal-semiconductor junction. The reverse saturation current for a Schottky diode is larger than that of a PN junction diode. The storage time for a Schottky diode is theoretically zero. The Schottky diode has a smaller turn-on voltage and shorter switching time than the PN junction diode.

Schottky barrier diode

0

PN junction diode

Vg (SB ) Vg (PN )

Voltage

Schottky diode can be used for rectification of signals of frequencies even exceeding 300 MHz. It is commonly used in switching power supplies at frequencies of 20 GHz. Its low noise figure finds application in sensitive communication receivers like radars. It is also used in clipping and clamping circuits and in computer gating.

An Ohmic contact is another type of metal–semiconductor junction. It is formed by applying a metal to a heavily doped semiconductor. Here the current is conducted equally in both directions and there will be a very little voltage drop across the junction. The usage of Ohmic contacts is to connect one semiconductor device to another on an IC, or to connect an IC to its external terminals. Ohmic contacts are very common in semiconductor devices. Metal–semiconductor contacts cannot be considered to offer a resistance as low as that of two metals connected to each other. Metal– semiconductor junctions can act as either a rectifying junction or an Ohmic contact depending upon the Fermi energy levels of the metal and the E semiconductor used. A proper choice of metal q( Fs – c) and semiconductor can offer a low resistance Ohmic contact. Alternatively, contacts that EC have a thin barrier can be created by heavily EFM EF + – – doping the semiconductor through which the + – q(c – FM) – + carriers can tunnel. Both these types of contacts are presented in this section. A metal–semiconductor junction can be an Ohmic contact if the Schottky barrier height, FB, is zero or negative. This means, for an N-type semiconductor, that the metal work function, FM, is either close to or smaller than the electron affinity (c) of the semiconductor; and for a P-type semiconductor, the metal work function is either close to or greater than the sum of electron affinity and the bandgap energy.

Ev

xd

Metal

That is,

FM £ c for an N-type semiconductor

or,

FM ≥ c + Eg for a P-type semiconductor

Figure 5.18 illustrates the energy band diagram when QM is less than the electron affinity, c. In this case, the electrons flow from the metal into the semiconductor thus forming a positive surface charge layer in metal. The resultant electric field sets up an electric potential and the energy bands of the semiconductor bend downward. There is no barrier for the flow of electrons in both directions. The current is directly proportional to the potential across the junction and is symmetric about the origin, as shown in Fig. 5.19. A more practical method of providing contacts in semiconductor devices is to create a junction that consists of a thin barrier. Such contacts are also

Semiconductor

I

V

referred to as tunnel contacts. Such contacts have a positive barrier at the junction and a heavy doping in the semiconductor. This creates a very thin barrier separating the metal from the semiconductor, through which the carriers can easily tunnel. Figure 5.20 shows the energy band in a heavily doped Ohmic contact.

The Tunnel or Esaki diode is a thin-junction diode which exhibits negative resistance under low forward bias conditions. An ordinary PN junction diode has an impurity concentration of about 1 part in 108. With this amount of doping, the width of the depletion layer is of the order of 5 microns. This potential barrier restrains the flow of carriers from the majority carrier side to the minority carrier side. If the concentration of impurity atoms is greatly increased to the level of 1 part in 103, the device characteristics are completely changed. The width of the junction barrier varies inversely as the square root of the impurity concentration and therefore, is reduced from 5 microns to less than 100 Å (10–8 m). This thickness is only about 1/50th of the wavelength of visible light. For such thin potential energy barriers, the electrons will penetrate through the junction rather than surmounting them. This quantum mechanical behavior is referred to as tunneling and hence, these high-impurity-density PN junction devices are called tunnel diodes.

E

EC EF N + region EV

distance Metal

+

N

N-semiconductor

The V–I characteristic for a typical germanium tunnel diode is shown in Fig. 5.21. It is seen that at first forward current rises sharply as applied voltage is increased, where it would have risen slowly for an ordinary PN junction diode (which is shown as dashed line for comparison). Also, reverse current is much larger for comparable back bias than in other diodes due to the thinness of the junction. The interesting portion of the characteristic starts at the point A on the curve, i.e. the peak voltage. As the forward bias is increased beyond this point, the forward current drops and continues to drop until point B is reached. This is the valley voltage. At B, the current starts to increase once again and does so very rapidly as bias is increased further. Beyond this point, characteristic resembles that of an ordinary diode. Apart from the peak voltage and valley voltage, the other two parameters normally used to specify the diode behaviour are the peak current and the peak-to-valley current ratio, which are 2 mA and 10 respectively, as shown. The V–I characteristic of the tunnel diode illustrates that it exhibits dynamic resistance between A and B. Figure 5.22 shows energy level diagrams of the tunnel diode for three interesting bias levels. The shaded areas show the energy states occupied by electrons in the valence band, whereas the cross hatched regions represent energy states in the conduction band occupied by the electrons. The levels to which the energy states are occupied by electrons on either side of the junctions are shown by dotted lines. When the bias is zero, these lines are at the same height. Unless energy is imparted to the electrons from some external source, the energy possessed by the electrons on the N–side of the junction is insufficient to permit to climb over the junction barrier to reach the P-side. However, quantum mechanics show that there is a finite probability for the electrons to tunnel through the junction to reach the other

2 mA

I

A

Negative resistance

Tunnel diode

B

0.2 mA –v O

50 mV

300 mV

Ordinary diode

–I

side, provided there are allowed empty energy states in the P-side of the junction at the same energy level. Hence, the forward current is zero. When a small forward bias is applied to the junction, the energy level of the P-side is lower as compared with the N-side. As shown in Fig. 5.22(b), electrons in the conduction band of the N-side see empty energy level on the P-side. Hence, tunneling from N-side to P-side takes place. Tunneling in other directions is not possible because the valence band electrons on the P-side are now opposite to the forbidden energy gap on the N-side. The energy band diagram shown in Fig. 5.22(b), is for the peak of the diode characteristic. When the forward bias is raised beyond this point, tunneling will decrease as shown in Fig. 5.22(c). The energy of the P-side is now depressed further, with the result that fewer conduction band electrons on the N-side are opposite to the unoccupied P-side energy levels. As the bias is raised, forward current drops. This corresponds to the negative resistance region of the diode characteristic. As forward bias is raised still further, tunneling stops altogether and it behaves as a normal PN junction diode.

The equivalent circuit of the tunnel diode when biased in the negative resistance region is as shown in Fig. 5.23(a). In the circuit, Rs is the series resistance and Ls is the series inductance which may be ignored except at highest frequencies. The resulting diode equivalent circuit is thus reduced to parallel

Electrons in conduction band Empty energy level

Electrons in valance band

N

N

P (a) Zero bias voltage

N

P (b) Peak voltage

P (c) Valley voltage

combination of the junction capacitance Cj and the negative resistance –Rn. Typical values of the circuit components are Rs = 6 W, Ls = 0.1 nH, Cj = 0.6 pF and Rn = 75 W. Ls

1. Tunnel diode is used as an ultra-high speed switch with switching speed of the order of ns or ps 2. As logic memory storage device 3. As microwave oscillator 4. In relaxation oscillator circuit 5. As an amplifier 1. 2. 3. 4.

Cj

Low noise Ease of operation High speed Low power

1. Voltage range over which it can be operated is 1 V less 2. Being a two terminal device, there is no isolation between the input and output circuit.

Rs

–Rn

In 1963, Gunn discovered the transferred electron effect which is now commonly referred to as Gunn effect. This effect is effectively utilised in the Gunn diode for generation of microwave oscillations. It was the first instance of useful semiconductor device operation depending on the bulk properties of a material. Gunn effect is exhibited by semiconductor materials like gallium arsenide, indium phosphide, cadmium telluride and indium arsenide. The structure of a practical Gunn diode is shown in Fig. 5.24. Anode Gold wire

Gold alloy contacts

N + Substrate

15 mm

5 mm

Active N layer

Heat sink

Cathode

If a relatively small d.c. voltage is applied across a thin slice of gallium arsenide, with thickness of the order of tens of micrometers, so that the voltage gradient across the slice is in excess of about 3300 V/cm, then negative resistance will manifest itself. Gunn effect is a bulk property of semiconductors and does not depend on other semiconductor properties like junction or contact properties. The energy band diagram of gallium arsenide is shown in Fig. 5.25. The conduction band has two valleys, lower and upper valley. The mobility of electrons in the lower valley is greater than the mobility of electrons in the upper valley. The energy level difference (DE) between the upper valley and lower valley is smaller than the energy difference (Eg) between the conduction and valence bands. When the applied voltage across the thin slice of N-type gallium arsenide is increased, the electrons move with greater velocity in step with the applied voltage and the current increases linearly with the voltage. When the voltage is increased beyond a certain level, so that the electric field is greater than the threshold electric field in the slice, electrons are transferred from the high mobility lower valley to the low mobility higher valley. As a result, the flow of electrons actually slows down so that the current decreases with increase in voltage as shown in Fig. 5.26, thereby exhibiting negative resistance.

Upper valley Lower valley

Conduction band DE = 0.36 eV

Ec

Forbidden band

Eg = 1.43 eV

Ev

Valence band

I

Original bulk resistance ITH

Negative resistance

Ultimate bulk resistance

Iv

O

VTH

Vv

V

The extent of doping will not be completely uniform throughout the sample of gallium arsenide. Hence, there is a possibility somewhere near the negative end where the impurity concentration is less than the average. Such an area has a fewer free electrons than in other areas, thereby having lesser conductivity. As a result, there will be greater than average potential across it. Thus, as the applied voltage across it

is increased, this region will be the first to have a voltage across it large enough to induce transfer of electrons to the higher valley. Such a region is commonly referred to as negative-resistance domain. The domain is normally unstable and it moves across the slice, towards the positive end with the same average velocity as the electrons before and after it (about 107 cm/s). This domain corresponds to a negative pulse of voltage and when it arrives at the positive end of the slices a pulse is received by the associated tank circuit and triggers oscillations in it. The sample is fairly short, such that once a domain forms, insufficient potential is left across the rest of the slice to permit another domain to form. The thickness of the slice and the applied voltage are such that one domain or pulse is formed per cycle of RF oscillations, so that energy is received by the tank circuit in correct phase to permit the oscillations to continue. The negative resistance property of the Gunn diode can be utilised for microwave generation and amplification.

IMPATT diode stands for IMPact Avalanche and Transit Time diode. Any device that exhibits dynamic negative resistance for direct current will also exhibit it for alternate current. When alternating voltage is applied, current will rise when voltage falls. Hence, negative resistance may be redefined as that property of the device which causes the current through it to be 180° out of phase with the voltage across it. IMPATT diode utilises a combination of delay involved in generating Avalanche current multiplication, together with the delay due to transit time through a drift space to provide the necessary 180° phase difference between applied voltage and the resulting current. The cross section of the active region of this device is shown in Fig. 5.27. From the figure, it should be noted that it is a diode, the junction being between the P+ and N layers. 2 mm 3 mm

Anode

P

+

10 mm

N

Avalanche region

N Junction

+

Cathode Drift region

–

+

d.c. applied + RF voltage

V

d.c. voltage (avalanche threshold)

90°

90°

t

(a) Applied DC and RF voltage

Current pulse

An extremely high voltage gradient of the order of 400 kV/ cm is applied to the IMPATT diode, eventually resulting in a very high current. The IMPATT diode is constructed to withstand such conditions repeatedly. Under such high potential gradient, applied in the reverse direction, results in flow of minority carriers across the junction. If it is assumed that oscillations exist, the effect of a positive swing of RF voltage superimposed on top of the high d.c. voltage should be considered. Electron and hole velocity now become so high, so that they form additional holes and electrons by knocking them out of the crystal structure by a process knows as impact ionization.

Current pulse maximum when V = 0

Current pulse at cathode when V = –Vm

These additional carriers continue the process at the Current drifts to junction and turns out into cathode an Avalanche. If the original d.c. field was just at the threshold of producing this Avalanche, then during the t whole of the positive RF (b) Resulting current pulse and its drift cycle, Avalanche multiplication will take place. As Avalanche is a multiplication process, the process takes a time, such that the resulting current pulse maximum at the junction, occurs at the instant when the RF voltage across the diode is zero and going negative, as shown in Fig. 5.28. Thus, a 90° phase difference between the voltage and current has been established. Because of the reverse bias that is applied, the current pulse flows to the cathode at a drift velocity dependent on the magnitude of the high d.c. field. The time taken by the pulse to reach the cathode depends on this velocity and on the thickness of the highly doped (N+) layer. The thickness of the drift region is selected so that the time taken for the current pulse to arrive at the cathode corresponds to a further 90° phase difference. Thus, as shown in Fig. 5.28, when current pulse actually arrives at the cathode terminal the RF voltage there is at its negative peak. As a result, voltage and current in the IMPATT diode is 180° out of phase, and a dynamic RF negative resistance has been proved to exist. Such a negative resistance finds extensive use in oscillators of amplifiers. Because of the short transit time involved they can be operated in the microwave frequency region.

IMPATT diodes are the most powerful CW solid state microwave power sources. A typical, commercial IMPATT diode for use below about 50 GHz is shown in Fig. 5.29. Copper cathode seal

Gold wire N

3 mm

+

Ceramic

N + P

Gold alloy contact Copper anode (to external heat sink)

It is composed of three regions. In addition to the usual N and P regions, an intrinsic layer (I region) is sandwiched between them, to form the PIN structure as shown in Fig. 5.30. Being intrinsic, the intermediate layer offers relatively high resistance which gives it two advantages compared to an ordinary PN diode. They are (1) decrease in capacitance between P and N regions as it is inversely proportional to the separation between these regions. It allows a faster response time for the diode. Hence, PIN diodes are used at high P I N frequencies (more than 300 MHz). (2) possibility of greater electric field between the P and N junctions, so that the charge carriers drift towards their majority carrier side. This enhances faster response of the diode. It offers a variable resistance under forward bias condition as shown in Fig. 5.31. Forward resistance offered is given by rac μ 50/I, where I is the d.c. current in mA. 100

RF (W )

10

0 1

10 IF (mA)

100

Hence, for large d.c. currents, the diode will look like a short. In reverse biased condition it looks like an open, i.e. it offers an infinite resistance. It is used as a switching diode for signal frequencies up to GHz range and as an AM modulator of very high frequency signals.

It is used for the detection of light at the receiving end in Optical communication. It is a three-region reverse biased junction diode. A layer of intrinsic silicon is sand-witched between heavily doped P and N type semiconductor materials. As shown in Fig. 5.32, the depletion region extends almost to the entire intrinsic layer where most of the absorption of light photons take place. The width of the intrinsic layer is large compared to the width of the other two layers. This ensures large absorption of light photons in the depletion region which also forms the absorption region. Light photons incident on the PIN photodiode are absorbed in the absorption region which leads to the generation of electron–hole pairs. These charge carriers present in the depletion region drift under the influence of the existing electric field that is set up due to the applied reverse bias. The reverse current flowing in the external circuit increases linearly with the level of illumination. hf

E field

P

l

Depletion region

Absorption region N+

Load

As the process of drifting is quicker than diffusion, the transit time of the charge carriers is small so that the response time is considerably reduced. The large width of the depletion region results in achieving high quantum efficiency.

APD is used in Optical communication for detection of light at the receiving end. It converts the input light signal into electrical signal. The structure of an APD is shown in Fig. 5.33. It essentially consists of reverse biased PN junction. The depletion region in this reverse biased PN junction is formed by immobile positively charged donor atoms in the N-type semiconductor material and immobile negatively

charged acceptor atoms in the P-type material. The electric field in this depletion region is very high where most of the photons are absorbed and primary charge carriers (electron–hole pair) are generated. These charge carriers acquire sufficient energy from the electric field to excite new electron-hole pairs by a process known as impact ionisation. These new carriers created by impact ionisation can themselves produce additional carriers by the same mechanism. For this process, APD requires a high reverse bias voltage in the order of 100–400 V. Carrier multiplication factors as great as 104 may be obtained using defect free materials. Electron-hole pairs thus generated separate and drift under the influence of the electric field in the depletion region and diffuse outside the depletion region so that they are finally collected in the detector terminals. This leads to a flow of current in the external circuit whose magnitude is proportional to the intensity of light incident on APD. E field

N P

Gain region

i Absorption region

P

+

Load

Due to the internal gain mechanism in an APD, a large electrical response is obtained even for a weak input light signal. Quantum efficiency closer to 100% in the working region can be obtained.

Similar to LED, Lasers are used to convert the electrical signal to light signal. In direct band gap materials where high recombination velocities exist, optical gain can be achieved by creating population inversion of carriers through high-level current injection and by forming a resonant cavity. This cavity is usually produced by the high Fresnel reflectivity obtained from cleaving the material along faces perpendicular to the junction plane. The structure and characteristics of a typical laser diode is shown in Fig. 5.34. In this diode, opposite ends of the junction are polished to get mirror like surfaces. When free electrons recombine with holes, the emitted photons reflect back and forth between the mirror surfaces. The region between the mirrored ends acts like a cavity that filters the light and purifies it colour. As the photons bounce back and forth, they induce an Avalanche effect that causes all newly created photons to be emitted with the same phase. One of the mirror surfaces is semitransparent. From this surface a fine thread like

beam of photons emerge out. All the photons of laser light have same frequency and phase and hence coherent. Output light power

P Light N

Input current

It has a well defined current threshold as seen from the power output vs. drive current characteristic. Below this threshold the device exhibits low levels of spontaneous emission. At the limiting current density, stimulated emission occurs and the emitted radiation increases linearly with drive current.

A Bipolar Junction Transistor (BJT) is a three terminal semiconductor device in which the operation depends on the interaction of both majority and minority carriers and hence the name Bipolar. The BJT is analogous to a vacuum triode and is comparatively smaller in size. It is used in amplifier and oscillator circuits, and as a switch in digital circuits. It has wide applications in computers, satellites and other modern communication systems.

The BJT consists of a silicon (or germanium) crystal in which a thin layer of N-type Silicon is sandwiched between two layers of P-type silicon. This transistor is referred to as PNP. Alternatively, in a NPN transistor, a layer of P-type material is sandwiched between two layers of N-type material. The two types of the BJT are represented in Fig. 6.1. The symbolic representation of the two types of the BJT is shown in Fig. 6.2. The three portions of the transistor are Emitter, Base and Collector, shown as E, B and C, respectively. The arrow on the emitter specifies the direction of current flow when the EB junction is forward biased. Emitter is heavily doped so that it can inject a large number of charge carriers into the base. Base is lightly doped and very thin. It passes most of the injected charge carriers from the emitter into the collector. Collector is moderately doped.

As shown in Fig. 6.3, usually the emitter-base junction is forward biased and collector-base junction is reverse biased. Due to the forward bias on the emitter-base junction an emitter current flows through

E E

C

C B

(a)

B

(b)

the base into the collector. Though the, collector-base junction is reverse biased, almost the entire emitter current flows through the collector circuit.

As shown in Fig. 6.4, the forward bias applied to the emitter base junction of an NPN transistor causes a lot of electrons from the emitter region to crossover to the base region. As the base is lightly doped with P-type impurity, the number of holes in the base region is very small and hence the number of electrons that combine with holes in the P-type base region is also very small. Hence a few electrons combine with holes to constitute a base current IB. The remaining electrons (more than 95%) crossover into the collector region to constitute a collector current IC. Thus the base and collector current summed up gives the emitter current, i.e. IE = – (IC + IB). In the external circuit of the NPN bipolar junction transistor, the magnitudes of the emitter current IE, the base current IB and the collector current IC are related by IE = IC + IB.

As shown in Fig. 6.5, the forward bias applied to the emitter-base junction of a PNP transistor causes a lot of holes from the emitter region to crossover to the base region as the base is lightly doped with N-types impurity. The number of electrons in the base region is very small and hence the number of holes combined with electrons in the N-type base region is also very small. Hence a few holes combined with electrons to constitute a base current IB. The remaining holes (more than 95%) crossover into the collector region to constitute a collector current IC. Thus the collector and base current when summed up gives the emitter current, i.e. IE = – (IC + IB). In the external circuit of the PNP bipolar junction transistor, the magnitudes of the emitter current IE, the base current IB and the collector current IC are related by IE = IC + IB

(6.1)

This equation gives the fundamental relationship between the currents in a bipolar transistor circuit. Also, this fundamental equation shows that there are current amplification factors and in common base transistor configuration and common emitter transistor configuration respectively for the static (d.c.) currents, and for small changes in the currents. The large signal current gain of a common base transistor is defined as the ratio of the negative of the collector-current increment to the emitter-current change from cut-off (IE = 0) to IE, i.e. (IC – ICBO) (6.2) = – __________ IE – 0 where ICBO (or ICO) is the reverse saturation current flowing through the reverse biased collector-base junction, i.e. the collector to base leakage current with emitter open. As the magnitude of ICBO is negligible when compared to IE, the above expression can be written as IC = __ IE

(6.3)

Since IC and IE are flowing in opposite directions, is always positive. Typical value of ranges from 0.90 to 0.995. Also, is not a constant but varies with emitter current IE, collector voltage VCB and temperature. In the active region of the transistor, the emitter is forward biased and the collector is reverse biased. The generalised expression for collector current IC for collector junction voltage VC and emitter current IE is given by IC = –

IE + ICBO (1 – eVc/VT)

(6.4)

If VC is negative and |Vc | is very large compared with VT , then the above equation reduces to IC = – a IE + ICBO

(6.5)

If VC, i.e. VCB, is few volts, IC is independent of VC. Hence the collector current IC is determined only by the fraction a of the current IE flowing in the emitter. From Eqn. (6.5), We have IC = – a IE + ICBO Since IC and IE are flowing in opposite directions, IE = – (IC + IB) IC = – a [– (IC + IB)] + ICBO

Therefore,

IC – a IC = a IB + ICBO IC (1– a) = a IB + ICBO ICBO a IC = _____ IB + _____ 1–a 1–a a b = _____ , 1–a

Since

(6.6)

the above expression becomes IC = (1 + b) ICBO + b IB

(6.7)

In the common-emitter (CE) transistor circuit, IB is the input current and IC is the output current. If the base circuit is open, i.e, IB = 0, then a small collector current flows from the collector to emitter. This is denoted as ICEO, the collector-emitter current with base open. This current ICEO is also called the collector to emitter leakage current. In this CE configuration of the transistor, the emitter-base junction is forward-biased and collectorbase junction is reverse-biased and hence the collector current IC is the sum of the part of the emitter current IE that reaches the collector, and the collector-emitter leakage current ICEO. Therefore, the part of IE, which reaches collector is equal to (IC – ICEO). Hence, the large-signal current gain (b) is defined as,

From the equation, we have

(IC – ICEO) b = __________ IB

(6.8)

I = bIB + ICEO

(6.9)

Comparing Eqs. (6.7) and (6.9), we get the relationship between the leakage currents of transistor common-base (CB) and common-emitter (CE) configurations as ICEO = (1 + b) ICBO

(6.10)

From this equation, it is evident that the collector-emitter leakage current (ICEO) in CE configuration is (1 + b) times larger than that in CB configuration. As ICBO is temperature-dependent, ICEO varies by large amount when temperature of the junctions changes.

IE = IC + IB Substituting Eqn. (6.7) in the above equation, we get IE = (1 + b) ICBO + (1 + b) IB

(6.11)

Substituting Eqn. (6.6) into Eqn. (6.11), we have 1 1 IE = _____ ICBO + _____ IB 1–a 1–a

(6.12) IC

to the base current IB. That is, IC bd.c. = hFE = __ IB

(6.13)

As IC is large compared with ICEO, the large signal current gain (b) and the d.c. current gain (hFE) are approximately equal.

When a transistor is to be connected in a circuit, one terminal is used as an input terminal, the other terminal is used as an output terminal and the third terminal is common to the input and output. Depending upon the input, output and common terminal, a transistor can be connected in three configurations. They are: (i) Common base (CB) configuration, (ii) Common emitter (CE) configuration, and (iii) Common collector (CC) configuration. This is also called grounded base configuration. In this configuration, emitter is the input terminal, collector is the output terminal and base is the common terminal. This is also called grounded emitter configuration. In this configuration, base is the input terminal, collector is the output terminal and emitter is the common terminal. This is also called grounded collector configuration. In this configuration, base is the input terminal, emitter is the output terminal and collector is the common terminal. The supply voltage connections for normal operation of an NPN transistor in the three configurations are shown in Fig. 6.6.

The circuit diagram for determining the static characteristics curves of an NPN transistor in the common base configuration is shown in Fig. 6.7. To determine the input characteristics, the collector-base voltage VCB is kept constant at zero volt and the emitter current IE is increased from zero in suitable equal steps by increasing VEB. This is repeated for higher fixed values of VCB. A curve is drawn between emitter current IE and emitter-base voltage VEB at constant collector-base voltage VCB. The input characteristics thus obtained are shown in Fig. 6.8.

IC

IB

C

B

IE IE

+ –

E

IC

C

IB

E + –

E

B

– +

IE

+ –

IB

(a)

IC

(c)

IE

– VEE

V

+

A VEB

+

– +

C + –

(b)

– –

B

IC C

E +

IC –

A

B IB

VCB

+ + V –

+ V – cc

IE (mA) VCB > 1 V VCB = 0 V

3.5 3 2.5 2 1.5 1 0.5 0.1 0.2 0.3 0.4 0.5 0.6

0.7 0.8 VEB (V)

When VCB is equal to zero and the emitter-base junction is forward biased as shown in the characteristics, the junction behaves as a forward biased diode so that emitter current IE increases rapidly with small increase in emitter-base voltage VEB. When VCB is increased keeping VEB constant, the width of the base region will decrease. This effect results in an increase of IE. Therefore, the curves shift towards the left as VCB is increased.

To determine the output characteristics, the emitter current IE is kept constant at a suitable value by adjusting the emitter-base voltage VEB. Then VCB is increased in suitable equal steps and the collector current IC is noted for each value of IE. This is repeated for different fixed values of IE. Now the curves of IC versus VCB are plotted for constant values of IE and the output characteristics thus obtained is shown in Fig. 6.9. IC (mA) Saturation region

Active region

IE = 5 mA

5 4 mA 4 3 mA 3 2 mA 2

1 mA

1

0 mA 1

–0.25

2

3

4

5

VCB (V )

Cut off region 0

From the characteristics, it is seen that for a constant value of IE, IC is independent of VCB and the curves are parallel to the axis of VCB. Further, IC flows even when VCB is equal to zero. As the emitterbase junction is forward biased, the majority carriers, i.e. electrons, from the emitter are injected into the base region. Due to the action of the internal potential barrier at the reverse biased collector-base junction, they flow to the collector region and give rise to IC even when VCB is equal to zero. As the collector voltage VCC is made to increase the reverse bias, the space charge width between collector and base tends to increase, with the result that the effective width of the base decreases. This dependency of base-width on collector-to-emitter voltage is known as the Early effect. This decrease in effective base-width has three consequences: (i) There is less chance for recombination within the base region. Hence, increases with increasing |VCB|. (ii) The charge gradient is increased within the base, and consequently, the current of minority carriers injected across the emitter junction increases. (iii) For extremely large voltages, the effective base-width may be reduced to zero, causing voltage breakdown in the transistor. This phenomenon is called the punch through. For higher values of VCB, due to Early effect, the value of increases. For example, changes, say from 0.98 to 0.985. Hence, there is a very small positive slope in the CB output characteristics and hence the output resistance is not zero. The slope of the CB characteristics will give the following four transistor parameters. Since these parameters have different dimensions, they are commonly known as common base hybrid parameters or h-parameters.

It is defined as the ratio of the change in (input) emitter voltage to the change in (input) emitter current with the (output) collector voltage VCB kept constant. Therefore, DVEB hib = _____, VCB constant (6.14) DIE It is the slope of CB input characteristics IE versus VEB as shown in Fig. 6.8. The typical value of hib ranges from 20 W to 50 W. It is defined as the ratio of change in the (output) collector current to the corresponding change in the (output) collector voltage with the (input) emitter current IE kept constant. Therefore, DIC hob = _____, IE constant (6.15) DVCB It is the slope of CB output characteristics IC versus VCB as shown in Fig. 6.9. The typical value of this parameter is of the order of 0.1 to 10 m mhos. to the corresponding change in the (input) emitter current keeping the (output) collector voltage VCB constant. Hence, DIC hfb = ____ , VCB constant. (6.16) DIE It is the slope of IC versus IE curve. Its typical value varies from 0.9 to 1.0. It is defined as the ratio of the change in the (input) emitter voltage and the corresponding change in (output) collector voltage with constant (input) emitter current, IE. Hence, DVEB hrb = _____ , IE constant (6.17) DVCB It is the slope of VEB versus VCB curve. Its typical value is of the order of 10 – 5 to 10 – 4.

To determine the input characteristics, the collector to emitter voltage is kept constant at zero volt and base current is increased from zero in equal steps by increasing VBE in the circuit shown in Fig. 6.10.

The value of VBE is noted for each setting of IB. This procedure is repeated for higher fixed values of VCE, and the curves of IB Vs. VBE are drawn. The input characteristics thus obtained are shown in Fig. 6.11.

IB (mA)

When VCE = 0, the emitter-base junction is forward biased and the junction behaves as a forward biased diode. Hence the input characteristic for VCE = 0 is similar to that of a forward-biased diode. When VCE is increased, the width of the depletion region at the reverse biased collectorbase junction will increase. Hence the effective width of the base will decrease. This effect causes a decrease in the base current IB. Hence, to get the same value of Ib as that for VCE = 0, VBE should be increased. Therefore, the curve shifts to the right as VCE increases.

150

250

VCE = 0V VCE > 0 V

200

100 50 0

0.2

0.4

0.6

0.8

VBE(V)

To determine the output characteristics, the base current IB is kept constant at a suitable value by adjusting base-emitter voltage, VBE. The magnitude of collector-emitter voltage VCE is increased in suitable equal steps from zero and the collector current IC is noted for each setting VCE. Now the curves of IC versus VCE are plotted for different constant values of IB. The output characteristics thus obtained are shown in Fig. 6.12. From Eqs. (6.6) and (6.7), we have a b = _____ 1–a

and IC = ( I + b) ICBO + b IB

For larger values of VCE, due to Early effect, a very small change in a is reflected in a very large change in b. For exam0.98 0.985 ple, when a = 0.98, b = _______ = 49. If a increases to 0.985, then b = ________ = 66. Here, a slight 1 – 0.98 1 – 0.985 increase in a by about 0.5% results in an increases in b by about 34%. Hence, the output characteristics of CE configuration show a larger slope when compared with CB configuration. The output characteristics have three regions, namely, saturation region, cut-off region and active region. The region of curves to the left of the line OA is called the saturation region (hatched), and the line OA is called the saturation line. In this region, both junctions are forward biased and an increase in the base current does not cause a corresponding large change in IC. The ratio of VCE(sat) to IC in this region is called saturation resistance. The region below the curve for IB = 0 is called the cut-off region (hatched). In this region, both junctions are reverse biased. When the operating point for the transistor enters the cut-off region, the transistor

is OFF. Hence, the collector current becomes almost zero and the collector voltage almost equals VCC, the collector supply voltage. The transistor is virtually an open circuit between collector and emitter. The central region where the curves are uniform in spacing and slope is called the active region (unhatched). In this region, emitter-base junction is forward biased and the collector-base junction is reverse biased. If the transistor is to be used as a linear amplifier, it should be operated in the active region. If the base current is subsequently driven large and positive, the transistor switches into the saturation region via the active region, which is traversed at a rate that is dependent on factors such as gain and frequency response. In this ON condition, large collector current flows and collector voltage falls to a very low value, called VCEsat, typically around 0.2 V for a silicon transistor. The transistor is virtually a short circuit in this state. High speed switching circuits are designed in such a way that transistors are not allowed to saturate, thus reducing switching times between ON and OFF times. The slope of the CE characteristics will give the following four transistor parameters. Since these parameters have different dimensions, they are commonly known as common emitter hybrid parameters or h-parameters. It is defined as the ratio of the change in (input) base voltage to the change in (input) base current with the (output) collector voltage VCE kept constant. Therefore, DVBE hie = _____, VCE constant (6.18) DIB It is the slope of CE input characteristics IB versus VBE as shown in Fig. 6.11. The typical value of hie ranges from 500 to 2000 W. It is defined as the ratio of change in the (output) collector current to the corresponding change in the (output) collector voltage with the (input) base current IB kept constant. Therefore, DIC hoe = _____ , IB constant (6.19) DVCE It is the slope of CE output characteristic IC versus VCE as shown in Fig. 6.12. The typical value of this parameter is of the order of 0.1 to 10 m mhos. It is defined as a ratio of the change in the (output) collector current to the corresponding change in the (input) base current keeping the (output) collector voltage VCE constant. Hence, DIC hfe = ____, VCE constant (6.20) DIB It is the slope of IC versus IB curve. Its typical value varies from 20 to 200. It is defined as the ratio of the change in the (input) base voltage and the corresponding change in (output) collector voltage with constant (input) base current, IB. Hence, DVBE hre = _____ , IB constant (6.21) DVCE It is the slope of VBE versus VCE curve. Its typical value is of the order of 10–5 to 10–4.

The circuit diagram for determining the static characteristics of an NPN transistor in the common collector configuration is shown in Fig. 6.13.

To determine the input characteristics, VEC is kept at a suitable fixed value. The base-collector voltage VBC is increased in equal steps and the corresponding increase in IB is noted. This is repeated for different fixed values of VEC. Plots of VBC versus IB for different values of VEC shown in Fig. 6.14 are the input characteristics.

The output characteristics shown in Fig. 6.15 are the same as those of the common emitter configuration.

Property

CB

CE

CC

Input resistance

Low (about 100 W)

Moderate (about 750 W)

High (about 750 kW)

Output resistance

High (about 450 kW)

Moderate (about 45 kW)

Low (about 25 W)

Current gain

1

High

High

Voltage gain

About 150

About 500

Less than 1

Phase shift between input & output voltages

0 or 360°

180°

0 or 360°

Applications

for high frequency circuits

for audio frequency circuits for impedance matching

In a transistor amplifier with a.c. input signal, the ratio of change in output current to the change in input current is known as the current amplification factor. DIC In the CB configuration the current amplification factor, a = ____ (6.22) DIE DIC In the CE configuration the current amplification factor, b = ____ DIB

(6.23)

DIE In the CC configuration the current amplification factor, g = ____ DIB

(6.24)

D IE = D IC + D IB By definition,

D IC = a D IE

Therefore,

D IE = a D IE + D IB

i.e.

D IB = D IE (1 – a)

Dividing both sides by D IC, we get DIB ____ DIE ____ = (1 – a) DIC DIC Therefore,

Rearranging, we also get

1 __ 1 __ = (1 – a) b a a b = ______ (1 – a) b 1 __ 1 a = ______ , or __ a–b=1 (1 + b)

(6.25)

From this relationship, it is clear that as

approaches unity,

approaches infinity. The CE configura-

tion is used for almost all transistor applications because of its high current gain, . In the CC transistor amplifier circuit, IB is the input current and IE is the output current. From Eq. (6.22), Substituting

IE = ____ IB IB = IE – IC, we get IE = _________ IE – IC

Dividing the numerator and denominator on RHS by IE, we get IE ____ IE 1 = _________ = _____ I I 1 – C E ____ – ____ IE IE Therefore,

1 = _____ = ( + 1) 1–

(6.26)

A load resistor RL is connected in series with the collector supply voltage VCC of CB transistor configuration as shown in Fig. 6.16. A small change in the input voltage between emitter and base, say Vi, causes a relatively larger change in emitter current, say IE. A fraction of this change in current is collected and passed through RL and is denoted by symbol . Therefore the corresponding change in voltage across the load resistor RL due to this current is V0 = RL IE. V0 Here, the voltage amplification Av = ____ is greater than unity and Vi thus the transistor acts as an amplifier.

C IC RL

IE + Vi –

E B

–

IB

+

We know from the characteristics of CE configuration, the current amplification factor is and

IC = (1 + ) ICBO + IB

The above equation can be expressed as IC – ICBO = ICBO + IB

VCC

_____, 1–

IC – ICBO = ___________ IB – (– ICBO)

Therefore,

The output characteristics of CE configuration show that in the cut-off region, the values IE = 0, IC = ICBO and IB = – ICBO. Therefore, the above equation gives the ratio of the collector-current increment to the base-current change from cut-off to IB, and hence is called the large-signal current gain of common-emitter transistor. The d.c. current gain of the transistor is given by d.c.

IC __ IB

hFE

Based on this hFE value, we can determine whether the transistor is in saturation or not. For any transis. tor, in general, IB is large compared to ICBO. Under this condition, the value of hFE The small-signal CE forward short-circuit gain is defined as the ratio of a collector-current increment IC for a small base-current change IB, at a fixed collector-to-emitter voltage VCE.

|

IC ___ IB VCE

i.e. If

is independent of currents, then

(ICBO + IB) ___. By using IB

= hfe and

=

hFE. However,

is a function of current, then

=

+

hFE. Therefore, the above equation becomes

hFE hfe = _________________ hFE 1 – (ICBO + IB) ____ IC In Fig. 6.17, the hFE versus IC shows a maximum and hence hfe > hFE for smaller currents, and hfe < hFE for larger currents. Therefore, the above equation is valid only for the active region.

In a common-base transistor circuit, the emitter current IE is 10 mA and the collector current IC is 9.8 mA. Find the value of the base current IB.

Solution

Given IE = 10 mA and IC = 9.8 mA

We know that emitter current is IE = IB + IC i.e.

10 = IB + 9.8

Therefore,

IB = 0.2 mA

In a common-base connection, the emitter current IE is 6.28 mA and the collector current IC is 6.20 mA. Determine the common-base d.c. current gain.

Solution

Given

IE = 6.28 mA and IC = 6.20 mA

We know that common-base d.c. current gain, IC 6.20 × 10 –3 a = __ = __________ = 0.987 IE 6.28 × 10 –3 The common-base d.c. current gain of a transistor is 0.967. If the emitter current is 10 mA, what is the value of base current?

Solution

Given

a = 0.967 and IE = 10 mA

The common-base d.c. current gain (a) is IC IC a = 0.967 = __ = ___ IE 10 Therefore,

IC = 0.967 ¥ 10 = 9.67 mA

The emitter current

IE = IB + IC

i.e.

10 = IB + 9.67

Therefore,

IB = 0.33 mA

The transistor has IE = 10 mA and

Solution

Given

= 0.98. Determine the values of IC and IB.

IE = 10 mA and a = 0.98

IC The common-base d.c. current gain, a = __ IE IC 0.98 = ___ 10 IC = 0.98 ¥ 10 = 9.8 mA

i.e. Therefore The emitter current

IE = IB + IC

i.e.

10 = IB + 9.8

Therefore,

IB = 0.2 mA

If a transistor has a

Solution

= 200, find the value of .

a 0.97 a = 0.97, b = _____ = _______ = 32.33 1 – a 1 – 0.97

If

b 200 b = 200, a = _____ = _______ = 0.995 b + 1 200 + 1

If

A transistor has

Solution

of 0.97, find the value of . If

= 100. If the collector current is 40 mA, find the value of emitter current.

Given

b = 100 and IC = 40 mA IC 40 b = 100 = __ = ___ IB IB

Therefore,

IB = 40/100 = 0.4 mA and IE = IB + IC = (0.4 + 40) ¥ 10 – 3 = 40.4 mA

A transistor has

Solution

= 150. Find the collector and base currents, if IE = 10 mA.

Given

b = 150 and IE = 10 mA

b 150 The common-base current gain, a = _____ = _______ = 0.993 b + 1 150 +1 Also,

IC a = __ IE

IC 0.993 = ___ 10

i.e. Therefore,

IC = 0.993 ¥ 10 = 9.93 mA

The emitter current

IE = IB + IC 10 ¥ 10 – 3 = IB + 9.93 ¥ 10 – 3

i.e.

IB = (10 – 9.93) ¥ 10 – 3 = 0.07 mA

Therefore,

Determine the values of IB and IE for the transistor circuit if IC = 80 mA and

Solution

b = 170 and IC = 80 mA

Given

IC 80 × 10–3 b = 170 = __ = ________ IB IB

We know that (b),

80 × 10 – 3 IB = _________ = 0.47 mA 170 IE = IB + IC = (0.47 + 80) mA = 80.47 mA

Therefore, and

Determine the values of IC and IE for the transistor circuit of

Solution

= 170.

Given

Therefore,

= 200 and IB = 0.125 mA.

IB = 0.125 mA and b = 200 IC IC b = 200 = __ = ___________ IB 0.125 × 10 – 3

Therefore,

IC = 200 ¥ 0.125 ¥ 10 – 3 = 25 mA

and

IE = IB + IC = (0.125 + 25) ¥ 10 – 3 = 25.125 mA

Determine the values of IC and IB for the transistor circuit of IE = 12 mA and

Solution

Given

= 100.

IE = 12 mA and b = 100

We know that base current,

IE 12 × 10 – 3 IB = _____ = _________ = 0.1188 mA 1 + 100 1+b

and collector current,

IC = IE – IB = (12 – 0.1188) ¥ 10 – 3 = 11.8812 mA

A transistor has IB = 100 A and IC = 2 A. Find (a) of the transistor, (b) of the transistor, (c) emitter current IE, (d) if IB changes by + 25 A and IC changes by + 0.6 mA, find the new value of .

Solution

Given

(a) To find

of the transistor

IB = 100 A = 100

10 – 6 A and IC = 2 mA = 2

10 – 3 A.

IC 2 × 10 – 3 = __ = __________ = 20 IB 100 × 10 – 6 (b) To find

of the transistor 20 = _____ = ______ = 0.952 + 1 1 + 20

(c) To find emitter current, IE IE = IB + IC = 100 = (0.01 + 2) (d) To find the new value of Therefore,

10 – 6 + 2

10 – 3 = 2.01

10 – 3 A 10 – 3 A = 2.01 mA

when IB = 25 A and IC = 0.6 mA IB = (100 + 25) A = 125 A IC = (2 + 0.6) mA = 2.6 mA

New value of

of the transistor, IC 2.6 × 10 – 3 = __ = __________ = 20.8 IB 125 × 10 – 6

For a transistor circuit having

Solution

Given

= 0.98, ICBO = ICO = 5 A and IB = 100 A, find IC and IE.

= 0.98, ICBO = ICO = 5 A and IB = 100 A

The collector current is ICO IB 0.98 × 100 × 10 – 6 5 × 10 – 6 IC = _____ + _____ = _______________ + _______ = 5.15 mA 1– 1– 1 – 0.98 1 – 0.98 The emitter current is IE = IB + IC = 100

10 – 6 + 5.15

10 – 3 = 5.25 mA

A germanium transistor used in a complementary symmetry amplifier has ICBO = 10 A at 27°C and hFE = 50. (a) Find IC when IB = 0.25 mA and (b) assuming hFE does not increase with temperature, find the value of new collector current, if the transistor’s temperature rises to 50°C.

Solution

Given

ICBO = 10 A and hFE (= ) = 50

(a) To find the value of collector current when IB = 0.25 mA IC =

IB + (1 + ) ICBO

= 50

(0.25

10 – 3) + (1 + 50)

(10

10– 6) A = 13.01 mA

(b) To find the value of new collector current if temperature rises to 50°C We know that ICBO doubles for every 10°C rise in temperature. Therefore, I ¢CBO (b = 50) = ICBO × 2 (T2 – T1)/10 = 10 ¥ 2(50 – 27)/10 mA = 10 ¥ 22.3 mA = 49.2 mA Therefore, the collector current at 50°C is IC = b ◊ IB + (1 + b) I ¢CBO = 50 ¥ (0.25 ¥ 10 – 3) + (1 + 50) ¥ 49.2 ¥ 10 – 6 A = 15.01 mA

When the emitter current of a transistor is changed by 1 mA, there is a change in collector current by 0.99 mA. Find the current gain of the transistor.

Solution

DIC 0.99 × 10 – 3 The current gain of the transistor is a = ____ = __________ = 0.99 DIE 1 × 10 – 3

The d.c. current gain of a transistor in CE mode is 100. Determine its d.c. current gain in CB mode.

Solution

bd.c. The d.c. current gain of the transistor in CB mode is ad.c. = _______ 1 + bd.c. 100 = _______ = 0.99 1 + 100

When IE of a transistor is changed by 1 mA, its IC changes by 0.995 mA. Find its common base current gain , and common-emitter current gain .

Solution

DIC 0.995 × 10 – 3 Common-base current gain is a = ____ = ___________ = 0.995 DIE 1 × 10 – 3 a 0.995 b = _____ = ________ = 199 1 – a 1 – 0.995

Common-emitter current gain is

The current gain of a transistor in CE mode is 49. Calculate its common-base current gain. Find the base current when the emitter current is 3 mA.

Solution

Given

We know that

b = 49 b a = _____ 1+b

49 Therefore, the common-base current gain is a = ______ = 0.98 1 + 49 IC We also know that a = __ IE Therefore,

IC = aIE = 0.98 ¥ 3 ¥ 10 – 3 = 2.94 mA

Determine IC, IE and

Solution

for a transistor circuit having IB = 15 A and

The collector current,

= 150.

IC = bIB = 150 ¥ 15 ¥ 10 – 6 = 2.25 mA

The emitter current,

IE = IC + IB = 2.25 ¥ 10 – 3 + 15 ¥ 10 – 6 = 2.265 mA

Common-base current gain,

b 150 a = _____ = ____ = 0.9934 1 + b 151

Determine the base, collector and emitter currents and VCE for a CE circuit shown in Fig. 6.18. For VCC = 10 V, VBB = 4 V, RB = 200 k , RC = 2 k , VBE (on) = 0.7 V, = 200.

Solution

Referring to Fig. 6.18, the base current is VBB – VBE (on) 4 – 0.7 IB = _____________ = _________3 = 16.5 mA RB 200 × 10

The collector current is IC = bIB = 200 ¥ 16.5 ¥ 10 – 6 = 3.3 mA The emitter current is IE = IC + IB = 3.3 ¥ 10 – 3 + 16.5 ¥ 10 – 6 = 3.3165 mA Therefore,

VCE = VCC – ICRC = 10 – 3.3 ¥ 10 – 3 ¥ 2 ¥ 103 = 3.4 V

Calculate the values of IC and IE for a transistor with 20 A.

d.c.

= 0.99 and ICBO = 5 A. IB is measured as

Solution

Given ad.c. = 0.99, ICBO = 5 mA and IB = 20 mA ICBO ad.c.IB 0.99 × 20 × 10 – 6 5 × 10 – 6 IC = _______ + _______ = _______________ + ________ = 2.48 mA 1 – ad.c. 1 – ad.c. 1 – 0.99 1 – 0.99 IE = IB + IC = 20 ¥ 10 – 6 + 2.48 ¥ 10 – 3 = 2.5 mA

Therefore,

The reverse leakage current of the transistor when connected in CB configuration is 0.2 A and it is 18 A when the same transistor is connected in CE configuration. Calculate d.c. and d.c. of the transistor.

Solution

The leakage current ICBO = 0.2 mA ICEO = 18 mA

Assume that

IB = 30 mA IE = IB + IC IC = IE – IB = bIB + (1 + b) ICBO

We know that

ICBO ICEO = _____ = (1 + b)ICBO 1–a ICEO 18 b = ____ – 1 = ___ – 1 = 89 ICBO 0.2 Ic = bIB + (1 + b)ICBO = 89 (30 ¥ 10– 3) + (1 + 89) (0.2 ¥ 10– 6)

ad.c.

= 2.67 A ICBO 0.2 × 10 – 6 = 1 – ____ = 1 – _________ = 0.988 ICEO 18 × 10 – 6

IC – ICBO bd.c. = ________ IB – ICEO 2.67 – 0.2 × 10 – 6 = ___________________ = 89 30 × 10 – 3 – 18 × 10 – 6

If

d.c.

= 0.99 and ICBO = 50 A, find emitter current.

Solution Assume that

Given

ad.c. = 0.99 and ICBO = 50 mA, IB = 1 mA ICBO ad.c. IB 0.99 (1 × 10 – 3) 50 × 10 – 6 IC = _______ + _______ = _____________ + _________ 1 – ad.c. 1 – ad.c. 1 – 0.99 1 – 0.99

0.99 × 10 – 3 50 × 10 – 6 = __________ + _________ = 99 mA + 5 mA = 104 mA 0.01 0.01 IE = IC + IB = 104 mA + 1 mA = 105 mA

For the CE amplifier circuit shown in Fig. 6.19, find the percentage change in collector current if the transistor with hfc = 50 is replaced by another transistor with hfc = 150. Assume VBE = 0.6.

Solution

R2 5 × 103 VB = _______ × VCC = ________________ × 12 = 2 V R1 + R2 5 × 103 + 25 × 103

+ 12 V

VE = VB – VBE = 2 – 0.6 = 1.4 V VE 1.4 IE = ___ = ____ = 14 mA RE 100 IE 14 × 10 – 3 b = 50, IB = _____ = _________ = 274.5 mA 51 1+b

Here, For Therefore, For Therefore,

R1 25 kW

RC 1 kW

R2 5 kW

RE 100 W

IC1 = bIB = 50 × 274.5 × 10 – 6 = 13.725 mA IE 14 × 10 – 3 b = 150, IB = ______ = _________ = 92.715 mA 151 1+b IC2 = bIB = 150 × 92.715 × 10 – 6 = 13.907 mA

Hence, the percentage change in collector current is calculated as IC2 – ICE 13.907 × 10 – 3 – 13.725 × 10 ________ × 100 = ________________________ × 100 = 1.326% IC1 13.725 × 10 – 3

Given an NPN transistor for which = 0.98, ICO = 2 A and ICEO = 16 A. A common emitter connection is used as shown in Fig. 6.20 with VCC = 12 V and RC = 4 k . What is the minimum base current required in order that transistor enter into saturation region.

Solution

Given a = 0.98, ICO = 2 mA, ICEO = 1.6 mA, VCC = 12 V and RC = 4 kW VCC 12 IC(sat) = ____ = _______3 = 3 mA RC 4 × 10 a 0.98 b = _____ = _______ = 49 1 – a 1 – 0.98

RC

4 kW

RB VBB

+ IB –

IB(min) 3 × 10 – 3 = ________ = 61.224 × 10 – 6 = 61.224 mA 49

12 V

+ VCC –

IC(sat) = _____ b

A transistor operating in CB configuration has IC = 2.98 mA, IE = 3 mA and ICO = 0.01 mA . What current will flow in the collector circuit of this transistor when connected in CE configuration with a base current of 30 A?

Solution Given

IC = 2.98 mA, IE = 3 mA, ICO = 0.01 mA and IB = 30 mA.

For CB configuration,

IC = aIE + ICO

Therefore,

IC – ICO (2.98 – 0.01) × 10 – 3 a = _______ = _________________ = 0.99 IE 3 × 10–3 a 0.99 b = _____ = _______ = 99 1 – a 1 – 0.99

For CE configuration,

IC = bIB + (1 + b) ICO = 99 × 30 × 10 – 6 + (1 + 99) × 0.01 × 10 – 3 = 3.97 mA.

There is a possibility of voltage breakdown in the transistor at high voltages even though the rated dissipation of the transistor is not exceeded. Therefore, there is an upper limit to the maximum allowable collector junction voltage. There are two types of breakdown, namely, Avalanche multiplication or Avalanche breakdown and reach-through or punch-through.

When a diode is reverse biased, there is a limit on the voltage that can be applied which is the Avalanche voltage. Similarly, in the transistor, the maximum reverse biasing voltage which may be applied before breakdown between the collector and base terminals with the emitter open is called breakdown voltage BVCBO. Therefore, an upper limit is set on the collector voltage VCB by avalanche breakdown in the reverse biased collector–base junction. Fields of order 106 V/m are required in the depletion layer for breakdown to occur, which usually limits VCB to a maximum of several tens of volts. Breakdown may occur because of Avalanche multiplication of the current ICO that crosses the collector junction. As a result of this multiplication, the current becomes MICO, where M is the Avalanche multiplication factor. At the breakdown voltage BVCBO, multiplication factor M becomes infinite and the current rises abruptly in the breakdown region, as shown in Fig. 6.21, there will be large changes in current with small changes in applied voltage. The Avalanche multiplication factor depends on the voltage VCB between collector and base, which has been found to be given empirically by 1 M = ____________n V CB 1 – ______ BVCBO

(

)

(6.27)

where the empirical constant, n, depends on the lattice material and the carrier type, which is usually in the range of about 2 to 10; for N-type silicon n ª 4 and for P-type n ª 2, and controls the sharpness of the onset breakdown. Taking Avalanche multiplication into account, IC has the magnitude M a IE, where a is the common base current gain. As a result, in the presence of Avalanche multiplication, the current gain of CB transistor has become Mm. As the effective current gain exceeds unity, the emitter circuit may then display negative resistance effects, which can lead to undesirable instabilities. IC

IB2 IB = 0 IB1

BVCEO

BVCBO

VCE

For the CE configuration, the collector to emitter breakdown voltage BVCEO with base open is ____

÷

1 BVCEO = BVCBO n ___ (6.28) hFE In general, BVCEO is 40–50% of BVCBO. This is the upper limit of VCE that can be placed across the transistor without damaging it.

According to Early effect, the width of the collector-junction transition region increases with increased collector-junction voltage. As the voltage applied across the junction VCB increases the transition region penetrates deeper into the base and will have spread completely across the base to reach the emitter junction, as the base is very thin. Thus, the collector voltage has reached through the base region. This effect, known as reach-through, also affects the output characteristics of a transistor since IC versus VCB curves are no longer horizontal but take on a positive slope indicating that the device has a finite output impedance that is voltage depen-dent. Since the input characteristics are also affected, the input impedance is also influenced by VCB. It is possible to raise the punch-through voltage by increasing the doping concentration in the base, but this automatically reduces the emitter efficiency. Punch-through takes place at a fixed voltage between collector and base and is not dependent on circuit configuration, whereas Avalanche multiplication takes place at different voltages depending upon the circuit configuration. Therefore, the voltage limit of a particular transistor is determined by either of the two types of breakdown, whichever occurs at lower voltage.

The general expression for collector current IC of a transistor for any voltage across collector junction VC and emitter current IE is

(

VC ___

IC = – aNIE – ICO e VT – 1

)

(6.29)

where aN is the current gain in normal operation and ICO is the collector junction reverse saturation current. In inverted mode of operation, the above equation can be written as

(

VE ___

IE = – aIIC – IEO e VT – 1

)

(6.30)

where aI is the inverted common-base current gain and IEO is the emitter junction reverse saturation current. The above four parameters are related by the condition aIICO = aNIEO

(6.31)

For many transistors IEO lies in the range 0.5 ICO to ICO . Figure 6.22 shows the Ebers–Moll model for a PNP transistor. Here, two separate ideal diodes are connected back to back with saturation currents – IEO and – ICO and there are two dependent currentcontrolled current sources shunting the ideal diodes. The current sources account for the minority carrier transport across the base. An application of Kirchoff’s current law to the collector node of Fig. 6.22 gives

(

VC ___

IC = – aNIE + I = – aNIE + IO e VT – 1

)

(6.32)

where I is the diode current. As IO is the magnitude of reverse saturation current, then IO = – ICO. Substituting this value of IO in Eqn. (6.32), we get

(

VC ___

IC = – aNIE – ICO e VT – 1

)

which is nothing but the general expression for collector current of a transistor given in Eqn. (6.29). Hence, this model is valid for both forward and reverse static voltages applied across the transistor junctions. Here, base spreading resistance has been omitted and the difference between ICBO and ICO have been neglected. The dependent current sources may be removed from the Fig. 6.22, provided aN = aI = 0. If the basewidth is made much larger than the diffusion length of minority carriers in the base, all minority carriers will recombine in the base and no minority carrier will be available to reach the collector. Therefore, the transistor amplification factor a will become zero. As a result, transistor action ceases. Hence, it is not possible to construct a transistor by simply placing two isolated diodes back to back.

The quiescent operating point of a transistor amplifier should be established in the active region of its characteristics. Since the transistor parameters such as b, ICO and VBE are functions of temperature, the operating point shifts with changes in temperature. The stability of different methods of biasing transistor (BJT, FET and MOSFET) circuits and compensation techniques for stabilizing the operating point are discussed in this chapter.

In order to produce distortion-free output in amplifier circuits, the supply voltages and resistances in the circuit must be suitably chosen. These voltages and resistances establish a set of d.c. voltage VCEQ and current ICQ to operate the transistor in the active region. These voltages and currents are called quiescent values which determine the operating point or Q-point for the transistor. The process of giving proper supply voltages and resistances for obtaining the desired Q-point is called biasing. The circuits used for getting the desired and proper operating point are known as biasing circuits. The collector current for common-emitter amplifier is expressed by IC = bIB + ICEO = bIB + (1 + b )ICO Here the three variables hFE, i.e., b, IB and ICO are found to increase with temperature. For every 10°C rise in temperature, ICO doubles itself. When ICO increases, IC increases significantly. This causes power dissipation to increase and hence to make ICO increase. This will cause IC to increase further and the process becomes cumulative which will lead to thermal runaway that will destroy the transistor. In addition, the quiescent operating point can shift due to temperature changes and the transistor can be driven into the region of saturation. The effect of b on the Q-point is shown in Fig. 6.23. One more source of bias instability to be considered is due to the variation of VBE with temperature.VBE is about 0.6 V for a silicon transistor and 0.2 V for a germanium transistor at room temperature. As the temperature increases, |VBE | decreases at the rate of 2.5 mV/°C for both silicon and germanium transistors. The transfer characteristic curve shifts to the left at the rate of 2.5 mV/°C (at constant IC) for increasing temperature and hence the operating point shifts accordingly. To establish the operating point in the active region, compensation techniques are needed. Referring to the biasing circuit of Fig. 6.24(a), the values of VCC and RC are fixed and IC and VCE are dependent on RB. Applying Kirchhoff’s voltage law to the collector circuit in Fig. 6.24(a), we get VCC = IC RC + VCE.

The straight line represented by AB in Fig. 6.24(b) is called the d.c. load line. The coordinates of the VCC end point A are obtained by substituting VCE = 0 in the above equation. Then IC = ____. Therefore, the RC VCC ____ . coordinates of A are VCE = 0 and IC = RC IC

IB4 IB3

VCC Rc

IB2 Q2 Q1 IB1

VCC

IB = 0 VCE

IC 3.5 mA

C

3 mA

A

+VCC

IC RB CC

RC

CC

Q

1.5 mA

Vout RL

Vin

D 0 (a)

12 V

B 21 V 24 V (b)

VCE

The coordinates of B are obtained by substituting IC = 0 in the above equation. Then VCE = VCC. Therefore, the coordinates of B are VCE = VCC and IC = 0. Thus, the d.c. load line AB can be drawn if the values of RC and VCC are known. As shown in Fig. 6.24(b), the optimum Q-point is located at the midpoint of the d.c. load line AB between the saturation and cut-off regions, i.e. Q is exactly midway between A and B. In order to get faithful amplification, the Q-point must be well within the active region of the transistor.

Even though the Q-point is fixed properly, it is very important to ensure that the operating point remains stable where it is originally fixed. If the Q-point shifts nearer to either A or B, the output voltage and current get clipped, thereby output signal is distorted. In practice, the Q-point tends to shift its position due to any or all of the following three main factors: (i) Reverse saturation current, ICO, which doubles for every 10 °C increase in temperature. (ii) Base-emitter voltage, VBE, which decreases by 2.5 mV per °C. (iii) Transistor current gain, b, i.e., hFE which increases with temperature. Referring to Fig. 6.24(a), the base current IB is kept constant since IB is approximately equal to VCC /RB. If the transistor is replaced by another one of the same type, one cannot ensure that the new transistor will have identical parameters as that of the first one. Parameters such as b vary over a range. This results in the variation of collector current IC for a given IB. Hence, in the output characteristics, the spacing between the curves might increase or decrease which leads to the shifting of the Q-point to a location which might be completely unsatisfactory. After drawing the d.c. load line, the operating point Q is properly located at the center of the d.c. load line. This operating point is chosen under zero input signal condition of the circuit. Hence, the a.c. load line should also pass through the operating point Q. The effective a.c. load resistance, Ra.c., is the combination of RC parallel to RL, i.e. Ra.c. = RC || RL. So the slope of the a.c. load line 1 CQD will be – ____ . Ra.c.

(

)

To draw an a.c. load line, two end points, viz. maximum VCE and maximum IC when the signal is applied are required. Maximum VCE = VCEQ + ICQ Ra.c., which locates the point D (0D) on the VCE axis. VCEQ Maximum IC = ICQ + _____, which locates the point C (0C ) on the IC axis. Ra.c. By joining points C and D, a.c. load line CD is constructed. As RC > Ra.c., the d.c. load line is less steep than the a.c. load line. When the signal is zero, we have the exact d.c. conditions. From Fig. 6.24(b), it is clear that the intersection of d.c. and a.c. load lines is the operating point Q.

In the transistor amplifier shown in Fig. 6.24(a), RC = 8 k , RL = 24 k and VCC = 24 V. Draw the d.c. load line and determine the optimum operating point. Also draw the a.c. load line.

Solution (i) d.c. load line: Referring to Fig. 6.24(a), we have VCC = VCE + IC RC. For drawing d.c. load line, the two end points, viz. maximum VCE point (at IC = 0) and maximum IC point (at VCE = 0) are required. Maximum

VCE = VCC = 24 V

VCC 24 Maximum IC = ____ = _______3 = 3 mA RC 8 × 10 Therefore, the d.c. load line AB is drawn with the point B (0B = 24 V) on the VCE axis and the point A (0A = 3 mA) on the IC axis, as shown in Fig. 6.24(b). (ii) For fixing the optimum operating point Q, mark the middle of the d.c. load line AB and the corresponding VCE and IC values can be found. Here,

VCC VCEQ = ____ = 12 V 2

and ICQ = 1.5 mA

(iii) a.c. load line: To draw an a.c. load line, two end points viz. maximum VCE and maximum IC when the signal is applied are required. The a.c. load, Maximum

8 × 24 Ra.c. = RC || RL = ______ = 6 kW 8 + 24 VCE = VCEQ + ICQ Ra.c. = 12 + 1.5 ¥ 10–3 ¥ 6 ¥ 103 = 21 V

This locates the point D (0D = 21 V) on the VCE axis. VCEQ Maximum collector current = ICQ + _____ Ra.c. 12 = 1.5 ¥ 10 – 3 + _______3 = 3.5 mA 6 × 10 This locates the point C (0C = 3.5 mA) on the IC axis. By joining points C and D, a.c. load line CD is constructed.

For the transistor amplifier shown in Fig. 6.25(a), VCC = 12 V, R1 = 8 k , R2 = 4 k , RC = 1 k , RE = 1 k and RL = 1.5 k . Assume VBE = 0.7 V. (i) Draw the d.c. load line, (ii) determine the operating point, and (iii) draw the a.c. load line.

Solution (i) d.c. load line: Referring to Fig. 6.25(a), we have VCC = VCE + IC (RC + RE ). To draw the d.c. load line, we need two end points, viz. maximum VCE point (at IC = 0) and maximum IC point (at VCE = 0). Maximum VCE = VCC = 12 V, which locates the point B (0B = 12 V) of the d.c. load line. Maximum

VCC 12 IC = ________ = ___________3 = 6 mA RC + RE (1 +1) × 10

This locates the point A (0A = 6 mA) of the d.c. load line. Figure 6.25(b) shows the d.c. load line AB, with (12 V, 6 mA).

IC (mA) D 12.3

+VCC (12 V)

8k

1k

R1

RC A 6

IC

IB

(5.4, 3.3)

Q 4k

R2

RE

1k

CE

C 7.38 VCE (V )

0

(a)

B 12

(b)

(ii) Operating point Q The voltage across

R2 R2 is V2 = _______ VCC R1 + R2 4 × 103 V2 = ________3 × 12 = 4 V 12 × 10

Therefore,

V2 = VBE + IERE V2 – VBE 4 – 0.7 IE = ________ = _______3 = 3.3 mA RE 1 × 10

Therefore, IC

IE = 3.3 mA VCE = VCC – IC (RC + RE)

= 12 – 3.3 10 – 3 2 103 = 5.4 V Therefore, the operating point Q is at 5.4 V and 3.3 mA, which is shown on the d.c. load line. (iii) a.c. load line To draw the a.c. load line, we need two end points, viz. maximum VCE and maximum IC when signal is applied. 1 × 1.5 a.c. load, Ra.c = RC || RL = _______ = 0.6 k 2.5 Therefore, maximum

VCE = VCEQ + ICQ Ra.c. = 5.4 + 3.3

10 – 3

0.6

103 = 7.38 V

This locates the point C (0C = 6.24 V) on the VCE axis. Maximum

VCEQ IC = ICQ + _____ Ra.c.

5.4 = 3.3 ¥ 10 – 3 + ________3 = 12.3 mA 0.6 × 10 This locates the point D (0D = 12.3 mA) on the IC axis. By joining points C and D, a.c. load line CD is constructed.

Design the circuit shown in Fig. 6.26, given Q-point values are to be ICQ = 1 mA and VCEQ = 6 V. Assume that VCC = 10 V, = 100 and VBE (on) = 0.7 V.

Solution

The collector resistance is VCC

VCC – VCEQ 10 – 6 RC = ___________ = _______ = 4 kW ICQ 1 × 10–3 The base current is

RB

ICQ 1 × 10–3 IBQ = ____ = _______ = 10 mA 100 b The base resistance is VCC – VBE (on) 10 – 0.7 RB = _____________ = _________ = 0.93 MW IBQ 10 × 10 – 6

Vi

Determine the characteristics of a circuit shown in Fig. 6.27. Assume that

Solution

Referring to Fig. 6.27, Kirchhoff’s voltage law equation is VBB = IBRB + VBE (on) + IERE

We know that IE = IB + IC = IB + bIB = (1 + b )IB VBB – VBE (on) The base current IB = ______________ RB + (1 + b) RE 5 – 0.7 = __________________ = 53.34 mA 20 × 103 + 101× 600 Therefore,

IC = bIB = 100 ¥ 53.34 ¥ 10–6 = 5.334 mA IE = IC + IB = 5.334 ¥ 10 – 3 + 53.34 ¥ 10 – 6 = 5.38734 mA

= 100 and VBE (on) = 0.7 V.

RC

VCE = VCC – ICRC – IE RE = 10 – 5.334 ¥ 10 – 3 ¥ 400 – 5.38734 ¥ 10 – 3 ¥ 600 = 4.634 V The Q point is at VCEQ = 4.634 V and ICQ = 5.334 mA

The collector current for the CE circuit of Fig. 6.24 is given by IC = bIB + (1 + b) ICO. The three variables in the equation, b, IB and ICO increase with rise in temperature. In particular, the reverse saturation current or leakage current ICO changes greatly with temperature. Specifically, it doubles for every 10 °C rise in temperature. The collector current IC causes the collector–base junction temperature to rise which, in turn, increase ICO, as a result IC will increase still further, which will further rise the temperature at the collector–base junction. This process will become cumulative leading to “thermal runaway.” Consequently, the ratings of the transistor are exceeded which may destroy the transistor itself. The collector is normally made larger in size than the emitter in order to help dissipate the heat developed at the collector junction. However, if the circuit is designed such that the base current IB is made to decrease automatically with rise in temperature, then the decrease in b IB will compensate for the increase in (1 + b)ICO, keeping IC almost constant. In power transistors, the heat developed at the collector junction may be removed by the use of heat sink, which is a metal sheet fitted to the collector and whose surface radiates heat quickly.

The extent to which the collector current IC is stabilised with varying ICO is measured by a stability factor S. It is defined as the rate of change of collector current IC with respect to the collector–base leakage current ICO, keeping both the current IB and the current gain b constant ∂IC dIC DIC S = _____ ª _____ ª _____, b and IB constant ∂ICO dICO DICO

(6.33)

The collector current for a CE amplifier is given by IC = b IB + (b + 1)ICO

(6.34)

Differentiating the above equation with respect to IC, we get dICO dIB 1 = b ____ + (b + 1) _____ dIC dIC Therefore,

(

(b + 1) dIB 1 – b ____ = ______ S dIC

)

1+b S = __________ dIB 1 – b ____ dIC

( )

(6.35)

From this equation, it is clear that this factor S should be as small as possible to have better thermal stability. The stability factor S¢ is defined as the rate of change of IC with VBE, keeping ICO and b constant

∂IC DIC S ¢ = _____ ª _____ ∂VBE DVBE The stability factor S ¢¢ is defined as the rate of change of IC with respect to b, keeping ICO and VBE constant ∂IC DIC S¢¢ = ___ ª ____ ∂b Db

The stability factors for some commonly used biasing circuits are discussed below.

A common emitter amplifier using fixed bias circuit is shown in Fig. 6.28. The d.c. analysis of the circuit yields the following equation. VCC = IBRB + VBE (6.36) V – V CC BE Therefore, IB = _________ RB Since this equation is independent of current IC, dIB/dIC = 0 and the stability factor given in Eq. (6.35) reduces to VCC S =1+b Since b is a large quantity, this is a very poor bias stable circuit. Therefore, in practice, this circuit is not used for biasing the base. The advantage of this method are: (a) simplicity, (b) small number of components required, and (c) if the supply voltage is very large as compared to VBE of the transistor, then the base current becomes largely independent of the voltage VBE.

RC

RB IB

IC

Vin

Vout

VBE

In the fixed bias compensation method shown in Fig. 6.29 a silicon transistor with = 100 is used. VCC = 6 V, RC = 3 k . RB = 530 k . Draw the d.c. load line and determine the operating point. What is the stability factor?

Solution

(a) d.c. load line:

IC (mA)

VCE = VCC – ICRC When When

IC = 0, VCE = VCC = 6 V VCC 6 VCE = 0, IC = ____ = _______3 = 2 mA RC 3 × 10

2

Q

1

(b) Operating point Q: For silicon transistor, VBE = 0.7 V 0

3

6

VCE (V )

VCC = IBRB + VBE Therefore,

VCC – VBE 6 – 0.7 IB = _________ = _________ = 10 mA RB 530 × 103

Therefore,

IC = bIB = 100 × 10 × 10 – 6 = 1 mA VCE = VCC – ICRC = 6 – 1 × 10 – 3 × 3 × 103 = 3 V

Therefore operating point is VCEQ = 3 V and ICQ = 1 mA. (c) Stability factor: S = 1 + b = 1 + 100 = 101

Find the collector current and collector-to-emitter voltage for the given circuit as shown in Fig. 6.30.

Solution

VCC = 9V

For a silicon transistor, VBE = 0.7 V Base current

RB 300 kW

VCC – VBE 9 – 0.7 IB = _________ = _________3 = 27.67 mA RB 300 × 10

Collector current IC = bIB = 50 × 27.67 × 10

–6

RC = 2 kW

b = 50

= 1.38 mA

Collector-to-emitter voltage VCE = VCC – ICRC = 9 – 1.38 × 10 – 3 × 2 × 103 = 6.24 V

A Germanium transistor having = 100 and VBE = 0.2 V is used in a fixed bias amplifier circuit where VCC = 16 V, RC = 5 k and RB = 790 k . Determine its operating point.

Solution

For a Germanium transistor, VBE = 0.2 V

VCC = 16 V

Applying KVL to the base circuit, we have VCC – IBRB – VBE = 0 Therefore,

RC = 5 kW RB = 790 kW

VCC – VBE 16 – 0.2 IB = _________ = _________3 = 20 mA RB 790 × 10 IC = bIB = 100 × 20 mA = 2 mA

Applying KVL to the collector circuit, we have VCC – ICRC – VCE = 0 VCE = VCC – ICRC = 16 – 2 × 10 – 3 × 5 × 103 = 6 V Hence, the operating point is IC = 2 mA and VCE = 6 V.

b = 100 VBE = 0.2 V

The circuit as shown in Fig. 6.32 has fixed bias using NPN transistor. Determine the value of base current, collector current and collector to emitter voltage. VCC = 25 V RC 820 W

Applying KVL to the base circuit, we have

Solution

VCC – IBRB – VBE = 0 Therefore,

RB 180 kW

Vo

VCC – VBE 25 – 0.7 IB = _________ = _________3 = 135 mA RB 180 × 10

b = 80

IC = bIB = 80 × 135 × 10 – 6 = 10.8 mA Applying KVL to the collector circuit, we have VCC – ICRC – VCE = 0 Therefore,

VCE = VCC – ICRC = 25 – 10.8 × 10 – 3 × 820 = 16.144 V

For a fixed bias configuration shown in Fig. 6.28, determine IC, RC, RB and VCE using the following specifications: VCC = 12 V, VC = 6 V, = 80 and IB = 40 A.

Solution

Assume VBE = 0.7 V for a silicon transistor. IC = bIB = 80 × 40 mA = 3.2 mA VCC – VC 12 – 6 RC = _________ = _________ = 1.875 kW IC 3.2 × 10 – 3 VCC – VBE 12 – 0.7 RB = _________ = _________ = 282.5 kW IB 40 × 10 – 6

Since emitter is grounded,

VE = 0. VCE = VC = 6 V VCC

The emitter-feedback bias network shown in Fig. 6.33 contains an emitter resistor for improving the stability level over that of the fixed-bias configuration. The analysis will be performed by first examining the base-emitter loop and then using the results to investigate the collector-emitter loop. Applying Kirchhoff’s voltage law for the base-feedback emitter loop, we get VCC – IBRB – VBE – IERE = 0 VCC – IBRB – VBE – (IB + IC) RE = 0

(6.37)

IC RC

RB IB

Vo

Vi C1

C2 IE RE

VCC – IB (RB + RE) – VBE – ICRE = 0 VCC – VBE = IB (RB + RE) + ICRE VCC – VBE RE IB = _________ – ________ IC RE + RB RE + RB

(

Therefore,

)

(6.38)

Here VBE is independent of IC.

(

dIB RE ___ = – ________ RE + RB dIC

Hence,

)

(6.39)

Substituting Eq. (6.39) in Eq. (6.35), we get the stability factor as 1+b S = ____________ (6.40) RL ________ 1+ b RE + RB bRE _________ Since 1 + > 1, S < (1 + b). Note that the value of the stability factor S is always lower in (RE + RB) emitter-feedback bias circuit than that of the fixed bias circuit. Hence it is clear that a better thermal stability can be achieved in emitter-feedback bias circuit than the fixed-bias circuit. Applying Kirchhoff’s voltage law for the collector-emitter loop, we get IE RE + VCE + IC RC – VCC = 0 Substituting IE = IC , we have VCE – VCC + IC (RC + RE) = 0 and

VCE = VCC – IC (RC + RE)

(6.41)

VE is the voltage from emitter to ground and is determined by VE = IERE

(6.42)

The voltage from collector to ground can be determined from VCE = VC – VE and

VC = VCE + VE

(6.43)

or

VC = VCC – ICRC

(6.44)

The voltage at the base with respect to ground can be determined from or

VB = VCC – IBRE

(6.45)

VB = VBE + VE

(6.46)

For the emitter-feedback bias circuit, VCC = + 10 V, RC = 1.5 k , RB = 270 k and RE = 1 k . Assuming = 50, determine (a) Stability factor, S (b) IB (c) IC (d) VCE (e) VC (f) VE (g) VB and (h) VBC.

Solution

(a) The stability factor is

1+b 1 + 50 S = _____________ = _____________________ bR (50 × 1 × 103) E 1 + _________ 1 + _________________ (RE + RB) 1 × 103 + 270 × 103 51 51 = _________ = _____ = 43.04 1 + 0.185 1.185 (b)

VCC – VBE 10 – 0.7 9.3 IB = ______________ = _____________________ = ____ = 28.97 mA RB + (b + 1) RE 27 × 103 + (51) (1 × 103) 321 IC = bIB = (50) (28.97 × 10 – 6) = 1.45 mA

(c) (d)

VCE = VCC – IC (RC + RE) = 10 – 1.45 × 10 – 3 (1.5 × 103 + 1 × 103) = 10 – 3.62 = 6.38 V

(e)

VC = VCC – ICRC = 10 – 1.45 × 10 – 3 (1.5 × 103) = 7.825 V

(f)

VE = VC – VCE = 7.825 – 6.38 = 1.445 V VE = IERE = ICRE = 1.45 × 10 – 3 × 1 × 103 = 1.45 V

or (g)

VB = VBE + VE = 0.7 + 1.45 = 2.15 V

(h)

VBC = VB – VC = 2.15 – 7.825 = |5.675| V

(reverse bias as required)

Calculate d.c. bias voltage and currents in the circuit in Fig. 6.34. Neglect VBE of transistor.

Solution Given: VCC = 20 V; RB = 400 kW, b = 100, RE = 1 kW; RC = 2 kW IBRB + VBE + IERE = VCC IC __ R + 0 + (IC + IB) RE = 20 b B

[

]

RB RE IC ___ + RE + ___ = 20 b b Therefore,

20 IC = _______________________ = 4 mA 3 400 × 10 _________ + 1 × 103 + 10 100

[

]

IC 4 × 10 – 3 IB = __ = ________ = 0.4 A 100 VB = VBE + IERE = 0 + 4 × 10 – 3 × 1 × 103 = 4 V, since IC

IE

+ VCC

A common emitter amplifier using collector-to-base bias circuit is shown in Fig. 6.35. This circuit is the simplest way to provide some degree of stabilization to the amplifier operating point. If the collector current IC tends to increase due to either increase in temperature or the transistor has been replaced by the one with a higher , the voltage drop across RC increases, thereby reducing the value or VCE. Therefore, IB decreases which, in turn, compensates the increase in IC. Thus, greater stability is obtained.

RC RB

Vin

IB

IC Vout

VBE

The loop equation for this circuit is VCC = (IB + IC) RC + IBRB + VBE i.e.

Therefore,

VCC – VBE – ICRC IB = ________________ RC + RB RC dIB ________ ___ = dIC RC + RB

(6.47) (6.48)

(6.49)

Substituting Eq. (6.49) into Eq. (6.35), we get 1+ S = _______________ RC 1 + ________ RC + RB

(

)

(6.50)

As can be seen, this value of the stability factor is smaller than the value obtained by fixed bias circuit. Also, S can be made small and the stability can be improved by making RB small or RC large. If RC is very small, then S = ( + 1), i.e. stability is very poor. Hence, the value of RC must be quite large for good stabilization. Thus, collector-to-base bias arrangement is not satisfactory for the amplifier circuits like transformer coupled amplifier where the d.c. load resistance in collector circuit is very small. For such amplifiers, emitter bias or self bias will be the most satisfactory transistor biasing for stabilization.

In the biasing with feedback resistor method, a silicon transistor with feedback resistor is used. The operating point is at 7 V, 1 mA and VCC = 12 V. Assume = 100. Determine (a) the value of RB, (b) stability factor, and (c) what will be the new operating point if = 50 with all other circuit values are same.

Solution Refer to Fig. 6.28. We know that for a silicon transistor, VBE = 0.7 V. (a) To determine RB : The operating point is at

VCE = 7 V and IC = 1 mA VCC – VCE 12 – 7 RC = __________ = ________ =5k IC 1 × 10 – 3

Here,

IC 1 × 10 – 3 IB = __ = ________ = 10 A 100 Using the relation, VCC – VBE – ICRC 12 – 0.7 – 1 × 10 – 3 × 5 × 103 RB = ________________ = _________________________ = 630 k IB 10 × 10 – 6 (b) Stability factor,

1+ S = ______________ RC 1 + ________ RC + RB

[

]

1 + 100 = 56.5 = ______________________ 5 × 103 1 + 100 _____________3 (5 + 630) × 10

[

(c) To determine new operating point when

]

= 50

VCC = IBRC + IBRB + VBE = IB ( RC + RB) + VBE 12 = IB (50 × 5 × 103 + 630 × 103) + 0.7

i.e.

11.3 IB = _________3 = 12.84 A 880 × 10 IC = IB = 50 × 12.84 × 10 – 6 = 0.642 mA

Therefore,

VCE = VCC – ICRC = 12 – 0.642 × 10 – 3 × 5 × 103 = 8.79 V Therefore, the coordinates of the new operating point are VCEQ = 8.79 V and ICQ = 0.642 mA.

An NPN transistor if = 50 is used in common emitter circuit with VCC = 10 V and RC = 2 k . The bias is obtained by connecting 100 k resistor from collector to base. Find the quiescent point and stability factor.

Solution

Given

VCC = 10 V, RC = 2 k , = 50 and collector to base resistor RB = 100 k

To determine the quiescent point: We know that for the collector to base bias transistor circuit,

VCC = bIBRC + IBRB + VBE Therefore,

VCC – VBE IB = __________ RB + b ◊ RC 10 – 0.7 = _______________________ = 46.5 mA 3 100 × 10 + 50 × 2 × 10 – 3 IC = b ◊ IB = 50 × 46.5 × 10 – 6 = 2.325 mA

Hence,

VCE = VCC – ICRC = 10 – 2.325 × 10 – 3 × 2 × 103 = 5.35 V Therefore, the co-ordinates of the new operating point are VCEQ = 5.35 V and ICQ = 2.325 mA To find the stability factor S: 1+b S = ______________ RC 1 + b ________ RC + RB

[

]

1 + 50 = _________________________ = 25.75 2 × 103 _________________ 1 + 50 2 × 103 + 100 × 103

[

]

In a collector to base CE amplifier circuit of Fig. 6.28 having VCC = 12 V, RC = 250 k , IB = 0.25 mA, = 100 and VCEQ = 8 V, calculate RB and stability factor.

VCEQ 8 RB = _____ = __________ = 32 kW IB 0.25 × 10 – 3

Solution

Stability factor,

1+b 101 S = _______________ = _________________ = 56.9 R 250 C 1 + 100 ________ 1 + b ________ 32 + 250 RC + RB

(

)

(

)

Calculate the quiescent current and voltage of collector to base bias arrangement using the following data:

VCC = 10 V, RB = 100 k , RC = 2 k ,

= 50 and also specify a value of RB so that VCE = 7 V.

Solution (a) Applying KVL to the base circuit, we have VCC – IB (1 + b) RC – IB RB – VBE = 0

Therefore,

VCC – VBE 10 – 0.7 IB = ______________ = __________________________ = 46 mA RB + (1 + b) RC 100 × 103 + (1 + 50) × 2 × 103 IC = bIB = 50 × 46 mA = 2.3 mA

Applying KVL to the collector circuit, we have

VCC = 10 V

VCC – (IB + IC) RC – VCE = 0 Therefore,

VCE = VCC – (IB + IC) RC

RB = 100 KW IC + IB

RC = 2 KW

= 10 – (46 × 10 – 6 + 2.3 × 10 – 3) IB

× 2 × 103 = 5.308 V Quiescent current, Quiescent voltage, (b) Given

b = 50

ICQ = 2.3 mA and VCEQ = 5.308 V VCE = 7 V (IB + IC) RC = VCC – VCE

We have,

(1 + b) IBRC = VCC – VCE VCC – VCE 10 – 7 IB = __________ = ________________3 = 29.41 mA (1 + b) RC (1 + 50) × 2 × 10 VCC = IBRB + VBE VCE – VBE 7 – 0.7 RB = _________ = ___________ = 214.2 kW IB 29.41 × 10 – 6

Figure 6.37 shows the collector-emitter feedback bias circuit that can be obtained by applying both the collector-feedback and emitter-feedback. Here collector-feedback is provided by connecting a resistance RB from the collector to the base and emitter-feedback is provided by connection an emitter resistance RE from the emitter to ground. Both the feedbacks are used to control the collector current IC and the base current IB in the opposite direction to increase the stability as compared to the previous biasing circuits. + VCC IC + IB RC

RB

Vo

IB IC Vi C

VCE VBE RE IE

Applying Kirchhoff’s voltage law to the current, we get (IB + IC) RE + VBE + IBRB + (IB + IC) RC – VCC = 0

(

)

VCC – VBE RE + RC IB = _____________ – _____________ IC RE + RC + RB RE + RC + RB

Therefore, Since VBE is independent of IC,

(

RE + RC dIB ___ = – _____________ RE + RC + RB dIC

)

Substituting the above equation in Eq. (6.35), we get 1+b S = ________________ b (RE + RC) 1 + _____________ RE + RC + RB

(6.51)

From this, it is clear that the stability of the collector-emitter feedback bias circuit is always better than that of the collector-feedback and emitter feedback circuits.

A simple circuit used to establish a stable operating point is the self biasing configuration. The self bias, also called as emitter bias, or emitter resistor and potential divider circuit, that can be used for low collector resistance, is shown in Fig. 6.38. The current in the emitter resistor RE causes a voltage drop which is in the direction to reverse bias the emitter junction. For the transistor to remain in the active region, the base-emitter junction has to be forward biased. The required base bias is obtained from the power supply through the potential divider network of the resistance R1 and R2. + VCC

IC R1

+ VCC

IC

RC IB

RC RB

Vout

VT VBE R2

IB

IE = (IB + IC) VT

RE

(a)

IE

RE

(b)

If IC tends to increase, say, due to increase in ICO with temperature, the current in RE increases. Hence, the voltage drop across RE increases thereby decreasing the base current. As a result, IC is maintained almost constant.

Applying Thevenin’s Theorem to the circuit of Fig. 6.38, for finding the base current, we have, R2 VCC R1R2 VT = _______ and RB = _______ R1 + R2 R1 + R2 The loop equation around the base circuit can be written as VT = IBRB + VBE + (IB + IC) RE Differentiating this equation with respect to IC, we get RE dIB ________ ___ = dIC RE + RB Substituting this equation in Eq. (6.35), we get 1+b S = ______________ RE 1 + b ________ RE + RB

(

Therefore,

)

RB 1 + ___ R E S = (1 + b) __________ RB 1 + b + ___ RE

(6.52)

As can be seen, the value of S is equal to one if the ratio RB /RE is very small as compared to 1. As this ratio becomes comparable to unity, and beyond towards infinity, the value of the stability factor goes on increasing till S = 1 + b. This improvement in the stability up to a factor equal to 1 is achieved at the cost of power dissipation. To improve the stability, the equivalent resistance RB must be decreased, forcing more current in the voltage divider network of R1 and R2. Often, to prevent the loss of gain due to the negative feedback, RE is shunted by a capacitor CE. The capacitive reactance XCE must be equal to about one-tenth of the value of the resistance RE at the lowest operating frequency. The stability factor S¢ is defined as the rate of change of IC with VBE, keeping ICO and b constant.

∂IC DIC S ¢ = _____ = _____ ∂VBE DVBE

From Fig. 6.38 (b), VT = IBRB + VBE + IERE = IB [RB + RE] + ICRE + VBE since [IE = IB + IC] We have

IC – (1 + b) ICO IB = ______________ b

(6.53) (6.54)

Substituting Eq. (6.53) in Eq. (6.54), we get IC ICO VT = __ (RB + RE) + VBE + ICRE + ____ (1 + b) {RB + RE} b b

(6.55)

Differentiating the above eq. w.r.t. VBE we get dIC RB + RE dIC 0 = _____ ________ + 1 + RE _____ + 0 dVBE dVBE b

(

)

[

dIC RB + RE – 1 = _____ RE + ________ dVBE b

[

]

dIC RB + (1 + b) RE – 1 = _____ ______________ dVBE b Therefore,

]

dIC –b S ¢ = _____ = ______________ dVBE RB + (1 + b) RE

(6.56)

The stability factor S¢¢ is defined as the rate of change of IC w.r.t. to b, keeping ICO and VBE constant. Rearranging Eq. (6.55), we have

( )

1+b b _____ ICO (RB + RE) b b (VT – VBE) IC = ______________ + _____________________ RB + (1 + b) RE RB + (1 + b) RE

(6.57)

Since b >> 1, the numerator of the second term can be written as

( )

1+b (RB + RE) _____ ICO = (RB + RE) ICO b

(6.58)

Substituting Eq. 6.58 in Eq. 6.57, we have b (RB + RE) ICO b (VT – VBE) IC = ______________ + ______________ RE + (1 + b) RE RB + (1 + b) RE

Therefore,

b [VT – VBE + (RB + RE) ICO] IC = _________________________ RB + (1 + b) RE

Let,

V ¢ = (RB + RE) ICO.

Therefore,

b [VT – VBE + V ¢] IC = _______________ RB + (1 + b) RE

(6.59)

Differenting the above equation w.r.t. b and simplifying, we obtain IC SIC dIC S≤ = ___ = _________________ = ________ db b (1 + b) R E b 1 + b ________ RE + RB

[ (

)]

(6.60)

In a CE Germanium transistor amplifier circuit, the bias is provided by self bias, i.e. emitter resistor and potential divider arrangement (refer to Fig. 6.29). The various parameters are: VCC = 16 V, RC = 3 k , RE = 2 k , R1 = 56 k , R2 = 20 k and = 0.985. Determine (a) the coordinates of the operating point, and (b) the stability factor S.

Solution

For a Germanium transistor, VBE = 0.3 V. As a = 0.985,

a 0.985 b = _____ = ________ = 66 1 – a 1 – 0.985 (a) To find the coordinates of the operating point Referring to Fig. 6.38, we have Thevenin’s voltage,

R2 VT = _______ VCC R1 + R2 20 × 103 = ________ × 16 = 4.21 V 76 × 103

Thevenin’s resistance,

R1R2 20 × 103 × 56 × 103 RB = _______ = _________________ R1 + R2 76 × 103 = 14.737 kW

The loop equation around the base circuit is VT = IBRB + VBE + (IB + IC) RE

(

)

IC IC = __ RB + VBE + __ + IC RE b b IC 1 4.21 = ___ × 14.737 × 103 + 0.3 + IC ___ + 1 × 2 × 103 66 66 3.91 = IC [0.223 + 2.03] × 103 3.91 IC = __________3 = 1.73 mA 2.253 × 10 IC ª IE = 1.73 mA

(

Therefore, Since IB is very small, Therefore,

)

VCE = VCC – ICRC – IERE = VCC – IC [RC + RE] = 16 – 1.73 × 10 – 3 × 5 × 103 = 7.35 V

Therefore, the coordinates of the operating point are IC = 1.73 mA and VCE = 7.35 V.

(b) To find the stability factor S, RB 1 + ___ R E S = (1 + b) __________ RB 1 + b + ___ RE 14.737 1 + _______ 2 ______________ = (1 + 66) 14.737 ______ 1 + 66 + 2 8.3685 = 67 × _______ = 7.537 74.3685

Consider the self bias circuit where VCC = 22.5 Volts, RC = 5.6 k , R2 = 10 k and R1 = 90 k , hfe = 55, VBE = 0.6 V. The transistor operates in active region. Determine (a) operating point and (b) stability factor.

So lution For the given circuit, VBE = 0.6 V, hfe = 55 (a) To determine the operating point: Rz 10 × 103 Thevenin’s voltage, VT = _______ VCC = _________3 × 22.5 = 2.25 V R1 + R2 100 × 10 Thevenin’s resistance,

R1R2 10 × 103 × 90 × 103 RB = _______ = _________________ = 9 kW R1 + R2 100 × 103

The loop equation around the base circuit is VB = IBRB + VBE + (IB + IC) RE

(

)

IC IC = ___ RB + VBE + ___ + IC RE hfe hfe IC 1 2.25 = ___ × 9 × 103 + 0.6 + ___ + 1 IC × 1 × 103 55 55

(

)

2.25 = IC × 0.16 × 103 + 0.6 + 1.01 × IC × 103 2.25 = IC × 1.17 × 103 + 0.6 Therefore, Since IB is very small, Therefore,

2.25 – 0.6 IC = _________3 = 1.41 mA 1.17 × 10 IC ª IE = 1.41 mA VCE = VCC – ICRC – IERE =VCC – IC (RC + RE) = 22.5 – 1.41 × 10 – 3 × 6.6 × 103 = 13.19 V

Operating point coordinates are VCE = 13.19 V and IC = 1.41 mA (b) To find the stability factor, S RB 9 × 103 1 + _______3 1 + ___ RE 1 × 10 56 × 10 560 S = (1 + b) __________ = (1 + 55) _______________ = _______ = ____ = 8.6 3 R 65 65 B 9 × 10 1 + b + ___ 1 + 55 + _______3 RE 1 × 10

The Fig. 6.39 shows that d.c. bias circuit of a common emitter transistor amplifier. Find the percentage change in collector current, if the transistor with hfe = 50 is replaced by another transistor with hfe = 150. It is given that the base emitter drop VBE = 0.6 V. +12 V

Solution (a) For the given circuit, VBE = 0.6 V, hfe = 50 Thevenin’s voltage,

R1 25 kW

R2 5 × 103 VT = ________ VCC = ________3 × 12 = 2 V R1 + R2 30 × 10

R1R2 25 × 103 × 5 × 103 Thevenin’s resistance, RB = _______ = ________________ = 4.16 kW R1 + R2 30 × 103

VT = VB R2 5 kW

The loop equation around the base circuit is VT = VB = IBRB + VBE + (IB + IC) RE

(

)

IC IC = ___ RB + VBE + ___ + IC RE hfe hfe IC 1 2 = ___ × 4.6 × 103 + 0.6 + ___ + 1 × IC × 0.1 × 103 50 50

(

)

2 – 0.6 = IC × (0.08 + 0.102) × 103 Therefore,

14 IC = __________3 = 7.69 mA 0.182 × 10

(b) For the given circuit,VBE = 0.6 V, hfe = 150 The loop equation around the base circuit is VB = IBRB + VBE + (IB + IC) RE

(

)

IC IC = ___ RB + VBE + ___ + IC RE hfe hfe

RC 1 kW

RE 100 W

IC 1 2 = ___ × 4.6 × 103 + 0.6 + ___ + 1 × IC × 0.1 × 103 50 50

(

)

2 – 0.6 = IC × (0.028 + 0.1) × 103 Therefore, Change in collector current

1.4 IC = __________3 = 10.93 mA 0.128 × 10 10.93 – 7.69 = ___________ = 0.42 i.e. 42% 7.69

There is 42% change in IC when hfe changes from 50 to 150.

If the various parameters of a CE amplifier which uses the self bias method are VCC = 12 V, R1 = 10 k , R2 = 5 k , RC = 1 k , RE = 2 k and = 100, find (a) the coordinates of the operating point and (b) the stability factor, assuming the transistor to be silicon.

Solution (a) To find the coordinates of the operating point Refer to Fig. 6.38 Thevenin’s voltage,

R2 5 × 103 VT = _______ VCC = ________3 × 12 = 4 V R1 + R2 15 × 10

Thevenin’s resistance,

R1R2 5 × 103 × 10 × 103 RB = _________ = ________________ = 3.33 kW (R1 + R2) 15 × 103

The loop equation around the basic circuit is VT = IBRB + VBE + (IB + IC) RE

(

)

IC IC = __ RB + VBE + __ + IC RE b b IC 1 4 = ____ × 3.33 × 103 + 0.7 + IC ____ + 1 × 2 × 103 100 100

(

)

3.3 = (33.3 + 2020) IC 3.3 IC = ______ = 1.61 mA 2053.3 Since IB is very small, Therefore,

IC ª IE = 1.61 mA VCE = VCC – ICRC – IERE = VCC – IC [RC + RE] = 12 – 1.61 × 10 – 3 × 3 × 103 = 7.17 V

Therefore, the coordinates of the operating point are IC = 1.61 mA and VCE = 7.17 V.

(b) To find the stability factor S: RB 3.33 × 103 1 + _________ 1 + ___ RE 2 × 103 S = (1 + b) __________ = (1 + 100) ___________________ = 2.6 RB 3.33 × 103 1 + b + ___ 1 + 100 + _________ RE 2 × 103

Determine the quiescent current and collector to emitter voltage for a Germanium transistor with = 50 in self biasing arrangement. Draw the circuit with a given component value with VCC = 20 V, RC = 2 k , RE = 100 , R1 = 100 k and R2 = 5 k . Also find the stability factor.

Solution

For a Germanium transistor, VBE = 0.3 V and b = 50

To find the coordinates of the operating point: Thevenin’s voltage,

R2 VT = _______ VCC R1 + R2 5 × 103 = _________3 × 20 = 0.95 V 105 × 10

Thevenin’s resistance,

R1R2 100 × 103 × 5 × 103 RB = _______ = _________________ = 4.76 kW R1 + R2 105 × 103

The loop equation around the base circuit is VT = IBRB + VBE + (IB + IC) RE

(

)

IC IC = __ RB + VBE + __ + IC RE b b IC 51 0.95 = ___ × 4.76 × 103 + 0.3 + IC × ___ × 100 50 50 0.65 = 197.2 IC Therefore,

0.65 IC = _____ = 3.296 mA 197.2

Since IB is very small,

IC = ª IE = 3.296 mA

Therefore,

VCE = VCC – ICRC – IERE = VCC – IC (RC + RE) = 20 – 3.296 × 10 – 3 × 2.01 × 103 = 13.375 V

Therefore, the coordinates of the operating point are IC = 3.296 mA and VCE = 13.375 V.

To find the stability factor S: RB 4.76 × 103 _________ 1 + ___ 1 + RE 100 S = (1 + b) __________ = (1 + 50) __________________ = 25.18 R B 4.76 × 103 1 + b + ___ 1 + 50 + _________ RE 100

A germanium transistor is used in a self biasing circuit configuration as shown below with VCC = 16 V, RC = 1.5 k and = 50. The operating point desired is VCE = 8V and IC = 4 mA. If a stability factor S = 10 is desired, calculate the values of R1 and R2 and RE of the circuit (Fig. 6.40). VCC = 16 V IC = 4 mA

RC = 1.5 kW

R1 C

VCE = 8 V

B E R2

RE

IE

Solution To determine RE : We know that,

VCC = VCE + IC (RC + RE) 16 = 8 + 4 × 10 – 3 (1.5 × 103 + RE)

Therefore,

RE = 500 W

To determine RTH: Given Stability factor

Upon solving, we get

S = 10 1+b 1 + 50 S = ______________ = _________________ R 500 E __________ 1 + b _________ 1 + 50 R + 500 RTH + RE TH

(

RTH = 5.58 kW

To determine R2: R2 = 0.1 b RE = 27.98 kW To determine R1: We know that,

R1R2 RTH = R1||R2 = _______ R1 + R2

)

R1 × 27.98 × 103 5.58 × 103 = _______________3 R1 + 27.98 × 10 Therefore,

R1 = 6.97 kW

A CE transistor amplifier with voltage divider bias circuit of Fig. 6.38 is designed to establish the quiescent point at VCE = 12 V, IC = 2 mA and stability factor 5.1. If VCC = 24 V, VBE = 0.7 V, = 50 and RC = 4.7 k , determine the values of resistors RE, R1 and R2.

Solution (a) To determine RE: VCE = VCC – ICRC – IERE = VCC – IC [RC + RE], since IC ª IE 12 = 24 – 2 × 10 – 3 [4.7 × 103 + RE] Therefore,

RE = 1.3 kW

(b) To determine R1 and R2: Stability factor,

R1R2 1+b S = _______________, where RB = _________ R (R E 1 + R2) 1 + b ________ RE + RB

(

)

51 5.1 = _____________________ 1.3 × 103 1 + 50 _____________ 1.3 × 103 + RB

( (

) )

i.e.

1.3 × 103 51 1 + 50 _____________ = ___ = 10 3 5.1 1.3 × 10 + RB

Therefore,

(

)

50 × 1.3 × 103 _____________ =9 1.3 × 103 + RB

50 × 1.3 × 103 1.3 × 103 + RB = _____________ = 7.2 kW 9 RB = 5.9 kW Also, we know that for a good voltage divider, the value of resistor R2 = 0.1 bRE Therefore,

R2 = 0.1 × 50 × 1.3 × 103 = 6.5 kW

R1R2 RB = _______ R1 + R2 R1 × 6.5 × 103 5.9 × 103 = _____________3 R1 + 6.5 × 10 Simplifying, we get

R1 = 64 kW

In the circuit shown in Fig. 6.41, if IC = 2 mA and VCE = 3 V, calculate R1 and R3.

Solution

Given: b = 100, IC = 2 mA, VCE = 3 V, VBE = 0.6 V,

+ VCC = 15 V

R2 = 10 kW and R4 = 500 W I + IB

IC b = __ IB

We know that

VCC = ICR3 + VCE + IER4 IE = IC + IB = 20 × 10 – 6 + 2 × 10 – 3 = 2.02 mA

R3 b = 100

IB

IC 2 × 10 – 3 IB = __ = ________ = 20 mA 100 b

Hence,

IC

R1

VBE (ac1) = 0.5 V VBE R2

10 kW

R4 = 500 W

Substituting the values, we get 15 = 2 × 10 – 3 × R3 + 3 × 2.02 × 10 –3 × 500 Therefore,

R3 = 5.495 kW VB = VBE + IER4 = 0.6 + 2.02 × 10 – 3 × 500 = 1.61

From the circuit,

R2VCC VB = _______ R1 + R2 10 × 103 × 15 1.61 = ____________3 R1 + 10 × 10

Therefore,

R1 = 83.17 kW

An NPN transistor if = 50 is used in common emitter circuit with VCC = 10 V and RC = 2 k . The bias is obtained by connecting 100 k resistor from collector to base. Find the quiescent point and stability factor.

Solution

Given

VCC = 10 V, RC = 2 kW, b = 50 and collector to base resistor, RB = 100 kW

To determine the quiescent point: We know that the collector to base bias transistor circuit

VCC = bIBRC + IBRB + VBE VCC – VBE IB = __________ RB + b ◊ RC

Therefore,

10 – 0.7 = ______________________ = 46.5 mA 100 × 103 + 50 × 2 × 10+3 IC = bIB = 50 × 46.5 × 10 – 6 = 2.325 mA

Hence,

VCE = VCC – ICRC = 10 – 2.325 × 10 – 3 × 2 × 103 = 5.35 V Therefore, the co-ordinates of the new operating point are VCEQ = 5.35 V and ICQ = 2.325 mA To find the stability factor S:

1+b S = ______________ RC 1 + b ________ RC + RB

[

]

1 + 50 = _________________________ = 25.75 2 × 103 1 + 50 _________________ 2 × 103 + 100 × 103

[

Design a voltage divider bias network using a supply of 24 V, VE = VCC / 8.

Solution

Given:

]

= 110 and ICQ = 4 mA VCEQ = 8 V. Choose

ICQ = 4 mA, VCEQ = 8 V, VE = VCC / 8, VCC = 24 V, b = 110

(a) To determine IB, IE and VE : ICQ 4 × 103 IB = ____ = _______ = 36.36 mA 110 b IE = IB + IC = 36.36 × 10 – 6 + 4 × 10 – 3 = 4.03636 mA VCC 24 VE = ____ = ___ = 3 V 8 8 (b) To determine RE and R2:

VE 0.3 RE = ___ = _____________ = 743.244 W IE 4.03636 × 10 – 3

Applying KVL to the collector circuit, VCC – ICRC – VCE – VE = 0 Therefore,

VCC – VCE – VE 24 – 8 – 3 RC = ______________ = _________ = 3.25 kW IC 4 × 10 – 3

(c) To determine R1 and R2 VB = VE + VBE = 3 + 0.7 = 3.7 V Referring to Fig. 6.38 consider the current through R1 be I + IB and that through R2 be I. Resistors R1 and R2 forms the potential divider. For proper operation of potential divider, current I should be atleast ten times the IB. i.e. I ≥ 10 IB. Therefore, I = 10 IB = 10 × 36.36 × 10 – 6 = 363.6 mA VB 3.7 R2 = ___ = ___________ = 10.176 kW I 363.6 × 10 – 6 VCC – VB 24 – 3.7 R1 = _________ = ____________________ = 50.755 kW I + IB (363.6 + 36.36) × 10 – 6

Determine the stability factor for the circuit shown in Fig. 6.42. VCC

Solution

(IC + I1)

VBE + (IC + IB) RE I2 = ________________ R2

RC R1

I1 = IB + I2

I1

VBE + (IC + IB) RE I1 = IB + ________________ R2

Therefore,

IBR2 + VBE + (IC + IB) RE = _______________________ R2

IB R2

I2

IC

(IC + IB) RE

Applying KVL to the collector, base-emitter loop, we have VCC = (IC + I1) RC – I1R1 – VBE – (IC + IB) RE = (IC + I1) RC + I1R1 + VBE + (IC + IB) RE = ICRC + I1RC + I1R1 + VBE + ICRE + IBRE = IC (RC + RE) + I1 (RC + R1) + VBE + IBRE Substituting the value of I1 from the equation determined above, we get IBR2 + VBE + (IC + IB) RE VCC = IC (RC + RE) + _______________________ (RC + R1) + VBE + IBRE R2

[

] [

] [

]

(RC + R1) (RC + R1) (RE + R2) (RC + R1) = IC RC + RE + _________ + IB RE + __________________ + 1 + _________ VBE R2 R2 R2

We know that IC = bIB + (1 + b) ICO Therefore,

IC – (1 + b) ICO IB = ______________ b

Substituting the value of IB, we get

[

]

RE (RC + R1) IC – (1 + b) ICO VCC = IC RC + RE + ____________ + ______________ × R2 b

[

] [

]

(RE + R2) (RC + R1) (RC + R1) RE + __________________ + 1 + _________ VBE R2 R2

dIC We know that S = _____ . Hence, differentiating the above equation and assuming VBE constant, we dICO get RE (RC + R1) ∂IC (RE + R2) (RC + R1) ∂IC 1 0 = _____ RC + RE + ____________ + _____ × __ RE + __________________ R2 R2 ∂ICO ∂ICO b

[

]

[

[

(RE + R2) (RC + R1) (1 + b) – ______ RE + __________________ R2 b

] ]

∂IC ∂IC R2RC + R2RE + RERC + RER1 1 = _____ __________________________ + _____ × __ × R2 ∂ICO ∂ICO b

[

[

R2RE + RERC + RER1 + R2RC + R1R2 _________________________________ R2

]

[

1 + b R2 (RC + R1) + RE (R1 + R2 + RC) – _____ _____________________________ R2 b

]

∂IC R2RC + RE (R1 + R2 + RC) ∂IC 1 = _____ _______________________ + _____ × __ × R2 ∂ICO ∂ICO b

[

[

]

R2 (RC + R1) + RE (R1 + R2 + RC) _____________________________ R2

[

]

1 + b R2 (RC + R1) + RE (R1 + R2 + RC) – _____ _____________________________ R2 b

]

]

∂IC R2RC + RE (R1 + R2 + RC) R2 (RC + R1) + RE (R1 + R2 + RC) = _____ _______________________ + _____________________________ R2 bR2 ∂ICO

] [

[

]

1+b _____ [R2 (RC + R1) + RE (R1 + R2 + RC)] ∂I b C _____ = _______________________________________________________ R2 (RC + R1) + RE (R1 + R2 + RC) ∂ICO R2RC + RE (R1 + R2 + RC) + _____________________________ b 1+b _____ [R2 (RC + R1) + RE (R1 + R2 + RC)] b = ________________________________________________________ b(R2RC + RE (R1 + R2 + RC)) + R2 (RC + R1) + RE (R1 + R2 + RC) ________________________________________________________ b ∂IC (1 + b) [R2 (RC + R1) + RE (R1 + R2 + RC)] Stability factor, S = _____ = _____________________________________ ∂ICO R1R2 + (b + 1) [R2RC + RE (R1 + R2 + RC)]

In a common base amplifier circuit, the equation for collector current IC is given by IC = aIE + ICO dI S ª _____ = 1 dICO Since this is highly stable, the common base amplifier circuit is not in need of bias stabilization.

In fixed bias method discussed in Section 6.12.1, the stability factor is given by S =1+b Since b, is normally a large quantity, this circuit provides very poor stability. Therefore the fixed biasing technique is not preferred for biasing the base. In collector-to-base bias method, when RC is very small, S ª 1 + b, which is equal to that of fixed bias. Hence, collector-to-base bias method is also not preferable. In self bias method discussed in Section RB 6.12.5, when ___ is very small. S ª 1, which provides good stability. Hence, self bias method is the best RE one over other types of “biasing”.

The various biasing circuits considered in the previous sections used some types of negative feedback to stabilise the operation point. Also, diodes, thermistors and sensistors can be used to compensate for variations in current.

In Fig. 6.43 a thermistor, RT, having a negative temperature coefficient is connected in parallel with R2. The resistance of thermistor decreases exponentially with increase of temperature. An increase in temperature will decrease the base + VCC voltage VBE, reducing IB and IC. Bias stabilization is also proR1 RC vided by RE and CE. IB

In Fig. 6.44 a sensistor, RS, having a positive temperature coefficient is connected across R1 (or RE). RS increase with temperature. As temperature increases, the equivalent resistance of the parallel combination of R1 and RS also increases and hence the base voltage VBE decrease, reducing IB and IC. This reduced IC compensates for the increased IC caused by the increase in ICO, VBE and b due to temperature rise.

Vout

Vin R2

RT RE

CE

+ VCC R1

Rs

RC Vout

Vin R2 RE

+ VCC

Figure 6.45 shows the Thevenin’s equivalent circuit of the voltage divider bias with bias compensation technique. Here, VDD is separately used to keep diode in forward biased condition. If the diode is of same material and type as the transistor, the voltage across the diode VD will have the same temperature coefficient (2.5 m V/°C) as the base to emitter voltage VBE. If VBE changes by a small amount with change in temperature, then VD also changes by the same amount and therefore, the changes cancel each other. We know that,

Rc Vout

RB Vin VBE RE – VD D +

RD – V + DD

[

]

[RB + (1 + b) RE] (RE + RB) (1 + b) VBE = VT – ________________ IC + _______________ ICO b b Rearranging, we have

[

]

[RB + (1 + b) RE] (RE + RB) (1 + b) _______________ IC = VT – VBE + _______________ ICO b IC b Hence,

b [VT – VBE] + (RE + RB) (1 + b) ICO IC = _______________________________ RB + (1 + b) RE

From KVL equation of the base circuit of Fig. 7.14, the above equation can be written as b [Vin – (VBE – VD)] + (RE + RB) (1 + b) ICO IC = _____________________________________ RB + (1 + b) RE Since variation of VD is same as VBE, the collector current IC will be insensitive to variation in VBE. +

Figure. 6.46 shows the diode compensation technique used in voltage divider bias. Here, the diode is connected in series with resistance R2 and it is in forward biased condition. Therefore, VE VB – VBE IE = ___ = ________ RE RE and

IC ª IE

Hence,

IC ª IE

RC

R1

IC VCC VD1

D1

VD2

D2

VB

RE VE –

When VBE changes with temperature, IC also changes. To cancel the change in IC, one diode is used to compensate the base terminal in VBE as shown in Fig. 6.46. The voltage at the base, VB, becomes VB = VR2 + VD Substituting in the above equation for IC, we get VR2 + VD – VBE IC ª ______________ RE If the diode is of the same material and type as the transistor, then the voltage across the diode will have the same temperature coefficient (2.5 mV/°C ) as the base to + VCC I emitter voltage VBE. When VBE changes by a small amount with Rs RC change in temperature, VD also changes by the same amount and thus they cancel each other and the collector current remains conVout IB stant. Therefore, VR2 D IO IC = ____ RE The change in VBE due to temperature is compensated by a change in the diode voltage that keeps IC stable at Q point.

Figure 6.47 shows a transistor amplifier with a diode D connected across the base–emitter junction for compensation of change in collector saturation current ICO. The diode is of the same material as the transistor and it is reverse biased by the base– emitter junction voltage VBE, allowing the diode reverse saturation current I0 to flow through diode D. The base current IB = I – Io. As long as temperature is constant, diode D operates as a resistor. As the temperature increase, ICO of the transistor increases. Hence, to compensate for this, the base current IB should be decreased. The increase in temperature will also cause the keakage current Io through D to increase and thereby decreasing the base current IB The is the required action to keep IC constant. This method of bias compensation does not need a change in IC to effect the change in IB, as both Io and ICO can track almost equally according to the change in temperature.

The FET is a device in which the flow of current through the conducting region is controlled by an electric field. Hence the name Field Effect Transistor (FET). As current conduction is only by majority carriers, FET is said to be a unipolar device. Based on the construction, the FET can be classified into two types as Junction FET(JFET) and Metal Oxide Semiconductor FET(MOSFET) or Insulated Gate FET (IGFET)or Metal Oxide Silicon Transistor(MOST). Depending upon the majority carriers, JFET has been classified into two types, namely, (1) N-channel JFET with electrons as the majority carriers, and (2) P-Channel JFET with holes as the majority carriers.

It consists of a N-type bar which is made of silicon. Ohmic contacts (terminals), made at the two ends of the bar, are called Source and Drain. This terminal is connected to the negative pole of the battery. Electrons which are the majority carriers in the N-type bar enter the bar through this terminal. This terminal is connected to the positive pole of the battery. The majority carriers leave the bar through this terminal. Heavily doped P-type silicon is diffused on both sides of the N-type silicon bar by which PN junctions are formed. These layers are joined together and called Gate G. The region BC of the N-type bar between the depletion region is called the channel. Majority carriers move from the source to drain when a potential difference VDS is applied between the source and drain.

When no voltage is applied between drain and source, and gate and source, the thickness of the depletion regions round the PN junction is uniform as shown in Fig. 7.1. Depletion region

In this case, the PN junctions are reverse biased and hence the thickness of the depletion region increases. As Vgs is decreased from zero, the reverse bias voltage across the PN junction is increased and hence, the thickness of the depletion region in the channel also increases until the two depletion regions make contact with each other. In this condition, the channel is said to be cut-off. The value of Vgs which is required to cut-off the channel is called the cut-off voltage VC.

G

P

C

S

B

N

D

N P

Drain is positive with respect to the source with VGS = 0. Now the majority carriers (electrons) flow through the N-channel from source to drain. Therefore the conventional current ID flows from drain to source. The magnitude of the current will depend upon the following factors: 1. The number of majority carriers (electrons) available in the channel, i.e. the conductivity of the channel. 2. The length L of the channel. 3. The cross-sectional area A of the channel at B. 4. The magnitude of the applied voltage VDS. Thus the channel acts as a resistor of resistance R given by rL R = ___ (7.1) A VDS AVDS ID = ____ = _____ (7.2) R rL where r is the resistivity of the channel. Because of the resistance of the channel and the applied voltage VDS, there is a gradual increase of positive potential along VGG the channel from source to drain. Thus the reverse voltage + – across the PN junctions increases and hence the thickness of G the depletion regions also increases. Therefore, the channel is wedge shaped as shown in Fig. 7.2. S D As VDS is increased, the cross-sectional area of the channel will be reduced. At a certain value VP of VDS, the crosssectional area at B becomes minimum. At this voltage, the channel is said to be pinched off and the drain voltage VP is called the pinch-off voltage. As a result of the decreasing cross-section of the channel with the increase of VDS, the following results are obtained.

C

B

N

N P

–

VDD

+

ID

(i) As VDS is increased from zero, ID increases along OP, and the rate of increase of ID with VDS decreases as shown in Fig. 7.3. The region from VDS = 0V to VDS = VP is called the ohmic region. VDS In the channel ohmic region, the drain to source resistance ____ is related to the gate voltage Vgs, ID in an almost linear manner. This is useful as a voltage variable resistor (VVR) or voltage dependent resistor (VDR). (ii) When VDS = VP, ID becomes maximum. When VDS is increased beyond VP, the length of the pinch-off or saturation region increases. Hence, there is no further increase of ID. (iii) At a certain voltage corresponding to the point B, ID suddenly increases. This effect is due to the Avalanche multiplication of electrons caused by breaking of covalent bonds of silicon atoms in the depletion region between the gate and the drain. The drain voltage at which the breakdown occurs is denoted by BVDGO. The variation of ID with VDS when Vgs = 0 is shown in Fig. 7.3 by the curve OPBC.

ID (mA)

Ohmic region

Pinch-off region

IDSS

VGS = 0

Break down voltage

C P

B

VGS = –1 V VGS = –2 V VGS = –3 V

0

Vp

BVDGO

VDS (V )

When the gate is maintained at a negative voltage less than the negative cut-off voltage, the reverse voltage across the junction is further increased. Hence for a negative value of Vgs, the curve of ID versus VDS is similar to that for Vgs = 0, but the values of VP and BVDGO are lower, as shown in Fig. 7.3. From the curves, it is seen that above the pinch-off voltage, at a constant value of VDS, ID increases with an increase of Vgs. Hence, a JFET is suitable for use as a voltage amplifier, similar to a transistor amplifier. It can be seen from the curve that for voltage VDS = VP, the drain current is not reduced to zero. If the drain current is to be reduced to zero, the ohmic voltage drop along the channel should also be reduced to zero. Further, the reverse biasing to the gate-source PN junction essential for pinching off the channel would also be absent. The drain current ID is controlled by the electric field that extends into the channel due to reverse biased voltage applied to the gate; hence, this device has been given the name Field Effect Transistor. In a bar of P-type semiconductor, the gate is formed due to N-type semiconductor. The working of the P-channel JFET will be similar to that of N-channel JFET with proper alterations in the biasing circuits; in this case holes will be the current carriers instead of electrons. The circuit symbols for N-channel and P-channel JFETs are shown in Fig. 7.4. It should be noted that the direction of the arrow points in the direction of conventional current which would flow into the gate if the PN junction was forward biased.

In a JFET, the drain current ID depends upon the drain voltage VDS and the gate voltage Vgs. Any one of these variables may be fixed and the relation between the other two are determined. These relations are determined by the three parameters which are defined below. It is the slope of the transfer characteristic curves, and is defined by

( )

ID gm = ____ Vgs

VDS

ID = _____, VDS held constant. Vgs

It is the ratio of a small change in the drain current to the corresponding small change in the gate voltage at a constant drain voltage. The change in ID and Vgs should be taken on the straight part of the transfer characteristics. It has the unit of conductance in mho. It is the reciprocal of the slope of the drain characteristics and is defined by

( )

VDS rd = _____ ID

VGS

VDS = _____, VGS held constant. ID

It is the ratio of a small change in the drain voltage to the corresponding small change in the drain current at a constant gate voltage. It has the unit of resistance in ohms. The drain resistance at Vgs = 0 V, i.e. when the depletion regions of the channel are absent, is called as drain-source ON resistance, represented as RDS or RDS(ON). The reciprocal of rd is called the drain conductance. It is denoted by gd or gds. It is defined by

( )

VDS VDS = _____ ID = – _____, ID held constant. Vgs Vgs It is the ratio of a small change in the drain voltage to the corresponding small change in the gate voltage at a constant drain current. Here, the negative sign shows that when Vgs is increased, VDS must be decreased for ID to remain constant. As ID depends on VDS and Vgs, the functional equation can be expressed as

ID = f(VDS, Vgs) If the drain voltage is changed by a small amount from VDS to (VDS + DVDS) and the gate voltage is changed by a small amount from Vgs to (Vgs + DVgs), then the corresponding small change in ID may be obtained by applying Taylor’s theorem with neglecting higher order terms. Thus the small change DID is given by DID DID = _____ DVDS

( )

Vgs

( )

∂ID DVDS + ____ ∂Vgs

DVgs

VDS

Dividing both the sides of this equation by DVGS, we obtain DID ∂ID _____ = _____ DVgs ∂VDS

DVDS ∂ID _____ + ____ DVgs ∂Vgs

( ) ( ) ( ) Vgs

VDS

DID If ID is constant, then _____ = 0 DVgs Therefore, we have DVDS _____ DVgs

( ) ( ) ( )

∂ID 0 = _____ ∂VDS

VGS

∂ID + ____ ∂Vgs ID

VDS

Substituting the values of the partial differential coefficients, we get 1 0 = __ rd ( – m ) + gm

( )

Hence,

m = rd X gm

Therefore, amplification factor (m) is the product of drain resistance (rd) and transconductance (gm). The FET’s continuous power dissipation, PD, is the product of ID and VDS. A single-ended-geometry junction FET is shown in Fig. 7.5 in which the diffusion is done from one side only. The substrate is of P-type material which is epitaxially grown on an N-type channel. A P-type gate is then diffused into the N-type channel. The substrate functions as a second gate which is of relatively low resistivity material. The diffused gate is also of very low resistivity material, allowing the depletion region to spread mostly into the N-type channel. A slab of N-type semiconductor is sandwiched between two layers of P-type material forming two PN junction in this device. Drain The gate reverse voltage that removes all the free charge from the channel is called the pinch-off voltage VP. We consider that the P-type region is doped with NA acceptor atoms, the N-type region is doped with ND donor atoms and the junction formed is abrupt. Moreover, if the acceptor impurity density is assumed to be much larger than the donor density, then the depletion region width in the P-region will be much smaller than the depletion width of the N-region i.e. NA >> ND, then

Gate

Source

Channel

Source

P

ID N

P

p (Substrate)

WP VDS(sat)) ID = KN(Vgs – VTN)2

Saturation region (VSD > VSD (sat)) ID = KP(VSG + VTP)2

Non saturation region (VDS < VDS(sat)) 2 ID = KN[2(Vgs – VTN)VDS – VDS ]

Non saturation region (VSD < VSD(sat)) ID = KP[2(VSG + VTP)VSD – V2 DS]

Transition point

Transition point

VDS(sat) = Vgs – VTN

VSD(sat) = VSG + VTP

Enhancement mode VTN > 0

Enhancement mode VTP < 0

Depletion mode VTN < 0

Depletion mode VTP > 0

1. The P-channel enhancement MOSFET is very popular because it is much easier and cheaper to produce than the N-channel device. 2. The hole mobility is nearly 2.5 times lower than the electron mobility. Thus, a P-channel MOSFET occupies a larger area than an N-channel MOSFET having the same ID rating. 3. The drain resistance of P-channel MOSFET is three times higher than that for an identical N-channel MOSFET. 4. The N-channel MOSFET has the higher packing density which makes it faster in switching applications due to the smaller junction areas and lower inherent capacitances. 5. The N-channel MOSFET is smaller for the same complexity than P-channel device. 6. Due to the positively charged contaminants, the N-channel MOSFET may turn ON prematurely, whereas the P-channel device will not be affected.

1. In an N-channel JFET the current carriers are electrons, whereas the current carriers are holes in a P-channel JFET. 2. Mobility of electrons is large in N-channel JFET; mobility of holes is poor in P-channel JFET. 3. The input noise in less in N-channel JFET than that of P-channel JFET. 4. The transconductance is larger in N-channel JFET than that of P-channel JFET.

FET is operated in the constant-current portion of its output characteristics for the linear applications. In the region before pinch-off, where VDS is small, the drain to source resistance rd can be controlled by the bias voltage VGS. The FET is useful as a Voltage Variable Resistor (VVR) or Voltage Dependent Resistor (VDR).

ID In JFET, the drain-to-source conductance gd = ____ for small values of VDS , which may also be expressed VDS as,

[ ( )]

Vgs gd = gdo 1 – ___ VP

1 __ 2

where gdo is the value of drain conductance when the bias voltage Vgs is zero. The variation of the rd with Vgs can be closely approximated by the empirical expression, r0 rd = ________ 1 – KVgs where r0 = drain resistance at zero gate bias, and K = a constant, dependent upon FET type. Thus, small signal FET drain resistance rd varies with applied gate voltage Vgs and FET acts like a variable passive resistor. FET finds wide applications where VVR property is useful. For example, the VVR can be used in Automatic Gain Control (AGC) circuit of a multistage amplifier.

The development of the digital CMOS logic led to the wide use of the MOSFET devices, Mostly, they employ the P and N channel enhancement MOSFETs, as the basic element. Power dissipation has become a major concern in the integrated circuits, since increasingly more number of transistors are packed into smaller chips. The main use of the CMOS logic arose due to the fact that it reduces the static power consumption, by (ideally) allowing zero current from the power supply to the ground. The CMOS circuit accomplishes this reduction of power dissipation by its operating characteristics. In the basic CMOS inverter configuration, both the gates are tied together to the input signal. When the input switches LOW, only the PMOS device conducts, providing the conducting path for charging the output node. The NMOS device does not conduct due to LOW at its gate. Thus, no power supply to ground path exists and power dissipation due to the short-circuit is avoided. Similarly, when the input switches to HIGH from LOW level, the PMOS devices stops conducting and the NMOS device conducts. This discharges the output node to the ground bringing the output to logic LOW. During this process, the PMOS device does not provide the path from the power supply to the output node. Thus, the static power dissipation from the power supply to ground is theoretically eliminated. This arrangement greatly reduces power consumption and heat generation. However, during the switching of the logic input and the resultant output signals, the short-circuit or switching power dissipation occurs. At this time, both the MOSFETs will conduct briefly leading to dynamic power dissipation that depends on the frequency of switching. Digital and analog CMOS applications are described below:

The growth of digital technologies like the microprocessor has provided the motivation to advance MOSFET technology faster than any other type of silicon-based devices. The major advantage of MOSFETs for digital switching is that the oxide layer between the gate and the channel prevents the d.c. current from flowing through the gate. This further reduces the power consumption and offers very large input impedance. The insulating oxide between the gate and channel effectively isolates the MOSFET between logic stages. This allows a single MOSFET output in driving a considerable number of MOSFET inputs. The bipolar transistor-based logic (such as TTL) does not have such a

high impedance input capability. This gate isolation realized by the MOS devices also makes it easier for the designers to ignore to some extent, the loading effects felt between the logic stages. However, this is limited by the operating frequency, since, as the frequency increases, the input impedance of the MOSFETs decreases.

The advantages of MOSFETs realized in most of the digital circuits do not reflect into the analog circuits. The two types of electronic circuits, namely, analog and digital, operate in different regions of the transistor operation. The digital circuits switch mostly outside the switching region or the Saturation region of operation. On the other hand, the analog circuits mainly operate in the linear region of operation. The bipolar junction transistor (BJT) has traditionally been the analog designer’s transistor of choice, due largely to its higher transconductance and its higher output impedance (drain-voltage independence) in the switching region. Nevertheless, the MOSFETs are also widely used in many types of analog circuits because of certain advantages. The characteristics and performance of many analog circuits can be designed by changing the sizes (length and width) of the MOSFETs. On the other hand, the size of the bipolar device does not significantly affect the performance. The near zero gate current and the negligible drain-source offset voltage of the MOSFETs make them ideal switching elements. This factor makes possible the realization of switched capacitor analog circuits. While operating in their linear region, the MOSFETs can be used as precision resistors, which can have a much higher controlled resistance than the BJTs. In high power circuits, MOSFETs have the advantage of not suffering from thermal runaway as BJTs do. Also, they can be formed into capacitors and gyrator circuits which allow op-amps made from them to appear as inductors, thereby allowing all of the normal analog devices, except for diodes (which can be made smaller than a MOSFET), to be built entirely out of MOSFETs. This allows the designer to realize a complete analog circuit to be made on a silicon chip, in a much smaller chip area. Some ICs combine both the analog and digital MOSFET circuitries on a single mixed-signal integrated circuit, making the required the required board size even smaller. This creates a need to isolate the analog circuits from the digital circuits in the chip level, leading to the use of isolation rings and the need for the Silicon-on-Insulator (SoI) chips. The main advantage of BJTs over MOSFETs, in the analog design process is the ability of BJTs to handle a larger current in a smaller space. Fabrication processes exit that incorporate both the BJTs and MOSFETs configured into a single dvice. Mixed-transistor deices are called Bi-FETs (Bipolar-FETs), if they contain either BJT-NFET or BJT-PFET combinations, or BiCMOS(Bipoar-CMOS) if they contain complementary BJT-PFETs. Such devices have the advantages of both the insulated gates and higher current density.

BJTs have some advantages over MOSFETs for at least two digital applications, Firstly, in high speed switching, they do not have the larger capacitance factor imposed by the gate, which when multiplied by the resistance of the channel gives the intrinsic time constant of the process. The intrinsic time constant places a limit on the speed performance at which a MOSFET can operate, since the higher frequency signals may be filtered out. Widening the channel reduces the resistance of the channel. However, it increases the capacitance by the same amount. On the other hand, reducing the width of the channel increases the resistance, but reduces the capacitance by the same amount. For example, if R × C = Tc1,

the value of 0.5 R × 2C = Tc1 and 2R × 0.5 = Tc1. There is no other way to minimize the intrinsic time constant for a certain process. The various processes using different channel lengths, channel heights, gate thicknesses and materials will also have varying intrinsic time constants. This problem is mostly avoided while using a BJT, since it does not use a gate. The second application where the BJTs prove more advantageous over the MOSFETs stems from the first reasoning. While driving several fan-out gates, the resistance of the MOSFET is in series with the gate capacitances of the other FETs, creating a secondary time constant. Delay circuits use this fact to create a fixed signal delay by using a small CMOS device to send a signal to many other, larger CMOS fan-out devices. The secondary time constant can be minimized by increasing the driving FET’s channel width to decrease its resistance and decreasing the channel widths of the FETs being driven, for reducing the fan-out or driven capacitance. However, its drawback the is that, this increases the capacitance of the driving FET and increases the resistance of the FETs being driven. Usually this drawback is a negligible factor, while comparing with the timing problem. The BJTs are better able to drive the other gates, since they can provide more output current than the MOSFETs. This allows the FETs being driven to get charged faster. Therefore, many integrated circuits employ the MOSFET driven inputs and BiCMOS outputs.

For the proper functioning of a linear FET amplifier, it is necessary to maintain the operating point Q stable in the central portion of the pinch off region. The Q-point should be independent of device parameter variations and ambient temperature changes. This can be achieved by suitably selecting the gate to source voltage (Vgs) and drain current(ID) which is referred to as biasing.

The Q-point, the quiescent point or operating point for a self-biased JFET is established by determining the value of drain current ID for a desired value of gate-to-source voltage, Vgs, or vice-versa. However, if the data sheet of JFET includes a transfer characteristics curve, then the Q-point may be determined by using the procedure given below. (i) Select a convenient value of drain current whose value is generally taken half of the maximum possible value of drain current, IDSS, Then find the voltage drop across source resistor, Rs, by Vs = ID Rs and the gate-to-source voltage from the equation Vgs = – Vs (ii) Plot the assumed value of drain current, ID, and the corresponding gate-to-source voltage, Vgs, on the transfer characteristics curve. (iii) Draw a line through the plotted point and the origin. The point of intersection of the line and the curve gives the desired Q-point. Then, read the co-ordinates of Q-point. It is necessary to fix the Q-point near the mid-point of the transfer characteristic curve of a JFET. The mid-point bias allows a maximum amount of drain current swing between the values of IDSS and the origin. The following analytical method or graphical method can be used for the design of self bias circuit.

The values of the maximum drain current, IDSS, and the gate-to-source cut-off voltage, Vgs(off) are noted down from the data sheets of JFET. The value of the drain current is determined by

[

Vgs ID = 1 – ______ Vgs (off)

]

2

For example, if we select the gate-to-source voltage, Vgs = Vgs(off)/4, then the value of the drain current will be ID = IDSS {1 – 0.25}2 = IDSS (0.75)2 = 0.56 IDSS Here, the drain current is slightly more than one-half of IDSS. But it will bias the JFET close to the midpoint of the curve. The value of the drain resistor, RD, is selected in such a way that the drain voltage, VD, is equal to half the drain supply voltage, RD. The value of gate resistor, RG, is chosen arbitrarily large, so that it prevents loading on the driving stages. A self-bias line is drawn such that it intersects the transfer characteristic curve near its mid-point gives the required Q-point. Then the co-ordinates of the Q-point are obtained. The value of source resistance, Rs, is expressed by the ratio of gate-to-source voltage, Vgs, to the drain current, ID. Therefore, the source resistance is given by Vgs Rs = ___ ID However, a more accurate method is to draw a self bias line through the co-ordinates of IDSS and Vgs(off) as shown in Fig.7.14. Then the point of intersection of self-bias line and the transfer characteristic curve locates the Q-point. The value of the source resistor is expressed by the relation Vgs(off) RS =_______ IDSS The value of drain resistor, RD, and the gate resistor, RG, are selected in the same way as discussed above for the analytical method. An FET may have a combination of self bias and fixed bias to provide stability of the quiescent drain current against device and temperature variations.

Figure 7.15 shows the self-bias circuit for an N-channel FET. When the drain voltage VDD is applied, a drain current ID flows even in the absence of gate voltage (VG). The voltage drop across resistor Rs produced by the drain current is given by Vs = ID Rs. This voltage drop

reduces the gate to source reverse voltage required for FET operation. The feedback resistor Rs prevents any variation in FET drain current. The drain voltage,

VD = VDD – ID RD

The drain-to-source voltage, VDS = VD – Vs = (VDD – ID RD) – ID Rs = VDD – ID(RD + Rs) The gate-to-source voltage Vgs = VGG – Vs = 0 – ID Rs = – IDRs When drain current increases, the voltage drop across Rs increases. The increased voltage drop increases the reverse gate to source voltage, which decreases the effective width of the channel and hence, reduces the drain current. Now the reduced drain current decreases the gate to source voltage which, in turn, increases the effective width of channel thereby increasing the value of drain current.

Figure 7.16(a) shows the voltage divider bias circuit and its Thevenin’s equivalent is shown in Fig. 7.16(b). Resistors R1 and R2 connected on the gate side forms a voltage divider. The gate voltage,

(

)

R2 VGG = _______ VDD R 1 + R2

and

R 1R 2 RG = _______ R1 + R2

The bias satisfies the equation Vgs = VGG – IDRs. The drain to ground voltage, VD = VDD – IDRD. If the gate voltage VGG is very large as compared to gate to source Vgs, the drain current is approximately constant. In practice, the voltage divider bias is less effective with JFET than BJT. This is because, in BJT, VBE 0.7 (silicon) with only minor variations from one transistor to another. But in a JFET, the Vgs can vary several volts from one JFET to another.

The FET device needs d.c. bias for setting the gate to source voltage Vgs to give desired drain-current ID. For a JFET, the drain current is limited by IDSS. Since the FET has a high input impedance, it does not allow the gate current to flow and the dc voltage of the gate set by a voltage divider or a fixed battery is not affected or loaded by the FET. The fixed bias circuit for an N-channel JFET shown in Fig. 7.17 is obtained by using a supply VGG. This supply ensures that the gate is always negative with respect to source and no current flows through resistor RG and gate terminal i.e. IG = 0. The VGG supply provides a voltage Vgs to bias the N-channel JFET, but no resulting current is drawn from the battery VGG. Resistor RG is included to allow any ac signal applied through capacitor C to develop across RG. While any ac signal will develop across RG, the d.c. voltage drop across RG is equal to IGRG which is equal to zero volt. Then, the gate to source voltage Vgs is Vgs = VG – Vs = –VGG – 0 = –VGG The drain-source current ID is then fixed by the gate-source voltage. This current will cause a voltage drop the drain resistor RD and is given as VDD = ID RD + VDS VDD – VDS ID = __________ RD

Figure 7.18 shows the drain-to-gate bias circuit for enhancement mode MOSFET. Here, the gate bias voltage is R1 Vgs = _______ VDS R 1 + Rf

[

–VDD

]

This circuit offers the d.c. stabilisation through the feedback resistor Rf . However, the input resistance is reduced because of Miller effect. Also, the voltage divider biasing technique given for JFET can be used for the enhancement MOSFET. Here, the d.c. stability is accomplished by the d.c. feedback through Rs. But the self-bias technique given for JFET cannot be used for establishing an operating point for the enhancement MOSFET because the voltage drop across Rs is in a direction to reverse-bias the gate and it actually needs forward gate bias.

RD Rf

D

VGG G

R1

S

Figure 7.19 shows an N-channel enhancement mode MOSFET common source circuit with source resistor. The gate voltage is R2 VG = VGS = _______ (VDD) R1 + R2

(

)

and the gate-to-source voltage is Vgs = VDD – VG Assuming that Vgs > VTN and the MOSFET is biased in the saturation region, the drain current is ID = KN(Vgs – VTN)2 Here the threshold voltage VTN and conduction parameter KN are functions of temperature. The drain-to-source voltage is VDS = VDD – IDRD If VDS > VDS (sat) = Vgs – VTN, then the MOSFET is biased in the saturation region. If VDS < VDS (sat) = Vgs – VTN, then the MOSFET is biased in the non-saturation region, and the drain current is given by ID = KN [2(Vgs – VTN) VDS – V2DS]

Both the self-bias technique and voltage divider bias circuit given for JFET can be used to establish an operating point for the depletion mode MOSFET.

Calculate the operating point of the self biased JFET having the supply voltage VDD = 20 V, maximum value of drain current IDSS = 10 mA and Vgs = – 3 V at ID = 4 mA. Also, determine the values of resistors RD and Rs to obtain this bias condition.

Solution

We know that the value of drain current at Q-point,

IDSS 10 × 10–3 IDQ = ____ = ________ = 5 mA 2 2 and the value of drain-to-source voltage at Q-point, VDD 20 VDSQ = ____ = ___ = 10 V 2 2 Therefore, the operating point is at VDS = 10 V and ID = 5 mA. Also, we know that the drain-to-source voltage, VDS = VDD – IDRD 10 = 20 – (4 × 10–3) RD

20 – 10 RD = _______ = 2.5 kW 4 × 10–3 The source voltage or voltage across the source resistor Rs is Therefore,

Vs = –Vgs = –3 V 3 = ( 4 × 10–3) Rs

Also,

Vs = IDRs i.e.

Therefore,

3 Rs = _______ = 750 W 4 × 10–3

Calculate the values of Rs required to self bias an N-channel JFET with IDSS = 40 mA, VP = – 10 V and VGSQ = – 5 V.

Solution

[

Vgs We know that ID = IDSS 1 – ___ VP

]

2

Substituting the given values, we get

[

]

(–5) 2 ID = 40 × 10–3 1 – _____ = 10 mA (–10)

| |

VDSQ 5 Rs = _____ = ________ = 500 W ID 10 × 10–3

Therefore,

A JFET amplifier with a voltage divider biasing circuit, shown in Fig. 7.13, has the following parameters: VP = – 2 V, IDSS = 4 mA, RD = 910 W, Rs = 3 kW, R1 = 12 MW, R2 = 8.57 MW and VDD = 24 V. Find the value of the drain current ID at the operating point. Verify whether the FET will operate in the pinch-off region.

Solution

We obtain R2 8.57 × 106 VGG = VDD _______ = 24 _______________6 = 10 V R1 + R2 (12 + 8.57) × 10

We know that

(

Vgs ID = IDSS 1 – ___ VP

2

)

(

)

VGG – ID Rs = IDSS 1 – __________ , where Vgs = VGG – ID Rs VP Expressing ID and IDSS in mA, we have

(

i.e., Therefore,

10 – ID × 3 ID = 4 × 1 – __________ –2 9I2D – 73ID + 144 = 0

2

)

ID = 3.39 mA or 4.72 mA

As ID = 4.72 mA > 4 mA = IDSS, this value is inappropriate. So, IDQ = 3.39 mA is selected. Therefore, VGSQ = VGG – IDQRs = 10 – (3.39 × 10–3 × 3 × 103) = – 0.17 V and

VDSQ = VDD – IDQ (RD + Rs) = 24 – 3.39 × 10–3 (0.91 + 3) × 103 = 10.745 V

Then

VDGQ = VDSQ – VGQS = 10.745 + 0.17 = 10.915 V

which is greater than |VP | = 2 V. Hence, the FET is in the pinch-off region.

A voltage divider bias is provided to an N-channel JFET circuit as shown in Fig. 7.20. To establish IDSS = 10 mA, VP = –3.5 V, R1 + R2 = 120 kW, ID = 5 mA and VDS = 5 V, determine the values of R1, R2 and RD.

Solution is given by

Let us assume that the JFET is biased in the saturation region. Then the d.c. drain current

(

Vgs ID = IDSS 1 – ___ VP

Therefore,

(

2

) )

Vgs 5 = 10 1 – ______ (–3.5)

2

By solving, we get Vgs = –1.008 V The voltage at the source terminal is Vs = IDRs – 5 = (5) (0.5) – 5 = –2.5 V The gate voltage is VG = Vgs + Vs = –1.008 – 2.5 = –3.508 V The gate voltage can be written as

(

)

R2 VG = _______ (10) – 5 R1 + R2 Therefore,

R2 –3.508 = ____ (10) – 5 120

i.e.,

R2 = 2.984 kW

and

R1 = 17.016 kW

The drain-to-source voltage is VDS = 5 – IDRD – IDRs – (–5) Substituting the specified values, we get 10 – VDS – ID Rs 10 – 5 – (5) (0.5) RD = ______________ = ______________ = 0.5 kW 5 Vgs – VP = –1.24 – (–3.5) = 2.26 V

Here, since VDS > (Vgs – VP), the JFET is biased in the saturation region, which satisfies the initial assumption.

For the circuit shown in Fig. 7.21, find the values of VDS and Vgs. Given, ID = 5 mA, VDD = 10 V, RD = 1 K and Rs = 500 .

Solution

VGG = Vgs + IDRs

Since

VGG = 0, Vgs = – IDRs = – 5 × 10–3 × 500 = – 2.5 V

We know that VDD = ID(RD + Rs) + VDS Therefore,

VDS = VDD – ID(RD + Rs) = 10 – 5 × 10–3 (1500) = 2.5 V

For the common-source N-channel MOSFET circuit shown in Fig. 7.22 with the threshold voltage VTN = 1.5 V, conduction parameter KN = 1 mA/V2, the channel-length modulation parameter = 0.01 V–1, Ri = R1 || R2 = 100 k and the current at the transition point IDt = 4 mA. Design the MOSFET circuit with voltage divider bias such that IDQ = 1.5 mA and Q-point is in the middle of the saturation region.

Solution To determine VDSt : We know that IDt = 4 = KN (VGst – VTN)2 = 1 (VGSt – 1.5)2

VDD = 12 V

RD

where the subscript t indicates transition point values. Solving, we get VGSt = 3.5 V Therefore, VDSt = VGSt – VTN = 3.5 – 1.5 = 2 V

R1

V CC

If the Q-point is in the middle of the saturation region, then VDSQ = 7 V, which gives 10 V peak-to-peak symmetrical output voltage. From Fig. 7.20,

Vi

R2

VDSQ = VDD – IDQRD

Therefore,

VDD – VDSQ 12 – 7 RD = ___________ = ______ = 3.33 k IDQ 1.5

Then

IDQ = 1.5 = KN (VGSQ – VTN)2

Therefore,

VGSQ

Then,

VGSQ

= (1) (VGSQ – 1.5)2 = 2.73 V R2 1 = 2.73 = _______ (VDD) = ___ R1 + R2 R1

(

)

ID = 2 mA

(V ( ) ( _______ R +R ) R1 R2 1

2

DD)

Ri (100 × 103) (12) 2.73 = ___ (VDD) = ______________ R1 R1 By solving, we get

R1 = 439.6 k

and R2 = 129.45 k

For the N-channel depletion mode MOSFET circuit shown in Fig. 7.23. VTN = –2 V and KN = 0.1 mA/V2. Assume that VDD = 5 V and Rs = 5 k . Determine ID and VDS.

Solution

Let us assume that the MOSFET is biased in the satura-

tion region. Then the d.c. drain current is ID = KN (Vgs – VTN)2 = KN (–VTN)2 = (0.1) (–(–2))2 = 0.4 mA The d.c. drain-to-source voltage is VDS = VDD – IDRs = 5 – (0.4)(5) = 3 V Then,

VDS(sat) = Vgs – VTN = 0 – (–2) = 2 V

Since VDS > VDS(sat), the MOSFET is biased in the saturation region.

Determine the following for the network shown in Fig. 7.24. (iv) VG (v) Vs (i) VGSQ (ii) VDS (iii) VD 35 V (VDD)

Solution (i) VGSQ = – VGG = – 3V (ii) IDQ = IDSS

[

]

RD

Vgs 2 –3 1 – ___ = 12 × 10–3 1 – ___ VP –6

[ ( ) ] = 3 mA

3.5 kW

2

D IDSS = 12 mA VP = – 6V

G

VDS = VDSQ = VDD – IDQRD = 35 – 3 × 10–3 × 3.5 × 103 = 24.5 V (iii) VD = VDS + Vs = 24.5 + 0 = 24.5 V (v) VS = 0 V

(iv) VG = – 3V

2 MW

VGG

3V

Determine IDQ, VGSQ, VD, VDS, and VDG for the given network shown in Fig. 7.25.

Solution

To find expression for VGS : R2 270 Vgs = ________ × VDD = ___________ × 20 = 2.28 V R1 + R2 (2100 + 270)

S

Vs = 1.5 ID

25 V

Therefore, Vgs = VG – Vs = (2.28 – 1.5 ID) To find ID : ID = IDSS

[

4.7 kW

]

Vgs 2 1 – ___ mA VP

[

2.1 MW

VD

]

(2.28 – 1.5 ID) 2 ID = 8 1 – ____________ mA 4 8 Therefore, ID = ___ [4 + 2.28 – 1.5 ID]2 = 0.5 (6.28 – 1.5 ID)2 16 2ID = 39.44 – 18.84 ID + 2.25 I2D

10 mF

VG

IDSS = 8 mA VD = –4 V

Vs 270 kW 1.5 kW

20 mF

2.25 I2D – 20.84 ID + 39.44 = 0

________________________

20.84 ± ÷(20.84)2 – (4 × 2.25 × 39.44) Therefore, ID = ________________________________ = 6.6 mA or 2.6 mA 2 × 2.25 For ID = 6.6 mA, VDS is negative and hence this value may be neglected. Let us choose ID = 2.65 mA. Therefore, IDQ = 2.65 mA. To find VGSQ : VGSQ = 2.28 – 1.5 IDQ = 2.28 – (1.5 × 2.65) = – 1.695 V To find VDSQ : VDSQ = VDD – IDQ(RD + Rs) VDSQ = 20 – 2.65 × 10–3 (4.7 + 1.5) × 10–3 = 3.57 V

Therefore, To find VD Vs and VDG :

Vs = IDRs = 2.65 × 10–3 × 1.5 × 10–3 = 3.975 V VD = Vs + VDS = 3.975 + 3.57 = 7.545 V VDG = VD – VG = 7.545 – 2.28 = 5.265 V

Hence,

For the given measurement Vs = 1.7 V for the network as shown in Fig. 7.26, determine (i) IDQ

(ii) VGSQ

(iii) IDSS

(iv) VD

(v) VDS

Solution (i)

Given Vs = 1.7 V Vs = IDRs Vs 1.7 IDQ = ___ = ____ = 3.33 mA Rs 510

(ii)

VGSQ = VG – Vs = – Vs = – 1.7 V

(

Vgs ID = IDSS 1 – ___ VP

(iii)

2

)

ID 3.33 × 10–5 IDSS = _________2 = ___________2 = 10 mA Vgs (–1.7) 1 – ______ 1 – ___ (–4) VP

(

)

VD = VDD – IDRD = 18 – 3.33 × 10–3 × 2 × 103 = 11.34 V

(iv) (v)

) (

VDS = VD – Vs = 11.34 – 1.7 = 9.64 V

For a circuit shown in Fig. 7.27, calculate V0, Zi and Z0. Given input is V1 = 0.2 V(rms). IDSS = 9 mA and VP = – 4.5 V.

Solution

Zi = RG = 10 MW

(

Vgs ID = IDSS 1 – ___ VP

2

)

(

–IDRs = 9 × 10–3 1 – ______ VP

2

)

(–1000 ID) 2 = 9 × 10–3 1 – _________ – 4.5 = 9 × 10–3 (1 – 222.22 ID)2

(

)

= 9 × 10–3(1 – 444.44 ID + 49383I D2 ) ID = 9 × 10–3 – 4ID + 444.45 I2D Therefore, 444.45 I2D – 5ID + 9 × 10–3 = 0 Solving the quadratic equation, we get ID = 2.25 mA or 9 mA Since ID < IDSS, we take ID = 2.25 mA. Therefore, 2IDSS 2 × (9 × 10–3) gmo = _____ = ____________ = 4 mS 4.5 |VP|

(

VGSQ gm = gmo 1 – _____ VP

)

where VGSQ = – IDRs = – 2.25 × 10–3 1000 = – 2.25 V (2.25) gm = 4 × 10–3 1 – ______ = 2 mS (4.5)

(

)

1 1 _______ 3 Zo = ___ gm || Rs = 2 × 10–3 || 1 × 10 = 333.33W

gm(rd || Rs) gm Rs 2 × 10–3 × 1 × 103 AV = _____________ = _________ = ____________________ = 0.667 1 + gm(rd || Rs) 1 + gm Rs 1 + (2 × 10–3 × 1 × 103) Vo = Vi × AV = 0.2 × 0.667 = 0.133 V

An N-channel JFET having VP = – 4 V and VDSS = 10 mA is used in the circuit of Fig. 7.28. The parameter values are VDD = 18 V, Rs = 2k , R1 = 450 k , and R2 = 90 k . Determine ID and VDS.

Solution

To find VGS : Vgs = VG – ID Rs R2 90 × 103 VG = _______ × VDD = ______________3 × 18 = 3 V R1 + R2 (450 + 90) × 10

Therefore,

Vgs = (3 – 2 × 103 ID)

To find ID : ID = IDSS

[

]

[

Vgs 2 (3 – 2 × 103 ID) ___ _____________ –3 1– = 10 × 10 1 – VP –4

]

2

10 × 10–2 = ________ [4 + 3 – 2 × 103 ID]2 16 –3 Therefore, 1.6 ID = 10 [7 – 2 × 103 ID]2 = 0.049 – 28 ID + 4 × 103 I2D 4 × 103 I2D – 29.6 ID + 0.049 = 0

_________________________

29.6 ± (29.6)2 – 4 × 4 × 103 × 0.049 ID = ________________________________ 2 × 4 × 103 Therefore, ID = 4.9 mA or 2.5 mA If ID = 4.9 mA, then VDS would be negative and hence this is not acceptable. Therefore,

IDQ = 2.5 mA

To find VDS : VDS = VDD – IDQ(RD + Rs) = 18 – 2.5 × 10–3 (2 + 2) × 103 = 8 V

Determine Vgs, ID, VDS , VD and VG for the circuit shown in Fig. 7.29.

Solution

To find VGSQ :

For a self bias circuit, VGSQ = – IDRs = – ID × 103 To find ID :

[

[

]

Vgs 2 (1 × 103 ID) ID = IDSS 1 – ___ = 8 × 10–3 1 + __________ VP –6

[

20 V

2

3.3 kW

]

2

1000 ID = 8 × 10–3 1 – _______ 6 –3

]

D IDSS = 3 mA VP = – 6 V

G

2

Therefore, 36 ID = 8 × 10 [6 – 1000 ID]

S

= 8 × 10–3 [36 – 12 × 103 ID + 106 I2D] = 8 × 103 I2D – 132ID + 0.288 = 0

1 kW

1 MW

________________________

132 ± ÷(132)2 – 4 × 8 × 103 × 0.288 ID = ______________________________ 2 × 8 × 103 Therefore,

ID = 13.9 mA or 2.5 mA

But ID cannot be higher than IDSS, Therefore, ID = 4.225 mA To find VDS : VDS = VDD – ID(RD + Rs) = 20 – 2.5 × 10–3(3.3 + 1) × 103 = 9.25 V To find Vgs, VD and Vs : Vgs = 1 × 103 × ID = 1 × 103 × 2.5 × 10–3 = 2.5 V Vs = IDRs = 2.5 × 10–3 × 1 × 103 = 2.5 V VD = Vs + VDS = 2.5 + 9.25 = 11.75 V

Determine the following for the network shown in Fig. 7.30 – VGSQ, VDQ, VD, VG, Vs and VDS .

Solution

VG = 0, Vs = IDRs

12 V

Vgs = VG – Vs = 0 – IDRs = – 680 ID To find ID :

(

Vgs We know that ID = IDSS 1 – ___ VP

2

)

( (

–680 ID = 12 × 10–3 1 – _______ –6

= 152.6 I2D – 2.7 ID + 0.01

_____________________

Therefore,

2.7 ± ÷(2.7)2 – 4 × 152.6 × 0.01 ID = ___________________________ 2 × 152.6 = 12.4 mA or 5.28 mA

Since ID is less than IDSS, IDQ = 5.28 mA To find VGSQ : VGSQ = – 680 ID = – 680 × 5.28 × 10–3 = –3.6 V

1.5 kW 10 mF

2

))

D G

Vo IDSS = 3 mA, VP = – 6V 10 mF

V1

S 680 W

To find Vs :

Vs = IDRs = 5.28 × 10–3 × 680 = 3.6 V

To find VDS : VDS = VDD – ID(RD + Rs) = 12 – 5.28 × 10–3 ( 1.5 × 103 + 680 ) = 12 – 11.51 = 0.49 V To find VD : VD = Vs + VDS = 3.6 + 0.49 = 4.09 V

A Charge Transfer Device (CTD) is a semiconductor structure in which discrete charge packets are removed. It finds wide applications in shift registers, imaging systems, dynamic memories and high speed filtering. There are two main methods of constructing CTD, namely, (i) Charge-Coupled Device (CDD), and (ii) Bucket Brigade Device (BBD).

A Charge-Coupled Device (CCD) is a shift register formed by a string of closely spaced MOS capacitors. A CCD can store and transfer analog signals, either electrons or holes, which may be introduced electrically or optically. A cross-sectional view of a three-phase charge-coupled device (CCD) is illustrated in Fig. 7.31. The structure consists of a series of metal gate electrodes, separated from a P- (or an N-) type semiconducting silicon substrate (for an N-channel device) by a thin silicon dioxide layer. On top of the silicon dioxide is an array of metallised electrodes which are connected to signal voltages V1, V2 and V3. +10 V

Aluminium gate electrodes

Injected electrons

G1

G2

G3

P type silicon

G4

G5

etc.

SiO2 layer

Depletion layer

A three-phase clocked voltage pulse system supplied to the gates ensures that the charge is transferred serially between gates and its direction is controlled, as given below. The first phase connects a positive voltage V1, say +10 V, to G1, where V1 is greater than either V2 or V3, a depletion layer is

formed, in typically less than 1 ms. This produces the potential well into which information, in the form of minority electrons, is stored. During the second phase, the adjacent gate G2 is biased to a greater positive voltage V2, say +15 V, to produce a deeper well under it as shown in Fig. 7.32(a). The stored charge then transfers into the deeper potential well by diffusion down the potential gradient, which incidentally can be a relatively slow process. In order to ensure the charge transfer, the potential wells must physically overlap. As depletion layers are typically only a few micrometers deep, the spacing between neighbouring gates must be as small as possible, to ensure sufficient overlap. The charge is then completely stored in the well under G2 and hence, the voltage on G1 is reduced to a low value, say +5 V and that on G2 to a sustaining level of say +10 V as shown in Fig. 7.32(b). A third-phase transfers a +15 V voltage pulse to the next gate G3 and the charge is transferred from G2 to the well under it, as shown in Fig. 7.32(c). The voltages on G2 and G3 can be relaxed as before as shown in Fig. 7.32(d), to complete one cycle of the clock frequency. The charge has been transferred from under G1 to under G3 in one cycle of the clocked three-phase pulse which causes a series of voltages in the sequence of +15, +10, +5, +15, etc., to be applied to each gate electrode. In this manner, the charge in the substrate is transferred under one electrode to the next, and so on. Here each storage cell of three adjacent of three electrodes accommodates the bit of information. As soon as charge is moved out of one set of three electrodes, say from G3 to G4, then the input gate is again put in a state to receive a further bit of information. The CCD structure thus behaves as a dynamic shift register, and charge has to be transferred to less than 1 ms. This process is only possible provided the charge is not stored in any well for long time for an inversion layer to form, in which case the charge would disappear and the corresponding information will be lost. G1

G2

+10 V

G1

+15 V

Stored electrons transfer

G2

+15 V

Deeper potential well

+10 V

Stored electrons

(a)

G1 +5 V

(b)

G2 +10 V

G3 +15 V

Change transfers (c)

G1 +5 V

G2 +5 V

G3 +10 V

Electrons temporarily stored before moving to G4 etc. (d)

The CCD can be used as memories by storing charge corresponding to full and empty wells (1 and 0). However, as the charge storage is limited to the storage time of the associated capacitor, the charge has to be periodically refreshed. The commercial CCDs can transfer up to 20 MHz. In solid-state imaging, the light may be shone in the CCD, either from the top or the bottom, through a tinned substrate. There may be a separate photosensing element which is connected to the CCD. When the incident light falls on the CCD, it generates charge in the depletion region, which is proportional to the intensity of light incident at that point. This is the signal charge which can be shifted out by suitable clocking pulses for further processing. A matrix version of a CCD operated in this mode has considerable potential in the imaging field and a solid-state colour TV camera. The CCD finds application as a dynamic shift register in computers and in solid-state imaging, such as video cameras. CCD is used in photosensor arrays and such signal processing components as variable delay lines and signal correlators. In delay lines, the time delay Td, can be electronically varied over a wide range by varying the clock frequency fc. For an N-bit CCD, Td = N/fc. The CCDs offer longer delays than Surface Acoustic Wave (SAW) devices. The delay line can be used as building block for analog signal processing applications like transversal filters, recursive filters, pulse compressors and pulse expanders. The packing density (the number of devices occupying the substrate) is in the order of 100 times as great as for the other semiconductor devices. The CCD consumes very little power and is capable of operating at high frequencies.

Bucket Brigade Devices (BBDs) are formed by connecting a series of capacitors with switches, generally FET. A single storage element consists of two capacitor-switch units. The BBD operates on the basis of charge transfer to the adjacent wells. The BBD structure consists of a series of MOS transistors (MOSFET) as shown in Fig. 7.33, in which the drain of the first transistor acts as the source of the adjacent transistor and so on. In a P-channel BBD, the source and drain regions are P+ regions and left floating, except at the input and output and thus act as the reservoirs of charge. The device is structured such that the capacitance C associated with the left hand cell L is much larger due to the larger gate overlap than that of the right hand cell R, i.e., CL > > CR. Assume at time t0, when all channels are OFF, a signal charge is stored in a diffused region L, charging it to a potential V0. Q = CLV0 If L has no charge to start with, no charge transfer will take place. At t1, the phase F1 is high and F2 is low. The charge transfer takes place from all odd numbered diffused regions to even numbered diffused regions, as shown in Fig. 7.34. In other words, all odd numbered diffused regions behave like L-type regions and transfer charge to the even numbered regions R. When F1 comes ON, cells L and R get connected. Since CL >> CR, QL Æ 0, the charge flow will continue till the left hand cell L contains practically no charge. At t2, all channels are OFF and a large potential barrier exists preventing any carrier flow. At t3, the phase F2 is high and F1 is low. Hence, all even numbered regions behave like L-type region and transfer charge to the R-type regions. One pair of even and odd numbered regions constitute a bit or a cell. The charge transfer takes place only from L to R and not from R to L, since there is always a potential barrier between them. During one complete clock period T, charge is transferred by one bit.

F1

1

P

F2

+

D1

P

S1 2

F3

+

S2 3

D2

P

F4

F5

+

4

5

6

P-Si (a) Structure of the BBD

t = t0

ys

L

R

L

R

L

R

t = t1

ys

t = t2 ys

t = t3 R

L

R

L

R

L

(b) Charge transfer in BBD with 2f clock

t f1

t0 t1

t2

t3

t

f2

(c) Non-overlapping 2f clock waveforms

BBDs normally operate at lower maximum frequencies than CCDs because the transfer speed is limited by the charge flow through the channel. BBDs have a large cell area. Since small interelectrode spacings are not required, the fabrication process is relatively simple. BBDs are used in areas such as audio delay lines to implement reverberation. Modern commercial BBDs can transfer at 1 MHz. Integration density and performance are better in a CCD structure.

÷

Thyristor, in general, is a semiconductor device having three or more junctions. Such a device acts as a switch without any bias and can be fabricated to have voltage ratings of several hundred volts and current ratings from a few amperes to almost thousand amperes. The family of thyristors consists of PNPN diode (Shockley diode), SCR, LASCR, TRIAC, DIAC, GTO, etc.

As shown in Fig. 8.1, it is a four layer PNPN silicon device with two terminals. When an external voltage is applied to the device in such a way that anode is positive with respect to cathode, junctions J1 and J3 are forward biased and J2 is reverse biased. Then the applied voltage appears across the reverse biased junction J2. Now the current flowing through the device is Anode (A) Anode only reverse saturation current. However, as this applied voltage is increased, the current increases slowly until the so called firing or breakover voltage (VBO) is reached. Once firing takes place, the current increases abruptly and the voltage drop across the device decreases sharply. At this point, the diode switches over from ‘OFF’ to ‘ON’state. Once the device is fired into conduction, a minimum amount of current known a holding current, IH, is required to flow to keep the device in ON state. To turn the device OFF from ON state, the current has to be reduced below IH by reducing the applied voltage close to zero, i.e. below holding voltage, VH. Thus the diode acts as a switch during forward bias condition. The characteristic curve of a PNPN diode is shown in Fig. 8.2.

J1 J2 J3

P1 N1 P2 N2

Cathode (K)

Cathode

Forward current

Reverse voltage

Saturation region

IH(mA)

Negative resistance region

IBO(mA)

Cut-off region VH

VBO

Forward voltage

Avalanche breakdown Reverse current

The basic structure and circuit symbol of SCR is shown in Fig. 8.3. It is a four layer three terminal device in which the end P-layer acts as anode, the end N-layer acts as cathode and P-layer nearer to cathode acts as gate. As leakage current in silicon is very small compared to germanium, SCRs are made of silicon and not germanium. Anode (A)

A P1 J1 N1 J2 Gate (G)

P2 J3 N2 G

K

Cathode (K) (a) Basic structure

(b) Circuit symbol

The characteristics of SCR are shown in Fig. 8.4. SCR acts as a switch when it is forward biased. When the gate is kept open, i.e. gate current IG = 0, operation of SCR is similar to PNPN diode. When IG < 0, the amount of reverse bias applied to J2 is increased. So the breakover voltage VBO is increased. When IG > 0, the amount of reverse bias applied to J2 is decreased thereby decreasing the breakover voltage. With very large positive gate current, breakover may occur at a very low voltage such that the characteristics of SCR is similar to that of ordinary PN diode. As the voltage

at which SCR is switched ‘ON’ can be controlled by varying the gate current IG, it is commonly called as controlled switch. Once SCR is turned ON, the gate loses control, i.e. the gate cannot be used to switch the device OFF. One way to turn the device OFF is by lowering the anode current below the holding current IH by reducing the supply voltage below holding voltage VH, keeping the gate open.

Forward current

IG > o IG = o IG < o

IHO With large

IBO IG VH VBO Forward voltage

Reverse voltage Avalanche breakdown

SCR is used in relay control, motor control, phase control, heater control, battery chargers, inverters, regulated power supplies and as static switches.

Reverse current

The operation of SCR can be explained in a very simple way by considering it in terms of two transistors, called as the two transistor version of SCR. As shown in Fig. 8.5, an SCR can be split into two parts and displaced mechanically from one another but connected electrically. Thus the device may be considered to be constituted by two transistors T1 (PNP) and T2 (NPN) connected back to back. T1 B

E JE

C JC

G Ie1

N1

P2

IC1

Ig

T1

Ib2 P1

Ie2

T2 JC N1

JE P2

Ib1 = IC2

Ik

IA

N2

A C

B T2

K

E

Assuming the leakage current of T1 to be negligibly small, we obtain Ib1 = IA – Ic1 = IA –

1IA

= (1 –

1) IA

(8.1)

Also, from the Fig. 8.5, it is clear that and

Ib1 = IC2

(8.2)

IC2 =

(8.3)

2IK

Substituting the values given in Eqs (8.2) and (8.3) in Eq. (8.1), we get

(1 – a1) IA = a2IK We know that

(8.4)

I K = IA + Ig

(8.5)

Substituting Eq. (8.5) in Eq. (8.4), we obtain (1 – a1) IA = a2 (IA + Ig) i.e. i.e.

(1 – a1 – a2)IA = a2Ig

[

a2Ig IA = ___________ 1 – (a1 + a2)

]

(8.6)

Equation (8.6) indicates that if (a1 + a2) = 1, then IA = •, i.e. the anode current IA suddenly reaches a very high value approaching infinity. Therefore, the device suddenly triggers into ON state from the original OFF state. This characteristic of the device is known as its regenerative action. The value of (a1 + a2) can be made almost equal to unity by giving a proper value of positive current Ig for a short duration. This signal Ig applied at the gate which is the base of T2 will cause a flow of collector current IC2 by transferring T2 to its ON state. As IC2 = Ib1, the transistor T1 will also be switched ON. Now, the action is regenerative since each of the transistors would supply base current to the other. At this point even if the gate signal is removed, the device keeps on conducting, till the current level is maintained to a minimum value of holding current.

Latching current is the minimum current required to latch or trigger the device from its OFF-state to its ON-state. Holding current is the minimum value of current to hold the device in ON-state. For turning the device OFF, the anode current should be lowered below IH by increasing the external circuit resistance. Gate current is the current applied to the gate of the device for control purposes. The minimum gate current is the minimum value of current required at the gate for triggering the device. The maximum gate current is the maximum value of current applied to the device without damaging the gate. More the gate current, earlier is the triggering of the device and vice-versa. Voltage safety factor Vf is a ratio which is related to the PIV, the RMS value of the normal operating voltage as, peak inverse voltage (PIV) __ Vf = __________________________________ ÷2 × rms value of the operating voltage The value of Vf normally lies between 2 and 2.7. For a safe operation, the normal working voltage of the device is much below its PIV.

SCRs are much superior in performance than ordinary diode rectifiers. They find their main applications as rectifiers. Some of the rectifier circuits have been explained in the following sections.

Though the SCR is basically a switch, it can be used in linear applications like rectification. Fig. 8.6 shows the circuit of an SCR half wave rectifier. During the negative halfcycle, the SCR does not conduct irrespective of the gate current, as the anode is negative with respect to cathode and also PIV is less than the reverse breakdown voltage. During the positive half cycle of a.c. voltage appearing across secondary, the SCR will conduct provided proper gate current is made to flow. The greater the gate current, the lesser the supply voltage at which the SCR is triggered ON. Referring to Fig. 8.6(b), the gate current is adjusted to such a value that SCR is turned ON at a positive voltage V1 of a.c. secondary voltage which is less than the peak voltage Vm. Beyond this, the SCR will be conducting till the applied voltage becomes zero. The angle at which the SCR starts conducting during the positive half cycle is called firing angle q. Therefore, the conduction angle is (180° – q).

Trigger circuit

SCR

a.c. input

RL

V0

(a) V0

Vm V1

The SCR will block not only the negative part of the applied sinusoidal voltage, but will also block the part of the 0 positive waveform up to a point SCR is p q q triggered ON. If the angle q is zero, this (b) will be an ordinary half wave rectification. Therefore by proper adjustment of gate current, the SCR can be made to conduct full or part of a positive half cycle, thereby controlling the power fed to the load.

wt

Let V = Vm sin wt be alternating voltage that appear across the secondary of the transformer. In SCR halfwave rectifier. q is the firing angle and the rectifier conducts from q to 180° (p radians) during the positive half cycle. p 1 Therefore, average or d.c. output, Vav = ___ Ú Vm sin wt dwt 2p q 1 = ___ [– Vm cos wt]pq 2p Vm = ___ (1 + cos q) 2p

Vm For q = 0°, Vav = ___ p . Here the full positive half cycle will appear across the load. This is the value of average voltage for ordinary halfwave rectifier. Vm When q = 90°, Vav = ___. This shows that greater the firing angle q, the smaller is the average voltage 2p __________________ and vice-versa. p 1 Similarly, Vrms = ___ Ú (Vm sin wt)2 dwt 2p q

÷ ÷

____________________ p

V2m ___ = Ú (1 – cos 2 wt) dwt 4p q _________________

÷

V2m sin 2 wt = ___ wt – _______ 4p 2

[

p

]

q

Vm 1 = ___ __ (p – q + sin 2q) 2 p Vm = ___ 2

[

If q = 0, then

Vrms

]

1 __ 2

In an SCR half wave rectifier, the forward breakdown voltage of SCR is 110 V for a gate current of 1 mA. If a 50 Hz sinusoidal voltage of 220 V peak is applied, find firing angle, conduction angle, average voltage, average current, power output and the time during which SCR remains OFF. Assume load resistance is 100 W and the holding current to be zero.

Solution

We know that

V1 = Vm sin q 110 = 220 sin q

Therefore, firing angle,

i.e.

sin q = 0.5

–1

q = sin (0.5) = 30°

Conduction angle

= 180° – q = 180° – 30° = 150° Vm = ___ (1 + cos q) 2p 220 = ____ (1 + cos 30°) = 65.37 V 2p

Average voltage,

Vav

Average current,

Iav = Vav/RL = 65.37/100 = 0.6537 A

Power output

= Vav Iav = (65.37) (0.6537) = 42.7326 W

V1 = Vm sin q = Vm sin w t p w t = q = 30° = __ 6 p __ 2p × 50t = 6 Therefore, the time during which the SCR remains OFF is As

t = 1/(2 × 6 × 50) = 1/600 = 1.667 ms

SCR 1

The SCR full wave rectifier is shown in Fig. 8.7. It is exactly similar to an ordinary full wave rectifier except that the two diodes have been replaced by two SCRs. The angle of conduction can be changed by adjusting the gate currents.

a.c. input

RL

During the positive half cycle of the input signal, anode of SCR1 becomes positive and at the same time the anode of SCR2 becomes negative. When the input voltage reaches V1 as shown in Fig. 8.7(b), SCR1 starts conducting and therefore only the shaded portion of positive half cycle will pass through the load. During the negative half cycle of the input, the anode of SCR1 becomes negative and the anode of SCR2 becomes positive. Hence, SCR1 does not conduct and SCR2 conducts when the input voltage becomes V1. The main advantage of this circuit over ordinary full wave rectifier circuit is that any voltage can be made available at the output by simply changing the firing angle of the SCRs.

Trigger circuit

V0

SCR 2 (a)

Vo

Vm V1

0 q

q

wt

(b)

Referring to Fig. 8.7, let V = Vm sin t be the alternating voltage that appears between center tap and either end of secondary and be the firing angle. 1 Vav = __ Vm sin t d t Vm = ___ [– cos t] Vm = ___ [1 + cos ] This is double that of a half wave rectifier, as negative half cycle is also rectified.

A full wave controlled rectifier employs 2 SCRs and 2 diodes in bridge configuration to rectify 230 V, 50 Hz a.c. mains and give an output of 150 V to a resistive load of 10 . Find the firing angle, the time during which the SCR remains OFF and the load current.

Solution

For an SCR full wave rectifier, Vm Vd.c. = ___ p (1 + cos q) __

230 × ÷2 150 = ________ (1 + cos q) p q = 63.33°

Therefore, For 50 Hz, T = 20 ms for 360°

20 t = ____ × 63.33° = 3.52 ms 360° Vav 150 Iav = ___ = ____ = 15 A RL 10

Therefore Load current,

When an SCR full wave rectifier is connected across a sinusoidal voltage of 400 sin 314t, the RMS value of the current flowing through the device is 20 A. Find the power rating of the SCR.

Solution

As the supply voltage is 400 sin 314t, Vm = 400 V __

__

Peak inverse voltage (PIV) = ÷3 Vm = ÷3 × 400 = 692.8 V rms value of current = 20 A Average value of current, Iav = rms value/form factor = 20/1.11 = 18 A Power rating of the SCR = PIV × Iav = 692.8 × 18 = 12.47 kW

The SCR bridge rectifier is shown in Fig. 8.8. During the positive half cycle of the input a.c. voltage, SCR1 and diode D1 conduct whereas SCR2 and diode D2 do not conduct. During the negative half cycle, SCR2 and diode D2 conduct. As shown in Fig. 8.8(b), the conduction angle and hence the output voltage can be changed by adjusting the gate currents of SCR1 and SCR2. Here, the d.c. output voltage, Vm Vav = ___ p [1 + cos q], which is equal to that of SCR full wave rectifier. SCR2

D1 Trigger circuit

AC input SCR1

D2 RL

(a)

Vo

V0

Vm V1

0 q

p

wt

q (b)

If the current is lowered below IH by increasing the external circuit resistance, the SCR will switch OFF.

The LASCR shown in Fig. 8.9 is triggered by irradiating with light. The arrows represent incoming light that passes through a window and falls on the depletion layer closer to the middle junction J2 of SCR. The incident +VCC +VCC light generates electron-hole pairs in the device thus increasing the number of charge carriers. This leads to the instantaneous flow of current within the device and the device turns ON. For RL RL light triggering to occur, the device must have high value of rate of change of voltage with time, dV/dt.

TRIAC is a three terminal semiconductor switching device which can control alternating current in a load. Its three terminals are MT1, MT2 and the gate (G). The basic structure and (a) circuit symbol of a TRIAC are shown in Fig. 8.10. TRIAC is equivalent to two SCRs connected in parallel but in the reverse direction as shown in Fig. 8.11. So, a TRIAC will act as a switch for both directions. The characteristics of a Triac are shown in Fig. 8.12.

Trip level (b)

Like an SCR, a TRIAC also starts conducting only when the breakover voltage is reached. Earlier to that the leakage current which is very small in magnitude flows through the device and therefore remains in the OFF state. The device, when starts conducting, allows very heavy amount of current to flow through it. The high inrush of current must be limited using external resistance, or it may otherwise damage the device.

MT1

G

N

N P MT2

MT1

N G

N

P

MT2 (a)

(b)

+l 1

ON state

1 N

MT2 (+ve)

P OFF state

P N

N

P

SCR1

SCR2

–V

–VBO

–VH OFF state

ON state

2 (a)

IH

MT1 (+ve)

N

V +VBO

O VH

Gate N

IH

2 (b)

–l

During the positive half cycle, MT1 is positive with respect to MT2, whereas MT2 is positive with respect to MT1 during negative half cycle. A TRIAC is a bidirectional device and can be triggered either by a positive or by a negative gate signal. By applying proper signal at the gate, the breakover voltage, i.e. firing angle of the device can be changed; thus phase control process can be achieved. TRIAC is used for illumination control, temperature control, liquid level control, motor speed control and as static switch to turn a.c. power ON and OFF. Nowadays, the DIAC–TRIAC pairs are increasingly being replaced by a single component unit known as quadrac. Its main limitation in comparison to SCR is its low power handling capacity.

The construction and symbol of DIAC are shown in Fig. 8.13. DIAC is a three layer, two terminal semiconductor device. MT1 and MT2 are the two main terminals which are interchangeable. It acts as a bidirectional Avalanche diode. It does not have any control terminal. It has two junctions J1 and J2. Though the DIAC resembles a bipolar transistor, the central layer MT1 MT1 is free from any connection with the terminals. From the characteristic of a DIAC shown in Fig. 8.14, it acts as a switch in both directions. As the doping level at the two ends of the device is the same, the DIAC has identical characteristics for both positive and negative half of an a.c. cycle. During the positive half cycle, MT1 is positive with respect to MT2 whereas MT2 is positive with respect to MT1 in the negative half cycle. At voltage less than the breakover voltage, a very small amount of current called the leakage current flows through the device and the device remains in OFF state. When the voltage level reaches the breakover voltage, the device starts conducting and it exhibits negative resistance characteristics, i.e. the current flowing in the device starts increasing and the voltage across it starts decreasing.

N P J1 N J2 P

MT2 (a)

N

MT2

The DIAC is not a control device. It is used as triggering device in Triac phase control circuits used for light dimming, motor speed control and heater control. Forward current ON IBO

OFF

–VBO VBO

Reverse voltage

OFF

Forward voltage

IBO

ON Reverse current

Conventional thyristors are used as ideal switches in power electronic applications. They have the capability of blocking several thousand volts in the OFF-state and conducting several thousand amperes in the ON-state with only small ON-state voltage drop. The only disadvantage of conventional thyristor is that when the gate turns into ON-state, the gate loses its control on the device and hence its use in switch-mode applications is prevented. The only way

to bring the device back to OFF-state is by reducing the anode forward current to a level below that of the holding current. In order to speed up turn-OFF capability, the thyristor requires structural modifications and the performance compromises. This section discusses the structure and operation of Gate Turn-OFF Thyristor (GTO) that has turn-OFF capability. GTOs can be turned OFF by applying a negative gate current.

The GTO is a three terminal device with anode, cathode and gate terminals. The GTO has the same four layer structure as the conventional thyristor, but special modifications are made to the structure to enable the gate to turn-OFF the device. The operation of a GTO is very simple. Stopping the current through the gate can turn OFF the GTO. Injecting current into the gate as in the conventional thyristor can turn it ON. The GTO has a complex structure that enables such simpler operation of turning ON and OFF. Figure 8.15 gives the structure of a GTO.

Anode

P+

N

P+

N

P+

N

P+

N P

The GTO has highly doped N regions in the P-layer at the anode, the ‘+’ sign indicates a higher concentration of N or P type conductors. The major modifications include a highly interdigited gate cathode structure with small cathode and gate widths, the use of anode shorts, and a shorter carrier life time in the drift region than that in a conventional thyristor.

N+

N+

Gate

N+

Cathode

In GTO, during the absence of the gate current, a positive voltage at the anode with respect to the cathode, will reverse bias the N-P junction at the center of the device and as a result, no conduction occurs. A negative voltage at the anode and a positive voltage at the cathode will break down the anode junction at a low level. The interdigitated nature of the gate (i.e., the cathode and gate electrodes are arranged alternatively in a large number of closely located narrow channels) results in a very rapid spread of conduction in the silicon, but it is necessary to maintain the gate current at a high level for a longer time to ensure that latching takes place. To minimize the anode–cathode voltage drop, it is advantageous to maintain a low level of gate current throughout conduction, otherwise the ON-state voltage and hence conduction losses will be slightly higher. Applying a Anode single positive current pulse at the gate can turn ON a GTO thyristor, and a pulse of A A A negative gate current can turn it OFF. The PNP gate current therefore controls both ONstate and OFF-state operation of the device. Gate Gate turn-OFF thyristor should be proNPN G G G tected against over currents because the gate turn OFF current cannot exceed a specified maximum value. K K K The symbols of GTO are shown in Fig. 8.16. The two transistor analogy of GTO is shown in Fig. 8.17.

(i)

(ii)

(iii)

Cathode

When a positive pulse is applied to the base of NPN transistor, the GTO switches regeneratively into the ON-state. This pronounced regenerative latching effect enables the thyristor not to stay in ON-state at the gate. In GTO, internal regeneration is reduced by a reduction in the current gain of the PNP transistor, while by drawing sufficient current from the gate, turn-OFF can be achieved. When a negative pulse is applied to the gate, excess carriers are drawn from the base region of NPN transistor and the collector current of the PNP transistor is diverted into the external gate circuit. Thus, the base drive of the NPN transistor is removed, and which in turn removes the base drive of the PNP transistor and stops conduction. The reduction in gain of the PNP transistor can be achieved by either of the following two techniques or by the combination of both. One technique involves the diffusion of gold or other heavy metal to reduce carrier lifetime. The other technique is introduction of anode to N-base short-circuiting spots. Device characteristics depend on the technique used. The Golddoped GTO retains its reverse blocking capacity, and has a high ON-state voltage drop. On the other hand, the shorted anode emitter construction has a lower ON-state voltage, but it loses the ability + to block reverse voltage. Ed.c. T 1

–

GTO

A simplified gate drive circuit for a GTO with separate d.c. supplies for turn-ON and turn-OFF is shown in Fig. 8.18. The GTO is gated into conduction by transistor T1 in the turn-ON circuit. The switching device in the turn-OFF circuit should have a high peak current achieved by an auxiliary thyristor in the circuit. Thyristor initiates the turn-OFF programme. The inductor L will enhance the turn OFF performance. The energy required to turn OFF the GTO is much less than that needed to turn OFF a conventional thyristor.

The GTO has a faster turn-ON time than conventional thyristors because of its narrow emitter width. The delay time decreases as the gate current increases. The rise time does not vary as long as the gate current is smaller than

L TH1

90%

Anode current

The turn-ON process of a GTO is similar to that of the conventional thyristor. The device is turned ON by a steep fronted pulse of gate current, and the gate drive can be removed without the loss of conduction when the anode current exceeds the latching current level. The anode current of the GTO does not respond immediately to the applied gate signal. As shown in Fig. 8.19, the turn-ON response of the anode current is characterized by a turn-ON time, ton, which consists of a delay time, td, and a rise time tr.

+ Ed.c. –

td

tr

10% Ton

Gate applied

Time (t)

the anode current in the ON-state. It is observed that since the rise time rate is faster, the turn-ON time becomes shorter.

The conducting electron–hole plasma occupies the central region of the GTO crystal in the conducting state. In order to turn-OFF the device, a negative pulse is applied to the gate and thereby the excess holes in the P region are removed. During the storage phase of the turn-OFF process the negative gate current extracts the excess holes in the P-base through the gate terminal. As a result, the anode current path is pinched into a narrow filament under each cathode finger. In this non-regenerative threelayer section of the crystal, current cannot sustain itself and thus the current filaments quickly collapse during the full period. Thus there is a small but slowly decaying tail of anode current due to residual charges in the remote regions of the crystal.

The peak value of OFF-gate current, Igp is a function of the anode current, Id, prior to turn-OFF. The Id a2 turn-OFF gain, boff expressed as boff = ___ = __________ is typically between 3 and 5. The turn-OFF Igp a1 + a2 – 1 gain must be very large while converting a conventional thyristor into a GTO so that large values of negative gate current can be avoided. Here a2 should be near unity and a1 should be small. The controllable current is the maximum anode current that can be interrupted by gate turn-off. This is dependent on the device structure and gate drive conditions. The GTO will get damaged if an attempt is made to turn-OFF an anode current that is greater than the maximum controllable current. The I–V characteristic of GTO is shown in Fig. 8.20. In the forward direction, the I–V characteristics are identical to that of a conventional thyristor. In the reverse direction, the GTO has virtually no blocking capability because of the anode short structure. The latching current is about 400 mA for conventional thyristor and 2 A for GTO. Large power GTOs require several amperes of latching current as compared to conventional thyristors of the same rating. If the gate current is insufficient to turn-on the GTO, it behaves like a high voltage, low gain transistor with considerable anode current. This leads to a noticeable power loss under such conditions. The on-state voltage is 3.4 V for a typical 550 A, 1200 V GTO. GTOs are available to handle thousands of voltage and current upto the frequengy of 10 kHz.

The GTO has the following advantages compared to conventional thyristor: (i) Since the GTO is a faster turn-OFF device, it is used for high switching frequency applications. (ii) It has high blocking voltage and large current capability. (iii) It eliminates commutating components in forced commutation and hence, GTO inverter has 60% of size and weight of the conventional thyristor unit and has a higher efficiency. (iv) It is used as a switching element and its use in inverter is growing rapidly. (v) It reduces acoustic and electromagnetic noises.

l 10 A

2A 0

V

(a)

Reverse breakdown voltage

l ON OFF®ON if positive gate voltage applied

ON®OFF if negative gate voltage applied

Real (b)

ON-state

OFF V

Reverse blocking

l

Forward breakdown voltage

OFF-state Reverse blocking

Forward blocking

V

Ideal (c)

(i) Latching and holding current values are high. (ii) The ON-state voltage drop and the associated loss are more. (iii) The triggering gate current of GTO is higher due to multi-cathode structure as compared to conventional thyristor.

The GTO has a higher blocking voltage capability and higher ON-state gain. In high power applications, the GTO eliminates the conventional thyristor in various applications like d.c.-a.c. inverters and d.c.-d.c. choppers.

The thyristor, in practice, may be subjected to overvoltage or overcurrent. When the thyristor is turned-ON, di/dt may be very large and also there may be false triggering due to high value of dV/dt. This signal across gate-cathode terminal leads to unwanted turn-ON. Therefore, thyristor should be protected against this abnormal condition.

When a gate pulse turns ON thyristor, conduction of anode current begins and spreads across the whole area of junction. The thyristor is designed to permit the spread of conduction to the whole junction area as fast as possible. Here the rate of rise of anode current, i.e., di/dt is very large as compared to spread

velocity of carriers. This leads to formation of local hot spots near the gate connection, and destroy the thyristor. In order to avoid the adverse effect, the value of di/dt is kept below the acceptable limit by connecting a small inductor in series with the circuit.

Forward leakage current

+

A

P N P

In Fig. 8.21, the junctions J1 and J3 of the thyristor are forward biased and junction J2 is reversed biased. The reverse biased junction J2 has the characteristics of a capacitor due to charges appearing across the junction and behaves like a capacitor Cj when the forward voltage V appears across junction J2. The charge Q leads to a charging current I as given below.

G

N

J1 J2 J3

–

dCj dQ d(Cj, V) dv I = ___ = _______ = Cj ___ + V ____ dt dt dt dt The junction capacitance Cj at junction J2 is almost constant. dv Therefore, current I = Cj ___. dt Here, if the rate of rise of forward voltage dv/dt is high, the current I will be more. The charging current plays the role of gate current and turns the thyristor ON even when gate current is zero. Such a phenomenon is called dv/dt turn-on. This leads to false operation of the thyristor. Thyristor can be prevented from these adverse effects by connecting Snubber circuit in parallel with the thyristor.

The Snubber circuit as shown in Fig. 8.22 consists of series combination of resistance R and capacitor C which is connected in parallel with the thyristor. The capacitor C is sufficient to prevent unwanted dv/dt triggering. When the switch S is closed, a voltage suddenly appears across the circuit. Initially, the capacitor C behaves like a short circuit and the voltage across thyristor is zero. After some time, voltage builds up across capacitor C at the rate of dv/dt and the capacitor C is charged to full voltage V.

R

C Discharge current

S + Load

V –

When the thyristor is turned ON, the capacitor discharges through the thyristor. In order to limit the magnitude of this discharge current, a resistance R is connected in series with capacitor C. When the thyristor is turned ON, the initial discharge current V/R is relatively small and turn-ON di/dt is reduced.

The equivalent circuit for a transistor can be drawn using simple approximations by retaining its essential features, at the same time discarding its less important qualities. These equivalent circuits will aid in analysing transistor circuits easily and rapidly. In this chapter, small signal equivalent circuits of the transistor are derived. Small signal operation is that in which the ac input signal voltages and currents are in the order of ±10% of Q point voltages and currents.

A transistor can be treated as a two-port network. The terminal behaviour of any two port network can be specified by the terminal voltages v1 and v2 at ports 1 and 2, respectively, and currents i1 and i2, entering ports 1 and 2, respectively, i1 i2 as shown in Fig. 9.1. Of these four + + variables v1, v2, i1 and i2, two can be Port 2 Port 1 selected as independent variables and v1 v2 (or) (or) Transistor Output port the remaining two can be expressed in Input port – – terms of these independent variables. This leads to various two-port parameters out of which the following three are more important. (i) Z-parameters or Impedance parameters (ii) Y-parameters or Admittance parameters (iii) h-parameters or Hybrid parameters.

Here, i1 and i2 are taken as independent variables. The voltages v1 and v2 are given by the equations v1 = Z11ii + Z12i2

(9.1)

v2 = Z21i1 + Z22i2

(9.2)

These four impedance parameters, Z11, Z22, Z12 and Z21 are defined as follows: v1 Z11 = __ with i2 = 0 i1

[ ]

= input impedance with output port open circuited v2 Z22 = __ with i1 = 0 i2

[ ]

= output impedance with input port open circuited v1 Z12 = __ with i1 = 0 i2

[ ]

Z21

= reverse transfer impedance with port 1 open circuited v2 = __ with i2 = 0 i1

[ ]

= forward transfer impedance with port 2 open circuited.

Here, v1 and v2 are taken as independent variables. The currents i1 and i2 are given by the equations i1 = y11v1 + y12v2

(9.3)

i2 = y21v1 + y22v2

(9.4)

y11, y12, y21 and y22 represent short-circuit admittance parameters or simply admittance parameters or y-parameters. They are defined as follows:

[ ]

i1 y11 = __ v1 with v2 = 0 = input admittance with port 2 short circuited

[ ]

i2 y22 = __ v2 with v1 = 0 = output admittance with port 1 short circuited

[ ]

i1 y12 = __ v2 with v1 = 0 = reverse transfer admittance with port 1 short circuited

[ ]

i2 y21 = __ v1 with v2 = 0 = forward transfer admittance with port 2 short circuited.

If the input current i1 and the output voltage v2 are taken as independent variables, the input voltage v1 and output current i2 can be written as

v1 = h11i1 + h12v2

(9.5)

i2 = h21i1 + h22v2

(9.6)

The four hybrid parameters h11, h12, h21 and h22 are defined as follows: v1 h11 = __ with v2 = 0 i1

[ ]

= input impedance with output port short circuited

[ ]

i2 h22 = __ v2 with i1 = 0 = output admittance with input port open circuited v1 h12 = __ v2 with i1 = 0

[ ]

= reverse voltage gain with input port open circuited

[]

i2 h21 = __ with v2 = 0 i1 = forward current gain with output port short circuited. The dimensions of h-parameters are as follows: h11 – h22 – mhos h12, h21 – dimensionless As the dimensions are not alike, i.e. they are hybrid in nature, these parameters are called as hybrid parameters. An alternative subscript notation recommended by IEEE is commonly used: i = 11 = input; o = 22 = output f = 21 = forward transfer; r = 12 = reverse transfer

When h-parameters are applied to transistors, it is a common practice to add a second subscript to designate the type of configuration considered — e for common emitter, b for common base and c for common collector. Thus, for a common emitter (CE) configuration, hie = h11e = short circuit input impedance hoe = h22e = open circuit output admittance hre = h12e = open circuit reverse voltage gain hfe = h21e = short circuit forward current gain

Based on the definition of hybrid parameters the mathematical model for two-port networks known as h-parameter model can be developed. Equations (9.5) and (9.6) can be written as v1 = hi i1 + hrv2

(9.7)

i2 = hf i1 + hov2

(9.8)

The proposed model shown in Fig. 9.2 should satisfy these two equations and it can be readily verified by writing Kirchhoff’s voltage law equation in the input loop and Kirchhoff’s current law equation for the output node. It is to be noted that the input circuit have a dependent voltage generator and the output circuit contains a dependent current generator. 1

i1 +

i2 +

hi (W)

2

+ W ho( )

hrv 2

v1

– –

v2

hfi 1 –

1¢

2¢

On extending the hybrid model for two-port network to a transistor it is assumed that the signal excursion about the Q point is small so that the transistor parameters may be considered constant over the signal excursion. Use of h-parameters to describe a transistor have the following advantages: (i) h-parameters are real numbers upto radio frequencies (ii) they are easy to measure (iii) they can be determined from the transistor static characteristics curves (iv) they are convenient to use in circuit analysis and design (v) easily convertable from one configuration to other (vi) readily supplied by manufacturers. In order to derive a hybrid model for transistor consider the CE circuit of Fig. 9.3. The variables are iB, iC, vB (= vBE) and vC (= vCE). iB and vC are considered as independent variables. Then,

vB = f1(iB, vC)

(9.9)

iC = f2(iB, vC)

(9.10)

Making a Taylor’s series expansion around the quiescent point IB, VC and neglecting higher order terms, the following two equations are obtained:

ic

C

RL

iB

B

vc

+ VCC

–

vB

E

( ) ( )

( ) ( )

∂ f1 DvB = ___ ∂ iB

VC

∂ f1 DiB + ____ ∂ vC

IB

∂ f2 DiC = ___ ∂ iB

∂ f2 DiB + ____ ∂ vC VC

IB

DvC

(9.11)

DvC

(9.12)

The partial derivatives are taken keeping the collector voltage or base current constant as indicated by the subscript attached to the derivative. DvB, DvC, D iB and DiC represent the small-signal (incremental) base and collector voltages and currents. They are represented by symbols vb, vc, ib and ic, respectively. Hence, Eqns (9.11) and (9.12) may be written as vb = hieib + hrevc ic = hfeib + hoevc where

( ( ( (

∂ f1 hie = ___ ∂ iB

) ) ) )

( ( ( (

∂ f1 hre = ____ ∂ vC

IB

∂ f2 hfe = ___ ∂ iB

∂ iC = ___ ∂ iB VC

∂ f2 hoe = ____ ∂ vC

) ) ) )

∂ vB = ____ ∂ iB VC ∂ vB = ____ ∂ vC

∂ iC = ____ ∂ vC IB

DvB ª ____ ∂ iB VC

IB

( ( ( (

DvB ª ____ DvC

DiC ª ___ DiB VC DiC ª ____ DvC IB

) ) ) )

vb = __ ib VC

IB

( )

vb = __ vc

( )

IB

iC = __ ib VC

IB

VC

( )

ic = __ vc

VC

( )

IB

(9.13)

(9.14)

(9.15)

(9.16)

The above equations define the h-parameters of the transistor in CE configuration. The same theory can be extended to transistors in other configurations.

The hybrid models and equations given in Table 9.1 are valid for NPN as well as PNP transistors and hold good for all types of loads and methods of biasing. Table 9.2 gives the typical h-parameter values for a transistor and Table 9.3 gives the conversion formulae to find the h-parameters for CC and CB configurations given the h-parameters for CE configuration.

ic

CE

C

hie

B

ic

C

hoe

vc

ib +

ib

vc

B

vb

hre◊vc

hfe◊ib

–

vb

vb = hie ◊ ib + hre ◊ vc ic = hfe ◊ ib + hoe ◊ vc

ie E

E CB E ie

E

E hib

E

ic

C

ic C ie vc

ve

+

hrb◊vc

ve

ib

hfb◊ie

hob

vc

–

B

ve = hib ◊ ie + hrb ◊ vc ic = hfb ◊ ie + hob ◊ vc

B B

B CC

hic

ic

ie

E

B ib

ib

+

vb

B ie

vb

hre◊ve

hfc◊ib

hoc ve

–

E

vb = hic ◊ ib + hrc ◊ ve ie = hfc ◊ ib + hoc ◊ ve

ve C

C

Parameter hi hr

C

CE

CC

1,100 2.5 × 10

1,100 –4

CB 22

1

3 × 10 – 4

hf

50

–51

– 0.98

ho

25 A/V

25 A/V

0.49 A/V

CC

CB

hic = hie

hie hib = ______ 1 + hfe

hrc = 1

hie hoe hrb = ______ – hre 1 + hfe

hfc = – (1 + hfe)

– hfe hfb = ______ 1 + hfe

hoc = hoe

hoe hob = ______ 1 + hfe

A transistor amplifier can be constructed by connecting an external load and signal source as indicated in Fig. 9.4 and biasing the transistor properly. Rs

I2

I1

1

+ Vs

V1

– –

2 IL

+

+ Two port active network (transistor)

V2

ZL

–

2¢

1¢ Zi

yo

The two port active network of Fig. 9.5 represents a transistor in any one of its configuration. The hybrid equivalent circuit is valid for any type of load whether it is pure resistance or impedance or another transistor. It is assumed that h-parameters remain constant over the operating range. Further, the input is sinusoidal and I1, V1, I2 and V2 are phasor quantities.

For a transistor amplifier the current gain AI is defined as the ratio of output current to input current, i.e, IL – I2 AI = __ = ____ (9.17) I1 I1

Rs

1

I1

I2

hi

2 +

+

IL

+

+ V1

Vs –

hrv2 –

ho

V2

hfI1

– 1¢

ZL

– 2¢

From the circuit of Fig. 9.5, I2 = hf I1 + hoV2 Substituting

(9.18)

V2 = ILZL = – I2ZL, I2 = hf I1 – I2ZLho I2 + I2ZLho = hf I1 I2(1 + ZLho) = hf I1 – hf – I2 AI = ____ = _________ I1 1 + ho Z L

Therefore,

(9.19)

–hf AI = ________ 1 + hoZL

In the circuit of Fig. 9.5, Rs is the signal source resistance. The impedance seen when looking into the amplifier terminals (1,1¢) is the amplifier input impedance Zi, i.e., V1 Zi = ___ (9.20) I1 From the input circuit of Fig. 9.5, V1 = hiI1 + hrV2 Hence,

Substituting

hiI1 + hrV2 Zi = __________ I1 V2 = hi + hr ___ I1 V2 = – I2ZL = AI I1ZL

AII1ZL Zi = hi + hr ______ I1

resulting in

Zi = hi + hr AI ZL

(9.21)

Substituting for AI, hf Zi = hi – ________ hr ZL 1 + hoZL hf hr = hi – ___________ ZL 1 ZL ___ + ho ZL

(

)

1 Taking the load admittance as YL = ___ ZL hf hr Zi = hi – _______ YL + ho

(9.22)

Note that the input impedance is a function of load impedance.

The ratio of output voltage V2 to input voltage V1 gives the voltage gain of the transistor, i.e. V2 AV = ___ V1 Substituting

(9.23)

V2 = – I2ZL = AI I1ZL AII1ZL AIZL AV = ______ = _____ V1 Zi

(9.24)

By definition, Yo is obtained by setting Vs to zero, ZL to infinity and by driving the output terminals I2 from a generator V2. If the current drawn from V2 is I2, then Yo ∫ ___ with Vs = 0 and RL = •. V2 From the circuit of Fig. 9.5, I2 = hf I1 + hoV2 Dividing by V2, I2 I1 ___ = hf ___ + ho V2 V2

(9.25)

With Vs = 0, by KVL in input circuit, RsI1 + hiI1 + hrV2 = 0

(9.26)

I1 (Rs + hi) + hrV2 = 0 Hence,

I1 –hr ___ = ______ V2 Rs + hi

Substituting Eqn. (9.26) in Eqn. (9.25),

(

)

– hr I2 ___ = hf ______ + ho V2 Rs + hi hf hr Yo = ho – ______ hi + Rs

(9.27)

From Eqn. (9.27), the output admittance is a function of source resistance. If the source impedance is resistive then Yo is real.

This overall voltage gain AVs is given by V2 V2 V1 V1 AVs = ___ = ___ ___ = AV ___ Vs V1 Vs Vs

(9.28)

From the equivalent input circuit using Thevenin’s equivalent for the source shown in Fig. 9.6, Vs Zi V1 = _______ Zi + Rs

(9.29)

Zi V1 _______ ___ = Vs Zi + Rs Then,

AV Zi AVs = _______ Zi + Rs

Substituting

AI ZL AV = ______ Zi AIZL AVs = _______ Zi + Rs

(9.30)

(9.31)

AIZL Note that if Rs = 0, then AVs = _____ = AV. Hence, AV is the voltage gain with an ideal voltage source Zi (with Rs = 0). In practice, AVs is more meaningful than AV because source resistance has an appreciable effect on the overall amplification.

The modified input circuit using Norton’s equivalent circuit for the source for the calculation of AIs is shown in Fig. 9.7.

Overall current gain,

From Fig. 9.7,

–I2 –I2 I1 I1 AIS = ___ = ___ __ = AI __ IS I1 IS IS Rs I1 = IS _______ R s + Zi

(9.32)

(9.33)

Rs I1 _______ __ = IS Rs + Zi and hence,

Rs AIS = AI _______ R s + Zi

(9.34)

If Rs = , then AIS = AI. Hence, AI is the current gain with an ideal current source (one with infinite source resistance). From Eqn. (9.31) AIZL Rs AVs = _______ ___ Zi + Rs Rs Then,

AIS ZL AVs = ______ Rs

(9.35)

From Fig. 9.5 average power delivered to the load is P2 = |V2 | |IL | cos , where is the phase angle between V2 and IL. Assume that ZL is resistive i.e. ZL = RL. Since h-parameters are real at low frequencies, the power delivered to the load is P2 = V2IL = – V2I2. Since the input power P1 = V1I1, the operating power gain AP of the transistor is defined as P2 – V2I2 RL AP = ___ = ______ = AV AI = AI AI ___ P1 V1 1 Ri

( )

RL AP = A2I ___ Ri

(9.36)

The important relations derived above are summarised in Table 9.4.

– hf AI = _________ 1 + ho ZL

AI ZL AV = ______ Zi

hf hr Zi = hi + hr AI ZL = hi – _______ YL + ho

AV Zi AI ZL ZL AVs = _______ = _______ = AIS ___ Zi + Rs Zi + Rs Rs

hf hr 1 Yo = ho – ______ = ___ hi + Rs Zo

AI Rs Rs AIS = _______ = AVs ___ Zi + Rs ZL

A CE amplifier has the h-parameters given by hie = 1000 , hre = 2 × 10 – 4, hfe = 50 and hoe = 25 m mho. If both the load and source resistances are 1 k , determine the (a) current gain and (b) voltage gain.

Solution

Given Rs = 1 kW and rL = 1 kW

(a) Current gain,

hfe Ai = ___________ 1 + hoe × RL 50 = ____________________ = 48.78 1 + 25 × 10–6 × 1 × 103

(b) Voltage gain,

Here,

– hfe AV = ____________ 1 hoe + ___ Zin RL

(

)

hre hfe Zin = hie – ________ 1 hoe + ___ RL 2 × 10 – 4 × 50 = 1000 – __________________ = 990.24 W 25 × 10 – 6 + 1 × 10 – 3

Therefore,

– 50 AV = ____________________________ –6 (25 × 10 + 1 × 10 – 3) × 990.24 = – 49.26

The output voltage is 180° out of phase to the input signal with a gain of 49.26.

A transistor amplifier circuit has the h-parameters as follows: hie = 1100 , hfe = 100, hre = 10 × 10 – 4, hoe = 4 × 10 – 4 mho. Determine the (a) a.c. input impedance of the amplifier and (b) the voltage gain.

Solution

At load resistance of the amplifier, 10 × 40 RL = Ra.c. = _______ = 8 kW = 8000 W 10 + 40 hre hfe Zin = hie – ________ 1 hoe + ___ RL

(a) Input impedance,

4 × 10 – 4 × 100 = 1100 – ______________ = 1024 W 1 4 × 10 – 4 + _____ 8000 The a.c. input resistance of the entire stage Ra.c. is Ra.c. = Zin || R1 || R2 = 1024 || 100 × 1000 || 50 × 1000 = 993.4 W (b) Voltage gain,

– hfe AV = _____________ 1 hoe + ___ Zin RL

(

)

–100 = ____________________ = –186.34 1 –4 4 × 10 + _____ 1024 8000

(

)

The output is 180° out of phase to the input with a gain of 186.34.

The characteristics of three configurations are summarised in Table 9.5. Here the quantities Ai, AV, Ri, Ro and AP are calculated for a typical transistor whose h-parameters are given in Table 9.2. The values of RL and Rs are taken as 3 kW.

Quantity

CB

CC

CE

AI

0.98

47.5

– 46.5

AV

131

0.989

– 131

AP

128.38

46.98

6091.5

Ri

22.6 W

144 kW

1065 W

Ro

1.72 MW

80.5 W

45.5 kW

The values of current gain, voltage gain, input impedance and output impedance calculated as a function of load and source impedances can be shown graphically as in Fig. 9.8.

From Table 9.5 and Fig. 9.8, the performance of the CB, CC and CE amplifiers can be summarised as follows: (i) Current gain is less than unity and its magnitude decreases with the increase of load resistance RL, (ii) Voltage gain AV is high for normal values of RL, (iii) The input resistance Ri is the lowest of all the three configurations, and (iv) The output resistance Ro is the highest of all the three configurations.

The CB amplifier is not commonly used for amplification purpose. It is used for (i) matching a very low impedance source (ii) as a non-inverting amplifier with voltage gain exceeding unity (iii) for driving a high impedance load (iv) as a constant current source

(i) For low value of RL (< 10 kW), the current gain AI is high and almost equal to that of a CE amplifier, (ii) The voltage gain AV is less than unity, (iii) The input resistance is the highest of all the three configurations, and (iv) The output resistance is the lowest of all the three configurations. The CC amplifier is widely used as a buffer stage between a high impedance source and a low impedance load. The CC amplifier is called the emitter follower.

(i) The current gain AI is high for RL < 10 kW, (ii) The voltage gain is high for normal values of load resistance RL, (iii) The input resistance Ri is medium, and (iv) The output resistance Ro is moderately high. Of the three configurations CE amplifier alone is capable of providing both voltage gain and current gain. Further the input resistance Ri and the output resistance Ro are moderately high. Hence CE amplifier is widely used for amplification purpose.

As the h-parameters themselves vary widely for the same type of transistor, it is justified to make approximations and simplify the expressions for AI, AV, AP, Ri and Ro. In addition, a better understanding of the behaviour of the transistor circuit can be obtained by using the simplified hybrid model. Since CE configuration is more useful and general, it is taken for consideration. The h-parameter equivalent circuit of the transistor in the CE configuration is shown in Fig. 9.9. Here, 1 1 ___ is in parallel with RL. The parallel combination of two unequal impedances, i.e. ___ and RL is approx hoe hoe 1 mately equal to the lower value, i.e. RL. Hence, if ___ >> RL, then the term hoe may be neglected provided hoe that hoeRL > hie, Zi

hie

(9.63)

It is the impedance determined with Vi = 0. With Vi = 0, Ib = 0 and hfe Ib = 0 indicating an open circuit equivalence for the current source. Hence,

Zo = RL (= RC)

Voltage gain,

Vo AV = ___ Vi Vo = – IoRC

Substituting

Io = hfe Ib Vo = –hfe IbRC

Assuming that

RB >> hie, Ii

Ib and

Vi = Ib hie

– hfeIbRC AV = ________ Ib hie

Therefore,

– hfeRC = _______ hie

(9.64)

As hfe and hie are positive, AV is negative. The negative sign indicates a 180° phase shift between input and output signals. IL AI = __ Ii – Io = ___ Ii

– hfeIb ______ = – hfe Ib

(9.65)

Note: The sign for AI will be positive if AI is defined as the ratio of Io to Ii. Substituting the re model for the transistor in CE connection, the circuit of Fig. 9.34 reduces to that shown in Fig. 9.36. Zi = RB || re If

(9.66)

RB >> re Zi = re

(9.67)

For similar reasons, Zo = R C

(9.68)

Vo AV = ___ Vi Vo = –IoRC Substituting

Io = Ib Vo = – (+ Ib)RC = – IbRC B

lb

C

+

+

Io blb

Vi

RB

E

–

Zi

Vo RL

bre

–

E Zo

Assuming

RB >> re Vi

Ib re

– IbRC AV = _______ Ib re – RC = _____ re – Io AI = ____ Ii – I o = ____ Ib

(9.69)

– Ib = _____ = – Ib

(9.70)

Determine the input impedance, output impedance, voltage gain and current gain for the CE amplifier of Fig. 9.37. The h-parameters of the transistor of hfe = 60, hie = 500 at IC = 3 mA.

Solution

RB = 220 k

12 V

>> hie = 500

From h-parameter model Zi = hie = 500 Zo = RC = 5.1 k

220 kW 3

– hfeRC – 60 (5.1 × 10 ) AV = ______ = _____________ 500 hie = – 612

Vo 0.1 mF

Vi

AI = – hfe = – 60 From re model 26 mV Zi = re where re = ______ Ie VCC – VBE _________ From the circuit, Ib = RB 12 – 0.6 = _________3 = 51.8 A 220 × 10 Ie

Ic = Ib = 60 × 51.8 × 10 –6 = 3.108 mA

26 × 10 –3 re = ___________ = 8.37 3.108 × 10 –3

5.1 kW 0.1 mF

Zi = b re = 60 × 8.37 = 502.2 W Zo = RC = 5.1 kW – RC AV = ____ r e

– (5.1 × 103) = ___________ = – 609 8.37 AI = – b = – 60 Note: Small differences in the calculation of amplifier parameters between the h-parameter and re models might arise due to the approximations made in the circuit design.

A simple and effective way to provide voltage gain stabilisation in a CE amplifier is to add an emitter resistor RE which provides feedback as shown in Fig. 9.38. An approximate solution for this arrangement can be obtained by considering the simplified hybrid model equivalent circuit.

Ic – hfe Ib AI = – __ = ______ = – hfe Ib Ib Thus, the current gain is equal to the short circuit current gain with RE = 0 and is unaffected by RE. Vi [ hie + (1 + hfe) RE ]Ib Ri = __ = __________________ Ib Ib

(9.71)

Ri = hie + (1 + hfe) RE Comparing with Eqn. (9.38), the input resistance is augmented by (1 + hfe) RE and may be very much larger than hie. For example, with RE = 1 kW, hfe = 60, (1 + hfe) RE = 61 kW >> hie ª 1 kW. Hence, RE greatly increases the input resistance of the amplifier. From Eqn. (9.24), hfe RL RL AV = AI ___ = – _______________ Ri hie + (1 + hfe)

(9.72)

Thus, the addition of emitter resistor RE greatly reduces the voltage amplification as Ri has increased from hie to hie + (1 + hfe)RE. This reduction in gain is compensated by stability improvement. If (1 + hfe) RE >> hie and hfe >> 1 Then

hfe RL – RL AV ª – __________ ª _____ (1 + hfe) RE RE

(9.73)

VCC

RL = (RC) Vo

C

B

lC

hie

C

B hfe lb

E E

Rs

Rs RE

RE

Vi +

+

Vs

RL Vc

(1 + hfe) lb

Vs –

–

Ri

N

(a)

N (b)

Hence, under these approximations AV is completely stable and independent of all transistor parameters provided stable resistances are used for RL and RE. Output resistance Ro with RL excluded is infinite and with RL included, it is equal to RL and is independent of RE.

A CE amplifier uses load resistor RC = 2 k in the collector circuit and is given by the voltage source Vs of internal resistance 1000 . The h-parameters of the transistor are hie = 1300 , hre = 2 × 10–4, hfe = 55 and hoe = 22 mhos. Neglecting the biasing resistors, compute the current gain AI, input resistance Ri, voltage gain AV, output resistance Ro and output terminal resistance RoT for the following values of emitter resistor RE inserted in the emitter circuit: (i) 200 (ii) 400 and (iii) 1000 . Use the approximate model for the transistor if permissible.

Solution (i) For

RE = 200 hoe × (RE + RC) = (2 × 103 + 200) × (22 × 10–6) = 0.0484

Since hoe × (RE + RC) < 0.1, the approximate model is permissible. AI = – hfe = –55 Ri = hie + (1 + hfe) RE = 12.5 k

RC AV = AI ___ 2000 = –55 × ______ = – 8.8 12,500 Output resistance, Ro = • Output terminal resistance, ROT = Ro | | RC = 2 kW (ii) For RE = 400 W hoe × (RE + RC) = (2 × 103 + 400) × (22 × 10–6) = 0.0528 Since hoe × (RE + RC) < 0.1, approximate model is permissible. AI = – hfe = – 55 Ri = hie + (1 + hfe) RE = 23.7 kW RC AV = AI ___ Ri 2000 = – 55 × ______ = – 4.654 23,700 Output resistance, Ro = • Output terminal resistance, ROT = Ro | | RC = 2 kW (iii) For

RE = 1000 W

Since hoe × (RE + RC) < 0.1, approximate model is permissible. Al = –hfe = –55 Ri = hie + (1 + hfe) RE = 57.3 kW RC AV = AI ___ Ri 2000 = – 55 × ______ = –1.92 57,300 Output resistance, Ro = • Output terminal resistance, ROT = Ro || RC = 2 kW

The a.c. equivalent circuit for this amplifier shown in Fig. 9.39 can be drawn by following the steps mentioned earlier. By substituting the hybrid equivalent circuit for the transistor of Fig. 9.40, the circuit reduces to that shown in Fig. 9.41. Current through the emitter resistor RE is Ie = Ib + hfe Ib = (1 + hfe)Ib

From Fig. 9.41, Vi = Ibhie + (1 + hfe) IbRE Vi Zb = __ = hie + (1 + hfe)RE Ib

(9.74)

As hfe >> 1, Zb Normally,

hie + hfeRE

(9.75)

hfeRE >> hie leading to Zb

hfeRE

(9.76)

From the circuit of Fig. 9.41, Zi = RB || Zb With Vi = 0, Ib = 0, hfeIb = 0 indicating open circuit for current source.

(9.77)

Hence,

Zo = RC

(9.78)

Vo AV = ___ Vi From the circuit of Fig. 9.41, Vo = –IoRC = – (hfeIb)RC

( )

Vi = – hfe ___ RC Zb Vo – hfeRC AV = ___ = ______ Vi Zb With

Zb

(9.79)

hfeRE,

– hfeRC AV = ______ hfeRE – RC = _____ RE – Io AI = ____ Ii Io = hfeIb where

RB Ib = Ii ________ R B + Zb

(9.80)

Therefore, Substituting

Vo – RC AV = ___ = _____ Vi Zb RE Zb – RC AV = ____ RE Io AI = – __ Ii Io = Ib

where Therefore,

(9.85)

RB Ib = Ii ________ R B + Zb RB Io = Ii ________ R B + Zb – Io RB AI = ___ = – ________ Ii RB + Zb

(9.86)

Consider the CE amplifier of Fig. 9.43 in which the base bias is obtained by two resistors R1 and R2.

By substituting the h-parameter equivalent for the transistor, the a.c. equivalent circuit can be obtained directly as shown in Fig. 9.44. As capacitor CE bypasses RE in the operating frequency range, RE is omitted in the equivalent circuit.

Let

R 1R 2 RB = R1 || R2 = _______ R1 + R2 Zi = RB || hie

(9.87)

Zo = R C

(9.88)

Vo AV = ___ Vi Substituting

Vo = – hfe Ib RC

and Vi = Ib hie

– hfeIb RC AV = ________ Ib hie – hfeRC = ______ hie

(9.89)

– Io AI = ___ Ii Substituting

Io = – hfe Ib

where

RB Ib = Ii _______ RB + hie

Therefore,

RB Io = – hfe Ii _______ RB + hie

RB AI = – hfe _______ RB + hie Substituting the re model for the transistor, the a.c. equivalent circuit is as given in Fig. 9.45. Zi = RB || re

(9.90)

(9.91)

lb

li +

lo Vi

R1

bre

R2

blb

RC

Vo

–

Zo

Zi

Zo = R C

(9.92)

Vo AV = ___ Vi where

Vo = – IbRC Vi Ib = ____ re

Therefore,

Vo = –

( )

Vi ____ R re C

Vo – RC AV = ___ = ____ re Vi

(9.93)

– Io AI = ___ Ii From the circuit of Fig. 9.43, Io = – Ib where

RB Ib = Ii ________ RB + re

Therefore,

RB Io = – Ii ________ RB + re Io AI = __ = – Ii

RB ________ RB + re

(9.94)

Determine the input impedance, output impedance, voltage gain and current gain of the CE amplifier of Fig. 9.46 using h-parameter and re model equivalents for the transistor with hie = 3.2 k and hfe = 100 at the operating conditions.

VCC = 16 V

RC 40 kW

4 kW

Vo 1 mF

1 mF

Vi

4.7 kW

R2

RE 1.2 kW

Solution

h-Parameter analysis Zi = RB || hie RB = R1 || R2 = 40 k

|| 4.7 k

= 4.2 k Zi = 4.2 k

|| 3.2 k

= 1.82 k

Zo = RC = 4 k – hfeRC AV = ______ hie – 100 × 4 × 103 = _____________ = –125 3.2 × 103 – hfeRB AI = _______ RB + hie – 100 × 4.2 × 103 = _______________3 = –56.76 (4.2 + 3.2) × 10 Using re model To find IB, R2VCC VB = _______ R1 + R2

CE = 10 mF

4.7 × 16 × 103 = _____________ = 1.682 V 44.7 × 103 Using Thevenin’s equivalent for input part, VB – VBE IB = ______________ RB + (1 + b) RE 1.682 – 0.6 = ____________________________ 3 4.2 × 10 + (1 + 100) (1.2 × 103) 1.082 = __________3 = 8.628 mA 125.4 × 10 IC = b IB = 100(8.628 × 10 –6) = 0.86 mA IE ª IC = 0.86 mA 26 mV 26 × 10 –3 re = ______ = __________ = 30.23 W IE 0.86 × 10 –3 Zi = RB ||b re = (4.2 × 103) || (100 × 30.23) = 4200 || 3023 = 1.76 kW Zo = RC = 4 kW – RC AV = ____ re – 4000 = ______ = –132.3 30.23 – b RB AI = ________ RB + bre – 100 (4.2 × 103) = _______________________ = – 58.147 (4.2 × 103) + (100 × 30.23)

Figure 9.47 shows the circuit of a CB amplifier. By applying the steps mentioned earlier to draw the a.c. equivalent circuit the circuit of Fig. 9.47 reduces to the circuit of Fig. 9.48. Substituting the approximate hybrid model for the transistor in CB connection the circuit of Fig. 9.48 reduces to the circuit of Fig. 9.49.

Zi = RE || hib Zo = R C Vo AV = ___ Vi

(9.95) (9.96)

Vo = – Io RC = – hfb Ie RC Assuming that RE >> hib, Ii and Vi = Iehib Vo – hfb RC AV = ___ = _______ Vi hib – I o AI = ____ Ii – hfb Ie ______ Ie Ie

AI = – hfb Note: As hfb is negative, AV and AI are positive for CB configuration.

(9.97)

(9.98)

For substituting the re model for the transistor, substitute hib = re and hfb = –1. Note the direction of IE reversed from the diagram of Fig. 9.49 and hence, the orientation of current source is also reversed. This results in the a.c. equivalent circuit for the CB amplifier using re model shown in Fig. 9.50.

Zi = RE || re Zo = R C

(9.99) (9.100)

Vo – IoRC AV = ___ = ______ Vi Ie re (– Ie) RC = – ________ Ie re RC = ___ r

(9.101)

e

– Io AI = ____ Ii

(– IE) – _____ = 1 IE

(9.102)

Find the input impedance, output impedance, voltage gain and current gain for the CB circuit of Fig. 9.51. Assume VBE = 0.6 V.

Solution

VEE – VBE | IE | = _________ RE 8 – 0.6 = ______ = 1.85 mA 4000 26 mV re = ______ IE

26 = ____ = 14.05 W 1.85 Zi = RE || re = 4000 || 14.05 = 14 W Zo = RC = 3 kW RC _____ 3000 AV = ___ re = 14.05 = 213.52 AI = 1

Figure 9.52 shows the Emitter Follower circuit in which the output is taken from the emitter terminal with respect to ground and the collector terminal is VCC directly connected to VCC. Since VCC is at signal ground in the a.c. equivalent circuit as shown in Fig. 9.52, the emitter follower circuit is also called common collector amplifier. R 1

The small signal current gain, Ai, is defined as the ratio of output load current IL to input current Ib. IL Ie (1 + hfe)Ib Ai = __ = __ = _________ = 1 + hfe Ib I b Ib where

Rs

CC Vo

Vs

+ –

R2

RE

Ie = –(1 + hfe)Ib

From Fig. 9.53, the input resistance looking into the base is denoted as Ri, that is, Vb Ri = ___ = hie + (1 + hfe)RL Ib where

Vb = hie Ib + (1 + hfe)Ib RL

Therefore, the input resistance seen by the signal source R¢i is R¢i = Ri || R1 || R2 The small signal voltage gain, AV, is defined as the ratio of output voltage, Vo, to input voltage, Vi. That is, Vo AiRL Ri – hie hie AV = ___ = _____ = ______ = 1 – ___ Vi Ri Ri Ri Therefore, AV ª 1 but always slightly less than one since Ri >> hie.

Ib

Ic

B

E

+

hie

IL

(1 + hfe)lb

Rs VI

+ Vc –

R1 || R2

hfe lb

RL

– C R ¢i

C Ri

Ro

R

From Fig. 9.53, the output admittance looking back into the emitter is denoted as Y0, that is, hfchrc Y0 = hoc – _______ hic + R¢S where

R¢s = Rs || R1 || R2

Neglecting hoc and assuming hrc = 1, hfc = – (1 + hfe), we get – hfc Y0 = _______ hic + R¢s – hic + R¢s hie + R¢s R0 = _________ = _______ hfc 1 + hfe Hence, the output resistance looking back into the output terminals, R¢o, is the load resistance, RL, in parallel with the resistance looking back into the emitter, Ro, that is, Therefore,

R¢o = Ro || RL The equations for input impedance, output impedance, voltage gain and current gain are given below: h-parameter model

re model

Zi = RB || Zb, where Zb = hie + hfe RE ª hfe RE

Zi = RB || Zb, where Zb = b (re + RE) ª b RE

hie Zo = RE || ______ 1 + hfe

bre Zo = RE || _____ 1+ b

RE AV = ____________ hie RE + ______ 1 + hfe

RE AV = _______ RE + re

(hfe) RB AI = ________ RB + Zb

bRB AI = ________ RB + Zb

[ ]

For the Emitter Follower shown in Fig. 9.52, the circuit parameters are Rs = 500 , R1 = R2 = 50 k , RL = 2 k , hfe = 100 and hie = 1.1 k . Determine the input resistance, output resistance, current gain and voltage gain.

Solution (a) To determine input resistance (Ri) Ri = hie + (1 + hfe)RL = 1.1 × 103 + (1 + 100) × 2 × 103 = 203.1 kW R¢i = Ri || R1 || R2 = 203.1 × 103 || 50 × 103 || 50 × 103 = 22.26 kW (b)To determine output resistance (R0) hie + R¢s 1.1 × 103 + (500 || 50 × 103 || 50 × 103) R0 = _______ = _________________________________ 1 + 100 1 + hfe 1.59 × 103 = _________ = 15.74 W 101 R¢o = Ro || RL = 15.74 || 2 × 103 = 15.62 W (c) To determine current gain (Ai) Ai = 1 + hfe = 1 + 100 = 101 (d) To determine voltage gain (AV) hie 1.1 × 103 AV = 1 – ___ = 1 – __________3 = 0.9946 Ri 203.1 × 10

Calculate the current gain AI, voltage gain AV, input resistance Ri and output resistance Ro for the common collector amplifier shown in Fig. 9.54. The transistor parameters are hic = 1.4 k , hfc = 100, hrc = 20 A/V and hoc = 20× 10–6. + VCC R1

20 kW

C1 C2 Rs + Vs –

21 kW R2

20 kW

RE

10 kW

RL 40 kW

where

– hfc AI = _________ 1 + hoc R¢L R¢L = RE || RL = (40 || 10) kW = 8 kW – (–100) 100 A1 = _____________________ = ____ = 86.2 1 + (20) × 10–6 × 8 × 103 1.16

Input resistance

Ri = hic + hrcAIR¢L

Solution

Current gain

= 1.4 × 103 + (1) (86.2) (8 × 103) = 691 kW AI R¢L (86.2)(8 × 103) AV = _____ = _____________ = 0.998 RI 691 × 103 1 Ro = ___ Yo hfc hrc Yo = hoc – _______ hic + R¢s

Voltage gain Output resistance,

where

R¢s = Rs || R1 || R2 = 1|| 20 || 20 kW = 0.9 kW (– 100)(1) Yo = 20 × 10–6 – _____________________ = 43478.26 × 106 (1.4 × 103) + (0.9 × 103) Ro = 22.99 W R¢o = Ro || R¢L = (22.99) || (8 × 103) = 22.92 W

The common collector amplifier shown in Fig. 9.55 has VCC = 15 V, RB = 75 k and RE = 910 . The of the silicon transistor is 100. Find the input impedance of the amplifier stage (Zi) and voltage gain of the amplifier (AV). VCC = 15 V

75 KW

RB

Vo

+ Vs

–

RE

910 W

Solution

We know that

VCC – VBE IB = ______________ RB + (1 + b) RE 15 – 0.7 IB = _____________________ = 85.7 mA 3 75 × 10 + (1 + 100) 910

Therefore,

IE = (1 + b)IB = 8.57 mA The dynamic resistance is

0.026 0.026 re = _____ = __________ = 3.03 W IE 8.57 × 10–3 The input impedance of the amplifier is Zb = (1 + b)(re + RE) = 101 (3.03 + 910) = 92.2 kW [since hfc = 1 + hfe] The input impedance of the amplifier stage is (75 × 103) (92.2 × 103) Zi = RB || Zb = ___________________ = 41.35 kW 75 × 103 + 92.2 × 103 The voltage gain of the amplifier is RE 910 AV = _______ = __________ = 0.997 re + RE 3.03 + 910 The common collector amplifier shown in Fig. 9.56 has VCC = 10 V, RB = 470 k and RE = 3.3 k . The of the silicon transistor is 100. Find the input impedance of the amplifier state (Zi) and overall voltage gain (VL/VS). VCC = 10 V

470 KW

Rs

RB

1 kW +

Vs

RE

3.3 kW –

50 W

RL

VL

Solution

VCC – VBE IB = ______________ RB + (1 + b) RE

From Fig. 9.56,

10 – 0.7 = ________________________ = 11.58 mA 3 470 × 10 + 101 × 3.3 × 103 IE = (1 + b)IB = 101 × 11.58 × 10 – 6 = 1.16 mA The load resistance of the emitter follower is rL = RE || RL = 3.3 kW || 50 W = 50 W Zi = RB || (1 + b)(re + rL) = 470 × 103 || (101)(22.4 + 50) = 7.13 kW

(

Zi VL ______ rL ___ = = _______ r + r Vs Rs + Zi e L

)

(

)

7.13 × 103 50 = __________ _________________ = 0.605 (22.4 + 50) 1 × 103 + 7.3 × 103

For the circuit shown in Fig 9.57, find the input impedance of the amplifier (Zb), input impedance of the amplifier stage Zi, voltage gain of the amplifier (AV), load voltage VL and load current iL, overall voltage gain (VL/Vs), and overall current gain iL is. VL

Rs

Vs

500 W

RE

Therefore,

4 kW

(rms) –6V

We know that

1 kW

+ 10 mV –

Solution

Ro

2 kW

6V

VEE – VBE IE = _________ RE 6 – 0.7 IE = _______3 = 2.65 mA 2 × 10 0.026 Zb = re = __________ = 9.81 W 2.65 × 10–3 Zi = re || RE = 9.81 W || 2 kW = 9.76 W

RL

RC _____ 1000 AV = ___ re = 9.81 = 101.9 re VL RL ___ = AV ______ ________ Vs re + Rs RL + RC

)(

(

(

9.81 = 101.9 _________ 9.81 + 50

)

4 × 10 ) ( _______________ ) = 13.37 4 × 10 + 1 × 10 3

3

3

VL = 13.37 ◊ Vs = 13.37 × 10 mV (rms) = 133.7 mV (rms)

Therefore,

VL 133.7 × 10–3 iL = ___ = ___________ = 33.4 mA (rms) RL 4 × 103

(

Rs iL __ = a ______ iS Rs + re

(

)(

50 = 1 _________ 50 + 9.81

RC ________ RC + RL

)

1 × 10 ) ( ________________ ) = 0.167 1 × 10 + 4 × 10 3

3

3

()

( )

VL iL Find the voltage gain of the amplifier AV, overall voltage gain ___ and overall current gain __ of the comVs iS mon base amplifier as shown in Fig. 9.58. Assume the transistor used is Germanium.

Solution

The emitter current of the common base amplifier is

VEE – VBE 24 – 0.3 IE = _________ = ________3 = 1.077 × 10–3 A RE 22 × 10

– 24 V VL RC

0.026 0.026 re = _____ = ___________ = 24.14 W IE 1.077 × 10–3

12 kW 15 kW

RC AV = ___ re = 497

RL

re VL ___ = AV ______ re + Rs Vs

(

) ( ________ R +R )

(

)(

RL

L

24.14 = 497 __________ 24.14 + 10

(

Rs iL __ = Ai ______ iS Rs + re

)(

10 W

C

)

15 × 103 _________________ = 195.156 12 × 103 + 15 × 103

)

RC ________ = 0.444 RC + RL

Rs

22 kW

+ Vs

RE

– + 24 V

The silicon transistor in the amplifier stage shown in Fig. 9.59 has a collector resistance of rc = 1.5 M . Find (i) the input resistance of the amplifier stage, (ii) the output resistance of the amplifier stage, and (iii) the rms load voltage VL. +9V

–9V

RE

2.2 kW Ro

4.7 kW

VL

Rs

20 W RL

10 kW

+ Vs

20 mV (rms) –

Solution We know that

VEE – VBE 9 – 0.7 IE = _________ = ________3 = 1.765 mA RE 4.7 × 10 0.026 re = _____ = 14.7 W IE Zi = RE || re = 4.7 kW || 14.7 W = 14.6 W Zo = RC || rc = 2.2 kW || 1.5 MW Zo RC || rc AV = ___ = ______ = 149.5 Zi RE || re

(

Zi VL ___ = AV _______ Vs Rs + Zi Therefore,

)(

)

RL ________ = 51.9 RL + Zo

VL(rms) = 51.9 × Vs (rms) = 1.038 V(rms)

Find the input impedance of the amplifier stage (Zi) and overall voltage gain (VL/Vs) for each of the amplifier shown in Fig. 9.60. Assume = 100.

Solution

Referring to Fig 9.60 (a), we get R2 4.7 × 103 × 10 VB = _______ VCC = __________________ = 1.39 V R1 + R2 27 × 103 + 4.7 × 103

+ 10 V RC 3.3 kW

27 kW R1

Rs +

600 W

R2 4.7 kW

Vs

10 V

RE

R1 27 kW 3.3 kW 600 W

+ RL VL 15 kW –

+

–

4.7 k

Vs

680 W

+ VL 15 kW –

R2

680 W

–

(b)

(a)

VE = (1.39 – 0.7) = 0.69 V VE 0.69 IE = ___ = ____ = 1 mA RE 680 0.026 re = _____ = 26 W IE Zi = R1 || R2 || b (re + RE) = 3.79 kW

(

RC VL The overall voltage gain is ___ = – _______ Vs R E + re Referring to Fig 9.60(b)

)(

Zi _______ Rs + Zi

)(

)

RL ________ = – 3.3 RC + RL

Zi = R1 || R2 || bre = 1.58 kW Z R ________ = – 74.9 ( ) ( _______ ) ( R +Z R +R )

RC VL ___ = – ___ re Vs

i

s

L

i

C

L

An amplifier should produce an output waveform which does not differ from the input signal waveform in any respect except amplitude, i.e. the output is an amplified signal of the input. In practice, it is highly impossible to construct an ideal amplifier whose output waveform is an exact replica of the input signal waveform because of the nonlinearity of the characteristic of an active device. The output differs from the input either in its waveform or frequency content. The difference between the output waveform and the input waveform in an amplifier is called distortion. Harmonic distortion is seen by the nonlinear dynamic curve for an active device. In this type of distortion, the new frequencies are produced in the output, which are not present in the input signal. This harmonic distortion is sometimes called amplitude distortion. The intermodulation distortion is also a type of nonlinear distortion which occurs when the input signal consists of more than one frequency. If an input signal contains two frequencies f1 and f2, then the

output will contain their harmonics, i.e. f1, 2f1, 3f1, etc and f2, 2f2, 3f2, etc. In addition, there would be components ( f1 + f2) and ( f1 – f2) and also the sum and difference of the harmonics. These sum and difference frequencies are called intermodulation frequencies which are undesirable because they subtract from the original intelligence. The second harmonic distortion is obained from the dynamic transfer curve using the three-point method for small signals, or the total harmonic distortion is calculated by the five-point method for large signals. In this type of distortion, the signal components at different frequencies are amplified by different amounts. This distortion may be caused by the various frequency dependent reactances associated with the circuit or active device itself. Due to the capacitive and inductive components in the amplifier circuits, and the active device, there is a loss in gain at the lower and higher extremes of the frequency range. Hence the gain becomes a complex number whose magnitude and phase angle depend upon the frequency of the applied signal. In this type of distortion, the phase shift between input and output waveforms depends upon the signals of different frequencies. Since human ear is not sensitive to phase shift, the phase distortion has no practical significance in audio amplifiers. If the phase shift varies with frequency, different frequency components of the signal are delayed by different amounts of time and hence a television picture is smeared.

Miller’s theorem states that if an impedance Z is connected between the input and output terminals of a network which provides a voltage gain A, an equivalent circuit that gives the Z same effect can be drawn by removing Z and connecting an impedance Zi = _____ across the input and 1–A Z ZA Zo = _____ = _____ across the output as shown in Fig. 9.61. 1 A–1 __ 1– A

In inverting amplifiers, the capacitive element, Cf, is connected between input and output terminals of 1 the active device i.e., XC = _____. The large capacitors will control the low-frequency response due to f jw Cf their low reactance levels.

Therefore, the Miller effect input capacitance CMi, is derived as Z Zi = ______ (1 – A) i.e. Therefore,

1 1 ______ = ___________ jw CMi jw Cf (1 – A) CMi = (1 – A)Cf.

Hence, it is evident that, in any inverting amplifier, the input capacitance will be increased by a Miller effect capacitance sensitive to the gain of the amplifier and the interelectrode capacitance, Cf, between the input and output terminals of the active device. The Miller output capacitance, CMo is derived as Z Zo = _______ 1 1 – __ A

(

i.e.

Therefore, If

)

1 1 ______ = ____________ jw CMo 1 jw Cf 1 – __ A

(

(

)

)

1 CMo = 1 – __ Cf A A >> 1, CMo = Cf.

Dual of Miller’s theorem states that if an impedance Z connected as shunt element between input and output terminals, as shown in Fig. 9.62(a) can be replaced by an impedance (AI – 1) 1 Zi = Z(1 – AI) at the input side and Z0 = Z 1 – ___ = Z _______ at the output side as shown in Fig. AI AI I__2 9.62(b), where the current ratio, AI = . This can be verified by finding that the voltage across Zi is I1Zi I1 which is equal to the voltage drop (I1 + I2)Z across Z if Zi = Z(1 – AI). Hence the input voltage Vi is the

(

)

same in the two circuits in Fig. 9.62(a) and (b).

[ ]

AI – 1 Similarly the voltage V2 has the same value in the two circuits if the impedance Zo = ______ Z. Therefore, AI the two networks are identical. This transformation is useful in the analysis of electric circuits.

A single-stage RC coupled CE amplifier shown in Fig. 9.63 can be employed as a small-signal amplifier but a circuit with two cascaded stage gives large amplification. The design of resistor values involves application of Ohm’s law after selecting suitable voltage and current levels throughout the circuit. The design of capacitor values are based on the lower cut-off frequency of the circuit and the resistance which is in series with the capacitor.

In this circuit, the biasing is provided by three resistors R1, R2 and RE. The resistors R1 and R2 act as a potential divider giving a fixed voltage to the base. If collector current increases due to change in temperature or change in hfe, then the emitter current IE also increases, reducing the voltage difference between base and emitter (VBE). Due to reduction in VBE, base current IB and hence collector current IC also reduces. Negative feedback acts in emitter bias circuit. This reduction in collector current IC compensated for the original change in IC. The frequency response of the single-stage RC coupled BJT amplifier is shown in Fig. 9.64. The design of single-stage RC coupled amplifier is based on the specifications like supply voltage, minimum voltage gain, frequency response, source impedance and load impedance. The circuit shown in Fig. 9.63 has no provision for negative feedback because of the bypass capacitor CE and hence it is designed to achieve the largest possible gain. The voltage gain of a CE amplifier circuit is given by

– hfe (RC || RL) AV = _____________ hie Since AV is directly proportional to RC || RL, the design for large voltage gain requires selection of the largest possible collector resistance. But a large value of RC needs the collector current to be small for satisfactory operation of transistor. The value of collector resistance RC can be determined by applying Kirchhoff’s voltage law around the collector-emitter circuit. i.e.

VCC = ICRC + VCE + VE

VCC – VCE – VE RC = ______________, where VE = IERE IC VCC VCC To achieve larger value of RC, let us assume VCE = ____ and VE = ____. 2 10 For good bias stability, the emitter resistor voltage drop, VE, should be greater than the base emitter voltage VBE i.e., VE >> VBE. Since VE = VB – VBE, the emitter voltage VE will be slightly affected by the VE variation in VBE due to change in temperature. Hence, IE and IC remain stable at IC ª IE = ___. RE By Ohm’s law, the input resistance at the transistor base is Vin Rin(base) = ___ Iin Here

Vin = VBE + IERE ª IERE, ª b IBRE,

and Therefore,

since VBE > R2 (at least 10 times greater), then R2 VB = _______ VCC. R1 + R2

(

)

IC The voltage divider current I2 is selected as ___ which results in good bias 10 stability and high input resistance. Hence, the bias resistors are calculated as VB R2 = ___ and I2

VCC – VB R1 = _________ I2

where

(

)

R2 VB = VE + VBE or VB = _______ VCC. R1 + R2

Always the bypass capacitor across the emitter resistor is used to filter out the signal variations at the emitter with respect to ground. Therefore the reactance offered by this capacitor should be low for high frequencies but high for d.c. and nearby low frequencies. 1 XC = ______ E 2p fCE where XC should be high for dc and very low frequency signals and low for high frequencies. E Therefore, 1 CE = _______ 2p fXC E

where CE should be high for high frequencies starting from 100 Hz. Therefore, XC can be fixed at one-tenth of RE. E

All capacitors should be selected to have the smallest possible capacitance value mainly to minimize the physical size of the circuit. Each capacitor has its highest impedance at the lowest operating frequency and it is calculated based on the lower cut-off frequency. The bypass capacitor CE is normally the largest capacitor in the circuit. We known that the voltage gain for CE circuit with unbypassed emitter resistance given by –hfe(RC || RL) AV = ______________ hie + RE(1 + hfe) By including the bypass capacitor in parallel with RE the voltage gain is given by –hfe(RC || RL) AV = _______________________ hie + RE(1 + hfe)(RE || XC ) E

Normally RE >> XC so RE can be neglected and also XC is capacitive reactance. E

E

–hfe(RC || RL) __________________ AV = ____________________ 2 h2ie + [(1 + hfe) (XC )]

Hence,

÷

E

When hie = (1 + hfe)XC

E

–hfe(RC || RL) Avm ______ = ____ __ , |AV| = ____________ ÷2 hie ÷12 + 12 where AVm is the mid frequency gain. Therefore, at lower cut-off frequency fL, hie = (1 + hfe)XC

E

hie XC = ______ E 1 + hfe

Hence, We know that

hie ______ = hib 1 + hfe 1 1 CE = ________ = _______ 2p fLXC 2p fLhib

Therefore,

E

The coupling capacitors C1 and C2 have negligible effect on the frequency response of the amplifier circuit and to minimize the effects of these capacitors, the reactance of each coupling capacitor is selected to be approximately equal to one-tenth of the impedance in series with it at the lower cut-off frequency fL. These capacitances can be determined from the equations given by Zi (R1 || R2 || hie) 1 C1 = ________, where XC = ___ = ____________ 1 10 10 2p fLXC 1

1 C2 = ________, 2p fLXC

and

2

ZO RC || RL where XC = ___ = _______ 2 10 10

Design a single stage RC coupled BJT amplifier circuit shown in Fig. 9.63. Assume that VCC = 10 V, IC = 4 mA, hfe = 100, hie = 1 k , RL = 100 k and fL = 100 Hz.

Solution

Refer to Fig. 9.63.

(a) To determine bias resistors R1 and R2 and RC and RE We know that

VCC 10 VCC VE = ____ = ___ = 1V, VCE = ____ = 5V 2 10 10

VCC = ICRC + VCE + VE Therefore,

ICRC = VCC – VCE – VE = 10 – 5 – 1 = 4V

i.e

4 RC = _______ = 1 kW 4 × 10–3

Here,

VE = IERE ª ICRE

Therefore, VE 1 RE = ___ = _______ = 250 W IC 4 × 10–3 VB = VBE + VE = 0.7 + 1 = 1.7

(

)

R2 VB = _______ VCC R1 + R2 R2 VB 1.7 _______ = ____ = ___ = 0.17 R1 + R2 VCC 10 R2 = 0.17(R1 + R2) 5.88R2 = R1 + R2 4.88R2 = R1 The value of R2 can be selected to satisfy b RE >> R2. Hence R2 is selected as 2 kW. Therefore, R1 = 9.76 kW ª 10 kW (b) To determine the bypass capacitor CE hie 1 × 103 XC = ______ = _______ = 9.9 E 1 + hfe 1 + 100 1 1 1 CE = ________ = _____________ = ______ = 160.8 m F 2p × 100 × 9.9 6217.2 2p fLXC E

(c) To determine coupling capacitors C1 and C2 Zi (R1 || R2 || hie) (10 × 103 || 2 × 103 || 1 × 103) XC = ___ = ____________ = _________________________ 1 10 10 10 = 246.154 1 1 C1 = ________ = _________________ = 6.47 m F 2p × 100 × 246.154 2p fLXC 1

ZO RC || RL 1 × 103 || 100 × 103 XC = ___ = _______ = _________________ = 99.001 2 10 10 10 1 1 1 C2 = ________ = ________________ = _________ = 0.1608 m F 2p × 100 × 99.001 62172.628 2p fLXC 2

The small signal models for the common source FET can be used for analysing the three basic FET amplifier configurations: (i) Common source (CS), (ii) Common drain (CD) or Source-follower, and (iii) Common gate (CG). The CS amplifier which provides good voltage amplification is most frequently used. The CD amplifier with high input impedance and near-unity voltage gain is used as a buffer amplifier and the CG amplifier is used as high frequency amplifier. The small signal current-source model for the FET in CS configuration is redrawn in Fig. 9.65(a) and the voltage-source model shown in Fig. 9.65(b) can be derived by finding the Thevenin’s equivalent for the output part of Fig. 9.65(a). m, rd and gm are the amplification factor, drain resistance and mutual conductance of the FET. Field Effect Transistor (FET) amplifiers provide an excellent voltage gain with the added feature of high input impedance. They have low power consumption with a good frequency range, and minimal size and weight. The noise output level is low. This feature makes them very useful in the amplifier circuits meant for very small signal amplifications. JFETs, depletion MOSFETs and enhancement MOSFETs are used in the design of amplifiers having comparable voltage gains. However, the depletion MOSFET circuit realizes much higher input impedance than the equivalent JFET configuration. Because of the high input impedance characteristic of FETs, the a.c. equivalent model is somewhat simpler than that employed for BJTs. The common source configuration is the most popular one, providing an inverted and amplified signal. However, one also finds the common drain (source follower) circuits providing unity gain with no inversion and common gate circuits providing gain with no inversion. Due to very high input impedance, the input current is generally assumed to be negligible, and it is of the order of few microamperes and the current gain is an undefined quantity. Output impedance values are comparable for both the BJT and FET circuits id

G +

D +

rd

G +

id

D

+

– Vgs

gmVgs

rd

Vds

Vgs

Vds

mVgs

+ –

–

–

–

S

S

(a)

(b)

A simple common-source amplifier is shown in Fig. 9.66(a), and the associated small signal equivalent circuit using the voltage-source model of FET is shown in Fig. 9.66(b). Source resistor (Rs) is used to set the Q-point but is bypassed by CS for mid-frequency operation. From the small signal equivalent circuit, the output voltage, – RD Vo = _______ mVgs RD + rd

(9.103)

VDD

RD

+

D G S

+ Vi

RG

Vo

Rs

CS

–

– (a)

where Vgs = Vi, the input voltage. Hence, the voltage gain, Vo – m RD AV = ___ = _______ Vi RD + rd

(9.104)

From Fig. 9.66(b), Input Impedance is given by Zi = RG For voltage divider bias as in CE Amplifiers of BJT RG = R1 || R2 Output Impedance is the impedance measured at the output terminals with the input voltage Vi = 0. From Fig. 9.66(b), when Vi = 0, Vgs = 0 and hence mVgs = 0 Then the equivalent circuit for calculating Output Impedance is given in Fig. 9.66 (c). Output impedance

Zo = rd || RD

Normally rd will be far greater than RD. Hence,

Zo ª RD

In the CS amplifier of Fig. 9.66(a), let RD = 5 k , RG = 10 M , = 50, and rd = 35 k . Evaluate the voltage gain AV, input impedance Zi and output impedance Zo.

Solution

The voltage gain, Vo – m RD AV = ___ = _______ Vi RD + rd – 50 × 5 × 103 = ________________ 5 × 103 + 35 × 103 – 250 × 103 = __________ = – 6.25 40 × 103

The minus sign indicates a 180° phase shift between Vi and Vo. Input Impedance

Zi = RG = 10 MW

Output Impedance

Zo ª RD = 5 kW

A FET amplifier in the common-source configuration uses a load resistance of 500 k . The ac drain resistance of the device is 100 k and the transconductance is 0.8 mAV–1. Calculate the voltage gain of the amplifier.

Solution Given load resistance,

RL = RD = 500 kW, rd = 100 W, gm = 0.8 mAV–1

The transconductance

m = gmrd = 0.8 × 10 – 3 × 100 × 103 = 80 mRD – 80 × 500 × 103 40 × 106 AV = – _______ = ___________________ = _________3 = – 66.67 3 3 RD + rd 500 × 10 +100 × 10 600 × 10

The voltage gain,

A simple common-drain amplifier is shown in Fig. 9.67(a) and the associated small signal equivalent circuit using the voltage-source model of FET is shown in Fig. 9.67(b). Since voltage Vgd is more easily determined than Vgs, the voltage source in the output circuit is expressed in terms of Vgd using Thevenin’s theorem. The output voltage, mRs Vgd Rs m Vo = __________ × _____ Vgd = _____________ r m+1 d (m + 1) Rs + rd Rs + _____ m+1 where Vgd = Vi, the input voltage.

(9.105)

Hence, the voltage gain, Vo mRs AV = ___ = _____________ Vi (m + 1) Rs + rd

(9.106)

VDD

D G

Vi

+

S

+ RG

RS

Vo

–

– (a)

Zi = RG From Fig. 9.67(b), Output Impedance measured at the output terminals with input voltage Vi = 0 can be simply calculated from the following equivalent circuit. m As Vi = 0; Vgd = 0; _____ Vgd = 0 m+1 rd _____ Output Impedance Zo = || Rs m+1 when m >> 1 (typical value of m = 50) rd 1 ___ Zo ª __ m || Rs = gm || Rs

In the CD amplifier of Fig. 9.67(b), let Rs = 4 k , RG = 10 M , = 50, and rd = 35 k . Evaluate the voltage gain AV, Input Impedance Zi and Output Impedance Zo.

Soution

The voltage gain, Vo mRs AV = ___ = _____________ Vi (m + 1) Rs + rd 50 × 4 × 103 = _________________________ = 0.836 (50 + 1) × 4 × 103 + 35 × 103

The positive value indicates that Vo and Vi are in-phase and further note that AV < 1 for CD amplifier. Input Impedance

Zi = RG = 10 MW

Output Impedance

1 Zo = ___ gm || Rs

rd = __ || Rs

( )

35 × 103 Zo = ________ || 4 × 103 = 595.7 50

A simple common-gate amplifier is shown in Fig. 9.68(a) and the associated small signal equivalent circuit using the current-source model of FET is shown in Fig. 9.68(b).

From the small signal equivalent circuit by applying KCL, ir = id – gm Vgs. Applying KVL around the outer loop gives Vo = (id – gmVgs) rd + Vgs But Thus,

– Vo Vsg = –Vgs = Vi and id = ____ RD – V o Vo = ____ + gmVi rd + Vi RD

(

Hence, the voltage gain, Vo (gmrd + 1) RD AV = ___ = ____________ Vi RD + rd

)

(9.107)

Figure 9.68(b) is modified for calculation of input impedance as shown in Fig. 9.68(c). Current through rd is given by Ird = –Ir = I1 + gmVgs I1 = Ird – gmVgs where

Vi – Vo Ird = _______ r d

Vi – IRD RD = __________ r d

Vi – IRD RD I1 = __________ – gmVgs r

Hence

d

From Fig. 9.68(c), Vi = –Vgs Vi – IRD RD I1 = __________ + gmVi r d

Vi ______ IRDRD = __ + gmVi r – r d

d

Vi IRDRD __ I1 + ______ rd = rd + gmVi From Fig. 9.68(c), I1 = IRD Therefore,

[

] [

rd + RD 1 I1 _______ = Vi __ rd rd + gm

]

Vi ________ rd + RD __ = = Zi I1 1 + gm rd From Fig. 9.68(c), Zi = Rs || Zi r d + RD = Rs || ________ 1 + gm rd In practice rd >>RD and gmrd >> 1 Therefore,

rd Zi = Rs || ____ gm rd

Therefore,

1 Zi = Rs || ___ g m

It is the impedance seen from the output, terminals with input short circuited. From Fig. 9.68(c), when Vi = 0, Vsg = 0, the resultant equivalent circuit is shown in Fig. 9.68(d).

rd

RD

Zo = rd || RD as

rd >> RD Zo

RD

(d)

Zo

In the CG amplifier of Fig. 9.68(b), let RD = 2 k , Rs = 1 k , gm = 1.43 × 10–3 mho, and rd = 35 k . Evaluate the voltage gain AV, input impedance Zi and output impedance Zo.

Solution

The voltage gain, Vo (gmrd + 1) RD AV = ___ = ____________ Vi R D + rd (1.43 × 10 – 3 × 35 × 103 + 1) 2 × 103 = 2.75 = _______________________________ 2 × 103 + 35 × 103

Input Impedance

1 Zi = Rs || ___ g m

103 = 1 × 103 || ___ 1.4 = 0.41 kW Output Impedance

Zo ª RD = 2 kW

From the drain and transfer characteristics of the Field Effect Transistor shown in Figs. 7.3 and 7.5, the drain current of an FET is a function of Drain to Source voltage (vDS) and Gate to Source Voltage (vGS). The linear small signal equivalent circuit for FET can be drawn analogous to the BJT. Assuming varying currents and voltages for an FET, iD = f (vGS, vDS)

(9.108)

If both gate and drain voltages are varied, the change in drain current is given approximately by first two terms in the Taylor’s series expansion of Eqn. (9.108) ∂iD DiD = ____ ∂vGS

( )

VDS

∂iD DVGS + ____ ∂vDS

( )

VGS

DvDS

(9.109)

In small signal notation as for BJT, DiD = id, DvGS = vgs and DvDS = vds so that Eqn. (9.109) can be written as 1 id = gmvgs + __ r vds

(9.110)

d

where mutual conductance or transconductance of the FET is defined as ∂iD gm = ____ ∂vGS

DiD ª _____ DvGS VDS

( ) ( ) ( ) VDS

id = ___ vgs

VDS

(9.111)

and drain (or output) resistance of the FET is defined as ∂vDS rd = ____ ∂iD

DvDS ª _____ DiD VGS

( ) ( ) ( ) vds = ___ id VGS

(9.112)

VGS

The reciprocal of rd is the drain conductance gd. An amplification factor m for an FET may be defined as ∂vDS m = – ____ ∂vGS

(

DvDS ª – _____ DvGS ID

) (

) ( ) ID

vds = – ___ vgs

(9.113)

id = 0

From Eqn. (9.110) by setting id = 0, it can be verified that m, rd and gm are related by m = gmrd

(9.114)

A small-signal model for FET in common source configuration can be drawn satisfying Eqn. (9.110) as shown in Fig. 9.69. id

Gate G +

Vgs

gmVgs

rd

D + Drain

Vds

– Source S

– S

This low frequency model for FET has a Norton’s output circuit with a dependent current generator whose magnitude is proportional to the gate-to-source voltage. The proportionality factor is the transconductance ‘gm’. The output resistance is rd. The input resistance between the gate and source is infinite, since it is assumed that the reverse biased gate draws no current. For the same reason, the resistance between gate and drain is assumed to be infinite. The h-parameter model of a BJT in CE configuration is redrawn in Fig. 9.70 for comparison. Comparing circuits of Figs 9.69 and 9.70, the BJT also has a Norton’s output circuit, but the current generated depends on the input current and not on the input voltage as in FET. There is no feedback from output to input in the FET, whereas a feedback exist in the BJT through the parameter hre. The high (almost infinite) input resistance of the FET is replaced by an input resistance of about 1 kW for a CE amplifier.

B

lB

hie

lc

C +

+

+

Vb

hreVc

hfelb

Vc

hoe

–

–

–

E

E

Due to the high input impedance and the absence of feedback from output to input, FET is a much more ideal amplifier than the BJT at low frequencies. This becomes invalid beyond the audio range as the low frequency model of FET shown in Fig. 9.69 is not valid in the high frequency range.

The high frequency model of an FET is shown in Fig. 9.71. This high frequency model is identical with the low frequency model except that the capacitances between the various terminals (gate, source and drain) have been added. The capacitor Cgs represents the barrier capacitance between the gate and source and Cgd represents the barrier capacitance between the gate and drain. The capacitor Cds is the drain-to-source capacitance of the channel. Because of these internal capacitances feedback exists between the output and input circuits of the FET and the voltage amplification drops drastically with increase in frequency.

G

D Cgd

gmVgs

Cgs

rd

Cds

S

The function of a differential amplifier is to amplify the difference between two signals. The need for differential amplifier arises in many physical measurements where response from d.c. to many Megahertz is required. Moreover, it is the basic input stage of an integrated amplifier. Figure 9.72 shows the basic block diagram of a differential amplifier in which there are two input terminals and one output terminal.

S

V1 V2

+

A –

Vo

The output signal in a differential amplifier is proportional to the difference between the two input signals. Vo = Ad (V1 – V2)

(9.115)

If V1 = V2, the output voltage is zero. A non-zero output voltage is obtained if V1 and V2 are not equal. The difference mode input voltage is defined as Vd = (V1 – V2) and the common mode input voltage is (V1 + V2) defined as Vcm = _________. 2 These equations show that if V1 = V2, the differential mode input signal is zero and common mode input signal is Vcm = V1 = V2. For example, if V1 = +20 mV and V2 = –20 mV, then the differential mode voltage is Vd = 40 mV and the common voltage is Vcm = 0. However, if V1 = 120 mV and V2 = 80 mV, then the differential mode input signal is still Vd = 40 mV, but the common mode input signal is Vcm = 100 mV. For both the sets of input voltages, the output voltage of an ideal differential amplifier would be exactly the same. However, in practice the common mode input signal will affect the output. In the design of differential amplifier one goal is to minimize the effect of common mode input signal.

The basic Differential Amplifier is shown in Fig. 9.73(a). The amplifier has two input signals V1 and V2 and a single output Vo. For the purpose of signal analysis, they can be represented by its input resistance Rid, output resistance Ro, and controlled voltage source as shown in Fig. 9.73(b). Here A is the open circuit voltage gain, Vid = (V1 – V2) is the differential mode input voltage.

The signal voltage developed at the output of the amplifier is in phase with the voltage applied to the positive input terminal and 180° out of phase with the signal applied to the negative input terminal. The V1 and V2 terminals are therefore refered to as non-inverting input and inverting input respectively. Hence the output of the diffrential amplifier is written as Vo μ (V1 – V2) i.e.,

Vo = A (V1 – V2)

From Fig. 9.73(b), the Thevenin resistance and output voltage are RL Rth = ________ Ro + RL

and

RL Vo = AVid ________ Ro + RL

(9.116)

Rid Vid = Vs _______ Rid +Rs RL Rid Vo = AVs ________ ________ Rid + Rs Ro + RL Vo ARid RL AV = ___ = ________ ________ Vs Rid + Rs Ro + RL The operational amplifier circuits are d.c.-coupled amplifiers and the signals V and Vs may have a d.c. component that represents a d.c. shift of the input away from Q-point. The op-amp amplifies not only the a.c. components of the signal but also the d.c. component, and hence the amplitude and phase of the signal determine AV. An ideal differential amplifier produces an output that depends purely on the voltage difference (Vid) between its two input terminals, and this voltage would be independent of the source and load resistance. Therefore, Rid RL ________ = 1 and ________ = 1 Ro + RL Rid + Rs From Eqn. (9.116)

Vo = AVid

Vo AV = ___ = Ad Vid were Ad is the differential voltage gain. Therefore, Therefore,

Vo = AV (V1 – V2)

Hence, if V1 = V2, the output voltage is zero; if V1 and V2 are not equal, a non-zero output voltage is obtained. However, a practical differential amplifier cannot be described by the above equation because the output voltage depends on the average level called common mode signal, which is given by V1 + V2 VC = _______ 2 Considering the common mode alone, the output of the differential amplifier can be given as Vo = ACVC where AC is the common mode gain. Hence the total output of any differential amplifier can be given as Vo = AdVid + ACVC

(9.117)

The differential amplifier is said to be operated in a common mode configuration when the same voltage is applied to both the inputs i.e. V1 = V2. One of the main requirements of the differential amplifier is to cancel or reject the noise signal that appears as a common input signal to both the input terminals of the differential amplifier. Hence a figure of merit called Common

Mode Rejection Ratio (CMRR is introduced to define the ability of a differential amplifier to reject a common mode signal. CMRR is defined as the ratio of the differential voltage gain Ad to common mode gain AC and is generally expressed in dB.

| |

Ad CMRR = 20 log10 ___ AC

(9.118)

In ideal cases, since Ac = 0, CMRR = • and in practical cases, since Ad >> Ac, CMRR is high, though finite. Therefore, Vo = AdVid + AcVc

[ [ [

AcVc = AdVid 1 + ______ Ad Vid

]

Vc 1 = AdVid 1 + _______ ___ (Ad /Ac) Vid

] ]

Vc 1 Vo = AdVid 1 + _______ ___ CMRR Vid

(9.119)

where CMRR is not expressed in (dB). As CMRR approaches •, the output voltage becomes Vo = AdVid Here the common mode voltage is nullified to a greater extent.

The differential amplifiers using BJT are broadly classified into two types namely (i) differential BJT amplifier with resistive loading and (ii) differential BJT amplifier with active loading. The emitter coupled or source coupled differential amplifier forms the input stage of most analog ICs. The Emitter-coupled differential amplifier circuit is shown in Fig. 9.74. It is important to note that the performance of a differential amplifier depends on the ideal matching of the transistor pair, Q1 and Q2. The amplifier uses both a positive power supply +VCC and a negative power supply –VEE. Though in practical situations the power supplies are equal in magnitude, it need not be the case always. It is to be mentioned that these amplifiers operate even at d.c., because appropriate d.c. level shifting could be obtained without the use of coupling capacitors. The d.c. analysis begins with the assumption that Q1 and Q2 are ideally matched, and the mismatching effects will be considered later. Here, we consider b >>1 so that – iE1 ª iC1 and hence

and

–iE2 ª iC2

VI1 = VBE1 – VBE2 + VI2

In the d.c. analysis, the operating point values i.e. ICQ and VCEQ can be obtained for Q1 and Q2. The d.c. equivalent circuit can be derived by making a.c. inputs zero as shown in Fig. 9.75.

For matched transistor pairs, we have • since RE1 = RE2, RE = RE1||RE2 • RC1 = RC2 = RC • |VCC| = |VEE| For a symmetrical circuit with matched transistors, IC1Q = IC 2Q and VCE1Q = VCE2Q. Hence it is enough finding out operating point ICQ and VCEQ for any one of the two transistors. Any symmetrical circuit as shown in Fig. 9.76 will be suitable for a.c.-analysis. + VCC

+ VCC

RC

RC Vo

Vo

Q1 Rs

Q1 Rs

lb

lb

+ Vs 2

2RE

Vs1 –

+ –

– VEE

– VEE

Consider Fig. 9.75 for the d.c. analysis. Applying KVL to base-emitter loop of Q, we get IBRs + VBE + 2IERE = VEE

Therefore,

IC IE As b = __ for common emitter and IC ª IE, b = __ IB IB IE __ R + VBE + 2IERE = VEE b s

[

]

Rs IE ___ + 2 RE = VEE – VBE b VEE – VBE IE = __________ Rs ___ + 2RE b

(

Rs In practical conditions, ___ VBE, IE can be approximated by VEE 15 IE ª _____ = ___________3 = 115.38 mA 2 REE 2 × 65 × 10 Find the Q-point for the MOSFETS in the differential amplifier shown in Fig. 9.88 with VDD = VSS = 12 V, ISS = 175 A, RD = 65 k , Kn = 3m A/V2 and VTN = 1 V. What is the maximum VIC for which M1 remains saturated?

+ VDD

RD

RD VD1 +

VD2 VoD

–

M1

+ –

M2

V1

+ –

lSS

V2

– VSS

Solution ISS IDS = ___ = 87.5 mA 2 ___

VGS VDS

÷

__________

÷

ISS 175 × 10–6 = VTN + ___ = 1 + _________ = 1.242 V Kn 3 × 10–3 = VDD – IDSRD + VGS = 12 – (87.5 × 10 – 6 A)

+3

(65 × 10 ) + 1.242 = 7.55 V Checking for saturation, VGS – VTN = 0.242 V and VDS ≥ 0.2. Thus both transistors in the differential amplifier are baised at Q-point of (87.5 mA, 7.55 V). Requiring saturation of M1 for non zero VIC, VGD = VIC – (VDD – IDSRD) £ VTN VIC £ VDD – IDRD + VTN = 12 – (87.5 × 10–6)(65 × 103) + 1 = 7.31 V

Calculate the operating point values, differential gain, common mode gain, CMRR, output if Vs1 = 60 mV (peak to peak) at 1 kHz and Vs2 = 40 mV (peak to peak) at 1 kHz for the differential amplifier shown in Fig. 9.89. Assume the transistor is made of silicon with hie = 3.2 k .

Solution b = hfe = 100 VEE – VBE IE = _________ Rs 2 RE + ___ b 12 – 0.7 = _________________ = 1.009 mA 120 2 × 5.6 × 103 + ____ 100 IC ª IE = 1.009 mA Therefore,

ICQ = 1.009 mA VCE = VCC + VBE – ICRC = 12 + 0.7 – (1.009 × 10–3 × 4.5 × 10–5) = 8.16 V

and The differential gain is

VCEQ = 8.16 V hfe RC 100 × 4.5 × 103 Ad = _______ = ______________3 = 135.54 RS + hie 120 + 3.2 × 10

Common mode gain is hfe RC AC = ____________________ 2 RE (1 + hfe) + Rs + hie 100 × 4.5 × 103 = _________________________________ = 0.3966 2 × 5.6 × 103 (1 + 100) + 120 + 3.2 × 103

Ad 135.54 CMRR = ___ = ______ = 341.755 AC 0.3966

| |

Ad CMRR = 20 log ___ = 50.674 dB Ac The output voltage is

Vo = AdVd + ACVC.

Here

Ad = Vs1 – Vs2 = 60 × 10–3 – 40 × 10–3 = 20 mV (p – p)

Then,

Vs1 + Vs2 60 × 10–3 + 40 × 10–3 VC = ________ = __________________ = 50 mV (p – p) 2 2

Therefore, Vo = 135.54 × 20 × 10–3 + 0.3966 × 50 × 10–3 = 2.73 V (p – p)

In the circuit shown in Fig. 9.90(a), the transistor has hie = 400 25 × 10–6. Calculate Ri, R¢L, AV, AVs, Ro.

Solution

, hre = 2.1 × 10–4, hfe = 40 and hoe =

In this circuit, R¢L = hoe (RL||RC); 25 × 10–6 × (5 k || 3 k) = 0.047 W

Here R¢L is less than 0.1 W. So, the h-parameter equivalent circuit is used to analyze the given circuit. It is obtained by replacing all capacitors and the d.c. source with short circuits and replacing the transistor with its h-parameter equivalent circuit shown in Fig. 9.90(b). Input resistance, Output Resistance,

Ri = hie || 100 k = 400 || 100 k = 398.4 W Ro = 50 k || 3 k || 5 k = 1807.2 W Vo ___ Vo ___ Vi ___ = × Vs Vi Vs

– hfe R¢L Vo _______ ___ = Vi hie Therefore, In the equivalent circuit,

– hfe (Ro) – 40 × 1807.2 Vo ________ ___ = = ____________ = – 180.72 Vi 400 hie Vs Ri Vi = _______ Ri + Rs Vi _______ Ri 398.4 ___ = = _______________ = 0.2849 Vs Ri + Rs 398.4 + (1 × 103)

Hence, Vo Vo Vi AVs = ___ = ___ ___ = 180.72 × 0.2849 = 51.48 Vs Vi Vs

If the voltage or power gain obtained from a single stage small signal amplifier is not sufficient for a practical application, one have to use more than one stage of amplification to achieve necessary voltage and power gain. Such an amplifier is called a multistage amplifier. In multistage amplifier, the output of one stage is fed as the input to the next as shown in Fig. 10.1. Such a connection is commonly referred to as cascading. In amplifiers, cascading is also done to achieve correct input and output impedances for specific applications. Depending upon the type of amplifier used in individual stages, multistage amplifiers can be classified into several types. A multistage amplifier using two or more single stage common emitter amplifier is called as cascaded amplifiers. A multistage amplifier with common emitter as the first stage and common base as the second stage is called as cascode amplifier. Such cascade and cascode connections are also possible in FET amplifiers. Rs Vs –

Vi

Source

First Stage

Second Stage

Two stage cascade amplifier

Vo

RL

+

Load

When amplifiers are cascaded, it is necessary to use a coupling network between the output of one amplifier and the input of the following amplifier. This type of coupling is called inter stage coupling. Basically, these coupling networks serve the following two purposes. (1) It transfers the a.c. output of one stage to the input of the next stage. (2) It isolates the d.c. conditions of one stage to the next.

The three coupling schemes commonly used in multistage amplifiers are: It is the most commonly used discrete device amplifiers as it is least expensive and has satisfactory frequency response. In this method, the signal developed across the collector resistor Rc of each stage is coupled through capacitor Cc into the base of the next stage as shown in Fig. 10.2(a). The coupling capacitor Cc isolates the d.c. conditions of one stage from the following stage. The amplifiers using this coupling scheme are called RC-coupled amplifiers. In this method, the primary winding of the transformer acts as a collector load and the secondary winding transfers the a.c. output signal directly to the base of the next stage as shown in Fig. 10.2(b). Such a coupling increases the overall circuit gain and the level of inter stage impedance matching. However, transformers with broad frequency response are very expensive and hence, this type of coupling is restricted mostly to power amplifiers where efficient impedance matching is a critical requirement for maximum power transfer and efficiency. The amplifiers using this coupling scheme are called Transformer-coupled amplifiers. In this method the a.c. output signal is fed directly to the next stage as shown in Fig. 10.2(c). No reactance is included in the coupling network. Special d.c. voltage level circuits are used to match the output d.c. levels. It is used when amplification of low frequency signals is to be done. Further, coupling devices such as capacitors, transformers cannot be used at low frequencies because their size becomes very large. The amplifiers using this coupling schemes are called direct-coupled amplifiers or d.c. amplifiers. +VCC

+VCC

RB2

RC1 Cc

RB1

RC2 Vo Q2

Vin

+VCC

Q1

+VCC

+VCC

+VCC

Vo RB

Q2

TR

RB1

RB2

RC1

RC2 Vo Q2

Vin

Q1

(b) Transformer coupling

Vin

Q1

(c) Direct coupling

The voltage gain of the amplifier and the phase shift of the gain depend on the frequency range over which the amplifier operate. In general the entire frequency range can be divided into three ranges: (1) Mid frequency range, (2) Low frequency range, and (3) High frequency range. In this frequency range the voltage gain is practically constant, that is not 1 affected by the changes of the capacitances in the circuit. The reactance ____ of the coupling capacitor wCc in series between the amplifying stages is very small so that it can be neglected. The reactances of the internal capacitances of the transistor are very large because these capacitances have very small values and as these equivalent capacitances come in parallel with the associated resistances, they are not considered in this high frequency range. Thus, in the mid frequency range all the capacitive reactances are neglected as compared with the associated resistances. In this frequency range, the circuit behaves like the simple high pass circuit as shown in Fig. 10.3 with time constant t1 = R1C1. Vo R1 1 AOL = ___ = ___________ = ____________ Vi 1 1 1 – j ______ R1 – j ____ wC1 wR1C1

( )

(

C1 +

)

+

V

R

V

o i 1 Therefore, the voltage gain at low frequency, AOL, is expressed as 1 1 AOL = ________ , where fL = _______ – – 2pR f__ 1C 1 L 1–j f Therefore, the magnitude of the voltage gain at low frequency response is 1 ________ |AOL| = _________ fL 2 1 + __ f fL and the phase is q1 = –tan–1 __ f 1__ At f = fL, AOL = ___ = 0.707 whereas at midband frequency, AOL = 1. Therefore, the frequency, at which ÷2 gain is 0.707 times its midband value AO, is called fL. This drop corresponds to a decibel reduction of 20 log (0.707) or 3 dB and hence fL is called lower 3 dB cutoff frequency.

( )

( )

÷ ()

Above the midband frequency, i.e. f >> fH, the transistor behaves like the simple low pass circuit, which is shown in Fig. 10.4, with time constant t2 = R2C2. 1 _____ jwC V 2 o 1 AOH = ___ = ___________ = __________ + + Vi 1 + jwR 1 2C2 R2 R2 + _____ jwC2 1 Vo Vi C2 _____________ AOH = 1 + j 2 p fR2 C2

( ) ( )

Therefore, the voltage gain at high frequency, AOH, is expressed as 1 1 AOH = _________, where fH = _______ 2pR f 2C2 1 + j __ fH

( )

–

–

Therefore, the magnitude of the voltage gain at low frequency response is 1 _________ |AOH| = __________ f 2 1 + __ fH

÷ ( )

and the phase is

( )

f q2 = –tan–1 __ fH

1__ At f = fH, AOH = ___ = 0.707, i.e. the gain ÷2 is reduced to 0.707 times its midband value AO. Hence fH is called the upper 3 dB cutoff frequency. The values q1 and q2 represents the angle by which the output lags the input signal. The frequency response of the transistor RC coupled amplifier is shown in Fig. 10.5. The frequency range between fL and fH is called the bandwidth of the amplifier.

20 log10

A AVm

0

–10 –20 –30 –40 0.010.1

1

10

f/fL

0.1

1

10 100

f/fH

The most popular cascade amplifier is formed by cascading several CE amplifier stages. Before considering the analysis of any specific type of multistage amplifiers, the analysis of a general ‘n’ stage CE amplifier shown in Fig. 10.6 is done in this section. Biasing arrangements and coupling elements are omitted for simplicity. The expressions for quantities such as voltage gain, current gain, power gain, input impedance and output impedance of this ‘n’ stage CE amplifier are to be derived. In a multistage amplifier, the output voltage of the first stage acts as the input voltage of second stage and so on. The voltage gain of the complete cascade amplifier is equal to the product of the voltage gains of the individual stages. The voltage gain of the first stage __

__

AV1

output voltage of the first stage V2 ___________________________ __ = = ___ input voltage of the first stage V1 = AV1 – q1

where AV1 is the magnitude of voltage gain and q1 is phase angle of the output voltage relative to input voltage. Similarly, __ __

AV2

V3 ______________________________ output voltage of the second stage __ = = ___ input voltage of the second stage V2 = AV2 – q2

+

Similar expressions can be written for all the ‘n’ stages of the cascade amplifier. The resultant voltage gain, __ __ V0 output voltage of the nth stage ___ AV = __ = ___________________________ V1 input voltage of the first stage = AV –q But

__

__

__

__

__

__

V0 ___ Vn V0 V2 V3 ___ V4 ___ __ = __ × ___ __ × __ ... ______ __ __ × ___ VI V1 V2 V3 V(n – 1) Vn Hence, it follows that

__

__

__

__

__

AV = AV1 ◊ AV2 ◊ AV3 ... AVn

(10.1)

= AV1 ◊ AV2 ◊ AV3 ... AVn ... –q1 + –q2 + –q + ... –qn = AV – q

Hence,

AV = AV1 . AV2 . AV3 ... AVn

(10.2)

q = q1 + q2 + q3 + ... + qn

and

(10.3)

From Eqns (10.2) and (10.3), one can conclude that (i) the magnitude of the resultant voltage gain equals the product of the magnitudes of the voltage gains of the individual stages, and (ii) the phase shift of the resultant voltage gain equals the sum of the phase shifts of the individual stages comprising the multistage cascade amplifier. Figure 10.7 shows a particular stage, say, the Kth stage, say of the n stage cascaded amplifier. From Eqn. (10.3), the voltage gain of the Kth stage is given by __

__

AVK

AIK RLK = ________ RiK

(10.4)

where RLK is the effective load impedance at the collector of the Kth stage and RiK is the input impedance of the Kth stage. Ic (K – 1)

Ibk

ICK BK

Rc (k – 1)

CK

th

Vk

K Stage

EK

RCK

Vk + 1

EK

__

The terms AIK, RLK and RiK may be evaluated by starting from the last stage and proceeding backward to the first stage.

From the Eqn. (9.19), the current gain – hfe AIn = __________ 1 + hoe RLn and from Eqn. (9.21), Rin = hie + hre AIn RLn where RLn is the effective load impedance for the last stage and equals RCn. The effective load impedance RL (n – 1) of the (n – 1)th stage is equal to RC (n – 1) || Ri(n) Thus,

RC (n – 1) × Ri (n) RL (n – 1) = _____________ RC (n – 1) + Ri (n)

(10.5)

Having known RL(n–1) AI(n–1) can be found out from – hfe AI(n – 1) = _____________ 1 + hoe RL (n – 1) and Ri(n – 1) can be found from

(10.6)

Ri (n – 1) = hie + hre AI(n – 1) RL(n – 1)

(10.7)

By proceeding in this manner, one can calculate the current gain and input impedance of each stage including the first. The voltage gain of each stage can be obtained from Eqn. (10.4) for that stage. In order to find the resultant voltage gain, the voltage gain of the individual stages can be found out and the product of these gains gives the resultant voltage gain. Alternatively, the resultant voltage gain can be found directly by the relation __

AIRCn AV = ______ Ri1 __

__

where AI is the current gain of the complete n-stage amplifier. __ Now, AI is given by _ _ __ Io –____ ICn ___ AI = _ = _ Ib1 Ib1 _

_

_

_

–____ ICn ____ – Ic1 Ic2 ______ ICn _ _ ◊◊◊ _ = _ ◊ ___ Ib1 Ib1 Ic1 IC (n – 1)

Now, or

__

__

__

__

__

AI = AI 1 ◊ AI¢ 2 ◊ AI¢ 3 ... AIn ¢

_

– Ic1 _ , Here, AI 1 is the base to collector gain of the first stage and equals ____ Ib1 __

__

__

while AI¢2, AI¢3 are the collector to collector current gains of second and third stages. For Kth stage the collector to collector current gain is given by _

ICK _ AIK ¢ = _______ Ic (K – 1) __

(10.8)

For the same Kth stage, the base to collector current gain is given by _ __ ICK ___ AIK = _ IbK These two current gains can be related by the equation, RC (K – 1) __ __ AIK = AIK _____________ RC (K – 1) + RiK

(10.9) __

This may be substituted in Eqn. (10.8) to give the resultant current gain AI. __ The procedure for calculating the resultant current gain AI is as follows. __ (i) Find the base to collector current gain AIn for the last stage, i.e. nth stage using – hfe __ AIn = __________ 1 + hoe RLn (ii) Find input impedance, Rin = hie + hre AIn RLn (iii) Calculate the effective load resistance RL(n–1) for the last stage RL(n–1) = RC(n–1) || Ri(n) (iv) Calculate

– hfe AI (n – 1) = _____________ 1 + hoe RL (n – 1) __ Proceed in this manner to find AIK __

__

(v) Find the collector to collector current gain AIK for the Kth stage using RC (K –1) __ __ __ AIK = AIK ____________ RC(K – 1) + RiK __

(vi) Find the resultant current gain AI of the n-stage cascaded amplifier using __

__

__

AI = AI1 AI 2 AI 3

AIn

The power gain of n-stage amplifier is given by __ output power of last stage AP = _______________________ input power of first stage __ _

__ _

Vo Io _____ VoIcn _ = __ _ = _____ V1Ib1 V1Ib1 __ __

= AV AI Substituting

(10.10)

Rcn AV = AI ___ Ri1 __

__

__ Rcn AP = ( AI )2 ___ Ri1 By starting from last stage and proceeding towards the first stage, the input impedance can be found out as follows. __

– hfe __ Find (i) AIn = __________ 1 + hoe RLn __

__

(ii) Rin = hie + hre AInRLn __

(iii) RL (n – 1) = RC(n – 1)||Ri(n) __

RL (n –1) is the effective load impedance of the (n – 1)th stage. __

__

__

(iv) Calculate AI (n – 1), Ri (n – 1) and RL (n – 2) from the above equations. (v) Proceed in this manner to find the effective input impedance (Ri ) of the first stage. The output impedance of each transistor amplifier stage and that of the complete multistage amplifiers may be calculated starting from the first stage. From Eqn. (9.27), the output admittance of first transistor, hfe hre (10.11) Yo1 = hoe – _______ hie + Rs 1 Ro1 = ____ gives the output impedance of the first transistor. Yo1 Parallel combination of Ro1 with Rc1 forms the output impedance of the first stage. Ro1 Rc1 Rot1 = _________ Ro1 + Rc1 This Rot1 forms the source impedance of the second stage. Once again use Eqn. (10.11) to find Yo2 with Rs replaced by Rot1. 1 Find Rot2 = Ro2 || Rc2, where Ro2 = ____ Yo2 Similarly, proceed to find output impedance of the last stage. The above methods can be used for common base and common collector configurations, also as well as for combination of these three configurations.

For the two stage CE-CC amplifier circuit shown in Fig. 10.8, find the input and output impedance and individual as well as overall current gains and voltage gains. The h-parameters of the transistors at the quiescent points are hie = 1600 ; hfe = 60, hre = 5 × 10–4, hoe = 25 A / V, hic = 1600 ; hfc = –61, hrc = 1 and hoc = 25 A/V.

Solution

The a.c. equivalent circuit of the CE-CC amplifier is shown in Fig. 10.9(a).

As shown in Fig. 10.9(b), the collector resistance of the first stage is shunted by the input impedance of the next stage. Compute the current gain, the input impedance and the voltage gain of the second stage and then proceed towards the first stage. The output impedance can be calculated by starting the analysis with the first stage and proceeding towards the output stage, i.e. second stage. The second stage Current gain The current gain of a particular stage is given by

Ic2

Ie2 +

Ib2 Ib1

B + 1

Rs

+

Q1

B2 +

V2

Q2 E2

RE2

Vo

Rc1 Vs

V1

–

E1

C2

–

Ri1

–

–

Ro1

Rot 2

Ro2

Rot1 Ri2

(a) AC equivalent circuit of CE-CC amplifier

Ic1

Ib2 B2

Rc1

Ri 2

hf AI = – ________ 1 + hoZL For the second stage ZL = RE2 and the current gain of the second stage is – hfc – Ie2 AI2 = ____ = __________ Ib2 1 + hoc RE2 61 = __________________ 1 + 25 × 10–6 × 4000 = 55.45 The input impedance Ri of a particular stage is given by Ri = hi + hr AIZL For the second stage, Ri2 = hic + hrc AI2 RE2 = 1600 + 1 × 55.45 × 4000 = 223.4 kW Thus, the CC stage has a high input impedance. The voltage gain of a particular stage is

For the second stage,

AIZL AV = _____ Zi Vo AI2 RE2 AV2 = ___ = _______ V2 Ri2 55.45 × 4000 = ____________ = 0.993 223.4 × 103

The First Stage RL1 = Rc1 || Ri2 4000 × 223.4 × 103 = _________________3 = 3.92 kW 4000 + 223.4 × 10 Current gain, – Ic1 – hfe AI1 = ____ = __________ Ib1 1 + hoe RL1 – 60 = _______________________ = – 54.6 1 + 25 × 10–6 × 3.92 × 103 The input impedance of the first stage, which is also the input impedance of the cascaded amplifier is Ri1 = hie + hreAI1RL1 = 1600 + 5 × 10–4 × (–54.6) × 3.92 × 103 = 1.71 kW

The voltage gain of the first stage is V2 AI1 RL1 AV1 = ___ = _______ V1 Ri1 – 54.6 × 3.92 × 103 = ________________ = – 125.16 1.71 × 103 The output admittance of the first transistor Q1 hfe hre Yo1 = hoe – _______ hie + RS 60 × 5 × 10–4 = 25 × 10–6 – ____________ 1600 + 600 = 11.4 mA / V The output impedance of the first stage 1 Ro1 = ____ = 87.72 kW Yo1 The output impedance taking Rc1 into account is Rot1 = Ro1 || Rc1 87.72 × 103 × 4 × 103 = ______________________ (87.72 × 103) + (4 × 103) = 3.82 kW This is the effective source resistance R¢s2 of the second stage The output admittance of the second stage hfc hrc Yo2 = hoc – ________ hic + Rot1 (– 61) × (1) = (25 × 10–6) – __________________ (1600) + (3.82 × 103) = 25 × 10–6 + 11.5 × 10–3 = 11.525 × 10–3 A/V Output impedance, 1 Ro2 = ____ = 87W Yo2 The amplifier output impedance taking RE2 into account is Ro2 || RE 2 Hence, Ro2 × RE 2 Ro2 = _________ Ro2 + RE 2

87 × 4000 = _________ = 85.15 W 87 + 4000 The overall or total current gain of both the stages is – Ie2 – Ie2 Ib2 Ic1 AI = ____ = ____ ___ ___ Ib1 Ib2 Ic1 Ib1

( )

From Fig. 10.9(b),

Ib2 = – AI 2 ___ AI 1 Ic1 Rc1 Ib2 = (– IC1) ________ Rc2 + Ri2 Ib2 ________ – Rc1 ___ = Ic1 Rc1 + Ri2 4 × 103 = – ___________________ 4 × 103 + 223.4 × 103 = –17.6 × 10–3 Rc1 AI = AI2 AI1 ________ Ri2 + Rc1 = (55.45) (– 54.6) × 17.6 × 10–3 = –53.23

The overall voltage gain of the amplifier, Vo Vo V2 AV = ___ = ___ ◊ ___ V1 V2 V1 = AV2 AV1 = (0.993)(– 125.16) = –124.3 The overall voltage gain taking the source impedance into account, Vo Ri1 AVs = ___ = AV ________ Vs Ri1 + Rs 1.71 × 103 = (– 124.3) _______________ = – 92 1.71 × 103 + 600

The choice of transistor configuration depends on the maximum voltage gain expected from the cascade amplifier. Thus, for intermediate stages in a cascade amplifier, common collector configuration cannot be used since such a stage has a voltage gain less than unity. Common base configuration is also rarely used in the intermediate stages since the resultant voltage gain of such a cascade amplifier is also low and is almost equal to that of the last stage alone. The proof for this can be given as follows.

From Eqn. (10.4), the voltage gain, AIK RLK AVK = ________ RiK But

RLK = RCK || Ri(K + 1)

Thus,

RLK < Ri(K + 1)

Assuming the stages to be identical Ri(K + 1) = RiK, the effective load resistance RLK < RiK. Further, the maximum value of current gain AIb is hf b which is less than unity but only slightly less. Accordingly, the voltage gain of any stage (AVK) except the output stage is less than unity. Hence, for intermediate stages common base configuration is not suitable. Common emitter configuration is popularly used in the intermediate stages since the short-circuit current gain hfe is very much greater than unity. It is thus possible to obtain a high voltage gain by cascading CE stages. Here, the consideration is not the maximum voltage gain but impedance matching of the source and the input circuit of the first stage. Thus some transistors driving a cascade amplifier require almost open circuit, while others require an almost short-circuit operation. Accordingly, one may prefer CC or CB configuration as the input stage thereby securing proper impedance match and sacrificing voltage or current gain. A similar choice is made for the output stage.

Figure 10.10 shows the two stage RC coupled common emitter amplifier. The two transistors are identical and a common power supply is used. RC is the collector (load) resistor. Resistors R1, R2 and RE provide the required bias. The bypass capacitor CE prevents loss of amplification due to negative feedback. The output of the first stage gets coupled to the input of the second stage via coupling capacitor CC which also serves as the blocking capacitor to keep the d.c. component of the output of the first stage from reaching the input of the second stage and to pass ac component.

The ac input signal applied at the base is amplified by the transistor Q1 as shown in Fig. 10.10.

Its phase is reversed and the amplified output appears across its collector load RC. The output of the first stage across RC is given to the base of the second stage transistor Q2 through the coupling capacitor Cc. This signal at the base of Q2 is further amplified and its phase is again reversed. Hence the output signal is the twice amplified replica of the input signal. The output signal is in phase with the input signal becasue it has been reversed twice. In the mid-frequency range, the gain is constant because the coupling and bypass capacitors are as good as short circuits. On both sides of the mid-frequency range, the gain decreases. At high frequencies, the value b of the transistor decreases. Hence, the reactance of the capacitor Cc increases with the reduction in frequency of the signal, the voltage gain of the amplifier reduces. At very low and very high frequencies, the gain of the amplifier reduces to almost zero. 1. It requires cheap components like resistors and capacitors and not expensive or bulky components. Hence it is small, light and inexpensive. 2. It gives uniform voltage amplification over a wide frequency range from a few Hz to a few MHz because resistor values are independent of frequency changes. Hence, RC coupled amplifier can be used to great advantage in speech, music, etc. 3. Since it does not use any coil or transformer which may pick up unwanted signals, it has minimum possible nonlinear distortion. Hence, there is no magnetic field to interface with the signal. 4. Its overall amplification is higher than that of the other couplings. 1. Due to large drop across collector load resistors, the collectors work at relatively small voltages unless higher supply voltage is used to overcome this voltage drop. 2. It is noisy in humid weather. 3. The impedance matching is poor as the output impedance of the RC coupled amplifier is several hundred ohms while that of a speaker is only a few ohms. Hence, the amount of power transferred to the speaker is reduced. 1. 2. 3. 4.

Its overall amplification is higher. Its non-linear distortion is less. It has better fidelity over a wide frequency range. Its frequency response is much better over the audio frequency range.

Since audio fidelity is excellent over a wide range of frequencies, the RC coupled amplifier is extensively employed as a voltage amplifier, e.g. in the initial stages of a public address system. However, as the impedance matching is poor, reduced power is transferred to the speaker. For finding the response of the RC coupled amplifier, in the three frequency ranges, the transistor Q1 of Fig. 10.11 is replaced by its high frequency p model yielding the equivalent circuit of Fig. 10.12. Here, Cs1 and Cs2 represent stray capacitances caused by wiring, proximity of components to chassis etc. RB = R1 || R2 is the biasing resistance of a particular stage. The equivalent circuit of Fig. 10.12 may be modified by Miller’s theorem by which the parallel combination of rb¢c and Cb¢c are replaced by the corresponding impedances in the input circuit and the output circuit. The modified equivalent circuit is shown in Fig. 10.13.

+VCC

RC

R1

X1 I/P

R1

Y1

C

RC Y2

Q1 CC

X2

Z1

R2

CE

RE

R2

Q2 Z2 O/P RE

CE

As the equivalent circuit of the Fig. 10.13 is quite complicated, it may be simplified with a few assumptions as follows: (i) Making use of the fact that in most cases, the time constant of the output shunt circuit is negligible Cb c (A – 1) as compared with that of the input circuit, the capacitances __________, Cb e and Cs2 may be A omitted from the output circuit. Vce A (ii) Since A is equal to ____, |A| >> 1. Hence, rb c _____ rb c. But rb c >> rce. Vb e A–1 A A Hence, rb c _____ || rce rce and rb c _____ is omitted from the output circuit. A–1 A–1 rb c (iii) For typical values of transistor parameters and circuit components _____ >> rb e. 1–A rb c rb c Hence, _____ || rb e rb e . Hence _____ is neglected in the input circuit. 1–A 1–A (iv) From Table 11.1, 1 gce = ___ rce = hoe – (1 + hfe)gb c

(

(

)

)

)

(

hoe – hfe gb c

( )

Thus,

gce

hre = hoe – hfe ____ rb e 1 = ___ rce hoe – gmhre

1 It can be assumed that ___ rce

hoe without introducing much error. Since rce comes in shunt with 1 much smaller load resistance RC (typically 250 ) rce may be replaced by ___ = Ro (say). hoe (v) rbb and rb e can be combined to form Ri = hie. (vi) C is the parallel combination of Cb e, CS1 and Cb c (1 – A). With the above simplifying assumptions, the circuit of Fig. 10.13 reduces to equivalent circuit shown in Fig. 10.14. Let RC represent the parallel combination of Ro and RC and similarly let Ri represent the parallel combination of Ri and RB. Then the circuit reduces to that shown in Fig. 10.15.

Ib

Ib

V1

E1

Rs

B1 rbb¢

rb¢e

Rs

rb e

Cb¢e

rbb

B1

B¢1

Vb¢e

Vb e

rb¢c 1–A

cb c

rb c

Cb e + Cs1

B1

Cc(1–A)

gmVb¢e

gmVb e

rce

rce Cs2

Cc (A – 1) A

rb¢c A 1–A

C1

Cs2

Rc

Cc

Rc

Cc

RB

RB

rb e

rbb

rb¢e

rbb¢

Cb e

E2

Cb¢e

B2

E2

B2

B1

C1

B¢1

B2 +

rbb¢

Rs Vi

rb¢e

Ro

Vb¢e

C

IS

Rc

Ri Vo

RB

gm Vb¢e –

E1

E2

B1

rbb¢

rb¢e

Rs

CC

B¢1

R ¢C

C Vb¢e

IS

B2

R¢i

Vo

gmVb¢e

E2

In most cases Ro >> RC, hence, RC = RC || Ro RC. Similarly RB >> Ri, hence Ri = Ri || RB Ri leading to the circuit shown in Fig. 10.16. In those circuits where these approximations are not valid, Rc and Ri can be taken instead of RC and Ri. The analysis of RC coupled amplifier for the three frequency ranges can be done using the simplified equivalent circuit shown in Fig. 10.16. B1 +

rbb¢

CC

B¢1

B2 Io

Is

Rs Vi

rb¢e

C

Vb¢e

RC

Vo

Ri

gmVb¢e – E1

E2

In the mid-frequency range, the reactance offered by Cc is small enough so that it can be omitted. Further, the frequency is small enough to make shunt capacitor-

(

)

1 reactance XC = ___ extremely large. Hence, C can be omitted in the equivalent circuit leading to the C circuit shown in Fig. 10.17. Let Io be the current through the resistor Ri. This current I0 is the useful output current from the first stage and hence forms the input current for the next stage. B1

rbb¢

B2

Ib Io

Is

rb¢e

Rs Vi

RC

Ri

Vo

gmVb¢e E1

Current gain AIm:

E2

Io AIm = __ Ib

RC Io = – gm Vb e _______ RC + Ri

gm Vb e RC AIm = – ______ _______ Ib RC + Ri But Hence, As

Vb e = Ibrb e RC AIm = –gmrb e _______ R C + Ri gmrb e = hfe, RC AIm = –hfe _______ RC + Ri

Hence current gain AIm in the mid-band is independent of frequency. Voltage gain AVm: Vo AVm = ___ Vi Vo = –gmVb eRci = – gmIbrb eRci where

Rci = RC || Ri Vi = Ib (rbb + rb e) = Ibhie

(10.12)

(10.13)

Vo – gm Ib rb¢e Rci AVm = ___ = ____________ Vi Ib hie Substituting gmrb¢e = hfe, – hfe Rci AVm = _______ (10.14) hie In the low frequency range capacitor C is omitted since its reactance is extremely large as XC || rb¢e ª rb¢e. However, capacitor Cc cannot be neglected leading to the equivalent circuit shown in Fig. 10.18. Hence,

B1 +

Ib

CC

C1

rbb¢ Vi

Rs

B ¢1

Io

rb¢e

Is

B2

RC

Ri

Vo

gmVb¢e –

E2

E1

Current gain AIl

From Fig. 10.18,

Io AIl = __ Ib RC Io = – gmVb¢e _______________ RC + (Ri – jXCc) RC = – gmVb¢e ______________ 1 RC + Ri + _____ j wCc RC = – gm Ib rb¢e ______________ 1 RC + Ri + _____ j wCc

Hence the current gain, RC Io AIl = __ = – gm rb¢e ______________ Ib 1 RC + Ri + _____ j wCc RC = – hfe ______________ 1 RC + Ri + _____ j wCc or

–hfe RC RC + Ri = _______ ______________ RC + Ri 1 RC + Ri + _____ j wCc

(10.15)

RC + Ri = AIm ______________ 1 RC + Ri + _____ j Cc (RC + Ri) = AIm ___________________________ 1 (RC + Ri) 1 + _____________ j Cc (RC + Ri)

[

]

AIm = ___________________ j 1 – ______________ 2 fCc (RC + Ri)

[

]

AIm AIl = ______ jfL 1 – ___ f where

(10.16)

1 fL = ______________ 2 Cc (RC + Ri)

(10.17)

| AIm | _________ |AIl| = __________ 1 + (fL/f)2 The phase angle of current gain at any frequency f is given by Il

( )

fL = phase angle of AIm + tan–1 __ f fL –1 __ = 180° + tan f

( ) (

1 = 180° + tan–1 ______________ 2 fCc (RC + Ri) At

)

| AIm | __ f = fL, |AIL| = _____ 2 = 0.707 |AIm|

Thus, fL forms the lower 3 dB frequency for the current gain. Vo AVl = ___ Vi R C Ri Vo = IoRi = –gm Ib rb e ______________ 1 RC + Ri + _____ j Cc Vi = Ib(rbb + rb e) = Ibhie Hence the voltage gain is given by – gm Ib rb e RC Ri Vo AVl = ___ = _____________________ Vi 1 (Ib hie) RC + Ri + _____ j Cc

[

]

Substituting,

hfe = gm rb e – hfe RC R i = ____ ___________________________ hie 1 (RC + Ri) 1 + _____________ j Cc (RC + Ri)

[

]

– hfe Rci = ____ ___________________ j hie 1 – ______________ 2 f Cc (RC + Ri)

[

where Rci = Rc || Ri. Therefore,

where Also,

]

AVm AVl = _________________ j 1 – ______________ 2 fCc (RC + Ri) AVm = _______ fL 1 – j __ f 1 fL = _____________ 2 Cc (RC + Ri)

(10.18)

(10.19)

| AVm | _________ |AVl | = __________ 1 + (fL/f )2

Phase angle of the voltage gain AVl is given by

At

( )

fL = phase angle of AVm + tan–1 __ f 1 –1 ______________ = 180° + tan 2 fCc (RC + Ri) f = fL

Vl

| AVm | __ = 0.707|AVm| |AVL| = _____ 2 Thus, fL forms the lower 3 dB frequency for the voltage gain. Since in both derivations for current gain and voltage gain 1 fL = ______________ 2 Cc (RC + Ri) the lower 3 dB frequencies are the same. In this frequency range, coupling capacitance Cc can be omitted since its reactance is small, whereas the shunt capacitance C cannot be neglected to the equivalent circuit of Fig. 10.19. RC Io = –gm Vb e _______ RC + Ri

B ¢1

B1 I b +

C1

B2

rbb¢

Io gmVb¢e rb¢e

Vi

Rs

C

RC

Ri

Vo

Is –

E1

But

E2

Ib Vb¢e = _________ 1 ___ + jwC r b¢e

Ibrb¢e = __________ 1 + j C rb¢e Therefore,

(

)

RC Ibrb¢e Io = – gm __________ _______ 1 + j C rb¢e RC + Ri

Hence, current gain in high frequency range, Io RC 1 AIh = __ = – gm rb¢e _______ ◊ __________ Ib RC + Ri 1 + j wCrb¢e AIm AIh = ___________ 1 + j w C rb¢e Let Therefore,

1 fH = ________ 2 p C rb¢e AIm AIh = _________ 1 + j (f/fH) | AIm | _________ | AIh| = __________ ÷1 +(f/fH)2

At

f = fH | AIm | __ = 0.707|AIm| |AIh| = _____ ÷2

Hence, fH forms the upper 3 dB frequency. Phase angle of current gain at any frequency f is given by fIh = phase angle of AIm – tan–1 ( f/fH) = 180° – tan–1 (2p fCrb¢e). Vo = –gmVb¢e (RCi)

(10.20) (10.21)

where

Rci = Rc || Ri Ib Vo = – gm Rci _________ 1 ___ r +j C be

Substituting

rb e Ib = – gm Rci ___________ 1 + j C rb e gmrb e = hfe, Rci Ib Vo = – hfe __________ 1 + j C rb e Vi = Ib (rbb + rb e) = Ibhie Vo –hfe Rci AVh = ___ = ____ __________ Vi hie 1 + j C rb e

Substituting

–hfe Rci AVm = _______, hie AVm AVh = _____________ 1 + j 2 f Crb e

(10.22)

(10.23)

AVm = _________ 1 + j (f/fH) where

1 fH = _______ 2 Crb e

Also

| AVm | _________ | AVh| = __________ 1 + (f/fH)2

At f = fH ,

| AVm | __ | AVh| = _____ 2

(10.24)

= 0.707 |AVm| Thus fH forms the upper 3 dB frequency. Phase angle of voltage gain at any frequency ‘f ’, Vh

= phase angle of AVm – tan–1 ( f/fH) = 180° – tan–1 (2 fCrb e)

1 Since fH = _______ in both cases, upper 3 dB frequencies of AIh and AVh are the same. 2 C rb e A plot of |AV /AVm| in dB against frequency f on log scale is shown in Fig. 10.20. From the Fig. 10.20, the 3 dB bandwidth extends from fL to fH . Thus, 3 dB bandwidth equal to fH – fL fH . But the true midband in which the gain remains truly constant extends from 10 fL to 0.1 fH . A plot of |AI /AIm| in dB against frequency will result in a similar curve.

20 log10 A AVm 0 – 10 – 20 – 30 – 40 0.01 0.1 f/fL

1

10 0.1

1 f/fH

10 100

Gain bandwidth product for the current gain is given by RC 1 | AIm fH | = hfe _______ ◊ ________ RC + Ri 2p C rb¢e gm rb¢e RC = ________ ◊ _______ 2p C rb¢e RC + Ri gm RC = _____ ◊ _______ 2p C RC + Ri

(10.25)

Similarly, the gain bandwidth product for the voltage gain is given by hfe 1 | AVm fH | = ___ ◊ Rci ________ 2p C rb¢e hie gm Rci = _____ ___ 2p C hie

(10.26)

A CE, RC coupled amplifier uses transistors with the following h-parameters: hfe = 50, hie = 1200 , hoe = 30 × 10–6 mhos, hre = 2.5 × 10–4. The value of gm at the operating point is 50 mmhos. The biasing resistor R1 between VCC and base is 100 k and R2 between base and ground is 10 k . The load resistor RC = 5 k . Let C = 160 pF be the total shunt capacitance in the input circuit and the coupling capacitor CC = 6 F. Calculate for one stage of the amplifier (a) mid-band current gain (b) mid-band voltage gain (c) lower and higher 3 dB frequencies and (d) gain-bandwidth product.

Solution

106 1 Ro = ___ = ___ = 33.33 kW hoe 30 RB = R1 || R2 = 100 × 103 || 10 × 103 = 9.1 kW Ri = hie = 1.2 kW R¢C = RC || Ro = 5 × 103 || 33.33 × 103 = 4.35 kW Ri¢ = RB || Ri = 9.1 × 103 || 1.2 × 103 = 1.1 kW

R¢ci = R¢c || R¢i

rb¢e

(a) Mid-band current gain,

= 4.35 × 103 || 1.1 × 103 = 0.87 kW hfe = ___ gm 50 = ________ = 1000 W 50 × 10–3

–hfe R¢C AIm = ________ R¢C + R¢i –50 × 4.35 × 103 = ___________________ 4.35 × 103 + 1.1 × 103 = –39.9 (b) Mid-band voltage gain, R¢ci AVm = –hfe ___ hie 0.87 × 103 = 50 × _________ = –36.25 1.2 × 103 (c) Lower 3 dB frequency, 1 fL = ______________ 2p CC (R¢C + R¢i) 1 = ________________________________ = 4.87 Hz 2p × 6 × 10–6 (4.35 × 103 + 1.1 × 103) Higher 3 dB frequency, 1 fH = ________ 2p C rb¢e 1 = _______________________ = 995.2 kHz 2p × 160 × 10–12 × 1 × 103 (d) Voltage gain × bandwidth | AVm fH | = |–36.25 × 995.2 × 103| = 36.07 MHz

Figure 10.21 shows the circuit diagram of a multistage transformer coupled amplifier. A current source IS with shunt resistance Rs drives the amplifier through the input transformer TR1. The load resistor RL is connected to the output circuit of the second amplifier stage through transformer TR3. The transformer coupled amplifier may be used in the following three ways: (i) as input stage usually driven by a microphone, (ii) as output stage feeding the load impedance, and (iii) as intermediate stage. The coupling of one stage to another may be made more effective by the use of transformers to match the output impedance of one stage to the input impedance of the next. This impedance matching

results in increased power gain. Further, this method of coupling isolates the load impedance circuit of the amplifier from d.c. bias stabilisation network of the next stage. However, for good results it becomes necessary to shield the transformer against noise, hum and unwanted signal pickups. In the circuit, capacitors C1 and C2 permit complete input power to flow into the base circuit. Given the load resistor RL, the circuit can be analysed starting at the right obtaining RL2 by taking into account the turns ratio of the output transformer TR3. This will be the load for transistor Q2 and should be ideally equal to the output resistance of Q2 for a maximum power transfer. Next, the input resistance of Q2 equal to Ri2 ( hie2) would permit the determination of the load across the interstage transformer TR2, if the turns ratio of TR2 were known. This would be the effective load RL1 for Q1. Finally, the input resistance Ri1 to Q1 ( hie1) would allow the selection of driver transformer TR1, based on the knowledge of source resistance RS. In general, transformers are not selected for their turns ratio, but for the impedances they are to match and their power handling capacity. However, these impedances would permit the determination of turns ratio for calculating current gain and voltage gain. The analysis of a transformer coupled amplifier may be done as in the case of RC coupled amplifier. Thus the entire frequency range may be divided into three frequency regions.

The selection of transformer TR2 for the stage enclosed in Fig. 10.21 and Ib2 the current gain of the stage Ai = ___ are done. Assuming that all capacitor reactances are negligible, the Ib1 approximate equivalent circuit shown in Fig. 10.22 may be used. Q1 +

IC1

C1

B1

Ib2

Q2

B2

Ib1 Vb1

hie1

hoe1 VC1 N1

N2

hie2

Vb2

hfe1Ib1 TR2

–

E1

E1

E2

N1 A transformer of turns ratio ___ reflects a load impedance hie2 on the secondary, into the primary equal N2 N1 2 ___ to a value of hie2, the equivalent circuit becomes as shown in Fig. 10.23. N2

( )

Q1 IC1

B1 +

+

Vt1

hie1

hfe1Ib1

hoe1

C1

N1 2 N2 hie

VC1

–

–

E1

N1 2 1 Thus Q1 has an effective load equal to ___ hie2 and since its output impedance is equal to ____, these N2 hoe1 two impedances should be equal for maximum power transfer, i.e. N1 2 1 ___ hie2 = ____ N2 hoe1

( )

( )

N1 ________ 1 ___ = _______ N2 hie2 hoe1

(10.27)

Typical values of h-parameters for a BJT are hie1 = hie2 = 1.2 k , hfe1 = 60, hoe1 = 25 × 10–6 mho. N1 ________________ 1 ___ = _______________ = 5.8 Hence N2 1000 × 25 × 10–6 N1 = 5.8 N2 Thus, TR2 is a step down transformer having a primary to secondary turns ratio of 5.8 to 1. 1 Since ____ = 40 k , the transformer would be specified as matching a 40 k primary to a 1 k secondary. hoe1 Actually the output impedance of Q1 is closer to 50 k , if the source resistance Rs is also taken into account. To determine the current gain, assume Ib1 flowing into B1 as hfe1 Ib1 shown. The current through the transformer primary will be ______ for matched conditions. Since TR2 2 is a voltage step-down transformer the current on the secondary will be stepped up by the ratio N1/N2. N1 hfe1 Ib1 N1 Thus, Ib2 = ___ Ic1 = ______ ___ and the expression for mid-frequency current gain is N2 N2 2 Ib2 N1 hfe1 AI = ___ = ___ ___ (10.28) Ib1 N2 2 50 = 5.8 × ___ = 145 2 The current gain is several times as large as the gain evaluated for RC coupled amplifier. This is because there is no current division between load resistance, biasing resistors and base input. All the collector current magnified by the transformer turns ratio is the base input current to the next stage. This expression for current gain may also be used for the second stage, if TR3 matches load resistance Ib1 N1 RL to output resistance of Q2. Similarly, the current gain ___ will be given by ___ for TR1. Ii N2 From Fig. 10.23, Vb2 AV = ____ Vb1

( )

N1 Vc1 = –Ic1 ___ N2 Substituting

2

(10.29)

hie2

hfe1 Ib1 Vb1 Ic1 = ______ and Ib1 = ____, 2 hie1 hfe1 Vb1 Ic1 = _______ 2hie1

Substituting Eqn. (10.30) in Eqn. (10.29), –hfe1 Vb1 N1 Vc1 = ________ ___ N2 2hie1

( )

2

hie2

(10.30)

–hfe1 hie2 N1 Vc1 ____ ____ × ___ ___ = Vb1 2 hie1 N2

2

( )

Vc1 N1 ____ = – ___ Vb2 N2

( )

As

hfe1 hie2 N1 Vc1 Vc1 ___ ____ × ___ ___ ____ = Vb1 2 hie1 N2 Vb2

( )

Vb2 hfe1 hie2 N1 AV = ____ = ___ × ___ ___ Vb1 2 hie1 N2

( )

(10.31)

If identical transistors are used with hie2 = hie1, N1 hfe1 (10.32) AV = ___ ___ N2 2 which is the same expression as for the current gain. Thus AV = 145. Note that a large voltage gain results inspite of the presence of a step down transformer. This is because the transistor is working into a much higher effective load resistance than in RC coupled amplifier resulting in large voltage gain between base and collector. For the matched conditions, stage power gain Ap = AV × Ai = 1452 = 21025. Hence Ap in dB = 10 log10 21025 43 dB. Thus, fewer stages would be necessary to provide a required power gain if transformer coupling were used instead of RC coupling. However, this must be balanced by the cost of transformers (often more expensive than transistors) and the effect of transformers on the frequency response. A more accurate equivalent circuit of a transformer coupled amplifier at low frequencies includes the primary inductance LP so that the load reflected from the secondary into the primary is shunted by LP as shown in Fig. 10.24. Q1

B1

C1

+

+

Ib1 hfe1Ib1 V b1

hie1 hoe1

VC1

LP

N1 2 N2 hie2

–

–

E1

At lower frequencies, the shunting effect of LP will reduce the effective load for transistor Q1 with a reduction in VC1 and voltage gain.

( )

N1 1 If R represents the parallel combination of ____ and ___ N2 hoe1 when the reactance of LP = R, i.e.

where

2

hie2, the lower 3 dB frequency fL will occur

2 fLLP = R R fL = _____ 2 LP

(10.33) 2

( )

N1 1 R = ____ || ___ hoe1 N2

(10.34)

hie2

For the example under consideration, R = 40 k || 40 k = 20 k . To obtain lower 3 dB frequency fL = 150 Hz, a transformer whose primary inductance given by 20,000 R LP = _____ = ________ = 21.2 H is required. 2 fL 2 × 150 Values of inductance available in a transformer range from 0.6 mH to 150 F, with the larger inductance obviously involving a bulkier transformer and more cost. If R is reduced, the necessary value of LP is also reduced (or fL is reduced for a given value of LP), but this will destroy the maximum power transfer condition resulting in decrease in AP. The shunting effect of the transformer’s primary inductance LP at mid-to-high frequencies is negligible but the series leakage inductances and distributed capacitances in both primary and secondary now become significant. These are included in the high frequency equivalent circuit for a transformer coupled amplifier shown in Fig. 10.25.

Since the high frequency capability of the amplifier will normally be limited by the transformer’s characteristics and not by that of the transistor, the transistor can be represented by its approximate low frequency model. Thus, Vs and Rs represent either the input source or the equivalent output from the previous transistor. RL may be the output load or the input to the next stage. When the resistance, inductance and capacitance on the secondary side are reflected into the primary. Then, N1 2 N2 2 L1 = L1P + L1S ___ and C = CP + ___ CS N2 N1

( )

The simplified equivalent circuit shown in Fig. 10.26 is obtained.

( )

The circuit will have a series resonant effect at high frequencies. But because of the usually large value of Rs, the overall Q of the circuit will be low in the region of 0.5 to 2. Thus the resonant effect is not pronounced but the resonant frequency fo where XC = XL1 will give an indication of the upper 3 dB frequency fH. That is why fH is usually some what higher than fO which is given by 1____ fo = ________ 2p ÷L1C The variation of the amplifier’s voltage gain with frequency is shown in Fig. 10.27 for different values of Q. For example, if L1 = 0.2 H and C = 500 pF, fo ª 16 kHz and f2 will be in this neighbourhood, with its precise value depending upon the Q of the circuit.

In the field of instrumentation and power supplies, there are many signals that change very slowly with time. To process these signals, circuits must be employed whose frequency response is stretched flat down to d.c. This prevents the use of the interstage coupling elements, such as capacitors and transformers, as these components attenuate very low frequencies and completely block d.c. signals. There are two basic techniques for amplifying such low frequency signals that change very slowly with time. One is to use direct coupled (d.c.) amplifiers and the second one requires chopping the d.c. signals so as to change it to an a.c. signal which is then amplified using conventional a.c. amplifiers and reconstructed at the output as d.c. In the design of d.c. amplifiers, one should ensure that d.c. levels of each stage are compatible with those of other circuits to which the stage is connected. As an example, consider the identical amplifier stages of Fig. 10.28. Assume that VCC1 = VCC2 = 12 V; VB1 = VB2 = 2 V; VE1 = VE2 = 1.5 V and VC1 = VC2 = 5 V. Each stage is therefore biased at VBE = 0.5 V and VCB = 3 V. Also there is a potential difference of 3 V between the collector of Q1 and the base of Q2.

VCC1 = 12 V VCC2 = 12 V RC1

RB1

VC1 = 5 V RC2

RB2

Q1 VB1 = 2 V

VC2 = 5 V VE1 = 1.5 V

VB1 = 2 V

Q2

RE1

VE2 = 1.5 V RE2

For a.c. operation, a capacitor is connected between the collector of Q1 and the base of Q2 as shown in Fig. 10.29. By this method, the a.c. signal is coupled from Q1 to Q2, but the capacitor charges to 3 V d.c. so that VC1 is still at 5 V and VB2 is still at 2 V. The d.c. levels of both the stages remain independent of the other. VCC = 15 V

RC2 RB1

RC1 5V

3V +

2V

–

RB2 2V

5V

Q2

Q1 1.5 V 1.5 V

RE2 RE1

For d.c. operation, the capacitor is to be omitted but the collector of Q1 cannot be directly connected to the base of Q2 unless the voltages at these points are the same. One possible solution is to leave the first stage as it is but lift the second stage by 3 V relative to ground so that VB2, VE2 and VC2 are all 3 V higher than they were earlier. This may be accomplished by connecting a 3 V battery in series with RE2 and using a 18 V supply for VCC2 as shown in Fig. 10.30.

VCC = 18 V VCC = 15 V

RC2

RB2 8V

RC1

RB1

Q2

5V 5V 2V

Q1

4.5 V

1.5 V

RE1

RE2 3V

In the circuit of Fig. 10.30, VB2 = 5 V and VC2 = 8 V. This causes VC1 to be equal to VB2 enabling connection of the two points directly to each other. Increasing the base, emitter and collector voltages by the same amount does not alter any of the potential differences, i.e. VBE2 = 0.5 V and VCB2 = 3 V and therefore the operating point is unchanged. The above arrangement has a number of obvious disadvantages. As VCC1 and VCC2 are not the same and because of the 3 V battery in series with RE2, a total of three different supplies are required. The 3 V battery can be replaced by a 3 V zener diode or it could be simply eliminated and RE2 made correspondingly larger. This would increase the input resistance to Q2 and lower the gain because of the increased negative feedback. Further, as VCC2 must be larger than VCC1, if a third stage is added VCC3 must be larger than VCC2. Hence for a multistage amplifier the required d.c. voltage supplies might be impractically large. A circuit arrangement that solves the above problem is shown in Fig. 10.31. Here, alternate polarity transistors are cascaded and the d.c. voltages are so adjusted that each of the three transistors is operating at exactly the same point. In this circuit, there is a 0.5 V forward bias across each base-emitter junction and 5 V reverse bias across each collector-base junction. Further, it is to be noted that only one external supply is needed. An additional problem peculiar to d.c. amplifiers is that small changes in the operating point due to temperature or power supply fluctuations as well as aging of circuit components are also amplified as there is nothing to block d.c. and these changes appear in the amplified form across the output. The d.c. input voltage required to bring the output voltage back to its original level (no signal level) is a measure of performance of d.c. amplifiers and is called voltage offset VOS. Similarly, a d.c. input current known as offset current, IOS, might be required to bring the output current back to its original level. Both the offset voltage and current tend to vary with time and temperature. d.c. amplifiers generally require a potentiometer adjustment for cancelling such offsets. The manufacturer also usually specify the values of EOS and IOS and the expected drift with time and temperature. Stabilising techniques can also be applied here.

+ 12 V

RE2

RC1

RB1

n Q1

P

3V

R C3

8.5 V P

8V

8V

Q2

n

n

P n RE1

3V

2.5 V

3V

Q3

P n

RC2

2.5 V

RE3

A very popular connection of two bipolar junction transistors for operation as one “superbeta” transistor is the Darlington connection, which is shown in Fig. 10.32. The main feature of the Darlington connection is that the composite transistor acts as a single unit with a current gain that is the product of the current gains of the individual transistors. If the connection is made using two separate transistors having current gains of b1 and b2, the Darlington connection provides a current gain of bD = b1b2 C

B

C

Q1 Q2

E

B

QD

E

If the two transistors are matched such that b1 = b2 = b, the Darlington connection provides a current gain of bD = b2 When two transistors having high current gain are connected as a Darlington pair, the overall gain of the pair becomes very high.

For instance let the current gain b be 400. Then, the overall gain of the pair is 400 × 400 = 1,60,000. Darlington pairs are generally available in IC packages. The package has only three terminals namely, base, emitter and collector. In other words, it can be considered as a single Darlington transistor having very high current gain as compared to other typical single transistor. Darlington transistor is commonly used in emitter follower circuit. This gives an equivalent circuit of two emitter followers in cascade, thereby increasing the input impedance.

In Fig. 10.33, a Darlington transistor having very high current gain bD is used. The base current is given by VCC – VBE IB = __________ RB + bDRE and the emitter current is given by IE = (bD + 1) IB ª bDIB + VCC

C

IC

RB

IB

B

E

IE RE

The dc voltages are given by VE = IERE VB = VE + VBE

For some applications, it is necessary to have an amplifier with high input impedance. Emitter follower may be used to have input resistances of about 500 kW. For achieving still higher input impedances, the Darlington connection shown in Fig. 10.33 is used. Darlington connection has two transistors forming a composite pair. The input resistance of the second transistor constitutes the emitter load for the first. The Darlington circuit consists of two cascaded emitter followers with infinite emitter resistance in the first stage, as shown in Fig. 10.34. The Darlington composite emitter follower will be analyzed by referring to Fig. 10.35. Assume that hoRe £ 0.1 and hfeRe >> hie.

+

B Q1 Q2

Vi Re1 Æ • – C

E + Vo –

Re

C

Io AI2 = __ ª 1 + hfe Ri2 ª (1 + hfe) Re I2 Since the effective load for transistor Q1 is Ri2¢ which does not meet the requirement hoeRi2 £ 0.1, the current gain of the first transistor becomes 1 + hfe 1 + hfe Io AI1 = __ = _________ = ________________ I2 1 + hoe Ri2 1 + hoe (1 + hfe) Re As hoeRe £ 0.1, we get 1 + hfe AI1 ª ________ hoe hfe Re The overall current gain is Io I o I 2 AI = __ = __ __ = AI2AI1 Ii I2 Ii Therefore,

(1 + hfe)2 ___________ AI = 1 + hoe hfe Re

Similarly, the input resistance of Q1, is

(1 + hfe)2 Re RiI = hie + AI1Ri2 ª ___________ 1 + hoe hfe Re This equation for the input resistance of the Darlington circuit is valid for hoe Re £ 0.1. The voltage gain of the Darlington circuit is close to unity, but its deviation from unity is slightly greater than that of the emitter follower. Then hie hie 1 – AV2 = 1 – ___ ª ______ Ri1 AI1 Ri2 where We know that,

AV2 = Vo/V2 and AV1 = V2/Vi. AV = Vo/Vi

[

][

]

hie hie hie hie AV = AV1 AV2 = 1 – ___ 1 – ______ ª 1 – ______ – ___ Ri2 AI1 Ri2 AI1 Ri2 Ri2 Since AI1Ri2 >> Ri2, the above equation becomes hie AV ª 1 – ___ Ri2 This result indicates that the voltage gain of the Darlington circuit used as an emitter follower is essentially the same as the voltage gain of the emitter follower consisting of transistor Q2 alone, but very slightly smaller. The output resistance Ro1 of Q1 is Rs + hie Ro1 = _______ 1 + hfe Therefore, the output resistance of the Q2 is

Ro2

Rs + hie _______ + hie 1 + hfe Rs + hie hie ___________ = = ________2 + ______ 1 + hfe 1 + hfe (1 + hfe)

We can now conclude from the foregoing discussion that the Darlington emitter follower has higher current gain, a higher input resistance, a voltage gain less close to unity, and a lower output resistance than a single-stage emitter follower. In the Darlington pair, it is assumed that both the transistors Q1 and Q2 are identical i.e. same value of h-parameters. In reality, this is usually not the case, because the h parameters depend on the quiescent conditions of Q1 and Q2. Since the emitter current of Q1 is the base current of Q2, the quiescent current of the first stage is much smaller than that of the second stage. Hence hfe may be much smaller for Q1 than for Q2 and hie may be much larger for Q1 than for Q2. In order to have reasonable operating current in the first transistor Q1, the second transistor Q2 may have to be a power stage. Another major drawback of the Darlington transistor pair is that the leakage current of the transistor Q1 is amplified by the transistor Q2, and hence the overall leakage current may be high. For these two reasons, a Darlington connection of three or more transistors is usually impractical.

The composite transistor pair can be used as a common-emitter amplifier. The advantage of this pair is very high overall current gain, which is normally equal to the product of CE short-circuit current gains of the two transistors. In fact, Darlington integrated transistor pairs are commercially available with hfe as high as 30,000. If hoeRe hie2, then hoe1 may be neglected from this circuit and solving for Vi /Ib1 results in the input resistance of bootstrapped Darlington pair as VCC 1 hob

Rc1 C1

+

B1

C2

Q1 E1

CO

B1

Q2

Vi

E2

+

Re2 N

Ri –

Vo = AV Vi –

(a)

hfe1 Ib1 C1 Ib1

hie1

B1

hoe1 Ib2

E1, B2

hie2

I

E2

Re = Rc1 || Rc2

Vi Ri

hre1 Vce1 + –

hfe2 Ib2 C2

N (b)

Ri = hfe1hfe2Re The above expression shows that the input resistance of the bootstrapped Darlington emitter follower is essentially equal to the product of the short-circuit current gains and the effective emitter resistance. If hfe1 = hfe2 = 50 and Re = 4 KW, then Ri = 10 MW. If transistors with current gains of the order of magnitude of 100 instead of 50 were used, an input resistance of 40 MW would be obtained. If the biasing arrangement is considered for the bootstrapped pair shown in Fig. 10.37(a) then the input resistance, taking into account the bootstrapping both at the base and at the collector of Q1, would be R3 Reff || hfe1hfe2Re, where Reff is given by Reff = ______. 1 – AV

Cascode amplifier is a composite amplifier pair with a large bandwidth used for RF applications and as a video amplifier. It consists of a CE stage followed by a CB stage directly coupled to each other and combines some of the features of both the amplifiers. For high frequency applications, CB configuration has the most desirable characteristics. However, it suffers from low input impedance (Zi ª hib). The cascode configuration is designed to have the input impedance essentially that of CE amplifier, the current gain that of CE amplifier, the voltage gains that of CB amplifier and good isolation between the input and output. Figure 10.38 shows a cascode amplifier.

The a.c. equivalent circuit for cascode amplifier is drawn by shorting the d.c. supply and coupling capacitors as shown in Fig.10.39. The simplified h-parameter equivalent circuit for cascode amplifier is further drawn by replacing the transistors with their simplified equivalent circuits as shown in Fig.10.40.

From the approximate analysis of a single stage CB amplifier, we know that hfe Ic2 Ai2 = ___ = ______ Ie2 1 + hfe hie Ri2 = ______ 1 + hfe Vo Ai2 RL AV2 = ___ = ______ Ve2 Ri2 From the approximate analysis of a single stage CE amplifier, we know that Ic1 Ai1 = ___ = –hfe Ib1 Ri1 = hie Vc1 Ai1 RL1 AV1 = ____ = _______ Vb1 Ri1 where

RL1 = Ri2

The overall voltage gain is the product of individual gains and it is written as Ai1RL1 Ai2RL AV = AV1 × AV2 = ______ × ______ Ri1 Ri2 From the simplified circuit, the overall input resistance is given by Ri = Ri1 || RB = Ri1 || R3 || R4 The overall voltage gain by considering the source is given by Vo Vo Vi Ri AVs = ___ = ___ × ___ = AV × _______ Vs Vi Vs R1 + Rs The overall current gain, by considering the source, is written as Io Io Ic2 Ie2 Ic1 Ib1 Ais = __ = ___ × ___ × ___ × ___ × ___ Is Ic2 Ie2 Ic1 Ib1 IS Io Ic2 Ie2 Ic1 Ib1 RB ___ = –1, ___ = –Ai2, ___ = –1, ___ = –Ai1, ___ = ________ Ic2 Ie2 Ic1 Ib1 IS RB + Ri1

where

The output resistance of individual stages is very high i.e. R01 = R02 = • and the overall output resistance is almost equal to the load resistance i.e. R0 = R02 || RL ª RL.

The cascode amplifier shown in Fig. 10.38 makes use of identical transistors Q1 and Q2 with the following h-parameters: hfe = 50, hie=1.1 k , hoe=10 ×10–6 mhos, hre = 2.5 ×10–4. The circuit parameters are Rs = 1 k , R3 = 200 k , R4 =10 k and RL = 3 k . Calculate the overall current gain, voltage gain, input and output resistances.

Solution

To find Overall Input Resistance

Input resistance of the first stage (CE amplifier), Ri1 = hie = 1.1 kW hie 1.1 × 103 Input resistance of the second stage (CB amplifier), Ri2 = ______ = ________ = 21.56 W 1 + 50 1 + hfe Overall input resistance is Ri = Ri1 || RB = Ri1 || R3 || R4 = 1.1 × 103 || 200 × 103 || 10 × 103 = 986.1 W To find Overall Current Gain Current gain of first stage,

Ai1 = – hfe = – 50

hfe 50 Current gain of second stage, Ai2 = ______ = ______ = 0.98 1 + hfe 1 + 50 Overall current gain is

Io Io Ic2 Ie2 Ic1 Ib1 Ais = __ = ___ × ___ × ___ × ___ × ___ IS Ic2 Ic2 Ic1 Ib1 IS

where

Io Ic2 Ie2 Ic1 Ib2 RB ___ = –1, ___ = –Ai2, ___ = –1, ___ = –Ai1, ___ = ________ Ic2 Ic2 Ic1 Ib1 IS RB + Ri1

and Therefore,

RB = R3 || R4 = 200 × 103 || 10 × 103 = 9.5 kW RB Ais = –1 × –Ai2 × – 1 –Ai1 × ________ = – 43.9 RB + Ri1

To find Overall Voltage Gain Ai1RL1 Voltage gain of the first stage, AV1 = ______ Ri1 where

RL1 = Ri2 = 21.56 W

Therefore,

– 50 × 21.56 AV1 = ___________ = – 0.98 1.1 × 103

Ai2RL2 0.98 × 3 × 103 Voltage gain of the second stage, AV2 = ______ = _____________ = 136.36 Ri2 21.56 Overall voltage gain is AV = AV1 × AV2 = –0.98 × 136.36 = –133.63 Vo Vo Vi Ri AVs = ___ = ___ × ___ = AV × _______ = –66.35 Vs Vi Vs Ri + Rs To find Overall Output Resistance Output resistance of the first stage, Ro1 = • Output resistance of the second stage, Ro2 = • Overall output resistance, Ro = Ro2 || RL = • || 3 × 103 = 3 kW

The gain factors such as voltage, current, transconductance and transresistance of amplifiers are functions of signal frequency. In the amplifier gain versus frequency plot, the gain factor is plotted in terms of decibels and frequency in terms of Hertz on logarithmic scales. The main purpose is to determine the frequency response of amplifier circuits due to circuit capacitors and transistor capacitances. The frequency response will be useful to determine bandwidth of the circuit. The transfer function is derived by using the complex frequencys, of several passive circuits. With the help of Bode plots of the transfer function, the magnitude response, phase response, time constant and 3 dB cutoff frequencies are calculated. In this chapter, the frequency responses of transistor circuits including BJTs and FETs are studied. The effects due to circuit capacitors including coupling, bypass, and load capacitors and internal transistor capacitances are analysed. The RF amplifier and video amplifier circuits used in high frequency applications are discussed.

The analysis of amplifiers normally extends over a wide frequency range. Use of logarithmic scale makes it comfortable plotting the response between wide limits. Logarithm taken to the base 10 is common logarithm. For example, logarithm of a variable “a” is log10 a. Logarithm taken to the base “e” is natural logarithm. For example, logarithm of a variable “a” is loge a. Common logarithm

:

u = log10 a

Natural logarithm

:

v = loge a

Natural logarithm can be written as ln a(= loge a). Numerically e = 2.71828 and loge a = 2.3 log10 a. In amplifier analysis, a frequency of 10,000 Hz becomes log10 104 = 4 log10 10 = 4 in logarithmic scale. Thus the frequency plot is compressed without major class of information and the problem of dealing with huge numbers is overcome.

In a semilog graph shown in Fig. 11.1 (a), only one of the two scales is a log-scale. In a double log graph shown in Fig. 11.1 (b), both the scales are log scales. Figure 11.2 indicates how a linear scale is converted into a log scale. Thus logarithmic scale helps to explain variations of parameters over a wide range by a simple graph. N

log10 10,000 = 4

log10 100,000 = 5

Linear scale

log10 1000 = 3

(b)

N

log10 100 = 2

Log scale

(a)

N 100

log10 10 = 1

Log scale

N 10

log10 1 = 0

Log scale

Linear scale

N 1

1000 10,000 100,000

0

1

2

3

4

5

Log scale

1. If a = b u, then u = logb a For example, if log10 1 = y, then 1 = 10y. Hence y = 0. u 2. log10 __ v = log10 u – log10 v 3. log10 uv = log10 u + log10 v Table 11.1 clearly shows how the logarithm of number increases only as the exponent of the number.

log10 100 = 0 × log10 10 = 0 log10 101 = 1 × log10 10 = 1 log10 102 = 2 × log10 10 = 2 log10 103 = 3 × log10 10 = 3

and so on.

Decibel is used to compare two power levels on a logarithmic basis. The term “bel” is derived from the name of telephone invention, Alexander Graham Bell. The unit “bel” (B) is defined relating two power levels P1 and P2 as P2 G = log10 ___ bel P1

( )

As “bel” was found to be a large unit for measurement, the “decibel” (dB) is defined where 10 decibels = 1 bel.

Hence,

( )

P2 GdB = 10 log10 ___ dB P1 The above equations indicate that dB is a measure of difference in magnitude between two power levels, say output power level and input power level (or some reference level). Quite often the input power level (or reference power level) is taken as 1 milliwatt in electronics. Then “decibel” symbol can be written as dBm, where P2 GdBm = 10 log10 ______ dBm 1 mW V21 V22 In terms of voltage P1 = ___ and P2 = ___ where Ri is input resistance of the system, where output Ri Ro resistance Ro is assumed to be equal to input resistance. V22/Ri P2 ___ _____ Hence, GdB = 10 log10 = 10 log10 2 P1 V /R 1

= 10 log10

i

2

( ) ( ) V2 ___ V1

V2 GdB = 20 log10 ___ dB V1 The advantage of logarithmic relationship is that the overall gain of a cascaded system is simply the sum of individual gains. Overall gain for a “n” stage system is given by G = G1 × G2 × G3 × ... × Gn – 1 × Gn

V1

1

V2

Vn – 1 n – 1

V3

2

Vn

n

3

Vo/p

Vo/p Vo/p Vn V2 V3 V4 ____ = ___ × ___ × ___ × ... × ____ × ____ V1 V1 V2 V3 Vn – 1 Vn In logarithmic relationship

( )

Vo/p V3 V2 V4 GdB = 20 log10 ____ = 20 log10 ___ + 20 log10 ___ + 20 log10 ___ + º + V1 V1 V2 V3

( )

( )

( )

Vo/p Vn 20 log10 ____ + 20 log10 ____ Vn–1 Vn

( )

where

GdB = G1 + G2 + G3 + ... + Gn – 1 + Gn

and G1, G2, G3, … are voltage gains of stages 1, 2, 3, … respectively in decibels.

Calculate the magnitude gain corresponding to a voltage gain of 200 dB.

( )

Solution log10

V2 GdB = 20 log10 ___ = 200 dB V1 V2 ___ = 10 V1

( )

( )

V4

V2 Gain = ___ = 1010 V1 A three-stage amplifier has a first stage-voltage gain of 30, second stage voltage gain of 200 and third stage gain of 400. Find the total voltage gain in dB.

Solution

First-stage voltage gain in dB,

G1 Second-stage voltage gain in dB, G2 Third-stage voltage gain in dB, G3 Therefore, the total voltage gain G

= 20 log10 30 = 20 × 1.477 = 29.54 = 20 log10 200 = 20 × 2.3 = 46 = 20 log10 400 = 20 × 2.6 = 52 = G1 + G2 + G3 = 29.54 + 46 + 52 = 127.54 dB

(a) A multistage amplifier employs five stages each of which has a power gain of 30. What is the total gain of the amplifier in dB? (b) If a negative feedback of 20 dB is employed, find the resultant gain.

Solution

Given, the gain of each stage = 30 and number of stages = 5

(a) Power gain of one stage = 10 log10 30 = 10 × 1.477 = 14.77 dB Total power gain = 5 × 14.77 = 73.85 dB (b) The resultant power gain with negative feedback = 73.85 – 20 = 63.85 dB

In an amplifier, the output power is 1.5 W at 2 kHz and 0.3 W at 20 Hz, while the input power is constant at 10 mW. Determine by how many decibels is the gain at 20 Hz below that at 2 kHz?

Solution

To determine power gain at 2 kHz

At 2 kHz, the output power is 1.5 W and input power is 10 mW. 1.5 Therefore, power gain in dB = 10 log10 ________ = 10 log10 150 = 21.76 10 × 10 – 3 To determine power gain in dB at 20 Hz At 20 Hz, the output power is 0.3 W and input power is 10 mW. 0.3 Therefore, power gain in dB = 10 log10 ________ = 10 log10 30 = 14.77 10 × 10 – 3 Fall in gain from 2 kHz to 20 Hz = 21.76 – 14.77 = 6.99 dB

An amplifier has a voltage gain of 15 dB. If the input signal voltage is 0.8 V, determine the output voltage.

Solution

Voltage gain in

dB = 20 log10 V2/V1

Therefore,

15 = 20 log10 V2/V1 15/20 = log10 V2/V1 0.75 = log10 V2/0.8

Taking antilogarithm, we get 100.75 = V2/0.8 Hence,

V2 = 100.75 × 0.8 = 4.5 V

In amplifier analysis, half power gain is found out as follows: Poutput max /2 Half power gain in dB = 10 log10 ___________ Poutput max

20 log10

Vo / p Vi /p 3 dB

()

1 = 10 log10 __ 2 = 10 log10 (0.5) = – 3 dB Hence, the half power gain is maximum gain minus three decibels. As shown in Fig. 11.4, half power bandwidth i.e., (f2 ~ f1), is the frequency range over which gain is more than half power gain.

f1

f2

Frequency

The response of any single-stage (or) Multistage network is highly influenced by the frequency of the applied signal. At low frequencies, the effect of capacitors (coupling and bypass) cannot be neglected due to their high value of capacitive reactance under these conditions. Moreover, any fluctuations in the number of stages of a cascaded system will also affect the frequency response of that system. While plotting the frequency response of a circuit, it is conventional to use a logarithmic scale along the X-axis (horizontal axis), so as to permit a plot extending from low to the high frequency regions. In general, any frequency response curve can be splitted into three regions, namely. (a) Low frequency region (b) Mid frequency region and (c) High frequency region

In general, the frequency response curve is a plot between magnitudes of gain and logarithmic frequencies. A typical frequency response curve of an RC-coupled amplifier is shown in Fig. 11.5. AV mid = Vout Vin

Bandwidth

AV mid 1 A 2 V mid Mid frequency region Low frequency region 10

f1 100

1000

10,000

100k

High frequency region

f2 1M 10M

Freq. (log scale)

The main reason for the drop in gain at the low frequency region and the high frequency is due to the increase in capacitive reactance in the low frequency region and due to the parasitic capacitive elements (or) the frequency dependence of the network’s gain on the active devices, in the high frequency region. 1__ AV mid” to be The frequency boundaries of relatively high gain region is determined by choosing “___ 2 the gain at the cut off levels. The frequencies corresponding to such values ( f1 and f2) are called cut-off frequencies (or) band frequencies (or) corner frequencies (or) half power frequencies. At cut-off frequencies, the output power is half the mid band power output.

but Therefore,

|V2out| Pout ( mid) = _____ Ro V out | Av | mid = ____ Vin

(11.1)

| |

(11.2)

| AV mid Vin |2 Pout = ___________ Ro

(11.3)

at half power frequencies, f1 and f2 (Ref Fig. 11.1) Pout HPF

| 0.707 AV mid Vin |2 | AV mid Vin |2 ________________ ___________ = = 0.5 Ro Ro

(11.4)

Comparing Eqs (11.1) and (11.4) Pout HPF = 0.5 Pout (mid)

(11.5)

The bandwidth of each system is hence given by Bandwidth = f2 – f1

(11.6)

However, in most applications it is preferrable to have the plot of gains in (dB) and it is also conventional to use a normalized plot for such analysis. A normalized plot is a plot of gain Vs log frequencies, with the gain values divided by the gain in the mid frequency ranges (i.e., the maximum gain)

AV AV mid

Normalized gain 1 0.707 × 1

f1 10

f2 100

1000

10,000

100k

f (log scale) 1M 10M

A decibel plot can now be obtained by using the following transformation AV AV ______ = 20 log10 ______ AV mid dB AV mid

|

(11.7)

Hence, the gain at half power point becomes 1__ 20 log10 ___ = – 3 dB. ÷2 The plot is as shown in Fig. 11.7.

( )

AV AV mid

0 dB

10

f1

100

1000

10k

100k

f21M 10M

f (log)

dB

–3 –6 –9 – 12

RC coupled

The cut-off frequencies of single stage BJT/FET amplifiers are influenced by the RC combinations formed by the network capacitors CC, CE, etc. and the resistive + + parameters that are present in the network. C

For the purpose of analysis, each capacitive element can be modelled as one shown in Fig. 11.8 and its frequency response can be studied. Once the cut-off frequencies due to individual capacitors are studied, they can be compared to establish, which will determine the cut-off frequency (lower cut-off) for the system.

Vin –

R

Vout –

In this section, a methodology for determining the lower cut-off frequency ( f1) will be presented. However, a straight forward mechanism can be employed to find the Upper cut-off frequency ( f2), with some extension in the frequency response region f1 and f2 are also referred to as a and b cut-off frequencies. It is to be recalled that 1 XC = ____ ª 0 W 2pfc

at High frequencies

1 XC = ____ ª • W 2pfc Figure 11.9 can hence be approximated as at Low frequencies

Short +

+

Vin

R

+ Vin

Vout

–

–

+ R

–

Vout –

A typical frequency response between the above two extremes is as shown. Applying the voltage divider rule in Fig. 11.8 RVin Vout = _______ R – jXC

(11.8)

where, magnitude of Vout is given by RVin ________ |Vout | = _________ 2 2 ÷R + XC Case: When

(11.9)

XC = R RVin _______ |Vout | = _________ ÷R2 + R2 1__ |Vout | = ___ Vin ÷2

From Eq. (11.2),

(11.10) 1

Vout Vin 1__ ___ | AV | = ____ = ___ = 0.707 at XC = R Vin ÷2 Vin

(11.11)

AV = Vout/Vin

0.707

which is shown in Fig. 11.11. Now, as per the assumption

f1

XC = R

f (log)

1 ______ =R 2pf1C 1 f1 = ______ 2pRC

Therefore,

(11.12)

In terms of dBs, 0.707 corresponds to 3 dB from Eq. (11.8) Vout R AV = ____ = _______ Vin R – jXC

(11.13)

R 1 1 AV = ________ = ___________ = ____________ R – jXC 1 – j(XC /R) 1 ______ 1–j 2pfCR Substituting Eq. (11.12) into Eq. (11.14), we get

(

)

1 AV = _________ 1 – j(f1/ ) When

(11.14)

(11.15)

f = f1 1 1__ _______ = ___ | AV | = ________ = 0.707, that corresponds to (–3 dB) 2 2 ÷ ÷1 + (1)

(11.16)

In general, “AV” can be written in magnitude and phase form. Vout tan–1(f1/f ) _________ AV = ____ = __________ Vin 1 + (f /f )2

÷

(11.17)

1

In the logarithmic form (dB), 1 _________ | AV | dB = 20 log10 __________ 1 + ÷ (f1/f)2

[ ( )]

f1 = – 10 log10 1 + __ f

(11.18)

2

(11.19)

If f1 >> f, ( f1/f )2 >> 1,

()

f1 |AV|dB = – 10 log10 __ f

2

f1 = – 20 log10 __ f Equation (11.20) can be used to find the future decibel plots, by ignoring the condition f > f1 a straight line is obtained only for the “0 dB” value, and hence it could be said that sloped line for such low frequency response can be obtained only when f > 1 Rs + hie (1 + hfe) RE __________ Rs + hie fp ª __________ 2p CE RE

From Eqs (11.28) and (11.29) fp >> fo. AV(LF) If ______ at f = fp is considered, AV(MF)

f __p 1 + j AV(LF) Rs + hie fo ______ = __________ × _______ AV(MF) (1 + hfe) RE 1 + j1 fp j __ Rs + hie fo ª __________ × ______ (1 + hfe) RE 1 + j1

(11.29)

The magnitude of this ratio is

|

|

AV(LF) Rs + hie ______ = __________ × __ AV(MF) (1 + hfe) RE ÷2 (1 + hfe) RE f __p ª __________ fo Rs + hie

But

Therefore,

f __p fo ___

|

|

AV(LF) 1__ ______ = ___ AV(MF) ÷2

(11.30)

1__ As the ratio of voltage gain has dropped by ___ , the power gain at this low frequency will be having a 2 ÷ 1 __ drop of or 3 dB form the gain at mid frequency. 2 Thus, the lower 3 dB frequency is (1 + hfe) RE 1 + __________ Rs + hie f1 ª fp = ______________ 2p CERE (1 + hfe) RE ª ________________ (Rs + hie) 2p CERE (1 + hfe) = _____________ (Rs + hie) 2pCE

(11.31)

when fp = fo. If this condition is not met, f1 π fp and there may not be a 3-dB point. From Eq. (11.31), 1 + hfe CE = ____________ 2pf1 (Rs + hie)

(11.32)

Thus CE determines the lower 3-dB frequency f1. Further, the equation for f1 does not include RE so that the choice of CE for a given f1 is dependent only upon the transistor and the source resistance. Note: (i) The use of electrolytic capacitors for CE cause reduction in the lower 3-dB frequency and the mid frequency gain. If RCE represents the series resistance of CE, – hfe RL AV(MF) = ____________________ Rs + hie + (1 + hfe) RCE (ii) If the effect of biasing resistors R1 and R2 are taken into account, – hfe RL AV(MF) = ______________ hfe Rs Rs + hie + _____ RB where

RB = R1 || R2.

(11.33)

(11.34)

For the CE amplifier in Fig. 11.18, calculate the mid frequency voltage gain and lower 3-dB point. The transistor has h-parameters of hfe = 400 and hie = 10 k . The circuit details are Rs = 600 , RL = 5 k , RE = 1 k , VCC = 12 V, R1 = 15 k , R2 = 2.2 k and CE = 50 F.

Solution

– hfe RL AV(MF) = ______________ hfe Rs Rs + hie + _____ RB – 400 × 5 × 103 = ________________________________ = – 145.69 400 × 600 600 + 10 × 103 + _________________ 15 × 103 || 2.2 × 103

Lower 3-dB point, (1 + hfe) f1 = _____________ (Rs + hie) 2 CE 1 + 400 = ______________________________ (600 + 10 × 103) × 2 × 50 × 10 – 6 = 120 Hz

In the CE amplifier of Fig. 11.18, it is desired to study the effect of coupling capacitor CC on the low frequency response. It is assumed that CE is large enough to cause no reduction in low-frequency gain. With RE effectively bypassed, the low frequency model for the CE amplifier with the coupling capacitor CC is shown in Fig. 11.20.

In the mid frequency range reactance of CC is negligible. Hence, the equations for AV(MF) given in Eqs (11.33) and (11.34) are valid. The lower 3-dB frequency Where

1 f1 = ______________ 2p (Rs + R¢i ) CC

(11.35)

R¢i = R1 || R2 || R i R i = hie for an ideal emitter bypass capacitor R i ª hie + (1 + hfe )R CE, if capacitor’s series resistance is taken into account.

Thus, from Eqs (11.31) and (11.35) for good low frequency response (for lower f1), the capacitors CC and CE should be large.

Calculate the coupling capacitor CC required in Fig. 11.20 to provide a low frequency 3 dB point at 125 Hz if Rs = 600 , hie = 1 k , hfe = 60, R1 = 5 k and R2 = 1.25 k . For (a) an ideal bypass capacitor CE, (b) a practical bypass capacitor with RCE = 25 .

Solution (a)

1 The lower 3 dB frequency, f1 = ______________ 2p (Rs + R¢i ) CC R¢i = R1 || R2 || hie 1 1 CC = ____________ = _____________________________________ 2pf1(Rs + R¢i ) 125 × 2p × [600 + 5000 || 1.25 × 103 || 1000] 1 = ____________________ 125 × 2p × [600 + 500] CC = 1.15 mF

(b)

R¢i = R1 || R2 || [hie + (1 + hfe) RCE] = 5000 || 1.25 × 103 || [1000 + (61) (25)] = 716.31 W 1 CC = ____________ 2pf1(RS + R¢i ) 1 = ______________________ = 0.97 mF 125 × 2p × [600 + 716.31]

At high frequencies, the capacitive effects of the transistor junctions and the delay in response of the transistor caused by the process of diffusion of carriers should be taken into account in determining the high frequency model of a transistor. A high frequency-p or Giacoletto model for a transistor is shown in Fig. 11.21. rbb¢ —base spreading resistance between the actual base B and virtual base B¢. It represents the bulk resistance of the base. Its typical value is 100 W. rb¢e —resistance between the virtual base B¢ and the emitter terminal E. Typical value is 1 kW.

rb¢c rbb¢

Cb¢c

B¢

B

rb¢e

C

rce

Vb¢e

gm Vb¢e

Cb¢e E

E

(a)

Input resistance from base to emitter with the output shorted is simply rbb¢ + rb¢e and this is the same as hie. Hence, hie = rbb¢ + rb¢e. rb¢c —resistance between the virtual base B¢ and the collector terminal C. It has a large value (typical value = 4 MW). Cb¢e — diffusion capacitance of the normally forward biased base-emitter junction. It has a typical value of 100 pF. Cb¢c — transistor capacitance of the normally reverse biased collector-base junction. It has a typical value of 3 pF. rce — output resistance with a typical value of 80 kW. Since rce >> RL, if a load RL is connected rce can be neglected. gmVb¢e — output current generator value where gm is the transconductance of the transistor.

The hybrid p model for the CE transistor at low frequencies is shown in Fig. 11.22(a). The h-parameter model for the same is shown in Fig. 11.22(b). As the hybrid model is drawn for low frequencies, the capacitive elements are considered as open circuit. B

Vbe

E

lb

rbb¢

lc

rbb =1/gb¢c

B¢

C

+ rb¢e = 1/gb¢e

Vb¢e

–

rb¢e = 1/gb¢e

gmVb¢e

Vce

E

Ib

ic

B

C +

hie

+ Vbs hreVce

hoe

hfe Ib

Vce

–

E

–

E

In the circuit shown in Fig. 11.22(b), the value of input resistance is equal to hie when the output terminals are short circuited, i.e. Vce = 0. Under these conditions for the circuit in Fig. 11.22(a), the input resistance is given by Zi |V Therefore

ce

=0

= rbb + rb e || rb c

hie = rbb + rb e || rb c

As rb c >> rb e, the above equation can be written as hie = rbb + rb e In the circuit shown in Fig. 11.22(b), if the input terminals are open-circuited, then the reverse voltage gain hre can be written in terms of the circuit in Fig. 11.22(a), and it is given by Vb e rb e hre = ____ = ________ r Vce b e + rb c Rearranging the above equation, we get rb e (1 – hre) = hre rb c As the value of hre is in the range of 10 – 4, the above equation can be approximated by rb e = hre rb c

or gb c = hre gb e

The equation also shows that the value of resistance rb c is much larger than resistance (rb e), i.e., rb c >> rb e. In the circuit shown in Fig. 11.22(b), if the input terminals are open circuited, then Vb e = hre Vce For the circuit in Fig. 11.22(a), with the input terminals open, i.e, Ib = 0, then the collector current Ic is given by Vce ________ Vce Ic = ___ rce + rb e + rb c + gm Vb e

The value of output admittance hoe is given by

|

Ic gm Vb¢e 1 1 hoe = ___ = ___ + ________ + ______ Vce Ib = 0 rce rb¢e + rb¢c Vce Substituting the value of Vbe in the above equation, we get Assuming that rb¢c >> rb¢e, the above equation can be rewritten in terms of conductance as gb¢c hoe = gce + gb¢c + gm ___ gb¢e Substituting gm = hfe gb¢e in the equation, we get hoe = gce + gb¢c + gb¢c hfe Rearranging the terms in the above equation, we get gce = hoe – (1 + hfe) gb¢c Since hfe >> 1, the above equation can be written as gce @ hoe – hfe gb¢c @ hoe – gm hre As the value of rb¢c is much greater than rb¢e, most of the current Ib flow through rb¢e in the circuit shown in Fig. 11.22(b) and the value of Vb¢e is given by Vb¢e @ Ib rb¢e The short-circuit collector current, Ic, is given by Ic = gm Vb¢e @ gm Ib rb¢e The short-circuit current gain, hfe is defined as Ic hfe = __ = gm rb¢e Ib Vce

|

Rearranging the above equation, we get gm rb¢e = hfe or gb¢e ___ hfe The transconductance of a transistor (gm) is defined as the ratio of change in Ic to change in Vb¢e for constant value of collector-emitter voltage. For common-emitter transistor configuration, the expression for collector current is given by Ic = ICO + a Ie The value of gm is given by

Ic gm = ____ Vb¢e

|

VCE

as the emitter diode (re) and the dynamic resistance of a forward-biased (rd) is given as VT rd = ___ ID where VT is the volt equivalent of temperature and ID is the diode current. Therefore, the value of gm can be generalized as

aIe Ic – ICO gm = ___ = _______ VT VT As Ic >> ICO, the value of gm for a NPN transistor is positive. For a PNP transistor, the analysis can be carried out on similar lines and the value of gm in the case of a PNP transistor is also positive. Therefore, the above expression for gm is written as |Ic| gm = ___ VT In the hybrid p model shown in Fig. 11.22(b), there are two capacitances namely the collector-junction barrier capacitance (Cc) and the emitter-junction diffusion capacitance (Ce). The capacitance Cc is the output capacitance of the commonbase transistor configuration with the input open (Ie = 0). As the collector-base junction is reverse-biased, Cc is the transition capacitance and it varies as (VCB)–n, where n is 1/2 for abrupt junction and 1/3 for a graded junction. The capacitance Ce is the diffusion capacitance of the forwardbiased emitter junction and is proportional to the emitter current Ie and is almost independent of temperature. For a given collector current, the conductances and resistances of the hybrid p circuit calculated from the low frequency h-parameter values from the equations are given in Table 11.1.

(i)

| | gm = ___ VT T where VT = ______ with T in K. At room temperature (300 K), VT = 0.026 V so that 11,600 IC (in mA) gm = _________ 26 mV

(ii)

hfe rb¢e = ___ gm

(iii)

rbb¢ = hie – rb¢e

(iv)

rb¢e 1 ___ rb¢c = ___ gb¢c = h re

(v)

gce

1 = ___ rce = hoe – (1 + hfe) gb¢c

A BJT has hie = 6 k and hfe = 224 at IC = 1 mA, with fT = 80 MHz and Cb¢c = 12 pF. Determine (a) gm (b)rb¢e (c) rbb¢ and (d) cb¢e at room temperature and a collector current of 1 mA. Determine the parameters, gm, rb¢e rbb¢ and Cb¢e of the small signal high frequency model of the BJT.

Solution IC (mA) 1 gm = _______ = ___ = 38.46 m mho 26 mV 26 hfe 224 ___________ rb e = ___ gm = 38.46 × 10 – 3 = 5.824 k rbb = hie – rb e = 6000 – 5824 = 176 gm Cb e = ____ – Cb c 2 fT 38.46 × 10 – 3 = ____________6 – 12 × 10 – 12 2 × 80 × 10 = 76.5 × 10 – 12 – 12 × 10 – 12 = 64.5 pF

A certain BJT transistor has r = 2 k and of fT, f and C .

Solution

We know that

or

fT = f =

= 100 at 1 MHz and

f

= 5 at 20 MHz. Determine the values

f

fT = 5 × 20 × 106 = 100 MHz fT 100 × 106 f = __ = _________ = 1 MHz 100

We know that

1 f = _______ 2 C r 1 1 × 106 = _____________3 2 C × 2 × 10 1 C = ____________________ = 80 2 × 2 × 103 × 1 × 106

B

The transistor’s high frequency capability can be known, if its CE short-circuit forward-current transfer ratio or current gain is found as a function of frequency. As RL is short circuited the approximate high frequency model becomes as shown in Fig. 11.23, where Cb e is in parallel with Cb c.

rbb¢

C +

Ii

rb¢e

Vb¢e

Cb¢e + Cb¢c

Hence,

gm Vb¢e

–

E

E

IL

The short circuit current gain is given by IL Ai = __ Ii From circuit of Fig. 11.23, IL = – gmVb¢e Vb¢e Ii = _________ rb¢e || – jXC Vb¢e = _________________ –j rb¢e || ____________ w (Cb¢e + Cb¢c) Vb¢e _____ – jrb¢e ____________ w (Cb¢e + Cb¢c) = _________________ j rb¢e – ____________ w (Cb¢e + Cb¢c) Vb¢e _________ – j(rb¢e)2 fb _________ f = __________ jrb¢e fb rb¢e – ______ f

[

1 Let fb = ________________ 2p rb¢e (Cb¢e + Cb¢c)

]

Vb¢e = _______ – jrb¢e fb _______ f – j fb Current gain,

– gm Vb¢e jgmrb¢e fb AI = ________ = ________ Vb¢e f – j fb _______ –jrb¢e fb _______ f – j fb jhfe fb = ______ f – j fb hfe fb = ________ – ( fb + jf) – hfe AI = _______ f 1 + j ___ b

(11.36)

1 fb = _______________ is the b cut-off frequency. 2prb¢e(Cb¢e + Cb¢c)

where

(11.37)

The b cut-off frequency fb , also referred to as fhfe, is the CE short-circuit small signal forward-currenttransfer-ratio cut-off frequency. fb is the frequency at which a transistor’s CE short-circuit current gain drops 3-dB from its value at lower (mid) frequencies. fb represents the maximum attainable band width for the current gain of a CE amplifier with a given transistor.

A CB amplifier has a much higher 3 dB frequency than a CE amplifier. The short-circuit current gain for CB amplifier which can be derived from the approximate high frequency circuit of the CB amplifier with output shorted is given by – hfb IL Ai = __ = _________ (11.38) Ii f 1 + j __ fa

()

hfe 1 fa = ________________ ª ________ 2prb¢e(1 + hfb) Cb¢e 2prb¢eCb¢e

Where

(11.39)

Substituting Eq. (11.37) in Eq. (11.39), hfe fb (Cb¢e + Cb¢c) fa = _______________ Cb¢e

(11.40)

fa is the ‘a’ (alpha) cut-off frequency at which the CB short-circuit small signal forward-current transfer ratio (Ai) drops 3 dB from its value at low frequencies (ª 1 kHz). Figure 11.24 shows the variation of Ai with frequency for CE and CB amplifiers and fa and fb Ai 100 b (Common-emitter)

hfe 0.707 hfe 10

b cut-off Gain-bandwidth product

0.707

1 hfb hfb

a Cut-off a (Common base)

0.1 2

10

3

10

4

10

5

10

6

10

7

10

8

10

Frequency in Hz

fa and fb defined in the last section gives an idea about the high-frequency capability of a transistor. An even more important characteristic is fT, which is defined as the frequency at which the short-circuit common-emitter current gain has a magnitude of unity. From Eq. (11.36),

hfe _________ | Ai | = __________ 1 + (f/fb)2

and at f = fT,

| Ai | = 1

(11.41)

÷

2

( )

fT From Fig. 11.17 fT is less than fa but much greater than fb and __ fB Hence, Eq. (11.41) reduces to

>> 1

hfe 1 ª ___ fT __ fb Then

fT __ ª hfe fb

(11.42)

fT ª hfe fb

(11.43)

fT is the product of low frequency current gain ‘hfe’ and b cut-off frequency, fb , or CE bandwidth. Similarly, it can be proved that fT ª hf b fa

(11.44)

Value of fT range from 1 MHz for audio transistor up to 1 GHz for high frequency transistors. Typical values of fb , fa and fT are 0.36 MHz, 95.9 MHz and 80.63 MHz. Substituting for fb from Eq. (11.37) in (11.43), 1 fT = hfe ________________ 2p rb¢e (Cb¢e + Cb¢e) hfe 1 _____________ = ___ rb¢e × 2p (C + C ) b¢e b¢c gm = _____________ 2p (Cb¢e + Cb¢c) Since Cb¢c >> Cb¢e,

(11.45)

gm gm fT ª ______ or Cb¢e = _____ 2pCb¢e 2p fT

fT Substituting fb = ___ in Eq. (11.36) hfe

– hfe Ai = ___________ f 1 + jhfe __ fT

( )

(11.46)

This equation shows the dependence of transistor’s short circuit current gain on the transistor’s gain at low frequencies “hfe” and the high frequency characteristics “fT”.

A BJT has gm = 38 mhos, rb¢e = 5.9 k , hie = 6 k , rbb¢ = 100 , Cb¢c = 12 pF, Cb¢e = 63 pF, and hfe = 224 at 1 kHz. Calculate and cut-off frequencies and fT.

Solution

hfe fa ª _________ 2prb¢e Cb¢e 224 = ________________________ = 95.9 MHz 2p × 5.9 × 103 × 63 × 10 – 12 1 fb = ________________ 2prb¢e (Cb¢e + Cb¢c) 1 = ____________________________________ = 0.359 MHz 2p × 5.9 × 103 × (63 × 10 – 12 + 12 × 10 – 12) gm fT = _____________ 2p (Cb¢e + Cb¢c) 38 × 10 0– 3 = _________________________ = 80.63 MHz 2p (63 × 10 – 12 + 12 × 10 – 12)

A certain BJT transistor has r = 2 k of fT, f , and C .

Solution

and

= 100 at 1 MHz and

= 5 at 20 MHz. Determine the value

We know that fT = b fb = bf f

or

fT = 5 × 20 × 106 = 100 MHz fT 100 × 106 fb = __ = _________ = 1 MHz 100 b

We know that

1 fb = _______ 2p Cp rp 1 1 × 106 = ______________3 2p Cp × 2 × 10

Hence,

1 Cp = ____________________ = 80 pF 2p × 2 × 103 × 1 × 106

With a resistive load connected in the output, the high frequency equivalent circuit of a CE transistor amplifier is shown in Fig. 11.25.

By using Miller’s theorem the circuit of Fig. 11.25 can be modified as described below. rbb¢

B

Cb¢c

B¢

C

+

rb¢e

Vb¢e

Cb¢e

gm Vb¢e

RL

VCE

–

E

E

From Fig. 11.25, the voltage gain, VCE – gm Vb e RL A = ____ = ___________ = – gmRL Vb e Vb e 1 – A = 1 – (– gmRL) = 1 + gm RL Since the impedance at the input gets decreased by a factor of (1 – A), the capacitance will be increased by a factor of (1 – A) or 1 + gmRL. The capacitance that is to be included in the output circuit will not make any significant change in the performance and may be neglected. This results in the modified equivalent circuit of Fig. 11.26. rbb¢

C

B¢

rb¢e

Cb¢e Vb¢e

Cb¢c (1 + gm RL)

B

E

gm Vb¢e

RL

VCE

E

The total input capacitance between B and E is C = Cb e + (1 + gmRL)Cb c

(11.47)

Since the circuit of Fig. 11.26 is essentially the same as that of Fig. 11.23, Eq. (11.37) can be used to find the upper 3 dB frequency. Hence, the upper dB frequency, 1 f2 = _______ (11.48) 2 rb e C

If the effect of source resistance Rs is also taken into account the upper 3-dB frequency f2 is given by 1 f2 = ______ 2pR¢C where

(11.49)

R¢ = (Rs + rbb¢) || rb¢e (Rs + rbb¢) rb¢e = ____________ Rs + rbb¢ + rb¢e (Rs + rbb¢) rb¢e = ____________ Rs + hie

and C is the total input capacitance given by C = Cb¢e + (1 + gm RL) Cb¢c If the effect of biasing resistors R1 and R2 are also taken into account, then (R¢s + rbb¢)rb¢e R¢ = ___________ R¢s + hie where

R¢s = Rs || RB

(11.50)

and RB = R1 || R2

Thus, the source and biasing resistors have a strong influence in determining the upper 3 dB frequency f2.

Consider a cascode amplifier with transistor and the circuit parameters are r = 2 k , gm = 0.05 , = 100, C = 19.5 pF, C = 0.5 pF, Rs = 300 and RC = 1.5 k . Determine fH and mid-band gain G of cascode amplifier and CE amplifier.

Solution

Here, R¢s = Rs || rp = 300 || 2000 = 260 W.

For cascode amplifier We know that Here, Therefore,

1 wH = ____________ R¢s (Cp + 2Cm) Cp + 2Cm = 19.5 + 2 × 0.5 = 20.5 pF wH 1 fH = ___ = _________________ 2p 2p × R¢s (Cp + 2Cm) 1 = ______________________ ª 30 MHz 2p × 260 × (20.5 × 10–12)

The mid-band gain, RC b ______________ 1.5 × 103 × 100 G = ____ = 75 rp = 2 × 103

For CE amplifier Considering the CE amplifier with same transistor and gain, G = 75 CT = Cp + GCm = 19.5 × 10–12 + 75 × 0.5 × 10–12 = 57 pF 1 1 fH = _______ = ________________________ = 10.7 MHz 2p R¢sCT 2p × 0.26 × 103 × 57 × 10–12 It is inferred that with the same mid-band gain, the cascade configuration has a bandwidth three times that of CE configuration.

A BJT transistor amplifier shown in Fig. 11.27 has RE = RC = 1 k , RS = 600 , RL = 2 k and transistor parameters as = 100 and r = 1 k . Determine the values of CC1, CC2 and CE needed to obtain fL = 50 Hz.

Solution

w1p = 2p fL = 100 p rad/s

We know that

1 w1p = ___________, C ¢E (Rs + rp)

Therefore,

1 C ¢E = ___________ w1p (Rs + rp) 1 C ¢E = __________ = 1.99 mF 100 p × 1.6

We know that CE = (1 + b)C ¢E CE = 101 × 1.99 × 10–6 = 201 mF w1p 100 p 1 We know that w1l = ___ = _____ = 10 p = ____________ 10 10 (Rs + Rp) CC1 1 CC1 = _________ = 19.9 mF 10p × 1.6 We choose Therefore, Hence,

w1p 100 p w12 = ___ = _____ = 5p. 20 20 1 _____________ w12 = 5p = (RC + RL) CC2 1 1 CC2 = ____________ = ___________3 = 21.23 mF w12 (RC + RL) 5p × 3 × 10

Since w12 is inversely proportional to CC2, we can choose any value CC2 > 21.23 mF. Hence, let us choose CC2 = 22 mF.

A silicon BJT small signal amplifier shown in Fig. 11.28 has the circuit parameters as follows:

VCC = 10 V, R1 = 11.5 k , R2 = 41.4 k , RC = 5 k , RE = 1 k Rs = 1 k , CE = 150 F, CC1 = CC2 = 20 F and = 50 C = 100 pF, C = 5 pF, CW + CL = 5 pF and RL = 10 k . Determine (a) dc bias values (b) mid-frequency gain (c) low-frequency cut-off, and (d) high-frequency cut-off. Solution (a) To determine dc bias values: RB = R1 || R2 = 11.5 × 103 || 41.4 × 103 = 9 k R1 11.5 × 103 VBB = _______ VCC = ________________3 × 10 = 2.174 V R 1 + R2 (11.5 + 41.4) × 10 VBB – 0.7 2.174 – 0.7 IB = ______________ = ___________________ RB + RE (1 + ) 9 × 103 + 1 × 103 × 51

0.0246 mA

IC = IB = 50 × 0.0246 × 10–3 = 1.23 mA VCE = VCC – IC RC – (IC + IB) RE = 10 – 1.23 × 10–3 × 5 × 103 – (1.23 + 0.0246) × 10–3 × 1 × 103 = +2.595 V (b) To determine mid-frequency gain: The mid-frequency circuit model is shown in Fig. 11.29. Assume

Vs = 1 V 25 25 × 50 r = _______ = _______ = 1 k 1.23 IC (mA) Vs × (RB || r ) Vbe = ____________ Rs + (RB || r ) 9 × 103 × 1 × 103 RB || r = _______________ = 0.9 k 9 × 103 + 1 × 103

Given Therefore

Rs = 1 k 1 × 0.9 × 103 Vbe = _____________3 = 0.474 V (1 + 0.9) × 10

Vbe _______ 0.474 Ib = ___ rp = 1 × 103 = 0.474 mA bIb = 50 × 0.474 × 10–3 = 23.7 mA 10 Ro = RC || RL = 5 × 103 || 10 × 103 = ___ kW 3 10 ___ 3 Vo = –bIb Ro = – 23.7 × 10 × × 103 = –79 V 3 Vo AVo = ___ = – 79 Vs (c) To determine low-frequency cut-off: 1 1 w11 = _________________ = _____________________ = 26.3 rad/s CC1 [Rs + (rp || RB)] 20 × 10–6 (1 + 0.9) × 103 1 1 w12 = _____________ = _____________________ = 3.3 rad/s CC2 (RC + RL) 20 × 10–6 (5 + 10) × 103 1 1 w1p = ________________ = ____________________________ = 179 rad/s CE [(Rs || RB) + rp] (150/51) × 10–6 × (0.9 + 1) × 103 As w1p > w11 > w12,

wL = w1p = 179 rad/s = 28.5 Hz

(d) To determine high-frequency cut-off: 1 w21 = _______________ Ceq (Rs || RB || rp) 1 w22 = _____ CoRo where

Ceq = Cp + Cm (1 + gm Ro)

(

1 Co = Co¢ + Cm 1 + _____ gm R o where

)

Co¢ = CW + CL = 5 pF Cp = 100 pF b ___ 50 gm = __ rp = 1 = 50 mS 10 Ro = ___ kW 3 10 500 gm Ro = 50 × 10–3 × ___ × 103 = ____ 3 3

Substituting the values,

(

)

500 Ceq = 100 × 10–12 + 5 × 10–12 1 + ____ ª 938.3 pF 3

(

)

3 Co = 5 × 10–12 + 5 × 10–12 1 + ____ ª 10 pF 500 R¢s = RB || Rs = 9 × 103 || 1 × 103 = 0.9 kW R¢s || rp = 0.9 × 103 || 1 × 103 = 0.474 kW Therefore,

1 w 21 = _______________ Ceq (Rs || RB || rp) 1 = ________________________ = 2.25 × 106 rad/s or 0.358 MHz 938.3 × 10–12 × 0.474 × 103 1 1 w22 = _____ = ___________________ = 30 × 106 rad/s or 4.77 MHz Co Ro 10 – 12 ___ 10 × 10 × 103 3

( )

Thus

wH = 0.358 MHz, since f21 < f22.

An RC-coupled amplifier has equal input and output-circuit corner frequencies in the high-frequency band as given by 21

=

22

=

2

= 250 × 103 rad/s

Calculate the cut-off frequency of this band. Solution

AV 0 AVH = __________ 1 + j (w /w2) AV0 __________ | AVH | = ____________ ÷1 + j (w /w2) __

The gain at 3 dB cut-off frequency is 1/÷2 of its mid-frequency gain. Therefore, AVO AVO ___________ = ____ __ AVH (wH) = ____________ ÷1 + (wH/w2)2 ÷2 Solving for wH, we have wH = w2 = 250 × 103 rad/s

Let us analyse the high frequency response of an emitter follower i.e., common collector amplifier circuit shown in Fig. 11.30. If the transistor of the circuit is replaced by its high frequency model, we get the high frequency equivalent circuit shown in Fig. 11.31, with the coupling capacitors acting effectively as short circuits. The emitter follower circuit has a zero and two poles. Assuming that Cb¢e is open-circuited and Vs = 0, the equivalent circuit is as shown in Fig. 11.32(a). Looking the resistance to the left of Cb¢c, we get

RC

b c1

= RB || Rs.

Looking the resistance to the right of Cb c, we get RC

b c2

= [rb e + (1 + ) (RE || RL)].

Thus, Thevenin’s equivalent resistance presented to Cb c is R C = RC bc

bc 1

|| RC

bc 2

= (RB || Rs) || [rb e + (1 + ) (RE || RL)].

Assuming that Cb e is open-circuited, its equivalent circuit will be as shown in Fig. 11.32(b). To determine RC , we can remove Cb e and apply a test voltage vx as shown in Fig. 11.32(c). be

Using Kirchhoff’s voltage law around the loop formed by RB in parallel Rs and by RL in parallel with RE, we get vx vx ___ vx = (RB || Rs) ix – ___ rb e + (RL || RE) ix – rb e – gm vx)

(

)

(

)

Simplifying, we get

[

RB || Rs _______ RL || RE ix(RB || Rs + RL || RE) = vx 1 + _______ + r + gm (RL || RE) r i.e.

be

be

ix ___ 1 + gm (RL || RE) 1 __ ________________ vx = rb e + R || R + R || R be

s

L

E

Therefore, Thevenin’s equivalent resistance presented to Cb e is vx RB || Rs + RL || RE RC = __ = rb e || ________________ be ix 1 + gm (RL || RE)

]

Hence, the high 3 dB frequency is

1 fH = _____________________ 2p (RC Cb¢e + RC Cb¢c) b¢e

b¢c

Calculate the high 3 dB cut-off frequency fH of BJT Emitter follower as shown in Fig. 11.32, whose parameters are Cb¢e = 15 pF, Cb¢c = 1 pF, gm = 57.14 m mho, = 80, Rs = 200 , rb¢e = 1.4 k .

Solution

RB = R1 || R2 = 75 × 103 || 4.35 × 103 = 3.66 kW

We know that

1 fH = _____________________ 2p (RC Cb¢e + RC Cb¢c) b¢e

where

b¢c

RB || Rs + RL || RE RC = rb¢e || ________________ b¢e 1 + gm (RL || RE) RC = (RB || Rs) || [rb¢e + (1 + b) (RE || RL)] b¢c

RC = (2.665 × 103 || 200) || [1.45 × 103 + (1 + 80) (330 || 55 × 103)] b¢c

= 184.6 W

RC = 1.4 be

(2.66 × 103 || 200) + (5 × 103 || 330) || ______________________________ 1 + 57.14 × 10 – 3 × (55 × 103 || 330)

= 26.02 Hence, the 3 dB upper cut-off frequency is 1 fH = _____________________ 2 (RC Cb e + RC Cb c) be

bc

1 = _____________________________________ 2 (20.02 × 15 × 10–12 + 184.6 × 1 × 10–12) = 276.9 MHz

In the high frequency model of FET, the capacitances between nodes have to be added in the low frequency model. The resulting equivalent circuit is shown in Fig. 11.33. Cgd

Cgs represents the barrier capacitance between gate and source. Cgd is the barrier capacitance between gate and drain. Cds is the drain to source capacitance of the channel. These interval capacitances leads to feedback from output to input and the voltage amplification decreases at higher frequencies.

G

Range

gm

0.1 – 1 M

S

S

cds

Cgs , Cgd

0.1 – 1 pF

1 – 10 pF

rd

0.1 – 10 mA/V

Cds

rd

gm Vgs

Cgs

The parameters of FET shown in Fig. 11.33 will have their magnitudes as given in Table 11.2.

Parameter

D

rgs

rgd

>108

>108

The circuit of Fig. 11.34 shows the CS amplifier. The equivalent circuit at high frequencies is shown in Fig. 11.35. Cgd + VDD ZL

D G + –

Vi

G

+

Vo S

–

D +

+

Vi –

S

Cgs

gmVi

Cds

rd

ZL

Vo

– S

The Norton’s equivalent circuit between D & S can be obtained by finding the short circuit current from D to S and impedance Z seen from output point with independent voltage sources short circuited and independent current sources open circuited. With Vi = 0, current gmvi = 0, the circuit of Fig. 11.35 reduces to circuit of Fig. 11.36.

D

Cgd

ZL

rd

Cds

Z

S

Hence admittance at the output point 1 Y = __ = YL + gd + Yds + Ygd Z Where

(11.51)

1 YL = ___ is admittance corresponding to ZL ZL 1 gd = __ rd is conductance corresponding to rd Yds = j Cds is admittance corresponding to Cds Ygd = j Cgd is admittance corresponding to Cgd.

Cgd D

The equivalent circuit to find the short circuit current from D to S is shown in Fig. 11.37.

+

Hence, current

–

I = –gmVi + ViYgd

(11.52)

Voltage gain (amplification) AV with load ZL included

Vi

gmVi

I S

is given by Vo IZ I AV = ___ = ___ = ____ Vi Vi Vi Y From Eqs (11.51) and (11.52), – gm + Ygd AV = _________________ YL + gd + Yds + Ygd

(11.53)

At low frequencies, FET capacitances can be neglected and hence, Yds = Ygd = 0 Eq. (11.53) at low frequencies reduces to – gm – gm AV = ________ = _______ YL + gd ___ 1 1 + __ ZL rd – gm rd ZL AV = _________ = – gm ZL rd + ZL where

(11.54)

ZL = ZL || rd

From Fig. 11.35, it is found that the Gate circuit is not isolated from drain circuit, but connected by Cgd .

According to Miller’s theorem, an impedance Z connected between two points (1) & (2) of a circuit Z AV Z can be replaced by Z1 = ______ from (1) to Ground and Z2 = _______ from (2) to Ground, where AV is 1 – AV AV – 1 the voltage gain V2 /V1. Applying Miller’s theorem to circuit of Fig. 11.35 the circuit of Fig. 11.38 is obtained, where capacitances are replaced by equivalent admittances. D

G Cds ZL

+

Vi –

Ygs

Ygd (1 – AV)

Ygd 1 – 1 AV

gmVi

rd

S

S

Hence the input admittance is given by Yi = Ygs + (1 – AV)Ygd

(11.55)

As Ygs = j Cds and Ygd = j Cgd for an FET to possess negligible input admittance over a wide range of frequencies, the gate-source and gate-drain capacitances must be negligible. From Eq. (11.54), the voltage gain AV = – gm ZL where ZL = ZL || rd . For an FET with drain-circuit resistance Rd, the voltage gain AV = – gmRd where Rd = Rd || rd. From Eq. (11.55) Yi = Ygs + (1 + gm Rd) Ygd Yi = j Cgs + (1 + gm Rd) j Cgd Yi ___ = Ci = Cgs + (1 + gm Rd) Cgd j

(11.56)

The increase in input capacitance Ci over the capacitance from gate to source is the Miller effect. In multistage (cascaded amplifiers) this input capacitance appears in shunt with output impedance of previous stage. As capacitive reactance decrease with increase in frequency, the resultant output impedance will be lower at higher frequencies, thereby reducing the gain. The output impedance for the CS amplifier of Fig. 11.36 is obtained by setting input voltage Vi = 0 and looking from the output point. The resultCgd ing equivalent circuit is shown in Fig. 11.39. The output admittance with ZL considered external to CS amplifier circuit is given by Yo = gd + Yds + Ygd

(11.57)

Cds rd

Zo =

1 Yo

The Common-Drain amplifier (Source-follower) circuit is shown in Fig. 11.40 and its high frequency equivalent circuit is shown in Fig. 11.41.

The small signal high frequency equivalent circuit of CD Amplifier is shown in Fig. 11.41. The output voltage Vo is the product of the short-circuit current and the impedance between terminals S and N. It is found to be, voltage gain (gm + j Cgs) Rs AV = _____________________ 1 + (gm + gd + j CT) Rs where

CT

(11.58)

Cgs + Cds + Csn

Cgs is the capacitance from gate to source, Cds is the capacitance from drain to source and Csn is the capacitance from source to ground. At low frequencies, the voltage gain reduces to gm R s AV ______________ 1 + (gm + gd) Rs The amplification is positive and has a value less than unity. If gmRs >> 1, then gm gm Rs AV _____________ = _______ = _____ gm + gd gm Rs + gd Rs +1 The input admittance Yi is obtained by applying Miller’s theorem to Cgs. Yi = j Cgd + j Cgs (1 – AV) Yi

j Cgd as AV

1

The CD amplifier offers the important advantage of lower input capacitance than the CS amplifier. The output admittance with input voltage set to zero is given by Yo = gm + gd + j CT

where Rs is considered external to the amplifier. At low frequencies, the output admittance Yo gm + gd 1 1 and output resistance Ro= _______ = ___ since gm >> gd . gm + gd gm The CD amplifier (Source follower) is used for the same application as emitter follower, in applications requiring high input impedance and low output impedance.

In the case of FET amplifier, the high frequency characteristic of the amplifier is determined by the interelectrode and wiring capacitances. The capacitor Cgs and Cgd typically vary from 1–10 pF, while the capacitances Cds is usually quite a bit smaller, ranging from 0.1–1 pF. At high frequencies, Ci (miller capacitance) will approach a short-circuit equivalent and Vgs will drop and in value and reduce the overall gain. The cut-off frequencies defined by the input and output circuits can be obtained by first finding the Thevenin equivalent circuits for each section as shown in Fig. 11.42.

RThi = RSig || RG

RTho = RD || RL|| rd

–

+

EThi

Ci –

ETho

Co +

(i)

For the input circuit shown in Fig. 11.42(b) fHi = 1/(2 RThiCi) where RThi = RSig||RG Ci = Cgs + (1 + gm Rd)Cgd

(ii)

and for the output circuit shown in Fig. 11.42(b) fHo = 1/(2 RThoCo) where RTho = RD||RL||rd

For a second transistor stage connected directly to the output of the first stage, there will be significant change in the overall frequency response. There will be additional low frequency cut-off levels due to the second stage that will further reduce the overall gain of the system in this region. For each additional stage, the upper cut-off frequency will be determined primarily by the stage having the lowest high frequency cut-off frequency. The low frequency cut-off is primarily determined by that stage having the highest low frequency cut-off frequency. Hence one poorly designed stage can off set an otherwise well designed cascaded system. The effect of increasing the number of identical stages, having the same lower and upper cut-off frequencies, can be clearly demonstrated by considering Fig. 11.43. AV 0

f (log scales)

–3 dB –6 dB –9 dB –12 dB

n=1 n=2 n=3

–15 dB –18 dB

f1 f1 f1 (n = 1) (n = 2)(n = 3)

f 2 f2 f2 (n = 3) (n = 2)(n = 1)

For a single stage, the cut-off frequencies are f1 and f2 as indicated. For two identical stages in cascade, the drop off rate in the low and high frequency regions has increased to –12 dB/octave or – 40 dB per decade. At f1 and f2, therefore, the decibel drop is now –6 dB, rather than the defined band frequency gain level of –3 dB. The –3 dB point has shifted to f1 and f2 as indicated, with a resulting drop in the bandwidth. A –18 dB/octave or –60 dB/decade slope will result for a three stage system of identical stages with indicated reduction in bandwidth (f1 and f2 ). Assuming identical stages, an equation for each band frequency as a function of the number of the stages (n) can be determined in the following manner. For the low frequency region, AV low(overall) = AV1 low AV2 low AV3 low … AVn low

As each stage is identical, AV1 low = AV2 low = … = Avn low AV low(overall) = (AV low)n

Therefore,

AV low/AV mid (overall) = (AV low/AV mid)n = 1/[1 – j( f1/f )]n __

Setting the magnitude of the result equal to 1/÷2 (–3 dB level) results in ___________

__

1/÷[1 + (f1/f1¢)2]n = 1/÷2 Rearranging the above we get

___________ – n

{ ÷[1 + (f1/f1¢)2] }

__

= 1/÷2

{[1 + ( f1/f1¢ )2]1/2}n = (2)1/2 {[1 + ( f1/f1¢ )2]}n = 2 1 + ( f1/f1¢ )2 = (2)1/n and hence we get

[

________

f1¢ = f1/ ÷(2)1/n – 1

]

In a similar manner, it can be shown that for the high frequency region. ________

f2¢ =

[ ÷(2)1/n – 1 ]

f2

________

The presence of

[ ÷(2)1/n – 1 ] is to be noted in both f1¢ and f2¢. The magnitude of this factor for various

values of n is listed below. ________

n

[ ÷(2)1/n – 1 ]

2

0.64

3

0.51

4

0.43

5

0.39

For n = 2, consider the upper cut-off frequency f2¢ = 0.64 f2 or 64% of the value obtained for a single stage, while f1¢ = (1/0.64) f1 = 1.56 f1. For n = 3, consider the upper cut-off frequency f2¢ = 0.51 f2 or approximately half the value of a single stage, while f1¢ = (1/ 0.51) f1 = 1.96 f1 or approximately twice the single stage value. A decrease in bandwidth is not always associated with an increase in the number of stages if the midband gain can remain fixed and independent of the number of stages.

RF amplifiers are circuits that amplify signals that lie in the RF (Radio Frequency) portion of the frequency spectrum. As there is no common agreement for the RF range, a better definition of RF amplifiers is based on their function. Thus, RF amplifiers are amplifiers that select and amplify a narrow band of high frequency signals as shown in Fig. 11.44.

Gain

Band pass of RF amplifier Band pass of A-F amplifier Band pass of video amplifier

20 kHz

200 kHz

2 kHz

20 MHz

Frequency

From Fig. 11.44, while audio and video amplifiers amplify only a fixed band of frequencies, the frequencies to be amplified by an RF amplifier can be varied. Generally, RF amplifiers are tuned amplifiers which select and amplify a narrow band of signals.

In a television receiver or a transmitter, it is required to amplify the video signals obtained from the detector or generator. As the video signals occupy the frequency range from 30 Hz to 5.5 MHz, the amplifier should have wide bandwidth to amplify such signals without any distortion. The requirements of a video amplifier are: (i) All the frequencies within the video bandwidth must be amplified equally in order to maintain the same relative amplitudes, i.e. the frequency response must be flat over the video bandwidth of 30 Hz to 5.5 MHz, and (ii) The relative phases of all the frequency components in the output must be the same as at the input, otherwise distortion results in the shape of the waveform. A typical two stage video amplifier is shown in Fig. 11.45. In this circuit, additional components have been added to extend the signal frequency range to the required level. One of these units is the shunt inductor L5 which parallels capacitances of both the transistors and those formed within the circuitry. The latter consists of capacitances from the wiring to ground and metallic components to ground. The inductance of L5 in parallel with circuit capacitances form a low Q broadly resonant circuit for the upper frequency signals. As a parallel LC combination offers high impedance for signals at resonant frequency, the shunting effects for high frequency signals are minimised. In addition, the narrow band of signals on either side of resonance also encounter sufficient impedance to prevent signal attenuation. Such an inductor L5 is termed as peaking coil, and in Fig. 11.45 this coil is in series with R6, to which the collector potential is applied.

C1 IF Signal input

L1

To sound IF amplifiers

L2

Q1 Video detector

L4

R5

To sync circuits

+V

Q2 R2

C4 L5

C2 R1

L3

C3

R3

R8

Contrast

R4

4.5 MHz Trap

R1

R6

R9

– V Pix tube

Brightness

–V

Another peaking coil L4 is in the collector circuit of Q2 and isolates shunt capacitances of the two amplifiers. A shunting resistor R2 loads the coil L4 to minimise transient oscillations that may cause oscillations or ringing. This inductor in series with any circuit capacitance will have a low impedance bandpass for high frequency signals. Inductor L3 forms a 4.5 MHz series resonant circuit with capacitor C2. As a series resonant circuit offers low impedance at the frequency of resonance, 4.5 MHz signals are shunted and hence are not applied to the Q2 input where they would eventually cause interference patterns on the picture screen. Both the demodulated picture and sound intermediate frequency (IF) signals are applied to the base input of Q1. In addition, the 4.5 MHz signal is produced in the video detector and this is a lower frequency version of the sound IF signal generator in the tuner. Transistor Q1 feeds the demodulated signals to the base of Q2 for amplification and application to the picture tube. Sound signals are trapped out as shown in Fig. 11.45. The 4.5 MHz sound IF signal present in the emitter–collector circuitry of Q1 is applied to a parallel resonant circuit tuned to this signal. A transformer is created by the coupling of L1 to L2 as shown. Thus, the resonant circuit composed of C1 and L1 tend to reject all signals except the 4.5 MHz sound signal to which it is tuned. Resistor R3 in the emitter of Q2 alters the bias potential when the variable arm is adjusted. Thus, the gain of this transistor is set by the viewer to the level desired. Resistor R4 prevents the emitter from being directly connected to the ground when the variable arm R4 is at the top of R3. Brightness is regulated by adjusting R9, as the picture tube cathode is made more positive with respect to the control grid, the latter becomes more negative and hence repels more of the electrons coming from the cathode structure. Consequently, beam intensity is decreased as is the brightness level. For a less positive picture tube cathode, control grid bias is reduced, more current flows and brightness increases.

The frequency response of a transistor is controlled by the interelectrode capacitances along with the various resistances in the circuit. In this section, the frequency response of the transistor common emitter stage is analysed to determine the factors influencing the design of a video amplifier.

Figure 11.46 shows the basic common emitter amplifier with the d.c. biasing details omitted for simplicity. The transistor junction capacitances and the base spreading resistance are shown as external elements for the purpose of analysis. Further the source resistance Rs, the load resistance RL and the load capacitance CL are included in this circuit.

Cb¢c C Rs

rbb¢

B

B¢

B RL

rbb¢

CL

E

Vs Cb¢e

In Fig. 11.47, a small signal a.c. equivalent circuit for the common emitter stage of Fig. 11.46 is shown. The signal source Vs and series resistance of Rs + rbb is transformed into an equivalent current source iS 1 in parallel with conductance G1 = _______, leading to the equivalent circuit of Fig. 11.48. Rs + rbb

Cb e

B

C

1/RL

is

G1

Cb e

gb e

CL gmVb e

In the following analysis, Kirchhoff’s current law (KCL) equations are written for nodes B and C. Current coming out of node B = Vb G1 + Vb ( j Cb e) + Vb e gb e + (Vb – Vc ) j Cb c Current flowing into node B = is Applying KCL to node B , Vb [G1 + gb e + j (Cb e + Cb c)] = is + j Cb c Vc Current coming out of node C = Vc GL + gmVb + Vc ( j CL)

(11.59)

Current flowing into node C = (Vb¢ – Vc) jw Cb¢c Applying KCL to node C, Vc [GL + j w (Cb¢c + CL)] + gm Vb¢ = jw Cb¢c Vb¢ (jwCb¢c – gm) Vc = Vb¢ _________________ GL + jw (Cb¢c + CL) – [gm – jwCb¢c] Vb¢ = _________________ GL + jw (Cb¢c + CL)

(11.60)

Substituting for Vc in Eq. (11.59),

[

]

jwCb ¢c(gm – jwCb¢c) Vb¢ [G1 + gb¢e + jw (Cb¢e + Cb¢c) + _________________ = iS GL + jw (Cb¢c + CL) gb¢e is the dynamic input conductance of the transistor looking into the base given by dIB IB 1 _____ ____ gb¢e = ___ rb¢e = dV = hVT BE where h is a dimensionless factor ranging from 1 to 2, typically 1.5. Hence, iS V¢b = _________________________________________ jwCb¢c (gm – jwCb¢c) G1 + gb¢e + jw (Cb¢e + Cb¢c) + _________________ GL + jw (Cb¢c + ) Substituting for V b¢ in Eq. (11.60), iS – [gm – jwCb¢c] Vc= _________________ × _________________________________________ GL + jw (Cb¢c + CL) jwCb¢c (gm – jwCb¢c) G1 + gb¢e + jw (Cb¢e + Cb¢c) + _________________ GL + jw (Cb¢c + CL)

{

Since

}

Vs iS = _________ = VsG1 (Rs + r¢bb)

{

– [gm – jwCb¢c] Vs G1 Vc = ________________ × _________________________________________ GL + jw (Cb¢c + CL) jwCb¢c (gm – jwCb¢c) G1 + gb¢e + jw (Cb¢e + Cb¢c) + _________________ GL + w (Cb¢c + ) Voltage gain, Vc – (gm – jwCb¢c) AV = ___ = _________________ × Vs GL + jw (Cb¢c + CL)

{

}

G1 _________________________________________ jwCb¢c (gm – jwCb¢c) G1 + gb¢e + jw (Cb¢e + Cb¢c) + _________________ GL + jw (Cb¢c + CL)

}

(11.61)

This is rather a complicated expression for frequency dependence of voltage gain, which can be simplified by the following approximations:

1. In the frequency range of interest as gm >> wCb¢c; gm – jwCb¢c ª gm, the input conductance. 1 2. gb¢e > w (Cb¢c + CL) and gm >> w Cb¢c. gm – jwCb¢c gm so that _________________ ª ___ = gm RL. GL + jw (Cb¢c + CL) GL Using these approximations, – gm G1 AV ª ________________________________________________ [GL + jw (Cb¢c + CL)] [G1 + jw (Cb¢e + Cb¢c + gm RL Cb¢c)]

(11.62)

Two break point radian frequencies can be defined as 1 1 w1 = ___________________ = ____________________________ Cb¢e + Cb¢c(1 + gm RL) (Rs + r¢bb) [Cb¢e + Cb¢c(1 + gm RL)]

1 = ___________ (Rs + r¢bb) Ci

(11.63)

where Ci = Cb ¢e + Cb¢c (1 + gm RL) In the net input capacitance Ci, the base–collector capacitance Cb¢c is multiplied by 1 + gm RL = 1 – A by applying Miller’s theorem (refer to Section 11.9.7). GL 1 w2 = _________ = ____________ (11.64) Cb¢c + CL RL(Cb¢c + ) The equation for voltage gain AV can now be rewritten in terms of two break point frequencies as – gm/GL – gm RL AV ª ___________________ = _________________ (11.65) [1 + jw/w1] [1 + jw/w2] [1 + j f/f1] [1 + j f/f2] w1 w2 f1 = ___ and f2 = ___ 2p 2p For a video IF amplifier, it is necessary that the two characteristics or breakpoint frequencies f1 and f2 be sufficiently large since the bandwidth will be lesser than either of these two frequencies. Further, since f1 is smaller than f2, f1 will be the principal factor in determining the bandwidth of the amplifier stage. where

In order to achieve a wide bandwidth from Eqs (11.63) and (11.64), the following steps have to be taken: 1. Decrease RL, thereby gain is traded-off for increased bandwidth. 2. Decrease Rs to a small value. 3. Decrease the net load capacitance. 4. Choose a transistor with a small value of Cb¢c (i.e., a high-frequency transistor). 5. Choose a transistor with a small value of base spreading resistance rbb¢. 6. Choose a transistor with a small value of Cb¢e. 7. Use one or more negative feedback loops, to trade-off reduced gain for increased bandwidth.

The main aim of a large signal amplifier, otherwise called as a power amplifier is to deliver a substantial amount of power to a load. If the operation is almost linear, the equivalent circuit method is applied; otherwise, the graphical method can be used to obtain accurate results. The maximum power rating of a transistor is related to the maximum allowed device temperature at which the device can operate without being damaged. The type of operation of a power amplifier, such as Class-A or Class-B or Class-C, is decided by its ultimate power. In a Class-A amplifier, the output transistor conducts 100% of the time. Its theoretical maximum conversion efficiency is 25%, which can be increased to 50% by using inductors or transformers. In a Class-B amplifier, the output stage is composed of complementary pair of transistors operating in a push-pull manner, where each output transistor conducts 50% of the time. Its theoretical maximum conversion efficiency is 78.5%. If an extremely large amount of power over a narrow range of frequencies is to be obtained, tuned Class-B or Class-C operation is generally preferred. Hence the transistor power amplifier stage should be so designed that the power conversion efficiency is maximum and the collector dissipation of the transistor is minimum.

Based on the amount of transistor bias and amplitude of the input signal, amplifiers can be classified as Class A, Class B, Class AB and Class C. In a Class A amplifier, the transistor is biased such that the output current flows, i.e. the transistor is ON for the full cycle (360°) of the input ac signal as shown in Fig. 12.1. Io

Input signal

Ii

wt p

2p

3p

4p

Av

Amplifier

0

Output signal

p

2p

3p

360° Conduction

4p

wt

In a Class B amplifier the transistor bias and the amplitude of the input signal are selected such that the output current flows, i.e. the transistor is ON for only one half cycle (180°) of the input ac signal as shown in Fig. 12.2. Ii

Io

2p

p

wt Av 4p Amplifier

3p

0

2p

p

3p

wt

4p

Class-B 180° Conduction

In a Class AB amplifier, the transistor operates between the two extremes defined for Class A and Class B amplifiers. Hence, the output signal exists for more than 180° but less than 360° of the input ac signal. In a Class C amplifier, the transistor bias and the amplitude of the input signal are selected such that the output current flows, i.e. the transistor is ON for less than one half cycle (180°) of the input ac signal as shown in Fig. 12.3. Io

Ii wt p

2p

3p

4p

Av

wt p

2p

3p

4p

Amplifier 120° –150° Conduction

A simple transistor amplifier that supplies power to a pure resistance load RL is shown in Fig. 12.4. Assuming that the static output characteristics are equidistant for equal increments of input base current iB, if the input signal iB is a sinusoidal the output current and voltage are also sinusoidal as shown in Fig. 12.5, ic, vc are instantaneous deviations from quiescent values IC and Vc. The power output is given by the equation P = Vc × Ic = I 2c × RL, where Vc and IC are the RMS values of the output voltage vc and current ic, respectively. From Fig. 12.5,

Imax – Imin Im _________ __ = __ and Ic = ___ 2 2 2 Vmax – Vmin Vm __________ __ = __ Vc = ___ 2 2 2

IB1

ic ic

Imax

1

Im 0

p/2 p 2p

wt

IB2

Q

Ic

2

Imin

Vmax

Vmin VC vm

IB3

VCC

vc

0 p

p/2 2p

wt

(Vmax – Vmin) (Imax – Imin) P = VcIc = ______________________ 8 The power output can be expressed in terms of RL: The power output,

Vm Im I 2m RL V 2m P = VcIc = _____ = ______ = _____ 2 2 2 RL

(12.1)

(12.2)

Since the dynamic transfer curve shown in Fig. 12.6 is non-linear over the region of operation described by a parabolic equation, the output waveform differs from the input signal. Hence this distortion is called non-linear or amplitude distortion. The output waveform now consists of fundamental and higher harmonics. Harmonic distortion is caused by the non-linearity of the characteristic curve of an active device. The second harmonic distortion is determined from the dynamic transfer curve using the three-point method for small signals. The relationship between alternating current ic and the input excitation ib is expressed by ic = k1ib + k2i 2b where k1 and k2 are constants. Let the excitation be sinusoidal and expressed by ib = Ibm cos w t. Therefore, ic = k1 Ibm cos w t + k2I 2bm cos2 w t As 2 cos2 w t = 1 + cos 2w t, the instantaneous total current ic reduces to the form ic = IC + B0 + B1 cos wt + B2 cos wt

Output, current (and voltage) waveform, iO

Output, iO

Unequal positive and negative amplitudes

Dynamic transfer curve

Imax New average value

I1 2

AO

IQ I

–

1 2

IQ

Imin 0

0

Excitation

wt

Xm 2

0

x, input excitation waveform

p

Xm wt

where IC is the d.c. component of current, B0 is the extra d.c. component due to rectification of the signal, B1 the amplitude of the desired signal at the fundamental frequency, w, and B2 is the amplitude of the second harmonic frequency, 2w. Referring to Fig. 12.6, we get For

For

w t = 0, ic = Imax p w t = __, ic = IC 2 w t = p , ic = Imin

Therefore,

IC = IC + B0 – B2, i.e., B0 = B2

For

Imax = IC + B0 + B1 + B2 Imin = IC + B0 – B1 + B2 Imax – Imin B1 = _________ 2 I_____________ max + Imin – IC B2 = 4 The values of Imax, Imin and IC can be obtained directly from the dynamic transfer curves of the transistor and from the intersection of the load line drawn on the characteristic curves. i.e.

The second harmonic distortion D2 in percentage is defined as |B2| D2 = ____ × 100% |B1| Imax + Imin If IC = _________, then B2 and B0 are equal to zero. Hence there is no distortion. 2

The total harmonic distortion is evaluated for large signals by the five-point method. To express the increased curvature of the dynamic transfer curve, ic is represented by a power series of the form ic = K1ib + K2i 2b + K3i 3b + K4i 4b + … If the input wave is sinusoidal, then the output is expressed by ic = IC + B0 + B1 cos w t + B2 cos 2 w t + B3 cos 3 w t + B4 cos 4 wt … For determining the five coefficients B0, B1, B2, B3 and B4, five values of current ib are needed. These are chosen at equal intervals and include values at one-half the maximum positive value of the input, I1/2 and at one-half the maximum negative value of the input, I __1 as shown in Fig. 12.6. –2

Let us assume the input signal, ib = Ibm cos w t For For For For

w t = 0, ic = Imax p w t = __, ic = I __1 3 2 p w t = __, ic = IC 2 2p ___ w t = , ic = I __1 3 – 2

For

w t = p, ic = Imin

The solution of these equations gives 1 B0 = __ Imax + 2I__1 + 2I __1 + Imin – IC 6 – B1

( 1 = __ I 3(

2

max

+ I__1 – I 2

)

2

1 – __ 2

+ Imin

)

1 B2 = __ (Imax – 2IC + Imin) 4 1 B3 = __ Imax + 2I__1 + 2I__1 + Imin – IC 6

(

2

2

)

1 B4 = ___ Imax – 4I__1 + 6IC – 4I __1 + Imin 12 –

(

2

2

)

A measure of the distortion represented by a particular harmonic is the ratio of the amplitude of the harmonic to that of fundamental.

Hence, the individual contributions to harmonic distortion are given by |B3| |B2| |B4| D2 = ____, D3 = ____, D4 = ____ |B1| |B1| |B1| where Ds (s = 1, 2, 3, 4, …) represents the distortion of the sth harmonic. Power output: If the distortion is present, the output power at the fundamental frequency is given by B21 RL P1 = ______ 2 Therefore, the total power output is P = P1 + P2 + P3 + … RL = (B 21 + B 22 + B 23 + º) ___ 2 RL = (1 + D 22 + D 23 + º ) B 21 ___ 2 = (1 + D 22 + D 23 + º) P1 = (1 + D2) P1 where D is the total harmonic distortion (THD), or distortion factor, which is defined as the ratio of the rms value of all the harmonics to the rms value of the fundamental _________________

D = ÷D 22 + D 23 + D 24 + º

For high quality audio amplifiers, the maximum THD is 0.7% at the desired listening level, even though the harmonic distortion of an amplifier increases at higher power levels.

In Fig. 12.4, the load resistor is connected directly in the output circuit. Hence, the quiescent current passes through this resistor resulting in considerable waste of power as it does not contribute to the ac signal at the output, thereby decreasing the efficiency of the amplifier. Further, it is not advisable to pass the d.c. component of current through the output device. For example, the voice coil of a loud speaker. This problem can be solved by using a suitable transformer for coupling the load to the amplifier as shown in Fig. 12.7. Since the load is not directly connected to collector terminal the d.c. collector current does not pass through it. In an ideal transformer, the resistance of the primary winding is zero. Hence d.c. power loss in the load is zero. Hence, the transformer substitutes the d.c. load with an ac load. To transfer a significant amount of power to a practical load such as a loud speaker with a voice coil impedance of 4 to 20 W, it is necessary to use an output matching transformer. Otherwise, the internal device resistance which might be higher than that of the speaker will lead to most of the power generated be lost in the active device. The secondary load RL when reflected into the primary becomes RL¢ = RL/n2, where n = voltage transformation ratio = N2/N1, where N2 = number of secondary turns and N1 = number of primary turns. By taking N2 lesser than N1, n can be made much less than unity and RL can be made to look much bigger than the actual value.

Calculate the effective resistance RL seen looking into the primary of a 10:1 transformer connected to an output load of 16 .

Solution where

RL RL = ___ n2 N2 n = ___ N1 N1 RL = ___ N2

( )

2

RL

= (10)2 16 = 1600

= 1.6 k

Calculate the transformer turns ratio required to match an 8 effective load resistance is 7.2 k .

Solution

N1 ___ N2

( )

2

speaker load to an amplifier so that the

RL 7200 = ___ = _____ = 900 RL 8

N1 ___ = (900)1/2 = 30. N2

Hence N1 : N2 = 30 : 1

A class-A power amplifier has a transformer as the load. If the transformer has a turn ratio of 5 and the secondary load is 100 , determine the maximum ac power output. Given that zero signal collector current is 100 mA.

Solution

Secondary load, RL = 100 W

Transformer turn ratio,

n =5

Zero signal collector current

IC = 100 mA

Load as seen by the primary of the transformer, RL¢ = n2RL = (5)2 × 100 = 2500 W Therefore, maximum a.c. power output 1 1 = __ I C2 R L¢ = __ (100 × 10–3)2 × 2500 = 25 W 2 2

To determine efficiency, the various components of power in an amplifier circuit are considered. Assume that the amplifier is supplying power to a pure resistive load. The average power input from the d.c. supply is VCC × IC. The power absorbed by the output circuit is I 2C RL + ICVC, where IC and VC are the RMS output current and voltage, respectively, and RL is the static load resistance. If PDV is taken as the average power dissipated by the active device, then from the principle of conservation of energy, VCCIC = I 2C RL + ICVC + PDV

(12.3)

Under d.c. conditions from Fig. 12.4, VCC = VC + ICRL. Substituting for VCC. PDV may be written in the form,

PDV = VCIC – VC IC

(12.4)

The above equation gives the amount of power that must be dissipated by the active device. It represents the kinetic energy of the electrons which is converted into heat. For no applied input signal, the a.c. power output is zero, then PDV has its maximum value of VCIC. For an applied input signal, the heating of the device is reduced by the amount of ac power converted by the stage and supplied to the load. Hence, the amplifying device is cooler when delivering power to the load than when there is no such a.c. power transfer. It is a measure of the ability of an active device in converting the d.c. power of the supply into the ac power delivered to the load. Conversion efficiency is also referred to as theoretical efficiency or collector circuit efficiency (for transistor amplifier) and is denoted by h. By definition, the percentage efficiency is signal power delivered to the load h = _______________________________ × 100% d.c. power supplied to output circuit Vm ___ Im ___ __ × __ VmIm ÷2 ÷2 = ________ × 100% = 50 ______ % VCCIC VCCIC

(12.5)

The collector circuit efficiency differs from the overall efficiency because the power taken by the base is not included in the denominator of the above equation. With certain idealisations made in the characteristic curves, it is possible to obtain an approximate expression for the maximum value of efficiency. Though these assumptions introduce errors in the analysis, the results permit a rapid estimate of the numerical value of efficiency and furnishes an upper limit for this figure of merit. It is assumed that the static curves are equally spaced in the region of the load line for equal increments in the excitation (base current).

Referring to Fig. 12.8, the distance from 1 to Q is equal to that from Q to 2. Further, it is assumed that the excitation is such as to give zero minimum current. Figure 12.8 may be used to analyse either a simple series-fed amplifier or a transformer-coupled amplifier. The only difference between these two circuits is that the supply voltage VCC = Vmax in the series-fed case, whereas VCC = quiescent voltage VC in the transformer coupled amplifier. Under these idealised conditions,

ic 1

Imax

Load line

Im Q

IC Im

Vm

Vm

Imin Vmin

VC

2 Vmax

vc

(Vmax – Vmin) Im = IC and Vm = ____________ 2 Hence Eq. (12.5) becomes (Vmax – Vmin) = 25 ____________ % VCC The type of coupling used must now be taken into account for the series-fed load, VCC = Vmax and (Vmax – Vmin) = 25 ____________% Vmax

(12.6)

Equation 12.6 indicates that the upper limit of the conversion efficiency is 25%, and even this low value is approached only when Vmax >> Vmin. If the load is coupled to the amplifier stage through a transformer, then Vmax – Vmin VCC = VC = __________ 2 and Eq. (12.5) reduces to (Vmax – Vmin) = 50 ____________% Vmax + Vmin

(12.7)

Equation 12.7 shows that the upper limit of theoretical efficiency for a transformer coupled power amplifier is 50%, which is twice that of series fed circuit. For a transistor amplifier Vmin occurs near the saturation region and hence, Vmin R is in the frequency range of operation. As _____ > Rs and high output resistance Ro >> RL.

Figure 14.4 shows the equivalent circuit of transresistance amplifier, in which the input circuit is Norton and the output circuit is Thevenin and the output voltage Vo is proportional to the signal current Is, independent of the magnitudes of Rs and RL. Here, if Rs >> Ri, Ii Is and if Ro > RL

Ii

Ri > 1, then Af = 1/b, where b is a feedback ratio. Hence, the gain depends less on the operating potentials and the characteristics of the transistor or vaccum tube. The gain may be made to depend entirely on the feedback network. If the feedback network contains only stable passive elements, the gain of the amplifier using negative feedback is also stable. The stabilization of the d.c. operating point of a transistor amplifier is accomplished by the use of negative feedback as far the d.c. potential is concerned and the operating point is kept constant in the case of change in temperature or a change in the hfe or b of a transistor. Negative feedback is used to improve the performance of an electronic amplifier. Negative feedback always helps to increase the bandwidth, decrease distortion and noise, modify input and output resistances as desired. All the above advantages are obtained at the expense of reduction in voltage gain. The block diagram of a feedback amplifier shown in Fig. 14.5 consists of sampling network, feedback network and mixer network. There are two ways of sampling the signal at the output which is shown in Fig. 14.6(a) and (b). In Fig. 14.6(a), the output voltage is sampled by connecting the feedback network in shunt across the output. This type of connection at the output is referred to as voltage or node sampling. Another feedback connection which samples the output current is shown in Fig. 14.6(b), where the feedback network is connected in series with the output. This type of connection is referred to as current or loop sampling.

The block diagram of feedback network shown in Fig. 14.5 is usually a passive two-port network which may contain resistors, capacitors, and inductors. Most often it is simply a resistive configuration in amplifier circuits. It provides a reduced portion of the output as feedback signal to the input mixer network and it is given as Vf = bVo where b is a feedback factor or feedback ratio which always lies between 0 and 1. Like sampling, there are two ways of mixing the feedback signal with the input signal. The two mixing blocks are shown in Fig. 14.7(a) and (b) at the input side of the amplifier. Figure 14.7(a) shows the series (loop) connection and Fig. 14.7(b) shows the shunt (node) connection at the input.

The symbol A shown in Fig. 14.5 represents the ratio of the output signal to the input signal of the basic amplifier. The transfer ratio V/Vi is the voltage amplification, or the voltage gain, AV. Similarly, the transfer ratio I/Ii is the current amplification, or current gain, AI for the amplifier. The ratio I/Vi of the basic amplifier is the transconductance GM and V/Ii is the transresistance RM. Although GM or RM does not represent an amplification in the usual sense of the word, as the ratio of two signals shows one of these is a current and the other is a voltage signal. But it is convenient to refer to each of the four quantities AV, AI, GM and RM as a transfer gain of the basic amplifier without feedback and to use the common symbol A to represent any one of these quantities. The symbol Af is defined as the ratio of the output signal to the input signal of the amplifier and is called the transfer gain of the amplifier with feedback. Hence Af is used to represent any one of the four ratios Vo/Vs ∫ AVf, Io/Is ∫ AIf, Io/Vs ∫ GMf and Vo/Is ∫ RMf. Figure 14.8 shows the signal flow diagram of a feedback amplifier in which quantity “X” represents either voltage or current signals. When the feedback signal Xf and the input signal Xi are out of phase, then the feedback is called negative feedback. In a negative feedback structure, the signal fedback to the input is out of phase with the input signal of the amplifier.

Source

Xs +

S

Xi = X s – X f

–

Xo = AXi

Amplifier A

Load

Xf = bXo Feedback network b

Based on the type of sampling at the output side and the type of mixing to the input side, feedback amplifiers shown in Fig. 14.9, are classified into four topologies as (1) voltage-series feedback or series shunt feedback (2) current-series feedback or series series feedback (3) current-shunt feedback or shunt series feedback (4) voltage-shunt feedback or shunt shunt feedback In Fig. 14.8, the source resistance Rs is considered to be part of the amplifier and the transfer gain A(AV, GM, AI, RM) includes the effect of the loading of the b network (as well as RL) upon the amplifier. Io = IL + –

Vs – bVo +

+ Vi –

Voltage amplifier

+ Vf –

b

+ RL Vo –

+ –

+ Vi –

Vs

+ bIo = Vf –

(a)

Ii Is

b

Ii RL

Is

Trans resistance amplifier

If = bVo

I f = b lo

RL

(b)

Io = I L Current amplifier

Trans conductance amplifier

b

b

(c)

(d)

+ RL Vo –

The input signal Xs, the output signal Xo, the feedback signal Xf, and the difference signal Xd represents either a voltage or a current signal. These signals and the corresponding ratios A and b are summarized in Table 14.2.

Signal or ratio

Voltage-series feedback

Current-series feedback

Current-shunt feedback

Voltage-shunt feedback

Xo

Voltage

Current

Current

Voltage

Xs, Xf, Xd

Voltage

Voltage

Current

Current

A

AV

GM

AI

RM

b

V ___f Vo

V ___f Io

I __f Io

If ___ Vo

From Fig. 14.8, we know that Xd = Xs – Xf = Xi where Xd represents the difference between the applied input signal Xs and feedback signal Xf and it is called the difference or error or comparison signal. The reverse transmission factor or feedback factor b is defined by Xf b = ___ Xo where the symbol Xo is the output voltage or the output current. The transfer gain without feedback A is defined by Xo A = ___ Xi and the gain with feedback Af is defined by Xo Xo Xo Xo Af = ___ = _______ = ________ = _____________ Xs Xi + Xf Xi + bXo Xi (1 + bXo/Xi) A Af = _______ 1 + bA Here, symbol A represents open-loop gain or the transfer gain of the amplifier without feedback, which includes the loading of the b network, RL, Rs and Af represents the closed-loop gain or gain with feedback. If |Af | < |A|, the feedback is termed as negative, or degenerative and if |Af | > |A|, the feedback is termed positive, or regenerative. In the case of negative feedback, the gain of the basic amplifier with feedback is equal to the open loop gain divided by the factor (1 + bA).

The positive feedback in amplifier circuit results in oscillations as in various types of oscillators circuits. The negative feedback in amplifier circuit results in decreased voltage gain, noise and distortion, but there will be an increase in bandwidth. In addition to these characteristics, input and output impedances get varied according to feedback connections.

Although there is a reduction in overall voltage gain, there are some improvements in using negative feedback in amplifier circuits as listed below: 1. Better stabilized voltage gain 2. Enhanced frequency response 3. Higher input impedance 4. Lower output impedance 5. Reduction in noise 6. Increase in linearity The effects of negative feedback on amplifier characteristics according to the type of feedback connections can be found in Table 14.3. The characteristics of negative feedback are discussed below in detail.

The variation due to aging, temperature, replacement, etc., of the circuit components and transistor or FET characteristics results in unstable amplifier transfer gain. The closed-loop gain of the amplifier with negative feedback is given by A Af = _______ 1 + bA Differentiating the above equation with respect to A, we have

| |

dA (1 + bA) 1 – bA _________ 1 ____f = ______________ = dA (1 + bA)2 (1 + bA)2 dA dAf = _________2 (1 + bA)

Dividing both sides by Af, we get dA (1 + bA) dA dA dA 1 1 ____f = _________ × ___ = _________2 × ________ = ___ × ________ 2 Af A A A (1 + bA) (1 + bA) (1 + bA) f dA dA/A ____f = ________ Af (1 + bA) dAf dA The term ____ represents the fractional change in amplifier voltage gain with feedback and ___ denotes Af A the fractional change in voltage gain without feedback. The term 1/1 + Ab is called sensitivity. Therefore, the sensitivity is defined as the ratio of percentage change in voltage gain with feedback to the percentage change in voltage gain without feedback. dA ____f Af 1 Sensitivity = _____ = ________ (1 + bA) dA ___ A

( ) ( )

For example, if the sensitivity is 0.1, then the percentage change in gain with feedback is one-tenth the percentage change in gain without feedback.

The reciprocal of the term sensitivity is called desensitivity D, or desensitivity D = (1 + bA). Hence, the transfer gain divided by desensitivity is called the closed-loop gain and it can be written as A A Af = _______ = __ 1 + bA D In particular, if |bA| >> 1, then A A 1 Af = _______ ª ___ = __ 1 + bA bA b Hence the gain depends entirely on the feedback network. If the feedback network contains only stable passive elements, the improvement in stability may be high. Increase in stability shows that the gain is made insensitive to changes in transistor parameters. Since A represents either AV, GM, AI or RM, then Af represents the corresponding transfer gains with feedback: either AVf, GMf, AIf or RMf. For voltage-series feedback, AVf ª 1/b shows the voltage gain is stabilized. For current-series feedback, GMf ª 1/b GMf ª 1/b, shows the transconductance gain is desensitized. Similarly, the current gain is desensitized for current-shunt feedback (AIf ª 1/b) and the transresistance gain is stabilized or desensitized for voltage-shunt feedback (RMf ª 1/b).

An amplifier has an open-loop gain of 1000 and a feedback ratio of 0.04. If the open-loop gain changes by 10% due to temperature, find the percentage change in gain of the amplifier with feedback.

dA A = 1000, b = 0.04 and ___ = 10 A We know that the percentage change in gain of the amplifier with feedback is dA dA ________ 1 1 ____f = ___ = 10 × ______________ = 0.25% Af A (1 + Ab) 1 + 1000 × 0.04 Solution

Given

An amplifier has voltage gain with feedback of 100. If the gain without feedback changes by 20% and the gain with feedback should not vary more than 2%, determine the value of open-loop gain A and feedback ratio .

Solution

Given

We know that

dAf dA Af = 100, ____ = 2% = 0.02 and ___ = 20% = 0.2 Af A dAf dA 1 ____ = ___ ________ Af A (1 + Ab)

1 0.02 = 0.2 × _______ 1 + Ab 0.2 Therefore, (1 + Ab) = ____ = 10 0.02 Also, we know that the gain with feedback is A Af = _______ 1 + Ab

i.e., Therefore,

Therefore,

A 100 = ___ 10 A = 1000 1 + Ab = 10; i.e. Ab = 9 9 b = _____ = 0.009 1000

We know that, the gain with feedback for an amplifier is given by A Af = _______ 1 + bA Using the above equation, we can write Amid Af mid = _________ 1 + b Amid Alow Af low = _________ 1 + b Alow and

Ahigh Af high = __________ 1 + b Ahigh

The effect of negative feedback on lower cut-off and upper cut-off frequencies of the amplifier is analyzed here. We know that, the relation between gain at lower cut-off frequency and gain at mid frequency for an amplifier is given as A low 1 ____ = ________ Amid fL 1 – j __ f

( )

Therefore,

Amid Alow = ________ fL 1 – j __ f

( )

Substituting Alow in the Af low equation, we get

Af low

Amid ________ fL 1 – j __ f = _____________ Amid 1 + b ________ fL 1 – j __ f A mid = ________________ f__ L 1–j + Amid b f

( )

( )

( )

Amid = _________________ fL (1 + Amid b) – j __ f

( )

Dividing numerator and denominator by (1 + Amid .b), we have

Af low =

Amid _________ 1 + Amid b __________________

[

fL 1 – j ____________ (1 + Amid b ) f

]

Af mid Amid = ___________________ , since Af mid = _________ 1 + Amid b f L 1 – j ____________ (1 + Amid b) f

[(

)]

A f low 1 ______ = _________ A f mid fLf 1 – j ___ f where the lower cut-off frequency with feedback is given as fL fLf = _________ 1 + Amid b Therefore,

( )

From the above equation, we can say that lower cut-off frequency with feedback is less than the lower cut-off frequency without feedback by factor (1 + Amid b). Therefore, by introducing negative feedback, low frequency response of the amplifier is improved. We know that, the relation between gain at upper cutoff frequency and gain at mid frequency for an amplifier is given as Ahigh 1 _____ = _________ Amid f 1 + j __ fH

( )

Amid Ahigh = _________ f 1 + j __ fH

( )

Substituting Ahigh in the Af high equation, we have Amid _________

Af high

( )

f 1 + j __ fH Amid = _______________ = ________________ A f mid 1 + j __ + Amid b 1 + b _________ fH f 1 + j __ fH

[ ( )]

( )

Dividing numerator and denominator by (1 + Amid b), we get Amid Af high = ___________________ 1 + Amid b ___________________ f 1 + j _____________ (1 + Amid b) fH

[

Therefore,

]

Af mid Amid Af high = ___________________, since Af mid = _________ 1 + Amid b f 1 + j _____________ (1 + Amid b) fH Af high 1 ______ = _________ Af mid f 1 + j ___ fHf

[ ( )

]

where the upper cut-off frequency with feedback is given as fHf = (1 + Amid b) fH From the above equation, we can say that upper cut-off frequency with feedback is greater than upper cut-off frequency without feedback by factor (1 + Amid b). Therefore, by introducing negative feedback, high frequency response of the amplifier is improved. The bandwidth of the amplifier without feedback is given as BW = fH – fL Therefore, the bandwidth of the amplifier with feedback can be written. or fL BWf = fHf – fLf = (1 + Amid b) fH – ___________ (1 + Amid b) or, it can also be written as BWf = BW(1 + Amid b) From the frequency response graph shown in Fig. 14.10, it is very clear that (fHf – fLf) > (fH – fL) and hence the bandwidth of the amplifier with feedback is greater than the bandwidth of the amplifier without feedback. As the voltage gain of a feedback amplifier reduces by the factor (1 + Ab), its bandwidth increases by (1 + Ab). This shows that the product of voltage gain and bandwidth of an amplifier without feedback and with feedback remains the same, i.e. Af × BWf = A × BW.

Gain Without feedback

Amid 0.707 Amid With feedback

Af mid 0.707 Af mid fLf

fL

fH BW BWf

fHf

Frequency

An amplifier has a midband gain of 125 and a bandwidth of 250 kHz. (a) If 4% negative feedback is introduced, find the new bandwidth and gain. (b) If the bandwidth is to restricted to 1 MHz, find the feedback ratio.

Solution

Given

A = 125, BW = 250 kHz and

(a) We know that Gain with feedback,

= 4% = 0.04

BWf = (1 + A ) BW = (1 + 125 × 0.04) × 250 × 103 = 1.5 MHz 125 125 A Af = _______ = _____________ = ____ = 20.83 1 + 125 × 0.04 6 1+A BWf = (1 + A ) BW

(b)

1 × 106 = (1 + 125 Therefore, i.e.

(1 + 125

) × 250 × 103

1 × 106 ) = _________3 = 4 250 × 10 3 = ____ = 0.024 = 2.4% 125

An RC coupled amplifier has a mid-frequency gain of 200 and a frequency response from 100 Hz to 20 kHz. A negative feedback network with = 0.02 is incorporated into the amplifier circuit. Determine the new system performance.

Solution

200 A Af = _______ = _____________ = 40 1 + 200 × 0.02 1+A fL 100 fLf = _______ = _____________ = 20 Hz 1 + 200 × 0.02 1+A fHf = fH × (1 + A ) = 20 × 103 × (1 + 200 × 0.02) = 100 kHz BWf = fHf – fLf = 100 × 103 – 20

100 kHz

Af × BWf = 40 × 100 × 103 = 4000 kHz BW = fH – fL = 20 × 103 – 100

20 kHz

A × BW = 200 × 20 × 103 = 4000 kHz This shows that the gain-bandwidth product of the amplifier with negative feedback is same as that of the gain-bandwidth product of the amplifier without feedback.

Negative feedback reduces the noise or interference in an amplifier, more precisely, by increasing the ratio of signal to noise, which is possible only under certain conditions. Consider the amplifier block shown in Fig. 14.11(a) with input signal Vs noise signal Vn and gain A1. Assume that the noise is

Vn + Vs – – bV + o

Vn + Vs –

A1

A2

+ Vo –

(a)

A1

+ Vo –

b (b)

introduced at the input of the amplifier and the signal-to-noise ratio for this amplifier is given by S/N = Vs/Vn. In Fig. 14.11(b), another amplifier stage with gain A2, that does not suffer from the noise problem, is connected before the main amplifier A1 and by applying negative feedback around the overall cascaded block, the overall gain is maintained constant. The output voltage of the circuit shown in Fig. 14.11(b) can be obtained by superposition and it is given by A1A2 A1 Vo = Vs __________ + Vn __________ 1 + A 1A 2 b 1 + A1A2 b Thus the signal-to-noise ratio at the output becomes A1A2 Vs __________ Vs 1 + A1A2 b ___ S ____________ __ = = A2 N V A n 1 Vn __________ 1 + A1A2 b which is A2 times higher than the original case. Hence, there is an improvement in signal-to-noise ratio (SNR), by connecting a noise free amplifier before the noisy stage, with the application of negative feedback. Improvement in SNR results in reduction of noise.

The transfer characteristics of an amplifier shown in Fig. 14.12 indicates that it is piecewise linear, with the voltage gain changing from 1000 to 100 and then to 0. This nonlinear transfer characteristics of an amplifier generates a large amount of nonlinear distortion at the output. This transfer characteristics can be considerably linearized (i.e. made less nonlinear) by applying negative feedback to the amplifier. As it is known that, negative feedback reduces the dependence of the overall closed-loop gain on the open-loop gain of the basic amplifier. Thus, large changes in openloop gain (1000 to100 in this case) results in much smaller changes in closed-loop gain. The transfer characteristics of the closed-loop amplifier is shown in Fig. 14.12 as curve (b) in which a negative feedback with b = 0.01 is applied to the amplifier whose open-loop voltage transfer characteristic is indicated in Fig. 14.12 as curve (a). Here the slope of the steepest segment is given by 1000 Af1 = ______________ = 90.9 1 + 1000 × 0.01

VO (V ) (a)

4

(b)

3 2 1 –0.08

–0.06

–0.04

–0.02

0.02

0.04

0.06

0.08 Vi

–2 –3 –4

And the slope of the next segment is given by 100 Af2 = _____________ = 50 1 + 100 × 0.01 Thus the order-of-magnitude change in slope with feedback as shown in (a) has been considerably reduced compared to the change in slope without feedback as shown in (b) . This has been achieved at the expense of reduction in voltage gain. Thus, if the overall gain has to be restored, then a preamplifier should be added. This preamplifier should not present a severe nonlinear-distortion problem, since it deals with smaller signals. Consider an amplifier with an open-loop voltage gain (A) and a total harmonic distortion without feedback (D). Then, due to introduction of negative feedback, with the feedback ratio ( ), the distortion (D) is reduced by a factor of 1 + A and the distortion with feedback (Df) is given by D Df = _______ 1+A

An amplifier has a voltage gain of 400, f1 = 50 Hz, f2 = 200 kHz and a distortion of 10% without feedback. Determine the amplifier voltage gain f1f , f2f and Df when a negative feedback is applied with feedback ratio of 0.01.

Solution

Given A = 400, f1 = 50 Hz, f2 = 200 kHz, D = 10% and

We know that voltage gain with feedback 400 A Af = _______ = _____________ = 80 1 + 400 × 0.01 1+A New lower 3 dB frequency, f1 50 f1f = _______ = _____________ = 10 Hz 1 + 400 × 0.01 1+A New upper 3 dB frequency, f2f = (1 + A ) × f2

= 0.01

= (1 + 400 × 0.01) × 200 × 103 = 1 MHz Distortion with feedback, 10 D Df = _______ = ___ = 2% 5 1+A

When the negative feedback signal is fed back to the input in series with the applied voltage, the input resistance is increased. Since the feedback voltage Vf opposes Vs, the input current Ii becomes less and the input resistance with feedback Rif Vs /Ii is greater than the input resistance without feedback Ri. Hence, for voltage series feedback and current-series feedback, Rif = Ri (1 + A) = RiD. When the negative feedback signal is fed back to the input in shunt with the applied signal, the input resistance is decreased. Since Is = Ii + If, then the source current Is is increased and the input resistance with feedback Rif Vi /Is is smaller than the input resistance without feedback Ri. Hence, for voltageshunt feedback and current-shunt feedback, Rif = Ri /(1 + A) = Ri /D. In other words, we can say that, in feedback amplifiers, series mixing at the input tends to increase the input resistance and shunt mixing tends to decrease the input resistance. The voltage-series feedback topology is shown in Fig. 14.13, with the amplifier input and output circuit replaced by its Thevenin’s model. In this circuit AV represents the open-circuit voltage gain taking Rs into account. We have considered Rs to be part of the amplifier throughout the discussion of feedback amplifier. Here, the input impedance with feedback is given by Rif = Vs /Ii. Ii

Io

+

Ro

+

I

+

+

Vs

Vi

–

Ri

AvVi

Vo

RL –

– V – t + Vf = bVo

Rif = Vs /li

Applying KVL to the input side, we get Vs = IiRi + Vf = IiRi + Vo The output voltage is written as AVViRL Vo = ________ = AVVi Ro + RL AVRL Vo where AV = ___ = ________ Vi Ro + RL

–

Rof

R¢of

Substituting the value of Vo in the above KVL equation, we get Vs = IiRi + AVIiRi Vs Rif = ___ = Ri (1 + AV) Ii where AV represents the open-circuit voltage gain without feedback and AV indicates the voltage gain without feedback taking the load RL into account. Therefore, Therefore,

AV = lim AV RL

The current-series feedback topology is shown in Fig. 14.14, with the amplifier input circuit represented by Thevenin’s model and the output circuit by Norton’s equivalent circuit. Here, the input impedance with feedback is given by Rif = Vs /Ii.

Applying KVL to the input side, we get Vs = IiRi + Vf = IiRi + Io The output current is written as GmViRo Io = ________ = GMVi Ro + RL where

Io GmRo GM = __ = ________ Vi Ro + RL

Substituting the value of Io in the above KVL equation, we get Vs = IiRi + GMIiRi Vs Rif = ___ = Ri (1 + GM) Ii where Gm represents the short-circuit transconductance without feedback and GM indicates the transconductance without feedback taking the load RL into account.

Therefore,

Gm = lim GM 0

RL

The current-shunt feedback topology is shown in Fig. 14.15, with the amplifier input and output circuit replaced by its Norton’s model. Ii

Io +

+

I Ai Ii

Is Ri

Vi

Ro

Vo

RL

If = blo –

–

Rif = Vi /ls

Rof

R¢of

Applying KCL to the input side, we get Is = Ii + If = Ii + Io The output current is written as AiIiRo Io = ________ = AIIi Ro + RL Io AiRo where AI = __ = ________ Ii Ro + RL Substituting the value of Io in the above KCL equation, we get Is = Ii + AIIi = (1 + AI) Ii The input resistance with feedback is given as Vi Vi Ri Rif = __ = __________ = _______ Is (1 + AI)Ii 1 + AI where Ai represents the short-circuit current gain without feedback and AI is the current gain without feedback taking the load RL into account. Therefore, Ai = lim AI RL

0

The voltage-shunt feedback topology is shown in Fig. 14.16, with the amplifier input circuit represented by Norton’s model and the output circuit by Thevenin’s equivalent.

Applying KCL to the input side, we get Is = Ii + If = Ii + Vo The output voltage is written as RmIiRo Vo = ________ = RMIi Ro + RL Vo RmRo where RM = ___ = ________ Ii Ro + RL Substituting the value of Vo in the above KCL equation, we get Is = Ii + RMIi = (1 + RM) Ii The input resistance with feedback is given as Vi Vi Ri Rif = __ = __________ = ________ Is (1 + RM)Ii 1 + RM where Rm represents the open circuit transresistance without feedback and RM is the transresistance without feedback taking the load RL into account. Therefore, Rm = lim RM. RL

The negative feedback, which samples the output voltage, irrespective of how it is fed back to the input, decreases the output resistance. For example, if RL increases, Vo increases. The effect of feeding this voltage to the input in the degenerative manner (negative feedback) causes Vo to increase. This increase in Vo is less than that of when there is no feedback and, the output voltage tends to remain constant, as RL changes, which means that Rof > RL), and it can be concluded that this type of current sampling increases the output resistance.

In other words, we can say that, in feedback amplifiers, voltage sampling at the output tends to decrease the output resistance (Rof < Ro) and current sampling tends to increase the output resistance (Rof > Ro). In voltage-series feedback topology shown in Fig. 14.13, the resistance with feedback Rof looking into the output terminals is obtained by disconnecting RL (i.e., RL = ) and by making the external source signal to zero (i.e., set Vs = 0). To find Rof, impress a voltage V across the output terminals and calculate the current I delivered by V. Then, Rof = V/I. In Fig. 14.13, Vo is replaced with V. Applying KVL to the output side, we get

The input voltage is written as

V – AVVi I = ________ Ro Vi = –Vf = – V

(with VS = 0)

Substituting Vi in the above KVL equation, we get V + AVV V(1 + AV) I = _________ = __________ Ro Ro The output resistance with feedback is given as Ro V Rof = __ = ________ I 1 + AV where AV represents the open-circuit voltage gain without taking the load RL into account. The output resistance with feedback Rof including RL as part of the amplifier is given by Rof = Rof || RL Therefore,

Rof RL Ro RL Ro RL 1 Rof = ________ = ________ _________________ = ________________ Rof + RL 1 + AV (Ro/(1 + AV)) + RL Ro + RL + AVRL

Dividing numerator and denominator by (Ro + RL), we get RoRL/(Ro + RL) Rof = ___________________ 1 + AVRL/(Ro + RL) AVRL RoRL where Ro = ________ and AV = ________ Ro + RL R o + RL Ro Rof = ________ 1 + AV where AV indicates the open circuit voltage gain taking the load RL into account. The voltage-shunt feedback topology is shown in Fig. 14.16. For finding Rof, RL is disconnected (i.e., RL = ), the external source signal is made zero (i.e., set Is = 0) and Vo is replaced with V.

Applying KVL to the output side, we get

The input current is written as

V – RmVi I = ________ Ro Ii = – If = – V

(with Is = 0)

Substituting Ii in the above KVL equation, we get V + RmV V (1 + Rm) I = __________ = ___________ Ro Ro The output resistance with feedback is given as Ro V Rof = __ = ________ I 1 + Rm where Rm represents the open-circuit transresistance without taking the load RL into account. The output resistance with feedback R of including RL as part of the amplifier is given by R of = Rof || RL Therefore,

RofRL RoRL RoRL 1 Rof = ________ = ________ _________________ = ________________ Rof + RL 1 + Rm (Ro/(1 + Rm))+ RL Ro + RL + RmRL

Dividing numerator and denominator by (Ro + RL), we get RoRL/(Ro + RL) R of = ___________________ 1 + RmRL/(Ro + RL) R oR L RmRL where Ro = ________ and RM = ________ R o + RL Ro + RL Ro Rof = ________ 1 + RM where RM indicates the open circuit transresistance taking the load RL into account. The current-shunt feedback topology is shown in Fig. 14.15. For finding Rof, RL is disconnected (i.e., RL = ), the external source signal is made zero (i.e., set IS = 0) and Vo is replaced with V. Applying KCL to the output node, we get

The input current is written as

V I = ___ – AiIi Ro Ii = – If = – Io = + I

Substituting Ii in the above KCL equation, we get V I = ___ – AiI Ro

(with Is = 0 and I = –Io)

V I(1 + bAi) = ___ Ro The output resistance with feedback is given as V Rof = __ = Ro (1 + bAi) I where Ai represents the short circuit current gain without taking the load RL into account. The output resistance with feedback R¢of including RL as part of the amplifier is given by R¢of = Rof || RL Therefore,

Rof RL Ro (1 + bAi)RL Ro RL (1 + bAi) R¢of = ________ = _______________ = ______________ Rof + RL Ro (1 + bAi) + RL Ro + RL + bAiRo

Dividing numerator and denominator by (Ro + RL), we get Ro RL (1 + bAi) _____________ Ro + RL 1 + bAi R¢of = ______________ = R¢o _______ bAiRo 1 + bAI 1 + ________ Ro + RL RoRL AiRo where R¢o = ________ and AI = ________. Ro + RL Ro + RL The current-series feedback topology is shown in Fig. 14.14. For finding Rof, RL is disconnected (i.e., RL = •), the external source signal is made zero (i.e., set Vs = 0) and Vo is replaced with V. Applying KCL to the output node, we get V I = ___ – GmVi Ro The input voltage is written as Vi = Vf = – bI0 = bI (with Vs = 0 and I = – Io) Substituting Vi in the above KCL equation, we get V I = ___ – bGmI Ro V I (1 + bGm) = ___ Ro The output resistance with feedback is given as V Rof = __ = Ro (1 + bGm) I where Gm represents the short circuit transconductance without taking the load RL into account. The output resistance with feedback R¢of including RL as part of the amplifier is given by R¢of = Rof || RL

Rof RL Ro (1 + bGm)RL Ro RL (1 + bGm) R¢of = ________ = ________________ = ________________ Rof + RL Ro (1 + bGm) + RL Ro + RL + bGmR0

Therefore,

Dividing numerator and denominator by (Ro + RL), we get RoRL (1 + bGm) ______________ Ro + RL 1 + bGm R¢of = ______________ = R¢o ________ bGmRo 1 + bGM 1 + ________ Ro + RL RoRL GmRo where R¢o = ________ and GM = ________ Ro + RL Ro + RL The characteristics of the four feedback topologies are summarized in Table 14.3.

Characteristic

Current-series

Voltage -series

Voltage-shunt

Current-shunt

Input resistance

Increases

Increases

Decreases

Decreases

Output resistance

Increases

Decreases

Decreases

Increases

Voltage gain

Decreases

Decreases

Decreases

Decreases

Bandwidth

Increases

Increases

Increases

Increases

Nonlinear distortion

Decreases

Decreases

Decreases

Decreases

Noise

Decreases

Decreases

Decreases

Decreases

A voltage-series negative feedback amplifier has a voltage gain without feedback of A = 500, input resistance Ri = 3 k , output resistance Ro = 20 k and feedback ratio = 0.01. Calculate the voltage gain Af, input resistance Rif and output resistance Rof of the amplifier with feedback.

Solution

Given

A = 500, Ri = 3 kW, Ro = 20 kW and b = 0.01

Voltage gain,

500 500 A Af = _______ = _____________ = ____ = 83.33 1 + Ab 1 + 500 × 0.01 6

Input resistance,

Rif = (1 + Ab) Ri = (1 + 500 × 0.01) × 3 × 103 = 18 kW

Output resistance

Ro 20 × 103 Rof = _______ = ______________ = 3.33 kW 1 + Ab (1 + 500 × 0.01)

For analysing the feedback amplifier, it is necessary to go through the following steps.

(i) By shorting the output if feedback signal becomes zero, then it is called “Voltage Sampling”. (ii) By opening the output loop if feedback signal becomes zero, then it is called “Current Sampling”. (i) If the feedback signal is subtracted from the externally applied signal as a voltage in the input loop, it is called “series mixing”. (ii) If the feedback signal is subtracted from the externally applied signal as a current in the loop, it is called “shunt mixing”. Thus by finding the type of sampling network and mixing network, type of feedback amplifier can be determined. For example, if amplifier uses a voltage sampling and series mixing, then it is called a voltage series amplifier. (i) For voltage sampling, the output voltage is made zero by shorting the output. (ii) For current sampling, the output current is made zero by opening the output loop. (i) For series mixing, the input current is made zero by opening the input loop. (ii) For shunt mixing, the input voltage is made zero by shorting the input.

Ensure that the feedback is reduced to zero without altering the loading on the basic amplifier. Optional. Replace each active device by its h-parameter model at low frequency. Find, A, the open loop gain (gain without feedback) of the amplifier. Indicate Xf (feedback voltage or feedback current) and Xo (output voltage or output current) on the circuit and evaluate b = Xf /Xo. From A and b, find D, Af, Rif, Rof and R¢of .

Three examples of the voltage-series topology, viz. (i) BJT common-collector amplifier (emitter follower), (ii) FET common-drain amplifier (source follower), and (iii) voltage-series feedback pair are discussed in this section.

Figure 14.17(a) shows the BJT emitter follower circuit. The feedback signal is the voltage Vf across RE and the sampled signal is Vo across RE. This configuration conforms to voltage series feedback topology, as the sampled signal is taken directly from the output node and the feedback signal is applied in series with the external excitation. Using the analysis steps, approximate expressions for voltage gain, input resistance and output resistance with feedback are obtained. Now the basic amplifier without feedback is drawn. Set Vo = 0, and hence, Vs in series with Rs, appears between base B and emitter E. Set Ii = Ib = 0 (i.e., the input loop is opened), and hence RE appears only in the output loop. Following the above rules, the circuit shown in Fig. 14.17(b) is obtained. Figure 14.17(c) shows the equivalent circuit after replacing the transistor by its low-frequency approximate h-parameter model. In the Fig. 14.17(c), Vf and Vo are equal and hence, b = Vf /Vo = 1. This topology stabilizes the voltage gain. Since Rs is considered as part of the amplifier, then Vi = Vs , and the voltage gain without feedback is given by hfeRE Vo hfeIbRE AV = ___ = _______ = _______ Vi Vs Rs + hie where Vs = Ib (Rs + hie) The desensitivity is given by hfeRE Rs + hie + hfeRE D = 1 + bAV = 1 + _______ = ______________ Rs + hie Rs + hie

Rc

C Rs + VCC +

Rc

–

B +

Ii

E

Vs

Vo

RE

C Rs

–

B (b)

+ –

Ii

E

Vs RE

Rs

+ Vo –

+ –

B

C

I i = Ib Vs

Rc hie

– Vf

hfeIb

(a) E

(c)

RE

– Vo

+ Ro

+ R¢o

Vf where b = ___ = 1. Then, the voltage gain with feedback can be written as Vo hfeRE AV AVf = ___ = ______________ D Rs + hie + hfeRE If hfeRE >> Rs + hie, then AVf ª 1. This unity gain shows that it is an emitter follower circuit. From Fig. 14.17(c), the input resistance without feedback is given by Ri = Rs + hie Hence, for voltage series feedback amplifier, the input resistance with feedback increases due to series mixing at the input and it is given by Rs + hie + hfeRE Rif = RiD = (Rs + hie) × ______________ = Rs + hie + hfeRE (Rs + hie) From Fig. 14.17(c), the output resistance of the amplifier with feedback, without considering the external load resistance (RL = R) is given by Ro • Rof = _______ = __ 1 + bAv • where Ro = • and AV = lim AV = •. This indeterminacy can be resolved by first evaluating R¢of and RL Æ •

then apply the limit RL Æ •. The output resistance of the amplifier with feedback by considering the external load, can be written as R¢o RE (Rs + hie) R¢of = ___ = ______________ D Rs + hie + hfeRE where R¢o = RL = RE Rs + hie Rof = lim R¢of = _______ hfe RL Æ • Hence, the feedback desensitizes voltage gain with respect to changes in hfe and it increases the input resistance and decreases the output resistance for voltage series feedback topology.

In the BJT emitter follower circuit shown in Fig. 14.17(a), the circuit component values are Rs = 600 RC = 4.7 k , RE = 2 k , hfe = 80, hie = 5 k . Calculate AVf , Rif , Rof and R¢of .

hfeRE 80 × 2 × 103 AV = _______ = ____________3 = 28.57 Rs + hie 600 + 5 × 10

Solution The desensitivity is given by

Rs + hie + hfeRE 600 + 5 × 103 + 80 × 2 × 103 D = 1 + bAV = ______________ = _________________________ = 29.57 Rs + hie 600 + 5 × 103

,

Vf where b = ___ = 1. Vo Then, the voltage gain with feedback can be written as AV 28.57 AVf = ___ = _____ = 0.966 ª 1 D 29.57 This unity gain shows that it is an emitter follower circuit. From Fig. 14.17 (c), the input resistance without feedback is given by Ri = Rs + hie = 600 + 5 × 103 = 5.6 kW Hence, for voltage series feedback amplifier, the input resistance with feedback increases due to series mixing at the input and it is given by Rif = RiD = 5.6 × 103 × 29.57 = 165.59 kW From Fig. 14.17(c), the output resistance of the amplifier with feedback, without considering the external load resistance (RL = R) is given by Ro • Rof = _______ = __ 1 + bAv • where Ro = • and AV = lim AV = •. This indeterminacy can be resolved by first evaluating R¢of and RL Æ •

then apply the limit RL Æ •. The output resistance of the amplifier with feedback by considering the external load, can be written as R¢o 2 × 103 R¢of = ___ = _______ = 67.64 W D 29.57 where R¢o= RL = RE. This shows that the output resistance decreases due to voltage sampling at the output. 600 + 5 × 103 Rof = lim R¢of = ____________ = 70 W. 80 RL Æ •

Figure 14.18(a) shows the FET source follower circuit. The feedback signal is the voltage Vf across Rs and the sampled signal is the output voltage Vo across Rs. This configuration corresponds to voltage series feedback topology, as the sampled signal is taken directly from the output node and the feedback signal is applied in series with the external excitation. Using the analysis steps, approximate expressions for voltage gain, input resistance and output resistance with feedback are obtained. Now the basic amplifier without feedback is drawn. Set Vo = 0 and hence Vs appears directly between G and S at the input side. Set Ii = 0 (i.e., the input loop is opened), and hence Rs appears only in output loop.

D –

G Rs

VDD

Vo

+ –

D

Vs +

S

G

(b) S

+ –

Vs Rs

G

+

D –

Vo –

+ –

rd

Vs

(a)

Rs

Vf

gmVs

– Vo

+ S (c)

+ Ro

Ro

Figure 14.18(b) shows the basic amplifier without feedback and Fig. 14.18(c) shows equivalent circuit after replacing the FET by its low-frequency model. In Fig. 14.18(c), Vf and V0 are equal and hence, = Vf /V0 = 1. This topology stabilizes the voltage gain. From Fig. 14.18(c), the voltage gain without feedback is given by gmVgs rdRs V0 Rs AV = ___ = ___________ = ______ Vi (rd + Rs) Vs rd + Rs where

= gm × rd and Vs = Vgs

The desensitivity is given by where

rd + (1 + ) Rs Rs D = 1 + AV = 1 + ______ = _____________ rd + Rs rd + Rs

= 1. Then, the voltage gain with feedback can be written as AV Rs AVf = ___ = _____________ D rd + (1 + ) Rs

The input impedance of FET is infinite, i.e., Ri = , and hence Rif = RiD = . From Fig. 14.18(c), the output resistance of the amplifier with feedback without considering the external load resistance (RL = R) is given by Ro rd Rof = _______ = _____ 1 + Av 1 + where R0 = rd and Av = lim AV = RL

The output resistance of the amplifier with feedback by considering the external load, can be written as R¢o Rs rd rd + R s Rs rd R¢of = ___ = ______ × ____________ = ____________ D Rs + rd rd + (m + 1)Rs rd + (m + 1)Rs where R¢o = R || rd rd Note that the output resistance without load can also be obtained by, Rof = lim R¢of = _____. 1+m RL Æ • For voltage series feedback amplifier shown in Fig. 14.18 (a), Rs = 5 k , rd = 40 k , Rif, Rof and R¢of .

Solution

= 40. Determine AVf,

The voltage gain without feedback is given by Vo mRs 40 × 5 × 103 AV = ___ = ______ = ________________ = 4.44 Vi rd + Rs 40 × 103 + 5 × 103

The desensitivity is given by D = 1 + bAV = 1 + 4.44 = 5.44 where b = 1. Then, the voltage gain with feedback can be written as AV 4.44 AVf = ___ = _____ = 0.816 D 5.44 The input impedance of FET is infinite, i.e. Ri = •, and hence Rif = RiD = •. The output resistance of the amplifier with feedback, without considering the external load resistance (RL = Rs) is given by Ro 40 × 103 Rof = ________ = ________ = 7.35 kW 5.44 1 + bAV where Ro = rd, and AV = lim AV = m RL Æ •

The output resistance of the amplifier with feedback, by considering the external load, can be written as R¢o Rs rd 4.44 × 103 1 5 × 103 × 40 × 103 ____ 1 R¢of = ___ = ______ × __ = ________________ × = _________ = 816.2 W 3 3 D Rs + rd D 5 × 10 + 40 × 10 5.44 5.44 where R¢o = Rs || rd.

Figure 14.19 (a) shows two CE stages connected in cascade with voltage gains AV1 and AV2 respectively, in which the output of the second stage is returned through the feedback network R1 – R2 in opposition to the input signal Vs . As the sampled signal is taken directly from the output node and the feedback signal is applied in series with the external excitation, this is another case of voltage-series feedback topology.

Now the basic amplifier without feedback is drawn. Set Vo = 0 and hence R2 appears in parallel with R1 between the emitter of first transistor and ground. Set Ii = 0 and hence R1 is placed in series with R2 between the collector of second transistor and ground. Figure 14.19(b) shows equivalent circuit without external feedback, including the loading of R2. This topology stabilizes the voltage gain. From Fig. 14.19(b), the feedback factor is given by Vf R1 b = ___ = _______ Vo R1 + R2 The circuit of Fig. 14.19(c) shows a two-stage CE amplifier, with voltage-series feedback, by connecting the second transistor collector to the first transistor emitter through the voltage divider resistors, R1 and R2. For this amplifier, the voltage gain AVf is given approximately by 1/b, and is thus stabilized against changes in temperature and replacement of transistors. The detailed analysis for this topology is discussed below.

B

AV 2

AV 1 I¢ E

+

Vs –

R1

B

+

V1

AV 1

R2

AV 2

E

R2

+

Vo

I (I ¢ + I )

Vs –

R1

+Vo

R2

R1

– (a)

(b) + VCC

C2 Vs

C5

V1

C1

Q1

Vo

C6

Q2

R2 C3

C4

Rif (C)

+

R¢of

Vf – –

Find the voltage gain, feedback factor, input resistance and output resistance of a series-shunt pair type two stage feedback amplifier using transistors with hfe = 90 and hie = 2 k , shown in Fig. 14.20. + VCC

RC 22 kW Vi

R1 220 kW

C2

R¢C 4.7 kW

C5

Vo

C1 R2 22 kW RE

C3

Q2 R4 100 kW

C4

R3 R4 100 W

Solution

Given

7.8 kW

hfe = hfe1 = hfe2 = 99, hie = hie1 = 2 kW, RC = 22 kW R4 = 100 W, R1 = 220 kW, R2 = 22 kW, R¢C = 4.7 kW and R3 = 7.8 kW.

(a) To determine voltage gain: hfe × R01 AV1 = ________ hie where

R01 = RC || (R1 || R2) || hie2 = 22 × 103 || (220 × 103 || 22 × 103) || 2 × 103 = 1.67 kW

Therefore,

99 × 1.67 × 103 AV1 = ______________ = 82.7 2 × 103 hfe × R02 AV2 = ________ hie

where

R02 = R¢C || (R3 + R4) = 4.7 × 103 || (7.8 × 103 + 100) = 2.95 kW

Therefore,

99 × 2.95 × 103 AV2 = ______________ = 146 2 × 103

Overall gain of the cascaded amplifier without feedback AV = AV1 × AV2 = 82.7 × 146 = 13,155

(b) Feedback factor: R4 100 1 b = _______ = ______________ = ___ R3 + R4 7.8 × 103 + 100 79 (c) Input resistance with feedback: Rif = Ri (1 + bAV) where Ri = hie1 = 2 kW Therefore,

(

)

1 Rif = 2 × 103 1 + ___ × 13,155 = 335 kW 79

(d) Output resistance with feedback: R02 Rof = ________ where R02 = R¢C || (R3 + R4) 1 + bAV = 4.7 × 103 || (7.8 × 103 + 100) = 2.95 kW 2.95 × 103 Rof = ________________ = 17.61 W 1 1 + ___ × 13,155 79 (e) Voltage gain with feedback: Therefore,

(

)

AV 13,155 AVf = ________ = ________________ = 78.53 1 + bAV 1 ___ 1+ × 13,155 79

(

)

Two examples of current-series feedback topology: (i) common emitter amplifier with a resistor RE in the emitter terminal, and (ii) FET common-source amplifier with a resistor Rs in the source lead are discussed in this section.

Figure 14.21(a) shows a CE amplifier with emitter resistor RE. The feedback signal is the voltage Vf across RE and the sampled signal is the load current Io. This configuration corresponds to currentseries feedback topology, as the sampled signal is taken from the output loop and the feedback signal is applied in series with the external excitation. To draw the basic amplifier without feedback as shown in Fig. 14.21(b), the input circuit of the amplifier is obtained by opening the output loop. Hence RE appears in the input side. Similarly, the output circuit is obtained by opening the input loop, and this place RE again in the output side. The resultant equivalent circuit is given in Fig.14.21(c) after replacing the transistor by its low frequency h-parameter model. No ground can be indicated in this circuit because by doing so, would again couple the input to the output via RE, i.e., it would reintroduce feedback, but taking the loading of the b network into account. This topology stabilizes the transconductance gain GM. Since the feedback voltage Vf appears across RE in the output circuit, then, from Fig. 14.21(c),

+

C Io Rs VCC Io

+

RL

–

C Rs + –

B

B RL

Ii

Vo

Vs RE

+

RE

E

–

(b)

Ii

E

Vs

Rs

Vo

RE

+ –

–

B

C Io

Ii = Ib Vs

hie RE

(a)

hfeIb RE

E

Ri

+

Vf

+

RL Vo –

– Ro

(c)

Vf –I0RE = ___ = ______ = – RE I0 I0 Since the input signal Vt without feedback is equal to Vs, then the transconductance without feedback is given by – hfe I0 – hfeIb GM = __ = ______ = ____________ Vi Vs Rs + hie + RE where

Vs = Ib (Rs + hie + RE)

The desensitivity is given by

hfeRE Rs + hie + (1 + hfe) RE D = 1 + GM = 1 + ____________ = ___________________ Rs + hie + RE Rs + hie + RE Then, the transconductance with feedback can be written as – hfe GM GMf = ____ = ___________________ D Rs + hie + (1 + hfe) RE Note that if (1 + hfe) RE >> Rs + hie, and since hfe >> 1, then GMf –1/RE 1/ . If RE is a stable resistor, the transconductance gain with feedback is stabilized (desensitized). The load current is given by – hfeVs I0 = GMfVs = ___________________ Rs + hie + (1 + hfe) RE

Vs – ___ RE

Under the conditions, (1 + hfe) RE >> Rs + hie and hfe >> 1, the load current is directly proportional to the input voltage, and this current depends only upon RE and not upon any other circuit or transistor parameter. The voltage gain is given by

– hfeRL I0RL AVf = _____ = GMfRL = ___________________ Vs Rs + hie + (1 + hfe) RE From Fig. 14.21(c), the input resistance without feedback is given by Ri = Rs + hie + RE Hence, for current-series feedback amplifier, the input resistance with feedback increases due to series mixing at the input and it is given by Rif = RiD = Rs + hie + (1 + hfe) RE Since RE is considered to be part of the amplifier, it appears as a part of the input resistance. From Fig. 14.21(c), R0 = • and the output resistance of the amplifier with feedback, without considering the external load resistance is given by Rof = Ro (1 + bGm) = • The output resistance of the amplifier with feedback by considering the external load, can be written as R¢of = RL || Rof = RL Alternatively, it can also be written as 1 + bGm R¢of = R¢o ________ 1 + bGM Since Gm represents the short-circuit transconductance, then Gm = lim GM. However, GM is independent RL Æ 0 of RL and hence Gm = GM and R¢of = R¢o = RL.

For current series feedback amplifier using BJT shown in Fig. 14.21(a), RE = 1.2 k , Rs = 1 k , RL = 2.2 k , hie = 1.1 k , hfe = 50. Determine GMf AVf , Rif , Rof and R¢of .

Solution

The transconductance without feedback is given by – hfe –50 GM = ____________ = ________3 = – 0.015 Rs + hie + RE 3.3 × 10

The desensitivity is given by D = 1 + bGM = 1 + (–1.2 × 103) × (– 0.015) = 19 Vf where b = ___ = –RE I0 Then, the transconductance with feedback can be written as GM – 0.015 GMf = ____ = ______ = – 0.789 × 10 – 3 D 19 The voltage gain is given by I0RL AVf = _____ = GMf RL = –0.789 × 10 –3 × 2.2 × 103 = – 1.73 Vs

The input resistance without feedback is given by Ri = Rs + hie + RE = 3.3 kW For current series feedback amplifier, the input resistance with feedback increases due to series mixing at the input and it is given by Rif = RiD = 3.3 × 103 × 19 = 62.7 kW For BJT, we know that, output resistance, R0 = • The output resistance of the amplifier with feedback, without considering the external load resistance is given by Rof = Ro (1 + bGm) = • The output resistance of the amplifier with feedback by considering the external load, can be written as R¢of = Rof || RL = • || 2.2 × 103 = 2.2 kW Alternatively, it can also be written as 1 + bGm R¢of = R¢o ________ = 2.2 kW 1 + bGM Since Gm represents the short-circuit transconductance, then Gm = lim GM. However, GM is independent RL Æ 0 of RL and hence Gm = GM and R¢of = R¢o = RL.

Figure 14.22(a) shows a CS amplifier with source resistor Rs. Following the same procedure as we did for the BJT amplifier, the basic amplifier without feedback is drawn as shown in Fig. 14.22(b) and then the FET by its low-frequency model is replaced as shown in Fig. 14.22(c). D

+

G

VDD

Io +

Io D +

–

Vs

+ –

–

D +

–

N (a)

G

o

+ Vf R s –

Rs (b)

SV Vs

S Rs

G

RL Vo

+ –

gmVgs

Vs

rd

Rs

Io

RL

Vo

Rs +

S (c)

Vf

– –

Ro

R¢o

Without feedback, Vi = Vs and the transconductance without feedback is given by – gmVgsrd I0 I 0 –m 1 GM = __ = ___ = ___________ × ___ = ___________ Vi Vs rd + RL + Rs Vs rd + RL + Rs where m = gm × rd and Vs = Vgs . The desensitivity is given by

Vf where b = ___ = –Rs . I0

mRs rd + RL + (m + 1) Rs D = 1 + bGM = 1 + ___________ = _________________ rd + RL + Rs rd + RL + Rs

Then, the transconductance with feedback can be written as GM –m GMf = ____ = _________________ D rd + RL + (m + 1) Rs Since Ri = •, then Rif = Ri × D = •. From Fig. 14.22(c), we see that, Ro = rd + Rs . To calculate Rof, we need Gm and it is obtained by, Gm = lim GM. Since b is independent of RL, then RL Æ 0

rd + (m + 1) Rs 1 + bGm = lim D = _____________ rd + Rs RL Æ 0 The output resistance of the amplifier with feedback, without considering the external load resistance is given by rd + (m +1) Rs Rof = Ro (1 + bGm) = (rd + Rs) ____________ = rd + (m + 1) Rs rd + Rs The output resistance of the amplifier with feedback by considering the external load, can be written as RL × (rd + (m + 1) Rs) R¢of = Rof || RL = ___________________ RL + rd + (m + 1) Rs The same result can also be obtained with R¢o = Ro || RL = (rd + Rs) || RL. Thus 1 + bGm R¢of = R¢o ________ D (rd + Rs) RL rd + (m + 1) Rs rd + R L + R s = ___________ × _____________ × _________________ rd + RL + Rs rd + Rs rd + RL + (m + 1) Rs RL × (rd + (m + 1) Rs) = ___________________ rd + RL + (m + 1) Rs which is equivalent to RL in parallel with Rof.

For current series feedback amplifier using FET shown in Fig. 14.22(a), Rs = 1 k , RL = 4.7 k , rd = 40 k , = 50. Determine GMf , AVf , Rif , Rof and R¢of .

The transconductance without feedback is given by –m – 50 GM = ___________ = _________3 = –1.09 × 10 –3 rd + RL + Rs 45.7 × 10 The desensitivity is given by, Solution

D = 1 + bGM = 1 + (–1 × 103) × (– 1.09 × 10 –3) = 2.09 where b = –Rs . Then, the transconductance with feedback can be written as, GM – 1.09 × 10 –3 GMf = ____ = ___________ = 0.52 × 10–3 D 2.09 The voltage gain is given by I0RL AVf = _____ = GMfRL = – 0.52 × 10 –3 × 4.7 × 103 = –2.44 Vs For FET, we know that, input resistance, Ri = •, then Rif = Ri × D = • . The output resistance,

Ro = rd + Rs = 41 kW

To calculate Rof, we need Gm and it is obtained by, Gm = lim GM. Since b is independent of RL, then RL Æ 0

rd + (m + 1) Rs 1 + bGm = lim D = _____________ rd + Rs RL Æ 0 The output resistance of the amplifier with feedback, without considering the external load resistance is given by, rd + (m + 1) Rs Rof = Ro (1 + bGm) = (rd + Rs) _____________ = rd + (m + 1)Rs rd + Rs = 40 × 103 + (1 + 50) × 1 × 103 = 91 kW The output resistance of the amplifier with feedback by considering the external load, can be written as, R¢of = Rof || RL = 91 kW || 4.7 kW = 4.47 kW.

Figure 14.23(a) shows two CE amplifiers in cascade with feedback taken from the second transistor emitter to the first transistor base through the feedback resistor R¢. The output voltage of Q1 (Vo1 ª Vi2) is much larger than Vi1 because of its high voltage gain and it is 180° out of phase with Vi1. Due to emitter-follower action, the voltage across emitter of Q2 (Ve2) is only slightly smaller then Vi2 and these voltages are in phase. Hence Ve2 is larger in magnitude than Vi1 and is 180° out of phase with Vi1. This configuration corresponds to current-shunt topology, as the

Vcc Rc1 I¢s

Rs

Rc2 +

Ii

+ + Vs –

+

Ic Q2

Q1

Vo

Vi2

Vi1

+

R¢

If –

RE

–

Ve2 Rof –

–

R¢if

sampled signal is taken from the output loop and the feedback signal is connected directly to the input node. Using the analysis steps, approximate expressions for current gain, input resistance, output resistance and the voltage gain with feedback are obtained.

Vcc Rc1 Ib1 R¢

+

Is

Rs

Io Ic 1 Q1

Ib 2

Rc 2 +

Ic 2 Q2 Vo

In Fig. 14.23(b), the input circuit – RE R¢ RE If – of the amplifier is obtained by opening the output loop at the emitter of Q2. This places Ri hie Ri 2 R R¢ in series with Re from base to emitter of Q1. The output circuit is obtained by shorting the input node (the base of Q1). This places R¢ in parallel with Re. In the circuit shown in Fig. 14.23(b), as the feedback signal is a current, the source is represented by a Norton’s equivalent circuit with Is = Vs/Rs. From Fig. 14.23(a), neglecting the base current of Q2 compared with the collector current and Ve2 >> Vi1, the feedback current is given by Vi1 – Ve2 Ve2 (I0 – If) RE If = ________ ª ___ = _________ R¢ R¢ R¢ Therefore,

REI0 If = ________ = bI0 R¢ + RE

where b = RE/(R¢ + RE). Since the feedback current is proportional to the output current, this circuit is an example of a current-shunt feedback amplifier. This topology stabilizes the transfer (current) gain. After replacing Q1 and Q2 by its low-frequency approximate h-parameter model, the transfer current gain without feedback is given by –Ic2 –Ic2 Ib2 Ic1 Ib1 AI = ____ = ____ ___ ___ ___ Is Ib2 Ic1 Ib1 Is

–Ic2 Ic1 Ib2 –Rc1 Ib1 R where ____ = – hfe, ___ = + hfe, ___ = ________ and ___ = ______ Ib2 Ib1 Ic1 Rc1 + Ri2 Is R + hie in which

Ri2 = hie + (1 + hfe) (RE || R¢) R ∫ Rs || (R¢ + RE)

The desensitivity is given by D = 1 + bAI where b = RE/(R¢ + RE). The current gain with feedback is given by AI AIf = ___ D The voltage gain with feedback is written as Vo – Ic2Rc2 AIfRc2 Rc2 AVf = ___ = _______ = ______ ª ____ Vs IsRs Rs bRs

1 where AIf = __ which shows the transfer current gain is stabilized. The input impedance without feedback b seen by the current source is given by Ri = R || hie Hence, for current-shunt feedback amplifier, the input resistance with feedback decreases due to shunt mixing at the input, as seen by the current source and it is given by Ri Rif = __ D The output resistance with feedback, without considering the load resistance Rc2, increases due to current sampling and it is given by Rof = Ro (1 + bAi) = •.

(Since hoe = 0, then Ro = •.)

From the AI expression, we find that, it is independent of the load (RL = Rc2). Hence Ai = lim AI = AI. Rc2 Æ 0

From Fig. 14.23(b), R¢o = Ro || Rc2 = Rc2. The output resistance with feedback, by considering the load resistance, can be written as 1 + bAi R¢of = R¢o _______ = R¢o = Rc2. 1 + bAI The circuit of Fig. 14.23(a) has the following parameters: Rc1 = 3 k , Rc2 = 500 1.2 k , hfe = 50, hie = 1.1 k , and hre = hoe = 0. Find AIf, AVf, Rif, Rof and R¢of .

Solution

, RE = 50

Referring to Fig. 14.23(a), the current gain without feedback is given by – Ic2 – Ic2 Ib2 Ic1 Ib1 AI = ____ = ____ ___ ___ ___ Is Ib2 Ic1 Ib1 Is

, R¢ = Rs =

–Ic2 Ic1 where ____ = – hfe = –50 ___ = +hfe = +50 Ib2 Ib1

(

)

50 × 1.2 × 103 Ri 2 = hie + (1 + hfe) (RE || R¢) = 1.14 + (51) _____________ = 3.55 kW 1.25 × 103 Ib2 ________ –Rc1 –3 ___ = = ________ = – 0.458 Ic1 Rc1 + Ri2 3 + 3.55 (1.2 × 103) (1.25 × 103) R ∫ Rs || (R¢ + RE) = ____________________ = 0.612 kW (1.2 + 1.25) × 103 Ib1 ______ 0.61 × 103 R ___ = = _______________3 = 0.358 Is R + hie (0.61 + 1.1) × 10 Substituting all the above current ratio numerical values in AI equation results in AI = (–50) (– 0.458) (50) (0.358) = 410 The feedback factor is given by RE 50 b = ________ = _____ = 0.04 R¢ + RE 1,250 The desensitivity is given by D = 1 + bAI = 1 + (0.040) (410) = 17.4 Current gain and voltage gain with feedback is given by AI 410 AIf = ___ = _____ = 23.6 D 17.4 Vo –Ic2Rc2 AIfRc2 (23.6) (0.5) AVf = ___ = _______ = ______ = __________ = 9.83 Vs IsRs Rs 1.2 The approximate expression for voltage gain results in Rc2 0.5 AVf ª ____ = __________ = 10.4 bRs (0.04) (1.2) which is in error by 6% with the actual value. The input resistance without feedback, seen by the current source is (0.61 × 103) (1.1 × 103) Ri = R || hie = ____________________ = 0.394 kW 1.71 × 103 and the resistance Rif with feedback, seen by the current source is Ri 394 Rif = __ = ____ = 22.6 W D 17.4

If Rc2 is considered as an external load, then Ro is the resistance seen looking into the collector of Q2. Since h0e = 0, then R0 = •. The output resistance with feedback without considering the load, is written as R0f = R0 (1 + bAi) = •. We know that, for current-shunt feedback, AI is independent of the load (RL = Rc2). Hence Ai = lim AI = AI. Since R¢o = Ro || Rc2 = Rc2, then the output resistance with feedback, by Rc2 Æ 0

1 + bAi considering the load, R¢of = R¢o _______ = R¢o = Rc2 = 500 W. 1 + bAI

Figure 14.24(a) shows a common-emitter stage with a resistor R¢ connected from the output to the input. This configuration corresponds to voltage-shunt topology, as the sampled signal is taken directly from the output node and the feedback signal is connected directly to the input node. Using the analysis steps, approximate expressions for transresistance gain, input resistance, output resistance and the voltage gain with feedback are obtained. In Fig. 14.24(a), the output voltage V0 is much greater than the input voltage Vi and is 180° out of phase with Vi. Hence, Vi – V0 V0 If = _______ ª – ___ = bV0 R¢ R¢ If 1 where b = ___ = – ___. Vo R¢ As the feedback current is proportional to the output voltage, this circuit is an example of a voltageshunt feedback amplifier. This topology stabilizes the transresistance gain RM. The basic amplifier without feedback is shown in Fig. 14.24(b) and the input circuit of the amplifier without feedback is obtained by shorting the output node (Vo = 0). This results in R¢ connected between base and emitter of the transistor. The output circuit is found by shorting the input node (Vi = 0), thus connecting R¢ from collector to emitter. The resultant equivalent circuit is given in Fig. 14.24(c) after replacing the transistor by its low frequency hparameter model. As the feedback signal is current, the source is represented by a Norton’s equivalent Vcc

R¢

Rc

Vcc Io

Vo Ib

Rs If

Rc +

Ic

+

Vs

Vi

Is = –

R¢if

Vs Rs

Rs

If

R¢

N

R ¢ Vo

–

R¢of

Ri

R

hie

with Is = Vs/Rs. The feedback signal is the current If flowing in the resistor R¢ which is in the output circuit. From Fig. 14.24(b), If 1 b = ___ = – ___ V0 R¢ The transresistance for the amplifier without feedback is given by – hfeIbR¢c – hfeR¢cR Vo Vo – IcR¢c RM = ___ = ___ = ______ = ________ = ________ Ii Is Is Is R + hie Ib RsR¢ R¢Rc R where __ = ______, R = Rs || R¢ = _______ and R¢c = Rc || R¢ = _______ Is R + hie Rs + R¢ R¢ + Rc The desensitivity is given by hfeR¢cR R¢(R + hie) + hfeR¢cR D = 1 + bRM = 1 + __________ = __________________ R¢(R + hie) R¢(R + hie) The transresistance with feedback is given by – hfeR¢cRR¢ RM RMf = ____ = __________________ D R¢(R + hie) + hfeR¢cR The voltage gain with feedback can be written as RMf Vo Vo AVf = ___ = ____ = ____ Vs IsRs Rs Rhie From Fig. 14.24(c), Ri = R || hie = ______ R + hie Hence, for voltage-shunt feedback amplifier, the input resistance with feedback decreases due to shunt mixing at the input and it is given by Ri R || hie Rif = __ = ______ D D – hfeR¢R Ro Since Ro = R¢, then Rof = ________ where Rm = lim RM = _______ 1 + bRm R + hie RL Æ • Therefore,

hfeR¢R R + hie + hfeR hie + R(1 + hfe) 1 + bRm = 1 + __________ = ____________ = _____________ R¢(R + hie) R + hie R + hie

The output resistance with feedback, without considering the load resistance, decreases due to voltage sampling and it is given by Ro R¢(R + hie) Rof = ________ = _____________ 1 + bRm hie + R(1 + hfe) From Fig. 14.24(c), R¢o = Ro || Rc = R¢ || Rc = R¢c. The output resistance with feedback, by considering the load resistance, can be written as

R¢o R¢o R¢cR¢(R + hie) R¢of = ___ = ________ = __________________ D 1 + bRM R¢(R + hie) + hfeR¢cR Alternatively, it can also be written as R¢of = Rof || RL = Rof || R¢c

The circuit of Fig. 14.24(a) has the following parameters: Rc = 4 k , R¢ = 40 kW, Rs = 10 k , hie = 1.1 k , hfe = 50, and hoe = 0. Find RMf , AVf , Rif and R¢0f .

Solution

Referring to Fig. 14.24, the transresistance gain without feedback is given by Vo – IcR¢c – hfeIbR¢c – hfeR¢cR RM = ___ = ______ = ________ = ________ Is Is Is R + hie

4 × 103 × 40 × 103 where R¢c ∫ Rc || R¢ = ________________ = 3.64 kW 44 × 103 10 × 103 × 40 × 103 R ∫ Rs || R¢ = _________________ = 8 kW 50 × 103 Substituting the above values in RM equation, we get –hfeR¢cR (–50) (3.64) (8) RM = _______ = _____________ = –160 kW 8 + 1.1 R + hie The feedback factor is given by

The desensitivity is given by

1 1 b = – ___ = – ________3 = –0.025 mA/V R¢ 40 × 10 D = 1 + bRM = 1 + 0.025 × 10 –3 × 160 × 103 = 5

The transresistance gain and voltage gain with feedback is given by RM –160 × 103 RMf = ____ = __________ = 32 kW D 5 RMf V0 V0 AVf = ___ = ____ = ____ Vs IsRs Rs – 32 × 103 AVf = _________ = – 3.2 10 × 103 The input resistance without feedback is written as Rhie (8 × 103) (1.1 × 103) Ri = ______ = _________________ = 968 W R + hie 9.1 × 103

The input resistance with feedback is given by Ri 968 Rif = __ = ____ = 193 W D 5 If Rc is an external load resistance, then the output resistance of the amplifier, without considering the load, is given by Ro = R¢ = 40 kW and the transresistance without load resistance is obtained by – hfeR¢R (–50) (40 × 103) (8 × 103) Rm = lim RM = ________ = ______________________ = – 1760 kW, R + hie RL Æ • (8 + 1.1) × 103 The output resistance with feedback is given by Ro 40 × 103 Rof = ________ = ________________ = 890 W 1 + bRm 1 + (0.025) (1760) and

(890) (4000) R¢of = Rof || Rc = ___________ = 728 W 4890

Alternatively, R¢of can also be calculated as R¢o = Rc || R¢ = R¢c = 3.64 kW and

R¢o 3.64 × 103 Rof ¢ = ___ = _________ = 728 W D 5

Find Rm and Rmf using feedback principle for the circuit shown in Fig. 14.25. Assume and hfe = 50 and hie = 1.1 k . Vcc Rc1 3 kW

Rc2 = 500 W

1.2 kW

R3 V3

Solution

R1 = 1.2 kW

Re2 = 50 W

R12 = hie2 + (1 + hfe2) Re2 = 1.1 × 103 + 51 × 50 = 3.65 kW

V0 V0 Ib2 IC1 Ib1 We know that Rm = ___ = ___ ◊ ___ ◊ ___ ◊ ___ Is Ib2 IC1 Ib1 Is

– hfeIb2 (Rc2 || R1) V0 ___ = _______________ = –50 (0.5 × 103 || 1.2 × 103) = –17.6 × 103 Ib2 Ib2 IC1 ___ = hfe = 50 Ib1 Ib2 –Rc1 – 3 × 103 ___ = ________ = __________________ = – 0.451 IC1 Rc1 + Ri2 3 × 103 + 3.65 × 103 Ib1 ____________ (Rs || R1) (1.2 × 103 || 12 × 103) ___ = = _____________________________ = 0.353 IS (Rs || Ri) + Ri1 (1.2 × 103 || 1.2 × 103) + 1.1 × 103 where Ri1 = hie = 1.1 kW Rm = –17.6 × 103 × (–0.451) × 50 × 0.353 = 139.79 kW If 1 1 b = ___ = ___ = ________3 = 0.833 × 10 –3 V0 R1 1.2 × 10 Rm 139.79 × 103 Rmf = ________ = ___________________________ = 1.19 kW 1 + Rmb 1 + 139.79 × 103 × 0.833 × 10 –3 or,

1 1 Rmf ª __ ª ___________ ª 1.2 kW b 0.833 × 10 –3

In the negative feedback amplifier discussed so far, the feedback signal was opposite to the input signal in the mid frequency range of operation. The gain A and phase shift of an amplifier change with frequency. The gain gets decreased at low and high frequencies from the mid frequency value. When the phase shift changes at high frequencies, then some of the feedback signal adds to the input signal. Due to this positive feedback, the amplifier breaks out into oscillation at some high or low frequencies. If an amplifier is designed to have negative feedback in a particular frequency range and oscillates at some high or low frequency. It is no longer useful as an amplifier. Hence, the feedback amplifier should be designed properly in such a way that the circuit is stable at all frequencies and not merely over the frequency range of interest. Otherwise, a transient response may make the stable feedback amplifier unstable and suddenly start oscillating. Also, a feedback amplifier with more than two poles may become unstable and break into oscillation if too much feedback is applied. For the system to be stable, all the poles of the transfer function or the zeros of (1 + Ab) must lie in the left half of the complex frequency plane. Some compensation techniques may be employed to prevent a feedback amplifier from becoming unstable, i.e. oscillator. In order to investigate stability, Nyquist method, a popular technique, is used. Nyquist diagram is used to plot gain and phase shift as a function of frequency, on a complex plane. Since the product Ab is a complex number and function of frequency, points in the complex plane are obtained for the value of Ab corresponding to values of f from – • to + •. The locus of all these points forms a closed curve.

Nyquist criterion for stability states that an amplifier is unstable if the Nyquist curve encloses the –1 + j0 point, and the amplifier is stable if the curve does not enclose this point, which is shown in Fig. 14.26. The Nyquist criterion also represents in the complex plane for positive and negative feedback. As illustrated in Fig. 14.27, |1 + Ab | = 1 represents a circle of unit radius, with the center at –1 + j0 point. For any frequency, if Ab extends outside this circle, the feedback is negative, i.e. |1 + Ab | > 1. If Ab lies within this circle, then |1 + Ab | < 1, and the feedback is positive. If the locus Ab does not enclose the point –1 + j0, i.e. |1 + Ab | > 1, then the amplifier is stable and the feedback is negative for all frequencies. With the help of Nyquist criterion. it is evident that a feedback amplifier is stable if the loop gain, Ab, is less than unity (0 dB) when its phase angle is 180°. Also from the Bode plots, we can determine some margins of stability to indicate how close to instability the system is. Gain Margin (GM) is defined as the value of |Ab | in dB at the frequency at which the phase angle of Ab is 180°. If the gain margin is negative, then the amplifier is stable. If the gain margin is positive, then the amplifier is unstable. Phase Margin (PM) is defined as the angle of 180° minus the magnitude of the angle of Ab at which |Ab | is unity (0 dB). The GM and PM may be evaluated directly from the curves of Fig. 14.28.

Gain Ab (dB)

O

Frequency (f) Phase angle

0 – 90° – 180° – 270°

Gain margin

Frequency (f) Phase margin

Any circuit which is used to generate a periodic voltage without an a.c. input signal is called an oscillator. To generate the periodic voltage, the circuit is supplied with energy from a d.c. source. If the output voltage is a sine wave function of time, the oscillator is called a “Sinusoidal” or “Harmonic” oscillator. Positive feedback and negative resistance oscillators belong to this category. There is another category of oscillators which generate non-sinusoidal waveforms such as square, rectangular, triangular or sawtooth waves. This chapter surveys methods of generating the sinusoidal waveforms.

Oscillators are classified in the following different ways. 1. According to the waveforms generated: (a) Sinusoidal oscillator (b) Relaxation oscillator generates sinusoidal voltages or currents as shown in Fig. 15.1(a). generates voltages or currents which vary abruptly one or more times in a cycle of oscillation as shown in Fig. 15.1(b) to 15.1(d). 2. According to the fundamental mechanisms involved: (a) Negative resistance oscillators (b) Feedback oscillators

V

V t

O

t

O

(a)

(b) V

V

t

O t

O (c)

(d)

uses negative resistance of the amplifying device to neutralize the positive resistance of the oscillator. uses positive feedback in the feedback amplifier to satisfy the Barkhausen criterion. 3. According to the frequency generated: (a) Audio frequency oscillator (AFO): up to 20 kHz (b) Radio frequency oscillator (RFO): 20 kHz to 30 MHz (c) Very high frequency (VHF) oscillator: 30 MHz to 300 MHz (d) Ultra high frequency (UHF) oscillator: 300 MHz to 3 GHz (e) Microwave frequency oscillator: above 3 GHz 4. According to the type of circuit used, sine-wave oscillators may be classified as (a) LC tuned oscillator (b) RC phase shift oscillator.

The oscillator circuit is set into oscillations by a random variation caused in the base current due to noise component or a small variation in the d.c. power supply. The noise components i.e., extremely small random electrical voltages and currents are always present in any conductor, tube or transistor. Even when no external signal is applied, the ever-present noise will cause some small signal at the output of the amplifier. When the amplifier is tuned at a particular frequency fo, the output signal caused by noise signals will be predominantly at fo. If a small fraction ( b ) of the output signal is fed back to the input with proper phase relation, then this feedback signal will be amplified by the amplifier. If the amplifier has a gain of more than 1/b, then the output increases and thereby the feed back signal becomes larger. This process continues and the output goes on increasing. But as the signal level increases, the gain of the amplifier decreases and at a particular value of output, the gain of the amplifier is reduced exactly equal to 1/b. Then the output voltage remains constant at frequency fo, called frequency of oscillation. The essential conditions for maintaining oscillations are: 1. | Ab | = 1, i.e. the magnitude of loop gain must be unity. 2. The total phase shift around the closed loop is zero or 360 degrees. As soon as the oscillations are initiated, they quickly grow in size till the amplitude becomes great enough to introduce nonlinear effects which reduce the amplification of the system. Then the equilibrium is established at an amplitude where the amplification of the loop from base to collector and back to base has dropped to exactly unity. If there was no such amplitude limiting, the amplitude of oscillation would build up to infinity. Thus nonlinear action establishes the equilibrium amplitude in an oscillator. The condition | Ab | = 1 gives a single and precise value of Ab which should be set throughout the operation of the oscillator circuit. But in practice, as transistor characteristics

Vot Basic amplifier

Positive feedback network

Vo Amplitude limiter

Vot

Sustained oscillation

Vo

t

and performance of other circuit components change with time, | A | will become greater or less than unity. Hence, in all practical circuits | A | should be set greater than unity so that the amplitude of oscillation will continue to increase without limit but such an increase in amplitude is limited by the onset of the nonlinearity of operation in the active devices associated with the amplifier as shown in Fig. 15.2. In this circuit, A is larger than unity for positive feedback. This onset of nonlinearity is an essential feature of all practical oscillators.

In the general form of oscillator shown in Fig. 15.3(a), any of the active devices such as Vacuum tube, Transistor, FET and Operational amplifier may be used in the amplifier section. Z1, Z2 and Z3 are reactive elements constituting the feedback tank circuit which determines the frequency of oscillation. Here, Z1 and Z2 serve as an a.c. voltage divider for the output voltage and feedback signal. Therefore, the voltage across Z1 is the feedback signal. The frequency of oscillation of the LC oscillator is

1___ fo = _______ 2p÷LC The inductive or capacitive reactances are represented by Z1, Z2 and Z3. In Fig. 15.3(a), the output terminals are 2 and 3, and input terminals are 1 and 3. Figure 15.3(b) gives the equivalent circuit of Fig. 15.3(a). Since Z1 and the input resistance hie of the transistor are in parallel, their equivalent impedance Z¢ is given by 1 1 1 ___ = ___ + ___ Z¢ Z1 hie From this equation, we get Z1 hie Z¢ = _______ Z1 + hie

(15.1)

Now the load impedance ZL between the output terminals 2 and 3 is the equivalent impedance of Z2 in parallel with the series combination of Z¢ and Z3. Therefore, 1 1 1 ___ = ___ + _______ ZL Z2 Z¢ + Z3 1 1 = ___ + ____________ Z2 _______ Z1 hie + Z3 Z1 + hie Z1 + hie 1 = ___ + ___________________ Z2 Z1 hie + Z1 Z3 + hie Z3 Z1 + hie 1 = ___ + __________________ Z2 hie (Z1 + Z3) + Z1 Z3 hie (Z1 + Z3) + Z1Z3 + Z2 (Z1 + hie) = ______________________________ Z2 [hie (Z1 + Z3) + Z1 Z3]

Therefore,

This is given by

hie(Z1 + Z2 + Z3) + Z1 Z2 + Z1 Z3 = _____________________________ Z2 [hie(Z1 + Z3) + Z1 Z3] Z2 [hie (Z1 + Z3) + Z1 Z3] ZL = _____________________________ hie(Z1 + Z2 + Z3) + Z1 Z2 + Z1 Z3

(15.2)

hfe ZL Ave = – ______ hie

(15.3)

The output voltage between the terminals 3 and 2 in terms of the current I1 is given by

(

Z1 hie V0 = – I1 (Z¢ + Z3) = – I1 _______ + Z3 Z1 + hie

(

hie (Z1 + Z3) + Z1 Z3 = – I1 __________________ Z1 + hie

)

)

(15.4)

The voltage fedback to the input terminals 3 and 1 is given by

(

Z1 hie Vfb = – I1Z¢ = – I1 _______ Z1 + hie Therefore, the feedback ratio b is given by Vfb Z1 hie b = ___ = I1 _______ Vo Z1 + hie

(

)[

)

(15.5)

]

Z1 + hie 1 __________________ ◊ __ hie (Z1 + Z3) + Z1 Z3 I1

Z1 hie b = _________________ hie(Z1 +Z3) + Z1 Z3

(15.6)

For oscillation, we must have Ave b = 1 Substituting the values of Ave and b, we get

( {

)[

– hfe ZL Z1 hie _______ __________________ =1 hie hie(Z1 + Z3) + Z1 Z3

]

hfe Z2 [hie (Z1 + Z3) + Z1 Z3] _____________________________ hie(Z1 + Z2 + Z3) + Z1 Z2 + Z1 Z3

}[

]

Z1hie __________________ = –1 hie (Z1 + Z3) + Z1 Z3

hfe Z2 Z1 _____________________________ =–1 hie(Z1 + Z2 + Z3) + Z1 Z2 + Z1 Z3 hie (Z1 + Z2 + Z3) + Z1Z2 + Z1Z3 = – hfe Z1Z2 hie (Z1 + Z2 + Z3) + Z1Z2 (1 + hfe) + Z1Z3 = 0

(15.7)

This is the general equation for the oscillator.

In the Hartley oscillator shown in Fig. 15.4, Z1 and Z2 are inductors and Z3 is a capacitor. Resistors R1, R2 and RE provide the necessary d.c. bias to the transistor. CE is a bypass capacitor. CC1 and CC2 are coupling capacitors. The feedback network consisting of inductors L1 and L2, and capacitor C determines the frequency of the oscillator. When the supply voltage +VCC is switched ON, a transient current is produced in the tank circuit and consequently, damped harmonic oscillations are set up in the circuit. The oscillatory current in the tank circuit produces a.c. voltages across L1 and L2. As terminal 3 is earthed, it is at zero potential.

If terminal 1 is at a positive potential with respect to 3 at any instant, terminal 2 will be at a negative potential with respect to 3 at the same instant. Thus the phase difference between the terminals 1 and 2 is always 180°. In the CE mode, the transistor provides the phase difference of 180° between the input and output. Therefore, the total phase shift is 360°. Thus, at the frequency determined for the tank circuit, the necessary condition for sustained oscillations is satisfied. If the feedback is adjusted so that the loop gain Ab = 1, the circuit acts as an oscillator. 1___ The frequency of oscillation is fo = _______ , where L = L1 + L2 + 2M, and M is the value of mutual 2p÷LC inductance between coils L1 and L2. The condition for sustained oscillation is L1 + M hfe ≥ _______ L2 + M In the Hartley oscillator, Z1 and Z2 are inductive reactances and Z3 is the capacitive reactance. Suppose M is the mutual inductance between the inductors, then Z1 = jw L1 + jw M Z2 = jw L2 + jw M –j 1 Z3 = ____ = ___ jwC wC Substituting the values in Eq. (15.7) and simplifying, we get

[

]

[

]

1 1 jw hie L1 + L2 + 2M – ____ – w2 (L1 + M) (L2 + M) (1 + hfe) – ____ =0 2 w 2C w C

(15.8)

wo The frequency of oscillation fo = ___ can be determined by equating the imaginary part of Eq. (15.8) to 2p zero. 1 Therefore, L1 + L2 + 2M – _____ =0 w2o C

[

]

Simplifying this equation, we obtain wo 1 ________________ fo = ___ = ____________________ 2p 2p ÷(L1 + L2 + 2M) C

(15.9)

The condition for maintenance of oscillation is obtained by substituting Eq. (15.9) into Eq. (15.8). Now the imaginary part becomes zero and hence,

[

]

1 (L2 + M) (1 + hfe) – _____ =0 w2o C

Substituting Eq. (15.9) into the above equation and simplifying, we get L1 + M hfe = _______ L2 + M

(15.10)

In the Hartley oscillator, L2 = 0.4 mH and C = 0.004 mF. If the frequency of the oscillator is 120 kHz, find the value of L1. Neglect the mutual inductance.

Solution

Therefore,

The frequency of Hartley oscillator is given by 1 __________ fo = _____________ 2p ÷(L1 + L2)C 1 L1 = _______ – L2 4p2fo2 C 1 = ___________________________ – 0.4 × 10 – 3 4p2 (120 × 103)2 × 0.004 × 10 – 6 = 0.44 × 10 – 3 – 0.4 × 10 – 3 = 0.04 mH.

In a transistorized Hartley oscillator, the two inductances are 2 mH and 20 mH while the frequency is to be changed from 950 kHz to 2050 kHz. Calculate the range over which the capacitor is to be varied.

Solution

Given, for a Hartley oscillator L1 = 2 mH L2 = 20 mH f1 = 950 kHz f2 = 2050 kHz

To find the range over which capacitance is to be varied Frequency of oscillation of Hartley Oscillator is 1 _________ fo = _____________ 2p ÷(L1 +L2)C Therefore, When fo = 950 kHz

1 C = _____________ 4p 2(L1 + L2)fo2 1 C = ___________________________________ = 13.89 pF 2 –3 4p [( 2 × 10 + 20 × 10 – 6 ) (950 × 103)2]

When fo = 2050 kHz 1 C = ___________________________________ = 2.98 pF 4p2 [( 2 × 10 – 3 + 20 × 10 – 6 ) (2050 × 103)2] Hence, the range of capacitance is from 2.98 pF to 13.89 pF.

In a Hartley oscillator, the value of the capacitor in the tuned circuit is 500 pF and the two sections of coil have inductances 38 mH and 12 mH. Find the frequency of oscillations and the feedback factor .

Solution

1___ fo = _______ 2p÷LC

where

L = L1 + L2 = 38 × 10 – 6 + 12 × 10 – 6 = 50 × 10 – 6 = 50 mH and C = 500 pF

Therefore,

1 _____________________ = 1 MHz fo = _________________________ –6 2p ÷50 × 10 × 500 × 10 – 12

Feedback factor,

L1 38 × 10 – 6 b = ___ = _________ =3.166 L2 12 × 10 – 6

In the Colpitts oscillator shown in Fig. 15.5, Z1 and Z2 are capacitors and Z3 is an inductor. The resistors R1, R2 and RE provide the necessary d.c. bias to the transistor. CE is a bypass capacitor. CC1 and CC2 are coupling capacitors. The feedback network consisting of capacitors C1 and C2 and an inductor L determines the frequency of the oscillator. When the supply voltage +VCC is switched ON, a transient current is produced in the tank circuit and consequently, damped harmonic oscillations are set up in the circuit. The oscillatory current in the tank circuit produces a.c. voltages across C1 and C2. As terminal 3 is earthed, it will be at zero potential. If terminal 1 is at a positive potential with respect to 3 at any instant, terminal 2 will be at a negative potential with respect to 3 at the same instant. Thus the phase difference between the terminals 1 and 2 is always 180°. In the CE mode, the transistor provides the phase difference of 180° between the input and output. Therefore, the total phase shift is 360°. Thus, at the frequency determined for the tank circuit, the necessary condition for sustained oscillations is satisfied. If the feedback is adjusted so that the loop gain Ab = 1, the circuit acts as an oscillator. The frequency of oscillation is

+ VCC RC

R1

CC2 Vout

CC1

R2

RE

CE

3

1

2

C1

C2 L

___ fo = _______ 2p ÷LC

where

C1 C2 1 ___ 1 ___ 1 __ = + , i.e. C = _______ C C1 C2 C1 + C2

It is widely used in commercial signal generators for frequencies between 1 MHz and 500 MHz. It is also used as a local oscillator in super heterodyne radio receiver.

For this oscillator,

j 1 Z1 = _____ = – ____ jw C1 wC1 j 1 Z2 = _____ = – ____ jw C2 wC2 Z3 = jw L

Substituting these values in Eq. (15.7) and simplifying, we get

(

)

1 + hfe L 1 1 – jhie ____ + ____ – wL + ________ – ___ = 0 (15.11) w C1 wC2 w2 C1C2 C1 wo The frequency of oscillation, fo = ___ , is found by equating the imaginary part of Eq. (15.11) to zero. 2p Thus we get

(

)

_______

÷

wo 1 C1 + C2 fo = ___ = ___ _______ 2p 2p LC1C2

(15.12)

Substituting Eq. (15.12) into Eq. (15.11) and simplifying, we get the condition for maintenance of oscillation as

Substituting Eq. (15.12) into Eq. (15.11) and simplifying, we get the condition for maintenance of oscillation as C2 hfe = ___ (15.13) C1

In the Colpitts oscillator, C1 = 0.2 F and C2 = 0.02 F. If the frequency of the oscillator is 10 kHz, find the value of the inductor. Also find the required gain for oscillation.

Solution

The frequency of the Colpitts oscillator is given by _______

1 C1 +C2 fo = ___ _______ LC1C2 2 C 1 + C2 L = __________ 4 2 f2o C1C2 0.22 × 10 – 6 = ______________________________________ 4 2 × (10 × 103)2 × 0.2 × 10 – 6 × 0.02 × 10 – 6

Therefore,

= 13.932 mH. The voltage gain required to produce oscillation is C1 0.2 × 10 – 6 AV > ___ = __________ = 10 C2 0.02 × 10 – 6

In a Colpitts oscillator, the values of the inductors and capacitors in the tank circuit are L = 40 mH, C1 = 100 pF and C2 = 500 pF. (i) (ii) (iii) (iv) (v)

Find the frequency of oscillations. If the output voltage is 10 V, find the feedback voltage. Find the minimum gains if the frequency is changed by changing L alone. Find the value of C1 for a gain of 10. Also, find the new frequency.

Solution (i) In a Colpitts oscillator, a series combination of C1 and C2 which is in parallel with inductance L and frequency of oscillations is 1 1 _____ = ____________ ________ fo = ________ LC 2 LCeq 1C 2 2 ________ (C1 +C2) Substituting the values, we get 1 ________________________________ = 87.2 kHz fo = ____________________________________ 3 40 × 10 × 100 × 10 – 12 × 500 × 10 –12 2 ________________________________ 100 ×10 –12 + 500 × 10 –12 (ii) The output potential is across C1 and is proportional to XC1, and the feedback voltage is across C2 and proportional to XC2. Therefore,

( ) ( )

1 _____ XC w C1 V C2 ___o = ____1 = _______ = ___ Vf XC C1 1 ____ 2 w C2 Hence,

VoC1 10 × 100 × 10 –12 Vf = _____ = ________________ =2V 500 × 10 – 12 2

(iii) Since the gain depends upon C1 and C2 only and is independent of L, 500 × 10 – 12 Gain = ___________ =5 100 × 10 – 12 C2 (iv) When the gain is equal to 10, ___ = 10 C1 C2 500 × 10 – 12 C1 = ___ = ___________ = 50 pF = 50 pF 10 10 (v) The frequency of oscillation is Therefore,

1 _______________________________ = 118.1 kHz fo = ___________________________________ –3 40 × 10 × 50 10 – 12 × 500 × 10 –12 2p ______________________________ 50 × 10 –12 + 500 × 10 – 12

÷

For the Colpitts oscillator using BJT in self bias having R = 1500 W and the feedback elements C1 = 0.018 mF, C2 = 0.16 mF, find the values of (a) feedback fraction (b) minimum gain to sustain oscillations and (c) emitter resistor RE. Solution (a) (b)

IXc2 C1 0.018 × 10 – 6 Feedback fraction = ____ = ___ = ___________ = 0.11 IXc1 C2 0.16 × 10 – 6 1 1 Av(min) = _______________ = ____ = 9 feedback fraction 0.11

(c)

RC Av = ___ RE

Hence,

RC 1500 RE = ___ = _____ = 167 W Av 9

A Colpitts oscillator is designed with C1 = 100 pF and C2 = 7500 pF. The inductance is variable. Determine the range of inductance values, if the frequency of oscillation is to vary between 950 kHz and 2050 kHz.

Solution

Given

C1 = 100 pF, C2 = 7500 pF and fo = 950 kHz to 2050 kHz C1C2 C = _______ = 98.68 × 10 – 12 F C1 + C2

Here,

To find the value of inductance, L1, for fo = 950 kHz 1____ fo = ________ 2p ÷L1C

We know that

1 ________________ 950 × 103 = ____________________ 2p ÷L1 × 98.68 × 10 – 12 Upon simplifying, we get

L1 = 284 mH

To find the value of inductance, L2, for fo = 2050 kHz 1____ fo = ________ 2p ÷L1C

Here,

1 ________________ 2050 × 103 = ____________________ 2p ÷L2 × 98.68 × 10 – 12 Upon simplifying, we get

L2 = 61 mH

Hence, the range of inductance required is from 61 mH to 284 mH

The frequency of oscillation of a Colpitts oscillator is given by 1 ___________ fo = _______________ C1C2 2p L _______ C1 + C2

÷(

)

where L, C1 and C2 are the frequency determining components. This circuit operates at 450 kHz with C1 = C2. Determine the frequency of oscillation if the value of C2 is doubled?

Solution

Given

fo = 450 kHz with C1 = C2 = C.

We know that the frequency of oscillation of a Colpitts oscillator is ____

÷

1 1 1____ ___ 1 2 ___________ = _____________ _________ = ________ fo = _______________ = ◊ ____ L◊C 2p C◊C L◊C C C ______ ____ 1 2 2p L ◊ 2p 2p L _______ C+C 2 C1 + C2

÷(

) ÷

When the value of C2 is doubled, the frequency of oscillation is 1 1 ____________ = ____________ ________ f o¢ = _______________ 2C◊C C ◊2C 1 2 2p L ◊ _____ 2p L ________ 3C C + 2C

÷(

1

2

) ÷

÷

(1)

_____

÷

3 1_____ ___ 1 = _________ = ◊ ____ 2p 2LC 2LC 2p ◊ ____ 3

÷

(2)

Dividing Eqn. (2) by (1), we get _____

÷ ÷

3 1 ___ __________ __ ◊ ____ f o¢ __________ 2p 2LC LC 3 3 __ ____ = ____ × ___ = __ = 0.866 = 2LC 2 4 fo 1 2 ___ ___ ◊ 2p LC

÷

÷

fo¢ = 0.866 × fo = 0.866 × 450 × 103 = 389 × 103 Hz = 389.7 kHz.

In the Clapp oscillator, Z1 and Z2 are capacitors C1 and C2, and Z3 is the series combination of an inductor L and a capacitor C3 as shown in Fig. 15.6. Addition of C3 improves the frequency stability. The frequency of oscillation is 1___ fo = _______ 2p ÷LC 1 1 1 1 __ = ___ + ___ + ___. C C1 C2 C3

where

+ VCC RC

R1

CC2 Vout

CC1

R2

RE

CE

C1

C2 L C3

Calculate the frequency of oscillation for the Clapp oscillator with C1 = 0.1 F, C2 = 1 F, C3 = 100 pF and L = 470 H.

Solution

Given

C1 = 0.1 mF, C2 = 1 mF, C3 = 100 pF and L = 470 mH 1___ 1 1 1 1 1 fo = _______ where __ = ___ + ___ + ___ ª ___________ C C1 C2 C3 100 × 10 – 12 2p ÷LC

We know that,

1 _________ 1 1 1 __ = + ________ + ___________ C 0.1 × 10 – 6 1 × 10 – 6 100 × 10 – 12 C ª 100 × 10 – 12 F 1___ __________________________ 1 ______________________ = 734.5 kHz fo = _______ = 2p ÷LC 2p ÷470 × 10 – 6 × 100 × 10 – 12

Therefore, Hence,

Figure 15.7 shows a simple LC oscillator called Franklin Oscillator. Here two CE amplifier stages are used which give 360° phase shift from input to output. The values of all the components of the circuit are chosen in such a way that the overall loop gain of these two states, | Ab |, should be greater than 1. 1___ Here the frequency of oscillation is fo = _______ . 2p ÷LC + VCC

RS C

R1

R3

RC

LS

CC Rb

Q2 RL

Q1 R2

R4

RE1

RE2

Rf

The Armstrong oscillator circuit is shown in Fig. 15.8. The Armstrong oscillator uses transformer coupling for the feedback signal. The secondary winding is also called tickler coil, because it feedbacks the signal that sustains the oscillations. The LC tank circuit is driven by the collector. The feedback signal is taken from the small secondary winding and feedback to the base. There is a phase shift of 180° in the transformer. If the loading effect M of the base is ignored, the feedback fraction is b = ___, where M is the mutual inductance and L is the L

+ VCC R1

RF Choke

C

R2

L

R3

inductance of the primary winding. Here the voltage gain must be greater than 1/b for starting the oscillations. + VCC

A tuned collector oscillator circuit is shown in Fig. 15.9. There is a tuned LC circuit in the collector branch, which is connected to +VCC. Resistors R1, R2 and RE establish the proper d.c. operating conditions as in a common emitter amplifier. Capacitor CE is an emitter by-pass capacitor. Resistor RB is used to control the amount of feedback to the value just needed for sustained oscillators and to prevent loading of the collector circuit by the low input resistance of the amplifier. Here, the common emitter amplifier introduces 180° phase shift and the additional 180° phase shift required for sustained oscillation is introduced by inductor LS which is coupled with inductor LP of tank circuit. The frequency of oscillation is 1____ fo = ________ 2p ÷LPC

M RB R1

R2

LP

C

RE

LS

CE

(15.14)

A tuned collector oscillator in a radio receiver has a fixed inductance of 60 H and has to be tunable over the frequency band of 400 to 1200 kHz. Find the range of variable capacitor to be used.

Solution

The resonant frequency is given by 1____ fo = ________ 2p ÷LPC

Therefore,

1 C = ________ 4p 2 fo2 LP

1 C = ________________________ = 2641 pF 2 3 2 4p (400 × 10 ) × 60 × 10 – 6

When fo = 400 kHz,

1 C = __________________________ = 293 pF 4p2 (1200 × 103)2 × 60 × 10 – 6 Hence, the capacitor range required is 293 pF–2641 pF. When fo = 1200 kHz,

A tank circuit contains an inductance of 1 mH. Find out the range of tuning capacitor value if the resonant frequency ranges from 540–1650 kHz.

Solution

Given L = 1 mH

fo ranges from 540 kHz to1650 kHz We know that 1___ fo = _______ 2p ÷LC Therefore, Here,

1 C = ________ 4p2 fo2 L 1 Cmax = ____________________ = 86.86 pF 4p2(540 × 103)2 × 10 – 3 1 Cmin = _____________________ = 9.3 pF 2 4p (1650 × 103)2 × 10 – 3

Hence, the value of capacitance ranges from 9.3 pF to 86.86 pF.

All the oscillators using tuned LC circuits operate well at high frequencies. At low frequencies, as the inductors and capacitors required for the time circuit would be very bulky, RC oscillators are found to be more suitable. Two important RC oscillators VCC are (i) RC Phase shift oscillator and (ii) Wien Bridge oscillator.

In a BJT based RC phase shift oscillator using phase lead RC network shown in Fig. 15.10(a), BJT is used as an active element of the amplifier. Here, the output of the feedback network is loaded appreciably by the relatively low resistance of the transistor. Thus the resistance R of the feedback network is in parallel with the low input resistance hie of the transistor, which reduces the effective value of R in the last section of

R1 R3 I3

RC

C

Ib B1

C

Q R

R2 RE

C

CE

R

the feedback network. The feedback signal is coupled through the feedback resistor R3 in series with the amplifier stage input resistor. In order to make the three sections identical, R3 is chosen as R3 = R – Ri where Ri is the input impedance of the circuit.

B1 Ib

C

C

C I3 R3

hie

hfeIb

RC

R

R

B2 Ri (= hie )

The BJT amplifier provides a phase shift of 180° and the feedback RC network provides the remaining 180° phase shift to obtain a total phase shift of 360° around the loop. Hence, each RC section is designed so as to provide a phase shift of 60° at the desired frequency of oscillation.

The small-signal ac equivalent model is shown in Fig. 15.10(b). Simplifying this circuit by replacing the current source to voltage source, the simplified small-signal ac equivalent model is obtained as shown in Fig. 15.10(c). B1 Ib

hie

C

RC

C

C I3 R3

I1 R

I2

R

I3

B2 R = R3 + hie hie

hfcRcIb

Applying KVL, we get

(

)

1 I1 RC + R + ____ – I2R = – hfeRCIb jwC

( ) 1 –I R + I ( 2R + ____ ) = 0 jwC

1 –I1R + I2 2R + ____ –I3R = 0 jwC 2

3

RC 1 a = _____ and k = ___ R wRC Upon solving the above equations, we get Let

I2 = I3 (2 – ja) and

I1 = I3 (3 – a2 – j4a)

Substituting the above I1 and I2 equations in the first KVL equation, we get loop gain I3/Ib as – hfek I3 _________________________________ __ = Ib 1 + 3k – (5 + k) a2 – j [(6 + 4k) a – a3]

Since the loop gain is a real quantity, we have (6 + 4k) a – a3 = 0 a2 = 6 + 4k The frequency of oscillation fo is given by 1______ fo = _____________ 2pRC ÷6 + 4k At this frequency, the loop gain I3/Ib becomes hfek I3 _____________ __ = 2 Ib 4k + 23k + 29 We know that for sustained oscillation, I3/Ib > 1. 29 Therefore, hfe > 4k + 23 + ___ k

(15.15)

dhfe 29 ____ = 4 – ___2 = 0 dk k

( )

29 k = ___ 4 Therefore,

1/2

= 2.7

29 (hfe)min = 4 (2.7) + 23 + _____ = 44.5 (2.7)

(15.16)

Hence, it is understood that the value of hfe for a transistor must be at least 45 for the circuit to oscillate.

In an RC phase shift oscillator, if R1 = R2 = R3 = 200 k of oscillations.

Solution

and C1 = C2 = C3 = 100 pF. Find the frequency

The frequency of an RC phase shift oscillator is given by 1 __ fo = ________ 2pRC÷6 1 __ = ____________________________ 3 2p × 200 × 10 × 100 × 10 – 12 ÷6 = 3.248 kHz

Determine the frequency of oscillations when a RC phase-shift oscillator has R = 10 k , C = 0.01 mF and RC = 2.2 k . Also, find the minimum current gain needed for this purpose.

Solution

The frequency of oscillations of a RC phase-shift oscillator is

1 _________ fo = ________________ 4RC 2pRC 6 + ____ R Substituting the given values, we get

÷ ( )

1 ________________ = 607 Hz fo = ______________________________________________ 4 × 2.2 × 103 3 –6 2 × 3.142 × 10 × 10 × 0.01 × 10 6 + ____________ 10 × 103

÷

For sustained oscillations, the minimum value of current gain or forward current gain ratio hfe is 4RC R b = hfe = 23 + 29 ___ + ____ RC R 2.2 10 ___ ___ b = 23 + 29 × +4× = 155.6 2.2 10

Therefore,

Find the capacitor C and hfe for the transistor to provide a resonating frequency of 10 kHz of a transistorized phase shift oscillator. Assume R1 = 25 k , R2 = 60 k , RC = 40 k , R = 7.1 k and hie = 1.8 k .

Solution

For a phase shift oscillator, fo = 10 kHz R1 = 25 kW R2 = 60 kW RC = 40 kW R = 7.1 kW hie = 1.8 kW

(i) To find capacitance, C: Frequency of oscillation is

RC 1______ fo = _____________ , where K = ___ R 2pRC÷6 + 4K 1_______ C = ______________ 4RC 2p foR 6 + ____ R

÷

(ii) To find hfe: We know that

1 _______________ = 0.41 nF = ______________________________________ 4 × 40 × 103 3 3 2p × 10 × 10 × 7.1 × 10 6 + ___________ 7.1 × 103 R C R hfe 23 + 29 ____ + 4 ___ R RC

÷

7.1 × 103 40 × 103 23 + 29 ________ + 4 × ________3 3 40 × 10 7.1 × 10 23 + 5.1475 + 22.53 = 50.67 Therefore,

50.67

hfe

The Fig. 15.11(a) shows the RC phase shift oscillator using cascade connection of low pass filters. There are three RC networks with the output of the last section returned to the input. In this oscillator, the required phase shift of 180° is obtained by using RC network. In practice, the resistor R of the last section is adjusted in such a way that the total phase shift produced by the cascade connection of RC network is exactly equal to 180°. The transistor in the amplifier circuit gives a phase shift of another 180°. Hence, the total phase shift around the circuit is 360° i.e., 0°. From Fig. 15.11(b) we can write the following three equations I1 I3 2 – ____ + R + ____ I2 – ____ = 0 jwC jwC jwC

(

)

(15.17)

VCC

RC

R1

CC

R

R

C R2

RE

C

R

C

CE

(a) R

l1

hie

hfelb

RC

Ei

(b)

R

l3

l2 C

C

l4 C

( ) 1 1 – ____ I + ( R + ____ ) I = 0 jwC jwC

1 2 1 – ____ I2 + R+ ____ I3 – ____ I4= 0 jwC jwC jwC 3

(15.18) (15.19)

4

From Eq. (15.19), the value of I3 becomes I3 = I4 (1 + jw RC)

(15.20)

Substituting Eq. (15.20) into Eq. (15.18), we get

(

)

1 2 1 – ____ I2 + (1 + jw RC ) R + ____ I4 – ____ I4 = 0 jwC jwC jwC – I2 + (3jw RC + 1 – w 2R 2C 2) I4 = 0 Therefore, I2 = (3jw RC + 1 – w 2R2C2) I4

(15.21)

By substituting the values of I2 and I3 into Eq. (15.17), we get I1 1 I4 6R – w 2R2C2 + ____ + 5 jw CR2 = ____ = 0 jwC jwC

(

Therefore,

Hence

)

I1 I4 = _______________________________ 2 2 2 1 – 5w R C + jwRC (6 – w2 R2 C2) I1 = __________________ where a = w RC 2 1 – 5a + ja (6 – a2) I4 1 b = __ = _________________ I1 1 – 5a2 + ja (6 – a2)

To determine the frequency of oscillation, the imaginary part is equated to zero, i.e., a (6 – a 2) = 0 __

Therefore

a = ÷6 ;

Hence the frequency of oscillation is

__

w CR = ÷6

__

÷6 fo = ______ 2pRC

By substituting the values of fo into Eq. (15.22), we get 1 __ 1 b = _________________ = ___ 1 – 30 – j ÷6 (6 – 6) 29 or

1 | b | = ___ 29

(15.22)

Thus sustained oscillation is obtained by having the gain of transistor amplifier greater than 29 and frequency of oscillation may be varied by changing the value of impedance element in the phase shifting network. A two stage oscillator uses the phase-shifting network is shown in Fig. 15.12.

From Fig. 15.12, we can write the following three equations using Kirchhoff’s voltage law,

[

]

1 1 I1 R + ___ – I2 ___ = Vo jwc jwc 1 2 I2 ____ + R – I1 ____ = 0 jwC jwC

[

]

I2R = V ¢f Solving the above simultaneous equations, we get the feedback factor (b ) of the network given by Vo 1 b = ___ = _________________ V ¢f 1 3 + j wRC – _____ wRC

(

)

1 Here the oscillator oscillates when woRC – ______ = 0. w0RC i.e.

1 woRC = ______ woRC 1 2p fo RC = ________ 2p fo RC 1 fo = ______ 2pRC

1 Therefore, the frequency of oscillation is fo = ______ 2pRC Vo 1 At frequency of oscillation, |b | = ___ = __. V ¢f 3 As |Ab | should not be less than unity, it is necessary that the amplifier gain |A| must be greater than 3 for the operation of the oscillator.

Find the value of C in RC phase shift oscillator using BJT designed for a frequency of 1 kHz having value of R is 10 k .

Solution Hence,

The frequency of RC phase shift oscillator is given by 1 __ fo = ________ 2pRC ÷6 1 __ _________________________ 1 1 __ = ___________ = 6.5 nF C = _________ = 2p foR ÷6 2p × 1 × 103 × 10 × 103 × ÷6 15.386 × 107

Design a RC phase shift oscillator to generate 5 kHz sine wave with 20V peak to peak amplitude. Draw the designed circuit. Assume hfe = 150.

Solution

Given Let

Refer to Fig. 15.13.

fo = 5 kHz, VCC = 20 V, hfe = 150, RE = 1 kW and CE = 100 mF. VCC VCC VCE = ____ = 10 V and VE = ____ = 2 V 2 10 VE 2 IC ª IE = ___ = _______3 = 2 mA RE 1 × 10 VCC – VCE 20 – 10 RC = _________ = ________ = 5 kW IC 2 × 10 – 3 IC 2 × 10 – 3 IB = ___ = ________ = 13.33 mA 150 hfe

VCC – 0.6 20 – 0.6 RB = _________ = ___________ = 1.45 MW IB 13.33 × 10 – 6 Rin = RB || hie hVT 2 × 26 × 10 – 3 hie = ____ = ____________ = 7.79 kW IB 6.67 × 10 – 6 Ri = 1.45 MW || 7.79 kW ª 7.75 kW R ª Ri = 7.75 kW RC 5 × 103 K = ___ = _________3 = 0.65 R 7.75 × 10 1______ fo = _____________ 2pRC ÷4K + 6 1 ___________ 5 × 103 = _______________________________ 3 2p × 7.75 × 10 × C × ÷4 × 0.65 + 6 1 C = ____________________________ = 1.4 nF 2p × 5 × 103 × 7.75 × 103 × 2.93

Therefore,

Design an oscillator with network in the feedback path of the amplifier shown in Fig. 15.14(a) to generate a sine wave of 2 kHz.

Solution

Refer to Fig. 15.14(b).

Applying KVL to loop-1, we get

( ) j I R ( 1– _____ ) – I R = V wRC

j I1 R – ____ – I2 R = Vi wC

1

Let

2

i

1 a = _____ wRC

Vi I1(1 – ja) – I2 = __ R Applying KVL to loop-2, we get

C

R

+

+

Vi

R I1

–

C

Vo

I2 –

(1)

–I1R + I2(2R – j/wC) = 0 I1 = I2(2 – ja)

(2)

Substituting the Eq.(2) in Eq.(1), we get Vi I2(2 – ja)(1 – ja) – I2 = __ R V i I2(2 – 2ja – ja – a2 – 1) = __ R I2 ______________ 1 __ = Vi R[(1 – a2) – 3ja] Loop gain is given by j I2 × – ___ V wC o b = ___ = _________ Vi Vi –j = _________________ wCR[(1 – a2) – 3ja] – ja = ___________ (1 –a2) – 3ja Dividing both numerator and denominator by ja, we get a2 a b = _______________ = ____________ ja[(1 – a2) – 3ja] 3a + j(1 – a2) At frequency of oscillation, (1 – a2) = 0 Therefore, a = 1 Hence,

1 1 ______ = _______ = 1 wo RC 2pfoRC 1 fo = ______ 2pRC

Equating the imaginary part of b to zero, we get 1 b = __ 3 To obtain sustained oscillations, |Ab| ≥ 1 1 Therefore, |A| ≥ ___ ≥ 3 |b | Given,

fo = 2kHz

Here,

1 fo = ______ 2pRC

Let

C = 0.01 mF 1 2 × 103 = __________ 2pR × 10–8

Therefore, R = 7.957 kW.

As the feedback network shown in Fig. 15.14(a) is a lead lag network which introduces 0° phase shift, the amplifier in the forward path should be a two stage amplifier as shown in Fig. 15.14(c) to obtain overall phase shift of 0°. +VCC R3

R1

RC1

R5

RC2 CC Vo

CC C

R Q1

Q2

0.01 mf R (7.957 kW) Feedback network 0° phase shift

C

R2

Stage 1 180°

R4

R6 RE2

C E2

Stage 2 180°

Total phase shift 360°

In this oscillator, the required phase-shift of 180° in the feedback loop from output to input is obtained by using R and C components instead of tank circuit. Figure 15.15(a) shows the circuit of FET based RC phase-shift oscillator using cascade connection of high-pass filter, i.e. phase lead RC network. The FET amplifier self-biased with a capacitor-bypassed source resistor and a drain resistor. The feedback network consists of three cascaded RC sections. Here, a common source amplifier is followed by three sections of phase lead network and the feedback voltage Vf available at the output of the last RC section of the VDD feedback network is fed to the gate as the input. The phase shift, F, given by each RC section is F = tan

–1

(

RD C

)

1 _____ . If R is made zero, then F will become 90o. But wCR

making R = 0 is impracticable because if R is zero, then the voltage across it will become zero. Therefore, in practice, the value of R is adjusted such that F becomes 60o. If the values of R and C are so chosen that, for the given frequency fo, the phase shift of each RC section is 60°. Thus such a RC ladder network produces a total phase shift of 180o between its input and output voltages for the given frequency. Therefore, at the specific frequency fo, the total phase shift from

C

C

+ R RS

CS

R

R Vf

the base of the transistor around the circuit and back to the base will be exactly 360o or 0o, thereby satisfying Barkhausen condition for oscillation.

rd || RD. Also, it is assumed that the feedback network does not load the R¢D is neglected in Fig. 15.15(c).

Applying KVL, we have

(

)

1 I1 R + ____ – I2R = – gmR¢DVi jwC

( ) 1 – I R + I ( 2R + ____ ) = 0 jwC

1 – I1R + I2 2R + ____ – I3R = 0 jwC 2

3

1 Substituting a = _____ and writing I2 in terms of I3, we get wRC I2 = I3 (2 – ja) Substituting the above expression in the second KVL equation and writing I1 in terms of I3, we get I1 = I3 (3 – 4ja – a2) Substituting the above I1 and I 2 equations in the first KVL equation, we get – gmR D ¢ Vi I3 [(3 – 4ja – a2) (1 – ja)] – I3 (2 – ja) = _________ R – gmR¢DVi I3 = _____________________ R[(1 – 5a2) + j (a3 – 6a)]

– gmR¢DVi Vf = I3R = ___________________ (1 – 5a2) + j (a3 – 6a)

We know that

Therefore, the loop gain Ab can be written as Vf – gmR¢D Ab = ___ = ___________________ 2 Vi (1 – 5a ) + j (a3 – 6a) 1 a = _____ wRC

where

Since the loop gain is a real quantity, we have a3 – 6a = 0 a2 = 6 1 C2 = __ 6 Therefore, the frequency of oscillation becomes w2

2

and the loop gain |Ab| becomes

1 __ fo = ________ 2pRC ÷6

gmR¢D |Ab | = _____ 29 We know that for sustained oscillation, |Ab | > 1 and hence gmR¢D > 29 The voltage gain of the FET amplifier is given by |A| > gmR¢D Therefore,

1 |A| > 29 and b = ___ 29

Hence, the gain of the FET amplifier gate must be at least 29 to sustain oscillations. The RC phase shift oscillator is suitable for audio frequencies only. Its main drawbacks are that the three capacitors or resistors should be changed simultaneously to change the frequency of oscillation and it is difficult to control the amplitude of oscillation without affecting the frequency of oscillation.

Figure 15.16(a) shows the circuit of a Wien-bridge oscillator. The circuit consists of a two-stage RC coupled amplifier which provides a phase shift of 360° or 0°. A balanced bridge is used as the feedback network which has no need to provide any additional phase shift. The feedback network consists of a lead-lag network (R1 – C1 and R2 – C2) and a voltage divider (R3 – R4). The lead-lag network provides a positive feedback to the input of the first stage and the voltage divider provides a negative feedback to the emitter of Q1.

+ VCC Lead-lag network B R1 C1

R5

RC1

C2

R2

RC2

R7

CC

CC

Vout

C

A R3

R4 D

Q1 R6

RB

Q2

V(f )

RE

Vf (s) R

R

1/sC Vo(s)

1/sC

Feedback signal (b)

(a)

If the bridge is balanced,

R1 – jXC1 R3 ____________ ___ = R4 R 2 (– jXC2) __________ R2 – jXC2

[

]

(15.23)

where XC1 and XC2 are the reactances of the capacitors. Simplifying Eq. (15.23) and equating the real and imaginary parts on both sides, we get the frequency of oscillation as, 1 _________ fo = _____________ 2p ÷R1R2C1C2 1 = ______ , if R1 = R2 = R and C1 = C2 = C. 2pRC The ratio of R3 to R4 being greater than 2 will provide a sufficient gain for the circuit to oscillate at the desired frequency. This oscillator is used in commercial audio signal generators.

Assume that

R1 = R2 = R

and C1 = C2 = C

Then the feedback circuit is as shown in Fig. 15.16(b).

Therefore,

1 R|| ___ sC _______________ Vf (s) = Vo(S) 1 1 R + ___ + R|| ___ sC sC R ________ 1 + sRC Vf (s) = Vo(s) ________________ 1 R R + ___ + ________ sC 1 + sRC

sRC = Vo(s) __________________ s2 R2C2 + 3 sRC + 1 Hence, the feedback factor is Vf (s) sRC b = _____ = __________________ Vo(s) s2 R2 C2 + 3 sRC + 1 We know that

Ab = 1

Therefore, the gain of the amplifier, 1 s2 R2 C2 + 3 sRC + 1 A = __ = __________________ sRC b 1 1 Substituting s = jwo, where the frequency of oscillation fo = ______ , i.e. wo = ____ , in the above equation RC 2pRC and simplifying, we get A = 3. Hence the gain of the Wien bridge oscillator using BJT amplifier is at least equal to 3 for oscillations to occur.

In a Wien-bridge oscillator, if the value of R is 100 k , and frequency of oscillation is 10 kHz, find the value of capacitor C.

Solution

Therefore,

The operating frequency of a Wien-bridge oscillator is given by 1 fo = ______ 2pRC 1 C = ______ 2pRfo 1 = _______________________ = 159 pF 2p × 100 × 103 × 10 × 103

Figure 15.17 shows the circuit of a Twin-TOscillator. This circuit consists of Darlington pair (Q1 and Q2) and it is followed by emitter follower (Q3). The Twin-T-network is used as the feedback circuit, which is used as a notch filter. The Darlington pair circuit provides 180° phase –shift and the feedback network also introduces 180° phase-shift. The total phase-shift around the circuit is 360° or 0°. The Twin-T network oscillator yields better frequency stability. The resonant frequency of this oscillator is 1 fo = ______. 2pRC

VCC

R1 C

R3

R4

Q3

C Q1

R

R6

R Q2

2C

R5

R R2 2

R7

By using the Star-Delta conversion formulae, the Twin-T network shown in Fig. 15.18 can be modified as equivalent delta network shown in Fig. 15.19. C

V1

C

R

R 2C R/2

sCR + 1 z1 = z3 = ________ 2sC 2R(sCR + 1) z2 = ____________ (s2 C2 R2 + 1) From Fig. 15.19, we can get the relation expressed by V2 __________________ s2 C2 R2 + 1 ___ = 2 2 2 V1 s C R + 4 sCR + 1 By substituting s = jw, the above equation becomes V2 __________________ 1 – w2 C2 R2 ___ = V1 1 – w2 C2 R2 + jwRC

V2

By setting the real part to be zero, we have 1 fo = ______ 2pRC

Figure 15.20 shows a crystal controlled oscillator circuit. Here, it is a Colpitts crystal oscillator in which the inductor is replaced by the crystal. In this type, a piezo-electric crystal, usually quartz, is used as a resonant circuit replacing an LC circuit. The crystal is a thin slice of piezo-electric material, such as quartz, tourmaline and rochelle salt, which exhibit a property called Piezo-electric effect. The piezo-electric effect represents the characteristics that the crystal reacts to any mechanical stress by producing an electric charge; in the reverse effect, an electric field results in mechanical strain.

+ VCC R1 RC

VO CC

C1

Crystal R2

RE

CE C2

In order to obtain high degree of frequency stability, crystal oscillators are essentially used. Generally, the crystal is a ground wafer of translucent quartz or tourmaline stone placed between two metal plates and housed in a stamp sized package. There are two different methods of cutting this crystal wafer from the crude quartz. The method of cutting determines the natural resonant frequency and temperature coefficient of the crystal. When the wafer is cut in such a way that its flat surfaces are perpendicular to its electrical axis (X-axis), it is called an X-cut crystal as shown in Fig. 15.21(b). When the wafer is cut in such a way that its flat surfaces are perpendicular to its mechanical axis (Y-axis), it is called Y-cut crystal as shown in Fig. 15.21(c).

If an alternating voltage is applied, then the crystal wafer is set into vibration. The frequency of vibration equal to the resonant frequency of the crystal is determined by its structural characteristics. If the

frequency of the applied a.c. voltage is equal to the natural resonant frequency of the crystal, then the maximum amplitude of vibration will be obtained. In general, the frequency of vibration is inversely proportional to the thickness of the crystal. __

÷

P Y The frequency of vibration is f = __ __ 2l r where Y is the Young modulus, r is the density of the material and P = 1, 2, 3, . . . The crystal is suitably cut and polished to vibrate at a certain frequency and mounted between two metal plates as shown in Fig. 15.22(a). The equivalent circuit of the crystal is shown in Fig. 15.22(b). The ratio of Cp to Cs may be several hundred or more so that series resonance frequency is very close to parallel resonant frequency. The resonant frequency is inversely proportional to the thickness of the crystal. Resonant frequencies from 0.5 MHz to 30 MHz can be obtained. The reactance function shown in Fig. 15.22(c) is w2 – w2s 1 jX = _____ ◊ _______ jwCp w2 – w2p 1 neglecting R. Here w2s = ____ is the series resonant frequency and LCs 1 w2p = ___________ 1 1 L ___ + ___ Cs Cp

(

)

is the parallel resonant frequency. Since Cp >> Cs, wp @ ws. For ws < w < wp, the reactance is inductive and for w out of the above range, it is capacitive.

R

L Cp

Reactance (X )

XL

Frequency (f ) fs

X tal Cs

(a) XC

(b)

(c)

fp

For crystal Hartley oscillator, the capacitors C1 and C2 shown in Fig. 15.20 are replaced with inductors L1 and L2 respectively, so that the reactance of the crystal is capacitive. Hence, its oscillation frequency 1 __________ . is _____________ 2p ÷(L1 + L2)C The advantage of the crystal is its very high Q as a resonant circuit, which results in good frequency stability for the oscillator. However, since the resonant frequencies of the crystals are temperature dependent, it is necessary to enclose the crystal in a temperature controlled oven to achieve the frequency stability of the order of 1 part in 1010.

A crystal has the following parameters: L = 0.5 H, Cs = 0.06 pF, Cp = 1pF and R = 5 k . Find the series and parallel resonant frequencies and Q-factor of the crystal.

Solution

(a) The series resonant frequency of the crystal is 1____ ___________________ 1 ________________ = 918.9 kHz. fs = _______ = 2p÷LCs 2p÷0.5 × 0.06 × 10 – 12

wsL 2pfsL Q factor of the crystal at fs= ____ = _____ R R 2p × 918.9 × 103 × 0.5 = ____________________ = 577 5 × 103 (b) The parallel resonant frequency of the crystal is _______

÷

1 Cs + Cp fp = ___ _______ 2p LCs Cp ___________________________

1 = ___ 2p

÷

1.06 × 10 – 12 __________________________ = 946 kHz 0.5 × 0.06 × 10 – 12 × 1 × 10 – 12

wpL 2pfpL Q factor of the crystal at fp = ____ = _____ R R 2p × 946 × 103 × 0.5 = __________________ = 594 5 × 103 A certain X-cut quartz crystal resonates at 500 kHz. It has an equivalent inductance of 4.2 H and an equivalent capacitance of 0.03 pF. If its equivalent resistance is 500 , calculate its Q-factor.

Solution

wL 2pfL 2p × 500 × 103 × 4.2 Q = ___ = _____ = __________________ = 26,376 R R 500

The Miller crystal controlled oscillator circuit is shown in Fig. 15.23. The crystal has two resonant frequencies. In between the series-resonant frequency and parallel resonant frequency, the reactance of the crystal becomes inductive and hence the crystal can be used as an inductor. One of the inductors in Hartley Oscillator is replaced by the crystal, which acts as an inductor when the frequency is greater than the series resonant frequency. The inter electrode capacitance of the transistor acts as a capacitor to generate oscillations in the circuit. + VCC

C

L

R1

R2 XTAL

RE

The transistor Pierce Crystal oscillator is shown in Fig. 15.24. Here the crystal is connected as a series element in the feedback path from the collector to the base. The resistor R1, R2 and RE provide the necessary d.c. bias to the transistor and CE is an emitter by pass capacitor. The radio frequency (RF) choke coil provides d.c. bias while decoupling any a.c. signal on the power lines from affecting the output signal. The coupling capacitor C blocks any d.c. between collector and base, and has negligible impedance at the operating frequency of the oscillator. The frequency of oscillation set by the series-resonant frequency of the crystal is given by, 1____ fo = _______ 2p÷LCs

C

+ VCC XTAL R1

R2

RF Choke c

RE

Vout

CE

The main advantage of Pierce crystal oscillator is its simplicity.

The Wien-bridge RC oscillator is used in the range of 5 Hz to about 1 MHz, i.e., in low frequency applications like audio generators. It is not suitable for high frequency applications above 1 MHz since

the phase shift through the amplifier and the phase shift of the lead-lag circuit jointly cause resonance to occur at different frequencies other than the specified resonant frequency. Alternatively LC oscillators can be used for frequencies from 1 MHz to 500 MHz and they are called Radio Frequency (RF) oscillators. With an amplifier and LC feedback tank circuit, a signal can be fedback with the correct amplitude and phase for the sustained oscillations. At higher frequencies, the stray capacitances and lead inductances also determine oscillation frequency in RC and LC oscillators. The quartz crystal oscillators are used whenever accuracy and stability of oscillation are required. Since the crystal acts as a large inductor in series with a small capacitor, the resonance frequency is not affected by the stray capacitances and transistor.

The frequency stability of an oscillator is a measure of its ability to maintain the required frequency as precisely as possible over as long a time interval as possible. The accuracy of frequency calibration required may be anywhere between 10–2 and 10–10. The main drawback in transistor oscillators is that the frequency of oscillation is not stable during a long time operation. The following are the factors which contribute to the change in frequency. 1. Due to change in temperature, the values of the frequency-determining components, viz., resistor, inductor and capacitor change. 2. Due to variation in the power supply, unstable transistor parameters, change in climatic conditions and aging. 3. The effective resistance of the tank circuit is changed when the load is connected. 4. Due to variation in biasing conditions and loading conditions. The variation of frequency with temperature is given by Dw /wo Sw ,T = ______ ppmc (parts per million per °C) DT /To where wo, To are the desired frequency of oscillation and the operating temperature respectively. In the absence of automatic temperature control, the effect of temperature on the resonant LC circuit can be reduced by selecting an inductance L with positive temperature coefficient and a capacitance C with negative temperature coefficient. The loading effect may be minimised if the oscillator is coupled to the load loosely or by a circuit with high input resistance and low output resistance properties. The frequency stability is defined as dq Sw = ___ dw where dq is the phase shift introduced for a small frequency change in nominal frequency fo. The cirdq cuit giving the larger value of ___ has the more stable oscillator frequency. If the Q is infinite (an ideal dw dq inductor with zero series resistance), this phase change in phase is abrupt, ___ Æ • because the phase dw changes abruptly from – 90° to + 90°. For tuned oscillators, Sw is directly proportional to the Q of a tuned circuit. A frequency stability of one part in 104 can be achieved with LC circuits. For LC oscillators, a tuned circuit must be lightly loaded to preserve high Q value. As piezo-electric crystals have high Q values of the order of 105, they can be used as parallel resonant circuits in oscillators to get very high frequency stability of 1 ppm (part per million).

All oscillators do not require positive feedback for their operation. If the positive resistance of the LC tank circuit is cancelled by introducing the right amount of negative resistance across the tank circuit, then the steady oscillation can be maintained. There are several devices such as dynatron, transitron, UJT and tunnel diode that exhibit a region of negative resistance within the V–I characteristics as shown in Fig. 15.25. Such devices operated in the negative resistance region are placed across a high Q parallel LC circuit as the frequency determining section. For oscillation to occur, the negative resistance should be numerically less than the dynamic resistance of the tuned circuit. Figure 15.26 shows the tunnel diode oscillator. If the parallel tank circuit with a resistance R, a capacitance C and an inductance L is connected across the tunnel diode whose negative resistance is – Rn, the net resistance Req represents R and – Rn in parallel and is given by Ls

– Rn ◊ R Req = _______ R – Rn If R > Rn, then Req is negative and oscillations can build-up. The oscillation amplitude then grows until it occupies a voltage range greater than the extent of the negative resistance region of the characteristics. When the operating point enters the region of positive resistance, the amplitude of oscillation is limited. To obtain the maximum output, the quiescent point must be accurately located at the center of the negative resistance region. The frequency of oscillation is given by

Tunnel diode

1___ fo = _______ 2p ÷LC A tunnel diode has a characteristic with a negative resistance region between voltages of approximately 0.1V and 0.3 V and can be used as an oscillator at frequencies up to 100 GHz.

The circuit diagrams of Hartley Oscillator, Colpitts Oscillator, Wien Bridge Oscillator, Miller Crystal Oscillator and Pierce Crystal Oscillator using FET are given below.

+VDD Cgd

L

+VDD

C Vo

Xtal C

Rg

Crystal

Rs

RFC

Cs

RG

RFC

A wide variety of different waveforms are used in the field of electronics. But the primary constituents of these are the sine wave, rectangular pulse and sawtooth or ramp. The rectangular pulse is the fundamental form of signal in computers and digital equipments and is also extensively used in television, radar and other equipment. This chapter surveys waveform shaping circuits, diode clippers, slicers and clampers, and methods of generating pulse waveforms.

The waveform shaping circuits like differentiating and integrating circuits are used in multivibrators as triggering and synchronizing pulse generators. The leading and trailing edges of the trigger pulses are of utmost importance and the horizontal part of the pulse is not important in multivibrator applications. Hence, the triggering pulses to the multivibrators are to be reshaped using (i) high-pass RC Circuit (Differentiating circuit) and (ii) low-pass RC Circuit (Integrating circuit). A simple high-pass RC circuit, that is, differentiating circuit is shown in Fig. 16.1(a). It consists of a series capacitor and a shunt resistor. Since the 1 reactance of a capacitor is, XC = _____ , XC decreases with increasing frequency ( f ). Therefore, at very 2pfC high frequencies, the capacitor acts as a short circuit and all the higher frequency components appear at the output with less attenuation than the lower frequency components. Hence this circuit is called high-pass filter. If the time constant is very small in comparison with the time needed for the input signal to make an appreciable change, the circuit is called a differentiator. Here, the voltage drop across R will be

very small when compared to the voltage drop across C. Hence the total input voltage vi(t) appears across C. The current flowing through the capacitor is given by dvC (t) dvi(t) i(t) = C ______ = C _____ dt dt Hence the output voltage which is drop across R is written as vo(t) = i(t) R dvi(t) vo(t) = RC _____ dt Hence, the output voltage is proportional to the derivative of the input voltage. In general, the time constant of the differentiating circuit shall be small compared to the period of the input signal. A 1 1 = 0.707 ÷2

A = |G (f )|

0

C +

f1

+

90° Vi(t )

i(t )

R

Vo(t )

–

f

f f = G (f )

45°

– 0 f1 f (b) Frequency response of the high-pass filter

(a) RC high-pass filter

By applying KVL in the circuit shown in Fig. 16.1(a), we get vi (t) = vC (t) + vR(t) t

1 vi (t) = __ Ú i(t) dt + i(t)R Co Applying Laplace transform on both sides, we get I(s) Vi (s) = ____ + RI(s) = I(s) [R + 1/sC] sC Therefore,

Vi (s) I(s) = __________ (R + 1/sC)

Since vo(t) = i(t) R, we have Vi (s)R Vo(s) = I(s) R = ________ R + 1/sC

Hence, the transfer function is Vo(s) sRC 1 G(s) = _____ = _________ = ________ Vi (s) 1 + 1/sRC 1 + sRC The frequency function G( f ) can be obtained from the transfer function G(s) by substituting s = j2 f. j2 RCf 1 G( f ) = __________ = _____________ 1 + j2 RCf 1 – j(1/2 RCf ) Therefore,

1 G( f ) = ________ 1 – j(f1/f)

where f1 is the lower cut-off frequency given by 1 f1 = ______ 2 RC The frequency function G(f ) can also be expressed as G( f ) = |G( f )|G( f ) = A| where A is the magnitude and is

and

the phase angle of the frequency function G( f ). Therefore, 1 _________ A = __________ 1 + (f1/f)2 = tan–1 (f1/f)

The frequency response of the RC high-pass filter is shown in Fig. 16.1(b) where the lower cut-off 1__ at f1. The frequency f1 is indicated. Plots of A and with variation of frequency are seen. Here A = ___ 2 gain of this high-pass filter is close to unity in the pass band and this gain drops to zero in the stop band. The reactance of the capacitor and the resistance of the circuit are equal at lower cut-off frequency f1.

The transient response of a circuit is studied with the help of the differential equation representing that circuit. t

or Hence,

1 vi (t) = __ i(t) dt + i(t)R Co vo(t) = i(t)R vo(t) i(t) = ____ R t 1 vi (t) = ____ vo(t) dt + vo(t) RC o

where RC is the time constant of the circuit. Differentiating the above equation on both sides and after rearranging them, we have vo(t) _____ dvi(t) dvo(t) _____ ____ = + RC dt dt

This equation is a first-order linear non-homogeneous equation. Solving the above differential equation using standard mathematical techniques, we get vo(t) = A + Be – t/RC The values of the two arbitrary constants A and B are determined from the knowledge of two boundary conditions of the function vo(t). Since vo(t) is a function associated with an electrical circuit, its initial value and final value can be obtained from the behaviour of the circuit. Let the initial value be vo(0) and the final value be vo( ). Substituting vo(0) at t = 0, we have vo(0) = A + B. t = , vo( ) = A + 0 = A

Then, at

A = vo( ) and B = vo(0) – vo( )

Therefore,

vo(t) = vo( ) + [vo(0) – vo( )] e – t/RC

Hence,

An RC high-pass filter is shown in Fig. 16.2(a). A step waveform shown in Fig. 16.2(b) is applied to the input of the RC high-pass filter and it is mathematically defined as vi(t) =

0 for t < 0 V for t 0

The generalized transient expression for the circuit is vo(t) = vo( ) + [vo(0) – vo( )] e – t/RC The response of the circuit shown in Fig. 16.2(a) to a step waveform can be obtained by finding vo(t) at t = 0 and t = . Initially, at t = 0, when the input goes through a sudden change, the capacitor C behaves as a shortcircuit. Consequently, the entire input voltage V appears at the output as vo(0) = V. When the circuit reaches steady-state at t = , the capacitor C is fully charged and behave as an open-circuit. Consequently, no current flows through resistor R and the output is zero, that is, vo( ) = 0. vi (t ) V

C +

+ (b) Step waveform

v i (t )

i(t )

R

vo(t )

vo(t )

–

V

– (a) RC high-pass filter

vo(t ) = Ve

t

–t/RC

t (c) Output waveform of the RC high-pass filter

The expression for vo(t) can be found by substituting the initial condition vo(0) and final condition vo( ) in the above transient expression and it is given by vo(t) = 0 + (V – 0) e – t/RC vo(t) = Ve – t/RC where RC is the time constant of the circuit. The output waveform for the step input to an RC high-pass filter is an exponentially falling waveform as shown in Figure 16.2(c). This response reaches almost zero after a time t greater than five times RC. Figure 16.3 shows the response V0 which exhibits a tilt when a step Vi is applied to a highpass RC circuit. Since the capacitor is initially uncharged, the output at t = 0+ will be V. Hence, the output becomes V0 = Ve

t – ____ RC

At t = t1, if the time constant RC is very large, i.e. RC >> t1, there is only a slight tilt to the output pulse. At t = t1, V0 = V . Therefore, t1 V = V 1 – _____ R1C1

(

)

% Tilt or sag in time t1 is given by t1 V–V P = ______ × 100 = _____ × 100% V R1C1 It is found that the same expression is valid for the tilt of each half cycle of a symmetrical square wave of peak to peak value V and period T provided t1 = T/2. If f = 1/T is the frequency of the square wave and by using the lower 3 dB frequency, we have 1 f1 = _______ 2 R1C1 Hence, P is expressed as f1 T 1 P = _______× 100 = _______ × 100 = ___ × 100% 2R1C1 2f R1C1 f From the above expression, it is found that the tilt is directly proportional to the lower 3 dB frequency (f1). It is the ratio of the ON period (TON) to the total period T = TON + TOFF. TON Therefore, duty cycle = ____. T A pulse waveform shown in Fig. 16.4(a) is defined by

vi(t) =

V for 0 £ t £ tp 0 elsewhere

Here tp is the duration of the pulse. The response of the RC high-pass filter to this waveform is similar to that obtained for the step waveform for the duration 0 < t < tp. The response to the pulse waveform can be written as vo(t) = Ve – t/RC for 0 < t < tp Using this equation, we get vo(tp) = Ve – tp/RC Vp = Ve – tp/RC

or

At t = tp, the generalized transient equation is modified with t = tp as the initial time reference. vo(t) = vo(•) + [vo(tp) – vo(•)] e – (t – tp)/RC Now the initial output value vo( t+p ) has to be found from Vp as expressed above. The input has an abrupt fall of –V at t = tp for which the capacitor behaves as short-circuit. Consequently, the output waveform also falls abruptly by –V at t = tp. The initial condition can be written as vo( t+p ) = Vp – V vo( t+p ) = Ve – tp/RC – V vo(t )

vi (t )

V

V

0 0

tp

tp

RC >> 1 tp t

t

(a) Pulse input waveform

(b) Output of the RC high-pass filter for RC/tp >> 1

vo(t ) V

0

tp

Effect of reducing time constant

RC 1 is shown in Fig. 16.4(b). This waveform can be mathematically expressed as vo(t) =

Ve – t/RC,

0 < t < tp

V(e– tp/RC – 1) e – (t – tp)/RC, t > tp

Figure 16.4(c) shows the output waveform for RC/tp > 1 is shown in Fig. 16.5(b). Here, T = T1 + T2. The peak-to-peak amplitude of the input waveform is given by V = V ¢ – V ¢¢ Since the output goes through a discontinuity of the same magnitude while the input is rising and falling abruptly, we can write V 1¢ – V2 = V V1 – V 2¢ = V V1¢ = V1 e – t1/RC V 2¢ = V2 e –t2 /RC By solving the above four equations, we can determine the values of the corner voltages V1, V ¢2, V2 and V ¢2 in Fig. 16.5(b). The output waveform shown in Fig 16.5(c) has a series of sharp positive and negative spikes. When RC > 1

vo(t ) V 0 t V

T1

T2

(c) Output of the RC high-pass filter for RC/T 1

V 1¢ = V1 e – T/2RC V2¢ = V2 e – T/2 RC V1 – V2¢ = V V1¢ – V2 = V Due to the symmetry of the waveform, we have V1 = – V2 and V¢1 = – V¢2 The above set of equations can be used to obtain expression for percentage tilt P. V1 – V¢2 = V Substituting for V 2¢ , we have V1 – V2 e–T/RC = V V1 – (V¢1 – V) e–T/2RC = V V1 – ( V1 e – T/2 RC – V ) e – T/2 RC = V V1( 1 – e – T/RC ) = V ( 1 – e – T/2 RC ) When T/2 RC 1, the output equation of the ramp signal, becomes v0(t) ª at For RC/T > 1 and RC/T > 1

T

t

(c) Output of the RC high-pass filter for RC/T > f2 and is zero in the stop band where f

Vo(t) V

tp

t

(c) Output of the RC low-pass filter for RC/tp > 1, the exponentially rising output waveform cannot reach V at t = tp and Vp < V. The resulting output waveform is shown in Fig. 16.11(b). V0(t) = Vp e–(t – tp)/RC for t > tp If RC/tp > 1

v o (t ) V¢ Vdc

V ¢¢ 0

t (d) Output of the RC low-pass filter for RC/T > 1 is shown in Fig. 16.12(c), where V1 > V ≤ and V2 < V ¢. Here the output waveform looks like a triangular waveform. The output waveform for RC / T > 1 vo(t )

t

(d) Output of the RC low-pass filter for RC/T > 1 looks like a V V triangular waveform as shown in Fig.16.13(c), where V1 > – __ and V2 < __. The output waveform for 2 2 V V __ __ RC/T 0

Here the constant represents the slope of the ramp signal and the waveform is shown in Fig. 16.14 over the interval 0 < t < T for convenience. The ramp input is applied to the RC low-pass filter. Applying KVL to the circuit, we get t

1 vi (t) = vR (t) + vC (t) = i (t) R + __ i (t) dt C0 Where

t dv0(t) 1 __ v0 (t) = i (t) dt and i (t) = C _____ C0 dt

Therefore,

dv0(t) vi (t) = RC _____ + v0(t) dt

dv0(t) t = RC _____ + v0(t) dt Applying Laplace transform, we get __ = sRCV (s) + V (s) 0 0 s2 V0(s) = ______________ RCs2(s + 1/RC) Upon solving, we get RC ________ RC + V0(s) = __2 – _____ s s + 1/RC s Taking inverse Laplace transform on both sides, we have v0(t) =

t – RC + RC e–t/RC

Hence,

(t – RC) + RCe–t/RC

v0(t) =

This response is plotted for different values of RC in Fig. 16.14. According to Fourier analysis, a nonsinusoidal waveform like the ramp signal contains a group of sinusoidal frequency components. When the ramp waveform passes through the low-pass filter, it loses some of its high frequency content. Hence, the slope of the output is lower than that of the input. When RC/T tp, the output also decays exponentially towards zero, v02(t) = Vp e–(t – tp)/ for t > tp Hence the overall pulse response of low pass RL circuit is sum of the voltages v01(t) and v02(t). From Fig. 16.23, it can be seen that the output is distorted. Input The output can be made similar to the input by selecting Signal smaller rise time compared to the pulse width. If rise time, vp tr is 0.35 tp, then the output resembles the input with little v o2( t ) vo1(t ) distortion. With a small time constant, i.e. small tr as compared to tp, the output preserves the shape of the input as shown in the Fig. 16.24.

0

tp

Consider a square wave input with a constant amplitude of A1 for the period T1 and it changes abruptly from A1 to A2 and remains at A2 for the period T2. The period of the square wave is T = T1 + T2.

t

Signal

Input VP = A

A 0.9A

Output

0.1A 0

t

tp

tr tr = R > Rf _____ and R = ÷Rf Rr , where Rf is the forward resistance and Rr is the reverse resistance of the diode. There are four general categories of clippers, viz. (i) positive clipper (ii) negative clipper (iii) biased clipper and (iv) combination clipper. In the series positive clipper as shown in Fig. 16.29(a), when the input voltage is positive, the diode does not conduct and acts as an open circuit and hence the positive half cycle does not appear at the output, i.e. the positive half cycle is clipped off. When the input signal is negative, the diode conduct and acts as a closed switch (short circuit), the negative half cycle appears at the output as shown in Fig. 16.29(c). In the shunt positive clipper as shown in Fig. 16.29(b), when the input voltage is positive, diode conducts and acts as short-circuit and hence there is zero signal at the output, i.e. the positive half cycle is clipped off. When the input signal is negative, the diode does not conduct and acts as an open switch, the negative half cycle appears at the output as shown in Fig. 16.29(c). It is evident from the above discussion that positive clippers act as half wave rectifier. Thus the positive clipper has clipped the positive half cycle completely and allowed to pass the negative half cycle of the input signal. In the negative clipping circuit, the diode is connected in a direction opposite to that of a positive clipper. In the series negative clipper as shown in Fig. 16.30(a), during the positive half cycle of the input signal, the diode conducts and acts as a short-circuit and hence, the positive half cycle of the input signal will appear at the output as shown in Fig. 16.30(c). During the negative half cycle of the input signal, the diode does not conduct and acts as an open circuit. The negative half cycle will not appear at the output, i.e. the negative half cycle is clipped off, as shown in Fig. 16.30(c). It is evident from the above discussion that the negative clippers of both series and shunt types work as half wave rectifier. Thus, the negative clipper has clipped the negative half cycle completely and allowed to pass the positive half cycle of the input signal. In some applications, it is required to remove a small portion of positive or negative half cycle of the signal voltage and hence the biased clipper is used. The name bias is designated because the adjustment of the clipping level is achieved by adding a biasing voltage in series with the diode or resistor. Figure 16.31 shows the circuits of shunt and series type positive clipper along with the input and output voltage waveforms. In the biased series positive clipper as shown in Fig. 16.31(a), the diode does not conduct as long as the input voltage is greater than +VR and

Vi

R

Vo

Vo

Vi

(a)

(b)

Vi V

Vi V t

0 –V Vo

t

0 –V Vo

t

0 –V

0

t

–V Vi V

t

0

–V Vo

t

0

–V (c)

hence, the output remains at +VR. When the input voltage becomes less than +VR, the diode conduct and acts as a short circuit. Hence, all the input signal having less than +VR as well as negative half cycle of the input wave will appear at the output, as shown in Fig. 16.31(c). In the biased shunt positive clipper as shown in Fig. 16.31(b), the diode conducts as long as the input voltage is greater than +VR and the output remains at +VR until the input voltage becomes less than +VR. When the input voltage is less than +VR, the diode does not conduct and acts as an open switch. Hence all the input signal having less than +VR as well as negative half cycle of the input wave will appear at the output, shown in Fig. 16.31(c).

The clipping level can be shifted up or down by varying the bias voltage VR. Figure 16.32 shows the biased series and shunt clippers with reverse polarity of VR along with the input and output voltage waveforms. Here, the entire signal above –VR is clipped off. In the biased series negative clipper shown in Fig. 16.33(a), when the input voltage Vi £ – VR the diode does not conduct and clipping takes place. In the biased shunt clipper shown in Fig. 16.33(b), when the input voltage Vi £ – VR the diode conducts and clipping takes place. The clipping level can be shifted up and down by varying the bias voltage (–VR). Figure 16.34 shows the biased series and shunt clippers with reverse polarity of VR along with the input and output waveforms, as shown in Fig. 16.33(c). Here, the entire signal below +VR is clipped off. This is the combination of a biased positive clipper and a biased negative clipper. Figure 16.35 shows the combination clipper along with the input and output voltage waveforms. When the input signal voltage Vi ≥ + VR1, diode D1 conducts and acts as a closed switch, while diode D2 is reverse biased and D2 acts as an open switch. Hence, the output voltage cannot exceed the voltage level of +VR1 during the positive half cycle.

R

Vi

Vo

R – –VR +

Vi

– +

–VR

(a)

Vo

(b) Voltage Input

t

0 –VR Output (c)

Voltage Output

R

VR

Vi

Vo

VR

(a)

– +

Vo

t Input

–VR

(b)

(c)

R Vi

R – +

VR

Vi

Vo

VR

(a)

(b) Voltage

Output

+ VR

t

0 Input (c)

– +

R

+ –

Vi

0

Vo

Similarly, when the input signal voltage Vi –VR2, diode D2 conducts and acts as a closed switch, while diode D1 is reverse biased and D1 acts as an open switch. Hence the output voltage Vo cannot go below the voltage level of –VR2 during the negative half cycle. It is evident that, the clipping levels may be changed by varying the values of VR1 and VR2. If VR1 = VR2, the circuit will clip both the positive and negative half cycles at the same voltage; levels and hence, such a combination clipper is called symmetrical clipper. The circuit of a two level slicer shown in Fig. 16.36(a) is similar to the combination clipper but with the diode connections reversed. The circuit has a slice cut from positive half cycle of the input signal as shown in Fig. 16.36(b). R

+

D2

D1

Vi

Vo +VB2 – VB2 >VB1 –

+ VB1 –

–

Vi,Vo

+

Output

VR2 VR1 0

Time(t ) Input

(a)

(b)

The different types of clipping or limiting circuits with the input and output waveforms are shown below.

D +

+

Vo(t )

Vo(t) Vi (t)

R

VR

Vo(t)

0

2p

p

Vi (t ) –

– (a)

(b)

3p

wt

D

+

Vo(t ) + Vm

+ Vo(t)

Vi (t)

R

–

Vo(t)

0

V i (t )

p

(a)

R

3p

wt

2p

3p

wt

2p

3p

wt

– Vm

–

+

2p

(b)

Vo(t )

+ Vo(t)

Vi (t)

D

Vo(t)

0

p

Vi (t )

–

– (a)

R

+

(b)

Vo(t ) + Vm

+ Vo(t)

Vi (t)

D

–

Vo(t)

VR

+

+ Vo(t)

Vi (t)

p

– Vm

–

D

0

V i (t )

R

VR

Vo(t)

– VR –

– (a)

V i (t )

Vo(t ) + Vm VR 0

p 2p

3p wt

– Vm (b)

D

VR

+

+ Vo(t )

Vo(t) Vi (t)

R

VR 0

Vo(t) VR

–

p

D

2p

3p wt

2p

3p wt

2p

3p

(b)

VR

+

+ Vo(t ) + Vm VR

Vo(t) Vi (t)

R

–

Vo(t)

– VR

0

Vi (t )

p

– Vm

– (a)

D

(b)

VR

+

+ Vo(t )

Vo(t) Vi (t)

R

VR

VR

Vo(t)

0 – VR

–

p

Vi (t)

– (a)

R

(b)

Vo(t )

+ Vo(t)

Vi (t)

3p wt

– (a)

+

2p

Vi (t )

Dz

Vo(t)

+Vm

Vy Vi(t )

– Vz –

0

p

– Vz – Vm

– (a)

Vy

(b)

(c)

wt

+

R

Vo(t )

+

+Vm Vz

Vo(t) Vi (t)

Dz

–

Vo(t)

Vz

– Vy Vi(t )

R

Vo(t)

0

Vz Vi(t )

p

wt

2p

3p

wt

Vo(t ) Vo(t)

D Vo(t) Vz

– (a)

3p

(b)

+

–

2p

– Vm

(a)

Vi (t)

wt

+ Vm VR

Vz

–

R

3p

Vo(t )

Dz

+

2p

(c)

Vo(t) D

–

p

(b)

+

Vi (t)

0

– Vm

– (a)

+

– Vy

+ Vm

– Vz 0 – Vz Vi(t ) – V z

p

– Vm (b)

Determine the output waveform for the network of Fig. 16.49(a) for the input sinusoidal and square waveforms. Assume the diode is ideal. 3V – + Vi

R

(a)

Vo

Solution Here, the addition of bias voltage + 3 V shifts the entire input signal by +3 V. Then the circuit clips off the negative half cycle lying below the zero axis. The resultant output waveforms are shown in Fig. 16.49(b), (c), (d) and (e). Vi

Vi

+15 V

+15 V

O

T/2

t

T

–15 V

t

O

–15 V (b)

+18 V

(c)

Vo

+18 V

+3 V OV

+3 V OV

t

–12 V

Vo

t

–12 V (d)

(c)

Determine Vo for the network of Fig. 16.50 (a), (b) for the waveform given. Assume the diode is ideal. +15 V

Vi

R Vi

3V

+ –

Vo

O t

–15 V (a)

(b)

Solution When the input voltage Vi £ 3 V the diode is forward biased, resulting in a short-circuited diode. Then the circuit clips off the wave which is below +3 V. The resultant output waveform is shown in Fig. 16.50(c). Vo

+ 15 V

Vi

Output

+3V O

t

Input

– 15 V (c)

Determine Vo for the network of Fig. 16.51(a), (b) for the waveform given. Assume the diodes are ideal. Vi

Input

10 V R Vi 5V

D1 + 3V –

– +

D2

t

0

Vo

–15 V (a)

(b)

Solution When the input voltage Vi ≥ 5 V, the diode D1 conducts when Vi £ –3 V, diode D2 conducts. Hence, the positive half cycle of the input voltage is clipped at +5 V and the negative half cycle is clipped at –3 V, as shown in Fig. 16.51(c). Vo

Solution

10 V 5V 0 –3 V

t

–15 V (c)

Determine Vo for the network of Fig. 16.52(a), (b) for the waveform given. Assume the diodes are ideal. Vi

Input

10 V R Vi 3V

D1 + 6V –

– +

D2

t

0 Vo – 10 V

(a)

(b)

Solution When the input voltage Vi £ 3V, D1 conducts. When Vi ≥ 6V, D2 conducts. Hence, both D1 and D2 will not conduct and act as open switches and allow the signal to pass during 3 V ≥ Vi £ 6 V. The resultant waveform is shown in Fig. 16.52(c).

Vo 10 V 6V 3V 0

Solution

t

(c)

Sketch the output waveform for the positive peak limiting circuit shown in Fig. 16.53(a) for the sinusoidal input vi(t) = 6 sin 2 ft shown in Fig 16.53(b). +

R

+

Vi (t )

5.7 V D Vi (t)

Vo(t)

0

5V –

–

2p

p

wt

–6V

(a)

(b)

Solution The limiting circuit has a reference voltage equal to 5 V. When the silicon diode whose cut in voltage is 0.7 V, is forward biased, the resultant output voltage becomes 5.7 V. When vi(t) ≥ 5.7 V, the diode will be ON. When vi(t) ≥ 5.7 V, the diode will be OFF and hence vo(t) = vi(t). This can be summarised as vo(t) =

3p

5.7 V for vi(t) ≥ 5.7 V vi(t) for vi(t) < 5.7 V

Vo(t )

5.7 V 0

2p

p

3p

wt

–6V (c)

When the sinusoidal input waveform passes through this circuit, the output waveform is obtained as shown in Fig. 16.53(c).

In the diode positive peak limiting circuit of Fig. 16.54(a), VR = 10 V, Vi(t) = 20 sin 2 ft and the diode forward resistance is Rf = 100 while Rr = and Vr = 0. Neglect all capacitances in the circuit. Draw the input and output waveform if R =1.2 k . +

R

+

V i (t )

+20 V D Vi (t)

Vo(t)

0

VR

–

– (a)

2p

p

3p

wt

–20 V (b)

Solution From the circuit shown in Fig. 16.54(a), and the input waveform shown in Fig. 16.54(b), vi(t)(max) = 20 V. Given Rf = 100 kW and VR = 10 V. When vi(t) > VR, the diode conducts. The reference voltage, VR = 10 V. When Vi(t) = Vo(t), the diode does not conduct. When the diode conducts i.e. in ON state, the following equations are valid.

Vo(t )

10.78 V 0

2p

p

– 20 V (c)

3p

wt

Rf Vo(t) = (Vi(t) – VR) ______ + VR R + Rf R + 2Rf Vo(t)max = VR _______ R + Rf

(

)

The maximum value of the output waveform for R = 1.2 kW is calculated as

(

)

1200 + 200 Vo(t)max = 10 × __________ = 10 × 1.078 = 10.78 V 1200 + 100 The output waveform is sketched in Fig. 16.54(c).

In the diode limiting circuit of Fig. 16.55(a), VR = 15 V, Vi(t) = 30 sin 2 ft and the diode forward resistance is Rf = 150 While Rf = 15 k and Vi = 0. Neglect all capacitances. Draw the input and output waveforms if R = 15 . R

+

Vi (t ) + 30 V

+ D

Vi (t)

Vo(t) VR

0

–

–

– 30 V

(a)

2p

p

3p wt

(b)

Solution We consider the given diode circuit in Fig. 16.55(a) and the input waveform in Fig. 16.55(b). The diode is in ON state when Vi(t) > VR. Here the reference voltage VR = 15 V. The following equations are valid when the diode is in ON state

(

)

Ri Vi(t) = (Vi(t) – VR) ______ + VR R + Rf

(

R – 2 Rf Vo(t)max = VR ________ R + Rf

)

when Vi(t) < VR. The diode does not conduct.

( )

)

Rr Vo(t) = (Vi(t) – VR) ______ + VR R + Rr

(

R – 2Rr Vo(t)min = VR _______ R + Rr

When R = 150 W, the maximum values of the output waveform are calculated as

(

)

150 + 300 Vo(t)max = 15 × _________ = 15 × 1.5 = 22.5 V 150 + 150

(

Vo(t )

+ 22.5 V

0

)

150 – 30000 Vo(t)min = 15 × ___________ = 15 × (–1.97) = –29.5 V 150 + 15000 The output waveform is sketched in Fig. 16.56.

– 29.5 V

2p

p

3p wt

(c)

The nonlinear circuit which was used to perform the operation of clipping may also be used to perform the operation of comparison and this circuit shown in Fig.16.57(a) is called the comparator. The comparator circuit compares an input signal Vi(t) with a reference voltage VR. The comparator output is independent of the signal until it attains the reference level. When the signal and reference level become equal, there will be a sharp pulse at the comparator output. The input signal is considered as a ramp. At t = t1, Vi(t) = VR + Vg , and V0 = VR until t = t1. Beyond t = t1, the output rises with the input signal. At some later time t = t2, the device responds in the range DV0 for a precise input voltage DVt corresponding to Dt.

When VR = 0, the output will respond everytime the input passes through zero. This arrangement is called a zero-crossing detector. The most important systems using comparators are

(i) (ii) (iii) (iv) (v) (vi) (vii)

Square waves from a sine wave Timing markers generator from a sine wave Phase meter Amplitude—distribution analyzer Pulse time modulation Pulse, square wave and triangular wave generators, and Analog to digital converter

Clamping network shifts (clamps) a signal to a different d.c. level, i.e. it introduces a dc level to an ac signal. Hence, the clamping network is also known as d.c. restorer. These circuits find application in television receivers to restore the dc reference signal to the video signal. The clamping network has the various circuit components like a diode, a capacitor and a resistor. The time constant for the circuit t = RC must be large so that the voltage across the capacitor does not discharge significantly when the diode is not conducting. Consider the clamper circuit shown in Fig. 16.58. The diodes used are assumed to be ideal. A square wave with maximum amplitude of V is given as the input to the network. During the positive half cycle, the diode conducts, i.e. it acts like a short circuit. The capacitor charges to V volts. During this interval, the output which is taken across the short C circuit will be Vo = 0 V. During the nega+ – tive half cycle, the diode is open. The output voltage can be found out by applying Vi D R Kirchhoff’s law. –V – V – Vo = 0 Therefore,

Vi

Vi

Vo = –2 V

The analysis of the clamper circuit can be done as follows. Determine the portion of the input signal that forward biases the diode. When the diode is in short circuit condition, the capacitor charges up to a level determined by the voltage across the capacitor in its equivalent open circuit state. During the open circuit condition of the diode, it is assumed that the capacitor will hold on to all its charge and therefore voltage. In the clamper networks, the total swing of the output is equal to the total swing of the input signal.

+V

V 0

0

t

Vo

–2V

T

t

–V

–V

0

T/2

Vo t

0

–2V

T T/2

t

Determine Vo for the network shown in Fig. 16.59(a). C

Vi

Vc = 20 V

+ –

R Vo

5V

(a)

Solution The frequency of the given input signal is 2000 Hz. Hence, the period of the signal is 0.5 ms. During the negative half of the input signal, the diode is forward biased and it acts like a short circuit and the capacitor charges to 20 V. This can be found out by applying Kirchhoff’s law in the input side.

Vi

15 V

–15 V Vo

15 + Vc – 5 = 0 and

t

30 V

35 V

Cc = 20 V

The voltage across the resistor will be equal to the dc voltage 5 V. 5V 0

During the positive half of the input signal, the diode is reverse biased and it acts like an open circuit. Hence, the 5 V battery has no effect on Vo. Applying Kirchhoff’s voltage law around the outside loop, we get +15 + 20 – Vo = 0.

t

(b)

Therefore, Vo = 35 V. The resulting output appears in Fig. 16.59(a). Here, the output swing of 30 V is equal to the input swing of 30 V.

Determine Vo for the clamping circuit shown in Fig. 16.60(a) for the given sinusoidal input signal Fig. 16.60(b). Vi

10 V

C

+

– t

0 Vi

R

Vo

–10 V (a)

(b)

Solution During the negative half of the input signal, the diode conducts, and acts like a short circuit. Now, the output voltage, Vo = 0 V. The capacitor is charged to 10 V with polarities shown in Fig. 16.60(a) and it behaves like a battery. During the positive half of the input signal, the diode does not conduct, and acts like an open circuit. Hence, the output voltage, Vo = 10 V + 10 V = 20 V. This gives positively clamped voltage and the resultant output waveform is shown in Fig. 16.60(c).

Vo 20 V 10 V

t

0 (c)

Determine Vo for the clamping circuit shown in Fig. 16.61(a) for the given sinusoidal input signal, Fig. 16.61(b). Vi +12 V

C +

–

t

0

Vi

R

Vo –12 V

(a)

(b)

Solution During the positive half of the input signal, the diode conducts and acts like a short circuit. Now, the output voltage, Vo = 0 V. The capacitor is charged to 12 V with polarities shown in Fig. 16.61 and it behaves like a battery. During the negative half of the input signal, the diode does not conduct and acts like an open circuit. Hence, the output voltage, Vo = –12 V –12 V = – 24 V. This gives negatively clamped voltage and the resultant output waveform is shown in the Fig. 16.61 (c).

Vo t

0 –12 V +24 V (c)

Multivibrators are two-stage switching circuits in which the output of the first stage is fed to the input of the second stage and vice-versa. The outputs of two stages are complementary. Multivibrators are of three types, namely, (i) Astable multivibrator, (ii) Bistable multivibrator, and (iii) Monostable multivibrator.

The astable or free running multivibrator generates square wave without any external triggering pulse. It has no stable states, i.e. it has two quasi stable states. It switches back and forth from one state to the other, remaining in each state for a time depending upon the discharging of a capacitive circuit. Figure 16.62(a) shows a basic symmetrical transistor astable multivibrator in which components in one half of a cycle of the circuit are identical to their counter part in the other half. The square wave output can be taken from collector point of Q1 or Q2. The waveforms at base and collector of transistors Q1 and Q2 are shown in Fig. 16.62(b).

+ VCC

RC1 VC 1

R1

RC 2

R2

C1 +

–

–

+

Q1

VC 2 Q2

VB1

VB2

(a)

Q1 ON

Q1

VBE(sat) Q2 OFF

Q2

OFF

Q1 ON

ON

Q2 OFF

VB1

t2

t3

time (t )

t1

t2

t3

time (t )

t1

t2

t3

time (t )

t2

t3

time (t )

t1

0

–Vcc

t2 = R2C2 T1

T2 T

VCC VC1 VCE(sat) 0

VBE(sat) VB2 0

–Vcc

t1 = R1C1

Vcc VC2 VCE(sat) 0

t1 (b)

When the supply voltage +VCC is applied, one transistor will conduct more than the other due to some circuit imbalance. Initially, let us assume that Q1 is conducting and Q2 is cut-off. Then VC1, the output of Q1 is equal to VCE(sat), i.e. approximately zero volt and VC2 = +VCC. At this instant, C1 charges exponentially with a time constant R1C1 towards the supply voltage through R1 and correspondingly VB2 also increases exponentially towards VCC. When VB2 crosses the cut-in voltage, Q2 starts conducting and VC2 falls to VCE(sat). Also, VB1 falls due to capacitive coupling between collector of Q2 and base of Q1, thereby driving Q1, into OFF state. Now, the rise in voltage VC1 is coupled through C1 to the base of Q2, causing a small overshoot in voltage VB2. Thus Q1 is OFF and Q2 is ON. At this instant, the voltage levels are: VB1 is negative, VC1 = VCC, VB2 = VBE(sat) and VC2 = VCE(sat). When Q1 is OFF and Q2 is ON, the voltage VB1 increases exponentially with a time constant R2C2 towards VCC. Therefore, Q1 is driven into saturation and Q2 is cut-off. Now, the voltage levels are: VB1 = VBE(sat), VC1 = VCE(sat), VB2 is negative and VC2 = VCC. It is clear that when Q2 is ON, the falling voltage VC2 permits the discharging of the capacitor C2 which drives Q1 into cut-off. The rising voltage of VC1 feeds back to the base of Q2 tending to turn it ON. This process is said to be regenerative.

The expression for time period T can be derived by finding the ON time T1 for Q1 and the ON time T2 for Q2. The waveform at the base of transistor as shown in Fig. 16.62 is taken for consideration. The equation at the output can be written as Vo = Vf – (Vf – Vi)e– t/t where Vo means the base voltage at B2. As the capacitor C2 discharges exponentially, the voltage VB2 at base B2 increases exponentially. Here,

Vi = initial value of VB2 = – VCC

and

Vf = final value of VB2 = +VCC

Though it stops increasing beyond the cut in voltage Vg, its rise in towards +VCC, which is its final steady state value with the time constant t2 = R2C2. Therefore,

VB2 = VCC – ( VCC – (– VCC) ) e– t/R2C2 = VCC – 2VCC e– t/R2C2 = VCC ( 1 – 2 e– t/R2C2 )

Here, at switching time, t = T2 and VB2 = Vg Therefore,

Vg = VCC ( 1 – 2e– T2/R2C2 )

The best approximation to obtain T2 is, Vg = 0 V Therefore, i.e.

0 = VCC ( 1 – 2e– T2/R2C2 ) 1 – 2e– T2/R2C2 = 0 e– T2/R2C2 = 0.5

ln ( e– T2/R2C2 ) = ln (0.5) – T2 _____ = – 0.693 R2C2 T2 = 0.693 R2C2 Hence the ON time for Q2 is T2 = 0.693 R2C2 Similarly the ON time T1 for Q1 can be expressed as the same as T2 by the equation, T1 = 0.693 R1C1 Therefore, the total period of the waveform is T = T1 + T2 = 0.69 (R1C1 + R2C2) If R1 = R2 = R and C1 = C2 = C, we have a symmetrical multivibrator, with outputs at the two collectors having the same waveforms but out of phase with each other. Therefore,

1 1 T = 1.386 RC and f = __ = _________ T 1.386 RC

To ensure oscillations, the value of resistors should satisfy the following conditions. R1 £ hFE(min) RC1 and R2 £ hFE(min) RC2 where hFE(min) is the minimum value of d.c. current gain of transistors Q1 and Q2. 1. The astable multivibrator is used as square wave generator, voltage to frequency convertor and in pulse synchronisation, as clock for binary logic signals, and so on. 2. Since it produces square waves, it is a source of production of harmonic frequencies of higher order. 3. It is used in the construction of digital voltmeter and SMPS. 4. It can be operated as an oscillator over a wide range of audio and radio frequencies.

If an astable multivibrator has C1 = C2 = 1000 pF and R1 = R2 = 20 k , calculate the frequency of oscillation.

Solution

The frequency of a symmetrical astable multivibrator is 1 1 f = _________ = ___________________________ = 36.25 kHz 1.386 RC 1.386 × 20 × 103 × 1000 × 10–12

Determine the period and frequency of oscillation for an astable multivibrator with component values R1 = 2 k , R2 = 10 k , C1 = 0.01 F and C2 = 0.05 F.

Solution

The period of oscillation for an asymmetrical astable multivator is

T = 0.693 (R1C1 + R2C2) = 0.693 (2 × 103 × 0.01 × 10 – 6 + 10 × 103 × 0.05 × 10 – 6) = 360.36 ms 1 1 Therefore, the frequency of oscillation, f = __ = ____________ = 2.775 kHz T 360.36 × 10–6 Determine the value of capacitors to be used in an astable multivibrator to provide a train of pulse 2 s wide at a repetition rate of 100 kHz, if R1 = R2 = 20 k .

Solution

The period of oscillation is 1 1 T = __ = _________3 = 10 ms f 100 × 10 T1 = 2 ms

(given)

T2 = T – T1 = 8 ms

Hence,

T1 = 0.693 R1C1 T1 2 × 10 – 6 C1 = ________ = _______________3 = 145 pF 0.693 R1 0.693 × 20 × 10

Therefore,

T2 = 0.693 R2C2 T2 8 × 10 – 6 C2 = ________ = _______________3 = 580 pF 0.693 R2 0.693 × 20 × 10

Therefore,

Design a saturated collector coupled multivibrator for the following specifications: Output voltage 12 V peak; Output to be a positive pulse; the duration is 10 s; the time between pulses to be 20 s. For the BJTs is used, hFE (min) = 100; ICBO = 0 and IC(ON) = 1 mA.

Solution

To design a saturated collector coupled astable multivibrator

Given:

Vcc = 12 V (peak) IC (on) = 1 mA, hfe (min) = 100 ICBO = 0, TON = 10 ms, TOFF = 20 ms

Let us assume that Refer to Fig. 16.62.

VCE(sat) = 0.2 V

Here, ‘C’ can be kept constant and timing resistor ‘R’ can be varied to get appropriate Ton, Toff (or) ‘R’ can be kept constant ‘C’ can be varied. Now R £ hfe Rc. Therefore, it is better to keep ‘R’ constant. VCC – Vc2(sat) RC = ___________ IC(ON)

Assuminmg VC2 (sat) ª 0.2 V, 12 – 0.2 RC = ________ = 11.8 kW 1 × 10 – 3 R £ hfe RC £ 100 × 11.8 × 103 £ 1.18 MW Hence, let us assume that R = R1 = R2 = 1 MW TOFF = 0.693 RC1 20 × 10 – 6 = 0.693 × 106 × C1 Therefore,

C1 = 29 pF TON = 0.693 RC2 10 × 10 – 6 = 0.693 × 106 × C2

Therefore,

C2 = 14.5 pF

Design a collector coupled astable multivibrator using VCC(peak) = 20 V and Ic(sat) = 3 mA, to generate a pulse wave at a frequency f = 2 kHz with 70% duty cycle. Assume hfe(min) = 100.

Solution

Refer to Fig. 16.63.

Given: Ic(sat) = 3 mA, f = 2 kHz, hfe(min) = 100 and duty cycle = 70% = 0.7 VCC – VCE(sat) 20 – 0.3 RC = ____________ = ________ = 6.56 kW IC 3 × 10 – 3 Here,

IC 3 × 10 – 3 IB = ___ = ________ = 0.03 mA 100 hfe VCC – VBE(sat) 20 – 0.7 R1 = ____________ = __________ = 643.33 kW IB 0.03 × 10 – 3 R2 = R1 = 643.33 kW

Here,

We know that Duty cycle

Therefore, We know that

1 1 T = __ = _______3 = 0.5 ms or 500 ms f 2 × 10 TON TON = ___________ = ____ TON + TOFF T T ON 0.7 = __________ where TON = 350 ms and TOFF = 150 ms 500 × 10 – 6 TON = 0.693 R1C1

VCC = + 20 V

RC 6.56 kW C2

Vc1

R2 643.3 kW

R1 643.3 kW

RC 6.56 kW

C1

Vc2

0.336 nF 0.785 nF

Q1

Q2

We know that,

350 × 10–6 = 0.693 × 643.33 × 103 × C1 350 × 10 – 6 C1 = __________________3 = 0.785 mF 0.693 × 643.33 × 10 TOFF = 0.693 R2C2

Therefore,

150 × 10 – 6 = 0.693 × 643.33 × 103 × C2

Therefore,

150 × 10 – 6 C2 = __________________3 = 0.336 nF 0.693 × 643.33 × 10

In the astable multivibrator, R1 = R2 = R = 10 k frequency of the square wave.

Solution

and C1 = C2 = 0.01 F. Determine the time period and

Given R1 = R2 = R = 10 kW and C1 = C2 = 0.01 mF.

(a) Time period of the square wave is T = 1.386 RC = 1.386 × 10 × 103 × 0.01 × 10– 6 = 0.1386 msec (b) Frequency of the square wave is 1 1 f = __________ Hz = ___________ Hz = 7215 Hz T in second 1.386 × 10 – 3 The modified astable multivibrator circuit is shown in Fig. 16.64. When the transistors Q1 and Q2 are OFF, the base voltage at each transistor is approximately –VCC. When VCC becomes more than the maximum reverse VBE, the transistors will be damaged. The diodes D1 and D2 protect the transistor base-emitter junctions against the reverse bias. If C1 and C2 are unequal or RB1 and RB2 are unequal, one transistor will remain OFF for a longer period than the other. Hence, the output will not be a perfect square wave i.e., the ON and OFF times will not be equal. The inclusion of R1 in series with RB1 controls the rate of discharge of capacitor C1 and adjusts the OFF time of Q1 and thus frequency is controlled. In order to synchronize the frequency of an astable multivibrator to some external frequency, a negative going spike is coupled to the base of Q2 via capacitor C3.

+VCC RC1 Frequency control

RB2

RB1

RC2

Q2 output when C1 > C2

R1 C1

C2

Q1

Q2

D1

D2

C3 Synchronizing input

Due to the + VCC circuit symmetry of collector-coupled astable multiviRC RC RB RB brator, sometimes both the transistors Q1 and Q2 may be ON or remain OFF. Therefore, when the supply voltage VCC is supplied, the circuit may not start oscillatC2 C1 ing. By shorting the base and emitter terminals of one of the transistors for a short time, the oscillation can Q1 Q2 be started. But for solving this problem practically, the emitter coupled astable multivibrator circuit shown in Fig. 16.65 is used. Here, when one transistor starts conRE ducting, the emitter voltage of the other one increases and its base voltage decreases. Thus, the presence of RE eliminates the possibility of both transistors remaining ON at the same time and ensures that the circuit oscillates. In the circuit design, RE = VCC/2IC and the other components can be determined as done in collector coupled astable multivibrator.

Monostable multivibrator has one stable state and one quasi-stable state. It is also known as one-shot multivibrator or univibrator. It remains in its stable state until an input pulse triggers it into its quasistable state for a time duration determined by the discharging an RC circuit and the circuit returns to its original stable state automatically. It remains there until the next trigger pulse is applied. Thus, a monostable multivibrator cannot generate square waves of its own like an astable multivibrator. Only external trigger pulses will cause it to generate the rectangular waves. Figure 16.66(a) shows the circuit of a transistor monostable multivibrator and the output waveforms are shown in Fig. 16.66(b). It consists of two identical transistors Q1 and Q2 with equal collector resistances

of RC1 and RC2. The output of Q2 is coupled to the input at the base of Q1 through a resistive attenuator in which C1 is a small speed up capacitor to speed up the transition. The values of R2 and –VBB are chosen so as to reverse bias Q1 and keep it in the OFF state. The collector supply +VCC and R will forward bias Q2 and keep it in the ON state. Actually, this is the stable state for the circuit. When a positive trigger pulse of short duration and sufficient magnitude is applied to the base of Q1 through C2, transistor Q1 starts conducting and thereby decreasing the voltage at its collector VC1 which is coupled to the base of Q2 through capacitor C. This decreases the forward bias on Q2 and its collector current decreases. The increasing positive potential on the collector of Q2 is applied to the base of Q1 through R1. This further increases the base potential of Q1 and Q1 is quickly driven to saturation and Q2 to cut-off. The capacitor C is charged to approximately +VCC, through the path VCC, R and Q1. As the capacitor C discharges, the base of Q2 is forward biased and collector current starts to flow into Q2. Thus Q2 is quickly driven to saturation and Q1 is cut-off. This is the stable state for the circuit and remains in this condition until another trigger pulse causes the circuit to switch over the states. The pulse width T is the time for which the circuit remains in the quasi-stable state, which is also called gate width. To derive its expression, consider the voltage variation at base of Q2. Initially, Q2 is in saturation and hence VB2 = VBE2(sat) = Vs which is about 0.72 V for silicon transistor. When the pulse is applied at t = 0, i.e. t = 0+ as the capacitor voltage cannot change instantaneously, the voltage VB2 decreases by I1RC. Then the capacitor charges exponentially and hence VB2 also increases exponentially, whose final value at t Æ • is VCC. When VB2 becomes equal to Vg , then Q2 starts conducting and the circuit comes back to stable state. This is the time T at which transition occurs. The graph of VB2 against time is shown in Fig. 16.67.

To write equation for exponential charging of capacitor, we can write When t = 0+,

Vi = Vs – I1RC

When t = •,

Vf = VCC

Here

VC = Vf – (Vf – Vi) e – t/t

where t = time constant

Therefore,

VB2 = VCC – (VCC – Vs + I1RC) e– t/t

At t = T,

VB2 = Vg

Therefore,

Vg = VCC – (VCC – Vs + I1RC) e– t/t

(

VCC + I1RC – Vs T = t ln _______________ VCC – Vg where

)

Vs = 0.2 V for germanium = 0.72 V for silicon

When Q1 is in saturation under quasi-stable state, we can write VC1 = VCE (sat)

and I1RC = VCC – VCE (sat)

Since Vs = VBE (sat), we get

( (

VCC + VCC – VCE (sat) – VBE (sat) T = t ln ___________________________ VCC – Vg 2VCC – (VCE (sat) + VBE (sat)) = t ln ________________________ VCC – Vg

{[

) )]

(

VCE (sat) + VBE (sat) 2 VCC – ________________ 2 __________________________ = t ln VCC – Vg

= t ln (2) + t ln

{[

)

}

(

)

VCE (sat) + VBE (sat) VCC – ________________ 2 _______________________ VCC – Vg

]}

At room temperature, VCE (sat) + VBE (sat) = 2Vg Therefore,

T = t ln (2) + t ln (1) = t ln (2)

The time constant t for the charging path of capacitor C is RC. i.e. t = RC Hence,

T = 0.693 RC.

The duration of the output pulse of the monostable multivibrator is given by T = 0.693 RC. 1. 2. 3. 4.

The monostable multivibrator is used to function as an adjustable pulse width generator. It is used to generate uniform width pulses from a variable width input pulse train. It is used to generate clean and sharp pulses from the distorted pulses. It is used as a time delay unit since it produces a transition at a fixed time after the trigger signal.

Calculate the component values of a monostable multivibrator developing an output pulse of 140 s duration. Assume hFEmin = 20, Ic(sat) = 6 mA, VCC = 6 V, VBB = – 1.5 V.

Solution

At stable state, Q2 is ON and Q1 is OFF: VCC – VCE (sat) 6 – 0.3 RC2 = RC1 = ____________ = ________ = 950 W IC (sat) 6 × 10 – 3 IC (sat) 6 × 10 – 3 IB2 (sat) = _______ = ________ = 0.3 mA 20 hFE (min)

Also,

IB1(sat) = 0.3 mA VCC – VBE (sat) 6 – 0.7 R =_____________ = _________ = 17.67 kW IB2 (sat) 0.3 × 10 – 3 [ VBE(sat) = 0.7 V for Si transistor]

At quasi-stable state, Q1 is ON and Q2 is OFF T = 0.693 RC Therefore, Assume Therefore,

140 × 10 – 6 T C = _______ = _________________3 = 0.0114 mF 0.693 R 0.693 × 17.67 × 10 IB1(sat) = IR2 IR1 = IB1(sat) + IR2 = 0.3 mA + 0.3 mA = 0.6 mA VCC = VBE(sat) + IR1 (RC2 + R1) 6 = 0.7 + 0.6 × 10 –3 (950 + R1)

Therefore,

VCC – VBE (sat) R1 = ____________ – RC2 IR1 6 – 0.7 = _________ – 950 = 7.883 kW 0.6 × 10–3 VBE (sat) – (– VBB) R2 = _______________ IR2

0.7 + 1.5 = _________ = 7.33 kW 0.3 × 10–3 The speed up capacitor C1 is chosen such that R1C1 = 1 ms and hence, 10 – 6 C1 = __________3 = 126.9 pF 7.833 × 10

Design and draw a saturated collector coupled monostable multivibrator for the following specifications: VCC = 10 V, VBB = – 5 V, pulse duration = 12 ms, IC(ON) = 2 mA and two NPN transistors with minimum hfe = 100 and ICBO = 0.

Solution

Refer to Fig. 16.68. Va = + 10 V

RC1 4.85 kW Vaa D1 Pulse Trigger

I R 4.85 kW

R

RC2 4.85 kW

37.42 kW

C 0.03 mF

C1

IB1

Q2

Q1 28.5 kW

R2 l2

VCC = – 5 V

Given We know that

VCC = 10 V, VBB = –5 V, T = 12 ms, IC = 2 mA and hfe = 100 VCC – VCE(sat) 10 – 0.3 RC1 = RC2 = ____________ = _______ = 4.85 kW IC 2 × 10–3 IC 2 IB2 = ___ = ____ × 10–3 = 0.02 mA hfe 100 VCC – VBE (sat) 10 – 0.7 R = ____________ = __________ = 465 kW IB2 0.02 × 10–3 T = 0.693 RC

Hence, Assume

12 × 10 – 3 12 × 10 – 3 T C = _______ = ________________3 = ____________ = 0.03 mF 0.693 R 0.693 × 465 × 10 320.85 × 10 – 3 Ic 2 mA I2 = ___ = _____ = 0.2 mA 10 10 VB1 = VBE = 0.7 V VR2 = VB1 – VBB

Therefore,

VR2 VB1 – VBB 0.7 – (– 5) _________ 5.7 R2 = ____ = _________ = _________ = = 28.5 k I2 I2 0.2 × 10–3 0.2 × 10 – 3 I1 = IB1 + I2 = 0.02 mA + 0.2 mA = 0.22 mA VCC – VB1 10 – 0.7 RC2 + R1 = _________ = __________ = 42.27 × 10 – 3 I1 0.22 × 10 – 3

Hence,

R1 = 42.27 × 103 – 4.85 × 103 = 37.42 k

The emitter coupled monostable multivibrator circuit is shown in Fig. 16.69. Here both the emitter terminals of transistors Q1 and Q2 are connected to ground via a resistance RE. R2 is connected directly to ground instead of being connected to a negative supply voltage and hence the emitter coupled monostable multivibrator operates from a single supply voltage. As the transistors are unsaturated due to the presence of RE, they can be made to switch faster than that of the collector coupled monostable multivibrator.

+ VCC

RC1

RC 2

RB

C1 C2 Q1

R1 Q2

As the transistor Q2 is supplied with base current via RB, it is R2 VE RE normally ON and so a voltage drop VE across RE. The voltage VC 2 at collector of Q2 becomes lower than the supply voltage VCC. The base of Q1 is biased from VC 2 through the potential divider R1 and R2 whose values are selected so that VB 1 is less than VE to keep Q1 OFF and Q2 ON. Therefore, VC 1 is equal to VCC and the voltage across the capacitor C1 is equal to (VCC – VB 2). When Q1 is triggered ON, VC 1 falls and the charge on C1 causes VB 2 to drop. When Q2 is OFF, VC 2 starts to increase, thus increasing VB 1. Now VE becomes (VB 1 – VBE 1). The Q2 remains OFF until C1 has discharged enough to allow VCB2 to increase above VE. The triggering methods and the design procedure for a saturating emitter coupled monostable multivibrator are the same as those for the collector coupled monostable multivibrator. Let us assume that Q1 is OFF and Q2 is ON in a collector coupled monostable multivibrator. When a positive going spike (triggering pulse) is given to the base of Q1 via a coupling capacitor, Q1 turns ON which causes Q2 to turn OFF. Otherwise, when a negative going spike is given to the base of Q2 via a coupling capacitor, Q2 turns OFF which causes Q1 to turn ON. Positive going triggering pulse is preferred because triggering by a negative going spike at the base of Q2 requires a larger input current than triggering by a positive going spike at the base of Q1. A monostable multivibrator circuit shown in Fig. 16.70 can be triggered by an additional transistor Q3 which is normally OFF. The pulse is differentiated by the coupling capacitor CC and resistor R3 to generate the triggering pulse. A positive spike turns Q3 ON and there will be a voltage drop across RC1, and the charge on C1 will turn Q2 OFF.

VCC RC1 +

lc Cc

C1 R1

Q3 Q1

Input

R3

D2

Vi

–

Q2 R2

The bistable multivibrator is also referred to as flip-flop, Eccles–Jordan circuit, trigger circuit or binary. It has two stable states. A trigger pulse applied to the circuit will cause it to switch from one state to the other. Another trigger pulse is then required to switch the circuit back to its original state. Figure 16.71(a) shows the circuit of a bistable multivibrator using two NPN transistors. In this circuit the output (collector point) of a transistor Q2 is coupled to the base of transistor Q1 through a resistor R2. Similarly the output of Q1 is coupled to the base of Q2 through resistor R1. When abruptly changing pulse is applied to the circuit, the transition from one state to other should occur instantaneously. The transition time i.e. the time interval during which conduction transfers from one transistor to other should be as small as possible. The main purpose of capacitors C1 and C2 is to improve the switching characteristics of the circuit by passing the high frequency components of these square wave pulses. This allows fast rise and fall times, so that these square waves will not be distorted. C1 and C2 are thus called Commutating capacitors, speed-up capacitors or transpose capacitors. When the circuit is first switched on, one of the transistors will start conducting more than the other. This transistor is thus driven into saturation (i.e. ON). Then, because of the regenerative feed back action, the other transistor is taken into cut-off (i.e. OFF) state. Let us assume that transistor Q1 is ON and Q2 is OFF. It is a stable state of the circuit and will remain in this state till a trigger pulse is applied from outside. A positive triggering pulse applied to the reset input (base of Q2) increases its forward bias, thereby turning transistor Q2 ON and an increase in collector current and a decrease in collector voltage. The fall in collector voltage is coupled to the base of Q1, wherein it reverse biases the base– emitter circuit and Q1 is thus turned OFF. The circuit is then in its second stable state and remains so till a positive trigger pulse is applied to set input (base of Q1). A similar action can be achieved by applying a negative pulse at the set input for transition from the first stable state to the second stable state and by applying a negative pulse at the reset input, reverse transition can be obtained. Figure 16.71(b) shows the waveforms at the collector of transistors Q1 and Q2 of the bistable multivibrator in response to the trigger pulses applied to the set and reset input. It is evident from these waveforms that the output waveforms are the complement of each other.

1. The bistable multivibrator is used as memory elements in shift registers, counters, and so on. 2. It is used to generate square waves of symmetrical shape by sending regular triggering pulse to the input. By adjusting the frequency of the input trigger pulse, the width of the square wave can be altered. 3. It can also be used as a frequency divider (as a divide by two counter).

Calculate the stable state currents and voltages for the bistable multivibrator having VCC = 12 V, VBB = –12 V, RC1 = RC2 = 2.2 k , R1 = R2 = 15 k , R3 = R4 = 100 k . Assume that a transistor having a minimum hfe of 20 is used.

Solution

Referring to Fig. 16.71,

R2 –12 × 15 × 103 VB1 = – VBB _______ =______________ = – 1.56 V R2 + R3 115 × 103 Since VB1 is less than VBE (cut-off), i.e. 0.7 V for silicon transistor, Q1 is OFF. Therefore, IB 1 = 0 and IC 1 = 0 I2 = I4 + IC 2 I C 2 = I2 – I4

][

[

VCC – VC2 (sat) VC2 (sat) – (– VBB) = ____________ – _______________ RC2 R2 + R3

[

][

]

]

12 – 0.3 0.3 + 12 = ________3 – _________3 (Since Q2 is ON VC 2(sat) = 0.3 V) 2.2 × 10 115 × 10 = 5.35 mA IC2 5.35 × 10–3 IB 2 > ______ = __________ > 0.27 mA ª 0.5 mA 20 hfe (min) I1 = I3 + IC 1 = I3,

as IC 1 = 0

I3 = IB 2 + I6 VB2 – (– VBB) I6 = ____________ R4 VB 2 = VBE2(on) = 0.7 V Therefore,

0.7 + 12 I6 = _________3 = 0.127 mA 100 × 10 I3 = IB 2 + I6 = 0.5 + 0.397 = 0.627 mA

VC1 = VCC – I1 × RC1 = 12 – (0.627 × 10–3 × 2.2 × 103) = 10.62 V.

Design a collector coupled bistable multivibrator to operate from ± 5 V supply with IC (sat) = 2 mA and hfe = 70.

Solution

Refer to Fig. 16.72.

Given

VCC = ±5 V,

IC (sat) = 2 mA

and

hfe = 70.

We know that

VCC – VCE (sat) 5 – 0.2 RC1 = RC2 = ____________ = ______ = 2.4 kW IC (sat) 2 mA IC 2 × 10 – 3 IB = ___ = ________ = 28.6 mA 70 hfe VCC = + 5 V

RC 1 2.4 kW

Vo1

RC 2 2.4 kW

Pulse trigger D1

D2

C1

C1

R1

I1

15.5 kW

15.5 kW

R1

Vo2 Q2

IB Q1 R2 28.5 kW

R2 I2 28.5 kW VBB = – 5 V

VR2 = VBE1 – VBB = 0.7 – (– 5) = 5.7 V IC I2 = ___ = 200 mA 10 VR2 5.7 R2 = ____ = __________ = 28.5 kW I2 200 × 10 – 6

VCC – VBE 5 – 0.7 RC2 + R1 = _________ = _________________ = 17.9 k IB + I2 (200 + 28.6) × 10 – 6 Therefore,

R1 = 17.9 k

– 2.4 k

= 15.5 k

The triggering is used to induce a transition of the flip-flop from one state to the other. The triggering signal is either a pulse of short duration or a step voltage. There are two types of triggering namely unsymmetrical triggering and symmetrical triggering.

This method uses two triggering inputs. The triggering signal from the first input is applied to set the circuit in one particular state. The triggering signal from the second input is applied to reset the circuit to the opposite state. This process is called set-reset triggering. The unsymmetrical triggering is used in register and coding circuits. The unsymmetrical method of triggering a flip-flop with a diode is shown in Fig. 16.73. When Q1 is OFF, the drop across diode D is zero and hence D will transmit a negative going triggering pulse. When Q1 is ON, the diode D is reverse biased and hence D will not transmit a negative going triggering signal. When a negative __ going triggering pulse is applied to the set terminal S, Q1 will be ON and Q2 OFF so that Y = 1 and Y = 0. Similarly, when a negative__going triggering pulse is applied to the reset terminal R, Q1 will be OFF and Q2 ON, so that Y = 0 and Y = 1. Here the resistance R should be sufficiently large so that it must not load down the triggering input. At the same time, R should be small enough so that the charge accumulated during the pulse will have time to decay during the time between pulses. When the triggering rate is high, R may be replaced with a diode. Let us consider the triggering arrangement shown in dashed box in Fig. 16.73(a) when a level 1 signal is __ applied to the dc set terminal S , Q1 is ON and Q2 OFF, so that, Y = 1 and Y = 0. When the level 1 signal __ is applied to the d.c. reset terminal R , Q1 is OFF and Q2 ON, so that, Y = 0 and Y = 1. Another diode-triggering arrangement is shown in Fig. 16.73(b). Here R is connected to ground instead of the supply voltage. The negative triggering pulse is applied to the set terminal S that is applied to the base of the ON stage Q2 through diode D. If PNP transistors are used, the diodes in Figs 16.73(a) or (b) should be reversed and only the positive triggering signal is required for turning OFF the ON transistor.

In symmetrical triggering method, each successive triggering signal changes the state of the flip-flop. Symmetrical triggering is used in binary counting circuits. The circuits of symmetrical triggering through diodes at the outputs and inputs of the amplifiers are shown in Fig. 16.74. These circuits are symmetrical forms of the unsymmetrical circuits of Fig. 16.73, except that the resistor R has been replaced by D3. When Q2 is ON, the drop ( VCC) across RC reverse biases D2. At the same time, Q1 is OFF and hence there is zero voltage across RC of Q1 and D1 is at zero bias. When a negative going triggering pulse is applied, D1 conducts. Hence this triggering signal

VCC

RC – Y D

R S

C

C1 Y

( Pulse reset ) R

( Pulse set ) R1 Q2 ON

Q1 OFF R2

–VBB S’ (d.c. set)

R’ (d.c. reset)

(a) VCC

RC

C

D

C1 – Y

R1

Y

S R Q2 ON Q1 OFF

R2

S’

–VBB (b)

reaches the collector of Q1 and to the collector of the ON stage Q2 via the R1 C1 combination connecting the output of Q1 to the input of Q2, which will turn Q2 OFF. After the transition is over, D1 will be reverse biased and D2 will be at zero bias. The next negative triggering pulse will pass through D2 instead of D1. Hence these diodes D1 and D2 are called steering diodes. When the pulse rate is low, then D3 should be replaced by R.

Schmitt trigger is a wave shaping circuit, used for generation of a square wave from a sine wave input. It is a bistable circuit in which two transistor switches are connected regeneratively.

Figure 16.75 shows the circuit of a Schmitt trigger with the input and output waveforms. It consists of two identical transistors Q1 and Q2 coupled through an emitter resistor RE. Resistors R1 and R2 form a voltage divider across VC 1 and ground. This provides a small forward bias to the base–emitter junction of transistor Q2. When the supply is switched ON, with no input signal, transistor Q2 starts conducting. The rise in current (IE) of Q2 causes a voltage drop across RE, i.e. VRE = IERE. This voltage provides a reverse bias across the emitter–base junction of Q1 and it is driven into cut-off state. Since Q1 is in the OFF state, the voltage at its collector rises to VCC. Since the collector of Q1 is coupled to the base of Q2 through the resistor R1, the forward bias for the transistor Q2 is increased. Thus Q2 is driven into saturation. At this instant, the collector voltage levels are VC 1 = VCC and VC 2 = VCE(sat) + VRE. Consider an a.c. signal of sinusoidal or triangular variation applied to the base of Q1. When the voltage increases above zero, nothing will happen till it crosses the Upper Trigger Level (UTL). As the input voltage increases above UTL, i.e. Vin £ VRE + VBE1, Q1 conducts. The point at which Q1 starts conducting is known as Upper Trigger Point (UTP). As transistor Q1 conducts, its collector voltage falls below VCC. Since the collector of Q1 is coupled to base of Q2, the forward bias to Q2 is reduced. This in turn reduces the current of transistor Q2 and hence the voltage drop across RE. As a result, the reverse bias of transistor Q1 is reduced and it conducts more which drives Q2 to nearer to cut-off. This process continues till Q1 is driven into saturation and Q2 is cut-off. At this instant, the collector voltage levels are VC 1 = VCE(sat) + VRE and VC 2 = VCC. Transistor Q1 will continue to conduct till the input voltage crosses the Lower Trigger Level (LTL). When the input voltage becomes equal to LTL, the emitter–base junction of Q1 becomes reverse biased, i.e. Vin < VRE + VBE1. Hence its collector voltage starts rising towards VCC. This forward biases Q2 and it starts conducting. The point at which Q2 starts conducting is called Lower Trigger Point (LTP). Then Q2 is very quickly driven into saturation and Q1 is cut-off. At this instant the collector voltage levels are VC 1 = VCC and VC 2 = VCE(sat) + VRE. No change in state will occur during the negative half cycle of the input voltage. The difference between UTP and LTP is known as Hysteresis voltage (VH) as shown in Fig. 16.76. VH is also known as Dead zone of the Schmitt Trigger. The lagging of the lower threshold voltage from the upper threshold voltage is known as the Hysteresis. 1. Schmitt trigger is used for wave shaping circuits. 2. It can be used for generation of a rectangular waveforms with sharp edges from a sine wave or any other waveform.

+ VCC

lC2 = l E

l C1 + l1 C1

RC1 RB

l1

Vin

RC2 Vout

R1

lB2

Q1

Q2

l2

lE

RE

R2

(a) Vin

UTP LTP UTL

LTL

t

0 Vout

t

0 (b)

3. It can be used as a voltage comparator. 4. The hysteresis in Schmitt trigger is valuable when conditioning noisy signals for using digital circuits. The noise does not cause false triggering and so the output will be free from noise. 5. The hysteresis can be eliminated by keeping RC 1 = RC 2 in the circuit or by introducing another resistor between the two emitters. Reducing the hysteresis increases the rise and fall times of the output. This makes the triggering more sensitive to small noise fluctuations present in the input signal.

Vout E

C

D High state Low state

A

B

F

0

LTP

UTP

Vin

Design a Schmitt trigger circuit to have VCC = 12 V, UTP = 5 V, LTP = 3 V and IC = 2 mA, using two silicon NPN transistors with hFE(min) = 100 and I2 = 0.1 IC 2.

Solution

Referring to Fig. 16.75, UTP = VB 2 = 5 V

Voltage across RE is

VE = VB 2 – VBE = 5 – 0.7 = 4.3 V IE = IC = 2 mA VE 4.3 RE = ___ = _______ = 2.15 kW IE 2 × 10–3

Taking Q2 saturated,

VCE sat = 0.2 V typically. IC RC 2 = VCC – VE – VCE(sat) = 12 – 4.3 – 0.2 = 7.5 V C2

7.5 = _______ = 3.75 kW 2 × 10–3

I2 = 0.1 IC2 = 0.1 × 2 × 10–3 = 0.2 mA VB2 5 R2 = ____ = _________ = 25 kW I2 0.2 × 10–3 IC2 2 × 10–3 IB 2 = _______ = _______ = 20 mA 100 hFE (min) I1 = I2 + IB2 VCC – VB2 _________ = I1 = 0.2 × 10–3 + 20 × 10–6 RC1 + R1 12 – 5 ________ = 0.22 × 10–3 RC1 + R1

7 RC1 + R1 = __________ = 31.8 kW 0.22 × 10–3 When

Q1 is ON, Vi = LTP = VB2 = 3 V VB2 3 I1 = ____ = ________ = 0.12 mA R2 25 × 10–3 VB1 – VBE 3 – 0.7 IC1 = IE = _________ = _________3 = 1.07 mA RE 2.15 × 10 VCC = RC1 (IC1 + I1) + I1 (R1 + R2) 12 = RC1 (IC1 + I1) + I1 (31.8 × 103 – RC1 + R2) = RC1IC1 + I1 [31.8 × 103 + 25 × 103] 12 – 0.12 × 10–3 × 56.8 × 103 RC1 = _________________________ = 4.84 kW 1.07 × 10–3 R1 = (31.8 – 4.84) × 103 = 26.96 kW RB < hFERE hFERE 100 × 2.15 × 103 RB = ______ = _______________ = 21.5 kW 10 10

C

Vi

C

Ideal

Vi

Vo

Vi Ideal

Ideal 0

t

Vi

– 4V +

–15 V

R

Vo

(b)

Vi

10 V

0

–4 V

– 3V + (c)

(a)

C

+15 V

R

t

R

Vo

Circuits used to generate a single pulse or a train of pulses using regenerative feedback characteristics are called blocking oscillators. Time base generators are the circuits which provide an output waveform, a part of which is characterized by a linear variation of voltage or current with respect to time. This chapter deals with UJT saw tooth generator, pulse transformers, different types of blocking oscillators and voltage and current time base generators. Linearization techniques for the current time base generators are also discussed.

UJT is a three terminal semiconductor switching device. As it has only one PN junction and three leads, it is commonly called as Unijunction transistor. The basic structure of UJT is shown in Fig. 17.1(a). It consists of a lightly doped N-type Silicon bar with a heavily doped P-type material alloyed to its one side closer to B2 for producing single PN junction. The circuit symbol of UJT is shown in Fig. 17.1(b). Here the emitter leg is drawn at an angle to the vertical and the arrow indicates the direction of the conventional current. Referring to Fig. 17.1(c), the interbase resistance between B2 and B1 of the silicon bar is RBB = RB1 + RB2. With emitter terminal open, if voltage VBB is applied between the two bases, a voltage gradient is established along the N-type bar. The voltage drop across RB1 is given by V1 = hVBB, where the intrinsic stand-off ratio h = RB1/(RB1 + RB2). The typical value of h ranges from 0.56 to 0.75. This voltage V1 reverse biases the PN junction and emitter current is cut-off. But a small leakage current flows from B2 to emitter due to minority carriers. If a positive voltage VE is applied to the emitter, the PN junction will remain reverse biased so long as VE is less than V1. If VE exceeds V1 by the cut-in voltage Vg , the diode becomes forward biased. Under this condition, holes are injected into N-type bar. These holes are repelled by the terminal B2 and are attracted by the terminal B1. Accumulation of holes in E to B1 region reduces the resistance in this section and hence emitter current IE is increased and is limited by VE. The device is now in the ‘ON’ state.

Base 2 (B2)

B2 B2

Emitter (E)

+

P

RB2 E

E +

N

VE –

Base 1 (B1)

B1

(a)

(b)

VBB D

V1

RB1

–

B1

(c)

If a negative voltage is applied to the emitter, PN junction remains reverse biased and the emitter current is cut-off. The device is now in the ‘OFF’ state. Figure 17.2 shows a family of input characteristics of UJT. Here, up to the peak point P, the diode is reverse biased and hence, the region to the left of the peak point is called cut-off region. The UJT has a stable firing voltage VP which depends linearly on VBB and a small firing current IP ( 25 A). At P, the peak voltage VP = VBB + V , Negative VE the diode starts conducting and holes are resistance injected into N-layer. Hence, resistance region decreases thereby decreasing VE for the (P) Peak point VP increase in IE. So, there is a negative Saturation resistance region from peak point P to region valley point V. After the valley point, the device is driven into saturation and behaves like a conventional forward (V) Valley point VV biased PN junction diode. The region Cut-off lB2 = 0 to the right of the valley point is called region saturation region. In the valley point, lE lP lV the resistance changes from negative to positive. The resistance remains positive Leakage in the saturation region. For very large current IE, the characteristic asymptotically approaches the curve for IB2 = 0. A unique characteristic of UJT is, when it is triggered, the emitter current increases regeneratively until it is limited by emitter power supply. Due to this negative resistance property, a UJT can be employed in a variety of applications, viz. sawtooth wave generator, pulse generator, switching, timing and phase control circuits. The relaxation oscillator using UJT which is meant for generating sawtooth waveform is shown in Fig. 17.3. It consists of a UJT and a capacitor CE which is charged through RE as the supply voltage VBB is switched ON.

+ VBB

Ve VP

R2 RE V0 Output

CE

Vv E

B2

VB2

B1

VB1

O

Time

T1T2

T3T4

T5T6

T1T2

T3T4

T5T6

T1T2

T3T4

T5T6

VEE Ve

R1

VB2 O

Time

VB1 O

Time

The voltage across the capacitor increases exponentially and when the capacitor voltage reaches the peak point voltage VP, the UJT starts conducting and the capacitor voltage is discharged rapidly through EB1 and R1. After the peak point voltage of UJT is reached, it provides negative resistance to the discharge path which is useful in the working of the relaxation oscillator. As the capacitor voltage reaches zero, the device then cuts off and capacitor CE starts to charge again. This cycle is repeated continuously generating a sawtooth waveform across CE. The inclusion of external resistors R2 and R1 in series with B2 and B1 provides spike waveforms. When the UJT fires, the sudden surge of current through B1 causes drop across R1, which provides positive going spikes. Also, at the time of firing, fall of VEBI causes I2 to increase rapidly which generates negative going spikes across R2. By changing the values of capacitance CE or resistance RE, frequency of the output waveform can be changed as desired, since these values control the time constant RE CE of the capacitor charging circuit. The time period and hence the frequency of the sawtooth wave can be calculated as follows. Assuming that the capacitor is initially uncharged, the voltage VC across the capacitor prior to breakdown is given by VC = VBB (1 – e – t/RE CE) where RE CE = charging time constant of resistor-capacitor circuit, and t = time from the commencement of the waveform. The discharge of the capacitor occurs when VC is equal to the peak-point voltage VP, i.e. VP = hVBB = VBB (1 – e – t/RE CE) h = 1 – e– t/RE CE e– t/RE CE = (1 – h)

1 t = RE CE loge ______ (1 – h)

Therefore,

1 = 2.303 RE CE log10 ______ (1 – h) If the discharge time of the capacitor is neglected, then t = T, the period of the wave. Therefore, frequency of oscillation of sawtooth wave, 1 1 fo = __ = ______________________ T 1 2.303 RE CE log10 ______ (1 – h)

Design a UJT relaxation oscillator to generate a sawtooth waveform at a frequency of 500 Hz. Assume the supply voltage VBB = 20 V, VP = 2.9 V, VV = 1.118 V, IP = 1.6 mA and IV = 3.5 mA.

Solution

We know that 1 fo = ______________________ 1 2.303 RE CE log10 ______ (1 – h)

We know that hmin = 0.56 For determining RE, we have VBB – VP 20 – 2.9 RE < ________ , i.e. RE < _________ = 10.7 kW IP 1.6 × 10 – 3 VBB – VV 20 – 1.118 RE > ________, i.e. RE > _________ = 5.36 kW IV 3.5 × 10 – 3 Therefore, RE is selected as 10 kW.

(

1 1 ____ = 2.303 × 10 × 103 CE log10 _________ 500 (1 – 0.56) Therefore,

1 CE = _____________________ = 0.24 mF 500 × 2.303 × 104 × 0.36

So, CE is selected as 0.22 mF. Let the required pulse voltage at B1 = 5 V Let the peak pulse current,

IE = 250 mA.

Therefore,

VR1 5 R1 = ____ = _________ = 20 W IE 250 × 10–3

So, R1 is selected to be 22 W. We select the voltage characteristics for VB1B2 = 4 V.

)

Therefore,

VR2 = 20 – (4 + 5) = 11 V 11 R2 = ____ × 103 = 44 W 250

So, R2 is selected as 100 W.

A UJT has a firing potential of 20 V. It is connected across the capacitor of a series circuit with R = 100 kW and C = 1000 pF supplied by a source of 40 V d.c. Calculate the time period of the sawtooth waveform generated.

Solution

Given, RE = 100 kW and CE = 1000 pF VBB = 40 V, VP = 20 V

(

–t _____

VP = VBB 1– e RECE

(

–t _____

20 = 40 1 – e RECE

)

)

1 e–t/RECE = __ 2 –t 1 _____ = ln __ RECE 2 t _____ = ln (2) RECE t = ln (2) × RECE Therefore, t = 0.693 × 100 × 103 × 1000 × 10 – 12 = 0.693 × 10 – 4 = 69.3 ms

This section deals with the analysis of linear wave shaping of a step or pulse waveform when it is passed through a transformer. It is important to obtain an equivalent circuit of the pulse transformer for the calculations of distortions present in the output. In order to analyze it, the equivalent circuit of the pulse transformer has been presented. The pulse waveform is divided into three parts; leading edge, flat top and trailing edge, and they are also analyzed individually. M

The schematic diagram of a transformer is shown in Fig. 17.4, in which the effective resistances and the capacitances are neglected. If Lp is the primary inductance, Ls is the secondary inductance and M is the mutual inductance, the coefficient of coupling K between primary and secondary can be defined by M ______ K = _______ L ÷ p ◊ Ls

(17.1)

+ +

Vi

iP

Lp

Ls

is

RL Vo

– –

The mesh equation for Fig. 17.4 is written as dip dis Vi = Lp___ – M ___ dt dt dip dis Vo = M ___ – Ls ___ dt dt Vo = isRL

(17.2) (17.3) (17.4)

Substituting Eq. (17.4) into Eq. (17.3), we get dip dis isRL = M ___ – Ls ___ dt dt This equation can be expressed as dip dis 0 = –M ___ + Ls ___ + isRL (17.5) dt dt We know that for ideal transformer, the output Vo is an exact replica of the input Vi and the transformation ratio n is independent of the load. Therefore, ___ ip Vo __ Ls N s ___ = = ___ = ___ = n (17.6) i Vi Lp Np s

÷

where ip is primary current, is is secondary current, Np is number of primary turns and Ns is number of secondary turns. s1

Pulse transformer behaves as an ideal transformer when used in connection with the fast waveforms it is intended to handle. The equivalent circuit shown in Fig. 17.5 includes an ideal transformer in cascade with the configuration of inductors. Now, the load resistance RL is reflected to the primary side and appear as resistance of a2RL, where (1/a) = n). This is shown in Fig. 17.6. s1

+ Vi –

s2

+ + Vi

RL is a

ip

–

L

is T

Vo –

s2 2

ip

1:1/a

l

L

is a

+

a RL a . Vo ll –

To get the values of the parameters s1, s2 and L in terms of a, Lp, Ls, and M, we have to find the mesh equation of Fig. 17.6.

Applying KVL to the loop I, we get

is d __ dip dip a Vi = s1 ___ + L ___ – L _____ dt dt dt dip L dis ___ Vi = (s1 + L) ___ – __ dt a dt Applying KVL to the loop II, we get is is d __ d __ dip is a a L _____ – L ___ + s2 _____ + a2 RL __ a =0 dt dt dt

( )

( )

( )

( )

dip s2 dis L ___ 0 = – L ___ + __ + a ___ + aRLis a dt dt Dividing Eq. (17.8) by ‘a’ on both sides, we get dip dis s2 ___ L ___ L ___ ___ 0 = – __ a dt + a2 + a2 dt + RLis dip dis L + s2 ___ L ___ ______ 0 = – __ + RLis 2 a dt + dt a

(

)

(

(

)

L Lp = (s1 + L) and M = __ a Comparing Eq. (17.5) with Eq. (17.9), we get L + s2 Ls = ______ a2 (or) L = Ma, Lp = s1 + Ma

Ma + s2 and Ls = ________ a2

L = Ma, s1 = Lp – Ma

and s2 = a2Ls – Ma

For different values of a, the values of L, a1 and s2 are calculated as follows. ___

÷

Lp a = ___ Ls

We know that

L = Ma

since

_____ M _____ , L = ( K LpLs ) K = ______ ÷ ÷Lp Ls

___

(÷ )

L ___p = KL p Ls

a1 = Lp – Ma = Lp – L = Lp – KLp = Lp[1 – K ] Then,

s2 = a2Ls – aM

(17.8)

)

Comparing Eq. (17.2) with Eq. (17.7), we get

For

(17.7)

(17.9)

( )

Lp = ___ Ls – KLp = Lp (1 – K ) Ls The calculated parameters L, s1 and s2 are substituted in Fig. 17.6 and its modified diagram is shown in Fig. 17.7. ___

For

s1 = Lp(1 – K) s2 = Lp(1 – K)

( )÷

L ___p Ls

1 a = __ K

+ Vi –

L = aM ___

÷

_____ 1 Lp = __ ___ × K ÷LpLs = Lp K Ls

Therefore,

2

is a

ip

+

a RL a . Vo

L = KLp

–

÷

s1 = Lp – Ma = Lp – L = Lp – Lp = 0 s2 = a2LS – Ma

[ ]

1 Lp = ___2 ___ × Ls – Lp K Ls Lp 1 = ___2 – Lp = Lp ___2 – 1 K K

(

)

The calculated parameters L, s1 and s2 are substituted in Fig. 17.6 and its modified diagram is shown in Fig. 17.8.

(

1 s2 = Lp ___ – 1 K2

a RL

L = Lp

+ a . Vo –

_____

For a = K ÷Lp/Ls We know that L = aM

_____

2

+ Vi –

)

s2

s1 = 0

_____

÷

= K ÷Lp/Ls × K ÷LpLs = K2Lp s1 = Lp – Ma = Lp – K2Lp = Lp(1 – K2) s2 = a2Ls – Ma

( )

Lp = K2 ___ Ls – K2Lp = 0 Ls The calculated parameters L, s1 and s2 are substituted in Fig. 17.6 and its modified diagram is shown in Fig. 17.9.

2

s1 = Lp(1–K )

s2 = 0

Vi

+

2

+

a RL

2

L = K Lp

a . Vo

– –

÷ In earlier discussion, we have neglected the effective capacitances and resistances associated with a transformer, which is incomplete. Now, we shall introduce these neglected parameters, as shown in Fig. 17.10.

R1

s +

+ Vi –

L

C

R2

Vo n

In a transformer, the voltage decreases linearly with – distance along the winding. Similarly, an electric field exists in the space between the windings, and thereby the electrostatic energy is stored. The circuit element that stores energy electrostatically is a capacitor. Therefore, the transformer capacitance is taken into account by introducing a shunt capacitor C, which is connected on the load side of the leakage inductance. We have also included the resistor R1, which represents the sum of the primary winding and the generator resistance. Similarly, at the load side, an equivalent load resistance R2 is included, which is the combination of the load resistance RL and the secondary winding resistance R2¢, so that RL + R¢2 R2 = _______ n2

(17.10)

For the equivalent circuit of Fig. 17.9, it is clear that the magnetizing inductance is simply the primary winding inductance L = K2Lp. In other words, the magnetizing inductance is the inductance presented at the input terminals when the secondary is open circuited. Similarly, the leakage inductance s is the inductance presented at the terminals of the primary when the secondary is short circuited.

In general, a pulse shown in Fig. 17.11 will have three phases such as (a) Leading edge, (b) Flat top, and (c) Trailing edge. Amplitude

When the pulse is transferred through a pulse transformer, the responses of all the phases are not similar. The variation is predominantly depending upon the phases of a pulse. Therefore, the responses of all the individual phases are analyzed and combined at different frequencies.

Flat top Leading edge

Trailing edge Time

At the leading edge of a pulse, the signal frequency will be large, as the frequency is reciprocal of time. This large frequency results in very high impedance for

(

)

1 magnetizing inductance (XL = w L), and low impedance for shunt capacitance Xc = ___ . Since both wC are in parallel, the magnetizing inductance can be ignored at high frequencies. Therefore, the resultant circuit is shown in Fig. 17.12.

R1

s +

+

Let the Laplace transform of input pulse vi (t) be Vi (s) and the Laplace transform of out-

C

vi (t ) = Vu (t )

R2

vo n –

–

vo (t) V o (s) _____ put _____ n is n . The response of Fig. 17.12 on s-domain can be written by using the voltage divider rule, 1 ___ R Cs 2 ________ 1 R2 + ___ Vo (s) __________________ Cs _____ Vi (s) n = 1 ___ R2 Cs R1+ s ◊ s + ________ 1 R2 + ___ Cs Then, 1 ___ Vo (s) ____________________________ Cs _____ n = _____ R1 ____ R1 + R2 1 1 _______ ___ ___ 2 Vi (s) s + s + CR s + Cs R

(

2

)

(17.11)

2

Let us introduce the amplification factor a, the period T, and the damping constant d, which are defined by R2 a = _______ R1 + R2 ______

T = 2p ÷s ◊ Ca

(

Substituting back, we get

)

R1 ____ 1 ___ T d = ___ s + CR2 4p

[

(17.12)

s 2p 2 __ ___ V (s) s T o _____ = a __________________ n _____ 2p 2p 2 s2 + 2d ___ s + ___ Vi (s) T T

( )(

)

( )

]

(17.13)

Therefore, the characteristic equation of the system is 2p 2 2p s2 + 2d ___ s + ___ = 0 T T The roots of the above equation are given below,

( )

_______

2p 2p s1, s2 = – ___ d ± j ___ ÷(1 – d2) T T The final response of a transformer for a step signal is

[

(17.14)

]

2p 2 ___ v_____ (t) T V V o __________________ –1 ◊ __ , since L [Vu (t)] = __ n =L a 2 s 2p 2p 2 s ___ ___ s + 2d s+ T T

( )

( )

( )

______ 2p vo (t) ___ 2p 1 _____ _______ _____ e– T d ◊ t sin F + ___ ÷(1 – d2 ) ◊ t n = Va 1 – T ÷1 – d2

[

F = tan–1

where

(

(

_______

÷(1 – d2) ________ d

)]

(17.15)

)

Though there are many responses of transformations such as over damped, critically damped, under damped and un-damped oscillations, under-damped, i.e. d < 1, is the most suitable choice for leading edge of a pulse waveform. The overall leading edge response of a pulse transformer is shown in Fig. 17.13. y 2.0 1.8 1.6 1.4 1.2

d = 0.2 0.4 0.6

1.0 0.8

d=1

0.6

2

0.4

4

0.2 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0

(

pd _____ – _______

x

)

It is observed that for d = 0.6, the overshoot is 6% i.e. 100e ÷1 – d2 , and the rise time tr = 0.27 T. In contrary, the flat top of a pulse is of low frequency. Therefore, the impedance of a shunt capacitance is very large, whereas that of magnetizing inductance

is low. Then, the shunt capacitance can be ignored. Similarly, as R1 >> ws, leakage inductance is also ignored. Hence, the effective equivalent circuit for low frequency is shown in Fig. 17.14.

R1 + +

R2

vi (t ) = Vu(t ) –

Let the Laplace transform of input pulse vi (t) be Vi (s) and the Laplace transform of output v_____ V o (t) o (s) _____ n be n . The response of Fig. 17.14 in s-domain can be written by using voltage divider rule,

L

Vo n –

R2Ls _______ Vo (s) ____________ R2 + Ls _____ Vi (s) n = R2Ls R1 + _______ R2 + Ls

Then,

R2Ls _______ Vo (s) _____ R n 2 + Ls ______ = ____________ R2Ls Vi (s) R1 + _______ R2 + Ls Vo (s) _____ R2 n s ______ = _______ _____________ R1 + R2 Vi (s) 1 R1R2 s + __ _______ L R1 + R2

(

Letting

R1R2 _______ = R and R1 + R2

)

(17.16)

R2 a = _______, R1 + R2

Vo (s) _____ n s ______ = a _____ R Vi (s) s + __ L

(17.17) Vu(t)

V is __ s where V is the amplitude of the step input. Vo (s) s _____ _____ V (s) n =a× R i s + __ L V __ Substituting Vi (s) = s in the above equation, we get Vo (s) V s __ _____ _____ n =a s R s + __ L Taking inverse Laplace transform on both sides

[

]

Vo (s) 1 L – 1 _____ = aVL – 1 _____ n R s + __ L

[ ]

R vo (t) – __t _____ n = aVe L R vo (t) – __ t y(t) = _____ = e L naV

(17.18)

R 2 R 3 R __ __ __ t t t L L L = 1 – ___ + ______ – ______ + ... 1! 2! 3!

( ) ( )

R When __ t tp is y(t) – y(t – tp). The response of a trailing edge with overall response of a transformer is shown in Fig. 17.15. y 1.4 1.2

Input pulse

1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4

1

2

3

4

5

6

t, m sec –0.071

Pulse transformer can be used to (i) change the amplitude and impedance level of a pulse. (ii) invert the polarity of a pulse. (iii) produce a pulse in a circuit having negligible d.c. resistance. (iv) affect d.c. isolation between source and load. (v) couple between stages of pulse amplifiers. (vi) differentiate a pulse. (vii) act as a coupling element in certain pulse generating circuits.

Sharp triggering pulses are usually obtained by differenting the output of some form of the multivibrator. The rise times of the pulses so derived will be in the range 2–10 s and the output frequencies range from 10–100 Hz. The blocking oscillator produces sharp pulses in the range 1 kHz to more than 1 MHz. It is a tuned collector oscillator with a positive feedback arrangement via a pulse transformer. The oscillator cuts itself OFF or BLOCKS after one or more cycles. Hence the name Blocking oscillator. It can be free running or driven like a monostable multivibrator.

+VCC Figure 17.16 shows the circuit of a free running BJT blocking oscillaT tor. When the supply is switched ON, the base voltage increases rapidly. When this voltage becomes greater D L1 L2 than VBE, the collector current (IC) C2 increases. The increase in IC through R1 Output the winding L1, induces a voltage in C1 winding L2 of the pulse transformer. Q Hence, the base–emitter junction of R R2 3 the transistor is more forward biased and thus conducts more. As a result, IC further increases. Because of the regenerative action, the transistor is driven into saturation. At this state, IC is maximum and it cannot further increase. Therefore, the rate of change of flux in winding L1 becomes zero (dIC /dt = 0) and hence, no induced voltage is produced in winding L2. Due to this, the base current (Ib) drops, thereby reducing Ic. Also, capacitor C1, which had charged earlier, provides a negative voltage to the base of the transistor and reverse biases its base–emitter junction and ultimately the transistor is driven into cut-off.

The transistor remains at cut-off as the charge on capacitor C1 leaks away through resistor R3. When the capacitor discharges a sufficient amount of charge, the reverse bias of the transistor decreases and forward bias increases due to which the transistor starts conducting again. Like this, the entire cycle of operation is repeated. The output waveform of the narrow and short pulses generated by the circuit are also shown in Fig.17.16.

The waveforms for the free running blocking oscillator are shown in Fig. 17.17. At the end of the pulse, the magnetizing current im is expressed by vC VCC

Vg t=0 t

V

(a)

QOFF

QON vB nV

nVg

Vg Q

t

(b)

im lm

lo 0

tp

tf T

t

ta

(c)

T

VCC tp im = ______ __ = Io (n + 1) L When RL = •, we have VCC n Io = ______ ____ (n + 1) R From this equation, it is understood that the peak magnetizing current is independent of the inductance L. When t = tp, the transistor Q is turned OFF and im will flow through the diode and transformer capacitor C as shown in Fig. 17.18(a). Here, since the diode forward resistance rf is negligibly small, the diode cutin voltage Vg appears directly across L and C. Hence the collector voltage increases above VCC by Vg as shown in Fig. 17.18. When t > tp, we have dim L ___ = –Vg dt

– Vg t im = _____ + Io L

Therefore,

After the pulse ends, the current decreases linearly with time as shown in Fig. 17.17(c). The diode current falls to zero at a time tf expressed by LIo n L VCC tf = ___ = ______ __ ____ Vg (n + 1) R Vg VCC

When Im = 0, rf = • and hence the under damped

VCC

ringing circuit results as shown in Fig.17.18(b). As C is initially charged to Vg , a sinusoidal oscillation of

–

___

amplitude Vg and period 2p ÷LC begins, as indicated by the dashed curve in Fig.17.17(a). The collector voltage VC falls below VCC after one quarter of a cycle, i.e.,

+

L

im

Vg

L

C

C

rf ª 0

___

ta = 15.7 ÷LC

and hence there will be an equal positive swing at the base.

Collector (a)

(b)

When vBE >> Vg , the cut-in voltage of the transistor, the transistor Q is turned ON again without an external trigger. The diode makes the circuit to function in an astable mode with period T = tp + tf + ta. The advantages of the diode controlled blocking oscillator are: 1. As there is no overshoot at the end of the pulse, the voltage waveforms at collector and base are nearly rectangular. 2. Since the design equations are simpler, the synthesis of the circuit is easier to meet the desired specifications. 3. There is much less possibility that the oscillations pretending the pulse appear. The disadvantages of this circuit are: 1 1. It is impossible to achieve the stable operation below tp /tf ª ___. 20 2. For a given pulse duration tp, tf can be changed only by changing the diode cutin voltage Vg or the supply voltage VCC.

Another form of astable blocking oscillator is obtained with the inclusion of R1C1 network in the emitter circuit of a monostable blocking oscillator as shown in Fig. 17.19(a) or in the base circuit as shown in Fig. 17.19(b).

VCC

VCC

n : 1 : n1

n : 1 : n1 RL

RL

Q

VBB

Q

R R1

R

C1 + C1v1 –

R1

(a)

(b)

The waveform across R1C1 network and the collector waveform are shown in Figs 17.19(a) and (b) respectively. Referring to Fig. 17.19(a), let us assume initially that the voltage V1 on C1 is larger than (VBB – Vg ), where Vg is the cut in base-to-emitter voltage. Therefore, the transistor is now OFF and C1 discharges exponentially to ground with a time constant R1C1. When v1 = (VBB – Vg ), the base starts to draw current, as does the collector, and the regenerative action starts. The collector and base waveforms are similar to those in Fig. 17.24. For the period tp during which the transistor Q is ON, the capacitor C recharges and reaches the peak capacitor voltage V1. Then the transistor is OFF for a period tf, during which C1 discharges to the voltage at which the transistor is turned ON again. From Fig. 17.20(a), we get v1 V1 VBB – Vg 0

tp

tf

(a)

t

T

vC VCC

V (b)

0

t

V1 tf = R1C1 ln ________ VBB – Vg The total period of the free running oscillations is T = tp + tf t n21 n –tp/R C1 __p – __ e = – ___ L R RL If tp /RC1 > Vg Q, and R1 and C1 are independent of temperature.

t

The main disadvantage of this circuit is that the oscillations preceding the collector pulse appear when the transistor comes out of cut-off very gradually as shown in Fig. 17.21 Also a small change in voltage V1 will produce a large change in tf, which results in instability from cycle to cycle. 2

nL n1 L In the previous section, while deriving for tp ª ___ – ____, we have assumed that the magnetizing inducR RL tance L is a constant. Now let us assume that the core saturates when the flux density (B) of the core of the transformer reaches a maximum value Bm. Because of the core saturation, the inductance L decreases with current and L Æ 0 as B Æ Bm. Then, the collector current iC increases very quickly and base current iB rapidly decreases toward zero. Therefore the pulse ends when the maximum flux density is reached. Letting that N be the number of turns in collector winding, A be the cross sectional area of the core and f be the magnetic flux, the voltage across the collector winding becomes a constant as given by VCC df dB V = N ___ = NA ___ = _____ dt n + 1 dt

Integrating between the limit 0 and tp for t, with respect to the corresponding variation from 0 to Bm for B in the above equation, we get (n + 1) NABm tp = ____________ VCC From this, it is clear that the pulse duration, tp, depends on the core properties and supply voltage VCC but not on the transistor parameters. Thus the core saturation controls the pulse duration and hence the frequency of a blocking oscillator.

The circuit of a triggered monostable blocking oscillator is shown in Fig. 17.22(a). A slowly varying input voltage may be used to trigger the circuit. The width of the triggering pulse may lie in the range from nanosec to microsec, depending upon the parameters of the pulse transformer and the circuit. The transformer has n times as many turns in the base circuit as in the collector circuit and is connected into the circuit so as to provide polarity inversion as indicated by the dots on the windings. Resistor R connected in series with the base of the transistor controls the pulse duration. The transistor is OFF in the quiescent state. VBB of less than one volt is applied to the circuit to avoid triggering by noise pulses and to prevent free running operations at elevated temperatures. On application of the triggering pulse to the collector, the collector voltage gets reduced. By transformer action and with the winding polarities indicated in Fig. 17.22(a), the base potential gets increased and the transistor starts to draw current. With increase in collector current, the collector voltage is further lowered, which in turn raises the base voltage. If the a.c. loop gain exceeds unity, regeneration takes place and the transistor is quickly driven into saturation. The transistor will be in ON state for a period of tp. The pulse duration tp can be determined with the help of the equivalent circuit during the pulse formation shown in Fig. 17.22(b). In an ideal transformer, the sum of the ampere-turns is constant and the induced voltages are proportional to the turns. From the figure, i = niB and V = VCC where

i = current of collector circuit iB = current of base circuit V = voltage of collector circuit nV = voltage of base circuit.

From the base circuit,

Therefore,

nV nVCC iB = ___ = _____ R R n2VCC i = niB = ______ R

VCC ic n:1 2

n VCC R

C

hFEiB 0

t

t = tp

t=0 (c)

iB nVCC R

B R

E 0

t

tp

–VBB ª 0

(d) (a) Ideal transformer

n:1

–

+

iC i

nV +

im

L

iB iC B

E

C

(b)

Since im is a magnetising current and V is constant,

Since

+ –

R

Integrating, we get

V

dim L ___ = V dt Vt im = ___ L iC = i + im, n2 VCC VCC t iC = ______ + _____ R L

VCC –

At

n2VCC nVCC iC = ______ and iB = _____ R R

t = 0+,

VCC tp n2VCC ______ ______ At t = tp, iC = + R L When the transistor comes out of saturation, then the pulse width tp can be determined by the condition, iC = hFE iB Therefore,

VCC tp n2VCC ______ nVCC ______ + = hFE _____ R L R

nL tp = ___ (hFE – n) R Since hFE is larger than n, the above equation reduces to nLhFE tp = ______ R Simplifying, we get

Figures 17.22(c) and (d) show the collector current and the base current of the triggered blocking oscillator, respectively. Over the duration tp, the base current remains constant and the collector current linearly increases with time. At the end of the pulse duration, VCE increases rapidly and this decreases the transformer voltage and hence the base current. At this point, the transistor comes out of saturation. As the loop gain exceeds unity in the active region, the transistor is quickly driven to cut-off by regenerative action. As shown in Fig. 17.22(d), at t = tp, current iB returns to zero and remains at this level. Due to minority carriers stored in the base, there may be an undershoot as indicated by the dashed curve.

The transformer used is a pulse transformer with three windings. One winding is in the base circuit with n turns and another is in the collector circuit. The third winding is in the collector and it feeds the load resistor. The base and collector turns must be connected for regenerative feedback. If a triggering signal is momentarily applied to the collector to lower its potential, the base potential increases. Therefore, regeneration takes place. Pulse transformer is replaced with an ideal transformer, in shunt with the magnetizing inductance L of the collector winding as shown in Fig. 17.23. Considering the mesh on collector to base loop, VCC = V + nV = V(n + 1) where V is the drop across the collector winding during a pulse. VCC Therefore, V = _____ n+1 The drop VEN across R is given by VEN = nV = (iC + iB) R

Ideal transformer

VCC n : 1 : n1

i1

+

vL

RL

RL

n:1:n

+ n1 V = vL –

–

B

– i nV B +

E

i

ic VCC

B

C iC + iB

R

–VBB ª 0

N

(a)

We know that,

+

L V –

iC

iB

R

im

(b)

nVCC nV – iE = iC + iB = ___ = ________ R (n + 1) R

(17.20)

From the above equation, we can say emitter current is constant. We know that the sum of ampereturns in an ideal transformer is zero. i.e., (17.21) i – niB + n1i1 = 0 n V 1 From load circuit, i1 = – ____ RL Vt (17.22) i = iC – im = iC – ___ L where ‘i’ is the current through winding in collector. Substituting Eq. (17.22) in Eq. (17.21), we get Vt iC – ___ – niB + n1i1 = 0 L n21 V Vt iC – ___ – niB – ____ = 0 L RL

(17.23)

Rearranging Eq. (17.23), we can write iC – niB =

VCC t (n 1) L

VCC (n 1)

n12 RL

(17.24)

Subtracting Eq. (17.24) from Eq. (17.20), we obtain (n + 1)iB =

VCC n (n 1) R

VCC t (n 1) L

VCC (n 1)

n12 RL

The above equation can be arranged as (n + 1)iB =

n12 RL

VCC n (n 1) R

[

t L

2 VCC n n1 t iB = _______2 __ – ___ – __ (n + 1) R RL L

Therefore,

]

(17.25)

Substituting Eq. (17.25) in Eq. (17.20), we get

(

2 VCC n2 n1 t iC = _______2 __ + ___ + __ (n + 1) R RL L

)

We can observe that, base current waveform is trapezoidal with negative slope and collector current waveform is also trapezoidal with positive slope. Emitter current is constant during the pulse. The waveforms are shown in Fig. 17.24. 1. The blocking oscillator can be used as a frequency divider or counter. vCN

ic

VCC

hFElB 0

(d)

0

t

t

vBN

iB

nV

lB 0

–iE =

V

(a)

X

0

t

t

vL

nV R

vEN R

(e)

(b)

n1V (c) 0

0

tp

t

(f) 0 0

tp

t

2. The blocking oscillator as a low impedance switch can be used to discharge a capacitor quickly. 3. The output of the blocking oscillator can be used as a gating waveform with a very small mark– space ratio. 4. Blocking oscillator is capable of generating a pulse of large peak power. The average power is small since the duty cycle is low. 5. The astable circuit is used as a master oscillator to supply triggers for synchronising a system of pulse type waveforms-square waves, sweep voltages, etc. 6. The monostable circuit is used to obtain abrupt pulses from a slowly varying input triggering voltage. 7. Using a tertiary winding, output pulses of either polarity may be obtained depending upon which end of the winding is grounded. Also, the output winding may be isolated from ground where required.

A linear time base generator is one that provides an output waveform, a portion of which exhibits a linear variation of voltage or current with time.

The voltage–time base circuit finds a major application in CRO. Among several methods to achieve sweep linearity, the Miller circuit and Bootstrap circuit are commonly used. In the Miller circuit, an operational integrator is used to convert a step into a ramp waveform. In the Bootstrap circuit, a constant current is approximated by maintaining nearly constant voltage across a fixed resistor is series with a capacitor. Figure 17.25(a) shows the circuit of a Miller integrator or a sweep circuit. Transistor Q1 acts as a switch and transistor Q2 is a common-emitter amplifier, i.e. a high gain amplifier. Consider the case when Q1 is ON and Q2 is OFF. At this condition, the voltage across the capacitor C and the output voltage Vo is equal to VCC. When a negative pulse is applied to the base of Q1, the emitter–base junction of Q1 is reverse biased and hence Q1 is turned OFF. Thus, the collector voltage (VC1) of Q1 increases which increases the bias to Q2 and as a result Q2 is turned ON. Since Q2 conducts, Vout begins to decrease. Because the capacitor is coupled to the base of transistor Q2, the rate of decrease of output voltage is controlled by rate of discharge of capacitor. The time constant of the discharge is given by td = RB2C. As the value of time constant is very large, the discharge current practically remains constant. Hence, the run down of the collector voltage is linear. When the input pulse is removed, Q1 turns ON and Q2 turns OFF. The capacitor charges quickly to +VCC through Rc with the time constant tc = RcC. The waveforms are shown in Fig. 17.25(b). The bootstrap circuit illustrated in Fig. 17.26(a) is a commonly used method for achieving a constant charging current. Here, transistor Q1 acts as a switch and Q2 as an emitter follower which is connected across capacitor C. Therefore, the output voltage Vo will be approximately equal to the voltage across C. The transistor, therefore, provides a low resistance output terminal for the sawtooth generator.

0

t Ts

+VCC

Vout

RC

RB2

C Vout

Vin

Vin

VCC

Q2

RB1 Q1

t Ts (a)

Tr

(b)

Initially, Q1 is ON and Q2 is OFF. Hence, C1 is charged to the supply voltage VCC through diode D and the output voltage Vo is zero. When a negative pulse, as shown in Fig. 17.26(b), is applied to the base of Q1, Q1 is turned OFF. Now, capacitor C1 discharges and capacitor C starts charging through resistor R. As a result, the base voltage of Q2 and Vo start increasing from zero volts. Therefore, diode D becomes reverse biased. The value of capacitor C1 is much larger than that of capacitor C. The voltage across R remains substantially constant throughout the charging process and thus the charging current (iR) is maintained constant. So, capacitor C is charged with a constant current which causes the voltage across C, i.e. the output voltage Vo to increase linearly with time with the relation. VCC t Vo = _____ RC When the negative pulse at the input is removed, C discharges through Q1 and Vo reduces to zero. Then capacitor C1 again charges to the supply voltage VCC through diode D. The bootstrap sweep circuit is called so because the circuit itself pulls up by its own bootstrap.

The current–time base circuit finds wide application in Television and Radar displays. A simple current– time base circuit and gating waveforms are shown in Fig. 17.27. The transistor is initially in the OFF state. At time t = 0, current iL through the coil of inductance L is zero. When an input gating pulse of width tp with a voltage vi is applied, current iL increases linearly with time during the pulse interval of tp. The linear variation of iL is given by, VCC iL = ____ t L

R1

R

C1

Input voltage (Vi)

D

Time (t )

0

+VCC

iR

Ts

Q2 Vi

RE

C R2

Vo

Output voltage (Vo)

Q1

0

Time (t )

(a)

(b)

During this sweep interval, diode D does not conduct since it is reverse biased. The sweep terminates at t = tp, when the gating signal drives the transistor to cut-off. Then iL continues to flow through D and RD until it decays exponentially to zero. During the discharge period, the current through the inductor, iL, decreases exponentially as given by, iL = IL e– RD (t – tp)/L Vi +VCC

t

iL

L

tp

t=0

RD

iL = D

VCC t L

iL

Vi

R –RD (t – t p)/L

iL = lL e

lL

tp

t (a)

(b)

where IL is the maximum value of current flowing through the inductor L. For improved linearity of the current sweep, coil resistance must be kept small.

The non-linearity which was observed v s in the current sweep circuit as shown in previous section was due to the fact kL that as the yoke current increases, the k(R L + RS)t current in the series resistance also increases. This leads to decreasing voltage across the yoke, and the rate of t=0 change of current also thus decreases. Therefore, compensation for the voltage drop across the resistor is inevitable and one way of achieving this end is as shown in Fig. 17.28.

+

Rs

RL

vs –

L

t

Here, Rs is the Thevenin’s resistance and the total resistance of the circuit is Rs + RL. For achieving linearity, the current is needed to be iL = kt, and the voltage source waveform is therefore, d di vs = L __ + (Rs + RL)i = L . __ (kt) + (Rs + RL)kt dt dt = Lk + (Rs + RL)kt Vs is a trapezoidal waveform, which is a step voltage followed by a ramp as shown in Fig. 17.28. Representing the circuit using Norton’s equivalent, Vs L k RL is = ___ = ____ + 1 + ___ kt Rs Rs Rs

(

)

The waveform of the current source also is thus trapezoidal, which is a step followed by ramp. The circuit and the generation of a linear current ramp is shown Fig. 17.29. is k L RS

kt 1 +

RL

RL RS

is

RS L

t

t=0 (a)

(b)

iL = kt

iL = kt

At the end of the sweep, the current returns to zero exponentially with a time constant t = L/(Rs + RL). Rs >> RL, t ª L/Rs.

Since

For small values of Rs, the current decays slowly, with a large time constant t. Hence, the peak voltage developed across the current source will be small. For large values of Rs, the current decays fast, with large peak voltage across the source. Normally, a damping resistor Rd is used across the yoke to limit the peak voltage. V

With Rs and Rd in parallel, the retrace time constant will be t = L/R, where R = Rs || Rd.

R2

can be generated by a voltage sweep circuit as shown in Fig. 17.30. A resistor R1 in series with capacitor C1 is connected across the switch. When switch S remains closed initially, the voltage across C1 is zero. If the switch is opened at time t = 0, analyzing the behaviour of the circuit, we find that it leads to the capacitor acting as a short.

S

R1 C1

+ vo –

Therefore, current = V/(R1 + R2) at time immediately after t = 0, and the voltage across R1 is V . R1/(R1 + R2). When the capacitor starts charging at t = 0 sec onwards, the voltage across it builds up, with exponentially reducing voltage across R1. Finally the capacitor voltage reaches V, with voltage across resistor becoming 0. Therefore, the output voltage vo can be represented as, vo = Exponential decay of voltage across R1 + Exponential rise of voltage across C1. –t –t ___________ ___________ V◊R1 = _________ e (R1 + R2) C1 + V 1 – e (R1 + R2) C1 (R1 + R2)

(

)

–t R2◊V ___________ = V – _______ e (R1 + R2) C1 R1 + R2

Thus,

R2◊V t t2 vo = V – _______ 1 – ___________ + _____________2 – º R1 + R2 (R1 + R2) C1 2 (R + R ) C

[

1

2

1

Neglecting higher order terms of the exponential series, we get R2 VR2t VR2t2 _____________ vo = V 1 – _______ + ____________ – R1 + R2 (R1 + R2)2 C1 2 (R1 + R2)3 C21

[

]

VR1 VR2 VR2t2 _____________ = _______ + ____________ – R1 + R2 (R + R )2 C 2 (R + R ) C2 1

2

1

With R2 >> R1, VR1 VR2t _______ VR2t2 vo = ____ + _____ – R2 R2 C 2 R3 C2 2

1

2

1

1

2

1

]

VR1 Vt t = ____ + _____ 1 – ______ R2 R2C1 2R2C1

[

]

V R1 t Keeping ______ > Vg where Vg is the cut-in voltage of the diode. During the positive half cycle of the input signal, the anode of the diode becomes more positive with respect to the cathode and hence, diode D conducts. For an ideal diode, the forward voltage drop is zero. So the whole input voltage will appear across the load resistance, RL. During negative half cycle of the input signal, the anode of the diode becomes negative with respect to the cathode and hence, diode D does not conduct. For an ideal diode, the impedance offered by the diode is infinity. So the whole input voltage appears across diode D. Hence, the voltage drop across RL is zero. The ratio of rms value of a.c. component to the d.c. component in the output is known as ripple factor ( G ). rms value of a.c. component Vr, rms G = _________________________ = ______ Vd.c. d.c. value of component _________

where

÷

2 Vr, rms = V2rms – Vd.c.

__________

G=

÷( ) Vrms ____ Vd.c.

2

–1

Vav is the average or the d.c. content of the voltage across the load and is given by 1 Vav = Vd.c. = ___ 2p

Therefore,

Id.c

[

p

2p

Ú Vm sin wtd(wt) + Ú 0.d(wt) p

0

]

Vm Vm = ___ [– cos wt]p0 = ___ p 2p Vd.c. Vm Im = ____ = _____ = ___ RL p RL p

If the values of diode forward resistance (rf ) and the transformer secondary winding resistance (Rs) are also taken into account, then Vm Vd.c. = ___ p – Id.c.(rs + rf) Vd.c. Vm Id.c. = ____________ = ______________ (rs + rf) + RL p (rs + rf + RL) The rms voltage at the load resistance can be calculated as Vrms

p

[

1 = ___ Ú V2m sin2 wtd(wt) 2p 0

[

]

1 __ 2

p

1 = Vm ___ Ú (1 – cos 2 wt) d(wt) 4p 0 ___________

Therefore

G=

÷[

V____ m /2 Vm /p

]

2

–1 =

]

1 __ 2

Vm = ___ 2

_______

p

÷( __2 ) – 1 = 1.21 2

From this expression it is clear that the amount of a.c. present in the output is 121% of the d.c. voltage. So the half-wave rectifier is not practically useful in converting a.c. into d.c. The ratio of d.c. output power to a.c. input power is known as rectifier efficiency (h). d.c. output power d.c. h = ________________ = ____ Pa.c. a.c. input power (Vd.c.)2 Vm 2 ______ ___ R p L 4 = _______2 = ______2 = __2 = 0.406 = 40.6% V (Vrms) p m ___ ______ 2 RL

( )

( )

The maximum efficiency of a half-wave rectifier is 40.6%. It is defined as the maximum reverse voltage that a diode can withstand without destroying the junction. The peak inverse voltage across a diode is the peak of the negative half cycle. For half-wave rectifier, PIV is Vm.

In the design of any power supply, the rating of the transformer should be determined. This can be done with a knowledge of the d.c. power delivered to the load and the type of rectifying circuit used. d.c. power delivered to the load TUF = __________________________________ a.c. rating of the transformer secondary Pd.c. = _________ Pa.c. rated

__

In the half-wave rectifying circuit, the rated voltage of the transformer secondary is Vm / 2 , but the __ Im actual rms current flowing through the winding is only ___, not Im / 2 . 2 2 2 I___ V m m ___ 1 ___ __ R 2 L 2 R 2 2 L ________ _______ TUF = = = 0.287 = ____ 2 Im ___ Vm Vm ___ Vm ____ ___ __ × __ 2 2 2 2 The TUF for a half-wave rectifier is 0.287.

rms value Form factor = ____________ average value Vm/2 = ____ = __ = 1.57 Vm / 2 peak value Peak factor = __________ rms value Vm = _____ = 2 Vm/2

A half-wave rectifier, having a resistive load of 1000 , rectifies an alternating voltage of 325 V peak value and the diode has a forward resistance of 100 . Calculate (a) peak, average and rms value of current (b) d.c. power output (c) a.c. input power, and (d) efficiency of the rectifier.

Solution (a) Peak value of current, Average current,

Vm 325 Im = _______ = __________ = 295.45 mA rf + RL 100 + 1000 Im 295.45 Id.c. = ___ = ______ mA = 94.046 mA

RMS value of current,

Im 295.45 Irms = ___ = ______ = 147.725 mA 2 2

(b) The d.c. power output, Pd.c. = I2d.c. × RL = (94.046 × 10 – 3)2 × 1000 = 8.845 W (c) The a.c. input power,

Pa.c. = (Irms)2 × (rf + RL) = (147.725 × 10 – 3)2 (1100) = 24 W

Pd.c. 8.845 (d) Efficiency of rectification, h = ____ = _____ = 36.85%. Pa.c. 24

A half-wave rectifier is used to supply 24 V d.c. to a resistive load of 500 and the diode has a forward resistance of 50 . Calculate the maximum value of the a.c. voltage required at the input.

Solution

Average value of load current, Vd.c. 24 Id.c. = ____ = ____ = 48 mA RL 500

Maximum value of load current, Im = p × Id.c. = p × 48 mA = 150.8 mA Therefore, maximum a.c. voltage required at the input, Vm = Im × (rf + RL) = 150.8 × 10 – 3 × 550 = 82.94 V

An a.c. supply of 230 V is applied to a half-wave rectifier circuit through transformer of turns ratio 5:1. Assume the diode is an ideal one. The load resistance is 300 . Find (a) d.c. output voltage (b) PIV (c) maximum, and (d) average values of power delivered to the load.

Solution (a) The transformer secondary voltage

230 = ____ = 46 V 5 __

Maximum value of secondary voltage, Vm = ÷2 × 46 = 65 V Therefore, d.c. output voltage, (b) PIV of a diode (c) Maximum value of load current,

Vm ___ 65 Vd.c. = ___ p = p = 20.7 V Vm = 65 V Vm 65 Im = ___ = ____ = 0.217 A RL 300

Therefore, maximum value of power delivered to the load, Pm = I2m × RL = (0.217)2 × 300 = 14.1 W (d) The average value of load current,

Vd.c. 20.7 Id.c. = ____ = ____ = 0.069 A RL 300

Therefore, average value of power delivered to the load, 2 Pd.c. = Id.c. × RL = (0.069)2 × 300 = 1.43 W

A HWR has a load of 3.5 k . If the diode resistance and secondary coil resistance together have a resistance of 800 and the input voltage has a signal voltage of peak value 240 V. Calculate

(a) (b) (c) (d)

peak average and rms value of current flowing d.c. power output a.c. power input efficiency of the rectifier

Solution

Load resistance in a HWR, RL = 3.5 kW

Diode and secondary coil resistance, Rf + rs = 800 W Peak value of input voltage = 240 V Vm 240 Im = __________ = _____ = 55.81 mA rs + rf + RL 4300

(a) Peak value of current,

Im ___________ 55.81 × 10 – 3 Average value of current, Id.c. = ___ = 17.77 mA p = p Im 55.81 × 10 – 3 The rms value of current, Irms = ___ = ___________ = 27.905 mA 2 2 (b) The d.c. power output is Pd.c. = (Id.c.)2 RL = (17.77 × 10 – 3)2 × 3500 = 1.105 W (c) The a.c. power input is Pa.c. = (Irms)2 × (rf + RL) = (27.905 × 10 – 3)2 × 4300 = 3.348 W (d) Efficiency of the rectifier is Pd.c. 1.105 h = ____ = _____ × 100 = 33% Pa.c. 3.348 A HWR circuit supplies 100 mA d.c. to a 250 load. Find the d.c. output voltage. PIV rating of a diode and the rms voltage for the transformer supplying the rectifier.

Solution Given Id.c. = 100 mA,RL = 250 W (a) The d.c. output voltage, Vd.c. = Id.c. × RL = 100 × 10 – 3 × 250 = 25 V

(b) The maximum value of secondary voltage, Vm = (c) PIV rating of a diode,

× Vd.c. =

× 25 = 78.54 V

Vm = 78.54 V

(d) The rms voltage for the transformer supplying the rectifier Vm 78.54 Vrms = ___ = _____ = 39.27 V 2 2

A voltage of 200 cos t is applied to HWR with load resistance of 5 k . Find the maximum d.c. current component, rms current, ripple factor, TUF and rectifier efficiency,

Solution Given Applied voltage = 200 cos t, Vm = 200 V, RL = 5 k (a) To find d.c. current: Vm 200 Im = ___ = _______3 = 40 mA RL 5 × 10 Im 40 × 10 – 3 Id.c. = ___ = _________ = 12.7 × 10 – 3 A = 12.73 mA

Therfore, (b) To find rms current:

Im 40 × 10 – 3 Irms = ___ = _________ = 20 mA 2 2 __________

(c) Ripple factor:

=

(d) To determine TUF:

2

( ) Irms ____ Id.c.

–1=

_________________

(

20 × 10 – 3 ___________ 12.73 × 10 – 3

)

2

–1 = 1.21

Pd.c. TUF = ________ Pa.c. (rated) Pd.c. = I 2d.c.RL = (12.73 × 10 – 3)2 × 5 × 103 = 0.81 W Vm ___ Im ____ 200 40 × 10 – 3 __ × Pa.c. (rated) = ___ = __ × _________ = 2.828 2 2 2 2

Therefore, (e) Rectifier Efficiency:

Pd.c. 0.81 TUF = ________ = _____ = 0.2863 Pa.c. (rated) 2.828 Pd.c. = ____ Pa.c. Pd.c. = 0.81 W 2 Pa.c. = Irms RL = (20 × 10 – 3)2 × 5 × 103 = 2 W

Therefore,

Pd.c. 0.81 = ____ × 100 = ____ × 100 = 40.5% Pa.c. 2

A diode has an internal resistance of 20 and 1000 load from a 110 V rms source of supply. Calculate (i) the efficiency of rectification (ii) the percentage regulation from no load to full load.

Solution

Given

rf = 20 W, RL = 1000 W and Vrms (secondary) = 110 V

The half-wave rectifier uses a single diode. __

Therefore,

Vm = ÷2 Vrms (secondary) = 155.56 V Vm 155.56 Im = _______ = _________ = 0.1525 A rf + RL 20 + 1000 Im ______ 0.1525 Id.c. = ___ p = p = 0.04854 A Vd.c. = Id.c.RL = 0.04854 × 1000 = 48.54 V Pd.c. = Vd.c.Id.c. = 48.54 × 0.04854 = 2.36 W 2

( ) (r + R ) ( since I

Im 2 (rf + RL) = ___ Pa.c. = Irms 2

(

0.1525 = ______ 2 Efficiency,

f

L

rms

Im = ___ for half-wave 2

)

2

) (1000 + 20) = 5.93 W

Pd.c. 2.36 h = ____ × 100 = ____ × 100 = 39.7346% Pa.c. 5.93

Vm ___ VNL – VFL p –Vd.c. _________ ________ Percentage of line regulation = × 100 = × 100 VFL Vd.c. 155.56 ______ p – 48.54 _____________ = × 100 = 2% 48.54

Show that maximum d.c. output power Pd.c. = Vd.c. × Id.c. in a half-wave single phase circuit occur when the load resistance equals diode resistance rf .

Solution

For a half wave rectifier, Vm Im = _______ rf + RL

Im _________ Vm Id.c. = ___ p = p(rf + RL) and

Vd.c. = Id.c. × RL

Therefore,

V2mRL 2 Pd.c. = Vd.c. × Id.c. = Id.c. RL = __________ p2(rf + RL)2

For this power to be maximum, dPd.c. _____ dRL

=0

] [

]

(rf + RL)2 – RL × 2 (rf + RL) V2mRL V2m ________________________ d __________ ____ ___ = 2 =0 dRL p2(rf + RL)2 p (rf + RL)4

[

(rf + RL)2 – 2RL(rf + RL) = 0 r2f + 2rf RL + R2L – 2rf RL – 2R2L = 0 r2f – R2L = 0 R2L = r2f Thus the power output is maximum if RL = rf

The transformer of a half-wave rectifier has a secondary voltage of 30 Vrms with a winding resistance of 10 . The semiconductor diode in the circuit has a forward resistance of 100 . Calculate (a) No load d.c. voltage (b) d.c. output voltage at IL = 25 mA (c) % regulation at IL = 25 mA (d) ripple voltage across the load (e) ripple frequency (f ) ripple factor (g) d.c. power output and (h) PIV of the semiconductor diode.

Solution Vrms (secondary) = 30 V, rs = 10 W, rf = 100 W __

__

Vm = ÷2 × Vrms = ÷2 × 30 = 42.4264 V Vm _______ 42.4264 Vd.c. = ___ = 13.5047 V p = p

(a) (b)

IL = Id.c. = 25 mA

Here

Im Vm ______________ Vd.c. = Id.c.RL = ___ p RL = p (rf + rs + RL) × RL Vd.c. RL = ____ Id.c.

Vd.c. Vm Vd.c. = _______________ × ____ Id.c. Vd.c. p rf + rs + ____ Id.c.

Therefore,

(

)

42.426Vd.c. 1 Vd.c. = ______________________ × _________ V 25 × 10 – 3 d.c. p 100 + 10 + _________ 25 × 10 – 3

(

)

Vd.c. (110 + 40Vd.c.) = 540.1897 Vd.c. 540.1897 – 110 Vd.c. = _____________ = 10.7547 V 40 Vd.c. (NL) –Vd.c. (FL) = _______________ × 100 Vd.c. (FL)

(c) Percentage of regulation

13.5047 – 10.7547 = ________________ × 100 = 25.569% 10.7547 Vd.c. Vm 10.7547 Im = __________, where RL = ____ = _________ = 430.188 V rf + rs + RL Id.c. 25 × 10 – 3

(d)

42.4264 Im = _________________ = 0.07854 A 100 + 10 + 430.188

Therefore,

Im Irms = ___ = 0.03927 A 2 _________

G= Ripple voltage

÷( ) Irms ____ Id.c.

2

______________

0.03927 –1 = 1.21 (÷ _________ 25 × 10 ) 2

–1 =

–3

G × Vd.c. = 1.21 × 10.7547 = 13.02791 V

(e) Ripple frequency, f = 50Hz (f) G = ripple factor = 1.21 (g) Pd.c.= Vd.c.Id.c. = 10.7547 × 25 × 10 – 3 = 0.2688 W (h) PIV = Vm = 42.4264 V It converts an a.c. voltage into a pulsating d.c. voltage using both half cycles of the applied a.c. voltage. It uses two diodes of which one conducts during one half-cycle while the other diode conducts during the other half-cycle of the applied a.c. voltage. There are two types of full-wave rectifiers viz. (i) Full-wave rectifier with center tapped transformer and (ii) Full-wave rectifier without transformer (Bridge rectifier).

Vin Vm

p

D1

2p

wt

–Vm Vo

V1 RL

Vin

Vo

Vm

V2 0

D2

Center tapped transformer

(a)

2p

p

wt

(b)

Figure 18.4 shows the basic circuit and waveforms of full-wave rectifier. During positive half of the input signal, anode of diode D1 becomes positive and at the same time the anode of diode D2 becomes negative. Hence, D1 conducts and D2 does not conduct. The load current flows through D1 and the voltage drop across RL will be equal to the input voltage. During the negative half-cycle of the input, the anode of D1 becomes negative and the anode of D2 becomes positive. Hence, D1 does not conduct and D2 conducts. The load current flows through D2 and the voltage drop across RL will be equal to the input voltage. ___________

=

( ) Vrms ____ Vd.c.

2

–1

The average voltage or d.c. voltage available across the load resistance is 1 Vd.c. = __ Vm sin t d( t) 0

Vm 2Vm = ___ [– cos t]0 = ____ Vd.c. 2Vm 2Im Im __ Id.c. = ____ = ____ = ____ and Irms = ___ RL RL 2 If the diode forward resistance (rf ) and the transformer secondary winding resistance (rs) are included in the analysis, then 2Vm V = ____ – I (r + r ) d.c

d.c.

s

f

Vd.c. 2Vm Id.c. = ____________ = _____________ (rs + rf) + RL p(rs + rf + RL) RMS value of the voltage at the load resistance is

___________________

Vrms =

÷[ ÷(

p

]

Vm 1 __ ___ 2 2 __ p Ú Vm sin wt d(wt) = ÷2 0

_____________ __

Therefore,

G=

V m /÷2 ______ 2 /p

2

)

______

÷

p2 – 1 = __ – 1 = 0.482 8

The ratio of d.c. output power to a.c. input power is known as rectifier efficiency (h). d.c. output power Pd.c. h = ________________ = ____ Pa.c. a.c. input power

[ ]

2Vm 2 ____ 2 (V ) /R p 8 d.c. L =_________ = _______ = ___2 = 0.812 = 81.2% 2 2 V (Vrms) /RL p m ___ __ ÷2

[ ]

The maximum efficiency of a full-wave rectifier is 81.2%. mined by considering the primary and secondary windings separately and it gives a value of 0.693. rms value of the output voltage Form factor = ______________________________ average value of the output voltage __

Vm /÷2 p__ = ______ = ____ = 1.11 2Vm /p 2÷2 __ Vm peak value of the output voltage __ = ÷2 Peak factor = ____________________________ = ______ rms value of the output voltage Vm /÷2

Peak inverse voltage for full-wave rectifier is 2Vm because the entire secondary voltage appears across the non-conducting diode.

A 230 V, 60 Hz voltage is applied to the primary of a 5:1 step-down, center-tap transformer use in a full wave rectifier having a load of 900 . If the diode resistance and secondary coil resistance together has a resistance of 100 , determine (a) d.c. voltage across the load, (b) d.c. current flowing through the load, (c) d.c. power delivered to the load, (d) PIV across each diode, (e) ripple voltage and its frequency and (f) rectification efficiency.

Solution

230 The voltage across the two ends of secondary = ____ = 46 V 5

46 Voltage from center tapping to one end, Vrms = ___ = 23 V 2 __ 2V 2 × 23 × ÷2 m ____ ___________ (a) The d.c. voltage across the load, Vd.c. = p = = 20.7 V p Vd.c. 20.7 (b) The d.c. current flowing through the load, Id.c. = ___________ = _____ = 20.7 mA (rs + rf +RL) 1000 (c) The d.c. power delivered to the load, Pd.c. = (Id.c.)2 × RL = (20.7 × 10 – 3)2 × 900 = 0.386 W __

=2Vm = 2 × 23 × ÷2 = 65 V

(d) PIV across each diode

_____________

Vr, rms = ÷(Vrms)2 – (Vd.c.)2

(e) Ripple voltage,

____________

= ÷(23)2 – (20.7)2 = 10.05 V Frequency of ripple voltage

= 2 × 60 = 120 Hz 2 Pd.c. (Vd.c.)2/RL (V d.c.) ______ h = ___ = _________ = Pa.c. (Vrms)2/RL (Vrms)2

(f) Rectification efficiency,

(20.7)2 ______ 428.49 = ______ = = 0.81 2 529 (23) Therefore, percentage of efficiency = 81%

A full-wave rectifier has a center-tap transformer of 100-0-100 V and each one of the diodes is rated at Imax = 400 mA and Iav = 150 mA. Neglecting the voltage drop across the diodes, determine (a) the value of load resistor that gives the largest d.c. power output, (b) d.c. load voltage and current, and (c) PIV of each diode.

Solution (a) We know that the maximum value of current flowing through the diode for normal operation should not exceed 80% of its rated current. Therefore,

Imax = 0.8 × 400 = 320 mA

The maximum value of the secondary voltage, __

Vm = ÷2 ×100 = 141.4 V Therefore, the value of load resistor that gives the largest d.c. power output Vm 141.4 RL = ____ = __________ = 442 W Imax 320 × 10 – 3

2Vm _________ 2 × 141.4 Vd.c. = ____ = 90 V p = p

(b) The d.c. (load) voltage,

Vd.c. 90 Id.c. = ____ = ____ = 0.204 A 442

The d.c. load current, (c) PIV of each diode

= 2Vm = 2 × 141.4 = 282.8 V

A full-wave rectifier delivers 50 W to a load of 200 voltage across the load.

Solution

. If the ripple factor is 1%, calculate the a.c. ripple

The d.c. power delivered to the load, Pd.c.

V 2d.c. _____ = RL _________

________

Vd.c. = ÷Pd.c. × RL = ÷50 × 200 = 100 V

Therefore, The ripple factor,

Va.c. G = ____ Vd.c. Va.c. 0.01 = ____ 100

i.e.

Therefore, the a.c. ripple voltage across the load, Va.c. = 1 V

In a full wave rectifier, the transformer rms secondary voltage from center tap to each end of the secondary is 50 V. The load resistance is 900 . If the diode resistance and transformer secondary winding resistance together has a resistance of 100 , determine the average load current and rms value of load current?

Solution

Voltage from center tapping to one end, Vrms = 50 V __

Maximum load current,

Vm Vrms × ÷2 70.7 Im = __________ = __________ = _____ = 70.7 mA rs + rf + RL rs + rf + RL 1000

Average load current,

2Im ______________ 2 × 70.7 × 10 – 3 Id.c. = ____ = = 45 mA p p

RMS value of load current,

Im __________ 70.7 ×__10 – 3 __ = Irms = ___ = 50 mA ÷2 ÷2

A full-wave rectifier has a center-tap transformer of 100–0–100 V and each one of the diodes is rated at Imax = 400 mA and Iav = 150 mA. Neglecting the voltage drop across the diodes, determine (a) the value of load resistor that gives the largest d.c. power output, (b) d.c. load voltage and current, and (c) PIV of each diode.

Solution (a) We know that the maximum value of current flowing through the diode for normal operation should not exceed 80% of its rated current. Therefore,

Imax = 0.8 × 400 = 320 mA

The maximum value of the secondary voltage, __

Vm = ÷2 × 100 = 141.4 V Therefore, the value of load resistor that gives the largest d.c. power output Vm 141.4 RL = ____ = __________ = 442 W Imax 320 × 10 – 3 (b) The d.c. load voltage, The d.c. load current, (c) PIV of each diode

2Vm _________ 2 × 141.4 Vd.c. = ____ = 90 V p = p Vd.c. 90 Id.c. = ____ = ____ = 0.204 A RL 442 = 2 Vm = 2 × 141.4 = 282.8 V

A full-wave rectifier circuit uses two silicon diodes with a forward resistance of 20 connected across the load of 1 k reads 55.4 Volts. Calculate

(a) (b) (c) (d)

Irms average voltage across each diode ripple factor and transformer secondary voltage rating.

So lution

Given

Vd.c. = 55.4 V and RL = 1 kW Vd.c. 55.4 Id.c. = ________ = _________ = 54.31 × 10 – 3 A (rf + RL) 20 + 1000

(a)

we know that

2Im Im ___ __ Id.c. = ____ p and Irms = ÷2 p p Im = Id.c. × __ = 54.31 × 10 – 3 × __ = 85.31 mA 2 2

Im ___________ 85.31 × 10 – 3 __ = __ Irms = ___ = 60.32 mA ÷2 ÷2 (b) The average voltage across each silicon diode will be 0.72 V. (c) To find ripple factor G _________ Irms 2 G = ____ –1 Id.c.

÷( )

each. A d.c. voltmeter

_________________

=

÷(

60.32 × 10 – 3 ___________ 54.31 × 10 – 3

2

)

–1 = 0.4833

To find transformer secondary voltage rating 2Vm We know that, Vd.c. = ____ p –Id.c. (rs + rf) where rf is the diode forward resistance and rs is the transformer secondary winding resistance. 2Vm 2Vm ____ –3 55.4 = ____ p – 54.31 × 10 × 20 = p – 1.086 2Vm 56.49 = ____ p

p Vm = 56.49 × __ = 88.73 V 2 Vm _____ 88.73 ___ Vrms = __ = __ = 62.74 V ÷2 ÷2 Hence, transformer secondary voltage rating is 65 V – 0 = 65 V Therefore,

The need for a center tapped transformer in a full-wave rectifier is eliminated in the bridge rectifier. As shown in Fig. 18.5, the bridge rectifier has four diodes connected to form a bridge. The a.c. input voltage is applied to the diagonally opposite ends of the bridge. The load resistance is connected between the other two ends of the bridge. For the positive half-cycle of the input a.c. voltage, diodes D1 and D3 conduct, whereas diodes D2 and D4 do not conduct. The conducting diodes will be in series through the load resistance RL. So the load current flows through RL. During the negative half-cycle of the input a.c. voltage, diodes D2 and D4 conduct, whereas diodes D1 and D3 do not conduct. The conducting diode D2 and D4 will be in series through the load RL and the current flows through RL in the same direction as in the previous half-cycle. Thus a bidirectional wave is converted into an unidirectional one. The average values of output voltage and load current for bridge rectifier are the same as for a centertapped full-wave rectifier. Hence, Vd.c. 2Vm 2Im 2Vm Vd.c. = ____ and Id.c. = ____ = _____ = ____ p p RL p RL If the values of the transformer secondary winding resistance (rs) and diode forward resistance (rf) are considered in the analysis, then 2Vm Vd.c. = ____ p – Id.c. (rs + rf ) 2Im _____________ 2Vm Id.c. = ____ p = p(rs + rf + RL) The maximum efficiency of a bridge rectifier is 81.2% and the ripple factor is 0.48. The PIV is Vm. In the bridge rectifier, the ripple factor and efficiency of the rectification are the same as for the full-wave rectifier. The PIV across either of the non-conducting diodes

is equal to the peak value of the transformer secondary voltage, Vm. The bulky center tapped transformer is not required. Transformer utilisation factor is considerably high. Since the current flowing in the transformer secondary is purely alternating, the TUF increases to 0.812, which is the main reason for the popularity of a bridge rectifier. The bridge rectifiers are used in applications allowing floating output terminals, i.e. no output terminal is grounded. The bridge rectifier has only one disadvantage that it requires four diodes as compared to two diodes for center-tapped full-wave rectifier. But the diodes are readily available at cheaper rate in the market. Apart from this, the PIV rating required for the diodes in a bridge rectifier is only half of that for a center tapped full-wave rectifier. This is a great advantage, which offsets the disadvantage of using extra two diodes in a bridge rectifier. The comparison of rectifiers is given in Table 18.1.

Particulars

Type of rectifier Half-wave

No. of diodes

Full-wave

Bridge

1

2

4

Maximum efficiency

40.6%

81.2%

81.2%

Vd.c. (no load)

Vm/p

2Vm/p

2Vm/p

Average current/diode

Id.c.

Id.c./2

Id.c./2

Ripple factor

1.21

0.48

0.48

Peak inverse voltage

Vm

2Vm

Vm

f

2f

2f

Transformer utilisation factor

0.287

0.693

0.812

Form factor

1.57

1.11

1.11

Output frequency

__

Peak factor

2

÷2

__

÷2

A 230 V, 50 Hz voltage is applied to the primary of a 4:1 step-down transformer used in a bridge rectifier having a load resistance of 600 . Assuming the diodes to be ideal, determine (a) d.c. output voltage, (b) d.c. power delivered to the load, (c) PIV, and (d) output frequency.

Solution (a) The rms value of the transformer secondary voltage, 230 Vrms = ____ = 57.5 V 4 The maximum value of the secondary voltage __

Vm = ÷2 × 57.5 = 81.3 V Therefore, d.c. output voltage, 2Vm ________ 2 × 81.3 Vd.c. = ____ = 52 V p = p (b) The d.c. power delivered to the load, V2d.c. 522 Pd.c. = ____ = _____ = 2.704 W RL 1000 (c) PIV across each diode

= Vm = 81.3 V

(d) Output frequency

= 2 × 50 = 100 Hz

In a bridge rectifier, the transformer is connected to 200 V, 60 Hz mains and the turns ratio of the step down transformer is 11:1. Assuming the diode is ideal, find

(a) Id.c. (b) Voltage and (c) PIV. Solution Given in a bridge rectifier, input voltage = 200 V, 60 Hz and turns ratio = 11:1 (a) To find the voltage across load, Vd.c. 2Vm Vd.c. = ____ p where

__

Vm = Vrms ÷2

Vrms (primary) 200 Vrms (secondary) = __________ = ____ = 18.18 V 11 Turns ratio __

Therefore Hence,

Vm = 18.18 × ÷2 = 25.7 2 × 25.7 Vd.c. = ________ = 16.36 V p

(b) To find Id.c. Assuming that, RL = 600 W, then

Vd.c. 16.36 Id.c. = ____ = _____ = 27.26 mA RL 600

(c) To find PIV

PIV = Vm = 25.7 V

A bridge rectifier uses four identical diodes having forward resistance of 5 and the secondary voltage is 30 V(rms). Determine the d.c. output voltage for Id.c. = 200 mA and value of the output ripple voltage.

Solution

Given Transformer secondary resistance = 5

Secondary voltage

Vrms = 30 V, Id.c. = 200 mA

Since only two diodes of the bridge rectifier circuit will conduct during positive of negative half cycle of the input signal, the diode forward resistance rf = 2 × 5 = 10 We know that,

__ __ 2Vm Vd.c. = ____ – Id.c. (rf + rs) where Vm = 2 Vrms = 2 × 30 V __

Therefore,

Vd.c.

2 × 2 × 30 = ___________ – 200 × 10–3 (10 +5) = 24 V

rms value of ripple at the output Ripple factor = ____________________________ average value of output voltage rms value of ripple at the output 0.48 = ____________________________ 24 Hence, rms value of ripple at the output = 0.48 × 24 = 11.52 V Therefore,

In a full wave rectifier, the required d.c. voltage is 9 V and the diode drop is 0.8 V. Calculate a.c. rms input voltage required in center tapped full wave rectifier and bridge rectifier circuits.

Solution

(a) The d.c. voltage across the load of the full wave rectifier circuit, __

Vd.c.

2 2 × Vrms 2Vm = 9 = ____ – 0.8 = __________ – 0.8

where Vrms is the rms input voltage from center tapping to on end. That is, __

2 2 Vrms 9.8 = ________ Therefore,

9.8__ = 10.885 V Vrms = ____ 2 2

Hence, the voltage across the two ends of the secondary = 2 × 10.885 = 21.77 V __

(b) In the bridge rectifier,

Vd.c.

2 2 Vrms = 9 = ________ – 2 × 0.8

10.6__ = 11.77 V. Therefore, the voltage across two ends of secondary, Vrms = _____ 2 2

The term harmonic is defined as “a sinusoidal component of a periodic waveform or quantity possessing a frequency, which is an integral multiple of the fundamental frequency.” By definition, a perfect sine wave has no harmonics, except fundamental component at one frequency. Harmonics are present in waveforms that are not perfect sine waves due to distortion from nonlinear loads. The French mathematician named Fourier discovered that a distorted waveform can be represented as a series of sine waves, with each being an integer multiple of the fundamental frequency and each with a specific magnitude. That is, the harmonic frequencies are integer multiples [2, 3, 4,….] of the fundamental frequency. For example, the second harmonic on a 50 Hz system is 2 × 50 or 100 Hz. The sixth harmonic in a 50 Hz system, or the fifth harmonic in a 60 Hz system is 300 Hz. There are a number of different types of equipment that may experience faulty operations or failures due to high harmonic voltage and/ or current levels. The amount of the harmonic voltage and current levels that a system can tolerate is dependent on the equipment and the source. The sum of the fundamental and all the harmonics is called the Fourier series. This series can be viewed as a spectrum analysis where the fundamental frequency and the harmonic component are identified. The result of such an analysis for the current waveform of a half-wave rectifier circuit using a single diode is given by

[

cos kwt 1 __ 1 2 S __ ____________ i = Im __ p + 2 sinwt – p k = 2,4,6 (k +1) (k – 1)

]

The angular frequency of the power supply is the lowest angular frequency present in the above expression. All the other terms are the even harmonics of the power frequency. The full-wave rectifier consists of two half-wave rectifier circuits, arranged in such a way that one circuit conducts during one half cycle and the second circuit operates during the second half cycle. Therefore, the currents are functionally related by the expression i1 (a) = i2 (a + p). Thus, the total current of the full-wave rectifier is i = i1 + i2 as expressed by cos k wt 2 __ 4 ________ S ____________ i = Im __ p – p k = even (k +1) (k – 1) kπ0 From the above equation, it can be seen that the fundamental angular frequency is eliminated and the lowest frequency is the second harmonic term 2w. This is the advantage that the full-wave rectifier presents in filtering of the output. Additionally, the current pulses in the two halves of the transformer winding are in such directions that the magnetic cycles formed through the iron core is essentially that of the alternating current. This avoids any d.c. saturation of the transformer core that could give rise to additional harmonics at the output.

[

]

The output of a rectifier contains d.c. component as well as a.c. component. Filters are used to minimise the undesirable a.c., i.e. ripple leaving only the d.c. component to appear at the output. The ripple in the rectified wave being very high, the factor being 48% in the full-wave rectifier; majority of the applications which cannot tolerate this, will need an output which has been further processed.

Figure 18.6 shows the concept of a filter, where the full-wave rectified output voltage is applied at its input. The output of a filter is not exactly a constant d.c. level. But it also contains a small amount of a.c. component. Some important filters are: (i) Inductor filter (ii) Capacitor filter (iii) LC or L-section filter (iv) CLC or p-type filter Figure 18.7 shows the inductor filter. When the output of the rectifier passes through an inductor, it blocks the a.c. component and allows only the d.c. component to reach the load. The ripple factor of the Inductor filter is given by RL __ G = _______ 3÷2 wL It shows that the ripple factor will decrease when L is increased and RL is decreased. Clearly, the inductor filter is more effective only when the load current is high (small RL). The larger value of the inductor can reduce the ripple and at the same time the output d.c. voltage will be lowered as the inductor has a higher d.c. resistance. The operation of the inductor filter depends on its well known fundamental property to oppose any change of current passing through it. To analyse this filter for a full-wave, the Fourier series can be written as 2Vm 4V m __ 1 1 1 ____ ___ ___ ... Vo = ____ p – p 3 cos 2 w t + 15 cos 4w t + 35 cos 6 w t +

[

]

2Vm The d.c. component is ____ p . Assuming the third and higher terms contribute little output, the output voltage is 2Vm 4Vm Vo = ____ – ____ cos 2 wt 2p 3p The diode, choke and transformer resistances can be neglected since they are very small as compared Vm with RL. Therefore, the d.c. component of current Im = ___. The impedance of series combination of RL L and RL at 2w is __________

___________

Z = ÷R2L + (2 wL)2 = ÷R2L + 4w2 L2

Therefore, for the a.c. component, Vm ___________ Im = ____________ 2 ÷RL + 4w2 2 Therefore, the resulting current i is given by, 2Vm 4Vm cos (2wt – j) ___________ i = _____ – ____ ____________ p RL 3p R2 + 4w2 L2 ÷ L

( )

2wL where j = tan–1 ____ . The ripple factor, which can be defined as the ratio of the rms value of the ripple to the d.c. value of the wave, is 4Vm _________________ __ ___________ 3p÷2 ÷R2L + 4w2 L2 2__ ___________ 1 G = _________________ = ____ ◊ __________ 2V 3 2 ÷ m 4w2 L2 _____ ______ 1 + p RL R2L 2 2 4w L If ______ >> 1, then a simplified expression for G is R2L

÷

RL __ G = _______ 3÷2 wL In case, the load resistance is infinity, i.e. the output is an open circuit, then the ripple factor is 2__ G = ____ = 0.471 3÷2 This is slightly less than the value of 0.482. The difference being attributable to the omission of higher harmonics as mentioned. It is clear that the inductor filter should only be used where RL is consistently small.

Calculate the value of inductance to use in the inductor filter connected to a full-wave rectifier operating at 60 Hz to provide a d.c. output with 4% ripple for a 100 load.

Solution

Therefore,

RL __ We know that the ripple factor for inductor filter is G = _______ 3÷2 wL 0.0625 100 __ 0.04 = ________________ = ______ L 3÷2 (2p × 60 × L) 0.0625 L = ______ = 1.5625 H 0.04

An inexpensive filter for light loads is found in the capacitor filter which is connected directly across the load, as shown in Fig. 18.8(a). The property of a capacitor is that it allows a.c. component and blocks the d.c. component. The operation of a capacitor filter is to short the ripple to ground but leave the d.c. to appear at the output when it is connected across a pulsating d.c. voltage.

During the positive half-cycle, the capacitor charges up to the peak value of the transformer secondary voltage, Vm, and will try to maintain this value as the full-wave input drops to zero. The capacitor will discharge through RL slowly until the transformer secondary voltage again increases to a value greater than the capacitor voltage (equal to the load voltage). The diode conducts for a period which depends on the capacitor voltage. The diode will conduct when the transformer secondary voltage becomes more than the ‘cut-in’ voltage of the diode. The diode stops conducting when the transformer voltage becomes less than the diode voltage. This is called cut-out voltage. Referring to Fig. 18.8(b) with slight approximation, the ripple voltage waveform can be assumed as triangular. From the cut-in point to the cut-out point, whatever charge the capacitor acquires is equal to the charge the capacitor has lost during the period of non-conduction, i.e. from cut-out point to the next cut-in point. The charge it has acquired

= Vr, p–p × C

The charge it has lost

= Id.c. × T2

Therefore,

Vr, pp × C = Id.c. × T2

If the value of the capacitor is fairly large, or the value of the load resistance is very large, then it can be assumed that the time T2 is equal to half the periodic time of the waveform. Id.c. T 1 T2 = __ = __ , then Vr, p – p = ____ 2 2f 2fC

i.e.

With the assumptions made above, the ripple waveform will be triangular in nature and the rms value of the ripple is given by Vr, p – p __ Vr, rms = ______ 2÷3 Therefore from the above equation, we have Id.c. __ Vr, rms = ______ 4÷3 fC Vd.c. Vd.c. __ = _________ , since Id.c. = ____ RL 4÷3 fCRL Therefore, ripple factor

Vr, rms 1 __ G = ______ = _________ Vd.c. 4÷3 fCRL

The ripple may be decreased by increasing C or RL (or both) with a resulting increase in d.c. output voltage. 2890 If f = 50 Hz, C in mF and RL in W, G = _____. CRL

Calculate the value of capacitance to use in a capacitor filter connected to a full-wave rectifier operating at a standard aircraft power frequency of 400 Hz, if the ripple factor is 10% for a load of 500 .

Solution

We know that the ripple factor for capacitor filter is 1 __ G = _________ 4÷3 fCRL

Therefore,

0.722 × 10 – 6 1 __ 0.01 = ___________________ = ___________ C 4÷3 × 400 × C × 500 0.722 × 10 – 6 C = ___________ = 72.2 mF 0.01

A15-0-15 Volts (rms) ideal transformer is used with a full-wave rectifier circuit with diodes having forward drop of 1 Volt. The load is a resistance of 100 Ohm and a capacitor of 10,000 F is used as a filter across the load resistance. Calculate the d.c. load current and voltage.

Solution

Given transformer secondary voltage = 15-0-15 V (rms);

Diode forward drop

= 1 V; RL = 100 W; C = 10,000 mF

We know that,

Vrepp Id.c. Vd.c. = Vm – _____ = Vm – ____ 2 4fC

Therefore,

Vd.c. Vd.c. Vd.c. = Vm – _______, since Id.c. = ____ RL RL 4fC

Simplifying, we get

4f RLC Vd.c. = __________ Vm 4f RLC + 1

[

[

]

]

__

__

Vm = Vrms × ÷2 = 15 × ÷2

We know that

[

]

__ 4 × 50 × 100 × 10000 × 10 – 6 Therefore,Vd.c. = ____________________________ × 15 × 2 = 21.105 V ÷ 4 × 50 × 100 × 10000 × 10 – 6 + 1

Considering the given voltage drop of 1 volt due to diodes, Vd.c. = 21.105 – 1 = 20.105 V Vd.c. 20.105 Id.c. = ____ = ______ = 0.20105 A RL 100

A full-wave rectified voltage of 18 V peak is applied across a 500 F filter capacitor. Calculate the ripple and d.c. voltages if the load takes a current of 100 mA.

Solution

Given

Vm = 18 V, C = 500 mF and Id.c. = 100 mA Id.c. 100 × 10 – 3 Vd.c. = Vm – ____ = 18 – __________________ = 17 V 4fC 4 × 50 × 500 × 10 – 6 Id.c. 100 × 10 – 3 __ __ Vr, rms = ______ = ____________________ = 0.577 V 4÷3 fC 4÷3 × 50 × 500 × 10 – 6

Therefore, ripple

Vrms 0.577 G = ____ = _____ × 100 = 3.39% Vd.c. 17

A bridge rectifier with capacitor filter is fed from 220 V to 40 V step down transformer. If average d.c. current in load is 1 A and capacitor filter of 800 F, calculate the load regulation and ripple factor. Assume power line frequency of 50 Hz. Neglect diode forward resistance and d.c. resistance of secondary of transformer.

Solution

Vrms = 40 V, Id.c. = 1A, C = 800 mF and f = 50 Hz

__

__

Vm = ÷2 Vrms = ÷2 × 40 = 56.5685 V

On no load,

Id.c. 1 Vd.c. (FL) = Vm – ____ = 56.5685 – __________________ = 50.3185 V 4fC 4 × 50 × 800 × 10 – 6 Id.c. = 0

Hence,

Vd.c. (NL) = Vm = 56.5685 V

Vd.c. (NL) – Vd.c. (NL) Therefore, percentage of regulation = ________________ × 100 I d.c. (NL) 56.5685 – 50.3185 = ________________ × 100 = 12.42% 50.1385 Vd.c. 50.1385 RL = ____ = _______ = 50.1385 W Id.c. 1 1 1 __ __ G = _________ = ______________________________ = 0.0717, i.e. 7.17% 4 ÷3 fCRL 4 ÷3 × 50 × 800 × 10 – 6 × 50.3185 We know that the ripple factor is directly proportional to the load resistance RL in the inducRL in the capacitor filter. Therefore, if these two filters are combined as LC filter or L-section filter as shown in Fig. 18.9, the ripple factor will be independent of RL. If the value of the inductance is increased, it will increase the time of conduction. At some critical value of inductance, one diode, either D1 or D2 in full-wave rectifier, will always be conducting. From Fourier series, the output voltage can be expressed as 2Vm 4Vm Vo = ____ – ____ cos 2 wt 3 The d.c. output voltage,

2Vm Vd.c. = ____ __

Therefore,

Irms

4Vm ___ ÷2 Vd.c. 1 __ ◊ = _____ = ___ ◊ ____ X 3 3 ÷2 L

This current flowing through Xc creates the ripple voltage in the output. __ XC ÷2 ___ Therefore, Vr, rms = Irms ◊ XC = ◊ Vd.c. ◊ ___ XL 3 __ Vr, rms ÷2 XC The ripple factor, G = ______ = ___ ◊ ___ Vd.c. 3 XL __

÷2 1 1 = ___ ◊ ______ , since XC = ____ and XL = 2wL 3 4w2CL 2wC

1.194 If f = 50 Hz, C is in mF and L is in Henry, ripple factor G = _____ . LC It was assumed in the analysis given above that for a critical value of inductor, either of the diodes is always conducting, i.e. current does not fall to zero. The incoming current consists of two components: Vd.c. 4Vm (i) Id.c. = ____ and (ii) a sinusoidal varying components with peak value of ______. The negative peak of 3 XL __ Vd.c. ____ the a.c. current must always be less than d.c., i.e., ÷2 Irms £ . RL __ ÷2 Vd.c. We know that for LC filter, Irms = ___ × ____ XL 3 2Vd.c. Vd.c. 2 Hence _____ £ ____, i.e. XL ≥ __ RL XL 3 RL RL i.e., LC = ___, where LC is the critical inductance. 3w 2 It should be noted that the condition XL ≥ __ RL cannot be 3 satisfied for all load requirements. At no load, i.e. when the

L Full-wave

C RB load resistance is infinity, the value of the inductance will rectified input Vi also tend to be infinity. To overcome this problem, a bleeder resistor RB, is connected in parallel with the load resistance as shown in Fig. 18.10. Therefore, a minimum current will always be present for optimum operation of the inductor. It improves voltage regulation of the supply by acting as the pre-load on the supply. Also, it provides safety by acting as a discharging path for capacitor.

RL

Design a filter for full-wave circuit with LC filter to provide an output voltage of 10 V with a load current of 200 mA and the ripple is limited to 2%.

Solution

10 The effective load resistance RL = __________ = 50 W 200 × 10 – 3

1.194 We know that the ripple factor, G = _____ LC i.e. i.e.

1.194 0.02 = _____ LC 1.194 LC = _____ = 59.7 0.02

50 Critical value of L = ___ = _______ = 53 mH 3w 3 × 2 f Taking L = 60 mH (about 20% higher), C will be about 1000 mF.

A full wave rectifier (FWR) supplies a load requiring 300 V at 200 mA. Calculate the transformer secondary voltage for (a) a capacitor input filter using a capacitor of 10 mF and (b) a choke input filter using a choke of 10 H and a capacitance of 10 F. Neglect the resistance of choke.

Solution

Given

Vd.c. = 300 V; Id.c. = 200 mA

(a) For the capacitor filter with C = 10 mF, Id.c. Vd.c. = Vm – ____ 4fC 200 × 10–3 300 = Vm – _______________ = Vm – 100 4(50) (10 × 10–6) Therefore,

Vm = 400 V(p – p) V__ Vrms = ___ = 282.84 V ÷2

(b) For the choke, i.e., LC filter with L = 10 H; C = 10 mF 2Vm Vd.c. = ____ p 2Vm 300 = ____ p Therefore,

Vm = 471.23 V Vm __ = 333.21 V Vrms = ___ ÷2

Determine the ripple factor of a L-type choke input filter comprising a 10 H choke and 8 F capacitor used with a FWR. Compare with a simple 8 F capacitor input filter at a load current of 50 mA and also at 150 mA. Assume the d.c. voltage of 50V.

Vd.c. = 50 V, L = 10 H, C = 8 mF

Solution

Assume f = 50 Hz i.e. w = 2p f = 100p rad /sec. For LC filter, the ripple factor is 1 1 __ __ G = _________ = __________________________ = 0.01492 i.e. 1.492% 6÷2 w2LC 6÷2 ×(100p)2 × 10 × 8 × 10 – 6 For simple capacitor filter, C = 8 mF, (i)

IL = 50 mA Vd.c. 50 RL = ____ = _________ = 1000 W IL 50 × 10 – 3

1 1 __ __ G = ________ = _________________________ = 0.3608, i.e. 36.08 % 4÷3 fCRL 4 ÷3 × 50 × 8 × 10 – 6 × 1000 (ii)

IL = 150 mA Vd.c. 50 RL = ____ = __________ = 333.33 W IL 150 × 10 – 3 1 1 __ __ G = ________ = __________________________ = 1.082, i.e. 108.2% 4÷3 fCRL 4÷3 × 50 × 8 × 10 – 6 × 333.33

Thus it is inferred that LC choke input filter is more effective than capacitor input filter and the ripple factor of LC choke input filter does not depend on the load resistance.

In a full-wave rectifier using an LC filter L = 10 H, C = 100 F and RL = 500 ripple factor for an input of Vi = 30 sin (100 t)V.

Solution

. Calculate Id.c.,Vd.c. and

Comparing the input with Vi = Vm sin wt Vm (secondary) = Vm = 30 V 2Vm ______ 2 × 30 Vd.c. = ____ p = p = 19.0985 V Vd.c. 19.0985 Id.c. = ____ = _______ = 0.03819 A = 38.19 mA RL 500 1 __ Ripple factor = _________ 6÷2 w2LC 1 __ = ____________________________ = 1.194 × 10 – 3 6÷2 × (100p)2 × 10 × 100 × 10 – 6

The filtering level can be improved by using two of more L-section filters in series, as shown in Fig. 18.11. It is assumed that the reactance of all the inductances are much larger than the reactance of the capacitors and the reactance of the last capacitor is small compared with the resistance of the load. Under these conditions, the impedance between 3 and 3¢ is XC2, the impedance between 2 and 2¢ is XC1, and the impedance between 1 and 1¢ is XL1. The alternating current I1 through L1 is, given by __

I1 =

2 Vd.c. ____ ÷______ 1 3

The a.c. voltage across C1 is given by V22¢ = I1XC1

XL1

The alternating current I2 through L2 is given by

L1 1

V22¢ I2 = ____ XL2

L2

2

+

I1

I2 C1

The a.c. voltage across C2 and hence across the load is given by

3

C2

RL

Vo –

1¢

2¢

3¢

__

XC2XC1 ÷2 Vd.c. XC2 XC1 V33¢ = I2XC2 = I1 _______ = ______ ____ ____ XL2 XL2 XL1 3 The ripple factor is obtained by dividing the above equation by Vd.c.. Hence __

÷2 XC1 XC2 G = ___ ____ ____ 3 XL1 XL2

The generalized expression for any number of sections can be obtained by comparing the above equation with that of a single L-section. For example, the ripple factor of a multiple L-section filter (Gn) is given by __

n

( )

÷2 XC Gn = ___ ___ 3 XL

__

÷2 1 = ___ ___________ 3 (16p 2f 2LC)n

where n is the number of similar L-sections. Figure 18.12 shows the CLC or p-type filter which basically consists of a capacitor filter followed by an LC section. This filter provided a fairly smooth output, and is characterized by a highly peaked diode currents and poor regulation. The action of a p-section filter can best be understood by considering the inductor and the second capacitor as an L-section filter that acts upon the triangular output-voltage wave from the first capacitor. The output voltage is then approximately that from the input capacitor, decreased by the d.c. voltage drop in the inductor. The ripple contained in this output is reduced by the L-section filter.

L1 Full-wave rectified input Vi

C1

C2

RL Vo

The ripple voltage can be calculated by analyzing the triangular wave into a Fourier series and then multiplying each component by XC2/XL1 for this harmonic. The Fourier analysis of this waveform is given by Vr sin 2w t _______ sin 6wt º _______ v = Vd.c. – ___ + – p sin 2w t – 2 3

(

We know that

Id.c. Vr = ____ 2fC1

The rms second-harmonic voltage is __ Id.c. Vr __ = ÷2 Id.c.XC1 __ = ________ Vrms = V 2¢ = ____ 2pfC1÷2 p÷2

)

where XC1 is the reactance of C1 at the second-harmonic frequency. The voltage V 2¢ is impressed on an L-section, and the output ripple is V 2¢ XC2/XL1. Hence the ripple factor is

__

__ XC1 X Vrms ÷2 Id.c.XC1 XC2 C2 G = ____ = _________ ____ = ÷2 ____ ____ Vd.c. Vd.c. XL1 RL XL1

where all reactance are calculated at the second-harmonic frequency. For f = 60 Hz, the above equation reduces to 3,300 G = _________ C1C2L1RL In order to obtain pure d.c. at the output, more number of p-sections may be used in series. Such a filter using more than one p-section, as shown in Fig. 18.13, is called multiple p-section filter. L1 Full-wave rectified input Vi

C1

L2

C2

Section I

C2

C3

Section II

The ripple factor for multiple p-section filler is given by __ XC1 X X XCn C2 C3 G = ÷2 ____ ____ ____ º ______ RL XL1 XL2 XL(n – 1) where n is the number of p-sections.

Design a CLC or -section filter for Vd.c. = 10 V, IL = 200 mA and

Solution

= 2%.

10 RL = __________ = 50 W 200 × 10 – 3 5700 114 0.02 = ___________ = _______ LC1 C2 × 50 LC1 C2

If we assume L = 10 H and C1 = C2 = C, we have 114 11.4 0.02 = ____2 = ____ C2 ____

C2 = 570; therefore, C = ÷570 ª 24 mF

RL Vo

A full-wave single phase rectifier employs a -section filter consisting of two 4 F capacitances and a 20 H choke. The transformer voltage to the center tap is 300 V rms. The load current is 500 mA. Calculate the d.c. output voltage and the ripple voltage. The resistance of the choke is 200 .

Solution

C1 = C2 = 4 mF, L = 20 H IC = 500 mA, Rx = 200 W

Maximum value of secondary voltage,

__

Vsm = ÷2 × 300 = 424.2 V Vd.c. 270.19 RL = ____ = __________ = 540 W Id.c. 500 × 10 – 3 Vr Vd.c. = Vs (max) – ___ – Id.c.Rx 2 Ripple voltage,

Id.c. Vr = ____ 2fC 500 × 10 – 3 = ________________ = 1.25 mV 2 × 50 × 4 × 10 – 6

1.25 × 10 – 3 Vd.c. = 424.2 – __________ – (500 × 10–3 × 200) = 324.19 V 2 Consider the CLC filter with the inductor L replaced by a resistor R. This type of filter called R+C filter is shown in Fig. 18.14. The expression for the ripple factor can be obtained by replacing XL by R. Then, D.C. output voltage,

__ XC1 XC2 G = ÷2 ____ ◊ ____ RL R

Therefore, if resistor R is chosen equal to the reactance of the inductor which it replaces, the ripple remains unchanged.

R Full-wave rectified input Vi

C1

C2

RL

The resistance R will increase the voltage drop and hence, the regulation will be poor. This type of filters are often used for economic reasons, as well as the space and weight requirement of the iron-cored choke for the LC filter. Such R+C filters are often used only for low current power supplies. Table 18.2 shows the comparison of various types of filters, when used with full-wave circuits. In all these filters, the resistances of diodes, transformer and filter elements are considered negligible and a 60 Hz power line is assumed.

Type of Filter None

L

C

L-Section

-Section

Vd.c. at no load

0.636 Vm

0.636 Vm

Vm

Vm

Vm

Vd.c. at load Id.c.

0.636 Vm

0.636 Vm

4170Id.c. Vm – _______ C

0.636 Vm

Ripple factor

0.48

RL _______ 16000L

2410 _____ CRL

0.83 ____ LC

3330 _________ LC1C2RL

Peak inverse voltage (PIV)

2 Vm

2 Vm

2 Vm

2 Vm

2 Vm

4170Id.c. Vm – _______ C

A full-wave voltage doubler circuit is shown in Fig. 18.15, where each diode allows one capacitor to be charged up to the peak of the input voltage, Vm. During the positive half cycle, diode D1 conducts and capacitor C1 is charged to Vm. Similarly, during the negative half cycle, diode D2 conducts and the capacitor C2 is charged to Vm. Since the load RL is across the series combination of C1 and C2, the total output voltage is 2Vm, with a ripple frequency twice that of the input. Such circuits are useful only when the load current is very small.

D2

D1

230 V a.c. +

– +

C2

–

C1

RL

A half-wave voltage doubler circuit is shown in Fig. 18.16, where C1 and D1 together behave like a clamper and the clamped output voltage V1 has a peak value of 2Vm and V1 will not become negative. The voltage V1 is a sine wave with Vm as the average value. Diode D2 acts as a rectifier and capacitor C2 acts as a filter. The output d.c. voltage Vo is 2Vm, with a ripple frequency equal to that of the input. A d.c. output voltage of – 2Vm or + 2Vm can be produced, depending upon diode polarities. The half-wave voltage doubler is used to provide a high d.c. output voltage, typically 3 kV. The principle of the half-wave voltage doubler may be used to provide any degree of voltage multiplication by cascading diodes and capacitors. The voltage multiplier circuit showing tripling and quadrupling action is shown in Fig. 18.17.

–

Voltage

D2

+

2 Vm

+

C1 230 V a.c.

C2

D1

RL –

Vo

wt Rectifier and filter

Clamper circuit

Tripler

A

C1 +

C3

–

+

Vm 230 V a.c.

–

B

2Vm

D1

D2 C2 +

C

D3

D4 C4

–

+

2Vm Quadrupler

2Vm

–

D

A load connected between A and B will have a d.c. voltage of 3 Vm and from C to D an output of 4 Vm, since C1 charges up to Vm and other capacitors to 2 Vm. By using the same principle, voltages up to 14 kV may be obtained for oscilloscope, CRT applications.

In an unregulated power supply, the output voltage changes whenever the input voltage or load changes. An ideal regulated power supply is an electronic circuit designed to provide a predetermined d.c. voltage Vo which is independent of the load current and variations in the input voltage. A voltage regulator is an electronic circuit that provides a stable d.c. voltage independent of the load current, temperature and a.c. line voltage variations. The output d.c. voltage Vo depends on the input unregulated d.c. voltage Vin, load current IL and temperature T. Hence, the change in output voltage of power supply can be expressed as follows: Vo Vo o Vo = ____ Vin + ____ IL + ____ T Vin IL T or

Vo = SV Vin + Ro IL + ST T

where the three coefficients are defined as

Input regulation factor, Output resistance, Temperature coefficient,

DVo SV = ____ | D IL = 0; DT = 0 DVin DVo Ro = ____ | Vin = 0; DT = 0 DIL DVo ST = ____ | DVin = 0; DIL = 0 DT

Smaller the value of the three coefficients, better the regulation of the power supply. Line regulation is defined as the change in output voltage for a change in line supply voltage, keeping the load current and temperature constant. Line regulation is given by change in output voltage DVo Line regulation = ______________________ = ____ DVin change in input voltage Load regulation is defined as a change in regulated output voltage as the load current changes from no load to full load. It is expressed as a percentage of no load voltage or full load voltage. Vno load – Vfull load % Load regulation = _______________ × 100 Vno load Vno load – Vfull load or % Load regulation = _______________ × 100 Vfull load where Vno load the output voltage at zero load current and Vfull load the output voltage at rated load current. This is usually denoted in percentage. The plot of the output voltage Vo versus the load current IL for a full-wave rectifier is given in Fig. 18.18. The drop in the characteristics is a measure of the internal resistance of the power supply.

Vo 2 Vm p

ld.c.(rf )

l

L A zener diode, under reverse bias breakdown condition, can be used to regulate the voltage across a load, irrespective of the supply voltage or load current variations. A simple zener voltage regulator circuit is shown in Fig. 18.19. The zener diode is selected with Vz equal to the voltage desired across the load. The zener diode has a characteristic that under reverse bias condition, the voltage across it practically remains constant, even if the current through it changes by a large extent. Under normal conditions, the input current Ii = IL + IZ flows through resistor R. The input voltage Vi can be li = l z + l L + R – written as Vi = IiR + Vz = (IL + Iz) R + Vz. +

+

When the input voltage Vi increases (say due to supply voltage variations), as the voltage across zener diode remains constant, the drop across resistor R will increase with a corresponding increase in IL + IZ. As VZ is a constant, the voltage across the load will also remain constant and

+

li Vi

–

lz

Vz –

RL

V –

hence, IL will be a constant. Therefore, an increase in IL + IZ will result in an increase in IZ which will not alter the voltage across the load. It must be ensured that the reverse voltage applied to the zener diode never exceeds PIV of the diode and at the same time, the applied input voltage must be greater than the breakdown voltage of the zener diode for its operation. The zener diodes can be used as ‘stand-alone’ regulator circuits and also as reference voltage sources.

Design a Zener shunt voltage regulator with the following specifications: Vo = 10 V; Vin = 20–30 V;

IL = (30–50) mA; Iz = (20–40) mA Solution

Refer to Fig. 18.19.

Selection of zener diode Vz = Vo = 10 V Iz max = 40 mA Pz = Vz × Iz max = 10 × 40 × 10 – 3 = 0.4 W Hence a 0.5WZ 10 zener can be selected Value of load resistance, RL Vo 10 RL min = _____ = _________ = 200 W IL max 50 × 10 – 3 Vo 10 RL max = _____ = _________ = 333 W IL min 30 × 10 –3 Value of input resistance, R Vin(max) – Vo R max = _____________ ILmin + Iz(max) 30 – 10 = _______________ = 286 W (30 + 40) × 10 – 3 Vin (min) – Vo R min = _____________ IL max + Iz (min) 20 – 10 = _______________ = 143 W (50 + 20) × 10 – 3 Therefore,

Rmax + Rmin R = ___________ = 215 W 2

In a Zener regulator, the d.c. input is 10V ± 20%. The output requirements are 5 V, 20 mA. Assume Iz(min) and Iz(max) as 5 mA and 80A. Design the Zener regulator.

Solution The minimum Zener current is Iz (min) = 5 mA when the input voltage is minimum. Here the input voltage varies between 10 V ± 20% i.e. 8 V and 12 V. Therefore, the input voltage Vi(min) = 8 V Given load current IL = 20 mA and the voltage across the load, V0 = 5 V. Therefore, V0 5V RL = ___ = ________ = 250 IL 20 × 10 – 3 Hence, the series resistance Vi(min) – V0 R = ___________ (Iz(min) + IL) (8 – 5) = ______________ = 120 (5 + 20) × 10 – 3 The various values are given in the Zener regulator shown in Fig. 18.20.

If d.c. unregulated input is 20 V, V0 = 10 V, load current is 0–20 mA, design the regulator, assume for the Zener, Iz(min) = 10 mA, Iz(max) = 100 mA.

Solution

Given input voltage, Vi = 20 V

Output voltage

V0 = 10 V

Load current varies from 0 to 20 mA Iz(min) = 10 mA, Iz(max) = 100 mA Here,

Vz = V0 = 10 V (constant)

Applying KVL to a closed-loop circuit, 20 = IR + 10 or

IR = 10 10 ___ Therefore, R = , where I is the loop current in I amperes (i) Let Iz = Iz(min) and IL = 0 The total current I = IL + Iz = 10 mA Therefore,

10 V R = ______ = 1000 10 mA

(ii) For Iz = Iz(max) = 100 mA and IL = 20 mA I = IL + Iz = 20 + 100 = 120 mA 10 V Therefore R = _______ = 83.33 W 120 mA (iii) The range of R varies from 83.33 W to 1000 W.

Design a Zener voltage regulator to meet the following specifications: Output voltage = 5 V, Load current = 10 mA, Zener wattage = 400 mW and Input voltage = 10 V ± 2 V.

Solution

Given

V0 = 5 V, IL = 10 mA V0 5 RL = ___ = ________ = 500 W IL 10 × 10 – 3

Here, load resistance is

400 mW Iz(max) = ________ = 80 mA 5V The minimum input voltage required will be when Iz = 0. Under this condition, Maximum Zener Current

I = IL = 10 mA Minimum input voltageVi(min) = Vo + IR Hence,

Vi(min) = 10 – 2 = 8 V 8 = 5 + (10 × 10 – 3) R 3 Rmax = _________ = 300 W 10 × 10 – 3

or Thererfore,

Now, maximum input voltage, Vi(max) = 5 + [(80 + 10)10 – 3]R 12 = 5 + (90 × 10 – 3)R

or

7 Rmin = ________ = 77.77 W 90 × 10 – 3 The value of R is chosen between 77.77 W and 300 W.

A 24 V, 600 mW Zener diode is used for providing a 24 V stabilized supply to a variable load. If the input voltage is 32 V, calculate (i) the value of series resistance required and (ii) diode current when the load is 1200 .

Solution

Given

The load current,

V0 = 24 V, Vi = 32 V, PZ = 600 mW V0 24 IL = ___ = _____ = 20 mA RL 1200

Max. Zener current,

600 × 10 – 3 Iz(max) = __________ = 25 mA 24

Vi – V0 8 32 – 24 1600 Rmax = _____________ = _______________ = ________ = _____ = 177.78 W IL(min) + Iz(max) (20 + 25) × 10 – 3 45 × 10 – 3 9

A Zener voltage regulator circuit is to maintain constant voltage at 60 V, over a current range frome 5 to 50 mA. The input supply voltage is 200 V. Determine the value of resistance R to be connected in the circuit, for voltage regulation from load current IL = 0 mA to IL max, the maximum possible value of IL. What is the value of IL max?

Given Vz = Vo = 60 V and Vin = 200 V

Solution

(a) To find the value of resistance (R). Vin – Vo R = ______________ Iz(min) + IL(max) 200 – 60 140 = _________ = _________ = 2.8 kW 50 × 10 – 3 50 × 10 – 3 (b) To find the value of IL(max). If Iz(max) = 50 mA, IL(min) = 0 mA If Iz(min) = 5 mA, IL(max) = 45 mA Therefore,

IL(max) = 45 mA

For the Zener voltage regulation shown, determine the range of RL and IL that gives the stabilizer voltage of 10 V. 1 kW

Solution

From the circuit, I = IZ + IL

But from R,

Vin – Vo 40 – 10 I = _______ = _______3 = 30 mA R 1 × 10

When IL is minimum, IZ is maximum and vice versa. I = IZmax + ILmin 30 mA = 24 mA + ILmin Therefore,

ILmin = 6 mA

But

Vo ILmin = ______ RLmax

R Vin = 40 V

I IZ VZ = 10 V

IZmax = 24 mA

IL RL Vo = 10 V

Vo 10 RLmax = _____ = ________ = 1.667 kW ILmin 6 × 10 – 3 and

I = IZmin + ILmax 30 mA = 5 mA + ILmax ILmax = 25 mA Vo ILmax = _____ RL min

But

Vo 10 RLmin = _____ = _________ = 400 W ILmax 25 × 10 – 3 Hence, the range of IL is 6 mA to 25 mA and that of RL is 400 W to 1.667 kW.

Determine the range of input voltage that maintains the output voltage of 10 V, for the regulator circuit shown.

Solution

1 kW

As Vo = 10 V constant and RL = 10 kW constant, we have Vo 10 IL = ___ = ________3 = 1 mA RL 10 × 10

R Vin

I IZ VZ = 10 V IZmax = 24 mA

When

Vin = Vin (max). IZ = IZ max

Now

I = IZ + IL

Therefore,

Imax = IZmax + IL = 24 mA + 1 mA = 2 mA.

Vin(max) – VZ ___________ = 25 mA R Therefore, Vin(max) –10 = 1 × 103(25 × 10 – 3) Vin(max) = 35 V. When

Vin = Vin(min),

Therefore,

Imin = IZmin + IL = 5 mA + 1 mA = 6 mA Vin (min) – Vz __________ = 6 × 10–3 R

IZ = IZmin = 5 mA

IL RL = 10 kW

Vin(min) –10 = 1 × 103(6 × 10 – 3) Vin(min) = 16 V Thus range of input voltage is 16 V to 35 V for which the output voltage will be of 10 V. In the Zener voltage regulator, the zener current varies over a wide range as the input voltage and load current vary. As a result, the output voltage which is equal to Vz also changes by a small amount. This change in the output voltage can be minimised by reducing the change in the zener current with the help of a circuit called Emitter-follower type regulator as shown in Fig. 18.25.

Here, the load resistance, RL, is not connected across the zener directly as in the zener regulator, but is connected through an amplifier/buffer circuit. Transistor is connected as an emitter-follower. As can be seen, the output voltage, Vo = (Vz – VBE). However, the load current IL is supplied by the transistor from the input voltage Vin, deriving its base IL current from the zener circuit. The base current IB is equal to __, where b is the current-gain of the b transistor. As far as the zener circuit is concerned, it is supplying only the base current. Any change in the load current is reduced by b times i.e. change in the zener current. The Fig. 18.26(a) shows overload protection circuit in which a small sensing resistance RSC is added in series with the load resistance and two diodes are connected from the base of the transistor to the output. The emitter voltage is equal to (Vz – VBE). The voltage drop across the sensing resistance RSC is equal to (IL × RSC). As long as the voltage drop across RSC is less than twice the cut-in voltage of the diode, the diodes are effectively as good as not connected in the circuit. If the voltage drop across RSC increases suddenly due to over current in the load, then the diodes will be forward biased and will start conducting. This will divert a part of the base current, which will be directly led to the output, thus restricting the base current and hence, the transistor current. With a proper design, the transistor can be turnedoff in the case of a short circuit. The protective diodes can be replaced by another transistor Q2 as shown in Fig. 18.26(b). In this case, the voltage across RSC is used in turning ON transistor Q2, giving the same effect as before. If the control element of a regulator operates in its linear region, then the regulator is called a linear regulator. Linear regulators are generally of series

+

RSC

–

lL R Vin

RL Vz

(a)

Q1 +

RSC

–

R Vin

RL Q2

(b)

mode type. The regulator circuit using Zener diode is vulnerable to the variations in supply voltage since the current through the Zener diode also changes correspondingly. Hence the linear regulator uses an op-amp as an error amplifier, and a pass transistor as a control element. The error output from the op-amp drives the control element, which allows current to the load accordingly and keeps the output voltage constant. The basic circuit of a linear voltage regulator is shown in Fig. 18.27. The regulating circuit consists of a voltage reference (Vref), a differential amplifier called error amplifier using op-amp and a series regulating element Q1 connected as an emitter follower. The output voltage is sampled and fed back to the inverting input of the error amplifier through the potential divider R2 – R3. The error amplifier produces an output voltage that is proportional to the difference between the reference voltage and the sampled output voltage and it may be written as Vo¢ = A[Vref – bVo], where A is the gain of the amplifier and b is the feedback factor which is equal to R3/(R2 + R3). Since the drop across the base-emitter junction of transistor Q1 is small, the output Vo can be approximated to Vo¢. Thus

Vo¢ = Vo = A[Vref – bVo]

That is,

Vo = AVref /(1 + Ab)

This equation implies that the output voltage is determined by the reference voltage and the feedback factor. The output voltage thus obtained is kept at a constant level by the control of series element connected with the error amplifier. For instance, an increase in output voltage causes a corresponding decrease

in the error amplifier output, which biases the series control transistor with reduced base current. This action causes an increase in collector-to-emitter voltage and thus the increase in the output is reduced. On the other hand, when the output voltage reduces, the output of the differential amplifier increases. Then, the series transistor is biased heavily at its base and as a consequence, the collector-to-emitter voltage decreases. Thus the reduction in output is compensated and the output voltage is maintained constant. Series element, Q1

Vi R1 Vref bVo

Unregulated supply

+Vo

+ OP.AMP

–

V¢o

C1

RL

R2

VZ VR3 = VZ

R3 –Vo

Referring to Fig. 18.27, design a linear voltage regulator to produce an output of 15 V with a maximum load current of 50 mA.

Solution

Refer to Fig. 18.27. We know that Vi(min) = Vo + 3V = 15 + 3 = 18V

Assuming the ripple voltage Vr = 2V (max), the input voltage is Vr Vi = Vi(min) + ___ = 18 + 1 = 19 V 2 Therefore, the input voltage, Vi = 19 V with a 2 V (max) ripple superimposed Vi 19 Then Vz = __ = ___ = 9.5 V (use the Zener diode 1N758 for 10 V) 2 2 Therefore, Vz = 10 V Iz ª 20 mA Vi – Vz 19 – 10 R1 = _______ = ________ = 450 W Iz 20 × 10 – 3 Let

I2 = IB(max) = 50 mA Vo – Vz 15 – 10 R2 = _______ = ________ = 100 kW I2 50 × 10 – 6 Vz 105 R3 = ___ = ________ = 200 kW I2 50 × 10 – 6

Select

C1 = 50 F.

Specification of transistor Q1 VCE(max) = Vi(max) = Vi + Vr /2 = 19 + 2/2 = 20 V IE = IL = 50 mA P = VCE × IL = (Vi – Vo) × IL = (16 – 15) × 50 × 10 – 3 = 200 mW Use the transistor 2N718 for Q1. The circuit diagram of a dual tracking voltage regulator using op-amps is shown in Fig. 18.28. The top half of the circuit is similar to the single polarity positive voltage regulator shown in Fig. 18.27. The bottom half of the circuit consisting of the components op-amp A2, PNP transistor Q2, resistors R4 and R5, and capacitor C2 constitutes a negative voltage regulator. The reference voltage for the negative voltage regulator is provided by the output of the positive voltage regulator circuit. The potential divider R4 and R5 is connected between the positive and negative output terminals. Any change in the negative voltage output is applied to the op-amp A2, which amplifies and inverts to correct the change accordingly. When the resistors R4 and R5 are made equal, the output voltage between the positive and negative terminals is exactly twice the positive voltage. This gives a negative output that is equal to the positive output. This type of negative voltage regulator is called a tracking regulator, since the negative voltage output tracks the change in the positive output voltage. Series element, Q1

lL

+

+

+ Vo

R1 + A – 1

+

R4 C1

Vi

Vo

R2

VZ

R3 VR = VZ 3

– +

– + +

A2 –

C2

–

Vi

Vo

R5 –

–

Q2

lL

– Vo

The arrangement of this type of plus-minus power supply is possible only when there is no ground connection in the unregulated power supply. In the transistorised shunt voltage regulator shown in Fig. 18.29, the output voltage is determined by the voltage drop across series resistor Rs. If IL increases due to a load change, Vo will tend to decrease. However, the voltage across R2 will also decrease, thereby reducing the forward bias on the transistor and driving it to cut-off. This results in less current flow through the transistor, thereby maintaining IS almost constant, which keeps the voltage drop across RS relatively unchanged. Thus, for a given input voltage, output voltage Vo = Vi – IsRs, remains substantially constant. The major drawback in this circuit is the large amount of power dissipated in Rs. +

Rs +

ls R1 Unregulated power supply

lT

lL

RL Vo

R3 –

IS = IT + IL

If Rs is replaced by a transistor as shown in Fig. 18.30, a more efficient circuit results which is more sensitive to voltage changes and provides better regulation. Transistor Q2 actually serves as a differential amplifier in which the fraction of the output voltage Vo is compared with reference voltage Vz. The difference ( Vo – Vz) is amplified by Q2 and appears at the base of Q1. This in turn determines the voltage drop that will occur across Q1. Because of the gain of Q2, it requires only a small change in Vo to have a large effect on Q1. Further, the output voltage may be varied over wide range using R2. The zener diode and transistor Q2 can be chosen so that the temperature coefficients practically cancel. If R2 is adjusted for a lower output voltage, a greater voltage drop occurs across Q1. Maximum dissipation in Q1 thus takes place at high load currents and low output voltage in variable regulated power supplies employing a series regulator. The transistorised series voltage regulator has the limitation that the output voltage available is restricted by the VCEO of the series transistor used. The power rating of the transistor used, as a series loser, depends on the voltage difference between the input and output voltages. This difficulty can be minimised to a great extent by using thyristors. Thyristors have the ability to control large power with minimal control power, and this control power does not have to remain continuous as in the case of the base current of a transistor. Transistors for a relatively high voltage, high power operations are rarely available.

Q1

Unregulated power supply

–

+

R4 R2

R1

+

Q2

RL Vo

+ +

bVo

lL

R3

Vz –

–

–

Design a series voltage regulator with the following specifications: Vo = 20 V; Vin = (22 –30) V;

IL (max) = 50 mA. Solution

Refer to Fig. 18.30.

Selection of Zener diode Vo 20 RL min = ______ = _________ = 400 W IL(max) 50 × 10 – 3 Vo 20 Vz ª ___ = ___ = 10 V 2 2 Hence, the Zener diode 0.5Z10 is chosen. Since

IC2 10 × 10 – 3 IR1 > IB2, IR1 > ___, IR1 > _________ 150 b IR1 > 66.7 mA

Let

IR1 ª IR2 ª IR3 = 10 mA (neglecting IB2)

Let

IC2 ª IE2 = 10 mA

So, the current flowing through the Zener, Iz = IE2 + IR1 = 20 mA Pz = VzIz = 10 × 20 × 10–3 = 0.2 W < 0.5 W Hence selection of 0.5WZ10 Zener diode is confirmed.

Selection of transistor Q1 IE1 = IR1 + IR2 + IL = (10 + 10 + 50) mA = 70 mA Vi (max) – V0 = 30 – 20 = 10 V For transistor SL100, the ratings are IC(max) = 500 mA VCE(max) = 50 V hFE = 50 to 280 Hence, SL100 can be chosen for Q1. Selection of transistor Q2 From the figure,

VCE2(max) + Vz = (Vo + VBE1)

Therefore,

VCE2(max) = (Vo + VBE1) – Vz = 20.6 – 10 = 10.6 V

For transistor BC107, the ratings are VCEO(max) = 45 V IC(max) = 200 mA hFE = 125 – 300 Hence, transistor BC107 is selected for Q2. Selection of resistors R1, R2 and R3 VR1 = Vo – Vz = 20 – 10 = 10 V VR1 10 R1 = ____ = _________ = 1 kW IR1 10 × 10 – 3 VR2 = Vo – VR3 = 20 – 10.6 = 9.4 V VR2 9.4 R2 = ____ = ________ = 940 W IR2 10 × 10 – 3 VR3 = Vz + VBE2(sat) = 10 + 0.6 = 10.6 V VR3 10.6 R3 = ____ = ________ = 1060 W IR3 10 × 10–3 Selection of resistor R4 VB1 = VC 2 = Vo + VBE1 = 20 + 0.6 = 20.6 V IC1 70 × 10 – 3 IB1 = ___ = ________ = 1.4 mA 50 b

IR4 = IB1 + IC 2 = 11.4 mA VR4(max) Vi(max) – VB1 R4(max) = _______ = ___________ IR4 IR4 30 – 20.6 = __________ = 825 W 11.4 × 10 – 3 VR4(min) Vi(min) – VB1 R4(min) = _______ = ___________ IR4 IR4 22 – 20.6 = __________ = 123 W 11.4 × 10 – 3 R4(max) + R4(min) R4 = ______________ = 474 W 2 Although voltage regulators can be designed using op-amps, it is quicker and easier to use IC voltage regulators. Furthermore, the IC voltage regulators are versatile, relatively inexpensive and are available with features such as programmable output, current/voltage boosting and floating operation for high voltage application. Some important types of linear IC voltage regulators are: 1. Fixed positive/negative output voltage regulators 2. Adjustable output voltage regulators. 78XX series are three terminal, positive fixed voltage regulators. There are seven output voltage options available such as 5, 6, 8, 12, 15, 18 and 24 V. In 78XX, the last two numbers (XX) indicate the output voltage. 79XX series are negative fixed voltage regulators which are complements to the 78XX series devices. There are two extra voltage options of – 2 V and – 5.2 V available in 79XX series. Figure 18.31 shows the standard representation of a monolithic voltage regulator. The input capacitor Ci is used to cancel the inductive effects due to long distribution leads and the output capacitor Co improves the transient response. Dual tracking regulated voltage supplies can be obtained using 7815 and 7915 chips as shown in Fig. 18.32. Type 7815 provides +15 V output and type 7915 provides –15 V output. The advantage of this method is that it can supply a wide range of voltages at much higher currents. LM 723C is the general purpose adjustable voltage regulator. The output voltage is adjustable from 2 to 37 V. It will supply output currents up to 150 mA without

1

3

+Vi

7815

2

33 mF

33 mF

+15 V

0.1 mF

1

0.1 mF 3

2 –Vi

7915

–15 V

external pass transistor and output currents excess of 10 A by adding external transistors. It can be used as either a linear or a switching regulator. Also, it can be used as a negative voltage regulator. The regulating function of this chip will be best understood by considering its internal circuit which is shown in Fig. 18.33. 8V+ Temprature compensated zener

Inv. input 4 2

5 V

7

VC

Series pass transistor

–

+ 3 Non-inv. input

Vref

Voltage reference amplifier

Frequency compensation

Error amplifier

Vout Current Q1 limiter

–

10 Current limit

1 Current sense

6

Vz

A reference voltage is developed across the zener diode which is temperature compensated. The reference amplifier acts as a buffer and so the constant reference voltage is available at its output. The control amplifier has two inputs, one inverting and the other non-inverting. This amplifier compares the reference with a fixed part of the feedback output voltage and the resultant error is amplified. This error voltage controls the series transistor such that the output voltage remains at a constant level. Transistor Q1 is used for current limiting. The load current can be limited by providing a small resistance Rsc between the current limit and current sense terminals. The voltage across Rsc is used to bias the current limiting transistor, present inside the chip. Hence,VBE = Ilimit Rsc, where VBE is the bias voltage and Ilimit is the limiting current

VBE Rsc = ____ Ilimit When the output terminals of a power supply are short circuited, the load current becomes too high and the power supply unit may be damaged. To guard against such an occurrence, current limiters have to be included in the regulator circuit. Current limiting can be provided by means of a fuse or a resistor (Rsc), rated for desired value of current. Figure 18.34 shows the regulator with current limiting. The resistance Rsc has to be chosen for the desired current limit. 0.7 Rsc = ____ Ilimit By doing this, it is ensured that the power supply is being operated safely.

The over voltage problems are divided into two types, namely, (i) spikes and (ii) surges. Spikes are high voltage transients which last for short duration of few ms. Surges are high voltage transients which will last for longer duration and will stretch for many ms. Spike and surge protectors are designed to prevent over voltages from reaching the system. They absorb excess voltages before they enter the system. Surge protectors are connected between the system and the power line. The most common over-voltage protection devices are the metal oxide varistors. The varistors can chop and shunt away all voltages above a certain level. These devices are designed to accept voltages as high as 6000 V and divert any voltage above 200 V to ground. The excess energy does not disappear but turns into heat possibly destroying the varistors. The most important characteristic of over-voltage protection devices are how fast they work and how much energy they can dissipate. Other than varistors, semiconductors, ionised spark-gaps and ferro-resonant transformers are also used as surge protectors.

A system needs to be powered with 9 V d.c. source of maximum load current 100 mA. Design a circuit to supply power with the available domestic a.c. line. Assume any data required, but reasonably. Provide short circuit protection. __

Solution The secondary output of step-down transformer is ÷2 times the output d.c. voltage required. Therefore, the step-down transformer is wound to have 230 V:13 V. Given data:

The d.c. output voltage = 9 V and Load current = 100 mA

The current rating is 1.5 times the maximum load current, i.e. 150 mA. A bridge rectifier or full wave rectifier is used to get the pulsating d.c. output. Vd.c. 9 RL = ____ = _________ = 90 W IL 100 × 10 – 3 A capacitor filter is used to remove the ripple and get a smooth output. 1 __ Ripple factor G = _________ 4÷3 f CRL Assume the ripple factor to be 0.03. 1 __ C = __________________ = 1069 m F ª 1000 m F 4÷3 × 50 × 0.03 × 90 The short circuit resistance Rsc connected with the series pass transistor is VBE 0.7 Rsc = ____ = __________ ª 4.7 W Ilimit 150 × 10 – 3 Assume 7.6 V Zener diode in series with 1.5 kW. The designed circuit is shown in Fig. 18.35. Rsc

+

4.7 W 230 V 50 Hz

1.5 KW

13 V

C

Step-down Transformer

Bridge rectifier

1000 mF

Capacitor Filter

Vz = 7.6 V

Serious voltage regulator with short circuit protection

RL

90 W 9V

Load

The d.c. to d.c. converters and d.c. to a.c. converters belong to the category of Switched Mode Power Supplies (SMPS). The SMPS operating from mains, without using an input transformer at line frequency 50 Hz is called “off-line switching supply”. In off-line switching supply, the a.c. mains is directly rectified and filtered and the d.c. voltage so obtained is then used as an input to a switching type d.c. to d.c. converter. The various types of voltage regulators used in LPS, fall in the category of dissipative regulator, as it has a voltage control element (transistor or zener diode) which dissipates the power equal to the voltage difference between an unregulated input voltage and a fixed output voltage multiplied by the current flowing through it. The switching regulators solve the above problem. The switching regulator acts as a continuously variable power converter and hence, its efficiency is negligibly affected by the voltage difference. Therefore, the switching regulator is also known as ‘non-dissipative regulator’. In a switching power supply, the active device that provides regulation is always operated in a switched mode, i.e. it is operated either in cut-off or in saturation. The input d.c. is chopped at a high frequency (15 to 50 kHz) using an active device (bipolar transistor, power MOSFET or SCR) and the converter transformer. Here, the size of the ferrite core reduces inversely with frequency. The lower limit is defined at about 15 kHz by the requirement for silent operation and the upper limit of 50 kHz is to limit losses in the choke and in the active switching elements. The transformed chopped waveform is rectified and filtered. A sample of the output voltage is used as the feedback signal for the drive circuit for the switching transistor to achieve regulation. Figure 18.1(b) shows the concept of a switching regulator in simple form. The added elements are control logic and oscillator. The oscillator allows the control element to be switched ON and OFF. The control element usually consists of a transistor switch, an inductor and a diode. For each switch ON, energy is pumped into the magnetic field associated with the inductor which is a transformer winding in practice. This energy is then released to the load at the desired voltage level. By varying the duty cycle or frequency of switching, one can vary the stored energy in each cycle and thus control the output voltage. As a switch can only be ON or OFF, it either allows energy to pass or stop, but does not dissipate energy itself. Since only the energy required to maintain the output voltage at a load current is drawn, there is no dissipation and hence, a higher efficiency is obtained. Energy is pumped in discrete lumps, but the output voltage is kept steady by capacitor storage. The major feature of SMPS is the elimination of physically massive power transformers and other power line magnetics. The net result is a smaller, lighter package and reduced manufacturing cost, resulting primarily from the elimination of the 50 Hz components. The block diagram of d.c. to d.c. converter (SMPS) is shown in Fig. 18.37(a). Here, the primary power received from a.c. main is rectified and filtered as high voltage d.c. It is then switched at a high rate of speed approximately 15 kHz to 50 kHz and fed to the primary side of a stepdown transformer. The step-down transformer is only a fraction of the size of a comparable 50 Hz unit thus relieving the size and weight problems. The output at the secondary side of the transformer is rectified and filtered. Then it is sent to the output of the power supply. A sample of this output is sent back to the switch to control the output voltage. SMPS rely on PWM to control the average value of the output voltage. The average value of a repetitive pulse waveform depends on the area under the waveform. If the duty cycle is varied as illustrated in Fig. 18.36, the average value of the voltage changes proportionally.

V

10

5 50

Vav

0 On time

100

t(mS)

Period

V V 10

Vav

2.5

t(mS)

0 25

100

V 10 7.5

Vav 0

t(mS) 75

100

As the load increases, output voltage tends to fall. Most switching power supplies regulate their output using a method called Pulse-Width Modulation (PWM). The power switch which feeds the primary side of the step-down transformer is driven by a pulse-width modulated oscillator. When the duty cycle is at 50%, then the maximum amount of energy will be passed through the step-down transformer. As the duty cycle is decreased, less energy will be passed through the transformer. The width or ON time of the oscillator is controlled by the voltage feedback from the secondary rectifier output, and forms a closed loop regulator. As shown in Fig. 18.37(b), the pulse width given to the power switch is inversely proportional to the output voltage. When the output voltage drops, the switch is ON for longer time, resulting in more energy delivered to the transformer and a higher output voltage. As the output voltage raises, the ON time becomes shorter until the loop stabilises. Since the switching regulator circuit is complex, modern IC packages like Motorola MC 3420/3520 or Silicon General SG 1524 can be used instead of discrete components.

High-frequency switch (15-50 kHz) Input a.c.

High-volt lowfrequency a.c.

Tiny or low-mass step-down Lowtransformer volt a.c.

Rectifier and filter High-volt d.c.

Rectifier and filter

Pulsewidthmodulating oscillator

– + Error amp

Isolation

Output d.c.

Output senser

Reference

(a) Reference sawtooth Duty cycle = 50%

Maximum output current demand

Duty cycle ª 10%

Minimum output current demand

Low d.c. output switch waveform High d.c. output switch waveform

(b)

The three types of switched mode power supplies commonly employed, depending upon the intended application, are (a) Forward converter, (b) Flyback converter, and (c) Push–pull converter. In the forward converter, as shown in Fig. 18.38, the choke carries current both when the transistor is conducting as well as it is not. The diode carries the current during the OFF period of the transistor. Therefore, energy flows into load during both periods. The output voltage Vo can only be less than Vs in this circuit. The choke stores energy during the ON period and also passes some energy into the output load. The diode serves two functions. (i) It provides a discharge path for the choke so that, when the transistor switch opens, there is no arcing due to induced high voltage, and (ii) it provides a path for the current in the coil to decay. In the flyback converter type as shown in Fig. 18.39, the energy is stored entirely in the magnetic flux of the inductor during the ON period of the switch. The energy is emptied (discharged) into the output voltage circuit when the switch is in the open state. The output voltage depends upon the duty cycle.

VCC ON period

Drive

L + Load

C OFF period

–

Vo

VCC Switch Drive When switch is OFF

+ C Vo –

Figure 18.40 shows the self-oscillating type flyback converter which is the most basic and simple converter based on the flyback principle. A switching transistor, a converter transformer, a fast recovery rectifier and an output filter capacitor make up a complete d.c. to d.c. converter. It is a constant output power converter and so are all other d.c. to d.c. converters based on flyback principle. During the conduction time of the switching transistor, the current through the transformer primary starts ramping up linearly with a slope equal to Vin/Lp. The voltage induced in the secondary and the feedback windings make the fast recovery rectifier reverse biased and hold the conducting transistor ON. When the primary current reaches a peak value Ip, where the core begins to saturate, the current tends to rise very sharply. This sharp rise in current cannot be supported by the fixed base drive provided by the feedback winding. As a result, the switching transistor begins to come out of saturation. This is a regenerative process with the transistor getting switched OFF. The magnetic field due to the current flowing in the primary winding collapses, thus reversing the polarities of the induced voltages.

The fast recovery rectifier is forward biased and the stored energy is transferred to the capacitor and load through the secondary winding. Thus, energy is stored during the ON time and transferred during OFF time. The output capacitor supplies the load current during the ON time of the transistor when no energy is being transferred from the primary side. It is constant output power converter. The output voltage reduces as the load increases and vice versa. Utmost care should be taken to ensure that the load is not accidentally taken off the converter. In that case, the output voltage would rise without limit till any converter component gets damaged. It is suitable for low output power applications due to its inherent nature of operation and may be used with advantage up to an output power of 150 W. It has high output voltage ripple. Push–pull converter is the most widely used switching supply belonging to the family of forward converters. There are several different circuit configurations within the push–pull converter sub-family. This circuit differ only in the mode in which the transformer primary is driven. Figure 18.41 shows the conventional self-oscillating push–pull converter. Its operation can be explained by considering it equivalent to two self-oscillating flyback converters operating alternately.

When transistor Q1 is in saturation, energy is stored in the upper half of the primary winding when the linearly rising current reaches a value where the transformer core begins to saturate. The current tends to rise sharply which is not supported by a more or less fixed base bias. The transistor starts coming out of saturation. This is a regenerative process and ends up in switching OFF transistor Q1 and switching ON transistor Q2. Thus, transistors Q1 and Q2 switch ON and OFF alternately. When Q1 is ON, energy is being stored in the upper half of the primary and the energy stored in the immediately preceding half cycle in the lower half of the primary winding (when transistor Q2 was ON) is getting transferred. Thus energy is stored and transferred at the same time. The voltage across secondary is a symmetrical square waveform which is then rectified and filtered to get the d.c. output.

The block diagram of Standby Power Supply (SPS), otherwise called as off-line UPS is shown in Fig. 18.42. It is a system that uses a special circuit that senses the a.c. line current. If the sensor detects a loss of power on the line, the system quickly switches over to a standby power system. The SPS transfers the load to the inverter which draws its power from the attached batteries. The switching process requires a small but measurable amount of time. First, the failure of the electrical supply must be sensed. Even the fastest electronic voltage sensors take a finite time to detect a power failure. Even after a power failure is detected, there is another slight pause before the computer receives its fresh supply of electricity. If the switch is not fast enough, the system shuts down and reboots which defeats the purpose of the use of the backup power supply. The name Uninterrupted Power Supply is self-explanatory. Its output is never interrupted because it does not need to switch its output from linepower to battery. Rather, its battery is constantly and continuously connected to the output of the system through its inverter. It is always supplying power from the battery to the computer. While a.c. power is available to the UPS, it keeps the UPS battery charged through the rectifier circuits. When the power fails, the charging of the battery is stopped, but the system gets continuous supply from the battery. d.c. supply

a.c. a.c. input

Line sensing circuit

a.c. –

d.c. –

–

Triac switch

– d.c.

d.c. - a.c. inverter

– a.c.

To system

d.c.

Storage battery

– d.c.

Battery charger

– a.c.

It is independent of all the variations of the electrical lines. It is the computer’s own generating station keeping it safe from the polluting effects of lightning and load transients. Dips and surges can never reach the computer. The computer gets a smooth, constant electrical supply. The duration for which the UPS powers a system depends not on the rating of the UPS in volt-amperes, but that of the rating of the batteries powering it in ampere-hours. Normally, the UPS comes with a by-pass switch. It helps to directly connect the system to the incoming a.c. supply if there is any problem with the UPS. 1. 2. 3. 4. 5. 6.

Efficiency is high because of less heat dissipation. As the transformer size is very small, it will have a compact unit. Protection against excessive output voltage by quick acting guard circuits. Reduced harmonic feedback into the supply main. Isolation from main supply without the need of large mains transformer. Generation of low and medium voltage supplies are easy.

7. Switching supplies can change an unregulated input of 24 V into a regulated output of 1000 V d.c. 8. Though RF interference can be a problem in SMPS unless properly shielded, SMPS in TV sets is in synchronisation with the line frequency (15.625 kHz) and thus switching effects are not visible on the screen. 9. SMPS are also used in personal computers, video projectors and measuring instruments. Table 18.3 gives the comparison between SMPS and linear supply.

Feature

SMPS

Linear power supply

Efficiency

65–75 per cent

25–50 per cent

Temperature rise

20–40 °C

50–100 °C

Ripple value

Higher 25 to 50 mV

Even 5 mV possible

Overall regulation (percentage drop in volts on load)

0.3 per cent is common, tighter regulation is difficult to get

Even 0.1 per cent is possible

RF interference

Can be a problem unless properly shielded

None

Magnetic material

Uses ferrite core

Uses stalloy or CRGO core

Weight

About 60 W/kg

20–30 W/kg

Cost

More parts, special ones, increase the cost

Advantage for smaller units up to 10 –15 W, but cost is higher if bigger

Reliability

Depends upon availability of suitable transistors

More reliable

Transient response

Slower (in ms)

Faster (in ms)

Complexity

More

Less

In SMPS, the energy conversion is done through storage of energy in the magnetic field of a choke coil (inductor). Energy is stored only during the conduction period of the switching transistor. The amount of energy decides the power capacity of an SMPS. In order to increase energy, large current must be pumped into high inductance. The inductance L is a measure of the flux per ampere of current in the coil. So the energy stored in a coil is given by 1/ 2 LI2 = 1/2(F/I)I2 = 1/2 FI where L is the inductance of the coil in henries, F is flux linking the coil in Webers, and I is current in amps. The flux, F, is supported by the magnetic core of the coil. Iron core cannot be used above 400 Hz due to increased core heating. The core material chosen is generally ferrite as it can work at the

frequencies which are employed in SMPS. Any frequency above 15 kHz is employed in these supplies, but as frequency increases, the core material must have low energy loss due to hysteresis. At lower frequencies, i.e. below 10 kHz, it is not advantageous to make use of switched mode power supplies. The size of core reduces inversely with frequency. Some companies in the USA are making even 300 kHz SMPS units which need special ferrite material for the core. The core size decides the value of flux. The core should not be allowed to get saturated by-passing too much direct current around its core. It is advisable to work well below saturation level. When used as a switch, a transistor internally has a fast switch-on time, ample current rating to withstand surges and a high break down voltage rating to withstand the peak induced voltage in the coil at switch off. Switching time should be very small, below 1 ms, comprising turn-on delay, rise time and fall times of current. When used at frequencies of 15 kHz and above, diodes are generally different from the common diffused junction types used at mains frequency. In SMPS, generally one employs switching diodes with either gold doped junctions or the Schottky barrier diodes which have metal semiconductor junctions. There is not much charge storage in the junction in such switching diodes. The difference between an ordinary diode and a switching diode is apparent in the rectifier waveforms shown in Fig. 18.43.

Input a. c. to diode

Ordinary junction diode

Gold doped and Schottky barrier diode

Electrolytic capacitors used for filtering ripples are necessary for any type of power supply. With power frequency rectifiers, the ripples are at 100 Hz but in SMPS, the frequency of switching is high, of the order of several kHz. At such frequencies, electrolytic capacitors invariably have a series inductance and a resistance effect. The equivalent series resistance (ESR) of the capacitor is about 0.05 to 0.1 W. It grows with frequencies above 10 kHz. The impedance of a capacitor becomes minimum at about 20 kHz, where upon it increases further as shown in Fig. 18.44. In order to decrease the resistance, it is advisable to employ 2 or 3 capacitors of similar type in parallel rather than use a single one. This reduces the ESR.

Integrated circuit (IC) is the outcome of continued improvements in the characteristics and miniaturization of solid-state devices and components. When solid-state devices such as transistors and diodes were invented, they replaced vacuum tubes. Similarly, a new generation of solid-state electronics, i.e. integrated circuits, is replacing the discrete components like resistors, capacitors, diodes, transistors, FETs, etc. In a discrete circuit, the components are separable, whereas the components of integrated circuit are inseparable. Most of the ICs are silicon chips with devices such as transistors, diodes, capacitors and resistors fabricated in them. A single silicon chip can contain a few devices or many thousands of devices. Large and complex circuits can be reduced to a small size by IC technology. The following are the advantages of ICs over discrete components. (i) Small size (around 20,000 components/square inch) (ii) Improved performance (more complex circuits may be used) (iii) Low cost (iv) High reliability and ruggedness (v) Low power consumption (vi) Less vulnerability to parameter variations (vii) Easy troubleshooting by replacement (viii) Simpler design of systems (ix) Standard packaging (x) Increased operating speed (due to the absence of parasitic capacitance effect) (xi) Less weight and portable (xii) Battery operated systems due to low power supply requirement The limitations of integrated circuits are as follows: 1. As IC is small in size, it is unable to dissipate large amount of power. Increase in current may produce enough heat which may destroy the device. 2. At present coils, inductors and transformers cannot be produced in IC form.

IC technology has been advancing rapidly, increasing the complexity and functionality of the circuits fabricated. This necessitates the need for categorizing the ICs based on their complexity levels. Type of IC

No. of Gates

No. of Transistors

Small Scale Integration (SSI)

3–30 per chip approx.

100

Medium Scale Integration (MSI)

30–300 per chip approx.

100–1,000

Large Scale Integration (LSI)

300–3,000 per chip approx.

1,000–20,000

Very Large Scale Integration (VLSI)

More than 3,000 per chip

20,000–10,00,000

Ultra Large Scale Integration (ULSI)

—

106–107

Giant-Scale Integration (GSI)

—

More than 107

The area for SSI chip is 1 sq.mm (1600 sq.mil) and for LSI chip it is 1 sq.cm (1,60,000 sq.mil). The ICs can be classified as shown in Fig. 19.1. On the basis of fabrication process used, ICs can be classified as monolithic circuits and hybrid circuits. The word monolithic means single stone and as the name implies, the entire circuit is fabricated on a single chip of semiconductor. In monolithic integrated circuits, the components like transistors, diodes, resistors and capacitors are formed simultaneously by diffusion process steps. Then the process of metallization is used in interconnecting these components to form the required circuit. The dielectric or PN junction is used to provide electrical isolation in monolithic ICs. The monolithic circuit technology is ideal for applications requiring identical characteristics of components in very large quantities. Therefore, they cost very less and provide higher order of reliability. A hybrid circuit contains individual component parts attached to a ceramic substrate. The components are interconnected by the use of either metallization patterns or bonding wires. The hybrid circuits improve the circuit performance, since passive component values can be trimmed to precision at higher values. This technology is more suitable to custom-designed circuits of small volume fabrication. Hybrid ICs are categorized as thin film and thick film, based on the method used to form the resistors, capacitors, and related interconnections on the substrate. Based on the active devices used, ICs can be classified as bipolar (using BJT) and unipolar (FET). Depending on the isolation technique employed to separate the individual components in the ICs, the bipolar ICs may further be classified as (i) PN junction isolation and (ii) dielectric isolation. On the basis of the type of field effect generation in the FET devices, the unipolar ICs may further be classified as JFET and MOSFET. The ICs are also classified as (i) Linear or Analog ICs, (ii) Digital ICs and (iii) Mixed signal ICs based on the type of signals they process. The linear ICs such as op-amps, voltage regulators, voltage comparators and timers are related to all the design phases of electronics in which signals are represented by continuous or analog quantities. The digital ICs such as logic gates, flip-flops, counters, digital clock chips, calculator chips, memory chips and microprocessors deal with discrete quantities. In a digital IC, the information is represented by binary digits and involves logic and memory. The mixed signal ICs involve both the analog and digital signal processing.

Integrated circuits

Hybrid circuits

Monolithic circuits

Bipolar

Unipolar

(i) Silicon wafer preparation (ii) Epitaxial growth (iii) Oxidation (iv) Photolithography (v) Diffusion (vi) Metallization (vii) Circuit probing (viii) Scribing and separating into chips (ix) Mounting and packaging (x) Encapsulation

The starting material for integrated circuits is a slice of single crystal silicon, which is normally the metallurgical grade silicon (MGS). By the use of chemical vapour deposition techniques (CVD) and hydrogen reduction method, the electronic grade silicon (EGS) is obtained. The EGS is a polycrystalline material of high purity and it is used as the raw material for the preparation of single crystal silicon. The processes of obtaining EGS from MGS are (i) reaction with HCl as given by Si + 3HCl Æ SiHCl3 + H2 thus forming trichlorosilane and (ii) hydrogen reduction of trichlorosilane as represented by 2SiHCl3 + 2H2 Æ 2Si + 6HCl. The EGS has very small impurity level and is a polycrystalline material. This is converted to purer and defect free single crystal by Czochralski technique or Bridgeman technique. The former method is used for growing single crystals and the latter method is used for growing gallium arsenide crystals. The Czochralski technique for growing crystals was developed by Czochralski. The crystal growth apparatus consisting of the Czochralski puller used in this technique is shown in

Seed shaft, lift and rotation Sensor for diameter control

Viewport Purge tube Insulation Heater Susceptor Temperature sensor Control system and power supply

Upper housing

Isolation valve Ambient gas inlet Seed shaft and chuck Furnace chamber Melt Crucible

To vacuum pump Crucible rotation and lift

Fig. 19.2. The Czochralski puller consists of a quartz crucible. The polycrystalline EGS along with an appropriate amount of dopant impurities is placed in the quartz crucible. The material is then heated to a temperature that is slightly in excess of the silicon melting point of 1420oC. A small single-crystal rod of silicon called a seed crystal is then dipped into the silicon melt. The conduction of heat up the seed crystal will produce a reduction in the temperature of the melt in the area of contact with the seed crystal to slightly below the silicon melting point. This will make the silicon to freeze onto the end of the seed crystal, and as the seed crystal is slowly pulled up and out of the melt, it will pull with it a solidified mass of silicon that will be a crystallographic continuation of the seed crystal. Both the seed crystal and the crucible are rotated in opposite directions during the crystal pulling process in order to produce the crystalline silicon ingots of circular cross section. The ingots are then cut into slices, about a millimeter thick, and the surface is polished to give a smooth, highly flat region. P-type (or N-type) impurities are added with the melt to give the required resistivity characteristics to the final silicon ingots (bars) obtained from the crystal growth process. The doping elements are normally identified in parts per billion. The P-type silicon bar is cut into thin slices called wafers as shown in Fig. 19.3. These wafers are polished to mirror finish and they serve as the base or substrate for hundreds of ICs. The enlarged views of circular and rectangular P-type silicon wafers are shown in Fig. 19.4.

Epitaxy means growing a single crystal silicon structure upon a original silicon substrate, such that the new structure is essentially a molecular extension of the original substrate. Thus the structure of the grown epitaxial layer will be a continuation of the single crystal substrate. There is a distinct difference between epitaxy and crystal growing techniques. In epitaxy, a thin film of single crystal silicon is grown

Chip or die Wafer

Silocon wafer

200 mm Silicon crystal or rod 15 – 50 mm

from a vapour phase upon an existing single crystal of the same material, whereas in crystal growing technique, a single crystal is grown from the liquid phase. Epitaxy layers can be closely controlled for their size and resistivity. Growth of epitaxial layer makes it possible to control the doping profile in a device structure. The epitaxy layer is generally free from oxygen and carbon. Most of the integrated circuit structure is formed in the epitaxy layer, the rest of the slice acting purely as a supporting plane. Epitaxy apparatus is very similar to the oxide growth arrangement. RF heating coils are normally used and silicon wafers are stacked in a graphite boat, which may be coated with quartz to prevent the graphite from contaminating the silicon. The apparatus used for the epitaxial growth is shown in Fig. 19.5.

Induction coil

Outlet

Silicon wafers Graphite boat Inlet for various gases

Initially, the slices are heated to about 1200oC and pure hydrogen and hydrochloric acid vapour mixture is passed over them to etch any oxide or impurities away which may exist on the surface of the silicon. HCl vapour is then cut-off and hydrogen gas bubbled through SiCl4 kept in a bubbler is allowed. When this reaches the hot silicon, SiCl4 dissociates and silicon atoms are deposited on the slice where they rapidly establish themselves as part of the original crystal structure. It is essential to saturate the

tube with SiCl4 vapour to ensure a uniform layer thickness over the whole slice. There are a number of different chemical reactions that can be used for the deposition of epitaxial layers. The overall reaction can be classified as hydrogen reduction of a gas. SiCl4 + 2H2 Æ Si + 4HCl When the hydrogen reduction of SiCl4 takes place, the reaction gives rise to free silicon atoms. Atoms from the gas phase skid along the surface of the growing epitaxial film until they find correct position in the lattice structure before becoming fastened into the growing structure. The epitaxy layer may be doped with P or N-type impurities by introducing these dopants with the required concentration, into the vapour stream. Four silicon sources can be used for growing epitaxial silicon. These are silicon tetrachloride (SiCl4), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3) and silane (SiH4). Silicon tetrachloride has been the most studied and has obtained the widest industrial use. The usual sources of dopants are hydrides of phosphorus, boron, or arsenic.Generally, biborane (B2H6) is used for P-type doping and phosphine (PH3) for N-type doping. Doping levels in epitaxial layers rarely exceed 1017 atoms/cm3. The epitaxy layer is about 10 – 15 mm in depth and has a resistivity, which varies in the region, around 10 W-cm.

Silicon dioxide is formed by exposing the wafer to an oxygen environment at a high temperature for a controlled duration and removed from the surface of the silicon slice many times during the manufacture of an integrated circuit. This process is called thermal oxidation because high temperature is used to grow the oxide layer. The layer of silicon dioxide serves two important purposes. (i) SiO2 is an extremely hard protective coating. Hence, it is used for surface passivation and is unaffected by moisture, reagents except hydrofluoric acid and other atmospheric contaminants. (ii) It acts as a diffusion mask permitting selective diffusions into silicon wafer through the windows etched in the oxide. It is also used for insulating the metal interconnections from the silicon. Figure 19.6 shows a typical arrangement of the apparatus used for oxidation. The silicon wafers are kept in a quartz boat and placed in a quartz tube. The tube is heated to a temperature of 1000oC to 1200oC with the use of heating coils. Care is taken for maintaining a uniform temperature along the length of the tube. The wafer is exposed to a gas containing O2 or H2O or both. Silicon dioxide layer is formed on the surface of the silicon wafer by thermal oxidation as given by the Si + 2H2O Æ SiO2 + 2H2 A thickness of 0.02 to 2 mm is normally grown. The thickness of the oxide layer is governed by time, temperature and the moisture content. The colour of the silicon surface changes with thickness of the oxide layer due to the shift in the wavelength of the reflected light, and it is an indication of the layer thickness.

The process of photolithography makes it possible to produce microscopically small circuit and device patterns on Si wafers. Its prime use in integrated circuit manufacturing is to selectively remove the

oxide from the silicon slice. The openings where the SiO2 layer is removed are called as windows and through these windows, the diffusions are allowed to take place. The windows are produced by the process of photolithography. This process enables the fabrication of extremely small circuits and devices, numbering as many as 10,000 components on silicon wafers of less than 1 cm2 area. The photolithographic process involves the following processes. The first step in photolithography is the application of the photoresist. The photoresist is a light sensitive emulsion, which, when exposed to ultraviolet radiation and curing becomes resistant to chemical corrosion. The silicon wafer is held firm in a vacuum chuck and a drop of photoresist is applied at the centre of the oxide layer. The wafer is then rotated at a speed of 5000 rpm. This spin makes the photoresist to uniformly spread as a thin coating over the oxide layer. Hence, this process is also called spin coating. The silicon wafers coated with photoresist are then baked in an oven at a temperature of 100°C. This prebaking is necessary to harden the photoresist coat. The next step in the process of photolithography is the aligning of the photomask over the silicon wafer. The photomask indicates the location of the windows in the oxide layer where the SiO2 layer is to be removed. Thus, a photomask is a photographic plate in which the windows are represented by an opaque area and the remaining regions are made transparent. The photomask is placed over the photoresist-coated silicon wafer. The photomasks can be aligned well over the wafer using a mask aligner. The entire setup is then exposed to ultraviolet radiation. The photoresist under the transparent region of the mask becomes polymerized. These polymerized portions become tougher and they are insoluble in the developer solution. This type of photoresist is called negative photoresist. With a positive photoresist, the exposed region becomes depolymerized and is readily soluble in the developer solution.

After UV exposure, the mask is removed and the wafer is developed using a suitable chemical like trichloroethylene. This results in the removal of the photoresist film where windows are required. After developing, curing is done to the wafer, and this makes the polymerized area resistant to corrosion. After developing and curing, the silicon wafer is again baked in the oven at 150°C for about 20 minutes. The chip is then dipped in an etching solution of diluted hydrofluoric acid which removes the oxide layer that is not protected by the polymerized photoresist. The hydrofluoric acid etches the SiO2 but will not remove the underlying silicon or the photoresist layer to any appreciable extent. The wafers are kept dipped in the etching solution for a sufficiently long time allowing the complete removal of SiO2 in the areas of the wafer that are not covered by the photoresist. The resultant pattern on the SiO2 layer, after etching, is a pattern of openings or windows which is same as the pattern on the photomask. Through these openings, N or P type impurities are diffused in various steps of IC fabrication. After diffusion of impurities, the resist mask is removed with sulphuric acid and by means of a mechanical abrasion process. The process of photolithography is illustrated in Fig. 19.7.

This is an important process in the fabrication of monolithic ICs. During epitaxial growth, the full epitaxy layer is doped by a closely controlled amount of impurity. On the other hand, the diffusion process enables selective areas to be doped to the required levels. The process of junction formation, i.e., generation of P and N-type areas is typically accomplished by the process of allowing the appropriate dopant or impurities to diffuse at a high temperature. It is normally carried out in a furnace similar to that used in thermal oxidation process, by placing the wafers inside it and allowing an inert gas containing the desired dopant passing through it in the temperature environment of 800°C–1200°C. P-type semiconductor is obtained by diffusion of boron in the form of solid, liquid or gaseous source and N-type semiconductor is obtained by diffusion of solid, liquid or gaseous source of arsenic or phosphorous into silicon. The compounds such as boron oxide (B2O3) and boron chloride (BCl3) are used for boron and, phosphorous pentoxide (P2O5) and phosphorous oxychloride (POCl3) are used as sources of phosphorous. The carrier gas such as dry oxygen or nitrogen is normally used for exposing the impurity to the diffusant at high temperatures. The depth of diffusion depends on the time allowed for diffusion and it normally extends to two hours. The diffusion profile is determined by a number of factors, namely, solid solubility, diffusion temperature, diffusion time and surface cleanliness. The diffusion apparatus is shown in Fig. 19.8. The diffusion process uses a high temperature furnace which has a flat temperature profile over its useful length. A quartz boat containing the cleaned wafers

is kept in the hot zone of the furnace. The hot zone temperature is maintained close to the melting point of silicon, i.e., 1200oC, and at this temperature, the silicon atoms are highly mobile. The impurity atoms freely move through the silicon lattice. By the process of substitution, the impurity atoms replace the silicon atoms, going from a region of higher concentration to that of lower concentration.

Substitutional diffusion takes place at high temperature conditions, when several atoms in the semiconductor move out of their lattice site leaving vacancies, into which, the impurity atoms can move-in. This substitutional diffusion mechanism is applicable for most of the common diffusion processes, such as those with boron, phosphorus, and arsenic. Moreover, these dopant atoms are too big to fit into the interstices. Hence, they are made to substitute the vacancies created by silicon atoms. It is defined as the maximum concentration of impurity which can be dissolved in the solid diffusant. The amount of dopant impurities is decided by the dopant profile required and the solid solubility of the diffusant. For example, the solid solubility of phosphorus in silicon is 1021 atoms/cm3 and the density of pure silicon is 1021 atoms/cm3. Therefore, the pure silicon diffusant can accept phosphorus atoms only to about 2% of silicon’s density. At higher temperatures, the diffused impurity atoms acquire higher thermal energy and thereby, higher velocity. The impurities with higher velocities can diffuse much further into the diffusant. It is found that the diffusion coefficient critically depends upon temperature. Therefore, the temperature profile of the diffusion apparatus must have closely controlled flat temperature response over the entire length of its hot zone. The time duration of diffusion process determines the junction depth. For Gaussian distribution profile, the net concentration will decrease due to impurity compensation, and it can approach zero with increasing diffusion time lengths. The silicon surface must be prevented against contaminants during diffusion, which may interfere seriously with the uniformity of the diffusion profile. The crystal defects such as dislocation or stacking faults may produce localized impurity concentration. This results in the degradation of junction characteristics. Hence, the silicon crystals must be made highly perfect.

Metallization is the final step in the wafer manufacturing process. During the manufacture of integrated circuits, it is necessary to deposit a thin layer of metal on the silicon, for instance, to form aluminium interconnections. This process produces a thin-film metal layer that serves as the conductor pattern for the interconnection of various components on the chip. Metallization is also used to produce bonding pads around the periphery of the chip to produce metallized areas for the bonding of wire leads from the package to the chip. The metal films are formed by various methods such as chemical vapour deposition (CVD) and physical vapour deposition (PVD). The arrangement of metallization process using vacuum deposition technique is shown in Fig. 19.9. The silicon wafers are placed face down around the bell jar, with the source of metal in the centre. The vacuum pressure is lowered to below 5 × 10 – 6 Torr before the metal deposition commences. The silicon is then heated to a temperature range of 100°C to 300°C, which causes the deposited metal to chemically react with the silicon dioxide and adhere to the wafer surface. Upward evaporation is also used to prevent impurities, which may be generated by the heat source, from falling onto the wafers. The metal film is normally of 1 m thickness. The thickness can be monitored by including a quartz crystal oscillator in the vacuum, whose frequency can be set with the amount of metal to be deposited on its surface.

After evaporation, the wafers are heated at about 1500°C in an inert-gaseous (nitrogen) atmosphere. This causes the metal to alloy well with the silicon surface so that low resistance is achieved in the interface between the two. This is referred to as a ohmic contact joint.

The performance of each of the integrated circuit fabricated on the wafer is checked electrically by placing probes on the bonding pads of the ICs. Faulty chips are identified and discarded after scribing and separating the individual chips from the wafer.

The wafer, in which hundreds of ICs are fabricated, is broken into individual chips by scribing with a diamond-tipped tool.

The individual chip cannot be directly handled because it is very small and brittle. Hence it is soldered to a gold plated header with which leads have already been connected. The standard packages available are top-hat (TO) package, flat package and dual-in-line plastic package shown in Fig. 19.10(a), (b) and (c) respectively.

Encapsulation of an IC is essential to protect it against mechanical and chemical damages while in use. The encapsulation is done by placing a cap over the circuit and sealing it in an inert atmosphere.

The fabrication of a monolithic transistor includes the following steps. (i) Epitaxial growth (ii) Oxidation (iii) Photolithography (iv) Isolation diffusion (v) Base diffusion (vi) Emitter diffusion (vii) Contact mask (viii) Aluminium metallization (ix) Passivation The letters P and N in the figures refer to the type of doping, and a minus (–) or plus (+) with P and N indicates lighter or heavier doping respectively.

The first step in the transistor fabrication is creation of the collector region. We normally require a low resistivity path for the collector current. This is due to the fact that, the collector contact is normally taken at the top, thus increasing the collector series resistance and the VCE(Sat) of the device. The higher collector resistance is reduced by a process called buried layer diffusion as shown in

Fig. 19.11. In this arrangement, a heavily doped N+ region is sandwiched between the N-type epitaxial layer and P-type substrate. This buried N+ layer provides a low resistance path in the active collector region to the collector contact C. In effect, the buried layer provides a low resistance shunt path for the flow of current. For fabricating an NPN transistor, we begin with a P-type silicon substrate having a resistivity of typically 1 W–cm corresponding to an acceptor ion concentration of 1.4 × 1015 atoms/cm3. An oxide mask with the necessary pattern for buried layer diffusion is prepared. This is followed by masking and etching the oxide in the buried layer mask. The N-type buried layer is now diffused into the substrate. A slow-diffusing material such as arsenic or antimony is used, so that the buried layer will stay-put during subsequent diffusions. The junction depth is typically a few microns, with sheet resistivity of around 20 W per square. Then, an epitaxial layer of lightly doped N-silicon is grown on the P-type substrate by placing the wafer in the furnace at 1200oC and introducing a gas containing phosphorous (donor impurity). The resulting structure is shown in Fig. 19.11. The subsequent diffusions are done in this epitaxial layer. All active and passive components are formed on the thin N-type epitaxial layer grown over the P-type substrate. Obtaining an epitaxial layer of the proper thickness and doping with high crystal quality is perhaps the most formidable challenge in bipolar device processing. As shown in Fig. 19.12, a thin layer of silicon dioxide (SiO2) is grown over the N-type layer by exposing the silicon wafer to an oxygen atmosphere at about 1000oC.

The prime use of photolithography in IC manufacturing is to selectively etch or remove the SiO2 layer. As shown in Fig. 19.13(a), the surface of the oxide is first covered with a thin uniform layer of photosensitive emulsion (Photoresist). The mask, a black and white negative of the required pattern, is placed over the structure. When exposed to ultraviolet light, the photoresist under the transparent region of the mask becomes polymerized. The mask is then removed and the wafer is treated chemically that removes the unexposed portions of the photoresist film. The polymerized region is cured so that it becomes resistant to corrosion. Then the chip is dipped in an etching solution of hydrofluoric acid which removes the oxide layer not protected by the polymerized photoresist. This creates openings in the SiO2 layer through which P-type or N-type impurities can be diffused using the isolation diffusion process as shown in Fig. 19.13(b). After diffusion of impurities, the polymerized photoresist is removed with sulphuric acid and by a mechanical abrasion process.

The integrated circuit contains many devices. Since a number of devices are to be fabricated on the same IC chip, it becomes necessary to provide good isolation between various components and their interconnections.

Ultraviolet Mask SiO2 Photoresist SiO2

P-substrate

P-substrate

(a)

(b)

The most important techniques for isolation are (i) PN junction isolation (ii) Dielectric isolation In PN junction isolation technique, the P+ type impurities are selectively diffused into the N-type epitaxial layer, so that it touches the P-type substrate at the bottom. This method generates N-type isolation regions surrounded by P-type moats. If the P substrate is held at the most negative potential, the diodes will become reverse-biased, thus providing isolation between these islands. The individual components are fabricated inside these islands. This method is very economical, and is the most commonly used for general purpose integrated circuits. In dielectric isolation method, a layer of solid dielectric such as silicon dioxide or ruby surrounds each component and this dielectric provides isolation. The isolation is both physical and electrical. This method is very expensive due to additional processing steps needed. This technique is mostly used for fabricating ICs required for special applications such as military and aerospace. The PN junction isolation diffusion method is shown in Fig. 19.14. The process takes place in a furnace using boron source. The diffusion depth must be atleast equal + + + to epitaxial thickness in order to obtain complete isolation. P N P N P Poor isolation results in device failures as all transistors are shorted together. The N-type island shown in Fig. 19.14 forms P-substrate the collector region of the NPN transistor. The heavily doped + P-type regions marked P are the isolation regions among the active and passive components that will be formed in the various N-type islands of the epitaxial layer.

Formation of the base is a critical step in the construction of a bipolar transistor. The base must be aligned so that, during diffusion, it does not come into contact with either the isolation region or the buried layer. Frequently, the base diffusion step is also used in parallel to fabricate diffused resistors for the circuit. The value of these resistors depends on the diffusion conditions and the width of the opening made during etching. The base width influences the transistor parameters very strongly. Therefore, the base junction depth and resistivity must be tightly controlled. The base sheet resistivity should be fairly

high (200 W – 500 W per square) so that the base does not inject carriers into the emitter. For NPN transistor, the base is diffused in a furnace using a boron source. The diffusion process is done in two steps, predeposition of dopants at 900°C and driving them in at about 1200°C. The drive-in is done in an oxidizing ambience, so that oxide is grown over the base region for subsequent fabrication steps.

P N

P N

P-substrate

Figure 19.15 shows the P-type base region of the transistor diffused in the N-type island (collector region) using photolithography and isolation diffusion processes.

Emitter diffusion is the final step in the fabrication of the transistor. The emitter opening must lie wholly within the base. Emitter masking not only opens windows for the emitter, but also for the contact point, which provides a low-resistivity ohmic contact path for the emitter terminal. The emitter diffusion is normally a heavy N-type diffusion, producing low-resistivity layer that can inject charge easily into the base. A phosphorus source is commonly used so that the diffusion time is shortened and the previous diffusion layers do not diffuse further. The emitter is diffused into the base, so that the emitter junction depth very closely approaches the base junction depth. The active base is then a P-region between these two junctions, which can be made very narrow by adjusting the emitter diffusion time. Various diffusion and drive-in cycles can be used to N P fabricate the emitter. The resistivity of the emitter is usually not too N P critical. The N-type emitter region of the transistor diffused into the P-type base region is shown in Fig. 19.16. However, this is not needed to fabricate a resistor where the resistivity of the P-type base region itself will serve the purpose. In this way, an NPN transistor and a resistor are fabricated simultaneously.

N

P-substrate

After the fabrication of emitter, windows are etched into the N-type regions where contacts are to be made for collector and emitter terminals. Heavily concentrated phosphorous N+ dopant is diffused into these regions simultaneously. The reason for the use of heavy N+ diffusion is explained as follows: Aluminium, being a good conductor used for interconnection, is a P-type of impurity N+ when used with silicon. Therefore, it can produce an N P unwanted diode or rectifying contact with the lightly P N doped N-material. Introducing a high concentration of N N+ dopant causes the Si lattice at the surface semi-metallic. Thus, the N+ layer makes a very good ohmic contact with the Aluminium layer. Figure 19.17 shows the P-substrate pre-ohmic etch pattern used to get a good metal ohmic (non-rectifying) contact with the diffused region. This is done by the oxidation, photolithography and isolation diffusion processes.

The IC chip is now complete with the active and passive devices, and the metal leads are to be formed for making connections with the terminals of the devices. Aluminium is deposited over the entire wafer by vacuum deposition. The thickness for single layer metal is 1 mm. Metallization is carried out by evaporating aluminium over the entire surface and then selectively etching away aluminium to leave behind the desired interconnection and bonding pads as shown in Fig. 19.18. Metal

C

B E

2 1 2

R N N

P

P

1

N Resistor

Transistor

C

B P-substrate

E

Metallization is done for making interconnection between the various components fabricated in an IC and providing bonding pads around the circumference of the IC chip for later connection of wires.

Metallization is followed by passivation, in which an insulating and protective layer is deposited over the whole device. This protects it against mechanical and chemical damage during subsequent processing steps. Doped or undoped silicon oxide or silicon nitride, or some combination of them, are usually chosen for passivation of layers. The layer is deposited by chemical vapour deposition (CVD) technique at a temperature low enough not to harm the metallization.

The integrated PNP transistors are fabricated in one of the following three structures. (i) Substrate or vertical PNP (ii) Lateral or horizontal PNP and (iii) Triple diffused PNP The P-substrate of the IC is used as the collector, the N-epitaxial layer is used as the base and the next P-diffusion is used as the emitter region of the PNP transistor. The structure of a vertical monolithic PNP transistor Q1 is shown in Fig. 19.19(a). The base region of the NPN transistor structure is formed in parallel with the emitter region of the PNP transistor. This method of fabrication has the disadvantage of having its collector held at a fixed negative potential. This is due to the fact that the P-substrate of the IC is always held at a negative potential normally for providing good isolation between the circuit components and the substrate.

C Q2 C B

Metal

E

Q1 E

B

P N P N-well

C

B

P

Q1

C

N B

Q2

E

P-substrate E

This type of PNP transistor is formed by including an additional diffusion process over the standard NPN transistor processing steps. This is called as triple diffusion process, because it involves an additional diffusion of P-region in the second N-diffusion region of a NPN transistor. The structure of the triple diffused monolithic PNP transistor Q2 is also shown in Fig. 19.19(a). This has the limitation of requiring additional fabrication steps and needs sophisticated fabrication assemblies. This is the most commonly used form of integrated PNP transistor fabrication. This has the advantage that it can be fabricated simultaneously with the processing steps of a NPN transistor and therefore it requires no additional masking and diffusion steps. The N-type epitaxial layer is used as the base of the PNP transistor. During the P-type base diffusion process of NPN transistor, two parallel P-regions are formed which make the emitter and collector regions of the horizontal PNP transistor. This arrangement is shown in Fig. 19.19(b). NPN transistor is preferred in monolithic circuits due to the following reasons: (i) The vertical PNP transistor must have his collector held at a fixed negative voltage. (ii) The lateral PNP transistor has very wide base region and has the limitation due to the lateral diffusion of P-type impurities into the N-type base region. This makes the photographic mask making, alignment and etching processes very difficult. This reduces the current gain of lateral PNP transistors as low as 19.5 to 30 as against 50 to 300 for a monolithic NPN transistor. (iii) The collector region is formed prior to the formation of base and emitter diffusion. During the later diffusion steps, the collector impurities diffuse on either side of the defined collector junction.

Since the N-type impurities have smaller diffusion constant compared to P-type impurities, the N-type collector performs better than the P-type collector. This makes the NPN transistor preferable for monolithic fabrication due to the easier process control. The applications such as transistor-transistor logic (TTL) require multiple emitters. Figure 19.20 shows the cross-sectional view of three N+ emitter regions diffused in three places inside the P-type base. This arrangement saves the chip area and enhances the component density of the IC.

The metal contacts are required to be ohmic and no PN junctions to be formed between the metal and silicon layers. The N+ diffusion region serves the purpose of generating ohmic contacts. On the other hand, if aluminium is deposited directly on the N-type silicon, then a metal-semiconductor diode can be said to be formed. Such a metal semiconductor diode junction exhibits the same type of V-I characteristics as that of an ordinary PN junction. The cross-sectional view and symbol of a Schottky barrier diode are shown in Fig. 19.21(a) and (b) respectively. Contact 1 shown in Fig. 19.21(a) is a Schottky barrier and the contact 2 is an ohmic contact. The contact potential between the semiconductor and the metal generates a barrier for the flow of conducting electrons from semiconductor to metal. When the junction is forward biased, this barrier is lowered and the electron flow is allowed from semiconductor to metal, where the electrons are in large quantities.

SiO2

1

2

Al

N

+

N-type

P-type substrate

1

2

The majority carriers carry the conduction current in the Schottky diode whereas in the PN junction diode, minority carriers carry the conduction current and it incurs an appreciable time delay from ON state to OFF state. This is due to the fact that the minority carriers stored in the junction have to be totally removed. This characteristic puts the Schottky barrier diode at an advantage since it exhibits negligible storage time to flow the electron from N-type silicon into aluminium almost right at the contact surface, where they mix with the free electrons. The other advantage of this type of diode is that it has less forward voltage (approximately 0.4 V). Thus, it can be used for clamping and detection in high frequency applications and microwave integrated circuits.

The cross-sectional view of a transistor employing a Schottky barrier diode clamped between its base and collector regions is shown in Fig.19.22 (a). The equivalent circuit and the symbolic representation of the Schottky transistor are shown in Fig.19.22 (b) and (c) respectively. The Schottky diode is formed by allowing aluminium metallization for the base lead which makes contact with the N-type collector region also as shown in Fig. 19.22 (a).

When the base current is increased to saturate the transistor, the voltage at the collector C reduces and this makes the diode Ds conduct. The base to collector voltage reduces to 0.4 V, which is less than the cut-in voltage of a silicon base-collector junction. Therefore, the transistor does not get saturated.

The diodes used in integrated circuits are made using transistor structures in one of the five possible connections. The three most popular structures are shown in Fig. 19.23. The diode is obtained from a transistor structure using one of the following structures. (i) The emitter-base diode, with the collector short-circuited to the base (ii) The emitter-base diode, with the collector open and (iii) The collector-base diode, with the emitter open-circuited. N N+ P

+

P N P

P

N N+

N+ P

+

P N P

P

P N+

N N+

P

+

P N

P

+

P

The choice of the diode structure depends on the performance and application desired. Collector-base diodes have higher collector-base voltage breaking rating, and they are suitable for common-cathode diode arrays diffused within a single isolation island. The emitter-base diffusion is very popular for the fabrication of diodes, provided the reverse-voltage requirement of the circuit does not exceed the lower base-emitter breakdown voltage.

A resistor in a monolithic integrated circuit is obtained by utilizing the bulk resistivity of the diffused volume of semiconductor region. The commonly used methods for fabricating integrated resistors are (i) diffused, (ii) epitaxial, (iii) pinched and (iv) thin film techniques. The diffused resistor is formed in any one of the isolated regions of epitaxial layer during base or emitter diffusion processes. This type of resistor fabrication is very economical as it runs in parallel to the bipolar transistor fabrication. The N-type emitter diffusion and P-type base diffusion are commonly used to realize the monolithic resistor. The diffused resistor has a severe limitation in that, only small valued resistors can be fabricated. The surface geometry such as the length, width and the diffused impurity profile determine the resistance value. The commonly used parameter for defining this resistance is called the sheet resistance. It is defined as the resistance in ohms/square offered by the diffused area.

In the monolithic resistor, the resistance value is expressed by l R = Rs __ w where R = resistance offered (in ohms) Rs = sheet resistance of the particular fabrication process involved (in ohms/square*) l = length of the diffused area and w = width of the diffused area (*1 square = 1 mil

1 mil; 1 mil = 1 milli inch = 25.4 m)

The sheet resistance of the base and emitter diffusion is 200 /square and 2.2 ohm/square respectively. For example, an emitter-diffused strip of 2 mil wide and 20 mil long will offer a resistance of 22 . For higher values of resistances, the diffusion region can be formed in a zig-zag fashion resulting in larger effective length. The polysilicon layer can also be used for resistor fabrication.

Assume the sheet resistance of P-type diffusion is 200

/square. Design a 5 k

diffused resistor.

Solution Given the sheet resistance

Rs = 200

/square.

Then the resistance

R =5k

l = Rs __ w = 200

Therefore,

l 5000 R _____ __ ___ w = Rs = 200 = 25

So, a 5 k

resistor can be fabricated by using a pattern of 25 mil

Given the sheet resistance of polysilicon layer as 30

Solution

Given the sheet resistance Rs = 30

1 mil.

/square, design a 1 k

resistor.

/square.

l l __ = Rs __ w = 30 × w

Then the resistance

R =1k

Therefore,

100 1000 ____ R _____ __l = ___ w Rs = 30 = 3 .

So, a 1 k

l __ w

resistor can be fabricated by using a pattern of 100 mil × 3 mil in the polysilicon layer.

The N-epitaxial layer can be used for realizing large value of resistance. Figure 19.24 shows the cross-sectional view of the epitaxial resistor formed in the epitaxial layer between the two N+ aluminium metal contacts. The sheet resistance offered by the diffusion regions can be increased by narrowing down its effective cross-sectional area. This type of resistance is normally achieved in the base region.

Al metal contacts

N P

+

N

+

N-epitaxial layer

+

P

+

P-substrate

Figure 19.25 shows a pinched base diffused resistor. It can offer resistances of the order of mega ohms in a comparatively smaller area. In the structure shown, no current can flow in the N-type material since the diode achieved at contact 2 is biased in the reversed direction. Only very small reverse saturation current can flow in the N-region. Therefore, by forming this N-region in the base diffusion, the conduction path for the current has been reduced or pinched. Therefore, the resistance between the contact 1 and 2 increases as the width narrows down and hence acts as a pinched resistor. The thin film deposition technique can also be used for the fabrication of monolithic resistors. A very thin metallic film of thickness less than 1 m is deposited on the silicon dioxide layer by vapour deposition techniques. Normally, Nichrome (NiCr) is used for this process. Desired geometry is achieved using masked etching processes to obtain suitable value of resistors. Ohmic contacts are made using aluminium metallization as discussed in the earlier sections. The cross-sectional view of a thin film resistor is shown in Fig. 19.26. Sheet resistances of the value 40 to 400 /square can be easily obtained in this method and thus 20 k to 50 k values are very practical. The advantages of thin film resistors are as follows: (i) They have smaller parasitic components which makes their high frequency behaviour good. (ii) The thin film resistor values can be very minutely controlled using laser trimming. (iii) They have low temperature coefficient of resistance and this makes them more stable.

Al contact

SiO2

Thin film (Ta, Nichrome, SnO2, etc)

The thin film resistor can be obtained by the use of Tantalum over silicon dioxide layer. The main disadvantage of thin film resistor is that its fabrication requires additional processing steps.

Monolithic capacitors are not frequently used in integrated circuits since they are limited in range of values obtained and their performance. There are, however, two types available, the junction capacitor and the thin film capacitor as shown in Fig. 19.27. The junction capacitor is a reverse biased PN junction formed by the collector-base or emitter-base diffusion of the transistor. The capacitance is proportional to the area of the junction and inversely proportional to the depletion thickness. Ca A - area of the junction and Ca T – 1 - thickness of the depletion layer The capacitance value thus obtainable can be around 19.2 nF/mm2 The thin-film or metal oxide silicon capacitor uses a thin layer of silicon dioxide as the dielectric. One plate is the connecting metal and the other is a heavily doped layer of silicon, which is formed during the emitter diffusion. This capacitor has a lower leakage current and is non-directional since emitter plate can be biased positively. The capacitance value of this method can be varied between 0.3 nF/mm2 and 0.8 nF/mm2.

No satisfactory integrated inductors exist. If high Q inductors with inductance of values larger than 5 mH are required, they are usually supplied by a wound inductor which is connected externally to the chip. Therefore, the use of inductors is normally avoided when integrated circuits are used.

Figure 19.28 shows a hypothetical electronic circuit and the possible monolithic integrated circuit realization.

The FET is a device in which the flow of current through the conducting region is controlled by an electric field and hence the name Field Effect Transistor (FET). As current conduction is only by majority carriers, FET is said to be a unipolar device.

1 2

Aluminum metallization

SiO2

P-type N

N-type epi layer

J2 J1

+

P-type substrate

(a) 1 2

Aluminum metallization

SiO2

N

+

N-type epi layer P-type substrate

(b)

Based on the construction, the Field Effect Transistors are classified into two types, namely, (i) Junction Field Effect Transistor (JFET) and (ii) Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) or Insulated Gate FET (IGFET) or Metal Oxide Silicon Transistor (MOST). Depending upon the majority carriers, JFET has been classified into two types, namely, (i) N-channel JFET with electrons as the majority carriers, and (ii) P-channel JFET with holes as the majority carriers. The fabrication of monolithic N-channel JFET and MOSFET, and the Complementary Metal-OxideSemiconductor (CMOS) are discussed in the following sections.

P P

R D

C

l

P

N

O

T

N

PN

P

N

E

(a) Interconnections Oxide layer

I

E N+

P N

N+

P

+

N

Capacitor

N+

P

+

N + N

Diode

O

P

N+

P

+

N

Transistor

Resistor

P-type substrate (b)

The structural arrangement of an N-channel JFET is depicted in Fig. 19.29. The processing steps as followed for NPN and PNP transistors are used for JFET fabrication also. The epitaxial layer of the monolithic IC forms the N-channel of the JFET. The P+ gate structure is formed in the N-channel by diffusion process or ion-implantation procedure. The drain and source connections are made through the ohmic contact regions as shown in the Fig. 19.29. The ohmic regions are diffusion regions with N+ regions of higher doping concentration. They provide good ohmic contacts which are only resistive in nature and are not rectifying. Source

P

+

N

+

Gate

P

+

N-channel

p-type substrate

Drain

N

+

P

+

The two types of MOSFET devices, namely, the enhancement type and depletion type can be fabricated. The cross-sectional view of an N-channel enhancement MOSFET is shown in Fig. 19.30. The substrate forms the channel of the MOS transistor. The metallic gate G is grown over an insulating SiO2 layer. This is formed by oxidation process and it is normally 300Å-800Å with extremely high resistances of the order of 1010 MW to 1015 MW. G (Aluminum)

S

D

Thin film oxide (~5000Å–10000 Å)

N

+

N

+

Thin film oxide (~300–800 Å)

P-substrate

The threshold voltage VT of a MOSFET is determined by the gate material, insulation material and its thickness, substrate doping and other process conditions such as impurities in the silicon-insulator surface. The value of VT of the MOSFET normally ranges from 0.4 V for 350nm process to 6 V for a few mm processes. The superior masking properties of Silicon Nitride (Si3N4) make this material an effective dielectric for use in monolithic MOSFET fabrication. The dielectric constant of Si2N4 is 7.5 as compared to 4.0 of SiO2. This higher value of dielectric constant reduces the threshold voltage VT. This makes low voltage and low power circuit designs possible using ICs. Normally, aluminium is used as the gate electrode material. The polycrystalline silicon doped with phosphorous is conductive and it replaces the aluminium gate in recent monolithic fabrication processes. Since the polycrystalline silicon is grown over the silicon dioxide insulator material, it is commonly called polysilicon. The polysilicon gate structure facilitates self-alignment of the gate with the source and drain. The gate electrode is formed earlier than the source and drain diffusions in the fabrication process. This is followed by N+ dopant diffusions in the source and drain regions. The process of self-alignment avoids any masking errors and eliminates any additional capacitance. This structure has the advantage that the isolation island is not required because the drain terminal in an NMOS device is held positive with respect to the source that is tied to the substrate and the current flows only along the channel between the Drain D and the Source S. In BJT, the isolation diffusion occupies a large part of chip area. It is possible to get a higher packaging density with the MOSFET technology, which is 20 times more than that of BJT IC. The Silicon Nitride (Si3N4) has excellent masking properties as compared to SiO2. Therefore, a Si3N4 layer is sandwiched between two SiO2 layers. This prevents the impurities from penetrating through the

SiO2 layer. This structure also reduces the threshold voltage of the transistor, thus making possible to operate at low voltage levels. P-type substrate of moderate doping level. The source and drain regions are formed by diffusing N-type impurities through the masks. Connections to the source and drain are made by a deposited metal layer. Depending upon the type of the device – Depletion-mode or Enhancement-mode, a suitable gate region is formed. The steps involved in the fabrication of an NMOS device are briefly discussed here. Processing takes place on a P-doped silicon crystal wafer on which is grown a ‘thick’ layer of SiO2. 2 to expose the silicon surface in areas where paths in the diffusion layer or source, drain or gate areas of transistors are required. 2 is grown all over the chip area and then polysilicon is deposited on top of this to form the gate structure. The polysilicon layer consists of heavily doped polysilicon deposited by chemical vapour deposition. Further photolithography allows the polysilicon to be patterned as shown in Fig. 19.31(c)

N-type impurities are to be diffused to form the source and drain, as shown in Fig. 19.31(d) Diffusion is achieved by heating the wafer to a high temperature in an ambient of a gas containing the desired N-type impurity. The polysilicon and the underlying thin oxide and the thick oxide act as masks during diffusion, and this is referred to as self-aligning. UV light Mask Photoresis Thick oxide

+

N diffusion (d)

(a) Contact holes (e)

(b)

Patterned metallization

Polysilicon Thin oxide

(c)

2

(f)

is grown all over again and slots are made selectively over the polysilicon, drain, and

To form depletion mode devices, it is only necessary to introduce a masked ion implantation step between steps 1 and 2.

The NMOS and PMOS enhancement devices can be fabricated on the same silicon chip. These devices are called complementary MOSFETs and are abbreviated as CMOS. The four important CMOS process technologies are (i) N-well process (ii) P-well process (iii) Twin-tub process and (iv) Silicon-OnInsulator (SOI) process. In the N-well process, an N-type well or tub is diffused in the P-type substrate. The PMOS transistor M2 is fabricated within this well. The N-well region acts as the substrate for the PMOS transistor. Two additional steps are therefore required in the fabrication of PMOS transistor M2 in comparison with the NMOS transistor M1. The additional processing steps are the formation of N-region and the ionimplantation step of P-type source and drain regions. A typical CMOS inverter circuit and the crosssectional view of the N-well CMOS structure is shown in Fig. 19.32 (a) and (b) respectively. VDD S2 G2

D2

v1

v0

D1 G1

M1 NMOS

PMOS (M2)

NMOS (M1)

S1 (a)

B1

P

+

S1

N

+

G1

M2 PMOS D1

N

+

D2

P

Insulator

G2

S2

+

P N

+

B2

N

+

SiO2

P-substrate (b)

The P-well processes were the commonly used forms of CMOS fabrication and the process steps are similar to N-well process except that the P-well diffusions are formed for fabricating NMOS devices. The P-well processes are preferred in situations where the characteristics of PMOS and NMOS devices are to be more balanced. The twin-tub CMOS process employs both N-well and P-well diffusion regions for fabricating PMOS and NMOS devices respectively in the wells. Therefore, individual optimization for the PMOS and NMOS through the control of VT at other characteristics can be achieved. The emerging process of SOI technology achieves closer packing of PMOS and NMOS transistors and it avoids such problems as latchup and lower parasitic capacitances. In this process, a thin layer of single crystal silicon is epitaxially grown over an insulator such as sapphire or magnesium aluminate spinel. The SOI can also be grown on SiO2 which in turn is grown on silicon material. This is a very popular structure in recent years.

A number of fabrication approaches are available for CMOS devices, which includes the P-well, N-well, twin-tub, and silicon-on-insulator processes. The P-well process is widely used and hence, discussed here. A simplified sketch of different steps involved in CMOS P-well process is illustrated in Fig. 19.33. The structure consists of an N-type substrate in which a deep P-well is diffused. The P-type devices are fabricated in the N-type substrate and the N-type devices are fabricated in the diffused P-well. The fabrication steps involve oxide formation, masking and diffusion. The first step is the formation of the P-type well by diffusing the P-type impurities into the N-type substrate. The depth of this P-well affect the breakdown voltages of the N-transistors. This P-well acts as a substrate for N-devices. The following steps are patterning the oxide layer, forming the thin oxide layer all over the chip area and forming the polysilicon gates for both N-type and P-type devices. The fabrication steps are similar to the fabrication of NMOS devices, discussed earlier.

The next step is diffusing the source and drain regions for the P-type devices and this is done by masking off the P-well completely. The negative of the mask used for this stage of fabrication can be used for the next step, and this masks off the P-type devices completely. Now, the source and drain are diffused for the N-type devices inside the P-well. A thick oxide is formed all over the chip area and then etched selectively for the contact cuts. A layer of metal is deposited and interconnections are made by etching to form the CMOS devices.

A specialized transistor device is required for applications involving low input bias current level, typically less than 1 nA. Since the bipolar transistor usually has low input impedance, it needs larger drive current. To overcome this drawback, the high input impedance characteristics of FET can be utilized. But the FET circuit normally has lower overall voltage gain than a similar BJT-based circuit. In such a situation, the circuit based on a combination of the two technologies, with FET amplifier circuit forming the input stage, and the BJT stage following it provides the designer with the inherent advantages of both the type of devices. Such a combination of Bipolar Junction Transistor and Field Effect Transistor is called a BiFET device. This BiFET device provides very high input impedance as well as high voltage gain of the order of 103.

The fabrication of this device generally requires the addition of one or more masking steps to the basic fabrication process of integrated circuits. A typical structural arrangement of an NPN transistor and a JFET is shown in Fig. 19.34. E

P

N

+

B

C

P

N

N

S

P

+

N

D

G +

P

+

N

N

N

+

P

+

P-type substrate BJT

JFET

Film ICs are broadly classified as Thick film and Thin film circuits. Thin films are the ones whose thickness vary from 50Å to 20000Å and the thick films have thickness that vary between 125000Å and 625000Å. However, the thickness of the film is not a critical tool for classifying, but the technology for fabricating the film classifies whether the film is thin film or thick film. Only passive components like resistors and capacitors can be fabricated using film technology. Conventional film circuits are made by depositing film capacitors and resistors on a non-conducting substrate like glass or ceramic, and pre-fabricated active components are added to the film structure.

Thin films provide greater precision in component values. Thin film deposition can be done using any of the following methods. (i) Vacuum evaporation (ii) Plating technique (iii) Sputtering (iv) Screening technique has already been discussed in Sections. 19.2.6 and 19.3.8. The technique is the same as depositing thin metallic layer for interconnections. Two types of plating techniques are widely in use, viz., electroplating and electrolessplating. Electroplating is a process of coating an object with one or more layers of metals. In thin film fabrication, the substrate (acting as cathode) and the metal (acting as anode) are dipped in an electrolytic solution. When a proper voltage is connected across the substrate and the metal, the metal ions from the anode get deposited on the substrate. Electrolessplating involves reducing a metal ion in a solution to free metal and depositing the same as a coating over the substrate without the use of an electric current. uses a system that is identical to that used for vacuum evaporation. The process of sputtering is carried out at a very low pressure. The source material to be deposited on the substrate is subjected to heavy bombardment by the ions of a heavy inert gas, viz., argon. These ions are accelerated by making

the source material as the cathode of the dc glow discharge. The atoms are given out from the cathode, they migrate away from the cathode through a low pressure inert gas and finally land on the substrate. The high energy possessed by the particles, while landing on the substrate results in a uniform coating over the substrate with good crystal structure and adhesion. The main parts of a sputtering system are shown in Fig. 19.35. Heaters

Support for silicon slice Movable baffle

Vacuum chamber

Evaporating source

A dc potential of about 3 kV is applied between the cathode and the anode, which produces a glow discharge from the cathode that fills completely the inter-electrode space. The screening process uses screen from very fine silk threads and mounted on aluminium frames. The screen is coated with a photo-sensitive emulsion and a mask of desired pattern is kept on it. Then the screen is exposed to light and developed. The screen becomes clear wherever thin film is to be deposited on the substrate and blocked by the photoresist elsewhere. The screen is then placed on the substrate and the components are deposited by driving a squeegee across the patterned screen at a constant rate. The squeegee forces the metal in the paste form through the openings on the screen. The deposited film is developed by firing it in a furnace where the temperature varies from 500oC to 1000oC. The firing process vaporizes the organic binders in the film and the remaining material fuses with the substrate. The following are the major advantages of thin film circuits. (i) Good high frequency package density (ii) High component package density (iii) Resistors can be trimmed to precision (iv) Simple processing techniques The thin film hybrid circuits are used in microwave ICs. Since precision resistors can be fabricated, these ICs are more suitable for ladder type D/A converters.

Thick film technology can be used to fabricate high density circuits containing resistors, conductors and capacitors at low cost. Active components can be added to form a fully functional hybrid circuit.

Thick film circuits are finding a wide range of applications in areas where size and high-frequency requirements are considered important. The technique used for depositing thick films over substrate involves (i) Screen printing and (ii) Substrate firing. The screen printing and the substrate firing processes are essentially the same as that of thin film deposition except that the screen used for thick film deposition is woven from stainless steel wires. The processing equipment for thick film circuits is relatively inexpensive and easy to use. Thin film technology provides greater precision in manufacturing but is more costly than thick film technology. The following are the advantages of thick film hybrid circuits. 1. Low fabrication cost 2. Good high frequency response 3. Very low tolerance because of trimming 4. Highly stable and reliable over a long run 5. Simple fabrication steps The thick film circuits are used in automobile electronic circuits, digital watches, and electronic toys and also in telecommunication circuits and computers.

Gallium arsenide is a compound semiconductor made of a compound of two elements. Gallium having three valence electrons can be combined with arsenic, which has five valence electrons to form the compound GaAs. Figure 19.36 shows the arrangement of atoms in a gallium arsenide substrate. The gallium and arsenic atoms are alternatively positioned in exact crystallographic locations. Being a binary semiconductor, GaAs requires special care to avoid high temperatures during processing to prevent dissociation of the surface. This is one of the basic difficulties in the growth of bulk GaAs material. Key Ga As

Group IV elements such as silicon can act as either donors (on Ga sites) or acceptors (on As sites). The covalent radius for Ga is 1.26 Armstrong units and As is 1.18 Armstrong units. As the silicon atoms are larger in size than arsenic, they tend to occupy gallium sites. Thus, silicon in GaAs is used as the dopant for the formation of N-type material. Figure 19.37 gives the structure of N-type GaAs material. Key Ga As Si (dopant atom)

Beryllium (Be) or magnesium (group II) can be used for the formation of P-type material. Beryllium being the lightest P-type dopant for GaAs, deep implantation of the dopant atoms can be accomplished. However, magnesium is also used as a suitable dopant in a number of processes.

Gallium arsenide is a direct gap semiconductor, with its valence band maximum and conduction band minimum occuring at the same wave vectors. This means little momentum change is necessary for transition of an electron from the conduction band to the valence band. This property makes the GaAs an excellent light-emitting diode. For the GaAs effective mass of the electrons traveling through the crystal is 0.067 times the mass of a free electron. This means electrons travel faster in gallium arsenide than in silicon. Gallium arsenide has a superior electron mobility characteristic because of the shapes of their conduction bands as shown in Fig. 19.38. Electron energy, eV

Conduction band Upper valley

1.5

Lower valley

1.0 0.5

1.4 eV

0 –0.5

Valence band

0

Electron momentum

As a result of considerable development in GaAs integrated circuitry and the technology, GaAs devices are widely gaining popularity. The GaAs devices provide the following typical characteristics: • less than one-micron gate geometry • less than two-micron metal pitch • up to four-layer metal • ON and OFF devices • Four-inch diameter wafers • Suitability for clock rates in the range of 1 GHz–2 GHz.

The salient features of this technology include: • Improved electron mobility over the silicon technology, resulting in very fast electron transit times. • The saturation velocity for GaAs occurs at a lower threshold filled than for silicon. • Large energy band gap offers bulk semi-insulating substrate with resistivities in the order of hundred to thousands of megaohms-cm. • GaAs devices operate over a wider temperature range (– 200°C to + 200oC) • Direct bandgap allows GaAs to be used as light emitters. • Less power dissipation compared to silicon technology.

A number of devices have been developed in the last few years using GaAs technology, which includes: • Depletion-mode metal semiconductor field-effect transistor, D-MESFET • Enhancement-mode metal semiconductor field-effect transistor, E-MESFET • Enhancement-mode junction field-effect transistor, E-JFET and • Complementary enhancement-mode junction field-effect transistor, CE-JFET. The devices developed in the initial periods of introduction of GaAs technology have exhibited switching delays as low as 70 psec to 80 psec while dissipating power of the order of 1.5 mW to 150 microwatts. These devices are called the first generation devices. Much improvement in the electron mobility (upto five times greater than the first generation) could be achieved in the second generation devices, such as • High electron mobility transistor, HEMT • Heterojunction bipolar transistor, HBT

The processing of a GaAs MESFET is relatively simple and requires only about 8 masking stages. The structure of the basic MESFET using GaAs technology consists of a thin N-type active region bridging two ohmic contacts with a narrow metal schottky barrier gate that separates the more heavily doped drain and source. Fabrication involes photolithography, and ion implantation into semi-insulating GaAs structure. GaAs MESFETs are similar to silicon MOSFETs. The difference is the presence of a Schottky diode at the gate region.

A cross sectional view of the structure of GaAs D-MESFET is shown in Fig. 19.39. A thin N-type region joins two ohmic contacts with a narrow metal Schottky barrier gate. In the process of fabricating the depletion-mode MESFET, the N-type dopants having a concentration density of approximately 1017 cm– 3 are directly implanted into the semi-insulating GaAs substrate to form the channel and the more heavily doped source and the drain. The gate and the first level interconnect metallizations are deposited by E-beam evaporation techniques. The transconductance of the device is determined by the gate length and its position relative to the drain and source contacts.

The fabrication process is illustrated in Fig. 19.39. Initially, the GaAs substrate is coated with the first level of insulator, a thin layer of silicon nitride. This thin film of insulator remains on the wafer throughout the processing steps and allows the annealing of GaAs at temperatures of up to 900 degrees centigrade. The second step is the formation of the N-type active layer, by direct ion implantation into the GaAs substrate. The Silicon nitride insulating layer is cut to make a window using photolithography processes for ion implantation of the N-active layer. Implantation of dopant ions takes place at about 200 to 230 keV to an impurity concentration of up to 1012 cm– 2. There are only two main steps involved—formation of a shallow N-channel layer with high resistivity, and a deep n+ layers for source and drain. The wafer is then coated with the interleaved SiO2 by chemical vapour deposition, and this layer provides protection against physical damage. This step is followed by encapsulation. Encapsulation is important as it prevents out-diffusion of arsenic, brought about as the result of high vapour pressure of GaAs when exposed to high temperatures. The next step in the process is formation of gates, the ohmic contacts and the first-level metal interconnects. The metals used must have a very low contact resistance. The ohmic contacts between the metal interconnect and the source and drain are deposited by evaporation using E-beam technology. A thin layer of gold-germanium-platinum alloy is used for contacts. The following processes accomplish the first-level metallization, delineating photoresist patterns, plasma etching the underlying insulator, deposition of the metal on GaAs wafer by sputtering and photoresist lift-off. Second-level metallization entails magenetron sputtered titanium/gold alloy, which is followed by filling the via between first-level and second-level metal. The final step in the fabrication is passivation and is used to protect the wafer from contamination. Passivation layer is deposited at low temperature, using plasma-enhanced chemical vapour deposition (CVD) process.The final structure of GaAs MESFET is shown in Fig. 19.40.

Source

Schottky barrier gate Drain Gate

N

+

N

+

N

+

Shallow N-channel Semi-insulating GaAs substrate

Process technology has progressed, and more complex chips are constantly increasing. For high speed and low noise applications, bipolar technology is preferred. Since the heat dissipation in bipolar circuits is comparatively large, elaborate heat dissipation capabilities are required. The MOS technology is becoming popular due to the high component density that can be achieved. Originally, PMOS devices were used but now NMOS technology is predominant due to high-speed performance. The CMOS technology leads the NMOS with its extremely low static power dissipation. The feature size of the devices is also decreasing rapidly. In 1990s the minimum feature size for CMOS was 0.5 mm, which reduced to 0.12 mm in the year 2002 and it is predicted that 35 nm devices will be available for production by 2010. Gallium Arsenide (GaAs) technology is also advancing and this semiconductor material is found suitable for military and aerospace applications. They exhibit better performance characteristics than silicon, due to its higher carrier mobility. The electron-beam photolithographic techniques lost its place due to increasingly lower feature sizes of the devices and X-rays are exclusively in use. New techniques such as Extreme Ultraviolet (EUV) lithography and electron beam lithography such as Scattering with Angular Limitation Projection Electron-Beam Lithography (SCALPEL) are being used for sub-micron size devices. The interconnections inside the chip start demanding more attention and research. They move from aluminium to copper, and optical interconnections may soon arrive. The IC design engineers develop and use advanced Electronic Design Automation (EDA) tools that can aid in the fabrication of ICs. Such Computer Aided Design (CAD) tools are being used for the full flow of IC fabrication processes, from high level synthesis of system, logic synthesis, circuit optimization, layout simulation, design verifications to final testing. An emerging technology is the BiCMOS which makes use of the advantages of both bipolar and CMOS devices on the same chip. These devices are capable of driving much higher loads, and faster as compared to CMOS, at the cost of higher fabrication costs. The silicon-on-insulation technology enables easy integration of analog and digital circuits using a novel substrate technology. It shows better performance characteristics against cross-talk. The integrated circuit technology has made possible the evolution of low-power displays and faster and denser memory packages.

Packaging technology has improved greatly from the earlier Dual-in-line-packages (DIP) for ICs with number of pins less than 64. Pin-through-hole (PTH), surface–mounted technology (SMT), Pin-Grid Array (PGA) packages with higher pin count and better power dissipation characteristics, Ball-Grid Arrays (BGA) to reduce parasitics for higher performance chips, Quad-Flat Packs (QFP) with very high pin counts (up to 500) are becoming popular in recent years. Multi-Chip Modules (MCM) are being fabricated for very high performance requirements with multiple chips assembled on a common substrate placed in a single package. This arrangement makes the critical interconnections among the chips possible within the package.

The operational amplifier, or op-amp, was originally developed in response to the needs of the analog computer designers. An op-amp is a high gain, direct-coupled amplifier. The voltage gain can be controlled by externally providing feedback. The op-amp can be used in almost any d.c. to 1 MHz amplifier and signal processing applications. Operational amplifiers can be designed with various types of active devices, however, IC technology is remarkably successful in offering low-cost, high-performance, versatile and economic op-amps; thus becoming a widely accepted building block of modern signal processing and conditioning techniques.

The “ideal” operational amplifier is a differential input, single-ended output device. The characteristics of an ideal op-amp are as follows: 1. Infinite input resistance, Ri = infinity 2. Zero output resistance, Ro = 0 3. Infinite voltage gain, AV = infinity 4. Infinite bandwidth, BW = infinity 5. Infinite common-mode rejection ratio 6. Infinite slew-rate 7. Zero offset, i.e. when V1 = V2, Vo = 0 8. Characteristics do not drift with temperature. The advantage of an ideal op-amp is that it can be used to perform a large number of mathematical operations, or generate a number of circuit functions by applying passive feedback around the amplifier. If the input and output impedance levels are respectively high and low with respect to the feedback impedances (connected externally), and if the voltage gain is sufficiently high, then the resulting amplifier performance becomes solely determined by the external feedback components.

V1

+

V2

–

A

V0

Figure 20.1 shows the schematic symbol of an op-amp. It has two inputs and one output. The upper input is called the noninverting input and is marked with a plus sign to indicate that Vo is in phase with V1. The lower input is known as the inverting input; it is marked with a minus sign to indicate that Vo is 180° out of phase with V2. If the overall voltage gain of the op-amp is A, then Vo = A(V1 – V2)

(20.1)

Thus the output voltage is equal to the voltage gain times the difference of the two input voltages.

The first stage of an op-amp is almost a differential amplifier and the last stage is usually a class B push– pull emitter follower. Figure 20.2(a) shows the block diagram of a typical op-amp and Fig. 20.2(b) shows a simplified schematic diagram for a typical op-amp. This circuit is equivalent to the 741 and many later-generation op-amps. Dual-input unbalanced output differential amplifier

Non-inverting input Input stage Inverting input

Dual-input balanced output differential amplifier

Inter mediate stage

Complementary symmetry pushpull amplifier

Level shifting stage

Output stage

Output

Emitter follower with constant current source

The input stage is a dual-input, balanced-output differential amplifier. This stage provides most of the voltage gain of the amplifier and also establishes the input resistance of the op-amp. In Fig. 20.2(b), Q13 and Q14 form a current mirror circuit. Therefore, Q14 sources tail current to the input differential amplifier stage (Q1 and Q2). The differential amplifier drives a current mirror consisting of Q3 and Q4. An input signal Vin produces an amplified current out of this mirror that goes into the base of Q5. The input stage should have the following characteristics: (i) High input resistance (typ. 10 M ohm) (ii) Low input bias current (typ. 0.5 A) (iii) Small input offset voltage (typ. 10 mV) (iv) Small input offset current (typ. 0.2 mA) (v) High CMRR (typ. 70 dB) (vi) High open-loop voltage gain (typ. 104)

VCC Q13

Q12

Q14

Q11 R3

R2 –

–

Q8 Vout

Q7 CC Q10

+

Vin +

–

Q2

Q1

Q5

Q4 Q6 Q3 R1 – VEE

In most of the amplifiers, an intermediate stage (dual input, unbalanced output differential amplifier) is provided which increases the overall gain of the op-amp. Because of direct coupling between the first two stages, the d.c. level at the output of the intermediate stage is well above the ground potential. This requires a level translator as the succeeding stage in order to bring the d.c. level back to the ground potential.

The level shifter (translator) circuit is used after the intermediate stage to shift the d.c. level at the output of the intermediate stage downward to zero volts with respect to ground. Usually, the third stage is an emitter follower (Q5) using constant current source. It steps up the input impedance of the stage consisting of Q6 by a factor of BETA. Note that Q6 is the driver for the output stage. Incidentally, the

plus sign on the Q5 collector means it is connected to the VCC supply, similarly, the minus signs at the bottom of R2 and R3 mean these are connected to the VEE supply.

The last stage is a complementary symmetry push–pull amplifier (Q9 and Q10). Q11 is part of a current mirror that sources current through the compensating diodes (Q7 and Q8). Q12 is the input half of the mirror, and biasing resistor R3 sets up the desired mirror current. CC, called as a compensating capacitor (typically 30 pF), has a pronounced effect on the frequency response. It is needed to prevent oscillations and unwanted signals produced within the amplifier. The output stage should have the following desirable properties: (i) Large output voltage swing capability. (ii) Large output current swing capability. (iii) Low output resistance. (iv) Short circuit protection. An emitter follower as the output stage can provide low output resistance and class B and class AB stage can provide large amount of output power.

The electrical parameters of the operational amplifier are defined in the following paragraphs. The input voltage is the error voltage needed to null or zero the quiescent outan op-amp to null the output. For instance, the 741 has a worst-case input offset voltage of 5 mV, i.e., when using 741 ICs, we have to apply a difference input of up to 5 mV to null the quiescent output voltage. The smaller the value of input offset voltage, the better the input terminals are matched. Op-amp fabrication uses monolithic integrated circuit construction, which can produce very well-matched devices for input stages, etc. by using identical geometry for a pair of devices diffused at the same time on the same chip. Nevertheless, there is always some mismatch, which gives rise to the input offset current. The input offset current is the difference between the two input currents. The 741 has an input offset current of 20 nA. When working with 741 ICs, we may find 20 nA more current in one base than the other. These unequal base currents produce a false difference voltage that gets amplified to produce a false output voltage. The smaller the input offset current, the better is the op-amp’s performance. Input bias current is the average of the currents that flow into the inverting and non-inverting input terminals of an op-amp. Input bias current affects all applications of op-amps. For the op-amp to function, it is necessary to supply a small current, from picoamperes for op-amps with FET inputs to microamperes for junction transistor type inputs. The smaller the input bias current, the smaller the possible unbalance. The 741 has an input bias current of 80 nA. The common-mode rejection ratio (CMRR) serves as a figure of merit of an op-amp and is defined as the ratio of the differential voltage gain Ad to the common-mode voltage gain Acm; that is, Ad CMRR = ____ (20.2) Acm

| |

The differential voltage gain, Ad , is the gain of the op-amp when two different voltages are applied at the two inputs and is same as the large-signal voltage gain, which is specified on the data sheet. The common-mode voltage gain, Acm , is the gain of the op-amp when the two terminals of the op-amp are applied with the same voltage from the same source. Generally, the common-mode voltage gain is very small and the differential voltage gain is very large; therefore, the CMRR is very large. Ideally, an op-amp has zero common-mode voltage gain and hence, the CMRR is infinite. CMRR, being a very large value, is normally expressed in decibels. For 741 ICs, CMRR is 90 dB typically. The higher the value of CMRR, the better is the matching between two input terminals and the smaller is the output common-mode voltage. A high CMRR means that the op-amp has a better ability to reject commonmode signals like electrical noise.

For a given op-amp, CMRR = 105 and differential gain Ad = 105. Determine the common-mode gain Acm of the op-amp.

Solution Ad CMRR = ____ = 105 Acm Ad Therefore, the common-mode gain, Acm = _______ CMRR 105 = ___5 = 1 10 The two input terminals of an op-amp are connected to voltage signals of strength 745 V and 740 V respectively. The gain of the op-amp in differential mode is 5 × 105 and CMRR is 80 dB. Calculate the output voltage and % error due to common mode.

Solution

Therefore,

Given

CMRR = 80 dB, V1 = 745 mV, V2 = 740 mV, Ad = 5 × 105 Ad CMRR in dB = 20 log ___ Ac 5 × 105 80 = 20 log _______ Ac

i.e. Hence, common mode gain

5 × 105 10000 = _______ Ac Ac = 50

V1 + V2 Output = AdVd + AcVc, where Vc = _______, Vd = V1 – V2 2

[

]

745 +740 = 5 × 105 [745 – 740] × 10 – 6 + 50 × _________ × 10 – 6 2 = 2.5371 V Ideal output

AdVd = 2.5 V 2.5371 – 2.5 % error = ___________ × 100 = 1.484% 2.5

Hence,

Slew rate is an important parameter because it limits the bandwidth for large signals. Slew rate limiting affects all amplifiers where capacitance on internal nodes, or as part of the external load, has to be charged and discharged as voltage levels change. It is defined as the maximum rate of change in output voltage per unit of time and is expressed in volts per microseconds, i.e., dVo SR = ____ V/ms (20.3) dt max

|

Slew rate indicates how fast the output of an op-amp can change in response to changes in the input frequency. For example, the op-amp 741 has a slew rate of 0.5 V/ms and its implication can be explained by considering Fig. 20.3. If we overdrive a 741 with a large step input (Fig. 20.3 a), the output slews as shown in Fig. 20.3b. It takes 20 microseconds (SR = 0.5 V/ms, i.e. for 0.5 volt change, 741 takes 1 microseconds; therefore for 10 volts change, it takes 10/0.5 = 20 microseconds) for the output voltage to change from 0 to 10 V. It is impossible for the 741 to change faster than this.

Overdrive

+ 10 V

0

0

20 ms (b)

(a)

Slew rate limiting can occur even with a sinusoidal signal. Figure 20.4(a) shows a sinusoidal output with a peak of 10 V. The initial slope of the sine wave where it passes through zero is important. As long as this initial slope is less than the slew rate of the op-amp, there is no problem. But when the frequency increases, the initial slope of the sine wave may be greater than the slew rate, and this results + 10 V

+ 10 V

Slope > SR

0

Slope £ SR

– 10 V (a)

– 10 V (b)

in the distortion of the output waveform as shown in Fig. 20.4(b). The higher the frequency is, the smaller is the swing and the output waveform will be more triangular. Generally, the slew rate is specified for unity gain and hence, let us assume that a high frequency, large amplitude sinusoidal input is given to an op-amp voltage follower. The equation for the input sinusoidal signal is thus, Vs = Vm sin w t

(20.4)

With no slew rate limitations, the output voltage of the voltage follower is thus, Vo = Vm sin w t The rate of change of the output is, dV ____o = wV cos w t m dt The maximum rate of change of the output occurs when cos w t = 1, i.e., dV ____o (max) = wV m dt Thus, the slew rate is,

(20.5)

(20.6)

(20.7)

dVo SR = ____ (max) = 2p fVm V/s dt = 2p f Vm 10 – 6 V/ms

(20.8)

Equation (20.8) suggests that for faithful reproduction of the sinusoid, wVm must be less than or equal to the slew rate. For distortionless output, the slew rate determines the maximum frequency of operation, fmax, for a desired output swing. The frequency fmax is called full power bandwidth and is defined as the maximum frequency at which an undistorted sinusodial output can be obtained with peak voltage Vm. For the most general purpose op-amps, full power bandwidth ranges from 5 to 50 kHz for a peak output swing of 10 V.

The output voltage of a certain op-amp circuit changes by 20 V in 4 s. What is its slew rate?

Solution The slew rate,

dVo SR = ____ dt 20 V = _____ = 5 V/ms 4 ms

The 741C is used as an inverting amplifier with a gain of 50. The sinusodial input signal has a variable frequency and maximum amplitude of 20 mV peak. What is the maximum frequency of the input at which the output will be undistorted? Assume that the amplifier is initially nulled.

Solution

The 741C has a typical slew rate of 0.5 V/ s. Using Eq. (20.8), the slew rate is, 2 f Vm SR = _______ = 0.5 V/ s 106

The maximum output voltage, Vm = A Vid = 50 × 20 mV = 1V ( peak) The maximum frequency of the input for which undistorted output is obtained is given by, SR fmax = _____ × 106 2 Vm 0.5 = ______ × 106 = 79.6 kHz 2 ×1

An inverting amplifier using the 741C must have a flat response up to 40 kHz. The gain of the amplifier is 10. What maximum peak-to-peak input signal can be applied without distorting the output?

Solution

The 741C has a typical slew rate of 0.5 V/ s. Using Eq. (20.8), the slew rate is, 2 fVm SR = ______ = 0.5 V/ s 106

SR × 106 The maximum output voltage, Vm = ________ 2 f 0.5 × 106 = ____________3 = 1.99 V peak 2 × 40 × 10 = 3.98 V peak-to-peak The maximum peak-to-peak input voltage for undistorted output is, Vm 3.98 vid = ___ = ____ = 0.398 V peak-to-peak. A 10 The voltage gain of the op-amp decreases at high frequencies. This is due to the parasitic junction capacitance and minority-carrier charge storage in devices making up the circuit. This aspect of op-amp is characterised by the gain-bandwidth product, which is the bandwidth of the op-amp when the voltage gain is unity. Equivalent terms for gain-bandwidth product are closedloop bandwidth, unity gain bandwidth and small-signal bandwidth. For general purpose op-amps, the gain-bandwidth product is in the 1 to 20 MHz range.

The op-amp having bipolar input stage has an input resistance in the range of 100 kW to 1 MW. Usually, the voltage gain is large enough that this input resistance has little effect on circuit performance in closed-loop feedback configurations. FET input stages have very high input resistance. The output resistance of general purpose op-amps is in the order of 40 to 100 W. This resistance does not significantly affect the closed-loop performance of the op-amp.

The equivalent circuit of an op-amp is shown in Fig. 20.5. The equivalent circuit is useful in analyzing the operating principles of op-amps and in observing the effects of feedback. This circuit includes the values of open-loop gain A, input resistance Ri and output resistance Ro. The voltage source AVid is an equivalent Thevenin voltage source, and Ro is the Thevenin equivalent resistance looking back into the output terminal of an op-amp.

For the circuit shown in Fig. 20.5, the output voltage is Vo = AVid = A(V1 – V2) where

(20.9)

A = large-signal voltage gain Vid = difference input voltage V1 = voltage at the noninverting input terminal V2 = voltage at the inverting input terminal.

The output voltage is directly proportional to the algebraic difference between the two input voltages. In other words, the op-amp amplifies the difference between the two input voltages; it does not amplify the input voltages themselves. The polarity of the output voltage depends on the polarity of the difference voltage.

The equation for the output voltage of an op-amp, as given by Eq. (20.9), is used in analysing the characteristics of an op-amp. In Fig. 20.6, the output voltage of an ideal op-amp is plotted as a function of input differential voltage, keeping the large signal gain constant. We notice that for very small values of the input differential voltage the output voltage increases linearly, however, the output voltage cannot exceed the saturation voltages. The saturation voltages are a function of the supply voltages. The output voltage is directly proportional to the input difference voltage only until it reaches the saturation voltages and thereafter output voltage remains constant. The curve plotted in Fig. 20.6 is called an ideal voltage transfer curve because output offset voltage is assumed to be zero. The curve, if drawn to scale, would be almost vertical because of the very large values of the large-signal gain, A.

Vo Positive saturation voltage + Vsat < + VCC

Slope = A – Vid

+ Vid

Negative saturation voltage – Vsat < – VEE

The term open-loop indicates that no feedback, in any form, is given to the input from the output. When connected in open-loop, the op-amp functions as a very high gain amplifier. There are three open-loop configurations of op-amp, namely, 1. Differential amplifier 2. Inverting amplifier 3. Noninverting amplifier. The above configurations are classified based on the number of inputs used and the terminal to which the input is applied. The op-amp is a versatile device and it amplifies both a.c. and d.c. input signals. Thus, the input signals can be either a.c. or d.c. voltages.

In this configuration, the inputs are applied to both the inverting and the noninverting input terminals of the op-amp and the device amplifies the difference between the input voltages. Figure 20.7 shows the open-loop differential amplifier. The input voltages are represented by Vin1 and Vin2. The source resistance Rin1 and Rin2 are negligibly small in comparison with the very high input resistance of the op-amp, and thus the voltage drop across these source resistances are assumed to be zero. The output voltage Vo is given by Vo = A(Vin1 – Vin2)

(20.10)

where A is the large-signal voltage gain. Thus, the output voltage is equal to the voltage gain, A, times the difference between the two input voltages. This is why this configuration is called a differential amplifier. In open-loop configurations, the large-signal voltage gain A is also called open-loop gain.

In this configuration, the input signal is applied to the inverting input terminal of the op-amp and the noninverting input terminal is connected to the ground. Figure 20.8 shows the open-loop inverting amplifier. The output voltage is 180° out of phase with respect to input and hence, the output voltage Vo is given by Vo = – AVin

(20.11)

Thus, in an inverting amplifier the input signal is amplified by the open-loop gain A and is also phase shifted by 180°.

Figure 20.9 shows the open-loop noninverting amplifier. The input signal is applied to the noninverting input terminal of the op-amp and the inverting input terminal is connected to the ground. The input signal is amplified by the open-loop gain A and the output is in phase with the input signal. Vo = AVin

(20.12)

In all the above open-loop configurations, only very small values of input voltages can be applied. Even for voltage levels slightly greater than zero the output is driven into saturation, which is obvious from the ideal transfer characteristics of op-amp shown in Fig. 20.6. Thus, when operated in the open-loop configuration, the output of the op-amp is either negative or positive saturation or switches between positive and negative saturation levels. This prevents the open-loop configurations of op-amps from being used in linear applications.

In open-loop configurations, clipping of the output waveform occurs when the output voltage exceeds the saturation levels. This is because of very high open-loop gain of the op-amps and due to this fact only the smaller signals, of the order of microvolts or less, having very low frequency can be amplified accurately without distortion. However, signals of this magnitude are very susceptible to noise and almost impossible to obtain in the laboratory. The open-loop gain of the op-amp is not a constant and varies with changing temperature and power supply. Also, the bandwidth of most open-loop op-amps is negligibly small. This makes the open-loop op-amps unsuitable for a.c. applications. The open-loop bandwidth of the 741 is approximately 5 Hz, but in almost all a.c. applications the bandwidth requirement is much larger than this. For the reasons stated, the open-loop op-amp is generally not used in linear applications. However, the open-loop op-amp configurations are also useful in certain nonlinear applications like square-wave generation, a stable multivibrator etc.

The op-amp can be effectively utilized in linear applications by providing feedback from the output to the input either directly or via another network. If the signal fed back is out of phase by 180° with respect to the input, then the feedback is referred to as negative feedback or degenerative feedback. Conversely, if the signal fed back is in phase with that at the input, then the feedback is referred to as positive feedback or regenerative feedback. An op-amp that uses feedback is called as a closed-loop amplifier. The most commonly used closedloop configurations are (i) Inverting amplifier (voltage shunt feedback) and (ii) Noninverting amplifier (voltage series feedback).

The inverting amplifier is shown in Fig. 20.10(a), and in Fig. 20.10(b), the same inverting amplifier is redrawn in a different way so as to illustrate how voltage shunt feedback is provided. The input signal drives the inverting input of the op-amp through resistor R1.

f

f

The op-amp has an open-loop gain of A, so that the output signal is much larger than the error voltage. Because of the phase inversion, the output signal is 180° out of phase with the input signal. This means the feedback signal opposes the input signal and the feedback is negative or degenerative. The open-loop gain of an op-amp is extremely high, typically 200,000 for a 741. If the output voltage is 10 V, the input differential voltage, Vid, is only Vo 10 Vid = ___ = _______ = 0.05 mV A 200,000 Furthermore, the open-loop input impedance of a 741 is around 2 M . Therefore, for an input differential voltage of 0.05 mV, the input current is only Vid 0.05 mV iin = ___ = ________ = 0.025 nA. Rin 2M Since the input current is so small compared to all other signal currents, this can be approximated to zero. For any input voltage applied at the inverting input, the input differential voltage, Vid, is negligibly small and the input current is ideally zero. Hence, the inverting input appears to be a ground point for all input voltages. Hence, the inverting input of Fig. 20.10(a) acts as a virtual ground. The term virtual ground signifies a point whose voltage with respect to ground is zero, and yet no current can flow into the point. The expression for the closed-loop voltage gain of an inverting amplifier can be obtained from Fig. 20.10(a). Because the inverting input is a virtual ground, all of the input voltage appears across R1. This sets up a current through R1 that equals,

Vin i1 = ___ R1

(20.13)

All of this current must flow through RF, because the virtual ground accepts negligible current. The left end of RF is ideally grounded, and so the output voltage appears wholly across it. Therefore, RF Vo = –i2RF = – i1RF = – ___ Vin R1

(20.14)

The closed-loop voltage gain, AF , is given by Vo RF AF = ___ = – ___ Vin R1

(20.15)

The above equation shows that the gain of the inverting amplifier is set by selecting a ratio of feedback resistance RF to the input resistance R1. The ratio RF /R1 can be set to any value, even to less than 1. Because of this property of the gain equation, the inverting amplifier configuration with feedback is more popular and lends itself to a majority of applications.

For the inverting amplifier of Fig. 20.10, RF = 10 k and R1 = 1 k . Calculate the closed-loop voltage gain AF.

Solution

RF The closed-loop voltage gain AF = ___ R1 10 kW = ______ = – 10 1 kW

The noninverting amplifier with negative feedback is shown in Fig. 20.11. The input signal drives the noninverting input of the op-amp. The op-amp provides an internal gain, A. The external resistors R1 and RF form the feedback voltage divider circuit. Since the returning feedback voltage drives the inverting input, it opposes the input voltage and hence, the feedback is negative or degenerative. The feedback factor of the feedback voltage divider network is R1 b = _______ R1 + RF

(20.16)

Therefore, the approximate closed-loop gain is 1 R1 + RF AF ª __ = _______ R1 b RF = 1 + ___ R1

(20.17) (20.18)

From the above equation, it is noted that the closed-loop gain is always greater than 1 and depends on the ratio of the feedback resistors. If precision resistors are used in the feedback network, a precise value

of closed-loop gain can be achieved. The closed-loop gain does not drift with temperature changes or op-amp replacements.

For the non-inverting amplifier of Fig. 20.11, R1 = 1 k and RF = 10 k . Calculate the closed-loop voltage gain of the amplifier and the feedback factor .

Solution

RF The closed-loop voltage gain, AF = 1 + ___ R1 10 kW = 1 + ______ = 11 1 kW

The feedback factor,

R1 b = _______ R1 + RF 1 kW = ____________ = 0.091 1 kW + 10 kW

The bandwidth of an amplifier is defined as the range of frequencies for which the gain remains constant. The gain-bandwidth product of an op-amp is always a constant. The gain of an op-amp and its bandwidth are inversely proportional to one another. The bandwidth of an op-amp can be increased by providing feedback signal to its input. Consider the following statement. The product of closed-loop gain and closed-loop bandwidth is same as the product of open-loop gain and open-loop bandwidth. That is, AF ×BWcl = A × BWol (20.19) The op-amp 741 has an open-loop gain of 200,000 and a bandwidth of about 5 Hz. Therefore, the product of its open-loop gain and bandwidth is

A × BWol = 200,000 × 5 Hz = 1 MHz. The open-loop gain-bandwidth product of a 741 is 1 MHz. The left-hand side of Eq. (20.19) is the product of closed-loop gain and closed-loop bandwidth. No matter what the values of R1 and RF, the product of closed-loop gain and closed-loop bandwidth must equal the open-loop gain-bandwidth product, i.e. for 741 the closed-loop gain-bandwidth product must also be 1 MHz. The open-loop response is shown in Fig. 20.12. The open-loop gain has a maximum value of 200,000. When the operating frequency increases to 5 Hz, the open-loop gain is down to 0.707 of its maximum value. The gain keeps dropping off with increasing frequency. After the upper cut-off frequency, fOL, the gain drops by 20 dB/decade. The unity-gain frequency is the frequency where the open-loop gain has decreased to unity. In Fig. 20.12, funity equals 1 MHz. fOL

If the feedback resistors are changed, the closed-loop gain will change to a new value and so will the closed-loop cut-off frequency. But, because the gain-bandwidth product is constant, the closed-loop curve superimposes the open-loop curve beyond cut-off frequency.

100,000

Open-loop gain

10,000

Voltage gain

The curve in Fig. 20.12 represents the closedloop response of an op-amp. It can be seen from this figure that the open-loop gain decreases continuously until it approaches the value of closed-loop gain. Then, the closed-loop gain starts to decrease and at fCL, the closed-loop gain is down to 0.707 of its maximum value. Thereafter, both the curves superimpose and decrease to unity at funity.

1,000

Closed-loop gain

100 fCL 10 funity 1 1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz Frequency

Noise is a major source of interference with the desired signal in electronic systems. Any unwanted signal associated with the desired signal is noise. Noise is random in nature and difficult to predict or analyze. In any electronic system, noise can come from many external sources as well as be self-induced, a result of the circuitry itself. Examples of external noise sources are switching or rotating machinery, ignition systems, and various control circuits. Natural phenomena such as lightning may also be an external noise source. The internal noise may be caused by the a.c. random voltages and currents generated within the conductors and semiconductors of one circuit as a result of the switching of another circuit. The rate of change of current and voltage per unit of time, the speed of operation of the circuit, and the type of coupling between two circuits are some of the factors that determine the amount of noise induced in a given circuit.

Different types of noise phenomena are associated with op-amps: Schottky noise, thermal noise, and 1/f noise are the most important. The thermal noise increases with an increase in temperature. Like thermal noise, the amount of Schottky noise is greater with wider bandwidths and larger resistances; on the other hand, 1/f noise increases with a decrease in frequency f. Wider bandwidths of operation for a given value of source resistance generate more noise; also, larger source resistances for a given bandwidth increase the noise level appreciably. To reduce the effect of electrical noise on ICs, several schemes have been commonly used. Physical shielding of the ICs and associated wiring helps to prevent external electromagnetic radiation from inducing noise into the internal circuity. Special buffering and filtering circuits can be used between the electronic circuits and signal leads. To provide a path for any radio frequency (RF), all linear IC power supply terminals should generally be bypassed to ground. The breadboard layout should be such that the bypass capacitors are as near the IC terminals as possible. Internal noise generation can be reduced by keeping input and output lead lengths as short as practically possible. One common tie point should be used near the IC for all grounds. In a high electrical noise environment, an IC with a high degree of noise immunity will minimize the amount of special care needed for proper circuit operation.

In Sec. 20.9, we saw that the gain of an op-amp is frequency dependent. The gain A decreases as the operating frequency increases. This variation in gain as a function of frequency imposes a limitation on the performance and applications of the op-amps. In this section, the factors responsible for variations in open-loop gain as a function of frequency are investigated. The gain of the op-amp is a complex number which is a function of frequency. At a given frequency, the gain will have a specific magnitude as well as a phase angle. This means that the variation in operating frequency will cause the variation in gain magnitude and its phase angle. The manner in which the gain of the op-amp responds to different frequencies is called the frequency response. Generally, for an amplifier, as the operating frequency increases, the gain of the amplifier decreases, and the phase shift between the output and input signals increases. In the case of an op-amp, the change in gain and phase shift as a function of frequency is attributed to the internally integrated capacitors, as well as the stray capacitors. These capacitors are due to the physical characteristics of semiconductor devices and the internal construction of the op-amp. The magnitude plot shows the way in which the gain of the op-amp changes with variation in frequency. The later-generation op-amps, such as the 741, 351 and 771, have phase shifts less than 90° even at cross-over frequencies. The cross-over frequency, also referred to as the unity gain bandwidth (UGB), is the maximum usable frequency of a given op-amp. The UGB, the range of frequencies upto to funity in Fig. 20.12, is 1 MHz for 741 op-amp. The rate of change of gain as well as the phase shift can be changed using specific components with the op-amp. The most commonly used components are resistors and capacitors. The network formed by such components and used for modifying the rate of change of gain and the phase shift is called a compensating network. The phase lag and phase lead networks are the most commonly used compensating networks in op-amps. These two networks are indicative of their functions since phase lag contributes a negative phase angle and phase lead a positive phase angle. Thus, the main purpose of the compensating networks is to modify the performance of an op-amp circuit over the desired frequency range by controlling its gain and phase shift.

In internally compensated op-amps, the compensating network is designed into the circuit to control the gain and the phase shift of the op-amp. The op-amp 741C is an internally compensated opamp. The open-loop frequency response curve for internally compensated op-amps is same as that shown in Fig. 20.12. For internally compensated op-amps like 741, the gain remains essentially constant from 0 Hz to the upper cut-off frequency fOL and thereafter rolls off at a constant rate of 20 dB/decade. Thus, the open-loop bandwidth is the frequency band extending from 0 Hz to fOL, or simply fOL. In the 741 op-amp, a 30 pF capacitor is the internal compensating component (CC in Fig. 20.2(b)), which helps to control the open-loop gain to allow it to roll off at a rate of 20 dB/decade. In fact, even if the 741 is configured as a closed-loop amplifier, inverting or noninverting, using only resistive components, the gain will always roll off at a rate of 20 dB/decade, regardless of the value of its closed-loop gain. The internally compensated op-amps are sometimes simply called compensated op-amps and generally have very small open-loop bandwidths.

Three compensating components, a resistor and two capacitors, are required for 709C. The nature of the frequency response curve depends on the values of the compensating components used. The roll-off rate with various compensating components that are specified along the gain versus frequency curves is about 20 dB/ decade. Note that the open-loop bandwidth of a 709C decreases from the outermost compensated curve to the innermost. That is, if C1 = 10 pF, R1 = 0 ohm, and C2 = 3 pF, the bandwidth is approximately 5 kHz, while if C1 = 5000 pF, R1 = 1.5 kW, and C2 = 200 pF, the bandwidth is 100 Hz. The frequency compensation circuit for mA 709 is shown in Fig. 20.13(b). The uncompensated op-amps offer relatively broader openloop bandwidths.

100,000

Voltage gian

In externally compensated op-amps, the external compensating components are added at designated terminals in noncompensated op-amps. For proper operation, the manufacturer recommends appropriate compensating components for the uncompensated op-amps. The op-amp 709C is a noncompensated (externally compensated) op-amp. The open-loop frequency response curves of these op-amps, as well as the connection diagram of the 709C for the external compensating components, are shown in Fig. 20.13.

10,000 1,000 100

Vs = ±15 V C1 = 10 pF, R1 = 0 W, TA = 25° C C2 = 3 pF C C 1 =1 C 2 = 3 00 p 1 = F, R C 50 pF C 1 = 0 2 1.5 C 1 = 5 = 20 pF, 2 = 00 pF R kW 1 = 20 0 , p 1.5 0 pF F, R kW 1 = , 1. 5 kW ,

10 1 100 Hz 1 kHz

10 kHz 100 kHz 1 MHz 10 MHz Frequency (a) C2

2

+ mA709

3

–

8

5 6

1 R1

C1

(b)

R3 = 50 W, for capacitive loading

The operational amplifier, or op-amp, was originally developed in response to the requirements of analog computer designers. An op-amp is a high gain, direct coupled amplifier. The voltage gain can be controlled by the externally connected feedback components. The op-amp can be used in amplifier and signal processing applications involving d.c. to several MHz of frequency ranges. The operational amplifier circuits can be designed with various types of active devices. However, IC technology is remarkably successful in offering low-cost, high-performance, versatile and economic op-amps in a monolithic form, and the op-amp became a widely accepted building block of modern signal processing and conditioning circuits. Since the IC op-amps are inexpensive, versatile and easy to use, they are used for negative feedback amplifier applications, and they also find applications in waveshaping, filtering and solving mathematical operations. Some common applications are discussed below.

Figure 20.14 shows the basic inverting amplifier configuration using an op-amp with input impedance Z1 and feedback impedance Zf . If the impedances Z1 and Zf are equal in magnitude and phase, then the closed-loop voltage gain is –1, and the input signal will undergo a 180° phase shift at the output. Hence, such a circuit is also called phase inverter. If two such amplifiers are connected in cascade, then the output from the second stage is the same as the input signal without any change of sign. Hence, the outputs from the two stages are equal in magnitude but opposite in phase and such a system is an excellent paraphase amplifier.

Vi

Ii

ZI

Zf

Ii

– Vo

+

Referring to Fig. 20.14, if the ratio Zf = Z1 = k, a real constant, then the closed-loop gain is – k, and the input voltage is multiplied by a factor – k and the scaled output is available at the output. Usually, in such applications, Zf and Z1 are selected as precision resistors for obtaining precise and scaled value of input voltage.

If R1 = • and Rf = 0 in the noninverting amplifier configuration discussed in Chapter 3, then the amplifier acts as an unity-gain amplifier or voltage follower as shown in Fig. 20.15. That is, Rf Rf Av = 1 + ___ or ___ = Av – 1 R1 R1 Rf Since ___ = 0 we have Av = 1. R1

– + + Vi

–

Vo

The circuit consists of an op-amp and a wire connecting the output to the input, i.e. the output voltage is equal to the input voltage, both in magnitude and phase. In other words, Vo = Vi. Since the output voltage of this circuit follows the input voltage, the circuit is called voltage follower. It offers very high input impedance of the order of MW and very low output impedance. Therefore, this circuit draws negligible current from the source. Thus, the voltage follower can be used as a buffer between a high impedance source and a low impedance load for impedance matching applications.

The adder, also called summing amplifier, is shown in Fig. 20.16. The output of this arrangement is the linear addition of a number of input signals. Since a virtual ground exists at the inverting input of op-amp at the node a, Vn V1 V2 I = ___ + ___ + º + ___ R1 R2 Rn

and

[

Rf Rf Rf Vo = – Rf I = – V1 ___ + V2 ___ + º + Vn ___ R1 R2 Rn

]

(20.20)

R1 = R2 = … = Rn = R, then

If

Rf Vo = – ___ (V1 + V2 + … + Vn) R I

V1

R1

(20.21)

Rf

I a

– Vo

V2 R2

Vn

+

Rn

Therefore, the output is proportional to the sum of the individual inputs. In other words, the output signal is the sum of all the inputs multiplied by their associated gains. It can then be expressed as Vo = V1AV 1 + V2AV 2 + V3AV 3 + … + Vn AVn where AV1, AV2 … AVn are the individual gains of the inputs. The summing amplifier may have equal gain for each of the inputs, and then it is referred to as an equal-weighted configuration. The advantage of this method of summation of signals is that a very large number of inputs can be added together, thus requiring only one additional resistor for each additional input with individual gain controls.

Theoretically, individual gain controls may be produced by making the input resistors variable, or by making the feedback resistor Rf variable with the use of potentiometer. However, for a.c. signals, the summation is not so straight forward, since a.c. signals of different frequency and phase relationships do not add correctly. Then, an rms calculation can be made for finding the effective value. A level-shifter circuit can be realized by use of a two-input summing circuit, in which, one input can be the a.c. signal, and the second input can be the d.c. value by whose value the a.c. signal is to be shifted. The d.c. value acts as the offset for the a.c. signal.

The summing amplifier shown in Fig. 20.16 has the following inputs, Rf = R1 = R2 = R3 = R = 1 k , V1 = + 2V, V2 = + 3V, V2 = + 4V and the supply voltages are ± 15 V. Determine the output voltage. Assume that the op-amp is initially nulled.

Solution

The output voltage is given by Rf 1 × 103 Vo = – ___ (V1 + V2 + … + Vn) = – _______3 (2 + 3 + 4) = – 9 V R 1 × 10

The basic op-amp can be used as a subtractor as shown in Fig. 20.17. To analyze the operation of the circuit, assume that all resistors are equal in value of R, i.e., R1 = R2 = R3 = Rf = R. The output voltage can be determined by using the super-position principle. If V1 = 0, i.e. V1 is grounded, then the output voltage Vo1 will be due to the input voltage V2 alone. Hence the circuit shown in Fig. 20.17 becomes a noninverting amplifier of unity gain with input voltage V2/2 at the noninverting input terminal and the output voltage is given by Vo2 = [V2 /2](1 + R/R) = V2 Rf

V1

R1

a b

V2

– Vo = V2 – V1 +

R2 R3

Similarly, if V2 = 0, then the output voltage Vo1 will be due to V1 alone. Hence, the circuit becomes an inverting amplifier of unity gain and the output voltage is given by Vo1 = – V1

Now, considering that both the inputs are applied, the output voltage Vo is Vo = Vo2 + Vo1 = V2 – V1

(20.22)

Thus, the output voltage is proportional to the difference between the two input voltages. Hence, it acts as a difference amplifier with unity gain.

Find the output voltage of the following op-amp circuit shown in Fig. 20.18(a)

Solution

10 kW

Let us use the principle of superposition.

To find output due to V1

–

Let V2 = 0 and only V1 being applied as shown in Fig. 20.18(b). This is the inverting amplifier. V2 Rf Therefore, Vo1 = – ___ × V1 R1 10 × 103 = ________ × V1 = – 2V1 5 × 103

To find output due to V2

Vo2

Vo + 5 kW

1 kW

(1) R1

Let V1 = 0 and only V2 being applied as shown in Fig. 20.18(c). This is the noninverting amplifier. Therefore,

Rf

5 kW

V1

( ( (

10 kW –

Vo1

) )

Rf = 1 + ___ × VA R1

+ 5 kW

Rf 2 × 103 = 1 + ___ × _______________ × V2 R1 5 × 103 + 2 × 103 3

Rf

V1

2 kW

V2 = 0

)

10 × 10 2 Vo2 = 1 + ________ × __ × V2 7 5 × 103 Hence

Vo2

6 = __ V2 7

R1

Rf

5 kW

10 kW –

To find Vo 6 Vo = Vo1 + Vo2 = –2V1 + __ V2 7

The circuit shown in Fig. 20.19(a) can perform both addition and subtraction simultaneously on the input signals.

VA

V2

Vo 2 +

5 kW 2 kW

R R V1 R

Va

V2

–

Vb

V3

Vo = (V3 + V4) – (V1 + V2)

+

R V4 R R

(a) R

Va

Va

–

Vb

+

–

R Vb R

R

V1/2

R

V1

R

R/2

Vo = – V1

Vo

+

R

R/3 (b) R R Va

R V3

R

Vb

R

– +

V0

R

(c)

The output voltage Vo can be determined with the help of superposition theorem. The output voltage Vo1 due to the input voltage V1 alone can be found by making all other input voltages equal to zero. The equivalent circuit is shown in Fig. 20.19(b). Thus the circuit becomes an inverting amplifier for the input V1 alone and its output voltage is R V1 Vo1 = – ____ ___ = –V1 R/2 2

Similarly, the output voltage Vo2 due to V2 alone is Vo2 = – V2 The output voltage Vo3 due to the input voltage V3 alone can be determined by making other input voltages V1, V2 and V4 equal to zero. The equivalent circuit is shown in Fig. 20.19(c). Here the circuit becomes a noninverting amplifier and the voltage at the noninverting terminal or node b is V3 R/2 Vb = ________ V3 = ___ . 3 R + R/2 Therefore, the output voltage Vo3 due to input V3 alone is given by

( )

V3 R Vo3 = 1 + ____ Vb = 3 ___ = V3 3 R/2

(

)

Similarly, for the input voltage V4, the output voltage Vo4 is Vo4 = V4 Therefore, the output voltage for all four input voltages applied at the inputs simultaneously is Vo = Vo1 + Vo2 + Vo3 + Vo4 = – V1 – V2 + V3 + V4 Vo = (V3 + V4) – (V1 + V2)

(20.23)

Hence, the circuit using op-amp shown in Fig. 20.19(a) is an adder-subtractor.

Instrumentation amplifiers are used in monitoring and controlling of the physical quantities in the industrial processes for measurement and control of temperature, humidity, and light intensity. Normally, a transducer which converts one form of energy into another is used to sense and deliver the required information in the form of an electrical quantity such as voltage, current or resistance. The signal is sent to the preamplifier stage for initial amplification and, after further amplification and processing, may be passed to the output stages such as meters, oscilloscopes, charts, memories and magnetic recorders. The major function of an instrumentation amplifier is precise amplification of low level output signal of the transducer, and the instrumentation amplifier is widely used in applications where low noise, low thermal and time drifts, high input impedance and accurate closed-loop gains are required. There are many commercially available instrumentation amplifier ICs, such as AD521, AD524, and AD624 manufactured by Analog Devices, and mA725, ICL7605, and LH0036. The requirements for instrumentation amplifiers are more rigid than that of general purpose amplifiers. The important features required for an instrumentation amplifier are (i) High gain accuracy (ii) High CMRR (iii) High gain stability with low temperature coefficient (iv) Low d.c. offset and (v) Low output impedance

Consider a basic difference amplifier shown in Fig. 20.20. The output voltage Vo is given by

(

R2 R2 1 Vo = – ___ V2 + ________ V1 1 + ___ R1 R1 R3 1 + ___ R4

( )

)

Therefore,

[

(

)

R2 R1 1 Vo = – ___ V2 – ________ 1 + ___ V1 R1 R2 R3 1 + ___ R4

( )

]

R1 R3 R2 If ___ = ___, then Vo = ___ (V1 – V2) i.e., the output voltage Vo is the difference of the two input voltages R2 R4 R1 with the gain of R2/R1. The differential amplifier discussed above has its input impedance value limited by the value of resistor R1. The gain of the differential amplifier is decided by the factor R2/R1, which restricts the high gain values. This limitation is overcome by the use of a voltage follower between each signal input terminal and the difference amplifier. This has the disadvantage that the gain of the amplifier cannot easily be changed. Hence, a circuit with the possibility of gain adjustment by the use of a single resistor is preferable for instrumentation applications involving very low voltages of the order of microvolts and common-mode signals existing between the two input terminals. The instrumentation amplifier shown in Fig. 20.21 has this feasibility of offering high input impedance and a high gain. V2

R2 R1 V2

– R3 +

V1 R4

+

R2

A1

0V –

R1

V2

R¢

R V1

R¢

V1

A2 –

V1¢

A3 + R1 R2

+ 0V

–

V2¢

V0

Vo

The op-amps A1 and A2 as shown in Fig. 20.21 are voltage follower or buffer circuits acting as the input stage for each of the inputs V1 and V2. They have zero differential input voltage, i.e.,Vid = 0. Under such conditions with common mode signal = 0, and V1 = V2, the voltage across the resistor R is zero. The voltages at the inverting terminals of the buffers are equal to the input voltages. Since no current flows through the resistors R and R¢, the output voltages are V ¢2 = V2 and V 1¢ = V1 respectively. However, if V1 π V2, then a current flows through the resistors R and R¢, and (V ¢2 – V 1¢ ) > (V2 – V1). Therefore, this circuit will have more differential gain and CMRR compared to the single op-amp circuit shown in Fig. 20.20. (V1 – V2) The current flowing in the resistor R is I = ________ and the same current I will flow through the resisR R2V¢1 tors R¢ in the direction shown. The voltage at the noninverting terminal of op-amp A3 is _______. R1 + R2 By using superposition theorem, we get

(

Simplifying, we get

R2 R2 Vo = – ___ V2¢ + 1 + ___ R1 R1

)(

R2V1¢ _______ R1 + R2

)

R2 Vo = ___ (V 1¢ – V ¢2 ) R1

(20.24)

(V1 – V2) Since there is no current entering the op-amp, the current I = ________, which flows through the R resistor R¢.

and

R¢ V1¢ = R¢I + V1 = ___ (V1 – V2) + V1 R R¢ V ¢2 = –R¢I + V2 = – ___ (V1 – V2) + V2 R

Substituting the values of V ¢1 and V ¢2 in Eq. (20.24), Vo is given by R2 2R¢ Vo = ___ ____ (V1 – V2) + (V1 – V2) R1 R

[

That is,

]

R2 2R¢ Vo = ___ 1 + ____ (V1 – V2) R1 R

(

)

By using a variable resistor R, the gain of this instrumentation amplifier can be varied. Figure 20.22 shows a differential instrumentation amplifier using Transducer Bridge. In a resistive transducer, the resistance of the transducer changes as a function of the physical quantity under measurement, which is connected as one arm of the bridge, with a small circle shown around it in the Fig. 20.22. Due to a change in temperature, the effective resistance of the transducer changes and it is indicated by (RT ± DR), where RT is the resistance of the transducer and DR is the change in resistance RT. The operation of the instrumentation amplifier using the transducer is explained as follows. The bridge is initially balanced with the use of a d.c. supply voltage Vd.c., so that V1 =V2.

Resistive transducer RT ± DR RA + –

V2

Vdc RB

RC

V12

3-op-amp instrumentation amplifier of Fig. 20.20

Indicator or display device

V1

That is,

RC (Vd.c.) RB (Vd.c.) ________ ________ = RB + RA RC + RT

Therefore,

RA ___ RT ___ = RB RC

or

RA RT = ___ RC RB

( )

If the ratio of RA to RB, which is called the ratio arms of the bridge is assumed a constant k, then the value of the transducer resistance RT = kRC. As the physical quantity changes, the resistance value RT of the transducer changes, and this causes an imbalance in the bridge. That is, the output of the bridge V1 π V2. The three op-amp instrumentation amplifier shown in Fig. 20.21 amplifies this differential voltage. Let DR be the change in resistance of the transducer. As the resistor RB and RC are fixed resistors, the voltage V1 is constant. However, the voltage V2 varies as a function of the change in transducer resistance. Therefore,

RC (Vd.c.) V2 = ______________ RC + (RT + DR) RB (Vd.c.) V1 = ________ RC + RB

Consequently, the voltage V12 across the output terminal of the bridge is V12 = V2 – V1. Therefore, RC (Vd.c.) RB (Vd.c.) V12 = _____________ – ________ RC + RT + DR RC + RB

If RA = RB = RC = RT = R, then the above equation becomes DR (Vd.c.) V12 = ___________ 2 (2 R + DR) The gain of the basic differential amplifier is –R2/R1. Therefore, the output voltage Vo is DR (Vd.c.) R2 R2 Vo = V12 – ___ = ___________ ___ R1 2 (2 R + DR) R1

( )

Since the change in resistance of a transducer is normally very small, (2R + DR) @ 2R. Hence the output voltage Vo becomes R2 DR (Vdc) Vo = ___ ________ R1 4R

( )

Therefore, the output voltage is a function of the change in resistance of the transducer element, multiplied by the gain value of the op-amp A3 and it is also determined by the resistor R.

A circuit in which the output voltage waveform is the time integral of the input voltage waveform is called integrator or integrating amplifier. Integrator produces a summing action over a required time interval and the circuit is based on the general parallel-inverting voltage feedback model. In order to achieve integration, the basic inverting amplifier configuration shown Fig. 20.23 can be used with the feedback element Zf replaced by a capacitor Cf as shown in Fig. 20.23. The expression for the output voltage vn(t) can be obtained by writing Kirchhoff’s current equation at node a as given by i1 = IB + if Since IB is negligibly small, i1 = if

dvo(t) The current through the capacitor ic(t) = C _____ dt vi(t) – va(t) d __________ Therefore, = Cf __ [va(t) – vo(t)] R1 dt However, vb(t) = va(t) = 0 because the gain of the op-amp Av is very large. Therefore, vi(t) d ____ = Cf __ (– vo(t)) R1 dt Integrating both sides with respect to time, we get the output voltage as defined by t vi(t) t d ____ (– vo(t)) dt = –Cfvo(t) + vo (0) Ú R = Ú Cf __ dt 1 0 0

1 vo(t ) = – _____ R1Cf

Therefore,

t

Ú 0

vi(t)dt + vo(0)

(20.25)

where vo(0) is the initial output voltage. Equation (20.25) indicates that the output voltage is directly proportional to the negative integral of the input voltage and inversely proportional to the time constant R1Cf . In frequency domain, the above equation becomes 1 Vo(s) = – _____ Vi (s) sR1Cf Letting s = jw in steady state, we get

(20.26)

1 Vo( jw) = – _______ Vi (jw) jwR1Cf

(20.27)

Hence, the magnitude of the transfer function of the integrator is

|

| |

Vo( jw) j 1 |A| = ______ = ________ = ______ wR1Cf Vi( jw) w (R1Cf)

|

(20.28)

At w = 0, the gain of the integrator is infinite. Also the capacitor acts as an open circuit and hence there is no negative feedback. Thus, the op-amp operates in open loop and hence the gain becomes infinite (or the op-amp saturates). In practice, the output will never become infinite. As the frequency increases, the gain of the integrator decreases. The input sinusoidal and square waveforms and the corresponding output waveforms of integrator circuit using op-amp are shown in Figs. 20.24(a) and (b). Vi

0

Vi

p

2p

3p

t

t

Vo

Vo

0

0

p

2p

(a)

3p

t

0

t

(b)

The differentiator can perform the mathematical operation of differentiation, i.e. the output voltage is the differentiation of the input voltage. This operation is very useful to find the rate at which a signal varies with time.

The ideal differentiator may be constructed from a basic inverting amplifier, if the input resistor R1 is replaced by a capacitor C1. The ideal differentiator circuit is shown in Fig. 20.25. The expression for the output voltage can be obtained from Kirchoff’s Current Law written at node a as follows: iC = IB + if Since

IB = 0, iC = if va – vo d C1 __ (vi – va) = ______ Rf dt

But

vo = vb = 0 V, because A is very large. dvi vo C1 ___ = ___ Rf dt

Therefore,

dvi vo = – RfC1 ___ (20.29) dt Thus the output vo is equal to the RfC1 times the negative instantaneous rate of change of the input voltage vi with time. A differentiator performs the reverse of the integrator’s function. This upper cutoff frequency is given by 1 fo = _______ 2pRfC1 The input sinusoidal and square waveforms and the corresponding output waveforms of differentiator circuit using op-amp are shown in Figs. 20.26(a) and (b). or

vi

0

vi

p

2p

3p

t

vo

0

0

t

vo

p

2p

3p

t

t

The process of integration involves the accumulation of signal over time, and hence sudden changes in the signal are suppressed. Therefore, an effective smoothing of the signal is achieved, and hence, integration can be viewed as low-pass filtering. The process of differentiation involves the identification of sudden changes in the input signal. Constant and slowly changing signals are suppressed by a differentiator. Therefore, the differentiator can be viewed as a form of high-pass filtering.

The signal processing applications with very low voltage, current and power levels require rectifier circuits. The ordinary diodes cannot rectify voltages below the cut-in voltage of the diode. A circuit which can act as an ideal diode or precision signal-processing rectifier circuit for rectifying voltages which are below the level of cut-in voltage of the diode can be designed by placing the diode in the feedback loop of an op-amp. Figure 20.27(a) shows the arrangement of a precision diode. It is a single diode arrangement and functions as a non-inverting precision half-wave rectifier circuit. If Vi in the circuit of Fig. 20.27(a) is positive, the op-amp output VoA also becomes positive. Then the closed loop condition is achieved for the op-amp, and the output voltage Vo = Vi. When Vi < 0, the voltage VoA becomes negative, and the diode is reverse biased. The loop is then broken and the output Vo = 0. Vi 100 mV

Vo D

t –100 mV

– RL +

VoA

Vi

V0 100 mV 70 mV

(a)

D–ON

D–OFF (b)

t

Consider the open loop gain AOL of the op-amp is approximately 104 and the cut-in voltage Vg for Vg silicon diode is ª 0.7 V. When the input voltage Vi > ____, the output of the op-amp VoA exceeds Vg AOL Vg and the diode D conducts. Then the circuit acts like a voltage follower for input voltage level Vi > ____ AOL 0.7 (i.e., when Vi > ___4 = 70 mV), and the output voltage Vo follows the input voltage during the positive 10 half cycle for input voltages higher than 70 mV as shown in Fig. 20.27(b). When Vi is negative or less

Vg than ____, the output of op-amp VoA becomes negative, and the diode becomes reverse biased. The loop AOL is then broken, and the op-amp swings down to negative saturation. However, the output terminal is now isolated from both the input signal and the output of the op-amp, and thus Vo = 0. No current is then delivered to the load RL except for the small bias current of the op-amp and the reverse saturation current of the diode. This circuit is an example of a non-linear circuit, in which linear operation is achieved over the region (Vi > 0) and non-linear operation is achieved over the remaining region (Vi < 0). Since the output swings to negative saturation level when Vi < 0, the circuit is basically of saturating form. Thus the frequency response is also limited. The precision diodes are used in Half-wave rectifier, Full-wave rectifier, Peak value detector, Clipper and Clamper circuits. It can be observed that the precision diode shown in Fig. 20.27 (a) operates in the first quadrant with Vi > 0 and Vo > 0. The operation in third quadrant can be achieved by connecting the diode in reverse direction. A non-saturating half-wave precision rectifier circuit is shown in Fig. 20.28 (a). When Vi > 0 V, the voltage at the inverting input becomes positive, forcing the output VoA to go negative. This results in forward biasing the diode D1 and the op-amp output drops only by ª 0.7 V below the inverting input voltage. Diode D2 becomes reversebiased. The output voltage Vo is zero since no current flows in the feedback circuit through Rf. Hence, the output Vo is zero when the input is positive. When Vi < 0, the op-amp output VoA becomes positive, forward biasing the diode D2 and reverse biasing the diode D1. The circuit then acts like an inverting amplifier circuit with a non-linear diode in the forward path. The gain of the circuit is unity when Rf = Ri.

Vi

and

Rf Vo = – ___ Vi for Vi < 0 Ri

The voltage VoA at the op-amp output is VoA @ – 0.7 V for Vi > 0 V and

Rf VoA @ ___ Vi + 0.7 V for Vi < 0 V. Ri

Rf D1

– +

Vo D2

VoA

R (a) Vi Vm

t –Vm V0

The circuit operation can mathematically be expressed as Vo = 0 when Vi > 0

Ri

0V

D1 – ON D2 – OFF D1 – OFF D2 – ON

t (b)

The input and output waveforms are shown in Fig. 20.28 (b). The op-amp shown in the circuit must be a high-speed op-amp. This accommodates the abrupt changes in the value of VoA when Vi changes sign and it improves the frequency response characteristics of the circuit. The advantages of precision half-wave rectifier are (i) it can rectify signals of very low amplitude and (ii) it is a non-saturating one. The inverting characteristics of the output Vo can be circumvented by the use of an additional inversion for achieving a positive output.

A filter is a frequency selective circuit that allows only a certain band of the desired frequency components of an input signal to pass through and attenuates the signals of undesired frequency components. The filters are of two types namely (i) analog filters and (ii) digital filters. The analog filters are further classified as passive filters and active filters. The passive filters utilize only resistors, inductors and capacitors. An active network is a circuit obtained by interconnecting passive elements (resistors and capacitors) and active elements (transistors, tunnel diodes and operational amplifiers). An active filter uses an op-amp in order to minimize the effect of loading on the frequency characteristics of the filter. The filters are widely used in communication, signal processing and sophisticated electronic instruments. The applications of filters also include the suppression of power-line hum, rejection of very low or high-frequency interference and noise, bandwidth limiting and specialized spectral shaping. A filter can be realized in any one of the following four basic response types: (i) Low-pass filter (LPF) (ii) High-pass filter (HPF) (iii) Bandpass filter (BPF) (iv) Band-reject filter (BRF), Bandstop or Band elimination filter (BEF). A low-pass filter allows only low frequency signals upto a certain break point fH to pass through, while suppressing high frequency components as shown in Fig. 20.29(a). The range of frequency from 0 to higher cut-off frequency fH is called passband and the range of frequencies beyond fH is called stopband. A high-pass filter allows only frequencies above a certain break point to pass through and attenuates the low frequency components as shown in Fig. 20.29(b). The range of frequencies beyond its lower cut-off frequency fL is called passband and the range of frequencies from 0 to fL is called stopband. The bandpass filter is the combination of high and low-pass filters, and this allows a specified range of frequencies to pass through. The ideal and practical characteristics of the bandpass filter are shown in Fig. 20.29(c). It has two stopbands in the range of frequencies between 0 to fL and beyond fH. The band between fL and fH is called passband. Hence its bandwidth is ( fH – fL ). The band-reject filter is the logical inverse of bandpass filter, which does not allow a specified range of frequencies to pass through. The ideal and practical characteristics of the band-reject filter are shown in Fig. 20.29(d). It has two passbands in the range of frequencies between 0 to fL and beyond fH. The band between fL and fH is called stopband.

Figure 20.30 is an active low pass filter with single RC network connected to the non-inverting terminal of op-amp. The input resistor Ri and feedback resistor Rf are

Rf

Ri

– R

Vi

V1

+

V0

C

(a) Rf

Ri

– R

R

Vi

V1

+

V0

C

(b)

used to determine the gain of the filter in the pass band. At low frequencies the capacitor appears open,

(

)

Rf and the circuit acts like a non-inverting amplifier with a voltage gain of 1 + ___ . As the frequency Ri increases, the capacitive reactance decreases, causing the voltage gain to drop off. Referring to Fig. 20.30(a), the voltage V1 across the capacitor is Vi V1 = ___________ 1 + j2pf RC The output voltage V0 for non-inverting amplifier is Rf V0 = 1 + ___ V1 Ri

(

)

By substituting V1 in the above equation, then the output voltage V0 becomes

(

)

Rf Vi V0 = 1 + ___ ___________ Ri 1 + j2p f RC

V0 _________ A ___ = Vi f 1 + j __ fH

or

( )

( )

Rf V0 where ___ is the gain of the low pass filter which is a function of frequency, A = 1 + ___ is the passband Vi Ri 1 gain of the filter, f is the frequency of the input signal and fH = ______ is the high cut-off frequency of 2pRC the filter. The frequency response of the filter can be determined by using the magnitude of the gain of the low- pass filter, which is expresses as

| |

V0 A ___ ________ = __________ Vi f 2 1 + __ fH

÷ ( )

At very low frequencies i.e., f < fH, the gain is @ A. When the frequency reaches the cut-off frequency i.e., f = fH, the gain falls to 0.707 times the maximum gain A. The frequency range from 0 to fH is called the pass band. At high frequencies i.e., f > fH , the gain decreases at a constant rate of –20 dB/decade. The frequency range beyond fH is called stop band. The frequency response of the active low pass filter (non-ideal) is shown in Fig. 20.31. Voltage gain

–20 dB/decade

A

0.707 A

Pass band

Stop band f

fH

The following steps are used for the design of active low-pass filter. 1. Choose the value of high cut-off frequency fH. 2. Select the value of capacitor C such that is value is £ 1 mF. 1 3. When the values fH and C are known, the value R can be calculated by using, fH = ______. 2pRC 4. Finally select the value of Ri and Rf depending on the desired pass-band gain by using,

( )

Rf A = 1 + ___ Ri

The active high pass filter with single RC network connected to non-inverting terminal op-amp is shown in Fig. 20.32. The input resistor Ri and feedback resistor Rf are used to determine the gain of the filter in the pass band. At low frequencies the capacitor appears open, and the voltage gain approaches zero. At high frequencies the capacitor appears shorted, and the circuit becomes a

( )

Rf non-inverting amplifier with a voltage gain of 1 + ___ . Ri

Ri

C Vi

Rf

– V1

+

V0

R

The output voltage V0 of the first order active high-pass filter is

(

)

Rf j2pf RC V0 = 1 + ___ ___________ Vi Ri 1 + j2pf RC Therefore, the gain of the filter becomes

( ) ( ) ( )

f j __ fL V0 ___ = A _________ Vi f 1 + j __ fL

( )

Rf where passband gain of the filter is A = 1 + ___ , f is the frequency of the input signal and the lower Ri 1 cutoff frequency of the filter is fL = ______. 2pRC The frequency response of the filter is obtained from the magnitude of the filter, i.e.,

| |

V0 ___ =A Vi

( ) ( ) ÷ ()

f __ f L _________ ________

f 1 + __ fL

2

At very low frequencies i.e., f < fL, the gain is @ A. At the frequency f = fL, the gain falls to 0.707 times the maximum gain A. The range of frequency above fL is called the pass band. For the frequency f < fL, the gain decreases at a constant rate of –20 dB/decade. The frequency range below the cutoff frequency is called stop band. The frequency response of the first order active high-pass filter is shown in Fig. 20.33. Note: The high-pass second order filter is obtained from the low-pass second order filter by applying the transformation. wo s ___ ___ = s High-pass wo Low-pass

|

|

Voltage gain

–20 dB/decade A

0.707A

Stop band

Pass band fL

f

Hence, the resistors R and capacitors C are interchanged in a low-pass active filer to get a high-pass active filter.

Design a high-pass filter with cut-off frequency 1 kHz and a pass-band gain of 2.

Solution 1. Given: fL = 1 kHz 2. Since R and C values are not given, let us assume C = 0.01 mF 1 1 3. Therefore, R = ______ = _________________ = 15.9 kW. 2pfLC 2p (10)3 (0.01) 10– 6

( )

Rf 4. Given pass-band gain A = 1 + ___ = 2 i.e. the value of Ri Rf = Ri. Let Rf = Ri = 10 kW. The high-pass circuit values are shown in Fig. 20.34. A band-pass filter can be constructed simply by cascading a low-pass filter whose cut-off frequency is fH and a high-pass filter whose cut-off frequency is fL, provided fH > fL. A band-reject filter is obtained by parallel connecting a high-pass filter whose cutoff frequency is fL and a low-pass filter whose cut-off frequency is fH provided fH < fL.

A comparator compares a voltage signal applied to one input of the op-amp with a known voltage, called the reference voltage applied at the other input. In its simplest form, the comparator consists of an op-amp operated in open-loop, which is fed with two analog inputs, and it produces one of the two saturation voltages, namely, positive or negative at the output of the op-amp. The transfer characteristics of an ideal comparator and a practical comparator using op-amp are shown in Fig. 20.35(a) and 20.35(b) respectively. It can be seen from Fig. 20.35(b) that the output

state of a practical comparator can change with an input increment of only 2 mV. This width of 2 mV is the region of uncertainty of a practical comparator. Two types of comparators (i) Non-inverting comparator and (ii) Inverting comparator can be constructed using op-amps. v0

V0

+Vsat

10

0

(v1 – Vref)

0

1

2

(V1 – Vref) mV

– 10

–Vsat (a)

(b)

Figure 20.36(a) shows an op-amp configured for use as a non-inverting comparator. A fixed reference voltage Vref is applied to (–) input and a time-varying signal Vi is applied to the (+) input. When the non-inverting input Vi is less than the reference voltage Vref , the output voltage Vo is at – Vsat @ – VEE. On the other hand, when Vi is greater than Vref , the output voltage Vo is at + Vsat @ +VCC. Thus, the output Vo changes from one saturation level to another depending on the voltage difference between Vi and Vref . Figures 20.36(b) and (c) show the input and output waveforms of the comparator when Vref is positive, and negative respectively. The diodes D1 and D2 are connected to protect the op-amp from excessive input voltages of Vi as shown in the Fig. 20.36(a). In practical circuits, Vref can be obtained by the use of a 10 kW potentiometer forming a voltage divider with the use of supply voltages V + and V –, and the wiper connected to (–) input terminal of op-amp as shown in Fig. 20.36(d). Output voltage level other than ±Vsat at the output can be obtained by using a resistor R and backto-back Zener diodes connected at the output of op-amp as shown in Fig. 20.36(e). Then, the limiting values of voltage Vo becomes (VZ1 + VD) and – (VZ 2 + VD), where VD ª 0.7 V, and VZ1 and VZ 2 are the Zener voltages. Figure 20.37(a) shows a practical inverting comparator with the reference voltage Vref applied to (+) input and the voltage signal Vi applied to the (–) input. For a sinusoidal input signal Vi and for positive and negative Vref , the input and output waveforms are as shown in Fig. 20.37 (b) and (c) respectively.

Multivibrators are regenerative circuits, which are mainly used in timing applications. Based on their operational characteristics, they can be classified into three categories, namely, (i) Astable multivibrator (ii) Monostable multivibrator (iii) Bistable multivibrator

+VCC –

D1

vo

D2 +

R

RL

R Vref

+

–VEE

+

Vi

– –

(a)

Vi

Vi vP

vP + Vref = 1 V 0V

t

0V – Vref = –1

– vp

t

–vp

vo Vi > Vref

Vi > Vref + Vsat

+ Vsat

0V

t

0V

t

t

– Vsat

– Vsat

Vin < Vref

Vin < Vref

(b)

(c)

V

V

+

+ –

vi V

R +

vi 2

+

vi 1

–

vo

V

+

R vz 2

–

V

Vref V

vz1

–

–

10 k (d)

(e)

The astable multivibrator toggles between one state and the other without the influence of any other external control signal. It is also called a free-running multivibrator. The monostable multivibrator or one-shot requires an external signal called a trigger to force the circuit into a quasi-stable state for a particular time duration or delay. A suitable timing network determines the time delay, and it returns to the stable state at the end of the delay time. An astable multivibrator is a square-wave generator. Figure 20.37(a) shows the circuit of an astable multivibrator with the output of op-amp fedback to the (+) R2 input terminal. The resistors R1 and R2 form a voltage divider network, and a fraction b = _______ of R1 + R2 +VCC

– RP 10 kW

Vref

D1

D2

vo + RL 10 kW

R

–VEE

+ Vi – (a) vi

vi

VP + Vref 0V

VP t

0V –Vref

t

–VP

– VP

Vo

vo +Vsat

+Vsat 0V

t

0V

t

–Vsat

–Vsat vin > Vref

vin > –Vref

(b)

(c)

the output is fed back to the input. The output can take values of + bVsat or – bVsat. The voltage ± bVsat acts as Vref at the (+) input terminal. The output is connected also to the (–) input terminal through an integrating low-pass RC network. When the voltage Vc across capacitor C just exceeds Vref , switching takes place resulting in a square-wave output. To understand the operation of the circuit, let us consider that initially the output is at +Vsat as shown in Fig. 20.38(b). The capacitor C with its voltage shown as Vc starts charging through resistor R towards +Vsat. The voltage at (+) input terminal is held at + bVsat as indicated by the use of R1 – R2 potential divider network. The charging of C continues until the voltage Vc at the (–) input terminal is just greater than the voltage at the (+) input terminal, + bVsat. When this happens as shown at point b of Fig. 20.38(b), the output is switched down to –Vsat. The voltage + bVo across the capacitor now starts discharging through resistance R and charging towards – Vsat. The capacitor voltage Vc now increases more and more negative, and at point c just exceeds –bVsat. The output now switches back to +Vsat, and the cycle repeats. Summarizing, (i) when Vo = +Vsat, C charges from –bVsat to + bVsat and switches Vo to –Vsat and (ii) when Vo = –Vsat, C charges from +bVsat to – bVsat and switches Vo to +Vsat. The frequency of the free running multivibrator is determined by the charging and discharging time of the capacitor between the voltage levels – bVsat and + bVsat, and vice versa. The voltage across the capacitor as a function of time can be represented as –t ____

vc(t) = Vfin + (Vini + Vfin) e RC

where Vfin is the final value of the voltage and Vini is the initial voltage. Considering the charging of the capacitor from point a towards +Vsat, –t ____

vc(t) = +Vsat + (– bVsat – Vsat) e RC –t ____

= Vsat – Vsat(1 + b) e RC

(20.30)

At t = T1, the voltage across the capacitor reaches + bVsat and switches at point b. Therefore, capacitor voltage vc at time T1 is

(

– T1 ____

bVsat = Vsat 1 – (1 + b) e RC That is, and

)

– T1 ____

(1 – b ) = (1 + b)e RC

R1 + 2R2 1+b T1 = RC ln _____ = RC ln ________ R1 1–b

As shown in Fig. 20.35(b), the total time period is given by 1+b T = 2T1 = 2RC ln _____ 1–b

(20.31)

That is,

(

R1 + 2R2 T = 2RC ln ________ R1

)

(20.32)

and the output is a symmetrical waveform. 1 1 Hence, the frequency of oscillation is fo = __ = ______________ T 1+b 2 RC In _____ 1+b

( )

R 1 Considering R1 = R2, we have b = ____ = 0.5, T = 2RC ln 3 and fo = _________. 2R 2 RC ln 3

(20.33)

(20.34)

Equation (20.31) shows that the period is directly proportional to the time constant, RC. Thus, varying either R or C changes the period correspondingly. Therefore, providing a tunable resistance R paves the way for a continuously tunable square-wave generator. The output peak amplitudes can be varied by the use of Zener diodes connected back to back as shown in Fig. 20.38(c). The output voltage is then regulated to ± (Vz + VD) where Vz is the Zener voltage. Then the peak-topeak output voltage is given by vo(peak-to-peak) = 2(VZ + VD). To generate an asymmetric square wave, a variable voltage source V can be introduced as shown in Fig. 20.38(d).

For the circuit shown in Fig. 20.38(a), assuming that R1 = 116 k , R2 = 100 k and ±Vsat = ±14 V, find

(i) the time constant to produce 1 kHz output (ii) the resistance R and (iii) the maximum value of differential input voltage. Solution

R1 + 2 R2 (a) From Eq. (20.32), the time period, T = 2RC ln _________ R1 T = 2RC ln (116 × 103 + 2 × 100 × 103/116 × 103) = 2RC ln(316 × 103/116 × 103) = 2RC (since ln(316 × 103/116 × 103) ª 1) Given That is,

1 f = 1 kHz, T = __ = 1 ms f 2RC = 1 × 10 – 3 sec

Therefore, the time constant RC = 0.5 × 10 – 3 sec (b) With C = 0.01 mF,

0.5 × 10 –3 R = __________ = 50 kW 0.01 × 10 – 6

(c) Maximum value of differential input voltage is

(

)

R2 100 2Vsat _______ = 2 × 14 × _________ = 12.96 V. R 1 + R2 100 + 116 Therefore, the peak values for the differential input voltage just exceed ±2 × 6.48 V. The circuit diagram of a monostable multivibrator, also called a one-shot multivibrator is shown in Fig. 20.39(a). This has a stable state and a quasi-stable state. Single output pulse of adjustable time duration in response to a triggering signal can be generated using the monostable multivibrator. The time duration for the output pulse is achieved by connecting required external components to the op-amp. When the output Vo is at positive saturation, the diode D1 clamps the capacitor (C ) voltage to VD (0.7 V). This is the stable state of the circuit. In this state, the inverting terminal b is clamped to ground R D1 C –

b

Vo

A +

R2

VT D2 a

CT

R1

R3

(a)

vi

t

TP

To + Vsat

(b)

VD

VD

vc

T

t

– Vsat (c)

Vsat

To – Vsat

vo – Vsat

t

T (d)

by diode D1. This results in preventing the inverting input terminal going more positive than VD (0.7 V). This makes terminal a also positive by the same voltage VD. A negative-going narrow trigger pulse is passed through the R3Cr differentiator and diode D2, and connected to the noninverting input terminal of op-amp. R3 is made much larger than R1, so that its loading effect may be minimized. The diode D2 prevents positive spikes arriving from the triggering circuit. Let us assume that in the stable state, the output Vo of op-amp is at +Vsat, the voltage at inverting terminal is VD and the voltage at (+) terminal through the potential divider R1 – R2 is +bVsat, where R1 b = _______ . When a negative trigger signal VT is applied to the (+) terminal through the trigger line, R1 + R2 the effective signal is less than 0.7V. That is, voltage at (+) terminal is [bVsat + (– VT)] < 0.7 V. Then, the op-amp output switches from +Vsat to –Vsat. The diode D1 is now reverse-biased and the capacitor C starts charging exponentially to –Vsat through the resistance R in the closed loop. In this condition, the voltage at positive input terminal is – bVsat. While charging exponentially, just as the capacitor voltage vc becomes slightly more than – bVsat, the voltage at (–) terminal becomes more negative than that at (+) terminal. Then the op-amp output switches back to +Vsat. The capacitor C now starts charging towards +Vsat through the resistance R. This continues only until the voltage at (–) terminal becomes VD (0.7 V), and then it clamps the capacitor C to VD. The waveforms of the negative polarity triggering signal, voltage across the capacitor and output of op-amp are shown in Fig. 20.39(b), (c) and (d) respectively. For a low-pass RC circuit, the general solution is vo = Vfm + (Vini – vfin)e – t/RC where Vini is the initial voltage value and Vfm is the final voltage value. For the circuit explained above, Vfm = – Vsat and Vini = VD (diode forward voltage) The output vC is then given by, vC = – Vsat + (VD + Vsat)e – t/RC

(20.35)

At the end of time t = T as shown in Fig. 20.39(c) vC = – bVsat. Thus, – bVsat = – Vsat + (VD + Vsat)e – T/RC Simplifying for the pulse width, we get

(

)

1 + VD/Vsat R2 T = RC ln __________ where b = _______ R 1–b 1 + R2

(20.36)

When Vsat >> VD (0.7 V) and R1 = R2 with b = 0.5, T = 0.693RC.

(20.37)

Understandably, the trigger pulse width should be less than the pulse width T. The monostable multivibrator circuit can generate a fast transition after a calculated time T equal to the pulse width in response to the application of the input trigger pulse as explained above. Therefore, it can be used as a time-delay circuit. The rectangular waveform can be used as a gating signal in counters and analog-to-digital converters.

A transducer is a device which converts the energy from one form to another form. This energy may be electrical, mechanical, chemical, optical or thermal. Transducers may be classified according to their application, method of energy conversion, nature of the output signal, and so on. All these classifications usually result in overlapping areas. A sharp distinction among the types of transducers is difficult. The transducer that gives electrical energy as output is known as electrical transducer. The output electrical signal may be voltage, current, or frequency and production of these signals is based upon resistive, capacitive, inductive effects etc. For measuring non-electrical quantities, a detector is used which usually converts the physical quantity into a displacement, that activates the electrical transducer. The displacement transducers, such as capacitive, oscillation, potentiometric, photoelectric (phototube) and piezoelectric, use the principle of converting a mechanical force into displacement and then into electrical parameters. Here, the mechanical elements used for converting this applied force into displacement are called force-summing devices. The transducers may also be classified as (i) Active and (ii) Passive transducers. Active transducers, also known as self generating type, develop their own voltage or current as the output signal. The energy required for production of this output signal is obtained from the physical phenomenon being measured. Passive transducers, also known as externally powered transducers, derive the power required for energy conversion from an external power source. However, they may also absorb some energy from the physical phenomenon under study. A few examples of active and passive transducers are given in Table 21.1.

Active transducers

Passive transducers

Thermocouple

Resistance

Piezoelectric transducer

Potentiometric device

Photovoltaic (Photojunction) cell

Resistance strain gauge

Moving coil generator

Resistance thermometer

Photoelectric (Photoemission) cell

Thermistor Photoconductive cell Inductance Linear Variable Differential Transformer (LVDT) Capacitance Voltage and current Devices using Hall effect Photoemissive cell Photomultiplier tube

The opto-electronic transducer such as photoconductive cell, photovoltaic cell, solar cell, phototube and photomultiplier tube use the principle of converting light energy into electrical energy. Some of the basic requirements of a transducer are given below. The input-output characteristics of the transducer should be linear. The transducer should withstand overloads, with measures for overload protection. The transducer should produce identical output signals when the same input signal is applied at different times under the same environmental conditions. The output from the transducer should not be affected by temperature, vibration and other environmental variations and there should be minimum error in measurements. In industrial, aerospace and biological applications, the input to the transducer will not be static but dynamic in nature, i.e. the input will vary with time. The transducer should respond to the changes in input as quickly as possible. The transducer should produce a sufficiently high analog output signal with high signal to noise ratio, so that the output can be measured either directly or after suitable amplification. The transducer, under working conditions, will be subjected to various mechanical strains. Such external forces should not introduce any deformity and affect the performance of the transducer.

Of the many effects that are used in transducers, the principal effects used are variation of resistance, inductance, capacitance, piezoelectric effect and thermal effects which are described in the following sections.

The capacitance of a parallel-plate capacitor is given by A C = o r __ d where A = area of each plate in m2 d = distance between parallel plates in m o

= dielectric constant (permittivity) of free space in F/m

r

= relative dielectric constant (permittivity)

The capacitance is directly proportional to the area of the plate (A) and inversely proportional to the distance between the parallel plates (d ). Obviously, any variation in A or d causes a corresponding variation in the capacitance. This principle of variation in d is used in the capacitive transducer, shown in Fig. 21.1. Deflected diaphragm Diaphragm static position

Static plate

Insulting material Rear cavity termination, etc.

Pressure

Dielectric

When a force is applied to a diaphragm which acts as one plate of a capacitor, the distance between the diaphragm and the static plate is changed. The resulting change in capacitance can be measured with an a.c. bridge or an oscillator circuit in which the change in frequency can be measured by an electronic counter and it is a measure of the magnitude of the applied force. In capacitor microphone, the same principle is used in which sound pressure varies the capacitance between the fixed plate and a movable diaphragm.

The capacitive transducer can measure static and dynamic changes. The drawback of this transducer is its sensitivity to temperature variations.

When a force is applied to the ferromagnetic armature, the air gap, as shown in Fig. 21.2, is changed thereby varying the reluctance of the magnetic circuit. Thus the applied force is measured by the change of inductance in a single coil. Displacement Armature

Air gap Coil winding

Ferromagnetic core

Output

The inductive transducer enables static and dynamic measurements. Its drawback is that it has limited frequency response.

The most widely used inductance transducer is the Linear Variable Differential Transformer (LVDT) and is shown in Fig. 21.3(a). It consists of a primary coil and two exactly similar secondary coils with a rod shaped magnetic core positioned centrally inside the coil. An alternating current is fed into the primary and voltages Vo1 and Vo2 are induced in the secondary coils. As these coils are connected in series opposition, the output voltage Vo = Vo1 – Vo2. If the core is placed ideally in the central position (null position or reference position), Vo1 = Vo2 and hence the output voltage Vo = 0. In practice due to incomplete balance, a residual voltage usually remains with the core in this position. As shown in Fig. 21.3, when the core is displaced from the null position, the induced voltage in the secondary towards which the core has moved increases while that in the other secondary decreases. This results in a differential voltage output from the transformer. The output voltage produced by the displacement of the core is linear over a considerable range as shown in Fig. 21.3(b) but flattens out at both ends, and the voltage phase changes by 180° as the core moves through the center position. LVDT provides continuous resolution and shows low hysteresis and hence, repeatability is excellent under all conditions. As there are no sliding contacts, there is less friction and less noise.

Secondary-1 + Vo1

Primary +

–

Core

Output voltage Vo

Vi

Linear range –

– +

Vo2

Secondary-2

Residual voltage +

–

B

0

(a)

A

(b)

It is sensitive to vibrations and temperature. The receiving instrument must be selected to operate on a.c. signals or a demodulator network must be used if a d.c. output is required.

Figure 21.4 shows the basic circuit of an oscillation transducer. The force-summing device is used to change the distance between the parallel plates of the capacitor thereby changing the value of capacitance (similarly, the inductance value can also be changed) in the stable LC oscillator. The change in oscillator frequency caused by the externally applied force can be measured by an electronic counter. This transducer measures both the static and dynamic phenomena and is used in telemetry systems. Its limited range, poor thermal stability and low accuracy restrict its use to low accuracy applications.

C

L

Oscillator port

Output

Force summing member

Pressure port

The basic circuit of a potentiometric transducer is shown in Fig. 21.5. A potentiometric transducer consists of a resistance element that is contacted by a movable slider. A force-summing member is used to move the slider thereby changing the resistance and correspondingly, the output voltage changes. The same principle can be used to vary the resistance in a bridge circuit. This transducer has high electric efficiency and provides a sufficient output to permit control operations without further amplification.

Pressure port Force summing member

Source Output

Potentiometer

If a metal conductor is stretched or compressed, its resistance changes because of dimensional changes (length and cross sectional area) and resistivity change. If a wire is under tension and increases its Dl length from l to l + Dl, i.e. the strain S = __, then its resistance increases from R to R + DR. l The sensitivity of a strain gauge is described in terms of a characteristic called the gauge factor G, defined as the unit change in resistance per unit change in length, i.e. DR/R DR/R G = _____ = _____ S Dl/l

The schematic diagram of a typical displacement transducer wherein the measuring forces are transmitted to the platform containing the unbonded wire structure by means of a force rod is shown in Fig. 21.6. The resistance wires have equal lengths. When an external force is applied to the strain gauge, the armature moves in the direction indicated. Elements A and D increase in length, whereas elements B and C decrease in length. The change in resistance of the four wires is proportional to their change in length and this change can be measured with a Wheatstone bridge as shown in Fig. 21.6(c). Thus, the external force causes variation in resistance of the wires, unbalancing the bridge and causing an output voltage Vo proportional to the pressure. The bridge is balanced if RA ___ RB ___ = RC RD

A bonded wire strain gauge consists of a grid of fine resistance wire of diameter of about 25 mm. The wire is cemented to a base. The base may be a thin sheet of paper or a very thin Bakelite sheet. The wire

Force Resistance wire

Force rod Welded joints

Fixed frame

B

A

Mounting rings

Moving armature Direction of movement

D

C Body

Sapphire pins

Stretched unbonded strain gauge wire

Cross spring (a)

(b)

RA

RB Vo

Vs RC

Output voltage

RD

(c)

is covered with a thin sheet of material so that it is not damaged mechanically. The base is bonded to the structure under study with an adhesive material. It acts as a bonding material. It permits a good transfer of strain from base to wires. The commonly used types of bonded strain gauges are shown in Fig. 21.7. Carrier (Base) Wire grid

Terminals

Wire grid Base (a) Linear strain gauge

Terminals (b) Rossette

Base Terminals

Wire Wire grid

(c) Torque gauge

(d) Helical gauge

Base

The resistance of most electrical conductors varies with temperature according to the relation R = R0(1 + T + T 2 + ...) where R0 = resistance at temperature T0 (at 0 °C), R = resistance at T, and ,

= constants.

Over a small temperature range, depending on the material, the above equation reduces to R = R0 (1 +

is the temperature coefficient of resistance.

Important properties of materials used for resistance thermometers are (i) high temperature coefficient of resistance, (ii) stable properties so that the resistance characteristic does not drift with repeated heating and cooling or mechanical strain, and (iii) a high resistivity to permit the construction of small sensors. The variation of resistivity with temperature of some of the materials used for resistance thermometers is shown in Fig. 21.8. From the figure, it can be seen that tungsten has a suitable temperature coefficient of resistance but is brittle and difficult to form. Copper has a low resistivity and is generally confined to applications where the sensor size is not restricted. Both platinum and nickel are widely used because they are relatively easy to obtain in pure state. Platinum has an advantage over nickel in that its temperature coefficient of resistance is linear over a larger temperature range. The resistance–temperature relationship for platinum resistance elements is determined from the Callendar equations

Nickel

Tungsten

5

Resistivity relative to 0°C value

where

T)

Copper 4 Platinum 3

2

1 0

2

4

6

Temperature (°C)

8 × 10

2

100 (RT – R0) T T T = ____________ + d ____ – 1 ____ R100 – R0 100 100

(

)

where RT is the resistance at temperature T, R0 is the resistance at 0°C, R100 is the resistance at 100°C and d is the Callendar constant (approximately 1.5). The construction of industrial platinum resistance thermometer is shown in Fig. 21.9.

Thermistor or Thermal resistor is a two-terminal semiconductor device whose resistance is temperature sensitive. The value of such resistors decreases with increase in temperature. Materials employed in the manufacture of the thermistors include oxides of cobalt, nickel, copper, iron, uranium and manganese. Connecting leads The thermistor has very high temperature coefficient of resistance, of the order of 3 to 5% per °C, making it an ideal temperature transducer. The temperature coefficient of resistance is normally negative. The resistance at any temperature T, is given approximately by 1 1 RT = Ro exp b __ – ___ T To where RT = thermistor resistance at temperature T (K),

(

)

Ro = thermistor resistance at temperature To (K), and b = a constant determined by calibration. At high temperatures, this equation reduces to b RT = Ro exp __ T The resistance–temperature characteristic is shown in Fig. 21.10. The curve is non-linear and the drop in resistance from 5000 W to 10 W occurs for an increase in temperature from 20°C to 100°C. The temperature of the device can be changed internally or externally. An increase in current through the device will raise its temperature carrying a drop in its terminal resistance. Any externally applied heat source will result in an increase in its body temperature and drop in resistance. This type of action (internal or external) lends itself well to control mechanisms.

()

Mounting thread

Lead supports

Sheath

Element

Three useful parameters for characterizing the thermistor are the time constant, dissipation constant, and resistance ratio. The time constant is the time for a thermistor to change its resistance by 63% of its initial value, for zero-power dissipation. Typical values of time constant range from 1 s to 50 s. The dissipation factor is the power necessary to increase the temperature of a thermistor by 1°C. Typical values of dissipation factor range from 1 mW/°C to 10 mW/°C. Resistance ratio is the ratio of the resistance at 25°C to that at 125°C. Its range is approximately 3–60. Thermistors are used to measure temperature, flow, pressure, liquid level, voltage or power level, vacuum, composition of gases and thermal conductivity and also in compensation network.

T (a) Symbol

R

8

10 10

6

4

10

2

10

0

10

–2

10

–4

10

–100

0

100

200

300

400

T

Temperature (°C) (b) Characteristics

A thermocouple is a junction between two dissimilar metals or semiconductors that generates a small voltage, typically in the milli volt range, with coefficient of about 50 V/°C. Various thermocouple materials and methods of construction are used depending on the temperature, environment and sensitivity. A Iron typical thermocouple circuit for temperature Reference measurement is shown in Fig. 21.11. It consists junction Constantan of two junctions, reference and sensing maintained at different temperatures. Each junction is made by welding two dissimilar metals together. The reference junction is Iron + maintained at a fixed temperature, usually Sensing Millivolt 0°C and the output voltage depends upon the junction meter temperature of the sensing junction. As only a – Constantan relatively small output of the order of 50 V/°C is obtained, it is necessary to amplify the output for calibration and measurement. The iron-constantan thermocouple is used for measuring temperatures up to 760°C and Chromel–Alumel thermocouple is used for temperature measurement up to 1370°C.

When a transverse magnetic field B is applied to a specimen (thin strip of metal or semiconductor) carrying current I, an electric field E is induced in the direction perpendicular to both I and B. This phenomenon is known as the Hall effect. A Hall effect measurement experimentally confirms the validity of the concept that it is possible for two independent types of charge carriers, electrons and holes, to exist in a semiconductor. The schematic arrangement of the semiconductor, the magnetic field and the current flow pertaining to the Hall effect are shown in Fig. 21.12. Under the equilibrium condition, the electric field intensity, E, due to the Hall effect must exert a force on the carrier of charge, q, which just balances the magnetic force, i.e. qE = Bqvd where vd is the drift velocity. Also, the electric field intensity due to Hall effect is VH E = ___ d where d is the distance between surfaces 1 and 2, and VH is the Hall voltage appearing between surfaces 1 and 2. In an N-type semiconductor, the current is carried by electrons and these electrons will be forced downward towards side 1 which becomes negatively charged with respect to side 2. y 2

d

l w x

B 1

z

The current density (J ) is related to charge density ( r) by J = rvd Further, the current density (J ) is related to current (I ) by I I J = _____ = ___ Area wd where w is the width of the specimen in the direction of magnetic field (B). Combining the above relations, we get BJd ___ BI VH = Ed = B vd d = ____ r = rw

The Hall coefficient, RH, is defined by 1 RH = __ r RH so that VH = ___ w BI. A measurement of the Hall coefficient RH determines not only the sign of the charge carriers but also their concentration. The Hall coefficient for a P-type semiconductor is positive, whereas it is a negative for an N-type semiconductor. This is true because the Hall voltage in a P-type semiconductor is of opposite polarity to that in an N-type semiconductor. The advantage of Hall effect transducers is that they are non-contact devices with high resolution and small size. The Hall effect is used to find whether a semiconductor is N-or P-type and to determine the carrier concentration. If terminal 2 becomes charged positively with respect to terminal 1, the semiconductor must be N-type and r = nq, where n is the electron concentration. On the other hand, if the polarity of VH is positive at terminal 1 with respect to terminal 2, the semiconductor must be P-type and r = pq, where p is the hole concentration. The mobility ( m) can also be calculated with simultaneous measurement of the conductivity (s). The conductivity and the mobility are related by the equation s = rm or m = s RH. Therefore, the conductivity for N-type semiconductor is s = nqmn and for P-type semiconductor, s = pqmp, where mn is the electron mobility and mp is the hole mobility. Thus, if the conductivity of a semiconductor is also measured along with RH, then mobility can be determined from the following relations. s For N-type semiconductor, mn = ___ nq = sRH s and for P-type semiconductor, mp = ___ pq = sRH Since VH is proportional to B for a given current I, Hall effect can be used to measure the a.c. power and the strength of magnetic field and sense the angular position of static magnetic fields in a magnetic field meter. It is also used in an instrument called Hall effect multiplier which gives the output proportional to the product of two input signals. If I is made proportional to one of the inputs and B is made BI proportional to the second signal, then from the equation, VH = ___ rw , VH will be proportional to the product of two inputs. Hall devices for such applications are made from a thin wafer or film of indium antimonide (InSb) or indium arsenide. As the material has a very high electron mobility, it has high Hall coefficient and high sensitivity. An electrical current can be controlled by a magnetic field because the magnetic field changes the resistances of some elements with which it comes in contact. In the magnetic bubble memory, while read-out, the Hall effect element is passed over the bubble. Hence, a change in current of the circuit will create, say, a one. If there is no bubble, there will be a zero and there will be no current change in the output circuit. The read-in device would have an opposite effect, wherein the Hall device creates a magnetic field when supplied with a pulse of current. This, in turn, creates a little domain and then a magnetic bubble is created.

Some of the other applications are in measurement of velocity, rpm, sorting, limit sensing and noncontact current measurements.

An N-type semiconductor has a Hall coefficient of 200 cm3/C and its conductivity is 10 S/m. Find its electron mobility.

Solution

Given RH = 200 cm3/C and s = 10 S/m

Therefore, the electron mobility, mn = sRH = 10 × 200 = 2000 cm2/V-s

The conductivity of an N-type semiconductor is 10 S/m and its electron mobility is 50 × 10 – 4 m2/V-s. Determine the electron concentration.

Given s = 10 s/m and mn = 50 × 10 – 4 m2/V-s s We know that the electron mobility, mn = ___ nq Solution

Therefore, the electron concentration, s ____________________ 10 n = ___ mq = 50 × 10 – 4 × 1.6 × 10 – 19 = 12.5 × 1021 m– 3

A current of 20 A is passed through a thin metal strip, which is subjected to a magnetic flux density of 1.2 Wb/m2. The magnetic field is directed perpendicular to the current. The thickness of the strip in the direction of the magnetic field is 0.5 mm. The Hall voltage is 60 V. Find the electron density.

Solution Given: I = 20 A, B = 1.2 Wb/m2, VH = 60 V and w = 0.5 mm We know that the number of conduction electrons, i.e. electron density, 1.2 × 20 BI n = ______ = _________________________ = 5 × 1021 m3 VH qw 60 × 1.6 × 10 – 19 × 0.5 × 10 – 3

If the dimensions of asymmetrical crystalline materials, such as quartz, rochelle salt and barium titanite, are changed by the application of a mechanical force, the crystal produces an emf. This property is used in piezoelectric transducers.

The basic circuit of a piezoelectric transducer is shown in Fig. 21.13. Here, a crystal is placed between a solid base and the force-summing member. An externally applied force gives pressure to the top of the crystal. Hence, it produces an emf across the crystal which is proportional to the magnitude of the applied pressure. As this transducer has a very good high frequency response, it is used in high frequency accelerometers. As it needs no external power source, it is called as self-generating transducer. The main drawbacks are that it cannot measure static conditions and the output voltage is affected by temperature variations of the crystal.

Pressure port

Force-summing member

Output

Base

Crystal

This is an optoelectronic or optical transducer shown in Fig. 21.14. It uses a phototube and a light source separated by a small window whose aperture is controlled by the force-summing device. The quantity of incident light on the photosensitive cathode is varied according to the externally applied force thereby changing the anode current. Pressure port

Force-summing member

Light modulation Phototube

+ Output

– Window Light source

This device measures both static and dynamic phenomena and it has high efficiency. It does not respond to high frequency light variation. Note: The other optoelectronic transducers such as photoconductive cell, photovoltaic cell, solar cell, photomultiplier have been explained in Chapter 22.

Light can be emitted from a solid when it is stimulated by the source of incident energy. This phenomenon is called luminescence. If the incident energy is in the form of photons, then it is called photo-luminescence. If the radiation is produced by the application of an electric field, it is termed electro-luminescence. In cathode-luminescence, a beam of electrons bombard the solid and produce radiation of light. In all types of luminescence, the radiation of a characteristic wavelength, l, is emitted as a consequence of electronic transition between two energy levels E2 and E1 (where E2 > E1), which is related by hc E2 – E1 = hf = ___ l where c = velocity of light = 3 × 108 m/s, f = frequency and h = Planck’s constant = 6.626 × 10 – 34 J-s. As E2 and E1 are usually the components of allowed bands of energy, the emitted radiation occurs over a spectrum of wavelengths. The devices that resulted from the emission of electrons from a metallic surface with vacuum and gas phototubes and were commonly called photoelectric devices. However, modern solid state devices, which include emitters, sensors, and couplers are called optoelectronic devices or electro-optics. The optoelectronic devices are the products of a technology that combines optics with electronics. The optoelectronic devices utilise energy in the visible and infrared regions. Figure 22.1 shows the classification of optoelectronic devices. Optoelectronic sensors are of two categories, viz. (i) photoconductive devices and (ii) photovoltaic devices. The photovoltaic devices generate a voltage, while the photoconductive devices require an external source. The photoconductive devices are subdivided into bulk type photoresistors and junction type photoconductors. Photodiodes and phototransistors which utilise the reverse biased depletion junctions are the branches of function type photoconductors. The characteristics of optoelectronic devices depend on light that occupies a small portion of the electromagnetic spectrum shown in Fig. 22.2. This gives a graphical representation of the different radiations that exist at different frequencies and wavelengths. The wavelength (l) and frequency ( f ) of electromagnetic waves are related to the velocity of light (c) by the expression

Optoelectronic devices

Emitters

LED sensor

LASER LED IR

Photomultiplier tube

Isolators or couplers

Sensors

Photoemmisive

Photodetectors

Photoelectric tube

Photoconductive

Fiber optics

Photovoltaic

Si

Junction type photoconductor

Photoresistors (Bulk-type)

PbS

Photodiodes Avalanche photodiode PIN diode Photo duo diode Si PN photodiode

Se

CdS CdSe

Phototransistors Laser FET Bipolar Darlington

c =lf 8

where c = 3 × 10 m/s, f is in Hz and l is in metres.

The human eye is somewhat like a filter with a response similar to that of a tuned circuit. In Fig. 22.3, the solid curve shows the response of an average human eye—photopic vision for normal light levels—to the visible part of the spectrum extending from 380 to 760 nm. It is seen that the peak sensitivity occurs at 555 nm and tapers off to zero at 380 and 760 nm. Different colours corresponding to different wavelengths have also been shown. The human eye is more sensitive to green-yellow and less sensitive to violet (shorter wavelength) and red (longer wavelength). The broken

–7

24

10

10

COSMIC RAYS –5

22

10

10

GAMMA RAYS 20

–3

10

10 X-RAYS

18

–1

16

Frequency-Hertz (Hz)

10

10 ULTRA VIOLET VISIBLE

14

1

10

3

10

10 INFRARED

5

12

10

10

10

10

MICROWAVES

8

7

10

Wavelength-Nanometer

10

9

10

10 RADIO

6

11

10

4

10

10 AUDIO

2

13

10

15

10

10 POWER

1

17

10

curve in the Fig. 22.3 with a peak at 507 nm is termed the scotopic eye response for low light levels. The existence of the two responses arises out of the fact that the eye’s spectral response shifts at very low light levels. The lens system of the eye focuses the optical image of the object being observed on the retina. Retina contains light sensitive cellular structures of rods and cones. The rods sense the brightness levels and the cones are mainly responsible for colour perception. It is estimated that there are some 6,500,000 cones and about 100,000,000 rods connected to the brain through about 800,000 optic nerve fibers. Horizontal resolution is the ability to resolve horizontal details, i.e. change in brightness levels. Such changes represent vertical edges in the illumination level with frequency determined by the rate of brightness levels. But the human eye follow the abrupt changes in brightness level up to 5 MHz. But for colour images, the eye can sense the different colours up to 1.5 MHz. Above 1.5 MHz, eye receive only the illumination changes in the object; colours received as black, white and gray.

When radiation is incident on a semiconductor, some absorption of light by the material takes place, and its conductivity increases. This effect is called photoconductive effect which is described as follows.

In a semiconductor material, the forbidden energy gap (EG) is expressed by hc EG = E2 – E1 = hf = ___ l Energy content of a photon is E = hf, where h is the Planck’s constant (6.626 × 10 – 34 J-s) and f is the frequency of the incident light. If frequency f is very low so that E < EG, where EG is the forbidden band energy between valence band and conduction band, the energy is inadequate to transfer an electron from valence band to conduction band and hence light passes through the material with very little absorption. However, if E ≥ EG, electrons in the valence band absorb the incident photons and get shifted to the conduction band. Also, the conductivity of a semiconductor material is proportional to the concentration of charge carriers as given by s = (nmn + pmp) where n = magnitude of free electron concentration p = magnitude of hole concentration s = conductivity mn = mobility of electrons

p

= mobility of holes

Thus electron-hole pairs generated by the incident light in addition to those created thermally increases the conductivity (decreases the resistance) of the material resulting in increase in the current in the external circuit. Hence, such a material is called photoconductor or photoresistor. Therefore, for photoconduction to take place in an intrinsic semiconductor, the photon must possess energy atleast equal to the forbidden energy gap EG. Thus the minimum frequency fc to cause photoconduction is given by EG fc = ___ h

Conduction band

E2

EG

Acceptor level

EA E1

Electron

The long wavelength limit, cut-off wavelength, or the critical wavelength of the material, c, is obtained by substituting the values of c and h resulting in c

For silicon, EG = 1.1 eV and room temperature.

Donor level

ED

c

Valence band

Hole

Photon

1.24 = _______ m EG (eV)

= 1.13 m, whereas for germanium, EG = 0.72 eV and

c

= 1.73 m at

The photoconductive cell (PC ) or photodetector is a two terminal device which is used as a Light Dependent Resistor (LDR). It is made of a thin layer of semiconductor material such as cadmium sulphide (CdS), lead sulphide (PbS), or cadmium selenide (CdSe) whose spectral responses are shown in Fig. 22.5. The photoconducting device with the widest applications is the CdS cell, because it has high dissipation capability, with excellent sensitivity in the visible spectrum and low resistance when stimulated by light. The main drawback of CdS cell is its slower speed of response. PbS has the fastest speed of response. The illumination characteristics of photoconductive detectors are shown in Fig. 22.6(a). It exhibits the peculiar property that its resistance decreases in the presence of light and increases in the absence of light. The cell simply acts as a conductor whose resistance changes when illuminated. In absolute darkness, the resistance is as high as 2 M and in strong light, the resistance is less than 10 . A simple circuit for a photoconductive detector is shown in Fig. 22.6(b). The semiconductor layer is enclosed in a sealed housing. A glass window in the housing permits light to fall on the active material of the cell. Here, the resistance of the photoconductive detector, in series with R, limits the amount of current I in the circuit. The ammeter A is used to measure the current I. When no light falls on the cell,

Light

Resistance (k )

100

+

10

V

I

–

PC

1

R

0.1 1 10 100 2 Illumination lm/m (a)

1000

–

A

+

(b)

its resistance is very high and the current I is low. Hence the voltage drop Vo across R is relatively low. When the cell is illuminated, its resistance becomes very low. Hence, current I increases and voltage Vo increases. Thus, this simple circuit arrangement with slight modification can be used in control circuits to control the current. The detector is used either as an ON/OFF device to detect the presence or absence of a light source which is used for automatic street lighting or some intermediate resistance value can be

used as a trigger level to control relays and motors. Further, it is used to measure a fixed amount of illumination and to record a modulating light intensity. It is used in counting systems where the objects on a conveyor belt interrupt a light beam to produce a series of pulses which operates a counter. It is used in twilight switching circuits. When the day light has faded to a given level, the corresponding resistance of the detector causes another circuit to switch ON the required lights. It is widely used in cameras to control shutter opening during the flash. Twin photoconductive cells mounted in the same package have been used in optical bridge circuits for position control mechanisms and dual-channel remote volume control circuits.

Silicon photodiode is a light sensitive device, also called photodetector, which converts light signals into electrical signals. The construction and symbol of a photodiode are shown in Fig. 22.7. The diode is made of a semiconductor PN junction kept in a sealed plastic or glass casing. The cover is so designed that the light rays are allowed to fall on one surface across the junction. The remaining sides of the casing are painted to restrict the penetration of light rays. A lens permits light to fall on the junction. When light falls on the reverse biased PN photodiode junction, hole-electron pairs are created. The movement of these hole-electron pairs in a properly connected circuit results in current flow. The magnitude of the photocurrent depends on the number of charge carriers generated and hence, on the illumination of the diode element. This current is also affected by the frequency of the light falling on the junction of the photodiode. The magnitude of the current under large reverse bias is given by I = IS + Io (1 – eV/ where Io IS V VT

VT

)

= reverse saturation current = short-circuit current which is proportional to the light intensity = voltage across the diode = volt equivalent of temperature = parameter, 1 for Ge and 2 for Si.

The characteristics of a photodiode are shown in Fig. 22.8. The reverse current increases in direct proportion to the level of illumination. Even when no light is applied, there is a minimum reverse leakage current called dark current, flowing through the device. Germanium has a higher dark current than silicon, but it also has a higher level of reverse current.

Photodiodes are used as light detectors, demodulators and encoders. They are also used in optical communication system, high speed counting and switching circuits. Further, they are used in computer card punching and tapes, light operated switches, sound track films and electronic control circuits. Phototransistor or Photodiode is a much more sensitive semiconductor photodevice than the PN photodiode. The current produced by a photodiode is very low which cannot be directly used in control applications. Therefore, this current should be amplified before applying to control circuits. The phototransistor is a light detector which combines a photodiode and a transistor amplifier. When the phototransistor is illuminated, it permits a larger flow of current. Figure 22.9 shows the circuit of an NPN phototransistor. It is usually connected in a CE configuration with the base open. A lens focuses the light on the base-collector junction. Although the phototransistor has three sections, only two leads, the emitter and collector leads, are generally used. In this device, base current is supplied by the current created by the light falling on the base-collector photodiode junction. When there is no radiant excitation, the minority carriers are generated thermally, and the electrons crossing from the base to the collector and the holes crossing from the collector to the base constitute the reverse saturation collector current ICO. With IB = 0, the collector current is given by IC = (b + 1) ICO When the light is turned ON, additional minority carriers are photogenerated and the total collector current is IC = (b + 1)(ICO + IL) where IL is the reverse saturation current due to the light. Current in a phototransistor is dependent mainly on the intensity of light entering the lens and is less affected by the voltage applied to the external circuit. Figure 22.10 shows a graph of collector current IC as a function of collector-emitter voltage VCE and as a function of illumination H. The phototransistors find extensive applications in high-speed reading of computer punched cards and tapes, light detection systems, light operated switches, reading of film sound track, production line counting of objects which interrupt a light beam, etc.

If the PN junction is open circuited, the light energy is used to create a potential difference which is proportional to the frequency and intensity of the incident light. This phenomenon is called photovoltaic effect.

Photovoltaic cell, a light-sensitive semiconductor device, produces a voltage when illuminated which may be used directly to supply small amounts of electric power. In the photovoltaic device without any applied voltage, the junction generates a voltage depending upon the illumination and the load. The voltage generated is due to the accumulation of carriers produced by photon excitation. The photovoltaic potential is the voltage at which zero resultant current is obtained under open circuited conditions. The photovoltaic emf is 0.5 V for either silicon or selenium cell and 0.1 V for germanium cell the short circuit cell current is of the order of 1 mA. The magnitude of the current under large reverse bias is given by I = IS + Io (1 – eV/

VT

)

The photovoltaic voltage Vmax which corresponds to an open circuited diode can be obtained by substituting I = 0 in the above equation. Hence, IS Vmax = VT ln 1 + __ Io

(

As IS >> Io, Vmax increases logarithmically with short circuit current, IS, and hence with illumination. The voltage increases as the intensity of light falling on the semiconductor junction of this cell increases. A photovoltaic cell consists of a piece of semiconductor material such as silicon, germanium or selenium which is bonded to a metal plate, as shown in Fig. 22.11(a). The circuit symbol for photovoltaic cell is shown in Fig. 22.11(b).

)

Metal

Semiconductor

Light +

+

RL –

–

(a) (b)

The spectral response of silicon, germanium and selenium are shown in Fig. 22.12, indicating that photoconductor is a frequency-selective device. As the spectral response of silicon and germanium extends well into infrared region, its efficiency is quite high. Selenium cell has two advantages over silicon, viz. (i) its spectral response is almost similar to that of the human eye, and (ii) it has the ability to withstand damaging radiation environments, lasting up to 10,000 times longer than silicon. The characteristic curves of output voltage versus light intensity and output current versus light intensity are shown in Figs 22.13(a) and (b), respectively. Photovoltaic cells are used in low-power devices such as light meters. Nowadays, with an improvement in the efficiency of these cells, more power is produced, as in solar cells which are photovoltaic

devices. When operated in the short-circuit mode, the current is proportional to the illumination and photovoltaic cell is used to construct a direct-reading foot-candle meter.

When sunlight is incident on a photovoltaic cell, it is converted into electric energy. Such an energy converter is called Solar cell or Solar battery and is used in satellites to provide the electrical power. This cell consists of a single semiconductor crystal which has been doped with both P- and N-type impurities, thereby forming a PN junction. The basic construction of a PN junction solar cell is shown in Fig. 22.14. Sunlight incident on the glass plate G passes through it and reaches the junction. An incident light photon at the junction may collide with a valence electron and impart sufficient energy to make a transition to the conduction band. As a result, an electron-hole pair is formed. The newly formed electrons are minority carriers in the P-region. They move freely across the junction. Similarly,

holes formed in the N-region cross the junction in the opposite direction. The flow of these electrons and holes across the junction is in a direction opposite to the conventional forward current in a PN junction. Further, it leads to the accumulation of a majority carriers on both sides of the junction. This gives rise to a photovoltaic voltage across the junction in the open circuit condition. This voltage is a logarithmic function of illumination.

Incident sunlight

Glass plate G Outer ring contact +

P-type junction Va

N-type

–

In bright sunlight, about 0.6 V is developed by a single solar cell. The Metallic amount of power the cell can deliver contcat depends on the extent of its active surface. An average cell will produce about 30 mW per square inch of surface, operating in a load of 4 W. To increase the power output, large banks of cells are used in series and parallel combinations. The efficiency of the solar cell is measured by the ratio of electric energy output to the light energy input expressed as a percentage. At present, an efficiency in the range of 10 to 40% is obtained. Silicon and selenium are the materials used widely in solar cells because of their excellent temperature characteristics.

The phototube is a radiant energy device that controls its electron emission when exposed to incident light. Figure 22.15 shows the circuit diagram of a phototube. The anode and the photosensitive cathode are placed in a high vacuum glass envelope. When sufficient voltage is applied between the photocathode and the anode, Cathode Light mA tthe collector current is directly proportional to the amount of – incident light. +

Typical voltage–current characteristics of a high vacuum phototube are shown in Fig. 22.16(a) and the variation of anode current with illumination is shown in Fig. 22.16(b). The current through the tube is extremely small, usually in the range of a few microamperes. Hence, the phototube is connected to an amplifier to provide an useful output.

V

The current handled in a vacuum phototube may be increased if a small amount of gas is introduced resulting in characteristics as shown in Fig. 22.17(a). At voltages above the saturation level of 10 V, the electrons may acquire sufficient energy in passing between cathode and anode to ionise some of

the gas atoms which adds more charges to the current. Further increase in voltage provides even more ionisation, and the total current increases. The process must be limited to prevent secondary emission or bombardment of the cathode by the positive ions since bombardment will destroy the emitting surface. The safe limit is normally set at about 90 V. The resulting increase in current due to the presence of gas may be of the order of 7 to 10 times of the vacuum phototube and this current ratio is called the gas-amplification factor.

Gas phototubes are not highly linear with incident light intensity and hence, they are not suitable for use with modulated light above 2 kHz since the ionisation process takes a finite time to accomplish. The non-linear characteristics of the gas filled phototube with a load resistance of RL = 10 M is shown in Fig. 22.17(b).

Emitted currents from photoelectric surfaces are very small, especially with low light levels. These currents can be directly amplified in a device called electron multiplier or photomultiplier. The photomultiplier tube consists of an evacuated glass envelope containing a photocathode, an anode and several additional electrodes, called dynodes, each at a higher voltage than the previous dynode. Photomultiplier or Multiplier phototube uses secondary emission to provide current multiplication in excess of a factor of 106. Figure 22.18 shows the arrangement of a photomultiplier. It consists of six dynodes which are maintained at increasing potentials in sequence from photocathode C to the anode A. When light falls on the cathode, electrons are emitted and directed at a high velocity toward dynode d1 which is at a higher potential. They bombard the treated surface of dynode d1 which has a secondary emission coefficient, , above unity and dynode d1 liberates secondary electrons for every primary electron striking it. These secondary electrons are focused to a second dynode d2 which is at a relatively higher potential above that of d1. This surface may also have a secondary emission coefficient, , so that 2 electrons leave due to every electron originally leaving the photoelectric cathode C. This process of secondary emission is repeated ‘n’ times on ‘n’ electrodes or dynodes as they are called, giving an overall current gain of n. In practice, may be in the range of 5 to 10, and as many as 9 cascaded dynodes are used for current gains as high as 109. The dynodes are shaped to form curved electric fields which will focus the electrons on to each succeeding dynode. If the electrons are deflected from their normal path between stages due to magnetic fields and miss a dynode, the gain falls. To minimise this effect, -metal magnetic shields are often placed around the photomultiplier tube. Thus, the original emission of electrons from the photocathode are multiplied many times and are finally collected by the anode.

A

The characteristics of a photomultiplier depend upon the voltage per dynode and upon the potential between the last dynode and collector. Performance in terms of a last dynode-to-collector voltage is shown in Fig. 22.19.

Typical anode current ratings range from a minimum of 100 A to a maximum of 1 mA. Luminous sensitivities range from 1 A per lumen or less, to over 2000 A per lumen. The extreme luminous sensitivity possible with these devices is 100 A per lumen, i.e., only 10–5 lumen is needed to produce 1 mA of output current. Since they have fast response, low noise, ultra high sensitivity and small dark current, they find wide applications in space explorations, laser communications, scintillators and radiation detectors of X-rays, gamma rays and energetic particles found in nuclear physics.

The Light Emitting Diode (LED) is a PN junction device which emits light when forward biased, by a phenomenon called electroluminescence. In all semiconductor PN junctions, some of the energy will be radiated as heat and some in the form of photons. In silicon and germanium, greater percentage of energy is given out in the form of heat and the emitted light is insignificant. In other materials such as gallium phosphide (GaP) or gallium arsenide phosphide (GaAsP), the number of photons of light energy emitted is sufficient to create a visible light source. Here, the charge carrier recombination takes place when electrons from the N-side cross the junction and recombine with the holes on the P-side. LED under forward bias and its symbol are shown in Figs 22.20(a) and (b), respectively. When an LED is forward biased, the electrons and holes move towards the junction and recombination takes place. As a result of recombination, the electrons lying in the conduction bands of N-region fall into the

holes lying in the valence band of a P-region. The difference of energy between the conduction band and the valence band is radiated in the form of light energy. Each recombination causes radiation of light energy. Light is generated by recombination of electrons and holes whereby their excess energy is transferred to an emitted photon. The brightness of the emitted light is directly proportional to the forward bias current. Figure 22.20(c) shows the basic structure of an LED showing recombination of carriers and emission of light. Here, an N-type layer is grown on a substrate and a P-type is deposited on it by diffusion. Since carrier recombination takes place in the P-layer, it is kept uppermost. The metal anode connections are made at the outer edges of the P-layer so as to allow more central surface area for the light to escape. LEDs are manufactured with domed lenses in order to reduce the reabsorption problem. A metal (gold) film is applied to the bottom of the substrate for reflecting as much light as possible to the surface of the device and also to provide cathode connection. LEDs are always encased to protect their delicate wires. The efficiency of generation of light increases with the increases in injected current and with a decrease in temperature. The light is concentrated near the junction as the carriers are available within a diffusion length of the junction. LEDs radiate different colours such as red, green, yellow, orange, blue and white. Some of the LEDs emit infrared (invisible) light also. The wavelength of emitted light depends on the energy gap of the material. Hence, the colour of the emitted light depends on the type of material used is given as follows. Gallium arsenide (GaAs) – infrared radiation (invisible) Gallium phosphide (GaP) – red or green Gallium arsenide phosphide (GaAsP) – red or yellow In order to protect LEDs, resistance of 1 kW or 1.5 kW must be connected in series with the LED. LEDs emit no light when reverse biased. LEDs operate at voltage levels from 1.5 to 3.3 V, with the current of some tens of milliamperes. The power requirement is typically from 10 to 150 mW with a life time of 1,00,000 + hours. LEDs can be switched ON and OFF at a very fast speed of 1 ns. They are used in burglar alarm systems, picture phones, multimeters, calculators, digital meters, microprocessors, digital computers, electronic telephone exchange, intercoms, electronic panels, digital watches, solid state video displays and optical communication systems. Also, there are two-lead LED lamps which contain two LEDs, so that a reversal in biasing will change the colour from green to red, or vice-versa. When the emitted light is coherent, i.e. essentially monocromatic, then such a diode is referred to as an Injection Laser Diode (ILD). The LED and ILD are the two main types used as optical sources. ILD has a shorter rise time than LED, which makes the ILD more suitable for wide-bandwidth and high-data-rate applications. In addition, more optical power can be coupled into a fiber with an ILD, which is important for long distance transmission. A disadvantage of the ILD is the strong temperature dependence of the output characteristic curve.

The infrared emitting diodes are PN junction gallium arsenide devices which emit a beam of light when forward biased. When the junction is energised, electrons from the N-region will recombine with

the excess holes of the P-material in a specially formed recombination region sandwiched between the P- and N-type materials. This recombination, which tends to restore the equilibrium carrier densities, can result in the emission of photons from the junction. The radiant energy from the device is infrared with a typical peak at 0.9 m, which ideally matches the response of silicon photodiode and phototransistors. These infrared emitting diodes are used in shaft encoders, data-transmission systems, intrusion alarms, card and paper tape readers, and high density mounting applications. The shaft encoder can produce 150 W of radiant energy at 1.2 V and 50 mA.

Liquid Crystal Displays (LCDs) are used for display of numeric and alphanumeric character in dot matrix and segmental displays. The two liquid crystal materials which are commonly used in display technology are nematic and cholesteric whose schematic arrangement of molecules is shown in Fig. 22.21(a). The most popular liquid crystal structure is the Nematic Liquid Crystal (NLC). In this type, all the molecules align themselves approximately parallel to a unique axis (director), while retaining the complete translational freedom. The liquid is normally transparent, but if subjected to a strong electric field, disruption of the well ordered crystal structure takes place causing the liquid to polarise and turn opaque. The removal of the applied electric field allows the crystal structure to regain its original form and the material becomes transparent. Based on the construction, LCDs are classified into two types. They are (i) Dynamic scattering type, and (ii) Field effect type. The construction of a dynamic scattering liquid crystal cell is shown in Fig. 22.21(b). The display consists of two glass plates, each coated with tin oxide (SnO2) on the inside with transparent electrodes separated by a liquid crystal layer, 5 to 50 m thick. The oxide coating on the front sheet is etched to produce a single or multi-segment pattern of characters, with each segment properly insulated from each other. A weak electric field applied to a liquid crystal tends to align molecules in the direction of the field. As soon as the voltage exceeds a certain threshold value, the domain structure collapses and the appearance is changed. As the voltage grows further, the flow becomes turbulent and the substance turns optically inhomogenous. In this disordered state, the liquid crystal scatters light. Thus, when the liquid is not activated, it is transparent. When the liquid is activated, the molecular turbulence causes light to be scattered in all directions and the cell appears to be bright. This phenomenon is called dynamic scattering. The construction of a field effect LCD display is similar to that of the dynamic scattering type, with the exception that two thin polarising optical filters are placed at the inside of each glass sheet. The LCD material is of twisted nematic type which twists the light (change in direction of polarisation) passing through the cell when the latter is not energised. This allows light to pass through the optical filters and the cell appears bright. When the cell is energised, no twisting of light takes place and the cell appears dull. Liquid crystal cells are of two types: (i) Transmittive type, and (ii) Reflective type. In the transmittive type cell, both glass sheets are transparent so that light from a rear source is scattered in the forward direction when the cell is activated.

Helix axis

Pitch

Director (i)

(ii) (a) Liquid crystal

Spacer

Transparent electrode

Glass

Transparent electrode for transmissive type (or) Reflecting electrode for reflective type

The reflective type cell has a reflecting surface on one side of the glass sheet. The incident light on the front surface of the cell is dynamically scattered by an activated cell. Both types of cells appear quite bright when activated even under ambient light conditions. Liquid crystals consume small amount of energy. In a seven segment display the current drawn is about 25 mA for dynamic scattering cells and 300 mA for field effect cells. LCDs require a.c. voltage supply. A typical voltage supply to dynamic scattering LCDs is 30 V peak-to-peak with 50 Hz. LCDs are normally used for seven-segmental displays. (i) The voltages required are small. (ii) They have a low power consumption. A seven segment display requires about 140 W (20 W per segment), whereas LEDs require about 40 mW per numeral. (iii) They are economical.

(i) LCDs are very slow devices. The turn ON and turn OFF times are quite large. The turn ON time is typically of the order of a few ms, while the turn OFF time is 10 ms. (ii) When used on d.c., their life span is quite small. Therefore, they are used with a.c. supplies having a frequency less than 50 Hz. (iii) They occupy a large area.

LED Consumes more power–requires 10–250 mW power per digit

LCD Essentially acts as a capacitor and consumes very less power–requires 10–200 mW power per digit

Because of high power requirement, it requires Can be driven directly from IC chips external interface circuitry when driven from ICs Good brightness level

Moderate brightness level

Operable within the temperature range – 40 to 85 °C

Temperature range limited to – 20 to 60 °C

Life time is around 100,000 hours

Life time is limited to 50,000 hours due to chemical degradation

Emits light in red, orange, yellow, green blue and Invisible in darkness – requires external illumination white Operating voltage range is 1.5 to 5 V d.c. Response time is 50 to 500 ns

Operating voltage range is 3 to 20 V a.c. Has a slow decay time – response time is 50 to 200 ms

Viewing angle 150°

Viewing angle 100°

The Nixie tube is a numeric indicator based on glow discharge in cold cathode gas filled tubes. It is a small vacuum tube having a common anode and 10 individual cathodes. Each of the cathodes is made of a thin wire, and the anode is also in the form of a thin frame. The cathode take the form of numbers from 0 through 9. These are stacked from front to rear in the tube, which has a transparent front. The tube is a sort of glorified neon bulb. The Nixie tube is a non-planar display device. It is gaseous glow tube having a set of electrodes, each shaped in the form of a digit. When a particular digit is selected, the corresponding electrode is surrounded by a gaseous discharge and glows. As the electrodes are stacked one behind the other, the various digits appear in different planes in the readout. The basic construction of a digital indicator Nixie tube is shown in Fig. 22.22. The device works on the principle that when a gas breaks down, a glow discharge is produced. A gauze electrode with a positive voltage supply functions as an anode, and there are 10 separate wire contacts, each in the shape of a numeral from 0 through 9. The electrodes are enclosed in a gas filled glass envelope with connecting pins at the bottom. Neon gas is usually employed and it gives an orange-red glow when activated. When different gases are used, other colours can be made available.

In a Nixie tube, the separate cathodes are connected to the control circuitry. Grounding a particular cathode causes the neon gas around that tube to ionize and the number is illuminated with an orange glow which is clearly visible. Obviously there will be as many tubes used in particular display as the

desired number of digits. A transistor gate is usually employed at each cathode so that the desired numeral can be switched ON. The circuitry driving the Nixie tubes is simpler than that for seven-segment displays. However, high voltages (150–220 V) are required to produce glow discharge. The current required is of the order of 1–5 mA. The Nixie tubes are bulkier in size than the seven-segmental displays. Special Nixie tubes have 15 cathodes constituting 15 segments that can be used to produce numeric as well as alphanumeric characters. The life time of a Nixie tube is dependent on gas pressure, electrode material and the spacing between the electrodes. The Nixie tubes generally provide a display which is brighter and has large numbers than the LED types. However, they require a relatively high exciting voltage and draw very high current for practical battery operation. Thus, these units are generally line operated. The Nixie tube display is not as visible under high ambient light conditions as the reflective liquid crystal type. The reliability of the Nixie display in high ambient light is better than that of the LED displays.

Display devices provide a visual display of numbers, letters, and various signs in response to electrical input, and serve as constituents of an electronic display system. Display devices can be classified as

The optical devices described so far were capable of operating in an OFF/ON mode. LEDs are used as low consumption indicator lamps. Also, both LEDs and LCDs are potentially more useful as elements in alphanumeric display panels. There are two possible arrangements of optical displays, viz. seven segment and dot matrix, the choice being based on the display size, definition and allowed circuit complexity. One way of producing an alphanumeric display is to make a seven-segment monolithic device, as shown in Fig. 22.23(a), which can display all numerals and nine letters. Each segment contains LED/ LCD which can be turned ON or OFF to form the desired digit. Each segment of the array has to be switched in response to a logic signal. For example, Fig. 22.23(a) shows the response to a logic signal corresponding to 2, in which segments a, b, d, e and g have been switched ON and c and f remain OFF. Similarly, when all segments are ON, the digit formed is 8. If only the center segment, g, is OFF, the digit will be zero. Common anode and Common cathode seven segment LED displays are shown in Fig. 22.23(b). Common anode type LED displays require an active LOW configuration, whereas an active HIGH circuitry is necessary for the common cathode type LED display. The seven segment displays are used in digital clocks, calculators, microwave ovens, digital multimeters, microprocessor trainer kits, stereo tuners, etc. Another method of producing an alphanumeric display is to make a dot matrix of LEDs/LCDs in a monolithic structure. Commonly used dot matrices for this display are 5 × 7, 5 × 8 and 7 × 9, which can display 64 different characters including the alphabets, numerals and various symbols, by driving the appropriate horizontal and vertical inputs. A 5 × 7 dot matrix assembly using LEDs and the corresponding wiring pattern is shown in Fig. 22.24.

LED displays are available in many different sizes and shapes. The light emitting region is available in lengths from 0.25 to 2.5 cm.

The emissive type displays like CRTs have the disadvantages of bulkier size, radiation effects, more power consumption, etc. Such devices are not suitable for portable applications. Portable computers require lightweight, low-power displays, and size suitable for one-on-one computing. The leading

technology is the liquid-crystal display (LCD), which is nonemissive and based on the properties of a class of materials known as liquid crystals. The particular type of liquid crystal used in displays is known as nematic because of its elongated rodshaped structure of molecules. The molecules crystals when placed into a container that has its interior surfaces slightly grooved, will naturally align themselves with the pattern of the grooves. Also, if an electric field is applied in this situation, the molecular alignment will shift to be more or less parallel to the applied electric field. This effect of liquid crystals can be used to produce a display by viewing the crystal material with polarized light. The alignment of the crystal molecules is capable of rotating the light’s polarization. The structure shown in Fig. 22.25 is called a twisted nematic display. The twisting is because of the grooves in the top and bottom plates that are perpendicular to each other. If polarized light is applied to the cell with the polarization parallel to the top grooves, the polarization will rotate by 90 degrees going through the cell. A second polarizer perpendicular to the first one is placed at the bottom of the cell, so that the light rotated by the cell will pass through it. However, if an electric field is applied to the cell in a direction perpendicular to the surface of the cell, the molecules will align with the field and the twisting effect is destroyed. The result is that there is no rotation of polarization, and light therefore will be blocked by the bottom polarizer.

The electrodes are placed on the top and bottom grooved glass plates to control the effect locally for an array of pixels. There will be no effect if the electric field is below certain threshold. This helps in switching of individual pixels by using the combination of voltage applied to row and column electrodes to select the pixel at the intersection of the electrodes. Liquid crystal displays are available in different sizes both in colour and in monochrome. The use of LCD in pocket size TV receivers, video games, mobile phones, lap-top computer displays has led to an increased pace of development of LCDs in video display units. The advantages of LCDs are compactness, less weight, and low power consumption, however, LCDs suffer from the limitations of contrast and brightness. An LCD display consists of a P-channel MOS switching matrix of M×N pixels. The gates of all transistors in a horizontal row are connected to each horizontal common bus, while the drains of the transistors in vertical columns are connected to common vertical buses, as shown in Fig. 22.26. A shift register drives the horizontal gate buses that provide the row address and each row is selected in sequence. The video information is placed on each column bus of drain connections, during the horizontal scan via a set of sample and hold stages, which hold and store the respective line pixel information. This creates a line sequential display, and the information on each drain line is updated only once every horizontal period of 64 microseconds. As the number of rows available

are less instead of 625 lines as in a standard TV receiver, both the interlaced fields are scanned on the same rows, while the extra lines of each field are eliminated during the top and bottom overscan. Colour LCDs are possible with an active matrix TFT (Thin Film Transistor) display developed jointly by IBM and Toshiba. A schematic arrangement of a typical TFT LCD colour display is shown in Fig. 22.27. A diffusion plate uniformly spreads the fluorescent backlight over the polarizing filter. The TFTs are addressed by row and column lines. The TFTs can apply a voltage to the liquid crystal material and it forms a capacitor along with the display and the common electrodes, for storing the voltage for the duration of the frame. The pixels are in quadruplet subpixels of red, green, blue and white translucent dots. In the absence of any applied voltage, the liquid crystals twist the polarized light to make it either parallel or perpendicular to the second polarizer, forming a lighted or dark pixel. When an electric field is applied by means of selecting a particular TFT assigned to the dot, the crystal orientation is disrupted. This leaves the polarized light unaffected, and the light shines through the pixels. The pixel can assume one of 16 colours (24) depending on the combination of primary colours with white.

A leading contender for a television flat-panel display is the plasma display panel (PDP). This is an emissive display and uses an electronic discharge in a gas, such as xenon, to produce the radiation. In colour displays, ultraviolet rays are emitted by the radiation that excite normal colour phosphors. PDPs have been used for more than 25 years in special military and industry applications, and now they are emerging as a most promising technology for large-screen colour television displays for HDTV. Figure 22.28 shows the cross-sectional view of one type of colour PDP. A mixture of inert gases is sandwiched between the two glass plates. This mixture of gases is excited locally by electric fields set up by arrays of parallel, but orthogonal electrodes on the inner surface of glass. When the voltage applied

to a pair of horizontal and vertical electrodes is sufficiently high, a discharge occurs at the intersection of the electrodes, and ultraviolet energy is emitted. This emission excites the colour phosphor located

for one PDP cell of the display. The voltage in the graph represents the combined voltages of the two control lines that intersect at the cell. The significant feature is the extreme nonlinearity that occurs at the firing voltage VF. The cell abruptly begins drawing current, which will increase rapidly until it is limited by some means outside of the cell. Thus, there is no practical way to control the brightness of a cell by conventional analog means. The cell is either on or off. The discharge current can be limited either by using an external resistor or using an internal capacitor to limit the current. The latter approach is the most popular because it also facilitates a memory feature that allows the pixel-on time to be increased. In PDP using a capacitor to limit the current, a dielectric layer is placed over the top electrodes of the panel to form a capacitor as shown in Fig. 22.28. As a result of this capacitive coupling, the cells can only be accessed by transient changes in the voltages applied to the electrodes. When a cell is fired, a charge begins to accumulate on the dielectric layer above that cell and this in turn reduces the effective voltage of the discharge. When enough charge accumulates, the voltage drops and extinguishes the discharge. However, the charge on the dielectric, called the wall voltage, remains and it allows the cell to refire on the next transition of the applied voltage. Thus, the cell also remembers whether it was fired on the last cycle and continues to refire and give out a pulse of light for every successive cycle until the wall voltage is erased.

An optocoupler is a solid-state component in which the light emitter, the light path and the light detector are all enclosed within the component and cannot be changed externally. As the optocoupler

provides electrical isolation between circuits, it is also called optoisolator. An optoisolator allows signal transfer without coupling wires, capacitors or transformers. It can couple digital (ON/OFF) or analog (continuous) signals. The schematic representation for an optocoupler appears in Fig. 22.30. The optoisolator, also referred to as an optoelectronic coupler, generally consists of an infrared LED and a photodetector such as PIN photodiode for fast switching, phototransistor Darlington pair, or photo-SCR combined in a single package. Optoisolators transduce input voltage to proportional light intensity by using LEDs. The light is transduced back to output voltage using light sensitive devices. GaAs LEDs are used to provide spectral matching with the silicon sensors. The wavelength response of each device is made to be as identical as possible to permit the highest measure of coupling possible. There is a transparent insulating cap between each set of elements embedded in the structure (not visible) to permit the passage of light. They are designed with very small response times in such a way that they can be used to transmit data in the MHz range. The rigid structure of this package permits one-way transfer of the electrical signal from the LED to the photodetector, without any electrical connection between the input and output circuitry. The extent of isolation between input and output depends on the kind of material in the light path and on the distance between the light emitter and the light detector. A significant advantage of the optoisolator is its high isolation resistance, of the order of 1011 with isolation voltages upto 2500 V between the input and output signals, and this feature allows it to be used as an interface between high voltage and low voltage systems. Application for this device includes the interfacing of different types of logic circuits and their use in level-and-position-sensing circuits. In the optoisolator, the power dissipation of LED and phototransistor are almost equal and ICEO is measured in nano-amperes. The relative output current is almost constant when the case temperature varies from 25 to 75 °C. The VCE voltage affects the resulting collector current only very slightly. The switching time of an optoisolator decreases with increased current, while for many devices it is exactly the reverse. It is only 2 s for a collector current of 6 mA and a load resistance of 100 . The schematic diagrams for a photodiode, photo-Darlington pair and photo SCR optoisolator are illustrated in Fig. 22.31.

The principal motivations behind new communication systems are (i) to improve transmission fidelity, (ii) to increase the data rate (more information transmitted), and (iii) to increase the transmission distance between relay stations. Optical frequencies lie in the range 1014 to 1015 Hz. The laser information carrying capacity is greater than the microwave system by a factor of 105. A fiber can carry approximately 10 million TV channels. In optical fiber communication, electromagnetic wave in the optical frequency region is used as the carrier. The schematic block diagram of an optical fiber communication system is shown in Fig. 22.32. The message to be transmitted is converted into a suitable electrical form by the electrical transmit section. This electrical signal is allowed to modulate the light output from the optical source, which may be either a light emitting diode (LED) or an injection laser diode (ILD). The modulated light is launched into the optical fiber which is the communication channel linking the transmitter with the receiver. At the receiving end, the input optical signal is converted into suitable electrical variations by the optical detector, which may be either a PIN photodiode or Avalanche photodiode. These electrical variations are converted to the original message form in the electrical receive section and given to the destination.

An optical fiber is a piece of very thin (hair-thin), highly pure glass, with an outside cladding of glass that is similar, but because of a slightly different chemical composition, has a different refractive index. As shown in Fig. 22.33, the simplest optical fiber consists of a central cylindrical core of constant refractive index n1 and a concentric cladding surrounding the core of slightly lower refractive index n2. An optic fiber cable is quite similar in appearance to the coaxial cable system. This type of fiber is called step index fiber, whose core diameter is in the range of 2 to 200 mm, as the refractive index makes a step change at the core-cladding interface. The refractive index profile which gives the variation of refractive index with distance along the cross section of the fiber may be defined as n(r) = n1; r < a (core) = n2; r ≥ a (cladding) The refractive indices of core and cladding are related by the relative refractive index difference (D) between the core and the cladding by the relation

n21 – n22 D = ______ 2 n21 n1 – n2 ª ______ n , where n1 ª n2 1

As the core and the cladding are normally made of glass or plastic, the refractive indices n1 and n2 lie around 1.5. Step index fiber may be used for multimode or single-mode propagation. If a light ray travelling in the core of higher refractive index is incident at the core-cladding interface with an angle of incidence, with respect to the normal, greater than the critical angle, it will be reflected back into the originating dielectric medium, i.e. core, with high efficiency (around 99%). This phenomenon is known as total internal reflection. In an optical fiber, transmission of light ray takes place by a series of total internal reflections at the core-cladding interface as shown in Fig. 22.34. Low index cladding f f High index core

f f Core axis f f

In the graded-index fiber, the refractive index gradually reduces from the center to the core to the cladding boundary in a parabolic manner. The graded index fibers are easier to manufacture. Lower attenuations are possible with step index fibers. 1. As an optical carrier in the range of 1014 to 1015 Hz is used, the system has enormous potential bandwidth.

2. Optical fibers have very small diameters and hence they are of small size and weight. 3. Optical fibers are fabricated from glass or a plastic polymer which are electrical insulators so that good electrical isolation in a hazardous environment is possible. 4. As an optical fiber is a dielectric waveguide, it is free from electromagnetic interference (EMI), radio frequency interference (RFI), or switching transients giving electromagnetic pulses. 5. As optical fibers do not radiate light, they provide a high degree of signal security and cross talk between parallel fibers is avoided. 6. Optical fiber cables exhibit very low attenuation compared with copper cables making them suitable for long-haul telecommunication applications. Hence, they are highly reliable and easy to maintain. 7. Optical fibers are manufactured with very high tensile strengths and they are flexible, compact and extremely rugged. 8. The glass from which the optical fibers are made is derived from sand which is a natural resource. So, in comparison with copper conductors, optical fibers offer the potential for low cost line communication. 9. Optical fibers offer high tolerance to temperature extremes as well as to liquids and corrosive gases and have longer life span. (i) Computers Fibers are used because of their greater data handling capacities and higher memory densities. The fibers are used for mutual interfacing of central processor, linking them to peripheral devices, data transmission within the main frame. Hence, reduced bit errors and free environmental interference are assured. (ii) LAN In local area networks, fibers are used to link the computers in ring, star or bus topology. They find applications in office operations, private automatic branch exchanges etc. (iii) Industrial electronics They are used in power plants, rail-road networks and metal industry for data acquisition control and signal processing, as transmission is not affected by high energy fields. In medical electronics by using fibers, noise free control signals are possible. In automobile manufacturing, fibers are used as sensors because of less weight. (iv) Telecommunications The enormous bandwidth of optical fiber communication system finds their principle use in long distance communication for transmission of speech, video and digital data signals. In the near future, all the existing copper based trunk lines will be replaced by optical fibers. Table 22.2 gives the comparison of conventional electrical and optical communication systems.

Parameters

Conventional electrical

Optical

Carrier frequency

104–1010 Hz

1014–1015 Hz

Bandwidth

Smaller to medium

larger about a million times greater than RF carrier

Source characteristic

Inherently coherent

Coherent and non-coherent (LED/ILD) (Contd)

(Contd)

Signal

Signal propagates as voltage or current

Signal propagates as wavefront of light

Modulation formats

AM/FM/PM/PCM are possible

Intensity modulation, phase, frequency polarisation are possible

Analog, digital transmission of signals

Both are feasible

Both are feasible

Channel

Free space as a guided wave channel, coaxial cable and metallic waveguides

Free space and fibers (dielectric)

Techniques for modulation and demodulation

Purely electronics

Either purely electronics or hybrid versions of electronic and optical methods

Detection

Purely electronics

Optoelectronics methods

Components

R, L, C

Lenses, mirrors, beam splitters, gratings, prisms and R, L, C

Theoretical aspects

Linear system theory (LST) and Statistical theory of communication (STC)

LST, STC, optical diffraction and interference theory

Microminiaturisation

LSI, VLSI

Through integrated optics (IO) using thin film technology

Power density

Moderate

High

Transmitter antenna and receiver antenna size

Larger

Small

Attenuation

Coaxial cables have 10 dB/km

Optical fibers have 0.25 dB/km

The success of an engineer is judged by his ability to measure the unknown quantity precisely and interpret the circuit performance correctly. Instruments are essentially used in measurements as the physical means of determing the unknown quantity. The terms commonly used in the field of measurements are defined as follows: The degree of closeness of a measurement compared to the true value. Consistency of the instrument to produce the same output for the given value of the input. The ratio of the change in the output of the instrument to a change in the input. The smallest change in the input which can be measured by an instrument. The deviation of the measured value from the true value. Measurement can be done by mechanical, electrical and electronic means. Accordingly, instruments are classified as (i) Mechanical instruments, (ii) Electrical instruments, and (iii) Electronic instruments. Among the above three measurement techniques, the electronic measurement is very sensitive in detection of measured quantity because amplification is provided by the active electronic device. It has higher sensitivity and greater flexibility in recording, indicating and controlling the measured quantity and fast response. In electronic measurement systems, there are two types of instruments, namely, (i) Analog instruments, and (ii) Digital instruments. Analog instruments are deflection type instruments with a scale calibrated in terms of measured quantity and a movable pointer. The value of the electrical quantity being measured is given by pointer deflection on the scale. But digital instruments use logic circuits and techniques for measurement and the quantity is displayed as a numerical reading. Light Emitting Diode (LED) display or Liquid Crystal Display (LCD) is used for digital readouts.

The digital instruments have several advantages over analog instruments such as easy readability, greater accuracy, better resolution, automatic polarity and zeroing, and output signals can be directly printed and used for further processing.

The CRO is a versatile electronic testing and measuring instrument that allows the amplitude of the signal which may be voltage, current, power etc., to be displayed primarily as a function of time. It is used for voltage, frequency and phase angle measurement and also for examining the waveforms, from d.c. or very low frequency to very high frequencies. Figure 23.1 shows the basic block diagram of a CRO. It comprises the main sections of (i) Horizontal and vertical voltage amplifiers, (ii) Power supply circuits, and (iii) Cathode Ray Tube (CRT).

These amplifiers are connected between the input terminals and the deflection plates. The function of the amplifiers is to increase the deflection sensitivity for weak input voltages.

The input signal is fed through a calibrated attenuator and a wide band high gain vertical amplifier to the vertical deflection plates of the CRT. The horizontal amplifier which is connected to the horizontal plates of the CRT is fed from an internally generated time base, usually a sawtooth waveform generator, or alternatively the horizontal amplifier can also be fed from an externally connected X input. The horizontal sweep (sawtooth) signal is triggered by a portion of the input signal applied to the vertical plates. A finite amount of time (in the range of sec.) is elapsed before the sawtooth waveform is applied to the horizontal plates. Hence, to observe the starting edge of the input signal fully, it should be delayed by the same amount of time in the delay line.

The power supply unit provides high voltages required by the CRT to generate and to accelerate the electron beam in addition to supplying the required operating voltage for the other circuits of the oscilloscope. The CRT requires high voltages, of the order of a few thousand volts, for acceleration and a low voltage for the heater of the electron gun which emits electrons. The CRO has various control switches on the panel. The intensity of the spot and focusing can be adjusted by the respective control knobs.

The CRT is the heart of the oscilloscope. It is a vacuum tube of special geometrical shape and converts an electrical signal into visual one. A heated cathode emits electrons which are accelerated to high velocity and are brought to focus on a fluorescent screen. When the electron beam strikes the screen of the CRT, a spot light is produced. The electron beam on its journey, is deflected in response to the electrical signal under study. As a result, the waveform of the electrical signal is displayed. As shown in Fig. 23.1, the CRT has various parts which are described below. It houses the electron gun, vertical and horizontal plates, and a screen on the conical front end. The inner walls of the CRT between neck and screen are usually coated with a conducting material (graphite) called acquadag. This conductive coating is electrically connected to the accelerating anode so that electrons which accidentally strike the wall are returned to the anode. It prevents the wall of the tube from charging to a high negative potential. The screen is coated with a suitable fluorescent material depending on the required color of the spot. Some of the substances which give characteristic fluorescent colors are Zinc orthosilicate : green (used in CRT for general purpose) Calcium tungstate : blue (used in CRT for fast photography) Zinc sulphide or Zinc cadmium sulphate : white (used in television receiver tubes). It produces a focused beam of electrons. It consists of an indirectly heated cathode, a control grid, a focusing anode and an accelerating anode. The control grid is at a negative potential with respect to cathode, whereas the two anodes are maintained at a high positive potential with respect to cathode. These two anodes act as an electrostatic lens to converge the electron beam at a point on the screen. The cathode consists of a nickel cylinder coated with an oxide coating that provides plenty of electrons. The control grid encloses the cathode and consists of a metal cylinder with a tiny circular

opening to keep the electron beam small in size. The focusing anode focuses the electron beam to a sharp point by controlling the positive potential on it. The positive potential (about 10,000 V) on the accelerating anode is much higher than that on the focusing anode so that this anode accelerates the narrow beam to high velocity. Therefore, the electron gun generates a narrow, accelerated beam of electrons which produces a spot of light when it strikes the screen. The electron beam comes under the influence of vertical and horizontal deflection plates before it strikes the screen. When no voltage is applied to the vertical deflection plates, the electron beam produces a spot of light at the center of the screen. If the upper plate is positive with respect to the lower plate, the electron beam is deflected upwards and strikes the screen above its center. If the upper plate is negative with respect to the lower plate, the electron beam is deflected downwards and strikes the screen below its center. Thus the electron beam is made to move up and down vertically by controlling the voltage on the vertical plates thereby producing spots of light on the screen. When a sinusoidal voltage is applied to the vertical deflection plates, the upper plate is positive during the positive half cycle and negative during the negative half cycle thereby producing a continuous vertical line on the screen. The electron beam is made to move horizontally from side to side at a uniform rate by applying a sawtooth wave which varies linearly with time across the horizontal deflection plates. Thus, the spot of light can be moved all over the surface of the screen by the simultaneous action of both vertical and horizontal deflection plates. In order to get the exact pattern of the signal on the screen, the signal voltage is given to the vertical deflection plates and sawtooth wave to the horizontal deflection plates. Conventionally, CRTs form the basis of cathode ray oscilloscopes (CROs), TVs and consoles/monitors. They are useful in displaying numeric, alphanumeric and graphic displays with high resolution. These are of two types: (i) Electrostatic (used in CROs) (ii) Electromagnetic (used in TVs) There are also storage CRTs using digital storage, mesh storage, phosphor storage and transfer storage. Flat CRTs are also available.

Some special oscilloscopes, which are discussed briefly in the following section, have been designed for specific applications. A dual-beam oscilloscope is useful to observe two signals simultaneously and compare their waveforms. Figure 23.2 shows the block diagram of a dual beam CRO. It has two completely separate electron guns, two sets of Vertical deflecting plates (Y-plates) and a single set of Horizontal deflecting plates (X-plates). Both the channels have a common time base but have completely independent pre-amplifiers, delay lines and vertical amplifiers. Only one beam can be synchronised at one time because the horizontal sweep is common for both signals. In order to lock the two signals on the CRT screen, the two signals must have the same frequency and phase or must be related harmonically.

The dual-beam CRO is used to observe both the input and output signals of the amplifier under test. Signal A may be the input signal and signal B may be the output signal from the amplifier. The function of dual trace CRO is similar to dual-beam CRO but this CRO has a single electron gun. One single electron beam is split into two beams by means of an electronic switch. The two signals are displayed simultaneously. Figure 23.3 shows a block diagram of the two vertical input channels of a dual trace CRO. Channel A Pre-amplifier and attenuator

Delay line

Channel B Pre-amplifier and attenuator

Delay line

A B EXT

Electronic switch

Vertical amplifier

Vertical deflection plates (VDP)

HDP

S

Trigger circuit

Sweep generator

Horizontal amplifier

Line

Each channel has its own calibrated input attenuator and positioning control. Therefore, the amplitude of each signal can be independently adjusted. The electronic switch alternately connects the two input

channels to the vertical amplifier. The signals pass through the common vertical channel or vertical amplifier. The horizontal sweep is shared by the two channels on the time basis. The dual trace oscilloscopes have four modes of operation, namely A, B, alternate and chopped. In the A or B mode, only the input at that channel is displayed. In the alternate mode, the inputs are displayed on alternate traces. The switching rate of the electronic switch is synchronised to the sweep rate, so that the CRT spot traces the channel A signal on one sweep and the channel B signal on the succeeding sweep. This mode of operation is generally preferred when displaying relatively high-frequency signals. In the chopped mode, the electronic switch is free running at the rate of 100–500 kHz, entirely independent of the frequency of the sweep generator. The switch successively connects small segments of A and B waveforms alternately to the main vertical amplifier at a relatively fast chopping rate of 500 kHz. If the sweep rate is low, the chopped mode is normally used as the alternate mode would provide a display with considerable flicker. disappear from the screen after a relatively short interval of time, as the persistence of the phosphor on the screen ranges only from a few millisec to several sec. In a storage CRO, the display is retained for a much longer time, sometimes even for some hours, after the image was first traced on the screen. This retention feature is, therefore, useful in the study of waveforms which have very low frequency. In a conventional CRO, the start of such a display will fade out before the end is reached. The analog storage oscilloscopes use the phenomenon of secondary electron emission to build up and store electrostatic charges on the surface of an insulated target. The block diagram of a basic Digital Storage Oscilloscope (DSO) is illustrated in Fig. 23.4. The input signal is digitised and stored in memory in digital form. In this digital form, it is capable of being analysed to produce a variety of information about the input signal. The digital data is reconstructed in analog form to view the display on the CRT. In order to ensure that no information is lost, the sampling rate must be atleast twice the highest frequency of the input signal. The digital oscilloscope is primarily limited in speed by the digitizing capacity of the analog to digital converter. Digital oscilloscope is capable of an infinite storage time using its digital memory. A time base in a digital oscilloscope is generated by a crystal clock.

In addition, digital storage oscilloscopes are available in processing and non-processing types. Processing type has built-in computing facility and takes advantage of the fact that all data is already in digital form. DSO is also capable of operating in a look back mode like waveform recorder. If it is triggered, it prints out the stored result on to a hardcopy recorder or disk storage. A sampling CRO is used to examine very fast signals using instruments having bandwidth several orders lower. The gain bandwidth relationship of the vertical amplifier limits the frequency range of signals which can be displayed on a CRO. As shown in Fig. 23.5, samples of the input waveform are taken at different portions of the waveform over successive cycles, with one sample taken per cycle, and each sample slightly delayed with respect to the preceding sample. Then the total picture is stretched, amplified by relatively low bandwidth amplifiers and displayed as a continuous waveform on the screen. The disadvantage of sampling CRO is that it can only make measurements on repetitive waveform signals.

The sampling technique transforms the high frequency input signal into lower frequency domain where conventional low frequency circuit is capable of producing a highly effective display. The sample fre1 quency used in sampling CROs can be as low as ____ of the signal frequency and hence a signal fre100 quency of 1 GHz needs an amplifier bandwidth of 10 MHz.

The modulation index of Amplitude Modulation (AM) waves can be measured using a CRO. The voltage-current characteristics of PN junction diode and transistor, and characteristics of a transformer core can be displayed on CRO. Some more applications are discussed below. If the signal is applied to the vertical deflection plates only, a vertical line appears on the screen. The height of the line is proportional to peak voltage of the applied signal. The amplitude of the signal can be measured by applying the signal to the vertical plates and the sweep is applied to the horizontal plates using internal sweep circuitry. The vertical scale on the CRT screen is marked in centimeters. Each centimeter is further subdivided into 5 parts so that each part represents 0.2 cm. If the peak amplitude of the waveform is 1.7 cm and the scale selected by the dial setting is 1 V/cm, then the amplitude of the signal is 1.4 cm × 1 V/cm = 1.4 V.

and the voltage across it is measured.

f ) is to be measured is given to the vertical input. The number of divisions occupied by one complete cycle of the waveform is measured. The number of divisions multiplied by the time base setting in sec. is equal to the time period (T ) of one cycle. The frequency ( f ) of the waveform is inverse of the time period T, i.e. f = 1/T. If sinusoidal voltages are applied to both vertical and horizontal inputs of CRO, some interesting figures are displayed, which are known as Lissajous figures. Two sine waves of the same frequency produce a Lissajous figure which may be a straight line, an ellipse or a circle, depending on the phase and amplitude of the two signals. Two sine waves of equal amplitudes but different frequencies will produce a figure from which the relationship between the two frequencies can be understood. For example, Fig. 23.6(a) shows that the vertical input signal has twice the frequency of the horizontal input signal. Similarly, Fig. 23.6(b) indicates that horizontal input signal has twice the frequency of the vertical one. Figure 23.6(c) shows three loops indicating that vertical input signal has thrice the frequency of the horizontal one.

A known frequency ( fH) is applied to horizontal input and unknown frequency ( fV) to the vertical input. Then a Lissajous pattern with loops is obtained. The unknown frequency ( fV) can be measured by the following relationship. fV ______________________________ No. of loops cut by horizontal line __ = fH No. of loops cut by vertical line frequency can be calculated from the amplitudes A and B of the Lissajous pattern (an ellipse) shown in Fig. 23.7. The phase difference (deg), q = sin–1 (A/B). Lissajous figures are formed when two sine waves are applied simultaneously to the vertical and horizontal deflecting plates of a CRO. In general, the shape of the Lissajous figures depends on amplitude, phase difference and ratio of frequency of the two waves. Two sine waves of the same frequency and amplitude may produce a straight line, an ellipse or a circle, depending on their phase difference as shown in Fig. 23.8.

CRO is useful to measure the distortion using Lissajous figure. Figure 23.9 shows the connections for testing the frequency distortion of an amplifier network. The audio oscillator is adjusted to a known frequency and is connected to the deflecting plates x –x . The

input signal obtained at the output of the amplifier is connected to the deflecting plates y – y¢. If the amplifier produces higher harmonics of the input frequency due to the nonlinearities of the active device used, the CRO screen shows the loops in Lissajous figure which indicates the presence of distortion. A straight line display indicates the absence of distortion in the amplifier.

In PMMC meter, as shown in Fig. 23.10, there is a coil suspended in the magnetic field of permanent magnet in the shape of a horse shoe. The coil is suspended so that it can rotate freely in the magnetic field. When a d.c. current flows in the coil, electromagnetic torque (EM) is developed and the coil is deflected. The EM torque is counter balanced by the mechanical torque of the control springs attached to it so that the angular position of the movable coil is indicated by a pointer against a fixed reference called a scale. The equation for the developed torque is T = B .A.I.N where

T = torque, newton-meter (N-m) B = flux density in the air gap, Webers/square meter (Tesla) A = effective coil area, square meters (m2) I = current in the movable coil, amperes (A) N = turns of wire of the coil.

The basic PMMC movement is often called d’Arsonval movement, named after its inventor. Referring to Fig. 23.11, the d.c. ammeter is constructed using the basic movement. But the instrument with the basic movement alone can carry only small current for full scale deflection because the coil winding is small and light. When large currents are to be measured, it is necessary to bypass the excess current through a resistance called “shunt” so that the current through the coil of the basic movement is not exceeding its maximum limit.

The resistance of the shunt can be calculated by applying conventional circuit analysis. Since the shunt resistance is in parallel with the meter movement, the voltage drop across the shunt and movement must be same. Vshunt = Vmovement Therefore,

Since

Im R m IsRs = ImRm and Rs = ______ Is I______ R m m Is = I – Im, Rs = I – Im

The current range of the d.c. ammeter can be extended by having a number of shunts, selected by a range switch. Figure 23.12 shows the diagram of a multirange ammeter. The circuit has three shunts, Ra, Rb and Rc which are placed in parallel with the basic movement to give three different current ranges. Switch S is a multiposition make-before-break type. Hence the movement of the pointer will not be damaged because the range of movement is always restricted by the shunt. Ayrton or Universal shunt eliminates the possibility of having the meter in the circuit without a shunt and is shown in Fig. 23.13. For example, the d’Arsonval movement is selected with the internal resistance Rm = 50 W and full scale deflection current Ifsd = 1 mA. If this ammeter is extended with the current ranges of I1 = 1 A, I2 = 5 A, I3 = 10 A, the following design procedures are to be followed. For the (0–I1) range, Ra, Rb and Rc are included and are in parallel with the 50 W movement. Since Ifsd is 1 mA, the shunt will be required to pass a current of 1 A–1 mA = 999 mA. Voltage drop across the

basic movement Vm is 1 mA × 50 W = 50 mV. The voltage across the shunt and the basic movement is the same. 1 × 10 – 3 × 50 Therefore, Ra + Rb + Rc = Vm/(I1 – Ifsd) = ____________ 999 × 10 – 3 Similarly, for (0–I2) range, Ra and Rb are included and are in parallel with the basic movement and Rc is in series with Rm. Therefore, Ifsd (Rc + Rm) Ra + Rb = ____________ I2 – Ifsd For the (0–I3) range, Ra alone serves as the shunt, and Rb and Rc are in series with Rm. Therefore,

Ifsd(Rb + Rc +Rm) Ra = _______________ I3 – Ifsd

Solving the three simultaneous equations, the values of Ra, Rb and Rc can be calculated.

Basic d’Arsonval movement is used to measure d.c. voltage, but voltage across the meter, Vm = Ifsd. Rm, is small. If the voltage to be measured is greater than Vm, the excess voltage is allowed to drop across the series resistance or “multiplier” so that current through the basic movement is not exceeding the value of full scale deflection current.

The basic d.c. voltmeter is shown in Fig. 23.14. The d.c. voltmeter measures the potential difference between two points in a d.c. circuit and is, therefore, connected across a source of emf or a circuit component with correct polarity. V = Im (Rs + Rm) V – ImRm RS = ________ im The multiplier is usually mounted inside the case of the voltmeter for moderate range up to 500 V. For higher voltages, the multiplier may be mounted separately outside the case on a pair of binding posts to avoid excess heating inside the case. The addition of a number of multipliers, together with a range switch, provides the instrument with a workable number of voltage ranges. Figure 23.15 shows a multirange voltmeter using a four-position switch and four multipliers, R1, R2, R3 and R4, for the voltage ranges V1, V2, V3 and V4, respectively. The values of the multiplier can be calculated using the method shown earlier. In an alternate method, as shown in Fig. 23.16, multipliers are connected in a series string and the range selector switches the appropriate amount of resistance in series with the movement. This system has the advantage that all multipliers except the first have standard resistance values and can be obtained commercially in precision tolerances. The low-range multiplier, R4, is the only special resistor that must be manufactured to meet the specific circuit requirements.

A VTVM is an electronic instrument for accurate measurement of low a.c. and d.c. voltages in the order of millivolts. It consists of an ordinary voltmeter and vacuum tubes. It draws small current from the circuit because it has high internal resistance in the order of MW. It has a wide frequency response.

As shown in Fig. 23.17, it includes a vacuum tube diode, a resistance R and a meter M (permanent magnet moving coil instrument), all connected in series. The plate resistance of the diode is not constant and therefore, the plate voltage-current characteristics is non-linear. A high value of series resistance R (100 kW) is used to make the variation in plate resistance negligible. This high series resistance R will limit the current and make the plate voltage-current characteristics linear thereby making the plate current directly proportional to the input voltage. The tube conducts during positive half cycle and does not conduct during the negative half cycle. Therefore, the average current through the meter is given by

lav

Vacuum tube diode

R a.c input

M

Meter

Erms Iav = 0.45 ____ R The meter ‘M’ is calibrated to read the rms value of the applied voltage.

The circuit diagram of a VTVM using triodes is shown in Fig. 23.18. When input is not applied, the plate current flowing in both valves are equal and so the current flowing through the meter M is zero, provided the two triodes are identical. However, in practice, there may be some constructional differences in plates, grids and cathodes of the two valves. Eventually, the two plate currents differ slightly and meter M may show some reading. This error in the meter reading is nullified by changing the resistance re. The voltage to be measured is applied at the input terminals AB, making the grid negative with respect to cathode. This results in a change in the plate current of triode T1 and the plates of T1 and T2 are no longer at the same potential. Therefore, meter ‘M ’ shows the reading depending upon the value of the voltage across terminals AB. Here, triode T1 is used for voltage measurement and T2 for zero adjustment of the meter.

Digital voltmeter (DVM) is a voltage indicating device. The main use of DVM is to measure voltage between two points. It displays d.c. or a.c. voltage as discrete numerals. It is an useful laboratory instrument for several applications. It is also an useful building block of digital instrumentation systems. The utility of a DVM can be easily extended for multiple functions, such as in a Digital Multimeter (DMM) by the addition of simple auxiliary hardware. The DVM is often used in data processing system. An ideal voltmeter has an infinitely high input resistance so that it does not draw any current from the circuit. Consider a meter which has a low input resistance of 1000 W. It cannot give an accurate value of the voltage across a resistance of the same magnitude because the meter shunts the resistance. Therefore, it is important to measure the loading effect of a voltmeter in terms of ohms per volt. The Block diagram of a digital voltmeter is shown in Fig. 23.19. It has three stages: (i) Signal preparation, (ii) Analog to Digital conversion, and (iii) Display unit. The signal preparation stage or input circuit modifies the signal amplitude according to the requirement and it also protects the source from loading. Here, resistive attenuator is used to decrease the large incoming signal and amplifier is used to amplify the small incoming signal to the measurable range. The input circuit for DVM using operational amplifier is shown in Fig. 23.20. Operational amplifier is a multistage integrated circuit. Amplification is controlled with negative feedback since amplifier gain ‘A’ is proportional to the ratio of the feedback and input resistors. Rf A = – ___ Ri

In the next two stages, the analog input signals are typically converted into digital signals in the form of binary or Binary Coded Decimal (BCD) data and suitably displayed in the display unit. The block diagram of dual slope A/D converter with display unit is shown in Fig. 23.21.

The unknown voltage Vin is given to the input of the integrator through the selection switch for a known time period T. The output from the integrator is given by the equation, Vin VC = – ____ T RC Here, R and C are the resistance and capacitance values in the integrator. As the input voltage Vin is positive, the integrator output will be negative ramp as shown in Fig. 23.21. The output from the integrator is compared with zero volts reference in the comparator. The output from the comparator will be a positive voltage. For the entire time period T, the AND gate is opened and during this period the pulses from the crystal clock oscillator is counted in the counter. At the end of known time period T, the counters are reset by the control circuit and at the same time it activates the selection switch so that the negative known reference voltage VR is applied to the input of the integrator. As shown in Fig. 23.22, the output from the integrator will be a positive going ramp given by the equation VR VC = ____ t RC At the end of time period t, VC is equal to zero volts. All this time, the counter is counting and hence, t can be known. Since the integrator output begins at zero volts, integrates down to –VC and then integrates back up to zero volts, the two equations given for VC can be equated as

Vin VR ____ T = ____ t RC RC The value RC will cancel from both sides. Therefore, VR Vin = ___ t T Since VR and T are known values, the unknown input voltage Vin which is the content of the counter is proportional to the variable time period t. A complete DVM on a single chip (IC) is available. They include A/D conversion circuitry and the 1 necessary timing, counting and display circuitry. Examples are the low power 3 __ -digit ICL 7136 and 2 1 the 4 __ -digit ICL 7129; both use LCD 7-segment displays and run from a single 9-V battery. 4 The merits of DVM over other voltmeter types are • Greater speed • Higher accuracy and resolution • No parallax error • Reduced human error • Compatibility with other digital equipment for further processing and recording.

There are two types of Ohmmeters namely, series-type Ohmmeter and shunt-type Ohmmeter.

The series-type ohmmeter circuit is shown in Fig. 23.23, where the meter internal resistance Rm is connected in series with the current limiting resistance Ra and a battery E, with a pair of terminals A & B. The unknown resistance Rx can be connected to this terminal. The meter current Im depends on the value of Rx. As other values are constant, the meter reading is proportional to the value of Rx.

When the terminals of A and B are shorted (Rx = 0), the meter current Im will be maximum causing the meter to reach its full scale deflection (Im = Ifsd) and hence this position is marked as “0 W” on the meter scale. For reverse condition, when the terminals A & B are open (Rx = •), the meter current Im = 0 and hence this position is marked as ‘•’ on the meter scale. Similarly, by connecting different known values of Rx to the terminals A and B, the intermediate readings are marked on the meter scale. It is to be noted that the half-scale position resistance Rh is marked when the unknown resistance is equal to the total internal resistance of the ohmmeter. In the design of the meter shown in Fig. 6.23, the following parameters are considered: Rh = the value of ‘R’, which cause the half scale deflection Ra = current limiting resistor Rb = zero adjust resistor Rm = internal resistance of the movement E = internal battery The half-scale deflection resistance is given by RbRm Rh = Ra + ________ Rb + Rm For producing full-scale deflection, the battery current is expressed by E Ih = ____ 2Rh For producing full-scale deflection, the battery current should be doubled.

(23.1)

(23.2)

Therefore, E It = 2Ih = ___ Rh

(23.3)

Ib = It – Ifsd

(23.4)

The shunt current through Rb is

The shunt voltage (Esh) is equal to the voltage across the movement. Therefore, Esh = Em or IbRb = IfsdRm and

IfsdRm Rb = ______ Ib

(23.5)

Substituting Eq. (23.4) into Eq. (23.5) and using Eq. (23.3), we get IfsdRm IfsdRmRh Rb = ______ = _________ It – Ifsd E – IfsdRh

(23.6)

Upon solving Eq. (23.1) for Ra, we get RbRm Ra = Rh – ________ Rb + Rm

(23.7)

Substituting Eq. (23.6) into Eq. (23.7) and solving for Ra, we get IfsdRmRh Ra = Rh – ________ E Figure 23.24 shows the circuit diagram of a shunt-type Ohmmeter. Here, the internal battery E is connected in series with the adjustable resistor ‘Ra’ and a d’Arsonval movement. There are two terminals A and B connected in parallel with the meter. The unknown resistance Rx is connected across the terminals A and B. A switch ‘S’ is used for disconnecting the battery when the Ohmmeter is not in use. When the unknown resistor Rx = 0, i.e. the terminals A and B are shorted, the meter current Im = 0 (no current). When Rx = , i.e. the terminals A and B are open, the meter current will be maximum (full scale deflection current). The range of shunt-type ohmmeter is normally used to measure low-value resistors. As shown in Fig. 23.24, when Rx = , the full-scale meter current becomes E Ifsd = ________ R a + Rm Solving for the current limiting resistor, Ra, we get E Ra = ___ – Rm Ifsd

(23.8)

When any value of resistor Rx is connected across the terminals A and B, the meter current decreases and it is given by Rx E Im = ____________________ ________ Ra + [RmRx /(Rm + Rx)] Rm + Rx

{

That is,

}

ERx Im = ___________________ RaRm + Rx (Ra + Rm)

(23.9)

The ratio of meter current to the full-scale deflection current is given by Im Rx(Ra + Rm) S = ___ = __________________ Ifsd Ra(Rm + Rx) + RmRx That is,

Rx(Ra + Rm) S = __________________ Rx(Ra + Rm) + RaRm

(23.10)

Here, RaRm ________ = Rp Ra + Rm Therefore,

Rx S = _______ R x + Rp

(23.11)

When Im = 0.5Ifsd, the meter current Im given in Eq. (23.9) reduces to ERh 0.5Ifsd = ___________________ RaRm + Rh (Ra + Rm) where Rh = resistance required for half-scale deflection. For determining the relative scale value for the given value of Ra, the half-scale reading may be found by diving equation and solving for Rh, RaRm Rh = ________ Ra + Rm

(23.12)

An instrument used to measure voltage, current and resistance is known as a Multimeter. There are two types of multimeters, analog and digital. Of these two types, the digital multimeter is commonly used in laboratory and workshop because of its high input resistance, greater accuracy, better resolution and easy readability. The DMM combines in one case the instruments for the measurements of voltage, current and resistance. The block diagram of a digital The digital voltmeter (DVM) for the measurement of voltage is discussed in Section 23.6. The same principle is used in DMM for the measurement of voltage. current. The current to be measured is passed through one of the sensing resistors and the DMM digitizes the voltage developed across the resistor. For example, referring to Fig. 23.26, the output voltage of a current to voltage converter is given by Vo = – IsRf where Rf is the known resistance. The output voltage Vo which is proportional to the unknown source current Is is applied to DVM section of DMM and the value of current Is is displayed. The DMM measures the resistance by applying a known current from an internal current source to the unknown resistance and then digitizing the resulting voltage developed. For example, referring to Fig. 23.27, the output voltage of a scale changer is given by

– Rf Vo = ____ Vi Ri where Vi and Ri are known parameters. The output voltage which is proportional to the unknown resistance Rf is applied to DVM section of DMM and the value of unknown resistance Rf is displayed. Most of the DMMs are similar in terms of voltage, current and resistance measurements. They differ only in terms of accuracy, selection of ranges and a.c. bandwidth. There are some DMMs having built-in capacitance measuring circuitry also. Most DMMs have protection from input overload by using circuit breakers, fuses, auto ranging and diode clipper circuit. The display used can be either Liquid Crystal Display (LCD) or Light Emitting Diode (LED) display. A DMM is typically used for measurement of voltage, current and resistance. It is also used to test whether the diode, transistor or SCR is good or faulty and to check circuit continuity. For example, to check a diode, the resistance is measured in one direction and then in other direction. In the forward-biased direction, a low resistance is indicated and in the reverse-biased direction, a high resistance is indicated.

For the measurement of resistance, capacitance and inductance, a simple bridge can be used with four arms. The unknown impedance R, L or C is connected in one of the arm. The other arms are connected with the proper impedances. For example, Wheatstone bridge for resistance measurement, Maxwell’s inductance bridge for the measurement of inductance, and Schering’s bridge for the measurement of capacitance are dealt in the following sections.

The basic d.c. bridge is used for accurate measurement of resistance called Wheatstone’s bridge. The bridge circuit merely compares the value of an unknown component with that of an accurately known component (a standard). So its accuracy of measurement is very high. The classification of resistance from the point of view of measurement, is as follows. (i) Low resistance—resistances of the order of 1 ohm (R < 1 W). (ii) Medium resistance—resistances from 1 W upwards to about 100 kW (1 W < R < 0.1 MW) (iii) High resistance—resistances of the order of 100 kW and upwards (R > 100 kW). This classification is not rigid but forms a basis for techniques. medium resistance is the “Wheatstone bridge” and is popular for laboratory use. It has four resistive arms together with a source of emf (a battery) and a null detector, usually a galvanometer G, or other current sensitive meter, with a zero center scale, as shown in Fig. 23.28.

The current through the galvanometer depends on the potential difference between points C and D. When there is no current through the meter, the galvanometer pointer rests at zero, i.e. middle of the scale. Current in one direction causes the pointer to deflect in one side and current in the opposite direction to the other side. For bridge balance, currents divided into the two arms at point A, i.e. I1 and I2 are such that potentials at points C and D are equal, i.e. potential difference across the galvanometer is zero and hence zero or no current flows through galvanometer. At balanced condition, E I1 = I3 = ______ P+Q E I2 = I4 = ______ R+S

and

(23.13) (23.14)

where E = emf of the battery. Combining Eqs (23.13) and (23.14), and simplifying, we get I1P = I2R E◊P E◊R ______ = ______ P+Q R+S P R ______ = ______ P+Q R+S

(23.15)

(23.16)

From Eq. (23.16), we obtain the bridge balance equation, P(R + S) = R(P + Q) PR + PS = PR + RQ PS = RQ If three of the resistances are known, the fourth may be determined. PS R = ___ Q where S is the standard arm, and P and Q are ratio arms.

Measurement of inductance, capacitance, storage factor, i.e. Q, and loss factor or dissipation factor, i.e. D, are conveniently and accurately made by employing a.c. bridge networks. The a.c. bridge is a natural outgrowth of d.c. Wheatstone bridge, except that the bridge arms are impedances, the bridge is excited by an a.c. source and the galvanometer is replaced by an a.c. detector. The commonly used detectors are head phones, vibration galvanometers, tunable amplifier detector or a.c. ammeter. The most sensitive detector for the frequencies from 250 Hz to 3 or 4 kHz is the head phone. Figure 23.29 shows the basic a.c. bridge. The four arms of the bridge are impedances Z1, Z2, Z3 and Z4. The condition for balance of bridge require that there should be no current through the detector. This will be the case when the voltage drop from A to B equals the voltage drop from A to D, both in magnitude and phase.

(23.17)

E1 = E2 I1Z1 = I2Z2

(23.18)

E I1 = I3 = _______ Z1 + Z3

(23.19)

E I2 = I4 = _______ Z2 + Z4

(23.20)

Using Eqs (23.19) and (23.20), Z1 Z2 _______ = _______ Z1 +Z3 Z2 + Z4 Z1(Z2 + Z4) = Z2(Z1 + Z3) Z1Z4 = Z2Z3

(23.21)

Equation (23.21) represents the basic equations for balance of an a.c. bridge. This equation states that product of impedances of opposite arms must be equal. Since the impedances consist of real resistive and imaginary reactive part, both the magnitude and phase angles of the impedances must be taken into account. If impedances are represented in polar form, the equation of bridge balance can be written as Z1 q1 Z4 q4 = Z2 q2 Z3 q3 (23.22) Z1Z4 (q1 + q4) = Z2 Z3 (q2 + q3)

(23.23)

Equation (23.23) shows that two conditions must be met simultaneously when balancing an a.c. bridge. The first condition is that the magnitudes of the impedances satisfy the relationship Z1Z4 = Z2Z3, i.e. the product of the magnitudes of the opposite arms must be equal. The second condition required that the phase angles of the impedances satisfy the relationship (q1 + q4) = (q2 + q3) In other words, the sum of the phase angles of the opposite arms must be equal.

From the measurement point of view, inductance is broadly classified as low Q coil, medium Q coil and high Q coil based on quality factor of the inductance. Q = wL/R (i) Low Q coil, (Q < 1) (ii) Medium Q coil (1 < Q < 10) (iii) High Q coil (Q > 10) For the measurement of inductance, the idea about its Q value is necessary because bridge’s sensitivity is maximum for certain values of Q. For example, Maxwell’s inductance–capacitance bridge is suitable for the measurement of medium Q coils. Figure 23.30 shows Maxwell’s inductance-capacitance bridge.

The bridge consists of Z1 = R1 + j L1, which is the unknown arm where R1 is the internal resistance of the coil and L1 is the self inductance of the coil. Z3 and Z2 are pure resistances. Z4 is a parallel combination of R4 and C4. Z1Z4 = Z2 Z3

At balance,

(

(23.24)

)

R4 (R1 + j L1) ____________ = R2R3 1 + j C4R4 (R1 + j L1) R4 = R2R3 (1 + j C4R4) Separating real and imaginary terms,

and

R2 R3 R1 = _____ R4

(23.25)

L1 = R2R3C4

(23.26)

The product R2R3 appears on both the equations. So, it is enough to keep R2 and R3 as fixed value resistors. To balance the bridge, R4 and C4 are to be changed and hence, R4 and C4 are to be selected as variable resistance and variable capacitance, respectively. Equation (23.25) is the d.c. balance equation and Eq. (23.26) is the a.c. balance equation and for a.c. bridge balance, both the balances should be obtained simultaneously. L1 The quality factor Q of the coil can be calculated as Q = ____, where is the angular frequency at which R1 bridge balance is obtained.

Referring to Schering’s bridge of Fig. 23.31, Z1 is the unknown capacitance C1 with internal resistance r1. The ratio arms are Z3 and Z2, 1 where Z3 = R3 and _____. Z4 is the standard arm consists of capacitance C4 j C2 in parallel with R4 which are variable. At balance,

Z1Z4 = Z2Z3

1 1 ___________ = _____ R ( r + _____ j C ) (1 + j C R ) j C R4

1

1

4

4

2

3

Separating real and imaginary parts and equating them, R3 R3R4C4 R4 r1 R4 + _____ = _____ + _______ j C1 j C2 C2 R3 R4 C4 r1R4 = ________ C2 R3 C4 r1 = _____ C2

(23.27)

(23.28)

(23.29)

and

R4 C1 = ___ C2 R3

(23.30)

Dissipation factor, D1 = tan q = w C1r1, where w is the angular frequency at which balance is obtained.

An instrument to measure the electrical property Q of an inductor and a capacitor is the Q meter. In the case of inductor, a small internal resistance present is due to losses in the inductors core material and the variation of conductors resistance due to Skin effect. Mathematically, Q = XL/R = 2 p f L/R. Q indicates the merit or ability of a coil to develop induced voltages under the influence of magnetic fields. Capacitors also have a value of Q equal to the ratio of the capacitive reactance to the effective resistance of the capacitor. For the capacitor, Xc 1 Q = ___ = ______ R 2pfCR

(23.31)

This resistance may be in the leads, due to Skin effect and due to the internal losses of the capacitor, R i.e. dielectric leak. In the other way “dissipation factor,” D of a capacitor is, D = ___ = 2p fCR, and XC 1 therefore, D = __. The dissipation factor gives about the quality of a capacitor, i.e. how close the phase Q angle of the capacitor is to the ideal value of 90 degrees. The measurement of Q of a coil or a capacitor uses the characteristics of a series resonant circuit. At resonance voltage across the coil equals the drop across the capacitor. XC = XL XL XC Q = ___ = ___ R R But the type of component and its size determine the method of connecting the component under test to the test terminal of the Q meter. Figure 23.32 shows the basic Q meter. Most coils can be connected directly across the test terminals. The circuit is resonated by adjusting the resonating capacitor.

E EC = IXC = IXL, where I = __ R XL EC Q = ___ = ___ (23.32) R E A wide range oscillator with a frequency range from 50 kHz to 50 MHz delivers current to a low value shunt resistance RSH, typically of the order of 0.02 W. It introduces no resistance into the oscillator circuit and therefore, represents a voltage source of magnitude E and with a negligible internal resistance. Therefore,

To make a measurement, voltage across the variable capacitor at resonance, EC is measured. The ratio EC/E gives the value of Q directly. Figure 23.33 shows the series connection for the measurement of low impedance components such as low value of resistors, small coils and large capacitors.

The unknown component under test is placed in series with a stable work coil. A shorting strap is connected across the unknown component. First the unknown component is shorted and resonated, establishing a reference condition. The values of the tuning capacitance (C1) and the corresponding Q (Q1) of the circuit are noted. In the second measurement, the shorting strap is removed and the circuit is retuned to resonance again. New values of tuning capacitance (C2) and Q (Q2) of the circuit is noted. For the resonance condition, XC1 = XL. 1 wL Q1 = ___ = ______ wC1R R For the second measurement, the unknown reactance, XS can be expressed in terms of C2 and the inductance L of the work coil. 1 1 XS = XC2 – XL or XS = ____ – ____ wC2 wC1 C1 – C2 Therefore, XS = _______ wC1 C2

If the unknown component is inductive, C1 > C2 and if it is capacitive, C1 < C2. The resistive component of the unknown impedance is found using the Q value. XC XC R1 = ____1 and R2 = ____2 Q1 Q2 1 1 RS = R2 – R1 = ______ – ______ wC2Q2 wC1Q1 Therefore,

C1Q1 – C2 Q2 RS = ____________ wC1 C2 Q1 Q2

If the unknown component is a small inductor, C1 – C2 LS = ________ w2 C1 C2 Thus, (C1 – C2) (Q1 Q2) QS = _______________ C1 Q1 – C2 Q2 If the unknown is a capacitor, C1 C2 CS = _______ C2 – C1

(23.33)

(23.34)

(23.35)

(23.36)

If the unknown component is purely resistive, the value of the tuning capacitance will be same for both the conditions, i.e. C1 = C2. The value of Q will not be same. The expression for resistance is now expressed as Q1 – Q2 RS = __________ wC1 Q1 Q2 capacitor are measured by this method. Figure 23.34 shows the parallel connection. Unknown component under test is connected in parallel with the work coil. Before the unknown is connected, the circuit is resonated with the work coil, to establish the resonance condition (Q1 and C1). Then the unknown is included in the circuit and the circuit is reresonated. A new value of tuning capacitance (C2) and Q (Q2) are noted.

At the initial resonant condition, wL 1 1 wL = ____ and Q1 = ___ = ______ R wC1 R wC1 When the second measurement is made, at resonance the reactance of the working coil (XL) equals the parallel reactances of the tuning capacitor (XC2) and the unknown (Xp). Hence,

(XC2) (Xp) XL = _________ XC2 + Xp

which gives

1 Xp = __________ w (C1 – C2)

If the unknown connected is inductive, Xp = wLp and hence, 1 Lp = ___________ w2 (C1 – C2)

(23.37)

If the unknown impedance is capacitive, 1 Xp = ____ wCp and hence,

Cp = C1 – C2

(23.38)

The total resistance in a parallel resonant circuit at resonance is equal to the product of the circuit Q and the reactance of the coil. Q2 RT = Q2XC1 = ____ (23.39) wC1 The resistance of the unknown impedance is easily found by calculating the conductances in the circuit. Let

GT = total conductance of the resonant circuit GP = conductance of the unknown impedance GL = conductance of the working coil.

Then, GT = GP + GL or GP = GT – GL wC1 1 GT = ___ = ____ RT Q2 wC1 1 R ___ = ____ – _________ Rp Q2 R2 + w2L2

wC1 1 = ____ – ____2 Q2 RQ

(23.40)

1

Therefore,

wC1 wC1 1 ___ = ____ – ____ Rp Q2 Q1 Q1 Q2 Rp = _____________ w C1(Q1 – Q2)

(23.41)

(C1 – C2) (Q1 Q2) Qp = _______________ C1 (Q1 – Q2)

(23.42)

Equation (23.42) gives the value of Q.

A digital instrument which is used to measure the frequency of any periodic waveform is known as Frequency meter (Frequency counter). It is one of the most important measuring instruments. It has high sensitivity, resolution, accuracy and stability. It can perform a wide range of functions, such as frequency measurement, period measurement, ratio of frequencies measurement, scaling, time interval measurement etc. The block diagram of a basic frequency meter is shown in Fig. 23.35. The frequency measurement is performed by totaling the number of input cycles for a known period of time so that the resulting total count is proportional to the unknown input frequency. The time reference (gate ENABLE signal having a known period ‘t’) is obtained from a precision, high stability quartz crystal oscillator along with a wave shaper (Schmitt trigger) and a set of dividers.

The input signal is applied to a Schmitt trigger circuit so that it will provide uniform pulses. This pulse train is given to the counter through an AND gate and this gate is controlled by the time reference. The number of pulses totaled in the counter for the selected time period ‘t’ represents the input signal frequency. Finally, it is displayed on the numeric display device at the output of the counter. The counted frequency is displayed on the display devices for a finite time period until a new sample is taken. The display time of the frequency measurement is determined by the sample rate control. The resetting of the counter and the next measurement cycle are also initiated by using the sample rate control. For example, if the time reference is one second and the input signal is a 750 Hz square wave, at the end of 1s, the counter will have counted up to 750 which is exactly the frequency of the input signal.

With some modifications, the frequency counter can be converted into a Time counter (Time meter). Time counter is an instrument to measure time. The block diagram of a time meter is shown in Fig. 23.36. It shows the construction of an instrument which is used to measure the period of any periodic waveform.

The unknown signal is passed through an amplifier to produce a periodic waveform that is compatible with TTL circuits and is then applied to a J-K flip-flop. The output of this flip-flop is used as the Enable gate signal since it is high for a time t that is exactly equal to the time period of the unknown input voltage. The oscillator and divider provide a series of pulses that are passed through the count gate and serve as the clock for the counter. The contents of the counter and display unit will then be proportional to the time period of the unknown input signal. For example, let the unknown input sinusoidal signal be at a frequency ‘f ’ of 10 kHz and the clock pulses from the divider are 0.1 ms in width at the rate of one pulse per ms. The J-K flip-flop produces an output pulse train with ON time ‘t’ which is equal to 1/f. Therefore, t = 1/10 × 103 = 100 ms. Hence the counter and display will read 100. This means 100 ms, since 100 of these 0.1 ms pulses will pass through the count gate during 100 ms when ENABLE gate signal is high.

Energy is the total power delivered or consumed over a time interval by an electrical system. Energy = power × time Electrical energy is expressed as t

W = Ú VI dt 0

V is expressed in volts, I is expressed in amperes, and t is in seconds. Unit for Energy is Joules or Watt second. If the unit of time is taken as hour, energy is then expressed in Watt hours. For larger units, energy may be expressed in kW-hours. In d.c. and a.c. circuits, for the measurement of energy, motor meters are used. In motor meters, a moving system revolves continuously. The speed of rotation is proportional to power consumed or delivered. Thus, the total number of revolutions made by the moving system in a given interval of time is proportional to the energy supplied or consumed. In this connection, motor constant is defined as the number of revolutions made per kilo Watt hour (kWh). The value of meter constant is always marked on the meter. Induction type of energy meters are usually used for measurement of energy in domestic and industrial a.c. circuits. This type of meters are inexpensive and accurate, and retain the accuracy over a wide range of loads and temperature conditions. The driving system of a meter consists of two electromagnets. The core of these electromagnets is made up of silicon steel laminations. The coil of one of the electromagnets is excited by the load current. This coil is called as the current coil. The coil of second electromagnet is connected across the supply and, therefore, carries a current proportional to the supply voltage. This coil is called as the pressure coil. Consequently, the two electromagnets are known as series and shunt magnets, respectively. Copper shading bands are provided on the central limb. The position of these bands is adjustable. The function of these bands is to bring the flux produced by the shunt magnet exactly in quadrature with the applied voltage. This consists of an aluminium disc mounted on a light alloy shaft. This disc is positioned in the air gap between series and shunt magnets. The upper bearing of the rotor (moving system) is a steel pin located in a hole in the bearing gap fixed to the top of the shaft. The rotor runs on a hardened steel pivot, screwed to the foot of the shaft. The pivot is supported by a jewel bearing. A pinion engages the shaft with the counting or registering mechanism. A unique design for the suspension of the disc is used in the floating-shaft energy meter. Here, the rotating shaft has a small magnet at each end, where the upper magnet of the shaft is attracted to a magnet in the upper bearing and the lower magnet of the shaft is attracted to a magnet in the lower bearing. The moving system thus floats without touching either bearing surface, and the only contact with the movement is that of the gear connecting the shaft with the gear of the train, thus the friction is drastically reduced. A permanent magnet positioned near the edge of the aluminium disc forms the braking system. The aluminium disc moves in the field of this magnet and provides a braking torque.

The position of the permanent magnet is adjustable and therefore braking torque can be adjusted by shifting the radial position of the permanent magnet. The function of a registering or counting mechanism is to record continuously a number which is proportional to the revolutions made by the moving system. By a suitable system, a train of reduction gears the pinion on the rotor shaft drives a series of five or six pointers. These rotate on round dials which are marked with ten equal divisions.

Power taken by a load from a d.c. supply is given as P = V.I

W

where V is in volts and I is in amperes. An ammeter and a voltmeter are needed to measure current through the load and voltage drop across the load, respectively. The two possible connections are as shown in Fig. 23.37. Referring to Fig. 23.37(a), Va is the voltage drop across the ammeter. Let Ra be the internal resistance of ammeter. Ammeter read the current through the load. VL = V – Va Va = IL Ra Power consumed by the load = ILVL. P = IL (V – Va) = IL V – IL Va = power indicated by instruments – power loss in ammeter. In Fig. 23.37(b), voltmeter is connected across the load and indicates the voltage drop across the load VL, but ammeter reads (IV + IL). Therefore, the ammeter not only indicates the current through load but also the current through the voltmeter. Current through the voltmeter = IV = V/RV, where RV = resistance of voltmeter. Power consumed by load = IL VL = VL (I – IV) = VI – V2/RV = power indicated by instrument – power loss in voltmeter Thus, in both cases the power indicated by the instruments is equal to the power consumed by the load and the power consumed by the instrument nearest to the load terminals. In order to obtain the true power, corrections must be applied for power loss in instruments. Under normal conditions, power loss in instruments is quite small as compared with the load power and therefore, the error introduced on this account is small. For a permanently wired installation where power measurements are required, it is advantageous to install a watt meter instead of a voltmeter and an ammeter.

Watt meter gives direct indication of power. In alternating current, instantaneous power varies continuously as the current and voltage go through a cycle. Average power over a cycle is measured in steady state condition. Average power over a time interval measures the transfer of energy to the load. Vm Im Average power = ______ cos 2 where Vm= maximum value of voltage, Im = maximum value of current, and cos

= power factor of the load.

There are two coils connected in different circuits for the measurement of power. Fixed coil or field coil is connected in series with the load and so carry the current in the circuit. The fixed coil, therefore, form the current coil of the watt meter. The moving coil is connected across the voltage and, therefore, carries a current proportional to the voltage and hence known as pressure coil or voltage coil of the watt meter. A high non-inductive resistance is connected in series with a moving coil to limit the current to a small value. Figure 23.38 shows the circuit of a watt meter. The instantaneous torque of an electrodynamometer instrument is given by dM Ti = ic ip ____ d where ic = instantaneous value of current in the fixed coils in amperes, ip = instantaneous value of current in the moving coil in amperes, and M = mutual inductance between fixed and moving coils in henrys. By the principle of conservation of energy,

(a) Dynamometer watt meter

Total electrical input energy = change in energy stored – mechanical energy

Current coil

ip Resistance R

Mechanical energy = icip dM Work done = Ti d , where d is the change in deflection Ti d Therefore,

Supply

Load

Pressure coil (P.C.)

= icip dM

Ti = icip dM/d

Let V and I be the rms values of voltage and current being measured.

ic

(b)

__

Therefore, instantaneous value of voltage across the pressure coil circuit, v = ÷2 V sin w t. Current in __

v ÷2 V sin w t the pressure coil ip = __ = ___________ R RL

__

ip = ÷2 I sin w t If the current in the current coil lags the voltage in phase by an angle F, instantaneous value of current in the coil is __

ic = ÷2 I sin (w t – F) __ __ dM Ti = (÷2 I sin w t) ÷2 I sin (w t – f) ____ dq

Average deflecting torque, T

1 Td = __ Ú Ti d (wt) T0 Integrating the equation, we get Td = Ip I cos dM/dq = VI/Rp cos dM/dq Controlling torque exerted by spring is Tc = kq, where k = spring constant and q = final steady deflection. Since the moving system of an instrument cannot follow the rapid variations in torque, it will take up a position at which the average deflection torque to equal to the restoring torque of the spring. Therefore, at balance position, kq = Ip I cos F dM/dq IpI dM VI cos F dM q = ___ cos F ____ = ____________ K dq Rp k ◊ dq dM = k1 P ____ dq 1 where k1 = ____ and P = power being measured. Rp k

A spectrum analyser is an instrument designed to graphically present amplitude as a function of frequency in a portion of the spectrum. These devices generate an x-y oscilloscope display, with y-axis representing signal strength (usually logarithmic, i.e. in decibels), but with x representing frequency as shown in Fig. 23.39. Spectrum analysis may be defined as the study of energy distribution across the frequency spectrum for a given electrical signal.

The Fourier decomposition of the input waveform or the response of the broad range high performance receiver through its frequency range can be visualised. This ability can be very handy when analysing modulated signals, looking for intermodulation products or distortion, analysing noise and drift, trying to make accurate frequency measurements on weak signals in the presence of stronger signals, and making a host of other measurements. Spectrum analysers come in two basic varieties: Swept tuned and Real time swept tuned are the most common methods, and they work as shown in Fig. 23.40. It consists of a super-heterodyne receiver with a Local Oscillator (LO) that can be swept by an internally generated ramp waveform. As the LO is swept through its range of frequencies, different input frequencies are successively mixed to pass through the IF amplifier and filter. For example, in a spectrum analyser with an IF of 200 MHz and an LO that can sweep from 200 to 300 MHz, when the LO is at 210 MHz, input signals at 10 MHz (+/– the IF filter bandwidth) pass through to the detector and produce vertical deflection on the scope. Image frequency at 410 MHz would also pass through but it is rejected by the input low pass filter itself. At any given time, input frequencies 200 MHz lower than the LO are detected. Real spectrum analysers allow lots of flexibility as to sweep range, center frequency, filter bandwidth, display scales etc. The input frequency ranges from Hertz to Giga Hertz with selectable bandwidths

~

ranging from Hertz to Mega Hertz. In addition, sophisticated spectrum analysers have features such as absolute amplitude calibration, storage of spectra to prevent flicker during sweeping, additional storage for comparison and normalisation, and display of digital information on the screen. Some spectrum analysers help in analysing phase versus frequency, to generate frequency markers, program the operation via IEEE-488 bus, include tracking oscillators (for increased dynamic range), make precise frequency measurements of features in the spectrum, generate tracking noise voltages for system stimulus, and even do signal averaging. Since one frequency at a time is looked, only a small portion of the input signal is analysed. To overcome this disadvantage, a set of narrow filters are used to look at a wide range of frequencies simultaneously. Based on Cooley–Tukey fast Fourier Transform, analog input signal is converted into digital numbers and a special purpose computer generates digital frequency spectrum. Since this method looks all frequencies simultaneously, it can also be used for analysis of transients. Another technique for real time spectrum analysis is the Bragg cell, in which the IF signal is used to generate acoustic waves in a transparent crystal. These deformations diffract a laser beam, generate a real time display of the frequency spectrum as light intensity versus position. An array of photo detectors completes the analyser output. A typical unit has 2 GHz instantaneous bandwidth, analysed into 16,000 channels of 125 kHz bandwidth each. The fast Fourier transform applied to digitize the data from an experiment provides a very powerful method of signal analysis, particularly the recognition of weak signals of well defined periodicity buried in interfering signals or noise. For instance, FFT is used to search for pulsars, perform audio analysis and resolution of astronomical images has been enhanced.

An electronic system comprises many nonlinear devices such as A/D and D/A converters, pulse modulators/demodulators and active devices. They are considered to be linear within a small region of operation. But in practice, due to the non-linearities, the output signal of the system is no longer proportional to the input signal. They result in the change of signal waveform or nonlinear amplification of the signals, leading to waveform distortion or harmonic distortion. The output waveform now consists of fundamental and higher harmonics. A measure of the distortion represented by a particular harmonic is the ratio of the amplitude of the harmonic to that of fundamental. E3 En E2 D2 = ___, D3 = ___, º, Dn = ___ E1 E1 E1 The Total Harmonic Distortion (THD) or distortion factor is defined as the ratio of the rms value of all the harmonics to the rms value of the fundamental. ________________

THD = ÷D22 + D23 + º + D2n

________________

÷E2 + E 3 + º + En = _________________ 2

2

2

E1

_____________

S (harmonics)2 ÷ _______________ = fundamental But in practical measurements, the working equation expressed THD as the ratio of the rms value of all the harmonics to the rms value of the total signal which includes fundamental and harmonics.

_____________

________________

÷E2 + E3 + º + En ÷S(harmonics)2 ____________________________ = _________________ THD = _____________________________ Et ÷(fundamental)2 + S(harmonics)2 2

2

2

____________________

where

Et = ÷E21 + E22 + E23 + º + E2n

Figure 23.41 shows the block diagram of a practical distortion meter. When the selector switch is put to position 1, the tunable band pass filter allows the total signal Et. The meter M shows the rms value of the total signal consisting of fundamental and harmonics. The amplifier circuit is adjusted so that the meter reads the maximum, i.e. 100%.

Then the selector switch is changed to position 2. Now the signal passes through a tunable rejection filter which is highly selective notch filter circuit designed to reject the fundamental frequency. Therefore, the attenuation at fundamental frequency component is infinite. As the output of the amplifier now contains only the higher harmonics, meter M indicates the percentage of distortion directly. ________________

2 2 2 ÷E2 + E3 + º + En Percentage of distortion = _________________ × 100 Et

The distortion meter is useful in analysing the waveform distortion that occurs due to the presence of harmonics and hence, this is generally referred to as harmonic distortion analyser or simply distortion analyser.

A digital circuit is different from analog circuits. The term digital is derived from the way in which circuits perform operations by counting digits. Applications of digital electronics are not only confined to computer system but are applied in many diverse areas like telephony, data processing, radar navigation, military systems, medical instruments and consumer products. Digital technology has progressed from vacuum-tube circuits to integrated circuits and microprocessors. Digital circuits involve systems in which there are only two possible states. These states are typically represented by voltage levels. Other circuit conditions, such as current levels, open or closed switches, and ON or OFF lamps, can also represent the two states. In digital systems, the two states are used to represent numbers, symbols, alphabetic characters and other types of information.

In our daily life, decimal number system (0, 1, 2, º, 9) is commonly used even though there are many other number systems like binary, octal, hexadecimal, etc. For understanding the digital circuits and systems, students must be familiar with these number systems also. The following sections are dedicated to binary, octal and hexadecimal number systems.

The binary number system is simple because it is composed of only two digits, i.e. 0 and 1. Just as the decimal system, with its ten-digits, is a base-ten system, the binary system with its two digits is a base-two system. The position of 1 or 0 in a binary number indicates its “weight” within the number. The weight of each successively higher position (to the left) in a binary number is an increasing power of two. For example, in decimal system, 13910 = 1 × 102 + 3 × 101 + 9 × 100 hundreds

tens

units Positional weights

Similarly, the binary numbers are also represented by positional weights. For example, 13910 = 100010112 = 1 × 27 + 0 × 26 + 0 × 25 + 0 × 24 + 1 × 23 + 0 × 22 + 1 × 21 + 1 × 20 = 128 + 0 + 0 + 0 + 8 + 0 + 2 + 1 = 139. In the digital system, each of the binary digits is called a bit and a group of bits having a significance is called a byte or word. The highest decimal number that can be represented by an n bits binary number is 2n – 1. Thus, with a 8-bit binary number the maximum decimal number that can be represented is 28 – 1 = 255.

One easier method of converting a decimal number into binary number is to divide progressively the decimal number by 2 until quotient of zero is obtained. Writing the remainders after each division in the reverse order, the binary number is obtained. This method is popularly known as double-dabble method. The procedure for converting the decimal to binary is explained below. Consider the decimal number 52; its binary equivalent can be obtained as follows. 52 divided by 2 = quotient 26 with a remainder of 0 26 divided by 2 = quotient 13 with a remainder of 0 13 divided by 2 = quotient 6 with a remainder of 1 6 divided by 2 = quotient 3 with a remainder of 0 3 divided by 2 = quotient 1 with a remainder of 1 1 divided by 2 = quotient 0 with a remainder of 1 Reading the remainders from bottom to top gives the binary equivalent. Thus, 5210 = 1101002. If the decimal number is a fraction, its binary equivalent is obtained by multiplying the number continuously by 2, recording each time a carry in the integer position. The carries in the forward order gives the required binary number. For example, the decimal number 0.62510 can be expressed in binary as follows. 0.625 multiplied by 2 = 1.250 : carry = 1 0.250 × 2

= 0.50 : carry = 0

0.500 × 2

= 1.00 : carry = 1

0.000× 2 = 0.00 As the product is zero, no further multiplication by two is possible. The binary equivalent is obtained by reading the carry terms from top to bottom. Thus, 0.62510 is 0.1012. The binary equivalent of a decimal real number, which includes both integer and fractional parts, can be found using the same techniques, i.e. find the binary equivalent of the integer part and fractional part using respective methods and the combined number will give the binary equivalent. For example, 52.62510 = 110100.1012. The conversion of a binary number into its decimal equivalent can also be carried out. In a binary number, digits from extreme right represent coefficient of the ascending powers of two, the starting power being zero. For example,

1 0 1 1 1 0

0

0¥2 =0 1

1¥2 =2 2

1¥2 =4 3

1¥2 =8 4

0¥2 =0 5

1 ¥ 2 = 32 46

Therefore, (101110)2 can be written as (46)10. Conversion of fractions is also carried out in a similar manner. For example, the conversion of 0.1101 is illustrated below. 0.1 1 0 1

–4

1 ¥ 2 = 0.0625 –3

0 ¥ 2 = 0.0000 –2

1 ¥ 2 = 0.2500 –1

1 ¥ 2 = 0.5000 0.8125

Thus, 0.11012 is equivalent to 0.812510.

The octal number system uses the digits 0, 1, 2, 3, 4, 5, 6 and 7. The base or radix of this system is eight. Each significant position in an octal number has a positional weight. The least significant position has a weight of 80, i.e. 1, and the higher significant positions are, respectively, given weightage as the ascending powers of eight, i.e. 81, 82, 83, etc. The octal equivalent of a decimal number can be obtained by dividing the decimal number by 8 repeatedly, until a quotient of 0 is obtained. The procedure is exactly same as the double-dabble method explained earlier. The conversion from decimal to octal number is explained hereunder.

Convert 1210 to an octal number.

Solution

The procedure is as follows. 12 divided by 8 = quotient 1 with a remainder of 4 1 divided by 8 = quotient 0 with a remainder of 1

Reading the remainders from bottom to top, the decimal number 1210 is equivalent to octal 148. The conversion from octal to decimal number can be carried out by multiplying each significant digit of the octal number by the respective weights and adding the products. The following example illustrates the conversion from octal to decimal.

Convert the following octal numbers to decimals. (i) 4448 (ii) 2378 (iii) 1208

Solution (i) 4448 = 4 × 82 + 4 × 81 + 4 × 80 = 4 × 64 + 4 × 8 + 4 × 1 = 256 + 32 + 4 = 29210 (ii) 2378 = 2 × 82 + 3 × 81 + 7 × 80 = 2 × 64 + 3 × 8 + 7 × 1 = 128 + 24 + 7 = 15910 (iii) 1208 = 1 × 82 + 2 × 81 + 0 × 80 = 1 × 64 + 2 × 8 + 0 × 1 = 64 + 16 + 0 = 8010

Conversion from octal to binary and vice-versa can be easily carried out. For obtaining the binary equivalent of an octal number, just replace each significant digit in the given number by its 3-bit binary equivalent. For example, 2768 =

2

7

6

= 010 111 110 Thus, 2768 = 010 111 1102. The reverse procedure is used for converting binary to octal, i.e. starting from the least significant bit, replace each group of 3 bits by their decimal equivalents. For example, 110110101012 = 11 011 010 101 = Thus,

3

3

2

5

110110101012 = 33258.

Hexadecimal number system has a radix of 16 and uses 16 symbols, namely, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E and F. The symbols A, B, C, D, E, and F represent the decimals 10, 11, 12, 13, 14 and 15, respectively. Each significant position in hexadecimal number has a positional weight. The least significant position has a weight of 160, i.e. 1, and the higher significant positions are, respectively, given weightage as the ascending powers of sixteen, i.e. 161, 162, 163, etc. The hexadecimal equivalent of a decimal number can be obtained by dividing the decimal number by 16 repeatedly, until a quotient of 0 is obtained. The following example illustrates how the hexadecimal equivalent of a given decimal can be obtained.

Convert 11210 and 25310 to hexadecimal numbers.

Solution The procedure is as follows, (i) 112 divided by 16 = quotient 7 with a remainder of 0 7 divided by 16 = quotient 0 with a remainder of 7 Reading the remainders from bottom to top, the decimal number 11210 is equivalent to hex 7016. The hexadecimal 7016 can also be represented as 70 H. (ii) 253 divided by 16 = quotient 15 with a remainder of 13, i.e D 15 divided by 16 = quotient 0 with a remainder of 15, i.e. F Reading the remainders from bottom to top, the decimal number 25310 is equivalent to hex FD16. The conversion from hex to decimal number can be carried out by multiplying each significant digit of the hexadecimal number by the respective weights and adding the products. The following example illustrates the conversion from hex to decimal.

Convert the following hexadecimal numbers to decimals. (i) 4AB H (ii) 23F H

Solution (i) 4AB16 = 4 ¥ 162 + A ¥ 161 + B ¥ 160 = 4 ¥ 162 + 10 ¥ 161 + 11 ¥ 160 = 4 ¥ 256 + 10 ¥ 16 + 11 ¥ 1 = 1024 + 160 + 11 = 119510 (ii) 23F16 = 2 ¥ 162 + 3 ¥ 161 + F ¥ 160 = 2 ¥ 256 + 3 ¥ 16 + 15 ¥ 1 = 512 + 48 + 15 = 57510 Conversion from hex to binary and vice-versa can be easily carried out. For obtaining the binary equivalent of a hexadecimal number, replace each significant digit in the given number by its 4-bit binary equivalent. For example, 2A616 =

2

6

A

= 0010 1010 0110 Thus, 2A616 = 0010 1010 01102. The reverse procedure is used for converting binary to hex, i.e. starting from the least significant bit, replace each group of 4 bits by their decimal equivalents. For example, 110110101012 = 110 1101 0101 = 6

D

5

Thus,

110110101012 = 6D516

Conversion between hexadecimal and octal numbers is sometimes required. To convert a hexadecimal number to octal, the following steps can be used. (i) Convert the given hexadecimal number to equivalent binary. (ii) Starting from the LSB, form groups of 3 bits. (iii) Write the equivalent octal number for each group of 3 bits. For example, 2416 = 0010 01002 = 00 100 1002 = 0448 Thus, 24 in hexadecimal is equivalent to 44 in octal number system. To convert an octal number to hexadecimal the steps are as follows. (i) Convert the given octal number to equivalent binary. (ii) Starting from the LSB, form groups of 4 bits. (iii) Write the equivalent hexadecimal number for each group of 4 bits. For example, 248 = 010 1002 = 01 01002 = 1416 Thus, 24 in octal is equivalent to 14 in hexadecimal number system.

The arithmetic rules for addition, subtraction, multiplication and division of binary numbers are given below: Addition

Subtraction

Multiplication

Division

(i)

0+0=0

0–0=0

0×0=0

0∏1=0

(ii)

0+1=1

1–0=1

0×1=0

1∏1=1

(iii)

1+0=1

1–1=0

1×0=0

0 ∏ 0 = not allowed

(iv)

1 + 1 = 10

10 – 1 = 1

1×1=1

1 ∏ 0 = not allowed

Two binary numbers can be added in the same way as two decimal number are added. The addition is carried out from the least significant bits and proceeded to higher significant bits, adding the carry resulting from previous addition each time. Consider the addition of the binary number 1101 and 1111.

MSB LSB

Decimal

1101 1111

13 15

11100

28

The addition carried out above can be explained as follows. Step 1:

The least significant bits are added, i.e. 1 + 1 = 0 with a carry 1.

Step 2: The carry in the previous step is added to the next higher significant bits, i.e. 1 + 0 + 1 = 0 with a carry 1. Step 3: The carry in the previous step is added to the next higher significant bits, i.e. 1 + 1 + 1 = 1 with a carry 1. Step 4: The carry in the previous step is added to the most significant bit, i.e. 1 + 1 + 1 = 1 with a carry 1. Thus the sum is 11100. The addition is also shown in decimal number system in order to compare the results.

Binary subtraction is also carried out in the same way as decimal number are subtracted. The subtraction is carried out from the least significant bits and proceeded to higher significant bits. When a 1 is subtracted from a 0, a 1 is borrowed from immediate higher significant bit. The following problem explains the steps involved. Suppose that 1001 is subtracted from 1110. MSB LSB

Decimal

1110

14

1001

9

0101

5

The steps are explained below. Step 1: The least significant bits (1 column) are considered. 0 – 1 needs a borrow from the next higher significant bit (column 2 from the right). Thus, 0 – 1 results in a difference of 1 and borrow 1. Step 2: The second column is taken. Since a 1 is given to the first column, now change the 1 here to 0. Thus the subtraction to be performed is 0 – 0 = 0 Step 3:

In the third column, the difference is given by 1 – 0 = 1

Step 4:

In the fourth column (MSB), the difference is given by 1 – 1 = 0

Thus, the difference between the two binary numbers is 0101. Binary multiplication is rather simpler than the decimal multiplication. The procedure is same as that of decimal multiplication. The binary multiplication procedure is as shown. Step 1: The least significant bit of the multiplier is taken. If the multiplier bit is 1, the multiplicand is copied as such and if the multiplier bit is 0, 0 is placed in all the bit positions.

Step 2: Next higher significant bit of the multiplier is taken and as in step 1, the product is written with a shift in left. Step 3:

Step 2 is repeated for all other higher significant bits and everytime a left shift is given.

Step 4: When all the bits in the multiplier have been taken into account, the product terms are added, which gives the actual product of the multiplier and the multiplicand. The following examples illustrates the multiplication procedure.

Multiply the following binary numbers. (i) 1101 and 1100 (ii) 1000 and 101 (iii) 1111 and 1001

Solution (i) 1101 × 1100

(ii) 1000 × 101 1 1 0 1

1 0 0 0

× 1 1 0 0

×

0 0 0 0

1 0 0 0

0 0 0 0 1 1 0 1 1 1 0 1

1 0 1

00 0 0 1 00 0 1 01 0 00

1 0 0 1 1 1 0 0 (iii) 1111 × 1001 1 1 1 1 × 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1

Division in binary follows the same procedure as division in decimal. Division by 0 is meaningless. An example is given below.

Perform the following divisions: (i) 110 ∏ 10 (ii) 1111 ∏ 110

Solution (i) 110 ∏ 10

(ii) 1111 ∏ 110

112 10 110 10 10 10

310

10.12

2 6 6 0

2.510

110 1111.0 110 110 110

00

6 15.0 12 30 30

000

00

The usefulness of the complement numbers stems from the fact that subtraction of a number from another can be accomplished by adding the complement of the subtrahend to the minuend. The actual difference can be obtained with minor manipulations.

Subtraction of binary numbers can be accomplished by using the 1’s complement method, which allows us to subtract using only addition. The 1’s complement of a binary number is found by simply changing all 1s to 0s and all 0s to 1s. To subtract a smaller number from a larger number, the 1’s complement method is as follows: 1. Determine the 1’s complement of the smaller number. 2. Add the 1’s complement to the larger number. 3. Remove the carry and add it to the result. This carry is called end-around-carry.

Subtract 10102 from 11112 using 1’s complement method. Show direct subtraction for comparison.

Solution Direct subtraction

1’s complement method

1 1 1 1

1 11 1

–1 0 1 0

1’s comp. Æ

0 1 0 1

carry

0 1 0 1 10 10 0

add carry

1 0 10 1

To subtract a larger number from a smaller one, the 1’s complement method is as follows: 1. Determine the 1’s complement of the larger number. 2. Add the 1’s complement to the smaller number. 3. The answer has an opposite sign and is the 1’s complement of the result. There is no carry.

Subtract 10102 from 10002 using 1’s complement method. Show direct subtraction for comparison.

Solution Direct subtraction 1 0 0 0 –1 0 1 0

1’s complement method 1 00 0 0 1 0 1

1’s comp.Æ

–0 0 1 0

1 10 1

No carry results and the answer is the 1’s complement of 1101 and opposite in sign, i.e. – 0010. The 1’s complement method is particularly useful in arithmetic logic circuits because subtraction can be accomplished with an adder.

The 2’s complement of a binary number is found by adding 1 to its 1’s complement. To subtract a smaller number from a larger one, the 2’s complement method is applied as follows: 1. Determine the 2’s complement of the smaller number. 2. Add the 2’s complement to the larger number. 3. Discard the carry (there is always a carry in this case).

Subtract 10102 from 11112 using 2’s complement method. Show direct subtraction for comparison.

Solution Direct subtraction 1 1 1 1 –1 0 1 0 0 1 0 1

2’s complement method 1 1 11 0 1 10

2’s comp.Æ carry

1 0 1 01

The carry is discarded. Thus, the answer is 01012. To subtract a larger number from a smaller one, the 2’s complement method is as follows: 1. Determine the 2’s complement of the larger number. 2. Add the 2’s complement to the smaller number. 3. There is no carry. The result is in 2’s complement form and is negative. 4. To get an answer in true form, take the 2’s complement and change the sign.

Subtract 10102 from 10002 using 2’s complement method. Show direct subtraction for comparison.

Solution Direct subtraction

2’s complement method

1 0 0 0

1 00 0

–1 0 1 0

2’s comp.Æ

0 1 1 0

0 0 1 0

no carry

1 11 0

No carry results. Thus, the difference is negative and the answer is the 2’s complement of 11102, i.e. 00102. Both 1’s and 2’s complement methods of subtraction may seem more complex compared to direct subtraction. However, they both have distinct advantages when implemented with logic circuits because they allow subtraction to be done using addition. Both 1’s and the 2’s complements of a binary number are relatively easy to accomplish with logic circuits; and the 2’s complement has an advantage over the 1’s complement in that an end-around-carry operation does not have to be performed.

The 9’s complement of a decimal number can be found by subtracting each digit in the number from 9. The 9’s complement of decimal 0 to 9 is shown below: Decimal digit

9’s complement

0

9

1

8

2

7

3

6

4

5

5

4

6

3

7

2

8

1

9

0

Find the 9’s complement of each of the following decimal numbers: (a) 19 (b) 146 (c) 469 (d) 4397

Solution

Subtract each digit in the number from 9 to get the 9’s complement

(a)

99 –19

(b)

999

80

Æ 9’s Complement of 19

–146 853 (c)

999 – 469 530

(d)

Æ 9’s Complement of 146

Æ 9’s Complement of 469

9999 – 4397 5602

Æ 9’s Complement of 4397

Subtraction of a smaller decimal number from a larger one in the 9’s complement system is done by the addition of the 9’s complement of the subtrahend to the minuend and then adding the carry to the result. Subtraction of a larger number from a smaller one does not produce a carry, and the result is a negative in the 9’s complement form. This procedure has a distinct advantage in certain types of arithmetic logic.

Perform the following subtractions by using the 9’s complement method: (a) 18 – 06 (b) 39 – 23 (c) 34 – 49 (d) 49 – 84.

Solution (a) Regular subtraction 18 – 06 12

9’s complement subtraction 18 + 93 ¨ 9’s Complement of 6 (1)11 +1 add carry to result 12

(b)

39 – 23 16

39 + 76 ¨ 9’s Complement of 23 (1)15 +1 add carry to result

(c)

34 – 49

34 +50

–15 Ø – 15 ¨ 9’s Complement of 84 (d)

49 – 84

+ 15 ¨

– 35 Ø – 35 ¨ 9’s Complement of 84

The 10’s complement of a decimal number is equal to its 9’s complement +1.

Convert the following decimal numbers into its 10’s complement form: (a) 9 (b) 46 (c) 739.

Solution (a)

(b)

(c)

9 –9 0 +1 1

¨ 9’s Complement of 9

99 – 46 53 +1 54

¨ 9’s Complement of 46

999 – 739 260 +1 261

¨ 9’s Complement of 739

¨ 10’s Complement of 9

¨ 10’s Complement of 46

¨ 10’s Complement of 739

added to the 10’s complement of the subtrahend and the carry is dropped.

Subtract the following decimal numbers using the 10’s complement method: (a) 9 – 4 (b) 24 – 09 (c) 69 – 32 (d) 347 – 265.

Solution Regular subtraction (a) 9 –4 5

10’s complement subtraction 9 +6 ¨ 10’s Complement of 4 (1)5 Drop carry

(b)

24 – 09 15

24 + 91 ¨ 10’s Complement of 9 (1)15 Drop carry

(c)

69 – 32 37

69 + 68 ¨ 10’s Complement of 32 (1)37 Drop carry

(d)

347 – 265 82

347 + 735 ¨ 10’s Complement of 265 (1)082 Drop carry

When a computer is handling numbers in binary but in group of four digits, the number system is called Binary Coded Decimal (BCD). Combinations of binary digits that represent numbers, letters, or symbols are digital codes. The 8421 code is a type of binary coded decimal code. It has four bits and represents the decimal digits 0 through 9. The designation 8421 indicates the binary weights of the four bits. The case of conversion between 8421 code numbers and the familiar decimal numbers is the main advantage of this code. To express any decimal number in BCD, simply replace each decimal digit by the appropriate four-bit code. Table 24.1 gives the binary and BCD for the decimal numbers 0 through 15.

Decimal number

Binary number

Binary coded decimal (8421)

0

0000

0000

1

0001

0001

2

0010

0010

3

0011

0011

4

0100

0100

5

0101

0101 Contd...

Contd...

6

0110

0110

7

0111

0111

8

1000

1000

9

1001

1001

10

1010

0001

0000

11

1011

0001

0001

12

1100

0001

0010

13

1101

0001

0011

14

1110

0001

0100

15

1111

0001

0101

BCD is a numerical code, and many applications require that arithmetic operations be performed. Addition is the most important operation because the other three operations like subtraction, multiplication and division can be accomplished using addition. The rule for adding two BCD numbers is given below. 1. Add the two numbers, using the rules for binary addition. 2. If a four-bit sum is equal to or less than 9, it is a valid BCD number. 3. If a four-bit sum is greater than 9, or if a carry-out of the group is generated, it is an invalid result. Add 6 (01102) to the four-bit sum in order to skip the six invalid states and return the code to 8421. If a carry results when 6 is added, simply add the carry to the next four-bit group.

Add the following BCD numbers:

Solution (i)

0 0

(ii)

0 0 + 0 0 0 0 0 0

1 + 0 1 + 0 0 1 0 Ø 1 0 1 1 0 1 0 1 0 1 + 0 1 1 0 Ø 3

0 1 1 1 0

0 1 1 1 0

0 0 0 1 1 Ø 3 0 0 0 1 1 Ø 3

1 0 1 0 1

1 0 1 0 1

Invalid BCD number Add 6 Valid BCD number

Right group is invalid Add 6 Valid BCD number

9 +4 1310

19 + 14 3310

Boolean algebra is a set of rules, laws, and theorems by which logical operations can be expressed mathematically. It is a convenient and systematic way of expressing and analyzing the operation of digital circuits and systems. In Boolean algebra, a variable can be either a zero or a one. The binary digits are utilized to represent the two levels that occur within digital logic circuits. A binary 1 will represent a HIGH level and a binary 0 will represent a LOW level. The complement of __ a variable is represented by a ‘bar’ over the letter; for example, the complement of A is represented by A.

Boolean addition involves variables having values of either a binary 1 or a 0. The basic rules for Boolean addition are as follows: 0+0 =0 0+1 =1 1+0 =1 1+1 =1 The Boolean addition is the same as the logical OR operation. The multiplication rules for Boolean algebra are the same as the binary multiplication rules, discussed in Section 24.3.3. 0.0 = 0 0.1 = 0 1.0 = 0 1.1 = 1 The Boolean multiplication is the same as the logical AND operation. The three basic properties of Boolean algebra are commutativity, associativity and distributivity. The Boolean addition is commutative, i.e. A+B =B+A This says that the order in which the variables are ORed makes no difference. The Boolean algebra is also commutative over multiplication, i.e. A◊B =B◊A This states that the order in which the variables are ANDed makes no difference. The associative property of addition is stated as follows: A + (B + C) = (A + B) + C The ORing of several variables results in the same regardless of the grouping of the variables. The associative law of multiplication is stated as follows: A◊ (B◊C) = (A◊B) ◊ C This law tells us that it makes no difference in what order the variables are grouped when ANDing several variables.

The Boolean addition is distributive over Boolean multiplication. That is, A + BC = (A + B) (A + C) Also, the Boolean multiplication is distributive over Boolean addition, i.e., A (B + C) = A B + A C The first distributive property states that ANDing several variables and ORing the result with a single variable is equivalent to ORing the single variable with each of the several variables and then ANDing the sums. The second distributive property states that ORing several variables and ANDing the result with a single variable is equivalent to ANDing the single variable with each of the several variables and then ORing the products. The other basic laws of Boolean algebra are given in Table 24.2.

Sl. No.

Boolean Law

1

A+0=A

2

A+1=1

3

A 0=0

4

A 1=A

5

A+A=A

6

A+A=1

7

A A=A

8

A A=0

9

(A) = A

__

__ __

10

A + AB = A

11

A + AB = A + B

12

AB + AC + BC = AB + AC

__ __

__

The rules 1 to 9 can be very easily proved by perfect induction. The proofs for the rules 10, 11 and 12 are given as follows. __

__

Prove __ the following laws of Boolean algebra. (i) A + AB = A (ii) A + AB = A + B (iii) AB + AC + BC = AB + AC

Solution (i) A + AB

__

(ii) A + AB

= A (1 + B) distributive law =A 1 law 2 =A law 4 __ = (A + A) (A + B) distributive law = 1 (A + B) law 6 =A+B law 4

__

__

(iii) AB + AC + BC = AB + A C + BC1 __ __ = AB + A C + BC (A + A) __ __ = AB + AC + ABC + A BC __ = AB (1 __ + C) + AC (1 + B) = AB + AC __

__

The above property, i.e AB + AC + BC = AB + AC, is called consensus theorem.

Two theorems that are important parts of Boolean algebra were proposed by De Morgan. The first theorem states that the complement of a product is equal to the sum of the complements. That is, if the variables are A and B, then ___

__

__

AB = A + B The second theorem states that the complement of a sum is equal to the product of the complements. In equation form, this can be written as ______

__ __

A+B =A◊B The complement of a Boolean logic function or a logic expression may be expanded or simplified by following the steps of De Morgan’s theorem. (i) Replace the symbol (+) with symbol (.), the symbol (.) with symbol (+) given in the expression. (ii) Complement each of the terms or variable in the given expression. De Morgan’s theorems can be proved for any number of variables; proof of these two theorems for 2-input variables can be found in Table 24.3.

1

2

3

4

5

6

__

__

A

B

A

B

A+B

A◊B

0

0

1

1

0

0

1

1

0

1

0

0

1

1

0

7

8

9

______

__ __

_____

A◊B

10 __

__

A+B

A◊B

0

1

1

1

1

1

0

0

0

1

1

1

1

0

0

0

1

1

0

1

1

0

0

0

0

A+B

A study of Table 24.3 makes clear that columns 7 and 8 are equal. Therefore, ______

__ __

A+B =A◊B Similarly, columns 9 and 10 are equal. Therefore, _____

__

__

A◊B =A+B Also, De Morgan’s theorem can be proved by a algebraic method as follows: __

__

According to the first theorem, (A + B) is the complement of AB. From Table 24.2, the Boolean laws are given as, __

__

A + A = 1 and AA = 0

__

__

__

Substituting AB for A and (A + B) for A in the above expressions. __

__

__

AB + A + B = 1

__

and

AB (A + B) = 0

A+B+B =1

and

ABA + ABB = 0

A+1 =1

and

0+0 =0

1 =1

and

0 =0

__

__

__ __

__

Thus De Morgan’s first theorem is proved algebraically.

__ __

Similarly, according__to __ De Morgan’s second theorem, (A ◊ B) is the complement of (A + B). Substituting (A + B) for A and (A ◊ B) for A in the Boolean laws 6 and 8 given in Table 24.2 __ __

A+B+A◊B=1

__ __

and

(A + B) ◊ (A ◊ B) = 0

A+B+B=1

and

AAB + BAB = 0

A+1=1

and

0+0 =0

1=1

and

0 =0

__

__

___

Thus De Morgan’s second theorem is proved algebraically.

In the application of Boolean algebra one has to reduce a particular expression to its simplest form or change its form to a more convenient one in order to implement the expression most efficiently. The basic rules and laws of Boolean algebra are used to manipulate and simplify an expression. The algebraic simplification method requires a thorough knowledge of Boolean algebra and considerable practice in its application. Several examples are given below to illustrate the technique. __

__

Simplify the following expressions using Boolean algebra: (a) A + AB + ABC (b) (A + B)C + ABC __ __ (c) ABC (BD + CDE) + AC

Solution __

(a) Step 1: Step 2:

Step 3:

A + AB + ABC Apply rule 10 of Table 24.2, i.e A + AB = A. The expression simplifies to __ A + ABC Apply distributive property __ (A + A) (A +__BC) = A (A + BC) Taking A as the common term, __

A[1. (1 + BC)] __

Step 4:

Apply rule 2 of Table 24.2, i.e. 1 + BC = 1 A.1 = A

Thus, the simplified expression is__A (b) (A + B) C + ABC

Step 1: Step 2: Step 3: Step 4:

Apply distributive property __ AC + BC + ABC Taking BC as a common term, __ AC + BC (1 + A) Apply rule 2 __ AC + BC.1 Taking C as the common term, __ C (A + B) __

Thus, the simplified expression is C (A + B) __ __ (c) ABC (BD + CDE) + AC Step 1: Apply distributive property __ __ __ AB BCD + ABCCDE + AC Step 2: Apply rules 8 and 7 to the first and second terms, respectively, __ __ 0 + ABCDE + AC Step 3: Taking A as the common term, __ __ A ( B CDE + C) __ __ __ __ Step 4: Apply rule 11, i.e., B CDE__+ C = B DE +C __ A (BDE + C) __

__

Thus, the simplified expression is A (BDE + C) ______________________ __________ __ __

Simplify the expression AB + ABC + A (B + AB)

Solution ______________________ __________ __ __

_____________________ __________ __

AB + ABC + A (B + AB) = A (B + BC) + A (B + A) _____________________ _________ __

= A (B + C) + AB + A ◊ A _________________ ________ __

= AB + AC + AB + A

___________________ ________ __

= AB + AC + A (B + 1) _______________ ________ __

= AB + AC + A ◊ 1 ____________ ________ __

= AB + AC + A

______________ _____ __ _____

= (AB) ◊ (AC) + A ___________________ __ __ __

= (A + B) ◊ (A + C) + A ____________ __ __

= (A + BC) + A { ___________ __ __

= A + BC + A _______ __

= 1 + BC

(A + B) (A + C) = A + BC]

_

=1

[

1 + A = 1]

=0 __

__

Simplify Y = ABC +ABC +ABC to Y = A (B + C)

Solution

__

__

Y = ABC +ABC +ABC __

__

= AC (B + B) + ABC __

= AC ◊ 1 + ABC __

= A (C + BC) = A (B + C) __ ___ __

__ __

___

__

Simplify the given Boolean expression Y = A B C + ABC + ABC + ABC.

Solution

__ __ __

__ __

__ __

__

Y = A B C + ABC + AB C + ABC __ __

__

__

__

= A C (B + B) + AC (B + B) __ __

__

= A C + AC __ __

= C (A + A) __

=C◊1 __

=C ___________________ __ ______

Simplify the expression Y = (AB + C) (A + B +C).

Solution

___________________ __ ______

Y = (AB + C)(A + B + C) __________________ __ __ __

= (AB + C)(A ◊ B + C)

___________________________ __ __ __ __ __ __

= AB ◊ A B + ABC + A B C + CC __________________ __ __ __

= 0 + ABC + A B C + 0 ____________ __ __ __

= ABC + A B C _____ _____ __ __ __

= ABC ◊ A B C __

__

__

__

__

__

__ __

__ __

__ __

= (A + B + C) ◊ (A + B + C) = (A + B + C) ◊ (A + B + C)

__

_____ __

__ __

__

Simplify the expression Y = AC [ ABD ] + ABC + ABC.

Solution

_____ __

__

__ __ __

__

Y = AC [ABD] + ABC D + ABC __

__

__

__ __

__ __ __

__

__

= AC [ A + B + D ] + ABC D + ABC __ __ __

__ __

__

= ACA + ACB + ACD + ABC D + ABC __ __

__ __ __

__ __

__

__

__

__

__ __

= BC (A + A) + A D (C + BC) __ __

__

__

= BC + A D (B + C)

[ A + AB = A +B] _______ __

__ __

__ __

Prove the following Boolean expression: (A + B) (A C + C) (B + AC) = ABC.

Solution

_______ __

__ __

__ __ ____

__ __

(A + B) (A C + C) (B + AC) = (A + B) + (A C + C) (B ◊ AC) __ __

____

= (A + B) (A C + C) (B ◊ AC) __ __

__ __

__

__

= [AA C + AC + A CB + BC] [B (A + C)] __ __

__

__

= (AC + A CB + BC) ◊ (BA + BC) __

__

__ __

__

= AC ◊ BA + AC ◊ BC + A CB ◊ BA __ __

__

__

__

+ A CB ◊ BC + BC ◊ BA + BC ◊ BC __ __

__ __

__

= 0 + 0 + ABC + A CB + BCA + 0 __

__

__

= AB (C + C + C) __

= AB __ __ __

__ __

__ __

__ __

__

__

______

Prove that A B C + A BC + ABC + ABC + AB C = A + B + C.

Solution

__ __ __

__ __

__ __

__

__ __

__ __ __

__

__

__ __

A B C + A BC + ABC + ABC + AB C = A B (C + C) + AB (C + C) +AB C __ __

__ __

__

= A B + AB + AB C

__ __

__ __

= A (B + B) + AB C __

__ __

= A + AB C __

__ __

= A + BC __

__

[ A + AB = A + B]

______

=A+B+C

__

[ A◊A=0]

= A BC + ACD + ABC D + ABC

__

__ __

__

Find the complement of the expression Y = ABC + ABC + A BC + ABC.

Solution __

_________________________ __ __ __ __

Y = ABC + ABC + A BC + ABC _____ __

_____

_____ __ __

_____ __

= (ABC) (ABC) (A BC) (ABC) __

__

__

__

__

__

__

__

= (A + B + C) (A + B + C) (A + B + C) (A + B + C) __

__

__

__

__

= (A + B + CC) (A + C + BB) __

[ (A + B) (A + C) = A + BC]

__

__

= (A + B) (A + C) __ __

__ __

__

Prove that BCD + AC D + ABD = BCD + AC D + ABC.

Solution

__ __

__ __

BCD + AC D + ABD = BCD + AC D + (ABD) ◊ 1 __ __

__

= BCD + AC D + (ABD) (C + C) __ __

__

= BCD + AC D + ABCD + ABCD __ __

= BCD (1 + A) + AC (D + DB) __ __

= BCD + AC (D + B) __ __

__

= BCD + AC D + ABC Hence

LHS = RHS __

__ __

Simplify the given expression Y = AB + ABD + ABCD + BC.

Solution

__

__

__ __

__ __

AB + ABD + ABCD + BC = B (A + AD) + C (B + BAD) __

__

__

= B (A + D) + C (B + AD) __

[ A +AB = A +B]

__

= AB + BD + BC + ACD __

__

__

= AB + BD + BC (A + A) + ACD [ A + A = 1] __

__

__

= AB + BD + ABC + ABC + ACD __

__

= AB (1 + C) + BD + ABC + ACD __

__

= AB + BD + ACD

__

__

[ AB + BC + AC = AB + AC] [Here A = D; B = B; C = AC]

__

__ __

__

__

__ __

__ __

If AB + CD = 0, then prove that AB + C (A + D) = AB + BD + B D + A CD.

Solution

__ __

__

LHS = AB + C (A + D) + 0 __ __

__

__

__

__

__

= AB + C (A + D) + AB + CD (given that AB + CD = 0) __ __

__ __

__

__

= AB + A C + C D + AB + CD __

__

__

__ __

= B (A + A) + D (C + C) + A C __ __

__

= B + D + AC __ __

__ __

RHS = AB + BD + B D + A CD + 0 __ __

__ __

__

__

__ __

__

__

= AB + BD + B D + A CD + AB + CD __ __

__

= B (A + A) + BD + B D + A CD + CD __ __

__ __

__

= B (1 + D) + B D + A CD + CD __ __

__ __

__

= B + B D + A CD + CD __

__ __

__

__

= B + D + A CD + CD (since A + AB = A + B) __ __

__

= B + D (1 + C) + A CD __ __

__

= B + D + DA C __

__ __

= B + D + AC Hence,

__

(since A + AB = A + B)

LHS = RHS __

__

Simplify Y = AB + (A + B) C.

Solution __

__

Y = AB + (A + B) C __

___ __

__

__ __

___ __

__

= AB + (AB) C

(since A + B = AB)

__

__

= AB + C

(since X + XY = X +Y)

__ __ __

Simplify Y = A + AB + A BC + A B CD.

Solution

__

__ __

__ __ __

__ __

__ __ __

__

A + AB + A B C + A B CD = A + B + A BC + A B CD [ A + AB = A + B] __

__ __ __

= A + B + BC + A B C D __ __ __

= A + B + C + A B CD

__

(given that AB + CD = 0)

__ __

= A + B + C + B CD __

= A + B + C + CD =A+B+C+D __

__

__

__

If AB + AB = C, show that AC + AC = B.

Solution

__

________ __ __

__

__

__

__

__

AC + AC = A (AB + AB) + A (AB + AB) __

__

__ __

__

(given that C = AB + AB)

__ __

= A (A + B) (A + B) + AAB + A AB __

__

= (AA + AB) (A + B) + AB __

= AB + AB + AB __

= AB + AB __

= B (A + A) =B

The basic elements that make up a digital system are called as logic gates. The most common logic gates are OR, AND, NOT, NAND and NOR gates. The NAND and NOR gates are called as universal gates. Exclusive-OR gate is another logic circuit which can be constructed using AND, OR and NOT gates.

The OR gate performs logical addition, commonly known as OR function. The OR gate has two or more inputs and only one output. The operation of OR gate is such that a high (1) on the output is produced when any of the inputs is high (1). The output is low (0) only when all the inputs are low (0). As shown in Fig. 24.1, A and B represent the inputs and Y the output. Resistance R is the load resistance. If A = 0 and B = 0 then V0 = 0 and Y = 0. If A = 1 and B = 0, diode D1 will conduct and so the output Y = 1. If A = 0 and B = 1, diode D2 will conduct and the output Y = 1. If A = 1 and B = 1, both the diodes will conduct and so the output Y = 1. The electrical equivalent circuit of an OR gate is shown in Fig. 24.1(b) where switches A and B are connected in parallel with each other. If either A, B or both are closed, then the output will result. The logic symbol for OR gate is shown in Fig. 24.1(c). The logic operation of the two input OR gate is described in the truth table shown in Table 24.4.

D1 A y D2 B R

Vo

(a) A y Input

A

y

Output B

B

(b)

(c)

Input

Output

A

B

Y

0

0

0

0

1

1

1

0

1

1

1

1

The AND gate performs logical multiplication, commonly known as AND function. The AND gate has two or more inputs and a single output. The output of AND gate is high only when all the inputs are high. When any of the inputs is low, the output is low. As shown in the Fig. 24.2(a), A and B represent the inputs and Y represents the output. If A = 0 and B = 0, both diodes conduct as they are forward biased and the output Y = 0. If A = 0 and B = 1, diode D1 conducts and D2 does not conduct, and again the output Y = 0. If A = 1 and B = 0, diode D1 does not conduct and D2 conducts, and the output Y = 0. If A = 1 and B = 1, both the diodes do not conduct as they are reverse based and so the output Y = 1. The electrical equivalent circuit of an AND gate is shown in Fig. 24.2 (b) where two switches A and B are connected in series. If both A and B are closed, then only output will result. Logic symbol of the AND gate is shown in Fig. 24.2(c). The logic operation of the two input AND gate is described in the truth table shown in Table 24.5.

VCC

R D1 A y

D2 B

Vo

(a) A Input

y A

B

y

Output B

(b)

(c)

Input

Output

A

B

Y

0

0

0

0

1

0

1

0

0

1

1

1

The NOT gate performs a basic logic function called inversion or complementation. The purpose of the gate is to change one logic level to opposite level. It has one input and one output. When a high level is applied to an inverter input, a low level will appear at its output and vice-versa. The operation of the circuit can be explained as follows. When a high voltage is applied to the base of the transistor, base current increases and the transistor is saturated. The transistor now acts as a closed switch and conducts heavily. Thus the output voltage is logic 0. On the VCC other hand, when a low voltage is applied at the base, the transistor is cut-off due to very low or no base curRc rent. Now, the transistor can be considered as an open y switch, with no current flowing through it. The output R A is now clamped to the supply voltage. The transistor Vo when operated between cut-off and saturation will act y as a switch. A As shown in Fig. 24.3(a), A represents the input and y represents the output. If the input is high, the transistor is in ON state and the output is low. If the input is low,

(a)

(b)

the transistor is in OFF state and the output is high. The symbol for the inverter is shown in Fig. 24.3(b). The truth table is given in Table 24.6.

Input A

Output Y

0 1

1 0

NAND is a contraction of NOT–AND. It has two or more inputs and only one output. When all the inputs are high, the output is low. If any of the inputs is low, the output is high. The logic symbol for the NAND gate is shown in Fig. 24.4.

A

y

B

The truth-table for the NAND gate is shown in Table 24.7.

A

Input B

Output Y

0

0

1

0

1

1

1

0

1

1

1

0

The NAND gate is a very popular logic function because it is an universal function; that is, it can be used to construct an AND gate, an OR gate, and INVERTER or any combination of these functions. Figure 24.5 shows how NAND gates can be connected to realize various logic gates.

A

A A+B

B

– – A.B

A B

– B

(ii) AND gate

(i) OR gate

A

A (iii) NOT gate

A.B

NOR is a contraction of NOT–OR. It has two or more inputs and only one output. Only when all the inputs are low, the output is high. If any of the inputs is high, the output is low. The logic symbol for the NOR gate is shown in Fig. 24.6.

A Y

B

The truth-table for the NOR gate is shown in Table 24.8.

A

Input B

Output Y

0

0

1

0

1

0

1

0

0

1

1

0

The NOR gate is also a very popular logic function because it is also an universal function; that is, it can be used to construct an AND gate, an OR gate, and INVERTER or any combination of these functions. Figure 24.7 shows how NOR gates can be connected to realize various logic gates. A

A+B A

B

– A

(i) OR gate

A

– A

A (iii) NOT gate

B

B

– B (ii) AND gate

An Exclusive-OR gate is a gate with two or more inputs and one output. The output of a two-input Ex-OR gate assumes a HIGH state if one only one input assumes a HIGH state. This is equivalent to saying that the output is HIGH if either input A or input B is HIGH exclusively, and low when both are 1 or 0 simultaneously. The logic symbol for the Ex-OR gate is shown in Fig. 24.8(a) and the truth table for the Ex-OR operation is given in Table 24.9. The truth table of the Ex-OR gate shows that the output is HIGH when any one, but not all, of the inputs is at 1. This exclusive feature eliminates a similarity to the OR gate. The Ex-OR gate responds with a HIGH output only when an odd number of inputs is HIGH. When there is an even number of HIGH inputs, such as two or four, the output will always be LOW. From the truth table of a 2-input

– A

A

– AB

B Y=A

A

– – Y = AB + AB = A

B

B

Y

B A B (a) Logic symbol

– AB

– B

(b) Using AND-RO-NOT gates

Input A

B

Output Y=A B

0

0

0

0

1

1

1

0

1

1

1

0

Ex-OR__gate, the __ Ex-OR function can be written as Y = AB + AB = A B.

– A

A

– AB

The above expression can be read as Y equals A Ex-OR B. Using the above expression, a 2-input Ex-OR gate can be implemented using basic gates like AND, OR and NOT gates as shown in Fig. 24.8(b). The 2-input Ex-OR gate can also be implemented using NAND gates as shown in Fig. 24.9.

B

– – Y = AB – AB – – = AB – AB

A

– B

– AB

A

Y

B

B

The main characteristic property of an Ex-OR gate is that it can perform modulo-2 addition. It should be noted that the same Ex-OR truth table applies when adding two binary digits (bits). A 2-input Ex-OR circuit is, therefore, sometimes called a module-2 adder or a half-adder without carry output. The name half-adder refers to the fact that possible carry-bit, resulting from an addition of two preceding bits, has not been taken into account. A full addition is performed by a second Ex-OR circuit with the output signal of the first circuit and the carry as input A signals, as shown in Fig. 24.10. B The configuration of Fig. 24.10 is a cascading of two Ex-OR circuits resulting in an Ex-OR operation of three variables A, B, and C. Consequently, the sum output of a full adder

Y = [A C

B]

C

for two bits is an Ex-OR operation of the 2 bits to be added and the carry of the preceding adding stage. The logic expression of the Ex-OR operation of three variables A, B, and C is given by __

__

__

________ __ __

__

__

__

__ __

A ≈ B ≈ C = (AB + AB) C + (AB + AB) C = (AB + AB) C + (A B + AB) C __ __

__ __

__ __

A ≈ B ≈ C = AB C + ABC + A BC + ABC In general, Ex-OR operation of n variables results in a logical 1 output if and odd number of the input variables are 1s. An Ex-OR operation of n variables can be obtained by cascading 2-input Ex-OR gates. Another important property of an Ex-OR gate is that it Logic variable A input can be used as a controlled inverter, i.e., by using an Ex-OR gate, a logic variable can be complemented or allowed Control input to pass through it unchanged. This is done by using one Ex-OR input as a control input and the other as the logic variable input as shown in Fig.__24.11. When the control input is HIGH, the output Y = A and when the control input is LOW, the output Y = A.

Y(output)

The exclusive-NOR gate, abbreviated Ex-NOR, is an Ex-OR gate, followed by an inverter. An exclusiveNOR gate has two or more inputs and one output. The output of a two-input Ex-NOR gate assumes a HIGH state if both the inputs assume the same logic state or have an even number of 1s, and its output is LOW when the inputs assume different logic states or have an odd number of 1s. The logic symbol of Ex-NOR gate is shown in Fig. 24.12 and its Y=A≈B Y=A≈B truth table is given in Table 24.10. From the A A truth table, it is clear that the Ex-NOR output B B is the complement of the Ex-NOR gate. The Boolean expression for the Ex-NOR gate is ______

Y =A≈B

Input A

B

Output ______ Y=A≈B

0

0

1

0

1

0

1

0

0

1

1

1

Read the above as “Y equals A Ex-NOR B”. According to De Morgan’s theorem, ______

________ __ __

A ≈ B = AB + AB ___ ___ __ __

= AB ◊ AB

__

__

= (A + B) (A + B) __ __

= AB + A B An important property of the Ex-NOR gate is that it can be used for bit comparison. The output of an Ex-NOR gate is 1 if both the inputs are similar, i.e., both are 0 or 1; otherwise, its output is 0. Hence, it can be used as a one-bit comparator. It is also called a coincidence circuit. Another property of the Ex-NOR gate is that it can be used as an even-parity checker. The output of the Ex-NOR gate is 1 if the number of 1s in its inputs is even; if the number of 1s is odd, the output is 0. Hence, it can be used as an even/odd parity checker. Hence, the 2-input Ex-NOR gate is immensely useful for bit comparison and parity checking.

___

___

___

Realise the logic expression Y = BC + AC + AB using basic gates.

Solution In the given expression, there are 3 product terms each with two variables which can be implemented using three 2-input AND gates, and the product terms can be OR operated together using a 3-input OR gate. The complemented form of individual variable can be obtained by 3 NOT gates. Thus, the circuit for the given expression is realised as shown in Fig. 24.13.

A

–– AB

B

–– BC –– –– –– Y = AB + BC + AC

C

–– AC

__

Realise the logic expression Y = (A + B) (A + C) (B + D) using basic gates.

Solution In the given expression, there are 3 sum terms which can be implemented using three 2-input OR gates and their outputs are AND operated together by a 3-input AND gate. A NOT gate can be used to obtain the inverse of A. Now, the realised circuit is shown in Fig. 24.14. A

(A + B )

B – (A + C ) – Y = (A + B)(A + C)(B + D)

C (B + D) D

______

___

Implement Y = AB + A + (B + C) using NAND gates only.

Solution

The implementation of the given function is shown in Fig. 24.15. A

AB

AB

– Y = AB, A. (B + C) = AB + A + (B + C)

B – A

– B B+C

C

– C

The logic gates are the fundamental building blocks of the combinational logic circuit. When logic gates are connected together to produce a specified output for certain specified combinations of input variables, with no storage involved, the resulting network is called combinational logic. In combinational logic, the output level is at all times dependent on the combination of input levels. Basically, digital circuits are divided into (i) Combinational Circuits, and (ii) Sequential Circuits. In combinational circuits, the outputs at any instant of time depend upon the inputs present at that instant of time. This means there is no memory in these circuits. There are other types of circuits in which the output at any instant of time depend upon the present inputs as well as past outputs. This means that there are elements used to store past information. Such circuits are known as sequential circuits. Logical functions are expressed in terms of logical variables. Boolean algebraic theorems are used for the manipulation of logical expressions. A logical expression can be realized using the logical gates. The values assumed by the logical functions as well as the logical variables are in the binary form. Any arbitrary logical function can be expressed in the following forms. (i) Sum of Products Form (SOP) (ii) Product of Sums Form (POS)

For example, the logical expression, Y = AB + A C + BC is a sum of products expression and Y = (A + B)(B + C ) is in product of sums form. The sum-of-product form of logical expressions can be realized using AND–OR combination as shown in Fig. 24.16. This realization is known as two level realization. The first level consists of AND gates and the second level consists of OR gates. Consider the expression, Y = (A + BC)(B + C A) = (A + B)(A + C)(B + C )(B + A) = (A + B)(A + C)(B + C ) The above equation can be realized using OR–AND combination as shown in Fig. 24.17.

A B

A B

A A– Y

C

Y

C B – C

B C

I Level I Level

II Level

II Level

Each individual term in the standard SOP form is called as minterm and the standard POS form as maxterm. An important characteristics of sum-of-products and product-of-sums forms is that the corresponding implementation is always a two-level gate network; hence, the maximum number of gates through which a signal must pass in going from an input to the output is two, excluding inversions.

Karnaugh map technique provides a systematic method for simplifying and manipulating Boolean expressions. In this technique, the information contained in a truth table or available in POS or SOP form is represented on Karnaugh map (K-map). In an n-variable K-map there are 2n cells. Each cell corresponds to one of the combinations of n variables. Therefore, we see that for each row of the truth table, i.e. for each minterm and for each maxterm, there is one specific cell in the K-map. The variables have been designated as A, B, C and D, and the binary numbers formed by them are taken as AB, ABC, and ABCD for two, three and four variables, respectively. The K-map for two, three and four variables are shown in Fig. 24.18.

The entries in a truth table can be represented in a K-map as discussed below. A B 0

0

AB

1

C

0

2

1

3

0 1

1

00 0

01 2

1

3

(a)

10

11 6

4

7

5

(b)

AB CD

00

00 01

01

10

0

4

11 12

1

5

13

9

3

7

15

11

2

6

14

10

8

11 10

(c)

Consider the truth table shown in Table 24.11.

A

Inputs B

C

Output Y

0

0

0

0

0

0

1

1

0

1

0

1

0

1

1

0

1

0

0

1

1

0

1

0

1

1

0

0

1

1

1

1

The output Y can be written as, __ __

__ __

__ __

Y = A BC + ABC + AB C + ABC The K-map for the above expression is shown below. Variables

__ __

__

AB 00

AB 01

__

AB 11

AB 10

__

C

0

C

1

1

1

1

1

The value of the output variable Y (0 or 1) in each cell can be entered corresponding to its decimal or minterm or maxterm identification. Simplification is based on the principle of combining terms in adjacent cells. One can group 1s that are in adjacent cells according to the following rules by drawing a loop around those cells: 1. Adjacent cells are cells that differ by only a single variable. For example, the cells numbered 000 and 001 are adjacent to each other because they differ by only one bit. Similarly, the cells 011 and 111, 000 and 010, 100 and 110 are all adjacent cells. 2. The 1s in adjacent cells must be combined in groups of 1, 2, 4, 8 and so on. 3. Each group of 1s should be maximized to include the largest number of adjacent cells as possible in accordance with rule 2. 4. Every 1 on the map must be included in at least one group. There can be overlapping groups if they include common 1s. Grouping is illustrated by the following examples.

Simplify the K-map shown below.

Variables __

C

0

C

1

__ __

__

AB 00

AB 01

__

AB 11

1

AB 10 1

1

1

The adjacent cells that can be combined together are the cells 000 and 100 and the cell 011 and 111. By combining the adjacent cells, we get Y = (A + A) B C + (A + A) BC = B C + BC The above equation can be obtained from the K-map by using the following procedure. (i) Identify adjacent ones, then see the values of the variables associated with these cells. Only one variable will be different and gets eliminated. Other variables will appear in ANDed form in the term; it will be in the uncomplemented form if it is 1 and in the complemented form if it is 0.

(ii) Determine the term corresponding to each group of adjacent ones. These terms are ORed to get simplified equation in SOP form.

Simplify the K-map shown below.

Variables __ __

CD

00

CD

01

CD

11

__

__ __

__

AB

AB

AB

AB

00

01

11

10

__

1

1 1

1

__

CD

10

In the above K-map, the of adjacent 1s. __adjacent cells can be combined to form __ __ __following __ __ __ __two pairs Thus, the cell pairs are B C D and BCD. The simplified functions is Y = B C D + BCD.

In this section, several types of MSI combinational logic functions are studied, including adders, multiplexers, demultiplexers and code converters.

Adder circuits form one of the main applications of the combinational logic circuits. Half adders and full adders are discussed in this section. A logic circuit for the addition of two one-bit numbers is referred to as an half adder. The half adder accepts two binary digits on its inputs and produces two binary digits on its outputs, a sum bit and a carry bit. The logical operation of the half adder is explained in Table 24.12.

Inputs

Outputs

X

Y

Sum

Carry

0

0

0

0

0

1

1

0

1

0

1

0

1

1

0

1

From the truth table, the logical expressions for the sum (S) and carry (C) outputs are given by S = X¢Y + XY¢ = X ≈ Y C = XY

The implementation required for the half adder is apparent from the above two logical expressions. The sum output is generated with an exclusive-OR gate and the carry output is produced with an AND gate with X and Y on the inputs. The realization of an half adder using gates is shown in Fig. 24.19.

X S Y

C

An half adder has only two inputs and there is no provision to add a carry coming from the lower order bits when multibit addition is performed. To include the carry, a third input terminal is added and this circuit is used to add Xn, Yn and Cn – 1, where Xn and Yn are the nth order bits of the numbers X and Y, respectively, and Cn – 1 is the carry generated from the addition of (n–1) order bits. This circuit is called the full adder circuit. The operation of a full adder is shown in Table 24.13. +

Xn

Inputs Yn

Cn – 1

Sum

Outputs Cn

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1

From the truth table, the logical expressions for sum (Sn) and carry (Cn) outputs are given by __ __

__

__

Sn = XnYnCn – 1 + XnYnCn – 1 + XnYn __

Cn – 1 + XnYnCn – 1 __ __

__

__

= Xn (YnCn–1 + YnCn – 1) + Xn __

Xn Yn Cn –1

SUM

Xn

Yn

__

(YnCn – 1 + Yn Cn – 1) = Xn __

Yn

Cn – 1 __

Cn = XnYnCn – 1 + XnYnCn – 1 + XnYn __

Cn – 1 + XnYnCn – 1 = YnCn – 1 + XnCn–1 + XnYn The realization of a full adder circuit is shown in Fig. 24.20.

CARRY

YnCn –1 + XnCn–1 + Xn Yn

A logic circuit for subtracting two bits is referred to as a half subtractor. The logical operation of a half subtractor can be understood from Table 24.14.

Inputs

Outputs

X

Y

D

B

0

0

0

0

0

1

1

1

1

0

1

0

1

1

0

0

Here, X (minuend) and Y (subtrahend) are the two inputs, and D (difference) and B (borrow) are the two outputs. From the truth table, the logical expressions for D and B are obtained as D = X Y + XY = X

Y

B =XY Figure 24.21 shows the realization of a half subtractor using logic gates.

X

D

Y

A full subtractor circuit performs multibit subtraction where a borrow from the previous bit position may be included. A full subtractor has three inputs, Xn (minuend), Yn (subtrahend) and Bn – 1 (borrow from the previous stage) and two outputs, Dn (difference) and Bn (borrow).

B

Xn

Input Yn

Bn – 1

Dn

Output Bn

0

0

0

0

0

0

0

1

1

1

0

1

0

1

1

0

1

1

0

1

1

0

0

1

0

1

0

1

0

0

1

1

0

0

0

1

1

1

1

1

From the truth table, the output logical expressions can be written as __ __

__

__

__ __

Dn = XnYnBn – 1 + XnYnBn – 1 + XnYnBn – 1 + XnYnBn – 1 = Xn

Yn

__ __

Bn–1 __

__

__

Bn = XnYnBn – 1 + XnYnBn – 1 + XnYn Bn – 1 + XnYnBn – 1 __ __

__

__

__

= XnYnBn – 1 + XnYnBn – 1 + YnBn – 1 (Xn + Xn) __

__

__

= Xn (YnBn – 1 + Yn Bn – 1) + YnBn – 1 __

= Xn (Yn

Bn – 1) + YnBn – 1

Figure 24.22 shows the realization of a full subtractor circuit. Xn

DIFFERENCE

Xn

Yn

Bn –1

Yn Bn –1

BORROW – Xn[Yn

The multiplexer (or data selector) is a logical circuit that gates one out of several inputs to a single output. The input selected is controlled by a set of select inputs. Figure 24.23 shows the block diagram of a multiplexer with n input lines and one output lines. For selecting one out of n inputs for connection to the output, a set of m (2m = n) select signals is required.

Bn–1] + YnBn–1

l0 l1 l2 Inputs

l3

n:1 Multiplexer

ln –1 G

Depending upon the digital codes applied to the select inputs one out of n data sources is selected and transmitted to a single output channel, provided that the system is enabled. Truth table for 14–1 multiplexer is given in Table 24.16.

Sm–1 S2 S1 S0

y Output

l0

Select inputs S1

S2

Output Y

0

0

I0

0

1

I1

1

0

I2

l2

1

1

I3

S2

l1 S1

The logical output Y can be expressed as

l3

Y = S1S2I0 + S1S2I1 + S1S2I2 + S1S2I3

– (G) ENABLE

y

The above equation can be realized using gates and is shown in Fig. 24.24.

The demultiplexer does the reverse operation of a multiplexer. It can be used to separate the multiplexed signals into individual signals. The block diagram of a demultiplexer is shown in Fig. 24.25. The select input code determines to which output the data input will be transmitted.

Demultiplexer 1 input signal

n output signals

m select lines

The number of output lines is n and the number of select lines is m, where n = 2m. Figure 24.26 shows a 1–16 demultiplexer. The input data D is transmitted to one of the outputs Yi by means of the select signals S1, S2, S3, and S4. When S4 = 0, S3 = 0, S2 = 0 and S1 = 0, data D is available at output Y0, and for S4 = 1, S3 = 1, S2 = 1 and S1 = 1 data D is available at output Y15. For other combinations of select signal lines, data D is available on the respective output lines.

An encoder converts an active input signal into a coded output signal. Figure 24.27 shows the block diagram of an encoder. There are n input lines, only one of which is active. Internal logic within the encoder converts this active input to a coded binary output with m bits. Figure 24.28 shows a common type encoder, the decimal to BCD encoder. For example, when the button 5 is pressed, the B and D OR gates have high inputs, therefore the output is ABCD = 0101.

S4

S3

S2

S1

Data D

Y0

Y1

n-input

ENCODER

Y2

Y15 m-output

+ 5V

A decoder is similar to demultiplexer, with one exception – there is no data input. The only inputs are the control bits ABCD as shown in Fig. 24.29. This logic circuit is called 1-of-16 decoder stance, when ABCD is 0001, only the Y1 AND gate has all inputs high, and the outputs of all other AND gates are low.

0 1 2 3 4 5 6 7 8

The Gray code is an unweighted code, which means that there are no specific weights assigned to the bit positions. The Gray code exhibits only a single bit change from one code number to the other.

9

A

Table 24.17 gives a set of four bit binary numbers and their equivalent Gray code.

B

C

D

A

B

C

D

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15

Decimal

Binary numbers

Gray code

0

0000

0000

1

0001

0001

2

0010

0011

3

0011

0010

4

0100

0110 Contd..

Contd..

5

0101

0111

6

0110

0101

7

0111

0100

8

1000

1100

9

1001

1101

10

1010

1111

11

1011

1110

12

1100

1010

13

1101

1011

14

1110

1001

15

1111

1000

The most significant digit (left most) in the Gray code is the same as the corresponding digit in the binary number. Going from left to right, add each adjacent pair of binary digits to get the next Gray code digit. Neglect carries. For example, consider the binary number 10110 to Gray code conversion. 1. The left most Gray digit is the same as the left most binary digit. 10110 Binary 1 Gray 2. Add the left most binary digit to the adjacent one 10110 Binary 11 Gray 3. Add the next adjacent pair 10110 Binary 111 Gray 4. Add the next adjacent pair and discard carry 10110 Binary 1110 Gray 5. Add the last adjacent pair 10110 Binary 11101 Gray The conversion is now complete and the Gray code is 11101. The logical expression for each of the Gray code bits can be obtained from the truth-table using algebraic simplification. The logical expressions for each bit of the 4-bit Gray code (G3G2G1G0) are given below. G 3 = B3 G 2 = B3 ≈ B2 G 1 = B2 ≈ B1 G0 = B1 ≈ B0

where B3B2B1B0 is the given binary number. A binary-to-Gray code convertor is shown in Fig. 24.30 (a). sponding digit in the Gray code. Add each binary digit generated to the Gray digit in the next adjacent position. Neglect carries. B3

G3

G2

B2

G1

B1

G0

B0 (a)

B3

G3

B2

G2

B1

G1

B0

G0 (b)

The conversion of the Gray code number 11011 to binary is given below. 1. The left most digits are the same. 11011 Gray 1 Binary 2. Add the last binary digit just generated to the Gray digit in the next position. Disregard carry. 11011 Gray 10 Binary 3. Add the last binary digit generated to the next Gray digit.

11011 Gray 100 Binary 4. Add the last binary digit generated to the next Gray digit. 11011 Gray 1001 Binary 5. Add the last binary digit generated to the next Gray digit. Disregard carry. 11011 Gray 10010 Binary The final binary number is 10010. The logical expression for each of the binary bits can be obtained from the truth-table using algebraic simplification. The logical expressions for each bit of the 4-bit Binary (B3B2B1B0) are given as follows. B3 B2 B1 B0

= G3 = G3 ≈ G2 = G3 ≈ G2 ≈ G1 = G3 ≈ G2 ≈ G1 ≈ G0

where G3G2G1G0 is the given binary number. A Gray-to-binary code convertor is shown in Fig. 24.30 (b). the result to 4-bit binary. Excess 3 code is an unweighted code. The following Table 24.18 shows the conversion between decimal, BCD and Excess-3 codes.

Decimal

BCD

Excess-3

0

0000

0011

1

0001

0100

2

0010

0101

3

0011

0110

4

0100

0111

5

0101

1000

6

0110

1001

7

0111

1010

8

1000

1011

9

1001

1100

A combinational circuit can be defined from the behavioural point of view as a circuit whose output is dependent on the inputs at that time instant, or can be defined from the constructional point of view as a circuit that does not contain any memory element.

External inputs

A sequential circuit, on the other hand, can be defined from the behavioural point of view as a circuit whose output depends not only on the present inputs, but also on the past outputs, or can be defined from the constructional point of view as a circuit that contains at least one memory element. The block diagram of a sequential circuit is shown in Fig. 24.31.

Combinational circuit

Memory element

Outputs from combinational circuit

Outputs from memory element

Clock

Sequential circuits are classified into (i) asynchronous and (ii) synchronous circuits depending on the timing signals. A sequential circuit whose behaviour depends upon the sequence in which the input signals change is referred to as an asynchronous sequential circuit. The outputs will be affected whenever the inputs change. A sequential circuit whose behaviour can be defined from the knowledge of its signals at discrete instants of time is referred to as a synchronous sequential circuit. In these circuits, the memory elements are affected only at discrete instants of time. The synchronisation is achieved by a timing signal known as system clock. The outputs are affected only with the application of a clock pulse.

A device that exhibits two stable states is extremely useful as a memory element in a binary system. Any electrical circuit that has this characteristic falls into the category of the devices commonly known as flip-flop (or bistable multivibrators). The most basic type of flip-flop is the reset/set flip-flop. This can be built using either two NOR gates or two NAND gates. Each flip-flop has two outputs, Q and Q¢. When Q = 1 and Q¢ = 0, the flip-flop is said to be set. When Q = 0 and Q¢ = 1, the flip-flop is said to be reset. The truth-table for the RS flip-flop is given in Table 24.19.

R

S

Q

0

0

Last value

0

1

1 (set)

1

0

0 (reset)

1

1

Illegal

Consider the NOR gate flip-flop circuit shown in Fig. 24.32(a). When R = 1 and S = 0, the outputs Q = 0 and Q¢ = 1, therefore, the flip-flop is reset. When R = 0 and S = 1, the outputs Q = 1 and Q¢ = 0, therefore, the flip-flop is set. When the first condition is applied, i.e. R = 0 and S = 0, the flip-flop remains in its present state, i.e. Q remains unchanged. The condition R = 1 and S = 1 is forbidden as it violates the basic definition of a flip-flop taking both Q and Q¢ to the low state. Figure 24.32(b) shows the RS flip-flop that has a clock (CLK) input (Square wave). When the clock is low, the outputs will not change regardless of the conditions of the R and S

R

Q

S

– Q (a) Q

R

CLK

Q

S

(b)

inputs. When the clock input is high, the flip-flop will set if R = 0 and S = 1. When the clock input is high and R = 1 and S = 0, the flip-flop will reset. The truth-table of the clocked RS flip-flop is shown below in Table 24.20.

CLK

R

S

Q

0

0

0

No change

0

0

1

No change

0

1

0

No change

0

1

1

No change

1

0

0

No change

1

0

1

1

1

1

0

0

1

1

1

Illegal

Figure 24.33 shows the logic symbol and the realisation of an edge triggered D flip-flop using NAND gates. The presence of a small triangle on the clock input indicates that the flip-flop is edge triggered. The x in the truth-table (Table 24.21) are called “don’t cares’’ because if the clock is low, high or on its negative edge, the flip-flop is inactive. The outputs Q and Q¢ change only on the positive going edge of the incoming clock pulse. If D = 0 when the positive going clock appears, then Q = 0 and Q¢ = 1. If D = 1 when the positive going clock edge appears, then Q = 1 and Q¢ = 0. The data input and output

Q

D CLK

– Q (a) D Q

CLK – Q

(b)

are the same after the positive going pulse, i.e. the input data D is stored only on the positive going edge of the incoming clock pulse.

Clock

D

Q

x

0

No change

x

1

No change

0

0

1

1

Figure 24.34 shows the negative edge triggered JK flip-flop. The flip-flop is inactive when the clock is low, high, or on its positive going edge. When J = 0 and K = 0, the circuit is inactive. When J = 0 and K = 1, the negative going edge of the clock pulse puts the outputs at Q = 0 and Q¢ = 1. When J = 1 and K = 0, the negative going edge of the clock pulse puts the Q outputs at Q = 1 and

J

Q

K

– Q

CLK

Q¢ = 0. When J = 1 and K = 1, the outputs Q and Q¢ toggles or alternate with each negative going clock edge. (See Table 24.22).

Clock

J

K

Q

x

0

0

No change

x

0

1

No change

x

1

0

No change

x

1

1

No change

0

0

No change

0

1

0

1

0

1 __

1

1

Q J

T

hence, it acts as a toggle switch. If J = K = 1, then output is the complement of the previous state, so that the JK flip-flop is converted into a T flip-flop. The realisation of a T flip-flop from a JK flip-flop is shown in Fig. 24.35.

Q

CLK

K

The truth-table for a positive edge-triggered T flip-flop is shown in Table 24.23.

Clock

T

QN

x

0

No change

x

1

No change

0

No change

– Q

__

1

QN – 1

A register is a group of flip-flops that can be used to store a binary number. Registers find a variety of applications in digital systems including microprocessors. If the output of each flip-flop is connected to the input of the adjacent flip-flop, then the circuit is called a shift register. The name comes from the fact that each successive clock pulse moves or shifts the data bits one flip-flop to the left or to the right, depending on how the flip-flops are connected. Registers are classified depending upon the way in which data is entered and retrieved. They are: (1) Serial-in serial-out (SISO) (2) Serial-in parallel-out (SIPO)

(3) Parallel-in serial-out (PISO) (4) Parallel-in parallel-out (PIPO) Input data is applied one bit at a time to the first flip-flop in a chain and read out from the last flip-flop in a chain one bit at a time. Figure 24.36 shows four D flip-flops connected in serial-in serial-out The output Q of one flip-flop is connected to the D input of the next _____ _____ fashion. flip-flop. CLK , PRE, and CLR signals are connected in parallel to all four flip-flops, so that they are all clocked, all set, or all reset at the same time. This shift register is known as the shift right register because when the clock pulse is given the data are shifted to the right. _____

When an active low signal, as shown in Fig. 24.36(a), is given to the CLR input, all the Q outputs are 0’s. Next, assume that the data signal ‘1’ is given as the input to the flip-flop A. When the next positive edge of the clock pulse occurs, the 1 on the D inputs of the A flip-flop will be transferred to the QA output. On the next rising edge of the clock signal, the 1 at QA is transferred to QB output. The D input for the flip-flop A is ‘0’ and hence, the output QA is ‘0’. On the 3rd positive edge of the clock pulse QC becomes high and for the 4th positive edge of the clock pulse QD becomes high. The corresponding waveforms are shown in Fig. 24.36(b).

Data in

D PRE Q

D PRE Q

D PRE Q

D PRE Q

CLK

CLK

CLK

CLK

– CLR Q

– CLR Q

– CLR Q

CLR

Clear Clock (a) 1

2

3

Clock

Data

QA QB QC QD (b)

4

– Q

Data out

Input data is applied one bit at a time to the D input of the first flip-flop in a chain and read out from the Q outputs in parallel after a data word is all shifted in. A serial in—parallel out shift register is shown in Fig. 24.37. In a parallel-in serial-out shift registers, the bits are entered simultaneously into their respective stages on parallel lines rather than on a bit by bit basis on one line as with serial data inputs. Figure 24.38 shows the PISO shift register. There are four input data lines, A, B, C and D, ______

and a SHIFT/LOAD input that allows four bits for data to be entered into the shift register in a parallel fashion. ______

When SHIFT/LOAD is low, gates G1, G2 and G3 are enabled, allowing each data bit to be applied to the D input of the respective flip-flops. When a clock pulse is applied, the flip-flops with D = 1______ will SET and those with D = 0 will RESET, thereby storing all 4 bits simultaneously. When SHIFT/LOAD is high, gates G4, G5 and G6 are enabled, allowing the data bits to shift right from one stage to the next. The OR gates allow either the normal shifting operation ______ or the parallel data entry operation, depending on which AND gates are enabled by the SHIFT/LOAD control signal. Data input

D

D

C

D

D

C

C

C

CLK QA

QB

QC

QD

Data input CLK

QA QB QC QD

Data is entered into the PIPO shift register as in the previous PISO case. The difference is, the outputs are taken only from the Qs of all the flip-flops simultaneously.

A counter is one of the most important subsystems in a digital system. A counter circuit activated by a clock can be used to count the number of clock cycles. There are two types of counters: (1) Synchronous counters (2) Asynchronous counters.

A

B

C

D

Shift/Load

G4

D

G5

G1

D

G6

D

QA C

G2

QC

QB C

C

G3

D

Serial data QD out

C

CLK (a) Logic diagram Data in A B C D

SHIFT/LOAD Data out CLK (b) Logic symbol

The ripple counter is simple and requires less hardware. However, it has speed limitation. Each flipflop is triggered by the previous flip-flop, and thus the counter has a cumulative settling time. These counters are called Serial or Asynchronous. The speed of operation can be increased by using a parallel or synchronous counter but the hardware cost increases because of the extra circuitry introduced. In this type, every flip-flop is triggered by the clock in synchronism and the settling time is equal to the delay time of a single flip-flop.

Figure 24.39 shows the connection of JK flip-flops to act as a binary counter. For each flip-flop, the J and K inputs are connected to +5V. This means that each flip-flop will toggle when its clock input receives a negative _____ going clock pulse. The MSB of the counter is Q3 and the LSB of the counter is Q0. Initially, the CLR input of all the flip-flops _____ are tied to ground and hence all the Q outputs will be ‘0’. When the flip-flops are counting, the CLR input is tied to +5V, its inactive state. Figure 24.39 shows how the Q outputs of each flip-flop respond to each negative going clock edge. At each negative going clock edge, the count increases by 1.

+5 V

Q3

Q2

J CLK

Q1

J CLK

– Q3 CLR K

Q0

J CLK

– Q1

– Q2 CLR K

CLR

J CLK

– Q0 CLR K

K

CLR

Q3

Q2

Q1

Q0

(a) CLK

Q0

Q1

Q2

Q3 (b)

Initially the count is 0000. For the first negative going edge of the clock input, the LSB flip-flop sets, increasing the count to 0001. The Q0 output is connected to the clock input of the next most significant flip-flop. This high clock pulse does not cause the Q1 output to change. However, the second negative going clock edge applied to the LSB flip-flop causes the Q0 output to toggle from 1 to 0. This negative going clock edge causes the Q1 output to go from 0 to 1, changing the count to 0010. The count continues until 1111 is reached. Then on the next negative going clock edge, all flip-flop outputs toggle back to 0 for a count of 0000. Each flip-flop divides the incoming clock pulse frequency by a factor of 2. The frequency of the Q0 output is one-half that of the clock input. Similarly, Q1 output is one-fourth the frequency of the clock input, Q2 output is one-eighth the frequency of the clock input and the Q3 output is one-sixteenth the frequency of the clock input. The counter is called a ripple counter because the output of one flip-flop is fed to the clock input of another.

The delay time and hence, the settling time increase in the ripple counters are overcome in the synchronous counters. Figure 24.40 shows the circuit of a parallel (synchronous) binary counter. The J and K inputs of each flip-flop is tied to +5V, such that the flip-flop toggles for negative clock transition at its +5 V

J

CLK

A

J

B

K

– B

X

(a) Time count

a 0

b 1

c 2

d 3

C

K

– C

Y

– A

K

J

e 4

f 5

g 6

h 7

Clock

A

B

C (b)

C

B

A

Count

0 0 0 0

0 0 1 1

0 1 0 1

0 1 2 3

1 1 1 1

0 0 1 1

0 1 0 1

4 5 6 7

0

0

0

0

(c)

i 0

j 1

clock input. The AND gates are used to gate every second clock to flip-flop B, every fourth clock to flip-flop C, and so on. The clock is directly applied to flip-flop A. Since J and K inputs are tied to +5V, flip-flop A will change state for each negative clock transition. When A is high, AND gate X is enabled and the clock pulse is passed through the gate to the clock input of flip-flop B. Similarly, the AND gate Y is enabled and the clock pulse is passed through the gate to the clock input of the flip-flop C when A and B are high. The counter counts from 000 to 111 in a synchronous manner.

A decade counter requires four flip-flops. This is achieved by recycling after the count of 9 (1001) is reached. To decode the count 1010, a NAND gate is used and the output of the gate is connected to the _____ clear (CLR) inputs of the flip-flop as shown in the Fig. 24.41(a). Only QB and QD are connected to the NAND gate inputs. This is an example of partial decoding, in which the two unique state (QB = 1 and QD = 1) are sufficient to decode the count 1010 because none of the other states have both QB and QD high at the same time. When the counter goes into count 1010, the decoding gate output goes low and asynchronously RESETS all the flip-flops. 10 Decoder CLR High

QA J

C

CLK

QC

QB

J K cr

J

C

C

K cr

K cr

QD J C K cr

(a) CLK

1

2

3

4

5

6

QA

QB

QC

QD CLR (b)

7

8

9

10

Most physical quantities such as pressure, temperature, and flow are analog in nature. There are usually several steps in producing electrical signals which represent the values of these variables and in converting the electrical signals to a digital form that can be used for example, to drive an LED display or be stored in the memory of a microcomputer. The first step involves a sensor which produces a current or voltage signal that is proportional to the amount of the physical pressure, temperature, or other variable. The signals from most sensors are quite small, so they must be amplified and perhaps filtered to remove unwanted noise. Amplification is usually done with some type of operational amplifier circuit. The final step is to convert the signal to a proportional binary word with an analog-to-digital (A/D) converter.

Many systems accept a digital word as an input signal and translate or convert it to an analog voltage or current. These systems are called digital-to-analog converters. The digital word is presented in a variety of codes, the most common being pure binary or binary-coded-decimal. Figure 24.42 shows a circuit which will produce an output voltage proportional to the binary word applied to its inputs by the four switches. Since this converter has four data inputs, it is called a 4-bit converter. The circuit in Figure 24.42 is just a 4-input op amp adder circuit. The noninverting input of the op amp is tied to ground, so that input will be at 0 V. There is feedback from the output of the op amp to the inverting input, so the op amp will work continually to hold this input at 0 V. + 5V RF = 10 kW

D0

R1 = 100 kW

D1

R2 = 50 kW

D2

R3 = 25 kW

D3

R4 = 12.5 kW

+15 V 2

–

7 741

3

+

6

Vout

4 –15 V

If none of the data switches are closed, there will be no current through any of the input resistors and no current through RF. The output of the op amp, then, will be at the same voltage as the inverting input, 0 V. Now, suppose the D0 data switch is closed. This will apply a voltage of +5 V to one end of R1. The other end of R1 will be held at 0 V by the op amp, so R1 has a voltage of 5 V across it and the current

through R1 is 0.05 mA. In order to hold the inverting input at 0 V, the op amp pulls this current through RF. The voltage across RF produced by this current will be 0.05 × 10 kW = 0.5 V. Since one end of RF is at 0 V, the output of the op amp must be at –0.5 V in order to keep the current flowing from +5 V through R1 to 0 V and on through RF. Thus, closing D0 produces a voltage of –0.5 V on the output of the converter circuit. Suppose the D1 data switch alone is closed. Since R2 is only half the value of R1, twice as much current, or 0.1 mA, will flow through R2 to the summing point and on through RF into the output of the op amp. In order to pull a current of 0.1 mA through RF, the op amp will assert a voltage of –1 V on its output. The D1 data switch then produces an output voltage of –1 V, or twice as much as that produced by the D0 switch. If D2 alone is closed, a current of 0.2 mA, will flow through R3 to the summing point an on through RF into the output of the op amp. This current will produce a voltage of –2 V on the output of the op amp. Likewise, if switch D3 is closed, a current of 0.4 mA, will flow into the summing point and on through RF into the output of the op amp. This current will produce a voltage of –4 V on the output of the op amp. Now, suppose that switches D2 and D3 are both closed. The 0.2 mA current through R3 will combine with the 0.4 mA current through R4 at the summing point to produce a total current of 0.6 mA. The output voltage is proportional to the sum of the currents produced by the closed switches and is –6 V. The value of the four currents are related to each other in the same way that the weights of binary digits are. Therefore, the output voltage will be proportional to the binary word applied to the data inputs. D0 represents the least significant bit (LSB) because it produces the smallest current, and D3 represents the most significant bit (MSB) because it produces the largest current. Since there are four inputs, there are 16 possible input words, 0000 to 1111. These words produce output voltages ranging from 0 V for an input word of 0000 to –7.5 for an input word of 1111. Figure 24.43 shows D/A converter using R–2R ladder network. The ladder used in this circuit is a current-splitting device, and thus the ratio of the resistors is more critical than their absolute value. It can be observed from the figure that at any of the ladder nodes the resistance is 2R looking to the left or the right or towards the switch. Hence, the current will split equally toward the left and right, and this happens at every node. Considering node N – 1 and assuming the MSB turned ON, the voltage at that node will be –VR/3. Since the gain of the operational amplifier to node N–1 is –3R/2R, the weight of the MSB becomes V –3 R = ___ ( ) ( _____ ) 2R 2

VR Vo = – ___ 3

R

Similarly, when the second most significant bit is ON and all others are OFF, the output will VR VR VR Vo = + ___, the third bit gives + ___, and the LSB gives + ___ . The circuit uses a negative reference volt4 8 2N age and gives a positive analog output voltage. If negative binary numbers are to be converted, the sign-magnitude approach is used; an extra bit is added to the binary word to represent the sign, and this bit can be used to select the polarity of the reference voltage.

3R

+ 15V 2 R

2R

2R

R

2R

–

R

7 741

2R 3

+

6

Vo

4 – 15V

LSB

MSB – VR +

It is often required that data taken in a physical system be converted into digital form. Such data would normally appear in electrical analog form. For example, a temperature difference would be represented by the output of a thermocouple, the strain of a mechanical member would be represented by the electrical unbalance of a strain-gauge bridge, etc. The need therefore arises for a device that converts analog information into digital form. Two major characteristics of an A/D converter are resolution and conversion time. The resolution of an A/D converter is determined by the number of bits in the output word. An 8-bit A/D converter, for example, will represent the value of an input voltage with one of 256 possible words. Another way of putting this is to say that it will resolve an input voltage to the nearest one of 256 levels. The conversion time for an A/D converter is simply the time it takes the converter to produce a valid output word after it is given a ‘start conversion’ signal. When we refer to an A/D converter as ‘high speed’ or ‘fast’, we mean that it has a short conversion time. There are many different ways to do an analog-to-digital conversion. The method chosen depends on the resolution, speed, and type of interfacing needed for a given application. verter is the parallel converter, or flash type shown in Fig. 24.44(a). The resistor voltage divider sets a sequence of voltages on the reference inputs of the comparators as shown. If the voltage on the ‘+’ input of a comparator is greater than the reference voltage on its ‘–’ input, the output of the comparator will be high. In the circuit, the voltage to be converted is applied to the + inputs of all the comparators in parallel, so the number of comparators that have high on their outputs indicates the amplitude of the input

voltage. An input voltage of between 0 and 1 V, for example, is less than the reference voltage on any of the comparators, so none of the comparator outputs will be high. If the input voltage is between 1.002 and 2 V, only the A1 output will be high. For an input voltage between 2.001 and 3 V, both the A1 and A2 outputs will be high. Finally, for an input voltage greater than 3 V, all the comparator outputs will be high. Figure 24.44(b) summarizes the comparator output code that will be produced by input voltages between 0 and 4 V. The code produced on the outputs of the comparators is not binary, but with a simple gate circuit it can be converted to the binary equivalents shown in the rightmost column of Fig. 24.44(b). To increase the resolution, more comparators can be added. Seven comparators are required for 3-bit resolution and 15 comparators are required for 4-bit resolution. An N-bit converter requires 2N – 1 comparators. The number of comparators needed increases rapidly as the desired number of bits increases. The main advantage of a parallel comparator type A/D converter is its speed. The binary word is present on the outputs after just the propagation delay time of the comparators plus the delay time of the encoding gates. This is why a parallel comparator type A/D converter is often called a flash converter.

+4V

+

A3

10 kW –

3V 10 kW VIN

+

A2

Encoding gates

–

2V

D1 D2

10 kW + A1

–

1V 10 kW

(a)

VIN Volts 0 to 1 1.001 to 2 2.001 to 3 3.001 to 4

Comparator outputs

Binary outputs

A3

A2

A1

D1 D0

0 1 0 1

0 1 0 1

0 1 0 1

0 1 0 1

0 1 0 1

(b)

Figure 24.45 shows the block diagram of a counter type A/D converter. In this system, a continuous sequence of equally spaced pulses is passed through a gate. At the start of a conversion cycle, the counters are reset to 0, so the output of the D/A is at 0 V. A positive unknown voltage applied to the input of the converter will cause the output of the comparator to go high and enable the AND gate. This will let the clock pulses into the counter. Each clock pulse increments the counter by 1 and increases the voltage on the output of the D/A converter by one step. When the voltage on the output of the D/A converter passes the voltage on the unknown V input, the output of the comparator will go low and shut off the clock pulses to the counters. The count accumulated on the counters is proportional to the input voltage. The control circuitry then strobes the latches to transfer the count to the output and resets the counters to start another conversion cycle.

CLK

Comparator Analog + Vin – Reset Binary counter

8-Bit Binary output

Control circuit

D7

Latches

D0

Voltage output D/A

Latch strobe

The counter method is slower than flash type converter. The drawback of this type is that it requires a precision D/A converter. Another drawback of this type is that the counter has to start at 0 and count up until the D/A output passes the input voltage. For an 8-bit converter, then, conversion, may take as long as 255 clock cycles and for a 10-bit converter, a conversion may take as many as 1024 clock pulses. The successive approximation technique is another method to implement an A/D converter. Instead of a binary counter as shown in Fig. 24.45, a programmer is used. The programmer sets the most significant bit (MSB) to 1, with all other bits to 0, and the comparator compares the D/A output with the analog signal. If the D/A output is larger, the 1 is removed from the MSB, and it is tried in the next most significant bit. If the analog input is larger, the 1 remains in that bit. Thus a 1 is tried in each bit of the D/A decoder until, at the end of the process, the binary equivalent of the analog signal is obtained. The successive approximation type A/D converter has the disadvantage that it requires a D/A converter, but it has the advantages of good resolution and relatively high speed.

Digital integrated circuits are classified as small-scale integration (SSI) with less than 12 gates on the same chip, medium-scale integration (MSI) from 12 to 100 gates per chip, large-scale integration (LSI) with more than 100 gates per chip, and very large-scale integration (VLSI) with more than 1000 gates per chip.

ICs can be manufactured using two basic techniques, namely, bipolar and metal-oxide semiconductor (MOS) technologies. Bipolar technology is preferred for SSI and MSI because it is faster. MOS technology dominates the LSI field because of increased density of MOSFETs in the same chip area. A digital family is a group of compatible devices with the same logic levels and supply voltages. The major categories of the bipolar family are Diode–transistor logic (DTL), Transistor–transistor logic (TTL) and Emitter-coupled logic (ECL). The MOS category consists of PMOS–p channel MOSFET, NMOS–n channel MOSFET and CMOS–Complementary MOSFET families.

DTL uses diodes and transistors. A DTL NAND gate may be implemented as shown in Fig. 24.46. The operation of this positive NAND gate can be understood easily. If atleast one input is low, diode D connected to this input conducts and the voltage VA at point A is low. Therefore, diodes D1 and D2 do not conduct, IB = 0 and the transistor is off. This makes the output of transistor Q high and Y is in logic 1 state. When all the inputs are high (1) so that all input diodes D are cutoff, then VA rise towards VCC, and a base current IB results. When IB is sufficiently large, Q is driven into saturation and the output Y falls to its low (0) state. DTL has a fan-out of about 12 and can be further increased by replacing D1 by a transistor. DTL gates are obsolete and are seldom used these days.

VCC = 5 V

5K

2.2 K Y

D

A B C

D

A

D

l1

D1

D2 5K

lc B

Q l2

The fastest saturating logic circuit is the transistor–transistor logic shown in Fig. 24.47. TTL is fast, inexpensive, and easy to use. This switch uses a multiple-emitter transistor which can be easily and economically fabricated. The TTL circuit has the topology of the DTL circuit with the emitter junctions of Q1 acting as the input diodes D of the +5V DTL gate and the collector junction of 130 W 1.6 kW 4 kW Q1 replacing diode D1. The base-to-emitter diode of Q2 is used in place of diode Q3 D2 of the DTL gate, and both circuits have an output transistor. Transistor Q1 and 4-kW resistor act like a 2-input AND gate. The rest of the circuit inverts the signal so that the overall circuit acts like a 2-input NAND gate. The output transistors (Q3 and Q4) form a totem-pole connection; this kind of output stage is typical of most TTL devices. With a totem-pole output stage,

A B

Q1

D1

Q2

y 1 kW

Q4

either the upper or lower transistor is on. When Q3 is on, the output is high and when Q4 is on, the output is low. The input voltages A and B are either low (ground) or high (+ 5 V). If A or B is low, the base of Q1 is pulled down to approximately 0.7 V. This reduces the base voltage of Q2 to almost zero. Therefore, Q2 is cut-off. With Q2 open, Q4 goes into cut-off, and the base of Q3 is pulled high. Since Q3 acts as an emitter follower, the Y output is pulled up to a high voltage. On the other hand, when A and B are both high voltages, the emitter diodes of Q1 stop conducting, and the collector diode goes into forward conduction. This forces Q2 base to go high. In turn, Q4 goes into saturation, producing a low output. Without diode D1 in the circuit, Q3 will conduct slightly when the output is low. To prevent this, the diode is inserted; its voltage drop keeps the base–emitter diode of Q3 reverse-biased. In this way, only Q4 conducts when the output is low. Totem-pole transistors are used because they produce a low output impedance. Either Q3 acts as an emitter follower (high output), or Q4 is saturated (low output). The output voltage can change quickly from one state to the other because any stray output capacitance is rapidly charged or discharged through the low output impedance.

The circuit shown in Fig. 24.47 is called standard TTL. The internal time constants of the circuit can be lowered by decreasing the resistances. This decreases the propagation delay time; however, the small resistances increase the power dissipation. This design variation is known as highspeed TTL. A high speed TTL gate has a power dissipation of around 22 mW and a propagation delay time of approximately 6 nS, whereas a standard TTL gate has a power dissipation of about 10 mW and propagation delay time of approximately 10 ns. By increasing the internal resistances, the power dissipation of TTL gates can be reduced. Devices of this type are called low-power TTL. These devices are slower than standard TTL because of the larger internal time constants. A low-power TTL gate has a power dissipation of 1 mW and a propagation delay time of about 35 ns. When a transistor is switched from saturation to cut-off, one has to wait for the extra carriers to flow out of the base. The delay is known as Saturation Delay time. This delay can be reduced by using Schottky TTL. A Schottky diode is fabricated along with each bipolar transistor of a TTL circuit, as shown in Fig. 24.48. Because the Schottky diode has a forward voltage of only 0.25 to 0.4 V, it prevents the transistor from saturating fully. This eliminates saturation delay time and increases switching speed. Schottky TTL devices are very fast, capable of operating reliably at 100 MHz. The power dissipation is around 20 mW per gate and the propagation delay time is approximately 3 ns. By increasing internal resistances as well as using Schottky diodes, a compromise has been made between low power and high speed, which is referred to as low-power Schottky TTL. A low-power Schottky gate has a power dissipation of around 2 mW and a propagation delay time of approximately 10 ns.

Emitter-coupled logic has several other common names—current-mode logic (CML), current-steering logic, and non-saturating logic. The last Ground term is the key to this type of circuit. The propagation delay time can be eliminated by operating transistors only in either the active or the cut-off regions rather than R2 300 kW 290 kW R1 operating them in saturation or cut-off Q1 regions. The ECL devices are the fastest currently available. ECL has not proved Q2 X as popular as TTL, primarily because it is – X Q3 Q4 more expensive. Superfast computers use X 1.5 kW 1.5 kW ECL as do a number of the higher speed special-purpose computers. The basic ECL configuration can be best understood by examining a particular inverter. Figure 24.49 shows an ECL inverter. The logic levels in this system are as follows: Binary 0 is represented by –1.55 V and binary 1 by – 0.75 V. This is ‘positive logic’ since the more positive level, – 0.75 V, is the binary 1.

R3 1.8 kW

– 5.2 V

The circuit’s operation is based on a differential amplifier consisting of Q3 and Q4. When the input to Q3 is at –1.55 V, Q3 will be off and current will flow through R3 and R2. There will be a drop of about 0.8 V across R2. So, figuring a base-emitter drop of 0.75 V for Q1, the X output will be at –1.55 V. Since Q2 is cut-off by the –1.55 V input, very little current will flow through R1, and the output X will be at the base-emitter drop voltage across Q2. So the output will be at –0.75 V. When the input is at – 0.75 V, transistor Q3 will be on, Q4 will be off, the X output will be at –0.75 V, and the X output will be at – 1.55 V. The transistors are never saturated; they are either in their active region or off. A three-input ECL gate is shown in Fig. 24.50. This is a combined NOR and OR gate, depending on which output connection is used. Several generations of ECL circuits have evolved. In general, the circuits have become faster and require more power with each generation.

Integrated injection logic circuits represent an attempt to attain packing densities comparable to MOS circuits while using bipolar junction transistor technology. Standard bipolar technology is the fastest, however, it occupies larger space when compared to MOS circuits. This is due to the reasons that bipolar circuits require resistors, the transistors are larger and an isolation diffusion has to be provided. The problem can be overcome by the technique called merging, where the same transistor region is used as part of two or more devices. IIL is the most popular and commonly used merged technology. The basic IIL gate and a possible semiconductor layout is shown in Fig. 24.51. Each gate has an injector transistor to feed current into the base. This logic circuit has single input and multiple outputs. As no standard symbol exists, the logic gate is represented by a rectangular box, with arrow to represent input and outputs.

13 VCC (Ground) 9 4 OR 5 NOR

6

7

8

Inputs

1 VBB (–1.175 V)

10

8 0 0 0 0 1 1 1 1

2

VEE (– 5.2 V)

Injector + V

C1

B

C2

7 0 0 1 1 0 0 1 1

Outputs 6 0 1 0 1 0 1 0 1

5 1 0 0 0 0 0 0 0

4 0 1 1 1 1 1 1 1

C3 Al

P

N

+

N

+

N

+

SiO2

B

C3 C2 C1

Input

+V Injector

P N epitaxial

E +

N substrate (b)

E (a)

C3 C2

Input

C1 (b)

The configuration shown in Fig. 24.51 is actually an INVERTER with multiple outputs. Various other gates can be formed from this configuration. In Fig. 24.52, realizations for different logic gates are shown. The IIL outputs are open-collector outputs, and hence connecting them together forms a wired AND. Because the basic IIL gate has a single input and multiple outputs, design does not proceed along regular lines. The advantages of this technology has overcome this problem. IIL doesn’t lend itself to chip interconnections as TTL, and seems primarily suited for large-scale integration.

A

A

– A

–– AB = A + B –– AB = A + B –– AB = A + B

B

B – B

A·B = A + B (b)

(a) A

A·B A·B A·B B (c)

–5V

The circuits described so far are all termed bipolar circuits and use conventional transistors. For large-scale integration, quite often a field-effect transistor (FET) is used. The FET devices are easier to manufacture, smaller in size and have small power dissipation. As switching circuit, a FET can be used to form an inverter. A MOS INVERTER is shown in Fig. 24.53. With a logic 0, or ground input, the output of the circuit will have a –5 V output and with a –2 V or more negative input, the output will go to about 0 V. The FET on the top acts as a resistor.

Out

In

When a P-type substrate with N-type doping for the source and drain is used, the N-channel MOSFET is formed. This type is called as NMOS device. Figure 24.54 shows a NMOS NOR gate. The logic levels for this circuit are 0 to 1 V for a binary 0 and greater than +1.5 V for a binary 1. If any of the inputs A, B or C is a 1, the corresponding FET will conduct, causing the output to go to about + 0.8 V or less. If all inputs are at + 0.8 V or less, all the FETs will be off and the output will be at + 5 V. Figure 24.55 shows a NMOS NAND gate. The complementary MOS (CMOS) circuits have very low power consumption and considerable resistance to noise. They are, however, slow. But large numbers of circuits can be placed on a single chip, the power supply voltage can vary over a large range, and the circuits are

+ VCC T4 act as a resistor + VCC (5V)

y T1 A

T4 Act as resistor T2 B

D T1 A

T3

T2 B

C

C

T3

relatively economical to manufacture. The newest CMOS circuits have become relatively fast and are widely used for everything from electronic watches and calculators to microprocessors. In CMOS circuits both N- and P-channel field effect transistors are fabricated on the same substrate. The simplest form of CMOS integrated circuit consists of one N-channel and one P-channel MOS transistor, with both gate contacts tied together to form the input and both drain contacts tied together to form the output. Figure 24.56 shows the basic CMOS INVERTER. When the voltage at the input is near ground level, the gate-to-source voltage of the P-channel transistor approaches the value of the supply voltage +V, and P-channel FET is turned on. A low-resistance path is created between the supply voltage and the output, while a high-resistance path exists between the output and ground because the N-channel FET is off. The output voltage will approach that of the supply voltage +V. When the input voltage is near +V, the P-channel FET is turned off and the N-channel FET is turned on. This makes the output voltage to approach the ground value. As one FET is always off and since both N-channel and P-channel FETs allow very low leakage current when off, the power consumption is very low in either state. A two-input NOR gate can be constructed using CMOS circuits as shown in Fig. 24.57. It can be seen that each additional input requires an additional P- and N-channel pair of MOSFETs.

+V (+3 V to 5 V) A

B

Out

Logic families are normally compared based on the following parameters. It is the maximum number of loads that the device can reliably drive. Here, the load and device refer to the logic gates of the same family. This is the power dissipated per gate. It is defined as the amount of noise voltage that causes unreliable operation. If noise immunity is 0.3 V, then as long as the noise voltages induced on connecting lines are less than 0.3 V, the device will work reliably. The time delay encountered when a transistor tries to come out of the saturation out of hard saturation; extra carriers must first flow out of the base region. The delay incurred in this process is called as the propagation delay.

Between the bipolar family and MOS family, in general, the bipolar circuits are faster and the MOS circuits provide high package density. Table 24.24 gives the values of the parameters discussed above, for different logic families.

Parameter

DTL

TTL

ECL

MOS

CMOS

Basic gates

NAND

NAND

OR-NOR

NAND

NOR or NAND

8

10

25

20

> 50

Power dissipated per gate, mW

8 – 12

12 – 22

40 – 55

0.2 – 10

0.01

Noise immunity

Good

Very good

Good

Nominal

Very good

Propagation delay per gate, ns

30

12 – 6

4–1

300

70

Fan-out

Modern data processing systems require permanent or semi-permanent storage of large amounts of data. Microprocessor based systems rely on memories for their operation because memories are used to programs and data for processing. A number of reliable memory circuits are available which have replaced older devices like magnetic cores. A typical semiconductor memory consists of a rectangular array of memory cells, which are nothing but transistor flip-flops or a circuit capable of storing charge and is used to store 1 bit of information. Memories can be divided into the following categories—Read only memories (ROM) and random access, read–write memories (RAM).

Random access memory is used for applications where in the data changes frequently. Logic circuitry is available to store a single bit of information in a memory cell (WRITE) or to detect a 0 or a 1 stored in the memory cell (READ). A bit of data can be stored in any cell or read from any cell and so this type of memory is called as random access memory. The data stored in this type of memory is lost once the power is switched off. So, this memory is said to provide volatile storage. ROM is used in applications where the data do not change. Applications like monitor programs, look-up tables can be stored in a ROM. The content of a ROM is fixed during manufacturing. A ROM is random access and logic circuitry is available to read data from the selected cell, however, there is no write mode. Since data is permanently stored, loss of power never lead to loss of data.

Memory addressing is the process of selecting one of the cells in a memory to be written into or to be read from. Memories are generally arranged by placing cells in a rectangular arrangement of rows and columns. Figure 25.1 shows a memory array with m rows and n columns, with a total of m × n cells in the memory. The control circuitry is designed such that if only one row line is activated and only one column line is activated, the memory cell at the intersection of these two lines is selected. For example, in Fig. 25.1, if

n Columns 1

2

3

4

n

1

2

3 m rows

Memory cell 35 Column 5 4 Row 3

m (b)

(a)

row 3 and column 5 is activated, the cell at the intersection of this row and column is selected, and the address of this cell is designated as 35. Any row or column can be activated by placing a logic 1 on it. Memory can be arranged in various possible configurations of rectangular array of memory cells. If there are M memory cells, these can be arranged in M × 1 array, or 1 × M array, or m × n = M array. A signal column with n rows is frequently called as a linear array and addressing a cell in this array is referred to as linear addressing. The linear addressing requires the maximum number of address lines. The arrangement that requires the minimum address lines is a square array of m rows and m columns with a total of m2 memory cells. This arrangement is frequently known as matrix addressing. The number of address lines can be further reduced using decoders. To illustrate this, consider a 4 × 4 memory array as shown in Fig. 25.2. Normally, A2 A1 eight address lines are required to select a memory cell in the array. To select a single cell, we must activate only one row and only one column. This suggests the use of 1 of 4 two 1-of-4 binary-to-decimal decoders. decoder If the memory 34 (row 3 and column 4) is to be selected, A4A3A2A1 must be 1011. That is, if A4 = 1 and A3 = 0, the decoder will hold row 3 line high, while all other row lines will be low. Similarly, if A2 = 1 and A1 = 1, the decoder will hold column 4 line high and all other column lines low. Thus, the input A4A3A2A1 = 1011 will select the memory cell 34. We can consider A4A3 as row address of 2 bits and A2A1 as a column address of 2 bits. In general, an address

1 1

A4

2 1 of 4 decoder

A3

2

3 4

4¥4

3

4

of n bits can be used to define a square memory of 2n cells, where there are n/2 bits for the rows and n/2 bits for the columns as shown in Fig. 25.3.

Semiconductor ROMs are manufactured with bipolar technology or with MOS technology. A ROM contains permanently or semi-permanently stored data which can be read from the memory, but which either cannot be changed at all or cannot be changed without specialised equipment. A ROM is permanently programmed during the manufacturing process to provide widely used standard functions such as popular conversions or to provide user specified functions. Once the memory is programmed, it cannot be changed. The logic 1 or 0 is represented by the presence or absence of a transistor connection at a row/column junction as shown in Fig. 25.4(a). Presence of a connection from a row line to the base of a transistor represents a 1 at that location because when the row line is taken HIGH, all transistors with a base connection to that row line turn on and connect the HIGH (1) to the associated column lines. At row/column junctions where there are no base connections, the column lines remain LOW (0), when the row is addressed. Figure 25.4(b) illustrates MOS ROM cells. The presence or absence of a gate connection at the junction permanently stores a 1 or a 0. A simple ROM array is shown in Fig. 25.5. The blank squares represent that 0s are stored and the dark squares represent that 1s are stored. When a binary address is given to the address decoder, the corresponding row line goes HIGH. This HIGH is connected to the column lines through the transistors at each junction where a 1 is stored. At each cell where a 0 is stored, the column line stays LOW. The eight data bits stored in the selected row appear on the output lines. the manufacturing process, but are custom programmed in the field. PROMs are available in bipolar as well as in MOS technologies. Some type of fusing process is used to store bits. The fuse is open to

represent a 0 or left intact to represent a 1. The contents of a PROM, once programmed, cannot be changed. Figure 25.6 shows a PROM with fuses between the emitter of the transistor of each cell and its column line. The fuse can be blown by passing sufficient current through it, and a blown fuse represent a 0 and the unblown fuse represent a 1. A PROM is normally programmed using an instrument called a PROM programmer. An address is selected by the switch settings on the address lines and a pulse is applied to those output lines corresponding to cell locations where 0s are to be stored. These pulses blow the fuse links, thus creating the desired bit pattern. The next address is now selected and the process is repeated. This sequence is done automatically by the PROM programmer. Columns

+ VCC

+ VCC

+ VCC

+ VCC

+ VCC

+ VCC

+ VCC

+ VCC

Rows

+ VCC

The contents of an EPROM can be erased and reprogrammed. The memory arrays in these devices use an NMOS array with an isolated gate structure. The isolated gate has no electrical connections and store electrical charge for indefinite period of time. The presence of stored charge represents logic 1 and absence of stored charge represents a logic 0. Erasure of a data bit is a process that removes the gate charge. Two types of erasable PROMs are available, namely, the ultraviolet light erasable PROM (UVEPROM) and the electrically erasable PROM (EEPROM). In UVEPROMs, there is a quartz transparent lid on the package. When UV light is passed through this lid, the positive charge stored on every gate is neutralized. In EEPROM, electrical pulses are used for both programming and erasure of data bits. This type of device is also known as electrically alterable ROM (EAROM). The application of a voltage pulse on the control gate in the floating gate structure either stores or removes the charge from the floating gate.

The random access memory is an array of memory storage cells. In this memory, information can be randomly written into or read out of each storage element as required. The basic monolithic storage cell is the latch, or flip-flop. The operation of a RAM cell can be understood easily by considering the simple, 1-bit D flip-flop circuit shown in Fig. 25.7. X Address Write data in

D

CLK

Q

Read data out

– Q

Write enable

To read a data or to write it, the address line must be excited, i.e. X must be equal to logic 1. To perform write operation, the write enable line must also be excited. If the write input is a logic 1, then D = 1. Hence, Q = 1, and the data read out is 1. When the write input is logic 0, then D = 0, Q = 0 and the data read out is also 0. A system that can store 16 words of 8 bits each requires 16 × 8 = 128 storage cells, eight data input lines, eight data output lines and sixteen address lines. Figure 25.8 shows a block diagram of a MOS static memory. The 4096 bits of memory are arranged in an array of 64 rows and 64 columns. The memory cells are accessed by simultaneously decoding the X address A0 – A5 for the rows and the Y address A6–A11 for the columns. The chip select (CS) input controls the operation of the memory. When CS is low, the input address buffers, decoders, sensing circuits, and output stages are held in the off state, and power is supplied only to the memory elements. When CS goes high, the memory is enabled. The CS pulse clocks the TTL level addresses, READ–WRITE, and DATA input into D flip-flops and enables the output stage. When a cell is read from, one of the two outputs will be a 1. Figure 25.9 shows a random access memory of 16 words by 1-bit. For M-bit words, there will be M planes, like the one shown.

The DRAMs have individual memory cells composed of from one to three MOS transistors and a capacitor. The state of the cell is determined by placing or not placing a positive charge on the capacitor. A logic 0 is represented by no charge on the capacitor and logic 1 by placing a positive charge on the capacitor. This kind of memory requires individual memory cells that are simpler than flip-flops, less area on the chips and has lower power consumption. The disadvantages of DRAMs are that they are slower and the charge slowly leaks from the capacitor. Thus, the contents of each memory cells must be rewritten periodically. This is called refreshing the memory. In spite of these disadvantages, the memory costs are lower than the static memories and hence DRAMs are widely used in present day systems. Dynamic random access memories are arranged in the same way as static memories are. The twodimensional selection with decoders is standard. Memory controller chips are used to control several dynamic memory chips assembled into a memory. These controller chips handle the sequencing of the row and column addresses into the individual chips during a normal memory access and also control

Select lines A0

X Address FLIPFLOPS

A5

X-Row decoder

Memory matrix

Mode logic

Presence

128 lines, 64 pairs of digit lines

READ/WRITE

Output transmission gate

DATA INPUT

D0 – D0

64 lines Y column decoder

A6

Y address FLIPFLOPS

A11

Chip select

Y Address

Decoder X0

Y0

Y1

Y2

Y3

Decoder

X Address

X1

X2

– S

W

S

W

Write amplifiers

Sense amplifiers

X3

necessary refreshing of the memory. The refreshing generally involves a counter which sequences through all possible states during a 2-ms period. The memory controller chip attempts to perform refresh operations between memory accesses, whenever possible, thus reducing the time lost to memory

refreshes. Use of dynamic memory controller chips simplifies dynamic memory design and optimizes memory operation.

Programmable logic array is similar to a ROM in many ways but is very different in terms of their internal structure. The PLA can be either programmed while manufacturing or field programmed by the user. The user programmable PLAs are called as Field Programmable Logic Arrays (FPLAs). A PLA consists of two arrays, one for AND logic and one for OR logic, and can be programmed to produce desired logic functions on the outputs. Figure 25.10 shows a layout of a small PLA. This particular array has three AND gates and two OR gates. In actual PLAs, an array would have several hundred or more gates. A

B

C

Fusible link

Y1

Y2

In the figure, note that the connection from inputs A, B and C to the AND gates and the AND gate outputs to the OR gates are all connected through fusible links. These fuses are blown and connections established as desired by the gate network designer. __

__

__

__

To realize the Boolean algebra expressions, Y1 = ABC + AB and Y2 = A B C + AB, the fuses at the respective crossover points are kept intact and the fuses at the other crossover points are blown out, as shown in Fig. 25.11. The unblown fuses are represented by black dots at the crossover points.

A microprocessor is an electronic device which can be extensively used for various control applications when it is interfaced with memories and several input and output devices. It is a device that has a

A

B

C

ABC

– AB

– – ABC

– Y1 = ABC + AB – – – Y2 = ABC + AB Y1

Y2

limited set of on-chip memory locations, known as registers, to hold information. It can understand a fixed set of basic commands and can generate signals to control external devices. Inside the chip, there is an arithmetic logic unit (ALU). The ALU executes all arithmetic and logic instructions. For example, the arithmetic addition and logical AND operations will be performed by the ALU. The registers inside the microprocessor hold data on which the operations are performed. The control unit generates the external control signals and also controls the operation of the internal on-chip circuitry. The on-chip memory, in the form of registers, is generally very limited. Thus, almost every microprocessor based system has an off-chip memory also. The set of basic commands that a microprocessor can understand, is known as the instruction set of the microprocessor. Figure 25.12 shows the signals available in a typical microprocessor chip. The chip itself has several pins, like any other chip. The microprocessor sends or receives information over these pins. Each pin transmits or receives a Boolean signal which is either at logical 0 or at logical 1. Some pins may be in neither of these two states at certain points of time. Such pins, or lines, are said to be tri-state outputs. As shown in Fig. 25.12, a typical microprocessor has several lines over which it transmits an address to the off-chip memory or to the I/O devices. These are referred to as address lines. More often, the address lines are known as the address bus. A typical 8-bit microprocessor has an address bus consisting of 16 lines for transmitting the address. Thus, such a microprocessor can transmit an address that is of 16-bit wide. Every microprocessor has a set of lines for transmitting and receiving data. These lines are referred to as the data bus. A 8-bit microprocessor will generally have eight lines in its data bus. A 16-bit microprocessor may have either 16 lines in its data bus or only 8 lines. For example, the 8085 microprocessor

from Intel is an 8-bit microprocessor and has 8 lines in its data bus. The 8086 microprocessor, has 16 lines in its data bus and is a 16-bit microprocessor. The 8088 is a 16 bit microprocessor but has only 8 lines in its data bus. A lesser number of data bus is provided to reduce the space required on a printed circuit board for the data bus lines. A microprocessor also has lines for controlling the input and output devices. These devices could be an electric motor, or a display lamp or one of a variety of other devices. In addition to the control signals for input/output devices, a microprocessor also has some other control signals for (a) controlling off chip memory, (b) providing information about its own status and (c) performing other miscellaneous tasks. A brief description of the function of each element in a microprocessor is given below. One function of the accumulator is to store an operand prior to an operation by the arithmetic logic unit (ALU), and the other function is to temporarily store the result of the operation. This 16-bit counter produces the sequence of memory addresses in which the program instructions are stored. The content of the program counter is always the memory address from which the next instruction is to be taken. When the contents of the program counter go out onto the address bus to the memory, an eight-bit instruction is read from that memory location and is transferred on the data bus, to be temporarily stored in the instruction register until it is decoded and executed by the instruction decode and control element. An instruction is a binary code that tells the microprocessor what it is to do. A sequence of many different instructions designed to accomplish a specific result is a program. In other words, a program is a step-by-step procedure used by the microprocessor to carry out a specified task. The instruction decode and control element decodes an instruction code that has been transferred on the data bus from the memory. The instruction code is often called an op code. When the op code is decoded, the instruction decoder provides the control unit with this information so that it can produce the proper signals and timing sequence to execute or carry out the instruction.

The basic purpose of this element is to indicate the status of the contents of the accumulator or certain other conditions within the microprocessor. For example, it can indicate a zero result, a negative result, the occurrence of a carry, and the occurrence of an overflow from the accumulator. This register is used in conjunction with a portion of RAM that is set aside for use as a memory stack. The stack is used mainly to temporarily store the contents of all the registers when a subroutine is called or an interrupt requires the microprocessor to temporarily cease its current operation to respond to a request from an external device that needs to send data or requires service from the microprocessor. When an interrupt request has been serviced, the contents of the stack are transferred back into the appropriate registers and the microprocessor continues where it left off. The stack pointer is used to address the stack portion of RAM for storing and retrieving data in such a situation.

A simple block diagram of the Intel 8085A microprocessor is shown in Fig. 25.13. The 8085A has an 8-bit data bus which is shared with a 16-bit address bus. The 8085A has a 16-bit program counter, a 16-bit stack pointer, and an 8-bit instruction register and flag registers. The 8085A has a single 8-bit accumulator and six 8-bit general-purpose registers (B, C, D, E, H and L). Two general-purpose registers in the register array can be combined to form 16-bit registers. The incrementer/decrementer is associated with the register array and allows each register to be incremented or decremented independent of the ALU and accumulator. The single temporary register associated with the accumulator holds one of the operands for an ALU operation. The 8085A operates on a single 5 V supply. The required clock signals are created internally by connecting an external crystal between X1 and X2. Also, the 8085A has serial input data (SID) and serial output data (SOD) capability for use in simple forms of serial communications, such as teletype. A logic symbol showing inputs and outputs with pin numbers appears in Fig. 25.14.

A generalised block diagram of the 6800 microprocessor is shown in Fig. 25.15. All the elements are interconnected by an 8-bit common internal bus structure. This microprocessor can handle data in groups of eight bits from the data bus, and it has a 16-bit address bus. Thus, up to 65,536 memory locations can be addressed. All memory (other than registers) is external to this particular microprocessor, thus requiring additional chips to form a complete microcomputer system. The registers in the 6800 are as follows: two 8-bit accumulators, one 16-bit index register, one 16-bit program counter, one 16-bit stack pointer, one 8-bit condition code register, and one 8-bit instruction register. The 16-bit registers are actually treated as a combination of two 8-bit registers. The H label refers to the high-order bits, the L label to the low-order 8-bits. A logic symbol of the 6800 showing input and outputs with pin numbers appears in Fig. 25.16. The 6800 was the first of the Motorola microprocessor family and is still a widely used device. It requires three other chips to form a complete microcomputer system: an external clock generator, a RAM, and a ROM.

The 8086 and 8088 microprocessors are extensions of Intel’s 8080 microprocessor series. There are a number of changes in the 8086/8088, the most obvious being the fact that computations can be

Accumulator latch (8)

Accumulator (8)

Temporary register (8)

ALU

Flag flip-flops (5)

Interrupt control

SOD

E Register (8) L Register (8)

D Register (8) H Register (8)

Address buffer (8)

A15 – A8

Timing and control system

AD 7 – AD0 Address bus

Data/Address buffer (8)

Incrementer/decrementer address latch (16)

Program counter (16)

Stack pointer (16)

C Register (8)

B Register (8)

Timing and control

Instruction decoder and machine cycle encoding

Instruction register

Serial l/O control

SID

performed using 16-bit data. There are a number of other advantages including multiplication and division instructions, instruction queuing to improve operation speed, the ability to address a million bytes of memory, more general registers, and more instructions and addressing modes. The pin-outs for the 8086 and 8088 are shown in Fig. 25.17. The address and data lines are shared by using time-division multiplexing. The principal difference between the 8086 and 8088 lies in the number of data lines output to the bus. The 8086 has 16 data lines on its bus, and the 8088 has only 8. The 8086 use 16 of the address lines for data also, so that AD0 to AD15 are used for address and data while the 8088 has only AD0 to AD7 for data and uses A8 to A19 for addresses. The internal paths on the chips are the same and each can add, subtract, multiply, or divide 16-bit binary numbers. An important feature of the 8086 and 8088 microprocessors is the instruction queue used in each. The 8086/8088 chips read instructions in order from the memory in advance of their operation, and the instructions are placed in a queue consisting of a set of flip-flop registers. This speeds up operation because the processor can continue executing a time-consuming instruction and at the same time read

instructions from the memory of the processor. Then the processor can execute fast instructions from the queue at a speed faster than memory cycle times. Logic is supplied so that if the computer branches, the instructions in the queue are discarded if necessary. ____

The 8086/8088 pair each have a special output pin, the MN/MX pin. When this pin is connected to logic ‘1’, the processor is placed in a minimum mode; when it is connected to logic ‘0’, the processor is placed in a maximum mode. When in the minimum mode, the processor is used in single processor systems. In the maximum mode, several processors can be used with an 8288 bus controller which provides a special multibus architecture for multiprocessor systems. The maximum mode is for large arrays of memory, processors, and I/O devices. A block diagram of the registers of the 8086 and 8088 is shown in Fig. 25.18. The 8086/8088 processors have a number of addressing modes. Addresses are 20 bits in length. Each address is formed in two sections which are then added: a segment address and an offset. The segment address is a full 20 bits, and the offset address is 16 bits.

8086 CPU

8088 CPU

There are four segment registers, CS, DS, SS and ES, each containing 16 bits. These registers must be loaded by the program to starting values because the contents of one of these registers are automatically added to each address as it is generated. The contents of the 16-bit segment registers are first shifted left four binary places. (This is equivalent to multiplying the contents of the registers by 16.) Loading the segment registers with 0s would simply place the program and stacks in the first 216 words in memory and would effectively remove this feature for simple programs. When a program is operated, the content of the program counter is automatically added to CS to form each instruction address. Data offsets are automatically added to DS (or ES in special cases), and stack offsets are automatically added to SS. Setting the CS, DS, and SS registers to addresses in different parts of a large memory would cause the instructions, data and stacks to be in different parts of the memory. Setting the CS, SS, and DS registers to the same number would place everything in the same part of memory. Once the segment registers are set, the processor simply generates 16-bit offset

addresses in a conventional manner from the instruction words while adding the segment register to each address to form the final 20-bit address. If a program really needed 220 addresses, it would be necessary to change the segment registers from time to time to utilize the entire memory. In effect, the 8086 and 8088 generate conventional 16-bit (offset) addresses by using instruction words and then add the contents of a 20-bit number to each of these offsets to form a 20-bit final address. Quite a number of addressing modes are used to form the offsets in the 8086/8088 chips. Operands can be in general registers, memory, or I/O ports, and immediate addressing is provided. When 20-bit addresses are generated, the second byte in an instruction word contains the information as to how the 16-bit offset or effective address part of the address is to be calculated. (The first 3 and last 2 bits in this byte provide that information). In general, this section of the address is formed by summing the contents of a displacement (part of the instruction word), an index register, and a base register. Any combination of these three can be used. And this implements, for example, direct addressing, register indirect addressing, and indexed addressing. The segment registers make it possible to address a 220 word memory while only generating 16-bit offset addresses in the instruction words. Another advantage is that use of the segment registers makes a program relocatable in memory. This means that an operating system can place a program in memory where it desires. It can even place several programs in different parts of memory while the programmer simply writes a program without concern about where it will be run.

The 68000 microprocessor is a semiconductor chip with a number of support chips such as I/O processors, a floating-point arithmetic chip, and bus handler chips. The 68000 has 16-bit data paths on its system bus and performs 32-bit arithmetic and logic operations internally. The 68000 microprocessor can directly address 16 Mbytes of memory, having a 24-bit address bus. There are 14 addressing modes and 56 types of instructions. The I/O is memory mapped. The basic registers in the 68000 are shown in Fig 25.19. The registers are 32 bits, and there are eight data registers along with seven address registers and a program counter. There are actually two stack pointers. A status bit determines whether the 68000 is in the supervisor (operating system) mode or user mode; this bit also determines which of the two stack pointers are in use. The status register contains 5 bits for conditions codes. The 68000 supervisor and user modes are an important feature. There are privileged instructions which can be executed in supervisor mode, but not in user mode. When the supervisor-user mode select bit is a 1, the 68000 uses the supervisor stack pointer and the privileged instructions are available. When the select bit is a 0, the user stack pointer is employed, and certain instructions will not execute. Instruction words can be from one word (16 bits) to four words in length. Stacks in the 68000 go from high memory to low memory. So the stack pointer is decremented when data are pushed into a stack and incremented when data are popped from a stack.

A microprocessor does not have enough memory for program and data storage, neither does it have any input and output devices. Thus, when a microprocessor is used to design a system for specific applications, additional chips are also used to make up a complete system. These extra chips imply additional cost and increased size of the product. For example, when used inside a toy, a designer

would like to minimize the size and cost of the electronics equipment inside the toy. Therefore, in such applications, a microcontroller is used often than a microprocessor.

A microcontroller is a chip consisting of a microprocessor, memory and input/output devices. Microcontrollers vary in their data handling capacities. Thus there are 4-bit as well as 16-bit microcontrollers. The MCS-51 is a family of microcontroller ICs developed by Intel Corporation. A dedicated controller readily available for control applications in MCS-51 family is 8051 microcontroller. This is an 8-bit microcontroller. Other 8-bit microcontrollers in this family are 8031, 8751 and 8052 microcontrollers. The 8031 microcontroller does not contain internal ROM. It only uses an external ROM for making a complete system. The 8051 has Mask programmed ROM whereas the 8751 contains the UV Erasable on-chip ROM. The 8052 microcontroller offers two enhancements to the 8051 microcontroller. First, there is an additional 128 bytes of on-chip RAM. The second enhancement is an additional 16-bit Timer. The main hardware features of the 8051 series are the on-chip incorporation of (i) Program ROM (4 K Bytes) (ii) Data RAM (128 Bytes) (iii) Special Function Registers (iv) 32 bit programmable I/O Port (v) UART (Universal Asynchronous Receiver Transmitter) for series data input and output (vi) Two programmable Timers and Counters (vii) Two external interrupts with priority and masking. The software features available in 8051 that are not found in the microprocessors are as follows: (a) Bit manipulation (b) Single instruction multiplication (c) Individual program and data memory (d) Four banks of eight temporary registers each and (e) Direct, indirect, paged and relative addressing modes The main advantage of the 8031 is its low cost and the possibility of using it with popular EPROM’s externally. Though the primary 8051 has built-in ROM, this will become an advantage only in volume production, since mask programming of the ROM has to be done at the time of manufacturing itself. The 8751 is ideally suited for single chip systems, since it has a self contained EPROM. Though it is costlier, the number of ports available will be a total of 32 bits. This is in contrast to the 8031 system wherein the number of port bits is reduced to 16 as the rest of the port lines are used for accessing the external ROM. Addition of external programmable I/O ports such as 8255 to the 8031 can, however, enhance the capacity of the system to more than 40 lines of programmable I/O ports. A schematic block diagram of the 8051 microcontroller is shown in Fig. 25.20. The microcontroller comprises a 4 K Byte ROM, 128 Byte RAM, Two Timers/Counters TIMER0 and TIMER1, four 8-bit I/O ports, serial port and two interrupt controls. The program counter is 16-bit wide and provides addressing capability up to 64 K Bytes of memory. Two types of memories can be separately addressed. These are program memory (64 K) and Data memory (64 K). In 8051 and 8751, the___ lower 4 K of the program memory is filled by internal ROM and EPROM respectively. By tying the EA pin high, the processor can be forced to fetch data from the internal ROM/EPROM for program memory addresses 0 through 4 K. Bus expansion for accessing program memory beyond 4 K is automatic since external instruction fetch occurs automatically when the program counter increases ___ above 4095. If the EA point is tied low, all program memory fetches are from external memory.

The data memory is external and can be as wide as 64 K Bytes. When a “MOVX” instruction is executed, external data memory is automatically accessed. One of the important features of the 8051 is the incorporation of the on-chip data RAM and special function registers. The data RAM is 128 Byte wide and a cell can be directly addressed by a single byte address. The internal structure of the RAM and special function registers is shown in Fig 25.21. The RAM cells with addresses in the range 00 H to 7F H can be addressed by direct address. However, the cells with address 00 H to 1F H also function as a set of four register banks with eight registers in each bank. Thus Bank-0 registers R0 to R7 have addresses 00 H to 07 H; Bank-1 registers R0 to R7 have addresses 08 H to 0F H and so on. The memory cells 20 H to 2F H have the special feature by which provision is made for bit addressing in this region. One can set or reset a bit by direct addressing of the bit cell, whose address is from 00 H to 7F H. The bit cells 00 H to 07 H forms the RAM Byte cell with address 20H. The special function registers are also part of the internal RAM but with specific addresses as shown in Fig. 25.21. All of these have addresses in the range 80 H to FF H. All of the 128 Bytes from 80 H to FF H are not used, and the user has no access for the unused locations. Some of the locations in this region of the RAM also have the facility for “Bit Addressing”. The functions of these registers are detailed below: ACC

Accumulator. This is the most active register in the microcontroller.

B

B register. This register is mainly used in multiplication and division.

PSW

Program Status Word. The bits of this register serve as flags and for switching various banks of the registers R0 to R7.

Byte address

Byte address

Bit address

7F

Bit addressable locations

General purpose RAM 30 2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20 1F 18 17 10 0F 08 07 00

F7 F6 F5 F4 F3 F2 F1 F0 B

E0

E7 E6 E5 E4 E3 E2 E1 E0 ACC

D0

D7 D6 D5 D4 D3 D2 - D0 PSW

B8 7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07

7E 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06

7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05

7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 14 0C 04

7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03

7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02

Bank 3 Bank 2 Bank 1 Default register bank for R0-R7 RAM

79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01

78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00

Bit address

FF F0

-

-

- BC BB BA B9 B8 IP

B0

B7 B6 B5 B4 B3 B2 B1 B0 P3

A8

AF -

A0

A7 A6 A5 A4 A5 A5 A5 A5 P2

99 98

not bit addressable SBUF 9F 9E 9D 9C 9B 9A 99 98 SCON

90

97 96 95 94 93 92 91 90 P1

8D 8C 8B 8A 89 88 87

TH1 not bit addressable TH0 not bit addressable TL1 not bit addressable TL0 not bit addressable not bit addressable TMOD 8F 8E 8D 8C 8B 8A 89 88 TCON PCON not bit addressable

83 82 81 80

not bit addressable not bit addressable not bit addressable 87 86 85 84 83 82 81 80

- AC AB AA A9 A8 IE

DPH DPL SP P0

Special function registers

DPTR

Data Pointer. This is a 16 bit address, used for indirect addressing of external memory. DPTR consists of DPH and DPL.

P0-P3

The microcontroller supports four 8-bit ports viz., P0, P1, P2 and P3. Each bit’s contents pass through a buffer to the outgoing line. Because of the priority given to logic “0”, all input ports should be initialized to logic “1” before reading a data through the port. When external memories are used, the lines of ports P0 & P2 serve as address and data buses.

IP/IE

Interrupt priority control, Interrupt enable control.

TMOD/TCON These registers are used in the control of timers and the mode in which they are used. The 8051 has two timers that can also be used as counters. Each timer consists of two bytes TH and TL. TH0/TL0 TH1/TL1

These registers hold the data in the timers, and consist of higher and lower bytes.

SCON

Control of serial communications. The 8051 has two lines which allow transmission and reception. SCON serves as the communication control.

SBUF

Serial data buffer. This buffer is used to store data that is transmitted serially.

PCON

Power control. Some of the bits of this register enable switching of the CPU and disconnection of it from the clock system, even to the point of stopping its functioning. This switching is done by software.

The MCS-96 family of microcontrollers has been optimized for modern control applications which require high speed calculations and fast I/O operations. It is a 16-bit microcontroller with a number of dedicated I/O systems and a complete set of 16-bit arithmetic operations. Because of specific requirements of high speed and performance its architecture is different from MCS-51. The basic features of MCS-96 are: • 16-bit register based CPU • 8K Bytes of ROM • 256 Bytes of RAM and 232 Bytes of Special Function Registers • Hardware multiply and divide instructions • Six addressing modes • High speed I/O with 4 dedicated and 4 programmable I/O lines • 10-bit A/D converter • Full duplex serial port • 40 I/O pins available • Two, 16-bit Timers / Counters • Watch Dog timer to recover from errors • Programmable 8-source, 2-priority level interrupt system • Available in 48 pin DIP or 68 pin Flat pack The 8096 is used for sophisticated real time control and used in high-end instruments and instrumentation. The CPU has a 16-bit ALU. Since the ALU does not have an accumulator, the location in the register file are used as source and destination. Hence the ALU unit of 8096 microcontroller is called RALU (Register Arithmetic and Logic Unit). Out of 64K memory, the first 256 bytes can be used as Data/Program memory which is a feature of Princeton architecture. When accessed as data memory (internal memory), the first 24 bytes correspond to SFRs (Special Function Registers) and the remaining 232 bytes can be used as general purpose RAM. The upper 16 bytes of the register file has a power down mode, so that data in it can be saved on power down. When accessed as program memory (External memory), it is reserved for use by Intel development systems. The internal program memory of 8K Bytes is from 2080 H to 3FFF H. The external memory can be expanded by using the ports P3 and P4 for the multiplexed Address and Data bus. For the reconstruction of ports P3 and P4, the locations 1FFF H to 2000 H has been kept. The vectored interrupt lie

between 2000 H and 2011 H. Therefore, the memory 00 H to FF H and 1FFE H to 2011 H has a special purpose. On reset, the PC points to the location 2080H. interrupt, serial port interrupt, software time interrupt, the high speed input interrupt, the high speed output interrupt, the high speed data available interrupt, the A/D conversion complete interrupt and the time over flow interrupt. These interrupts can be masked, and can be assigned a priority. These interrupts are vectored. There are two 16-bit timers, T1 and T2. The timer T1 is used to synchronize events to real time. It is clocked once every 8 state times. T2 can be clocked externally and synchronize events to external occurrences. Both the timers can cause the timer interrupt and also set I/O flags. These are four lines (HSI 0 to HSI 3) can be used to record events with respect to timer Tl. Up to 8 events can be recorded in a FIFO RAM, which holds the time value from timer as well as the state of HSI inputs at that instant. The HSI interrupt indicates that either the FIFO is full or the holding register is loaded. These are used to trigger events at specific times. These reduce the CPU overheads. These events could be to start A/D conversion, reset the timer T2, set software flags, generate interrupts or switch the 6 output lines (HSO 0 to HSO 5). The HSO 4 and HSO 5 share the same pins with HSI 2 and HSI 3. Up to 8 events can be kept pending at any time. This unit is controlled by a content addressable memory (CAM) which has 8 location and stores the time for taking action, the type of action and whether timer T1 or T2 is used as reference. Four software timers can be programmed through HSO to provide interrupts at predetermined times. Anyone of the analog inputs (ACH 0 to ACH 7) can be sampled and converted to a 10-bit digital value. The analog inputs share the pins with Port P0. The results are put in the 2-byte A/D result register. The Digital to Analog conversion is available in the form of a PWM output. The output waveform is a pulse with a frequency of 256 state times. The width of the pulse is the analog equivalent of an 8-bit digital value. The PWM output shares the same pin as port P2 bit 5. The serial port is similar to that of MCS-51. It is a full duplex port with four modes of operation. The serial port shares pins with port P2, bits 0 and 1. In any one of the modes of operation, it can be used for serial I/O using shift registers and latches. There are five ports. Some ports are inputs only, some ports are outputs only, while some are bidirectional and some share alternate functions. Port 0 is an input port and also be used for A/D converter inputs. Port 1 is bidirectional. Port 2 has input, output as well as bidirectional pins. Port 3 and 4 are bidirectional ports and can be used for expanding the memory. If the software fails to reset the watch dog every 64 K states, the 8096 is reset. This is a graceful method of recovering from software failure.

Any computer system has essentially three important parts, namely, input device, central processing device, and output device. The central processing unit (CPU) itself has three parts, namely, memory unit, control unit, and arithmetic logic unit (ALU). These three units along with the input and output devices form the five important components of any computer system. In addition to the above, computers also employ secondary storage devices (or auxiliary storage or backing storage), which are used for holding data or instructions on a long term basis. Figure 25.22 shows a computer system with peripheral devices.

The input devices are used to transfer the information into the memory unit of the computer. Information from the memory can be transferred to the ALU where comparisons or calculations are done and the results are sent back to the memory unit. Thus, the memory unit is used to store the set of instructions that determines the operations to be carried out on a set of data as well as the data on which these operations are performed. The memory unit is also called the main memory or the immediate access store. It accepts instructions held in store, interprets these instructions and process them for execution by appropriate parts of the system in the correct sequence. The control unit ensures that, according to the stored instructions, the right operation is done on the right data at the right time. The results that are stored in the memory can be transformed into a form that can be understood by us by means of an output device.

Probable Values of General Physical Constants Constant

Symbol

Value

Electronic charge

q

1.602 × 10 – 19 C

1 electron volt

eV

1.602 × 10 – 19 Joules

Electronic mass

m

9.109 × 10 – 31 kg

q/m

1.759 × 1011 C/kg

Planck’s constant

h

6.626 × 10 – 34 J-s

Boltzmann constant

k

8.620 × 10–5 eV/°K

Velocity of light

c

2.998 × 108 m/s

Acceleration of gravity

g

9.807 m/s2

Permeability of free space

m0

1.257 × 10 – 6 H/m

Permittivity of free space

e0

8.854 × 10 – 12 F/m

1 joule

J

6.25 × 1018 eV

Ratio of charge to mass of an electron

Conversion Factors and Prefixes Constant

Value

1 ampere (A)

1 C/s

1 angstrom unit (Å)

10

– 10

m = 10 – 8 cm

1 coulomb (C)

1 A–s

1 farad (F)

1 C/V

1 henry (H)

1 V–s/A

1 hertz (Hz)

1 cycle/s

1 lumen

0.0016 W (at 0.55 m m) 10 – 3 inch = 25 m m

1 mil

1 m m = 10 – 6 m

1 micron

1 kg = m/s2

1 newton (N) 1 Volt (V)

1 W/A

1 watt (W)

1 J/s

1 weber (Wb)

1 V–s 2

1 weber per square meter (Wb/m )

104 gauss

1 tesla (T)

1 Wb/m2

1’s and 2’s Complements 961 1’s Complement Subtraction 961 2’s Complement Subtraction 962 9’s Complement 963 10’s Complement 965 A/D Converter 928, 1009, 1048 Alphanumeric Displays 902 Ammeter 923, 945 Analysis of a transistor amplifier circuit using hparameters 280 Current Gain or Current Amplification, 280 Input Impedance, 281 Voltage Gain or Voltage Amplification Factor, 282 Output Admittance, 282 Voltage Amplification taking into Account the Resistance of the Source 283 Current Amplification taking into Account the Source Resistance 284 Operating Power Gain, AP 284 Comparison of Transistor Amplifier Configurations 286 Analysis of CB amplifier using the approximate model 294 Analysis of CC amplifier using the approximate model 292 Applications of JFET 229 Armstrong Oscillator 591, 592 Atomic Energy Level Diagram 5 Atomic Structure 1 Avalanche Photo Diode (APD) 155 Backward Diode 138, Bandwidth with feedback 814 Basic Concept of Feedback 532 Bias Compensation 191, 214, 215-217 Diode Compensation 215 Thermistor Compensation 215 Sensistor Compensation 215

Bias Stability 184, 336, 337 Need for Biasing 184 Thermal Runaway 184 Stability Factor (S) 190 Biasing the FET 238 Biasing the MOSFET 241 Biasing of Enhancement MOSFET 241 Biasing of Depletion MOSFET 242 Binary Arithmetic 958 Binary Addition 958 Binary Subtraction 958 Binary Multiplication 959 Binary Division 960 Binary coded Decimal 928, 966, 1009 BCD Addition 967 BJT Amplifiers 302, 307, 358 Classification of Amplifiers 302 Blocking Oscillator 690, 703 Bode Plot Analysis 427 Bohr Atom Model 3 Bohr’s Postulates 3 Critical Potentials 4 Spectral Series of Hydrogen Atom 4 Boolean Algebra 968, 971, 985 Boolean Addition and Multiplication 968 De Morgan’s Theorems 970 Algebraic Simplification of Logical Expressions 971 Bootstrapped Darlington amplifier 412 Bootstrapped emitter follower 411, 412 Bootstrapping 411-413 Breakdown in PN junction diodes 127 Breakdown in Transistors 181 Avalanche Breakdown and Multiplication 181 Reach-Through or Punch-Through 181

Capacitive Transducer 870, 871 Capacitors 16, 23, 25-41, 424 Fixed Capacitors 25 Variable Capacitors 32 Dissipation Factor 29 Connecting Capacitors 39 Characteristics and Applications 16 Carrier Concentration in Intrinsic Semiconductor 78 Carrier Life Time 93, 94, 268 Cascode amplifier 373, 413-415, 446 Cathode Ray Oscilloscope (CRO) 915 Vertical and Horizontal Voltage Amplifiers 915 Power Supply Circuits 916 Cathode Ray Tube (CRT) 916 Special Oscilloscopes 917 Applications of CRO 920 Channel length Modulation 231, 232, 245 Characteristic Parameters of the JFET 222 Charge transfer devices (CTDs) 251 Charge-Coupled Device (CCD) 251 Bucket Brigade Device (BBD) 253 Charged Particles 1, 47, 66 Choice of Transistor Configuration in Cascade Amplifier 385 Clamper 661, 753, 851 Clapp Oscillator 590 Class A Large Signal Amplifiers 467 Class B Amplifier 302, 466, 467, 476 Class D Amplifier 486, 487, 488 Class S Amplifier 487 Classification Based on Biasing Condition 466 Classification of Oscillators 578 Classification of Semiconductors 72 CLC filter 752 Clipper 648-652 Closed-loop op-amp Configurations 831 Inverting Amplifier 838 Noninverting Amplifier 833 Colpitts Oscillator 585, 587-589, 614 Combinational Logic Design 985 Common Mode Rejection Ratio (CMRR) 351, 357, 823 Comparator 488, 660, 684, 857 Comparison Between Electric and Magnetic Deflection Systems 69 Comparison of JFET and BJT 228 Comparison of MOSFET with JFET 233 Comparison of N- with P- Channel FETs 235 Comparison of N- with P-Channel MOSFETs 235 Complementary Symmetry (Class B) Push-Pull Amplifier 480 Conditions for Oscillation (Barkhausen Criterion) 579 Mechanism for Start of Oscillations 579 Conductivity of Semiconductor 75 Conductivity 10, 11, 12, 73 Construction of A Monolithic Bipolar Transistor 793 Epitaxial Growth 786 Oxidation 788

Photolithography 788 Isolation Diffusion 793 Base Diffusion 793 Emitter Diffusion 793 Contact Mask 793 Metallization 792 Passivation 797 Construction of N-channel JFET 219 Continuity Equation 95, 96 Cross over distortion 479, 480 Crystal Oscillators 609, 613 Current series, Current shunt feedback amplifier 535 A/D and D/A Converter Circuits 1009 Digital-to-Analog Converters 1009 Analog-to-Digital converters 865, 1011 Darlington amplifier 407, 411, 412 d.c. Voltmeter 925, 926 Defocusing 69, 70 Depletion MOSFET 229, 231, 340 Effect of Channel Length Modulation 231 Temperature Effects 233 DIAC (Diode a.c. switch) 257, 267 Different Coupling Schemes used in Amplifiers 373 Differential Amplifiers 348, 351, 361 Differential Amplifier Using Operational Amplifier 349 Differential Amplifiers Using BJT 351 Transfer Characteristics of a Differential Amplifier 360 Differential Amplifier using FET 361 Diffusion (or Storage) Capacitance (CD) 120, 436 Digital Multimeter (DMM) 928, 933 Digital Voltmeter 928, 933 Diode as a Circuit Element 128 Load Line Concept 129 Piecewise Linear Diode Model 131 PN Diode Applications 132 Diode Clippers 648 Diode Comparator 660 Diode Current Equation 110, 120, 123 Diode Resistance 125, 726, 728, 732, 734 Direct Coupled (d.c.) Amplifiers 404 Distortion in Amplifiers 332 Distortion Meter 949-951 Drift and Diffusion Currents 91 Einstein Relationship for Semiconductor 93 Early effect 165, 167, 182 Ebers–Moll Model 183 Effect of Cascading Double Tuned Amplifiers on Bandwidth 513 Effect of Cascading Single Tuned Amplifiers on Bandwidth 512 Effect of Coupling Capacitor CC on Low Frequency Response 434 Effect of Temperature on PN Junction Diodes 122

Effects of Negative Feedback 537 Stabilisation of Gain 537 Decrease Distortion 533 Decreased Noise 536 Types of Negative Feedback Connections 537 Voltage-Series Feedback 535 Voltage-Shunt Feedback 535 Current-Series Feedback 535 Current-Shunt Feedback 535 Efficiency of Class A Amplifiers 473 Efficiency of Class B Amplifier 476 Einstein’s Relationship 93 Electrical Strain Gauges 873 Unbonded Strain Gauge 873 Bonded Wire Strain Gauge 873 Electron Emission from Metals 13 Types of Electron Emission 14 Electronic Configuration of Elements 6 Electrostatic Deflection in Cathode Ray Tube 62 Emitter Follower 288, 306, 324-326, Energy Band structure of Open Circuited PN Junction 105 Energy Band Structures and Conduction in Insulators, Semiconductors and Metals 10 Insulator 8 Metal 10 Semiconductor 1 Energy Meter 944 Energy-Band theory of crystals 8 Enhancement MOSFET 229, 230, 807 Equivalent Circuit of op-amp 828 Expression for Saturation Drain Current 226 Extrinsic 12, 73, 84, 90 Fabrication of Field Effect Transistors 804 Junction Field Effect Transistor (JFET) 806 Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) 807 Complementary MOSFET (CMOS) 809 BiFET Devices 810 FET Amplifiers 229, 340, 373 Common Source (CS) Amplifier 340 Common Drain (CD) Amplifier 342 Common Gate (CG) Amplifier 344 FET Model at High Frequency 453 The Common Source (CS) Amplifier at High Frequencies. 453 The Common-Drain Amplifier at High Frequencies 456 Fiber Optics 909 Forbidden energy gap 9-11 Force in Magnetic Field 55 Force, Field Intensity, Potential, and Energy 47 Franklin Oscillator 591 Free Running Blocking Oscillator 703, 704 Astable Blocking Oscillator with Base-Timing (Diode Controlled) 703

Push-Pull Astable Blocking Oscillator with Emitter Timing (RC controlled) 705 Frequency Control using Core Saturation 707 Frequency Meter 942 Frequency range of RC and LC oscillators 612 Frequency response and compensation 836 Internal Compensation 837 External Compensation 837 Frequency Response of FET Amplifier 457 Frequency Response of Multistage Amplifiers 458 Frequency Stability of Oscillator 613 Gain Margin 575 Gallium Arsenide Devices 813, 815, 897 N-type material 80 P-type material 74 Energy band structure 9 GaAs technology 814 GaAs Metal semiconductor FET (MESFET) 815 Fabrication of GaAs Depletion-mode MESFET 815 Gate turn-off (GTO) Thyristors 268 Basic Structure of GTO 268 Switching Characteristics 124 Gate Turn-On 269 Gate Turn-Off 268 Current–Voltage Characteristics 103 Advantages of GTO 270 Disadvantages of GTO 271 Applications of GTO 271 General Analysis of Cascade Amplifier 376 General Form of an LC Oscillator 580 General shape of Frequency Response of Amplifiers 422 Gunn Diode 150-152 Gunn Effect 150 Hall Effect 869, 878, 879 Handling Precautions for MOSFET 233 Current–Voltage Relationships of the N-channel and P-channel MOSFETs 234 Hartley Oscillator 582-585, 612, 614 Harmonic distortion 332, 470, 471 Heat sink 190, 489, 491 Hazeltine neutralization 522, 523 High Frequency p Model for a Transistor 387 CE Short-circuit Current Gain 440 b Cut-Off Frequency 442 a Cut-Off Frequency 442 Gain-Bandwidth Product 397 High Frequency Current Gain with Resistive Load 444 Higher-Order Harmonic Generation 470 Hydrogen atom 2-5 Hysteresis 43, 683, 871 Ideal operational amplifier 820 Ideal Voltage Transfer Curve 829 Impatt Diode 152-154

Inductive Transducer 871 Inductors 16, 582, 804, 938 Fixed Inductors 42 Variable Inductors 42 Inductive Reactance 43 Energy Stored in a Magnetic Field 43 Q of an inductor 44 Mutual coupled coils 44 Connecting Inductors 45 Integrated Resistors 801 Intrinsic 11, 72, 133, 690, 887 Introduction to Computers 1050 Introduction to Microprocessors 1033 8085A Microprocessor 1036 6800 Microprocessor 1036 8086 and 8088 Microprocessors 1036 68000 Microprocessor 1043 Microcontrollers 1043 Ionisation potential 3, 4 Junction Diode Switching Characteristics 124 Karnaugh Map Representation of Logical Functions 986 Large Signal Tuned Amplifiers 494, 516 Efficiency of Class-C Tuned Amplifier 518 Applications of Class-C Tuned Amplifier 519 Large signal, d.c., and Small Signal CE values of Current Gain 171 Lascr (Light Activated SCR) 257, 265 Laser Diode 156, 157 LCD Panels 903, 906 Light Emitters 815, 896, 902 Light Emitting Diode (LED) 896 Infrared Emitters 897 Linear Mode Power Supply 720, 721 Requirements of Linear Mode Power Supply 721 Rectifiers 72 Filters 23 Voltage Regulators 132 Linear Variable Differential Transformer (LVDT) 869, 871 Linearization Through Adjustment of Driving Waveform 716 Line regulation 728, 755 Liquid Crystal Display (LCD) 904, 914, 934 Load regulation 745, 755 Loaded Q 496 Logic Families 1013, 1020 Diode–Transistor Logic (DTL) 1014 Transistor–Transistor Logic (TTL) 799, 1014 TTL Sub-families 1015 Emitter-Coupled Logic (ECL) 1016 Integrated Injection Logic (IIL) Circuits 1016 Metal Oxide Semiconductor (MOS) Circuits 1018 Comparison of logic families 1020

Logic Gates 784, 977, 980, 985, 991 OR Gate 808, 977 AND Gate 220, 978 NOT Gate (Inverter) 979 NAND Gate 980 NOR Gate 981 Low Frequency Response of Transistor Amplifier 430 Effect of Emitter Bypass Capacitor (CE) on Low Frequency Response 430 Magnetic Deflection in Cathode ray Tube 66 Manufacturing Processes of Monolithic ICs 785 Silicon Wafer Preparation 785 Epitaxial Growth 785 Oxidation 785 Photolithography 785 Diffusion 93, 785 Metallization 785 Circuit Probing 785 Scribing and Separating into Chips 785 Mounting and Packaging 785 Encapsulation 785 Mass-Action Law 83, 84, 90, 106 Measurement of R, L, C and Q 934 Measurement of Resistance 933, 934 Measurement of Inductance 934, 936 Measurement of Capacitance 934, 937 Measurement of Q 938 Metal Oxide Semiconductor Field Effect Transistor (MOSFET) 807 Metal–semiconductor Junctions 104, 141, 146 Structure of Metal–Semiconductor Junction 141 Energy Band Diagram 106 Thermal Equilibrium 77 Forward and Reverse Bias 113 Schottky Diode 145 Ohmic Contacts 104 Method of identifying feedback topology and feedback factor 553 Methods of Transistor Biasing 191 Fixed Bias or Base Resistor Method 191 Collector-to-Base Bias or Biasing with Feedback Resistor 196 Self Bias, or Emitter Bias 200 Common Base Stability 214 Advantage of Self Bias (Voltage Divider Bias) Over Other Types of Biasing 214 Miller Oscillator 612 Miller’s theorem 333-335, 387, 411 Mobility 11-13, 75, 76, 88-91 Monolithic Capacitors 28, 804 Monolithic Diodes 801 MOSFET Power Amplifiers 448 Motion in Magnetic Field 55 Multivibrators 618, 658, 663, 681, 999 Collector Coupled Astable Multivibrator 663

Monostable Multivibrator 663 Bistable Multivibrator 677 Negative-Resistance Oscillators 578 Neutralization 521-524 Nixie Tube 900-902 Noise 139, 145, 146, 149 Number System 953, 955, 956, 958 Binary Numbers 653 Decimal–Binary Conversion 954 Octal Numbers 955 Octal-Binary Conversions 956 Hexadecimal Numbers 956 Hexadecimal–Binary Conversions 957 Hexadecimal–Octal Conversions 958 Nyquist criterion 574, 575 Ohmmeter 930-932 Op-Amp Applications 838 Sign Changer (Phase Inverter) 838 Scale Changer (Inverting Amplifier) 838 Voltage Follower 826, 838 Adder or Summing Amplifier 839 Subtractor 840 Adder-Subtractor 841 Instrumentation Amplifier 843 Integrator 629, 847 Differentiator 848 Precision Rectifier 850 Active Filters 851 Comparators 857 Open-loop op-amp configurations 829 Open-Loop Differential Amplifier 829 Inverting Amplifier 830, 832 Noninverting Amplifier 830 Limitations of Open-Loop OP-Amp Configurations 831 Operation of N-Channel JFET 220 Operation of NPN Transistor 160 Operation of PNP Transistor 161 Operational Amplifier parameters 823 Operational amplifier stages 821 Input Stage 348 Intermediate Stage 398 Level Shifter Stage 822 Output Stage 381 Optocoupler 907, 908 Oscillation Transducer 872, Oscillators Using FET 614 Parallel Electric and Magnetic Fields 58 Perpendicular Electric and Magnetic Fields 59, 60, 61 Phase Inverters 483 Phase Margin 575 Photoconductive Sensors 885 Bulk Type Photoresistor or Photoconductive Cell 887 Junction Type Photoconductive Cell 889

Photoelectric Transducer 881 Photoemissive sensors 893 Vacuum Phototube 893 Gas Filled Phototube 893 Photomultiplier 891 Photovoltaic sensors 891 Photovoltaic Cell 891 Solar Cell 891, 893 Pierce Crystal Oscillator 612, 614, 616 Piezoelectric Transducer 869, 880, 881 Pin Diode 154 PIN Photodiode 155, 908, 909 Plasma Display Panels 906 PNP Transistors 279, 681, 797, 798, 806 Comparison of Monolithic NPN and PNP Transistors 798 PNPN diode (Shockley diode) 257 Point-contact Diode 140 Potentiometric Transducer 872, 873 Power amplifier 302, 466, 471 Power Meter 945 Practical Semiconductor Materials 11, 13 Properties of Intrinsic Semiconductors 89 Pulse Transformers 690, 694 Transformer and its Equivalent Circuits 694 Complete Equivalent Circuit 698 Response of a Pulse Transformer 698 Applications of Pulse Transformer 703 Push-Pull Amplifier (Class-B) 481 Q-Factor 28, 494, 495, 528, 611 Q-factor of a Capacitor 495 Unloaded Q and Loaded Q 496 Quantitative Theory of PN Diode Currents 107 RC Coupled Amplifier 334-376, 386 RC Oscillators 593 Recent Trends in IC Technology 817 Rectifier Circuits using SCR 260 SCR Half Wave Rectifier 261 SCR Full Wave Rectifier 263 SCR Bridge Rectifier 264 Resistance Thermometer 869, 875, 876 Resistors 16-19, 21 Fixed Resistors 16 Variable Resistors 16 Tolerance 21 Colour Coding of Resistors 22 Connecting Resistors 23 Ripple factor 722, 727, 729, 731 RF Amplifiers 229, 460, 522 Schmitt Trigger 682-685, 944 Schottky Barrier Diode 145, 779, 799, 800 Schottky Transistor 800 SCR (Silicon Controlled Rectifier) 258

Second Harmonic Distortion 333, 468, 470 Semiconductor Memories 1026 Memory Addressing 1026 ROMs, PROMs and EPROMs 1028 Random Access Memory (RAM) 1031 Dynamic Random Access Memories (DRAMs) 1031 Programmable Logic Arrays (PLAs) 1033 Sequential Circuits 985, 998, 999 Flip-Flops 784, 799 Shift Registers 251 Counters 679, 1004 Asynchronous Counters 1005 Synchronous Counters 1007 Decade Counters 1008 Simplified CE Hybrid Model 288 Generalised Approximate Model 289 Common Emitter Amplifier with Emitter Resistor 311 Single Stage Amplifiers 303 Common Emitter Amplifier 184 Common Collector (CC) Amplifier 305 Common Base (CB) Amplifier 306 Slope of the Transfer Characteristic at IDSS 227 Small Signal Analysis of Single Stage BJT amplifiers 307 CE Amplifier with Fixed Bias 307 CE Amplifier with Unbypassed Emitter Resistor 313 CE Amplifier with Voltage-Divider Bias 317 CB Amplifier 218 CC Amplifier (or) Emitter Follower 324 Cascode Amplifier 373 Darlington Connection 407 Small Signal Tuned Amplifiers 494, 497, 516, 517 Capacitance Coupled Single Tuned Amplifier 497 Double Tuned Amplifier 503 Some Common Combinational Circuits 989 Half Adder 989 Full Adder 989 Half Subtracter 991 Full Subtracter 991 Multiplexer 992 Demultiplexer 993 Encoder 890 Decoder 994 Code Converters 994 Spectral response of human eye 884, 886 Spectrum Analyser 947, 948 Speed up Capacitor 646, 647, 672, 674 Stability factor 190, 191, 192, 194 Stability of Feedback Amplifier 194-198, 201 Stability of Tuned Amplifiers 519 Stagger Tuned Amplifiers 497, 514, 515 Step Recovery Diode 139, 140 Switched Mode Power Supply (SMPS) 720, 772 The “re” Model of Transistor 298 Analysis of CE Amplifier using re Model 301

The FET Small-Signal Model 346 Comparison of FET Model with h-Parameter Model of BJT 347 High Frequency Model of FET taking the Various Capacitors into Account 348 The Hybrid model for two-port network 277 Transistor Hybrid Model 277 Theory of PN Junction Diode 98 PN Junction Diode in Equilibrium with no Applied Voltage 98 Under forward Bias Condition 102 Under Reverse Bias Condition 102 PN junction Diode as Rectifier 104 Limiting Values of PN Junction Diode 104 Thermal Stability and Heat Sink 489 Thermistor 215, 869, 876, 877 Thermionic Emission 14 Thermocouple 869, 877, 1011 Thin and Thick Film Technology 811 Thin Film Fabrication 811 Thick Film Fabrication 812 Thyristor Protection 271 (a) di/dt Protection 271 (b) dv/dt Protection 272 Snubber Circuit 272 Thyristor Ratings 260 Time Base Circuits 713 Voltage–Time Base Circuit 713 Current–Time Base Circuit 714 Time Meter 943 Transformation of a Hypothetical Electronic Circuit Into Monolithic Form 804 Transformer Coupled Amplifier 196, 398, 399, 400 Transformer Coupled Class a Audio Power Amplifier 471 Transconductance 222, 223, 225 Transient Response 428, 429, 574 Transistor as an Amplifier 171 Transistor Biasing 159, 160, 191 Transistor Transistor logic (TTL) 799, 1014 Transition or Space charge (or Depletion Region) Capacitance 116 TRIAC (Triode AC Switch) 265 Triggered Blocking Oscillator 708-710 Monostable Blocking Oscillator with Base Timing 708 Monostable Blocking Oscillator with Emitter Timing 710 Triggering Methods For Bistasle Multivibrators 681 Unsymmetrical Triggering 559 Symmetrical Triggering 559 Tuned Collector Oscillator 592, 703 Tunnel Diode 147-149, 614 Equivalent Circuit 24 Twin-T-Oscillator 607 Two-Dimensional Motion of Electron 50 Two-Port Devices and Network Parameters 274

Z-Parameters or Impedance Parameters 274 Y-Parameters or Admittance Parameters 274 Hybrid parameters or h-Parameters 165 Notations Used in Transistor Circuits 276 Types of Configuration 163 CB Configuration 162 CE Configuration 162 CC Configuration 163 Comparison 26 Current Amplification Factor 170 UJT (Unijunction Transistor) Relaxation Oscillator 690 Unloaded Q 496 Use of JFET as Voltage-Variable Resistor 235 Vacuum Tube voltmeter (VTVM) 927 VTVM using Vacuum Tube Diode 927 VTVM using Triodes 927 Varactor Diode 138, 139

Variation in Semiconductor Parameters with Temperature 89 Video Amplifiers 460 Factors Influencing Design of a Video Amplifier 461 Voltage divider bias 200, 209, 211, 214 Voltage series, Voltage shunt feedback amplifier 571 Watt Meter 945, 946 Electrodynamometer Watt Meter 946 Waveform Shaping Circuits 618 RC Circuits 618 RL Circuits 639 Storage, Delay and Calculation of Transistor Switching Times 645 Wien-Bridge Oscillator 605-607 Zener Diode 128, 632, 135 Avalanche Breakdown 127 Zener Breakdown 127 Applications 127