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Table of contents :
Title
Contents
1 INTRODUCTION
2 DIODES, CHARACTERISTICS, AND APPLICATIONS
3 RECTIFIERS AND FILTERS
4 TRANSISTOR CHARACTERISTICS
5 TRANSISTOR BIASING AND THERMAL STABILIZATION
6 SMALLSIGNAL, LOWFREQUENCY BJT AMPLIFIERS
7 FET CHARACTERISTICS, BIASING, AND FET AMPLIFIERS
8 MULTISTAGE AMPLIFIERS
9 FEEDBACK AMPLIFIERS
10 OSCILLATORS
11 POWER AMPLIFIERS
12 HIGHFREQUENCY TRANSISTOR AND FET AMPLIFIERS
13 TUNED AMPLIFIERS
14 OPERATION ALAMPLIFIERS
15 APPLICATIONS OF OPAMP
16 ACTIVE FILTERS
17 VOLTAGE REGULATORS
18 MULTIVIBRATORS
19 TIMEBASE GENERATORS
20 INTEGRATED CIRCUITS
21 555 TIMER AND APPLICATIONS
22 SPECIAL ELECTRONIC DEVICES, OPTOELECTRONIC DEVICES, AND MEASURING INSTRUMENTS
23 DIGITAL ELECTRONICS
24 MICROCOMPUTERS AND MICROPROCESSORS
APPENDIX A
APPENDIX B
APPENDIX C
INDEX
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Electronic Devices and Circuits
About the Authors K Venkata Rao obtained his BE (Telecommunications) and ME (Control Systems) degrees from Andhra University, Visakhapatnam, and PhD degree from University of Roorkee, Roorkee (now IIT Roorkee). He retired as Professor from Andhra University College of Engineering and has over 45 years of teaching and 25 years of research experience. He has published and presented 32 research articles in reputed international/national journals and conference proceedings respectively. He has received the S K Mitra Memorial Award for the best researchoriented paper published in JIETE in 1985. He is presently Director, Chaitanya Engineering College, Vishakhapatnam. He is a Life Fellow, IETE. K Rama Sudha received her BE degree in Electrical and Electronics Engineering from GITAM University (formerly known as GITAM college, Andhra University), in 1991. She obtained her ME degree in Power Systems 1994, and was awarded her doctorate in Electrical Engineering in 2006 by Andhra University. She has published and presented over 62 research articles in reputed international/national journals and conference proceedings. She has 19 years of teaching experience and 7 years of research experience. During 1994–2006, she worked with GITAM Engineering College and presently, she is working as Professor and Head in the Department of Electrical Engineering, AUCE(W), Andhra University, Visakhapatnam, India. She is a member of ISTE, IEEE and WIE.
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Electronic Devices and Circuits
K Venkata Rao Former Professor (Dept. of ECE), Andhra University Director, PG Programme Chaitanya Engineering College Visakhapatnam, Andhra Pradesh
K Rama Sudha Professor and Head Department of Electrical Engineering College of Engineering for Women Andhra University Visakhapatnam, Andhra Pradesh
McGraw Hill Education (India) Private Limited NEW DELHI McGraw Hill Education Offices New Delhi New York St Louis San Francisco Auckland Bogotá Caracas Kuala Lumpur Lisbon London Madrid Mexico City Milan Montreal San Juan Santiago Singapore Sydney Tokyo Toronto
McGraw Hill Education (India) Private Limited Published by McGraw Hill Education (India) Private Limited P24, Green Park Extension, New Delhi 110 016 Visit us at: www.mheducation.co.in Electronic Devices and Circuits Copyright © 2015 by McGraw Hill Education (India) Private Limited. No part of this publication may be reproduced or distributed in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise or stored in a database or retrieval system without the prior written permission of the publishers. The program listings (if any) may be entered, stored and executed in a computer system, but they may not be reproduced for publication. This edition can be exported from India only by the publishers, McGraw Hill Education (India) Private Limited. Print Edition: ISBN (13): 9789332901155 ISBN (10): 9332901155 eBook Edition: ISBN (13): 9789339219635 ISBN (10): 9339219635 Managing Director: Kaushik Bellani Head—Products (Higher Education and Professional): Vibha Mahajan Assistant Sponsoring Editor: Koyel Ghosh Senior Editorial Researcher: Sachin Kumar Manager—Production Systems: Satinder S Baveja Assistant Manager—Editorial Services: Sohini Mukherjee Senior Production Executive: Suhaib Ali Senior Graphic Designer—Cover: Meenu Raghav Senior Publishing Manager (SEM & Tech. Ed.): Shalini Jha Assistant Product Manager (SEM & Tech. Ed.): Tina Jajoriya General Manager—Production: Rajender P Ghansela Manager—Production: Reji Kumar Information contained in this work has been obtained by McGraw Hill Education (India), from sources believed to be reliable. However, neither McGraw Hill Education (India) nor its authors guarantee the accuracy or completeness of any information published herein, and neither McGraw Hill Education (India) nor its authors shall be responsible for any errors, omissions, or damages arising out of use of this information. This work is published with the understanding that McGraw Hill Education (India) and its authors are supplying information but are not attempting to render engineering or other professional services. If such services are required, the assistance of an appropriate professional should be sought. Typeset at Mukesh Technologies Pvt. Ltd., Puducherry, India 605 008 and printed at Cover Printer:
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Dedicated to my wife Yasoda K Venkata Rao
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Contents Preface
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1. Introduction 1.1 Introduction 1 1.1.1 Resistors 1 1.1.2 Capacitors 5 1.1.3 Inductors 11 1.2 The Nature of Atom 12 1.2.1 Energy Levels 13 1.3 Electronic Structure of the Elements 16 1.3.1 Energy Band Theory of Crystals 17 1.3.2 Insulators, Conductors, and Semiconductors 18 1.4 Semiconductors 19 1.4.1 Intrinsic or Pure Semiconductors 19 1.4.2 Conduction in Intrinsic Semiconductors 21 1.4.3 Fermi Level in an Intrinsic Semiconductor 21 1.4.4 Calculation of the Intrinsic Fermi Energy 23 1.4.5 Mass Action Law 24 1.4.6 Extrinsic Semiconductors 24 1.4.7 Conductivity of Semiconductor Materials 27 1.4.8 Drift Current 29 1.4.9 Diffusion Current 30 1.4.10 Einstein’s Relationship 31 1.4.11 Mean Lifetime and Diffusion Lengths of Charge Carriers 1.4.12 The Continuity Equation 32 1.4.13 The Hall Effect 33 1.4.14 Basic Unbiased PN Junction 34 Additional Solved Examples 36 Summary 38 Multiple Choice Questions 39 Short Answer Questions 41 Long Answer Questions 42 Unsolved Problems 42
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2. Diodes, Characteristics, and Applications
43
2.1 PN Junction Diode 43 2.1.1 Forward Bias 45 2.1.2 Reverse Bias 46 2.2 Analysis of the Diode Circuit 53 2.2.1 Numerical Method 53 2.2.2 Graphical Method 54 2.3 Junction Capacitances 58 2.3.1 Diffusion or Storage Capacitance, CD 58 2.4 Some Important Diode Parameters 64 2.5 Breakdown Diodes 65 2.5.1 Zener Diode 65 2.5.2 Avalanche Diode 66 2.6 Clipping Circuits 67 2.6.1 OneLevel Clippers 67 2.6.2 TwoLevel Clippers 72 2.7 Clamping Circuits 75 2.7.1 Working of a Clamping Circuit 75 2.7.2 Practical Clamping Circuit 76 2.7.3 Biased Clamping Circuits 77 2.7.4 Clamping Circuit Theorem 79 2.8 Tunnel Diode 80 2.9 Varactor Diode 85 2.10 Schottky Barrier Diode 89 2.10.1 Ohmic Contact 89 2.10.2 Rectifying Contact 90 2.11 Semiconductor Photodiode 91 2.12 PIN Diode 94 2.13 Back Diode or Backward Diode 96 2.14 Gunn Diode 96 2.15 IMPATT Diode 97 Additonal Solved Examples 99 Summary 103 Multiple Choice Questions 104 Short Answer Questions 106 Long Answer Questions 107 Unsolved Problems 107
3. Rectifiers and Filters 3.1 Introduction 108 3.2 Rectifiers 109
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3.2.1 HalfWave Rectifier 109 3.2.2 FullWave Rectifier 115 3.2.3 FullWave Bridge Rectifier 120 3.3 Filters 122 3.3.1 HalfWave Rectifier with Inductor Filter 122 3.3.2 FullWave Rectifier with Inductor Filter 124 3.3.3 Halfwave Rectifier with Capacitor Filter 127 3.3.4 FullWave Rectifier with Capacitor Filter 129 3.3.5 FullWave Rectifier with LC Filter 131 3.4 Multiple Cascaded Filters 135 3.4.1 Two Stages of an LC Filter 135 3.4.2 πFilter or CLC Filter 136 3.4.3 FullWave Rectifier with CRC Filter 137 3.5 Power Supply Performance 138 Additional Solved Examples 139 Summary 148 Multiple Choice Questions 148 Short Answer Questions 149 Long Answer Questions 150 Unsolved Problems 150
4. Transistor Characteristics 4.1 4.2 4.3 4.4
4.5 4.6
4.7
4.8 4.9
Junction Transistor 151 Transistor Current Components 154 Transistor as an Amplifier 157 Basic Transistor Configurations 157 4.4.1 Common Base Configuration 158 4.4.2 Common Emitter Configuration 163 4.4.3 Common Collector Configuration 169 Analytical Expressions for Transistor Characteristics 172 Maximum Transistor Junction Voltages 177 4.6.1 Reach Through or Punch Through in a Transistor 177 4.6.2 Avalanche Multiplication 177 Transistor Construction 180 4.7.1 Grown JunctionType Transistor 180 4.7.2 Alloy JunctionType Transistor 180 4.7.3 DiffusionType Transistor 181 4.7.4 EpitaxialType Transistor 182 BJT Specifications 182 Phototransistor 182
Additional Solved Examples Summary 192
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Multiple Choice Questions 192 Short Answer Questions 193 Long Answer Questions 194 Unsolved Problems 194
5. Transistor Biasing and Thermal Stabilization
195
5.1 Introduction 195 5.2 The Three Methods of Biasing a Transistor 195 5.2.1 Forward–Forward Biasing 195 5.2.2 Reverse–Reverse Biasing 196 5.2.3 Forward–Reverse Biasing 196 5.3 Bias Stability 200 5.4 Methods of Biasing a Transistor 201 5.4.1 Fixed Bias 202 5.4.2 Emitter Bias 204 5.4.3 CollectortoBase Bias or Collector Feedback Bias 211 5.4.4 Voltage Divider Bias or SelfBias 213 5.5 CB Configuration 219 5.6 CC Configuration 220 5.7 Bias Compensation 221 5.7.1 Diode Compensation 221 5.7.2 Thermistor Compensation 222 5.7.3 Sensistor Compensation 223 5.8 Integrated Circuit Biasing 224 5.9 Combination of Voltage Divider and CollectortoBase Bias 224 5.10 Emitter Current Bias 226 5.11 Thermal Resistance 226 Additional Solved Examples 227 Summary 239 Multiple Choice Questions 239 Short Answer Questions 240 Long Answer Questions 241 Unsolved Problems 241
6. SmallSignal, LowFrequency BJT Amplifiers 6.1 6.2 6.3 6.4 6.5 6.6
Introduction 242 The Location of the Operating Point 242 Sketching the AC Circuit of the Amplifier 244 SmallSignal, LowFrequency Model of the Transistor Analysis of a CE Transistor Amplifier 249 Simplified Equivalent Circuit of the Transistor 255
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6.7 6.8 6.9 6.10
6.11
6.12 6.13 6.14 6.15 6.16 6.17 6.18
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Analysis of CC Amplifier 256 Analysis of CB Amplifier 260 Comparison of Performance of CE, CC, and CB Amplifiers 261 Relevance of Input and Output Resistances 262 6.10.1 Voltage Amplifier 262 6.10.2 Current Amplifier 263 6.10.3 Transconductance Amplifier 263 6.10.4 Transresistance Amplifier 263 Distortion in an Amplifier 264 6.11.1 Harmonic Distortion 264 6.11.2 Noise 265 6.11.3 Intermodulation Distortion 266 Transconductance Model of the Transistor 266 Frequency Response Characteristic of an Amplifier 267 Transistor h Parameter Conversion 270 6.14.1 CE hParameters in Terms of CB hParameters 270 CE Amplifier with Unbypassed Emitter Resistance 276 Miller’s Theorem and Its Dual 278 Analysis of the Amplifier Circuit Using the Dual of the Miller’s Theorem 281 Analysis of the Amplifier Circuit Using the Miller’s Theorem 283
Additional Solved Examples 285 Summary 296 Multiple Choice Questions 297 Short Answer Questions 299 Long Answer Questions 299 Unsolved Problems 299
7. FET Characteristics, Biasing, and FET Amplifiers 7.1 7.2 7.3 7.4 7.5 7.6 7.7
Introduction 301 Construction of JFET 302 Characteristic Curves of JFET 303 Plotting the Transfer Characteristic Using Shockley’s Equation 306 Parameters of the FET and Their Interrelationship 307 Theoretical Determination of gm 308 MOSFETs 311 7.7.1 DepletionType MOSFETs 311 7.7.2 EnhancementType MOSFETs 314 7.7.3 Characteristics of an nChannel EnhancementType MOSFET 315 7.7.4 Characteristics of a pChannel EnhancementType MOSFET 317 7.8 Biasing JFETs 317 7.8.1 Fixed Bias 318
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7.9 7.10 7.11
7.12 7.13
7.8.2 SelfBias 320 7.8.3 Voltage Divider Bias 324 7.8.4 The Drain Feedback Bias 328 Universal Transfer Characteristic or the Universal Bias Curve 328 FET as a Voltage Variable Resistance or VoltageControlled Resistance FET Amplifiers 334 7.11.1 Common Source Amplifier 334 7.11.2 CS Amplifier with Unbypassed RS 337 7.11.3 CD Amplifier or Source Follower 340 7.11.4 CG Amplifier 343 Comparison of Performance of the Three Configurations 346 Comparison of BJT and FET Amplifiers 347
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Additional Solved Problems 347 Summary 358 Multiple Choice Questions 358 Short Answer Questions 360 Long Answer Questions 360 Unsolved Problems 361
8. Multistage Amplifiers 8.1 Introduction 363 8.2 Compound Amplifiers 364 8.2.1 CE–CC Amplifier 364 8.2.2 CE–CE Amplifier 368 8.2.3 CE–CB Amplifier or Cascode Amplifier 372 8.3 Miller Effect 373 8.3.1 CC–CC Amplifier 374 8.3.2 Biasing a Darlington Emitter Follower 378 8.4 Multistage Amplifiers 380 8.5 RCCoupled Amplifier Using a BJT 381 8.5.1 Gain in the MidBand 382 8.5.2 Gain in the LowFrequency Range 383 8.5.3 Gain in the HighFrequency Range 384 8.6 RCCoupled Amplifier Using FET 386 8.6.1 MidBand Range 386 8.6.2 LowFrequency Range 387 8.6.3 HighFrequency Range 388 8.7 Effect of CE on the LowFrequency Response of CE Amplifier Assuming CC to be Sufficiently Large 388 8.8 Bandwidth of nIdentical Multistage Amplifiers 392 8.9 TransformerCoupled Amplifier 393 8.10 DirectCoupled Amplifiers 395
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Additional Solved Examples 397 Summary 420 Multiple Choice Questions 421 Short Answer Questions 422 Long Answer Questions 422 Unsolved Problems 422
9. Feedback Amplifiers
424
9.1 Introduction 424 9.2 The Feedback Amplifier 425 9.2.1 Sampling Network 425 9.2.2 b Network 426 9.2.3 Mixing Network 427 9.3 Calculation of the Gain of the Feedback Amplifier 428 9.4 Advantages of Negative Feedback 433 9.4.1 Improved Gain Stability 433 9.4.2 Improved Bandwidth 434 9.4.3 Reduced Harmonic Distortion 436 9.4.4 Reduced Noise 438 9.4.5 Disadvantage with Negative Feedback in an Amplifier 438 9.5 Calculation of Input Resistance of a Feedback Amplifier 439 9.5.1 Calculation of the Input Resistance with Series Mixing 439 9.5.2 Calculation of the Input Resistance with Shunt Mixing 441 9.6 Calculation of Output Resistance of the Feedback Amplifier 443 9.6.1 Calculation of the Output Resistance with Voltage Sampling 443 9.6.2 Calculation of the Output Resistance with Current Sampling 446 9.7 Assumptions Made in the Analysis of Feedback Amplifiers 448 9.8 Reducing a Feedback Amplifier Circuit into an Amplifier Circuit without Feedback 449 9.9 Method of Analysis of Feedback Amplifiers 451 9.10 Analysis of Voltage Series Feedback Amplifier 453 9.11 Analysis of Current Series Feedback Amplifier 457 9.12 Analysis of Voltage Shunt Feedback Amplifier 461 9.13 Analysis of Current Shunt Feedback Amplifier 465 9.14 Voltage Series Feedback Pair 470 9.15 Some Circuit Variations 473 Additional Solved Examples 475 Summary 488 Multiple Choice Questions 488 Short Answer Questions 489 Long Answer Questions 490 Unsolved Problems 490
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10. Oscillators 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.11 10.12 10.13 10.14 10.15
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Introduction 491 LC Oscillators 493 Colpitts Oscillator 497 Hartley Oscillator 500 Clapp Oscillator 502 TunedCollector Oscillator 503 RC Oscillators 506 Wien Bridge Oscillator 507 RC Phase Shift Oscillator Using FET 509 RC PhaseShift Oscillator Using a BJT 511 Amplitude Stability in Oscillators 516 Frequency Stability in Oscillators 516 Crystal Oscillators 517 Beat Frequency Oscillator 519 Exact Analysis of Colpitts and Hartley Oscillators 520 10.15.1 Colpitts Oscillator 522 10.15.2 Hartley Oscillator 524
Additional Solved Examples 525 Summary 534 Multiple Choice Questions 534 Short Answer Questions 535 Long Answer Questions 536 Unsolved Problems 536
11. Power Amplifiers 11.1 Introduction 537 11.2 Distortion in Power Amplifiers 539 11.3 ClassA Power Amplifier 540 11.3.1 SeriesFed ClassA Power Amplifier 540 11.3.2 ClassA TransformerCoupled Power Amplifier 547 11.3.3 ClassA Push–Pull Power Amplifier 555 11.4 ClassB Push–Pull Power Amplifier 557 11.4.1 Calculation of the Conversion Efficiency 558 11.4.2 CrossOver Distortion 559 11.4.3 Dissipation in each Transistor of a ClassB Push–Pull Power Amplifier 11.4.4 Determining the Turns Ratio of the Output Transformer, To 561 11.4.5 Determining the Turns Ratio of the Input Transformer, Ti 562 11.4.6 Advantages of ClassB Push–Pull Power Amplifier 565 11.4.7 Disadvantages of ClassB Push–Pull Power Amplifier 565
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11.5 11.6 11.7 11.8
ClassB Push–Pull Power Amplifier That Eliminates the Transformer 565 Complementary Symmetry Push–Pull ClassB Power Amplifier 566 Heat Sinks 568 A ClassD Power Amplifier 570 11.8.1 ClassD Amplifier Using Complementary Transistors 570 11.8.2 A ClassD Amplifier Using CenterTapped Transformer and NPN Transistors 571 11.9 ClassS Amplifier 574 Additional Solved Examples 575 Summary 588 Multiple Choice Questions 588 Short Answer Questions 590 Long Answer Questions 590 Unsolved Problems 590
12. HighFrequency Transistor and FET Amplifiers 12.1 12.2 12.3 12.4 12.5
12.6 12.7 12.8
12.9 12.10 12.11
Introduction 592 The Miller Capacitances 593 CE Amplifier: Influence of Network Parameters at High Frequencies 594 HighFrequency Equivalent Circuit of the Transistor 595 Calculation of HighFrequency Parameters in Terms of the LowFrequency Parameters 596 12.5.1 The Transconductance, gm 596 12.5.2 Input Conductance, gb¢e 597 12.5.3 Feedback Conductance, gb¢c 598 12.5.4 The BaseSpreading Resistance, rbb¢ 599 12.5.5 Output Conductance gce 600 CE ShortCircuit Current Gain 601 CE Current Gain with Resistive Load 606 Hybrid p Capacitances 609 12.8.1 The Collector Junction Capacitance Cc 609 12.8.2 The Emitter Junction Capacitance Ce 610 12.8.3 Validity of the Hybrid p Model 612 Common Collector Amplifier (Emitter Follower) at High Frequencies 612 CB Amplifier at High Frequencies 616 HighFrequency FET Circuits 620 12.11.1 CS Amplifier at High Frequencies 620 12.11.2 Common Drain Amplifier at High Frequencies 623
Additional Solved Examples 626 Summary 641 Multiple Choice Questions 641
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Short Answer Questions 642 Long Answer Questions 642 Unsolved Problems 643
13. Tuned Amplifiers 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8
13.9
13.10 13.11 13.12
644
Introduction 644 Quality Factor, Q of L and C 646 SingleTuned CapacitiveCoupled Voltage Amplifier 647 Bandwidth of n Identical Cascaded Tuned Amplifiers 654 Inductively Coupled Tuned Primary BJT Amplifier 655 Inductively Coupled Tuned Secondary FET Amplifier 661 Impedance Adjustment with Tapped Circuits 664 DoubleTuned Amplifiers 667 13.8.1 Synchronously Tuned DoubleTuned Amplifier 667 13.8.2 StaggerTuned Amplifier 676 Instability in Tuned Amplifiers 678 13.9.1 Unilateralization 678 13.9.2 Mismatching Technique 679 13.9.3 Neutralization 679 Tuned Power Amplifiers 680 Tuned ClassC Power Amplifier 681 13.11.1 Applications of Class C Tuned Amplifiers 685 Wideband or Compensated Amplifier 687
Additional Solved Examples 693 Summary 702 Multiple Choice Questions 702 Short Answer Questions 703 Long Answer Questions 704 Unsolved Problems 704
14. Operational Amplifiers 14.1 Introduction 706 14.2 Differential Amplifier 707 14.2.1 DC Analysis 709 14.2.2 AC Analysis 710 14.2.3 Theoretical Calculation of r of a Differential Amplifier 711 14.2.4 Differential Amplifier Supplied with Constant Current 713 14.2.5 Transfer Characteristic of the Differential Amplifier 716 14.2.6 DualInput, UnbalancedOutput Differential Amplifier 718 14.2.7 Methods to Improve the Input Resistance 719 14.2.8 Methods to Derive Large Gain 721 14.2.9 Cascaded Differential Amplifier 722
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14.3 14.4 14.5 14.6 14.7 14.8
DCLevel Shifter 723 Output Power Stage 724 DC Characteristics of an OpAmp 725 AC Characteristics of an OpAmp 727 Frequency Stability in OpAmps 730 Frequency Compensation in OpAmps 732 14.8.1 External Frequency Compensation 732 14.8.2 Internal Compensation 734 14.9 Ideal Characteristics of an OpAmp 734 14.9.1 Concept of Virtual Ground in an OpAmp 735 14.9.2 Balancing an OpAmp 735 14.10 Bias Compensation in an OpAmp 736 14.11 Measurement of OpAmp Parameters 738 14.11.1 OpenLoop Differential Voltage Gain, Ad 738 14.11.2 Output Resistance, Ro 738 14.11.3 Differential Input Resistance, Ri 739 14.11.4 Input Offset Voltage, Vio 739 14.11.5 Input Bias Current, IB 740 14.11.6 Input Offset Current, Iio 740 14.11.7 Slew Rate, S 740 14.11.8 CommonMode Rejection Ratio, r 742 14.12 Differential Amplifier Using FET 743 Additional Solved Examples 744 Summary 745 Multiple Choice Questions 746 Short Answer Questions 747 Long Answer Questions 747 Unsolved Problems 747
15. Applications of OpAmp 15.1 Introduction 749 15.2 Linear Applications of OpAmp 749 15.2.1 Inverting Amplifier 749 15.2.2 Scale Changer 754 15.2.3 Sign Changer and Phase Changer 754 15.2.4 Noninverting Amplifier 754 15.2.5 Buffer Amplifier 757 15.2.6 Summing Amplifier or Adder 758 15.2.7 Subtracting Amplifier or Differential Amplifier 15.2.8 AdderSubtractor 763 15.2.9 Integrator 767 15.2.10 Differentiator 773
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15.2.11 Instrumentation Amplifier 779 15.2.12 VoltagetoCurrent Converter 783 15.2.13 CurrenttoVoltage Converter 785 15.3 Nonlinear Applications 786 15.3.1 Monostable Multivibrator Using OpAmp 15.3.2 Astable Multivibrator 788 15.3.3 Triangular Wave Generator 791 15.3.4 Comparator 791 15.3.5 Schmitt Trigger 798 15.3.6 Logarithmic Amplifier 800 15.3.7 Antilog Amplifier 802 15.3.8 Multiplier 805 15.3.9 Divider 806 15.3.10 Precision Rectifiers 807
786
Additional Solved Examples 812 Summary 816 Multiple Choice Questions 816 Short Answer Questions 819 Long Answer Questions 820 Unsolved Problems 820
16. Active Filters 16.1 Introduction 822 16.2 Passive LowPass, HighPass, and BandPass Filters 823 16.2.1 LowPass Filter 823 16.2.2 HighPass Filter 825 16.2.3 BandPass Filter 827 16.3 Active Filters 827 16.3.1 Classification of Active Filters 828 16.3.2 Butterworth Filter 829 16.3.3 BandPass Filter 842 16.3.4 BandRejection Filter 849 16.3.5 Allpass Filter 855 16.3.6 Switched Capacitor Filter 856 Additional Solved Examples 860 Summary 862 Multiple Choice Questions 863 Short Answer Questions 864 Long Answer Questions 864 Unsolved Problems 864
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17. Voltage Regulators
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17.1 Introduction 865 17.2 Classification of Voltage Regulators 867 17.3 Shunt Regulators 868 17.3.1 Zener Diode as a Shunt Regulator 868 17.3.2 Basic Transistor Shunt Regulator 874 17.4 Series Regulators 878 17.4.1 Transistor Series Regulator 878 17.4.2 Improved Series Regulator 882 17.5 Overload and Shortcircuit Protection in Regulators 883 17.5.1 Constant Current Limiting in a Series Regulator 883 17.5.2 FoldBack Current Limiting in a Series Regulator 885 17.6 A Series Regulator Using an Error Amplifier (Feedback Regulator) 891 17.7 IC Regulators 896 17.7.1 Linear IC Regulators 896 17.7.2 Switching Regulators 904 17.8 Voltage Multipliers 910 17.8.1 HalfWave Voltage Doubler 911 17.8.2 FullWave Voltage Doubler 913 Additional Solved Examples 917 Summary 927 Multiple Choice Questions 927 Short Answer Questions 929 Long Answer Questions 930 Unsolved Problems 930
18. Multivibrators 18.1 Introduction 932 18.2 Transistor as a Switch 933 18.2.1 Switching Times of the Transistor 936 18.3 Bistable Multivibrators 937 18.4 Fixed Bias Binary 937 18.4.1 Calculation of the StableState Currents and Voltages 938 18.4.2 Heaviest Load the Binary Can Drive 941 18.4.3 CollectorCatching Diodes 943 18.5 Resolution Time and Maximum Switching Speed of the Binary 947 18.6 Methods of Triggering a Binary 952 18.6.1 Unsymmetric Triggering 952 18.6.2 Symmetric Triggering 953 18.6.3 Nonsaturating Binary 955
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18.7 SelfBias Binary 956 18.8 Monostable Multivibrators 963 18.8.1 CollectorCoupled Monstable Multivibrator 963 18.8.2 Calculation of StableState Currents and Voltages 967 18.8.3 VoltagetoTime Converter 976 18.9 Astable Multivibrator 978 18.9.1 Calculation of the Time Period T2 for Which Q2 is OFF 979 18.9.2 Condition for the ON Transistor to be in Saturation 982 18.9.3 Recovery Time of Symmetric Astable Multivibrator 983 18.9.4 VoltagetoFrequency Converter 986 18.9.5 Astable Multivibrator with Vertical Edges for the Collector Waveforms 18.10 Schmitt Trigger 988 18.10.1 Elimination of Hysteresis in Schmitt Trigger 997 18.10.2 Applications of Schmitt Trigger 998
987
Additional Solved Examples 998 Summary 1000 Multiple Choice Questions 1001 Short Answer Questions 1003 Long Answer Questions 1003 Unsolved Problems 1004
19. TimeBase Generators
1005
19.1 Introduction 1005 19.2 Voltage Sweep Generators 1006 19.2.1 Exponential Sweep Generator 1006 19.2.2 Miller’s Sweep Generator 1019 19.2.3 Bootstrap Sweep Generator 1022 19.3 Current Sweep Generators 1026 19.3.1 Linear Current Sweep by Adjusting the Driving Waveform 19.3.2 Generation of Trapezoidal Waveform 1029
1028
Additional Solved Examples 1031 Summary 1034 Multiple Choice Questions 1034 Short Answer Questions 1036 Long Answer Questions 1037 Unsolved Problems 1037
20. Integrated Circuits 20.1 Introduction 1038 20.1.1 Classification of ICs
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20.2 The Monolithic Integrated Circuit 1039 20.2.1 Fabrication of an NPN Transistor 1040 20.2.2 Fabrication of the Diode 1042 20.2.3 Fabrication of Capacitor 1043 20.2.4 Fabrication of Resistors 1043 20.3 Fabrication of a Typical Circuit as a Monolithic IC 1044 20.4 Package Types of ICs 1048 20.5 IC Transistor Amplifier 1050 20.6 Fabrication of NMOS ICs 1051 20.6.1 Simple Fabrication of IC MOS Transistors 1052 20.6.2 MOS Transistor as a Resistor 1052 Summary 1053 Multiple Choice Questions 1053 Short Answer Questions 1054 Long Answer Questions 1054
21. 555 Timer and Applications
1055
21.1 Introduction 1055 21.1.1 Pin Details 1055 21.2 Operating Modes of 555 Timer 1057 21.2.1 555 Timer as a Monostable Multivibrator 1057 21.2.2 555 Timer as Astable Multivibrator 1061 21.2.3 Some Other Applications 1069 21.2.4 556 Dual Timer 1076 Additional Solved Examples 1077 Summary 1080 Multiple Choice Questions 1080 Short Answer Questions 1082 Long Answer Questions 1082 Unsolved Problems 1082
22. Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments 22.1 Power Electronic Devices 1085 22.1.1 SiliconControlled Rectifier 1085 22.1.2 TRIAC 1092 22.1.3 DIAC 1094 22.1.4 The Gate TurnOff Thyristor or GTO Thyristor 1096 22.1.5 LightActivated SCR or Photo SCR 1096 22.1.6 LightActivated TRIAC or Photo TRIAC 1096
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22.2 Optoelectronic Devices 1097 22.2.1 Photoconductivity 1097 22.2.2 Photodetectors 1099 22.3 Optocouplers 1107 22.3.1 Photodiode Optocoupler 1108 22.3.2 Cold Cathode or Nixie Displays 1109 22.3.3 SevenSegment LED Display 1110 22.3.4 Liquid Crystal Display 1112 22.3.5 Plasma Display Panels 1114 22.4 Fiber Optics 1114 22.4.1 Refractive Index 1115 22.4.2 Types of Optical Fibers 1117 22.4.3 Optical Communication Link 1120 22.5 Measuring Instruments 1121 22.5.1 DC Ammeter 1121 22.5.2 DC Voltmeter 1125 22.5.3 Multirange Voltmeter 1125 22.5.4 MovingIron Instruments 1126 22.5.5 MovingIron Voltmeter 1127 22.5.6 Ohm Meter 1127 22.5.7 Multimeter 1128 22.5.8 Electronic Voltmeters 1129 22.5.9 Digital Voltmeters 1133 22.5.10 Energy Meter 1138 22.5.11 Digital Frequency Meter 1140 22.5.12 Cathode Ray Oscilloscope 1145 Summary 1150 Multiple Choice Questions 1151 Short Answer Questions 1155 Long Answer Questions 1155 Unsolved Problems 1156
23. Digital Electronics Scan the QR Code given here to Access the Full Chapter. 23.1 Introduction 23.2 Binary Logic 23.2.1 Conversion of a Binary Number into a Decimal Number 23.2.2 Conversion of Decimal Number into Binary 23.3 Unsigned Numbers 23.4 Representation of Negative Numbers 23.5 Subtraction Using Complement Methods
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23.6 23.7 23.8 23.9 23.10 23.11 23.12 23.13 23.14 23.15 23.16 23.17 23.18 23.19
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Octal and Hexadecimal Representation Boolean Algebra Theorems Simplification of Boolean Functions De Morgan’s Laws Boolean Expressions in Sum of Products Form and in Product of Sums Form Universal Gates Exclusive OR Gate Realization of Logic Functions Using NAND Gates Realization of Logic Functions Using NOR Gates Karnaugh Map Don’t Care Conditions Logic Gates A/D and D/A Converters
Additional Solved Examples Summary Multiple Choice Questions Short Answer Questions Long Answer Questions Unsolved Problems
24. Microcomputers and Microprocessors Scan the QR Code given here to Access the Full Chapter. 24.1 Evolution of Microprocessor 24.2 Salient Features of 8085 Microprocessor 24.3 8085 Bus Structure 24.4 Internal Architecture of 8085 Microprocessor 24.4.1 Register Array 24.4.2 Arithmetic Logic Unit 24.4.3 Timing and Control Unit 24.4.4 Interrupt Control 24.4.5 Serial I/O Control 24.5 Microcomputer Languages 24.5.1 Machine Language 24.5.2 Assembly Language 24.5.3 HighLevel Language 24.6 Instruction Set 24.6.1 Operation Code and Operand 24.7 Classification of Instruction Set 24.7.1 DataTransfer Group
1208
xxiv
Contents
24.8
24.9
24.10 24.11
24.7.2 Arithmetic Operations 24.7.3 Logical Operations 24.7.4 Branching Operations 24.7.5 Stack, I/O, and Machine Control Group The 8085 Addressing Modes 24.8.1 Direct Addressing 24.8.2 Register Addressing 24.8.3 Register Indirect Addressing 24.8.4 Immediate Addressing 24.8.5 Implicit Addressing Instruction Formats 24.9.1 SingleByte Instructions 24.9.2 TwoByte Instructions 24.9.3 ThreeByte Instructions 16Bit Microprocessor Differences between 8085 and 8086
Additional Solved Examples Summary Multiple Choice Questions Short Answer Questions Unsolved Problems
Appendix A Appendix B Appendix C
1232 1236 1261
Index
1267
Preface Understanding the principles of workings of various electronic devices, and the ability to analyze electronic circuits are the prerequisites for further learning in the fields of electronics, instrumentation, communications and power electronics. Amplifiers, oscillators, sweep generators, multivibrators, A/D converters and D/A converters, etc., eventually become the subsystems of either an analog or a digital system.
Rationale behind Writing the Book There are many standard books on these topics. However, the experience of the authors has shown that the presentday student wants books that give emphasis to neat and crisp circuit presentations that help him/her understand the underlying principles better. In reality, some students are even reluctant to consult the prescribed textbooks, and prefer to look for shortcuts. Therefore, in trying to address the needs of the students, the authors, with their vast experience in teaching, have made a genuine attempt in this book to provide solutions to circuit simplifications that enable readers to appreciate the nuances in circuit analysis. This will help students understand the principles better and thus will sustain their interest in the subject.
Target Readers Initially, the authors aimed to limit the scope of this book to the syllabi prescribed by only certain universities. However, the scope has been expanded to meet the requirements of many other universities. Therefore, it is obvious that this single book caters to the curriculum requirements of many Indian universities. Undergraduate students of ECE, EEE, Instrumentation and Computer Science branches will find this book very useful, mainly because of the method of presentation of the content with relevant tips for circuit simplification and analysis. Further, this book will also be very useful for practicing engineers as a quick reference since it deals with a wide variety of topics. This book additionally, to a large extent, addresses the needs of those who appear for competitive examinations like IES, UPSC, GATE, etc.
Salient Features of this Book • •
Simplification of circuits presented in a systematic fashion, which may be termed the biggest asset of this book Thorough coverage of devices and analyses of electronic circuits
xxvi • • •
Preface
Diagrammatic exposition of subject matter with elaborate analysis and necessary derivations Dedicated chapter on integrated circuits with classifications, fabrication, etc. Excellent pedagogy: • 923 illustrations • 570 Solved examples • 655 Review questions • 215 Review numerical problems • 700 Multiple choice questions with answers
Use of Technology In bringing out this edition, we have taken advantage of the recent technological developments to create a wealth of useful information not present in the physical book. For students using smart phones and tablets, scanning QR codes located within the chapters give them immediate access to more resources. The QR code appearing in chapters 23 and 24 give students access to the full chapters.
Organization of Chapters This book contains 24 chapters. Chapter 1 deals with identification of R, L and C components and considers them as circuit elements that can be connected either in series or in parallel. This chapter also deals with the atomic structure of elements, and classification of elements as conductors, insulators and semiconductors. Intrinsic semiconductors and P and Ntype extrinsic semiconductors are considered. The behaviour of an unbiased junction diode is also presented. Chapter 2 considers the VI characteristics and equivalent circuits of a junction diode and the application of the PN junction diode in clipping and clamping circuits. This chapter also discusses the principles of working of some specialpurpose diodes, their characteristics and typical applications, such as tunnel diode, varactor diode, Schottky barrier diode, PIN diode, photo diode, Gunn diode and IMPATT diode. Chapter 3 considers the application of diodes in rectifiers to convert ac to dc. The analysis of halfwave and fullwave rectifiers is presented. Also, various types of filters that help in reducing ripple like a capacitor input filter, inductor filter, Ltype filter and πtype filter are presented. Chapter 4 talks about the principle of working of the bipolar junction transistor and also considers the three basic configurations, namely, common emitter, common base and common collector. Operating the transistor in the active, saturation and cutoff regions is discussed. The current gains in the three configurations are compared. The principle of working of a phototransistor is also discussed. Chapter 5 deals with the various biasing techniques, namely, fixed bias, emitter bias, voltage divider bias, collectortobase feedback bias and also IC bias. The performance of these biasing methods, visavis the stability of the operating point is discussed. Also, biascompensation methods like diode compensation, thermistor compensation and sensistor compensation are illustrated.
Preface
xxvii
Chapter 6 considers the use of a BJT as a smallsignal amplifier. The procedure to draw the dc and ac circuits is presented. The graphical analysis of a CE amplifier using the output characteristics, dc and ac load lines is presented. Analysis of the three basic amplifier configurations using the smallsignal, lowfrequency model of the transistor in terms of hparameters is discussed and their performance quantities are compared. The effect of noise and distortion on the performance of the amplifier is also presented. Chapter 7 deals with the principle of working of JFETs and MOSFETs and their characteristics. The various biasing methods and the design procedures are presented. Further, the smallsignal model of the FET and the analysis of the three amplifiers, namely, common source, common drain and common gate amplifiers is presented and their performances are compared. Chapter 8 discusses about the need for compound amplifiers like CECE, CCCE, CCCC, etc. and shows the advantage of these amplifiers in deriving the necessary characteristics. In addition, the various interstage coupling methods like RC coupling, transformer coupling and direct coupling are presented. Analysis of both BJT and FET RC coupled amplifiers is carried out and the frequency response characteristic is presented to calculate the bandwidth. Finally, the bandwidth of an nstage RC coupled amplifier is calculated. Chapter 9 presents the need for negative feedback in an amplifier and the expression for the gain of a feedback amplifier is derived. Also, the advantages of negative feedback in an amplifier like improved gain stability, reduced harmonic distortion and noise, improved bandwidth are also considered. In addition, the way in which the input and output impedances in a feedback amplifier change depending on the type of mixing and method of sampling is discussed. Analysis of the four basic feedback amplifiers, namely, voltage series, current series, voltage shunt and current shunt feedback amplifier is presented in detail. Chapter 10 considers Colpitts, Hartley, Clapp and tuned collector oscillators under the category of RF LC oscillators and Wienbridge and RC phase shift oscillators under the category of audio frequency RC sinusoidal oscillators. Crystal oscillators that give better frequency stability as RF oscillators are considered. Finally, a beat frequency oscillator that provides better frequency stability of lowfrequency oscillations is considered. Chapter 11 covers large signal amplifiers which are also called power amplifiers. Graphical method of analysis is presented and the procedure to calculate the output power, conversion efficiency and harmonic distortion is considered in detail for Class A and Class B power amplifiers. In addition, a transformerless complementary symmetry pushpull power amplifier, Class D and Class S amplifiers are presented. Finally, the need for heat sinks is discussed. Chapter 12 deals with the highfrequency behaviour of BJT and FET. Analysis of CE, CC and CB amplifiers and also CS and CD amplifiers is carried out using the highfrequency models of the transistor and FET. Chapter 13 considers the need for tuned amplifiers, and the expressions for the voltage gain and bandwidth of singletuned capacitorcoupled tuned amplifier, synchronously tuned doubletuned amplifier and the staggertuned amplifier are derived using which it is possible to infer as to the specific application of these amplifiers. The chapter also deals with the problem of instability in tuned amplifiers and throws light on possible methods that can help overcome this problem. Finally, a tuned Class C power amplifier and a wideband amplifier are considered too. Chapter 14 discusses the basic building blocks of an Opamp like a differential amplifier and a dc level shifter. It also illustrates that a differential amplifier supplied with constant current will have a large common mode rejection ratio. It considers the need for a dc level shifter in an
xxviii
Preface
Opamp and presents possible methods for dc level shifting. It presents the frequencycompensation methods that need to be employed in Opamps and also illustrates experimental methods for measuring the Opamp parameters. Chapter 15 considers the linear applications of Opamps such as inverting and noninverting amplifiers, summing and subtracting amplifiers, differentiator and integrator and currenttovoltage and voltagetocurrent converters. This chapter also deals with some of the nonlinear applications such as monostable and astable multivibratos, and logarithmic and antilog amplifiers. It also talks about precision rectifiers. Chapter 16 deals with active filters and presents the method of analysis and design of first and secondorder Butterworth LPF, HPF and BPF filters. It also presents wide and narrowband reject filters. Chapter 17 considers the need for voltage regulators to stabilize the output of a power supply and illustrates the principle of working of series and shunt regulators. It then talks about a complete feedback regulator. It subsequently discusses linear IC regulators and later presents switching regulators that achieve better efficiency. Finally, it introduces voltage multipliers. Chapter 18 deals with analysis and design of bistable, monostable and astable multivibrators and presents some simple applications of these regenerative circuits. It also discusses symmetric and unsymmetric methods of triggering a binary. Finally, it deals with an emitter coupled binary, which is also known as the Schmitt trigger and its varied applications. Chapter 19 considers an exponential voltage sweep generator and presents methods to linearize a nonlinear sweep using Miller and bootstrap sweep generators. It considers the principle of working of a current sweep and shows that an exponential current sweep can be linearized by adjusting the driving waveform. Chapter 20 presents the monolithic IC fabrication process. It talks about fabrication of resistors, capacitors and transistors on an IC and presents the packaging techniques. Finally, it introduces MOS technology for greater circuit density. Chapter 21 deals with the principle of operation of IC 555 timer as monostable, astable and bistable multivibrator circuits. This chapter introduces dual timer IC 556. Chapter 22 introduces the principle of working of some power electronic devices such as SCR, TRIAC, DIAC, etc., and optoelectronic devices such as photoconductors, LEDs, and laser diodes. Also, information is provided on the working of display devices such sevensegment LED displays, LCDs, and plasma display panels. The chapter also considers the working of various measuring instruments such as multimeter, power meter, and energy meter. Finally, instruments for the measurement of frequency, time, distortion and spectral analysis are presented. Chapters 23 and 24 can be accessed through the QR codes given in the Table of Contents and the respective chapters. Chapter 23 deals with number systems and conversions from one radix to the other. The chapter also introduces rules for the minimization of Boolean expressions for the reduction of complex combinational circuits. Further, Karnaugh maps that help in the simplification of the Boolean function in a much effective manner have been considered. TTL and CMOS logic gates using discrete components have been presented and the performance parameters that define the suitability of a gate for a given application have been discussed. Finally, ADC and DAC circuits are considered. Chapter 24 deals with the structure of the microcomputers and microprocessors. The chapter also talks about the instruction set of 8085 processor and also tells the procedure to load the program into the processor. Simple programs are considered. Finally, the chapter introduces 8086.
Preface
xxix
Web Supplements Instructors can access the Solution Manual and PowerPoint Lecture Slides at http://highered.mheducation.com/sites/9332901155 Also, students can read chapters 23 and 24 by scanning the QR codes given in the Table of contents and the respective chapters.
Acknowledgements The authors wish to express their sincere thanks and gratitude to Dr G S N Raju, Vice Chancellor, Andhra University, who has been a source of inspiration and motivation through his academic excellence and leadership qualities. The authors acknowledge their sincere gratitude to the Principal of the AU college of Engineering for Women, Dr Ch. Ratnam, for his inspiration and encouragement throughout the course of this project. The authors also express their heartfelt gratefulness to Dr K V V Satyanarayana Raju, Chairman, Sri. K Sasi Kiran Varma, Secretary, and Dr D L N Raju, CEO of Chaitanya Group of Institutions, for their cooperation and encouragement and also for providing the necessary facilities. The authors also wish to thank, Sri. K. Murali Krishnam Raju, Finance Director, Sri. S. S. Varma, CAO and Dr. M. Ramjee, Principal of Chaitanya Engineering College for their support. The authors wish to thank the following reviewers for their suggestions in improving the quality and the content of this book. Ratish Agarwal
University Institute of Technology, Rajiv Gandhi Technical University (RGTU), Bhopal, Madhya Pradesh
N R Kidwai
Gautam Buddh Technical University (GBTU), Uttar Pradesh Technical University (UPTU), Lucknow, Uttar Pradesh
Sanjit Kumar Dash
Krupajal Engineering College, Biju Patnaik University of Technology (BPUT), Bhubaneswar, Odisha
Barnali Dey
Sikkim Manipal University, Gangtok, Sikkim
Yogesh Dandawate
Vishwakarma Institute of Information Technology (VIIT), Pune, Maharashtra
Mrunal Mahesh Honap
Pune Vidhyarthi Griha’s College of Engineering and Technology, University of Pune, Pune, Maharashtra
S G Patil
Dr D Y Patil College of Engineering, Pune, Maharashtra
C V Raghu
National Institute of Technology (NIT) Calicut, Kozhikode, Kerala
Asha Elizabeth
Cochin University of Science and Technology (CUSAT), Cochin, Kerala
S Gomathi
KSR College of Technology, Tiruchengode, Tamil Nadu
Prakash Biswagar
RV College of Engineering, Visvesvaraya Technological University (VTU), Bangalore, Karnataka
Jammalamadugu Ravindranadh
RV. & JC College of Engineering, Acharya Nagarjuna University, Guntur, Andhra Pradesh
xxx
Preface
A Hazrathaiah
Narayana Engineering College, Nellore, Andhra Pradesh
P Rajesh Kumar
University College of Engineering, Vishakhapatnam, Andhra Pradesh
Special thanks to Dr M Murali, Sanketika Institute of Technology, and Mr M S Prakasa Rao, Sri Vasavi Engineering College, Tadepalligudem, for their suggestions and inputs. The authors also thank Dr A Chanrda Sekhar, GITAM, for his useful suggestions. Finally, the authors would fail in their duty if they do not profusely thank Ms A Amulya and Ms A Alekhya for their frank opinions and inputs, at every stage of this book. The authors felicitate Ms Vibha Mahajan, Ms Koyel Ghosh, Mr Suhaib Ali and the other members of the editorial team at McGraw Hill Education (India) for their wholehearted cooperation in bringing out a quality product.
Feedback Request Suggestions for the improvement of the content (factual or otherwise) and the script are welcome and the readers are requested to write to us at [email protected] and [email protected]. We appreciate your time and effort in improving the content presented in the book. K Venkata Rao K Rama Sudha
Publisher’s Note McGrawHill Education (India) invites suggestions and comments from you, all of which can be sent to [email protected] (kindly mention the title and author name in the subject line). Piracyrelated issues may also be reported.
1
INTRODUCTION
Learning objectives After reading this chapter, the reader will be able to
1.1
Understand the method to identify and use R, C, and L as circuit components Understand the atomic structure of elements Classify elements as conductors, insulators, and semiconductors Appreciate the need for N and Ptype extrinsic semiconductors Understand the relevance of the laws that govern the behavior of semiconductor elements Understand the operation of an unbiased PN junction
INTRODUCTION
Resistors, capacitors, and inductors are the passive linear circuit components that are extensively used in electronic circuits. Although resistors are energydissipating elements, capacitors and inductors are energystoring elements.
1.1.1 Resistors Resistors determine the flow of current in an electrical circuit. The higher the resistance in the circuit, the smaller is the current in it and vice versa. Resistance obeys Ohm’s Law. Resistance is measured in ohms (Ω). All modern fixed value resistors can be classified into four broad groups: 1. Carbon composition resistor: Carbon composition resistor is manufactured from a mixture of finely ground carbon dust or graphite and a nonconducting ceramic (clay) powder to bind it all together. These are usually lowwattage resistors. 2. Film resistors: Film resistors are of two types: (i) thin film resistors and (ii) thick film resistors. (i) Thin film resistors may consist of metal film, carbon film and metal oxide film resistor types. These resistors are made by depositing pure metals, such as nickel, or an oxide film, such as tinoxide, onto an insulating ceramic rod or substrate made from conductive metal oxide paste. These are also lowwattage resistors. (ii) Thick film resistors are made by depositing a much thicker conductive paste of ceramic and metal, called cermet, onto an alumina ceramic substrate.
2
Electronic Devices and Circuits
3. Wirewound resistor: Wirewound resistor is made by winding a thin metal alloy wire such as nichrome onto an insulating ceramic former in the form of a spiral helix. These types of resistors are generally only available from few ohms to typically 100 kΩ. 4. Semiconductor resistor: Semiconductor resistor is derived from a doped semiconductor material. In fact, some of the active devices that will be discussed later will be replacing resistors in the manufacture of integrated circuits (ICs). To calculate the current and power dissipated in a resistor, consider the circuit in Figure 1.1. Using Ohm’s law
I
100 Ω R
V 10 I= = = 0.1 A R 100
V
10 V
and the power dissipated in R is P=
V2 = I 2 R = ( 0.1)2 × 100 = 1 W R
Figure 1.1 Calculation of I and P in R
Example 1.1 Calculate the maximum permissible current in a resistor of 1 kΩ and power dissipation capability of 1 W. Solution: I =
1 = 0.032 A 1000
P = R
When resistors are connected in series, the total resistance is the sum of the individual resistors. Consider Figure 1.2 where R = R1 + R2 + R3. The current I in the loop remains constant, whereas voltages across the individual resistors are different.
I
+ V1 −
+ V2 −
+ V3 −
200 Ω
300 Ω
500 Ω
R1
R2
R3
R
10 V V
Figure 1.2 Resistors connected in series
Example 1.2 For the circuit in Figure 1.2, for the indicated resistor values, calculate I, V1, V2, V3, P1, P2, and P3. Solution: R = R1 + R2 + R3 = 200 + 300 + 500 = 1000 Ω
Introduction
I=
3
V 10 = = 0.01 A R 1000
V1 = IR1 = 0.01 × 200 = 2 V
P1 = V1I = 2 × 0.01 = 0.02 W
V2 = IR2 = 0.01 × 300 = 3 V
P2 = V2I = 3 × 0.01 = 0.03 W
V3 = IR3 = 0.01 × 500 = 5 V
P3 = V3I = 5 × 0.01 = 0.05 W
Consider Figure 1.3. When resistors are connected in parallel, the effective resistance is calculated as follows: 1 1 1 1 or G = G1 + G2 + G3 = + + R R1 R2 R3
(1.1)
1 where G = 1 , G1 = 1 , G2 = 1 , and G3 = . The Gs are conductances. R3 R R1 R2 V across the resistors is the same, but the currents in the individual branches are different.
I V
I1 R1
10 V
I2
I3
R2
R3
300 Ω
500 Ω
R
200 Ω
Figure 1.3 Resistors in parallel
Example 1.3 For the circuit in Figure 1.3, for the indicated resistor values, calculate I, I1, I2, I3, P1, P2, and P3. Solution: I1 =
10 V = = 0.05 A R1 200
I2 =
10 V = = 0.033 A R2 300
I3 =
10 V = = 0.02 A R3 500
P1 = VI1 = 10 × 0.05 = 0.5 W
P2 = VI 2 = 10 × 0.033 = 0.33 W
P3 = VI 3 = 10 × 0.02 = 0.2 W
I = I1 + I2 + I3 = 0.05 + 0.033 + 0.02 = 0.103 A
Identification of Resistor Values Resistors are identified by their color code: 4, 5, or even 6 bands are represented on a resistor. In a 4band coded resistor, the first two bands represent the digits, the third band represents the multiplying factor, and the fourth band represents
4
Electronic Devices and Circuits
Digit 1
Digit 2
Multiplier
Tolerance
Digit 1
Digit 2
Digit 3
Multiplier
Tolerance
Band 1
Band 2
Band 3
Band 4
Band 1
Band 2
Band 3
Band 4
Band 5
tolerance (Figure 1.4(a)). In a 5band coded resistance, the first three bands represent the digits, the fourth band represents the multiplying factor, and the fifth band represents tolerance (Figure 1.4(b)). The colors of the bands and the corresponding digit values and tolerances are shown in Table 1.1.
(a) 4band code
(b) 5band code
Figure 1.4 4– and 5–band coded resistors
Table 1.1 Color codes and tolerances Color
Digit
Multiplier
Tolerance (%)
Black
0
100
Brown
1
101
1
Red
2
102
2
Orange
3
103
Yellow
4
104
Green
5
105
0.5
Blue
6
106
0.25
Violet
7
107
0.1
Gray
8
108
White
9
109
Gold
10−1
5
Silver
10−2
10
Blank
20
Brown, red, green, blue, and violet are used as tolerance codes on 5band resistors only. The blank 20 percent band is used only with the 4band code. For carbon composition and carbon film resistors, the common tolerances are 5 percent, 10 percent, and 20 percent.
Introduction
5
Example 1.4 For the colorcoded resistors shown in Figure 1.5, find the resistor value and tolerance. Solution: The values and tolerances are shown in Figure 1.5. 7 102
4
10
6
8
0 102
5
Gold
(b)
(a)
9
Red
Black
Blue
68 kΩ ± 5%
Gray
Silver
Red
Violet
Yellow
4.7 kΩ ± 10%
7 100
3
3
0 101
0.1 3.3 kΩ ± 0.1%
5
Violet
Black
(d)
(c)
1
Brown
Orange
Orange
Black
White
Violet
97 Ω ± 20%
8 10− 2 2
3
3
0 10− 1
0.1
(e)
Violet
Gold
Black
Orange
33 Ω ± 0.1%
Orange
Red
Grey Silver
Green
Brown
1.58 Ω ± 2%
(f)
Figure 1.5 Color coded resistors
Specification of a Resistor A resistor is completely specified by its resistance value, power rating, tolerance, and temperature coefficient. Temperature coefficient is indicated as ppm/°C, where ppm stands for parts per million. For example, if temperature coefficient = 100 ppm/°C, then it means that the value of the 1 MΩ resistance can change by not more than 100 Ω for a temperature change of 1°C or 0.1 Ω for every 1 kΩ. It is important to note that the same resistance is offered for both dc and ac currents. A variable resistance is called a potentiometer.
1.1.2 Capacitors Capacitor is also called a condenser and is a linear passive circuit element, which has the capacity to store energy in the form of an electrical charge and produces a potential difference across its terminals. A capacitor basically consists of two parallel metal plates that are electrically separated by a distance d in meters with dielectric material between the plates. The most common types of
6
Electronic Devices and Circuits
dielectric materials used are air, paper, polyester, polypropylene, Mylar, ceramic, glass, oil, or a variety of other materials. A parallel plate condenser is shown in Figure 1.6(a) and its schematic representation in Figure 1.6(b). C=
eA e 0e r A kA Farads = = d d d
(1.2)
where k = ε0 εr ε0 = permittivity of free space = 8.854 × 10−12 F/m k = relative permittivity of the dielectric material between the plates The capacitance C is 1 F when a charge of 1 Coulomb is stored on the plates by a voltage of 1 V (Coulomb/V). εr for common materials is: pure vacuum = 1.0, air = 1.0005, paper = 2.5–3.5, glass = 3–10, mica = 5–7, wood = 3–8, and metal oxide powders = 6–20, etc. On the application of voltage V, positive charges are stored on the top plate and negative charges on the bottom plate. C is given as C=
Q or V = CQ V
(1.3)
where Q is the charge in Coulombs, C is the capacitance in Farads, and V is the applied voltage in Volts. Metal plate +
+
d
+ + + + + A in m 2
+Q + + + + + + + + +
Dielectric e
− − − − − − −− −Q − − − − − − − − − − −
I
V
− C
Metal plate (a)
(b)
Figure 1.6 (a) Parallel plate capacitor and (b) schematic representation
Example 1.5 In a parallel plate condenser, the plates are separated by a distance of 0.1 cm and the area of the plates is 100 cm2. Express C in pF, if the dielectric medium is air. Solution: ε = ε0εr = 8.854 × 10−12 × 1.0005 = 8.854 pF/m A = 100 cm2 = 0.01 m2 d = 0.1 cm = 0.001 m C =
εA 8.854 × 10 −12 × 0.01 m 2 = = 88.54 pF d 0.001 m
7
Introduction
The current in a capacitor is directly related to the charge on the plates. As current is the rate of flow of charge with respect to time and Q is proportional to the applied voltage V, then I =C
dV dt
I
(1.4)
+ +
The energy stored in a capacitor is the integral of the instantaneous power. Assuming that the capacitor had no charge across its plates at t = −∞, then the energy stored in the capacitor at time t is
C V V −
−
Figure 1.7 Circuit of Example 1.6
dv 1 E = ∫ Pdt = ∫ VI dt = ∫ VC dt = CV 2 J ( Joules) −∞ −∞ −∞ dt 2 t
t
t
(1.5) 10 K
Example 1.6 A 47μF capacitor is connected to a voltage that varies in time as v = 20 sin(200πt) volts (Figure 1.7). Calculate the current i through the capacitor.
20 K
1 µF
15 V
C
Solution: i =C
dv d = 47 × 10 −6 [ 20 sin( 200pt )] Figure 1.8 Circuit of Example 1.7 dt dt = 47 × 10−6 × 20 × 200π cos(200πt) = 0.59 cos(200πt) A
Example 1.7 Calculate the energy stored in C shown in Figure 1.8. Solution: Under dc condition, C is an open circuit and the circuit in Figure 1.8 reduces to that shown in Figure 1.9. The voltage across C is
V = 15 ×
10 K
20 K
V
15 V
Figure 1.9 Circuit of Figure 1.8 under dc condition
20 = 10 V 10 + 20
1 1 The energy stored in C = CV 2 = × 1 × 10 −6 × 102 = 50 µJ 2 2
I + V
C1
I1
C2
I2
−
Capacitors in Parallel When capacitors C1 and C2 are
Figure 1.10 Capacitors in parallel
connected in parallel (Figure 1.10), then the effective capacitance Ceq is calculated as follows: I = I1 + I 2 = C1 ∴ Ceq = C1 + C2
dV dV dV dV + C2 = (C1 + C2 ) = Ceq dt dt dt dt (1.6)
8
Electronic Devices and Circuits
Capacitors in Series When capacitors C1 and C2 are connected in series (Figure 1.11), then the effective capacitance Ceq is calculated as follows: 1 d (V1 + V2 ) dV1 dV2 dV I I 1 = = + = + = I + dt dt dt dt C1 C2 C1 C2 I=
dV 1 1 dV = Ceq dt 1 1 dt C + C 1 2
1 1 1 = + Ceq C1 C2
I + V −
+ V1 − + V2 −
C1
C2
Figure 1.11 Capacitors in series
(1.7)
Types of Capacitors Different types of capacitors are available in the market. A few types are listed below: (i) Dielectric capacitors: Dielectric capacitors are multiplate, airspaced, variable type condensers. These condensers have a set of fixed plates and a set of movable plates that move in between the fixed plates. These are used as tuning condensers in transmitters and receivers. (ii) Film capacitors: Film capacitors use polystyrene, polycarbonate, or Teflon as their dielectrics and are also called plastic capacitors. The dielectric is a plastic film and these capacitors operate well at high temperatures and have smaller tolerances. (iii) Ceramic capacitors: Ceramic capacitors or disc capacitors are made by coating two sides of a small porcelain or ceramic disc with silver and are then stacked together to make a capacitor. Very low capacitance values in a single ceramic disc of about 3–6 mm are available. (iv) Electrolytic capacitors: An electrolytic capacitor uses a semiliquid electrolyte solution in the form of a jelly or paste as one of its plates to achieve a larger capacitance per unit volume. The dielectric is a very thin layer of oxide with thickness typically of the order of 10 µ (microns). As the insulating layer is thin, capacitors with a large value of capacitance with small physical size are possible, as d, the spacing between the plates, is very small. Electrolytic capacitors are polarized capacitors. Consequently, while connecting to a dc voltage the positive end of the voltage source should be connected to the positive terminal of C and negative end to the negative terminal of C. Improper polarization will breakdown the insulating oxide layer and can damage the capacitor.
Characteristics of Capacitors The following are some of the characteristics that are usually listed in the data sheets and are helpful in proper use of capacitors: (i) The nominal value of the capacitance C of a capacitor is marked on the body of the capacitor as numbers, letters, or colored bands. (ii) The working voltage: The maximum dc or ac voltage that can be applied for a relatively long duration to the capacitor so as to ensure that no damage is done to the condenser is called the working voltage (WV). Voltages larger than the rated voltage can cause the breakdown of the dielectric. The breakdown of the dielectric causes short circuit, which may
Introduction
V C
I
−
RP IL
Tolerance D
Digit B
Figure 1.12 Leakage current
Multiplier C
(v) Temperature coefficient: Temperature coefficient of a capacitor is the maximum change in its capacitance over a specified range of temperature and is expressed as parts per million per degree centigrade (PPM/°C).
+
Digit A
eventually lead to heating of the capacitor. It is possible that the capacitor may even explode. (iii) Tolerance: Tolerance is the range over which the value of C is allowed to vary from its nominal value and is expressed as ±10 percent or so. Thus, the value of a 100 µF capacitor with ±20 percent tolerance could lie anywhere between 80 µF and 120 µF. (iv) Leakage current: The dielectric is not a perfect insulator and as such may offer a relatively large insulation resistance, Rp, through which small current of the order of nA can flow and this current is called the leakage current, IL. This leakage current will discharge C if the supply voltage is removed (Figure 1.12).
9
Figure 1.13 Bands with color code
Capacitor Color Codes Capacitor color codes are shown in Table 1.2 and the bands in Figure 1.13. However, few more parameters such as temperature coefficient and WV are also depicted. Table 1.2 Color codes and tolerances of capacitors Color
Digits A, B
Black
0
100
20
Brown
1
101
1
Red
2
102
2
Orange
3
10
3
3
Yellow
4
104
4
Green
5
105
5
Blue
6
106
6
Violet
7
107
7
Gray
8
108
8
White
9
109
9
Gold
10−1
5
Silver
10−2
10
Blank
Multiplier C
Tolerance, %D
20
10
Electronic Devices and Circuits
When connected to a dc source C gets charged to the source voltage with the time constant t = RC (Figure 1.14). The voltage variation in the capacitor is given as −t vC = V 1 − e t
(1.8)
iC iC
vC
R
vC
+ V
C −
iC
vC 0
t
(b) Variation of iC and vC
(a) Charging of C
Figure 1.14 Capacitor connected to a dc source
At t = 0, vC = 0 and at t = ∞, vC = V The current variation in the capacitor is given as −t
iC = At t = 0, iC =
V t e R
(1.9)
V and at t = ∞, iC = 0 R
Therefore, when there is a sudden change in voltage the capacitor behaves as a short circuit and when fully charged it behaves as an open circuit for dc. However, under ac conditions the capacitor offers a reactance, XC, given as XC =
1 1 = w C 2p fC
(1.10) I
where w = 2p f is the radial frequency of the applied signal (Figure 1.15); f is in Hertz and C is in Farads.
+ C V
I =
V = V ´ 2p fC XC
(1.11)
−
Figure 1.15 Sinusoidal signal applied to C
where V and I are the rms components of voltage and current. Example 1.8 For the circuit in Figure 1.15, V = 200 V, C = 1 µF, and f = 50 Hz. Calculate I. Solution: X C =
1 1 = = 3.185 kΩ 2 πfC 2 π × 50 × 1 × 10 −6
11
Introduction
I =
V 200 = = 62.79 mA XC 3.185
IL + L
VL
1.1.3 Inductors
r l
−
Inductor is a coil of wire often wound around a steel or ferrite core (Figure 1.16). The magnetic flux within the coil is
Figure 1.16 Voltage applied to an inductor
f=
mNA I l
(1.12)
where N is the number of turns in wire coil, A = πr2, is the crosssectional area of the coil, l is the length of the coil, and µ = µ0µr is the permeability of the core material. For free space (or air): μ0 = 1.26 μH/m and µr is relative permeability and is a dimensionless quantity. 2 From Faraday’s law, V = N d f = mN A di = L di dt l dt dt
and the inductance L =
mN 2 A l
(1.13)
(1.14)
I + +
From Figure 1.16, i = IL and from Eqn. (1.13) L=
V2 −
Vdt Volt second = Henry. = Ampere dI L
V
L is measured in henries.
+ V1
The energy stored in an inductor is E =
1 2 LI L joules 2
L2
−
(1.15)
L1
−
Figure 1.17 Inductors connected in series
Inductors in Series When two inductors are connected in series (Figure 1.17), the effective inductance is calculated as follows: V = V1 +V2 = L1 ∴ L = L1 + L2
dI dI dI dI + L2 = ( L1 + L2 ) = Leq dt dt dt dt (1.16)
If a number of inductors is connected in series, then the effective inductance is the sum of the individual inductances.
12
Electronic Devices and Circuits
Inductors in Parallel When two inductors are
I
connected in parallel (Figure 1.18), the effective inductance is calculated as follows:
+
I1
I2
L1
L2
V
1 dI d ( I1 + I 2 ) dI1 dI 2 V V 1 = = + = + =V + dt dt dt dt L1 L2 L1 L2
−
V=
∴ Leq =
dI 1 dI = 1 1 dt Leq dt L + L 1 2 1
Figure 1.18 Inductors connected in parallel
1 1 + L1 L2
(1.17)
An inductor has an associated resistance (in which case it is called a choke) and hence a practical inductor is represented as shown in Figure 1.19. + I
RL
≡
V L
Choke
−
Figure 1.19 Practical inductor
The two pertinent characteristics of an inductor are (i) dc resistance and (ii) the maximum dc current. (i) dc resistance: Inductors have very low resistance for dc signals, usually of the order of a few ohms. (ii) The maximum dc current of an inductor is the maximum level of continuous direct current that can be passed through an inductor with no damage. For a dc voltage as input, the inductor offers only the dc resistance. However, for an ac input voltage an inductor offers a reactance, XL = wL = 2pfL.
1.2 THE NATURE OF ATOM An atom is the smallest particle that retains the properties of an element. Atoms comprise three types of particles: protons that have positive charge; neutrons that have no charge; and electrons that have negative charge. Protons and neutrons reside in the nucleus. The mass of an electron is very small and is 9.108 × 10−31 kg. The mass of a proton and neutron is 1,800 times larger than that of an electron. Therefore, protons and neutrons are responsible for most of the atomic mass. The charge of an electron is expressed in Coulombs and is equal to 1.602 × 10−19 C. The number of protons (electrons) in an atom is specified by the atomic number, Z.
Introduction
13
Electrons circle the nucleus at different elliptical orbits called shells. A definite energy level is associated with each shell. A shell can accommodate only a fixed number of electrons, namely, 2n2 electrons. The occupancy of each shell is indicated in Table 1.3. Table 1.3 Shells and the number of orbital electrons Number of orbital electrons = 2n2
n
Shell called as
1
K
2 × 12 = 2
2
L
2 × 22 = 8
3
M
2 × 32 = 18
4
N
2 × 42 = 32
A Li atom has one valence electron in the L shell and a Si atom has four valence electrons in the M shell (Figure 1.20).
M L
L +3
K
+14 K
Lithium Silicon
Figure 1.20 Electrons in orbits for Li and Si atoms
Only if the inner shells are completely filled the electrons in an atom usually occupy outer shells. The farther is the electron away from the nucleus the greater is the energy associated with it. The electrons located in the innermost shells are tightly bound to the nucleus and those in the outermost shell are loosely bound and are called valence electrons. The electrical and chemical properties of semiconductor materials are essentially decided by these valance electrons. When an electron moves from a lower energy level to a higher energy level, energy is absorbed by the atom. When an electron moves from a higher to a lower energy level, energy is released, often as light.
1.2.1 Energy Levels The energy associated with each orbit can be calculated. Consider the hydrogen atom in which an electron moves in circular motion with a velocity v and the radius of the orbit is rn (Figure 1.21). For the electron to remain in orbit, the outward centrifugal force must be equal to electrostatic force of attraction between the electron and the nucleus. e2 Electrostatic force of attraction = (1.18) 4pe 0 rn2
14
Electronic Devices and Circuits
2 Outward centrifugal force = mv rn From Eqs (1.18) and (1.19) 2
e mv = 4pe 0 rn2 rn
2
V
mv 2/rn
(1.19)
e 2/4π e 0rn 2 rn
(1.20) +
2
Or
mv 2 =
e 4pe 0 rn
(1.21)
The kinetic energy of the electron 1 2 e2 mv = 2 8pe 0 rn
Figure 1.21 Motion of electron in hydrogen atom
(1.22)
Bohr has stipulated that only those orbits are possible for which the angular momentum of the electron is equal to an integral multiple of h (quantization of angular momentum), where h is 2p the Plank’s constant in Jouleseconds. nh ∴ Angular momentum = mvrn = (1.23) 2p v= ∴
mv 2 =
nh nh and mv = 2pmrn 2prn
nh nh n2 h2 × = 2prn 2pmrn 4p 2 mrn2
(1.24)
From Eqs (1.21) and (1.24) e2 n2 h2 = 4p ∈0 rn 4p 2 mrn2 Or
rn =
e 0 n2 h2 pme 2
(1.25)
Mass of an electron, m = 9.107 × 10 −31 kg Charge of an electron, e = 1.602 × 10−19 C Plank’s constant, h = 6.626 × 10−34 Js Permittivity of free space, ε0 = 8.854 × 10−12 F/m ∴ rn =
e 0 n2 h2 8.854 × 10 −12 × (6.626 × 10 −34 )2 n2 = 0.529 × 10 −10 × n2 m = pme 2 p × 9.107 × 10 −31 × (1 1.602 × 10 −19 )2
For the first shell (K shell), n = 1, therefore, r1 = 0.529 × 10−10 × 12 m 1 Å = 10−10 m rn = n2 × 0.529 Å
(1.26)
15
Introduction
The potential energy of an electron at a distance rn from the nucleus =
−e 2 4p ∈0 rn
(1.27)
Using Eqn (1.22) and (1.27) the energy associated with an orbit or shell is 1 e2 e2 e2 −e 2 Wn = mv 2 − = − = 2 4p ∈0 rn 8p ∈0 rn 4p ∈0 rn 8p ∈0 rn
(1.28)
Substituting the value of rn from Eqn. (1.25) in Eqn. (1.28) Wn =
pme 2 −e 2 −e 2 − me 4 = × = 8p ∈0 rn 8p ∈0 e 0 n2 h2 8 ∈0 2 n2 h2
(1.29)
Equation 1.29 gives the energy of the nth shell. The energy associated with each shell can be obtained by substituting different values of n, n = 1, 2, 3. − me 4 −9.107 × 10 −31 × (1.602 × 10 −19 )4 = − 21.78 × 10 −19 = −12 2 −34 2 2 2 8 ∈0 h 8 × (8.854 × 10 ) × (6.6626 × 10 )
∴ Wn =
−21.78 × 10 −19 J n2
The energy acquired by an electron in rising to a potential of 1 V is defined as 1 eV and 1 eV = 1.602 × 10−19 J Or
∴ Wn =
−21.78 × 10 −19 13.61 = − 2 eV n 1.6 × 10 −19 n2
(1.30)
For n = 1, W1 = −13.61 eV and for n = ∞, W∞ = 0 eV Table 1.4 shows rn and Wn for n = 1, 2, 3, 4. Table 1.4 rn and Wn for n = 1, 2, 3, 4 n rn = n2 × 0.529 Å
Wn = −
13.61 eV n2
1(K shell)
2(L shell)
3(M shell)
4(N shell)
r1 = 0.529 Å
r2 = 2.116 Å
r3 = 4.761 Å
r4 = 8.464 Å
W1 = −13.61 eV
W2 = −3.40 eV
W3 = −1.512 eV
W4 = −0.850 eV
The energy level diagram is shown in Figure 1.22. When a transition occurs from one stationary orbit, say from a state with associated energy W2 to a state with associated energy W1, then energy is radiated with a frequency f given by
16
Electronic Devices and Circuits n=∞ n=7 n=6
E∞ = 0 E7 E6 = −0.38 eV
n=5
E5 = −0.54 eV
n=4
E4 = −0.854 eV
n=3
E3 = −1.512 eV
10 11 12 13 Paschen lines (IR)
n=2
E2 = −3.40 eV
6789 Balmer lines (Visible)
Forbidden region
n=1
1 2 345
Ground state
E1 = −13.61 eV
Lyman lines (UV)
Figure 1.22 Energy level diagram
f =
W2 − W1 h
(1.31)
where h is the Planck’s constant and f is in Hz. For the first orbit n = 1 and W1 = −13.61 eV. This is called the ground state. If a photon is at higher energy levels it is said to be in an excited state. When a photon drops from an excited state to the second orbit, Balmer lines are observed and these transitions are in the visible region. All transitions that drop to the ground state emit photons in the Lyman lines and these transitions are in the UV region. All transitions that drop to the third orbital are known as the Paschen lines and are near IR region. It may be noted that to remove an electron from an outer orbit less energy is imparted to it. Similarly, to remove an electron from the inner orbits a relatively large amount of energy is required to be expended.
1.3
ELECTRONIC STRUCTURE OF THE ELEMENTS
The principal quantum number n refers to the shell or energy level to which the electron belongs. The shells K, L, M, N,… consist of inner subshells that further consist of orbitals. Each orbital 1 1 will have two electrons with opposite spins, that is, + (clockwise) and − (anticlockwise). 2 2 The subshell(s) present in n = 1 → s. The subshell s consists of one orbital, that is, two electrons. n = 2 → s, p. The subshell p consists of three orbitals, that is, six electrons. n = 3 → s, p, d. The subshell d consists of five orbitals, that is, 10 electrons n = 4 → s, p, d, f. The subshell f consists of seven orbitals, that is, 14 electrons, and so on.
Introduction
17
1s2 2s2 2p6 3s2
1s 2
3p6 4s2 2s
2p
2 3s
Increasing energy
3d10 4p6 5s2
6 3p
2
6 4s
10
10
6 5s
5p
2 6s
5f 14
6d
6p 10 7p
5f14 6d10 7p6 8s2
14
10
6 7s
4d
5d
6
2
4f14 5d10 6p6 7s2 4d
4p
2
4d10 5p6 6s2
3d
6f 14
7d
7f
Figure 1.23 Order of subshell filling
The filling of the electrons takes place in the increasing order of the energies of the orbitals (Aufban principle) (Figure 1.23). The order of filling of electrons is as follows: 1s 2s 2p 3s 3p 4s 3d 4p 5s 4d 5p 6s 4f 5d 6p 7s 5f 6d 7p Or, the number of electrons in the orbitals is as follows: 1s2 2s2 2p6 3s2 3p6 4s2 3d10 4p6 5s2 4d10 5p6 6s2 4f14 5d10 6p6 7s2 5f14 6d10 7p6 Based on the above discussion, it is possible to write down the electron configurations in some of the fourth group elements as shown in Table 1.5. Table 1.5 Electron configuration of some fourth group elements Element
Atomic number
Electron configuration
C
6
1s 2s 2p
Si
14
1s2 2s2 2p6 3s2 3p2
Ge
32
1s2 2s2 2p6 3s2 3p6 4s2 3d10 4p2
Sn
50
1s2 2s2 2p6 3s2 3p6 4s2 3d10 4p6 5s2 4d10 5p2
Pb
82
1s2 2s2 2p6 3s2 3p6 4s2 3d10 4p6 5s2 4d10 5p6 6s2 4f14 5d10 6p2
2
2
2
1.3.1 Energy Band Theory of Crystals Metals, depending on the chemical composition, have closely packed atoms or ions and exhibit a crystal lattice structure with a periodic array of the atoms. Metals, diamond, and graphite are some examples of crystalline solids. The smallest structure is the unit cell that repeats itself through
18
Electronic Devices and Circuits
Energy of electrons
eV
the crystal. The bodycentered cubic and the hexagonal closepacked unit cells are shown in Figure 1.24. The behavior of the electron orbits of an atom in a closely packed crystal lattice is described by the Energy band theory of crystals. When atoms are closely packed the electrons in the outer orbits belong not only to the parent atom but also to the neigh(a) Cubic bodycentered (b) Hexagonal boring atoms, in which case is said that covaFigure 1.24 Unit crystal lattice examples lent bonds are formed. Formation of these covalent bonds may appear as though the electrons belong to the entire crystal. The result is that the discrete energy levels cease to exist, instead energy bands are formed. The uppermost band that contains electrons is called the valence band and the lowermost band that is empty is called Conduction band the conduction band. The energy band gap that exists between these two bands is called the forbidden gap (Figure 1.25). If Forbidden gap an electron in the valence band acquires sufficient energy, it breaks free from the covalent bond and jumps into the conducValence band tion band. On the application of an external electric field, these electrons in the conduction band account for the electric current. The conductivity of the material depends on the energy Figure 1.25 Energy bands in crystal gap between the valence band and the conduction bands.
1.3.2 Insulators, Conductors, and Semiconductors Depending on the material, the forbidden gap can be large, small, and can even be nonexistent. It is the width of the forbidden energy gap that defines the distinction between insulators, semiconductors, and conductors. The forbidden energy gap is large for the insulators, typically of the order 5 eV or more (Figure 1.26(a)). For the semiconductors this energy gap is typically of the order 1 eV (Figure 1.26(b)). For the conductors the forbidden gap does not exist and the conduction and valence bands overlap (Figure 1.26(c)). By now it is known that materials are grouped into three categories depending on their ability to conduct electricity: (i) Conductors: Silver, copper, aluminum, etc., contain free electrons that are responsible for conduction and are called conductors. The larger the number of free electrons, the greater is the current. Conductors offer a very low resistance, typically less than 10−8 Ωm. (ii) Insulators: Materials such as glass, ceramic, quartz, bakelite, rubber, etc., have their valence electrons very tightly bound to the nucleus. As such a very large energy is required to remove the electron from the attracting force of the nucleus. Such materials are called insulators. Insulators have high resistivity, typically greater than 1010Ωm. They are poor conductors of electricity. (iii) Semiconductors: Materials whose conductivity lies between that of conductors and insulators are called semiconductors. Germanium and silicon have resistivity of the order of 102 Ωm. Some important semiconductors are silicon (Si), germanium (Ge), and galliumarsenide (GaAs). The resistivity chart is shown in Table 1.6.
Valence band
(a) Insulator
Conduction band Forbidden gap = 1 eV Valence band
Energy of electrons
eV Forbidden gap = 5 eV
Energy of electrons
eV Energy of electrons
Conduction band
19
eV
Introduction
(b) Semiconductor
Conduction band Overlap of valence and conduction bands Valence band
(c) Conductor
Figure 1.26 Insulators, semiconductors, and conductors
Table 1.6 Resistivity chart Material Conductors
Semiconductors
Resistivity Ω − m
Silver
1.6 × 10−8
Gold
2.4 × 10−8
Carbon
3.5 × 10−5
Germanium
4.6 × 10−1
Silicon
6.4 × 102
Glass
1.0 × 1010
Quartz
7.5 × 1018
Insulator
1.4
SEMICONDUCTORS
Semiconductors are classified as (i) intrinsic or pure semiconductors and (ii) extrinsic or impure semiconductors.
1.4.1 Intrinsic or Pure Semiconductors Figure 1.27 shows how atoms of Ge or Si combine to form one crystal. Covalent bonds are formed by the sharing of the valence electrons by the neighboring atoms. At absolute zero temperature 0 K (−273.15°C), as no energy is imparted, all the electrons in the outer orbits remain in the valence bands. Consequently, the semiconductor behaves as an insulator. However, at room temperature, some of the electrons in the outer orbits may acquire sufficient energy to jump to the conduction band and can be available as free electrons. The energy required to break the covalent bonds in Ge is 0.72 eV and that in Si is 1.12 eV. Si and Ge have the same crystal structure and identical characteristics and they are the most widely used semiconductor materials. When energy is imparted to an atom, an electron (−ve charge) is removed from the valence band of an atom, in which case a hole is said to be created. In pure Si or Ge, there will be as many holes as there are electrons and these combinations are called electron–hole pairs. Electrons and
20
Electronic Devices and Circuits Ge
Ge
+4
+4
Ge +4
Valence electrons Ge Ge
Ge +4
+4
+4
Covalent bond
+4
+4
+4
Ge
Ge Ge
Figure 1.27 Twodimensional representation of Ge crystal
holes are present in equal numbers and this concentration is called intrinsic concentration and is indicated as n = p = ni (1.32) where n is the number of free electrons per unit volume p is the number of free holes per unit volume ni is the intrinsic concentration When an atom loses an electron, it is said to be ionized (Figure 1.28).
Ge
Ge
+4
+4
Ge +4
Valence electrons Ge Ge
Ge +4
Broken covalent bond
+4
+4
Hole
Covalent bond
+4
+4
+4
Ge
Ge Ge Free electron
Figure 1.28 Ge crystal at room temperature
Introduction
21
1.4.2 Conduction in Intrinsic Semiconductors An intrinsic semiconductor at room temperature has a fewer number of electrons in the conduction band and an identical number of holes in the valence band. On the application of an external electric field, free electrons move toward the positive terminal of the battery and the holes toward the negative terminal, thereby constituting an electric current. However, it is to be noted here that in a conductor the current is due to electrons, whereas in a semiconductor the current is essentially due to two types of charge carriers–electrons and holes (Figure 1.29). Electron ﬂow
Hole ﬂow
External emf
Figure 1.29 Current flow in an intrinsic semiconductor
1.4.3 Fermi Level in an Intrinsic Semiconductor Fermi energy level is defined as the highest occupied energy level found in that material at absolute zero temperature (0 K or −273.15°C). It is a reference energy level. The energy band diagram of an intrinsic semiconductor is shown in Figure 1.30. The top of energy level of the valence band is designated as EV and the bottom of the energy level of conduction band is designated as EC. The EF is the energy of Fermi level. E Conduction band EC EF
EG
EV Valence band
Figure 1.30 Energy band diagram of an intrinsic semiconductor
Let the energy density of states be N(E) which gives the number of states between E and E + dE. NC(E) represents the energy density of electrons in the conduction band and N V ( E ) represents the
22
Electronic Devices and Circuits
energy density of holes in the valence band. For energies that are close to the extremes of these two bands, the density of states has a quadratic dependence with E: 3
1 2m 2 NC ( E ) = 2 2 c 2p h
( E − EC )
(1.33)
(EV − E )
(1.34)
3
1 2m 2 NV (E ) = 2 2v 2p h
h is the normalized Planck’s constant (h = 6.626 × 10−34 Js) and mc and mv are the 2p average effective masses of the conduction and the valence bands. For a direct gap semiconductor, where h =
mc and mv are the effective masses of an electron and the hole in the crystal. The probability for an electron to occupy a level with a given energy E is given by the Fermi– Dirac distribution function: 1
f ( E ) = fE =
(E − E )
(1.35)
F
1+ e
kT
where k = 1.38 × 10−23 JK−1 is the Boltzmann constant, T the temperature, and EF the Fermi energy. The probability for a hole to occupy a level of energy E is given by (1 − f(E)) because a hole is by definition the absence of an electron. The electron density n [cm−3] in the conduction band is obtained by integrating, over the range of energies accessible by electrons in the band, the number of states that may be occupied by electrons of energy E, weighted by the probability to find an electron having this given energy: n=∫
+∞ EC
N C ( E ) . f ( E ) dE
(1.36)
Similarly, the hole density p [cm−3] in the valence band is written as follows: p =∫
Ev −∞
N V ( E ) .[1 − f ( E )]dE
(1.37)
For a semiconductor whose Fermi level EF is located more than 3 kT away from the extremes, the Fermi distribution function can be written under the form of a simple exponential, so that the expressions for the charge carriers densities become: − (EC − EF )
n = NC e where N C = ∫
+∞ E
(E
and p = N V e
NC (E ). e
kT
(1.38)
− (E − EC ) kT
dE
C
V
− EF )
kT
(1.39)
Introduction
where N V = ∫
EV −∞
N V (E ) e
(
− E − Ev kT
23
)
dE
NC and NV are called the effective densities of states and are given as 3
2pme kT 2 NC = 2 h2
(1.40)
where me is the effective mass of the electron. 3
2pm p kT 2 NV = 2 h2
(1.41)
where mp is the effective mass of the hole. From Eqs (1.38) and (1.39), the product of the two densities is given as np = ni2 − (EC − EF )
ni 2 = N C e
kT
ni 2 = N C N V e ni =
− (E V − EF )
NVe
kT
= NC N V e
− EC + EF + E V − EF kT
− ( EC − E V ) kT
NC N V e
(1.42)
− ( EC − E V ) 2 kT
− EG
= N C N V e 2 kT
where ni is the density of intrinsic carriers (for Si at 300 K, ni = 1010 cm−3). ni is seen to be independent of the position of the Fermi level.
1.4.4 Calculation of the Intrinsic Fermi Energy For an intrinsic semiconductor the electron hole densities are equal. n = p = ni Using Eqs (1.38) and (1.39), − (EC − EF )
n = NC e − (EC − EF )
NC e
kT
(E
= NVe
V
− EF )
kT
− (E V − EF )
kT
kT
p = NVe −E NV =e NC
C
+ EF − E V + EF kT
2 EF − (EC + E V )
=e
kT
Taking logarithms, (E + EV ) 2 EF − C 2 = ln N V kT NC
EF −
( EC + E V ) = 2
kT N V ln 2 NC
24
Electronic Devices and Circuits
EF =
( EC + E V ) + 2
kT N V ln 2 NC
(1.43)
where EF is the Fermi level of the intrinsic semiconductor and is designated as EFi. At room temperature kT is very much lower than the energy gap. EFi ≅
( EC + E V ) 2
(1.44)
The Fermi level of an intrinsic semiconductor lies in the middle of the forbidden gap.
1.4.5 Mass Action Law From Eqn (1.42), under thermal equilibrium, the product of the electron and hole density in an extrinsic semiconductor is always equal to the square of the intrinsic carrier density. ni2 = N C N V e
− ( EC − E V ) kT
= np
(1.45)
This property is referred to as the mass action law. In an intrinsic semiconductor n = p = ni, the number of holes is the same as the number of electrons. If, however, a fifth group impurity is added then the extrinsic semiconductor is an Ntype semiconductor in which the electron concentration increases very much but the hole concentration decreases. Alternately, if a third group impurity is added, then the extrinsic semiconductor is a Ptype semiconductor in which the hole concentration increases very much but the electron concentration decreases. Under thermal equilibrium np = ni2, is constant and is independent of the amount of doping. Thus, the mass action law is a powerful relation that enables to quickly find the hole density if the electron density is known or vice versa.
1.4.6 Extrinsic Semiconductors In an intrinsic semiconductor at room temperature the electron–hole pairs generated account for a small electron current and practically zero hole current on account of recombination. However, for a semiconductor to be useful its conduction properties should be increased. The electrical conductivity of the intrinsic semiconductor can be increased by adding impurities (one atom per million atoms). Then the semiconductor is called an extrinsic or impure semiconductor. Adding impurity atoms to a pure semiconductor is called doping. Extrinsic semiconductors are of two types: (i) Ntype and (ii) Ptype.
NType Semiconductors When a small number of fifth group impurities such as bismuth, antimony, arsenic, and phosphorus is added to a pure semiconductor during crystal growth, the resulting semiconductor is called an Ntype semiconductor. The fifth group atoms have five valence electrons and pure Ge or Si atoms have only four valence electrons. The four valence electrons of either Ge or Si form covalent bonds with four valence electrons of the impurity atom and the fifth valence electron of the impurity atom is not covalently bonded. It is loosely bound to the parent impurity atom (Figure 1.31). By imparting a very small amount of energy it is possible to detach the electron from the binding force of the parent atom. The amount of energy that is needed to remove the electron from the valence band is typically 0.01 eV for Ge and 0.05 eV for Si. As the impurity atom donates its excess electron it is called the donor atom.
Introduction Ge
Ge
+4
+4
25
Ge +4
Valence electrons As
Conduction band
+4
+5
Energy
Ge
Ge +4
Free electrons Valence band
Covalent bond
Holes +4
+4
+4
Ge
Ge Ge Free electron
Figure 1.31 (a) Covalent bonds with fifth group impurity (b) energy bands in Ntype semiconductor
When donor atom loses an electron, it becomes an immobile positive ion. An Ntype semiconductor has a fairly large number of electrons and a smaller number of holes. Hence, electrons are called majority carriers and holes are called minority carriers. Conduction in this type of material is essentially through electrons. When an electric field is applied electrons move toward the positive terminal of the battery, constituting an electric current (Figure 1.32). Immobile positive donor ions Electron ﬂow +
+
+
+
+
+
+
+
Hole ﬂow
External emf
Figure 1.32 Conduction in Ntype semiconductor
An Ntype semiconductor has a higher electron density n and a lower hole density p than the same intrinsic semiconductor. Let ND be the donor density. Then n = ND. From the mass action law p=
ni 2 ND
(1.46)
26
Electronic Devices and Circuits
(
n = NC e
− E −E F C kT
)
(
ND = NC e
− E −E F C kT
)
(
e
− E −E F C kT
) =
NC ND
( EC − EF ) N = ln C kT ND EF = EC − kT ln
NC ND
The Fermi level of the Ntype semiconductor is EFn = EC − kT ln
NC ND
(1.47)
When the donor density is increased, the Fermi level moves closer to the edge of the conduction band. If ND = NC, the Fermi level enters the conduction band: the semiconductor is then said to be degenerate.
PType Semiconductor When a small number of third group impurities such as gallium, indium, aluminum and boron is added to a pure semiconductor during crystal growth, the resulting semiconductor is called a Ptype semiconductor (Figure 1.33). The third group atoms have three valence electrons and pure Ge or Si atoms have four valence electrons. The three valence electrons of either Ge or Si form covalent bonds with three valence electrons of aluminum or boron atom and only three covalent bonds are completed. In the fourth covalent bond Ge or Si atom only contributes to one valence electron and there is a shortage of one electron, which is called a hole. There will be as many number of holes as there are impurity atoms. As the impurity atom accepts one electron, the impurity atom is called an acceptor atom. When an acceptor atom accepts an electron the atom becomes a negatively charged ion, which is immobile. The hole moves from one atom to the other. A Ptype semiconductor has a fairly large number of holes and a smaller number of electrons. Hence, holes are called majority carriers and electrons are called minority carriers. Conduction in this type of material is essentially through holes. When an electric field is applied holes move toward the negative terminal of the battery, constituting an electric current (Figure 1.34). A Ptype semiconductor has a higher hole density p and a lower electron density n than the same intrinsic semiconductor. Let NA be the acceptor density. Then p = NA. From the mass action law n=
p = NVe
ni 2 NA
(EV − EF )
(EV − EF )
kT
kT
NA = NVe
(1.48)
(EV − EF ) e
kT
=
NA NV
27
Introduction Ge
Ge
+4
+4
Ge +4 Broken covalent bond B Ge
Ge +4
+3
Conduction band Energy
Hole
Valence electrons
+4
Electrons Holes
Covalent bond +4
+4
Valence band
(b)
+4
Ge
Ge Ge (a)
Figure 1.33 (a) Covalent bonds with third group impurity (b) energy bands in Ptype semiconductor Electron ﬂow
− −
− −
Negative ions
−
−
−
−
Hole ﬂow
External emf
Figure 1.34 Conduction in Ptype semiconductor
(EV − EF ) = ln N A kT
NV
EF = E V − kT ln
NA NV
The Fermi level of the Ptype semiconductor is EFp = E V + kT ln
NV NA
(1.49)
When the acceptor density is increased, the Fermi level moves closer to the edge of the valence band. If NA = NV , the Fermi level enters the valence band: the semiconductor is then said to be degenerate.
1.4.7 Conductivity of Semiconductor Materials In a conductor the conduction is mainly due to electrons and the conductivity of a conductor is given as
28
Electronic Devices and Circuits
s = ne me However, in a semiconductor the conduction is due to electrons and holes as well. Hence, the conductivity due to electrons in a semiconductor can be written as s n = ne me and that due to holes as s p = pe mp
The total conductivity is given as
(
s = ne me + pe mp = e nme + pmp
)
(1.50)
where n = electron density (number of electrons in unit volume) p = hole density e = charge of an electron v me = = mobility of an electron E v = drift velocity E = electric field Meters v Meter 2 Second = = me = Volt E Voltsec Meter mp = mobility of a hole The resistivity r =
1 1 = s e nme + pmp
(
)
(i) Conductivity of intrinsic semiconductor: In an intrinsic semiconductor n = p = ni. Therefore, from Eqn. (1.50)
(
s i = ni e me + ni e mp = eni me + mp
)
(1.51)
If an electric field e is applied, then
(
)
Current density, J = s i e = eni me + mp e
(1.52)
If A is the crosssectional area of the semiconductor
(
)
I = J A = eni me + mp eA
(1.53)
(ii) Conductivity of an Ntype semiconductor: In an Ntype semiconductor n >> p If n = ND, then from Eqn. (1.50) s n = N D e me
(1.54)
(iii) Conductivity of a Ptype semiconductor: In a Ptype semiconductor p >> n If p = NA, then (1.55) r = N em p
A
p
Introduction
29
1.4.8 Drift Current When an electric field is applied to a semiconductor material the electrons and holes drift to the positive and negative terminals of the battery. The drift current density of electrons is J n(drift ) = s n e = N D e me E
(1.56)
And the drift current density of holes is J p(drift ) = s p e = N A e mp E
(1.57)
Example 1.9 The following data is available for an intrinsic semiconductor at 300 K: The mobility of electrons = 0.39 m2/Vs and the mobility of holes = 0.19 m2/Vs and ni = 2.4 × 1019/m3. Calculate the resistivity of the material.
(
)
s i = eni me + mp = 1.6 × 10 −19 × 2.4 × 1019 (0.39 + 0.19)
Solution:
= 2.227( Ω − m)−1 Resistivity, ri =
1 1 = = 0.449 Ω − m s i 2.227
Example 1.10 Calculate the number of donor atoms for an Ntype semiconductor whose resistivity is 0.449 Ω  m. The mobility of the electrons is 0.6 m2/Vs. Solution: s n = N D e me ∴ ND =
sn 1 1 = = rn e me 0.449 × 1.6 × 10 −19 × 0.6 e me
N D = 2.32 × 1019 /m 3 Example 1.11 A pure Ge at 300 K having the density of the charge carriers as 2.25 × 1019/ m 3 is doped with impurity phosphorus atoms at 1 in 106. The electron and hole mobilities are 0.4 m2/Vs and 0.2 m2/Vs, respectively. The number of intrinsic atoms is 4 × 1028 atoms/m3. If all the impurity atoms are ionized, find the resistivity of the Ntype semiconductor. Solution: Given:
ni = 2.25 × 1019 /m3 me = 0.4 m 2 /Vs mp = 0.2 m 2 /Vs Doping concentration = 1 × 106
30
Electronic Devices and Circuits
28 ∴ Impurity atoms/m3 = Number of intrinsic atoms = 4 × 10 = 4 × 1022 /m3 106 106
If all the impurity atoms are ionized, n = 4 × 1022 /m 3 . From the law of mass action np = ni2 Therefore, the hole concentration p = rn =
(
19 ni2 2.25 × 10 = n 4 × 1022
2
)
= 1.26 × 1016 /m 3
1 1 1 = = −19 22 s n e n me + p mp 1.6 × 10 4 × 10 × 0.4 + 1.26 × 1016 × 0.2
(
≅
)
(
1 1.6 × 10
−19
(4 × 10
22
× 0.4
)
)
= 0.39 × 10 −3 Ω − m
1.4.9 Diffusion Current Diffusion current exists in a semiconductor, as electrons and holes diffuse from high concentration region to low concentration region. Consider Figure 1.35 in which there is a large concentration of holes on the left when compared to the right of the vertical line Y1Y2. Due to the natural process of diffusion holes diffuse from left to the right, resulting in hole current. Diffusion of holes from high concentration to low concentration Y1 p
Hole gradient +
Slope = −
dp dX
∆p
Y2
X
∆x
Figure 1.35 Diffusion of holes in random motion
The diffusion current density is proportional to the rate of change of hole concentration with distance x (concentration gradient) and is given as J p(diffusion) = qDp Dp = diffusion coefficient in m2/s dp = concentration gradient of holes dx
dp dx
(1.58)
Introduction
31
Similarly, diffusion current density of electrons that move from right to left is J n(diffusion) = qDn
dn dx
(1.59)
The total electron current density due to drift and diffusion, from Eqs (1.56) and (1.59), is J n = J n(drift ) + J n(diffusion) = N D q me e + qDn
dn dx
D dn = q me N D e + n me dx
(1.60)
1.4.10 Einstein’s Relationship The diffusion coefficient D and the mobility µ are related to each other by the following equation, known as Einstein’s equation: Dp Dn kT = = (1.61) q mp mn At room temperature (300 K),
kT = 0.026 V q Dp = mp
Dn = 0.026 V mn
(1.62)
It is known that for Ge at 300 K, me = 0.38 m 2 / Vs, then Dn = 0.38 × 0.026 = 0.0099 m 2 /s
1.4.11 Mean Lifetime and Diffusion Lengths of Charge Carriers In an intrinsic semiconductor at room temperature electron hole pairs are generated due to thermal agitation. It is possible that some electrons may recombine with holes and at the same time new electron hole pairs can be generated. The instant at which a charge carrier is generated to the time instant at which it recombines is known as the lifetime of the charge carrier. If tp and te are the time intervals for which holes and electrons exist before recombination, then these two time intervals are called the lifetimes of the holes and electrons, respectively, and the average lifetime is called the mean lifetime. When charge carriers move from a high concentration region to a low concentration region, their concentration decreases exponentially due to recombination. The average distance covered by a charge carrier before recombination is called the diffusion length and is designated as Lp for holes and Le for electrons. Lp = Dp t p
Le = Dn t n
where Dp and Dn are the diffusion constants for holes and electrons, respectively.
(1.63)
32
Electronic Devices and Circuits
1.4.12 The Continuity Equation In a semiconductor, charges drift due to an electric field, diffuse due to concentration gradient, and recombine due to the presence of charges of opposite polarity. The differential equation that governs all these effects, based on the fact charge can neither be created or destroyed, is the continuity equation. The concentration of carriers in a semiconductor material varies with time and distance. p holes/m3
Area A
Ip
Ip + dIp
x
x + dx
Figure 1.36 Law of conservation of charge
Consider a very small element of volume having area, A, and length, dx, in which the average hole 3 concentration is p/ m as shown in Figure 1.36. The xdimensions of n and p regions are assumed to be large when compared to the diffusion length of the respective regions. Let I p be the current entering the volume at x at time t and Ip + dIp the current leaving at x + dx about the same time t, then the number of Coulomb/s decrease in the volume is dIp. From the definition of current Ip =
NA q t
(1.64)
where NA is the number of holes. Hence, it can be said that dI p = dI p
Or
q
=
qdN A t dN A t
(1.65)
= Decrease in the number of holes per second Volume = Adx ∴ dp =
dN A Adx
33
Introduction
Dividing both sides of Eqn. (1.55) by Adx dI p dN A 1 1 dN A 1 dp × = × = × = Adx q Adx t Adx t t
(1.66)
= Decrease in hole concentration per second dI p dp 1 A 1 dJp ∴ = × = × dx t q q dx
(1.67)
Let be p0 the hole concentration under thermal equilibrium and tp the mean lifetime of the hole. Then increase in hole concentration per second is g=
p0 tp
(1.68)
p Decrease in the number of holes/s due to recombination per unit volume = 0 tp As charge can neither be crated nor destroyed,
(1.69)
dp = (Increase in hole concentration/s) − (Decrease in hole concentration/s) dt Using Eqs (1.67), (1.68), and (1.69), dp p0 p 1 dJ P p0 − p 1 dJ P = − + − = dt t p t p q dx q dx tp
(1.70)
As p is a function of both x and t, the derivatives in Eqn. (1.70) become partial derivatives. ∂p p0 − p 1 ∂J p = − ∂t tp q dx
(1.71)
Magnetic ﬁeld perpendicular to I (into the paper) B
1.4.13 The Hall Effect The Hall effect can be used to determine the type of majority charge carriers as well as carrier concentration and mobility. Consider a thin, flat, uniform semiconductor bar (Figure 1.37). Let a voltage V be applied such that
I +
+
+
+
+
−
Holes − −
−
−
VH
Figure 1.37 Hall effect (positive VH )
34
Electronic Devices and Circuits
Magnetic ﬁeld perpendicular to I (into the paper) the current I flows from left to right (meaning that the current is carried by the positive charges) along B the length of the bar. Let, now, a uniform magnetic field B be applied perpendicular to the flat surface. I This results in the positive charges being deflected − − − − − upward. Consequently, the upper edge of the bar gets VH Electrons positively charged and the lower edge gets negatively + + + + + charged, resulting in a positive voltage, VH, between the upper and the lower edges of the semiconductor Figure 1.38 Hall effect (negative VH) bar. This voltage VH is called the Hall voltage. Alternately, if the current I is carried by the negative charges (electrons) that move from right to left (because current flow is opposite to the direction of the electron flow), then negative charges are deflected upward by the magnetic field. The upper edge of the bar, therefore, becomes negatively charged and the lower edge positively charged. The Hall voltage VH, now, is negative (Figure 1.38). It is now evident from the above inferences that it is possible to determine the type charge carriers depending on the polarity of the Hall voltage. The Hall voltage is given as
VH = vd wB
(1.72)
where vd is the drift velocity and w is the width of the bar. From Eqn. (1.72), it is seen that the Hall voltage is directly proportional to the magnitude of the magnetic field.
1.4.14 Basic Unbiased PN Junction It is already learnt that in a Ptype semiconductor holes are majority carries and electrons are the minority carriers. Similarly, in an Ntype semiconductor electrons are the majority carriers and holes are the minority carriers (Figure 1.39). Usually, electrons are uniformly distributed in the Ntype semiconductor and holes are uniformly distributed in the Ptype semiconductor. The N and Ptype bars are placed side by side, representing a PN junction. Few free electrons from the Nside crossover (diffuse) to the Pside of the junction attracted by the holes and fill the holes. These free electrons give to some atoms one more electron and create negative ion. Similarly, holes diffuse from the Pside to the Nside and give to some atoms a hole and create positive ion on the Nside near the junction. As negative ions are created on the Pside near the junction, the Pside acquires a negative voltage. At the same time as positive ions are created on the Nside near the junction, the Nside acquires a positive voltage. A layer is created on either side of the junction, which is devoid of charge carriers and is called the depletion, or the space charge, or the transition region. The thickness of the depletion region is usually 0.5 µm. The diffusion of the charge carriers creates a barrier potential, which is negative on the Pside and positive on the Nside. At equilibrium the barrier field prevents further movement of electrons; the majority carriers on the Nside to the Pside and holes, the majority carriers on the Pside to the Nside of the junction (Figure 1.40). However, minority carriers on either side, aided by the barrier potential, can crossover to the other side of the junction. The magnitude of the barrier potential can be calculated by knowing the doping densities and the junction temperature.
Introduction
Positive ions
Negative ions
Holes
Electron
−
−
− −
− − − −
+ +
+
+
+
+
+
−
−
− −
− − − −
+ +
+
+
+
+
+
−
−
− −
− − − −
+ +
+
+
+
+
+
Ptype semiconductor
Ntype semiconductor
Figure 1.39 P and Ntype semiconductors
Depletion region
−
−
− −
− −
− −
+ +
+
+
+
+
+
−
−
− −
− −
− −
+ +
+
+
+
+
+
−
−
− −
− − − −
+
+
+
+
+
+ +
(a) PN junction
Ptype
Hole concentration
Ntype Electron concentration
(b) Electron Hole concentrations Positive space charge + −
Negative space charge (c) Concentration of uncovered charges
VB 0 x0
x
(d) Variation of barrier potential
Figure 1.40 PN junction
Electrons Holes
35
36
Electronic Devices and Circuits
The concentration of electrons is the same as the concentration of the donor atoms and the concentration of the holes is the same as the concentration of the acceptor atoms. The barrier field can be found from Poisson equation: d 2V −r (1.73) = ∈ dx 2 where r is the charge density, ∈ is the permittivity, and V is the electrostatic potential at a distance x. Permittivity (∈) is a measure of the ability of a material to be polarized by an electric field. Integrating Eqn. (1.73) x −r −dV F= =∫ dx (1.74) x dx 0 ∈ The electrostatic potential at a point is x
Vx = − ∫ Fdx x0
(1.75)
This is the barrier potential, VB. VB can also be obtained as N N VB = VT ln D 2 A ni
(1.76)
Additional Solved Examples Example 1.12 Mobilities of electrons and holes in pure Ge at room temperature are 0.36 m2/Vs and 0.18 m2/Vs, respectively. If the density of electrons is 2.4 × 1019/ m 3, calculate its resistivity. Solution:
(
)
s i = eni me + mp = 1.6 × 10 −19 × 2.4 × 1019 (0.36 + 0.18) = 2.074 (Ω − m )
Resistivity, ri =
−1
1 1 = = 0.482 Ω − m s i 2.074
Example 1.13 To an intrinsic Si crystal (i) donortype impurity atoms are added so as to have an Ntype semiconductor having a resistivity of 10 −4 Ω − m. (ii) Acceptortype impurity atoms are added so as to have an Ptype semiconductor having a resistivity of 10 −4 Ω − m . Calculate the density of the impurity atoms added in each case: m e = 0.36 m 2 / V  s and m p = 0.18 m 2 / V − s . Solution: (i) s n = eN D me or ND = (ii) s p = eN A mp
1 = eN D me rn
1 1 = = 1.736 × 1023/ m 3 rn × e × me 10 −4 × 1.6 × 10 −19 × 0.36 or
1 = eN A mp rp
Introduction
NA =
37
1 1 = −4 = 3.472 × 1023/m3 rp × e × mp 10 × 1.6 × 10 −19 × 0.18 −1
Example 1.14 An Ntype Ge semiconductor has s n = 100 (Ω − cm ) and me = 0.39 × 10 4 cm / V − s. Calculate the position of the Fermi level with reference to the intrinsic Fermi level at 300 K. Solution: N D =
sn 100 1017 = = = 1.60 × 1017/ cm 3 e me 1.6 × 10 −19 × 0.39 × 10 4 1.6 × 0.39 EFn = EFi + kT ln
ND Ni
For pure Si n = p = 1.5 × 1010 /cm 3 at 300 K 10 3 For pure Ge n = p = 2.5 × 10 /cm at 300 K
k = Boltzmann constant in eV/K = 8.61 × 10 −5 eV/K
kT = 8.61 × 10 −5 × 300 = 0.026 eV 1.6 × 1017 EFn = EFi + 0.026 ln = EFi + 0.026 × 8.764 = EFi + 0.228 eV 2.5 × 1013
Example 1.15 A Ptype Ge semiconductor has hole density of 3.29 × 1017/ cm3. Calculate the position of the Fermi level with reference to the intrinsic Fermi level at 300 K. Solution: NA = 3.29 × 1017/ cm3 EFp = EFi + kT ln
NA Ni
For pure Ge n = p = 2.5 × 1013/cm 3 at 300 K k = Boltzmann constant in eV/K = 8.61 × 10 −5 eV/K
kT = 8.61 × 10 −5 × 300 = 0.026 eV 3.29 × 1017 = EFi + 0.026 × 9.48 = EFi + 0.246 eV EFP = EFi + 0.026 ln 2.5 × 1013
38
Electronic Devices and Circuits
Example 1.16 A Germanium Ntype semiconductor has its Fermi level at 0.2 eV below the conduction band edge. Estimate its dopant, majority, and minority carrier concentrations at equilibrium K. Assume ni = 2.5 × 1019/m3 and me = 1.2 m .
Solution: n = N C e
− ( EC − EF ) kT
We have m = 9.107 × 10 −31 kg, k = 1.38 × 10 −23 J/K, T = 300 K, and
h = 6.625 × 10 −34 Js , k in eV/K = 8.61 × 10 −5 eV/K 3
2 2p × 1.2 × 9.107 × 10 −31 × 1.38 × 10 −23 × 300 2pme kT = 3.29 × 1025 /m 3 NC = 2 =2 2 − 34 h2 6.625 × 10 3 2
(
(
n = NC e
− EC − EF kT
(
)
0.2 −5 × 300
= 3.290 × 1025 × e 8.62 ×10
)
= 14.46 × 1021 / m 3
2
)
2.5 × 1019 n2 = 4.32 × 1016/m 3 p= i = n 14.46 × 1021
Summary • Resistors can be classified as (i) carbon composition resistors; (ii) film resistors; (iii) wire wound resistors; and (iv) semiconductor resistors. • Electrolytic capacitors are polarized capacitors. Consequently, while connecting to a dc voltage the positive end of the voltage source should be connected to the positive terminal of C and the negative end to the negative terminal of C. Improper polarization can damage the capacitor. • Electrons circle the nucleus at different elliptical orbits called shells. A definite energy level is associated with each shell. A shell can accommodate only 2n2 electrons. • The forbidden energy gap is large for the insulators, typically of the order of 5 eV or more. For the semiconductors this energy gap is typically of the order 1 eV. For the conductors the forbidden gap does not exist and the conduction and valence bands overlap. • An intrinsic semiconductor at room temperature has a fewer number of electrons in the conduction band and an identical number of holes in the valence band, resulting in a small current on the application of an external field. • Fermi energy level is defined as the highest occupied energy level found in that material at absolute zero temperature (0 K or −273.15°C). It is a reference energy level. • When a small number of fifth group impurities such as bismuth, antimony, arsenic, and phosphorus are added to a pure semiconductor during crystal growth, the resulting semiconductor is called an Ntype semiconductor.
Introduction
39
• When a small number of third group impurities such as gallium, indium, aluminum, and boron are added to a pure semiconductor during crystal growth, the resulting semiconductor is called a Ptype semiconductor. • When an electric field is applied to a semiconductor material the electrons and holes drift to the positive and negative terminals of the battery, constituting a current called the drift current. Diffusion current exists in a semiconductor, as electrons and holes diffuse from a high concentration region to a low concentration region.
multiple ChoiCe QueStionS 1. An intrinsic semiconductor is characterized by _________ valence electrons. (a) 8 (c) 4
(b) 2 (d) 16
2. Pure germanium and silicon at absolute zero behave as (a) perfect conductors (b) insulators (c) Ntype semiconductors (d) Ptype semiconductors 3. In an Ntype material, majority carriers are (a) electrons (c) both electrons and holes
(b) holes (d) none of the above
4. In a Ptype semiconductor the minority carriers are (a) electrons (b) holes (c) both electrons and holes (d) none of the above 5. An electron that is in the conduction band has (a) no mobility (c) energy more than the one in valence band
(b) no energy (d) less than the one in valance band
6. When an electron jumps from the valence band to the conduction band, it leaves a vacancy, which is called (a) energy band (b) hole (c) covalent bond (d) electron–hole pair 7. Which one of the following is a doping material? (a) Ntype semiconductor (c) pentavalent atom
(b) Ptype semiconductor (d) uncovered charges
8. Energy band gap size for insulators is in the range __________ eV. (a) 1–2 (b) 2–3 (c) 3–4 (d) > 4 9. In an intrinsic semiconductor, number of electrons __________ the number of holes. (a) equal (b) greater than (c) less than (d) none of the above 10. Forbidden band lies (a) above the conduction band (c) between valence and conduction bands
(b) below the valance band (d) none of the above
40
Electronic Devices and Circuits
11. The concentration of the minority carriers in the Ntype semiconductor depends on (a) type of donor atom added (b) quality of intrinsic semiconductor (c) temperature of the material (d) number of donor atoms added 12. Fermi energy level for intrinsic semiconductors lies (a) at middle of the forbidden band gap (b) close to conduction band (c) close to valence band (d) above the conduction band 13. Fermi energy level for Ntype extrinsic semiconductors lies (a) at middle of the forbidden band gap (b) close to conduction band (c) close to valence band (d) above the conduction band 14. Fermi energy level for Ptype extrinsic semiconductors lies (a) at middle of the forbidden band gap (b) close to conduction band (c) close to valence band (d) above the conduction band 15. Electrical conductivity of the insulators is of the order: (a) 10 −10 (Ω − mm ) (c) 10 −10 (Ω − m )
−1
−1
(b) 10 −10 ( Ω − cm ) (d) 10 −8 (Ω − m )
−1
−1
16. Covalent bonding between electrons of adjacent atoms refers to: (a) the addition of an impurity (b) the sharing of valence electrons (c) the generation of excess electrons (d) the generation of excess holes 17. Mobile electrons are found (a) below the valence band (c) in the forbidden gap
(b) below the conduction band (d) in the conduction band
18. Mobile holes are found (a) in the valence band (c) in the forbidden gap
(b) below the conduction band (d) in the conduction band
19. Germanium doped with Arsenic will result in (a) an intrinsic semiconductor (c) an Ntype semiconductor
(b) an extrinsic semiconductor (d) a Ptype semiconductor
20. Silicon doped with Aluminum will result in (a) an intrinsic semiconductor (c) an Ntype semiconductor
(b) an extrinsic semiconductor (d) a Ptype semiconductor
21. The forbidden gap of the semiconductor material (a) does not vary with temperature (c) decreases with temperature
(b) increases with temperature (d) may increase or decrease
22. In an intrinsic silicon, the forbidden gap is (a) 1.12 eV (c) 3 eV
(b) 0.7 eV (d) 0.1 eV
23. In an intrinsic Ge, the forbidden gap is (a) 1.12 eV (c) 3 eV
(b) 0.7 eV (d) 0.1 eV
Introduction
41
24. The diffusion current in a semiconductor is influenced by (a) externally applied voltage (c) electric field
(b) concentration gradient of mobile charges (d) magnetic field
25. Electrons in the outermost orbit are called (a) valence electrons (c) donor electrons
(b) free electrons (d) acceptor electrons
26. A resistor with color bands red, violet, green, and black will have a value (a) 27 K ± 10% K (c) 270 K ± 5% K
(b) 2.7 M ± 20% K (d) 2.7 K ± 2% K
27. Which of the following doping schemes will produce a Ptype semiconductor? (a) germanium with phosphorus (c) germanium with antimony
(b) silicon with germanium (d) silicon with indium
28. The depletion region in a junction diode contains (a) both minority and majority charge carriers (c) only impurity atoms
(b) only majority charge carriers (d) only ions (immobile charges)
Short anSwer QueStionS 1. Three resistances R1 = 30 kΩ , R2 = 30 kΩ , and R3 = 30 kΩ are connected in series in a circuit. What is the effective resistance? 2. Three resistances R1 = 30 kΩ , R2 = 30 kΩ , and R3 = 30 kΩ are connected in parallel in a circuit. What is the effective resistance? 3. Three capacitances C1 = 30 mF , C2 = 30 mF , and C3 = 30 mF are connected in series in a circuit. What is the effective capacitance? 4. Three capacitances C1 = 30 mF , C2 = 30 mF , and C3 = 30 mF are connected in parallel in a circuit. What is the effective capacitance? 5. Based on the conductivity, how are materials classified as? 6. Distinguish between insulators, semiconductors, and conductors based on the forbidden gap. 7. What is an intrinsic semiconductor? 8. Why are germanium and silicon the most preferred semiconductor materials? 9. What is an extrinsic semiconductor? 10. What is an Ntype semiconductor and what are donor impurities? 11. What is a Ptype semiconductor and what are acceptor impurities? 12. What is the mean lifetime of an electron? 13. In which bands does conduction of electrons and holes takes place? 14. State the mass action law. 15. What is drift current in a semiconductor?
16. What is diffusion current in a semiconductor? 17. What is depletion region and what is barrier potential in a PN junction? 18. Between Ge and Si, which one will have a larger conductivity at room temperature? 19. Describe Hall effect. 20. How does Hall voltage help in deciding whether the semiconductor is an N or Ptype?
42
Electronic Devices and Circuits
long anSwer QueStionS Discuss electronic structure of elements and electron configuration of some of the fourth group elements. What is a Ptype semiconductor and derive the expression for its Fermi level? What is an Ntype semiconductor and derive the expression for its Fermi level? Write short notes on (i) mass action law (ii) continuity equation and (iii) Hall effect. 5. Discuss with relevant diagrams the working of unbiased PN junction. 1. 2. 3. 4.
unSolved problemS 14 3 1. An Ntype Si sample has the donor concentration at 300 K as 5 × 10 /cm . Determine the electron hole concentrations and the conductivity. 2. A rod of intrinsic silicon is 1 cm long and has a diameter of 1 mm. At room temperature, the 16 3 intrinsic concentration in the silicon is ni = 1.5 × 10 /m . The electron and hole mobilities 2 2 are me = 0.13 m /V − s and mh = 0.05 m / V − s . Calculate the conductivity s of the silicon and the resistance R of the rod, assuming circular cross section with diameter d. 2 3. For Ge at 300 K, the mobility of electrons = 0.39 m /V − s and the mobility of holes −19 19 3 2 = 0.19 m /V − s , ni = 2.5 × 10 /m , and e = 1.6 × 10 C . Calculate the resistivity of the material. 4. For Si at 300 K, the mobility of electrons = 0.15 m 2 /V − s, the mobility of holes = 0.05 m 2 /Vs , ni = 0.15 × 1016 /m 3, and e = 1.6 × 10 −19 C . Calculate the resistivity of the material. 5. A ptype silicon semiconductor is made by adding boron at the rate of one boron atom per 4 × 108 silicon atoms, ni = 1.5 × 1016 at 300 K. There are 5 × 10 28 germanium atoms per m3. Calculate (i) the acceptor atom density in the pmaterial; (ii) the hole density; (iii) the electron density; and (iv) n n 6. A sample of silicon has a resistivity of 2 × 103 Ω − m at 300 K. Find the donor concentration. i
DIODES, CHARACTERISTICS, AND APPLICATIONS
2 Learning objectives
After reading this chapter, the reader will be able to � � � �
2.1
Understand the working of a PN junction diode, its VI characteristics, and its equivalent circuits Appreciate the effect of temperature on the VI characteristic of a PN junction diode Use the diodes in applications such as clipping and clamping circuits Understand the principle of working of some specialpurpose diodes such as tunnel diode, varactor diode, Schottky barrier diode, PIN diode, photodiode, Gunn diode and IMPATT diode
PN JUNCTION DIODE
An unbiased PN junction was discussed in Chapter 1, and it was mentioned that a builtin potential will be developed at the junction. The energy band diagrams of the Ptype and Ntype semiconductors are shown in Figure 2.1. When a PN junction is formed, under equilibrium conditions (no current flow), as two materials come together, their Fermi levels must line up. For a PN junction, this will cause a shift in the energy bands. This shift will be directly proportional to the builtin potential (Figure 2.1).
ECP
ECN
EF1
EFN EF1
EFP EVP Ptype EFP < EF1
eVB = eVP + eVn
ECP eVp
ECN EFN eVn EF1
EF1 EFP EVP
EVN Ntype EFN > EF1
EVN Unbiased PN junction
Figure 2.1 Energy band diagram of a PN junction
From Figure 2.1, eVp = EFI − EFP
(2.1)
eVn = EFN − EFI
(2.2)
44
Electronic Devices and Circuits
and eVj = eVB = e(Vp + Vn)
(2.3)
We have (E
n = NC e
− ECN ) kT
(E
FN
− EFI ) kT
eVn
FN
= ni e
= ni e kT
(2.4)
Let n = ND, then from Eqn. (2.4) eVn
N D = ni e kT
(2.5)
N Vn = VT ln D ni
(2.6)
N Vp = VT ln A ni
(2.7)
Taking logarithms
Similarly,
Combining Eqs (2.6) and (2.7) N N N N VB =Vn + Vp =VT ln D +VT ln A =VT ln D 2 A ni ni ni
(2.8)
Example 2.1 If a PN junction has NA = 3 × 1018/cm3 on the Pside and ND = 1016/cm3 on the Nside, (i) Calculate the Fermi level in the P and Nregions at 300 K. (ii) Calculate the builtin potential. Solution: (i) Assume that p = NA and n = ND. On the Pside, ( EFI − EFP )
p = ni e
kT
Taking logarithms p 3 × 1018 EFI − EFP = kT ln = 0.026 ln = 0.497 eV ni 1.5 × 1010 Similarly, n 1 × 1016 EFN − EFI = kT ln = 0.026 ln = 0.349 eV ni 1.5 × 1010 VB = ( EFI − EFP ) + ( EFN − EFI ) = 0.497 + 0.349 = 0.846 eV N N 3 ×1018 × 1 × 1016 (ii) VB =VT ln A 2 D = 0.026 × ln = 0.846 eV 2 ni 1.5 ×1010
(
)
Diodes, Characteristics, and Applications
45
Example 2.2 An abrupt junction has doping densities of NA = 1015 atoms/cm3, and ND = 1016 atoms/cm3. Calculate the builtin potential at 300 K. Solution: We have, VB = 0.026 ln
15 NA ND 10 × 1016 = 0.638 V = 0.026 × ln 2 2 ni 1.5 × 1010
(
)
Example 2.3 Compute the resistivity and the resistance of the semiconductor material of length 1mm and area of cross section of 200 µm2 at 300 K. Assume the mobility of electrons to be 1200 cm2/Vs and the electron doping level to be n = 1016/cm3. Solution: Given n = 1016 / cm 3 = 1022 / m 3
me = 1200 cm 2 / V − s =1200 × 10 −4 m 2 / V − s
We have, s = ne me =1022 ×1.6 × 10 −19 ×1200 ×10 −4 =192 (Ω − m)−1 r=
R=
1 1 = = 52.08 × 10 −4 Ωm s 192
r l 52.08 × 10 −4 × 1 × 10 −3 = = 26.04 m Ω A 200 × 10 −12
When a PN junction is formed, the resultant twoterminal device is called a junction diode. The Pterminal is called the anode (A) and the Nterminal is called the cathode (K). Under unbiased condition, there is no conduction, that is no current exists in the device. For current to flow, the device must be biased suitably. By biasing, it means the application of an external voltage. There are two methods of biasing a junction diode: (i) forward biasing and (ii) reverse biasing.
2.1.1 Forward Bias The forwardbiased junction diode is shown in Figure 2.2. By forward bias, it is meant that the positive terminal of the external source is connected to the Pmaterial and the negative terminal to the Nmaterial, respectively. By doing so, the externally connected dc voltage establishes an electric field opposite to the potential barrier, thereby reducing the potential barrier. The potential barrier is typically 0.1 V for Ge and 0.5 V for Si. As such, a small external voltage is enough to eliminate the barrier, and the junction resistance becomes almost zero. Now aided by this external voltage, the free electrons in the Nmaterial cross the junction and move into the Pregion.
46
Electronic Devices and Circuits
The free electrons combine with holes near the junction. Since a hole is in the covalent bond, when a free electron combines with a hole, it becomes a valence electron and in the Pregion the electrons travel as valence electrons and enter the positive terminal of a battery. Therefore, the current is mainly due to the majority carriers only and is called the forward current of the diode. Barrier potential with forward bias
VB = Barrier potential with no external ﬁeld
Metal contact
Metal contact
A
Schematci representation of diode
K
P
K
A
mA
N
mA
+
− −
I
+
V
V
Figure 2.2 Forwardbiased PN junction diode
2.1.2 Reverse Bias When the positive terminal and the negative terminal of a battery are connected to the Ntype material and the Ptype material, respectively, then the type of biasing is called reverse bias. Electrons in the Nregion and holes in Pregion move away from the junction, and therefore reverse bias increases the potential barrier (Figure 2.3), which prevents the flow of the majority charge carriers across the junction. The junction offers a very high resistance. As there is no combination of electrons and holes, practically the reverse current is zero, and whatever little current is present is mainly due to the minority carriers only. Barrier potential– with external reverse bias voltage Barrier potential– with no external voltage
P
µA
N
+
µA +
− V
V
I
Figure 2.3 Reversebiased PN junction diode
I
−
Diodes, Characteristics, and Applications
47
From the two methods of biasing, it is evident that when forward biased, the junction diode offers a very small forward resistance, resulting in an appreciable forward current. When reverse biased, the current in the device is zero. Alternately, it can be said that when forward biased, the junction diode behaves as a closed switch. On the contrary, when reverse biased, it behaves as an open switch. Hence, a junction diode can either be used to convert a bidirectional signal into a unidirectional one, or it can be used as a rectifier.
Current Components in a PN Junction Diode In a forwardbiased diode, the depletion region becomes small. Holes are injected from the Pregion into the Nregion, and electrons are injected from the Nregion into the Pregion. The number of these charge carriers decreases exponentially with increasing distance from the junction. As the holes are minority carriers in the Ntype and as the number of holes in the Ntype decreases with increasing distance from the junction, the hole current I pn in the Nregion decreases with distance, and hence this current may be expressed as a function of x as I pn ( x ). Similarly, as the electrons are minority carriers in the Ptype and as the number of electrons in the Ptype decreases with increasing distance from the junction, the electron current I np in the Pregion decreases with distance and is expressed as I np ( x ) (Figure 2.4). When holes cross over from Pside to the Nside, there is a current from P to N. In addition, when electrons cross over from Nside to the Pside, once again there is a current from P to N, since the current is supposed to be flowing opposite to the direction of the electron flow. Therefore, at x = 0 , the total current at the junction I is I = I pn ( 0 ) + I np ( 0 )
(2.9)
It is noted that I pn ( x ) and I np ( x ) decrease as we move away from the junction on the Nside and Pside, respectively. But the total current I should remain constant at any given distance x from the junction. Since the junction is forward biased, there exists a hole current I pp ( x ) on the Pside and an electron current I nn ( x ) on the Nside, which are majority carrier currents due to drift. Therefore, the total current on the Pside is I = I pp ( x ) + I np ( x )
(2.10)
and the total current on the Nside is I = I nn ( x ) + I pn ( x )
(2.11)
From Figure 2.4, it can be noted that as holes, the majority carriers in the Pside approach the junction, some of them may combine with electrons crossing the junction from the Nside. Therefore, I pp decreases near the junction and is equal to I np . Similarly, I nn decreases near the junction and is equal to I pn . However, the total current I remains constant.
Law of the Junction In the case of an unbiased junction, let the barrier potential, VB =V0 . Using Boltzmann relation, it can be written as follows: ppo = pno e
Vo VT
(2.12)
48
Electronic Devices and Circuits
where, ppo = concentration of holes on the Pside under thermal equilibrium pno = concentration of holes on the Nside under thermal equilibrium But, with the application of forwardbias voltage, V ppo = pn ( 0 )e
_ Vo V VT
(2.13)
where, pn ( 0 ) = concentration of holes on the Nside near the junction
V
I
I
From Eqs (2.12) and (2.13) pno e
Vo VT
P
= pn ( 0 )e
∴ pn ( 0 ) = pno e
V VT
Vo −V VT
N x=0
x
(2.14)
x
I Ipp
Inn
It can be noted from Eqn. (2.14) that the Inp Ipn total concentration of holes at the edge of the junction is an exponential function of x=0 x x the applied bias voltage. It is obviously evident Figure 2.4 Current components in a PN junction diode that the hole concentration near the junction under forwardbias condition, pn ( 0 ) , is much larger than the hole concentration under thermal equilibrium, pno . Equation (2.14) is called the law of the junction.
The Diode Equation From Eqn. (2.14), injected or excess charge concentration Pn ( 0 ) = pn ( 0 ) − pno = pno e
V VT
VV − pno = pno e − 1 T
(2.15)
Similarly, VV N p ( 0 ) = npo e − 1
(2.16)
T
The hole current that crosses the junction from the Pside to the Nside is given as follows: VV AqDp Pn ( 0 ) AqDp I pn ( 0 ) = = pno e − 1 Lp Lp T
where, A = area of cross section of the junction Dp = diffusion constant for holes and Lp = diffusion length of the holes
(2.17)
Diodes, Characteristics, and Applications
49
Similarly, the electron current that crosses the junction from the Nside to the Pside is given as follows: I np ( 0 ) =
VV AqDn N p ( 0 ) AqDn = npo e − 1 Ln Ln
(2.18)
T
where, Dn = diffusion constant for electrons and Ln = diffusion length of the electrons I = I pn ( 0 ) + I np ( 0 ) =
AqDp Lp
VV VV AqD n pno e − 1 + npo e − 1 Ln T
T
AqDp V AqDn = pno + npo eV − 1 Ln Lp T
VV I = I S e − 1
Or
T
where,
IS =
AqDp Lp
pno +
AqDn npo Ln
(2.19)
(2.20)
I is the diode current in A V is the voltage at the anode with respect to the cathode in V IS is the leakage or reverse saturation current in A In general,
hVV I = IS e − 1 T
(2.21)
h is the emission coefficient or the ideality factor, and is 1 Ge and 2 Si, respectively The VI characteristics of a diode are shown in Figure 2.5.
Forward Bias From Eqn. (2.21), if V = VD = 0.1 V and h = 1, 0.1 I D = I S e 0.026 − 1 = I S ( 46.80 − 1) = 45.80 I S Usually, when forward biased, VD > 0.1V, I D >> I S ; therefore, VD
I D = ISe
hVT
(2.22)
Reverse Bias When reverse biased, V = VD is negative; VD >> Vγ , the threshold voltage, say VD < − 0.1 V , then
50
Electronic Devices and Circuits
When, VD is more negative than –0.1 V, then VR
VD
Ge
ID
−0.1 I D = I S e 0.026 − 1 = I S ( 0.02 − 1) = −0.98 I S
VBV2
Si
VBV1 Vγ1
0
e V → 0 ; therefore, T
Vγ2
VD
(2.23)
I D = −I S
From Eqn. (2.23), it can be noted that the reverse current in a diode is constant and is IS.
Si
IR
Ge
Figure 2.5 VI characteristic of a diode.
Breakdown Region When the reversebias voltage is equal to the specified voltage called the breakdown voltage, VBV say 100 V, then the reverse current in the diode increases rapidly. In normal applications, a diode is never used in the breakdown region. However, it can be noted from Figure 2.5, when breakdown occurs, that the voltage across the diode terminals remains almost constant. Hence, when operated under this condition the diode is used as a constant voltage source. However, care must be taken to ensure that the power dissipation in the device is not more than the rated dissipation for the device.
Temperature Dependence of the VI Characteristics Temperature has significant effect on the diode characteristics. VT and IS are temperature dependent. Increase in temperature results in increased thermal activity and decreased diode resistance, which influences both the forward and the reverse operation of the diode. Figure 2.6 shows the effect of temperature on the diode characteristics. 50°C 25°C
IF
Reverse breakdown voltage increases with increase in temperature VBV VR
IF2
Forward current increases with increase in temperature for the same voltage
IF1 0
VF1
VF
Forward voltage decreases with increase in temperature
50°C 25°C
IR Reverse current increases with increase in temperature
Figure 2.6 Effect of temperature on the diode characteristics
Diodes, Characteristics, and Applications
51
As temperature increases, IF increases at a specified forward voltage. From Figure 2.6, it can be noted that at VF1, IF at 25°C is IF1 and at 50°C is IF2 and IF2 > IF1. The diode forward voltage decreases by 2.5 mV per a degree rise in temperature ( in Celsius). The reverse saturation current and the breakdown voltage increase with increase in temperature. The reverse saturation current IS increases by 7.2 percent by a degree rise in junction temperature (in Celsius) and gets doubled for every 10°C rise in temperature (Fig. 2.7.) VR
27°C
0
IS
37°C 2IS IR
Figure 2.7 Effect of temperature on the reverse characteristic of the diode
The temperature dependence of the reverse saturation current is expressed as −Vg m hVT
I S = KT e
(2.24)
where, K is a constant independent of temperature, h is 1 for Ge and 2 for Si. m is 2 for Ge and 1.5 for Si. Vg, the forbidden gap is 0.785 eV for Ge and 1.21eV for Si. Example 2.4 Using the diode equation, find the forward current in a Si junction diode at a forward voltage of 0.6 V and temperature of 27°C, if the reverse saturation current is 0.1 mA. V h Solution: I D = I S e V − 1 D
T
For Si, h = 2. Given VD = 0.6 V and IS = 0.1 mA VT = kT = 8.62 ´10 5 T V At 27°C, VT = kT = 8.62 ´10 5 ( 27 + 273) = 0.026 V VT can also be calculated as follows: VT = kT = At 27°C, VT =
300 = 0.026 V 11, 600
T T T = = 1 1 11, 600 k 8.62 ×10 −5
0.6 I D = 0.1 × 10 −6 e 2 × 0.026 − 1 = 10.27 mA
52
Electronic Devices and Circuits
Example 2.5 Find the factor by which the reverse saturation current of Ge and Si diodes increases when the temperature increases from 27°C to 77°C. −Vg m hVT
Solution: I S = KT e
(i) For Ge, m = 2,
h = 1 T = 27 + 273 = 300 K and Vg = 0.785 V
VT = 0.026 V −0.785
∴I S1 = K (300 )2 e 1× 0.026 −0.785
e 1× 0.026 = 0.775 × 10 −13
IS1 = 69750 × 10−13 K
(2.25)
At T = 77 + 273 = 350 K VT =
T 350 = = 0.03 V 11, 600 11, 600 0.785
I S2 = K (350 )2 e 1´0.03 = 52675 ´ 10 11 K I S2 52675 × 10 −11 = = 75.5 I S1 69750 × 10 −13
Or
(2.26)
I S2 = 75.5I S1
(2.27)
(ii) For Si, m = 1.5, h = 2 T = 27 + 273 = 300 K and Vg =1.21 V VT = 0.026 V −1.21
∴I S1 = K (300 )1.5 e 2×0.026 −1.21
e 2× 0.026 = 0.78 × 10 −10
IS1 = 4053 × 10−10 K
(2.28)
At T = 77 + 273 = 350 K VT =
350 T = = 0.03 V 11, 600 11, 600 −1.21
I S2 = K (350 )1.5 e 2 × 0.03 = 11394 × 10 −9 K
(2.29)
Diodes, Characteristics, and Applications
I S2 11394 × 10 −9 = = 28.11 I S1 4053 × 10 −10
Or
IS2 = 28.11 IS1
53
(2.30)
From Eqs (2.27) and (2.30), it can be noted that variation of IS with temperature is small in Si when compared with Ge. Example 2.6 A Si diode has reverse saturation current of 0.1 µA at 27°C. Find its reverse saturation current at (a) 37° C and (b) 127° C. Solution: The temperature dependence of IS is also given by the relation T2 − T1 10
(2.31) I S2 = I S1 2 where, IS2 is the leakage current at temperature T2 and IS1 is the leakage current at temperature T1, usually 27°C. (a) T1 = 27 + 273 = 300 K and T2 = 37 + 273 = 310 K I S2 = I S1 2
T2 −T1 10
310 − 300 10
= 0.1 × 2
= 0.2 µA.
This means that the leakage current gets doubled for every 10°C rise in temperature. (b) T1 = 27 + 273 = 300 K and T2 = 127 + 273 = 400 K æ T2 T1 ö ç ÷ 10 ø
I S2 = I S1 2è
2.2
æ 400 300 ö ç ÷ 10 ø
= 0.1 ´ 2 è
= 102.4 mA.
ANALYSIS OF THE DIODE CIRCUIT
Consider a practical diode circuit shown in Figure 2.8. + VD −
ID
+ V
RL
VL −
Figure 2.8 Practical diode circuit
The diode is a nonlinear component, and therefore the methods of circuit analysis cannot be used. Hence, the analysis of a diode circuit basically involves two methods: (i) numerical and (ii) graphical.
2.2.1 Numerical Method From Figure 2.8, . But, I D = I S hV e − 1 VD
T
V = VD + IDRL
(2.32)
54
Electronic Devices and Circuits
Substituting this value in Eqn. (2.32), V V = VD + I S e hV − 1 RL D
(2.33)
T
Equation (2.33) can only be solved numerically. But an alternate simple procedure would be the graphical method.
2.2.2 Graphical Method From Eqn. (2.32), ID =
V VD − RL RL
(2.34)
From Figure 2.9, VD is the variable on the xaxis and ID is the variable on the yaxis. Equation (2.34) is in the form of y = mx + C and is the equation of the straight line and is called the load line. In order to draw the straight line, at least two points are required. To locate these two points, the following conditions are imposed on Eqn. (2.34): V Set, VD = 0, then I D = (point Y on the yaxis) RL Set, ID = 0, then VD = V (point X on the xaxis) The line joining these two points, X and Y, is the dc load line. Similarly, Eqn. (2.19) gives the VI characteristic of the diode as shown in Figure 2.9. ID will have to satisfy both Eqs (2.19) and (2.34). The intersection of the diode curve and the load line will give the value of ID for a given VD (Figure 2.9) and is called the quiescent point or the operating point. iD Y
V RL
Load line ID
Q
X 0
VD
V
vD
Figure 2.9 Graphical method of analysis
In the analysis of diode circuits, sometimes certain approximations are made to arrive at simple solutions. First, let us assume that the diode is ideal, that is, the forward resistance of the diode is zero and the diode conducts for VD = 0 and the diode current is ideally infinity. For a reverse voltage, the diode current is ideally zero. This means that that the diode behaves as a closed switch when forward biased and as an open switch when reverse biased (Figure 2.10).
Diodes, Characteristics, and Applications
55
Forward bias ID
A
K Closed switch
VR
VD
0
Reverse bias K
A
Ideal diode
Open switch
Figure 2.10 Ideal diode characteristic and equivalent circuit
A diode, however, has a barrier potential or cutin voltage, Vg . Unless the forwardbias voltage is equal to Vg , there can be no current in the device; and at Vg , the current abruptly becomes infinity, assuming an ideal diode. The diode is now represented as a closed switch in series with a battery of value, Vg ( Figure 2.11). Forward bias ID
A
K Vγ
Closed switch 0
VR
Vγ
VD
Reverse bias K
A
Ideal diode with Vγ
Open switch
Figure 2.11 Ideal diode with barrier potential and the equivalent circuit
However, a practical diode has a finite forward resistance and the diode characteristic, and its equivalent circuit are shown in Figure 2.12. Forward bias ID
RF
A
K Vγ
Closed switch VR
0
Vγ
VD
Idealized diode
Reverse bias K
A Open switch
Figure 2.12 Practical diode idealized characteristic and equivalent circuit
From Figure 2.9, RF = VD is the dc resistance or the static resistance of the diode. ID However, in certain applications, a small sinusoidal signal may be overriding on the steady
56
Electronic Devices and Circuits
dc component (Figure 2.13). In such applications, there is a range (not necessarily linear) over which the diode voltage varies, and correspondingly there exists a range over which the diode current varies. The ratio of the incremental change in the diode voltage to the incremental change the diode current is an ac resistance and is called the dynamic resistance of the diode (Figure 2.13). id
ID
id
id
+
Q
ID
vd
∆ID
RL −
VD vD
0
VD vd
∆VD
Figure 2.13 Diode circuit with a sinusoidal signal overriding a dc signal
rd = rac =
∆VD around the operating point. ∆I D
Bulk Resistance of the Diode The P and Nregions offer finite resistances Rp and Rn, and the sum of these resistances is called the bulk resistance, RB = Rp + Rn, which is typically of the order of 5 Ω and essentially depends on the doping, the dimensions of the Ptype and Ntype materials, and the operating temperature.
Dynamic Resistance or ac Resistance The dynamic resistance rd of the forwardbiased junction depends on the forward current, I, which rapidly increases with the increasing bias voltage. From Eqn.( 2.19),
hVV I = IS e − 1 T
V
dI 1 V ISe h = dV hVT
T
V
1 1 V ISe h = rac hVT
T
Or
rac = rd =
hVT ISe
rac is the dynamic resistance.
V hVT
(2.35)
Diodes, Characteristics, and Applications
57
But, from Eqn. (2.19), V VT
I + IS = IS eh
(2.36)
Substituting Eqn. (2.36) in Eqn. (2.35), rac = rd =
hVT hVT ≈ I + IS I
(2.37)
since, I >> IS. Example 2.7 A Ge diode has a reverse saturation current of 25 μA at 100°C. Find its dynamic resistance for a bias voltage of 0.2 V (i) in the forward direction and (ii) in the reverse direction. Solution: T = 100°C = 100 + 273 = 373 K IS = 25 × 10−6 A VT =
T 373 = = 32 mV 11, 600 11, 600
(i) When V = 0.2 V V
From Eqn. (2.35), racf =
0.2 VT V 0.032 0.032 ´ =1280 ´1.93 ´10 3 = 2.47 W e = e IS 25 ´10 6 T
(ii) When V = –0.2 V, V
racr =
0.2 VT V 0.032 0.032 ´ =1280 ´ 518 = 0.663 MW e = e IS 25 ´10 6 T
Example 2.8 At 27°C, the diode current is 0.5 mA at 0.45 V and 25 mA at 0.65 V. Determine h. Solution: T = 27 + 273 = 300 K and VT =
300 T = = 0.026 V 11, 600 11, 600
V hVV hV I = IS e − 1 = I S e T
T
(i) When I = 0.5 × 10−3 A, V = 0.45 V 0.45
∴0.5 ×10 −3 = I S e 0.026h = I S e
17.31 h
(2.38)
(ii) When I = 25 × 10–3 A, V = 0.65 V −3
∴25 × 10 = I S e
25 h
(2.39)
58
Electronic Devices and Circuits
Dividing Eqn. (2.39) by Eqn. (2.38), e
50 =
25 h
17.31
=e
7.69 h
eh 7.69 = ln(50)=3.91 h ∴h =
2.3
7.69 =1.97 3.91
JUNCTION CAPACITANCES
The capacitive effects in a diode limit its application at high frequencies. Basically, a PN junction diode offers two types of capacitive effects: one when reverse biased and the other when forward biased. When forward biased, the diode offers a capacitance called the diffusion capacitance or storage capacitance, CD; and when reverse biased, the capacitance offered by it is called the transition capacitance or space charge capacitance or depletion region capacitance, CT .CD >> CT.
2.3.1 Diffusion or Storage Capacitance, C D The capacitance offered by the junction diode when forward biased is the diffusion capacitance, CD. Forward bias reduces the barrier potential, and holes from the Pside are injected into the Nside and electrons from the Nside are injected into the Pside. There will be a large concentration of holes on the Nside of the junction and the concentration of holes decreases exponentially on the Nside as we move away from the junction. This may be understood like this—a positive charge is injected from the Pside into the Nside. In addition, the injected charge Q is proportional to the forwardbias voltage, V. The rate of change of Q with V is the diffusion capacitance. CD =
dQ dV
(2.40)
When the diode is operated under forward bias, additional charge is stored near the edges of the space charge region. The amount of charge Q stored in the diode is proportional to the diode current I. Q = It (2.41) where t is the mean lifetime of the charge carriers, and I is the diode current. From Eqn. (2.19), V hVVT hV I = IS e − 1 ≈ I S e
T
Substituting in Eqn. (2.41), V VT
Q = tI S e h
(2.42)
Diodes, Characteristics, and Applications
59
From Eqs (2.40) and (2.42), CD =
V V dQ d t V hV IS e h = t I S e = dV dV V h T T
T
(2.43)
Also from Eqn (2.19), I + IS = ISe
V hVT
(2.44)
Substituting Eqn. (2.44) in Eqn. (2.43), V
CD =
tI S hV t ( I + I S ) e = hVT hVT T
(2.45)
As I >> IS, when forward biased, Eqn. (2.45) can be written as follows: CD =
t ( I + IS ) t I ≈ hVT hVT
(2.46)
Equation (2.46) tells that CD is proportional to I.
Transition Capacitance, C T In a reversebiased diode, the width of the depletion region
depends on the applied reversebias voltage. If the P and Nregions, which offer low resistances, are considered as parallel plates and the depletion region that behaves as an insulator as the dielectric, then the reversebiased PN diode can be seen as a parallel plate capacitor. The capacitance offered by the diode when reverse biased is called the transition capacitance or the depletion layer capacitance or the space charge capacitance, CT (Figure 2.14). W is the width of the depletion region for the applied reversebias voltage, V.
Transition capacitance, CT =
Rate of changeof charge at the junction dQ = . dV Rate of changeof the applied reversebias voltage
PN junctions are of two types: (i) stepgraded junction and (ii) linearly graded junction.
Calculation of C T for a StepGraded Junction (Alloy Junction) A stepgraded junction
is one in which there is an abrupt change in acceptor ion concentration on the Pside to the donor ion concentration on the Nside. The acceptor density NA and the donor density ND can be unequal. Let NA > ND (Figure 2.15). As NA >> ND, the depletion region penetrates more into the Nside than into the Pside. Then W = WN + WP ≈ WN (2.47) where, W = width of the depletion region WN = width of the depletion region on the Nside and WP = width of the depletion region on the Pside Poisson’s equation gives the relation between the charge density and the potential as follows: d 2V qN D = e dx 2
(2.48)
60
Electronic Devices and Circuits Parallel plates W
P + + + + + + + + +
N − − − − − − − − −
Dielectric
V
Figure 2.14 Transition capacitance, CT
where, q = the charge of an electron x = the distance from the junction e = the permittivity of the semiconductor = e0 er e0 = the permittivity of free space = 8.85 × 10−12 F/m er = the relative permittivity of the semiconductor and is 16 for Ge and 12 for Si. Integrating Eqn. (2.48) with respect to x and assuming that the constant of integration is zero, qN d 2V ∫ dx2 dx = ∫ e D dV qN D = x dx e
(2.49)
dV is the electric field intensity E in the depletion region. dx Therefore, from Eqn. (2.49), E=
qN D x e
(2.50)
Integrating Eqn. (2.49) gives the potential V: dV
∫ dx dx = ∫
W
0
V= From Figure 2.15(d), at x = W, V = VB,
qN D xdx e
qN D W 2 × e 2
(2.51)
Diodes, Characteristics, and Applications
61
Therefore, VB =
qN D W 2 × 2 e
∴W 2 =
(2.52)
2e ×VB qN D 1
W ∝VB2
Or
(2.53)
V
P
(a)
N W WP
Charge density, r
0
ND x (b) WN
NA 0
Electric ﬁeld E intensity
x (c)
VB 0
Potential, V
x (d)
Figure 2.15 Variation of ρ, E, and V as a function of distance x from the junction
From Eqn. (2.53), it is evident that the width of the depletion region W increases with the increasing reversebias voltage. The total charge density of the Ntype material is Q = qND × Volume = qND AW
(2.54)
From Eqn. (2.54), CT =
dQ dW = qN D A dV dV
(2.55)
Differentiating Eqn. (2.51) with respect to V 1=
qN D 2W dW e 2 dV
Or
dW e = dV qN DW
(2.56)
62
Electronic Devices and Circuits
Substituting Eqn. (2.56) in Eqn. (2.55) CT =
dQ dW qN D Ae eA = qN D A = = dV dV qN DW W
(2.57)
Equation (2.57) can be seen as the expression for the capacitance of a parallel plate capacitor, and CT is inversely proportional to the width of the depletion region, W.
Linearly Graded Junction (Grown or Diffused Junction) In a linearly graded junction, the charge density varies linearly with distance in the depletion region (Figure 2.16). CT is given by 1
1
−W/2
Charge density, r
Eqn. (2.57). But W varies as VB 3 , but not as VB 2 as in the case of an abrupt junction.
0
+W/2
Figure 2.16 Variation of charge density with distance
Example 2.9 In an abrupt Si PN junction, ND = 1023 atoms/m3, and NA = 0.5 × 1022 atoms/m3. Calculate the width of the junction when (i) no external voltage is applied, that is, VB = 0.7 V and (ii) when the applied reversebias voltage is −5 V. Solution: In general, W =
2eVB q
1 1 + NA ND
e = e0er = 12 × 8.85 × 10−12 F/m = 1.062 × 10−10 F/m q = 1.602 × 10−19 C (i) VB = 0.7 V, W=
2 × 1.062 ×10 −10 × 0.7 1 1 + 23 = 0.432 ×10 −6 m 22 1.602 ×10 −19 0 . 5 10 10 ×
(ii) When VR = – 5 V .VB =Vo − ( −VR ) = Vo +VR = 0.7 + 5 = 5.7 V
W=
2 ×1.062 ×10 −10 × 5.7 1 1 −6 0.5 ×1022 + 1023 = 1.26 ×10 m 1.602 ×10 −19
Diodes, Characteristics, and Applications
63
Example 2.10 In a Si junction diode, NA >> ND, the resistivity on the Nside is 4 Ω−cm and the contact potential is 0.5 V. A reverse bias of 10 V is applied to the junction. Assume circular junction with diameter 1 mm. μe = 500 cm2/Vs Calculate, CT . Solution: For silicon, e = e0er = 12 × 8.85 × 10−12 F/m = 1.062 × 10−10 F/m q = 1.602 × 10−19 C Given re = 4 Ω–cm = 4 × 10−2 Ω–m, me = 500 cm 2 / V − s = 500 × 10 −4 m 2 / V − s 1 1 −1 = = 25 (Ω − m ) re 4 × 10 −2
se =
s e = qN D me
∴ qN D =
se 25 = = 500 me 500 × 10 −4
Given, V0 = 0.5 V and VR = −10 V ∴VB =V0 − ( −VR ) =V0 + VR = 0.5 + 10 = 10.5 V From Eqn. (2.52), VB =
qN DW 2 2e
W2 =
2eVB 2 × 1.062 × 10 −10 × 10.5 = = 4.46 × 10 −12 qN D 500
W = 2.11×10 −6 m
(
−3 pd 2 p 1×10 A= = 4 4
CT =
2
)
= 0.785 ×10 −6 m 2
e A 1.062 ´10 10 ´ 0.785 ´10 6 = = 39.51pF W 2.11´10 6
Switching Times in a Diode Consider the diode circuit to which a signal is applied as shown in Figure 2.17. During the interval 0 to t1, the input is VF , the diode is forward biased and the diode current is I F . Suddenly, at t = t1, the diode is reverse biased by a voltage VR and as such the diode current is expected to become zero ideally. However, this does not happen because of the fact that when the diode is forward biased, there are a
+
VF t1
Vi
0 VR
RL
−
Figure 2.17 Diode circuit with input
64
Electronic Devices and Circuits
large number of stored charges on either side of the junction, which ensure large reverse current even under reversebiased condition. The time for which the reverse current is large is called the storage time, tS , that is, (t2 − t1 ) . The reverse current eventually falls to zero when all the stored charges are cleaned up. The time interval from t2 to t3 is called the transition time, tt (Figure 2.18). Thus, it is evident that when a forwardbiased diode is suddenly reverse biased, the diode will not switch into the OFF state unless a minimum time interval (tS + tt ) elapses, and this total time interval is called the reverse recovery time of the diode, trr .
VF
Vi 0
t1 VR
IF
Reverse recovery time, trr t1
t2
t3
0 Storage time, ts IR
Transition time, tt
Figure 2.18 Switching times of a junction diode
2.4
SOME IMPORTANT DIODE PARAMETERS
Diodes can be broadly classified as follows: (a) signal diodes and (b) power diodes. Signal diodes are mainly used under small signal conditions, that is, in lowcurrent and lowpower applications. These are better used in switching circuits and for highfrequency applications. Power diodes are used in highcurrent and highpower applications such as rectifiers. Whenever a diode is used for a specific application, the following diode parameters will have to be borne in mind: (i) Maximum forward current: The maximum forward current I F( max ) is the maximum current allowed to flow through the diode when forward biased. When I > I F( max ) , then more power is dissipated at the junction resulting in more heat at the junction. The diode will fail due to thermal overload. As an example, for a signal diode 1N4148, I F( max ) is 150 mA and power dissipation is 500 mW at 25oC. (ii) Peak inverse voltage (PIV) or peak reverse voltage (PRV): Peak inverse voltage is the maximum reversebias voltage that can be applied to the diode so as to ensure that no
Diodes, Characteristics, and Applications
65
reverse breakdown occurs. This specification is important in applications such as rectifiers and the diode should be properly chosen. (iii) Maximum power dissipation: Maximum power dissipation, PD( max ) , is the maximum allowable power dissipation in device when forward biased. (iv) Maximum operating temperature: The maximum operating temperature actually refers to the junction temperature (TJ) of the diode and is related to the maximum power dissipation. Usually, the operating temperature range of the diode is mentioned.
2.5
BREAKDOWN DIODES
The VI characteristic of certain diodes is such that when forward biased, these diodes exhibit the same characteristic as that of an ordinary PN junction diode; but when reverse biased, the voltage across the diode terminals remains almost constant, but the current in the diode suddenly becomes large (the device conducts heavily at a voltage called the breakdown voltage). Such diodes can be used as reference elements or simple voltage regulators. A voltage regulator is one that maintains the output voltage constant irrespective of the variations in the input voltage or variations in the load current. We consider two breakdown diodes, namely Zener and avalanche diodes.
2.5.1 Zener Diode A Zener diode is a heavily doped diode, with an anode A and cathode K as shown in Figure 2.19, with its VI characteristic represented in Figure 2.20. Zener breakdown occurs due to the physical rupturing of the covalent bonds due to the applied reversebias voltage, and the current abruptly rises to a large value at a voltage VZ, called the Zener breakdown voltage. To limit the current to a safe value of IZ(max), there is need to provide a series limiting resistor. The Zener diode conducts when the current is IZ(min). The power dissipation capability of the Zener diode is PD(max) = VZ IZ(max), which is normally specified at 25°C. However, at elevated temperatures, the power dissipation capability of the Zener diode decreases as the Zener diode exhibits negative temperature coefficient, a Z As a result, VZ decreases with increase in temperature. If a Z = −0.06%/°C and VZ = 3.6 V at 25°C, then VZ at 100°C is given as follows:
K
A
Figure 2.19 Zener diode
IF
VR
VZ
0 Vg IZ(min)
VF
IZ(max) IR
VZ (at 100° C) = VZ + ∆VZ where ∆VZ = VZ a Z (T − 25)
(2.58)
Figure 2.20 VI Characteristic of Zener diode
66
Electronic Devices and Circuits
−0.06 × 75 = − 0.162 V ∴ ∆VZ = 3.6 × 100 VZ (at 100°C) = 3.6 − 0.162 = 3.438 V. Zener diodes normally operate below 6 V. As a reversebiased Zener diode conducts heavily at VZ, its approximate equivalent circuit can be simply a battery with terminal voltage VZ, Figure 2.21(a). However,VZ may vary by ∆VZ , when I Z varies from I Z ( min ) to I Z ( max ) ( = ∆I Z ) . Thus, a Zener has a dynamic resistance, rZ , given as follows: rZ =
∆VZ ∆I Z
(2.59)
Hence, the exact equivalent circuit of the Zener diode may be represented as a battery, VZ , with internal resistance, rZ (Figure 2.21(b)). A
K
rz
K
VZ
A
VZ
(a) Approximate equivalent circuit
(b) Exact equivalent circuit
Figure 2.21 Equivalent circuits of a Zener diode
2.5.2 Avalanche Diode An avalanche diode too has a similar VI characteristic as a Zener diode, but the device conducts heavily, when reverse biased, at larger voltages. When reverse biased, the minority charge carriers in the P and N materials acquire large kinetic energy, aided by the external voltage. When a charge carrier collides with an atom, it may knock off an electron, which in turn can acquire large energy, and may in turn knock off another electron from a different atom. This results in a large number of charge carriers, due to the process called avalanche multiplication. Hence, there results a large current. This diode is called an avalanche diode. This phenomenon occurs at large reversebias voltages. But both avalanche and Zener diodes are generally called as Zener diodes, though the principle of operation is different. An avalanche diode has a positive temperature coefficient, that is, VZ increases with temperature. If a Z = 0.06%/°C and VZ = 10 V at 25°C, then VZ at 100°C is given as follows: VZ (at 100°C) = VZ + ∆VZ where ∆VZ = VZ a Z (T − 25) 0.06 ∴ ∆VZ = 10 × × 75 = 0.45 V 100
(2.60)
67
Diodes, Characteristics, and Applications
VZ (at 100°C) = 10 + 0.45 = 10.45 V Zener and avalanche diodes are used as voltage reference elements because once breakdown occurs, the voltage across the diode remains almost constant.
2.6
CLIPPING CIRCUITS
A device or a circuit may be destroyed when a signal of large amplitude (positive or negative) is applied to it. Therefore, it becomes necessary to protect the device or a circuit. A clipping circuit is used in such applications. A clipper eliminates a portion or portions of the input signal. Clipping circuits are classified into (i) onelevel and (ii) twolevel clippers.
2.6.1 OneLevel Clippers Onelevel clippers clip the input signal at only one voltage level. Onelevel clippers can be (i) series clippers and (ii) shunt clippers. Further, these can be biased or unbiased circuits.
Series Clippers In a series clipper, the clipping element, a diode, is connected in series with the output. The input–output waveforms are obtained based on the assumption that the diode is ideal. (i) Negative clipper: Figure 2.22(a) shows a series negative clipper, and Figure 2.22(b) shows its transfer characteristic from which the input–output relation is obtained. When Vi ≥ 0, D is forward biased and is ON. Its equivalent circuit is a closed switch. Hence, Vo =Vi . When Vi < 0, D is reverse biased and is OFF. Its equivalent circuit is an open switch. Hence, Vo = 0. The relation between Vi and Vo is called the transfer characteristic.
Vo
D π 0
π/2
t Vi −
Slope = 1
+
+ R
Vo
Vo 0
t
0
π/2
π t
− Vi 0 π/2 π t
(a) Circuit
(b) Transfer curve and waveforms
Figure 2.22 Negativepeak clipper
(ii) Positive clipper: If the polarity of the diode is reversed, then the circuit of Figure 2.22 becomes a positivepeak clipper (Figure 2.23). When Vi > 0, D is reverse biased and is OFF. Hence, Vo = 0. When Vi ≤ 0, D is forward biased and is ON. Vo =Vi .
68
Electronic Devices and Circuits
Vo
D + 2π 0
R
t Vi −
π
Slope = 1
+ Vo
π
Vo
2π
0
0
t
2π t
Vi 0 π
−
π 0
2π t (b) Transfer curve and waveforms
(a) Circuit
Figure 2.23 Positive clipper
(iii) Biased series clippers: The circuits in Figures 2.22 and 2.23 completely eliminate one half cycle of the input signal and are used as halfwave rectifiers. However, if only a small portion of the input signal is to be removed, then biased clippers are used. (iv) Positivebase clipper: Consider the circuit and the transfer characteristic in Figure 2.24. Vo
D
0
π
+ 2π t Vi −
Slope = 1 + R VR
VR
Vo
Vo 0
VR
VR
− Vi π 2π t
Figure 2.24 Positivebase clipper
When Vi < VR , D is OFF. Therefore, Vo =VR . When Vi ≥ VR , D is ON. Therefore, Vo =Vi . The circuit clips the output during the positive half cycle below the reference voltage, VR (v) Negativepeak clipper: Consider the circuit and the transfer characteristic in Figure 2.25. When Vi < − VR , D is OFF. Therefore, Vo = − VR When Vi ≥ − VR , D is ON. Therefore, Vo =Vi . The circuit is a negativepeak clipper that clips the negative peak at −VR . (vi) Positivepeak clipper: Consider the circuit and the transfer characteristic in Figure 2.26. When Vi < VR , D is ON. Therefore, Vo =Vi . When Vi ≥ VR , D is OFF. Therefore, Vo =VR The circuit is a positivepeak clipper that clips the positive peak at VR.
Diodes, Characteristics, and Applications
Vo
D +
+
R π t Vi
0 π/2
Vo
Vo
−VR
π
0 VR
−VR
−VR
−
−
2π
0
Vi 0 π 2π
t
Figure 2.25 Negativepeak clipper
(vii) Negativebase clipper: Consider the circuit and the transfer characteristic in Figure 2.27. When Vi < − VR , D is ON. Therefore, Vo =Vi When Vi ≥ − VR , D is OFF. Therefore, Vo = − VR The circuit is a negativebase clipper that clips at −VR . Vo
D +
+
VR
VR Vo
R π 0
Vo
t Vi
π/2
0
π
2π
t
0
VR
VR Vi
−
− 0 π
2π
t
Figure 2.26 Positivepeak clipper.
Vo
D +
+
π
Vo
t Vi
0 π/2 −
Vo
−VR
R
0
π
2π
0 −VR
VR
−VR − Vi 0 π 2π
Figure 2.27 Negativebase clipper
69
70
Electronic Devices and Circuits
Shunt Clippers A shunt clipper or a parallel clipper is one in which the diode is connected in shunt with the output. (i) Positive clipper: Consider the circuit in Figure 2.28. When Vi ≥ 0, D is ON. Therefore, Vo = 0. When Vi < 0, D is OFF. Therefore, Vo =Vi The circuit is a positive clipper that clips the positive peak at 0. Vo
R +
+
Vo 0
π
Vo
D
t Vi
0
2π
π
0
t
π
π/2
t
0 π/2 −
− Vi 0 π 2π
t
Figure 2.28 Shunt positive clipper
(ii) Negative clipper: Consider the circuit in Figure 2.29. When Vi ≥ 0, D is OFF. Therefore, Vo =Vi When Vi ≤ 0, D is ON. Therefore, Vo = 0. The circuit is a negative clipper that clips the negative peak at 0. Vo
R + + Vo
π
t Vi
0
D
0
π
π/2 −
0
Vo
0 π/2 −
t
Vi 0 π 2π
t
Figure 2.29 Shunt negative clipper
2π π
t
Diodes, Characteristics, and Applications
71
It is possible to clip the input at different levels using biased shunt clippers, and the circuits and the waveforms are shown in Figure 2.30. Vo
Vo
R
VR
VR
+ +
2π t
π
Vo
D
t Vi
0 π/2
0
VR
π
Vi 0
VR
0
−
−
π 2π
t
(a) Positivepeak clipper
Vo
R + +
0
−VR
D
π
t Vi
0 π/2
Vo
Vo
2π
π
0 −VR
VR −
−
Vi
0 π 2π
(b) Negativebase clipper
Vo
R + +
π
t Vi
0 π/2 −
Vo VR
D
VR
Vo 0
VR
VR
− Vi
0 π
2π
t
(c) Positivebase clipper
0
π
t
72
Electronic Devices and Circuits
Vo
R +
Vo
+
−VR
D
π t Vi
0 π/2
0
t
0 VR
VR
−
2π
π
Vo
− Vi
0 π
2π
t
(d) Negativepeak clipper
Figure 2.30 Circuits and waveforms of biased shunt clippers
2.6.2 TwoLevel Clippers An input signal can be clipped at two different levels so as to get an ouput of the desired nature.
Limiter The positive and negative peaks of the input signal may be clipped either at different levels or at the same level. If the clipping levles are the same, then the circuit is called a limiter. The circuit, the transfer characteristic, and the waveforms of a limiter are shown in Figure 2.31. D1 and VR form the positivepeak clipper and D2 and −VR form the negativepeak clipper. Thus, a cascaded combination of a positivepeak clipper and a negativepeak clipper operates as a limiter. When Vi < − VR , D2 is ON and D1 is OFF Vo = − VR. When Vi > VR, D1 is ON and D2 is OFF.Vo = VR. When −VR < Vi < VR, D1 is OFF and D2 is OFF Vo = Vi . VR Vo
−V
R
VR Vo
−VR 0
+ +
VR
D1 π VR
VR − π 2π
t
Figure 2.31 Limiter
0
−VR
0
−
VR Vi
π/2
Vo
D2
t Vi
0
V
2π π
t
73
Diodes, Characteristics, and Applications
Positive Slicer If only a portion of the positive half cycle of the input signal that lies between two voltage levels, VR1 and VR2 , is to be available at the output, then the circuit that delivers this output is called a positive slicer (Figure 2.32). Obviously, it is a cascaded configuration of a positivebase clipper and a positivepeak clipper (Figure 2.32). When Vi VR2 , D1 is OFF and D2 is ON Vo =VR2 . When VR1 VR1 2π
t
Figure 2.32 Positive slicer
Example 2.11 Design a negative slicer to slice a sinusoidal signal between the voltage levels −3 V and −5 V. The diode forward resistance is 10 Ω and the reverse resistance is 10 MΩ. Solution: R is usually chosen as R = Rf Rr = 0.01´103 ´10 ´106 = 10 kW The circuit is a cascaded configuration of a negativebase clipper and a negativepeak clipper, with VR1 = − 3 V and VR2 = − 5 V (Figure 2.33).
−VR2 −VR1
R
0
+
0
+
π 0
D1
D2
t Vi
π/2
–VR2
VR1
0
−
VR2 3V 5V − –VR2 < –VR1
–VR1
Vo
π 2π t
Figure 2.33 Negative slicer
π
2π
t
74
Electronic Devices and Circuits
Zener diodes can also be used in clipping circuits. A limiter using Zener diodes is shown in Figure 2.34. During positive half cycle of the input, D1 is forward biased and D2 is reverse biased, and hence Vo = (VD +VZ ) and during the negative half cycle of the input cycle D2 is forward biased and D1 is reverse biased, and hence Vo = − (VD +VZ ) . R
Vo (VD +VZ)
+
+
D1
Vi
D2 −
+ VD − + Vo VZ − −
– (VD + VZ)
0 (V +V ) D Z
Vi
– (VD +VZ)
Figure 2.34 Limiter using Zener diodes
Example 2.12 For the circuit shown in Figure 2.35, a sinusoidal input vi = 50 sinwt is applied as input. Plot the waveforms.
15 K
10 K
+
+ D1
D2
10 V
25 V
Vo
Vi
Solution: (i) When Vi 25 V, D1 is OFF and D2 is ON, Figure 2.36(b) Vo = 25 V 15 K
10 K
15 K
+
+ D1
+
D2 OFF
ON
Vo
Vi 10 V
−
D1 OFF
Vo 10 V
−
− (b)
15 K
+
10 K
D1 OFF
D2 OFF
+ Vo
Vi 10 V
−
25 V
−
(a)
+
+
D2 ON
Vi
25 V
−
10 K
25 V
−
− (c)
Figure 2.36 Equivalent circuits
75
Diodes, Characteristics, and Applications
(iii) When 10 V < Vi < 25 V , D1 and D2 are OFF, Figure 2.36(c) Vo =Vi .
vi 25 V Vo 10 V 0
Figure 2.37 shows the waveforms.
t
Figure 2.37 Waveforms
2.7
CLAMPING CIRCUITS
When a signal associated with a dc component is passed through a high pass RC circuit, the dc component is lost, as the capacitor blocks the dc. If the dc component is once again required to be introduced, then a clamping circuit is used. A clamping circuit reintroduces the dc component or restores the dc component. A clamping circuit is simply a dclevel shifter or dc restorer. It shifts the dc level of an input waveform to a desired level. Thus, clamping circuits can be positive clampers (that introduce a positive dc voltage) or negative clampers (that introduce a negative dc voltage) (see Figure 2.38). 0
0
−Vdc
t
t
Vdc
t
0 Output of Negative clamper
Input
Output of Positive clamper
Figure 2.38 Input and output of clamping circuits
2.7.1 Working of a Clamping Circuit p of the input, Vi , 2 with the polarity shown at
Consider the circuit in Figure 2.39 and its waveforms. During the period 0 to
D is ON and the output Vo = 0. The capacitor C gets charged to Vm p p . After , the input decreases and the voltage across D is (Vi − Vm ), which reverse biases D 2 2 and the diode is OFF. Vm π
Vi 0
C
+
−
+
+ Vi
Vm
2π
−V m Vo
D
t
π/2
π/2
0
−
−
Vo −Vm
π
t
2π
−2Vm
(a) Circuit
(b) Waveforms
Figure 2.39 Negative clamper
76
Electronic Devices and Circuits
Therefore, (2.61)
Vo = Vi − Vm At p,Vi = 0 ,Vo = 0 − Vm = − Vm . At
3p , Vi = − Vm ,Vo = − Vm − Vm = − 2Vm . 2
Thus, for a quarter cycle, the output is zero. However, after one cycle, the positive peaks are clamped to 0 V, indicating that a negative voltage is introduced by the clamping circuit. If for some reason or the other the input increases from Vm to Vm1, the diode once again conducts for a quarter cycle, and the positive peaks of the output are once again clamped to zero (Figure 2.40).
2.7.2 Practical Clamping Circuit However, if the input decreases, there is no way that the output can once again be clamped, because there is no path for the discharge of the condenser C. If an alternate path for the discharge of C is provided through, R when D is OFF, the charge on C discharges exponentially with a time constant RC. Again, when the voltage just becomes positive, D conducts and the positive peaks of the input will once again be clamped to zero after a few cycles (Figure 2.41). V m1 Vm Vi
0
C
−
+ + Vi
Vm
+ D
Vo 0
−
− Vo
−2Vm
−2Vm1
Figure 2.40 Output of the clamping circuit in Figure 2.39 when Vi increases
The circuit in Figure 2.42 is a positive clamper. The polarity of the diode is reversed, and the negative peaks of the input are clamped to 0 level.
77
Diodes, Characteristics, and Applications
2.7.3 Biased Clamping Circuits If the positive or negative peaks of an input signal are to be clamped to a reference voltage, VR, this dc voltage is introduced in the output circuit. The voltage level to which the peaks in the output are clamped depends on the polarity of the diode and the polarity of the reference voltage. To understand biased clamping, consider the following examples: Vm Vm2 Vi 0
t
C
+
− +
+ Vm
Vi
Vo
D
0
R
−
t
− Vo −2Vm2 −2Vm Discharge of C with τ = RC
Figure 2.41 Output of the clamping circuit when Vi decreases Vm π/2
Vi
t π
C −
+
+
+ Vi
2π
0
Vm
−Vm Vo
D
2Vm −
− Vo Vm
t
π 2π
0 π/2
(a) Circuit
(b) Waveforms
Figure 2.42 Positive clamper
Example 2.13 A symmetric square wave of 1 kHZ and having a peak amplitude of 10 V is applied to the clamping circuit shown in Figure 2.43. Compute and plot the waveforms. Solution: When the input swings to 10 V, D is ON and VA = 10 − 2 = 8 V with the polarity shown. Under steady state, Vo = Vi − VA = Vi − 8 When Vi =10 V, Vo = 10 − 8 = 2 V When Vi = −10 V, Vo = − 10 − 8 = − 18 V. However, the peaktopeak swing remains as 20 V only.
78
Electronic Devices and Circuits C
+10 V
+ VA
+
D
0
R
Vi
Vo VR
−
−10 V
2V 0
+
−
2V −
−18 V 1 mS
1 mS
Figure 2.43 Clamping circuit for Example 2.13
Example 2.14 A symmetric square wave of 1 kHZ and having a peak amplitude of 10 V is applied to the clamping circuit shown in Figure 2.44. Compute and plot the waveforms. C
+10 V
+ VA
+
D
0
R
Vi
Vo VR
−
−10 V
0 −2 V
+
−
2V −
−22 V 1 mS
1 mS
Figure 2.44 Clamping circuit for Example 2.14
Solution: When the input swings to 10 V, D is ON and VA =10 − ( −2 ) =12 V with the polarity shown. Under steady state, Vo =Vi −VA =Vi − 12 V When Vi = 10 V, Vo = 10 − 12 = − 2 V When Vi = −10 V, Vo = −10 − 12 = − 22 V. Example 2.15 A symmetric square wave of 1 kHZ and having a peak amplitude of 10 V is applied to the clamping circuit shown in Figure 2.45. Compute and plot the waveforms. C
+10 V −
−
22 V
+
+ VA R
0
Vi
−10 V
+
D
VR
Vo 2V −
2V 0 1 mS
1 mS
Figure 2.45 Clamping circuit for Example 2.15
Diodes, Characteristics, and Applications
79
Solution: When the input swings to −10 V, D is ON and VA = −10 − 2 = − 12 V, with the polarity shown. Under steady state, Vo = Vi − VA = Vi − ( −12 ) V = (Vi + 12 ) V When Vi = −10 V, Vo = −10 + 12 = 2 V When Vi = 10 V, Vo = 10 + 12 = 22 V . Example 2.16 A symmetric square wave of 1 kHZ and having a peak amplitude of 10 V is applied to the clamping circuit shown in Figure 2.46. Compute and plot the waveforms. C
+10 V −
18 V
+
+
− VA
R
0
−10 V
Vi
D
+
VR
Vo 2V −
0 −2 V 1 mS
1 mS
Figure 2.46 Clamping circuit for Example 2.16
Solution: When the input swings to −10 V, D is ON and VA = −10 + 2 = − 8 V, with the polarity shown. Under steady state, Vo = Vi − VA = Vi − ( −8) V = (Vi +8) V When Vi = −10 V, Vo = −10 + 8 = − 2 V When Vi = 10 V, Vo = 10 + 8 = 18 V .
2.7.4 Clamping Circuit Theorem Clamping circuit theorem states that for any input, under steadystate condition, the ratio of the area under the output curve when the diode is forward biased, Af to the area of the output curve when the diode is R reverse biased, Ar is equal to the ratio f R Af Rf = Ar Rr
(2.62)
Af V1 0 T1
V V − V1
Ar
T2
Figure 2.47 Clamping circuit theoremoutput waveform
Example 2.17 For the output shown in Figure 2.47, V = 40 V, T1 = 1000 µS and T2 = 10 µS Rf =10 Ω , and R =100 kΩ. Find V1 to which the output is clamped.
80
Electronic Devices and Circuits
Solution: Af =1000V1 and Ar =10 ( 40 −V1 ) 1000V1 10 = = 0.1 × 10 −3 10 ( 40 − V1 ) 100 × 103 1000V1 = ( 40 −V1 ) × 10 −3
V1 = 40 µV
2.8 TUNNEL DIODE In a PN junction diode, the width, W of the depletion region is given as follows: W≈
2eVB qN A
(2.63)
where q = charge of an electron = 1.6 ×10 −19 Coulombs N A = impurity concentration on the Pside, number of electrons/m3 e0 = permittivity of free space = 8.85 ×10 −12 F/m er = Relative permittivity of Ge is 16 and that of Si is 11.9 e = absolute permittivity of Si = e 0e r = 11.9 × 8.85 ×10 −12 = 10.53 × 10 −11 F / m VB = barrier potential = 0.5 V Let N A = 3 × 1018 / m 3 W=
2 ´10.53 ´10 11 ´ 0.5 = 14.8 m 1.602 ´10 19 ´ 3 ´1018
(1m = 10 6 m)
Let the impurity concentration be increased to N A = 3 × 1022 / m 3 , then W=
2 ´10.53 ´10 11 ´ 0.5 = 0.148m 1.602 ´10 19 ´ 3 ´1022
The width of the depletion region decreases substantially with increase in impurity concentra1 tion. From Eqn. (2.63), it is seen that W a . That is, the width of the depletion region is NA inversely proportional to the square root of impurity concentration. Thus, we see that when the concentration of the impurity charge carriers is very high, the width of the depletion region becomes negligibly small. A tunnel diode, also known as the Esaki (inventor) diode is a twoterminal PN junction diode in which the doping is nearly 1000 times higher than that of an ordinary PN junction diode. With this huge amount of doping, the potential barrier becomes so thin that electrons can penetrate or punch through the junction with the velocity of light, even though they do not possess enough energy to overcome the potential barrier. This results in large forward current at a relatively low forward
Diodes, Characteristics, and Applications
81
voltage ≈ 0.1 V. The charge carriers that possess negligible energy punch through the barrier instead of surmounting it. This phenomenon is called tunneling and the diode, as a result, is called tunnel diode. The reverse breakdown voltage is also reduced to a very small value. But usually this diode is used in the forwardbiased mode. The principle of working of the tunnel diode and its VI characteristic are better explained with the help of the energylevel diagrams (ELDs). A large number of electrons exist between ECN and EFN in a heavily doped Ntype semiconductor, and a large number of holes exist between E VP and EFP in a heavily doped Ptype semiconductor. If now a PN junction is formed, the ELD of the junction under zero bias condition is shown in Figure 2.48. Under this condition, the Fermi levels of both electrons and holes are the same, that is EFN = EFP. As the energy associated with the electrons is not sufficient enough to cross the junction,there can be no current in the device. Space charge region Pside Conduction band
N  side
ECP EG Conduction band
EVP EFP
EFN Valence band
Holes
ECN
Electrons
EG Valence band
EVN
Figure 2.48 Heavily doped PN junction with zero bias
(i) Now let the junction be forward biased by a small voltage, say 0.1 V (for Si), then the barrier potential decreases by the same amount. Hence, Nside energy levels shift upwards with respect to those on the Pside (Figure 2.49). It can be seen that a fewer number of electrons exist on the Nside in the conduction band that has the same energy as holes in the valence band on the Pside. Therefore, electrons from the Nside can tunnel through the narrow junction to the Pside, giving rise to a small current. If, the forwardbias voltage is increased from 0.1 V to 0.3 V, this current increases with increasing forwardbias volatge (points O to A in Figure 2.55). Pside Conduction band
N  side Tunneling of electron (low)
ECP EG
Conduction band
EVP Holes
EFP
EFN Electrons
Valence band
ECN EG Valence band
EVN
Figure 2.49 Heavily doped PN junction with small forward bias (0.1 V)
82
Electronic Devices and Circuits
(ii) When the forwardbias volatge is 0.3 V (for Si), it is seen that E VP = EFN and ECN = EFP (Figure 2.50). Maximum tunneling occurs under this condition, and the forward current reaches a maximum value (point A in Figure 2.55). (iii) When the forward bias voltage is increased beyond 0.3 V, say from 0.3 V to 0.6 V, Figure 2.51, not many electrons can tunnel through, thereby the current starts reducing (points A to B in Figure 2.54) and at 0.6 V, this current is minimum (point B in Figure 2.55). (iv) When the forwardbias voltage is increased beyond 0.6 V, the electrons in the conduction band on the Nside cannot cross the junction to reach the holes in the valence band on the Pside, and consequently, the tunneling current is reduced to zero (Figure 2.52). However, as the forwardbias voltage is increased further, the electrons surmount the potential energy barrier to reach the Pside; and from now onward, the tunnel diode behaves as an ordinary semiconductor diode. The current increases with the applied voltage (Figure 2.55, beyond point B). (v) When the reversebias voltage is applied, the height of the barrier increases on the Pside and that on the Nside decreases (Figure 2.53). Some of the holes in valence band on the Pside have the same energy as the electrons in the conduction band on the Nside; these can tunnel through, resulting in a reverse current. As the magnitude of the reversebias voltage increases, this current abruptly rises to a large value as in a Zener diode. Figure 2.54 shows the current components in a tunnel diode. Figure 2.55 gives the net variation of I F for a variation in VF . Conduction band ECP
Tunneling of electrons (Maximum) EG
Conduction band
EVP Holes
EFP
EFN ECN
Valence band
Electrons
EG Valence band
EVN
Figure 2.50 Heavily doped PN junction for a forward bias of 0.3 V ECP Tunneling of electron (Low once again)
EFN EVP Holes
Electrons ECN
EFP
EVN
Figure 2.51 Heavily doped PN junction for a forward bias of 0.3–0.6 V
Diodes, Characteristics, and Applications
ECP
Electrons EFN
EVP
ECN
Holes EFP EVN
Figure 2.52 Heavily doped PN junction for a forward bias greater than 0.6 V
ECP
EVP
Holes tunneling to vacant sites
Holes EFP EFN Electrons ECN
EVN
Figure 2.53 ELD of a tunnel diode under reverse bias
Tunneling current IF(mA)
A
C Diode current B
VR(V)
O
IR
Figure 2.54 Tunnel diode current components
VF(V)
83
84
Electronic Devices and Circuits
Tunneling region
IF (mA)
Negative resistance region
A
IP
C
B
IV VR(V)
Diode region
O
0.3
0.6
VP
VV
0.9 V VF
IR
Figure 2.55 VI characteristic of a tunnel diode (Si)
In the region A to B, the tunnel diode behaves as a neagtive resistance, that is with increase in voltage there is a decrease in current. The forward characteristic of the tunnel diode is similar to the characteristic of a unijunction transistor (UJT). A UJT and a tunnel diode, as such, can be used for generating oscillations. However, a tunnel diode is specifically used in microwave oscillators and other highspeed applications. The shematic representations of tunnel diode are shown in Figure 2.56, and its electrical equivalent circuit is shown in Figure 2.57.
A
A
K
K
Figure 2.56 Schematic representations of a tunnel diode RS
LS
A C
−R n
K
Figure 2.57 Electrical equivalent circuit of a tunnel diode
Example 2.18 Construct the piecewise linear characteristic of a tunnel diode and calculate its negative resistance. Given data: I P = I F = 1 mA, I V = 0.15 mA, VP = 75 mV, VV =350 mV, VF =500 mV. Solution: The VI characteristic of the tunnel diode is plotted in Figure 2.58. At VF =VP = 75 mV, I F = I P =1 mA (point A) At VF =VV =350 mV, I F = I V = 0.15 mA (point B)
Diodes, Characteristics, and Applications
85
The diode curve varies as the OA curve. When the forward voltage increases from 10 mV to 75 (=65 mV) mV, the tunneling current increases from 0.15 mA to 1 mA, The VI characteristic and the diode characteristic are identical. Hence, the voltage at point C is 500 − 65 = 435 mV at which the current is 0.15 mA. The current at voltage 500 mV is 1 mA (Point D). From Figure 2.58, the negative resistance is Rn = −
∆VF −(350 − 75 ) = − 323.5 Ω = ∆I F 1 − 0.15
A
IF(mA) 1.0 IP
0.7 ∆IF = 0.85 mA 0.5
0.3 0.15 O 0
IV
B
C
∆VF = 275 mV 10
75
200
350
VP
435
500
VF (mV)
VV
Figure 2.58 Forward characteristic of the tunnel diode
2.9 VARACTOR DIODE A varactor diode is also known as voltage variable capacitor diode, varicap, and as tuning diode. A varactor diode is a reversebiased diode in which the junction capacitance or the transition capacitance, CT, varies as the width of the depletion region varies. Consider an unbiased PN junction diode (Figure 2.59). W is the width of the depletion region. If the diode is reverse biased, electrons and holes are drawn away from the junction, and therefore the width of the depletion region increases as the reversebias voltage increases (Figure 2.60). This can be considered as a parallel plate condenser, the junction having an area of crosssection as A (m2), spacing between plates as W (m) and permittivity of the dielectric (semiconductor) as e. While considering a reversebiased diode, it has been shown that the transition capacitance CT is given as follows: CT =
eA W
(2.64)
CT ∝
1 W
(2.65)
86
Electronic Devices and Circuits Width of the depletion region W
P
Anode, A
− −
+ +
− −
+ +
− −
+ +
Acceptor ions
Cathode, K
N
Donor ions
Figure 2.59 Depletion region in an unbiased semiconductor diode
Width of the depletion region W
A
P
− − − −
+ + + +
− − − −
+ + + +
− − − −
+ + + +
Acceptor ions
N
K
Donor ions
VR
Figure 2.60 Depletion region increases with increase in reversebias voltage
Depending on the doping profiles, varactor diodes are either abrupt (steptype) junction devices or linearly gradedtype junction devices. In the abrupt junction varactor diode, the semiconductor material is uniformly doped, and it changes abruptly from Ptype to Ntype at the junction. The charge density profile is shown in Figure 2.61(a). Here, it is assumed that NA, the acceptor ion concentration is very much larger that ND, the donor ion concentration. Since the net charge must be zero, N AWp = N DWn
Or
Wn =
Since N A >> N D , Wn >> Wp
NA Wp ND
Diodes, Characteristics, and Applications
87
Therefore, W =Wn +Wp ≈Wn In a lineargraded junction device, the charge density varies gradually, almost linearly, as shown in Figure 2.61(b). It is also known that W ∝ VR for a steptype junction Or
1
CT ∝
1
(VR )2 and, W ∝ 3 VR for a linearly gradedtype junction Or
1
CT ∝
1
(VR )3 r
r
Charge density
Charge density ND
−W/ 2
0
0
W/ 2
NA >> ND
−NA
Wn Wp W
(a) Abrupt junction
(b) Linearly graded junction
Figure 2.61 Charge density profiles of abrupt and lineargraded junctions
Therefore, CT ∝
1
(VR )
1 2
or
CT ∝
1 1
(2.66)
(VR )3
It can be noted from Eqn. (2.66) that CT varies inversely with VR . If the reversebias voltage increases,CT decreases; and if the reversebias voltage decreases, CT increases. This is the basic principle of operation of varactor diodes. A typical graph that depicts the variation of CT (pF) with the reversebias voltage, VR (V) is shown in Figure 2.62.
88
Electronic Devices and Circuits
From Figure 2.62, it can be noted that typically CT varies from 25 pF to 500 pF as VR varies from −10 V to −1 V. The schematic representation and the electrical equivalent circuit of varactor diode are shown in Figures 2.63(a) and 2.63(b), respectively. C T(pF) 500
100
25 VR(v)
0 −10 −9
−7
−5
−3
−1
Figure 2.62 Variation of CT as a function of VR RS
A
A
K
K CT
(a) Schematic representation of varator diode
(b) Equivalent circuit
Figure 2.63 Schematic representation and equivalent circuit of a varactor diode
Here RS is the resistance of the semiconductor material. The main application of varactor diodes is as tuning capacitors to adjust the resonant frequency of the tuned circuits, Figure 2.64. If f0 is the resonant frequency of the tank circuit comprising C and L, then by adjusting the reversebias voltage on the varactor diode (changing CT ), the frequency can be varied as f0 ± ∆f . f0 =
f0 L
C
1
(2.67)
2p LC
f0 ± ∆f
Figure 2.64 Varactor diode used to tune the resonant circuit
Example 2.19 Calculate the value of CT of a Si PN junction whose area of cross section is 1 mm × 1 mm, space charge thickness is 2 × 10−4 cm. The dielectric constant of Si relative to free space is 11.9.
Diodes, Characteristics, and Applications
Solution: We have CT =
(
Given A= 1×10 −3
)
2
89
eA W
= 1×10 −6 m 2
Space charge width, W = 2 ×10 −4 cm = 2 ×10 −6 m Absolute permittivity of Si, e = e 0 e r = 11.9 × 8.85 × 10 −12 = 10.53 × 10 −11 F/m ∴ CT =
eA 10.53 × 10 −11 × 1 × 10 −6 = = 52.65 pF. W 2 × 10 −6
Example 2.20 The depletion capacitance of an abrupt junction is 4 pF at a reversebias voltage of 4 V. (i) Calculate the change in the junction capacitance for (a) 1 V increase in bias voltage (b) 1 V decrease in bias voltage. (ii) Determine the incremental change in the capacitance. Solution: (i) For an abrupt junction, CT ∝ 1 VR K Or CT = VR We have, at VR = 4 V, CT = 4 pF. ∴K = CT VR = 4 × 4 = 8 (a) The new VR is VR1 = VR + 1 = 4 + 1 = 5 V CT1 =
8
K =
5
VR1
= 3.58 pF
(b) The new VR is VR 2 = VR −1 = 4 −1 = 3 V CT 2 =
8
K = VR 2
3
= 4.62 pF
(ii) DCT = 4.62  3.58 =1.04 pF
2.10
SCHOTTKY BARRIER DIODE
When a metal such as aluminum is required to make a contact with an Ntype semiconductor, two types of contacts are possible: (i) ohmic contact and (ii) rectifying contact.
2.10.1 Ohmic Contact When a terminal of a device is required to be brought out externally to enable connections to be made to that terminal, then an ohmic contact is provided. In order to provide metal–semiconductor ohmic contact, an N++ (heavily doped Ntype) region is created in the Ntype semiconductor, near the surface. Aluminum is deposited on this N++ region to create an ohmic contact.
90
Electronic Devices and Circuits
2.10.2 Rectifying Contact If aluminum is directly deposited on the Ntype semiconductor, then the type of contact made is called a rectifying contact. A rectifying contact results in a metal–semiconductor diode, which has the similar VI characteristics as a PN junction diode. Such a metal–semiconductor diode is called a Schottky diode. Silicon Schottky barrier diode is different from a PN junction diode in that the depletion region exists only in the Ntype semiconductor and no depletion region can exist in the metal. As the depletion region is reduced practically to half in a Schottky diode, it can conduct at a lesser forwardbias voltage when compared to a PN junction diode. This is one major advantage of the Schottky diode. Next, if a semiconductor diode is ON for some time and if it is required to be switched into the OFF state, the device will not switch into the OFF state immediately because of the stored charges on either side of the junction. There can be a finite time delay before the device switches into the OFF state. This time delay is called the reverse recovery time, which is large for a PN junction diode. A Schottky diode, practically, has no depletion region. This eliminates the stored charges near the junction. Consequently, the switching speed of a Schottky barrier diode is faster. Semiconductor diodes may operate satisfactorily up to 10 MHz, whereas Schottky diodes can operate up to 300 MHz. The construction of a Schottky barrier diode is shown in Figure 2.65(a) and its schematic representation is shown in Figure 2.65(b). The diode is formed by the rectifying contact at anode A and ohmic contact is provided at the cathode K. Aluminum Rectifying contact
A
K
Ohmic contact
SiO2
ntype A
(a) Construction
K
(b) Schematic representation
Figure 2.65 Schottky barrier diode
In the case of aluminum and also in the Ntype semiconductor, the charge carriers are mainly electrons, since holes are smaller in number in the Ntype semiconductor. The energies of the electrons in the Ntype semiconductor are small when compared with the energies of the electrons in the metal. As such, when the diode is unbiased, electrons cannot cross from the Ntype semiconductor into the metal, because of the junction barrier called the Schottky barrier. However, when the diode is forward biased, electrons acquire large energies and cross the barrier. As the electrons reach the metal with large energies, these charge carriers are called hot carriers, and the Schottky diode is also known as the hot carrier diode. When reverse biased, a Schottky diode has a smaller breakdown potential when compared with an ordinary semiconductor diode. The VI characteristics of a semiconductor and Schottky diodes are shown in Figure 2.66. It can be noted that a Si Schottky diode has a smaller barrier potential (typically, 0.2–0.25 V); whereas, the barrier potential of the Si semiconductor diode is typically 0.7 V.
Diodes, Characteristics, and Applications
IF (mA)
91
Schottky diode
Semiconductor diode VR (V)
VR2
VR1 0.25
0.7
VF (V)
(mA) IR
Figure 2.66 VI characteristics of Schottky and semiconductor diodes
The main differences between Schottky and PN junction diodes are as follows: 1. Schottky diode is a unipolar device, since holes are so few in number. But a semiconductor diode is a bipolar device, that is both electrons and holes are the charge carriers. 2. In the absence of holes in the metal, the depletion layer is negligibly small. Hence, there can be no stored charges near the junction when the diode is forward biased. As such, the device can be quickly switched OFF. Therefore, a Schottky diode is used for highspeed switching applications. By contrast, a semiconductor diode has a relatively larger reverse recovery time. Hence, the speed of switching is limited by the diffusion capacitance. 3. Because of a larger contact area between the metal and the semiconductor, the forward resistance of the Schottky diode is smaller than an ordinary semiconductor diode. Hence, noise gets reduced. 4. The reverse breakdown potential of a Schottky diode (VR1) is very much smaller than a semiconductor diode (VR2). The approximate equivalent circuit of the Schottky diode is simply an ideal diode in shunt with junction capacitance (Figure 2.67). Ideal diode A
K
C
Figure 2.67 Equivalent circuit of Schottky diode
2.11
SEMICONDUCTOR PHOTODIODE
In an ordinary semiconductor diode, when reverse biased, the current that flows is only due to thermally generated minority charge carriers and is negligibly small at room temperature (typically of the order of µA). This current is called the reverse saturation current. When the temperature of the junction is increased, more number of electron–hole pairs are generated, and hence the minority carrier current increases. Electron–hole pairs are also generated due to incident light
92
Electronic Devices and Circuits
radiation on the junction, resulting in the increase in the reverse current in a diode. This current can further be increased by increasing the intensity of the incident light radiation. Twoterminal devices (diodes) that are designed to be sensitive to incident light radiation are called photodiodes as indicated in Figure 2.68. Light radiation
Transparent plastic casing
p
n IR
Reverse bias VR
Depletion region
Figure 2.68 Semiconductor Photodiode
When there is no incident illumination, the current in the photodiode is the minimum and is called the dark current, ID. Practically, this current can be taken to be zero (typically this current is of the order of 2nA). An illumination of 10 mW/cm2 can now cause a reverse current, IR of 18 µA. Increasing VR will not necessarily increase IR, because with a small VR itself all the charge carriers must have been swept across the junction. Hence, IR remains constant even with increase in VR. Now the illumination can be increased to 20 mW/cm2 and a different characteristic can be plotted. One can, thus, obtain a family of curves (Figure 2.69). DC load line I (mA) 80
50 mW/cm2
70 40 mW/cm2
60 50
30 mW/cm2
40 20 mW/cm2
30
VF (V)
20
10 mW/cm2
10
H = 5 mW/cm2 Dark current VR (V) 40
0.4 Forward bias
0
10
20
30
Reverse bias
Figure 2.69 Characteristics of a photodiode
Diodes, Characteristics, and Applications
93
The current in a photodiode is given as follows: V V I = I S + I o 1 − e h
(2.68)
T
where, I is the total reverse current, IS is the reverse current proportional to illumination, and Io is the reverse current due to minority carriers and V is the applied voltage (positive for forward bias and negative for reverse bias). If V is a large reversebias voltage, then e
V hVT
I S , I = I S e
V hVT
(2.72)
Let V1 be the voltage at which the forward current is 3I. V1
∴ 3I = I S e
hVT
(2.73)
Dividing Eqn. (2.73) by Eqn. (2.72),
3= e
V1 − V = ln 3 hVT
V1 −V hVT
V1 − V = hVT ln 3 = 2 × 0.026 × 1.1 = 0.057 V Example 2.27 In a PN junction diode, the reverse saturation current at T1 is I S1. I S2 = 40 I S1 at T2 . Find the increase in temperature. T2 − T1
Solution: I S2 = I S1 2
10 T2 −T1
2 T2 − T1 log10 2 = log10 40 10
10
=
I S2 = 40 I S1
T2 − T1 log10 40 = log10 2 10 T2 − T1 = 10 × 5.32 = 53.2 °C
T2 − T1 =10 ×
1.602 0.3010
102
Electronic Devices and Circuits
Example 2.28 For the circuit shown in Figure 2.83, a sinusoidal signal vi = 50 sinwt is applied as input. The diodes are ideal. Plot the transfer characteristic.
D1
D2
+
+ 100 K Vo
Vi
Solution: (i) When Vi ≤ 0 V, D1 is ON and D2 is OFF, Figure 2.84(a). Vo = 0 V
100 K
20 V
−
−
Figure 2.83 Circuit for Example of 2.28
(ii) When 0 < Vi < 20 V , D1 is ON and D2 is ON, Figure 2.84(b). Vo = Vi
(iii) When Vi > 20 V , D1 is OFF and D2 is ON, Figure 2.84(c).
Vo = 20 ×
D1 +
D2 100 K
D1 + Vo
Vi
−
20 V
100 K
100 = 10 V 100 + 100
−
+
D2
D1 +
100 K
Vo
Vi
−
20 V
(a)
100 K
−
(b)
+
D2 +
100 K
Vo
Vi
−
20 V
100 K
−
(c)
Figure 2.84 Equivalent circuits
Figure 2.85 gives the transfer characteristic. 20 V Vo
0
10 V 20 V
Vi
Figure 2.85 Transfer characteristic
Example 2.29 For the following clamping circuits, the input is a symmetric square wave, referenced to zero and having a peaktopeak amplitude of 10 V. Plot the output. Solution: For the circuit in Figure 2.86(a), the positive peaks of the output are clapmed to VD and for the circuit in Figure 2.86(b), the negative peaks of the output are clapmed to VD .
Diodes, Characteristics, and Applications
+
0
10 V
VD
−
0
+
C
+ Vi
103
R
+ VD −
10 V
D Vo
Vo
−
− (a) −
+ 0
10 V
Vi
+ +
C
R
− VD +
D Vo
Vo
10 V
VD
−
−
0
(b)
Figure 2.86 (a) Negative clamper and (b) positive clamper
Example 2.30 A Si diode is operated at 300 K. Find the reverse voltage at which the current falls to 80 percent of I S. hVV Solution: I = I S e − 1
For Si, h = 2
T
80 percent reverse saturation current = 0.8I S hVV 0.8I S = I S e − 1 T
V
0.2 = e 2 × 0.026
V = ln ( 0.2 ) 2 × 0.026
V =  83.6 mV
Summary • When forward biased, the junction diode offers a very small forward resistance, resulting in an appreciable forward current and behaves as a closed switch. When reverse biased, the current in the device is zero and behaves as an open switch. • Temperature has significant effect on the diode characteristics. VT and IS are temperature dependent. IS gets doubled for every 10°C rise in temperature. • When forward biased, the diode offers a capacitance called the diffusion capacitance or storage capacitance, CD; and when reverse biased, the capacitance offered by it is called the transition capacitance or space charge capacitance or depletion region capacitance, CT. CD » CT. • Zener and avalanche diodes are breakdown diodes. Zener breakdown occurs due to the physical rupturing of the covalent bonds due to the applied reversebias voltage. An avalanche diode conducts heavily, when reverse biased, at larger voltages due to the process called avalanche multiplication.
104
Electronic Devices and Circuits
• A clipper eliminates a portion or portions of the input signal. A clamping circuit is simply a dclevel shifter or dc restorer. It shifts the dc level of an input waveform to a desired level. • A heavily doped PN junction diode in which the potential barrier becomes so thin that the charge carriers that possess negligible energy punch through the barrier instead of surmounting it. This phenomenon is called tunneling, and the diode is called tunnel diode. • A varactor diode is a reversebiased diode in which the junction capacitance or the transition capacitance, CT varies as the width of the depletion region varies. • A metal–semiconductor diode is called a Schottky diode and is different from a PN junction diode in that the depletion region is reduced practically to half when compared to a PN junction diode. • Twoterminal devices (diodes) that are designed to be sensitive to incident light radiation are called photodiodes. • In a PIN diode, a slightly doped intrinsic (I ) region is sandwiched between heavily doped P and Nregions and PIN diodes are used as microwave switches, phase shifters, and attenuators, where high isolation and low loss are required. • Gunn and IMPATT diodes are used at microwave frequencies to generate oscillations.
multiple ChoiCe QueStionS 1. Which capacitance dominates in the reversebias region? (a) Depletion capacitance (b) Diffusion capacitance (c) Distributed capacitance (d) Stray capacitance 2. Schottky diodes is also known as (a) avalanche diode (c) hot carrier diode
(b) breakdown diode (d) junction diode
3. What breakdown mechanism is observed in a diode which has a breakdown voltage less than 5 V? (a) Avalanche breakdown (b) Zener breakdown (c) Physical breakdown (d) Internal breakdown 4. A Zener diode is normally (a) reverse biased (c) unbiased
(b) forward biased (d) none of the above
5. A 3.8 V Zener diode has a power rating of 2 W. The maximum Zener current is (a) 526.3 mA (b) 5.263 A (c) 526 A (d) 0.05263 A 6. What breakdown mechanism is observed in a diode that has a breakdown voltage more than 5 V? (a) Avalanche breakdown (b) Zener breakdown (c) Physical breakdown (d) Internal breakdown 7. Avalanche breakdown results basically due to (a) impact ionization (b) strong electric field across the junction (c) emission of electrons (d) rise in temperature 8. The varactor diode is usually (a) forward biased (c) unbiased
(b) reverse biased (d) holes and electronics
Diodes, Characteristics, and Applications
105
9. The depletion region in a junction diode contains (a) only charge carriers (of minority type and majority type) (b) no charge at all (c) vacuum, and no atoms at all (d) only ions , that is, immobile charges 10. The main reason why electrons can tunnel through a PN junction is that (a) they have high energy (b) the barrier potential is very high (c) the depletion layer is extremely thin (d) the impurity level is low 11. Negative resistance is exhibited by a Gunn diode when electrons are transferred from (a) low mobility energy band to high mobility energy band (b) high mobility energy band to low mobility energy band (c) diffusion region to drift region (d) drift region to diffusion region 12. In an stepgraded junction varactor diode 1
1
(a) C is proporrtional to V 3
(b) C is proporrtional to V 2
(c) C is proporrtional to V
−1 2
(d) C is proporrtional to V
−1 3
13. In a linearly graded junction varactor diode 1
1
(a) C is proporrtional to V 3
(b) C is proporrtional to V 2
(c) C is proporrtional to V
−1 2
(d) C is proporrtional to V
14. For an ideal PN junction diode, the forward resistance is . (a) zero, infinity (b) infinity, zero (c) zero, zero (d) infinity, infinity 15. Zener breakdown occurs due to (a) high forward voltage (c) strong electric field
−1 3
and the reverse resistance is
(b) high reverse voltage (d) strong magnetic field
16. If the breakdown in a diode is due to avalanche multiplication, then the temperature coefficient of the diode is (a) negative (b) positive (c) zero (d) infinity 17. For a Zener diode, the temperature coefficient is (a) negative (b) positive (c) zero (d) infinity 18. A Schottky diode is preferred over a semiconductor diode for highfrequency applications because of its (a) faster switching speed (b) slower switching speed (c) large physical size (d) small physical size
106
Electronic Devices and Circuits
19. Both avalanche diodes and Zener diodes are commonly known as (a) avalanche diodes (b) Zener diodes (c) varactor diodes (d) tunnel diodes 20. Zener and avalanche diodes are used as (a) voltage reference elements (b) current reference elements (c) resistance reference elements (d) none of the above 21. In which of the following diodes the impurities are heavily doped? (a) PN junction diode (b) Gunn diode (c) Varactor diode (d) Tunnel diode 22. The minimum voltage required for a PN junction diode to conduct when forward biased is called (a) breakdown voltage (b) conducting voltage (c) cutin voltage (d) applied voltage 23. A circuit that is used to eliminate a portion or portions of the input signal is called (a) clamping circuit (b) clipping circuit (c) damping circuit (d) oscillator 24. A circuit that is used to reintroduce the dc component that is lost during transmission is called (a) clamping circuit (b) clipping circuit (c) damping circuit (d) oscillator 25. Avalanche multiplication and transit time effects are responsible for negative resistance in the following diode: (a) Gunn diode (b) IMPATT diode (c) Varactor diode (d) Tunnel diode 26. A back diode is a tunnel diode in which (a) IP is reduced to the level of IV (b) IV is increased to the level of IP (c) current is zero (d) current is infinity
Short anSwer QueStionS 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14.
How does the reverse saturation current in a PN junction diode vary with temperature? What is a diffusion capacitance in a PN junction diode? What is the reverse recovery time of a PN junction diode? In a junction diode when the P material is more positive than the N material, then what type of biasing is it ? Why does the reverse current suddenly rise to a large value when the breakdown voltage is reached, in a Zener diode? What is avalanche multiplication and when does this phenomenon occur in a PN junction diode? What is a clamping circuit? State the clamping circuit theorem. What is tunneling? What is a varactor diode? What are the main advantages of a Schottky diode? What is photovoltaic effect? What is Gunn effect? What is an IMPATT diode?
Diodes, Characteristics, and Applications
107
long anSwer QueStionS 1. Obtain the expression for the diode current and draw the forward and reverse characteristic. 2. Derive the expressions for the diffusion and transition capacitances of the junction diode. 3. Write short notes on the following: (i) Zener diode and (ii) avalanche diode 4. With the help of neat circuit diagrams and transfer characteristics, explain the working of a limiter and a slicer. 5. With the help of a neat circuit diagram and waveforms, explain the working of the practical clamper. 6. Explain the working of the following diodes: (i) tunnel diode, (ii) varactor diode (iii) Schottky diode, and (iv) PIN diode. 7. Write short notes on the following: (i) Gunn diode and (ii) IMPATT diode.
unSolved problemS 1. Find the factor by which the reverse saturation current of a Ge PN junction diode increases when the temperature rises from 27°C to 127°C. 2. A Germanium diode operating at 27°C is forward biased at 0.4 V. The temperature is increased from 27°C to 127°C. By what factor will the forward current increase? 3. A silicon diode operated at 127°C has its reverse saturation current as 50 µA. Calculate its dynamic resistance at (i) forward voltage of 0.3 V and (ii) reverse voltage of −0.4 V. Assume ideal diode. 100 K 4. A diode has a forward current of 0.5 mA at 0.3 V and its forward current is 30 mA at a forward voltage of 0.6 V + + at 300 K. Is the diode a Si or Ge diode? D2 5. For the circuit in Figure 2.87, plot the transfer charD1 100 K acteristic and the input output waveforms, if the Vi Vo input varies as vi = 50 sinwt is applied as input. The − 10 V 20 V − diodes are ideal . Figure 2.87 6. A square wave referenced to 0 V has a peaktopeak swing of 20 V. Plot the output of the clamping circuit shown in Figure 2.88, if VR = 5 V. Assume that there is no distortion in the output.
C
+
+
D
Vi
−
5V
Figure 2.88
R
Vo
−
3
RECTIFIERS AND FILTERS
Learning objectives After reading this chapter, the reader will be able to
3.1
Appreciate the application of diodes in fullwave and halfwave rectifiers Calculate the possible values of dc and ac currents, rectification efficiency, ripple, and so on Understand the need for using different types of filters, such as inductor filter, capacitor filter, Ltype filter, and ptype filter, to reduce the ripple Appreciate the need for multiple filters
INTRODUCTION
A PN junction diode can be used for various applications, such as rectifiers, demodulators, clipping and clamping circuits, and so on. The choice of the diode for a specific application depends on many factors. A few important parameters are listed below: 1. Peak inverse voltage: The maximum reversebias voltage that can be applied to a PN junction diode is called peak inverse voltage (PIV) or peak reverse voltage (PRV). This is normally specified at a reverse saturation current. If the PIV rating of the diode used in a circuit is less than that required, then another diode is connected in series with the first diode. This is known as stacking of the diodes. If n identical diodes are stacked, then the PIV of the diode stack is n times the PIV of the individual diode. 2. Maximum power dissipation: If the current in the diode is ID and the voltage between the diode terminals is VD, then the amount of power dissipation in the device is PD = IDVD. PD can be PD(max) when the current and voltage take maximum values. For instance, if PD(max) is specified as 1 W at room temperature (25°C), it means that the diode can handle a dissipation of 1 W. Anything in excess of this will damage the device. However, with an increase in temperature, the dissipation capability of the diode decreases. This information is normally given by the manufacturer by way of a derating curve or specifies the same by a derating factor. Derating factor is specified as, say, D = 2.5 mW/°C. It means that the dissipation capability decreases by 2.5 mW per degree rise in temperature. 3. Switching speed: Ideally, it is assumed that the diode behaves as a switch. But we have seen that a forwardbiased diode has junction capacitance called the diffusion capacitance, CD. When reverse biased, the diode has transition capacitance (CT). As CD >> CT, CT influences the switching speed of the diode. But, at low frequencies, this is not a serious constraint.
109
Rectifiers and Filters
4. Forward and reverse resistances: Ideally, the forward resistance Rf of a diode (when ON, that is, when conducting) is zero. But a practical diode has Rf of a few ohms (typically 5–10 Ω). Similarly, the reverse resistance Rr of the diode (when OFF, that is when not conducting) is ∞. But a practical diode has Rr of a few megaohms (typically, 1–2 MΩs).
3.2
RECTIFIERS
All the electronic circuits require a dc voltage or battery to operate. Batteries may have to be used invariably, where there is no access to the conventional mains supply. However, the life of a battery is limited. Therefore, it becomes a necessity to derive the dc voltage from an ac source, preferably the mains power supply. This mains voltage of 230 V is an alternating signal operating at 50 cycles per second. The voltages that we normally need to operate electronic circuits are typically of the order of 3 V, 6 V, 9 V, 12 V, 15 V, etc., which are essentially low voltages. Hence, in majority of such applications, there is a need to step down the mains voltage using a transformer. A transformer is a device that transfers electrical energy from the primary winding to the secondary winding through inductive coupling. A varying current in the primary winding creates a varying magnetic flux in the transformer’s core, and thus a varying magnetic field through the secondary winding. This varying magnetic field induces a varying voltage in the secondary winding. The secondary voltage of the transformer can be chosen appropriately by choosing proper turns ratio of the transformer. Yet, there is a need to convert the alternating signal into a unidirectional one, called the dc signal. The circuits that convert the ac signals into dc signals are called rectifiers. These rectifiers are of two types: (i) halfwave rectifiers and (ii) fullwave rectifiers.
3.2.1 HalfWave Rectifier A halfwave rectifier is one in which the diode conducts for only onehalf of the input cycle period (Figure 3.1), and the input–output waveforms are shown in Figure 3.2. Ideal diode ON
D
vs = Vmsinwt 230 V, 1 φ 50c/s Mains
vs = Vmsinwt
+ RL
230 V, 1 φ Load 50c/s Mains
−
Rf
+ Idc
−
i
+ RL
VL Load −
Figure 3.1 Circuit of halfwave rectifier
The input to the rectifier circuit is a sinusoidal signal taken from the secondary of the transformer and varies as Vm sinwt . Neglecting Vg when forward biased, the diode can be replaced by an ON switch in series with the forward resistance of the diode, Rf. We have vs = Vm sinwt (3.1) Neglecting the resistance of the secondary winding of the transformer, the peak load current, Im is Im =
Vm Rf + RL
(3.2)
110
Electronic Devices and Circuits Vm vs
3p
0
2p
p
t
−Vm Input to the diode circuit Im
i
Idc 0
2p
p
3p
t
Output current
Figure 3.2 Input and output waveforms
The current i also varies as vs and is given as follows: I sin a for 0 ≤ a ≤ p i = I m sin wt = m 0 for p ≤ a ≤ 2p
(3.3)
where a = wt. But the output current flows in half cycles, which means that the output is no longer sinusoidal and as such will have a number of frequency components (w, 2w, 3w, and so on) in it in addition to the dc component. The components with frequencies 2w, 3w,… are called harmonics. This suggests that the output is not a constant value (dc) as desired, but will have unwanted ac components that will change the magnitude of the dc from time to time.
DC Component of Current Let us now try to find out the dc component of current, which is the average taken over one cycle, that is, from 0 to 2p. Idc =
1 2p
∫
p
0
Im sin a d a =
I dc =
Im [ −cosa ]p0 2p
Im I (1 + 1) = m p 2p
(3.4)
Vm p (Rf + RL )
(3.5)
I dc =
Rectifiers and Filters
111
Root Mean Square Component of Current The root means square or rms component of current for a sinusoidal signal is as follows:
Im 2
. In the case of halfwave rectifier, the rms value is calculated p
1 2 I m2 (sin a ) d a 2p ∫0
I rms =
I rms =
Im 2p
p Im = 2 2
(3.6)
Form factor, F is defined as follows: F=
I rms I m p = = 1.57 I dc 2 I m
(3.7)
Ripple Factor We are aware of the following relationship: (3.8)
2 2 I rms = I dc + I ac2
where Iac is the rms value of the ac components. The fluctuating component in the output is called the ripple. What is a ripple? If you throw a stone in steady water, you see ripples. A good dc source should give a constant dc voltage. If ripple is present along with this voltage, this voltage will change with time. The effectiveness with which the rectifier is able to reject the ripple is given by the ripple factor, g defined as follows: g =
I ac Vac = I dc Vdc
(3.9)
From Eqn. (3.8), (3.10)
2 2 I ac = I rms − I dc
For the halfwave circuit, using Eqn. (3.10), g =
Iac = Idc
Irms 2 − Idc 2 I dc g =
2
I rms = −1 = F 2 −1 Idc
(1.57)2 − 1 = 1.21
(3.11)
The ripple in the output of a halfwave rectifier is large, resulting in large variation of the dc voltage. This is one disadvantage.
Rectification Efficiency or Ratio of Rectification The effectiveness with which the given ac input power from the secondary of the transformer is converted into the desired dc output power is given by the rectification efficiency and is designated as h. h=
Pdc dc power delivered to the load = Pi ac power input from the secondaary of the transformer
112
Electronic Devices and Circuits
2
I2 I Pdc = I RL = m RL = m2 RL p p
(3.12)
2 dc
Pi = I
h=
2 rms
I (Rf + RL ) = 2m
I m2 p 2 RL Im 2
2
(Rf + RL )
=
2
(Rf + RL )
(3.13)
4 1 4 ≈ = 40.6% p 2 Rf p 2 1 + R L
(3.14)
since Rf > RL. Equation (3.40) reduces to I1( rms ) =
1 w 2 2 L Vm
(3.41)
From Eqn. (3.39), the rms component of the second harmonic I2 is I 2 ( rms ) =
2I m 3p 2
=
2Vm 3p 2
×
1
(R
2 L
+ 4w 2 L2
)
(3.42)
124
Electronic Devices and Circuits
As wL >> RL, Eqn. (3.42) reduces to I 2 ( rms ) =
2Vm
×
3p 2
Vm 1 = 2wL 3pwL 2
(3.43)
The ac component of current Iac is 2
I ac = I
+I
2 1( rms )
I ac =
2 2 ( rms )
Vm Vm = + wL 2 2 pwL3 2
2
(3.44)
Vm 1 1 0.36Vm + = wL 8 18p 2 wL
I dc =
(3.45)
I m Vm = p pRL
(3.46)
Using Eqs (3.45) and (3.46), g =
I ac 0.36Vm pRL 1.13RL = × = I dc Vm wL wL
(3.47)
Equation (3.47) shows that g is inversely proportional to L and directly proportional to RL. Hence, for g to be small, L should be large and also RL should be small. It implies that inductor filter is better used to reduce ripple when the load current is large. If
If
wL = 1, then g = 1.13 RL
(3.48)
wL = 5, then g = 0.226 RL
(3.49)
3.3.2 FullWave Rectifier with Inductor Filter A fullwave rectifier circuit with inductor filter is shown in Figure 3.16 and the waveforms in Figure 3.17. D1
L +
vs = Vmsinwt
i RL
230 V, 1 φ 50c/s Mains
Load −
vs′ = Vmsin(wt + p)
D2
Figure 3.16 Fullwave rectifier with inductor filter
Rectifiers and Filters
125
The output current of a simple fullwave rectifier shown in Figure 3.16, neglecting the third and higher harmonic terms, is given by i=
2I m 4I m − cos 2wt p 3p
(3.50)
Equation (3.50) tells that the output current has a dc component and the second harmonic; whereas the fundamental component is not present. I
L=0 L≠ 0 Im 2Im π
Idc
0
wt 2p
p
3p
∅
4p
Figure 3.17 Output current with and without L
From Figure 3.16, if Rf = 0 and the resistance associated with L is also assumed to be zero, ideally, the net resistance in the loop is RL only: ∴ Im =
Vm RL
From Eqn. (3.50), I dc =
2 I m 2Vm = p pRL
(3.51)
However, for ac components the circuit offers an impedance Z: Z = RL + j 2wL
(3.52)
since the second harmonic is present in the output: Z =
(RL )2 + (2wL )2
Therefore, Im for the ac component is Im =
Vm 2
(RL ) + (2wL )2
(3.53)
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Electronic Devices and Circuits
From Eqn. (3.50), the peak amplitude of the ac component (2nd harmonic) I2 is I2 =
4I m 3p
(3.54)
Substituting Eqn. (3.53) in Eqn. (3.54), I2 =
The rms value of I2, I2 (rms) is
4 × 3p
Vm 2
(RL ) + (2wL )2
(3.55)
I2 2 I 2 ( rms ) = I ac =
4 3p 2
Vm
×
2
(RL ) + (2wL )2
(3.56)
From Figure 3.17, it can be noted that the load current lags behind the voltage by an angle f. Ripple factor, g =
I ac 4 = × I dc 3p 2
Vm 2
(RL ) + (2wL ) g =
If 1 ( RL  X C ) and also that XC > XC at 2w. From Eqn. (3.50), the maximum amplitude of the second harmonic component is I2 and is given as follows: 4I i = 2 I m − m cos 2wt p 3p
I2 =
4I m 3p
(3.85)
Im =
Vm XL
(3.86)
But
Rectifiers and Filters
133
From Eqs (3.85) and (3.86), I ripple (rms) =
4I m 3p 2
=
2 2Vm 2 = = Vdc 3 2pX L 3X L p 3X L
(3.87)
Vripple (rms) = I ripple (rms) × X C
(3.88)
4Vm
Using Eqn. (3.87), Eqn. (3.88) reduces to Vripple (rms) = Vac =
g =
2 Vdc X C 3X L
(3.89)
Vac 2 XC 2 1 1 1 = = × × = 3 XL 3 2wC 2wL 6 2w 2 LC Vdc
g =
1.19 LC
(3.90)
where, L is in henries, C is in mF and f = 50c/s. From Eqn. (3.90), it is evident that g is independent of RL. The larger the values of L and C, the smaller the value of g.
Critical Inductance, LC From Figure 3.24, it can be seen that the current i contains a
dc component I dc. As the value of L increases, i decreases. L should be chosen so that i does not become zero. This value of inductance is called critical inductance, L C. The 4 I m 4Vm second harmonic current has a peak amplitude of = . If i is not to be zero, 3p 3pXL the negative peak of i should not fall below I dc. That is, 4Vm 3pX L
(3.91)
2Vm 4Vm ≥ pRL 3pX L
(3.92)
I dc ≥ But Idc =
2Vm pRL
from which wL ≥
L = LC ≥ L is in henries, RL is in ohms, and f = 50 Hz.
2RL 3 2RL RL = 3w 471
(3.93)
134
Electronic Devices and Circuits
One important thing to note here is that if iL is small (RL large), a large value of L is required to reduce ripple. On the contrary, if iL is large (RL small), a small value of L may be enough to reduce ripple. To satisfy these extreme requirements, a choke whose inductance decreases with increasing load current and whose inductance increases with decreasing load current may be used. Such an ironcored choke is called a swinging choke. This type of choke may typically have L = 30 H at IL = 20 mA and can have L = 5 H at IL = 200 mA.
Bleeder Resistance The output dc voltage of a FW rectifier with LC filter is shown in Figure 3.25. If in the rectifier circuit L is small, then its associated resistance is also small. The capacitor allows the output to reach Vm, which is the noload output voltage. This voltage falls to Vdc = 2Vm p at IL = IL(min) and remains the same with variation in IL. If the load is disconnected suddenly, that is RL→∞, VL jumps to Vm from Vdc, resulting in poor regulation. If a resistance RB is connected across the load such that RB ensures the minimum load current IL(min) even when the load is open, then the load voltage will remain at Vdc only, ensuring better regulation. The resistance RB is called the bleeder resistance (Figure 3.26). The calculation of RB is similar to the calculation of LC. 4Vm From Eqn. (3.91), I dc ≥ 3pX L 2V And with RL open and RB included, I dc = m . p RB Hence,
VL Vm
Vdc = 2Vm/p
O IL(min)
IL
Figure 3.25 Variation of the output voltage with load current
L
FW Rectiﬁer
lL + VL
i ic
RB −
Load RL
Figure 3.26 Bleeder resistance RB ensures IL(min)
2Vm 4Vm ≥ pRB 3pX L
(3.94)
RB = 1.5X L
(3.95)
Typically RB ≤ 471 Lmax.
HalfWave Rectifier with LC Filter A halfwave rectifier with LC filter is shown in Figure 3.27. From Eqn. (3.45) we have, 0.36Vm p 0.36p Vm 0.36p I ac = × = Vdc = wL p wL p wL
(3.96)
135
Rectifiers and Filters
D
L iL i C
vs = Vmsinwt
230 V, 1 φ 50c/s Mains
+ VL Load
iC
−
RL
Figure 3.27 Halfwave rectifier with LC filter
Using Eqn. (3.96), Vac = I ac × X C =
g =
0.36pX C × Vdc wL
Vac 1.13 1.13 11.5 = = = Vdc (wL )(wC ) w 2 LC LC
(3.97)
where f = 50c/s, L is in henries, and C is in μF.
3.4
MULTIPLE CASCADED FILTERS
When filters are cascaded, the g of the cascaded filter can be calculated.
3.4.1 Two Stages of an LC Filter Consider two stages of an LC filter as shown in Figure 3.28.
Transformer
L1
and
L2 C1
+ VL C2
FW rectiﬁer
−
Load RL
Figure 3.28 FW rectifier with twostage LC filter
From Eqn. (3.89), the ripple factor for a fullwave rectifier with LC filter is given as follows: g =
2 XC 2 X C1 × = × 3 XL 3 X L1
where g is the ripple after the first LC filter.
(3.98)
136
Electronic Devices and Circuits
The ripple factor after the second LC filter is g =
2 X C1 X C 2 3 X L1 X L 2
(3.99)
If there are nidentical LC filters, in which case L1 = L2 =… = Ln = L and C1 = C2 =… =Cn = C then g =
2 XC 3 X L
n
(3.100)
for n = 2 g =
2 1 1 0.471 1 3.03 × 2 2 = × 2 2 = 2 2 × 4 4 3 (2pf ) LC (2p × 100) L C L C
(3.101)
3.4.2 pFilter or CLC Filter Consider the filter circuit in Figure 3.29, where in a C filter is cascaded with an LC filter. The filter is called a p filter or CLC filter. The output of the C filter is the input to the LC (or Ltype) filter.
Transformer
L
and
C1
+ V¢ g (rms) C2
FW rectiﬁer
Load R − L
Figure 3.29 FW rectifier with p filter
The output of the C filter is a triangular wave that can be expressed by Fourier series (neglecting higher order components) as follows: Vo = Vdc −
I dc sin 2wt 2pfC1
(3.102)
where Vg (pp) at the second harmonic component is Vg (pp) =
I dc 2pfC1
The rms value of the second harmonic component at 2f is Vg (rms) =
Vg (pp) 2
=
I dc 2 2pfC1
=
I dc 2 = 2 I dc X C1 4pfC1
Rectifiers and Filters
The harmonic current through the inductor is = Harmonic component of voltage across C2 is Vg′(rms) =
2 I dc X C1X C 2 = XL
137
2 I dc X C1 XL
2 I dc X C1X C 2 RL × = XL RL
2Vdc X C1X C 2 X L RL
since Vdc = I dc RL gp =
Vg ′(rms) Vdc
X X 2 2 = 2 C1 C 2 = 3 = RL X L w C1C2 LRL (2pf )3 C1C2 LRL
(3.103)
If f = 100 Hz, C is in μF, L is in H, and RL is in ohms. gp =
5700 C1C2 LRL
(3.104)
3.4.3 FullWave Rectifier with CRC Filter If there is an unacceptable level of ripple in a fullwave rectifier with capacitor filter, it is also possible to reduce the ripple across the capacitor by using an additional RC filter as shown in Figure 3.30. The RC network is required to pass the dc component of voltage to the load unattenuated, but it is required to attenuate the ac component appreciably. When the capacitor is fully charged, it behaves as an open circuit for dc. The resultant circuit is shown in Figure 3.31. The circuit to calculate ac voltage across RL is shown in Figure 3.32. Vdc
Vg (rms) V′g (rms)
R Transformer and
C
+ Vdc
+ Vo C
Load RL
−
FW rectiﬁer
Figure 3.30 Cascading an RC filter with a C filter R
Vdc
+ Load Vo RL −
Figure 3.31 DC circuit from Figure 3.30
138
Electronic Devices and Circuits R
+
+
V(rms)
C
V ′(rms)
Figure 3.32 AC circuit to calculate the ac voltage across the load
From Figure 3.31, if Vdc is the dc voltage across the first capacitor, then RL Vo = Vdc R + RL
(3.105)
If Vdc = 20V, R = 100Ω, RL = 1000Ω, then the dc voltage at the output ,Vo = 18.18V. If the ac ripple voltage across the first capacitor is V(rms), from Figure 3.32, the ac voltage across the load is ′ V( rms)
At f = 100 Hz, X C =
1 XC XC = V( rms ) = V( rms ) ≈ V( rms ) R R R + XC 1+ X C
(3.106)
1 1 1.59 = = C 2pfC 2p × 100 × C
where XC is in kΩ and C is in μF.
3.5
POWER SUPPLY PERFORMANCE
The performance of a power supply depends on three important factors: (i) source effect (ii) load effect, and (iii) ripple rejection ratio. (i) Source effect: The ac input voltage to a rectifier (called power supply) does not remain constant. A change in the ac source voltage (also called the line voltage) can cause a change in the dc output voltage. The change in the dc output voltage for 10 percent change in source voltage is called source effect. Source effect = ∆Vo for a 10 percent change in Vi Another way of expressing the change in the dc output voltage due to source effect is by line regulation, which is defined as follows: Line regulation =
Source effect ´ 100% Vi
Rectifiers and Filters
139
(ii) Load effect: The dc voltage at the output of a power supply changes with load current. Vo decreases with increase in IL and increases with decrease in IL. The load effect specifies how the output dc voltage changes when IL increases from 0 to IL(max). Load effect = ∆Vo for ∆ I L ( max ) Another way of expressing the change in the dc output voltage due to load effect is by load regulation, which is defined as follows: Load regulation =
Load effect × 100% Vi
(iii) Ripple rejection ratio is defined as the ratio of the ripple voltage at the output to the ripple voltage at the input: Ripple rejection ratio =
Vg o Vg i
Additional Solved Examples Example 3.4 A halfwave rectifier with RL = 1 kΩ is given an input of 15 V peak from stepdown transformer. Calculate dc voltage and load current for ideal and silicon diodes. Solution: Given values are RL = 1 kΩ, Vm = 15 V Case (i): Ideal diode Vg = 0 V, Rf = 0 Ω Vdc =
Vm 15 = =4.78 V p p
I dc =
Vdc 4.78 = = 4.78 mA RL 1× 103
Case (ii): Silicon diode Vγ = 0.5 V Vdc = I dc =
Vm − Vg = p
15 − 0.5 = 4.62 V p
Vdc 4.62 = = 4.62 mA RL 1× 103
Example 3.5 A halfwave rectifier has a load of 5 kΩ. If the diode resistance and the secondary coil resistance together have resistance of 100 Ω and the input varies as 230 2 sin 2p × 50t , calculate the following:
140
(i) (ii) (iii) (iv)
Electronic Devices and Circuits
Peak, average, and rms values of the current dc power output dc power input Efficiency of the rectifier
Solution: RL = 5 kΩ , Rs + Rf = 100Ω Vm = 230 2 = 325.22 V (i) I m =
I dc =
I rms =
Vm 325.22 = = 63.77 mA Rs + Rf + RL 5000 + 100 I m 63.77 = = 20.31 mA p p Im
63.77 =
2
= 45.10 mA
2
(ii) Vdc = I dc RL = (20.31mA )(5 kΩ ) = 101.55 V Pdc = Vdc I dc = 101.55 ´ 20.31 mA = 2.062 W (iii) Pac = Vrms I rms = 230 ´ 45.10 mA = 10.373 W (iv) h =
Pdc 2.062 × 100 = × 100 = 19.88% Pac 10.373
Example 3.6 A 240 V(rms) , 50 Hz voltage is applied to the primary of a 20:1 stepdown centertapped transformer used in the fullwave rectifier having a load of 900Ω. If the diode resistance and the secondary coil resistance together is 100Ω, determine the following: (i) (ii) (iii) (iv) (v)
dc current flowing through the load dc voltage across the load dc power delivered to the load PIV across each diode Ripple voltage and its frequency
Solution:
N 2 2Vs ( rms ) 1 = = N1 Vp( rms ) 20
Vs (rms) =
Vp(rms) 40
=
240 = 6V 40
Rectifiers and Filters
RL = 900 Ω
141
Rs + Rf = 100 Ω
RL + Rs + Rf = 900 + 100 = 1000 Ω Im =
Vs ( max ) RL + Rs + Rf
(i) I dc =
=
6 2 = 8.484 mA 1000
2 I m 2 × 8.484 = = 5.40 mA p p
(ii) Vdc = I dc RL = 5.40 × 0.9 = 4.86 V (iii) Pdc = Vdc I dc = 4.86 × 5.40 × 10 −3 = 0.026 W (iv) PIV = 2Vs ( max ) = 2 × 2 × 6 = 16.968 V (v) Ripple factor =
Vripple( rms ) Vdc
= 0.48
Vripple( rms ) = 0.48 ×Vdc = 0.48 × 4.86 = 2.33 V Ripple frequency = 2f = 2 × 50 = 100 Hz Example 3.7 A bridge rectifier uses four identical diodes having forward resistance of 10 Ω each. Transformer secondary resistance is 10 Ω and the secondary voltage is 30 V(rms). Determine the dc output voltage for Idc = 200 mA and the value of the ripple voltage. Solution: Vs (rms) = 30V , Rs = 10 Ω, Rf = 10 Ω , Idc = 200 mA Since,
I dc =
We know that I m =
2I m p
∴ Im =
pI dc p × 200 = = 314 mA 2 2
Vs ( max ) Rs + 2Rf + RL
Rs + 2Rf + RL =
Vs (max ) Im
=
30 2 = 135.12 Ω 314
RL = 135.12 − 10 − 2 × 10 = 105.12 ≈ 105 Ω Vdc = I dc RL = 200 × 10 −3 × 105 = 21 V g=
Vg (rms) Vdc
= 0.48
∴Vg (rms) = 0.48Vdc = 0.48 × 21 = 10.08 V
142
Electronic Devices and Circuits
Example 3.8 A rectifier arrangement uses a centertapped transformer having 230–0–230 V. Determine (i) the value of RL that gives the maximum dc output power, (ii) Vdc, (iii) Idc, and (iv) PIV of each diode. Assume ideal diodes rated to handle maximum current of 600 mA. Solution: As the diodes are rated to handle a maximum current of 600 mA, for safe operation the diode current must be limited to 80 percent of this maximum value. Therefore, I m = 0.8 × 600 = 480 mA. Vs ( max ) = 2 ×230 = 325.22 V (i)
RL =
(ii)
I dc =
Vs ( max ) Im
=
325.22 = 677 Ω 480 × 10 −3
2 I m 2 × 480 = = 305.73mA p p
(iii) Vdc = I dc RL = 305.73 × 10 −3 × 677 = 206.98V (iv) PIV of each diode = 2Vs (max ) = 2 × 325.22 = 650.44 V Example 3.9 Calculate the value of L of an inductor filter used in (i) halfwave rectifier and (ii) fullwave rectifier, operating at power supply frequency of 50 Hz. It is required to derive a dc output with 5 percent ripple. RL = 500 Ω. Solution: (i) Ripple factor for halfwave rectifier with inductor filter is given as follows: g HW =
1.13RL 1.13 × 500 565 = = wL 2pfL 100pL
∴L =
565 = 35.99 H 100p × 0.05
(ii) Ripple factor for fullwave rectifier with inductor filter is given as follows: g FW =
0.236RL 0.236 × 500 118 = = wL 2pfL 100pL
∴L =
118 = 7.52 H 100p × 0.05
Example 3.10 Calculate the value of C of a capacitor filter used in (i) halfwave rectifier and (ii) fullwave rectifier, operating at power supply frequency of 50 Hz. It is required to derive a dc output with 5 percent ripple. RL = 500 Ω. Solution: (i) Ripple factor for halfwave rectifier with capacitor filter is given as follows: 1 g HW =
= 2 3 fCRL
5780 , where C is in μF and RL is in ohms. CRL
Rectifiers and Filters
143
5780 5780 C=g = = 231.2 µF HW R 0.05 × 500 L (ii) Ripple factor for fullwave rectifier with capacitor filter is given as follows: g FW =
1 = 4 3 fCRL
2890 , where C is in μF and RL is in ohms. CRL
2890 2890 C=g = = 115.6 µF FW R L 0.05 × 500 Example 3.11 A 15015 V(rms) ideal transformer is used with a fullwave rectifier circuit with diodes having forward drop of 1 V. The load has a resistance of 100 Ω and a capacitor of 1000 μF is used as a filter across the load resistance. Calculate the dc load current and the voltage. Solution: Vs ( max ) = 2Vs ( rms ) = 2 × 15 = 21.21V RL = 100 Ω, drop across the diode = Vd = 1 V, C = 1000 μF Im = I rms = I dc =
Vs ( max ) Vd RL Im 2
0.202 =
=
21.21  1 = 0.202 A 100
= 0.143 A
2
2I m 2 × 0.202 = = 0.129A p p
4 fCRL Vdc = Vs (max ) − Vd 1 + 4 fCRL 4 × 50 × 1000 × 10 −6 × 100 Vdc = 21.21 − 1 = 19.2 V 1 + 4 × 50 × 1000 × 10 −6 × 100 Example 3.12 In a fullwave rectifier using an LC filter, L = 10 H, C = 100 μF, and RL = 500 Ω. Calculate Vdc, Idc, and ripple factor for an input of vi = 100 sin (100pt). Solution: Given that vi = 100 sin(100p t) ∴Vm = 100 V Vdc =
2Vm 2 × 100 = = 63.69V p p
I dc =
Vdc 63.69 = = 127.38 mA RL 500
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Electronic Devices and Circuits
Ripple factor g =
1.19 1.19 = 1.19 × 10 −3 = LC 10 × 100
Example 3.13 A fullwave rectifier supplies a dc voltage of 200 V at 500 mA. f = 50 Hz. Calculate the transformer secondary voltage for (i) a capacitor filter using a capacitor of 100 μF. (ii) a choke input filter using a choke of 10 H and a capacitor of 100 µF. Neglect the resistance of choke. Solution: Vdc = 200 V, I dc = 500 mA, f = 50 Hz (i) Capacitor input filter with C = 100 μF 1 Vdc = Vs ( max ) − I dc 4 fC 1 Vs ( max ) = Vdc + I dc 4 fC Vs ( max ) = 200 +
500 × 10 −3 4 × 50 × 100 × 10 −6
Vs ( max ) = 200 + 25 = 225 V
Vs ( rms ) =
Vs ( max ) 2
=
225 2
= 159.12V
(ii) Choke input filter with L = 10 H, C = 100 μF, Rx = 0 Vdc =
2 Vs (max ) R × p (Rx + R )
Since, Rx = 0 Vdc = ∴ Vs (max ) =
Vs ( rms ) =
2Vs ( max ) p
p p Vdc = × 200 = 314 V 2 2
Vs ( max ) 2
=
314 2
= 222.06 V
Rectifiers and Filters
145
Example 3.14 A fullwave singlephase rectifier uses a pfilter consisting of two 1000 μF capacitances and a 20 H choke. The transformer voltage to the center tap is 300 V rms. The load current is 1000 mA. Calculate the dc output voltage and the ripple voltage. The resistance of the choke is 100 Ω. Solution: C = 1000 μF, L = 20 H, Vs ( rms ) = 300 V, Rx (resistance of the choke) = 100 Ω, I dc = 1000 mA For the capacitor filter, Vg = peaktopeak ripple voltage =
I dc 1000 × 10 −3 = 3.18 V = 2p fC 2p × 50 × 1000 × 10 −6
For a p filter, Vdc = Vs (max ) −
Vg 2
− I dc Rx
Vg Vdc = 2Vs (rms) − − I dc Rx = 300 2 − 1.59 − 1000 × 10 −3 × 100 = 322.6 V 2 RL =
Vdc 322.6 = = 322.6 Ω I dc 1000 × 10 −3
gp =
5700 5700 = = 0.000883 × 10 −3 C1C2 LRL 1000 × 1000 × 20 × 322.6
Ripple voltage = g p Vdc = 0.000883 × 10 −3 × 322.6 = 0.285mV
Example 3.15 For the fullwave rectifier with p filter (CRC filter) shown in Figure 3.30, calculate the dc and ac components of voltages across the load. Also calculate the value of g . R = 500 Ω, RL = 5 kΩ, C = 500 μF, Vdc = 100 V, and Vg (rms) = 10 V. Solution: (i) The dc voltage at the output, Vo is Vo = Vdc (ii) X C =
RL 5000 = 100 ´ = 90.91 V R + RL 500 + 5000
1.59 1.59 = = 3.18 Ω C 500
The ac ripple voltage across the load is Vg ′(rms) = Vg (rms) (iii) Ripple factor, g =
Vg ′(rms) Vo
=
XC 3.18 = 10 × = 0.0636 V R 500
0.0636 × 100 = 0.07% 90.91
146
Electronic Devices and Circuits
Example 3.16 (i) The output voltage Vo of a power supply decreases from 15 V to 14.5 V when IL increases from 0 to IL(max). Calculate load effect and load regulation. (ii) If Vo increases from 15 V to 15.5 V when Vi increases by 10 percent. Calculate line effect and line regulation. Solution: (i) Load effect = 15 − 14.5 = 0.5 V 0.5 × 100 = 3.33% Load regulation = 15 (ii) Source effect = 15.5 − 15 = 0.5 V Line regulation =
0.5 × 100 = 3.33% 15
Example 3.17 Determine the component values of CLC filter for Vdc = 15 V, I L = 300 mA and g p = 1%. Solution: RL =
gp =
Vdc 15 = = 50 Ω I L 300 × 10 −3 5700 = 0.01 C1C2 LRL
Let C1 = C2 = C Then,
5700 5700 = 0.01 Or C 2 = 0.01× LRL C 2 LRL
Choose L = 20 H. Then, C 2 = C=
5700 = 570 0.01× 20 × 50
570 = 23.88 μF.
Example 3.18 A fullwave rectifier with Ctype filter is to supply I dc = 50 mA at Vdc = 20 V . Determine (i) RL , (ii) C, and (iii) Vrms of the transformer secondary. g = 5% Solution: Given I dc = 50 mA , Vdc = 20 V and g = 5% = 0.05 (i) RL = (ii) g =
Vdc 20 = = 400 Ω I dc 50 × 10 −3 1
1 =
4 3 fCRL
Or C =
4 × 3 × 50 × C × 400 1
4 × 3 × 50 × 0.05 × 400
= 144 µF
Rectifiers and Filters
(iii) Vdc = Vm
147
4 fCRL 1 + 4 fCRL Or Vm = Vdc 1 + 4 fCRL 4 fCRL 4 fCRL = 4 × 50 × 144 × 10 −6 × 400 = 11.52 Vm = 20 ´ Vr ms =
1 + 11.52 = 21.74 V 11.52 21.74
= 15.36 V
2
Example 3.19 A 24 V peak rectified voltage of a rectifier is applied as input to a capacitor filter with C = 1000 µF . Determine the values of g and Vdc , for a load current is 500 mA and f = 50Hz (i) if the rectifier is a HW rectifier and (ii) if the rectifier is a FW rectifier. Solution: (i) For the HW rectifier, 1 Vm = Vdc + I dc 2 fC 1 500 × 10 −3 = 24 − 5 = 19 V Or Vdc = Vm − I dc = 24 − 2 × 50 × 1000 × 10 −6 2 fC RL =
Vdc 19 = = 38 Ω I L 500 × 10 −3 1
g =
= 2 3 fCRL
5780 5780 = = 0.152 CRL 1000 × 38
(ii) For the FW rectifier, 1 Vm = Vdc + I dc 4 fC 1 500 × 10 −3 Or Vdc = Vm − I dc = 24 − 2.5 = 21.5 V = 24 − 4 × 50 × 1000 × 10 −6 4 fC RL =
Vdc 21.5 = = 43 Ω I L 500 × 10 −3 1
g =
= 4 3 fCRL
2890 2890 = = 0.067 CRL 1000 × 43
148
Electronic Devices and Circuits
Example 3.20 A transformer, rectifier, and filter arrangement has a noload voltage of 100 V and its voltage regulation is specified as 5 percent. What is its fullload voltage? Solution: Voltage regulation can be also specified as follows: % regulation =
VNL −VFL ×100 VNL
V 5 = 1 − FL × 100 100
1−
VFL = 0.05 100
VFL = 1 − 0.05 = 0.95 100
∴VFL = 100 × 0.95 = 95 V
Summary • A PN junction diode can be used in many applications; one application considered here is in rectifiers. • A simple HW rectifier has a g of 1.21, which says that the ripple is large. But FW rectifier has a g of 0.48, which says that the ripple in FW rectifier is relatively small. • A bridge rectifier is used to eliminate the need for a centertapped transformer. • Filters are used to reduce the ripple in the load. • Though an inductor filter reduces the ripple appreciably, it is effective only at highload currents. • A capacitor filter also reduces the ripple appreciably, but it is effective only at lowload currents. • An LC or Ltype filter, which is a combination of L and Ctype filters, can be used to reduce ripple, and g can be made independent of load current or load resistance. • The diode used in a halfwave rectifier and in bridge rectifier should have a PIV of Vm. • The diode used in an FW rectifier should have a PIV of 2Vm. • Multiple filters such as LC or CLC filters are filters connected in tandem to effectively reduce the ripple.
multiple ChoiCe QueStionS 1. The dc and rms components of currents in a HW rectifier are given by the relations (a)
Im I and m 2 p
(b)
Im I and m p 2
(c)
2I m 2I m and p p
(d)
Im 2I m and 2p 2
2. The values of g, TUF, and h of a HW rectifier, in the same order are (a) 1.21, 0.287, and 40.6 (b) 0.48, 0.363, and 81.2 (c) 0.48, 0.363, and 40.6 (d) 1.21, 0.287, and 81.2 3. The values of g, TUF, and h of a FW rectifier, in the same order are (a) 1.21, 0.287, and 40.6 (b) 0.48, 0.693, and 81.2 (c) 0.48, 0.363, and 40.6 (d) 1.21, 0.287, and 81.2
Rectifiers and Filters
149
4. A HW rectifier circuit gives an output dc voltage of 10 V at 0 load current. When the full load of 100 mA is drawn, the output dc voltage falls to 9.5 V. The percentage regulation is (a) 50% (b) 5% (c) 2.5% (d) 55% 5. A transformer with a secondary voltage of 100 V (rms) is used in a FW rectifier circuit using a C filter. The PIV of the diode should at least be (a) 282.8 V (b) 600 V (c) 110 V (d) 141.4 V 6. The ripple in a rectifier circuit using an inductor filter (a) increases with increasing load current (b) decreases with increasing load current (c) remains unaltered with variations in load current (d) None of the above 7. The ripple in a rectifier circuit employing a capacitor filter (a) increases with increasing load current (b) decreases with decreasing load current (c) remains unaltered with variations in load current (d) None of the above 8. The ripple in a rectifier circuit employing an LC filter (a) increases with increasing load current (b) decreases with increasing load current (c) remains unaltered with variations in load current (d) None of the above 9. A bleeder resistance RB is used in association with an LC filter, to ensure (a) good regulation (b) poor regulation (c) 50% regulation (d) 100% regulation 10. Multiple Lsection filters are used to (a) make g as small as possible (b) make g as large as possible (c) to reduce the output dc voltage (d) None of the above 11. The minimum frequency of the ripple component present in the output of HW and FW rectifiers, in same order, are (a) 50c/s and 50c/s (b) 50c/s and 100c/s (c) 100c/s and 100c/s (d) 100 and 50c/s
Short anSwer QueStionS 1. List three main limitations of a halfwave rectifier. 2. What are the advantages of FW rectifier over a HW rectifier? 3. What is the PIV of a diode in a rectifier circuit? What is its value in a HW rectifier, FW rectifier, and bridge rectifier? 4. What are the values of g for a HW rectifier and FW rectifier without filter? 5. What is ripple in a rectifier? Explain a simple method to minimize the ripple.
150 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.
Electronic Devices and Circuits
What is meant by transformer utilization factor? What is form factor? What is meant by diode stacking? Name two main advantages of the bridge rectifier over the conventional FW rectifier. What is its disadvantage? Justify that an inductor filter is better used to reduce ripple when the load current is large. Justify that capacitor filter is better used to reduce ripple when the load current is small. What is the advantage of an LC filter when compared to simple L and C filters? What is a critical inductance? What is a bleeder resistance? Why are multiple filters used?
long anSwer QueStionS For a HW rectifier, derive the expressions for Idc, Irms, Pi, Pdc, h, TUF, and g. For a FW rectifier, derive the expressions for Idc, Irms, Pi, Pdc, h, TUF, and g. For a FW bridge rectifier, derive the expressions for Idc, Irms, Pi, Pdc, h, TUF, and g. Derive the expression for g of HW rectifier with inductor filter. Draw the waveforms. Derive the expression for g of FW rectifier with inductor filter. Draw the waveforms. Derive the expression for g of HW rectifier with capacitor filter. Draw the waveforms. Derive the expression for g of FW rectifier with capacitor filter. Draw the waveforms. Draw the circuit of a FW rectifier with LC filter and explain its working. Calculate its g . What is meant by critical inductance? Why is a bleeder resistance used in the circuit? 9. Explain the need to cascade filters. Draw the circuit of an FW rectifier using two cascaded sections of LC filters and calculate its ripple factor. 10. Write short notes on (a) line and load regulation in a power supply (b) PIV of diodes used in HW and FW rectifier circuits 1. 2. 3. 4. 5. 6. 7. 8.
unSolved problemS 1. A centertapped transformer having 1000100 V (rms) is used in a fullwave rectifier. The diode has a resistance of 10 Ω and the load resistance is 90 Ω. Calculate (i) Im, (ii) Idc, (iii) Idc through each diode, (iv) Pdc, (v) h, (vi) % regulation, and (vii) PIV of each diode. 2. A transformer having a secondary voltage of 100 V(rms) is used in a fullwave bridge rectifier. The diode has a resistance of 10 Ω and the load resistance is 90 Ω. Calculate (i) Im, (ii) Idc, (iii) Idc through each diode, (iv) Pdc, (v) h, (vi) % regulation, and (vii) PIV of each diode. 3. A FW rectifier with a capacitor filter having C = 50 µF, has a peak output voltage of 50 V and RL = 1 kΩ. Find (a) I dc ,(b) Vdc , (c) ripple voltage, and (d) g. The supply frequency is 50 Hz. 4. A FW rectifier with C filter delivers a current of 100 mA at 50 V. f = 50 Hz and C = 50 μF. Find (a) the peak secondary voltage of the transformer and (b) g. 5. A FW rectifier with Ctype filter supplies a dc current of 50 mA at 25 V. The supply frequency is 50 Hz. Allowed ripple is 10 percent. Calculate C. 6. Determine the component values of CLC filter for Vdc = 20 V, I L = 500 mA, and g p = 2%.
4
TRANSISTOR CHARACTERISTICS
Learning objectives After reading this chapter, the reader will be able to
4.1
Understand the working bipolar junction transistors (BJTs) Appreciate the methods of biasing BJTs Realize the three basic configurations of BJTs, namely, CE, CB, and CC configurations and obtain the input and output characteristics Derive the expressions for the current gain in each of the configurations and obtain their interrelationship Derive the analytical expressions to explain the output characteristic in the CE configuration, using the Ebers–Moll model Understand the working of a phototransistor
JUNCTION TRANSISTOR
A bipolar junction transistor (BJT) that is commonly known as transistor is a threeterminal device. These three terminals are identified as emitter, base, and collector. The basic construction of NPN and PNP transistors is shown in Figure 4.1, and their schematic representations are shown in Figure 4.2. Emitter, E
N
P
Collector, C
N
Emitter, E
P
Base, B
N
P
Collector, C
Base, B
Figure 4.1 The NPN and PNP transistors
E
C
B
E
C
B
Figure 4.2 Schematic representation of NPN and PNP transistors
A transistor has an emitter, E, base, B, and a collector C. Base is made very thin and the collector is the largest region. The emitter is highly doped from which charge carriers are injected into the base. The charge carriers are aided by the external field, and later they could diffuse into the
152
Electronic Devices and Circuits
collector region, constituting the current in the device. As can be seen from Figure 4.1, transistors are of two types: NPN transistors and PNP transistors. From the construction, it can be noted that the transistor consists of two PN junctions, which can be represented as two diodes, with anodes as common terminal, for NPN transistor and the cathodes as common terminal for a PNP transistor as shown in Figure 4.3. D1 K
D2
D1 A
A
D2 A
K
K E
C
E
C
B
B
NPN transistor
PNP transistor
Figure 4.3 Diode representation of transistors
Consider an NPN transistor. Let us assume JC basecollector junction JEemitterbase junction that the emitter and the collector regions have identical physical dimensions and Base doping concentration. Then, the transistor Nmaterial is said to have symmetrical junctions. When no external voltage is applied, as the electron Emitter Collector Pmaterial density is very high in the Ntype emitter, Pmaterial these majority charge carriers from the JC JE emitter diffuse into the Ptype base and holes from the Ptype base diffuse into the Ntype emitter. The net result is concentration of Barrier potential electrons on the Pside of the junction and concentration of holes on the Nside of the Figure 4.4 Potential distribution in an unbiased transistor junction, which prevents further migration of electrons and holes to either side of the junction. There exist barrier potentials, whose height is the same at the base–emitter junction, JE, and base–collector junction, JC, as shown in Figure 4.4. The minority carrier concentration in the opencircuited PNP transistor is shown in Figure 4.5. The barrier potential, also called cutin voltage, Vg , is typically 0.1 V for Ge and 0.5 V for Si. npo–minority carrier (electron) concentration in the Ptype emitter and collector at equilibrium pno–minority carrier (hole) concentration in the Ntype base at equilibrium Minority carrier concentration pno npo
npo
Ntype base
Ptype emitter
Ptype collector JE
JC
Figure 4.5 Minority carrier concentration in an opencircuited PNP transistor at equilibrium
Transistor Characteristics
153
For the current to flow in the device (for the device to conduct or to be in the ON state), the base–emitter diode (called the emitter diode) is to be forward biased by a voltage more than Vg , and the base–collector diode (called the collector diode) is reverse biased, in which case the transistor is said to be in the active region, as depicted in Figure 4.6.
IE P
N
P
+
C
E
IC
IE
IC
B
VEB
IB −
VEB
IB VCB
RL
VO −
−
VEB
VCB
+
+
VCC
Figure 4.6 Biasing a PNP transistor in the active region
Let VEB be the forwardbias voltage applied between the base and emitter terminals, and let Vg be the barrier potential. By the application of the forwardbias voltage, the height of the barrier at JE is reduced to Vg −  VEB  . LetVCC be the reversebias voltage applied to the collector diode. The voltage across the collector and base terminals isVCB . The collector junction barrier voltage as a result of the reversebias voltageVCB . is Vg +  VCB  , as shown in Figure 4.7, which increases the potential barrier. The dotted line depicts the situation as shown in Figure 4.5.
V
Base width, WB Ntype base
Ptype emitter
Vg − VEB Vg
VEB JE Vg + VCB Emitter junction barrier
VCB
Ptype collector JC Collector junction barrier
Figure 4.7 Potential variation at the junctions in a PNP transistor biased in the active region
154
Electronic Devices and Circuits
As a result of the application of the forwardbias voltage, the height of the barrier at JE is reduced to Vg −  VEB  , which facilitates injection of holes from Ptype emitter into the Ntype base. The holes in the base region are the minority carriers. The concentration of these holes in the Ntype base, pn is the maximum near the junction and their concentration decreases away from the junction (Figure 4.8). Similarly, electrons from the Ntype base are injected into the Ptype emitter, which are now minority carriers in the emitter. Once again, it can be noted that the concentration of these electrons in the Ptype emitter, np is the maximum near the junction, and their concentration decreases away from the junction. The excess holes in the base region diffuse to the collector junction. As the electric field intensity at JC is large ( = ( −dV ) / dx >> 0 ) , the holes are accelerated across the junction, and are therefore collected by the collector. Since the collector junction is reverse biased, the electron concentration np increases away from the junction, JC. The dotted lines depict the situation in an unbiased transistor as shown in Figure 4.5. Minority carrier concentration
pn
np pno
np
npo
npo
WB Ptype emitter
JE
Ntype base
JC
Ptype collector
Figure 4.8 Minority carrier concentration in a PNP transistor biased in the active region
4.2 TRANSISTOR CURRENT COMPONENTS The current components in a PNP transistor biased in the active region are shown in Figure 4.9. As the base–emitter junction is forward biased, holes from the Ptype emitter are injected into the Ntype base. This component of emitter current is called IpE. Similarly, electrons from the Ntype base are injected into the Ptype emitter. This component of emitter current is called InE. Therefore, the total emitter current IE is I E = I pE + I nE
(4.1)
But in a commercial transistor, the emitter is heavily doped when compared to the base. Therefore, I nE I B( min ) Hence, the transistor is in saturation.
192
Electronic Devices and Circuits
Summary • A transistor is said to be in the active region (class A operation), when the base–emitter diode is forward biased and the base–collector diode is reverse biased. • A transistor is said to be in the saturation region (ON switch), when the base–emitter as well as the base–collector diodes are forward biased. • A transistor is said to be in the cutoff region (OFF switch), when the base–emitter as well as the base– collector diodes are reverse biased. a h • The current gain in CB configuration is a ( = hFB ) , that in the CE configuration is b hFE = = FB 1 − a 1 − hFB and in the CE configuration is g = (1 + hFE ) . • The leakage current, ICEO in CE configuration is (1 + b dc ) times larger than the leakage current, ICO in CB configuration. Further, ICO gets doubled for every 10°C rise in temperature • The base width decreases with increasing reversebias voltage, VCB at the collector junction. This effect is called base width modulation or Early Effect. • The effective base width W ′ practically reduces to zero, when the reversebias voltage on the collector diode is increased beyond a limit. At this, the collector voltage now can be seen to have reached through the base region, resulting in the emitter barrier voltage to be reduced from Vg to V ′ This phenomenon is called reach through or punch through. • The Ebers–Moll equivalent circuit of the transistor analytically explains the characteristics of the transistor in the CE mode.
multiple ChoiCe Questions 1. When forward–forward bias is provided in a transistor, then the transistor is said to be in (a) active region (b) saturation region (c) cutoff region (d) none of these 2. When forward–reverse bias is provided in a transistor, then the transistor is said to be in (a) active region (b) saturation region (c) cutoff region (d) none of these 3. When reverse–reverse bias is provided in a transistor, then the transistor is said to be in (a) active region (b) saturation region (c) cutoff region (d) none of these 4. The current gain in the CB configuration in terms of the current gain in the CE configuration is given by (a) hFB = (c)
hFE 1 + hFE
1 + hFE hFE
5. The current gain in the CE configuration is given by h (a) hFE = FB 1 + hFB (c)
1 + hFB hFB
(b) hFB = (d)
1 − hFE hFE
(b) hFE = (d)
hFE 1 − hFE
hFB 1 − hFB
1 − hFB hFB
Transistor Characteristics
6. The current gain in the CC configuration is given by (a) hFC = 1 + hFE (c) hFC = 1 − hFB
193
(b) hFC = 1 + hFB (d) hFC = 1 − hFE
7. The current gain in the CB configuration is 0.98. Then, the current gain in the CE configuration is (a) 149 (b) 49 (c) 100 (d) 9.8 8. The current gain in the CE configuration is 50. The, the current gain in the CB configuration is (a) 98 (b) 0.98 (c) 100 (d) 9.8 9. The current gain in the CE configuration is 49. Then, the current gain in the CC configuration is (a) 149 (b) 150 (c) 50 (d) 0.49 10. The current gain in the CB configuration is 0.99. Then, the current gain in the CC configuration is (a) 100 (b) 50 (c) 49 (d) 9.9 11. If I CO = 2µA, I EO = 1.62 µA , and a N = 0.99 , then a I is (a) 0.99 (c) 1.99
(b) 0.8 (d) 99
12. The base width decreases with increasing reversebias voltage, VCB at the collector junction. This effect is called (a) avalanche multiplication (b) reach through (c) Early effect (d) none of these 13. The effective base width W ′ reduces to zero, when the reversebias voltage on the collector diode is increased beyond a limit. This phenomenon is called (a) go through (b) avalanche multiplication (c) punch through (d) none of these 14. If VCB = 40,VCBO (max) = 50 , then M n for n = 2 is (a) 2.78 (c) 0.278
(b) 27.8 (d) 278
15. If VCBO (max) = 50 V, b dc = 50 , and n = 2 , then VCEO(max) is (a) 7.07 V (b) 1.88 V (c) 188 V (d) 0.188 V
Short answer Questions 1. 2. 3. 4. 5. 6. 7. 8.
A transistor is called a bipolar device. Why? Why is the base made very thin? When is a transistor said to be in the active region? A transistor is a currentcontrolled device. Justify the statement. Why is a Silicon transistor preferred over a Germanium transistor? What are the three basic transistor configurations? What is a dc ? What is b dc ?
194
9. 10. 11. 12. 13. 14. 15. 16.
Electronic Devices and Circuits
Specify the interrelationship between a dc and b dc . Of the three transistor configurations, which configuration has the maximum current gain? What are the two mechanisms by which breakdown may occur in a transistor? What is reach through or punch through in a transistor? How does current increase in the transistor when breakdown occurs due to avalanche multiplication? What is meant by the operating point in a transistor circuit? What is thermal runaway? What is Early effect or base width modulation?
Long answer Questions 1. What are the three basic configurations of a transistor? Describe the procedure to plot the input and output characteristics of transistor in CE mode. Clearly indicate active, saturation, and cutoff regions on the output curves. 2. Obtain the interrelationship between the current gains in the three basic transistor configurations. 3. Draw the equivalent circuit of the transistor in terms of Ebers–Moll parameters and explain with the help of relevant relations the analytical procedure to plot the output characteristics of an NPN transistor. 4. Write short notes on (a) Early effect (b) reach through 5. Explain the principle of working of a phototransistor.
unsolved problems 1. For Germanium transistor, b dc = 50, I CO = I CBO = 5 µA and I B = 100 µA . Calculate a dc , I C , and IE. 2. A transistor has IE = 10 mA, adc = 0.99, ICO = 5 µA. Determine IC, IB bdc and ICEO. 3. For the Si transistor in Figure 4.48, the reverse saturation current is 0.5 µA at 25°C. VBB = 10 V. Determine the value of RB for the transistor to be OFF at 100°C. 4. In the circuit shown in Figure 4.45, Si transistor is used with VCC = 12 V, RC = 1 kΩ, RB = 500 kΩ, and VCE = 8 V. Determine the transistor currents and VCB. 5. In a CE configuration, VCC = 9V and when a resistance RC of 1 kΩ is connected in series with the collector to VCC, it is found that the drop RC across RC is 3 V. If a dc = 0.98 , find (i) VCE and ICO (ii) I B . 6. In a CE circuit, VCC = 10 V, RC = 1 kW. When + RB the transistor is OFF, its collector current is VBE − 100 nA, and when the transistor is ON and in VBB VCE saturation, VCE = 0.2 V. Determine the power 10 V dissipation PD (i) when the transistor is in saturation, (ii) when the transistor is OFF, and Figure 4.48 Circuit for Problem 3 (iii) when VCE = 5 V.
5
TRANSISTOR BIASING AND THERMAL STABILIZATION
Learning objectives After reading this chapter, the reader will be able to
5.1
Understand the relevance of the transistor characteristics on the biasing of a bipolar junction transistor Realize the three basic configurations of BJTs, namely, CE, CB, and CC configurations Understand the various methods of biasing transistors, namely, fixed bias, selfbias, voltage divider bias, and collector feedback bias Appreciate the need for bias stabilization
INTRODUCTION
A transistor can be used as a switch, or it can also be used either as a linear or as a nonlinear circuit element. To accomplish this, it becomes necessary to set the dc conditions in the circuit. Establishing the relevant dc conditions in the circuit is called biasing. Whenever a transistor is to be used for any application, three major parameters are to be borne in mind: (i) the maximum permissible collector current, IC(max), (ii) the maximum VCE, and (iii) the dissipation in the device, PD(max).
5.2 THE THREE METHODS OF BIASING A TRANSISTOR Basically, a transistor can be either used as a switch or as a linear or nonlinear circuit element. There are three methods of biasing a transistor, and they are explained below.
5.2.1 Forward–Forward Biasing This means both the emitter and the collector diodes are forward biased, in which case the transistor is said to be in saturation. For all practical purposes, VCE = 0. Then, the resistance between the collector and the emitter terminals is ideally zero. We may consider the transistor as a closed switch or ON switch (Figure 5.1). As VBE = 0.7 V, the emitter diode is forward biased. In addition, the base is positive with respect to the collector by 0.5 V. Hence, the collector diode is also forward biased.
196
Electronic Devices and Circuits
IC(sat) E
N
P
+
C
N
IB
VCE = 0.2 V
B
+ RB
VBB
VCC
RL
− −
VBE = 0.7 V
IE VCC
VBB
Figure 5.1 Forward–forward bias
5.2.2 Reverse–Reverse Biasing This means that both the emitter and the collector diodes are reverse biased, in which case the transistor is said to be in the OFF state, that is, IC = 0. Since IC ≈ 0, for all practical purposes VCE = VCC, the supply voltage. Then, the resistance between the collector and emitter terminals is ideally infinity. We may consider the transistor as an open switch or OFF switch (Figure 5.2). As VBE is negative, the emitter diode is reverse biased. Since VCB is positive, the collector diode is also reverse biased. IC = 0
VBE > IB
G
Figure 5.14 Emitter bias circuit
VCC = IBRB + VBE + ICRE
VCC − VBE − I C RE 15 − 0.6 − 0.1 × 103 × 12.5 × 10 −3 = = 52.6 kΩ ≈ 50 kΩ IB 0.25 × 10 −3
RB = Calculation of S: Here,
RB 50 = = 500 RE 0.1 Using Eqn. (5.20), S=
(1 + b dc ) (1 + 50) = 51 = 51 = 46.36 = 1 1 + 50 1 + 0.1 1 + 50 1 1 + 500 501 1 + b dc 1 + RB RE
We see that without RE, S = 51 and with RE of 0.1kΩ, S = 46.36. The poor value of S is because RB = 500 , which is very large. RE Let us calculate S for (i)
RB = 0, S = 1 RE
RB varying from 0 to 1000: RE
Transistor Biasing and Thermal Stabilization
RB = 1, S = (ii) RE
(iii)
207
51 =2 50 1+ 1+1
RB 51 = 10, S = = 9.197 50 RE 1+ 1 + 10
(iv)
RB = 25, S = RE
51 = 17.45 50 1+ 1 + 25
(v)
RB = 50, S = RE
51 = 25.75 50 1+ 1 + 50
(vi)
RB = 100, S = RE
51 = 34.11 50 1+ 1 + 100
(vii)
RB = 250, S = RE
51 = 42.53 50 1+ 1 + 250
(viii)
RB = 500, S = RE
51 = 46.36 50 1+ 1 + 500
(ix)
RB = 750, S = RE
51 = 47.84 50 1+ 1 + 750
(x)
RB = 1000, S = RE
(xi) As
51 = 48.57 50 1+ 1 + 1000
RB increases further, S → (b + 1) = 51 RE
RB is small (Figure 5.15). RE Keeping RB constant, if RE is increased, to set the same Qpoint, VCC needs to be increased, which From the above calculations, it is obvious that S is small when
is unwarranted.
208
Electronic Devices and Circuits S
51 48.57 47.84 46.36 42.53 34.11 25.75 17.45 9.2 1
S = 51
RB/RE
0 1 10 25 50 100 250 500 750 1000
Figure 5.15 Variation of S with
RB RE
Calculation of S′: From Eqn. (5.6), S′ =
dI C , I , b constant. dVBE CO dc
And from Eqn. (5.18), VCC = I B ( RB + RE ) + VBE + I C RE
(5.22)
And also from Eqn. (5.3), IC = bdc IB + ICO (1 + bdc) From Eqn. (5.3), IB =
I C − I CO (1 + bdc )
(5.23)
bdc
Substituting Eqn. (5.23) in Eqn. (5.22) and after simplification, ( R + RE ) ( R + RE ) (1 + bdc ) VCC = B + RE I C − B I CO + VBE bdc bdc Therefore, VBE = VCC +
( RB + RE ) (1 + bdc ) bdc
I CO −
Assuming ICO and bdc to be constant, from Eqn. (5.24), R + RE (1 + bdc ) dVBE =− B dI C bdc
RB + RE (1 + bdc ) bdc
IC
(5.24)
Transistor Biasing and Thermal Stabilization
209
Therefore, S′ =
bdc dI C =− RB + (1 + bdc ) RE dVBE
(5.25)
But from Eqn. (5.20), S=
( RB + RE ) (1 + bdc ) RB + (1 + bdc ) RE
Multiplying and dividing Eqn. (5.25) by ( RB + RE ) (1 + bdc ) and using Eqn. (5.20),
S′ = −
(RB + RE ) (1 + bdc ) bdc × RB + (1 + bdc ) RE (RB + RE ) (1 + bdc ) S′ =
S′ =
If
− bdc S (RB + RE ) (1 + bdc ) − bdc S R (1 + bdc ) 1 + RB RE E
(5.26)
RB > 1. S′ can be minimized either by choosing RB or RE large and RB is chosen on base current requirement. Calculation of S″: From Eqn. (5.24), ∴VBE = VCC +
( RB + RE ) (1 + bdc ) bdc
I CO −
RB + RE (1 + bdc ) bdc
IC
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Electronic Devices and Circuits
Let V1 =
( RB + RE ) (1 + bdc ) bdc
I CO = ( RB + RE ) I CO
since
(1 + bdc ) bdc
≈1
Hence,
VBE = VCC + V1 −
IC =
RB + RE (1 + bdc ) bdc
IC
bdc (VCC + V1 −VBE ) RB + RE (1 + bdc )
(5.29)
Keeping VBE and ICO constant, S ′′ =
dI C RB + RE (1 + bdc ) (VCC + V1 − VBE ) − bdc (VCC + V1 − VBE ) RE = 2 db RB + RE (1 + bdc )
Using Eqn. 5.29, S′′ =
(VCC +V1 −VBE ) ( RB + RE ) I C ( RB + RE ) = × 2 bdc RB + RE (1 + bdc ) RB + RE (1 + bdc )
Multiplying and dividing by (1+ bdc ),
S ′′ =
(1 + bdc ) (RB + RE ) IC × bdc (1 + bdc ) RB + RE (1 + bdc )
But,
S ′′ =
S=
( RB + RE ) (1 + bdc ) RB + (1 + bdc ) RE
S ′′ =
ICS bdc1 (1 + bdc 2 )
I C1S where bdc1 and bdc2 are the values of bdc at two different temperatures. bdc1 (1 + bdc 2 )
(5.30)
Transistor Biasing and Thermal Stabilization
211
5.4.3 CollectortoBase Bias or Collector Feedback Bias The CE configuration with collectortobase bias is shown in VCC Figure 5.16. In this circuit too, the feedback is provided from collector IB + IC RL to base. As a result, this arrangement should give better RB thermal stability when compared to simple fixed bias + arrangement. Stability of operating point means ICQ and VCEQ IB VCE should remain unaltered with temperature variations. In this + arrangement, if the temperature increases, IC increases and the − − drop across RL increases, which will result in reduced VCE. As VBE V −VBE VCE I B = CE ≈ , decreases. As IB decreases, IC decreases, RB RB G thereby reducing the drop across RL. VCE is brought back to the Figure 5.16 CE configuration with desired value, ensuring the stability of the operating point. On collectortobase bias the other hand, if the device is replaced by another device, which has a slightly smaller value of bdc (= hFE), IC decreases, resulting in increase in VCE. This in turn increases IB, and hence IC. The drop across RL now increases, once again bringing back IC and VCE to the desired values. Using Figure 5.16 and writing the KVL equation, VCC = ( I B + I C ) RL + I B RB + VBE
(5.31)
From Eqn. (5.31), IB =
VCC −VBE − I C RL RB + RL
(5.32)
dI B RL =− RB + RL dI C
(5.33)
We have from Eqn. (5.10),
(1 + bdc )
S=
1 − bdc
(5.34)
dI B dI C
Substituting Eqn. (5.33) in Eqn. (5.34), S=
If
(1 + bdc ) RL 1 + bdc RB + RL
=
(1 + bdc ) 1 1 + bdc 1 + RB R L
RB R is small, S is small. If B becomes large, S approaches (1 + bdc). RL RL
(5.35)
212
Electronic Devices and Circuits
Example 5.3 In the collectortobase bias circuit shown in Figure 5.16, Si transistor is used. VCC = 10 V, VCEQ = 5 V, and ICQ = 2 mA. If bdc = 80, (i) calculate the values of RL, RB, and S; and (ii) if in the above circuit, all other values remain unaltered, except for bdc which now changes to 40 when this transistor is replaced by another, find out the new operating point. Solution: (i) From Figure 5.16, RL =
VCC − VCEQ I CQ
I BQ =
I CQ b dc
=
=
10 − 5 = 2.5 kΩ 2
2 = 0.025 mA 80
We have from Eqn. (5.31),
(
)
VCC = I BQ + I CQ RL + I BQ RB + VBE IBQ (RL + RB) = VCC − VBE − ICQRL
(RL + RB ) =
VCC − VBE − I CQ RL I BQ
=
10 − 0.6 − 5 4.4 = = 176 kΩ 0.025 0.025
RB = (RL + RB)−RL = 176 − 2.5=173.5 kΩ. From Eqn. (5.35),
S=
(1 + b dc ) 1 1 + b dc 1 + RB RL
=
81 1 + 80 = = 37.92 1 + 1.136 1 1 + 80 173.5 1 + 2.5
(ii) Equation (5.31) can be written as follows: I VCC = I B 1 + C RL + I B RB + VBE IB
VCC = IB(1 + bdc) RL + IBRB + VBE IB =
VCC − VBE 10 − 0.6 9.4 = = 0.034 mA = RB + (1 + b dc ) RL 173.5 + 41 × 2.5 276
Transistor Biasing and Thermal Stabilization
213
IC = bdc IB = 40 × 0.034 = 1.362 mA. VCE = VCC − (IC + IB)RL = 10 − (1.362 + 0.034)2.5 =10 − 3.49 = 6.51 V. The collectortobase bias circuit, when used in an amplifier, would produce negative feedback under ac conditions too, thereby reducing the output. This could be major limitation of this circuit.
5.4.4 Voltage Divider Bias or SelfBias If in a biasing circuit, a potential divider network comprising R1 and R2 is incorporated so as to eliminate the need for a second source, and a resistance RE is included in the emitter lead to the ground terminal, the resulting biasing arrangement is called a voltage divider bias or selfbias (Figure 5.17). VCC
VCC
IC
R1
IB
+
VCE +
+ VBE R2
−
VBE
Vth
IB
+
IB
Rth
VCE
−
RL
IC
RL
−
−
IB
IC
IC RE
RE
G G (a)
(b)
Figure 5.17 Voltage divider bias
The potential divider network derives the necessary forwardbias voltage between the base and the emitter terminals. Thevenizing the circuit in Figure 5.17(a) results in the circuit in Figure 5.17(b). Vth = VCC
R2 R1 + R2
and Rth = R1  R2 =
R1R2 R1 + R2
(5.36)
From the circuit in Figure 5.17(b), Vth = I B Rth + ( I B + I C ) RE + VBE
(5.37)
214
Electronic Devices and Circuits
Vth =
IC I Rth + C RE + I C RE + VBE bdc bdc
IC Rth + (1 + bdc ) RE = Vth − VBE bdc
IC =
(Vth −VBE ) bdc Rth + (1 + bdc ) RE
(5.38)
And VCE ≈ VCC − I C ( RL + RE )
(5.39)
since IB is small. From Eqn. (5.37), I B ( Rth + RE ) + I C RE = Vth −VBE
dI B RE =− Rth + RE dI C
(5.40)
Substituting Eqn. (5.40) in Eqn. (5.10),
S=
If
(1 + bdc ) RE 1 + b dc Rth + RE
=
(1 + bdc )
(5.41)
1 1 + b dc Rth + 1 R E
Rth R >1. If in Eqn. (5.42),
RE = 1 , then Rth
Rth
Since, IC is independent of hFE, the Qpoint is stable. If RB is decreased, then the effective input resistance decreases, A smaller input resistance loads the generator and in turn reduces the gain, when used as an amplifier. Alternatively, if RE is increased, the voltage drop across it increases, thereby increasing the feedback signal, and this in turn reduces the gain. To overcome this problem, a large capacitor, CE (typically of the order of 100 µF) which ideally behaves as a short circuit at the lowest frequeny of operation (say, 50 c/s) is connected in shunt with RE as shown in Figure 5.18. VCC
IC RL R1
+ IB VCE
+ VBE
−
−
+ V2
R2
IB
IC
+ CE
− RE
−
G
Figure 5.18 CE connected in shunt with RE
Example 5.4 In the voltage divider bias circuit shown in Figure 5.17, Si trannsistor with hFB = 0.99 is used. VCC = 20 V, RE = 1.5 kΩ, RC = 2 kΩ, R1 = 50 kΩ, R2 = 20 kΩ, VC = 0.7 V, and VCE(sat) = 0.2 V. (i) Determine the coordinates of the Qpoint and (ii) calculate the stability factor, S.
216
Electronic Devices and Circuits
Solution: Given hFB = 0.99. Therefore, hFE =
hFB 0.99 = = 99 1 − hFB 1 − 0.99
From Figure 5.17, (i) Vth = VCC
R2 20 = 20 × = 5.71 V R1 + R2 20 + 50
Rth = R1  R2 =
20 × 50 = = 14.28 kΩ 20 + 50
The circuit in Figure 5.17 is redrawn as in Figure 5.19. VCC 20 V
RC = 2
IC Rth = 14.28
IB +
VBE−
Vth = 5.71 V
+ VCE −
IC IB RE = 1.5
Figure 5.19 Redrawn circuit of Figure 5.17 with component values as given in Example 5.4
From Figure 5.19, writing the KVL equation of the base loop, Vth = IBRth + VBE + (IB + IC)RE =
IC 1 Rth + I C 1 + hFE h FE
Rth (1 + hFE ) + RE RE + VBE = VBE + I C hFE hFE
14.28 100 × 1.5 5.01 ∴ 5.71 = 0.7 + I C + = 3.02 mA and I C = 99 99 1.659 IE = IB + IC ≈ IC since IB is small. VCE = VCC − IC(RC + RE) = 20 − 3.02(2 + 1.5) = 9.43 V Therefore, the coordinates of the Qpoint are IC = 3.02 mA and VCE = 9.43 V
Transistor Biasing and Thermal Stabilization
217
(ii) Stability factor, S: From Eqn. (5.41), S=
(1 + bdc ) 1 1 + bdc Rth + 1 R E
(1 + 99 )
=
1 1 + 99 1 + 14.28 1.5
= 9.6
Example 5.5 Design the voltage divider bias circuit shown in Figure 5.17, to have VCE = 15 V and IC = 5 mA, given that VCC = 30 V, VBE = 0.7 V, hFE = 50, RC = 2 kΩ, and S ≤ 5. Solution: (i) To calculate RE: From Figure 5.17, VCC =VCE + IC(RC + RE) IC(RC + RE) = VCC − VCE = 30−15 = 15 V (RC + RE) =
15 = 3 kΩ 5
RE = (RC + RE) − RC = 3−2 = 1 kΩ
(ii) To calculate R1 and R2: Given S ≤ 5. We have S =
∴S =
1 + hFE RE 1+ RE + Rth
hFE
where Rth = R1 / / R2
1 + 50 1 1 + 50 1 + Rth
Hence, 5=
51(1 + Rth ) 51 + Rth
46 Rth = 204 Rth = 4.43 kΩ Normally, from experience, R2 is chosen as R2 ≤ 0.1 hFE RE = 0.1 × 50 × 1 = 5 kΩ Rth =
R1R2 R1 + R2
4.43 =
5R1 R1 + 5
R1 =
22.15 = 38.85 kΩ 0.57
218
Electronic Devices and Circuits
Example 5.6 For the voltage divider bias circuit shown in Figure 5.20, determine the values of RE, R1, R2, and RC, if the Qpoint is to be loacted at IC = 5 mA, VCE = 12 V, and hFE = 50. Silicon transistor is used. Solution: (i) Calculation of RE: In the design, the approximation made is that VE =
VCC = 30 V
VCC 30 = =3 V 10 10 IC = 5 mV
RL
Given IC = 5 mA = IE R1
V 3 ∴ RE = E = = 600 Ω IE 5
+ IB VCE = 12 V
VB +
+
(ii) Calculation of RL:
VBE R2
V − VCE − VE 30 − 12 − 3 15 RL = CC = = = 3 kΩ IC 5 5
(iii) Calculation of R2: The approximation acceptable to calculate R2 is
IB
−
−
IC
+ VE
−
RE − G
Figure 5.20 Biasing circuit of Example 5.6
R2 ≤ 0.1 hFE RE R2 = 0.1 × 50 × 600 = 3 kΩ (iv) Calculation of R1: VB = VCC
R2 (R1 + R2 )
We have VB = VE + VBE = 3 + 0.7 = 3.7 V
∴ 3.7 = 30 ×
3 R1 + 3
Choose R1 = 22 kΩ.
⇒
3.7 R1 = 78.9
⇒
R1 =
78.9 = 21.32 kΩ 3.7
Transistor Biasing and Thermal Stabilization
5.5
219
CB CONFIGURATION
The biasing of CB configuration using NPN and PNP devices is shown in Figures 5.21 and 5.22, respectively. +
+
IE
VEB −
RE
−
IC
VCB RC
VCC
VEE
Figure 5.21 Biasing an NPN transistor in CB
IE
IC
+
+ VEB
RE
VEE
−
−
VCB RC
VCC
Figure 5.22 Biasing a PNP transistor in CB
From Figures 5.21 and 5.22, it can be seen that the polarities of the supply voltages are exactly opposite, and also the directions of the currents. Except for this fact, the analysis of a PNP transistor circuit is precisely the same as the analysis of an NPN transistor. The output characteristics are shown in Figure 5.23. From Figure 5.23, it is evident that the collector current almost remains constant with variation of VCB. To locate the Qpoint, we write down the KVL equation of the collector loop as indicated in Figure 5.21.
IC (mA) 20
20
17.5 15
15
12.5 Q
10
10
7.5
5
0
5
ICBO
IE
10
15
=
5 2.5 0 mA 20
VCB(V)
VCC = ICRC + VCB
Figure 5.23 Output characteristics of CB configuration
VCB VCC + RC RC
(5.44)
IC = −
220
Electronic Devices and Circuits
VCC . We locate these RC two points on the output characteristics and draw the load line. Now select IE = 10 mA. Then the coordinates of the Qpoint are IC = 10 mA and VCB = 10 V. To draw the load line, set IC = 0, then VCB = VCC and set VCB = 0, then I C =
5.6
CC CONFIGURATION
Biasing of CC configuration using NPN and PNP devices is shown in Figures 5.24 and 5.25, respectively. IE VEB IB
−
−
+
VCE
VCC
− +
+
VCB VBB
Figure 5.24 Biasing a CC configuration using an NPN transistor IE VEB IB
+
−
VEC
+
VBB
+
VBC
VCC
− −
Figure 5.25 Biasing a CC configuration using a PNP transistor
For the CC configuration, it can be seen that the input current is IB and the output current is IE . As
IE = IC + IB
IE = IB(1 +
IC ) = IB(1 + hFE) IB IE = 1 + hFE = 1 + bdc IB
Thus CC configuration has the largest current gain.
(5.45)
Transistor Biasing and Thermal Stabilization
5.7
221
BIAS COMPENSATION
In the biasing circuits considered so far, the stability of the operating point was ensured by providing negative feedback in the biasing circuit. We shall see later that when a transistor is used as an amplifier, if negative feedback is used in the circuit, the gain of the amplifier gets reduced. To overcome this problem, a bypass capacitor is connected in shunt with RE, the resistance in emitter lead. However, no such arrangement can be incorporated in the collector to base bias circuit. The stability of the operating point can be achieved by providing compensating techniques, wherein circuit elements such as diodes, thermistors, and sensistors are connected in such a manner that any variation in leakage currents is nullified by an identical variation in these devices.
5.7.1 Diode Compensation One method of bias compensation is by using a diode as shown in Figure 5.26. VCC
IC
RL
+
R1 IB
VCE
VB
Q
+ + VD −
VBE
−
− IE
D
+ VR2
RE
R2
−
Figure 5.26 First method of diode compensation
From Figure 5.26, VB = VD + VR Therefore, IE = IC =
2
VD + VR2 −VBE RE
If, for any reason, VBE changes (by ± ∆VBE), then VD also changes in a similar manner (by ± ∆VD). V Thus, IC remains almost constant and is given as I C = R2 . RE The second method is to connect diode D between the base and the emitter terminals, and the diode voltage is also the same as VBE. As VBE reverse biases D, the current in it is IO, the reverse
222
Electronic Devices and Circuits
saturation current. If the diode D and the transistor Q are Si devices, ICO and IO vary identically, since the V − I characteristic of the diode is the same as the VBE − IC characteristic of the transistor. From Figure 5.27, I = IB + IO
or
(5.46)
IB = I − IO
Let there be an increase in temperature, which can increase ICO, resulting in an increase in IC. Since IO also changes as ICO, IO increases, resulting in decrease in IB. This in turn reduces IC to the original value, and hence ensures the stability of the operating point. The third method is to connect the diode D in the emitter lead as shown in Figure 5.28. The diode voltage VD is the same as VBE. The diode is connected such that VD and VBE are of opposite polarity. If VBE changes, VD also changes in a similar manner, thereby maintaining IC constant. VCC
I
VCC RL
ICO
IC
+
R IB
IB
VCE
Q
Q
VB
− D +
+ VBE IO
RL
Rs VBB
−
+
VBE−
+ VCE −
RE RD
IE
− VD +
−
Figure 5.27 Second method of diode compensation
D
VDD
Figure 5.28 Third method of diode compensation
5.7.2 Thermistor Compensation A thermistor is a temperaturesensing element that exhibits a large change in resistance proportional to a small change in temperature. Thermistors usually have negative temperature coefficient, which means that the resistance of the thermistor decreases as the temperature increases. In practice, the resistance decreases exponentially with the increase in temperature. As an approximation, if the relationship between resistance and temperature is linear, then ΔR = k ΔT where, ΔR is the change in resistance, ΔT is the change in temperature, and k is the temperature coefficient of resistance. Based on the sign of k, thermistors can be classified into two types: (i) If k is positive, the resistance increases with increasing temperature, and the device is called
223
Transistor Biasing and Thermal Stabilization
a positive temperature coefficient (PTC) thermistor or posistor. (ii) If k is negative, the resistance decreases with increasing temperature, and the device is called a negative temperature coefficient (NTC) thermistor. A thermistor with negative temperature coefficient can be used for bias compensation as shown in Figure 5.29. A thermistor with NTC is connected in shunt with R2. If the temperature remains unchanged, the voltage across R2 is V2. Then, the basetoemitter voltage is VBE, base current is IB, collector current IC, and the collector to emitter voltage is VCE. If, however, the temperature increases, IC increases VCE decreases. As a result, the Qpoint can be altered, despite bias stabilization using RE. But with the thermistor connected and as the temperature increases, RT decreases, the effective value of R2//RT is reduced, V2 is reduced, and therefore VBE, IB, IC are reduced (the reduced IC compensates for an increase in ICO) and VCE increases (brought back to the original value). Hence, the operating point remains unaltered.
VCC
IC
RL +
R1 IB
VCE
+ Thermistor with NTC
VBE
+
−
− IC +
IB V2
RT
R2
VE −
−
RE
Figure 5.29 Bias compensation using thermistor with NTC
5.7.3 Sensistor Compensation Sensistor is a resistor whose resistance increases with temperature, that is, the temperature coefficient is positive (e.g. 0.007/°C ). Sensistors are used in electronic circuits for compensating temperature. A bias compensation circuit using a sensistor is shown in Figure 5.30. A sensistor with PTC is connected in shunt with R1. If the temperature remains unchanged, the voltage across R1 is V1. Then, the basetoemitter voltage is VBE, base current is IB, collector current IC, and the collector to emitter voltage is VCE. If, however, the temperature increases, IC increases and VCE decreases. As a result, the Qpoint can be altered. But with sensistor connected, as temperature increases, RS increases, the effective value of R1//RS is increases, V1 is increased, and V2 is decreased. Therefore, VBE is decreased, IB is decreased, IC is reduced (the reduced IC compensates for changes in ICO, VBE, and bdc), and VCE increases (brought back to the original value). Hence, the operating point remains unaltered.
VCC
IC
+ Sensistor RS
RL R1 V1
+ IB
VCE
− + VBE
+
−
− IC +
IB V2 −
R2
VE −
RE
Figure 5.30 Bias compensation using a sensistor
224
5.8
Electronic Devices and Circuits
INTEGRATED CIRCUIT BIASING
In IC fabrication, resistors occupy more space. Hence, the biasing circuit shown in Figure 5.31, called the current mirror, is normally used. In this circuit, Q2 is used as a diode by connecting its collector to the base. Q1 and Q2 are identical transistors. Hence, IB1 = IB2 = IB
IC1 = IC2 = IC and b1 = b2 = b
Writing the KVL equation in the base–emitter loop of Q1 and Q2, VBE2 − VBE1 = 0 or VBE2 = VBE1 = VBE
VCC IR
R
IC1 RL
IC2 I Q2
Q1
+ IB1 VBE2 −
IB2
+ VBE1 −
Figure 5.31 IC biasing
IR, the reference current is determined as follows: IR =
VCC −VBE R
(5.47)
and I = I B1 + I B 2 = 2 I B
(5.48)
IR = I + IC2 = I + IC
(5.49)
Also,
Substituting Eqs (5.47) and (5.48) in Eqn. (5.49), 2 2+ b VCC − VBE = 2 I B + I C = I C + 1 = I C R b b Therefore, b VCC − VBE IC = R 2 + b
(5.50)
Even if b changes by wide margins (say from 50 to 200), the first term in Eqn. (5.50) almost remains constant. If VCC, VBE remain stable, and if R is a precision resistor, IC is stable.
5.9
COMBINATION OF VOLTAGE DIVIDER AND COLLECTORTOBASE BIAS
The circuit in Figure 5.32 is similar to the voltage divider bias circuit, except for the fact that R1 is returned to the collector of the transistor as in the case of collector–base bias circuit, instead of VCC. The circuit thus combines the collectortobase bias arrangement and the voltage divider circuit. The resultant advantage is that it can provide better bias stability. The analysis and design are, by far, similar to the analysis and design of the voltage divider bias circuit. This circuit differs from the voltage divider bias circuit on two counts: (i) the voltage across R1 is (VC − VB),where VC and VB are the voltages at the collector and base nodes and (ii) the current through RL is (IC + I2).
Transistor Biasing and Thermal Stabilization
225
VCC
RL
+ VC I2
IC
R1 VCE VB
+ I2
VBE
−
−
IB
R2
IC
+ VE
RE −
Figure 5.32 Combined collectortobase bias and voltage divider bias circuit
Example 5.7 Design the bias circuit shown in Figure 5.32. VCC = 24 V, VCE = 12 V, VE = 5 V, and IC = 5 mA. Solution: VE 5 = = 1 kΩ IC 5
RE =
VB = VBE + VE = 0.7 + 5 = 5.7 V Choose I 2 =
1 5 IC = = 0.5 mA 10 10 ∴R2 =
VB 5.7 = = 11.4 kΩ I 2 0.5
VC = VCE + VE = 12 + 5 = 17 V R1 =
RL =
VC − VB 17 − 5.7 = = 22.6 kΩ 0.5 I2
VCC − VC 24 − 17 = = 1.27 kΩ 5 + 0.5 IC + I2
226
5.10
Electronic Devices and Circuits
EMITTER CURRENT BIAS
The emitter current bias circuit shown in Figure 5.33 uses two separate sources for biasing the transistor: one is a VCC source and the other is a −VEE source. The base of the transistor is connected to the ground through R1. For all practical purposes, VB ≈ 0. This circuit can be represented as a voltage divider bias circuit with VB adjusted to 0.1 VBE, as shown in Figure 5.34. VCC VCC
+ RL
− IC VC
VBE IB
R1 IB
VCE VB = 0
VCE
+ −
−
+ VC IC
R1
+ VB
RL
VRL
+ +
VBE
IC VE
R2
IB
−
−
+
IC VE RE −
RE −
−VEE
−VEE
Figure 5.33 Emitter current bias circuit
Figure 5.34 Voltage divider bias equivalent of emitter current bias circuit
R1 is usually selected to have a voltage drop that is very much smaller than VBE. As a rule of thumb IB(max) R1 = 0.1 VBE. As the voltage at the base VB = 0, for the device to be in the active region, the voltage at the emitter should be VBE below zero level. From Figure 5.34, the voltage across RE = VEE − VBE The voltage at the collector, VC = VCC − VRL And VCE = VC − VBE since the voltage at the emitter is VBE.
5.11 THERMAL RESISTANCE Consider a transistor in which the junction temperature is TJ and the temperature of the air around the transistor (ambient temperature) is TA. The larger the power dissipated in the transistor, the larger the junction temperature. Therefore, (TJ − TA) ∝ PD ∴ (TJ − TA) = q PD where q is called the thermal resistance.
(5.51)
Transistor Biasing and Thermal Stabilization
PD =
227
TJ − TA q
(5.52)
TJ − TA °C/W PD
(5.53)
And q= Also TJ = TA + q PD
(5.54)
To improve the powerhandling capacity of the transistor, the junction temperature should be quickly removed. This can be achieved by increasing the effective surface area of the transistor by using a heat sink, which is usually a finned, large, black metallic heat conducting device. The heat sink is placed in close contact with the transistor casing. Example 5.8 Determine PD that a transistor can safely dissipate in free air if TA = 25°C, TJ = 150°C, and qJA = 10°C/W. Solution: PD =
TJ − TA 150 − 25 = = 12.5 W q 10
Additional Solved Examples Example 5.9 In the fixed bias circuit shown in Figure 5.11, a Si transistor with bdc = 100 is used. VCC = 12 V, VBE = 0.7 V, RL = 3 kΩ, and RB = 500 kΩ. Draw the dc load line and locate the Qpoint. Also find S. Solution: From Eqn. (5.2), IC = −
VCE VCC + RL RL
When IC = 0, VCE(cutoff) = VCC = 12 V V 12 When VCE = 0, I C (sat ) = CC = = 4 mA RL 3 The load line is drawn by locating these two points on the output characteristics, Figure 5.35. From Figure 5.11, IB =
VCC −VBE 12 − 0.7 = = 0.0226 mA RB 500
IC = IB bdc = 0.0226 × 100 = 2.26 mA Q
VCEQ = VCC − IC RL = 12 − 2.26 × 3 = 5.22 V
228
Electronic Devices and Circuits IC(sat) = 4 mA
Qpoint
ICQ = 2.26 mA
Load line 0
VCEQ = 5.22 V
VCC = 12 V
Figure 5.35 Locating the Qpoint
Stability factor S = (bdc + 1) = 101 Example 5.10 For the emitter bias circuit in Figure 5.36, RL = 2.5 kΩ, RE = 0.5 kΩ, and VCC = 24 V. Calculate the coordinates of the Qpoint, if midpoint bias is provided. Determine RB. bdc = 100. Calculate S. VCC
Solution: When IC = 0, VCE = VCE(cutoff) = VCC = 24 V
IC RL
When VCE = 0, I C = I C ( sat )
VCC 24 = = = 8 mA RL + RE 2.5 + 0.5
RB
+
IB +
For midpoint bias, I CQ =
I C(sat) 2
= 4 mA
VBE IB
And
I BQ =
I CQ bdc
=
4 = 0.04 mA 100
IC RE
G
Since, IC ≈ IE
Figure 5.36 Emitter bias circuit
VCC = IBRB + VBE + ICRE RB =
−
VCE −
VCC − VBE − I C RE 24 − 0.7 − 0.5 × 103 × 4 × 10 −3 = = 532.5 kΩ ≈ 500 kΩ IB 0.04 × 10 −3
Calculation of S: Here, RB 500 = = 1000 RE 0.5
Transistor Biasing and Thermal Stabilization
229
Using Eqn. (5.20),
S=
(1 + bdc ) 1 1 + bdc 1 + RB RE
=
(1 + 100) 1 1 + 100 1 + 1000
=
101 101 = = 91.82 100 1 + 0.1 1+ 1001
Example 5.11 In the collectortobase bias circuit shown in Figure 5.16, a Si transistor is used. VCC = 24 V, VCEQ = 10 V, and ICQ = 4 mA. If bdc = 50, (i) calculate the values of RL, RB, and S. (ii) If in the above circuit all other values remain unaltered, except for bdc which now changes to 100 when this transistor is replaced by another, find out the new operating point. Solution: (i) From Figure 5.16, RL =
VCC − VCEQ
I BQ =
I CQ
I CQ bdc
=
=
24 − 10 = 3.5 kΩ 4
4 = 0.08 mA 50
From Eqn. (5.31), VCC = (IBQ + ICQ)RL + IBQRB + VBE IBQ(RL + RB) = VCC − VBE − ICQRL
(RL + RB ) =
VCC − VBE − I CQ RL I BQ
=
24 − 0.7 − 4 × 3.5 9.3 = = 116.25 kΩ 0.08 0.08
RB = (RL + RB) − RL = 116.25 − 3.5 = 112.75 kΩ From Eqn. (5.35),
S=
(1 + bdc ) 1 1 + bdc 1 + RB R L
=
1 + 50 51 = = 20.4 1 + 1.50 1 1 + 50 112 75 . 1 + 3.5
230
Electronic Devices and Circuits
(ii) Equation (5.31) can be written as follows: I VCC = I B 1 + C RL + I B RB + VBE IB VCC = IB(1 + bdc)RL + IBRB + VBE IB =
VCC − VBE 24 − 0.7 23.3 = = = 0.05 mA RB + (1 + b dc )RL 112.75 + 101 × 3.5 466.25 IC = bdcIB = 100 × 0.05 = 5 mA. VCE = VCC − (I C + IB)RL = 24 − (5 + 0.05)3.5 = 24−17.675= 6.325 V
Example 5.12 (i) Design the biasing circuit shown in Figure 5.37 if IC = 10 mA and VCE = 5.8 V. dI C . bdc = hFE = 100, VBE = 0.7 V, and VCC = 12 V; (ii) determine the thermal stability factor , K = dI CEO Solution: VCC
(i) VCE = 5.8 V RL =
VCC −VCE 12 − 5.8 = = 620 Ω IC 10
IC RL RB
IB =
+
V − VBE 12 − 0.7 RB = CC = = 113 kΩ IB 0.1 × 10 −3
(ii) We can write
+
IB
IC 10 = = 0.1 mA bdc 100
dI C dI C dI = × CO dI CEO dI CO dI CEO
VBE
−
VCE − IE
Figure 5.37 Fixed bias circuit
But, S=
∴
dI C dI CO
dI C dI = S × CO dI CEO dI CEO
dI CO 1 And also, we know that ICEO = (bdc + 1)ICO. Therefore, = and for the fixed bias dI b ( dc + 1) CEO circuit S = (bdc + 1) ∴
(bdc + 1) = 1 dI C S =K= = b 1 dI CEO + ( dc ) (bdc + 1)
Transistor Biasing and Thermal Stabilization
231
Example 5.13 For the collector–base bias circuit RL = 500 Ω, IC = 10 mA, bdc = 50, and VCC = 12 V. Determine RB, S, and K. Assume VBE = 0 Solution: VCC = (IB + IC)RL + IBRB + VBE I C 10 = = 0.2 mA b dc 50
IB =
ICRL = 10 × 0.5 = 5 V IBRL = 0.2 × 0.5 = 0.1 V
RB = S=
12 − 5 − 0.1 = 34.5 kΩ 0.2
(1 + b dc ) 1 1 + b dc 1 + RB RL K=
=
51 1 + 50 = = 29.75 1 + 0.714 1 1 + 50 34.5 1 + 0.5
29.75 S = = 0.58 ( b dc + 1) 51
Example 5.14 For the biasing circuit shown in Figure 5.11, VCC = 12 V, RB = 500 kΩ, and RC = 2 kΩ. Find the maximum and minimum levels of IC and VCE, if bdc(min) = 50 and bdc(max) = 200. Solution: IB =
VCC − VBE 12 − 0.7 = 0.0226 mA = RB 500 × 103
IC(min) = bdc(min) × IB = 50 × 0.0226 = 1.13 mA VCE(max) = VCC − IC(min)RL = 12 − 1.13 × 2 = 9.74 V IC(max) = bdc(max) × IB = 200 × 0.0226 = 4.52 mA VCE(min) = VCC − IC(max)RL = 12 − 4.52 × 2 = 2.96 V Example 5.15 For the collectortobase bias circuit, VCC = 12 V, RB = 500 kΩ, and RL = 2 kΩ. Find the maximum and minimum levels of IC and VCE, if (i) bdc1 = 100, (ii) bdc2 = 150, and (iii) bdc3 = 200. Locate the Qpoints on the dc load line. Solution: (i) I B1 =
VCC − VBE 12 − 0.7 = = 0.016 mA RB + (1 + b dc1 ) RL 500 + (1 + 100 ) 2
232
Electronic Devices and Circuits
IC1 = bdc1 × IB = 100 × 0.016 = 1.6 mA VCE1 = VCC − IC1 RL = 12 − 1.6 × 2 = 8.8 V (ii) I B2 =
VCC −VBE 12 − 0.7 = = 0.014 mA RB + (1 + bdc 2 ) RC 500 + (1 + 150 ) 2 IC2 = bdc2 × IB = 150 × 0.014 = 2.1 mA VCE2 = VCC − IC2 RL = 12 − 2.1 × 2 = 7.8 V
(iii) I B3 =
VCC −VBE 12 − 0.7 = = 0.012 mA RB + (1 + bdc 3 ) RC 500 + (1 + 200 ) 2 IC3 = bdc3 × IB = 200 × 0.012 = 2.4 mA VCE3 = VCC − IC3 RL = 12 − 2.4 × 2 = 7.2 V
The Qpoints are located on the dc load line as shown in Figure 5.38. I C (sat ) =
VCC 12 = = 6 mA and VCE(cutoff) = VCC = 12 V RL 2 IC 6 mA DC load line
Q3
2.4 mA 2.1 mA
Q2
1.6 mA
Q1
0
7.2 V 7.8 V 8.8 V
12 V
VCE
Figure 5.38 Qpoints for the bias circuit of Example 5.15
Example 5.16 In the voltage divider bias circuit shown in Figure 5.17, Si transistor with hFE = 100 is used. VCC = 30 V, RE = 10 kΩ, RC = 10 kΩ, R1 = 30 kΩ, R2 = 20 kΩ, and VBE = 0.7 V. (i) determine IE, IB, IC, and VCE; (ii) calculate the stability factor S. Solution: (i) From Figure 5.17, Vth = VCC
R2 20 = 30 × = 12 V R1 + R2 20 + 30
Rth = R1 / / R2 =
20 × 30 = 12 kΩ 20 + 30
Transistor Biasing and Thermal Stabilization
The circuit in Figure 5.17 is redrawn as in Figure 5.39. VCC = 30 V
RC = 10 kΩ
IC Rth = 12 kΩ
IB +
VBE−
Vth = 12 V
+ VCE −
IC IB RE = 10 kΩ
Figure 5.39 Redrawn circuit of Figure 5.17 with component values as given in Example 5.16
From Figure 5.39, writing the KVL equation of the base loop: Vth = IBRth + VBE + (IB + IC)RE Vth =
IC 1 Rth + I C 1 + hFE hFE
Rth (1 + hFE ) + RE RE + VBE = VBE + I C hFE hFE
11.3 12 101× 10 ∴12 = 0.7 + I C + = 1.10 mA and I C = 10.22 100 100
IB =
I C 1.10 = = 0.011 mA hFE 100 IE = IB + IC = 1.1 + 0.011 = 1.111 mA
VCE = VCC − IC(RC + RE) = 30 − 1.1(10 + 10) = 8 V Therefore, the coordinates of the Qpoint are IC = 1.1 mA and VCE = 8 V (ii) Stability factor, S: From Eqn. (5.41), S=
(1 + bdc ) 1 1 + bdc Rth + 1 R E
=
(1 + 100 ) 1 1 + 100 1 + 12 10
= 2.17
233
234
Electronic Devices and Circuits
Example 5.17 For the voltage divider biasing circuit, VCC = 16 V, RE = 1.5 kΩ, RC = 2 kΩ, R1 = 80 kΩ, R2 = 20 kΩ, and VBE = 0.7 V. (i) Determine the operating point when (a) bdc = 100 and (b) when bdc is doubled; (ii) comment on the stability of the operating with change in bdc. Solution: (i) From Figure 5.17, Vth = VCC
R2 20 = 16 × = 3.2 V R1 + R2 20 + 80
Rth = R1 / / R2 =
20 × 80 =16 kΩ 20 + 80
The circuit in Figure 5.17 is redrawn as in Figure 5.40. VCC = 16 V
RC = 2 kΩ
IC Rth = 16 kΩ
Vth = 3.2 V
IB
+
VCE + − − VBE IB
IC RE = 1.5 kΩ
Figure 5.40 Redrawn circuit of Figure 5.17 with component values as given in Example 5.17
(a) From Figure 5.40, writing the KVL equation of the base loop: Vth = IBRth + VBE + (IB + IC)RE Vth =
Rth (1 + hFE ) IC 1 + Rth + I C 1 + RE RE + VBE = VBE + I C hFE h hFE FE hFE
2.5 16 101× 1.5 ∴ 3.2 = 0.7 + I C + = 1.49 mA and I C = 100 1.675 100 VCE = VCC − IC(RC + RE) = 16 − 1.49(2 + 1.5) = 10.78 V Therefore, the coordinates of the Qpoint are IC = 1.49 mA and VCE = 10.79 V
Transistor Biasing and Thermal Stabilization
235
(b) When doubled, bdc = 2 × 100 = 200 2.5 16 201× 1.5 ∴ 3.2 = 0.7 + I C + = 1.57 mA and I C = 1.59 200 200 VCE = VCC − IC(RC + RE) = 16 − 1.57(2 + 1.5) = 10.5 V Therefore, the coordinates of the Qpoint are IC = 1.57 mA and VCE = 10.5 V (ii) When bdc changes from 100 to 200, the change in (a) IC is from 1.49 mA to 1.57 mA = 0.08 mA in 1.49 mA is 5.37% (b) VCE is from 10.79 V to 10.5 V = 0.29 V in 10.79 V is 2.69% Example 5.18 Design the voltage divider bias circuit shown in Figure 5.17, to have VCE = 10 V and IC = 2 mA, given that VCC = 18 V, VBE = 0.7 V, hFE = 50, RC = 2 kΩ, and S ≤ 5. Solution: Calculation of RE: From Figure 5.17, VCC = VCE + IC(RC + RE) IC(RC + RE) = VCC − VCE = 18 − 10 = 8 V.
8
(RC + RE ) = 2 = 4 kΩ
RE = (RC + RE) − RC = 4 − 2 = 2 kΩ Calculation of R1 and R2: Given S ≤ 5. We have S =
1 + hFE where Rth = R1//R2 RE 1+ hFE RE + Rth ∴S =
1 + 50 2 1 + 50 2 + Rth
Hence, Rth = 8.87 kΩ. Normally, from experience, R2 is chosen as R2 ≤ 0.1 hFERE = 0.1 × 50 × 2 = 10 kΩ Rth =
R1R2 R1 + R2
8.87 =
10R1 R1 + 10
R1 =
88.7 = 78.5 kΩ 1.13
236
Electronic Devices and Circuits
Example 5.19 A PNP transistor is used in a voltage divider bias circuit, given that VBE = −0.7 V and bdc = 50. The Q point is required to be located at IC = −1.5 mA and VCE = −8 V. VCC = −18 V and the drop across RE is −3 V. If S = 5, determine RC, R1, and R2. Solution: ICRC = VCC − VCE − VE = −18 −(−8) −(−3) = −7 V RC =
−7 V = 4.66 kΩ −1.5 mA
( I C + I B ) RE = −3 V RE =
S=
1 I C 1 + b dc
RE = −3 V
−3 = 1.96 kΩ −1.02 × 1.5
RE 1 + hFE 51 1+ hFE = = = 10.2 S 5 RE + Rth
1 + hFE RE 1+ hFE RE + Rth
RE R + R 50 = 9.2 E th
RE 9.2 = = 0.184 RE + Rth 50 Rth = 8.7 kΩ
From the base–emitter loop, −Vth =
− I C Rth −1.5 × 8.7 − VE − VBE = − 3 − 0.7 = −3.96 V bdc 50
Vth = VCC
R V R2 −18 or 1 + 1 = CC = = 4.54 R2 Vth −3.96 R1 + R2 R1 = 3.54 or R1 = 3.54R2 R2 Rth =
R1R2 R1 + R2
8.7 =
3.54R2 R2 3.54R2 = 3.54R2 + R2 4.54
R2 =
8.7 × 4.54 = 11.16 kΩ 3.54
R1 = 3.54 R2 = 3.54 × 11.16 = 39.50 kΩ
Transistor Biasing and Thermal Stabilization
237
Example 5.20 Design the bias circuit shown in Figure 5.33 to operate from ±15 V supply voltages, given that VC = 7 V, VBE = 0.7 V, IC = 1.5 mA, and hFE = 50. Solution: The voltage at the emitter is VE = VEE − VBE = 15 − 0.7 = 14.3 V ∴ RE =
VE 14.3 = = 9.53 kΩ IC 1.5
The voltage drop across RL = VCC − VC = 15 −7 = 8 V ∴ RC = IB =
VCC − VC 8 = = 5.33 kΩ IC 1.5 I C 1.5 = = 0.03 mA hFE 50
VR1 = 0.1 VBE = 0.1 × 0.7 = 0.07 V R1 =
VR1 0.07 = = 2.33 kΩ 0.03 IB
Example 5.21 For the basing circuit in Figure 5.31, IC = 1 mA, VCC = 12 V, VBE = 0.7 V, and hFE = 100. Find R. Solution: We have b VCC −VBE IC = R 2 + b Or b VCC − VBE 100 12 − 0.7 R= = 11.08 kΩ = 102 × 2 + b IC 1
Example 5.22 For the voltage divider bias circuit shown in Figure 5.17, VCC = 30 V, VBE = 0.7 V, and RC = 4 kΩ. The Qpoint has VCE = 15 V and IC = 3 mA. IC varies from IC1 = 2.5 mA to IC2 = 3.5 mA as bdc of the transistor varies from b1 = 40 to b2 = 100 at 25°C, whereas the variation of ICO is negligible. Find (i) RE, (ii) R1, and R2. Solution: (i) From Figure 5.17, RC + RE =
VCC − VCE 30 − 15 = = 5 kΩ IC 3
238
Electronic Devices and Circuits
RE = ( RC + RE ) − RE = 5 − 4 = 1 KΩ
(ii) S ′′ = ∆I C = 3.5 − 2.5 = 0.017 ∆b 100 − 40 The stability factor S is S2 at b = b2 From Eqn. (5.31), S ′′ =
I C1S2 b1 (1 + b2 )
S2 =
S ′′ b1 (1 + b2 ) I C1
=
0.017 × 40 (1 + 100 ) = 27.47 2.5
We have S2 = (1 + b2 )
27.47 = (1 + 100 )
Rth + RE = 27.47 Rth + (1 + b2 ) RE
(Rth + 1)
(Rth + 1)
Rth + (1 + 100 )1
Rth + 101
0.27(Rth + 101) = Rth + 1 Rth =
= 0.27
0.73 Rth = 26.27
26.27 = 36 kΩ 0.73
Also, from Eq 5.37 Vth = VBE +
Rth + RE (1 + b1 ) b1 Vth = VCC
I C1 = 0.7 +
36 + 1(1 + 40 ) × 2.5 = 5.51 V 40
R2 V R2 = th or R1 + R2 R1 + R2 VCC
And Rth =
RV R1R2 = 1 th R1 + R2 VCC
∴ R1 = Rth
VCC 30 = 36 × = 196 kΩ Vth 5.51
Vth(R1 + R2) = VCC R2 or Vth R1 = R2(VCC − Vth) ∴ R2 = R1
Vth 5.51 = 196 × = 44.1 kΩ VCC − Vth 30 − 5.51
Transistor Biasing and Thermal Stabilization
239
Summary • A transistor is said to be in the active region (class A operation), when the base–emitter diode is forward biased and the base–collector diode is reverse biased.
• The current gain in CB configuration is a (= hFB), that in the CE configuration is b hFE =
a h = FB , 1 − a 1 − hFB
and that in the CC configuration is (1 + hFE). • ICO in CE configuration is (1 + bdc) times larger than that in the CB configuration. Further, ICO gets doubled for every 10°C rise in temperature. • The operating point or Qpoint in CE configuration gives the values of IC and VCE under no signal conditions (dc components). The operating point is likely to change with variations ICO, VBE, and b. • To provide bias stability, negative feedback is used in the circuit. The examples are collectortobase feedback bias and selfbias circuits. • Bias compensation can be provided by using diodes, thermistors, and sensistors. • Normally, a thermistor has a negative temperature coefficient (NTC) and a sensistor has a positive temperature coefficient (PTC).
multiple ChoiCe Questions 1. When forward–forward bias is provided in a transistor, then the transistor is said to be in (a) active region (b) saturation region (c) cutoff region (d) none of these 2. When forward–reverse bias is provided in a transistor, then the transistor is said to be in (a) active region (b) saturation region (c) cutoff region (d) none of these 3. When reverse–reverse bias is provided in a transistor, then the transistor is said to be in (a) active region (b) saturation region (c) cutoff region (d) none of these 4. The stability factor S is defined as (b) S =
dI C , I , and bdc constant dVBE CO
(d) S =
dI C , IC, and IB constant dI CO
dI C , b dc , and VBE constant dI CO
(b) S′ =
dI C , ICO, and bdc constant dVBE
(c) S′ = dI C , ICO, and VBE constant db
(d) S′ =
dI C , IC, and IB constant dI CO
(a) S =
dI C , b dc , and VBE constant dI CO
(c) S = dI C , ICO, and VBE constant db 5. The stability factor S′ is defined as (a) S′ =
240
Electronic Devices and Circuits
6. The stability factor S″ is defined as (a) S ″ =
dI C , b dc , and VBE constant dI CO
(b) S ″ =
dI C , ICO, and bdc constant dVBE
(c) S ″ =
dI C , I ,V , and constant d b CO BE
(d) S ″ =
dI C , IC, and IB constant dI CO
7. The stability factor S in the case of fixed bias is (a) 1 + hFE (c)
1 + hFE hFE
(b) 1 − hFE (d)
1 − hFE hFE
8. Stability factor S in the case of emitter bias and voltage divider bias becomes small because of (a) negative feedback provided in the circuit (b) positive feedback provided in the circuit (c) BJT is used in the circuit (d) none of the above 9. Thermistor and sensistor are used in a biasing circuit to provide (a) sufficient voltage gain (b) sufficient current gain (c) required power gain (d) bias compensation 10. A thermistor is a circuit element that normally has (a) positive temperature coefficient (b) negative temperature coefficient (c) large current gain (d) large voltage gain 11. A sensistor is a circuit element that normally has (a) positive temperature coefficient (c) large current gain
(b) negative temperature coefficient (d) large voltage gain
12. The resistance of a thermistor (a) increases with increase in temperature (b) decreases with increase in temperature (c) does not change with temperature (d) none of these 13. The resistance of a sensistor (a) increases with increase in temperature (b) decreases with increase in temperature (c) does not change with temperature (d) none of the above
short answer Questions 1. 2. 3. 4. 5. 6. 7. 8.
What do you mean by biasing a transistor? What are the different methods of biasing a transistor? What are the coordinates of the operating point in the CE mode of operation? What is meant by midpoint biasing? Give its advantage. What is a fixed bias arrangement? What is its main limitation? What is bias stabilization? What is the main advantage of the emitter bias arrangement over the fixed bias arrangement? It is often said that the collectortobase feedback bias is usually not preferred. Why is this so?
Transistor Biasing and Thermal Stabilization
9. 10. 11. 12.
241
What is meant by bias compensation? Explain its principle. What is a thermistor? How does its resistance vary with temperature? What is a sensistor? How does its resistance vary with temperature? Define the stability factor S.
long answer Questions 1. Draw the circuit of collectortobase bias arrangement of a transistor and explain its working. Derive the expression for S and infer how the stability factor can be improved. 2. With the help of a neat circuit diagram, explain the principle of operation of emitter bias arrangement. Derive the expression for S and infer how the stability factor can be improved. 3. With the help of a neat circuit diagram, explain the principle of operation of voltage divider bias arrangement. Derive the expression for S and infer how the stability factor can be improved. 4. What is the difference between bias stability and bias compensation? Explain how bias compensation can be achieved using a diode, thermistor, and sensistor.
unsolved problems 1. For a fixed bias configuration, determine, IC, RB, RC, and VCE, using the following specifications: VCC = 12 V, VC = 6 V, b = 80, and IB = 40 µA. 2. For a fixed bias configuration, determine IBQ, ICQ, and VCEQ using the following specifications: VCC = 16 V, b = 90, RC = 2.7 kΩ, RB = 470 kΩ and also find the saturation current Isat. 3. Calculate the quiescent collector current and voltage of collectortobase bias arrangement using the following data: VCC = 10 V, RB = 100 kΩ, RC = 2 kΩ and b = 50. Also specify the value of RB so that VCE =7V 4. Calculate the thermal resistance for 2N338 transistor for which the manufacturer specifies PC(max) = 125 mW at 25°C and maximum junction temperature of Tj = 150°C. What is the junction temperature if the collector dissipation is 75 mW? 5. A silicon transistor with b = 50, VBE = 0.6 V, VCC = 22.5 V, and RC = 5.6 kΩ is used for selfbiasing circuit. It is desired to establish a Qpoint at VCE = 12 V and IC = 1.5 mA and a stability factor S ≤ 3. Find RE, R1, and R2. 6. For the bias circuit shown in Figure 5.32, VCC = 20 V, VC =15 V, VE = 5 V, and IC = 4 mA. Determine the values of RE, R1, R2, and RC.
6
SMALLSIGNAL, LOWFREQUENCY BJT AMPLIFIERS
Learning objectives After going through this chapter, the reader will be able to
6.1
Draw the lowfrequency smallsignal equivalent circuits of transistor Realize the three basic amplifier configurations, namely, common base (CB), common emitter (CE), and common collector (CC) configurations Obtain the expressions for the voltage gain, current gain, input resistance, and the output resistance of an amplifier Compare the performance of the three basic configurations of BJT Convert the hparameters from one configuration to the other configurations Understand the relevance of bandwidth of an amplifier Understand the influence of distortion on the output waveform of the amplifier
INTRODUCTION
The bipolar junction transistor (BJT) is often referred to as transistor. A transistor can operate in one of the three regions of operation: active region, saturation region, and cutoff region. In switching applications, the operating point shifts between the saturation and cutoff regions. When the transistor is used in linear applications such as in amplifiers, the operating point is located in the middle of the active region. It has to be noted here that the transistor enters nonlinear portions of the characteristic in largesignal amplifiers (Chapter 11). The location of the operating point on the device characteristics determines the region of operation of a device. The word biasing means establishing the operating point in the desired region. Thus, biasing provides the necessary dc conditions in the circuit. The actual signal to be amplified by the circuit is applied only after the circuit is biased in the linear region of operation. We know that the linear region exists in the active region.
6.2 THE LOCATION OF THE OPERATING POINT Let us consider a transistor amplifier in CE configuration as shown in Figure 6.1. The location of the operating point determines the region in which a transistor is being operated. The output characteristics of a transistor are available in the datasheets. We can write the Kirchhoff’s voltage law (KVL) equation from the output loop of the circuit shown in Figure 6.1 as follows: VCE = VCC − I C RC
(6.1)
SmallSignal, LowFrequency BJT Amplifiers
The load line of the amplifier is obtained by rewriting Eqn. (6.1) as follows: IC =
VCC VCE − RC RC
243
VCC
(6.2) IC
RC
This is in the form of y = mx + c and is the equation R1 of straight line and this represents dc load line. + IB In the output characteristics of transistor in CE VCE configuration, we take collector voltage VCE on the + − xaxis and collector current IC on the yaxis. Typical − VBE output characteristics are shown in Figure 6.2. The + point of intersection of the device characteristic and R2 V2 the load line is called the operating point. The points − of intersection of the output characteristics and the dc load line specify the manner in which the IC varies as a function of VCE, since IC will have to satisfy both the output characteristics and the dc load line. G Appropriate point of intersection of the de load line and the output characteristics is chosen as the Figure 6.1 Transistor biased in the active region operating point. Operating point is also referred to as quiescent point or Qpoint. The operating point of the transistor amplifier circuit has to be located in the active region. This can be done by establishing the necessary dc conditions. The word biasing is used to indicate the method for establishing the dc conditions. Here, dc conditions mean fixing the collector voltage VCE and the collector current IC in such a way that the operating point (VCE , I C ) is located in the active region. DC load line
IC mA 15
IB7 IC(sat) = VCC/RL 10 QPoint
ICQ 5
IB2 IB1 IB = 0
0
0
5 VCEQ
10 VCC VCE(cutoff) VCE
V
Figure 6.2 Output characteristics and the dc load line
Readers may note that the operating point moves along the load line as expressed in Eqn. (6.2). At the lower extreme of the load line (VCE = VCC , I C = 0 ), we find the transistor operating in the cutoff region. At the upper extreme of the load line (VCE = 0, I C = VCC RC ) , we find the transistor operating in the saturation region. We expect the transistor to operate in the middle of the active
244
Electronic Devices and Circuits
region, and this means that VCE has to be around VCC 2 and the collector current has to be around I C = VCC 2R C . When a transistor circuit is used as an amplifier, the output signal is larger than the input signal. In practical applications, such as in a public address system, the input signal is a speech signal. The speech signal contains a number of frequency components with varying amplitudes. To find the amplitude of each of these frequency components in the output is a very difficult task. To avoid such difficulty, a sinusoidal signal with constant amplitude Vm sinwt is applied as input to the amplifier, and the output is found for the fundamental frequency w. Readers may note that sinusoidal signal is also known as an alternating signal. In this way, we find that the output signal at the collector contains a dc component and a series of ac components of frequencies w1, w2, w3, and so on, as we have at the input. The dc component of the output depends on the operating point. The series of ac components in the output represent the signals that are amplified. A coupling capacitor CC is connected at the collector for blocking the dc component. After passing through the blocking capacitor, the output retains only ac components that represent the input signals. The rms values of these output signals are represented by Vo .
6.3
SKETCHING THE AC CIRCUIT OF THE AMPLIFIER
Sometimes, the input signal may contain a dc component, and this component is blocked by the blocking capacitor, CC , connected at the input. Now, in order to find the ac component in the output when compared to the input, we have to draw the ac circuit of the amplifier. The ac circuit is drawn by using the superposition theorem, considering only the ac source and shorting the dc power supply VCC . The bias circuit has to be sketched as indicated in Figure 6.3(a) in order to determine the dc conditions of the circuit. We assume that CC and CE can be replaced by a short circuitin the range of frequencies of operation. The values of CC and CE are chosen to satisfy this condition. VCC
VCC
IC
IC
RL
R1 IB
+ VCE
+ VBE
−
−
R2 IB
IB
0
− IC RE
(a) The bias circuit
+
Cc +
+ V2
RL Cc + VC
R1
Vs
VCE
VC 0 −
0 +
+ V2 −
Vo
+
R2
CE RE
−
(b) The common emitter amplifier
Figure 6.3 Transistor amplifier in CE configuration
We apply superposition theorem to the transistor amplifier circuit shown in Figure 6.3 and consider the case of applying only the input ac signal. When we consider only the ac signal, the power supply voltage VCC is treated as a short circuit as indicated in Figure 6.4.
SmallSignal, LowFrequency BJT Amplifiers
IC Short 0
IB +
Cc +
R1
VBE
Short RL + VC
Cc 0
VC 0 −
+
+
Vs
V2
VCC
Short
Vo
+
R2
245
CE RE −
−
Short
Figure 6.4 The circuit of Figure 6.3 redrawn with VCC shorted and capacitors shortcircuited
In a similar way, the two coupling capacitors CC and emitter bypass capacitor CE are replaced by short circuits. Readers can also find “short” near these components in Figure 6.4. After applying these assumptions, the circuit in Figure 6.4 appears to be totally different. The ac equivalent circuit of Figure 6.4 is redrawn as Figure 6.5. 0 + Io
0
Ib + Vs
RL
R1
Vo R2
−
Figure 6.5 Resultant circuit of Figure 6.4
Application of superposition theorem enables us to draw its dc equivalent circuit and ac equivalent circuit. The dc equivalent circuit indicated in Figure 6.3(a) is wellknown as the biasing circuit as it provides the dc biasing conditions. Readers may note that Figure 6.3(b) contains both ac and dc sources and is a complete transistor amplifier circuit. The circuit in Figure 6.4 also contains all the components of a complete transistor amplifier circuit with some portions labeled “short” to enable us to understand the way in which we obtained the circuit in Figure 6.5. The ac equivalent circuit Figure 6.5 is used in our further analysis to obtain the properties of the transistor amplifier. Normally, the biasing resistances R1 and R2, as indicated in Figure 6.3(a) and Figure 6.5, are chosen to be large so that the amount of current drawn from the power supply VCC is small. The resistances R1 and R2 are also chosen to ensure R = R1  R2, is not going to alter the input conditions
246
Electronic Devices and Circuits
of the amplifier. We can see in Figure 6.5 that resistor R is the effective resistance of R1 and R2 that appears across Ic 0 the input resistance of the amplifier. If the input resistance + of the amplifier is very small compared to R, the circuit of 0 Figure 6.5 becomes same as Figure 6.6. In order to find the performance quantities of the Io Ib amplifier, namely, the current gain AI, the input resistance RL + Ri, the voltage gain AV, and the output resistance Ro, the Vo circuit in Figure 6.6 cannot be used directly, since the tranVs Ro sistor Q is present in the circuit. We know that transistor Ri is a nonlinear device, and the methods of network analysis can be used in a circuit that contains only linear bilateral − elements. Unless the transistor is replaced by its equivalent circuit, in terms of linear components, the performance quantities cannot be evaluated. This is the reason Figure 6.6 Simplified circuit of Figure 6.5 for replacing the transistor by its equivalent circuit. First, we replace the transistor by its equivalent circuit at low frequencies and under smallsignal conditions. We can note the transfer characteristic of the CE configuration in Figure 6.7. In the figure, it can be noted that the transistor is biased in the middle of the linear region of the characteristic. We can also note from Figure 6.7, where midpoint bias is provided we get the largest possible undistorted output swing. As long as the operation is limited to a very small region on the transfer characteristic, between points A and B, where the characteristic is linear, if the input swing is sinusoidal, the output swing is too sinusoidal. The input is reproduced at the output with the same frequency, but with increased amplitude. There is no distortion in the shape of the output waveform. Under these conditions, the transistor is said to be operating as a linear circuit element, and the amplifier can be described as a linear amplifier or smallsignal amplifier or voltage amplifier. We shall be referring to this circuit as smallsignal voltage amplifier in our further discussion. IC IC(sat)
IC 0
A ωt
IC1
Q1
IC1 =
IC(sat) 2
B
0
IB1
IB
Ib ωt
Figure 6.7 Transfer characteristic of CE configuration
SmallSignal, LowFrequency BJT Amplifiers
6.4
247
SMALLSIGNAL, LOWFREQUENCY MODEL OF THE TRANSISTOR
To calculate the performance quantities, we need to replace the transistor in Figure 6.6 by its equivalent circuit. We now try to obtain the smallsignal, lowfrequency model of the transistor. We observe that there exists a stray capacitance between a pair of terminals of an electronic circuit. Normally, this capacitance is small and is of the order of pF. At low frequencies, the reactance offered by these stray capacitances is very large compared to the other components in the circuit. Under these practical conditions, the stray capacitances can be replaced by open circuits. For this reason, the equivalent circuit is valid only at low frequencies. Let us consider the hparameter model of the transistor. For this purpose, consider Figure 6.8, in which the transistor is shown enclosed in a black box with input and output terminals shown externally. If the emitter is common between the input and the output, the configuration is called the CE configuration. Alternatively, if base or collector is common between the input and the output, the transistor configuration is I1 I2 called CB or CC configuration. + + The transistor shown as a black box in Figure 6.8 Transistor can be modeled in several ways: zparameter model, V1 V2 yparameters, and hparameter model. In early 1950s, the analysis of transistor circuits was carried out by using all these models. It has been found that the results Figure 6.8 Transistor as a twoport network obtained using the hparameter model were found to be compatible with experimental observations. Transistor is modeled in zparameters using Eqs (6.3) and (6.4) as given below where we write voltage equations. Readers may note that the four zparameters are measured in ohms. V1 = z11I1 + z12 I 2
(6.3)
V2 = z21I1 + z22 I 2
(6.4)
We can also write down current Eqs (6.5) and (6.6) in terms of yparameters. Readers may note that the four yparameters are measured in mhos. I1 = y11V1 + y12V2
(6.5)
I 2 = y21V1 + y22V2
(6.6)
As a result of the convenience offered by them, hparameters are normally listed in the datasheets. In the network shown in Figure 6.8, let us represent V1 and I2 as follows: V1 = hi I1 + hrV2
(6.7)
I 2 = hf I1 + hoV2
(6.8)
Equations (6.7) and (6.8) describe a lowfrequency, smallsignal transistor mathematically, and the resulting equivalent circuit is indicated in Figure 6.9. The word hybrid in hparameters indicates that the units of these four parameters are hybrid and do not belong to one physical quantity.
248
Electronic Devices and Circuits
The hparameters hi and ho are measured in ohms and mhos, respectively, and hparameter hr and hf are ratios and do not have units. hi +
+ I1 V1
I2
+
hf I1
h r V2
ho
V2
Figure 6.9 The lowfrequency, smallsignal model of the transistor
The definitions of the four hparameters hi, hr, hf, and ho are given below: Shortcircuit input resistance, hi V1 V2 = 0 I1
(6.9)
hr =
V1 I1 = 0 V2
(6.10)
hf =
I2 V2 = 0 I1
(6.11)
ho =
I2 I1 = 0 V2
(6.12)
hi = Opencircuit reverse transmission gain, hr:
Shortcircuit forward current gain, hf:
Opencircuit output admittance, ho:
Ib
For the CE configuration, these parameters are called hie, hre, hfe, and hoe; for the CC configuration, these parameters are called hic, hrc, hfc, and, hoc; and for the CB configuration, these parameters are called hib, hrb, hfb, and hob. Consider the transistor in the CE configuration as shown in Figure 6.10. hie
Ic
B+
Ib Vbe
hfe Ib
+
hoe
hre Vce
+ B
Vce
E
Figure 6.11 Equivalent circuit of the transistor in CE configuration
Q
+
E
Vce
Vbe
−
+C
Ic
C
−
Figure 6.10 Transistor in CE configuration
249
SmallSignal, LowFrequency BJT Amplifiers
Now, the transistor can be replaced between the base, emitter, and collector terminals by the equivalent circuit in Figure 6.11, with its CE parameters as in Table 6.1. Consider now the transistor in CB configuration, Figure 6.12 and its hparameter equivalent circuit in Figure 6.13.
Ie E
Ic
C +
+
Veb
Vcb
B
Figure 6.12 Transistor in CB configuration Ic
hib E+
+C Ie
Veb
Ib
hob
hrb Vcb
Ie
B +
+ Vcb
hfbI e
Vbc
C
E + Vec
B
Figure 6.13 Equivalent circuit
Figure 6.14 Transistor in CC configuration
Consider the CC configuration shown in Figure 6.14 and the equivalent circuit shown in Figure 6.15. The parameters can be evaluated using the input and the output characteristics for a given transistor configuration at a specified operating point. Typical values of these parameters are listed in Table 6.1, which can be used to evaluate the numerical values of the performance quantities.
Ie
hic
B
E
+ Ib Vbc
+
hfc I b + hoc
hrcVec
Vec
C
Figure 6.15 Equivalent circuit
Table 6.1 Typical values of the parameters at specified I C . Parameter
6.5
CE configuration
CC configuration
CB configuration
hi
hie = 1100 Ω
hic = 1100 Ω
hib = 21.6 Ω
hr
hre = 2.5 × 10 −4
hrc = 1
hrb = 2.9 × 10 −4
hf
hfe = 50
hfc = −51
hfb = −0.98
ho
hoe = 25 × 10 −6 A/V
hoc = 25 × 10 −6 A/V
hob = 0.4 × 10 −6 A/V
1 ho
1 = 40 kΩ hoe
1 = 40 kΩ hoc
1 = 2.04 MΩ hob
ANALYSIS OF A CE TRANSISTOR AMPLIFIER
Once again, consider the CE transistor amplifier shown in Figure 6.5 in which the parallel combination of R1 and R2 is replaced by R, as shown in Figure 6.16, and Rs is the internal resistance of the voltage source.
250
Electronic Devices and Circuits
In order to calculate the performance quantities, the transistor is now replaced by its equivalent circuit between the base, emitter, and collector terminals as in shown in Figure 6.17 and this circuit again redrawn as Figure 6.18 for the computation of the performance quantities. C + Io
Rs
B
Ib RL
+
CE ampliﬁer
+ Vs
Vo
R
Vi −
Rs
Ro
B
C +
+
+ Ri
RL
Vi −
Vs
−
−
Vo Io −
E
E
Figure 6.16 Resultant circuit of Figure 6.5 RS
Figure 6.17 The CE transistor voltage amplifier
hie
B
Ic +
+
+
Vi Vs −
Ib
hfe Ib
+
C hoe
hre Vo
RL
Vo Io
−
−
E
Figure 6.18 Circuit of Figure 6.17 with transistor replaced by its equivalent circuit
Current gain, AI We can write the following equation from the output circuit in Figure 6.18: I c = hfe I b + hoeVo
(6.13)
The output voltage can be expressed as follows: Vo = −I c RL
(6.14)
Substituting Eqn. (6.14) in Eqn. (6.13), I c = hfe I b + hoe ( −I c RL ) I c (1+ hoe RL ) = hfe I b We can obtain the ratio of currents as follows: Ic hfe = I b 1 + hoe RL
(6.15)
SmallSignal, LowFrequency BJT Amplifiers
251
A I, the current gain, using Eqn. (6.15), is given as follows: AI =
− hfe Io −Ic = = 1 + hoe RL Ib Ib
(6.16)
Input resistance, Ri From the base–emitter loop, Vi = hie I b + hreVo
(6.17)
Using Eqn. (6.14), Vi = hie I b + hre ( −I c RL ) Dividing by I b, −I Vi = Ri = hie + hre c Ib Ib
RL = hie + hre AI RL
(6.18)
Using Eqn. (6.16), − hfe RL Ri = hie + hre AI RL = hie + hre 1 + hoe RL
(6.19)
Dividing numerator and denominator in the second term by RL,
Ri = hie −
hfe hre h h = hie − fe re 1 YL + hoe + hoe RL
(6.20)
Here, Ri is the input resistance of the amplifier and YL = 1 ZL. Voltage gain, AV The voltage gain can be expressed as follows: AV =
R Vo −I c RL = = AI L Vi I b Ri Ri
(6.21)
Overall voltage gain, AV From the circuit in Figure 6.18, we have the input circuit of the amplifier as indicated in Figure 6.19. We have drawn the circuit with a voltage source in Figure 6.19(a) and a current source in Figure 6.19(b) for convenience. s
252
Electronic Devices and Circuits Rs
B
B
+
+
Ii
Vi Vs
Ri
Is
Rs
Ri
−
− (a)
(b)
Figure 6.19 Input circuit of the amplifier: (a) voltage source driving the input and (b) current source driving the input.
We can write the following equation from Figure 6.19 (a) by applying voltage divider method. Ri Vi = Vs Ri + Rs
(6.22)
We can write from Eqn. (6.14) that Vo = −I c RL Rewriting Eqn. (6.22), R + Rs Vs = Vi i Ri
(6.23)
Using Eqs (6.23) and (6.21), AV = s
Vo = Vs
Ri R Ri Vo = AI = AV = AI L R + R Ri + Rs Ri Ri + Rs i s Vi Ri
RL R + R i s
(6.24)
where AV is the overall voltage gain and AV is the gain of the amplifier not taking Rs into s
account. If in an amplifier, Ri >> Rs, then AVs = AV. Overall current gain, AI The overall current gain can be written as follows: s
AI = s
−Ic Is
Applying current divider method, from Figure 6.19(b), Rs I i = Is Rs + Ri Alternatively, this can be written as follows: R + Ri Is = I i s Rs
SmallSignal, LowFrequency BJT Amplifiers
253
Therefore, AI = s
−Ic = Is
Rs = AI . R + Ri Rs + Ri Ii s Rs −Ic
(6.25)
Dividing Eqn. (6.24) by Eqn. (6.25): RL Ri + Rs 1 RL = AI = AI Ri + Rs Rs AI Rs
AV
s
s
Therefore, R AV = AI L Rs s
(6.26)
s
Output impedance: Ro Ro = 1 Yo , where Yo is the output admittance. The procedure to find Ro or Yo is shown in the following discussion: Let RL → ∞ that is, open the load. Introduce a voltage source V2 at the output and find the circulating current I 2 , with Vs = 0 (short circuit the voltage source) or I s = 0 (open circuit the current source). The ratio of I 2 to V2 gives the output admittance, and its reciprocal is the output resistance of the circuit in Figure 6.20. RS + Vs = 0
hie
B
+
I2
Ib
Vi
h fe I b
+
C
+ V2 R1
hoe
hre V2
∞
−
− E
Figure 6.20 Amplifier circuit with Vs = 0 and RL = ∞
Yo =
I I 2 hfe I b + hoeV2 = = hfe b + hoe V2 V2 V2
From Figure 6.20, the KVL equation of the input loop with Vs = 0 is I b ( Rs + hie ) + hreV2 = 0 We can rewrite this equation as follows: I b ( Rs + hie ) = −hreV2
(6.27)
254
Electronic Devices and Circuits
Therefore, Ib −hre = V2 Rs + hie
(6.28)
Substituting Eqn. (6.28) in Eqn. (6.27), Yo =
I h h I2 = hfe b + hoe = hoe − fe re Rs + hie V2 V2
(6.29)
The CB and CC amplifiers are shown in Figures 6.21 and 6.22, respectively. The performance quantities for these amplifiers are also calculated on similar lines, except for the fact that the hparameters of the concerned configuration are now used in the expressions as indicated in Table 6.2 Rs
E
Rs
C
B
E
+ +
+ Vs −
CB ampliﬁer
Vi −
+ +
+ Vo
RL
Vs
Io −
B
−
Figure 6.21 CB transistor amplifier
CC ampliﬁer
Vi −
C
Figure 6.22 CC transistor amplifier
Table 6.2 Expressions to calculate the performance quantities of CB and CC amplifiers S. No
Performance quantity
CB amplifier
CC amplifier
1
AI
−hfb 1 + hob RL
−hfc 1 + hoc RL
2
Ri
hib + hrb AI RL
hic + hrc AI RL
3
AV
R AI L Ri
R AI L Ri
4
AV
RL AI Ri + Rs
RL AI Ri + Rs
5
AIs
Rs AI Ri + Rs
Rs AI Ri + Rs
6
Yo
hob −
s
RL
hfb hrb Rs + hib
hoc −
hfc hrc Rs + hic
Vo Io −
SmallSignal, LowFrequency BJT Amplifiers
6.6
255
SIMPLIFIED EQUIVALENT CIRCUIT OF THE TRANSISTOR
In the equivalent circuit of the transistor in Figure 6.11, since hreVce > hoeVce , I c = hfe I b (This means that ideally hoe = 0 or 1 hoe = ∞ .) Hence, this equivalent circuit in Figure 6.11 can be replaced by its approximate model as shown in Figure 6.23. Ic
B+
+C Ib hie
Vbe
hfe Ib Vce
E
Figure 6.23 Approximate CE model of the transistor
Using the approximate model, we can calculate the performance quantities. The amount of error is negligibly small. From Eqn. (6.16), AI =
−I c −hfe = I b 1 + hoe RL
Since hoe = 0, AI = −hfe From Eqn. (6.20), Ri = hie AV, AV , and AI are calculated using Eqs (6.21), (6.24), and (6.25), respectively. s
s
From Eqn. (6.29), Yo = 0 and Ro = ∞ Example 6.1 A transistor used in a linear CE amplifier at low frequencies has the following parameters: hie = 1.1 kΩ, hfe = 100, hoe = 25 µA/V, hre = 2.5 ×10 −4 , RL = 2.2 kΩ, and Rs = 500 Ω. Calculate the performance quantities. Solution: 1 1 = = 40 kΩ hoe 25 × 10 −6 From Eqn. (6.16), AI =
− hfe −100 −100 = = − 94.79 = 2.2 1 + 0.055 1 + hoe RL 1+ 40
256
Electronic Devices and Circuits
From Eqn. (6.18), Ri = hie + hre AI RL = 1100 + 2.5 × 10 −4 × ( −94.79 ) × 2.2 × 103 = 1100 – 52.13 ≈ 1048 Ω From Eqn. (6.21), AV =AI ×
RL 2.2 = − 94.79 × = − 198.99 Ri 1.048
From Eqn. (6.24), AV = AV × s
Ri 1.048 = −198.99 × = −134.72 Ri + Rs 1.048 + 0.500
From Eqn. (6.29), Yo = hoe −
hfe hre 100 × 2.5 × 10 −4 = 25 × 10 −6 − = 10 −6 ( 25 − 15.625 ) = 9.375 × 10 −6 mhos ( Rs + hie ) 500 + 1100 Ro =
6.7
1 1000 = = 106.67 kΩ Yo 9.375
ANALYSIS OF CC AMPLIFIER
VCC The CC amplifier is shown in Figure 6.24, and its ac circuit is shown in Figure 6.25. This circuit cannot be seen apparently as a CC amplifier. When redrawn, the circuit of IC Figure 6.25 with R1  R2 considered as large when compared to the input resistance of R1 the amplifier is shown in Figure 6.26. Here, it IB 0 can be clearly noted that the collector is the common terminal between the input and the + Cc Cc − output. The output is taken at the emitter. We 0 VBE + will subsequently be seeing that the voltage + Vs gain of this amplifier is approximately unity. + R2 V2 Hence, the emitter follows the base. This Vo means that when the base voltage changes, − RE − an almost identical change takes place at the emitter always. Hence, the common collector amplifier is also called an emitter follower. This amplifier gives an output that has the Figure 6.24 The emitter follower (CC transistor amplifier) same magnitude as the input. The output of this circuit also has the same phase as the input. This obviously means that this amplifier faithfully transmits the input to the output terminals. Hence, this is used as a buffer amplifier.
257
SmallSignal, LowFrequency BJT Amplifiers Ic 0 0
+ 0 Ib
+ Ib
+
Io
R1
Vs
RL
+
R2 RL
Vo
Ro
Vs
Vo
Ri −
−
Figure 6.26 Circuit that shows collector as the common terminal
Figure 6.25 The ac circuit of Figure 6.24
Replacing the transistor in Figure 6.26 with its lowfrequency smallsignal model, the equivalent circuit of the amplifier is as shown in Figure 6.27. RS
hic
B
E +
+
+
Ib
Vi Vs
+ RL hrc Vo
hfc Ib
Io
−
−
Vo
hoc −
C Ri
Figure 6.27 Equivalent circuit of CC amplifier shown in Figure 6.26
Using the relations in Table 6.2, the performance quantities of the CC amplifier can be calculated. Example 6.2 A transistor used in a linear CC amplifier at low frequencies has the following parameters: hic = 1.1 kΩ, hfc = −101, hoc = 25 µA/V, hrc = 1, RL = 2.2 kΩ, and Rs = 500 Ω. Calculate the performance quantities. Solution: 1 1 = = 40 kΩ hoc 25 × 10 −6 AI =
−hf c 1 + hoc RL
=
101 101 = = 95.73 2.2 1 + 0.055 1+ 40
R i = hic + hrc AI RL = 1.1 + 1× ( 95.73 ) × 2.2 = 1.1 + 210.6 = 211.7 kΩ
258
Electronic Devices and Circuits
A V = AI ×
RL Ri
= 95.73 ×
2.2 = 0.995 211.7
A Vs = AV ×
Ri 211.7 = 0.995 × = 0.993 Ri + Rs 211.7 + 0.500
Yo = hoc −
hfc hrc 101 × 1 = 0.063 mhos = 25 × 10 −6 + ( Rs + hic ) 500 + 1100
Ro =
1 1 = = 15.87 Ω Yo 0.063
From Example 6.2, it can be seen that AI for CC amplifier is 500 Rs B large, AV ≈ 1, Ri is large, and Ro is small. Here, it has to be + 6.67 mV + pointed out that while we write that AV is only 1, in reality Vi Ri the value of AV is slightly less than 1. Apparently, there is no 10mV V 1000 s justification to call this circuit as an amplifier since its voltage − − gain is less than unity. But this circuit has the advantage that Ri is large and Ro is small. How can this be an advantage? Figure 6.28 Voltage source driving the input of the CE amplifier Let us consider the input circuits of CE and CC amplifiers shown in Figures 6.28 and 6.29. For the CE amplifier in Figure 6.28, if the signal 0.5 Rs B Vs = 10 mV, Vi , the actual input to the amplifier is +
Ri 1000 Vi = Vs = 10 = 6.67 mV 1000 + 500 Ri + Rs
10mV
Vs
−
+
9.98 mV
Vi
Ri
−
200
In this case, though the signal at the input is 10 mV, only 6.67 mV appears between the actual input terminals of the Figure 6.29 Voltage source driving the input of the CC amplifier amplifier, which will be amplified by the amplifier. Considerable signal is wasted as drop across Rs . Whereas, for the CC amplifier in Figure 6.29, for the same input signal Vs = 10 mV , Vi , the actual input to the amplifier is Ri 200 Vi = Vs = 10 = 9.98 mV 200 + 0.5 Ri + Rs In this case, once again the signal at the input is 10 mV, but 9.98 mV appears between the actual input terminals of the amplifier, which will be amplified by the amplifier. This means that the entire signal appears at the actual input terminals of the amplifier. This is the advantage of using an amplifier with large input resistance when the driving signal is a voltage. Let us consider the output circuits of CE and CC amplifiers shown in Figures 6.30 and 6.31.
40 Ro
1500mV AVi +
+
2
Vo
RL
−
71.43mV
Figure 6.30 Voltage as the desired signal at the output of CE amplifier
SmallSignal, LowFrequency BJT Amplifiers 20
For the CE amplifier in Figure 6.30, let AVi = 1500 mV. Then Vο , the actual output of the amplifier is
Ro +
RL 2 Vo = − AVi = −1500 = −71.43 mV 2 + 40 RL + Ro
+
2 RL
1500 mV Vo
AVi
−
−
In this case, though the signal at the output is 1500 mV, only 71.43 mV appears across the load terminals. Considerable signal is wasted as drop across Ro .
259
1485 mV
Figure 6.31 Voltage as the desired signal at the output of CC amplifier
Whereas, for the CC amplifier in Figure 6.31, for the input signal AVi = 1500 mV , the actual output of the amplifier is RL 2000 Vo = AVi = 1500 = 1485 mV 2000 + 20 RL + Ro In this case, a signal of 1500 mV appears across the load terminals as 1485 mV. This means that the entire output signal appears across the load. This is the advantage of using an amplifier with small output resistance when the desired signal at the output is a voltage. From the above discussion, it is evident that a CC amplifier transmits the input to the output terminals reliably, with the same phase and with almost the same magnitude. Hence, CC amplifier is used as a buffer amplifier. Therefore, to derive a larger output voltage, it is preferable to provide a CC amplifier as an input stage for a CE amplifier and also a CC amplifer as an output stage for a CE amplifier (Figure 6.32). 0.5 K Rs + 10 mV Vs
+ 10 mV Vi −
+ 200 K 20 Ro 10 mV + Ri 1K A vVi −
1500 mV
1250 mV
CC ampliﬁer
CE ampliﬁer
CC ampliﬁer
Ri
40 K +
Ro
A vVi
+ 1250 mV 200 K
Ri
20 +
Ro
A vVi
RL
+ 1238 mV Vo 2K −
Figure 6.32 CC–CE–CC configuration
When 10 mV was the input to a CE amplifier alone, its output was 71.43 mV. If a CC amplifier is used as a preamplifier and also as an output stage, the output of the cascaded amplifier configuration is 1238 mV (Figure 6.32.) The output voltage in this case is 1238 mV, which is very large. Thus, we see the utility of CC amplifier. Despite its gain being equal to 1, it helps in deriving a larger output voltage when used in cascade with a CE amplifier mainly because of its large input resistance and negligible output resistance.
260
6.8
Electronic Devices and Circuits
ANALYSIS OF CB AMPLIFIER
The circuit of CB amplifier and its equivalent circuit are shown in Figures 6.33 and 6.34. Ie
Rs
Ic +
+ RL
Vs
Vo
− VEE
VCC
Figure 6.33 CB amplifier Rs
IC
hib
E
C +
+
+ Vs −
Ie
+
Vi −
hob hrb Vo
RL
Vo
hfb Ie B
Figure 6.34 Equivalent circuit
Using the relations in Table 6.2, the performance quantities of the common base amplifier can be calculated. Example 6.3 A transistor used in a linear CB amplifier at low frequencies has the following parameters: hib = 21.6 Ω, hfb = −0.98, hob = 0.49 µA/V, hrb = 2.9 × 10 −4. RL = 2.2 kΩ, and Rs = 500 Ω. Calculate the performance quantities. Solution: 1 1 = = 2.04 MΩ hob 0.49 × 10 −6 AI =
− hfb = 1 + hob RL
0.98 = 0.98 2.2 1+ 2040
SmallSignal, LowFrequency BJT Amplifiers
261
Ri = hib + hrb AI RL = 21.6 + 2.9 × 10 −4 × 0.98 × 2.2 × 103 = 21.6 + 0.625 = 22.23Ω
AV =AI ×
RL 2.2 = 0.98 × = 98 Ri 0.022
AV = AV ×
Ri 22.23 = 98 × = 4.17 Ri + Rs 22.23 + 500
Yo = hob −
hfb hrb 0.98 × 2.9 × 10 −4 = 0.49 × 10 −6 + = 10 −6 (0.49 + 0.545) ( Rs + hib ) 500 + 21.6
s
= 1.035 × 10 −6 mhos Ro =
1 106 = = 966.18 kΩ Yo 1.035
6.9 COMPARISON OF PERFORMANCE OF CE, CC, AND CB AMPLIFIERS In the preceding sections, we have calculated the performance quantities of CE, CC, and CB amplifiers. It was found that a CE amplifier has large AI and AV but has small Ri and medium Rο . Ri and Ro account for a reduced output voltage. The CE amplifier can be used as a voltage amplifier as well as a current amplifier. In the case of a CC amplifier, AI is large and AV ≈ 1. But this amplifier has large Ri and very small Ro . This amplifier ensures that the input is transmitted to the output terminals with the same magnitude and with the same phase. We can see that this amplifier is used as a voltage buffer amplifier. A CB amplifier has AI ≈ 1 but has a larger AV . Here again, there is no phase inversion. The output and the input are in the same phase. However, a CB amplifier has very small Ri and large Ro . Hence, the overall output gets reduced. It can be seen that this amplifier is used as a current buffer amplifier. The performance quantities calculated earlier for all these three configurations are tabulated in Table 6.3, for RL = 2.2 kΩ and Rs = 500 Ω. Table 6.3 Comparison of performance quantities of CE, CC, and CB amplifiers Amplifier configuration
AI
CE
−94.79
CC
95.73
CB
0.98
Ri (kW) 1.048 211.7 0.02223
AV −198.99 0.995 98
Ro (kW) 106.67 0.01587 966.18
262
6.10
Electronic Devices and Circuits
RELEVANCE OF INPUT AND OUTPUT RESISTANCES
We calculated the input and output resistances of the three basic topologies, namely, CE, CC, and CB. Now the pertinent question is:should the amplifier have small input resistance, or should it have large input resistance? Similarly, should an amplifier have small output resistance or should it have large output resistance? The answers to these questions depend on the type of signal drive used at the input and the type of signal desired at the output. We classify small signal amplifiers into four kinds based on these considerations: (i) voltage amplifiers, (ii) current amplifiers, (iii) transconductance amplifiers, and (iv) transresistance amplifiers. These four classes of amplifiers are discussed elaborately in feedback amplifiers in Chapter 9.
6.10.1 Voltage Amplifier A voltage amplifier, also called a voltagecontrolled voltage source (VCVS), is one in which the driving signal is a voltage and the desired signal at the output is a voltage. The constant proportionality is voltage gain AV , which is independent of Rs and RL (see Figure 6.35). The voltage gain AV is denoted by Eqn. (6.30) and it is a ratio: Rs
AV =
Vo Vi
+
(6.30)
Ri
In a voltage amplifier, output voltage can be written as follows: Vo = AVVi
Vs
+
Ro +
RL
Vi
Vo
A vVi
−
Figure 6.35 Voltage amplifier
Ideally, in a voltage amplifier, Ri = ∞ for the entire Vs to appear across Ri and Ro = 0 for the entire output to appear across RL. In practice, however, Ri >> Rs and Ro > Ro. However, to ensure maximum power transfer from generator to the load, as per the maximum power transfer theorem, Ro = RL . Therefore, in circuits called power amplifiers, there arises the need to provide an impedance matching transformer. We shall discuss power amplifiers later.
263
SmallSignal, LowFrequency BJT Amplifiers
6.10.2 Current Amplifier Alternately, consider another amplifier called the current amplifier, also called currentcontrolled current source (CCCS), in which the output current I o is proportional to the input current I s . The constant of proportionality is the current gain AI (see Figure 6.36). The current gain AI is denoted by Eqn. (6.31) and it is a ratio: Ii
AI =
Io Ii
(6.31)
Io
+
A iIi
Is Rs
In a current amplifier, output current can be written as follows:
RL
Ri
I o = AI I i
Vo
Ro
Figure 6.36 Current amplifier
Ideally in this case, Ri = 0 so that the entire I s flows through Ri and Ro = ∞ so that the entire AI I i flows through RL . However, in practice, Ri > RL . This means that if the driving signal is a current for the entire signal to flow through the actual input terminals of the amplifier, the amplifier chosen should have small Ri . Similarly, if the desired signal at the output is a current, for this current to flow through the load, the amplifier chosen should have large Ro.
6.10.3 Transconductance Amplifier On similar lines, we have transconductance amplifier, also called voltagecontrolled current source (VCCS), in which the desired output signal is a current I o, and the driving signal is a voltage Vs (see Figure 6.37). The transconductance Gm is denoted by Eqn. (6.32), and it is measured in mhos: Gm =
Rs
Io Vi
Io
(6.32)
+
+ +
In a transconductance amplifier, output current can be written as follows:
Ri
Vi G mVi
Ro
RL
Vo
−
Vs
I o = GmVi Figure 6.37 Transconductance amplifier
6.10.4 Transresistance Amplifier
Last, we have the transresistance amplifier, also called the currentcontrolled voltage source (CCVS), in which the desired output signal is a voltage Vo and the driving signal is a current I s (see Figure 6.38). The transresistance Rm is denoted Ii by Eqn. (6.33), and it is measured in ohms: V Rm = o Ii
+
Ro
(6.33)
Is
+ Rs
Ri
R mIi
RL
In a transresistance amplifier, the output voltage can be written as follows: Vo = Rm I i
Figure 6.38 Transresistance amplifier
Vo
264
Electronic Devices and Circuits
The amplifiers discussed till now, namely, CE, CC, and CB will not satisfy all the requirements of large AI , large AV , and large or small Ri or Ro . Hence, there arises the need to cascade these three basic amplifiers to derive the necessary performance quantities.
6.11
DISTORTION IN AN AMPLIFIER
Distortion may be present in the output of an amplifier due to various factors. Some of the factors responsible for distortion are discussed in the sections that follow.
6.11.1 Harmonic Distortion As long as the operation of the transistor is restricted to a small region around the operating point, in which the transfer characteristic can be representd by a straight line, the amplifier is free from harmonic distortion. This means that if the input is sinusoidal, the output is also sinusoidal but with an enlarged magnitude. The frequency of the signal in the output is the same as the frequency of the signal at the input. There is no distortion in the amplifier. However, if the amplitude of the input is increased, the operation is no longer restricted to the linear region in the transfer characteristic, and its operation extends into the nonlinear region. The operation in the nonlinear region, obviously, results in distortion in the output. This means that though the input is sinusoidal, the output is no longer sinusoidal, but is distorted in waveshape, as indicated in Figure 6.39. Amplitude distortion gives rise to harmonic distortion. Harmonic distortion essentially means that output contains frequency components that are not present in the input. We have described harmonic distortion here graphically. Now, the presence of additional frequency components in the output can be shown mathematically. Let us assume that the transfer characteristic is represented by a parabola with the operating point as its vertex. Let the instantaneous value of input base current ib be written as follows: IC
IC(sat)
A IC1
Q1
IC1 =
wt
IC(sat) 2
B IB
0 0
wt
Figure 6.39 Amplitude distortion in an amplifier
SmallSignal, LowFrequency BJT Amplifiers
265
ib = I m coswt The equation of the parabola is written as follows: ic = G1ib + G2 ib2 Substituting for ib in the above equation gives the following: ic = G1I m cos wt + G2 I m2 cos 2 wt A few mathematical manipulations indicate additional frequency components in the output current: G I2 ic = G1I m cos wt + 2 m (1 + cos 2 wt ) 2 ic =
G2 I m2 G I2 + G1I m cos wt + 2 m cos 2 wt 2 2
ic = Bo + B1 cos wt + B2 cos 2 wt Here, Bi are constants, where i = 0, 1, ... 2. Thus, it can be noted that the output contains, in addition to the required fundamental component B1 , an additional unwanted dc component B0 and a harmonic component B2. Thus operation of the transistor in the nonlinear region of the transfer curve gives rise to harmonic distortion. Higher order harmonics can also be present in the output. In general, if ic is expressed as a power series, ic = Bo + B1 cos wt + B2 cos 2 wt + B3 cos 3 wt + B4 cos 4 wt + ...
(6.34)
Thus, harmonic components can be present in the output of the amplifier having amplitudes: Bi , i = 1, 2, ... n. Usually, higher order harmonics are the worst culprits.
6.11.2 Noise Random variations in the output currents of electric circuits and amplifiers are called noise. These fluctuations are mainly due to (i) particle nature of the electric currents and (ii) variations in path, recombination rates, and diffusion caused by randomness of the charge movement. In general, noise can be due to two main factors: (i) Noise generated by sources external to the circuits such as lightning or localized electrical arcs or discharges. This type of noise is present typically below 20 MHz. (ii) Noise generated in the circuits due to internal phenomena. This type of noise is present typically above 20 MHz in the form of a hissing sound or snow.
Noise in Amplifiers Thermal Noise Thermal noise is developed due to random thermal motions and collisions of the charges and the atoms in all conductors. Thermal noise due to resistance R is given as Vn = 4 kTRB where k = Boltzmann’s constant = 1.38 × 10 −23 J/K , T is temperature in K, and B is the bandwidth in hertz.
266
Electronic Devices and Circuits
Shot Noise Shot noise arises because of the random nature of charge diffusion across a junction. This noise is present uniformly in the frequency spectrum. Flicker Noise Flicker noise is due to random variations in the charge diffusion processes and is usually present below 1 kHz. This noise varies inversely with frequency, and hence is also called 1 f noise.
6.11.3 Intermodulation Distortion If two or more signals are applied as inputs to an amplifier and if the operation is not limited to the linear region of the transfer characteristic, then because of the nonlinearity of the transfer curve an additional distortion may be present in the output due to some and difference frequencies. This type of distortion is called intermodulation distortion. Let the input to the amplifier be vi = V1 sin w1t + V2 sin w 2 t Then using the Taylor series 2
iC = I C + a1 (V1 sin w1t + V2 sin w 2 t ) + a2 (V1 sin w1t + V2 sin w 2 t ) + ... This simplifies to a2 2 V1 + V22 + aV 1 1 sin w1t + aV 1 2 sin w 2 t 2 aV2 aV2 − 2 1 cos 2w1t − 2 2 cos 2w 2 t 2 2 + a2VV w − w cos ( 1 2 1 2 ) t − a2VV 1 2 cos (w1 + w 2 ) t
iC = I C +
(
)
Thus, the output contains an additional dc component, the desired fundamental frequencies w1 and w 2 , harmonic terms 2w1 and 2w 2 , and additional sum and difference frequencies (w1 + w 2 ) and (w1 − w 2 ).
6.12 TRANSCONDUCTANCE MODEL OF THE TRANSISTOR Using the CE amplifier with approximate model for the transistor as shown in Figure 6.23 AV =
vo −hfe I b RL −hfe = = RL vi hie I b hie Ic
B +
(6.35)
Vi = Vbe
C +
Ib
Io
hie
RL gm Vbe
Vo
E
Figure 6.40 CE Amplifier with Transconductance Model for the Transistor
SmallSignal, LowFrequency BJT Amplifiers
267
Using the definitions of hfe and hie, Ic hfe I b I = c = hie Vbe Vbe Ib
(6.36)
Equation (6.36) relates current I c in the output and voltage Vbe in the input and is called transconductance, gm I gm = c or I c = gmVbe (6.37) Vbe Also from Figure 6.23, I c = hfe I b
(6.38)
I c = hfe I b = gmVbe
(6.39)
From Eqs (6.37) and (6.38),
Hence, the equivalent circuit in Figure 6.23 can be replaced by the equivalent circuit in Figure 6.40.
6.13
FREQUENCY RESPONSE CHARACTERISTIC OF AN AMPLIFIER
Let the input to a voltage amplifier be a speech signal through a microphone as in a public address system. The output of the voltage amplifier is fed to a power amplifier that ultimately drives an electromechanical device such as a loud speaker. The speech signal contains a number of frequency components with varying amplitudes. As a result, if one wants to find out which frequency component is amplified by what amount, it becomes a difficult task. It is for this reason we normally consider a sinusoidal signal to find the response of the amplifier. This method is repeated for all possible frequency components present in the input. Dealing with a singlesinusoidal signal is the simplest of the cases. We select a signal of one frequency with constant amplitude, find out the output of the amplifier. Now, the frequency is changed, keeping the input amplitude the same as in the earlier case, find out the output. This procedure is repeated in the range of frequencies of interest. Ideally, whatever may be the frequency component of the signal at the input, as long as the amplitude is the same, the output should be the same, as labeled as “curve1” in Figure 6.41. In this case, the relation A = Vo Vi is valid and Vi is constant. However, in an amplifier, we have coupling capacitance CC (shown in Figure 6.42) and a stray shunt capacitance Cs (shown in Figure 6.43). The coupling capacitance CC degrades the lowfrequency response and the shunt capacitance Cs degrades the highfrequency response. The degraded curved portions of the frequency response are labeled “curve2,” as shown in Figure 6.41. Now, it becomes necessary to find out the frequency range in which the amplifier can be used so that the output almost remains the same. For this, we define two frequencies, f1 and f2, at which the power is P 2, where P is the power in the midband range. P is given as Vm2 RL, where Vm is the voltage in the midband range and RL is the load into which the power is dissipated. Readers may note that the frequency response curve is drawn for the output voltage of the amplifier. However, since the input is constant, it can be plotted for the gain. The maximum value of the gain is Am and a horizontal dotted line is drawn at 0.707 Am on this response, and obtained frequencies f1 and f2 . Then, the power at f1 and f2 can be given by the following expression:
268
Electronic Devices and Circuits
Vm
Am
P
Curve1 P/2
0.707Am
2
0
f1 is the lower half power (3dB) frequency
Vm Curve2
f2
f1
f2 is the upper half power (3dB) frequency
f
Bandwidth
Figure 6.41 Frequency response characteristic and calculation of bandwidth
(
Vm 2 P Vm2 = = 2 2RL RL
2
)
(6.40)
Therefore, if Vm is the voltage in the midband, Vm 2 is the voltage at f1 and f2 . We have located 0.707 Am on the gain axis and have drawn a horizontal line to determine f1 and f2 . The frequency range from f1 to f2 is called the passband or the bandwidth of the amplifier. In simple terms, by bandwidth we mean the frequency range in which the gain and the output of the amplifier almost remain constant as long as the input remains constant. The ratio of the power in the midband to that at f1 or f2 is measured in decibels abbreviated as dB in technical literature. Normally, linear gain is a ratio and does not have any units. We use logarithmic gain measured in dB for representing very large and very small values of gain. Logarithmic gain is mathematically defined as follows: P V GdB = 10 log10 2 = 20 log10 2 (6.41) P1 V1 dB power = 10 log10
P = 10 log10 2 = 10 × 0.3010 ≈ 3 dB P 2
Hence, these two frequencies f1 and f2 are also called 3dB frequencies and the bandwidth the 3dB bandwidth. If a frequency component below f1 or above f2 appears at the output along with a frequency component in the midband range, the output fluctuates by large amounts. Frequency components outside the prescribed bandwidth are not acceptable. We shall see later that in order to obtain the frequency response characteristic of an amplifier, we divide the frequency range into three ranges, namely, the midband range, lowfrequency range, and highfrequency range. In the midband range, the gain remains almost constant. In the lowfrequency range, the gain is influenced by the coupling capacitor Cc . The amplifier behaves like a RC highpass filter as shown in Figure 6.42. As the frequency increases, the X c of Cc decreases and Vo increases. At low frequencies, the gain assumes a lower value than its midband value. In the highfrequency range, the gain is influenced by the shunt capacitor Cs. This shunt capacitance is not an externally connected component in the circuit, and appears due to stray capacitances at high frequencies. Now, the amplifier functions as a RC lowpass filter as shown in Figure 6.43. As the frequency increases, the X c of Cs decreases, and consequently Vo decreases. Thus at high frequencies, the gain assumes a lower value than its midband value.
SmallSignal, LowFrequency BJT Amplifiers
269
Cc R2
+ +
R1
Vo
+
Vs
+ Cs
Vo
Vs −
−
Figure 6.42 Lowfrequency response influenced by CC
Figure 6.43 Highfrequency response influenced by Cs
We can calculate the lower cutoff frequency from Figure 6.42 as follows: R1 Vo = Vs R1 + 1 jwCc Vo = Vs
R1 1 R1 + j wC c Vo = Vs
where w1 =
1
=
1 1+ jwR1Cc
1 w 1+ 1 w
2
=
1 w 1− j 1 w
1
=
f 1+ 1 f
2
1 . At f = f1, Cc R1 Vo = Vs
1 1 1+ 1
2
=
1 2
Here, f1 denotes the halfpower frequency that is also known as lower 3dB frequency. Consider Figure 6.43. This circuit is a lowpass circuit. At low frequencies, X c is large and hence Vo is large. Vo 1 1 = = 2 2 Vs w f 1+ 1+ w2 f2 1 where w 2 = . Cs R2 Vo 1 = . Here, f2 denotes the halfpower frequency that is also known as upper Vs 2 3dB frequency. At f = f2 ,
270
Electronic Devices and Circuits
6.14 TRANSISTOR h PARAMETER CONVERSION Normally, CE hparameters are listed in the datasheets supplied by the manufacturer. If the amplifier under consideration is a CB amplifier, then the CB hparameters are required to be obtained in terms of CE hparameters. Alternatively, if the CB hparameters are specified, then it becomes necessary to derive the CE hparameters in terms of CB hparameters. In general, it may be required to obtain hparameters of one configuration in terms of hparameters of a different configuration. The procedure for hparameter conversion is discussed in this section.
6.14.1 CE hParameters in Terms of CB hParameters To obtain hie, hre, hfe, and hoe in terms of CB parameters, the CB equivalent circuit is drawn as shown in Figure 6.44 and is now represented as a CE configuration as shown in Figure 6.45. The relevant CE parameters are evaluated as per the definitions of these parameters. Ie
hib
Ic C
E +
hfb Ie
+
Veb
+ hob
hrb Vcb
−
Vcb
−
− B
Figure 6.44 CB equivalent circuit
hfbIe B
Ib
Ic
Y
Ic
X +
−
Ie
hob
C
I
+
hrbVcb Vbe
+
+
Vbc
−
Vce
hib −
− E
Figure 6.45 Circuit of Figure 6.44 drawn in CE configuration
(i) hie is defined as follows: hie =
Vbe Ib
Vce =0
From Figure 6.44, Veb = hib I e + hrbVcb
(6.42)
I c = hfb I e + hobVcb
(6.43)
and
SmallSignal, LowFrequency BJT Amplifiers
271
From Figure 6.45, (6.44)
Vce = Vcb + Vbe To get hie , set Vce = 0 then from Eqn. (6.44), 0 = Vcb + Vbe or Vcb = −Vbe = Veb
(6.45)
Substituting Eqn. (6.45) in Eqn (6.42), Vcb = hib I e + hrbVcb Ie =
Vcb (1 − hrb )
(6.46)
hib
From Figure 6.45, I b + I c + I e = 0 or −I b = I c + I e
(6.47)
Substituting Eqn. (6.43) in Eqn. (6.47), −I b = hfb I e + hobVcb + I e = I e (1 + hfb ) + hobVcb
(6.48)
Substituting Eqn. (6.46) in Eqn. (6.48), V (1 − hrb ) −I b = cb (1 + hfb ) + hobVcb hib (1 − hrb ) (1 + hfb ) + hob hib −I b = hib
Vcb
But, from Eqn. (6.45), Vcb = −Vbe Therefore, (1 − hrb ) (1 + hfb ) + hob hib −I b = hib Hence, hie =
(6.49)
( −Vbe )
Vbe hib = I b (1 − hrb ) (1 + hfb ) + hob hib
(6.50)
If hrb > hob hib , then Eqn. (6.51) reduces to hie ≈
hib 1 + hfb
(6.52)
272
Electronic Devices and Circuits
Equation (6.50) gives the exact value of hie, whereas Eqn. (6.52) gives the approximate value. (ii) hre is defined as follows: hre =
Vbe Vcb
Ib = 0
To get hre, set I b = 0 . From Eqn. (6.47), I c = −I e Substituing this value in Eqn. (6.43), −I e = hfb I e + hobVcb or I e (1+ hfb ) = −hobVcb Hence, Ie =
−hobVcb 1 + hfb
(6.53)
Substituting Eqn. (6.53) in Eqn. (6.42), −h V Veb = hib ob cb 1 + hfb
− hib hob + hrb Vcb + hrbVcb = 1 + hfb
h h − h (1 + hfb ) h h Vbe = ib ob − hrb Vcb = ib ob rb Vcb 1 + hfb 1 + hfb
(6.54)
We know that, Vce = Vcb + Vbe. Hence, (6.55)
Vcb = Vce −Vbe Substituting Eqn. (6.55) in Eqn. (6.54), h h − h (1 + hfb ) Vbe = ib ob rb (Vce −Vbe ) 1 + hfb h h − h (1 + hfb ) Vbe = ib ob rb Vce 1 + hfb
h h − h (1 + hfb ) − ib ob rb Vbe 1 + hfb
h h − h (1 + hfb ) hib hob − hrb (1 + hfb ) Vbe 1 + ib ob rb = Vce 1 + hfb 1 + hfb hib hob − hrb (1 + hfb ) 1 + h fb Vbe hre = = Vce (1 + hfb ) (1 − hrb ) + hib hob 1+ hfb
SmallSignal, LowFrequency BJT Amplifiers
hre =
hib hob − hrb (1 + hfb )
(1 + hfb ) (1 − hrb ) + hib hob
273
(6.56)
If hrb > hob hib , then Eqn. (6.57) reduces to hre =
hib hob − hrb (1 + hfb )
(1 + hfb )
=
hib hob −h (1 + hfb ) rb
(6.58)
Equation (6.56) gives the exact value of hre , whereas Eqn. (6.58) gives its approximate value. (iii) hfe is defined as follows: hfe =
Ic Ib
Vce =0
From Figure 6.45, writing the KCL equation at node X, I c + I − hfb I e = 0 I c = hfb I e − I (6.59)
I c = hfb I e + hobVbc Writing the KVL equation of the outer loop, Vbe = Vbc + Vce With Vce = 0,
(6.60)
Vbe = Vbc = −Vcb From the input loop Ie =
− (Vbe + hrbVcb )
(6.61)
hib
But from Eqn. (6.60), Vbe = −Vcb . Ie =
− ( −Vcb + hrbVcb ) hib
=
Vcb (1 − hrb ) hib
Substituting Eqn. (6.62) in Eqn. (6.59), Vcb (1 − hrb ) hfb (1 − hrb ) I c = hfb I e + hobVbc = hfb + hob + hobVcb = Vcb hib hib
(6.62)
274
Electronic Devices and Circuits
h (1 − hrb ) + hob hib I c = Vcb fb hib
(6.63)
Writing the KCL equation at node Y, I b + I c + I e = 0 or I b = −I c − I e
(6.64)
Substituting Eqs (6.62) and (6.63) in Eqn. (6.64), h (1 − hrb ) + hob hib I b = −Vcb fb hib
1 − hrb −Vcb hib
h (1 − hrb ) + hob hib + (1 − hrb ) (1 − hrb ) (1 + hfb ) + hob hib I b = −Vcb fb = −Vcb hib hib Hence,
h (1 − hrb ) + hob hib Vcb fb hib I hfe = c = Ib (1 − hrb ) (1 + hfb ) + hob hib −Vcb hib hfe = −
hfb (1 − hrb ) + hob hib
(1 − hrb ) (1 + hfb ) + hob hib
(6.65)
Eqn. (6.65) gives the exact value of hfe . If hrb > hob hib , then Eqn. (6.66) reduces to hfe =
−hfb 1 + hfb
(6.67)
Equation (6.67) gives the approximate value of hfe. (iv) hoe is defined as follows: hoe =
Ic Vce
I b =0
To get hoe , set I b = 0 From Eqn. (6.47), I c = −I e . Substituting this value in Eqn. (6.43), I c = −hfb I c + hobVcb or I c (1+ hfb ) = hobVcb
SmallSignal, LowFrequency BJT Amplifiers
275
Hence, Ic =
hobVcb 1 ( + hfb )
(6.68)
Substituting Eqn. (6.68) in Eqn. (6.42), and since Ie = −Ic Veb = hib I e + hrbVcb −h h −h V Veb = hib ob cb + hrbVcb = ib ob + hrb Vcb (1 + h ) (1 + h ) fb fb h h Vbe = ib ob − hrb Vcb (1 + h ) fb
(6.69)
Vce = Vcb + Vbe
(6.70)
We know that
Substituting Eqn. (6.69) in Eqn. (6.70), h h Vce = Vcb + ib ob − hrb Vcb (1 + h ) fb (1 + hfb ) + hib hob − hrb (1 + hfb ) h h Vce = 1 + ib ob − hrb Vcb = Vcb (1 + h ) (1 + hfb ) fb (1 + hfb ) (1 − hrb ) + hib hob Vce = (1 + hfb )
Vcb
(6.71)
From Eqn. (6.68) and Eqn. (6.71),
hoe =
hobVcb (1 + hfb )
Ic = Vce (1 + hfb ) (1 − hrb ) + hib hob (1 + hfb )
Vcb
=
hob (1 + hfb ) (1 − hrb ) + hib hob
(6.72)
Equation (6.72) gives the exact value of hoe. If hrb > hob hib, then Eqn. (6.73) reduces to hoe =
hob 1 + hfb
Equation (6.74) gives the approximate value of hoe.
(6.74)
276
Electronic Devices and Circuits
On similar lines, it is possible to convert parameters of one configuration into the other. The simplified parameters are listed in Table 6.4. Table 6.4 hparameter conversion Parameter
CE configuration
CC configuration
CB configuration
hie
–
hic
hib 1 + hfb
hre
–
1 − hre
hib hob − hrb 1 + hfb
hfe
–
− (1 + hfe )
− hfb 1 + hfb
hoe
–
hoc
hob 1 + hfb
hic
hie
–
hib 1 + hfb
hrc
(1 − hre ) ≈ 1
–
hfc
6.15
− (1 + hfe )
≈1
–
−1 1 + hfb
hoc
hoe
–
hob 1 + hfb
hib
hie 1 + hfe
−hic hfc
–
hrb
hie hoe − hre 1 + hfe
hfb
− hfe 1 + hfe
hob
hoe 1 + hfe
hrc − 1 −
−
hic hoc hfc
(1 + hfc ) hfc
−
hoc hfc
–
– –
CE AMPLIFIER WITH UNBYPASSED EMITTER RESISTANCE
A CE amplifier with unbypassed emitter resistance is shown in Figure 6.46 and its ac circuit is shown in Figure 6.47(a). To calculate its gain, Ri and Ro , we replace the transistor by its lowfrequency approximate model indicated in Figure 6.47(b).
277
SmallSignal, LowFrequency BJT Amplifiers VCC
IC
RL
R1 0
+ VC
IB
Cc
Cc 0
Vc
+
+ −
VBE
+
+
Vs
Vo
R2 V2 −
RE
Figure 6.46 CE amplifier with unbypassed RE
Ic 0 +
B
0
+
Io
C
Ic +
Ib hie
Ib
RL
+ Ro
Vo
Vo
hfeIb
E
Vs
RL Io
Vs
Ri
Ib RE
hfeIb RE
−
− Ri
(a) The ac equivalent circuit of Figure 6.46
(b) The equivalent circuit
Figure 6.47 Equivalent circuit of Figure 6.46
Writing the KVL equation of the input loop, Vs = I b hie + ( I b + hfe I b ) RE = I b ( hie + (1 + hfe ) RE ) Ri =
Vs = hie + (1 + hfe ) RE Ib
(6.75)
278
Electronic Devices and Circuits
AI =
I o − hfe I b = = − hfe Ib Ib
(6.76)
R RL AV = AI L = − hfe Ri hie + (1 + hfe ) RE
(6.77)
Since (1+ hfe ) RE >> hie and also since hfe >> 1, hie + (1 + hfe ) RE ≈ hfe RE Therefore, Eqn. (6.77) reduces to AV ≈ −
hfe RL R =− L hfe RE RE
(6.78)
To find Ro, open RL and look into the output terminals. The resistance seen is the output 1 resistance, Figure 6.48. Since hfe I b is an ideal current source as = ∞ , Ro = ∞. hoe Ro′ = Ro  RL = RL B
C
+ I b
(6.79) Io +
hie hfeIb E
Vs Ib
Vo open RL
hfeIb RE
− Ro
Figure 6.48 Circuit to find Ro
6.16
MILLER’S THEOREM AND ITS DUAL
Consider circuit in Figure 6.49 which is essentially a feedback amplifier. The drop across RE , which we call as Vf is fed back to the input in phase opposition to the input voltage Vs . In order to illustrate the principle of feedback, we also make use of the amplifier depicted in Figure 6.50 where collector to base feedback bias is used. The two circuits in Figures 6.49 and 6.50 are feedback amplifiers. Feedback amplifiers are discussed in more detail in Chapter 9. These two feedback amplifier circuits can be converted into amplifier circuits without feedback by using Miller’s theorem and its dual.
SmallSignal, LowFrequency BJT Amplifiers
279
R′ + +
Rs
If
Io
Rs
Io Ib
Is Ib
RL
+
RL
+
Vo
+ Vo
Vs
Vs Vf
RE
− −
Figure 6.50 Amplifier with R′ between the output and the input
Figure 6.49 CE amplifier with unbypassed RE
We use the diagram in Figure 6.51 to introduce Miller’s theorem. According to Miller’s theorem if in a network there are n nodes, with node 1 as the input node, node 2 as the output node, and node N as the reference node, then the resistance R ′ connected between the input and output nodes can be replaced by two resistances R1 and R2 —the former connected in shunt with the input terminals and the latter connected in shunt with the output terminals. By using Miller’s theorem, it is possible to reduce a feedback amplifier into an amplifier without feedback. Then we can use the relations already derived to calculate the performance quantities. I1
I2
R′
I1 1 V1
2 V2
I2 1 V1
2 V2
R1 N
R2
N
Figure 6.51 Miller’s theorem
Let us calculate I1 . V V1 1 − 2 V1 V1 (1 − AV ) V − V2 = = I1 = 1 = R′ R′ R′ where R1 =
R′ 1 − ( AV )
V V1 = 1 R′ R1 (1 − AV )
(6.80)
(6.81)
280
Electronic Devices and Circuits
Similarly, V 1 V2 1 − 1 V2 1 − AV V2 V − V1 = I2 = 2 = = R′ R′ R′
V2 V = 2 R′ R2 1 1 − A V
(6.82)
where R2 =
R′ 1 1 − A V
(6.83)
and AV is the voltage gain. R1 and R2 draw the same currents I1 and I 2 from nodes 1 and 2 as R ′ has drawn from nodes 1 and 2. Miller’s theorem is valid with impedances also. Using Miller’s theorem, the circuit in Figure 6.50 is redrawn as in Figure 6.52. The circuit in Figure 6.52 is an amplifier circuit without feedback.
+ Rs
R2
+
RL Vo
R1 Vs −
Figure 6.52 Circuit of Figure 6.50 using the Miller’s theorem
The dual of the Miller’s theorem states that a resistance R ′ connected between node 3 and the reference node N can be replaced by two resistances R1 and R2 —the former connected in series with input node 1 and the latter connected in series with the output node 2 as indicated in Figure 6.53. R1 = R ′ (1 − AI )
(6.84)
A − 1 R2 = R ′ I AI
(6.85)
and
Here, AI is the current gain. Let us compare Eqs (6.81) and (6.84), which deal with Miller theorem and its dual. R ′ is divided (1− AV ) in Eqn. (6.81). R ′ is multiplied by (1− AI ) in the dual as shown in Eqn. (6.84).
SmallSignal, LowFrequency BJT Amplifiers
1
2
R1
1
2
281
R2
3 R′ N N
Figure 6.53 Dual of the Miller’s theorem
A − 1 R′ R′ and Eqn. (6.85), R2 = R ′ I . , which was 1 AI 1− AV AV AI multiplied by in Eqn. (6.83) is divided by in the dual, Eqn. (6.85). AV −1 AI −1 Similarly, compare Eqn. (6.83), R2 =
6.17
ANALYSIS OF THE AMPLIFIER CIRCUIT USING THE DUAL OF THE MILLER’S THEOREM
The circuit in Figure 6.49 can now be redrawn as in Figure 6.54, using the dual of the Miller’s theorem (Figure 6.53). The feedback amplifier is converted into an amplifier without feedback. R2 = R ′(A I−1)/A I
Rs R1 = R ′(1−A I) Ib +
Io
Ic +
RL Vo
Vs − Ri
Figure 6.54 Circuit of Figure 6.53 redrawn using the dual of the Miller’s theorem
Let us now consider the CE amplifier with unbypassed emitter resistance shown in Figure 6.49. This circuit is redrawn as in Figure 6.54 using the dual of the Miller’s theorem. We can now calculate the performance quantities. From Eqn. (6.84) and (6.85), A − 1 R1 = R ′ (1 − AI ) and R2 = R ′ I AI
282
Electronic Devices and Circuits
From Figure 6.54, the load for the amplifier is A − 1 RL′ = R2 + RL = R ′ I + RL AI The current gain, AI AI =
− hfe = 1 + hoe RL
− hfe AI − 1 1 + hoe R′ + RL AI
AI + hoe R ′ ( AI − 1) + AI hoe RL = − hfe AI (1+ hoe (RL + R ′ )) = hoe R ′ − hfe AI =
hoe R ′ − hfe 1 + hoe (RL + R ′ )
(6.86)
If hoe R ′ VG , VGS becomes negative. The advantage with voltage divider bias is that if for any reason ID increases, VGS becomes more negative, and thus reduces ID to the desired level. Thus, ID is stabilized. RD is usually chosen as a large value so as to get a large output. Also RS is chosen to be large on the consideration of bias stability. To achieve these twin objectives, generally RD and RS are chosen as the same values, that is RD = RS. In order to locate the Qpoint, we first draw the transfer curve and draw the straight line using Eqn. (7.25). Where this line intersects, the transfer curve is the Qpoint (Figure 7.35).
FET Characteristics, Biasing, and FET Amplifiers
ID
RD R1
D
IG = 0 VG
R2
G + VGS
R1
+
IG = 0
VDD
VDS S−
− + VS −
ID
RD
VD
G + VGS
VG +
VDD
R2
RS ID
D
− (a)
− + VS
325
VD + VDS S−
VDD
RS ID
− (b)
Figure 7.34 Voltage divider bias arrangement of an nchannel FET
To draw the straight line, we need two points. We get these two points using Eqn. (7.25). (i) Set VGS = 0, then, ID = VG/RS (point A) (ii) Set ID = 0, then VGS = VG (point B) ID IDSS
Q
IDQ ID = VG/RS B
IDSS/2 IDSS/4 VGSQ
A
−VGS VP
VP/2
0.3VP
0
VGS = VG
Figure 7.35 Locating the Qpoint for the voltage divider bias circuit
The coordinates of the Qpoint are VGSQ and IDQ. The advantage with voltage divider bias is that it stabilizes ID. Example 7.6 For the voltage divider bias circuit shown in Figure 7.34, VDD = 20 V, R1 = 2 MΩ, R2 = 0.4 MΩ, RD = 2 kΩ, RS = 1 kΩ, IDSS = 10 mA, and VP = −6 V (i) find IDQ, VGSQ. Calculate VD, VS, and VDS and (ii) repeat for RS = 4 kΩ.
Solution: VG = VDD
R2 0.4 = 20 × = 3.33 V R1 + R2 2 + 0.4
326
Electronic Devices and Circuits
The transfer curve is plotted in Figure 7.36. ID (mA) 10 IDSS
Q1 5.1
5 IDSS/2 3.3 2.5 IDSS/4
Q2
1.8
−3.7 −VGS (V)
VP = −6
RS = 1
RS = 4
−1.6
−1.8 −3 0.5 VP 0.3 VP
0
VG = 3.33 V
Figure 7.36 Transfer curve and locating Q1 and Q2
(i) The straight line for RS = 1 kΩ is plotted by locating two points, namely, VG = 3.33 V on ID = 0 axis and ID = 3.3 mA (= VG/RS) on the VGS = 0 axis. The coordinates of Q1 are IDQ1 = 5.1 mA and VGSQ1 = −1.6 V VS = IDQ1RS = 5.1 × 1 = 5.1 V, VD = VDD − IDQ1RD = 20 − (5.1)(2) = 9.8 V and VDS = VDD − IDQ1 (RS + RD) = 20 − (5.1)(3) = 4.7 V. The value of ID can be theoretically calculated as follows: 2
V ID = IDSS 1 − GS and VGS = VG−IDRS VP 2 (V − I R ) V I R 3.33 I D × 1 ∴ I D = I DSS 1 − G D S = I DSS 1 − G + D S = 10 1 − + −6 −6 VP VP VP 2
2
2
∴I D = 10 (1 + 0.55 − 0.167 I D ) From the above equation,
0.28 ID2 − 6.18 ID + 24 = 0 The two values of ID are 17.03 mA and 5.03 mA. Choose the second value. Hence, VGS = VG−IDRS = 3.33−(5.03)(1) = −1.7 V. From the graphical method, VGS = −1.6 V. (ii) The straight line for RS = 4 kΩ is plotted by locating two points: VG = 3.33 V on ID = 0 axis and ID = 0.833 mA (= VG/RS) on the VGS = 0 axis. The coordinates of Q2 are IDQ2 = 1.8 mA and VGSQ2 = −3.7 V VS = IDQ2RS = 1.8 × 4 = 7.2 V, VD = VDD − IDQ2RD = 20 − (1.8)(2) = 16.4 V and VDS = VDD − IDQ2 (RS + RD) = 20 − (1.8)(6) = 9.2 V.
FET Characteristics, Biasing, and FET Amplifiers
327
The value of ID can be theoretically calculated as follows: 2 (VG − I D RS ) VG I D RS 3.33 I D × 4 + I D = I DSS 1 − + = I DSS 1 − = 10 1 − −6 VP VP −6 VP 2
2
2
∴ ID = 10 (1.55 − 0.67 I D ) From the above equation,
4.5ID2 − 21.8ID + 24 = 0 The two values of ID are 3.15 mA and 1.69 mA. Choose the second value. Hence, VGS = VG−IDRS = 3.33 − (1.69)(4) = −3.43 V. From the graphical method, VGS = −3.7 V. Example 7.7 For the voltage divider bias circuit shown in Figure 7.34, VDD = 20 V, R1 = 2 MΩ, R2 = 0.5 MΩ, RD = 2 kΩ, and RS = 2 kΩ. Find ID(max), ID(min), VDS(max), and VDS(min). Use the minimum and maximum transfer curves in Figure 7.33. R2 0.5 = 20 × = 4 V. The bias curve is drawn by locating VG = 4.0 V R1 + R2 2 + 0.5 V 4 on the ID = 0 axis and ID = G = = 2 mA, on VGS = 0 axis. The bias curve is drawn using these RS 2 two points, Figure 7.37 and ID(max) and ID(min) are found out: Solution: VG = VDD
VGS(min) = VG − ID(max)RS = 4 − (3.15) (2) = −2.3 V VGS(max) = VG − ID(min)RS = 4 − (2.1) (2) = −0.2 V VDS(min) = VDD − ID(max)RD = 20 − (3.15) (2) = 13.7 V VDS(max) = VDD − ID(min)RD = 20 − (2.1) (2) = 15.8 V IDSS(max) = 10 mA ID Maximum transfer characteristic 5 mA ID(max) = 3.15 mA ID(min) = 2.1 mA 2 mA Minimum transfer characteristic VGS VP(max) = −6 V
−3 V
0 VP(min) = −2 V
VG = 4 V
Figure 7.37 Maximum and minimum transfer characteristics and the bias curve
328
Electronic Devices and Circuits
7.8.4 The Drain Feedback Bias The drain feedback biasing circuit is another biasing circuit that stabilizes ID (Figure 7.38). This circuit is almost similar to the voltage divider bias circuit shown in Figure 7.34, except for the fact that R1 is connected to the drain rather than to the VDD source. As in the case of the voltage divider bias, RS helps in stabilizing ID. Another feature of the drain feedback bias circuit is that if ID increases, the drop across RD, VRD increases, thereby reducing VG. Hence, VGS becomes more negative and ID is brought back to the desired value. Thus in this method of biasing, the voltage drops across RD and RS help in stabilizing ID. The voltage at the drain, VD, is VD = VDD − I D RD
(7.26)
And VG = VD
R2 R2 = (VDD − I DRD ) R1 + R2 R1 + R2
(7.27)
Therefore, R2 VGS = VG − I D RS = (VDD − I DRD ) − I D RS R1 + R2
(7.28)
VDD ID
RD + R1
VD
I2 IG = 0
VG
+ VGS
R2 I2
− + VS −
+ VDS − RS ID
Figure 7.38 The drain feedback circuit
7.9
UNIVERSAL TRANSFER CHARACTERISTIC OR THE UNIVERSAL BIAS CURVE
To analyze the biasing circuits, the transfer characteristic was drawn for the given FET and the circuit parameters were determined. If a device with different specifications is used, then it becomes necessary once gain to draw the transfer characteristic for this particular FET. However, if the V I universal transfer characteristic is drawn with GS and D as the variables, then this curve can VP I DSS
FET Characteristics, Biasing, and FET Amplifiers
329
be used to analyze the biasing circuits using FETs with different specifications, since the variables are normalized. From Eqn. (7.1), V ID = 1 − GS I DSS VP
2
V ID for GS varying from 0 to 1 are tabulated in Table 7.6, and the universal VP I DSS transfer characteristic is plotted as shown in Figure 7.39. The values of
Table 7.6
VGS VP ID I DSS
V ID as a function of GS VP I DSS 0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.0
0.81
0.64
0.49
0.36
0.25
0.16
0.09
0.04
0.01
0
1.0 0.9
ID/IDSS
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.0 0.9 0.8 0.7
0.6 0.5 0.4 VGS/VP
0.3
0.2 0.1
0
Figure 7.39 Universal transfer characteristic
The utility of the universal transfer characteristic for the analysis of the biasing circuits is illustrated by the following examples. Example 7.8 In the circuit shown in Figure 7.28, the FET has VP = VGS(off) = −6 V (maximum) and IDSS = 10 mA(maximum). Find out IDQ and VDSQ for VGSQ = −1.3 V, using the universal transfer characteristic in Figure 7.39. Solution: (i) To find ID(max) and VDS(min),
330
Electronic Devices and Circuits
VGS 1.3 = = 0.217 VP ( max ) 6 Draw the vertical line at 0.217 (Figure 7.40). This intersects the transfer curve at Q, and the ID corresponding value of = 0.615 I DSS( max ) 1.0 0.9
ID/IDSS
0.8 0.7 Q 0.6
0.615
0.5 0.4 0.3 0.2 0.1 0 1.0
0.9
0.8
0.7
0.6
0.5
0.4
VGS /VP
0.3
0.2
0.1
0
0.217
Figure 7.40 Analysis the fixed bias circuit using the universal transfer characteristic
Therefore, IDQ = 0.615 IDSS = 0.615 × 10 = 6.15 mA VDSQ = VDD − I DQ RD = 20 − (6.15)(2) = 7.7 V Example 7.9 For the selfbias circuit shown in Figure 7.30, RD = 2 kΩ, RS = 2 kΩ, and VDD = 20 V. Find IDQ, VDSQ, and VGSQ. Use the universal transfer curve in Figure 7.39. Solution: To draw the bias curve, we need two points: V I (i) When ID = 0, VGS = VS = −IDRS = 0. Therefore, D = 0 and GS = 0. This is the first point, A. VP I DSS I 2 (ii) When ID = 2 mA, VGS = VS = −IDRS = −2 × 2= −4 V. Therefore, D = = 0.2 and I DSS 10 VGS −4 = = 0.66 . This is the other point, B. VP −6 The line joining these two points is the bias curve. Q is the point where the line intersects the I universal bias curve (Figure 7.41) for which D = 0.18. Therefore, IDQ = 0.18 × IDSS = 0.18 I DSS × 10 = 1.8 mA. Hence, VDSQ = VDD − I D ( RD + RS ) = 20 − (1.8)(2 + 2) = 12.8 V. And VGSQ = IDQ RS = − (1.8) 2 = −3.6 V (Figure 7.30).
FET Characteristics, Biasing, and FET Amplifiers 1.0 0.9
331
ID/IDSS
0.8 0.7 0.6 0.5 0.4 0.3 B
0.2 0.18 0.1
Q 1.0 0.9 0.8 0.7
0.6 0.5
0.4
0.3
0.2 0.1
A 0 0
VGS/VP
Figure 7.41 Analysis of the selfbias circuit using the universal bias curve
From the above curve,
VGS = 0.595. Therefore, VGSQ = 0.595 × ( −6 ) = −3.57 V VP
Example 7.10 For the voltage divider bias circuit shown in Figure 7.34, VDD = 20 V, R1 = 2 MΩ, R2 = 0.5 MΩ, RD = 2 kΩ, and RS = 2 kΩ. VP = 6 V and IDSS = 10 mA. Find IDQ, VDSQ and VGSQ.. Use the universal transfer curves in Figure 7.39. Solution: VG = VDD
R2 0.5 = 20 × =4V R1 + R2 2 + 0.5
VGS = VG − I D RS (i) When VGS = 0,
VGS = 0. VP
Also, I D RS = VG . Therefore, I D =
VG 4 = = 2 mA RS 2
Hence, When
VGS I = 0, D = 0.2 . This is the first point, A, to draw the bias curve VP I DSS
VGS = 0.5, VGS = 0.5 VP = 0.5 × − 6 = −3 V. VP From Figure 7.34, (ii) When
I D RS = VG −VGS = 4 − ( −3 ) = 7 V
332
Electronic Devices and Circuits
Therefore, ID =
I D RS 7 = = 3.5 mA RS 2
Hence, ID 3.5 = = 0.35 I DSS 10 Thus, the second point to plot the bias curve is B, when VGS = 0.5, VP
ID = 0.35 I DSS
The bias curve is drawn joining points A and B. Q is the point at which the bias curve intersects I the universal transfer curve (Figure 7.42). At Q, D = 0.33 I DSS Therefore, I DQ = 0.33I DSS = 0.33 × 10 = 3.3 mA Hence, VDS = VDD − I DQ ( RD + RS ) = 20 − 3.3 ( 2 + 2 ) = 6.8 V And VGS = 0.425 VP Therefore, VGSQ = 0.425 ×VP = 0.425 ×VP = ( 0.425 ) ( −6 ) = −2.55 V 1.0 0.9
ID/IDSS
0.8 0.7 0.6 0.5 0.4 0.35 0.33 0.3
B Q
0.2
A
0.1
0.425 1.0 0.9 0.8 0.7
0.6 0.5 0.4 0.3 VGS /VP
0.2 0.1
0
0
Figure 7.42 Analysis of the voltage divider bias circuit using the universal bias curve
FET Characteristics, Biasing, and FET Amplifiers
7.10
333
FET AS A VOLTAGE VARIABLE RESISTANCE OR VOLTAGECONTROLLED RESISTANCE
From the characteristics of the nchannel JFET in Figure 7.43, it can be seen that to the left of VP ID increases linearly and the value of ID becomes smaller as VGS becomes more and more negative. We can infer from this that JFET behaves as a VCR, the value of this resistance becomes larger as VGS becomes more and more negative. Ohmic
Saturation region
Break down
ID (mA) 20 IDSS
“knee”
VGS = 0 VGS = −1 V
15 VGS = −2 V 10
VGS = −3 V
5
VGS = −4 V VGS = −VP
0
VP
VDS (V)
Figure 7.43 Output characteristic V–I curves of an nchannel JFET
The characteristics curves show four different regions of operation for a JFET, and these are given as follows: (i) Ohmic region – When VGS = 0, the depletion layer of the channel is very small and the JFET acts like a VCR. (ii) Cutoff region – This is also known as the pinchoff region where VGS ( = V P enough to make I D ≈ 0 , because the channel resistance is maximum.
) is negative
(iii) Saturation region – This is also known as active region. In this region, ID is controlled by VGS . VDS has little effect on ID. (iv) Breakdown region – When VDS is large enough, it causes the JFET’s resistive channel to break down, and ID becomes excessively large. The current in nJFET due to a small voltage VDS is given by the following equation: I DSS = ( 2a )
W qN d m nVDS L
(7.29)
where 2a = channel thickness, W = width, L = length, q = charge of an electron = 1.6 × 10−19 C, μn = electron mobility, and Nd = ntype doping concentration. In the saturation region, V I D = I DSS 1 − GS VP
2
(7.30)
334
Electronic Devices and Circuits
In the linear region called the triode region
ID =
2 I DSS V V −VP − DS VDS 2 GS 2 VP
In the triode region VDS is small. Hence I D =
(7.31)
2 I DSS (VGS − VP )VDS VP2
The following empirical relation is a good valid approximation to find out the resistance offered by the JFET as a function of the controlling voltage VGS. rd =
rdo
(7.32)
VGS 1 − V P
where rdo is the resistance when VGS = 0 and rd is the resistance for a given VGS. As an example, let a JFET have rdo = 20 kΩ . Then, rd at VGS = −4 V, if VP = −6 V is rd =
7.11
20 = 60 kΩ 4 1 − 6
FET AMPLIFIERS
In the earlier sections, we have seen the methods of biasing an FET. When we say we have provided bias to the FET, it means that we had established the necessary dc conditions in the circuit, say, IDQ and VGS, in a CS configuration (coordinates of the Qpoint). Now the transistor circuit is required to be used as an amplifier, that is, a circuit for which the output is larger than the input. We have three basic amplifier configurations: (i) common source (CS) amplifier, (ii) common drain (CD) amplifier, and (iii) common gate (CG) amplifier.
7.11.1 Common Source Amplifier
VDD
Consider the CS amplifier with voltage divider bias RD as shown in Figure 7.44 and its dc circuit shown R in Figure 7.45. Using the dc circuit, we select IDQ 1 and VGS. Once the operating point is selected, the Cc ac signal (sinusoidal) is applied at the input that is + required to be amplified. To find out the ac signal at Cc S the output and to calculate the other performance Rs Vo quantities, the ac circuit is drawn. R2 + The ac circuit of Figure 7.44 is drawn as shown in RS1 CS Vs Figure 7.46. Now the source S is common between − the input and the output. Hence, the amplifier is called CS amplifier. Figure 7.44 CS amplifier with voltage divider bias
FET Characteristics, Biasing, and FET Amplifiers
335
VDD RD
IDQ
R1 +
+ VDQ + VGSQ R2
RD
S
+
Rs R2
RS
Vo
R1
+
VS
Vs
−
−
Figure 7.45 DC circuit
Figure 7.46 AC circuit of Figure 7.44
The FET shown in Figure 7.47 is to be replaced by its equivalent circuit. There are two ways by which we can do this: (i) a voltage source equivalent circuit and (ii) a current source equivalent circuit. The parameters of the FET, namely, µ, rd, and gm are already defined. Using these parameters, the voltage source and the current source equivalent circuits are represented as shown in Figure 7.48.
R = R1//R2
+ RD
+ Vgs
Rs R
Vo −
+ Vs
−
Figure 7.47 Simplified circuit of Figure 7.46 rd D G +
D
−
G +
µVgs Vgs −
gmVgs
rd
Vgs −
+ S
(a) Voltage source equivalent circuit
S (b) Current source equivalent circuit
Figure 7.48 Equivalent circuit of the FET
In the ac circuit of Figure 7.47, the FET is now replaced by any of these equivalent circuits to calculate the gain. Using the current source equivalent circuit in Figure 7.48(b), the resultant circuit is as shown in Figure 7.49. Let RD = RL. From Figure 7.24, D
rR Vo = − gmVgs × d L rd + RL Vo rR = − gm × d L Vgs rd + RL
gmVgs
+
+
∴A =
G
Rs Vs
R
+ rd
RL Vo
Vgs −
− S
Figure 7.49 AC circuit of the CS amplifier
336
Electronic Devices and Circuits
Dividing by rd A = − gm ×
A=
If
− mRL RL = R rd + RL 1+ L rd
(7.33)
−m . As RL → ∞, A → m r 1+ d RL
D Io + gmVgs
rd
RL RL Normally, yos is listed in the data sheet. yos is the output admittance of CS configuration. The reciprocal of it is rd. If, for example, yos =10 µmhos, then rd =
1 = 100 kΩ 10 × 10 −6
Example 7.11 For the CS amplifier with voltage divider bias shown in Figure 7.52, VDD = 20 V, R1 = 2 MΩ, R2 = 0.4 MΩ, RD = 2 kΩ, Rs =1 kΩ, IDSS = 10 mA, and VP = −6 V. The coordinates of Q are IDQ = 5.1 mA and VGSQ = −1.6 V (Example 7.6). yos = 20 µmhos. Determine: (i) gmo , (ii) gm , (iii) rd , (iv) Ri , (v) Ro′ , and (vi) A. Solution: (i) gmo =
2 I DSS 2 × 10 = = 3.33 mmhos VP 6
FET Characteristics, Biasing, and FET Amplifiers
VGSQ −1.6 (ii) gm = gmo 1 − = 3.33 1 − = 2.44 mmhos VP −6
VDD RL
(iii) rd =
1 1 = = 50 kΩ yos 20 × 10 −6
(iv) R =
R1R2 2 × 0.4 = = 333 kΩ R1 + R2 2 + 0.4
337
R1
2
2
Cc +
Cc S 100
Ri = R = 333 kΩ (v) Ro′ =
Rs
R2
Vo
0.4
+
rd RL 50 × 2 = = 1.92 kΩ rd + RL 50 + 2
1
RS1
Vs
CS −
(vi) A = −gm × RL = −2.44 × 2 = −4.88
Figure 7.52 CS amplifier with voltage divider bias
7.11.2 CS Amplifier with Unbypassed R S In the circuit of Figure 7.44, if CS is removed, then the amplifier has an unbypassed Rs (Figure 7.53). Then the ac circuit is as shown in Figure 7.54. VDD RL R1 R = R1//R2
Cc +
Cc
+
RL
+ Vgs
Cc R2
Vi
+
+ Vi
Vo RS
−
−
Vo Rs
−
−
Figure 7.53 CS amplifier with unbypassed source resistance
R
−
Figure 7.54 AC circuit of Figure 7.53
The FET is now replaced by its equivalent circuit, resulting in the circuit in Figure 7.55. From Figure 7.55, writing the KVL equation of the outer loop, I d RL + ( I d − gmVgs ) rd + I d Rs = 0
(7.37)
Also Vgs = Vi − I d Rs Substituting Eqn. (7.38) in Eqn. (7.37), I d ( RL + Rs + rd ) − gm rd (Vi − I d Rs ) = 0
(7.38)
338
Electronic Devices and Circuits
I d RL + rd + Rs ( m + 1) = mVi ∴ Id =
mVi RL + rd + Rs ( m + 1)
Vo = −I d RL =
A=
(7.39)
− mVi RL RL + rd + Rs ( m + 1)
Vo − mRL = Vi RL + rd + Rs ( m + 1)
(7.40)
D
Ig
+
G +
R
rd
gmVgs Vgs
Vi
ld
Vo
S
− ld
RL Rs −
−
R¢i
Ro
Ri
R¢o
Figure 7.55 Equivalent circuit of Figure 7.54
If gm = 2.5 mmhos, rd = 50 kΩ, RL = 2 kΩ, and Rs = 1 kΩ, then m = 2.5 × 50 = 125; therefore, A with unbypassed Rs is A=
Vo − mRL −125 × 2 = = = − 1.4 Vi RL + rd + Rs ( m + 1) 2 + 50 + 1(125 + 1)
If RS is bypassed, that is Rs = 0 from Eqn. (7.40), A=
− mRL −125 × 2 = = −4.81 50 + 2 rd + RL
The gain gets reduced, with RS included. The minus sign indicates phase inversion. To calculate, Ri: Let Ig be the gate current and Rgs the gate to source resistance, which normally is very large for an FET (Figure 7.55). Ri =
Vi Ig
Vi = Vgs + gmVgs Rs = Vgs (1 + gm Rs )
(7.41) (7.42)
FET Characteristics, Biasing, and FET Amplifiers
339
And, Ig =
Vgs
(7.43)
Rgs
Substituting Eqs (7.42) and (7.43) in Eqn. (5.41), Ri =
Vi Vgs (1 + gm Rs ) Rgs = = (1 + gm Rs ) Rgs Ig Vgs
(7.44)
Since, Rgs is large, Ri is large. (7.45)
Ri′ = Ri  R ≈ R To calculate, Ro:
To calculate Ro, in Figure 7.55, let RL → ∞ , set Vi = 0, and take the ratio of Vo to Id (Figure 7.56). Now, replace the current source and its internal resistance by the voltage source and its internal resistance, as shown in Figure 7.57(a). D + rd
gmVgs Vgs
S
−
Vi = 0
ld
+
ld
RL= ∞ Vo
Rs −
Figure 7.56 Circuit to calculate Ro D
D
rd
+
ld
rd
−
ld
+
+
gmVgs rd
gm IdRs rd +
ld
S
−
Vo
ld
Rs
S
Vo Rs
−
−
Ro (a)
Ro (b)
Figure 7.57 Circuit to calculate Ro
340
Electronic Devices and Circuits
From Figure 7.56, with Vi = 0, Vgs = − I d Rs . Putting this condition in Figure 7.57(a), we get the circuit in Figure 7.57(b). From Figure 7.57(b), Vo = I d (rd + gm rd Rs + Rs ) = I d rd + Rs ( m + 1) Vo = rd + Rs ( m + 1) Id
∴ Ro =
(7.46)
Ro′ = Ro  RL
(7.47)
7.11.3 CD Amplifier or Source Follower The CD amplifier or the source follower is shown in Figure 7.58 and its ac circuit is shown in Figure 7.59.
VDD R1 R = R1//R2
CC
+
S R ′S
R S′
+
R2
+
Rs Vs
+
Vo
− Vgs
+
R Rs
Vo
Vs
−
Figure 7.58 CD amplifier or source follower
−
Figure 7.59 AC circuit of Figure 7.58
D G R′s +
+ R
rd
gmVgs Vgs
S
−
Vs Vi
ld
X
+
Rs
Vo
X
−
Figure 7.60 Equivalent circuit of Figure 7.59
When the FET is replaced by its current source equivalent circuit, the circuit in Figure 7.59 is drawn as in Figure 7.60. Folding the circuit along XX results in the circuit of Figure 7.61.
FET Characteristics, Biasing, and FET Amplifiers
From Figure 7.61, Vo = gmVgs
G +
(rd + Rs )Vo rd Rs or Vgs = rd + Rs gm rd Rs
(7.48)
+
S Vgs − gmVgs
Vi
341
+ V Rs o −
rd
Also,
D
(7.49)
Vi = Vgs + Vo
Figure 7.61 Resultant circuit of Figure 7.50
Substituting Eqn. (7.48) in Eqn. (7.49), Vi =
(rd + Rs )Vo + V gm rd Rs
A=
(rd + Rs ) ( gm rd Rs + rd + Rs ) = Vo 1 + = Vo gm rd Rs gm rd Rs
o
mRs Vo gm rd Rs = = Vi ( gm rd Rs + rd + Rs ) rd + ( m + 1) Rs
(7.50)
Dividing by rd, g m Rs
A=
1 + g m Rs +
Rs rd
≈
g m Rs ≈1 1 + g m Rs
(7.51)
Ri = R. The input resistance of a source follower can be made large. However, the highfrequency response of an FET tends to be poor.
Output Resistance Output resistance is calculated with load Rs included, by taking the ratio of Vo to Io with Vi = 0 (Figure 7.62). From Eqn. (7.49), when Vi = 0, Vgs = −Vo. Then, gmVgs = −gmVo. The equivalent circuit to calculate Ro is as shown in Figure 7.62. Note that the direction of current is now downward. G +
Io
S Vgs −
Vi = 0
gmVo
rd
Rs
+ Vo −
Io
S IL
≡
gmVo
+ V rd Rs o −
D Ro¢
Figure 7.62 Circuit to calculate the output resistance
Writing the KCL equation at node S, I o = gmVo + I L or I L = I o − gmVo
(7.52)
342
Electronic Devices and Circuits
and
Vo = I L
rd Rs rd + Rs
(7.53)
Substituting Eqn. (7.52) in Eqn. (7.53), Vo = ( I o − gmVo )
rd Rs rd + Rs
rR rR Vo 1+ gm d s = I o d s rd + Rs rd + Rs
Ro′ =
rd Rs rd + Rs
Rs Vo rd Rs rd Rs = = = = Io rd Rs rd + Rs + gm rd Rs rd + ( m + 1) Rs 1 + g R + Rs m s 1 + gm r + R rd d s
(7.54)
If rd >> Rs, Eqn. (7.54) reduces to Ro′ =
Rs 1 + gm Rs
(7.55)
1 gm
(7.56)
If gm Rs >> 1, Eqn. (7.55) reduces to, Ro′ =
Example 7.12 For the source follower in Figure 7.58, rd = 50 kΩ, gm = 0.0025 mhos, and Rs = 4 kΩ. Find A and Ro′ . Solution: From Eqn. (7.51), A=
gm Rs 1 + gm Rs +
Rs rd
0.0025 × 4000
=
1 + 0.0025 × 4000 +
4 50
=
10 = 0.90 11.08
From Eqn. (7.54), Ro′ =
Rs R 1 + gm Rs + s rd
=
4000 = 361.01 Ω 11.08
FET Characteristics, Biasing, and FET Amplifiers
343
7.11.4 CG Amplifier The CG amplifier is shown in Figure 7.63, and its ac circuit is shown in Figure 7.64. Cc
S
Cc
D
S +
+
D +
+ G
G Rs
Vi
RL
Vo VDD
−
−
RL
Rs
Vi
Vo
−
−
Figure 7.63 CG amplifier
Figure 7.64 AC circuit of Figure 7.63
If the FET is now replaced by its equivalent circuit, the circuit in Figure 7.64 is drawn as shown in Figure 7.65. (i) Calculation of Ri and R′i: To find Ri, the circuit in Figure 7.65 is redrawn as in Figure 7.66. From Figures 7.65 and 7.66, we
Ir
−
S +
D +
− Rs
Vi
Vgs +
−
V −Vgs can calculate Ri and R′i as Ri = i = since I I Vi = −Vgs and Ri′ = Ri / / Rs
Ri
R¢i
RL
gmVgs
I S
+ gmVgs
Ir + Vr
rd
Vi Vgs
D +
RL
Vo I +
− G Ri
Figure 7.66 Circuit to find Ri
From Figure 7.66, writing the KVL equation, Vi = Vr + Vo = Vr + IRL
Vo
I − G
Ro
Figure 7.65 Equivalent circuit of Figure 7.64
−
−
+ Vr rd
R¢o
344
Electronic Devices and Circuits
Or
Vr = Vi − IRL
(7.57)
I + gmVgs = I r
(7.58)
Writing the KCL equation at node S,
From Figure 7.66 and Eqn. (7.57), Ir =
Vr Vi − IRL = rd rd
(7.59)
From Eqs (7.58) and (7.59), I = I r − gmVgs =
Vi − IRL V − IRL − gmVgs = i + gmVi rd rd
since Vi = −Vgs .
R 1 ∴ I 1 + L = Vi + gm rd rd
Ri =
RL 1 + r
r + RL Vi d = = d I 1 1 + rd gm r + gm
(7.60)
(7.61)
d
If
RL 1 Ri 2. To calculate the exact value of the gain AV , using Eqn. (8.10), we need to calculate AI1 and Ri2 AI 2 =
Io −hfc = ≈ (1 + hfe ) if hoc RE RD
8.6.2 LowFrequency Range In the lowfrequency range CS is an open circuit, but CC is considered as shown in Figure 8.36. RD
Cc +
+
gmVgsRD Vgs −
R
+
Vo −
Figure 8.36 Lowfrequency equivalent circuit
From Figure 8.36, R
Vo = − gmVgs RD
R + RD +
1 j wC c
RRD − gm R + RD V Am RRD = Al = o = − gm = 1 1 w Vgs R + RD + 1+ 1− j 1 jw Cc jw Cc (R + RD ) w
The final result is Al =
Am w 1− j 1 w
(8.33)
388
Electronic Devices and Circuits
where the lower halfpower frequency is given by w1 =
1 Cc (R + RD )
(8.34)
8.6.3 HighFrequency Range In the highfrequency range Cc is a short circuit, but Cs is considered in Figure 8.37. RD +
Cs + Vgs −
gmVgsRD
R
+
Vo −
Figure 8.37 Highfrequency equivalent circuit
From Figure 8.37,
Vo = − gmVgs RD
1 R × jwC s 1 RD + R × j w Cs
1 R + jwC s 1 R + jwC Cs
RRD R − gm R + RD j wC s V Am − gm RD R = Ah = o = − gm RD = = w jwRRDCs R Vgs 1 R + RD + jwRRDCs 1+ j 1+ + RD R + w R + R j wC s 2 D j wC s The final result is Am
Ah =
1+ j
(8.35)
w w2
where the upper halfpower frequency is given by w2 =
8.7
R + RD RRDCs
(8.36)
EFFECT OF CE ON THE LOWFREQUENCY RESPONSE OF CE AMPLIFIER ASSUMING CC TO BE SUFFICIENTLY LARGE
Consider the CE amplifier shown in Figure 8.38. If CE in the circuit does not behave as a short circuit, the parallel combination of RE and CE offers a finite impedance, Ze . The equivalent circuit in the lowfrequency range, on the assumption that Cc is sufficiently large, is as given in Figure 8.39.
Multistage Amplifiers
389
VCC RC
+
Cc
+ Vi
Vo RE
CE
−
−
Figure 8.38 CE amplifier Ib
Ib
+
+ hie
RC
Vi
(1+ hfe)Ib
RE
hie
+
hfeIb
+
hfeIb
Vo
RC
Vi (1 + hfe)Ib
−
Vo
−
Ze
CE
−
−
Ri
Ri
Figure 8.39 Circuit to show the effect of CE on the lowfrequency response
We have R Al = −hfe C Ri
(8.37)
Ri = hie + (1 + hfe ) Ze
(8.38)
1 RE RE j wC E = Ze = 1 1 + jwCE RE RE + j wC E
(8.39)
Substituting Eqn. (8.39) in Eqn. (8.38), RE Ri = hie + (1 + hfe ) 1 + jwCE RE
(8.40)
390
Electronic Devices and Circuits
From Eqn. (8.37) and Eqn. (8.40), Al = −hfe
RC = Ri
−hfe RC RE hie + (1 + hfe ) 1 + jwCE RE
(8.41)
In the midband range w is large. Hence, the second term in the denominator is small. Therefore, from Eqn. (8.41), Am =
−hfe RC hie
(8.42)
Therefore, Al = Am
−hfe RC RE hie + (1 + hfe ) 1 + jwCE RE
hie hie = −hfe RC RE hie + (1 + hfe ) 1 + jwCE RE
hie (1 + jwCE RE ) Al = = Am hie (1 + jwCE RE ) + (1 + hfe ) RE
(1 + jwCE RE ) (1 + hfe ) RE (1 + jwCE RE ) + hie
(1 + hfe ) RE Taking 1 + hie
as the common factor, Al 1 = Am (1 + hfe ) RE 1 + hie
(1 + jwCE RE ) 1 + jwCE RE (1 + hfe ) RE 1+ hie
1+ Al 1 = Am (1 + hfe ) RE 1 + 1+ hie
j j
f fp f fo
(8.43)
where wo =
1 CE RE
(8.44)
Multistage Amplifiers
391
and 1+ wp =
since 1 > fo . Considering Eqn. (8.43) at f = fp , fp j fo hie × = + hfe ) RE 1 + j 1 fp (1+ fp
fp 1+ j fo
Al 1 = × Am (1 + hfe ) RE 1 + 1+ hie
since 1 > fo
From Eqs (8.44) and (8.45),
(1 + hfe ) RE fp fo
=
CE RE (1 + hfe ) RE hie = 1 CE RE hie
(8.47)
Substituting Eqn. (8.47) in Eqn. (8.46),
(1 + hfe ) RE 1 1 hie Al = × × = Am (1 + hfe ) RE hie 2 2 Thus, w p is the halfpower frequency:
w1 = w p =
(1 + hfe ) RE (1 + hfe ) hieCE RE
=
hieCE
(8.48)
Example 8.5 For the circuit in Figure 8.38, calculate the size of CE to provide f1 = 100 Hz, when RE = 1 kΩ, hie = 1.1 kΩ, and hfe = 70.
392
Electronic Devices and Circuits
Solution: From Eqn. (8.48), fp =
CE =
(1 + hfe ) 2phie fp
=
(1 + hfe ) 2phieCE
71 = 102.75 µF ≈ 100 µF 2p × 1100 × 100
The above expression is valid only when fp >> fo. From Eqn. (8.44), fo =
1 1 = = 1.59 Hz 2pCE RE 2p × 100 × 10 −6 × 1× 103
Hence, the condition is satisfied.
8.8
BANDWIDTH OF nIDENTICAL MULTISTAGE AMPLIFIERS
Consider n noninteracting (means there is no loading by the succeeding stage on the previous stage. This in turn may mean that the stages are isolated) identical cascaded stages with f1 and f2 as the halfpower frequencies. Then,
Ah for the n stages is Am
Ah 1 = 2 Am f + 1 f2
n
n2 1 = 2 1 + f f2
(8.49)
Let f2* be the upper halfpower frequency of the cascaded stage. Then, at this frequency Ah 1 = . Therefore, Am 2
1 * 2 1 + f2 f 2
n2
f * 2 1 + 2 f2
n2
2
=
1 2
= 2
f* 1n 1 + 2 = (2) f 2
Multistage Amplifiers
393
2
f2* 1n = (2) −1 f2 f2* = f2 f2* = f2
1n
(2)
−1
1n
(2)
−1
(8.50)
Similarly, Al 1 = 2 Am f1 1 + f
n
(8.51)
Proceeding on similar lines, f1* =
f1 1n
(2)
(8.52) −1
The bandwidth is f2* − f1* = f2* Example 8.6 The bandwidth of a singlestage amplifier is 100 kHz. Calculate the bandwidth when (i) n = 2 (ii) n = 3. Solution: From Eqn. (8.50), 1
f2* = f2 2 n − 1 1
(i) when n = 2,
2 n − 1 = 0.643. Hence, f2* = 100 × 0.643 = 64.3 kHz
(ii) when n = 3,
2 n − 1 = 0.510. Hence, f2* = 100 × 0.510 = 51.0 kHz
1
8.9 TRANSFORMERCOUPLED AMPLIFIER A transformer transfers electrical energy from the primary coil to the secondary coil through inductive coupling. A varying current in the primary induces a varying voltage in the secondary due to mutual induction. A CE amplifier with load RL connected through a transformer is shown in Figure 8.40. Normally, for lowfrequency applications a transformer is not used mainly because of the fact that the transformer becomes bulky and occupies more space as it is wound on an iron core. However, the transformer may be used for impedance matching in power amplifiers.
394
Electronic Devices and Circuits VCC N:1 R1
+ RL Vo
R′L
−
+
Cc
Vs
−
R2
CE
RE
Figure 8.40 A CE amplifier with load connected through a transformer
We have discussed about these amplifiers in Chapter 11 in detail. In the radio frequency range, the size of the transformer becomes small, and it hence can be used for interstage coupling. We will consider these transformercoupled amplifiers when we consider tuned amplifiers in Chapter 13. A twostage transformer coupled amplifier is shown in Figure 8.41 to illustrate the principle of transformer coupling. The transformers in circuit of Figure 8.41 can be ferrite cored transformers, in which the coefficient of coupling can be adjusted by adjusting the position of the ferrite core. The main advantage with this transformer coupling is that it blocks the dc component of the output signal. Inclusion of transformer in the coupling circuit helps in allowing only ac component of the output signal to the input of the next stage. Another major advantage is that a tuned circuit can be provided in the secondary winding (in some cases, both in the primary and secondary windings), which allows signals of only a narrow band of frequencies. Such amplifiers are called tuned amplifiers, which we will be discussing in Chapter 13. VCC N:1
N:1
R1
+ RL Vo
R1
− T2
T1 Q2
Q1 Cc
+ Vs
−
R2
RE
CE
R2
RE
CE
−
Figure 8.41 A twostage transformercoupled amplifier
Multistage Amplifiers
8.10
395
DIRECTCOUPLED AMPLIFIERS
A directcoupled amplifier, popularly known as a dc amplifier, is an amplifier in which the output of one stage is connected to the input of the next stage directly without using any reactive elements such as capacitors, inductors, or transformers. It is seen in the analysis of an RCcoupled amplifier that the lowfrequency response tends to become poor mainly because of the coupling capacitor Cc . As Cc is totally eliminated, the frequency response of this amplifier tends to be flat right form 0 Hz (dc) as shown in Figure 8.42. This is the major advantage of this amplifier. A singlesupply directcoupled amplifier is shown in Figure 8.43. When the output of one stage is directly coupled to the input of the next stage, not only the ac signal but also the dc is coupled to the input of the subsequent stage. As such, care should be taken to provide proper biasing in the circuit. A 0.707A
0
f
f2
Figure 8.42 Frequency response of a dc amplifier
VCC
RC1 R1
RC2
+VC Q2
Q1
+ Vs
R2
RE1
RE2
−
Figure 8.43 The direct coupled amplifier
The dc conditions for a specific amplifier are shown in Figure 8.44. R1 and R2 are adjusted to get a voltage of 2 V at the base of Q1. If the transistor is in the active region, then VBE1 = 0.6 V . Therefore, the voltage at the first emitter is 1.4 V. As RE1 is 1.4 kΩ, I E1 = 1 mA . Hence, I C1 ≈ 1 mA . As a result, the voltage at the first collector is 3 V, since RC1 = 12 kΩ . Since Q2 is also in the
396
Electronic Devices and Circuits
active region, VBE 2 = 0.6 V . Hence, the voltage at the second emitter is 2.4 V. Since RE 2 = 2.4 kΩ, I E 2 ≈ I C2 = 1 mA. As RC 2 = 9 kΩ, Vo , the voltage at the second collector is 6 V. Under quiescent conditions, output voltage Vo = 6 V . When a signal is applied at the input, this dc voltage at the output changes as per the variation of the signal at the input, resulting in an ac voltage referenced to 6 V. If now the temperature increases resulting in the increase in hFE , the dc voltage Vo at the output is smaller than 6 V. But any change in the output can only be due to an input signal present, but cannot occur due to device parameter variation. Thus, a change in the output voltage due to a change in hFE may be construed as a change occurring due to an input signal; but in reality, this change is due to the variation in hFE . This problem is called the problem of drift in dc amplifiers. If the problem of drift is taken care by providing proper temperature compensation,
VCC = 15 V
IC1
RC1
RC2
12
9
IC2 1 mA
1 mA 3V 2V Q1
2V 0
6V + 0.6 V
+ 0.6 V − RE1 1.4
VE1
6V
Q2 V0 −
VE2
0
2.4 V
1.4 V RE2 IE1 1 mA
2.4 1 mA IE2
G
Figure 8.44 The dc conditions
directcoupled amplifiers are the best amplifiers. In the singlesupply directcoupled amplifier (Figure 8.44), the output is referenced to a dc voltage of 6 V. However, in many applications, it may be required that the output may have to be referenced to 0 level. Then, it becomes necessary to use a twosupply (a positive source and a negative source) dc amplifier as shown in Figure 8.45. In the singlesupply dc amplifier, the input is not referenced to 0 V but is referenced to 2 V. However, if the input is to be referenced to 0 V, the negative 10 V source gives a voltage of −0.6 V at the emitter of Q1 which is the voltage needed to forward bias the emitter diode. The emitter and collector resistances of Q1 are adjusted so as to have a collector current of 1 mA. Consequently, the voltage at the first collector is 3 V. As discussed earlier, the emitter and collector resistances of Q2 are so adjusted that its collector current is again 1 mA and the voltage at the second collector is 6 V. Similarly the dc voltage at the collector of Q3 is 10 V. By providing a potential divider network comprising 100 kΩ and 100 kΩ resistors, it is possible to adjust the dc voltage at the output to 0 V. That is, in a twinsupply directcoupled amplifier if a dc voltage is present at the output, it can be translated to zero level. This is called level translation.
Multistage Amplifiers
397
VCC = 15 V
12
0.6 V
Q3 10 V 100 5.4 V
−
−
− 0.6 V
+ 0.6 V
Q2 6 V VE2
+ Q1
1 mA
1 mA
3V
1 mA 0
5
9
2.4 V
+ 0 Vs
5.4
12
Vo
10
2.4 1 mA
1 mA
1 mA
100 − 10 V
Figure 8.45 A twinsupply DC amplifier with input and the output referenced to zero
Additional Solved Examples Example 8.7 For the amplifier circuit shown in Figure 8.46, calculate the performance quantities, 1 using the exact and approximate analysis. hie = 1.1 kΩ, hre = 2.5 × 10−4, hfe = 100, and = 40 kΩ. hoe VCC
5 220
RC2 1
RC1 R3
R1
1
150
Rs
+
Cc
Cc Cc
+
Vo Vs
33
R2
RE
CE
−
R4
RE
CE
10
Figure 8.46 The CE–CE amplifier
Solution: R = R1//R2 =
220 × 33 150 × 10 = 28.7 kΩ and R′ = R3//R4 = = 9.38 kΩ 220 + 33 150 + 10
(i) Second stage; AI 2 =
−hfe −100 = = −97.56 1 + hoe RC 2 1 + 1 40
398
Electronic Devices and Circuits
Ri2 = hie + hre AI 2 RC2 = 1100 + 2.5 × 10 −4 × 1 × 103 ( −97.56 ) =1.076 kΩ
AV2 = AI2
RC2 1 = −97.56 × = −90.67 Ri 2 1.076
(ii) First stage: Load for the first stage RL is RL = RC1 / / R′ / / Ri 2 =
=
AI1 =
Ri 2 RC1R′ Ri 2 RC1 + RC1R′ + Ri 2 R′
1.076 × 5 × 9.38 = 0.81 kΩ 1.076 × 5 + 5 × 9.38 + 1.076 × 9.38 −hfe −100 = = −98.04 1 + hoe RL 1 + 0.81 40
Ri1 = hie + hre AI1RL = 1100 + 2.5 × 10 −4 × 0.81 × 103 × ( −98.04 ) = 1.08 kΩ
AV1 = AI1
RL 0.81 = −98.04 × = −73.53 Ri1 1.08
AV = AV1AV 2 = −73.53 × −90.67 = 6666.96
AV = AV × s
Ri = Ri  R =
Ri Ri + Rs
where
Ri = R//Ri1
28.7 × 1.08 =1.04 kΩ. 28.7 + 1.08
AV = 6666.96 × s
1.04 = 3398.84 1.04 + 1
This gain is very large, and the output and the input are in the same phase as each of these amplifiers produces a phase shift of 180°. Output resistance, Ro: Yo = hoe −
hfe hre hie + Rs1
where
Rs1 = Ro1//RL.
Multistage Amplifiers
399
Ro1 is the output resistance of the first stage, and RL is the load for the first stage. This value is effectively RL since Ro1 is large. Yo = 25 × 10 −6 −
100 × 2.5 × 10 −4 = (25 − 13.09) × 10−6 mhos 1100 + 810
Ro = 83.96 kΩ Approximate analysis: If hoe = hre = 0, the circuit in Figure 8.10 simplifies to that in Figure 8.12. (i) Second stage; AI2 = −hfe − 100 Ri2 = hie = 1.1 kΩ AV2 = AI2
RC2 1 = −100 × = −90.91 Ri 2 1.1
(ii) First stage: Load for the first stage RL is RL = RC1 / / R′ / / Ri2 =
=
Ri 2 RC1R′ Ri 2 RC1 + RC1R′ + Ri 2 R′
1.1× 5 × 9.38 = 0.82 kΩ 1.1× 5 + 5 × 9.38 + 1.1× 9.38
AI1 = −hfe = −100 Ri1 = hie = 1.1 kΩ
AV1 = AI1
RL 0.82 = −100 × = −74.55 Ri1 1.1
AV = AV1AV 2 = −74.55 × −90.91 = 6777.34 To calculate AV consider the circuit in Figure 8.11. s
AV = AV × s
Ri =
Ri Ri + Rs
28.7 × 1.1 = 1.06 kΩ 28.7 + 1.1
where
Ri = R//Ri1
400
Electronic Devices and Circuits
AVs = 6777.34 ×
1.06 = 3487.37 1.06 + 1
Opening the load RL = RC2 and looking into the output terminals, Ro = ∞ and R′o = RC2 = 1 kΩ. 1 = 40 kΩ , hoe hre = 2.5 × 10−4, RC = 5 kΩ, Rs = 1000 Ω, hrc = 1, and RE = 5 kΩ, calculate AV, AVs , Ri, and Ro. Example 8.8 For the CE–CC amplifier in Figure 8.47, with hie = 1.1 kΩ, hfe = 100,
VCC
RC
5
Rs 1 Q2
Q1
+
Ib + Vs
RE
Vo
5
Figure 8.47 CE–CC amplifier
Solution: (i) Calculations pertaining to the second stage: AI2 =
(1 + hfe ) 101 I e2 −hfc = = = = 89.78 I b 2 1 + hoc RE 1 + hoe RE 1 + 5 40
Ri 2 = hic + hrc AI 2 RE = hie + AI 2 RE = 1.1 + (89.78)(5) = 450 kΩ
AV2 = AI 2
RE 5 = 89.78 × = 0.998 Ri 2 450
(ii) Calculations pertaining to the first stage of the load for the first stage is RL = RC / / Ri 2 = 5 / /450 =
5 × 450 = 4.945 kΩ 5 + 450
Multistage Amplifiers
AI1 =
401
−I c1 −hfe −100 = = = −88.97 I b1 1 + hoe RL 1 + 4.945 40
Ri1 = hie + hre AI1RL = 1100 + 2.5 × 10 −4 (−88.97)(4.945 × 103) = 0.99 kΩ
AV1 = AI1
RL 4.945 = −88.97 × = −444.4 Ri1 0.99
AV = AV1AV 2 = −444.4 × 0.998 = −443.51 (iii) Overall voltage gain and current gain: AVs =
Vo Ri1 0.99 = AV × = −443.51 × = −220.64 Vs Rs + Ri1 0.99 + 1
Refer Figure 8.3, then AI =
To calculate
I e 2 I e 2 I b 2 I c1 I = = AI 2 b 2 AI1 I b1 I b 2 I c1 I b1 I c1
I b2 , refer Figure 8.5 I c1 I b 2 = −I c1
AI = AI 2
RC RC + Ri 2
I b2 RC −5 =− = = −0.011 I c1 RC + Ri 2 5 + 450
I b2 AI1 = 89.78 × ( −0.011) ( −88.97 ) = 87.86 I c1
(iv) To calculate the output resistance: The expression for Yo is Yo = hoc −
hfc hrc hic + Rs1
To calculate Yo, we first calculate Ro1, the output resistance of the first stage and then calculate Rs1(=Ro1//RC) Yo1 = hoe −
hfe hre hie + Rs
402
Electronic Devices and Circuits
Yo1 = 25 × 10 −6 −
Ro1 =
1 1 = 76.34 kΩ = Yo1 13.1× 10 −6
Rs1 = Ro1//RC =
Yo = hoc −
100 × 2.5 × 10 −4 = (25 − 11.90) 10−6 = 13.1 × 10−6 mhos 1100 + 1000
76.34 × 5 = 4.69 kΩ 76.34 + 5
hfc hrc 101 × 1 = 0.0174 mhos = 25 × 10 −6 + hic + Rs1 1100 + 4690
Ro =
1 1 = = 57.47 Ω Yo 0.0174
Approximate analysis: If hre = hoe = 0, then the circuit in Figure 8.3 is reduced to that in Figure 8.6. (i) Calculations pertaining to the second stage:
AI2 =
I e2 = (1 + hfe ) = 1 + 100 = 101 I b2
Ri2 = hic + hrc AI2 RE = hie + AI2 RE = 1.1 + (101) (5) = 506.1 kΩ
AV 2 = AI 2
RE 5 = 0.998 = 101× Ri 2 506.1
(ii) Calculations pertaining to the first stage: From Figure 8.6, the load for the first stage is as shown in Figure 8.7.
RL = RC / / Ri 2 = 5 / /506.1 =
AI1 =
−I C1 = −hfe = −100 I b1
Ri1 = hie = 1.1 kΩ
5 × 506.1 = 4.95 kΩ 5 + 506.1
Multistage Amplifiers
AV1 = AI1
403
RL 4.95 = −100 × = −450 Ri1 1.1
AV = AV1AV 2 = −450 × 0.998 = −449.1 (iii) Overall voltage gain and current gain: AV = s
AI =
To calculate
Vo Ri1 1.1 = AV × = −449.1 × = −235.24 Vs Rs + Ri1 1.1 + 1 I e 2 I e 2 I b 2 I c1 I = = AI 2 b 2 AI1 I b1 I b 2 I c1 I b1 I c1
I b2 , consider Figure 8.5. I c1 I b 2 = −I c1
AI = AI 2
RC RC + Ri 2
I b2 RC −5 =− = = −0.0098 I c1 RC + Ri 2 5 + 506.1
I b2 AI1 = 101× ( −0.0098 ) ( −100 ) = 98.98 I c1
(iv) To calculate the output resistance: The expression for Yo is Yo = hoc −
hfc hrc hic + Rs1
To calculate Yo, we first calculate Ro1, the output resistance of the first stage and then calculate Rs1(= Ro1//RC). Yo1 = hoe −
hfe hre hie + Rs
Yo1 = 0 Ro1 =
1 = ∞. Yo1
404
Electronic Devices and Circuits
Rs1 = R′o1 = Ro1//RC = 5 kΩ. Yo =
Ro =
(1 + hfe ) hie + Rs1
=
101 = 0.0166 mhos 1100 + 5000
1 1 = = 60.24 Ω. Yo 0.0166
Example 8.9 For the amplifier shown in Figure 8.48, calculate Ri1, AV1, Ro1, AI2, Ri2, AV2, Ro2, Ri, AV, and AV . The transistors have hfe = 100, hrc = 1, hie = 1 kΩ, hoe = hre = 0. R1 = R2 = 100 kΩ, RE = 5 kΩ, R3 = 150 kΩ, RC = 5 kΩ, Rs = 1 kΩ, and R4 = 30 kΩ. s
VCC
RC R3
R1 1
+
Cc Rs
Cc
+ Vs
R2
Vo
Cc R4
RE
RE
CE
−
Figure 8.48 The CC–CE amplifier
Solution: The simplified ac circuit of Figure 8.48 is shown in Figure 8.49.
1
+
Rs RC V o
+ Vs
R
RL
−
Figure 8.49 Simplified circuit of Figure 8.48
R = R1 / / R2 =
R2 R2 100 × 100 = = 50 kΩ R1 + R2 100 + 100
RL = RE / / R3 / / R4 =
5 × 150 × 30 = 4.17 kΩ 5 × 150 + 150 × 30 + 30 × 5
Multistage Amplifiers
(i) Secondstage CE amplifier: AI2 = −hfe = −100, since hoe = 0 Ri 2 = hie = 1 kΩ , since hre = 0
AV 2 = AI 2 ×
RC 5 = −100 × = −500 Ri 2 1
(ii) Firststage CC amplifier: AI1 = −hfc = (1 + hfe ) = 101
R i1 = hie + AI1RL = 1× 101× 4.17 = 422.17 kΩ
AV1 = AI1 ×
RL 4.17 = 101× = 0.998 Ri1 422.17
Rs1 = Rs / / R =
Ro1 =
RRs 1 × 50 = = 0.98 kΩ R + Rs 1 + 50
Rs1 + hie 0.98 + 1 = = 0.02 kΩ 1 + hfe 1 + 100
Ro2 = ∞
Ri = Ri1 / / R =
RRi1 50 × 422.17 = = 44.71 kΩ R + Ri1 50 + 422.17
AV = AV1AV 2 = 0.998 × −500 = −499
AV = AV s
Ri 44.71 = −499 × = −488.08 Ri + Rs 44.71 + 1
405
406
Electronic Devices and Circuits
Example 8.10 For the circuit shown in Figure 8.50, calculate Ri, AV, AV , and Ro, given that hfe = 100, hie = 1 kΩ, and hoe = hre = 0. s
VCC
10
500
Rc1
Re2
Rs 1 Q2
Q1
+ + Vs
5
Re1
Vo
Rc2
500
Figure 8.50 A twostage amplifier
Solution: Q2 is a PNP transistor, connected upside down. If Q2 is replaced by an NPN trans istor, the ac circuit is as shown in Figure 8.51. Each stage is a CE amplifier with unbypassed emitter resistance. Rs 1 Q1
Vi
+ Vs
Re1 500
+
Q2
+
10
Rc1
500
Re2
5 Rc2
Vo
− Ri2
Ri1
Figure 8.51 The ac circuit of Figure 8.50
(i) Second stage: AI 2 = −hfe = −100 Ri 2 = hie + (1 + hfe ) Re 2 = 1 + (1 + 100 )(0.5) = 51.5 kΩ
AV 2 = AI 2
Rc 2 5 = −100 × = −9.71 Ri 2 51.5
Multistage Amplifiers
407
(ii) First stage: Rc1Ri 2 10 × 51.5 = 8.37 kΩ = Rc1 + Ri 2 10 + 51.5
RL = Rc1 / / Ri 2 =
AI1 = −hfe = −100 Ri1 = hie + (1 + hfe ) Re1 = 1 + (1 + 100 )(0.5) = 51.5 kΩ
AV1 = AI1
RL 8.37 = −100 × = −16.25 Ri1 51.5
AV = AV1AV 2 = ( −16.25) ( −9.71) = 157.79
AV = AV s
Ri1 51.5 = 157.79 = 154.78 Ri1 + Rs 51.5 + 1
Ro ′ = Rc 2 = 5 kΩ
Example 8.11 For the amplifier circuit shown in Figure 8.52, calculate Ri, AV, AV , and Ro ′ , given that hfe = 100, hie = 1 kΩ, and hoe = hre = 0. s
VCC 5
Re1
5
Rc2 Rs 1 Q2
Q1
+ Vs
Re2 500
Figure 8.52 A twostage amplifier
+
Vo
408
Electronic Devices and Circuits
Solution: Q1 is a PNP transistor, connected upside down. If Q1 is replaced by an NPN transistor, the first stage can be seen as a CC amplifier. The second stage is a CE amplifier with unbypassed emitter resistance. The ac circuit of the twostage amplifier is shown in Figure 8.53. Rs 1 Q1 Q2
+ + Vs
+
Vi
5 Rc2
Re1 500
5
Vo
Re2
− Ri1
Ri2
Figure 8.53 AC circuit of Figure 8.52
(i) Second stage: AI 2 = −hfe = −100 Ri 2 = hie + (1 + hfe ) Re2 = 1 + (1 + 100 )(0.5) = 51.5 kΩ AV2 = AI 2
Rc2 5 = −100 × = −9.71 Ri2 51.5
(ii) First stage: RL = Re1 / / Ri 2 =
Re1Ri2 5 × 51.5 = 4.56 kΩ = Re1 + Ri2 5 + 51.5
AI1 = −hfc = 1 + hfe = 101 Ri1 = hie + (1 + hfe ) Re1 = 1 + (1 + 100 )( 5 ) = 506 kΩ
AV1 = AI1
RL 4.56 = 101 × = 0.91 Ri1 506
AV = AV1AV 2 = ( −9.71)(0.91) = −8.84
AV = AV s
Ri1 506 = −8.84 × = −8.82 Ri1 + RS 506 + 1
Ro ′ = Rc 2 = 5 kΩ
Multistage Amplifiers
409
Example 8.12 For the amplifier circuit shown in Figure 8.54, calculate Ri, AV, AV and Ro ′ , given that hfe = 100, hie = 1 kΩ, and hoe = hre = 0. s
VCC 5 10 200
Rc1
Rc2
R′
Rs 1
+
Q2
Q1
+ Vs
Re2
Re1
Vo
500
500
Figure 8.54 Twostage amplifier
Solution: In the firststage compound feedback is used. Using Miller’s theorem, R′ can be replaced by R1 and R2 appearing in shunt with the input and the output terminals of Q1. The ac circuit is as shown in Figure 8.55 Rs 1 Q2
Q1 +
+ 5
Vs R1
Ri
Re1 500
Ri1
Rc1 10
Re2
R2
Rc2
Vo
500
Ri2
Figure 8.55 AC circuit of Figure 8.54
R1 =
R′ and R2 ≈ R′ = 200 kΩ 1 − AV1
(i) Second stage: AI 2 = −hfe = −100 Ri 2 = hie + (1 + hfe ) Re 2 = 1 + 1(1 + 100 )( 0.5 ) = 51.5 kΩ
410
Electronic Devices and Circuits
Rc 2 5 = −100 × = −9.71 Ri 2 51.5
AV 2 = AI 2
(ii) First stage R L = Rc1  R2  Ri 2 = 200//10//51.5 = 8.03 kΩ. AI1 = −hfe = −100 Ri1 = hie + (1 + hfe ) Re1 = 1 + (1 + 100 )( 0.5 ) = 51.5 kΩ
AV1 = AI1
RL 8.03 = −100 × = −15.59 Ri1 51.5
AV = AV1AV 2 = ( −9.71) ( −15.59 ) = 151.38 R1 =
200 R′ = = 12.05 kΩ 1 − AV1 1 + 15.59
Ri = R1 / / Ri1 = 12.05 / /51.5 = 9.765 kΩ AVs = AV
Ri 9.765 = 151.38 × = −137.32 Ri + Rs 9.765 + 1
Ro ′ = Rc 2 = 5 kΩ Example 8.13 For the bootstrap emitter follower shown in Figure 8.56, calculate Ri and AV, given that hfe = 1000, hie = 1 kΩ, and hoe = hre = 0. R1 = R2 = R3 = 10 kΩ, RE = 5 kΩ VCC R1 Q
X
+
Darlington transistor
Y +
R3 Vi R2 CB
Vo
RE −
Figure 8.56 The bootstrapped emitter follower
Multistage Amplifiers
411
Solution: The ac circuit is shown in Figure 8.57. R3 appears between the input and the output. Using the Miller’s theorem, the circuit in Figure 8.57 is drawn as in Figure 8.58 Q
X
+
Y +
R3
Vi
R2
R1
Vo
RE −
Figure 8.57 AC circuit of Figure 8.56
X
Q
+
Y + Rx
Vi
RY
RL
Vo −
Ri
R′i
Figure 8.58 Input and output circuits using the Miller’s theorem
RX =
Therefore,
R3 RA and RY = 3 V ≈ ∞ AV − 1 1 − AV
RL = RE / / R1 / / R2 =
5 × 10 × 10 = 2.5 kΩ 5 × 10 + 10 × 10 + 5 × 10
AI = − hfc = 1 + hfe = 1 + 1000 = 1001 Ri ′ = hie + (1 + hfe ) RL = 1 + 1001× 2.5 = 2503.5 kΩ
Alternately,
AV = AI
RL 2.5 = 1001× = 0.9996 Ri ′ 2503.5
AV = 1 −
hie 1 = 1− = 0.9996 Ri ′ 2503.5
RX =
R3 10 = = 25 MΩ 1 − AV 1 − 0.9996
Ri = Ri ′ / / RX =
2503.5 × 25000 = 2.27 MΩ 2503.5 + 25000
(since AV ≈ 1)
412
Electronic Devices and Circuits
Example 8.14 For the amplifier shown in Figure 8.59, calculate AV and Ri, hfc = −101 , hie = 1 kΩ, hoe = 0, and hrc = 1. RE = 5 kΩ VCC Ib1 Q1 +
Ib2 Q2 +
+
+ Vi2 Vo
Io
Vs
− Ri2
Figure 8.59 The Darlington emitter follower (CC–CC amplifier)
Solution: The ac circuit is shown in Figure 8.60.
Q1 Q2
+ Vs
+ + Vo1 = Vi2
Ri2
RE
Vo −
Figure 8.60 The ac circuit of Figure 8.59
(i) Second stage AI 2 = −hfc = 1 + hfe = 1 + 100 = 101 Ri 2 = hie + (1 + hfe ) RE = 1 + 101× 5 = 506 kΩ . AV 2 = AI2
RE 5 = 101 × = 0.998 Ri 2 506
Multistage Amplifiers
413
(ii) First stage: AI1 = −hfc = 1 + hfe = 1 + 100 = 101 Ri1 = hie + (1 + hfe ) Ri 2 = 1 + 101 × 506 = 51.11 MΩ. AV1 = AI1
Ri 2 506 =1 = 101× Ri1 51110
AV = AV1AV 2 = 0.998 × 1 = 0.998
Example 8.15 It is required that the voltage gain of an RC coupled amplifier should not decrease by more than 10 percent of its midband gain at 100 Hz. Choose the proper value of Cc. The circuit has RC = 1 kΩ and the transistor has hie = 1 kΩ Solution:
Al = Am
1 f 1+ 1 f
2
It is desired that at f = 100 Hz,
2
1
Therefore,
f 1+ 1 f f1 = 0.48 f
AL = 0.9 Am
2
= 0.9
or
f1 = 0.48 × f
For the RCcoupled amplifier, f1 =
Therefore, Cc =
f 1 1+ 1 = = 1.23 f 0.81
2
f1 f = 0.23
f1 = 0.48 × 100 = 48 Hz.
1 2pCc (RC + hie )
or
1 1 = = 1.66 mF 2pf1 (RC + hie ) 2p × 48 × (1 + 1)103
Cc =
1 2pf1 (RC + hie )
414
Electronic Devices and Circuits
Example 8.16 The lower and the upper halfpower frequencies of an RCcoupled amplifier are 50 Hz and 50 kHz, respectively. Calculate the frequenceis act range over which the gain falls by 10 percent of its midband gain. Solution: Given f1 = 50 Hz and f2 = 50 kHz Al = Am
We have,
At f,
f 1+ 1 f
2
Al = 0.9 Am 2
f 1 = 1.11 1+ 1 = f 0.9
1
∴ 0.9 =
f 1+ 1 f
2
2
f1 f = 0.23
We have
At f ′,
1
Ah = Am
f1 = 0.48 f
f =
2
f 1 + 1 = 1.23 f
f1 50 = = 104.16 Hz 0.48 0.48
1 f 1+ f2
2
Ah = 0.9 Am 2
1
∴ 0.9 =
f ′ 1+ f2 2
f ′ f = 0.23 2
2
f′ = 0.48 f2
f ′ 1 1+ = = 1.11 0.9 f2
2
f ′ 1 + = 1.23 f2
f ′ = 0.48 f2 = 0.48 × 50 = 24 kHz
The frequencies at which Am falls by 10 percent are 104.16 Hz and 24 kHz
Multistage Amplifiers
415
Example 8.17 For the amplifier circuit shown in Figure 8.61, find the midband gain and the value of Cc needed to give a lower halfpower frequency of 50 Hz. The transistor has hfe = 100 and hie = 1 kΩ. CE is large. hre = hoe = 0
VCC
5 60
RC1
10 60
R1
RC2
R3 +
Cc
Cc
+
10 Vi
60
R2
CE
RE
R5
60 R4 RE
Vo
CE
Figure 8.61 Twostage CE–CE amplifier
Solution: The ac circuit of Figure 8.61 is shown in Figure 8.62. R6 = R7 = 60//60 = 30 kΩ
+ +
RC2 Vi
5 30
R6
RC1
R5
10
30
10
Vo
R7
Ril
Ri2
Figure 8.62 The ac circuit of Figure 8.61 in the midband
From Figure 8.29, RL 2 = 10 / /10 = 5 kΩ R7 = R3 / / R4 = 60 / / 60 = 30 kΩ R4
=
kΩ
R8 = R7 / / R c1 = 30 / / 5 = 4.29 kΩ
R8 =
kΩ
416
Electronic Devices and Circuits
The simplified Ac circuit is drawn in Figure 8.63.
4.29 Vi
30
+
Q2
Q1
+
5
RL2
Vo
R8
R6
Ril
Ri2
Figure 8.63 Simplified circuit of Figure 8.62
(i) Second stage: RL 2 = 5 kΩ AI 2 = −hfe = −100 Ri 2 = hie = 1 kΩ AV 2 = AI 2 ×
RL 2 5 = −100 × = −500 Ri 2 1
(ii) First stage: AI1 = −hfe = −100 and Ri1 = hie = 1 kΩ RL1 = Ri 2 / / R8 = 1 / /4.29 = AV1 = AI1 ×
1 × 4.29 = 0.81 kΩ 1 + 4.29
RL1 0.81 = −81 = −100 × Ri1 1
AV = AV1AV 2 = −81 × −500 = 40500 For the RCcoupled amplifier, f1 =
Therefore,
Cc =
1 1 or Cc = 2pCc (RL1 + hie ) 2pf1 (RL1 + hie )
1 1 = = 1.76 µF 2pf1 (RL1 + hie ) 2p × 50 × (0.81 + 1)103
Example 8.18 A threestage noninteracting RCcoupled amplifier has an overall gain less by 0.3 dB at 50 kHz, when compared to the midband gain. Calculate f2 of the individual stages. Solution: Given,
Ah = −0.3 dB, f = 50 kHz and n = 3. Am
Multistage Amplifiers
417
We have, Ah = Am
20 log
Ah = 20 log Am
1 f 1+ ∗ f2
2
1 f 1+ ∗ f2
2
2
f 20 log 1 + ∗ = 0.3 f2
= −0.3
2
2
f 0.3 log 1 + ∗ = = 0.015 20 f2 2
f 1 + ∗ = 1.071 f2
f 1 + ∗ = 1.035 f2
2
f f ∗ = 0.071 2 1
f2∗ = f2 2 n − 1
f2 =
f = 0.266 f2∗ f2∗
f2∗ =
187.97 =
1 n
2 −1
=
1 3
f 50 = 187.97 kHz = 0.266 0.266
187.97 = 368.57 kHz 0.51
2 −1
1 = 40k = hoe and hfe = 50. Calculate (i) the lower 3 dB frequency and (ii) the frequency f at which the midband gain falls to 12 dB. Example 8.19 For the RCcoupled amplifier shown in Figure 8.64, Cc = 5 µF, hie = 1 kΩ,=
VCC
3
RC1 50
R1
Cc
+
+ 5 Vi
R2
Vo
Ri2 = hie
RE CE −
−
Second stage
Figure 8.64 Singlestage RCcoupled amplifier
418
Electronic Devices and Circuits
Solution: The ac circuit of the singlestage amplifier is drawn in Figure 8.65, and its simplified circuit is shown in Figure 8.66. Ib Cc
+ Vi
hfeIb
hie
1/hoe
50
RC1
+
5
hie
3
Vo
R2
R1
= 40
−
−
Figure 8.65 The ac circuit of Figure 8.64
R=
1 / / RC1 = 40 / /3 = 2.8 kΩ hoe
RL = R1 / / R2 / / hie = 50 / /5 / /1 = 0.82 kΩ Ib
Ib Cc
+ Vi
hfeIb
hie
R RL
+
+
Vo
Vi
R
Cc
+ hie
−
hfeIbR +
−
Figure 8.66 Simplified lowfrequency circuit of Figure 8.65
(i) Comparing Fig 8.66 with Fig 8.29 and using Eqn. 8.24 f1 =
1 1 = = 8.8 Hz . 2pCc (R + RL ) 2 π × 5 × 10 −6 (2.8 + 0.82 ) × 103
(ii) The midband equivalent circuit is shown in Figure 8.67. Ib + Vi
+ hie
hfeIb
¢ RL
Vo −
−
Figure 8.67 The midband equivalent circuit
RL ′ = RL / / R
RL
Vo
Multistage Amplifiers
419
We have, 20 log
∴
Al = 12 Am
1 f 1+ 1 f
2
f 1 1+ 1 = 0.251 f
2
2
Al = 0.251 Am
= 0.251
2
f1 f = 14.84
f1 = 3.85 f
f =
f1 8.8 = = 2.29 Hz 3.85 3.85
Example 8.20 An nstage FET amplifier has FETs having gm = 2 mA/V , rd = 50 kΩ , RD = 10 kΩ, RG = 100 kΩ, and Cc = 0.005 µF . CS is very large. Calculate (i) the midband gain, when, n = 1, 2, 3, and 4 as a dimensionless quantity and also in dB (ii) f1 of a single stage and (iii) the lower halfpower frequency f1∗ when n = 2, 3, and 4. Solution: (i) (a) The midband gain of a single stage, that is when n = 1, is 50 × 10 / /100 = 8.33 / /1000 = 7.69 kΩ Am = − gm RL where RL = (rd / / RD ) / / RG = 50 + 10 ∴ Am = − gm RL = −2 × 7.69 = −15.38 Am ( in dB ) = 20 log (15.38 ) = 23.74 dB. (b) When n = 2, Am = Am1Am 2 = 15.38 × 15.38 = 236.54 Am ( in dB ) = 20 log ( 236.54 ) = 47.48 dB. Or alternatively Am ( in dB) = 2 × 23.74 = 47.48 dB
(c) When n = 3, Am = Am1Am 2 Am 3 = 15.38 × 15.38 × 15.38 = 3637.99 Am ( in dB ) = 20 log ( 3637.99 ) = 71.22 dB Or alternatively, Am ( in dB ) = 3 × 23.74 = 71.22 dB (d) When n = 4, Am = Am1Am 2 Am 3 Am 4 = 15.38 × 15.38 × 15.38 × 15.38 = 55952.29 Am ( in dB ) = 20 log ( 559952.29 ) = 94.96 dB
420
Electronic Devices and Circuits
Or alternatively, Am ( in dB ) = 4 × 23.74 = 94.96 dB (ii) The load for the single stage is RL ≈ rd / / RD =
50 × 10 = 8.33 kΩ 50 + 10
Ri = 100 kΩ f1 =
1 1 = 293.98 Hz = −6 2pCc (RL + Ri ) 2p × 0.005 × 10 (8.33 + 100 ) × 103
(iii) The lower halfpower frequency of the cascaded amplifier is given as follows: f1
f1∗ =
1
2n −1 (a) For n = 2, f1∗ =
f1
293.98 =
1
1
2n −1 (b) For n = 3, f1∗ =
f1
293.98 =
1 n
f1 1 n
2 −1
= 1.414 − 1
22 −1
293.98 =
1 3
2 −1 (c) For n = 4, f1∗ =
293.98 =
= 1.26 − 1
293.98 = 457.20 Hz 0.643
293.98 = 576.43 Hz 0.51
2 −1 293.98 =
293.98 =
1 4
= 1.189 − 1
293.98 = 675.82 Hz 0.435
2 −1
Summary • Cascading of amplifiers influences the performance quantities of the compound amplifier configuration. • A CE–CC amplifier gives a larger output for the same given input compared to a single CE amplifier. • A CE–CC amplifier has medium Ri , large AV , and small Ro . • A CE–CE amplifier has a large AI and large AV . • A CE–CB (cascode) amplifier has large AV and minimizes Miller effect. • A Darlington emitter follower (CC–CC amplifier) gives a large Ri . It is possible to use bootstrapping technique for making Ri very large. • The midband gain of an RCcoupled amplifier is constant, whereas the lowfrequency and the highfrequency gains tend to become poor due to Cc and Cs , respectively. • A transformercoupled amplifier is not preferably used in the lowfrequency range (audio frequency range) mainly because of the size of the transformer. • Directcoupled amplifiers have flat frequency response characteristic right from 0 Hertz. • Drift is a major problem in directcoupled amplifiers.
Multistage Amplifiers
421
multiple ChoiCe QueStionS 1. The following compound amplifier has the highest AI and large AV (a) CE–CE (c) CE–CB
(b) CE–CC (d) CC–CC
2. A Cascode amplifier is a cascaded (a) CE–CE amplifier (c) CE–CB amplifier
(b) CE–CC amplifier (d) CB–CE amplifier
3. The advantage of a cascode amplifier is that it (a) minimizes Miller effect (c) gives small Ro
(b) gives large Ri (d) none of these
4. The effective Ri of a Darlington emitter follower is reduced by the biasing resistors. The following procedure is used to make the effective Ri very large: (a) Negative feedback is used. (b) Positive feedback is used. (c) Bootstrapping is used. (d) Negative resistance device is used. 5. The midband gain of an RCcoupled amplifier (a) increases linearly with frequency (b) decreases linearly with frequency (c) remains constant (d) none of these 6. The lowfrequency gain of an RCcoupled amplifier tends to become poor due to (a) Cc (b) Cs (c) hfe (d) hie 7. The highfrequency gain of an RCcoupled amplifier tends to become poor due to (a) Cc (b) Cs (c) hfe (d) hie 8. The major problem in dc amplifiers is (a) drift (c) small gain
(b) biasing (d) large gain
9. A transformercoupled amplifier is usually not preferred in the audio frequency range because (a) the gain becomes very large (b) the gain becomes very small (c) the transformer becomes bulky (d) the transformer has no weight 10. Three identical, noninteracting CE amplifiers are cascaded, each having a gain of 10. The overall gain is (a) 10 (b) 100 (c) 1000 (d) 10000
422
Electronic Devices and Circuits
Short anSwer QueStionS Where is the need for cascaded amplifiers? What are the different types of interstage coupling techniques used in multistage amplifiers? How is the midband range in an RCcoupled amplifier defined as? What is meant by bootstrapping? What is Miller effect? What are the two main advantages of a cascode amplifier? What is the advantage of a Darlington transistor? Why is a Darlington transistor preferably used in an emitter follower? In a threestage CE amplifier, what will be the bandwidth when bandwidth of the singlestage amplifier is f2? 10. What is drift in dc amplifiers? 1. 2. 3. 4. 5. 6. 7. 8. 9.
long anSwer QueStionS For a CE–CC amplifier derive the expressions for AV , Ri , and Ro . For a CE–CB amplifier derive the expressions for AV , Ri, and Ro . For a CC–CC amplifier derive the expressions for AV, Ri, and Ro. Draw the ac circuit of a singlestage RCcoupled amplifier and derive the expressions for Am , Al , and Ah using the approximate model for the transistor. 5. Derive the expression for the lowfrequency gain of a CE amplifier in which CE is not an effective bypass condenser. 1. 2. 3. 4.
unSolved problemS 1. For the Darlington emitter follower shown in Figure 8.15, Rs = RE = 1 kΩ, hie = 1.1 kΩ, hfe = 100, and hre = hoe = 0. Find Ri, AI, AV, and Ro. 2. For the amplifier circuit shown in Figure 8.68, hie = 1 kΩ, hfe = 50, hre = hoe = 0, RL = 4 kΩ, and Rs = 0. Calculate Ri, AV, and Ro? 3. For the circuit in Figure 8.1, hie = 1 kΩ, hfe = 100, hre = hoe = 0, RC = 4 kΩ, Rs = 1 kΩ, and RE = 2 kΩ. Find AV. VCC
Q2
RL
Q1
+
+
Vi
Vo CB
Ro2 = Ro Ri1 = Ri
Ri2
Figure 8.68 CE–CB amplifier
Multistage Amplifiers
423
4. In an RCcoupled amplifier the transistor used has hie = 1 kΩ and hfe = 50. RC = 2 kΩ. hoe = hre = 0. Find (i) The midband gain, (ii) the value of Cc required to give a lower 3 dB frequency of 20 Hz, and (iii) the value of CS required to give an upper 3 dB frequency of 100 kHz. 5. For the circuit in Figure 8.38, calculate the size of CE to provide f1 = 20 Hz, when RE = 1 kΩ, hie = 1 kΩ, and hfe = 50. VCC
5
Re1
5
Rc2 Rs 1
Q2
Q1
+ Vo + Vs
Re2 500
−
Figure 8.69 Amplifier 6. For the amplifier circuit shown in Figure 8.69, calculate AV, given that hfe = 50, hie = 1 kΩ, hoe = 0, and hrc = 1.
9
FEEDBACK AMPLIFIERS
Learning objectives After going through this chapter the reader will be able to
9.1
Understand the need for feedback in an amplifier Realize the four basic feedback amplifier topologies Appreciate the advantages when negative feedback is used in an amplifier Derive the expressions for the performance quantities of the feedback amplifiers Analyze voltage series, current series, voltage shunt and current shunt feedback amplifiers
INTRODUCTION
The analysis of voltage amplifiers is considered in Chapter 6. Then, it is known that the gain of a singlestage amplifier, say a CE amplifier, depends not only on the external circuit components provided in the circuit but also on the device parameters. The voltage gain of a CE amplifier is given by the following expression: A = AI
RL Ri
Here, AI is the current gain and RL and Ri are the load and input resistances, respectively. Using the approximate model for the transistor and assuming Rs = 0, A = − hfe (RL hie ) . If for the given transistor hfe = 100, hie = 1.1 kΩ, and RL = 2.2 kΩ, then A = −100 × (2.2 1.1) = −200 ; and if Vi = 1 mV , then Vo = AVi = 200 × 1 = 200 mV . The minus sign accounts for phase inversion in a CE amplifier. If the transistor used has been replaced by an identical transistor or if the transistor has been used for a relatively long time, which is referred to as aging, there is a possiblility that the parameters of the device may not be the same as that of the earlier used device. Further, it is noted that temperature variations can cause a change in the device parameters. Now assume that due to any of these reasons hfe has increased to 110, then A = −110 × (2.2 1.1) = −220 . And once again if Vi = 1 mV , then Vo = AVi = 220 × 1 = 220 mV . The output has now increased by 10 percent. In practice, the gain of the amplifier is required to remain unchanged mostly against temperature variations. In order to meet this objective, feedback must be used in the amplifier.
Feedback Amplifiers
425
Therefore, the feedback is essentially used in an amplifier to stabilize the gain. In a feedback amplifier, the output is sampled to see if it has changed from the desired value or not. If it has changed, either increased or decreased, then a corrective mechanism must be used at the input so as to bring back the output once again to the desired value by taking a part of the output to the input through a feedback network.
9.2 THE FEEDBACK AMPLIFIER The basic feedback amplifier is shown in Figure 9.1. The feedback amplifier basically consists of an internal amplifier whose gain A is required to be stabilized. The sampling network samples the output. If the output changes, a small fraction of the output is fed back to the input in phase opposition to the already available input Vs . The difference of Vs and Vf , which is Vi is fed as input to the internal amplifier.
RS +
Mixing network
Vs
+
Vi
Internal ampliﬁer A
Sampling network
+ Vo
RL
+ Vf
Feedback or bnetwork b
Figure 9.1 Feedback amplifier
If for some reason or the other Vo increases, then Vf increases. As Vi = (Vs − Vf ), Vi decreases, and hence Vo is brought back to the original value. Alternately, if Vo decreases, then Vf decreases and Vi increases, and hence Vo is brought back to the original value. This is the principle of a feedback amplifier. Let us now see what each of the blocks mean to us.
9.2.1 Sampling Network The purpose of a sampling network is to sense or monitor the output. The requirement of the amplifier is that the output Vo should remain unaltered despite the variations of the parameters of the device. If, for any reason, Vo changes it should be brought back to the desired value. There are two methods of sampling: (i) voltage sampling or node sampling and (ii) current sampling or loop sampling.
426
Electronic Devices and Circuits
(i) Voltage sampling or node sampling: In voltage sampling, a potential divider network comprising R1 and R2 is connected in shunt with the load. However, it must be ensured that this potential divider network is not going to change the load to the amplifier, Figure 9.2. Although the output of the bnetwork in the present case is a voltage Vf , in general it can be a current or a voltage.
Sampling network
R1 + Vf −
+ Vo
RL
+ Vo
R2 bnetwork
Figure 9.2 Voltage sampling
(ii) Current sampling or loop sampling: In current sampling the load current I o is made to flow through the bnetwork, which in turn can derive in the output a current or a voltage as shown in Figure 9.3.
Sampling network
+ Vo
RL
Io
bnetwork
Figure 9.3 Current sampling
9.2.2 bNetwork Having sampled the output, a small fraction of the output is taken to the input and connected at the input in such a way that if the output is increased, the actual input to the amplifier is decreased, thereby once again bringing back the output to the desired value and vice versa. The network that derives the feedback signal is called the bnetwork or feedback network. As mentioned earlier, the output of the bnetwork can either be a voltage or a current that is derived either by sampling the output voltage or output current.
Feedback Amplifiers
427
9.2.3 Mixing Network The output of the bnetwork is connected at the input such that the output of the amplifier is brought back to the desired value, if it changes. There are basically two methods of mixing: (i) series and (ii) shunt. (i) Series mixing: In this method, the output of the bnetwork is connected in series with the input signal. When it is said that series mixing is used at the input, it obviously means that the output of the bnetwork is a voltage and the driving source is a voltage (Thévenin’s) source as shown in Figure 9.4).
+
+ Vi −
Vs −
− V + f
Internal ampliﬁer A
Feedback or bnetwork b
Figure 9.4 Series mixing
(ii) Shunt mixing: In this method, the output of the bnetwork is connected in shunt with the input signal. When it is said that shunt mixing is used at the input, it obviously means that the output of the bnetwork is a current and the driving source is a current (Norton) source as shown in Figure 9.5. Ii
Is
If
Internal ampliﬁer A
Feedback or bnetwork b
Figure 9.5 Shunt mixing
Hitherto, we have seen that either series mixing or shunt mixing can be used at the input and voltage, or current sampling can be used at the output. Based on how the signal is sampled at the output and how it is mixed at the input, amplifiers are classified into four basic feedback amplifier topologies: (i) voltage series feedback amplifier, (ii) current series feedback amplifier, (iii) voltage shunt feedback amplifier, and (iv) current shunt feedback amplifier. From the above classification, it is evident that the first term represents the type of sampling, whereas the second term represents the type of mixing. The four feedback amplifiers are schematically represented in Figure 9.6.
428
Electronic Devices and Circuits
+ Vs −
− V + f
+ Vi −
Internal ampliﬁer A
+
Vo
RL
+ Vs −
− V + f
+ Vi −
+
Internal ampliﬁer A
Vo RL
Io Feedback or bnetwork b
Feedback or bnetwork b
(a) Voltage series feedback ampliﬁer
(b) Current series feedback ampliﬁer Ii
Ii
Is
If
Internal ampliﬁer A
+
V RL o
Is
If
Feedback or bnetwork b
Internal ampliﬁer A
+
Feedback or bnetwork b
(c) Voltage shunt feedback ampliﬁer
V RL o
Io
(d) Current shunt feedback ampliﬁer
Figure 9.6 Feedback amplifier topologies
9.3
CALCULATION OF THE GAIN OF THE FEEDBACK AMPLIFIER
(i) Consider the voltage series feedback amplifier shown in Figure 9.7 The gain with feedback is calculated as follows: Vo Vs
(9.1)
Vo or Vo = AVVi Vi
(9.2)
Vs = Vi + Vf
(9.3)
Vf = bVo
(9.4)
Vs = Vi + bVo
(9.5)
AV = f
AV, the gain of the internal amplifier is AV = From Figure 9.7,
and
Substituting Eqn. (9.4) in Eqn. (9.3),
Feedback Amplifiers
429
Using Eqs (9.5) and (9.2), Eqn. (9.1) is written as follows: AV = f
Vo AVVi AV = = Vs (Vi + bAVVi ) 1 + bAV
+ Vs −
+ Vi
AV
bV o
b
− Vf +
(9.6)
+ Vo −
RL
Figure 9.7 Voltage series feedback amplifier
It can be seen from Eqn. (9.6) that the gain of a feedback amplifier is the ratio of gain without feedback AV and (1+ AV b ) . (ii) Now consider the current series feedback amplifier shown in Figure 9.8. + Vs −
+ Vi
GM
bIo
b
Io
RL
− V + f
Figure 9.8 Current series feedback amplifier
In this amplifier, it can be seen that the input is a voltage Vs and the desired output signal is a current I o . The ratio of this output current I o to input voltage Vs is called the transconductance gain. The transconductance gain without feedback is GM and that with feedback is GMf . The gain with feedback is calculated as follows: Io Vs
(9.7)
Io or I o = GMVi Vi
(9.8)
GM = f
GM the gain of the internal amplifier is GM =
430
Electronic Devices and Circuits
From Figure 9.8, Vs = Vi + Vf
(9.9)
Vf = bI o
(9.10)
Vs = Vi + bI o
(9.11)
and
Substituting Eqn. (9.10) in Eqn. (9.9),
Using Eqs (9.11) and (9.8), Eqn. (9.7) is written as follows: GM = f
Io GMVi GM = = Vs (Vi + bGMVi ) 1 + bGM
(9.12)
(iii) Consider the circuit in Figure 9.9. Ii Is
If
RM
+ Vo −
RL
b
Figure 9.9 Voltage shunt feedback amplifier
In this amplifier, it can be noted that the input is a current I s , and the desired output signal is a voltage Vo . The ratio of this output voltage Vo to input current I s is called the transresistance gain. The transresistance gain without feedback is RM and that with feedback is RMf . The gain with feedback is calculated as Vo Is
(9.13)
Vo or Vo = RM I i Ii
(9.14)
Is = I i + If
(9.15)
I f = bVo
(9.16)
RM = f
RM, the gain of the internal amplifier is RM = From Figure 9.9,
and
Feedback Amplifiers
431
Substituting Eqn. (9.16) in Eqn. (9.15), I s = I i + bVo
(9.17)
Using Eqs (9.17) and (9.14), Eqn. (9.13) is written as follows: RM = f
Vo RM I i RM = = I s ( I i + bRM I i ) 1 + bRM
(9.18)
(iv) Consider Figure 9.10 Ii Is
If
Io
AI
RL
b
Figure 9.10 Current shunt feedback amplifier
In this amplifier, it can be noted that the input is a current I s and the desired output signal is a current I o. The ratio of this output current I o to input current I s is called the current gain. The current gain without feedback is AI and that with feedback is AI . f
The current gain with feedback is calculated as follows: Io Is
(9.19)
Io or I o = AI I i Ii
(9.20)
Is = I i + If
(9.21)
I f = bI o
(9.22)
I s = I i + bI o
(9.23)
AI = f
AI , the gain of the internal amplifier is AI = From Figure 9.10,
and
Substituting Eqn. (9.22) in Eqn. (9.21),
432
Electronic Devices and Circuits
Using Eqs (9.23) and (9.20), Eqn. (9.19) is written as follows: AI = f
Io AI I i AI = = I s ( I i + bAI I i ) 1 + bAI
(9.24)
In general, the expression for the gain of a feedback amplifier can be written as follows: Af =
A 1 + Ab
(9.25)
where Af can be AVf , GMf , RMf , or AIf , and A can be AV , GM , RM , or AI , depending on the topology. Therefore, it is obvious that to calculate the gain with feedback, it is necessary to calculate the gain without feedback and b . From Eqn. (9.25), (i) If (1 + Ab ) > 1, then Af < A. If the gain with feedback is smaller than the gain without feedback, then negative or degenerative feedback is said to be used in the amplifier. (ii) If (1 + Ab ) < 1, then Af > A. If the gain with feedback is greater than the gain without feedback, then positive or regenerative feedback is said to be used in the amplifier. 1 (iii) If Ab >> 1, then Af = . This condition says that the gain of the feedback amplifier is b inversely proportional to b. The gain is independent of temperature variable parameters and is solely decided by the bnetwork. As long as the bnetwork is stable, the gain of the feedback amplifier is stable, which is the obvious requirement. Further, the frequency response characteristic of the amplifier is the inverse frequency response characteristic of the bnetwork. Thus, it is possible to get the desired frequency response characteristic for the amplifier by choosing a bnetwork that has the desired inverse frequency response characteristic. Vo = ∞. As Af → ∞, Vs → 0. This means that the amplifier gives a Vs finite output even with zero input. Such an amplifier is called an oscillator (Figure 9.11). Thus, we see that if the condition (1 + Ab ) = 0 is satisfied in an amplifier, then the amplifier is called an oscillator and the condition (1 + Ab ) = 0 is called Barkhausen criterion. We consider oscillators in Chapter 10.
(iv) If (1 + Ab ) = 0, then Af =
Vs = 0
+ Vi
AV
bV o
b
− Vf +
Figure 9.11 Feedback oscillator
Load
Feedback Amplifiers
433
When we consider an amplifier, our main concern is the stability of gain. An amplifier in which negative feedback is used ensures better gain stability. The amount of negative feedback used in an amplifier is defined as the ratio of the power output without feedback to power output with feedback, for the same input and is expressed in dB. Amount of dB feedback used is 10 log10 Power output without feedback Po =
Po for the same input. Po′
Vo 2 , where Vo is the output voltage without feedback. RL
V ′2 Power output with feedback Po′ = o , where Vo′ is the output voltage with feedback for the RL same input. V2 R V V V Amount of dB feedback used = 10 log10 o 2 L = 20 log10 o = 20 log10 o s Vo′ Vo′ Vs Vo′ RL A Amount of dB feedback used = 20 log10 = 20 log10 (1 + Ab ) Af
(9.26)
If (1 + Ab ) = 10, then amount of dB feedback used is 20 log10 10 = 20 dB. In addition to gain stability, negative feedback in an amplifier gives us a few more additional advantages.
9.4
ADVANTAGES OF NEGATIVE FEEDBACK
1 It has already been noted that large amount of negative feedback makes the gain stable Af = . b However, even if the amount of negative feedback incorporated is not large, it can be shown that negative feedback in an amplifier improves gain stability.
9.4.1 Improved Gain Stability From Eqn. (9.25), the expression for the gain of the feedback amplifier is Af =
A A = . D is 1 + Ab D
called the return difference. If there is an incremental change in the gain of the internal amplifier by dA , then the gain of the feedback amplifier changes by dAf . To find out the incremental change in gain of the feedback amplifier, we differentiate Eqn. (9.25): dAf =
(1 + Ab ) dA − AbdA = dA (1 + Ab )2 (1 + Ab )2
dAf dA 1 dA (1 + Ab ) = 2 2 = Af (1 + Ab ) Af (1 + Ab ) A
434
Electronic Devices and Circuits
dA dAf = A 1 + Ab Af
(9.27)
dAf dA is the percent change in the gain of the internal amplifier and is the percent change A Af dAf 20 dA in gain of the feedback amplifier. If is 20% and (1 + Ab ) = 10 , then = = 2%. This 10 A Af means that if the gain of the internal amplifier changes by 20 percent, then the gain of the feedback amplifier changes only by 2 percent. That is, negative feedback in an amplifier gives better gain stability.
9.4.2 Improved Bandwidth While considering an RC coupled amplifier in Chapter 8, we have derived the expressions for the gains in the highfrequency range, Ah and in the lowfrequency range, Al in terms of the gain in the midband range, Am as follows: Ah =
Am w 1+ j w2
Al =
Am w 1+ j 1 w
and
(9.28)
(9.29)
A And from Eqn. (9.25), the gain with feedback is Af = . Therefore, the highfrequency gain 1 + Ab with feedback is Ahf =
Ah 1 + Ah b
(9.30)
Substituting Eqn. (9.28) in Eqn. (9.30), Am w 1+ j w2 Am Ahf = = = Am b w 1+ 1 + Am b + j 1 + w w2 1+ j w2 Ahf =
Am′ w 1+ j w 2′
Am 1 + Am b w j (1 + Am b ) w 2
(9.31)
Feedback Amplifiers
435
where Am′ =
Am 1 + Am b
(9.32)
and w 2′ = (1 + Am b ) w 2
(9.33)
From Eqn. (9.32), it can be noted that the gain in the midband, Am is reduced to Am′ , since (1+ Am b ) is greater than 1. However, the new upper halfpower frequency w 2′ is greater than w 2 Eqn. (9.33). Once again using Eqn. (9.25), Alf =
Al 1 + Al b
(9.34)
Substituting Eqn. (9.29) in Eqn. (9.34), Am w 1+ j 1 w Am Alf = = = Am b w1 1+ 1 + Am b + j 1 + w w 1+ j 1 w Alf =
Am 1 + Am b w1 j (1 + Am b )w
Am′ w ′ 1+ j 1 w
(9.35)
where w1′ =
w1 1 + Am b
(9.36)
Gain Am 0.707 Am Am′ 0.707 Am′
ω1′
ω1
ω2
ω2′
ω
Figure 9.12 Frequency response characteristics with and without feedback
From Eqn. (9.35), it can be noted that the gain in the midband, Am is reduced to Am′ , since (1+ Am b ) is greater than 1, and the new lower halfpower frequency w1′ is smaller than w1 as shown in Eqn. (9.36). Now, let us look at the frequency response characteristics of the amplifier with and without feedback, Figure 9.12. w1 and w1′ are small when compared to w 2 and w 2′ .
436
Electronic Devices and Circuits
Therefore, w 2 and w 2′ are practically the bandwidths of the amplifiers without and with feedback. Taking the product of the gain and bandwidth of the amplifier with feedback, using Eqs (9.32) and (9.33), we have, Am (1 + Am b )w 2 = Amw 2 (1 + Am b )
Gain × bandwidth = Am′ w 2′ =
(9.37)
Equation (9.37) shows that the gain bandwidth product with feedback is the same as the gain bandwidth product without feedback. Hence, it can be said that the gain bandwidth product of an RCcoupled amplifier is constant.
9.4.3 Reduced Harmonic Distortion We have already noted, while considering small signal and large signal amplifiers, that harmonic distortion can be present in the output of an amplifier, if the operation is not restricted to a limited region in the transfer characteristic, in which region the characteristic can be approximated by a straight line. Thus, if the input swing is large, the harmonic distortion can be present in the output of a voltage amplifier, which is unwanted. It was noted earlier that ic = Bo + B1 cos wt + B2 cos 2wt + B3 cos 3wt + ... where B1 is the magnitude of the fundamental, and B2 , B3, B4 , etc., are the magnitudes of the harmonics. We now show that negative feedback in an amplifier reduces harmonic distortion. Let us now consider an amplifier without feedback in which harmonic distortion is present, Fig. 9.13(a) + Vs −
+
Vh
A
− Vo
+ RL −
+
+ V′s − +
Vf
(a) Ampliﬁer without feedback
+ Vi − −
Vh
A
− RL
+ Vo = V′o −
(b) Ampliﬁer with feedback
Figure 9.13 Harmonic distortion in an amplifier
From Figure 9.13(a), Vo = AVs + Vh
(9.38)
But when feedback is used in an amplifier, Fig. 9.13(b) the output is no longer Vo , but is Vo′ which is smaller than Vo . Obviously, the harmonic component in the output becomes small. However, to make a realistic comparison, the output with feedback should also be made equal to the output without feedback (Vo = Vo′), and then the harmonic components in the two outputs need to be compared. For this to happen, the input must be increased. We now try to get the value of the input Vs′ for which Vo = Vo′. We have Vo = AVs and Vo′ = AV f s , which is smaller than Vo . To make Vo = Vo′, Vs is increased to Vs′. Then, Vo′ = AV f s′ . Since now, Vo = Vo′,
Feedback Amplifiers
437
AVs = AV f s′ Vs′ =
AVs Af
But from Eqn. (9.25), A = (1 + Ab ) Af Therefore, Vs′ = (1 + Ab )Vs
(9.39)
1 Vo or Now with feedback, a small fraction of this output is fed back to the input (may be 50 1 Vo ), which is a small fraction of Vo . When compared to the signal at the output, the harmonic 100 component is very small. Hence, the harmonic component that is fed back to the input is negligible and is not taken into account. From Figure 9.13(b), Vo′ = (Vs′− Vf ) A + Vh
(9.40)
But Vf = bVo′ Vo′ = AVs′− AbVo′ + Vh Using Eqn. (9.39), Vo′ (1 + Ab ) = AVs (1 + Ab ) + Vh Vo = Vo′ = AVs +
Vh
(1 + Ab )
(9.41)
Comparing Eqs (9.38) and (9.41), it can be seen that the signal component in the output in both the cases is AVs where as the harmonic component in the output without feedback is Vh and Vh that in the output of the amplifier with feedback is . (1+ Ab ) is a quantity greater than 1. 1+ ( Ab ) Hence, negative feedback in an amplifier reduces harmonic distortion.
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Electronic Devices and Circuits
9.4.4 Reduced Noise Noise in an amplifier can be due to external sources or can be internally generated. Noise is an unwanted signal in the output of an amplifier. Just as we have seen that harmonic distortion can be reduced in a feedback amplifier, on similar lines we can also show that noise is reduced in an amplifier. Only thing that we have to do is to replace the harmonic generator by a noise generator, Vn. Vn It can be seen that noise with feedback is . (1+ Ab )
9.4.5 Disadvantage with Negative Feedback in an Amplifier As the gain of a feedback amplifier is smaller than the gain without feedback, in order to get a larger output, there arises the need to cascade more number of stages that add to cost. Example 9.1 An amplifier has an openloop gain of 1000. This gain varies by ±100, and feedback is introduced to ensure that the voltage gain varies by not more than ±0.1%. Find (i) b and (ii) Af. Solution: dA dAf = A 1 + Ab Af dAf 0.1 = 0.1% = = 0.001 100 Af Given A = 1000 and dA = 100 Hence, dA 100 = = 0.1 A 1000 From Eqn. (9.27), dA dAf = A Af 1 + Ab 0.001 =
1 + Ab = (i) Ab = 100 − 1 = 99 (ii) Af =
b =
1000 A = = 10 1 + Ab 100
99 = 0.099 1000
0.1 1 + Ab 0.1 = 100 0.001
Feedback Amplifiers
9.5
439
CALCULATION OF INPUT RESISTANCE OF A FEEDBACK AMPLIFIER
When negative feedback is introduced in an amplifier, the input and output resistances get altered. If Ri is the input resistance of an amplifier without feedback, then Rif is the input resistance with feedback. Rif is larger or smaller than Ri , depending on the type of mixing (series or shunt) used at the input.
9.5.1 Calculation of the Input Resistance with Series Mixing Input resistance gets altered depending on the type of mixing used at the input. Let us consider the influence of series mixing on the input resistance of a feedback amplifier. For this, we may consider either a voltage series feedback amplifier or a current series feedback amplifier. In both the cases, the type of mixing used at the input is series mixing. 1. Voltage series feedback amplifier Voltage series feedback amplifier is considered here (Figure 9.14). From the input circuit of Figure 9.14, Rif =
Vs Ii
(9.42)
Vs = Vi + Vf = Vi + bVo
(9.43)
RL Vo = AvVi = AVVi Ro + RL
(9.44)
From the output circuit,
where AV = Av finite RL .
RL , Av is the voltage gain with RL = ∞, and AV is the voltage gain with Ro + RL
Ii + + Vi Ri
Vs − − Rif
Vf
− +
+ AvVi −
+
Ro RL
Vo −
Ampliﬁer Ri
Figure 9.14 Series mixing–voltage series feedback amplifier
440
Electronic Devices and Circuits
RL Av Lim Lim Lim A = A = = Av RL → ∞ V RL → ∞ v Ro + RL RL → ∞ Ro +1 RL Thus, Av is AV in which RL → ∞. Substituting Eqn. (9.44) in Eqn. (9.43), Vs = Vi + bVo = Vi + bAVVi = Vi (1 + AV b ) = I i Ri (1 + AV b ) Rif =
Vs I i Ri (1 + AV b ) = = Ri (1 + AV b ) = Ri D Ii Ii
(9.45) (9.46)
The input resistance of a voltage series feedback amplifier is the input resistance without feedback, Ri multiplied by D . As D is greater than 1, Rif > Ri. 2. Current series feedback amplifier A current series feedback amplifier is considered here (Figure 9.15). From the input circuit of Figure 9.15, Rif =
Vs Ii
(9.47)
Vs = Vi + Vf = Vi + bI o
(9.48)
From the output circuit, I o = GmVi
Ro = GMVi Ro + RL
(9.49)
Ro , Gm is the transconductance gain with RL = 0, and GM is the Ro + RL transconductance gain with finite RL . where GM = Gm
Ii + + Vi Ri
Vs − − Rif
Vf
GmVi
Ro
− +
Io
+
RL
Vo −
Ampliﬁer Ri
Figure 9.15 Series mixing–current series feedback amplifier
Ro Lim Lim G = G = Gm RL → 0 M RL → 0 m Ro + RL
Feedback Amplifiers
441
Thus, Gm is GM in which RL → 0. Substituting Eqn. (9.49) in Eqn. (9.48), Vs = Vi + bI o = Vi + bGMVi = Vi (1 + GM b ) = I i Ri (1 + GM b ) Rif =
Vs I i Ri (1 + GMb ) = = Ri (1 + GM b ) = Ri D Ii Ii
(9.50) (9.51)
The input resistance of a current series feedback amplifier is the input resistance without feedback, Ri multiplied by D . Thus, it can be concluded that whatever be the type of sampling used at the output, as long as the mixing at the input is series mixing, the input resistance with feedback is the input resistance without feedback multiplied by D. This means that the input resistance increases with series mixing. Because the signal that drives the amplifier is a voltage, the input resistance of the amplifier should be very much larger than the source resistance, for the entire signal to appear between the actual input terminals of the amplifier. Hence, this is a welcome requirement.
9.5.2 Calculation of the Input Resistance with Shunt Mixing Let us consider the influence of shunt mixing on the input resistance of a feedback amplifier. For this, we may consider either a voltage shunt feedback amplifier or a current shunt feedback amplifier. In both the cases, the type of mixing used at the input is shunt mixing. 1. Voltage shunt feedback amplifier Voltage shunt feedback amplifier is considered here (Figure 9.16). From the input circuit of Figure 9.16, Rif =
Vi Is
I s = I i + I f = I i + bVo
(9.52) (9.53)
From the output circuit, Vo = Rm I i where RM = Rm finite RL .
RL = RM I i Ro + RL
(9.54)
RL , Rm is the transresistance gain with , RL = ∞ and RM is the gain with Ro + RL RL Rm Lim Lim Lim R = R = = Rm RL → ∞ M RL → ∞ m Ro + RL RL → ∞ Ro +1 RL
Thus, Rm is RM in which RL → ∞. Substituting Eqn. (9.54) in Eqn. (9.53), I s = I i + bVo = I i + bRM I i = I i (1 + RM b )
(9.55)
442
Electronic Devices and Circuits
Rif =
Vi I i Ri Ri R = = = i I s I i (1 + RMb ) (1 + RMb ) D
(9.56)
The input resistance of a voltage shunt feedback amplifier is the input resistance without feedback, Ri divided by D. As D is greater than 1, Rif < Ri. Ii +
+
If Vi
Is
+
Ro RL
Rm I i
Ri
−
−
Vo −
Ampliﬁer Ri
Rif
bnetwork
Figure 9.16 Shunt mixing–voltage shunt feedback amplifier
2. Current shunt feedback amplifier A current shunt feedback amplifier is considered here (Figure 9.17). From the input circuit of Figure 9.17, Ii +
Io
If Vi
Is
AiIi
Ri
Ro
RL
− Ampliﬁer Rif
Ri bnetwork
Figure 9.17 Shunt mixing–current shunt feedback amplifier
Rif =
Vi Is
I s = I i + I f = I i + bI o
(9.57) (9.58)
From the output circuit, I o = Ai I i
Ro = AI I i Ro + RL
(9.59)
Feedback Amplifiers
443
where AI = Ai Ro , Ai is the current gain with RL = 0, and AI is the current gain with Ro + RL finite RL . Ro Lim Lim A = A = Ai RL → 0 I RL → 0 i Ro + RL Thus, Ai is AI in which RL → 0 . Substituting Eqn. (9.59) in Eqn. (9.58), I s = I i + bI o = I i + bAI I i = I i (1 + AI b ) = I i (1 + AI b ) Rif =
Vi I i Ri Ri R = = = i I s I i (1 + AI b ) (1 + AI b ) D
(9.60) (9.61)
The input resistance of a voltage shunt feedback amplifier is the input resistance without feedback, Ri divided by D. Thus, it can be concluded that whatever be the type of sampling used at the output, as long as the mixing at the input is shunt mixing, the input resistance with feedback is the input resistance without feedback divided by D. This means that the input resistance decreases with shunt mixing. Because the signal that drives the amplifier is a current, the input resistance of the amplifier should be very much smaller than the source resistance, for the entire signal current to flow through the actual input terminals of the amplifier. Hence, this is a welcome requirement.
9.6
CALCULATION OF OUTPUT RESISTANCE OF THE FEEDBACK AMPLIFIER
When negative feedback is introduced in an amplifier, the output resistance gets altered. If Ro is the output resistance of an amplifier without feedback, then Rof is the output resistance with feedback. Rof is larger or smaller than Ro , depending on the type of sampling (voltage or current) used at the output.
9.6.1 Calculation of the Output Resistance with Voltage Sampling Let us consider the influence of voltage sampling on the output resistance of a feedback amplifier. For this, we may consider either a voltage series feedback amplifier or a voltage shunt feedback amplifier. In both the cases, the type of sampling used at the output is voltage sampling. The procedure to calculate the output resistance is as follows: (i) Let RL → ∞. That is, open the load RL . (ii) Introduce a voltage source V at the output and find out the circulating current, I . (iii) The ratio of V to I with Vs = 0 (short the input voltage source) or I s = 0 (open circuit the input current source) is the output resistance. 1. Voltage series feedback amplifier Voltage series feedback amplifier in which the output voltage is sampled is shown in Figure 9.18.
444
Electronic Devices and Circuits Ii
I +
Vs = 0
+
Vi Ri
−
Vf
Ro
AvVi −
− +
+ V
Open RL Introduce V = Vo
−
Ampliﬁer
Figure 9.18 Voltage sampling—voltage series feedback amplifier
From the output circuit of Figure 9.18, I=
V − AvVi Ro
(9.62)
With Vs = 0, Vi = −Vf = − bVo = − bV
(9.63)
since Vo = V . Substituting Eqn. (9.63) in Eqn. (9.62), I=
V − Av ( − bV ) V (1 + Av b ) = Ro Ro
(9.64)
From Eqn. (9.64), Rof =
Ro V = I (1 + Av b )
(9.65)
The output resistance with feedback, for a voltage series feedback amplifier, is calculated using Eqn. (9.65). Sometimes, calculating the output resistance using Eqn. (9.65) may not be possible (we will consider this fact when we analyze a specific amplifier later) since we may end up with an indeterminate quantity. Then, an alternate way out would be to first calculate Rof′ , where Rof′ is the parallel combination of Rof and RL . Having calculated Rof′ , we then let RL → ∞ in it. We get Rof . Using Eqn. (9.65), Ro RL (1 + Av b ) = Rof RL Ro RL Rof′ = Rof  RL = = R Rof + RL Ro + RL + Av bRL o +R (1 + Av b ) L Ro RL Ro + RL Ro′ R′ = = = o RL 1 + AV b D 1 + bAv Ro + RL
(9.66)
Feedback Amplifiers
445
where Ro′ = Ro  RL the output resistance without feedback taking RL into account and RL AV = Av . The output resistance decreases with voltage sampling. Ro + RL 2. Voltage shunt feedback amplifier Voltage shunt feedback amplifier, in which the sampled output signal is once again voltage, is considered here (Figure 9.19). From the output circuit of Figure 9.19, V − Rm I i I= (9.67) Ro With I s = 0, I i = − I f = − bVo = − bV
(9.68)
since Vo = V . Substituting Eqn. (9.68) in Eqn. (9.67), I=
V − Rm ( − bV ) V (1 + Rm b ) = Ro Ro
(9.69)
From Eqn. (9.69), Rof =
Ro V = I (1 + Rm b )
(9.70)
The output resistance with feedback, for a voltage shunt feedback amplifier, is calculated using Eqn. (9.70). We also calculate Rof′ , where Rof′ is the parallel combination of Rof and RL . Using Eqn. (9.70),
Ro RL R′ R R Ro′ (1 + Rm b ) = Rof′ = Rof  RL = of L = = o Ro D Rof + RL 1 + RM b + RL (1 + Rm b )
(9.71)
RL . The output resistance with feedback is smaller than Ro + RL the output resistance without feedback, which in fact is the requirement to ensure that the entire output voltage appears across the load terminals. where Ro′ = Ro  RL and RM = Rm
Ii Open Is
Is
I +
If
RmIi
Ri
Ro
+ V Open RL Introduce V −
− Ampliﬁer
bnetwork
Figure 9.19 Voltage sampling—voltage shunt feedback amplifier
446
Electronic Devices and Circuits
9.6.2 Calculation of the Output Resistance with Current Sampling To calculate the output resistance with feedback, with current sampling at the output, we can consider current series and current shunt feedback amplifiers. 1. Current series feedback amplifier Consider the current series feedback amplifier (Figure 9.20). Writing down the KCL equation at node C, GmVi + I =
V Ro
(9.72)
With Vs = 0, Vi = −Vf = − bI o = bI
(9.73)
Substituting Eqn. (9.73) in Eqn. (9.72), Gm bI + I = I (1+ Gm b ) =
V Ro V Ro
(9.74)
Ii
I +
Vs = 0 Short Vs
−
Vf
Io
C +
Vi Ri
GmVi
Ro
Open RL Introduce V
V −
− +
Ampliﬁer
Figure 9.20 Current sampling—current series feedback amplifier
Rof =
V = Ro (1 + Gm b ) I
(9.75)
Ro RL (1 + Gm b ) Ro RL (1 + Gm b ) Ro RL (1 + Gm b ) Ro + RL Rof RL Rof′ = Rof  RL = = = = G bR Rof + RL Ro (1 + Gm b ) + RL Ro + RL + Gm bRo 1+ m o Ro + RL Rof′ = Ro′
(1 + Gm b ) = R ′ (1 + Gm b ) (1 + GM b ) o D
(9.76)
From Eqn. (9.75), it can be noted that the output resistance with feedback is larger than the output resistance without feedback, and this is advantageous because most of the output current is now allowed to flow through the load RL .
Feedback Amplifiers
447
2. Current shunt feedback amplifier Consider the current shunt feedback amplifier (Figure 9.21). Writing down the KCL equation at node C, Ai I i + I =
V Ro
(9.77)
With I s = 0 , I i = − I f = − bI o = bI
(9.78)
Substituting Eqn. (9.78) in Eqn. (9.77), Ai bI + I =
V Ro
I (1+ Ai b ) =
Rof =
V Ro
(9.79)
V = Ro (1 + Ai b ) I
(9.80)
Ro RL (1 + Ai b ) Ro RL (1 + Ai b ) Ro RL (1 + Ai b ) Ro + RL Rof RL Rof′ = Rof  RL = = = = A bR Rof + RL Ro (1 + Ai b ) + RL Ro + RL + Ai bRo 1+ i o Ro + RL
Rof′ = Ro′
Open Is
(1 + Ai b ) = R ′ (1 + Ai b ) (1 + AI b ) o D
Ii
(9.81)
I C
Io
If Is = 0
Ri
AiIi
Ro
+ V
−
Open RL Introduce V
Ampliﬁer
bnetwork
Figure 9.21 Current sampling—current shunt feedback amplifier
448
9.7
Electronic Devices and Circuits
ASSUMPTIONS MADE IN THE ANALYSIS OF FEEDBACK AMPLIFIERS
The assumptions we make in the analysis of feedback amplifiers are the following: (i) The amplifier is a unilateral network. This means that if a signal is transmitted from the input to the output, it is transmitted only through the amplifier but not through the b network (Figure 9.22).
Vs
+
+ −
+
−
Vi
+ Vo
A
RL
−
Vf
R1
+ Vo
R2 bnetwork
Figure 9.22 b network can transmit the input to the output
But this assumption may be violated in some cases because in most of the cases, the bnetwork happens to be a simple resistive network, and it is possible that the input may be transmitted to the output through the b network also, Figure 9.22. Cs
+ Vi
+ Vs
Q
A −
− Vf +
b Vo
+ Vo −
RL
b
Figure 9.23 Interelectrode capacitance Cs transmits the signal from the output to the input
(ii) The second assumption is that the b network is a unilateral network. This means that if a signal is transmitted from the output to the input, it is transmitted only through the b network but not through the amplifier. But this assumption may be violated in some cases because of the interelectrode capacitance Cs in a transistor (Figure 9.23). The stray capacitance between the output and the input Cs behaves as an open circuit at low frequencies. However, at high frequencies, the reactance of Cs becomes smaller and Cs may eventually behave as a short circuit at relatively higher frequencies. Thus, the output can be fed back to the input through the amplifier too. (iii) The third assumption is that b is independent of Rs and RL.
Feedback Amplifiers
449
Example 9.2 An amplifier has a gain of 100 and a normal input of 50 mV. If feedback with b = 0.1 is added, (i) find Af. (ii) What should be the input to get the same amount of output as without feedback? (iii) Calculate the amount of dB feedback used. Solution: Given A = 100, Vs = 50 mV and b = 0.1
Ab = 100 × 0.1 = 10
1 + Ab = 1 + 10 = 11 (i) Af =
A 100 = = 9.09 1 + Ab 11
Vo ′ = AV f s = 9.09 × 50 = 0.455 V
(ii) Vo = AVs = 100 × 50 = 5 V If the output with feedback is to be the same as that without feedback, the new input needed is Vs ′. Vs ′ = Vs (1 + Ab ) = 50 × 11 = 550 mV AV f s ′ = 9.09 × 550 = 5 V (iii) The amount of dB feedback used = 20 log10 (1 + Ab ) = 20 log10 11 = 20.83 dB.
9.8
REDUCING A FEEDBACK AMPLIFIER CIRCUIT INTO AN AMPLIFIER CIRCUIT WITHOUT FEEDBACK
Now that we have known all the prerequisites for the analysis of feedback amplifiers, let us discuss the procedure to analyze a given feedback amplifier. We, by now, know that Af = A/D , Rif is either Ri D or Ri /D and Rof = Ro (1 + Av b ) or Ro / (1+ Ai b ) , and so on. Hence, to calculate the performance quantities of the feedback amplifier, it is first required to calculate A, the gain of the amplifier without feedback and b , the feedback factor. To do this, it becomes necessary that the feedback amplifier is reduced to an amplifier without feedback. In an amplifier without feedback, there is no signal transmitted from the input to the output and vice versa through the feedback network. To achieve this objective, the following conditions need to be imposed on the feedback amplifier circuit. 1. Drawing the input loop of the amplifier without feedback To draw the input loop of the amplifier circuit without feedback, the signal transmitted from the output to the input through the b network should be reduced to zero. This condition means that the output of the bnetwork should be made zero. Let the output of the bnetwork be a voltage Vf , which could be derived by either sampling the output voltage Vo or the output current I o. That is, Vf = bVo or Vf = bI o . For Vf to be zero if the sampled signal at the output is a voltage, Vo , then in the feedback amplifier circuit, set Vo = 0, that is short the output terminals (Figure 9.24).
450
Electronic Devices and Circuits
Vs
+
+ +
−
−
Vf = 0
Vi
Set Vo = 0 Short Vo
A
−
R1 Vo R2 bnetwork
Figure 9.24 Drawing the input loop of the amplifier without feedback when the sampled signal is a voltage
For Vf to be zero if the sampled signal at the output is a current, I o , then in the feedback amplifier circuit, set I o = 0 , that is open the output loop (Figure 9.25). +
+ Vi
Vs −
−
Io
GM
RL
+ Vf = 0 Set Io = 0 Open the output loop Vf = bIo
b
Figure 9.25 Drawing the input loop of the amplifier without feedback when the sampled signal is a current
2. Drawing the output loop of the amplifier without feedback To draw the output loop of the amplifier circuit without feedback, the signal transmitted from the input to the output through the bnetwork should be reduced to zero. This condition means that the output of the bnetwork should be made zero. Let the mixing at the input be series mixing. Then, to make the signal transmitted through the b network to the output zero, make the current in the input loop zero, that is open the input loop. Hence, to draw the output loop of the amplifier without feedback, set I i = 0 (Figure 9.26).
Vs
+
Open the input loop Set Ii = 0 Ii + Vi
−
Ri
A
RL
−
R1 Vo R2
bnetwork
Figure 9.26 Drawing the output loop of the amplifier without feedback when series mixing is used at the input
Feedback Amplifiers
451
Now let the mixing at the input be shunt mixing. Then to make the signal transmitted through the bnetwork to the output zero, make the voltage between the input nodes zero, that is short the input nodes. Hence to draw the output loop of the amplifier without feedback, set Vi = 0 (Figure 9.27). + Vs −
+ Set Vi = 0 Short input Vi Ri nodes
RM
RL
b
Figure 9.27 Drawing the output loop of the amplifier without feedback when shunt mixing is used at the input
9.9
METHOD OF ANALYSIS OF FEEDBACK AMPLIFIERS
A simple, systematic, and straightforward procedure to analyze a feedback amplifier is presented below: Step 1: Let X o be the sampled signal and X f be the feedback signal. Identify whether X o is a voltage or current and whether the feedback signal, X f is a voltage or current. If X o is a current and if X f is a voltage, then the topology under consideration is voltage series feedback amplifier topology. Alternately, if X o is a voltage and if X f is a current, then the topology under consideration is voltage shunt feedback amplifier topology, and so on. Step 2: Reduce the feedback amplifier circuit into an amplifier circuit without feedback. For this, we impose the following conditions on the feedback amplifier circuit. (i) To draw the input loop, set Vo = 0, if the sampled signal is a voltage and I o = 0 if the sampled signal is a current. (ii) To draw the output loop, set Vi = 0 if shunt mixing is used and I i = 0 if series mixing is used. Now, the amplifier circuit without feedback is drawn, by using the above conditions. Step 3: Replace the transistor by its lowfrequency, smallsignal approximate model. Step 4: Calculate A and b . (i) If X o is a voltage and X f is a voltage (voltage series feedback amplifier), then X V X o Vo = and b = f = f . X o Vo X i Vi
A = AV =
(ii) If X o is a voltage and X f is a current (voltage shunt feedback amplifier), then A = RM =
X o Vo X I = and b = f = f . Xi Ii X o Vo
(iii) If X o is a current and X f is a current (current shunt feedback amplifier), then A = AI =
X o Io X I = and b = f = f . Xi Ii X o Io
452
Electronic Devices and Circuits
(iv) If X o is a current and X f is a voltage (current series feedback amplifier), then A = GM =
X o Io X V = and b = f = f . X o Io X i Vi
Step 5: Having calculated A and b , calculate D. D = 1 + AV b for voltage series feedback amplifier D = 1 + RM b for voltage shunt feedback amplifier D = 1 + AI b for current shunt feedback amplifier D = 1 + GM b for current series feedback amplifier Step 6: Now calculate Af . AV for voltage series feedback amplifier D R Af = RMf = M for voltage shunt feedback amplifier D AI Af = AIf = for current shunt feedback amplifier D G Af = GMf = M for current series feedback amplifier D
Af = AVf =
Step 7: Calculate AVf for the last three topologies since all said and done these are voltage amplifiers. R Step 8: Calculate Rif as Rif = i for shunt mixing and Rif = Ri D for series mixing. D Step 8: Calculate Rof Rof =
Ro for voltage series feedback amplifier 1 + Av b
Rof =
Ro for voltage shunt feedback amplifier 1 + Rm b
Rof = Ro (1 + Gm b ) for current series feedback amplifier Rof = Ro (1 + Ai b ) for current shunt feedback amplifier Step 9: Calculate Rof′ Rof′ =
Ro′ for voltage series feedback amplifier and voltage shunt feedback amplifier D Rof′ = Rof′ =
Ro′ (1 + Ai b ) D Ro′ (1 + Gm b ) D
for current shunt feedback amplifier for current series feedback amplifier
Feedback Amplifiers
453
By following the procedure step by step, we can arrive at the performance quantities of the feedback amplifier. Although the procedure seems complicated, in practice it turns out to be very simple. This fact can be seen when we consider practical amplifiers later. But care must be taken to identify the topology properly, to apply the rules.
9.10
ANALYSIS OF VOLTAGE SERIES FEEDBACK AMPLIFIER
Consider the circuit in Figure 9.28 and its ac circuit in Figure 9.29. VCC RL Io Rs
Rs
Io
+
+ Io
+
+
Vs
+
Vs Vf
−
−
Vo Vf
−
Vo
RE
RL
+
−
−
RE −
Figure 9.29 AC circuit of Figure 9.28
Figure 9.28 Voltage series feedback amplifier
Step 1: The first requirement in the analysis of the amplifier is to identify the topology properly. From Figure 9.29, it can be noted that the type of mixing used at the input is series mixing. The voltage drop across RE is the feedback signal Vf , which is in series with the input signal Vs . Is this feedback signal derived by sampling the output voltage, or is it derived by sampling the output current? To answer this, let us put a test on the circuit. We know that if the sampled signal is a voltage, then Vf = bVo and if the sampled signal is a current, then Vf = bI o. This means that if we set Vo = 0 and then if Vf = 0 , then the type of sampling used is voltage sampling. Alternately, if we set I o = 0 and then if Vf = 0, then the type of sampling employed is current sampling. Set I o = 0 (Figure 9.30), then Vf ≠ 0, as there is an open circuit voltage. Alternately, set Vo = 0 (Figure 9.31), then Vf = 0. Hence, it can be concluded that the sampled signal is a voltage. Hence, the topology of the amplifier in circuit in Figure 9.28 is a voltage series feedback amplifier. Io
+
+ Vs
−
Io
Io = 0
Rs
+
RL
Rs
−
RE −
Figure 9.30 Circuit when I o = 0
+ + Vs
Vo Vf
RL
+ −
Vf
Vo = 0
− −
Figure 9.31 Circuit when Vo = 0
454
Electronic Devices and Circuits
Step 2: To draw the input loop of the amplifier without feedback, set Vo = 0, since the sampled signal is a voltage. Imposing this condition on the circuit in Figure 9.29, we draw the input loop as in Figure 9.32. Io
Open loop Ii = 0
Rs
RS
+
+
+ + Vs
RC
+
+ Vs
Vf
−
Vo = 0
−
− −
Vo
Vf RE
−
Figure 9.32 To draw the input loop, set Vo = 0
−
Figure 9.33 To draw the output loop, set I i = 0
To draw the output loop, set I i = 0 (Figure 9.33). Then, there is no contribution of the signal in RE due to I i , and hence RE can be considered totally as part of the output circuit only, Figure 9.34. Combining the circuits in Figures 9.32 and 9.34, we can draw the amplifier circuit without feedback as in Figure 9.35.
RC
−
−
Vs
Vo
RE
−
Vf
+
−
+ Io
RE
RC
Rs
Vo Io
Vf +
+
Figure 9.34 Output loop when I i = 0
−
+
Figure 9.35 Amplifier circuit without feedback
Step 3: In Figure 9.35, replace the device by its lowfrequency, smallsignal approximate model as in Figure 9.36. Ib = Ii Rs + Vs
+ Vi
RC hie
hfeIb
−
− Io
Figure 9.36 Equivalent circuit of Figure 9.35
Vf
− RE Vo
+
+
Feedback Amplifiers
455
Step 4: Calculate A and b . From Figure 9.36, b=
Vf =1 Vo
(9.82)
since Vf and Vo are the voltages across the same resistance RE with the same polarity. AV =
Vo Vo = since Vi = Vs, if Rs is considered as part of the amplifier circuit. Vi Vs hfe I b RE hfe RE AV = = (Rs + hie ) I b (Rs + hie )
(9.83)
Step 5: Using Eqs (9.82) and (9.83), calculate D. D = 1 + AV b = 1 +
hfe RE R + hie + hfe RE ×1 = s (Rs + hie ) (Rs + hie )
(9.84)
Step 6: Calculate AVf . Using Eqs (9.83) and (9.84),
(Rs + hie ) = AV hfe RE hfe RE = D ( Rs + hie ) Rs + hie + hfe RE Rs + hie + hfe RE
AV = f
(9.85)
If hfe RE >> (Rs + hie ) , then AVf ≈ 1. Step 7: We calculated AV because this is a voltage series feedback amplifier. f
Step 8: Rif = RI D From Figure 9.36 and using Eq. 9.84 (Rs + hie ) I b = R + h V Ri = s = ( s ie ) Ib Ib Rif = Ri D = ( Rs + hie )
(9.86)
Rs + hie + hfe RE = Rs + hie + hfe RE (Rs + hie )
(9.87)
Ro where Ro is the output resistance without feedback (Figure 9.37). Open the 1 + Av b load RE and look into the output terminals, then the resistance that is seen is Ro. hfe I b is an ideal current source with its internal resistance ∞. Hence, Ro is ∞. Step 9: Rof =
Rs + + Vs
Vi
RC hie
hfeIb
−
Ro
Figure 9.37 Circuit to find Ro
456
Electronic Devices and Circuits
Av =
hfe RE hfe Lim Lim Lim AV = = =∞ RE → ∞ RE → ∞ (Rs + hie ) RE → ∞ (Rs + hie ) RE
Ro ∞ = , which is an indeterminate quantity. Hence, Rof is not calculated using (1 + Av b ) ∞ Eqn. (9.65). To calculate Rof , we first calculate Rof′ using the expression obtained earlier, and then R′ let RE → ∞ in this. Using Eqn. (9.66), Rof′ = o where Ro′ = Ro  RE = RE since Ro = ∞. D Rof =
Rof′ =
Rof =
=
RE (Rs + hie ) RE = Rs + hie + hfe RE Rs + hie + hfe RE Rs + hie
(9.88)
RE (Rs + hie ) Lim Lim Rof′ = RE → ∞ RE → ∞ Rs + hie + hfe RE
(Rs + hie )
Lim RE → ∞
R + hie hfe + s RE
=
(Rs + hie )
(9.89)
hfe
Example 9.3 For the circuit in Figure 9.28, RE = 2 kΩ, Rs = RC = 1 kΩ, hie = 1 kΩ, and hfe = 50. Calculate AV, b, D, AVf , Rif, and Rof. Solution: Using Eqs (9.82) and (9.83), b=
Vf hfe RE 50 ´ 2 = 1 and AV = = = 50 Vo ( Rs + hie ) 1 + 1 D = 1 + AV b = 1 + 50 (1) = 51
AV = f
AV 50 = = 0.98 D 51
Rif = Ri D and Ri = Rs + hie = 1 + 1 = 2 kΩ
Rof =
∴ Rif = 2 × 51 = 102 kΩ
(Rs + hie ) = 1 + 1 hfe
50
= 40 Ω
The voltage series feedback amplifier is nothing but an emitter follower.
Feedback Amplifiers
9.11
457
ANALYSIS OF CURRENT SERIES FEEDBACK AMPLIFIER
Consider the circuit in Figure 9.38 and its ac circuit in Figure 9.39. VCC RC Io Rs
Rs
+
+ RC
+
Io
+ Vs
Io Vf
−
RE −
+ Vs
Vo
Vf
−
Vo
+
−
−
Figure 9.38 Current series feedback amplifier
−
RE
Figure 9.39 AC circuit of Figure 9.38
Step 1: Let us identify the topology properly. From Figure 9.38, it can be noted that the type of mixing used at the input is series mixing. The voltage drop across RE is the feedback signal Vf , which is in series with the input signal Vs . To find out the type of sampling used, set Vo = 0 (Figure 9.40). As I o ≠ 0, Vf ≠ 0. Alternately, set I o = 0 (Figure 9.41), then, Vf = 0. Hence, it can be concluded that the sampled signal is a current. Hence, the topology of the amplifier in Figure 9.38 is a current series feedback amplifier.
Io = 0 Io Rs
Rs
+
+ Vo = 0
+ Vs
−
Vf
RC Vo
+
+
RE
−
Figure 9.40 Circuit when Vo = 0
+
Vs
− −
Vf
Io
−
RE −
Figure 9.41 Circuit when I o = 0
Step 2: To draw the input loop of the amplifier without feedback, since the sampled signal is a current, set I o = 0. In Figure 9.39, when I o = 0, there is no contribution of the signal in RE , and hence RE can be considered totally as part of the input loop only as shown in Figure 9.42.
458
Electronic Devices and Circuits Io = 0 Rs
Io
Open loop Ii = 0
+
Rs
+ Vs
RC
Vo
+ −
Vs
+ −
RE
− Vf − RE
Figure 9.42 Input loop with I o = 0
Figure 9.43 Output loop with I i = 0
To draw the output loop, set I i = 0 (Figure 9.43). Then there is no contribution of the signal in RE due to I i , and hence RE can be considered totally as part of the output circuit only (Figure 9.44). Combining the circuits in Figures 9.42 and 9.44, the amplifier circuit can be drawn without feedback as shown in Figure 9.45.
+
Ii = 0
Rs
+ Io
RC Vo
+
RCVo
−
Vs
− + Vf
−Io
−
+ Vf −
−
RE
RE
Figure 9.44 Output loop with I i = 0
RE
Figure 9.45 Amplifier circuit without feedback
Step 3: In Figure 9.45, replace the device by its lowfrequency, smallsignal approximate model as in Figure 9.46. Ib Rs +
Vi
Vs −
Io
+
RC
Vo
+ hie
hfeIb
− RE
−Io
RE
+
Vf
Figure 9.46 Equivalent circuit
− −
Feedback Amplifiers
459
Step 4: Calculate A and b . From Figure 9.46, b=
since Vf = − I o RE . GM =
Vf −I o RE = = −RE Io Io
(9.90)
Io Io = since Vi = Vs , if Rs is considered as part of the amplifier circuit. Vi Vs GM =
− hfe I b − hfe = + + + R R h I R ( s E ie ) b ( s RE + hie )
(9.91)
Step 5: Using Eqs (9.90) and (9.91), calculate D. Rs + hie + (1 + hfe ) RE − hfe −RE ) = D = 1 + GM b = 1 + ( Rs + RE + hie (Rs + RE + hie )
(9.92)
Step 6: Calculate GMf . Using Eqs (9.91) and (9.92), GMf =
− hfe − hfe Rs + RE + hie GM = × = D (Rs + RE + hie ) Rs + hie + (1 + hfe ) RE Rs + hie + (1 + hfe ) RE
(9.93)
Io − hfeVs or I o = GMfVs = Vs Rs + hie + (1 + hfe ) RE
(9.94)
GMf =
If (Rs + hie ) w o . Equating the real terms: −R +
hfe M hoe L = C hie C
(10.27)
Or hfe M RC + hoe L = hie C C hfe RC + hoe L ≥ hie M
(10.28)
Equation (10.28) is the amplitude condition to be satisfied in the circuit for the oscillations to build up and sustain.
506
Electronic Devices and Circuits
Example 10.3 A tuned collector oscillator has L = 100 µH and C = 1000 pF. (i) Calculate its frequency. (ii) If, hoe = 25 × 10−6 and the resistance associated with the inductance R is 1 kΩ, calculate the exact frequency of oscillations. (iii) If M = 5 µH, find the minimum value of hfe for the oscillations to build up, if hie = 1 kΩ. Solution: The approximate frequency is ( i) f =
1
1
=
2p LC
−6
2p 100 × 10 × 1000 × 10 −12
= 503.91 kHz
(ii) The exact of frequency is given as follows: 2 w exact =t w 2 (1 +(1hoe Roe) )e fexact = f 1 (1 + hoe R )
1 + hoeR = 1 + 25 × 10−6 × 1 × 103 = 1.025 (1+ hoe R ) = 1.012
( iii )
hfe RC + hoe L ≥ hie M hfe ( min ) =
10.7
fexact = f (1 + hoe R ) = 503.91 × 1.012 = 509.95 kHz
hie (RC + hoe L ) M
(
1 × 103 1 × 103 × 1000 × 10 −12 + 25 × 10 −6 × 100 × 10 −6 =
5 × 10
−6
) = 200.5
RC OSCILLATORS
At audio frequencies, the value of the inductance is large and can be in the order of Henries. Therefore, the inductance is wound on an iron core and thus becomes bulky and occupies more space. Hence, we go in for RC oscillators. We basically consider two types of audio oscillators, namely, RC phaseshift oscillator and Wien bridge oscillator. In all the feedback oscillators, as the amplifier produces a phase shift of 180°, the bnetwork is required to produce the additional phase shift of 180°. A single RC network can produce a maximum phase shift of 90° under ideal conditions. Hence, there arises the need to cascade more than two such stages to obtain a phase shift of 180° because attaining an ideal case is not possible. But there cannot be scope for changing the frequency. So sometimes it becomes necessary to cascade three RC networks to produce the required phase shift of 180°. The RC phase shift oscillator is mostly used to obtain a fixed frequency output. Alternatively, a twostage amplifier that gives a phase shift of 360° is used, and the RC b network is so chosen that it produces a phase shift of 0° at a desired frequency. The procedure followed in the analysis of these oscillators is that we calculate the gain of the amplifier and also calculate the gain using the b network and equate these two gains. Equating the imaginary and real terms, the frequency and the condition for oscillations to build up and sustain are obtained.
Oscillators
507
10.8 WIEN BRIDGE OSCILLATOR The Wien bridge oscillator is so called because the circuit is based on a frequencyselective form of the Whetstone bridge circuit. The Wien bridge oscillator is a twostage RC coupled amplifier circuit that has good stability at its resonant frequency. This oscillator uses a feedback circuit consisting of a series RC circuit connected with a parallel RC of the same component values producing the necessary phase shift. At the resonant frequency, the phase shift is 0°. The Wien’s network, shown in Figure 10.17 , consists of a series RC circuit connected to a parallel RC . At low frequencies, the reactance of the series capacitor C is very high, and hence the series RC circuit acts as a highpass filter. At high frequencies, the reactance of the shunt capacitor C is very low, and hence the parallel RC circuit acts as a lowpass filter. Thus, these cascaded filters produce a very selective secondorder frequency dependent bandpass filter with a high Q factor at the desired frequency. However, between these two extremes, the output voltage reaches a maximum value at a frequency called the resonant frequency. Highpass ﬁlter Lowpass ﬁlter
R
C
C Output
Input R
Figure 10.17 Wien’s network
A Wien bridge oscillator is one in which a twostage RC coupled amplifier is used and the output is fed back to the input through the b network as shown in Figure 10.18.
VDD C RD
R
RD
CC
CC Q2
Q1 R
C
bNetwork
Twostage ampliﬁer
Figure 10.18 Wien bridge oscillator
Output
508
Electronic Devices and Circuits
− mRD and the overall gain is the product of the individual gains. rd + RD And this gain is a real gain. Now, we calculate the gain using b network (Figure 10.19). The gain of each stage is A =
Vds is the output of the amplifier and Vgs is the input. The ratio of Vds to Vgs is the gain A. Vgs = Vds R+
R× R+
1 jwC 1 jwC
R× 1 + jwC R+
1 jwC 1 jwC
R Vds + Vgs C
R+ V A = ds = Vgs
R× 1 + jwC R+ R× R+
1 jwC 1 jwC
+
C
1 jwC 1 jwC
R − −
Figure 10.19 b network
2
A=
2 1 j wC 1 2 R j wC Vds = 1+ R + = 1 + R − 2 2 + Vgs j wC R jwC R wC
A = 1 + jwRC +
1 1 + 2 = 3 + jwRC + jwRC jwRC
(10.29)
Equating the imaginary parts in Eqn. (10.29), 1 =0 jwRC
jwRC +
w=
f =
(10.30)
1 RC
1 2pRC
(10.31)
Oscillators
509
Equating real terms, (10.32)
A=3
The gain of the amplifier should be adjusted to 3. If the gain is more than 3, then there is distortion in the amplitude.
10.9
RC PHASE SHIFT OSCILLATOR USING FET
We know that a classA commonemitter amplifier produces a phase shift of 180°. To produce an additional phase shift of 180° so as to derive an inphase signal at the input of the amplifier, an RC network may also be used. Singlestage and threestage RC networks are shown in Figure 10.20. C Input
Output R 0°
60°
60°
0°
0°
C
C
C Output
Input 0° R
0°
60°
R
R
180°
180°
120°
Figure 10.20 Singlestage and threestage RC networks −1 X C Z = R + jX C and the phase angle q = tan R
An RC phaseshift oscillator using an FET is shown in Figure 10.21. VDD RD
Output
C
+
C
C
+ Vgs
Vds
−
R
R
R CS
RS
−
Figure 10.21 RC phaseshift oscillator using a JFET
510
Electronic Devices and Circuits
− mRD , which is a real gain. Once again, we calculate rd + RD A using the b network comprising three RC phaseshifting networks as shown in Figure 10.22.
Here also the gain of the amplifier is A =
I2 + I3 I1 + I2 + I3
I3 C
+
C
R
Vds I1
+
C
R
I2
R
Vgs
I3
−
−
Figure 10.22 b network
From Figure 10.22, Vgs = I 3 R
(10.33)
1 I 2 R = I3 R + jwC Or 1 I 2 = I 3 1 + jwRC
(10.34)
1 1 I1 R = I 2 R + + I3 jwC jwC Or 1 1 I1 = I 2 1 + + I3 jwRC jwRC Substituting for I 2 from Eqn. (10.34), 1 3 1 1 1 I1 = I 3 1 + 1+ + I3 = I 3 1 + − 2 2 2 jwRC jwRC jwRC jwRC w R C 1 1 1 Vds = I1 R + + I2 + I3 jwC jwC jwC
(10.35)
511
Oscillators
1 3 1 1 1 1 + I3 Vds = I 3 1 + − 2 2 2 R + + I 3 1 + jwRC w R C j wC jwRC jwC C jwC 3 1 1 3 1 1 1 1 Vds = I 3 R + − 2 + − 2 − 3 2 3+ − 2 + 2 2 2 jwC jwC w RC jwC w RC jwC w RC jw R C 6 5 1 Vds = I 3 R 1 + − 2 2 2 − 3 3 3 jwRC w R C jw R C Using Eqn (10.33) 6 5 1 Vds = Vgs 1 + − 2 2 2 − 3 3 3 jwRC w R C jw R C A=
Vds 6 5 1 = 1+ − − Vgs jwRC w 2 R 2C 2 jw 3 R3C 3
(10.36)
Equating the imaginary terms in Eqn. (10.36), 6 1 1 − 3 3 3 = 0 or w 2 = wRC w R C 6R 2C 2
(10.37)
Equating the real terms in Eqn. (10.36), A = 1−
5 w R 2C 2 2
Substituting for w 2 from Eqn. (10.37), A = 1−
5 = −29 1 2 2 2 2 R C 6R C
(10.38)
From Eqs (10.38) and (10.37), it is evident that for oscillations to build up and sustain, the gain of the amplifier must be greater than that or equal to 29; and if this condition is satisfied, then the 1 oscillator oscillates at w = . 6RC 1 f = (10.39) 2p 6RC
10.10
RC PHASESHIFT OSCILLATOR USING A BJT
RC phaseshift oscillators using a BJT are shown in Figure 10.23. In the circuit in Figure 10.23(a), three identical highpass RC circuits are connected in cascade. However, a CE amplifier has a small input resistance hie ≈ 1 kΩ; R and C decide the frequency of oscillations. Let R be chosen as 10 kΩ to derive a desired frequency. The R in the third phaseshifting network will appear in parallel with hie as such the effective resistance of the parallel combination is approximately hie. To ensure that the value of this resistance remains as R only, (R − hie) is connected in series with the
512
Electronic Devices and Circuits
base terminal as shown in the modified circuit in Figure 10.23(b). An alternate form of RC phaseshift oscillator using low pass circuits as phaseshifting networks is shown in Figure 10.23(c). VCC
RC
60°
120°
180°
0° C
C
C Output
R
R
R CE
1
RE
3
2
Three identical RC high pas circuits
Figure 10.23(a) RC phase shift oscillator using a BJT VCC
RC
60°
R − hie
120°
180°
0° C
R
C
C
R CE
RE
Figure 10.23(b) Modified circuit of Figure 10.23(a)
The equivalent circuit of Figure 10.23(b) is shown in Figure 10.24. The current source hfe I b with its internal resistance is replaced by a voltage source hfe I b RC with internal resistance RC (Figure 10.25). In order to get the frequency and the condition for the oscillations to build up and sustain, we write down the KVL equations of the three loops and write down the determinant.
Oscillators
513
VCC
CC
R
R
C
RC
R
C
C RE
CE
(c) Alternate circuit of RC phase shift oscillator
Figure 10.23(c) RC phaseshift oscillators using a BJT
As the individual currents I1 , I 2 , and I b are not zero, the determinant is zero. Equating real and imaginary terms, we get the frequency and the condition for the oscillations to build up and sustain.
C
RC
hfeIb
C
R
C
R − hie
hie
R
Figure 10.24 Equivalent circuit of Figure 10.23(b)
RC
C
C
C
R − hie − R
hfeIbRC +
I1
R I2
Ib
hie
Figure 10.25 Circuit of Figure 10.24 with current source replaced by voltage source
514
Electronic Devices and Circuits
From Figure 10.25, writing the KVL equations,
(R + RC − jX C ) I1 − RI 2 + hfe RC I b = 0
(10.40)
−RI1 + (2R − jX C ) I 2 − RI b = 0
(10.41)
−RI 2 + (2R − jX C ) I b = 0
(10.42)
As I1, I 2 , and I b are nonzero currents, the determinant of the coefficients of I1, I 2 , and I b is zero: R + RC − jX C −R 0
−R 2R − jX C −R
hfe RC −R =0 2R − jX C
(R + RC − jX C ) (2R − jX C ) (2R − jX C ) − ( −R ) ( −R ) + R −R (2R − jX C + hfe RRC ) = 0 R3 + R 2 RC (3 + hfe ) − 5RX C2 − RC X C2 − j 6R 2 X C − j 4RRC X C + jX C3 = 0
(10.43)
Equating imaginary terms in Eqn. (10.43), 6R 2 X C + 4RRC X C − X C3 = 0 or X C2 = 6R 2 + 4RRC
(10.44)
Or 4R X C2 = R 2 6 + C = R 2 (6 + 4 k ) R where k =
RC R X C = R 6 + 4k
Or 1 = R 6 + 4k wC 1 w=
RC 6 + 4 k
(10.45)
Oscillators
f =
515
1 (10.46)
2pRC 6 + 4 k
Equating real terms in Eqn. (10.43), R3 + R 2 RC (3 + hfe ) − (5R + RC ) X C2 = 0
(10.47)
Substituting Eqn. (10.44) in Eqn. (10.47)
(
)
R3 + R 2 RC (3 + hfe ) − (5R + RC ) 6R 2 + 4RRC = 0 When simplified, hfe = 23 + 4 k +
29 k
(10.48)
29 Equation (10.48) implies that for oscillations to build up, hfe > 23 + 4 k + and after the oscil k lations reach the sustained condition. hfe = 23 + 4 k +
29 k
If k = 1, then hfe ≥ 56. Analysis of the circuit shown in Figure 10.23(c) can be carried out on similar lines. Example 10.4 In an RC phaseshift oscillator using BJT, the feedback network uses R = 6 kΩ and C = 1.5 nF. The transistor amplifier uses RC = 18 kΩ. Calculate the frequency of oscillations and hFE(min). Solution: RC = 18 kΩ and R = 6 kΩ. k=
f =
RC 18 = =3 6 R 1
1
2pRC 6 + 4 k
hFE (min) = 4 k + 23 +
=
3
2p × 6 × 10 × 1.5 × 10 −9 6 + 4 × 3
29 29 = 4 × 3 + 23 + = 44.67 k 3
= 4.17 kHz
516
10.11
Electronic Devices and Circuits
AMPLITUDE STABILITY IN OSCILLATORS
A lowdistortion oscillator requires effective amplitude stabilization. The amplitude of electronic oscillators tends to increase until clipping or limitation of the gain by some other form is reached. This leads to high harmonic distortion, which is undesirable. A resistance RE can be used in the emitter lead to ground to stabilize the gain of the amplifier, and thus derive amplitude stability of the oscillations. But this can result in reduction in the gain of the amplifier. As a result, oscillations may not build up at all. An incandescent bulb as a positive temperature coefficient (PTC) thermistor can be used in the oscillator feedback path to limit the gain. The resistance of light bulbs and similar heating elements increases as their temperature increases. Thus initially, when the oscillations build up, the light bulb offers small resistance. But, as the amplitude increases further, as its resistance increases, provides negative feedback and thus stabilizes the gain. But a light bulb can be bulky. Therefore, oscillators can use other nonlinear elements, such as diodes, thermistors, field effect transistors, or photocells for amplitude stabilization in place of light bulbs as indicated in Figure 10.26.
VDD C R
C
bnetwork
R
RD
RD
Q1 C C
Q2 CC
T1
T2
Thermistors
Twostage ampliﬁer
Figure 10.26 Amplitude stabilization with thermistors
10.12
FREQUENCY STABILITY IN OSCILLATORS
The main limitation of both LC and RC oscillators is their poor frequency stability. Consider a radio station transmitting at a frequency of 1 MHz. To receive the signal corresponding to this station, radio receiver must be tuned to this frequency. Unfortunately, the frequency of the oscillator used for generating this 1 MHz signal keeps changing from time to time. The change in frequency is due to various reasons, mainly because of variations of device parameters and components values used in the tank circuit due to temperature variations, as the transmitted power is large. Every time this frequency changes, the radio receiver must be retuned, and this is obviously disgusting. Hence, it becomes imperative that the frequency of the oscillator should remain unaltered. One method used, usually, is to provide a constant temperature chamber. Second, the instability in frequency is due to small value of Qs in LC and RC oscillators. Incidentally, Q
Oscillators
517
is the figure of merit of a tuned circuit. Typically, it can be expressed as Q = wL /R = 1/wRC . The larger the value of Q , the sharper the response characteristic of the tuned circuit, and hence its ability to reject the unwanted frequencies and select only the desired frequency, because in all the oscillators we require that only one frequency component be fed back from the output through the bnetwork. The Qs that are normally encountered in LC oscillators are typically of the order of 200, and consequently the response is not necessarily sharp. On the contrary, when Q is 10,000, then response of the tuned circuit is very sharp as shown in Figure 10.27. Crystal oscillators have large Qs of the order of 50,000 and more. Crystal oscillators are chosen for generating stable frequencies. Q large Response
Q relatively small
0
fo
f
Figure 10.27 Response of the tank circuit as a function of Q
10.13
CRYSTAL OSCILLATORS
We know that certain materials available in nature, such as Rochelle salt, Quartz, and Tourmaline, exhibit piezoelectric property. If pressure is applied across the opposite faces of the crystal, it generates a voltage. Alternatively, if an oscillating signal is applied to the crystal, the crystal vibrates. This property is called the piezoelectric property. Of the three materials, Rochelle salt has the best piezoelectric property, but it is the weakest of all. Hence, when a thin slab of the crystal is used and if it vibrates, it may break. On the contrary, Tourmaline has the least piezoelectric property, but it is the strongest of all. Quartz has strength better than Rochelle salt and better piezoelectric property compared to Tourmaline. Further, it is abundantly available in nature. Hence, Quartz crystals are used for majority of the applications. The Quartz crystal is in the shape of a hexagonal prism with pyramids at the top as indicated in Figure 10.28. A thin slab of this crystal is cut along XXaxis, YYaxis, XYaxis, and so on, and it is held between a pair of electrodes as shown in Figure 10.29. The electrical equivalent of the crystal is shown in Figure 10.30. From the equivalent circuit of the crystal, it is evident that a crystal has two resonant frequencies: (i) a series resonantfrequency and (ii) a parallel resonantfrequency. The series resonantfrequency fs is given as follows:
fs =
1 2p LSCS
518
Electronic Devices and Circuits
A
CS A
CM
LS
t RS B
B
Figure 10.28 A quartz crystal
Figure 10.29 A thin slab mounted between electrodes
Figure 10.30 Electrical equivalent of the crystal
and the parallel resonantfrequency is given as follows: fp =
1 2p LSCeq
where Ceq =
CMCS CM + CS
CM is called the mounting capacitance. Figure 10.31 shows the variations of impedance of the crystal with respect to frequency f . Between fs and fp, it can be noted that the impedance of the crystal varies linearly with frequency as in an inductance. Hence the inductance can be replaced by a crystal.
Impedance
0
fs
fp
Figure 10.31 The two resonant frequencies of the crystal
f
Oscillators
519
A crystal oscillator is shown in Figure 10.32. This circuit is a mere modification of a Colpitts oscillator in which the inductance is replaced by a crystal. The frequency of the crystal is inversely proportional to the thickness of the slab. That is, f = k t, where k the constant of proportionality that depends on the orientation in which the thin slab of the crystal is cut. Therefore, as there is a minimum thickness for the crystal slab, and hence there is a maximum frequency up to which the crystal can be used.
C2
A Crystal B
C1
Figure 10.32 Crystal oscillator
Example 10.5 For the crystal, L = 0.1 H, C = 0.01 pF, RS = 10 kΩ, and CM = 1 pF. Find the resonant frequencies and the Q factor. Solution: (i)
fs =
1 2p LC
(ii) Ceq = fp =
(iii) Q =
10.14
1
= 5.035 MHz
= 2p 0.1 × 0.01 × 10 −12
CCM 0.01 × 1 = 0.0099 pF . = C + CM 0.01 + 1 1 2p LCeq
=
1 2p 0.1 × 0.0099 × 10 −12
= 5.06 MHz
wLs 2p × 5.035 × 106 × 0.1 = = 316.2 RS 10 × 103
BEAT FREQUENCY OSCILLATOR
It can be noted that by using crystal oscillators, it is possible to generate stable radio frequency oscillations. But at audio frequencies as we use RC oscillators, their frequency stability cannot be assured. Hence, to generate stable audio frequency oscillations, we can use crystal oscillators. Such an oscillator is called beat frequency oscillator and is indicated in Figure 10.33.
520
Electronic Devices and Circuits Fixed frequency crystal oscillator 500 kHz f1
f1 − f2 Mixer
RF ﬁlter
f2
0−20 kHz
Audio ampliﬁer
Output
480−500 kHz Variable frequency crystal oscillator
Figure 10.33 Beat frequency oscillator
Here, we have two crystal oscillators: one is a fixed frequency oscillator ( f1 = 500 kHz) and the other is a variable frequency oscillator ( f2 varies from 480 to 500 kHz). These two signals are inputs to a mixer. At the output of the mixer, there are many sum frequencies and difference frequencies, ( mf1 ± nf2 ), where m and n are integers. The output of the mixer has a tuned circuit tuned to ( f1 − f2 ) , and hence the output of the mixer consists of audio frequencies (0–20 kHz). To eliminate radio frequency components of ripple, an RF filter is used. The output audio components are amplified by an audio amplifier.
10.15
EXACT ANALYSIS OF COLPITTS AND HARTLEY OSCILLATORS
The ac circuit of Figure 10.6 with the transistor replaced by its equivalent circuit is shown in Figure 10.34 . Here, hoe is not neglected. hoe is an admittance and Z2 is an impedance. Hence the effective admittance is I2
I1
1 1 + hoe Z2 hoe + = Z2 Z2
+ hie
hfeI1
hoe
V2
Z2
−
Hence hoe  Z2 can be replaced by an
Z3
admittance, (1 + hoe Z2 ) Z2 . Further, when hie is pulled down, hie and Z1 are in paral
Z1
lel and the current I1 in Z1 flows upwards, Figure 10.35. From Figure 10.35, Figure 10.34 Equivalent circuit of Figure 10.6 considering hoealso
I1 = − I 2
I −Z1 Z1 or 1 = b = Z1 + hie I2 Z1 + hie
(10.49)
Oscillators
C
521
I2
+ V2
hfeI1
(1 + hoeZ2) Z2
− I2
hie
Z3
I1
Z1
− I2 I2
Figure 10.35 Simplified circuit of Figure 10.34
Writing the KVL equation of the outer loop h Z V2 + ie 1 I 2 + I 2 Z3 = 0 hie + Z1
(10.50)
Writing the KCL equation at node C I 2 = hfe I1 +
1 + hoe Z2 V2 Z2
(10.51)
Or Z2 V2 = ( I 2 − hfe I1 ) 1 + hoe Z2
(10.52)
Substituting Eqn. (10.52) in Eqn. (10.50),
Z2 hie Z1 + I 2 + I 2 Z3 = 0 1 + hoe Z2 hie + Z1
( I 2 − hfe I1 )
Z2 Z2 h Z I2 + ie 1 + Z3 = hfe I1 1 + hoe Z2 hie + Z1 1 + hoe Z2 Z ( h + Z1 ) + hie Z1 (1 + hoe Z2 ) + Z3 ( hie + Z1 ) (1 + hoe Z2 ) I 2 2 ie = hfe I1Z2 ( hie + Z1 ) A=
hfe Z2 ( hie + Z1 ) I2 = I1 Z2 ( hie + Z1 ) + hie Z1 (1 + hoe Z2 ) + Z3 ( hie + Z1 ) (1 + hoe Z2 )
(10.53)
522
Electronic Devices and Circuits
From Eqs (10.52) and (10.53), −Z1 hfe Z2 ( hie + Z1 ) Ab = Z2 ( hie + Z1 ) + hie Z1 (1 + hoe Z2 ) + Z3 ( hie + Z1 ) (1 + hoe Z2 ) Z1 + hie −hfe Z1Z2 Ab = = −1 Z ( h + Z ) + h Z (1 + h Z ) + Z ( h + Z ) (1 + h Z ) 1 ie 1 oe 2 3 oe 2 ie 1 2 ie hfe Z1Z2 = Z2 ( hie + Z1 ) + hie Z1 (1 + hoe Z2 ) + Z3 ( hie + Z1 ) (1 + hoe Z2 ) hfe Z1Z2 = Z1Z2 + Z1Z3 + hie ( Z1 + Z2 + Z3 ) + hie hoe ( Z1Z2 + Z2 Z3 ) + hoe Z1Z2 Z3
(10.54)
We can recognize that Eqn. (10.54) is the Barkhausen criterion. In order to find out the frequency of oscillations, we substitute specific conditions in Eqn. (10.54). By separating real and imaginary parts and equating the imaginary terms on either side of the relation we get the frequency of oscillations and by equating the real terms on either side of the relation we get the condition that must be satisfied in the amplifier circuit for the oscillations to build up and sustain.
10.15.1 Colpitts Oscillator Z1 =
1 1 , Z2 = , and Z3 = jwL jwC1 j wC 2
Substituting these conditions in Eqn. (10.54), we have 1 1 hfe jwC1 jwC2
1 1 = jwC1 jwC2
1 1 1 + + j wL + + jwL + hie jwC1 jwC1 jwC2
1 1 hie hoe jwC1 jwC2
1 + jwC 2
1 1 jwL + hoe jwC1 jwC2
−1 1 −hfe L jh L L 1 −1 + − oe = 2 + + jhie wL − + + hie hoe 2 2 w C1C2 w C1C2 C1 wC1 wC2 w C1C2 C2 wC1C2 Equating imaginary terms on either side of Eqn. (10.55), 1 1 hoe L hie wL − + =0 − wC1 wC2 wC1C2 Or w 2 LC1C2 − (C1 + C2 ) =
hoe L hie
j wL
(10.55)
Oscillators
523
Or w 2 LC1C2 = (C1 + C2 ) + w2 =
hoe L hie
hoe 1 1 1 + + L C1 C2 hieC1C2
(10.56)
The second term in the above equation becomes negligible, since hoe hie is extremely small in all transistors. As a result, the frequency of oscillations of this circuit can be written as w2 =
1 1 1 + L C1 C2
Let Ceq be the equivalent capacitance of C1 and C2 and we have 1 1 1 = + Ceq C1 C2
w2 =
f =
1 , LCeq
w=
1 LCeq
1 2p LCeq
(10.57)
Equating real terms on either side of Eqn. (10.55) −1 −hfe L L −1 = 2 + + hie hoe 2 + 2 w C1C2 w C1C2 C1 w C1C2 C2 −hfe = −1 + w 2 LC2 + hie hoe −1 + w 2 LC1 = −1 − hie hoe + w 2 ( LC2 + hie hoe LC1 ) Substituting Eqn (10.56) in Eqn (10.58) 1 1 hoe 1 − hfe = −1 − hie hoe + ( LC2 + hie hoe LC1 ) + + L C1 C2 hieC1C2 h L C2 C L + 1 + oe + hie hoe + hie hoe 1 + hoe2 C1 hieC1 C2 C2 h L C C L C2 −hfe = 2 + oe + hie hoe 1 + hoe2 ≈ C1 hieC1 C2 C2 C1
−hfe = −1 − hie hoe +
since the other terms can be neglected as hoe is negligible.
(10.58)
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Electronic Devices and Circuits
Hence the condition to be satisfied for the oscillations to build up and sustain is hfe ≥
C2 C1
(10.59)
10.15.2 Hartley Oscillator Z1 = jwL1 , Z2 = jwL2 and Z3 =
1 j wC
Substituting these conditions in Eqn. (10.54), we have 1 1 hfe ( jwL1 )( jwL2 ) = ( jwL1 )( jwL2 ) + ( jwL1 ) + hie jwL1 + jwL2 + + jw C j wC 1 1 hie hoe ( jwL1 ) ( jwL2 ) + ( jwL2 ) + hoe ( jwL1 )( jwL2 ) j wC j wC
(1 − hfe ) w 2 L1L2 =
L1L2 L1 L2 1 2 + jhie w ( L1 + L2 ) − + hie hoe −w L1L2 + C + jwhoe C w C C
(10.60)
Equating imaginary terms on either side of Eqn. (10.60) LL 1 hie w ( L1 + L2 ) − + whoe 1 2 = 0 wC C w 2 ( L1 + L2 )C − 1 + w 2 L1L2
hoe =0 hie
h w 2 ( L1 + L2 )C + L1L2 oe = 1 hie
(10.61)
Since hoe hie is extremely small in all transistors, the above equation (10.61)can be simplified as w 2 ( L1 + L2 )C = 1 w2 =
w=
1
( L1 + L2 )C 1
( L1 + L2 )C 1
f = 2p
( L1 + L2 )C
(10.62)
Oscillators
525
Equation (10.62) gives the frequency of oscillations. Equating real terms on either side of Eqn. (10.60), −hfew 2 L1L2 = −w 2 L1L2 +
L1 L + hie hoe −w 2 L1L2 + 2 C C
−hfe = −1 − hie hoe +
L1 + hie hoe L2 w 2 L1L2C
L1 + hie hoe L2 L1L2C
−hfe = −1 − hie hoe +
hoe ( L1 + L2 )C + L1L2 hie
( L1 + hie hoe L2 ) ( L1 + L2 )C + L1L2
−hfe = −1 − hie hoe +
−hfe = −1 − hie hoe +
− hfe =
hoe hie
L1L2C L1 L h L L + 1 + hie hoe + hie hoe 2 + oe 1 + hoe2 2 L2 L1 hieC C
L1 L h L L L + hie hoe 2 + oe 1 + hoe2 2 ≈ 1 1 L2 L1 hieC C L2
(10.63)
since hoe is negligible. Hence the condition to be satisfied for the oscillations to build up and sustain is hfe ≥
L1 L2
(10.64)
Additional Solved Examples Example 10.6 In a transistor Hartley oscillator, the two inductances are 2 mH and 20 µH. The frequency is to be changed from 950 and 2050 kHz. Calculate the range over which the capacitor is to be varied. Solution: f =
f2 =
1 2p CLeq
and Leq = L1 + L2 = 2000 + 20 = 2020 µH.
1 1 Or C = 40CLeq 40 f 2 Leq
526
Electronic Devices and Circuits
When f = 950 kHz, Cmax =
1
(
40 × 950 × 10
3 2
)
= 13.71 pF
× 2020 × 10 −6
When f = 2050 kHz, 1
Cmin =
(
40 × 2050 × 10
3 2
)
= 2.95 pF × 2020 × 10 −6
C varies from 2.95 to 13.71 pF. Example 10.7 A crystal has L = 2 mH, C = 0.01 pF, and R = 2 kΩ. Its mounting capacitance is 2 pF. Calculate its series and parallel resonant frequencies. Solution: From Figure 10.30, the series resonant frequency is given as follows: fs =
1
1
= 35.62 MHz
= −3
2p 2 × 10 × 0.01 × 10 −12
2p LC
and the parallel resonant frequency is given as follows: Ceq =
fp =
CMC 2 × 0.01 = 0.00995 pF = CM + C 2 + 0.01 1
1
=
2p LCeq
−3
2p 2 × 10 × 0.00995 × 10 −12
= 35.69 MHz
Both the resonant frequencies are approximately the same. Example 10.8 A Quartz crystal has the following constants: L = 50 mH, C1 = 0.02 pF, R = 500 Ω, and C2 = 12 pF. (i) Find the values of fs and fp. (ii) If an external capacitor, Cx (stray capacitance), appearing across the crystal terminals, changes from 5 to 6 pF, find the change in the parallel resonant frequency. Solution: Given L = 50 mH, C1 = 0.02 pF, and C2 = 12 pF A A C1 C2
L
C2
Cx
Cx B
R C2′ B
Figure 10.36 Electrical circuit of the crystal when Cx is connected externally
Oscillators
(i)
527
(a) When Cx is not connected, Figure 10.36 fs =
1
= 5.035 MHz
−3
2p 50 × 10 × 0.02 × 10 −12
2p LC1
Ceq = fp =
1 =
C2C1 12 × 0.02 = 0.01997 pF = C2 + C1 12 + 0.02 1
1
=
2p LCeq
−3
2p 50 × 10 × 0.01997 × 10 −12
= 5.04 MHz
(b) When Cx is connected. C2′ = C2 / /Cx = C2 + Cx (ii) (a) When, Cx = 5 pF, C2′ = 12 + 5 = 17 pF Ceq′ =
fp′′=
C2′C1 17 × 0.02 = 0.019976 pF = C2′ + C1 17 + 0.02
1
1
= −3
2p 50 × 10 × 0.019976 × 10 −12
2p LCeq
= 5.0385 MHz
(b) When, Cx = 6 pF, C2′′ = 12 + 6 = 18 pF Ceq′′ =
fp′′=
C2′′C1 18 × 0.02 = 0.01998 pF = C2′ + C1 18 + 0.02 1 2p LCeq
1
=
2p 50 × 10 −3 × 0.0199778 × 10 −12
= 5.0383 MHz
Change in fp = fp′ − f ′′p = 5.0385 − 5.0383 = 0.0002 MHz = 200 Hz. Example 10.9 An RC phaseshift oscillator, using an FET, uses three identical phaseshifting networks in which R = 100 kΩ and C = 64.79 pF. Calculate the frequency of the oscillations and the value of RD. The FET has gm = 5 mmhos and rd = 50 kΩ. Solution: Given, R = 100 kΩ and C = 64.79 pF For the oscillator, f =
1
1 =
2pRC 6
3
2p × 100 × 10 × 64.79 × 10 −12 6
= 10.03 kHz,
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Electronic Devices and Circuits
For the oscillations to build up and sustain, A ≥ 29. We have A = gm RL or RL =
A 29 = = 5.8 kΩ. gm 5
But RL = rd / / RD 50 × RD = 5.8 kΩ 50 + RD
50 RD = 290 + 5.8 RD RR D D RD =
290 = 6.56 kΩ 44.2
Example 10.10 A crystal has L = 0.4 H, C1 = 0.085 pF, CM = 1 pF, and R = 5 kΩ. Find the following: (i) the series resonant frequency, (ii) the parallel resonant frequency, (iii) by what percent does the parallel resonant frequency exceed the series resonant frequency, and (iv) Q of the crystal. Solution: (i)
fs =
1
1 =
2p LC1
(ii) Ceq =
fp =
2p 0.4 × 0.085 × 10 −12
C1CM 1 × 0.085 = = 0.07834 pF C1 + CM 1 + 0.085 1 2p LCeq
1
=
2p 0.4 × 0.07834 × 10 −12
(iii) Percentage increase =
(iv) Q =
= 863.55 kHz
= 900.90 kHz
900.90 − 863.55 × 100 = 4.325% 863.55
wL 2p × 863.55 × 103 × 0.4 = = 433.85 R 5 × 103
Example 10.11 Find R3, C, and hfe of the transistor to generate oscillations at 50 kHz, in the RC phase shift oscillator shown in Figure 10.37. R1 and R2 are the biasing resistors. R1 = 22 kΩ, R2 = 68 kΩ, RC = 20 kΩ, R = 6.8 kΩ, and hie = 2 kΩ. Solution: The circuit of the RC phaseshift oscillator is shown in Figure 10.37.
Oscillators
529
VCC
R1
C
C
C
RC
R3 R2
R
R RE CE
Figure 10.37 Circuit of the RC phaseshift oscillator
Let
R1 ′ = R1 // R2 // hie = R = R1 ′ + R3
f= ∴
C=
C=
22 × 68 × 2 = 1.785 kΩ (22 × 68) + (68 × 2) + (2 × 22)
R3 = R − R1 ′ = 6.8 − 1.785 = 5.015 kΩ
k=
RC 20 = 2.941 = R 6.8
1 2pRC 6 + 4 k 1 2pRf 6 + 4 k 1 2p × 6.8 × 103 × 50 × 103 6 + 4 × 2.941
hfe = 4 k + 23 +
= 111.12 pF
29 29 = 4 × 2.941 + 23 + = 44.62 k 2.941
Example 10.12 In a Hartley oscillator, L1 = 15 mH, C = 50 pF and the mutual inductance, M = 5 µH. Its frequency of oscillations is 168 kHz. Calculate L2. Solution: In a Hartley oscillator, f =
1 2p LeqC
530
Electronic Devices and Circuits
where Leq = L1 + L2 ± 2M, depending on the dot convention on the coils. Leq =
1 1 = 2 4p f C 4 × 10 × 168 × 103 2
(
)
2
= 17.715 mH × 50 × 10 −12
(i)
L2 = Leq − L1 − 2M = 17.715 − 15 − 2 × 0.005 = 2.705 mH
(ii)
L2 = Leq − L1 + 2M = 17.715 − 15 + 2 × 0.005 = 2.725 mH
Example 10.13 A Colpitts oscillator has a coil of inductance, L = 120 µH, C1 = 300 pF, and C2 = 1200 pF. Find the frequency of oscillations and the minimum value of hfe required to sustain the oscillations. Solution: In a Colpitts oscillator, f = where Ceq =
1 2p LCeq
C1C2 C1 + C2 Ceq =
f=
C1C2 300 × 1200 = 240 pF = C1 + C2 300 + 1200 1
1
=
2p LCeq
−6
2p 120 × 10 × 240 × 10 −12
= 938.97 kHz
Minimum value of hfe required is hfe(min) =
C2 1200 = =4 C1 300
Example 10.14 In a Hartley oscillator, L1 = L2 = 0.5 mH and C can be varied from 100 to 500 pF. Determine the highest and the lowest frequency of oscillations and the frequency range of the oscillator. Mutual coupling between the coils is negligible. Solution: Leq = L1 + L2 = 0.5 + 0.5 = 1 mH (i)
Cmin = 100 pF
Therefore, fmax = (ii)
Cmax = 500 pF
1 2p LeqCmin
1
= −3
2p 1 × 10 × 100 × 10 −12
= 503.6 kHz
Oscillators
531
Therefore, fmin = (iii)
1
1
= −3
2p 1 × 10 × 500 × 10 −12
2p LeqCmax
= 225.18 kHz
Frequency range = fmax − fmin = 503.6 − 225.18 = 278.42 kHz
Example 10.15 Determine the maximum and the minimum frequency of the oscillations developed in the Wien Bridge oscillator, in which the phaseshifting network has R = 10 kΩ and C varies from 0.001 to 1 µF. Solution: The frequency of oscillations of a Wien Bridge oscillator is given as follows: 1 2pRC
f = Given Cmin = 0.001 µF and Cmax = 1 µF fmax =
1 = 15.92 kHz 2p × 10 × 10 × 0.001 × 10 −6 3
fmin =
1 = 15.92 Hz 2p × 10 × 103 × 1 × 10 −6
Example 10.16 A Hartley oscillator has L1 = 1 mH and L2 = 10 mH. Its frequency is required to be varied from 1000 to 2000 kHz. Determine the maximum and the minimum values of C. The mutual coupling between the coils is negligible. Solution:
f =
1 2p CLeq
f2=
and Leq = L1 + L2 = 1 + 10 = 11 µH
1 1 or C = 40CLeq 40 f 2 Leq
When f = 1000 kHz Cmax =
1 2
(
)
40 × 1000 × 103
× 11 × 10 −6
= 2273 pF
When f = 2000 kHz Cmin =
1
(
40 × 2000 × 103
2
)
× 11 × 10 −6
= 568.25 pF
C varies from 568.25 to 2273 pF. Example 10.17 For the Colpitts oscillator, C1 = 0.01 µF, C2 = 0.001 µF, L = 10 mH, and RC = 1800 Ω. Determine (i) f, the frequency (ii) b, the feedback factor (iii) Amin, the minimum gain needed to sustain the oscillations, and (iv) the value of RE, the emitter resistance that can be used to stabilize the gain.
532
Electronic Devices and Circuits
Solution: The basic Colpitts oscillator and the feedback network are shown in Figure 10.38.
+
C1
C1
Vo
L
+
C2 +
Vf
Vo
−
+ C2
−
Vf −
−
Figure 10.38 Basic Colpitts oscillator and the feedback network
( i)
f=
where Ceq =
1 2p LCeq C1C2 C1 + C2
Ceq =
f=
C1C2 0.01 × 0.001 = 909.1 pF = C1 + C2 0.01 + 0.001 1
2p LCeq
1
= 52.82 kHz
= −3
2p 10 × 10 × 909 × 10 −12
(ii)
Vf =Vo
C1 C1 0.001 or b = = = 0.091 C1 + C2 0.001 + 0.01 C1 + C2
(iii)
Amin =
1 1 = = 10.99 b 0.091
(iv)
Amin =
R RC 1800 or RE = C = = 164 Ω Amin 10.99 RE
Example 10.18 In a Colpitts oscillator, C1 = 100 pF and C2 = 1000 pF. L is varied to vary the frequency of oscillations from 1000 to 2000 kHz. Determine the range of L. Solution: In a Colpitts oscillator, f=
1 2p LCeq
Oscillators
where Ceq =
533
C1C2 C1 + C2 Ceq =
L=
C1C2 100 × 1000 = = 90.91 pF C1 + C2 100 + 1000
1 4p f 2Ceq 2
Lmax =
Lmin =
1 4p
2
2
( fmin )
1
= Ceq
1 2
4p 2 ( max ) Ceq
(
40 × 1000 × 10
3 2
)
= 275 µH × 90.91 × 10 −12
1
=
(
40 × 2000 × 10
3 2
)
× 90.91 × 10 −12
= 68.75 µH
Example 10.19 A tuned collector oscillator has an inductance of 50 µH. The frequency is to be varied from 500 to 1000 kHz. (i) Calculate the range of the capacitor. (ii) If L = 50 µH, C = 750 pF, hoe = 25 × 10−6 A/V and the resistance associated with the inductance R is 1 kΩ, calculate the exact frequency of oscillations. Solution: The approximate frequency is (i)
f=
∴
Cmin =
1 2p LC 1 2
4p 2 ( fmax ) L
and Cmax =
Cmin =
f=
4p
( fmin )2 L 1
4p
Cmax =
(ii)
1 2
2
2
( fmax )
=
4p
2
( fmin )
1
= L
(
40 × 1000 × 103
L
1 2
1
1 2
40 ( fmin ) L
2
)
× 50 × 10 −6 1
=
2p LC
(
40 × 500 × 103
1 = −6
= 500 pF
2p 50 × 10 × 750 × 10 −12
2
)
= 1000 pF × 50 × 10 −6
= 822.29 kHz
534
Electronic Devices and Circuits
The exact frequency is given as follows: 2 w exact = w 2 (t1 + hoe R (1)
eoe
)
fexact 1= f
(1 + hoe R )
1 + hoe R = 1 + 25 × 10 −6 × 1 × 103 = 1.025
(1+ hoe R ) = 1.012
fexact = f
(1 + hoe R ) = 822.29 × 1.012 = 832.16 kHz
Example 10.20 A tuned collector oscillator oscillates at 1000 kHz. If C is increased by 50%, calculate the new frequency. Solution: The frequency of oscillations with C is, f1 =
1 2p LC
the new value of capacitance C1 = 1.5C. Therefore, f2 =
. When C is increased by 50%,
1 2p
(1.5C ) L
f2 1 2p LC 1 = × = = 0.8167 f1 2p 1.5CL 1 1.5
f2 = 0.8167 × f1 = 0.8167 × 1000 = 816.7 kHz
Summary • In order to obtain oscillations, the condition (1 + Ab ) = 0 is to be satisfied. This condition is called Barkhausen criterion. • In an oscillator, the external input is zero, but there results an output signal whose frequency depends mainly on the tuned circuit. • Positive feedback is used in an oscillator. • LC oscillators are used in the RF range, and RC oscillators are used in the audio frequency range. • The Q of the tank circuit used in LC and RC oscillators is small, and hence the frequency of the oscillations so generated may not necessarily be stable. • Crystal oscillators are used to generate stable oscillations. • In a beat frequency oscillator two highfrequency signals generated by crystal oscillators are heterodyned or mixed in a mixer, giving rise to stable audio oscillations.
multiple ChoiCe QueStionS 1. The type of feedback used in an oscillator for oscillations to build up is (a) degenerative feedback (b) regenerative feedback (c) composite feedback (d) none of these
Oscillators
535
2. The Barkhausen criterion is given by the following relation:
(a ) (1 + Ab ) = 0
( b ) (1 + Ab ) > 1
( c ) (1 + Ab ) < 1
( d ) Ab >> 1
3. LC oscillators are not used in the audio frequency range mainly because (a) positive feedback cannot be used (b) negative feedback cannot be used (c) size of the inductor is very large (d) size of the inductor is small 4. LC oscillators are mainly used in the (a) radio frequency range (b) audio frequency range (c) ultrasonic frequency range (d) none of these 5. In a practical LC oscillator, the frequency of oscillations is (a) slightly less than the resonant frequency of the tank circuit (b) slightly more than the resonant frequency of the tank circuit (c) much less than the resonant frequency of the tank circuit (d) much more than the resonant frequency of the tank circuit 6. In a Colpitts oscillator, L = 10 µH , C1 = C2 = 20 pF , then the approximate radial frequency is (a) 100 × 106 radians (b) 15.92 MHz (c) 100 MHz (d) 200 MHz 7. In a Hartley oscillator, C = 10 pF , L1 = L2 = 55 mH, then the approximate radial frequency is (a) 100 × 106 radians (b) 15.92 MHz (c) 100 MHz (d) 200 MHz 8. The amplitude condition to be satisfied in an RC phaseshift oscillator using a BJT for oscillations to build up and sustain, when k = 2 is
(a ) hfe ≥ 45.5
( b ) hfe ≥ 52
( c ) hfe ≥ 29
( d ) hfe ≥ 23
9. The best Q of the tank circuit for better frequency stability is (a) 10 (b) 100 (c) 1000 (d) 50,000 10. To generate stable audio frequencies the oscillator used is (a) Beat frequency oscillator (b) Hartley oscillator (c) Colpitts oscillator (d) Tuned collector oscillator
Short anSwer QueStionS 1. What is the main difference between an amplifier and an oscillator? 2. What is the Barkhausen criterion, and what are the two conditions that need to be satisfied for the oscillations to build up and sustain? 3. Why are LC oscillators not preferred in the audio frequency range? 4. Between the Colpitts and Hartley oscillators, which is more preferred and why? 5. What are the two main advantages of the Clapp oscillator over the Colpitts oscillator?
536
Electronic Devices and Circuits
6. Why and where crystal oscillators are used? 7. How is amplitude stability achieved in a Wien bridge oscillator using two transistor amplifiers? 8. Why is the beat frequency oscillator used in the audio frequency range, in preference to an RC oscillator? What is its main limitation?
long anSwer QueStionS 1. Draw the circuit of a Colpitts oscillator and derive the expression for its frequency of oscillations. Also obtain the condition for the oscillations to build up and sustain. Assume ideal components. 2. Draw the circuit of a Hartley oscillator and derive the expression for its frequency of oscillations. Also obtain the condition for the oscillations to build up and sustain. Assume ideal components 3. Draw the circuit of a tuned collector oscillator and derive the expression for its frequency of oscillations. Also obtain the condition for the oscillations to build up and sustain. Assume that the inductor has an associated resistance. 4. Draw the circuit of a Wien bridge oscillator and derive the expression for its frequency of oscillations. Also obtain the condition for the oscillations to build up and sustain. 5. Draw the circuit of a RC phase shift oscillator using an FET and derive the expression for its frequency of oscillations. Also obtain the condition for the oscillations to build up and sustain. 6. Draw the circuit of a RC phase shift oscillator using a BJT and derive the expression for its frequency of oscillations. Also obtain the condition for the oscillations to build up and sustain. 7. Write short notes on (i) Crystal oscillators (ii) Beat frequency oscillators
unSolved problemS 1. A tuned collector oscillator has an inductance of 100 µH. If its frequency is to be varied in the range 100–1000 kHz, determine the maximum and the minimum values of C. 2. A Hartley oscillator has L1 = 100 µH and L2 = 1 mH and C = 100 pF. (i) Find the operating frequency if the coupling between the coils is negligible. (ii) Repeat the calculation if the coefficient of coupling between the coils k = 0.0316. 3. A Colpitts oscillator has a coil of inductance, L = 100 µH, C1 = 200 pF and C2 = 1000 pF. Find the frequency of oscillations and the minimum gain required to sustain the oscillations. 4. In an RC phase shift oscillator using an FET, the RC network uses R = 5 kΩ and C = 0.01 µF. What is the operating frequency and the phase shift produced by each RC network? 5. Determine the frequency range of operation of the Wien Bridge oscillator, if R = 4.7 kΩ and C varies from 0.001 to 1 µF.
11
POWER AMPLIFIERS
Learning objectives After going through this chapter, the reader will be able to
11.1
Understand the classification of power amplifiers, namely, class A, class B, and class C Analyze power amplifiers using the graphical procedure Calculate the output power, harmonic distortion, and the conversion efficiency of seriesfed and singleended transformercoupled classA power amplifiers Realize the need for classA and classB push–pull power amplifiers Appreciate the need for eliminating transformers in power amplifiers as in complementary push–pull power amplifiers Understand the relevance of classD and classS power amplifiers Understand the need for heat sinks in power amplifiers
INTRODUCTION
ib
Smallsignal amplifiers, also called voltage iC amplifiers, are amplifiers in which the input IC(sat) signal swing is so small that the operation of the transistor is restricted to a small limited region in the transfer characteristic, in which region the characteristic is linear. As such ic A small signal amplifiers are also called linear I IC1 0 Q1 I = C(sat) amplifiers as shown in Figure 11.1. A voltage C1 wt 2 amplifier gives only voltage gain but not the B necessary power output. However, if the input swing is large, the operation is not restricted to a small linear 0 IB1 region in the transfer curve, but stretches iB into the nonlinear region. Then, the amplifier 0 is called a largesignal amplifier or a power amplifier as shown in Figure 11.2. A power amplifier gives the necessary power output so Figure 11.1 Voltage amplifier or smallsignal amplifier as to drive a loud speaker or a relay. The output of a voltage amplifier is usually the input to a power amplifier. Power amplifiers are classified as (i) classA power amplifier, (ii) classB power amplifier, and (iii) classC power amplifier. wt
538
Electronic Devices and Circuits
wt
(i) ClassA power amplifier is one in which there is output for the entire input cycle period. For this to happen, the transistor is required to be biased in the active region. Thus, all voltage amplifiers are biased in the active region; Figures 11.1 and 11.2 represent classA operation of voltage and power amplifiers. The major limitation of classA operation is that even when there is no input, there is appreciable power dissipation ( PD = VCE I C ) in the transistor. If a battery is used as a dc source for biasing the transistor, the life of the battery is reduced as there is drain on the battery even under quiescent (nosignal) condition. The life of a battery is usually specified in amperehours. (ii) ClassB power amplifier is one in which there is iC output for exactly onehalf of the input cycle IC(sat) period. This means that the transistor conducts during only one half cycle of the input signal period (X) and is OFF during the other A ic half cycle (Y) as shown in Figure 11.3. There IC Q is no output during the shaded region (Y). In wt this type of operation, the transistor is biased at cutoff. Under quiescent condition, there is no current drawn from the dc source, and hence B there is no dissipation in the transistor under 0 nosignal condition. This gives a longer life for IB iB 0 the battery, which is desirable, particularly when the amplifier is used in remote places ib where there is no access to conventional power to derive the necessary dc voltage using a transformer, rectifier, and filter. ClassA and Figure 11.2 Large signal or power amplifier classB power amplifiers are used mostly for audiofrequency applications. iC (iii) ClassC power amplifier is one in which IC(sat) the output current flows for less than one half of the input cycle period (Figure 11.4). Consequently, the output is in the form of pulses. There is IC no output during the shaded region. Such an output, we know from Fourier analysis, contains many freX quency components. In order to get back the original signal in the outQ put of the power amplifier, a tuned iB 0 0 p 0 circuit or filter is used. ClassC power X amplifiers are usually tuned power Y p amplifiers that are used in the radio2p frequency range. They are also used as harmonic generators. Figure 11.3 ClassB operation In addition to the classifications mentioned till now, we have many more classifications, of which we will subsequently consider the principle of operation of classD and classS power amplifiers.
Power Amplifiers
539
iC IC(sat)
IC
X Q iB
0
q1
q2
q1
0
X p
q2
2p
Figure 11.4 ClassC operation
11.2
DISTORTION IN POWER AMPLIFIERS
In a smallsignal amplifier if the input swing ib varies as I bm coswt , the output collector current swing also varies as ic = I cm cos wt. There is no amplitude distortion in the output, and hence no frequency distortion. The output has the same frequency as the input. Let now the input swing be increased further, so that in the region of operation in the transfer curve is represented by a parabola with the operating point as the vertex. Then, even though the input has only one frequency w, as the amplitude of the signal in the output gets distorted, which results in frequency distortion (Figure 11.2). As ib = I bm coswt , we can write for ic as follows: ic = G1ib + G2 ib 2 = G1I bm cos wt + G2 ( I bm cos wt )2 = G1I bm cos wt +
G2 I bm 2 (1 + cos 2wt ) 2
Therefore, ic can be written as follows: ic = B0 + B1 cos wt + B2 cos 2wt
(11.1)
where B0 = B2 =
2 G2 I bm and B1 = G1I bm 2
From Eqn. (11.1), it can be noted that the output of the power amplifier not only contains the required fundamental frequency, w, but also contains an unwanted dc component of current B0 and a second harmonic component 2w, having a magnitude B2 . Thus, we say that the output contains harmonic distortion. If, alternatively, the operation is not restricted to a small limited region, then ic can be expressed as power series:
540
Electronic Devices and Circuits
ic = G1ib + G2 ib 2 + G3ib3 + G4 ib 4 + ... Then, ic can be written as follows: ic = B0 + B1 cos wt + B2 cos 2wt + B3 cos 3wt + B4 cos 4wt + ...
(11.2)
where Bn , n = 1,2,3,4,… represent the magnitudes of various frequency components. Thus, higher order harmonics can also be present in the output. The magnitudes of the higher order components are usually smaller. It is the second harmonic component that is usually the worst offender. Thus, it is established that harmonic distortion is invariably present in the output of a power amplifier. In a subsequent section, we try evaluate the magnitudes of Bs and think of methods to minimize harmonic distortion.
11.3
CLASSA POWER AMPLIFIER
A classA power amplifier, as defined earlier, is an amplifier in which the transistor is ON for entire input cycle period. If the transistor is biased in the active region, then the type operation is called classA operation. The main limitation of classA operation is the dissipation in the transistor even under nosignal condition. We now consider a few classA power amplifier circuits.
11.3.1 SeriesFed ClassA Power Amplifier VCC The voltage amplifier considered in Chapter 6 (CE amplifier) can be used as a power amplifier; the only difference now is that RL the input swing is large. Consider the amplifier circuit shown in Figure 11.5. This is called seriesfed power amplifier because Ic + the load RL is directly connected to the collector terminal. Cc Vo To calculate the output voltage and hence the ac output power, Q we cannot use the smallsignal model of the transistor. The Ib method of analysis is, therefore, essentially graphical method. RB The procedure to calculate the output power is to first plot the + Vs output characteristics of the given transistor, draw the dc load VBB line, and locate the Qpoint. Then, draw the ac load line, superimpose a suitable base current swing on the output curves, and find out the corresponding collector current swing and the permissible collector voltage swing. Next, we can calculate the outFigure 11.5 A seriesfed classA put power as illustrated here using Figure 11.6. To draw the dc power amplifier load line, we locate two points IC(sat) = VCC/RL and VCE(cutoff) = VCC. The Qpoint is then located. The ac load in this case is the same as the dc load. The base current swing, ib = I bm cosw t is selected such that the output current and voltage swings are symmetric with respect to the operating point. The corresponding ic and vc swings are represented on the output curves. Vm and Im are the maximum voltage and current swings. V(max), V(min), I(max), and I(min) are now obtained.
Calculation of the ac Output Power The ac output power Po = VcIc, where Vc is the rms value of the output voltage and Ic is the rms value of the output current.
Power Amplifiers
541
IB(max) iC IC(sat) IB
I(max)
ib = Ibmcoswt Im IC
IB(min)
Q
wt
0 dc and ac load line
I(min) 0 VCC V(max)
0 V(min)
VC
vCE
wt
Vm
Figure 11.6 Graphical method of analysis
From Figure 11.6, Vm = and Im =
V(max) −V(min) 2 I (max) − I (min) 2
Vc =
Vm V(max) − V(min) = 2 2 2
(11.3)
Ic =
I m I (max) − I (min) = 2 2 2
(11.4)
and
Therefore, the ac output power is
(
)(
V(max) − V(min) I (max) − I (min) V(max) − V(min) I (max) − I (min) Po = PL = Vc I c = = 8 2 2 2 2
)
(11.5)
Calculation of B 0 , B 1, and B 2 From Eqn. (11.1) we have ic = B0 + B1 cos wt + B2 cos 2wt , where iC is the alternating component of collector current. Therefore, the instantaneous total value of collector current iC is the sum of the ac component iC and the dc component IC. iC = ic + I C = I C + B0 + B1 cos wt + B2 cos 2wt
(11.6)
In Eqn. (11.6), there are three unknowns, namely, B0, B1, and B2. To evaluate these three unknowns, we need three equations. For getting these three equations, we set the following conditions:
542
Electronic Devices and Circuits
(i) When wt = 0, From Figure 11.6, iC = I (max) Using Eqn. (11.6), I (max) = I C + B0 + B1 + B2
(11.7)
I C = I C + B0 − B2
(11.8)
I (min) = I C + B0 − B1 + B2
(11.9)
p , 2 From Figure 11.6, iC = I C (ii) When wt =
Using Eqn. (11.6),
(iii) When wt = p , From Figure 11.6, iC = I (min) Using Eqn. (11.6),
Solving Eqs (11.7), (11.8), and (11.9), B1 =
(I
(max)
− I (min) )
(11.10)
2
and B0 = B2 =
I (max) + I (min) − 2 I C
(11.11)
4
Using Eqs (11.10) and (11.11), B0, B1, and B2 are calculated. B1 and B2 are the maximum values of the fundamental and the second harmonic components of currents. The total output power PL is now due to the fundamental and the second harmonic components. B 2R B 2R B 2R PL = 1 L + 2 L = 1 L 2 2 2 where the second harmonic distortion, D2 =
(
B 2 1 + 2 = P1 1 + D2 2 B1
(
)
(11.12)
B2 and P1 is the power due to the fundamental B1 2
)
component. If D2 = 10%, then PL = P1 1 + ( 0.1) = 1.01P1. To calculate the magnitudes of the higher order harmonics: If there is need to calculate the magnitudes of higher order harmonics as given by Eqn. (11.2), it is required to get five equations. To get five equations, in addition to the conditions imposed earlier, we have to impose two more
Power Amplifiers
543
additional conditions. We now additionally consider iC at ib = Ibm/2 and − Ibm/2 and name the corresponding values of i as I 1 and I − 1 as indicated in Figure 11.7. C
2
2
We have, using Eqn. (11.2), iC = I C + B0 + B1 cos wt + B2 cos 2wt + B3 cos 3wt + B4 cos 4wt + ...
(11.13)
From Figure 11.7, IB(max) iC
Ibm/2
IC(sat)
IB
I(max)
ib = Ibmcoswt −Ibm/2
I1/2
Im
IC
Ibm
Q
wt
IB(min)
I1/2
0
0 dc and ac load line
I(min)
123p
V(min)
vCE
VCC V(max)
0
1 = p/3 2 = p/2 3 = 2p/3
VC wt
Vm
Figure 11.7 Fivepoint method to calculate B0, B1, B2, B3, and B4
p , iC = I 1 2 3 2p (iv) When wt = , iC = I − 1 2 3
(i) When wt = 0, iC = I (max)
(ii) When wt =
p , iC = I C 2 (v) When wt = p , iC = I (min)
(iii) When wt =
Substituting the above five conditions in Eqn. (11.13), we get five equations; and by solving the five equations, popularly known as the Espley’s method, we get 1 I (max) + 2 I 1 + 2 I − 1 + I (min) − I C 2 2 6 1 B1 = I (max) + I 1 + I − 1 + I (min) 2 2 3
B0 =
( (
)
)
1 ( I (max) − 2I C + I (min) ) 4 1 B3 = I (max) − 2 I 1 + 2 I − 1 − I (min) 2 2 6 1 B4 = I (max) − 4 I 1 + 6 I C − 4 I − 1 + I (min) 2 2 6
(11.14)
B2 =
( (
)
)
544
Electronic Devices and Circuits
Using Eqn. (11.14), PL =
B12 RL 1 + D2 2 + D32 + D4 2 = P1 1 + D 2 2
(
)
(
)
(11.15)
where D 2 = ( D2 )2 + ( D3 )2 + ( D4 )2
(11.16)
Calculation of Conversion Efficiency The effectiveness with which the power amplifier is able to convert the given total dc input power into the required ac output power is given by the conversion efficiency, h of the power amplifier. Conversion efficiency, h =
P Ac output power = L Total dc input power PBB
Conversion efficiency h is usually expressed as a percentage. Using the simplified presentation of Figure 11.7 by avoiding the output curves as shown in Figure 11.8, we have iC I(max)
IC
Q dc and ac load line VCC
I(min) 0 V(min) 0
0
vCE
V(max)
VC
Figure 11.8 Simplified representation of Figure 11.7
V( max ) ≈ VCC ,V( min ) ≈ 0, I ( min ) ≈ 0 and I ( max ) = 2 I C and substituting these values in Eqn. (11.5),
PL (max) = and
(V
(max)
−V(min) ) ( I (max) − I (min) ) 8
=
VCC × 2 I C VCC I C = 8 4
(11.17)
Power Amplifiers
PBB = VCC I C
h(max) =
PL (max) PBB
545
(11.18)
VCC I C = 4 × 100 = 25% VCC I C
(11.19)
It is evident from Eqn. (11.19) that a seriesfed classA power amplifier has a maximum conversion efficiency of only 25 percent. This means that if a total dc input power of 1 W is given to the power amplifier, only 0.25 W is available as the required ac output power. The rest of the power of 0.75 W is dissipated in the transistor and the load; that is, it is simply wasted in heating the transistor and the load. This is the major disadvantage of this amplifier.
Power Dissipation in the Transistor, PD Consider the
VCC
output circuit of the power amplifier as shown in Figure 11.9. From Figure 11.9, it can be noted that there is a dc component of current I C in RL and also an rms component of current I c due to the input signal and an rms component of voltage Vc across the load. PD is the power dissipation in the transistor and VC is the dc voltage at the collector. Therefore, the total dc input power is the sum of the dc power dissipated in RL , ac power in the load, and the power dissipated in the transistor. VCC I C = I C 2 RL + Vc I c + PD
RL
IC
Ic
+ Vc ,VC Q PD
(11.20)
Also (11.21)
VCC = VC + I C RL
Figure 11.9 Circuit to calculate PD
Substituting Eqn. (11.21) in Eqn. (11.20),
(VC + I C RL ) I C = I C 2 RL + Vc I c + PD Therefore, VC I C = Vc I c + PD PD = VC I C − Vc I c
(11.22)
PD is maximum when the second term in Eqn. (11.22) is zero: PD(max) = VC I C
(11.23)
VC = Vm = 2Vc and I C = I m = 2 I c
(11.24)
But from Figure 11.8,
546
Electronic Devices and Circuits
Substituting the relations in Eqn. (11.24) in Eqn. (11.23), (11.25)
PD(max) = VC I C = 2Vc × 2 I c = 2Vc I c = 2 PL (max)
From Eqn. (11.25), it can be noted that the amount of dissipation that occurs in the device is twice the maximum amount of ac output power that one desires to get at the output of the power amplifier. Therefore, if PL (max) = 1 W, then one should choose a transistor with a power dissipation capability of at least 2 W. This means that the choice of transistor depends on the desired ac output power. The larger the desired ac output power, the larger the power dissipation capability of the transistor. PD(max) = PT is specified by the manufacturer at 25°C. As the temperature increases, PD(max) will be less than the value specified at 25 °C. Manufacturer either supplies the derating curve or specifies the derating factor.
Derating Factor and Derating Curve Let for a transistor PD(max) = PT (at25°C) = 5 W (say). If the derating factor is specified as D = 25 mW/ °C, then it means that for every degree rise in temperature, the power dissipation capability decreases by 25 mW. The change in power is given as follows: ∆P = D(TA − 25°C ) = (25°mW / °C ) (TA − 25°C ) where TA is the ambient temperature. If the power dissipation capability of the transistor is to be obtained at 100°C, then
PD(max) 5
∆P = ( 25mW / °C)(100 − 25 ) = 25 × 75 = 1.875 W
(11.26)
W
3.125
∴ PD(max) = PT (at100°C ) = 5 − 1.875 = 3.125 W Alternatively, the derating curve as shown in Figure 11.10 is given in the data sheet. From Figure 11.10, it is possible to find out PD(max) at a given temperature. From Figure 11.10, PD(max) = 3.125 W.
0
100
TA °C
Figure 11.10 Derating curve
Example 11.1 A classA seriesfed power amplifier delivers power to a load of 15 Ω. VCC = 20 V and the coordinates of the Q point are VC = 10 V and IC = 0.5 A. The ac output current swing is ±0.45 A. Determine (i) PBB, (ii) the dc power wasted in RL, (iii) ac power delivered to RL, (iv) PD, and (v) h. Solution: Given VCC = 20 V, IC = 0.5 A, VC = 10 V, and the ac current swing = Im = 0.45 A. (i) PBB = VCC I C = 20 ×0.5 = 10 W . (ii) Dc power wasted in RL = I C 2 RL = ( 0.5 )2 × 15 = 3.75 W
Power Amplifiers
IC =
Im
0.45 =
2
547
= 0.318 A
2
(iii) Ac power delivered to RL , PL = ( 0.318)2 × 15 = 1.52 W (iv) PD = PBB − dc power wasted in RL − ac power delivered to RL PD = 10 − 3.75 − 1.52 = 4.73 W (v) h=
1.52 × 100 = 15.2% 10
Example 11.2 A transistor delivers a power of 1 W to a load RL of 1 kΩ. The quiescent collector current is 30 mA and the collector current with signal is 35 mA. Determine D2. Solution: The quiescent collector current IC = 30 mA. The dc collector current with signal = 35 mA = IC + Bo ∴
Bo =
(I C + Bo ) − I C = 35 − 30 = 5 mA
We know that Bo = B2 = 5 mA. Also, we know that PL = ∴
B12 =
B12 RL 2
2 PL 2 ×1 2 = 2 × 10 −3 = 2000 × 10 −6 ( A ) = RL 1 × 103
B1 = 2000 mA = 44.72 mA ∴
D2 =
B2 5 × 100 = × 100 = 11.18% B1 44.72
It can be noted that the procedure to calculate PL and the magnitudes of Bs is by using the graphical method. It is found out that for a classA power amplifier, PD(max) = 2PL(max) and h for a classA seriesfed power amplifier is only 25 percent.
11.3.2 ClassA TransformerCoupled Power Amplifier h for a seriesfed power amplifier is poor mainly because of the fact the load resistance RL is small when compared to the output resistance of the amplifier. From maximum power transfer theorem, we know that for maximum power to be transferred from the generator to the load the load must, in the simple case, be equal to the internal resistance of the generator, which in this case is the output resistance of the amplifier. Therefore, if h is to be improved, it is required that RL = Ro. The loads in power amplifiers are lowimpedance loads, like the impedance of the voice coil of the loud speaker that typically is of the order of 3 Ω, 8 Ω, 16 Ω, 32 Ω, and so on, and the output resistance of the amplifier is of the order of few kiloohms. Hence, there arises the need for an impedance matching transformer as shown in Figure 11.11.
548
Electronic Devices and Circuits
We know that
I1
N V1 N1 I = and also that 2 = 1 I1 N 2 V2 N 2 ∴
V1 I 2 N1 × = V2 I1 N 2
I2 +
+ N2
N1
R′L V1 2
V2
RL


Figure 11.11 Impedance matching transformer
Hence, 2
V1 N1 V2 = I1 N 2 I 2 Therefore, R ′L = a 2 RL
(11.27)
If RL is the load on the secondary side, the load reflected on to the primary side is R′ L and a is the turns ratio of the transformer. Thus, the ac load is different from the dc load. ′ 2 If RL = 10 Ω and a = 50, then RL = (50 ) × 10 = 25 kΩ. If the output resistance of the amplifier is 25 kΩ, then impedance matching is achieved. By choosing proper a we can get desired R ′ L .
Procedure to Draw the ac Load Line to Predict the Possible Signal Swing at the Output We have seen in Chapter 5 the method to locate the Qpoint by drawing the dc load line. Consider the circuit in Figure 11.12, its dc circuit in Figure 11.13, and the ac circuit in Figure 11.14. VCC
VCC
IC
RC R1
RL
R1
Cc
IB
+
+ VBE −
Cc RL
+ Vs
Vo
R2 RE
+ V2
R2 RE
−
Figure 11.12 Amplifier circuit
Figure 11.13 DC circuit
Power Amplifiers
549
ic vce
+ −
RL
rc = RC RL
RC
ie re = RE
RE
Figure 11.14 AC circuit
The dc load line is drawn by locating I C (sat ) and VCE(cut −off ) . From Figure 11.13, I C(sat) =
VCC and VCE ( cut −off ) = VCC RC + RE
Preferably, the Qpoint is located such that under quiescent condition, I C = I CQ =
I C(sat)
, and the 2 corresponding VCE is termed VCEQ (Figure 11.15). The ac load line is now drawn using the ac circuit in Figure 11.14, where rc is the ac resistance in the collector circuit and re is the ac resistance in the emitter loop. We have from Figure 11.14,
iC IC(sat)
ICQ =
IC(sat) 2
ac load line
Q dc load line
0
VCEQ
vCE
VCC
Figure 11.15 Drawing the ac load line
vce + ie re + ic rc = 0
since
ie ≈ ic , ic =
−vce rc + re
When an ac signal is applied, it causes the change in the collector current and voltage.
(11.28)
550
Electronic Devices and Circuits
Therefore, ic = iC − I CQ and vce = vCE − VCEQ
(11.29)
Substituting the conditions in Eqn. (11.29) in Eqn. (11.28), iC − I CQ =
iC =
VCEQ rc + re
−(vCE − VCEQ ) rc + re + I CQ −
vCE rc + re
(11.30)
Equation (11.30) is in the form of y = mx + c . To draw this straight line, (i) Set vCE = 0 , then iC =
VCEQ rc + re
+ I CQ
(ii) Set iC = 0, then vCE = VCEQ + I CQ ( rc + re ) These two points are located in Figure 11.15 and the line joining these two points is the ac load line that passes through the Qpoint. The ac load lines are different for different values of rc and re. Example 11.3 For the amplifier circuit shown in Figure 11.12, RC = 1kΩ, RE = 1kΩ, RL = 0.5 kΩ, and VCC = 30 V . Under ac conditions, RE is effectively bypassed by CE. (i) Draw the dc load line and locate the Qpoint and (ii) draw the ac load line. Solution: (i) To draw the dc load line, we have I C(sat) =
VCC 30 = 15 mA = RC + RE 1 + 1
VCE ( cut −off ) = VCC = 30 V and I CQ =
I C(sat) 2
=
15 = 7.5 mA 2
and VCEQ = VCC − I CQ ( RC + RE ) = 30 − 7.5 (1 + 1) = 15V. 1 (ii) To draw the ac load line, from Figure 11.14, we have rc = RC / / RL = 1kΩ / /0.5 kΩ = kΩ , 3 and since RE is effectively bypassed by CE , re = 0 .
∴ iC =
VCEQ rc + re
+ I CQ =
15 + 7.5 = 45 + 7.5 = 52.5 mA 1 3
and 1 vCE = VCEQ + I CQ (rc + re ) = 15 + 7.5 = 15 + 2.5 = 17.5 V 3
Power Amplifiers
551
The dc and ac load lines are drawn as in Figure 11.16. mA 52.5 15
ac load line
7.5
Q dc load line
0 15
17.5
30
V
Figure 11.16 Dc and ac load lines for Example 11.3
A SingleEnded TransformerCoupled ClassA Power Amplifier A classA singleended transformercoupled amplifier is shown in Figure 11.17. The ac circuit of Figure 11.17, assuming that R1 and R2 are large, is shown in Figure 11.18. CE and CB ideally behave as short circuits. To calculate the ac output power, once again we resort to graphical procedure. The dc load for the amplifier is the dc resistance offered by the primary winding of the output transformer, which is negligibly small, typically of the order of few ohms (say 10 Ω). Then the dc load line is almost a vertical line. An appropriate Q point is chosen on the dc load line, ensuring that the output voltage swing is symmetric with reference to the Q point. The point where the dc load line intercepts the VCEaxis is VCC. If RL is the load, R′L is the impedance reflected on to the primary side of the output transformer, which is the ac load for the amplifier. Therefore, the ac load line, with a slope equal to −1 RL′ and passing through the Q point, is drawn to find out the permissible output swing as indicated in Figure 11.19.
VCC N1 R1
N2 + RL Vo
R ′L
RS + N3
Vs −
N4 CB
R2
RE
CE −
Figure 11.17 ClassA singleended transformercoupled power amplifier
552
Electronic Devices and Circuits
N1
RS
N2
R ′L
+ Vs
RL
N4
N3
+ Vo −
−
Figure 11.18 AC circuit of Figure 11.17 dc load line
I(max)
IC
Q ac load line for R′L VCC
I(min) 0 V(min) 0
0
vCE
VC = VCC V(max)
Figure 11.19 Graphical procedure to calculate PL′ of transformercoupled power amplifier
As discussed in Section 11.3, V( max ) ,V( min ) , I ( max ) , and I ( min ) are located on the characteristics, and the ac output power is calculated using Eqn. (11.5). From Figure 11.19, the quiescent voltage VC = VCC and is given as follows: (V(max) +V(min) ) VC = (11.31) 2 The rms value of the output swing is
Vc =
(
V(max) − V(min) VC = 2 2 2
)
and I c =
IC 2
(11.32)
Using Eqs (11.31) and (11.32), the power on the primary side of the output transformer PL′ is PL′ =
and
PBB =
(V
(max)
− V(min)
2 2
(V
(max)
+ V(min) 2
)× I )×I
C
2
C
Power Amplifiers
(V
(max)
)
− V(min) ×
P′ 2 2 ∴h = L = PBB V(max) + V(min)
(
2
553
IC
)×I
2 × 100%
(11.33)
C
If V( min ) = I ( min ) = 0 then PL′ = PL′ ( max ) Hence, from Eqn. (11.33), h( max ) = 50% The maximum conversion efficiency in the case of a singleended transformercoupled classA power amplifier, therefore, is 50 percent. This means that if the total dc input power is 1 W, then the available ac output power is 0.5 W. Certainly, there is improvement over a seriesfed classA power amplifier. Example 11.4 In a singleended transformercoupled power amplifier operated under classA condition, the operating point is adjusted for symmetrical swing. The amplifier is required to deliver a maximum power of 6 W to a load of 3 Ω. VCC = 18 V and assume V( min ) = 0. Find (i) α, (ii) the peak collector current Im, (iii) coordinates of the Qpoint, and (iv) h. Efficiency of the transformer is 75 percent. Solution: (i) As the efficiency of the transformer is 75 percent, then PL′ ( max ) =
PL 6 = = 8W hT 0.75
And with V( min ) = 0 , Vm = VCC = 18 V P ′ L (max ) =
RL′ =
Vm 2 2RL ′ Vm 2 18 × 18 = = 20.25 Ω 2×8 2 PL′ (max)
RL′ = a 2 RL a2 =
RL′ 20.25 = = 6.75, RL 3
a = 2.6
554
(ii)
Electronic Devices and Circuits
PL′ ( max ) =
I m2 RL′ 2
I m2 =
2 PL(max) ′ ′ L
R
=
2×8 = 0.79 20.25
I m = 0.89A
(iii) With Vmin = 0 , Vm = VCC = 18 V and I C = I m = 0.89 A (iv) PBB = VCC I C = 18 × 0.89 = 16.02 W
h(max) =
PL(max) ′ PBB
× 100 =
8 × 100 = 49.94% 16.02
Limitations of SingleEnded TransformerCoupled ClassA Power Amplifier 1. Although the conversion efficiency is double the conversion efficiency of a seriesfed power amplifier, this is still a classA power amplifier, PD( max ) =2PL′ ( max ). 2. In Section 11.2 the procedure to calculate Bs is discussed, in which B0 to B4 are calculated for one RL. But choosing different values of a, RL′ will be different, for each value of a. Hence, ′ the values of Bs and PL(max) are now calculated and plotted as in Figure 11.20. From Figure ′ 11.20, it can be seen that for a load RL1 , though distortion is minimum, the amount of PL′ ′ ′ derived is only PL1, which is smaller than PL(max) . This says that if distortion is to be small, then the amount of ac output power derived is smaller than the maximum power. This means that you are sacrificing power to reduce distortion. On the contrary, if maximum output power is the requirement, then there is an excessive associated distortion, as in the ′ case of RL2 . Thus, there is need to adjust RL′ to derive the necessary power, of course, with an inevitable amount of distortion. It is obvious here that there is a need to compromise. P′L P ′L(max) P′L1 % Distortion D D2 D3 D4 0
R′L2
R′L1
R′L
′ L and distortion as a function of
Figure 11.20 P
RL′
3. The transformer is a magnetic circuit. The dc resistance offered by the primary winding of the transformer is practically zero so that the dc collector current of the transistor is very large. Such large IC results in large magnetic flux density B. This could result in saturation of the magnetic circuit, and hence can cause distortion as shown in Figure 11.21. This is another limitation of this circuit.
555
Power Amplifiers B, Flux density BQ
QM, Operating point of the magnetic circuit
0
0
HQ
H, Magnetizing force
Figure 11.21 Large IC resulting in saturation of the magnetic circuit
11.3.3 ClassA Push–Pull Power Amplifier The two major limitations of a singleended transformercoupled power amplifier, namely excessive distortion and saturation of the magnetic circuit of the amplifier, can be eliminated by using a push–pull configuration. A classA push–pull power amplifier is shown in Figure 11.22. ic1 ib1
RS +
IB1 + Vs1 VBE1
Q1
IC1 R1
N1
io
R′L
N2
Vs − Ti
ib2
R2 Vs2 VBE2 + IB2
−
RL
VCC R′L
Q2
IC2
N1 To
ic2
Figure 11.22 ClassA push–pull power amplifier
From Figure 11.22, it can be seen that two identical NPN transistors Q1 and Q2 are used in this amplifier. Each of these transistors is operated under classA condition. The necessary VBE of Q1 and Q2 is derived by R1 and R2. The waveforms are shown in Figure 11.23. Ti and To are the input and the output centertapped transformers. The characteristic of a centertapped transformer is that the signals Vs1 and Vs2 are equal in magnitude but opposite in phase as indicated by the dots. The quiescent base currents IB1 = IB2 = IB. When the input signals are present iB1 increases and iB2 decreases. Consequently, iC1 increases and iC2 decreases. The output current io is proportional to (ic1 − ic2) or io = k(iC1 − iC2), because of the output centertapped transformer, To. Hence, io goes through the positivegoing halfcycle. During the period when Vs1 goes through the negativegoing period, Vs2 goes through the
iB1
ib1
IB1 0 iB2
ib2
IB2 0 Push io = k(iC1−iC2) 0 io = k(iC2−iC1)
Pull
Figure 11.23 Waveforms of the currents
556
Electronic Devices and Circuits
positivegoing period. Hence, iB2 increases and iB1 decreases, and the output current io is now proportional to (iC2 − iC1) or io = k(iC2 − iC1), and is negative because of the phase shift provided by To. In this amplifier when io = k(iC1 − iC2), the output is pushed up (positivegoing signal) and when io = k(iC2 − iC1), the output is pulled down (negativegoing signal). It is for this reason this circuit is named push–pull amplifier. The output voltage in the load RL is not necessarily a sinusoidal signal. We know that distortion can be present in this amplifier as well. But it is mentioned when considering this amplifier configuration that this will eliminate saturation of the magnetic circuit and also will minimize distortion. Let us see how the push–pull amplifier achieves these twin objectives.
Elimination of Saturation Problem of the Magnetic Circuit From Figure 11.22, it can be seen that IC1 and IC2 are equal dc collector currents of Q1 and Q2, but they flow in opposite directions in onehalf of the primary winding of To. Hence, saturation problem of the magnetic circuit of the amplifier that could give rise to distortion is eliminated.
Elimination of Even Harmonic Distortion The base currents of Q1 and Q2 are shifted in phase by 180°. Therefore, if ib1 = I bm coswt, then ib2 = I bm cos(wt + p ). Hence, from Eqn. (11.13), iC1 = I C + B0 + B1 cos wt + B2 cos 2wt + B3 cos 3wt + B4 cos 4wt
(11.34)
and
iC2 = I C + B0 + B1 cos(wt + p ) + B2 cos 2(wt + p ) + B3 cos 3(wt + p ) + B4 cos 4(wt + p )
or
iC2 = I C + B0 − B1 cos wt + B2 cos 2wt − B3 cos 3wt + B4 cos 4wt
(11.35)
Subtracting Eqn. (11.35) from Eqn. (11.34), iC1 − iC 2 = 2 B1 cos wt + 2 B3 cos 3wt io = k ( iC1 − iC 2 ) = 2 kB1 cos wt + 2 kB3 cos 3wt
D3 =
(11.36) (11.37)
2 kB3 B3 = 2 kB1 B1
All even harmonics are totally eliminated. Hence, the total harmonic distortion is reduced. In majority of the cases, the second harmonic term alone almost accounts for the total distortion. As all even harmonics are eliminated in a push–pull amplifier, the total harmonic distortion is drastically reduced. Hence, it is now possible to adjust RL′ to derive PL′ ( max) with minimum distortion. Thus, it is seen that a classA push–pull amplifier reduces distortion. But still, it is a classA amplifier and hence h is only 50 percent. This is the limitation of the classA push–pull power amplifier. The conversion efficiency can be improved in a classB power amplifier.
Power Amplifiers
11.4
557
CLASSB PUSH–PULL POWER AMPLIFIER
A classB push–pull power amplifier is one in which the transistors are biased at cutoff. This means that the transistors do not draw any current in the quiescent state, and there is dc current in the transistors only when an input signal is present. The circuit of a classB push–pull power amplifier is shown in Figure 11.24. RS
ib1 Vs1
+
VBE1
ic1
Q1
+
N1
−
N2
Vs −
Vs2 Ti
io
R′L
VBE2 − + ib2
RL
VCC R′L
Q2
ic2
N1 To
Figure 11.24 ClassB push–pull power amplifier
From Figure 11.24, it can be seen that VBE1 = VBE2 = 0. Hence, Q1 and Q2 are OFF. When an input signal Vs is present, the signal Vs1 at the base of Q1 could be the same as Vs. However, the signal Vs2 at the base of Q2 is shifted in phase by 180°. When Vs1 is positive Q1 conducts and during this period Q2 is OFF. When Vs2 is positive Q2 conducts and during this period Q1 is OFF. ic1 and ic2 are the collector currents of Q1 and Q2, respectively, when ON. Hence, io = k (ic1 − ic2) as shown in Figure 11.25, the transformer To, being a centertapped one produces two signals shifted in phase by 180°. Although each of the transistors operates under classB condition, there is output for the entire input cycle period.
Vs 0
wt
ic1 0
wt
Vs1 0
wt
ic2 0
wt
Vs2 0
wt
vo 0
wt
Figure 11.25 Waveforms of classB push–pull power amplifier
To calculate the output power of the amplifier, composite characteristics (since two transistors are used and the inputs are shifted in phase by 180°) are drawn and the procedure described earlier is followed as shown in Figure 11.26.
558
Electronic Devices and Circuits
iC1 IB
I(max)
Im
ib
ic IC
0
vCE2
Q
vCE1
0 I(min) iC2
0 0
VC = VCC V (max) V(min) Vm
vce
Figure 11.26 Composite characteristics and the waveforms
If Vc and Ic are the rms values of vce and ic, then P′L, the output power on the primary side of the output transformer is P′L = VcIc. P′L is P′L(max), when V(min) = I(min) = 0.
11.4.1 Calculation of the Conversion Efficiency To calculate h, PBB has to be calculated. To calculate Idc, consider Figure 11.27.
ic1
Q1 N1
+
VCC
Idc N1
To
Q2
ic2
Figure 11.27 Circuit to calculate I dc
Since Q1 and Q2 conduct only for half cycles, the total current drawn from VCC is similar to the output of a fullwave rectifier. We have,
Power Amplifiers
I dc =
2I m 2 2I c = p p
559
(11.38)
If V(min)0, Vm = VCC. Therefore, (11.39)
VCC = 2Vc Using Eqs (11.38) and (11.39), ∴
PBB = VCC I dc = 2Vc ×
2 2 I c 4Vc I c 4 P ′L (max) = = p p p
Hence, h(max) =
PL′ (max) PBB
=
p × 100 = 78.5% 4
(11.40)
Thus, the maximum conversion efficiency of a pure classB push–pull power amplifier is 78.5 percent. This means that if the total dc input power is 100 W, then the available ac power at the output is 78.5 W; whereas in a classA push–pull power amplifier, the available ac output power is only 50 W. This is the major advantage of classB push–pull power amplifier over classA power amplifier.
11.4.2 CrossOver Distortion However, till now the assumption made was that Q1 and Q2 conduct the moment the voltage at the base is ideally 0 V. But in practice, Q1 and Q2 conduct only when a voltage Vg is present to forward bias the base–emitter diode. Till such time, these transistors are OFF. The resultant base current variation is shown in Figure 11.28. For the shaded portion of the input, ib = 0. IB1 ib
VBE2
Vγ
Crossover distortion
0 0
Vγ
VBE1
vbe IB2
Figure 11.28 Crossover distortion in a pure classB power amplifier
560
Electronic Devices and Circuits
As Q1 and Q2 are OFF when the input signal vbe changes from +Vg to −Vg , this type of distortion is called crossover distortion. A push–pull amplifier is chosen because it minimizes distortion. But the amplifier, as can seen from Figure 11.28, is producing an additional unwanted distortion called crossover distortion, which in turn increases the total distortion in the amplifier. Thus, the very purpose of using a push–pull configuration is defeated. Hence, there arises the need to eliminate crossover distortion. If a minimum bias voltage Vg is provided between the base–emitter terminals of each transistor, the moment an input signal is present there is base current in the transistor, thereby eliminating crossover distortion. This is called trickle bias. Imagine a glass full of water. Any extra drop of water poured into it trickles down, hence the name trickle bias. Then, the resultant amplifier is called classAB amplifier for which h is slightly less than 78.5 percent. Though h is reduced marginally, distortion is kept at a smaller value. In the classA push–pull power amplifier as shown in Figure 11.22, if R1 and R2 are adjusted such that VBE = Vg , then the amplifier is a classAB power amplifier.
11.4.3 Dissipation in each Transistor of a ClassB Push–Pull Power Amplifier The dissipation in the transistors is PD = PBB − PL′
(11.41)
and we know that PL′ =
V V V m2 = CC ′ m ′ 2RL 2RL
(11.42)
But PBB =
PL′ VCCVm 4 2VCCVm = × = h 2RL′ p pRL′
(11.43)
Substituting Eqs (11.42) and (11.43) in Eqn. (11.41), PD = PBB − PL′ =
2VCCVm Vm 2 − ′ 2RL pRL′
(11.44)
To get PD(max), differentiate PD with respect to Vm and equate it to zero and get the value of Vm . Substitute this value of Vm in Eqn. (11.44): dPD 2VCC 2Vm = − ′ =0 dVm pRL′ 2RL Therefore, Vm =
2VCC p
(11.45)
Substituting Eqn. (11.45) in Eqn. (11.44), PD = PD(max) =
2 2 2 4VCC 4VCC 2VCC − = p 2 RL′ 2p 2 RL′ p 2 RL′
(11.46)
Power Amplifiers
561
But when V( min ) = 0, Vm = VCC and PL′ = PL′ ( max ) Therefore, from Eqn. (11.42), PL′ (max) =
2 VCC 2RL′
(11.47)
From Eqn. (11.46), PD(max) =
2 2VCC 2 2V 2 4 V2 = × 2 CC′ = 2 × CC′ = 0.4 PL′ (max) 2 ′ p RL 2 p RL p 2RL
(11.48)
From Eqn. (11.48), it can be seen that the maximum dissipation in both the transistors is 0.4 PL′ (max ) . Hence, PD(max) in each transistor PD(max) = 0.2 PL′ (max) =
PL′ (max) 5
(11.49)
Now let it be assumed that the required PL′ (max ) = 10 W. If a classA power amplifier is used then the transistor is required to have PD(max) = 2 PL′ (max ) = 20 W. Whereas in a classB push–pull power amplifier to derive the same output power of 10 W, it is enough if the transistor has PD(max) = 0.2 × 10 = 2 W. That is, transistors with lesser power dissipation capability can be used, which reduces the cost. This is another advantage of the classB push–pull power amplifier.
11.4.4 Determining the Turns Ratio of the Output Transformer, T o 2N1 is the total number of turns on the primary winding of the output transformer, and N2 is the number of turns on secondary. 2N Given RL , to find the turns ratio 1 , the resistance RCC between the two collectors is to be N2 2 2 N1 RCC = found out. Then . RL N 2 With Vmin = 0, Vm = VCC. Therefore, PL′ =
V2 Vm2 = CC′ ′ 2RL 2RL
(11.50)
2 VCC 2 PL′
(11.51)
RL′ =
562
Electronic Devices and Circuits
From Figure 11.29, Collector of Q1
N1 R′L
P′L
N2
RCC P′L
R′L N1
RL
To
Collector of Q2
Figure 11.29 Finding out the turns ratio of the output transformer 2
2N RCC = 1 RL = 4a 2 RL = 4RL′ N2
(11.52)
Since, 2
N RL′ = 1 RL = a 2 RL N2 ′ Thus RL is found from Eqn. (11.51) and RCC is found from Eqn. (11.52). If RCC and RL are 2N known, then the turns ratio 1 can be found out. N2
11.4.5 Determining the Turns Ratio of the Input Transformer, T i Consider the input circuit of the power amplifier (Figure 11.30). Power amplifier being a largesignal amplifier to stabilize the output, usually a small RE is included in the emitter lead, which provides feedback. Ri, the input resistance, is given as follows: Q1 Rs + Vs
N3
RE
RBB
N4 N3
−
RE
Ti
Q2 Ri
Figure 11.30 Determining the turns ratio of the input transformer
Ri = hie + hfe RE
(11.53)
Power Amplifiers
563
Using Eqn. (11.52), RBB = 4Ri
(11.54)
2 N3 RBB = N4 Rs
(11.55)
Therefore,
The turns ratio of the input transformer is decided using Eqn. (11.55). Example 11.5 Design a classAB push–pull power amplifier with tricklebias using silicon NPN transistors having hie = 100 Ω and hfe = 100 (Figure 11.31). The amplifier is required to deliver an output power of 1 W to a load of 3 Ω. The transformers have an efficiency of 75 percent. The internal resistance of the driving source is 1 kΩ.VCE ( max ) = 30 V and PD(max) = 4 W , for each transistor.
Q1 RS
R1
+ Vs
N1
N3 RE
N2
N4 R2
−
RE
N3 Ti
VCC
RL
N1
Q2
Figure 11.31 ClassAB push–pull power amplifier
Solution: Given PL = 1W and hT = 0.75 ∴
PL′ =
1 = 1.33 W 0.75
Usually, VCC ≤
VCE ( max ) 2
≤ 15 V Therefore choose VCC = 12 V
From Eqn. (11.49), PD(max) in each transistor = 0.2 PL′ (max ) =
PL’ (max ) 5
=
1.33 = 0.267 W 5
564
Electronic Devices and Circuits
Since it is given that each transistor has a dissipation capability of 4 W and the possible dissipation in each transistor in trying to get PL = 1W is only 0.267 W, the transistors can be safely used. Selection of TO : RL′ =
2 VCC 12 × 12 = = 54 Ω ′ 2 PL 2 × 1.33
RCC = 4 × 54 = 216 Ω ∴
2 N1 2 216 N = 3 = 72 2
2 N1 − 72 = 8.49 N2
The total number of turns on the primary side of the output transformer is 8.49 times more than the number of turns on the secondary, and the transformer should have a power rating of 1.5 W. Selecting RE , R1, and R2 : Im =
VCC 12 I 0.22 = = 0.22 A and I dc = m = = 0.07 A 54 p p RL′
Each transistor draws I dc = 70 mA RE is not very large. Choose RE = 10 Ω (typically). Then VE, the voltage drop across RE is VE = I dc RE = 0.07 × 10 = 0.7 V For classAB operation VBE = 0.7 V. Therefore, the total voltage between the base and the ground is (VBE + VE ) = 1.4 V. R1 and R2 are adjusted to derive 1.4 V between the base and the ground. 1.4 = 12 ×
R2 R1 + R2
1.4 ( R1 + R2 ) = 12R2
R1 = 7.58R2
Choose R2 = 1000 Ω, then R1 = 7.58 × 1000 = 7580 Ω Selecting Ti: From Eqn. (11.55), Ri = hie + hfe RE = 100 + 100 × 10 = 1100 Ω From Eqn. (11.54) RBB = 4Ri = 4 × 1100 = 4400 Ω Given 2
Rs = 1000 Ω,
2N3 RBB 4400 N = R = 1000 = 4.4 s 4
2N3 = 4.4 = 2.1 N4
The secondary of Ti should have 2.1 times more number of turns on the secondary when compared to the primary.
Power Amplifiers
565
11.4.6 Advantages of ClassB Push–Pull Power Amplifier The following are the advantages of a classB push–pull power amplifier: 1. The efficiency is much higher (78.5 percent), whereas that in a classA power amplifier the efficiency is only 50 percent. 2. Under zerosignal condition, the dissipation in the device is zero. Hence, the battery used can have a longer life. In addition, PD(max ) = 0.2 PL′ (max ) and hence devices with smaller dissipation capability can be used. Whereas in a classA power amplifier, PD(max ) = 2 PL′ (max ) . 3. Since, even harmonics are totally eliminated, distortion is minimized. 4. The centertapped transformer eliminates saturation of the magnetic circuit of the amplifier.
11.4.7 Disadvantages of ClassB Push–Pull Power Amplifier However, classB push–pull power amplifier has the following disadvantages: 1. First, the transformers, in the audiofrequency range, are wound on an iron core, and hence become bulky and occupy more space. Second, the transformer is a lossy circuit element that accounts for a reduced power output. Third, the centertap should be an exactly electrical one. 2. Crossover distortion is present in a pure classB push–pull amplifier.
11.5
CLASSB PUSH–PULL POWER AMPLIFIER THAT ELIMINATES THE TRANSFORMER
The purpose of a centertapped transformer in the push–pull amplifiers is to derive two signals of equal magnitude and of opposite polarity. But the problem with such a circuit arrangement is that the transformer is bulky and is also a lossy circuit element. To overcome these limitations, a transformerless classB push–pull power amplifier is used (Figure 11.32). VCC
RC Q2
CC Q1
+ Vi
CC Q3
+ RL
Vo
CC RE −VEE
Figure 11.32 A transformerless classB push–pull power amplifier
Transistor Q1 acts as a phase splitter. The signal taken from the emitter of Q1 is the same as at the input, because Q1 acts as an emitter follower. If RC = RE, the gain of the inverting amplifier is
566
Electronic Devices and Circuits
1, and the output taken at the collector of Q1 is the same in magnitude but is shifted in phase by 180° with respect to the input. Thus inputs to Q2 and Q3 are signals having the same magnitude but are phase inverted, which precisely was done by a centertapped transformer. During the period when the input goes through the positivegoing half cycle, the input to Q3 is the same, whereas the input to Q2 is inverted. Hence, Q3 is ON and derives a negativegoing signal at the output. During the negativegoing half cycle of the input, the input to Q2 is positive, whereas that for Q3 is negative. Hence, Q3 is OFF and Q2 is ON. As Q2 acts as an emitter follower, the output is a positivegoing signal. Thus, there is output for the entire input cycle period, although each of the transistors operates under class B. −VEE is included to ensure that Q3 operates in the active region.
11.6
COMPLEMENTARY SYMMETRY PUSH–PULL CLASSB POWER AMPLIFIER
The need for a centertapped transformer and a phase splitter can be eliminated in a push–pull amplifier using complementary transistors. NPN and PNP transistors are called complementary devices since the polarities of the voltages and the directions of the currents are exactly opposite in these two types of devices. We also know that an emitter follower has the largest current gain. Hence, using complementary transistors in an emitter follower, it is possible to construct a classB push–pull power amplifier. Consider the emitter follower using an NPN transistor as shown in Figure 11.33. There is output only during the period A VCC and during the period B as the transistor is OFF; the output is zero (shaded region). Now consider the circuit in Figure 11.34, which is A an emitter follower using a PNP transistor. B Here, obviously there can be output only Q1 + during the period B and no output during the Vi period A (shaded region). This means that Q1 A is ON during the positivegoing half cycle and Vo B Q2 is ON during the negativegoing half cycle, which suggests that by combining these two circuits it is possible to get an amplifier cirRE cuit that gives output for the entire input cycle period, in which, one device takes care of onehalf of the input cycle, and the other device Figure 11.33 Emitter follower using an NPN transistor takes care of the other half. Such a classB power amplifier is called complementary symmetry push–pull power amplifier, since NPN and PNP devices are called complementary devices (Figure 11.35). But a pure classB push–pull power amplifier will have crossover distortion. To eliminate it, we provide trickle bias (Figure 11.36). R and R1 are adjusted such that VBE of each transistor is 0.7 V. However, resistance values may change with temperature and can change the output. Power amplifier being a largesignal amplifier, temperature compensation needs to be provided as in Figure 11.37. If the V–I characteristic of the diode is identical to the VBE − IC characteristic of the transistor, temperature changes do not influence the performance of the amplifier. To get a larger current gain, Darlington transistors are used as in Figure 11.38.
Power Amplifiers
567
VCC VCC
A B Q1
Q1
+ Vi
Cc Vo
Cc + Vo
A B Q2
+ Vi
RL
RE
Figure 11.34 Emitter follower using a PNP transistor
Figure 11.35 Complementary symmetry classB push–pull power amplifier VCC
R Q1 R1
Cc
Cc
R1
+ Q2
+ Vi
RL
Vo
R
Figure 11.36 Complementary symmetry classB push–pull power amplifier with trickle bias VCC
Positive halfcycle
R Q1
Input signal
D1
Cc
Cc
D2 Q2
+ Vi
Negative halfcycle
+ RL
Vo
Output signal
R
Figure 11.37 Complementary classB push–pull power amplifier with temperature compensating diodes
568
Electronic Devices and Circuits VCC
R NPN pair
Q1 Q2
D1 D2
Cc
Cc +
+ Vi
D3
PNP pair
D4
RL
Vo
Q4 Q3
R
Figure 11.38 ClassAB pushpull power amplifier with Darlington transistors
Example 11.6 For the circuit in Figure 11.35, RL = 10 Ω, VCC = 30 V. Calculate the maximum ac output power and the minimum power rating of the transistor. Solution: The nosignal voltage is half the supply voltage, VCC/2 and Vm = VCC/2 Therefore, Vm = 30/2 = 15 V and Im = Vm/RL = 15/10 = 1.5 A. PL ( max ) =
Vm I m 15 × 1.5 = = 11.25 W 2 2
PD(max ) = 0.2 × PL (max ) = 0.2 × 11.25 = 2.25 W
11.7
HEAT SINKS
A power amplifier being a largesignal amplifier, heat is generated at the collector junction of the transistor, which in turn can cause an increase in leakage current. The increase in leakage current can further rise the junction temperature, and this may lead to a cumulative effect that may ultimately lead to thermal runaway of the junction. Second, we have seen that the power rating of the transistor reduces at higher temperatures. Hence, there arises the need to quickly remove the heat at the junction for stable operation. Heat sinks are used to accomplish this objective. A heat sink is a mass of metallic conductor mounted on the casing of the transistor. Heat is transferred from the junction to the casing. The heat sink transfers heat from the casing to surroundings and ambient air. Heat sinks effectively reduce the junction temperature and avoid breakdown of the device. The larger the surface area of the heat sink, the easier it is for the heat to escape into the surrounding air. The power dissipation capability is proportional to the difference in temperatures between the junction and the ambient surroundings. PD ∝ (TJ − TA )
569
Power Amplifiers
PD =
(T − T ) j
A
(11.56)
q jA
where TJ = temperature of the junction in °C TA = ambient temperature, °C q JA = thermal resistance of the junction and the surrounding air, °C / W To understand how heat is removed from the junction to the surrounding air, let us consider the thermal circuit (Figure 11.39). Here, TJ, TC, TS, and TA are temperatures of the junction, casing, surroundings, and the ambient air, respectively and q JC ,q CS and qSA are the thermal resistances between the junction and casing, casing and surroundings, and surroundings and ambient air, respectively. From Figure 11.39, it can be seen that
TA
Ambient air qSA
TS
Surroundings qCS
TC
Casing qJC
TJ
Junction
Figure 11.39 Thermal circuit with heat sink
q jA = q jC + q CS + qSA and q CA = q CS + qSA
(11.57)
And using Eqn. (11.56), q jA =
(T − T ) j
A
PD
q jC =
(T − T ) j
C
PD
q CS =
(TC − TS ) PD
qSA =
(TS − TA ) PD
and q CA =
(TC − TA ) PD
(11.58)
Example.11.7 q JA of a power transistor is 175°C / W . (i) Find PD( max ), if TJ = 100°C and TA = 25°C. (ii) If with a heat sink q JA is reduced to 50°C/W, what is PD( max )? Solution: (i) Given q JA = 175°C/W , TJ = 100°C, and TA = 25°C. Using Eqn. (11.56), PD =
(TJ − TA ) (100 − 25 ) q JA
=
175
= 0.43 W
(ii) If q JA = 50°C / W , then PD =
(TJ − TA ) (100 − 25 ) q JA
=
50
=1.5 W
Thus, the power dissipation capability increases with heat sink.
570
11.8
Electronic Devices and Circuits
A CLASSD POWER AMPLIFIER
Even in the best power amplifier seen till now, namely the classB power amplifier, certain amount of power gets wasted in heating the transistors, and hence the efficiency is less than 100 percent. However, if a transistor is used as a switch, then when the transistor is ON or when it is OFF, the amount of dissipation in the device is so negligible that efficiency as high as 100 percent can be achieved. Such an amplifier is called a classD amplifier. Since the transistor is used as a switch, classD amplifier is also called a switching amplifier. This type of amplifier can be used in transmitters.
11.8.1 ClassD Amplifier Using Complementary Transistors A classD amplifier using complementary transistors is shown in Figure 11.40. VCC
Q1
VCC
0
+ Vs −
Vmsinωt
L
C
+
0 Q2 RL
Vo
0
Figure 11.40 ClassD amplifier
Transistors Q1 and Q2 are complementary transistors. An RF transformer couples the input to the two bases. The winding polarities are such that the signals applied to the bases are the same. The inputs are adjusted such that the ON transistor is driven into saturation. During the positive going half cycle of the input signal, Q1 is OFF as it is a PNP transistor and Q2 is ON as it is an NPN transistor. Consequently, VC = 0 (Figure 11.41). During the negativegoing half cycle of the input, Q1 is ON and is in saturation and Q2 is OFF (Figure 11.42). Hence, VC = VCC. During the next positivegoing half cycle of the input signal, Q1 is once again ON and Q2 is OFF. Hence, VC = 0. During the negativegoing half cycle, once again Q2 is ON and Q1 is OFF. VC rises to VCC. This process is repeated, and the result is that VC is a square wave, having amplitude VCC. The spacing between pulses varies with frequency.
VCC
OFF Q1 0 VC = 0 —
0 Q2 ON VCE(sat) = 0
Figure 11.41 Circuit of Figure 11.40 when Q1 is OFF and Q2 is ON
Power Amplifiers
571
VCC
VCC
Q1 VCE(sat) = 0 0 VC = VCC
0
0 Q2 OFF
Figure 11.42 Circuit of Figure 11.40 when Q1 is ON and Q2 is OFF
The output circuit is a high Qseries resonant circuit, which is tuned to the signal frequency so as to recover the original signal transmitted at the output. The larger the value of Q, the better the rejection of the unwanted frequencies.
11.8.2 A ClassD Amplifier Using CenterTapped Transformer and NPN Transistors A classD amplifier using centertapped transformer and NPN transistors Q1 and Q2 as switches is shown in Figure 11.43. The inputs Q1 and Q2 are shifted in phase by 180°. Consequently, the output VC is a square wave referenced to 0 and has an amplitude ±VCC . Such an output, when resolved into its frequency spectrum, contains many frequencies in addition to the fundamental component. The series resonant circuit in the output is tuned to the fundamental frequency to get the desired frequency. From Fourier analysis, the magnitude of the fundamental frequency 4 component in the output is given as V1 = VCC . The ac component of this, therefore, varies as, p VCC
VCC
0 Q1
0 VC −VCC
+ Vs
L
−
C
+
Q2 RL
Vo
0
−VCC
Figure 11.43 ClassD amplifier using NPN transistors and centertapped transformer
572
Electronic Devices and Circuits
4 VCC sinwt . As a series resonant circuit is used at the output, at resonance, the p effective impedance is resistive and is equal to RL, if the transistor switch is considered to be ideal, V that is, its saturation resistance, RCS = 0. Hence, the fundamental component of current I1 is I1 = 1 . R L 4V Hence, i1 varies as I1sinwt, where I1 = CC . The average current in the output is Iave and is the pRL average over one cycle. Let wt = q
v1 = V1sinwt =
I ave =
4VCC 1 pRL 2p
∫
p
0
4V 4V 1 p 4V 1 sinq dq = CC ( − cosq )0 = CC (1 + 1) = 2 CC pRL 2p p RL pRL 2p
(11.59)
This is the dc component when one device is ON. Therefore, I dc due to the two devices is I dc = 2 I ave =
8VCC p 2 RL
(11.60)
Therefore, the total dc input power PBB is 8V PBB = VCC I dc = 2 CC p RL
2 8VCC VCC = 2 p RL
(11.61)
The output power due to the fundamental component P1 is 2
2 4VCC 8V 2 I P1 = 1 RL = RL = 2 CC 2 p RL 2pRL
(11.62)
The conversion efficiency, h=
P1 × 100% PBB
Therefore, 2 8VCC p 2 RL × 100% = 100% h= 2 8VCC p 2 RL
Thus, the conversion efficiency of a classD amplifier, ideally, can be as high as 100 percent. But in practice, the transistor switch, when ON has a saturation resistance of RCS. Hence, the output circuit, when Q1 is ON, is drawn as in Figure 11.44. RL VC reduces by a factor RL + RCS
.
Power Amplifiers
573
Hence
h=
P1 RL × 100 = × 100% PBB RL + RCS
(11.63)
If RL = 100 Ω and RCS = 10 Ω , then
h=
100 × 100 = 90.91% 100 + 10
A More General ClassD Amplifier The output of a squarewave generator is connected VCC as input to an integrator, which converts the square wave into a triangular wave. The input signal and the triangular wave are the inputs Q1 ON to a comparator. A comparator is one that RCS VC gives a high output when the both the inputs are the same (Figure 11.45). The output of the + comparator consists of a train of pulses whose average value is directly proportional to the Q2 OFF RL instantaneous value of the signal at that time. To be able to reconstruct the signal, the frequency of the pulses is required to be reasonably larger than the highest frequency of interest in the input −VCC signal. The width of the pulses is a function of Figure 11.44 VC reduces when RCS is taken into the amplitude and frequency of the signal being consideration amplified (pulse width modulation or PWM), and hence these amplifiers are also called PWM amplifiers. The output contains, in addition to the required signal, unwanted harmonics that must be removed by a lowpass LC filter. In practice, the triangular wave has a much larger frequency than shown in Figures 11.46 and 11.47. Signal input
+ Comparator
Triangle
PWM output
Low pass ﬁlter
−
Integrator
Output
Square wave generator
Figure 11.45 ClassD amplifier
As the output of a classD amplifier is insensitive to the changes in the amplitude of the signal, it cannot be used to amplify an AM signal. It can only be used to amplify an FM signal or any constant amplitude sinusoidal signal.
574
Electronic Devices and Circuits
+VP +Vm 0 −Vm −VP V PWM 0
Figure 11.46 Waveforms of classD power amplifier
+Vm Input Triangle 0
−Vm V PWM 0
Figure 11.47 Waveforms of the classD amplifier when the frequency of the triangular wave is much larger than the input signal
11.9
CLASSS AMPLIFIER
A classS amplifier is a switching amplifier (Figure 11.48). VCC
Q
VE −
T
VBE +
VCC
L
+ C RL
Vo −
0
Vi T1
Figure 11.48 ClassS amplifier
575
Power Amplifiers
T1 is called the duty cycle, D. When T − VBE ). The LCfilter eliminates ripple and delivers dc to the
This type of amplifier is used in switching regulators. The ratio Vi = VCC , VE = VCC −VBE. Vo = D(VCC
load. In a switching regulator, if the output voltage increases, for any reason, D decreases. The output is restored back to its original value. If, alternatively, Vo decreases, D increases and the output voltage is once again brought back to the required value. VCC
Additional Solved Examples
18 V
Example 11.8 A sinusoidal signal is applied to a series fed classA power amplifier shown in Figure 11.49. The base current of the transistor varies as ib = 0.005 sinwt . Calculate (i) the coordinates of the Qpoint, (ii) PBB, (iii) PL, and (iv) h. Silicon transistor with hFE = 50 and VBE = 0.6 V is used.
IC
RL
RB 4
32 IB
Cc
+ Cc
VCE
+ VBE
+
Solution:
−
+ Vo
−
Vs
−
V − VBE 18 − 0.6 (i) I B = CC = = 4.35 mA RB 4
−
Figure 11.49 ClassA seriesfed power amplifier
I C = hFE I B = 50 × 4.35 = 217.5 mA = 0.2175 A VCE = VCC − I C RL = 18 − 0.2175 × 32 = 11.04 V (ii) PBB = VCC I C = 18 × 0.2175 = 3.915 W (iii) I bm = 0.005 A . The rms value of the base current, I b =
0.005 = 0.0035 A 2
The rms value of the collector current, I c = hfe I b = 50 × 0.0035 = 0.175A 2
The ac output power, PL = I c2 RL = ( 0.175 ) × 32 = 0.98 W (iv) h =
PL 0.98 × 100 = × 100 = 25.03% PBB 3.915
Example 11.9 A classA seriesfed power amplifier has h = 20 percent. The amplifier delivers an output power of 1 W. Calculate (i) PBB, (ii) PD in the transistor, and (iii) the minimum power dissipation capability needed for the transistor.
576
Electronic Devices and Circuits
Solution: (i) h =
PL PBB
PBB =
PL 1 = = 5W h 0.2
(ii) PD = PBB − PL = 5 − 1 = 4 W (iii) The power dissipation is maximum when PL = 0 Power dissipation capability needed for the transistor = PBB − 0 = 5 − 0 = 5 W Example 11.10 A load of 15 Ω is connected to a singleended transformercoupled classA power amplifier shown in Figure 11.50. I C drawn by the transistor under nosignal condition is 250 mA. N 4 The transformer has = 1 = . VCC = 9 V. PL = 1 W. The efficiency of the transformer, hT = 75%. N2 1 Calculate (i) PL′ , (ii) rms values of the load voltage and the primary voltage, (iii) rms values of the load current and the primary current, (iv) PBB, (v) h, and (vi) PD. VCC N1 N2 + Vp R′L − Ip
Is + Vs −
RL
IC + RB Vi RE
VBB
CE
−
Figure 11.50 Singleended transformercoupled classA power amplifier
Solution: (i) PL′ =
PL 1 = = 1.33 W hT 0.75 2
N (ii) R = a RL = 1 RL = 42 × 15 = 240 Ω N ′ L
2
2
′ L
P =
Vp2(rms)
Vp(rms) Vs (rms)
RL′
=
Vp2(rms) = PL′ RL′ = 1.33 × 240 = 319.2
N1 =4 N2
Vs (rms) =
Vp(rms) 4
=
17.87 = 4.47 V 4
Vp(rms) = 17.87 V
Power Amplifiers
577
(iii) Power delivered to the load, PL = 1W 1 = I s2( rms ) RL I s(rms ) I p(rms )
=
I s2( rms ) =
N1 =4 N2
1 = 0.067 15 I p(rms ) =
I s ( rms ) = 0.26 A
I s(rms ) 4
=
0.26 = 0.065 A 4
(iv) PBB = VCC I C = 9 × 0.25 = 2.25 W (v) h =
PL 1 = × 100 = 44.44% PBB 2.25
(vi) PD = PBB − PL′ = 2.25 − 1.33 = 0.92 W Example 11.11 In a singleended transformercoupled power amplifier operated under classA condition, the operating point is adjusted for symmetrical swing. The amplifier is required to deliver a maximum power of 5 W to a load of 10 Ω. VCC = 20 V and assume V(min) = 0. Find (i) α, (ii) the peak collector current Im, (iii) coordinates of the Qpoint, and (iv) h. The transformer is ideal. Solution: (i) PL′ (max ) = 5 W PL′ (max ) = RL′ =
Vm 2 and with V(min) = 0, Vm = VCC = 20 V 2RL′ Vm 2 20 × 20 = = 40 Ω ′ 2×5 2 PL (max)
RL′ = a 2 RL ∴
∴
a2 =
RL′ 40 = =4 RL 10
a=2 (ii) PL′ (max ) =
I m2 RL′ 2
I m2 =
2 PL′ (max) 2 × 5 = = 0.25 40 RL′
(iii) With Vmin = 0, Vm = VCC = 20 V and IC = Im = 0.5 A (iv) PBB = VCC I C = 20 × 0.5 = 10 W
h=
PL 5 × 100 = × 100 = 50% PBB 10
I m = 0.5 A
578
Electronic Devices and Circuits
Example 11.12 A singleended transformercoupled classA power amplifier is driving a 10 Ω load. The quiescent base current is adjusted to be 5 mA. The input signal is adjusted to have a base current swing of 4 mA. The following values are noted from the characteristics: VCE ( max ) = 18.5, VCE ( min ) = 1.5 V, I C ( max ) = 250 mA, and I C ( min ) = 5 mA. N1 4 = . V = 15 V. Determine (i) the rms value of the load current and N 2 1 CC voltage, (ii) ac power delivered to the load, (iii) total dc input power, (iv) power dissipation in the transistor, and (v) efficiency of the amplifier. The transformer has =
Solution: (i) The rms value of the voltage on the primary, Vc =
VCE( max ) − VCE( min) 2 2
=
18.5 − 1.5 = 6.01V 2 2
The rms value of the voltage on the secondary (load), Vs =
Vc 6.01 = = 1.5 V a 4
Il =
Vs 1.5 = = 0.15 A RL 10
The rms value of the load current,
(ii) I c =
I C( max ) − I C( min) 2 2
=
250 − 5 = 86.63 mA 2 2 PL′ = Vc I c = 6.01 × 86.63 = 0.521W
(iii) The quiescent collector current I C =
I C ( max ) + I C ( min ) 2
=
250 + 5 = 127.5 mA 2
PBB = VCC I C = 15 × 127.5 = 1.91 W (iv) Power dissipation in the transistor, PD = PBB − PL′ = 1.91 − 0.521 = 1.39 W
(v) h =
PL′ 0.521 = × 100 = 27.28% 1.91 PBB
Example 11.13 Design a singleended transformercoupled classA power amplifier to deliver a power of 60 mW to a load of 3 Ω. Choose 2N109 transistor and a supply voltage of 10V. The transformer has an efficiency of 80 percent. Note: 2N109 is a Ge PNP transister with PD(max)= 165mw at 25°C.
579
Power Amplifiers
Solution: 2N109 is a Ge PNP transistor with PD(max) = 165 mW at 25°C. PL′ =
PL 60 = = 75 mW hT 0.8
PD in the transistor = 2PL′ = 2 × 75 = 150 mW PD is less than PD(max). Hence, the transistor can be safely used. PL′ =
VCC 2 2RL ′
RL′ =
RL′ = a 2 RL
a2 =
VCC 2 10 × 10 = = 666.66 Ω 2 × 75 2 PL′
RL ′ 666.66 = = 222.22 3 RL
a = 14.90
The transformer is required to have a power rating of 150 mW. Choice of RE, R1, and R2: VCC I C = 2 PL′
VC = VCC = 10 V
IC =
2 PL′ 150 = = 15 mA VCC 10
Choose RE = 47 Ω. RE is meant for stability for the operating point. Therefore, VR, the voltage drop across RE is VR = I C RE = 15 × 47 = 0.71 V For Q to be in the active region, the voltage drop across R2 must be more than 0.7 V by 0.3 V. The voltage drop across R2 = VCC
R2 R1 + R2
1 = 10
R2 R1 + R2
R1 + R2 = 10R2 VCC −10 V
9R2 = R1 Choose R2 = 2.2 kΩ
R1
22
R2
2.2
N1 15
Then
N2 1
RL
R1 = 9R2 = 9 × 2.2 = 20.8 kΩ Choose R1 = 22 kΩ The designed circuit is shown in Figure 11.51. Example 11.14 A classB power amplifier uses a single transistor and delivers power to a load of 2 kΩ (Figure 11.52). A moving coil meter connected in series with the load measures a dc current of 20 mA. Calculate the ac output power.
RE
CE
47
Figure 11.51 Singleended transformercoupled classA power amplifier
580
Electronic Devices and Circuits
Solution: The amplifier in Figure 11.52 is a pure classB amplifier. The collector current flows in half cycles. The dc component of collector current is I dc
15 V RL
2 + ic 0
MC ammeter Idc
I = m p
−
or +
I m = pI dc
Idc
+ Vo
Vs 0 −
I rms
pI I = m = dc 2 2
−
Figure 11.52 Singletransistor classB power amplifier
2
p2 10 2 pI PL = ( I rms ) RL = dc RL = × I dc 2 × RL = × 20 × 10 −3 2 4 4
(
)
2
× 2 × 103 = 2 W
Example 11.15 An idealized classB push–pull power amplifier, shown in Figure 11.53, has VCC = 20 V, N 2 = 2 N1 and the load to the amplifier is a loud speaker with an impedance of 16 Ω. The sinusoidal input swing is adjusted such that Vm = VCC. Determine (i) PL′, (ii) PBB, (iii) h , and (iv) dissipation in each transistor. ic1
Q1
+
N1 R′L
Vs1 N2
0
RL
VCC
Vs2 −
Q2
R′L
ic2
N1
Figure 11.53 Idealized classB push–pull power amplifier
Solution: 2
N RL’ = 1 RL N2
(i) Vm = VCC But,
N 2 = 2 N1 2
∴
N RL′ = 1 RL = 0.25 RL 2 N1 RL′ = 0.25 × 16 = 4 Ω
Power Amplifiers
Im =
Vm VCC 20 = ′ = = 5A 4 RL′ RL
PL′ =
Vm I m 20 × 5 = = 50 W 2 2
(ii) I dc =
581
2I m 2 × 5 = = 3.19 A p p
PBB = VCC I dc = 20 × 3.19 = 63.8 W (iii) h =
PL′ 50 × 100 = × 100 = 78.36% PBB 63.8
(iv) PD in each transistor =
PBB − PL′ 63.8 − 50 = = 6.9 W 2 2
Example 11.16 Design the singleended transformercoupled classA power amplifier shown in Figure 11.54 to deliver a power of 150 mW of audio power into a load of 3 Ω. The quiescent base current is adjusted so that Vm = VCC. The supply voltage VCC = 18 V. The collector dissipation should not exceed 250 mW. VCC
N1
R1
RL
+
VB Vs
N2
+ VBE
VCE −
R2 RE
CE
Figure 11.54 Transformercoupled amplifier
Solution: RE is included to provide bias stability. Let VE, the voltage drop across RE be 1 V. Therefore, VCE = VCC − 1 = 18 − 1 = 17 V
582
Electronic Devices and Circuits
PD = 250 mW
∴
IC =
PD = VCE I C
PD 250 × 10 −3 = = 14.70 mA 17 VCE
VE = I C RE = 1V ∴
RE =
1 = 68 Ω 14.7 × 10 −3
The bypass condenser CE is chosen such that X CE =
RE = 6.8 Ω 10
1 = 6.8 Ω 2pfCE At f = 50 Hz, CE =
1 = 468.3 mF 2p × 50 × 6.8
Let VBE be 0.7 V. Then VB = VE + 0.7 = 1 + 0.7 = 1.7 V VB = VCC
∴
R2 + R1 VCC = R2 VB
1+
R2 R2 + R1
R1 18 = = 10.59 R2 1.7
R1 = 9.59 R2
R1 = 9.59R2
Choose R2 = 1000Ω R1 = 9.59 R2 = 9.59 × 1000 = 9.59k Ω
PL′ = 150 mW 2
N RL′ = 1 RL N2
PL′ =
VCC 2 2RL′
RL′ =
VCC 2 18 × 18 = 1080 Ω = 2 PL′ 2 × 150 × 10 −3
2
N1 RL′ 1080 N = R = 3 = 360 2 L
N1 = 18.97 N2
Power Amplifiers
583
Example 11.17 A classA seriesfed power amplifier delivers power to a resistive load. The quiescent collector current is 8 mA. The maximum and the minimum collector to emitter voltages are 20 V and 2 V, and the corresponding values of collector currents are 20 mA and 2 mA, when an ac signal is applied to it. Determine: (i) the rms value of the collector voltage and collector current, (ii) ac power output, (iii) power rating of the transistor, and (iv) the second harmonic distortion. Solution: (i) Vc =
Ic =
VCE(max ) − VCE(min) 2 2 I C(max ) − I C(min) 2 2
=
=
20 − 2 2 2
20 − 2 2 2
= 6.36 V
= 6.36 mA
(ii) PL = Vc I c = 6.36 × 6.36 = 40.45 mW (iii) Power rating of the transistor = 2 × PL = 2 × 40.45 = 80.9 mW
(iv) B1 = B2 =
D2 =
I C ( max ) − I C ( min ) 2
=
20 − 2 = 9 mA 2
I C (max ) + I C (min) − 2 I C 4
=
20 + 2 − 2 × 8 = 1.5 mA 4
B2 1.5 × 100 = × 100 = 16.67% 9 B1
Example 11.18 A signal, varying as 2 cos ( 314t ) , is applied to a classA singleended transformercoupled power amplifier. The alternating component of collector current is given as follows: ic = 18 cos ( 3140t ) + 1.8 cos ( 2 × 3140t ) + 1.5 cos ( 3 × 3140t ) + 0.6 cos ( 4 × 3140t ) + 0.3 cos ( 5 × 3140t ) (a) Calculate (i) the frequency of the fundamental component of the input, (ii) Dn, n = 2, 3, 4, 5, and (iii) the percent increase in the output power due to distortion. (b) Repeat for a classA push–pull power amplifier. Solution: (a) The alternating component of collector current is expressed as follows: ic = B1 cos (wt ) + B2 cos ( 2wt ) + B3 cos ( 3wt ) + B4 cos ( 4wt ) + B5 cos ( 5wt )
584
Electronic Devices and Circuits
(i) We have, w = 2pf1 = 3140 Therefore, f1 = 500 Hz
(ii) D2 =
B2 1.8 = = 0.1 18 B1
( D2 )
D3 =
B3 1.5 = = 0.083 B1 18
( D3 )
D4 =
B4 0.6 = = 0.033 18 B1
( D4 )
D5 =
B5 0.3 = = 0.0167 B1 18
( D5 )
2
2
2
2
2
2
= 0.01
= 0.0069
= 0.0011
= 0.0003
2
2
(
)
D 2 = ( D2 ) + ( D3 ) + ( D4 ) + ( D5 ) = 0.01 + 0.0069 + 0.0011 + 0.0003 = 0.0183
(iii) Total output power, PL = P1 1 + D 2 = P1 (1 + 0.0183 ) = 1.0183P1
When the distortion is zero, PL = P1
Therefore, increase in output power due to distortion =
1.0183P1 − P1 × 100 = 1.83% P1
(b) In a push pull–power amplifier, even harmonics are eliminated. Hence, 2
2
D 2 = ( D3 ) + ( D5 ) = 0.0069 + 0.0003 = 0.0072
(
)
Total output power, PL = P1 1 + D 2 = P1 (1 + 0.0072 ) = 1.0072 P1
Therefore, increase in output power due to distortion =
1.0072 P1 − P1 × 100 = 0.72% P1
Thus, it is seen that harmonic distortion is reduced in a push–pull power amplifier.
Power Amplifiers
585
Example 11.19 A classB push–pull power amplifier is to dissipate 6 W in load of 8 Ω. Specify the output transformer and the transistors. Assume the efficiency of the transformers hT as 75 percent. VCC = 24V Solution: The output circuit of the power amplifier is shown in Figure 11.55. Q1 24 V
N1
R′L
N1
R′L
Q2
RL ∞
N2 VCC
Figure 11.55 Output circuit of the power amplifier
PL = 6 W
PL′ =
PL 6 = = 8W hT 0.75 RL′ =
Vm = VCC
PL′ =
2 VCC Vm2 = 2RL′ 2RL′
2 VCC 242 = = 36 Ω 2 PL′ 2 × 8
The resistance between the two collectors, RCC = 4 × 36 = 144 Ω 2
2 N1 2 N1 144 = = 18, = 4.24 and the transformer The turns ratio of the output transistor = N 8 N2 2 should have a power rating of more than 8 W. The voltage swing is symmetric with respect to VCC. Therefore, VCE ( max ) = 2VCC = 2 × 24 = 48 V Vm I m VCC I m = 2 2 2 PL′ 2×8 Im = = = 0.67 A VCC 24 PL′ = ∴
I dc =
2 I m 2 × 0.67 = = 0.427 A p p
PBB = VCC I dc = 24 × 0.427 = 10.25 W PD(each) =
PBB − PL′ 10.25 − 8 = = 1.125 W 2 2
The transistor is chosen such that PD ≥ 1.25 W, VCE(max) = 50 V and I C = 500 mA
586
Electronic Devices and Circuits
Example 11.20 Design the classB push–pull power amplifier with trickle bias shown in Figure 11.56, to deliver 600 mW to a load of 4 Ω. The silicon transistor used has a dissipation capability of 250 mW at 25°C and VCE(max) = 50 V. The output transformer has hT = 75 percent. Determine, VCC, RCC, the turns ratio and the values of the biasing resistors, R1 and R2. Assume RE = 10 Ω. Q1 R1 N1
N3 RE
N2 R2
RE
N3
VCC
RL
N1
Q2
Figure 11.56 ClassB power amplifier with trickle bias
Solution: Given PL = 600 mW, VCE(max) = 50, hT = 75% and RE = 10 Ω PL′ =
PL 600 = = 800 mW ηT 0.75
The output swing is symmetric with respect to VCC. Hence, VCC ≤
VCE(max) 2
=
50 = 25 V 2
Choose VCC = 20 V With Vmin ≈ 0, Vm = VCC
PL′ =
2 VCC 2RL′
RL′ =
2 VCC 202 = = 250 Ω ′ 2 PL 2 × 800
RCC = 4 × 250 = 1000 Ω Therefore, the output transformer should have 2 N1 2 RCC 1000 250 N = R = 4 = 1 2 L
2 N1 = 15.81 N2
The transformer should have the power rating of at least 1 W.
Power Amplifiers
I m=
VCC 20 = = 80 mA RL’ 250
I dc =
2 I m 2 × 80 = 50.96 mA = p p
IC =
587
I dc = 25.48 mA 2
The dc voltage drop VE across RE is VE ≈ I C RE = 25.48 × 10 −3 × 10 = 0.26 V For the transistor to be in the active region, VBE = 0.6 V. Therefore, the voltage drop, V2, across R2 is required to be 0.6 V more than 0.26 V. V2 = 0.26 + 0.6 = 0.86 V V2 = VCC
1+
R1 VCC = R2 V2
For bias stability, RB ≥ 10RE
R2 R1 + R2
R1 VCC 20 = − 1= − 1 = 22.26 R2 V2 0.86
RB =
R1 = 22.26R2
R1R2 22.26R2 R2 22.26R2 = = R1 + R2 22.26R2 + R2 23.26
If RB = 10RE = 10 × 10 = 100 Ω, 22.26R2 = 100 23.26
R2 = 104 Ω
R1 = 22.26R2 = 22.26×104 = 2315 Ω PBB = VCCIdc = 20 × 50.96 × 10−3 = 1.02 W PD(each) =
PBB − PL′ 1.02 − 0.8 = = 0.11 W 2 2
Example 11.21 A silicon transistor operates with a heat sink. qSA = 1.5°C/W. The transistor, rated at 100 W, has qJC = 0.5°C/W and θCS = 0.5°C/W. What is the maximum power dissipated if TA = 50°C and TJ = 150°C? Solution: q JA = q JC + q CS + q SA = 0.5 + 0.5 + 1.5 = 2.5 oC/W PD =
TJ − TA 150 − 50 = = 40 W q JA 2.5
588
Electronic Devices and Circuits
Summary • A classA power amplifier is a largesignal amplifier in which the transistor is biased in the active region. There is an output for the entire input cycle period. • In a classB power amplifier, there is output for exactly onehalf of the input cycle period. The output is in the form of half cycles as the transistor is biased at cutoff. • ClassA and classB amplifiers are used in the audiofrequency range. • A classC power amplifier is one in which the transistors are biased below cutoff. Consequently the output is in the form of pulses. To get back the original signal, filters or tuned circuits are used. ClassC amplifiers are either used as tuned amplifiers or harmonic generators in the radiofrequency range. • ClassA seriesfed power amplifier has a conversion efficiency of 25 percent. The dissipation in the transistor is maximum under quiescent condition PD(max) = 2PL. Harmonic distortion is present in this amplifier. • A classA singleended transformercoupled power amplifier has a conversion efficiency of 50 percent. But additional distortion can be present in the output of the amplifier due to saturation of the magnetic circuit of the amplifier in addition to harmonic distortion. In addition, it still has the associated disadvantages of a seriesfed power amplifier. • A classA push–pull power amplifier eliminates even harmonic distortion and distortion that could be present due to saturation of the magnetic circuit, since equal and opposite dc currents flow in the two halves of the primary winding of the centertapped output transformer. • A classB power amplifier has a conversion efficiency of 78.5 percent. But an additional distortion called crossover distortion could be present in a pure classB push–pull power amplifier. To eliminate crossover distortion, trickle bias is provided. • In a classB push–pull power amplifier the maximum dissipation in each transistor PD(max) = 0.2P´L(max). • A complementary push–pull power amplifier is used to eliminate the centertapped transformer. • Heat sinks are used to improve the power dissipation capability of the transistors at elevated temperatures. • A classD amplifier is one in which the transistors are used as switches so that the dissipation in the devices is so small that efficiencies near 100 percent can be achieved.
Multiple Choice Questions 1. The conversion efficiency of a seriesfed classA power amplifier is (a) 100% (b) 75% (c) 25% (d) 50% 2. For a classA seriesfed power amplifier, the total dc input power is 100 W. Then, the ac output power is (a) 78.5 W (b) 50 W (c) 25 W (d) 100 W 3. If 1 W is the maximum ac power output of a classA power amplifier, then the amount of possible dissipation in the transistor is (a) 0.5 W (b) 0.2 W (c) 0.75 W (d) 2 W
Power Amplifiers
589
4. During graphical analysis, it is found that B1 = 0.2 mA and B0 = 0.01 mA, then the percent second harmonic distortion is (a) 10% (c) 5%
(b) 20% (d) 50%
5. The conversion efficiency of a singleended transformercoupled classA power amplifier is (a) 25% (b) 50% (c) 78.5% (d) 100% 6. In singleended transformer coupled classA power amplifier, if the total dc input power is 1 W, then the available ac output power and the dissipation in the transistor are, respectively, (a) 0.5 W and 2 W (b) 0.25 W and 1 W (c) 0.5 W and 1 W (d) 0.785 W and 2 W 7. If PD(max) for a transistor at 25°C is 1 W and the derating factor D = 20 mW/°C, then PD(max) at 50°C is (a) 0.375 mW (b) 500 mW (c) 785 mW (d) 1 W 8. In a singleended transformercoupled power amplifier, distortion is present in the output due to saturation of the magnetic circuit mainly because (a) a large dc current flows through the primary winding of the transformer (b) there is no impedance matching (c) ac load to the amplifier is large (d) the load is open circuited 9. The two major advantages of a push–pull power amplifier are (a) even harmonics are eliminated and saturation of the magnetic circuit is prevented (b) efficiency is 100 percent and even harmonics are eliminated (c) dissipation in the transistor under nosignal condition is zero and even harmonics are eliminated (d) dissipation in the transistor under nosignal condition is zero and saturation of the magnetic circuit is prevented 10. In a pure classB push–pull power amplifier, the total dc input power is 100 W. Then, the ac output power and the possible dissipation in each transistor are, respectively, (a) 78.5 W and 15.7 W (b) 50 W and 50 W (c) 50 W and 100 W (d) 100 W and 100 W 11. The major disadvantage of a pure classB push–pull power amplifier is that it introduces (a) even harmonic distortion (b) crossover distortion (c) ripple (d) feedback 12. Crossover distortion can be eliminated with only a negligible loss in efficiency by (a) providing trickle bias (b) providing midpoint bias (c) biasing at cutoff (d) biasing below cutoff 13. In a singleended transformercoupled classA power amplifier if the power output due to the fundamental component is 500 mW and the total percent distortion is 10 percent, then the total output power is (a) 505 mW (b) 510 mW (c) 575 mW (d) 1000 mW
590
Electronic Devices and Circuits
14. In a complementary symmetry push–pull power amplifier phase inversion is provided by (a) centertapped transformer (b) NPN and PNP transistors (c) CE amplifier (d) CE–CB pair 15. If qJA of a power transistor is 100°C/W and if TJ = 75°C and TA = 25°C, then PD(max) is (a) 1 W (b) 0.5 W (c) 0.25 W (d) 0.75 W
Short Answer Questions 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.
What are the main differences between a voltage amplifier and a power amplifier? A voltage amplifier is used as a preamplifier to a power amplifier. Why? What is a classA power amplifier? How is the transistor biased? What are the main limitations of the classA seriesfed power amplifier? What is the main improvement in a classA singleended transformer power amplifier when compared to a seriesfed power amplifier? What is its main limitation? What are the advantages of classB operation? What are the two major limitations of the classB operation? What can be listed as the drawback of the classB operation? What is a classD amplifier? What are the advantages of complementary symmetry push–pull configuration over the conventional push–pull configuration?
Long Answer Questions 1. Explain the graphical procedure to calculate PL, h, and PD(max) for a seriesfed classA power amplifier. 2. Explain the graphical procedure to calculate P′L (max) and h for a singleended transformer coupled classA power amplifier. 3. Draw the circuit of a classA push–pull power amplifier and show that this amplifier eliminates some of the disadvantages associated with a singleended transformer coupled classA power amplifier. 4. Draw the circuit of a classB push–pull power amplifier and explain its working. Obtain the expression for its conversion efficiency. What are its advantages and disadvantages? 5. Draw the circuit of a complementary symmetry push–pull power amplifier with trickle bias and temperature compensation and explain its working. What is its advantage over a conventional push–pull power amplifier? 6. Write short notes on (i) crossover distortion, (ii) classD power amplifier, and (iii) classS power amplifier.
Unsolved Problems 1. A sinusoidal signal vs = 1.76 sin (600t ) is fed to a singleended transformercoupled power amplifier. The resulting output current is ic = 15 sin(600t) + 1.5 sin(1200t) + 1.2sin (1800t ) + 0.5 sin (2400t ) (i) Determine the percent increase in the output power due to distortion. (ii) Repeat for a classA push–pull power amplifier. 2. Two transistors operate in a class B push–pull circuit with VCC = 15 V. The turns ratio of the output transformer is 3:1 and RL = 9 Ω. Determine the ac output power and the dc input power. Also find h. 3. A singleended transformercoupled classA power amplifier operates with a supply voltage of 10 V and load of 10 Ω. If PD (max ) = 1 W, calculate (i) PL′ (max ) , (ii) the quiescent collector current, and (iii) the turns ratio of the transformer.
Power Amplifiers
591
4. Determine the efficiency of the transformer coupled class A power amplifier with a supply voltage of 10 V for (i) the peak voltage swing in the output of 10 V and (ii) the peak voltage swing in the output of 5 V. 5. For the circuit shown in Figure 11.36, VCC = 20 V and RL = 3 Ω. If an input voltage of 10 V(rms) is applied, determine (i) the total dc input power, (ii) the ac output power, (iii) the dissipation in each transistor, and (iv) the efficiency. 6. q JA of a power transistor is 150°C/W. Find (i) PD (max ), if TJ = 150°C and TA = 25°C. (ii) If with a heat sink q JA is reduced to 50°C/W, what is PD (max )?
12
HIGHFREQUENCY TRANSISTOR AND FET AMPLIFIERS
Learning objectives After going through this chapter, the reader will be able to Appreciate the influence of Miller capacitor on the performance of the transistor at high frequencies Draw the highfrequency model (hybrid p model) of the transistor Define the highfrequency parameters of the transistor in terms of the lowfrequency parameters Calculate the shortcircuit current gain of a CE transistor amplifier Calculate hybrid p capacitances Analyze CS and CD amplifiers at high frequencies
12.1
INTRODUCTION
Chapters 6 and 7 of this book dealt with the analysis of the smallsignal amplifiers confining to the lowfrequency model. In these two chapters, we have used the lowfrequency model of the transistor and FET, and neglected the influence of stray capacitances and the interelectrode capacitances. It has been assumed that stray capacitances and the interelectrode capacitances behave as open circuits at low frequencies. However, when the operation of a transistor is considered at high frequencies, the reactance of these capacitors may not be so large as to be replaced by open circuits. Therefore, we have to consider the influence of these capacitors at radiofrequencies. In order to calculate the gain of the amplifier at high frequencies, a totally different equivalent circuit of the transistor needs to be considered. This equivalent circuit is known as the hybrid p model of the bipolar junction transistor. In the analysis of an RCcoupled amplifier earlier, we have considered the influence of the coupling condenser Cc and the shunt condenser Cs on the performance of the amplifier. At high frequencies, Cc continues to behave as a short circuit. It has to be noted that the reactance of Cs decreases with increase in frequency. Further, the stray capacitance between the input and the output terminals appears as Miller capacitances in shunt with the input and output terminals. Miller capacitance needs to be considered at high frequencies. Miller theorem and Miller effect were presented and made use of in an earlier chapter of this book. It is presented once again here for the sake of continuity and for the convenience of the reader.
HighFrequency Transistor and FET Amplifiers
593
12.2 THE MILLER CAPACITANCES Consider the amplifier circuits in Figure 12.1. If an impedance Z ′ is connected between the input and output nodes in an amplifier, it can be replaced by two impedances Z1 and Z2 connected in Z′ Z′ shunt with the input and the output terminals, where Z1 = and Z2 = . A is the volt1− A 1 − (1 A) age gain of the amplifier. Z′
Z1
C′
+
Ampliﬁer with gain A
Z2
Vi −
Ampliﬁer with gain A
+ Vo −
Figure 12.1 Use of Miller’s theorem to calculate Miller capacitance
If C ′ is in the feedback path, Z1 =
1 wC ′ 1 1 = = 1 − A wC ′ (1 − A) wCMi
where CMi = C ′ (1 − A)
(12.1)
CMi is the Miller capacitance on the input side. Similarly, Z2 =
1 wC ′ 1 1 = = 1 − (1 A) wC ′ (1 − (1 A)) wCMo
where CMo = C ′ (1 − (1 A)) ≈ C ′
(12.2)
CMo is the Miller capacitance on the output side and CMo ≈ C ′ since A is large. Thus, it can be noted that a capacitance C ′ that appears between the input and the output is replaced by two capacitances CMi and CMo. These capacitances CMi and CMo appear in shunt with the input and output terminals.
594
12.3
Electronic Devices and Circuits
CE AMPLIFIER: INFLUENCE OF NETWORK PARAMETERS AT HIGH FREQUENCIES
Consider the CE amplifier at high frequencies (Figure 12.2). In the ac circuit of Figure 12.2, CE and Cc are considered as short circuits due to their high values. The reactance offered by these capacitors is almost zero. The resultant ac circuit is shown in Figure 12.3 VCC RC Cbc
R1
Cc Cce
Cc Rs
RL
Cbe Cwo
R2
+
Cwi CE
RE
Vs −
Figure 12.2 The CE amplifier at high frequencies
RC
Rs Cce + Vs
R2
R1
Cbe
Cwi
Cwo
RL
CMo
CMi
−
Figure 12.3 The ac circuit of Figure 12.2
Co = Cwo + Cce + CMo = Cwo + Cce + Cbe Ci = Cbe + Cwi + CMi = Cbe + Cwi + Cbc (1 − A) Cbe , Cbc , Cce are the interelectrode capacitors, Cwi and Cwo are the stray wiring capacitances on the input and the output side, and CMi and CMo are the Miller capacitances on the input and the output side. Ci is the effective input capacitance and Co is the effective output capacitance. If R = R1  R2 and RL′ = RL  RC , the circuit shown in Figure 12.3 reduces to that shown in Figure 12.4.
Rs
Co
+
R
R′L
Ci
Vs −
Figure 12.4 The simplified circuit of Figure 12.3
595
HighFrequency Transistor and FET Amplifiers
Replacing the transistor by a current source, Figure 12.4 is simplified to that shown in Figure 12.5. Here, Ri is the input resistance and Ro is the output resistance. Application of Thévenin’s theorem on the input side gives, Vthi and Rthi , which are Thévenin’s voltage source and internal resistance, respectively. Rthi = Rs  R  Ri . Vtho and Rtho are the Thévenin’s source and the internal resistance on the output side. The resistance Rtho = Ro  RL′ is indicated in Figure 12.6. At high frequencies, the effect of Ci is to reduce the input voltage as X Ci becomes small, and hence I b. Similarly at high frequencies, X Co reduces and hence the output voltage. As the frequency increases further, the output reduces to zero. The upper 3dB frequency for the input 1 circuit is fHi = and the upper 3dB 2pRthiCi frequency of the output circuit is
Ib hfeIb
Rs R
+
Ci
R′L
Co
Ro Ri
Vs −
Figure 12.5 Circuit of Figure 12.4 with transistor replaced by its approximate model
Rtho Rthi
− Ci
+
+
Vthi
fHo =
Co
Vtho
Figure 12.6 The simplified circuit
1 2pRthoCo
(12.3)
It is clear from the above discussion that the network parameters can influence the response of the amplifier.
12.4
HIGHFREQUENCY EQUIVALENT CIRCUIT OF THE TRANSISTOR
To calculate the gain at high frequencies, the highfrequency equivalent circuit of the transistor should be drawn. Consider the transistor shown in Figure 12.7. Let us start drawing the highfrequency transistor model using Figure 12.7. Here, B is the external base lead and B′ is the internal base lead. Between these terminals, we have what is known as the basespreading resistance rbb′, which is due to the resistance between the external base lead and the active region of the base and the resistance of the active base region. Also, in a transistor, the emitter is relatively highly doped and depending on the amount of doping, there exists a resistance between B′ and the emitter, that is rb ′ e and an interelectrode capacitance Cb ′ e. Further, the collector is lightly doped and between B′ and the collector,
Collector
r b′c r bb′ B
B′
Base
r b′e
Emitter
Figure 12.7 Transistor with its internal resistances
596
Electronic Devices and Circuits
there appears rb ′ c and an interelectrode capacitance Cb ′c. A relatively large resistance rce appears between the collector and emitter terminals. If Vb ′ e is the voltage between B′ and emitter, then gmVb ′ e is the collector current. The equivalent circuit is shown in Figure 12.8. This circuit is also called Giacoletto model or hybrid p model of the transistor. rb′c = 1/gb′c rbb′
Ic
B′
B Base
Collector Ib
Cb′e = Ce rb′e
+
+
Vb′e
Cb′c = Cc rce = 1/gce
Vce
gmVb′e
= 1/gb′e
−
− Emitter
Figure 12.8 The highfrequency model of the transistor
12.5
CALCULATION OF HIGHFREQUENCY PARAMETERS IN TERMS OF THE LOWFREQUENCY PARAMETERS
The lowfrequency parameters of a transistor are already calculated around an operating point and are listed in Table 6.1. We now try to calculate the highfrequency parameters of the transistor.
12.5.1 The Transconductance, gm Consider the transistor circuit in Figure 12.9. Under ac conditions, the collector is shorted to ground. It has been noted earlier that the collector current in the active region is given by I C = I CO + a o I E
(12.4)
I C − I CO = a o I E
(12.5)
or
where I CO is the leakage current and a o I E is the collector current. From Figure 12.8, I C = I E = gmVB ′E.
By definition, gm =
∂I C ∂VB ′E
IC VCE
From Eqn. (12.4),
r bb′ B
∂I E ∂I = ao E gm = a o ∂VB ′E ∂VE
(12.6)
B′ VCC
+
V B′E = V E
IE
−
since VB ′E = VE
Figure 12.9 Circuit to calculate gm
HighFrequency Transistor and FET Amplifiers
If re is the resistance of the emitter diode, re =
597
∂VE . Using Eqn. (12.6), ∂I E
gm =
ao re
(12.7)
But we also know that
I eV hV dI I = s = dV hVT hVT T
rf =
dV hVT = dI I
VT . I Hence for the emitter diode, and if h = 1, then rf =
re =
VT IE
(12.8)
where VT = kT q is the volt equivalent of temperature and at room temperature VT = 26 mV. Substituting Eqn. (12.8) in Eqn. (12.7), gm = a o
IE VT
(12.9)
Using Eqn. (12.5), gm =
I C − I CO I C I C ≈ = VT VT 26
(12.10)
since I CO > rb′e. Therefore, it is evident from Figure 12.8 that I b flows through rb′e. The short circuit collector current is given as follows:
598
Electronic Devices and Circuits
I c = gmVb′e = gm I b rb′e
(12.11)
hfe, the short circuit current gain is hfe =
Ic Ib
VCE
From Eqn. (12.11), hfe = gm rb′e Using Eqn. (12.10),
rb′e =
hfe hfeVT = gm IC
(12.12)
gm hfe
( 12.13)
or
g b ′e =
12.5.3 Feedback Conductance, gb′c hre is defined as the reverse voltage gain with the input open circuited. With I b = 0, the circuit of Figure 12.8 is as shown in Figure 12.10, since at low frequencies Ce and Cc behave as open circuits.
hre =
Vb′e rb′e = Vce rb′e + rb′c
From the above relation, hre ( rb′e + rb′c ) = rb′e Therefore, rb′e (1 − hre ) = hre rb′c Since hre > rb′e
12.5.4 The BaseSpreading Resistance, rbb′ hie is the input resistance with the output shorted. From Figure 12.8, if the output is shorted rb′c and rb′e are in parallel, but rb′c >> rb′e. Therefore, rb′c  rb′e = rb′e Hence, hie = rbb′ + rb′e
(12.16)
rbb′ = hie − rb′e
(12.17)
or
From Eqn. (12.12) and Eqn. (12.16), hie = rbb′ +
hfeVT hfeVT ≈ IC IC
(12.18)
600
Electronic Devices and Circuits
12.5.5 Output Conductance gce hoe is the output admittance, defined as the ratio of I c to Vce with input open circuited. With I b = 0, the circuit in Figure 12.8 is drawn as shown in Figure 12.11. From Figure 12.11, Ic
rb′c
B′
V Vce I c = ce + + gmVb′e rce rb′c + rb′e
(12.19)
+ rce rb′e
Also with I b = 0,
Vce
gmVb′e
−
Vb′e = hreVce
(12.20) Figure 12.11 Circuit to calculate gce
Substituting Eqn. (12.20) into Eqn. (12.19), Ic =
hoe =
Vce Vce + + gm hreVce rce rb′c + rb′e
(12.21)
Ic 1 1 = + + gm hre Vce rce rb′c + rb′e
(12.22)
But we know that rb′c >> rb′e. Therefore, Eqn. (12.22) is written as follows: hoe =
1 1 + + gm hre rce rb′c
Or hoe = gce + gb′c + gm hre
(12.23)
From Eqn. (12.13), we have gb′e = gm hfe , and therefore gm = hfe gb′e
(12.24)
From Eqn. (12.15), we have gb′c = gb′e hre , and therefore hre =
g b ′c g b ′e
(12.25)
From Eqs (12.24) and (12.25), g gm hre = hfe gb′e b′c = hfe gb′c g b ′e
(12.26)
HighFrequency Transistor and FET Amplifiers
601
Substituting Eqn. (12.26) in Eqn. (12.23), hoe = gce + gb′c + hfe gb′c = gce + gb′c (1 + hfe ) ≈ gce + gb′c hfe
(12.27)
gce = hoe − gb′c hfe
(12.28)
From Eqn. (12.15), gb′c = gb′e hre and from Eqn. (12.13), gb′e = gm hfe g gb′c = hre m hfe
(12.29)
Substituting Eqn. (12.29) in Eqn. (12.28), g gce = hoe − hfe hre m = hoe − hre gm hfe
(12.30)
From the above calculations, it can be noted that if the parameters of the transistor at low frequencies are known, it is possible to calculate the highfrequency parameters. The highfrequency model or the hybrid π model is valid for frequencies up to fT 3 , where fT is the frequency at which the shortcircuit current gain is unity. Typical parameters at I C = 1.3 mA are gm = 50 mA/V, rbb′ = 0.1 kΩ, rb′e = 1 kΩ, rb′c = 4 MΩ, rce = 80 kΩ , Cc = 3 pF, and Ce = 100 pF.
12.6
CE SHORTCIRCUIT CURRENT GAIN
The CE amplifier used at high frequencies is shown in Figure 12.12, and its highfrequency model is shown in Figure 12.13.
IL
+
Ib +
RL
Vce
Vi −
−
Figure 12.12 The CE amplifier at high frequencies
602
Electronic Devices and Circuits gb′c rbb′
Ic
B′
B
IL Ib
+
Ce
+ Cc
Vb′e
gb′e
gce
RL
gmVb′e
Vce
−
−
Figure 12.13 The equivalent circuit of Figure 12.12
To calculate of the short circuit current gain, short RL (Figure 12.14): gb′c rbb′
Ic
B′
B Ib
Ce
IL
+ Cc
Vb′e
gce
gb′e
RL= 0
gmVb′e −
Figure 12.14 The equivalent circuit with RL = 0
With RL = 0, Cc is in parallel with Ce. gb′c is small, and hence rb′c is large. Therefore, the current through it is negligible and is considered as an open circuit. Further, when RL = 0, gce = 0. Therefore, the resultant simplified equivalent circuit is shown in Figure 12.15. rbb′
B′
B
IL +
Ib
Vb′e gb′e = gm/hfe
Ce + Cc
gmVb′e
RL= 0
−
Figure 12.15 The simplified equivalent circuit
The load current I L is I L = − gmVb′e
(12.31)
I b = Vb′e gb′e + jw (Ce + Cc )
(12.32)
Using Eqs (12.31) and (12.32), Ai =
− gmVb′e IL − gm = = I b Vb′e gb′e + jw (Ce + Cc ) gb′e + jw (Ce + Cc )
(12.33)
HighFrequency Transistor and FET Amplifiers
603
Dividing by gb′e Ai =
− g m g b ′e jw (Ce + Cc ) 1+ g b ′e
(12.34)
From Eqn. (12.13), hfe =
gm g b ′e
(12.35)
Substituting Eqn. (12.35) in Eqn. (12.34), Ai =
− hfe = jw (Ce + Cc ) 1+ 1+ g b ′e
− hfe w j wb
(12.36)
where wb =
g b ′e gm = (Ce + Cc ) hfe (Ce + Cc )
(12.37)
From Eqn. (12.36), Ai =
At f = f b , Ai = hfe
hfe f 1+ fb
2
(12.38)
2 = 0.707 hfe . Hence, fb is the bandwidth with RL = 0.
Calculation of fT: Let us now define fT as the frequency at which the shortcircuit current gain of the CE amplifier becomes unity. That is, at f = fT , Ai = 1. We have from Eqn. (12.38), Ai =
1=
hfe f 1+ fb hfe f 1+ T fb
2
2
604
Electronic Devices and Circuits
2
f 1 + T = hfe fb Therefore, 2
f 1 + T = hfe2 fb 2
fT 2 2 f = hfe − 1 ≈ hfe b since hfe2 >> 1 Hence, fT = hfe or fT = hfe f b fb
(12.39)
Therefore, using Eqn. (12.37), we can write that fT = hfe f b =
hfe gm gm g = ≈ m 2p (Ce + Cc ) hfe 2p (Ce + Cc ) 2pCe
(12.40)
since Ce >> Cc From Eqn. (12.36) and Eqn. (12.39), Ai =
− hfe = f 1+ j 1+ fb
− hfe − hfe = f f 1 + jhfe j fT fT h fe
(12.41)
We have to note that fT is an important parameter, and fT = hfe f b. We also note that fT represents the shortcircuit current gain bandwidth. Here, hfe is the lowfrequency current gain and fb the upper 3dB frequency. Let us try to understand the relevance of fT.We have, f b = fT hfe . Let us take two transistors with same fT = 100 MHz. Let hfe of the first transistor be hfe1 = 10 , then fb 1 =
fT 100 = = 10 MHz. hfe1 10
fT 100 = = 12.5 MHz. hfe 2 8 Although transistors having the same fT are chosen, the bandwidth is different for the two of them. When larger bandwidth is desired, gain is sacrificed. Alternatively, if larger gain is the requirement, then bandwidth is to be sacrificed. Alternatively, let hfe of the second transistor be hfe2 = 8, then f b 2 =
HighFrequency Transistor and FET Amplifiers
Further, we know that fT =
605
gm g ≈ m 2p (Ce + Cc ) 2pCe
As gm is directly proportional to I C , the dc collector current, fT varies with I C . Variation of Ai with frequency is shown in Figure 12.16. Measurement of fT: fT can be, typically, 80–100 MHz. Therefore, to measure fT in the laboratory, it is required to have a signal generator that can deliver a constant input signal to the amplifier at 100 MHz and more and associated measuring instruments. Even if this sophisticated equipment is not available in the laboratory, it is possible to measure fT, with less sophisticated equipment usually available. Consider Figure 12.16. Choose a frequency,
½Ai½ hfe 0.707hfe ½Ai½ decreases linearly at 20dB/decade
½Ail½
1 0
fβ
f1
fT
f
Figure 12.16 Frequency vs shortcircuit current gain of CE amplifier
f1, which is 5 to 10 times larger than fb . If fb is 2MHz, choose f1 = 10 MHz. It is presumed that at least this generator and associated measuring instruments are usually available. Now, measure Ai1 at f1. Beyond f b, it can be noted that the shortcircuit current gain decreases linearly at the rate of 20dB/decade. We know that f1 Ai1 = fT × 1. Therefore, fT = f1 A i1 . If at f1 = 10 MHz, the measured value of Ai1 = 10, then fT = f1 A i1 = 10 × 10 = 100 MHz. Example 12.1 A transistor has hie = 2 kΩ, hfe = 50, IE = 2 mA, Cb′c= Cob = 3pF, and fT = 400 MHz at room temperature. Calculate gm, rb′e, rbb, and Cb′e. Solution: gm =
IC 2 × 10 −3 = 76.92 mA/V = VT 26 × 10 −3
rb ′ e =
hfe 50 = = 650 Ω gm 76.92
rbb ′ = hie − rb ′ e = 2000 − 650 = 1350 Ω gm 76.92 mA / V = = 30.62pF 2 p fT 2 × 3.14 × 400 × 106 Ce + Cc = Ce =
gm 2pfT gm − Cc = 30.62 − 3 = 27.62 pF 2p fT
606
Electronic Devices and Circuits
12.7
CE CURRENT GAIN WITH RESISTIVE LOAD
Let us now consider the CE current gain with resistive load (Figure 12.17). This circuit is redrawn in Figure 12.18 using the Miller’s theorem. gb′c rbb′
Ic
B′
B
IL Ib
Ce gb′e
+
+ Cc
Vb′e
gce
RL
Vce
gmVb′e −
−
Figure 12.17 The CE amplifier with resistive load rbb′
B′
B Ib
Ce gb′e
IL + Vb′e
gb′c (1A)
Cc (1A)
+
gb′c (A1)/A
gmVb′e gce Cc (A1)/A
RL
Vce −
−
Figure 12.18 Circuit of Figure 12.17, after using the Miller’s theorem
In order to simplify the circuit in Figure 12.18, the following assumptions are made: (i) In majority of the cases, the output time constant is very much smaller when compared to the input time constant. Hence, Cc ( A − 1) A ≈ Cc may be replaced by an open circuit. (ii) gb′c ( A − 1) A ≈ gb′c . Since gb′c t o, the upper halfpower frequency, fH = f2 is decided by t i only, as shown in Eqn. (12.49). In general, if t i = RC , then f2 =
1 2pRC
(12.50)
In the circuit show in Figure 12.20, let a voltage source Vs with its internal resistance Rs drive the amplifier. Consider rbb′ and rb′e, as shown in Figure 12.21, and the circuit to calculate the input time constant, t i is shown in Figure 12.22. rbb′
B
B′
Rs
Cc (1+gmRL ) +
rb′e
Vs
+
gmVb′e
Vo
RL
Ce
−
−
Figure 12.21 Circuit with Vs driving the amplifier
rbb′
Cc (1+gmRL ) rb′e
R
Ce
C
Rs
Figure 12.22 Circuit to calculate t i
From Figure 12.22, R = ( Rs + rbb′ )  rb′e =
(Rs + rbb′ ) rb′e = (Rs + rbb′ ) rb′e Rs + rbb′ + rb′e Rs + hie
(12.51)
and C = Ce + Cc (1 + gm RL ) ≈ Ce + Cc gm RL
(12.52)
since, gm RL >> 1. But, from Eqn. (12.40), gm ≈ 2pCe fT
(12.53)
C ≈ Ce + Cc 2pCe fT RL = Ce (1 + 2pfTCc RL )
(12.54)
Substituting Eqn. (12.53) in Eqn. (12.52),
609
HighFrequency Transistor and FET Amplifiers
From Eqs (12.51) and (12.54), t i = RC =
(Rs + rbb′ ) rb′e × C Rs + hie
e
(1 + 2pfTCc RL )
(12.55)
From Eqn. (12.50), f2 =
Rs + hie 1 = 2pRC 2p ( Rs + rbb′ ) rb′eCe (1 + 2pfTCc RL )
(12.56)
The midband gain is AVs =
− hfe RL Rs + hie
AVs =
hfe RL Rs + hie
(12.57)
From Eqs (12.56) and (12.57), the gain–bandwidth product is AVs f2 =
hfe RL h RL 1 = fe × × 2p ( Rs + rbb′ ) rb′eCe (1 + 2pfTCc RL ) rb′e ( Rs + rbb′ ) 2pCe (1 + 2pfTCc RL )
(12.58)
But it is known that, gm =
gm 2pCe (1 + 2pfTCc RL )
(12.59)
2pCe fT RL fT = × 2pCe (1 + 2pfTCc RL ) ( Rs + rbb′ ) (1 + 2pfTCc RL )
(12.60)
AVs f2 =
RL
hfe rb′e
(Rs + rbb′ )
×
But, from Eqn. (12.53), gm ≈ 2pCe fT AVs f2 =
RL
(Rs + rbb′ )
×
Similarly, when current gain is considered, the gain–bandwidth product is AIs f2 =
12.8
Rs
×
fT
(Rs + rbb′ ) (1 + 2pfTCc RL )
(12.61)
HYBRID p CAPACITANCES
Two capacitances Cc and Ce can be easily identified in the hybrid p model of the transistor.
12.8.1 The Collector Junction Capacitance Cc The collector junction capacitance Cc ( = Cb ′ c ) is the output capacitance in the CB configuration, with I E = 0 and is normally specified in the data sheet by the manufacturer as Cob. As the amplifier
610
Electronic Devices and Circuits
is operated in the active region, the collector–base diode (collector diode) is reverse biased. Under these conditions, Cc ( = Cob ) varies inversely as the reversebias voltage: Cc ∝
1
(VCE )
n
= (VCE )
−n
(12.62)
where n = 12 for an abrupt junction and n = 13 for a graded junction. Cc decreases as VCE increases and vice versa. However, variations in I C and temperature, T have no influence on capacitance, Cc
12.8.2 The Emitter Junction Capacitance Ce P
N
P
In the active region, the base–emitter diode (emitter p(0) diode) is forward biased and the base–collector (collector diode) is reverse biased. Therefore, Ce ( = Cb′e ) is the sum of the emitter diffusion capacitance, CD and the emitter junction capaciC tance, CJ. That is, Ce = CD + CJ ≈ CD , since CJ is small. E B p(W) Ce = CD is calculated as illustrated in Figure 12.23 that x=0 x=W depicts the emitter–base and base–collector junctions of a PNP transistor. The width of the base, W is very Figure 12.23 Emitter–base and base–collector junctions of a transistor small, typically of the order of 1 μ. = 10 −6 m .
(
)
The assumptions we make in trying to evaluate CD are (i) W ( Rs + rbb′ )Cc gm or CL >> gm ( Rs + rbb′ )Cc
(12.88)
616
Electronic Devices and Circuits
If for the given transistor, gm = 50 mA/V , Rs = 100 Ω, rbb′ = 200 Ω, and Cc = 3 pF, then from Eqn. (12.88): CL >> 50 × 10 −3 × (100 + 200 ) × 3 × 10 −12 Therefore, CL >> 45 pF If CL = 100 pF and Ce = 100 pF , then from Eqn. (12.83): (12.89)
fH = f T
The input circuit that enables us to calculate Vi is shown in Figure 12.27. Ri is the input resistance of the emitter follower which is large. rbb′ From Figure 12.27, Vi =
Vs Ri ≈ Vs Ri + Rs + rbb′
(12.90)
+ Rs
Ri +
Therefore, Ahs = Ah, where Ahs is the overall voltage gain.
Vs
Vi −
−
Gain × bandwidth = Am fH ≈ fH
Figure 12.27 Circuit to calculate Vi
12.10
CB AMPLIFIER AT HIGH FREQUENCIES
Let us now calculate the shortcircuit current gain of the CB amplifier as shown in Figure 12.28. Its simplified highfrequency circuit is shown in Figure 12.29. Ic
Ie Ie
Ic
+ Vi
RL
C
B′
E
C
E
rb′e
+
+
Vo
Vi
−
−
rb′c RL rbb′
− B
B
Figure 12.28 CB amplifier rce Ie
Ic
E − Vb′e +
C
gmVb′e
rb′e Cb′e
Cb′c
rb′c
B′ rbb′ B
Figure 12.29 Circuit at high frequencies
RL
HighFrequency Transistor and FET Amplifiers
617
To calculate the short circuit current gain, set RL = 0 in Figure 12.29. The result is the equivalent circuit in Figure 12.30. rce Ie
Ic
E −
gmVb′e
rb′e
Vb′e
C
Cb′e
+
Cb′c
rb′c
RL = 0
B′ rbb′ B
Figure 12.30 Equivalent circuit with RL = 0
Let us now simplify the circuit in Figure 12.30. Cb′c = Cc is small, typically, 3pF, and hence is replaced by an open circuit as it offers high reactance in the frequency range of operation. With RL = 0, rbb, and rb′c are in parallel. Typically, rbb′ = 200 Ω and rb′c = 4 MΩ. Hence, rb′c can be replaced by an open circuit. Further, with RL = 0, rce is in parallel with hie ( = rbb′ + rb′e ) . Typically, hie = 1.1 kΩ and rce = 80 kΩ. Hence, rce can be considered to be an open circuit. These approximations result in the simplified circuit shown in Figure 12.31. Ie
Ic
E −
gmVb′e
rb′e
Vb′e
Cb′e
+
C
RL = 0
B′ rbb′ B
Figure 12.31 Simplified equivalent circuit
From Figure 12.31, I c = − gmVb′e
(12.91)
Let Z be the parallel combination of rb′e and Cb′e. Then, Vb′e = − ( I e + gmVb′e ) Z
(12.92)
or Vb′e (1 + gm Z ) = − I e Z −I e =
Vb′e (1 + gm Z ) 1 = Vb′e gm + Z Z
(12.93)
618
Electronic Devices and Circuits
However, 1 rb′e jwCb′e rb′e 1 Z = rb′e  = = 1 jwCb′e r + 1 + jwrb′eCb′e b ′e jwCb′e
(12.94)
Substituting Eqn. (12.94) in Eqn. (12.93), 1 + gm rb′e + jwrb′eCb′e 1 + jwrb′eCb′e 1 − I e = Vb′e gm + = Vb′e gm + = Vb′e Z rb′e rb′e 1 + gm rb′e + jwrb′eCb′e I e = −Vb′e rb′e
(12.95)
I c = − gmVb′e
(12.96)
and
Ai, the shortcircuit current gain in the CB configuration, using Eqs (12.95) and (12.96), is Ai =
Ic = Ie
− gmVb′e gm rb′e = 1 + gm rb′e + jwrb′eCb′e 1 + gm rb′e + jwrb′eCb′e −Vb′e rb′e
(12.97)
But from Eqn. (12.12), gm rb′e = hfe
(12.98)
Substituting Eqn. (12.98) in Eqn. (12.97),
Ai =
hfe 1 + hfe + jwrb′eCb′e
where
hfe 1 + hfe hfb = = jwrb′eCb′e f 1+ j 1+ fa 1 + hfe
(12.99)
hfe 1 + hfe
(12.100)
1 + hfe 2prb′eCb′e
(12.101)
hfb = and fa =
Ai =
hfb f 1+ fa
2
(12.102)
At f = fa , Ai = hfb 2. Therefore, fa is the upper halfpower frequency. fa can also be expressed differently. From Eqn. (12.101), fa can be written down as follows:
619
HighFrequency Transistor and FET Amplifiers
1 + hfe
fa =
2prb′eCb′e
hfe hfe
(12.103)
But from Eqn. (12.98), rb′e 1 = hfe gm
(12.104)
Substituting Eqn. (12.104) in Eqn. (12.103), fa =
g (1 + hfe ) 1 + hfe gm gm = m = = h hfe 2pCb′e hfb 2pCb′e hfe 2pCb′e fe 2pCb′e gm (1 + hfe )
(12.105)
fa can be expressed also in another different form. From Eqn. (12.101), fa =
1 + hfe 2prb′eCb′e
Multiplying both numerator and denominator in Eqn. (12.101) by 1 2prb′eCb′e (1 + hfe ) 1 2prb′eCb′e fa = 1 1 + hfe
(12.106)
h 1 = 1 − fe = 1 − hfb 1 + hfe 1 + hfe
(12.107)
But
Also, from Eqn. (12.39), fb ≈
1 2prb′eCb′e
(12.108)
Substituting Eqs (12.107) and (12.108) in Eqn. (12.106), fa =
fb 1 − hfb
(12.109)
Example 12.2 A transistor has gm = 25 millimhos , rbb’ = 200 Ω, hie = 5.2 kΩ, Cb’c = 10 pF , Cb’e = 65pF, and hfe = 100 . Calculate fa , fb , and unity gain bandwidth product of CE amplifier.
620
Electronic Devices and Circuits
Solution: We have rb’e = hie − rbb’ = 5.2 − 0.2 = 5 kΩ. fa =
1 + hfe 1 + 100 = = 49.49MHz 2p Cb’e rb’e 2p × 65 × 10 −12 × 5 × 103
fb =
1 1 = = 0.425MHz 2p rb’e (Cb’e + Cb’c ) 2p (65 + 10 )10 −12 × 5 × 103
fT = hfe f b = unity gain bandwidth product = 100 × 0.425 = 42.5MHz
12.11
HIGHFREQUENCY FET CIRCUITS
Let us consider the behavior of an FET at high frequencies. At low frequencies, we have neglected the effect of the interelectrode capacitances. However, their influence is to be considered when we talk of an FET amplifier at high frequencies. The low frequency equivalent of an FET (either JFET or MOSFET) is already considered in Chapter 7. The equivalent circuit at high frequencies is obtained by simply considering the interelectrode capacitances also as shown in Figure 12.32.
Cgd
G
D
+ gmVi
Vi
rd
Cgs
Cds
− S
Figure 12.32 Highfrequency equivalent circuit of FET
12.11.1 CS Amplifier at High Frequencies Consider the smallsignal CS amplifier at highfrequency amplifier shown in Figure 12.33 and its equivalent circuit as shown in Figure 12.34. VDD ZL
+
gmVi rd
Cgs
Vo Vi
D
+ Vi
+ +
Cgd
G
ZL
Vo
Cds
−
−
−
S
Figure 12.33 CS amplifier
Figure 12.34 Equivalent circuit
Corollaries of Thévenin’s and Norton’s theorems are widely used to simplify network analysis. If V is the opencircuit voltage and I the shortcircuit current, and if Z (or Y) is the impedance (or admittance) between the two terminals 1 and 2 (Figure 12.35), then the opencircuit voltage shortcircuit current theorem implies that 1
1
Z +
I= V Z
V −
Z
2
(a) Thévenin circuit
2 (b) Norton circuit
Figure 12.35 Thévenin’s circuit in (a) is replaced by a Norton circuit in (b)
HighFrequency Transistor and FET Amplifiers
Z=
V I
V = VY Z I V = IZ = Y I=
621
(12.110)
where V is the opencircuit voltage and I is the shortcircuit current as shown in Figure 12.35. Hence, to find out the output voltage Vo , of the CS amplifier in Figure 12.34, we need to calculate Z and I . To calculate Z, set Vi = 0. When Vi = 0, then gmVi = 0. That is, the current is zero. Hence, replace the current source by an open circuit. Hence, to calculate Z, set Vi = 0, Figure 12.36. The resultant circuit is shown in Figure 12.37. Cgd
G
D
+ Set Vi = 0
gmVi
Vi
rd
Cgs
ZL
Cds
− S
Figure 12.36 Circuit to calculate Z D
gmVi = 0
rd
Cgd
ZL
Cds S Z
Figure 12.37 Circuit of Figure 12.36 with Vi set to zero
From Figure 12.37, 1 = YL + Yds + Ygd + gd (12.111) Z 1 1 where YL = , Yds = jwCds , Ygd = jwCgd , and gd = . ZL rd Having calculated Z, we now calculate I. To calculate I, short D and S in Figure 12.34. The resultant circuit is shown in Figure 12.38. Y=
G
Cgd
D
I
+ gmVi
Vi
Short D and S rd
Cgs
ZL
Cds
− S
Figure 12.38 Circuit to calculate I
622
Electronic Devices and Circuits Cgd
From Figure 12.38, Vi is seen to appear across Cgd . The simplified circuit is as shown in Figure 12.39. From Figure 12.39, writing down the KCL equation at node X
(
I = − gmVi + VY i gd = Vi − g m + Ygd
)
+
Vi
I
X
D
− gmVi
(12.112) S
(i) Voltage gain: The voltage gain AV is
Figure 12.39 Simplified circuit
AV =
Vo IZ I = = Vi Vi YVi
(12.113)
Substituting Eqs (12.111) and (12.112) in Eqn. (12.113), AV =
(
Vi − gm + Ygd
)
(
Vi YL + Yds + Ygd + gd
(−g
=
) (Y
L
m
+ Ygd
)
+ Yds + Ygd + gd
(12.114)
)
At low frequencies, the interelectrode capacitances are neglected. Hence, Ygd = Yds = 0. Therefore, Eqn. (12.114) reduces to AV =
(
(
Vi − gm + Ygd
)
Vi YL + Yds + Ygd + gd
=
− gm
) (YL + gd )
=
− gm rd ZL − gm = = − gm ZL′ 1 1 ( rd + ZL ) Z + r L
(12.115)
d
where ZL′ = ZL  rd
(12.116)
Equation (12.115) gives the gain of the CS amplifier at low frequencies. (ii) Input admittance: From the circuit in Figure 12.34, there is no isolation between the input and the output. Cgd appears between the input and the output. By using the Miller’s theorem, Ygd can be replaced by two admittances Y1 andY2: Y1 in shunt with the input terminals and Y2 in shunt with the output terminals. G
A − 1 Y1 = Ygd (1 − AV ) and Y2 = Ygd V AV
+
(12.117)
Y1 = Ygd (1Av)
Vi Ygs −
The input circuit of Figure 12.34, using Eqn. (12.117), is as shown in Figure 12.40. From Figure 12.40, Yi = Ygs + Ygd (1 − AV )
S
Yi
(12.118)
Figure 12.40 Circuit to calculateYi
623
HighFrequency Transistor and FET Amplifiers
The Miller capacitor that appears at the input terminals, Ci, using Eqn. (12.118) is Ci =
Yi = Cgs + Cgd (1 − AV ) jw
(12.119)
We know that AV = − gm RL’ , where RL’ = rd / / RD , and Eqn. (12.119) is written as follows: Ci = Cgs + Cgd (1 + gm RL′ )
(12.120)
The input capacitance Ci is seen to be large and as the frequency increases its reactance decreases. If the output of a CS amplifier with load RL is connected to the input of this amplifier, the effective load decreases at high frequencies, thereby reducing the gain. (iii) Output admittance: From Figure 12.34, to calculate Yo, open ZL and set Vi = 0. Then, gmVi = 0. That is, open the current source. The admittance seen between the output terminals is Yo . Since AV is large, D
Cgd
AV − 1 ≈ Cgd AV
(12.121) rd
Cgd Cds
The output circuit to determine Yo is shown in Figure 12.41. From Figure 12.41,
S Yo
(12.122)
Yo = Ygd + Yds + gd
Figure 12.41 Circuit to calculateYo
12.11.2 Common Drain Amplifier at High Frequencies The CD amplifier is also known as the source follower. Consider the CD amplifier circuit in Figure 12.42. The highfrequency equivalent circuit is presented in Figure 12.43. VDD
+
G
+ Vi RS −
+
+
Vo
Vi
Figure 12.42 CD amplifier or source follower
−
Cgs S + gmVgs
Csn
Cgd
− N
Vgs
rd
RS
Vo
Cds
−
− D
N
Figure 12.43 Equivalent circuit
To calculate Z, for the circuit in Figure 12.43, set Vi = 0 as shown in Figure 12.44. With Vi = 0, the current gmVgs is zero. Hence, open the current source. The simplified equivalent circuit is as shown in Figure 12.45. Csn is a stray capacitance.
624
Electronic Devices and Circuits
+
Vgs
−
Cgs
G
S
+
+ gmVgs
Vi
Set Vi = 0
Csn
Cgd
rd
RS
Vo
Cds
−
− D
N
Figure 12.44 Circuit to calculate Z
S
Cgs
S
Csn
gmVgs
rd
RS
CT
rd
RS
Cds D
N
N Y
Figure 12.45 Simplified circuit to calculate Z
From Figure 12.45, Y = Ygs + Yds + Ysn + gd + gS where gd =
(12.123)
1 1 , gS = ,Ygs = jwCgs ,Yds = jwCds , andYsn = jwCsn rd RS
Let YT = Ygs + Yds + Ysn
(12.124)
Y = YT + gd + gS
(12.125)
Then
From Eqn. (12.124),
(
jwCT = jw Cgs + Cds + Csn
)
or CT = Cgs + Cds + Csn
(12.126)
625
HighFrequency Transistor and FET Amplifiers
To calculate I, short S and N terminals in Figure 12.43. The resultant circuit is shown in Figure 12.46 +
G
Vgs
−
Cgs
I
S
+ gmVgs
Vi
Csn
Cgd
rd
Short S and N
RS
Cds
− D
N
Figure 12.46 Circuit to calculate I
The simplified circuit is as shown in Figure 12.47 From Figure 12.47,
Cgs +
(12.127)
I = gmVgs + YgsVi
Vi
S
I
− Short S and N
gmVgs
From Figure 12.43, D
(12.128)
Vgs = Vi − Vo
N
Figure 12.47 Simplified circuit
Substituting Eqn. (12.128) in Eqn. (12.127),
(
)
I = gmVgs + YgsVi = gm (Vi − Vo ) + YgsVi = Vi gm + Ygs − gmVo
(12.129)
(i) Voltage gain: Vo = IZ =
(
)
I Vi gm + Ygs − gmVo = YT + gd + gS Y
(
Vo (YT + gd + gS + gm ) = Vi gm + Ygs
AV =
gm + Ygs Vo = = Vi YT + gd + gS + gm
gm + jwCgs 1 jwC T + g d + g m + RS
=
(12.130)
)
(g
m
)
+ jwCgs Rs
1 + Rs ( jwCT + gd + gm )
(12.131)
Equation (12.131) gives the gain of the CD amplifier at high frequencies. At low frequencies, since Ygs = YT = 0, Eqn. (12.131) reduces to AV = In practice, AV < 1.
gm RS gm ≈ 1 + RS ( gd + gm ) gm + gd
(12.132)
626
Electronic Devices and Circuits
(ii) Input Admittance: To calculate the input admittance, Yi, Cgs is replaced by Miller’s capacitor on the input side as shown in Figure 12.48.
G + Vi
Y1 = Ygs (1Av)
Ygd
From Figure 12.48, −
Yi = Ygd + Ygs (1 − AV )
(12.133)
N
Yi
Figure 12.48 Circuit to calculateYi
Since AV ≈ 1, Eqn. (12.133) reduces to
(12.134)
Yi = Ygd = jwCgd S
(iii) Output admittance: To calculate Yo, in Figure 12.43, open RS and set Vi = 0. Then gmVi = 0. That is, open the current source. The admittance seen between the output terminals is Yo . The output circuit to determine Yo is shown in Figure 12.49.
gd
CT
From Figure 12.49,
D Yo
(12.135)
Yo = YT + gd
Figure 12.49 Circuit to calculate Yo
Additional Solved Examples Example 12.3 At room temperature, the following parameters are listed for a silicon transistor: IC = 1.3 tmA and VCE = 10 V. hie = 2000 Ω, hoe = 25 × 10 −6 , hfe =60 and
hre = 2 × 10 −4
It is also known that fT = 100 MHz
and
Calculate the values of the hybrid p parameters. Solution: (i) gm =
I C 1.3 × 10 −3 = 0.05 A / V = VT 26 × 10 −3
(ii) rb’e =
hfe 60 = = 1200 Ω gm 0.05
(iii) rbb’ = hie − rb’e = 2000 − 1200 = 800 Ω (iv) rb’c = gb’c =
rb’e 1200 = = 4.8 M Ω hre 2.5 × 10 −4 1 = 0.21µmhos 4.8 × 106
Cob = 3pF
HighFrequency Transistor and FET Amplifiers
627
−6 −6 −6 (v) gce = hoe − hfe gb ′ c = 25 × 10 − 60 × 0.21 × 10 = 12.4 × 10 mhos
rce =
(vi)
1 1 = = 80.65 kΩ gce 12.4 × 10 −6
gm 0.05A / V = = 79.6 pF 2p fT 2 × 3.14 × 100 × 106 Ce + Cc =
Therefore,
Ce =
gm 2p fT
Cc = Cob = 3pF
gm − Cc = 79.6 − 3 = 76.6 pF 2p fT
Example 12.4 A CE amplifier has the shortcircuit current gain Ai = 10 at 20 MHz. The transistor used has hfe = 50. Find fb and fT. Solution: We have 2
Ai =
hfe f 1+ fb
2
10 =
20 50 =5 1+ = 10 fb
50 20 1+ fb
2
2
20 1 + = 25 fb
f b2 =
400 = 16.67 24
f b = 4.08MHz
fT = hfe f b = 50 × 4.08 = 204 MHz
Example 12.5 A CE amplifier is used at high frequencies. The transistor is operated at IC = 2 mA and has hfe = 100. C e = 37pF and Cc = 3 pF. Determine f b and fT . Solution: gm =
IC 2 = = 0.077 A / V VT 26 fb =
Ce + Cc = 37 + 3 = 40 pF
gm 0.077 = = 3.065 MHz 2p (Ce + Cc ) hfe 2p × 40 × 10 −12 × 100
fT = hfe f b = 100 × 3.065 = 306.5 MHz
628
Electronic Devices and Circuits
Example 12.6 The shortcircuit current gain of a CE amplifier is 15 at f = 150 KHz. f b = 0.25 MHz. Find the unity gain bandwidth. Solution: We have Ai =
15 =
hfe f 1+ fb
2
hfe 150 1+ 250
2
2
150 hfe = 15 × 1 + = 15 × 1.17 = 17.55 250 fT = hfe f b = 17.55 × 0.25 = 4.39 MHz
Example 12.7 A CE amplifier is operated with RL = 1kΩ . At room temperature, the following parameters are listed for a silicon transistor: I C = 2.5 mA and VCE = 10 V . hie = 1500 Ω, hfe = 50. It is also known that fT = 500 MHz and Cob = 3 pF . Calculate fH and the midband voltage gain considering Rs = 1kΩ.
Solution: gm =
I C 2.5 = = 0.096 A / V VT 26 rb’e =
hfe 50 = = 520 Ω gm 0.096
rbb’ = hie − rb’e = 1500 − 520 = 980 Ω gm 0.096 = = 30.57 pF 2pfT 2p × 500 × 106 Ce =
gm − Cc = 30.57 − 3 = 27.57 pF 2pfT
C = Ce + Cc (1 + gm RL ) = 27.57 + 3 (1 + 0.096 × 1000 ) = 318.57 pF fH =
1 1 = = 0.96 MHz 2pCrb’e 2p × 318.57 × 10 −12 × 520
A = gm RL = 0.096 × 1000 = 96 Rs′ = Rs + rbb’ = 1000 + 980 = 1980Ω Avs = A ×
rb’e 520 = 96 × = 19.97 1980 + 520 Rs′ + rb’e
HighFrequency Transistor and FET Amplifiers
629
Example 12.8 A transistor is operated at IC = 2.6 mA and has hie = 1000 Ω, rbb’ = 200 Ω and Ce = 50 pF . Cc is negligible. Find (a) fT, (b) fb , (c) Ai at 5 MHz and at 50 MHz. Solution: gm =
I C 2.6 = = 0.1 A / V VT 26 rb’e = hie − rbb’ = 1000 − 200 = 800 Ω hfe = gm rb’e = 0.1 × 800 = 80
(i)
fT =
gm 0.1 = = 318.47 MHz 2pCe 2p × 50 × 10 −12
(ii)
fb =
fT 318.47 = = 3.98 MHz hfe 80
(iii)
At f = 5 MHz Ai =
hfe f 1+ fb
2
=
80 5 1+ 3.98
2
= 49.69
and at f = 50 MHz Ai =
hfe f 1+ fb
2
=
80 50 1+ 3.98
2
= 6.35
Example 12.9 For the CE amplifier shown in Figure 12.50, the transistor is operated at IC = 1.46 mA. RC = R3 = 3 kΩ , R1 = 20 kΩ , R2 = 5 kΩ , Rs = 500 Ω , hie = 2 kΩ , hfe = 50, Ce = 100 pF , Cc = 5 pF . Find the gain at f = 100 kHz and also determine fH. VCC = 20 V
RC R1 +
Cc Cc
Rs
R3
Vo
+ Vs
R2
CE
RE −
−
Figure 12.50 CE amplifier at high frequencies
630
Electronic Devices and Circuits
Solution: The simplified equivalent circuits are as shown in Figures 12.51 and 12.52. B
rbb′
B′
Rs +
+
gmVb′e
C R
RL
Vs
rb′e
Vo −
−
Figure 12.51 Simplified circuit B
rbb′
B′
R′s +
+
gmVb′e
C
RL
V ′s
rb′e
Vo −
−
Figure 12.52 Simplified circuit of Figure 12.51 using Thévenin’s theorem
RL = RC / / R3 = gm =
rb’e =
3×3 = 1.5 kΩ 3+3
R = R1 / / R2 =
20 × 5 = 4 kΩ 20 + 5
I C 1.46 = = 56.15 mA / V 26 VT
hfe 50 = = 893 Ω gm 0.056
rbb’ = hie − rb’e = 2000 − 893 = 1107 Ω C = Ce + Cc (1 + gm RL ) = 100 + 5(1 + 56.15 × 1.5 ) = 100 + 421 = 521pF 1 1 = = 3.06 kΩ 2pfC 2p × 100 × 103 × 521 × 10 −12 Z = rb’e / / Vs’ =
1 = 0.893 / /3.06 = 0.69 kΩ 2pfC
R 4000 × Vs = = 0.89Vs R + Rs 4000 + 500
Vb’e = Vs’ ×
Rs’ = Rs / / R =
690 Z = 0.89Vs × = 0.31Vs 440 + 1107 + 690 Rs’ + rbb’ + Z
0.5 × 4 = 0.44 kΩ 0.5 + 4
HighFrequency Transistor and FET Amplifiers
V0 = − gmVb’e RL = − gm × 0.31Vs RL
(
Avs =
631
Vo = − 0.31 × 56.15 × 1.5 = −26.11 Vs
)
Req = Rs’ + rbb’ / / rb’e = ( 440 + 1107 ) / /893 = 566.18 Ω fH =
1 1 = = 0.54 MHz 2pReqC 2p × 566.18 × 521 × 10 −12
Example 12.10 A transistor with IC = 1.5 mA is used as a highfrequency CE amplifier. hie = 1.1 kΩ, rbb’ = 0.1kΩ , Ce = 150 pF , and Cc = 5 pF . Calculate fH, when (i) RL = 0 and (ii) RL = 2 kΩ. Solution: rb’e = hie − rbb’ = 1.1 − 0.1 = 1kΩ gm =
I C 1.5 = = 57.69 mA / V VT 26
(i) When RL = 0, C = Ce + Cc = 150 + 5 = 155 pF fH =
1 1 = = 1.03 MHz 3 2p rb ′eC 2p × 1 × 10 × 155 × 10 −12
(ii) When RL = 2 kΩ, C = Ce + Cc (1 + gm RL ) = 150 + 5(1 + 57.69 × 2 ) = 150 + 115.38 = 731.9 pF fH =
1 1 = = 217.56 kHz 2prb ′ eC 2p × 1 × 103 × 731.9 × 10 −12
Example 12.11 A CE amplifier shown in Figure 12.53 has RC = 1 kΩ and RL = 1 kΩ. IC = 1.3 mA, hfe = 60, rbb′ = 300 Ω, Cc = 3 pF, and fT = 400 MHz. If it is required to have a bandwidth of 5 MHz, find Rs. VCC Solution: gm =
I C 1.3 = = 50 mA / V VT 26
rb’e =
hfe 60 = = 1200 Ω gm 0.05
hie = rbb’ + rb’e = 300 + 1200 = 1500 Ω
RC +
Cc Rs R3
Vo
+
1×1 RL = RC / / R3 = = 0.5 kΩ 1+1 Cc (1 + gm RL ) = 3 (1 + 50 × 0.5) = 78 pF
Vs −
Figure 12.53 CE amplifier with resistive load
632
Electronic Devices and Circuits
Ce =
gm 50 × 10 −3 = 19.9 pF = 2pfT 2p × 400 × 106
C = Ce + Cc (1 + gm RL ) = 19.9 + 78 = 97.9 pF Req =
Req =
1 1 = = 325.3 Ω 6 2pfHC 2p × 5 × 10 × 97.9 × 10 −12
(Rs + rbb’ ) rb’e Rs + rbb’ + rb’e
325.3 =
(Rs + 300)1200 Rs + 300 + 12200
Rs = 146 .1Ω
Example 12.12 A CE amplifier with RL = 1 kΩ has fH = 2 MHz. The transistor has gm = 37.5 mA/V, hfe = 75, rbb′ = 200 Ω, Cc = 5 pF, and fT = 200 MHz. Calculate (i) Rs that gives fH = 2 MHz and (ii) AVs with Rs calculated in (i). Solution: (i) rb’e =
hfe 75 = = 2000 Ω gm 37.5 hie = rbb’ + rb’e = 200 + 2000 = 2200 Ω
Cc (1 + gm RL ) = 5 (1 + 37.5 × 1) = 192.5 pF Ce + Cc =
gm 37.5 × 10 −3 = 29.86 pF = 2pfT 2p × 200 × 106
Ce = (Ce + Cc ) − Cc = 29.86 − 5 = 24.86 pF C = Ce + Cc (1 + gm RL ) = 24.86 + 192.5 = 217.36 pF Req =
Req = (ii)
1 1 = = 366.29 Ω 6 2pfHC 2p × 2 × 10 × 217.36 × 10 −12
(Rs + rbb’ ) rb’e Rs + rbb’ + rb’e
AVs =
366.29 =
(Rs + 200) 2000 Rs + 200 + 20000
Rs = 248.41 Ω
− hfe RL −75 × 1000 = = −30.63 Rs + hie 248.41 + 2200
h R Example 12.13 The midband gain of a CE amplifier with resistive load is given as AVs = fe L Rs + hie g RL 1 and fH = . Verify that AVs fH = m × . 2pReqC 2pC Rs + rbb ′
HighFrequency Transistor and FET Amplifiers
633
Solution: We have
(Rs + rbb’ ) rb’e
Req =
Rs + rbb’ + rb’e 1 1 = (R + r ) r (R + r ) r 2pC s bb ′ b ′ e 2pC s bb ′ b ′ e Rs + rbb ′ + rb ′ e Rs + hie
∴ fH =
since hie = rbb ′ + rb ′ e AVs = AVs fH =
hfe RL Rs + hie hfe RL × Rs + hie
hfe RL 1 = (Rs + rbb ′ ) rb ′ e 2pC (Rs + rbb ′ ) rb ′ e 2pC Rs + hie
But hfe = gm rb ′ e ∴ AVs fH =
gm rb ′ e RL g RL = m × 2pC ( Rs + rbb’ ) rb’e 2pC Rs + rbb ′
Example 12.14 A silicon PNP transistor has fT = 200 MHz, DB = 15 cm2/sec. What is the thickness of the base? Solution: We have fT =
gm 2pCe
and
Ce ( = CD ) = g m ×
W2 2DB
Therefore, fT =
gm 2
2pgm ×
W=
W 2DB
=
DB pW 2
W2 =
DB pfT
DB 15 = = 0.155 × 10 −3 cm pfT p × 200 × 106
Example 12.15 A PNP transistor operated at room temperature has a base width of 1.5 × 10 −4 cm , DB =15 cm2/sec and a dc collector current of 2.6 mA. Find (i) CD and (ii) fT.
634
Electronic Devices and Circuits
Solution:
gm =
I C 2.6 = = 100 mA / V VT 26
(
−3 −4 W 2 100 × 10 × 1.5 × 10 CD = g m × = 2DB 2 × 15
fT =
2
)
= 75 pF
gm 100 × 10 −3 = = 212.31 MHz 2pCD 2p × 75 × 10 −12
Example 12.16 A Germanium NPN transistor is used as a CE amplifier at high frequencies (Figure 12.54). Determine (i) gm, (ii) rb ′ e, (iii) hie, (iv) rb ′ c, (v) rce, (vi) Ce, and (vii) Avs at 100 kHz, given that rbb′ = 200 Ω, hfe = 75, hre = 2 × 10 −4, hoe = 25 × 10 −6 mhos, fT = 200 MHz, and Cc = 3 pF. VCC = 12 V 2.2 RC 100
R1
+
Cc 2.2
Cc
Rs
Vo
R3
500 100
+ R2
Vs
CE
RE 4.7 −
−
Figure 12.54 CE amplifier at high frequencies
Solution: To calculate IC, the dc circuit is shown in Figure 12.55. From Figure 12.55, V2 = VCC ×
R2 100 = 12 × = 6V 100 + 100 R1 + R2 VCC = 12 V
For the transistor to be in the active region, for the Ge transistor, VBE = 0.2 V. Therefore, VE = V2 − VBE = 6 − 0.2 = 5.8 V . R1
V 5.8 Hence, I E = I C = E = = 2.15 mA . RE 2.7 (i)
gm =
(ii) rb ′ e =
I C 2.15 = = 82.69 mA / V 26 VT hfe 75 = = 907 Ω gm 82.69 × 10 −3
2.2 RC
IC 100
+
+ VBE −
V2
100 R2
−
+
IE
VE RE 2.7 −
Figure 12.55 DC circuit to calculate IC
HighFrequency Transistor and FET Amplifiers
635
(iii) hie = rbb ′ + rb ′ e = 200 + 907 = 1107 Ω rb ′ e 907 = = 4.54 MΩ hre 2 × 10 −4 1 gb ′ c = = 0.22 m mhos 4.54 × 106 (v) gce = hoe − hfe gb’c = 25 × 10 −6 − 75 × 0.22 × 10 −6 = 8.5 × 10 −6 mhos (iv) rb ′ c =
1 1 = = 117.65 kΩ gce 8.5 × 10 −6 g 82.69 × 10 −3 = 65.84 pF (vi) Ce = m = 2pfT 2 × 3.14 × 200 × 106 2.2 × 2.2 (vii) RL = RC / / R3 = = 1.1kΩ 2.2 + 2.2 C = Ce + Cc (1 + gm RL ) = 65.84 + 3(1 + 82.69 × 1.1) = 65.84 + 275.9 = 341.74 pF rce =
1 1 = = 4.66 kΩ 3 2pfC 2p × 100 × 10 × 341.74 × 10 −12 1 Z = rb ′ e / / = 0.907 / /4.66 = 760Ω 2pfC 100 × 100 R = R1 / / R2 = = 50 kΩ 100 + 100 R 50 V s′ = × Vs = = 0.99Vs R + Rs 50 + 0.5
Rs′ = Rs / / R =
0.5 × 50 = 0.495 kΩ 0.5 + 50
Z 760 = 0.99Vs × = 0.517Vs 495 + 200 + 760 R ′s + rbb + Z V Vo = − gmVb’e RL = − gm × 0.517Vs RL Avs = o = −0.517 × 82.69 × 1.1 = −47.02 Vs
Vb ′ e = V s′ ×
Example 12.17 A transistor is operated at IC = 2.6 mA. rbb’ = 200Ω , hie = 1200 Ω , Cb’c = 10 pF . W = 1.25 × 10 −4 cm, DB = 10 cm2/sec. Calculate (i) gm, (ii) rb ′ e, (iii) hfe, (iv) Ce, (v) fa , (vi) fb , and (vii) fT . Solution: I C 2.6 = = 100 mA / V VT 26
(i)
gm =
(ii)
rb’e = hie − rbb’ = 1200 − 200 = 1kΩ
(iii) hfe = rb’e gm = 1 × 103 × 100 × 10 −3 = 100
(
−3 −4 W 2 100 × 10 × 1.25 × 10 (iv) CD = Ce = gm × = 2DB 2 × 10
(v)
fa =
2
)
= 78.13 pF
1 + hfe 1 + 100 = = 205.85 MHz 2pCb ′ e rb ′ e 2p × 78.13 × 10 −12 × 1 × 103
636
Electronic Devices and Circuits
1 1 = = 1.81 MHz 2prb ′ e (Cb’e + Cb ′ c ) 2p (78.13 + 10 )10 −12 × 1 × 103
(vi)
fb =
(vii)
fT = hfe f b = Unity gain bandwidth product = 100 × 1.81 = 181 MHz
Example 12.18 Consider the highfrequency amplifier shown in Figure 12.56. The amplifier is required to satisfy the following requirements: S ≤ 5, fL = 20 Hz, fH = 100 kHz, AVs (min) = −35, Rs = 0.5 kΩ The transistor used has rbb’ = 300 Ω, rb’e = 2000 Ω, Cc = 5 pF, Ce = 500 pF, and gm = 50 mA / V.
(
)
The amplifier is driven by a signal vs = 70.71 × 10 −3 sin 2p × 10 × 103 t . Design the circuit. VCC
RL R1 Cc Cc
Rs
Vo
+ R2
Vs
+
RE
CE
−
−
Figure 12.56 CE highfrequency amplifier
hfe = gm rb’e = 50 × 10 −3 × 2 × 103 = 100
Solution:
hie = rbb ′ + rb ′ e = 300 + 2000 = 2300 Ω (i) Selection of RL Given:
AVs (min) = 35
AVs (min) = RL =
hfe RL Rs + hie
35 =
hfe RL Rs + hie
35 ( Rs + hie ) 35 × 2.8 = = 0.98 kΩ hfe 100
Choose RL = 1.5 kΩ, as the gain will have to be more than 35. With RL = 1.5 kΩ, AVs =
hfe RL 100 × 1.5 = 53.57 = Rs + hie 0.5 + 2.3
(ii) Selection of RE: Vsm = 70.71mV Therefore, the maximum output swing is Vm = AVs × 70.71 = 53.57 × 70.71 = 3.79 V
HighFrequency Transistor and FET Amplifiers
Assuming, V
CE(sat )
637
≈ 0 , as the swing is symmetric with respect to VCE VCC = 2VCE = 2 × 3.79 = 7.58 V
Choose VCC = 9 V Then VCE = 4.5 V Usually, RE is chosen such that the drop across it, V 9 VE ≈ CC = = 0.9 V 10 10 The voltage drop VL , across RL is VL = VCC − VCE − VE = 9 − 4.5 − 0.9 = 3.6 V ∴ IE = IC =
VL 3.6 = = 2.4 mA RL 1.5
Hence, RE =
VE 0.9 = = 375 Ω I E 2.4
(iii) Selection of Req : C = Ce + Cc (1 + gm RL ) = 500 + 5(1 + 50 × 1.5 ) = 880 pF Req =
1 1 = = 1.81kΩ 2pfHC 2p × 0.1 × 106 × 880 × 10 −12
This means that to have fH = 100 kHz , Req = 1.81kΩ . Hence, in practice, to get the desired bandwidth, Req < 1.58 kΩ. Let us calculate Req from the given data. R = R1R2. Req = ( Rs / / R ) + rbb’ / / rb’e ≈ ( Rs + rbb’ ) / / rb’e = ( 0.5 + 0.3) / /2 = 0..570 kΩ Req < 1.58 kΩ Hence, it is possible to get the desired bandwidth. (iv) Selection of R1 and R2 S=
5=
1 + hFE RE 1 + hFE RE + R 1 + 100 375 1 + 100 375 + R
375 101 1 + 100 = = 20.2 375 + R 5 375 = 0.192 375 + R
638
Electronic Devices and Circuits
375 = 1953 0.192 R = 1953 − 375 = 1578 Ω
375 + R =
V2 = VE + 0.6 = 0.9 + 0.6 = 1.5 V R2 R1 + R2
V2 = VCC 1+
R1 VCC 9 = = =6 R2 V2 1.5 R1 = 5 Or R1 = 5R2 R2
But, R =
R1R2 5R2 R2 5R = = 2 R1 + R2 5R2 + R2 6
1578 =
5R2 6
R2 = 1.2 × 1578 = 1.89 kΩ
R1 = 5R2 = 5 × 1.89 = 9.45 kΩ (v) Selection of CE: RE 375 = = 37.5 Ω 10 10 1 = 212.31 mF CE = 2p × 20 × 37.5
For CE to be a bypass condenser, at f = 20 Hz, X CE ≈ 1 = 375Ω 2pfCE (vi) Selection of Cc:
Ri = R / / hie = 1.578 / /2.3 = 936 Ω Cc =
1 1 = = 8.51 mF 2p fRi 2p × 20 × 936
The designed amplifier circuit is shown in Figure 12.57. 9V
1.5 5 µF +
R1
10
RL +
Cc
Cc 500
Rs
Vs
+
Vo R2
2
200 µF + CE
RE 375
−
Figure 12.57 The designed CE amplifier
−
HighFrequency Transistor and FET Amplifiers
639
Example 12.19 For the circuit designed in example 12.18, determine (i) fH and (ii) AVs at 10kHz. (i) C = Ce + Cc (1 + gm RL ) = 500 + 5(1 + 50 × 1.5 ) = 880 pF Req = ( Rs / / R ) + rbb’ / / rb’e 0.5 × 1.58 = 0.38 kΩ 0.5 + 1.58 Rs’ + rbb’ = 0.38 + 0.3 = 0.68 kΩ Rs’ = Rs / / R =
(
)
Req = Rs’ + rbb’ / / rb’e = fH =
(ii)
0.68 × 2 = 0.51kΩ 0.68 + 2
1 1 = = 345.8 kHz 2pReqC 2p × 0.51 × 103 × 880 × 10 −12
1 1 = = 18.09 kΩ 3 2pfC 2p × 10 × 10 × 880 × 10 −12 1 = 2 / /18.09 = 1.8 kΩ Z = rb’e / / 2pfC R = R1 / / R2 = Vs′ =
R 1.67 × Vs = Vs = 0.77Vs R + Rs 1.67 + 0.5
10 × 2 = 1.67 kΩ 10 + 2 0.5 × 1.67 Rs′ = Rs / / R = = 0.385 kΩ 0.5 + 1.67
Z 1.8 = 0.77Vs × = 0.558Vs 0.38 + 0.3 + 1.8 Rs′ + rbb ′ + Z V Vo = − gmVb’e RL = − gm × 0.558Vs RL AVs = o = −0.558 × 50 × 1.5 = −41.85 Vs Vb ′ e = Vs′ ×
Example 12.20 A CS amplifier using an FET is connected to a resistive load RL = 100 kΩ. For the FET, rd = 50 kΩ, gm = 2 mA / V, Cgs = 3.5 pF , Cds = 1pF, and Cgd = 3 pF. Calculate the voltage gain and the input capacitance at (i) 200 Hz and (ii) 200 kHz. Solution: The expression for AV is AV =
− gm + Ygd YL + Yds + gd + Ygd
(i) At f = 200 Hz, Ygd = jwfCgd = j × 2p × 200 × 3 × 10 −12 = j 3.768 × 10 −9 mhos Yds = jwfCds = j × 2p × 200 × 1 × 10 −12 = j1.256 × 10 −9 mhos
640
Electronic Devices and Circuits
gd = YL =
1 1 = = 20 × 10 −6 mhos rd 50 × 103
1 1 = = 10 × 10 −6 mhos RL 100 × 103
YL + gd + Ygd + Yds = (20 + 10 )10 −6 + j (3.768 + 1.256 )10 −9 AV =
− gm + Ygd YL + Yds + gd + Ygd
=
−2 × 10 −3 + j 3.768 × 10 −9 −2000 = = −66.67 30 30 × 10 −6 + j 5.024 × 10 −9
since the j terms are very small, RL′ = rd / / RL =
50 × 100 = 33.33kΩ 50 + 100
The input capacitance, Ci is
(
)
(
)
Ci = Cgs + 1 + gm RL′ Cgd = 3.5 + 1 + 2 × 10 −3 × 33.33 × 103 × 3 = 206.48 pF (ii) At f = 200 kHz, Ygd = jwfCgd = j × 2p × 200 × 103 × 3 × 10 −12 = j 3.768 × 10 −6 mhos Yds = jwfCds = j × 2p × 200 × 103 × 1 × 10 −12 = j1.256 × 10 −6 mhos YL + gd + Ygd + Yds = (20 + 10 )10 −6 + j (3.768 + 1.256 )10 −6 AV =
 gm +Ygd YL +Yds + gd +Ygd
AV =
=
2 ´ 10 3 + j 3.768 ´ 10 6 30 ´ 10 6 + j 5.024 ´ 10 6
−2000 + j 3.768 30 + j 5.024
Multiplying the numerator and the denominator by the complex conjugate of (30 + j 5.024 ), AV =
=
( −2000 + j 3.768) (30 − j 5.024) (30 + j 5.024) (30 − j 5.024) ( −2000 × 30 + 3.768 × 5.024) + j (2000 × 5.024 + 3.768 × 30)
= −64.82 + j10.98
900 + 25.24
Taking only the real part of the gain, the input capacitance, Ci is Ci = Cgs + (1 − AV )Cgd = 3.5 + (1 + 64.82 ) × 3 = 200.96 pF
HighFrequency Transistor and FET Amplifiers
641
Summary • If C′ is a capacitor connected between the input and the output terminals of an amplifier, then the Miller capacitance in shunt with the input terminals is CMi = C ′ (1 − A) and the Miller capacitance in shunt with the output terminals is CMo = C ′
( A − 1) . A
I I • The transconductance is g m ≈ C = C VT 26 • The input conductance is g b′e =
gm hfe
• The basespreading resistance is rbb′ = hie − rb′e gm hfe • The highfrequency model or the hybrid p model is valid for frequencies up to fT 3, where fT is the frequency at which the shortcircuit current gain is unity. • The output conductance is g b′c = hre
• When the shortcircuit current gain is calculated in the CE mode, then the upper halfpower frequency is f b and fT = hfe f b . • When the current gain with resistive load is calculated, fH is the halfpower frequency • The collector junction capacitance Cc ( = C b′c ) is the output capacitance in the CB configuration, with I E = 0 and is normally specified in the data sheet by the manufacturer as Cob . • The emitter junction capacitance, Ce is the sum of the emitter diffusion capacitance, CD and the emitter junction capacitance, CJ .
multiple ChoiCe QueStionS 1. If the capacitor connected between the input and the output terminals of an amplifier is C ′ = 10 pF, and A = 100, then the Miller capacitance in shunt with the input terminals is (a) 10 µF (c) 1.01 nF
(b) 1 µF (d) 1.01 µF
2. If the capacitor connected between the input and the output terminals of an amplifier is C ′ = 10 pF, and A = 100, then the Miller capacitance in shunt with the output terminals is (a) 10 pF (c) 1 µF
(b) 10 µF (d) 1.01 nF
3. If IC = 1.3 mA, then g m is (a) 50 mA/V (c) 25 mA/V
(b) 100 mA/V (d) 200 mA/V
4. If hie = 2 kΩ and rb′e is 1 kΩ, then rbb′ is (a) 1 kΩ (b) 10 kΩ (c) 100 kΩ (d) 1 MΩ 5. If fT = 265 MHz (a) 30 pF (c) 3 pF
and g m = 50 mA/V , then Ce is (b) 300 pF (d) ∞
642
Electronic Devices and Circuits
6. If f b = 1 MHz and hfe = 100, then fT is (a) 10 MHz (b) 100 MHz (c) 1GHz (d) 7. rb’e (a) (b) (c) (d)
is proportional to the dc bias current through it inversely proportional to the dc bias current through it constant none of the above
8. rb’c is typically of the order of (a) 1 kΩ (c) 100 kΩ 9.
(b) 10 kΩ (d) 100 MΩ
fT is the frequency at which the shortcircuit current gain of CE configuration is (a) 1 (b) 10 (c) 100 (d)
10. fb is the frequency at which the shortcircuit current gain of CE configuration is (a) 1 (b) 10 (c) 100 (d) 0.707 times the midband gain
Short anSwer QueStionS 1. A capacitor C ′ exists between the input output terminals of a CE amplifier. What are the values of the Miller capacitances that appear in shunt with the input and the output terminals? 2. What is basespreading resistance? 3. What is the b − cutoff frequency of a BJT? 4. What is fT of a BJT? 5. What is the relationship between f b and fT ? 6. What is the relation between fa and f b ?
long anSwer QueStionS 1. Draw the hybrid p model of the transistor and obtain the relations that enable you to calculate the highfrequency parameters in terms of the lowfrequency parameters. 2. Obtain the expression for the shortcircuit current gain of CE amplifier and define the frequencies f b and fT . Obtain the interrelationship between f b and fT . 3. Obtain the expression for the current gain with resistive load for a CE amplifier and define the frequency fH . 4. Draw the highfrequency equivalent circuit of the CS amplifier and derive the expressions for the voltage gain, input impedance, and the output impedance. 5. Draw the highfrequency equivalent circuit of the CD amplifier and derive the expressions for the voltage gain, input impedance, and the output impedance.
W
HighFrequency Transistor and FET Amplifiers
643
unSolved problemS 1. A CE amplifier uses a transistor having hfe = 50, rbb’ = 200 Ω, and g m = 100 mA / V . The internal resistance of the voltage source driving the amplifier is 1 kΩ and the load resistance is 1 kΩ. fT = 500 MHz. Determine the midband gain taking Rs also into account and the upper 3dB frequency. 2. A PNP transistor operated at room temperature has a base width of 1.25 × 10 −6 m, DB =15 × 10 −4 m 2 / sec and a dc collector current of 2.5 mA. Find (i) Ce and (ii) fT 3. A BJT biased at IC = 5 mA, VCE = 5 V, produces the hybrid parameters as hie = 1.0 kΩ, hre = 10−4, hfe = 50, and hoe = 24 × 10−6 A/V, having fT = 50 MHz with Cb’c=Cob = 2 pF. Obtain the hybrid π parameters. 4. The midband current gain of a CE amplifier is 20 at 10 MHz. The lowfrequency parameters of the transistor are hie = 1.5 kΩ, hre = 10−4, hfe = 100, and hoe = 24 × 10−6 A/V. Determine the bcutoff frequency and unity gain bandwidth.
.
5. A transistor is operated at IC = 5 mA. rbb’ = 200 Ω, hie = 1200 Ω , C b’c = 10 pF. W = 1.25 × 10 −6 m, D = 0 −6 m, DB =10 ×10 −4 m / sec . Calculate (i) g m , (ii) rb’e , (iii) hfe , (iv) Ce , (v) fa , (vi) f b , and (vii) fT . 6. A CS amplifier using an FET is connected to a resistive load RL = 50 kΩ. For the FET, rd = 50 kΩ , g m = 2 mA / V, Cgs = 3.5 pF, Cds = 1pF , and Cgd = 3 pF . Calculate the voltage gain and the input capacitance at 100 Hz.
1
13
TUNED AMPLIFIERS
Learning objectives After going through this chapter, the reader will be able to
13.1
Realize the need for tuned amplifiers Understand the difference between smallsignal and largesignal tuned amplifiers Appreciate the difference between singletuned, staggertuned and synchronously tuned doubletuned voltage amplifiers Calculate the gain and bandwidth of these different tuned amplifiers Understand the working of a classC tuned power amplifier Understand the principle of frequency compensation in wideband amplifiers.
INTRODUCTION
We have seen that commonemitter amplifiers have large voltage and current gain. The voltage gain in a commonemitter amplifier is given as A = AI (RL Ri ), where RL is the load resistance and Ri is the input resistance. The load resistance RL cannot be made very large to make gain large, so as to satisfy the biasing requirements. These amplifiers also have reasonably large bandwidth, since the gain is not excessively large. However, consider a radio transmitter, in which amplitude modulation (AM) is used for signal transmission. In such a case, at the input of the radio receiver, we have a narrow band of frequencies (audio frequencies) with the carrier as the center frequency. The bandwidth of an AM transmitter is typically 10 kHz. The signal strength at the input of the radio receiver is typically of the order of a few microvolts. The strength of the signal will have to be raised to such a level so as to be able to drive an electromechanical device such as a loud speaker. Hence, the voltage amplifiers (RF and IF amplifiers) are required to give a large gain with narrow bandwidth. The impedance of a paralleltuned circuit is maximum at resonance and the tunedcircuit offers only a negligible dc resistance. Hence, biasing problems are taken care of, and at the same time large gain can be achieved in a single stage with resultant narrow bandwidth, which essentially is the requirement. Therefore, tuned amplifiers are used where there is a need to derive a large gain with narrow bandwidth. The frequency–impedance and frequency–current curves of series and parallel resonant circuits are shown, respectively, in Figures 13.1 and 13.2.
Tuned Amplifiers
I
Z R
I
645
I
+ V
L Z C fo
0
f
Figure 13.1 Series resonant circuit and its response
Z Z I I +
L
V
C R
I
0
fo
f
Figure 13.2 Parallel resonant circuit and its response
As the parallel resonant circuit offers large impedance at resonance, this is used as load to derive the largest possible gain in a single stage. At resonance, X L = X C or w o L = 1 w oC . Therefore, fo =
1
(13.1)
2p LC
Here fo is the resonant frequency of the tank circuit. Ideally, the requirement is that the response should be flat in a limited frequency range and should fall off rapidly as shown in Figure 13.3. Ideal response
A
Practical response
0
f1
fo
f2
f
Figure 13.3 Ideal and practical responses of tuned amplifiers
646
Electronic Devices and Circuits
But in practice, the practical response differs from the desired ideal response. We consider three types of tuned voltage amplifiers: (i) singletuned capacitance coupled voltage amplifier, (ii) synchronously tuned doubletuned voltage amplifier, and (iii) staggertuned voltage amplifier. A singletuned voltage amplifier is one in which there is only one tuned circuit, tuned to a desired resonant frequency. A synchronously tuned doubletuned amplifier is one in which there are two tuned circuits, and both the tuned circuits are tuned to the same center frequency. The response can be varied by adjusting the coupling between the coils. A staggertuned amplifier is one in which there are two tuned circuits. However, each of these tuned circuits is tuned to two different frequencies, and these two center frequencies are separated by bandwidth of a singletuned amplifier.
13.2
QUALITY FACTOR, Q OF L AND C
The response of a resonant circuit becomes sharp, that is, highly selective, or relatively flat depending on the value of Q, the figure merit of the tank circuit. Consider a practical inductance, L, as shown in Figure 13.4, in which R is the series resistance and CP is the distributed capacitance of the winding of the inductance. This tells that an inductance can have a selfresonant frequency. If the inductance is used below its selfresonant frequency, then CP, which usually is very small, can be omitted. R is normally specified by the manufacturer by specifying Q, the quality factor. The quality factor Q is defined as the ratio of the energy stored in the inductor in one cycle to the energy dissipated in one cycle. Q=
v wL Energy stored in one cycle = L = R Energy dissipated in one cycle vR
wL 2p × 10 × 106 × 10 × 10 −6 = = 6.28 Ω. Q 100 Thus, when L and R are in series, Q = wL R. If L and R are in parallel, then Q = R wL. If L = 10 µH , Q = 100 at f = 10 MHz, then R =
+ I
R vR − + L
R
L
vL −
(a) R and L in series
(b) R and L in parallel
Figure 13.4 A practical inductor
Alternatively, a practical capacitance may be represented as in Figure 13.5. For a capacitor C, to calculate the effective series resistance R, the dissipation factor, which is the reciprocal of Q is usually specified by the manufacturer. R 1 Energy dissipated in one cycle vR = = = wRC = vC 1 wC Q Energy stored in one cyclee
Tuned Amplifiers
647
The quality factor defined for a series and a parallel circuit is expressed in the following ways: 1 (for a series circuit) wRC
Q=
(13.2)
Q = wRC (for a parallel circuit)
(13.3)
Readers are advised to take special note of Eqs (13.2) and (13.3) that can normally create confusion. Q=
Energy stored in one cycle Energy dissipated in one cycle
(13.4)
However, there is no change in the original definition as expressed in Eqn. (13.4) from which the previous two equations have been obtained. + R vR − +
I
C
R
vC
C
− (a) C and R in series
(b) C and R in parallel
Figure 13.5 A practical capacitor
13.3
SINGLETUNED CAPACITIVECOUPLED VOLTAGE AMPLIFIER
A twostage singletuned amplifier, using transistors, is shown in Figure 13.6 in which a single stage is identified. Ri is the input resistance of the second stage. VCC L
L C
C R
R1
R
R1
Cc
Cc Q1
Cc
+
Q2 +
+ Vs
R2
Vo RE
−
CE
Vo2
R2 RE
− Single stage
Figure 13.6 A twostage singletuned amplifier
CE −
648
Electronic Devices and Circuits
A tuned amplifier is an RF amplifier. As such Cc and CE being large condensers, ideally behave as short circuits. R1 and R2 are large and can be replaced by open circuits. The ac circuit of a single stage is shown in Figure 13.7. The highfrequency equivalent circuit of Figure 13.7 is given in Figure 13.8. Using the Miller’s theorem, rb ′c and Cb ′c are replaced as shunt elements on the input and the output side. The resultant circuit is as shown in Figure 13.9.
Q1
+
L C
Vo
Ri
R + Vs
−
−
Figure 13.7 AC circuit of the singletuned amplifier
r b′c C
B′
B
+
+
r bb′
C b′e
r b′e
+
C b′c
V b′e Vs
Vo
L C
Ri
R
gce
gm V b′e
−
−
−
Figure 13.8 Equivalent circuit of Figure 13.7
B
B r bb′ Vs +
C + C wi
+ C b′e
r b′cA/(A−1)
= 1/hoe
C wo
Vo L
r b′e
C C b′c (1−A) r b′c/ (1−A)
−
gce
−
gm V b′e
R
Ri
C b′c (A−1)/A
−
Figure 13.9 Circuit of Figure 13.8, when Miller’s theorem is used
Tuned Amplifiers
649
To simplify the circuit, let Cs = Cb ′e + Cwi + Cb ′c (1 − A) and C′=
Cb ′c ( A − 1) A
+ Cwo + C
Also gce = 1 hoe = Ro and rb ′ c is considered as an open circuit. Then the circuit in Figure 13.9 reduces to that in Figure 13.10. B′
B
C +
r bb′
+ R
+
gm V b′e
V b′e
Vs
r b′e
L
Cs R o = 1/hoe
−
C′
Vo Ri
− −
Figure 13.10 Simplified circuit of Figure 13.9
To simplify the circuit further, let us replace the series combination of R and L as a parallel combination, as worked out in the following mathematical analysis: Z L = R + j wL YL =
YL =
1 1 R − j wL R − j wL = = = 2 ZL R + jwL (R − jwL ) (R + jwL ) R + w 2 L2
R − j wL R − j wL R wL = + = + R 2 + w 2 L2 R 2 + w 2 L2 R 2 + w 2 L2 R 2 + w 2 L2 j R 2 + w 2 L2
(
)
YL =
1 1 + Rp jwLp
(13.5)
Rp =
R 2 + w 2 L2 R
(13.6)
where
and Lp =
R 2 + w 2 L2 R2 = +L ≈L w 2L w 2L
(13.7)
650
Electronic Devices and Circuits
R2 > Rs . But from Figure 13.18, I = − gmVbe1. Consequently, we have V = IZ = − gmVbe1
R11 R M 1 + 11 R22 L1
2
(13.50)
2
(13.51)
Using Eqs (13.49) and (13.50), jwL1I1 = − gmVbe1
R11 R M 1 + 11 R22 L1
Hence,
Vbe1
2
R M 1 + 11 R22 L1 = − jwL1I1 gm R11
(13.52)
and (13.53)
Vbe2 = jwMI1 The gain A, therefore, is A=
Vbe 2 jwMI1 =− Vbe1 jwL1I1
gm R11 R M 1 + 11 R22 L1
2
=−
gm R11 (M L1 ) R M 1 + 11 R22 L1
2
(13.54)
The effective value of Q is Qe1 and is Qe1 =
Rp wL1
=
(R11
wL1 )
R M 1 + 11 R22 L1
2
(13.55)
and that at resonance is Qe1 =
(R11
w o L1 )
R M 1 + 11 R22 L1
2
(13.56)
Mutual impedance M controls Qe1 which in turn controls the bandwidth. By optimizing the value of M , the gain can be maximized. On the other hand, we interpret it as M can be used to control the bandwidth. To get the maximum value of A, we differentiate Eqn. (13.54), with respect to M and equate it to zero to get the optimum value of M . Then substitute this value of M in Eqn. (13.54).
660
Electronic Devices and Circuits
From Eqn. (13.54), A= −
gm R11 (M L1 ) R M 1 + 11 R22 L1
2
2 2M R dA R11 M − gm R11 M = 1 + gm R11 2 11 = 0 + dM R22 L1 L1 L1 L1 R22
R M 2 2M 2 R 11 − 1 + 11 + 2 =0 R22 L1 L1 R22 2
2
R M R M − 11 + 2 11 = 1 R22 L1 R22 L1 or 2
R11 M R L = 1 22
1
R M 2 = L12 22 R11 R22 R11
M o = L1
(13.57)
Substituting Eqn. (13.57) in Eqn. (13.54), A(max) =
gm R11R22 2
(13.58)
Substituting Eqn. (13.57) in Eqn. (13.56), R11 w o L1 1 R11 1 Qe1 = = = = Q1 2 2 2 w o L1 2 R M 1 + 11 R22 L1 R11 w o L1
(13.59)
where Q1 is the Q of the primary circuit. As the Q is halved the bandwidth increased by a factor 2. Thus, the main advantage of the tuned primary amplifier is that the bandwidth is twice the bandwidth of a singletuned amplifier. The capacitance C1 is normally made larger to neglect the effect of stray capacitances. The limitation is that the value of L1 becomes small.
Tuned Amplifiers
13.6
661
INDUCTIVELY COUPLED TUNED SECONDARY FET AMPLIFIER
An FET has a high input resistance. When FET is used as a frequency selective circuit, it is possible that for impedance matching, the tuned circuit is placed at the input of the amplifier that is in the secondary of the coupling network (Figure 13.21). The output from the previous stage is connected to the input of the FET amplifier. 1
I
M
I1 rd
2 I2
L2
L1
RL Vgs2
gmVgs1
C2
2
1
Figure 13.21 Tuned secondary FET amplifier
The equivalent circuit of Figure 13.21 is shown in Figure 13.22. I = −gmVgs1 L1 − M
1
L2 − M
R2 2
+
+
V11
rd
M
I2
C2 Vgs2
I1 −
− 2
1
Figure 13.22 Equivalent circuit of Figure 13.21
R2 is the resistance associated with L2. Writing the loop equations: V11 = jwL1I1 − jwMI 2 0 = R2 + At resonance w o L2 =
1 j wL2 − I 2 − jwMI1 wC2
1 . Substituting this condition in Eqn. (13.61), w oC2 0 = R2 I 2 − jw o MI1
(13.60) (13.61)
662
Electronic Devices and Circuits
Hence, I2 =
jw o MI1 R2
(13.62)
Substituting Eqn. (13.62) in Eqn. (13.60), jw MI w 2M 2 V11 = jw o L1I1 − jw oM o 1 = I1 jw o L1 + o R2 R2 Z11 =
(13.63)
w 2M 2 V11 = jw o L1 + o I1 R2
(13.64)
I1 flows through Z11. To find out the value of I1, consider the equivalent circuit in Figure 13.23. From Figure 13.23, I1 = I
rd rd + Z11
(13.65)
I = −gmVgs1 1
Using Eqn. (13.64), +
1 =I I1 = I 2 2 jw L w 2 M 2 w M 1+ o 1 + o rd + jw o L1 + o R2 rd rd R2 rd
(13.66)
V11
rd
Z11 I1
As the primary is untuned, rd >> w o L1, Eqn. (13.66) reduces to I1 = I But
1 w o2 M 2 1+ rd R2
−
(13.67)
1
Figure 13.23 Circuit to calculate I1
I = − gmVgs1
(13.68)
Substituting Eqn. (13.68) in Eqn. (13.67), I1 = I
1 1 = − gmVgs1 w o2 M 2 w o2 M 2 1+ 1+ rd R2 rd R2
(13.69)
Substituting Eqn. (13.69) in Eqn. (13.62), jw o MI1 jw o M 1 − gmVgs1 = I2 = R2 R2 w o2 M 2 1+ rd R2
(13.70)
Tuned Amplifiers
663
From Figure 13.22 and using Eqn. (13.70),
Vgs 2
−g w M −j − j jw oM 1 1 m o − gmVgs1 = = Vgs1 I2 = 2 2 w oC2 w oC2 R2 w o R2C2 w oM w o2M 2 1 + 1 + rd R2 rd R2
A=
Vgs 2 Vgs1
=
− gmw o M w o R2C2
1 w 2M 2 1+ o rd R2
(13.71)
But Q2 =
w L 1 = o 2 w o R2C2 R2
(13.72)
Using Eqn. (13.72), A=
− gmw o M w o R2C2
Q2 1 = − gmw o M 2 2 w M w 2M 2 1+ o 1+ o rd R2 rd R2
(13.73)
We may want to derive the maximum gain or a desired bandwidth. In either case, we are required to adjust M . To find A(max), we differentiate Eqn. (13.73), with respect to M and equate it to zero to get the optimum value of M . Then substitute this value of M in Eqn. (13.73) to get A(max). 2w o2 M dA w o2 M 2 = 1 + − g w Q g w MQ + =0 ( ) 2 m o 2 m o rd R2 dM rd R2 w 2M 2 2w o2M 2 − 1 + o + =0 rd R2 rd R2 w o2 M 2 =1 rd R2
w o M o = R2 rd
(13.74)
The optimum value of M is Mo =
R2 rd wo
(13.75)
664
Electronic Devices and Circuits
Substituting Eqn. (13.74) in Eqn. (13.73), A(max) = − gmw o M o
− gm rd R2 Q2 Q2 Q2 = − gm R2 rd = 2 2 Rr 2 w M 1+ 2 d 1+ o r R rd R2 d 2
(13.76)
Define the effective value of Q, that is Qe2 as follows: Qe 2 =
Q2 w 2M 2 1+ o rd R2
(13.77)
Substituting Eqn. (13.74) in Eqn. (13.77), Qe 2 =
Q2 Q = 2 rd R2 2 1+ rd R2
(13.78)
Bandwidth is fo f 2f = o = o Qe 2 Q2 2 Q2
(13.79)
From Eqn. (13.79) it can be noted that the bandwidth is twice the bandwidth of the resonant circuit. This result is similar to that in the tuned primary amplifier.
13.7
IMPEDANCE ADJUSTMENT WITH TAPPED CIRCUITS
A tuned circuit is shown in Figure 13.24, in which there is a tap on the inductor. The total inductance L is L = L1 + L2 ± 2M . Resistor Ri is the input resistance of the next stage. The parallel combination of ( L2 ± M ) and Ri is resolved into a series combination of ( L2 ± M ) and Rs as shown in Figure 13.25.
L1 ± M L1 ± M
C
C L2 ± M L2 ± M
Ri Rs
Figure 13.24 Tuned circuit, with a tap on the inductor
Figure 13.25 Circuit of Figure 13.24, with Ri replaced by Rs
Tuned Amplifiers
665
Here, we know that Rs is given by the following equation: 2
w 2 ( L2 ± M )
Rs =
(13.80)
Ri
Once again, the series resistance Rs can be replaced by a parallel resistance Rp as shown in Figure 13.26. Rp =
w 2 L2 Rs
(13.81) 1
Using Eqn. (13.80),
L1 ± M C
L2 w 2 L2 w 2 L2 Ri Rp = = = 2 Rs w 2 ( L2 ± M ) (L2 ± M )2 Ri
Rp
(13.82)
L2 ± M
1
We thus see that a resistance Ri at a tap on L can be replaced by a resistance Rp connected in shunt with the terminals 1–1 (Figure 13.26). Now consider the amplifier circuit in Figure 13.27.
Figure 13.26 Circuit of Figure 13.25, with Rs replaced by Rp
1
L1 L Q1
M
C
Rp
Q2
L2 1
Ri
Figure 13.27 Amplifier, with tapped inductance in the resonant circuit
Ri is a small input resistance appearing across the tuned circuit. Consequently, the Q of the circuit becomes smaller, and hence the bandwidth becomes larger than desired. When the input of Q2 is connected to a tapped tuned circuit, Ri gets transformed into Rp in parallel with the tank circuit. Rp is a large resistance, and hence the Q of the circuit becomes large;therefore, the bandwidth reduces to the desired value. In fact, Rp can be adjusted by adjusting the tap on the inductance. Hence, the Q of the tank circuit can be adjusted, which in turn controls the bandwidth. Alternately, Ri can be connected across a tapped capacitance to manipulate with the Q of the circuit, and hence can be used to derive the necessary bandwidth as shown in Figure 13.28.
666
Electronic Devices and Circuits 1 C1 L
Rp
Q1
Q2 C2
1 Ri
Figure 13.28 Amplifier, with tapped capacitance in the resonant circuit
When C and R are connected in parallel, they can be replaced by a series circuit (Figure 13.29). To find out the values of Rs and Cs , let us calculate YL of the parallel circuit. YL =
ZL =
ZL =
where Rs =
1 + jwRiC2 1 + j wC 2 = Ri Ri
Ri (1 − jwRiC2 ) Ri Ri jwRi2C2 = = − 1 + jwRiC2 (1 + jwRiC2 ) (1 − jwRiC2 ) 1 + (wRiC2 )2 1 + (wRiC2 )2
Ri 2
(wRiC2 ) 1
(wC2 )2 Ri
−
jwRi2C2 2
(wRiC2 )
=
1 2
(wC2 )
+ Ri
1 1 = Rs + j wC 2 j wC 2
and Cs = C2. The resultant tuned circuit of Figure 13.28 is shown in
Figure 13.29. Now replacing Rs by Rp, results in the circuit in Figure 13.30.
C1
L
C2
C1
Rp
L
C2
Rs
Figure 13.29 Tank circuit of Figure 13.28, with Rs in series with the capacitor combination
Figure 13.30 Tuned circuit of Figure 13.29, with Rs replaced by Rp
Tuned Amplifiers
Rp =
1
(wC )2 Rs
=
1 2
CC w 1 2 Rs C1 + C2 2
Rp
=
(C1 + C2 )2 1 wCC 2 (wC2 ) Ri 2
2 1
2 C1 + C2 ) ( R =
2 2
C12
2 C1 + C2 ) ( R =
C12
667
i
(13.83)
i
Thus, by adjusting the tap on C, Rp can be controlled, which in turn controls Q and hence the bandwidth.
13.8
DOUBLETUNED AMPLIFIERS
Doubletuned amplifiers are further classified as (i) synchronously tuned amplifiers and (ii) staggertuned amplifiers.
13.8.1 Synchronously Tuned DoubleTuned Amplifier A synchronously tuned doubletuned amplifier has two mutually coupled tuned circuits, and both the tuned circuits are tuned to the same center frequency. The resultant response of this amplifier is almost a near flat response in limited frequency range of interest. The doubletuned amplifier usually finds application in radiofrequency (RF) and intermediate frequency (IF) amplifiers in radio receivers. Before we actually take up the analysis of the doubletuned amplifier, let us first obtain the expression for transfer admittance that can be used subsequently.
Calculation of the Transfer Admittance Consider the twoport network shown in Figure 13.31. We can write the KVL equations pertaining to the input and output ports using the zparameters. I1
I2 +
+ V1
Network
V2
ZL
−
−
Figure 13.31 Twoport network
V1 = Zi I1 + Zr I 2
(13.84)
V2 = Zf I1 + Zo I 2
(13.85)
V2 = − I 2 ZL
(13.86)
From Figure 13.31,
668
Electronic Devices and Circuits
Substituting Eqn. (13.86) in Eqn. (13.85), − I 2 ZL = Zf I1 + Zo I 2 or −Zf I1 = (Zo + ZL ) I 2 or I1 = −
(Zo + ZL ) I Zf
(13.87)
2
Substituting Eqn. (13.87) in Eqn. (13.84), (Zo + ZL ) Zr Zf − Zi (Zo + ZL ) Zi (Zo + ZL ) V1 = Zi I1 + Zr I 2 = Zi − I 2 + Zr I 2 = I 2 Zr − = I2 Zf Zf Zf YT =
I2 Zf Zf = = V1 Zr Zf − Zi (Zo + ZL ) Zf2 − Zi (Zo + ZL )
since Zf = Zr . We can write for the transfer admittance YT as YT =
1 Z ( Z + ZL ) Zf − i o Zf
(13.88)
Analysis of Synchronously Tuned DoubleTuned Amplifier The circuit of a doubletuned amplifier is shown in Figure 13.32 and the ac circuit of a single stage in Figure 13.33. Resistance r1 is the output resistance of the first stage and r2 is the input resistance of the second stage. VCC
C1
L1
L2
R1
R2
C2
M
Q1 +
Q2
Vo + V1 −
Figure 13.32 Synchronously tuned doubletuned amplifier
Tuned Amplifiers
669
Resistances r1 and r2 that are parallel elements are replaced as series elements using the following relations: L2w 2 r1s = 1 o r1 r2s =
L22w o2 r2
Hence, the circuit in Figure 13.33 reduces to that in Figure 13.34 in which R11 = R1 + r1s and R22 = R2 + r2s . R1
R2
+ C1
r1
gmV1
L1
L2
Vo
r2
C2 M
Figure 13.33 AC circuit of Figure 13.32, for a single stage r1s
R1
gmV1
r2s
L1
C1
R2
+
L2
Vo
C2
M
Figure 13.34 Simplified circuit of Figure 13.33
If the current source in Figure 13.34 is replaced by a voltage source and the coupling network is replaced by the equivalent Tnetwork, then the circuit in Figure 13.34 reduces to that in Figure 13.35. R11
1
L1 − M
L2 − M
R22 2
+
C1
+
+ V11
jgmV1/wC1
M I1
Vo I2
C2
2 1
Figure 13.35 Equivalent circuit of Figure 13.34
670
Electronic Devices and Circuits
1 1 = and the Qs of the circuits are Q1 = w o L1 R11 and L1C1 L2C2 Q2 = w o L2 R22 . Normally, both the tuned circuits are chosen to have the same Q. Hence, The resonant frequency, w o2 =
Q1 = Q2 = Q. From Figure 13.35, Vo =
−j I2 w oC2
(13.89)
From the definition of transfer admittance, we haveYT = I 2 V11 or I 2 = YTV11 and V11 = jgmV1 w oC1 . Therefore, I 2 = YTV11 =
jgmV1 YT w oC1
(13.90)
Substituting Eqn. (13.90) in Eqn. (13.89), Vo =
gmVY −j − j jgmV1 1 T I2 = YT = w oC2 w oC2 w oC1 (w oC1 )(w oC2 )
(13.91)
But at resonance, w o L1 =
1 1 and w o L2 = w oC1 w oC2
(13.92)
Substituting Eqn. (13.92) in Eqn. (13.91), 2 Vo = gmVY 1 T w o L1w o L2 = g mVY 1 T w o L1 L2
or A = gmYTw o2 L1L2
(13.93)
To calculate A, we need to calculate YT. To calculate YT using Eqn. (13.88), we need to calculate Zf, Zi, and (Zo + ZL ). From Figure 13.35, Zf = jw o M = jw o k L1L2
(13.94)
1 Zi = R11 + j wL1 − wC1
(13.95)
1 Zo + ZL = R22 + j wL2 − wC2
(13.96)
From Eqn. (13.95), 1 Zi = R11 + j wL1 − = R11 1 + wC1
wL 1 j 1 − R11 wR11C1
(13.97)
Tuned Amplifiers
671
But we have Q1 = Q =
w o L1 1 = R11 w o R11C1
(13.98)
Using Eqn. (13.98), Eqn. (13.97) can be written as w wo Zi = R11 1 + jQ − w o w
(13.99)
From Eqn. (13.98), R11 =
w o L1 Q
(13.100)
Using Eqn. (13.100), w w o w o L1 w wo Zi = R11 1 + jQ − = − 1 + jQ Q wo w w o w
(13.101)
Also we have defined d as follows: w= or
w − wo w = −1 wo wo w = 1+ d wo
(13.102)
Using Eqn. (13.102), Zi =
w w o w o L1 w o L1 − 1 + jQ = Q Q w o w
Zi =
w o L1 [1 + j 2dQ ] Q
1 1 + jQ (1 + d ) − (1 + d ) (13.103)
Similarly, 1 w o L2 Zo + ZL = R22 + j wL2 − = [1 + j 2dQ ] wC2 Q
(13.104)
Using Eqs (13.94), (13.103), and (13.104), YT =
1 = Zi (Zo + ZL ) Zf − Zf
1
( jw k o
)
L1L2 −
w o L1 w o L2 Q [1 + j 2dQ ] Q [1 + j 2dQ ]
( jw k o
L1L2
)
672
YT =
Electronic Devices and Circuits
jw o kQ 2 L1L2
=
2
−w o2 k 2 L1L2Q 2 − w o2 L1L2 (1 + j 2dQ ) YT =
jw o kQ 2 L1L2
(
−w o2 k 2 L1L2Q 2 − w o2 L1L2 1 + j 4dQ − 4d 2Q 2
)
− kQ 2
(
(
 jw o L1L2 k 2Q 2 + 1 − j 4dQ − 4d 2Q 2
))
or YT =
− kQ 2
(
(
w o L1L2 4dQ − j 1 + k 2Q 2 − 4d 2Q 2
(13.105)
))
Therefore using Eqn. (13.105), A = gmw o2 L1L2YT =
A=
(− g
)
w o2 L1L2 kQ 2
m
(
(
w o L1L2 4dQ − j 1 + k 2Q 2 − 4d 2Q 2
− gmw o kQ 2 L1L2
(
4dQ − j 1 + k 2Q 2 − 4d 2Q 2
(13.106)
) kQ
A = gmw oQ L1L2
))
(
16d 2Q 2 + 1 + k 2Q 2 − 4d 2Q 2
2
(13.107)
)
The response of the doubletuned amplifier is plotted in Figure 13.36 with dQ as the independent variable versus A as a function of kQ. We see, from Figure 13.36, that as the value of kQ increases the response has two peaks. The frequency deviation d at which the gain peaks occur can d A be found out by maximizing the gain. For this, we equate to zero and get the value of d. Then dd d A substitute this value of d in the expression for A . From Eqn. (13.107), is obtained by simply dd 2 differentiating 16d 2Q 2 + 1 + k 2Q 2 − 4d 2Q 2 .
(
)
(
)
2 d 16d 2Q 2 + 1 + k 2Q 2 − 4d 2Q 2 = 0 dd
(
(
32dQ 2 + −16dQ 2 1 + k 2Q 2 − 4d 2Q 2
(
)) = 0
)
16dQ 2 − 16dQ 2 k 2Q 2 − 4d 2Q 2 = 0 or
(1 − k Q 2
2
)
+ 4d 2Q 2 = 0
(13.108)
Tuned Amplifiers
673
A kQ = 1
kQ = 2.5
0.5 kQ = 2
0.4 0.3 0.2 0.1 kQ = 0.2 −2.0
−1.5
−1.0
−0.5
0
0.5
kQ = 0.5 1.0
1.5
2.0 dQ
−dQ
Figure 13.36 Response of the synchronously tuned, doubletuned amplifier
From Eqn. (13.108), d1,2 = ±
1 k 2Q 2 − 1 2Q
(13.109)
The two gain peaks occur at frequencies f1 and f2, where 1 f1 = fo 1 − k 2Q 2 − 1 2Q
(13.110)
1 f 2 = fo 1 + k 2Q 2 − 1 2Q
(13.111)
and
When k 2Q 2 = 1, from Eqn. (13.109), d = 0 and from Eqn. (13.110) and from Eqn. (13.111), we see that the two frequencies are equal to fo. At kQ = 1, the response is similar to the response of a singletuned amplifier. This value of k = kc is called critical coupling. For kQ < 1, it is said to be the case of undercoupling and the gain is less than the maximum. At kQ > 1, there is overcoupling. There are two peaks in the output. The spacing between the two peaks depends on the value of k. When the requirement is a sufficient bandwidth, overcoupling is used in the amplifier to derive the doublepeaked response. The maximum amplitude of the gain occurs at d = 0 ( kQ = 1).
674
Electronic Devices and Circuits
From Eqn. (13.109), as the peaks occur at d 1,2 = ∓
Ap = gmw oQ L1L2
Ap = gmw oQ L1L2
1 k 2Q 2 − 1 , from Eqn. (13.107), 2Q kQ
2 2 k 2Q 2 − 1 2 2 2 2 k Q − 1 Q + + k Q − Q 16 1 4 2 2 4Q 4Q
kQ
gmw oQ L1L2
=
4 k 2Q 2 − 4 + 4
2
(13.112)
2
The minimum gain AC occurs at d = 0 and from Eqn. (13.107) and is given as follows: AC = gmw oQ L1L2
kQ
(13.113)
(1 + k Q ) 2
2
From Eqn. (13.113), AC = gmw oQ L1L2 Ap AC
2 kQ
(
2
2 1+ k Q
2
)
= Ap
2 kQ
(1 + k Q ) 2
2
(13.114)
is called ripple g , the variation of gain and is Ap AC
=g =
1 + k 2Q 2 2 kQ
(13.115)
From Eqn. (13.115), k 2Q 2 − 2 kQg + 1 = 0 or x 2 − 2 xg + 1 = 0, where x = kQ
x1,2 =
2g ± 4g 2 − 4 = g ± g 2 −1 2
Consequently, kQ = g ± g 2 − 1
(13.116)
In the overcoupled case, kQ > 1. Hence, choosing positive in Eqn. (13.116), kQ = g + g 2 − 1
(13.117)
From Eqn. (13.117), it can be noted that to get a desired ripple, kQ can be adjusted accordingly. The response of the overcoupled amplifier is shown in Figure 13.37. The difference in the two frequencies at which the gain has fallen to AC is the useful bandwidth of the amplifier.
Tuned Amplifiers
675
A
AP AC
δP δC
f1
0
f0
f2
f
Figure 13.37 Response of the overcoupled, doubletuned amplifier
Therefore, the bandwidth is 2d c = f2′ − f1′= 2 ( f2 − f1 )
(13.118)
But from Eqs (13.110) and (13.111), 1 f1 = fo 1 − k 2Q 2 − 1 2Q 1 f 2 = fo 1 + k 2Q 2 − 1 2Q Therefore, f2 − f1 =
fo k 2Q 2 − 1 Q
(13.119)
For a 3 dB change between the d c frequencies, the value of g = 2. From Eqn. (13.117), kQ = g + g 2 − 1 = 2 + 2 − 1 = 2.414. Therefore, from Eqn. (13.119), f2 − f1 =
fo Q
(2.414)2 − 1
(13.120)
From Eqn. (13.118), the bandwidth is as follows:
2 ( f2 − f1 ) =
fo 2 Q
(2.414)2 − 1 =
3.1 fo Q
(13.121)
676
Electronic Devices and Circuits
1
1 4 The bandwidth of nstage doubletuned amplifier is given as BW1 2 n − 1 . The bandwidth of either tuned primary or tuned secondary has a bandwidth of 2 fo Q , whereas the bandwidth of the doubletuned amplifier is 3.1 fo Q, which is much larger. Also the response falls off very rapidly known as the steep skirt region, giving a near ideal response characteristic.
13.8.2 StaggerTuned Amplifier A staggertuned amplifier has two tuned circuits. But these are tuned to two resonant frequencies that are separated by the bandwidth of a singletuned amplifier. The resultant response of this cascaded amplifier is somewhat similar to the response of a doubletuned amplifier. As the resonant frequencies are separated or staggered, this amplifier is called a staggertuned amplifier. The circuit of staggertuned amplifier is shown in Figure 13.38. The responses of the individual tuned circuits and the resultant response of the stagger tuned amplifier are shown in Figure 13.39. The resultant staggertuned amplifier will have 2 times the bandwidth of the singletuned amplifiers. The relative response of a singletuned amplifier is given by Eqn. (13.21) and its magnitude by Eqn. (13.22) as follows: A 1 1 = = Ar 1 + j 2dQe 1 + jX where X = 2dQe. When X = 1,
A 1 1 = = . When 2dQe = 1, 2 Ar 2 1 + (2dQe ) Qe =
1 2d
(13.122) VCC
Tuned circuit I C 1
L1
C2
L2
Q2
Q1 CC
Tuned circuit II
+ Vo
+ V1 − −
Figure 13.38 Staggertuned amplifier
Tuned Amplifiers
677
Resultant response
A Ar
1 Tuned circuit I
Tuned circuit II
0 fa
−dQe
+dQe
BW
Figure 13.39 Response of the staggertuned amplifier
The bandwidth of a singletuned amplifier is given as follows: BW =
fo = 2dfo Qe
(13.123)
Stage I is tuned to a frequency d o fo below fo and the second tuned circuit is tuned to a frequency d o fo above fo. Hence, the relative gains these two tuned circuits are given as follows: A 1 A = 1 + j (X − 1) r 1
(13.124)
A 1 A = 1 + j (X + 1) r 2
(13.125)
and
The overall gain of the amplifier is A A A 1 1 A = A A = 1 + j ( X − 1) 1 + j ( X + 1) r p r 1 r 2 A 1 1 1 A = 1 + j (X − 1) 1 + j (X + 1) = 1 + 2 jX − X 2 + 1 = 2 − X 2 + j 2X r p
(
A A r
= p
1
(
2−X
)
2 2
+ (2X )
2
=
1
)
(13.126)
4+X4
But X = 2d oQ . Therefore, A A r
= p
1 4 + (2d oQ )
4
=
1 1 2 1 + 4Q 4d 4 o
(13.127)
678
Electronic Devices and Circuits
where d o is the value of d at w o and Q is the value of Qe for each of these circuits referred to w o. At the halfpower point 4Q 4d o4 = 1 or d o = 1
2Q. Hence, the bandwidth of staggertuned amplifier
is 2 times the bandwidth of a singletuned amplifier. In addition, the response is relatively flat in the desired frequency band and falls off rapidly.
13.9
INSTABILITY IN TUNED AMPLIFIERS
At high frequencies, noise and random variations may drive the tuned amplifier into generating oscillations. Also it is possible that the feedback produced through the collector to base interelectrode capacitance can produce positive feedback at certain frequencies which can drive the amplifier into generating oscillations. Thus, the amplifier becomes unstable. This means that the amplifier no longer behaves as an amplifier as is expected but behaves as an oscillator. This problem of instability in a tuned amplifier can be eliminated by using the following methods of stabilization: (i) unilateralization, (ii) mismatching, and (iii) neutralization.
13.9.1 Unilateralization An amplifier is supposed to be a unilateral network. This means that the input is transmitted to the output through the active device. However, no output is transmitted to the input terminals through the active device. But at high frequencies, Cb ′c (the interelectrode capacitance between the base and the collector), though is small, can offer relatively small reactance that it is possible for the output to be transmitted through Cb ′c to the input. This can cause oscillations to develop under proper circuit conditions, with the result that the tuned amplifier may not behave as an amplifier but can behave as an oscillator as depicted in Figure 13.40. r b′c B′ + C b′c r b′e
C b′e
L
V b′e
C gmV b′e
R
−
Figure 13.40 Feedback from the output to the input through Cb′c at high frequencies
Using the Miller’s theorem, Cb ′c and rb ′c can be replaced by Miller capacitance CMi and conductance in shunt with the input terminals (Figure 13.41). CMi = Cb ′c (1 − A). Since A is large and negative, CMi is reasonably large and at high frequencies its reactance tends to become small. The net effect is that the Miller capacitance and conductance reduce the input impedance, which in turn reduces the input signal. Thus, the gain of the amplifier is reduced, and hence the amplifier becomes stable.
Tuned Amplifiers
679
+ V b′e
gmV b′e C b′e
L C
C Mi
R −
Figure 13.41 Replacing Cb′c by CMi , using the Miller’s theorem
13.9.2 Mismatching Technique The load impedance of an untuned amplifier is usually small. Hence, there will be a large current flowing through the load. As feedback is provided through Cb ′c and rb ′c , the feedback current is relatively smaller. But a tuned amplifier is required to have a reasonably large Q so as to get a narrow band response. Hence, the tank circuit presents high impedance. To derive optimum response, transformer coupling is used for impedance matching. If instability is to be avoided, sometimes mismatch is desirable so as to reduce the gain of the amplifier. Thus, unilateralization and mismatching methods try to control the gain to eliminate instability. VCC
13.9.3 Neutralization Neutralization is a method that reduces the possibility of generating oscillations in a tuned amplifier and thus improves its stability. If a feedback signal is derived through Cb ′c , so as to develop oscillations, in this method, an equal and opposite signal is derived and is added to the feedback signal at the input so that the net feedback component is reduced to zero. Thus, the stability of the amplifier improves. Although there are many methods by which this requirement is implemented, essentially we consider here three methods of neutralization: (i) Hazeltine neutralization, (ii) neutradyne neutralization, and (iii) Rice neutralization. Figure 13.42 shows an RF amplifier without neutralization.
C b′c C1 Q
M
+
Vs RE
CE
−
Figure 13.42 Tuned RF amplifier VCC C b′c
Hazeltine Neutralization The feedback signal that can be responsible for driving the amplifier into generating oscillations and thus can cause instability is derived through Cb ′c . The characteristic of a centertapped winding of a transformer is that it is possible to derive signals of equal magnitude but of opposite phase. In Hazeltine method of neutralization, a signal of equal magnitude to that derived through Cb ′c but of opposite polarity is derived through CN , using the centertapped primary of the tuned circuit and this signal is added at the input to the feedback signal so as to nullify the effect of feedback and thus ensure stability of the tuned amplifier (Figure 13.43).
L2 L1
C1 Q
L2 L1 M
+ CN Vs RE
CE
−
Figure 13.43 Hazeltine nuetralization
680
Electronic Devices and Circuits
Neutrodyne Neutralization In neutrodyne neutralization, the neutralizing capacitance, CN is connected from the coil connected to the base end of the next stage to the base of the first stage as indicated in Figure 13.44. Incidentally, a neutradyne receiver is a kind of tuned RF radio receiver. VCC C b′c L2
C1
L1
Q1
Q2
M
+ CN Vs RE
CE
−
Figure 13.44 Neutradyne neutralization
Rice Neutralization In this method, a tuned circuit is provided on the input side with a centertap on the secondary. One end of this winding (marked X) is connected to the base of Q. The output taken from the lower end of the centertapped transformer on the output side is connected through CN to the other end of the centertapped transformer (marked Y) on the input side. The feedback signal (through Cb ′c ) and the neutralizing signal (through CN ) connected to both ends of the centertapped secondary coil on the input side are equal in magnitude and are opposite in polarity (Figure 13.45). VCC C b′c C1 + Vs −
Q
X
L2 L1 M
Ci Y
CN RE
CE
Figure 13.45 Rice neutralization
13.10 TUNED POWER AMPLIFIERS The transmitting power of a radio station is very large, of the order of few tens to hundreds of kW. Hence, the signal power is required to be raised to the desired value. A classB power amplifier is one in which the output load current flows for exactly one half of the time period of an input sinusoidal signal. A classC power amplifier is one in which the output load current flows
Tuned Amplifiers
681
for less than one half of the time period of the input sinusoidal signal. The input voltage and the output current waveforms of classB and classC amplifiers are shown in Figures 13.46 and 13.47, respectively. From Figure 13.46, it can be noted that the output current flows exactly for 180° in classB operation and for less than 180° in classC operation. The duration, in terms of angle, for which there is current flow through the load is called the angle of conduction. Obviously, it can be noted from Figure 13.46 that even though the device conducts for exactly one half of the input cycle period, by using a push–pull configuration, output can be derived for the entire input cycle period in a classB push–pull amplifier. Hence, a classB amplifier can be used for audio frequency applications. However, from Figure 13.47, it can be noted that the output is highly distorted. As such, a classC amplifier cannot be used for audio applications, where there is need for high fidelity. Both classB and classC amplifiers can be used in highpower, highfrequency applications, like in radio transmitters. The outputs of classB and classC amplifiers contain a number of frequency components in addition to the fundamental component. The signal of interest could be an amplitude modulated signal, transmitted from an AM transmitter. To transmit the carrier and the two sidebands, a narrow band tuned amplifier that has the required bandwidth, is used which is tuned to the carrier frequency. A tuned amplifier may be either a tuned classB or a tuned classC power amplifier. However, as the efficiency of a classC amplifier is large, classC amplifiers are preferred over classB amplifiers, for highpower applications. As the output of a classC amplifier can also have the harmonics of the fundamental component, sometimes a tuned circuit may be used that is tuned to any desired harmonic component. Such a classC amplifier is called a harmonic generator. Primarily, we discuss about a classC tuned power amplifier.
Input voltage 0 vs
Output current ic
p
0 p
2p
2p
3p
3p
4p
4p
Input voltage vs 0
Output current ic
p
3p
4p
0 qC
Figure 13.46 Input voltage and the output current of classB power amplifier
2p
qC
Figure 13.47 Input voltage and the output current of classC power amplifier
13.11 TUNED CLASSC POWER AMPLIFIER Figure 13.48 shows a classC amplifier with resistive load. Under classC operation, the base– emitter diode is reverse biased by a negative VBB source. This voltage controls the angle of conduction. This −VBB source is connected through a radiofrequency choke (RFC). This RFC offers high impedance to RF input signals, and thereby eliminates the possibility of these RF signals getting shorted at the input through the battery.
682
Electronic Devices and Circuits
VCC
ic I P = I C(sat)
ic RL
t
qC vi VP VC 0
Q
vi t
qC
RFC VBB
Figure 13.48 ClassC amplifier with resistive load
For the transistor to conduct, the minimum input voltage, VC will have to be at least just sufficient enough to overcome the reverse bias voltage VBB and the VBE of 0.7 V. Therefore, VC = VBB + 0.7. As long as vi is less than VC , Q is OFF, and there is no load current. When vi = VC, Q conducts for a duration q C and again when the input falls below VC the load current becomes zero. Thus, the output is in the form of pulses. It is now obvious that larger the value of VC the shorter is the duration of conduction of Q and vice versa. Thus, q C is controlled by VBB. VP is chosen such that at this value of input, Q is driven into saturation. Thus, I P corresponds to I C ( sat ). At high frequencies, the sinusoidal input can be approximated to a triangular wave to calculate q C. Hence, from Figure 13.49, VP V V q q V cos C = C or C = cos −1 C . Therefore, q C = 2 cos −1 C . 2 VP 2 VP VP
VC
0
0 (ii) If VC = 0, then q C = 2 cos = 180°. This Vp
p qC qC 2 2
V (i) If VC = Vp, then q C = 2 cos −1 C = 0 Vp
qC
Figure 13.49 Calculation of qc
−1
VCC
condition corresponds to classB operation. L
C
For classC operation, 0 ≤ q C ≤ 180°. But usually a classC amplifier is not used with resistive load but with tuned circuit as load to select a desired frequency band of signal as in AM transmitters, which consists of the carrier and the two side bands as shown in Figure 13.50. The LC parallel tuned circuit is tuned to the carrier frequency, fc =
1 2p LC
Q RFC vi
VBB
Figure 13.50 Tuned classC amplifier
Tuned Amplifiers
683
The pulsed waveform at the output of the classC amplifier can be resolved into its frequency spectrum by using Fourier series. The amplitude of the fundamental frequency component of a classC amplifier depends on the angle of conduction, q C. The larger is the value of q C, the larger is the amplitude of the fundamental component in the output. Let r1 be the ratio of the fundamental component to the peak amplitude of the classC waveform. It is seen that to a close approximation r1 is given as r1 =
B1 = −3.54 + 4.1q C − 0.0072q C2 × 10 −3 IP
(
)
(13.128)
where, 0 ≤ q C ≤ 180° and B1 is the fundamental component of current. For q C = 0, r1 ≈ 0. For q C = 180°, r1 = 0.5. Thus r1 varies from 0 to 0.5 as q C varies from 0° to 180°. Similarly, let ro be the ratio of the dc component to the peak value of the classC waveform. ro can be evaluated from the relation: ro =
Bo qC dc component of current = = I P Peak amplitude of the classC output p (180°)
(13.129)
where Bo is the dc component of current. As q C varies from 0° to 180°, ro varies from 0 to 1 . For most of the input cycle period, Q is OFF and conducts only for a small duration q C. p Hence the amount of dissipation in the device can be very small. As a result the efficiency of a classC amplifier can be large. The maximum output power (when Vm = VCC) at the fundamental frequency is P1 =
B1 2
×
Vm 2
=
r1I p 2
×
VCC 2
=
( )
VCC r1I p 2
(13.130)
The total dc input power
( )
PBB = BoVCC = r0 I p VCC
h=
(13.131)
P1 × 100% PBB
From Eqs (13.130) and (13.131),
( )
VCC r1I p
r 2 h= × 100% = 1 × 50% ro VCC ro I p
( )
(13.132)
Example 13.1 A classC amplifier has a bias voltage of –5.3 V and a supply voltage VCC = 25 V. It is found that a peak input voltage of 10 V at 1 MHz is required to drive the transistor into saturation, with IC(sat) = 2 A. Find (i) the angle of conduction, q C, (ii) the power due to the fundamental component, P1 at 1 MHz, (iii) the efficiency of the power amplifier, h, (iv) the value of L of the tank circuit if C = 100 pF.
684
Electronic Devices and Circuits
Solution: (i) The voltage VC at which the transistor conducts is VC = VBB + 0.7 = 5.3 + 0.7 = 6 V. V 6 qC = 2cos −1 C = 2cos −1 = 2 × 53.13 = 106.26° 10 VP 2 (ii) r1 = −3.54 + 4.1(106.26 ) − 0.0072 (106.26 ) × 10 −3 = 0.351
B1 = r1I P = r1I C(sat) = 0.351 × 2 = 0.702 A P1 = (iii) ro =
B1
×
VCC
2
2
0.702 × 25 = 8.775 W 2
qC 106.26 = = 0.188 p (180°) p × 180 h = 50 ×
(iv) L =
=
1
1
=
2
r1 0.351 = 50 × = 93.35% 0.188 ro
6 2
(2pfo ) C (2p × 1 × 10 )
= 0.25 mH
× 100 × 10 −12
Example 13.2 For a tuned classC amplifier shown in Figure 13.51, calculate (i) the output power when Vpp = 30 V, (ii) maximum ac output power, (iii) dc input power if the current drain from the battery is 5 mA, (iv) efficiency when Vpp = 30 V, (v) bandwidth if Q = 100, and (vi) maximum dissipation in the transistor. 2VCC Vo
VCC = 25 V
VCC
t
VPP = 30 V
L = 1 µH
C = 100 pF
0
Q +
Cc
2VCC
+
RFC vi
VBB
Vo −
RL = 1
Vo VCC
− 0
Figure 13.51 Tuned classC amplifier with waveforms
VPP = 2VCC = 50 V t
Tuned Amplifiers
685
Solution: (i) ∴
Po =
2 Vrms RL
Po =
V (30) = 112.5 mW = 8RL 8 × 1 × 103
Vpp = 2 2 Vrms or Vrms =
VPP 2 2
2
2 PP
(ii) Maximum ac output power is obtained when the output voltage swing is 2VCC. That is, VPP = 2VCC = 50 V. Po(max ) =
∴
(2VCC )2
=
8RL
(50)2 8 × 1 × 103
= 312.5 mW
(iii) Dc input power, PBB = VCCIdc = 25 × 5 = 125 mW Po 112.5 × 100 = 90% ×100 = PBB 125
(iv) Efficiency, h = (v) fo =
1 2p LC
=
1 −6
2p 1 × 10 × 100 × 10 −12
= 15.92 MHz
fo 15.92 = = 159.2 kHz Q 100 (vi) Maximum power dissipation in the transistor (also sometimes called as the worst case Po(max ) power dissipation) is . 5 Bandwidth =
Therefore,
PD(max )
2 2VCC ) ( =
40Rt
where Rt = Rp//RL We have, Q =
RP wo L
or RP = w o LQ = 2π × 15.92 ×106 × 1 × 10 −6 × 100 = 10 kΩ Hence,
Rt =
1 × 10 = 0.91 kΩ 1 + 10 PD(max ) =
(50)2 40 × 0.91
= 68.68 mW
13.11.1 Applications of Class C Tuned Amplifiers Two main applications of tuned Class C amplifier are considered here. One application is as an amplitude modulator and the other application is as a harmonic generator.
686
Electronic Devices and Circuits
Class C Tuned Amplifier as an Amplitude Modulator A Class C tuned amplifier can be used for transmitting an Amplitude Modulated (AM) signal from an AM radio station. Modulation is a process by which one of the parameters of a high frequency signal, (called the carrier), namely the amplitude, frequency or the phase, is varied in accordance with the instantaneous amplitude of the low frequency signal, (called the intelligence or the modulating signal to be transmitted from the radio station). If the amplitude of the carrier is varied in accordance with the instantaneous amplitude of the low frequency signal, then the type of modulation is called amplitude modulation. Similarly, if the frequency of the carrier is varied, then the type modulation is called frequency modulation and if the phase of the carrier is varied then the type of modulation is called phase modulation. Let the carrier vary as ec = Ec sinw c t and let the modulating signal vary as em = E m sinw m t. Then the amplitude of the carrier varies as A = ( Ec + em ) = ( Ec + E m sinw m t ) and the frequency of the carrier remains unaltered. Therefore, the amplitude modulated signal varies as A sinw c t . If the amplitude modulated signal is called e(t ), then E e(t ) = A sin w c t = ( Ec + E m sin w m t ) sin w c t = Ec 1 + m sin w m t sin w c t Ec e(t ) = Ec (1 + ma sin w mt ) sin w ct In other way, this can also be expressed as, e(t ) = Ec sin w c t +
ma Ec cos (w c − w m ) − cos (w c + w m ) 2
(13.133)
where, ma = E m Ec , is called the depth of modulation. w m, actually is not a single frequency but is a band of frequencies. (w c − w m ) is called the lower sideband (LSB) and (w c + w m ) is called the upper sideband (USB). In commercial broadcasting, the carrier is also transmitted so as to get back the signal in the receiver by a process called demodulation. A Class C amplifier used as an amplitude modulator is shown in Figure 13.52 and the waveforms in Figure 13.53. VCC
em 0
em = E msin w mt signal
L
Q
t
C e(t) A M s i gn a l
e ( t) Ec
ec = E csin w ct carrier
RFC VBB
0
t
ec
Figure 13.52 ClassC amplitude modulator
Figure 13.53 Waveforms
Tuned Amplifiers
687
The modulating signal is connected at the collector through transformer coupling. The voltage at the collector is, therefore, the sum of VCC and vm. As vm varies, the voltage at the collector also varies. The carrier is applied at the base. When the transistor is driven into saturation, the peak amplitude of the collector current I c ( sat) depends on the voltage at the collector. As the amplitude of vm changes from time to time so does the peak collector current. The result is that the output signal is an amplitude modulated wave. ClassC output 0
qC
t
Fundamental fs component in the output 0 t
Second harmonic in the output
2fs 0
Third harmonic 3fs in the 0 output
t
t
Figure 13.54 The output of a class C amplifier and frequencies in the output
Tuned ClassC Amplifier as a Harmonic Generator The output of a ClassC amplifier consists of the fundamental frequency component, fs and many higher order harmonics, nfs , where n = 1, 2, 3, ... Figure 13.54. The tuned circuit is tuned to the desired harmonic frequency. Then this amplifier is called harmonic generator.
13.12 WIDEBAND OR COMPENSATED AMPLIFIER V
CC In television receivers, it becomes necessary that the amplifier has bandwidth of the order of 4.5 MHz. But, when a transistor is used as an active element in a high frequency amplifier, L the Miller effect capacitor at the input, CMi reduces the input impedance of the amplifier and consequently the high frequency Q gain of the amplifier is reduced. This results in a decreased + bandwidth. In such a case it may not be possible to get a desired Cd + bandwidth of the order of 4.5 MHz. One method to derive V be1 Vbe2 this bandwidth, in such a case, is to reduce the gain. However, if the requirement is not to sacrifice the gain but at the same − − time obtain the desired bandwidth, then there arises the need to provide frequency compensation circuits which ensure that Figure 13.55 Shunt compensated the gain is maintained constant up to the desired frequency. wideband amplifier
688
Electronic Devices and Circuits
Such amplifiers are called wideband amplifiers or compen+ sated amplifiers. Wideband amplifiers include an inductance Cd in the load, which can appear either in series or in shunt with hie Vbe2 L the input capacitance of the next stage. The resonant frequency and the Q of the tank circuit are appropriately cho gmVbe1 − sen so that the gain remains constant up to the frequency of interest. If the inductance is included in series with the input Figure 13.56 Equivalent circuit capacitance (Cd is Miller capacitance, CMi plus other capacitances) of the next stage, the type of compensation is called series compensation and the wideband amplifier is called a series compensated wideband amplifier. If alternately, the inductance is placed in shunt with the input capacitance of the next stage, the resultant compensation is called shunt compensation and the amplifier is called the shunt compensated (or shuntpeaked) wideband amplifier. To understand the principle of a wideband amplifier, we consider a shunt compensated wideband amplifier shown in Figure 13.55. The equivalent circuit is shown in Figure 13.56. hie in shunt with L can be replaced by R in series with L as shown in Figure 13.57. +
R + Cd Vbe2
≡
L gmVbe1
gmVbe1(s)
Vbe2(s)
Z(s) −
−
Figure 13.57 Circuit of Figure 13.56, with hie and L replaced by R and L
From Figure 13.57, using Laplace transforms Y ( s ) = sCd +
1 R + Ls
(13.134)
and Z(s) =
1 1 sCd + R + Ls
(13.135)
Our interest is to consider the influence of the compensating inductance, L on the gain of the amplifier. When the compensating inductance is not included, that is, L = 0, from Figure 13.57, the upper halfpower frequency is w 2 and is given as follows: w2 =
1 RCd
(13.136)
To show that there is improvement in bandwidth with compensation, we use w 2 as the reference. From the tuned circuit in Figure 13.56, w o2 =
1 LCd
(13.137)
Tuned Amplifiers
689
We have, Vbe 2 ( s ) = − gmVbe1 ( s )Z ( s )
(13.138)
Therefore, Vbe 2 ( s ) = − gm Z ( s ) Vbe1 ( s )
(13.139)
R + Ls R + Ls = 1 + sCd (R + Ls ) LCd s 2 + RCd s + 1
(13.140)
Ah ( s ) = From Eqn. (13.135), 1
Z(s) =
=
1 R + Ls Dividing the numerator and the denominator by L and using Eqn. (13.137), sCd +
R R R s+ s+ L L L = = Z(s) = RCd 1 R 2 R 1 Cd s + s+ Cd s 2 + s + w o2 Cd s 2 + s + L L L L LCd s+
(13.141)
From Eqs (13.139) and (13.141), R s+ − gm L Ah ( s ) = − gm Z ( s ) = Cd 2 R 2 s + s + w o L
(13.142)
The expression for Ah ( s ) has a zero at s = −R L and two poles. To get the location of the two poles, we equate the denominator to zero. s2 +
R s + w o2 = 0 L
(13.143)
The two roots are as follows: 2
− s1,2 =
R R ± − 4w o2 2 L L −R R = ± − w o2 2L 2 2L
(13.144)
2
R When w o2 = , the term under the square root becomes zero and both the poles are real and 2 L −R appear at . With this condition, the gain can be optimized. With L large conjugate poles are 2 L present. Using the condition 2
R2 R = 2 w o2 = 2L 4L
(13.145)
690
Electronic Devices and Circuits
From Eqs (13.137) and (13.145), R2 1 = 2 LCd 4 L or L=
R 2Cd 4
This value of L is called the critical inductance, Lcritical : Lcritical =
R 2Cd 4
(13.146)
With conjugate poles, we have a raise in gain at w = w o, for the resonant load amplifier. The raise in gain can be controlled by Q, referenced to w 2. Q=
w2 L R
(13.147)
From Eqs (13.136) and (13.147), Q=
1 L L × = 2 RCd R R Cd
Dividing both numerator and denominator by 4 and using Eqn. (13.146), L L L Q = 2 = 24 = R Cd R Cd 4 Lcritical 4
(13.148)
From Eqn. (13.140), we have Z(s) =
R + Ls LCd s 2 + RCd s + 1
Substituting s = jw, in the above equation, we have Z=
R + j wL
(1 − w LC ) + jwRC
(13.149)
2
d
d
We have Vbe 2 = − gmVbe1Z . Therefore, using Eqn. (13.149), Ah = − gm Z = − gm ×
R + j wL
(1 − w LC ) + jwRC 2
d
d
Hence, 2
R 2 + (wL )
2
Ah = gm ×
(1 − w
2
) + (wRC ) 2
LCd
2
d
wL 1+ R = gm R × 1 + w 4 L2Cd2 − 2w 2 LCd + w 2 R 2Cd2
Tuned Amplifiers
wL 1+ R
Ah = Am
Ah Am
2
2L 1 + w 4 L2Cd2 + w 2 R 2Cd2 1 − 2 R Cd wL w 2 1+ R w 2
=
691
2
(13.150)
2L 1 + w L C + w R C 1 − 2 R Cd 4
2
2 d
2
2
2 d
Using Eqs (13.136), (13.137), and (13.147), in Eqn. (13.150) can be written as follows:
Ah
=
Am
w 1 + Q2 w2
2
(13.151)
2
w 4 w 2w L 1 + 4 + 1 − 2 R wo w2
From Eqs (13.137) and (13.136), w o2 =
1 1 R 1 R R = × = × = w2 × LCd LCd R RCd L L w o4 = w 22 ×
R2 L2
Hence, w 4 w 4 L2 = w o4 w 22 R 2
(13.152)
Substituting Eqn. (13.152) in Eqn. (13.151), w 1+ Q w2
2
w 1+ Q w2
2
Ah Am
=
2
2
2
w 4 L2 w 2w L 1 + 2 2 + 1 − 2 R w2 R w2
=
2
w 4 w 2 L2 w 2w L 1 + 4 2 2 + 1 − 2 R w2 R w2
Using Eqn. (13.147),
Ah Am
=
w 1 + Q2 w2 2
2
4
w w 1 + (1 − 2Q ) + Q 2 w2 w2
(13.153)
692
Electronic Devices and Circuits
In the highfrequency range, because of Miller effect, as the gain is likely to fall, shunt compensation is provided to keep the response flat and thus improve the bandwidth. Consider the function H (w ) =
1 + a1w 2 + a2w 4 + ... 1 + b1w 2 + b2w 4 + ...
(13.154)
Mathematically, it is shown that a function of the form shown in Eqn. (13.154) can be made to have the flattest response by equating the coefficients of the equivalent powers of the variable in the numerator and the denominator. That is, the response in the desired frequency range tends to be flat if a1 = b1, a2 = b2, and so on. 2
w Equating the coefficients of in Eqn. (13.153), w2 Q 2 = 1 − 2Q or Q 2 + 2Q − 1 = 0
(13.155)
Therefore, Q=
−2 ± 4 + 4 = −1 ± 2 = −2.414 or 0.414 2
Q is taken as 0.414, since Q cannot have a negative value. From Eqn. (13.148), Q=
L 4 Lcritical
From this, L = 4QLcritical = 4 × 0.414 × Lcritical = 1.656 Lcritical
(13.156)
Choosing L using Eqn. (13.156) will give a flat response in the frequency range of interest. The relative response of the shunt compensated wideband amplifier is plotted as a function of f f2 , for Q varying from 0 (uncompensated amplifier) to 1, Figure 13.58. It can be noted that the bandwidth of the compensated amplifier is 1.72 times the bandwidth of the uncompensated amplifier, for Q = 0.414 . As Q increases, there is no appreciable improvement in bandwidth. The response tends to be peaky, which is not the desired response. Thus, it can be noted that by providing a compensating inductance L, chosen as 1.656 times Lcritical , the response of the amplifier can be made flat for Q = 0.414 . The resultant bandwidth of the compensated amplifier is 1.72 times the bandwidth of the uncompensated amplifier. Because of the
Tuned Amplifiers Relative gain magnitude
693
Q=1
1
Q = 0.8 0.707 Q = 0.5 Q = 0.414 Q=0 0
1
f f2
1.72 f2′ f2
Figure 13.58 Relative response of shunt compensated wideband amplifier
small input resistance of a CB configuration, the Miller effect capacitance will have negligible say on the input impedance. Hence, a cascode amplifier is preferred for highfrequency applications.
Additional Solved Examples Example 13.3 In a capacitivecoupled singletuned amplifier circuit, the bandwidth is 5 kHz and the voltage gain has the maximum value at 1000 kHz when the tuning capacitor is adjusted to 500 pF. Calculate (i) the inductance of the coil and (ii) the Q of the circuit. Solution: (i)
fo =
1 2p LC
(ii) BW =
fo Qe
L=
1 1 = 2 4p Cfo 40 × 500 × 10 −12 1 × 106
Qe =
fo 1000 = = 200 BW 5
2
(
Example 13.4 For the parallel resonant circuit shown in Figure 13.59, R = 100 Ω , L = 50 mH and C = 0.005 µF. Find (i) the resonant frequency considering R, (ii) the resonant frequency neglecting R, (iii) Q of the inductor, and (iv) the bandwidth of the circuit.
2
)
= 0.05 mH
Is
+
L C R
V
s Solution: At resonance, the reactive component of the RL branch current, iL is equal to the reactive component of the capacitive Figure 13.59 Parallel resonant circuit branch current, iC.
694
Electronic Devices and Circuits
Reactive component of the RL branch current, Vs wo L w o LVs iL = × = 2 2 2 2 2 2 R + (w o L ) R + (w o L ) R + (w o L ) Reactive component of the capacitive branch current, iC = w oCVs w o LVs 2
R 2 + (w o L )
= w oCVs
2
R 2 + (w o L ) =
⇒ fo =
(i) fo =
1 2p
1 1 R2 − 2 = 2p LC L
fo =
1 R2 − 2 LC L
R2 1  2 LC L
1 1002 − −6 50 × 10 × 0.005 × 10 50 × 10 −3 −3
1
(
2
)
1 = 3
2p 50 ´ 10 ´ 0.005 ´ 10 6
2p LC
4000 = 10.071 kHz 2p
=
(iii) Q of the inductor at resonance = (iv) Bandwidth =
wo2 =
4000 − 4 = 10.066 kHz 2p
= (ii) With R = 0,
1 2p
L ⇒ C
w o L 2p × 10.066 × 103 × 50 × 10 −3 = = 31.61 R 100
fo 10.066 = = 318 Hz 31.61 Q
Example 13.5 The following circuit parameters are specified for a singletuned capacitivecoupled transistor RF amplifier: Ro of the amplifier stage is 40 kΩ, Ri of the next stage is 20 kΩ. The parallel tank circuit consists of L = 0.01 mH, R = 20 Ω , and C = 47 pF. The stray capacitance at the output terminals is 3 pF. Calculate (i) fo, (ii) Qe, and (iii) BW. Solution: The output circuit is shown in Figure 13.60. Rp C Ro
L C′
+ Ri
Vo −
gmVb′e
Figure 13.60 Output circuit
Ceq = C + C ′ = 47 + 3 = 50 pF
(i) fo =
1
1 =
2p LC
2p 0.01 × 10 −3 × 50 × 10 −12
= 7.12 MHz
Tuned Amplifiers
2
(
)(
2p × 7.12 × 106 0.01 × 10 −3 w o2 L2 Rp = = R 20
(ii)
Rt = Ro // Rp // Ri = 40 // 10.14 // 20 =
695
2
)
= 10.14 kΩ
40 × 10.14 × 20 = 5.76 kΩ 40 × 10.14 + 10.14 × 20 + 20 × 40
Qe = w oCeq Rt = 2p × 7.12 × 106 × 50 × 10 −12 × 5.76 × 103 = 12.88 (iii) BW =
fo 7.12 × 106 = = 552.80 kHz Qe 12.88
Example 13.6 A singletuned transistor amplifier is to amplify a modulated signal, whose carrier frequency is 10.7 MHz and bandwidth is 150 kHz. The effective shunt resistance is 10 kΩ and the stray shunt capacitance is 10 pF. Calculate L and C values used in the tank circuit. Solution: Given Rt = 10 kΩ, fo = 10.7 MHz, and BW = 150 kHz. Qe =
Qe = w oCeq Rt⇒ Ceq =
fo 10700 = = 71.33 BW 150
Qe 71.33 = = 106.15 pF. w o Rt 2p × 10.7 × 106 × 10 × 103
Ceq = C + C ′ ⇒ C = Ceq − C ’ = 106.15−10 = 96.15 pF
L=
1 1 = 4p 2Ceq fo2 40 × 106.15 × 10 −12 10.7 × 106
(
2
)
= 2.06 µH
Example 13.7 A singletuned transistor amplifier is to amplify a modulated signal, whose center 1 frequency is 10.7 MHz and bandwidth is 150 kHz. gm = 10 mA/V, = 40 kΩ, Ri of the next stage hoe is 40 kΩ and the magnitude of the gain at resonance is 100. Find Qe , L, R, and C of the tank circuit. Solution: The output circuit is shown in Figure 13.61.
L C gmVb′e
Ro =1/hoe
Ri R
+ Vo −
+
≡
C gmVb′e
Vo
L
Ro
Figure 13.61 Output circuit of the singletuned transistor amplifier
Rp
Ri −
696
Electronic Devices and Circuits
Given fo = 10.7 MHz, BW = 150 kHz, gm = 10 mA/V, Ro =
Qe =
fo 10700 = = 71.33 BW 150
L=
A = gm Rt = 100
1 = 40 kΩ , Ri = 40 kΩ , and A = 100 hoe Rt =
Rt 10 × 103 = = 2.09 µH w oQe 2p × 10.7 × 106 × 71.33
Rt = Ro // Ri // Rp
⇒
200 + 10Rp = 20Rp
⇒
Ro // Ri = 40 // 40 = 20 kΩ 10Rp = 200 2
(
)(
1 1 = 2 4p Lfo 40 × 2.09 × 10 −6 × 10.7 × 106 2
(
10 =
⇒
20Rp 20 + Rp
Rp = 20 kΩ
⇒
2p × 10.7 × 106 2.09 × 10 −6 w 2 L2 R= o = Rp 20000 C=
100 100 = = 10 kΩ 10 gm
2
)
2
)
=1Ω
= 104.5 pF
Example 13.8 For the singletuned FET amplifier, fo = 10 MHz, BW = 50 kHz, gm = 10 mA/V, and rd = 80 kΩ. The amplifier is required to have A = 75. Determine the component values of the tank circuit. Solution: The input resistance of the next stage is very large, and hence is omitted as an open circuit. Hence, the resultant equivalent circuit is as shown in Figure 13.62, in which R in series with L is replaced by a parallel Rp. +
+
V gs
gmV gs
Rp
rd
Vo C
L
−
−
Figure 13.62 Output circuit of the singletuned FET amplifier
Given fo =10 MHz, BW = 50 kHz, gm = 10 mA/V, rd = 80 kΩ, and A = −75 Qe =
fo 10000 = = 200 BW 50
A = gm Rt = 75
⇒
Rt =
A 75 = = 7.5 kΩ gm 10
Tuned Amplifiers
L=
697
Rt 7.5 × 103 = = 0.597 µH w oQe 2p × 10 × 106 × 200
The input resistance of the next stage is large. Rt = rd // Rp= 80 // Rp = 7.5 kΩ
∴ 600 + 7.5Rp = 80Rp
72.5Rp = 600
⇒
⇒
⇒
)(
2p × 10 × 106 0.597 × 10 −6 w 2 L2 R= o = Rp 8280 1 1 = 4p 2 Lfo2 40 × 0.597 × 10 −6 × 10 × 106
C=
(
80Rp 80 + Rp
Rp = 8.28 kΩ
2
(
7.5 =
2
)
2
)
= 0.17 Ω
= 418.76 pF
Example 13.9 A singletuned FET amplifier has µ = 200 and gm = 5 mA/V. The tuned circuit consists of an inductance of 100 µH and having an associated resistance of 5 Ω in parallel with capacitance of 100 pF. Find (i) fo, (ii) Rp, (iii) A at resonance, and (iv) BW. Solution: 1
(i) fo =
1 =
2p LC
(ii) Rp =
−6
2p 100 × 10 × 100 × 10 −12
w o2 L2 1 and w o2 = LC R ∴
(iii) rd =
= 1.59 MHz
m 200 = = 40 kΩ gm 5
Rp =
L 100 × 10 −6 L2 = = = 200 kΩ LCR CR 100 × 10 −12 × 5
Rt = rd // Rp =
40 × 200 = 33.33 kΩ 40 + 200
A = gm Rt = 5×33.33 = 166.65
(iv) Qe =
Rt 33.33 × 103 = = 33.38 w o L 2p × 1.59 × 106 × 100 × 10 −6 BW =
fo 1590 = = 47.63 kHz Qe 33.38
698
Electronic Devices and Circuits
Example 13.10 A singletuned RF amplifier uses an FET having µ = 300 and rd = 60 kΩ . The parallel tuned circuit consists of an inductance L = 100 µH, which has a series resistance R. Q of the inductance at the resonant frequency is 100. The resonant frequency of the tank circuit is 9.985× 106 rad/sec. A stray capacitance C’ = 10 pF appears across the tank circuit. Find (i) C of the tank circuit, (ii) R, (iii) Rp, (iv) Rt, (v) Qe, ( vi ) A at resonance, (vii) A at a frequency 50 kHz above resonance, (viii) A at a frequency 20 kHz below the resonant frequency, and (ix) BW. Solution: (i) Ceq = C + C ′
=
⇒
wo =
1 6 2
(9.985 × 10 )
× 100 × 10 −6
1
⇒
LCeq
Ceq =
1 w o2 L
= 100.30 pF
C = Ceq − C ′ = 100.30−10 = 90.30 pF
(ii) Q of L at resonance is Q =
R=
∴
(iii) Rp=
wo L R w o L 9.985 × 106 × 100 × 10 −6 = = 9.985 Ω 100 Q
L 100 × 10 −6 = = 110.91 kΩ CR 90.30 × 10 −12 × 9.985
(iv) Rt = rd // Rp = 60 // 110.91 = 38.94 kΩ (v) Qe =
Rt 38.94 × 103 = = 39 w o L 9.985 × 106 × 100 × 10 −6
(vi) Ares = gm Rt =
(vii) fo =
m 300 × Rt = × 38.94 = 194.7 rd 60
w o 9.985 × 106 = 1.59 MHz = 2p 2p d =
f = fo + 50 kHz A = Ares
1 2
1 + ( 2dQe )
f − f0 50 = = 0.0314 f0 1590
⇒ A=
Ares 2
1 + ( 2dQe )
=
194.7 2
1 + ( 2 × 0.0314 × 39)
= 73.58
Tuned Amplifiers
(viii)
d =
f = fo − 20 kHz
f0 − f 20 = = 0.0126 f0 1590
Ares
A=
2
194.7
=
2
1 + ( 2dQe ) (ix) BW =
699
= 139.07
1 + ( 2 × 0.0126 × 39)
fo 1590 = = 40.77 kHz Qe 39
Example 13.11 A singletuned RF amplifier using FET has Ares = 50, fo = 10 MHz, and BW = 125 kHz. The parameters of the FET are µ = 400 and rd = 80 kΩ. The tank circuit consists of L and C in parallel with R as the resistance in series with L. Calculate the parameters of the tank circuit. Solution: gm =
m 400 = = 5 mA/V rd 80
Ares = gm Rt
Ares = 50 Rt =
⇒
 Ares  50 = = 10 kΩ 5 gm
fo 10000 = = 80 BW 125 Rt R 10 × 103 Qe = t ⇒ L = = = 1.99 µH w oL w oQe 2p × 10 × 106 × 80
Qe =
Rt = rd // Rp =
(
rd Rp
⇒10 =
80 × Rp 80 + Rp
rd + Rp 2
)(
⇒70Rp = 800 ⇒Rp =
2p × 10 × 106 1.99 × 10 −6 w 2 L2 R= o = Rp 11430 Rp =
or
C=
800 =11.43 kΩ 70
2
)
= 1.39 Ω
1.99 × 10 −6 L L = ⇒C = = 125.25 pF RRp 11.43 × 103 × 1.39 CR 1 1 = 2 − 4p Lfo 40 × 1.99 × 10 6 × 10 × 106 2
(
2
)
= 125.63 pF
Example 13.12 For a double tuned amplifier, k = 3kc and Q1 = Q2 = Q = 100. The resonant frequency of the tank circuit is 10 MHz. Find (i) the two frequencies f1 and f2 at which the gain peaks occur and (ii) BW of the circuit if g = 3 dB.
700
Electronic Devices and Circuits
Solution: kc =
1 1 = = 0.01 Q 100
k = 3kc = 3× 0.01 = 0.03 2
2
k 2Q 2 = (0.03) (100 ) = 9 (i) The two gain peaks occur at frequencies f1 and f2, where æ ö 1 f1 = fo ç1 k 2Q 2  1 ÷ è 2Q ø 1 1 = 10 1 − 9 − 1 =9.86 MHz k 2Q 2 − 1 = 10 1 − 200 200 æ ö 1 f 2 = fo ç 1 + k 2Q 2  1 ÷ è 2Q ø
and
1 = 10 1 + 9 − 1 =10.14 MHz 200 (ii) g = 3 dB ⇒20 log10 g = 3 dB ⇒ log10 g = 0.15 ⇒g = 2 = 1.414 kQ = g + g 2 − 1 = 2 + 2 − 1 = 2.414 f2 − f1 =
fo Q
Bandwidth = 2( f2 − f1 ) = 2 × 2.2
(2.414)2 − 1 = 2.2 ×
fo Q
fo 3.1 fo 3.1 × 10 = = = 310 kHz. Q Q 100
Example 13.13 A doubletuned amplifier has L1 = L2 = 75 µH and Q1 = Q2 = 80. The transistor has gm = 5 mA/V. Find (i) C1 and C2 so as to have fo = 10.7 MHz, (ii) the spacing between the gain peaks when k = 2kc, (iii) Ap , and (iv) g . Solution: (i) C =
1 1 = 2 − 6 4p Lfo 40 × 75 × 10 × 10.7 × 106 2
(ii) k = 2 kc =
(
2
)
= 2.91 pF ⇒C1 = C2 = 2.91 pF.
2 Q
æ ö 1 4 1 ´ Q 2  1 ÷÷ = 10.7 1 − f1 = fo çç1 3 =10.7 × 0.989 = 10.58 MHz 2 Q 2 Q 160 è ø
Tuned Amplifiers
701
1 æ ö and f2 = 10.7 ç1 + 3 ÷ = 10.82 MHz è 160 ø (iii) Ap =
gmw oQ L1L2
=
2
Ap
1 + k 2Q 2 (iv) =g = = Ac 2 kQ
5 × 10 −3 × 2p × 10.7 × 106 × 80 × 75 × 10 −6 = 1007.9 2 4 × Q2 5 Q2 = = 1.25 2 4 2 × ×Q Q
1+
Example 13.14 A doubletuned amplifier has fo = 10.7 MHz and the spacing between the response Ap peaks is 200 kHz. = 2, Ap = 16 and gm = 10 mA/V. Determine L and C of the tank circuits. Ac Solution: g = 2 ⇒kQ = g + g 2 − 1 = 2 + 2 − 1 = 2.414 f2 − f1 =
Ap =
fo Q
(2.414)2 − 1 = 2.2
fo 2.2 fo 2.2 × 1070 ⇒Q = = = 11.77 Q f2 − f1 200
gmw oQ L1L2 2
16 =
10 × 10 −3 × 2p × 10.7 × 106 × 11.77 × L 2
L=
16 × 2 = 4.05 µH ⇒ L1 = L2 = L = 4.05 µH 10 × 10 × 2p × 10.7 × 106 × 11.77
C=
1 1 = 2 − 6 4p Lfo 40 × 4.05 × 10 × 10.7 × 106
−3
2
(
2
)
= 53.92 pF
C1 = C2 = C = 53.92 pF Example 13.15 The bandwidth of a singlestage, doubletuned amplifier is 200 kHz. Calculate the bandwidth of a 4stage cascaded amplifier. 1
1 4 Solution: The bandwidth of nstage doubletuned amplifier = BW1 2 n − 1 1
1 4 The bandwidth of 4stage doubletuned amplifier = 200 2 4 − 1 = 132 kHz
702
Electronic Devices and Circuits
Summary • A tuned amplifier amplifies only a desired narrow band of frequencies and effectively rejects the unwanted frequencies. • The bandwidth of a singletuned amplifier is fo Qe , where fo is the resonant frequency of the tank circuit and Qe is its effective Q. 1
• The bandwidth of cascaded n identical stages of tuned amplifiers is BWn = BW1 2 n − 1. • The bandwidth of either tuned primary or tuned secondary inductively coupled amplifier is 2 fo Qe, that is, twice the bandwidth of a singletuned capacitivecoupled amplifier. • The Qe of the tank circuit can be adjusted by using a tapped inductance or a tapped capacitance, which in turn controls the bandwidth • A synchronously tuned doubletuned amplifier has two mutually coupled tuned circuits and both the tuned circuits are tuned to the same center frequency. The doubletuned amplifier usually finds application in radiofrequency (RF) and intermediate frequency (IF) amplifiers in radio receivers. • In the synchronously tuned doubletuned amplifier, at kQ = 1, the response is similar to the response of a singletuned amplifier. This value of k = kc is called critical coupling. • In the synchronously tuned doubletuned amplifier, if kQ < 1, it is said to be a case of under coupling and the gain is less than the maximum. • In the synchronously tuned doubletuned amplifier, if kQ > 1, there is overcoupling. There are two peaks in the output. The spacing between the two peaks depends on the value of k. 3.1 fo . Q • In a staggertuned amplifier two tuned circuits are used, which are tuned to two resonant frequencies that are separated by the bandwidth of a singletuned amplifier. • The bandwidth of a synchronously tuned doubletuned amplifier is
• The bandwidth of a staggertuned amplifier is 2 times the bandwidth of the single tuned amplifier. • Tuned power amplifiers are used to raise the narrow band AM signal power to the tune of a few hundred kW or they may be also used as harmonic generators. • Miller capacitance reduces the input impedance of an amplifier at high frequencies, and hence the gain of the amplifier and its bandwidth are reduced. In order to improve the bandwidth of this amplifier either series compensation or shunt compensation is used. Such compensated amplifier is called wideband amplifier.
multiple ChoiCe QueStionS 1. In a tuned circuit, L = 100 µH and C = 100 pF. The resonant frequency w o is (a) 10 MHz (b) 20 MHz (c) 5 MHz (d) 1 MHz 2. In a singletuned amplifier, f = 12 MHz and fo = 10 MHz. Then the frequency deviation d is (a) 0.2 (b) 0.1 (c) 10 (d) 20 3. Two identical singletuned amplifiers are cascaded. The bandwidth of each stage is 10 kHz. The bandwidth of the cascaded amplifier is (a) 64.3 kHz (b) 6.43 kHz (c) 0.643 kHz (d) 643 kHz
Tuned Amplifiers
703
4. In a tapped inductance tuned amplifier, the tap on the inductance is used to adjust (a) Q of the tank circuit (b) output resistance (c) lower halfpower frequency (d) upper halfpower frequency 5. In a doubletuned amplifier, both the tuned circuits are tuned to (a) two different frequencies (b) same frequency (c) two different frequencies separated by the bandwidth of each stage (d) none of these 6. In a doubletuned amplifier, k = 0.25, Q = 10, and fo = 10 MHz. Then the two gain peaks occur at (a ) f1 = 0.885 MHz and f2 = 1.115 MHz ( b ) f1 = 88.5 MHz and f2 = 111.5 MHz ( c ) f1 = 8.85 MHz and f2 = 11.15 MHz ( d ) f1 = 885 MHz and f2 = 111.5 MHz 7. In a doubletuned amplifier, k = 0.25, Q = 10, then g is (a) 14.5 (b) 1.45 (c) 0.145 (d) 1450 8. In a doubletuned amplifier (a) 31 kHz (c) 3.1 MHz
fo = 1 MHz . Then its bandwidth is Q (b) 3.1 kHz (d) 31 MHz
9. In a staggertuned amplifier two tuned circuits are used which are tuned to two resonant frequencies which are separated by (a) the bandwidth of a singletuned amplifier (b) the bandwidth of a doubletuned amplifier (c) 2 times the bandwidth of a singletuned amplifier (d) none of these 10. A classC tuned power amplifier can also be used as a (a) wideband amplifier (b) staggertuned amplifier (c) audio power amplifier (d) harmonic generator 11. Miller effect reduces the bandwidth, when a CE amplifier is used at high frequencies. If, to improve the bandwidth shunt compensation is used, then the resultant amplifier is called (a) RC coupled amplifier (b) tuned ClassC amplifier (c) wideband amplifier (d) emitter follower 12. 2 MHz is the bandwidth of an uncompensated CE amplifier at high frequencies. If frequency compensation is provided with shunt connected inductance L chosen as L = 1.656 Lcritical, then the new bandwidth is (a) 3.44 MHz (c) 8 MHz
(b) 4 MHz (d) 1.72 MHz
Short anSwer QueStionS 1. Where is the need for tuned amplifiers? 2. What is Q of the tank circuit?
704
Electronic Devices and Circuits
3. What is the expression for the relative gain of a singletuned capacitor coupled amplifier? 4. How are resonant frequency and bandwidth related in a singletuned amplifier? 5. n number of singletuned identical amplifiers are cascaded, what is the bandwidth of the cascaded configuration? 6. How are doubletuned amplifiers classified as? 7. What is the difference between the synchronously tuned doubletuned amplifier and the staggeredtuned aamplifier? 8. What is the advantage of the synchronously tuned doubletuned amplifier when compared to a singletuned amplifier, in terms of bandwidth? 9. What is the advantage of the staggertuned doubletuned amplifier when compared to a singletuned amplifier, in terms of bandwidth? 10. What do you understand by instability in a tuned amplifier? 11. How do you propose to eliminate the problem of instability in a tuned amplifier? 12. List two applications of a tuned classC amplifier. 13. What is the need for frequency compensation in an amplifier, and how is it implemented?
long anSwer QueStionS 1. Draw the circuit of a singletuned voltage amplifier and show that the relative gain is given as
1 . 1 + j 2dQe
Draw the circuit of a tuned primary transistor voltage amplifier and derive the expression for its gain. Draw the circuit of a tuned secondary FET voltage amplifier and derive the expression for its gain. Draw the circuit of a doubletuned transistor voltage amplifier and derive the expression for its gain. Draw the circuit of a staggertuned transistor voltage amplifier and obtain the expression for its gain. 6. Draw the circuit of a tuned classC power amplifier and derive the expression for its efficiency. 7. What is a wideband amplifier? Show with the help of relevant expressions that by proper choice of Q the bandwidth of a compensated amplifier is 1.72 times the bandwidth of the uncompensated amplifier.
2. 3. 4. 5.
unSolved problemS 1. An RLC circuit shown in Figure 13.63 has fo = 1 MHz , Qo = 100, and R = 500 Ω. Determine the values of L and C. 2. A variable condenser that has C min = 50 pF and C max = 500 pF is used in an LC tank circuit for which the minimum frequency to be tuned, L C fmin = 1 MHz. Find (i) the value of L, (ii) fmax, and (iii) R of the coil if the R bandwidth is 10 kHz. 3. The following circuit parameters are specified for a singletuned capacitivecoupled transistor RF amplifier: Ro of the amplifier stage is 50 kΩ, Ri of the next stage is 2 kΩ. The parallel tank circuit consists of L = 0.01 mH, Figure 13.63 Tuned circuit R = 10 Ω, and C = 100 pF. The stray capacitance at the output terminals is 3 pF. Calculate (i) fo , (ii)Qe , and (iii) BW. 4. For the singletuned FET amplifier, fo =10 MHz, BW = 100 kHz, gm = 2.5 mA/V, and rd = 60 kΩ. The amplifier is required to have A = 50. Determine the component values of the tank circuit.
Tuned Amplifiers
705
5. A singletuned transistor amplifier is required to amplify an AM signal with center frequency of 500 kHz and bandwidth of 10 kHz. The total shunt resistance is 10 kΩ and the output capacitance is 30 pF. Determine the values of L and C. 6. (i) The bandwidth of a singletuned amplifier is 10 kHz. Calculate the bandwidth if two and four such stages are cascaded. (ii) The bandwidth of a doubletuned amplifier is 10 kHz. Calculate the bandwidth if two and four such stages are cascaded.
14
OPERATIONAL AMPLIFIERS
Learning objectives After reading this chapter the reader will be able to Understand the need for a differential amplifier and necessity to have a large common mode rejection ratio (r) Realize that a differential amplifier supplied with a constant current will make the value of r ideally infinity Appreciate the need for a dc level shifter in an Opamp Understand the need and the types of frequency compensation techniques employed in Opamps Learn the experimental procedures to measure the parameters of the Opamp
14.1
INTRODUCTION
An operational amplifier is a highgain directcoupled amplifier. The main advantage of a directcoupled amplifier is that its frequency response is flat right from 0 Hz. Opamp can be used both for dc and ac applications. The block diagram in Figure 14.1 gives the basic building blocks of an opamp.
V1 V2
Dualinput, balancedoutput differential ampliﬁer
Dualinput, unbalancedoutput differential ampliﬁer
DC level shifter
Output power stage
Vo
Figure 14.1 Block diagram of operational amplifier
The first stage in an operational amplifier is a differential amplifier or a difference amplifier. Two signals V1 and V2 are the inputs to the differential amplifier consisting of two transistors: Q1 and Q2. The output of this amplifier is taken between the two collectors. If Q1 and Q2 are identical, then the dc voltage between these two collectors is zero. Therefore, the first stage in an operational amplifier is a dualinput balancedoutput differential amplifier. This stage accounts for the maximum gain in the amplifier. The second stage is also a dual input; but in this case, the output is taken at one of the collectors with respect to the reference terminal and hence the output is
Operational Amplifiers
707
unbalanced. Therefore, the second stage is a dual input, unbalanced output differential amplifier. Since opamp is a directcoupled amplifier, the output of one stage is directly connected to the input of the next stage without using any reactive elements such as capacitors or transformers. If dc is directly connected to the input of the next stage, this may alter the biasing conditions of the succeeding stage that may cause distortion in its output. Hence, there arises the need for incorporating a dclevel shifter in an opamp, which is usually an emitter follower stage. Hence, the third stage in an opamp is a dclevel shifter or dclevel translator. The device should ultimately be capable of delivering a certain amount of output power. Therefore, the output stage is a complementary symmetry push–pull power amplifier, which has been considered in Chapter 11. We now discuss the working of each of these building blocks.
14.2
DIFFERENTIAL AMPLIFIER
A differential amplifier is used as an input stage in many measuring instruments. A differential amplifier has two inputs V1 and V2 and the output Vo is proportional to the difference of the two inputs (Figure 14.2). The difference signal Vd is (14.1)
Vd = V1 − V2
In many cases, the output, in addition to the required differential signal, may also contain an error term due to the average of the two inputs, called the commonmode signal, Vc. Vc =
V1 + V2 2
(14.2)
V1 Differential ampliﬁer
Vo = AdVd
V2
Figure 14.2 Differential amplifier
A twotransistor differential (or difference) amplifier is shown in Figure 14.3. The circuit can be seen as one in which two CE amplifiers with emitter bias are combined together. The two halves of the circuit are assumed to be identical. As the output is taken between the two collectors, this is a dualinput, balancedoutput differential amplifier. From Figure 14.3, let Vo be the linear combination of the outputs of Q1 and Q2. Vo = AV 1 1 + A2V2
(14.3) VCC
where A1 is the gain of Q1 and A2 is the gain of Q2. We have V1 V2 = Vd
(14.4)
RC
RC
And
Vo
V1 + V2 = 2Vc
(14.5)
V1
V2 Q2
Q1
Solving Eqs (14.4) and (14.5), 1 V1 = Vc + Vd 2
(14.6)
1 V2 =Vc  Vd 2
(14.7)
RE
−VEE
Figure 14.3 A twotransistor differential amplifier
708
Electronic Devices and Circuits
Substituting Eqs (14.6) and (14.7) in Eqn (14.3),
( A − A2 )V + A + A V 1 1 Vo = A1 (Vc + Vd ) + A2 (Vc − Vd ) = 1 ( 1 2) c d 2 2 2 \Vo = Ad (V1 V2 ) + Ac where Ad =
( A1  A2 ) 2
(V1 +V2 ) 2
(14.8)
and Ac = ( A1 + A2 ) \Vo = AdVd + AV c c
(14.9)
æ ö æ A 1 ö Vo = Ad çVd + c Vc ÷ = Ad çVd + Vc ÷ Ad ø r ø è è
(14.10)
Or
Ad is the figure of merit of the differential Ac amplifier. r, the figure of merit of the differential amplifier is indicative of the ability of the differential amplifier to reject the unwanted commonmode signal Vc (error signal) and deliver only the desired differential signal Vd at the output. The larger the value of r, the better the rejection of the unwanted common mode signal in the output. Ideally, when r = ∞, Vo = AdVd . The output contains only the differential signal. where r = common mode rejection ratio (CMRR) =
Example 14.1 A differential amplifier has Ad = r = 40 dB (i) V1 = 50 μV and V2 = –50 μV. (ii) V1 = 1050 μV and V2 = 950 μV. Calculate V0 and the percent error in both the cases. Solution: Given r = 40dB, then it means that r = 100, since 20 log10 100 = 40dB. (i) Vd = V1  V2 = 50  ( 50 ) = 100 mV and Vc =
V1 + V2 50 − 50 = = 0. 2 2
\Vo = AdVd = (100 ´ 100 )mV = 10 mV This is the output of an ideal differential amplifier. The output contains only the differential component: % error = 0% V + V2 1050 + 950 (ii) Vd = V1 V2 =1050  950 = 100 mV and Vc = 1 = =1000 mV 2 2 æ 1 ö 1 æ ö Vo = Ad çVd + Vc ÷ =100 ç100 + ´ 1000 ÷ = 11mV r 100 è ø è ø % error = 10% Example 14.2 A differential amplifier has Ad = 40 dB. V1 = 1050 μV and V2 = 950 μV. Calculate the % error, if (i) r = 60 dB and (ii) r = 80 dB
Operational Amplifiers
Solution: Vd = V1 V2 =1050  950 =100 mV and Vc =
709
V1 + V2 1050 + 950 = =1000 mV 2 2
(i) r = 60dB, then it means that r = 1000 æ 1 ö 1 æ ö Vo = Ad çVd + Vc ÷ =100 ç100 + ´ 1000 ÷ = 10.1mV r 1000 è ø è ø For an ideal differential amplifier, Vo =10 mV Therefore, % error = 1% (ii) r = 80dB, then it means that r = 10000 æ 1 ö 1 æ ö Vo = Ad çVd + Vc ÷ = 100 ç100 + ´ 1000 ÷ = 10.01mV r 10000 è ø è ø For an ideal differential amplifier, Vo =10 mV Therefore, % error = 0.1% From the above examples, it can be noted that the percentage error becomes small as the value of r becomes larger and larger. Ideally, r should be infinity.
14.2.1 DC Analysis For the differential amplifier shown in Figure 14.3, proper dc conditions must first be established before being used as an amplifier. To determine the operating point, consider the dc circuit shown in Figure 14.4. The dc circuit is obtained by shorting the ac sources. From Figure 14.4, VCC
VEE = VBE + 2 I E RE or
RC
IE =
VEE VBE 2RE
VC = VCC  I C RC
(14.11) +
(14.12) IB
and
IC
VC +V Q1 CE −
VBE −
IE
IC
VE
RC
+VC VCE Q − 2 IE
− VBE
RE
VE = VBE
(14.13)
VCE = VC − VE = VCC − I C RC − ( −VBE ) = VCC + VBE − I C RC \ VCE = VCC + VBE  I E RC since I E » I C I C and VCE specify the coordinates of the Qpoint.
(14.14)
VEE
Figure 14.4 DC circuit
+ IB
710
Electronic Devices and Circuits
14.2.2 AC Analysis In order to determine the gain, input resistance, and output resistance, it becomes necessary to draw the ac circuit. The ac circuit is drawn by shorting the dc sources (Figure 14.5). The redrawn ac circuit and the equivalent circuit are shown in Figures 14.6 and 14.7. From Figure 14.7, VCC
VCC
RC
RC −
V1
Vo
Q1
V1 = ( re + RE ) I e1 + RE I e 2
(14.15)
V2 = RE I e1 + ( re + RE )I e 2
(14.16)
Using Cramer’s rule,
+ Q2
V1 RE V ( r + RE ) V2 RE V2 re + RE I e1 = = 1 e (14.17) re + RE RE re ( re + 2RE ) RE re + RE
V2
RE
Similarly, re + RE V1 I e2 =
Figure 14.5 To draw ac circuit short dc sources Vo Vc1 Ic1
V2 (re + RE ) − V1RE RE V2 (14.18) = re + RE RE re (re + 2RE ) RE re + RE
+
− Ie1
Vc2 Ic2
Ie2 Q2
Q1
Ad = RC
Ib1
+
(V1 − V2 )( re + 2RE )RC re ( re + 2RE )
Vo = (II e1 − I e 2 )RC =
+
Ib2 RE
RC
V2
V1
(re + 2RE ) RC ≈ RC Vo = (V1 −V2 ) re (re + 2RE ) re
since re 0
(ii) When Vi < 0, Vo1 = Vsat . Therefore, D1 is OFF and D2 is ON (Figure 15.97). I3
R
R
R V
R
−
+ A Vs
OFF A1
I1
+
D1 V
Vo1
− Vd = 0
0 A2
+
t
+ Vo −
D2 ON 0
t
R
I2
Figure 15.97 Circuit whenVi < 0
Let Vo1 = V . If Vd is approximately zero, V appears at the inverting input of A2. A virtual ground exists at the input of A1. Therefore, V V V I1 = s , I 2 = and I 3 = R R 2R
812
Electronic Devices and Circuits
Writing the KCL at node A, I1 + I 2 + I 3 = 0
(15.109)
Vs V V + + =0 R R 2R
(15.110)
2 V = − Vs 3 To find Vo , consider the circuit of A2 (Figure 15.98). or
R
R
(15.111)
R
− A2 V
+
t
0 + Vo −
Figure 15.98 Circuit to calculate Vo
R 3 3 2 Vo = V 1 + = V = × − Vs = −Vs 2R 2 2 3
(15.112)
During the negative half cycle of the input, the output is shifted in phase by 180°. The input and the output waveforms are shown in Figure 15.99.
Vs
0
t
0
t
Vo
Figure 15.99 Input and the output waveforms of the fullwave rectifier
Additional Solved Examples Example 15.19 Design the noninverting amplifier shown in Figure 15.100, using opamp 741, so as to get an output voltage of 4 V, with an input of 50 mV. For IC 741, I B(max ) = 500 nA
Applications of OpAmp
R3
813
+ Ri
+
+
−
Vi
R1
−
Vo
−
I2 I2
R2
Figure 15.100 Noninverting amplifier
Solution: I B(max ) = 500 nA . I 2 is chosen such that I 2(min) >> I B(max ) . Choose I 2 = 0.1 mA . The voltage across R2 = VR 2 = Vi = 50 mV ⇒ Vi = I 2 R2 . Therefore, R2 =
Vi 50 = = 500 Ω I 2 0.1
From Figure 15.100, I 2 ( R1 + R2 ) = Vo Þ ( R1 + R2 ) =
Vo 4 = = 40 kW. Therefore, I 2 0.1
R1 = ( R1 + R2 ) − R2 = 40 − 0.5 = 39.5 kΩ For bias compensation, R3 = R2  R1 =
39.5 × 0.5 = 494 Ω ≈ 500 Ω 39.5 + 0.5
For the noninverting amplifier, R 39.5 Vo = Vi 1 + 1 = 50 × 10 −3 1 + =4V 0.5 R2 Example 15.20 For the summing amplifier in Figure 15.101, find Vo , if V1 = 1 V , V2 = 1 V, R = 10 kΩ, and RF = 100 kΩ. The voltage at the noninverting input terminal is due to V1 and V2 sources. Using the superposition theorem, the net voltage VA is VA = V1
V V R 1 1 R + V2 = 1 + 2 = + =1V R+R R+R 2 2 2 2
R 100 Vo = VA 1 + F = 1 1 + = 11 V 10 R
814
Electronic Devices and Circuits RF
R −
R
+ Vo −
VA
V1
+
V2 R
Figure 15.101 Summing amplifier
Example 15.21 For the Schmitt trigger circuit shown in Figure 15.77, determine the values of R1 and R2 . The supply voltages are ± 15 V and the range of hysteresis is 5 V. Solution: VH = VUTP − VLTP = bVsat − ( − bVsat ) = 2 bVsat = 2Vsat
R2 R1 + R2
Vsat = 0.9VCC = 0.9 × 15 = 13.5 V 5 = 2 × 13.5 × 1+
R2 R1 + R2
R1 27 R = = 5.4 ⇒ 1 = 4.4 ⇒ R1 = 4.4R2 R2 5 R2
Choose R2 = 10 kΩ, then R1 = 4.4 × 10 = 44 kΩ Example 15.22 For the opamp circuit shown in Figure 15.21, R1 = 10 kΩ, R2 = 20 kΩ, R3 = 25 kΩ, R4 = 50 kΩ, RF = 100 kΩ, and R5 = 20 kΩ. Determine the numerical value of Vo , if V1 = V2 = 1 V , and V3 = V4 = 2 V . Solution: R R 100 100 Vo1 = − F V1 + F V2 = − ×1+ × 1 = −15 V. 10 20 R2 R1 From Eqn. (15.23), VA = V3
R4 R5 R3 + R4 R5
= 2×
+ V4
R3 R5 R4 + R3 R5
50 20 25 20 +2× = 0.73 + 0.36 = 1.09 V 25 + 50 20 50 + 25 20
RF 100 Vo 2 = VA 1 + = 1.09 1 + = 17.43 V 10 20 R1 R2 Vo = Vo 2 + Vo1 = 17.43 − 15 = 2.43 V
Applications of OpAmp
815
Example 15.23 Design the symmetric astable circuit, shown in Figure 15.55, to oscillate at 5 kHz. Solution: T =
1 1 = = 0.2 ms f 5 T = 2t log n
If
Therefore,
R1 = 1.16R2 , b =
1+ b 1− b
[ in Eqn. (15.72 )]
R2 R2 1 = = = 0.46. R1 + R2 1.16R2 + R2 2.16
1 + 0.46 T = 2t log n t n = 2t log=n 2t.70 =n 2t 1 − 0.46
=
T = 0.1 ms 2
Therefore, RC = 0.1 × 10 −3 s
Choose C = 0.01 mF, then R =
0.1 × 10 −3 = 10 kΩ 0.01 × 10 −6
R2 R R 1 = 0.46 ⇒ 1 + 1 = = 2.17 ⇒ 1 = 1.17 ⇒ R1 = 1.17R2 R1 + R2 R2 0.46 R2 Choose R2 = 10 kΩ, then R1 = 1.17R2 = 1.17 × 10 = 11.7 kΩ Example 15.24 A triangular waveform having a peak amplitude of 2 V, and a frequency of 1 kHz is applied to the inverting input terminal of the zerocrossing detector (Figure 15.102). Plot the input and the output waveforms, if the supply voltages are ±15 V .
− + vs
VR
Vo
+
−
Figure 15.102 Inverting zerocrossing detector
Solution: Vsat = 0.9 × VCC = 0.9 × 15 = 13.5 V When, Vs > 0, Vo = Vsat = 13.5 V and when, Vs < 0, Vo = +Vsat = 13.5 V The input and the output waveforms are shown in Figure 15.103.
816
Electronic Devices and Circuits
2V Vi
2
1
3
0V
t ms
−2 V +Vsat = 13.5 V Vo 0 V
t ms
−Vsat = −13.5 V
Figure 15.103 Input and output waveforms
Summary R and that of the noninverting amplifier is 1 + F . R1 R1 • In a summing amplifier, the output is proportional to the sum of the input voltages, and in a subtracting amplifier the output is proportional to the difference of the input voltages • The gain of an inverting amplifier is
−RF
• A differential amplifier can be used as an instrumentation amplifier. • An integrator is a circuit that gives an output proportional to the integral of the input signal and a differentiator is a circuit that gives an output proportional to the differential of the input signal. • A voltagetocurrent converter is a circuit in which the output current is proportional to the input voltage, and a currenttovoltage converter is a circuit in which the output voltage is proportional to the input current. • Opamp can be used as a monostable, astable, and Schmitt trigger. • Log and antilog amplifiers can be used as voltage multipliers and dividers. • A zerocrossing detector is the one that tells the time instant the input has reached a zero level. • A level detector is the one that tells the time instant the input has reached a preset reference level. • The purpose of a window detector is to tell whether the unknown input lies between a specified voltage range or not. • Precision rectifiers use opamps along with diodes to ensure that the circuit configuration behaves as an ideal diode. Then, this circuit configuration is called a superdiode
multiple ChoiCe QueStionS 1. What is the output of the amplifier shown below? RF
1 R1
− 1
+
+ Vi
1mV −
+15V
Vo
+
− −15V
Applications of OpAmp
(a) +15 V (c) −1 V
(b) −15 V (d) −10 V
2. What is the output of the amplifier shown below? RF
1 R1
+15V
− 1
+ Vo
+ + 1mV Vi −
(a) +15 V
− −15V
(b) −15 V (d) −2 mV
(c) 2 mV
3. What is the input voltage of the amplifier, if the output voltage is −10 V ? (a) 10 V (b) 1 V (c) 0.1 V (d) 0.01 V RF
10
R1
+15V
−
+ Vi
10 + Vo −
+ −15V
5
4. For the circuit shown below, Vo is 200
20 10mV
10mV
+15V
− 10 + −15V
(a) 300 mV (c) +15 V
(b) 500 mV (d) −15 V
+ Vo −
817
818
Electronic Devices and Circuits
5. For the circuit shown below, Vo is 20
20
+15V
− 10mV 10mV
+ Vo −
+
20
−15V
20
(a) 0 (c) +15 V
(b) 500 mV (d) −15 V
6. In an inverting RC integrator using an opamp, RC = 1 s, Vi = 5 V , then Vo = _______ (a) 10 t (b) −5 t (c) 5 t (d) 15 V 7. In a monostable multivibrator using an opamp, if b = 0.5 , R = 10 kΩ and C = 0.1 mF, T = _________ (a) 0.69 ms (b) 6.9 ms (c) 0.69 ms (d) 6.9 ms 8. In an astable multivibrator using an opamp, if, R1 = 1.16R2 , R = 10 kΩ, and C = 0.1 mF , then f is (a) 500 Hz (c) 50 Hz
(b) 1000 Hz (d) 100 Hz
9. If the transfer characteristic of a circuit is as shown in figure below, the circuit is a VCC Vo
0 VLR
(a) pulse generator (c) window detector
VUR
(b) dc amplifier (d) ac amplifier
Vi
Applications of OpAmp
819
10. For the Schmitt trigger circuit shown below, the UTP and LTP, respectively, are VCC Vi
− Vsat = 14V VR
+
+ −VEE
R
R
(a) +7 V and − 7 V (c) −7 V and + 7 V
(b) +15 V and − 15 V (d) −15 V and + 15 V
Short anSwer QueStionS 1. What is the expression for the gain of an inverting feedback amplifier? 2. What is the expression for the gain of a noninverting feedback amplifier? 3. What is a summing amplifier? 4. What is a subtracting amplifier? 5. What are the advantages of a buffer amplifier? 6. What are the limitations of an ideal integrator? How are they overcome? 7. What are the main requirements of an instrumentation amplifier? 8. How are V − I converters classified as? 9. Name some of the applications of a comparator?
Vi 10. If the output of a logarithmic amplifier is given as Vo = −hVT ln I R , name the limitation of this amplifier. S
820
Electronic Devices and Circuits
long anSwer QueStionS 1. Draw the circuit of an adder–subtractor using a single opamp and derive the expression for its output voltage. 2. Draw the circuit of a logarithmic amplifier and derive the expression for its output voltage. Show how temperature compensation is provided in this amplifier. 3. Draw the circuit of an antilogarithmic amplifier and derive the expression for its output voltage. Show how temperature compensation is provided in this amplifier. 4. With the help of a neat circuit diagram, explain the working of a monostable multivibrator using an opamp. Derive the expression for its pulse width. Draw the waveforms. 5. With the help of a neat circuit diagram, explain the working of an astable multivibrator using an opamp. Derive the expression for its frequency. Draw the waveforms. 6. What are precision rectifiers? Explain the working of a fullwave rectifier.
unSolved problemS 1. For the circuit shown in Figure 15.5, R4 = R2 = 200 kΩ, R3 = 1 kΩ and R1 = 500 kΩ Calculate the gain and input resistance of the amplifier. 2. For the circuit shown in Figure 15.104, V1 = 1 V and V2 = 2 V . Determine Vo . R R R
− R Vi
+ V1
A1
+
Vo1
+
R
A2
R
− +
−
+ Vo −
V2
−
Figure 15.104 Twostage amplifier 3. For the amplifier circuit shown in Figure 15.44, find the differential input needed to give an output of 10 V, when the center tap of the 1 kΩ pot is (i) at position A and (ii) at position B. 4. For the circuit in Figure 15.105, calculate Vo , if Vi = 2V .
Applications of OpAmp
821
R4 5
5
−
Vi R3
VA VB
A1
Vo
+
+
R1 100
5
R2
Figure 15.105 Amplifier circuit 5. For the unsymmetric astable shown in Figure 15.58, R1 = R2 = 10 kΩ, R4 = 5 kΩ, R3 = 10 kΩ, and C = 0.1 mF, calculate the frequency and the duty cycle. 6. Design an adder–subtractor shown in Figure 15.21 to get V0 = 3V1 − 3V2 + 3V3 − 4V4 .
16
ACTIVE FILTERS
Learning objectives After reading this chapter, the reader will be able to
16.1
Learn the characteristics of lowpass, highpass, and bandpass passive filters Understand the limitations of passive filters and the need for active filters Appreciate the analysis and design of firstorder and higherorder Butterworth filters Understand the need and application of an allpass filter Realize the importance of switched capacitor filters
INTRODUCTION
Filters are frequencyselective electronic circuits that pass only the desired band of frequencies from the input to the output and reject or attenuate the unwanted frequencies. Filters are broadly classified as follows: (i) Passive and active filters (ii) Analog and digital filters (iii) Audio frequency (AF) and radio frequency (RF) filters (i) Passive and active filters: Passive filters use only passive circuit components such as resistors, capacitors, and inductors; whereas, active filters use active circuit components such as transistors and opamps in addition to the passive circuit components. The main limitation of the passive filters is that the output is smaller than the input as the signal gets attenuated. Also the circuit may load the driving signal source. (ii) Analog and digital filters: Analog filters are used to process analog signals using analog techniques and digital filters use the digital techniques to process analog signals. (iii) Audio frequency (AF) and radio frequency (RF) filters: These filters are classified as AF and RF filters depending on the frequency range of operation. Filters are also classified as follows (i) (ii) (iii) (iv) (v)
Lowpass filter Highpass filter Bandpass filter Band elimination (or band reject) filter Allpass filter
Active Filters
16.2
823
PASSIVE LOWPASS, HIGHPASS, AND BANDPASS FILTERS
16.2.1 LowPass Filter An ideal lowpass filter is one for which there is a constant output for frequencies from 0 to fH and no output for frequencies beyond fH. This means the filter only passes frequencies from 0 to fH . fH is called the corner frequency or the cutoff frequency. But a practical lowpass filter will not have a sharp cutoff and frequency components above fH may also be found in the output, though with a reduced magnitude (Figure 16.1). Ideal response
Practical response
A = Vo / Vi
Stop band Pass band
fH
0
f
Figure 16.1 Ideal and practical responses of a lowpass filter
A passive lowpass circuit may contain RC or RL components (Figure 16.2). L R +
+ C
Vi
Vo
−
−
+
+
Vi
R
−
Vo −
(b) RL circuit
(a) RC circuit
Figure 16.2 Passive lowpass circuit
Assuming sinusoidal input and using Laplace transforms, from Figure 16.2(a), 1 Vo ( s ) 1 sC = = 1 Vi ( s ) 1 + sCR +R sC
(16.1)
To plot the frequency response, substitute s = jw in Eqn. (16.1). Vo ( jw ) 1 = Vi ( jw ) 1 + jwCR
Let
wH =
1 1 or fH = CR 2pCR
(16.2)
(16.3)
824
Electronic Devices and Circuits
Therefore,
A=
Vo ( jw ) = Vi ( jw ) A=
1
w 1+ j wH 1
f 1+ fH
=
1 f 1+ j fH
(16.5)
2
f q = − tan −1 fH
and
(16.4)
(16.6)
where q is the phase angle. From Eqn. (16.5), 1 At f = 0, A = 1, at f = fH , A = and at f = ¥, A = 0. 2 Therefore, the response of the circuit is as shown in Figure 16.3. For 0 < f < fH, A < 1 and the gain (which in fact is attenuation here) will not remain constant in the pass band. This is one main limitation of the passive lowpass circuit. Also the response of the filter is not ideal, and hence the output contains unwanted frequencies. The cutoff or corner or breakpoint frequency ( fH ) is the frequency where R = X C . At this V 1 frequency, Vo is attenuated to 70.7 percent of Vi or −3 dB = 20 log10 o = 20 log10 = −3 dB Vi 2 of the input. Also, since the filter contains C, the phase angle (q) of the output signal lags behind that of the input and at fH it is −45° out of phase. By cascading two RC lowpass filters, the filter becomes a secondorder filter, for which the gain rolls off at a slope of −40 dB/decade. For a fourthorder filter, the rolloff is at a slope of −80 dB/decade and so on. This means that as the order of the filter is increased, the rolloff slope becomes steeper and the actual stop band response of the filter approaches its ideal stop band characteristics. A 0 dB 1 −3 dB 0.707
Stop band
Slope = −20 dB/decade Pass band
0
fH
f
0
fH
f
0° q −45°
−90°
Figure 16.3 Response of a practical RC passive lowpass circuit
Active Filters
825
When n identical RC filters are cascaded together, the output gain at the required cutoff n 1 frequency ( fH ) is reduced and is given as , where n is the number of cascaded stages. 2 2 Therefore, for a secondorder passive lowpass filter the gain at fH is (0.707 ) Vi = 0.5Vi (the gain 3
is = −6 dB), for a thirdorder passive lowpass filter it is (0.707 ) Vi = 0.353Vi (the gain is = −9 dB) and so on.
16.2.2 HighPass Filter An ideal highpass filter is one for which there is zero output for frequencies from 0 to fL and constant output for frequencies beyond fL. This means the filter passes frequencies from fL to ¥. fL is called the corner frequency or the cutoff frequency. But a practical highpass filter will not have a sharp cutoff and frequency components below fL may also be found in the output, though with a reduced magnitude (Figure 16.4). Practical response A = Vo / Vi
Ideal response Stop band Pass band
fL
0
f
Figure 16.4 Ideal and practical responses of a highpass filter
Passive RC and RL highpass circuits are shown in Figure 16.5. For a sinusoidal input and using Laplace transforms, from Figure 16.5(a), Vo ( s ) R sCR = = 1 Vi ( s ) 1 + sCR +R sC
(16.7)
To plot the frequency response, substitute s = jw in Eqn. (16.7), R
C
+
+
Vi
Vo R
−
− (a) RC circuit
+
+ L
Vi
Vo
−
− (b) RL circuit
Figure 16.5 Passive highpass circuit
826
Electronic Devices and Circuits
A=
Let
1 Vo ( jw ) jwCR = = Vi ( jw ) 1 + jwCR 1 − j 1 wCR
ωL =
1 or 1 fL = CR 2pCR
(16.8)
(16.9)
Therefore, A=
Vo ( jw ) = Vi ( jw )
1 w 1− j L w
1
=
1− j
fL f
1
A=
f 1+ L f
(16.11)
2
f q = − tan −1 L f
and the phase angle
(16.12)
From Eqn. (16.11), 1
At f = 0, A = 0, at f = fL , A =
and at f = ¥, A = 1. 2 Therefore, the response of the circuit is as shown in Figure 16.6. A 1 0.707
0
fL
f
fL
f
90°
q
45°
0° 0
Figure 16.6 Response of a practical RC passive highpass circuit
Highpass circuits may be cascaded to improve the rolloff.
(16.10)
Active Filters
827
16.2.3 BandPass Filter A cascaded configuration of a HPF and an LPF would form a bandpass filter (Figure 16.7). The filter passes to the output, signals that lie between fL and fH. fo = fL fH . The phase angle of Vo leads Vi by +90° up to fL and then decreases linearly till fo at which it becomes zero. Then, Vo lags Vi and at f = fH and beyond it is −90° (Figure 16.8). High pass ﬁlter
Low pass ﬁlter
C2
R1
+
+
Vi
C1
R2
−
Vo −
Figure 16.7 Bandpass filter
Stop band
Stop band
0 dB −3 dB A Pass band −dB 0
fL
f0
fH
f
+90° q
f
0° −90°
Figure 16.8 Response of the bandpass filter
16.3
ACTIVE FILTERS
The main disadvantages of passive filters are (i) the amplitude of the output signal is less than that of the input signal; (ii) the load impedance affects the filters characteristics; (iii) attenuation becomes severe in cascaded filter; and (iv) when multiple stages are cascaded, there can be loading effect between successive filter stages, which results in further loss of signal. The loss of signal can be made up by using active filters. Further, isolation can be provided between successive stages
828
Electronic Devices and Circuits
by using buffers. Active filter circuits contain active components such as operational amplifiers, transistors, or FETs with the main objective of providing amplification. However, there is no need to provide power from an external power source in passive filters, whereas active filters need external power source(s). A simple active lowpass filter using opamp is shown in Figure 16.9.
R
− A +
+
+ Vo
Vi C
−
Figure 16.9 Active lowpass filter
The filter uses a buffer amplifier (A = 1), but the major advantage is that the buffer amplifier has a large input resistance that avoids loading the signal.
16.3.1 Classification of Active Filters Active filters can be mainly of three configurations: (i) Butterworth, (ii) Chebyshev, and (iii) Bessel filters. (i) Butterworth filter: Butterworth filter is also called as maximally flat or flat–flat filter. These filters have a flat amplitudefrequency response in the pass band and have a monotonic drop (uniform slope) with increase in frequency in the stop band. The rolloff slope can be −20 dB/decade for the first order filter which is slow. The phaseshift of a Butterworth filter is nonlinear as a function of frequency (Figure 16.10). (ii) Chebyshev filter: Chebyshev filter is also called an equal ripple filter. It has a gain ripple in the lower frequency pass band, but it gives a sharper rolloff than Butterworth filter in the stop band. A Chebyshev filter is used where very sharp rolloff is required. Chebyschev
0 Butterworth A dB Bessel f
Figure 16.10 Frequency response of three types of filters
Active Filters
829
(iii) Bessel filter: The Bessel filter has a very linear phase response but a fairly gentle skirt slope. It is a minimal phase shift filter even though its cutoff characteristics are not very sharp. It is well suited for pulse applications.
16.3.2 Butterworth Filter The study hereunder is essentially confined to Butterworth filters as they are the maximally flat response filters. The rolloff can be made sharp with higher order filter design. These filters have Butterworth polynomial in the denominator of the transfer function of the filter. Butterworth polynomials and the coefficients of the Butterworth polynomials are shown in Tables 16.1 and 16.2, respectively. Table 16.1 Butterworth polynomials n, order of the polynomial
Polynomial (factored form)
1
( s + 1)
(s
2
2
)
+ 2 s +1
3
( s + 1) (s 2 + s + 1)
4
(s2 + 0.7654s + 1) (s2 + 1.8478s + 1)
5
(s + 1) (s2 + 0.6180s + 1) (s2 + 1.6180s + 1)
6
(s2 + 0.5176s + 1) (s2 + 1.4142s + 1) (s2 + 1.9319s + 1)
7
(s + 1) (s2 + 0.4450s + 1) (s2 + 1.2470s + 1) (s2 + 1.8019s + 1)
8
(s2 + 0.3986s + 1) (s2 + 1.1110s + 1) (s2 + 1.6630s + 1) (s2 + 1.9622s + 1)
Table 16.2 Coefficients of the Butterworth polynomials n
Polynomial
a1
1
s + a1
1
2
s 2 + a1s + a2
2
1
3
s 3 + a1s 2 + a2 s + a3
2
2
1
4
s 4 + a1s 3 + a2 s 2 + a3 s + a4
2.613
3.414
2.613
a2
a3
FirstOrder LowPass Butterworth Filter The firstorder lowpass Butterworth filter is shown in Figure 16.11(a).
a4
1
830
Electronic Devices and Circuits
R2 − R1 +
R + Vi
+
VA
Vo
C
−
Figure 16.11 (a) Firstorder lowpass Butterworth filter
1 Vi j ωC VA = Vi = 1 1+ jwCR R+ j ωC
From Figure 16.11(a),
(16.13)
The amplifier in Figure 16.11(a) is a noninverting amplifier. R Therefore, AF = 1 + 2 R1 Vo = VA AF =
AFVi 1 + jwCR
Vo AF = = Vi 1 + jwCR fH =
where
(16.14)
AF w 1+ j wH
AF
=
1+ j
f fH
1 2pRC
(16.15)
(16.16)
To ensure that the dc offset voltage is zero, bias compensation is provided. In the circuit in Figure 16.11(a), for dc the capacitor is open circuited and shorting Vi, the compensating resistance R is chosen as, R = R2R1 (Figure 16.11(b)). R2 R1 − +
+
R
Figure 16.11 (b) To determine the value of R
Vo
Active Filters
831
The design of the firstorder lowpass Butterworth filter is illustrated in the following examples. Example 16.1 Design a lowpass firstorder Butterworth filter with fH = 4 kHz and midband gain of 2. fH =
Solution:
1 2pRC
AF = 1 +
R2 =2 R1
Therefore, R2 = 1 ⇒R2 = R1 = 10 kΩ R1 R = R2R1 = 5 kΩ Therefore, C=
1 ≈ 0.008 µF 2 π × 5 × 103 × 4 × 103
Example 16.2 Design a noninverting active lowpass filter circuit that has a gain of 10 at low frequencies, a corner frequency of 1590 Hz, and an input resistance of 10 kΩ. Solution: The voltage gain of a noninverting operational amplifier is AF = 1 +
R2 = 10 R1
Choose R1 = 1 kΩ R2 = 9 ⇒R2 = 9R1 = 9 kΩ R1 Since the input resistance is given as 10 kΩ, R = 10 kΩ fH =
1 1 1 ⇒C = = = 10 nF 2pRC 2pfH R 2p × 1.59 × 103 × 10 × 103
Frequency Scaling A filter is usually designed for a specified cutoff frequency. However, sometimes it may become necessary to change the cutoff frequency. The procedure used to change the original cutoff frequency to a new cutoff frequency is called frequency scaling. For frequency scaling, instead of using a fixed resistance R, a potentiometer is used so that by varying
832
Electronic Devices and Circuits
R, the cutoff frequency can be changed (Figure 16.12).
R2 − R1 R +
+
+
VA
Vo
C
−
Vi
Figure 16.12 Frequency scaling
Second and HigherOrder Butterworth Filters In order to have a steep rolloff so that the response of the filter approximates the ideal filter response, higherorder filters are the answer. A secondorder lowpass filter will give a rolloff rate of −40 dB/decade. A secondorder filter can be derived by cascading two first–order, lowpass filters, which obviously will have to use two opamps. Secondorder, lowpass and highpass filters are best designed using a single opamp, as a Sallen–Key or voltagecontrolled voltage source (VCVS) topology.
Sallen–Key topology The general form of the Sallen–Key topology is shown in Figure 16.13. Y1, Y2, Y3, and Y4 are the admittances. It is required to find From Figure 16.13, the KCL equation at node A is
Vo . Vi
I1 − I 2 − I 3 = 0 or
(Vi −VA )Y1 = (VA −VB )Y2 + (VA −Vo )Y3 = 0 VY i 1 = VA (Y1 + Y2 + Y3 ) − VBY2 − VoY3
(16.17)
The KCL equation at node B is I2 − I4 = 0 or Therefore,
(VA −VB )Y2 − (VB − 0)Y4 = 0 VA =
VB =
VB (Y2 + Y4 ) Y2 Vo AF
(16.18)
(16.19)
Active Filters
833
where AF is the gain in the noninverting mode. AF = 1 +
R2 R1
(16.20)
Substituting Eqn. (16.19) in Eqn. (16.18), VA =
Vo (Y2 + Y4 )
(16.21)
AFY2
Substituting Eqs (16.19) and (16.21) in Eqn. (16.17), VY i 1 =
VY i 1 =
Vo (Y2 + Y4 ) AFY2
Vo (Y2 + Y4 ) (Y1 + Y2 + Y3 ) − VoY22 − VoY3 AFY2 AFY2
=
V
(Y1 +Y2 +Y3 ) − Ao Y2 −VoY3
(16.22)
F
Vo (Y2 + Y4 ) (Y1 + Y2 + Y3 ) −Y22 −Y3 AFY2 AFY2
Therefore, VY i 1 =
Vo YY 1 2 + Y4 (Y1 + Y2 + Y3 ) + Y3Y2 (1 − AF ) AFY2 Vo AFYY 1 2 = Vi YY + Y Y + Y + Y ( 1 2 4 1 2 3 ) + Y2Y3 (1 − AF )
(16.23)
R2 I1 +
−
A VA
R1 Y2
Y1
Vi I2 I3
B VB
Y4
Y3
+
+ Vo
I4
Figure 16.13 Sallen–Key topology
SecondOrder LowPass Butterworth Filter The secondorder, lowpass Sallen–Key filter is shown in Figure 16.14(a). Y1 = Y2 =
1 =G R
Y3 = Y4 = sC
834
Electronic Devices and Circuits
From Eqn. (16.23), H (s ) =
Vo AFG 2 = 2 Vi G + sC (2G + sC ) + GsC (1 − AF ) AFG 2 C2
=
G G2 3 − AF ) + 2 ( C C AF R 2C 2 = 1 1 3 − AF ) + 2 2 s2 + s ( RC RC s2 + s
(16.24)
R2 − R1
+ Vi
R
+
+ Vo
R C C
Figure 16.14 (a) Sallen–Key secondorder, lowpass Butterworth filter
The transfer function of a secondorder, lowpass system can, in general, be written as follows: H (s) =
AF ω o2 s + ζω o s + ω o2 2
(16.25)
where w o = w H , is the cutoff frequency and ζ is the damping factor. Comparing Eqs (16.24) and (16.25), 1 C R2 1 wo = RC
w o2 = or
zw o = Therefore,
(3 − AF ) or CR
2
(3 − AF ) z = RC CR
z = 3 − AF For the second order Butterworth polynomial is s 2 + 2 s + 1 3 − AF = 2
(16.26)
Active Filters
835
Therefore, AF = 3 − 2 = 1.585 But AF = 1 +
R2 R = 1.585 or 2 = 0.585 R1 R1
To Plot the Frequency Response Equation (16.25) can be written as follows: H (s ) =
Put s = jw , then
AF s zs + +1 w o2 w o
(16.27)
2
H ( jw ) =
AF w2 w − 2 + jz +1 wo wo
For a Butterworth filter, z = 2. Therefore, AF AF AF H ( jw ) = = = 2 2 4 2 w2 w2 w w 1 + − 1 2 1 + + w w 2 w 2 w o o o o When expressed in dB, 20 log10 H ( jw ) = 20 log10
For the n th order filter,
H ( jw ) =
AF w 1+ wo
(16.29) (16.30)
4
AF w 1+ wo
(16.28)
2n
(16.31)
Example 16.3 (i) Design a secondorder, Sallen–Key lowpass Butterworth filter having fH = 2 kHz, (ii) repeat the design for minimum dc offset, and (iii) plot the frequency response. 1 Solution: (i) fH = 2pRC Choose C = 0.01 µF. Therefore, 1 1 R= = = 7.96 kΩ 2pfHC 2p × 2 × 103 × 0.01 × 10 −6 R AF = 3 − 2 = 1.585 1.585 = 1 + 2 Þ R2 = 0.585 × R1 R1 Choose R1 = 10 kΩ. Then, R2 = 0.585 × 10 = 5.85 kΩ.
836
Electronic Devices and Circuits
(ii) Consider R1 = 10 kΩ and R2 = 5.85 kΩ. Under dc conditions the capacitors are open circuits and shorting Vi, 2R is the resistance from the noninverting terminal to ground (Figure 16.14(b)).
R2 R1 − +
+ Vo
R R
Figure 16.14 (b) Bias compensation
Therefore, for minimum dc offset, 2R = R1R2 =
10 × 5.85 = 3.69 kΩ , R = 1.85 kΩ. 10 + 5.85
Therefore, C=
1 1 = = 0.043 µF 2pfHC 2 π × 2 × 103 × 1.85 × 103
(iii)Using Eqn. (16.30), 20 log10 H ( jw ) = 20 log10
AF f 1+ fo
4
= 20 log10
1.585 f 1+ 2 × 103
4
For plotting the frequency response, the frequency range is taken from 0.1 fo (a decade below fo = 200 Hz) and 10 fo (a decade above fo = 20 kHz). See Table 16.3. Table 16.3 Variation of gain with frequency Frequency (Hz)
Gain in dB
200
4
500
3.98
1000
3.73
2000
1.00
4000
−8.4
8000
−20.08
16000
−31.06
20000
−35.99
Active Filters
837
The frequency response is plotted in Figure 16.15. Gain in dB 4 1
−40 dB/decade
−35.99 200
Hz 2000
20000
f
Figure 16.15 Frequency vs gain curve
HigherOrder LowPass Filters A firstorder filter provides a −20 dB/decade rolloff and a secondorder filter provides a −40 dB/decade rolloff in the stop band. Each increase in the order of the filter produces an additional rolloff of −20 dB/decade. For the nthorder filter, the rolloff rate in the stop band is ( n × − 20 dB/decade ) . Consequently, the response of the higher order filters corresponds to the response of the ideal filter. The transfer function of the thirdorder filter is of the following type: A AF H ( s ) = 2 F1 s + z 1s + 1 s +1 The fourthorder filter is of the following type: AF1 AF2 2 s + z 1s + 1 s + z 2 s + 1
H (s ) =
2
The fifth orderfilter is of the following type: H (s ) =
AF1 AF 2 AF 2 s + z 1s + 1 s + z 2 s + 1 s + 1 2
The rolloff rate for different values of n is shown in Figure 16.16. Gain in dB 0
n=1
−20 db/decade
n=2 6
5
4
n=3 −40 −60 −80
−120 −100
−120 0.2
2
20
200
Figure 16.16 Rolloff rate in the stop band for different values of n
f
kHZ
838
Electronic Devices and Circuits
Example 16.4 Design a lowpass Butterworth filter with a corner frequency of 2 kHz and a rolloff rate in the stop band as −80 dB/decade. Solution: A rolloff rate in the stop band as −80 dB/decade is derived by a fourthorder filter. The tranfer function of the fourthorder filter is
H (s ) =
AF1 AF2 AF1 AF2 = s 2 + z 1s + 1 s 2 + z 2 s + 1 s 2 + 0.7654 s + 1 s 2 + 1.8478s + 1
For the Butterworth filter, z 1 = 0.765 and z 2 = 1.848 AF1 = 3 − z 1 = 3 − 0.765 = 2.235 = 1 +
R2 ⇒R2 = 1.235R1 R1
Choose R1 = 10 kΩ. Then R2 = 1.235R1 = 12.35 kΩ AF2 = 3 − z 2 = 3 − 1.848 = 1.152 = 1 +
R4 ⇒ R4 = 0.152R3 R3
Choose R3 = 10 kΩ. Then R4 = 0.152R3 = 1.52 kΩ Choose C = 0.01 µF Therefore, R=
1 1 = = 7.96 kΩ 3 2pfHC 2p × 2 × 10 × 0.01 × 10 −6
The designed circuit is shown in Figure 16.17. 1.52 kΩ 12.35 kΩ R4 R1 + Vi
R C
−
10 kΩ
8 kΩ R 8 kΩ C 0.01 µF
R3
R2
0.01 µF
− AF1 +
8 kΩ
8 kΩ
10 kΩ +
R
R C
C 0.01 µF
Figure 16.17 Designed circuit
0.01 µF
AF2
+ Vo
Active Filters
839
FirstOrder HighPass Butterworth Filter The firstorder, highpass Butterworth filter is shown in Figure 16.18. R2 − R1 + Vi
+
+
VA
Vo
R
−
C
Figure 16.18 Firstorder, highpass Butterworth filter
From Figure 16.18, VA = Vi
R 1 R+ j wC
= Vi
jwCR 1+ jwCR
The amplifier in Figure 16.18 is a noninverting amplifier. R AF = 1 + 2 R1 Therefore,
(16.32)
(16.33)
jwCR 1 + jwCR w f j j Vo wL fL jwCR = H ( jw ) = AF = AF = AF w f Vi 1 + jwCR 1+ j 1+ j wL fL Vo = VA AF = AFVi
fL =
where
1 2pCR
H ( jw ) = AF
From Eqn. (16.36), (i) If f > fL, then H ( jw ) = AF
(16.34)
(16.35) f fL
f 1+ fL
(16.36) 2
840
Electronic Devices and Circuits
The response of the filter is shown in Figure 16.19. H(jw) AF 0.707AF
Pass band Stop band
fL
0
f
Figure 16.19 Response of the firstorder, highpass Butterworth filter
The design of the firstorder, highpass Butterworth filter is illustrated in the following example. Example 16.5 Design a firstorder, highpass Butterworth filter to have a cutoff frequency of 2 kHz and passband gain of 2. Plot its frequency response. Solution: Choose C = 0.01 µF. R =
1 1 = = 7.96 kΩ 2pCfL 2p × 0.01 × 10 −6 × 2 × 103 AF = 1 +
Therefore,
R2 =2 R1
R2 = R1 Choose R2 = R1 = 10 kΩ. Table 16.4 shows variation of gain with frequency.
20 log10
f fL H ( jw ) = 20 log10 AF 2 f 1+ fL
Table 16.4 Variation of gain with frequency. Frequency (Hz) 200 500 1000 2000 4000 8000 16000 20000
Gain in dB −13.98 −6.285 −0.983 3.00 5.06 5.75 5.95 6.02
(16.37)
Active Filters
841
SecondOrder, HighPass Butterworth Filter The secondorder, highpass Butterworth filter is shown in Figure 16.20. R2 R1 −
Y1
Y2
+ Vi
C
+
+ Vo
C Y3
Y4
R
R
Figure 16.20 Secondorder, highpass Butterworth filter
From Eqn. (16.23), Vo AFYY 1 2 = Vi YY + Y Y + Y + Y 1 2 4( 1 2 3 ) + Y2Y3 (1 − AF ) From Figure 16.20, 1 =G R Vo AF s 2C 2 = H (s ) = 1 1 sC Vi s 2C 2 + sC + sC + + (1 − AF ) R R R Y1 = Y2 = sC , Y3 = Y4 =
=
AF s 2C 2 AF s 2 = sC s 1 1 s 2C 2 + 3 − AF ) + 2 s 2 + 3 − AF ) + 2 2 ( ( R RC R C R H (s ) = =
(16.38)
AF s 2 s 2 + s (3 − AF )w o + w o2 AF 1 + (3 − AF )
wo wo + s s
2
For the secondorder, highpass Butterworth filter z 1 = 2 and w o = w L. Therefore, 3 − AF = 2 or A F = 3 − 2 = 1.585 AF = 1 +
R2 = 1.585 R1
R2 = 0.585R1
(16.39)
842
Electronic Devices and Circuits
From Eqn. (16.39), AF
H ( jw ) =
2
wo wo jw − jz w + 1 AF
H ( jw ) =
2
w o2 wo 1 − w 2 + 2 w
H ( jw ) =
In general,
AF f 1+ o f
4
=
AF
= 2
w 1+ o w
AF f 1+ L f
f 1+ L f
AF f 1+ o f
4
(16.40) 4
AF
H ( jw ) =
4
=
(16.41) 2n
Example 16.6 Design a highpass Butterworth filter, Figure 16.20, to have a cutoff frequency of 2 kHz and a rolloff rate of −40 dB/decade. Solution: AF = 1 +
R2 = 1.585, R2 = 0.585R1 R1
Choose R1 = 10 kΩ, R2 = 5.85 kΩ 2R = R1R2 =
R1R2 10 × 5.85 = = 3.69 kΩ R1 + R2 10 + 5.85
Therefore, R = 1.85 kΩ
fL =
1 2pCR
Hence, C=
1 1 = = 0.043 µF 2 πfL R 2 π × 2 × 103 × 1.85 × 103
16.3.3 BandPass Filter Bandpass filters can be of two types: (i) wide bandpass filter and (ii) narrow bandpass filter.
Active Filters
843
Wide BandPass Filter In wide bandpass filter, Q < 10. The response is typically as shown in Figure 16.21. Stop band
Stop band
AF 0.707 AF A
H(jw) Bandwidth
0
fL
f0
fH
f
Figure 16.21 Typical response of the wide bandpass filter
A wide bandpass filter is derived by cascading a highpass filter and a lowpass filter. If the desired rolloff rate is −20 dB/decade, then firstorder filters are connected in tandem and for a rolloff rate of −40 dB/decade, secondorder filters are connected in tandem. Q, the quality factor is Q=
fo fo = BW fH − fL
(16.42)
A bandpass filter with a rolloff rate of −20 dB/decade is shown in Figure 16.22.
R3
R3
R
R − A1 +
+ Vi
−
A2
+ R1
+ Vo
C2
R2 V01
High pass ﬁlter
C1
Low pass ﬁlter
Figure 16.22 Firstorder, wide bandpass Butterworth filter
−
844
Electronic Devices and Circuits
From Eqn. (16.36),
f fL
H 2 ( jw ) = AF1
f 1+ fH
Therefore, AF1
H ( jw ) = H 2 ( jw ) × H1 ( jw ) =
H ( jw ) =
or
and
2
AF2
H1 ( jw ) =
And using Eqn. (16.31),
(16.43)
f 1+ fL
(16.44)
2
f fL
f 1+ fL
AF2 2
f 1+ fH
f AF fL f 2 f 2 1 + 1 + fL fH
AF = AF1AF2
2
(16.45)
(16.46)
Example 16.7 Design a wide bandpass Butterworth filter to have a stop band rolloff of −20 dB/decade, midband gain of 4 and fL = 2 kHz , and fH = 4 kHz . Determine Q. Plot the response. Solution: (i) Highpass filter Choose C2 = 0.01 µF ⇒ R2 =
1 1 = = 7.96 kΩ 2pC2 fL 2p × 0.01 × 10 −6 × 2 × 103 AF2 = 1 +
Therefore,
R3 =2 R
R3 =R Choose R3 =R = 10 kΩ. (ii) Lowpass filter Choose C1 = 0.01 µF ⇒ R1 =
1 1 = = 3.98 kΩ 2pC1 fH 2p × 0.01 × 10 −6 × 4 × 103 AF2 = 1 +
R3 =2 R
Active Filters
845
Therefore, R3 =R Choose R3 = R = 10 kΩ fH − fL = 4 − 2 = 2 kHz ⇒ fo = Q=
fH fL = 4 × 2 = 2.83 kHz
fo 2.83 = = 1.42 ⇒ Q < 10 fH − f L 2
From Eqn. (16.45), H ( jw ) =
f 4 2000 f 2 f 2 1 + 1 + 2000 4000
Frequency (Hz)
Gain in dB
100
−13.98
200
−7.96
500
−0.33
1000
1.23
2000
8.06
3000
8.53
4000
8.06
8000
4.79
16000
−0.33
20000
−2.15
The band pass filter in Figure 16.22 uses two opamps.
Multiple Feedback Topology A filter configuration in which a single Opamp is used is called infinite gain multiple feedback (IGMF) configuration (Figure 16.23). LPF, HPF as well as BPF filters can be implemented using this configuration also. IGMF topology is used to have high Qs and high gain. From Figure 16.23, assuming a virtual ground at the input, the KCL equation at node A is I1 = I 2 + I 3 + I 4 or
(Vi −VA )Y1 = VAY2 + VAY4 + (VA −Vo )Y3 Vi Y1 = VA (Y1 + Y2 + Y3 + Y4 ) − VoY3
The KCL equation at node B is I 2 + I5 = 0
(16.47)
846
Electronic Devices and Circuits
I3
Y5
Y3 I2
I1 +
I5
A
Y1
Y2
VA
Vi
B − VB
+ Vo
+ I4
Y4
Figure 16.23 IGMF filter configuration
VAY2 + VoY5 = 0
or
VA =
−Y5 Vo Y2
(16.48)
Substituting Eqn. (16.48) in Eqn. (16.47), Vi Y1 = Vo
−Y5 (Y1 +Y2 +Y3 +Y4 ) −VoY3 Y2
Y5 (Y1 + Y2 + Y3 + Y4 ) + Y2Y3 Vi Y1 = −Vo Y2 Vo −YY 1 2 = Vi Y5 (Y1 + Y2 + Y3 + Y4 ) + Y2Y3
(16.49)
IGMF Narrow BandPass Filter The IGMF narrow band pass filter is shown in Figure 16.24. For the circuit in Figure 16.24, 1 1 1 Y1 = = G1, Y2 = sC2 , Y3 = sC3, Y4 = = G4, Y5 = = G5 R1 R4 R5
R5
C3 +
(16.50)
C2
R1
−
Vi + R4
Figure 16.24 IGMF narrow bandpass filter
+ Vo
Active Filters
847
From Eqs (16.49) and (16.50), H (s) =
− sC2G1 G5 (G1 + G4 ) + G5 s (C2 + C3 ) + s 2C2C3
−G1 G (G + G4 ) G5 (C2 + C3 ) (16.51) + sC3 + 5 1 C2 sC2 The transfer function of an RLC parallel resonant circuit in Figure 16.25, driven by a current source G ′Vi is shown in Figure 16.26. =
+ C
L G
G′Vi
Vo −
Figure 16.25 RLC circuit 1 0.707
fL f0
fH
Figure 16.26 Frequency response
The response of the RLC circuit in Figure 16.25 is given as follows: H (s ) =
−G ′ 1 sC + +G sL
(16.52)
Comparing Eqs (16.51) and (16.52), G ′ = G1 and C = C3
(16.53)
1 G5 (G1 + G4 ) = sL sC2 L= and G=
C2 G5 (G1 + G4 )
(16.54)
G5 (C2 + C3 ) C2
(16.55)
848
Electronic Devices and Circuits
The resonant frequency of the RLCtuned circuit is 1 LC
w o2 =
(16.56)
Therefore, using Eqs (16.53) and (16.54), w o2 for the narrow band pass filter is G (G + G4 ) 1 = 5 1 LC C2C3
w o2 =
(16.57)
From Eqs (16.52), (16.53), and (16.55), the gain at resonance is Ao =
−G1C2 R G C2 C2 −G ′ −G1 = = =− 5 =− 1 G G G5 (C2 + C3 ) G5 C2 + C3 R1 C2 + C3
(16.58)
If C2 = C3, Eqs (16.58) and (16.57) reduce to Ao = −
R5 2R1
(16.59)
G5 (G1 + G4 )
wo =
C
(16.60)
Q at resonance is Qo = w oCR = Using Eqn. (16.55), Qo =
w oC3 G
w oC3 w oC3C2 2pfoC3C2 = = G G5 (C2 + C3 ) G5 (C2 + C3 )
Bandwidth =
(16.61)
fo G5 (C2 + C3 ) = Qo 2pC2C3
(16.62)
G5 × 2C 1 = 2 pR5C 2pC
(16.63)
If C2 = C3, Eqn. (16.62) reduces to BW =
Example 16.8 Design an IGMF narrow band pass filter, Figure 16.24, to have fo = 2 kHz, Qo = 10 and gain of 20 at resonance. Solution: Choose C2 = C3 = C = 0.01 µF Qo =
2pfoC3C2 2pfoC 2 = = pfo R5C G5 (C2 + C3 ) 2G5C
Active Filters
R5 =
Qo 10 = = 159 kΩ 3 πfoC π × 2 × 10 × 0.01 × 10 −6
Ao =
R5 R 159 ⇒R1 = 5 = = 3.975 kΩ 2R1 2 Ao 2 × 20
849
(Cw o )2 = G5 (G1 + G4 )
From Eqn (16.60),
2
(G1 + G4 ) = R5 (Cw o )2 = 159 × 103 × (0.01 × 10 −6 × 2π × 2 × 103 )
= 2.51 × 10 −3
1 1 + = 2.51 × 10 −3 R4 R1 1 1 = 2.51 × 10 −3 − = 10 −3 (2.51 − 0.251) = 2.259 × 10 −3 R4 3.975 × 103 R4 =
1 = 442.7 Ω. 2.259 × 10 −3
The typical response of the narrow bandpass filter for different values of Q is shown in Figure 16.27. 0 Q=5 A0 in dB
10
0.1
1.0
10
f/f0
Figure 16.27 Response of the narrow bandpass filter for different Q
16.3.4 BandRejection Filter Band rejection (also called band elimination or band stop) filters can be of two types: (i) wide bandrejection filter and (ii) narrow bandrejection filter.
850
Electronic Devices and Circuits
Wide BandRejection Filter A wide bandrejection filter consists of a HPF, an LPF and a summing amplifier as shown in Figure 16.28. fL of the HPF should be greater than fH of the LPF. R3 R − A + 1 HPF C2
R4
Summing ampliﬁer R4
R2
− A + 3 RC
R3
+ Vi −
R R1
R4
− A + 2 LPF
+ Vo −
RC = R4/3
C1
Figure 16.28 Wide bandrejection filter
The response of the filter is shown in Figure 16.29.
AF Pass band
0
Pass band
Stop band
fH
f0
fL
Figure 16.29 Response of the bandrejection filter
fo =
f L fH
Example 16.9 Design a wide bandrejection filter to have fL = 4 kHz and fH = 2 kHz. The pass band gain is required to be 2. Solution: Highpass filter: Choose C2 = 0.01 µF. Lowpass filter:
R2 =
1 1 = = 3.98 kΩ 2pC2 fL 2p × 0.01 × 10 −6 × 4 × 103
Active Filters
Choose C1 = 0.01 µF.
R1 =
851
1 1 = = 7.96 kΩ 2pC1 fH 2p × 0.01 × 10 −6 × 2 × 103
AF = 1 +
R3 =2 R
Therefore, R3 = R Choose R3 = R = 10 kΩ fH − fL = 4 − 2 = 2 kHz
fH fL = 4 × 2 = 2.83 kHz
fo =
Choose R4 = 12 kΩ. Therefore, RC =
R4 12 = = 4 kΩ 3 3
Narrow BandReject Filter A narrow band reject filter is also called a notch filter. A simple method of deriving a narrow band reject filter is to use a narrow band pass filter and a subtracting amplifier, as shown in Figure 16.30. Narrow BPF Vi
Summer f + −
V0
f0
fL f0 fH
A0
Figure 16.30 Notch filter
But in practice, the expression for the gain of the narrow band pass filter (Eqn. 16.58) shows that the pass band signal gets inverted. As such, a summing amplifier is used in place of a subtracting amplifier. Further, as the BPF has a gain of Ao, the input is also required to be increased by a factor Ao .
852
Electronic Devices and Circuits
A notch filter is usually implemented using a twinT network as shown in Figure 16.31.
C
I1
VA
C
I2
−
A
Buffer
I3
Vi
VD = Vo
R/2
+
Vo RL
D R
R
VB B
I4
I5
2C I6
Figure 16.31 Notch filter using a twinT network
The KCL equation at node A is I1 + I 2 + I 3 = 0 Therefore,
(Vi −VA ) sC + (Vo −VA ) sC −VA (2G ) = 0
(16.64)
sC (Vi + Vo ) = 2VA ( sC + G ) Therefore,
VA =
sC (Vi + Vo ) 2 ( sC + G )
(16.65)
The KCL equation at node B is I 4 + I5 + I6 = 0 Therefore,
(Vi −VB )G + (Vo −VB )G −VB (2sC ) = 0
(16.66)
G (Vi + Vo ) = 2VB ( sC + G ) Therefore,
VB =
G (Vi + Vo ) 2 ( sC + G )
The KCL equation at node D is I 2 + I5 = 0
(16.67)
Active Filters
853
Therefore,
(Vo −VA ) sC + (Vo −VB )G = 0 VA sC + VBG = Vo ( sC + G )
(16.68)
Substituting Eqs (16.65) and (16.67) in Eqn. (16.68), sC (Vi + Vo ) 2 ( sC + G )
× sC +
G (Vi + Vo ) 2 ( sC + G )
× G = Vo ( sC + G ) 2
s 2C 2 (Vi + Vo ) + G 2 (Vi + Vo ) = 2Vo ( sC + G )
(s C 2
2
(
)
2 + G 2 Vi = 2 ( sC + G ) − s 2C 2 + G 2 Vo
)
(
)
= 2 s 2C 2 + 2G 2 + 4 sCG − s 2C 2 + G 2 Vo = s 2C 2 + 4 sCG +G 2 Vo Therefore,
G s + C
2
2
Vo s 2C 2 + G 2 = H (s ) = 2 2 = Vi s C + 4 sCG +G 2
4 sG G s2 + + C C
(16.69) 2
Substituting s = jw , then Eqn. (16.69) is H ( jw ) =
where w o =
G 1 = C RC
w o2 − w 2 w 2 − w o2 = 2 2 w − w + 4 jww o w − w o2 − 4 jww o
or
(16.70)
2 o
fo =
1 2pRC
(16.71)
Dividing Eqn.16.70 by w 2 − w 20 H ( jw ) =
and
H ( jw ) =
1 ww 0 1− j4 2 w − w 02 1 ww 0 2 1 + ±4 2 w − w 20
(16.72)
854
Electronic Devices and Circuits
At the 3 db frequency, H ( jw ) =
1 2
. Therefore, from Eqn. (16.72), ±4
ww 0 =1 w 2 − w 20
w 2 − w o2 = ±4ww 0
w 2 − ±4ww 0 − w 20 = 0
or 2
w w w ± 4 w − 1 = 0 o o
or
±4 ± 16 − 4 × 1 × −1 w = wo 2 ×1
Therefore,
( =(
fH = fL
and
) 5 − 2) f
5 + 2 fo = 4.24 fo
(16.73)
= 0.24 fo
(16.74)
o
Bandwidth = BW = fH − fL = 4 fo
(16.75)
The response of the notch filter is shown in Figure 16.32.
BW
1.0
0.707
f L f0
fH
Figure 16.32 Response of the notch filter
Example 16.10 Design a notch filter to have fo = 50 Hz. Use C = 0.05 µF. Calculate fH, fL, and BW. Solution: fo =
1 2pRC ∴
R=
1 1 = = 63.69 kΩ 2 p foC 2 × p × 50 × 0.05 × 10 −6 fH = 4.24 fo = 4.24 × 50 = 212 Hz
and
fL = 0.24 fo = 0.24 × 50 = 12 Hz Bandwidth = BW = fH − fL = 212 − 12 = 200 Hz
Active Filters
855
16.3.5 Allpass Filter An allpass filter has a constant gain in the entire frequency range, and a phase response that changes linearly with frequency (Figure 16.33). R1
R1
VA Vi
R
− +
Vo
C
Figure 16.33 Allpass filter
Using the superposition theorem, grounding the input to the noninverting input terminal, the amplifier is an inverting amplifier. Then −R1 (16.76) Vo1 = Vi = −Vi R1 Grounding the input to the inverting input terminal, the amplifier is a noninverting amplifier. Then 1 Vi jwC (16.77) VA = Vi = 1 1 + jwCR R+ jwC R 1 Vo2 = VA 1 + 1 = 2VA = 2Vi 1 + jwCR R1 Vo = Vo1 + Vo2 = −Vi + 2Vi
(16.78)
Vi 2 − (1 + jwCR ) 1 1 − jwCR = = Vi 1 + jwCR 1 + jwCR 1 + jwCR Vo 1 − jwCR = H ( jw ) = Vi 1 + jwCR 2
H ( jw ) =
The phase shift is
1 + (wCR )
2
1 + (wCR )
=1
wCR = −2 tan −1 (2pfCR ) f = −2 tan −1 1
(16.79)
(16.80)
From Eqs (16.79) and (16.80), it can be noted that the filter has a gain of 1, but the phase shift changes as a function of frequency. It is known that when a signal is transmitted over a transmission line, its phase can change. An allpass filter is used to compensate for such phase changes. As such, all passfilters are also called as delay equalizers and phase correctors.
856
Electronic Devices and Circuits
Example 16.11 For the allpass filter if the signal has a frequency of 1 kHz and uses a C of 0.05 µF, find f when (i) R = 1.6 kΩ and (ii) R = 3.2 kΩ. Solution: (i) f = −2 tan −1 (2pfCR )
(
= −2 tan −1 2p × 1 × 103 × 0.05 × 10 −6 × 1.6 × 103
)
= −2 tan −1 ( 0.5024 ) = −53.35°
(
(ii) f = −2 tan −1 2p × 1 × 103 × 0.05 × 10 −6 × 3.2 × 103
)
= −2 tan −1 (1.005) = −90°
16.3.6 Switched Capacitor Filter A switched capacitor is an element used for discrete time signal processing. It works by moving charges into and out of capacitors by using switches that are controlled by nonoverlapping signals, which means that not all switches are closed simultaneously. Filters implemented with these elements are termed switchedcapacitor filters, and depend only on the ratios between capacitances. Switched capacitors are suitable for use in integrated circuits to construct resistors and capacitors accurately and economically.
SC Resistor Simulation The simplest switched capacitor (SC) circuit is the switched capacitor resistor, made of one capacitor C and two switches S1 and S2 controlled by two phase nonoverlapping 1 clock pulses f1 and f 2 . f1 and f 2 connect the capacitor with a given frequency f = , T alternately, to the input and the output (Figure 16.34).
V1
f1 0
S2
S1
T = 1/f
1
f2
f1
1
V2
C
f2 0
(a) Simple switched capacitor resistor
(b) Nonoverlapping clock waveforms
R V1
V2 IR
(c) Resistor simulation
Figure 16.34 Switchedcapacitor resistor
Active Filters
857
When S1 is closed, the charge on C at steady state is q1 = CV1 When S2 is closed, the charge on C at steady state is q2 = CV2 Assuming V1 > V2, the charge ∆q transferred is ∆q = q1 − q2 = C (V1 − V2 ) = CV
(16.81)
As charge ∆q is transferred at a rate f, the rate of transfer of charge per unit time is I = ∆qf =
∆q T
Therefore, the average current flowing is I=
CV T
(16.82)
From Figure 16.34(c) and using Eqn. (16.81), R=
V 1 V T = = = V C C fC I T
(16.83)
Thus the switched capacitor behaves like a lossless resistor whose value depends on capacitance C and switching frequency f. The SC resistor can replace a simple resistor in an integrated circuit, since it is easier to fabricate reliably with a wide range of values. Also its value can be adjusted by changing the switching frequency f. It may be said that it can be considered as a programmable resistance.
Switched Capacitor Integrator An integrator using an opamp as an inverting amplifier is shown in Figure 16.35. Cf
R −
Vs
Vo +
Figure 16.35 Opamp inverting integrator
Its output Vo in the sdomain is given as follows: Vo ( s ) =
−Vs ( s ) RCf s
(16.84)
858
Electronic Devices and Circuits
Now, R can be replaced by a switched capacitor (Figure 16.36). Cf
f1
f2 −
Vs
Vo C
+
Figure 16.36 Switched capacitor integrator
Using Eqs (16.83) and (16.84), Vo ( s ) =
−Vs ( s ) 1 fC Cf s
C V (s ) = −f s Cf s
(16.85)
The switches in Figure 16.36 can, in fact, be replaced by MOS devices (Figure 16.37). Consider the secondorder, lowpass filter shown in Figure 16.38 and its transfer function is given as follows: 1 Vo ( s ) R1R3C2C4 w o2 (16.86) = = 1 1 wo Vi ( s ) 2 2 2 s + s+ s + s + wo R3C4 R1R3C2C4 Q The circuit in Figure 16.38 can be converted into a switched capacitor filter using Eqn. (16.83). See Figure 16.39. 1 1 and R3 = R1 = fC1 fC3 (16.87)
f1
Cf
f2
−
Vs
Vo C
+
Figure 16.37 Switches in Figure 16.36 replaced by MOS devices
Active Filters
859
R1
C2 −
Vs R1
Vo R3
+
C4
Figure 16.38 Secondorder, lowpass filter
C1
C2 −
Vs
Vo C1
+ C3
C4
Figure 16.39 Switched capacitor filter
Substituting the values in Eqn. (16.87) in Eqn. (16.86), 1 1 1 fC fC C2C4 Vo ( s ) 1 3 = 1 1 Vi ( s ) s2 + s+ 1 1 1 fC fC C2C4 fC C4 3 1 3 C1C3 2 f w o2 C2C4 = = w C CC s 2 + 3 fs + 1 3 f 2 s 2 + o s + w o2 C4 C2C4 Q
(16.88)
860
Electronic Devices and Circuits
Example 16.12 Design a lowpass filter shown in Figure 16.39 with fo = 15.9 kHz and Q = 5. The amplifier has a unity dc gain. Solution: From Eqn. (16.88), Vo ( s ) = Vi ( s )
w o2 1010 = 2 w s + 20000 s + 1010 s 2 + o s + w o2 Q
C1C3 2 f = 1010 C2C4
C3 f = 20000 C4
and
Choose f = 10 fo = 159 kHz C3 f = 20000 C4 C1C3 2 f = 1010 C2C4
C3 20000 = = 0.126 C4 159000 C1 1010 1010 = = = 31.45 C 2 C3 20000 × 15.9 × 103 f×f C4
and
Let C2 = 1 pF and C4 = 10 pF, then C1 = 31.45C2 = 31.45 × 1 = 31.45 pF C3 = 0.126C4 = 0.126 × 10 = 1.26 pF
Additional Solved Examples Example 16.13 For a firstorder, unitygain lowpass Butterworth filter with fH = 1 kHz and C = 0.1 µF. Find R. Solution: For the firstorder, lowpass Butterworth filter Vo = Vi where fH =
AF f 1+ j fH
=
1 1+ j
f fH
1 2pRC R=
1 1 = = 1.59 kΩ 2 πfHC 2 π × 1 × 103 × 0.1 × 10 −6
Active Filters
861
Example 16.14 Design a lowpass Butterworth filter with a corner frequency of 2 kHz and a rolloff rate in the stop band as −100 dB/decade and the pass band gain of 2.575. Solution: A rolloff rate in the stop band as −100 dB/decade is derived by a fifthorder filter. The tranfer function of the fifthorder filter is H (s ) =
=
AF1 AF2 AF s 2 + z 1s + 1 s 2 + z 2 s + 1 s + 1
AF AF1 AF2 s 2 + 0.7654 s + 1 s 2 + 1.8478s + 1 s +1
For the Butterworth filter, z 1 = 0.765 and z 2 = 1.848, AF1 = 3 − z 1 = 3 − 0.765 = 2.235 = 1 +
R2 ⇒R2 = 1.235R1 R1
Choose R1 = 10 kΩ. Then R2 = 1.235R1 = 12.35 kΩ AF2 = 3 − z 2 = 3 − 1.848 = 1.152 = 1 +
R4 ⇒R4 = 0.152R3 R3
Choose R3 = 10 kΩ. Then R4 = 0.152R3 = 1.52 kΩ AF1AF2 = 2.235 × 1.152 = 2.575 For the the overall pass band gain to be 2.575, the firstorder filter will have to have AF = 1.� Choose C = 0.01 µF Therefore, R=
1 1 = = 7.96 kΩ ≈ 8 kΩ 3 −6 2pfHC 2p × 2 × 10 × 0.01 × 10
The designed circuit is shown in Figure 16.40. 1.52 kΩ 12.35 kΩ R4
R2
R3
R1 + Vi
10 kΩ
8 kΩ R
R 8 kΩ C C
− AF1 +
8 kΩ
− +
AF2
− 8 kΩ
R
R
C 0.01 µF C
0.01 µF
10 kΩ
8 kΩ
0.01 µF
0.01 µF
Figure 16.40 Designed circuit
+
AF2
R C
0.01 µF
+ Vi
862
Electronic Devices and Circuits
Example 16.15 Design a first order band reject filter, Figure 16.28, to have a lower cutoff frequency of 2000 Hz and a higher cutoff frequency of 400 kHz. Assume pass band gain as 2. Solution: Highpass filter: 1 1 = Choose C2 = 0.01 µF. R2 = = 7.96 kΩ 2pC2 fL 2p × 0.01 × 10 −6 × 2 × 103 AF2 = 1 +
R3 =2 R
Therefore, R3 = R Choose R3 = R = 10 kΩ Lowpass filter: Choose C1 = 0.01 µF.
R1 =
1 1 = = 39.81 kΩ 2pC1 fH 2p × 0.01 × 10 −6 × 400
AF2 = 1 + ∴
R3 =2 R
R3 = R
Choose R3 = R = 10 kΩ
Summary • Filters are frequency selective electronic circuits that pass only the desired band of frequencies from the input to the output and reject or attenuate the unwanted frequencies. • Passive filters use only passive circuit components such as resistors, capacitors, and inductors; whereas, active filters use active circuit components such as transistors and opamps in addition to the passive circuit components. • Butterworth filter is also called as maximally flat or flat–flat filter. These filters have a flat amplitudefrequency response up to the cutoff frequency and have a monotonic drop in gain with increase in frequency in the cutoff region. • In order to have a steep rolloff so that the response of the filter approximates the ideal filter response, higher order filters are used. A secondorder, lowpass filter will give a rolloff rate of −40 dB/decade. In general, an nth order filter will give a rolloff rate of −20n dB/decade . • Secondorder, lowpass and highpass filters are best designed using a single opamp, as a Sallen–Key or voltagecontrolled voltage source (VCVS) topology. • A filter configuration in which a single opamp is used to derive a bandpass filter is called infinite gain multiple feedback (IGMF) configuration. • An allpass filter has a constant gain in the entire frequency range, and a phaseresponse that changes linearly with frequency. • The switched capacitor behaves like a lossless resistor whose value depends on capacitance C and switching frequency f. The SC resistor can replace a simple resistor in an integrated circuit, since it is easier to fabricate reliably with a wide range of values.
Active Filters
863
multiple ChoiCe QueStionS 1. Which one of the following filters significantly attenuates all frequencies below fc and passes all frequencies above fc ? (a) Low pass (b) High pass (c) Band pass (d) Band stop 2. Which one of the following filters rejects all frequencies within a specified band and passes all those outside this band? (a) Low pass (b) High pass (c) Band pass (d) Band stop 3. When a rapid rolloff in the stop band is required, the type of filter that is preferred is (a) Butterworth (b) Chebyshev (c) Bessel (d) Elliptical 4. In which filter, the bandwidth equals the cutoff frequency? (a) Low pass (b) High pass (c) Band pass (d) Band stop 5. The cutoff frequency is the frequency at which the filter response drops by ________ from the pass band. (a) −3 dB (b) −6 dB (c) −20 dB (d) 0 dB 6. The filter with a very flat response in the passband and a rolloff rate of –20 dB/decade/pole in the stop band is ________ (a) Butterworth (b) Chebyshev (c) Bessel (d) Elliptical 7. If the cutoff frequency of a lowpass filter is 2 kHz, its bandwidth is ________ (a) 4 kHz (b) 2 kHz (c) 8 kHz (d) 1 kHz 8. The rolloff rate in the stop band of a fourthorder filter is (a) −20 dB/decade (b) −40 dB/decade (c) −80 dB/decade (d) −60 dB/decade 9. A lowpass filter with a cutoff frequency of 4 kHz is cascaded with a highpass filter with a cutoff frequency of 2 kHz. The resultant filter is (a) an allpass filter (b) an allstop filter (c) a bandreject filter (d) a bandpass filter 10. A highpass filter with a cutoff frequency of 2 kHz is cascaded with a lowpass filter with a cutoff frequency of 4 kHz. The resultant filter is (a) an allpass filter (b) an allstop filter (c) a bandreject filter (d) a bandpass filter 11. A firstorder, lowpass filter has R = 50 Ω and C = 5 μF. The frequency at which the gain falls by 3 dB is (a) 0.637 kHz (b) 6.37 kHz (c) 63.6 kHz (d) 636 kHz
864
Electronic Devices and Circuits
12. A filter that has a constant gain in the entire frequency range, and a phase response that changes linearly with frequency is (a) an allpass filter (b) an allstop filter (c) a bandreject filter (d) a bandpass filter
Short anSwer QueStionS 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.
What is a filter? Where is the need for cascading firstorder passive filters? Compare an ideal lowpass filter and a firstorder RC lowpass. What are the main limitations of the passive filters? What are active filters and what are their main advantages? What is an allpass filter and what is its main application? Classify active filters. What is a Butterworth filter? Why are higherorder filters used? What is a notch filter?
long anSwer QueStionS 1. Draw the circuit of a secondorder, lowpass, Sallen–Key Butterworth filter and derive the expression for its transfer function. 2. Draw the circuit of a secondorder, highpass, Sallen–Key Butterworth filter and derive the expression for its transfer function. 3. Draw the circuit of a wide band pass filter and obtain the expression for its gain. 4. Draw the circuit of a wide band reject filter and obtain the expression for its gain. 5. Draw the circuit of the IGMF narrow band pass filter and derive the expression for its transfer function. 6. Draw the circuit of the twinT notch filter and derive the expression for its transfer function. 7. What is an all pass filter? With the help of a neat circuit diagram, derive the expression for its gain. 8. Write short notes on switched capacitor filters.
unSolved problemS 1. Design a firstorder wide bandpass Butterworth filter shown in Figure 16.22, to have a midband gain of 4, fL = 200 Hz and fH = 1 kHz . Determine Q. 2. Design a first order wide bandreject Butterworth filter shown in Figure 16.28 to have a midband gain of 2, fH = 200 Hz and fL = 1 kHz . 3. Design an IGMF narrow band pass filter, Figure 16.24, to have fo = 2 kHz , BW = 200 Hz and gain of 50 at resonance. 4. Design a secondorder, highpass Butterworth filter, Figure 16.20, to have a cutoff frequency of 1 kHz. 5. Design a secondorder, lowpass Butterworth filter, Figure 16.14, having fH = 1 kHz . The opamp is required to have minimum dc offset voltage. 6. Design a firstorder, highpass Butterworth filter to have a cutoff frequency of 4 kHz and pass band gain of 4.
17
VOLTAGE REGULATORS
Learning objectives After reading this chapter, the reader will be able to
17.1
Appreciate the need for voltage regulators to stabilize the output of a power supply Understand the principle of working of Zener and transistor shunt regulators Understand the principle of working of a transistor series regulator Design a complete feedback regulator Understand the need and methods to implement protection in a regulator Learn the operation of linear IC regulators Understand the working of switching regulators and the principle of SMPS Appreciate the need for voltage multipliers
INTRODUCTION
In chapter 3, we have considered the method of converting alternating (mains) signal into DC using rectifiers and eliminating or minimizing the ripple using filters circuits. The combination of transformer, rectifier, and filter (TRF) can be called a power supply that can be used for biasing transistor and FET circuits (Figure 17.1). But the voltage of the power supply should remain constant as any change in the power supply voltage can change the operating point of the circuit. IL ± ∆IL 230 V, + 50c/s Vi ± ∆Vi Mains input −
Transformer
+ Rectiﬁer
Filter
VO ± ∆VO Load
−
Figure 17.1 TRF power supply
However, the output of the TRF power supply can change mainly due to the following reasons: (i) The input voltage Vi to the circuit can change due to fluctuations in mains voltage. As a result, the DC output voltage as well as the ripple in output can change. (ii) Due to changes in load resistance RL, the load current IL can change, resulting in a change in the output voltage. (iii) Due to changes in temperature, the device parameters can change, which in turn could change the output voltage.
866
Electronic Devices and Circuits
Therefore, the change in the output voltage of a power supply can be expressed as follows: ∆VO = SV ∆Vi + RO ∆I L + ST ∆T
(17.1)
where ∆VO is the possible change in the output voltage due to an incremental change ∆Vi in Vi or due to an incremental change ∆I L in load current IL or due to a small change ∆T in temperature T. The stability factor SV is defined as follows: SV =
∆VO ∆I L = 0, ∆T = 0 ∆Vi
(17.2)
In a good power supply, SV should be as small as possible. RO, the output resistance is defined as follows: RO =
∆VO ∆Vi = 0, ∆T = 0 ∆I L
(17.3)
RO should be small to ensure that the entire output voltage appears across the load. ST, the temperature coefficient is defined as follows: ST =
∆VO ∆Vi = 0, ∆I L = 0 ∆T
(17.4)
A small value of ST indicates that even for larger changes in T, there are negligible changes in VO. These parameters define the goodness of a power supply. The performance of a power supply is also specified in terms of three important factors: (i) source effect, (ii) load effect, and (iii) ripple rejection ratio. (i) Source effect: The ac input voltage to a rectifier (called power supply) does not remain constant. A change in the ac source voltage (also called the line voltage) can cause a change in the dc output voltage. The change in the dc output voltage for 10 percent change in source voltage is called source effect. Source effect = ∆Vo for a 10 percent change in Vi Another way of expressing the change in the dc output voltage due to source effect is by line regulation defined as follows: Line regulation =
Source effect ´100% Vi
(17.5)
Line regulation is also defined as the percentage change in the output voltage for a given change in the input voltage: Line regulation =
∆VO × 100% ∆Vi
(17.6)
For a good power supply, this value is small. (ii) Load effect: The dc voltage at the output of a power supply changes with load current. VO decreases with increase in IL and increases with decrease in IL. The load effect specifies how the output dc voltage changes when IL increases from 0 to IL(max).
Voltage Regulators
867
Load effect = ∆Vo for ∆I L(max ) Another way of expressing the change in the dc output voltage due to load effect is by load regulation, defined as follows: Load regulation =
Load effect ´100% Vi
(17.7)
Load regulation is also defined as the percentage change in the output voltage due to given change in the load current. This is normally expressed as follows: Load regulation =
VNL − VFL ×100% VNL
(17.8)
where VNL is the noload voltage (RL = ) and VFL is the output voltage with maximum permissible load current IL. In a good power supply, the load regulation should be as small as possible. Ideally, it should be zero. (iii) Ripple rejection: Ripple rejection is the ability of the power supply to reject ripple and is usually expressed in dB. It is defined as the ratio of the peaktopeak ripple voltage, Vor(pp) in the output to the peaktopeak ripple voltage, Vir(pp) at the input. Ripple rejection = 20log10
Vor(pp) Vir(pp)
dB
(17.9)
(iv) Temperature stability: Temperature stability is defined as the change in the output voltage for a given change in temperature and is expressed in mV/°C. ∆VO (17.10) ∆T It can be noted that the output voltage can change due to many factors. Hence, there arises the need for voltage regulators, whose purpose is essentially to ensure that the output voltage almost remains constant, irrespective of the variations in the input voltage, load current, or temperature. Temperature stability =
17.2
CLASSIFICATION OF VOLTAGE REGULATORS
Depending on how regulation is achieved, voltage regulators are classified as (i) linear regulators and (ii) switching regulators. First, linear regulators using discrete components are considered, and subsequently the IC versions of these regulators are discussed. A linear voltage regulator senses the output voltage and adjusts the current source to maintain the output voltage at the desired value. Thus, it can be noted that a linear regulator uses a voltagecontrolled current source to maintain the output constant. In this chapter, firstly we discuss about linear voltage regulators that use Zener diodes, transistors, or their combination for controlling the output voltage. Further, the controlling element, a Zener diode or transistor, can be used either in series with the load or in shunt with the load, based on which the linear regulators can be further classified as (i) shunt regulators (ii) series regulators. A shunt controller is shown in Figure 17.2 and a series controller is shown in Figure 17.3. The output voltage is sampled by a voltage sensor, and this signal controls the current I(v) to control VO.
868
Electronic Devices and Circuits IL +
+ I (v)
Vi
RL
Unregulated input
Vo
Voltage sensor − Shunt controlling element
−
Figure 17.2 A linear shunt regulator Series controlling element I (v)
IL
+
+
Vi
RL
Unregulated input
Vo
Voltage sensor −
−
Figure 17.3 A linear series regulator
17.3
SHUNT REGULATORS
As mentioned earlier, shunt regulators use the controlling element in shunt with the load. A Zener diode or a transistor can be used as the controlling elements.
17.3.1 Zener Diode as a Shunt Regulator Let us consider a Zener shunt regulator (Figure 17.4). The V–I characteristic of the Zener diode is shown in Figure 17.5. II TRF power supply
RS
+ Vi ± ∆Vi
IL +
IZ
VZ
RL
VO
−
−
Figure 17.4 Zener diode as a shunt regulator
IZ(min) is the minimum Zener current needed to keep the device ON and IZ(max) is the maximum Zener current the device can handle. Between IZ(min) and IZ(max), the Zener voltage varies between VZ(min) and VZ(max). For all practical purposes, it can be assumed that VZ remains constant as ∆VZ
(
)
= V − Vz(min) , the change in the Zener voltage is negligible. The maximum dissipation in z( max )
Voltage Regulators
869
IF
VZ(max) V
Z(min)
0
VR IZ(min)
Vγ
VF
IZ(max) IR
Figure 17.5 V–I characteristic of the Zener diode
the Zener diode and the breakdown voltage of the Zener are specified by the manufacturer in PZ(max ) the data sheet as PZ(max) and VZ. From these two values IZ(rated) can be calculated as I Z(rated) = . VZ Normally, the device is not operated at its rated current, but at a value slightly less than this. Hence, IZ(max) and IZ(min) are usually chosen as IZ(max) = 0.8 IZ(rated) and IZ(min) = 0.2 IZ(rated). Choosing the value of RS: Let the input voltageVi vary between Vi(max ) = (Vi − ∆Vi ) and Vi(min) = (Vi − ∆Vi ), and let the load current I L vary between I L(max ) and I L(min). Let the variation of the Zener current be between the limits IZ(min) and IZ(max). From Figure 17.4, Vi= ( I Z + I L ) RS + VZ
(17.11)
(i) When the input voltageVi is Vi(min) to have VO at the output IL = IL(max) and correspondingly for the Zener to conduct, there should be minimum Zener current IZ(min). Hence, under this condition RS is RS(max) and Eqn. (17.11) gets modified as follows:
(
)
Vi(min) = I Z(min) + I L(max ) RS(max ) + VZ ∴ I Z(min) =
Vi(min) −VZ RS(max )
− I L(max )
(17.12)
Or RS(max ) =
Vi( min)  VZ I Z ( min) + I L ( max )
RS(max ) is the maximum allowable series resistance.
(17.13)
870
Electronic Devices and Circuits
(ii) When the input voltage Vi is Vi(max ) to have VO at the output IL = IL(min) and correspondingly for the Zener, there should be maximum Zener current IZ(max). Hence, under this condition, RS is RS(min) and Eqn. (17.11) gets modified as follows:
(
)
Vi(max ) = I Z(max ) + I L(min) RS(min) +VZ ∴ I Z(max ) =
Vi(max ) −VZ RS(min)
(17.14)
− I L(min)
Or RS( min) =
Vi( max )  VZ
(17.15)
I Z ( max ) + I L ( min)
RS(min) is the minimum value series resistance. The value of RS, therefore, should lie somewhere between RS(max) and RS(min). Alternately, RS is taken as the average of these two values. Example 17.1 In the Zener regulator shown in Figure 17.6, Vi varies from 20 to 30 V, IL varies from 0 to 90 mA, and the Zener breakdown occurs at 5 mA. Find RS, IZ(max), RL(min), and RL(max). The Zener rating is 10 V and 2 W. Ii
RS
IL
+
+
Vi
IZ
VZ
RL
−
VO −
Figure 17.6 Zener regulator
Solution: Given Vi(min) = 20 V, VZ = 10 V, I Z(min) = 5 mA, I L(max ) = 90 mA, Vi(max ) = 30 V, IL(min) = 0 mA, and PZ(max) = 2 W. RS( max ) =
Vi( min)  VZ
I Z ( min) + I L ( max ) resistance.
=
20  10 = 105 Ω. Since RS < RS(max), choose RS = 100 Ω, a standard 5 + 90
I Z(max ) =
PZ(max ) VZ
=
2 = 200 mA 10
VZ VZ VZ 10 10 , RL(min) = = = 111 Ω, and RL(max) = = = ∞. We I L(max ) 90 0 IL I L(min) can choose RL as a 500 Ω potentiometer. We have VZ = 10 V. Since RL =
Example 17.2 Design a Zener regulator to supply a load current of 0 to 500 mA at 10 V. The dc input varies from 20 to 30 V. For stable operation, the minimum Zener current required is 10 mA.
Voltage Regulators
871
Solution: Given Vi(min) = 20 V, VZ = 10 V, I Z(min) = 10 mA, I L(max ) = 500 mA, Vi(max ) = 30 V, and IL(min) = 0 mA RS(max ) =
Vi(min) − VZ I Z(min) + I L(max )
I Z(max ) + I L(min) =
Vi(max ) − VZ RS
=
=
20 − 10 = 19.6 Ω. Choose RS = 10 Ω 10 + 500
30 − 10 = 2 A, which is I Z(max ) since I L(min) = 0. 10
The maximum current through RS = Ii = I Z(max ) + I L(max ) = 2 + 0.5 = 2.5 A. 2
Therefore, the power rating of RS = I i2 RS = ( 2.5) × 10 = 62.5 W. The power rating of the Zener = VZ I Z(max ) = 10 × 2 = 20 W. Choose a Zener with PZ > 25 W. Stability factor for Zener regulator: The stability factor is defined in Eqn. (17.2) as follows: SV =
∆V0 ∆I L = 0, ∆T = 0 ∆Vi
Let an incremental change in the input voltage Vi give rise to an incremental change in the output ∆VZ voltage Vo. Let rZ be the ac resistance of the Zener diode which is given as rZ = (Figure 17.7). ∆I Z When there is an incremental change in Vi, there are corresponding changes in Ii, Vo, IZ, and IL.
−VZ
∆VZ
0
∆IZ
−IZ
Figure 17.7 To calculate rz of the Zener diode
From Figure 17.6, V V Vi = I i RS + Vo = ( I z + I L ) RS + Vo = o + o RS + Vo = Vo rz RL ∴ Vo =
Vi RS RS 1+ r + R z L
RS RS 1+ r + R z L
(17.16)
(17.17)
872
Electronic Devices and Circuits
∂Vo 1 = SV = ∂Vi RS RS 1+ r + R Z L When RL = ∞. SV =
(17.18)
rZ rZ + RS
If RL »RS and rZ «RS, Eqn. (17.18) reduces to SV =
1 RS RS 1 + r + R Z L
≈
r 1 ≈ Z RS RS rZ
(17.19)
SV is small only when RS is large. To evaluate the performance of the Zener diode regulator, we need to calculate source effect, line regulation, load effect, load regulation, and ripple rejection ratio. For this, we need to draw the ac circuit by replacing the Zener diode with its dynamic resistance, rZ, as shown in Figure 17.8. RS + ∆Vi
+ rZ
RL
−
∆Vo −
Figure 17.8 AC circuit of Figure 17.6
From Figure 17.8, ∆Vo = ∆Vi
rZ  RL
(17.20)
RS + ( rZ  RL )
The source effect is determined using Eqn. (17.20). Ripple rejection =
rZ  RL Vr o = Vr i RS + ( rZ  RL )
(17.21)
Output resistance: To calculate the load effect, the output resistance of the regulator is to be determined. The output resistance is calculated with RL = ∞ (open the load) and Vi = 0 (short the input voltage source). Imposing these conditions on Figure 17.8, we get the circuit in Figure 17.9. RS
Set Vi = 0
Open RL rZ
Ro
Figure 17.9 Circuit to calculate Ro
Voltage Regulators
873
From Figure 17.9, Ro = rZ  RS
(17.22)
Load effect is ∆Vo = ∆I L ( rZ  RS )
(17.23)
Example 17.3 Design a Zener regulator to deliver 6.8 V dc voltage. The unregulated input is 20 V to produce a maximum load current. Calculate RS and the maximum load current. IZ(min) = 0. Solution: From the data sheet, choose Zener diode that has VZ = 6.8 V and PZ = 500 mW. I Z(max ) =
PZ 500 mW = = 73.53 mA ≈ I i(max ) ,since I Z(min) = 0 6.8 V VZ
I i(max ) = I L(max ) + I Z(min) = 73.53 mA RS =
Vi  VZ 20  6.8 = = 180 W 73.53 I Z ( max )
(
2 Dissipation in RS = I i(max) RS = 73.53 × 10 −3
2
)
× 180 = 0.98 . W
From the data sheet, select I Z(min). Let I Z(min) = 5 mA ∴ I L(max ) = I i(max ) − I Z(min) = 73.53 − 5 = 68.53 mA Example 17.4 For the circuit in Example 17.3, if rZ = 5 Ω, determine (i) source effect, (ii) line regulation, (iii) load effect, (iv) load regulation, and (v) ripple rejection ratio. Solution: (i) Source effect ∆Vi = 10% of 20 V = 2 V RL =
DVo = DVi
(ii) Line regulation =
Vo 6.8 = = 99.23 W I L ( max ) 68.53 ´ 10 3
rZ  RL 5  99.23 = 2´ = 51.53 mV RS + ( rZ  RL ) 180 + (5  99.23)
51.53 × 10 −3 × 100 = 0.76% 6.8
(iii) Load effect = ∆Vo = ∆I L ( rZ  RS ) = 68.53 ´ 10 3 (5  180 ) = 333.4 mV (iv) Load regulation =
333.4 × 10 −3 × 100 = 4.9% 6.8
(v) Ripple rejection =
rZ  RL 5  99.23 Vr o = = = 0.025 Vr i RS + ( rZ  RL ) 180 + (5  99.23)
874
Electronic Devices and Circuits
The power dissipation capability of the Zener diode is PD(max) = VZIZ(max)., which is normally specified at 25°C. However, at elevated temperatures, the power dissipation capability of the Zener diode decreases. As the Zener diode exhibits negative temperature coefficient, a Z, VZ decreases with increase in temperature. If a Z = − 0.06%/°C and VZ = 3.6 V at 25°C, then VZ at 100°C is given as follows: VZ (at 100°C) = VZ + ∆VZ
(17.24)
where ∆VZ = VZ a Z (T25), æ  0.06 ö \ DVZ = 3.6 ´ ç ÷ ´ 75 =  0.162 V è 100 ø VZ (at 100°C) = 3.6−0.162=3.438 V Zener diodes normally operate below 6 V Avalanche and Zener diodes are generally called Zener diodes although the principle of operation is different. An avalanche diode has a positive temperature coefficient, that is, VZ increases with temperature. If az = 0.06%/°C and VZ=10 V at 25°C, then VZ at 100°C is given as follows: where ∆VZ = VZ a Z (T25)
VZ (at 100°C) = VZ + ∆VZ
(17.25)
æ 0.06 ö \VZ = 10 ´ ç ÷ ´ 75 = 0.45 V è 100 ø VZ (at 100°C) = 10+0.45 = 10.45 V The main limitations of the simple Zener regulator are that (i) the Zener current varies by larger amounts, (ii) relatively poor regulation, and (iii) large amount of dissipation occurs both in the Zener diode and in RS, when compared to RL.
17.3.2 Basic Transistor Shunt Regulator The main limitation of the Zener shunt regulator is that to control the output voltage, the Zener current varies by wide limits. On the contrary, it may be preferable that for better control, smaller current variations can control the variations in the output voltage. Such a requirement is satisfied by a transistor shunt regulator (Figure 17.10). In this circuit, the Zener supplies the base current to the transistor. A series resistance RS is included and the drop across this controls the output voltage. The current Ii is given as follows: Ii = IB + IC + IL
(17.26)
The output voltage VO is given as follows: Vo = VZ + VBE
(17.27)
Also Vo = Vi − IiRS = Vi − (IB + IC + IL) RS
(17.28)
From Eqn. (17.27), since both VZ and VBE are supposed to remain constant, VO remains constant. However, if Vi increases for some reason or the other, then VO also increases. Since VZ remains
Voltage Regulators
875
+VR− Ii
RS
+ + VZ − IB
IZ Unregulated
D
Vi
IC
IL +
Q RL
+ VBE
Vo −
−
Figure 17.10 Basic transistor shunt regulator
constant, VBE increases. Hence, IB increases resulting in larger IC because I C = hFE I B. Consequently, Ii increases and thereby the voltage drop across RS increases and VO is once again brought back to the desired value. This can be expressed as follows: ↑ Vi →↑ VO →↑ VBE →↑ I B →↑ I C →↑ I i → ↑ VR →↓ VO
(17.29)
The arrow pointing upward (↑) represents an increase in the value of the variable and an arrow pointing downward (↓) represents a decrease in the value of the variable. The above representation is read thus: Increase in Vi leads to (→) increase in VO. Increase in VO leads to increase in VBE. Increase in VBE leads to increase in IB. Increase in IB leads to increase in IC. Increase in IC leads to increase in Ii. Increase in Ii leads to increase in VR, the voltage drop across RS. Increase in VR leads to decrease in VO. Alternately, decrease in Vi leads to decrease in VO. Decrease in VO leads to decrease in VBE. Decrease in VBE leads to decrease in IB. Decrease in IB leads to decrease in IC. Decrease in IC leads to decrease in Ii. Decrease in Ii leads to decrease in VR, the voltage drop across RS. Decrease in VR leads to increase in VO. VO is brought back to the desired value. ↓ Vi →↓ VO →↓ VBE →↓ I B →↓ I C →↓ I i → ↓ VR →↑ VO
(17.30)
Thus, a transistor shunt regulator takes care of the changes in the input voltage Vi and maintains the output VO constant. If RL decreases, then IL increases and VO decreases. Decrease in VO leads to decrease in VBE, which in turn leads to a decrease in IB. Decrease in IB in turn decreases IC. Hence, Ii decreases and so does VR. Therefore, VO increases. VO is once again brought back to the required value. This condition is represented below: ↓ RL →↑ I L →↓VO →↓ VBE →↓ I B →↓ I C →↓ I i →↓VR →↑ VO
(17.31)
Thus, the regulator will take care of the changes in load current. Example 17.5 For the transistor shunt regulator shown in Figure 17.11, calculate the regulated output voltage and the circuit currents. Solution: The load voltage VO = VZ + VBE = 6.8 + 0.7 = 7.5 V For the given, RL, IL =
VO 7.5 = = 30 mA. RL 250
876
Electronic Devices and Circuits
Vi − VO 25 − 7.5 = = 175 mA RS 100 Therefore, the collector current IC, since IZ = IB is small, is IC = Ii − IL = 175 − 30 = 145 mA
When Vi = 25 V, Ii =
Ii RS = 100 + IZ Vi = 25 V
−
D
+ VZ = 6.8 V − IB
IC IL + Q
RL = 250
+ VBE = 0.7 V −
VO −
Figure 17.11 Transistor shunt regulator
Example 17.6 Design the transistor shunt regulator shown in Figure 17.10 to maintain the output voltage constant at 10 V. The maximum permissible load current is 500 mA. IC = 10 mA and hFE = 50. The input voltage varies as 20 ± 10%. VBE of the transistor is 0.7 V. Solution: Given VO = 10 V, VBE = 0.7 V, and IL = 500 mA. VO = VZ + VBE ∴VZ = VO − VBE = 10 − 0.7 = 9.3 V Since Vi varies as 20 ± 10%, Vi(max ) = 22 V and Vi(min) = 18 V Since IC and IB are small when compared to IL, Ii = IL. Therefore, RS = 2 and its wattage is ( 0.5) × 24 = 6 W. RL(min) =
Vi(max ) − VO IL
=
22 − 10 = 24 Ω 500
VO 10 2 = = 20 Ω and its wattage is ( 0.5) × 20 = 5 W. I L 500
I C 10 = = 0.2 mA and PZ = VZ I Z = 9.3×0.2 = 1.86 mW. hFE 50 Choose a Zener with VZ = 9.3 V and having a PZ = 10 mW.
IB = IZ =
VCE = 10 V and IC = 10 mA. Therefore, PD = 10 V × 10 mA = 100 mW. Choose a transistor with PD(max) =250 mW. Stability factor SV for the transistor shunt regulator: The stability factor SV is defined with IL = 0, that is change in load current is zero. SV is calculated using the small signal model of Figure 17.10 as shown in Figure 17.12. From Figure 17.12, Vi = Vo + ( I b + I c + I L ) RS = Vo + ( I b + hfe I b + I L ) RS ≈ Vo + hfe I b RS + I L RS
(17.32)
Voltage Regulators
Ii
877
RS Collector
+ rz
Iz
Ic IL
Vi
+
Base hie
RL
Vo
hfeIb
Ib
−
− Emitter
Figure 17.12 AC circuit to calculate SV
since I b « hfe I b. But from Figure 17.12, Vo (rZ + hie )
(17.33)
Vi = hfe I b RS + Vo + I L RS
(17.34)
Ib = and
Using Eqn. (17.33), V h R Vi = hfe o RS + Vo+I L RS = Vo 1+ fe S + I L RS r h + r Z ie Z + hie ∴Vo =
∂Vo = SV = ∂Vi
Vi − I L RS h R 1 + fe S rZ + hie
rZ + hie h 1 1 ≈ ie = = hfe RS rZ + hie + hfe RS hfe RS hfe 1+ R rZ + hie hie S
since hfe RS » ( rZ + hie ) and rZ « hie. We know that SV =
1 gm RS
(17.35)
(17.36)
hfe = gm. Therefore, hie (17.37)
From Eqn. (17.36), it can be noted that regulation can be improved by using a transistor with larger hfe. I Advantage of a transistor shunt regulator: Since I Z = I B = C , the changes in IZ are reduced by a hFE factor h ( = b ). FE
dc
Limitations of a transistor shunt regulator: (i) There is an appreciable power loss across the series resistance RS; (ii) a large current flows through the transistor. Hence, the transistor chosen should have a larger power dissipation capability; (iii) overload or short circuit protection cannot be
878
Electronic Devices and Circuits
implemented in a shunt regulator; and (iv) the output strictly cannot be maintained constant because VBE and VZ are likely to change with temperature.
17.4
SERIES REGULATORS
In series regulators, the controlling element is connected in series with the load. The controlling element usually is a transistor, whose resistance either increases or decreases depending on whether the output is increasing or decreasing.
17.4.1 Transistor Series Regulator A transistor series regulator is shown in Figure 17.13. The Zener diode is used as a reference element. The assumption is that VZ almost remains constant. The transistor is used as an emitter follower. Current passing through the transistor controls the resistance between the collector and emitter terminals, and hence the output voltage. The transistor is called the series pass transistor. The output voltage VO can change due to variations in Vi, IL, or temperature. IL can change due to temperature variations or due to variations in RL, and hence the influence of temperature variations can be taken care of to some extent when load current variations are taken into account. Hence, we see how the regulator works for changes in Vi and IL. Ii
VCE Q
+
+
IR = IB + IZ
Vi Unregulated input
R
− +
VBE
IB
+
D
+ VZ −
IZ
IL
−
RL
VO −
−
Figure 17.13 Transistor series regulator
From Figure 17.13, writing the KVL equation of the output loop, VO =VZ − VBE or VBE = VZ − VO
(17.38)
Also VO =Vi − VCE
(17.39)
1. Changes in Vi : The input voltage changes by Vi ± ∆Vi. (i) First consider when the input voltage increases by ∆Vi . When Vi increases, VO increases. From Eqn. (17.38), when VO increases VBE decreases which in turn decreases IB. Decrease in IB increases VCE. When VCE increases, VO is brought back to the desired value. This can be represented as follows: ↑ Vi →↑ VO →↓ VBE →↓ I B →↑ VCE →↓ VO
(17.40)
(ii) Now consider the situation when Vi decreases. When Vi decrease Vo decreases. From Eqn. (17.38), VBE increases. Increase in VBE gives rise to an increase in IB. Increase in IB reduces VCE, and hence VO is once again brought back to the required value.
Voltage Regulators
↓ Vi →↓ VO →↑ VBE →↑ I B → ↓ VCE →↑ VO
879
(17.41)
2. Changes in IL: (i) If RL decreases, then IL increases and VO decreases. Decrease in VO leads to increase in VBE which in turn leads to an increase in IB. Increase in IB in turn decreases VCE. Therefore, VO increases. VO is once again brought back to the required value. This condition is represented below: ↓ RL →↑ I L →↓VO →↑ VBE →↑ I B → ↓VCE →↑ VO
(17.42)
(ii) If RL increases, then IL decreases and VO increases. Increase in VO leads to decrease in VBE which in turn leads to a decrease in IB. Decrease in IB in turn increases VCE. Therefore, VO decreases. VO is once again brought back to the required value. This condition is represented below: ↑ RL →↓ I L →↑VO →↓ VBE →↓ I B → ↑VCE →↓ VO
(17.43)
Thus, this regulator maintains the output voltage constant irrespective of the variations in Vi or IL. Advantage of a transistor series regulator: Overload or shortcircuit protection can be implemented Limitations of a transistor series regulator: (i) VO strictly cannot be maintained constant because both VBE and VZ can change with temperature (ii) The power dissipation in the series pass transistor, PD (= VCEIC) becomes larger for larger load currents. Stability factor SV for the transistor series regulator: The stability factor SV is defined with IL = 0, that is, change in load current is zero. The circuit in Figure 17.13 is redrawn as in Figure 17.14. The incremental equivalent circuit is shown in Figure 17.15. SV is calculated using the smallsignal model of Figure 17.15 as shown in Figure 17.16. + R Q Vi Unregulated input D
+ VZ −
−
+ RL
VO −
Figure 17.14 Redrawn circuit of Figure 17.13
Thevenizing the circuit at B: Vth = Vi
rZ and Rth = rZ //R ≈ rZ R + rZ
880
Electronic Devices and Circuits
+ R B
Q
Vi +
rZ RL
Vo −
−
Figure 17.15 Circuit of Figure 17.14 with Zener replaced by rZ
The ac circuit of Figure 17.15 is drawn in Figure 17.16. The emitter follower has unity voltage R +h gain and output resistance as S ie . In the present case, RS = rZ. Hence, the output circuit is hfe drawn as in Figure 17.16.
rZ Q
+ +
Vbe − Vi rZ/ (R + rZ)
−
RL
+ Vo −
Figure 17.16 AC circuit of Figure 17.15 (rZ + hie) / hfe
+ Vi rZ / (R + rZ) RL −
+ Vo −
Figure 17.17 Output circuit
From Figure 17.17, Vo = Vi
If
(rZ + hie ) « R hfe
L
rZ ´ R + rZ
, then Eqn. (17.44) reduces to
RL r +h RL + Z ie . hfe
(17.44)
Voltage Regulators
Vo = Vi
rZ R + rZ
881
(17.45)
∂Vo r = SV = Z ∂Vi R + rZ
(17.46)
SV is small when R is large. Example 17.7 Design the series voltage regulator shown in Figure 17.13 to deliver a load current of 1.5 A and a constant output voltage of 9.7 V. The unregulated input varies as 20 ± 10%, VBE = 0.7 V, IZ = 10 mA, and hFE = 40. Solution: VO = VZ − VBE or VZ = VO + VBE = 9.7 + 0.7 = 10.4 V and IZ = 10 mA. Therefore, PZ = 10.4 × 10 = 0.104 W. I 1.5 IL = IC = 1.5 A and hFE = 40. Therefore, IB = C = = 37.5 mA. Given IZ = 10 mA. hFE 40 Therefore, IR = IZ + IB = 37.5 + 10 = 47.5 mA. R(max) =
Vi(max ) − VZ IR
Vi(max) = 20 + 2 = 22 V and Vi(min) = 20 – 2 = 18 V Vi(min) − VZ 18 − 10.4 22 − 10.4 = = 244 Ω and R(min) = = = 160 Ω 47.5 47.5 47.5
R(min) + R(max )
(
)
2 244 + 160 = = 202 Ω and its wattage is 47.5 × 10 −3 × 202 = 0.456 W 2 2 VCE(max) = Vi(max ) − VO = 22 −9.7 = 12.3 V and IL = IC = 1.5 A. PD = 12.3 × 1.5 = 18.45 W
R=
Output resistance: To find out the output resistance of the series regulator, set Vi = 0 and RL = ∞ in Figure 17.13 and replace the devices by their incremental models (Figure 17.18). The equivalent circuit of Figure 17.18 is shown in Figure 17.19. In Figure 17.19, R is omitted since, normally, R>>rZ. Find I
Open RL Introduce V
R Set Vi = 0 rZ
Ro
Figure 17.18 Circuit to calculate Ro
From Figure 17.19, V = I b ( rZ + hie ) and I = I b (1 + hfe )
882
Electronic Devices and Circuits Ib B
E
Ib(1 + hfe) I
hie rZ
− V hfeIb + C
Figure 17.19 Simplified equivalent circuit
∴ Ro =
V I b ( rZ + hie ) rZ + hie = = 1 + hfe I I b (1 + hfe )
(17.47)
17.4.2 Improved Series Regulator The circuit in Figure 17.20 is an improved series voltage regulator. R1 and R2 combination is the sampling and feedback network. The Zener diode is used as a reference element. R2 V2 = VO = bVo. As Vo changes, bVo changes. bVo = VZ + VBE2 . VZ practically remains R1 + R2 constant. So, when bVo changes, VBE2 changes. Hence IB2 changes and controls IL. Ii
+
VCE
IC1
Q1
+
− +
IB1 + IC2 R4 Vi Unregulated input
IL
IB1
+
VBE1 + IB2 VZ −
IC2 Q2
+ VBE2 −
R1
−
RL
+
VO −
V2 = βVo R3
R2 −
Figure 17.20 Improved series regulator
(i) Let VO increase from the desired value. Then bVo increases. Hence, VBE2 increases. Therefore, IB2 increases. As a result, IC2 increases. Hence, the drop across R4 increases and the voltage at the base of Q1 decreases. Consequently, IB1 decreases. The result is that IC1 = IL decreases and VO is brought back to the desired value. (ii) Alternately, let VO decrease from the desired value. Then bVo decreases. Hence, VBE2 decreases. Therefore, IB2 decreases. As a result, IC2 decreases. Hence the drop across R4 decreases and the voltage at the base of Q1 increases. Consequently, IB1 increases. The result is that IC1 = IL increases and VO is brought back to the desired value. We have V2 = VO
R2 = bVO R1 + R2
Voltage Regulators
883
Also bVO = VZ + VBE2 ∴VO
R2 = VZ + VBE2 R1 + R2
Hence, R + R2 VO = (VZ + VBE2 ) 1 R2
(17.48)
Example 17.8 For the series regulator circuit shown in Figure 17.20, VZ = 6.8 V, VBE2 = 0.7 V, R1 = 20 kΩ, and R2 = 30 kΩ. Calculate the output voltage. R + R2 20 + 30 Solution: Vo = (VZ + VBE2 ) 1 = (6.8 + 0.7 ) = 12.5 V 30 R2
17.5
OVERLOAD AND SHORTCIRCUIT PROTECTION IN REGULATORS
When a regulated power supply is used, it is possible that there could be an overload, that is, RL may decrease. Hence, the load current increases with the resultant decrease in output voltage. Or sometimes, it may be possible that the output terminals of the power supply may accidentally get shorted, resulting in a very large load current, which will damage the regulator and the associated components. To avoid these problems, overload or shortcircuit protection is usually provided in the regulated power supplies. It is easy to implement protection circuit in a series regulator. The most commonly used current limiting circuits are (i) constant current limiting, (ii) foldback current limiting, also called voltage dependent current limiting.
17.5.1 Constant Current Limiting in a Series Regulator From Figure 17.13, it can be noted that if RL decreases, IL (= IC) increases. Sometimes, IL may be so large that the dissipation that can occur in the transistor, PD may be much larger than PD(max) specified for the transistor. This could damage the transistor. To avoid this, overload protection is used in the regulator. Figure 17.21 shows the method to implement overload protection in a series regulator. A small sensing resistor RSC is connected in series with the load RL. Two diodes D1 and D2 are connected from the base of the transistor to the output terminal. The voltage drop across RSC is ILRSC. The diodes D1 and D2 conduct only when the voltage drop across them is at least 2Vγ =[(Vγ + Vγ)]. But (VBE + ILRSC) is the voltage drop across the two diodes. However, VBE ≈ Vγ. Hence for the diodes to conduct, the drop across RSC should be atleast Vγ. RSC is adjusted such that as long as IL is less than the specified maximum, the drop across RSC is less than Vγ. Hence, the diodes are OFF. If now for any reason, IL>IL(max), D1 and D2 are ON (behave as short circuits, ideally) (Figure 17.22). Hence, part of the base current is directed to the output as IF, thereby reducing the base current to the transistor. Hence the load current is limited to IL(max). This ensures safety of the regulator.
884
Electronic Devices and Circuits
Ii
IC
+ VCE − Q
+
IB
+
RSC
IL
IL
− VBE
+
R
Vi IR = IB + IZ Unregulated input
RL + D1 VZ −
IZ D
−
VO
D2
−
Figure 17.21 Overload protection in a series regulator Ii
RSC
+ VCE − Q
+
IB
IR = IB + IZ
+
− VBE
R
Vi Unregulated input
IZ
IL
IL +
IF RL
ON ON + D1 D2 VZ −
D
−
VO −
Figure 17.22 D1 and D2 conduct when there is an overload
As a small change in the base current can cause a large change in the collector current, a transistor may be used in place of the two protective diodes to effectively bypass a large amount of base current to the load, if needed (Figure 17.23). As long as IL is less than IL(max), the drop across RSC is less than VBE. Hence, Q2 is OFF. Normal regulator action takes place. If IL is more than IL(max), Q2 conducts, thereby directing a larger portion of the base current of Q1 to load as IC2. Hence, IL is not allowed to go beyond IL(max). Ii
+ VCE1 −
IR = IB1 + IZ Vi
IB1 R
+ IC2
−
Iz D
IL
IL
+
IB2 + VBE2
+ Unregulated input
RSC
− VBE1
Q1
+
IC1
Q2
IC2
RL
VO −
VZ −
Figure 17.23 Transistor Q1 is used for overload protection
Thus, we have seen that the function of a current limiting circuit is to prevent damage to the series pass transistor when suddenly the load resistance decreases. In the absence of a current limiting circuit, there flows an excessive current in the series pass transistor. To prevent this occurrence, the current limit circuit will reduce the base current to the series pass transistor, thereby ensuring the maximum safe current limit, IL(max) is not exceeded. From Figure 17.24, it can be noted that as long as I L ≤ I L(max ), VO remains constant. When I L > I L(max ), VO falls to zero. A shortcircuit current, ISC
Voltage Regulators
885
Vo Current limit operates
Regulated Vo
0
IL(max) ISC
IL
RL(min)
RL = ∞
Figure 17.24 V–I characteristic of a constant current limit
flows through the transistor. Practically, the entire input voltage Vi appears as VCE. Therefore, PD = Vi ISC, which can be very large. Hence, the transistor chosen should have this power dissipation capability. When current limit operates, the regulator is no longer in the constant voltage mode, but operates in the constant current mode, because the main concern here is no longer to maintain the output voltage constant but to somehow ensure that the load current is never above the rated maximum. The advantage with constant current limit is that if the load resistance is increased above the point where the current limit operates, the regulator automatically goes into constant voltage mode. For silicon transistor to conduct VBE = Vγ = 0.5V. If IL(max) = 100 mA, then RSC is Vg 0.5 chosen as RSC = = = 5 W. I L ( max ) 100
17.5.2 FoldBack Current Limiting in a Series Regulator The main limitation of simple current limit is that when there is an overload or short circuit, the dissipation in the series pass transistor becomes large, and hence the transistor is required to have a large power dissipation capability. This disadvantage is overcome in a foldback current limiting circuit. When short circuit occurs, the maximum current through the series pass transistor is limited to ISC, which is very much smaller than IL(max), thereby ensuring the safety of the regulator. The foldback current limiting circuit is shown in Figure 17.25, and its V–I characteristic is shown in Figure 17.26. From Figure 17.25, we can draw Figure 17.27, to calculate VBE2. Ii
+ VCE1 − Q1
+
IR = IB1 + IZ Vi Unregulated input −
+ VR1 − IB2
IC2
IB1
IL
IC1
R Q2 IZ D
VZ −
VBE2 −
+
RSC
R1
+
I1 RL I1 R2
Figure 17.25 Foldback current limiting
VO −
886
Electronic Devices and Circuits Vo Regulated Vo Foldback
0
IL(max)
ISC = IL(max) /3
IL
Figure 17.26 V – I characteristic of foldback current limit
RSC R1
IL −
VBE2 + VR2
+
+ RL
VO
R2 −
−
Figure 17.27 Circuit to calculateVBE2
From Figure 17.27, VR2 = ( I L RSC + VO ) where a = Also
R2 = a ( I L RSC + VO ) R1 + R2
(17.49)
R2 R1 + R2 VR2 = VBE2 + VO
(17.50)
From Eqs (17.49) and (17.50), VBE2 + VO = a ( I L RSC + VO ) Or R2 R1 VBE 2 = VO (a − 1) + a I L RSC = VO − 1 + a I L RSC = a I L RSC − VO R1 + R2 R1 + R2 ∴VBE2 = aI L RSC − VO
R1 R1 + R2
(17.51)
When RL reduces, VO reduces and IL increases. Hence VBE2 increases, thereby increasing the base current of Q2. This results in an increased collector current in Q2, which is diverted to the load. This in turn decreases IB1 and hence the load current IL. If RL decreases further, due to any reason,
Voltage Regulators
887
Q2 is driven ON stronger, diverting more current to the load and this further reduces the base current of Q1 and hence IL. Thus foldback current limiting occurs (Figure 17.26). When the output is shorted (VO = 0), the voltage drop across R1 is zero. Hence a = 1. Therefore, VBE2 = ILRSC. RSC is chosen such that as long as I L < I L (max ), VBE2 < 0.5 V, required for Q2 to be ON. Hence, normal regulator action takes place. For Q2 to be ON, the voltage drop across RSC must be larger than the drop across R1by 0.5 V. Then Choosing VR1 = 0.5 V, I L(max ) RSC = VR1 + VBE2 = 0.5 + 0.5 = 1V . If I SC RSC is chosen as 0.5 V, to prevent damage to the transistor, IL(max) = 2ISC. Alternately, If VR1 = 1 V, I L(max ) RSC = 1.0 + 0.5 = 1.5 V . If I SC RSC is chosen as 0.5 V, then IL(max) = 3ISC. Example 17.9 For a series regulator shown in Figure 17.24, design a foldback current limit circuit. The regulated output is 15 V. IL(max) = 300 mA, and ISC = 100 mA. Solution: Given ISC = 100 mA. Choose ISCRSC= 0.5 V. Therefore, RSC =
ISC RSC 0.5 = =5Ω I SC 100
For IL(max) = 300 mA, IL(max) RSC = 300 × 10 −3 × 5 = 1.5 V Therefore, VR1 = IL(max) RSC − 0.5 = 1.5 – 0.5 = 1 V V 1 Usually I1 » I B2 . Let I1 = 1 mA. As VR1 = 1 V and I1 = 1 mA, R1 = R1 = = 1000 Ω I1 1 VR2, the voltage drop across R2 is VR2 = VR1 + I L(max ) RSC + VO = 1 + 1.5 + 15 = 17.5 V R2 =
VR 2 17.5 = = 17.5 kΩ I1 1
Nearest standard values of resistances are usually chosen. From the V–I characteristic of a foldback current limit, it can be noted that as RL decreases to the point where current limit occurs, the output voltage falls to a very small value. Even though RL is returned to its original value, regulator action may not take place because of the foldback characteristic. It becomes necessary to increase RL to a much larger value than the value at which the current limit has occurred.
Overvoltage Protection in a Regulator Although power supplies are usually reliable, occasionally they may fail and can cause damage to the circuitry to which dc voltage is supplied from this source. In a regulator, the unregulated input can be sufficiently large when compared to the regulated output (high dropout voltage). If the output dc voltage required is 5 V, then the input unregulated dc voltage can be as high as 10–15 V. A dc voltage of 5 V is required to operate transistor–transistor logic (TTL) gate for reliable gate operation; the supply voltage of 5 V may be allowed to vary by not more than ±0.5 V. If the power supply uses a series regulator and if the series pass transistor gets short circuited, then the full input voltage of 10 or 15 V will appear as dc voltage to the TTL gate. This will damage the external TTL circuit that uses this dc source. To avoid this, a crowbar protection circuit using a siliconcontrolled rectifier (SCR) is used (Figure 17.28). The protection circuit uses an SCR (also called a thyristor), a Zener diode, with its current limiting resistor, R and R1 that controls the gate current of the SCR.
888
Electronic Devices and Circuits
+ Regulated VO output
+ VZ − + R
−
SCR
IG
DC Voltage connected to circuit
R1
External Circuit like TTL Logic Gate
VR −
Figure 17.28 Crowbar overvoltage protection
VZ is chosen to be slightly above VO. Typically, if VO = 5 V, then VZ can be chosen as 6.2 V. Now due to the failure of the series pass transistor, if VO = 15 V, the Zener diode conducts, a voltage VR develops across R. This supplies gate current IG as trigger to the SCR and drives into the ON state. When an SCR is ON, the voltage between its anode and cathode is ideally zero. This will then provide a short circuit at the output terminals, thereby protecting the external circuit. An SCR can handle high peak currents, of the order of 50 A or more for relatively longer duration. Once the SCR fires (conducts), the voltage across the SCR is typically of the order of a fraction of a volt. Hence, the dissipation in the device is not necessarily large. As long as VO remains unchanged, the SCR is OFF. Normally, current limit is provided in a regulator. Often a fuse is also used. The overvoltage protection circuit is based on brute force: when the power supply voltage increases too much, the thyristor short circuits the output. This means that the overvoltage is quickly removed from equipment and the fuse will burn. The term crowbar is used as a verb to describe the act of shortcircuiting the output of a power supply. In Figure 17.29, the overvoltage protection circuit is used in the output of the regulator. Ci and Co are the filter condensers on the input and the out side. Fuse Regulator Mains input
Overvoltage Sense
Transformer Rectiﬁer
Ci
Co
+ VO −
Figure 17.29 Implementation of overload protection in a regulator
Reverse Polarity Protection in a Regulator Voltage regulators are called dc to dc converters. When connecting the unregulated input to dc to dc converter, one should properly take care of the polarity of the supply. Otherwise, the regulator may get damaged. Let us see the consequences of such a polarity reversal. Let the polarity of the unregulated output be accidentally reversed, as shown in Figure 17.30. The Zener diode gets forward biased by a large Vi. The Zener can be damaged. The transistor can be driven hard into the ON state and may be damaged. (i) Reverse polarity protection using a blocking diode: To prevent damage to the regulator, reverse polarity protection is usually provided in some regulators. One such protection circuit in Figure 17.31 simply uses a diode to block the reverse polarity. When the applied polarity is proper, the diode conducts and the unregulated voltage is applied to the regulator. When the polarity gets reversed, the diode is OFF and no voltage is applied to the regulator.
Voltage Regulators
VCE
Ii
IL
Q
− IB Vi Unregulated input
889
+
− VBE
R
RL
VO
− IZ D
+
VZ +
Figure 17.30 Series regulator with polarity reversal at the input Blocking diode
Blocking diode
+
−
Unregulated output
ON
Regulator
OFF
Unregulated output
−
Regulator
+
(a) Normal polarity
(b) Reverse polarity
Figure 17.31 Reverse polarity protection with blocking diode
(ii) Reverse polarity protection using a shunt diode and fuse: An alternate method to protect the regulator from reverse polarity is by using a shunt diode and fuse (Figure 17.32). When the polarity is normal, the diode is OFF and the unregulated voltage is applied to the regulator input. When the polarity gets reversed, the diode is ON draws a large current that can blow off the fuse. Fuse
Fuse
+ Unregulated output
− OFF
− (a) Normal polarity
Regulator
Unregulated output
ON
Regulator
+ (b) Reverse polarity
Figure 17.32 Reverse polarity protection with shunt diode and fuse
(iii) Reverse polarity protection using a power MOSFET: A Pchannel power MOSFET with a body diode can be used as a switch to provide reverse polarity protection (Figure 17.33). As long as the polarity is proper, the MOSFET switch is ON (diode is forward biased) and its ON resistance RDS(ON) is very small. The unregulated voltage is applied at the regulator input. If the polarity is reversed, the MOSFET switch is OFF (diode is reverse biased) and is an open circuit. No reverse voltage is applied to the regulator. Reverse polarity protection can also be provided at the output of the regulator to ensure that the external circuit is not damaged. One method is to use an electromechanical relay as shown in Figure 17.34. Regulated dc voltage is applied to the external circuit. If the polarity of the regulated output changes, D1 is OFF and D2 is ON. When power is switched OFF to the relay coil with di inductance L, a back emf −L is produced. D2 is used to clamp this voltage to 0.7 V. When no dt current flows through the relay coil, the relay contact opens, thereby protecting the external circuit
890
Electronic Devices and Circuits
ON
OFF
+
−
Unregulated output
Unregulated output
Regulator
Regulator
−
+
(a) Normal polarity
(b) Reverse polarity
Figure 17.33 Reverse polarity protection with Pchannel power MOSFET and body diode
from reverse polarity. However, the relay draws some current. All the earlier protection circuits can also be used at the output of the regulator to protect the external circuit from reverse polarity. With normal polarity D1 is ON and D2 is OFF. Current flows through the relay coil and the relay contact closes.
Thermal Shutdown When the junction temperature in the series pass power transistor QS reaches around 160°C, it is possible that the regulator may be damaged. Junction temperature may rise either due to selfheating or due to rise in ambient temperature. To prevent damage to the regulator at elevated junction temperatures, the thermal shutdown protection circuit is incorporated in a regulator (Figure 17.35). The temperature sensor (Q1) is placed near the series pass power transistor, in which the maximum dissipation occurs, to track temperature changes. Relay contact + + Regulated output
External circuit
Relay D1
D2
−
−
Figure 17.34 Reverse polarity protection to the external circuit + R To error ampliﬁer Vi IZ
+
R1
VZ D −
R2 −
IBS
QS Series pass power transistor
IC1
IL
Q1 + VBE1 −
+
Heat ﬂow RL
Vo −
Figure 17.35 Implementation of thermal shutdown
R1and R2 are chosen such that as long as the junction temperature is below 160°C, Q1 is OFF. D is an avalanche breakdown diode with breakdown voltage VZ and has a positive temperature coefficient. With increase in temperature, VZ increases and VBE1of Q1 increases. When the temperature reaches
Voltage Regulators
891
160°C, the drop across R2 will be sufficient enough to drive Q1 into saturation. A large current IC1 is diverted from the base of QS, and hence IBS is reduced, thereby reducing the junction temperature of QS. QS may even be driven into the OFF state.
17.6
A SERIES REGULATOR USING AN ERROR AMPLIFIER (FEEDBACK REGULATOR)
The circuit in Figure 17.36 is a series regulator with Q2 used as an error amplifier. The main advantages of using an error amplifier are (i) regulation improves and (ii) ripple in the output reduces. Ii + IR = IB1 + IC2 R4 Vi Unregulated input
IC1
+ VCE1 − Q1
− VBE1 + + VR3 − VB1 = VC2
IB1
IC2 + Q2 VCE2 − IE2 + VZ −
−
IB2 + V − BE2 IZ
+ VR1 R3
−
IL
+
R1 RL IR1
Vo −
IR3 + R2 V2 = βVo IR2 −
Figure 17.36 A series regulator with error amplifier
If, for any reason, Vi increases, VO increases. R1 and R2 comprise the sampling network. The R2 voltage V2 ( = VO = bVO ) increases. The current in the Zener diode is limited by R3 and VZ is R1 + R2 the Zener voltage. VBE2 = V2 − VZ, since VZ almost remains constant, VBE2 increases. Consequently, IB2 increases and hence IC2 increases. Increase in IC2 increases the drop across R4. Therefore, the voltage at the base of Q1 reduces and IB1 reduces. As a result IC1 = IL reduces. VO is brought back to the required value. Similarly, if Vi decreases, VO is once again brought back to the required value.
Calculation of VO From Figure 17.36, (17.52)
VO = VR1 + VBE2 + VZ VR1 = VO
R1 R1 + R2
(17.53)
Substituting Eqn. (17.53) in Eqn. (17.52), VO = VO
R1 + VBE2 + VZ R1 + R2
R1 ∴VO 1 − = VBE2 + VZ R1 + R2
Or
R2 VO = VBE2 + VZ R1 + R2
892
Electronic Devices and Circuits
R R + R2 VO = (VBE2 + VZ ) 1 = (VBE2 + VZ ) 1 + 1 R2 R2 R VO ≈ VZ 1 + 1 R2
(17.54)
(17.55)
VO can be more than the Zener voltage. VO can be adjusted by adjusting R1 and R2. The main advantages of this regulator are as follows: ∆VO (i) As Vi changes by ∆Vi , Vo changes by , where A is the voltage gain of the error amplifier. A This improves regulation. (ii) If Vg is the ripple in the output of a series regulator without error amplifier, then the ripple Vg in the output of this regulator is . Thus the ripple is appreciably reduced. A Adjusting the Output Voltage In the regulator circuit shown in Figure 17.36, VO is constant for given values of R1 and R2. If VZ = 7.5 V, VBE2 = 0.7 V, R1 = 2 kΩ, and R2 = 10 kΩ, 2 VO = ( 0.7 + 7.5) 1 + = 9.84 V 10 If VO is required to be 10 V, it is not possible with this arrangement, since R1 and R2 are chosen as standard values of resistances. Further, let R1 and R2 be resistors with 10 percent tolerance. Then R1 varies from R1(min) = 1.8 kΩ to R1(max) = 2.2 kΩ. Similarly, R2 varies from R2(min) = 9 kΩ to 1.8 R2(max) = 11 kΩ. Then, VO can vary between VO1 and VO2, where V01 = ( 0.7 + 7.5) 1 + = 9.54 V 11 2.2 = 10 . 20 V. and V0 2 = ( 0.7 + 7.5) 1 + 9 Thus, the output can vary due to tolerances of the resistances used. If the output needs to be adjusted to a desired voltage, then a potentiometer R5 is included as shown in Figure 17.37. IL
R1 A +
Q2 + VBE2 − + VZ −
R5
RL
B
VO −
R2
Figure 17.37 Adjusting the output voltage
From Eqn. (17.54), when only R1 and R2 are used, R + R2 VO = (VBE2 + VZ ) 1 R2
Voltage Regulators
893
If the centertap of R5 is adjusted to be at B, then VO is VO(max) and is given as follows: R + R5 + R2 VO(max ) = (VBE2 + VZ ) 1 R2
(17.56)
And if the center tap of R5 is adjusted to be at point A, then VO is VO(min) and is given as follows: R + R5 + R2 VO(min) = (VBE2 + VZ ) 1 R2 + R5
(17.57)
A complete series regulator with adjustable output is shown in Figure 17.38. Ii + IR = IB1 + IC2 R4 IB1
Vi Unregulated input
IC1
+ V