Electronic Devices and Circuits 9789339219635, 9339219635

Table of contents :
Title
Contents
1 INTRODUCTION
2 DIODES, CHARACTERISTICS, AND APPLICATIONS
3 RECTIFIERS AND FILTERS
4 TRANSISTOR CHARACTERISTICS
5 TRANSISTOR BIASING AND THERMAL STABILIZATION
6 SMALL-SIGNAL, LOW-FREQUENCY BJT AMPLIFIERS
7 FET CHARACTERISTICS, BIASING, AND FET AMPLIFIERS
8 MULTISTAGE AMPLIFIERS
9 FEEDBACK AMPLIFIERS
10 OSCILLATORS
11 POWER AMPLIFIERS
12 HIGH-FREQUENCY TRANSISTOR AND FET AMPLIFIERS
13 TUNED AMPLIFIERS
14 OPERATION ALAMPLIFIERS
15 APPLICATIONS OF OP-AMP
16 ACTIVE FILTERS
17 VOLTAGE REGULATORS
18 MULTIVIBRATORS
19 TIME-BASE GENERATORS
20 INTEGRATED CIRCUITS
21 555 TIMER AND APPLICATIONS
22 SPECIAL ELECTRONIC DEVICES, OPTOELECTRONIC DEVICES, AND MEASURING INSTRUMENTS
23 DIGITAL ELECTRONICS
24 MICROCOMPUTERS AND MICROPROCESSORS
APPENDIX A
APPENDIX B
APPENDIX C
INDEX

Citation preview

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Electronic Devices and Circuits

About the Authors K Venkata Rao obtained his BE (Telecommunications) and ME (Control Systems) degrees from Andhra University, Visakhapatnam, and PhD degree from University of Roorkee, Roorkee (now IIT Roorkee). He retired as Professor from Andhra University College of Engineering and has over 45 years of teaching and 25 years of research experience. He has published and presented 32 research articles in reputed international/national journals and conference proceedings respectively. He has received the S K Mitra Memorial Award for the best research-oriented paper published in JIETE in 1985. He is presently Director, Chaitanya Engineering College, Vishakhapatnam. He is a Life Fellow, IETE. K Rama Sudha received her BE degree in Electrical and Electronics Engineering from GITAM University (formerly known as GITAM college, Andhra University), in 1991. She obtained her ME degree in Power Systems 1994, and was awarded her doctorate in Electrical Engineering in 2006 by Andhra University. She has published and presented over 62 research articles in reputed international/national journals and conference proceedings. She has 19 years of teaching experience and 7 years of research experience. During 1994–2006, she worked with GITAM Engineering College and presently, she is working as Professor and Head in the Department of Electrical Engineering, AUCE(W), Andhra University, Visakhapatnam, India. She is a member of ISTE, IEEE and WIE.

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Electronic Devices and Circuits

K Venkata Rao Former Professor (Dept. of ECE), Andhra University Director, PG Programme Chaitanya Engineering College Visakhapatnam, Andhra Pradesh

K Rama Sudha Professor and Head Department of Electrical Engineering College of Engineering for Women Andhra University Visakhapatnam, Andhra Pradesh

McGraw Hill Education (India) Private Limited NEW DELHI McGraw Hill Education Offices New Delhi New York St Louis San Francisco Auckland Bogotá Caracas Kuala Lumpur Lisbon London Madrid Mexico City Milan Montreal San Juan Santiago Singapore Sydney Tokyo Toronto

McGraw Hill Education (India) Private Limited Published by McGraw Hill Education (India) Private Limited P-24, Green Park Extension, New Delhi 110 016 Visit us at: www.mheducation.co.in Electronic Devices and Circuits Copyright © 2015 by McGraw Hill Education (India) Private Limited. No part of this publication may be reproduced or distributed in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise or stored in a database or retrieval system without the prior written permission of the publishers. The program listings (if any) may be entered, stored and executed in a computer system, but they may not be reproduced for publication. This edition can be exported from India only by the publishers, McGraw Hill Education (India) Private Limited. Print Edition: ISBN (13): 978-93-329-0115-5 ISBN (10): 93-329-0115-5 eBook Edition: ISBN (13): 978-93-392-1963-5 ISBN (10): 93-392-1963-5 Managing Director: Kaushik Bellani Head—Products (Higher Education and Professional): Vibha Mahajan Assistant Sponsoring Editor: Koyel Ghosh Senior Editorial Researcher: Sachin Kumar Manager—Production Systems: Satinder S Baveja Assistant Manager—Editorial Services: Sohini Mukherjee Senior Production Executive: Suhaib Ali Senior Graphic Designer—Cover: Meenu Raghav Senior Publishing Manager (SEM & Tech. Ed.): Shalini Jha Assistant Product Manager (SEM & Tech. Ed.): Tina Jajoriya General Manager—Production: Rajender P Ghansela Manager—Production: Reji Kumar Information contained in this work has been obtained by McGraw Hill Education (India), from sources believed to be reliable. However, neither McGraw Hill Education (India) nor its authors guarantee the accuracy or completeness of any information published herein, and neither McGraw Hill Education (India) nor its authors shall be responsible for any errors, omissions, or damages arising out of use of this information. This work is published with the understanding that McGraw Hill Education (India) and its authors are supplying information but are not attempting to render engineering or other professional services. If such services are required, the assistance of an appropriate professional should be sought. Typeset at Mukesh Technologies Pvt. Ltd., Puducherry, India 605 008 and printed at Cover Printer:

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Dedicated to my wife Yasoda K Venkata Rao

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Contents Preface

xxv

1. Introduction 1.1 Introduction 1 1.1.1 Resistors 1 1.1.2 Capacitors 5 1.1.3 Inductors 11 1.2 The Nature of Atom 12 1.2.1 Energy Levels 13 1.3 Electronic Structure of the Elements 16 1.3.1 Energy Band Theory of Crystals 17 1.3.2 Insulators, Conductors, and Semiconductors 18 1.4 Semiconductors 19 1.4.1 Intrinsic or Pure Semiconductors 19 1.4.2 Conduction in Intrinsic Semiconductors 21 1.4.3 Fermi Level in an Intrinsic Semiconductor 21 1.4.4 Calculation of the Intrinsic Fermi Energy 23 1.4.5 Mass Action Law 24 1.4.6 Extrinsic Semiconductors 24 1.4.7 Conductivity of Semiconductor Materials 27 1.4.8 Drift Current 29 1.4.9 Diffusion Current 30 1.4.10 Einstein’s Relationship 31 1.4.11 Mean Lifetime and Diffusion Lengths of Charge Carriers 1.4.12 The Continuity Equation 32 1.4.13 The Hall Effect 33 1.4.14 Basic Unbiased PN Junction 34 Additional Solved Examples 36 Summary 38 Multiple Choice Questions 39 Short Answer Questions 41 Long Answer Questions 42 Unsolved Problems 42

1

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2. Diodes, Characteristics, and Applications

43

2.1 PN Junction Diode 43 2.1.1 Forward Bias 45 2.1.2 Reverse Bias 46 2.2 Analysis of the Diode Circuit 53 2.2.1 Numerical Method 53 2.2.2 Graphical Method 54 2.3 Junction Capacitances 58 2.3.1 Diffusion or Storage Capacitance, CD 58 2.4 Some Important Diode Parameters 64 2.5 Breakdown Diodes 65 2.5.1 Zener Diode 65 2.5.2 Avalanche Diode 66 2.6 Clipping Circuits 67 2.6.1 One-Level Clippers 67 2.6.2 Two-Level Clippers 72 2.7 Clamping Circuits 75 2.7.1 Working of a Clamping Circuit 75 2.7.2 Practical Clamping Circuit 76 2.7.3 Biased Clamping Circuits 77 2.7.4 Clamping Circuit Theorem 79 2.8 Tunnel Diode 80 2.9 Varactor Diode 85 2.10 Schottky Barrier Diode 89 2.10.1 Ohmic Contact 89 2.10.2 Rectifying Contact 90 2.11 Semiconductor Photodiode 91 2.12 PIN Diode 94 2.13 Back Diode or Backward Diode 96 2.14 Gunn Diode 96 2.15 IMPATT Diode 97 Additonal Solved Examples 99 Summary 103 Multiple Choice Questions 104 Short Answer Questions 106 Long Answer Questions 107 Unsolved Problems 107

3. Rectifiers and Filters 3.1 Introduction 108 3.2 Rectifiers 109

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3.2.1 Half-Wave Rectifier 109 3.2.2 Full-Wave Rectifier 115 3.2.3 Full-Wave Bridge Rectifier 120 3.3 Filters 122 3.3.1 Half-Wave Rectifier with Inductor Filter 122 3.3.2 Full-Wave Rectifier with Inductor Filter 124 3.3.3 Half-wave Rectifier with Capacitor Filter 127 3.3.4 Full-Wave Rectifier with Capacitor Filter 129 3.3.5 Full-Wave Rectifier with LC Filter 131 3.4 Multiple Cascaded Filters 135 3.4.1 Two Stages of an LC Filter 135 3.4.2 π-Filter or CLC Filter 136 3.4.3 Full-Wave Rectifier with CRC Filter 137 3.5 Power Supply Performance 138 Additional Solved Examples 139 Summary 148 Multiple Choice Questions 148 Short Answer Questions 149 Long Answer Questions 150 Unsolved Problems 150

4. Transistor Characteristics 4.1 4.2 4.3 4.4

4.5 4.6

4.7

4.8 4.9

Junction Transistor 151 Transistor Current Components 154 Transistor as an Amplifier 157 Basic Transistor Configurations 157 4.4.1 Common Base Configuration 158 4.4.2 Common Emitter Configuration 163 4.4.3 Common Collector Configuration 169 Analytical Expressions for Transistor Characteristics 172 Maximum Transistor Junction Voltages 177 4.6.1 Reach Through or Punch Through in a Transistor 177 4.6.2 Avalanche Multiplication 177 Transistor Construction 180 4.7.1 Grown Junction-Type Transistor 180 4.7.2 Alloy Junction-Type Transistor 180 4.7.3 Diffusion-Type Transistor 181 4.7.4 Epitaxial-Type Transistor 182 BJT Specifications 182 Phototransistor 182

Additional Solved Examples Summary 192

183

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Multiple Choice Questions 192 Short Answer Questions 193 Long Answer Questions 194 Unsolved Problems 194

5. Transistor Biasing and Thermal Stabilization

195

5.1 Introduction 195 5.2 The Three Methods of Biasing a Transistor 195 5.2.1 Forward–Forward Biasing 195 5.2.2 Reverse–Reverse Biasing 196 5.2.3 Forward–Reverse Biasing 196 5.3 Bias Stability 200 5.4 Methods of Biasing a Transistor 201 5.4.1 Fixed Bias 202 5.4.2 Emitter Bias 204 5.4.3 Collector-to-Base Bias or Collector Feedback Bias 211 5.4.4 Voltage Divider Bias or Self-Bias 213 5.5 CB Configuration 219 5.6 CC Configuration 220 5.7 Bias Compensation 221 5.7.1 Diode Compensation 221 5.7.2 Thermistor Compensation 222 5.7.3 Sensistor Compensation 223 5.8 Integrated Circuit Biasing 224 5.9 Combination of Voltage Divider and Collector-to-Base Bias 224 5.10 Emitter Current Bias 226 5.11 Thermal Resistance 226 Additional Solved Examples 227 Summary 239 Multiple Choice Questions 239 Short Answer Questions 240 Long Answer Questions 241 Unsolved Problems 241

6. Small-Signal, Low-Frequency BJT Amplifiers 6.1 6.2 6.3 6.4 6.5 6.6

Introduction 242 The Location of the Operating Point 242 Sketching the AC Circuit of the Amplifier 244 Small-Signal, Low-Frequency Model of the Transistor Analysis of a CE Transistor Amplifier 249 Simplified Equivalent Circuit of the Transistor 255

242

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6.7 6.8 6.9 6.10

6.11

6.12 6.13 6.14 6.15 6.16 6.17 6.18

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Analysis of CC Amplifier 256 Analysis of CB Amplifier 260 Comparison of Performance of CE, CC, and CB Amplifiers 261 Relevance of Input and Output Resistances 262 6.10.1 Voltage Amplifier 262 6.10.2 Current Amplifier 263 6.10.3 Transconductance Amplifier 263 6.10.4 Transresistance Amplifier 263 Distortion in an Amplifier 264 6.11.1 Harmonic Distortion 264 6.11.2 Noise 265 6.11.3 Intermodulation Distortion 266 Transconductance Model of the Transistor 266 Frequency Response Characteristic of an Amplifier 267 Transistor h -Parameter Conversion 270 6.14.1 CE h-Parameters in Terms of CB h-Parameters 270 CE Amplifier with Un-bypassed Emitter Resistance 276 Miller’s Theorem and Its Dual 278 Analysis of the Amplifier Circuit Using the Dual of the Miller’s Theorem 281 Analysis of the Amplifier Circuit Using the Miller’s Theorem 283

Additional Solved Examples 285 Summary 296 Multiple Choice Questions 297 Short Answer Questions 299 Long Answer Questions 299 Unsolved Problems 299

7. FET Characteristics, Biasing, and FET Amplifiers 7.1 7.2 7.3 7.4 7.5 7.6 7.7

Introduction 301 Construction of JFET 302 Characteristic Curves of JFET 303 Plotting the Transfer Characteristic Using Shockley’s Equation 306 Parameters of the FET and Their Interrelationship 307 Theoretical Determination of gm 308 MOSFETs 311 7.7.1 Depletion-Type MOSFETs 311 7.7.2 Enhancement-Type MOSFETs 314 7.7.3 Characteristics of an n-Channel Enhancement-Type MOSFET 315 7.7.4 Characteristics of a p-Channel Enhancement-Type MOSFET 317 7.8 Biasing JFETs 317 7.8.1 Fixed Bias 318

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7.9 7.10 7.11

7.12 7.13

7.8.2 Self-Bias 320 7.8.3 Voltage Divider Bias 324 7.8.4 The Drain Feedback Bias 328 Universal Transfer Characteristic or the Universal Bias Curve 328 FET as a Voltage Variable Resistance or Voltage-Controlled Resistance FET Amplifiers 334 7.11.1 Common Source Amplifier 334 7.11.2 CS Amplifier with Un-bypassed RS 337 7.11.3 CD Amplifier or Source Follower 340 7.11.4 CG Amplifier 343 Comparison of Performance of the Three Configurations 346 Comparison of BJT and FET Amplifiers 347

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Additional Solved Problems 347 Summary 358 Multiple Choice Questions 358 Short Answer Questions 360 Long Answer Questions 360 Unsolved Problems 361

8. Multistage Amplifiers 8.1 Introduction 363 8.2 Compound Amplifiers 364 8.2.1 CE–CC Amplifier 364 8.2.2 CE–CE Amplifier 368 8.2.3 CE–CB Amplifier or Cascode Amplifier 372 8.3 Miller Effect 373 8.3.1 CC–CC Amplifier 374 8.3.2 Biasing a Darlington Emitter Follower 378 8.4 Multistage Amplifiers 380 8.5 RC-Coupled Amplifier Using a BJT 381 8.5.1 Gain in the Mid-Band 382 8.5.2 Gain in the Low-Frequency Range 383 8.5.3 Gain in the High-Frequency Range 384 8.6 RC-Coupled Amplifier Using FET 386 8.6.1 Mid-Band Range 386 8.6.2 Low-Frequency Range 387 8.6.3 High-Frequency Range 388 8.7 Effect of CE on the Low-Frequency Response of CE Amplifier Assuming CC to be Sufficiently Large 388 8.8 Bandwidth of n-Identical Multistage Amplifiers 392 8.9 Transformer-Coupled Amplifier 393 8.10 Direct-Coupled Amplifiers 395

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Additional Solved Examples 397 Summary 420 Multiple Choice Questions 421 Short Answer Questions 422 Long Answer Questions 422 Unsolved Problems 422

9. Feedback Amplifiers

424

9.1 Introduction 424 9.2 The Feedback Amplifier 425 9.2.1 Sampling Network 425 9.2.2 b -Network 426 9.2.3 Mixing Network 427 9.3 Calculation of the Gain of the Feedback Amplifier 428 9.4 Advantages of Negative Feedback 433 9.4.1 Improved Gain Stability 433 9.4.2 Improved Bandwidth 434 9.4.3 Reduced Harmonic Distortion 436 9.4.4 Reduced Noise 438 9.4.5 Disadvantage with Negative Feedback in an Amplifier 438 9.5 Calculation of Input Resistance of a Feedback Amplifier 439 9.5.1 Calculation of the Input Resistance with Series Mixing 439 9.5.2 Calculation of the Input Resistance with Shunt Mixing 441 9.6 Calculation of Output Resistance of the Feedback Amplifier 443 9.6.1 Calculation of the Output Resistance with Voltage Sampling 443 9.6.2 Calculation of the Output Resistance with Current Sampling 446 9.7 Assumptions Made in the Analysis of Feedback Amplifiers 448 9.8 Reducing a Feedback Amplifier Circuit into an Amplifier Circuit without Feedback 449 9.9 Method of Analysis of Feedback Amplifiers 451 9.10 Analysis of Voltage Series Feedback Amplifier 453 9.11 Analysis of Current Series Feedback Amplifier 457 9.12 Analysis of Voltage Shunt Feedback Amplifier 461 9.13 Analysis of Current Shunt Feedback Amplifier 465 9.14 Voltage Series Feedback Pair 470 9.15 Some Circuit Variations 473 Additional Solved Examples 475 Summary 488 Multiple Choice Questions 488 Short Answer Questions 489 Long Answer Questions 490 Unsolved Problems 490

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10. Oscillators 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.11 10.12 10.13 10.14 10.15

491

Introduction 491 LC Oscillators 493 Colpitts Oscillator 497 Hartley Oscillator 500 Clapp Oscillator 502 Tuned-Collector Oscillator 503 RC Oscillators 506 Wien Bridge Oscillator 507 RC Phase Shift Oscillator Using FET 509 RC Phase-Shift Oscillator Using a BJT 511 Amplitude Stability in Oscillators 516 Frequency Stability in Oscillators 516 Crystal Oscillators 517 Beat Frequency Oscillator 519 Exact Analysis of Colpitts and Hartley Oscillators 520 10.15.1 Colpitts Oscillator 522 10.15.2 Hartley Oscillator 524

Additional Solved Examples 525 Summary 534 Multiple Choice Questions 534 Short Answer Questions 535 Long Answer Questions 536 Unsolved Problems 536

11. Power Amplifiers 11.1 Introduction 537 11.2 Distortion in Power Amplifiers 539 11.3 Class-A Power Amplifier 540 11.3.1 Series-Fed Class-A Power Amplifier 540 11.3.2 Class-A Transformer-Coupled Power Amplifier 547 11.3.3 Class-A Push–Pull Power Amplifier 555 11.4 Class-B Push–Pull Power Amplifier 557 11.4.1 Calculation of the Conversion Efficiency 558 11.4.2 Cross-Over Distortion 559 11.4.3 Dissipation in each Transistor of a Class-B Push–Pull Power Amplifier 11.4.4 Determining the Turns Ratio of the Output Transformer, To 561 11.4.5 Determining the Turns Ratio of the Input Transformer, Ti 562 11.4.6 Advantages of Class-B Push–Pull Power Amplifier 565 11.4.7 Disadvantages of Class-B Push–Pull Power Amplifier 565

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11.5 11.6 11.7 11.8

Class-B Push–Pull Power Amplifier That Eliminates the Transformer 565 Complementary Symmetry Push–Pull Class-B Power Amplifier 566 Heat Sinks 568 A Class-D Power Amplifier 570 11.8.1 Class-D Amplifier Using Complementary Transistors 570 11.8.2 A Class-D Amplifier Using Center-Tapped Transformer and NPN Transistors 571 11.9 Class-S Amplifier 574 Additional Solved Examples 575 Summary 588 Multiple Choice Questions 588 Short Answer Questions 590 Long Answer Questions 590 Unsolved Problems 590

12. High-Frequency Transistor and FET Amplifiers 12.1 12.2 12.3 12.4 12.5

12.6 12.7 12.8

12.9 12.10 12.11

Introduction 592 The Miller Capacitances 593 CE Amplifier: Influence of Network Parameters at High Frequencies 594 High-Frequency Equivalent Circuit of the Transistor 595 Calculation of High-Frequency Parameters in Terms of the Low-Frequency Parameters 596 12.5.1 The Transconductance, gm 596 12.5.2 Input Conductance, gb¢e 597 12.5.3 Feedback Conductance, gb¢c 598 12.5.4 The Base-Spreading Resistance, rbb¢ 599 12.5.5 Output Conductance gce 600 CE Short-Circuit Current Gain 601 CE Current Gain with Resistive Load 606 Hybrid p Capacitances 609 12.8.1 The Collector Junction Capacitance Cc 609 12.8.2 The Emitter Junction Capacitance Ce 610 12.8.3 Validity of the Hybrid p Model 612 Common Collector Amplifier (Emitter Follower) at High Frequencies 612 CB Amplifier at High Frequencies 616 High-Frequency FET Circuits 620 12.11.1 CS Amplifier at High Frequencies 620 12.11.2 Common Drain Amplifier at High Frequencies 623

Additional Solved Examples 626 Summary 641 Multiple Choice Questions 641

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Contents

Short Answer Questions 642 Long Answer Questions 642 Unsolved Problems 643

13. Tuned Amplifiers 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8

13.9

13.10 13.11 13.12

644

Introduction 644 Quality Factor, Q of L and C 646 Single-Tuned Capacitive-Coupled Voltage Amplifier 647 Bandwidth of n Identical Cascaded Tuned Amplifiers 654 Inductively Coupled Tuned Primary BJT Amplifier 655 Inductively Coupled Tuned Secondary FET Amplifier 661 Impedance Adjustment with Tapped Circuits 664 Double-Tuned Amplifiers 667 13.8.1 Synchronously Tuned Double-Tuned Amplifier 667 13.8.2 Stagger-Tuned Amplifier 676 Instability in Tuned Amplifiers 678 13.9.1 Unilateralization 678 13.9.2 Mismatching Technique 679 13.9.3 Neutralization 679 Tuned Power Amplifiers 680 Tuned Class-C Power Amplifier 681 13.11.1 Applications of Class C Tuned Amplifiers 685 Wideband or Compensated Amplifier 687

Additional Solved Examples 693 Summary 702 Multiple Choice Questions 702 Short Answer Questions 703 Long Answer Questions 704 Unsolved Problems 704

14. Operational Amplifiers 14.1 Introduction 706 14.2 Differential Amplifier 707 14.2.1 DC Analysis 709 14.2.2 AC Analysis 710 14.2.3 Theoretical Calculation of r of a Differential Amplifier 711 14.2.4 Differential Amplifier Supplied with Constant Current 713 14.2.5 Transfer Characteristic of the Differential Amplifier 716 14.2.6 Dual-Input, Unbalanced-Output Differential Amplifier 718 14.2.7 Methods to Improve the Input Resistance 719 14.2.8 Methods to Derive Large Gain 721 14.2.9 Cascaded Differential Amplifier 722

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14.3 14.4 14.5 14.6 14.7 14.8

DC-Level Shifter 723 Output Power Stage 724 DC Characteristics of an Op-Amp 725 AC Characteristics of an Op-Amp 727 Frequency Stability in Op-Amps 730 Frequency Compensation in Op-Amps 732 14.8.1 External Frequency Compensation 732 14.8.2 Internal Compensation 734 14.9 Ideal Characteristics of an Op-Amp 734 14.9.1 Concept of Virtual Ground in an Op-Amp 735 14.9.2 Balancing an Op-Amp 735 14.10 Bias Compensation in an Op-Amp 736 14.11 Measurement of Op-Amp Parameters 738 14.11.1 Open-Loop Differential Voltage Gain, Ad 738 14.11.2 Output Resistance, Ro 738 14.11.3 Differential Input Resistance, Ri 739 14.11.4 Input Offset Voltage, Vio 739 14.11.5 Input Bias Current, IB 740 14.11.6 Input Offset Current, Iio 740 14.11.7 Slew Rate, S 740 14.11.8 Common-Mode Rejection Ratio, r 742 14.12 Differential Amplifier Using FET 743 Additional Solved Examples 744 Summary 745 Multiple Choice Questions 746 Short Answer Questions 747 Long Answer Questions 747 Unsolved Problems 747

15. Applications of Op-Amp 15.1 Introduction 749 15.2 Linear Applications of Op-Amp 749 15.2.1 Inverting Amplifier 749 15.2.2 Scale Changer 754 15.2.3 Sign Changer and Phase Changer 754 15.2.4 Non-inverting Amplifier 754 15.2.5 Buffer Amplifier 757 15.2.6 Summing Amplifier or Adder 758 15.2.7 Subtracting Amplifier or Differential Amplifier 15.2.8 Adder-Subtractor 763 15.2.9 Integrator 767 15.2.10 Differentiator 773

749

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15.2.11 Instrumentation Amplifier 779 15.2.12 Voltage-to-Current Converter 783 15.2.13 Current-to-Voltage Converter 785 15.3 Nonlinear Applications 786 15.3.1 Monostable Multivibrator Using Op-Amp 15.3.2 Astable Multivibrator 788 15.3.3 Triangular Wave Generator 791 15.3.4 Comparator 791 15.3.5 Schmitt Trigger 798 15.3.6 Logarithmic Amplifier 800 15.3.7 Antilog Amplifier 802 15.3.8 Multiplier 805 15.3.9 Divider 806 15.3.10 Precision Rectifiers 807

786

Additional Solved Examples 812 Summary 816 Multiple Choice Questions 816 Short Answer Questions 819 Long Answer Questions 820 Unsolved Problems 820

16. Active Filters 16.1 Introduction 822 16.2 Passive Low-Pass, High-Pass, and Band-Pass Filters 823 16.2.1 Low-Pass Filter 823 16.2.2 High-Pass Filter 825 16.2.3 Band-Pass Filter 827 16.3 Active Filters 827 16.3.1 Classification of Active Filters 828 16.3.2 Butterworth Filter 829 16.3.3 Band-Pass Filter 842 16.3.4 Band-Rejection Filter 849 16.3.5 All-pass Filter 855 16.3.6 Switched Capacitor Filter 856 Additional Solved Examples 860 Summary 862 Multiple Choice Questions 863 Short Answer Questions 864 Long Answer Questions 864 Unsolved Problems 864

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17. Voltage Regulators

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17.1 Introduction 865 17.2 Classification of Voltage Regulators 867 17.3 Shunt Regulators 868 17.3.1 Zener Diode as a Shunt Regulator 868 17.3.2 Basic Transistor Shunt Regulator 874 17.4 Series Regulators 878 17.4.1 Transistor Series Regulator 878 17.4.2 Improved Series Regulator 882 17.5 Overload and Short-circuit Protection in Regulators 883 17.5.1 Constant Current Limiting in a Series Regulator 883 17.5.2 Fold-Back Current Limiting in a Series Regulator 885 17.6 A Series Regulator Using an Error Amplifier (Feedback Regulator) 891 17.7 IC Regulators 896 17.7.1 Linear IC Regulators 896 17.7.2 Switching Regulators 904 17.8 Voltage Multipliers 910 17.8.1 Half-Wave Voltage Doubler 911 17.8.2 Full-Wave Voltage Doubler 913 Additional Solved Examples 917 Summary 927 Multiple Choice Questions 927 Short Answer Questions 929 Long Answer Questions 930 Unsolved Problems 930

18. Multivibrators 18.1 Introduction 932 18.2 Transistor as a Switch 933 18.2.1 Switching Times of the Transistor 936 18.3 Bistable Multivibrators 937 18.4 Fixed Bias Binary 937 18.4.1 Calculation of the Stable-State Currents and Voltages 938 18.4.2 Heaviest Load the Binary Can Drive 941 18.4.3 Collector-Catching Diodes 943 18.5 Resolution Time and Maximum Switching Speed of the Binary 947 18.6 Methods of Triggering a Binary 952 18.6.1 Unsymmetric Triggering 952 18.6.2 Symmetric Triggering 953 18.6.3 Nonsaturating Binary 955

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18.7 Self-Bias Binary 956 18.8 Monostable Multivibrators 963 18.8.1 Collector-Coupled Monstable Multivibrator 963 18.8.2 Calculation of Stable-State Currents and Voltages 967 18.8.3 Voltage-to-Time Converter 976 18.9 Astable Multivibrator 978 18.9.1 Calculation of the Time Period T2 for Which Q2 is OFF 979 18.9.2 Condition for the ON Transistor to be in Saturation 982 18.9.3 Recovery Time of Symmetric Astable Multivibrator 983 18.9.4 Voltage-to-Frequency Converter 986 18.9.5 Astable Multivibrator with Vertical Edges for the Collector Waveforms 18.10 Schmitt Trigger 988 18.10.1 Elimination of Hysteresis in Schmitt Trigger 997 18.10.2 Applications of Schmitt Trigger 998

987

Additional Solved Examples 998 Summary 1000 Multiple Choice Questions 1001 Short Answer Questions 1003 Long Answer Questions 1003 Unsolved Problems 1004

19. Time-Base Generators

1005

19.1 Introduction 1005 19.2 Voltage Sweep Generators 1006 19.2.1 Exponential Sweep Generator 1006 19.2.2 Miller’s Sweep Generator 1019 19.2.3 Bootstrap Sweep Generator 1022 19.3 Current Sweep Generators 1026 19.3.1 Linear Current Sweep by Adjusting the Driving Waveform 19.3.2 Generation of Trapezoidal Waveform 1029

1028

Additional Solved Examples 1031 Summary 1034 Multiple Choice Questions 1034 Short Answer Questions 1036 Long Answer Questions 1037 Unsolved Problems 1037

20. Integrated Circuits 20.1 Introduction 1038 20.1.1 Classification of ICs

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20.2 The Monolithic Integrated Circuit 1039 20.2.1 Fabrication of an NPN Transistor 1040 20.2.2 Fabrication of the Diode 1042 20.2.3 Fabrication of Capacitor 1043 20.2.4 Fabrication of Resistors 1043 20.3 Fabrication of a Typical Circuit as a Monolithic IC 1044 20.4 Package Types of ICs 1048 20.5 IC Transistor Amplifier 1050 20.6 Fabrication of NMOS ICs 1051 20.6.1 Simple Fabrication of IC MOS Transistors 1052 20.6.2 MOS Transistor as a Resistor 1052 Summary 1053 Multiple Choice Questions 1053 Short Answer Questions 1054 Long Answer Questions 1054

21. 555 Timer and Applications

1055

21.1 Introduction 1055 21.1.1 Pin Details 1055 21.2 Operating Modes of 555 Timer 1057 21.2.1 555 Timer as a Monostable Multivibrator 1057 21.2.2 555 Timer as Astable Multivibrator 1061 21.2.3 Some Other Applications 1069 21.2.4 556 Dual Timer 1076 Additional Solved Examples 1077 Summary 1080 Multiple Choice Questions 1080 Short Answer Questions 1082 Long Answer Questions 1082 Unsolved Problems 1082

22. Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments 22.1 Power Electronic Devices 1085 22.1.1 Silicon-Controlled Rectifier 1085 22.1.2 TRIAC 1092 22.1.3 DIAC 1094 22.1.4 The Gate Turn-Off Thyristor or GTO Thyristor 1096 22.1.5 Light-Activated SCR or Photo SCR 1096 22.1.6 Light-Activated TRIAC or Photo TRIAC 1096

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22.2 Optoelectronic Devices 1097 22.2.1 Photoconductivity 1097 22.2.2 Photodetectors 1099 22.3 Optocouplers 1107 22.3.1 Photodiode Optocoupler 1108 22.3.2 Cold Cathode or Nixie Displays 1109 22.3.3 Seven-Segment LED Display 1110 22.3.4 Liquid Crystal Display 1112 22.3.5 Plasma Display Panels 1114 22.4 Fiber Optics 1114 22.4.1 Refractive Index 1115 22.4.2 Types of Optical Fibers 1117 22.4.3 Optical Communication Link 1120 22.5 Measuring Instruments 1121 22.5.1 DC Ammeter 1121 22.5.2 DC Voltmeter 1125 22.5.3 Multirange Voltmeter 1125 22.5.4 Moving-Iron Instruments 1126 22.5.5 Moving-Iron Voltmeter 1127 22.5.6 Ohm Meter 1127 22.5.7 Multimeter 1128 22.5.8 Electronic Voltmeters 1129 22.5.9 Digital Voltmeters 1133 22.5.10 Energy Meter 1138 22.5.11 Digital Frequency Meter 1140 22.5.12 Cathode Ray Oscilloscope 1145 Summary 1150 Multiple Choice Questions 1151 Short Answer Questions 1155 Long Answer Questions 1155 Unsolved Problems 1156

23. Digital Electronics Scan the QR Code given here to Access the Full Chapter. 23.1 Introduction 23.2 Binary Logic 23.2.1 Conversion of a Binary Number into a Decimal Number 23.2.2 Conversion of Decimal Number into Binary 23.3 Unsigned Numbers 23.4 Representation of Negative Numbers 23.5 Subtraction Using Complement Methods

1157

Contents

23.6 23.7 23.8 23.9 23.10 23.11 23.12 23.13 23.14 23.15 23.16 23.17 23.18 23.19

xxiii

Octal and Hexadecimal Representation Boolean Algebra Theorems Simplification of Boolean Functions De Morgan’s Laws Boolean Expressions in Sum of Products Form and in Product of Sums Form Universal Gates Exclusive OR Gate Realization of Logic Functions Using NAND Gates Realization of Logic Functions Using NOR Gates Karnaugh Map Don’t Care Conditions Logic Gates A/D and D/A Converters

Additional Solved Examples Summary Multiple Choice Questions Short Answer Questions Long Answer Questions Unsolved Problems

24. Microcomputers and Microprocessors Scan the QR Code given here to Access the Full Chapter. 24.1 Evolution of Microprocessor 24.2 Salient Features of 8085 Microprocessor 24.3 8085 Bus Structure 24.4 Internal Architecture of 8085 Microprocessor 24.4.1 Register Array 24.4.2 Arithmetic Logic Unit 24.4.3 Timing and Control Unit 24.4.4 Interrupt Control 24.4.5 Serial I/O Control 24.5 Microcomputer Languages 24.5.1 Machine Language 24.5.2 Assembly Language 24.5.3 High-Level Language 24.6 Instruction Set 24.6.1 Operation Code and Operand 24.7 Classification of Instruction Set 24.7.1 Data-Transfer Group

1208

xxiv

Contents

24.8

24.9

24.10 24.11

24.7.2 Arithmetic Operations 24.7.3 Logical Operations 24.7.4 Branching Operations 24.7.5 Stack, I/O, and Machine Control Group The 8085 Addressing Modes 24.8.1 Direct Addressing 24.8.2 Register Addressing 24.8.3 Register Indirect Addressing 24.8.4 Immediate Addressing 24.8.5 Implicit Addressing Instruction Formats 24.9.1 Single-Byte Instructions 24.9.2 Two-Byte Instructions 24.9.3 Three-Byte Instructions 16-Bit Microprocessor Differences between 8085 and 8086

Additional Solved Examples Summary Multiple Choice Questions Short Answer Questions Unsolved Problems

Appendix A Appendix B Appendix C

1232 1236 1261

Index

1267

Preface Understanding the principles of workings of various electronic devices, and the ability to analyze electronic circuits are the pre-requisites for further learning in the fields of electronics, instrumentation, communications and power electronics. Amplifiers, oscillators, sweep generators, multivibrators, A/D converters and D/A converters, etc., eventually become the subsystems of either an analog or a digital system.

Rationale behind Writing the Book There are many standard books on these topics. However, the experience of the authors has shown that the present-day student wants books that give emphasis to neat and crisp circuit presentations that help him/her understand the underlying principles better. In reality, some students are even reluctant to consult the prescribed textbooks, and prefer to look for shortcuts. Therefore, in trying to address the needs of the students, the authors, with their vast experience in teaching, have made a genuine attempt in this book to provide solutions to circuit simplifications that enable readers to appreciate the nuances in circuit analysis. This will help students understand the principles better and thus will sustain their interest in the subject.

Target Readers Initially, the authors aimed to limit the scope of this book to the syllabi prescribed by only certain universities. However, the scope has been expanded to meet the requirements of many other universities. Therefore, it is obvious that this single book caters to the curriculum requirements of many Indian universities. Undergraduate students of ECE, EEE, Instrumentation and Computer Science branches will find this book very useful, mainly because of the method of presentation of the content with relevant tips for circuit simplification and analysis. Further, this book will also be very useful for practicing engineers as a quick reference since it deals with a wide variety of topics. This book additionally, to a large extent, addresses the needs of those who appear for competitive examinations like IES, UPSC, GATE, etc.

Salient Features of this Book • •

Simplification of circuits presented in a systematic fashion, which may be termed the biggest asset of this book Thorough coverage of devices and analyses of electronic circuits

xxvi • • •

Preface

Diagrammatic exposition of subject matter with elaborate analysis and necessary derivations Dedicated chapter on integrated circuits with classifications, fabrication, etc. Excellent pedagogy: • 923 illustrations • 570 Solved examples • 655 Review questions • 215 Review numerical problems • 700 Multiple choice questions with answers

Use of Technology In bringing out this edition, we have taken advantage of the recent technological developments to create a wealth of useful information not present in the physical book. For students using smart phones and tablets, scanning QR codes located within the chapters give them immediate access to more resources. The QR code appearing in chapters 23 and 24 give students access to the full chapters.

Organization of Chapters This book contains 24 chapters. Chapter 1 deals with identification of R, L and C components and considers them as circuit elements that can be connected either in series or in parallel. This chapter also deals with the atomic structure of elements, and classification of elements as conductors, insulators and semiconductors. Intrinsic semiconductors and P- and N-type extrinsic semiconductors are considered. The behaviour of an unbiased junction diode is also presented. Chapter 2 considers the V-I characteristics and equivalent circuits of a junction diode and the application of the PN junction diode in clipping and clamping circuits. This chapter also discusses the principles of working of some special-purpose diodes, their characteristics and typical applications, such as tunnel diode, varactor diode, Schottky barrier diode, PIN diode, photo diode, Gunn diode and IMPATT diode. Chapter 3 considers the application of diodes in rectifiers to convert ac to dc. The analysis of half-wave and full-wave rectifiers is presented. Also, various types of filters that help in reducing ripple like a capacitor input filter, inductor filter, L-type filter and π-type filter are presented. Chapter 4 talks about the principle of working of the bipolar junction transistor and also considers the three basic configurations, namely, common emitter, common base and common collector. Operating the transistor in the active, saturation and cut-off regions is discussed. The current gains in the three configurations are compared. The principle of working of a phototransistor is also discussed. Chapter 5 deals with the various biasing techniques, namely, fixed bias, emitter bias, voltage divider bias, collector-to-base feedback bias and also IC bias. The performance of these biasing methods, vis-a-vis the stability of the operating point is discussed. Also, bias-compensation methods like diode compensation, thermistor compensation and sensistor compensation are illustrated.

Preface

xxvii

Chapter 6 considers the use of a BJT as a small-signal amplifier. The procedure to draw the dc and ac circuits is presented. The graphical analysis of a CE amplifier using the output characteristics, dc and ac load lines is presented. Analysis of the three basic amplifier configurations using the small-signal, low-frequency model of the transistor in terms of h-parameters is discussed and their performance quantities are compared. The effect of noise and distortion on the performance of the amplifier is also presented. Chapter 7 deals with the principle of working of JFETs and MOSFETs and their characteristics. The various biasing methods and the design procedures are presented. Further, the small-signal model of the FET and the analysis of the three amplifiers, namely, common source, common drain and common gate amplifiers is presented and their performances are compared. Chapter 8 discusses about the need for compound amplifiers like CE-CE, CC-CE, CC-CC, etc. and shows the advantage of these amplifiers in deriving the necessary characteristics. In addition, the various inter-stage coupling methods like RC coupling, transformer coupling and direct coupling are presented. Analysis of both BJT and FET RC coupled amplifiers is carried out and the frequency response characteristic is presented to calculate the bandwidth. Finally, the bandwidth of an n-stage RC coupled amplifier is calculated. Chapter 9 presents the need for negative feedback in an amplifier and the expression for the gain of a feedback amplifier is derived. Also, the advantages of negative feedback in an amplifier like improved gain stability, reduced harmonic distortion and noise, improved bandwidth are also considered. In addition, the way in which the input and output impedances in a feedback amplifier change depending on the type of mixing and method of sampling is discussed. Analysis of the four basic feedback amplifiers, namely, voltage series, current series, voltage shunt and current shunt feedback amplifier is presented in detail. Chapter 10 considers Colpitts, Hartley, Clapp and tuned collector oscillators under the category of RF LC oscillators and Wien-bridge and RC phase shift oscillators under the category of audio frequency RC sinusoidal oscillators. Crystal oscillators that give better frequency stability as RF oscillators are considered. Finally, a beat frequency oscillator that provides better frequency stability of low-frequency oscillations is considered. Chapter 11 covers large signal amplifiers which are also called power amplifiers. Graphical method of analysis is presented and the procedure to calculate the output power, conversion efficiency and harmonic distortion is considered in detail for Class A and Class B power amplifiers. In addition, a transformer-less complementary symmetry push-pull power amplifier, Class D and Class S amplifiers are presented. Finally, the need for heat sinks is discussed. Chapter 12 deals with the high-frequency behaviour of BJT and FET. Analysis of CE, CC and CB amplifiers and also CS and CD amplifiers is carried out using the high-frequency models of the transistor and FET. Chapter 13 considers the need for tuned amplifiers, and the expressions for the voltage gain and bandwidth of single-tuned capacitor-coupled tuned amplifier, synchronously tuned doubletuned amplifier and the stagger-tuned amplifier are derived using which it is possible to infer as to the specific application of these amplifiers. The chapter also deals with the problem of instability in tuned amplifiers and throws light on possible methods that can help overcome this problem. Finally, a tuned Class C power amplifier and a wideband amplifier are considered too. Chapter 14 discusses the basic building blocks of an Op-amp like a differential amplifier and a dc level shifter. It also illustrates that a differential amplifier supplied with constant current will have a large common mode rejection ratio. It considers the need for a dc level shifter in an

xxviii

Preface

Op-amp and presents possible methods for dc level shifting. It presents the frequency-compensation methods that need to be employed in Op-amps and also illustrates experimental methods for measuring the Op-amp parameters. Chapter 15 considers the linear applications of Op-amps such as inverting and non-inverting amplifiers, summing and subtracting amplifiers, differentiator and integrator and current-to-voltage and voltage-to-current converters. This chapter also deals with some of the non-linear applications such as monostable and astable multivibratos, and logarithmic and antilog amplifiers. It also talks about precision rectifiers. Chapter 16 deals with active filters and presents the method of analysis and design of first- and second-order Butterworth LPF, HPF and BPF filters. It also presents wide and narrowband reject filters. Chapter 17 considers the need for voltage regulators to stabilize the output of a power supply and illustrates the principle of working of series and shunt regulators. It then talks about a complete feedback regulator. It subsequently discusses linear IC regulators and later presents switching regulators that achieve better efficiency. Finally, it introduces voltage multipliers. Chapter 18 deals with analysis and design of bistable, monostable and astable multivibrators and presents some simple applications of these regenerative circuits. It also discusses symmetric and unsymmetric methods of triggering a binary. Finally, it deals with an emitter coupled binary, which is also known as the Schmitt trigger and its varied applications. Chapter 19 considers an exponential voltage sweep generator and presents methods to linearize a nonlinear sweep using Miller and bootstrap sweep generators. It considers the principle of working of a current sweep and shows that an exponential current sweep can be linearized by adjusting the driving waveform. Chapter 20 presents the monolithic IC fabrication process. It talks about fabrication of resistors, capacitors and transistors on an IC and presents the packaging techniques. Finally, it introduces MOS technology for greater circuit density. Chapter 21 deals with the principle of operation of IC 555 timer as monostable, astable and bistable multivibrator circuits. This chapter introduces dual timer IC 556. Chapter 22 introduces the principle of working of some power electronic devices such as SCR, TRIAC, DIAC, etc., and optoelectronic devices such as photoconductors, LEDs, and laser diodes. Also, information is provided on the working of display devices such seven-segment LED displays, LCDs, and plasma display panels. The chapter also considers the working of various measuring instruments such as multi-meter, power meter, and energy meter. Finally, instruments for the measurement of frequency, time, distortion and spectral analysis are presented. Chapters 23 and 24 can be accessed through the QR codes given in the Table of Contents and the respective chapters. Chapter 23 deals with number systems and conversions from one radix to the other. The chapter also introduces rules for the minimization of Boolean expressions for the reduction of complex combinational circuits. Further, Karnaugh maps that help in the simplification of the Boolean function in a much effective manner have been considered. TTL and CMOS logic gates using discrete components have been presented and the performance parameters that define the suitability of a gate for a given application have been discussed. Finally, ADC and DAC circuits are considered. Chapter 24 deals with the structure of the microcomputers and microprocessors. The chapter also talks about the instruction set of 8085 processor and also tells the procedure to load the program into the processor. Simple programs are considered. Finally, the chapter introduces 8086.

Preface

xxix

Web Supplements Instructors can access the Solution Manual and PowerPoint Lecture Slides at http://highered.mheducation.com/sites/9332901155 Also, students can read chapters 23 and 24 by scanning the QR codes given in the Table of contents and the respective chapters.

Acknowledgements The authors wish to express their sincere thanks and gratitude to Dr G S N Raju, Vice Chancellor, Andhra University, who has been a source of inspiration and motivation through his academic  excellence and leadership qualities. The authors acknowledge their sincere gratitude to the Principal of the AU college of Engineering for Women, Dr Ch. Ratnam, for his inspiration and encouragement throughout the course of this project. The authors also express their heartfelt gratefulness to Dr K V V Satyanarayana Raju, Chairman, Sri. K Sasi Kiran Varma, Secretary, and Dr D L N Raju, CEO of Chaitanya Group of Institutions, for their cooperation and encouragement and also for providing the necessary facilities. The authors also wish to thank, Sri. K. Murali Krishnam Raju, Finance Director, Sri. S. S. Varma, CAO and Dr. M. Ramjee, Principal of Chaitanya Engineering College for their support. The authors wish to thank the following reviewers for their suggestions in improving the quality and the content of this book. Ratish Agarwal

University Institute of Technology, Rajiv Gandhi Technical University (RGTU), Bhopal, Madhya Pradesh

N R Kidwai

Gautam Buddh Technical University (GBTU), Uttar Pradesh Technical University (UPTU), Lucknow, Uttar Pradesh

Sanjit Kumar Dash

Krupajal Engineering College, Biju Patnaik University of Technology (BPUT), Bhubaneswar, Odisha

Barnali Dey

Sikkim Manipal University, Gangtok, Sikkim

Yogesh Dandawate

Vishwakarma Institute of Information Technology (VIIT), Pune, Maharashtra

Mrunal Mahesh Honap

Pune Vidhyarthi Griha’s College of Engineering and Technology, University of Pune, Pune, Maharashtra

S G Patil

Dr D Y Patil College of Engineering, Pune, Maharashtra

C V Raghu

National Institute of Technology (NIT) Calicut, Kozhikode, Kerala

Asha Elizabeth

Cochin University of Science and Technology (CUSAT), Cochin, Kerala

S Gomathi

KSR College of Technology, Tiruchengode, Tamil Nadu

Prakash Biswagar

RV College of Engineering, Visvesvaraya Technological University (VTU), Bangalore, Karnataka

Jammalamadugu Ravindranadh

RV. & JC College of Engineering, Acharya Nagarjuna University, Guntur, Andhra Pradesh

xxx

Preface

A Hazrathaiah

Narayana Engineering College, Nellore, Andhra Pradesh

P Rajesh Kumar

University College of Engineering, Vishakhapatnam, Andhra Pradesh

Special thanks to Dr M Murali, Sanketika Institute of Technology, and Mr M S Prakasa Rao, Sri Vasavi Engineering College, Tadepalligudem, for their suggestions and inputs. The authors also thank Dr A Chanrda Sekhar, GITAM, for his useful suggestions. Finally, the authors would fail in their duty if they do not profusely thank Ms A Amulya and Ms A Alekhya for their frank opinions and inputs, at every stage of this book. The authors felicitate Ms Vibha Mahajan, Ms Koyel Ghosh, Mr Suhaib Ali and the other members of the editorial team at McGraw Hill Education (India) for their wholehearted cooperation in bringing out a quality product.

Feedback Request Suggestions for the improvement of the content (factual or otherwise) and the script are welcome and the readers are requested to write to us at [email protected] and [email protected]. We appreciate your time and effort in improving the content presented in the book. K Venkata Rao K Rama Sudha

Publisher’s Note McGraw-Hill Education (India) invites suggestions and comments from you, all of which can be sent to [email protected] (kindly mention the title and author name in the subject line). Piracy-related issues may also be reported.

1

INTRODUCTION

Learning objectives After reading this chapter, the reader will be able to ˆ ˆ ˆ ˆ ˆ ˆ

1.1

Understand the method to identify and use R, C, and L as circuit components Understand the atomic structure of elements Classify elements as conductors, insulators, and semiconductors Appreciate the need for N- and P-type extrinsic semiconductors Understand the relevance of the laws that govern the behavior of semiconductor elements Understand the operation of an unbiased PN junction

INTRODUCTION

Resistors, capacitors, and inductors are the passive linear circuit components that are extensively used in electronic circuits. Although resistors are energy-dissipating elements, capacitors and inductors are energy-storing elements.

1.1.1 Resistors Resistors determine the flow of current in an electrical circuit. The higher the resistance in the circuit, the smaller is the current in it and vice versa. Resistance obeys Ohm’s Law. Resistance is measured in ohms (Ω). All modern fixed value resistors can be classified into four broad groups: 1. Carbon composition resistor: Carbon composition resistor is manufactured from a mixture of finely ground carbon dust or graphite and a non-conducting ceramic (clay) powder to bind it all together. These are usually low-wattage resistors. 2. Film resistors: Film resistors are of two types: (i) thin film resistors and (ii) thick film resistors. (i) Thin film resistors may consist of metal film, carbon film and metal oxide film resistor types. These resistors are made by depositing pure metals, such as nickel, or an oxide film, such as tin-oxide, onto an insulating ceramic rod or substrate made from conductive metal oxide paste. These are also low-wattage resistors. (ii) Thick film resistors are made by depositing a much thicker conductive paste of ceramic and metal, called cermet, onto an alumina ceramic substrate.

2

Electronic Devices and Circuits

3. Wire-wound resistor: Wire-wound resistor is made by winding a thin metal alloy wire such as nichrome onto an insulating ceramic former in the form of a spiral helix. These types of resistors are generally only available from few ohms to typically 100 kΩ. 4. Semiconductor resistor: Semiconductor resistor is derived from a doped semiconductor material. In fact, some of the active devices that will be discussed later will be replacing resistors in the manufacture of integrated circuits (ICs). To calculate the current and power dissipated in a resistor, consider the circuit in Figure 1.1. Using Ohm’s law

I

100 Ω R

V 10 I= = = 0.1 A R 100

V

10 V

and the power dissipated in R is P=

V2 = I 2 R = ( 0.1)2 × 100 = 1 W R

Figure 1.1 Calculation of I and P in R

Example 1.1 Calculate the maximum permissible current in a resistor of 1 kΩ and power dissipation capability of 1 W. Solution: I =

1 = 0.032 A 1000

P = R

When resistors are connected in series, the total resistance is the sum of the individual resistors. Consider Figure 1.2 where R = R1 + R2 + R3. The current I in the loop remains constant, whereas voltages across the individual resistors are different.

I

+ V1 −

+ V2 −

+ V3 −

200 Ω

300 Ω

500 Ω

R1

R2

R3

R

10 V V

Figure 1.2 Resistors connected in series

Example 1.2 For the circuit in Figure 1.2, for the indicated resistor values, calculate I, V1, V2, V3, P1, P2, and P3. Solution: R = R1 + R2 + R3 = 200 + 300 + 500 = 1000 Ω

Introduction

I=

3

V 10 = = 0.01 A R 1000

V1 = IR1 = 0.01 × 200 = 2 V

P1 = V1I = 2 × 0.01 = 0.02 W

V2 = IR2 = 0.01 × 300 = 3 V

P2 = V2I = 3 × 0.01 = 0.03 W

V3 = IR3 = 0.01 × 500 = 5 V

P3 = V3I = 5 × 0.01 = 0.05 W

Consider Figure 1.3. When resistors are connected in parallel, the effective resistance is calculated as follows: 1 1 1 1 or G = G1 + G2 + G3 = + + R R1 R2 R3

(1.1)

1 where G = 1 , G1 = 1 , G2 = 1 , and G3 = . The Gs are conductances. R3 R R1 R2 V across the resistors is the same, but the currents in the individual branches are different.

I V

I1 R1

10 V

I2

I3

R2

R3

300 Ω

500 Ω

R

200 Ω

Figure 1.3 Resistors in parallel

Example 1.3 For the circuit in Figure 1.3, for the indicated resistor values, calculate I, I1, I2, I3, P1, P2, and P3. Solution: I1 =

10 V = = 0.05 A R1 200

I2 =

10 V = = 0.033 A R2 300

I3 =

10 V = = 0.02 A R3 500

P1 = VI1 = 10 × 0.05 = 0.5 W

P2 = VI 2 = 10 × 0.033 = 0.33 W

P3 = VI 3 = 10 × 0.02 = 0.2 W

I = I1 + I2 + I3 = 0.05 + 0.033 + 0.02 = 0.103 A

Identification of Resistor Values Resistors are identified by their color code: 4, 5, or even 6 bands are represented on a resistor. In a 4-band coded resistor, the first two bands represent the digits, the third band represents the multiplying factor, and the fourth band represents

4

Electronic Devices and Circuits

Digit 1

Digit 2

Multiplier

Tolerance

Digit 1

Digit 2

Digit 3

Multiplier

Tolerance

Band 1

Band 2

Band 3

Band 4

Band 1

Band 2

Band 3

Band 4

Band 5

tolerance (Figure 1.4(a)). In a 5-band coded resistance, the first three bands represent the digits, the fourth band represents the multiplying factor, and the fifth band represents tolerance (Figure 1.4(b)). The colors of the bands and the corresponding digit values and tolerances are shown in Table 1.1.

(a) 4-band code

(b) 5-band code

Figure 1.4 4– and 5–band coded resistors

Table 1.1 Color codes and tolerances Color

Digit

Multiplier

Tolerance (%)

Black

0

100

Brown

1

101

1

Red

2

102

2

Orange

3

103

Yellow

4

104

Green

5

105

0.5

Blue

6

106

0.25

Violet

7

107

0.1

Gray

8

108

White

9

109

Gold

10−1

5

Silver

10−2

10

Blank

20

Brown, red, green, blue, and violet are used as tolerance codes on 5-band resistors only. The blank 20 percent band is used only with the 4-band code. For carbon composition and carbon film resistors, the common tolerances are 5 percent, 10 percent, and 20 percent.

Introduction

5

Example 1.4 For the color-coded resistors shown in Figure 1.5, find the resistor value and tolerance. Solution: The values and tolerances are shown in Figure 1.5. 7 102

4

10

6

8

0 102

5

Gold

(b)

(a)

9

Red

Black

Blue

68 kΩ ± 5%

Gray

Silver

Red

Violet

Yellow

4.7 kΩ ± 10%

7 100

3

3

0 101

0.1 3.3 kΩ ± 0.1%

5

Violet

Black

(d)

(c)

1

Brown

Orange

Orange

Black

White

Violet

97 Ω ± 20%

8 10− 2 2

3

3

0 10− 1

0.1

(e)

Violet

Gold

Black

Orange

33 Ω ± 0.1%

Orange

Red

Grey Silver

Green

Brown

1.58 Ω ± 2%

(f)

Figure 1.5 Color coded resistors

Specification of a Resistor A resistor is completely specified by its resistance value, power rating, tolerance, and temperature coefficient. Temperature coefficient is indicated as ppm/°C, where ppm stands for parts per million. For example, if temperature coefficient = 100 ppm/°C, then it means that the value of the 1 MΩ resistance can change by not more than 100 Ω for a temperature change of 1°C or 0.1 Ω for every 1 kΩ. It is important to note that the same resistance is offered for both dc and ac currents. A variable resistance is called a potentiometer.

1.1.2 Capacitors Capacitor is also called a condenser and is a linear passive circuit element, which has the capacity to store energy in the form of an electrical charge and produces a potential difference across its terminals. A capacitor basically consists of two parallel metal plates that are electrically separated by a distance d in meters with dielectric material between the plates. The most common types of

6

Electronic Devices and Circuits

dielectric materials used are air, paper, polyester, polypropylene, Mylar, ceramic, glass, oil, or a variety of other materials. A parallel plate condenser is shown in Figure 1.6(a) and its schematic representation in Figure 1.6(b). C=

eA e 0e r A kA Farads = = d d d

(1.2)

where k = ε0 εr ε0 = permittivity of free space = 8.854 × 10−12 F/m k = relative permittivity of the dielectric material between the plates The capacitance C is 1 F when a charge of 1 Coulomb is stored on the plates by a voltage of 1 V (Coulomb/V). εr for common materials is: pure vacuum = 1.0, air = 1.0005, paper = 2.5–3.5, glass = 3–10, mica = 5–7, wood = 3–8, and metal oxide powders = 6–20, etc. On the application of voltage V, positive charges are stored on the top plate and negative charges on the bottom plate. C is given as C=

Q or V = CQ V

(1.3)

where Q is the charge in Coulombs, C is the capacitance in Farads, and V is the applied voltage in Volts. Metal plate +

+

d

+ + + + + A in m 2

+Q + + + + + + + + +

Dielectric e

− − − − − − −− −Q − − − − − − − − − − −

I

V

− C

Metal plate (a)

(b)

Figure 1.6 (a) Parallel plate capacitor and (b) schematic representation

Example 1.5 In a parallel plate condenser, the plates are separated by a distance of 0.1 cm and the area of the plates is 100 cm2. Express C in pF, if the dielectric medium is air. Solution: ε = ε0εr = 8.854 × 10−12 × 1.0005 = 8.854 pF/m A = 100 cm2 = 0.01 m2 d = 0.1 cm = 0.001 m C =

εA 8.854 × 10 −12 × 0.01 m 2 = = 88.54 pF d 0.001 m

7

Introduction

The current in a capacitor is directly related to the charge on the plates. As current is the rate of flow of charge with respect to time and Q is proportional to the applied voltage V, then I =C

dV dt

I

(1.4)

+ +

The energy stored in a capacitor is the integral of the instantaneous power. Assuming that the capacitor had no charge across its plates at t = −∞, then the energy stored in the capacitor at time t is

C V V −

−

Figure 1.7 Circuit of Example 1.6

dv 1 E = ∫ Pdt = ∫ VI dt = ∫ VC dt = CV 2 J ( Joules) −∞ −∞ −∞ dt 2 t

t

t

(1.5) 10 K

Example 1.6 A 47-μF capacitor is connected to a voltage that varies in time as v = 20 sin(200πt) volts (Figure 1.7). Calculate the current i through the capacitor.

20 K

1 µF

15 V

C

Solution: i =C

dv d = 47 × 10 −6 [ 20 sin( 200pt )] Figure 1.8 Circuit of Example 1.7 dt dt = 47 × 10−6 × 20 × 200π cos(200πt) = 0.59 cos(200πt) A

Example 1.7 Calculate the energy stored in C shown in Figure 1.8. Solution: Under dc condition, C is an open circuit and the circuit in Figure 1.8 reduces to that shown in Figure 1.9. The voltage across C is

V = 15 ×

10 K

20 K

V

15 V

Figure 1.9 Circuit of Figure 1.8 under dc condition

20 = 10 V 10 + 20

1 1 The energy stored in C = CV 2 = × 1 × 10 −6 × 102 = 50 µJ 2 2

I + V

C1

I1

C2

I2

−

Capacitors in Parallel When capacitors C1 and C2 are

Figure 1.10 Capacitors in parallel

connected in parallel (Figure 1.10), then the effective capacitance Ceq is calculated as follows: I = I1 + I 2 = C1 ∴ Ceq = C1 + C2

dV dV dV dV + C2 = (C1 + C2 ) = Ceq dt dt dt dt (1.6)

8

Electronic Devices and Circuits

Capacitors in Series When capacitors C1 and C2 are connected in series (Figure 1.11), then the effective capacitance Ceq is calculated as follows:  1 d (V1 + V2 ) dV1 dV2 dV I I 1 = = + = + = I +  dt dt dt dt C1 C2  C1 C2  I=

dV 1 1 dV = Ceq dt  1 1  dt  C + C  1 2

1 1 1 = + Ceq C1 C2

I + V −

+ V1 − + V2 −

C1

C2

Figure 1.11 Capacitors in series

(1.7)

Types of Capacitors Different types of capacitors are available in the market. A few types are listed below: (i) Dielectric capacitors: Dielectric capacitors are multi-plate, air-spaced, variable type condensers. These condensers have a set of fixed plates and a set of movable plates that move in between the fixed plates. These are used as tuning condensers in transmitters and receivers. (ii) Film capacitors: Film capacitors use polystyrene, polycarbonate, or Teflon as their dielectrics and are also called plastic capacitors. The dielectric is a plastic film and these capacitors operate well at high temperatures and have smaller tolerances. (iii) Ceramic capacitors: Ceramic capacitors or disc capacitors are made by coating two sides of a small porcelain or ceramic disc with silver and are then stacked together to make a capacitor. Very low capacitance values in a single ceramic disc of about 3–6 mm are available. (iv) Electrolytic capacitors: An electrolytic capacitor uses a semi-liquid electrolyte solution in the form of a jelly or paste as one of its plates to achieve a larger capacitance per unit volume. The dielectric is a very thin layer of oxide with thickness typically of the order of 10 µ (microns). As the insulating layer is thin, capacitors with a large value of capacitance with small physical size are possible, as d, the spacing between the plates, is very small. Electrolytic capacitors are polarized capacitors. Consequently, while connecting to a dc voltage the positive end of the voltage source should be connected to the positive terminal of C and negative end to the negative terminal of C. Improper polarization will breakdown the insulating oxide layer and can damage the capacitor.

Characteristics of Capacitors The following are some of the characteristics that are usually listed in the data sheets and are helpful in proper use of capacitors: (i) The nominal value of the capacitance C of a capacitor is marked on the body of the capacitor as numbers, letters, or colored bands. (ii) The working voltage: The maximum dc or ac voltage that can be applied for a relatively long duration to the capacitor so as to ensure that no damage is done to the condenser is called the working voltage (WV). Voltages larger than the rated voltage can cause the breakdown of the dielectric. The breakdown of the dielectric causes short circuit, which may

Introduction

V C

I

−

RP IL

Tolerance D

Digit B

Figure 1.12 Leakage current

Multiplier C

(v) Temperature coefficient: Temperature coefficient of a capacitor is the maximum change in its capacitance over a specified range of temperature and is expressed as parts per million per degree centigrade (PPM/°C).

+

Digit A

eventually lead to heating of the capacitor. It is possible that the capacitor may even explode. (iii) Tolerance: Tolerance is the range over which the value of C is allowed to vary from its nominal value and is expressed as ±10 percent or so. Thus, the value of a 100 µF capacitor with ±20 percent tolerance could lie anywhere between 80 µF and 120 µF. (iv) Leakage current: The dielectric is not a perfect insulator and as such may offer a relatively large insulation resistance, Rp, through which small current of the order of nA can flow and this current is called the leakage current, IL. This leakage current will discharge C if the supply voltage is removed (Figure 1.12).

9

Figure 1.13 Bands with color code

Capacitor Color Codes Capacitor color codes are shown in Table 1.2 and the bands in Figure 1.13. However, few more parameters such as temperature coefficient and WV are also depicted. Table 1.2 Color codes and tolerances of capacitors Color

Digits A, B

Black

0

100

20

Brown

1

101

1

Red

2

102

2

Orange

3

10

3

3

Yellow

4

104

4

Green

5

105

5

Blue

6

106

6

Violet

7

107

7

Gray

8

108

8

White

9

109

9

Gold

10−1

5

Silver

10−2

10

Blank

Multiplier C

Tolerance, %D

20

10

Electronic Devices and Circuits

When connected to a dc source C gets charged to the source voltage with the time constant t = RC (Figure 1.14). The voltage variation in the capacitor is given as −t   vC = V 1 − e t   

(1.8)

iC iC

vC

R

vC

+ V

C −

iC

vC 0

t

(b) Variation of iC and vC

(a) Charging of C

Figure 1.14 Capacitor connected to a dc source

At t = 0, vC = 0 and at t = ∞, vC = V The current variation in the capacitor is given as −t

iC = At t = 0, iC =

V t e R

(1.9)

V and at t = ∞, iC = 0 R

Therefore, when there is a sudden change in voltage the capacitor behaves as a short circuit and when fully charged it behaves as an open circuit for dc. However, under ac conditions the capacitor offers a reactance, XC, given as XC =

1 1 = w C 2p fC

(1.10) I

where w = 2p f is the radial frequency of the applied signal (Figure 1.15); f is in Hertz and C is in Farads.

+ C V

I =

V = V ´ 2p fC XC

(1.11)

−

Figure 1.15 Sinusoidal signal applied to C

where V and I are the rms components of voltage and current. Example 1.8 For the circuit in Figure 1.15, V = 200 V, C = 1 µF, and f = 50 Hz. Calculate I. Solution: X C =

1 1 = = 3.185 kΩ 2 πfC 2 π × 50 × 1 × 10 −6

11

Introduction

I =

V 200 = = 62.79 mA XC 3.185

IL + L

VL

1.1.3 Inductors

r l

−

Inductor is a coil of wire often wound around a steel or ferrite core (Figure 1.16). The magnetic flux within the coil is

Figure 1.16 Voltage applied to an inductor

f=

mNA I l

(1.12)

where N is the number of turns in wire coil, A = πr2, is the cross-sectional area of the coil, l is the length of the coil, and µ = µ0µr is the permeability of the core material. For free space (or air): μ0 = 1.26 μH/m and µr is relative permeability and is a dimensionless quantity. 2 From Faraday’s law, V = N d f = mN A di = L di dt l dt dt

and the inductance L =

mN 2 A l

(1.13)

(1.14)

I + +

From Figure 1.16, i = IL and from Eqn. (1.13) L=

V2 −

Vdt Volt second = Henry. = Ampere dI L

V

L is measured in henries.

+ V1

The energy stored in an inductor is E =

1 2 LI L joules 2

L2

−

(1.15)

L1

−

Figure 1.17 Inductors connected in series

Inductors in Series When two inductors are connected in series (Figure 1.17), the effective inductance is calculated as follows: V = V1 +V2 = L1 ∴ L = L1 + L2

dI dI dI dI + L2 = ( L1 + L2 ) = Leq dt dt dt dt (1.16)

If a number of inductors is connected in series, then the effective inductance is the sum of the individual inductances.

12

Electronic Devices and Circuits

Inductors in Parallel When two inductors are

I

connected in parallel (Figure 1.18), the effective inductance is calculated as follows:

+

I1

I2

L1

L2

V

 1 dI d ( I1 + I 2 ) dI1 dI 2 V V 1 = = + = + =V  +  dt dt dt dt L1 L2  L1 L2 

−

V=

∴ Leq =

dI 1 dI =  1 1  dt Leq dt  L + L  1 2 1

Figure 1.18 Inductors connected in parallel

1 1 + L1 L2

(1.17)

An inductor has an associated resistance (in which case it is called a choke) and hence a practical inductor is represented as shown in Figure 1.19. + I

RL

≡

V L

Choke

−

Figure 1.19 Practical inductor

The two pertinent characteristics of an inductor are (i) dc resistance and (ii) the maximum dc current. (i) dc resistance: Inductors have very low resistance for dc signals, usually of the order of a few ohms. (ii) The maximum dc current of an inductor is the maximum level of continuous direct current that can be passed through an inductor with no damage. For a dc voltage as input, the inductor offers only the dc resistance. However, for an ac input voltage an inductor offers a reactance, XL = wL = 2pfL.

1.2 THE NATURE OF ATOM An atom is the smallest particle that retains the properties of an element. Atoms comprise three types of particles: protons that have positive charge; neutrons that have no charge; and electrons that have negative charge. Protons and neutrons reside in the nucleus. The mass of an electron is very small and is 9.108 × 10−31 kg. The mass of a proton and neutron is 1,800 times larger than that of an electron. Therefore, protons and neutrons are responsible for most of the atomic mass. The charge of an electron is expressed in Coulombs and is equal to 1.602 × 10−19 C. The number of protons (electrons) in an atom is specified by the atomic number, Z.

Introduction

13

Electrons circle the nucleus at different elliptical orbits called shells. A definite energy level is associated with each shell. A shell can accommodate only a fixed number of electrons, namely, 2n2 electrons. The occupancy of each shell is indicated in Table 1.3. Table 1.3 Shells and the number of orbital electrons Number of orbital electrons = 2n2

n

Shell called as

1

K

2 × 12 = 2

2

L

2 × 22 = 8

3

M

2 × 32 = 18

4

N

2 × 42 = 32

A Li atom has one valence electron in the L shell and a Si atom has four valence electrons in the M shell (Figure 1.20).

M L

L +3

K

+14 K

Lithium Silicon

Figure 1.20 Electrons in orbits for Li and Si atoms

Only if the inner shells are completely filled the electrons in an atom usually occupy outer shells. The  farther is the electron away from the nucleus the greater is the energy associated with it. The  electrons located in the innermost shells are tightly bound to the nucleus and those in the outermost shell are loosely bound and are called valence electrons. The electrical and chemical properties of semiconductor materials are essentially decided by these valance electrons. When an electron moves from a lower energy level to a higher energy level, energy is absorbed by the atom. When an electron moves from a higher to a lower energy level, energy is released, often as light.

1.2.1 Energy Levels The energy associated with each orbit can be calculated. Consider the hydrogen atom in which an electron moves in circular motion with a velocity v and the radius of the orbit is rn (Figure 1.21). For the electron to remain in orbit, the outward centrifugal force must be equal to electrostatic force of attraction between the electron and the nucleus. e2 Electrostatic force of attraction = (1.18) 4pe 0 rn2

14

Electronic Devices and Circuits

2 Outward centrifugal force = mv rn From Eqs (1.18) and (1.19) 2

e mv = 4pe 0 rn2 rn

2

V

mv 2/rn

(1.19)

e 2/4π e 0rn 2 rn

(1.20) +

2

Or

mv 2 =

e 4pe 0 rn

(1.21)

The kinetic energy of the electron 1 2 e2 mv = 2 8pe 0 rn

Figure 1.21 Motion of electron in hydrogen atom

(1.22)

Bohr has stipulated that only those orbits are possible for which the angular momentum of the electron is equal to an integral multiple of h (quantization of angular momentum), where h is 2p the Plank’s constant in Joule-seconds. nh ∴ Angular momentum = mvrn = (1.23) 2p v= ∴

mv 2 =

nh nh and mv = 2pmrn 2prn

nh nh n2 h2 × = 2prn 2pmrn 4p 2 mrn2

(1.24)

From Eqs (1.21) and (1.24) e2 n2 h2 = 4p ∈0 rn 4p 2 mrn2 Or

rn =

e 0 n2 h2 pme 2

(1.25)

Mass of an electron, m = 9.107 × 10 −31 kg Charge of an electron, e = 1.602 × 10−19 C Plank’s constant, h = 6.626 × 10−34 J-s Permittivity of free space, ε0 = 8.854 × 10−12 F/m ∴ rn =

e 0 n2 h2 8.854 × 10 −12 × (6.626 × 10 −34 )2 n2 = 0.529 × 10 −10 × n2 m = pme 2 p × 9.107 × 10 −31 × (1 1.602 × 10 −19 )2

For the first shell (K shell), n = 1, therefore, r1 = 0.529 × 10−10 × 12 m 1 Å = 10−10 m rn = n2 × 0.529 Å

(1.26)

15

Introduction

The potential energy of an electron at a distance rn from the nucleus =

−e 2 4p ∈0 rn

(1.27)

Using Eqn (1.22) and (1.27) the energy associated with an orbit or shell is 1 e2 e2 e2 −e 2 Wn = mv 2 − = − = 2 4p ∈0 rn 8p ∈0 rn 4p ∈0 rn 8p ∈0 rn

(1.28)

Substituting the value of rn from Eqn. (1.25) in Eqn. (1.28) Wn =

pme 2 −e 2 −e 2 − me 4 = × = 8p ∈0 rn 8p ∈0 e 0 n2 h2 8 ∈0 2 n2 h2

(1.29)

Equation 1.29 gives the energy of the nth shell. The energy associated with each shell can be obtained by substituting different values of n, n = 1, 2, 3. − me 4 −9.107 × 10 −31 × (1.602 × 10 −19 )4 = − 21.78 × 10 −19 = −12 2 −34 2 2 2 8 ∈0 h 8 × (8.854 × 10 ) × (6.6626 × 10 )

∴ Wn =

−21.78 × 10 −19 J n2

The energy acquired by an electron in rising to a potential of 1 V is defined as 1 eV and 1 eV = 1.602 × 10−19 J Or

∴ Wn =

−21.78 × 10 −19 13.61 = − 2 eV n 1.6 × 10 −19 n2

(1.30)

For n = 1, W1 = −13.61 eV and for n = ∞, W∞ = 0 eV Table 1.4 shows rn and Wn for n = 1, 2, 3, 4. Table 1.4 rn and Wn for n = 1, 2, 3, 4 n rn = n2 × 0.529 Å

Wn = −

13.61 eV n2

1(K shell)

2(L shell)

3(M shell)

4(N shell)

r1 = 0.529 Å

r2 = 2.116 Å

r3 = 4.761 Å

r4 = 8.464 Å

W1 = −13.61 eV

W2 = −3.40 eV

W3 = −1.512 eV

W4 = −0.850 eV

The energy level diagram is shown in Figure 1.22. When a transition occurs from one stationary orbit, say from a state with associated energy W2 to a state with associated energy W1, then energy is radiated with a frequency f given by

16

Electronic Devices and Circuits n=∞ n=7 n=6

E∞ = 0 E7 E6 = −0.38 eV

n=5

E5 = −0.54 eV

n=4

E4 = −0.854 eV

n=3

E3 = −1.512 eV

10 11 12 13 Paschen lines (IR)

n=2

E2 = −3.40 eV

6789 Balmer lines (Visible)

Forbidden region

n=1

1 2 345

Ground state

E1 = −13.61 eV

Lyman lines (UV)

Figure 1.22 Energy level diagram

f =

W2 − W1 h

(1.31)

where h is the Planck’s constant and f is in Hz. For the first orbit n = 1 and W1 = −13.61 eV. This is called the ground state. If a photon is at higher energy levels it is said to be in an excited state. When a photon drops from an excited state to the second orbit, Balmer lines are observed and these transitions are in the visible region. All transitions that drop to the ground state emit photons in the Lyman lines and these transitions are in the UV region. All transitions that drop to the third orbital are known as the Paschen lines and are near IR region. It may be noted that to remove an electron from an outer orbit less energy is imparted to it. Similarly, to remove an electron from the inner orbits a relatively large amount of energy is required to be expended.

1.3

ELECTRONIC STRUCTURE OF THE ELEMENTS

The principal quantum number n refers to the shell or energy level to which the electron belongs. The shells K, L, M, N,… consist of inner subshells that further consist of orbitals. Each orbital 1 1 will have two electrons with opposite spins, that is, + (clockwise) and − (anticlockwise). 2 2 The sub-shell(s) present in n = 1 → s. The sub-shell s consists of one orbital, that is, two electrons. n = 2 → s, p. The sub-shell p consists of three orbitals, that is, six electrons. n = 3 → s, p, d. The sub-shell d consists of five orbitals, that is, 10 electrons n = 4 → s, p, d, f. The sub-shell f consists of seven orbitals, that is, 14 electrons, and so on.

Introduction

17

1s2 2s2 2p6 3s2

1s 2

3p6 4s2 2s

2p

2 3s

Increasing energy

3d10 4p6 5s2

6 3p

2

6 4s

10

10

6 5s

5p

2 6s

5f 14

6d

6p 10 7p

5f14 6d10 7p6 8s2

14

10

6 7s

4d

5d

6

2

4f14 5d10 6p6 7s2 4d

4p

2

4d10 5p6 6s2

3d

6f 14

7d

7f

Figure 1.23 Order of sub-shell filling

The filling of the electrons takes place in the increasing order of the energies of the orbitals (Aufban principle) (Figure 1.23). The order of filling of electrons is as follows: 1s 2s 2p 3s 3p 4s 3d 4p 5s 4d 5p 6s 4f 5d 6p 7s 5f 6d 7p Or, the number of electrons in the orbitals is as follows: 1s2 2s2 2p6 3s2 3p6 4s2 3d10 4p6 5s2 4d10 5p6 6s2 4f14 5d10 6p6 7s2 5f14 6d10 7p6 Based on the above discussion, it is possible to write down the electron configurations in some of the fourth group elements as shown in Table 1.5. Table 1.5 Electron configuration of some fourth group elements Element

Atomic number

Electron configuration

C

6

1s 2s 2p

Si

14

1s2 2s2 2p6 3s2 3p2

Ge

32

1s2 2s2 2p6 3s2 3p6 4s2 3d10 4p2

Sn

50

1s2 2s2 2p6 3s2 3p6 4s2 3d10 4p6 5s2 4d10 5p2

Pb

82

1s2 2s2 2p6 3s2 3p6 4s2 3d10 4p6 5s2 4d10 5p6 6s2 4f14 5d10 6p2

2

2

2

1.3.1 Energy Band Theory of Crystals Metals, depending on the chemical composition, have closely packed atoms or ions and exhibit a crystal lattice structure with a periodic array of the atoms. Metals, diamond, and graphite are some examples of crystalline solids. The smallest structure is the unit cell that repeats itself through

18

Electronic Devices and Circuits

Energy of electrons

eV

the crystal. The  body-centered cubic and the hexagonal close-packed unit cells are shown in Figure 1.24. The behavior of the electron orbits of an atom in a closely packed crystal lattice is described by the Energy band theory of crystals. When atoms are closely packed the electrons in the outer orbits belong not only to the parent atom but also to the neigh(a) Cubic body-centered (b) Hexagonal boring atoms, in which case is said that covaFigure 1.24 Unit crystal lattice examples lent bonds are formed. Formation of these covalent bonds may appear as though the electrons belong to the entire crystal. The  result is that the discrete energy levels cease to exist, instead energy bands are formed. The uppermost band that contains electrons is called the valence band and the lowermost band that is empty is called Conduction band the conduction band. The energy band gap that exists between these two bands is called the forbidden gap (Figure 1.25). If Forbidden gap an electron in the valence band acquires sufficient energy, it breaks free from the covalent bond and jumps into the conducValence band tion band. On the application of an external electric field, these electrons in the conduction band account for the electric current. The conductivity of the material depends on the energy Figure 1.25 Energy bands in crystal gap between the valence band and the conduction bands.

1.3.2 Insulators, Conductors, and Semiconductors Depending on the material, the forbidden gap can be large, small, and can even be nonexistent. It is the width of the forbidden energy gap that defines the distinction between insulators, semiconductors, and conductors. The forbidden energy gap is large for the insulators, typically of the order 5 eV or more (Figure 1.26(a)). For the semiconductors this energy gap is typically of the order 1 eV (Figure 1.26(b)). For the conductors the forbidden gap does not exist and the conduction and valence bands overlap (Figure 1.26(c)). By now it is known that materials are grouped into three categories depending on their ability to conduct electricity: (i) Conductors: Silver, copper, aluminum, etc., contain free electrons that are responsible for conduction and are called conductors. The larger the number of free electrons, the greater is the current. Conductors offer a very low resistance, typically less than 10−8 Ωm. (ii) Insulators: Materials such as glass, ceramic, quartz, bakelite, rubber, etc., have their valence electrons very tightly bound to the nucleus. As such a very large energy is required to remove the electron from the attracting force of the nucleus. Such materials are called insulators. Insulators have high resistivity, typically greater than 1010Ωm. They are poor conductors of electricity. (iii) Semiconductors: Materials whose conductivity lies between that of conductors and insulators are called semiconductors. Germanium and silicon have resistivity of the order of 102 Ωm. Some important semiconductors are silicon (Si), germanium (Ge), and galliumarsenide (GaAs). The resistivity chart is shown in Table 1.6.

Valence band

(a) Insulator

Conduction band Forbidden gap = 1 eV Valence band

Energy of electrons

eV Forbidden gap = 5 eV

Energy of electrons

eV Energy of electrons

Conduction band

19

eV

Introduction

(b) Semiconductor

Conduction band Overlap of valence and conduction bands Valence band

(c) Conductor

Figure 1.26 Insulators, semiconductors, and conductors

Table 1.6 Resistivity chart Material Conductors

Semiconductors

Resistivity Ω − m

Silver

1.6 × 10−8

Gold

2.4 × 10−8

Carbon

3.5 × 10−5

Germanium

4.6 × 10−1

Silicon

6.4 × 102

Glass

1.0 × 1010

Quartz

7.5 × 1018

Insulator

1.4

SEMICONDUCTORS

Semiconductors are classified as (i) intrinsic or pure semiconductors and (ii) extrinsic or impure semiconductors.

1.4.1 Intrinsic or Pure Semiconductors Figure 1.27 shows how atoms of Ge or Si combine to form one crystal. Covalent bonds are formed by the sharing of the valence electrons by the neighboring atoms. At absolute zero temperature 0 K (−273.15°C), as no energy is imparted, all the electrons in the outer orbits remain in the valence bands. Consequently, the semiconductor behaves as an insulator. However, at room temperature, some of the electrons in the outer orbits may acquire sufficient energy to jump to the conduction band and can be available as free electrons. The energy required to break the covalent bonds in Ge is 0.72 eV and that in Si is 1.12 eV. Si and Ge have the same crystal structure and identical characteristics and they are the most widely used semiconductor materials. When energy is imparted to an atom, an electron (−ve charge) is removed from the valence band of an atom, in which case a hole is said to be created. In pure Si or Ge, there will be as many holes as there are electrons and these combinations are called electron–hole pairs. Electrons and

20

Electronic Devices and Circuits Ge

Ge

+4

+4

Ge +4

Valence electrons Ge Ge

Ge +4

+4

+4

Covalent bond

+4

+4

+4

Ge

Ge Ge

Figure 1.27 Two-dimensional representation of Ge crystal

holes are present in equal numbers and this concentration is called intrinsic concentration and is indicated as n = p = ni (1.32) where n is the number of free electrons per unit volume p is the number of free holes per unit volume ni is the intrinsic concentration When an atom loses an electron, it is said to be ionized (Figure 1.28).

Ge

Ge

+4

+4

Ge +4

Valence electrons Ge Ge

Ge +4

Broken covalent bond

+4

+4

Hole

Covalent bond

+4

+4

+4

Ge

Ge Ge Free electron

Figure 1.28 Ge crystal at room temperature

Introduction

21

1.4.2 Conduction in Intrinsic Semiconductors An intrinsic semiconductor at room temperature has a fewer number of electrons in the conduction band and an identical number of holes in the valence band. On the application of an external electric field, free electrons move toward the positive terminal of the battery and the holes toward the negative terminal, thereby constituting an electric current. However, it is to be noted here that in a conductor the current is due to electrons, whereas in a semiconductor the current is essentially due to two types of charge carriers–electrons and holes (Figure 1.29). Electron flow

Hole flow

External emf

Figure 1.29 Current flow in an intrinsic semiconductor

1.4.3 Fermi Level in an Intrinsic Semiconductor Fermi energy level is defined as the highest occupied energy level found in that material at absolute zero temperature (0 K or −273.15°C). It is a reference energy level. The energy band diagram of an intrinsic semiconductor is shown in Figure 1.30. The top of energy level of the valence band is designated as EV and the bottom of the energy level of conduction band is designated as EC. The EF is the energy of Fermi level. E Conduction band EC EF

EG

EV Valence band

Figure 1.30 Energy band diagram of an intrinsic semiconductor

Let the energy density of states be N(E) which gives the number of states between E and E + dE. NC(E) represents the energy density of electrons in the conduction band and N V ( E ) represents the

22

Electronic Devices and Circuits

energy density of holes in the valence band. For energies that are close to the extremes of these two bands, the density of states has a quadratic dependence with E: 3

1  2m  2 NC ( E ) = 2  2 c  2p  h 

( E − EC )

(1.33)

(EV − E )

(1.34)

3

1  2m  2 NV (E ) = 2  2v  2p  h 

h is the normalized Planck’s constant (h = 6.626 × 10−34 Js) and mc and mv are the 2p average effective masses of the conduction and the valence bands. For a direct gap semiconductor, where h =

mc and mv are the effective masses of an electron and the hole in the crystal. The probability for an electron to occupy a level with a given energy E is given by the Fermi– Dirac distribution function: 1

f ( E ) = fE =

(E − E )

(1.35)

F

1+ e

kT

where k = 1.38 × 10−23 JK−1 is the Boltzmann constant, T the temperature, and EF the Fermi energy. The probability for a hole to occupy a level of energy E is given by (1 − f(E)) because a hole is by definition the absence of an electron. The electron density n [cm−3] in the conduction band is obtained by integrating, over the range of energies accessible by electrons in the band, the number of states that may be occupied by electrons of energy E, weighted by the probability to find an electron having this given energy: n=∫

+∞ EC

N C ( E ) . f ( E ) dE

(1.36)

Similarly, the hole density p [cm−3] in the valence band is written as follows: p =∫

Ev −∞

N V ( E ) .[1 − f ( E )]dE

(1.37)

For a semiconductor whose Fermi level EF is located more than 3 kT away from the extremes, the Fermi distribution function can be written under the form of a simple exponential, so that the expressions for the charge carriers densities become: − (EC − EF )

n = NC e where N C = ∫

+∞ E

(E

and p = N V e

NC (E ). e

kT

(1.38)

− (E − EC ) kT

dE

C

V

− EF )

kT

(1.39)

Introduction

where N V = ∫

EV −∞

N V (E ) e

(

− E − Ev kT

23

)

dE

NC and NV are called the effective densities of states and are given as 3

 2pme kT  2 NC = 2   h2 

(1.40)

where me is the effective mass of the electron. 3

 2pm p kT  2 NV = 2   h2 

(1.41)

where mp is the effective mass of the hole. From Eqs (1.38) and (1.39), the product of the two densities is given as np = ni2 − (EC − EF )

ni 2 = N C e

kT

ni 2 = N C N V e ni =

− (E V − EF )

NVe

kT

= NC N V e

− EC + EF + E V − EF kT

− ( EC − E V ) kT

NC N V e

(1.42)

− ( EC − E V ) 2 kT

− EG

= N C N V e 2 kT

where ni is the density of intrinsic carriers (for Si at 300 K, ni = 1010 cm−3). ni is seen to be independent of the position of the Fermi level.

1.4.4 Calculation of the Intrinsic Fermi Energy For an intrinsic semiconductor the electron hole densities are equal. n = p = ni Using Eqs (1.38) and (1.39), − (EC − EF )

n = NC e − (EC − EF )

NC e

kT

(E

= NVe

V

− EF )

kT

− (E V − EF )

kT

kT

p = NVe −E NV =e NC

C

+ EF − E V + EF kT

2 EF − (EC + E V )

=e

kT

Taking logarithms,  (E + EV )  2  EF − C  2  = ln N V  kT NC

EF −

( EC + E V ) = 2

kT N V ln 2 NC

24

Electronic Devices and Circuits

EF =

( EC + E V ) + 2

kT N V ln 2 NC

(1.43)

where EF is the Fermi level of the intrinsic semiconductor and is designated as EFi. At room temperature kT is very much lower than the energy gap. EFi ≅

( EC + E V ) 2

(1.44)

The Fermi level of an intrinsic semiconductor lies in the middle of the forbidden gap.

1.4.5 Mass Action Law From Eqn (1.42), under thermal equilibrium, the product of the electron and hole density in an extrinsic semiconductor is always equal to the square of the intrinsic carrier density. ni2 = N C N V e

− ( EC − E V ) kT

= np

(1.45)

This property is referred to as the mass action law. In an intrinsic semiconductor n = p = ni, the number of holes is the same as the number of electrons. If, however, a fifth group impurity is added then the extrinsic semiconductor is an N-type semiconductor in which the electron concentration increases very much but the hole concentration decreases. Alternately, if a third group impurity is added, then the extrinsic semiconductor is a P-type semiconductor in which the hole concentration increases very much but the electron concentration decreases. Under thermal equilibrium np = ni2, is constant and is independent of the amount of doping. Thus, the mass action law is a powerful relation that enables to quickly find the hole density if the electron density is known or vice versa.

1.4.6 Extrinsic Semiconductors In an intrinsic semiconductor at room temperature the electron–hole pairs generated account for a small electron current and practically zero hole current on account of recombination. However, for a semiconductor to be useful its conduction properties should be increased. The electrical conductivity of the intrinsic semiconductor can be increased by adding impurities (one atom per million atoms). Then the semiconductor is called an extrinsic or impure semiconductor. Adding impurity atoms to a pure semiconductor is called doping. Extrinsic semiconductors are of two types: (i) N-type and (ii) P-type.

N-Type Semiconductors When a small number of fifth group impurities such as bismuth, antimony, arsenic, and phosphorus is added to a pure semiconductor during crystal growth, the resulting semiconductor is called an N-type semiconductor. The fifth group atoms have five valence electrons and pure Ge or Si atoms have only four valence electrons. The four valence electrons of either Ge or Si form covalent bonds with four valence electrons of the impurity atom and the fifth valence electron of the impurity atom is not covalently bonded. It is loosely bound to the parent impurity atom (Figure 1.31). By imparting a very small amount of energy it is possible to detach the electron from the binding force of the parent atom. The amount of energy that is needed to remove the electron from the valence band is typically 0.01 eV for Ge and 0.05 eV for Si. As the impurity atom donates its excess electron it is called the donor atom.

Introduction Ge

Ge

+4

+4

25

Ge +4

Valence electrons As

Conduction band

+4

+5

Energy

Ge

Ge +4

Free electrons Valence band

Covalent bond

Holes +4

+4

+4

Ge

Ge Ge Free electron

Figure 1.31 (a) Covalent bonds with fifth group impurity (b) energy bands in N-type semiconductor

When donor atom loses an electron, it becomes an immobile positive ion. An N-type semiconductor has a fairly large number of electrons and a smaller number of holes. Hence, electrons are called majority carriers and holes are called minority carriers. Conduction in this type of material is essentially through electrons. When an electric field is applied electrons move toward the positive terminal of the battery, constituting an electric current (Figure 1.32). Immobile positive donor ions Electron flow +

+

+

+

+

+

+

+

Hole flow

External emf

Figure 1.32 Conduction in N-type semiconductor

An N-type semiconductor has a higher electron density n and a lower hole density p than the same intrinsic semiconductor. Let ND be the donor density. Then n = ND. From the mass action law p=

ni 2 ND

(1.46)

26

Electronic Devices and Circuits

(

n = NC e

− E −E F C kT

)

(

ND = NC e

− E −E F C kT

)

(

e

− E −E F C kT

) =

NC ND

( EC − EF ) N = ln C kT ND EF = EC − kT ln

NC ND

The Fermi level of the N-type semiconductor is EFn = EC − kT ln

NC ND

(1.47)

When the donor density is increased, the Fermi level moves closer to the edge of the conduction band. If ND = NC, the Fermi level enters the conduction band: the semiconductor is then said to be degenerate.

P-Type Semiconductor When a small number of third group impurities such as gallium, indium, aluminum and boron is added to a pure semiconductor during crystal growth, the resulting semiconductor is called a P-type semiconductor (Figure 1.33). The third group atoms have three valence electrons and pure Ge or Si atoms have four valence electrons. The three valence electrons of either Ge or Si form covalent bonds with three valence electrons of aluminum or boron atom and only three covalent bonds are completed. In the fourth covalent bond Ge or Si atom only contributes to one valence electron and there is a shortage of one electron, which is called a hole. There will be as many number of holes as there are impurity atoms. As the impurity atom accepts one electron, the impurity atom is called an acceptor atom. When an acceptor atom accepts an electron the atom becomes a negatively charged ion, which is immobile. The hole moves from one atom to the other. A P-type semiconductor has a fairly large number of holes and a smaller number of electrons. Hence, holes are called majority carriers and electrons are called minority carriers. Conduction in this type of material is essentially through holes. When an electric field is applied holes move toward the negative terminal of the battery, constituting an electric current (Figure 1.34). A P-type semiconductor has a higher hole density p and a lower electron density n than the same intrinsic semiconductor. Let NA be the acceptor density. Then p = NA. From the mass action law n=

p = NVe

ni 2 NA

(EV − EF )

(EV − EF )

kT

kT

NA = NVe

(1.48)

(EV − EF ) e

kT

=

NA NV

27

Introduction Ge

Ge

+4

+4

Ge +4 Broken covalent bond B Ge

Ge +4

+3

Conduction band Energy

Hole

Valence electrons

+4

Electrons Holes

Covalent bond +4

+4

Valence band

(b)

+4

Ge

Ge Ge (a)

Figure 1.33 (a) Covalent bonds with third group impurity (b) energy bands in P-type semiconductor Electron flow

− −

− −

Negative ions

−

−

−

−

Hole flow

External emf

Figure 1.34 Conduction in P-type semiconductor

(EV − EF ) = ln N A kT

NV

EF = E V − kT ln

NA NV

The Fermi level of the P-type semiconductor is EFp = E V + kT ln

NV NA

(1.49)

When the acceptor density is increased, the Fermi level moves closer to the edge of the valence band. If NA = NV , the Fermi level enters the valence band: the semiconductor is then said to be degenerate.

1.4.7 Conductivity of Semiconductor Materials In a conductor the conduction is mainly due to electrons and the conductivity of a conductor is given as

28

Electronic Devices and Circuits

s = ne me However, in a semiconductor the conduction is due to electrons and holes as well. Hence, the conductivity due to electrons in a semiconductor can be written as s n = ne me and that due to holes as s p = pe mp

The total conductivity is given as

(

s = ne me + pe mp = e nme + pmp

)

(1.50)

where n = electron density (number of electrons in unit volume) p = hole density e = charge of an electron v me = = mobility of an electron E v = drift velocity E = electric field Meters v Meter 2 Second = = me = Volt E Volt-sec Meter mp = mobility of a hole The resistivity r =

1 1 = s e nme + pmp

(

)

(i) Conductivity of intrinsic semiconductor: In an intrinsic semiconductor n = p = ni. Therefore, from Eqn. (1.50)

(

s i = ni e me + ni e mp = eni me + mp

)

(1.51)

If an electric field e is applied, then

(

)

Current density, J = s i e = eni me + mp e

(1.52)

If A is the cross-sectional area of the semiconductor

(

)

I = J A = eni me + mp eA

(1.53)

(ii) Conductivity of an N-type semiconductor: In an N-type semiconductor n >> p If n = ND, then from Eqn. (1.50) s n = N D e me

(1.54)

(iii) Conductivity of a P-type semiconductor: In a P-type semiconductor p >> n If p = NA, then (1.55) r = N em p

A

p

Introduction

29

1.4.8 Drift Current When an electric field is applied to a semiconductor material the electrons and holes drift to the positive and negative terminals of the battery. The drift current density of electrons is J n(drift ) = s n e = N D e me E

(1.56)

And the drift current density of holes is J p(drift ) = s p e = N A e mp E

(1.57)

Example 1.9 The following data is available for an intrinsic semiconductor at 300 K: The mobility of electrons = 0.39 m2/V-s and the mobility of holes = 0.19 m2/V-s and ni = 2.4 × 1019/m3. Calculate the resistivity of the material.

(

)

s i = eni me + mp = 1.6 × 10 −19 × 2.4 × 1019 (0.39 + 0.19)

Solution:

= 2.227( Ω − m)−1 Resistivity, ri =

1 1 = = 0.449 Ω − m s i 2.227

Example 1.10 Calculate the number of donor atoms for an N-type semiconductor whose resistivity is 0.449 Ω - m. The mobility of the electrons is 0.6 m2/V-s. Solution: s n = N D e me ∴ ND =

sn 1 1 = = rn e me 0.449 × 1.6 × 10 −19 × 0.6 e me

N D = 2.32 × 1019 /m 3 Example 1.11 A pure Ge at 300 K having the density of the charge carriers as 2.25 × 1019/ m 3 is doped with impurity phosphorus atoms at 1 in 106. The electron and hole mobilities are 0.4 m2/V-s and 0.2 m2/V-s, respectively. The number of intrinsic atoms is 4 × 1028 atoms/m3. If all the impurity atoms are ionized, find the resistivity of the N-type semiconductor. Solution: Given:

ni = 2.25 × 1019 /m3 me = 0.4 m 2 /V-s mp = 0.2 m 2 /V-s Doping concentration = 1 × 106

30

Electronic Devices and Circuits

28 ∴ Impurity atoms/m3 = Number of intrinsic atoms = 4 × 10 = 4 × 1022 /m3 106 106

If all the impurity atoms are ionized, n = 4 × 1022 /m 3 . From the law of mass action np = ni2 Therefore, the hole concentration p = rn =

(

19 ni2 2.25 × 10 = n 4 × 1022

2

)

= 1.26 × 1016 /m 3

1 1 1 = = −19 22 s n e n me + p mp 1.6 × 10 4 × 10 × 0.4 + 1.26 × 1016 × 0.2

(

≅

)

(

1 1.6 × 10

−19

(4 × 10

22

× 0.4

)

)

= 0.39 × 10 −3 Ω − m

1.4.9 Diffusion Current Diffusion current exists in a semiconductor, as electrons and holes diffuse from high concentration region to low concentration region. Consider Figure 1.35 in which there is a large concentration of holes on the left when compared to the right of the vertical line Y1Y2. Due to the natural process of diffusion holes diffuse from left to the right, resulting in hole current. Diffusion of holes from high concentration to low concentration Y1 p

Hole gradient +

Slope = −

dp dX

∆p

Y2

X

∆x

Figure 1.35 Diffusion of holes in random motion

The diffusion current density is proportional to the rate of change of hole concentration with distance x (concentration gradient) and is given as J p(diffusion) = qDp Dp = diffusion coefficient in m2/s dp = concentration gradient of holes dx

dp dx

(1.58)

Introduction

31

Similarly, diffusion current density of electrons that move from right to left is J n(diffusion) = qDn

dn dx

(1.59)

The total electron current density due to drift and diffusion, from Eqs (1.56) and (1.59), is J n = J n(drift ) + J n(diffusion) = N D q me e + qDn

dn dx

  D   dn   = q me  N D e +  n      me   dx   

(1.60)

1.4.10 Einstein’s Relationship The diffusion coefficient D and the mobility µ are related to each other by the following equation, known as Einstein’s equation: Dp Dn kT = = (1.61) q mp mn At room temperature (300 K),

kT = 0.026 V q Dp = mp

Dn = 0.026 V mn

(1.62)

It is known that for Ge at 300 K, me = 0.38 m 2 / V-s, then Dn = 0.38 × 0.026 = 0.0099 m 2 /s

1.4.11 Mean Lifetime and Diffusion Lengths of Charge Carriers In an intrinsic semiconductor at room temperature electron hole pairs are generated due to thermal agitation. It is possible that some electrons may recombine with holes and at the same time new electron hole pairs can be generated. The instant at which a charge carrier is generated to the time instant at which it recombines is known as the lifetime of the charge carrier. If tp and te are the time intervals for which holes and electrons exist before recombination, then these two time intervals are called the lifetimes of the holes and electrons, respectively, and the average lifetime is called the mean lifetime. When charge carriers move from a high concentration region to a low concentration region, their concentration decreases exponentially due to recombination. The average distance covered by a charge carrier before recombination is called the diffusion length and is designated as Lp for holes and Le for electrons. Lp = Dp t p

Le = Dn t n

where Dp and Dn are the diffusion constants for holes and electrons, respectively.

(1.63)

32

Electronic Devices and Circuits

1.4.12 The Continuity Equation In a semiconductor, charges drift due to an electric field, diffuse due to concentration gradient, and recombine due to the presence of charges of opposite polarity. The differential equation that governs all these effects, based on the fact charge can neither be created or destroyed, is the continuity equation. The concentration of carriers in a semiconductor material varies with time and distance. p holes/m3

Area A

Ip

Ip + dIp

x

x + dx

Figure 1.36 Law of conservation of charge

Consider a very small element of volume having area, A, and length, dx, in which the average hole 3 concentration is p/ m as shown in Figure 1.36. The x-dimensions of n and p regions are assumed to be large when compared to the diffusion length of the respective regions. Let I p be the current entering the volume at x at time t and Ip + dIp the current leaving at x + dx about the same time t, then the number of Coulomb/s decrease in the volume is dIp. From the definition of current Ip =

NA q t

(1.64)

where NA is the number of holes. Hence, it can be said that dI p = dI p

Or

q

=

qdN A t dN A t

(1.65)

= Decrease in the number of holes per second Volume = Adx ∴ dp =

dN A Adx

33

Introduction

Dividing both sides of Eqn. (1.55) by Adx dI p dN A 1 1 dN A 1 dp × = × = × = Adx q Adx t Adx t t

(1.66)

= Decrease in hole concentration per second dI p dp 1 A 1 dJp ∴ = × = × dx t q q dx

(1.67)

Let be p0 the hole concentration under thermal equilibrium and tp the mean lifetime of the hole. Then increase in hole concentration per second is g=

p0 tp

(1.68)

p Decrease in the number of holes/s due to recombination per unit volume = 0 tp As charge can neither be crated nor destroyed,

(1.69)

dp = (Increase in hole concentration/s) − (Decrease in hole concentration/s) dt Using Eqs (1.67), (1.68), and (1.69), dp p0  p 1 dJ P  p0 − p 1 dJ P = − + − = dt t p  t p q dx  q dx tp

(1.70)

As p is a function of both x and t, the derivatives in Eqn. (1.70) become partial derivatives. ∂p p0 − p 1 ∂J p = − ∂t tp q dx

(1.71)

Magnetic field perpendicular to I (into the paper) B

1.4.13 The Hall Effect The Hall effect can be used to determine the type of majority charge carriers as well as carrier concentration and mobility. Consider a thin, flat, uniform semiconductor bar (Figure 1.37). Let a voltage V be applied such that

I +

+

+

+

+

−

Holes − −

−

−

VH

Figure 1.37 Hall effect (positive VH )

34

Electronic Devices and Circuits

Magnetic field perpendicular to I (into the paper) the current I flows from left to right (meaning that the current is carried by the positive charges) along B the length of the bar. Let, now, a uniform magnetic field B be applied perpendicular to the flat surface. I This results in the positive charges being deflected − − − − − upward. Consequently, the upper edge of the bar gets VH Electrons positively charged and the lower edge gets negatively + + + + + charged, resulting in a positive voltage, VH, between the upper and the lower edges of the semiconductor Figure 1.38 Hall effect (negative VH) bar. This voltage VH is called the Hall voltage. Alternately, if the current I is carried by the negative charges (electrons) that move from right to left (because current flow is opposite to the direction of the electron flow), then negative charges are deflected upward by the magnetic field. The upper edge of the bar, therefore, becomes negatively charged and the lower edge positively charged. The Hall voltage VH, now, is negative (Figure 1.38). It is now evident from the above inferences that it is possible to determine the type charge carriers depending on the polarity of the Hall voltage. The Hall voltage is given as

VH = vd wB

(1.72)

where vd is the drift velocity and w is the width of the bar. From Eqn. (1.72), it is seen that the Hall voltage is directly proportional to the magnitude of the magnetic field.

1.4.14 Basic Unbiased PN Junction It is already learnt that in a P-type semiconductor holes are majority carries and electrons are the minority carriers. Similarly, in an N-type semiconductor electrons are the majority carriers and holes are the minority carriers (Figure 1.39). Usually, electrons are uniformly distributed in the N-type semiconductor and holes are uniformly distributed in the P-type semiconductor. The N- and P-type bars are placed side by side, representing a PN junction. Few free electrons from the N-side crossover (diffuse) to the P-side of the junction attracted by the holes and fill the holes. These free electrons give to some atoms one more electron and create negative ion. Similarly, holes diffuse from the P-side to the N-side and give to some atoms a hole and create positive ion on the N-side near the junction. As negative ions are created on the P-side near the junction, the P-side acquires a negative voltage. At the same time as positive ions are created on the N-side near the junction, the N-side acquires a positive voltage. A layer is created on either side of the junction, which is devoid of charge carriers and is called the depletion, or the space charge, or the transition region. The thickness of the depletion region is usually 0.5 µm. The diffusion of the charge carriers creates a barrier potential, which is negative on the P-side and positive on the N-side. At equilibrium the barrier field prevents further movement of electrons; the majority carriers on the N-side to the P-side and holes, the majority carriers on the P-side to the N-side of the junction (Figure 1.40). However, minority carriers on either side, aided by the barrier potential, can crossover to the other side of the junction. The magnitude of the barrier potential can be calculated by knowing the doping densities and the junction temperature.

Introduction

Positive ions

Negative ions

Holes

Electron

−

−

− −

− − − −

+ +

+

+

+

+

+

−

−

− −

− − − −

+ +

+

+

+

+

+

−

−

− −

− − − −

+ +

+

+

+

+

+

P-type semiconductor

N-type semiconductor

Figure 1.39 P and N-type semiconductors

Depletion region

−

−

− −

− −

− −

+ +

+

+

+

+

+

−

−

− −

− −

− −

+ +

+

+

+

+

+

−

−

− −

− − − −

+

+

+

+

+

+ +

(a) PN junction

P-type

Hole concentration

N-type Electron concentration

(b) Electron Hole concentrations Positive space charge + −

Negative space charge (c) Concentration of uncovered charges

VB 0 x0

x

(d) Variation of barrier potential

Figure 1.40 PN junction

Electrons Holes

35

36

Electronic Devices and Circuits

The concentration of electrons is the same as the concentration of the donor atoms and the concentration of the holes is the same as the concentration of the acceptor atoms. The barrier field can be found from Poisson equation: d 2V −r (1.73) = ∈ dx 2 where r is the charge density, ∈ is the permittivity, and V is the electrostatic potential at a distance x. Permittivity (∈) is a measure of the ability of a material to be polarized by an electric field. Integrating Eqn. (1.73) x −r −dV F= =∫ dx (1.74) x dx 0 ∈ The electrostatic potential at a point is x

Vx = − ∫ Fdx x0

(1.75)

This is the barrier potential, VB. VB can also be obtained as N N  VB = VT ln  D 2 A   ni 

(1.76)

Additional Solved Examples Example 1.12 Mobilities of electrons and holes in pure Ge at room temperature are 0.36 m2/V-s and 0.18 m2/V-s, respectively. If the density of electrons is 2.4 × 1019/ m 3, calculate its resistivity. Solution:

(

)

s i = eni me + mp = 1.6 × 10 −19 × 2.4 × 1019 (0.36 + 0.18) = 2.074 (Ω − m )

Resistivity, ri =

−1

1 1 = = 0.482 Ω − m s i 2.074

Example 1.13 To an intrinsic Si crystal (i) donor-type impurity atoms are added so as to have an N-type semiconductor having a resistivity of 10 −4 Ω − m. (ii) Acceptor-type impurity atoms are added so as to have an P-type semiconductor having a resistivity of 10 −4 Ω − m . Calculate the density of the impurity atoms added in each case: m e = 0.36 m 2 / V - s and m p = 0.18 m 2 / V − s . Solution: (i) s n = eN D me or ND = (ii) s p = eN A mp

1 = eN D me rn

1 1 = = 1.736 × 1023/ m 3 rn × e × me 10 −4 × 1.6 × 10 −19 × 0.36 or

1 = eN A mp rp

Introduction

NA =

37

1 1 = −4 = 3.472 × 1023/m3 rp × e × mp 10 × 1.6 × 10 −19 × 0.18 −1

Example 1.14 An N-type Ge semiconductor has s n = 100 (Ω − cm ) and me = 0.39 × 10 4 cm / V − s. Calculate the position of the Fermi level with reference to the intrinsic Fermi level at 300 K. Solution: N D =

sn 100 1017 = = = 1.60 × 1017/ cm 3 e me 1.6 × 10 −19 × 0.39 × 10 4 1.6 × 0.39 EFn = EFi + kT ln

ND Ni

For pure Si n = p = 1.5 × 1010 /cm 3 at 300 K 10 3 For pure Ge n = p = 2.5 × 10 /cm at 300 K

k = Boltzmann constant in eV/K = 8.61 × 10 −5 eV/K

kT = 8.61 × 10 −5 × 300 = 0.026 eV  1.6 × 1017  EFn = EFi + 0.026 ln  = EFi + 0.026 × 8.764 = EFi + 0.228 eV  2.5 × 1013 

Example 1.15 A P-type Ge semiconductor has hole density of 3.29 × 1017/ cm3. Calculate the position of the Fermi level with reference to the intrinsic Fermi level at 300 K. Solution: NA = 3.29 × 1017/ cm3 EFp = EFi + kT ln

NA Ni

For pure Ge n = p = 2.5 × 1013/cm 3 at 300 K k = Boltzmann constant in eV/K = 8.61 × 10 −5 eV/K

kT = 8.61 × 10 −5 × 300 = 0.026 eV  3.29 × 1017  = EFi + 0.026 × 9.48 = EFi + 0.246 eV EFP = EFi + 0.026 ln   2.5 × 1013 

38

Electronic Devices and Circuits

Example 1.16 A Germanium N-type semiconductor has its Fermi level at 0.2 eV below the conduction band edge. Estimate its dopant, majority, and minority carrier concentrations at equilibrium K. Assume ni = 2.5 × 1019/m3 and me = 1.2 m .

Solution: n = N C e

− ( EC − EF ) kT

We have m = 9.107 × 10 −31 kg, k = 1.38 × 10 −23 J/K, T = 300 K, and

h = 6.625 × 10 −34 J-s , k in eV/K = 8.61 × 10 −5 eV/K 3

 2 2p × 1.2 × 9.107 × 10 −31 × 1.38 × 10 −23 × 300  2pme kT    = 3.29 × 1025 /m 3 NC = 2  =2 2 − 34  h2    6.625 × 10 3 2

(

(

n = NC e

− EC − EF kT

(

)

0.2 −5 × 300

= 3.290 × 1025 × e 8.62 ×10

)

= 14.46 × 1021 / m 3

2

)

2.5 × 1019 n2 = 4.32 × 1016/m 3 p= i = n 14.46 × 1021

Summary • Resistors can be classified as (i) carbon composition resistors; (ii) film resistors; (iii) wire wound resistors; and (iv) semiconductor resistors. • Electrolytic capacitors are polarized capacitors. Consequently, while connecting to a dc voltage the positive end of the voltage source should be connected to the positive terminal of C and the negative end to the negative terminal of C. Improper polarization can damage the capacitor. • Electrons circle the nucleus at different elliptical orbits called shells. A definite energy level is associated with each shell. A shell can accommodate only 2n2 electrons. • The forbidden energy gap is large for the insulators, typically of the order of 5 eV or more. For the semiconductors this energy gap is typically of the order 1 eV. For the conductors the forbidden gap does not exist and the conduction and valence bands overlap. • An intrinsic semiconductor at room temperature has a fewer number of electrons in the conduction band and an identical number of holes in the valence band, resulting in a small current on the application of an external field. • Fermi energy level is defined as the highest occupied energy level found in that material at absolute zero temperature (0 K or −273.15°C). It is a reference energy level. • When a small number of fifth group impurities such as bismuth, antimony, arsenic, and phosphorus are added to a pure semiconductor during crystal growth, the resulting semiconductor is called an N-type semiconductor.

Introduction

39

• When a small number of third group impurities such as gallium, indium, aluminum, and boron are added to a pure semiconductor during crystal growth, the resulting semiconductor is called a P-type semiconductor. • When an electric field is applied to a semiconductor material the electrons and holes drift to the positive and negative terminals of the battery, constituting a current called the drift current. Diffusion current exists in a semiconductor, as electrons and holes diffuse from a high concentration region to a low concentration region.

multiple ChoiCe QueStionS 1. An intrinsic semiconductor is characterized by _________ valence electrons. (a) 8 (c) 4

(b) 2 (d) 16

2. Pure germanium and silicon at absolute zero behave as (a) perfect conductors (b) insulators (c) N-type semiconductors (d) P-type semiconductors 3. In an N-type material, majority carriers are (a) electrons (c) both electrons and holes

(b) holes (d) none of the above

4. In a P-type semiconductor the minority carriers are (a) electrons (b) holes (c) both electrons and holes (d) none of the above 5. An electron that is in the conduction band has (a) no mobility (c) energy more than the one in valence band

(b) no energy (d) less than the one in valance band

6. When an electron jumps from the valence band to the conduction band, it leaves a vacancy, which is called (a) energy band (b) hole (c) covalent bond (d) electron–hole pair 7. Which one of the following is a doping material? (a) N-type semiconductor (c) pentavalent atom

(b) P-type semiconductor (d) uncovered charges

8. Energy band gap size for insulators is in the range __________ eV. (a) 1–2 (b) 2–3 (c) 3–4 (d) > 4 9. In an intrinsic semiconductor, number of electrons __________ the number of holes. (a) equal (b) greater than (c) less than (d) none of the above 10. Forbidden band lies (a) above the conduction band (c) between valence and conduction bands

(b) below the valance band (d) none of the above

40

Electronic Devices and Circuits

11. The concentration of the minority carriers in the N-type semiconductor depends on (a) type of donor atom added (b) quality of intrinsic semiconductor (c) temperature of the material (d) number of donor atoms added 12. Fermi energy level for intrinsic semiconductors lies (a) at middle of the forbidden band gap (b) close to conduction band (c) close to valence band (d) above the conduction band 13. Fermi energy level for N-type extrinsic semiconductors lies (a) at middle of the forbidden band gap (b) close to conduction band (c) close to valence band (d) above the conduction band 14. Fermi energy level for P-type extrinsic semiconductors lies (a) at middle of the forbidden band gap (b) close to conduction band (c) close to valence band (d) above the conduction band 15. Electrical conductivity of the insulators is of the order: (a) 10 −10 (Ω − mm ) (c) 10 −10 (Ω − m )

−1

−1

(b) 10 −10 ( Ω − cm ) (d) 10 −8 (Ω − m )

−1

−1

16. Covalent bonding between electrons of adjacent atoms refers to: (a) the addition of an impurity (b) the sharing of valence electrons (c) the generation of excess electrons (d) the generation of excess holes 17. Mobile electrons are found (a) below the valence band (c) in the forbidden gap

(b) below the conduction band (d) in the conduction band

18. Mobile holes are found (a) in the valence band (c) in the forbidden gap

(b) below the conduction band (d) in the conduction band

19. Germanium doped with Arsenic will result in (a) an intrinsic semiconductor (c) an N-type semiconductor

(b) an extrinsic semiconductor (d) a P-type semiconductor

20. Silicon doped with Aluminum will result in (a) an intrinsic semiconductor (c) an N-type semiconductor

(b) an extrinsic semiconductor (d) a P-type semiconductor

21. The forbidden gap of the semiconductor material (a) does not vary with temperature (c) decreases with temperature

(b) increases with temperature (d) may increase or decrease

22. In an intrinsic silicon, the forbidden gap is (a) 1.12 eV (c) 3 eV

(b) 0.7 eV (d) 0.1 eV

23. In an intrinsic Ge, the forbidden gap is (a) 1.12 eV (c) 3 eV

(b) 0.7 eV (d) 0.1 eV

Introduction

41

24. The diffusion current in a semiconductor is influenced by (a) externally applied voltage (c) electric field

(b) concentration gradient of mobile charges (d) magnetic field

25. Electrons in the outermost orbit are called (a) valence electrons (c) donor electrons

(b) free electrons (d) acceptor electrons

26. A resistor with color bands red, violet, green, and black will have a value (a) 27 K ± 10% K (c) 270 K ± 5% K

(b) 2.7 M ± 20% K (d) 2.7 K ± 2% K

27. Which of the following doping schemes will produce a P-type semiconductor? (a) germanium with phosphorus (c) germanium with antimony

(b) silicon with germanium (d) silicon with indium

28. The depletion region in a junction diode contains (a) both minority and majority charge carriers (c) only impurity atoms

(b) only majority charge carriers (d) only ions (immobile charges)

Short anSwer QueStionS 1. Three resistances R1 = 30 kΩ , R2 = 30 kΩ , and R3 = 30 kΩ are connected in series in a circuit. What is the effective resistance? 2. Three resistances R1 = 30 kΩ , R2 = 30 kΩ , and R3 = 30 kΩ are connected in parallel in a circuit. What is the effective resistance? 3. Three capacitances C1 = 30 mF , C2 = 30 mF , and C3 = 30 mF are connected in series in a circuit. What is the effective capacitance? 4. Three capacitances C1 = 30 mF , C2 = 30 mF , and C3 = 30 mF are connected in parallel in a circuit. What is the effective capacitance? 5. Based on the conductivity, how are materials classified as? 6. Distinguish between insulators, semiconductors, and conductors based on the forbidden gap. 7. What is an intrinsic semiconductor? 8. Why are germanium and silicon the most preferred semiconductor materials? 9. What is an extrinsic semiconductor? 10. What is an N-type semiconductor and what are donor impurities? 11. What is a P-type semiconductor and what are acceptor impurities? 12. What is the mean lifetime of an electron? 13. In which bands does conduction of electrons and holes takes place? 14. State the mass action law. 15. What is drift current in a semiconductor?

16. What is diffusion current in a semiconductor? 17. What is depletion region and what is barrier potential in a PN junction? 18. Between Ge and Si, which one will have a larger conductivity at room temperature? 19. Describe Hall effect. 20. How does Hall voltage help in deciding whether the semiconductor is an N- or P-type?

42

Electronic Devices and Circuits

long anSwer QueStionS Discuss electronic structure of elements and electron configuration of some of the fourth group elements. What is a P-type semiconductor and derive the expression for its Fermi level? What is an N-type semiconductor and derive the expression for its Fermi level? Write short notes on (i) mass action law (ii) continuity equation and (iii) Hall effect. 5. Discuss with relevant diagrams the working of unbiased PN junction. 1. 2. 3. 4.

unSolved problemS 14 3 1. An N-type Si sample has the donor concentration at 300 K as 5 × 10 /cm . Determine the electron hole concentrations and the conductivity. 2. A rod of intrinsic silicon is 1 cm long and has a diameter of 1 mm. At room temperature, the 16 3 intrinsic concentration in the silicon is ni = 1.5 × 10 /m . The electron and hole mobilities 2 2 are me = 0.13 m /V − s and mh = 0.05 m / V − s . Calculate the conductivity s of the silicon and the resistance R of the rod, assuming circular cross section with diameter d. 2 3. For Ge at 300 K, the mobility of electrons = 0.39 m /V − s and the mobility of holes −19 19 3 2 = 0.19 m /V − s , ni = 2.5 × 10 /m , and e = 1.6 × 10 C . Calculate the resistivity of the material. 4. For Si at 300 K, the mobility of electrons = 0.15 m 2 /V − s, the mobility of holes = 0.05 m 2 /V-s , ni = 0.15 × 1016 /m 3, and e = 1.6 × 10 −19 C . Calculate the resistivity of the material. 5. A p-type silicon semiconductor is made by adding boron at the rate of one boron atom per 4 × 108 silicon atoms, ni = 1.5 × 1016 at 300 K. There are 5 × 10 28 germanium atoms per m3. Calculate (i) the acceptor atom density in the p-material; (ii) the hole density; (iii) the electron density; and (iv) n n 6. A sample of silicon has a resistivity of 2 × 103 Ω − m at 300 K. Find the donor concentration. i

DIODES, CHARACTERISTICS, AND APPLICATIONS

2 Learning objectives

After reading this chapter, the reader will be able to � � � �

2.1

Understand the working of a PN junction diode, its V-I characteristics, and its equivalent circuits Appreciate the effect of temperature on the V-I characteristic of a PN junction diode Use the diodes in applications such as clipping and clamping circuits Understand the principle of working of some special-purpose diodes such as tunnel diode, varactor diode, Schottky barrier diode, PIN diode, photodiode, Gunn diode and IMPATT diode

PN JUNCTION DIODE

An unbiased PN junction was discussed in Chapter 1, and it was mentioned that a built-in potential will be developed at the junction. The energy band diagrams of the P-type and N-type semiconductors are shown in Figure 2.1. When a PN junction is formed, under equilibrium conditions (no current flow), as two materials come together, their Fermi levels must line up. For a PN junction, this will cause a shift in the energy bands. This shift will be directly proportional to the built-in potential (Figure 2.1).

ECP

ECN

EF1

EFN EF1

EFP EVP P-type EFP < EF1

eVB = eVP + eVn

ECP eVp

ECN EFN eVn EF1

EF1 EFP EVP

EVN N-type EFN > EF1

EVN Unbiased PN junction

Figure 2.1 Energy band diagram of a PN junction

From Figure 2.1, eVp = EFI − EFP

(2.1)

eVn = EFN − EFI

(2.2)

44

Electronic Devices and Circuits

and eVj = eVB = e(Vp + Vn)

(2.3)

We have (E

n = NC e

− ECN ) kT

(E

FN

− EFI ) kT

eVn

FN

= ni e

= ni e kT

(2.4)

Let n = ND, then from Eqn. (2.4) eVn

N D = ni e kT

(2.5)

N  Vn = VT ln  D   ni 

(2.6)

N  Vp = VT ln  A   ni 

(2.7)

Taking logarithms

Similarly,

Combining Eqs (2.6) and (2.7) N N  N  N  VB =Vn + Vp =VT ln  D  +VT ln  A  =VT ln  D 2 A   ni   ni   ni 

(2.8)

Example 2.1 If a PN junction has NA = 3 × 1018/cm3 on the P-side and ND = 1016/cm3 on the N-side, (i) Calculate the Fermi level in the P- and N-regions at 300 K. (ii) Calculate the built-in potential. Solution: (i) Assume that p = NA and n = ND. On the P-side, ( EFI − EFP )

p = ni e

kT

Taking logarithms  p  3 × 1018  EFI − EFP = kT ln   = 0.026 ln  = 0.497 eV  ni   1.5 × 1010  Similarly,  n  1 × 1016  EFN − EFI = kT ln   = 0.026 ln  = 0.349 eV  ni   1.5 × 1010  VB = ( EFI − EFP ) + ( EFN − EFI ) = 0.497 + 0.349 = 0.846 eV   N N  3 ×1018 × 1 × 1016 (ii) VB =VT ln  A 2 D  = 0.026 × ln   = 0.846 eV 2  ni   1.5 ×1010 

(

)

Diodes, Characteristics, and Applications

45

Example 2.2 An abrupt junction has doping densities of NA = 1015 atoms/cm3, and ND = 1016 atoms/cm3. Calculate the built-in potential at 300 K. Solution: We have, VB = 0.026 ln

 15  NA ND 10 × 1016  = 0.638 V = 0.026 × ln  2 2 ni  1.5 × 1010 

(

)

Example 2.3 Compute the resistivity and the resistance of the semiconductor material of length 1mm and area of cross section of 200 µm2 at 300 K. Assume the mobility of electrons to be 1200 cm2/V-s and the electron doping level to be n = 1016/cm3. Solution: Given n = 1016 / cm 3 = 1022 / m 3

me = 1200 cm 2 / V − s =1200 × 10 −4 m 2 / V − s

We have, s = ne me =1022 ×1.6 × 10 −19 ×1200 ×10 −4 =192 (Ω − m)−1 r=

R=

1 1 = = 52.08 × 10 −4 Ωm s 192

r l 52.08 × 10 −4 × 1 × 10 −3 = = 26.04 m Ω A 200 × 10 −12

When a PN junction is formed, the resultant two-terminal device is called a junction diode. The P-terminal is called the anode (A) and the N-terminal is called the cathode (K). Under unbiased condition, there is no conduction, that is no current exists in the device. For current to flow, the device must be biased suitably. By biasing, it means the application of an external voltage. There are two methods of biasing a junction diode: (i) forward biasing and (ii) reverse biasing.

2.1.1 Forward Bias The forward-biased junction diode is shown in Figure 2.2. By forward bias, it is meant that the positive terminal of the external source is connected to the P-material and the negative terminal to the N-material, respectively. By doing so, the externally connected dc voltage establishes an electric field opposite to the potential barrier, thereby reducing the potential barrier. The potential barrier is typically 0.1 V for Ge and 0.5 V for Si. As such, a small external voltage is enough to eliminate the barrier, and the junction resistance becomes almost zero. Now aided by this external voltage, the free electrons in the N-material cross the junction and move into the P-region.

46

Electronic Devices and Circuits

The free electrons combine with holes near the junction. Since a hole is in the covalent bond, when a free electron combines with a hole, it becomes a valence electron and in the P-region the electrons travel as valence electrons and enter the positive terminal of a battery. Therefore, the current is mainly due to the majority carriers only and is called the forward current of the diode. Barrier potential with forward bias

VB = Barrier potential with no external field

Metal contact

Metal contact

A

Schematci representation of diode

K

P

K

A

mA

N

mA

+

− −

I

+

V

V

Figure 2.2 Forward-biased PN junction diode

2.1.2 Reverse Bias When the positive terminal and the negative terminal of a battery are connected to the N-type material and the P-type material, respectively, then the type of biasing is called reverse bias. Electrons in the N-region and holes in P-region move away from the junction, and therefore reverse bias increases the potential barrier (Figure 2.3), which prevents the flow of the majority charge carriers across the junction. The junction offers a very high resistance. As there is no combination of electrons and holes, practically the reverse current is zero, and whatever little current is present is mainly due to the minority carriers only. Barrier potential– with external reverse bias voltage Barrier potential– with no external voltage

P

µA

N

+

µA +

− V

V

I

Figure 2.3 Reverse-biased PN junction diode

I

−

Diodes, Characteristics, and Applications

47

From the two methods of biasing, it is evident that when forward biased, the junction diode offers a very small forward resistance, resulting in an appreciable forward current. When reverse biased, the current in the device is zero. Alternately, it can be said that when forward biased, the junction diode behaves as a closed switch. On the contrary, when reverse biased, it behaves as an open switch. Hence, a junction diode can either be used to convert a bidirectional signal into a unidirectional one, or it can be used as a rectifier.

Current Components in a PN Junction Diode In a forward-biased diode, the depletion region becomes small. Holes are injected from the P-region into the N-region, and electrons are injected from the N-region into the P-region. The number of these charge carriers decreases exponentially with increasing distance from the junction. As the holes are minority carriers in the N-type and as the number of holes in the N-type decreases with increasing distance from the junction, the hole current I pn in the N-region decreases with distance, and hence this current may be expressed as a function of x as I pn ( x ). Similarly, as the electrons are minority carriers in the P-type and as the number of electrons in the P-type decreases with increasing distance from the junction, the electron current I np in the P-region decreases with distance and is expressed as I np ( x ) (Figure 2.4). When holes cross over from P-side to the N-side, there is a current from P to N. In addition, when electrons cross over from N-side to the P-side, once again there is a current from P to N, since the current is supposed to be flowing opposite to the direction of the electron flow. Therefore, at x = 0 , the total current at the junction I is I = I pn ( 0 ) + I np ( 0 )

(2.9)

It is noted that I pn ( x ) and I np ( x ) decrease as we move away from the junction on the N-side and P-side, respectively. But the total current I should remain constant at any given distance x from the junction. Since the junction is forward biased, there exists a hole current I pp ( x ) on the P-side and an electron current I nn ( x ) on the N-side, which are majority carrier currents due to drift. Therefore, the total current on the P-side is I = I pp ( x ) + I np ( x )

(2.10)

and the total current on the N-side is I = I nn ( x ) + I pn ( x )

(2.11)

From Figure 2.4, it can be noted that as holes, the majority carriers in the P-side approach the junction, some of them may combine with electrons crossing the junction from the N-side. Therefore, I pp decreases near the junction and is equal to I np . Similarly, I nn decreases near the junction and is equal to I pn . However, the total current I remains constant.

Law of the Junction In the case of an unbiased junction, let the barrier potential, VB =V0 . Using Boltzmann relation, it can be written as follows: ppo = pno e

Vo VT

(2.12)

48

Electronic Devices and Circuits

where, ppo = concentration of holes on the P-side under thermal equilibrium pno = concentration of holes on the N-side under thermal equilibrium But, with the application of forward-bias voltage, V ppo = pn ( 0 )e

_ Vo V VT

(2.13)

where, pn ( 0 ) = concentration of holes on the N-side near the junction

V

I

I

From Eqs (2.12) and (2.13) pno e

Vo VT

P

= pn ( 0 )e

∴ pn ( 0 ) = pno e

V VT

Vo −V VT

N x=0

x

(2.14)

x

I Ipp

Inn

It can be noted from Eqn. (2.14) that the Inp Ipn total concentration of holes at the edge of the junction is an exponential function of x=0 x x the applied bias voltage. It is obviously evident Figure 2.4 Current components in a PN junction diode that the hole concentration near the junction under forward-bias condition, pn ( 0 ) , is much larger than the hole concentration under thermal equilibrium, pno . Equation (2.14) is called the law of the junction.

The Diode Equation From Eqn. (2.14), injected or excess charge concentration Pn ( 0 ) = pn ( 0 ) − pno = pno e

V VT

 VV  − pno = pno  e − 1   T

(2.15)

Similarly,  VV  N p ( 0 ) = npo  e − 1  

(2.16)

T

The hole current that crosses the junction from the P-side to the N-side is given as follows:  VV  AqDp Pn ( 0 ) AqDp I pn ( 0 ) = = pno  e − 1 Lp Lp   T

where, A = area of cross section of the junction Dp = diffusion constant for holes and Lp = diffusion length of the holes

(2.17)

Diodes, Characteristics, and Applications

49

Similarly, the electron current that crosses the junction from the N-side to the P-side is given as follows: I np ( 0 ) =

 VV  AqDn N p ( 0 ) AqDn = npo  e − 1 Ln Ln  

(2.18)

T

where, Dn = diffusion constant for electrons and Ln = diffusion length of the electrons I = I pn ( 0 ) + I np ( 0 ) =

AqDp Lp

 VV   VV  AqD n pno  e − 1  + npo  e − 1 Ln     T

T

  AqDp  V AqDn = pno + npo   eV − 1 Ln  Lp   T

 VV  I = I S  e − 1  

Or

T

where,

IS =

AqDp Lp

pno +

AqDn npo Ln

(2.19)

(2.20)

I is the diode current in A V is the voltage at the anode with respect to the cathode in V IS is the leakage or reverse saturation current in A In general,

 hVV  I = IS  e − 1   T

(2.21)

h is the emission coefficient or the ideality factor, and is 1 Ge and 2 Si, respectively The V-I characteristics of a diode are shown in Figure 2.5.

Forward Bias From Eqn. (2.21), if V = VD = 0.1 V and h = 1,  0.1  I D = I S  e 0.026 − 1 = I S ( 46.80 − 1) = 45.80 I S   Usually, when forward biased, VD > 0.1V, I D >> I S ; therefore, VD

I D = ISe

hVT

(2.22)

Reverse Bias When reverse biased, V = VD is negative; VD >> Vγ , the threshold voltage, say VD < − 0.1 V , then

50

Electronic Devices and Circuits

When, VD is more negative than –0.1 V, then VR

VD

Ge

ID

  −0.1 I D = I S  e 0.026 − 1 = I S ( 0.02 − 1) = −0.98 I S  

VBV2

Si

VBV1 Vγ1

0

e V → 0 ; therefore, T

Vγ2

VD

(2.23)

I D = −I S

From Eqn. (2.23), it can be noted that the reverse current in a diode is constant and is IS.

Si

IR

Ge

Figure 2.5 V-I characteristic of a diode.

Breakdown Region When the reverse-bias voltage is equal to the specified voltage called the breakdown voltage, VBV say 100 V, then the reverse current in the diode increases rapidly. In normal applications, a diode is never used in the breakdown region. However, it can be noted from Figure 2.5, when breakdown occurs, that the voltage across the diode terminals remains almost constant. Hence, when operated under this condition the diode is used as a constant voltage source. However, care must be taken to ensure that the power dissipation in the device is not more than the rated dissipation for the device.

Temperature Dependence of the V-I Characteristics Temperature has significant effect on the diode characteristics. VT and IS are temperature dependent. Increase in temperature results in increased thermal activity and decreased diode resistance, which influences both the forward and the reverse operation of the diode. Figure 2.6 shows the effect of temperature on the diode characteristics. 50°C 25°C

IF

Reverse breakdown voltage increases with increase in temperature VBV VR

IF2

Forward current increases with increase in temperature for the same voltage

IF1 0

VF1

VF

Forward voltage decreases with increase in temperature

50°C 25°C

IR Reverse current increases with increase in temperature

Figure 2.6 Effect of temperature on the diode characteristics

Diodes, Characteristics, and Applications

51

As temperature increases, IF increases at a specified forward voltage. From Figure 2.6, it can be noted that at VF1, IF at 25°C is IF1 and at 50°C is IF2 and IF2 > IF1. The diode forward voltage decreases by 2.5 mV per a degree rise in temperature ( in Celsius). The reverse saturation current and the breakdown voltage increase with increase in temperature. The reverse saturation current IS increases by 7.2 percent by a degree rise in junction temperature (in Celsius) and gets doubled for every 10°C rise in temperature (Fig. 2.7.) VR

27°C

0

IS

37°C 2IS IR

Figure 2.7 Effect of temperature on the reverse characteristic of the diode

The temperature dependence of the reverse saturation current is expressed as −Vg m hVT

I S = KT e

(2.24)

where, K is a constant independent of temperature, h is 1 for Ge and 2 for Si. m is 2 for Ge and 1.5 for Si. Vg, the forbidden gap is 0.785 eV for Ge and 1.21eV for Si. Example 2.4 Using the diode equation, find the forward current in a Si junction diode at a forward voltage of 0.6 V and temperature of 27°C, if the reverse saturation current is 0.1 mA.  V  h Solution: I D = I S  e V − 1   D

T

For Si, h = 2. Given VD = 0.6 V and IS = 0.1 mA VT = kT = 8.62 ´10 -5 T V At 27°C, VT = kT = 8.62 ´10 -5 ( 27 + 273) = 0.026 V VT can also be calculated as follows: VT = kT = At 27°C, VT =

300 = 0.026 V 11, 600

T T T = = 1 1 11, 600 k 8.62 ×10 −5

  0.6 I D = 0.1 × 10 −6  e 2 × 0.026 − 1 = 10.27 mA  

52

Electronic Devices and Circuits

Example 2.5 Find the factor by which the reverse saturation current of Ge and Si diodes increases when the temperature increases from 27°C to 77°C. −Vg m hVT

Solution: I S = KT e

(i) For Ge, m = 2,

h = 1 T = 27 + 273 = 300 K and Vg = 0.785 V

VT = 0.026 V −0.785

∴I S1 = K (300 )2 e 1× 0.026 −0.785

e 1× 0.026 = 0.775 × 10 −13

IS1 = 69750 × 10−13 K

(2.25)

At T = 77 + 273 = 350 K VT =

T 350 = = 0.03 V 11, 600 11, 600 -0.785

I S2 = K (350 )2 e 1´0.03 = 52675 ´ 10 -11 K I S2 52675 × 10 −11 = = 75.5 I S1 69750 × 10 −13

Or

(2.26)

I S2 = 75.5I S1

(2.27)

(ii) For Si, m = 1.5, h = 2 T = 27 + 273 = 300 K and Vg =1.21 V VT = 0.026 V −1.21

∴I S1 = K (300 )1.5 e 2×0.026 −1.21

e 2× 0.026 = 0.78 × 10 −10

IS1 = 4053 × 10−10 K

(2.28)

At T = 77 + 273 = 350 K VT =

350 T = = 0.03 V 11, 600 11, 600 −1.21

I S2 = K (350 )1.5 e 2 × 0.03 = 11394 × 10 −9 K

(2.29)

Diodes, Characteristics, and Applications

I S2 11394 × 10 −9 = = 28.11 I S1 4053 × 10 −10

Or

IS2 = 28.11 IS1

53

(2.30)

From Eqs (2.27) and (2.30), it can be noted that variation of IS with temperature is small in Si when compared with Ge. Example 2.6 A Si diode has reverse saturation current of 0.1 µA at 27°C. Find its reverse saturation current at (a) 37° C and (b) 127° C. Solution: The temperature dependence of IS is also given by the relation  T2 − T1   10 

(2.31) I S2 = I S1 2 where, IS2 is the leakage current at temperature T2 and IS1 is the leakage current at temperature T1, usually 27°C. (a) T1 = 27 + 273 = 300 K and T2 = 37 + 273 = 310 K I S2 = I S1 2

 T2 −T1   10 

 310 − 300    10 

= 0.1 × 2 

= 0.2 µA.

This means that the leakage current gets doubled for every 10°C rise in temperature. (b) T1 = 27 + 273 = 300 K and T2 = 127 + 273 = 400 K æ T2 -T1 ö ç ÷ 10 ø

I S2 = I S1 2è

2.2

æ 400 -300 ö ç ÷ 10 ø

= 0.1 ´ 2 è

= 102.4 mA.

ANALYSIS OF THE DIODE CIRCUIT

Consider a practical diode circuit shown in Figure 2.8. + VD −

ID

+ V

RL

VL −

Figure 2.8 Practical diode circuit

The diode is a non-linear component, and therefore the methods of circuit analysis cannot be used. Hence, the analysis of a diode circuit basically involves two methods: (i) numerical and (ii) graphical.

2.2.1 Numerical Method From Figure 2.8, . But, I D = I S  hV  e − 1 VD

T

V = VD + IDRL

(2.32)

54

Electronic Devices and Circuits

Substituting this value in Eqn. (2.32),  V  V = VD + I S  e hV − 1 RL   D

(2.33)

T

Equation (2.33) can only be solved numerically. But an alternate simple procedure would be the graphical method.

2.2.2 Graphical Method From Eqn. (2.32), ID =

V VD − RL RL

(2.34)

From Figure 2.9, VD is the variable on the x-axis and ID is the variable on the y-axis. Equation (2.34) is in the form of y = mx + C and is the equation of the straight line and is called the load line. In order to draw the straight line, at least two points are required. To locate these two points, the following conditions are imposed on Eqn. (2.34): V Set, VD = 0, then I D = (point Y on the y-axis) RL Set, ID = 0, then VD = V (point X on the x-axis) The line joining these two points, X and Y, is the dc load line. Similarly, Eqn. (2.19) gives the V-I characteristic of the diode as shown in Figure 2.9. ID will have to satisfy both Eqs (2.19) and (2.34). The intersection of the diode curve and the load line will give the value of ID for a given VD (Figure 2.9) and is called the quiescent point or the operating point. iD Y

V RL

Load line ID

Q

X 0

VD

V

vD

Figure 2.9 Graphical method of analysis

In the analysis of diode circuits, sometimes certain approximations are made to arrive at simple solutions. First, let us assume that the diode is ideal, that is, the forward resistance of the diode is zero and the diode conducts for VD = 0 and the diode current is ideally infinity. For a reverse voltage, the diode current is ideally zero. This means that that the diode behaves as a closed switch when forward biased and as an open switch when reverse biased (Figure 2.10).

Diodes, Characteristics, and Applications

55

Forward bias ID

A

K Closed switch

VR

VD

0

Reverse bias K

A

Ideal diode

Open switch

Figure 2.10 Ideal diode characteristic and equivalent circuit

A diode, however, has a barrier potential or cut-in voltage, Vg . Unless the forward-bias voltage is equal to Vg , there can be no current in the device; and at Vg , the current abruptly becomes infinity, assuming an ideal diode. The diode is now represented as a closed switch in series with a battery of value, Vg ( Figure 2.11). Forward bias ID

A

K Vγ

Closed switch 0

VR

Vγ

VD

Reverse bias K

A

Ideal diode with Vγ

Open switch

Figure 2.11 Ideal diode with barrier potential and the equivalent circuit

However, a practical diode has a finite forward resistance and the diode characteristic, and its equivalent circuit are shown in Figure 2.12. Forward bias ID

RF

A

K Vγ

Closed switch VR

0

Vγ

VD

Idealized diode

Reverse bias K

A Open switch

Figure 2.12 Practical diode idealized characteristic and equivalent circuit

From Figure 2.9, RF = VD is the dc resistance or the static resistance of the diode. ID However, in certain applications, a small sinusoidal signal may be overriding on the steady

56

Electronic Devices and Circuits

dc component (Figure 2.13). In such applications, there is a range (not necessarily linear) over which the diode voltage varies, and correspondingly there exists a range over which the diode current varies. The ratio of the incremental change in the diode voltage to the incremental change the diode current is an ac resistance and is called the dynamic resistance of the diode (Figure 2.13). id

ID

id

id

+

Q

ID

vd

∆ID

RL −

VD vD

0

VD vd

∆VD

Figure 2.13 Diode circuit with a sinusoidal signal overriding a dc signal

rd = rac =

∆VD around the operating point. ∆I D

Bulk Resistance of the Diode The P- and N-regions offer finite resistances Rp and Rn, and the sum of these resistances is called the bulk resistance, RB = Rp + Rn, which is typically of the order of 5 Ω and essentially depends on the doping, the dimensions of the P-type and N-type materials, and the operating temperature.

Dynamic Resistance or ac Resistance The dynamic resistance rd of the forward-biased junction depends on the forward current, I, which rapidly increases with the increasing bias voltage. From Eqn.( 2.19),

 hVV  I = IS  e − 1   T

V

dI 1 V ISe h = dV hVT

T

V

1 1 V ISe h = rac hVT

T

Or

rac = rd =

hVT ISe

rac is the dynamic resistance.

V hVT

(2.35)

Diodes, Characteristics, and Applications

57

But, from Eqn. (2.19), V VT

I + IS = IS eh

(2.36)

Substituting Eqn. (2.36) in Eqn. (2.35), rac = rd =

hVT hVT ≈ I + IS I

(2.37)

since, I >> IS. Example 2.7 A Ge diode has a reverse saturation current of 25 μA at 100°C. Find its dynamic resistance for a bias voltage of 0.2 V (i) in the forward direction and (ii) in the reverse direction. Solution: T = 100°C = 100 + 273 = 373 K IS = 25 × 10−6 A VT =

T 373 = = 32 mV 11, 600 11, 600

(i) When V = 0.2 V -V

From Eqn. (2.35), racf =

-0.2 VT V 0.032 0.032 ´ =1280 ´1.93 ´10 -3 = 2.47 W e = e IS 25 ´10 -6 T

(ii) When V = –0.2 V, -V

racr =

0.2 VT V 0.032 0.032 ´ =1280 ´ 518 = 0.663 MW e = e IS 25 ´10 -6 T

Example 2.8 At 27°C, the diode current is 0.5 mA at 0.45 V and 25 mA at 0.65 V. Determine h. Solution: T = 27 + 273 = 300 K and VT =

300 T = = 0.026 V 11, 600 11, 600

V  hVV  hV I = IS  e − 1 = I S e   T

T

(i) When I = 0.5 × 10−3 A, V = 0.45 V 0.45

∴0.5 ×10 −3 = I S e 0.026h = I S e

17.31 h

(2.38)

(ii) When I = 25 × 10–3 A, V = 0.65 V −3

∴25 × 10 = I S e

25 h

(2.39)

58

Electronic Devices and Circuits

Dividing Eqn. (2.39) by Eqn. (2.38), e

50 =

25 h

17.31

=e

7.69 h

eh 7.69 = ln(50)=3.91 h ∴h =

2.3

7.69 =1.97 3.91

JUNCTION CAPACITANCES

The capacitive effects in a diode limit its application at high frequencies. Basically, a PN junction diode offers two types of capacitive effects: one when reverse biased and the other when forward biased. When forward biased, the diode offers a capacitance called the diffusion capacitance or storage capacitance, CD; and when reverse biased, the capacitance offered by it is called the transition capacitance or space charge capacitance or depletion region capacitance, CT .CD >> CT.

2.3.1 Diffusion or Storage Capacitance, C D The capacitance offered by the junction diode when forward biased is the diffusion capacitance, CD. Forward bias reduces the barrier potential, and holes from the P-side are injected into the N-side and electrons from the N-side are injected into the P-side. There will be a large concentration of holes on the N-side of the junction and the concentration of holes decreases exponentially on the N-side as we move away from the junction. This may be understood like this—a positive charge is injected from the P-side into the N-side. In addition, the injected charge Q is proportional to the forward-bias voltage, V. The rate of change of Q with V is the diffusion capacitance. CD =

dQ dV

(2.40)

When the diode is operated under forward bias, additional charge is stored near the edges of the space charge region. The amount of charge Q stored in the diode is proportional to the diode current I. Q = It (2.41) where t is the mean lifetime of the charge carriers, and I is the diode current. From Eqn. (2.19), V  hVVT  hV I = IS  e − 1 ≈ I S e  

T

Substituting in Eqn. (2.41), V VT

Q = tI S e h

(2.42)

Diodes, Characteristics, and Applications

59

From Eqs (2.40) and (2.42), CD =

V V  dQ d  t V hV IS e h = t I S e  = dV dV  V h  T  T

T

(2.43)

Also from Eqn (2.19), I + IS = ISe

V hVT

(2.44)

Substituting Eqn. (2.44) in Eqn. (2.43), V

CD =

tI S hV t ( I + I S ) e = hVT hVT T

(2.45)

As I >> IS, when forward biased, Eqn. (2.45) can be written as follows: CD =

t ( I + IS ) t I ≈ hVT hVT

(2.46)

Equation (2.46) tells that CD is proportional to I.

Transition Capacitance, C T In a reverse-biased diode, the width of the depletion region

depends on the applied reverse-bias voltage. If the P- and N-regions, which offer low resistances, are considered as parallel plates and the depletion region that behaves as an insulator as the dielectric, then the reverse-biased PN diode can be seen as a parallel plate capacitor. The capacitance offered by the diode when reverse biased is called the transition capacitance or the depletion layer capacitance or the space charge capacitance, CT (Figure 2.14). W is the width of the depletion region for the applied reverse-bias voltage, V.

Transition capacitance, CT =

Rate of changeof charge at the junction dQ = . dV Rate of changeof the applied reverse-bias voltage

PN junctions are of two types: (i) step-graded junction and (ii) linearly graded junction.

Calculation of C T for a Step-Graded Junction (Alloy Junction) A step-graded junction

is one in which there is an abrupt change in acceptor ion concentration on the P-side to the donor ion concentration on the N-side. The acceptor density NA and the donor density ND can be unequal. Let NA > ND (Figure 2.15). As NA >> ND, the depletion region penetrates more into the N-side than into the P-side. Then W = WN + WP ≈ WN (2.47) where, W = width of the depletion region WN = width of the depletion region on the N-side and WP = width of the depletion region on the P-side Poisson’s equation gives the relation between the charge density and the potential as follows: d 2V qN D = e dx 2

(2.48)

60

Electronic Devices and Circuits Parallel plates W

P + + + + + + + + +

N − − − − − − − − −

Dielectric

V

Figure 2.14 Transition capacitance, CT

where, q = the charge of an electron x = the distance from the junction e = the permittivity of the semiconductor = e0 er e0 = the permittivity of free space = 8.85 × 10−12 F/m er = the relative permittivity of the semiconductor and is 16 for Ge and 12 for Si. Integrating Eqn. (2.48) with respect to x and assuming that the constant of integration is zero, qN d 2V ∫ dx2 dx = ∫ e D dV qN D = x dx e

(2.49)

dV is the electric field intensity E in the depletion region. dx Therefore, from Eqn. (2.49), E=

qN D x e

(2.50)

Integrating Eqn. (2.49) gives the potential V: dV

∫ dx dx = ∫

W

0

V= From Figure 2.15(d), at x = W, V = VB,

qN D xdx e

qN D W 2 × e 2

(2.51)

Diodes, Characteristics, and Applications

61

Therefore, VB =

qN D W 2 × 2 e

∴W 2 =

(2.52)

2e ×VB qN D 1

W ∝VB2

Or

(2.53)

V

P

(a)

N W WP

Charge density, r

0

ND x (b) WN

NA 0

Electric field E intensity

x (c)

VB 0

Potential, V

x (d)

Figure 2.15 Variation of ρ, E, and V as a function of distance x from the junction

From Eqn. (2.53), it is evident that the width of the depletion region W increases with the increasing reverse-bias voltage. The total charge density of the N-type material is Q = qND × Volume = qND AW

(2.54)

From Eqn. (2.54), CT =

dQ dW = qN D A dV dV

(2.55)

Differentiating Eqn. (2.51) with respect to V 1=

qN D 2W dW e 2 dV

Or

dW e = dV qN DW

(2.56)

62

Electronic Devices and Circuits

Substituting Eqn. (2.56) in Eqn. (2.55) CT =

dQ dW qN D Ae eA = qN D A = = dV dV qN DW W

(2.57)

Equation (2.57) can be seen as the expression for the capacitance of a parallel plate capacitor, and CT is inversely proportional to the width of the depletion region, W.

Linearly Graded Junction (Grown or Diffused Junction) In a linearly graded junction, the charge density varies linearly with distance in the depletion region (Figure 2.16). CT is given by 1

1

−W/2

Charge density, r

Eqn. (2.57). But W varies as VB 3 , but not as VB 2 as in the case of an abrupt junction.

0

+W/2

Figure 2.16 Variation of charge density with distance

Example 2.9 In an abrupt Si PN junction, ND = 1023 atoms/m3, and NA = 0.5 × 1022 atoms/m3. Calculate the width of the junction when (i) no external voltage is applied, that is, VB = 0.7 V and (ii) when the applied reverse-bias voltage is −5 V. Solution: In general, W =

2eVB q

 1 1  +    NA ND 

e = e0er = 12 × 8.85 × 10−12 F/m = 1.062 × 10−10 F/m q = 1.602 × 10−19 C (i) VB = 0.7 V, W=

2 × 1.062 ×10 −10 × 0.7  1 1  + 23  = 0.432 ×10 −6 m  22 1.602 ×10 −19 0 . 5 10 10 ×  

(ii) When VR = – 5 V .VB =Vo − ( −VR ) = Vo +VR = 0.7 + 5 = 5.7 V

W=

2 ×1.062 ×10 −10 × 5.7  1 1  −6  0.5 ×1022 + 1023  = 1.26 ×10 m 1.602 ×10 −19  

Diodes, Characteristics, and Applications

63

Example 2.10 In a Si junction diode, NA >> ND, the resistivity on the N-side is 4 Ω−cm and the contact potential is 0.5 V. A reverse bias of 10 V is applied to the junction. Assume circular junction with diameter 1 mm. μe = 500 cm2/V-s Calculate, CT . Solution: For silicon, e = e0er = 12 × 8.85 × 10−12 F/m = 1.062 × 10−10 F/m q = 1.602 × 10−19 C Given re = 4 Ω–cm = 4 × 10−2 Ω–m, me = 500 cm 2 / V − s = 500 × 10 −4 m 2 / V − s 1 1 −1 = = 25 (Ω − m ) re 4 × 10 −2

se =

s e = qN D me

∴ qN D =

se 25 = = 500 me 500 × 10 −4

Given, V0 = 0.5 V and VR = −10 V ∴VB =V0 − ( −VR ) =V0 + VR = 0.5 + 10 = 10.5 V From Eqn. (2.52), VB =

qN DW 2 2e

W2 =

2eVB 2 × 1.062 × 10 −10 × 10.5 = = 4.46 × 10 −12 qN D 500

W = 2.11×10 −6 m

(

−3 pd 2 p 1×10 A= = 4 4

CT =

2

)

= 0.785 ×10 −6 m 2

e A 1.062 ´10 -10 ´ 0.785 ´10 -6 = = 39.51pF W 2.11´10 -6

Switching Times in a Diode Consider the diode circuit to which a signal is applied as shown in Figure 2.17. During the interval 0 to t1, the input is VF , the diode is forward biased and the diode current is I F . Suddenly, at t  = t1, the diode is reverse biased by a voltage VR and as such the diode current is expected to become zero ideally.  However, this does not happen because of the fact  that when the diode is forward biased, there are a

+

VF t1

Vi

0 VR

RL

−

Figure 2.17 Diode circuit with input

64

Electronic Devices and Circuits

large  number of stored charges on either side of the junction, which ensure large reverse current even under reverse-biased condition. The time for which the reverse current is large is called the storage time, tS , that is, (t2 − t1 ) . The reverse current eventually falls to zero when all the stored charges are cleaned up. The time interval from t2 to t3 is called the transition time, tt (Figure 2.18). Thus, it is evident that when a forward-biased diode is suddenly reverse biased, the diode will not switch into the OFF state unless a minimum time interval (tS + tt ) elapses, and this total time interval is called the reverse recovery time of the diode, trr .

VF

Vi 0

t1 VR

IF

Reverse recovery time, trr t1

t2

t3

0 Storage time, ts IR

Transition time, tt

Figure 2.18 Switching times of a junction diode

2.4

SOME IMPORTANT DIODE PARAMETERS

Diodes can be broadly classified as follows: (a) signal diodes and (b) power diodes. Signal diodes are mainly used under small signal conditions, that is, in low-current and low-power applications. These are better used in switching circuits and for high-frequency applications. Power diodes are used in high-current and high-power applications such as rectifiers. Whenever a diode is used for a specific application, the following diode parameters will have to be borne in mind: (i) Maximum forward current: The maximum forward current I F( max ) is the maximum current allowed to flow through the diode when forward biased. When I > I F( max ) , then more power is dissipated at the junction resulting in more heat at the junction. The diode will fail due to thermal overload. As an example, for a signal diode 1N4148, I F( max ) is 150 mA and power dissipation is 500 mW at 25oC. (ii) Peak inverse voltage (PIV) or peak reverse voltage (PRV): Peak inverse voltage is the maximum reverse-bias voltage that can be applied to the diode so as to ensure that no

Diodes, Characteristics, and Applications

65

reverse breakdown occurs. This specification is important in applications such as rectifiers and the diode should be properly chosen. (iii) Maximum power dissipation: Maximum power dissipation, PD( max ) , is the maximum allowable power dissipation in device when forward biased. (iv) Maximum operating temperature: The maximum operating temperature actually refers to the junction temperature (TJ) of the diode and is related to the maximum power dissipation. Usually, the operating temperature range of the diode is mentioned.

2.5

BREAKDOWN DIODES

The V-I characteristic of certain diodes is such that when forward biased, these diodes exhibit the same characteristic as that of an ordinary PN junction diode; but when reverse biased, the voltage across the diode terminals remains almost constant, but the current in the diode suddenly becomes large (the device conducts heavily at a voltage called the breakdown voltage). Such diodes can be used as reference elements or simple voltage regulators. A voltage regulator is one that maintains the output voltage constant irrespective of the variations in the input voltage or variations in the load current. We consider two breakdown diodes, namely Zener and avalanche diodes.

2.5.1 Zener Diode A Zener diode is a heavily doped diode, with an anode A and cathode K as shown in Figure 2.19, with its V-I characteristic represented in Figure 2.20. Zener breakdown occurs due to the physical rupturing of the covalent bonds due to the applied reversebias voltage, and the current abruptly rises to a large value at a voltage VZ, called the Zener breakdown voltage. To limit the current to a safe value of IZ(max), there is need to provide a series limiting resistor. The Zener diode conducts when the current is IZ(min). The power dissipation capability of the Zener diode is PD(max) = VZ IZ(max), which is normally specified at 25°C. However, at elevated temperatures, the power dissipation capability of the Zener diode decreases as the Zener diode exhibits negative temperature coefficient, a Z As a result, VZ decreases with increase in temperature. If a Z = −0.06%/°C and VZ = 3.6 V at 25°C, then VZ at 100°C is given as follows:

K

A

Figure 2.19 Zener diode

IF

VR

VZ

0 Vg IZ(min)

VF

IZ(max) IR

VZ (at 100° C) = VZ + ∆VZ where ∆VZ = VZ a Z (T − 25)

(2.58)

Figure 2.20 V-I Characteristic of Zener diode

66

Electronic Devices and Circuits

 −0.06  × 75 = − 0.162 V ∴ ∆VZ = 3.6 ×   100  VZ (at 100°C) = 3.6 − 0.162 = 3.438 V. Zener diodes normally operate below 6 V. As a reverse-biased Zener diode conducts heavily at VZ, its approximate equivalent circuit can be simply a battery with terminal voltage VZ, Figure 2.21(a). However,VZ may vary by ∆VZ , when I Z varies from I Z ( min ) to I Z ( max ) ( = ∆I Z ) . Thus, a Zener has a dynamic resistance, rZ , given as follows: rZ =

∆VZ ∆I Z

(2.59)

Hence, the exact equivalent circuit of the Zener diode may be represented as a battery, VZ , with internal resistance, rZ (Figure 2.21(b)). A

K

rz

K

VZ

A

VZ

(a) Approximate equivalent circuit

(b) Exact equivalent circuit

Figure 2.21 Equivalent circuits of a Zener diode

2.5.2 Avalanche Diode An avalanche diode too has a similar V-I characteristic as a Zener diode, but the device conducts heavily, when reverse biased, at larger voltages. When reverse biased, the minority charge carriers in the P and N materials acquire large kinetic energy, aided by the external voltage. When a charge carrier collides with an atom, it may knock off an electron, which in turn can acquire large energy, and may in turn knock off another electron from a different atom. This results in a large number of charge carriers, due to the process called avalanche multiplication. Hence, there results a large current. This diode is called an avalanche diode. This phenomenon occurs at large reverse-bias voltages. But both avalanche and Zener diodes are generally called as Zener diodes, though the principle of operation is different. An avalanche diode has a positive temperature coefficient, that is, VZ increases with temperature. If a Z = 0.06%/°C and VZ = 10 V at 25°C, then VZ at 100°C is given as follows: VZ (at 100°C) = VZ + ∆VZ where ∆VZ = VZ a Z (T − 25)  0.06  ∴ ∆VZ = 10 ×  × 75 = 0.45 V  100 

(2.60)

67

Diodes, Characteristics, and Applications

VZ (at 100°C) = 10 + 0.45 = 10.45 V Zener and avalanche diodes are used as voltage reference elements because once breakdown occurs, the voltage across the diode remains almost constant.

2.6

CLIPPING CIRCUITS

A device or a circuit may be destroyed when a signal of large amplitude (positive or negative) is applied to it. Therefore, it becomes necessary to protect the device or a circuit. A clipping circuit is used in such applications. A clipper eliminates a portion or portions of the input signal. Clipping circuits are classified into (i) one-level and (ii) two-level clippers.

2.6.1 One-Level Clippers One-level clippers clip the input signal at only one voltage level. One-level clippers can be (i) series clippers and (ii) shunt clippers. Further, these can be biased or unbiased circuits.

Series Clippers In a series clipper, the clipping element, a diode, is connected in series with the output. The input–output waveforms are obtained based on the assumption that the diode is ideal. (i) Negative clipper: Figure 2.22(a) shows a series negative clipper, and Figure 2.22(b) shows its transfer characteristic from which the input–output relation is obtained. When Vi ≥ 0, D is forward biased and is ON. Its equivalent circuit is a closed switch. Hence, Vo =Vi . When Vi < 0, D is reverse biased and is OFF. Its equivalent circuit is an open switch. Hence, Vo = 0. The relation between Vi and Vo is called the transfer characteristic.

Vo

D π 0

π/2

t Vi −

Slope = 1

+

+ R

Vo

Vo 0

t

0

π/2

π t

− Vi 0 π/2 π t

(a) Circuit

(b) Transfer curve and waveforms

Figure 2.22 Negative-peak clipper

(ii) Positive clipper: If the polarity of the diode is reversed, then the circuit of Figure 2.22 becomes a positive-peak clipper (Figure 2.23). When Vi > 0, D is reverse biased and is OFF. Hence, Vo = 0. When Vi ≤ 0, D is forward biased and is ON. Vo =Vi .

68

Electronic Devices and Circuits

Vo

D + 2π 0

R

t Vi −

π

Slope = 1

+ Vo

π

Vo

2π

0

0

t

2π t

Vi 0 π

−

π 0

2π t (b) Transfer curve and waveforms

(a) Circuit

Figure 2.23 Positive clipper

(iii) Biased series clippers: The circuits in Figures 2.22 and 2.23 completely eliminate one half cycle of the input signal and are used as half-wave rectifiers. However, if only a small portion of the input signal is to be removed, then biased clippers are used. (iv) Positive-base clipper: Consider the circuit and the transfer characteristic in Figure 2.24. Vo

D

0

π

+ 2π t Vi −

Slope = 1 + R VR

VR

Vo

Vo 0

VR

VR

− Vi π 2π t

Figure 2.24 Positive-base clipper

When Vi < VR , D is OFF. Therefore, Vo =VR . When Vi ≥ VR , D is ON. Therefore, Vo =Vi . The circuit clips the output during the positive half cycle below the reference voltage, VR (v) Negative-peak clipper: Consider the circuit and the transfer characteristic in Figure 2.25. When Vi < − VR , D is OFF. Therefore, Vo = − VR When Vi ≥ − VR , D is ON. Therefore, Vo =Vi . The circuit is a negative-peak clipper that clips the negative peak at −VR . (vi) Positive-peak clipper: Consider the circuit and the transfer characteristic in Figure 2.26. When Vi < VR , D is ON. Therefore, Vo =Vi . When Vi ≥ VR , D is OFF. Therefore, Vo =VR The circuit is a positive-peak clipper that clips the positive peak at VR.

Diodes, Characteristics, and Applications

Vo

D +

+

R π t Vi

0 π/2

Vo

Vo

−VR

π

0 VR

−VR

−VR

−

−

2π

0

Vi 0 π 2π

t

Figure 2.25 Negative-peak clipper

(vii) Negative-base clipper: Consider the circuit and the transfer characteristic in Figure 2.27. When Vi < − VR , D is ON. Therefore, Vo =Vi When Vi ≥ − VR , D is OFF. Therefore, Vo = − VR The circuit is a negative-base clipper that clips at −VR . Vo

D +

+

VR

VR Vo

R π 0

Vo

t Vi

π/2

0

π

2π

t

0

VR

VR Vi

−

− 0 π

2π

t

Figure 2.26 Positive-peak clipper.

Vo

D +

+

π

Vo

t Vi

0 π/2 −

Vo

−VR

R

0

π

2π

0 −VR

VR

−VR − Vi 0 π 2π

Figure 2.27 Negative-base clipper

69

70

Electronic Devices and Circuits

Shunt Clippers A shunt clipper or a parallel clipper is one in which the diode is connected in shunt with the output. (i) Positive clipper: Consider the circuit in Figure 2.28. When Vi ≥ 0, D is ON. Therefore, Vo = 0. When Vi < 0, D is OFF. Therefore, Vo =Vi The circuit is a positive clipper that clips the positive peak at 0. Vo

R +

+

Vo 0

π

Vo

D

t Vi

0

2π

π

0

t

π

π/2

t

0 π/2 −

− Vi 0 π 2π

t

Figure 2.28 Shunt positive clipper

(ii) Negative clipper: Consider the circuit in Figure 2.29. When Vi ≥ 0, D is OFF. Therefore, Vo =Vi When Vi ≤ 0, D is ON. Therefore, Vo = 0. The circuit is a negative clipper that clips the negative peak at 0. Vo

R + + Vo

π

t Vi

0

D

0

π

π/2 −

0

Vo

0 π/2 −

t

Vi 0 π 2π

t

Figure 2.29 Shunt negative clipper

2π π

t

Diodes, Characteristics, and Applications

71

It is possible to clip the input at different levels using biased shunt clippers, and the circuits and the waveforms are shown in Figure 2.30. Vo

Vo

R

VR

VR

+ +

2π t

π

Vo

D

t Vi

0 π/2

0

VR

π

Vi 0

VR

0

−

−

π 2π

t

(a) Positive-peak clipper

Vo

R + +

0

−VR

D

π

t Vi

0 π/2

Vo

Vo

2π

π

0 −VR

VR −

−

Vi

0 π 2π

(b) Negative-base clipper

Vo

R + +

π

t Vi

0 π/2 −

Vo VR

D

VR

Vo 0

VR

VR

− Vi

0 π

2π

t

(c) Positive-base clipper

0

π

t

72

Electronic Devices and Circuits

Vo

R +

Vo

+

−VR

D

π t Vi

0 π/2

0

t

0 VR

VR

−

2π

π

Vo

− Vi

0 π

2π

t

(d) Negative-peak clipper

Figure 2.30 Circuits and waveforms of biased shunt clippers

2.6.2 Two-Level Clippers An input signal can be clipped at two different levels so as to get an ouput of the desired nature.

Limiter The positive and negative peaks of the input signal may be clipped either at different levels or at the same level. If the clipping levles are the same, then the circuit is called a limiter. The circuit, the transfer characteristic, and the waveforms of a limiter are shown in Figure 2.31. D1 and VR form the positive-peak clipper and D2 and −VR form the negative-peak clipper. Thus, a cascaded combination of a positive-peak clipper and a negative-peak clipper operates as a limiter. When Vi < − VR , D2 is ON and D1 is OFF Vo = − VR. When Vi > VR, D1 is ON and D2 is OFF.Vo = VR. When −VR < Vi < VR, D1 is OFF and D2 is OFF Vo = Vi . VR Vo

−V

R

VR Vo

−VR 0

+ +

VR

D1 π VR

VR − π 2π

t

Figure 2.31 Limiter

0

−VR

0

−

VR Vi

π/2

Vo

D2

t Vi

0

V

2π π

t

73

Diodes, Characteristics, and Applications

Positive Slicer If only a portion of the positive half cycle of the input signal that lies between two voltage levels, VR1 and VR2 , is to be available at the output, then the circuit that delivers this output is called a positive slicer (Figure 2.32). Obviously, it is a cascaded configuration of a positive-base clipper and a positive-peak clipper (Figure 2.32). When Vi VR2 , D1 is OFF and D2 is ON Vo =VR2 . When VR1 VR1 2π

t

Figure 2.32 Positive slicer

Example 2.11 Design a negative slicer to slice a sinusoidal signal between the voltage levels −3 V and −5 V. The diode forward resistance is 10 Ω and the reverse resistance is 10 MΩ. Solution: R is usually chosen as R = Rf Rr = 0.01´103 ´10 ´106 = 10 kW The circuit is a cascaded configuration of a negative-base clipper and a negative-peak clipper, with VR1 = − 3 V and VR2 = − 5 V (Figure 2.33).

−VR2 −VR1

R

0

+

0

+

π 0

D1

D2

t Vi

π/2

–VR2

VR1

0

−

VR2 3V 5V − –VR2 < –VR1

–VR1

Vo

π 2π t

Figure 2.33 Negative slicer

π

2π

t

74

Electronic Devices and Circuits

Zener diodes can also be used in clipping circuits. A limiter using Zener diodes is shown in Figure 2.34. During positive half cycle of the input, D1 is forward biased and D2 is reverse biased, and hence Vo = (VD +VZ ) and during the negative half cycle of the input cycle D2 is forward biased and D1 is reverse biased, and hence Vo = − (VD +VZ ) . R

Vo (VD +VZ)

+

+

D1

Vi

D2 −

+ VD − + Vo VZ − −

– (VD + VZ)

0 (V +V ) D Z

Vi

– (VD +VZ)

Figure 2.34 Limiter using Zener diodes

Example 2.12 For the circuit shown in Figure 2.35, a sinusoidal input vi = 50 sinwt is applied as input. Plot the waveforms.

15 K

10 K

+

+ D1

D2

10 V

25 V

Vo

Vi

Solution: (i) When Vi 25 V, D1 is OFF and D2 is ON, Figure 2.36(b) Vo = 25 V 15 K

10 K

15 K

+

+ D1

+

D2 OFF

ON

Vo

Vi 10 V

−

D1 OFF

Vo 10 V

−

− (b)

15 K

+

10 K

D1 OFF

D2 OFF

+ Vo

Vi 10 V

−

25 V

−

(a)

+

+

D2 ON

Vi

25 V

−

10 K

25 V

−

− (c)

Figure 2.36 Equivalent circuits

75

Diodes, Characteristics, and Applications

(iii) When 10 V < Vi < 25 V , D1 and D2 are OFF, Figure 2.36(c) Vo =Vi .

vi 25 V Vo 10 V 0

Figure 2.37 shows the waveforms.

t

Figure 2.37 Waveforms

2.7

CLAMPING CIRCUITS

When a signal associated with a dc component is passed through a high pass RC circuit, the dc component is lost, as the capacitor blocks the dc. If the dc component is once again required to be introduced, then a clamping circuit is used. A clamping circuit reintroduces the dc component or restores the dc component. A clamping circuit is simply a dc-level shifter or dc restorer. It shifts the dc level of an input waveform to a desired level. Thus, clamping circuits can be positive clampers (that introduce a positive dc voltage) or negative clampers (that introduce a negative dc voltage) (see Figure 2.38). 0

0

−Vdc

t

t

Vdc

t

0 Output of Negative clamper

Input

Output of Positive clamper

Figure 2.38 Input and output of clamping circuits

2.7.1 Working of a Clamping Circuit p of the input, Vi , 2 with the polarity shown at

Consider the circuit in Figure 2.39 and its waveforms. During the period 0 to

D is ON and the output Vo = 0. The capacitor C gets charged to Vm p p . After , the input decreases and the voltage across D is (Vi − Vm ), which reverse biases D 2 2 and the diode is OFF. Vm π

Vi 0

C

+

−

+

+ Vi

Vm

2π

−V m Vo

D

t

π/2

π/2

0

−

−

Vo −Vm

π

t

2π

−2Vm

(a) Circuit

(b) Waveforms

Figure 2.39 Negative clamper

76

Electronic Devices and Circuits

Therefore, (2.61)

Vo = Vi − Vm At p,Vi = 0 ,Vo = 0 − Vm = − Vm . At

3p , Vi = − Vm ,Vo = − Vm − Vm = − 2Vm . 2

Thus, for a quarter cycle, the output is zero. However, after one cycle, the positive peaks are clamped to 0 V, indicating that a negative voltage is introduced by the clamping circuit. If for some reason or the other the input increases from Vm to Vm1, the diode once again conducts for a quarter cycle, and the positive peaks of the output are once again clamped to zero (Figure 2.40).

2.7.2 Practical Clamping Circuit However, if the input decreases, there is no way that the output can once again be clamped, because there is no path for the discharge of the condenser C. If an alternate path for the discharge of C is provided through, R when D is OFF, the charge on C discharges exponentially with a time constant RC. Again, when the voltage just becomes positive, D conducts and the positive peaks of the input will once again be clamped to zero after a few cycles (Figure 2.41). V m1 Vm Vi

0

C

−

+ + Vi

Vm

+ D

Vo 0

−

− Vo

−2Vm

−2Vm1

Figure 2.40 Output of the clamping circuit in Figure 2.39 when Vi increases

The circuit in Figure 2.42 is a positive clamper. The polarity of the diode is reversed, and the negative peaks of the input are clamped to 0 level.

77

Diodes, Characteristics, and Applications

2.7.3 Biased Clamping Circuits If the positive or negative peaks of an input signal are to be clamped to a reference voltage, VR, this dc voltage is introduced in the output circuit. The voltage level to which the peaks in the output are clamped depends on the polarity of the diode and the polarity of the reference voltage. To understand biased clamping, consider the following examples: Vm Vm2 Vi 0

t

C

+

− +

+ Vm

Vi

Vo

D

0

R

−

t

− Vo −2Vm2 −2Vm Discharge of C with τ = RC

Figure 2.41 Output of the clamping circuit when Vi decreases Vm π/2

Vi

t π

C −

+

+

+ Vi

2π

0

Vm

−Vm Vo

D

2Vm −

− Vo Vm

t

π 2π

0 π/2

(a) Circuit

(b) Waveforms

Figure 2.42 Positive clamper

Example 2.13 A symmetric square wave of 1 kHZ and having a peak amplitude of 10 V is applied to the clamping circuit shown in Figure 2.43. Compute and plot the waveforms. Solution: When the input swings to 10 V, D is ON and VA = 10 − 2 = 8 V with the polarity shown. Under steady state, Vo = Vi − VA = Vi − 8 When Vi =10 V, Vo = 10 − 8 = 2 V When Vi = −10 V, Vo = − 10 − 8 = − 18 V. However, the peak-to-peak swing remains as 20 V only.

78

Electronic Devices and Circuits C

+10 V

+ VA

+

D

0

R

Vi

Vo VR

−

−10 V

2V 0

+

−

2V −

−18 V 1 mS

1 mS

Figure 2.43 Clamping circuit for Example 2.13

Example 2.14 A symmetric square wave of 1 kHZ and having a peak amplitude of 10 V is applied to the clamping circuit shown in Figure 2.44. Compute and plot the waveforms. C

+10 V

+ VA

+

D

0

R

Vi

Vo VR

−

−10 V

0 −2 V

+

−

2V −

−22 V 1 mS

1 mS

Figure 2.44 Clamping circuit for Example 2.14

Solution: When the input swings to 10 V, D is ON and VA =10 − ( −2 ) =12 V with the polarity shown. Under steady state, Vo =Vi −VA =Vi − 12 V When Vi = 10 V, Vo = 10 − 12 = − 2 V When Vi = −10 V, Vo = −10 − 12 = − 22 V. Example 2.15 A symmetric square wave of 1 kHZ and having a peak amplitude of 10 V is applied to the clamping circuit shown in Figure 2.45. Compute and plot the waveforms. C

+10 V −

−

22 V

+

+ VA R

0

Vi

−10 V

+

D

VR

Vo 2V −

2V 0 1 mS

1 mS

Figure 2.45 Clamping circuit for Example 2.15

Diodes, Characteristics, and Applications

79

Solution: When the input swings to −10 V, D is ON and VA = −10 − 2 = − 12 V, with the polarity shown. Under steady state, Vo = Vi − VA = Vi − ( −12 ) V = (Vi + 12 ) V When Vi = −10 V, Vo = −10 + 12 = 2 V When Vi = 10 V, Vo = 10 + 12 = 22 V . Example 2.16 A symmetric square wave of 1 kHZ and having a peak amplitude of 10 V is applied to the clamping circuit shown in Figure 2.46. Compute and plot the waveforms. C

+10 V −

18 V

+

+

− VA

R

0

−10 V

Vi

D

+

VR

Vo 2V −

0 −2 V 1 mS

1 mS

Figure 2.46 Clamping circuit for Example 2.16

Solution: When the input swings to −10 V, D is ON and VA = −10 + 2 = − 8 V, with the polarity shown. Under steady state, Vo = Vi − VA = Vi − ( −8) V = (Vi +8) V When Vi = −10 V, Vo = −10 + 8 = − 2 V When Vi = 10 V, Vo = 10 + 8 = 18 V .

2.7.4 Clamping Circuit Theorem Clamping circuit theorem states that for any input, under steady-state condition, the ratio of the area under the output curve when the diode is forward biased, Af to the area of the output curve when the diode is R reverse biased, Ar is equal to the ratio f R Af Rf = Ar Rr

(2.62)

Af V1 0 T1

V V − V1

Ar

T2

Figure 2.47 Clamping circuit theorem-output waveform

Example 2.17 For the output shown in Figure 2.47, V = 40 V, T1 = 1000 µS and T2 = 10 µS Rf =10 Ω , and R =100 kΩ. Find V1 to which the output is clamped.

80

Electronic Devices and Circuits

Solution: Af =1000V1 and Ar =10 ( 40 −V1 ) 1000V1 10 = = 0.1 × 10 −3 10 ( 40 − V1 ) 100 × 103 1000V1 = ( 40 −V1 ) × 10 −3

V1 = 40 µV

2.8 TUNNEL DIODE In a PN junction diode, the width, W of the depletion region is given as follows: W≈

2eVB qN A

(2.63)

where q = charge of an electron = 1.6 ×10 −19 Coulombs N A = impurity concentration on the P-side, number of electrons/m3 e0 = permittivity of free space = 8.85 ×10 −12 F/m er = Relative permittivity of Ge is 16 and that of Si is 11.9 e = absolute permittivity of Si = e 0e r = 11.9 × 8.85 ×10 −12 = 10.53 × 10 −11 F / m VB = barrier potential = 0.5 V Let N A = 3 × 1018 / m 3 W=

2 ´10.53 ´10 -11 ´ 0.5 = 14.8 m 1.602 ´10 -19 ´ 3 ´1018

(1m = 10 -6 m)

Let the impurity concentration be increased to N A = 3 × 1022 / m 3 , then W=

2 ´10.53 ´10 -11 ´ 0.5 = 0.148m 1.602 ´10 -19 ´ 3 ´1022

The width of the depletion region decreases substantially with increase in impurity concentra1 tion. From Eqn. (2.63), it is seen that W a . That is, the width of the depletion region is NA inversely proportional to the square root of impurity concentration. Thus, we see that when the concentration of the impurity charge carriers is very high, the width of the depletion region becomes negligibly small. A tunnel diode, also known as the Esaki (inventor) diode is a two-terminal PN junction diode in which the doping is nearly 1000 times higher than that of an ordinary PN junction diode. With this huge amount of doping, the potential barrier becomes so thin that electrons can penetrate or punch through the junction with the velocity of light, even though they do not possess enough energy to overcome the potential barrier. This results in large forward current at a relatively low forward

Diodes, Characteristics, and Applications

81

voltage ≈ 0.1 V. The charge carriers that possess negligible energy punch through the barrier instead of surmounting it. This phenomenon is called tunneling and the diode, as a result, is called tunnel diode. The reverse breakdown voltage is also reduced to a very small value. But usually this diode is used in the forward-biased mode. The principle of working of the tunnel diode and its V-I characteristic are better explained with the help of the energy-level diagrams (ELDs). A large number of electrons exist between ECN and EFN in a heavily doped N-type semiconductor, and a large number of holes exist between E VP and EFP in a heavily doped P-type semiconductor. If now a PN junction is formed, the ELD of the junction under zero bias condition is shown in Figure 2.48. Under this condition, the Fermi levels of both electrons and holes are the same, that is EFN = EFP. As the energy associated with the electrons is not sufficient enough to cross the junction,there can be no current in the device. Space charge region P-side Conduction band

N - side

ECP EG Conduction band

EVP EFP

EFN Valence band

Holes

ECN

Electrons

EG Valence band

EVN

Figure 2.48 Heavily doped PN junction with zero bias

(i) Now let the junction be forward biased by a small voltage, say 0.1 V (for Si), then the barrier potential decreases by the same amount. Hence, N-side energy levels shift upwards with respect to those on the P-side (Figure 2.49). It can be seen that a fewer number of electrons exist on the N-side in the conduction band that has the same energy as holes in the valence band on the P-side. Therefore, electrons from the N-side can tunnel through the narrow junction to the P-side, giving rise to a small current. If, the forward-bias voltage is increased from 0.1 V to 0.3 V, this current increases with increasing forwardbias volatge (points O to A in Figure 2.55). P-side Conduction band

N - side Tunneling of electron (low)

ECP EG

Conduction band

EVP Holes

EFP

EFN Electrons

Valence band

ECN EG Valence band

EVN

Figure 2.49 Heavily doped PN junction with small forward bias (0.1 V)

82

Electronic Devices and Circuits

(ii) When the forward-bias volatge is 0.3 V (for Si), it is seen that E VP = EFN and ECN = EFP (Figure 2.50). Maximum tunneling occurs under this condition, and the forward current reaches a maximum value (point A in Figure 2.55). (iii) When the forward bias voltage is increased beyond 0.3 V, say from 0.3 V to 0.6 V, Figure 2.51, not many electrons can tunnel through, thereby the current starts reducing (points A to B in Figure 2.54) and at 0.6 V, this current is minimum (point B in Figure 2.55). (iv) When the forward-bias voltage is increased beyond 0.6 V, the electrons in the conduction band on the N-side cannot cross the junction to reach the holes in the valence band on the P-side, and consequently, the tunneling current is reduced to zero (Figure 2.52). However, as the forward-bias voltage is increased further, the electrons surmount the potential energy barrier to reach the P-side; and from now onward, the tunnel diode behaves as an ordinary semiconductor diode. The current increases with the applied voltage (Figure 2.55, beyond point B). (v) When the reverse-bias voltage is applied, the height of the barrier increases on the P-side and that on the N-side decreases (Figure 2.53). Some of the holes in valence band on the P-side have the same energy as the electrons in the conduction band on the N-side; these can tunnel through, resulting in a reverse current. As the magnitude of the reverse-bias voltage increases, this current abruptly rises to a large value as in a Zener diode. Figure 2.54 shows the current components in a tunnel diode. Figure 2.55 gives the net variation of I F for a variation in VF . Conduction band ECP

Tunneling of electrons (Maximum) EG

Conduction band

EVP Holes

EFP

EFN ECN

Valence band

Electrons

EG Valence band

EVN

Figure 2.50 Heavily doped PN junction for a forward bias of 0.3 V ECP Tunneling of electron (Low once again)

EFN EVP Holes

Electrons ECN

EFP

EVN

Figure 2.51 Heavily doped PN junction for a forward bias of 0.3–0.6 V

Diodes, Characteristics, and Applications

ECP

Electrons EFN

EVP

ECN

Holes EFP EVN

Figure 2.52 Heavily doped PN junction for a forward bias greater than 0.6 V

ECP

EVP

Holes tunneling to vacant sites

Holes EFP EFN Electrons ECN

EVN

Figure 2.53 ELD of a tunnel diode under reverse bias

Tunneling current IF(mA)

A

C Diode current B

VR(V)

O

IR

Figure 2.54 Tunnel diode current components

VF(V)

83

84

Electronic Devices and Circuits

Tunneling region

IF (mA)

Negative resistance region

A

IP

C

B

IV VR(V)

Diode region

O

0.3

0.6

VP

VV

0.9 V VF

IR

Figure 2.55 V-I characteristic of a tunnel diode (Si)

In the region A to B, the tunnel diode behaves as a neagtive resistance, that is with increase in voltage there is a decrease in current. The forward characteristic of the tunnel diode is similar to the characteristic of a unijunction transistor (UJT). A UJT and a tunnel diode, as such, can be used for generating oscillations. However, a tunnel diode is specifically used in microwave oscillators and other high-speed applications. The shematic representations of tunnel diode are shown in Figure 2.56, and its electrical equivalent circuit is shown in Figure 2.57.

A

A

K

K

Figure 2.56 Schematic representations of a tunnel diode RS

LS

A C

−R n

K

Figure 2.57 Electrical equivalent circuit of a tunnel diode

Example 2.18 Construct the piecewise linear characteristic of a tunnel diode and calculate its negative resistance. Given data: I P = I F = 1 mA, I V = 0.15 mA, VP = 75 mV, VV =350 mV, VF =500 mV. Solution: The V-I characteristic of the tunnel diode is plotted in Figure 2.58. At VF =VP = 75 mV, I F = I P =1 mA (point A) At VF =VV =350 mV, I F = I V = 0.15 mA (point B)

Diodes, Characteristics, and Applications

85

The diode curve varies as the OA curve. When the forward voltage increases from 10 mV to 75 (=65 mV) mV, the tunneling current increases from 0.15 mA to 1 mA, The V-I characteristic and the diode characteristic are identical. Hence, the voltage at point C is 500 − 65 = 435 mV at which the current is 0.15 mA. The current at voltage 500 mV is 1 mA (Point D). From Figure 2.58, the negative resistance is Rn = −

∆VF −(350 − 75 ) = − 323.5 Ω = ∆I F 1 − 0.15

A

IF(mA) 1.0 IP

0.7 ∆IF = 0.85 mA 0.5

0.3 0.15 O 0

IV

B

C

∆VF = 275 mV 10

75

200

350

VP

435

500

VF (mV)

VV

Figure 2.58 Forward characteristic of the tunnel diode

2.9 VARACTOR DIODE A varactor diode is also known as voltage variable capacitor diode, varicap, and as tuning diode. A varactor diode is a reverse-biased diode in which the junction capacitance or the transition capacitance, CT, varies as the width of the depletion region varies. Consider an unbiased PN junction diode (Figure 2.59). W is the width of the depletion region. If the diode is reverse biased, electrons and holes are drawn away from the junction, and therefore the width of the depletion region increases as the reverse-bias voltage increases (Figure 2.60). This can be considered as a parallel plate condenser, the junction having an area of cross-section as A (m2), spacing between plates as W (m) and permittivity of the dielectric (semiconductor) as e. While considering a reverse-biased diode, it has been shown that the transition capacitance CT is given as follows: CT =

eA W

(2.64)

CT ∝

1 W

(2.65)

86

Electronic Devices and Circuits Width of the depletion region W

P

Anode, A

− −

+ +

− −

+ +

− −

+ +

Acceptor ions

Cathode, K

N

Donor ions

Figure 2.59 Depletion region in an unbiased semiconductor diode

Width of the depletion region W

A

P

− − − −

+ + + +

− − − −

+ + + +

− − − −

+ + + +

Acceptor ions

N

K

Donor ions

VR

Figure 2.60 Depletion region increases with increase in reverse-bias voltage

Depending on the doping profiles, varactor diodes are either abrupt (step-type) junction devices or linearly graded-type junction devices. In the abrupt junction varactor diode, the semiconductor material is uniformly doped, and it changes abruptly from P-type to N-type at the junction. The charge density profile is shown in Figure 2.61(a). Here, it is assumed that NA, the acceptor ion concentration is very much larger that ND, the donor ion concentration. Since the net charge must be zero, N AWp = N DWn

Or

Wn =

Since N A >> N D , Wn >> Wp

NA Wp ND

Diodes, Characteristics, and Applications

87

Therefore, W =Wn +Wp ≈Wn In a linear-graded junction device, the charge density varies gradually, almost linearly, as shown in Figure 2.61(b). It is also known that W ∝ VR for a step-type junction Or

1

CT ∝

1

(VR )2 and, W ∝ 3 VR for a linearly graded-type junction Or

1

CT ∝

1

(VR )3 r

r

Charge density

Charge density ND

−W/ 2

0

0

W/ 2

NA >> ND

−NA

Wn Wp W

(a) Abrupt junction

(b) Linearly graded junction

Figure 2.61 Charge density profiles of abrupt and linear-graded junctions

Therefore, CT ∝

1

(VR )

1 2

or

CT ∝

1 1

(2.66)

(VR )3

It can be noted from Eqn. (2.66) that CT varies inversely with VR . If the reverse-bias voltage increases,CT decreases; and if the reverse-bias voltage decreases, CT increases. This is the basic principle of operation of varactor diodes. A typical graph that depicts the variation of CT (pF) with the reverse-bias voltage, VR (V) is shown in Figure 2.62.

88

Electronic Devices and Circuits

From Figure 2.62, it can be noted that typically CT varies from 25 pF to 500 pF as VR varies from −10 V to −1 V. The schematic representation and the electrical equivalent circuit of varactor diode are shown in Figures 2.63(a) and 2.63(b), respectively. C T(pF) 500

100

25 VR(v)

0 −10 −9

−7

−5

−3

−1

Figure 2.62 Variation of CT as a function of VR RS

A

A

K

K CT

(a) Schematic representation of varator diode

(b) Equivalent circuit

Figure 2.63 Schematic representation and equivalent circuit of a varactor diode

Here RS is the resistance of the semiconductor material. The main application of varactor diodes is as tuning capacitors to adjust the resonant frequency of the tuned circuits, Figure 2.64. If f0 is the resonant frequency of the tank circuit comprising C and L, then by adjusting the reverse-bias voltage on the varactor diode (changing CT ), the frequency can be varied as f0 ± ∆f . f0 =

f0 L

C

1

(2.67)

2p LC

f0 ± ∆f

Figure 2.64 Varactor diode used to tune the resonant circuit

Example 2.19 Calculate the value of CT of a Si PN junction whose area of cross section is 1 mm × 1 mm, space charge thickness is 2 × 10−4 cm. The dielectric constant of Si relative to free space is 11.9.

Diodes, Characteristics, and Applications

Solution: We have CT =

(

Given A= 1×10 −3

)

2

89

eA W

= 1×10 −6 m 2

Space charge width, W = 2 ×10 −4 cm = 2 ×10 −6 m Absolute permittivity of Si, e = e 0 e r = 11.9 × 8.85 × 10 −12 = 10.53 × 10 −11 F/m ∴ CT =

eA 10.53 × 10 −11 × 1 × 10 −6 = = 52.65 pF. W 2 × 10 −6

Example 2.20 The depletion capacitance of an abrupt junction is 4 pF at a reverse-bias voltage of 4 V. (i) Calculate the change in the junction capacitance for (a) 1 V increase in bias voltage (b) 1 V decrease in bias voltage. (ii) Determine the incremental change in the capacitance. Solution: (i) For an abrupt junction, CT ∝ 1 VR K Or CT = VR We have, at VR = 4 V, CT = 4 pF. ∴K = CT VR = 4 × 4 = 8 (a) The new VR is VR1 = VR + 1 = 4 + 1 = 5 V CT1 =

8

K =

5

VR1

= 3.58 pF

(b) The new VR is VR 2 = VR −1 = 4 −1 = 3 V CT 2 =

8

K = VR 2

3

= 4.62 pF

(ii) DCT = 4.62 - 3.58 =1.04 pF

2.10

SCHOTTKY BARRIER DIODE

When a metal such as aluminum is required to make a contact with an N-type semiconductor, two types of contacts are possible: (i) ohmic contact and (ii) rectifying contact.

2.10.1 Ohmic Contact When a terminal of a device is required to be brought out externally to enable connections to be made to that terminal, then an ohmic contact is provided. In order to provide metal–semiconductor ohmic contact, an N++ (heavily doped N-type) region is created in the N-type semiconductor, near the surface. Aluminum is deposited on this N++ region to create an ohmic contact.

90

Electronic Devices and Circuits

2.10.2 Rectifying Contact If aluminum is directly deposited on the N-type semiconductor, then the type of contact made is called a rectifying contact. A rectifying contact results in a metal–semiconductor diode, which has the similar V-I characteristics as a PN junction diode. Such a metal–semiconductor diode is called a Schottky diode. Silicon Schottky barrier diode is different from a PN junction diode in that the depletion region exists only in the N-type semiconductor and no depletion region can exist in the metal. As the depletion region is reduced practically to half in a Schottky diode, it can conduct at a lesser forward-bias voltage when compared to a PN junction diode. This is one major advantage of the Schottky diode. Next, if a semiconductor diode is ON for some time and if it is required to be switched into the OFF state, the device will not switch into the OFF state immediately because of the stored charges on either side of the junction. There can be a finite time delay before the device switches into the OFF state. This time delay is called the reverse recovery time, which is large for a PN junction diode. A Schottky diode, practically, has no depletion region. This eliminates the stored charges near the junction. Consequently, the switching speed of a Schottky barrier diode is faster. Semiconductor diodes may operate satisfactorily up to 10 MHz, whereas Schottky diodes can operate up to 300 MHz. The construction of a Schottky barrier diode is shown in Figure 2.65(a) and its schematic representation is shown in Figure 2.65(b). The diode is formed by the rectifying contact at anode A and ohmic contact is provided at the cathode K. Aluminum Rectifying contact

A

K

Ohmic contact

SiO2

n-type A

(a) Construction

K

(b) Schematic representation

Figure 2.65 Schottky barrier diode

In the case of aluminum and also in the N-type semiconductor, the charge carriers are mainly electrons, since holes are smaller in number in the N-type semiconductor. The energies of the electrons in the N-type semiconductor are small when compared with the energies of the electrons in the metal. As such, when the diode is unbiased, electrons cannot cross from the N-type semiconductor into the metal, because of the junction barrier called the Schottky barrier. However, when the diode is forward biased, electrons acquire large energies and cross the barrier. As the electrons reach the metal with large energies, these charge carriers are called hot carriers, and the Schottky diode is also known as the hot carrier diode. When reverse biased, a Schottky diode has a smaller breakdown potential when compared with an ordinary semiconductor diode. The V-I characteristics of a semiconductor and Schottky diodes are shown in Figure 2.66. It can be noted that a Si Schottky diode has a smaller barrier potential (typically, 0.2–0.25 V); whereas, the barrier potential of the Si semiconductor diode is typically 0.7 V.

Diodes, Characteristics, and Applications

IF (mA)

91

Schottky diode

Semiconductor diode VR (V)

VR2

VR1 0.25

0.7

VF (V)

(mA) IR

Figure 2.66 V-I characteristics of Schottky and semiconductor diodes

The main differences between Schottky and PN junction diodes are as follows: 1. Schottky diode is a unipolar device, since holes are so few in number. But a semiconductor diode is a bipolar device, that is both electrons and holes are the charge carriers. 2. In the absence of holes in the metal, the depletion layer is negligibly small. Hence, there can be no stored charges near the junction when the diode is forward biased. As such, the device can be quickly switched OFF. Therefore, a Schottky diode is used for high-speed switching applications. By contrast, a semiconductor diode has a relatively larger reverse recovery time. Hence, the speed of switching is limited by the diffusion capacitance. 3. Because of a larger contact area between the metal and the semiconductor, the forward resistance of the Schottky diode is smaller than an ordinary semiconductor diode. Hence, noise gets reduced. 4. The reverse breakdown potential of a Schottky diode (VR1) is very much smaller than a semiconductor diode (VR2). The approximate equivalent circuit of the Schottky diode is simply an ideal diode in shunt with junction capacitance (Figure 2.67). Ideal diode A

K

C

Figure 2.67 Equivalent circuit of Schottky diode

2.11

SEMICONDUCTOR PHOTODIODE

In an ordinary semiconductor diode, when reverse biased, the current that flows is only due to thermally generated minority charge carriers and is negligibly small at room temperature (typically of the order of µA). This current is called the reverse saturation current. When the temperature of the junction is increased, more number of electron–hole pairs are generated, and hence the minority carrier current increases. Electron–hole pairs are also generated due to incident light

92

Electronic Devices and Circuits

radiation on the junction, resulting in the increase in the reverse current in a diode. This current can further be increased by increasing the intensity of the incident light radiation. Two-terminal devices (diodes) that are designed to be sensitive to incident light radiation are called photodiodes as indicated in Figure 2.68. Light radiation

Transparent plastic casing

p

n IR

Reverse bias VR

Depletion region

Figure 2.68 Semiconductor Photodiode

When there is no incident illumination, the current in the photodiode is the minimum and is called the dark current, ID. Practically, this current can be taken to be zero (typically this current is of the order of 2nA). An illumination of 10 mW/cm2 can now cause a reverse current, IR of 18 µA. Increasing VR will not necessarily increase IR, because with a small VR itself all the charge carriers must have been swept across the junction. Hence, IR remains constant even with increase in VR. Now the illumination can be increased to 20 mW/cm2 and a different characteristic can be plotted. One can, thus, obtain a family of curves (Figure 2.69). DC load line I (mA) 80

50 mW/cm2

70 40 mW/cm2

60 50

30 mW/cm2

40 20 mW/cm2

30

VF (V)

20

10 mW/cm2

10

H = 5 mW/cm2 Dark current VR (V) 40

0.4 Forward bias

0

10

20

30

Reverse bias

Figure 2.69 Characteristics of a photodiode

Diodes, Characteristics, and Applications

93

The current in a photodiode is given as follows: V   V I = I S + I o 1 − e h   

(2.68)

T

where, I is the total reverse current, IS is the reverse current proportional to illumination, and Io is the reverse current due to minority carriers and V is the applied voltage (positive for forward bias and negative for reverse bias). If V is a large reverse-bias voltage, then e

V hVT

I S , I = I S e

V hVT

(2.72)

Let V1 be the voltage at which the forward current is 3I. V1

∴ 3I = I S e

hVT

(2.73)

Dividing Eqn. (2.73) by Eqn. (2.72),

3= e

V1 − V = ln 3 hVT

V1 −V hVT

V1 − V = hVT ln 3 = 2 × 0.026 × 1.1 = 0.057 V Example 2.27 In a PN junction diode, the reverse saturation current at T1 is I S1. I S2 = 40 I S1 at T2 . Find the increase in temperature. T2 − T1

Solution: I S2 = I S1 2

10 T2 −T1

2 T2 − T1 log10 2 = log10 40 10

10

=

I S2 = 40 I S1

T2 − T1 log10 40 = log10 2 10 T2 − T1 = 10 × 5.32 = 53.2 °C

T2 − T1 =10 ×

1.602 0.3010

102

Electronic Devices and Circuits

Example 2.28 For the circuit shown in Figure 2.83, a sinusoidal signal vi = 50 sinwt is applied as input. The diodes are ideal. Plot the transfer characteristic.

D1

D2

+

+ 100 K Vo

Vi

Solution: (i) When Vi ≤ 0 V, D1 is ON and D2 is OFF, Figure 2.84(a). Vo = 0 V

100 K

20 V

−

−

Figure 2.83 Circuit for Example of 2.28

(ii) When 0 < Vi < 20 V , D1 is ON and D2 is ON, Figure 2.84(b). Vo = Vi

(iii) When Vi > 20 V , D1 is OFF and D2 is ON, Figure 2.84(c).

Vo = 20 ×

D1 +

D2 100 K

D1 + Vo

Vi

−

20 V

100 K

100 = 10 V 100 + 100

−

+

D2

D1 +

100 K

Vo

Vi

−

20 V

(a)

100 K

−

(b)

+

D2 +

100 K

Vo

Vi

−

20 V

100 K

−

(c)

Figure 2.84 Equivalent circuits

Figure 2.85 gives the transfer characteristic. 20 V Vo

0

10 V 20 V

Vi

Figure 2.85 Transfer characteristic

Example 2.29 For the following clamping circuits, the input is a symmetric square wave, referenced to zero and having a peak-to-peak amplitude of 10 V. Plot the output. Solution: For the circuit in Figure 2.86(a), the positive peaks of the output are clapmed to VD and for the circuit in Figure 2.86(b), the negative peaks of the output are clapmed to VD .

Diodes, Characteristics, and Applications

+

0

10 V

VD

−

0

+

C

+ Vi

103

R

+ VD −

10 V

D Vo

Vo

−

− (a) −

+ 0

10 V

Vi

+ +

C

R

− VD +

D Vo

Vo

10 V

VD

−

−

0

(b)

Figure 2.86 (a) Negative clamper and (b) positive clamper

Example 2.30 A Si diode is operated at 300 K. Find the reverse voltage at which the current falls to 80 percent of I S.  hVV  Solution: I = I S  e − 1  

For Si, h = 2

T

80 percent reverse saturation current = 0.8I S  hVV  0.8I S = I S  e − 1   T

V

0.2 = e 2 × 0.026

V = ln ( 0.2 ) 2 × 0.026

V = - 83.6 mV

Summary • When forward biased, the junction diode offers a very small forward resistance, resulting in an appreciable forward current and behaves as a closed switch. When reverse biased, the current in the device is zero and behaves as an open switch. • Temperature has significant effect on the diode characteristics. VT and IS are temperature dependent. IS gets doubled for every 10°C rise in temperature. • When forward biased, the diode offers a capacitance called the diffusion capacitance or storage capacitance, CD; and when reverse biased, the capacitance offered by it is called the transition capacitance or space charge capacitance or depletion region capacitance, CT. CD » CT. • Zener and avalanche diodes are breakdown diodes. Zener breakdown occurs due to the physical rupturing of the covalent bonds due to the applied reverse-bias voltage. An avalanche diode conducts heavily, when reverse biased, at larger voltages due to the process called avalanche multiplication.

104

Electronic Devices and Circuits

• A clipper eliminates a portion or portions of the input signal. A clamping circuit is simply a dc-level shifter or dc restorer. It shifts the dc level of an input waveform to a desired level. • A heavily doped PN junction diode in which the potential barrier becomes so thin that the charge carriers that possess negligible energy punch through the barrier instead of surmounting it. This phenomenon is called tunneling, and the diode is called tunnel diode. • A varactor diode is a reverse-biased diode in which the junction capacitance or the transition capacitance, CT varies as the width of the depletion region varies. • A metal–semiconductor diode is called a Schottky diode and is different from a PN junction diode in that the depletion region is reduced practically to half when compared to a PN junction diode. • Two-terminal devices (diodes) that are designed to be sensitive to incident light radiation are called photodiodes. • In a PIN diode, a slightly doped intrinsic (I ) region is sandwiched between heavily doped P- and Nregions and PIN diodes are used as microwave switches, phase shifters, and attenuators, where high isolation and low loss are required. • Gunn and IMPATT diodes are used at microwave frequencies to generate oscillations.

multiple ChoiCe QueStionS 1. Which capacitance dominates in the reverse-bias region? (a) Depletion capacitance (b) Diffusion capacitance (c) Distributed capacitance (d) Stray capacitance 2. Schottky diodes is also known as (a) avalanche diode (c) hot carrier diode

(b) breakdown diode (d) junction diode

3. What breakdown mechanism is observed in a diode which has a breakdown voltage less than 5 V? (a) Avalanche breakdown (b) Zener breakdown (c) Physical breakdown (d) Internal breakdown 4. A Zener diode is normally (a) reverse biased (c) unbiased

(b) forward biased (d) none of the above

5. A 3.8 V Zener diode has a power rating of 2 W. The maximum Zener current is (a) 526.3 mA (b) 5.263 A (c) 526 A (d) 0.05263 A 6. What breakdown mechanism is observed in a diode that has a breakdown voltage more than 5 V? (a) Avalanche breakdown (b) Zener breakdown (c) Physical breakdown (d) Internal breakdown 7. Avalanche breakdown results basically due to (a) impact ionization (b) strong electric field across the junction (c) emission of electrons (d) rise in temperature 8. The varactor diode is usually (a) forward biased (c) unbiased

(b) reverse biased (d) holes and electronics

Diodes, Characteristics, and Applications

105

9. The depletion region in a junction diode contains (a) only charge carriers (of minority type and majority type) (b) no charge at all (c) vacuum, and no atoms at all (d) only ions , that is, immobile charges 10. The main reason why electrons can tunnel through a PN junction is that (a) they have high energy (b) the barrier potential is very high (c) the depletion layer is extremely thin (d) the impurity level is low 11. Negative resistance is exhibited by a Gunn diode when electrons are transferred from (a) low mobility energy band to high mobility energy band (b) high mobility energy band to low mobility energy band (c) diffusion region to drift region (d) drift region to diffusion region 12. In an step-graded junction varactor diode 1

1

(a) C is proporrtional to V 3

(b) C is proporrtional to V 2

(c) C is proporrtional to V

−1 2

(d) C is proporrtional to V

−1 3

13. In a linearly graded junction varactor diode 1

1

(a) C is proporrtional to V 3

(b) C is proporrtional to V 2

(c) C is proporrtional to V

−1 2

(d) C is proporrtional to V

14. For an ideal PN junction diode, the forward resistance is . (a) zero, infinity (b) infinity, zero (c) zero, zero (d) infinity, infinity 15. Zener breakdown occurs due to (a) high forward voltage (c) strong electric field

−1 3

and the reverse resistance is

(b) high reverse voltage (d) strong magnetic field

16. If the breakdown in a diode is due to avalanche multiplication, then the temperature coefficient of the diode is (a) negative (b) positive (c) zero (d) infinity 17. For a Zener diode, the temperature coefficient is (a) negative (b) positive (c) zero (d) infinity 18. A Schottky diode is preferred over a semiconductor diode for high-frequency applications because of its (a) faster switching speed (b) slower switching speed (c) large physical size (d) small physical size

106

Electronic Devices and Circuits

19. Both avalanche diodes and Zener diodes are commonly known as (a) avalanche diodes (b) Zener diodes (c) varactor diodes (d) tunnel diodes 20. Zener and avalanche diodes are used as (a) voltage reference elements (b) current reference elements (c) resistance reference elements (d) none of the above 21. In which of the following diodes the impurities are heavily doped? (a) PN junction diode (b) Gunn diode (c) Varactor diode (d) Tunnel diode 22. The minimum voltage required for a PN junction diode to conduct when forward biased is called (a) breakdown voltage (b) conducting voltage (c) cut-in voltage (d) applied voltage 23. A circuit that is used to eliminate a portion or portions of the input signal is called (a) clamping circuit (b) clipping circuit (c) damping circuit (d) oscillator 24. A circuit that is used to reintroduce the dc component that is lost during transmission is called (a) clamping circuit (b) clipping circuit (c) damping circuit (d) oscillator 25. Avalanche multiplication and transit time effects are responsible for negative resistance in the following diode: (a) Gunn diode (b) IMPATT diode (c) Varactor diode (d) Tunnel diode 26. A back diode is a tunnel diode in which (a) IP is reduced to the level of IV (b) IV is increased to the level of IP (c) current is zero (d) current is infinity

Short anSwer QueStionS 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14.

How does the reverse saturation current in a PN junction diode vary with temperature? What is a diffusion capacitance in a PN junction diode? What is the reverse recovery time of a PN junction diode? In a junction diode when the P material is more positive than the N material, then what type of biasing is it ? Why does the reverse current suddenly rise to a large value when the breakdown voltage is reached, in a Zener diode? What is avalanche multiplication and when does this phenomenon occur in a PN junction diode? What is a clamping circuit? State the clamping circuit theorem. What is tunneling? What is a varactor diode? What are the main advantages of a Schottky diode? What is photovoltaic effect? What is Gunn effect? What is an IMPATT diode?

Diodes, Characteristics, and Applications

107

long anSwer QueStionS 1. Obtain the expression for the diode current and draw the forward and reverse characteristic. 2. Derive the expressions for the diffusion and transition capacitances of the junction diode. 3. Write short notes on the following: (i) Zener diode and (ii) avalanche diode 4. With the help of neat circuit diagrams and transfer characteristics, explain the working of a limiter and a slicer. 5. With the help of a neat circuit diagram and waveforms, explain the working of the practical clamper. 6. Explain the working of the following diodes: (i) tunnel diode, (ii) varactor diode (iii) Schottky diode, and (iv) PIN diode. 7. Write short notes on the following: (i) Gunn diode and (ii) IMPATT diode.

unSolved problemS 1. Find the factor by which the reverse saturation current of a Ge PN junction diode increases when the temperature rises from 27°C to 127°C. 2. A Germanium diode operating at 27°C is forward biased at 0.4 V. The temperature is increased from 27°C to 127°C. By what factor will the forward current increase? 3. A silicon diode operated at 127°C has its reverse saturation current as 50 µA. Calculate its dynamic resistance at (i) forward voltage of 0.3 V and (ii) reverse voltage of −0.4 V. Assume ideal diode. 100 K 4. A diode has a forward current of 0.5 mA at 0.3 V and its forward current is 30 mA at a forward voltage of 0.6 V + + at 300 K. Is the diode a Si or Ge diode? D2 5. For the circuit in Figure 2.87, plot the transfer charD1 100 K acteristic and the input output waveforms, if the Vi Vo input varies as vi = 50 sinwt is applied as input. The − 10 V 20 V − diodes are ideal . Figure 2.87 6. A square wave referenced to 0 V has a peak-to-peak swing of 20 V. Plot the output of the clamping circuit shown in Figure 2.88, if VR = 5 V. Assume that there is no distortion in the output.

C

+

+

D

Vi

−

5V

Figure 2.88

R

Vo

−

3

RECTIFIERS AND FILTERS

Learning objectives After reading this chapter, the reader will be able to    

3.1

Appreciate the application of diodes in full-wave and half-wave rectifiers Calculate the possible values of dc and ac currents, rectification efficiency, ripple, and so on Understand the need for using different types of filters, such as inductor filter, capacitor filter, L-type filter, and p-type filter, to reduce the ripple Appreciate the need for multiple filters

INTRODUCTION

A PN junction diode can be used for various applications, such as rectifiers, demodulators, clipping and clamping circuits, and so on. The choice of the diode for a specific application depends on many factors. A few important parameters are listed below: 1. Peak inverse voltage: The maximum reverse-bias voltage that can be applied to a PN junction diode is called peak inverse voltage (PIV) or peak reverse voltage (PRV). This is normally specified at a reverse saturation current. If the PIV rating of the diode used in a circuit is less than that required, then another diode is connected in series with the first diode. This is known as stacking of the diodes. If n identical diodes are stacked, then the PIV of the diode stack is n times the PIV of the individual diode. 2. Maximum power dissipation: If the current in the diode is ID and the voltage between the diode terminals is VD, then the amount of power dissipation in the device is PD = IDVD. PD can be PD(max) when the current and voltage take maximum values. For instance, if PD(max) is specified as 1 W at room temperature (25°C), it means that the diode can handle a dissipation of 1 W. Anything in excess of this will damage the device. However, with an increase in temperature, the dissipation capability of the diode decreases. This information is normally given by the manufacturer by way of a derating curve or specifies the same by a derating factor. Derating factor is specified as, say, D = 2.5 mW/°C. It means that the dissipation capability decreases by 2.5 mW per degree rise in temperature. 3. Switching speed: Ideally, it is assumed that the diode behaves as a switch. But we have seen that a forward-biased diode has junction capacitance called the diffusion capacitance, CD. When reverse biased, the diode has transition capacitance (CT). As CD >> CT, CT influences the switching speed of the diode. But, at low frequencies, this is not a serious constraint.

109

Rectifiers and Filters

4. Forward and reverse resistances: Ideally, the forward resistance Rf of a diode (when ON, that is, when conducting) is zero. But a practical diode has Rf of a few ohms (typically 5–10 Ω). Similarly, the reverse resistance Rr of the diode (when OFF, that is when not conducting) is ∞. But a practical diode has Rr of a few megaohms (typically, 1–2 MΩs).

3.2

RECTIFIERS

All the electronic circuits require a dc voltage or battery to operate. Batteries may have to be used invariably, where there is no access to the conventional mains supply. However, the life of a battery is limited. Therefore, it becomes a necessity to derive the dc voltage from an ac source, preferably the mains power supply. This mains voltage of 230 V is an alternating signal operating at 50 cycles per second. The voltages that we normally need to operate electronic circuits are typically of the order of 3 V, 6 V, 9 V, 12 V, 15 V, etc., which are essentially low voltages. Hence, in majority of such applications, there is a need to step down the mains voltage using a transformer. A transformer is a device that transfers electrical energy from the primary winding to the secondary winding through inductive coupling. A varying current in the primary winding creates a varying magnetic flux in the transformer’s core, and thus a varying magnetic field through the secondary winding. This varying magnetic field induces a varying voltage in the secondary winding. The secondary voltage of the transformer can be chosen appropriately by choosing proper turns ratio of the transformer. Yet, there is a need to convert the alternating signal into a unidirectional one, called the dc signal. The circuits that convert the ac signals into dc signals are called rectifiers. These rectifiers are of two types: (i) half-wave rectifiers and (ii) full-wave rectifiers.

3.2.1 Half-Wave Rectifier A half-wave rectifier is one in which the diode conducts for only one-half of the input cycle period (Figure 3.1), and the input–output waveforms are shown in Figure 3.2. Ideal diode ON

D

vs = Vmsinwt 230 V, 1 φ 50c/s Mains

vs = Vmsinwt

+ RL

230 V, 1 φ Load 50c/s Mains

−

Rf

+ Idc

−

i

+ RL

VL Load −

Figure 3.1 Circuit of half-wave rectifier

The input to the rectifier circuit is a sinusoidal signal taken from the secondary of the transformer and varies as Vm sinwt . Neglecting Vg when forward biased, the diode can be replaced by an ON switch in series with the forward resistance of the diode, Rf. We have vs = Vm sinwt (3.1) Neglecting the resistance of the secondary winding of the transformer, the peak load current, Im is Im =

Vm Rf + RL

(3.2)

110

Electronic Devices and Circuits Vm vs

3p

0

2p

p

t

−Vm Input to the diode circuit Im

i

Idc 0

2p

p

3p

t

Output current

Figure 3.2 Input and output waveforms

The current i also varies as vs and is given as follows: I sin a for 0 ≤ a ≤ p i = I m sin wt =  m  0 for p ≤ a ≤ 2p

(3.3)

where a = wt. But the output current flows in half cycles, which means that the output is no longer sinusoidal and as such will have a number of frequency components (w, 2w, 3w, and so on) in it in addition to the dc component. The components with frequencies 2w, 3w,… are called harmonics. This suggests that the output is not a constant value (dc) as desired, but will have unwanted ac components that will change the magnitude of the dc from time to time.

DC Component of Current Let us now try to find out the dc component of current, which is the average taken over one cycle, that is, from 0 to 2p. Idc =

1 2p

∫

p

0

Im sin a d a =

I dc =

Im [ −cosa ]p0 2p

Im I (1 + 1) = m p 2p

(3.4)

Vm p (Rf + RL )

(3.5)

I dc =

Rectifiers and Filters

111

Root Mean Square Component of Current The root means square or rms component of current for a sinusoidal signal is as follows:

Im 2

. In the case of half-wave rectifier, the rms value is calculated p

1 2 I m2 (sin a ) d a 2p ∫0

I rms =

I rms =

Im 2p

p Im = 2 2

(3.6)

Form factor, F is defined as follows: F=

I rms  I m   p  =  = 1.57 I dc  2   I m 

(3.7)

Ripple Factor We are aware of the following relationship: (3.8)

2 2 I rms = I dc + I ac2

where Iac is the rms value of the ac components. The fluctuating component in the output is called the ripple. What is a ripple? If you throw a stone in steady water, you see ripples. A good dc source should give a constant dc voltage. If ripple is present along with this voltage, this voltage will change with time. The effectiveness with which the rectifier is able to reject the ripple is given by the ripple factor, g defined as follows: g =

I ac Vac = I dc Vdc

(3.9)

From Eqn. (3.8), (3.10)

2 2 I ac = I rms − I dc

For the half-wave circuit, using Eqn. (3.10), g =

Iac = Idc

Irms 2 − Idc 2 I dc g =

2

 I rms  =  −1 = F 2 −1  Idc 

(1.57)2 − 1 = 1.21

(3.11)

The ripple in the output of a half-wave rectifier is large, resulting in large variation of the dc voltage. This is one disadvantage.

Rectification Efficiency or Ratio of Rectification The effectiveness with which the given ac input power from the secondary of the transformer is converted into the desired dc output power is given by the rectification efficiency and is designated as h. h=

Pdc dc power delivered to the load = Pi ac power input from the secondaary of the transformer

112

Electronic Devices and Circuits

2

 I2  I  Pdc = I RL =  m  RL =  m2  RL  p  p 

(3.12)

2 dc

Pi = I

h=

2 rms

I (Rf + RL ) =  2m 

 I m2   p 2  RL  Im    2

2

(Rf + RL )

=

2

(Rf + RL )

(3.13)

4 1 4 ≈ = 40.6% p 2  Rf  p 2 1 + R  L

(3.14)

since Rf > RL. Equation (3.40) reduces to I1( rms ) =

1 w 2 2 L Vm

(3.41)

From Eqn. (3.39), the rms component of the second harmonic I2 is I 2 ( rms ) =

2I m 3p 2

=

2Vm 3p 2

×

1

(R

2 L

+ 4w 2 L2

)

(3.42)

124

Electronic Devices and Circuits

As wL >> RL, Eqn. (3.42) reduces to I 2 ( rms ) =

2Vm

×

3p 2

Vm 1 = 2wL 3pwL 2

(3.43)

The ac component of current Iac is 2

I ac = I

+I

2 1( rms )

I ac =

2 2 ( rms )

 Vm   Vm  =  +  wL 2 2   pwL3 2 

2

(3.44)

Vm  1   1  0.36Vm   +  = wL  8   18p 2  wL

I dc =

(3.45)

I m Vm = p pRL

(3.46)

Using Eqs (3.45) and (3.46), g =

I ac 0.36Vm pRL 1.13RL = × = I dc Vm wL wL

(3.47)

Equation (3.47) shows that g is inversely proportional to L and directly proportional to RL. Hence, for g to be small, L should be large and also RL should be small. It implies that inductor filter is better used to reduce ripple when the load current is large. If

If

wL = 1, then g = 1.13 RL

(3.48)

wL = 5, then g = 0.226 RL

(3.49)

3.3.2 Full-Wave Rectifier with Inductor Filter A full-wave rectifier circuit with inductor filter is shown in Figure 3.16 and the waveforms in Figure 3.17. D1

L +

vs = Vmsinwt

i RL

230 V, 1 φ 50c/s Mains

Load −

vs′ = Vmsin(wt + p)

D2

Figure 3.16 Full-wave rectifier with inductor filter

Rectifiers and Filters

125

The output current of a simple full-wave rectifier shown in Figure 3.16, neglecting the third and higher harmonic terms, is given by i=

2I m 4I m − cos 2wt p 3p

(3.50)

Equation (3.50) tells that the output current has a dc component and the second harmonic; whereas the fundamental component is not present. I

L=0 L≠ 0 Im 2Im π

Idc

0

wt 2p

p

3p

∅

4p

Figure 3.17 Output current with and without L

From Figure 3.16, if Rf = 0 and the resistance associated with L is also assumed to be zero, ideally, the net resistance in the loop is RL only: ∴ Im =

Vm RL

From Eqn. (3.50), I dc =

2 I m 2Vm = p pRL

(3.51)

However, for ac components the circuit offers an impedance Z: Z = RL + j 2wL

(3.52)

since the second harmonic is present in the output: Z =

(RL )2 + (2wL )2

Therefore, Im for the ac component is Im =

Vm 2

(RL ) + (2wL )2

(3.53)

126

Electronic Devices and Circuits

From Eqn. (3.50), the peak amplitude of the ac component (2nd harmonic) I2 is I2 =

4I m 3p

(3.54)

Substituting Eqn. (3.53) in Eqn. (3.54), I2 =

The rms value of I2, I2 (rms) is

4 × 3p

Vm 2

(RL ) + (2wL )2

(3.55)

I2 2 I 2 ( rms ) = I ac =

4 3p 2

Vm

×

2

(RL ) + (2wL )2

(3.56)

From Figure 3.17, it can be noted that the load current lags behind the voltage by an angle f. Ripple factor, g =

I ac 4 = × I dc 3p 2

Vm 2

(RL ) + (2wL ) g =

If 1 ( RL || X C ) and also that XC > XC at 2w. From Eqn. (3.50), the maximum amplitude of the second harmonic component is I2 and is given as follows: 4I i = 2 I m − m cos 2wt p 3p

I2 =

4I m 3p

(3.85)

Im =

Vm XL

(3.86)

But

Rectifiers and Filters

133

From Eqs (3.85) and (3.86), I ripple (rms) =

4I m 3p 2

=

 2   2Vm   2  =  =   Vdc 3 2pX L  3X L   p   3X L 

(3.87)

Vripple (rms) = I ripple (rms) × X C

(3.88)

4Vm

Using Eqn. (3.87), Eqn. (3.88) reduces to Vripple (rms) = Vac =

g =

2 Vdc X C 3X L

(3.89)

Vac 2  XC  2 1 1 1 = = × × =   3  XL  3 2wC 2wL 6 2w 2 LC Vdc

g =

1.19 LC

(3.90)

where, L is in henries, C is in mF and f = 50c/s. From Eqn. (3.90), it is evident that g is independent of RL. The larger the values of L and C, the smaller the value of g.

Critical Inductance, LC From Figure 3.24, it can be seen that the current i contains a

dc component I dc. As the value of L increases, i decreases. L should be chosen so that i does not become zero. This value of inductance is called critical inductance, L C. The 4 I m  4Vm  second harmonic current has a peak amplitude of = . If i is not to be zero, 3p  3pXL  the negative peak of i should not fall below I dc. That is, 4Vm 3pX L

(3.91)

2Vm 4Vm ≥ pRL 3pX L

(3.92)

I dc ≥ But Idc =

2Vm pRL

from which wL ≥

L = LC ≥ L is in henries, RL is in ohms, and f = 50 Hz.

2RL 3 2RL RL = 3w 471

(3.93)

134

Electronic Devices and Circuits

One important thing to note here is that if iL is small (RL large), a large value of L is required to reduce ripple. On the contrary, if iL is large (RL small), a small value of L may be enough to reduce ripple. To satisfy these extreme requirements, a choke whose inductance decreases with increasing load current and whose inductance increases with decreasing load current may be used. Such an iron-cored choke is called a swinging choke. This type of choke may typically have L = 30 H at IL = 20 mA and can have L = 5 H at IL = 200 mA.

Bleeder Resistance The output dc voltage of a FW rectifier with LC filter is shown in Figure 3.25. If in the rectifier circuit L is small, then its associated resistance is also small. The capacitor allows the output to reach Vm, which is the no-load output voltage. This voltage falls to Vdc  = 2Vm    p  at IL = IL(min) and remains the same with variation in IL. If the load is disconnected suddenly, that is RL→∞, VL jumps to Vm from Vdc, resulting in poor regulation. If a resistance RB is connected across the load such that RB ensures the minimum load current IL(min) even when the load is open, then the load voltage will remain at Vdc only, ensuring better regulation. The resistance RB is called the bleeder resistance (Figure 3.26). The calculation of RB is similar to the calculation of LC. 4Vm From Eqn. (3.91), I dc ≥ 3pX L 2V And with RL open and RB included, I dc = m . p RB Hence,

VL Vm

Vdc = 2Vm/p

O IL(min)

IL

Figure 3.25 Variation of the output voltage with load current

L

FW Rectifier

lL + VL

i ic

RB −

Load RL

Figure 3.26 Bleeder resistance RB ensures IL(min)

2Vm 4Vm ≥ pRB 3pX L

(3.94)

RB = 1.5X L

(3.95)

Typically RB ≤ 471 Lmax.

Half-Wave Rectifier with LC Filter A half-wave rectifier with LC filter is shown in Figure 3.27. From Eqn. (3.45) we have,  0.36Vm p   0.36p   Vm   0.36p  I ac =  ×  =  Vdc   =  wL p   wL   p   wL 

(3.96)

135

Rectifiers and Filters

D

L iL i C

vs = Vmsinwt

230 V, 1 φ 50c/s Mains

+ VL Load

iC

−

RL

Figure 3.27 Half-wave rectifier with LC filter

Using Eqn. (3.96), Vac = I ac × X C =

g =

0.36pX C × Vdc wL

Vac 1.13 1.13 11.5 = = = Vdc (wL )(wC ) w 2 LC LC

(3.97)

where f = 50c/s, L is in henries, and C is in μF.

3.4

MULTIPLE CASCADED FILTERS

When filters are cascaded, the g of the cascaded filter can be calculated.

3.4.1 Two Stages of an LC Filter Consider two stages of an LC filter as shown in Figure 3.28.

Transformer

L1

and

L2 C1

+ VL C2

FW rectifier

−

Load RL

Figure 3.28 FW rectifier with two-stage LC filter

From Eqn. (3.89), the ripple factor for a full-wave rectifier with LC filter is given as follows: g =

2 XC 2 X C1 × = × 3 XL 3 X L1

where g is the ripple after the first LC filter.

(3.98)

136

Electronic Devices and Circuits

The ripple factor after the second LC filter is g =

2  X C1   X C 2  3  X L1   X L 2 

(3.99)

If there are n-identical LC filters, in which case L1 = L2 =… = Ln = L and C1 = C2 =… =Cn = C then g =

2  XC  3  X L 

n

(3.100)

for n = 2 g =

2 1 1 0.471 1 3.03 × 2 2 = × 2 2 = 2 2 × 4 4 3 (2pf ) LC (2p × 100) L C L C

(3.101)

3.4.2 p-Filter or CLC Filter Consider the filter circuit in Figure 3.29, where in a C filter is cascaded with an LC filter. The filter is called a p filter or CLC filter. The output of the C filter is the input to the LC (or L-type) filter.

Transformer

L

and

C1

+ V¢ g (rms) C2

FW rectifier

Load R − L

Figure 3.29 FW rectifier with p filter

The output of the C filter is a triangular wave that can be expressed by Fourier series (neglecting higher order components) as follows: Vo = Vdc −

I dc sin 2wt 2pfC1

(3.102)

where Vg (pp) at the second harmonic component is Vg (pp) =

I dc 2pfC1

The rms value of the second harmonic component at 2f is Vg (rms) =

Vg (pp) 2

=

I dc 2 2pfC1

=

I dc 2 = 2 I dc X C1 4pfC1

Rectifiers and Filters

The harmonic current through the inductor is = Harmonic component of voltage across C2 is Vg′(rms) =

2 I dc X C1X C 2 = XL

137

2 I dc X C1 XL

2 I dc X C1X C 2 RL × = XL RL

2Vdc X C1X C 2 X L RL

since Vdc = I dc RL gp =

Vg ′(rms) Vdc

X X  2 2 = 2  C1   C 2  = 3 =  RL   X L  w C1C2 LRL (2pf )3 C1C2 LRL

(3.103)

If f = 100 Hz, C is in μF, L is in H, and RL is in ohms. gp =

5700 C1C2 LRL

(3.104)

3.4.3 Full-Wave Rectifier with CRC Filter If there is an unacceptable level of ripple in a full-wave rectifier with capacitor filter, it is also possible to reduce the ripple across the capacitor by using an additional RC filter as shown in Figure 3.30. The RC network is required to pass the dc component of voltage to the load un-attenuated, but it is required to attenuate the ac component appreciably. When the capacitor is fully charged, it behaves as an open circuit for dc. The resultant circuit is shown in Figure 3.31. The circuit to calculate ac voltage across RL is shown in Figure 3.32. Vdc

Vg (rms) V′g (rms)

R Transformer and

C

+ Vdc

+ Vo C

Load RL

−

FW rectifier

Figure 3.30 Cascading an RC filter with a C filter R

Vdc

+ Load Vo RL −

Figure 3.31 DC circuit from Figure 3.30

138

Electronic Devices and Circuits R

+

+

V(rms)

C

V ′(rms)

Figure 3.32 AC circuit to calculate the ac voltage across the load

From Figure 3.31, if Vdc is the dc voltage across the first capacitor, then  RL  Vo = Vdc    R + RL 

(3.105)

If Vdc = 20V, R = 100Ω, RL = 1000Ω, then the dc voltage at the output ,Vo = 18.18V. If the ac ripple voltage across the first capacitor is V(rms), from Figure 3.32, the ac voltage across the load is ′ V( rms)

At f = 100 Hz, X C =

   1   XC  XC = V( rms )  = V( rms )   ≈ V( rms )  R R  R + XC  1+   X C 

(3.106)

1 1 1.59 = = C 2pfC 2p × 100 × C

where XC is in kΩ and C is in μF.

3.5

POWER SUPPLY PERFORMANCE

The performance of a power supply depends on three important factors: (i) source effect (ii) load effect, and (iii) ripple rejection ratio. (i) Source effect: The ac input voltage to a rectifier (called power supply) does not remain constant. A change in the ac source voltage (also called the line voltage) can cause a change in the dc output voltage. The change in the dc output voltage for 10 percent change in source voltage is called source effect. Source effect = ∆Vo for a 10 percent change in Vi Another way of expressing the change in the dc output voltage due to source effect is by line regulation, which is defined as follows: Line regulation =

Source effect ´ 100% Vi

Rectifiers and Filters

139

(ii) Load effect: The dc voltage at the output of a power supply changes with load current. Vo decreases with increase in IL and increases with decrease in IL. The load effect specifies how the output dc voltage changes when IL increases from 0 to IL(max). Load effect = ∆Vo for ∆ I L ( max ) Another way of expressing the change in the dc output voltage due to load effect is by load regulation, which is defined as follows: Load regulation =

Load effect × 100% Vi

(iii) Ripple rejection ratio is defined as the ratio of the ripple voltage at the output to the ripple voltage at the input: Ripple rejection ratio =

Vg o Vg i

Additional Solved Examples Example 3.4 A half-wave rectifier with RL = 1 kΩ is given an input of 15 V peak from step-down transformer. Calculate dc voltage and load current for ideal and silicon diodes. Solution: Given values are RL = 1 kΩ, Vm = 15 V Case (i): Ideal diode Vg = 0 V, Rf = 0 Ω Vdc =

Vm 15 = =4.78 V p p

I dc =

Vdc 4.78 = = 4.78 mA RL 1× 103

Case (ii): Silicon diode Vγ = 0.5 V Vdc = I dc =

Vm − Vg = p

15 − 0.5 = 4.62 V p

Vdc 4.62 = = 4.62 mA RL 1× 103

Example 3.5 A half-wave rectifier has a load of 5 kΩ. If the diode resistance and the secondary coil resistance together have resistance of 100 Ω and the input varies as 230 2 sin 2p × 50t , calculate the following:

140

(i) (ii) (iii) (iv)

Electronic Devices and Circuits

Peak, average, and rms values of the current dc power output dc power input Efficiency of the rectifier

Solution: RL = 5 kΩ , Rs + Rf = 100Ω Vm = 230 2 = 325.22 V (i) I m =

I dc =

I rms =

Vm 325.22 = = 63.77 mA Rs + Rf + RL 5000 + 100 I m 63.77 = = 20.31 mA p p Im

63.77 =

2

= 45.10 mA

2

(ii) Vdc = I dc RL = (20.31mA )(5 kΩ ) = 101.55 V Pdc = Vdc I dc = 101.55 ´ 20.31 mA = 2.062 W (iii) Pac = Vrms I rms = 230 ´ 45.10 mA = 10.373 W (iv) h =

Pdc 2.062 × 100 = × 100 = 19.88% Pac 10.373

Example 3.6 A 240 V(rms) , 50 Hz voltage is applied to the primary of a 20:1 step-down centertapped transformer used in the full-wave rectifier having a load of 900Ω. If the diode resistance and the secondary coil resistance together is 100Ω, determine the following: (i) (ii) (iii) (iv) (v)

dc current flowing through the load dc voltage across the load dc power delivered to the load PIV across each diode Ripple voltage and its frequency

Solution:

N 2 2Vs ( rms ) 1 = = N1 Vp( rms ) 20

Vs (rms) =

Vp(rms) 40

=

240 = 6V 40

Rectifiers and Filters

RL = 900 Ω

141

Rs + Rf = 100 Ω

RL + Rs + Rf = 900 + 100 = 1000 Ω Im =

Vs ( max ) RL + Rs + Rf

(i) I dc =

=

6 2 = 8.484 mA 1000

2 I m 2 × 8.484 = = 5.40 mA p p

(ii) Vdc = I dc RL = 5.40 × 0.9 = 4.86 V (iii) Pdc = Vdc I dc = 4.86 × 5.40 × 10 −3 = 0.026 W (iv) PIV = 2Vs ( max ) = 2 × 2 × 6 = 16.968 V (v) Ripple factor =

Vripple( rms ) Vdc

= 0.48

Vripple( rms ) = 0.48 ×Vdc = 0.48 × 4.86 = 2.33 V Ripple frequency = 2f = 2 × 50 = 100 Hz Example 3.7 A bridge rectifier uses four identical diodes having forward resistance of 10 Ω each. Transformer secondary resistance is 10 Ω and the secondary voltage is 30 V(rms). Determine the dc output voltage for Idc = 200 mA and the value of the ripple voltage. Solution: Vs (rms) = 30V , Rs = 10 Ω, Rf = 10 Ω , Idc = 200 mA Since,

I dc =

We know that I m =

2I m p

∴ Im =

pI dc p × 200 = = 314 mA 2 2

Vs ( max ) Rs + 2Rf + RL

Rs + 2Rf + RL =

Vs (max ) Im

=

30 2 = 135.12 Ω 314

RL = 135.12 − 10 − 2 × 10 = 105.12 ≈ 105 Ω Vdc = I dc RL = 200 × 10 −3 × 105 = 21 V g=

Vg (rms) Vdc

= 0.48

∴Vg (rms) = 0.48Vdc = 0.48 × 21 = 10.08 V

142

Electronic Devices and Circuits

Example 3.8 A rectifier arrangement uses a center-tapped transformer having 230–0–230 V. Determine (i) the value of RL that gives the maximum dc output power, (ii) Vdc, (iii) Idc, and (iv) PIV of each diode. Assume ideal diodes rated to handle maximum current of 600 mA. Solution: As the diodes are rated to handle a maximum current of 600 mA, for safe operation the diode current must be limited to 80 percent of this maximum value. Therefore, I m = 0.8 × 600 = 480 mA. Vs ( max ) = 2 ×230 = 325.22 V (i)

RL =

(ii)

I dc =

Vs ( max ) Im

=

325.22 = 677 Ω 480 × 10 −3

2 I m 2 × 480 = = 305.73mA p p

(iii) Vdc = I dc RL = 305.73 × 10 −3 × 677 = 206.98V (iv) PIV of each diode = 2Vs (max ) = 2 × 325.22 = 650.44 V Example 3.9 Calculate the value of L of an inductor filter used in (i) half-wave rectifier and (ii) full-wave rectifier, operating at power supply frequency of 50 Hz. It is required to derive a dc output with 5 percent ripple. RL = 500 Ω. Solution: (i) Ripple factor for half-wave rectifier with inductor filter is given as follows: g HW =

1.13RL 1.13 × 500 565 = = wL 2pfL 100pL

∴L =

565 = 35.99 H 100p × 0.05

(ii) Ripple factor for full-wave rectifier with inductor filter is given as follows: g FW =

0.236RL 0.236 × 500 118 = = wL 2pfL 100pL

∴L =

118 = 7.52 H 100p × 0.05

Example 3.10 Calculate the value of C of a capacitor filter used in (i) half-wave rectifier and (ii) full-wave rectifier, operating at power supply frequency of 50 Hz. It is required to derive a dc output with 5 percent ripple. RL = 500 Ω. Solution: (i) Ripple factor for half-wave rectifier with capacitor filter is given as follows: 1 g HW =

= 2 3 fCRL

5780 , where C is in μF and RL is in ohms. CRL

Rectifiers and Filters

143

5780 5780 C=g = = 231.2 µF HW R 0.05 × 500 L (ii) Ripple factor for full-wave rectifier with capacitor filter is given as follows: g FW =

1 = 4 3 fCRL

2890 , where C is in μF and RL is in ohms. CRL

2890 2890 C=g = = 115.6 µF FW R L 0.05 × 500 Example 3.11 A 15-0-15 V(rms) ideal transformer is used with a full-wave rectifier circuit with diodes having forward drop of 1 V. The load has a resistance of 100 Ω and a capacitor of 1000 μF is used as a filter across the load resistance. Calculate the dc load current and the voltage. Solution: Vs ( max ) = 2Vs ( rms ) = 2 × 15 = 21.21V RL = 100 Ω, drop across the diode = Vd = 1 V, C = 1000 μF Im = I rms = I dc =

Vs ( max ) -Vd RL Im 2

0.202 =

=

21.21 - 1 = 0.202 A 100

= 0.143 A

2

2I m 2 × 0.202 = = 0.129A p p

 4 fCRL  Vdc = Vs (max )  − Vd  1 + 4 fCRL   4 × 50 × 1000 × 10 −6 × 100  Vdc = 21.21  − 1 = 19.2 V  1 + 4 × 50 × 1000 × 10 −6 × 100  Example 3.12 In a full-wave rectifier using an LC filter, L = 10 H, C = 100 μF, and RL = 500 Ω. Calculate Vdc, Idc, and ripple factor for an input of vi = 100 sin (100pt). Solution: Given that vi = 100 sin(100p t) ∴Vm = 100 V Vdc =

2Vm 2 × 100 = = 63.69V p p

I dc =

Vdc 63.69 = = 127.38 mA RL 500

144

Electronic Devices and Circuits

Ripple factor g =

1.19 1.19 = 1.19 × 10 −3 = LC 10 × 100

Example 3.13 A full-wave rectifier supplies a dc voltage of 200 V at 500 mA. f = 50 Hz. Calculate the transformer secondary voltage for (i) a capacitor filter using a capacitor of 100 μF. (ii) a choke input filter using a choke of 10 H and a capacitor of 100 µF. Neglect the resistance of choke. Solution: Vdc = 200 V, I dc = 500 mA, f = 50 Hz (i) Capacitor input filter with C = 100 μF  1  Vdc = Vs ( max ) − I dc    4 fC   1  Vs ( max ) = Vdc + I dc    4 fC  Vs ( max ) = 200 +

500 × 10 −3 4 × 50 × 100 × 10 −6

Vs ( max ) = 200 + 25 = 225 V

Vs ( rms ) =

Vs ( max ) 2

=

225 2

= 159.12V

(ii) Choke input filter with L = 10 H, C = 100 μF, Rx = 0 Vdc =

2 Vs (max ) R × p (Rx + R )

Since, Rx = 0 Vdc = ∴ Vs (max ) =

Vs ( rms ) =

2Vs ( max ) p

p p Vdc = × 200 = 314 V 2 2

Vs ( max ) 2

=

314 2

= 222.06 V

Rectifiers and Filters

145

Example 3.14 A full-wave single-phase rectifier uses a p-filter consisting of two 1000 μF capacitances and a 20 H choke. The transformer voltage to the center tap is 300 V rms. The load current is 1000 mA. Calculate the dc output voltage and the ripple voltage. The resistance of the choke is 100 Ω. Solution: C = 1000 μF, L = 20 H, Vs ( rms ) = 300 V, Rx (resistance of the choke) = 100 Ω, I dc = 1000 mA For the capacitor filter, Vg = peak-to-peak ripple voltage =

I dc 1000 × 10 −3 = 3.18 V = 2p fC 2p × 50 × 1000 × 10 −6

For a p filter, Vdc = Vs (max ) −

Vg 2

− I dc Rx

Vg Vdc = 2Vs (rms) − − I dc Rx = 300 2 − 1.59 − 1000 × 10 −3 × 100 = 322.6 V 2 RL =

Vdc 322.6 = = 322.6 Ω I dc 1000 × 10 −3

gp =

5700 5700 = = 0.000883 × 10 −3 C1C2 LRL 1000 × 1000 × 20 × 322.6

Ripple voltage = g p Vdc = 0.000883 × 10 −3 × 322.6 = 0.285mV

Example 3.15 For the full-wave rectifier with p filter (CRC filter) shown in Figure 3.30, calculate the dc and ac components of voltages across the load. Also calculate the value of g . R = 500 Ω, RL = 5 kΩ, C = 500 μF, Vdc = 100 V, and Vg (rms) = 10 V. Solution: (i) The dc voltage at the output, Vo is Vo = Vdc (ii) X C =

RL 5000 = 100 ´ = 90.91 V R + RL 500 + 5000

1.59 1.59 = = 3.18 Ω C 500

The ac ripple voltage across the load is Vg ′(rms) = Vg (rms) (iii) Ripple factor, g =

Vg ′(rms) Vo

=

XC 3.18 = 10 × = 0.0636 V R 500

0.0636 × 100 = 0.07% 90.91

146

Electronic Devices and Circuits

Example 3.16 (i) The output voltage Vo of a power supply decreases from 15 V to 14.5 V when IL increases from 0 to IL(max). Calculate load effect and load regulation. (ii) If Vo increases from 15 V to 15.5 V when Vi increases by 10 percent. Calculate line effect and line regulation. Solution: (i) Load effect = 15 − 14.5 = 0.5 V 0.5 × 100 = 3.33% Load regulation = 15 (ii) Source effect = 15.5 − 15 = 0.5 V Line regulation =

0.5 × 100 = 3.33% 15

Example 3.17 Determine the component values of CLC filter for Vdc = 15 V, I L = 300 mA and g p = 1%. Solution: RL =

gp =

Vdc 15 = = 50 Ω I L 300 × 10 −3 5700 = 0.01 C1C2 LRL

Let C1 = C2 = C Then,

5700 5700 = 0.01 Or C 2 = 0.01× LRL C 2 LRL

Choose L = 20 H. Then, C 2 = C=

5700 = 570 0.01× 20 × 50

570 = 23.88 μF.

Example 3.18 A full-wave rectifier with C-type filter is to supply I dc = 50 mA at Vdc = 20 V . Determine (i) RL , (ii) C, and (iii) Vrms of the transformer secondary. g = 5% Solution: Given I dc = 50 mA , Vdc = 20 V and g = 5% = 0.05 (i) RL = (ii) g =

Vdc 20 = = 400 Ω I dc 50 × 10 −3 1

1 =

4 3 fCRL

Or C =

4 × 3 × 50 × C × 400 1

4 × 3 × 50 × 0.05 × 400

= 144 µF

Rectifiers and Filters

(iii) Vdc = Vm

147

4 fCRL 1 + 4 fCRL Or Vm = Vdc 1 + 4 fCRL 4 fCRL 4 fCRL = 4 × 50 × 144 × 10 −6 × 400 = 11.52 Vm = 20 ´ Vr ms =

1 + 11.52 = 21.74 V 11.52 21.74

= 15.36 V

2

Example 3.19 A 24 V peak rectified voltage of a rectifier is applied as input to a capacitor filter with C = 1000 µF . Determine the values of g and Vdc , for a load current is 500 mA and f = 50Hz (i) if the rectifier is a HW rectifier and (ii) if the rectifier is a FW rectifier. Solution: (i) For the HW rectifier,  1  Vm = Vdc + I dc    2 fC   1  500 × 10 −3 = 24 − 5 = 19 V Or Vdc = Vm − I dc   = 24 − 2 × 50 × 1000 × 10 −6  2 fC  RL =

Vdc 19 = = 38 Ω I L 500 × 10 −3 1

g =

= 2 3 fCRL

5780 5780 = = 0.152 CRL 1000 × 38

(ii) For the FW rectifier,  1  Vm = Vdc + I dc    4 fC   1  500 × 10 −3 Or Vdc = Vm − I dc  = 24 − 2.5 = 21.5 V  = 24 − 4 × 50 × 1000 × 10 −6  4 fC  RL =

Vdc 21.5 = = 43 Ω I L 500 × 10 −3 1

g =

= 4 3 fCRL

2890 2890 = = 0.067 CRL 1000 × 43

148

Electronic Devices and Circuits

Example 3.20 A transformer, rectifier, and filter arrangement has a no-load voltage of 100 V and its voltage regulation is specified as 5 percent. What is its full-load voltage? Solution: Voltage regulation can be also specified as follows: % regulation =

VNL −VFL ×100 VNL

 V  5 = 1 − FL  × 100  100 

1−

VFL = 0.05 100

VFL = 1 − 0.05 = 0.95 100

∴VFL = 100 × 0.95 = 95 V

Summary • A PN junction diode can be used in many applications; one application considered here is in rectifiers. • A simple HW rectifier has a g of 1.21, which says that the ripple is large. But FW rectifier has a g of 0.48, which says that the ripple in FW rectifier is relatively small. • A bridge rectifier is used to eliminate the need for a center-tapped transformer. • Filters are used to reduce the ripple in the load. • Though an inductor filter reduces the ripple appreciably, it is effective only at high-load currents. • A capacitor filter also reduces the ripple appreciably, but it is effective only at low-load currents. • An LC- or L-type filter, which is a combination of L- and C-type filters, can be used to reduce ripple, and g can be made independent of load current or load resistance. • The diode used in a half-wave rectifier and in bridge rectifier should have a PIV of Vm. • The diode used in an FW rectifier should have a PIV of 2Vm. • Multiple filters such as LC or CLC filters are filters connected in tandem to effectively reduce the ripple.

multiple ChoiCe QueStionS 1. The dc and rms components of currents in a HW rectifier are given by the relations (a)

Im I and m 2 p

(b)

Im I and m p 2

(c)

2I m 2I m and p p

(d)

Im 2I m and 2p 2

2. The values of g, TUF, and h of a HW rectifier, in the same order are (a) 1.21, 0.287, and 40.6 (b) 0.48, 0.363, and 81.2 (c) 0.48, 0.363, and 40.6 (d) 1.21, 0.287, and 81.2 3. The values of g, TUF, and h of a FW rectifier, in the same order are (a) 1.21, 0.287, and 40.6 (b) 0.48, 0.693, and 81.2 (c) 0.48, 0.363, and 40.6 (d) 1.21, 0.287, and 81.2

Rectifiers and Filters

149

4. A HW rectifier circuit gives an output dc voltage of 10 V at 0 load current. When the full load of 100 mA is drawn, the output dc voltage falls to 9.5 V. The percentage regulation is (a) 50% (b) 5% (c) 2.5% (d) 55% 5. A transformer with a secondary voltage of 100 V (rms) is used in a FW rectifier circuit using a C filter. The PIV of the diode should at least be (a) 282.8 V (b) 600 V (c) 110 V (d) 141.4 V 6. The ripple in a rectifier circuit using an inductor filter (a) increases with increasing load current (b) decreases with increasing load current (c) remains unaltered with variations in load current (d) None of the above 7. The ripple in a rectifier circuit employing a capacitor filter (a) increases with increasing load current (b) decreases with decreasing load current (c) remains unaltered with variations in load current (d) None of the above 8. The ripple in a rectifier circuit employing an LC filter (a) increases with increasing load current (b) decreases with increasing load current (c) remains unaltered with variations in load current (d) None of the above 9. A bleeder resistance RB is used in association with an LC filter, to ensure (a) good regulation (b) poor regulation (c) 50% regulation (d) 100% regulation 10. Multiple L-section filters are used to (a) make g as small as possible (b) make g as large as possible (c) to reduce the output dc voltage (d) None of the above 11. The minimum frequency of the ripple component present in the output of HW and FW rectifiers, in same order, are (a) 50c/s and 50c/s (b) 50c/s and 100c/s (c) 100c/s and 100c/s (d) 100 and 50c/s

Short anSwer QueStionS 1. List three main limitations of a half-wave rectifier. 2. What are the advantages of FW rectifier over a HW rectifier? 3. What is the PIV of a diode in a rectifier circuit? What is its value in a HW rectifier, FW rectifier, and bridge rectifier? 4. What are the values of g for a HW rectifier and FW rectifier without filter? 5. What is ripple in a rectifier? Explain a simple method to minimize the ripple.

150 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.

Electronic Devices and Circuits

What is meant by transformer utilization factor? What is form factor? What is meant by diode stacking? Name two main advantages of the bridge rectifier over the conventional FW rectifier. What is its disadvantage? Justify that an inductor filter is better used to reduce ripple when the load current is large. Justify that capacitor filter is better used to reduce ripple when the load current is small. What is the advantage of an LC filter when compared to simple L and C filters? What is a critical inductance? What is a bleeder resistance? Why are multiple filters used?

long anSwer QueStionS For a HW rectifier, derive the expressions for Idc, Irms, Pi, Pdc, h, TUF, and g. For a FW rectifier, derive the expressions for Idc, Irms, Pi, Pdc, h, TUF, and g. For a FW bridge rectifier, derive the expressions for Idc, Irms, Pi, Pdc, h, TUF, and g. Derive the expression for g of HW rectifier with inductor filter. Draw the waveforms. Derive the expression for g of FW rectifier with inductor filter. Draw the waveforms. Derive the expression for g of HW rectifier with capacitor filter. Draw the waveforms. Derive the expression for g of FW rectifier with capacitor filter. Draw the waveforms. Draw the circuit of a FW rectifier with LC filter and explain its working. Calculate its g . What is meant by critical inductance? Why is a bleeder resistance used in the circuit? 9. Explain the need to cascade filters. Draw the circuit of an FW rectifier using two cascaded sections of LC filters and calculate its ripple factor. 10. Write short notes on (a) line and load regulation in a power supply (b) PIV of diodes used in HW and FW rectifier circuits 1. 2. 3. 4. 5. 6. 7. 8.

unSolved problemS 1. A center-tapped transformer having 100-0-100 V (rms) is used in a full-wave rectifier. The diode has a resistance of 10 Ω and the load resistance is 90 Ω. Calculate (i) Im, (ii) Idc, (iii) Idc through each diode, (iv) Pdc, (v) h, (vi) % regulation, and (vii) PIV of each diode. 2. A transformer having a secondary voltage of 100 V(rms) is used in a full-wave bridge rectifier. The diode has a resistance of 10 Ω and the load resistance is 90 Ω. Calculate (i) Im, (ii) Idc, (iii) Idc through each diode, (iv) Pdc, (v) h, (vi) % regulation, and (vii) PIV of each diode. 3. A FW rectifier with a capacitor filter having C = 50 µF, has a peak output voltage of 50 V and RL = 1 kΩ. Find (a) I dc ,(b) Vdc , (c) ripple voltage, and (d) g. The supply frequency is 50 Hz. 4. A FW rectifier with C filter delivers a current of 100 mA at 50 V. f = 50 Hz and C = 50 μF. Find (a) the peak secondary voltage of the transformer and (b) g. 5. A FW rectifier with C-type filter supplies a dc current of 50 mA at 25 V. The supply frequency is 50 Hz. Allowed ripple is 10 percent. Calculate C. 6. Determine the component values of CLC filter for Vdc = 20 V, I L = 500 mA, and g p = 2%.

4

TRANSISTOR CHARACTERISTICS

Learning objectives After reading this chapter, the reader will be able to      

4.1

Understand the working bipolar junction transistors (BJTs) Appreciate the methods of biasing BJTs Realize the three basic configurations of BJTs, namely, CE, CB, and CC configurations and obtain the input and output characteristics Derive the expressions for the current gain in each of the configurations and obtain their inter-relationship Derive the analytical expressions to explain the output characteristic in the CE configuration, using the Ebers–Moll model Understand the working of a phototransistor

JUNCTION TRANSISTOR

A bipolar junction transistor (BJT) that is commonly known as transistor is a three-terminal device. These three terminals are identified as emitter, base, and collector. The basic construction of NPN and PNP transistors is shown in Figure 4.1, and their schematic representations are shown in Figure 4.2. Emitter, E

N

P

Collector, C

N

Emitter, E

P

Base, B

N

P

Collector, C

Base, B

Figure 4.1 The NPN and PNP transistors

E

C

B

E

C

B

Figure 4.2 Schematic representation of NPN and PNP transistors

A transistor has an emitter, E, base, B, and a collector C. Base is made very thin and the collector is the largest region. The emitter is highly doped from which charge carriers are injected into the base. The charge carriers are aided by the external field, and later they could diffuse into the

152

Electronic Devices and Circuits

collector region, constituting the current in the device. As can be seen from Figure 4.1, transistors are of two types: NPN transistors and PNP transistors. From the construction, it can be noted that the transistor consists of two PN junctions, which can be represented as two diodes, with anodes as common terminal, for NPN transistor and the cathodes as common terminal for a PNP transistor as shown in Figure 4.3. D1 K

D2

D1 A

A

D2 A

K

K E

C

E

C

B

B

NPN transistor

PNP transistor

Figure 4.3 Diode representation of transistors

Consider an NPN transistor. Let us assume JC -base-collector junction JE-emitter-base junction that the emitter and the collector regions have identical physical dimensions and Base doping concentration. Then, the transistor N-material is said to have symmetrical junctions. When no external voltage is applied, as the electron Emitter Collector P-material density is very high in the N-type emitter, P-material these majority charge carriers from the JC JE emitter diffuse into the P-type base and holes from the P-type base diffuse into the N-type emitter. The net result is concentration of Barrier potential electrons on the P-side of the junction and concentration of holes on the N-side of the Figure 4.4 Potential distribution in an unbiased transistor junction, which prevents further migration of electrons and holes to either side of the junction. There exist barrier potentials, whose height is the same at the base–emitter junction, JE, and base–collector junction, JC, as shown in Figure 4.4. The minority carrier concentration in the open-circuited PNP transistor is shown in Figure 4.5. The barrier potential, also called cut-in voltage, Vg , is typically 0.1 V for Ge and 0.5 V for Si. npo–minority carrier (electron) concentration in the P-type emitter and collector at equilibrium pno–minority carrier (hole) concentration in the N-type base at equilibrium Minority carrier concentration pno npo

npo

N-type base

P-type emitter

P-type collector JE

JC

Figure 4.5 Minority carrier concentration in an open-circuited PNP transistor at equilibrium

Transistor Characteristics

153

For the current to flow in the device (for the device to conduct or to be in the ON state), the base–emitter diode (called the emitter diode) is to be forward biased by a voltage more than Vg , and the base–collector diode (called the collector diode) is reverse biased, in which case the transistor is said to be in the active region, as depicted in Figure 4.6.

IE P

N

P

+

C

E

IC

IE

IC

B

VEB

IB −

VEB

IB VCB

RL

VO −

−

VEB

VCB

+

+

VCC

Figure 4.6 Biasing a PNP transistor in the active region

Let VEB be the forward-bias voltage applied between the base and emitter terminals, and let Vg be the barrier potential. By the application of the forward-bias voltage, the height of the barrier at JE is reduced to Vg − | VEB | . LetVCC be the reverse-bias voltage applied to the collector diode. The voltage across the collector and base terminals isVCB . The collector junction barrier voltage as a result of the reverse-bias voltageVCB . is Vg + | VCB | , as shown in Figure 4.7, which increases the potential barrier. The dotted line depicts the situation as shown in Figure 4.5.

V

Base width, WB N-type base

P-type emitter

Vg − VEB Vg

VEB JE Vg + VCB Emitter junction barrier

VCB

P-type collector JC Collector junction barrier

Figure 4.7 Potential variation at the junctions in a PNP transistor biased in the active region

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Electronic Devices and Circuits

As a result of the application of the forward-bias voltage, the height of the barrier at JE is reduced to Vg − | VEB | , which facilitates injection of holes from P-type emitter into the N-type base. The holes in the base region are the minority carriers. The concentration of these holes in the N-type base, pn is the maximum near the junction and their concentration decreases away from the junction (Figure 4.8). Similarly, electrons from the N-type base are injected into the P-type emitter, which are now minority carriers in the emitter. Once again, it can be noted that the concentration of these electrons in the P-type emitter, np is the maximum near the junction, and their concentration decreases away from the junction. The excess holes in the base region diffuse to the collector junction. As the electric field intensity at JC is large ( = ( −dV ) / dx >> 0 ) , the holes are accelerated across the junction, and are therefore collected by the collector. Since the collector junction is reverse biased, the electron concentration np increases away from the junction, JC. The dotted lines depict the situation in an unbiased transistor as shown in Figure 4.5. Minority carrier concentration

pn

np pno

np

npo

npo

WB P-type emitter

JE

N-type base

JC

P-type collector

Figure 4.8 Minority carrier concentration in a PNP transistor biased in the active region

4.2 TRANSISTOR CURRENT COMPONENTS The current components in a PNP transistor biased in the active region are shown in Figure 4.9. As the base–emitter junction is forward biased, holes from the P-type emitter are injected into the N-type base. This component of emitter current is called IpE. Similarly, electrons from the N-type base are injected into the P-type emitter. This component of emitter current is called InE. Therefore, the total emitter current IE is I E = I pE + I nE

(4.1)

But in a commercial transistor, the emitter is heavily doped when compared to the base. Therefore, I nE I B( min ) Hence, the transistor is in saturation.

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Electronic Devices and Circuits

Summary • A transistor is said to be in the active region (class A operation), when the base–emitter diode is forward biased and the base–collector diode is reverse biased. • A transistor is said to be in the saturation region (ON switch), when the base–emitter as well as the base–collector diodes are forward biased. • A transistor is said to be in the cut-off region (OFF switch), when the base–emitter as well as the base– collector diodes are reverse biased.   a h • The current gain in CB configuration is a ( = hFB ) , that in the CE configuration is b  hFE = = FB 1 − a 1 − hFB   and in the CE configuration is g = (1 + hFE ) . • The leakage current, ICEO in CE configuration is (1 + b dc ) times larger than the leakage current, ICO in CB configuration. Further, ICO gets doubled for every 10°C rise in temperature • The base width decreases with increasing reverse-bias voltage, VCB at the collector junction. This effect is called base width modulation or Early Effect. • The effective base width W ′ practically reduces to zero, when the reverse-bias voltage on the collector diode is increased beyond a limit. At this, the collector voltage now can be seen to have reached through the base region, resulting in the emitter barrier voltage to be reduced from Vg to V ′ This phenomenon is called reach through or punch through. • The Ebers–Moll equivalent circuit of the transistor analytically explains the characteristics of the transistor in the CE mode.

multiple ChoiCe Questions 1. When forward–forward bias is provided in a transistor, then the transistor is said to be in (a) active region (b) saturation region (c) cut-off region (d) none of these 2. When forward–reverse bias is provided in a transistor, then the transistor is said to be in (a) active region (b) saturation region (c) cut-off region (d) none of these 3. When reverse–reverse bias is provided in a transistor, then the transistor is said to be in (a) active region (b) saturation region (c) cut-off region (d) none of these 4. The current gain in the CB configuration in terms of the current gain in the CE configuration is given by (a) hFB = (c)

hFE 1 + hFE

1 + hFE hFE

5. The current gain in the CE configuration is given by h (a) hFE = FB 1 + hFB (c)

1 + hFB hFB

(b) hFB = (d)

1 − hFE hFE

(b) hFE = (d)

hFE 1 − hFE

hFB 1 − hFB

1 − hFB hFB

Transistor Characteristics

6. The current gain in the CC configuration is given by (a) hFC = 1 + hFE (c) hFC = 1 − hFB

193

(b) hFC = 1 + hFB (d) hFC = 1 − hFE

7. The current gain in the CB configuration is 0.98. Then, the current gain in the CE configuration is (a) 149 (b) 49 (c) 100 (d) 9.8 8. The current gain in the CE configuration is 50. The, the current gain in the CB configuration is (a) 98 (b) 0.98 (c) 100 (d) 9.8 9. The current gain in the CE configuration is 49. Then, the current gain in the CC configuration is (a) 149 (b) 150 (c) 50 (d) 0.49 10. The current gain in the CB configuration is 0.99. Then, the current gain in the CC configuration is (a) 100 (b) 50 (c) 49 (d) 9.9 11. If I CO = 2µA, I EO = 1.62 µA , and a N = 0.99 , then a I is (a) 0.99 (c) 1.99

(b) 0.8 (d) 99

12. The base width decreases with increasing reverse-bias voltage, VCB at the collector junction. This effect is called (a) avalanche multiplication (b) reach through (c) Early effect (d) none of these 13. The effective base width W ′ reduces to zero, when the reverse-bias voltage on the collector diode is increased beyond a limit. This phenomenon is called (a) go through (b) avalanche multiplication (c) punch through (d) none of these 14. If VCB = 40,VCBO (max) = 50 , then M n for n = 2 is (a) 2.78 (c) 0.278

(b) 27.8 (d) 278

15. If VCBO (max) = 50 V, b dc = 50 , and n = 2 , then VCEO(max) is (a) 7.07 V (b) 1.88 V (c) 188 V (d) 0.188 V

Short answer Questions 1. 2. 3. 4. 5. 6. 7. 8.

A transistor is called a bipolar device. Why? Why is the base made very thin? When is a transistor said to be in the active region? A transistor is a current-controlled device. Justify the statement. Why is a Silicon transistor preferred over a Germanium transistor? What are the three basic transistor configurations? What is a dc ? What is b dc ?

194

9. 10. 11. 12. 13. 14. 15. 16.

Electronic Devices and Circuits

Specify the interrelationship between a dc and b dc . Of the three transistor configurations, which configuration has the maximum current gain? What are the two mechanisms by which breakdown may occur in a transistor? What is reach through or punch through in a transistor? How does current increase in the transistor when breakdown occurs due to avalanche multiplication? What is meant by the operating point in a transistor circuit? What is thermal runaway? What is Early effect or base width modulation?

Long answer Questions 1. What are the three basic configurations of a transistor? Describe the procedure to plot the input and output characteristics of transistor in CE mode. Clearly indicate active, saturation, and cut-off regions on the output curves. 2. Obtain the interrelationship between the current gains in the three basic transistor configurations. 3. Draw the equivalent circuit of the transistor in terms of Ebers–Moll parameters and explain with the help of relevant relations the analytical procedure to plot the output characteristics of an NPN transistor. 4. Write short notes on (a) Early effect (b) reach through 5. Explain the principle of working of a phototransistor.

unsolved problems 1. For Germanium transistor, b dc = 50, I CO = I CBO = 5 µA and I B = 100 µA . Calculate a dc , I C , and IE. 2. A transistor has IE = 10 mA, adc = 0.99, ICO = 5 µA. Determine IC, IB bdc and ICEO. 3. For the Si transistor in Figure 4.48, the reverse saturation current is 0.5 µA at 25°C. VBB = 10 V. Determine the value of RB for the transistor to be OFF at 100°C. 4. In the circuit shown in Figure 4.45, Si transistor is used with VCC = 12 V, RC = 1 kΩ, RB = 500 kΩ, and VCE = 8 V. Determine the transistor currents and VCB. 5. In a CE configuration, VCC = 9V and when a resistance RC of 1 kΩ is connected in series with the collector to VCC, it is found that the drop RC across RC is 3 V. If a dc = 0.98 , find (i) VCE and ICO (ii) I B . 6. In a CE circuit, VCC = 10 V, RC = 1 kW. When + RB the transistor is OFF, its collector current is VBE − 100 nA, and when the transistor is ON and in VBB VCE saturation, VCE = 0.2 V. Determine the power 10 V dissipation PD (i) when the transistor is in saturation, (ii) when the transistor is OFF, and Figure 4.48 Circuit for Problem 3 (iii) when VCE = 5 V.

5

TRANSISTOR BIASING AND THERMAL STABILIZATION

Learning objectives After reading this chapter, the reader will be able to    

5.1

Understand the relevance of the transistor characteristics on the biasing of a bipolar junction transistor Realize the three basic configurations of BJTs, namely, CE, CB, and CC configurations Understand the various methods of biasing transistors, namely, fixed bias, self-bias, voltage divider bias, and collector feedback bias Appreciate the need for bias stabilization

INTRODUCTION

A transistor can be used as a switch, or it can also be used either as a linear or as a nonlinear circuit element. To accomplish this, it becomes necessary to set the dc conditions in the circuit. Establishing the relevant dc conditions in the circuit is called biasing. Whenever a transistor is to be used for any application, three major parameters are to be borne in mind: (i) the maximum permissible collector current, IC(max), (ii) the maximum VCE, and (iii) the dissipation in the device, PD(max).

5.2 THE THREE METHODS OF BIASING A TRANSISTOR Basically, a transistor can be either used as a switch or as a linear or non-linear circuit element. There are three methods of biasing a transistor, and they are explained below.

5.2.1 Forward–Forward Biasing This means both the emitter and the collector diodes are forward biased, in which case the transistor is said to be in saturation. For all practical purposes, VCE = 0. Then, the resistance between the collector and the emitter terminals is ideally zero. We may consider the transistor as a closed switch or ON switch (Figure 5.1). As VBE = 0.7 V, the emitter diode is forward biased. In addition, the base is positive with respect to the collector by 0.5 V. Hence, the collector diode is also forward biased.

196

Electronic Devices and Circuits

IC(sat) E

N

P

+

C

N

IB

VCE = 0.2 V

B

+ RB

VBB

VCC

RL

− −

VBE = 0.7 V

IE VCC

VBB

Figure 5.1 Forward–forward bias

5.2.2 Reverse–Reverse Biasing This means that both the emitter and the collector diodes are reverse biased, in which case the transistor is said to be in the OFF state, that is, IC = 0. Since IC ≈ 0, for all practical purposes VCE = VCC, the supply voltage. Then, the resistance between the collector and emitter terminals is ideally infinity. We may consider the transistor as an open switch or OFF switch (Figure 5.2). As VBE is negative, the emitter diode is reverse biased. Since VCB is positive, the collector diode is also reverse biased. IC = 0

VBE > IB

G

Figure 5.14 Emitter bias circuit

VCC = IBRB + VBE + ICRE

VCC − VBE − I C RE 15 − 0.6 − 0.1 × 103 × 12.5 × 10 −3 = = 52.6 kΩ ≈ 50 kΩ IB 0.25 × 10 −3

RB = Calculation of S: Here,

RB 50 = = 500 RE 0.1 Using Eqn. (5.20), S=

(1 + b dc ) (1 + 50) = 51 = 51 = 46.36 =  1  1 + 50 1 + 0.1   1 + 50   1   1 + 500  501 1 + b dc    1 + RB   RE 

We see that without RE, S = 51 and with RE of 0.1kΩ, S = 46.36. The poor value of S is because RB = 500 , which is very large. RE Let us calculate S for (i)

RB = 0, S = 1 RE

RB varying from 0 to 1000: RE

Transistor Biasing and Thermal Stabilization

RB = 1, S = (ii) RE

(iii)

207

51 =2 50 1+ 1+1

RB 51 = 10, S = = 9.197 50 RE 1+ 1 + 10

(iv)

RB = 25, S = RE

51 = 17.45 50 1+ 1 + 25

(v)

RB = 50, S = RE

51 = 25.75 50 1+ 1 + 50

(vi)

RB = 100, S = RE

51 = 34.11 50 1+ 1 + 100

(vii)

RB = 250, S = RE

51 = 42.53 50 1+ 1 + 250

(viii)

RB = 500, S = RE

51 = 46.36 50 1+ 1 + 500

(ix)

RB = 750, S = RE

51 = 47.84 50 1+ 1 + 750

(x)

RB = 1000, S = RE

(xi) As

51 = 48.57 50 1+ 1 + 1000

RB increases further, S → (b + 1) = 51 RE

RB is small (Figure 5.15). RE Keeping RB constant, if RE is increased, to set the same Q-point, VCC needs to be increased, which From the above calculations, it is obvious that S is small when

is unwarranted.

208

Electronic Devices and Circuits S

51 48.57 47.84 46.36 42.53 34.11 25.75 17.45 9.2 1

S = 51

RB/RE

0 1 10 25 50 100 250 500 750 1000

Figure 5.15 Variation of S with

RB RE

Calculation of S′: From Eqn. (5.6), S′ =

dI C , I , b constant. dVBE CO dc

And from Eqn. (5.18), VCC = I B ( RB + RE ) + VBE + I C RE

(5.22)

And also from Eqn. (5.3), IC = bdc IB + ICO (1 + bdc) From Eqn. (5.3), IB =

I C − I CO (1 + bdc )

(5.23)

bdc

Substituting Eqn. (5.23) in Eqn. (5.22) and after simplification,   ( R + RE ) ( R + RE ) (1 + bdc ) VCC =  B + RE  I C − B I CO + VBE bdc  bdc  Therefore, VBE = VCC +

( RB + RE ) (1 + bdc ) bdc

I CO −

Assuming ICO and bdc to be constant, from Eqn. (5.24), R + RE (1 + bdc ) dVBE =− B dI C bdc

RB + RE (1 + bdc ) bdc

IC

(5.24)

Transistor Biasing and Thermal Stabilization

209

Therefore, S′ =

bdc dI C =− RB + (1 + bdc ) RE dVBE

(5.25)

But from Eqn. (5.20), S=

( RB + RE ) (1 + bdc ) RB + (1 + bdc ) RE

Multiplying and dividing Eqn. (5.25) by ( RB + RE ) (1 + bdc )  and using Eqn. (5.20),

S′ = −

(RB + RE ) (1 + bdc ) bdc × RB + (1 + bdc ) RE (RB + RE ) (1 + bdc ) S′ =

S′ =

If

− bdc S (RB + RE ) (1 + bdc ) − bdc S  R  (1 + bdc ) 1 + RB  RE  E

(5.26)

RB > 1. S′ can be minimized either by choosing RB or RE large and RB is chosen on base current requirement. Calculation of S″: From Eqn. (5.24), ∴VBE = VCC +

( RB + RE ) (1 + bdc ) bdc

I CO −

RB + RE (1 + bdc ) bdc

IC

210

Electronic Devices and Circuits

Let V1 =

( RB + RE ) (1 + bdc ) bdc

I CO = ( RB + RE ) I CO

since

(1 + bdc ) bdc

≈1

Hence,

VBE = VCC + V1 −

IC =

RB + RE (1 + bdc ) bdc

IC

bdc (VCC + V1 −VBE ) RB + RE (1 + bdc )

(5.29)

Keeping VBE and ICO constant, S ′′ =

dI C RB + RE (1 + bdc ) (VCC + V1 − VBE ) − bdc (VCC + V1 − VBE ) RE = 2 db RB + RE (1 + bdc )

Using Eqn. 5.29, S′′ =

(VCC +V1 −VBE ) ( RB + RE ) I C ( RB + RE ) = × 2 bdc RB + RE (1 + bdc ) RB + RE (1 + bdc ) 

Multiplying and dividing by (1+ bdc ),

S ′′ =

(1 + bdc ) (RB + RE ) IC × bdc (1 + bdc ) RB + RE (1 + bdc )

But,

S ′′ =

S=

( RB + RE ) (1 + bdc ) RB + (1 + bdc ) RE

S ′′ =

ICS bdc1 (1 + bdc 2 )

I C1S where bdc1 and bdc2 are the values of bdc at two different temperatures. bdc1 (1 + bdc 2 )

(5.30)

Transistor Biasing and Thermal Stabilization

211

5.4.3 Collector-to-Base Bias or Collector Feedback Bias The CE configuration with collector-to-base bias is shown in VCC Figure 5.16. In this circuit too, the feedback is provided from collector IB + IC RL to base. As a result, this arrangement should give better RB thermal stability when compared to simple fixed bias + arrangement. Stability of operating point means ICQ and VCEQ IB VCE should remain unaltered with temperature variations. In this + arrangement, if the temperature increases, IC increases and the − − drop across RL increases, which will result in reduced VCE. As VBE V −VBE VCE I B = CE ≈ , decreases. As IB decreases, IC decreases, RB RB G thereby reducing the drop across RL. VCE is brought back to the Figure 5.16 CE configuration with desired value, ensuring the stability of the operating point. On collector-to-base bias the other hand, if the device is replaced by another device, which has a slightly smaller value of bdc (= hFE), IC decreases, resulting in increase in VCE. This in turn increases IB, and hence IC. The drop across RL now increases, once again bringing back IC and VCE to the desired values. Using Figure 5.16 and writing the KVL equation, VCC = ( I B + I C ) RL + I B RB + VBE

(5.31)

From Eqn. (5.31), IB =

VCC −VBE − I C RL RB + RL

(5.32)

dI B RL =− RB + RL dI C

(5.33)

We have from Eqn. (5.10),

(1 + bdc )

S=

1 − bdc

(5.34)

dI B dI C

Substituting Eqn. (5.33) in Eqn. (5.34), S=

If

(1 + bdc )  RL  1 + bdc    RB + RL 

=

(1 + bdc )   1 1 + bdc   1 + RB  R L 

     

RB R is small, S is small. If B becomes large, S approaches (1 + bdc). RL RL

(5.35)

212

Electronic Devices and Circuits

Example 5.3 In the collector-to-base bias circuit shown in Figure 5.16, Si transistor is used. VCC = 10 V, VCEQ = 5 V, and ICQ = 2 mA. If bdc = 80, (i) calculate the values of RL, RB, and S; and (ii) if in the above circuit, all other values remain unaltered, except for bdc which now changes to 40 when this transistor is replaced by another, find out the new operating point. Solution: (i) From Figure 5.16, RL =

VCC − VCEQ I CQ

I BQ =

I CQ b dc

=

=

10 − 5 = 2.5 kΩ 2

2 = 0.025 mA 80

We have from Eqn. (5.31),

(

)

VCC = I BQ + I CQ RL + I BQ RB + VBE IBQ (RL + RB) = VCC − VBE − ICQRL

(RL + RB ) =

VCC − VBE − I CQ RL I BQ

=

10 − 0.6 − 5 4.4 = = 176 kΩ 0.025 0.025

RB = (RL + RB)−RL = 176 − 2.5=173.5 kΩ. From Eqn. (5.35),

S=

(1 + b dc )    1  1 + b dc    1 + RB   RL 

=

81 1 + 80 = = 37.92  1 + 1.136  1   1 + 80  173.5    1 + 2.5 

(ii) Equation (5.31) can be written as follows:  I  VCC = I B 1 + C  RL + I B RB + VBE  IB 

VCC = IB(1 + bdc) RL + IBRB + VBE IB =

VCC − VBE 10 − 0.6 9.4 = = 0.034 mA = RB + (1 + b dc ) RL 173.5 + 41 × 2.5 276

Transistor Biasing and Thermal Stabilization

213

IC = bdc IB = 40 × 0.034 = 1.362 mA. VCE = VCC − (IC + IB)RL = 10 − (1.362 + 0.034)2.5 =10 − 3.49 = 6.51 V. The collector-to-base bias circuit, when used in an amplifier, would produce negative feedback under ac conditions too, thereby reducing the output. This could be major limitation of this circuit.

5.4.4 Voltage Divider Bias or Self-Bias If in a biasing circuit, a potential divider network comprising R1 and R2 is incorporated so as to eliminate the need for a second source, and a resistance RE is included in the emitter lead to the ground terminal, the resulting biasing arrangement is called a voltage divider bias or self-bias (Figure 5.17). VCC

VCC

IC

R1

IB

+

VCE +

+ VBE R2

−

VBE

Vth

IB

+

IB

Rth

VCE

−

RL

IC

RL

−

−

IB

IC

IC RE

RE

G G (a)

(b)

Figure 5.17 Voltage divider bias

The potential divider network derives the necessary forward-bias voltage between the base and the emitter terminals. Thevenizing the circuit in Figure 5.17(a) results in the circuit in Figure 5.17(b). Vth = VCC

R2 R1 + R2

and Rth = R1 || R2 =

R1R2 R1 + R2

(5.36)

From the circuit in Figure 5.17(b), Vth = I B Rth + ( I B + I C ) RE + VBE

(5.37)

214

Electronic Devices and Circuits

Vth =

IC I Rth + C RE + I C RE + VBE bdc bdc

IC Rth + (1 + bdc ) RE  = Vth − VBE bdc 

IC =

(Vth −VBE ) bdc Rth + (1 + bdc ) RE 

(5.38)

And VCE ≈ VCC − I C ( RL + RE )

(5.39)

since IB is small. From Eqn. (5.37), I B ( Rth + RE ) + I C RE = Vth −VBE

dI B RE =− Rth + RE dI C

(5.40)

Substituting Eqn. (5.40) in Eqn. (5.10),

S=

If

(1 + bdc )  RE  1 + b dc    Rth + RE 

=

(1 + bdc )

(5.41)

   1   1 + b dc   Rth + 1   R  E 

Rth R >1. If in Eqn. (5.42),

RE = 1 , then Rth

Rth

Since, IC is independent of hFE, the Q-point is stable. If RB is decreased, then the effective input resistance decreases, A smaller input resistance loads the generator and in turn reduces the gain, when used as an amplifier. Alternatively, if RE is increased, the voltage drop across it increases, thereby increasing the feedback signal, and this in turn reduces the gain. To overcome this problem, a large capacitor, CE (typically of the order of 100 µF) which ideally behaves as a short circuit at the lowest frequeny of operation (say, 50 c/s) is connected in shunt with RE as shown in Figure 5.18. VCC

IC RL R1

+ IB VCE

+ VBE

−

−

+ V2

R2

IB

IC

+ CE

− RE

−

G

Figure 5.18 CE connected in shunt with RE

Example 5.4 In the voltage divider bias circuit shown in Figure 5.17, Si trannsistor with hFB = 0.99 is used. VCC = 20 V, RE = 1.5 kΩ, RC = 2 kΩ, R1 = 50 kΩ, R2 = 20 kΩ, VC = 0.7 V, and VCE(sat) = 0.2 V. (i) Determine the coordinates of the Q-point and (ii) calculate the stability factor, S.

216

Electronic Devices and Circuits

Solution: Given hFB = 0.99. Therefore, hFE =

hFB 0.99 = = 99 1 − hFB 1 − 0.99

From Figure 5.17, (i) Vth = VCC

R2 20 = 20 × = 5.71 V R1 + R2 20 + 50

Rth = R1 || R2 =

20 × 50 = = 14.28 kΩ 20 + 50

The circuit in Figure 5.17 is redrawn as in Figure 5.19. VCC 20 V

RC = 2

IC Rth = 14.28

IB +

VBE−

Vth = 5.71 V

+ VCE −

IC IB RE = 1.5

Figure 5.19 Redrawn circuit of Figure 5.17 with component values as given in Example 5.4

From Figure 5.19, writing the KVL equation of the base loop, Vth = IBRth + VBE + (IB + IC)RE =

 IC 1 Rth + I C 1 + hFE h  FE

 Rth (1 + hFE )   + RE   RE + VBE = VBE + I C  hFE   hFE 

 14.28 100 × 1.5  5.01 ∴ 5.71 = 0.7 + I C  + = 3.02 mA  and I C = 99 99 1.659   IE = IB + IC ≈ IC since IB is small. VCE = VCC − IC(RC + RE) = 20 − 3.02(2 + 1.5) = 9.43 V Therefore, the coordinates of the Q-point are IC = 3.02 mA and VCE = 9.43 V

Transistor Biasing and Thermal Stabilization

217

(ii) Stability factor, S: From Eqn. (5.41), S=

(1 + bdc )    1   1 + bdc   Rth + 1  R   E 

(1 + 99 )

=

    1 1 + 99    1 + 14.28  1.5  

= 9.6

Example 5.5 Design the voltage divider bias circuit shown in Figure 5.17, to have VCE = 15 V and IC = 5 mA, given that VCC = 30 V, VBE = 0.7 V, hFE = 50, RC = 2 kΩ, and S ≤ 5. Solution: (i) To calculate RE: From Figure 5.17, VCC =VCE + IC(RC + RE) IC(RC + RE) = VCC − VCE = 30−15 = 15 V (RC + RE) =

15 = 3 kΩ 5

RE = (RC + RE) − RC = 3−2 = 1 kΩ

(ii) To calculate R1 and R2: Given S ≤ 5. We have S =

∴S =

1 + hFE  RE 1+   RE + Rth

  hFE 

where Rth = R1 / / R2

1 + 50  1  1 + 50    1 + Rth 

Hence, 5=

51(1 + Rth ) 51 + Rth

46 Rth = 204 Rth = 4.43 kΩ Normally, from experience, R2 is chosen as R2 ≤ 0.1 hFE RE = 0.1 × 50 × 1 = 5 kΩ Rth =

R1R2 R1 + R2

4.43 =

5R1 R1 + 5

R1 =

22.15 = 38.85 kΩ 0.57

218

Electronic Devices and Circuits

Example 5.6 For the voltage divider bias circuit shown in Figure 5.20, determine the values of RE, R1, R2, and RC, if the Q-point is to be loacted at IC = 5 mA, VCE = 12 V, and hFE = 50. Silicon transistor is used. Solution: (i) Calculation of RE: In the design, the approximation made is that VE =

VCC = 30 V

VCC 30 = =3 V 10 10 IC = 5 mV

RL

Given IC = 5 mA = IE R1

V 3 ∴ RE = E = = 600 Ω IE 5

+ IB VCE = 12 V

VB +

+

(ii) Calculation of RL:

VBE R2

V − VCE − VE 30 − 12 − 3 15 RL = CC = = = 3 kΩ IC 5 5

(iii) Calculation of R2: The approximation acceptable to calculate R2 is

IB

−

−

IC

+ VE

−

RE − G

Figure 5.20 Biasing circuit of Example 5.6

R2 ≤ 0.1 hFE RE R2 = 0.1 × 50 × 600 = 3 kΩ (iv) Calculation of R1: VB = VCC

R2 (R1 + R2 )

We have VB = VE + VBE = 3 + 0.7 = 3.7 V

∴ 3.7 = 30 ×

3 R1 + 3

Choose R1 = 22 kΩ.

⇒

3.7 R1 = 78.9

⇒

R1 =

78.9 = 21.32 kΩ 3.7

Transistor Biasing and Thermal Stabilization

5.5

219

CB CONFIGURATION

The biasing of CB configuration using NPN and PNP devices is shown in Figures 5.21 and 5.22, respectively. +

+

IE

VEB −

RE

−

IC

VCB RC

VCC

VEE

Figure 5.21 Biasing an NPN transistor in CB

IE

IC

+

+ VEB

RE

VEE

−

−

VCB RC

VCC

Figure 5.22 Biasing a PNP transistor in CB

From Figures 5.21 and 5.22, it can be seen that the polarities of the supply voltages are exactly opposite, and also the directions of the currents. Except for this fact, the analysis of a PNP transistor circuit is precisely the same as the analysis of an NPN transistor. The output characteristics are shown in Figure 5.23. From Figure 5.23, it is evident that the collector current almost remains constant with variation of VCB. To locate the Q-point, we write down the KVL equation of the collector loop as indicated in Figure 5.21.

IC (mA) 20

20

17.5 15

15

12.5 Q

10

10

7.5

5

0

5

ICBO

IE

10

15

=

5 2.5 0 mA 20

VCB(V)

VCC = ICRC + VCB

Figure 5.23 Output characteristics of CB configuration

VCB VCC + RC RC

(5.44)

IC = −

220

Electronic Devices and Circuits

VCC . We locate these RC two points on the output characteristics and draw the load line. Now select IE = 10 mA. Then the coordinates of the Q-point are IC = 10 mA and VCB = 10 V. To draw the load line, set IC = 0, then VCB = VCC and set VCB = 0, then I C =

5.6

CC CONFIGURATION

Biasing of CC configuration using NPN and PNP devices is shown in Figures 5.24 and 5.25, respectively. IE VEB IB

−

−

+

VCE

VCC

− +

+

VCB VBB

Figure 5.24 Biasing a CC configuration using an NPN transistor IE VEB IB

+

−

VEC

+

VBB

+

VBC

VCC

− −

Figure 5.25 Biasing a CC configuration using a PNP transistor

For the CC configuration, it can be seen that the input current is IB and the output current is IE . As

IE = IC + IB

IE = IB(1 +

IC ) = IB(1 + hFE) IB IE = 1 + hFE = 1 + bdc IB

Thus CC configuration has the largest current gain.

(5.45)

Transistor Biasing and Thermal Stabilization

5.7

221

BIAS COMPENSATION

In the biasing circuits considered so far, the stability of the operating point was ensured by providing negative feedback in the biasing circuit. We shall see later that when a transistor is used as an amplifier, if negative feedback is used in the circuit, the gain of the amplifier gets reduced. To overcome this problem, a bypass capacitor is connected in shunt with RE, the resistance in emitter lead. However, no such arrangement can be incorporated in the collector to base bias circuit. The stability of the operating point can be achieved by providing compensating techniques, wherein circuit elements such as diodes, thermistors, and sensistors are connected in such a manner that any variation in leakage currents is nullified by an identical variation in these devices.

5.7.1 Diode Compensation One method of bias compensation is by using a diode as shown in Figure 5.26. VCC

IC

RL

+

R1 IB

VCE

VB

Q

+ + VD −

VBE

−

− IE

D

+ VR2

RE

R2

−

Figure 5.26 First method of diode compensation

From Figure 5.26, VB = VD + VR Therefore, IE = IC =

2

VD + VR2 −VBE RE

If, for any reason, VBE changes (by ± ∆VBE), then VD also changes in a similar manner (by ± ∆VD). V Thus, IC remains almost constant and is given as I C = R2 . RE The second method is to connect diode D between the base and the emitter terminals, and the diode voltage is also the same as VBE. As VBE reverse biases D, the current in it is IO, the reverse

222

Electronic Devices and Circuits

saturation current. If the diode D and the transistor Q are Si devices, ICO and IO vary identically, since the V − I characteristic of the diode is the same as the VBE − IC characteristic of the transistor. From Figure 5.27, I = IB + IO

or

(5.46)

IB = I − IO

Let there be an increase in temperature, which can increase ICO, resulting in an increase in IC. Since IO also changes as ICO, IO increases, resulting in decrease in IB. This in turn reduces IC to the original value, and hence ensures the stability of the operating point. The third method is to connect the diode D in the emitter lead as shown in Figure 5.28. The diode voltage VD is the same as VBE. The diode is connected such that VD and VBE are of opposite polarity. If VBE changes, VD also changes in a similar manner, thereby maintaining IC constant. VCC

I

VCC RL

ICO

IC

+

R IB

IB

VCE

Q

Q

VB

− D +

+ VBE IO

RL

Rs VBB

−

+

VBE−

+ VCE −

RE RD

IE

− VD +

−

Figure 5.27 Second method of diode compensation

D

VDD

Figure 5.28 Third method of diode compensation

5.7.2 Thermistor Compensation A thermistor is a temperature-sensing element that exhibits a large change in resistance proportional to a small change in temperature. Thermistors usually have negative temperature coefficient, which means that the resistance of the thermistor decreases as the temperature increases. In practice, the resistance decreases exponentially with the increase in temperature. As an approximation, if the relationship between resistance and temperature is linear, then ΔR = k ΔT where, ΔR is the change in resistance, ΔT is the change in temperature, and k is the temperature coefficient of resistance. Based on the sign of k, thermistors can be classified into two types: (i) If k is positive, the resistance increases with increasing temperature, and the device is called

223

Transistor Biasing and Thermal Stabilization

a positive temperature coefficient (PTC) thermistor or posistor. (ii) If k is negative, the resistance decreases with increasing temperature, and the device is called a negative temperature coefficient (NTC) thermistor. A thermistor with negative temperature coefficient can be used for bias compensation as shown in Figure 5.29. A thermistor with NTC is connected in shunt with R2. If the temperature remains unchanged, the voltage across R2 is V2. Then, the base-to-emitter voltage is VBE, base current is IB, collector current IC, and the collector to emitter voltage is VCE. If, however, the temperature increases, IC increases VCE decreases. As a result, the Q-point can be altered, despite bias stabilization using RE. But with the thermistor connected and as the temperature increases, RT decreases, the effective value of R2//RT is reduced, V2 is reduced, and therefore VBE, IB, IC are reduced (the reduced IC compensates for an increase in ICO) and VCE increases (brought back to the original value). Hence, the operating point remains unaltered.

VCC

IC

RL +

R1 IB

VCE

+ Thermistor with NTC

VBE

+

−

− IC +

IB V2

RT

R2

VE −

−

RE

Figure 5.29 Bias compensation using thermistor with NTC

5.7.3 Sensistor Compensation Sensistor is a resistor whose resistance increases with temperature, that is, the temperature coefficient is positive (e.g. 0.007/°C ). Sensistors are used in electronic circuits for compensating temperature. A bias compensation circuit using a sensistor is shown in Figure 5.30. A sensistor with PTC is connected in shunt with R1. If the temperature remains unchanged, the voltage across R1 is V1. Then, the base-to-emitter voltage is VBE, base current is IB, collector current IC, and the collector to emitter voltage is VCE. If, however, the temperature increases, IC increases and VCE decreases. As a result, the Q-point can be altered. But with sensistor connected, as temperature increases, RS increases, the effective value of R1//RS is increases, V1 is increased, and V2 is decreased. Therefore, VBE is decreased, IB is decreased, IC is reduced (the reduced IC compensates for changes in ICO, VBE, and bdc), and VCE increases (brought back to the original value). Hence, the operating point remains unaltered.

VCC

IC

+ Sensistor RS

RL R1 V1

+ IB

VCE

− + VBE

+

−

− IC +

IB V2 −

R2

VE −

RE

Figure 5.30 Bias compensation using a sensistor

224

5.8

Electronic Devices and Circuits

INTEGRATED CIRCUIT BIASING

In IC fabrication, resistors occupy more space. Hence, the biasing circuit shown in Figure 5.31, called the current mirror, is normally used. In this circuit, Q2 is used as a diode by connecting its collector to the base. Q1 and Q2 are identical transistors. Hence, IB1 = IB2 = IB

IC1 = IC2 = IC and b1 = b2 = b

Writing the KVL equation in the base–emitter loop of Q1 and Q2, VBE2 − VBE1 = 0 or VBE2 = VBE1 = VBE

VCC IR

R

IC1 RL

IC2 I Q2

Q1

+ IB1 VBE2 −

IB2

+ VBE1 −

Figure 5.31 IC biasing

IR, the reference current is determined as follows: IR =

VCC −VBE R

(5.47)

and I = I B1 + I B 2 = 2 I B

(5.48)

IR = I + IC2 = I + IC

(5.49)

Also,

Substituting Eqs (5.47) and (5.48) in Eqn. (5.49), 2  2+ b VCC − VBE = 2 I B + I C = I C  + 1 = I C  R b   b  Therefore,  b   VCC − VBE  IC =    R  2 + b  

(5.50)

Even if b changes by wide margins (say from 50 to 200), the first term in Eqn. (5.50) almost remains constant. If VCC, VBE remain stable, and if R is a precision resistor, IC is stable.

5.9

COMBINATION OF VOLTAGE DIVIDER AND COLLECTOR-TO-BASE BIAS

The circuit in Figure 5.32 is similar to the voltage divider bias circuit, except for the fact that R1 is returned to the collector of the transistor as in the case of collector–base bias circuit, instead of VCC. The circuit thus combines the collector-to-base bias arrangement and the voltage divider circuit. The resultant advantage is that it can provide better bias stability. The analysis and design are, by far, similar to the analysis and design of the voltage divider bias circuit. This circuit differs from the voltage divider bias circuit on two counts: (i) the voltage across R1 is (VC − VB),where VC and VB are the voltages at the collector and base nodes and (ii) the current through RL is (IC + I2).

Transistor Biasing and Thermal Stabilization

225

VCC

RL

+ VC I2

IC

R1 VCE VB

+ I2

VBE

−

−

IB

R2

IC

+ VE

RE −

Figure 5.32 Combined collector-to-base bias and voltage divider bias circuit

Example 5.7 Design the bias circuit shown in Figure 5.32. VCC = 24 V, VCE = 12 V, VE = 5 V, and IC = 5 mA. Solution: VE 5 = = 1 kΩ IC 5

RE =

VB = VBE + VE = 0.7 + 5 = 5.7 V Choose I 2 =

1 5 IC = = 0.5 mA 10 10 ∴R2 =

VB 5.7 = = 11.4 kΩ I 2 0.5

VC = VCE + VE = 12 + 5 = 17 V R1 =

RL =

VC − VB 17 − 5.7 = = 22.6 kΩ 0.5 I2

VCC − VC 24 − 17 = = 1.27 kΩ 5 + 0.5 IC + I2

226

5.10

Electronic Devices and Circuits

EMITTER CURRENT BIAS

The emitter current bias circuit shown in Figure 5.33 uses two separate sources for biasing the transistor: one is a VCC source and the other is a −VEE source. The base of the transistor is connected to the ground through R1. For all practical purposes, VB ≈ 0. This circuit can be represented as a voltage divider bias circuit with VB adjusted to 0.1 VBE, as shown in Figure 5.34. VCC VCC

+ RL

− IC VC

VBE IB

R1 IB

VCE VB = 0

VCE

+ −

−

+ VC IC

R1

+ VB

RL

VRL

+ +

VBE

IC VE

R2

IB

−

−

+

IC VE RE −

RE −

−VEE

−VEE

Figure 5.33 Emitter current bias circuit

Figure 5.34 Voltage divider bias equivalent of emitter current bias circuit

R1 is usually selected to have a voltage drop that is very much smaller than VBE. As a rule of thumb IB(max) R1 = 0.1 VBE. As the voltage at the base VB = 0, for the device to be in the active region, the voltage at the emitter should be VBE below zero level. From Figure 5.34, the voltage across RE = VEE − VBE The voltage at the collector, VC = VCC − VRL And VCE = VC − VBE since the voltage at the emitter is VBE.

5.11 THERMAL RESISTANCE Consider a transistor in which the junction temperature is TJ and the temperature of the air around the transistor (ambient temperature) is TA. The larger the power dissipated in the transistor, the larger the junction temperature. Therefore, (TJ − TA) ∝ PD ∴ (TJ − TA) = q PD where q is called the thermal resistance.

(5.51)

Transistor Biasing and Thermal Stabilization

PD =

227

TJ − TA q

(5.52)

TJ − TA °C/W PD

(5.53)

And q= Also TJ = TA + q PD

(5.54)

To improve the power-handling capacity of the transistor, the junction temperature should be quickly removed. This can be achieved by increasing the effective surface area of the transistor by using a heat sink, which is usually a finned, large, black metallic heat conducting device. The heat sink is placed in close contact with the transistor casing. Example 5.8 Determine PD that a transistor can safely dissipate in free air if TA = 25°C, TJ = 150°C, and qJA = 10°C/W. Solution: PD =

TJ − TA 150 − 25 = = 12.5 W q 10

Additional Solved Examples Example 5.9 In the fixed bias circuit shown in Figure 5.11, a Si transistor with bdc = 100 is used. VCC = 12 V, VBE = 0.7 V, RL = 3 kΩ, and RB = 500 kΩ. Draw the dc load line and locate the Q-point. Also find S. Solution: From Eqn. (5.2), IC = −

VCE VCC + RL RL

When IC = 0, VCE(cut-off) = VCC = 12 V V 12 When VCE = 0, I C (sat ) = CC = = 4 mA RL 3 The load line is drawn by locating these two points on the output characteristics, Figure 5.35. From Figure 5.11, IB =

VCC −VBE 12 − 0.7 = = 0.0226 mA RB 500

IC = IB bdc = 0.0226 × 100 = 2.26 mA Q

VCEQ = VCC − IC RL = 12 − 2.26 × 3 = 5.22 V

228

Electronic Devices and Circuits IC(sat) = 4 mA

Q-point

ICQ = 2.26 mA

Load line 0

VCEQ = 5.22 V

VCC = 12 V

Figure 5.35 Locating the Q-point

Stability factor S = (bdc + 1) = 101 Example 5.10 For the emitter bias circuit in Figure 5.36, RL = 2.5 kΩ, RE = 0.5 kΩ, and VCC = 24 V. Calculate the coordinates of the Q-point, if mid-point bias is provided. Determine RB. bdc = 100. Calculate S. VCC

Solution: When IC = 0, VCE = VCE(cut-off) = VCC = 24 V

IC RL

When VCE = 0, I C = I C ( sat )

VCC 24 = = = 8 mA RL + RE 2.5 + 0.5

RB

+

IB +

For mid-point bias, I CQ =

I C(sat) 2

= 4 mA

VBE IB

And

I BQ =

I CQ bdc

=

4 = 0.04 mA 100

IC RE

G

Since, IC ≈ IE

Figure 5.36 Emitter bias circuit

VCC = IBRB + VBE + ICRE RB =

−

VCE −

VCC − VBE − I C RE 24 − 0.7 − 0.5 × 103 × 4 × 10 −3 = = 532.5 kΩ ≈ 500 kΩ IB 0.04 × 10 −3

Calculation of S: Here, RB 500 = = 1000 RE 0.5

Transistor Biasing and Thermal Stabilization

229

Using Eqn. (5.20),

S=

(1 + bdc )    1  1 + bdc    1 + RB   RE 

=

(1 + 100) 1   1 + 100   1 + 1000 

=

101 101 = = 91.82 100 1 + 0.1 1+ 1001

Example 5.11 In the collector-to-base bias circuit shown in Figure 5.16, a Si transistor is used. VCC = 24 V, VCEQ = 10 V, and ICQ = 4 mA. If bdc = 50, (i) calculate the values of RL, RB, and S. (ii) If in the above circuit all other values remain unaltered, except for bdc which now changes to 100 when this transistor is replaced by another, find out the new operating point. Solution: (i) From Figure 5.16, RL =

VCC − VCEQ

I BQ =

I CQ

I CQ bdc

=

=

24 − 10 = 3.5 kΩ 4

4 = 0.08 mA 50

From Eqn. (5.31), VCC = (IBQ + ICQ)RL + IBQRB + VBE IBQ(RL + RB) = VCC − VBE − ICQRL

(RL + RB ) =

VCC − VBE − I CQ RL I BQ

=

24 − 0.7 − 4 × 3.5 9.3 = = 116.25 kΩ 0.08 0.08

RB = (RL + RB) − RL = 116.25 − 3.5 = 112.75 kΩ From Eqn. (5.35),

S=

(1 + bdc )   1 1 + bdc   1 + RB  R L 

     

=

1 + 50 51 = = 20.4  1 + 1.50    1 1 + 50   112 75 .  1 +  3.5  

230

Electronic Devices and Circuits

(ii) Equation (5.31) can be written as follows:  I  VCC = I B 1 + C  RL + I B RB + VBE  IB  VCC = IB(1 + bdc)RL + IBRB + VBE IB =

VCC − VBE 24 − 0.7 23.3 = = = 0.05 mA RB + (1 + b dc )RL 112.75 + 101 × 3.5 466.25 IC = bdcIB = 100 × 0.05 = 5 mA. VCE = VCC − (I C + IB)RL = 24 − (5 + 0.05)3.5 = 24−17.675= 6.325 V

Example 5.12 (i) Design the biasing circuit shown in Figure 5.37 if IC = 10 mA and VCE = 5.8 V. dI C . bdc = hFE = 100, VBE = 0.7 V, and VCC = 12 V; (ii) determine the thermal stability factor , K = dI CEO Solution: VCC

(i) VCE = 5.8 V RL =

VCC −VCE 12 − 5.8 = = 620 Ω IC 10

IC RL RB

IB =

+

V − VBE 12 − 0.7 RB = CC = = 113 kΩ IB 0.1 × 10 −3

(ii) We can write

+

IB

IC 10 = = 0.1 mA bdc 100

dI C dI C dI = × CO dI CEO dI CO dI CEO

VBE

−

VCE − IE

Figure 5.37 Fixed bias circuit

But, S=

∴

dI C dI CO

dI C dI = S × CO dI CEO dI CEO

dI CO 1 And also, we know that ICEO = (bdc + 1)ICO. Therefore, = and for the fixed bias dI b ( dc + 1) CEO circuit S = (bdc + 1) ∴

(bdc + 1) = 1 dI C S =K= = b 1 dI CEO + ( dc ) (bdc + 1)

Transistor Biasing and Thermal Stabilization

231

Example 5.13 For the collector–base bias circuit RL = 500 Ω, IC = 10 mA, bdc = 50, and VCC = 12 V. Determine RB, S, and K. Assume VBE = 0 Solution: VCC = (IB + IC)RL + IBRB + VBE I C 10 = = 0.2 mA b dc 50

IB =

ICRL = 10 × 0.5 = 5 V IBRL = 0.2 × 0.5 = 0.1 V

RB = S=

12 − 5 − 0.1 = 34.5 kΩ 0.2

(1 + b dc )    1  1 + b dc    1 + RB   RL  K=

=

51 1 + 50 = = 29.75   1 + 0.714 1   1 + 50  34.5    1 + 0.5 

29.75 S = = 0.58 ( b dc + 1) 51

Example 5.14 For the biasing circuit shown in Figure 5.11, VCC = 12 V, RB = 500 kΩ, and RC = 2 kΩ. Find the maximum and minimum levels of IC and VCE, if bdc(min) = 50 and bdc(max) = 200. Solution: IB =

VCC − VBE 12 − 0.7 = 0.0226 mA = RB 500 × 103

IC(min) = bdc(min) × IB = 50 × 0.0226 = 1.13 mA VCE(max) = VCC − IC(min)RL = 12 − 1.13 × 2 = 9.74 V IC(max) = bdc(max) × IB = 200 × 0.0226 = 4.52 mA VCE(min) = VCC − IC(max)RL = 12 − 4.52 × 2 = 2.96 V Example 5.15 For the collector-to-base bias circuit, VCC = 12 V, RB = 500 kΩ, and RL = 2 kΩ. Find the maximum and minimum levels of IC and VCE, if (i) bdc1 = 100, (ii) bdc2 = 150, and (iii) bdc3 = 200. Locate the Q-points on the dc load line. Solution: (i) I B1 =

VCC − VBE 12 − 0.7 = = 0.016 mA RB + (1 + b dc1 ) RL 500 + (1 + 100 ) 2

232

Electronic Devices and Circuits

IC1 = bdc1 × IB = 100 × 0.016 = 1.6 mA VCE1 = VCC − IC1 RL = 12 − 1.6 × 2 = 8.8 V (ii) I B2 =

VCC −VBE 12 − 0.7 = = 0.014 mA RB + (1 + bdc 2 ) RC 500 + (1 + 150 ) 2 IC2 = bdc2 × IB = 150 × 0.014 = 2.1 mA VCE2 = VCC − IC2 RL = 12 − 2.1 × 2 = 7.8 V

(iii) I B3 =

VCC −VBE 12 − 0.7 = = 0.012 mA RB + (1 + bdc 3 ) RC 500 + (1 + 200 ) 2 IC3 = bdc3 × IB = 200 × 0.012 = 2.4 mA VCE3 = VCC − IC3 RL = 12 − 2.4 × 2 = 7.2 V

The Q-points are located on the dc load line as shown in Figure 5.38. I C (sat ) =

VCC 12 = = 6 mA and VCE(cut-off) = VCC = 12 V RL 2 IC 6 mA DC load line

Q3

2.4 mA 2.1 mA

Q2

1.6 mA

Q1

0

7.2 V 7.8 V 8.8 V

12 V

VCE

Figure 5.38 Q-points for the bias circuit of Example 5.15

Example 5.16 In the voltage divider bias circuit shown in Figure 5.17, Si transistor with hFE = 100 is used. VCC = 30 V, RE = 10 kΩ, RC = 10 kΩ, R1 = 30 kΩ, R2 = 20 kΩ, and VBE = 0.7 V. (i) determine IE, IB, IC, and VCE; (ii) calculate the stability factor S. Solution: (i) From Figure 5.17, Vth = VCC

R2 20 = 30 × = 12 V R1 + R2 20 + 30

Rth = R1 / / R2 =

20 × 30 = 12 kΩ 20 + 30

Transistor Biasing and Thermal Stabilization

The circuit in Figure 5.17 is redrawn as in Figure 5.39. VCC = 30 V

RC = 10 kΩ

IC Rth = 12 kΩ

IB +

VBE−

Vth = 12 V

+ VCE −

IC IB RE = 10 kΩ

Figure 5.39 Redrawn circuit of Figure 5.17 with component values as given in Example 5.16

From Figure 5.39, writing the KVL equation of the base loop: Vth = IBRth + VBE + (IB + IC)RE Vth =

 IC 1 Rth + I C 1 + hFE  hFE

 Rth (1 + hFE )   + RE   RE + VBE = VBE + I C  hFE   hFE 

11.3  12 101× 10  ∴12 = 0.7 + I C  + = 1.10 mA  and I C = 10.22 100   100

IB =

I C 1.10 = = 0.011 mA hFE 100 IE = IB + IC = 1.1 + 0.011 = 1.111 mA

VCE = VCC − IC(RC + RE) = 30 − 1.1(10 + 10) = 8 V Therefore, the coordinates of the Q-point are IC = 1.1 mA and VCE = 8 V (ii) Stability factor, S: From Eqn. (5.41), S=

(1 + bdc )    1   1 + bdc   Rth + 1  R   E 

=

(1 + 100 )    1  1 + 100    1 + 12   10 

= 2.17

233

234

Electronic Devices and Circuits

Example 5.17 For the voltage divider biasing circuit, VCC = 16 V, RE = 1.5 kΩ, RC = 2 kΩ, R1 = 80 kΩ, R2 = 20 kΩ, and VBE = 0.7 V. (i) Determine the operating point when (a) bdc = 100 and (b) when bdc is doubled; (ii) comment on the stability of the operating with change in bdc. Solution: (i) From Figure 5.17, Vth = VCC

R2 20 = 16 × = 3.2 V R1 + R2 20 + 80

Rth = R1 / / R2 =

20 × 80 =16 kΩ 20 + 80

The circuit in Figure 5.17 is redrawn as in Figure 5.40. VCC = 16 V

RC = 2 kΩ

IC Rth = 16 kΩ

Vth = 3.2 V

IB

+

VCE + − − VBE IB

IC RE = 1.5 kΩ

Figure 5.40 Redrawn circuit of Figure 5.17 with component values as given in Example 5.17

(a) From Figure 5.40, writing the KVL equation of the base loop: Vth = IBRth + VBE + (IB + IC)RE Vth =

 Rth (1 + hFE )   IC 1  + Rth + I C 1 + RE   RE + VBE = VBE + I C  hFE h hFE FE    hFE 

2.5  16 101× 1.5  ∴ 3.2 = 0.7 + I C  + = 1.49 mA  and I C = 100  1.675  100 VCE = VCC − IC(RC + RE) = 16 − 1.49(2 + 1.5) = 10.78 V Therefore, the coordinates of the Q-point are IC = 1.49 mA and VCE = 10.79 V

Transistor Biasing and Thermal Stabilization

235

(b) When doubled, bdc = 2 × 100 = 200 2.5  16 201× 1.5  ∴ 3.2 = 0.7 + I C  + = 1.57 mA  and I C = 1.59 200   200 VCE = VCC − IC(RC + RE) = 16 − 1.57(2 + 1.5) = 10.5 V Therefore, the coordinates of the Q-point are IC = 1.57 mA and VCE = 10.5 V (ii) When bdc changes from 100 to 200, the change in (a) IC is from 1.49 mA to 1.57 mA = 0.08 mA in 1.49 mA is 5.37% (b) VCE is from 10.79 V to 10.5 V = 0.29 V in 10.79 V is 2.69% Example 5.18 Design the voltage divider bias circuit shown in Figure 5.17, to have VCE = 10 V and IC = 2 mA, given that VCC = 18 V, VBE = 0.7 V, hFE = 50, RC = 2 kΩ, and S ≤ 5. Solution: Calculation of RE: From Figure 5.17, VCC = VCE + IC(RC + RE) IC(RC + RE) = VCC − VCE = 18 − 10 = 8 V.

8

(RC + RE ) = 2 = 4 kΩ

RE = (RC + RE) − RC = 4 − 2 = 2 kΩ Calculation of R1 and R2: Given S ≤ 5. We have S =

1 + hFE where Rth = R1//R2  RE  1+   hFE  RE + Rth  ∴S =

1 + 50  2  1 + 50    2 + Rth 

Hence, Rth = 8.87 kΩ. Normally, from experience, R2 is chosen as R2 ≤ 0.1 hFERE = 0.1 × 50 × 2 = 10 kΩ Rth =

R1R2 R1 + R2

8.87 =

10R1 R1 + 10

R1 =

88.7 = 78.5 kΩ 1.13

236

Electronic Devices and Circuits

Example 5.19 A PNP transistor is used in a voltage divider bias circuit, given that VBE = −0.7 V and bdc = 50. The Q point is required to be located at IC = −1.5 mA and VCE = −8 V. VCC = −18 V and the drop across RE is −3 V. If S = 5, determine RC, R1, and R2. Solution: ICRC = VCC − VCE − VE = −18 −(−8) −(−3) = −7 V RC =

−7 V = 4.66 kΩ −1.5 mA

( I C + I B ) RE = −3 V RE =

S=

 1 I C 1 + b dc 

  RE = −3 V 

−3 = 1.96 kΩ −1.02 × 1.5

 RE  1 + hFE 51 1+  hFE = = = 10.2  S 5  RE + Rth 

1 + hFE  RE  1+  hFE  RE + Rth 

 RE   R + R  50 = 9.2 E th

RE 9.2 = = 0.184 RE + Rth 50 Rth = 8.7 kΩ

From the base–emitter loop, −Vth =

− I C Rth −1.5 × 8.7 − VE − VBE = − 3 − 0.7 = −3.96 V bdc 50

Vth = VCC

R V R2 −18 or 1 + 1 = CC = = 4.54 R2 Vth −3.96 R1 + R2 R1 = 3.54 or R1 = 3.54R2 R2 Rth =

R1R2 R1 + R2

8.7 =

3.54R2 R2 3.54R2 = 3.54R2 + R2 4.54

R2 =

8.7 × 4.54 = 11.16 kΩ 3.54

R1 = 3.54 R2 = 3.54 × 11.16 = 39.50 kΩ

Transistor Biasing and Thermal Stabilization

237

Example 5.20 Design the bias circuit shown in Figure 5.33 to operate from ±15 V supply voltages, given that VC = 7 V, VBE = 0.7 V, IC = 1.5 mA, and hFE = 50. Solution: The voltage at the emitter is VE = VEE − VBE = 15 − 0.7 = 14.3 V ∴ RE =

VE 14.3 = = 9.53 kΩ IC 1.5

The voltage drop across RL = VCC − VC = 15 −7 = 8 V ∴ RC = IB =

VCC − VC 8 = = 5.33 kΩ IC 1.5 I C 1.5 = = 0.03 mA hFE 50

VR1 = 0.1 VBE = 0.1 × 0.7 = 0.07 V R1 =

VR1 0.07 = = 2.33 kΩ 0.03 IB

Example 5.21 For the basing circuit in Figure 5.31, IC = 1 mA, VCC = 12 V, VBE = 0.7 V, and hFE = 100. Find R. Solution: We have  b   VCC −VBE  IC =    R   2 + b  Or  b   VCC − VBE  100 12 − 0.7 R= = 11.08 kΩ  = 102 ×  2 + b   IC 1

Example 5.22 For the voltage divider bias circuit shown in Figure 5.17, VCC = 30 V, VBE = 0.7 V, and RC = 4 kΩ. The Q-point has VCE = 15 V and IC = 3 mA. IC varies from IC1 = 2.5 mA to IC2 = 3.5 mA as bdc of the transistor varies from b1 = 40 to b2 = 100 at 25°C, whereas the variation of ICO is negligible. Find (i) RE, (ii) R1, and R2. Solution: (i) From Figure 5.17, RC + RE =

VCC − VCE 30 − 15 = = 5 kΩ IC 3

238

Electronic Devices and Circuits

RE = ( RC + RE ) − RE = 5 − 4 = 1 KΩ

(ii) S ′′ = ∆I C = 3.5 − 2.5 = 0.017 ∆b 100 − 40 The stability factor S is S2 at b = b2 From Eqn. (5.31), S ′′ =

I C1S2 b1 (1 + b2 )

S2 =

S ′′ b1 (1 + b2 ) I C1

=

0.017 × 40 (1 + 100 ) = 27.47 2.5

We have S2 = (1 + b2 )

27.47 = (1 + 100 )

Rth + RE = 27.47 Rth + (1 + b2 ) RE

(Rth + 1)

(Rth + 1)

Rth + (1 + 100 )1

Rth + 101

0.27(Rth + 101) = Rth + 1 Rth =

= 0.27

0.73 Rth = 26.27

26.27 = 36 kΩ 0.73

Also, from Eq 5.37 Vth = VBE +

Rth + RE (1 + b1 ) b1 Vth = VCC

I C1 = 0.7 +

36 + 1(1 + 40 ) × 2.5 = 5.51 V 40

R2 V R2 = th or R1 + R2 R1 + R2 VCC

And Rth =

RV R1R2 = 1 th R1 + R2 VCC

∴ R1 = Rth

VCC 30 = 36 × = 196 kΩ Vth 5.51

Vth(R1 + R2) = VCC R2 or Vth R1 = R2(VCC − Vth) ∴ R2 = R1

Vth 5.51 = 196 × = 44.1 kΩ VCC − Vth 30 − 5.51

Transistor Biasing and Thermal Stabilization

239

Summary • A transistor is said to be in the active region (class A operation), when the base–emitter diode is forward biased and the base–collector diode is reverse biased.



• The current gain in CB configuration is a (= hFB), that in the CE configuration is b  hFE =



 a h = FB , 1 − a 1 − hFB 

and that in the CC configuration is (1 + hFE). • ICO in CE configuration is (1 + bdc) times larger than that in the CB configuration. Further, ICO gets doubled for every 10°C rise in temperature. • The operating point or Q-point in CE configuration gives the values of IC and VCE under no signal conditions (dc components). The operating point is likely to change with variations ICO, VBE, and b. • To provide bias stability, negative feedback is used in the circuit. The examples are collector-to-base feedback bias and self-bias circuits. • Bias compensation can be provided by using diodes, thermistors, and sensistors. • Normally, a thermistor has a negative temperature coefficient (NTC) and a sensistor has a positive temperature coefficient (PTC).

multiple ChoiCe Questions 1. When forward–forward bias is provided in a transistor, then the transistor is said to be in (a) active region (b) saturation region (c) cut-off region (d) none of these 2. When forward–reverse bias is provided in a transistor, then the transistor is said to be in (a) active region (b) saturation region (c) cut-off region (d) none of these 3. When reverse–reverse bias is provided in a transistor, then the transistor is said to be in (a) active region (b) saturation region (c) cut-off region (d) none of these 4. The stability factor S is defined as (b) S =

dI C , I , and bdc constant dVBE CO

(d) S =

dI C , IC, and IB constant dI CO

dI C , b dc , and VBE constant dI CO

(b) S′ =

dI C , ICO, and bdc constant dVBE

(c) S′ = dI C , ICO, and VBE constant db

(d) S′ =

dI C , IC, and IB constant dI CO

(a) S =

dI C , b dc , and VBE constant dI CO

(c) S = dI C , ICO, and VBE constant db 5. The stability factor S′ is defined as (a) S′ =

240

Electronic Devices and Circuits

6. The stability factor S″ is defined as (a) S ″ =

dI C , b dc , and VBE constant dI CO

(b) S ″ =

dI C , ICO, and bdc constant dVBE

(c) S ″ =

dI C , I ,V , and constant d b CO BE

(d) S ″ =

dI C , IC, and IB constant dI CO

7. The stability factor S in the case of fixed bias is (a) 1 + hFE (c)

1 + hFE hFE

(b) 1 − hFE (d)

1 − hFE hFE

8. Stability factor S in the case of emitter bias and voltage divider bias becomes small because of (a) negative feedback provided in the circuit (b) positive feedback provided in the circuit (c) BJT is used in the circuit (d) none of the above 9. Thermistor and sensistor are used in a biasing circuit to provide (a) sufficient voltage gain (b) sufficient current gain (c) required power gain (d) bias compensation 10. A thermistor is a circuit element that normally has (a) positive temperature coefficient (b) negative temperature coefficient (c) large current gain (d) large voltage gain 11. A sensistor is a circuit element that normally has (a) positive temperature coefficient (c) large current gain

(b) negative temperature coefficient (d) large voltage gain

12. The resistance of a thermistor (a) increases with increase in temperature (b) decreases with increase in temperature (c) does not change with temperature (d) none of these 13. The resistance of a sensistor (a) increases with increase in temperature (b) decreases with increase in temperature (c) does not change with temperature (d) none of the above

short answer Questions 1. 2. 3. 4. 5. 6. 7. 8.

What do you mean by biasing a transistor? What are the different methods of biasing a transistor? What are the coordinates of the operating point in the CE mode of operation? What is meant by mid-point biasing? Give its advantage. What is a fixed bias arrangement? What is its main limitation? What is bias stabilization? What is the main advantage of the emitter bias arrangement over the fixed bias arrangement? It is often said that the collector-to-base feedback bias is usually not preferred. Why is this so?

Transistor Biasing and Thermal Stabilization

9. 10. 11. 12.

241

What is meant by bias compensation? Explain its principle. What is a thermistor? How does its resistance vary with temperature? What is a sensistor? How does its resistance vary with temperature? Define the stability factor S.

long answer Questions 1. Draw the circuit of collector-to-base bias arrangement of a transistor and explain its working. Derive the expression for S and infer how the stability factor can be improved. 2. With the help of a neat circuit diagram, explain the principle of operation of emitter bias arrangement. Derive the expression for S and infer how the stability factor can be improved. 3. With the help of a neat circuit diagram, explain the principle of operation of voltage divider bias arrangement. Derive the expression for S and infer how the stability factor can be improved. 4. What is the difference between bias stability and bias compensation? Explain how bias compensation can be achieved using a diode, thermistor, and sensistor.

unsolved problems 1. For a fixed bias configuration, determine, IC, RB, RC, and VCE, using the following specifications: VCC = 12 V, VC = 6 V, b = 80, and IB = 40 µA. 2. For a fixed bias configuration, determine IBQ, ICQ, and VCEQ using the following specifications: VCC = 16 V, b = 90, RC = 2.7 kΩ, RB = 470 kΩ and also find the saturation current Isat. 3. Calculate the quiescent collector current and voltage of collector-to-base bias arrangement using the following data: VCC = 10 V, RB = 100 kΩ, RC = 2 kΩ and b = 50. Also specify the value of RB so that VCE =7V 4. Calculate the thermal resistance for 2N338 transistor for which the manufacturer specifies PC(max) = 125 mW at 25°C and maximum junction temperature of Tj = 150°C. What is the junction temperature if the collector dissipation is 75 mW? 5. A silicon transistor with b = 50, VBE = 0.6 V, VCC = 22.5 V, and RC = 5.6 kΩ is used for self-biasing circuit. It is desired to establish a Q-point at VCE = 12 V and IC = 1.5 mA and a stability factor S ≤ 3. Find RE, R1, and R2. 6. For the bias circuit shown in Figure 5.32, VCC = 20 V, VC =15 V, VE = 5 V, and IC = 4 mA. Determine the values of RE, R1, R2, and RC.

6

SMALL-SIGNAL, LOW-FREQUENCY BJT AMPLIFIERS

Learning objectives After going through this chapter, the reader will be able to       

6.1

Draw the low-frequency small-signal equivalent circuits of transistor Realize the three basic amplifier configurations, namely, common base (CB), common emitter (CE), and common collector (CC) configurations Obtain the expressions for the voltage gain, current gain, input resistance, and the output resistance of an amplifier Compare the performance of the three basic configurations of BJT Convert the h-parameters from one configuration to the other configurations Understand the relevance of bandwidth of an amplifier Understand the influence of distortion on the output waveform of the amplifier

INTRODUCTION

The bipolar junction transistor (BJT) is often referred to as transistor. A transistor can operate in one of the three regions of operation: active region, saturation region, and cut-off region. In switching applications, the operating point shifts between the saturation and cut-off regions. When the transistor is used in linear applications such as in amplifiers, the operating point is located in the middle of the active region. It has to be noted here that the transistor enters nonlinear portions of the characteristic in large-signal amplifiers (Chapter 11). The location of the operating point on the device characteristics determines the region of operation of a device. The word biasing means establishing the operating point in the desired region. Thus, biasing provides the necessary dc conditions in the circuit. The actual signal to be amplified by the circuit is applied only after the circuit is biased in the linear region of operation. We know that the linear region exists in the active region.

6.2 THE LOCATION OF THE OPERATING POINT Let us consider a transistor amplifier in CE configuration as shown in Figure 6.1. The location of the operating point determines the region in which a transistor is being operated. The output characteristics of a transistor are available in the datasheets. We can write the Kirchhoff’s voltage law (KVL) equation from the output loop of the circuit shown in Figure 6.1 as follows: VCE = VCC − I C RC

(6.1)

Small-Signal, Low-Frequency BJT Amplifiers

The load line of the amplifier is obtained by rewriting Eqn. (6.1) as follows: IC =

VCC VCE − RC RC

243

VCC

(6.2) IC

RC

This is in the form of y = mx + c and is the equation R1 of straight line and this represents dc load line. + IB In the output characteristics of transistor in CE VCE configuration, we take collector voltage VCE on the + − x-axis and collector current IC on the y-axis. Typical − VBE output characteristics are shown in Figure 6.2. The + point of intersection of the device characteristic and R2 V2 the load line is called the operating point. The points − of intersection of the output characteristics and the dc load line specify the manner in which the IC varies as a function of VCE, since IC will have to satisfy both the output characteristics and the dc load line. G Appropriate point of intersection of the de load line and the output characteristics is chosen as the Figure 6.1 Transistor biased in the active region operating point. Operating point is also referred to as quiescent point or Q-point. The operating point of the transistor amplifier circuit has to be located in the active region. This can be done by establishing the necessary dc conditions. The word biasing is used to indicate the method for establishing the dc conditions. Here, dc conditions mean fixing the collector voltage VCE and the collector current IC in such a way that the operating point (VCE , I C ) is located in the active region. DC load line

IC mA 15

IB7 IC(sat) = VCC/RL 10 Q-Point

ICQ 5

IB2 IB1 IB = 0

0

0

5 VCEQ

10 VCC VCE(cut-off) VCE

V

Figure 6.2 Output characteristics and the dc load line

Readers may note that the operating point moves along the load line as expressed in Eqn. (6.2). At the lower extreme of the load line (VCE = VCC , I C = 0 ), we find the transistor operating in the cut-off region. At the upper extreme of the load line (VCE = 0, I C = VCC RC ) , we find the transistor operating in the saturation region. We expect the transistor to operate in the middle of the active

244

Electronic Devices and Circuits

region, and this means that VCE has to be around VCC 2 and the collector current has to be around I C = VCC 2R C . When a transistor circuit is used as an amplifier, the output signal is larger than the input signal. In practical applications, such as in a public address system, the input signal is a speech signal. The speech signal contains a number of frequency components with varying amplitudes. To find the amplitude of each of these frequency components in the output is a very difficult task. To avoid such difficulty, a sinusoidal signal with constant amplitude Vm sinwt is applied as input to the amplifier, and the output is found for the fundamental frequency w. Readers may note that sinusoidal signal is also known as an alternating signal. In this way, we find that the output signal at the collector contains a dc component and a series of ac components of frequencies w1, w2, w3, and so on, as we have at the input. The dc component of the output depends on the operating point. The series of ac components in the output represent the signals that are amplified. A  coupling capacitor CC is connected at the collector for blocking the dc component. After passing through the blocking capacitor, the output retains only ac components that represent the input signals. The rms values of these output signals are represented by Vo .

6.3

SKETCHING THE AC CIRCUIT OF THE AMPLIFIER

Sometimes, the input signal may contain a dc component, and this component is blocked by the blocking capacitor, CC , connected at the input. Now, in order to find the ac component in the output when compared to the input, we have to draw the ac circuit of the amplifier. The ac circuit is drawn by using the superposition theorem, considering only the ac source and shorting the dc power supply VCC . The bias circuit has to be sketched as indicated in Figure 6.3(a) in order to determine the dc conditions of the circuit. We assume that CC and CE can be replaced by a short circuitin the range of frequencies of operation. The values of CC and CE are chosen to satisfy this condition. VCC

VCC

IC

IC

RL

R1 IB

+ VCE

+ VBE

−

−

R2 IB

IB

0

− IC RE

(a) The bias circuit

+

Cc +

+ V2

RL Cc + VC

R1

Vs

VCE

VC 0 −

0 +

+ V2 −

Vo

+

R2

CE RE

−

(b) The common emitter amplifier

Figure 6.3 Transistor amplifier in CE configuration

We apply superposition theorem to the transistor amplifier circuit shown in Figure 6.3 and consider the case of applying only the input ac signal. When we consider only the ac signal, the power supply voltage VCC is treated as a short circuit as indicated in Figure 6.4.

Small-Signal, Low-Frequency BJT Amplifiers

IC Short 0

IB +

Cc +

R1

VBE

Short RL + VC

Cc 0

VC 0 −

+

+

Vs

V2

VCC

Short

Vo

+

R2

245

CE RE −

−

Short

Figure 6.4 The circuit of Figure 6.3 redrawn with VCC shorted and capacitors short-circuited

In a similar way, the two coupling capacitors CC and emitter bypass capacitor CE are replaced by short circuits. Readers can also find “short” near these components in Figure 6.4. After applying these assumptions, the circuit in Figure 6.4 appears to be totally different. The ac equivalent circuit of Figure 6.4 is redrawn as Figure 6.5. 0 + Io

0

Ib + Vs

RL

R1

Vo R2

−

Figure 6.5 Resultant circuit of Figure 6.4

Application of superposition theorem enables us to draw its dc equivalent circuit and ac equivalent circuit. The dc equivalent circuit indicated in Figure 6.3(a) is well-known as the biasing circuit as it provides the dc biasing conditions. Readers may note that Figure 6.3(b) contains both ac and dc sources and is a complete transistor amplifier circuit. The circuit in Figure 6.4 also contains all the components of a complete transistor amplifier circuit with some portions labeled “short” to enable us to understand the way in which we obtained the circuit in Figure 6.5. The ac equivalent circuit Figure 6.5 is used in our further analysis to obtain the properties of the transistor amplifier. Normally, the biasing resistances R1 and R2, as indicated in Figure 6.3(a) and Figure 6.5, are chosen to be large so that the amount of current drawn from the power supply VCC is small. The resistances R1 and R2 are also chosen to ensure R = R1 || R2, is not going to alter the input conditions

246

Electronic Devices and Circuits

of the amplifier. We can see in Figure 6.5 that resistor R is the effective resistance of R1 and R2 that appears across Ic 0 the input resistance of the amplifier. If the input resistance + of the amplifier is very small compared to R, the circuit of 0 Figure 6.5 becomes same as Figure 6.6. In order to find the performance quantities of the Io Ib amplifier, namely, the current gain AI, the input resistance RL + Ri, the voltage gain AV, and the output resistance Ro, the Vo circuit in Figure 6.6 cannot be used directly, since the tranVs Ro sistor Q is present in the circuit. We know that transistor Ri is a nonlinear device, and the methods of network analysis can be used in a circuit that contains only linear bilateral − elements. Unless the transistor is replaced by its equivalent circuit, in terms of linear  components, the performance quantities cannot be evaluated. This is the reason Figure 6.6 Simplified circuit of Figure 6.5 for replacing the transistor by its equivalent circuit. First, we replace the transistor by its equivalent circuit at low frequencies and under small-signal conditions. We can note the transfer characteristic of the CE configuration in Figure 6.7. In the figure, it can be noted that the transistor is biased in the middle of the linear region of the characteristic. We can also note from Figure 6.7, where mid-point bias is provided we get the largest possible undistorted output swing. As long as the operation is limited to a very small region on the transfer characteristic, between points A and B, where the characteristic is linear, if the input swing is sinusoidal, the output swing is too sinusoidal. The input is reproduced at the output with the same frequency, but with increased amplitude. There is no distortion in the shape of the output waveform. Under these conditions, the transistor is said to be operating as a linear circuit element, and the amplifier can be described as a linear amplifier or small-signal amplifier or voltage amplifier. We shall be referring to this circuit as small-signal voltage amplifier in our further discussion. IC IC(sat)

IC 0

A ωt

IC1

Q1

IC1 =

IC(sat) 2

B

0

IB1

IB

Ib ωt

Figure 6.7 Transfer characteristic of CE configuration

Small-Signal, Low-Frequency BJT Amplifiers

6.4

247

SMALL-SIGNAL, LOW-FREQUENCY MODEL OF THE TRANSISTOR

To calculate the performance quantities, we need to replace the transistor in Figure 6.6 by its equivalent circuit. We now try to obtain the small-signal, low-frequency model of the transistor. We observe that there exists a stray capacitance between a pair of terminals of an electronic circuit. Normally, this capacitance is small and is of the order of pF. At low frequencies, the reactance offered by these stray capacitances is very large compared to the other components in the circuit. Under these practical conditions, the stray capacitances can be replaced by open circuits. For this reason, the equivalent circuit is valid only at low frequencies. Let us consider the h-parameter model of the transistor. For this purpose, consider Figure 6.8, in which the transistor is shown enclosed in a black box with input and output terminals shown externally. If the emitter is common between the input and the output, the configuration is called the CE configuration. Alternatively, if base or collector is common between the input and the output, the transistor configuration is I1 I2 called CB or CC configuration. + + The transistor shown as a black box in Figure 6.8 Transistor can be modeled in several ways: z-parameter model, V1 V2 y-parameters, and h-parameter model. In early 1950s, the analysis of transistor circuits was carried out by using all these models. It has been found that the results Figure 6.8 Transistor as a two-port network obtained using the h-parameter model were found to be compatible with experimental observations. Transistor is modeled in z-parameters using Eqs (6.3) and (6.4) as given below where we write voltage equations. Readers may note that the four z-parameters are measured in ohms. V1 = z11I1 + z12 I 2

(6.3)

V2 = z21I1 + z22 I 2

(6.4)

We can also write down current Eqs (6.5) and (6.6) in terms of y-parameters. Readers may note that the four y-parameters are measured in mhos. I1 = y11V1 + y12V2

(6.5)

I 2 = y21V1 + y22V2

(6.6)

As a result of the convenience offered by them, h-parameters are normally listed in the datasheets. In the network shown in Figure 6.8, let us represent V1 and I2 as follows: V1 = hi I1 + hrV2

(6.7)

I 2 = hf I1 + hoV2

(6.8)

Equations (6.7) and (6.8) describe a low-frequency, small-signal transistor mathematically, and the resulting equivalent circuit is indicated in Figure 6.9. The word hybrid in h-parameters indicates that the units of these four parameters are hybrid and do not belong to one physical quantity.

248

Electronic Devices and Circuits

The h-parameters hi and ho are measured in ohms and mhos, respectively, and h-parameter hr and hf are ratios and do not have units. hi +

+ I1 V1

I2

+

hf I1

h r V2

ho

V2

Figure 6.9 The low-frequency, small-signal model of the transistor

The definitions of the four h-parameters hi, hr, hf, and ho are given below: Short-circuit input resistance, hi V1 V2 = 0 I1

(6.9)

hr =

V1 I1 = 0 V2

(6.10)

hf =

I2 V2 = 0 I1

(6.11)

ho =

I2 I1 = 0 V2

(6.12)

hi = Open-circuit reverse transmission gain, hr:

Short-circuit forward current gain, hf:

Open-circuit output admittance, ho:

Ib

For the CE configuration, these parameters are called hie, hre, hfe, and hoe; for the CC configuration, these parameters are called hic, hrc, hfc, and, hoc; and for the CB configuration, these parameters are called hib, hrb, hfb, and hob. Consider the transistor in the CE configuration as shown in Figure 6.10. hie

Ic

B+

Ib Vbe

hfe Ib

+

hoe

hre Vce

+ B

Vce

E

Figure 6.11 Equivalent circuit of the transistor in CE configuration

Q

+

E

Vce

Vbe

−

+C

Ic

C

−

Figure 6.10 Transistor in CE configuration

249

Small-Signal, Low-Frequency BJT Amplifiers

Now, the transistor can be replaced between the base, emitter, and collector terminals by the equivalent circuit in Figure 6.11, with its CE parameters as in Table 6.1. Consider now the transistor in CB configuration, Figure 6.12 and its h-parameter equivalent circuit in Figure 6.13.

Ie E

Ic

C +

+

Veb

Vcb

B

Figure 6.12 Transistor in CB configuration Ic

hib E+

+C Ie

Veb

Ib

hob

hrb Vcb

Ie

B +

+ Vcb

hfbI e

Vbc

C

E + Vec

B

Figure 6.13 Equivalent circuit

Figure 6.14 Transistor in CC configuration

Consider the CC configuration shown in Figure 6.14 and the equivalent circuit shown in Figure 6.15. The parameters can be evaluated using the input and the output characteristics for a given transistor configuration at a specified operating point. Typical values of these parameters are listed in Table 6.1, which can be used to evaluate the numerical values of the performance quantities.

Ie

hic

B

E

+ Ib Vbc

+

hfc I b + hoc

hrcVec

Vec

C

Figure 6.15 Equivalent circuit

Table 6.1 Typical values of the parameters at specified I C . Parameter

6.5

CE configuration

CC configuration

CB configuration

hi

hie = 1100 Ω

hic = 1100 Ω

hib = 21.6 Ω

hr

hre = 2.5 × 10 −4

hrc = 1

hrb = 2.9 × 10 −4

hf

hfe = 50

hfc = −51

hfb = −0.98

ho

hoe = 25 × 10 −6 A/V

hoc = 25 × 10 −6 A/V

hob = 0.4 × 10 −6 A/V

1 ho

1 = 40 kΩ hoe

1 = 40 kΩ hoc

1 = 2.04 MΩ hob

ANALYSIS OF A CE TRANSISTOR AMPLIFIER

Once again, consider the CE transistor amplifier shown in Figure 6.5 in which the parallel combination of R1 and R2 is replaced by R, as shown in Figure 6.16, and Rs is the internal resistance of the voltage source.

250

Electronic Devices and Circuits

In order to calculate the performance quantities, the transistor is now replaced by its equivalent circuit between the base, emitter, and collector terminals as in shown in Figure 6.17 and this circuit again redrawn as Figure 6.18 for the computation of the performance quantities. C + Io

Rs

B

Ib RL

+

CE amplifier

+ Vs

Vo

R

Vi −

Rs

Ro

B

C +

+

+ Ri

RL

Vi −

Vs

−

−

Vo Io −

E

E

Figure 6.16 Resultant circuit of Figure 6.5 RS

Figure 6.17 The CE transistor voltage amplifier

hie

B

Ic +

+

+

Vi Vs −

Ib

hfe Ib

+

C hoe

hre Vo

RL

Vo Io

−

−

E

Figure 6.18 Circuit of Figure 6.17 with transistor replaced by its equivalent circuit

Current gain, AI We can write the following equation from the output circuit in Figure 6.18: I c = hfe I b + hoeVo

(6.13)

The output voltage can be expressed as follows: Vo = −I c RL

(6.14)

Substituting Eqn. (6.14) in Eqn. (6.13), I c = hfe I b + hoe ( −I c RL ) I c (1+ hoe RL ) = hfe I b We can obtain the ratio of currents as follows: Ic hfe = I b 1 + hoe RL

(6.15)

Small-Signal, Low-Frequency BJT Amplifiers

251

A I, the current gain, using Eqn. (6.15), is given as follows: AI =

− hfe Io −Ic = = 1 + hoe RL Ib Ib

(6.16)

Input resistance, Ri From the base–emitter loop, Vi = hie I b + hreVo

(6.17)

Using Eqn. (6.14), Vi = hie I b + hre ( −I c RL ) Dividing by I b,  −I Vi = Ri = hie + hre  c Ib  Ib

  RL = hie + hre AI RL 

(6.18)

Using Eqn. (6.16),  − hfe RL  Ri = hie + hre AI RL = hie + hre    1 + hoe RL 

(6.19)

Dividing numerator and denominator in the second term by RL,

Ri = hie −

hfe hre h h = hie − fe re 1 YL + hoe + hoe RL

(6.20)

Here, Ri is the input resistance of the amplifier and YL = 1 ZL. Voltage gain, AV The voltage gain can be expressed as follows: AV =

R  Vo −I c RL = = AI  L  Vi I b Ri  Ri 

(6.21)

Overall voltage gain, AV From the circuit in Figure 6.18, we have the input circuit of the amplifier as indicated in Figure 6.19. We have drawn the circuit with a voltage source in Figure 6.19(a) and a current source in Figure 6.19(b) for convenience. s

252

Electronic Devices and Circuits Rs

B

B

+

+

Ii

Vi Vs

Ri

Is

Rs

Ri

−

− (a)

(b)

Figure 6.19 Input circuit of the amplifier: (a) voltage source driving the input and (b) current source driving the input.

We can write the following equation from Figure 6.19 (a) by applying voltage divider method.  Ri  Vi = Vs    Ri + Rs 

(6.22)

We can write from Eqn. (6.14) that Vo = −I c RL Rewriting Eqn. (6.22),  R + Rs  Vs = Vi  i   Ri 

(6.23)

Using Eqs (6.23) and (6.21), AV = s

Vo = Vs

 Ri   R   Ri  Vo = AI = AV  = AI  L    R + R  Ri + Rs   Ri   Ri + Rs   i s Vi   Ri 

 RL   R + R  i s

(6.24)

where AV is the overall voltage gain and AV is the gain of the amplifier not taking Rs into s

account. If in an amplifier, Ri >> Rs, then AVs = AV. Overall current gain, AI The overall current gain can be written as follows: s

AI = s

−Ic Is

Applying current divider method, from Figure 6.19(b),  Rs  I i = Is    Rs + Ri  Alternatively, this can be written as follows:  R + Ri  Is = I i  s   Rs 

Small-Signal, Low-Frequency BJT Amplifiers

253

Therefore, AI = s

−Ic = Is

 Rs  = AI .   R + Ri   Rs + Ri  Ii  s  Rs  −Ic

(6.25)

Dividing Eqn. (6.24) by Eqn. (6.25):  RL   Ri + Rs   1  RL = AI  = AI  Ri + Rs   Rs   AI  Rs

AV

s

s

Therefore, R  AV = AI  L   Rs  s

(6.26)

s

Output impedance: Ro Ro = 1 Yo , where Yo is the output admittance. The procedure to find Ro or Yo is shown in the following discussion: Let RL → ∞ that is, open the load. Introduce a voltage source V2 at the output and find the circulating current I 2 , with Vs = 0 (short circuit the voltage source) or I s = 0 (open circuit the current source). The ratio of I 2 to V2 gives the output admittance, and its reciprocal is the output resistance of the circuit in Figure 6.20. RS + Vs = 0

hie

B

+

I2

Ib

Vi

h fe I b

+

C

+ V2 R1

hoe

hre V2

∞

−

− E

Figure 6.20 Amplifier circuit with Vs = 0 and RL = ∞

Yo =

I  I 2 hfe I b + hoeV2 = = hfe  b  + hoe V2 V2  V2 

From Figure 6.20, the KVL equation of the input loop with Vs = 0 is I b ( Rs + hie ) + hreV2 = 0 We can rewrite this equation as follows: I b ( Rs + hie ) = −hreV2

(6.27)

254

Electronic Devices and Circuits

Therefore, Ib −hre = V2 Rs + hie

(6.28)

Substituting Eqn. (6.28) in Eqn. (6.27), Yo =

I h h I2 = hfe b + hoe = hoe − fe re Rs + hie V2 V2

(6.29)

The CB and CC amplifiers are shown in Figures 6.21 and 6.22, respectively. The performance quantities for these amplifiers are also calculated on similar lines, except for the fact that the h-parameters of the concerned configuration are now used in the expressions as indicated in Table 6.2 Rs

E

Rs

C

B

E

+ +

+ Vs −

CB amplifier

Vi −

+ +

+ Vo

RL

Vs

Io −

B

−

Figure 6.21 CB transistor amplifier

CC amplifier

Vi −

C

Figure 6.22 CC transistor amplifier

Table 6.2 Expressions to calculate the performance quantities of CB and CC amplifiers S. No

Performance quantity

CB amplifier

CC amplifier

1

AI

−hfb 1 + hob RL

−hfc 1 + hoc RL

2

Ri

hib + hrb AI RL

hic + hrc AI RL

3

AV

R  AI  L   Ri 

R  AI  L   Ri 

4

AV

 RL  AI   Ri + Rs 

 RL  AI   Ri + Rs 

5

AIs

 Rs  AI   Ri + Rs 

 Rs  AI   Ri + Rs 

6

Yo

hob −

s

RL

hfb hrb Rs + hib

hoc −

hfc hrc Rs + hic

Vo Io −

Small-Signal, Low-Frequency BJT Amplifiers

6.6

255

SIMPLIFIED EQUIVALENT CIRCUIT OF THE TRANSISTOR

In the equivalent circuit of the transistor in Figure 6.11, since hreVce > hoeVce , I c = hfe I b (This means that ideally hoe = 0 or 1 hoe = ∞ .) Hence, this equivalent circuit in Figure 6.11 can be replaced by its approximate model as shown in Figure 6.23. Ic

B+

+C Ib hie

Vbe

hfe Ib Vce

E

Figure 6.23 Approximate CE model of the transistor

Using the approximate model, we can calculate the performance quantities. The amount of error is negligibly small. From Eqn. (6.16), AI =

−I c −hfe = I b 1 + hoe RL

Since hoe = 0, AI = −hfe From Eqn. (6.20), Ri = hie AV, AV , and AI are calculated using Eqs (6.21), (6.24), and (6.25), respectively. s

s

From Eqn. (6.29), Yo = 0 and Ro = ∞ Example 6.1 A transistor used in a linear CE amplifier at low frequencies has the following parameters: hie = 1.1 kΩ, hfe = 100, hoe = 25 µA/V, hre = 2.5 ×10 −4 , RL = 2.2 kΩ, and Rs = 500 Ω. Calculate the performance quantities. Solution: 1 1 = = 40 kΩ hoe 25 × 10 −6 From Eqn. (6.16), AI =

− hfe −100 −100 = = − 94.79 = 2.2 1 + 0.055 1 + hoe RL 1+ 40

256

Electronic Devices and Circuits

From Eqn. (6.18), Ri = hie + hre AI RL = 1100 + 2.5 × 10 −4 × ( −94.79 ) × 2.2 × 103 = 1100 – 52.13 ≈ 1048 Ω From Eqn. (6.21), AV =AI ×

RL 2.2 = − 94.79 × = − 198.99 Ri 1.048

From Eqn. (6.24), AV = AV × s

Ri 1.048 = −198.99 × = −134.72 Ri + Rs 1.048 + 0.500

From Eqn. (6.29), Yo = hoe −

hfe hre 100 × 2.5 × 10 −4 = 25 × 10 −6 − = 10 −6 ( 25 − 15.625 ) = 9.375 × 10 −6 mhos ( Rs + hie ) 500 + 1100 Ro =

6.7

1 1000 = = 106.67 kΩ Yo 9.375

ANALYSIS OF CC AMPLIFIER

VCC The CC amplifier is shown in Figure 6.24, and its ac circuit is shown in Figure 6.25. This circuit cannot be seen apparently as a CC amplifier. When redrawn, the circuit of IC Figure 6.25 with R1 || R2 considered as large when compared to the input resistance of R1 the amplifier is shown in Figure 6.26. Here, it IB 0 can be clearly noted that the collector is the common terminal between the input and the + Cc Cc − output. The output is taken at the emitter. We 0 VBE + will subsequently be seeing that the voltage + Vs gain of this amplifier is approximately unity. + R2 V2 Hence, the emitter follows the base. This Vo means that when the base voltage changes, − RE − an almost identical change takes place at the emitter always. Hence, the common collector amplifier is also called an emitter follower. This amplifier gives an output that has the Figure 6.24 The emitter follower (CC transistor amplifier) same magnitude as the input. The output of this circuit also has the same phase as the input. This obviously means that this amplifier faithfully transmits the input to the output terminals. Hence, this is used as a buffer amplifier.

257

Small-Signal, Low-Frequency BJT Amplifiers Ic 0 0

+ 0 Ib

+ Ib

+

Io

R1

Vs

RL

+

R2 RL

Vo

Ro

Vs

Vo

Ri −

−

Figure 6.26 Circuit that shows collector as the common terminal

Figure 6.25 The ac circuit of Figure 6.24

Replacing the transistor in Figure 6.26 with its low-frequency small-signal model, the equivalent circuit of the amplifier is as shown in Figure 6.27. RS

hic

B

E +

+

+

Ib

Vi Vs

+ RL hrc Vo

hfc Ib

Io

−

−

Vo

hoc −

C Ri

Figure 6.27 Equivalent circuit of CC amplifier shown in Figure 6.26

Using the relations in Table 6.2, the performance quantities of the CC amplifier can be calculated. Example 6.2 A transistor used in a linear CC amplifier at low frequencies has the following parameters: hic = 1.1 kΩ, hfc = −101, hoc = 25 µA/V, hrc = 1, RL = 2.2 kΩ, and Rs = 500 Ω. Calculate the performance quantities. Solution: 1 1 = = 40 kΩ hoc 25 × 10 −6 AI =

−hf c 1 + hoc RL

=

101 101 = = 95.73 2.2 1 + 0.055 1+ 40

R i = hic + hrc AI RL = 1.1 + 1× ( 95.73 ) × 2.2 = 1.1 + 210.6 = 211.7 kΩ

258

Electronic Devices and Circuits

A V = AI ×

RL Ri

= 95.73 ×

2.2 = 0.995 211.7

A Vs = AV ×

Ri 211.7 = 0.995 × = 0.993 Ri + Rs 211.7 + 0.500

Yo = hoc −

hfc hrc 101 × 1 = 0.063 mhos = 25 × 10 −6 + ( Rs + hic ) 500 + 1100

Ro =

1 1 = = 15.87 Ω Yo 0.063

From Example 6.2, it can be seen that AI for CC amplifier is 500 Rs B large, AV ≈ 1, Ri is large, and Ro is small. Here, it has to be + 6.67 mV + pointed out that while we write that AV is only 1, in reality Vi Ri the value of AV is slightly less than 1. Apparently, there is no 10mV V 1000 s justification to call this circuit as an amplifier since its voltage − − gain is less than unity. But this circuit has the advantage that Ri is large and Ro is small. How can this be an advantage? Figure 6.28 Voltage source driving the input of the CE amplifier Let us consider the input circuits of CE and CC amplifiers shown in Figures 6.28 and 6.29. For the CE amplifier in Figure 6.28, if the signal 0.5 Rs B Vs = 10 mV, Vi , the actual input to the amplifier is +

 Ri   1000  Vi = Vs  = 10  = 6.67 mV   1000 + 500   Ri + Rs 

10mV

Vs

−

+

9.98 mV

Vi

Ri

−

200

In this case, though the signal at the input is 10 mV, only 6.67 mV appears between the actual input terminals of the Figure 6.29 Voltage source driving the input of the CC amplifier amplifier, which will be amplified by the amplifier. Considerable signal is wasted as drop across Rs . Whereas, for the CC amplifier in Figure 6.29, for the same input signal Vs = 10 mV , Vi , the actual input to the amplifier is  Ri   200  Vi = Vs   = 10   = 9.98 mV  200 + 0.5   Ri + Rs  In this case, once again the signal at the input is 10 mV, but 9.98 mV appears between the actual input terminals of the amplifier, which will be amplified by the amplifier. This means that the entire signal appears at the actual input terminals of the amplifier. This is the advantage of using an amplifier with large input resistance when the driving signal is a voltage. Let us consider the output circuits of CE and CC amplifiers shown in Figures 6.30 and 6.31.

40 Ro

1500mV AVi +

+

2

Vo

RL

−

71.43mV

Figure 6.30 Voltage as the desired signal at the output of CE amplifier

Small-Signal, Low-Frequency BJT Amplifiers 20

For the CE amplifier in Figure 6.30, let AVi = 1500 mV. Then Vο , the actual output of the amplifier is

Ro +

 RL   2  Vo = − AVi  = −1500  = −71.43 mV   2 + 40   RL + Ro 

+

2 RL

1500 mV Vo

AVi

−

−

In this case, though the signal at the output is 1500 mV, only 71.43 mV appears across the load terminals. Considerable signal is wasted as drop across Ro .

259

1485 mV

Figure 6.31 Voltage as the desired signal at the output of CC amplifier

Whereas, for the CC amplifier in Figure 6.31, for the input signal AVi = 1500 mV , the actual output of the amplifier is  RL   2000  Vo = AVi   = 1500   = 1485 mV  2000 + 20   RL + Ro  In this case, a signal of 1500 mV appears across the load terminals as 1485 mV. This means that the entire output signal appears across the load. This is the advantage of using an amplifier with small output resistance when the desired signal at the output is a voltage. From the above discussion, it is evident that a CC amplifier transmits the input to the output terminals reliably, with the same phase and with almost the same magnitude. Hence, CC amplifier is used as a buffer amplifier. Therefore, to derive a larger output voltage, it is preferable to provide a CC amplifier as an input stage for a CE amplifier and also a CC amplifer as an output stage for a CE amplifier (Figure 6.32). 0.5 K Rs + 10 mV Vs

+ 10 mV Vi −

+ 200 K 20 Ro 10 mV + Ri 1K A vVi −

1500 mV

1250 mV

CC amplifier

CE amplifier

CC amplifier

Ri

40 K +

Ro

A vVi

+ 1250 mV 200 K

Ri

20 +

Ro

A vVi

RL

+ 1238 mV Vo 2K −

Figure 6.32 CC–CE–CC configuration

When 10 mV was the input to a CE amplifier alone, its output was 71.43 mV. If a CC amplifier is used as a preamplifier and also as an output stage, the output of the cascaded amplifier configuration is 1238 mV (Figure 6.32.) The output voltage in this case is 1238 mV, which is very large. Thus, we see the utility of CC amplifier. Despite its gain being equal to 1, it helps in deriving a larger output voltage when used in cascade with a CE amplifier mainly because of its large input resistance and negligible output resistance.

260

6.8

Electronic Devices and Circuits

ANALYSIS OF CB AMPLIFIER

The circuit of CB amplifier and its equivalent circuit are shown in Figures 6.33 and 6.34. Ie

Rs

Ic +

+ RL

Vs

Vo

− VEE

VCC

Figure 6.33 CB amplifier Rs

IC

hib

E

C +

+

+ Vs −

Ie

+

Vi −

hob hrb Vo

RL

Vo

hfb Ie B

Figure 6.34 Equivalent circuit

Using the relations in Table 6.2, the performance quantities of the common base amplifier can be calculated. Example 6.3 A transistor used in a linear CB amplifier at low frequencies has the following parameters: hib = 21.6 Ω, hfb = −0.98, hob = 0.49 µA/V, hrb = 2.9 × 10 −4. RL = 2.2 kΩ, and Rs = 500 Ω. Calculate the performance quantities. Solution: 1 1 = = 2.04 MΩ hob 0.49 × 10 −6 AI =

− hfb = 1 + hob RL

0.98 = 0.98 2.2 1+ 2040

Small-Signal, Low-Frequency BJT Amplifiers

261

Ri = hib + hrb AI RL = 21.6 + 2.9 × 10 −4 × 0.98 × 2.2 × 103 = 21.6 + 0.625 = 22.23Ω

AV =AI ×

RL 2.2 = 0.98 × = 98 Ri 0.022

AV = AV ×

Ri 22.23 = 98 × = 4.17 Ri + Rs 22.23 + 500

Yo = hob −

hfb hrb 0.98 × 2.9 × 10 −4 = 0.49 × 10 −6 + = 10 −6 (0.49 + 0.545) ( Rs + hib ) 500 + 21.6

s

= 1.035 × 10 −6 mhos Ro =

1 106 = = 966.18 kΩ Yo 1.035

6.9 COMPARISON OF PERFORMANCE OF CE, CC, AND CB AMPLIFIERS In the preceding sections, we have calculated the performance quantities of CE, CC, and CB amplifiers. It was found that a CE amplifier has large AI and AV but has small Ri and medium Rο . Ri and Ro account for a reduced output voltage. The CE amplifier can be used as a voltage amplifier as well as a current amplifier. In the case of a CC amplifier, AI is large and AV ≈ 1. But this amplifier has large Ri and very small Ro . This amplifier ensures that the input is transmitted to the output terminals with the same magnitude and with the same phase. We can see that this amplifier is used as a voltage buffer amplifier. A CB amplifier has AI ≈ 1 but has a larger AV . Here again, there is no phase inversion. The output and the input are in the same phase. However, a CB amplifier has very small Ri and large Ro . Hence, the overall output gets reduced. It can be seen that this amplifier is used as a current buffer amplifier. The performance quantities calculated earlier for all these three configurations are tabulated in Table 6.3, for RL = 2.2 kΩ and Rs = 500 Ω. Table 6.3 Comparison of performance quantities of CE, CC, and CB amplifiers Amplifier configuration

AI

CE

−94.79

CC

95.73

CB

0.98

Ri (kW) 1.048 211.7 0.02223

AV −198.99 0.995 98

Ro (kW) 106.67 0.01587 966.18

262

6.10

Electronic Devices and Circuits

RELEVANCE OF INPUT AND OUTPUT RESISTANCES

We calculated the input and output resistances of the three basic topologies, namely, CE, CC, and CB. Now the pertinent question is:should the amplifier have small input resistance, or should it have large input resistance? Similarly, should an amplifier have small output resistance or should it have large output resistance? The answers to these questions depend on the type of signal drive used at the input and the type of signal desired at the output. We classify small signal amplifiers into four kinds based on these considerations: (i) voltage amplifiers, (ii) current amplifiers, (iii) transconductance amplifiers, and (iv) transresistance amplifiers. These four classes of amplifiers are discussed elaborately in feedback amplifiers in Chapter 9.

6.10.1 Voltage Amplifier A voltage amplifier, also called a voltage-controlled voltage source (VCVS), is one in which the driving signal is a voltage and the desired signal at the output is a voltage. The constant proportionality is voltage gain AV , which is independent of Rs and RL (see Figure 6.35). The voltage gain AV is denoted by Eqn. (6.30) and it is a ratio: Rs

AV =

Vo Vi

+

(6.30)

Ri

In a voltage amplifier, output voltage can be written as follows: Vo = AVVi

Vs

+

Ro +

RL

Vi

Vo

A vVi

−

Figure 6.35 Voltage amplifier

Ideally, in a voltage amplifier, Ri = ∞ for the entire Vs to appear across Ri and Ro = 0 for the entire output to appear across RL. In practice, however, Ri >> Rs and Ro > Ro. However, to ensure maximum power transfer from generator to the load, as per the maximum power transfer theorem, Ro = RL . Therefore, in circuits called power amplifiers, there arises the need to provide an impedance matching transformer. We shall discuss power amplifiers later.

263

Small-Signal, Low-Frequency BJT Amplifiers

6.10.2 Current Amplifier Alternately, consider another amplifier called the current amplifier, also called current-controlled current source (CCCS), in which the output current I o is proportional to the input current I s . The constant of proportionality is the current gain AI (see Figure 6.36). The current gain AI is denoted by Eqn. (6.31) and it is a ratio: Ii

AI =

Io Ii

(6.31)

Io

+

A iIi

Is Rs

In a current amplifier, output current can be written as follows:

RL

Ri

I o = AI I i

Vo

Ro

Figure 6.36 Current amplifier

Ideally in this case, Ri = 0 so that the entire I s flows through Ri and Ro = ∞ so that the entire AI I i flows through RL . However, in practice, Ri > RL . This means that if the driving signal is a current for the entire signal to flow through the actual input terminals of the amplifier, the amplifier chosen should have small Ri . Similarly, if the desired signal at the output is a current, for this current to flow through the load, the amplifier chosen should have large Ro.

6.10.3 Transconductance Amplifier On similar lines, we have transconductance amplifier, also called voltage-controlled current source (VCCS), in which the desired output signal is a current I o, and the driving signal is a voltage Vs (see Figure 6.37). The transconductance Gm is denoted by Eqn. (6.32), and it is measured in mhos: Gm =

Rs

Io Vi

Io

(6.32)

+

+ +

In a transconductance amplifier, output current can be written as follows:

Ri

Vi G mVi

Ro

RL

Vo

−

Vs

I o = GmVi Figure 6.37 Transconductance amplifier

6.10.4 Transresistance Amplifier

Last, we have the transresistance amplifier, also called the current-controlled voltage source (CCVS), in which the desired output signal is a voltage Vo and the driving signal is a current I s (see Figure 6.38). The transresistance Rm is denoted Ii by Eqn. (6.33), and it is measured in ohms: V Rm = o Ii

+

Ro

(6.33)

Is

+ Rs

Ri

R mIi

RL

In a transresistance amplifier, the output voltage can be written as follows: Vo = Rm I i

Figure 6.38 Transresistance amplifier

Vo

264

Electronic Devices and Circuits

The amplifiers discussed till now, namely, CE, CC, and CB will not satisfy all the requirements of large AI , large AV , and large or small Ri or Ro . Hence, there arises the need to cascade these three basic amplifiers to derive the necessary performance quantities.

6.11

DISTORTION IN AN AMPLIFIER

Distortion may be present in the output of an amplifier due to various factors. Some of the factors responsible for distortion are discussed in the sections that follow.

6.11.1 Harmonic Distortion As long as the operation of the transistor is restricted to a small region around the operating point, in which the transfer characteristic can be representd by a straight line, the amplifier is free from harmonic distortion. This means that if the input is sinusoidal, the output is also sinusoidal but with an enlarged magnitude. The frequency of the signal in the output is the same as the frequency of the signal at the input. There is no distortion in the amplifier. However, if the amplitude of the input is increased, the operation is no longer restricted to the linear region in the transfer characteristic, and its operation extends into the nonlinear region. The operation in the nonlinear region, obviously, results in distortion in the output. This means that though the input is sinusoidal, the output is no longer sinusoidal, but is distorted in waveshape, as indicated in Figure 6.39. Amplitude distortion gives rise to harmonic distortion. Harmonic distortion essentially means that output contains frequency components that are not present in the input. We have described harmonic distortion here graphically. Now, the presence of additional frequency components in the output can be shown mathematically. Let us assume that the transfer characteristic is represented by a parabola with the operating point as its vertex. Let the instantaneous value of input base current ib be written as follows: IC

IC(sat)

A IC1

Q1

IC1 =

wt

IC(sat) 2

B IB

0 0

wt

Figure 6.39 Amplitude distortion in an amplifier

Small-Signal, Low-Frequency BJT Amplifiers

265

ib = I m coswt The equation of the parabola is written as follows: ic = G1ib + G2 ib2 Substituting for ib in the above equation gives the following: ic = G1I m cos wt + G2 I m2 cos 2 wt A few mathematical manipulations indicate additional frequency components in the output current: G I2 ic = G1I m cos wt + 2 m (1 + cos 2 wt ) 2 ic =

G2 I m2 G I2 + G1I m cos wt + 2 m cos 2 wt 2 2

ic = Bo + B1 cos wt + B2 cos 2 wt Here, Bi are constants, where i = 0, 1, ... 2. Thus, it can be noted that the output contains, in addition to the required fundamental component B1 , an additional unwanted dc component B0 and a harmonic component B2. Thus operation of the transistor in the nonlinear region of the transfer curve gives rise to harmonic distortion. Higher order harmonics can also be present in the output. In general, if ic is expressed as a power series, ic = Bo + B1 cos wt + B2 cos 2 wt + B3 cos 3 wt + B4 cos 4 wt + ...

(6.34)

Thus, harmonic components can be present in the output of the amplifier having amplitudes: Bi , i = 1, 2, ... n. Usually, higher order harmonics are the worst culprits.

6.11.2 Noise Random variations in the output currents of electric circuits and amplifiers are called noise. These fluctuations are mainly due to (i) particle nature of the electric currents and (ii) variations in path, recombination rates, and diffusion caused by randomness of the charge movement. In general, noise can be due to two main factors: (i) Noise generated by sources external to the circuits such as lightning or localized electrical arcs or discharges. This type of noise is present typically below 20  MHz. (ii) Noise generated in the circuits due to internal phenomena. This type of noise is present typically above 20 MHz in the form of a hissing sound or snow.

Noise in Amplifiers Thermal Noise Thermal noise is developed due to random thermal motions and collisions of the charges and the atoms in all conductors. Thermal noise due to resistance R is given as Vn = 4 kTRB where k = Boltzmann’s constant = 1.38 × 10 −23 J/K , T is temperature in K, and B is the bandwidth in hertz.

266

Electronic Devices and Circuits

Shot Noise Shot noise arises because of the random nature of charge diffusion across a junction. This noise is present uniformly in the frequency spectrum. Flicker Noise Flicker noise is due to random variations in the charge diffusion processes and is usually present below 1 kHz. This noise varies inversely with frequency, and hence is also called 1 f noise.

6.11.3 Intermodulation Distortion If two or more signals are applied as inputs to an amplifier and if the operation is not limited to the linear region of the transfer characteristic, then because of the nonlinearity of the transfer curve an additional distortion may be present in the output due to some and difference frequencies. This type of distortion is called intermodulation distortion. Let the input to the amplifier be vi = V1 sin w1t + V2 sin w 2 t Then using the Taylor series 2

iC = I C + a1 (V1 sin w1t + V2 sin w 2 t ) + a2 (V1 sin w1t + V2 sin w 2 t ) + ... This simplifies to a2 2 V1 + V22 + aV 1 1 sin w1t + aV 1 2 sin w 2 t 2 aV2 aV2 − 2 1 cos 2w1t − 2 2 cos 2w 2 t 2 2 + a2VV w − w cos ( 1 2 1 2 ) t − a2VV 1 2 cos (w1 + w 2 ) t

iC = I C +

(

)

Thus, the output contains an additional dc component, the desired fundamental frequencies w1 and w 2 , harmonic terms 2w1 and 2w 2 , and additional sum and difference frequencies (w1 + w 2 ) and (w1 − w 2 ).

6.12 TRANSCONDUCTANCE MODEL OF THE TRANSISTOR Using the CE amplifier with approximate model for the transistor as shown in Figure 6.23 AV =

vo −hfe I b RL −hfe = = RL vi hie I b hie Ic

B +

(6.35)

Vi = Vbe

C +

Ib

Io

hie

RL gm Vbe

Vo

E

Figure 6.40 CE Amplifier with Transconductance Model for the Transistor

Small-Signal, Low-Frequency BJT Amplifiers

267

Using the definitions of hfe and hie,  Ic    hfe  I b  I = c = hie  Vbe  Vbe    Ib 

(6.36)

Equation (6.36) relates current I c in the output and voltage Vbe in the input and is called transconductance, gm I gm = c or I c = gmVbe (6.37) Vbe Also from Figure 6.23, I c = hfe I b

(6.38)

I c = hfe I b = gmVbe

(6.39)

From Eqs (6.37) and (6.38),

Hence, the equivalent circuit in Figure 6.23 can be replaced by the equivalent circuit in Figure 6.40.

6.13

FREQUENCY RESPONSE CHARACTERISTIC OF AN AMPLIFIER

Let the input to a voltage amplifier be a speech signal through a microphone as in a public address system. The output of the voltage amplifier is fed to a power amplifier that ultimately drives an electromechanical device such as a loud speaker. The speech signal contains a number of frequency components with varying amplitudes. As a result, if one wants to find out which frequency component is amplified by what amount, it becomes a difficult task. It is for this reason we normally consider a sinusoidal signal to find the response of the amplifier. This method is repeated for all possible frequency components present in the input. Dealing with a singlesinusoidal signal is the simplest of the cases. We select a signal of one frequency with constant amplitude, find out the output of the amplifier. Now, the frequency is changed, keeping the input amplitude the same as in the earlier case, find out the output. This procedure is repeated in the range of frequencies of interest. Ideally, whatever may be the frequency component of the signal at the input, as long as the amplitude is the same, the output should be the same, as labeled as “curve-1” in Figure 6.41. In this case, the relation A = Vo Vi is valid and Vi is constant. However, in an amplifier, we have coupling capacitance CC (shown in Figure 6.42) and a stray shunt capacitance Cs (shown in Figure 6.43). The coupling capacitance CC degrades the low-frequency response and the shunt capacitance Cs degrades the high-frequency response. The degraded curved portions of the frequency response are labeled “curve-2,” as shown in Figure 6.41. Now, it becomes necessary to find out the frequency range in which the amplifier can be used so that the output almost remains the same. For this, we define two frequencies, f1 and f2, at which the power is P 2, where P is the power in the mid-band range. P is given as Vm2 RL, where Vm is the voltage in the mid-band range and RL is the load into which the power is dissipated. Readers may note that the frequency response curve is drawn for the output voltage of the amplifier. However, since the input is constant, it can be plotted for the gain. The maximum value of the gain is Am and a horizontal dotted line is drawn at 0.707 Am on this response, and obtained frequencies f1 and f2 . Then, the power at f1 and f2 can be given by the following expression:

268

Electronic Devices and Circuits

Vm

Am

P

Curve1 P/2

0.707Am

2

0

f1 is the lower half power (3dB) frequency

Vm Curve2

f2

f1

f2 is the upper half power (3dB) frequency

f

Bandwidth

Figure 6.41 Frequency response characteristic and calculation of bandwidth

(

Vm 2 P Vm2 = = 2 2RL RL

2

)

(6.40)

Therefore, if Vm is the voltage in the mid-band, Vm 2 is the voltage at f1 and f2 . We have located 0.707 Am on the gain axis and have drawn a horizontal line to determine f1 and f2 . The frequency range from f1 to f2 is called the passband or the bandwidth of the amplifier. In simple terms, by bandwidth we mean the frequency range in which the gain and the output of the amplifier almost remain constant as long as the input remains constant. The ratio of the power in the mid-band to that at f1 or f2 is measured in decibels abbreviated as dB in technical literature. Normally, linear gain is a ratio and does not have any units. We use logarithmic gain measured in dB for representing very large and very small values of gain. Logarithmic gain is mathematically defined as follows: P V GdB = 10 log10 2 = 20 log10 2 (6.41) P1 V1 dB power = 10 log10

P = 10 log10 2 = 10 × 0.3010 ≈ 3 dB P 2

Hence, these two frequencies f1 and f2 are also called 3dB frequencies and the bandwidth the 3dB bandwidth. If a frequency component below f1 or above f2 appears at the output along with a frequency component in the mid-band range, the output fluctuates by large amounts. Frequency components outside the prescribed bandwidth are not acceptable. We shall see later that in order to obtain the frequency response characteristic of an amplifier, we divide the frequency range into three ranges, namely, the mid-band range, low-frequency range, and high-frequency range. In the mid-band range, the gain remains almost constant. In the low-frequency range, the gain is influenced by the coupling capacitor Cc . The amplifier behaves like a RC high-pass filter as shown in Figure 6.42. As the frequency increases, the X c of Cc decreases and Vo increases. At low frequencies, the gain assumes a lower value than its mid-band value. In the high-frequency range, the gain is influenced by the shunt capacitor Cs. This shunt capacitance is not an externally connected component in the circuit, and appears due to stray capacitances at high frequencies. Now, the amplifier functions as a RC low-pass filter as shown in Figure 6.43. As the frequency increases, the X c of Cs decreases, and consequently Vo decreases. Thus at high frequencies, the gain assumes a lower value than its mid-band value.

Small-Signal, Low-Frequency BJT Amplifiers

269

Cc R2

+ +

R1

Vo

+

Vs

+ Cs

Vo

Vs −

−

Figure 6.42 Low-frequency response influenced by CC

Figure 6.43 High-frequency response influenced by Cs

We can calculate the lower cut-off frequency from Figure 6.42 as follows:     R1 Vo = Vs    R1 + 1   jwCc  Vo = Vs

R1 1 R1 + j wC c Vo = Vs

where w1 =

1

=

1 1+ jwR1Cc

1 w  1+  1  w

2

=

1 w  1− j  1  w

1

=

f  1+  1   f

2

1 . At f = f1, Cc R1 Vo = Vs

1 1 1+   1

2

=

1 2

Here, f1 denotes the half-power frequency that is also known as lower 3dB frequency. Consider Figure 6.43. This circuit is a low-pass circuit. At low frequencies, X c is large and hence Vo is large. Vo 1 1 = = 2 2 Vs w  f  1+   1+    w2   f2  1 where w 2 = . Cs R2 Vo 1 = . Here, f2 denotes the half-power frequency that is also known as upper Vs 2 3dB frequency. At f = f2 ,

270

Electronic Devices and Circuits

6.14 TRANSISTOR h -PARAMETER CONVERSION Normally, CE h-parameters are listed in the datasheets supplied by the manufacturer. If the amplifier under consideration is a CB amplifier, then the CB h-parameters are required to be obtained in terms of CE h-parameters. Alternatively, if the CB h-parameters are specified, then it becomes necessary to derive the CE h-parameters in terms of CB h-parameters. In general, it may be required to obtain h-parameters of one configuration in terms of h-parameters of a different configuration. The procedure for h-parameter conversion is discussed in this section.

6.14.1 CE h-Parameters in Terms of CB h-Parameters To obtain hie, hre, hfe, and hoe in terms of CB parameters, the CB equivalent circuit is drawn as shown in Figure 6.44 and is now represented as a CE configuration as shown in Figure 6.45. The relevant CE parameters are evaluated as per the definitions of these parameters. Ie

hib

Ic C

E +

hfb Ie

+

Veb

+ hob

hrb Vcb

−

Vcb

−

− B

Figure 6.44 CB equivalent circuit

hfbIe B

Ib

Ic

Y

Ic

X +

−

Ie

hob

C

I

+

hrbVcb Vbe

+

+

Vbc

−

Vce

hib −

− E

Figure 6.45 Circuit of Figure 6.44 drawn in CE configuration

(i) hie is defined as follows: hie =

Vbe Ib

Vce =0

From Figure 6.44, Veb = hib I e + hrbVcb

(6.42)

I c = hfb I e + hobVcb

(6.43)

and

Small-Signal, Low-Frequency BJT Amplifiers

271

From Figure 6.45, (6.44)

Vce = Vcb + Vbe To get hie , set Vce = 0 then from Eqn. (6.44), 0 = Vcb + Vbe or Vcb = −Vbe = Veb

(6.45)

Substituting Eqn. (6.45) in Eqn (6.42), Vcb = hib I e + hrbVcb Ie =

Vcb (1 − hrb )

(6.46)

hib

From Figure 6.45, I b + I c + I e = 0 or −I b = I c + I e

(6.47)

Substituting Eqn. (6.43) in Eqn. (6.47), −I b = hfb I e + hobVcb + I e = I e (1 + hfb ) + hobVcb

(6.48)

Substituting Eqn. (6.46) in Eqn. (6.48),  V (1 − hrb )  −I b =  cb  (1 + hfb ) + hobVcb hib    (1 − hrb ) (1 + hfb ) + hob hib −I b =  hib 

 Vcb 

But, from Eqn. (6.45), Vcb = −Vbe Therefore,  (1 − hrb ) (1 + hfb ) + hob hib −I b =  hib  Hence, hie =

(6.49)

  ( −Vbe ) 

Vbe hib = I b (1 − hrb ) (1 + hfb ) + hob hib

(6.50)

If hrb > hob hib , then Eqn. (6.51) reduces to hie ≈

hib 1 + hfb

(6.52)

272

Electronic Devices and Circuits

Equation (6.50) gives the exact value of hie, whereas Eqn. (6.52) gives the approximate value. (ii) hre is defined as follows: hre =

Vbe Vcb

Ib = 0

To get hre, set I b = 0 . From Eqn. (6.47), I c = −I e Substituing this value in Eqn. (6.43), −I e = hfb I e + hobVcb or I e (1+ hfb ) = −hobVcb Hence, Ie =

−hobVcb 1 + hfb

(6.53)

Substituting Eqn. (6.53) in Eqn. (6.42),  −h V Veb = hib  ob cb  1 + hfb

  − hib hob  + hrb Vcb  + hrbVcb =    1 + hfb 

 h h − h (1 + hfb )  h h  Vbe =  ib ob − hrb Vcb =  ib ob rb Vcb 1 + hfb  1 + hfb   

(6.54)

We know that, Vce = Vcb + Vbe. Hence, (6.55)

Vcb = Vce −Vbe Substituting Eqn. (6.55) in Eqn. (6.54),  h h − h (1 + hfb )  Vbe =  ib ob rb  (Vce −Vbe ) 1 + hfb    h h − h (1 + hfb )  Vbe =  ib ob rb Vce 1 + hfb  

 h h − h (1 + hfb )  −  ib ob rb Vbe 1 + hfb  

  h h − h (1 + hfb )    hib hob − hrb (1 + hfb )  Vbe 1 +  ib ob rb   =  Vce  1 + hfb 1 + hfb       hib hob − hrb (1 + hfb )    1 + h fb Vbe   hre = = Vce  (1 + hfb ) (1 − hrb ) + hib hob    1+ hfb  

Small-Signal, Low-Frequency BJT Amplifiers

hre =

hib hob − hrb (1 + hfb )

(1 + hfb ) (1 − hrb ) + hib hob

273

(6.56)

If hrb > hob hib , then Eqn. (6.57) reduces to hre =

hib hob − hrb (1 + hfb )

(1 + hfb )

=

hib hob −h (1 + hfb ) rb

(6.58)

Equation (6.56) gives the exact value of hre , whereas Eqn. (6.58) gives its approximate value. (iii) hfe is defined as follows: hfe =

Ic Ib

Vce =0

From Figure 6.45, writing the KCL equation at node X, I c + I − hfb I e = 0 I c = hfb I e − I (6.59)

I c = hfb I e + hobVbc Writing the KVL equation of the outer loop, Vbe = Vbc + Vce With Vce = 0,

(6.60)

Vbe = Vbc = −Vcb From the input loop Ie =

− (Vbe + hrbVcb )

(6.61)

hib

But from Eqn. (6.60), Vbe = −Vcb . Ie =

− ( −Vcb + hrbVcb ) hib

=

Vcb (1 − hrb ) hib

Substituting Eqn. (6.62) in Eqn. (6.59),  Vcb (1 − hrb )   hfb (1 − hrb )  I c = hfb I e + hobVbc = hfb  + hob  + hobVcb = Vcb   hib hib    

(6.62)

274

Electronic Devices and Circuits

 h (1 − hrb ) + hob hib I c = Vcb  fb hib 

  

(6.63)

Writing the KCL equation at node Y, I b + I c + I e = 0 or I b = −I c − I e

(6.64)

Substituting Eqs (6.62) and (6.63) in Eqn. (6.64),  h (1 − hrb ) + hob hib I b = −Vcb  fb hib 

  1 − hrb   −Vcb    hib  

 h (1 − hrb ) + hob hib + (1 − hrb )   (1 − hrb ) (1 + hfb ) + hob hib I b = −Vcb  fb  = −Vcb  hib hib    Hence,

  

 h (1 − hrb ) + hob hib  Vcb  fb  hib I   hfe = c = Ib  (1 − hrb ) (1 + hfb ) + hob hib  −Vcb   hib   hfe = −

hfb (1 − hrb ) + hob hib

(1 − hrb ) (1 + hfb ) + hob hib

(6.65)

Eqn. (6.65) gives the exact value of hfe . If hrb > hob hib , then Eqn. (6.66) reduces to hfe =

−hfb 1 + hfb

(6.67)

Equation (6.67) gives the approximate value of hfe. (iv) hoe is defined as follows: hoe =

Ic Vce

I b =0

To get hoe , set I b = 0 From Eqn. (6.47), I c = −I e . Substituting this value in Eqn. (6.43), I c = −hfb I c + hobVcb or I c (1+ hfb ) = hobVcb

Small-Signal, Low-Frequency BJT Amplifiers

275

Hence, Ic =

hobVcb 1 ( + hfb )

(6.68)

Substituting Eqn. (6.68) in Eqn. (6.42), and since Ie = −Ic Veb = hib I e + hrbVcb  −h h  −h V   Veb = hib  ob cb  + hrbVcb =  ib ob + hrb Vcb  (1 + h )   (1 + h )  fb  fb     h h  Vbe =  ib ob − hrb Vcb  (1 + h )  fb  

(6.69)

Vce = Vcb + Vbe

(6.70)

We know that

Substituting Eqn. (6.69) in Eqn. (6.70),  h h  Vce = Vcb +  ib ob − hrb Vcb  (1 + h )  fb      (1 + hfb ) + hib hob − hrb (1 + hfb )  h h Vce = 1 + ib ob − hrb Vcb =  Vcb  (1 + h )   (1 + hfb ) fb      (1 + hfb ) (1 − hrb ) + hib hob Vce =   (1 + hfb ) 

 Vcb 

(6.71)

From Eqn. (6.68) and Eqn. (6.71),

hoe =

hobVcb (1 + hfb )

Ic = Vce  (1 + hfb ) (1 − hrb ) + hib hob  (1 + hfb ) 

 Vcb 

=

hob (1 + hfb ) (1 − hrb ) + hib hob

(6.72)

Equation (6.72) gives the exact value of hoe. If hrb > hob hib, then Eqn. (6.73) reduces to hoe =

hob 1 + hfb

Equation (6.74) gives the approximate value of hoe.

(6.74)

276

Electronic Devices and Circuits

On similar lines, it is possible to convert parameters of one configuration into the other. The simplified parameters are listed in Table 6.4. Table 6.4 h-parameter conversion Parameter

CE configuration

CC configuration

CB configuration

hie

–

hic

hib 1 + hfb

hre

–

1 − hre

hib hob − hrb 1 + hfb

hfe

–

− (1 + hfe )

− hfb 1 + hfb

hoe

–

hoc

hob 1 + hfb

hic

hie

–

hib 1 + hfb

hrc

(1 − hre ) ≈ 1

–

hfc

6.15

− (1 + hfe )

≈1

–

−1 1 + hfb

hoc

hoe

–

hob 1 + hfb

hib

hie 1 + hfe

−hic hfc

–

hrb

hie hoe − hre 1 + hfe

hfb

− hfe 1 + hfe

hob

hoe 1 + hfe

hrc − 1 −

−

hic hoc hfc

(1 + hfc ) hfc

−

hoc hfc

–

– –

CE AMPLIFIER WITH UN-BYPASSED EMITTER RESISTANCE

A CE amplifier with un-bypassed emitter resistance is shown in Figure 6.46 and its ac circuit is shown in Figure 6.47(a). To calculate its gain, Ri and Ro , we replace the transistor by its low-frequency approximate model indicated in Figure 6.47(b).

277

Small-Signal, Low-Frequency BJT Amplifiers VCC

IC

RL

R1 0

+ VC

IB

Cc

Cc 0

Vc

+

+ −

VBE

+

+

Vs

Vo

R2 V2 −

RE

Figure 6.46 CE amplifier with un-bypassed RE

Ic 0 +

B

0

+

Io

C

Ic +

Ib hie

Ib

RL

+ Ro

Vo

Vo

hfeIb

E

Vs

RL Io

Vs

Ri

Ib RE

hfeIb RE

−

− Ri

(a) The ac equivalent circuit of Figure 6.46

(b) The equivalent circuit

Figure 6.47 Equivalent circuit of Figure 6.46

Writing the KVL equation of the input loop, Vs = I b hie + ( I b + hfe I b ) RE = I b ( hie + (1 + hfe ) RE ) Ri =

Vs = hie + (1 + hfe ) RE Ib

(6.75)

278

Electronic Devices and Circuits

AI =

I o − hfe I b = = − hfe Ib Ib

(6.76)

 R  RL AV = AI  L  = − hfe    Ri   hie + (1 + hfe ) RE

  

(6.77)

Since (1+ hfe ) RE >> hie and also since hfe >> 1, hie + (1 + hfe ) RE ≈ hfe RE Therefore, Eqn. (6.77) reduces to AV ≈ −

hfe RL R =− L hfe RE RE

(6.78)

To find Ro, open RL and look into the output terminals. The resistance seen is the output 1 resistance, Figure 6.48. Since hfe I b is an ideal current source as = ∞ , Ro = ∞. hoe Ro′ = Ro || RL = RL B

C

+ I b

(6.79) Io +

hie hfeIb E

Vs Ib

Vo open RL

hfeIb RE

− Ro

Figure 6.48 Circuit to find Ro

6.16

MILLER’S THEOREM AND ITS DUAL

Consider circuit in Figure 6.49 which is essentially a feedback amplifier. The drop across RE , which we call as Vf is fed back to the input in phase opposition to the input voltage Vs . In order to illustrate the principle of feedback, we also make use of the amplifier depicted in Figure 6.50 where collector to base feedback bias is used. The two circuits in Figures 6.49 and 6.50 are feedback amplifiers. Feedback amplifiers are discussed in more detail in Chapter 9. These two feedback amplifier circuits can be converted into amplifier circuits without feedback by using Miller’s theorem and its dual.

Small-Signal, Low-Frequency BJT Amplifiers

279

R′ + +

Rs

If

Io

Rs

Io Ib

Is Ib

RL

+

RL

+

Vo

+ Vo

Vs

Vs Vf

RE

− −

Figure 6.50 Amplifier with R′ between the output and the input

Figure 6.49 CE amplifier with un-bypassed RE

We use the diagram in Figure 6.51 to introduce Miller’s theorem. According to Miller’s theorem if in a network there are n nodes, with node 1 as the input node, node 2 as the output node, and node N as the reference node, then the resistance R ′ connected between the input and output nodes can be replaced by two resistances R1 and R2 —the former connected in shunt with the input terminals and the latter connected in shunt with the output terminals. By using Miller’s theorem, it is possible to reduce a feedback amplifier into an amplifier without feedback. Then we can use the relations already derived to calculate the performance quantities. I1

I2

R′

I1 1 V1

2 V2

I2 1 V1

2 V2

R1 N

R2

N

Figure 6.51 Miller’s theorem

Let us calculate I1 .  V  V1 1 − 2   V1  V1 (1 − AV ) V − V2 = = I1 = 1 = R′ R′ R′ where R1 =

R′ 1 − ( AV )

V V1 = 1 R′ R1 (1 − AV )

(6.80)

(6.81)

280

Electronic Devices and Circuits

Similarly,   V  1  V2  1 − 1  V2 1 −  AV   V2  V − V1 = I2 = 2 = = R′ R′ R′

V2 V = 2 R′ R2  1  1 − A  V

(6.82)

where R2 =

R′  1  1 − A  V

(6.83)

and AV is the voltage gain. R1 and R2 draw the same currents I1 and I 2 from nodes 1 and 2 as R ′ has drawn from nodes 1 and 2. Miller’s theorem is valid with impedances also. Using Miller’s theorem, the circuit in Figure 6.50 is redrawn as in Figure 6.52. The circuit in Figure 6.52 is an amplifier circuit without feedback.

+ Rs

R2

+

RL Vo

R1 Vs −

Figure 6.52 Circuit of Figure 6.50 using the Miller’s theorem

The dual of the Miller’s theorem states that a resistance R ′ connected between node 3 and the reference node N can be replaced by two resistances R1 and R2 —the former connected in series with input node 1 and the latter connected in series with the output node 2 as indicated in Figure 6.53. R1 = R ′ (1 − AI )

(6.84)

 A − 1 R2 = R ′  I  AI 

(6.85)

and

Here, AI is the current gain. Let us compare Eqs (6.81) and (6.84), which deal with Miller theorem and its dual. R ′ is divided (1− AV ) in Eqn. (6.81). R ′ is multiplied by (1− AI ) in the dual as shown in Eqn. (6.84).

Small-Signal, Low-Frequency BJT Amplifiers

1

2

R1

1

2

281

R2

3 R′ N N

Figure 6.53 Dual of the Miller’s theorem

 A − 1  R′ R′ and Eqn. (6.85), R2 = R ′  I  . , which was 1  AI  1− AV AV AI multiplied by in Eqn. (6.83) is divided by in the dual, Eqn. (6.85). AV −1 AI −1 Similarly, compare Eqn. (6.83), R2 =

6.17

ANALYSIS OF THE AMPLIFIER CIRCUIT USING THE DUAL OF THE MILLER’S THEOREM

The circuit in Figure 6.49 can now be redrawn as in Figure 6.54, using the dual of the Miller’s theorem (Figure 6.53). The feedback amplifier is converted into an amplifier without feedback. R2 = R ′(A I−1)/A I

Rs R1 = R ′(1−A I) Ib +

Io

Ic +

RL Vo

Vs − Ri

Figure 6.54 Circuit of Figure 6.53 redrawn using the dual of the Miller’s theorem

Let us now consider the CE amplifier with un-bypassed emitter resistance shown in Figure 6.49. This circuit is redrawn as in Figure 6.54 using the dual of the Miller’s theorem. We can now calculate the performance quantities. From Eqn. (6.84) and (6.85),  A − 1 R1 = R ′ (1 − AI ) and R2 = R ′  I  AI 

282

Electronic Devices and Circuits

From Figure 6.54, the load for the amplifier is  A − 1 RL′ = R2 + RL = R ′  I + RL  AI  The current gain, AI AI =

− hfe = 1 + hoe RL

− hfe   AI − 1  1 + hoe  R′  + RL     AI  

AI + hoe R ′ ( AI − 1) + AI hoe RL = − hfe AI (1+ hoe (RL + R ′ )) = hoe R ′ − hfe AI =

hoe R ′ − hfe 1 + hoe (RL + R ′ )

(6.86)

If hoe R ′ VG , VGS becomes negative. The advantage with voltage divider bias is that if for any reason ID increases, VGS becomes more negative, and thus reduces ID to the desired level. Thus, ID is stabilized. RD is usually chosen as a large value so as to get a large output. Also RS is chosen to be large on the consideration of bias stability. To achieve these twin objectives, generally RD and RS are chosen as the same values, that is RD = RS. In order to locate the Q-point, we first draw the transfer curve and draw the straight line using Eqn. (7.25). Where this line intersects, the transfer curve is the Q-point (Figure 7.35).

FET Characteristics, Biasing, and FET Amplifiers

ID

RD R1

D

IG = 0 VG

R2

G + VGS

R1

+

IG = 0

VDD

VDS S−

− + VS −

ID

RD

VD

G + VGS

VG +

VDD

R2

RS ID

D

− (a)

− + VS

325

VD + VDS S−

VDD

RS ID

− (b)

Figure 7.34 Voltage divider bias arrangement of an n-channel FET

To draw the straight line, we need two points. We get these two points using Eqn. (7.25). (i) Set VGS = 0, then, ID = VG/RS (point A) (ii) Set ID = 0, then VGS = VG (point B) ID IDSS

Q

IDQ ID = VG/RS B

IDSS/2 IDSS/4 VGSQ

A

−VGS VP

VP/2

0.3VP

0

VGS = VG

Figure 7.35 Locating the Q-point for the voltage divider bias circuit

The coordinates of the Q-point are VGSQ and IDQ. The advantage with voltage divider bias is that it stabilizes ID. Example 7.6 For the voltage divider bias circuit shown in Figure 7.34, VDD = 20 V, R1 = 2 MΩ, R2 = 0.4 MΩ, RD = 2 kΩ, RS = 1 kΩ, IDSS = 10 mA, and VP = −6 V (i) find IDQ, VGSQ. Calculate VD, VS, and VDS and (ii) repeat for RS = 4 kΩ.

Solution: VG = VDD

R2 0.4 = 20 × = 3.33 V R1 + R2 2 + 0.4

326

Electronic Devices and Circuits

The transfer curve is plotted in Figure 7.36. ID (mA) 10 IDSS

Q1 5.1

5 IDSS/2 3.3 2.5 IDSS/4

Q2

1.8

−3.7 −VGS (V)

VP = −6

RS = 1

RS = 4

−1.6

−1.8 −3 0.5 VP 0.3 VP

0

VG = 3.33 V

Figure 7.36 Transfer curve and locating Q1 and Q2

(i) The straight line for RS = 1 kΩ is plotted by locating two points, namely, VG = 3.33 V on ID = 0 axis and ID = 3.3 mA (= VG/RS) on the VGS = 0 axis. The coordinates of Q1 are IDQ1 = 5.1 mA and VGSQ1 = −1.6 V VS = IDQ1RS = 5.1 × 1 = 5.1 V, VD = VDD − IDQ1RD = 20 − (5.1)(2) = 9.8 V and VDS = VDD − IDQ1 (RS + RD) = 20 − (5.1)(3) = 4.7 V. The value of ID can be theoretically calculated as follows: 2

 V  ID = IDSS 1 − GS  and VGS = VG−IDRS  VP  2  (V − I R )   V I R   3.33 I D × 1 ∴ I D = I DSS 1 − G D S  = I DSS 1 − G + D S  = 10 1 − +   −6 −6  VP VP   VP   2

2

2

∴I D = 10 (1 + 0.55 − 0.167 I D ) From the above equation,

0.28 ID2 − 6.18 ID + 24 = 0 The two values of ID are 17.03 mA and 5.03 mA. Choose the second value. Hence, VGS = VG−IDRS = 3.33−(5.03)(1) = −1.7 V. From the graphical method, VGS = −1.6 V. (ii) The straight line for RS = 4 kΩ is plotted by locating two points: VG = 3.33 V on ID = 0 axis and ID = 0.833 mA (= VG/RS) on the VGS = 0 axis. The coordinates of Q2 are IDQ2 = 1.8 mA and VGSQ2 = −3.7 V VS = IDQ2RS = 1.8 × 4 = 7.2 V, VD = VDD − IDQ2RD = 20 − (1.8)(2) = 16.4 V and VDS = VDD − IDQ2 (RS + RD) = 20 − (1.8)(6) = 9.2 V.

FET Characteristics, Biasing, and FET Amplifiers

327

The value of ID can be theoretically calculated as follows: 2  (VG − I D RS )   VG I D RS   3.33 I D × 4  + I D = I DSS 1 − +  = I DSS 1 −  = 10 1 − −6 VP VP  −6    VP   2

2

2

∴ ID = 10 (1.55 − 0.67 I D ) From the above equation,

4.5ID2 − 21.8ID + 24 = 0 The two values of ID are 3.15 mA and 1.69 mA. Choose the second value. Hence, VGS = VG−IDRS = 3.33 − (1.69)(4) = −3.43 V. From the graphical method, VGS = −3.7 V. Example 7.7 For the voltage divider bias circuit shown in Figure 7.34, VDD = 20 V, R1 = 2 MΩ, R2 = 0.5 MΩ, RD = 2 kΩ, and RS = 2 kΩ. Find ID(max), ID(min), VDS(max), and VDS(min). Use the minimum and maximum transfer curves in Figure 7.33. R2 0.5 = 20 × = 4 V. The bias curve is drawn by locating VG = 4.0 V R1 + R2 2 + 0.5 V 4 on the ID = 0 axis and ID = G = = 2 mA, on VGS = 0 axis. The bias curve is drawn using these RS 2 two points, Figure 7.37 and ID(max) and ID(min) are found out: Solution: VG = VDD

VGS(min) = VG − ID(max)RS = 4 − (3.15) (2) = −2.3 V VGS(max) = VG − ID(min)RS = 4 − (2.1) (2) = −0.2 V VDS(min) = VDD − ID(max)RD = 20 − (3.15) (2) = 13.7 V VDS(max) = VDD − ID(min)RD = 20 − (2.1) (2) = 15.8 V IDSS(max) = 10 mA ID Maximum transfer characteristic 5 mA ID(max) = 3.15 mA ID(min) = 2.1 mA 2 mA Minimum transfer characteristic VGS VP(max) = −6 V

−3 V

0 VP(min) = −2 V

VG = 4 V

Figure 7.37 Maximum and minimum transfer characteristics and the bias curve

328

Electronic Devices and Circuits

7.8.4 The Drain Feedback Bias The drain feedback biasing circuit is another biasing circuit that stabilizes ID (Figure 7.38). This circuit is almost similar to the voltage divider bias circuit shown in Figure 7.34, except for the fact that R1 is connected to the drain rather than to the VDD source. As in the case of the voltage divider bias, RS helps in stabilizing ID. Another feature of the drain feedback bias circuit is that if ID increases, the drop across RD, VRD increases, thereby reducing VG. Hence, VGS becomes more negative and ID is brought back to the desired value. Thus in this method of biasing, the voltage drops across RD and RS help in stabilizing ID. The voltage at the drain, VD, is VD = VDD − I D RD

(7.26)

And VG = VD

 R2  R2 = (VDD − I DRD )   R1 + R2  R1 + R2 

(7.27)

Therefore,  R2  VGS = VG − I D RS = (VDD − I DRD )   − I D RS  R1 + R2 

(7.28)

VDD ID

RD + R1

VD

I2 IG = 0

VG

+ VGS

R2 I2

− + VS −

+ VDS − RS ID

Figure 7.38 The drain feedback circuit

7.9

UNIVERSAL TRANSFER CHARACTERISTIC OR THE UNIVERSAL BIAS CURVE

To analyze the biasing circuits, the transfer characteristic was drawn for the given FET and the circuit parameters were determined. If a device with different specifications is used, then it becomes necessary once gain to draw the transfer characteristic for this particular FET. However, if the V I universal transfer characteristic is drawn with GS and D as the variables, then this curve can VP I DSS

FET Characteristics, Biasing, and FET Amplifiers

329

be used to analyze the biasing circuits using FETs with different specifications, since the variables are normalized. From Eqn. (7.1),  V  ID = 1 − GS  I DSS  VP 

2

V ID for GS varying from 0 to 1 are tabulated in Table 7.6, and the universal VP I DSS transfer characteristic is plotted as shown in Figure 7.39. The values of

Table 7.6

VGS VP ID I DSS

V ID as a function of GS VP I DSS 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.0

0.81

0.64

0.49

0.36

0.25

0.16

0.09

0.04

0.01

0

1.0 0.9

ID/IDSS

0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.0 0.9 0.8 0.7

0.6 0.5 0.4 VGS/VP

0.3

0.2 0.1

0

Figure 7.39 Universal transfer characteristic

The utility of the universal transfer characteristic for the analysis of the biasing circuits is illustrated by the following examples. Example 7.8 In the circuit shown in Figure 7.28, the FET has VP = VGS(off) = −6 V (maximum) and IDSS = 10 mA(maximum). Find out IDQ and VDSQ for VGSQ = −1.3 V, using the universal transfer characteristic in Figure 7.39. Solution: (i) To find ID(max) and VDS(min),

330

Electronic Devices and Circuits

VGS 1.3 = = 0.217 VP ( max ) 6 Draw the vertical line at 0.217 (Figure 7.40). This intersects the transfer curve at Q, and the ID corresponding value of = 0.615 I DSS( max ) 1.0 0.9

ID/IDSS

0.8 0.7 Q 0.6

0.615

0.5 0.4 0.3 0.2 0.1 0 1.0

0.9

0.8

0.7

0.6

0.5

0.4

VGS /VP

0.3

0.2

0.1

0

0.217

Figure 7.40 Analysis the fixed bias circuit using the universal transfer characteristic

Therefore, IDQ = 0.615 IDSS = 0.615 × 10 = 6.15 mA VDSQ = VDD − I DQ RD = 20 − (6.15)(2) = 7.7 V Example 7.9 For the self-bias circuit shown in Figure 7.30, RD = 2 kΩ, RS = 2 kΩ, and VDD = 20 V. Find IDQ, VDSQ, and VGSQ. Use the universal transfer curve in Figure 7.39. Solution: To draw the bias curve, we need two points: V I (i) When ID = 0, VGS = VS = −IDRS = 0. Therefore, D = 0 and GS = 0. This is the first point, A. VP I DSS I 2 (ii) When ID = 2 mA, VGS = VS = −IDRS = −2 × 2= −4 V. Therefore, D = = 0.2 and I DSS 10 VGS −4 = = 0.66 . This is the other point, B. VP −6 The line joining these two points is the bias curve. Q is the point where the line intersects the I universal bias curve (Figure 7.41) for which D = 0.18. Therefore, IDQ = 0.18 × IDSS = 0.18 I DSS × 10 = 1.8 mA. Hence, VDSQ = VDD − I D ( RD + RS ) = 20 − (1.8)(2 + 2) = 12.8 V. And VGSQ = IDQ RS = − (1.8) 2 = −3.6 V (Figure 7.30).

FET Characteristics, Biasing, and FET Amplifiers 1.0 0.9

331

ID/IDSS

0.8 0.7 0.6 0.5 0.4 0.3 B

0.2 0.18 0.1

Q 1.0 0.9 0.8 0.7

0.6 0.5

0.4

0.3

0.2 0.1

A 0 0

VGS/VP

Figure 7.41 Analysis of the self-bias circuit using the universal bias curve

From the above curve,

VGS = 0.595. Therefore, VGSQ = 0.595 × ( −6 ) = −3.57 V VP

Example 7.10 For the voltage divider bias circuit shown in Figure 7.34, VDD = 20 V, R1 = 2 MΩ, R2 = 0.5 MΩ, RD = 2 kΩ, and RS = 2 kΩ. VP = 6 V and IDSS = 10 mA. Find IDQ, VDSQ and VGSQ.. Use the universal transfer curves in Figure 7.39. Solution: VG = VDD

R2 0.5 = 20 × =4V R1 + R2 2 + 0.5

VGS = VG − I D RS (i) When VGS = 0,

VGS = 0. VP

Also, I D RS = VG . Therefore, I D =

VG 4 = = 2 mA RS 2

Hence, When

VGS I = 0, D = 0.2 . This is the first point, A, to draw the bias curve VP I DSS

VGS = 0.5, VGS = 0.5 VP = 0.5 × − 6 = −3 V. VP From Figure 7.34, (ii) When

I D RS = VG −VGS = 4 − ( −3 ) = 7 V

332

Electronic Devices and Circuits

Therefore, ID =

I D RS 7 = = 3.5 mA RS 2

Hence, ID 3.5 = = 0.35 I DSS 10 Thus, the second point to plot the bias curve is B, when VGS = 0.5, VP

ID = 0.35 I DSS

The bias curve is drawn joining points A and B. Q is the point at which the bias curve intersects I the universal transfer curve (Figure 7.42). At Q, D = 0.33 I DSS Therefore, I DQ = 0.33I DSS = 0.33 × 10 = 3.3 mA Hence, VDS = VDD − I DQ ( RD + RS ) = 20 − 3.3 ( 2 + 2 ) = 6.8 V And VGS = 0.425 VP Therefore, VGSQ = 0.425 ×VP = 0.425 ×VP = ( 0.425 ) ( −6 ) = −2.55 V 1.0 0.9

ID/IDSS

0.8 0.7 0.6 0.5 0.4 0.35 0.33 0.3

B Q

0.2

A

0.1

0.425 1.0 0.9 0.8 0.7

0.6 0.5 0.4 0.3 VGS /VP

0.2 0.1

0

0

Figure 7.42 Analysis of the voltage divider bias circuit using the universal bias curve

FET Characteristics, Biasing, and FET Amplifiers

7.10

333

FET AS A VOLTAGE VARIABLE RESISTANCE OR VOLTAGECONTROLLED RESISTANCE

From the characteristics of the n-channel JFET in Figure 7.43, it can be seen that to the left of VP ID increases linearly and the value of ID becomes smaller as VGS becomes more and more negative. We can infer from this that JFET behaves as a VCR, the value of this resistance becomes larger as VGS becomes more and more negative. Ohmic

Saturation region

Break down

ID (mA) 20 IDSS

“knee”

VGS = 0 VGS = −1 V

15 VGS = −2 V 10

VGS = −3 V

5

VGS = −4 V VGS = −VP

0

VP

VDS (V)

Figure 7.43 Output characteristic V–I curves of an n-channel JFET

The characteristics curves show four different regions of operation for a JFET, and these are given as follows: (i) Ohmic region – When VGS = 0, the depletion layer of the channel is very small and the JFET acts like a VCR. (ii) Cut-off region – This is also known as the pinch-off region where VGS ( = V P enough to make I D ≈ 0 , because the channel resistance is maximum.

) is negative

(iii) Saturation region – This is also known as active region. In this region, ID is controlled by VGS . VDS has little effect on ID. (iv) Breakdown region – When VDS is large enough, it causes the JFET’s resistive channel to break down, and ID becomes excessively large. The current in n-JFET due to a small voltage VDS is given by the following equation: I DSS = ( 2a )

W qN d m nVDS L

(7.29)

where 2a = channel thickness, W = width, L = length, q = charge of an electron = 1.6 × 10−19 C, μn = electron mobility, and Nd = n-type doping concentration. In the saturation region,  V I D = I DSS 1 −  GS   VP

   

2

(7.30)

334

Electronic Devices and Circuits

In the linear region called the triode region

ID =

2 I DSS  V  V −VP − DS VDS 2  GS 2  VP 

In the triode region VDS is small. Hence I D =

(7.31)

2 I DSS (VGS − VP )VDS VP2

The following empirical relation is a good valid approximation to find out the resistance offered by the JFET as a function of the controlling voltage VGS. rd =

rdo

(7.32)

 VGS  1 − V  P

where rdo is the resistance when VGS = 0 and rd is the resistance for a given VGS. As an example, let a JFET have rdo = 20 kΩ . Then, rd at VGS = −4 V, if VP = −6 V is rd =

7.11

20 = 60 kΩ  4 1 −  6

FET AMPLIFIERS

In the earlier sections, we have seen the methods of biasing an FET. When we say we have provided bias to the FET, it means that we had established the necessary dc conditions in the circuit, say, IDQ and VGS, in a CS configuration (coordinates of the Q-point). Now the transistor circuit is required to be used as an amplifier, that is, a circuit for which the output is larger than the input. We have three basic amplifier configurations: (i) common source (CS) amplifier, (ii) common drain (CD) amplifier, and (iii) common gate (CG) amplifier.

7.11.1 Common Source Amplifier

VDD

Consider the CS amplifier with voltage divider bias RD as shown in Figure 7.44 and its dc circuit shown R in Figure 7.45. Using the dc circuit, we select IDQ 1 and VGS. Once the operating point is selected, the Cc ac signal (sinusoidal) is applied at the input that is + required to be amplified. To find out the ac signal at Cc S the output and to calculate the other performance Rs Vo quantities, the ac circuit is drawn. R2 + The ac circuit of Figure 7.44 is drawn as shown in RS1 CS Vs Figure 7.46. Now the source S is common between − the input and the output. Hence, the amplifier is called CS amplifier. Figure 7.44 CS amplifier with voltage divider bias

FET Characteristics, Biasing, and FET Amplifiers

335

VDD RD

IDQ

R1 +

+ VDQ + VGSQ R2

RD

S

+

Rs R2

RS

Vo

R1

+

VS

Vs

−

−

Figure 7.45 DC circuit

Figure 7.46 AC circuit of Figure 7.44

The FET shown in Figure 7.47 is to be replaced by its equivalent circuit. There are two ways by which we can do this: (i) a voltage source equivalent circuit and (ii) a current source equivalent circuit. The parameters of the FET, namely, µ, rd, and gm are already defined. Using these parameters, the voltage source and the current source equivalent circuits are represented as shown in Figure 7.48.

R = R1//R2

+ RD

+ Vgs

Rs R

Vo −

+ Vs

−

Figure 7.47 Simplified circuit of Figure 7.46 rd D G +

D

−

G +

µVgs Vgs −

gmVgs

rd

Vgs −

+ S

(a) Voltage source equivalent circuit

S (b) Current source equivalent circuit

Figure 7.48 Equivalent circuit of the FET

In the ac circuit of Figure 7.47, the FET is now replaced by any of these equivalent circuits to calculate the gain. Using the current source equivalent circuit in Figure 7.48(b), the resultant circuit is as shown in Figure 7.49. Let RD = RL. From Figure 7.24, D

rR Vo = − gmVgs × d L rd + RL Vo rR = − gm × d L Vgs rd + RL

gmVgs

+

+

∴A =

G

Rs Vs

R

+ rd

RL Vo

Vgs −

− S

Figure 7.49 AC circuit of the CS amplifier

336

Electronic Devices and Circuits

Dividing by rd A = − gm ×

A=

If

− mRL RL = R rd + RL 1+ L rd

(7.33)

−m . As RL → ∞, A → m r 1+ d RL

D Io + gmVgs

rd

RL RL Normally, yos is listed in the data sheet. yos is the output admittance of CS configuration. The reciprocal of it is rd. If, for example, yos =10 µmhos, then rd =

1 = 100 kΩ 10 × 10 −6

Example 7.11 For the CS amplifier with voltage divider bias shown in Figure 7.52, VDD = 20 V, R1 = 2 MΩ, R2 = 0.4 MΩ, RD = 2 kΩ, Rs =1 kΩ, IDSS = 10 mA, and VP = −6 V. The coordinates of Q are IDQ = 5.1 mA and VGSQ = −1.6 V (Example 7.6). yos = 20 µmhos. Determine: (i) gmo , (ii) gm , (iii) rd , (iv) Ri , (v) Ro′ , and (vi) A. Solution: (i) gmo =

2 I DSS 2 × 10 = = 3.33 mmhos VP 6

FET Characteristics, Biasing, and FET Amplifiers

 VGSQ   −1.6  (ii) gm = gmo 1 −  = 3.33 1 −  = 2.44 mmhos VP  −6   

VDD RL

(iii) rd =

1 1 = = 50 kΩ yos 20 × 10 −6

(iv) R =

R1R2 2 × 0.4 = = 333 kΩ R1 + R2 2 + 0.4

337

R1

2

2

Cc +

Cc S 100

Ri = R = 333 kΩ (v) Ro′ =

Rs

R2

Vo

0.4

+

rd RL 50 × 2 = = 1.92 kΩ rd + RL 50 + 2

1

RS1

Vs

CS −

(vi) A = −gm × RL = −2.44 × 2 = −4.88

Figure 7.52 CS amplifier with voltage divider bias

7.11.2 CS Amplifier with Un-bypassed R S In the circuit of Figure 7.44, if CS is removed, then the amplifier has an un-bypassed Rs (Figure 7.53). Then the ac circuit is as shown in Figure 7.54. VDD RL R1 R = R1//R2

Cc +

Cc

+

RL

+ Vgs

Cc R2

Vi

+

+ Vi

Vo RS

−

−

Vo Rs

−

−

Figure 7.53 CS amplifier with un-bypassed source resistance

R

−

Figure 7.54 AC circuit of Figure 7.53

The FET is now replaced by its equivalent circuit, resulting in the circuit in Figure 7.55. From Figure 7.55, writing the KVL equation of the outer loop, I d RL + ( I d − gmVgs ) rd + I d Rs = 0

(7.37)

Also Vgs = Vi − I d Rs Substituting Eqn. (7.38) in Eqn. (7.37), I d ( RL + Rs + rd ) − gm rd (Vi − I d Rs ) = 0

(7.38)

338

Electronic Devices and Circuits

I d RL + rd + Rs ( m + 1) = mVi ∴ Id =

mVi RL + rd + Rs ( m + 1)

Vo = −I d RL =

A=

(7.39)

− mVi RL RL + rd + Rs ( m + 1)

Vo − mRL = Vi RL + rd + Rs ( m + 1)

(7.40)

D

Ig

+

G +

R

rd

gmVgs Vgs

Vi

ld

Vo

S

− ld

RL Rs −

−

R¢i

Ro

Ri

R¢o

Figure 7.55 Equivalent circuit of Figure 7.54

If gm = 2.5 mmhos, rd = 50 kΩ, RL = 2 kΩ, and Rs = 1 kΩ, then m = 2.5 × 50 = 125; therefore, A with un-bypassed Rs is A=

Vo − mRL −125 × 2 = = = − 1.4 Vi RL + rd + Rs ( m + 1) 2 + 50 + 1(125 + 1)

If RS is bypassed, that is Rs = 0 from Eqn. (7.40), A=

− mRL −125 × 2 = = −4.81 50 + 2 rd + RL

The gain gets reduced, with RS included. The minus sign indicates phase inversion. To calculate, Ri: Let Ig be the gate current and Rgs the gate to source resistance, which normally is very large for an FET (Figure 7.55). Ri =

Vi Ig

Vi = Vgs + gmVgs Rs = Vgs (1 + gm Rs )

(7.41) (7.42)

FET Characteristics, Biasing, and FET Amplifiers

339

And, Ig =

Vgs

(7.43)

Rgs

Substituting Eqs (7.42) and (7.43) in Eqn. (5.41), Ri =

Vi Vgs (1 + gm Rs ) Rgs = = (1 + gm Rs ) Rgs Ig Vgs

(7.44)

Since, Rgs is large, Ri is large. (7.45)

Ri′ = Ri || R ≈ R To calculate, Ro:

To calculate Ro, in Figure 7.55, let RL → ∞ , set Vi = 0, and take the ratio of Vo to Id (Figure 7.56). Now, replace the current source and its internal resistance by the voltage source and its internal resistance, as shown in Figure 7.57(a). D + rd

gmVgs Vgs

S

−

Vi = 0

ld

+

ld

RL= ∞ Vo

Rs −

Figure 7.56 Circuit to calculate Ro D

D

rd

+

ld

rd

−

ld

+

+

gmVgs rd

gm IdRs rd +

ld

S

−

Vo

ld

Rs

S

Vo Rs

−

−

Ro (a)

Ro (b)

Figure 7.57 Circuit to calculate Ro

340

Electronic Devices and Circuits

From Figure 7.56, with Vi = 0, Vgs = − I d Rs . Putting this condition in Figure 7.57(a), we get the circuit in Figure 7.57(b). From Figure 7.57(b), Vo = I d (rd + gm rd Rs + Rs ) = I d rd + Rs ( m + 1) Vo = rd + Rs ( m + 1) Id

∴ Ro =

(7.46)

Ro′ = Ro || RL

(7.47)

7.11.3 CD Amplifier or Source Follower The CD amplifier or the source follower is shown in Figure 7.58 and its ac circuit is shown in Figure 7.59.

VDD R1 R = R1//R2

CC

+

S R ′S

R S′

+

R2

+

Rs Vs

+

Vo

− Vgs

+

R Rs

Vo

Vs

−

Figure 7.58 CD amplifier or source follower

−

Figure 7.59 AC circuit of Figure 7.58

D G R′s +

+ R

rd

gmVgs Vgs

S

−

Vs Vi

ld

X

+

Rs

Vo

X

−

Figure 7.60 Equivalent circuit of Figure 7.59

When the FET is replaced by its current source equivalent circuit, the circuit in Figure 7.59 is drawn as in Figure 7.60. Folding the circuit along X-X results in the circuit of Figure 7.61.

FET Characteristics, Biasing, and FET Amplifiers

From Figure 7.61, Vo = gmVgs

G +

(rd + Rs )Vo rd Rs or Vgs = rd + Rs gm rd Rs

(7.48)

+

S Vgs − gmVgs

Vi

341

+ V Rs o −

rd

Also,

D

(7.49)

Vi = Vgs + Vo

Figure 7.61 Resultant circuit of Figure 7.50

Substituting Eqn. (7.48) in Eqn. (7.49), Vi =

(rd + Rs )Vo + V gm rd Rs

A=

 (rd + Rs )   ( gm rd Rs + rd + Rs )  = Vo 1 + = Vo    gm rd Rs  gm rd Rs   

o

mRs Vo gm rd Rs = = Vi ( gm rd Rs + rd + Rs ) rd + ( m + 1) Rs

(7.50)

Dividing by rd, g m Rs

A=

1 + g m Rs +

Rs rd

≈

g m Rs ≈1 1 + g m Rs

(7.51)

Ri = R. The input resistance of a source follower can be made large. However, the high-frequency response of an FET tends to be poor.

Output Resistance Output resistance is calculated with load Rs included, by taking the ratio of Vo to Io with Vi = 0 (Figure 7.62). From Eqn. (7.49), when Vi = 0, Vgs = −Vo. Then, gmVgs = −gmVo. The equivalent circuit to calculate Ro is as shown in Figure 7.62. Note that the direction of current is now downward. G +

Io

S Vgs −

Vi = 0

gmVo

rd

Rs

+ Vo −

Io

S IL

≡

gmVo

+ V rd Rs o −

D Ro¢

Figure 7.62 Circuit to calculate the output resistance

Writing the KCL equation at node S, I o = gmVo + I L or I L = I o − gmVo

(7.52)

342

Electronic Devices and Circuits

and

Vo = I L

rd Rs rd + Rs

(7.53)

Substituting Eqn. (7.52) in Eqn. (7.53), Vo = ( I o − gmVo )

rd Rs rd + Rs

 rR  rR Vo 1+ gm d s  = I o d s rd + Rs  rd + Rs 

Ro′ =

rd Rs rd + Rs

Rs Vo rd Rs rd Rs = = = = Io  rd Rs  rd + Rs + gm rd Rs rd + ( m + 1) Rs 1 + g R + Rs m s 1 + gm r + R  rd d s

(7.54)

If rd >> Rs, Eqn. (7.54) reduces to Ro′ =

Rs 1 + gm Rs

(7.55)

1 gm

(7.56)

If gm Rs >> 1, Eqn. (7.55) reduces to, Ro′ =

Example 7.12 For the source follower in Figure 7.58, rd = 50 kΩ, gm = 0.0025 mhos, and Rs = 4 kΩ. Find A and Ro′ . Solution: From Eqn. (7.51), A=

gm Rs 1 + gm Rs +

Rs rd

0.0025 × 4000

=

1 + 0.0025 × 4000 +

4 50

=

10 = 0.90 11.08

From Eqn. (7.54), Ro′ =

Rs R 1 + gm Rs + s rd

=

4000 = 361.01 Ω 11.08

FET Characteristics, Biasing, and FET Amplifiers

343

7.11.4 CG Amplifier The CG amplifier is shown in Figure 7.63, and its ac circuit is shown in Figure 7.64. Cc

S

Cc

D

S +

+

D +

+ G

G Rs

Vi

RL

Vo VDD

−

−

RL

Rs

Vi

Vo

−

−

Figure 7.63 CG amplifier

Figure 7.64 AC circuit of Figure 7.63

If the FET is now replaced by its equivalent circuit, the circuit in Figure 7.64 is drawn as shown in Figure 7.65. (i) Calculation of Ri and R′i: To find Ri, the circuit in Figure 7.65 is redrawn as in Figure 7.66. From Figures 7.65 and 7.66, we

Ir

−

S +

D +

− Rs

Vi

Vgs +

−

V −Vgs can calculate Ri and R′i as Ri = i = since I I Vi = −Vgs and Ri′ = Ri / / Rs

Ri

R¢i

RL

gmVgs

I S

+ gmVgs

Ir + Vr

rd

Vi Vgs

D +

RL

Vo I +

− G Ri

Figure 7.66 Circuit to find Ri

From Figure 7.66, writing the KVL equation, Vi = Vr + Vo = Vr + IRL

Vo

I − G

Ro

Figure 7.65 Equivalent circuit of Figure 7.64

−

−

+ Vr rd

R¢o

344

Electronic Devices and Circuits

Or

Vr = Vi − IRL

(7.57)

I + gmVgs = I r

(7.58)

Writing the KCL equation at node S,

From Figure 7.66 and Eqn. (7.57), Ir =

Vr Vi − IRL = rd rd

(7.59)

From Eqs (7.58) and (7.59), I = I r − gmVgs =

Vi − IRL V − IRL − gmVgs = i + gmVi rd rd

since Vi = −Vgs .

 R  1  ∴ I 1 + L  = Vi  + gm  rd    rd 

Ri =

 RL  1 + r 

r + RL Vi d = = d I 1  1 + rd gm  r + gm 

(7.60)

(7.61)

d

If

RL 1 Ri 2. To calculate the exact value of the gain AV , using Eqn. (8.10), we need to calculate AI1 and Ri2 AI 2 =

Io −hfc = ≈ (1 + hfe ) if hoc RE RD

8.6.2 Low-Frequency Range In the low-frequency range CS is an open circuit, but CC is considered as shown in Figure 8.36. RD

Cc +

+

gmVgsRD Vgs −

R

+

Vo −

Figure 8.36 Low-frequency equivalent circuit

From Figure 8.36, R

Vo = − gmVgs RD

R + RD +

1 j wC c

 RRD    − gm     R + RD  V Am RRD = Al = o = − gm  =  1 1 w Vgs  R + RD +  1+ 1− j 1  jw Cc  jw Cc (R + RD ) w

The final result is Al =

Am w 1− j 1 w

(8.33)

388

Electronic Devices and Circuits

where the lower half-power frequency is given by w1 =

1 Cc (R + RD )

(8.34)

8.6.3 High-Frequency Range In the high-frequency range Cc is a short circuit, but Cs is considered in Figure 8.37. RD +

Cs + Vgs −

gmVgsRD

R

+

Vo −

Figure 8.37 High-frequency equivalent circuit

From Figure 8.37,

Vo = − gmVgs RD

 1   R × jwC  s  1  RD +  R × j w Cs  

 1   R + jwC  s  1   R + jwC Cs 

   RRD  R − gm     R + RD  j wC s V Am − gm RD R = Ah = o = − gm RD  = = w jwRRDCs  R Vgs  1   R + RD + jwRRDCs 1+ j 1+ + RD  R +    w R + R j wC s   2  D  j wC s The final result is Am

Ah =

1+ j

(8.35)

w w2

where the upper half-power frequency is given by w2 =

8.7

R + RD RRDCs

(8.36)

EFFECT OF CE ON THE LOW-FREQUENCY RESPONSE OF CE AMPLIFIER ASSUMING CC TO BE SUFFICIENTLY LARGE

Consider the CE amplifier shown in Figure 8.38. If CE in the circuit does not behave as a short circuit, the parallel combination of RE and CE offers a finite impedance, Ze . The equivalent circuit in the low-frequency range, on the assumption that Cc is sufficiently large, is as given in Figure 8.39.

Multistage Amplifiers

389

VCC RC

+

Cc

+ Vi

Vo RE

CE

−

−

Figure 8.38 CE amplifier Ib

Ib

+

+ hie

RC

Vi

(1+ hfe)Ib

RE

hie

+

hfeIb

+

hfeIb

Vo

RC

Vi (1 + hfe)Ib

−

Vo

−

Ze

CE

−

−

Ri

Ri

Figure 8.39 Circuit to show the effect of CE on the low-frequency response

We have R  Al = −hfe  C   Ri 

(8.37)

Ri = hie + (1 + hfe ) Ze

(8.38)

 1  RE   RE  j wC E  = Ze =  1  1 + jwCE RE RE +    j wC E 

(8.39)

Substituting Eqn. (8.39) in Eqn. (8.38),   RE Ri = hie + (1 + hfe )    1 + jwCE RE 

(8.40)

390

Electronic Devices and Circuits

From Eqn. (8.37) and Eqn. (8.40), Al = −hfe

RC = Ri

−hfe RC   RE hie + (1 + hfe )    1 + jwCE RE 

(8.41)

In the mid-band range w is large. Hence, the second term in the denominator is small. Therefore, from Eqn. (8.41), Am =

−hfe RC hie

(8.42)

Therefore, Al = Am

−hfe RC  RE hie + (1 + hfe )   1 + jwCE RE

 hie  hie  =   −hfe RC    RE hie + (1 + hfe )      1 + jwCE RE 

hie (1 + jwCE RE ) Al = = Am hie (1 + jwCE RE ) + (1 + hfe ) RE

(1 + jwCE RE ) (1 + hfe ) RE (1 + jwCE RE ) + hie

 (1 + hfe ) RE Taking 1 + hie 

  as the common factor,  Al 1 = Am  (1 + hfe ) RE 1 + hie 

(1 + jwCE RE )      1 +  jwCE RE  (1 + hfe ) RE 1+ hie 

  1+  Al 1 =  Am  (1 + hfe ) RE   1 +  1+ hie  

 j   j  

    f    fp   f fo

     

(8.43)

where wo =

1 CE RE

(8.44)

Multistage Amplifiers

391

and 1+ wp =

since 1 > fo . Considering Eqn. (8.43) at f = fp ,  fp  j   fo  hie × = + hfe ) RE 1 + j 1 fp  (1+  fp 

 fp  1+ j    fo 

Al 1 = × Am  (1 + hfe ) RE  1 +  1+ hie  

since 1 > fo

From Eqs (8.44) and (8.45),

(1 + hfe ) RE fp fo

=

CE RE (1 + hfe ) RE hie = 1 CE RE hie

(8.47)

Substituting Eqn. (8.47) in Eqn. (8.46),

(1 + hfe ) RE 1 1 hie Al = × × = Am (1 + hfe ) RE hie 2 2 Thus, w p is the half-power frequency:

w1 = w p =

(1 + hfe ) RE (1 + hfe ) hieCE RE

=

hieCE

(8.48)

Example 8.5 For the circuit in Figure 8.38, calculate the size of CE to provide f1 = 100 Hz, when RE = 1 kΩ, hie = 1.1 kΩ, and hfe = 70.

392

Electronic Devices and Circuits

Solution: From Eqn. (8.48), fp =

CE =

(1 + hfe ) 2phie fp

=

(1 + hfe ) 2phieCE

71 = 102.75 µF ≈ 100 µF 2p × 1100 × 100

The above expression is valid only when fp >> fo. From Eqn. (8.44), fo =

1 1 = = 1.59 Hz 2pCE RE 2p × 100 × 10 −6 × 1× 103

Hence, the condition is satisfied.

8.8

BANDWIDTH OF n-IDENTICAL MULTISTAGE AMPLIFIERS

Consider n noninteracting (means there is no loading by the succeeding stage on the previous stage. This in turn may mean that the stages are isolated) identical cascaded stages with f1 and f2 as the half-power frequencies. Then,

Ah for the n stages is Am

   Ah 1 = 2 Am   f  + 1      f2 

n

n2        1    = 2   1 +  f      f2     

(8.49)

Let f2* be the upper half-power frequency of the cascaded stage. Then, at this frequency Ah 1 = . Therefore, Am 2

    1     * 2 1 +  f2     f     2  

n2

  f * 2  1 +  2     f2  

n2

2

=

1 2

= 2

 f*  1n 1 +  2  = (2) f  2 

Multistage Amplifiers

393

2

 f2*  1n   = (2) −1  f2  f2* = f2 f2* = f2

1n

(2)

−1

1n

(2)

−1

(8.50)

Similarly,    Al 1 = 2 Am   f1  1 +      f 

      

n

(8.51)

Proceeding on similar lines, f1* =

f1 1n

(2)

(8.52) −1

The bandwidth is f2* − f1* = f2* Example 8.6 The bandwidth of a single-stage amplifier is 100 kHz. Calculate the bandwidth when (i) n = 2 (ii) n = 3. Solution: From Eqn. (8.50), 1

f2* = f2 2 n − 1 1

(i) when n = 2,

2 n − 1 = 0.643. Hence, f2* = 100 × 0.643 = 64.3 kHz

(ii) when n = 3,

2 n − 1 = 0.510. Hence, f2* = 100 × 0.510 = 51.0 kHz

1

8.9 TRANSFORMER-COUPLED AMPLIFIER A transformer transfers electrical energy from the primary coil to the secondary coil through inductive coupling. A varying current in the primary induces a varying voltage in the secondary due to mutual induction. A CE amplifier with load RL connected through a transformer is shown in Figure 8.40. Normally, for low-frequency applications a transformer is not used mainly because of the fact that the transformer becomes bulky and occupies more space as it is wound on an iron core. However, the transformer may be used for impedance matching in power amplifiers.

394

Electronic Devices and Circuits VCC N:1 R1

+ RL Vo

R′L

−

+

Cc

Vs

−

R2

CE

RE

Figure 8.40 A CE amplifier with load connected through a transformer

We have discussed about these amplifiers in Chapter 11 in detail. In the radio frequency range, the size of the transformer becomes small, and it hence can be used for interstage coupling. We will consider these transformer-coupled amplifiers when we consider tuned amplifiers in Chapter 13. A two-stage transformer coupled amplifier is shown in Figure 8.41 to illustrate the principle of transformer coupling. The transformers in circuit of Figure 8.41 can be ferrite cored transformers, in which the coefficient of coupling can be adjusted by adjusting the position of the ferrite core. The main advantage with this transformer coupling is that it blocks the dc component of the output signal. Inclusion of transformer in the coupling circuit helps in allowing only ac component of the output signal to the input of the next stage. Another major advantage is that a tuned circuit can be provided in the secondary winding (in some cases, both in the primary and secondary windings), which allows signals of only a narrow band of frequencies. Such amplifiers are called tuned amplifiers, which we will be discussing in Chapter 13. VCC N:1

N:1

R1

+ RL Vo

R1

− T2

T1 Q2

Q1 Cc

+ Vs

−

R2

RE

CE

R2

RE

CE

−

Figure 8.41 A two-stage transformer-coupled amplifier

Multistage Amplifiers

8.10

395

DIRECT-COUPLED AMPLIFIERS

A direct-coupled amplifier, popularly known as a dc amplifier, is an amplifier in which the output of one stage is connected to the input of the next stage directly without using any reactive elements such as capacitors, inductors, or transformers. It is seen in the analysis of an RC-coupled amplifier that the low-frequency response tends to become poor mainly because of the coupling capacitor Cc . As Cc is totally eliminated, the frequency response of this amplifier tends to be flat right form 0 Hz (dc) as shown in Figure 8.42. This is the major advantage of this amplifier. A single-supply direct-coupled amplifier is shown in Figure 8.43. When the output of one stage is directly coupled to the input of the next stage, not only the ac signal but also the dc is coupled to the input of the subsequent stage. As such, care should be taken to provide proper biasing in the circuit. A 0.707A

0

f

f2

Figure 8.42 Frequency response of a dc amplifier

VCC

RC1 R1

RC2

+VC Q2

Q1

+ Vs

R2

RE1

RE2

−

Figure 8.43 The direct coupled amplifier

The dc conditions for a specific amplifier are shown in Figure 8.44. R1 and R2 are adjusted to get a voltage of 2 V at the base of Q1. If the transistor is in the active region, then VBE1 = 0.6 V . Therefore, the voltage at the first emitter is 1.4 V. As RE1 is 1.4 kΩ, I E1 = 1 mA . Hence, I C1 ≈ 1 mA .  As a result, the voltage at the first collector is 3 V, since RC1 = 12 kΩ . Since Q2 is also in the

396

Electronic Devices and Circuits

active region, VBE 2 = 0.6 V . Hence, the voltage at the second emitter is 2.4 V. Since RE 2 = 2.4 kΩ, I E 2 ≈ I C2 = 1 mA. As RC 2 = 9 kΩ, Vo , the voltage at the second collector is 6 V. Under quiescent conditions, output voltage Vo = 6 V . When a signal is applied at the input, this dc voltage at the output changes as per the variation of the signal at the input, resulting in an ac voltage referenced to 6 V. If now the temperature increases resulting in the increase in hFE , the dc voltage Vo at the output is smaller than 6 V. But any change in the output can only be due to an input signal present, but cannot occur due to device parameter variation. Thus, a change in the output voltage due to a change in hFE may be construed as a change occurring due to an input signal; but in reality, this change is due to the variation in hFE . This problem is called the problem of drift in dc amplifiers. If the problem of drift is taken care by providing proper temperature compensation,

VCC = 15 V

IC1

RC1

RC2

12

9

IC2 1 mA

1 mA 3V 2V Q1

2V 0

6V + 0.6 V

+ 0.6 V − RE1 1.4

VE1

6V

Q2 V0 −

VE2

0

2.4 V

1.4 V RE2 IE1 1 mA

2.4 1 mA IE2

G

Figure 8.44 The dc conditions

direct-coupled amplifiers are the best amplifiers. In the single-supply direct-coupled amplifier (Figure 8.44), the output is referenced to a dc voltage of 6 V. However, in many applications, it may be required that the output may have to be referenced to 0 level. Then, it becomes necessary to use a two-supply (a positive source and a negative source) dc amplifier as shown in Figure 8.45. In the single-supply dc amplifier, the input is not referenced to 0 V but is referenced to 2 V. However, if the input is to be referenced to 0 V, the negative 10 V source gives a voltage of −0.6 V at the emitter of Q1 which is the voltage needed to forward bias the emitter diode. The emitter and collector resistances of Q1 are adjusted so as to have a collector current of 1 mA. Consequently, the voltage at the first collector is 3 V. As discussed earlier, the emitter and collector resistances of Q2 are so adjusted that its collector current is again 1 mA and the voltage at the second collector is 6 V. Similarly the dc voltage at the collector of Q3 is 10 V. By providing a potential divider network comprising 100 kΩ and 100 kΩ resistors, it is possible to adjust the dc voltage at the output to 0 V. That is, in a twin-supply direct-coupled amplifier if a dc voltage is present at the output, it can be translated to zero level. This is called level translation.

Multistage Amplifiers

397

VCC = 15 V

12

0.6 V

Q3 10 V 100 5.4 V

−

−

− 0.6 V

+ 0.6 V

Q2 6 V VE2

+ Q1

1 mA

1 mA

3V

1 mA 0

5

9

2.4 V

+ 0 Vs

5.4

12

Vo

10

2.4 1 mA

1 mA

1 mA

100 − 10 V

Figure 8.45 A twin-supply DC amplifier with input and the output referenced to zero

Additional Solved Examples Example 8.7 For the amplifier circuit shown in Figure 8.46, calculate the performance quantities, 1 using the exact and approximate analysis. hie = 1.1 kΩ, hre = 2.5 × 10−4, hfe = 100, and = 40 kΩ. hoe VCC

5 220

RC2 1

RC1 R3

R1

1

150

Rs

+

Cc

Cc Cc

+

Vo Vs

33

R2

RE

CE

−

R4

RE

CE

10

Figure 8.46 The CE–CE amplifier

Solution: R = R1//R2 =

220 × 33 150 × 10 = 28.7 kΩ and R′ = R3//R4 = = 9.38 kΩ 220 + 33 150 + 10

(i) Second stage; AI 2 =

−hfe −100 = = −97.56 1 + hoe RC 2 1 + 1 40

398

Electronic Devices and Circuits

Ri2 = hie + hre AI 2 RC2 = 1100 + 2.5 × 10 −4 × 1 × 103 ( −97.56 ) =1.076 kΩ

AV2 = AI2

RC2 1 = −97.56 × = −90.67 Ri 2 1.076

(ii) First stage: Load for the first stage RL is RL = RC1 / / R′ / / Ri 2 =

=

AI1 =

Ri 2 RC1R′ Ri 2 RC1 + RC1R′ + Ri 2 R′

1.076 × 5 × 9.38 = 0.81 kΩ 1.076 × 5 + 5 × 9.38 + 1.076 × 9.38 −hfe −100 = = −98.04 1 + hoe RL 1 + 0.81 40

Ri1 = hie + hre AI1RL = 1100 + 2.5 × 10 −4 × 0.81 × 103 × ( −98.04 ) = 1.08 kΩ

AV1 = AI1

RL 0.81 = −98.04 × = −73.53 Ri1 1.08

AV = AV1AV 2 = −73.53 × −90.67 = 6666.96

AV = AV × s

Ri = Ri || R =

Ri Ri + Rs

where

Ri = R//Ri1

28.7 × 1.08 =1.04 kΩ. 28.7 + 1.08

AV = 6666.96 × s

1.04 = 3398.84 1.04 + 1

This gain is very large, and the output and the input are in the same phase as each of these amplifiers produces a phase shift of 180°. Output resistance, Ro: Yo = hoe −

hfe hre hie + Rs1

where

Rs1 = Ro1//RL.

Multistage Amplifiers

399

Ro1 is the output resistance of the first stage, and RL is the load for the first stage. This value is effectively RL since Ro1 is large. Yo = 25 × 10 −6 −

100 × 2.5 × 10 −4 = (25 − 13.09) × 10−6 mhos 1100 + 810

Ro = 83.96 kΩ Approximate analysis: If hoe = hre = 0, the circuit in Figure 8.10 simplifies to that in Figure 8.12. (i) Second stage; AI2 = −hfe − 100 Ri2 = hie = 1.1 kΩ AV2 = AI2

RC2 1 = −100 × = −90.91 Ri 2 1.1

(ii) First stage: Load for the first stage RL is RL = RC1 / / R′ / / Ri2 =

=

Ri 2 RC1R′ Ri 2 RC1 + RC1R′ + Ri 2 R′

1.1× 5 × 9.38 = 0.82 kΩ 1.1× 5 + 5 × 9.38 + 1.1× 9.38

AI1 = −hfe = −100 Ri1 = hie = 1.1 kΩ

AV1 = AI1

RL 0.82 = −100 × = −74.55 Ri1 1.1

AV = AV1AV 2 = −74.55 × −90.91 = 6777.34 To calculate AV consider the circuit in Figure 8.11. s

AV = AV × s

Ri =

Ri Ri + Rs

28.7 × 1.1 = 1.06 kΩ 28.7 + 1.1

where

Ri = R//Ri1

400

Electronic Devices and Circuits

AVs = 6777.34 ×

1.06 = 3487.37 1.06 + 1

Opening the load RL = RC2 and looking into the output terminals, Ro = ∞ and R′o = RC2 = 1 kΩ. 1 = 40 kΩ , hoe hre = 2.5 × 10−4, RC = 5 kΩ, Rs = 1000 Ω, hrc = 1, and RE = 5 kΩ, calculate AV, AVs , Ri, and Ro. Example 8.8 For the CE–CC amplifier in Figure 8.47, with hie = 1.1 kΩ, hfe = 100,

VCC

RC

5

Rs 1 Q2

Q1

+

Ib + Vs

RE

Vo

5

Figure 8.47 CE–CC amplifier

Solution: (i) Calculations pertaining to the second stage: AI2 =

(1 + hfe ) 101 I e2 −hfc = = = = 89.78 I b 2 1 + hoc RE 1 + hoe RE 1 + 5 40

Ri 2 = hic + hrc AI 2 RE = hie + AI 2 RE = 1.1 + (89.78)(5) = 450 kΩ

AV2 = AI 2

RE 5 = 89.78 × = 0.998 Ri 2 450

(ii) Calculations pertaining to the first stage of the load for the first stage is RL = RC / / Ri 2 = 5 / /450 =

5 × 450 = 4.945 kΩ 5 + 450

Multistage Amplifiers

AI1 =

401

−I c1 −hfe −100 = = = −88.97 I b1 1 + hoe RL 1 + 4.945 40

Ri1 = hie + hre AI1RL = 1100 + 2.5 × 10 −4 (−88.97)(4.945 × 103) = 0.99 kΩ

AV1 = AI1

RL 4.945 = −88.97 × = −444.4 Ri1 0.99

AV = AV1AV 2 = −444.4 × 0.998 = −443.51 (iii) Overall voltage gain and current gain: AVs =

Vo Ri1 0.99 = AV × = −443.51 × = −220.64 Vs Rs + Ri1 0.99 + 1

Refer Figure 8.3, then AI =

To calculate

I e 2 I e 2 I b 2 I c1 I = = AI 2 b 2 AI1 I b1 I b 2 I c1 I b1 I c1

I b2 , refer Figure 8.5 I c1 I b 2 = −I c1

AI = AI 2

RC RC + Ri 2

I b2 RC −5 =− = = −0.011 I c1 RC + Ri 2 5 + 450

I b2 AI1 = 89.78 × ( −0.011) ( −88.97 ) = 87.86 I c1

(iv) To calculate the output resistance: The expression for Yo is Yo = hoc −

hfc hrc hic + Rs1

To calculate Yo, we first calculate Ro1, the output resistance of the first stage and then calculate Rs1(=Ro1//RC) Yo1 = hoe −

hfe hre hie + Rs

402

Electronic Devices and Circuits

Yo1 = 25 × 10 −6 −

Ro1 =

1 1 = 76.34 kΩ = Yo1 13.1× 10 −6

Rs1 = Ro1//RC =

Yo = hoc −

100 × 2.5 × 10 −4 = (25 − 11.90) 10−6 = 13.1 × 10−6 mhos 1100 + 1000

76.34 × 5 = 4.69 kΩ 76.34 + 5

hfc hrc 101 × 1 = 0.0174 mhos = 25 × 10 −6 + hic + Rs1 1100 + 4690

Ro =

1 1 = = 57.47 Ω Yo 0.0174

Approximate analysis: If hre = hoe = 0, then the circuit in Figure 8.3 is reduced to that in Figure 8.6. (i) Calculations pertaining to the second stage:

AI2 =

I e2 = (1 + hfe ) = 1 + 100 = 101 I b2

Ri2 = hic + hrc AI2 RE = hie + AI2 RE = 1.1 + (101) (5) = 506.1 kΩ

AV 2 = AI 2

RE 5 = 0.998 = 101× Ri 2 506.1

(ii) Calculations pertaining to the first stage: From Figure 8.6, the load for the first stage is as shown in Figure 8.7.

RL = RC / / Ri 2 = 5 / /506.1 =

AI1 =

−I C1 = −hfe = −100 I b1

Ri1 = hie = 1.1 kΩ

5 × 506.1 = 4.95 kΩ 5 + 506.1

Multistage Amplifiers

AV1 = AI1

403

RL 4.95 = −100 × = −450 Ri1 1.1

AV = AV1AV 2 = −450 × 0.998 = −449.1 (iii) Overall voltage gain and current gain: AV = s

AI =

To calculate

Vo Ri1 1.1 = AV × = −449.1 × = −235.24 Vs Rs + Ri1 1.1 + 1 I e 2 I e 2 I b 2 I c1 I = = AI 2 b 2 AI1 I b1 I b 2 I c1 I b1 I c1

I b2 , consider Figure 8.5. I c1 I b 2 = −I c1

AI = AI 2

RC RC + Ri 2

I b2 RC −5 =− = = −0.0098 I c1 RC + Ri 2 5 + 506.1

I b2 AI1 = 101× ( −0.0098 ) ( −100 ) = 98.98 I c1

(iv) To calculate the output resistance: The expression for Yo is Yo = hoc −

hfc hrc hic + Rs1

To calculate Yo, we first calculate Ro1, the output resistance of the first stage and then calculate Rs1(= Ro1//RC). Yo1 = hoe −

hfe hre hie + Rs

Yo1 = 0 Ro1 =

1 = ∞. Yo1

404

Electronic Devices and Circuits

Rs1 = R′o1 = Ro1//RC = 5 kΩ. Yo =

Ro =

(1 + hfe ) hie + Rs1

=

101 = 0.0166 mhos 1100 + 5000

1 1 = = 60.24 Ω. Yo 0.0166

Example 8.9 For the amplifier shown in Figure 8.48, calculate Ri1, AV1, Ro1, AI2, Ri2, AV2, Ro2, Ri, AV, and AV . The transistors have hfe = 100, hrc = 1, hie = 1 kΩ, hoe = hre = 0. R1 = R2 = 100 kΩ, RE = 5 kΩ, R3 = 150 kΩ, RC = 5 kΩ, Rs = 1 kΩ, and R4 = 30 kΩ. s

VCC

RC R3

R1 1

+

Cc Rs

Cc

+ Vs

R2

Vo

Cc R4

RE

RE

CE

−

Figure 8.48 The CC–CE amplifier

Solution: The simplified ac circuit of Figure 8.48 is shown in Figure 8.49.

1

+

Rs RC V o

+ Vs

R

RL

−

Figure 8.49 Simplified circuit of Figure 8.48

R = R1 / / R2 =

R2 R2 100 × 100 = = 50 kΩ R1 + R2 100 + 100

RL = RE / / R3 / / R4 =

5 × 150 × 30 = 4.17 kΩ 5 × 150 + 150 × 30 + 30 × 5

Multistage Amplifiers

(i) Second-stage CE amplifier: AI2 = −hfe = −100, since hoe = 0 Ri 2 = hie = 1 kΩ , since hre = 0

AV 2 = AI 2 ×

RC 5 = −100 × = −500 Ri 2 1

(ii) First-stage CC amplifier: AI1 = −hfc = (1 + hfe ) = 101

R i1 = hie + AI1RL = 1× 101× 4.17 = 422.17 kΩ

AV1 = AI1 ×

RL 4.17 = 101× = 0.998 Ri1 422.17

Rs1 = Rs / / R =

Ro1 =

RRs 1 × 50 = = 0.98 kΩ R + Rs 1 + 50

Rs1 + hie 0.98 + 1 = = 0.02 kΩ 1 + hfe 1 + 100

Ro2 = ∞

Ri = Ri1 / / R =

RRi1 50 × 422.17 = = 44.71 kΩ R + Ri1 50 + 422.17

AV = AV1AV 2 = 0.998 × −500 = −499

AV = AV s

Ri 44.71 = −499 × = −488.08 Ri + Rs 44.71 + 1

405

406

Electronic Devices and Circuits

Example 8.10 For the circuit shown in Figure 8.50, calculate Ri, AV, AV , and Ro, given that hfe = 100, hie = 1 kΩ, and hoe = hre = 0. s

VCC

10

500

Rc1

Re2

Rs 1 Q2

Q1

+ + Vs

5

Re1

Vo

Rc2

500

Figure 8.50 A two-stage amplifier

Solution: Q2 is a PNP transistor, connected upside down. If Q2 is replaced by an NPN trans istor, the ac circuit is as shown in Figure 8.51. Each stage is a CE amplifier with un-bypassed emitter resistance. Rs 1 Q1

Vi

+ Vs

Re1 500

+

Q2

+

10

Rc1

500

Re2

5 Rc2

Vo

− Ri2

Ri1

Figure 8.51 The ac circuit of Figure 8.50

(i) Second stage: AI 2 = −hfe = −100 Ri 2 = hie + (1 + hfe ) Re 2 = 1 + (1 + 100 )(0.5) = 51.5 kΩ

AV 2 = AI 2

Rc 2 5 = −100 × = −9.71 Ri 2 51.5

Multistage Amplifiers

407

(ii) First stage: Rc1Ri 2 10 × 51.5 = 8.37 kΩ = Rc1 + Ri 2 10 + 51.5

RL = Rc1 / / Ri 2 =

AI1 = −hfe = −100 Ri1 = hie + (1 + hfe ) Re1 = 1 + (1 + 100 )(0.5) = 51.5 kΩ

AV1 = AI1

RL 8.37 = −100 × = −16.25 Ri1 51.5

AV = AV1AV 2 = ( −16.25) ( −9.71) = 157.79

AV = AV s

Ri1 51.5 = 157.79 = 154.78 Ri1 + Rs 51.5 + 1

Ro ′ = Rc 2 = 5 kΩ

Example 8.11 For the amplifier circuit shown in Figure 8.52, calculate Ri, AV, AV , and Ro ′ , given that hfe = 100, hie = 1 kΩ, and hoe = hre = 0. s

VCC 5

Re1

5

Rc2 Rs 1 Q2

Q1

+ Vs

Re2 500

Figure 8.52 A two-stage amplifier

+

Vo

408

Electronic Devices and Circuits

Solution: Q1 is a PNP transistor, connected upside down. If Q1 is replaced by an NPN transistor, the first stage can be seen as a CC amplifier. The second stage is a CE amplifier with un-bypassed emitter resistance. The ac circuit of the two-stage amplifier is shown in Figure 8.53. Rs 1 Q1 Q2

+ + Vs

+

Vi

5 Rc2

Re1 500

5

Vo

Re2

− Ri1

Ri2

Figure 8.53 AC circuit of Figure 8.52

(i) Second stage: AI 2 = −hfe = −100 Ri 2 = hie + (1 + hfe ) Re2 = 1 + (1 + 100 )(0.5) = 51.5 kΩ AV2 = AI 2

Rc2 5 = −100 × = −9.71 Ri2 51.5

(ii) First stage: RL = Re1 / / Ri 2 =

Re1Ri2 5 × 51.5 = 4.56 kΩ = Re1 + Ri2 5 + 51.5

AI1 = −hfc = 1 + hfe = 101 Ri1 = hie + (1 + hfe ) Re1 = 1 + (1 + 100 )( 5 ) = 506 kΩ

AV1 = AI1

RL 4.56 = 101 × = 0.91 Ri1 506

AV = AV1AV 2 = ( −9.71)(0.91) = −8.84

AV = AV s

Ri1 506 = −8.84 × = −8.82 Ri1 + RS 506 + 1

Ro ′ = Rc 2 = 5 kΩ

Multistage Amplifiers

409

Example 8.12 For the amplifier circuit shown in Figure 8.54, calculate Ri, AV, AV and Ro ′ , given that hfe = 100, hie = 1 kΩ, and hoe = hre = 0. s

VCC 5 10 200

Rc1

Rc2

R′

Rs 1

+

Q2

Q1

+ Vs

Re2

Re1

Vo

500

500

Figure 8.54 Two-stage amplifier

Solution: In the first-stage compound feedback is used. Using Miller’s theorem, R′ can be replaced by R1 and R2 appearing in shunt with the input and the output terminals of Q1. The ac circuit is as shown in Figure 8.55 Rs 1 Q2

Q1 +

+ 5

Vs R1

Ri

Re1 500

Ri1

Rc1 10

Re2

R2

Rc2

Vo

500

Ri2

Figure 8.55 AC circuit of Figure 8.54

R1 =

R′ and R2 ≈ R′ = 200 kΩ 1 − AV1

(i) Second stage: AI 2 = −hfe = −100 Ri 2 = hie + (1 + hfe ) Re 2 = 1 + 1(1 + 100 )( 0.5 ) = 51.5 kΩ

410

Electronic Devices and Circuits

Rc 2 5 = −100 × = −9.71 Ri 2 51.5

AV 2 = AI 2

(ii) First stage R L = Rc1 || R2 || Ri 2 = 200//10//51.5 = 8.03 kΩ. AI1 = −hfe = −100 Ri1 = hie + (1 + hfe ) Re1 = 1 + (1 + 100 )( 0.5 ) = 51.5 kΩ

AV1 = AI1

RL 8.03 = −100 × = −15.59 Ri1 51.5

AV = AV1AV 2 = ( −9.71) ( −15.59 ) = 151.38 R1 =

200 R′ = = 12.05 kΩ 1 − AV1 1 + 15.59

Ri = R1 / / Ri1 = 12.05 / /51.5 = 9.765 kΩ AVs = AV

Ri 9.765 = 151.38 × = −137.32 Ri + Rs 9.765 + 1

Ro ′ = Rc 2 = 5 kΩ Example 8.13 For the bootstrap emitter follower shown in Figure 8.56, calculate Ri and AV, given that hfe = 1000, hie = 1 kΩ, and hoe = hre = 0. R1 = R2 = R3 = 10 kΩ, RE = 5 kΩ VCC R1 Q

X

+

Darlington transistor

Y +

R3 Vi R2 CB

Vo

RE −

Figure 8.56 The bootstrapped emitter follower

Multistage Amplifiers

411

Solution: The ac circuit is shown in Figure 8.57. R3 appears between the input and the output. Using the Miller’s theorem, the circuit in Figure 8.57 is drawn as in Figure 8.58 Q

X

+

Y +

R3

Vi

R2

R1

Vo

RE −

Figure 8.57 AC circuit of Figure 8.56

X

Q

+

Y + Rx

Vi

RY

RL

Vo −

Ri

R′i

Figure 8.58 Input and output circuits using the Miller’s theorem

RX =

Therefore,

R3 RA and RY = 3 V ≈ ∞ AV − 1 1 − AV

RL = RE / / R1 / / R2 =

5 × 10 × 10 = 2.5 kΩ 5 × 10 + 10 × 10 + 5 × 10

AI = − hfc = 1 + hfe = 1 + 1000 = 1001 Ri ′ = hie + (1 + hfe ) RL = 1 + 1001× 2.5 = 2503.5 kΩ

Alternately,

AV = AI

RL 2.5 = 1001× = 0.9996 Ri ′ 2503.5

AV = 1 −

hie 1 = 1− = 0.9996 Ri ′ 2503.5

RX =

R3 10 = = 25 MΩ 1 − AV 1 − 0.9996

Ri = Ri ′ / / RX =

2503.5 × 25000 = 2.27 MΩ 2503.5 + 25000

(since AV ≈ 1)

412

Electronic Devices and Circuits

Example 8.14 For the amplifier shown in Figure 8.59, calculate AV and Ri, hfc = −101 , hie = 1 kΩ, hoe = 0, and hrc = 1. RE = 5 kΩ VCC Ib1 Q1 +

Ib2 Q2 +

+

+ Vi2 Vo

Io

Vs

− Ri2

Figure 8.59 The Darlington emitter follower (CC–CC amplifier)

Solution: The ac circuit is shown in Figure 8.60.

Q1 Q2

+ Vs

+ + Vo1 = Vi2

Ri2

RE

Vo −

Figure 8.60 The ac circuit of Figure 8.59

(i) Second stage AI 2 = −hfc = 1 + hfe = 1 + 100 = 101 Ri 2 = hie + (1 + hfe ) RE = 1 + 101× 5 = 506 kΩ . AV 2 = AI2

RE 5 = 101 × = 0.998 Ri 2 506

Multistage Amplifiers

413

(ii) First stage: AI1 = −hfc = 1 + hfe = 1 + 100 = 101 Ri1 = hie + (1 + hfe ) Ri 2 = 1 + 101 × 506 = 51.11 MΩ. AV1 = AI1

Ri 2 506 =1 = 101× Ri1 51110

AV = AV1AV 2 = 0.998 × 1 = 0.998

Example 8.15 It is required that the voltage gain of an RC coupled amplifier should not decrease by more than 10 percent of its mid-band gain at 100 Hz. Choose the proper value of Cc. The circuit has RC = 1 kΩ and the transistor has hie = 1 kΩ Solution:

Al = Am

1 f  1+  1   f

2

It is desired that at f = 100 Hz,

2

1

Therefore,

f  1+  1   f  f1 = 0.48 f

AL = 0.9 Am

2

= 0.9

or

f1 = 0.48 × f

For the RC-coupled amplifier, f1 =

Therefore, Cc =

f  1 1+  1  = = 1.23  f 0.81

2

 f1   f  = 0.23

f1 = 0.48 × 100 = 48 Hz.

1 2pCc (RC + hie )

or

1 1 = = 1.66 mF 2pf1 (RC + hie ) 2p × 48 × (1 + 1)103

Cc =

1 2pf1 (RC + hie )

414

Electronic Devices and Circuits

Example 8.16 The lower and the upper half-power frequencies of an RC-coupled amplifier are 50 Hz and 50 kHz, respectively. Calculate the frequenceis act range over which the gain falls by 10 percent of its mid-band gain. Solution: Given f1 = 50 Hz and f2 = 50 kHz Al = Am

We have,

At f,

f  1+  1   f

2

Al = 0.9 Am 2

f  1 = 1.11 1+  1  =  f 0.9

1

∴ 0.9 =

f  1+  1   f

2

2

 f1   f  = 0.23

We have

At f ′,

1

Ah = Am

f1 = 0.48 f

f =

2

f  1 +  1  = 1.23  f

f1 50 = = 104.16 Hz 0.48 0.48

1  f  1+    f2 

2

Ah = 0.9 Am 2

1

∴ 0.9 =

 f ′ 1+    f2  2

 f ′  f  = 0.23 2

2

f′ = 0.48 f2

 f ′ 1 1+   = = 1.11 0.9  f2 

2

 f ′ 1 +   = 1.23  f2 

f ′ = 0.48 f2 = 0.48 × 50 = 24 kHz

The frequencies at which Am falls by 10 percent are 104.16 Hz and 24 kHz

Multistage Amplifiers

415

Example 8.17 For the amplifier circuit shown in Figure 8.61, find the mid-band gain and the value of Cc needed to give a lower half-power frequency of 50 Hz. The transistor has hfe = 100 and hie = 1 kΩ. CE is large. hre = hoe = 0

VCC

5 60

RC1

10 60

R1

RC2

R3 +

Cc

Cc

+

10 Vi

60

R2

CE

RE

R5

60 R4 RE

Vo

CE

Figure 8.61 Two-stage CE–CE amplifier

Solution: The ac circuit of Figure 8.61 is shown in Figure 8.62. R6 = R7 = 60//60 = 30 kΩ

+ +

RC2 Vi

5 30

R6

RC1

R5

10

30

10

Vo

R7

Ril

Ri2

Figure 8.62 The ac circuit of Figure 8.61 in the mid-band

From Figure 8.29, RL 2 = 10 / /10 = 5 kΩ R7 = R3 / / R4 = 60 / / 60 = 30 kΩ R4

=

kΩ

R8 = R7 / / R c1 = 30 / / 5 = 4.29 kΩ

R8 =

kΩ

416

Electronic Devices and Circuits

The simplified Ac circuit is drawn in Figure 8.63.

4.29 Vi

30

+

Q2

Q1

+

5

RL2

Vo

R8

R6

Ril

Ri2

Figure 8.63 Simplified circuit of Figure 8.62

(i) Second stage: RL 2 = 5 kΩ AI 2 = −hfe = −100 Ri 2 = hie = 1 kΩ AV 2 = AI 2 ×

RL 2 5 = −100 × = −500 Ri 2 1

(ii) First stage: AI1 = −hfe = −100 and Ri1 = hie = 1 kΩ RL1 = Ri 2 / / R8 = 1 / /4.29 = AV1 = AI1 ×

1 × 4.29 = 0.81 kΩ 1 + 4.29

RL1 0.81 = −81 = −100 × Ri1 1

AV = AV1AV 2 = −81 × −500 = 40500 For the RC-coupled amplifier, f1 =

Therefore,

Cc =

1 1 or Cc = 2pCc (RL1 + hie ) 2pf1 (RL1 + hie )

1 1 = = 1.76 µF 2pf1 (RL1 + hie ) 2p × 50 × (0.81 + 1)103

Example 8.18 A three-stage noninteracting RC-coupled amplifier has an overall gain less by 0.3 dB at 50 kHz, when compared to the mid-band gain. Calculate f2 of the individual stages. Solution: Given,

Ah = −0.3 dB, f = 50 kHz and n = 3. Am

Multistage Amplifiers

417

We have, Ah = Am

20 log

Ah = 20 log Am

1  f  1+  ∗   f2 

2

1  f  1+  ∗   f2 

2

2

 f  20 log 1 +  ∗  = 0.3  f2 

= −0.3

2

2

 f  0.3 log 1 +  ∗  = = 0.015 20  f2  2

 f  1 +  ∗  = 1.071  f2 

 f  1 +  ∗  = 1.035  f2 

2

 f   f ∗  = 0.071 2 1

f2∗ = f2 2 n − 1

f2 =

f = 0.266 f2∗ f2∗

f2∗ =

187.97 =

1 n

2 −1

=

1 3

f 50 = 187.97 kHz = 0.266 0.266

187.97 = 368.57 kHz 0.51

2 −1

1 = 40k = hoe and hfe = 50. Calculate (i) the lower 3 dB frequency and (ii) the frequency f at which the mid-band gain falls to 12 dB. Example 8.19 For the RC-coupled amplifier shown in Figure 8.64, Cc = 5 µF, hie = 1 kΩ,=

VCC

3

RC1 50

R1

Cc

+

+ 5 Vi

R2

Vo

Ri2 = hie

RE CE −

−

Second stage

Figure 8.64 Single-stage RC-coupled amplifier

418

Electronic Devices and Circuits

Solution: The ac circuit of the single-stage amplifier is drawn in Figure 8.65, and its simplified circuit is shown in Figure 8.66. Ib Cc

+ Vi

hfeIb

hie

1/hoe

50

RC1

+

5

hie

3

Vo

R2

R1

= 40

−

−

Figure 8.65 The ac circuit of Figure 8.64

R=

1 / / RC1 = 40 / /3 = 2.8 kΩ hoe

RL = R1 / / R2 / / hie = 50 / /5 / /1 = 0.82 kΩ Ib

Ib Cc

+ Vi

hfeIb

hie

R RL

+

+

Vo

Vi

R

Cc

+ hie

−

hfeIbR +

−

Figure 8.66 Simplified low-frequency circuit of Figure 8.65

(i) Comparing Fig 8.66 with Fig 8.29 and using Eqn. 8.24 f1 =

1 1 = = 8.8 Hz . 2pCc (R + RL ) 2 π × 5 × 10 −6 (2.8 + 0.82 ) × 103

(ii) The mid-band equivalent circuit is shown in Figure 8.67. Ib + Vi

+ hie

hfeIb

¢ RL

Vo −

−

Figure 8.67 The mid-band equivalent circuit

RL ′ = RL / / R

RL

Vo

Multistage Amplifiers

419

We have, 20 log

∴

Al = 12 Am

1 f  1+  1   f 

2

f   1  1+  1  =   0.251  f

2

2

Al = 0.251 Am

= 0.251

2

 f1   f  = 14.84

f1 = 3.85 f

f =

f1 8.8 = = 2.29 Hz 3.85 3.85

Example 8.20 An n-stage FET amplifier has FETs having gm = 2 mA/V , rd = 50 kΩ , RD = 10 kΩ, RG = 100 kΩ, and Cc = 0.005 µF . CS is very large. Calculate (i) the mid-band gain, when, n = 1, 2, 3, and 4 as a dimensionless quantity and also in dB (ii) f1 of a single stage and (iii) the lower half-power frequency f1∗ when n = 2, 3, and 4. Solution: (i) (a) The mid-band gain of a single stage, that is when n = 1, is  50 × 10  / /100 = 8.33 / /1000 = 7.69 kΩ Am = − gm RL where RL = (rd / / RD ) / / RG =   50 + 10  ∴ Am = − gm RL = −2 × 7.69 = −15.38 Am ( in dB ) = 20 log (15.38 ) = 23.74 dB. (b) When n = 2, Am = Am1Am 2 = 15.38 × 15.38 = 236.54 Am ( in dB ) = 20 log ( 236.54 ) = 47.48 dB. Or alternatively Am ( in dB) = 2 × 23.74 = 47.48 dB

(c) When n = 3, Am = Am1Am 2 Am 3 = 15.38 × 15.38 × 15.38 = 3637.99 Am ( in dB ) = 20 log ( 3637.99 ) = 71.22 dB Or alternatively, Am ( in dB ) = 3 × 23.74 = 71.22 dB (d) When n = 4, Am = Am1Am 2 Am 3 Am 4 = 15.38 × 15.38 × 15.38 × 15.38 = 55952.29 Am ( in dB ) = 20 log ( 559952.29 ) = 94.96 dB

420

Electronic Devices and Circuits

Or alternatively, Am ( in dB ) = 4 × 23.74 = 94.96 dB (ii) The load for the single stage is RL ≈ rd / / RD =

50 × 10 = 8.33 kΩ 50 + 10

Ri = 100 kΩ f1 =

1 1 = 293.98 Hz = −6 2pCc (RL + Ri ) 2p × 0.005 × 10 (8.33 + 100 ) × 103

(iii) The lower half-power frequency of the cascaded amplifier is given as follows: f1

f1∗ =

1

2n −1 (a) For n = 2, f1∗ =

f1

293.98 =

1

1

2n −1 (b) For n = 3, f1∗ =

f1

293.98 =

1 n

f1 1 n

2 −1

= 1.414 − 1

22 −1

293.98 =

1 3

2 −1 (c) For n = 4, f1∗ =

293.98 =

= 1.26 − 1

293.98 = 457.20 Hz 0.643

293.98 = 576.43 Hz 0.51

2 −1 293.98 =

293.98 =

1 4

= 1.189 − 1

293.98 = 675.82 Hz 0.435

2 −1

Summary • Cascading of amplifiers influences the performance quantities of the compound amplifier configuration. • A CE–CC amplifier gives a larger output for the same given input compared to a single CE amplifier. • A CE–CC amplifier has medium Ri , large AV , and small Ro . • A CE–CE amplifier has a large AI and large AV . • A CE–CB (cascode) amplifier has large AV and minimizes Miller effect. • A Darlington emitter follower (CC–CC amplifier) gives a large Ri . It is possible to use bootstrapping technique for making Ri very large. • The mid-band gain of an RC-coupled amplifier is constant, whereas the low-frequency and the highfrequency gains tend to become poor due to Cc and Cs , respectively. • A transformer-coupled amplifier is not preferably used in the low-frequency range (audio frequency range) mainly because of the size of the transformer. • Direct-coupled amplifiers have flat frequency response characteristic right from 0 Hertz. • Drift is a major problem in direct-coupled amplifiers.

Multistage Amplifiers

421

multiple ChoiCe QueStionS 1. The following compound amplifier has the highest AI and large AV (a) CE–CE (c) CE–CB

(b) CE–CC (d) CC–CC

2. A Cascode amplifier is a cascaded (a) CE–CE amplifier (c) CE–CB amplifier

(b) CE–CC amplifier (d) CB–CE amplifier

3. The advantage of a cascode amplifier is that it (a) minimizes Miller effect (c) gives small Ro

(b) gives large Ri (d) none of these

4. The effective Ri of a Darlington emitter follower is reduced by the biasing resistors. The following procedure is used to make the effective Ri very large: (a) Negative feedback is used. (b) Positive feedback is used. (c) Bootstrapping is used. (d) Negative resistance device is used. 5. The mid-band gain of an RC-coupled amplifier (a) increases linearly with frequency (b) decreases linearly with frequency (c) remains constant (d) none of these 6. The low-frequency gain of an RC-coupled amplifier tends to become poor due to (a) Cc (b) Cs (c) hfe (d) hie 7. The high-frequency gain of an RC-coupled amplifier tends to become poor due to (a) Cc (b) Cs (c) hfe (d) hie 8. The major problem in dc amplifiers is (a) drift (c) small gain

(b) biasing (d) large gain

9. A transformer-coupled amplifier is usually not preferred in the audio frequency range because (a) the gain becomes very large (b) the gain becomes very small (c) the transformer becomes bulky (d) the transformer has no weight 10. Three identical, noninteracting CE amplifiers are cascaded, each having a gain of 10. The overall gain is (a) 10 (b) 100 (c) 1000 (d) 10000

422

Electronic Devices and Circuits

Short anSwer QueStionS Where is the need for cascaded amplifiers? What are the different types of interstage coupling techniques used in multistage amplifiers? How is the mid-band range in an RC-coupled amplifier defined as? What is meant by bootstrapping? What is Miller effect? What are the two main advantages of a cascode amplifier? What is the advantage of a Darlington transistor? Why is a Darlington transistor preferably used in an emitter follower? In a three-stage CE amplifier, what will be the bandwidth when bandwidth of the single-stage amplifier is f2? 10. What is drift in dc amplifiers? 1. 2. 3. 4. 5. 6. 7. 8. 9.

long anSwer QueStionS For a CE–CC amplifier derive the expressions for AV , Ri , and Ro . For a CE–CB amplifier derive the expressions for AV , Ri, and Ro . For a CC–CC amplifier derive the expressions for AV, Ri, and Ro. Draw the ac circuit of a single-stage RC-coupled amplifier and derive the expressions for Am , Al , and Ah using the approximate model for the transistor. 5. Derive the expression for the low-frequency gain of a CE amplifier in which CE is not an effective bypass condenser. 1. 2. 3. 4.

unSolved problemS 1. For the Darlington emitter follower shown in Figure 8.15, Rs = RE = 1 kΩ, hie = 1.1 kΩ, hfe = 100, and hre = hoe = 0. Find Ri, AI, AV, and Ro. 2. For the amplifier circuit shown in Figure 8.68, hie = 1 kΩ, hfe = 50, hre = hoe = 0, RL = 4 kΩ, and Rs = 0. Calculate Ri, AV, and Ro? 3. For the circuit in Figure 8.1, hie = 1 kΩ, hfe = 100, hre = hoe = 0, RC = 4 kΩ, Rs = 1 kΩ, and RE = 2 kΩ. Find AV. VCC

Q2

RL

Q1

+

+

Vi

Vo CB

Ro2 = Ro Ri1 = Ri

Ri2

Figure 8.68 CE–CB amplifier

Multistage Amplifiers

423

4. In an RC-coupled amplifier the transistor used has hie = 1 kΩ and hfe = 50. RC = 2 kΩ. hoe = hre = 0. Find (i) The mid-band gain, (ii) the value of Cc required to give a lower 3 dB frequency of 20 Hz, and (iii) the value of CS required to give an upper 3 dB frequency of 100 kHz. 5. For the circuit in Figure 8.38, calculate the size of CE to provide f1 = 20 Hz, when RE = 1 kΩ, hie = 1 kΩ, and hfe = 50. VCC

5

Re1

5

Rc2 Rs 1

Q2

Q1

+ Vo + Vs

Re2 500

−

Figure 8.69 Amplifier 6. For the amplifier circuit shown in Figure 8.69, calculate AV, given that hfe = 50, hie = 1 kΩ, hoe = 0, and hrc = 1.

9

FEEDBACK AMPLIFIERS

Learning objectives After going through this chapter the reader will be able to     

9.1

Understand the need for feedback in an amplifier Realize the four basic feedback amplifier topologies Appreciate the advantages when negative feedback is used in an amplifier Derive the expressions for the performance quantities of the feedback amplifiers Analyze voltage series, current series, voltage shunt and current shunt feedback amplifiers

INTRODUCTION

The analysis of voltage amplifiers is considered in Chapter 6. Then, it is known that the gain of a single-stage amplifier, say a CE amplifier, depends not only on the external circuit components provided in the circuit but also on the device parameters. The voltage gain of a CE amplifier is given by the following expression: A = AI

RL Ri

Here, AI is the current gain and RL and Ri are the load and input resistances, respectively. Using the approximate model for the transistor and assuming Rs = 0, A = − hfe (RL hie ) . If for the given transistor hfe = 100, hie = 1.1 kΩ, and RL = 2.2 kΩ, then A = −100 × (2.2 1.1) = −200 ; and if Vi = 1 mV , then Vo = AVi = 200 × 1 = 200 mV . The minus sign accounts for phase inversion in a CE amplifier. If the transistor used has been replaced by an identical transistor or if the transistor has been used for a relatively long time, which is referred to as aging, there is a possiblility that the parameters of the device may not be the same as that of the earlier used device. Further, it is noted that temperature variations can cause a change in the device parameters. Now assume that due to any of these reasons hfe has increased to 110, then A = −110 × (2.2 1.1) = −220 . And once again if Vi = 1 mV , then Vo = AVi = 220 × 1 = 220 mV . The output has now increased by 10 percent. In practice, the gain of the amplifier is required to remain unchanged mostly against temperature variations. In order to meet this objective, feedback must be used in the amplifier.

Feedback Amplifiers

425

Therefore, the feedback is essentially used in an amplifier to stabilize the gain. In a feedback amplifier, the output is sampled to see if it has changed from the desired value or not. If it has changed, either increased or decreased, then a corrective mechanism must be used at the input so as to bring back the output once again to the desired value by taking a part of the output to the input through a feedback network.

9.2 THE FEEDBACK AMPLIFIER The basic feedback amplifier is shown in Figure 9.1. The feedback amplifier basically consists of an internal amplifier whose gain A is required to be stabilized. The sampling network samples the output. If the output changes, a small fraction of the output is fed back to the input in phase opposition to the already available input Vs . The difference of Vs and Vf , which is Vi is fed as input to the internal amplifier.

RS +

Mixing network

Vs

+

Vi

Internal amplifier A

Sampling network

+ Vo

RL

+ Vf

Feedback or b-network b

Figure 9.1 Feedback amplifier

If for some reason or the other Vo increases, then Vf increases. As Vi = (Vs − Vf ), Vi decreases, and hence Vo is brought back to the original value. Alternately, if Vo decreases, then Vf decreases and Vi increases, and hence Vo is brought back to the original value. This is the principle of a feedback amplifier. Let us now see what each of the blocks mean to us.

9.2.1 Sampling Network The purpose of a sampling network is to sense or monitor the output. The requirement of the amplifier is that the output Vo should remain unaltered despite the variations of the parameters of the device. If, for any reason, Vo changes it should be brought back to the desired value. There are two methods of sampling: (i) voltage sampling or node sampling and (ii) current sampling or loop sampling.

426

Electronic Devices and Circuits

(i) Voltage sampling or node sampling: In voltage sampling, a potential divider network comprising R1 and R2 is connected in shunt with the load. However, it must be ensured that this potential divider network is not going to change the load to the amplifier, Figure 9.2. Although the output of the b-network in the present case is a voltage Vf , in general it can be a current or a voltage.

Sampling network

R1 + Vf −

+ Vo

RL

+ Vo

R2 b-network

Figure 9.2 Voltage sampling

(ii) Current sampling or loop sampling: In current sampling the load current I o is made to flow through the b-network, which in turn can derive in the output a current or a voltage as shown in Figure 9.3.

Sampling network

+ Vo

RL

Io

b-network

Figure 9.3 Current sampling

9.2.2 b-Network Having sampled the output, a small fraction of the output is taken to the input and connected at the input in such a way that if the output is increased, the actual input to the amplifier is decreased, thereby once again bringing back the output to the desired value and vice versa. The network that derives the feedback signal is called the b-network or feedback network. As mentioned earlier, the output of the b-network can either be a voltage or a current that is derived either by sampling the output voltage or output current.

Feedback Amplifiers

427

9.2.3 Mixing Network The output of the b-network is connected at the input such that the output of the amplifier is brought back to the desired value, if it changes. There are basically two methods of mixing: (i) series and (ii) shunt. (i) Series mixing: In this method, the output of the b-network is connected in series with the input signal. When it is said that series mixing is used at the input, it obviously means that the output of the b-network is a voltage and the driving source is a voltage (Thévenin’s) source as shown in Figure 9.4).

+

+ Vi −

Vs −

− V + f

Internal amplifier A

Feedback or b-network b

Figure 9.4 Series mixing

(ii) Shunt mixing: In this method, the output of the b-network is connected in shunt with the input signal. When it is said that shunt mixing is used at the input, it obviously means that the output of the b-network is a current and the driving source is a current (Norton) source as shown in Figure 9.5. Ii

Is

If

Internal amplifier A

Feedback or b-network b

Figure 9.5 Shunt mixing

Hitherto, we have seen that either series mixing or shunt mixing can be used at the input and voltage, or current sampling can be used at the output. Based on how the signal is sampled at the output and how it is mixed at the input, amplifiers are classified into four basic feedback amplifier topologies: (i) voltage series feedback amplifier, (ii) current series feedback amplifier, (iii) voltage shunt feedback amplifier, and (iv) current shunt feedback amplifier. From the above classification, it is evident that the first term represents the type of sampling, whereas the second term represents the type of mixing. The four feedback amplifiers are schematically represented in Figure 9.6.

428

Electronic Devices and Circuits

+ Vs −

− V + f

+ Vi −

Internal amplifier A

+

Vo

RL

+ Vs −

− V + f

+ Vi −

+

Internal amplifier A

Vo RL

Io Feedback or b-network b

Feedback or b-network b

(a) Voltage series feedback amplifier

(b) Current series feedback amplifier Ii

Ii

Is

If

Internal amplifier A

+

V RL o

Is

If

Feedback or b-network b

Internal amplifier A

+

Feedback or b-network b

(c) Voltage shunt feedback amplifier

V RL o

Io

(d) Current shunt feedback amplifier

Figure 9.6 Feedback amplifier topologies

9.3

CALCULATION OF THE GAIN OF THE FEEDBACK AMPLIFIER

(i) Consider the voltage series feedback amplifier shown in Figure 9.7 The gain with feedback is calculated as follows: Vo Vs

(9.1)

Vo or Vo = AVVi Vi

(9.2)

Vs = Vi + Vf

(9.3)

Vf = bVo

(9.4)

Vs = Vi + bVo

(9.5)

AV = f

AV, the gain of the internal amplifier is AV = From Figure 9.7,

and

Substituting Eqn. (9.4) in Eqn. (9.3),

Feedback Amplifiers

429

Using Eqs (9.5) and (9.2), Eqn. (9.1) is written as follows: AV = f

Vo AVVi AV = = Vs (Vi + bAVVi ) 1 + bAV

+ Vs −

+ Vi

AV

bV o

b

− Vf +

(9.6)

+ Vo −

RL

Figure 9.7 Voltage series feedback amplifier

It can be seen from Eqn. (9.6) that the gain of a feedback amplifier is the ratio of gain without feedback AV and (1+ AV b ) . (ii) Now consider the current series feedback amplifier shown in Figure 9.8. + Vs −

+ Vi

GM

bIo

b

Io

RL

− V + f

Figure 9.8 Current series feedback amplifier

In this amplifier, it can be seen that the input is a voltage Vs and the desired output signal is a current I o . The ratio of this output current I o to input voltage Vs is called the transconductance gain. The transconductance gain without feedback is GM and that with feedback is GMf . The gain with feedback is calculated as follows: Io Vs

(9.7)

Io or I o = GMVi Vi

(9.8)

GM = f

GM the gain of the internal amplifier is GM =

430

Electronic Devices and Circuits

From Figure 9.8, Vs = Vi + Vf

(9.9)

Vf = bI o

(9.10)

Vs = Vi + bI o

(9.11)

and

Substituting Eqn. (9.10) in Eqn. (9.9),

Using Eqs (9.11) and (9.8), Eqn. (9.7) is written as follows: GM = f

Io GMVi GM = = Vs (Vi + bGMVi ) 1 + bGM

(9.12)

(iii) Consider the circuit in Figure 9.9. Ii Is

If

RM

+ Vo −

RL

b

Figure 9.9 Voltage shunt feedback amplifier

In this amplifier, it can be noted that the input is a current I s , and the desired output signal is a voltage Vo . The ratio of this output voltage Vo to input current I s is called the transresistance gain. The transresistance gain without feedback is RM and that with feedback is RMf . The gain with feedback is calculated as Vo Is

(9.13)

Vo or Vo = RM I i Ii

(9.14)

Is = I i + If

(9.15)

I f = bVo

(9.16)

RM = f

RM, the gain of the internal amplifier is RM = From Figure 9.9,

and

Feedback Amplifiers

431

Substituting Eqn. (9.16) in Eqn. (9.15), I s = I i + bVo

(9.17)

Using Eqs (9.17) and (9.14), Eqn. (9.13) is written as follows: RM = f

Vo RM I i RM = = I s ( I i + bRM I i ) 1 + bRM

(9.18)

(iv) Consider Figure 9.10 Ii Is

If

Io

AI

RL

b

Figure 9.10 Current shunt feedback amplifier

In this amplifier, it can be noted that the input is a current I s and the desired output signal is a current I o. The ratio of this output current I o to input current I s is called the current gain. The current gain without feedback is AI and that with feedback is AI . f

The current gain with feedback is calculated as follows: Io Is

(9.19)

Io or I o = AI I i Ii

(9.20)

Is = I i + If

(9.21)

I f = bI o

(9.22)

I s = I i + bI o

(9.23)

AI = f

AI , the gain of the internal amplifier is AI = From Figure 9.10,

and

Substituting Eqn. (9.22) in Eqn. (9.21),

432

Electronic Devices and Circuits

Using Eqs (9.23) and (9.20), Eqn. (9.19) is written as follows: AI = f

Io AI I i AI = = I s ( I i + bAI I i ) 1 + bAI

(9.24)

In general, the expression for the gain of a feedback amplifier can be written as follows: Af =

A 1 + Ab

(9.25)

where Af can be AVf , GMf , RMf , or AIf , and A can be AV , GM , RM , or AI , depending on the topology. Therefore, it is obvious that to calculate the gain with feedback, it is necessary to calculate the gain without feedback and b . From Eqn. (9.25), (i) If (1 + Ab ) > 1, then Af < A. If the gain with feedback is smaller than the gain without feedback, then negative or degenerative feedback is said to be used in the amplifier. (ii) If (1 + Ab ) < 1, then Af > A. If the gain with feedback is greater than the gain without feedback, then positive or regenerative feedback is said to be used in the amplifier. 1 (iii) If Ab >> 1, then Af = . This condition says that the gain of the feedback amplifier is b inversely proportional to b. The gain is independent of temperature variable parameters and is solely decided by the b-network. As long as the b-network is stable, the gain of the feedback amplifier is stable, which is the obvious requirement. Further, the frequency response characteristic of the amplifier is the inverse frequency response characteristic of the b-network. Thus, it is possible to get the desired frequency response characteristic for the amplifier by choosing a b-network that has the desired inverse frequency response characteristic. Vo = ∞. As Af → ∞, Vs → 0. This means that the amplifier gives a Vs finite output even with zero input. Such an amplifier is called an oscillator (Figure 9.11). Thus, we see that if the condition (1 + Ab ) = 0 is satisfied in an amplifier, then the amplifier is called an oscillator and the condition (1 + Ab ) = 0 is called Barkhausen criterion. We consider oscillators in Chapter 10.

(iv) If (1 + Ab ) = 0, then Af =

Vs = 0

+ Vi

AV

bV o

b

− Vf +

Figure 9.11 Feedback oscillator

Load

Feedback Amplifiers

433

When we consider an amplifier, our main concern is the stability of gain. An amplifier in which negative feedback is used ensures better gain stability. The amount of negative feedback used in an amplifier is defined as the ratio of the power output without feedback to power output with feedback, for the same input and is expressed in dB. Amount of dB feedback used is 10 log10 Power output without feedback Po =

Po for the same input. Po′

Vo 2 , where Vo is the output voltage without feedback. RL

V ′2 Power output with feedback Po′ = o , where Vo′ is the output voltage with feedback for the RL same input. V2 R  V  V V  Amount of dB feedback used = 10 log10  o 2 L  = 20 log10  o  = 20 log10  o s   Vo′   Vo′ Vs   Vo′ RL   A Amount of dB feedback used = 20 log10   = 20 log10 (1 + Ab )  Af 

(9.26)

If (1 + Ab ) = 10, then amount of dB feedback used is 20 log10 10 = 20 dB. In addition to gain stability, negative feedback in an amplifier gives us a few more additional advantages.

9.4

ADVANTAGES OF NEGATIVE FEEDBACK

 1 It has already been noted that large amount of negative feedback makes the gain stable  Af =  . b  However, even if the amount of negative feedback incorporated is not large, it can be shown that negative feedback in an amplifier improves gain stability.

9.4.1 Improved Gain Stability From Eqn. (9.25), the expression for the gain of the feedback amplifier is Af =

A A = . D is 1 + Ab D

called the return difference. If there is an incremental change in the gain of the internal amplifier by dA , then the gain of the feedback amplifier changes by dAf . To find out the incremental change in gain of the feedback amplifier, we differentiate Eqn. (9.25): dAf =

(1 + Ab ) dA − AbdA = dA (1 + Ab )2 (1 + Ab )2

dAf  dA   1   dA   (1 + Ab )  = 2  2   =  Af  (1 + Ab )   Af   (1 + Ab )   A 

434

Electronic Devices and Circuits

dA dAf = A 1 + Ab Af

(9.27)

dAf dA is the percent change in the gain of the internal amplifier and is the percent change A Af dAf 20 dA in gain of the feedback amplifier. If is 20% and (1 + Ab ) = 10 , then = = 2%. This 10 A Af means that if the gain of the internal amplifier changes by 20 percent, then the gain of the feedback amplifier changes only by 2 percent. That is, negative feedback in an amplifier gives better gain stability.

9.4.2 Improved Bandwidth While considering an RC -coupled amplifier in Chapter 8, we have derived the expressions for the gains in the high-frequency range, Ah and in the low-frequency range, Al in terms of the gain in the mid-band range, Am as follows: Ah =

Am w 1+ j    w2 

Al =

Am w  1+ j  1  w

and

(9.28)

(9.29)

A And from Eqn. (9.25), the gain with feedback is Af = . Therefore, the high-frequency gain 1 + Ab with feedback is Ahf =

Ah 1 + Ah b

(9.30)

Substituting Eqn. (9.28) in Eqn. (9.30), Am w 1+ j    w2  Am Ahf = = = Am b w 1+ 1 + Am b + j   1 + w  w2  1+ j    w2  Ahf =

Am′ w 1+ j    w 2′ 

Am 1 + Am b   w j   (1 + Am b ) w 2 

(9.31)

Feedback Amplifiers

435

where Am′ =

Am 1 + Am b

(9.32)

and w 2′ = (1 + Am b ) w 2

(9.33)

From Eqn. (9.32), it can be noted that the gain in the mid-band, Am is reduced to Am′ , since (1+ Am b ) is greater than 1. However, the new upper half-power frequency w 2′ is greater than w 2 Eqn. (9.33). Once again using Eqn. (9.25), Alf =

Al 1 + Al b

(9.34)

Substituting Eqn. (9.29) in Eqn. (9.34), Am w  1+ j  1  w  Am Alf = = = Am b w1   1+ 1 + Am b + j   1 + w  w  1+ j  1  w  Alf =

Am 1 + Am b   w1 j   (1 + Am b )w 

Am′  w ′ 1+ j  1  w 

(9.35)

where w1′ =

w1 1 + Am b

(9.36)

Gain Am 0.707 Am Am′ 0.707 Am′

ω1′

ω1

ω2

ω2′

ω

Figure 9.12 Frequency response characteristics with and without feedback

From Eqn. (9.35), it can be noted that the gain in the mid-band, Am is reduced to Am′ , since (1+ Am b ) is greater than 1, and the new lower half-power frequency w1′ is smaller than w1 as shown in Eqn. (9.36). Now, let us look at the frequency response characteristics of the amplifier with and without feedback, Figure 9.12. w1 and w1′ are small when compared to w 2 and w 2′ .

436

Electronic Devices and Circuits

Therefore, w 2 and w 2′ are practically the bandwidths of the amplifiers without and with feedback. Taking the product of the gain and bandwidth of the amplifier with feedback, using Eqs (9.32) and (9.33), we have, Am (1 + Am b )w 2 = Amw 2 (1 + Am b )

Gain × bandwidth = Am′ w 2′ =

(9.37)

Equation (9.37) shows that the gain bandwidth product with feedback is the same as the gain bandwidth product without feedback. Hence, it can be said that the gain bandwidth product of an RC-coupled amplifier is constant.

9.4.3 Reduced Harmonic Distortion We have already noted, while considering small signal and large signal amplifiers, that harmonic distortion can be present in the output of an amplifier, if the operation is not restricted to a limited region in the transfer characteristic, in which region the characteristic can be approximated by a straight line. Thus, if the input swing is large, the harmonic distortion can be present in the output of a voltage amplifier, which is unwanted. It was noted earlier that ic = Bo + B1 cos wt + B2 cos 2wt + B3 cos 3wt + ... where B1 is the magnitude of the fundamental, and B2 , B3, B4 , etc., are the magnitudes of the harmonics. We now show that negative feedback in an amplifier reduces harmonic distortion. Let us now consider an amplifier without feedback in which harmonic distortion is present, Fig. 9.13(a) + Vs −

+

Vh

A

− Vo

+ RL −

+

+ V′s − +

Vf

(a) Amplifier without feedback

+ Vi − −

Vh

A

− RL

+ Vo = V′o −

(b) Amplifier with feedback

Figure 9.13 Harmonic distortion in an amplifier

From Figure 9.13(a), Vo = AVs + Vh

(9.38)

But when feedback is used in an amplifier, Fig. 9.13(b) the output is no longer Vo , but is Vo′ which is smaller than Vo . Obviously, the harmonic component in the output becomes small. However, to make a realistic comparison, the output with feedback should also be made equal to the output without feedback (Vo = Vo′), and then the harmonic components in the two outputs need to be compared. For this to happen, the input must be increased. We now try to get the value of the input Vs′ for which Vo = Vo′. We have Vo = AVs and Vo′ = AV f s , which is smaller than Vo . To make Vo = Vo′, Vs is increased to Vs′. Then, Vo′ = AV f s′ . Since now, Vo = Vo′,

Feedback Amplifiers

437

AVs = AV f s′ Vs′ =

AVs Af

But from Eqn. (9.25), A = (1 + Ab ) Af Therefore, Vs′ = (1 + Ab )Vs

(9.39)

1 Vo or Now with feedback, a small fraction of this output is fed back to the input (may be 50 1 Vo ), which is a small fraction of Vo . When compared to the signal at the output, the harmonic 100 component is very small. Hence, the harmonic component that is fed back to the input is negligible and is not taken into account. From Figure 9.13(b), Vo′ = (Vs′− Vf ) A + Vh

(9.40)

But Vf = bVo′ Vo′ = AVs′− AbVo′ + Vh Using Eqn. (9.39), Vo′ (1 + Ab ) = AVs (1 + Ab ) + Vh Vo = Vo′ = AVs +

Vh

(1 + Ab )

(9.41)

Comparing Eqs (9.38) and (9.41), it can be seen that the signal component in the output in both the cases is AVs where as the harmonic component in the output without feedback is Vh and Vh that in the output of the amplifier with feedback is . (1+ Ab ) is a quantity greater than 1. 1+ ( Ab ) Hence, negative feedback in an amplifier reduces harmonic distortion.

438

Electronic Devices and Circuits

9.4.4 Reduced Noise Noise in an amplifier can be due to external sources or can be internally generated. Noise is an unwanted signal in the output of an amplifier. Just as we have seen that harmonic distortion can be reduced in a feedback amplifier, on similar lines we can also show that noise is reduced in an amplifier. Only thing that we have to do is to replace the harmonic generator by a noise generator, Vn. Vn It can be seen that noise with feedback is . (1+ Ab )

9.4.5 Disadvantage with Negative Feedback in an Amplifier As the gain of a feedback amplifier is smaller than the gain without feedback, in order to get a larger output, there arises the need to cascade more number of stages that add to cost. Example 9.1 An amplifier has an open-loop gain of 1000. This gain varies by ±100, and feedback is introduced to ensure that the voltage gain varies by not more than ±0.1%. Find (i) b and (ii) Af. Solution: dA dAf = A 1 + Ab Af dAf 0.1 = 0.1% = = 0.001 100 Af Given A = 1000 and dA = 100 Hence, dA 100 = = 0.1 A 1000 From Eqn. (9.27), dA dAf = A Af 1 + Ab 0.001 =

1 + Ab = (i) Ab = 100 − 1 = 99 (ii) Af =

b =

1000 A = = 10 1 + Ab 100

99 = 0.099 1000

0.1 1 + Ab 0.1 = 100 0.001

Feedback Amplifiers

9.5

439

CALCULATION OF INPUT RESISTANCE OF A FEEDBACK AMPLIFIER

When negative feedback is introduced in an amplifier, the input and output resistances get altered. If Ri is the input resistance of an amplifier without feedback, then Rif is the input resistance with feedback. Rif is larger or smaller than Ri , depending on the type of mixing (series or shunt) used at the input.

9.5.1 Calculation of the Input Resistance with Series Mixing Input resistance gets altered depending on the type of mixing used at the input. Let us consider the influence of series mixing on the input resistance of a feedback amplifier. For this, we may consider either a voltage series feedback amplifier or a current series feedback amplifier. In both the cases, the type of mixing used at the input is series mixing. 1. Voltage series feedback amplifier Voltage series feedback amplifier is considered here (Figure 9.14). From the input circuit of Figure 9.14, Rif =

Vs Ii

(9.42)

Vs = Vi + Vf = Vi + bVo

(9.43)

 RL  Vo = AvVi  = AVVi  Ro + RL 

(9.44)

From the output circuit,

where AV = Av finite RL .

RL , Av is the voltage gain with RL = ∞, and AV is the voltage gain with Ro + RL

Ii + + Vi Ri

Vs − − Rif

Vf

− +

+ AvVi −

+

Ro RL

Vo −

Amplifier Ri

Figure 9.14 Series mixing–voltage series feedback amplifier

440

Electronic Devices and Circuits

 RL  Av Lim Lim Lim A = A = = Av RL → ∞ V RL → ∞ v  Ro + RL  RL → ∞ Ro +1 RL Thus, Av is AV in which RL → ∞. Substituting Eqn. (9.44) in Eqn. (9.43), Vs = Vi + bVo = Vi + bAVVi = Vi (1 + AV b ) = I i Ri (1 + AV b ) Rif =

Vs I i Ri (1 + AV b ) = = Ri (1 + AV b ) = Ri D Ii Ii

(9.45) (9.46)

The input resistance of a voltage series feedback amplifier is the input resistance without feedback, Ri multiplied by D . As D is greater than 1, Rif > Ri. 2. Current series feedback amplifier A current series feedback amplifier is considered here (Figure 9.15). From the input circuit of Figure 9.15, Rif =

Vs Ii

(9.47)

Vs = Vi + Vf = Vi + bI o

(9.48)

From the output circuit, I o = GmVi

Ro = GMVi Ro + RL

(9.49)

Ro , Gm is the transconductance gain with RL = 0, and GM is the Ro + RL transconductance gain with finite RL . where GM = Gm

Ii + + Vi Ri

Vs − − Rif

Vf

GmVi

Ro

− +

Io

+

RL

Vo −

Amplifier Ri

Figure 9.15 Series mixing–current series feedback amplifier

 Ro  Lim Lim G = G = Gm RL → 0 M RL → 0 m  Ro + RL 

Feedback Amplifiers

441

Thus, Gm is GM in which RL → 0. Substituting Eqn. (9.49) in Eqn. (9.48), Vs = Vi + bI o = Vi + bGMVi = Vi (1 + GM b ) = I i Ri (1 + GM b ) Rif =

Vs I i Ri (1 + GMb ) = = Ri (1 + GM b ) = Ri D Ii Ii

(9.50) (9.51)

The input resistance of a current series feedback amplifier is the input resistance without feedback, Ri multiplied by D . Thus, it can be concluded that whatever be the type of sampling used at the output, as long as the mixing at the input is series mixing, the input resistance with feedback is the input resistance without feedback multiplied by D. This means that the input resistance increases with series mixing. Because the signal that drives the amplifier is a voltage, the input resistance of the amplifier should be very much larger than the source resistance, for the entire signal to appear between the actual input terminals of the amplifier. Hence, this is a welcome requirement.

9.5.2 Calculation of the Input Resistance with Shunt Mixing Let us consider the influence of shunt mixing on the input resistance of a feedback amplifier. For this, we may consider either a voltage shunt feedback amplifier or a current shunt feedback amplifier. In both the cases, the type of mixing used at the input is shunt mixing. 1. Voltage shunt feedback amplifier Voltage shunt feedback amplifier is considered here (Figure 9.16). From the input circuit of Figure 9.16, Rif =

Vi Is

I s = I i + I f = I i + bVo

(9.52) (9.53)

From the output circuit, Vo = Rm I i where RM = Rm finite RL .

RL = RM I i Ro + RL

(9.54)

RL , Rm is the transresistance gain with , RL = ∞ and RM is the gain with Ro + RL  RL  Rm Lim Lim Lim R = R = = Rm RL → ∞ M RL → ∞ m  Ro + RL  RL → ∞ Ro +1 RL

Thus, Rm is RM in which RL → ∞. Substituting Eqn. (9.54) in Eqn. (9.53), I s = I i + bVo = I i + bRM I i = I i (1 + RM b )

(9.55)

442

Electronic Devices and Circuits

Rif =

Vi I i Ri Ri R = = = i I s I i (1 + RMb ) (1 + RMb ) D

(9.56)

The input resistance of a voltage shunt feedback amplifier is the input resistance without feedback, Ri divided by D. As D is greater than 1, Rif < Ri. Ii +

+

If Vi

Is

+

Ro RL

Rm I i

Ri

−

−

Vo −

Amplifier Ri

Rif

b-network

Figure 9.16 Shunt mixing–voltage shunt feedback amplifier

2. Current shunt feedback amplifier A current shunt feedback amplifier is considered here (Figure 9.17). From the input circuit of Figure 9.17, Ii +

Io

If Vi

Is

AiIi

Ri

Ro

RL

− Amplifier Rif

Ri b-network

Figure 9.17 Shunt mixing–current shunt feedback amplifier

Rif =

Vi Is

I s = I i + I f = I i + bI o

(9.57) (9.58)

From the output circuit, I o = Ai I i

Ro = AI I i Ro + RL

(9.59)

Feedback Amplifiers

443

where AI = Ai Ro , Ai is the current gain with RL = 0, and AI is the current gain with Ro + RL finite RL .  Ro  Lim Lim A = A = Ai RL → 0 I RL → 0 i  Ro + RL  Thus, Ai is AI in which RL → 0 . Substituting Eqn. (9.59) in Eqn. (9.58), I s = I i + bI o = I i + bAI I i = I i (1 + AI b ) = I i (1 + AI b ) Rif =

Vi I i Ri Ri R = = = i I s I i (1 + AI b ) (1 + AI b ) D

(9.60) (9.61)

The input resistance of a voltage shunt feedback amplifier is the input resistance without feedback, Ri divided by D. Thus, it can be concluded that whatever be the type of sampling used at the output, as long as the mixing at the input is shunt mixing, the input resistance with feedback is the input resistance without feedback divided by D. This means that the input resistance decreases with shunt mixing. Because the signal that drives the amplifier is a current, the input resistance of the amplifier should be very much smaller than the source resistance, for the entire signal current to flow through the actual input terminals of the amplifier. Hence, this is a welcome requirement.

9.6

CALCULATION OF OUTPUT RESISTANCE OF THE FEEDBACK AMPLIFIER

When negative feedback is introduced in an amplifier, the output resistance gets altered. If Ro is the output resistance of an amplifier without feedback, then Rof is the output resistance with feedback. Rof is larger or smaller than Ro , depending on the type of sampling (voltage or current) used at the output.

9.6.1 Calculation of the Output Resistance with Voltage Sampling Let us consider the influence of voltage sampling on the output resistance of a feedback amplifier. For this, we may consider either a voltage series feedback amplifier or a voltage shunt feedback amplifier. In both the cases, the type of sampling used at the output is voltage sampling. The procedure to calculate the output resistance is as follows: (i) Let RL → ∞. That is, open the load RL . (ii) Introduce a voltage source V at the output and find out the circulating current, I . (iii) The ratio of V to I with Vs = 0 (short the input voltage source) or I s = 0 (open circuit the input current source) is the output resistance. 1. Voltage series feedback amplifier Voltage series feedback amplifier in which the output voltage is sampled is shown in Figure 9.18.

444

Electronic Devices and Circuits Ii

I +

Vs = 0

+

Vi Ri

−

Vf

Ro

AvVi −

− +

+ V

Open RL Introduce V = Vo

−

Amplifier

Figure 9.18 Voltage sampling—voltage series feedback amplifier

From the output circuit of Figure 9.18, I=

V − AvVi Ro

(9.62)

With Vs = 0, Vi = −Vf = − bVo = − bV

(9.63)

since Vo = V . Substituting Eqn. (9.63) in Eqn. (9.62), I=

V − Av ( − bV ) V (1 + Av b ) = Ro Ro

(9.64)

From Eqn. (9.64), Rof =

Ro V = I (1 + Av b )

(9.65)

The output resistance with feedback, for a voltage series feedback amplifier, is calculated using Eqn. (9.65). Sometimes, calculating the output resistance using Eqn. (9.65) may not be possible (we will consider this fact when we analyze a specific amplifier later) since we may end up with an indeterminate quantity. Then, an alternate way out would be to first calculate Rof′ , where Rof′ is the parallel combination of Rof and RL . Having calculated Rof′ , we then let RL → ∞ in it. We get Rof . Using Eqn. (9.65), Ro RL (1 + Av b ) = Rof RL Ro RL Rof′ = Rof || RL = = R Rof + RL Ro + RL + Av bRL o +R (1 + Av b ) L Ro RL Ro + RL Ro′ R′ = = = o RL 1 + AV b D 1 + bAv Ro + RL

(9.66)

Feedback Amplifiers

445

where Ro′ = Ro || RL the output resistance without feedback taking RL into account and RL AV = Av . The output resistance decreases with voltage sampling. Ro + RL 2. Voltage shunt feedback amplifier Voltage shunt feedback amplifier, in which the sampled output signal is once again voltage, is considered here (Figure 9.19). From the output circuit of Figure 9.19, V − Rm I i I= (9.67) Ro With I s = 0, I i = − I f = − bVo = − bV

(9.68)

since Vo = V . Substituting Eqn. (9.68) in Eqn. (9.67), I=

V − Rm ( − bV ) V (1 + Rm b ) = Ro Ro

(9.69)

From Eqn. (9.69), Rof =

Ro V = I (1 + Rm b )

(9.70)

The output resistance with feedback, for a voltage shunt feedback amplifier, is calculated using Eqn. (9.70). We also calculate Rof′ , where Rof′ is the parallel combination of Rof and RL . Using Eqn. (9.70),

Ro RL R′ R R Ro′ (1 + Rm b ) = Rof′ = Rof || RL = of L = = o Ro D Rof + RL 1 + RM b + RL (1 + Rm b )

(9.71)

RL . The output resistance with feedback is smaller than Ro + RL the output resistance without feedback, which in fact is the requirement to ensure that the entire output voltage appears across the load terminals. where Ro′ = Ro || RL and RM = Rm

Ii Open Is

Is

I +

If

RmIi

Ri

Ro

+ V Open RL Introduce V −

− Amplifier

b-network

Figure 9.19 Voltage sampling—voltage shunt feedback amplifier

446

Electronic Devices and Circuits

9.6.2 Calculation of the Output Resistance with Current Sampling To calculate the output resistance with feedback, with current sampling at the output, we can consider current series and current shunt feedback amplifiers. 1. Current series feedback amplifier Consider the current series feedback amplifier (Figure 9.20). Writing down the KCL equation at node C, GmVi + I =

V Ro

(9.72)

With Vs = 0, Vi = −Vf = − bI o = bI

(9.73)

Substituting Eqn. (9.73) in Eqn. (9.72), Gm bI + I = I (1+ Gm b ) =

V Ro V Ro

(9.74)

Ii

I +

Vs = 0 Short Vs

−

Vf

Io

C +

Vi Ri

GmVi

Ro

Open RL Introduce V

V −

− +

Amplifier

Figure 9.20 Current sampling—current series feedback amplifier

Rof =

V = Ro (1 + Gm b ) I

(9.75)

Ro RL (1 + Gm b ) Ro RL (1 + Gm b ) Ro RL (1 + Gm b ) Ro + RL Rof RL Rof′ = Rof || RL = = = = G bR Rof + RL Ro (1 + Gm b ) + RL Ro + RL + Gm bRo 1+ m o Ro + RL Rof′ = Ro′

(1 + Gm b ) = R ′ (1 + Gm b ) (1 + GM b ) o D

(9.76)

From Eqn. (9.75), it can be noted that the output resistance with feedback is larger than the output resistance without feedback, and this is advantageous because most of the output current is now allowed to flow through the load RL .

Feedback Amplifiers

447

2. Current shunt feedback amplifier Consider the current shunt feedback amplifier (Figure 9.21). Writing down the KCL equation at node C, Ai I i + I =

V Ro

(9.77)

With I s = 0 , I i = − I f = − bI o = bI

(9.78)

Substituting Eqn. (9.78) in Eqn. (9.77), Ai bI + I =

V Ro

I (1+ Ai b ) =

Rof =

V Ro

(9.79)

V = Ro (1 + Ai b ) I

(9.80)

Ro RL (1 + Ai b ) Ro RL (1 + Ai b ) Ro RL (1 + Ai b ) Ro + RL Rof RL Rof′ = Rof || RL = = = = A bR Rof + RL Ro (1 + Ai b ) + RL Ro + RL + Ai bRo 1+ i o Ro + RL

Rof′ = Ro′

Open Is

(1 + Ai b ) = R ′ (1 + Ai b ) (1 + AI b ) o D

Ii

(9.81)

I C

Io

If Is = 0

Ri

AiIi

Ro

+ V

−

Open RL Introduce V

Amplifier

b-network

Figure 9.21 Current sampling—current shunt feedback amplifier

448

9.7

Electronic Devices and Circuits

ASSUMPTIONS MADE IN THE ANALYSIS OF FEEDBACK AMPLIFIERS

The assumptions we make in the analysis of feedback amplifiers are the following: (i) The amplifier is a unilateral network. This means that if a signal is transmitted from the input to the output, it is transmitted only through the amplifier but not through the b -network (Figure 9.22).

Vs

+

+ −

+

−

Vi

+ Vo

A

RL

−

Vf

R1

+ Vo

R2 b-network

Figure 9.22 b -network can transmit the input to the output

But this assumption may be violated in some cases because in most of the cases, the b-network happens to be a simple resistive network, and it is possible that the input may be transmitted to the output through the b -network also, Figure 9.22. Cs

+ Vi

+ Vs

Q

A −

− Vf +

b Vo

+ Vo −

RL

b

Figure 9.23 Interelectrode capacitance Cs transmits the signal from the output to the input

(ii) The second assumption is that the b -network is a unilateral network. This means that if a signal is transmitted from the output to the input, it is transmitted only through the b -network but not through the amplifier. But this assumption may be violated in some cases because of the interelectrode capacitance Cs in a transistor (Figure 9.23). The stray capacitance between the output and the input Cs behaves as an open circuit at low frequencies. However, at high frequencies, the reactance of Cs becomes smaller and Cs may eventually behave as a short circuit at relatively higher frequencies. Thus, the output can be fed back to the input through the amplifier too. (iii) The third assumption is that b is independent of Rs and RL.

Feedback Amplifiers

449

Example 9.2 An amplifier has a gain of 100 and a normal input of 50 mV. If feedback with b = 0.1 is added, (i) find Af. (ii) What should be the input to get the same amount of output as without feedback? (iii) Calculate the amount of dB feedback used. Solution: Given A = 100, Vs = 50 mV and b = 0.1

Ab = 100 × 0.1 = 10

1 + Ab = 1 + 10 = 11 (i) Af =

A 100 = = 9.09 1 + Ab 11

Vo ′ = AV f s = 9.09 × 50 = 0.455 V

(ii) Vo = AVs = 100 × 50 = 5 V If the output with feedback is to be the same as that without feedback, the new input needed is Vs ′. Vs ′ = Vs (1 + Ab ) = 50 × 11 = 550 mV AV f s ′ = 9.09 × 550 = 5 V (iii) The amount of dB feedback used = 20 log10 (1 + Ab ) = 20 log10 11 = 20.83 dB.

9.8

REDUCING A FEEDBACK AMPLIFIER CIRCUIT INTO AN AMPLIFIER CIRCUIT WITHOUT FEEDBACK

Now that we have known all the prerequisites for the analysis of feedback amplifiers, let us discuss the procedure to analyze a given feedback amplifier. We, by now, know that Af = A/D , Rif is either Ri D or Ri /D and Rof = Ro (1 + Av b ) or Ro / (1+ Ai b ) , and so on. Hence, to calculate the performance quantities of the feedback amplifier, it is first required to calculate A, the gain of the amplifier without feedback and b , the feedback factor. To do this, it becomes necessary that the feedback amplifier is reduced to an amplifier without feedback. In an amplifier without feedback, there is no signal transmitted from the input to the output and vice versa through the feedback network. To achieve this objective, the following conditions need to be imposed on the feedback amplifier circuit. 1. Drawing the input loop of the amplifier without feedback To draw the input loop of the amplifier circuit without feedback, the signal transmitted from the output to the input through the b -network should be reduced to zero. This condition means that the output of the b-network should be made zero. Let the output of the b-network be a voltage Vf , which could be derived by either sampling the output voltage Vo or the output current I o. That is, Vf = bVo or Vf = bI o . For Vf to be zero if the sampled signal at the output is a voltage, Vo , then in the feedback amplifier circuit, set Vo = 0, that is short the output terminals (Figure 9.24).

450

Electronic Devices and Circuits

Vs

+

+ +

−

−

Vf = 0

Vi

Set Vo = 0 Short Vo

A

−

R1 Vo R2 b-network

Figure 9.24 Drawing the input loop of the amplifier without feedback when the sampled signal is a voltage

For Vf to be zero if the sampled signal at the output is a current, I o , then in the feedback amplifier circuit, set I o = 0 , that is open the output loop (Figure 9.25). +

+ Vi

Vs −

−

Io

GM

RL

+ Vf = 0 Set Io = 0 Open the output loop Vf = bIo

b

Figure 9.25 Drawing the input loop of the amplifier without feedback when the sampled signal is a current

2. Drawing the output loop of the amplifier without feedback To draw the output loop of the amplifier circuit without feedback, the signal transmitted from the input to the output through the b-network should be reduced to zero. This condition means that the output of the b-network should be made zero. Let the mixing at the input be series mixing. Then, to make the signal transmitted through the b -network to the output zero, make the current in the input loop zero, that is open the input loop. Hence, to draw the output loop of the amplifier without feedback, set I i = 0 (Figure 9.26).

Vs

+

Open the input loop Set Ii = 0 Ii + Vi

−

Ri

A

RL

−

R1 Vo R2

b-network

Figure 9.26 Drawing the output loop of the amplifier without feedback when series mixing is used at the input

Feedback Amplifiers

451

Now let the mixing at the input be shunt mixing. Then to make the signal transmitted through the b-network to the output zero, make the voltage between the input nodes zero, that is short the input nodes. Hence to draw the output loop of the amplifier without feedback, set Vi = 0 (Figure 9.27). + Vs −

+ Set Vi = 0 Short input Vi Ri nodes

RM

RL

b

Figure 9.27 Drawing the output loop of the amplifier without feedback when shunt mixing is used at the input

9.9

METHOD OF ANALYSIS OF FEEDBACK AMPLIFIERS

A simple, systematic, and straightforward procedure to analyze a feedback amplifier is presented below: Step 1: Let X o be the sampled signal and X f be the feedback signal. Identify whether X o is a voltage or current and whether the feedback signal, X f is a voltage or current. If X o is a current and if X f is a voltage, then the topology under consideration is voltage series feedback amplifier topology. Alternately, if X o is a voltage and if X f is a current, then the topology under consideration is voltage shunt feedback amplifier topology, and so on. Step 2: Reduce the feedback amplifier circuit into an amplifier circuit without feedback. For this, we impose the following conditions on the feedback amplifier circuit. (i) To draw the input loop, set Vo = 0, if the sampled signal is a voltage and I o = 0 if the sampled signal is a current. (ii) To draw the output loop, set Vi = 0 if shunt mixing is used and I i = 0 if series mixing is used. Now, the amplifier circuit without feedback is drawn, by using the above conditions. Step 3: Replace the transistor by its low-frequency, small-signal approximate model. Step 4: Calculate A and b . (i) If X o is a voltage and X f is a voltage (voltage series feedback amplifier), then X V X o Vo = and b = f = f . X o Vo X i Vi

A = AV =

(ii) If X o is a voltage and X f is a current (voltage shunt feedback amplifier), then A = RM =

X o Vo X I = and b = f = f . Xi Ii X o Vo

(iii) If X o is a current and X f is a current (current shunt feedback amplifier), then A = AI =

X o Io X I = and b = f = f . Xi Ii X o Io

452

Electronic Devices and Circuits

(iv) If X o is a current and X f is a voltage (current series feedback amplifier), then A = GM =

X o Io X V = and b = f = f . X o Io X i Vi

Step 5: Having calculated A and b , calculate D. D = 1 + AV b for voltage series feedback amplifier D = 1 + RM b for voltage shunt feedback amplifier D = 1 + AI b for current shunt feedback amplifier D = 1 + GM b for current series feedback amplifier Step 6: Now calculate Af . AV for voltage series feedback amplifier D R Af = RMf = M for voltage shunt feedback amplifier D AI Af = AIf = for current shunt feedback amplifier D G Af = GMf = M for current series feedback amplifier D

Af = AVf =

Step 7: Calculate AVf for the last three topologies since all said and done these are voltage amplifiers. R Step 8: Calculate Rif as Rif = i for shunt mixing and Rif = Ri D for series mixing. D Step 8: Calculate Rof Rof =

Ro for voltage series feedback amplifier 1 + Av b

Rof =

Ro for voltage shunt feedback amplifier 1 + Rm b

Rof = Ro (1 + Gm b ) for current series feedback amplifier Rof = Ro (1 + Ai b ) for current shunt feedback amplifier Step 9: Calculate Rof′ Rof′ =

Ro′ for voltage series feedback amplifier and voltage shunt feedback amplifier D Rof′ = Rof′ =

Ro′ (1 + Ai b ) D Ro′ (1 + Gm b ) D

for current shunt feedback amplifier for current series feedback amplifier

Feedback Amplifiers

453

By following the procedure step by step, we can arrive at the performance quantities of the feedback amplifier. Although the procedure seems complicated, in practice it turns out to be very simple. This fact can be seen when we consider practical amplifiers later. But care must be taken to identify the topology properly, to apply the rules.

9.10

ANALYSIS OF VOLTAGE SERIES FEEDBACK AMPLIFIER

Consider the circuit in Figure 9.28 and its ac circuit in Figure 9.29. VCC RL Io Rs

Rs

Io

+

+ Io

+

+

Vs

+

Vs Vf

−

−

Vo Vf

−

Vo

RE

RL

+

−

−

RE −

Figure 9.29 AC circuit of Figure 9.28

Figure 9.28 Voltage series feedback amplifier

Step 1: The first requirement in the analysis of the amplifier is to identify the topology properly. From Figure 9.29, it can be noted that the type of mixing used at the input is series mixing. The voltage drop across RE is the feedback signal Vf , which is in series with the input signal Vs . Is this feedback signal derived by sampling the output voltage, or is it derived by sampling the output current? To answer this, let us put a test on the circuit. We know that if the sampled signal is a voltage, then Vf = bVo and if the sampled signal is a current, then Vf = bI o. This means that if we set Vo = 0 and then if Vf = 0 , then the type of sampling used is voltage sampling. Alternately, if we set I o = 0 and then if Vf = 0, then the type of sampling employed is current sampling. Set I o = 0 (Figure 9.30), then Vf ≠ 0, as there is an open circuit voltage. Alternately, set Vo = 0 (Figure 9.31), then Vf = 0. Hence, it can be concluded that the sampled signal is a voltage. Hence, the topology of the amplifier in circuit in Figure 9.28 is a voltage series feedback amplifier. Io

+

+ Vs

−

Io

Io = 0

Rs

+

RL

Rs

−

RE −

Figure 9.30 Circuit when I o = 0

+ + Vs

Vo Vf

RL

+ −

Vf

Vo = 0

− −

Figure 9.31 Circuit when Vo = 0

454

Electronic Devices and Circuits

Step 2: To draw the input loop of the amplifier without feedback, set Vo = 0, since the sampled signal is a voltage. Imposing this condition on the circuit in Figure 9.29, we draw the input loop as in Figure 9.32. Io

Open loop Ii = 0

Rs

RS

+

+

+ + Vs

RC

+

+ Vs

Vf

−

Vo = 0

−

− −

Vo

Vf RE

−

Figure 9.32 To draw the input loop, set Vo = 0

−

Figure 9.33 To draw the output loop, set I i = 0

To draw the output loop, set I i = 0 (Figure 9.33). Then, there is no contribution of the signal in RE due to I i , and hence RE can be considered totally as part of the output circuit only, Figure 9.34. Combining the circuits in Figures 9.32 and 9.34, we can draw the amplifier circuit without feedback as in Figure 9.35.

RC

−

−

Vs

Vo

RE

−

Vf

+

−

+ Io

RE

RC

Rs

Vo Io

Vf +

+

Figure 9.34 Output loop when I i = 0

−

+

Figure 9.35 Amplifier circuit without feedback

Step 3: In Figure 9.35, replace the device by its low-frequency, small-signal approximate model as in Figure 9.36. Ib = Ii Rs + Vs

+ Vi

RC hie

hfeIb

−

− Io

Figure 9.36 Equivalent circuit of Figure 9.35

Vf

− RE Vo

+

+

Feedback Amplifiers

455

Step 4: Calculate A and b . From Figure 9.36, b=

Vf =1 Vo

(9.82)

since Vf and Vo are the voltages across the same resistance RE with the same polarity. AV =

Vo Vo = since Vi = Vs, if Rs is considered as part of the amplifier circuit. Vi Vs hfe I b RE hfe RE AV = = (Rs + hie ) I b (Rs + hie )

(9.83)

Step 5: Using Eqs (9.82) and (9.83), calculate D. D = 1 + AV b = 1 +

hfe RE R + hie + hfe RE ×1 = s (Rs + hie ) (Rs + hie )

(9.84)

Step 6: Calculate AVf . Using Eqs (9.83) and (9.84),

(Rs + hie ) = AV hfe RE hfe RE = D ( Rs + hie ) Rs + hie + hfe RE Rs + hie + hfe RE

AV = f

(9.85)

If hfe RE >> (Rs + hie ) , then AVf ≈ 1. Step 7: We calculated AV because this is a voltage series feedback amplifier. f

Step 8: Rif = RI D From Figure 9.36 and using Eq. 9.84 (Rs + hie ) I b = R + h V Ri = s = ( s ie ) Ib Ib Rif = Ri D = ( Rs + hie )

(9.86)

Rs + hie + hfe RE = Rs + hie + hfe RE (Rs + hie )

(9.87)

Ro where Ro is the output resistance without feedback (Figure 9.37). Open the 1 + Av b load RE and look into the output terminals, then the resistance that is seen is Ro. hfe I b is an ideal current source with its internal resistance ∞. Hence, Ro is ∞. Step 9: Rof =

Rs + + Vs

Vi

RC hie

hfeIb

−

Ro

Figure 9.37 Circuit to find Ro

456

Electronic Devices and Circuits

Av =

hfe RE hfe Lim Lim Lim AV = = =∞ RE → ∞ RE → ∞ (Rs + hie ) RE → ∞ (Rs + hie ) RE

Ro ∞ = , which is an indeterminate quantity. Hence, Rof is not calculated using (1 + Av b ) ∞ Eqn. (9.65). To calculate Rof , we first calculate Rof′ using the expression obtained earlier, and then R′ let RE → ∞ in this. Using Eqn. (9.66), Rof′ = o where Ro′ = Ro || RE = RE since Ro = ∞. D Rof =

Rof′ =

Rof =

=

RE (Rs + hie ) RE = Rs + hie + hfe RE Rs + hie + hfe RE Rs + hie

(9.88)

RE (Rs + hie ) Lim Lim Rof′ = RE → ∞ RE → ∞ Rs + hie + hfe RE

(Rs + hie )

Lim RE → ∞

 R + hie  hfe +  s  RE 

=

(Rs + hie )

(9.89)

hfe

Example 9.3 For the circuit in Figure 9.28, RE = 2 kΩ, Rs = RC = 1 kΩ, hie = 1 kΩ, and hfe = 50. Calculate AV, b, D, AVf , Rif, and Rof. Solution: Using Eqs (9.82) and (9.83), b=

Vf hfe RE 50 ´ 2 = 1 and AV = = = 50 Vo ( Rs + hie ) 1 + 1 D = 1 + AV b = 1 + 50 (1) = 51

AV = f

AV 50 = = 0.98 D 51

Rif = Ri D and Ri = Rs + hie = 1 + 1 = 2 kΩ

Rof =

∴ Rif = 2 × 51 = 102 kΩ

(Rs + hie ) = 1 + 1 hfe

50

= 40 Ω

The voltage series feedback amplifier is nothing but an emitter follower.

Feedback Amplifiers

9.11

457

ANALYSIS OF CURRENT SERIES FEEDBACK AMPLIFIER

Consider the circuit in Figure 9.38 and its ac circuit in Figure 9.39. VCC RC Io Rs

Rs

+

+ RC

+

Io

+ Vs

Io Vf

−

RE −

+ Vs

Vo

Vf

−

Vo

+

−

−

Figure 9.38 Current series feedback amplifier

−

RE

Figure 9.39 AC circuit of Figure 9.38

Step 1: Let us identify the topology properly. From Figure 9.38, it can be noted that the type of mixing used at the input is series mixing. The voltage drop across RE is the feedback signal Vf , which is in series with the input signal Vs . To find out the type of sampling used, set Vo = 0 (Figure 9.40). As I o ≠ 0, Vf ≠ 0. Alternately, set I o = 0 (Figure 9.41), then, Vf = 0. Hence, it can be concluded that the sampled signal is a current. Hence, the topology of the amplifier in Figure 9.38 is a current series feedback amplifier.

Io = 0 Io Rs

Rs

+

+ Vo = 0

+ Vs

−

Vf

RC Vo

+

+

RE

−

Figure 9.40 Circuit when Vo = 0

+

Vs

− −

Vf

Io

−

RE −

Figure 9.41 Circuit when I o = 0

Step 2: To draw the input loop of the amplifier without feedback, since the sampled signal is a current, set I o = 0. In Figure 9.39, when I o = 0, there is no contribution of the signal in RE , and hence RE can be considered totally as part of the input loop only as shown in Figure 9.42.

458

Electronic Devices and Circuits Io = 0 Rs

Io

Open loop Ii = 0

+

Rs

+ Vs

RC

Vo

+ −

Vs

+ −

RE

− Vf − RE

Figure 9.42 Input loop with I o = 0

Figure 9.43 Output loop with I i = 0

To draw the output loop, set I i = 0 (Figure 9.43). Then there is no contribution of the signal in RE due to I i , and hence RE can be considered totally as part of the output circuit only (Figure 9.44). Combining the circuits in Figures 9.42 and 9.44, the amplifier circuit can be drawn without feedback as shown in Figure 9.45.

+

Ii = 0

Rs

+ Io

RC Vo

+

RCVo

−

Vs

− + Vf

−Io

−

+ Vf −

−

RE

RE

Figure 9.44 Output loop with I i = 0

RE

Figure 9.45 Amplifier circuit without feedback

Step 3: In Figure 9.45, replace the device by its low-frequency, small-signal approximate model as in Figure 9.46. Ib Rs +

Vi

Vs −

Io

+

RC

Vo

+ hie

hfeIb

− RE

−Io

RE

+

Vf

Figure 9.46 Equivalent circuit

− −

Feedback Amplifiers

459

Step 4: Calculate A and b . From Figure 9.46, b=

since Vf = − I o RE . GM =

Vf −I o RE = = −RE Io Io

(9.90)

Io Io = since Vi = Vs , if Rs is considered as part of the amplifier circuit. Vi Vs GM =

− hfe I b − hfe = + + + R R h I R ( s E ie ) b ( s RE + hie )

(9.91)

Step 5: Using Eqs (9.90) and (9.91), calculate D.   Rs + hie + (1 + hfe ) RE − hfe −RE ) = D = 1 + GM b = 1 +  (  Rs + RE + hie  (Rs + RE + hie ) 

(9.92)

Step 6: Calculate GMf . Using Eqs (9.91) and (9.92), GMf =

− hfe − hfe Rs + RE + hie GM = × = D (Rs + RE + hie ) Rs + hie + (1 + hfe ) RE Rs + hie + (1 + hfe ) RE

(9.93)

Io − hfeVs or I o = GMfVs = Vs Rs + hie + (1 + hfe ) RE

(9.94)

GMf =

If (Rs + hie ) w o . Equating the real terms: −R +

hfe M hoe L = C hie C

(10.27)

Or hfe M RC + hoe L = hie C C hfe RC + hoe L ≥ hie M

(10.28)

Equation (10.28) is the amplitude condition to be satisfied in the circuit for the oscillations to build up and sustain.

506

Electronic Devices and Circuits

Example 10.3 A tuned collector oscillator has L = 100 µH and C = 1000 pF. (i) Calculate its frequency. (ii) If, hoe = 25 × 10−6 and the resistance associated with the inductance R is 1 kΩ, calculate the exact frequency of oscillations. (iii) If M = 5 µH, find the minimum value of hfe for the oscillations to build up, if hie = 1 kΩ. Solution: The approximate frequency is ( i) f =

1

1

=

2p LC

−6

2p 100 × 10 × 1000 × 10 −12

= 503.91 kHz

(ii) The exact of frequency is given as follows: 2 w exact =t w 2 (1 +(1hoe Roe) )e fexact = f 1 (1 + hoe R )

1 + hoeR = 1 + 25 × 10−6 × 1 × 103 = 1.025 (1+ hoe R ) = 1.012

( iii )

hfe RC + hoe L ≥ hie M hfe ( min ) =

10.7

fexact = f (1 + hoe R ) = 503.91 × 1.012 = 509.95 kHz

hie (RC + hoe L ) M

(

1 × 103 1 × 103 × 1000 × 10 −12 + 25 × 10 −6 × 100 × 10 −6 =

5 × 10

−6

) = 200.5

RC OSCILLATORS

At audio frequencies, the value of the inductance is large and can be in the order of Henries. Therefore, the inductance is wound on an iron core and thus becomes bulky and occupies more space. Hence, we go in for RC oscillators. We basically consider two types of audio oscillators, namely, RC phase-shift oscillator and Wien bridge oscillator. In all the feedback oscillators, as the amplifier produces a phase shift of 180°, the b-network is required to produce the additional phase shift of 180°. A single RC network can produce a maximum phase shift of 90° under ideal conditions. Hence, there arises the need to cascade more than two such stages to obtain a phase shift of 180° because attaining an ideal case is not possible. But there cannot be scope for changing the frequency. So sometimes it becomes necessary to cascade three RC networks to produce the required phase shift of 180°. The RC phase shift oscillator is mostly used to obtain a fixed frequency output. Alternatively, a two-stage amplifier that gives a phase shift of 360° is used, and the RC b -network is so chosen that it produces a phase shift of 0° at a desired frequency. The procedure followed in the analysis of these oscillators is that we calculate the gain of the amplifier and also calculate the gain using the b -network and equate these two gains. Equating the imaginary and real terms, the frequency and the condition for oscillations to build up and sustain are obtained.

Oscillators

507

10.8 WIEN BRIDGE OSCILLATOR The Wien bridge oscillator is so called because the circuit is based on a frequency-selective form of the Whetstone bridge circuit. The Wien bridge oscillator is a two-stage RC -coupled amplifier circuit that has good stability at its resonant frequency. This oscillator uses a feedback circuit consisting of a series RC circuit connected with a parallel RC of the same component values producing the necessary phase shift. At the resonant frequency, the phase shift is 0°. The Wien’s network, shown in Figure 10.17 , consists of a series RC circuit connected to a parallel RC . At low frequencies, the reactance of the series capacitor C is very high, and hence the series RC circuit acts as a high-pass filter. At high frequencies, the reactance of the shunt capacitor C is very low, and hence the parallel RC circuit acts as a low-pass filter. Thus, these cascaded filters produce a very selective second-order frequency dependent band-pass filter with a high Q factor at the desired frequency. However, between these two extremes, the output voltage reaches a maximum value at a frequency called the resonant frequency. High-pass filter Low-pass filter

R

C

C Output

Input R

Figure 10.17 Wien’s network

A Wien bridge oscillator is one in which a two-stage RC -coupled amplifier is used and the output is fed back to the input through the b -network as shown in Figure 10.18.

VDD C RD

R

RD

CC

CC Q2

Q1 R

C

b-Network

Two-stage amplifier

Figure 10.18 Wien bridge oscillator

Output

508

Electronic Devices and Circuits

− mRD and the overall gain is the product of the individual gains. rd + RD And this gain is a real gain. Now, we calculate the gain using b -network (Figure 10.19). The gain of each stage is A =

Vds is the output of the amplifier and Vgs is the input. The ratio of Vds to Vgs is the gain A.      Vgs = Vds     R+   

 R×   R+ 

1  jwC  1  jwC 

 R×  1  +  jwC   R+ 

      1  jwC    1  jwC  

R Vds + Vgs C

   R+    V A = ds =  Vgs     

 R×  1  + jwC   R+   R×   R+ 

1  jwC  1  jwC 

+

C

1  jwC    1  jwC        

R − −

Figure 10.19 b -network

2

A=

  2 1   j wC  1 2 R   j wC  Vds = 1+  R +    = 1 +  R − 2 2 +   Vgs  j wC  R  jwC   R  wC

A = 1 + jwRC +

1 1 + 2 = 3 + jwRC + jwRC jwRC

(10.29)

Equating the imaginary parts in Eqn. (10.29), 1 =0 jwRC

jwRC +

w=

f =

(10.30)

1 RC

1 2pRC

(10.31)

Oscillators

509

Equating real terms, (10.32)

A=3

The gain of the amplifier should be adjusted to 3. If the gain is more than 3, then there is distortion in the amplitude.

10.9

RC PHASE SHIFT OSCILLATOR USING FET

We know that a class-A common-emitter amplifier produces a phase shift of 180°. To produce an additional phase shift of 180° so as to derive an in-phase signal at the input of the amplifier, an RC network may also be used. Single-stage and three-stage RC networks are shown in Figure 10.20. C Input

Output R 0°

60°

60°

0°

0°

C

C

C Output

Input 0° R

0°

60°

R

R

180°

180°

120°

Figure 10.20 Single-stage and three-stage RC networks −1  X C  Z = R + jX C and the phase angle q = tan   R 

An RC phase-shift oscillator using an FET is shown in Figure 10.21. VDD RD

Output

C

+

C

C

+ Vgs

Vds

−

R

R

R CS

RS

−

Figure 10.21 RC phase-shift oscillator using a JFET

510

Electronic Devices and Circuits

− mRD , which is a real gain. Once again, we calculate rd + RD A using the b -network comprising three RC phase-shifting networks as shown in Figure 10.22.

Here also the gain of the amplifier is A =

I2 + I3 I1 + I2 + I3

I3 C

+

C

R

Vds I1

+

C

R

I2

R

Vgs

I3

−

−

Figure 10.22 b -network

From Figure 10.22, Vgs = I 3 R

(10.33)

 1  I 2 R = I3  R +  jwC  Or  1  I 2 = I 3 1 +  jwRC 

(10.34)

  1  1  I1 R = I 2  R + + I3   jwC   jwC  Or   1  1  I1 = I 2  1 + + I3   jwRC   jwRC  Substituting for I 2 from Eqn. (10.34),     1  3 1 1  1  I1 = I 3  1 + 1+ + I3  = I 3 1 + − 2 2 2       jwRC   jwRC   jwRC  jwRC w R C    1   1  1  Vds = I1  R + + I2  + I3   jwC   jwC   jwC 

(10.35)

511

Oscillators

 1     3 1 1  1  1  + I3  Vds = I 3 1 + − 2 2 2  R + + I 3 1 +     jwRC w R C   j wC  jwRC   jwC C  jwC     3 1 1 3 1 1 1 1  Vds = I 3  R + − 2 + − 2 − 3 2 3+ − 2 + 2 2 2 jwC  jwC w RC jwC w RC jwC w RC  jw R C   6 5 1 Vds = I 3 R 1 + − 2 2 2 − 3 3 3 jwRC w R C  jw R C  Using Eqn (10.33)   6 5 1 Vds = Vgs 1 + − 2 2 2 − 3 3 3 jwRC w R C  jw R C  A=

Vds 6 5 1 = 1+ − − Vgs jwRC w 2 R 2C 2 jw 3 R3C 3

(10.36)

Equating the imaginary terms in Eqn. (10.36), 6 1 1 − 3 3 3 = 0 or w 2 = wRC w R C 6R 2C 2

(10.37)

Equating the real terms in Eqn. (10.36), A = 1−

5 w R 2C 2 2

Substituting for w 2 from Eqn. (10.37), A = 1−

5 = −29  1  2 2  2 2  R C 6R C

(10.38)

From Eqs (10.38) and (10.37), it is evident that for oscillations to build up and sustain, the gain of the amplifier must be greater than that or equal to 29; and if this condition is satisfied, then the 1 oscillator oscillates at w = . 6RC 1 f = (10.39) 2p 6RC

10.10

RC PHASE-SHIFT OSCILLATOR USING A BJT

RC phase-shift oscillators using a BJT are shown in Figure 10.23. In the circuit in Figure 10.23(a), three identical high-pass RC circuits are connected in cascade. However, a CE amplifier has a small input resistance hie ≈ 1 kΩ; R and C decide the frequency of oscillations. Let R be chosen as 10 kΩ to derive a desired frequency. The R in the third phase-shifting network will appear in parallel with hie as such the effective resistance of the parallel combination is approximately hie. To ensure that the value of this resistance remains as R only, (R − hie) is connected in series with the

512

Electronic Devices and Circuits

base terminal as shown in the modified circuit in Figure 10.23(b). An alternate form of RC phaseshift oscillator using low pass circuits as phase-shifting networks is shown in Figure 10.23(c). VCC

RC

60°

120°

180°

0° C

C

C Output

R

R

R CE

1

RE

3

2

Three identical RC high pas circuits

Figure 10.23(a) RC phase shift oscillator using a BJT VCC

RC

60°

R − hie

120°

180°

0° C

R

C

C

R CE

RE

Figure 10.23(b) Modified circuit of Figure 10.23(a)

The equivalent circuit of Figure 10.23(b) is shown in Figure 10.24. The current source hfe I b with its internal resistance is replaced by a voltage source hfe I b RC with internal resistance RC (Figure 10.25). In order to get the frequency and the condition for the oscillations to build up and sustain, we write down the KVL equations of the three loops and write down the determinant.

Oscillators

513

VCC

CC

R

R

C

RC

R

C

C RE

CE

(c) Alternate circuit of RC phase shift oscillator

Figure 10.23(c) RC phase-shift oscillators using a BJT

As the individual currents I1 , I 2 , and I b are not zero, the determinant is zero. Equating real and imaginary terms, we get the frequency and the condition for the oscillations to build up and sustain.

C

RC

hfeIb

C

R

C

R − hie

hie

R

Figure 10.24 Equivalent circuit of Figure 10.23(b)

RC

C

C

C

R − hie − R

hfeIbRC +

I1

R I2

Ib

hie

Figure 10.25 Circuit of Figure 10.24 with current source replaced by voltage source

514

Electronic Devices and Circuits

From Figure 10.25, writing the KVL equations,

(R + RC − jX C ) I1 − RI 2 + hfe RC I b = 0

(10.40)

−RI1 + (2R − jX C ) I 2 − RI b = 0

(10.41)

−RI 2 + (2R − jX C ) I b = 0

(10.42)

As I1, I 2 , and I b are nonzero currents, the determinant of the coefficients of I1, I 2 , and I b is zero: R + RC − jX C −R 0

−R 2R − jX C −R

hfe RC −R =0 2R − jX C

(R + RC − jX C ) (2R − jX C ) (2R − jX C ) − ( −R ) ( −R ) + R  −R (2R − jX C + hfe RRC ) = 0 R3 + R 2 RC (3 + hfe ) − 5RX C2 − RC X C2 − j 6R 2 X C − j 4RRC X C + jX C3 = 0

(10.43)

Equating imaginary terms in Eqn. (10.43), 6R 2 X C + 4RRC X C − X C3 = 0 or X C2 = 6R 2 + 4RRC

(10.44)

Or 4R   X C2 = R 2  6 + C  = R 2 (6 + 4 k )  R  where k =

RC R X C = R 6 + 4k

Or 1 = R 6 + 4k wC 1 w=

RC 6 + 4 k

(10.45)

Oscillators

f =

515

1 (10.46)

2pRC 6 + 4 k

Equating real terms in Eqn. (10.43), R3 + R 2 RC (3 + hfe ) − (5R + RC ) X C2 = 0

(10.47)

Substituting Eqn. (10.44) in Eqn. (10.47)

(

)

R3 + R 2 RC (3 + hfe ) − (5R + RC ) 6R 2 + 4RRC = 0 When simplified, hfe = 23 + 4 k +

29 k

(10.48)

29   Equation (10.48) implies that for oscillations to build up, hfe >  23 + 4 k +  and after the oscil k lations reach the sustained condition. hfe = 23 + 4 k +

29 k

If k = 1, then hfe ≥ 56. Analysis of the circuit shown in Figure 10.23(c) can be carried out on similar lines. Example 10.4 In an RC phase-shift oscillator using BJT, the feedback network uses R = 6 kΩ and C = 1.5 nF. The transistor amplifier uses RC = 18 kΩ. Calculate the frequency of oscillations and hFE(min). Solution: RC = 18 kΩ and R = 6 kΩ. k=

f =

RC 18 = =3 6 R 1

1

2pRC 6 + 4 k

hFE (min) = 4 k + 23 +

=

3

2p × 6 × 10 × 1.5 × 10 −9 6 + 4 × 3

29 29 = 4 × 3 + 23 + = 44.67 k 3

= 4.17 kHz

516

10.11

Electronic Devices and Circuits

AMPLITUDE STABILITY IN OSCILLATORS

A low-distortion oscillator requires effective amplitude stabilization. The amplitude of electronic oscillators tends to increase until clipping or limitation of the gain by some other form is reached. This leads to high harmonic distortion, which is undesirable. A resistance RE can be used in the emitter lead to ground to stabilize the gain of the amplifier, and thus derive amplitude stability of the oscillations. But this can result in reduction in the gain of the amplifier. As a result, oscillations may not build up at all. An incandescent bulb as a positive temperature coefficient (PTC) thermistor can be used in the oscillator feedback path to limit the gain. The resistance of light bulbs and similar heating elements increases as their temperature increases. Thus initially, when the oscillations build up, the light bulb offers small resistance. But, as the amplitude increases further, as its resistance increases, provides negative feedback and thus stabilizes the gain. But a light bulb can be bulky. Therefore, oscillators can use other nonlinear elements, such as diodes, thermistors, field effect transistors, or photocells for amplitude stabilization in place of light bulbs as indicated in Figure 10.26.

VDD C R

C

b-network

R

RD

RD

Q1 C C

Q2 CC

T1

T2

Thermistors

Two-stage amplifier

Figure 10.26 Amplitude stabilization with thermistors

10.12

FREQUENCY STABILITY IN OSCILLATORS

The main limitation of both LC and RC oscillators is their poor frequency stability. Consider a radio station transmitting at a frequency of 1 MHz. To receive the signal corresponding to this station, radio receiver must be tuned to this frequency. Unfortunately, the frequency of the oscillator used for generating this 1 MHz signal keeps changing from time to time. The change in frequency is due to various reasons, mainly because of variations of device parameters and components values used in the tank circuit due to temperature variations, as the transmitted power is large. Every time this frequency changes, the radio receiver must be retuned, and this is obviously disgusting. Hence, it becomes imperative that the frequency of the oscillator should remain unaltered. One method used, usually, is to provide a constant temperature chamber. Second, the instability in frequency is due to small value of Qs in LC and RC oscillators. Incidentally, Q

Oscillators

517

is the figure of merit of a tuned circuit. Typically, it can be expressed as Q = wL /R = 1/wRC . The larger the value of Q , the sharper the response characteristic of the tuned circuit, and hence its ability to reject the unwanted frequencies and select only the desired frequency, because in all the oscillators we require that only one frequency component be fed back from the output through the b-network. The Qs that are normally encountered in LC oscillators are typically of the order of 200, and consequently the response is not necessarily sharp. On the contrary, when Q is 10,000, then response of the tuned circuit is very sharp as shown in Figure 10.27. Crystal oscillators have large Qs of the order of 50,000 and more. Crystal oscillators are chosen for generating stable frequencies. Q large Response

Q relatively small

0

fo

f

Figure 10.27 Response of the tank circuit as a function of Q

10.13

CRYSTAL OSCILLATORS

We know that certain materials available in nature, such as Rochelle salt, Quartz, and Tourmaline, exhibit piezoelectric property. If pressure is applied across the opposite faces of the crystal, it generates a voltage. Alternatively, if an oscillating signal is applied to the crystal, the crystal vibrates. This property is called the piezoelectric property. Of the three materials, Rochelle salt has the best piezoelectric property, but it is the weakest of all. Hence, when a thin slab of the crystal is used and if it vibrates, it may break. On the contrary, Tourmaline has the least piezoelectric property, but it is the strongest of all. Quartz has strength better than Rochelle salt and better piezoelectric property compared to Tourmaline. Further, it is abundantly available in nature. Hence, Quartz crystals are used for majority of the applications. The Quartz crystal is in the shape of a hexagonal prism with pyramids at the top as indicated in Figure 10.28. A thin slab of this crystal is cut along XX-axis, YY-axis, XY-axis, and so on, and it is held between a pair of electrodes as shown in Figure 10.29. The electrical equivalent of the crystal is shown in Figure 10.30. From the equivalent circuit of the crystal, it is evident that a crystal has two resonant frequencies: (i) a series resonant-frequency and (ii) a parallel resonant-frequency. The series resonant-frequency fs is given as follows:

fs =

1 2p LSCS

518

Electronic Devices and Circuits

A

CS A

CM

LS

t RS B

B

Figure 10.28 A quartz crystal

Figure 10.29 A thin slab mounted between electrodes

Figure 10.30 Electrical equivalent of the crystal

and the parallel resonant-frequency is given as follows: fp =

1 2p LSCeq

where Ceq =

CMCS CM + CS

CM is called the mounting capacitance. Figure 10.31 shows the variations of impedance of the crystal with respect to frequency f . Between fs and fp, it can be noted that the impedance of the crystal varies linearly with frequency as in an inductance. Hence the inductance can be replaced by a crystal.

Impedance

0

fs

fp

Figure 10.31 The two resonant frequencies of the crystal

f

Oscillators

519

A crystal oscillator is shown in Figure 10.32. This circuit is a mere modification of a Colpitts oscillator in which the inductance is replaced by a crystal. The frequency of the crystal is inversely proportional to the thickness of the slab. That is, f = k t, where k the constant of proportionality that depends on the orientation in which the thin slab of the crystal is cut. Therefore, as there is a minimum thickness for the crystal slab, and hence there is a maximum frequency up to which the crystal can be used.

C2

A Crystal B

C1

Figure 10.32 Crystal oscillator

Example 10.5 For the crystal, L = 0.1 H, C = 0.01 pF, RS = 10 kΩ, and CM = 1 pF. Find the resonant frequencies and the Q factor. Solution: (i)

fs =

1 2p LC

(ii) Ceq = fp =

(iii) Q =

10.14

1

= 5.035 MHz

= 2p 0.1 × 0.01 × 10 −12

CCM 0.01 × 1 = 0.0099 pF . = C + CM 0.01 + 1 1 2p LCeq

=

1 2p 0.1 × 0.0099 × 10 −12

= 5.06 MHz

wLs 2p × 5.035 × 106 × 0.1 = = 316.2 RS 10 × 103

BEAT FREQUENCY OSCILLATOR

It can be noted that by using crystal oscillators, it is possible to generate stable radio frequency oscillations. But at audio frequencies as we use RC oscillators, their frequency stability cannot be assured. Hence, to generate stable audio frequency oscillations, we can use crystal oscillators. Such an oscillator is called beat frequency oscillator and is indicated in Figure 10.33.

520

Electronic Devices and Circuits Fixed frequency crystal oscillator 500 kHz f1

f1 − f2 Mixer

RF filter

f2

0−20 kHz

Audio amplifier

Output

480−500 kHz Variable frequency crystal oscillator

Figure 10.33 Beat frequency oscillator

Here, we have two crystal oscillators: one is a fixed frequency oscillator ( f1 = 500 kHz) and the other is a variable frequency oscillator ( f2 varies from 480 to 500 kHz). These two signals are inputs to a mixer. At the output of the mixer, there are many sum frequencies and difference frequencies, ( mf1 ± nf2 ), where m and n are integers. The output of the mixer has a tuned circuit tuned to ( f1 − f2 ) , and hence the output of the mixer consists of audio frequencies (0–20 kHz). To eliminate radio frequency components of ripple, an RF filter is used. The output audio components are amplified by an audio amplifier.

10.15

EXACT ANALYSIS OF COLPITTS AND HARTLEY OSCILLATORS

The ac circuit of Figure 10.6 with the transistor replaced by its equivalent circuit is shown in Figure 10.34 . Here, hoe is not neglected. hoe is an admittance and Z2 is an impedance. Hence the effective admittance is I2

I1

 1  1 + hoe Z2  hoe + = Z2  Z2 

+ hie

hfeI1

hoe

V2

Z2

−

Hence hoe || Z2 can be replaced by an

Z3

admittance, (1 + hoe Z2 ) Z2 . Further, when hie is pulled down, hie and Z1 are in paral-

Z1

lel and the current I1 in Z1 flows upwards, Figure 10.35. From Figure 10.35, Figure 10.34 Equivalent circuit of Figure 10.6 considering hoealso

I1 = − I 2

I −Z1 Z1 or 1 = b = Z1 + hie I2 Z1 + hie

(10.49)

Oscillators

C

521

I2

+ V2

hfeI1

(1 + hoeZ2) Z2

− I2

hie

Z3

I1

Z1

− I2 I2

Figure 10.35 Simplified circuit of Figure 10.34

Writing the KVL equation of the outer loop  h Z  V2 +  ie 1  I 2 + I 2 Z3 = 0  hie + Z1 

(10.50)

Writing the KCL equation at node C I 2 = hfe I1 +

1 + hoe Z2 V2 Z2

(10.51)

Or  Z2  V2 = ( I 2 − hfe I1 )    1 + hoe Z2 

(10.52)

Substituting Eqn. (10.52) in Eqn. (10.50), 

Z2   hie Z1  +  I 2 + I 2 Z3 = 0  1 + hoe Z2   hie + Z1 

( I 2 − hfe I1 ) 

  Z2   Z2 h Z I2  + ie 1 + Z3  = hfe I1    1 + hoe Z2 hie + Z1   1 + hoe Z2   Z ( h + Z1 ) + hie Z1 (1 + hoe Z2 ) + Z3 ( hie + Z1 ) (1 + hoe Z2 )  I 2  2 ie  = hfe I1Z2  ( hie + Z1 )   A=

 hfe Z2 ( hie + Z1 ) I2  = I1  Z2 ( hie + Z1 ) + hie Z1 (1 + hoe Z2 ) + Z3 ( hie + Z1 ) (1 + hoe Z2 ) 

(10.53)

522

Electronic Devices and Circuits

From Eqs (10.52) and (10.53),   −Z1   hfe Z2 ( hie + Z1 ) Ab =     Z2 ( hie + Z1 ) + hie Z1 (1 + hoe Z2 ) + Z3 ( hie + Z1 ) (1 + hoe Z2 )   Z1 + hie    −hfe Z1Z2 Ab =  = −1  Z ( h + Z ) + h Z (1 + h Z ) + Z ( h + Z ) (1 + h Z )  1 ie 1 oe 2 3 oe 2  ie 1  2 ie hfe Z1Z2 = Z2 ( hie + Z1 ) + hie Z1 (1 + hoe Z2 ) + Z3 ( hie + Z1 ) (1 + hoe Z2 ) hfe Z1Z2 = Z1Z2 + Z1Z3 + hie ( Z1 + Z2 + Z3 ) + hie hoe ( Z1Z2 + Z2 Z3 ) + hoe Z1Z2 Z3

(10.54)

We can recognize that Eqn. (10.54) is the Barkhausen criterion. In order to find out the frequency of oscillations, we substitute specific conditions in Eqn. (10.54). By separating real and imaginary parts and equating the imaginary terms on either side of the relation we get the frequency of oscillations and by equating the real terms on either side of the relation we get the condition that must be satisfied in the amplifier circuit for the oscillations to build up and sustain.

10.15.1 Colpitts Oscillator Z1 =

1 1 , Z2 = , and Z3 = jwL jwC1 j wC 2

Substituting these conditions in Eqn. (10.54), we have  1  1 hfe    jwC1   jwC2

  1  1 =    jwC1   jwC2

  1   1  1 + + j wL  + +  jwL + hie    jwC1   jwC1 jwC2 

 1  1 hie hoe      jwC1   jwC2

  1 +   jwC 2

  1  1    jwL  + hoe   jwC1   jwC2  

  −1  1 −hfe L  jh L L 1  −1 +  − oe = 2 + + jhie wL −  +   + hie hoe  2 2 w C1C2 w C1C2 C1  wC1 wC2    w C1C2 C2  wC1C2  Equating imaginary terms on either side of Eqn. (10.55),   1 1   hoe L hie wL −  + =0  −   wC1 wC2   wC1C2 Or w 2 LC1C2 − (C1 + C2 ) =

hoe L hie

  j wL 

(10.55)

Oscillators

523

Or w 2 LC1C2 = (C1 + C2 ) + w2 =

hoe L hie

hoe 1 1 1   + + L  C1 C2  hieC1C2

(10.56)

The second term in the above equation becomes negligible, since hoe hie is extremely small in all transistors. As a result, the frequency of oscillations of this circuit can be written as w2 =

1 1 1   +  L  C1 C2 

Let Ceq be the equivalent capacitance of C1 and C2 and we have 1 1 1 = + Ceq C1 C2

w2 =

f =

1 , LCeq

w=

1 LCeq

1 2p LCeq

(10.57)

Equating real terms on either side of Eqn. (10.55)  −1 −hfe L L −1 = 2 + + hie hoe  2 +  2 w C1C2 w C1C2 C1  w C1C2 C2  −hfe = −1 + w 2 LC2 + hie hoe  −1 + w 2 LC1  = −1 − hie hoe + w 2 ( LC2 + hie hoe LC1 ) Substituting Eqn (10.56) in Eqn (10.58) 1  1 hoe  1  − hfe = −1 − hie hoe + ( LC2 + hie hoe LC1 )   +  +  L  C1 C2  hieC1C2  h L C2 C L + 1 + oe + hie hoe + hie hoe 1 + hoe2 C1 hieC1 C2 C2 h L C C L C2 −hfe = 2 + oe + hie hoe 1 + hoe2 ≈ C1 hieC1 C2 C2 C1

−hfe = −1 − hie hoe +

since the other terms can be neglected as hoe is negligible.

(10.58)

524

Electronic Devices and Circuits

Hence the condition to be satisfied for the oscillations to build up and sustain is hfe ≥

C2 C1

(10.59)

10.15.2 Hartley Oscillator Z1 = jwL1 , Z2 = jwL2 and Z3 =

1 j wC

Substituting these conditions in Eqn. (10.54), we have   1   1  hfe ( jwL1 )( jwL2 ) = ( jwL1 )( jwL2 ) + ( jwL1 )   + hie  jwL1 + jwL2 +   +  jw C   j wC      1   1  hie hoe ( jwL1 ) ( jwL2 ) + ( jwL2 )    + hoe ( jwL1 )( jwL2 )    j wC    j wC  

(1 − hfe ) w 2 L1L2 =

L1L2 L1 L2  1   2  + jhie w ( L1 + L2 ) −  + hie hoe  −w L1L2 + C  + jwhoe C w C C    

(10.60)

Equating imaginary terms on either side of Eqn. (10.60) LL 1   hie w ( L1 + L2 ) − + whoe 1 2 = 0  wC  C  w 2 ( L1 + L2 )C − 1 + w 2 L1L2

hoe =0 hie

 h  w 2  ( L1 + L2 )C + L1L2 oe  = 1 hie  

(10.61)

Since hoe hie is extremely small in all transistors, the above equation (10.61)can be simplified as w 2 ( L1 + L2 )C = 1 w2 =

w=

1

( L1 + L2 )C 1

( L1 + L2 )C 1

f = 2p

( L1 + L2 )C

(10.62)

Oscillators

525

Equation (10.62) gives the frequency of oscillations. Equating real terms on either side of Eqn. (10.60), −hfew 2 L1L2 = −w 2 L1L2 +

L1 L   + hie hoe  −w 2 L1L2 + 2  C C  

−hfe = −1 − hie hoe +

L1 + hie hoe L2 w 2 L1L2C

L1 + hie hoe L2 L1L2C

−hfe = −1 − hie hoe +

 hoe   ( L1 + L2 )C + L1L2  hie   

( L1 + hie hoe L2 )  ( L1 + L2 )C + L1L2 

−hfe = −1 − hie hoe +

−hfe = −1 − hie hoe +

− hfe =

hoe   hie 

L1L2C L1 L h L L + 1 + hie hoe + hie hoe 2 + oe 1 + hoe2 2 L2 L1 hieC C

L1 L h L L L + hie hoe 2 + oe 1 + hoe2 2 ≈ 1 1 L2 L1 hieC C L2

(10.63)

since hoe is negligible. Hence the condition to be satisfied for the oscillations to build up and sustain is hfe ≥

L1 L2

(10.64)

Additional Solved Examples Example 10.6 In a transistor Hartley oscillator, the two inductances are 2 mH and 20 µH. The frequency is to be changed from 950 and 2050 kHz. Calculate the range over which the capacitor is to be varied. Solution: f =

f2 =

1 2p CLeq

and Leq = L1 + L2 = 2000 + 20 = 2020 µH.

1 1 Or C = 40CLeq 40 f 2 Leq

526

Electronic Devices and Circuits

When f = 950 kHz, Cmax =

1

(

40 × 950 × 10

3 2

)

= 13.71 pF

× 2020 × 10 −6

When f = 2050 kHz, 1

Cmin =

(

40 × 2050 × 10

3 2

)

= 2.95 pF × 2020 × 10 −6

C varies from 2.95 to 13.71 pF. Example 10.7 A crystal has L = 2 mH, C = 0.01 pF, and R = 2 kΩ. Its mounting capacitance is 2 pF. Calculate its series and parallel resonant frequencies. Solution: From Figure 10.30, the series resonant frequency is given as follows: fs =

1

1

= 35.62 MHz

= −3

2p 2 × 10 × 0.01 × 10 −12

2p LC

and the parallel resonant frequency is given as follows: Ceq =

fp =

CMC 2 × 0.01 = 0.00995 pF = CM + C 2 + 0.01 1

1

=

2p LCeq

−3

2p 2 × 10 × 0.00995 × 10 −12

= 35.69 MHz

Both the resonant frequencies are approximately the same. Example 10.8 A Quartz crystal has the following constants: L = 50 mH, C1 = 0.02 pF, R = 500 Ω, and C2 = 12 pF. (i) Find the values of fs and fp. (ii) If an external capacitor, Cx (stray capacitance), appearing across the crystal terminals, changes from 5 to 6 pF, find the change in the parallel resonant frequency. Solution: Given L = 50 mH, C1 = 0.02 pF, and C2 = 12 pF A A C1 C2

L

C2

Cx

Cx B

R C2′ B

Figure 10.36 Electrical circuit of the crystal when Cx is connected externally

Oscillators

(i)

527

(a) When Cx is not connected, Figure 10.36 fs =

1

= 5.035 MHz

−3

2p 50 × 10 × 0.02 × 10 −12

2p LC1

Ceq = fp =

1 =

C2C1 12 × 0.02 = 0.01997 pF = C2 + C1 12 + 0.02 1

1

=

2p LCeq

−3

2p 50 × 10 × 0.01997 × 10 −12

= 5.04 MHz

(b) When Cx is connected. C2′ = C2 / /Cx = C2 + Cx (ii) (a) When, Cx = 5 pF, C2′ = 12 + 5 = 17 pF Ceq′ =

fp′′=

C2′C1 17 × 0.02 = 0.019976 pF = C2′ + C1 17 + 0.02

1

1

= −3

2p 50 × 10 × 0.019976 × 10 −12

2p LCeq

= 5.0385 MHz

(b) When, Cx = 6 pF, C2′′ = 12 + 6 = 18 pF Ceq′′ =

fp′′=

C2′′C1 18 × 0.02 = 0.01998 pF = C2′ + C1 18 + 0.02 1 2p LCeq

1

=

2p 50 × 10 −3 × 0.0199778 × 10 −12

= 5.0383 MHz

Change in fp = fp′ − f ′′p = 5.0385 − 5.0383 = 0.0002 MHz = 200 Hz. Example 10.9 An RC phase-shift oscillator, using an FET, uses three identical phase-shifting networks in which R = 100 kΩ and C = 64.79 pF. Calculate the frequency of the oscillations and the value of RD. The FET has gm = 5 mmhos and rd = 50 kΩ. Solution: Given, R = 100 kΩ and C = 64.79 pF For the oscillator, f =

1

1 =

2pRC 6

3

2p × 100 × 10 × 64.79 × 10 −12 6

= 10.03 kHz,

528

Electronic Devices and Circuits

For the oscillations to build up and sustain, A ≥ 29. We have A = gm RL or RL =

A 29 = = 5.8 kΩ. gm 5

But RL = rd / / RD 50 × RD = 5.8 kΩ 50 + RD

50 RD = 290 + 5.8 RD RR D D RD =

290 = 6.56 kΩ 44.2

Example 10.10 A crystal has L = 0.4 H, C1 = 0.085 pF, CM = 1 pF, and R = 5 kΩ. Find the following: (i) the series resonant frequency, (ii) the parallel resonant frequency, (iii) by what percent does the parallel resonant frequency exceed the series resonant frequency, and (iv) Q of the crystal. Solution: (i)

fs =

1

1 =

2p LC1

(ii) Ceq =

fp =

2p 0.4 × 0.085 × 10 −12

C1CM 1 × 0.085 = = 0.07834 pF C1 + CM 1 + 0.085 1 2p LCeq

1

=

2p 0.4 × 0.07834 × 10 −12

(iii) Percentage increase =

(iv) Q =

= 863.55 kHz

= 900.90 kHz

900.90 − 863.55 × 100 = 4.325% 863.55

wL 2p × 863.55 × 103 × 0.4 = = 433.85 R 5 × 103

Example 10.11 Find R3, C, and hfe of the transistor to generate oscillations at 50 kHz, in the RC phase shift oscillator shown in Figure 10.37. R1 and R2 are the biasing resistors. R1 = 22 kΩ, R2 = 68 kΩ, RC = 20 kΩ, R = 6.8 kΩ, and hie = 2 kΩ. Solution: The circuit of the RC phase-shift oscillator is shown in Figure 10.37.

Oscillators

529

VCC

R1

C

C

C

RC

R3 R2

R

R RE CE

Figure 10.37 Circuit of the RC phase-shift oscillator

Let

R1 ′ = R1 // R2 // hie = R = R1 ′ + R3

f= ∴

C=

C=

22 × 68 × 2 = 1.785 kΩ (22 × 68) + (68 × 2) + (2 × 22)

R3 = R − R1 ′ = 6.8 − 1.785 = 5.015 kΩ

k=

RC 20 = 2.941 = R 6.8

1 2pRC 6 + 4 k 1 2pRf 6 + 4 k 1 2p × 6.8 × 103 × 50 × 103 6 + 4 × 2.941

hfe = 4 k + 23 +

= 111.12 pF

29 29 = 4 × 2.941 + 23 + = 44.62 k 2.941

Example 10.12 In a Hartley oscillator, L1 = 15 mH, C = 50 pF and the mutual inductance, M = 5 µH. Its frequency of oscillations is 168 kHz. Calculate L2. Solution: In a Hartley oscillator, f =

1 2p LeqC

530

Electronic Devices and Circuits

where Leq = L1 + L2 ± 2M, depending on the dot convention on the coils. Leq =

1 1 = 2 4p f C 4 × 10 × 168 × 103 2

(

)

2

= 17.715 mH × 50 × 10 −12

(i)

L2 = Leq − L1 − 2M = 17.715 − 15 − 2 × 0.005 = 2.705 mH

(ii)

L2 = Leq − L1 + 2M = 17.715 − 15 + 2 × 0.005 = 2.725 mH

Example 10.13 A Colpitts oscillator has a coil of inductance, L = 120 µH, C1 = 300 pF, and C2 = 1200 pF. Find the frequency of oscillations and the minimum value of hfe required to sustain the oscillations. Solution: In a Colpitts oscillator, f = where Ceq =

1 2p LCeq

C1C2 C1 + C2 Ceq =

f=

C1C2 300 × 1200 = 240 pF = C1 + C2 300 + 1200 1

1

=

2p LCeq

−6

2p 120 × 10 × 240 × 10 −12

= 938.97 kHz

Minimum value of hfe required is hfe(min) =

C2 1200 = =4 C1 300

Example 10.14 In a Hartley oscillator, L1 = L2 = 0.5 mH and C can be varied from 100 to 500 pF. Determine the highest and the lowest frequency of oscillations and the frequency range of the oscillator. Mutual coupling between the coils is negligible. Solution: Leq = L1 + L2 = 0.5 + 0.5 = 1 mH (i)

Cmin = 100 pF

Therefore, fmax = (ii)

Cmax = 500 pF

1 2p LeqCmin

1

= −3

2p 1 × 10 × 100 × 10 −12

= 503.6 kHz

Oscillators

531

Therefore, fmin = (iii)

1

1

= −3

2p 1 × 10 × 500 × 10 −12

2p LeqCmax

= 225.18 kHz

Frequency range = fmax − fmin = 503.6 − 225.18 = 278.42 kHz

Example 10.15 Determine the maximum and the minimum frequency of the oscillations developed in the Wien Bridge oscillator, in which the phase-shifting network has R = 10 kΩ and C varies from 0.001 to 1 µF. Solution: The frequency of oscillations of a Wien Bridge oscillator is given as follows: 1 2pRC

f = Given Cmin = 0.001 µF and Cmax = 1 µF fmax =

1 = 15.92 kHz 2p × 10 × 10 × 0.001 × 10 −6 3

fmin =

1 = 15.92 Hz 2p × 10 × 103 × 1 × 10 −6

Example 10.16 A Hartley oscillator has L1 = 1 mH and L2 = 10 mH. Its frequency is required to be varied from 1000 to 2000 kHz. Determine the maximum and the minimum values of C. The mutual coupling between the coils is negligible. Solution:

f =

1 2p CLeq

f2=

and Leq = L1 + L2 = 1 + 10 = 11 µH

1 1 or C = 40CLeq 40 f 2 Leq

When f = 1000 kHz Cmax =

1 2

(

)

40 × 1000 × 103

× 11 × 10 −6

= 2273 pF

When f = 2000 kHz Cmin =

1

(

40 × 2000 × 103

2

)

× 11 × 10 −6

= 568.25 pF

C varies from 568.25 to 2273 pF. Example 10.17 For the Colpitts oscillator, C1 = 0.01 µF, C2 = 0.001 µF, L = 10 mH, and RC = 1800 Ω. Determine (i) f, the frequency (ii) b, the feedback factor (iii) Amin, the minimum gain needed to sustain the oscillations, and (iv) the value of RE, the emitter resistance that can be used to stabilize the gain.

532

Electronic Devices and Circuits

Solution: The basic Colpitts oscillator and the feedback network are shown in Figure 10.38.

+

C1

C1

Vo

L

+

C2 +

Vf

Vo

−

+ C2

−

Vf −

−

Figure 10.38 Basic Colpitts oscillator and the feedback network

( i)

f=

where Ceq =

1 2p LCeq C1C2 C1 + C2

Ceq =

f=

C1C2 0.01 × 0.001 = 909.1 pF = C1 + C2 0.01 + 0.001 1

2p LCeq

1

= 52.82 kHz

= −3

2p 10 × 10 × 909 × 10 −12

(ii)

Vf =Vo

C1 C1 0.001 or b = = = 0.091 C1 + C2 0.001 + 0.01 C1 + C2

(iii)

Amin =

1 1 = = 10.99 b 0.091

(iv)

Amin =

R RC 1800 or RE = C = = 164 Ω Amin 10.99 RE

Example 10.18 In a Colpitts oscillator, C1 = 100 pF and C2 = 1000 pF. L is varied to vary the frequency of oscillations from 1000 to 2000 kHz. Determine the range of L. Solution: In a Colpitts oscillator, f=

1 2p LCeq

Oscillators

where Ceq =

533

C1C2 C1 + C2 Ceq =

L=

C1C2 100 × 1000 = = 90.91 pF C1 + C2 100 + 1000

1 4p f 2Ceq 2

Lmax =

Lmin =

1 4p

2

2

( fmin )

1

= Ceq

1 2

4p 2 ( max ) Ceq

(

40 × 1000 × 10

3 2

)

= 275 µH × 90.91 × 10 −12

1

=

(

40 × 2000 × 10

3 2

)

× 90.91 × 10 −12

= 68.75 µH

Example 10.19 A tuned collector oscillator has an inductance of 50 µH. The frequency is to be varied from 500 to 1000 kHz. (i) Calculate the range of the capacitor. (ii) If L = 50 µH, C = 750 pF, hoe = 25 × 10−6 A/V and the resistance associated with the inductance R is 1 kΩ, calculate the exact frequency of oscillations. Solution: The approximate frequency is (i)

f=

∴

Cmin =

1 2p LC 1 2

4p 2 ( fmax ) L

and Cmax =

Cmin =

f=

4p

( fmin )2 L 1

4p

Cmax =

(ii)

1 2

2

2

( fmax )

=

4p

2

( fmin )

1

= L

(

40 × 1000 × 103

L

1 2

1

1 2

40 ( fmin ) L

2

)

× 50 × 10 −6 1

=

2p LC

(

40 × 500 × 103

1 = −6

= 500 pF

2p 50 × 10 × 750 × 10 −12

2

)

= 1000 pF × 50 × 10 −6

= 822.29 kHz

534

Electronic Devices and Circuits

The exact frequency is given as follows: 2 w exact = w 2 (t1 + hoe R (1)

eoe

)

fexact 1= f

(1 + hoe R )

1 + hoe R = 1 + 25 × 10 −6 × 1 × 103 = 1.025

(1+ hoe R ) = 1.012

fexact = f

(1 + hoe R ) = 822.29 × 1.012 = 832.16 kHz

Example 10.20 A tuned collector oscillator oscillates at 1000 kHz. If C is increased by 50%, calculate the new frequency. Solution: The frequency of oscillations with C is, f1 =

1 2p LC

the new value of capacitance C1 = 1.5C. Therefore, f2 =

. When C is increased by 50%,

1 2p

(1.5C ) L

f2 1 2p LC 1 = × = = 0.8167 f1 2p 1.5CL 1 1.5

f2 = 0.8167 × f1 = 0.8167 × 1000 = 816.7 kHz

Summary • In order to obtain oscillations, the condition (1 + Ab ) = 0 is to be satisfied. This condition is called Barkhausen criterion. • In an oscillator, the external input is zero, but there results an output signal whose frequency depends mainly on the tuned circuit. • Positive feedback is used in an oscillator. • LC oscillators are used in the RF range, and RC oscillators are used in the audio frequency range. • The Q of the tank circuit used in LC and RC oscillators is small, and hence the frequency of the oscillations so generated may not necessarily be stable. • Crystal oscillators are used to generate stable oscillations. • In a beat frequency oscillator two high-frequency signals generated by crystal oscillators are heterodyned or mixed in a mixer, giving rise to stable audio oscillations.

multiple ChoiCe QueStionS 1. The type of feedback used in an oscillator for oscillations to build up is (a) degenerative feedback (b) regenerative feedback (c) composite feedback (d) none of these

Oscillators

535

2. The Barkhausen criterion is given by the following relation:

(a ) (1 + Ab ) = 0

( b ) (1 + Ab ) > 1

( c ) (1 + Ab ) < 1

( d ) Ab >> 1

3. LC oscillators are not used in the audio frequency range mainly because (a) positive feedback cannot be used (b) negative feedback cannot be used (c) size of the inductor is very large (d) size of the inductor is small 4. LC oscillators are mainly used in the (a) radio frequency range (b) audio frequency range (c) ultrasonic frequency range (d) none of these 5. In a practical LC oscillator, the frequency of oscillations is (a) slightly less than the resonant frequency of the tank circuit (b) slightly more than the resonant frequency of the tank circuit (c) much less than the resonant frequency of the tank circuit (d) much more than the resonant frequency of the tank circuit 6. In a Colpitts oscillator, L = 10 µH , C1 = C2 = 20 pF , then the approximate radial frequency is (a) 100 × 106 radians (b) 15.92 MHz (c) 100 MHz (d) 200 MHz 7. In a Hartley oscillator, C = 10 pF , L1 = L2 = 55 mH, then the approximate radial frequency is (a) 100 × 106 radians (b) 15.92 MHz (c) 100 MHz (d) 200 MHz 8. The amplitude condition to be satisfied in an RC phase-shift oscillator using a BJT for oscillations to build up and sustain, when k = 2 is

(a ) hfe ≥ 45.5

( b ) hfe ≥ 52

( c ) hfe ≥ 29

( d ) hfe ≥ 23

9. The best Q of the tank circuit for better frequency stability is (a) 10 (b) 100 (c) 1000 (d) 50,000 10. To generate stable audio frequencies the oscillator used is (a) Beat frequency oscillator (b) Hartley oscillator (c) Colpitts oscillator (d) Tuned collector oscillator

Short anSwer QueStionS 1. What is the main difference between an amplifier and an oscillator? 2. What is the Barkhausen criterion, and what are the two conditions that need to be satisfied for the oscillations to build up and sustain? 3. Why are LC oscillators not preferred in the audio frequency range? 4. Between the Colpitts and Hartley oscillators, which is more preferred and why? 5. What are the two main advantages of the Clapp oscillator over the Colpitts oscillator?

536

Electronic Devices and Circuits

6. Why and where crystal oscillators are used? 7. How is amplitude stability achieved in a Wien bridge oscillator using two transistor amplifiers? 8. Why is the beat frequency oscillator used in the audio frequency range, in preference to an RC oscillator? What is its main limitation?

long anSwer QueStionS 1. Draw the circuit of a Colpitts oscillator and derive the expression for its frequency of oscillations. Also obtain the condition for the oscillations to build up and sustain. Assume ideal components. 2. Draw the circuit of a Hartley oscillator and derive the expression for its frequency of oscillations. Also obtain the condition for the oscillations to build up and sustain. Assume ideal components 3. Draw the circuit of a tuned collector oscillator and derive the expression for its frequency of oscillations. Also obtain the condition for the oscillations to build up and sustain. Assume that the inductor has an associated resistance. 4. Draw the circuit of a Wien bridge oscillator and derive the expression for its frequency of oscillations. Also obtain the condition for the oscillations to build up and sustain. 5. Draw the circuit of a RC phase shift oscillator using an FET and derive the expression for its frequency of oscillations. Also obtain the condition for the oscillations to build up and sustain. 6. Draw the circuit of a RC phase shift oscillator using a BJT and derive the expression for its frequency of oscillations. Also obtain the condition for the oscillations to build up and sustain. 7. Write short notes on (i) Crystal oscillators (ii) Beat frequency oscillators

unSolved problemS 1. A tuned collector oscillator has an inductance of 100 µH. If its frequency is to be varied in the range 100–1000 kHz, determine the maximum and the minimum values of C. 2. A Hartley oscillator has L1 = 100 µH and L2 = 1 mH and C = 100 pF. (i) Find the operating frequency if the coupling between the coils is negligible. (ii) Repeat the calculation if the coefficient of coupling between the coils k = 0.0316. 3. A Colpitts oscillator has a coil of inductance, L = 100 µH, C1 = 200 pF and C2 = 1000 pF. Find the frequency of oscillations and the minimum gain required to sustain the oscillations. 4. In an RC phase shift oscillator using an FET, the RC network uses R = 5 kΩ and C = 0.01 µF. What is the operating frequency and the phase shift produced by each RC network? 5. Determine the frequency range of operation of the Wien Bridge oscillator, if R = 4.7 kΩ and C varies from 0.001 to 1 µF.

11

POWER AMPLIFIERS

Learning objectives After going through this chapter, the reader will be able to       

11.1

Understand the classification of power amplifiers, namely, class A, class B, and class C Analyze power amplifiers using the graphical procedure Calculate the output power, harmonic distortion, and the conversion efficiency of seriesfed and single-ended transformer-coupled class-A power amplifiers Realize the need for class-A and class-B push–pull power amplifiers Appreciate the need for eliminating transformers in power amplifiers as in complementary push–pull power amplifiers Understand the relevance of class-D and class-S power amplifiers Understand the need for heat sinks in power amplifiers

INTRODUCTION

ib

Small-signal amplifiers, also called voltage iC amplifiers, are amplifiers in which the input IC(sat) signal swing is so small that the operation of the transistor is restricted to a small limited region in the transfer characteristic, in which region the characteristic is linear. As such ic A small signal amplifiers are also called linear I IC1 0 Q1 I = C(sat) amplifiers as shown in Figure 11.1. A voltage C1 wt 2 amplifier gives only voltage gain but not the B necessary power output. However, if the input swing is large, the operation is not restricted to a small linear 0 IB1 region in the transfer curve, but stretches iB into the nonlinear region. Then, the amplifier 0 is called a large-signal amplifier or a power amplifier as shown in Figure 11.2. A power amplifier gives the necessary power output so Figure 11.1 Voltage amplifier or small-signal amplifier as to drive a loud speaker or a relay. The output of a voltage amplifier is usually the input to a power amplifier. Power amplifiers are classified as (i) class-A power amplifier, (ii) class-B power amplifier, and (iii) class-C power amplifier. wt

538

Electronic Devices and Circuits

wt

(i) Class-A power amplifier is one in which there is output for the entire input cycle period. For this to happen, the transistor is required to be biased in the active region. Thus, all voltage amplifiers are biased in the active region; Figures 11.1 and 11.2 represent class-A operation of voltage and power amplifiers. The major limitation of class-A operation is that even when there is no input, there is appreciable power dissipation ( PD = VCE I C ) in the transistor. If a battery is used as a dc source for biasing the transistor, the life of the battery is reduced as there is drain on the battery even under quiescent (no-signal) condition. The life of a battery is usually specified in ampere-hours. (ii) Class-B power amplifier is one in which there is iC output for exactly one-half of the input cycle IC(sat) period. This means that the transistor conducts during only one half cycle of the input signal period (X) and is OFF during the other A ic half cycle (Y) as shown in Figure 11.3. There IC Q is no output during the shaded region (Y). In wt this type of operation, the transistor is biased at cut-off. Under quiescent condition, there is no current drawn from the dc source, and hence B there is no dissipation in the transistor under 0 no-signal condition. This gives a longer life for IB iB 0 the battery, which is desirable, particularly when the amplifier is used in remote places ib where there is no access to conventional power to derive the necessary dc voltage using a transformer, rectifier, and filter. Class-A and Figure 11.2 Large signal or power amplifier class-B power amplifiers are used mostly for audio-frequency applications. iC (iii) Class-C power amplifier is one in which IC(sat) the output current flows for less than one half of the input cycle period (Figure 11.4). Consequently, the output is in the form of pulses. There is IC no output during the shaded region. Such an output, we know from Fourier analysis, contains many freX quency components. In order to get back the original signal in the outQ put of the power amplifier, a tuned iB 0 0 p 0 circuit or filter is used. Class-C power X amplifiers are usually tuned power Y p amplifiers that are used in the radio2p frequency range. They are also used as harmonic generators. Figure 11.3 Class-B operation In addition to the classifications mentioned till now, we have many more classifications, of which we will subsequently consider the principle of operation of class-D and class-S power amplifiers.

Power Amplifiers

539

iC IC(sat)

IC

X Q iB

0

q1

q2

q1

0

X p

q2

2p

Figure 11.4 Class-C operation

11.2

DISTORTION IN POWER AMPLIFIERS

In a small-signal amplifier if the input swing ib varies as I bm coswt , the output collector current swing also varies as ic = I cm cos wt. There is no amplitude distortion in the output, and hence no frequency distortion. The output has the same frequency as the input. Let now the input swing be increased further, so that in the region of operation in the transfer curve is represented by a parabola with the operating point as the vertex. Then, even though the input has only one frequency w, as the amplitude of the signal in the output gets distorted, which results in frequency distortion (Figure 11.2). As ib = I bm coswt , we can write for ic as follows: ic = G1ib + G2 ib 2 = G1I bm cos wt + G2 ( I bm cos wt )2 = G1I bm cos wt +

G2 I bm 2 (1 + cos 2wt ) 2

Therefore, ic can be written as follows: ic = B0 + B1 cos wt + B2 cos 2wt

(11.1)

where B0 = B2 =

2 G2 I bm and B1 = G1I bm 2

From Eqn. (11.1), it can be noted that the output of the power amplifier not only contains the required fundamental frequency, w, but also contains an unwanted dc component of current B0 and a second harmonic component 2w, having a magnitude B2 . Thus, we say that the output contains harmonic distortion. If, alternatively, the operation is not restricted to a small limited region, then ic can be expressed as power series:

540

Electronic Devices and Circuits

ic = G1ib + G2 ib 2 + G3ib3 + G4 ib 4 + ... Then, ic can be written as follows: ic = B0 + B1 cos wt + B2 cos 2wt + B3 cos 3wt + B4 cos 4wt + ...

(11.2)

where Bn , n = 1,2,3,4,… represent the magnitudes of various frequency components. Thus, higher order harmonics can also be present in the output. The magnitudes of the higher order components are usually smaller. It is the second harmonic component that is usually the worst offender. Thus, it is established that harmonic distortion is invariably present in the output of a power amplifier. In a subsequent section, we try evaluate the magnitudes of Bs and think of methods to minimize harmonic distortion.

11.3

CLASS-A POWER AMPLIFIER

A class-A power amplifier, as defined earlier, is an amplifier in which the transistor is ON for entire input cycle period. If the transistor is biased in the active region, then the type operation is called class-A operation. The main limitation of class-A operation is the dissipation in the transistor even under no-signal condition. We now consider a few class-A power amplifier circuits.

11.3.1 Series-Fed Class-A Power Amplifier VCC The voltage amplifier considered in Chapter 6 (CE amplifier) can be used as a power amplifier; the only difference now is that RL the input swing is large. Consider the amplifier circuit shown in Figure 11.5. This is called series-fed power amplifier because Ic + the load RL is directly connected to the collector terminal. Cc Vo To calculate the output voltage and hence the ac output power, Q we cannot use the small-signal model of the transistor. The Ib method of analysis is, therefore, essentially graphical method. RB The procedure to calculate the output power is to first plot the + Vs output characteristics of the given transistor, draw the dc load VBB line, and locate the Q-point. Then, draw the ac load line, superimpose a suitable base current swing on the output curves, and find out the corresponding collector current swing and the permissible collector voltage swing. Next, we can calculate the outFigure 11.5 A series-fed class-A put power as illustrated here using Figure 11.6. To draw the dc power amplifier load line, we locate two points IC(sat) = VCC/RL and VCE(cut-off) = VCC. The Q-point is then located. The ac load in this case is the same as the dc load. The base current swing, ib = I bm cosw t is selected such that the output current and voltage swings are symmetric with respect to the operating point. The corresponding ic and vc swings are represented on the output curves. Vm and Im are the maximum voltage and current swings. V(max), V(min), I(max), and I(min) are now obtained.

Calculation of the ac Output Power The ac output power Po = VcIc, where Vc is the rms value of the output voltage and Ic is the rms value of the output current.

Power Amplifiers

541

IB(max) iC IC(sat) IB

I(max)

ib = Ibmcoswt Im IC

IB(min)

Q

wt

0 dc and ac load line

I(min) 0 VCC V(max)

0 V(min)

VC

vCE

wt

Vm

Figure 11.6 Graphical method of analysis

From Figure 11.6, Vm = and Im =

V(max) −V(min) 2 I (max) − I (min) 2

Vc =

Vm V(max) − V(min) = 2 2 2

(11.3)

Ic =

I m I (max) − I (min) = 2 2 2

(11.4)

and

Therefore, the ac output power is

(

)(

 V(max) − V(min)   I (max) − I (min)  V(max) − V(min) I (max) − I (min) Po = PL = Vc I c =     = 8  2 2 2 2

)

(11.5)

Calculation of B 0 , B 1, and B 2 From Eqn. (11.1) we have ic = B0 + B1 cos wt + B2 cos 2wt , where iC is the alternating component of collector current. Therefore, the instantaneous total value of collector current iC is the sum of the ac component iC and the dc component IC. iC = ic + I C = I C + B0 + B1 cos wt + B2 cos 2wt

(11.6)

In Eqn. (11.6), there are three unknowns, namely, B0, B1, and B2. To evaluate these three unknowns, we need three equations. For getting these three equations, we set the following conditions:

542

Electronic Devices and Circuits

(i) When wt = 0, From Figure 11.6, iC = I (max) Using Eqn. (11.6), I (max) = I C + B0 + B1 + B2

(11.7)

I C = I C + B0 − B2

(11.8)

I (min) = I C + B0 − B1 + B2

(11.9)

p , 2 From Figure 11.6, iC = I C (ii) When wt =

Using Eqn. (11.6),

(iii) When wt = p , From Figure 11.6, iC = I (min) Using Eqn. (11.6),

Solving Eqs (11.7), (11.8), and (11.9), B1 =

(I

(max)

− I (min) )

(11.10)

2

and B0 = B2 =

I (max) + I (min) − 2 I C

(11.11)

4

Using Eqs (11.10) and (11.11), B0, B1, and B2 are calculated. B1 and B2 are the maximum values of the fundamental and the second harmonic components of currents. The total output power PL is now due to the fundamental and the second harmonic components. B 2R B 2R B 2R PL = 1 L + 2 L = 1 L 2 2 2 where the second harmonic distortion, D2 =

(

  B 2  1 +  2   = P1 1 + D2 2   B1  

(

)

(11.12)

B2 and P1 is the power due to the fundamental B1 2

)

component. If D2 = 10%, then PL = P1 1 + ( 0.1) = 1.01P1. To calculate the magnitudes of the higher order harmonics: If there is need to calculate the magnitudes of higher order harmonics as given by Eqn. (11.2), it is required to get five equations. To get five equations, in addition to the conditions imposed earlier, we have to impose two more

Power Amplifiers

543

additional conditions. We now additionally consider iC at ib = Ibm/2 and − Ibm/2 and name the corresponding values of i as I 1 and I − 1 as indicated in Figure 11.7. C

2

2

We have, using Eqn. (11.2), iC = I C + B0 + B1 cos wt + B2 cos 2wt + B3 cos 3wt + B4 cos 4wt + ...

(11.13)

From Figure 11.7, IB(max) iC

Ibm/2

IC(sat)

IB

I(max)

ib = Ibmcoswt −Ibm/2

I1/2

Im

IC

Ibm

Q

wt

IB(min)

I1/2

0

0 dc and ac load line

I(min)

123p

V(min)

vCE

VCC V(max)

0

1 = p/3 2 = p/2 3 = 2p/3

VC wt

Vm

Figure 11.7 Five-point method to calculate B0, B1, B2, B3, and B4

p , iC = I 1 2 3 2p (iv) When wt = , iC = I − 1 2 3

(i) When wt = 0, iC = I (max)

(ii) When wt =

p , iC = I C 2 (v) When wt = p , iC = I (min)

(iii) When wt =

Substituting the above five conditions in Eqn. (11.13), we get five equations; and by solving the five equations, popularly known as the Espley’s method, we get 1 I (max) + 2 I 1 + 2 I − 1 + I (min) − I C 2 2 6 1 B1 = I (max) + I 1 + I − 1 + I (min) 2 2 3

B0 =

( (

)

)

1 ( I (max) − 2I C + I (min) ) 4 1 B3 = I (max) − 2 I 1 + 2 I − 1 − I (min) 2 2 6 1 B4 = I (max) − 4 I 1 + 6 I C − 4 I − 1 + I (min) 2 2 6

(11.14)

B2 =

( (

)

)

544

Electronic Devices and Circuits

Using Eqn. (11.14), PL =

B12 RL 1 + D2 2 + D32 + D4 2 = P1 1 + D 2 2

(

)

(

)

(11.15)

where D 2 = ( D2 )2 + ( D3 )2 + ( D4 )2

(11.16)

Calculation of Conversion Efficiency The effectiveness with which the power amplifier is able to convert the given total dc input power into the required ac output power is given by the conversion efficiency, h of the power amplifier. Conversion efficiency, h =

P Ac output power = L Total dc input power PBB

Conversion efficiency h is usually expressed as a percentage. Using the simplified presentation of Figure 11.7 by avoiding the output curves as shown in Figure 11.8, we have iC I(max)

IC

Q dc and ac load line VCC

I(min) 0 V(min) 0

0

vCE

V(max)

VC

Figure 11.8 Simplified representation of Figure 11.7

V( max ) ≈ VCC ,V( min ) ≈ 0, I ( min ) ≈ 0 and I ( max ) = 2 I C and substituting these values in Eqn. (11.5),

PL (max) = and

(V

(max)

−V(min) ) ( I (max) − I (min) ) 8

=

VCC × 2 I C VCC I C = 8 4

(11.17)

Power Amplifiers

PBB = VCC I C

h(max) =

PL (max) PBB

545

(11.18)

VCC I C = 4 × 100 = 25% VCC I C

(11.19)

It is evident from Eqn. (11.19) that a series-fed class-A power amplifier has a maximum conversion efficiency of only 25 percent. This means that if a total dc input power of 1 W is given to the power amplifier, only 0.25 W is available as the required ac output power. The rest of the power of 0.75 W is dissipated in the transistor and the load; that is, it is simply wasted in heating the transistor and the load. This is the major disadvantage of this amplifier.

Power Dissipation in the Transistor, PD Consider the

VCC

output circuit of the power amplifier as shown in Figure 11.9. From Figure 11.9, it can be noted that there is a dc component of current I C in RL and also an rms component of current I c due to the input signal and an rms component of voltage Vc across the load. PD is the power dissipation in the transistor and VC is the dc voltage at the collector. Therefore, the total dc input power is the sum of the dc power dissipated in RL , ac power in the load, and the power dissipated in the transistor. VCC I C = I C 2 RL + Vc I c + PD

RL

IC

Ic

+ Vc ,VC Q PD

(11.20)

Also (11.21)

VCC = VC + I C RL

Figure 11.9 Circuit to calculate PD

Substituting Eqn. (11.21) in Eqn. (11.20),

(VC + I C RL ) I C = I C 2 RL + Vc I c + PD Therefore, VC I C = Vc I c + PD PD = VC I C − Vc I c

(11.22)

PD is maximum when the second term in Eqn. (11.22) is zero: PD(max) = VC I C

(11.23)

VC = Vm = 2Vc and I C = I m = 2 I c

(11.24)

But from Figure 11.8,

546

Electronic Devices and Circuits

Substituting the relations in Eqn. (11.24) in Eqn. (11.23), (11.25)

PD(max) = VC I C = 2Vc × 2 I c = 2Vc I c = 2 PL (max)

From Eqn. (11.25), it can be noted that the amount of dissipation that occurs in the device is twice the maximum amount of ac output power that one desires to get at the output of the power amplifier. Therefore, if PL (max) = 1 W, then one should choose a transistor with a power dissipation capability of at least 2 W. This means that the choice of transistor depends on the desired ac output power. The larger the desired ac output power, the larger the power dissipation capability of the transistor. PD(max) = PT is specified by the manufacturer at 25°C. As the temperature increases, PD(max) will be less than the value specified at 25 °C. Manufacturer either supplies the derating curve or specifies the derating factor.

Derating Factor and Derating Curve Let for a transistor PD(max) = PT (at25°C) = 5 W (say). If the derating factor is specified as D = 25 mW/ °C, then it means that for every degree rise in temperature, the power dissipation capability decreases by 25 mW. The change in power is given as follows: ∆P = D(TA − 25°C ) = (25°mW / °C ) (TA − 25°C ) where TA is the ambient temperature. If the power dissipation capability of the transistor is to be obtained at 100°C, then

PD(max) 5

∆P = ( 25mW / °C)(100 − 25 ) = 25 × 75 = 1.875 W

(11.26)

W

3.125

∴    PD(max) = PT (at100°C ) = 5 − 1.875 = 3.125 W Alternatively, the derating curve as shown in Figure 11.10 is given in the data sheet. From Figure 11.10, it is possible to find out PD(max) at a given temperature. From Figure 11.10, PD(max) = 3.125 W.

0

100

TA °C

Figure 11.10 Derating curve

Example 11.1 A class-A series-fed power amplifier delivers power to a load of 15 Ω. VCC = 20 V and the coordinates of the Q point are VC = 10 V and IC = 0.5 A. The ac output current swing is ±0.45 A. Determine (i) PBB, (ii) the dc power wasted in RL, (iii) ac power delivered to RL, (iv) PD, and (v) h. Solution: Given VCC = 20 V, IC = 0.5 A, VC = 10 V, and the ac current swing = Im = 0.45 A. (i) PBB = VCC I C = 20 ×0.5 = 10 W . (ii) Dc power wasted in RL = I C 2 RL = ( 0.5 )2 × 15 = 3.75 W

Power Amplifiers

IC =

Im

0.45 =

2

547

= 0.318 A

2

(iii) Ac power delivered to RL , PL = ( 0.318)2 × 15 = 1.52 W (iv) PD = PBB − dc power wasted in RL − ac power delivered to RL PD = 10 − 3.75 − 1.52 = 4.73 W (v) h=

1.52 × 100 = 15.2% 10

Example 11.2 A transistor delivers a power of 1 W to a load RL of 1 kΩ. The quiescent collector current is 30 mA and the collector current with signal is 35 mA. Determine D2. Solution: The quiescent collector current IC = 30 mA. The dc collector current with signal = 35 mA = IC + Bo ∴ 

Bo =

(I C + Bo ) − I C = 35 − 30 = 5 mA

We know that Bo = B2 = 5 mA. Also, we know that PL = ∴ 

B12 =

B12 RL 2

2 PL 2 ×1 2 = 2 × 10 −3 = 2000 × 10 −6 ( A ) = RL 1 × 103

 B1 = 2000 mA = 44.72 mA ∴ 

D2 =

B2 5 × 100 = × 100 = 11.18% B1 44.72

It can be noted that the procedure to calculate PL and the magnitudes of Bs is by using the graphical method. It is found out that for a class-A power amplifier, PD(max) = 2PL(max) and h for a class-A series-fed power amplifier is only 25 percent.

11.3.2 Class-A Transformer-Coupled Power Amplifier h for a series-fed power amplifier is poor mainly because of the fact the load resistance RL is small when compared to the output resistance of the amplifier. From maximum power transfer theorem, we know that for maximum power to be transferred from the generator to the load the load must, in the simple case, be equal to the internal resistance of the generator, which in this case is the output resistance of the amplifier. Therefore, if h is to be improved, it is required that RL = Ro. The loads in power amplifiers are low-impedance loads, like the impedance of the voice coil of the loud speaker that typically is of the order of 3 Ω, 8 Ω, 16 Ω, 32 Ω, and so on, and the output resistance of the amplifier is of the order of few kilo-ohms. Hence, there arises the need for an impedance matching transformer as shown in Figure 11.11.

548

Electronic Devices and Circuits

We know that

I1

N V1 N1 I = and also that 2 = 1 I1 N 2 V2 N 2 ∴

 

V1 I 2  N1  × = V2 I1  N 2 

I2 +

+ N2

N1

R′L V1 2

V2

RL

-

-

Figure 11.11 Impedance matching transformer 

Hence, 2

V1  N1  V2 =  I1  N 2  I 2 Therefore, R ′L = a 2 RL

(11.27)

If RL is the load on the secondary side, the load reflected on to the primary side is R′ L and a is the turns ratio of the transformer. Thus, the ac load is different from the dc load. ′ 2 If RL = 10 Ω and a = 50, then RL = (50 ) × 10 = 25 kΩ. If the output resistance of the amplifier is 25 kΩ, then impedance matching is achieved. By choosing proper a we can get desired R ′ L .

Procedure to Draw the ac Load Line to Predict the Possible Signal Swing at the Output We have seen in Chapter 5 the method to locate the Q-point by drawing the dc load line. Consider the circuit in Figure 11.12, its dc circuit in Figure 11.13, and the ac circuit in Figure 11.14. VCC

VCC

IC

RC R1

RL

R1

Cc

IB

+

+ VBE −

Cc RL

+ Vs

Vo

R2 RE

+ V2

R2 RE

−

Figure 11.12 Amplifier circuit

Figure 11.13 DC circuit

Power Amplifiers

549

ic vce

+ −

RL

rc = RC RL

RC

ie re = RE

RE

Figure 11.14 AC circuit

The dc load line is drawn by locating I C (sat ) and VCE(cut −off ) . From Figure 11.13, I C(sat) =

VCC and VCE ( cut −off ) = VCC RC + RE

Preferably, the Q-point is located such that under quiescent condition, I C = I CQ =

I C(sat)

, and the 2 corresponding VCE is termed VCEQ (Figure 11.15). The ac load line is now drawn using the ac circuit in Figure 11.14, where rc is the ac resistance in the collector circuit and re is the ac resistance in the emitter loop. We have from Figure 11.14,

iC IC(sat)

ICQ =

IC(sat) 2

ac load line

Q dc load line

0

VCEQ

vCE

VCC

Figure 11.15 Drawing the ac load line

vce + ie re + ic rc = 0

since

ie ≈ ic , ic =

−vce rc + re

When an ac signal is applied, it causes the change in the collector current and voltage.

(11.28)

550

Electronic Devices and Circuits

Therefore, ic = iC − I CQ and vce = vCE − VCEQ

(11.29)

Substituting the conditions in Eqn. (11.29) in Eqn. (11.28), iC − I CQ =

iC =

VCEQ rc + re

−(vCE − VCEQ ) rc + re + I CQ −

vCE rc + re

(11.30)

Equation (11.30) is in the form of y = mx + c . To draw this straight line, (i) Set vCE = 0 , then iC =

VCEQ rc + re

+ I CQ

(ii) Set iC = 0, then vCE = VCEQ + I CQ ( rc + re ) These two points are located in Figure 11.15 and the line joining these two points is the ac load line that passes through the Q-point. The ac load lines are different for different values of rc and re. Example 11.3 For the amplifier circuit shown in Figure 11.12, RC = 1kΩ, RE = 1kΩ, RL = 0.5 kΩ, and VCC = 30 V . Under ac conditions, RE is effectively bypassed by CE. (i) Draw the dc load line and locate the Q-point and (ii) draw the ac load line. Solution: (i) To draw the dc load line, we have I C(sat) =

VCC 30 = 15 mA = RC + RE 1 + 1

VCE ( cut −off ) = VCC = 30 V and I CQ =

I C(sat) 2

=

15 = 7.5 mA 2

and VCEQ = VCC − I CQ ( RC + RE ) = 30 − 7.5 (1 + 1) = 15V. 1 (ii) To draw the ac load line, from Figure 11.14, we have rc = RC / / RL = 1kΩ / /0.5 kΩ = kΩ , 3 and since RE is effectively bypassed by CE , re = 0 .  

∴ iC =

VCEQ rc + re

+ I CQ =

15 + 7.5 = 45 + 7.5 = 52.5 mA 1 3

and  1 vCE = VCEQ + I CQ (rc + re ) = 15 + 7.5   = 15 + 2.5 = 17.5 V  3

Power Amplifiers

551

The dc and ac load lines are drawn as in Figure 11.16. mA 52.5 15

ac load line

7.5

Q dc load line

0 15

17.5

30

V

Figure 11.16 Dc and ac load lines for Example 11.3

A Single-Ended Transformer-Coupled Class-A Power Amplifier A class-A single-ended transformer-coupled amplifier is shown in Figure 11.17. The ac circuit of Figure 11.17, assuming that R1 and R2 are large, is shown in Figure 11.18. CE and CB ideally behave as short circuits. To calculate the ac output power, once again we resort to graphical procedure. The dc load for the amplifier is the dc resistance offered by the primary winding of the output transformer, which is negligibly small, typically of the order of few ohms (say 10 Ω). Then the dc load line is almost a vertical line. An appropriate Q point is chosen on the dc load line, ensuring that the output voltage swing is symmetric with reference to the Q point. The point where the dc load line intercepts the VCE-axis is VCC. If RL is the load, R′L is the impedance reflected on to the primary side of the output transformer, which is the ac load for the amplifier. Therefore, the ac load line, with a slope equal to −1 RL′ and passing through the Q point, is drawn to find out the permissible output swing as indicated in Figure 11.19.

VCC N1 R1

N2 + RL Vo

R ′L

RS + N3

Vs −

N4 CB

R2

RE

CE −

Figure 11.17 Class-A single-ended transformer-coupled power amplifier

552

Electronic Devices and Circuits

N1

RS

N2

R ′L

+ Vs

RL

N4

N3

+ Vo −

−

Figure 11.18 AC circuit of Figure 11.17 dc load line

I(max)

IC

Q ac load line for R′L VCC

I(min) 0 V(min) 0

0

vCE

VC = VCC V(max)

Figure 11.19 Graphical procedure to calculate PL′ of transformer-coupled power amplifier

As discussed in Section 11.3, V( max ) ,V( min ) , I ( max ) , and I ( min ) are located on the characteristics, and the ac output power is calculated using Eqn. (11.5). From Figure 11.19, the quiescent voltage VC = VCC and is given as follows: (V(max) +V(min) ) VC = (11.31) 2 The rms value of the output swing is

Vc =

(

V(max) − V(min) VC = 2 2 2

)

and I c =

IC 2

(11.32)

Using Eqs (11.31) and (11.32), the power on the primary side of the output transformer PL′ is PL′ =

and

PBB =

(V

(max)

− V(min)

2 2

(V

(max)

+ V(min) 2

)× I )×I

C

2

C

Power Amplifiers

(V

(max)

)

− V(min) ×

P′ 2 2 ∴h = L = PBB V(max) + V(min)

(

2

553

IC

)×I

2 × 100%

(11.33)

C

If V( min ) = I ( min ) = 0 then PL′ = PL′ ( max ) Hence, from Eqn. (11.33), h( max ) = 50% The maximum conversion efficiency in the case of a single-ended transformer-coupled class-A power amplifier, therefore, is 50 percent. This means that if the total dc input power is 1 W, then the available ac output power is 0.5 W. Certainly, there is improvement over a series-fed class-A power amplifier. Example 11.4 In a single-ended transformer-coupled power amplifier operated under class-A condition, the operating point is adjusted for symmetrical swing. The amplifier is required to deliver a maximum power of 6 W to a load of 3 Ω. VCC = 18 V and assume V( min ) = 0. Find (i) α, (ii) the peak collector current Im, (iii) coordinates of the Q-point, and (iv) h. Efficiency of the transformer is 75 percent. Solution: (i) As the efficiency of the transformer is 75 percent, then PL′ ( max ) =

PL 6 = = 8W hT 0.75

And with V( min ) = 0 , Vm = VCC = 18 V P ′ L (max ) =

RL′ =

Vm 2 2RL ′ Vm 2 18 × 18 = = 20.25 Ω 2×8 2 PL′ (max)

RL′ = a 2 RL a2 =

RL′ 20.25 = = 6.75, RL 3

a = 2.6

554

(ii)

Electronic Devices and Circuits

PL′ ( max ) =

I m2 RL′ 2

I m2 =

2 PL(max) ′ ′ L

R

=

2×8 = 0.79 20.25

I m = 0.89A

(iii) With Vmin = 0 , Vm = VCC = 18 V and I C = I m = 0.89 A (iv) PBB = VCC I C = 18 × 0.89 = 16.02 W

h(max) =

PL(max) ′ PBB

× 100 =

8 × 100 = 49.94% 16.02

Limitations of Single-Ended Transformer-Coupled Class-A Power Amplifier 1. Although the conversion efficiency is double the conversion efficiency of a series-fed power amplifier, this is still a class-A power amplifier, PD( max ) =2PL′ ( max ). 2. In Section 11.2 the procedure to calculate Bs is discussed, in which B0 to B4 are calculated for one RL. But choosing different values of a, RL′ will be different, for each value of a. Hence, ′ the values of Bs and PL(max) are now calculated and plotted as in Figure 11.20. From Figure ′ 11.20, it can be seen that for a load RL1 , though distortion is minimum, the amount of PL′ ′ ′ derived is only PL1, which is smaller than PL(max) . This says that if distortion is to be small, then the amount of ac output power derived is smaller than the maximum power. This means that you are sacrificing power to reduce distortion. On the contrary, if maximum output power is the requirement, then there is an excessive associated distortion, as in the ′ case of RL2 . Thus, there is need to adjust RL′ to derive the necessary power, of course, with an inevitable amount of distortion. It is obvious here that there is a need to compromise. P′L P ′L(max) P′L1 % Distortion D D2 D3 D4 0

R′L2

R′L1

R′L

′ L and distortion as a function of

Figure 11.20 P

RL′

3. The transformer is a magnetic circuit. The dc resistance offered by the primary winding of the transformer is practically zero so that the dc collector current of the transistor is very large. Such large IC results in large magnetic flux density B. This could result in saturation of the magnetic circuit, and hence can cause distortion as shown in Figure 11.21. This is another limitation of this circuit.

555

Power Amplifiers B, Flux density BQ

QM, Operating point of the magnetic circuit

0

0

HQ

H, Magnetizing force

Figure 11.21 Large IC resulting in saturation of the magnetic circuit

11.3.3 Class-A Push–Pull Power Amplifier The two major limitations of a single-ended transformer-coupled power amplifier, namely excessive distortion and saturation of the magnetic circuit of the amplifier, can be eliminated by using a push–pull configuration. A class-A push–pull power amplifier is shown in Figure 11.22. ic1 ib1

RS +

IB1 + Vs1 VBE1

Q1

IC1 R1

N1

io

R′L

N2

Vs − Ti

ib2

R2 Vs2 VBE2 + IB2

−

RL

VCC R′L

Q2

IC2

N1 To

ic2

Figure 11.22 Class-A push–pull power amplifier

From Figure 11.22, it can be seen that two identical NPN transistors Q1 and Q2 are used in this amplifier. Each of these transistors is operated under class-A condition. The necessary VBE of Q1 and Q2 is derived by R1 and R2. The waveforms are shown in Figure 11.23. Ti and To are the input and the output center-tapped transformers. The characteristic of a center-tapped transformer is that the signals Vs1 and Vs2 are equal in magnitude but opposite in phase as indicated by the dots. The quiescent base currents IB1 = IB2 = IB. When the input signals are present iB1 increases and iB2 decreases. Consequently, iC1 increases and iC2 decreases. The output current io is proportional to (ic1 − ic2) or io = k(iC1 − iC2), because of the output center-tapped transformer, To. Hence, io goes through the positive-going half-cycle. During the period when Vs1 goes through the negative-going period, Vs2 goes through the

iB1

ib1

IB1 0 iB2

ib2

IB2 0 Push io = k(iC1−iC2) 0 io = k(iC2−iC1)

Pull

Figure 11.23 Waveforms of the currents

556

Electronic Devices and Circuits

positive-going period. Hence, iB2 increases and iB1 decreases, and the output current io is now proportional to (iC2 − iC1) or io = k(iC2 − iC1), and is negative because of the phase shift provided by To. In this amplifier when io = k(iC1 − iC2), the output is pushed up (positive-going signal) and when io = k(iC2 − iC1), the output is pulled down (negative-going signal). It is for this reason this circuit is named push–pull amplifier. The output voltage in the load RL is not necessarily a sinusoidal signal. We know that distortion can be present in this amplifier as well. But it is mentioned when considering this amplifier configuration that this will eliminate saturation of the magnetic circuit and also will minimize distortion. Let us see how the push–pull amplifier achieves these twin objectives.

Elimination of Saturation Problem of the Magnetic Circuit From Figure 11.22, it can be seen that IC1 and IC2 are equal dc collector currents of Q1 and Q2, but they flow in opposite directions in one-half of the primary winding of To. Hence, saturation problem of the magnetic circuit of the amplifier that could give rise to distortion is eliminated.

Elimination of Even Harmonic Distortion The base currents of Q1 and Q2 are shifted in phase by 180°. Therefore, if ib1 = I bm coswt, then ib2 = I bm cos(wt + p ). Hence, from Eqn. (11.13), iC1 = I C + B0 + B1 cos wt + B2 cos 2wt + B3 cos 3wt + B4 cos 4wt

(11.34)

and

iC2 = I C + B0 + B1 cos(wt + p ) + B2 cos 2(wt + p ) + B3 cos 3(wt + p ) + B4 cos 4(wt + p )

or

iC2 = I C + B0 − B1 cos wt + B2 cos 2wt − B3 cos 3wt + B4 cos 4wt

(11.35)

Subtracting Eqn. (11.35) from Eqn. (11.34), iC1 − iC 2 = 2 B1 cos wt + 2 B3 cos 3wt io = k ( iC1 − iC 2 ) = 2 kB1 cos wt + 2 kB3 cos 3wt

D3 =

(11.36) (11.37)

2 kB3 B3 = 2 kB1 B1

All even harmonics are totally eliminated. Hence, the total harmonic distortion is reduced. In majority of the cases, the second harmonic term alone almost accounts for the total distortion. As all even harmonics are eliminated in a push–pull amplifier, the total harmonic distortion is drastically reduced. Hence, it is now possible to adjust RL′ to derive PL′ ( max) with minimum distortion. Thus, it is seen that a class-A push–pull amplifier reduces distortion. But still, it is a class-A amplifier and hence h is only 50 percent. This is the limitation of the class-A push–pull power amplifier. The conversion efficiency can be improved in a class-B power amplifier.

Power Amplifiers

11.4

557

CLASS-B PUSH–PULL POWER AMPLIFIER

A class-B push–pull power amplifier is one in which the transistors are biased at cut-off. This means that the transistors do not draw any current in the quiescent state, and there is dc current in the transistors only when an input signal is present. The circuit of a class-B push–pull power amplifier is shown in Figure 11.24. RS

ib1 Vs1

+

VBE1

ic1

Q1

+

N1

−

N2

Vs −

Vs2 Ti

io

R′L

VBE2 − + ib2

RL

VCC R′L

Q2

ic2

N1 To

Figure 11.24 Class-B push–pull power amplifier

From Figure 11.24, it can be seen that VBE1 = VBE2 = 0. Hence, Q1 and Q2 are OFF. When an input signal Vs is present, the signal Vs1 at the base of Q1 could be the same as Vs. However, the signal Vs2 at the base of Q2 is shifted in phase by 180°. When Vs1 is positive Q1 conducts and during this period Q2 is OFF. When Vs2 is positive Q2 conducts and during this period Q1 is OFF. ic1 and ic2 are the collector currents of Q1 and Q2, respectively, when ON. Hence, io = k (ic1 − ic2) as shown in Figure 11.25, the transformer To, being a center-tapped one produces two signals shifted in phase by 180°. Although each of the transistors operates under class-B condition, there is output for the entire input cycle period.

Vs 0

wt

ic1 0

wt

Vs1 0

wt

ic2 0

wt

Vs2 0

wt

vo 0

wt

Figure 11.25 Waveforms of class-B push–pull power amplifier

To calculate the output power of the amplifier, composite characteristics (since two transistors are used and the inputs are shifted in phase by 180°) are drawn and the procedure described earlier is followed as shown in Figure 11.26.

558

Electronic Devices and Circuits

iC1 IB

I(max)

Im

ib

ic IC

0

vCE2

Q

vCE1

0 I(min) iC2

0 0

VC = VCC V (max) V(min) Vm

vce

Figure 11.26 Composite characteristics and the waveforms

If Vc and Ic are the rms values of vce and ic, then P′L, the output power on the primary side of the output transformer is P′L = VcIc. P′L is P′L(max), when V(min) = I(min) = 0.

11.4.1 Calculation of the Conversion Efficiency To calculate h, PBB has to be calculated. To calculate Idc, consider Figure 11.27.

ic1

Q1 N1

+

VCC

Idc N1

To

Q2

ic2

Figure 11.27 Circuit to calculate I dc

Since Q1 and Q2 conduct only for half cycles, the total current drawn from VCC is similar to the output of a full-wave rectifier. We have,

Power Amplifiers

I dc =

2I m 2 2I c = p p

559

(11.38)

If V(min)0, Vm = VCC. Therefore, (11.39)

VCC = 2Vc Using Eqs (11.38) and (11.39), ∴

PBB = VCC I dc = 2Vc ×

2 2 I c 4Vc I c 4 P ′L (max) = = p p p

Hence, h(max) =

PL′ (max) PBB

=

p × 100 = 78.5% 4

(11.40)

Thus, the maximum conversion efficiency of a pure class-B push–pull power amplifier is 78.5 percent. This means that if the total dc input power is 100 W, then the available ac power at the output is 78.5 W; whereas in a class-A push–pull power amplifier, the available ac output power is only 50 W. This is the major advantage of class-B push–pull power amplifier over class-A power amplifier.

11.4.2 Cross-Over Distortion However, till now the assumption made was that Q1 and Q2 conduct the moment the voltage at the base is ideally 0 V. But in practice, Q1 and Q2 conduct only when a voltage Vg is present to forward bias the base–emitter diode. Till such time, these transistors are OFF. The resultant base current variation is shown in Figure 11.28. For the shaded portion of the input, ib = 0. IB1 ib

VBE2

Vγ

Cross-over distortion

0 0

Vγ

VBE1

vbe IB2

Figure 11.28 Cross-over distortion in a pure class-B power amplifier

560

Electronic Devices and Circuits

As Q1 and Q2 are OFF when the input signal vbe changes from +Vg to −Vg , this type of distortion is called cross-over distortion. A push–pull amplifier is chosen because it minimizes distortion. But the amplifier, as can seen from Figure 11.28, is producing an additional unwanted distortion called cross-over distortion, which in turn increases the total distortion in the amplifier. Thus, the very purpose of using a push–pull configuration is defeated. Hence, there arises the need to eliminate cross-over distortion. If a minimum bias voltage Vg is provided between the base–emitter terminals of each transistor, the moment an input signal is present there is base current in the transistor, thereby eliminating cross-over distortion. This is called trickle bias. Imagine a glass full of water. Any extra drop of water poured into it trickles down, hence the name trickle bias. Then, the resultant amplifier is called class-AB amplifier for which h is slightly less than 78.5 percent. Though h is reduced marginally, distortion is kept at a smaller value. In the class-A push–pull power amplifier as shown in Figure 11.22, if R1 and R2 are adjusted such that VBE = Vg , then the amplifier is a class-AB power amplifier.

11.4.3 Dissipation in each Transistor of a Class-B Push–Pull Power Amplifier The dissipation in the transistors is PD = PBB − PL′

(11.41)

and we know that PL′ =

V V V m2 = CC ′ m ′ 2RL 2RL

(11.42)

But PBB =

PL′ VCCVm 4 2VCCVm = × = h 2RL′ p pRL′

(11.43)

Substituting Eqs (11.42) and (11.43) in Eqn. (11.41), PD = PBB − PL′ =

2VCCVm Vm 2 − ′ 2RL pRL′

(11.44)

To get PD(max), differentiate PD with respect to Vm and equate it to zero and get the value of Vm . Substitute this value of Vm in Eqn. (11.44): dPD 2VCC 2Vm = − ′ =0 dVm pRL′ 2RL Therefore, Vm =

2VCC p

(11.45)

Substituting Eqn. (11.45) in Eqn. (11.44), PD = PD(max) =

2 2 2 4VCC 4VCC 2VCC − = p 2 RL′ 2p 2 RL′ p 2 RL′

(11.46)

Power Amplifiers

561

But when V( min ) = 0, Vm = VCC and PL′ = PL′ ( max ) Therefore, from Eqn. (11.42), PL′ (max) =

2 VCC 2RL′

(11.47)

From Eqn. (11.46), PD(max) =

2 2VCC 2 2V 2 4 V2 = × 2 CC′ = 2 × CC′ = 0.4 PL′ (max) 2 ′ p RL 2 p RL p 2RL

(11.48)

From Eqn. (11.48), it can be seen that the maximum dissipation in both the transistors is 0.4 PL′ (max ) . Hence, PD(max) in each transistor PD(max) = 0.2 PL′ (max) =

PL′ (max) 5

(11.49)

Now let it be assumed that the required PL′ (max ) = 10 W. If a class-A power amplifier is used then the transistor is required to have PD(max) = 2 PL′ (max ) = 20 W. Whereas in a class-B push–pull power amplifier to derive the same output power of 10 W, it is enough if the transistor has PD(max) = 0.2 × 10 = 2 W. That is, transistors with lesser power dissipation capability can be used, which reduces the cost. This is another advantage of the class-B push–pull power amplifier.

11.4.4 Determining the Turns Ratio of the Output Transformer, T o 2N1 is the total number of turns on the primary winding of the output transformer, and N2 is the number of turns on secondary.  2N  Given RL , to find the turns ratio  1  , the resistance RCC between the two collectors is to be  N2  2  2 N1  RCC = found out. Then  . RL  N 2  With Vmin = 0, Vm = VCC. Therefore, PL′ =

V2 Vm2 = CC′ ′ 2RL 2RL

(11.50)

2 VCC 2 PL′

(11.51)

RL′ =

562

Electronic Devices and Circuits

From Figure 11.29, Collector of Q1

N1 R′L

P′L

N2

RCC P′L

R′L N1

RL

To

Collector of Q2

Figure 11.29 Finding out the turns ratio of the output transformer 2

 2N  RCC =  1  RL = 4a 2 RL = 4RL′  N2 

(11.52)

Since, 2

N  RL′ =  1  RL = a 2 RL  N2  ′ Thus RL is found from Eqn. (11.51) and RCC is found from Eqn. (11.52). If RCC and RL are  2N  known, then the turns ratio  1  can be found out.  N2 

11.4.5 Determining the Turns Ratio of the Input Transformer, T i Consider the input circuit of the power amplifier (Figure 11.30). Power amplifier being a largesignal amplifier to stabilize the output, usually a small RE is included in the emitter lead, which provides feedback. Ri, the input resistance, is given as follows: Q1 Rs + Vs

N3

RE

RBB

N4 N3

−

RE

Ti

Q2 Ri

Figure 11.30 Determining the turns ratio of the input transformer

Ri = hie + hfe RE

(11.53)

Power Amplifiers

563

Using Eqn. (11.52), RBB = 4Ri

(11.54)

2 N3 RBB = N4 Rs

(11.55)

Therefore,

The turns ratio of the input transformer is decided using Eqn. (11.55). Example 11.5 Design a class-AB push–pull power amplifier with trickle-bias using silicon NPN transistors having hie = 100 Ω and hfe = 100 (Figure 11.31). The amplifier is required to deliver an output power of 1 W to a load of 3 Ω. The transformers have an efficiency of 75 percent. The internal resistance of the driving source is 1 kΩ.VCE ( max ) = 30 V and PD(max) = 4 W , for each transistor.

Q1 RS

R1

+ Vs

N1

N3 RE

N2

N4 R2

−

RE

N3 Ti

VCC

RL

N1

Q2

Figure 11.31 Class-AB push–pull power amplifier

Solution: Given PL = 1W and hT = 0.75 ∴

PL′ =

1 = 1.33 W 0.75

Usually, VCC ≤

VCE ( max ) 2

≤ 15 V Therefore choose VCC = 12 V

From Eqn. (11.49), PD(max) in each transistor = 0.2 PL′ (max ) =

PL’ (max ) 5

=

1.33 = 0.267 W 5

564

Electronic Devices and Circuits

Since it is given that each transistor has a dissipation capability of 4 W and the possible dissipation in each transistor in trying to get PL = 1W is only 0.267 W, the transistors can be safely used. Selection of TO : RL′ =

2 VCC 12 × 12 = = 54 Ω ′ 2 PL 2 × 1.33

RCC = 4 × 54 = 216 Ω ∴ 

 2 N1  2 216  N  = 3 = 72 2

 

2 N1 − 72 = 8.49 N2

The total number of turns on the primary side of the output transformer is 8.49 times more than the number of turns on the secondary, and the transformer should have a power rating of 1.5 W. Selecting RE , R1, and R2 : Im =

VCC 12 I 0.22 = = 0.22 A and I dc = m = = 0.07 A 54 p p RL′

Each transistor draws I dc = 70 mA RE is not very large. Choose RE = 10 Ω (typically). Then VE, the voltage drop across RE is VE = I dc RE = 0.07 × 10 = 0.7 V For class-AB operation VBE = 0.7 V. Therefore, the total voltage between the base and the ground is (VBE + VE ) = 1.4 V. R1 and R2 are adjusted to derive 1.4 V between the base and the ground. 1.4 = 12 ×

R2 R1 + R2

1.4 ( R1 + R2 ) = 12R2

R1 = 7.58R2

Choose R2 = 1000 Ω, then R1 = 7.58 × 1000 = 7580 Ω Selecting Ti: From Eqn. (11.55), Ri = hie + hfe RE = 100 + 100 × 10 = 1100 Ω From Eqn. (11.54) RBB = 4Ri = 4 × 1100 = 4400 Ω Given 2

Rs = 1000 Ω,

 2N3  RBB 4400  N  = R = 1000 = 4.4 s 4

2N3 = 4.4 = 2.1 N4

The secondary of Ti should have 2.1 times more number of turns on the secondary when compared to the primary.

Power Amplifiers

565

11.4.6 Advantages of Class-B Push–Pull Power Amplifier The following are the advantages of a class-B push–pull power amplifier: 1. The efficiency is much higher (78.5 percent), whereas that in a class-A power amplifier the efficiency is only 50 percent. 2. Under zero-signal condition, the dissipation in the device is zero. Hence, the battery used can have a longer life. In addition, PD(max ) = 0.2 PL′ (max ) and hence devices with smaller dissipation capability can be used. Whereas in a class-A power amplifier, PD(max ) = 2 PL′ (max ) . 3. Since, even harmonics are totally eliminated, distortion is minimized. 4. The center-tapped transformer eliminates saturation of the magnetic circuit of the amplifier.

11.4.7 Disadvantages of Class-B Push–Pull Power Amplifier However, class-B push–pull power amplifier has the following disadvantages: 1. First, the transformers, in the audiofrequency range, are wound on an iron core, and hence become bulky and occupy more space. Second, the transformer is a lossy circuit element that accounts for a reduced power output. Third, the center-tap should be an exactly electrical one. 2. Cross-over distortion is present in a pure class-B push–pull amplifier.

11.5

CLASS-B PUSH–PULL POWER AMPLIFIER THAT ELIMINATES THE TRANSFORMER

The purpose of a center-tapped transformer in the push–pull amplifiers is to derive two signals of equal magnitude and of opposite polarity. But the problem with such a circuit arrangement is that the transformer is bulky and is also a lossy circuit element. To overcome these limitations, a transformerless class-B push–pull power amplifier is used (Figure 11.32). VCC

RC Q2

CC Q1

+ Vi

CC Q3

+ RL

Vo

CC RE −VEE

Figure 11.32 A transformer-less class-B push–pull power amplifier

Transistor Q1 acts as a phase splitter. The signal taken from the emitter of Q1 is the same as at the input, because Q1 acts as an emitter follower. If RC = RE, the gain of the inverting amplifier is

566

Electronic Devices and Circuits

1, and the output taken at the collector of Q1 is the same in magnitude but is shifted in phase by 180° with respect to the input. Thus inputs to Q2 and Q3 are signals having the same magnitude but are phase inverted, which precisely was done by a center-tapped transformer. During the period when the input goes through the positive-going half cycle, the input to Q3 is the same, whereas the input to Q2 is inverted. Hence, Q3 is ON and derives a negative-going signal at the output. During the negative-going half cycle of the input, the input to Q2 is positive, whereas that for Q3 is negative. Hence, Q3 is OFF and Q2 is ON. As Q2 acts as an emitter follower, the output is a positive-going signal. Thus, there is output for the entire input cycle period, although each of the transistors operates under class B. −VEE is included to ensure that Q3 operates in the active region.

11.6

COMPLEMENTARY SYMMETRY PUSH–PULL CLASS-B POWER AMPLIFIER

The need for a center-tapped transformer and a phase splitter can be eliminated in a push–pull amplifier using complementary transistors. NPN and PNP transistors are called complementary devices since the polarities of the voltages and the directions of the currents are exactly opposite in these two types of devices. We also know that an emitter follower has the largest current gain. Hence, using complementary transistors in an emitter follower, it is possible to construct a class-B push–pull power amplifier. Consider the emitter follower using an NPN transistor as shown in Figure 11.33. There is output only during the period A VCC and during the period B as the transistor is OFF; the output is zero (shaded region). Now consider the circuit in Figure 11.34, which is A an emitter follower using a PNP transistor. B Here, obviously there can be output only Q1 + during the period B and no output during the Vi period A (shaded region). This means that Q1 A is ON during the positive-going half cycle and Vo B Q2 is ON during the negative-going half cycle, which suggests that by combining these two circuits it is possible to get an amplifier cirRE cuit that gives output for the entire input cycle period, in which, one device takes care of onehalf of the input cycle, and the other device Figure 11.33 Emitter follower using an NPN transistor takes care of the other half. Such a class-B power amplifier is called complementary symmetry push–pull power amplifier, since NPN and PNP devices are called complementary devices (Figure 11.35). But a pure class-B push–pull power amplifier will have cross-over distortion. To eliminate it, we provide trickle bias (Figure 11.36). R and R1 are adjusted such that VBE of each transistor is 0.7 V. However, resistance values may change with temperature and can change the output. Power amplifier being a large-signal amplifier, temperature compensation needs to be provided as in Figure 11.37. If the V–I characteristic of the diode is identical to the VBE − IC characteristic of the transistor, temperature changes do not influence the performance of the amplifier. To get a larger current gain, Darlington transistors are used as in Figure 11.38.

Power Amplifiers

567

VCC VCC

A B Q1

Q1

+ Vi

Cc Vo

Cc + Vo

A B Q2

+ Vi

RL

RE

Figure 11.34 Emitter follower using a PNP transistor

Figure 11.35 Complementary symmetry class-B push–pull power amplifier VCC

R Q1 R1

Cc

Cc

R1

+ Q2

+ Vi

RL

Vo

R

Figure 11.36 Complementary symmetry class-B push–pull power amplifier with trickle bias VCC

Positive half-cycle

R Q1

Input signal

D1

Cc

Cc

D2 Q2

+ Vi

Negative half-cycle

+ RL

Vo

Output signal

R

Figure 11.37 Complementary class-B push–pull power amplifier with temperature compensating diodes

568

Electronic Devices and Circuits VCC

R NPN pair

Q1 Q2

D1 D2

Cc

Cc +

+ Vi

D3

PNP pair

D4

RL

Vo

Q4 Q3

R

Figure 11.38 Class-AB push-pull power amplifier with Darlington transistors

Example 11.6 For the circuit in Figure 11.35, RL = 10 Ω, VCC = 30 V. Calculate the maximum ac output power and the minimum power rating of the transistor. Solution: The no-signal voltage is half the supply voltage, VCC/2 and Vm = VCC/2 Therefore, Vm = 30/2 = 15 V and Im = Vm/RL = 15/10 = 1.5 A. PL ( max ) =

Vm I m 15 × 1.5 = = 11.25 W 2 2

PD(max ) = 0.2 × PL (max ) = 0.2 × 11.25 = 2.25 W

11.7

HEAT SINKS

A power amplifier being a large-signal amplifier, heat is generated at the collector junction of the transistor, which in turn can cause an increase in leakage current. The increase in leakage current can further rise the junction temperature, and this may lead to a cumulative effect that may ultimately lead to thermal runaway of the junction. Second, we have seen that the power rating of the transistor reduces at higher temperatures. Hence, there arises the need to quickly remove the heat at the junction for stable operation. Heat sinks are used to accomplish this objective. A heat sink is a mass of metallic conductor mounted on the casing of the transistor. Heat is transferred from the junction to the casing. The heat sink transfers heat from the casing to surroundings and ambient air. Heat sinks effectively reduce the junction temperature and avoid breakdown of the device. The larger the surface area of the heat sink, the easier it is for the heat to escape into the surrounding air. The power dissipation capability is proportional to the difference in temperatures between the junction and the ambient surroundings. PD ∝ (TJ − TA )

569

Power Amplifiers

PD =

(T − T ) j

A

(11.56)

q jA

where TJ = temperature of the junction in °C TA = ambient temperature, °C q JA = thermal resistance of the junction and the surrounding air, °C / W To understand how heat is removed from the junction to the surrounding air, let us consider the thermal circuit (Figure 11.39). Here, TJ, TC, TS, and TA are temperatures of the junction, casing, surroundings, and the ambient air, respectively and q JC ,q CS and qSA are the thermal resistances between the junction and casing, casing and surroundings, and surroundings and ambient air, respectively. From Figure 11.39, it can be seen that

TA

Ambient air qSA

TS

Surroundings qCS

TC

Casing qJC

TJ

Junction

Figure 11.39 Thermal circuit with heat sink

q jA = q jC + q CS + qSA and q CA = q CS + qSA

(11.57)

And using Eqn. (11.56), q jA =

(T − T ) j

A

PD

q jC =

(T − T ) j

C

PD

q CS =

(TC − TS ) PD

qSA =

(TS − TA ) PD

and q CA =

(TC − TA ) PD

(11.58)

Example.11.7 q JA of a power transistor is 175°C / W . (i) Find PD( max ), if TJ = 100°C and TA = 25°C. (ii) If with a heat sink q JA is reduced to 50°C/W, what is PD( max )? Solution: (i) Given q JA = 175°C/W , TJ = 100°C, and TA = 25°C. Using Eqn. (11.56), PD =

(TJ − TA ) (100 − 25 ) q JA

=

175

= 0.43 W

(ii) If q JA = 50°C / W , then PD =

(TJ − TA ) (100 − 25 ) q JA

=

50

=1.5 W

Thus, the power dissipation capability increases with heat sink.

570

11.8

Electronic Devices and Circuits

A CLASS-D POWER AMPLIFIER

Even in the best power amplifier seen till now, namely the class-B power amplifier, certain amount of power gets wasted in heating the transistors, and hence the efficiency is less than 100 percent. However, if a transistor is used as a switch, then when the transistor is ON or when it is OFF, the amount of dissipation in the device is so negligible that efficiency as high as 100 percent can be achieved. Such an amplifier is called a class-D amplifier. Since the transistor is used as a switch, class-D amplifier is also called a switching amplifier. This type of amplifier can be used in transmitters.

11.8.1 Class-D Amplifier Using Complementary Transistors A class-D amplifier using complementary transistors is shown in Figure 11.40. VCC

Q1

VCC

0

+ Vs −

Vmsinωt

L

C

+

0 Q2 RL

Vo

0

Figure 11.40 Class-D amplifier

Transistors Q1 and Q2 are complementary transistors. An RF transformer couples the input to the two bases. The winding polarities are such that the signals applied to the bases are the same. The inputs are adjusted such that the ON transistor is driven into saturation. During the positive going half cycle of the input signal, Q1 is OFF as it is a PNP transistor and Q2 is ON as it is an NPN transistor. Consequently, VC = 0 (Figure 11.41). During the negative-going half cycle of the input, Q1 is ON and is in saturation and Q2 is OFF (Figure 11.42). Hence, VC = VCC. During the next positive-going half cycle of the input signal, Q1 is once again ON and Q2 is OFF. Hence, VC = 0. During the negative-going half cycle, once again Q2 is ON and Q1 is OFF. VC rises to VCC. This process is repeated, and the result is that VC is a square wave, having amplitude VCC. The spacing between pulses varies with frequency.

VCC

OFF Q1 0 VC = 0 —

0 Q2 ON VCE(sat) = 0

Figure 11.41 Circuit of Figure 11.40 when Q1 is OFF and Q2 is ON

Power Amplifiers

571

VCC

VCC

Q1 VCE(sat) = 0 0 VC = VCC

0

0 Q2 OFF

Figure 11.42 Circuit of Figure 11.40 when Q1 is ON and Q2 is OFF

The output circuit is a high Q-series resonant circuit, which is tuned to the signal frequency so as to recover the original signal transmitted at the output. The larger the value of Q, the better the rejection of the unwanted frequencies.

11.8.2 A Class-D Amplifier Using Center-Tapped Transformer and NPN Transistors A class-D amplifier using center-tapped transformer and NPN transistors Q1 and Q2 as switches is shown in Figure 11.43. The inputs Q1 and Q2 are shifted in phase by 180°. Consequently, the output VC is a square wave referenced to 0 and has an amplitude ±VCC . Such an output, when resolved into its frequency spectrum, contains many frequencies in addition to the fundamental component. The series resonant circuit in the output is tuned to the fundamental frequency to get the desired frequency. From Fourier analysis, the magnitude of the fundamental frequency 4 component in the output is given as V1 = VCC . The ac component of this, therefore, varies as, p VCC

VCC

0 Q1

0 VC −VCC

+ Vs

L

−

C

+

Q2 RL

Vo

0

−VCC

Figure 11.43 Class-D amplifier using NPN transistors and center-tapped transformer

572

Electronic Devices and Circuits

4 VCC sinwt . As a series resonant circuit is used at the output, at resonance, the p effective impedance is resistive and is equal to RL, if the transistor switch is considered to be ideal, V that is, its saturation resistance, RCS = 0. Hence, the fundamental component of current I1 is I1 = 1 . R L 4V Hence, i1 varies as I1sinwt, where I1 = CC . The average current in the output is Iave and is the pRL average over one cycle. Let wt = q

v1 = V1sinwt =

I ave =

4VCC  1  pRL  2p

∫

p

0

4V 4V 1 p  4V  1 sinq dq  = CC  ( − cosq )0  = CC  (1 + 1)  = 2 CC  pRL  2p  p RL  pRL  2p

(11.59)

This is the dc component when one device is ON. Therefore, I dc due to the two devices is I dc = 2 I ave =

8VCC p 2 RL

(11.60)

Therefore, the total dc input power PBB is  8V PBB = VCC I dc =  2 CC  p RL

2  8VCC VCC = 2 p RL 

(11.61)

The output power due to the fundamental component P1 is 2

2  4VCC  8V 2  I  P1 =  1  RL =  RL = 2 CC   2 p RL  2pRL 

(11.62)

The conversion efficiency, h=

P1 × 100% PBB

Therefore, 2 8VCC p 2 RL × 100% = 100% h= 2 8VCC p 2 RL

Thus, the conversion efficiency of a class-D amplifier, ideally, can be as high as 100 percent. But in practice, the transistor switch, when ON has a saturation resistance of RCS. Hence, the output circuit, when Q1 is ON, is drawn as in Figure 11.44.  RL VC reduces by a factor   RL + RCS

 . 

Power Amplifiers

573

Hence

h=

P1 RL × 100 = × 100% PBB RL + RCS

(11.63)

If RL = 100 Ω and RCS = 10 Ω , then

h=

100 × 100 = 90.91% 100 + 10

A More General Class-D Amplifier The output of a square-wave generator is connected VCC as input to an integrator, which converts the square wave into a triangular wave. The input signal and the triangular wave are the inputs Q1 ON to a comparator. A comparator is one that RCS VC gives a high output when the both the inputs are the same (Figure 11.45). The output of the + comparator consists of a train of pulses whose average value is directly proportional to the Q2 OFF RL instantaneous value of the signal at that time. To be able to reconstruct the signal, the frequency of the pulses is required to be reasonably larger than the highest frequency of interest in the input −VCC signal. The width of the pulses is a function of Figure 11.44 VC reduces when RCS is taken into the amplitude and frequency of the signal being consideration amplified (pulse width modulation or PWM), and hence these amplifiers are also called PWM amplifiers. The output contains, in addition to the required signal, unwanted harmonics that must be removed by a low-pass LC filter. In practice, the triangular wave has a much larger frequency than shown in Figures 11.46 and 11.47. Signal input

+ Comparator

Triangle

PWM output

Low pass filter

−

Integrator

Output

Square wave generator

Figure 11.45 Class-D amplifier

As the output of a class-D amplifier is insensitive to the changes in the amplitude of the signal, it cannot be used to amplify an AM signal. It can only be used to amplify an FM signal or any constant amplitude sinusoidal signal.

574

Electronic Devices and Circuits

+VP +Vm 0 −Vm −VP V PWM 0

Figure 11.46 Waveforms of class-D power amplifier

+Vm Input Triangle 0

−Vm V PWM 0

Figure 11.47 Waveforms of the class-D amplifier when the frequency of the triangular wave is much larger than the input signal

11.9

CLASS-S AMPLIFIER

A class-S amplifier is a switching amplifier (Figure 11.48). VCC

Q

VE −

T

VBE +

VCC

L

+ C RL

Vo −

0

Vi T1

Figure 11.48 Class-S amplifier

575

Power Amplifiers

T1 is called the duty cycle, D. When T − VBE ). The LC-filter eliminates ripple and delivers dc to the

This type of amplifier is used in switching regulators. The ratio Vi = VCC , VE = VCC −VBE. Vo = D(VCC

load. In a switching regulator, if the output voltage increases, for any reason, D decreases. The output is restored back to its original value. If, alternatively, Vo decreases, D increases and the output voltage is once again brought back to the required value. VCC

Additional Solved Examples

18 V

Example 11.8 A sinusoidal signal is applied to a series fed class-A power amplifier shown in Figure 11.49. The base current of the transistor varies as ib = 0.005 sinwt . Calculate (i) the coordinates of the Q-point, (ii) PBB, (iii) PL, and (iv) h. Silicon transistor with hFE = 50 and VBE = 0.6 V is used.

IC

RL

RB 4

32 IB

Cc

+ Cc

VCE

+ VBE

+

Solution:

−

+ Vo

−

Vs

−

V − VBE 18 − 0.6 (i) I B = CC = = 4.35 mA RB 4

−

Figure 11.49 Class-A series-fed power amplifier

I C = hFE I B = 50 × 4.35 = 217.5 mA = 0.2175 A VCE = VCC − I C RL = 18 − 0.2175 × 32 = 11.04 V (ii) PBB = VCC I C = 18 × 0.2175 = 3.915 W (iii) I bm = 0.005 A . The rms value of the base current, I b =

0.005 = 0.0035 A 2

The rms value of the collector current, I c = hfe I b = 50 × 0.0035 = 0.175A 2

The ac output power, PL = I c2 RL = ( 0.175 ) × 32 = 0.98 W (iv) h =

PL 0.98 × 100 = × 100 = 25.03% PBB 3.915

Example 11.9 A class-A series-fed power amplifier has h = 20 percent. The amplifier delivers an output power of 1 W. Calculate (i) PBB, (ii) PD in the transistor, and (iii) the minimum power dissipation capability needed for the transistor.

576

Electronic Devices and Circuits

Solution: (i) h =

PL PBB

PBB =

PL 1 = = 5W h 0.2

(ii) PD = PBB − PL = 5 − 1 = 4 W (iii) The power dissipation is maximum when PL = 0 Power dissipation capability needed for the transistor = PBB − 0 = 5 − 0 = 5 W Example 11.10 A load of 15 Ω is connected to a single-ended transformer-coupled class-A power amplifier shown in Figure 11.50. I C drawn by the transistor under no-signal condition is 250 mA. N 4 The transformer has = 1 = . VCC = 9 V. PL = 1 W. The efficiency of the transformer, hT = 75%. N2 1 Calculate (i) PL′ , (ii) rms values of the load voltage and the primary voltage, (iii) rms values of the load current and the primary current, (iv) PBB, (v) h, and (vi) PD. VCC N1 N2 + Vp R′L − Ip

Is + Vs −

RL

IC + RB Vi RE

VBB

CE

−

Figure 11.50 Single-ended transformer-coupled class-A power amplifier

Solution: (i) PL′ =

PL 1 = = 1.33 W hT 0.75 2

N  (ii) R = a RL =  1  RL = 42 × 15 = 240 Ω N  ′ L

2

2

′ L

P =

Vp2(rms)

Vp(rms) Vs (rms)

RL′

=

Vp2(rms) = PL′ RL′ = 1.33 × 240 = 319.2

N1 =4 N2

Vs (rms) =

Vp(rms) 4

=

17.87 = 4.47 V 4

Vp(rms) = 17.87 V

Power Amplifiers

577

(iii) Power delivered to the load, PL = 1W 1 = I s2( rms ) RL I s(rms ) I p(rms )

=

I s2( rms ) =

N1 =4 N2

1 = 0.067 15 I p(rms ) =

I s ( rms ) = 0.26 A

I s(rms ) 4

=

0.26 = 0.065 A 4

(iv) PBB = VCC I C = 9 × 0.25 = 2.25 W (v) h =

PL 1 = × 100 = 44.44% PBB 2.25

(vi) PD = PBB − PL′ = 2.25 − 1.33 = 0.92 W Example 11.11 In a single-ended transformer-coupled power amplifier operated under class-A condition, the operating point is adjusted for symmetrical swing. The amplifier is required to deliver a maximum power of 5 W to a load of 10 Ω. VCC = 20 V and assume V(min) = 0. Find (i) α, (ii) the peak collector current Im, (iii) coordinates of the Q-point, and (iv) h. The transformer is ideal. Solution: (i) PL′ (max ) = 5 W PL′ (max ) = RL′ =

Vm 2 and with V(min) = 0, Vm = VCC = 20 V 2RL′ Vm 2 20 × 20 = = 40 Ω ′ 2×5 2 PL (max)

RL′ = a 2 RL ∴

∴

a2 =

RL′ 40 = =4 RL 10

a=2 (ii) PL′ (max ) =

I m2 RL′ 2

I m2 =

2 PL′ (max) 2 × 5 = = 0.25 40 RL′

(iii) With Vmin = 0, Vm = VCC = 20 V and IC = Im = 0.5 A (iv) PBB = VCC I C = 20 × 0.5 = 10 W

h=

PL 5 × 100 = × 100 = 50% PBB 10

I m = 0.5 A

578

Electronic Devices and Circuits

Example 11.12 A single-ended transformer-coupled class-A power amplifier is driving a 10 Ω load. The quiescent base current is adjusted to be 5 mA. The input signal is adjusted to have a base current swing of 4 mA. The following values are noted from the characteristics: VCE ( max ) = 18.5, VCE ( min ) = 1.5 V, I C ( max ) = 250 mA, and I C ( min ) = 5 mA. N1 4 = . V = 15 V. Determine (i) the rms value of the load current and N 2 1 CC voltage, (ii) ac power delivered to the load, (iii) total dc input power, (iv) power dissipation in the transistor, and (v) efficiency of the amplifier. The transformer has =

Solution: (i) The rms value of the voltage on the primary, Vc =

VCE( max ) − VCE( min) 2 2

=

18.5 − 1.5 = 6.01V 2 2

The rms value of the voltage on the secondary (load), Vs =

Vc 6.01 = = 1.5 V a 4

Il =

Vs 1.5 = = 0.15 A RL 10

The rms value of the load current,

(ii) I c =

I C( max ) − I C( min) 2 2

=

250 − 5 = 86.63 mA 2 2 PL′ = Vc I c = 6.01 × 86.63 = 0.521W

(iii) The quiescent collector current I C =

I C ( max ) + I C ( min ) 2

=

250 + 5 = 127.5 mA 2

PBB = VCC I C = 15 × 127.5 = 1.91 W (iv) Power dissipation in the transistor, PD = PBB − PL′ = 1.91 − 0.521 = 1.39 W

(v) h =

PL′ 0.521 = × 100 = 27.28% 1.91 PBB

Example 11.13 Design a single-ended transformer-coupled class-A power amplifier to deliver a power of 60 mW to a load of 3 Ω. Choose 2N109 transistor and a supply voltage of 10V. The transformer has an efficiency of 80 percent. Note: 2N109 is a Ge PNP transister with PD(max)= 165mw at 25°C.

579

Power Amplifiers

Solution: 2N109 is a Ge PNP transistor with PD(max) = 165 mW at 25°C. PL′ =

PL 60 = = 75 mW hT 0.8

PD in the transistor = 2PL′ = 2 × 75 = 150 mW PD is less than PD(max). Hence, the transistor can be safely used. PL′ =

VCC 2 2RL ′

RL′ =

RL′ = a 2 RL

a2 =

VCC 2 10 × 10 = = 666.66 Ω 2 × 75 2 PL′

RL ′ 666.66 = = 222.22 3 RL

a = 14.90

The transformer is required to have a power rating of 150 mW. Choice of RE, R1, and R2: VCC I C = 2 PL′

VC = VCC = 10 V

IC =

2 PL′ 150 = = 15 mA VCC 10

Choose RE = 47 Ω. RE is meant for stability for the operating point. Therefore, VR, the voltage drop across RE is VR = I C RE = 15 × 47 = 0.71 V For Q to be in the active region, the voltage drop across R2 must be more than 0.7 V by 0.3 V. The voltage drop across R2 = VCC

R2 R1 + R2

1 = 10

R2 R1 + R2

R1 + R2 = 10R2 VCC −10 V

9R2 = R1 Choose R2 = 2.2 kΩ

R1

22

R2

2.2

N1 15

Then

N2 1

RL

R1 = 9R2 = 9 × 2.2 = 20.8 kΩ Choose R1 = 22 kΩ The designed circuit is shown in Figure 11.51. Example 11.14 A class-B power amplifier uses a single transistor and delivers power to a load of 2 kΩ (Figure 11.52). A moving coil meter connected in series with the load measures a dc current of 20 mA. Calculate the ac output power.

RE

CE

47

Figure 11.51 Single-ended transformer-coupled class-A power amplifier

580

Electronic Devices and Circuits

Solution: The amplifier in Figure 11.52 is a pure class-B amplifier. The collector current flows in half cycles. The dc component of collector current is I dc

15 V RL

2 + ic 0

MC ammeter Idc

I = m p

−

or +

I m = pI dc

Idc

+ Vo

Vs 0 −

I rms

pI I = m = dc 2 2

−

Figure 11.52 Single-transistor class-B power amplifier

2

p2 10 2  pI  PL = ( I rms ) RL =  dc  RL = × I dc 2 × RL = × 20 × 10 −3 2 4 4  

(

)

2

× 2 × 103 = 2 W

Example 11.15 An idealized class-B push–pull power amplifier, shown in Figure 11.53, has VCC = 20 V, N 2 = 2 N1 and the load to the amplifier is a loud speaker with an impedance of 16 Ω. The sinusoidal input swing is adjusted such that Vm = VCC. Determine (i) PL′, (ii) PBB, (iii) h , and (iv) dissipation in each transistor. ic1

Q1

+

N1 R′L

Vs1 N2

0

RL

VCC

Vs2 −

Q2

R′L

ic2

N1

Figure 11.53 Idealized class-B push–pull power amplifier

Solution: 2

N  RL’ =  1  RL  N2 

(i) Vm = VCC But,  

N 2 = 2 N1 2

∴

 N  RL′ =  1  RL = 0.25 RL  2 N1  RL′ = 0.25 × 16 = 4 Ω

Power Amplifiers

Im =

Vm VCC 20 = ′ = = 5A 4 RL′ RL

PL′ =

Vm I m 20 × 5 = = 50 W 2 2

(ii) I dc =

581

2I m 2 × 5 = = 3.19 A p p

PBB = VCC I dc = 20 × 3.19 = 63.8 W (iii) h =

PL′ 50 × 100 = × 100 = 78.36% PBB 63.8

(iv) PD in each transistor =

PBB − PL′ 63.8 − 50 = = 6.9 W 2 2

Example 11.16 Design the single-ended transformer-coupled class-A power amplifier shown in Figure 11.54 to deliver a power of 150 mW of audio power into a load of 3 Ω. The quiescent base current is adjusted so that Vm = VCC. The supply voltage VCC = 18 V. The collector dissipation should not exceed 250 mW. VCC

N1

R1

RL

+

VB Vs

N2

+ VBE

VCE −

R2 RE

CE

Figure 11.54 Transformer-coupled amplifier

Solution: RE is included to provide bias stability. Let VE, the voltage drop across RE be 1 V. Therefore, VCE = VCC − 1 = 18 − 1 = 17 V

582

Electronic Devices and Circuits

PD = 250 mW

∴ 

IC =

PD = VCE I C

PD 250 × 10 −3 = = 14.70 mA 17 VCE

VE = I C RE = 1V   ∴

RE =

1 = 68 Ω 14.7 × 10 −3

The bypass condenser CE is chosen such that X CE =

RE = 6.8 Ω 10

1 = 6.8 Ω 2pfCE At f = 50 Hz, CE =

1 = 468.3 mF 2p × 50 × 6.8

Let VBE be 0.7 V. Then VB = VE + 0.7 = 1 + 0.7 = 1.7 V VB = VCC

∴  

R2 + R1 VCC = R2 VB

1+

R2 R2 + R1

R1 18 = = 10.59 R2 1.7

R1 = 9.59 R2

R1 = 9.59R2

Choose R2 = 1000Ω R1 = 9.59 R2 = 9.59 × 1000 = 9.59k Ω

PL′ = 150 mW 2

N  RL′ =  1  RL  N2 

PL′ =

VCC 2 2RL′

RL′ =

VCC 2 18 × 18 = 1080 Ω = 2 PL′ 2 × 150 × 10 −3

2

 N1  RL′ 1080  N  = R = 3 = 360 2 L

N1 = 18.97 N2

Power Amplifiers

583

Example 11.17 A class-A series-fed power amplifier delivers power to a resistive load. The quiescent collector current is 8 mA. The maximum and the minimum collector to emitter voltages are 20 V and 2 V, and the corresponding values of collector currents are 20 mA and 2 mA, when an ac signal is applied to it. Determine: (i) the rms value of the collector voltage and collector current, (ii) ac power output, (iii) power rating of the transistor, and (iv) the second harmonic distortion. Solution: (i) Vc =

Ic =

VCE(max ) − VCE(min) 2 2 I C(max ) − I C(min) 2 2

=

=

20 − 2 2 2

20 − 2 2 2

= 6.36 V

= 6.36 mA

(ii) PL = Vc I c = 6.36 × 6.36 = 40.45 mW (iii) Power rating of the transistor = 2 × PL = 2 × 40.45 = 80.9 mW

(iv) B1 = B2 =

D2 =

I C ( max ) − I C ( min ) 2

=

20 − 2 = 9 mA 2

I C (max ) + I C (min) − 2 I C 4

=

20 + 2 − 2 × 8 = 1.5 mA 4

B2 1.5 × 100 = × 100 = 16.67% 9 B1

Example 11.18 A signal, varying as 2 cos ( 314t ) , is applied to a class-A single-ended transformercoupled power amplifier. The alternating component of collector current is given as follows: ic = 18 cos ( 3140t ) + 1.8 cos ( 2 × 3140t ) + 1.5 cos ( 3 × 3140t ) + 0.6 cos ( 4 × 3140t ) + 0.3 cos ( 5 × 3140t ) (a) Calculate (i) the frequency of the fundamental component of the input, (ii) Dn, n = 2, 3, 4, 5, and (iii) the percent increase in the output power due to distortion. (b) Repeat for a class-A push–pull power amplifier. Solution: (a) The alternating component of collector current is expressed as follows: ic = B1 cos (wt ) + B2 cos ( 2wt ) + B3 cos ( 3wt ) + B4 cos ( 4wt ) + B5 cos ( 5wt )

584

Electronic Devices and Circuits

(i) We have, w = 2pf1 = 3140 Therefore, f1 = 500 Hz

(ii) D2 =

B2 1.8 = = 0.1 18 B1

( D2 )

D3 =

B3 1.5 = = 0.083 B1 18

( D3 )

D4 =

B4 0.6 = = 0.033 18 B1

( D4 )

D5 =

B5 0.3 = = 0.0167 B1 18

( D5 )

2

2

2

2

2

2

= 0.01

= 0.0069

= 0.0011

= 0.0003

2

2

(

)

D 2 = ( D2 ) + ( D3 ) + ( D4 ) + ( D5 ) = 0.01 + 0.0069 + 0.0011 + 0.0003 = 0.0183

(iii) Total output power, PL = P1 1 + D 2 = P1 (1 + 0.0183 ) = 1.0183P1

When the distortion is zero, PL = P1

Therefore, increase in output power due to distortion =

1.0183P1 − P1 × 100 = 1.83% P1

(b) In a push pull–power amplifier, even harmonics are eliminated. Hence, 2

2

D 2 = ( D3 ) + ( D5 ) = 0.0069 + 0.0003 = 0.0072

(

)

Total output power, PL = P1 1 + D 2 = P1 (1 + 0.0072 ) = 1.0072 P1

Therefore, increase in output power due to distortion =

1.0072 P1 − P1 × 100 = 0.72% P1

Thus, it is seen that harmonic distortion is reduced in a push–pull power amplifier.

Power Amplifiers

585

Example 11.19 A class-B push–pull power amplifier is to dissipate 6 W in load of 8 Ω. Specify the output transformer and the transistors. Assume the efficiency of the transformers hT as 75 percent. VCC = 24V Solution: The output circuit of the power amplifier is shown in Figure 11.55. Q1 24 V

N1

R′L

N1

R′L

Q2

RL ∞

N2 VCC

Figure 11.55 Output circuit of the power amplifier

PL = 6 W

PL′ =

PL 6 = = 8W hT 0.75 RL′ =

Vm = VCC

PL′ =

2 VCC Vm2 = 2RL′ 2RL′

2 VCC 242 = = 36 Ω 2 PL′ 2 × 8

The resistance between the two collectors, RCC = 4 × 36 = 144 Ω 2

 2 N1  2 N1 144 = = 18, = 4.24 and the transformer The turns ratio of the output transistor =   N 8 N2  2  should have a power rating of more than 8 W. The voltage swing is symmetric with respect to VCC. Therefore, VCE ( max ) = 2VCC = 2 × 24 = 48 V Vm I m VCC I m = 2 2 2 PL′ 2×8 Im = = = 0.67 A VCC 24 PL′ = ∴ 

I dc =

2 I m 2 × 0.67 = = 0.427 A p p

PBB = VCC I dc = 24 × 0.427 = 10.25 W PD(each) =

PBB − PL′ 10.25 − 8 = = 1.125 W 2 2

The transistor is chosen such that PD ≥ 1.25 W, VCE(max) = 50 V and I C = 500 mA

586

Electronic Devices and Circuits

Example 11.20 Design the class-B push–pull power amplifier with trickle bias shown in Figure 11.56, to deliver 600 mW to a load of 4 Ω. The silicon transistor used has a dissipation capability of 250 mW at 25°C and VCE(max) = 50 V. The output transformer has hT = 75 percent. Determine, VCC, RCC, the turns ratio and the values of the biasing resistors, R1 and R2. Assume RE = 10 Ω. Q1 R1 N1

N3 RE

N2 R2

RE

N3

VCC

RL

N1

Q2

Figure 11.56 Class-B power amplifier with trickle bias

Solution: Given PL = 600 mW, VCE(max) = 50, hT = 75% and RE = 10 Ω PL′ =

PL 600 = = 800 mW ηT 0.75

The output swing is symmetric with respect to VCC. Hence, VCC ≤

VCE(max) 2

=

50 = 25 V 2

Choose VCC = 20 V With Vmin ≈ 0, Vm = VCC

PL′ =

2 VCC 2RL′

RL′ =

2 VCC 202 = = 250 Ω ′ 2 PL 2 × 800

RCC = 4 × 250 = 1000 Ω Therefore, the output transformer should have  2 N1  2 RCC 1000 250  N  = R = 4 = 1 2 L

2 N1 = 15.81 N2

The transformer should have the power rating of at least 1 W.

Power Amplifiers

I m=

VCC 20 = = 80 mA RL’ 250

I dc =

2 I m 2 × 80 = 50.96 mA = p p

IC =

587

I dc = 25.48 mA 2

The dc voltage drop VE across RE is VE ≈ I C RE = 25.48 × 10 −3 × 10 = 0.26 V For the transistor to be in the active region, VBE = 0.6 V. Therefore, the voltage drop, V2, across R2 is required to be 0.6 V more than 0.26 V. V2 = 0.26 + 0.6 = 0.86 V V2 = VCC

1+

R1 VCC = R2 V2

For bias stability, RB ≥ 10RE

R2 R1 + R2

R1 VCC 20 = − 1= − 1 = 22.26 R2 V2 0.86

RB =

R1 = 22.26R2

R1R2 22.26R2 R2 22.26R2 = = R1 + R2 22.26R2 + R2 23.26

If RB = 10RE = 10 × 10 = 100 Ω, 22.26R2 = 100 23.26

R2 = 104 Ω

R1 = 22.26R2 = 22.26×104 = 2315 Ω PBB = VCCIdc = 20 × 50.96 × 10−3 = 1.02 W PD(each) =

PBB − PL′ 1.02 − 0.8 = = 0.11 W 2 2

Example 11.21 A silicon transistor operates with a heat sink. qSA = 1.5°C/W. The transistor, rated at 100 W, has qJC = 0.5°C/W and θCS = 0.5°C/W. What is the maximum power dissipated if TA = 50°C and TJ = 150°C? Solution: q JA = q JC + q CS + q SA = 0.5 + 0.5 + 1.5 = 2.5 oC/W PD =

TJ − TA 150 − 50 = = 40 W q JA 2.5

588

Electronic Devices and Circuits

Summary • A class-A power amplifier is a large-signal amplifier in which the transistor is biased in the active region. There is an output for the entire input cycle period. • In a class-B power amplifier, there is output for exactly one-half of the input cycle period. The output is in the form of half cycles as the transistor is biased at cut-off. • Class-A and class-B amplifiers are used in the audio-frequency range. • A class-C power amplifier is one in which the transistors are biased below cut-off. Consequently the output is in the form of pulses. To get back the original signal, filters or tuned circuits are used. ClassC amplifiers are either used as tuned amplifiers or harmonic generators in the radiofrequency range. • Class-A series-fed power amplifier has a conversion efficiency of 25 percent. The dissipation in the transistor is maximum under quiescent condition PD(max) = 2PL. Harmonic distortion is present in this amplifier. • A class-A single-ended transformer-coupled power amplifier has a conversion efficiency of 50 percent. But additional distortion can be present in the output of the amplifier due to saturation of the magnetic circuit of the amplifier in addition to harmonic distortion. In addition, it still has the associated disadvantages of a series-fed power amplifier. • A class-A push–pull power amplifier eliminates even harmonic distortion and distortion that could be present due to saturation of the magnetic circuit, since equal and opposite dc currents flow in the two halves of the primary winding of the center-tapped output transformer. • A class-B power amplifier has a conversion efficiency of 78.5 percent. But an additional distortion called cross-over distortion could be present in a pure class-B push–pull power amplifier. To eliminate cross-over distortion, trickle bias is provided. • In a class-B push–pull power amplifier the maximum dissipation in each transistor PD(max) = 0.2P´L(max). • A complementary push–pull power amplifier is used to eliminate the center-tapped transformer. • Heat sinks are used to improve the power dissipation capability of the transistors at elevated temperatures. • A class-D amplifier is one in which the transistors are used as switches so that the dissipation in the devices is so small that efficiencies near 100 percent can be achieved.

Multiple Choice Questions 1. The conversion efficiency of a series-fed class-A power amplifier is (a) 100% (b) 75% (c) 25% (d) 50% 2. For a class-A series-fed power amplifier, the total dc input power is 100 W. Then, the ac output power is (a) 78.5 W (b) 50 W (c) 25 W (d) 100 W 3. If 1 W is the maximum ac power output of a class-A power amplifier, then the amount of possible dissipation in the transistor is (a) 0.5 W (b) 0.2 W (c) 0.75 W (d) 2 W

Power Amplifiers

589

4. During graphical analysis, it is found that B1 = 0.2 mA and B0 = 0.01 mA, then the percent second harmonic distortion is (a) 10% (c) 5%

(b) 20% (d) 50%

5. The conversion efficiency of a single-ended transformer-coupled class-A power amplifier is (a) 25% (b) 50% (c) 78.5% (d) 100% 6. In single-ended transformer coupled class-A power amplifier, if the total dc input power is 1 W, then the available ac output power and the dissipation in the transistor are, respectively, (a) 0.5 W and 2 W (b) 0.25 W and 1 W (c) 0.5 W and 1 W (d) 0.785 W and 2 W 7. If PD(max) for a transistor at 25°C is 1 W and the derating factor D = 20 mW/°C, then PD(max) at 50°C is (a) 0.375 mW (b) 500 mW (c) 785 mW (d) 1 W 8. In a single-ended transformer-coupled power amplifier, distortion is present in the output due to saturation of the magnetic circuit mainly because (a) a large dc current flows through the primary winding of the transformer (b) there is no impedance matching (c) ac load to the amplifier is large (d) the load is open circuited 9. The two major advantages of a push–pull power amplifier are (a) even harmonics are eliminated and saturation of the magnetic circuit is prevented (b) efficiency is 100 percent and even harmonics are eliminated (c) dissipation in the transistor under no-signal condition is zero and even harmonics are eliminated (d) dissipation in the transistor under no-signal condition is zero and saturation of the magnetic circuit is prevented 10. In a pure class-B push–pull power amplifier, the total dc input power is 100 W. Then, the ac output power and the possible dissipation in each transistor are, respectively, (a) 78.5 W and 15.7 W (b) 50 W and 50 W (c) 50 W and 100 W (d) 100 W and 100 W 11. The major disadvantage of a pure class-B push–pull power amplifier is that it introduces (a) even harmonic distortion (b) cross-over distortion (c) ripple (d) feedback 12. Cross-over distortion can be eliminated with only a negligible loss in efficiency by (a) providing trickle bias (b) providing mid-point bias (c) biasing at cut-off (d) biasing below cut-off 13. In a single-ended transformer-coupled class-A power amplifier if the power output due to the fundamental component is 500 mW and the total percent distortion is 10 percent, then the total output power is (a) 505 mW (b) 510 mW (c) 575 mW (d) 1000 mW

590

Electronic Devices and Circuits

14. In a complementary symmetry push–pull power amplifier phase inversion is provided by (a) center-tapped transformer (b) NPN and PNP transistors (c) CE amplifier (d) CE–CB pair 15. If qJA of a power transistor is 100°C/W and if TJ = 75°C and TA = 25°C, then PD(max) is (a) 1 W (b) 0.5 W (c) 0.25 W (d) 0.75 W

Short Answer Questions 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

What are the main differences between a voltage amplifier and a power amplifier? A voltage amplifier is used as a preamplifier to a power amplifier. Why? What is a class-A power amplifier? How is the transistor biased? What are the main limitations of the class-A series-fed power amplifier? What is the main improvement in a class-A single-ended transformer power amplifier when compared to a series-fed power amplifier? What is its main limitation? What are the advantages of class-B operation? What are the two major limitations of the class-B operation? What can be listed as the drawback of the class-B operation? What is a class-D amplifier? What are the advantages of complementary symmetry push–pull configuration over the conventional push–pull configuration?

Long Answer Questions 1. Explain the graphical procedure to calculate PL, h, and PD(max) for a series-fed class-A power amplifier. 2. Explain the graphical procedure to calculate P′L (max) and h for a single-ended transformer- coupled class-A power amplifier. 3. Draw the circuit of a class-A push–pull power amplifier and show that this amplifier eliminates some of the disadvantages associated with a single-ended transformer coupled class-A power amplifier. 4. Draw the circuit of a class-B push–pull power amplifier and explain its working. Obtain the expression for its conversion efficiency. What are its advantages and disadvantages? 5. Draw the circuit of a complementary symmetry push–pull power amplifier with trickle bias and temperature compensation and explain its working. What is its advantage over a conventional push–pull power amplifier? 6. Write short notes on (i) cross-over distortion, (ii) class-D power amplifier, and (iii) class-S power amplifier.

Unsolved Problems 1. A sinusoidal signal vs = 1.76 sin (600t ) is fed to a single-ended transformer-coupled power amplifier. The resulting output current is ic = 15 sin(600t) + 1.5 sin(1200t) + 1.2sin (1800t ) + 0.5 sin (2400t ) (i) Determine the percent increase in the output power due to distortion. (ii) Repeat for a class-A push–pull power amplifier. 2. Two transistors operate in a class B push–pull circuit with VCC = 15 V. The turns ratio of the output transformer is 3:1 and RL = 9 Ω. Determine the ac output power and the dc input power. Also find h. 3. A single-ended transformer-coupled class-A power amplifier operates with a supply voltage of 10 V and load of 10 Ω. If PD (max ) = 1 W, calculate (i) PL′ (max ) , (ii) the quiescent collector current, and (iii) the turns ratio of the transformer.

Power Amplifiers

591

4. Determine the efficiency of the transformer coupled class A power amplifier with a supply voltage of 10 V for (i) the peak voltage swing in the output of 10 V and (ii) the peak voltage swing in the output of 5 V. 5. For the circuit shown in Figure 11.36, VCC = 20 V and RL = 3 Ω. If an input voltage of 10 V(rms) is applied, determine (i) the total dc input power, (ii) the ac output power, (iii) the dissipation in each transistor, and (iv) the efficiency. 6. q JA of a power transistor is 150°C/W. Find (i) PD (max ), if TJ = 150°C and TA = 25°C. (ii) If with a heat sink q JA is reduced to 50°C/W, what is PD (max )?

12

HIGH-FREQUENCY TRANSISTOR AND FET AMPLIFIERS

Learning objectives After going through this chapter, the reader will be able to ˆ Appreciate the influence of Miller capacitor on the performance of the transistor at high frequencies ˆ Draw the high-frequency model (hybrid p model) of the transistor ˆ Define the high-frequency parameters of the transistor in terms of the low-frequency parameters ˆ Calculate the short-circuit current gain of a CE transistor amplifier ˆ Calculate hybrid p capacitances ˆ Analyze CS and CD amplifiers at high frequencies

12.1

INTRODUCTION

Chapters 6 and 7 of this book dealt with the analysis of the small-signal amplifiers confining to the low-frequency model. In these two chapters, we have used the low-frequency model of the transistor and FET, and neglected the influence of stray capacitances and the interelectrode capacitances. It has been assumed that stray capacitances and the interelectrode capacitances behave as open circuits at low frequencies. However, when the operation of a transistor is considered at high frequencies, the reactance of these capacitors may not be so large as to be replaced by open circuits. Therefore, we have to consider the influence of these capacitors at radio-frequencies. In order to calculate the gain of the amplifier at high frequencies, a totally different equivalent circuit of the transistor needs to be considered. This equivalent circuit is known as the hybrid p model of the bipolar junction transistor. In the analysis of an RC-coupled amplifier earlier, we have considered the influence of the coupling condenser Cc and the shunt condenser Cs on the performance of the amplifier. At high frequencies, Cc continues to behave as a short circuit. It has to be noted that the reactance of Cs decreases with increase in frequency. Further, the stray capacitance between the input and the output terminals appears as Miller capacitances in shunt with the input and output terminals. Miller capacitance needs to be considered at high frequencies. Miller theorem and Miller effect were presented and made use of in an earlier chapter of this book. It is presented once again here for the sake of continuity and for the convenience of the reader.

High-Frequency Transistor and FET Amplifiers

593

12.2 THE MILLER CAPACITANCES Consider the amplifier circuits in Figure 12.1. If an impedance Z ′ is connected between the input and output nodes in an amplifier, it can be replaced by two impedances Z1 and Z2 connected in Z′ Z′ shunt with the input and the output terminals, where Z1 = and Z2 = . A is the volt1− A 1 − (1 A) age gain of the amplifier. Z′

Z1

C′

+

Amplifier with gain A

Z2

Vi −

Amplifier with gain A

+ Vo −

Figure 12.1 Use of Miller’s theorem to calculate Miller capacitance

If C ′ is in the feedback path, Z1 =

1 wC ′ 1 1 = = 1 − A wC ′ (1 − A) wCMi

where CMi = C ′ (1 − A)

(12.1)

CMi is the Miller capacitance on the input side. Similarly, Z2 =

1 wC ′ 1 1 = = 1 − (1 A) wC ′ (1 − (1 A)) wCMo

where CMo = C ′ (1 − (1 A)) ≈ C ′

(12.2)

CMo is the Miller capacitance on the output side and CMo ≈ C ′ since A is large. Thus, it can be noted that a capacitance C ′ that appears between the input and the output is replaced by two capacitances CMi and CMo. These capacitances CMi and CMo appear in shunt with the input and output terminals.

594

12.3

Electronic Devices and Circuits

CE AMPLIFIER: INFLUENCE OF NETWORK PARAMETERS AT HIGH FREQUENCIES

Consider the CE amplifier at high frequencies (Figure 12.2). In the ac circuit of Figure 12.2, CE and Cc are considered as short circuits due to their high values. The reactance offered by these capacitors is almost zero. The resultant ac circuit is shown in Figure 12.3 VCC RC Cbc

R1

Cc Cce

Cc Rs

RL

Cbe Cwo

R2

+

Cwi CE

RE

Vs −

Figure 12.2 The CE amplifier at high frequencies

RC

Rs Cce + Vs

R2

R1

Cbe

Cwi

Cwo

RL

CMo

CMi

−

Figure 12.3 The ac circuit of Figure 12.2

Co = Cwo + Cce + CMo = Cwo + Cce + Cbe Ci = Cbe + Cwi + CMi = Cbe + Cwi + Cbc (1 − A) Cbe , Cbc , Cce are the interelectrode capacitors, Cwi and Cwo are the stray wiring capacitances on the input and the output side, and CMi and CMo are the Miller capacitances on the input and the output side. Ci is the effective input capacitance and Co is the effective output capacitance. If R = R1 || R2 and RL′ = RL || RC , the circuit shown in Figure 12.3 reduces to that shown in Figure 12.4.

Rs

Co

+

R

R′L

Ci

Vs −

Figure 12.4 The simplified circuit of Figure 12.3

595

High-Frequency Transistor and FET Amplifiers

Replacing the transistor by a current source, Figure 12.4 is simplified to that shown in Figure 12.5. Here, Ri is the input resistance and Ro is the output resistance. Application of Thévenin’s theorem on the input side gives, Vthi and Rthi , which are Thévenin’s voltage source and internal resistance, respectively. Rthi = Rs || R || Ri . Vtho and Rtho are the Thévenin’s source and the internal resistance on the output side. The resistance Rtho = Ro || RL′ is indicated in Figure 12.6. At high frequencies, the effect of Ci is to reduce the input voltage as X Ci becomes small, and hence I b. Similarly at high frequencies, X Co reduces and hence the output voltage. As the frequency increases further, the output reduces to zero. The  upper 3dB frequency for the input 1 circuit is fHi = and the upper 3dB 2pRthiCi frequency of the output circuit is

Ib hfeIb

Rs R

+

Ci

R′L

Co

Ro Ri

Vs −

Figure 12.5 Circuit of Figure 12.4 with transistor replaced by its approximate model

Rtho Rthi

− Ci

+

+

Vthi

fHo =

Co

Vtho

Figure 12.6 The simplified circuit

1 2pRthoCo

(12.3)

It is clear from the above discussion that the network parameters can influence the response of the amplifier.

12.4

HIGH-FREQUENCY EQUIVALENT CIRCUIT OF THE TRANSISTOR

To calculate the gain at high frequencies, the highfrequency equivalent circuit of the transistor should be drawn. Consider the transistor shown in Figure 12.7. Let us start drawing the high-frequency transistor model using Figure 12.7. Here, B is the external base lead and B′ is the internal base lead. Between these terminals, we have what is known as the base-spreading resistance rbb′, which is due to the resistance between the external base lead and the active region of the base and the resistance of the active base region. Also, in a transistor, the emitter is relatively highly doped and depending on the amount of doping, there exists a resistance between B′ and the emitter, that is rb ′ e and an interelectrode capacitance Cb ′ e. Further, the collector is lightly doped and between B′ and the collector,

Collector

r b′c r bb′ B

B′

Base

r b′e

Emitter

Figure 12.7 Transistor with its internal resistances

596

Electronic Devices and Circuits

there appears rb ′ c and an interelectrode capacitance Cb ′c. A relatively large resistance rce appears between the collector and emitter terminals. If Vb ′ e is the voltage between B′ and emitter, then gmVb ′ e is the collector current. The equivalent circuit is shown in Figure 12.8. This circuit is also called Giacoletto model or hybrid p model of the transistor. rb′c = 1/gb′c rbb′

Ic

B′

B Base

Collector Ib

Cb′e = Ce rb′e

+

+

Vb′e

Cb′c = Cc rce = 1/gce

Vce

gmVb′e

= 1/gb′e

−

− Emitter

Figure 12.8 The high-frequency model of the transistor

12.5

CALCULATION OF HIGH-FREQUENCY PARAMETERS IN TERMS OF THE LOW-FREQUENCY PARAMETERS

The low-frequency parameters of a transistor are already calculated around an operating point and are listed in Table 6.1. We now try to calculate the high-frequency parameters of the transistor.

12.5.1 The Transconductance, gm Consider the transistor circuit in Figure 12.9. Under ac conditions, the collector is shorted to ground. It has been noted earlier that the collector current in the active region is given by I C = I CO + a o I E

(12.4)

I C − I CO = a o I E

(12.5)

or

where I CO is the leakage current and a o I E is the collector current. From Figure 12.8, I C = I E = gmVB ′E.

By definition, gm =

∂I C ∂VB ′E

IC VCE

From Eqn. (12.4),

r bb′ B

∂I E ∂I = ao E gm = a o ∂VB ′E ∂VE

(12.6)

B′ VCC

+

V B′E = V E

IE

−

since VB ′E = VE

Figure 12.9 Circuit to calculate gm

High-Frequency Transistor and FET Amplifiers

If re is the resistance of the emitter diode, re =

597

∂VE . Using Eqn. (12.6), ∂I E

gm =

ao re

(12.7)

But we also know that

I eV hV dI I = s = dV hVT hVT T

rf =

dV hVT = dI I

VT . I Hence for the emitter diode, and if h = 1, then rf =

re =

VT IE

(12.8)

where VT = kT q is the volt equivalent of temperature and at room temperature VT = 26 mV. Substituting Eqn. (12.8) in Eqn. (12.7), gm = a o

IE VT

(12.9)

Using Eqn. (12.5), gm =

I C − I CO I C I C ≈ = VT VT 26

(12.10)

since I CO > rb′e. Therefore, it is evident from Figure 12.8 that I b flows through rb′e. The short circuit collector current is given as follows:

598

Electronic Devices and Circuits

I c = gmVb′e = gm I b rb′e

(12.11)

hfe, the short circuit current gain is hfe =

Ic Ib

VCE

From Eqn. (12.11), hfe = gm rb′e Using Eqn. (12.10),

rb′e =

hfe hfeVT = gm IC

(12.12)

gm hfe

( 12.13)

or

g b ′e =

12.5.3 Feedback Conductance, gb′c hre is defined as the reverse voltage gain with the input open circuited. With I b = 0, the circuit of Figure 12.8 is as shown in Figure 12.10, since at low frequencies Ce and Cc behave as open circuits.

hre =

Vb′e rb′e = Vce rb′e + rb′c

From the above relation, hre ( rb′e + rb′c ) = rb′e Therefore, rb′e (1 − hre ) = hre rb′c Since hre > rb′e

12.5.4 The Base-Spreading Resistance, rbb′ hie is the input resistance with the output shorted. From Figure 12.8, if the output is shorted rb′c and rb′e are in parallel, but rb′c >> rb′e. Therefore, rb′c || rb′e = rb′e Hence, hie = rbb′ + rb′e

(12.16)

rbb′ = hie − rb′e

(12.17)

or

From Eqn. (12.12) and Eqn. (12.16), hie = rbb′ +

hfeVT hfeVT ≈ IC IC

(12.18)

600

Electronic Devices and Circuits

12.5.5 Output Conductance gce hoe is the output admittance, defined as the ratio of I c to Vce with input open circuited. With I b = 0, the circuit in Figure 12.8 is drawn as shown in Figure 12.11. From Figure 12.11, Ic

rb′c

B′

V Vce I c = ce + + gmVb′e rce rb′c + rb′e

(12.19)

+ rce rb′e

Also with I b = 0,

Vce

gmVb′e

−

Vb′e = hreVce

(12.20) Figure 12.11 Circuit to calculate gce

Substituting Eqn. (12.20) into Eqn. (12.19), Ic =

hoe =

Vce Vce + + gm hreVce rce rb′c + rb′e

(12.21)

Ic 1 1 = + + gm hre Vce rce rb′c + rb′e

(12.22)

But we know that rb′c >> rb′e. Therefore, Eqn. (12.22) is written as follows: hoe =

1 1 + + gm hre rce rb′c

Or hoe = gce + gb′c + gm hre

(12.23)

From Eqn. (12.13), we have gb′e = gm hfe , and therefore gm = hfe gb′e

(12.24)

From Eqn. (12.15), we have gb′c = gb′e hre , and therefore hre =

g b ′c g b ′e

(12.25)

From Eqs (12.24) and (12.25), g  gm hre = hfe gb′e  b′c  = hfe gb′c  g b ′e 

(12.26)

High-Frequency Transistor and FET Amplifiers

601

Substituting Eqn. (12.26) in Eqn. (12.23), hoe = gce + gb′c + hfe gb′c = gce + gb′c (1 + hfe ) ≈ gce + gb′c hfe

(12.27)

gce = hoe − gb′c hfe

(12.28)

From Eqn. (12.15), gb′c = gb′e hre and from Eqn. (12.13), gb′e = gm hfe g  gb′c = hre  m   hfe 

(12.29)

Substituting Eqn. (12.29) in Eqn. (12.28), g  gce = hoe − hfe hre  m  = hoe − hre gm  hfe 

(12.30)

From the above calculations, it can be noted that if the parameters of the transistor at low frequencies are known, it is possible to calculate the high-frequency parameters. The high-frequency model or the hybrid π model is valid for frequencies up to fT 3 , where fT is the frequency at which the short-circuit current gain is unity. Typical parameters at I C = 1.3 mA are gm = 50 mA/V, rbb′ = 0.1 kΩ, rb′e = 1 kΩ, rb′c = 4 MΩ, rce = 80 kΩ , Cc = 3 pF, and Ce = 100 pF.

12.6

CE SHORT-CIRCUIT CURRENT GAIN

The CE amplifier used at high frequencies is shown in Figure 12.12, and its high-frequency model is shown in Figure 12.13.

IL

+

Ib +

RL

Vce

Vi −

−

Figure 12.12 The CE amplifier at high frequencies

602

Electronic Devices and Circuits gb′c rbb′

Ic

B′

B

IL Ib

+

Ce

+ Cc

Vb′e

gb′e

gce

RL

gmVb′e

Vce

−

−

Figure 12.13 The equivalent circuit of Figure 12.12

To calculate of the short circuit current gain, short RL (Figure 12.14): gb′c rbb′

Ic

B′

B Ib

Ce

IL

+ Cc

Vb′e

gce

gb′e

RL= 0

gmVb′e −

Figure 12.14 The equivalent circuit with RL = 0

With RL = 0, Cc is in parallel with Ce. gb′c is small, and hence rb′c is large. Therefore, the current through it is negligible and is considered as an open circuit. Further, when RL = 0, gce = 0. Therefore, the resultant simplified equivalent circuit is shown in Figure 12.15. rbb′

B′

B

IL +

Ib

Vb′e gb′e = gm/hfe

Ce + Cc

gmVb′e

RL= 0

−

Figure 12.15 The simplified equivalent circuit

The load current I L is I L = − gmVb′e

(12.31)

I b = Vb′e  gb′e + jw (Ce + Cc )

(12.32)

Using Eqs (12.31) and (12.32), Ai =

− gmVb′e IL − gm = = I b Vb′e  gb′e + jw (Ce + Cc ) gb′e + jw (Ce + Cc )

(12.33)

High-Frequency Transistor and FET Amplifiers

603

Dividing by gb′e Ai =

− g m g b ′e jw (Ce + Cc ) 1+ g b ′e

(12.34)

From Eqn. (12.13), hfe =

gm g b ′e

(12.35)

Substituting Eqn. (12.35) in Eqn. (12.34), Ai =

− hfe = jw (Ce + Cc ) 1+ 1+ g b ′e

− hfe w  j  wb 

(12.36)

where wb =

g b ′e gm = (Ce + Cc ) hfe (Ce + Cc )

(12.37)

From Eqn. (12.36), Ai =

At f = f b , Ai = hfe

hfe  f  1+    fb 

2

(12.38)

2 = 0.707 hfe . Hence, fb is the bandwidth with RL = 0.

Calculation of fT: Let us now define fT as the frequency at which the short-circuit current gain of the CE amplifier becomes unity. That is, at f = fT , Ai = 1. We have from Eqn. (12.38), Ai =

1=

hfe  f  1+    fb  hfe  f  1+  T   fb 

2

2

604

Electronic Devices and Circuits

2

 f  1 +  T  = hfe  fb  Therefore, 2

 f  1 +  T  = hfe2  fb  2

 fT  2 2  f  = hfe − 1 ≈ hfe  b since hfe2 >> 1 Hence, fT = hfe or fT = hfe f b fb

(12.39)

Therefore, using Eqn. (12.37), we can write that fT = hfe f b =

hfe gm gm g = ≈ m 2p (Ce + Cc ) hfe 2p (Ce + Cc ) 2pCe

(12.40)

since Ce >> Cc From Eqn. (12.36) and Eqn. (12.39), Ai =

− hfe =  f  1+ j   1+  fb 

− hfe − hfe =  f   f  1 + jhfe   j  fT   fT   h  fe

(12.41)

We have to note that fT is an important parameter, and fT = hfe f b. We also note that fT represents the short-circuit current gain bandwidth. Here, hfe is the low-frequency current gain and fb the upper 3-dB frequency. Let us try to understand the relevance of fT.We have, f b = fT hfe . Let us take two transistors with same fT = 100 MHz. Let hfe of the first transistor be hfe1 = 10 , then fb 1 =

fT 100 = = 10 MHz. hfe1 10

fT 100 = = 12.5 MHz. hfe 2 8 Although transistors having the same fT are chosen, the bandwidth is different for the two of them. When larger bandwidth is desired, gain is sacrificed. Alternatively, if larger gain is the requirement, then bandwidth is to be sacrificed. Alternatively, let hfe of the second transistor be hfe2 = 8, then f b 2 =

High-Frequency Transistor and FET Amplifiers

Further, we know that fT =

605

gm g ≈ m 2p (Ce + Cc ) 2pCe

As gm is directly proportional to I C , the dc collector current, fT varies with I C . Variation of Ai with frequency is shown in Figure 12.16. Measurement of fT: fT can be, typically, 80–100 MHz. Therefore, to measure fT in the laboratory, it is required to have a signal generator that can deliver a constant input signal to the amplifier at 100 MHz and more and associated measuring instruments. Even if this sophisticated equipment is not available in the laboratory, it is possible to measure fT, with less sophisticated equipment usually available. Consider Figure 12.16. Choose a frequency,

½Ai½ hfe 0.707hfe ½Ai½ decreases linearly at 20dB/decade

½Ail½

1 0

fβ

f1

fT

f

Figure 12.16 Frequency vs short-circuit current gain of CE amplifier

f1, which is 5 to 10 times larger than fb . If fb is 2MHz, choose f1 = 10 MHz. It is presumed that at least this generator and associated measuring instruments are usually available. Now, measure Ai1 at f1. Beyond f b, it can be noted that the short-circuit current gain decreases linearly at the rate of 20dB/decade. We know that f1 Ai1 = fT × 1. Therefore, fT = f1 A i1 . If at f1 = 10 MHz, the measured value of Ai1 = 10, then fT = f1 A i1 = 10 × 10 = 100 MHz. Example 12.1 A transistor has hie = 2 kΩ, hfe = 50, IE = 2 mA, Cb′c= Cob = 3pF, and fT = 400 MHz at room temperature. Calculate gm, rb′e, rbb, and Cb′e. Solution: gm =

IC 2 × 10 −3 = 76.92 mA/V = VT 26 × 10 −3

rb ′ e =

hfe 50 = = 650 Ω gm 76.92

rbb ′ = hie − rb ′ e = 2000 − 650 = 1350 Ω gm 76.92 mA / V = = 30.62pF 2 p fT 2 × 3.14 × 400 × 106 Ce + Cc = Ce =

gm 2pfT gm − Cc = 30.62 − 3 = 27.62 pF 2p fT

606

Electronic Devices and Circuits

12.7

CE CURRENT GAIN WITH RESISTIVE LOAD

Let us now consider the CE current gain with resistive load (Figure 12.17). This circuit is redrawn in Figure 12.18 using the Miller’s theorem. gb′c rbb′

Ic

B′

B

IL Ib

Ce gb′e

+

+ Cc

Vb′e

gce

RL

Vce

gmVb′e −

−

Figure 12.17 The CE amplifier with resistive load rbb′

B′

B Ib

Ce gb′e

IL + Vb′e

gb′c (1-A)

Cc (1-A)

+

gb′c (A-1)/A

gmVb′e gce Cc (A-1)/A

RL

Vce −

−

Figure 12.18 Circuit of Figure 12.17, after using the Miller’s theorem

In order to simplify the circuit in Figure 12.18, the following assumptions are made: (i) In majority of the cases, the output time constant is very much smaller when compared to the input time constant. Hence, Cc ( A − 1) A ≈ Cc may be replaced by an open circuit. (ii) gb′c ( A − 1) A ≈ gb′c . Since gb′c t o, the upper half-power frequency, fH = f2 is decided by t i only, as shown in Eqn. (12.49). In general, if t i = RC , then f2 =

1 2pRC

(12.50)

In the circuit show in Figure 12.20, let a voltage source Vs with its internal resistance Rs drive the amplifier. Consider rbb′ and rb′e, as shown in Figure 12.21, and the circuit to calculate the input time constant, t i is shown in Figure 12.22. rbb′

B

B′

Rs

Cc (1+gmRL ) +

rb′e

Vs

+

gmVb′e

Vo

RL

Ce

−

−

Figure 12.21 Circuit with Vs driving the amplifier

rbb′

Cc (1+gmRL ) rb′e

R

Ce

C

Rs

Figure 12.22 Circuit to calculate t i

From Figure 12.22, R = ( Rs + rbb′ ) || rb′e =

(Rs + rbb′ ) rb′e = (Rs + rbb′ ) rb′e Rs + rbb′ + rb′e Rs + hie

(12.51)

and C = Ce + Cc (1 + gm RL ) ≈ Ce + Cc gm RL

(12.52)

since, gm RL >> 1. But, from Eqn. (12.40), gm ≈ 2pCe fT

(12.53)

C ≈ Ce + Cc 2pCe fT RL = Ce (1 + 2pfTCc RL )

(12.54)

Substituting Eqn. (12.53) in Eqn. (12.52),

609

High-Frequency Transistor and FET Amplifiers

From Eqs (12.51) and (12.54), t i = RC =

(Rs + rbb′ ) rb′e × C Rs + hie

e

(1 + 2pfTCc RL )

(12.55)

From Eqn. (12.50), f2 =

Rs + hie 1 = 2pRC 2p ( Rs + rbb′ ) rb′eCe (1 + 2pfTCc RL )

(12.56)

The mid-band gain is AVs =

− hfe RL Rs + hie

AVs =

hfe RL Rs + hie

(12.57)

From Eqs (12.56) and (12.57), the gain–bandwidth product is AVs f2 =

hfe RL h RL 1 = fe × × 2p ( Rs + rbb′ ) rb′eCe (1 + 2pfTCc RL ) rb′e ( Rs + rbb′ ) 2pCe (1 + 2pfTCc RL )

(12.58)

But it is known that, gm =

gm 2pCe (1 + 2pfTCc RL )

(12.59)

2pCe fT RL fT = × 2pCe (1 + 2pfTCc RL ) ( Rs + rbb′ ) (1 + 2pfTCc RL )

(12.60)

AVs f2 =

RL

hfe rb′e

(Rs + rbb′ )

×

But, from Eqn. (12.53), gm ≈ 2pCe fT AVs f2 =

RL

(Rs + rbb′ )

×

Similarly, when current gain is considered, the gain–bandwidth product is AIs f2 =

12.8

Rs

×

fT

(Rs + rbb′ ) (1 + 2pfTCc RL )

(12.61)

HYBRID p CAPACITANCES

Two capacitances Cc and Ce can be easily identified in the hybrid p model of the transistor.

12.8.1 The Collector Junction Capacitance Cc The collector junction capacitance Cc ( = Cb ′ c ) is the output capacitance in the CB configuration, with I E = 0 and is normally specified in the data sheet by the manufacturer as Cob. As the amplifier

610

Electronic Devices and Circuits

is operated in the active region, the collector–base diode (collector diode) is reverse biased. Under these conditions, Cc ( = Cob ) varies inversely as the reverse-bias voltage: Cc ∝

1

(VCE )

n

= (VCE )

−n

(12.62)

where n = 12 for an abrupt junction and n = 13 for a graded junction. Cc decreases as VCE increases and vice versa. However, variations in I C and temperature, T have no influence on capacitance, Cc

12.8.2 The Emitter Junction Capacitance Ce P

N

P

In the active region, the base–emitter diode (emitter p(0) diode) is forward biased and the base–collector (collector diode) is reverse biased. Therefore, Ce ( = Cb′e ) is the sum of the emitter diffusion capacitance, CD and the emitter junction capaciC tance, CJ. That is, Ce = CD + CJ ≈ CD , since CJ is small. E B p(W) Ce = CD is calculated as illustrated in Figure 12.23 that x=0 x=W depicts the emitter–base and base–collector junctions of a PNP transistor. The width of the base, W is very Figure 12.23 Emitter–base and base–collector junctions of a transistor small, typically of the order of 1 μ. = 10 −6 m .

(

)

The assumptions we make in trying to evaluate CD are (i) W ( Rs + rbb′ )Cc gm or CL >> gm ( Rs + rbb′ )Cc

(12.88)

616

Electronic Devices and Circuits

If for the given transistor, gm = 50 mA/V , Rs = 100 Ω, rbb′ = 200 Ω, and Cc = 3 pF, then from Eqn. (12.88): CL >> 50 × 10 −3 × (100 + 200 ) × 3 × 10 −12 Therefore, CL >> 45 pF If CL = 100 pF and Ce = 100 pF , then from Eqn. (12.83): (12.89)

fH = f T

The input circuit that enables us to calculate Vi is shown in Figure 12.27. Ri is the input resistance of the emitter follower which is large. rbb′ From Figure 12.27, Vi =

Vs Ri ≈ Vs Ri + Rs + rbb′

(12.90)

+ Rs

Ri +

Therefore, Ahs = Ah, where Ahs is the overall voltage gain.

Vs

Vi −

−

Gain × bandwidth = Am fH ≈ fH

Figure 12.27 Circuit to calculate Vi

12.10

CB AMPLIFIER AT HIGH FREQUENCIES

Let us now calculate the short-circuit current gain of the CB amplifier as shown in Figure 12.28. Its simplified high-frequency circuit is shown in Figure 12.29. Ic

Ie Ie

Ic

+ Vi

RL

C

B′

E

C

E

rb′e

+

+

Vo

Vi

−

−

rb′c RL rbb′

− B

B

Figure 12.28 CB amplifier rce Ie

Ic

E − Vb′e +

C

gmVb′e

rb′e Cb′e

Cb′c

rb′c

B′ rbb′ B

Figure 12.29 Circuit at high frequencies

RL

High-Frequency Transistor and FET Amplifiers

617

To calculate the short circuit current gain, set RL = 0 in Figure 12.29. The result is the equivalent circuit in Figure 12.30. rce Ie

Ic

E −

gmVb′e

rb′e

Vb′e

C

Cb′e

+

Cb′c

rb′c

RL = 0

B′ rbb′ B

Figure 12.30 Equivalent circuit with RL = 0

Let us now simplify the circuit in Figure 12.30. Cb′c = Cc is small, typically, 3pF, and hence is replaced by an open circuit as it offers high reactance in the frequency range of operation. With RL = 0, rbb, and rb′c are in parallel. Typically, rbb′ = 200 Ω and rb′c = 4 MΩ. Hence, rb′c can be replaced by an open circuit. Further, with RL = 0, rce is in parallel with hie ( = rbb′ + rb′e ) . Typically, hie = 1.1 kΩ and rce = 80 kΩ. Hence, rce can be considered to be an open circuit. These approximations result in the simplified circuit shown in Figure 12.31. Ie

Ic

E −

gmVb′e

rb′e

Vb′e

Cb′e

+

C

RL = 0

B′ rbb′ B

Figure 12.31 Simplified equivalent circuit

From Figure 12.31, I c = − gmVb′e

(12.91)

Let Z be the parallel combination of rb′e and Cb′e. Then, Vb′e = − ( I e + gmVb′e ) Z

(12.92)

or Vb′e (1 + gm Z ) = − I e Z −I e =

Vb′e (1 + gm Z ) 1  = Vb′e  gm +   Z Z

(12.93)

618

Electronic Devices and Circuits

However, 1 rb′e jwCb′e rb′e 1 Z = rb′e || = = 1 jwCb′e r + 1 + jwrb′eCb′e b ′e jwCb′e

(12.94)

Substituting Eqn. (12.94) in Eqn. (12.93),  1 + gm rb′e + jwrb′eCb′e   1 + jwrb′eCb′e  1  − I e = Vb′e  gm +  = Vb′e  gm + = Vb′e     Z rb′e rb′e     1 + gm rb′e + jwrb′eCb′e  I e = −Vb′e   rb′e 

(12.95)

I c = − gmVb′e

(12.96)

and

Ai, the short-circuit current gain in the CB configuration, using Eqs (12.95) and (12.96), is Ai =

Ic = Ie

− gmVb′e gm rb′e =  1 + gm rb′e + jwrb′eCb′e  1 + gm rb′e + jwrb′eCb′e −Vb′e   rb′e 

(12.97)

But from Eqn. (12.12), gm rb′e = hfe

(12.98)

Substituting Eqn. (12.98) in Eqn. (12.97),

Ai =

hfe 1 + hfe + jwrb′eCb′e

where

hfe 1 + hfe hfb = = jwrb′eCb′e f 1+ j 1+ fa 1 + hfe

(12.99)

hfe 1 + hfe

(12.100)

1 + hfe 2prb′eCb′e

(12.101)

hfb = and fa =

Ai =

hfb  f  1+    fa 

2

(12.102)

At f = fa , Ai = hfb 2. Therefore, fa is the upper half-power frequency. fa can also be expressed differently. From Eqn. (12.101), fa can be written down as follows:

619

High-Frequency Transistor and FET Amplifiers

1 + hfe

fa =

2prb′eCb′e

hfe hfe

(12.103)

But from Eqn. (12.98), rb′e 1 = hfe gm

(12.104)

Substituting Eqn. (12.104) in Eqn. (12.103), fa =

g (1 + hfe ) 1 + hfe gm gm = m = = h hfe 2pCb′e hfb 2pCb′e hfe 2pCb′e fe 2pCb′e gm (1 + hfe )

(12.105)

fa can be expressed also in another different form. From Eqn. (12.101), fa =

1 + hfe 2prb′eCb′e

Multiplying both numerator and denominator in Eqn. (12.101) by 1 2prb′eCb′e (1 + hfe ) 1 2prb′eCb′e fa = 1 1 + hfe

(12.106)

h 1 = 1 − fe = 1 − hfb 1 + hfe 1 + hfe

(12.107)

But

Also, from Eqn. (12.39), fb ≈

1 2prb′eCb′e

(12.108)

Substituting Eqs (12.107) and (12.108) in Eqn. (12.106), fa =

fb 1 − hfb

(12.109)

Example 12.2 A transistor has gm = 25 millimhos , rbb’ = 200 Ω, hie = 5.2 kΩ, Cb’c = 10 pF , Cb’e = 65pF, and hfe = 100 . Calculate fa , fb , and unity gain bandwidth product of CE amplifier.

620

Electronic Devices and Circuits

Solution: We have rb’e = hie − rbb’ = 5.2 − 0.2 = 5 kΩ. fa =

1 + hfe 1 + 100 = = 49.49MHz 2p Cb’e rb’e 2p × 65 × 10 −12 × 5 × 103

fb =

1 1 = = 0.425MHz 2p rb’e (Cb’e + Cb’c ) 2p (65 + 10 )10 −12 × 5 × 103

fT = hfe f b = unity gain bandwidth product = 100 × 0.425 = 42.5MHz

12.11

HIGH-FREQUENCY FET CIRCUITS

Let us consider the behavior of an FET at high frequencies. At low frequencies, we have neglected the effect of the interelectrode capacitances. However, their influence is to be considered when we talk of an FET amplifier at high frequencies. The low frequency equivalent of an FET (either JFET or MOSFET) is already considered in Chapter  7. The equivalent circuit at high frequencies is obtained by simply considering the interelectrode capacitances also as shown in Figure 12.32.

Cgd

G

D

+ gmVi

Vi

rd

Cgs

Cds

− S

Figure 12.32 High-frequency equivalent circuit of FET

12.11.1 CS Amplifier at High Frequencies Consider the small-signal CS amplifier at high-frequency amplifier shown in Figure 12.33 and its equivalent circuit as shown in Figure 12.34. VDD ZL

+

gmVi rd

Cgs

Vo Vi

D

+ Vi

+ +

Cgd

G

ZL

Vo

Cds

−

−

−

S

Figure 12.33 CS amplifier

Figure 12.34 Equivalent circuit

Corollaries of Thévenin’s and Norton’s theorems are widely used to simplify network analysis. If V is the open-circuit voltage and I the short-circuit current, and if Z (or Y) is the impedance (or admittance) between the two terminals 1 and 2 (Figure 12.35), then the open-circuit voltage short-circuit current theorem implies that 1

1

Z +

I= V Z

V −

Z

2

(a) Thévenin circuit

2 (b) Norton circuit

Figure 12.35 Thévenin’s circuit in (a) is replaced by a Norton circuit in (b)

High-Frequency Transistor and FET Amplifiers

Z=

       

V I

V = VY Z I V = IZ = Y I=

621

(12.110)

where V is the open-circuit voltage and I is the short-circuit current as shown in Figure 12.35. Hence, to find out the output voltage Vo , of the CS amplifier in Figure 12.34, we need to calculate Z and I . To calculate Z, set Vi = 0. When Vi = 0, then gmVi = 0. That is, the current is zero. Hence, replace the current source by an open circuit. Hence, to calculate Z, set Vi = 0, Figure 12.36. The resultant circuit is shown in Figure 12.37. Cgd

G

D

+ Set Vi = 0

gmVi

Vi

rd

Cgs

ZL

Cds

− S

Figure 12.36 Circuit to calculate Z D

gmVi = 0

rd

Cgd

ZL

Cds S Z

Figure 12.37 Circuit of Figure 12.36 with Vi set to zero

From Figure 12.37, 1 = YL + Yds + Ygd + gd (12.111) Z 1 1 where YL = , Yds = jwCds , Ygd = jwCgd , and gd = . ZL rd Having calculated Z, we now calculate I. To calculate I, short D and S in Figure 12.34. The resultant circuit is shown in Figure 12.38. Y=

G

Cgd

D

I

+ gmVi

Vi

Short D and S rd

Cgs

ZL

Cds

− S

Figure 12.38 Circuit to calculate I

622

Electronic Devices and Circuits Cgd

From Figure 12.38, Vi is seen to appear across Cgd . The simplified circuit is as shown in Figure 12.39. From Figure 12.39, writing down the KCL equation at node X

(

I = − gmVi + VY i gd = Vi − g m + Ygd

)

+

Vi

I

X

D

− gmVi

(12.112) S

(i) Voltage gain: The voltage gain AV is

Figure 12.39 Simplified circuit

AV =

Vo IZ I = = Vi Vi YVi

(12.113)

Substituting Eqs (12.111) and (12.112) in Eqn. (12.113), AV =

(

Vi − gm + Ygd

)

(

Vi YL + Yds + Ygd + gd

(−g

=

) (Y

L

m

+ Ygd

)

+ Yds + Ygd + gd

(12.114)

)

At low frequencies, the interelectrode capacitances are neglected. Hence, Ygd = Yds = 0. Therefore, Eqn. (12.114) reduces to AV =

(

(

Vi − gm + Ygd

)

Vi YL + Yds + Ygd + gd

=

− gm

) (YL + gd )

=

− gm rd ZL − gm = = − gm ZL′  1 1  ( rd + ZL )  Z + r  L

(12.115)

d

where ZL′ = ZL || rd

(12.116)

Equation (12.115) gives the gain of the CS amplifier at low frequencies. (ii) Input admittance: From the circuit in Figure 12.34, there is no isolation between the input and the output. Cgd appears between the input and the output. By using the Miller’s theorem, Ygd can be replaced by two admittances Y1 andY2: Y1 in shunt with the input terminals and Y2 in shunt with the output terminals. G

 A − 1 Y1 = Ygd (1 − AV ) and Y2 = Ygd  V   AV 

+

(12.117)

Y1 = Ygd (1-Av)

Vi Ygs −

The input circuit of Figure 12.34, using Eqn. (12.117), is as shown in Figure 12.40. From Figure 12.40, Yi = Ygs + Ygd (1 − AV )

S

Yi

(12.118)

Figure 12.40 Circuit to calculateYi

623

High-Frequency Transistor and FET Amplifiers

The Miller capacitor that appears at the input terminals, Ci, using Eqn. (12.118) is Ci =

Yi = Cgs + Cgd (1 − AV ) jw

(12.119)

We know that AV = − gm RL’ , where RL’ = rd / / RD , and Eqn. (12.119) is written as follows: Ci = Cgs + Cgd (1 + gm RL′ )

(12.120)

The input capacitance Ci is seen to be large and as the frequency increases its reactance decreases. If the output of a CS amplifier with load RL is connected to the input of this amplifier, the effective load decreases at high frequencies, thereby reducing the gain. (iii) Output admittance: From Figure 12.34, to calculate Yo, open ZL and set Vi = 0. Then, gmVi = 0. That is, open the current source. The admittance seen between the output terminals is Yo . Since AV is large, D

Cgd

AV − 1 ≈ Cgd AV

(12.121) rd

Cgd Cds

The output circuit to determine Yo is shown in Figure 12.41. From Figure 12.41,

S Yo

(12.122)

Yo = Ygd + Yds + gd

Figure 12.41 Circuit to calculateYo

12.11.2 Common Drain Amplifier at High Frequencies The CD amplifier is also known as the source follower. Consider the CD amplifier circuit in Figure 12.42. The high-frequency equivalent circuit is presented in Figure 12.43. VDD

+

G

+ Vi RS −

+

+

Vo

Vi

Figure 12.42 CD amplifier or source follower

−

Cgs S + gmVgs

Csn

Cgd

− N

Vgs

rd

RS

Vo

Cds

−

− D

N

Figure 12.43 Equivalent circuit

To calculate Z, for the circuit in Figure 12.43, set Vi = 0 as shown in Figure 12.44. With Vi = 0, the current gmVgs is zero. Hence, open the current source. The simplified equivalent circuit is as shown in Figure 12.45. Csn is a stray capacitance.

624

Electronic Devices and Circuits

+

Vgs

−

Cgs

G

S

+

+ gmVgs

Vi

Set Vi = 0

Csn

Cgd

rd

RS

Vo

Cds

−

− D

N

Figure 12.44 Circuit to calculate Z

S

Cgs

S

Csn

gmVgs

rd

RS

CT

rd

RS

Cds D

N

N Y

Figure 12.45 Simplified circuit to calculate Z

From Figure 12.45, Y = Ygs + Yds + Ysn + gd + gS where gd =

(12.123)

1 1 , gS = ,Ygs = jwCgs ,Yds = jwCds , andYsn = jwCsn rd RS

Let YT = Ygs + Yds + Ysn

(12.124)

Y = YT + gd + gS

(12.125)

Then

From Eqn. (12.124),

(

jwCT = jw Cgs + Cds + Csn

)

or CT = Cgs + Cds + Csn

(12.126)

625

High-Frequency Transistor and FET Amplifiers

To calculate I, short S and N terminals in Figure 12.43. The resultant circuit is shown in Figure 12.46 +

G

Vgs

−

Cgs

I

S

+ gmVgs

Vi

Csn

Cgd

rd

Short S and N

RS

Cds

− D

N

Figure 12.46 Circuit to calculate I

The simplified circuit is as shown in Figure 12.47 From Figure 12.47,

Cgs +

(12.127)

I = gmVgs + YgsVi

Vi

S

I

− Short S and N

gmVgs

From Figure 12.43, D

(12.128)

Vgs = Vi − Vo

N

Figure 12.47 Simplified circuit

Substituting Eqn. (12.128) in Eqn. (12.127),

(

)

I = gmVgs + YgsVi = gm (Vi − Vo ) + YgsVi = Vi gm + Ygs − gmVo

(12.129)

(i) Voltage gain: Vo = IZ =

(

)

I Vi gm + Ygs − gmVo = YT + gd + gS Y

(

Vo (YT + gd + gS + gm ) = Vi gm + Ygs

AV =

gm + Ygs Vo = = Vi YT + gd + gS + gm

gm + jwCgs 1 jwC T + g d + g m + RS

=

(12.130)

)

(g

m

)

+ jwCgs Rs

1 + Rs ( jwCT + gd + gm )

(12.131)

Equation (12.131) gives the gain of the CD amplifier at high frequencies. At low frequencies, since Ygs = YT = 0, Eqn. (12.131) reduces to AV = In practice, AV < 1.

gm RS gm ≈ 1 + RS ( gd + gm ) gm + gd

(12.132)

626

Electronic Devices and Circuits

(ii) Input Admittance: To calculate the input admittance, Yi, Cgs is replaced by Miller’s capacitor on the input side as shown in Figure 12.48.

G + Vi

Y1 = Ygs (1-Av)

Ygd

From Figure 12.48, −

Yi = Ygd + Ygs (1 − AV )

(12.133)

N

Yi

Figure 12.48 Circuit to calculateYi

Since AV ≈ 1, Eqn. (12.133) reduces to

(12.134)

Yi = Ygd = jwCgd S

(iii) Output admittance: To calculate Yo, in Figure 12.43, open RS and set Vi = 0. Then gmVi = 0. That is, open the current source. The admittance seen between the output terminals is Yo . The output circuit to determine Yo is shown in Figure 12.49.

gd

CT

From Figure 12.49,

D Yo

(12.135)

Yo = YT + gd

Figure 12.49 Circuit to calculate Yo

Additional Solved Examples Example 12.3 At room temperature, the following parameters are listed for a silicon transistor: IC = 1.3 tmA and VCE = 10 V. hie = 2000 Ω, hoe = 25 × 10 −6 , hfe =60 and

hre = 2 × 10 −4

It is also known that fT = 100 MHz

and

Calculate the values of the hybrid p parameters. Solution: (i) gm =

I C 1.3 × 10 −3 = 0.05 A / V = VT 26 × 10 −3

(ii) rb’e =

hfe 60 = = 1200 Ω gm 0.05

(iii) rbb’ = hie − rb’e = 2000 − 1200 = 800 Ω (iv) rb’c = gb’c =

rb’e 1200 = = 4.8 M Ω hre 2.5 × 10 −4 1 = 0.21µmhos 4.8 × 106

Cob = 3pF

High-Frequency Transistor and FET Amplifiers

627

−6 −6 −6 (v) gce = hoe − hfe gb ′ c = 25 × 10 − 60 × 0.21 × 10 = 12.4 × 10 mhos

rce =

(vi)

1 1 = = 80.65 kΩ gce 12.4 × 10 −6

gm 0.05A / V = = 79.6 pF 2p fT 2 × 3.14 × 100 × 106 Ce + Cc =

Therefore,

Ce =

gm 2p fT

Cc = Cob = 3pF

gm − Cc = 79.6 − 3 = 76.6 pF 2p fT

Example 12.4 A CE amplifier has the short-circuit current gain Ai = 10 at 20 MHz. The transistor used has hfe = 50. Find fb and fT. Solution: We have 2

Ai =

hfe  f  1+    fb 

2

10 =

 20  50 =5 1+   = 10  fb 

50  20  1+    fb 

2

2

 20  1 +   = 25  fb 

f b2 =

400 = 16.67 24

f b = 4.08MHz

fT = hfe f b = 50 × 4.08 = 204 MHz

Example 12.5 A CE amplifier is used at high frequencies. The transistor is operated at IC = 2 mA and has hfe = 100. C e = 37pF and Cc = 3 pF. Determine f b and fT . Solution: gm =

IC 2 = = 0.077 A / V VT 26 fb =

Ce + Cc = 37 + 3 = 40 pF

gm 0.077 = = 3.065 MHz 2p (Ce + Cc ) hfe 2p × 40 × 10 −12 × 100

fT = hfe f b = 100 × 3.065 = 306.5 MHz

628

Electronic Devices and Circuits

Example 12.6 The short-circuit current gain of a CE amplifier is 15 at f = 150 KHz. f b = 0.25 MHz. Find the unity gain bandwidth. Solution: We have Ai =

15 =

hfe  f  1+    fb 

2

hfe  150  1+   250 

2

2

 150  hfe = 15 × 1 +  = 15 × 1.17 = 17.55  250  fT = hfe f b = 17.55 × 0.25 = 4.39 MHz

Example 12.7 A CE amplifier is operated with RL = 1kΩ . At room temperature, the following parameters are listed for a silicon transistor: I C = 2.5 mA and VCE = 10 V . hie = 1500 Ω, hfe = 50. It is also known that fT = 500 MHz and Cob = 3 pF . Calculate fH and the mid-band voltage gain considering Rs = 1kΩ.

Solution: gm =

I C 2.5 = = 0.096 A / V VT 26 rb’e =

hfe 50 = = 520 Ω gm 0.096

rbb’ = hie − rb’e = 1500 − 520 = 980 Ω gm 0.096 = = 30.57 pF 2pfT 2p × 500 × 106 Ce =

gm − Cc = 30.57 − 3 = 27.57 pF 2pfT

C = Ce + Cc (1 + gm RL ) = 27.57 + 3 (1 + 0.096 × 1000 ) = 318.57 pF fH =

1 1 = = 0.96 MHz 2pCrb’e 2p × 318.57 × 10 −12 × 520

A = gm RL = 0.096 × 1000 = 96 Rs′ = Rs + rbb’ = 1000 + 980 = 1980Ω Avs = A ×

rb’e 520 = 96 × = 19.97 1980 + 520 Rs′ + rb’e

High-Frequency Transistor and FET Amplifiers

629

Example 12.8 A transistor is operated at IC = 2.6 mA and has hie = 1000 Ω, rbb’ = 200 Ω and Ce = 50 pF . Cc is negligible. Find (a) fT, (b) fb , (c) Ai at 5 MHz and at 50 MHz. Solution: gm =

I C 2.6 = = 0.1 A / V VT 26 rb’e = hie − rbb’ = 1000 − 200 = 800 Ω hfe = gm rb’e = 0.1 × 800 = 80

(i)

fT =

gm 0.1 = = 318.47 MHz 2pCe 2p × 50 × 10 −12

(ii)

fb =

fT 318.47 = = 3.98 MHz hfe 80

(iii)

At f = 5 MHz Ai =

hfe  f  1+    fb 

2

=

80  5  1+   3.98 

2

= 49.69

and at f = 50 MHz Ai =

hfe  f  1+    fb 

2

=

80  50  1+   3.98 

2

= 6.35

Example 12.9 For the CE amplifier shown in Figure 12.50, the transistor is operated at IC = 1.46 mA. RC = R3 = 3 kΩ , R1 = 20 kΩ , R2 = 5 kΩ , Rs = 500 Ω , hie = 2 kΩ , hfe = 50, Ce = 100 pF , Cc = 5 pF . Find the gain at f = 100 kHz and also determine fH. VCC = 20 V

RC R1 +

Cc Cc

Rs

R3

Vo

+ Vs

R2

CE

RE −

−

Figure 12.50 CE amplifier at high frequencies

630

Electronic Devices and Circuits

Solution: The simplified equivalent circuits are as shown in Figures 12.51 and 12.52. B

rbb′

B′

Rs +

+

gmVb′e

C R

RL

Vs

rb′e

Vo −

−

Figure 12.51 Simplified circuit B

rbb′

B′

R′s +

+

gmVb′e

C

RL

V ′s

rb′e

Vo −

−

Figure 12.52 Simplified circuit of Figure 12.51 using Thévenin’s theorem

RL = RC / / R3 = gm =

rb’e =

3×3 = 1.5 kΩ 3+3

R = R1 / / R2 =

20 × 5 = 4 kΩ 20 + 5

I C 1.46 = = 56.15 mA / V 26 VT

hfe 50 = = 893 Ω gm 0.056

rbb’ = hie − rb’e = 2000 − 893 = 1107 Ω C = Ce + Cc (1 + gm RL ) = 100 + 5(1 + 56.15 × 1.5 ) = 100 + 421 = 521pF 1 1 = = 3.06 kΩ 2pfC 2p × 100 × 103 × 521 × 10 −12 Z = rb’e / / Vs’ =

1 = 0.893 / /3.06 = 0.69 kΩ 2pfC

R 4000 × Vs = = 0.89Vs R + Rs 4000 + 500

Vb’e = Vs’ ×

Rs’ = Rs / / R =

690 Z = 0.89Vs × = 0.31Vs 440 + 1107 + 690 Rs’ + rbb’ + Z

0.5 × 4 = 0.44 kΩ 0.5 + 4

High-Frequency Transistor and FET Amplifiers

V0 = − gmVb’e RL = − gm × 0.31Vs RL

(

Avs =

631

Vo = − 0.31 × 56.15 × 1.5 = −26.11 Vs

)

Req = Rs’ + rbb’ / / rb’e = ( 440 + 1107 ) / /893 = 566.18 Ω fH =

1 1 = = 0.54 MHz 2pReqC 2p × 566.18 × 521 × 10 −12

Example 12.10 A transistor with IC = 1.5 mA is used as a high-frequency CE amplifier. hie = 1.1 kΩ, rbb’ = 0.1kΩ , Ce = 150 pF , and Cc = 5 pF . Calculate fH, when (i) RL = 0 and (ii) RL = 2 kΩ. Solution: rb’e = hie − rbb’ = 1.1 − 0.1 = 1kΩ gm =

I C 1.5 = = 57.69 mA / V VT 26

(i) When RL = 0, C = Ce + Cc = 150 + 5 = 155 pF fH =

1 1 = = 1.03 MHz 3 2p rb ′eC 2p × 1 × 10 × 155 × 10 −12

(ii) When RL = 2 kΩ, C = Ce + Cc (1 + gm RL ) = 150 + 5(1 + 57.69 × 2 ) = 150 + 115.38 = 731.9 pF fH =

1 1 = = 217.56 kHz 2prb ′ eC 2p × 1 × 103 × 731.9 × 10 −12

Example 12.11 A CE amplifier shown in Figure 12.53 has RC = 1 kΩ and RL = 1 kΩ. IC = 1.3 mA, hfe = 60, rbb′ = 300 Ω, Cc = 3 pF, and fT = 400 MHz. If it is required to have a bandwidth of 5 MHz, find Rs. VCC Solution: gm =

I C 1.3 = = 50 mA / V VT 26

rb’e =

hfe 60 = = 1200 Ω gm 0.05

hie = rbb’ + rb’e = 300 + 1200 = 1500 Ω

RC +

Cc Rs R3

Vo

+

1×1 RL = RC / / R3 = = 0.5 kΩ 1+1 Cc (1 + gm RL ) = 3 (1 + 50 × 0.5) = 78 pF

Vs −

Figure 12.53 CE amplifier with resistive load

632

Electronic Devices and Circuits

Ce =

gm 50 × 10 −3 = 19.9 pF = 2pfT 2p × 400 × 106

C = Ce + Cc (1 + gm RL ) = 19.9 + 78 = 97.9 pF Req =

Req =

1 1 = = 325.3 Ω 6 2pfHC 2p × 5 × 10 × 97.9 × 10 −12

(Rs + rbb’ ) rb’e Rs + rbb’ + rb’e

325.3 =

(Rs + 300)1200 Rs + 300 + 12200

Rs = 146 .1Ω

Example 12.12 A CE amplifier with RL = 1 kΩ has fH = 2 MHz. The transistor has gm = 37.5 mA/V, hfe = 75, rbb′ = 200 Ω, Cc = 5 pF, and fT = 200 MHz. Calculate (i) Rs that gives fH = 2 MHz and (ii) AVs with Rs calculated in (i). Solution: (i) rb’e =

hfe 75 = = 2000 Ω gm 37.5 hie = rbb’ + rb’e = 200 + 2000 = 2200 Ω

Cc (1 + gm RL ) = 5 (1 + 37.5 × 1) = 192.5 pF Ce + Cc =

gm 37.5 × 10 −3 = 29.86 pF = 2pfT 2p × 200 × 106

Ce = (Ce + Cc ) − Cc = 29.86 − 5 = 24.86 pF C = Ce + Cc (1 + gm RL ) = 24.86 + 192.5 = 217.36 pF Req =

Req = (ii)

1 1 = = 366.29 Ω 6 2pfHC 2p × 2 × 10 × 217.36 × 10 −12

(Rs + rbb’ ) rb’e Rs + rbb’ + rb’e

AVs =

366.29 =

(Rs + 200) 2000 Rs + 200 + 20000

Rs = 248.41 Ω

− hfe RL −75 × 1000 = = −30.63 Rs + hie 248.41 + 2200

h R Example 12.13 The mid-band gain of a CE amplifier with resistive load is given as AVs = fe L Rs + hie g RL 1 and fH = . Verify that AVs fH = m × . 2pReqC 2pC Rs + rbb ′

High-Frequency Transistor and FET Amplifiers

633

Solution: We have

(Rs + rbb’ ) rb’e

Req =

Rs + rbb’ + rb’e 1 1 =  (R + r ) r   (R + r ) r  2pC  s bb ′ b ′ e  2pC  s bb ′ b ′ e   Rs + rbb ′ + rb ′ e   Rs + hie 

∴ fH =

since hie = rbb ′ + rb ′ e AVs = AVs fH =

hfe RL Rs + hie hfe RL × Rs + hie

hfe RL 1 =  (Rs + rbb ′ ) rb ′ e  2pC (Rs + rbb ′ ) rb ′ e 2pC    Rs + hie 

But hfe = gm rb ′ e ∴ AVs fH =

gm rb ′ e RL g RL = m × 2pC ( Rs + rbb’ ) rb’e 2pC Rs + rbb ′

Example 12.14 A silicon PNP transistor has fT = 200 MHz, DB = 15 cm2/sec. What is the thickness of the base? Solution: We have fT =

gm 2pCe

and

Ce ( = CD ) = g m ×

W2 2DB

Therefore, fT =

gm 2

2pgm ×

W=

W 2DB

=

DB pW 2

W2 =

DB pfT

DB 15 = = 0.155 × 10 −3 cm pfT p × 200 × 106

Example 12.15 A PNP transistor operated at room temperature has a base width of 1.5 × 10 −4 cm , DB =15 cm2/sec and a dc collector current of 2.6 mA. Find (i) CD and (ii) fT.

634

Electronic Devices and Circuits

Solution:

gm =

I C 2.6 = = 100 mA / V VT 26

(

−3 −4 W 2 100 × 10 × 1.5 × 10 CD = g m × = 2DB 2 × 15

fT =

2

)

= 75 pF

gm 100 × 10 −3 = = 212.31 MHz 2pCD 2p × 75 × 10 −12

Example 12.16 A Germanium NPN transistor is used as a CE amplifier at high frequencies (Figure 12.54). Determine (i) gm, (ii) rb ′ e, (iii) hie, (iv) rb ′ c, (v) rce, (vi) Ce, and (vii) Avs at 100 kHz, given that rbb′ = 200 Ω, hfe = 75, hre = 2 × 10 −4, hoe = 25 × 10 −6 mhos, fT = 200 MHz, and Cc = 3 pF. VCC = 12 V 2.2 RC 100

R1

+

Cc 2.2

Cc

Rs

Vo

R3

500 100

+ R2

Vs

CE

RE 4.7 −

−

Figure 12.54 CE amplifier at high frequencies

Solution: To calculate IC, the dc circuit is shown in Figure 12.55. From Figure 12.55, V2 = VCC ×

R2 100 = 12 × = 6V 100 + 100 R1 + R2 VCC = 12 V

For the transistor to be in the active region, for the Ge transistor, VBE = 0.2 V. Therefore, VE = V2 − VBE = 6 − 0.2 = 5.8 V . R1

V 5.8 Hence, I E = I C = E = = 2.15 mA . RE 2.7 (i)

gm =

(ii) rb ′ e =

I C 2.15 = = 82.69 mA / V 26 VT hfe 75 = = 907 Ω gm 82.69 × 10 −3

2.2 RC

IC 100

+

+ VBE −

V2

100 R2

−

+

IE

VE RE 2.7 −

Figure 12.55 DC circuit to calculate IC

High-Frequency Transistor and FET Amplifiers

635

(iii) hie = rbb ′ + rb ′ e = 200 + 907 = 1107 Ω rb ′ e 907 = = 4.54 MΩ hre 2 × 10 −4 1 gb ′ c = = 0.22 m mhos 4.54 × 106 (v) gce = hoe − hfe gb’c = 25 × 10 −6 − 75 × 0.22 × 10 −6 = 8.5 × 10 −6 mhos (iv) rb ′ c =

1 1 = = 117.65 kΩ gce 8.5 × 10 −6 g 82.69 × 10 −3 = 65.84 pF (vi) Ce = m = 2pfT 2 × 3.14 × 200 × 106 2.2 × 2.2 (vii) RL = RC / / R3 = = 1.1kΩ 2.2 + 2.2 C = Ce + Cc (1 + gm RL ) = 65.84 + 3(1 + 82.69 × 1.1) = 65.84 + 275.9 = 341.74 pF rce =

1 1 = = 4.66 kΩ 3 2pfC 2p × 100 × 10 × 341.74 × 10 −12 1 Z = rb ′ e / / = 0.907 / /4.66 = 760Ω 2pfC 100 × 100 R = R1 / / R2 = = 50 kΩ 100 + 100 R 50 V s′ = × Vs = = 0.99Vs R + Rs 50 + 0.5

Rs′ = Rs / / R =

0.5 × 50 = 0.495 kΩ 0.5 + 50

Z 760 = 0.99Vs × = 0.517Vs 495 + 200 + 760 R ′s + rbb + Z V Vo = − gmVb’e RL = − gm × 0.517Vs RL Avs = o = −0.517 × 82.69 × 1.1 = −47.02 Vs

Vb ′ e = V s′ ×

Example 12.17 A transistor is operated at IC = 2.6 mA. rbb’ = 200Ω , hie = 1200 Ω , Cb’c = 10 pF . W = 1.25 × 10 −4 cm, DB = 10 cm2/sec. Calculate (i) gm, (ii) rb ′ e, (iii) hfe, (iv) Ce, (v) fa , (vi) fb , and (vii) fT . Solution: I C 2.6 = = 100 mA / V VT 26

(i)

gm =

(ii)

rb’e = hie − rbb’ = 1200 − 200 = 1kΩ

(iii) hfe = rb’e gm = 1 × 103 × 100 × 10 −3 = 100

(

−3 −4 W 2 100 × 10 × 1.25 × 10 (iv) CD = Ce = gm × = 2DB 2 × 10

(v)

fa =

2

)

= 78.13 pF

1 + hfe 1 + 100 = = 205.85 MHz 2pCb ′ e rb ′ e 2p × 78.13 × 10 −12 × 1 × 103

636

Electronic Devices and Circuits

1 1 = = 1.81 MHz 2prb ′ e (Cb’e + Cb ′ c ) 2p (78.13 + 10 )10 −12 × 1 × 103

(vi)

fb =

(vii)

fT = hfe f b = Unity gain bandwidth product = 100 × 1.81 = 181 MHz

Example 12.18 Consider the high-frequency amplifier shown in Figure 12.56. The amplifier is required to satisfy the following requirements: S ≤ 5, fL = 20 Hz, fH = 100 kHz, AVs (min) = −35, Rs = 0.5 kΩ The transistor used has rbb’ = 300 Ω, rb’e = 2000 Ω, Cc = 5 pF, Ce = 500 pF, and gm = 50 mA / V.

(

)

The amplifier is driven by a signal vs = 70.71 × 10 −3 sin 2p × 10 × 103 t . Design the circuit. VCC

RL R1 Cc Cc

Rs

Vo

+ R2

Vs

+

RE

CE

−

−

Figure 12.56 CE high-frequency amplifier

hfe = gm rb’e = 50 × 10 −3 × 2 × 103 = 100

Solution:

hie = rbb ′ + rb ′ e = 300 + 2000 = 2300 Ω (i) Selection of RL Given:

AVs (min) = 35

AVs (min) = RL =

hfe RL Rs + hie

35 =

hfe RL Rs + hie

35 ( Rs + hie ) 35 × 2.8 = = 0.98 kΩ hfe 100

Choose RL = 1.5 kΩ, as the gain will have to be more than 35. With RL = 1.5 kΩ, AVs =

hfe RL 100 × 1.5 = 53.57 = Rs + hie 0.5 + 2.3

(ii) Selection of RE: Vsm = 70.71mV Therefore, the maximum output swing is Vm = AVs × 70.71 = 53.57 × 70.71 = 3.79 V

High-Frequency Transistor and FET Amplifiers

Assuming, V

CE(sat )

637

≈ 0 , as the swing is symmetric with respect to VCE VCC = 2VCE = 2 × 3.79 = 7.58 V

Choose VCC = 9 V Then VCE = 4.5 V Usually, RE is chosen such that the drop across it, V 9 VE ≈ CC = = 0.9 V 10 10 The voltage drop VL , across RL is VL = VCC − VCE − VE = 9 − 4.5 − 0.9 = 3.6 V ∴ IE = IC =

VL 3.6 = = 2.4 mA RL 1.5

Hence, RE =

VE 0.9 = = 375 Ω I E 2.4

(iii) Selection of Req : C = Ce + Cc (1 + gm RL ) = 500 + 5(1 + 50 × 1.5 ) = 880 pF Req =

1 1 = = 1.81kΩ 2pfHC 2p × 0.1 × 106 × 880 × 10 −12

This means that to have fH = 100 kHz , Req = 1.81kΩ . Hence, in practice, to get the desired bandwidth, Req < 1.58 kΩ. Let us calculate Req from the given data. R = R1||R2. Req = ( Rs / / R ) + rbb’  / / rb’e ≈ ( Rs + rbb’ ) / / rb’e = ( 0.5 + 0.3) / /2 = 0..570 kΩ Req < 1.58 kΩ Hence, it is possible to get the desired bandwidth. (iv) Selection of R1 and R2 S=

5=

1 + hFE  RE  1 + hFE   RE + R  1 + 100  375  1 + 100   375 + R 

 375  101 1 + 100  = = 20.2  375 + R  5 375 = 0.192 375 + R

638

Electronic Devices and Circuits

375 = 1953 0.192 R = 1953 − 375 = 1578 Ω

375 + R =

V2 = VE + 0.6 = 0.9 + 0.6 = 1.5 V R2 R1 + R2

V2 = VCC 1+

R1 VCC 9 = = =6 R2 V2 1.5 R1 = 5 Or R1 = 5R2 R2

But, R =

R1R2 5R2 R2 5R = = 2 R1 + R2 5R2 + R2 6

1578 =

5R2 6

R2 = 1.2 × 1578 = 1.89 kΩ

R1 = 5R2 = 5 × 1.89 = 9.45 kΩ (v) Selection of CE: RE 375 = = 37.5 Ω 10 10 1 = 212.31 mF CE = 2p × 20 × 37.5

For CE to be a bypass condenser, at f = 20 Hz, X CE ≈ 1 = 375Ω 2pfCE (vi) Selection of Cc:

Ri = R / / hie = 1.578 / /2.3 = 936 Ω Cc =

1 1 = = 8.51 mF 2p fRi 2p × 20 × 936

The designed amplifier circuit is shown in Figure 12.57. 9V

1.5 5 µF +

R1

10

RL +

Cc

Cc 500

Rs

Vs

+

Vo R2

2

200 µF + CE

RE 375

−

Figure 12.57 The designed CE amplifier

−

High-Frequency Transistor and FET Amplifiers

639

Example 12.19 For the circuit designed in example 12.18, determine (i) fH and (ii) AVs at 10kHz. (i) C = Ce + Cc (1 + gm RL ) = 500 + 5(1 + 50 × 1.5 ) = 880 pF Req = ( Rs / / R ) + rbb’  / / rb’e 0.5 × 1.58 = 0.38 kΩ 0.5 + 1.58 Rs’ + rbb’ = 0.38 + 0.3 = 0.68 kΩ Rs’ = Rs / / R =

(

)

Req = Rs’ + rbb’ / / rb’e = fH =

(ii)

0.68 × 2 = 0.51kΩ 0.68 + 2

1 1 = = 345.8 kHz 2pReqC 2p × 0.51 × 103 × 880 × 10 −12

1 1 = = 18.09 kΩ 3 2pfC 2p × 10 × 10 × 880 × 10 −12 1 = 2 / /18.09 = 1.8 kΩ Z = rb’e / / 2pfC R = R1 / / R2 = Vs′ =

R 1.67 × Vs = Vs = 0.77Vs R + Rs 1.67 + 0.5

10 × 2 = 1.67 kΩ 10 + 2 0.5 × 1.67 Rs′ = Rs / / R = = 0.385 kΩ 0.5 + 1.67

Z 1.8 = 0.77Vs × = 0.558Vs 0.38 + 0.3 + 1.8 Rs′ + rbb ′ + Z V Vo = − gmVb’e RL = − gm × 0.558Vs RL AVs = o = −0.558 × 50 × 1.5 = −41.85 Vs Vb ′ e = Vs′ ×

Example 12.20 A CS amplifier using an FET is connected to a resistive load RL = 100 kΩ. For the FET, rd = 50 kΩ, gm = 2 mA / V, Cgs = 3.5 pF , Cds = 1pF, and Cgd = 3 pF. Calculate the voltage gain and the input capacitance at (i) 200 Hz and (ii) 200 kHz. Solution: The expression for AV is AV =

− gm + Ygd YL + Yds + gd + Ygd

(i) At f = 200 Hz, Ygd = jwfCgd = j × 2p × 200 × 3 × 10 −12 = j 3.768 × 10 −9 mhos Yds = jwfCds = j × 2p × 200 × 1 × 10 −12 = j1.256 × 10 −9 mhos

640

Electronic Devices and Circuits

gd = YL =

1 1 = = 20 × 10 −6 mhos rd 50 × 103

1 1 = = 10 × 10 −6 mhos RL 100 × 103

YL + gd + Ygd + Yds = (20 + 10 )10 −6 + j (3.768 + 1.256 )10 −9 AV =

− gm + Ygd YL + Yds + gd + Ygd

=

−2 × 10 −3 + j 3.768 × 10 −9 −2000 = = −66.67 30 30 × 10 −6 + j 5.024 × 10 −9

since the j terms are very small, RL′ = rd / / RL =

50 × 100 = 33.33kΩ 50 + 100

The input capacitance, Ci is

(

)

(

)

Ci = Cgs + 1 + gm RL′ Cgd = 3.5 + 1 + 2 × 10 −3 × 33.33 × 103 × 3 = 206.48 pF (ii) At f = 200 kHz, Ygd = jwfCgd = j × 2p × 200 × 103 × 3 × 10 −12 = j 3.768 × 10 −6 mhos Yds = jwfCds = j × 2p × 200 × 103 × 1 × 10 −12 = j1.256 × 10 −6 mhos YL + gd + Ygd + Yds = (20 + 10 )10 −6 + j (3.768 + 1.256 )10 −6 AV =

- gm +Ygd YL +Yds + gd +Ygd

AV =

=

-2 ´ 10 -3 + j 3.768 ´ 10 -6 30 ´ 10 -6 + j 5.024 ´ 10 -6

−2000 + j 3.768 30 + j 5.024

Multiplying the numerator and the denominator by the complex conjugate of (30 + j 5.024 ), AV =

=

( −2000 + j 3.768) (30 − j 5.024) (30 + j 5.024) (30 − j 5.024) ( −2000 × 30 + 3.768 × 5.024) + j (2000 × 5.024 + 3.768 × 30)

= −64.82 + j10.98

900 + 25.24

Taking only the real part of the gain, the input capacitance, Ci is Ci = Cgs + (1 − AV )Cgd = 3.5 + (1 + 64.82 ) × 3 = 200.96 pF

High-Frequency Transistor and FET Amplifiers

641

Summary • If C′ is a capacitor connected between the input and the output terminals of an amplifier, then the Miller capacitance in shunt with the input terminals is CMi = C ′ (1 − A) and the Miller capacitance in shunt with the output terminals is CMo = C ′

( A − 1) . A

I I • The transconductance is g m ≈ C = C VT 26 • The input conductance is g b′e =

gm hfe

• The base-spreading resistance is rbb′ = hie − rb′e gm hfe • The high-frequency model or the hybrid p model is valid for frequencies up to fT 3, where fT is the frequency at which the short-circuit current gain is unity. • The output conductance is g b′c = hre

• When the short-circuit current gain is calculated in the CE mode, then the upper half-power frequency is f b and fT = hfe f b . • When the current gain with resistive load is calculated, fH is the half-power frequency • The collector junction capacitance Cc ( = C b′c ) is the output capacitance in the CB configuration, with I E = 0 and is normally specified in the data sheet by the manufacturer as Cob . • The emitter junction capacitance, Ce is the sum of the emitter diffusion capacitance, CD and the emitter junction capacitance, CJ .

multiple ChoiCe QueStionS 1. If the capacitor connected between the input and the output terminals of an amplifier is C ′ = 10 pF, and A = 100, then the Miller capacitance in shunt with the input terminals is (a) 10 µF (c) 1.01 nF

(b) 1 µF (d) 1.01 µF

2. If the capacitor connected between the input and the output terminals of an amplifier is C ′ = 10 pF, and A = 100, then the Miller capacitance in shunt with the output terminals is (a) 10 pF (c) 1 µF

(b) 10 µF (d) 1.01 nF

3. If IC = 1.3 mA, then g m is (a) 50 mA/V (c) 25 mA/V

(b) 100 mA/V (d) 200 mA/V

4. If hie = 2 kΩ and rb′e is 1 kΩ, then rbb′ is (a) 1 kΩ (b) 10 kΩ (c) 100 kΩ (d) 1 MΩ 5. If fT = 265 MHz (a) 30 pF (c) 3 pF

and g m = 50 mA/V , then Ce is (b) 300 pF (d) ∞

642

Electronic Devices and Circuits

6. If f b = 1 MHz and hfe = 100, then fT is (a) 10 MHz (b) 100 MHz (c) 1GHz (d)  7. rb’e (a) (b) (c) (d)

is proportional to the dc bias current through it inversely proportional to the dc bias current through it constant none of the above

8. rb’c is typically of the order of (a) 1 kΩ (c) 100 kΩ 9.

(b) 10 kΩ (d) 100 MΩ

fT is the frequency at which the short-circuit current gain of CE configuration is (a) 1 (b) 10 (c) 100 (d) 

10. fb is the frequency at which the short-circuit current gain of CE configuration is (a) 1 (b) 10 (c) 100 (d) 0.707 times the mid-band gain

Short anSwer QueStionS 1. A capacitor C ′ exists between the input output terminals of a CE amplifier. What are the values of the Miller capacitances that appear in shunt with the input and the output terminals? 2. What is base-spreading resistance? 3. What is the b − cut-off frequency of a BJT? 4. What is fT of a BJT? 5. What is the relationship between f b and fT ? 6. What is the relation between fa and f b ?

long anSwer QueStionS 1. Draw the hybrid p model of the transistor and obtain the relations that enable you to calculate the high-frequency parameters in terms of the low-frequency parameters. 2. Obtain the expression for the short-circuit current gain of CE amplifier and define the frequencies f b and fT . Obtain the interrelationship between f b and fT . 3. Obtain the expression for the current gain with resistive load for a CE amplifier and define the frequency fH . 4. Draw the high-frequency equivalent circuit of the CS amplifier and derive the expressions for the voltage gain, input impedance, and the output impedance. 5. Draw the high-frequency equivalent circuit of the CD amplifier and derive the expressions for the voltage gain, input impedance, and the output impedance.

W

High-Frequency Transistor and FET Amplifiers

643

unSolved problemS 1. A CE amplifier uses a transistor having hfe = 50, rbb’ = 200 Ω, and g m = 100 mA / V . The internal resistance of the voltage source driving the amplifier is 1 kΩ and the load resistance is 1 kΩ. fT = 500 MHz. Determine the mid-band gain taking Rs also into account and the upper 3-dB frequency. 2. A PNP transistor operated at room temperature has a base width of 1.25 × 10 −6 m, DB =15 × 10 −4 m 2 / sec and a dc collector current of 2.5 mA. Find (i) Ce and (ii) fT 3. A BJT biased at IC = 5 mA, VCE = 5 V, produces the hybrid parameters as hie = 1.0 kΩ, hre = 10−4, hfe = 50, and hoe = 24 × 10−6 A/V, having fT = 50 MHz with Cb’c=Cob = 2 pF. Obtain the hybrid π parameters. 4. The mid-band current gain of a CE amplifier is 20 at 10 MHz. The low-frequency parameters of the transistor are hie = 1.5 kΩ, hre = 10−4, hfe = 100, and hoe = 24 × 10−6 A/V. Determine the b-cut-off frequency and unity gain bandwidth.

.

5. A transistor is operated at IC = 5 mA. rbb’ = 200 Ω, hie = 1200 Ω , C b’c = 10 pF. W = 1.25 × 10 −6 m, D = 0 −6 m, DB =10 ×10 −4 m / sec . Calculate (i) g m , (ii) rb’e , (iii) hfe , (iv) Ce , (v) fa , (vi) f b , and (vii) fT . 6. A CS amplifier using an FET is connected to a resistive load RL = 50 kΩ. For the FET, rd = 50 kΩ , g m = 2 mA / V, Cgs = 3.5 pF, Cds = 1pF , and Cgd = 3 pF . Calculate the voltage gain and the input capacitance at 100 Hz.

1

13

TUNED AMPLIFIERS

Learning objectives After going through this chapter, the reader will be able to ˆ ˆ ˆ ˆ ˆ ˆ

13.1

Realize the need for tuned amplifiers Understand the difference between small-signal and large-signal tuned amplifiers Appreciate the difference between single-tuned, stagger-tuned and synchronously tuned double-tuned voltage amplifiers Calculate the gain and bandwidth of these different tuned amplifiers Understand the working of a class-C tuned power amplifier Understand the principle of frequency compensation in wideband amplifiers.

INTRODUCTION

We have seen that common-emitter amplifiers have large voltage and current gain. The voltage gain in a common-emitter amplifier is given as A = AI (RL Ri ), where RL is the load resistance and Ri is the input resistance. The load resistance RL cannot be made very large to make gain large, so as to satisfy the biasing requirements. These amplifiers also have reasonably large bandwidth, since the gain is not excessively large. However, consider a radio transmitter, in which amplitude modulation (AM) is used for signal transmission. In such a case, at the input of the radio receiver, we have a narrow band of frequencies (audio frequencies) with the carrier as the center frequency. The bandwidth of an AM transmitter is typically 10 kHz. The signal strength at the input of the radio receiver is typically of the order of a few microvolts. The strength of the signal will have to be raised to such a level so as to be able to drive an electromechanical device such as a loud speaker. Hence, the voltage amplifiers (RF and IF amplifiers) are required to give a large gain with narrow bandwidth. The impedance of a parallel-tuned circuit is maximum at resonance and the tuned-circuit offers only a negligible dc resistance. Hence, biasing problems are taken care of, and at the same time large gain can be achieved in a single stage with resultant narrow bandwidth, which essentially is the requirement. Therefore, tuned amplifiers are used where there is a need to derive a large gain with narrow bandwidth. The frequency–impedance and frequency–current curves of series and parallel resonant circuits are shown, respectively, in Figures 13.1 and 13.2.

Tuned Amplifiers

I

Z R

I

645

I

+ V

L Z C fo

0

f

Figure 13.1 Series resonant circuit and its response

Z Z I I +

L

V

C R

I

0

fo

f

Figure 13.2 Parallel resonant circuit and its response

As the parallel resonant circuit offers large impedance at resonance, this is used as load to derive the largest possible gain in a single stage. At resonance, X L = X C or w o L = 1 w oC . Therefore, fo =

1

(13.1)

2p LC

Here fo is the resonant frequency of the tank circuit. Ideally, the requirement is that the response should be flat in a limited frequency range and should fall off rapidly as shown in Figure 13.3. Ideal response

A

Practical response

0

f1

fo

f2

f

Figure 13.3 Ideal and practical responses of tuned amplifiers

646

Electronic Devices and Circuits

But in practice, the practical response differs from the desired ideal response. We consider three types of tuned voltage amplifiers: (i) single-tuned capacitance coupled voltage amplifier, (ii) synchronously tuned double-tuned voltage amplifier, and (iii) stagger-tuned voltage amplifier. A single-tuned voltage amplifier is one in which there is only one tuned circuit, tuned to a desired resonant frequency. A synchronously tuned double-tuned amplifier is one in which there are two tuned circuits, and both the tuned circuits are tuned to the same center frequency. The response can be varied by adjusting the coupling between the coils. A stagger-tuned amplifier is one in which there are two tuned circuits. However, each of these tuned circuits is tuned to two different frequencies, and these two center frequencies are separated by bandwidth of a single-tuned amplifier.

13.2

QUALITY FACTOR, Q OF L AND C

The response of a resonant circuit becomes sharp, that is, highly selective, or relatively flat depending on the value of Q, the figure merit of the tank circuit. Consider a practical inductance, L, as shown in Figure 13.4, in which R is the series resistance and CP is the distributed capacitance of the winding of the inductance. This tells that an inductance can have a self-resonant frequency. If the inductance is used below its self-resonant frequency, then CP, which usually is very small, can be omitted. R is normally specified by the manufacturer by specifying Q, the quality factor. The quality factor Q is defined as the ratio of the energy stored in the inductor in one cycle to the energy dissipated in one cycle. Q=

v wL Energy stored in one cycle = L = R Energy dissipated in one cycle vR

wL 2p × 10 × 106 × 10 × 10 −6 = = 6.28 Ω. Q 100 Thus, when L and R are in series, Q = wL R. If L and R are in parallel, then Q = R wL. If L = 10 µH , Q = 100 at f = 10 MHz, then R =

+ I

R vR − + L

R

L

vL −

(a) R and L in series

(b) R and L in parallel

Figure 13.4 A practical inductor

Alternatively, a practical capacitance may be represented as in Figure 13.5. For a capacitor C, to calculate the effective series resistance R, the dissipation factor, which is the reciprocal of Q is usually specified by the manufacturer. R 1 Energy dissipated in one cycle vR = = = wRC = vC 1 wC Q Energy stored in one cyclee

Tuned Amplifiers

647

The quality factor defined for a series and a parallel circuit is expressed in the following ways: 1 (for a series circuit) wRC

Q=

(13.2)

Q = wRC (for a parallel circuit)

(13.3)

Readers are advised to take special note of Eqs (13.2) and (13.3) that can normally create confusion. Q=

Energy stored in one cycle Energy dissipated in one cycle

(13.4)

However, there is no change in the original definition as expressed in Eqn. (13.4) from which the previous two equations have been obtained. + R vR − +

I

C

R

vC

C

− (a) C and R in series

(b) C and R in parallel

Figure 13.5 A practical capacitor

13.3

SINGLE-TUNED CAPACITIVE-COUPLED VOLTAGE AMPLIFIER

A two-stage single-tuned amplifier, using transistors, is shown in Figure 13.6 in which a single stage is identified. Ri is the input resistance of the second stage. VCC L

L C

C R

R1

R

R1

Cc

Cc Q1

Cc

+

Q2 +

+ Vs

R2

Vo RE

−

CE

Vo2

R2 RE

− Single stage

Figure 13.6 A two-stage single-tuned amplifier

CE −

648

Electronic Devices and Circuits

A tuned amplifier is an RF amplifier. As such Cc and CE being large condensers, ideally behave as short circuits. R1 and R2 are large and can be replaced by open circuits. The ac circuit of a single stage is shown in Figure 13.7. The high-frequency equivalent circuit of Figure 13.7 is given in Figure 13.8. Using the Miller’s theorem, rb ′c and Cb ′c are replaced as shunt elements on the input and the output side. The resultant circuit is as shown in Figure 13.9.

Q1

+

L C

Vo

Ri

R + Vs

−

−

Figure 13.7 AC circuit of the single-tuned amplifier

r b′c C

B′

B

+

+

r bb′

C b′e

r b′e

+

C b′c

V b′e Vs

Vo

L C

Ri

R

gce

gm V b′e

−

−

−

Figure 13.8 Equivalent circuit of Figure 13.7

B

B r bb′ Vs +

C + C wi

+ C b′e

r b′cA/(A−1)

= 1/hoe

C wo

Vo L

r b′e

C C b′c (1−A) r b′c/ (1−A)

−

gce

−

gm V b′e

R

Ri

C b′c (A−1)/A

−

Figure 13.9 Circuit of Figure 13.8, when Miller’s theorem is used

Tuned Amplifiers

649

To simplify the circuit, let Cs = Cb ′e + Cwi + Cb ′c (1 − A) and C′=

Cb ′c ( A − 1) A

+ Cwo + C

Also gce = 1 hoe = Ro and rb ′ c is considered as an open circuit. Then the circuit in Figure 13.9 reduces to that in Figure 13.10. B′

B

C +

r bb′

+ R

+

gm V b′e

V b′e

Vs

r b′e

L

Cs R o = 1/hoe

−

C′

Vo Ri

− −

Figure 13.10 Simplified circuit of Figure 13.9

To simplify the circuit further, let us replace the series combination of R and L as a parallel combination, as worked out in the following mathematical analysis: Z L = R + j wL YL =

YL =

1 1 R − j wL R − j wL = = = 2 ZL R + jwL (R − jwL ) (R + jwL ) R + w 2 L2

R − j wL R − j wL R wL = + = + R 2 + w 2 L2 R 2 + w 2 L2 R 2 + w 2 L2 R 2 + w 2 L2 j R 2 + w 2 L2

(

)

YL =

1 1 + Rp jwLp

(13.5)

Rp =

R 2 + w 2 L2 R

(13.6)

where

and Lp =

R 2 + w 2 L2 R2 = +L ≈L w 2L w 2L

(13.7)

650

Electronic Devices and Circuits

R2 > Rs . But from Figure 13.18, I = − gmVbe1. Consequently, we have V = IZ = − gmVbe1

R11  R  M 1 +  11     R22   L1 

2

(13.50)

2

(13.51)

Using Eqs (13.49) and (13.50), jwL1I1 = − gmVbe1

R11  R  M 1 +  11     R22   L1 

Hence,

Vbe1

2

 R  M 1 +  11     R22   L1  = − jwL1I1 gm R11

(13.52)

and (13.53)

Vbe2 = jwMI1 The gain A, therefore, is A=

Vbe 2 jwMI1 =− Vbe1 jwL1I1

gm R11  R  M 1 +  11     R22   L1 

2

=−

gm R11 (M L1 )  R  M 1 +  11     R22   L1 

2

(13.54)

The effective value of Q is Qe1 and is Qe1 =

Rp wL1

=

(R11

wL1 )

 R  M 1 +  11     R22   L1 

2

(13.55)

and that at resonance is Qe1 =

(R11

w o L1 )

 R  M 1 +  11     R22   L1 

2

(13.56)

Mutual impedance M controls Qe1 which in turn controls the bandwidth. By optimizing the value of M , the gain can be maximized. On the other hand, we interpret it as M can be used to control the bandwidth. To get the maximum value of A, we differentiate Eqn. (13.54), with respect to M and equate it to zero to get the optimum value of M . Then substitute this value of M in Eqn. (13.54).

660

Electronic Devices and Circuits

From Eqn. (13.54), A= −

gm R11 (M L1 )  R  M 1 +  11     R22   L1 

2

2  2M R  dA   R11   M    − gm R11  M  = 1 +  gm R11  2 11  = 0 + dM   R22   L1    L1  L1  L1 R22   

  R   M  2   2M 2 R  11 − 1 +  11     +  2  =0   R22   L1    L1 R22  2

2

 R  M  R  M −  11    + 2  11    = 1  R22   L1   R22   L1  or 2

 R11   M   R   L  = 1 22

1

R  M 2 = L12  22   R11  R22 R11

M o = L1

(13.57)

Substituting Eqn. (13.57) in Eqn. (13.54), A(max) =

gm R11R22 2

(13.58)

Substituting Eqn. (13.57) in Eqn. (13.56), R11 w o L1 1 R11 1 Qe1 = = = = Q1 2 2 2 w o L1 2  R  M 1 +  11     R22   L1  R11 w o L1

(13.59)

where Q1 is the Q of the primary circuit. As the Q is halved the bandwidth increased by a factor 2. Thus, the main advantage of the tuned primary amplifier is that the bandwidth is twice the bandwidth of a single-tuned amplifier. The capacitance C1 is normally made larger to neglect the effect of stray capacitances. The limitation is that the value of L1 becomes small.

Tuned Amplifiers

13.6

661

INDUCTIVELY COUPLED TUNED SECONDARY FET AMPLIFIER

An FET has a high input resistance. When FET is used as a frequency selective circuit, it is possible that for impedance matching, the tuned circuit is placed at the input of the amplifier that is in the secondary of the coupling network (Figure 13.21). The output from the previous stage is connected to the input of the FET amplifier. 1

I

M

I1 rd

2 I2

L2

L1

RL Vgs2

gmVgs1

C2

2

1

Figure 13.21 Tuned secondary FET amplifier

The equivalent circuit of Figure 13.21 is shown in Figure 13.22. I = −gmVgs1 L1 − M

1

L2 − M

R2 2

+

+

V11

rd

M

I2

C2 Vgs2

I1 −

− 2

1

Figure 13.22 Equivalent circuit of Figure 13.21

R2 is the resistance associated with L2. Writing the loop equations: V11 = jwL1I1 − jwMI 2  0 = R2 +  At resonance w o L2 =

 1  j  wL2 −  I 2 − jwMI1 wC2   

1 . Substituting this condition in Eqn. (13.61), w oC2 0 = R2 I 2 − jw o MI1

(13.60) (13.61)

662

Electronic Devices and Circuits

Hence, I2 =

jw o MI1 R2

(13.62)

Substituting Eqn. (13.62) in Eqn. (13.60),   jw MI  w 2M 2  V11 = jw o L1I1 − jw oM  o 1  = I1  jw o L1 + o R2   R2   Z11 =

(13.63)

w 2M 2 V11 = jw o L1 + o I1 R2

(13.64)

I1 flows through Z11. To find out the value of I1, consider the equivalent circuit in Figure 13.23. From Figure 13.23, I1 = I

rd rd + Z11

(13.65)

I = −gmVgs1 1

Using Eqn. (13.64), +

1 =I I1 = I 2 2 jw L w 2 M 2 w M 1+ o 1 + o rd + jw o L1 + o R2 rd rd R2 rd

(13.66)

V11

rd

Z11 I1

As the primary is untuned, rd >> w o L1, Eqn. (13.66) reduces to I1 = I But

1 w o2 M 2 1+ rd R2

−

(13.67)

1

Figure 13.23 Circuit to calculate I1

I = − gmVgs1

(13.68)

Substituting Eqn. (13.68) in Eqn. (13.67), I1 = I

1 1 = − gmVgs1 w o2 M 2 w o2 M 2 1+ 1+ rd R2 rd R2

(13.69)

Substituting Eqn. (13.69) in Eqn. (13.62),     jw o MI1 jw o M 1  − gmVgs1  = I2 = R2 R2  w o2 M 2  1+  rd R2 

(13.70)

Tuned Amplifiers

663

From Figure 13.22 and using Eqn. (13.70),

Vgs 2

    −g w M −j − j jw oM 1 1 m o  − gmVgs1 = = Vgs1 I2 = 2 2 w oC2 w oC2 R2  w o R2C2 w oM  w o2M 2 1 + 1 +  rd R2 rd R2 

A=

Vgs 2 Vgs1

=

− gmw o M w o R2C2

1 w 2M 2 1+ o rd R2

(13.71)

But Q2 =

w L 1 = o 2 w o R2C2 R2

(13.72)

Using Eqn. (13.72), A=

− gmw o M w o R2C2

Q2 1 = − gmw o M 2 2 w M w 2M 2 1+ o 1+ o rd R2 rd R2

(13.73)

We may want to derive the maximum gain or a desired bandwidth. In either case, we are required to adjust M . To find A(max), we differentiate Eqn. (13.73), with respect to M and equate it to zero to get the optimum value of M . Then substitute this value of M in Eqn. (13.73) to get A(max).  2w o2 M  dA  w o2 M 2  = 1 + − g w Q g w MQ + =0 ( ) 2  m o 2 m o rd R2  dM   rd R2   w 2M 2   2w o2M 2  − 1 + o + =0 rd R2   rd R2   w o2 M 2 =1 rd R2

w o M o = R2 rd

(13.74)

The optimum value of M is Mo =

R2 rd wo

(13.75)

664

Electronic Devices and Circuits

Substituting Eqn. (13.74) in Eqn. (13.73), A(max) = − gmw o M o

− gm rd R2 Q2 Q2 Q2 = − gm R2 rd = 2 2 Rr 2 w M 1+ 2 d 1+ o r R rd R2 d 2

(13.76)

Define the effective value of Q, that is Qe2 as follows: Qe 2 =

Q2 w 2M 2 1+ o rd R2

(13.77)

Substituting Eqn. (13.74) in Eqn. (13.77), Qe 2 =

Q2 Q = 2 rd R2 2 1+ rd R2

(13.78)

Bandwidth is fo f 2f = o = o Qe 2 Q2 2 Q2

(13.79)

From Eqn. (13.79) it can be noted that the bandwidth is twice the bandwidth of the resonant circuit. This result is similar to that in the tuned primary amplifier.

13.7

IMPEDANCE ADJUSTMENT WITH TAPPED CIRCUITS

A tuned circuit is shown in Figure 13.24, in which there is a tap on the inductor. The total inductance L is L = L1 + L2 ± 2M . Resistor Ri is the input resistance of the next stage. The parallel combination of ( L2 ± M ) and Ri is resolved into a series combination of ( L2 ± M ) and Rs as shown in Figure 13.25.

L1 ± M L1 ± M

C

C L2 ± M L2 ± M

Ri Rs

Figure 13.24 Tuned circuit, with a tap on the inductor

Figure 13.25 Circuit of Figure 13.24, with Ri replaced by Rs

Tuned Amplifiers

665

Here, we know that Rs is given by the following equation: 2

w 2 ( L2 ± M )

Rs =

(13.80)

Ri

Once again, the series resistance Rs can be replaced by a parallel resistance Rp as shown in Figure 13.26. Rp =

w 2 L2 Rs

(13.81) 1

Using Eqn. (13.80),

L1 ± M C

L2 w 2 L2 w 2 L2 Ri Rp = = = 2 Rs w 2 ( L2 ± M ) (L2 ± M )2 Ri

Rp

(13.82)

L2 ± M

1

We thus see that a resistance Ri at a tap on L can be replaced by a resistance Rp connected in shunt with the terminals 1–1 (Figure 13.26). Now consider the amplifier circuit in Figure 13.27.

Figure 13.26 Circuit of Figure 13.25, with Rs replaced by Rp

1

L1 L Q1

M

C

Rp

Q2

L2 1

Ri

Figure 13.27 Amplifier, with tapped inductance in the resonant circuit

Ri is a small input resistance appearing across the tuned circuit. Consequently, the Q of the circuit becomes smaller, and hence the bandwidth becomes larger than desired. When the input of Q2 is connected to a tapped tuned circuit, Ri gets transformed into Rp in parallel with the tank circuit. Rp is a large resistance, and hence the Q of the circuit becomes large;therefore, the bandwidth reduces to the desired value. In fact, Rp can be adjusted by adjusting the tap on the inductance. Hence, the Q of the tank circuit can be adjusted, which in turn controls the bandwidth. Alternately, Ri can be connected across a tapped capacitance to manipulate with the Q of the circuit, and hence can be used to derive the necessary bandwidth as shown in Figure 13.28.

666

Electronic Devices and Circuits 1 C1 L

Rp

Q1

Q2 C2

1 Ri

Figure 13.28 Amplifier, with tapped capacitance in the resonant circuit

When C and R are connected in parallel, they can be replaced by a series circuit (Figure 13.29). To find out the values of Rs and Cs , let us calculate YL of the parallel circuit. YL =

ZL =

ZL =

where Rs =

1 + jwRiC2 1 + j wC 2 = Ri Ri

Ri (1 − jwRiC2 ) Ri Ri jwRi2C2 = = − 1 + jwRiC2 (1 + jwRiC2 ) (1 − jwRiC2 ) 1 + (wRiC2 )2 1 + (wRiC2 )2

Ri 2

(wRiC2 ) 1

(wC2 )2 Ri

−

jwRi2C2 2

(wRiC2 )

=

1 2

(wC2 )

+ Ri

1 1 = Rs + j wC 2 j wC 2

and Cs = C2. The resultant tuned circuit of Figure 13.28 is shown in

Figure 13.29. Now replacing Rs by Rp, results in the circuit in Figure 13.30.

C1

L

C2

C1

Rp

L

C2

Rs

Figure 13.29 Tank circuit of Figure 13.28, with Rs in series with the capacitor combination

Figure 13.30 Tuned circuit of Figure 13.29, with Rs replaced by Rp

Tuned Amplifiers

Rp =

1

(wC )2 Rs

=

1 2

 CC  w  1 2  Rs  C1 + C2  2

Rp

=

(C1 + C2 )2   1 wCC   2  (wC2 ) Ri  2

2 1

2 C1 + C2 ) ( R =

2 2

C12

2 C1 + C2 ) ( R =

C12

667

i

(13.83)

i

Thus, by adjusting the tap on C, Rp can be controlled, which in turn controls Q and hence the bandwidth.

13.8

DOUBLE-TUNED AMPLIFIERS

Double-tuned amplifiers are further classified as (i) synchronously tuned amplifiers and (ii) stagger-tuned amplifiers.

13.8.1 Synchronously Tuned Double-Tuned Amplifier A synchronously tuned double-tuned amplifier has two mutually coupled tuned circuits, and both the tuned circuits are tuned to the same center frequency. The resultant response of this amplifier is almost a near flat response in limited frequency range of interest. The double-tuned amplifier usually finds application in radiofrequency (RF) and intermediate frequency (IF) amplifiers in radio receivers. Before we actually take up the analysis of the double-tuned amplifier, let us first obtain the expression for transfer admittance that can be used subsequently.

Calculation of the Transfer Admittance Consider the two-port network shown in Figure 13.31. We can write the KVL equations pertaining to the input and output ports using the z-parameters. I1

I2 +

+ V1

Network

V2

ZL

−

−

Figure 13.31 Two-port network

V1 = Zi I1 + Zr I 2

(13.84)

V2 = Zf I1 + Zo I 2

(13.85)

V2 = − I 2 ZL

(13.86)

From Figure 13.31,

668

Electronic Devices and Circuits

Substituting Eqn. (13.86) in Eqn. (13.85), − I 2 ZL = Zf I1 + Zo I 2 or −Zf I1 = (Zo + ZL ) I 2 or I1 = −

(Zo + ZL ) I Zf

(13.87)

2

Substituting Eqn. (13.87) in Eqn. (13.84),  (Zo + ZL )    Zr Zf − Zi (Zo + ZL )  Zi (Zo + ZL )  V1 = Zi I1 + Zr I 2 = Zi  − I 2  + Zr I 2 = I 2  Zr −  = I2   Zf Zf Zf       YT =

I2 Zf Zf = = V1 Zr Zf − Zi (Zo + ZL ) Zf2 − Zi (Zo + ZL )

since Zf = Zr . We can write for the transfer admittance YT as YT =

1 Z ( Z + ZL ) Zf − i o Zf

(13.88)

Analysis of Synchronously Tuned Double-Tuned Amplifier The circuit of a double-tuned amplifier is shown in Figure 13.32 and the ac circuit of a single stage in Figure 13.33. Resistance r1 is the output resistance of the first stage and r2 is the input resistance of the second stage. VCC

C1

L1

L2

R1

R2

C2

M

Q1 +

Q2

Vo + V1 −

Figure 13.32 Synchronously tuned double-tuned amplifier

Tuned Amplifiers

669

Resistances r1 and r2 that are parallel elements are replaced as series elements using the following relations: L2w 2 r1s = 1 o r1 r2s =

L22w o2 r2

Hence, the circuit in Figure 13.33 reduces to that in Figure 13.34 in which R11 = R1 + r1s and R22 = R2 + r2s . R1

R2

+ C1

r1

gmV1

L1

L2

Vo

r2

C2 M

Figure 13.33 AC circuit of Figure 13.32, for a single stage r1s

R1

gmV1

r2s

L1

C1

R2

+

L2

Vo

C2

M

Figure 13.34 Simplified circuit of Figure 13.33

If the current source in Figure 13.34 is replaced by a voltage source and the coupling network is replaced by the equivalent T-network, then the circuit in Figure 13.34 reduces to that in Figure 13.35. R11

1

L1 − M

L2 − M

R22 2

+

C1

+

+ V11

jgmV1/wC1

M I1

Vo I2

C2

2 1

Figure 13.35 Equivalent circuit of Figure 13.34

670

Electronic Devices and Circuits

1 1 = and the Qs of the circuits are Q1 = w o L1 R11 and L1C1 L2C2 Q2 = w o L2 R22 . Normally, both the tuned circuits are chosen to have the same Q. Hence, The resonant frequency, w o2 =

Q1 = Q2 = Q. From Figure 13.35, Vo =

−j I2 w oC2

(13.89)

From the definition of transfer admittance, we haveYT = I 2 V11 or I 2 = YTV11 and V11 = jgmV1 w oC1 . Therefore, I 2 = YTV11 =

jgmV1 YT w oC1

(13.90)

Substituting Eqn. (13.90) in Eqn. (13.89), Vo =

gmVY −j − j jgmV1 1 T I2 = YT = w oC2 w oC2 w oC1 (w oC1 )(w oC2 )

(13.91)

But at resonance, w o L1 =

1 1 and w o L2 = w oC1 w oC2

(13.92)

Substituting Eqn. (13.92) in Eqn. (13.91), 2 Vo = gmVY 1 T w o L1w o L2 = g mVY 1 T w o L1 L2

or A = gmYTw o2 L1L2

(13.93)

To calculate A, we need to calculate YT. To calculate YT using Eqn. (13.88), we need to calculate Zf, Zi, and (Zo + ZL ). From Figure 13.35, Zf = jw o M = jw o k L1L2

(13.94)

 1  Zi = R11 + j  wL1 − wC1  

(13.95)

 1  Zo + ZL = R22 + j  wL2 − wC2  

(13.96)

From Eqn. (13.95),   1  Zi = R11 + j  wL1 − = R11 1 +  wC1   

 wL 1  j 1 −   R11 wR11C1  

(13.97)

Tuned Amplifiers

671

But we have Q1 = Q =

w o L1 1 = R11 w o R11C1

(13.98)

Using Eqn. (13.98), Eqn. (13.97) can be written as   w wo   Zi = R11 1 + jQ  −   w o w   

(13.99)

From Eqn. (13.98), R11 =

w o L1 Q

(13.100)

Using Eqn. (13.100),   w w o   w o L1   w wo   Zi = R11 1 + jQ  −  = − 1 + jQ   Q   wo w    w o w   

(13.101)

Also we have defined d as follows: w= or

w − wo w = −1 wo wo w = 1+ d wo

(13.102)

Using Eqn. (13.102), Zi =

 w w o   w o L1 w o L1  − 1 + jQ  = Q  Q  w o w  

Zi =

w o L1 [1 + j 2dQ ] Q

  1  1 + jQ  (1 + d ) −  (1 + d )     (13.103)

Similarly,  1  w o L2 Zo + ZL = R22 + j  wL2 − = [1 + j 2dQ ] wC2  Q 

(13.104)

Using Eqs (13.94), (13.103), and (13.104), YT =

1 = Zi (Zo + ZL ) Zf − Zf

1

( jw k o

)

L1L2 −

 w o L1   w o L2   Q [1 + j 2dQ ]  Q [1 + j 2dQ ]

( jw k o

L1L2

)

672

YT =

Electronic Devices and Circuits

jw o kQ 2 L1L2

=

2

−w o2 k 2 L1L2Q 2 − w o2 L1L2 (1 + j 2dQ ) YT =

jw o kQ 2 L1L2

(

−w o2 k 2 L1L2Q 2 − w o2 L1L2 1 + j 4dQ − 4d 2Q 2

)

− kQ 2

(

(

- jw o L1L2 k 2Q 2 + 1 − j 4dQ − 4d 2Q 2

))

or YT =

− kQ 2

(

(

w o L1L2 4dQ − j 1 + k 2Q 2 − 4d 2Q 2

(13.105)

))

Therefore using Eqn. (13.105), A = gmw o2 L1L2YT =

A=

(− g

)

w o2 L1L2 kQ 2

m

(

(

w o L1L2 4dQ − j 1 + k 2Q 2 − 4d 2Q 2

− gmw o kQ 2 L1L2

(

4dQ − j 1 + k 2Q 2 − 4d 2Q 2

(13.106)

) kQ

A = gmw oQ L1L2

))

(

16d 2Q 2 + 1 + k 2Q 2 − 4d 2Q 2

2

(13.107)

)

The response of the double-tuned amplifier is plotted in Figure 13.36 with dQ as the independent variable versus A as a function of kQ. We see, from Figure 13.36, that as the value of kQ increases the response has two peaks. The frequency deviation d at which the gain peaks occur can d A be found out by maximizing the gain. For this, we equate to zero and get the value of d. Then dd d A substitute this value of d in the expression for A . From Eqn. (13.107), is obtained by simply dd 2 differentiating 16d 2Q 2 + 1 + k 2Q 2 − 4d 2Q 2 .  

(

)

(

)

2 d  16d 2Q 2 + 1 + k 2Q 2 − 4d 2Q 2  = 0    dd

(

(

32dQ 2 + −16dQ 2 1 + k 2Q 2 − 4d 2Q 2

(

)) = 0

)

16dQ 2 − 16dQ 2 k 2Q 2 − 4d 2Q 2 = 0 or

(1 − k Q 2

2

)

+ 4d 2Q 2 = 0

(13.108)

Tuned Amplifiers

673

A kQ = 1

kQ = 2.5

0.5 kQ = 2

0.4 0.3 0.2 0.1 kQ = 0.2 −2.0

−1.5

−1.0

−0.5

0

0.5

kQ = 0.5 1.0

1.5

2.0 dQ

−dQ

Figure 13.36 Response of the synchronously tuned, double-tuned amplifier

From Eqn. (13.108), d1,2 = ±

1 k 2Q 2 − 1 2Q

(13.109)

The two gain peaks occur at frequencies f1 and f2, where   1 f1 = fo 1 − k 2Q 2 − 1   2Q

(13.110)

  1 f 2 = fo  1 + k 2Q 2 − 1   2Q

(13.111)

and

When k 2Q 2 = 1, from Eqn. (13.109), d = 0 and from Eqn. (13.110) and from Eqn. (13.111), we see that the two frequencies are equal to fo. At kQ = 1, the response is similar to the response of a single-tuned amplifier. This value of k = kc is called critical coupling. For kQ < 1, it is said to be the case of under-coupling and the gain is less than the maximum. At kQ > 1, there is overcoupling. There are two peaks in the output. The spacing between the two peaks depends on the value of k. When the requirement is a sufficient bandwidth, overcoupling is used in the amplifier to derive the double-peaked response. The maximum amplitude of the gain occurs at d = 0 ( kQ = 1).

674

Electronic Devices and Circuits

From Eqn. (13.109), as the peaks occur at d 1,2 = ∓

Ap = gmw oQ L1L2

Ap = gmw oQ L1L2

1 k 2Q 2 − 1 , from Eqn. (13.107), 2Q kQ

2 2   k 2Q 2 − 1 2  2 2 2  k Q − 1 Q + + k Q − Q 16  1 4 2 2      4Q   4Q   

kQ

gmw oQ L1L2

=

4 k 2Q 2 − 4 + 4

2

(13.112)

2

The minimum gain AC occurs at d = 0 and from Eqn. (13.107) and is given as follows: AC = gmw oQ L1L2

kQ

(13.113)

(1 + k Q ) 2

2

From Eqn. (13.113), AC = gmw oQ L1L2 Ap AC

2 kQ

(

2

2 1+ k Q

2

)

= Ap

2 kQ

(1 + k Q ) 2

2

(13.114)

is called ripple g , the variation of gain and is Ap AC

=g =

1 + k 2Q 2 2 kQ

(13.115)

From Eqn. (13.115), k 2Q 2 − 2 kQg + 1 = 0 or x 2 − 2 xg + 1 = 0, where x = kQ

x1,2 =

2g ± 4g 2 − 4 = g ± g 2 −1 2

Consequently, kQ = g ± g 2 − 1

(13.116)

In the overcoupled case, kQ > 1. Hence, choosing positive in Eqn. (13.116), kQ = g + g 2 − 1

(13.117)

From Eqn. (13.117), it can be noted that to get a desired ripple, kQ can be adjusted accordingly. The response of the overcoupled amplifier is shown in Figure 13.37. The difference in the two frequencies at which the gain has fallen to AC is the useful bandwidth of the amplifier.

Tuned Amplifiers

675

A

AP AC

δP δC

f1

0

f0

f2

f

Figure 13.37 Response of the overcoupled, double-tuned amplifier

Therefore, the bandwidth is 2d c = f2′ − f1′= 2 ( f2 − f1 )

(13.118)

But from Eqs (13.110) and (13.111),   1 f1 = fo 1 − k 2Q 2 − 1  2Q    1 f 2 = fo  1 + k 2Q 2 − 1  2Q  Therefore, f2 − f1 =

fo k 2Q 2 − 1 Q

(13.119)

For a 3 dB change between the d c frequencies, the value of g = 2. From Eqn. (13.117), kQ = g + g 2 − 1 = 2 + 2 − 1 = 2.414. Therefore, from Eqn. (13.119), f2 − f1 =

fo Q

(2.414)2 − 1

(13.120)

From Eqn. (13.118), the bandwidth is as follows:

2 ( f2 − f1 ) =

fo 2 Q

(2.414)2 − 1 =

3.1 fo Q

(13.121)

676

Electronic Devices and Circuits

1

 1 4 The bandwidth of n-stage double-tuned amplifier is given as BW1  2 n − 1 . The bandwidth of   either tuned primary or tuned secondary has a bandwidth of 2 fo Q , whereas the bandwidth of the double-tuned amplifier is 3.1 fo Q, which is much larger. Also the response falls off very rapidly known as the steep skirt region, giving a near ideal response characteristic.

13.8.2 Stagger-Tuned Amplifier A stagger-tuned amplifier has two tuned circuits. But these are tuned to two resonant frequencies that are separated by the bandwidth of a single-tuned amplifier. The resultant response of this cascaded amplifier is somewhat similar to the response of a double-tuned amplifier. As the resonant frequencies are separated or staggered, this amplifier is called a stagger-tuned amplifier. The circuit of stagger-tuned amplifier is shown in Figure 13.38. The responses of the individual tuned circuits and the resultant response of the stagger tuned amplifier are shown in Figure 13.39. The resultant stagger-tuned amplifier will have 2 times the bandwidth of the single-tuned amplifiers. The relative response of a single-tuned amplifier is given by Eqn. (13.21) and its magnitude by Eqn. (13.22) as follows: A 1 1 = = Ar 1 + j 2dQe 1 + jX where X = 2dQe. When X = 1,

A 1 1 = = . When 2dQe = 1, 2 Ar 2 1 + (2dQe ) Qe =

1 2d

(13.122) VCC

Tuned circuit I C 1

L1

C2

L2

Q2

Q1 CC

Tuned circuit II

+ Vo

+ V1 − −

Figure 13.38 Stagger-tuned amplifier

Tuned Amplifiers

677

Resultant response

A Ar

1 Tuned circuit I

Tuned circuit II

0 fa

−dQe

+dQe

BW

Figure 13.39 Response of the stagger-tuned amplifier

The bandwidth of a single-tuned amplifier is given as follows: BW =

fo = 2dfo Qe

(13.123)

Stage I is tuned to a frequency d o fo below fo and the second tuned circuit is tuned to a frequency d o fo above fo. Hence, the relative gains these two tuned circuits are given as follows:  A 1  A  = 1 + j (X − 1) r 1

(13.124)

 A 1  A  = 1 + j (X + 1) r 2

(13.125)

and

The overall gain of the amplifier is     A  A  A 1 1  A  =  A   A  = 1 + j ( X − 1)  1 + j ( X + 1)  r p r 1 r 2     A 1 1 1  A  = 1 + j (X − 1) 1 + j (X + 1) = 1 + 2 jX − X 2 + 1 = 2 − X 2 + j 2X r p   

(

 A  A  r

= p

1

(

2−X

)

2 2

+ (2X )

2

=

1

)

(13.126)

4+X4

But X = 2d oQ . Therefore,  A  A  r

= p

1 4 + (2d oQ )

4

=

1 1 2 1 + 4Q 4d 4 o

(13.127)

678

Electronic Devices and Circuits

where d o is the value of d at w o and Q is the value of Qe for each of these circuits referred to w o. At the half-power point 4Q 4d o4 = 1 or d o = 1

2Q. Hence, the bandwidth of stagger-tuned amplifier

is 2 times the bandwidth of a single-tuned amplifier. In addition, the response is relatively flat in the desired frequency band and falls off rapidly.

13.9

INSTABILITY IN TUNED AMPLIFIERS

At high frequencies, noise and random variations may drive the tuned amplifier into generating oscillations. Also it is possible that the feedback produced through the collector to base interelectrode capacitance can produce positive feedback at certain frequencies which can drive the amplifier into generating oscillations. Thus, the amplifier becomes unstable. This means that the amplifier no longer behaves as an amplifier as is expected but behaves as an oscillator. This problem of instability in a tuned amplifier can be eliminated by using the following methods of stabilization: (i) unilateralization, (ii) mismatching, and (iii) neutralization.

13.9.1 Unilateralization An amplifier is supposed to be a unilateral network. This means that the input is transmitted to the output through the active device. However, no output is transmitted to the input terminals through the active device. But at high frequencies, Cb ′c (the interelectrode capacitance between the base and the collector), though is small, can offer relatively small reactance that it is possible for the output to be transmitted through Cb ′c to the input. This can cause oscillations to develop under proper circuit conditions, with the result that the tuned amplifier may not behave as an amplifier but can behave as an oscillator as depicted in Figure 13.40. r b′c B′ + C b′c r b′e

C b′e

L

V b′e

C gmV b′e

R

−

Figure 13.40 Feedback from the output to the input through Cb′c at high frequencies

Using the Miller’s theorem, Cb ′c and rb ′c can be replaced by Miller capacitance CMi and conductance in shunt with the input terminals (Figure 13.41). CMi = Cb ′c (1 − A). Since A is large and negative, CMi is reasonably large and at high frequencies its reactance tends to become small. The net effect is that the Miller capacitance and conductance reduce the input impedance, which in turn reduces the input signal. Thus, the gain of the amplifier is reduced, and hence the amplifier becomes stable.

Tuned Amplifiers

679

+ V b′e

gmV b′e C b′e

L C

C Mi

R −

Figure 13.41 Replacing Cb′c by CMi , using the Miller’s theorem

13.9.2 Mismatching Technique The load impedance of an untuned amplifier is usually small. Hence, there will be a large current flowing through the load. As feedback is provided through Cb ′c and rb ′c , the feedback current is relatively smaller. But a tuned amplifier is required to have a reasonably large Q so as to get a narrow band response. Hence, the tank circuit presents high impedance. To derive optimum response, transformer coupling is used for impedance matching. If instability is to be avoided, sometimes mismatch is desirable so as to reduce the gain of the amplifier. Thus, unilateralization and mismatching methods try to control the gain to eliminate instability. VCC

13.9.3 Neutralization Neutralization is a method that reduces the possibility of generating oscillations in a tuned amplifier and thus improves its stability. If a feedback signal is derived through Cb ′c , so as to develop oscillations, in this method, an equal and opposite signal is derived and is added to the feedback signal at the input so that the net feedback component is reduced to zero. Thus, the stability of the amplifier improves. Although there are many methods by which this requirement is implemented, essentially we consider here three methods of neutralization: (i)  Hazeltine neutralization, (ii) neutradyne neutralization, and (iii) Rice neutralization. Figure 13.42 shows an RF amplifier without neutralization.

C b′c C1 Q

M

+

Vs RE

CE

−

Figure 13.42 Tuned RF amplifier VCC C b′c

Hazeltine Neutralization The feedback signal that can be responsible for driving the amplifier into generating oscillations and thus can cause instability is derived through Cb ′c . The characteristic of a center-tapped winding of a transformer is that it is possible to derive signals of equal magnitude but of opposite phase. In Hazeltine method of neutralization, a signal of equal magnitude to that derived through Cb ′c but of opposite polarity is derived through CN , using the center-tapped primary of the tuned circuit and this signal is added at the input to the feedback signal so as to nullify the effect of feedback and thus ensure stability of the tuned amplifier (Figure 13.43).

L2 L1

C1 Q

L2 L1 M

+ CN Vs RE

CE

−

Figure 13.43 Hazeltine nuetralization

680

Electronic Devices and Circuits

Neutrodyne Neutralization In neutrodyne neutralization, the neutralizing capacitance, CN is connected from the coil connected to the base end of the next stage to the base of the first stage as indicated in Figure 13.44. Incidentally, a neutradyne receiver is a kind of tuned RF radio receiver. VCC C b′c L2

C1

L1

Q1

Q2

M

+ CN Vs RE

CE

−

Figure 13.44 Neutradyne neutralization

Rice Neutralization In this method, a tuned circuit is provided on the input side with a centertap on the secondary. One end of this winding (marked X) is connected to the base of Q. The output taken from the lower end of the center-tapped transformer on the output side is connected through CN to the other end of the center-tapped transformer (marked Y) on the input side. The feedback signal (through Cb ′c ) and the neutralizing signal (through CN ) connected to both ends of the center-tapped secondary coil on the input side are equal in magnitude and are opposite in polarity (Figure 13.45). VCC C b′c C1 + Vs −

Q

X

L2 L1 M

Ci Y

CN RE

CE

Figure 13.45 Rice neutralization

13.10 TUNED POWER AMPLIFIERS The transmitting power of a radio station is very large, of the order of few tens to hundreds of kW. Hence, the signal power is required to be raised to the desired value. A class-B power amplifier is one in which the output load current flows for exactly one half of the time period of an input sinusoidal signal. A class-C power amplifier is one in which the output load current flows

Tuned Amplifiers

681

for less than one half of the time period of the input sinusoidal signal. The input voltage and the output current waveforms of class-B and class-C amplifiers are shown in Figures 13.46 and 13.47, respectively. From Figure 13.46, it can be noted that the output current flows exactly for 180° in class-B operation and for less than 180° in class-C operation. The duration, in terms of angle, for which there is current flow through the load is called the angle of conduction. Obviously, it can be noted from Figure 13.46 that even though the device conducts for exactly one half of the input cycle period, by using a push–pull configuration, output can be derived for the entire input cycle period in a class-B push–pull amplifier. Hence, a class-B amplifier can be used for audio frequency applications. However, from Figure 13.47, it can be noted that the output is highly distorted. As such, a class-C amplifier cannot be used for audio applications, where there is need for high fidelity. Both class-B and class-C amplifiers can be used in high-power, high-frequency applications, like in radio transmitters. The outputs of class-B and class-C amplifiers contain a number of frequency components in addition to the fundamental component. The signal of interest could be an amplitude modulated signal, transmitted from an AM transmitter. To transmit the carrier and the two sidebands, a narrow band tuned amplifier that has the required bandwidth, is used which is tuned to the carrier frequency. A tuned amplifier may be either a tuned class-B or a tuned class-C power amplifier. However, as the efficiency of a class-C amplifier is large, class-C amplifiers are preferred over class-B amplifiers, for high-power applications. As the output of a class-C amplifier can also have the harmonics of the fundamental component, sometimes a tuned circuit may be used that is tuned to any desired harmonic component. Such a class-C amplifier is called a harmonic generator. Primarily, we discuss about a class-C tuned power amplifier.

Input voltage 0 vs

Output current ic

p

0 p

2p

2p

3p

3p

4p

4p

Input voltage vs 0

Output current ic

p

3p

4p

0 qC

Figure 13.46 Input voltage and the output current of class-B power amplifier

2p

qC

Figure 13.47 Input voltage and the output current of class-C power amplifier

13.11 TUNED CLASS-C POWER AMPLIFIER Figure 13.48 shows a class-C amplifier with resistive load. Under class-C operation, the base– emitter diode is reverse biased by a negative VBB source. This voltage controls the angle of conduction. This −VBB source is connected through a radiofrequency choke (RFC). This RFC offers high impedance to RF input signals, and thereby eliminates the possibility of these RF signals getting shorted at the input through the battery.

682

Electronic Devices and Circuits

VCC

ic I P = I C(sat)

ic RL

t

qC vi VP VC 0

Q

vi t

qC

RFC VBB

Figure 13.48 Class-C amplifier with resistive load

For the transistor to conduct, the minimum input voltage, VC will have to be at least just sufficient enough to overcome the reverse bias voltage VBB and the VBE of 0.7 V. Therefore, VC = VBB + 0.7. As long as vi is less than VC , Q is OFF, and there is no load current. When vi = VC, Q conducts for a duration q C and again when the input falls below VC the load current becomes zero. Thus, the output is in the form of pulses. It is now obvious that larger the value of VC the shorter is the duration of conduction of Q and vice versa. Thus, q C is controlled by VBB. VP is chosen such that at this value of input, Q is driven into saturation. Thus, I P corresponds to I C ( sat ). At high frequencies, the sinusoidal input can be approximated to a triangular wave to calculate q C. Hence, from Figure 13.49, VP V  V  q q  V cos  C  = C or C = cos −1  C  . Therefore, q C = 2 cos −1  C  .  2  VP 2  VP   VP 

VC

0

 0 (ii) If VC = 0, then q C = 2 cos   = 180°. This  Vp 

p qC qC 2 2

V  (i) If VC = Vp, then q C = 2 cos −1  C  = 0  Vp 

qC

Figure 13.49 Calculation of qc

−1

VCC

condition corresponds to class-B operation. L

C

For class-C operation, 0 ≤ q C ≤ 180°. But usually a class-C amplifier is not used with resistive load but with tuned circuit as load to select a desired frequency band of signal as in AM transmitters, which consists of the carrier and the two side bands as shown in Figure 13.50. The LC parallel tuned circuit is tuned to the carrier frequency, fc =

1 2p LC

Q RFC vi

VBB

Figure 13.50 Tuned class-C amplifier

Tuned Amplifiers

683

The pulsed waveform at the output of the class-C amplifier can be resolved into its frequency spectrum by using Fourier series. The amplitude of the fundamental frequency component of a class-C amplifier depends on the angle of conduction, q C. The larger is the value of q C, the larger is the amplitude of the fundamental component in the output. Let r1 be the ratio of the fundamental component to the peak amplitude of the class-C waveform. It is seen that to a close approximation r1 is given as r1 =

B1 = −3.54 + 4.1q C − 0.0072q C2 × 10 −3 IP

(

)

(13.128)

where, 0 ≤ q C ≤ 180° and B1 is the fundamental component of current. For q C = 0, r1 ≈ 0. For q C = 180°, r1 = 0.5. Thus r1 varies from 0 to 0.5 as q C varies from 0° to 180°. Similarly, let ro be the ratio of the dc component to the peak value of the class-C waveform. ro can be evaluated from the relation: ro =

Bo qC dc component of current = = I P Peak amplitude of the class-C output p (180°)

(13.129)

where Bo is the dc component of current. As q C varies from 0° to 180°, ro varies from 0 to 1 . For most of the input cycle period, Q is OFF and conducts only for a small duration q C. p Hence the amount of dissipation in the device can be very small. As a result the efficiency of a class-C amplifier can be large. The maximum output power (when Vm = VCC) at the fundamental frequency is P1 =

B1 2

×

Vm 2

=

r1I p 2

×

VCC 2

=

( )

VCC r1I p 2

(13.130)

The total dc input power

( )

PBB = BoVCC = r0 I p VCC

h=

(13.131)

P1 × 100% PBB

From Eqs (13.130) and (13.131),

( )

VCC r1I p

r 2 h= × 100% = 1 × 50% ro VCC ro I p

( )

(13.132)

Example 13.1 A class-C amplifier has a bias voltage of –5.3 V and a supply voltage VCC = 25 V. It is found that a peak input voltage of 10 V at 1 MHz is required to drive the transistor into saturation, with IC(sat) = 2 A. Find (i) the angle of conduction, q C, (ii) the power due to the fundamental component, P1 at 1 MHz, (iii) the efficiency of the power amplifier, h, (iv) the value of L of the tank circuit if C = 100 pF.

684

Electronic Devices and Circuits

Solution: (i) The voltage VC at which the transistor conducts is VC = VBB + 0.7 = 5.3 + 0.7 = 6 V. V   6 qC = 2cos −1  C  = 2cos −1   = 2 × 53.13 = 106.26°  10   VP  2 (ii) r1 =  −3.54 + 4.1(106.26 ) − 0.0072 (106.26 )  × 10 −3 = 0.351  

B1 = r1I P = r1I C(sat) = 0.351 × 2 = 0.702 A P1 = (iii) ro =

B1

×

VCC

2

2

0.702 × 25 = 8.775 W 2

qC 106.26 = = 0.188 p (180°) p × 180 h = 50 ×

(iv) L =

=

1

1

=

2

r1 0.351 = 50 × = 93.35% 0.188 ro

6 2

(2pfo ) C (2p × 1 × 10 )

= 0.25 mH

× 100 × 10 −12

Example 13.2 For a tuned class-C amplifier shown in Figure 13.51, calculate (i) the output power when Vpp = 30 V, (ii) maximum ac output power, (iii) dc input power if the current drain from the battery is 5 mA, (iv) efficiency when Vpp = 30 V, (v) bandwidth if Q = 100, and (vi) maximum dissipation in the transistor. 2VCC Vo

VCC = 25 V

VCC

t

VPP = 30 V

L = 1 µH

C = 100 pF

0

Q +

Cc

2VCC

+

RFC vi

VBB

Vo −

RL = 1

Vo VCC

− 0

Figure 13.51 Tuned class-C amplifier with waveforms

VPP = 2VCC = 50 V t

Tuned Amplifiers

685

Solution: (i) ∴

Po =

2 Vrms RL

Po =

V (30) = 112.5 mW = 8RL 8 × 1 × 103

Vpp = 2 2 Vrms or Vrms =

VPP 2 2

2

2 PP

(ii) Maximum ac output power is obtained when the output voltage swing is 2VCC. That is, VPP = 2VCC = 50 V. Po(max ) =

∴

(2VCC )2

=

8RL

(50)2 8 × 1 × 103

= 312.5 mW

(iii) Dc input power, PBB = VCCIdc = 25 × 5 = 125 mW Po 112.5 × 100 = 90% ×100 = PBB 125

(iv) Efficiency, h = (v) fo =

1 2p LC

=

1 −6

2p 1 × 10 × 100 × 10 −12

= 15.92 MHz

fo 15.92 = = 159.2 kHz Q 100 (vi) Maximum power dissipation in the transistor (also sometimes called as the worst case Po(max ) power dissipation) is . 5 Bandwidth =

Therefore,

PD(max )

2 2VCC ) ( =

40Rt

where Rt = Rp//RL We have, Q =

RP wo L

or RP = w o LQ = 2π × 15.92 ×106 × 1 × 10 −6 × 100 = 10 kΩ Hence,

Rt =

1 × 10 = 0.91 kΩ 1 + 10 PD(max ) =

(50)2 40 × 0.91

= 68.68 mW

13.11.1 Applications of Class C Tuned Amplifiers Two main applications of tuned Class C amplifier are considered here. One application is as an amplitude modulator and the other application is as a harmonic generator.

686

Electronic Devices and Circuits

Class C Tuned Amplifier as an Amplitude Modulator A Class C tuned amplifier can be used for transmitting an Amplitude Modulated (AM) signal from an AM radio station. Modulation is a process by which one of the parameters of a high frequency signal, (called the carrier), namely the amplitude, frequency or the phase, is varied in accordance with the instantaneous amplitude of the low frequency signal, (called the intelligence or the modulating signal to be transmitted from the radio station). If the amplitude of the carrier is varied in accordance with the instantaneous amplitude of the low frequency signal, then the type of modulation is called amplitude modulation. Similarly, if the frequency of the carrier is varied, then the type modulation is called frequency modulation and if the phase of the carrier is varied then the type of modulation is called phase modulation. Let the carrier vary as ec = Ec sinw c t and let the modulating signal vary as em = E m sinw m t. Then the amplitude of the carrier varies as A = ( Ec + em ) = ( Ec + E m sinw m t ) and the frequency of the carrier remains unaltered. Therefore, the amplitude modulated signal varies as A sinw c t . If the amplitude modulated signal is called e(t ), then  E  e(t ) = A sin w c t = ( Ec + E m sin w m t ) sin w c t = Ec 1 + m sin w m t sin w c t Ec   e(t ) = Ec (1 + ma sin w mt ) sin w ct In other way, this can also be expressed as, e(t ) = Ec sin w c t +

ma Ec cos (w c − w m ) − cos (w c + w m ) 2 

(13.133)

where, ma = E m Ec , is called the depth of modulation. w m, actually is not a single frequency but is a band of frequencies. (w c − w m ) is called the lower sideband (LSB) and (w c + w m ) is called the upper sideband (USB). In commercial broadcasting, the carrier is also transmitted so as to get back the signal in the receiver by a process called demodulation. A Class C amplifier used as an amplitude modulator is shown in Figure 13.52 and the waveforms in Figure 13.53. VCC

em 0

em = E msin w mt signal

L

Q

t

C e(t) A M s i gn a l

e ( t) Ec

ec = E csin w ct carrier

RFC VBB

0

t

ec

Figure 13.52 Class-C amplitude modulator

Figure 13.53 Waveforms

Tuned Amplifiers

687

The modulating signal is connected at the collector through transformer coupling. The voltage at the collector is, therefore, the sum of VCC and vm. As vm varies, the voltage at the collector also varies. The carrier is applied at the base. When the transistor is driven into saturation, the peak amplitude of the collector current I c ( sat) depends on the voltage at the collector. As the amplitude of vm changes from time to time so does the peak collector current. The result is that the output signal is an amplitude modulated wave. Class-C output 0

qC

t

Fundamental fs component in the output 0 t

Second harmonic in the output

2fs 0

Third harmonic 3fs in the 0 output

t

t

Figure 13.54 The output of a class C amplifier and frequencies in the output

Tuned Class-C Amplifier as a Harmonic Generator The output of a Class-C amplifier consists of the fundamental frequency component, fs and many higher order harmonics, nfs , where n = 1, 2, 3, ... Figure 13.54. The tuned circuit is tuned to the desired harmonic frequency. Then this amplifier is called harmonic generator.

13.12 WIDEBAND OR COMPENSATED AMPLIFIER V

CC In television receivers, it becomes necessary that the amplifier has bandwidth of the order of 4.5 MHz. But, when a transistor is used as an active element in a high frequency amplifier, L the Miller effect capacitor at the input, CMi reduces the input impedance of the amplifier and consequently the high frequency Q gain of the amplifier is reduced. This results in a decreased + bandwidth. In such a case it may not be possible to get a desired Cd + bandwidth of the order of 4.5 MHz. One method to derive V be1 Vbe2 this bandwidth, in such a case, is to reduce the gain. However, if the requirement is not to sacrifice the gain but at the same − − time obtain the desired bandwidth, then there arises the need to provide frequency compensation circuits which ensure that Figure 13.55 Shunt compensated the gain is maintained constant up to the desired frequency. wideband amplifier

688

Electronic Devices and Circuits

Such amplifiers are called wideband amplifiers or compen+ sated amplifiers. Wideband amplifiers include an inductance Cd in the load, which can appear either in series or in shunt with hie Vbe2 L the input capacitance of the next stage. The resonant frequency and the Q of the tank circuit are appropriately cho- gmVbe1 − sen so that the gain remains constant up to the frequency of interest. If the inductance is included in series with the input Figure 13.56 Equivalent circuit capacitance (Cd is Miller capacitance, CMi plus other capacitances) of the next stage, the type of compensation is called series compensation and the wideband amplifier is called a series compensated wideband amplifier. If alternately, the inductance is placed in shunt with the input capacitance of the next stage, the resultant compensation is called shunt compensation and the amplifier is called the shunt compensated (or shunt-peaked) wideband amplifier. To understand the principle of a wideband amplifier, we consider a shunt compensated wideband amplifier shown in Figure 13.55. The equivalent circuit is shown in Figure 13.56. hie in shunt with L can be replaced by R in series with L as shown in Figure 13.57. +

R + Cd Vbe2

≡

L gmVbe1

gmVbe1(s)

Vbe2(s)

Z(s) −

−

Figure 13.57 Circuit of Figure 13.56, with hie and L replaced by R and L

From Figure 13.57, using Laplace transforms Y ( s ) = sCd +

1 R + Ls

(13.134)

and Z(s) =

1 1 sCd + R + Ls

(13.135)

Our interest is to consider the influence of the compensating inductance, L on the gain of the amplifier. When the compensating inductance is not included, that is, L = 0, from Figure 13.57, the upper half-power frequency is w 2 and is given as follows: w2 =

1 RCd

(13.136)

To show that there is improvement in bandwidth with compensation, we use w 2 as the reference. From the tuned circuit in Figure 13.56, w o2 =

1 LCd

(13.137)

Tuned Amplifiers

689

We have, Vbe 2 ( s ) = − gmVbe1 ( s )Z ( s )

(13.138)

Therefore, Vbe 2 ( s ) = − gm Z ( s ) Vbe1 ( s )

(13.139)

R + Ls R + Ls = 1 + sCd (R + Ls ) LCd s 2 + RCd s + 1

(13.140)

Ah ( s ) = From Eqn. (13.135), 1

Z(s) =

=

1 R + Ls Dividing the numerator and the denominator by L and using Eqn. (13.137), sCd +

R R R s+ s+ L L L = = Z(s) = RCd 1 R     2 R 1 Cd s + s+ Cd  s 2 + s + w o2  Cd  s 2 + s +    L L L L LCd   s+

(13.141)

From Eqs (13.139) and (13.141), R s+ − gm L Ah ( s ) = − gm Z ( s ) = Cd  2 R 2  s + s + w o  L

(13.142)

The expression for Ah ( s ) has a zero at s = −R L and two poles. To get the location of the two poles, we equate the denominator to zero. s2 +

R s + w o2 = 0 L

(13.143)

The two roots are as follows: 2

− s1,2 =

R  R ±   − 4w o2 2  L L −R  R = ±  − w o2   2L  2 2L

(13.144)

2

 R When w o2 =  , the term under the square root becomes zero and both the poles are real and  2 L   −R  appear at  . With this condition, the gain can be optimized. With L large conjugate poles are  2 L  present. Using the condition 2

R2  R = 2 w o2 =    2L  4L

(13.145)

690

Electronic Devices and Circuits

From Eqs (13.137) and (13.145), R2 1 = 2 LCd 4 L or L=

R 2Cd 4

This value of L is called the critical inductance, Lcritical : Lcritical =

R 2Cd 4

(13.146)

With conjugate poles, we have a raise in gain at w = w o, for the resonant load amplifier. The raise in gain can be controlled by Q, referenced to w 2. Q=

w2 L R

(13.147)

From Eqs (13.136) and (13.147), Q=

1 L L × = 2 RCd R R Cd

Dividing both numerator and denominator by 4 and using Eqn. (13.146), L L L Q = 2 = 24 = R Cd R Cd 4 Lcritical 4

(13.148)

From Eqn. (13.140), we have Z(s) =

R + Ls LCd s 2 + RCd s + 1

Substituting s = jw, in the above equation, we have Z=

R + j wL

(1 − w LC ) + jwRC

(13.149)

2

d

d

We have Vbe 2 = − gmVbe1Z . Therefore, using Eqn. (13.149), Ah = − gm Z = − gm ×

R + j wL

(1 − w LC ) + jwRC 2

d

d

Hence, 2

R 2 + (wL )

2

Ah = gm ×

(1 − w

2

) + (wRC ) 2

LCd

2

d

 wL  1+   R  = gm R × 1 + w 4 L2Cd2 − 2w 2 LCd + w 2 R 2Cd2

Tuned Amplifiers

 wL  1+   R 

Ah = Am

Ah Am

2

 2L  1 + w 4 L2Cd2 + w 2 R 2Cd2 1 − 2   R Cd   wL w 2  1+   R w 2 

=

691

2

(13.150)

 2L  1 + w L C + w R C 1 − 2   R Cd  4

2

2 d

2

2

2 d

Using Eqs (13.136), (13.137), and (13.147), in Eqn. (13.150) can be written as follows:

Ah

=

Am

w 1 + Q2    w2 

2

(13.151)

2

w 4  w   2w L  1 + 4 +   1 − 2  R  wo  w2  

From Eqs (13.137) and (13.136), w o2 =

1 1 R 1 R R = × = × = w2 × LCd LCd R RCd L L w o4 = w 22 ×

R2 L2

Hence, w 4 w 4 L2 = w o4 w 22 R 2

(13.152)

Substituting Eqn. (13.152) in Eqn. (13.151), w 1+ Q    w2 

2

w 1+ Q    w2 

2

Ah Am

=

2

2

2

w 4 L2  w   2w L  1 + 2 2 +   1 − 2  R  w2 R  w2  

=

2

w 4 w 2 L2  w   2w L  1 + 4 2 2 +   1 − 2  R  w2 R  w2  

Using Eqn. (13.147),

Ah Am

=

w 1 + Q2    w2  2

2

4

w w 1 +   (1 − 2Q ) +   Q 2  w2   w2 

(13.153)

692

Electronic Devices and Circuits

In the high-frequency range, because of Miller effect, as the gain is likely to fall, shunt compensation is provided to keep the response flat and thus improve the bandwidth. Consider the function H (w ) =

1 + a1w 2 + a2w 4 + ... 1 + b1w 2 + b2w 4 + ...

(13.154)

Mathematically, it is shown that a function of the form shown in Eqn. (13.154) can be made to have the flattest response by equating the coefficients of the equivalent powers of the variable in the numerator and the denominator. That is, the response in the desired frequency range tends to be flat if a1 = b1, a2 = b2, and so on. 2

w Equating the coefficients of   in Eqn. (13.153),  w2  Q 2 = 1 − 2Q or Q 2 + 2Q − 1 = 0

(13.155)

Therefore, Q=

−2 ± 4 + 4 = −1 ± 2 = −2.414 or 0.414 2

Q is taken as 0.414, since Q cannot have a negative value. From Eqn. (13.148), Q=

L 4 Lcritical

From this, L = 4QLcritical = 4 × 0.414 × Lcritical = 1.656 Lcritical

(13.156)

Choosing L using Eqn. (13.156) will give a flat response in the frequency range of interest. The relative response of the shunt compensated wideband amplifier is plotted as a function of f f2 , for Q varying from 0 (uncompensated amplifier) to 1, Figure 13.58. It can be noted that the bandwidth of the compensated amplifier is 1.72 times the bandwidth of the uncompensated amplifier, for Q = 0.414 . As Q increases, there is no appreciable improvement in bandwidth. The response tends to be peaky, which is not the desired response. Thus, it can be noted that by providing a compensating inductance L, chosen as 1.656 times Lcritical , the response of the amplifier can be made flat for Q = 0.414 . The resultant bandwidth of the compensated amplifier is 1.72 times the bandwidth of the uncompensated amplifier. Because of the

Tuned Amplifiers Relative gain magnitude

693

Q=1

1

Q = 0.8 0.707 Q = 0.5 Q = 0.414 Q=0 0

1

f f2

1.72 f2′ f2

Figure 13.58 Relative response of shunt compensated wideband amplifier

small input resistance of a CB configuration, the Miller effect capacitance will have negligible say on the input impedance. Hence, a cascode amplifier is preferred for high-frequency applications.

Additional Solved Examples Example 13.3 In a capacitive-coupled single-tuned amplifier circuit, the bandwidth is 5 kHz and the voltage gain has the maximum value at 1000 kHz when the tuning capacitor is adjusted to 500 pF. Calculate (i) the inductance of the coil and (ii) the Q of the circuit. Solution: (i)

fo =

1 2p LC

(ii) BW =

fo Qe

L=

1 1 = 2 4p Cfo 40 × 500 × 10 −12 1 × 106

Qe =

fo 1000 = = 200 BW 5

2

(

Example 13.4 For the parallel resonant circuit shown in Figure 13.59, R = 100 Ω , L = 50 mH and C = 0.005 µF. Find (i) the resonant frequency considering R, (ii) the resonant frequency neglecting R, (iii) Q of the inductor, and (iv) the bandwidth of the circuit.

2

)

= 0.05 mH

Is

+

L C R

V

s Solution: At resonance, the reactive component of the RL branch current, iL is equal to the reactive component of the capacitive Figure 13.59 Parallel resonant circuit branch current, iC.

694

Electronic Devices and Circuits

Reactive component of the RL branch current, Vs wo L w o LVs iL = × = 2 2 2 2 2 2 R + (w o L ) R + (w o L ) R + (w o L ) Reactive component of the capacitive branch current, iC = w oCVs w o LVs 2

R 2 + (w o L )

= w oCVs

2

R 2 + (w o L ) =

⇒ fo =

(i) fo =

1 2p

1 1 R2 − 2 = 2p LC L

fo =

1 R2 − 2 LC L

R2 1 - 2 LC L

1 1002 − −6 50 × 10 × 0.005 × 10 50 × 10 −3 −3

1

(

2

)

1 = -3

2p 50 ´ 10 ´ 0.005 ´ 10 -6

2p LC

4000 = 10.071 kHz 2p

=

(iii) Q of the inductor at resonance = (iv) Bandwidth =

wo2 =

4000 − 4 = 10.066 kHz 2p

= (ii) With R = 0,

1 2p

L ⇒ C

w o L 2p × 10.066 × 103 × 50 × 10 −3 = = 31.61 R 100

fo 10.066 = = 318 Hz 31.61 Q

Example 13.5 The following circuit parameters are specified for a single-tuned capacitive-coupled transistor RF amplifier: Ro of the amplifier stage is 40 kΩ, Ri of the next stage is 20 kΩ. The parallel tank circuit consists of L = 0.01 mH, R = 20 Ω , and C = 47 pF. The stray capacitance at the output terminals is 3 pF. Calculate (i) fo, (ii) Qe, and (iii) BW. Solution: The output circuit is shown in Figure 13.60. Rp C Ro

L C′

+ Ri

Vo −

gmVb′e

Figure 13.60 Output circuit

Ceq = C + C ′ = 47 + 3 = 50 pF

(i) fo =

1

1 =

2p LC

2p 0.01 × 10 −3 × 50 × 10 −12

= 7.12 MHz

Tuned Amplifiers

2

(

)(

2p × 7.12 × 106 0.01 × 10 −3 w o2 L2 Rp = = R 20

(ii)

Rt = Ro // Rp // Ri = 40 // 10.14 // 20 =

695

2

)

= 10.14 kΩ

40 × 10.14 × 20 = 5.76 kΩ 40 × 10.14 + 10.14 × 20 + 20 × 40

Qe = w oCeq Rt = 2p × 7.12 × 106 × 50 × 10 −12 × 5.76 × 103 = 12.88 (iii) BW =

fo 7.12 × 106 = = 552.80 kHz Qe 12.88

Example 13.6 A single-tuned transistor amplifier is to amplify a modulated signal, whose carrier frequency is 10.7 MHz and bandwidth is 150 kHz. The effective shunt resistance is 10 kΩ and the stray shunt capacitance is 10 pF. Calculate L and C values used in the tank circuit. Solution: Given Rt = 10 kΩ, fo = 10.7 MHz, and BW = 150 kHz. Qe =

Qe = w oCeq Rt⇒ Ceq =

fo 10700 = = 71.33 BW 150

Qe 71.33 = = 106.15 pF. w o Rt 2p × 10.7 × 106 × 10 × 103

Ceq = C + C ′ ⇒ C = Ceq − C ’ = 106.15−10 = 96.15 pF

L=

1 1 = 4p 2Ceq fo2 40 × 106.15 × 10 −12 10.7 × 106

(

2

)

= 2.06 µH

Example 13.7 A single-tuned transistor amplifier is to amplify a modulated signal, whose center 1 frequency is 10.7 MHz and bandwidth is 150 kHz. gm = 10 mA/V, = 40 kΩ, Ri of the next stage hoe is 40 kΩ and the magnitude of the gain at resonance is 100. Find Qe , L, R, and C of the tank circuit. Solution: The output circuit is shown in Figure 13.61.

L C gmVb′e

Ro =1/hoe

Ri R

+ Vo −

+

≡

C gmVb′e

Vo

L

Ro

Figure 13.61 Output circuit of the single-tuned transistor amplifier

Rp

Ri −

696

Electronic Devices and Circuits

Given fo = 10.7 MHz, BW = 150 kHz, gm = 10 mA/V, Ro =

Qe =

fo 10700 = = 71.33 BW 150

L=

A = gm Rt = 100

1 = 40 kΩ , Ri = 40 kΩ , and |A| = 100 hoe Rt =

Rt 10 × 103 = = 2.09 µH w oQe 2p × 10.7 × 106 × 71.33

Rt = Ro // Ri // Rp

⇒

200 + 10Rp = 20Rp

⇒

Ro // Ri = 40 // 40 = 20 kΩ 10Rp = 200 2

(

)(

1 1 = 2 4p Lfo 40 × 2.09 × 10 −6 × 10.7 × 106 2

(

10 =

⇒

20Rp 20 + Rp

Rp = 20 kΩ

⇒

2p × 10.7 × 106 2.09 × 10 −6 w 2 L2 R= o = Rp 20000 C=

100 100 = = 10 kΩ 10 gm

2

)

2

)

=1Ω

= 104.5 pF

Example 13.8 For the single-tuned FET amplifier, fo = 10 MHz, BW = 50 kHz, gm = 10 mA/V, and rd = 80 kΩ. The amplifier is required to have A = 75. Determine the component values of the tank circuit. Solution: The input resistance of the next stage is very large, and hence is omitted as an open circuit. Hence, the resultant equivalent circuit is as shown in Figure 13.62, in which R in series with L is replaced by a parallel Rp. +

+

V gs

gmV gs

Rp

rd

Vo C

L

−

−

Figure 13.62 Output circuit of the single-tuned FET amplifier

Given fo =10 MHz, BW = 50 kHz, gm = 10 mA/V, rd = 80 kΩ, and A = −75 Qe =

fo 10000 = = 200 BW 50

A = gm Rt = 75

⇒

Rt =

A 75 = = 7.5 kΩ gm 10

Tuned Amplifiers

L=

697

Rt 7.5 × 103 = = 0.597 µH w oQe 2p × 10 × 106 × 200

The input resistance of the next stage is large. Rt = rd // Rp= 80 // Rp = 7.5 kΩ

∴ 600 + 7.5Rp = 80Rp

72.5Rp = 600

⇒

⇒

⇒

)(

2p × 10 × 106 0.597 × 10 −6 w 2 L2 R= o = Rp 8280 1 1 = 4p 2 Lfo2 40 × 0.597 × 10 −6 × 10 × 106

C=

(

80Rp 80 + Rp

Rp = 8.28 kΩ

2

(

7.5 =

2

)

2

)

= 0.17 Ω

= 418.76 pF

Example 13.9 A single-tuned FET amplifier has µ = 200 and gm = 5 mA/V. The tuned circuit consists of an inductance of 100 µH and having an associated resistance of 5 Ω in parallel with capacitance of 100 pF. Find (i) fo, (ii) Rp, (iii) A at resonance, and (iv) BW. Solution: 1

(i) fo =

1 =

2p LC

(ii) Rp =

−6

2p 100 × 10 × 100 × 10 −12

w o2 L2 1 and w o2 = LC R ∴

(iii) rd =

= 1.59 MHz

m 200 = = 40 kΩ gm 5

Rp =

L 100 × 10 −6 L2 = = = 200 kΩ LCR CR 100 × 10 −12 × 5

Rt = rd // Rp =

40 × 200 = 33.33 kΩ 40 + 200

A = gm Rt = 5×33.33 = 166.65

(iv) Qe =

Rt 33.33 × 103 = = 33.38 w o L 2p × 1.59 × 106 × 100 × 10 −6 BW =

fo 1590 = = 47.63 kHz Qe 33.38

698

Electronic Devices and Circuits

Example 13.10 A single-tuned RF amplifier uses an FET having µ = 300 and rd = 60 kΩ . The parallel tuned circuit consists of an inductance L = 100 µH, which has a series resistance R. Q of the inductance at the resonant frequency is 100. The resonant frequency of the tank circuit is 9.985× 106 rad/sec. A stray capacitance C’ = 10 pF appears across the tank circuit. Find (i) C of the tank circuit, (ii) R, (iii) Rp, (iv) Rt, (v) Qe, ( vi ) A at resonance, (vii) A at a frequency 50 kHz above resonance, (viii) A at a frequency 20 kHz below the resonant frequency, and (ix) BW. Solution: (i) Ceq = C + C ′

=

⇒

wo =

1 6 2

(9.985 × 10 )

× 100 × 10 −6

1

⇒

LCeq

Ceq =

1 w o2 L

= 100.30 pF

C = Ceq − C ′ = 100.30−10 = 90.30 pF

(ii) Q of L at resonance is Q =

R=

∴

(iii) Rp=

wo L R w o L 9.985 × 106 × 100 × 10 −6 = = 9.985 Ω 100 Q

L 100 × 10 −6 = = 110.91 kΩ CR 90.30 × 10 −12 × 9.985

(iv) Rt = rd // Rp = 60 // 110.91 = 38.94 kΩ (v) Qe =

Rt 38.94 × 103 = = 39 w o L 9.985 × 106 × 100 × 10 −6

(vi) Ares = gm Rt =

(vii) fo =

m 300 × Rt = × 38.94 = 194.7 rd 60

w o 9.985 × 106 = 1.59 MHz = 2p 2p d =

f = fo + 50 kHz A = Ares

1 2

1 + ( 2dQe )

f − f0 50 = = 0.0314 f0 1590

⇒ A=

Ares 2

1 + ( 2dQe )

=

194.7 2

1 + ( 2 × 0.0314 × 39)

= 73.58

Tuned Amplifiers

(viii)

d =

f = fo − 20 kHz

f0 − f 20 = = 0.0126 f0 1590

Ares

A=

2

194.7

=

2

1 + ( 2dQe ) (ix) BW =

699

= 139.07

1 + ( 2 × 0.0126 × 39)

fo 1590 = = 40.77 kHz Qe 39

Example 13.11 A single-tuned RF amplifier using FET has Ares = 50, fo = 10 MHz, and BW = 125 kHz. The parameters of the FET are µ = 400 and rd = 80 kΩ. The tank circuit consists of L and C in parallel with R as the resistance in series with L. Calculate the parameters of the tank circuit. Solution: gm =

m 400 = = 5 mA/V rd 80

Ares = gm Rt

Ares = 50 Rt =

⇒

| Ares | 50 = = 10 kΩ 5 gm

fo 10000 = = 80 BW 125 Rt R 10 × 103 Qe = t ⇒ L = = = 1.99 µH w oL w oQe 2p × 10 × 106 × 80

Qe =

Rt = rd // Rp =

(

rd Rp

⇒10 =

80 × Rp 80 + Rp

rd + Rp 2

)(

⇒70Rp = 800 ⇒Rp =

2p × 10 × 106 1.99 × 10 −6 w 2 L2 R= o = Rp 11430 Rp =

or

C=

800 =11.43 kΩ 70

2

)

= 1.39 Ω

1.99 × 10 −6 L L = ⇒C = = 125.25 pF RRp 11.43 × 103 × 1.39 CR 1 1 = 2 − 4p Lfo 40 × 1.99 × 10 6 × 10 × 106 2

(

2

)

= 125.63 pF

Example 13.12 For a double tuned amplifier, k = 3kc and Q1 = Q2 = Q = 100. The resonant frequency of the tank circuit is 10 MHz. Find (i) the two frequencies f1 and f2 at which the gain peaks occur and (ii) BW of the circuit if g = 3 dB.

700

Electronic Devices and Circuits

Solution: kc =

1 1 = = 0.01 Q 100

k = 3kc = 3× 0.01 = 0.03 2

2

k 2Q 2 = (0.03) (100 ) = 9 (i) The two gain peaks occur at frequencies f1 and f2, where æ ö 1 f1 = fo ç1 k 2Q 2 - 1 ÷ è 2Q ø 1 1     = 10 1 − 9 − 1  =9.86 MHz k 2Q 2 − 1  = 10 1 −  200  200   æ ö 1 f 2 = fo ç 1 + k 2Q 2 - 1 ÷ è 2Q ø

and

1   = 10 1 + 9 − 1  =10.14 MHz  200  (ii) g = 3 dB ⇒20 log10 g = 3 dB ⇒ log10 g = 0.15 ⇒g = 2 = 1.414 kQ = g + g 2 − 1 = 2 + 2 − 1 = 2.414 f2 − f1 =

fo Q

Bandwidth = 2( f2 − f1 ) = 2 × 2.2

(2.414)2 − 1 = 2.2 ×

fo Q

fo 3.1 fo 3.1 × 10 = = = 310 kHz. Q Q 100

Example 13.13 A double-tuned amplifier has L1 = L2 = 75 µH and Q1 = Q2 = 80. The transistor has gm = 5 mA/V. Find (i) C1 and C2 so as to have fo = 10.7 MHz, (ii) the spacing between the gain peaks when k = 2kc, (iii) Ap , and (iv) g . Solution: (i) C =

1 1 = 2 − 6 4p Lfo 40 × 75 × 10 × 10.7 × 106 2

(ii) k = 2 kc =

(

2

)

= 2.91 pF ⇒C1 = C2 = 2.91 pF.

2 Q

æ ö 1 4 1  ´ Q 2 - 1 ÷÷ = 10.7 1 − f1 = fo çç1 3  =10.7 × 0.989 = 10.58 MHz 2  Q 2 Q 160  è ø

Tuned Amplifiers

701

1 æ ö and f2 = 10.7 ç1 + 3 ÷ = 10.82 MHz è 160 ø (iii) Ap =

gmw oQ L1L2

=

2

Ap

1 + k 2Q 2 (iv) =g = = Ac 2 kQ

5 × 10 −3 × 2p × 10.7 × 106 × 80 × 75 × 10 −6 = 1007.9 2 4 × Q2 5 Q2 = = 1.25 2 4 2 × ×Q Q

1+

Example 13.14 A double-tuned amplifier has fo = 10.7 MHz and the spacing between the response Ap peaks is 200 kHz. = 2, Ap = 16 and gm = 10 mA/V. Determine L and C of the tank circuits. Ac Solution: g = 2 ⇒kQ = g + g 2 − 1 = 2 + 2 − 1 = 2.414 f2 − f1 =

Ap =

fo Q

(2.414)2 − 1 = 2.2

fo 2.2 fo 2.2 × 1070 ⇒Q = = = 11.77 Q f2 − f1 200

gmw oQ L1L2 2

16 =

10 × 10 −3 × 2p × 10.7 × 106 × 11.77 × L 2

L=

16 × 2 = 4.05 µH ⇒ L1 = L2 = L = 4.05 µH 10 × 10 × 2p × 10.7 × 106 × 11.77

C=

1 1 = 2 − 6 4p Lfo 40 × 4.05 × 10 × 10.7 × 106

−3

2

(

2

)

= 53.92 pF

C1 = C2 = C = 53.92 pF Example 13.15 The bandwidth of a single-stage, double-tuned amplifier is 200 kHz. Calculate the bandwidth of a 4-stage cascaded amplifier. 1

1 4 Solution: The bandwidth of n-stage double-tuned amplifier = BW1 2 n − 1     1

 1 4 The bandwidth of 4-stage double-tuned amplifier = 200 2 4 − 1 = 132 kHz  

702

Electronic Devices and Circuits

Summary • A tuned amplifier amplifies only a desired narrow band of frequencies and effectively rejects the unwanted frequencies. • The bandwidth of a single-tuned amplifier is fo Qe , where fo is the resonant frequency of the tank circuit and Qe is its effective Q. 1

• The bandwidth of cascaded n identical stages of tuned amplifiers is BWn = BW1 2 n − 1. • The bandwidth of either tuned primary or tuned secondary inductively coupled amplifier is 2 fo Qe, that is, twice the bandwidth of a single-tuned capacitive-coupled amplifier. • The Qe of the tank circuit can be adjusted by using a tapped inductance or a tapped capacitance, which in turn controls the bandwidth • A synchronously tuned double-tuned amplifier has two mutually coupled tuned circuits and both the tuned circuits are tuned to the same center frequency. The double-tuned amplifier usually finds application in radiofrequency (RF) and intermediate frequency (IF) amplifiers in radio receivers. • In the synchronously tuned double-tuned amplifier, at kQ = 1, the response is similar to the response of a single-tuned amplifier. This value of k = kc is called critical coupling. • In the synchronously tuned double-tuned amplifier, if kQ < 1, it is said to be a case of under coupling and the gain is less than the maximum. • In the synchronously tuned double-tuned amplifier, if kQ > 1, there is overcoupling. There are two peaks in the output. The spacing between the two peaks depends on the value of k. 3.1 fo . Q • In a stagger-tuned amplifier two tuned circuits are used, which are tuned to two resonant frequencies that are separated by the bandwidth of a single-tuned amplifier. • The bandwidth of a synchronously tuned double-tuned amplifier is

• The bandwidth of a stagger-tuned amplifier is 2 times the bandwidth of the single tuned amplifier. • Tuned power amplifiers are used to raise the narrow band AM signal power to the tune of a few hundred kW or they may be also used as harmonic generators. • Miller capacitance reduces the input impedance of an amplifier at high frequencies, and hence the gain of the amplifier and its bandwidth are reduced. In order to improve the bandwidth of this amplifier either series compensation or shunt compensation is used. Such compensated amplifier is called wideband amplifier.

multiple ChoiCe QueStionS 1. In a tuned circuit, L = 100 µH and C = 100 pF. The resonant frequency w o is (a) 10 MHz (b) 20 MHz (c) 5 MHz (d) 1 MHz 2. In a single-tuned amplifier, f = 12 MHz and fo = 10 MHz. Then the frequency deviation d is (a) 0.2 (b) 0.1 (c) 10 (d) 20 3. Two identical single-tuned amplifiers are cascaded. The bandwidth of each stage is 10 kHz. The bandwidth of the cascaded amplifier is (a) 64.3 kHz (b) 6.43 kHz (c) 0.643 kHz (d) 643 kHz

Tuned Amplifiers

703

4. In a tapped inductance tuned amplifier, the tap on the inductance is used to adjust (a) Q of the tank circuit (b) output resistance (c) lower half-power frequency (d) upper half-power frequency 5. In a double-tuned amplifier, both the tuned circuits are tuned to (a) two different frequencies (b) same frequency (c) two different frequencies separated by the bandwidth of each stage (d) none of these 6. In a double-tuned amplifier, k = 0.25, Q = 10, and fo = 10 MHz. Then the two gain peaks occur at (a ) f1 = 0.885 MHz and f2 = 1.115 MHz ( b ) f1 = 88.5 MHz and f2 = 111.5 MHz ( c ) f1 = 8.85 MHz and f2 = 11.15 MHz ( d ) f1 = 885 MHz and f2 = 111.5 MHz 7. In a double-tuned amplifier, k = 0.25, Q = 10, then g is (a) 14.5 (b) 1.45 (c) 0.145 (d) 1450 8. In a double-tuned amplifier (a) 31 kHz (c) 3.1 MHz

fo = 1 MHz . Then its bandwidth is Q (b) 3.1 kHz (d) 31 MHz

9. In a stagger-tuned amplifier two tuned circuits are used which are tuned to two resonant frequencies which are separated by (a) the bandwidth of a single-tuned amplifier (b) the bandwidth of a double-tuned amplifier (c) 2 times the bandwidth of a single-tuned amplifier (d) none of these 10. A class-C tuned power amplifier can also be used as a (a) wideband amplifier (b) stagger-tuned amplifier (c) audio power amplifier (d) harmonic generator 11. Miller effect reduces the bandwidth, when a CE amplifier is used at high frequencies. If, to improve the bandwidth shunt compensation is used, then the resultant amplifier is called (a) RC -coupled amplifier (b) tuned Class-C amplifier (c) wideband amplifier (d) emitter follower 12. 2 MHz is the bandwidth of an uncompensated CE amplifier at high frequencies. If frequency compensation is provided with shunt connected inductance L chosen as L = 1.656 Lcritical, then the new bandwidth is (a) 3.44 MHz (c) 8 MHz

(b) 4 MHz (d) 1.72 MHz

Short anSwer QueStionS 1. Where is the need for tuned amplifiers? 2. What is Q of the tank circuit?

704

Electronic Devices and Circuits

3. What is the expression for the relative gain of a single-tuned capacitor coupled amplifier? 4. How are resonant frequency and bandwidth related in a single-tuned amplifier? 5. n number of single-tuned identical amplifiers are cascaded, what is the bandwidth of the cascaded configuration? 6. How are double-tuned amplifiers classified as? 7. What is the difference between the synchronously tuned double-tuned amplifier and the staggered-tuned aamplifier? 8. What is the advantage of the synchronously tuned double-tuned amplifier when compared to a singletuned amplifier, in terms of bandwidth? 9. What is the advantage of the stagger-tuned double-tuned amplifier when compared to a single-tuned amplifier, in terms of bandwidth? 10. What do you understand by instability in a tuned amplifier? 11. How do you propose to eliminate the problem of instability in a tuned amplifier? 12. List two applications of a tuned class-C amplifier. 13. What is the need for frequency compensation in an amplifier, and how is it implemented?

long anSwer QueStionS 1. Draw the circuit of a single-tuned voltage amplifier and show that the relative gain is given as

1 . 1 + j 2dQe

Draw the circuit of a tuned primary transistor voltage amplifier and derive the expression for its gain. Draw the circuit of a tuned secondary FET voltage amplifier and derive the expression for its gain. Draw the circuit of a double-tuned transistor voltage amplifier and derive the expression for its gain. Draw the circuit of a stagger-tuned transistor voltage amplifier and obtain the expression for its gain. 6. Draw the circuit of a tuned class-C power amplifier and derive the expression for its efficiency. 7. What is a wideband amplifier? Show with the help of relevant expressions that by proper choice of Q the bandwidth of a compensated amplifier is 1.72 times the bandwidth of the uncompensated amplifier.

2. 3. 4. 5.

unSolved problemS 1. An RLC circuit shown in Figure 13.63 has fo = 1 MHz , Qo = 100, and R = 500 Ω. Determine the values of L and C. 2. A variable condenser that has C min = 50 pF and C max = 500 pF is used in an LC tank circuit for which the minimum frequency to be tuned, L C fmin = 1 MHz. Find (i) the value of L, (ii) fmax, and (iii) R of the coil if the R bandwidth is 10 kHz. 3. The following circuit parameters are specified for a single-tuned capacitive-coupled transistor RF amplifier: Ro of the amplifier stage is 50 kΩ, Ri of the next stage is 2 kΩ. The parallel tank circuit consists of L = 0.01 mH, Figure 13.63 Tuned circuit R = 10 Ω, and C = 100 pF. The stray capacitance at the output terminals is 3 pF. Calculate (i) fo , (ii)Qe , and (iii) BW. 4. For the single-tuned FET amplifier, fo =10 MHz, BW = 100 kHz, gm = 2.5 mA/V, and rd = 60 kΩ. The amplifier is required to have A = 50. Determine the component values of the tank circuit.

Tuned Amplifiers

705

5. A single-tuned transistor amplifier is required to amplify an AM signal with center frequency of 500 kHz and bandwidth of 10 kHz. The total shunt resistance is 10 kΩ and the output capacitance is 30 pF. Determine the values of L and C. 6. (i) The bandwidth of a single-tuned amplifier is 10 kHz. Calculate the bandwidth if two and four such stages are cascaded. (ii) The bandwidth of a double-tuned amplifier is 10 kHz. Calculate the bandwidth if two and four such stages are cascaded.

14

OPERATIONAL AMPLIFIERS

Learning objectives After reading this chapter the reader will be able to ˆ Understand the need for a differential amplifier and necessity to have a large common mode rejection ratio (r) ˆ Realize that a differential amplifier supplied with a constant current will make the value of r ideally infinity ˆ Appreciate the need for a dc level shifter in an Op-amp ˆ Understand the need and the types of frequency compensation techniques employed in Op-amps ˆ Learn the experimental procedures to measure the parameters of the Op-amp

14.1

INTRODUCTION

An operational amplifier is a high-gain direct-coupled amplifier. The main advantage of a directcoupled amplifier is that its frequency response is flat right from 0 Hz. Op-amp can be used both for dc and ac applications. The block diagram in Figure 14.1 gives the basic building blocks of an op-amp.

V1 V2

Dual-input, balanced-output differential amplifier

Dual-input, unbalanced-output differential amplifier

DC level shifter

Output power stage

Vo

Figure 14.1 Block diagram of operational amplifier

The first stage in an operational amplifier is a differential amplifier or a difference amplifier. Two signals V1 and V2 are the inputs to the differential amplifier consisting of two transistors: Q1 and Q2. The output of this amplifier is taken between the two collectors. If Q1 and Q2 are identical, then the dc voltage between these two collectors is zero. Therefore, the first stage in an operational amplifier is a dual-input balanced-output differential amplifier. This stage accounts for the maximum gain in the amplifier. The second stage is also a dual input; but in this case, the output is taken at one of the collectors with respect to the reference terminal and hence the output is

Operational Amplifiers

707

unbalanced. Therefore, the second stage is a dual input, unbalanced output differential amplifier. Since op-amp is a direct-coupled amplifier, the output of one stage is directly connected to the input of the next stage without using any reactive elements such as capacitors or transformers. If dc is directly connected to the input of the next stage, this may alter the biasing conditions of the succeeding stage that may cause distortion in its output. Hence, there arises the need for incorporating a dc-level shifter in an op-amp, which is usually an emitter follower stage. Hence, the third stage in an op-amp is a dc-level shifter or dc-level translator. The device should ultimately be capable of delivering a certain amount of output power. Therefore, the output stage is a complementary symmetry push–pull power amplifier, which has been considered in Chapter 11. We now discuss the working of each of these building blocks.

14.2

DIFFERENTIAL AMPLIFIER

A differential amplifier is used as an input stage in many measuring instruments. A differential amplifier has two inputs V1 and V2 and the output Vo is proportional to the difference of the two inputs (Figure 14.2). The difference signal Vd is (14.1)

Vd = V1 − V2

In many cases, the output, in addition to the required differential signal, may also contain an error term due to the average of the two inputs, called the common-mode signal, Vc. Vc =

V1 + V2 2

(14.2)

V1 Differential amplifier

Vo = AdVd

V2

Figure 14.2 Differential amplifier

A two-transistor differential (or difference) amplifier is shown in Figure 14.3. The circuit can be seen as one in which two CE amplifiers with emitter bias are combined together. The two halves of the circuit are assumed to be identical. As the output is taken between the two collectors, this is a dual-input, balanced-output differential amplifier. From Figure 14.3, let Vo be the linear combination of the outputs of Q1 and Q2. Vo = AV 1 1 + A2V2

(14.3) VCC

where A1 is the gain of Q1 and A2 is the gain of Q2. We have V1 -V2 = Vd

(14.4)

RC

RC

And

Vo

V1 + V2 = 2Vc

(14.5)

V1

V2 Q2

Q1

Solving Eqs (14.4) and (14.5), 1 V1 = Vc + Vd 2

(14.6)

1 V2 =Vc - Vd 2

(14.7)

RE

−VEE

Figure 14.3 A two-transistor differential amplifier

708

Electronic Devices and Circuits

Substituting Eqs (14.6) and (14.7) in Eqn (14.3),

( A − A2 )V + A + A V 1 1 Vo = A1 (Vc + Vd ) + A2 (Vc − Vd ) = 1 ( 1 2) c d 2 2 2 \Vo = Ad (V1 -V2 ) + Ac where Ad =

( A1 - A2 ) 2

(V1 +V2 ) 2

(14.8)

and Ac = ( A1 + A2 ) \Vo = AdVd + AV c c

(14.9)

æ ö æ A 1 ö Vo = Ad çVd + c Vc ÷ = Ad çVd + Vc ÷ Ad ø r ø è è

(14.10)

Or

Ad is the figure of merit of the differential Ac amplifier. r, the figure of merit of the differential amplifier is indicative of the ability of the differential amplifier to reject the unwanted common-mode signal Vc (error signal) and deliver only the desired differential signal Vd at the output. The larger the value of r, the better the rejection of the unwanted common mode signal in the output. Ideally, when r = ∞, Vo = AdVd . The output contains only the differential signal. where r = common mode rejection ratio (CMRR) =

Example 14.1 A differential amplifier has Ad = r = 40 dB (i) V1 = 50 μV and V2 = –50 μV. (ii) V1 = 1050 μV and V2 = 950 μV. Calculate V0 and the percent error in both the cases. Solution: Given r = 40dB, then it means that r = 100, since 20 log10 100 = 40dB. (i) Vd = V1 - V2 = 50 - ( -50 ) = 100 mV and Vc =

V1 + V2 50 − 50 = = 0. 2 2

\Vo = AdVd = (100 ´ 100 )mV = 10 mV This is the output of an ideal differential amplifier. The output contains only the differential component: % error = 0% V + V2 1050 + 950 (ii) Vd = V1 -V2 =1050 - 950 = 100 mV and Vc = 1 = =1000 mV 2 2 æ 1 ö 1 æ ö Vo = Ad çVd + Vc ÷ =100 ç100 + ´ 1000 ÷ = 11mV r 100 è ø è ø % error = 10% Example 14.2 A differential amplifier has Ad = 40 dB. V1 = 1050 μV and V2 = 950 μV. Calculate the % error, if (i) r = 60 dB and (ii) r = 80 dB

Operational Amplifiers

Solution: Vd = V1 -V2 =1050 - 950 =100 mV and Vc =

709

V1 + V2 1050 + 950 = =1000 mV 2 2

(i) r = 60dB, then it means that r = 1000 æ 1 ö 1 æ ö Vo = Ad çVd + Vc ÷ =100 ç100 + ´ 1000 ÷ = 10.1mV r 1000 è ø è ø For an ideal differential amplifier, Vo =10 mV Therefore, % error = 1% (ii) r = 80dB, then it means that r = 10000 æ 1 ö 1 æ ö Vo = Ad çVd + Vc ÷ = 100 ç100 + ´ 1000 ÷ = 10.01mV r 10000 è ø è ø For an ideal differential amplifier, Vo =10 mV Therefore, % error = 0.1% From the above examples, it can be noted that the percentage error becomes small as the value of r becomes larger and larger. Ideally, r should be infinity.

14.2.1 DC Analysis For the differential amplifier shown in Figure 14.3, proper dc conditions must first be established before being used as an amplifier. To determine the operating point, consider the dc circuit shown in Figure 14.4. The dc circuit is obtained by shorting the ac sources. From Figure 14.4, VCC

VEE = VBE + 2 I E RE or

RC

IE =

VEE -VBE 2RE

VC = VCC - I C RC

(14.11) +

(14.12) IB

and

IC

VC +V Q1 CE −

VBE −

IE

IC

VE

RC

+VC VCE Q − 2 IE

− VBE

RE

VE = -VBE

(14.13)

VCE = VC − VE = VCC − I C RC − ( −VBE ) = VCC + VBE − I C RC \ VCE = VCC + VBE - I E RC since I E » I C I C and VCE specify the coordinates of the Q-point.

(14.14)

VEE

Figure 14.4 DC circuit

+ IB

710

Electronic Devices and Circuits

14.2.2 AC Analysis In order to determine the gain, input resistance, and output resistance, it becomes necessary to draw the ac circuit. The ac circuit is drawn by shorting the dc sources (Figure 14.5). The redrawn ac circuit and the equivalent circuit are shown in Figures 14.6 and 14.7. From Figure 14.7, VCC

VCC

RC

RC −

V1

Vo

Q1

V1 = ( re + RE ) I e1 + RE I e 2

(14.15)

V2 = RE I e1 + ( re + RE )I e 2

(14.16)

Using Cramer’s rule,

+ Q2

V1 RE V ( r + RE ) -V2 RE V2 re + RE I e1 = = 1 e (14.17) re + RE RE re ( re + 2RE ) RE re + RE

V2

RE

Similarly, re + RE V1 I e2 =

Figure 14.5 To draw ac circuit short dc sources Vo Vc1 Ic1

V2 (re + RE ) − V1RE RE V2 (14.18) = re + RE RE re (re + 2RE ) RE re + RE

+

− Ie1

Vc2 Ic2

Ie2 Q2

Q1

Ad = RC

Ib1

+

(V1 − V2 )( re + 2RE )RC re ( re + 2RE )

Vo = (II e1 − I e 2 )RC =

+

Ib2 RE

RC

V2

V1

(re + 2RE ) RC ≈ RC Vo = (V1 −V2 ) re (re + 2RE ) re

since re 0

(ii) When Vi < 0, Vo1 = Vsat . Therefore, D1 is OFF and D2 is ON (Figure 15.97). I3

R

R

R V

R

−

+ A Vs

OFF A1

I1

+

D1 V

Vo1

− Vd = 0

0 A2

+

t

+ Vo −

D2 ON 0

t

R

I2

Figure 15.97 Circuit whenVi < 0

Let Vo1 = V . If Vd is approximately zero, V appears at the inverting input of A2. A virtual ground exists at the input of A1. Therefore, V V V I1 = s , I 2 = and I 3 = R R 2R

812

Electronic Devices and Circuits

Writing the KCL at node A, I1 + I 2 + I 3 = 0

(15.109)

Vs V V + + =0 R R 2R

(15.110)

2 V = − Vs 3 To find Vo , consider the circuit of A2 (Figure 15.98). or

R

R

(15.111)

R

− A2 V

+

t

0 + Vo −

Figure 15.98 Circuit to calculate Vo

R 3 3  2   Vo = V 1 + = V = ×  − Vs  = −Vs  2R  2 2  3 

(15.112)

During the negative half cycle of the input, the output is shifted in phase by 180°. The input and the output waveforms are shown in Figure 15.99.

Vs

0

t

0

t

Vo

Figure 15.99 Input and the output waveforms of the full-wave rectifier

Additional Solved Examples Example 15.19 Design the non-inverting amplifier shown in Figure 15.100, using op-amp 741, so as to get an output voltage of 4 V, with an input of 50 mV. For IC 741, I B(max ) = 500 nA

Applications of Op-Amp

R3

813

+ Ri

+

+

−

Vi

R1

−

Vo

−

I2 I2

R2

Figure 15.100 Non-inverting amplifier

Solution: I B(max ) = 500 nA . I 2 is chosen such that I 2(min) >> I B(max ) . Choose I 2 = 0.1 mA . The voltage across R2 = VR 2 = Vi = 50 mV ⇒ Vi = I 2 R2 . Therefore, R2 =

Vi 50 = = 500 Ω I 2 0.1

From Figure 15.100, I 2 ( R1 + R2 ) = Vo Þ ( R1 + R2 ) =

Vo 4 = = 40 kW. Therefore, I 2 0.1

R1 = ( R1 + R2 ) − R2 = 40 − 0.5 = 39.5 kΩ For bias compensation, R3 = R2 || R1 =

39.5 × 0.5 = 494 Ω ≈ 500 Ω 39.5 + 0.5

For the non-inverting amplifier,  R   39.5  Vo = Vi 1 + 1  = 50 × 10 −3 1 +  =4V  0.5   R2  Example 15.20 For the summing amplifier in Figure 15.101, find Vo , if V1 = 1 V , V2 = 1 V, R = 10 kΩ, and RF = 100 kΩ. The voltage at the non-inverting input terminal is due to V1 and V2 sources. Using the superposition theorem, the net voltage VA is VA = V1

V V R 1 1 R + V2 = 1 + 2 = + =1V R+R R+R 2 2 2 2

 R   100  Vo = VA 1 + F  = 1 1 +  = 11 V   10  R

814

Electronic Devices and Circuits RF

R −

R

+ Vo −

VA

V1

+

V2 R

Figure 15.101 Summing amplifier

Example 15.21 For the Schmitt trigger circuit shown in Figure 15.77, determine the values of R1 and R2 . The supply voltages are ± 15 V and the range of hysteresis is 5 V. Solution: VH = VUTP − VLTP = bVsat − ( − bVsat ) = 2 bVsat = 2Vsat

R2 R1 + R2

Vsat = 0.9VCC = 0.9 × 15 = 13.5 V 5 = 2 × 13.5 × 1+

R2 R1 + R2

R1 27 R = = 5.4 ⇒ 1 = 4.4 ⇒ R1 = 4.4R2 R2 5 R2

Choose R2 = 10 kΩ, then R1 = 4.4 × 10 = 44 kΩ Example 15.22 For the op-amp circuit shown in Figure 15.21, R1 = 10 kΩ, R2 = 20 kΩ, R3 = 25 kΩ, R4 = 50 kΩ, RF = 100 kΩ, and R5 = 20 kΩ. Determine the numerical value of Vo , if V1 = V2 = 1 V , and V3 = V4 = 2 V . Solution: R  R 100   100 Vo1 = −  F V1 + F V2  = −  ×1+ × 1 = −15 V.  10  20 R2   R1 From Eqn. (15.23), VA = V3

R4 R5 R3 + R4 R5

= 2×

+ V4

R3 R5 R4 + R3 R5

50 20 25 20 +2× = 0.73 + 0.36 = 1.09 V 25 + 50 20 50 + 25 20

  RF  100  Vo 2 = VA 1 + = 1.09 1 + = 17.43 V   10 20   R1 R2  Vo = Vo 2 + Vo1 = 17.43 − 15 = 2.43 V

Applications of Op-Amp

815

Example 15.23 Design the symmetric astable circuit, shown in Figure 15.55, to oscillate at 5 kHz. Solution: T =

1 1 = = 0.2 ms f 5 T = 2t log n

If

Therefore,

R1 = 1.16R2 , b =

1+ b 1− b

[ in Eqn. (15.72 )]

R2 R2 1 = = = 0.46. R1 + R2 1.16R2 + R2 2.16

1 + 0.46 T = 2t log n t n = 2t log=n 2t.70 =n 2t 1 − 0.46

=

T = 0.1 ms 2

Therefore, RC = 0.1 × 10 −3 s

Choose C = 0.01 mF, then R =

0.1 × 10 −3 = 10 kΩ 0.01 × 10 −6

R2 R R 1 = 0.46 ⇒ 1 + 1 = = 2.17 ⇒ 1 = 1.17 ⇒ R1 = 1.17R2 R1 + R2 R2 0.46 R2 Choose R2 = 10 kΩ, then R1 = 1.17R2 = 1.17 × 10 = 11.7 kΩ Example 15.24 A triangular waveform having a peak amplitude of 2 V, and a frequency of 1 kHz is applied to the inverting input terminal of the zero-crossing detector (Figure 15.102). Plot the input and the output waveforms, if the supply voltages are ±15 V .

− + vs

VR

Vo

+

−

Figure 15.102 Inverting zero-crossing detector

Solution: Vsat = 0.9 × VCC = 0.9 × 15 = 13.5 V When, Vs > 0, Vo = -Vsat = -13.5 V and when, Vs < 0, Vo = +Vsat = 13.5 V The input and the output waveforms are shown in Figure 15.103.

816

Electronic Devices and Circuits

2V Vi

2

1

3

0V

t ms

−2 V +Vsat = 13.5 V Vo 0 V

t ms

−Vsat = −13.5 V

Figure 15.103 Input and output waveforms

Summary R and that of the noninverting amplifier is 1 + F . R1 R1 • In a summing amplifier, the output is proportional to the sum of the input voltages, and in a subtracting amplifier the output is proportional to the difference of the input voltages • The gain of an inverting amplifier is

−RF

• A differential amplifier can be used as an instrumentation amplifier. • An integrator is a circuit that gives an output proportional to the integral of the input signal and a differentiator is a circuit that gives an output proportional to the differential of the input signal. • A voltage-to-current converter is a circuit in which the output current is proportional to the input voltage, and a current-to-voltage converter is a circuit in which the output voltage is proportional to the input current. • Op-amp can be used as a monostable, astable, and Schmitt trigger. • Log and antilog amplifiers can be used as voltage multipliers and dividers. • A zero-crossing detector is the one that tells the time instant the input has reached a zero level. • A level detector is the one that tells the time instant the input has reached a preset reference level. • The purpose of a window detector is to tell whether the unknown input lies between a specified voltage range or not. • Precision rectifiers use op-amps along with diodes to ensure that the circuit configuration behaves as an ideal diode. Then, this circuit configuration is called a superdiode

multiple ChoiCe QueStionS 1. What is the output of the amplifier shown below? RF

1 R1

− 1

+

+ Vi

1mV −

+15V

Vo

+

− −15V

Applications of Op-Amp

(a) +15 V (c) −1 V

(b) −15 V (d) −10 V

2. What is the output of the amplifier shown below? RF

1 R1

+15V

− 1

+ Vo

+ + 1mV Vi −

(a) +15 V

− −15V

(b) −15 V (d) −2 mV

(c) 2 mV

3. What is the input voltage of the amplifier, if the output voltage is −10 V ? (a) 10 V (b) 1 V (c) 0.1 V (d) 0.01 V RF

10

R1

+15V

−

+ Vi

10 + Vo −

+ −15V

5

4. For the circuit shown below, Vo is 200

20 10mV

10mV

+15V

− 10 + −15V

(a) -300 mV (c) +15 V

(b) 500 mV (d) −15 V

+ Vo −

817

818

Electronic Devices and Circuits

5. For the circuit shown below, Vo is 20

20

+15V

− 10mV 10mV

+ Vo −

+

20

−15V

20

(a) 0 (c) +15 V

(b) 500 mV (d) −15 V

6. In an inverting RC integrator using an op-amp, RC = 1 s, Vi = 5 V , then Vo = _______ (a) 10 t (b) −5 t (c) 5 t (d) 15 V 7. In a monostable multivibrator using an op-amp, if b = 0.5 , R = 10 kΩ and C = 0.1 mF, T = _________ (a) 0.69 ms (b) 6.9 ms (c) 0.69 ms (d) 6.9 ms 8. In an astable multivibrator using an op-amp, if, R1 = 1.16R2 , R = 10 kΩ, and C = 0.1 mF , then f is (a) 500 Hz (c) 50 Hz

(b) 1000 Hz (d) 100 Hz

9. If the transfer characteristic of a circuit is as shown in figure below, the circuit is a VCC Vo

0 VLR

(a) pulse generator (c) window detector

VUR

(b) dc amplifier (d) ac amplifier

Vi

Applications of Op-Amp

819

10. For the Schmitt trigger circuit shown below, the UTP and LTP, respectively, are VCC Vi

− Vsat = 14V VR

+

+ −VEE

R

R

(a) +7 V and − 7 V (c) −7 V and + 7 V

(b) +15 V and − 15 V (d) −15 V and + 15 V

Short anSwer QueStionS 1. What is the expression for the gain of an inverting feedback amplifier? 2. What is the expression for the gain of a non-inverting feedback amplifier? 3. What is a summing amplifier? 4. What is a subtracting amplifier? 5. What are the advantages of a buffer amplifier? 6. What are the limitations of an ideal integrator? How are they overcome? 7. What are the main requirements of an instrumentation amplifier? 8. How are V − I converters classified as? 9. Name some of the applications of a comparator?

 Vi  10. If the output of a logarithmic amplifier is given as Vo = −hVT ln  I R  , name the limitation of this amplifier. S

820

Electronic Devices and Circuits

long anSwer QueStionS 1. Draw the circuit of an adder–subtractor using a single op-amp and derive the expression for its output voltage. 2. Draw the circuit of a logarithmic amplifier and derive the expression for its output voltage. Show how temperature compensation is provided in this amplifier. 3. Draw the circuit of an antilogarithmic amplifier and derive the expression for its output voltage. Show how temperature compensation is provided in this amplifier. 4. With the help of a neat circuit diagram, explain the working of a monostable multivibrator using an op-amp. Derive the expression for its pulse width. Draw the waveforms. 5. With the help of a neat circuit diagram, explain the working of an astable multivibrator using an opamp. Derive the expression for its frequency. Draw the waveforms. 6. What are precision rectifiers? Explain the working of a full-wave rectifier.

unSolved problemS 1. For the circuit shown in Figure 15.5, R4 = R2 = 200 kΩ, R3 = 1 kΩ and R1 = 500 kΩ Calculate the gain and input resistance of the amplifier. 2. For the circuit shown in Figure 15.104, V1 = 1 V and V2 = 2 V . Determine Vo . R R R

− R Vi

+ V1

A1

+

Vo1

+

R

A2

R

− +

−

+ Vo −

V2

−

Figure 15.104 Two-stage amplifier 3. For the amplifier circuit shown in Figure 15.44, find the differential input needed to give an output of 10 V, when the center tap of the 1 kΩ pot is (i) at position A and (ii) at position B. 4. For the circuit in Figure 15.105, calculate Vo , if Vi = 2V .

Applications of Op-Amp

821

R4 5

5

−

Vi R3

VA VB

A1

Vo

+

+

R1 100

5

R2

Figure 15.105 Amplifier circuit 5. For the unsymmetric astable shown in Figure 15.58, R1 = R2 = 10 kΩ, R4 = 5 kΩ, R3 = 10 kΩ, and C = 0.1 mF, calculate the frequency and the duty cycle. 6. Design an adder–subtractor shown in Figure 15.21 to get V0 = 3V1 − 3V2 + 3V3 − 4V4 .

16

ACTIVE FILTERS

Learning objectives After reading this chapter, the reader will be able to     

16.1

Learn the characteristics of low-pass, high-pass, and band-pass passive filters Understand the limitations of passive filters and the need for active filters Appreciate the analysis and design of first-order and higher-order Butterworth filters Understand the need and application of an all-pass filter Realize the importance of switched capacitor filters

INTRODUCTION

Filters are frequency-selective electronic circuits that pass only the desired band of frequencies from the input to the output and reject or attenuate the unwanted frequencies. Filters are broadly classified as follows: (i) Passive and active filters (ii) Analog and digital filters (iii) Audio frequency (AF) and radio frequency (RF) filters (i) Passive and active filters: Passive filters use only passive circuit components such as resistors, capacitors, and inductors; whereas, active filters use active circuit components such as transistors and op-amps in addition to the passive circuit components. The main limitation of the passive filters is that the output is smaller than the input as the signal gets attenuated. Also the circuit may load the driving signal source. (ii) Analog and digital filters: Analog filters are used to process analog signals using analog techniques and digital filters use the digital techniques to process analog signals. (iii) Audio frequency (AF) and radio frequency (RF) filters: These filters are classified as AF and RF filters depending on the frequency range of operation. Filters are also classified as follows (i) (ii) (iii) (iv) (v)

Low-pass filter High-pass filter Band-pass filter Band elimination (or band reject) filter All-pass filter

Active Filters

16.2

823

PASSIVE LOW-PASS, HIGH-PASS, AND BAND-PASS FILTERS

16.2.1 Low-Pass Filter An ideal low-pass filter is one for which there is a constant output for frequencies from 0 to fH and no output for frequencies beyond fH. This means the filter only passes frequencies from 0 to fH . fH is called the corner frequency or the cut-off frequency. But a practical low-pass filter will not have a sharp cut-off and frequency components above fH may also be found in the output, though with a reduced magnitude (Figure 16.1). Ideal response

Practical response

A = Vo / Vi

Stop band Pass band

fH

0

f

Figure 16.1 Ideal and practical responses of a low-pass filter

A passive low-pass circuit may contain RC or RL components (Figure 16.2). L R +

+ C

Vi

Vo

−

−

+

+

Vi

R

−

Vo −

(b) RL circuit

(a) RC circuit

Figure 16.2 Passive low-pass circuit

Assuming sinusoidal input and using Laplace transforms, from Figure 16.2(a), 1 Vo ( s ) 1 sC = = 1 Vi ( s ) 1 + sCR +R sC

(16.1)

To plot the frequency response, substitute s = jw in Eqn. (16.1). Vo ( jw ) 1 = Vi ( jw ) 1 + jwCR

Let

wH =

1 1 or fH = CR 2pCR

(16.2)

(16.3)

824

Electronic Devices and Circuits

Therefore,

A=

Vo ( jw ) = Vi ( jw ) A=

1

w 1+ j wH 1

 f  1+    fH 

=

1 f 1+ j fH

(16.5)

2

 f  q = − tan −1    fH 

and

(16.4)

(16.6)

where q is the phase angle. From Eqn. (16.5), 1 At f = 0, A = 1, at f = fH , A = and at f = ¥, A = 0. 2 Therefore, the response of the circuit is as shown in Figure 16.3. For 0 < f < fH, A < 1 and the gain (which in fact is attenuation here) will not remain constant in the pass band. This is one main limitation of the passive low-pass circuit. Also the response of the filter is not ideal, and hence the output contains unwanted frequencies. The cut-off or corner or breakpoint frequency ( fH ) is the frequency where R = X C . At this   V 1 frequency, Vo is attenuated to 70.7 percent of Vi or −3 dB  = 20 log10 o = 20 log10 = −3 dB Vi   2 of the input. Also, since the filter contains C, the phase angle (q) of the output signal lags behind that of the input and at fH it is −45° out of phase. By cascading two RC low-pass filters, the filter becomes a second-order filter, for which the gain rolls off at a slope of −40 dB/decade. For a fourth-order filter, the roll-off is at a slope of −80 dB/decade and so on. This means that as the order of the filter is increased, the roll-off slope becomes steeper and the actual stop band response of the filter approaches its ideal stop band characteristics. A 0 dB 1 −3 dB 0.707

Stop band

Slope = −20 dB/decade Pass band

0

fH

f

0

fH

f

0° q −45°

−90°

Figure 16.3 Response of a practical RC passive low-pass circuit

Active Filters

825

When n identical RC filters are cascaded together, the output gain at the required cut-off n  1  frequency ( fH ) is reduced and is given as  , where n is the number of cascaded stages.  2  2 Therefore, for a second-order passive low-pass filter the gain at fH is (0.707 ) Vi = 0.5Vi (the gain 3

is = −6 dB), for a third-order passive low-pass filter it is (0.707 ) Vi = 0.353Vi (the gain is = −9 dB) and so on.

16.2.2 High-Pass Filter An ideal high-pass filter is one for which there is zero output for frequencies from 0 to fL and constant output for frequencies beyond fL. This means the filter passes frequencies from fL to ¥. fL is called the corner frequency or the cut-off frequency. But a practical high-pass filter will not have a sharp cut-off and frequency components below fL may also be found in the output, though with a reduced magnitude (Figure 16.4). Practical response A = Vo / Vi

Ideal response Stop band Pass band

fL

0

f

Figure 16.4 Ideal and practical responses of a high-pass filter

Passive RC and RL high-pass circuits are shown in Figure 16.5. For a sinusoidal input and using Laplace transforms, from Figure 16.5(a), Vo ( s ) R sCR = = 1 Vi ( s ) 1 + sCR +R sC

(16.7)

To plot the frequency response, substitute s = jw in Eqn. (16.7), R

C

+

+

Vi

Vo R

−

− (a) RC circuit

+

+ L

Vi

Vo

−

− (b) RL circuit

Figure 16.5 Passive high-pass circuit

826

Electronic Devices and Circuits

A=

Let

1 Vo ( jw ) jwCR = = Vi ( jw ) 1 + jwCR 1 − j 1 wCR

ωL =

1 or 1 fL = CR 2pCR

(16.8)

(16.9)

Therefore, A=

Vo ( jw ) = Vi ( jw )

1 w 1− j L w

1

=

1− j

fL f

1

A=

f  1+  L   f 

(16.11)

2

f  q = − tan −1  L   f 

and the phase angle

(16.12)

From Eqn. (16.11), 1

At f = 0, A = 0, at f = fL , A =

and at f = ¥, A = 1. 2 Therefore, the response of the circuit is as shown in Figure 16.6. A 1 0.707

0

fL

f

fL

f

90°

q

45°

0° 0

Figure 16.6 Response of a practical RC passive high-pass circuit

High-pass circuits may be cascaded to improve the roll-off.

(16.10)

Active Filters

827

16.2.3 Band-Pass Filter A cascaded configuration of a HPF and an LPF would form a band-pass filter (Figure 16.7). The filter passes to the output, signals that lie between fL and fH. fo = fL fH . The phase angle of Vo leads Vi by +90° up to fL and then decreases linearly till fo at which it becomes zero. Then, Vo lags Vi and at f = fH and beyond it is −90° (Figure 16.8). High pass filter

Low pass filter

C2

R1

+

+

Vi

C1

R2

−

Vo −

Figure 16.7 Band-pass filter

Stop band

Stop band

0 dB −3 dB A Pass band −dB 0

fL

f0

fH

f

+90° q

f

0° −90°

Figure 16.8 Response of the band-pass filter

16.3

ACTIVE FILTERS

The main disadvantages of passive filters are (i) the amplitude of the output signal is less than that of the input signal; (ii) the load impedance affects the filters characteristics; (iii) attenuation becomes severe in cascaded filter; and (iv) when multiple stages are cascaded, there can be loading effect between successive filter stages, which results in further loss of signal. The loss of signal can be made up by using active filters. Further, isolation can be provided between successive stages

828

Electronic Devices and Circuits

by using buffers. Active filter circuits contain active components such as operational amplifiers, transistors, or FETs with the main objective of providing amplification. However, there is no need to provide power from an external power source in passive filters, whereas active filters need external power source(s). A simple active low-pass filter using op-amp is shown in Figure 16.9.

R

− A +

+

+ Vo

Vi C

−

Figure 16.9 Active low-pass filter

The filter uses a buffer amplifier (A = 1), but the major advantage is that the buffer amplifier has a large input resistance that avoids loading the signal.

16.3.1 Classification of Active Filters Active filters can be mainly of three configurations: (i) Butterworth, (ii) Chebyshev, and (iii) Bessel filters. (i) Butterworth filter: Butterworth filter is also called as maximally flat or flat–flat filter. These filters have a flat amplitude-frequency response in the pass band and have a monotonic drop (uniform slope) with increase in frequency in the stop band. The roll-off slope can be −20 dB/decade for the first order filter which is slow. The phase-shift of a Butterworth filter is non-linear as a function of frequency (Figure 16.10). (ii) Chebyshev filter: Chebyshev filter is also called an equal ripple filter. It has a gain ripple in the lower frequency pass band, but it gives a sharper roll-off than Butterworth filter in the stop band. A Chebyshev filter is used where very sharp roll-off is required. Chebyschev

0 Butterworth A dB Bessel f

Figure 16.10 Frequency response of three types of filters

Active Filters

829

(iii) Bessel filter: The Bessel filter has a very linear phase response but a fairly gentle skirt slope. It is a minimal phase shift filter even though its cut-off characteristics are not very sharp. It is well suited for pulse applications.

16.3.2 Butterworth Filter The study hereunder is essentially confined to Butterworth filters as they are the maximally flat response filters. The roll-off can be made sharp with higher order filter design. These filters have Butterworth polynomial in the denominator of the transfer function of the filter. Butterworth polynomials and the coefficients of the Butterworth polynomials are shown in Tables 16.1 and 16.2, respectively. Table 16.1 Butterworth polynomials n, order of the polynomial

Polynomial (factored form)

1

( s + 1)

(s

2

2

)

+ 2 s +1

3

( s + 1) (s 2 + s + 1)

4

(s2 + 0.7654s + 1) (s2 + 1.8478s + 1)

5

(s + 1) (s2 + 0.6180s + 1) (s2 + 1.6180s + 1)

6

(s2 + 0.5176s + 1) (s2 + 1.4142s + 1) (s2 + 1.9319s + 1)

7

(s + 1) (s2 + 0.4450s + 1) (s2 + 1.2470s + 1) (s2 + 1.8019s + 1)

8

(s2 + 0.3986s + 1) (s2 + 1.1110s + 1) (s2 + 1.6630s + 1) (s2 + 1.9622s + 1)

Table 16.2 Coefficients of the Butterworth polynomials n

Polynomial

a1

1

s + a1

1

2

s 2 + a1s + a2

2

1

3

s 3 + a1s 2 + a2 s + a3

2

2

1

4

s 4 + a1s 3 + a2 s 2 + a3 s + a4

2.613

3.414

2.613

a2

a3

First-Order Low-Pass Butterworth Filter The first-order low-pass Butterworth filter is shown in Figure 16.11(a).

a4

1

830

Electronic Devices and Circuits

R2 − R1 +

R + Vi

+

VA

Vo

C

−

Figure 16.11 (a) First-order low-pass Butterworth filter

1 Vi j ωC VA = Vi = 1 1+ jwCR R+ j ωC

From Figure 16.11(a),

(16.13)

The amplifier in Figure 16.11(a) is a non-inverting amplifier. R Therefore, AF = 1 + 2 R1 Vo = VA AF =

AFVi 1 + jwCR

Vo AF = = Vi 1 + jwCR fH =

where

(16.14)

AF w 1+ j wH

AF

=

1+ j

f fH

1 2pRC

(16.15)

(16.16)

To ensure that the dc offset voltage is zero, bias compensation is provided. In the circuit in Figure 16.11(a), for dc the capacitor is open circuited and shorting Vi, the compensating resistance R is chosen as, R = R2R1 (Figure 16.11(b)). R2 R1 − +

+

R

Figure 16.11 (b) To determine the value of R

Vo

Active Filters

831

The design of the first-order low-pass Butterworth filter is illustrated in the following examples. Example 16.1 Design a low-pass first-order Butterworth filter with fH = 4 kHz and mid-band gain of 2. fH =

Solution:

1 2pRC

AF = 1 +

R2 =2 R1

Therefore, R2 = 1 ⇒R2 = R1 = 10 kΩ R1 R = R2R1 = 5 kΩ Therefore, C=

1 ≈ 0.008 µF 2 π × 5 × 103 × 4 × 103

Example 16.2 Design a non-inverting active low-pass filter circuit that has a gain of 10 at low frequencies, a corner frequency of 1590 Hz, and an input resistance of 10 kΩ. Solution: The voltage gain of a non-inverting operational amplifier is AF = 1 +

R2 = 10 R1

Choose R1 = 1 kΩ R2 = 9 ⇒R2 = 9R1 = 9 kΩ R1 Since the input resistance is given as 10 kΩ, R = 10 kΩ fH =

1 1 1 ⇒C = = = 10 nF 2pRC 2pfH R 2p × 1.59 × 103 × 10 × 103

Frequency Scaling A filter is usually designed for a specified cut-off frequency. However, sometimes it may become necessary to change the cut-off frequency. The procedure used to change the original cut-off frequency to a new cut-off frequency is called frequency scaling. For frequency scaling, instead of using a fixed resistance R, a potentiometer is used so that by varying

832

Electronic Devices and Circuits

R, the cut-off frequency can be changed (Figure 16.12).

R2 − R1 R +

+

+

VA

Vo

C

−

Vi

Figure 16.12 Frequency scaling

Second- and Higher-Order Butterworth Filters In order to have a steep roll-off so that the response of the filter approximates the ideal filter response, higher-order filters are the answer. A second-order low-pass filter will give a roll-off rate of −40 dB/decade. A second-order filter can be derived by cascading two first–order, low-pass filters, which obviously will have to use two op-amps. Second-order, low-pass and high-pass filters are best designed using a single op-amp, as a Sallen–Key or voltage-controlled voltage source (VCVS) topology.

Sallen–Key topology The general form of the Sallen–Key topology is shown in Figure 16.13. Y1, Y2, Y3, and Y4 are the admittances. It is required to find From Figure 16.13, the KCL equation at node A is

Vo . Vi

I1 − I 2 − I 3 = 0 or

(Vi −VA )Y1 = (VA −VB )Y2 + (VA −Vo )Y3 = 0 VY i 1 = VA (Y1 + Y2 + Y3 ) − VBY2 − VoY3

(16.17)

The KCL equation at node B is I2 − I4 = 0 or Therefore,

(VA −VB )Y2 − (VB − 0)Y4 = 0 VA =

VB =

VB (Y2 + Y4 ) Y2 Vo AF

(16.18)

(16.19)

Active Filters

833

where AF is the gain in the non-inverting mode. AF = 1 +

R2 R1

(16.20)

Substituting Eqn. (16.19) in Eqn. (16.18), VA =

Vo (Y2 + Y4 )

(16.21)

AFY2

Substituting Eqs (16.19) and (16.21) in Eqn. (16.17), VY i 1 =

VY i 1 =

Vo (Y2 + Y4 ) AFY2

Vo (Y2 + Y4 ) (Y1 + Y2 + Y3 ) − VoY22 − VoY3 AFY2 AFY2

=

V

(Y1 +Y2 +Y3 ) − Ao Y2 −VoY3

(16.22)

F

Vo (Y2 + Y4 ) (Y1 + Y2 + Y3 ) −Y22 −Y3 AFY2  AFY2

Therefore, VY i 1 =

 Vo YY 1 2 + Y4 (Y1 + Y2 + Y3 ) + Y3Y2 (1 − AF ) AFY2 Vo AFYY 1 2 = Vi YY + Y Y + Y + Y ( 1 2 4 1 2 3 ) + Y2Y3 (1 − AF )

(16.23)

R2 I1 +

−

A VA

R1 Y2

Y1

Vi I2 I3

B VB

Y4

Y3

+

+ Vo

I4

Figure 16.13 Sallen–Key topology

Second-Order Low-Pass Butterworth Filter The second-order, low-pass Sallen–Key filter is shown in Figure 16.14(a). Y1 = Y2 =

1 =G R

Y3 = Y4 = sC

834

Electronic Devices and Circuits

From Eqn. (16.23), H (s ) =

Vo AFG 2 = 2 Vi G + sC (2G + sC ) + GsC (1 − AF ) AFG 2 C2

=

G G2 3 − AF ) + 2 ( C C AF R 2C 2 = 1 1 3 − AF ) + 2 2 s2 + s ( RC RC s2 + s

(16.24)

R2 − R1

+ Vi

R

+

+ Vo

R C C

Figure 16.14 (a) Sallen–Key second-order, low-pass Butterworth filter

The transfer function of a second-order, low-pass system can, in general, be written as follows: H (s) =

AF ω o2 s + ζω o s + ω o2 2

(16.25)

where w o = w H , is the cut-off frequency and ζ is the damping factor. Comparing Eqs (16.24) and (16.25), 1 C R2 1 wo = RC

w o2 = or

zw o = Therefore,

(3 − AF ) or CR

2

(3 − AF ) z = RC CR

z = 3 − AF For the second order Butterworth polynomial is s 2 + 2 s + 1 3 − AF = 2

(16.26)

Active Filters

835

Therefore, AF = 3 − 2 = 1.585 But AF = 1 +

R2 R = 1.585 or 2 = 0.585 R1 R1

To Plot the Frequency Response Equation (16.25) can be written as follows: H (s ) =

Put s = jw , then

AF s zs + +1 w o2 w o

(16.27)

2

H ( jw ) =

AF w2 w − 2 + jz +1 wo wo

For a Butterworth filter, z = 2. Therefore, AF AF AF H ( jw ) = = = 2 2 4 2  w2  w2  w  w  1 + − 1 2 1 + +  w   w 2    w 2  w o  o o o When expressed in dB, 20 log10 H ( jw ) = 20 log10

For the n th -order filter,

H ( jw ) =

AF w  1+    wo 

(16.29) (16.30)

4

AF w  1+    wo 

(16.28)

2n

(16.31)

Example 16.3 (i) Design a second-order, Sallen–Key low-pass Butterworth filter having fH = 2 kHz, (ii) repeat the design for minimum dc offset, and (iii) plot the frequency response. 1 Solution: (i) fH = 2pRC Choose C = 0.01 µF. Therefore, 1 1 R= = = 7.96 kΩ 2pfHC 2p × 2 × 103 × 0.01 × 10 −6 R AF = 3 − 2 = 1.585 1.585 = 1 + 2 Þ R2 = 0.585 × R1 R1 Choose R1 = 10 kΩ. Then, R2 = 0.585 × 10 = 5.85 kΩ.

836

Electronic Devices and Circuits

(ii) Consider R1 = 10 kΩ and R2 = 5.85 kΩ. Under dc conditions the capacitors are open circuits and shorting Vi, 2R is the resistance from the noninverting terminal to ground (Figure 16.14(b)).

R2 R1 − +

+ Vo

R R

Figure 16.14 (b) Bias compensation

Therefore, for minimum dc offset, 2R = R1R2 =

10 × 5.85 = 3.69 kΩ , R = 1.85 kΩ. 10 + 5.85

Therefore, C=

1 1 = = 0.043 µF 2pfHC 2 π × 2 × 103 × 1.85 × 103

(iii)Using Eqn. (16.30), 20 log10 H ( jw ) = 20 log10

AF  f  1+    fo 

4

= 20 log10

1.585  f  1+   2 × 103 

4

For plotting the frequency response, the frequency range is taken from 0.1 fo (a decade below fo = 200 Hz) and 10 fo (a decade above fo = 20 kHz). See Table 16.3. Table 16.3 Variation of gain with frequency Frequency (Hz)

Gain in dB

200

4

500

3.98

1000

3.73

2000

1.00

4000

−8.4

8000

−20.08

16000

−31.06

20000

−35.99

Active Filters

837

The frequency response is plotted in Figure 16.15. Gain in dB 4 1

−40 dB/decade

−35.99 200

Hz 2000

20000

f

Figure 16.15 Frequency vs gain curve

Higher-Order Low-Pass Filters A first-order filter provides a −20 dB/decade roll-off and a second-order filter provides a −40 dB/decade roll-off in the stop band. Each increase in the order of the filter produces an additional roll-off of −20 dB/decade. For the nth-order filter, the roll-off rate in the stop band is ( n × − 20 dB/decade ) . Consequently, the response of the higher order filters corresponds to the response of the ideal filter. The transfer function of the third-order filter is of the following type: A AF H ( s ) = 2 F1 s + z 1s + 1 s +1 The fourth-order filter is of the following type: AF1 AF2 2 s + z 1s + 1 s + z 2 s + 1

H (s ) =

2

The fifth order-filter is of the following type: H (s ) =

AF1 AF 2 AF 2 s + z 1s + 1 s + z 2 s + 1 s + 1 2

The roll-off rate for different values of n is shown in Figure 16.16. Gain in dB 0

n=1

−20 db/decade

n=2 6

5

4

n=3 −40 −60 −80

−120 −100

−120 0.2

2

20

200

Figure 16.16 Roll-off rate in the stop band for different values of n

f

kHZ

838

Electronic Devices and Circuits

Example 16.4 Design a low-pass Butterworth filter with a corner frequency of 2 kHz and a rolloff rate in the stop band as −80 dB/decade. Solution: A roll-off rate in the stop band as −80 dB/decade is derived by a fourth-order filter. The tranfer function of the fourth-order filter is

H (s ) =

AF1 AF2 AF1 AF2 = s 2 + z 1s + 1 s 2 + z 2 s + 1 s 2 + 0.7654 s + 1 s 2 + 1.8478s + 1

For the Butterworth filter, z 1 = 0.765 and z 2 = 1.848 AF1 = 3 − z 1 = 3 − 0.765 = 2.235 = 1 +

R2 ⇒R2 = 1.235R1 R1

Choose R1 = 10 kΩ. Then R2 = 1.235R1 = 12.35 kΩ AF2 = 3 − z 2 = 3 − 1.848 = 1.152 = 1 +

R4 ⇒ R4 = 0.152R3 R3

Choose R3 = 10 kΩ. Then R4 = 0.152R3 = 1.52 kΩ Choose C = 0.01 µF Therefore, R=

1 1 = = 7.96 kΩ 3 2pfHC 2p × 2 × 10 × 0.01 × 10 −6

The designed circuit is shown in Figure 16.17. 1.52 kΩ 12.35 kΩ R4 R1 + Vi

R C

−

10 kΩ

8 kΩ R 8 kΩ C 0.01 µF

R3

R2

0.01 µF

− AF1 +

8 kΩ

8 kΩ

10 kΩ +

R

R C

C 0.01 µF

Figure 16.17 Designed circuit

0.01 µF

AF2

+ Vo

Active Filters

839

First-Order High-Pass Butterworth Filter The first-order, high-pass Butterworth filter is shown in Figure 16.18. R2 − R1 + Vi

+

+

VA

Vo

R

−

C

Figure 16.18 First-order, high-pass Butterworth filter

From Figure 16.18, VA = Vi

R 1 R+ j wC

= Vi

jwCR 1+ jwCR

The amplifier in Figure 16.18 is a non-inverting amplifier. R AF = 1 + 2 R1 Therefore,

(16.32)

(16.33)

jwCR 1 + jwCR w f j j Vo wL fL jwCR = H ( jw ) = AF = AF = AF w f Vi 1 + jwCR 1+ j 1+ j wL fL Vo = VA AF = AFVi

fL =

where

1 2pCR

H ( jw ) = AF

From Eqn. (16.36), (i) If f > fL, then H ( jw ) = AF

(16.34)

(16.35) f fL

 f  1+    fL 

(16.36) 2

840

Electronic Devices and Circuits

The response of the filter is shown in Figure 16.19. H(jw) AF 0.707AF

Pass band Stop band

fL

0

f

Figure 16.19 Response of the first-order, high-pass Butterworth filter

The design of the first-order, high-pass Butterworth filter is illustrated in the following example. Example 16.5 Design a first-order, high-pass Butterworth filter to have a cut-off frequency of 2 kHz and pass-band gain of 2. Plot its frequency response. Solution: Choose C = 0.01 µF. R =

1 1 = = 7.96 kΩ 2pCfL 2p × 0.01 × 10 −6 × 2 × 103 AF = 1 +

Therefore,

R2 =2 R1

R2 = R1 Choose R2 = R1 = 10 kΩ. Table 16.4 shows variation of gain with frequency.

20 log10

  f     fL H ( jw ) = 20 log10  AF 2   f    1+      fL   

Table 16.4 Variation of gain with frequency. Frequency (Hz) 200 500 1000 2000 4000 8000 16000 20000

Gain in dB −13.98 −6.285 −0.983 3.00 5.06 5.75 5.95 6.02

(16.37)

Active Filters

841

Second-Order, High-Pass Butterworth Filter The second-order, high-pass Butterworth filter is shown in Figure 16.20. R2 R1 −

Y1

Y2

+ Vi

C

+

+ Vo

C Y3

Y4

R

R

Figure 16.20 Second-order, high-pass Butterworth filter

From Eqn. (16.23), Vo AFYY 1 2 = Vi YY + Y Y + Y + Y 1 2 4( 1 2 3 ) + Y2Y3 (1 − AF ) From Figure 16.20, 1 =G R Vo AF s 2C 2 = H (s ) = 1 1  sC Vi s 2C 2 +  sC + sC +  + (1 − AF ) R R R Y1 = Y2 = sC , Y3 = Y4 =

=

AF s 2C 2 AF s 2 = sC s 1 1 s 2C 2 + 3 − AF ) + 2 s 2 + 3 − AF ) + 2 2 ( ( R RC R C R H (s ) = =

(16.38)

AF s 2 s 2 + s (3 − AF )w o + w o2 AF 1 + (3 − AF )

wo  wo  + s  s 

2

For the second-order, high-pass Butterworth filter z 1 = 2 and w o = w L. Therefore, 3 − AF = 2 or A F = 3 − 2 = 1.585 AF = 1 +

R2 = 1.585 R1

R2 = 0.585R1

(16.39)

842

Electronic Devices and Circuits

From Eqn. (16.39), AF

H ( jw ) =

2

 wo   wo   jw  − jz  w  + 1 AF

H ( jw ) =

2

 w o2   wo  1 − w 2  +  2 w 

H ( jw ) =

In general,

AF f  1+  o   f 

4

=

AF

= 2

w  1+  o  w 

AF f  1+  L   f 

f  1+  L   f 

AF f  1+  o   f 

4

(16.40) 4

AF

H ( jw ) =

4

=

(16.41) 2n

Example 16.6 Design a high-pass Butterworth filter, Figure 16.20, to have a cut-off frequency of 2 kHz and a roll-off rate of −40 dB/decade. Solution: AF = 1 +

R2 = 1.585, R2 = 0.585R1 R1

Choose R1 = 10 kΩ, R2 = 5.85 kΩ 2R = R1R2 =

R1R2 10 × 5.85 = = 3.69 kΩ R1 + R2 10 + 5.85

Therefore, R = 1.85 kΩ

fL =

1 2pCR

Hence, C=

1 1 = = 0.043 µF 2 πfL R 2 π × 2 × 103 × 1.85 × 103

16.3.3 Band-Pass Filter Band-pass filters can be of two types: (i) wide band-pass filter and (ii) narrow band-pass filter.

Active Filters

843

Wide Band-Pass Filter In wide band-pass filter, Q < 10. The response is typically as shown in Figure 16.21. Stop band

Stop band

AF 0.707 AF A

H(jw) Bandwidth

0

fL

f0

fH

f

Figure 16.21 Typical response of the wide band-pass filter

A wide band-pass filter is derived by cascading a high-pass filter and a low-pass filter. If the desired roll-off rate is −20 dB/decade, then first-order filters are connected in tandem and for a roll-off rate of −40 dB/decade, second-order filters are connected in tandem. Q, the quality factor is Q=

fo fo = BW fH − fL

(16.42)

A band-pass filter with a roll-off rate of −20 dB/decade is shown in Figure 16.22.

R3

R3

R

R − A1 +

+ Vi

−

A2

+ R1

+ Vo

C2

R2 V01

High pass filter

C1

Low pass filter

Figure 16.22 First-order, wide band-pass Butterworth filter

−

844

Electronic Devices and Circuits

From Eqn. (16.36),

f fL

H 2 ( jw ) = AF1

 f  1+    fH 

Therefore, AF1

H ( jw ) = H 2 ( jw ) × H1 ( jw ) =

H ( jw ) =

or

and

2

AF2

H1 ( jw ) =

And using Eqn. (16.31),

(16.43)

 f  1+    fL 

(16.44)

2

f fL

 f  1+    fL 

AF2 2

 f  1+    fH 

 f  AF    fL    f 2  f 2 1 +    1 +      fL     fH  

AF = AF1AF2

2

(16.45)

(16.46)

Example 16.7 Design a wide band-pass Butterworth filter to have a stop band roll-off of −20 dB/decade, mid-band gain of 4 and fL = 2 kHz , and fH = 4 kHz . Determine Q. Plot the response. Solution: (i) High-pass filter Choose C2 = 0.01 µF ⇒ R2 =

1 1 = = 7.96 kΩ 2pC2 fL 2p × 0.01 × 10 −6 × 2 × 103 AF2 = 1 +

Therefore,

R3 =2 R

R3 =R Choose R3 =R = 10 kΩ. (ii) Low-pass filter Choose C1 = 0.01 µF ⇒ R1 =

1 1 = = 3.98 kΩ 2pC1 fH 2p × 0.01 × 10 −6 × 4 × 103 AF2 = 1 +

R3 =2 R

Active Filters

845

Therefore, R3 =R Choose R3 = R = 10 kΩ fH − fL = 4 − 2 = 2 kHz ⇒ fo = Q=

fH fL = 4 × 2 = 2.83 kHz

fo 2.83 = = 1.42 ⇒ Q < 10 fH − f L 2

From Eqn. (16.45), H ( jw ) =

 f  4  2000    f 2  f 2 1 +    1 +      2000     4000  

Frequency (Hz)

Gain in dB

100

−13.98

200

−7.96

500

−0.33

1000

1.23

2000

8.06

3000

8.53

4000

8.06

8000

4.79

16000

−0.33

20000

−2.15

The band pass filter in Figure 16.22 uses two op-amps.

Multiple Feedback Topology A filter configuration in which a single Op-amp is used is called infinite gain multiple feedback (IGMF) configuration (Figure 16.23). LPF, HPF as well as BPF filters can be implemented using this configuration also. IGMF topology is used to have high Qs and high gain. From Figure 16.23, assuming a virtual ground at the input, the KCL equation at node A is I1 = I 2 + I 3 + I 4 or

(Vi −VA )Y1 = VAY2 + VAY4 + (VA −Vo )Y3 Vi Y1 = VA (Y1 + Y2 + Y3 + Y4 ) − VoY3

The KCL equation at node B is I 2 + I5 = 0

(16.47)

846

Electronic Devices and Circuits

I3

Y5

Y3 I2

I1 +

I5

A

Y1

Y2

VA

Vi

B − VB

+ Vo

+ I4

Y4

Figure 16.23 IGMF filter configuration

VAY2 + VoY5 = 0

or

VA =

−Y5 Vo Y2

(16.48)

Substituting Eqn. (16.48) in Eqn. (16.47), Vi Y1 = Vo

−Y5 (Y1 +Y2 +Y3 +Y4 ) −VoY3 Y2

Y5 (Y1 + Y2 + Y3 + Y4 ) + Y2Y3  Vi Y1 = −Vo   Y2   Vo −YY 1 2 = Vi Y5 (Y1 + Y2 + Y3 + Y4 ) + Y2Y3

(16.49)

IGMF Narrow Band-Pass Filter The IGMF narrow band pass filter is shown in Figure 16.24. For the circuit in Figure 16.24, 1 1 1 Y1 = = G1, Y2 = sC2 , Y3 = sC3, Y4 = = G4, Y5 = = G5 R1 R4 R5

R5

C3 +

(16.50)

C2

R1

−

Vi + R4

Figure 16.24 IGMF narrow band-pass filter

+ Vo

Active Filters

847

From Eqs (16.49) and (16.50), H (s) =

− sC2G1 G5 (G1 + G4 ) + G5 s (C2 + C3 ) + s 2C2C3

−G1 G (G + G4 ) G5 (C2 + C3 ) (16.51) + sC3 + 5 1 C2 sC2 The transfer function of an RLC parallel resonant circuit in Figure 16.25, driven by a current source G ′Vi is shown in Figure 16.26. =

+ C

L G

G′Vi

Vo −

Figure 16.25 RLC circuit 1 0.707

fL f0

fH

Figure 16.26 Frequency response

The response of the RLC circuit in Figure 16.25 is given as follows: H (s ) =

−G ′ 1 sC + +G sL

(16.52)

Comparing Eqs (16.51) and (16.52), G ′ = G1 and C = C3

(16.53)

1 G5 (G1 + G4 ) = sL sC2 L= and G=

C2 G5 (G1 + G4 )

(16.54)

G5 (C2 + C3 ) C2

(16.55)

848

Electronic Devices and Circuits

The resonant frequency of the RLC-tuned circuit is 1 LC

w o2 =

(16.56)

Therefore, using Eqs (16.53) and (16.54), w o2 for the narrow band pass filter is G (G + G4 ) 1 = 5 1 LC C2C3

w o2 =

(16.57)

From Eqs (16.52), (16.53), and (16.55), the gain at resonance is Ao =

−G1C2 R G C2 C2 −G ′ −G1 = = =− 5 =− 1 G G G5 (C2 + C3 ) G5 C2 + C3 R1 C2 + C3

(16.58)

If C2 = C3, Eqs (16.58) and (16.57) reduce to Ao = −

R5 2R1

(16.59)

G5 (G1 + G4 )

wo =

C

(16.60)

Q at resonance is Qo = w oCR = Using Eqn. (16.55), Qo =

w oC3 G

w oC3 w oC3C2 2pfoC3C2 = = G G5 (C2 + C3 ) G5 (C2 + C3 )

Bandwidth =

(16.61)

fo G5 (C2 + C3 ) = Qo 2pC2C3

(16.62)

G5 × 2C 1 = 2 pR5C 2pC

(16.63)

If C2 = C3, Eqn. (16.62) reduces to BW =

Example 16.8 Design an IGMF narrow band pass filter, Figure 16.24, to have fo = 2 kHz, Qo = 10 and gain of 20 at resonance. Solution: Choose C2 = C3 = C = 0.01 µF Qo =

2pfoC3C2 2pfoC 2 = = pfo R5C G5 (C2 + C3 ) 2G5C

Active Filters

R5 =

Qo 10 = = 159 kΩ 3 πfoC π × 2 × 10 × 0.01 × 10 −6

Ao =

R5 R 159 ⇒R1 = 5 = = 3.975 kΩ 2R1 2 Ao 2 × 20

849

(Cw o )2 = G5 (G1 + G4 )

From Eqn (16.60),

2

(G1 + G4 ) = R5 (Cw o )2 = 159 × 103 × (0.01 × 10 −6 × 2π × 2 × 103 )

= 2.51 × 10 −3

1 1 + = 2.51 × 10 −3 R4 R1 1 1 = 2.51 × 10 −3 − = 10 −3 (2.51 − 0.251) = 2.259 × 10 −3 R4 3.975 × 103 R4 =

1 = 442.7 Ω. 2.259 × 10 −3

The typical response of the narrow band-pass filter for different values of Q is shown in Figure 16.27. 0 Q=5 A0 in dB

10

0.1

1.0

10

f/f0

Figure 16.27 Response of the narrow band-pass filter for different Q

16.3.4 Band-Rejection Filter Band rejection (also called band elimination or band stop) filters can be of two types: (i) wide band-rejection filter and (ii) narrow band-rejection filter.

850

Electronic Devices and Circuits

Wide Band-Rejection Filter A wide band-rejection filter consists of a HPF, an LPF and a summing amplifier as shown in Figure 16.28. fL of the HPF should be greater than fH of the LPF. R3 R − A + 1 HPF C2

R4

Summing amplifier R4

R2

− A + 3 RC

R3

+ Vi −

R R1

R4

− A + 2 LPF

+ Vo −

RC = R4/3

C1

Figure 16.28 Wide band-rejection filter

The response of the filter is shown in Figure 16.29.

AF Pass band

0

Pass band

Stop band

fH

f0

fL

Figure 16.29 Response of the band-rejection filter

fo =

f L fH

Example 16.9 Design a wide band-rejection filter to have fL = 4 kHz and fH = 2 kHz. The pass band gain is required to be 2. Solution: High-pass filter: Choose C2 = 0.01 µF. Low-pass filter:

R2 =

1 1 = = 3.98 kΩ 2pC2 fL 2p × 0.01 × 10 −6 × 4 × 103

Active Filters

Choose C1 = 0.01 µF.

R1 =

851

1 1 = = 7.96 kΩ 2pC1 fH 2p × 0.01 × 10 −6 × 2 × 103

AF = 1 +

R3 =2 R

Therefore, R3 = R Choose R3 = R = 10 kΩ fH − fL = 4 − 2 = 2 kHz

fH fL = 4 × 2 = 2.83 kHz

fo =

Choose R4 = 12 kΩ. Therefore, RC =

R4 12 = = 4 kΩ 3 3

Narrow Band-Reject Filter A narrow band reject filter is also called a notch filter. A simple method of deriving a narrow band reject filter is to use a narrow band pass filter and a subtracting amplifier, as shown in Figure 16.30. Narrow BPF Vi

Summer f + −

V0

f0

fL f0 fH

A0

Figure 16.30 Notch filter

But in practice, the expression for the gain of the narrow band pass filter (Eqn. 16.58) shows that the pass band signal gets inverted. As such, a summing amplifier is used in place of a subtracting amplifier. Further, as the BPF has a gain of Ao, the input is also required to be increased by a factor Ao .

852

Electronic Devices and Circuits

A notch filter is usually implemented using a twin-T network as shown in Figure 16.31.

C

I1

VA

C

I2

−

A

Buffer

I3

Vi

VD = Vo

R/2

+

Vo RL

D R

R

VB B

I4

I5

2C I6

Figure 16.31 Notch filter using a twin-T network

The KCL equation at node A is I1 + I 2 + I 3 = 0 Therefore,

(Vi −VA ) sC + (Vo −VA ) sC −VA (2G ) = 0

(16.64)

sC (Vi + Vo ) = 2VA ( sC + G ) Therefore,

VA =

sC (Vi + Vo ) 2 ( sC + G )

(16.65)

The KCL equation at node B is I 4 + I5 + I6 = 0 Therefore,

(Vi −VB )G + (Vo −VB )G −VB (2sC ) = 0

(16.66)

G (Vi + Vo ) = 2VB ( sC + G ) Therefore,

VB =

G (Vi + Vo ) 2 ( sC + G )

The KCL equation at node D is I 2 + I5 = 0

(16.67)

Active Filters

853

Therefore,

(Vo −VA ) sC + (Vo −VB )G = 0 VA sC + VBG = Vo ( sC + G )

(16.68)

Substituting Eqs (16.65) and (16.67) in Eqn. (16.68), sC (Vi + Vo ) 2 ( sC + G )

× sC +

G (Vi + Vo ) 2 ( sC + G )

× G = Vo ( sC + G ) 2

s 2C 2 (Vi + Vo ) + G 2 (Vi + Vo ) = 2Vo ( sC + G )

(s C 2

2

(

)

2 + G 2 Vi = 2 ( sC + G ) − s 2C 2 + G 2 Vo  

)

(

)

= 2 s 2C 2 + 2G 2 + 4 sCG − s 2C 2 + G 2 Vo =  s 2C 2 + 4 sCG +G 2 Vo Therefore,

G s +  C 

2

2

Vo s 2C 2 + G 2 = H (s ) = 2 2 = Vi s C + 4 sCG +G 2

4 sG  G  s2 + +  C C

(16.69) 2

Substituting s = jw , then Eqn. (16.69) is H ( jw ) =

where w o =

G 1 = C RC

w o2 − w 2 w 2 − w o2 = 2 2 w − w + 4 jww o w − w o2 − 4 jww o

or

(16.70)

2 o

fo =

1 2pRC

(16.71)

Dividing Eqn.16.70 by w 2 − w 20 H ( jw ) =

and

H ( jw ) =

1 ww 0 1− j4 2 w − w 02 1 ww 0  2  1 +  ±4 2  w − w 20 

(16.72)

854

Electronic Devices and Circuits

At the 3 db frequency, H ( jw ) =

1 2

. Therefore, from Eqn. (16.72), ±4

ww 0 =1 w 2 − w 20

w 2 − w o2 = ±4ww 0

w 2 − ±4ww 0 − w 20 = 0

or 2

w  w   w  ± 4  w  − 1 = 0 o o

or

±4 ± 16 − 4 × 1 × −1 w = wo 2 ×1

Therefore,

( =(

fH = fL

and

) 5 − 2) f

5 + 2 fo = 4.24 fo

(16.73)

= 0.24 fo

(16.74)

o

Bandwidth = BW = fH − fL = 4 fo

(16.75)

The response of the notch filter is shown in Figure 16.32.

BW

1.0

0.707

f L f0

fH

Figure 16.32 Response of the notch filter

Example 16.10 Design a notch filter to have fo = 50 Hz. Use C = 0.05 µF. Calculate fH, fL, and BW. Solution: fo =

1 2pRC ∴

R=

1 1 = = 63.69 kΩ 2 p foC 2 × p × 50 × 0.05 × 10 −6 fH = 4.24 fo = 4.24 × 50 = 212 Hz

and

fL = 0.24 fo = 0.24 × 50 = 12 Hz Bandwidth = BW = fH − fL = 212 − 12 = 200 Hz

Active Filters

855

16.3.5 All-pass Filter An all-pass filter has a constant gain in the entire frequency range, and a phase response that changes linearly with frequency (Figure 16.33). R1

R1

VA Vi

R

− +

Vo

C

Figure 16.33 All-pass filter

Using the superposition theorem, grounding the input to the non-inverting input terminal, the amplifier is an inverting amplifier. Then −R1 (16.76) Vo1 = Vi = −Vi R1 Grounding the input to the inverting input terminal, the amplifier is a non-inverting amplifier. Then 1 Vi jwC (16.77) VA = Vi = 1 1 + jwCR R+ jwC  R 1 Vo2 = VA 1 + 1  = 2VA = 2Vi 1 + jwCR  R1  Vo = Vo1 + Vo2 = −Vi + 2Vi

(16.78)

Vi 2 − (1 + jwCR ) 1 1 − jwCR =  = Vi 1 + jwCR 1 + jwCR 1 + jwCR Vo 1 − jwCR = H ( jw ) = Vi 1 + jwCR 2

H ( jw ) =

The phase shift is

1 + (wCR )

2

1 + (wCR )

=1

 wCR  = −2 tan −1 (2pfCR ) f = −2 tan −1   1 

(16.79)

(16.80)

From Eqs (16.79) and (16.80), it can be noted that the filter has a gain of 1, but the phase shift changes as a function of frequency. It is known that when a signal is transmitted over a transmission line, its phase can change. An all-pass filter is used to compensate for such phase changes. As such, all pass-filters are also called as delay equalizers and phase correctors.

856

Electronic Devices and Circuits

Example 16.11 For the all-pass filter if the signal has a frequency of 1 kHz and uses a C of 0.05 µF, find f when (i) R = 1.6 kΩ and (ii) R = 3.2 kΩ. Solution: (i) f = −2 tan −1 (2pfCR )

(

= −2 tan −1 2p × 1 × 103 × 0.05 × 10 −6 × 1.6 × 103

)

= −2 tan −1 ( 0.5024 ) = −53.35°

(

(ii) f = −2 tan −1 2p × 1 × 103 × 0.05 × 10 −6 × 3.2 × 103

)

= −2 tan −1 (1.005) = −90°

16.3.6 Switched Capacitor Filter A switched capacitor is an element used for discrete time signal processing. It works by moving charges into and out of capacitors by using switches that are controlled by nonoverlapping signals, which means that not all switches are closed simultaneously. Filters implemented with these elements are termed switched-capacitor filters, and depend only on the ratios between capacitances. Switched capacitors are suitable for use in integrated circuits to construct resistors and capacitors accurately and economically.

SC Resistor Simulation The simplest switched capacitor (SC) circuit is the switched capacitor resistor, made of one capacitor C and two switches S1 and S2 controlled by two phase nonoverlapping 1 clock pulses f1 and f 2 . f1 and f 2 connect the capacitor with a given frequency f = , T alternately, to the input and the output (Figure 16.34).

V1

f1 0

S2

S1

T = 1/f

1

f2

f1

1

V2

C

f2 0

(a) Simple switched capacitor resistor

(b) Non-overlapping clock waveforms

R V1

V2 IR

(c) Resistor simulation

Figure 16.34 Switched-capacitor resistor

Active Filters

857

When S1 is closed, the charge on C at steady state is q1 = CV1 When S2 is closed, the charge on C at steady state is q2 = CV2 Assuming V1 > V2, the charge ∆q transferred is ∆q = q1 − q2 = C (V1 − V2 ) = CV

(16.81)

As charge ∆q is transferred at a rate f, the rate of transfer of charge per unit time is I = ∆qf =

∆q T

Therefore, the average current flowing is I=

CV T

(16.82)

From Figure 16.34(c) and using Eqn. (16.81), R=

V 1 V T = = = V C C fC I T

(16.83)

Thus the switched capacitor behaves like a lossless resistor whose value depends on capacitance C and switching frequency f. The SC resistor can replace a simple resistor in an integrated circuit, since it is easier to fabricate reliably with a wide range of values. Also its value can be adjusted by changing the switching frequency f. It may be said that it can be considered as a programmable resistance.

Switched Capacitor Integrator An integrator using an op-amp as an inverting amplifier is shown in Figure 16.35. Cf

R −

Vs

Vo +

Figure 16.35 Op-amp inverting integrator

Its output Vo in the s-domain is given as follows: Vo ( s ) =

−Vs ( s ) RCf s

(16.84)

858

Electronic Devices and Circuits

Now, R can be replaced by a switched capacitor (Figure 16.36). Cf

f1

f2 −

Vs

Vo C

+

Figure 16.36 Switched capacitor integrator

Using Eqs (16.83) and (16.84), Vo ( s ) =

−Vs ( s )  1   fC  Cf s

 C  V (s ) = −f   s  Cf  s

(16.85)

The switches in Figure 16.36 can, in fact, be replaced by MOS devices (Figure 16.37). Consider the second-order, low-pass filter shown in Figure 16.38 and its transfer function is given as follows: 1 Vo ( s ) R1R3C2C4 w o2 (16.86) = = 1 1 wo Vi ( s ) 2 2 2 s + s+ s + s + wo R3C4 R1R3C2C4 Q The circuit in Figure 16.38 can be converted into a switched capacitor filter using Eqn. (16.83). See Figure 16.39. 1 1 and R3 = R1 = fC1 fC3 (16.87)

f1

Cf

f2

−

Vs

Vo C

+

Figure 16.37 Switches in Figure 16.36 replaced by MOS devices

Active Filters

859

R1

C2 −

Vs R1

Vo R3

+

C4

Figure 16.38 Second-order, low-pass filter

C1

C2 −

Vs

Vo C1

+ C3

C4

Figure 16.39 Switched capacitor filter

Substituting the values in Eqn. (16.87) in Eqn. (16.86), 1  1  1   fC   fC  C2C4 Vo ( s ) 1 3 = 1 1 Vi ( s ) s2 + s+  1   1  1   fC   fC  C2C4  fC  C4 3 1 3 C1C3 2 f w o2 C2C4 = = w C CC s 2 + 3 fs + 1 3 f 2 s 2 + o s + w o2 C4 C2C4 Q

(16.88)

860

Electronic Devices and Circuits

Example 16.12 Design a low-pass filter shown in Figure 16.39 with fo = 15.9 kHz and Q = 5. The amplifier has a unity dc gain. Solution: From Eqn. (16.88), Vo ( s ) = Vi ( s )

w o2 1010 = 2 w s + 20000 s + 1010 s 2 + o s + w o2 Q

C1C3 2 f = 1010 C2C4

C3 f = 20000 C4

and

Choose f = 10 fo = 159 kHz C3 f = 20000 C4 C1C3 2 f = 1010 C2C4

C3 20000 = = 0.126 C4 159000 C1 1010 1010 = = = 31.45 C 2 C3 20000 × 15.9 × 103 f×f C4

and

Let C2 = 1 pF and C4 = 10 pF, then C1 = 31.45C2 = 31.45 × 1 = 31.45 pF C3 = 0.126C4 = 0.126 × 10 = 1.26 pF

Additional Solved Examples Example 16.13 For a first-order, unity-gain low-pass Butterworth filter with fH = 1 kHz and C = 0.1 µF. Find R. Solution: For the first-order, low-pass Butterworth filter Vo = Vi where fH =

AF f 1+ j fH

=

1 1+ j

f fH

1 2pRC R=

1 1 = = 1.59 kΩ 2 πfHC 2 π × 1 × 103 × 0.1 × 10 −6

Active Filters

861

Example 16.14 Design a low-pass Butterworth filter with a corner frequency of 2 kHz and a roll-off rate in the stop band as −100 dB/decade and the pass band gain of 2.575. Solution: A roll-off rate in the stop band as −100 dB/decade is derived by a fifth-order filter. The tranfer function of the fifth-order filter is H (s ) =

=

AF1 AF2 AF s 2 + z 1s + 1 s 2 + z 2 s + 1 s + 1

AF AF1 AF2 s 2 + 0.7654 s + 1 s 2 + 1.8478s + 1 s +1

For the Butterworth filter, z 1 = 0.765 and z 2 = 1.848, AF1 = 3 − z 1 = 3 − 0.765 = 2.235 = 1 +

R2 ⇒R2 = 1.235R1 R1

Choose R1 = 10 kΩ. Then R2 = 1.235R1 = 12.35 kΩ AF2 = 3 − z 2 = 3 − 1.848 = 1.152 = 1 +

R4 ⇒R4 = 0.152R3 R3

Choose R3 = 10 kΩ. Then R4 = 0.152R3 = 1.52 kΩ AF1AF2 = 2.235 × 1.152 = 2.575 For the the overall pass band gain to be 2.575, the first-order filter will have to have AF = 1.� Choose C = 0.01 µF Therefore, R=

1 1 = = 7.96 kΩ ≈ 8 kΩ 3 −6 2pfHC 2p × 2 × 10 × 0.01 × 10

The designed circuit is shown in Figure 16.40. 1.52 kΩ 12.35 kΩ R4

R2

R3

R1 + Vi

10 kΩ

8 kΩ R

R 8 kΩ C C

− AF1 +

8 kΩ

− +

AF2

− 8 kΩ

R

R

C 0.01 µF C

0.01 µF

10 kΩ

8 kΩ

0.01 µF

0.01 µF

Figure 16.40 Designed circuit

+

AF2

R C

0.01 µF

+ Vi

862

Electronic Devices and Circuits

Example 16.15 Design a first- order band reject filter, Figure 16.28, to have a lower cut-off frequency of 2000 Hz and a higher cut-off frequency of 400 kHz. Assume pass band gain as 2. Solution: High-pass filter: 1 1 = Choose C2 = 0.01 µF. R2 = = 7.96 kΩ 2pC2 fL 2p × 0.01 × 10 −6 × 2 × 103 AF2 = 1 +

R3 =2 R

Therefore, R3 = R Choose R3 = R = 10 kΩ Low-pass filter: Choose C1 = 0.01 µF.

R1 =

1 1 = = 39.81 kΩ 2pC1 fH 2p × 0.01 × 10 −6 × 400

AF2 = 1 + ∴

R3 =2 R

R3 = R

Choose R3 = R = 10 kΩ

Summary • Filters are frequency- selective electronic circuits that pass only the desired band of frequencies from the input to the output and reject or attenuate the unwanted frequencies. • Passive filters use only passive circuit components such as resistors, capacitors, and inductors; whereas, active filters use active circuit components such as transistors and op-amps in addition to the passive circuit components. • Butterworth filter is also called as maximally flat or flat–flat filter. These filters have a flat amplitudefrequency response up to the cut-off frequency and have a monotonic drop in gain with increase in frequency in the cut-off region. • In order to have a steep roll-off so that the response of the filter approximates the ideal filter response, higher order filters are used. A second-order, low-pass filter will give a roll-off rate of −40 dB/decade. In general, an nth order filter will give a roll-off rate of −20n dB/decade . • Second-order, low-pass and high-pass filters are best designed using a single op-amp, as a Sallen–Key or voltage-controlled voltage source (VCVS) topology. • A filter configuration in which a single op-amp is used to derive a band-pass filter is called infinite gain multiple feedback (IGMF) configuration. • An all-pass filter has a constant gain in the entire frequency range, and a phase-response that changes linearly with frequency. • The switched capacitor behaves like a lossless resistor whose value depends on capacitance C and switching frequency f. The SC resistor can replace a simple resistor in an integrated circuit, since it is easier to fabricate reliably with a wide range of values.

Active Filters

863

multiple ChoiCe QueStionS 1. Which one of the following filters significantly attenuates all frequencies below fc and passes all frequencies above fc ? (a) Low pass (b) High pass (c) Band pass (d) Band stop 2. Which one of the following filters rejects all frequencies within a specified band and passes all those outside this band? (a) Low pass (b) High pass (c) Band pass (d) Band stop 3. When a rapid roll-off in the stop band is required, the type of filter that is preferred is (a) Butterworth (b) Chebyshev (c) Bessel (d) Elliptical 4. In which filter, the bandwidth equals the cut-off frequency? (a) Low pass (b) High pass (c) Band pass (d) Band stop 5. The cut-off frequency is the frequency at which the filter response drops by ________ from the pass band. (a) −3 dB (b) −6 dB (c) −20 dB (d) 0 dB 6. The filter with a very flat response in the pass-band and a roll-off rate of –20 dB/decade/pole in the stop band is ________ (a) Butterworth (b) Chebyshev (c) Bessel (d) Elliptical 7. If the cut-off frequency of a low-pass filter is 2 kHz, its bandwidth is ________ (a) 4 kHz (b) 2 kHz (c) 8 kHz (d) 1 kHz 8. The roll-off rate in the stop band of a fourth-order filter is (a) −20 dB/decade (b) −40 dB/decade (c) −80 dB/decade (d) −60 dB/decade 9. A low-pass filter with a cut-off frequency of 4 kHz is cascaded with a high-pass filter with a cut-off frequency of 2 kHz. The resultant filter is (a) an all-pass filter (b) an all-stop filter (c) a band-reject filter (d) a band-pass filter 10. A high-pass filter with a cut-off frequency of 2 kHz is cascaded with a low-pass filter with a cut-off frequency of 4 kHz. The resultant filter is (a) an all-pass filter (b) an all-stop filter (c) a band-reject filter (d) a band-pass filter 11. A first-order, low-pass filter has R = 50 Ω and C = 5 μF. The frequency at which the gain falls by 3 dB is (a) 0.637 kHz (b) 6.37 kHz (c) 63.6 kHz (d) 636 kHz

864

Electronic Devices and Circuits

12. A filter that has a constant gain in the entire frequency range, and a phase response that changes linearly with frequency is (a) an all-pass filter (b) an all-stop filter (c) a band-reject filter (d) a band-pass filter

Short anSwer QueStionS 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

What is a filter? Where is the need for cascading first-order passive filters? Compare an ideal low-pass filter and a first-order RC low-pass. What are the main limitations of the passive filters? What are active filters and what are their main advantages? What is an all-pass filter and what is its main application? Classify active filters. What is a Butterworth filter? Why are higher-order filters used? What is a notch filter?

long anSwer QueStionS 1. Draw the circuit of a second-order, low-pass, Sallen–Key Butterworth filter and derive the expression for its transfer function. 2. Draw the circuit of a second-order, high-pass, Sallen–Key Butterworth filter and derive the expression for its transfer function. 3. Draw the circuit of a wide band pass filter and obtain the expression for its gain. 4. Draw the circuit of a wide band reject filter and obtain the expression for its gain. 5. Draw the circuit of the IGMF narrow band pass filter and derive the expression for its transfer function. 6. Draw the circuit of the twin-T notch filter and derive the expression for its transfer function. 7. What is an all pass filter? With the help of a neat circuit diagram, derive the expression for its gain. 8. Write short notes on switched capacitor filters.

unSolved problemS 1. Design a first-order wide band-pass Butterworth filter shown in Figure 16.22, to have a mid-band gain of 4, fL = 200 Hz and fH = 1 kHz . Determine Q. 2. Design a first -order wide band-reject Butterworth filter shown in Figure 16.28 to have a mid-band gain of 2, fH = 200 Hz and fL = 1 kHz . 3. Design an IGMF narrow band pass filter, Figure 16.24, to have fo = 2 kHz , BW = 200 Hz and gain of 50 at resonance. 4. Design a second-order, high-pass Butterworth filter, Figure 16.20, to have a cut-off frequency of 1 kHz. 5. Design a second-order, low-pass Butterworth filter, Figure 16.14, having fH = 1 kHz . The op-amp is required to have minimum dc offset voltage. 6. Design a first-order, high-pass Butterworth filter to have a cut-off frequency of 4 kHz and pass band gain of 4.

17

VOLTAGE REGULATORS

Learning objectives After reading this chapter, the reader will be able to        

17.1

Appreciate the need for voltage regulators to stabilize the output of a power supply Understand the principle of working of Zener and transistor shunt regulators Understand the principle of working of a transistor series regulator Design a complete feedback regulator Understand the need and methods to implement protection in a regulator Learn the operation of linear IC regulators Understand the working of switching regulators and the principle of SMPS Appreciate the need for voltage multipliers

INTRODUCTION

In chapter 3, we have considered the method of converting alternating (mains) signal into DC using rectifiers and eliminating or minimizing the ripple using filters circuits. The combination of transformer, rectifier, and filter (TRF) can be called a power supply that can be used for biasing transistor and FET circuits (Figure 17.1). But the voltage of the power supply should remain constant as any change in the power supply voltage can change the operating point of the circuit. IL ± ∆IL 230 V, + 50c/s Vi ± ∆Vi Mains input −

Transformer

+ Rectifier

Filter

VO ± ∆VO Load

−

Figure 17.1 TRF power supply

However, the output of the TRF power supply can change mainly due to the following reasons: (i) The input voltage Vi to the circuit can change due to fluctuations in mains voltage. As a result, the DC output voltage as well as the ripple in output can change. (ii) Due to changes in load resistance RL, the load current IL can change, resulting in a change in the output voltage. (iii) Due to changes in temperature, the device parameters can change, which in turn could change the output voltage.

866

Electronic Devices and Circuits

Therefore, the change in the output voltage of a power supply can be expressed as follows: ∆VO = SV ∆Vi + RO ∆I L + ST ∆T

(17.1)

where ∆VO is the possible change in the output voltage due to an incremental change ∆Vi in Vi or due to an incremental change ∆I L in load current IL or due to a small change ∆T in temperature T. The stability factor SV is defined as follows: SV =

∆VO ∆I L = 0, ∆T = 0 ∆Vi

(17.2)

In a good power supply, SV should be as small as possible. RO, the output resistance is defined as follows: RO =

∆VO ∆Vi = 0, ∆T = 0 ∆I L

(17.3)

RO should be small to ensure that the entire output voltage appears across the load. ST, the temperature coefficient is defined as follows: ST =

∆VO ∆Vi = 0, ∆I L = 0 ∆T

(17.4)

A small value of ST indicates that even for larger changes in T, there are negligible changes in VO. These parameters define the goodness of a power supply. The performance of a power supply is also specified in terms of three important factors: (i) source effect, (ii) load effect, and (iii) ripple rejection ratio. (i) Source effect: The ac input voltage to a rectifier (called power supply) does not remain constant. A change in the ac source voltage (also called the line voltage) can cause a change in the dc output voltage. The change in the dc output voltage for 10 percent change in source voltage is called source effect. Source effect = ∆Vo for a 10 percent change in Vi Another way of expressing the change in the dc output voltage due to source effect is by line regulation defined as follows: Line regulation =

Source effect ´100% Vi

(17.5)

Line regulation is also defined as the percentage change in the output voltage for a given change in the input voltage: Line regulation =

∆VO × 100% ∆Vi

(17.6)

For a good power supply, this value is small. (ii) Load effect: The dc voltage at the output of a power supply changes with load current. VO decreases with increase in IL and increases with decrease in IL. The load effect specifies how the output dc voltage changes when IL increases from 0 to IL(max).

Voltage Regulators

867

Load effect = ∆Vo for ∆I L(max ) Another way of expressing the change in the dc output voltage due to load effect is by load regulation, defined as follows: Load regulation =

Load effect ´100% Vi

(17.7)

Load regulation is also defined as the percentage change in the output voltage due to given change in the load current. This is normally expressed as follows: Load regulation =

VNL − VFL ×100% VNL

(17.8)

where VNL is the no-load voltage (RL = ) and VFL is the output voltage with maximum permissible load current IL. In a good power supply, the load regulation should be as small as possible. Ideally, it should be zero. (iii) Ripple rejection: Ripple rejection is the ability of the power supply to reject ripple and is usually expressed in dB. It is defined as the ratio of the peak-to-peak ripple voltage, Vor(pp) in the output to the peak-to-peak ripple voltage, Vir(pp) at the input. Ripple rejection = 20log10

Vor(pp) Vir(pp)

dB

(17.9)

(iv) Temperature stability: Temperature stability is defined as the change in the output voltage for a given change in temperature and is expressed in mV/°C. ∆VO (17.10) ∆T It can be noted that the output voltage can change due to many factors. Hence, there arises the need for voltage regulators, whose purpose is essentially to ensure that the output voltage almost remains constant, irrespective of the variations in the input voltage, load current, or temperature. Temperature stability =

17.2

CLASSIFICATION OF VOLTAGE REGULATORS

Depending on how regulation is achieved, voltage regulators are classified as (i) linear regulators and (ii) switching regulators. First, linear regulators using discrete components are considered, and subsequently the IC versions of these regulators are discussed. A linear voltage regulator senses the output voltage and adjusts the current source to maintain the output voltage at the desired value. Thus, it can be noted that a linear regulator uses a voltage-controlled current source to maintain the output constant. In this chapter, firstly we discuss about linear voltage regulators that use Zener diodes, transistors, or their combination for controlling the output voltage. Further, the controlling element, a Zener diode or transistor, can be used either in series with the load or in shunt with the load, based on which the linear regulators can be further classified as (i) shunt regulators (ii) series regulators. A shunt controller is shown in Figure 17.2 and a series controller is shown in Figure 17.3. The output voltage is sampled by a voltage sensor, and this signal controls the current I(v) to control VO.

868

Electronic Devices and Circuits IL +

+ I (v)

Vi

RL

Unregulated input

Vo

Voltage sensor − Shunt controlling element

−

Figure 17.2 A linear shunt regulator Series controlling element I (v)

IL

+

+

Vi

RL

Unregulated input

Vo

Voltage sensor −

−

Figure 17.3 A linear series regulator

17.3

SHUNT REGULATORS

As mentioned earlier, shunt regulators use the controlling element in shunt with the load. A Zener diode or a transistor can be used as the controlling elements.

17.3.1 Zener Diode as a Shunt Regulator Let us consider a Zener shunt regulator (Figure 17.4). The V–I characteristic of the Zener diode is shown in Figure 17.5. II TRF power supply

RS

+ Vi ± ∆Vi

IL +

IZ

VZ

RL

VO

−

−

Figure 17.4 Zener diode as a shunt regulator

IZ(min) is the minimum Zener current needed to keep the device ON and IZ(max) is the maximum Zener current the device can handle. Between IZ(min) and IZ(max), the Zener voltage varies between VZ(min) and VZ(max). For all practical purposes, it can be assumed that VZ remains constant as ∆VZ

(

)

= V − Vz(min)  , the change in the Zener voltage is negligible. The maximum dissipation in z( max )  

Voltage Regulators

869

IF

VZ(max) V

Z(min)

0

VR IZ(min)

Vγ

VF

IZ(max) IR

Figure 17.5 V–I characteristic of the Zener diode

the Zener diode and the breakdown voltage of the Zener are specified by the manufacturer in PZ(max ) the data sheet as PZ(max) and VZ. From these two values IZ(rated) can be calculated as I Z(rated) = . VZ Normally, the device is not operated at its rated current, but at a value slightly less than this. Hence, IZ(max) and IZ(min) are usually chosen as IZ(max) = 0.8 IZ(rated) and IZ(min) = 0.2 IZ(rated). Choosing the value of RS: Let the input voltageVi vary between Vi(max )  = (Vi − ∆Vi ) and Vi(min)  = (Vi − ∆Vi ), and let the load current I L vary between I L(max ) and I L(min). Let the variation of the Zener current be between the limits IZ(min) and IZ(max). From Figure 17.4, Vi= ( I Z + I L ) RS + VZ

(17.11)

(i) When the input voltageVi is Vi(min) to have VO at the output IL = IL(max) and correspondingly for the Zener to conduct, there should be minimum Zener current IZ(min). Hence, under this condition RS is RS(max) and Eqn. (17.11) gets modified as follows:

(

)

Vi(min) = I Z(min) + I L(max ) RS(max ) + VZ ∴ I Z(min) =

Vi(min) −VZ RS(max )

− I L(max )

(17.12)

Or RS(max ) =

Vi( min) - VZ I Z ( min) + I L ( max )

RS(max ) is the maximum allowable series resistance.

(17.13)

870

Electronic Devices and Circuits

(ii) When the input voltage Vi is Vi(max ) to have VO at the output IL = IL(min) and correspondingly for the Zener, there should be maximum Zener current IZ(max). Hence, under this condition, RS is RS(min) and Eqn. (17.11) gets modified as follows:

(

)

Vi(max ) = I Z(max ) + I L(min) RS(min) +VZ ∴ I Z(max ) =

Vi(max ) −VZ RS(min)

(17.14)

− I L(min)

Or RS( min) =

Vi( max ) - VZ

(17.15)

I Z ( max ) + I L ( min)

RS(min) is the minimum value series resistance. The value of RS, therefore, should lie somewhere between RS(max) and RS(min). Alternately, RS is taken as the average of these two values. Example 17.1 In the Zener regulator shown in Figure 17.6, Vi varies from 20 to 30 V, IL varies from 0 to 90 mA, and the Zener breakdown occurs at 5 mA. Find RS, IZ(max), RL(min), and RL(max). The Zener rating is 10 V and 2 W. Ii

RS

IL

+

+

Vi

IZ

VZ

RL

−

VO −

Figure 17.6 Zener regulator

Solution: Given Vi(min) = 20 V, VZ = 10 V, I Z(min) = 5 mA, I L(max ) = 90 mA, Vi(max ) = 30 V, IL(min) = 0 mA, and PZ(max) = 2 W. RS( max ) =

Vi( min) - VZ

I Z ( min) + I L ( max ) resistance.

=

20 - 10 = 105 Ω. Since RS < RS(max), choose RS = 100 Ω, a standard 5 + 90

I Z(max ) =

PZ(max ) VZ

=

2 = 200 mA 10

VZ VZ VZ 10 10 , RL(min) = = = 111 Ω, and RL(max) = = = ∞. We I L(max ) 90 0 IL I L(min) can choose RL as a 500 Ω potentiometer. We have VZ = 10 V. Since RL =

Example 17.2 Design a Zener regulator to supply a load current of 0 to 500 mA at 10 V. The dc input varies from 20 to 30 V. For stable operation, the minimum Zener current required is 10 mA.

Voltage Regulators

871

Solution: Given Vi(min) = 20 V, VZ = 10 V, I Z(min) = 10 mA, I L(max ) = 500 mA, Vi(max ) = 30 V, and IL(min) = 0 mA RS(max ) =

Vi(min) − VZ I Z(min) + I L(max )

I Z(max ) + I L(min) =

Vi(max ) − VZ RS

=

=

20 − 10 = 19.6 Ω. Choose RS = 10 Ω 10 + 500

30 − 10 = 2 A, which is I Z(max ) since I L(min) = 0. 10

The maximum current through RS = Ii = I Z(max ) + I L(max ) = 2 + 0.5 = 2.5 A. 2

Therefore, the power rating of RS = I i2 RS = ( 2.5) × 10 = 62.5 W. The power rating of the Zener = VZ I Z(max ) = 10 × 2 = 20 W. Choose a Zener with PZ > 25 W. Stability factor for Zener regulator: The stability factor is defined in Eqn. (17.2) as follows: SV =

∆V0 ∆I L = 0, ∆T = 0 ∆Vi

Let an incremental change in the input voltage Vi give rise to an incremental change in the output ∆VZ voltage Vo. Let rZ be the ac resistance of the Zener diode which is given as rZ = (Figure 17.7). ∆I Z When there is an incremental change in Vi, there are corresponding changes in Ii, Vo, IZ, and IL.

−VZ

∆VZ

0

∆IZ

−IZ

Figure 17.7 To calculate rz of the Zener diode

From Figure 17.6, V V  Vi = I i RS + Vo = ( I z + I L ) RS + Vo =  o + o  RS + Vo = Vo  rz RL  ∴ Vo =

Vi  RS RS  1+ r + R  z L

 RS RS  1+ r + R  z L

(17.16)

(17.17)

872

Electronic Devices and Circuits

∂Vo 1 = SV = ∂Vi  RS RS  1+ r + R  Z L When RL = ∞. SV =

(17.18)

rZ rZ + RS

If RL »RS and rZ «RS, Eqn. (17.18) reduces to SV =

1  RS RS  1 + r + R  Z L

≈

r 1 ≈ Z RS RS rZ

(17.19)

SV is small only when RS is large. To evaluate the performance of the Zener diode regulator, we need to calculate source effect, line regulation, load effect, load regulation, and ripple rejection ratio. For this, we need to draw the ac circuit by replacing the Zener diode with its dynamic resistance, rZ, as shown in Figure 17.8. RS + ∆Vi

+ rZ

RL

−

∆Vo −

Figure 17.8 AC circuit of Figure 17.6

From Figure 17.8, ∆Vo = ∆Vi

rZ || RL

(17.20)

RS + ( rZ || RL )

The source effect is determined using Eqn. (17.20). Ripple rejection =

rZ || RL Vr o = Vr i RS + ( rZ || RL )

(17.21)

Output resistance: To calculate the load effect, the output resistance of the regulator is to be determined. The output resistance is calculated with RL = ∞ (open the load) and Vi = 0 (short the input voltage source). Imposing these conditions on Figure 17.8, we get the circuit in Figure 17.9. RS

Set Vi = 0

Open RL rZ

Ro

Figure 17.9 Circuit to calculate Ro

Voltage Regulators

873

From Figure 17.9, Ro = rZ || RS

(17.22)

Load effect is ∆Vo = ∆I L ( rZ || RS )

(17.23)

Example 17.3 Design a Zener regulator to deliver 6.8 V dc voltage. The unregulated input is 20 V to produce a maximum load current. Calculate RS and the maximum load current. IZ(min) = 0. Solution: From the data sheet, choose Zener diode that has VZ = 6.8 V and PZ = 500 mW. I Z(max ) =

PZ 500 mW = = 73.53 mA ≈ I i(max ) ,since I Z(min) = 0 6.8 V VZ

I i(max ) = I L(max ) + I Z(min) = 73.53 mA RS =

Vi - VZ 20 - 6.8 = = 180 W 73.53 I Z ( max )

(

2 Dissipation in RS = I i(max) RS = 73.53 × 10 −3

2

)

× 180 = 0.98 . W

From the data sheet, select I Z(min). Let I Z(min) = 5 mA ∴ I L(max ) = I i(max ) − I Z(min) = 73.53 − 5 = 68.53 mA Example 17.4 For the circuit in Example 17.3, if rZ = 5 Ω, determine (i) source effect, (ii) line regulation, (iii) load effect, (iv) load regulation, and (v) ripple rejection ratio. Solution: (i) Source effect ∆Vi = 10% of 20 V = 2 V RL =

DVo = DVi

(ii) Line regulation =

Vo 6.8 = = 99.23 W I L ( max ) 68.53 ´ 10 -3

rZ || RL 5 || 99.23 = 2´ = 51.53 mV RS + ( rZ || RL ) 180 + (5 || 99.23)

51.53 × 10 −3 × 100 = 0.76% 6.8

(iii) Load effect = ∆Vo = ∆I L ( rZ || RS ) = 68.53 ´ 10 -3 (5 || 180 ) = 333.4 mV (iv) Load regulation =

333.4 × 10 −3 × 100 = 4.9% 6.8

(v) Ripple rejection =

rZ || RL 5 || 99.23 Vr o = = = 0.025 Vr i RS + ( rZ || RL ) 180 + (5 || 99.23)

874

Electronic Devices and Circuits

The power dissipation capability of the Zener diode is PD(max) = VZIZ(max)., which is normally specified at 25°C. However, at elevated temperatures, the power dissipation capability of the Zener diode decreases. As the Zener diode exhibits negative temperature coefficient, a Z, VZ decreases with increase in temperature. If a Z = − 0.06%/°C and VZ = 3.6 V at 25°C, then VZ at 100°C is given as follows: VZ (at 100°C) = VZ + ∆VZ

(17.24)

where ∆VZ = VZ a Z (T-25), æ - 0.06 ö \ DVZ = 3.6 ´ ç ÷ ´ 75 = - 0.162 V è 100 ø VZ (at 100°C) = 3.6−0.162=3.438 V Zener diodes normally operate below 6 V Avalanche and Zener diodes are generally called Zener diodes although the principle of operation is different. An avalanche diode has a positive temperature coefficient, that is, VZ increases with temperature. If az = 0.06%/°C and VZ=10 V at 25°C, then VZ at 100°C is given as follows: where ∆VZ = VZ a Z (T-25)

VZ (at 100°C) = VZ + ∆VZ

(17.25)

æ 0.06 ö \VZ = 10 ´ ç ÷ ´ 75 = 0.45 V è 100 ø VZ (at 100°C) = 10+0.45 = 10.45 V The main limitations of the simple Zener regulator are that (i) the Zener current varies by larger amounts, (ii) relatively poor regulation, and (iii) large amount of dissipation occurs both in the Zener diode and in RS, when compared to RL.

17.3.2 Basic Transistor Shunt Regulator The main limitation of the Zener shunt regulator is that to control the output voltage, the Zener current varies by wide limits. On the contrary, it may be preferable that for better control, smaller current variations can control the variations in the output voltage. Such a requirement is satisfied by a transistor shunt regulator (Figure 17.10). In this circuit, the Zener supplies the base current to the transistor. A series resistance RS is included and the drop across this controls the output voltage. The current Ii is given as follows: Ii = IB + IC + IL

(17.26)

The output voltage VO is given as follows: Vo = VZ + VBE

(17.27)

Also Vo = Vi − IiRS = Vi − (IB + IC + IL) RS

(17.28)

From Eqn. (17.27), since both VZ and VBE are supposed to remain constant, VO remains constant. However, if Vi increases for some reason or the other, then VO also increases. Since VZ remains

Voltage Regulators

875

+VR− Ii

RS

+ + VZ − IB

IZ Unregulated

D

Vi

IC

IL +

Q RL

+ VBE

Vo −

−

Figure 17.10 Basic transistor shunt regulator

constant, VBE increases. Hence, IB increases resulting in larger IC because I C = hFE I B. Consequently, Ii increases and thereby the voltage drop across RS increases and VO is once again brought back to the desired value. This can be expressed as follows: ↑ Vi →↑ VO →↑ VBE →↑ I B →↑ I C →↑ I i → ↑ VR →↓ VO

(17.29)

The arrow pointing upward (↑) represents an increase in the value of the variable and an arrow pointing downward (↓) represents a decrease in the value of the variable. The above representation is read thus: Increase in Vi leads to (→) increase in VO. Increase in VO leads to increase in VBE. Increase in VBE leads to increase in IB. Increase in IB leads to increase in IC. Increase in IC leads to increase in Ii. Increase in Ii leads to increase in VR, the voltage drop across RS. Increase in VR leads to decrease in VO. Alternately, decrease in Vi leads to decrease in VO. Decrease in VO leads to decrease in VBE. Decrease in VBE leads to decrease in IB. Decrease in IB leads to decrease in IC. Decrease in IC leads to decrease in Ii. Decrease in Ii leads to decrease in VR, the voltage drop across RS. Decrease in VR leads to increase in VO. VO is brought back to the desired value. ↓ Vi →↓ VO →↓ VBE →↓ I B →↓ I C →↓ I i → ↓ VR →↑ VO

(17.30)

Thus, a transistor shunt regulator takes care of the changes in the input voltage Vi and maintains the output VO constant. If RL decreases, then IL increases and VO decreases. Decrease in VO leads to decrease in VBE, which in turn leads to a decrease in IB. Decrease in IB in turn decreases IC. Hence, Ii decreases and so does VR. Therefore, VO increases. VO is once again brought back to the required value. This condition is represented below: ↓ RL →↑ I L →↓VO →↓ VBE →↓ I B →↓ I C →↓ I i →↓VR →↑ VO

(17.31)

Thus, the regulator will take care of the changes in load current. Example 17.5 For the transistor shunt regulator shown in Figure 17.11, calculate the regulated output voltage and the circuit currents. Solution: The load voltage VO = VZ + VBE = 6.8 + 0.7 = 7.5 V For the given, RL, IL =

VO 7.5 = = 30 mA. RL 250

876

Electronic Devices and Circuits

Vi − VO 25 − 7.5 = = 175 mA RS 100 Therefore, the collector current IC, since IZ = IB is small, is IC = Ii − IL = 175 − 30 = 145 mA

When Vi = 25 V, Ii =

Ii RS = 100 + IZ Vi = 25 V

−

D

+ VZ = 6.8 V − IB

IC IL + Q

RL = 250

+ VBE = 0.7 V −

VO −

Figure 17.11 Transistor shunt regulator

Example 17.6 Design the transistor shunt regulator shown in Figure 17.10 to maintain the output voltage constant at 10 V. The maximum permissible load current is 500 mA. IC = 10 mA and hFE = 50. The input voltage varies as 20 ± 10%. VBE of the transistor is 0.7 V. Solution: Given VO = 10 V, VBE = 0.7 V, and IL = 500 mA. VO = VZ + VBE ∴VZ = VO − VBE = 10 − 0.7 = 9.3 V Since Vi varies as 20 ± 10%, Vi(max ) = 22 V and Vi(min) = 18 V Since IC and IB are small when compared to IL, Ii = IL. Therefore, RS = 2 and its wattage is ( 0.5) × 24  = 6 W.   RL(min) =

Vi(max ) − VO IL

=

22 − 10 = 24 Ω 500

VO 10 2 = = 20 Ω and its wattage is ( 0.5) × 20  = 5 W.   I L 500

I C 10 = = 0.2 mA and PZ = VZ I Z = 9.3×0.2 = 1.86 mW. hFE 50 Choose a Zener with VZ = 9.3 V and having a PZ = 10 mW.

IB = IZ =

VCE = 10 V and IC = 10 mA. Therefore, PD = 10 V × 10 mA = 100 mW. Choose a transistor with PD(max) =250 mW. Stability factor SV for the transistor shunt regulator: The stability factor SV is defined with IL = 0, that is change in load current is zero. SV is calculated using the small signal model of Figure 17.10 as shown in Figure 17.12. From Figure 17.12, Vi = Vo + ( I b + I c + I L ) RS = Vo + ( I b + hfe I b + I L ) RS ≈ Vo + hfe I b RS + I L RS

(17.32)

Voltage Regulators

Ii

877

RS Collector

+ rz

Iz

Ic IL

Vi

+

Base hie

RL

Vo

hfeIb

Ib

−

− Emitter

Figure 17.12 AC circuit to calculate SV

since I b « hfe I b. But from Figure 17.12, Vo (rZ + hie )

(17.33)

Vi = hfe I b RS + Vo + I L RS

(17.34)

Ib = and

Using Eqn. (17.33),  V   h R  Vi = hfe  o  RS + Vo+I L RS = Vo 1+ fe S  + I L RS r h + r  Z ie  Z + hie   ∴Vo =

∂Vo = SV = ∂Vi

Vi − I L RS h R 1 + fe S rZ + hie

rZ + hie h 1 1 ≈ ie = = hfe RS rZ + hie + hfe RS hfe RS hfe 1+ R rZ + hie hie S

since hfe RS » ( rZ + hie ) and rZ « hie. We know that SV =

1 gm RS

(17.35)

(17.36)

hfe = gm. Therefore, hie (17.37)

From Eqn. (17.36), it can be noted that regulation can be improved by using a transistor with larger hfe. I Advantage of a transistor shunt regulator: Since I Z = I B = C , the changes in IZ are reduced by a hFE factor h ( = b ). FE

dc

Limitations of a transistor shunt regulator: (i) There is an appreciable power loss across the series resistance RS; (ii) a large current flows through the transistor. Hence, the transistor chosen should have a larger power dissipation capability; (iii) overload or short circuit protection cannot be

878

Electronic Devices and Circuits

implemented in a shunt regulator; and (iv) the output strictly cannot be maintained constant because VBE and VZ are likely to change with temperature.

17.4

SERIES REGULATORS

In series regulators, the controlling element is connected in series with the load. The controlling element usually is a transistor, whose resistance either increases or decreases depending on whether the output is increasing or decreasing.

17.4.1 Transistor Series Regulator A transistor series regulator is shown in Figure 17.13. The Zener diode is used as a reference element. The assumption is that VZ almost remains constant. The transistor is used as an emitter follower. Current passing through the transistor controls the resistance between the collector and emitter terminals, and hence the output voltage. The transistor is called the series pass transistor. The output voltage VO can change due to variations in Vi, IL, or temperature. IL can change due to temperature variations or due to variations in RL, and hence the influence of temperature variations can be taken care of to some extent when load current variations are taken into account. Hence, we see how the regulator works for changes in Vi and IL. Ii

VCE Q

+

+

IR = IB + IZ

Vi Unregulated input

R

− +

VBE

IB

+

D

+ VZ −

IZ

IL

−

RL

VO −

−

Figure 17.13 Transistor series regulator

From Figure 17.13, writing the KVL equation of the output loop, VO =VZ − VBE or VBE = VZ − VO

(17.38)

Also VO =Vi − VCE

(17.39)

1. Changes in Vi : The input voltage changes by Vi ± ∆Vi. (i) First consider when the input voltage increases by ∆Vi . When Vi increases, VO increases. From Eqn. (17.38), when VO increases VBE decreases which in turn decreases IB. Decrease in IB increases VCE. When VCE increases, VO is brought back to the desired value. This can be represented as follows: ↑ Vi →↑ VO →↓ VBE →↓ I B →↑ VCE →↓ VO

(17.40)

(ii) Now consider the situation when Vi decreases. When Vi decrease Vo decreases. From Eqn. (17.38), VBE increases. Increase in VBE gives rise to an increase in IB. Increase in IB reduces VCE, and hence VO is once again brought back to the required value.

Voltage Regulators

↓ Vi →↓ VO →↑ VBE →↑ I B → ↓ VCE →↑ VO

879

(17.41)

2. Changes in IL: (i) If RL decreases, then IL increases and VO decreases. Decrease in VO leads to increase in VBE which in turn leads to an increase in IB. Increase in IB in turn decreases VCE. Therefore, VO increases. VO is once again brought back to the required value. This condition is represented below: ↓ RL →↑ I L →↓VO →↑ VBE →↑ I B → ↓VCE →↑ VO

(17.42)

(ii) If RL increases, then IL decreases and VO increases. Increase in VO leads to decrease in VBE which in turn leads to a decrease in IB. Decrease in IB in turn increases VCE. Therefore, VO decreases. VO is once again brought back to the required value. This condition is represented below: ↑ RL →↓ I L →↑VO →↓ VBE →↓ I B → ↑VCE →↓ VO

(17.43)

Thus, this regulator maintains the output voltage constant irrespective of the variations in Vi or IL. Advantage of a transistor series regulator: Overload or short-circuit protection can be implemented Limitations of a transistor series regulator: (i) VO strictly cannot be maintained constant because both VBE and VZ can change with temperature (ii) The power dissipation in the series pass transistor, PD (= VCEIC) becomes larger for larger load currents. Stability factor SV for the transistor series regulator: The stability factor SV is defined with IL = 0, that is, change in load current is zero. The circuit in Figure 17.13 is redrawn as in Figure 17.14. The incremental equivalent circuit is shown in Figure 17.15. SV is calculated using the small-signal model of Figure 17.15 as shown in Figure 17.16. + R Q Vi Unregulated input D

+ VZ −

−

+ RL

VO −

Figure 17.14 Redrawn circuit of Figure 17.13

Thevenizing the circuit at B: Vth = Vi

rZ and Rth = rZ //R ≈ rZ R + rZ

880

Electronic Devices and Circuits

+ R B

Q

Vi +

rZ RL

Vo −

−

Figure 17.15 Circuit of Figure 17.14 with Zener replaced by rZ

The ac circuit of Figure 17.15 is drawn in Figure 17.16. The emitter follower has unity voltage R +h gain and output resistance as S ie . In the present case, RS = rZ. Hence, the output circuit is hfe drawn as in Figure 17.16.

rZ Q

+ +

Vbe − Vi rZ/ (R + rZ)

−

RL

+ Vo −

Figure 17.16 AC circuit of Figure 17.15 (rZ + hie) / hfe

+ Vi rZ / (R + rZ) RL −

+ Vo −

Figure 17.17 Output circuit

From Figure 17.17, Vo = Vi

If

(rZ + hie ) « R hfe

L

rZ ´ R + rZ

, then Eqn. (17.44) reduces to

RL r +h RL + Z ie . hfe

(17.44)

Voltage Regulators

Vo = Vi

rZ R + rZ

881

(17.45)

∂Vo r = SV = Z ∂Vi R + rZ

(17.46)

SV is small when R is large. Example 17.7 Design the series voltage regulator shown in Figure 17.13 to deliver a load current of 1.5 A and a constant output voltage of 9.7 V. The unregulated input varies as 20 ± 10%, VBE = 0.7 V, IZ = 10 mA, and hFE = 40. Solution: VO = VZ − VBE or VZ = VO + VBE = 9.7 + 0.7 = 10.4 V and IZ = 10 mA. Therefore, PZ = 10.4 × 10 = 0.104 W. I 1.5 IL = IC = 1.5 A and hFE = 40. Therefore, IB = C = = 37.5 mA. Given IZ = 10 mA. hFE 40 Therefore, IR = IZ + IB = 37.5 + 10 = 47.5 mA. R(max) =

Vi(max ) − VZ IR

Vi(max) = 20 + 2 = 22 V and Vi(min) = 20 – 2 = 18 V Vi(min) − VZ 18 − 10.4 22 − 10.4 = = 244 Ω and R(min) = = = 160 Ω 47.5 47.5 47.5

R(min) + R(max )

(

)

2 244 + 160 = = 202 Ω and its wattage is  47.5 × 10 −3 × 202  = 0.456 W   2 2 VCE(max) = Vi(max ) − VO = 22 −9.7 = 12.3 V and IL = IC = 1.5 A. PD = 12.3 × 1.5 = 18.45 W

R=

Output resistance: To find out the output resistance of the series regulator, set Vi = 0 and RL = ∞ in Figure 17.13 and replace the devices by their incremental models (Figure 17.18). The equivalent circuit of Figure 17.18 is shown in Figure 17.19. In Figure 17.19, R is omitted since, normally, R>>rZ. Find I

Open RL Introduce V

R Set Vi = 0 rZ

Ro

Figure 17.18 Circuit to calculate Ro

From Figure 17.19, V = I b ( rZ + hie ) and I = I b (1 + hfe )

882

Electronic Devices and Circuits Ib B

E

Ib(1 + hfe) I

hie rZ

− V hfeIb + C

Figure 17.19 Simplified equivalent circuit

∴ Ro =

V I b ( rZ + hie ) rZ + hie = = 1 + hfe I I b (1 + hfe )

(17.47)

17.4.2 Improved Series Regulator The circuit in Figure 17.20 is an improved series voltage regulator. R1 and R2 combination is the sampling and feedback network. The Zener diode is used as a reference element. R2 V2 = VO = bVo. As Vo changes, bVo changes. bVo = VZ + VBE2 . VZ practically remains R1 + R2 constant. So, when bVo changes, VBE2 changes. Hence IB2 changes and controls IL. Ii

+

VCE

IC1

Q1

+

− +

IB1 + IC2 R4 Vi Unregulated input

IL

IB1

+

VBE1 + IB2 VZ −

IC2 Q2

+ VBE2 −

R1

−

RL

+

VO −

V2 = βVo R3

R2 −

Figure 17.20 Improved series regulator

(i) Let VO increase from the desired value. Then bVo increases. Hence, VBE2 increases. Therefore, IB2 increases. As a result, IC2 increases. Hence, the drop across R4 increases and the voltage at the base of Q1 decreases. Consequently, IB1 decreases. The result is that IC1 = IL decreases and VO is brought back to the desired value. (ii) Alternately, let VO decrease from the desired value. Then bVo decreases. Hence, VBE2 decreases. Therefore, IB2 decreases. As a result, IC2 decreases. Hence the drop across R4 decreases and the voltage at the base of Q1 increases. Consequently, IB1 increases. The result is that IC1 = IL increases and VO is brought back to the desired value. We have V2 = VO

R2 = bVO R1 + R2

Voltage Regulators

883

Also bVO = VZ + VBE2 ∴VO

R2 = VZ + VBE2 R1 + R2

Hence,  R + R2  VO = (VZ + VBE2 )  1  R2 

(17.48)

Example 17.8 For the series regulator circuit shown in Figure 17.20, VZ = 6.8 V, VBE2 = 0.7 V, R1 = 20 kΩ, and R2 = 30 kΩ. Calculate the output voltage.  R + R2   20 + 30  Solution: Vo = (VZ + VBE2 )  1 = (6.8 + 0.7 )  = 12.5 V   30   R2 

17.5

OVERLOAD AND SHORT-CIRCUIT PROTECTION IN REGULATORS

When a regulated power supply is used, it is possible that there could be an overload, that is, RL may decrease. Hence, the load current increases with the resultant decrease in output voltage. Or sometimes, it may be possible that the output terminals of the power supply may accidentally get shorted, resulting in a very large load current, which will damage the regulator and the associated components. To avoid these problems, overload or shortcircuit protection is usually provided in the regulated power supplies. It is easy to implement protection circuit in a series regulator. The most commonly used current limiting circuits are (i) constant current limiting, (ii) fold-back current limiting, also called voltage dependent current limiting.

17.5.1 Constant Current Limiting in a Series Regulator From Figure 17.13, it can be noted that if RL decreases, IL (= IC) increases. Sometimes, IL may be so large that the dissipation that can occur in the transistor, PD may be much larger than PD(max) specified for the transistor. This could damage the transistor. To avoid this, overload protection is used in the regulator. Figure 17.21 shows the method to implement overload protection in a series regulator. A small sensing resistor RSC is connected in series with the load RL. Two diodes D1 and D2 are connected from the base of the transistor to the output terminal. The voltage drop across RSC is ILRSC. The diodes D1 and D2 conduct only when the voltage drop across them is at least 2Vγ =[(Vγ + Vγ)]. But (VBE + ILRSC) is the voltage drop across the two diodes. However, VBE ≈ Vγ. Hence for the diodes to conduct, the drop across RSC should be atleast Vγ. RSC is adjusted such that as long as IL is less than the specified maximum, the drop across RSC is less than Vγ. Hence, the diodes are OFF. If now for any reason, IL>IL(max), D1 and D2 are ON (behave as short circuits, ideally) (Figure 17.22). Hence, part of the base current is directed to the output as IF, thereby reducing the base current to the transistor. Hence the load current is limited to IL(max). This ensures safety of the regulator.

884

Electronic Devices and Circuits

Ii

IC

+ VCE − Q

+

IB

+

RSC

IL

IL

− VBE

+

R

Vi IR = IB + IZ Unregulated input

RL + D1 VZ −

IZ D

−

VO

D2

−

Figure 17.21 Overload protection in a series regulator Ii

RSC

+ VCE − Q

+

IB

IR = IB + IZ

+

− VBE

R

Vi Unregulated input

IZ

IL

IL +

IF RL

ON ON + D1 D2 VZ −

D

−

VO −

Figure 17.22 D1 and D2 conduct when there is an overload

As a small change in the base current can cause a large change in the collector current, a transistor may be used in place of the two protective diodes to effectively bypass a large amount of base current to the load, if needed (Figure 17.23). As long as IL is less than IL(max), the drop across RSC is less than VBE. Hence, Q2 is OFF. Normal regulator action takes place. If IL is more than IL(max), Q2 conducts, thereby directing a larger portion of the base current of Q1 to load as IC2. Hence, IL is not allowed to go beyond IL(max). Ii

+ VCE1 −

IR = IB1 + IZ Vi

IB1 R

+ IC2

−

Iz D

IL

IL

+

IB2 + VBE2

+ Unregulated input

RSC

− VBE1

Q1

+

IC1

Q2

IC2

RL

VO −

VZ −

Figure 17.23 Transistor Q1 is used for overload protection

Thus, we have seen that the function of a current limiting circuit is to prevent damage to the series pass transistor when suddenly the load resistance decreases. In the absence of a current limiting circuit, there flows an excessive current in the series pass transistor. To prevent this occurrence, the current limit circuit will reduce the base current to the series pass transistor, thereby ensuring the maximum safe current limit, IL(max) is not exceeded. From Figure 17.24, it can be noted that as long as I L ≤ I L(max ), VO remains constant. When I L > I L(max ), VO falls to zero. A short-circuit current, ISC

Voltage Regulators

885

Vo Current limit operates

Regulated Vo

0

IL(max) ISC

IL

RL(min)

RL = ∞

Figure 17.24 V–I characteristic of a constant current limit

flows through the transistor. Practically, the entire input voltage Vi appears as VCE. Therefore, PD = Vi ISC, which can be very large. Hence, the transistor chosen should have this power dissipation capability. When current limit operates, the regulator is no longer in the constant voltage mode, but operates in the constant current mode, because the main concern here is no longer to maintain the output voltage constant but to somehow ensure that the load current is never above the rated maximum. The advantage with constant current limit is that if the load resistance is increased above the point where the current limit operates, the regulator automatically goes into constant voltage mode. For silicon transistor to conduct VBE = Vγ = 0.5V. If IL(max) = 100 mA, then RSC is Vg 0.5 chosen as RSC = = = 5 W. I L ( max ) 100

17.5.2 Fold-Back Current Limiting in a Series Regulator The main limitation of simple current limit is that when there is an overload or short circuit, the dissipation in the series pass transistor becomes large, and hence the transistor is required to have a large power dissipation capability. This disadvantage is overcome in a fold-back current limiting circuit. When short circuit occurs, the maximum current through the series pass transistor is limited to ISC, which is very much smaller than IL(max), thereby ensuring the safety of the regulator. The fold-back current limiting circuit is shown in Figure 17.25, and its V–I characteristic is shown in Figure 17.26. From Figure 17.25, we can draw Figure 17.27, to calculate VBE2. Ii

+ VCE1 − Q1

+

IR = IB1 + IZ Vi Unregulated input −

+ VR1 − IB2

IC2

IB1

IL

IC1

R Q2 IZ D

VZ −

VBE2 −

+

RSC

R1

+

I1 RL I1 R2

Figure 17.25 Fold-back current limiting

VO −

886

Electronic Devices and Circuits Vo Regulated Vo Fold-back

0

IL(max)

ISC = IL(max) /3

IL

Figure 17.26 V – I characteristic of fold-back current limit

RSC R1

IL −

VBE2 + VR2

+

+ RL

VO

R2 −

−

Figure 17.27 Circuit to calculateVBE2

From Figure 17.27, VR2 = ( I L RSC + VO ) where a = Also

R2 = a ( I L RSC + VO ) R1 + R2

(17.49)

R2 R1 + R2 VR2 = VBE2 + VO

(17.50)

From Eqs (17.49) and (17.50), VBE2 + VO = a ( I L RSC + VO ) Or  R2  R1 VBE 2 = VO (a − 1) + a I L RSC = VO  − 1 + a I L RSC = a I L RSC − VO R1 + R2  R1 + R2  ∴VBE2 = aI L RSC − VO

R1 R1 + R2

(17.51)

When RL reduces, VO reduces and IL increases. Hence VBE2 increases, thereby increasing the base current of Q2. This results in an increased collector current in Q2, which is diverted to the load. This in turn decreases IB1 and hence the load current IL. If RL decreases further, due to any reason,

Voltage Regulators

887

Q2 is driven ON stronger, diverting more current to the load and this further reduces the base current of Q1 and hence IL. Thus fold-back current limiting occurs (Figure 17.26). When the output is shorted (VO = 0), the voltage drop across R1 is zero. Hence a = 1. Therefore, VBE2 = ILRSC. RSC is chosen such that as long as I L < I L (max ), VBE2 < 0.5 V, required for Q2 to be ON. Hence, normal regulator action takes place. For Q2 to be ON, the voltage drop across RSC must be larger than the drop across R1by 0.5 V. Then Choosing VR1 = 0.5 V, I L(max ) RSC = VR1 + VBE2 = 0.5 + 0.5 = 1V . If I SC RSC is chosen as 0.5 V, to prevent damage to the transistor, IL(max) = 2ISC. Alternately, If VR1 = 1 V, I L(max ) RSC = 1.0 + 0.5 = 1.5 V . If I SC RSC is chosen as 0.5 V, then IL(max) = 3ISC. Example 17.9 For a series regulator shown in Figure 17.24, design a fold-back current limit circuit. The regulated output is 15 V. IL(max) = 300 mA, and ISC = 100 mA. Solution: Given ISC = 100 mA. Choose ISCRSC= 0.5 V. Therefore, RSC =

ISC RSC 0.5 = =5Ω I SC 100

For IL(max) = 300 mA, IL(max) RSC = 300 × 10 −3 × 5 = 1.5 V Therefore, VR1 = IL(max) RSC − 0.5 = 1.5 – 0.5 = 1 V V 1 Usually I1 » I B2 . Let I1 = 1 mA. As VR1 = 1 V and I1 = 1 mA, R1 = R1 = = 1000 Ω I1 1 VR2, the voltage drop across R2 is VR2 = VR1 + I L(max ) RSC + VO = 1 + 1.5 + 15 = 17.5 V R2 =

VR 2 17.5 = = 17.5 kΩ I1 1

Nearest standard values of resistances are usually chosen. From the V–I characteristic of a fold-back current limit, it can be noted that as RL decreases to the point where current limit occurs, the output voltage falls to a very small value. Even though RL is returned to its original value, regulator action may not take place because of the fold-back characteristic. It becomes necessary to increase RL to a much larger value than the value at which the current limit has occurred.

Overvoltage Protection in a Regulator Although power supplies are usually reliable, occasionally they may fail and can cause damage to the circuitry to which dc voltage is supplied from this source. In a regulator, the unregulated input can be sufficiently large when compared to the regulated output (high drop-out voltage). If the output dc voltage required is 5 V, then the input unregulated dc voltage can be as high as 10–15 V. A dc voltage of 5 V is required to operate transistor–transistor logic (TTL) gate for reliable gate operation; the supply voltage of 5 V may be allowed to vary by not more than ±0.5 V. If the power supply uses a series regulator and if the series pass transistor gets short circuited, then the full input voltage of 10 or 15 V will appear as dc voltage to the TTL gate. This will damage the external TTL circuit that uses this dc source. To avoid this, a crowbar protection circuit using a silicon-controlled rectifier (SCR) is used (Figure 17.28). The protection circuit uses an SCR (also called a thyristor), a Zener diode, with its current limiting resistor, R and R1 that controls the gate current of the SCR.

888

Electronic Devices and Circuits

+ Regulated VO output

+ VZ − + R

−

SCR

IG

DC Voltage connected to circuit

R1

External Circuit like TTL Logic Gate

VR −

Figure 17.28 Crowbar overvoltage protection

VZ is chosen to be slightly above VO. Typically, if VO = 5 V, then VZ can be chosen as 6.2 V. Now due to the failure of the series pass transistor, if VO = 15 V, the Zener diode conducts, a voltage VR develops across R. This supplies gate current IG as trigger to the SCR and drives into the ON state. When an SCR is ON, the voltage between its anode and cathode is ideally zero. This will then provide a short circuit at the output terminals, thereby protecting the external circuit. An SCR can handle high peak currents, of the order of 50 A or more for relatively longer duration. Once the SCR fires (conducts), the voltage across the SCR is typically of the order of a fraction of a volt. Hence, the dissipation in the device is not necessarily large. As long as VO remains unchanged, the SCR is OFF. Normally, current limit is provided in a regulator. Often a fuse is also used. The overvoltage protection circuit is based on brute force: when the power supply voltage increases too much, the thyristor short circuits the output. This means that the overvoltage is quickly removed from equipment and the fuse will burn. The term crowbar is used as a verb to describe the act of short-circuiting the output of a power supply. In Figure 17.29, the overvoltage protection circuit is used in the output of the regulator. Ci and Co are the filter condensers on the input and the out side. Fuse Regulator Mains input

Overvoltage Sense

Transformer Rectifier

Ci

Co

+ VO −

Figure 17.29 Implementation of overload protection in a regulator

Reverse Polarity Protection in a Regulator Voltage regulators are called dc to dc converters. When connecting the unregulated input to dc to dc converter, one should properly take care of the polarity of the supply. Otherwise, the regulator may get damaged. Let us see the consequences of such a polarity reversal. Let the polarity of the unregulated output be accidentally reversed, as shown in Figure 17.30. The Zener diode gets forward biased by a large Vi. The Zener can be damaged. The transistor can be driven hard into the ON state and may be damaged. (i) Reverse polarity protection using a blocking diode: To prevent damage to the regulator, reverse polarity protection is usually provided in some regulators. One such protection circuit in Figure 17.31 simply uses a diode to block the reverse polarity. When the applied polarity is proper, the diode conducts and the unregulated voltage is applied to the regulator. When the polarity gets reversed, the diode is OFF and no voltage is applied to the regulator.

Voltage Regulators

VCE

Ii

IL

Q

− IB Vi Unregulated input

889

+

− VBE

R

RL

VO

− IZ D

+

VZ +

Figure 17.30 Series regulator with polarity reversal at the input Blocking diode

Blocking diode

+

−

Unregulated output

ON

Regulator

OFF

Unregulated output

−

Regulator

+

(a) Normal polarity

(b) Reverse polarity

Figure 17.31 Reverse polarity protection with blocking diode

(ii) Reverse polarity protection using a shunt diode and fuse: An alternate method to protect the regulator from reverse polarity is by using a shunt diode and fuse (Figure 17.32). When the polarity is normal, the diode is OFF and the unregulated voltage is applied to the regulator input. When the polarity gets reversed, the diode is ON draws a large current that can blow off the fuse. Fuse

Fuse

+ Unregulated output

− OFF

− (a) Normal polarity

Regulator

Unregulated output

ON

Regulator

+ (b) Reverse polarity

Figure 17.32 Reverse polarity protection with shunt diode and fuse

(iii) Reverse polarity protection using a power MOSFET: A P-channel power MOSFET with a body diode can be used as a switch to provide reverse polarity protection (Figure 17.33). As long as the polarity is proper, the MOSFET switch is ON (diode is forward biased) and its ON resistance RDS(ON) is very small. The unregulated voltage is applied at the regulator input. If the polarity is reversed, the MOSFET switch is OFF (diode is reverse biased) and is an open circuit. No reverse voltage is applied to the regulator. Reverse polarity protection can also be provided at the output of the regulator to ensure that the external circuit is not damaged. One method is to use an electromechanical relay as shown in Figure 17.34. Regulated dc voltage is applied to the external circuit. If the polarity of the regulated output changes, D1 is OFF and D2 is ON. When power is switched OFF to the relay coil with di inductance L, a back emf −L is produced. D2 is used to clamp this voltage to 0.7 V. When no dt current flows through the relay coil, the relay contact opens, thereby protecting the external circuit

890

Electronic Devices and Circuits

ON

OFF

+

−

Unregulated output

Unregulated output

Regulator

Regulator

−

+

(a) Normal polarity

(b) Reverse polarity

Figure 17.33 Reverse polarity protection with P-channel power MOSFET and body diode

from reverse polarity. However, the relay draws some current. All the earlier protection circuits can also be used at the output of the regulator to protect the external circuit from reverse polarity. With normal polarity D1 is ON and D2 is OFF. Current flows through the relay coil and the relay contact closes.

Thermal Shutdown When the junction temperature in the series pass power transistor QS reaches around 160°C, it is possible that the regulator may be damaged. Junction temperature may rise either due to self-heating or due to rise in ambient temperature. To prevent damage to the regulator at elevated junction temperatures, the thermal shutdown protection circuit is incorporated in a regulator (Figure 17.35). The temperature sensor (Q1) is placed near the series pass power transistor, in which the maximum dissipation occurs, to track temperature changes. Relay contact + + Regulated output

External circuit

Relay D1

D2

−

−

Figure 17.34 Reverse polarity protection to the external circuit + R To error amplifier Vi IZ

+

R1

VZ D −

R2 −

IBS

QS Series pass power transistor

IC1

IL

Q1 + VBE1 −

+

Heat flow RL

Vo −

Figure 17.35 Implementation of thermal shutdown

R1and R2 are chosen such that as long as the junction temperature is below 160°C, Q1 is OFF. D is an avalanche breakdown diode with breakdown voltage VZ and has a positive temperature coefficient. With increase in temperature, VZ increases and VBE1of Q1 increases. When the temperature reaches

Voltage Regulators

891

160°C, the drop across R2 will be sufficient enough to drive Q1 into saturation. A large current IC1 is diverted from the base of QS, and hence IBS is reduced, thereby reducing the junction temperature of QS. QS may even be driven into the OFF state.

17.6

A SERIES REGULATOR USING AN ERROR AMPLIFIER (FEEDBACK REGULATOR)

The circuit in Figure 17.36 is a series regulator with Q2 used as an error amplifier. The main advantages of using an error amplifier are (i) regulation improves and (ii) ripple in the output reduces. Ii + IR = IB1 + IC2 R4 Vi Unregulated input

IC1

+ VCE1 − Q1

− VBE1 + + VR3 − VB1 = VC2

IB1

IC2 + Q2 VCE2 − IE2 + VZ −

−

IB2 + V − BE2 IZ

+ VR1 R3

−

IL

+

R1 RL IR1

Vo −

IR3 + R2 V2 = βVo IR2 −

Figure 17.36 A series regulator with error amplifier

If, for any reason, Vi increases, VO increases. R1 and R2 comprise the sampling network. The R2 voltage V2 ( = VO = bVO ) increases. The current in the Zener diode is limited by R3 and VZ is R1 + R2 the Zener voltage. VBE2 = V2 − VZ, since VZ almost remains constant, VBE2 increases. Consequently, IB2 increases and hence IC2 increases. Increase in IC2 increases the drop across R4. Therefore, the voltage at the base of Q1 reduces and IB1 reduces. As a result IC1 = IL reduces. VO is brought back to the required value. Similarly, if Vi decreases, VO is once again brought back to the required value.

Calculation of VO From Figure 17.36, (17.52)

VO = VR1 + VBE2 + VZ VR1 = VO

R1 R1 + R2

(17.53)

Substituting Eqn. (17.53) in Eqn. (17.52), VO = VO

R1 + VBE2 + VZ R1 + R2

 R1  ∴VO 1 − = VBE2 + VZ  R1 + R2 

Or

 R2  VO  = VBE2 + VZ  R1 + R2 

892

Electronic Devices and Circuits

 R   R + R2  VO = (VBE2 + VZ )  1 = (VBE2 + VZ ) 1 + 1   R2   R2   R  VO ≈ VZ 1 + 1   R2 

(17.54)

(17.55)

VO can be more than the Zener voltage. VO can be adjusted by adjusting R1 and R2. The main advantages of this regulator are as follows: ∆VO (i) As Vi changes by ∆Vi , Vo changes by , where A is the voltage gain of the error amplifier. A This improves regulation. (ii) If Vg is the ripple in the output of a series regulator without error amplifier, then the ripple Vg in the output of this regulator is . Thus the ripple is appreciably reduced. A Adjusting the Output Voltage In the regulator circuit shown in Figure 17.36, VO is constant for given values of R1 and R2. If VZ = 7.5 V, VBE2 = 0.7 V, R1 = 2 kΩ, and R2 = 10 kΩ, 2  VO = ( 0.7 + 7.5) 1 +  = 9.84 V  10  If VO is required to be 10 V, it is not possible with this arrangement, since R1 and R2 are chosen as standard values of resistances. Further, let R1 and R2 be resistors with 10 percent tolerance. Then R1 varies from R1(min) = 1.8 kΩ to R1(max) = 2.2 kΩ. Similarly, R2 varies from R2(min) = 9 kΩ to  1.8  R2(max) = 11 kΩ. Then, VO can vary between VO1 and VO2, where V01 = ( 0.7 + 7.5) 1 +  = 9.54 V  11   2.2  = 10 . 20 V. and V0 2 = ( 0.7 + 7.5) 1 +   9  Thus, the output can vary due to tolerances of the resistances used. If the output needs to be adjusted to a desired voltage, then a potentiometer R5 is included as shown in Figure 17.37. IL

R1 A +

Q2 + VBE2 − + VZ −

R5

RL

B

VO −

R2

Figure 17.37 Adjusting the output voltage

From Eqn. (17.54), when only R1 and R2 are used,  R + R2  VO = (VBE2 + VZ )  1  R2 

Voltage Regulators

893

If the center-tap of R5 is adjusted to be at B, then VO is VO(max) and is given as follows:  R + R5 + R2  VO(max ) = (VBE2 + VZ )  1  R2 

(17.56)

And if the center tap of R5 is adjusted to be at point A, then VO is VO(min) and is given as follows:  R + R5 + R2  VO(min) = (VBE2 + VZ )  1  R2 + R5 

(17.57)

A complete series regulator with adjustable output is shown in Figure 17.38. Ii + IR = IB1 + IC2 R4 IB1

Vi Unregulated input

IC1

+ VCE1 − Q1 +

IC2

−

IL IR3

VBE1 R3

R1 IR1

IB2

R5

Q2

+ VZ −

−

+ RL

B

+

V − BE2

A

Vo −

R2

Figure 17.38 A series regulator with adjustable output

Example 17.10 For the circuit shown in Figure 17.38, find VO(max) and VO(min), given that R1 = 2 kΩ, R5 = 2 kΩ, R2 = 10 kΩ, VBE2 = 0.7 V, and VZ = 7.5 V. Solution: From Eqn. (17.56), æ 2 + 2 + 10 ö VO( max ) = ( 0.7 + 7.5 ) ç ÷ = 11.48 V 10 è ø From Eqn. (17.57), æ 2 + 2 + 10 ö \VO( min) = ( 0.7 + 7.5 ) ç ÷ = 9.57 V è 10 + 2 ø VO can be adjusted between 9.57 V and 11.48 V.

High Output Current Series Regulator In the regulator circuit shown in Figure 17.38, to effectively control IB1, IC2 must be much larger than IB1. This may not pose a serious problem in low current applications such as in power supplies where IL typically is 100mA. If Q1 has hFE = 100, then IB1 = 1 mA. Q2 can easily supply much larger collector current IC2. However, in high current applications, IB1 may be large. As a result, unless IC2 is much larger than IB1, IC1 may not be controlled effectively. With hFE = 100, let IB1 = 15 mA. If IC2 is only 10 mA, effective control of IC1 is not possible. In such high current applications, the circuit in Figure 17.38 is modified as in Figure 17.39. An additional transistor Q3 is included in such a manner that Q1 and Q3 is a Darlington pair.

894

Electronic Devices and Circuits

For the Darlington circuit, we know that hFE = hFE3hFE1. If hFE3 = 50, hFE1 = 20, and IL = 1000 mA, IL 1000 then I B3 = = = 1 mA. Q2 with IC2 = 10 mA, can now effectively control IC1 = IL. hFE3 hFE1 50 × 20 Darlington pair IL

IC1 Q1

+ Q3 Vi

R4 IB3 + IC2

IB1 R3

IB3

+

IC2

+

R5

IB2

Q2

−

R1

−

RL

Vo −

+ VBE2

VZ

+ βVo

−

−

R2

Figure 17.39 High-output current series regulator

Design of a Feedback Regulator For the design of a regulator circuit shown in Figure 17.38, VO, Vi and IL, generally need to be specified. The Zener voltage, VZ is usually chosen as 0.5 VO or sometimes as 0.75VO, because in this regulator VO is greater than VZ. Then the current in R3( = IZ ) is calculated. Thus, PZ can be calculated, to completely specify the Zener. Then IC and VCE are calculated to specify Q1 and Q2. Finally, R1, R2, R3, and R4 are chosen appropriately. The procedure is best understood by considering an example. Example 17.11 Design the complete regulator circuit shown in Figure 17.36. It is required that VO = 20 V, Vi = 25 ± 3 V, IL(max) = 100 mA, hFE of Q1 and Q2 is 60, and IC2 = 12 mA. Solution: Choosing RL:

20 = 200 Ω. 100 2 Wattage of RL = I L2 ( max ) RL = ( 0.1) ´ 200 = 2 W . As IL(max) = 100 mA and VO = 20 V,RL(min) =

Selecting the Zener diode: V 20 Choose VZ = O = = 10 V 2 2 Having chosen VZ, we should now find out IZ so that we can specify PZ. I 12 From Figure 17.36, I R1 » I B2 . From the given data, I B2 = C2 = = 0.2 mA . hFE 60 Choose IR1 = IR2 = IR3 = 10 mA. I Z = I E2 + I R3 = I C2 + I R3 = 12 + 10 = 22 mA PZ = I ZVZ = 0.022 × 10 = 0.22 W. Choose a suitable Zener diode from the data sheet.

Voltage Regulators

Choosing Q1: I E1 = I R3 + I R1 + I L = 10 + 10 + 100 = 120 mA Vi varies as ( 25 ± 3) V. Therefore, Vi( max ) = 28 V and Vi(min) = 22 V ∴VCE1(max ) = Vi(max ) − VO = 28 − 20 = 8 V The possible dissipation in Q1 is PD1. PD1 = I E1VCE1( max ) = 0.120 ´ 8 = 0.96 W Q1 is chosen from the data sheet as a transistor with PD1 of at least 1 W. Choosing Q2: Given IC2 = 12 mA. From Figure 17.36, VCE2(max ) + VZ = VBE1 + VO \VCE2( max ) = VBE1 + VO - VZ = 0.7 + 20 - 10 = 10.7 V PD2 = IC2VCE2(max) = 12 ×10.7 = 128 mW Q2 is chosen from the data sheet as a transistor with PD2of at least 150 mW. Choosing R1, R2 and R3: Choose IR1 = IR2 = IR3 = 10 mA. VR1 = VO − (VZ + VBE2 ) = 20 − (10 + 0.7 ) = 9.3 V R1 =

VR1 9.3 = = 920 Ω ≈ 1 kΩ I R1 10

R2 =

V2 VZ + VBE2 10 + 0.7 = = = 1070 Ω ≈ 1 kΩ 10 I R2 I R2

R3 =

VO − VZ 20 − 10 = = 1 kΩ I R3 10

Choosing R4: VB1 = VC2 = VBE1 + VO = 0.7 + 20 = 20.7 V We have I C1 = I E1 = I R3 + I R1 + I L = 10 + 10 + 100 = 120 mA ∴ I B1 =

I C1 120 = = 2 mA 60 hFE

IR, the current in R4 is ( IB1 + IC2) IB1 + IC2 = 2 + 12 = 14 mA

895

896

Electronic Devices and Circuits

R4( max ) =

Vi( max ) - VC2

R4( min) =

IR Vi( min) - VC2 IR

=

28 - 20.7 = 521 W 14

=

22 - 20.7 = 93 W 14

R4 is chosen as the average value. R4 =

17.7

R4(max ) + R4(min) 2

=

521 + 93 = 307 Ω. ≈ 300 Ω 2

IC REGULATORS

Till now, regulators using discrete components have been considered. However, IC regulators with protection circuits are also available. Basically, these IC regulators are of two classes: (i) linear and (ii) switching. In a linear regulator, the regulating device is made to act like a variable resistor, whose resistance value varies continuously to maintain the output voltage constant. As the input voltage to the regulator is much larger than the output voltage, power is dissipated in the regulator, resulting in heating up of the regulator. Efficiency of the linear regulator is poor. A switching regulator, however, uses an active device that switches ON and OFF to maintain an average value of output. The amount of power dissipation in this type of regulator is negligible. This results in higher efficiency.

17.7.1 Linear IC Regulators The circuits that are considered with discrete components can be fabricated in an IC form to provide the following advantages: (i) low cost, (ii) simple wiring and operation, (iii) compact in construction, (iv) low output ripple, and (v) features such as overload and short-circuit protection and thermal shutdown can be integrated into the IC, which make the IC versatile. However, linear regulators suffer from the following disadvantages: (i) low efficiency and (ii) appreciable power dissipation in the linear regulator. Linear regulators are generally used when the difference between the input source voltage and the output supply voltage is minimal, and the efficiency of the regulator is not of great concern. IC regulators are either fixed voltage regulators or adjustable voltage regulators. Further, these can be classified as three-terminal or multiterminal regulators.

(a) Three-terminal Fixed Voltage Regulators A three-terminal regulator has only three pins brought out externally, which makes it very convenient to wire the circuit and derive a desired dc voltage. Many regulators manufactured by different manufacturers are available. However, 78XX, LM 340, LM 217, and LM 317 series positive regulators and 79XX, LM 237, LM 320, and LM 337 series fixed negative voltage regulators are only considered here. (i) 78XX series fixed positive voltage regulators: 78 or 7800 series regulators are fixed positive voltage regulators. XX stands for different standard voltages for which these regulators are available. Eight voltage options are available starting from 5 V to 24 V (see Table 17.1). For the regulators to work properly, the unregulated input voltage should at least be larger than the dc output voltage by 2–3 V. The minimum voltage difference that must exist between the input and the output of the regulator is called the dropout voltage.

Voltage Regulators

897

Table 17.1 Standard voltages of 78 series regulators S. No.

IC

Output voltage (V)

Minimum input voltage (V) (Typical values)

1

7805

+5

7.3

2

7806

+6

8.3

3

7808

+8

10.5

4

7810

+10

12.5

5

7812

+12

14.6

6

7815

+15

17.7

7

7818

+18

21.0

8

7824

+24

27.1

The specific regulator is chosen based on the desired dc voltage. For example, to get 15 V, 7815 regulator is chosen. The regulator circuit is wired as shown in Figure 17.40.

230 V 50 c / s

Rectifier-

Vi

Filter −

IC 7815

2

3 C1

0.01µF

0.01µF

C2

Regulated output

+ Transformer-

Unregulated input

1

+ L VO = 15 V O A D −

0

Figure 17.40 IC7815 used to derive + 15 V regulated dc

The unregulated dc output voltage Vi of transformer–rectifier–filter circuit is the input to the regulator, and the output of the regulator is the regulated dc voltage VO = 15 V. C1 and C2 are included to bypass high-frequency transients. Maximum load current of ≈1 A can be drawn from 78XXC series regulators. To be able to deliver a much larger load current than a 78XX regulator can normally deliver, a current boost transistor is connected externally as shown in Figure 17.41. From Figure 17.41, I i = I B + I1 orI B = I i − I1 IB = I i −

VEB R1

Ii = IQ + IO ≈ IO since I Q is small.

(17.58) (17.59)

898

Electronic Devices and Circuits

VEB −

IB

R1 +

I1

1 Ii

+

IC

2

78XX

IO 3

+ L VO O A D

IQ

Vi

IL

−

−

Figure 17.41 Current boost in a three-terminal regulator

Substituting Eqn. (17.59) in Eqn. (17.58), ∴ IB = IO −

VEB R1

(17.60)

Using Eqn. (17.60),  V  I C = hFE I B = hFE  I O − EB  R1  

(17.61)

 V  I L = I O + I C = I O + hFE  I O − EB  R1   or I L = I O (1 + hFE ) − hFE

VEB R1

(17.62)

If for Q1, hFE = 20 and VEB = 0.7 V , I O for the regulator is 1 A and R1 = 7Ω I L = I O (1 + hFE ) − hFE

VEB 0.7 = 1 (1 + 20 ) − 20 = 19 A 7 R1

Without current boost, the load current 78XX can deliver is 1 A; and with current boost, the load current is as high as 19 A. Three-terminal regulator as an adjustable regulator: 78 series fixed voltage three-terminal regulators can be used as adjustable voltage regulators if pin 3 is not connected to ground but is connected to the potential divider network as shown in Figure 17.42. From Figure 17.42, When I Q = 0,VREF = VO

R1 R1 + R2

Voltage Regulators

1

2

78XX

+

+ 3

VREF −

VI IQ

899

R1

+ VO

R2 IQ

−

−

Figure 17.42 78XX as an adjustable voltage regulator

Or  R  VO = VREF 1 + 2   R1 

(17.63)

 R  VO = VREF 1 + 2  + I Q R2  R1 

(17.64)

With finite IQ,

Example 17.12 In the circuit shown in Figure 17.42, 7815 regulator is used. If R1 = 50 Ω, R2 = 150 Ω and I Q = 10 mA , determine VO(min) andVO(max ). Solution: VO = VO(min) when R2 = 0 Then from Eqn. (17.64), VO(min) = 15 V VO = VO(max ) when R2 = 150 Ω  R  Then from Eqn. (17.64), VO(max ) = VREF  1 + 2  + I Q R2 R1    150  −3 = 15 1 +  + 10 × 10 × 150 = 61.5 V  50  LM 340, LM 217, and LM 317 are other types of fixed positive voltage regulators. (ii) 79XX series fixed negative voltage regulators: 79 or 7900 series regulators are fixed negative voltage regulators. These regulators are available in 10 fixed ranges. In addition to the 8 ranges in 78 series, 79 series are available in −2 V and −5.2 V ranges also. To get −15 V, 7915 regulator is chosen, and the circuit is wired as shown in Figure 17.43.

900

Electronic Devices and Circuits

1

2

IC 7915

−

−

Unregulated input C

3 0.01µF

1

0.01µF

Regulated C2 output

L O V = −15 V A O D

Vi +

+ 0

Figure 17.43 IC7915 used to derive −15 V regulated dc

LM 320, LM237, and LM 337 are other types of fixed negative voltage regulators In certain applications, such as biasing an op-amp, two identical positive and negative voltages are needed. Therefore, to derive these twin voltages 78 and 79 series regulators are wired as shown in Figure 17.44. 1

IC 7815

2

15 V

+ Unregulated dc

Vi

C1

0 Vi

C1

3

C2 0 C2

3

− 1

IC 7915

2

−15 V

Figure 17.44 Dual power supply

(b) IC723, the General-Purpose Regulator In the fixed voltage regulators seen till now, an IC is used to derive positive or negative voltage. However, the same IC cannot be used to derive either a positive or negative voltage. The general-purpose IC723 is versatile low-current device that can be used to obtain either a positive or negative voltage. The major limitation of this IC is that short circuit or overload protection need to be provided externally. For high-current applications, however, an external current boost transistor is to be connected. The functional block diagram of IC723 is shown in Figure 17.45. It consists of an error amplifier, a series pass transistor Q1 that can deliver a load current of about 150 mA, a current-limiting transistor Q2, and a reference voltage source of 7 V. The IC needs a maximum input voltage of 40 V. By suitable modifications, the IC can be used to get variable output voltage of 2 to 37 V. IC723 as a variable positive voltage regulator with current limit is shown in Figure 17.46.This circuit is called a high voltage (VO > 7 V ) and low current (150 mA) regulator. From Figure 17.46, if the potentiometer RC is adjusted to have R1 = RA + 0.5 = 6.8 + 0.5 = 7.3 kW and R2 = RB + 0.5 = 2.7 + 0.5 = 3.2 kΩ , then VO = VREF ´

R1 + R2 7.3 + 3.2 = 7´ = 10.06 V R1 7.3

NC 14

Frequency compensation (FC)

Voltage Regulators

VCC

VC

13

12

11

Output 10 Q1

VZ 9

901

NC 8

Series pass transistor

+ Error − amplifier

2

3

Current Current limit sense (CL) (CS)

4

5

6

7

Non-inverting input

1 NC

Inverting input

Q2

VREF

−VCC

Figure 17.45 Functional block diagram of IC723 RSC +

14

13

12

11

10

9

8

Q1

R1

C = 100pF

R2

Q2 1

2

3

+

6.8 RC VO 1

+ −

Vi

RA

4

5

−

6

7

RB 2.7

−

Figure 17.46 IC723 as a variable positive voltage regulator with current limit

The regulator works properly only when the unregulated dc input is greater than the regulated output voltage by at least 3to 5 V and is also greater than VREF.

High-voltage, Low-current Regulator This regulator can be drawn simply as in Figure 17.47. For the circuit in Figure 17.47, VO = VREF × RSC =

R1 + R2 R2

0.7 I L(max )

(17.65) (17.66)

902

Electronic Devices and Circuits

Vi 12

11

VCC

VC

6 V REF 723

R3 5

10

Output CL

+ 3

Non-Inv

CS 4

Inv FC

−VCC 7

RSC

2

R1

VO

13 R2

100pF

−

Figure 17.47 High-voltage, low-current regulator

(17.67)

R3 = R1 || R 2

Low-voltage, Low-current Regulator With no external pass transistor, if Vo is adjusted to lie between 2 V and 7 V, then the circuit is called a low- voltage, low-current regulator. For the lowvoltage regulator, VREF should be reduced. This is done by using the potential divider network comprising R1 and R2 (Figure 17.48). Vi 12

11

VCC

VC Output

6 V REF 723

R1

CL

10

Current boost transistor

2

RSC +

Vo

3 CS VNI

5

Non-Inv −VCC

R2

7

Inv FC

4 R3

13 100pF

Figure 17.48 Low-voltage, low-current regulator

The series pass transistor works as an emitter follower. The output of the emitter follower is the same as the input. VNI = VREF ×

R2 = VO R1 + R2

(17.68)

Voltage Regulators

903

where VNI is the input voltage at the noninverting terminal. Equation (17.66) holds good for this circuit also.

Low-voltage, High-current Regulator For IC723 the load current is limited to only 150 mA. If the regulator is to deliver larger load current, an external pass transistor needs to be connected as shown in Figure 17.49. Vi 12

11

VCC

VC

6 V REF 723

R3

10

Output

Q1

Current boost transistor RSC

2

CL

+

VO

3 CS 5

Non-Inv −VCC

R2

7

4

Inv FC

R3

13 100pF

Figure 17.49 Low-voltage, high-current regulator

High-voltage, High-current Regulator When the output voltage is to be greater than7 V and if the regulator is to deliver a load current larger than 150 mA, then in the circuit shown in Figure 17.47 a current boost transistor Q1 is included as shown in Figure 17.50. Vi 12

11

VCC

VC Output

6 V REF 723

R3 5

Non-Inv

−VCC 7

CL

10 2

Q1

Current boost transistor RSC +

3 CS Inv FC

4

R1

VO

13 100pF

R2 −

Figure 17.50 High-voltage, high-current regulator

Some Important Specifications of IC Regulators Some of the important specifications of linear IC regulators are as follows:

904

Electronic Devices and Circuits

1. Output voltage: When an IC regulator, say IC7815, is considered the output voltage of the regulator is 15 V. However, this output voltage can vary by only ±0.5 V. 2. Output regulation: The data sheets specify the typical permissible variation of the output voltage at the specified load current. For IC7815 regulator, this may be specified as 100 mV at an output current of 0.25 A. This means that for the load current of 0.25A, VO can only vary by ±100 mV. 3. Short-circuit output current: In the event of a short circuit, this is the maximum limit to the load current. This current can be typically 350 mA, for a given regulator. 4. Peak output current: The maximum rated current for an IC may be 1 A. However, a current of 1.5 A may be drawn for a short duration. This current is called the peak output current. 5. Dropout voltage: The minimum voltage difference that must exist between the input and the output terminals of the IC regulator to operate properly is called the dropout voltage. This voltage may range from 2 to 5 V.

17.7.2 Switching Regulators It has been mentioned earlier that the main limitation of a linear regulator is the excessive amount of power dissipation in it, mainly because the series pass transistor operates in the active region. The efficiency of the linear regulator as such is small, because of the power loss in the regulator. A switching regulator can reduce the dissipation in the regulator and improve the efficiency. In a switching regulator, the unregulated dc input is switched ON and OFF at a rate decided by an external source (Figure 17.51). Consequently, the output is a pulse train whose width varies as per the switching signal. This principle of operation is called pulse width modulation (PWM). The regulated dc voltage is thus a function of the duty cycle, D (Figure 17.52). SW + L O V A O D

Vi

−

Figure 17.51 Switch controlling the output dc Sampled dc

Sampled dc

Vi

Vi

TON

TOFF

VO

TON

Output dc voltage

TOFF Output dc voltage

VO 0

0 T

T

Figure 17.52 Pulse width modulation

Voltage Regulators

905

The output dc voltage is the average over one cycle and is given as follows: VO =

TON × Vi = DVi T

(17.69)

where the duty cycle is given as follows: D=

TON T

(17.70)

By controlling the D, it can be inferred that the output dc voltage can be controlled. Switching regulators are basically of three types based on the way the transistor switch and the diode are placed in the circuit as (i) buck-type or step-down regulator, (ii) boost-type or step-up regulator, and (iii) buck–boost-type or step-down–step-up-type regulator. (i) Buck-type regulator: A buck converter shown in Figure 17.53 is said to be operating in the continuous mode if the current through the inductor (IL) never falls to zero during the commutation cycle. C and L operate as a filter. The principle of operation is explained with the help of the waveforms in Figure 17.54. Transistor switch VO L Vi

D

Series pass transistor Q

+ Vi

C

V 0

−

Filter VO L C

D

Figure 17.53 Buck-type regulator

State of the switch

TOFF

TON 0 Vi

Voltage

VO VO 0 −VO

Inductor current

IL(max) IL IL(min) 0

DT

T

Figure 17.54 Waveforms of the buck-type regulator

When the switch is closed, the diode is reverse biased and hence is an open circuit. The voltage across the inductor is VL = Vi − Vo. The inductor current IL rises linearly. When the switch is

906

Electronic Devices and Circuits

open, the diode is forward biased, and hence is a short circuit. The voltage across the inductor is VL = −VO. The inductor current IL decreases linearly. LI 2 The energy stored in the inductor L = L and increases during the ON period and decrease 2 during the OFF period. We know that the voltage VL across the inductor is L

dI L = VL dt

During the ON period, VL = Vi − VO and during the OFF period VL = −VO. Hence, the increase in the inductor current during the ON-state is given as follows; TON

∆I L(ON ) =

∫ 0

(Vi −VO ) T VL dt = ON L L

But TON = DT ∴ ∆I L(ON ) =

(Vi −VO ) DT L

(17.71)

Similarly, the decrease in current during the OFF state is given as follows: T

∆I L(OFF) =

∫ TON

( −VO ) T VL dt = OFF L L

But TOFF = (1 − D )T ∴ ∆I L(OFF) =

( −VO ) (1 − D )T L

(17.72)

In steady state, the energy stored at the beginning of the cycle is the same at the end of the cycle, and hence the net energy is zero. Therefore from Eqs.17.71 and 17.72,

(Vi −VO ) DT − VO (1 − D )1T = 0 L

L

= −0 (Vi − VO ) D = VO (1 − D )

VO = DVi

(17.73)

If D = 0.5, then VO = 0.5Vi. Since VO < Vi , this regulator is called the buck-type regulator. D=

VO Vi

(17.74)

From Eqn. (17.73), it can be noted that D controls VO. The control circuit using the buck-type regulator is shown in Figure 17.55. The ouput of the integrator is compared with the output of the error amplifier in the PWM. As long as the output of the regulator is the desired value, the pulse width of the PWM is T (Figure 17.56). If, for any reason, the ouput of the regulator increases, then the pulse width of the PWM is T1, which is smaller than T (Figure 17.57). Hence, D is reduced and VO is brought back to the desired value. If, alternately, VO decreases from the desired value, then the pulse width of

Voltage Regulators

+

Series pass transistor Q

VO

L

Vi

D

R1

C

R2 Error amplifier + 0 − VREF − + C

Pulse width modulator

R − 0

+ Triangular wave

Square wave generator

Integrator

Figure 17.55 Control circuit for the buck-type regulator

Output of the integrator

Output of the error amlifier when VO is the desired value

0

t

Output of the Pulse width modulator

T t 0

Figure 17.56 Pulse width when VO is the desired value

Output of the integrator

Output of the error amlifier when VO is greater than the desired value

0 Output of the Pulse width modulator

t T1 t 0

Figure 17.57 Pulse width when VO is larger than the desired value

907

908

Electronic Devices and Circuits

the PWM is T2 which is larger than T (Figure 17.58). Hence, D increases. VO is once agin brought back to the desired value.

Output of the integrator

Output of the error amlifier when VO is smaller than the desired value

0 t

Output of the Pulse width modulator

T2 t 0

Figure 17.58 Pulse width when VO is smaller than the desired value

(ii) Boost-type regualator: The circuit in Figure 17.59 is that of a boost-type or step-up-type regulator. L

L

Vi

VO +

D Transistor switch

Vi

C

D

V o

Q

VO + C

Figure 17.59 Boost-type regulator

When the switch is open for a long time, D conducts and the capacitor C is charged to the input volatge Vi. When the switch closes, D is OFF and Vi appears across the inductor and the inductor current rises linearly. The capacitor voltage remains unchanged. When the switch opens again, the inductor current continues to flow into the diode to charge the output. As the output voltage rises, the slope of the current, di/dt, through the inductor reverses (Figure 17.60). The output voltage rises until equilibrium is reached. Switch open

i

Switch closed

Inductor current

−VL = L × di / dt

t=0

t

Figure 17.60 Variation of the inductor current

At equilibrium, ViTON = VLTOFF

(17.75)

TON TOFF

(17.76)

Or VL = Vi

Voltage Regulators

909

But (17.77)

VO = Vi + VL Substituting Eqn. (17.76) in Eqn. (17.77), ∴VO = Vi + Vi

D=

TON TONT+ TOFFT

 TON T  = Vi 1 + ON  TOFF  TOFF 

1− D = 1−

(17.78)

TON T + TOFF − TON TOFF = = ON TON + TOFF TON + TOFF TON + TOFF

T 1 = 1 + ON 1− D TOFF

(17.79)

Substituting Eqn. (17.79) in Eqn. (17.78),  T  Vi ∴Vo = Vi 1 + ON  =  TOFF  (1 − D )

(17.80)

If D = 0.5, then VO = 2Vi. Since VO > Vi , this regulator is called the boost-type regulator. (iii) Buck–boost regulator: The buck–boost regulator is shown in Figure 17.61. D

D VO +

Vi Transistor switch

VO +

Vi

C

V o

L

Q

C

L

Figure 17.61 Buck–boost regulator

Buck–boost converter produces a negative output supply voltage from a positive input source voltage. When the transistor switch is ON, D is reverse biased. The inductor current increases due to the positive voltage VL across it. When the switch is OFF, the inductor provides energy to the output load through the ground. The inductor current decreases, thereby reversing the polarity of the inductor voltage. One inductor node is tied to ground, and the other node is at a lower voltage level compared to ground. Therefore, there results a negative output voltage across the output load. For the buck–boost or inverter-type regulator, VO = Vi

D 1 − ( D)

(17.81)

Switched Mode Power Supply A switched mode power supply (SMPS) is an electronic power supply that uses a switching regulator to convert electrical power efficiently. SMPS transfers power

910

Electronic Devices and Circuits

from a source, such as mains power, to a load, such as a personal computer. The general block diagram of an SMPS is shown in Figure 17.62.

Chopper Mains input

dc output

Transformer Rectifier Filter

Output transformer

Rectifier and filter

Fixed frequency variable duty cycle Chopper contoller

Figure 17.62 General block diagram of SMPS

The mains supply is converted into unregulated dc using transformer–rectifier and filter arrangement. The unregulated dc is converted into a high-frequency square wave by using a chopper, the ON and OFF periods being controlled by a switching signal whose frequency typically ranges from 20 to 200 kHz. These high-frequency signals are applied to the high-frequency power transformer, which is usually a small-sized ferrite cored transformer. The output of the power transformer is rectified and filtered to give a constant dc. If the output dc changes for any reason, the chopper controller adjusts the duty cycle of the base feed so as to bring the output back to the desired value. For low-speed applications, ordinary silicon diodes are commonly used as rectifiers. For lower voltages and higher switching speeds, Schottky diodes are used. In the SMPS circuit in Figure 17.62, a high-frequency isolating transformer is used, which can be either a step-up or step-down transformer. Simpler, nonisolated power supplies contain an inductor instead of a transformer. This type includes buck, boost, and buck–boost converters, which belong to the simplest class of single-input, single-output converters that use one inductor and one active switch. These SMPS circuits are already discussed in the earlier sections.

17.8 VOLTAGE MULTIPLIERS When a half-wave rectifier is used to derive a certain dc output voltage, a transformer with a desired turns ratio is used (Figure 17.63). D

N1 230 V, 1φ 50c/s Mains

Vs = Vmsinωt Idc = IL N2

+R L Load V − L

Figure 17.63 Half-wave rectifier to get dc voltage

Vm , where Vm is the maximum voltage swing on the secondary side and RF is the p ( RF + RL ) forward resistance of the diode. Then, VO = IdcRL.

I dc =

Voltage Regulators

911

If Idc = 100 mA and RL = 100 Ω, then VO = 100 × 0.1 = 10 V. If it is required to get VO = 20 V, Vm should be doubled; and if the requirement is that VO should be 30 V, then Vm should be tripled, and so on. The size of the transformer increases. However, if it is required to derive the dc voltages that are integer multiples of Vm, that is, 2 Vm, 3Vm, 4 Vm, etc, then we use voltage multipliers.

17.8.1 Half-Wave Voltage Doubler A half-wave voltage doubler is shown in Figure 17.64. Let initially the voltages on the capacitors be zero. During the negative half cycle of the input signal, D1 is ON and D2 is OFF, resulting in the circuit in Figure 17.65. Capacitor C1 charges to Vm through the small forward resistance of D1. During the positive going half cycle, D2 is ON and D1 is OFF (Figure 17.66). The total voltage across C2 is (Vm + Vm) and C2 charges to this value through the small forward resistance of D2. VO is 2 Vm, with the polarity as shown in Figure 17.66. C1

D2 +

− N1 230 V, 1φ 50c/s Mains

N2 Vs = Vmsinωt

D1

Vo

C2

0 −

Figure 17.64 Half-wave doubler C1 − − N1 230 V, 1φ 50c/s Mains

D2 + +

Vm

N2 Vm

ON D1

Vo

C2

0 −

Figure 17.65 Circuit of Figure 17.64 when D1 is ON and D2 is OFF C1 − + N1 230 V, 1φ 50c/s Mains

N2 Vm 0

D2 + +

Vm + ON D1

2Vm Vo

C2 −

−

Figure 17.66 Circuit of Figure 17.65 when D1 is OFF and D2 is ON

When the input to the voltage doubler is a sinusoidal signal, the output is that of a half-wave rectifier. When load RL is connected, C2 discharges through RL when D2 is OFF (during the negative going half cycle of the input) (Figure 17.67). T If the change in the output voltage is ∆Vo during the period for which D2 is OFF, then 2 IL I LT ∆VO = t or C2 = (17.82) 2 ∆VO C2

912

Electronic Devices and Circuits OFF D2

+ +

IL

C2

Discharge of C2 Ripple

RL VO

− − 0

2π

π

3π

Figure 17.67 C2 discharges through RL when D2 is OFF

During the positive-going half cycle of the input, D1 is OFF and D2 is ON and the charge lost by C2 must be replenished (Figure 17.68). C1 −

ON

+

+ Vm Vm

Discharge of C2 Recharging of C2

D2

2IL

+

OFF

D1

+

IL C2

2Vm

IL

Ripple RL VO

− 0

−

0

π

2π

3π

Figure 17.68 Recharging of C2 when D1 is OFF and D2 is ON

When D2 is ON, C1 supplies IL and also the recharging current of C2. The recharging current of C2 must be IL to maintain 2Vm on C2. Hence, the total current supplied by C1 is 2IL. Therefore, ∆VO T supplied by C1 during is 2 2I 2I T ∆VO = L t or C1 = L (17.83) C1 2 ∆VO Comparing Eqs (17.82) and (17.83), it can be seen that C1 = 2C2 Example 17.13 The input to a half-wave doubling circuit is 15 sin (2p × 1 × 103 × t). Determine the values of C1 and C2 so as to limit the peak-to-peak ripple to 2 percent of the output voltage. RL = 10 kΩ. Solution: Neglecting a small voltage drop across the ON diode, VO = 2Vm = 2 × 15 = 30 V. VO 30 = = 3 mA RL 10 1 T Frequency of the input signal, f = 1 kHz. Therefore, T = = 1 mS. Hence, = 0.5 mS. f 2 Of the total output ripple of 2 percent, 1 percent can be considered to be due to the discharge T T of C2 for , and the other 1 percent due to the discharge of C1 during the other . 2 2 T Change in the output voltage ∆VO for during the discharge of C2 = 1 percent of 30 V = 300 mV. 2 ∴ IL =

Voltage Regulators

C2 =

913

I Lt 3 × 10 −3 × 0.5 × 10 −3 = = 5 µF ∆VO 300 × 10 −3 C1 =2 C2 = 2 × 5 = 10 µF

The circuit in Figure 17.64 can also be redrawn as in Figure 17.69. C1 − N1 230 V, 1φ 50c/s Mains

N2 Vs = Vmsinωt

D1

0

C2 − + 2Vm

Figure 17.69 Redrawn circuit of Figure 17.64

In case −2Vm is to be the output voltage, then the diode terminals in circuit 17.64 are reversed as in Figure 17.70. C1

D2 −

N1 230 V, 1φ 50c/s Mains

N2 Vs = Vmsinωt

D1

C2

Vo = −2Vm

0 +

Figure 17.70 Half-wave voltage doubler with output –2Vm

The circuit in Figure 17.70 can be redrawn as in Figure 17.71. Vm + N1 230 V, 1φ 50c/s Mains

−

C1 N2 Vs = Vmsinωt 0

D1

D2

C2 + − 2Vm

Figure 17.71 Redrawn orcuit of Figure 17.70.

17.8.2 Full-Wave Voltage Doubler Consider the full-wave bridge rectifier shown in Figure 17.72. If in this circuit, D3 and D4 are replaced by C1 and C2, respectively, then the resultant circuit is a full-wave voltage doubler with RL = ∞ (Figure 17.73).

914

Electronic Devices and Circuits

− Vs = Vmsinωt

D2

D1 +

VO

−

RL

0

D4

D3

Figure 17.72 Full-wave bridge rectifier

Vs = Vmsinωt

D2

D1 VO +

−

0

C2

C1

Figure 17.73 Full-wave voltage doubler

The circuit in Figure 17.73 can be redrawn as in Figure 17.74. It can be noted from Figure 17.74 that during the positive-going half cycle of the input signal, D1 is ON and D2 is OFF. As a result, C1 charges quickly to Vm through a small forward resistance of D1 Figure 17.75. During the negative-going half cycle of the input D2 conducts and D1 is OFF (Figure 17.76). There is no path for the discharge of the voltage Vm on C1. It remains unaltered. C2 now charges to Vm through the small forward resistance of D2 with a polarity as shown. From Figure 17.76, it can be noted that the total voltage across the two capacitors is 2Vm. In addition, it can also be noted that this circuit derives two voltages equal in magnitude and opposite in polarity with respect to the reference. D1 + Vmsinωt

D2

C1

0 −

C2

Figure 17.74 Redrawn circuit of Figure 17.73

Cascaded Voltage Multiplier Circuits Figure 17.77 is a two-stage voltage multiplier, where two voltage doubling circuits shown in Figure 17.69 are cascaded. The circuit in Figure 17.77 is redrawn as in Figure 17.78. During the negative-going half cycle of the input, D1 conducts charging C1 to Vm. During the positive-going half cycle, D1 is OFF and D2 is ON. C2 is charged to 2Vm as in the case of a voltage

Voltage Regulators

915

D1 ON D2 OFF

+ Vmsinωt

+

C1

0

Vm −

0 C2

Figure 17.75 Circuit of Figure 17.74 during the positive-going half cycle of the input D1 OFF − Vmsinωt

+

ON D2 0

C1

Vm −

0 + Vm C2 −

Figure 17.76 Circuit of Figure 17.74 during the negative-going half cycle of the input 3Vm 2Vm − +

Vm

−

+

+

C1

−

vs = Vmsinωt

0

D2 D1

D4 D3

C2 −

C3

+

C4 −

2Vm

+ 2Vm

4Vm

Figure 17.77 Two-stage voltage doubler

doubling circuit. During the next negative half cycle as once again D1 conducts (ideally short circuit) and D2 is OFF, D3 now conducts, charging C3 to 2 Vm through the small forward resistance of D3. During the next positive half cycle, D2 conducts and D3 is OFF. C4 is now charged to 2 Vm through D4, which is ON. The resultant output voltage taken across C1 and C2 is 3 Vm and that taken across C2 and C4 is 4 Vm. In the first case, the multiplier is called a tripler; and in the second case. it is called a quadrupler. A two-stage voltage doubler circuit, in which voltages of opposite polarities when compared to that in circuit in Figure 17.77 are derived, is shown in Figure 17.79. The circuit in Figure 17.79 is redrawn as shown in Figure 17.80.

916

Electronic Devices and Circuits

D4 + C4 2Vm

+

D3

−

Vm

2Vm −

C3

+

D2 C2

+

2Vm −

− C1 D1

0

0

+

Figure 17.78 Redrawn circuit of Figure 17.77 −3Vm 2Vm

Vm +

+

− C1

− C3

+ vs = Vmsinw t

D2

D1

D4 D3

−

C2 0

+

C4

− 2Vm −2Vm

+

2Vm

−4Vm

Figure 17.79 Two-stage negative voltage doubler D4 − C4 2Vm

−

2Vm +

C3 D3

+

D2 Vm

−

−

C2

2Vm +

+ C1 D1

0

+

0

Figure 17.80 Redrawn circuit of Figure 17.79

−

Voltage Regulators

917

Additional Solved Examples Example 17.14 For the Zener regulator shown in Figure 17.81, find the value of RS and the power dissipation in it. The unregulated input varies from 20 to 25 V. The dissipation in the Zener, PZ = 5 W and VZ = 10 V. RL = 100 Ω, I Z(min) = 5 mA and I L(min) = 0. Ii

IL

RS

+

+

Vi

IZ

VZ

RL

VO −

−

Figure 17.81 Zener regulator

P 5 Solution: I Z(max ) = Z = = 500 mA VZ 10

RS( max ) =

I L ( max ) = Vi( min) - VZ

I Z ( min) + I L ( max )

RS(min) =

VZ 10 = = 100 mA RL 0.1

=

Vi(max ) − VZ I Z(max ) + I L(min)

20 - 10 = 95.24 W 5 + 100

=

25 − 10 = 30 Ω 500 + 0

Choose RS as (i) RS =

RS( min) + RS( max ) 2

=

95.24 + 30 = 62.62 W 2

Or as (ii) RS(min) < RS < RS(max ), Choose RS = 50 Ω. I i(max ) = I Z(max ) + I L(max ) = 500 + 100 = 600 mA The dissipation PS in RS is

(

2 PS = I i(max) RS = 600 × 10 −3

2

)

× 50 = 18 W

Example 17.15 In the circuit shown in Figure 17.82, the Zener diode is used to prevent overloading the volt meter that has a full-scale deflection (FSD) of 20 V. The series resistance of the meter Rm is 1 kΩ and ( R1 + R2 ) is 99 kΩ.VZ = 15 V. The Zener diode conducts only when Vi > 20 V and shunts away the meter current. Find R1 and R2 . Solution: When Vi = 20 V, the Zener diode is OFF and the resultant circuit is as shown in Figure 17.83.

918

Electronic Devices and Circuits

R1

R2

Rm

+ Vi VZ

−

200 µA

Figure 17.82 Zener circuit

From Figure 17.83, Vi 20 = = 200 µA (FSD) R1 + R2 + Rm 99 + 1

I=

I

R1

R2

Rm

+

Zener OFF

Vi −

200 µA

Figure 17.83 Circuit whenVi = 20 V

When Vi > 20 V, the Zener diode is ON and the resultant circuit is as shown in Figure 17.84. R2

Rm VZ = 15 V

200 µA

Figure 17.84 Circuit whenVi > 20 V and the Zener diode is ON

From Figure 17.84, R2 + Rm =

VZ 15 = = 75 kΩ I 200 × 10 −6

Given Rm = 1 kΩ. Therefore, R2 = ( R2 + Rm ) − Rm = 75 − 1 = 74 kΩ Also given that ( R1 + R2 ) = 99 kΩ. Therefore, R1 = ( R1 + R2 ) − R2 = 99 − 74 = 25 kΩ. Example 17.16 For the Zener regulator shown in Figure 17.85, Vi = 25 V, VZ = 10 V, I Z(min) = 5 mA, I Z(max ) = 100 mA , and RS = 100 Ω. Determine the minimum and the maximum values of RL .

Voltage Regulators

Rs = 100 + +

+

Vi = 25 V

RL

Vo

VZ = 10 V

−

− −

Figure 17.85 Regulator circuit

Solution: With RL = ∞, I L = 0. The circuit is as shown in Figure 17.86. Rs = 100 I = IZ +

+ Vi = 25 V

VZ = 10 V

−

−

Figure 17.86 Circuit when RL = ∞

From Figure 17.86, I = IZ =

Vi − VZ 25 − 10 = = 150 mA 100 RS

If the load is open, I Z > I Z(max ) . The excess current, I E should be shunted away through RL . I E = I Z − I Z(max ) = 150 − 100 = 50 mA Therefore, RL(max ) =

VZ 10 = = 200 Ω I E 50

As RL decreases, I L increases. But I Z should not be allowed to fall below I Z(min) = 5 mA .

(

)

Vi = I L(max ) + I Z(min) RS + VZ ∴ I L(max ) RS = Vi − VZ − I Z(min) RS Or I L(max ) =

Vi − VZ − I Z(min) RS RS

=

25 − 10 − 5 × 10 −3 × 100 = 145 mA 100

Therefore, RL(min) =

VZ I L(max )

=

10 = 69 Ω 145

919

920

Electronic Devices and Circuits

Example 17.17 For the Zener regulator shown in Figure 17.87, VZ = 10 V, I Z(min) = 5 mA , and I Z ( max ) = 50 mA . Calculate the range of the input voltage over which the output voltage will remain constant. Rs = 1 I +

IL +

Vi −

IZ

RL

+ Vo

VZ = 10 V − −

Figure 17.87 Zener regulator

Solution: If Vo is to remain constant, then I L should remain constant. Given that RL = 1 kΩ and VZ = 10 V . Therefore, IL =

VZ 10 = = 10 mA 1 RL

For Vi = Vi(min), I Z = I Z(min) = 5 mA ∴ I = I Z(min) + I L= 5 + 10 = 15 mA Hence, Vi(min) = VZ + IRS = 10 + (15)(1) = 25 V For Vi = Vi(max ) , I Z = I Z(max ) = 50 mA ∴ I = I Z(max ) + I L = 50 + 10 = 60 mA Hence, Vi(max ) = VZ + IRS = 10 + (60 )(1) = 70 V Therefore, Vi can vary from 25 V to 70 V, for Vo to remain at 10 V. Example 17.18 For the regulator circuit shown in Figure 17.88, determine I L(min) and I L(max ) for which the Zener diode behaves as a regulator. Also determine RL(min). I Z(min) = 5 mA and I Z(max ) = 50 mA.

921

Voltage Regulators

Rs = 150 I

+

IL

+

+

Vi = 25 V

IZ

RL

Vo

VZ = 10 V

−

− −

Figure 17.88 Regulator circuit

Solution: From Figure 17.88, I=

Vi − VZ 25 − 10 = = 100 mA 150 RS

I = I L + I Z = constant

If I L = I L(min), then I Z = I Z(max ) ∴ I = I L(min) + I Z(max )

I L(min) = I − I Z(max ) = 100 − 50 = 50 mA

If I L = I L(max ), then I Z = I Z(min) ∴ I = I L(max ) + I Z(min)

I L(max ) = I − I Z(min) = 100 − 5 = 95 mA

I L can vary from 50 to 95 mA. RL (min) =

VZ I L (max )

=

10 = 105 Ω 95

Example 17.19 The peak-to-peak ripple at the input of a Zener regulator shown in Figure 17.89 is 3 V. RS = 150 Ω, rZ = 10 Ω, VZ = 10 V, and I L = 50 mA. Find the ripple at the output. Rs = 150 +

∆I

Rs = 150 IL

+ ∆IZ ∆Vi

RL

VZ = 10 V

+

+

∆Vo

∆Vi = 3 V

−

−

∆I

IL rZ

∆IZ

Figure 17.90 Incremental circuit

Solution: The incremental circuit is shown in Figure 17.90. From Figure 17.90, RL = ∆I =

∆Vo −

−

Figure 17.89 Regulator circuit

RL

+

VZ 10 = = 200 W I L 50 ´ 10 -3

∆Vi 3 = = 18.81 mA. RS + RL rZ 150 + 20010

922

Electronic Devices and Circuits

D I Z = DI ´

RL 200 = 18.81 ´ = 17.91 mA rZ + RL 10 + 200

DVo = DI Z ´ rZ = 17.91 ´ 10 = 179.1 mV Example 17.20 For the Zener regulator, RS = 150 Ω, VZ = 10 V. (i) Calculate Vi if I Z = 20 mA and I L = 30 mA. (ii) If Vi changes to 25 V, calculate the new value of I Z , assuming I L constant. Solution: (i) I =

Vi − VZ Vi −10 = RS 150 ∴

Also I = I L + I Z = 30 + 20 = 50 mA. Vi − 10 = 50 × 10 −3× 150

− Vi − 10 = 7.5 V

Vi = 7.5 + 10 = 17.5 V (ii) I =

Vi − VZ 25 − 10 = = 100 mA. RS 150

I Z = I − I L = 100 − 30 = 70 mA

Example 17.21 For a Zener regulator, I L(max ) = 100 mA, I L(min) = 0 mA,VZ = 10 V, RS = 100 Ω and rz = 5 Ω. Vi varies from 20 to 25 V. Calculate (i) maximum power dissipated in RS, (ii) maximum power dissipated in the Zener, (iii) % load regulation, when Vi = 25 V and the nominal output voltage is 10 V. Solution: The Zener regulator when the Zener diode is replaced by its equivalent circuit is shown in Figure 17.91. Rs = 100 +

VZ

I

Vi rZ = 5

IL IZ

RL

+ VO −

−

Figure 17.91 Equivalent circuit of the Zener regulator

Dissipation in the Zener diode, and RS is maximum when Vi = 25 V. We therefore first consider when Vi = 25 V. (i) Maximum power dissipated in RS : Given, I L(max ) = 100 mA. From Figure 17.91, I = IL + IZ Also I=

Vi − VO 25 − Vo = 100 RS

Voltage Regulators

923

and IZ =

∴

25 − VO VO − 10 = + 100×10 −3 100 5

VO − VZ VO −10 = rZ 5

or 25 − VO = 20 (VO − 10 ) + 10 VO =

21VO = 25 + 200 − 10 = 215

215 = 10.24 V 21

Hence, IZ =

VO − 10 10.24 − 10 = = 48 mA 5 5

I = IL + I Z = 100 + 48 = 148 mA

(

)

2

PRS = I 2 RS = 148 ´ 10 -3 100 = 2.19 W (ii) Maximum power dissipated in the Zener: PZ (max ) = VO I Z = 10.24 × 48 × 10 −3 = 0.492 W. (iii) % load regulation, when Vi = 25 V: To find VO(NL), open RL , Figure 17.92. Rs = 100 +

I

Ri = 25 V −

+

VZ rz = 5

IZ

VO −

Figure 17.92 Circuit when RL = ∞

When RL = ¥, I L = 0 . Then I = I Z =

Vi - VZ 25 - 10 = = 142.86 mA RS + rZ 100 + 5

VO( NL ) = VZ + I Z rZ = 10 + 142.86 ´ 10 -3 ´ 5 = 10.714 V % load regulation =

VO(NL) − VO(L) VO(Nominal)

× 100 =

10.714 − 10.24 × 100% = 4.74% 10

Example 17.22 For the transistor series regulator, calculate (i) VO, (ii) PD, the dissipation in the transistor, (iii) PZ, the dissipation in the Zener diode, (iv) SV, and (v) Ro. The circuit components are R = 500 Ω, RL = 1 kΩ. The parameters of the devices are rZ = 10 Ω, hie = 100 Ω, hfe = hFE = 50, VZ = 10 V, VBE = 0.7 V and Vi = 25 V.

924

Electronic Devices and Circuits

Solution: (i) VO = VZ − VBE = 10 − 0.7 = 9.3 V (ii) VCE = Vi − VO = 25 − 9.3 = 15.7 V

IL = IC =

VO 9.3 = = 9.3 mA RL 1

\ PD = VCE I C = 15.7 ´ 9.3 = 146 mW (iii) I R =

Vi − VZ 25 − 10 = = 30 mA R 500

IB =

IC 9.3 = = 0.186 mA hFE 50

\ I Z = I R - I B = 30 - 0.186 = 29.814 mA PZ = VZ I Z = 10 ´ 29.814 = 298.14 mW rZ 10 = = 0.0196 R + rZ 500 + 10 h +r 100 + 10 (v) Ro = ie Z = = 2.16 W 1 + hfe 1 + 50

(iv) SV =

Example 17.23 For the circuit shown in Figure 17.37, find VO(max) and VO(min), given that R1 = 5 kΩ, R5 = 5 kΩ, R2 = 10 kΩ, VBE2 = 0.7 V, and VZ = 6.8 V. Solution: From Eqn. (17.56),  5 + 5 + 10  VO(max ) = ( 0.7 + 6.8)  = 15 V.  10  From Eqn. (17.57),  5 + 5 + 10  ∴VO(min) = ( 0.7 + 6.8)  = 10 V.  10 + 5  VO can be adjusted between 10 V and 15 V. Example 17.24 Design the regulator circuit shown in Figure 17.93. It is desired to get VO ranging from 15 to 18 V. IQ = 5 mA. 1 + 3 VI −

2

IC7812 + RREF −

IQ IQ

R1

+

I1 VO = 15 to 18 V R2 I2 −

Figure 17.93 Regulator

Voltage Regulators

Solution: R1 =

925

VREF . Usually I1 » I Q. Choose I1 = 5I Q = 5 ×5 = 25 mA I1 I 2 = I1 + IQ = 5I Q + I Q = 6 IQ = 6 × 5 = 30 mA R2 =

VO − VREF I2

(i) If VO = 15 V, then R2 =

VO −VREF 15 − 12 V 12 = 100 Ω and R1 = REF = = 480 Ω = I2 25 30 I1

(ii) If VO = 18 V, then R2 =

VO − VREF 18 − 12 V 12 = 200 Ω and R1 = REF = = 480 Ω = I2 25 30 I1

Example 17.25 Design an adjustable voltage regulator using LM317 to derive the output voltage ranging from 5 to 10 V. For LM317, Iadj = 0.1 mA, and VREF = 1.25 V. Solution: The regulator using LM317 is shown in Figure 17.94. Input

LM 317

+ Adj VI = 15 V

Iadj

−

Output + RREF − Iadj

R1

+ VO = 5 to 10 V

R2

−

Figure 17.94 Regulator using LM317

From Figure 17.94, when Iadj = 0 VREF = VO

R1 R1 + R2

 R  or VO = VREF 1 + 2   R1 

When Iadj is considered,  R  VO = VREF 1 + 2  + I adj R2  R1  Choose R1 = 480 Ω (i) For VO = 5 V R   5 = 1.25 1. + 2  + 0.1 × R.2  480 

R2 3.75 = R22.6R2 + 0.1 × R.21 = R 2.27R22. R2 ∴ R2 =

3.75 = 1.38 kΩ 2.7

926

Electronic Devices and Circuits

(ii) For VO = 10 V R   10 = 1.25 1.+ 2  + 0.1 ×+ R.2 × R2 8.75 R = 22.6R2 + 0.1 × R2 = 2.7R2  480  ∴ R2 =

8.75 = 3.24 kΩ 2.7

Example 17.26 For the low-voltage, low-current regulator using IC723 shown in Figure 17.95, Vi = 12 V, VO = 5 V, VSC = 0.7V, and I L = 100 mA. Design the circuit. Vi = 12 V

12

11

VCC

6 R1

R2

I1

10

Output VREF

723

I1 5

VC

2

RSC

CL 3

IL

VO = 5 V +

CS Non-Inv −VCC 7

Inv FC

4

R3

13 100pF

Figure 17.95 Low-voltage, low-current regulator using IC723

Solution: R1 =

VR − VO . Choose I1 = 1 mA I1 ∴ R1 = R2 =

7 −5 = 2 kΩ 1

VO 5 = = 5 kΩ I1 1

R3 = R1 || R2 =

2×5 = 1.43 kΩ 2+5

For IC723, from the data sheet, 966 Ω ≤ R3 ≤ 3.52 kΩ. Hence, R3 = 1.43 kΩ is acceptable. RSC =

VSC 0.7 = = 7W I L 100

Voltage Regulators

927

Summary • The output voltage VO of regulator can change by ∆VO due to an incremental change ∆Vi in Vi or due to an incremental change ∆I L in load current IL or due to a small change ∆T in temperature T. • Ripple rejection is the ability of the power supply to reject ripple and is usually expressed in dB. • The simplest of the regulator circuits is the Zener shunt regulator. But its main limitation is that to control VO, IZ varies by larger amounts. • The basic transistor shunt regulator controls the variations in output voltage with smaller variations in base current. • In the absence of a current-limiting circuit, excessive current flows in the series pass transistor. To prevent this occurrence, the current limit circuit will reduce the base current to the series pass transistor, thereby ensuring the maximum safe current limit, IL(max) is not exceeded. • In a fold-back current limiting circuit, when short circuit occurs the maximum current through the series pass transistor is limited to ISC, which is very much smaller than IL(max), thereby ensuring the safety of the regulator. • In high-current regulators, a Darlington emitter follower is used as a series pass transistor. • The overvoltage protection circuit is based on brute force: when the power supply voltage increases too much, the thyristor short circuits the output. This means that the overvoltage is quickly removed from equipment. • In a switching regulator, the unregulated dc is chopped by switching a transistor ON and OFF by a pulse train whose duty cycle decides the dc voltage at the output, • Switching regulators basically are (i) buck-type or step-down regulators, (ii) boost-type or step-up regulators, and (iii) buck–boost-type or step-down–step-up-type regulators. • An SMPS is an electronic power supply that uses a switching regulator to convert electrical power efficiently to dc. • Voltage multipliers are used to derive large output dc voltage using a transformer of smaller number of turns on the secondary.

multiple ChoiCe QueStionS 1. The stability factor SV is defined as ∆VO (a) ∆I L = 0, ∆T = 0 ∆Vi (c)

∆VO ∆I L

∆Vi = 0, ∆T = 0

2. A Zener regulator is an example of (a) shunt regulator (c) feedback regulator 3. Ripple rejection in dB is defined as V (a) 20log10 i VO V (c) 20log10 O Vi

(b)

(d)

∆Vi ∆VO ∆I L ∆VO

∆I L = 0, ∆T = 0 ∆Vi = 0, ∆T = 0

(b) series regulator (d) none of these

(b) 20log10

Vor(pp) Vir(pp) VO

(d) 20log10

VO

928

Electronic Devices and Circuits

4. One of the main limitations of a Zener regulator is that to control VO, IZ varies by (a) small amounts (b) large amounts (c) remains unchanged (d) none of these 5. The advantage of a transistor shunt regulator over Zener regulator is that (a) large changes in IB only can effectively control VO (b) small changes in IB can effectively control VO (c) if Vo changes, only constant IB can control VO (d) none of these 6. One major limitation of a transistor shunt regulator is that it is difficult to (a) control VO when Vi changes (b) control VO when IL changes (c) control VO when temperature changes (d) implement current limit and overload protection 7. For a Zener shunt regulator, if rZ = 10 and RS = 100 Ω, then (a) SV = 20% (b) SV = 1% (c) SV = 10% (d) SV = 0.1% 8. For a transistor shunt regulator, if hie = 1000 Ω, hfe = 100 and RS = 100 Ω, then (a) SV = 10% (b) SV = 1% (c) SV = 20% (d) SV = 0.1% 9. To prevent damage to the regulator (a) overload and short-circuit protection is provided in a regulator (c) IO is made zero

(b) VO is shorted (d) Vi is made zero

10. The main limitation of simple current limit is that when there is an overload or short circuit, the dissipation in the series pass transistor becomes (a) small (b) zero (c) large (d) none of these 11. In a fold-back current limiting circuit, when short circuit occurs the maximum current through the series pass transistor is limited to ISC which is (a) very much larger than IL(max), (b) very much smaller than IL(max) (c) equal to IL(max), (d) none of these 12. In a high current regulator circuit using an error amplifier, to effectively control VO, in place of a single series pass transistor (a) a Darlington transistor is used (b) a complementary pair is used (c) a high power transistor is used (d) a low-power transistor is used 13. If in a regulator, the series pass transistor is shorted, to provide protection to the external circuit, the following protection circuit is used: (a) constant current limit (b) fold-back current limit (c) overvoltage protection (d) reverse polarity protection 14. If in a regulator there is accidental reversal in polarity, to provide protection to the external circuit as well as to the regulator, the following protection circuit is used: (a) constant current limit (b) fold-back current limit (c) overvoltage protection (d) reverse polarity protection 15. The two main limitations of the linear regulators are (a) low efficiency and high power dissipation (b) high efficiency and low power dissipation

Voltage Regulators

929

(c) low efficiency and low power dissipation (d) High efficiency and high power dissipation 16. The two main advantages of the switching regulators are (a) low efficiency and high power dissipation (b) high efficiency and low power dissipation (c) low efficiency and low power dissipation (d) high efficiency and high power dissipation 17. An SMPS is an electronic power supply that uses (a) a switching regulator (b) a fixed three-terminal linear regulator (c) a general-purpose linear regulator (d) an adjustable three-terminal linear regulator 18. A current that can be larger than the maximum rated current of an IC regulator but is allowed to be drawn only for a short duration is called (a) the peak output current (b) the average current (c) RMS current (d) input current 19. The minimum voltage difference that must exist between the input and the output terminals of the IC regulator to operate properly is called (a) dropout voltage (b) output voltage (c) input voltage (d) safe operating voltage 20. Buck-type regulator is a (a) step-up regulator (c) step-up/step-down regulator

(b) step-down regulator (d) none of these

Short anSwer QueStionS 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11.

What are the factors responsible for the output of a TRF power supply to change? What is ripple rejection? Express it mathematically. Where is the need for a voltage regulator? What are the main limitations of the simple Zener regulator? What are the main limitations of the transistor shunt regulator? What is the main advantage of the transistor series regulator over a transistor shunt regulator? What are its limitations? Where is the need for the overload or short-circuit protection in a power supply? List two methods using which current limit and overload protection can be provided. Mention the various types of protection mechanisms implemented in a regulated power supply. What are the advantages of the IC regulators? How are IC regulators broadly classified?

12. What is the main limitation in linear IC regulators and how is it overcome in switching regulators? 13. What are the different types of switching regulators? 14. What is an SMPS?

930

Electronic Devices and Circuits

long anSwer QueStionS 1. Draw the circuits of simple transistor shunt and series regulators and explain their working. List the advantages and limitations of each type. 2. With a neat circuit diagram, explain how current limit and overload protection is implemented in a series regulator. 3. Draw the circuit of a feedback regulator using an error amplifier and explain its working. Calculate VO. Suggest a method to vary the output voltage. Calculate VO(max) and VO(min). 4. Illustrate the procedure to design a feedback regulator. 5. Write short notes on (i) (ii) (iii) (iv) (v)

constant current limit and fold-back current limit high current feedback regulator voltage multipliers overvoltage protection reverse polarity protection.

6. Explain the principle of operation of a buck-type switching regulator and derive the expression for its output voltage as a function of the duty cycle. Draw the relevant waveforms. Draw also the control circuit and explain its operation. 7. Write short notes on (i) boost-type regulator and (ii) buck–boost-type regulator 8. Write short notes on (i) half-wave and (ii) full-wave doubling circuits.

unSolved problemS 1. For the Zener regulator shown in Figure 17.96, determine the value of I L(min) and the minimum and the maximum values of RL , given that PZ = 300 mW, RS = 500 Ω , and VZ = 10 V Ii +

+

RS

Vi 45 V −

IL

+ VR−

IZ

VZ 10 V −

+ RL

VO −

Figure 17.96 Zener regulator 2. For the Zener regulator shown in Figure 17.96, determine the minimum and the maximum values of Vi that will keep the Zener ON, if RL = 200 Ω and RS = 500 Ω, I Z(max) = 30 mA, and VZ = 10 V. 3. Calculate VO , I L , I B , and I Z for the voltage regulator circuit shown in Figure 17.97. R = 200 Ω, hFE = 60, RL = 500 Ω, and VZ = 6.8 V

Voltage Regulators

Ii

931

IL Q

+ 25 V

IB IR = IB + IZ

− VBE 0.7 V

+

+

R

RL

Vi +

Unregulated input

Iz D

VO −

VZ −

−

Figure 17.97 Series transistor regulator 4. For the voltage regulator shown in Figure 17.98, VO = 9 V and R1 = 1 kΩ. Calculate the value of R2 . For LM317, Iadj = 0.1 mA and VREF = 1.25 V Input

LM 317

Output

+

+ Adj

VREF

R1

+

I1

− V1 = 15 V −

VO = 9 V ladj ladj

R2 −

Figure 17.98 IC regulator 5. For the circuit shown in Figure 17.37, find VO(max) and VO(min), given that R1 = 5 kΩ, R5 = 5 kΩ, R2 = 10 kΩ, VBE2 = 0.7 V, and VZ = 6.8 V 6. Design the complete feedback regulator circuit shown in Figure 17.38. It is required that VO = 15 V. Vi = 25 ±5 V, IL(max) = 500 mA and hFE of Q1 and Q2 is 50. IC2 = 15 mA.

18

MULTIVIBRATORS

Learning objectives After reading this chapter, the reader will be able to      

18.1

Understand the method of analysis and design of the bistable multivibrators Know the methods of triggering a binary Appreciate the difference between the saturating and nonsaturating binary Understand the principle of working of monostable multivibrator and application of monostable multivibrator as a voltage-to-time converter Understand the principle of working of collector-coupled astable multivibrator and application of an astable multivibrator as a voltage-controlled oscillator Principle of operation of a Schmitt trigger

INTRODUCTION

A multivibrator is a regenerative circuit that uses two devices (may be BJTs or FETs) Q1 and Q2. In these circuits, the output of one device is fed back as input to the other. The prerequisite for the circuit to function is that if one device is ON, the other device is OFF. The ON device may be driven into the active region or into saturation. The states of the two devices can be interchanged either with the help of an external pulse (called trigger) or through capacitive coupling. Multivibrators are classified as bistable multivibrators, monostable multivibrators, or astable multivibrators. A bistable multivibrator, as the name implies, has two stable states. Let Q1 be ON and Q2 be OFF. This is one stable state for the multivibrator. Q1 remains ON and Q2 remains OFF till such time that an external trigger of proper magnitude and polarity is applied. On the application of this trigger signal, regenerative action takes place and Q1 that was initially in the ON state now would switch into the OFF state and Q2 that earlier was in the OFF state will switch into the ON state. This is other stable state for the bistable multivibrator. Once again, only when an external trigger is applied, change of state for the devices occurs. A bistable multivibrator is basically two inverters connected back to back. A transistor in the CE mode can be used as an inverter. We are aware that in CE mode, when the transistor is OFF, the voltage at its collector is VCE = VCC, the supply voltage and when it is ON and driven into saturation VCE ≈ 0 V. A voltage VCC is termed as a 1 level, in terms of binary representation and a voltage 0 V is termed as a 0 level (positive logic). Initially, it is assumed that the voltage at the collector of Q1 corresponds to a 0 level and that at the collector of Q2 was at 1 level. If no trigger is applied, then the 0 would have remained as a 0 and the 1 would have remained as 1. Only when a trigger is applied, the 0 at the collector of Q1 has become a 1 and the 1 at the collector of Q2 has become a 0. Obviously, this means that

Multivibrators

933

the contents of this register will remain unaltered till an external trigger is applied. As such, a bistable multivibrator can be used as a one bit memory element in digital circuits. The bistable multivibrator is also called as a binary, flip-lop, scale-of two circuit (for every two trigger pulses, there appears one pulse at the collectors) and also as an Eccles–Jordan circuit (named after the designers of the vacuum tube version). A monostable multivibrator, sometimes also referred to as a one-shot multivibrator, also has two possible states, only one of which is stable. In this circuit, the output of one device (say Q1) is connected to the input of Q2 through an RC circuit, whereas the output of Q2 is connected to the input of Q1 through a resistance network only. Once again, let us assume that Q2 is ON and Q1 is OFF. This is the stable state for this multivibrator. The multivibrator (henceforth also referred to as multi) will remain in this state forever till an external trigger is applied. When a proper trigger is applied, Q1 switches to the ON state and Q2 switches to the OFF state. However, these two devices are not going to remain in these states forever because of the discharge of the condenser that will drive the multi once again into the initial stable state of Q1 OFF and Q2 ON. On the application of the trigger as Q1 goes ON and Q2 goes OFF and as this state of the devices is not going to exist forever because of the discharge of the condenser, the multi is said to be driven into the quasistable condition. Only after a finite time interval elapses (decided by the time constant used) the multi will again return back to the initial stable state, ending the quasistable condition. The main application of this circuit is to generate a pulse for finite time duration T, which is called the gate width, pulse width, or pulse duration of the monostable multivibrator. With the help of this pulse, it is possible to control some other circuit for a time duration T. An astable multivibrator has two possible states, neither of which is stable (two quasistable states), and switches automatically between the two states, usually controlled by two RC-coupling circuits. Change of state in the devices occurs automatically as decided by the time constants used in the circuit. If the two time constants are the same, then the circuit is called a symmetric astable mutlivibrator; and if the time constants differ, the circuit is called an unsymmetric astable multivibrator. The voltage levels abruptly change between VCC and VCE(sat) at the end of a time interval. Hence, the astable circuit is called a relaxation oscillator, which is essentially a squarewave generator. An astable multivibrator is also called a free-running multivibrator. The main application of this circuit is as a clock in digital circuits.

18.2 TRANSISTOR AS A SWITCH BJT or FET can be used as switch. When a switch is ON, ideally the resistance between the switch terminals should be 0; when it is OFF, its resistance should be ∞. (i) Let us now consider an Si transistor as a switch (Figure 18.1). Here, the circuit conditions are adjusted such that the transistor is in the active region (since VBE = 0.6 V and VCB = 4.4 V). The switch is ON. The ON resistance (the resistance between the collector and emitter terminals) of the switch is RON =

VCE 5V = = 5 kΩ 1 mA IC

Such a large resistance between the switch terminals, when it is supposed to be in the ON state, is not normally acceptable.

934

Electronic Devices and Circuits VCC = 10V RC = 5kΩ

IC = 1mA

VCB = 4.4V + + − VCE = 5V + − VBE = 0.6V

0.6V 0

RON = 5kΩ

Figure 18.1 Transistor in the active region

When the transistor is driven into saturation VCE = VCE(sat) = 0.2 V. Since VBE = 0.7 V and VCB = −0.5 V, both the diodes are forward biased. IC = IC(sat) = 1.96 mA. Its ON resistance becomes 100 Ω, which is very small (Figure 18.2). Now, the transistor behaves as a closed switch. VCC = 10V RC = 5kΩ VCB = −0.5V − + VBE = 0.7V

0.7V

IC(sat) = 1.96 mA

+ VCE(sat) = 0.2V −

0 RON = 100kΩ

Figure 18.2 Transistor in saturation

RO N =

VCE(sat) I C(sat)

=

0.2 V ≈ 100 Ω 1.96 mA

(ii) Let now the input to the switch be 0 V. Since VBE = 0, IB = 0. Therefore, ideally, IC = 0. Hence, the drop across RC is 0, and hence VCE = VCC (Figure 18.3). The OFF resistance of the transistor switch now is RO FF =

VCC 10 = =∞ IC 0

But, in practice, IC is not ideally zero, and there exists a leakage current called ICEO. If typically, ICEO = 0.01 mA, then RO FF =

VCC 10 V = = 1MΩ I CEO 0.01mA

Multivibrators

935

If an OFF switch has a resistance of 1 MΩ between its terminals, then this condition is unacceptable (Figure 18.4). Therefore, in order to derive large OFF resistance, the base-emitter diode is actually reverse biased to reduce the leakage current from ICEO to ICBO = ICO. If for the given transistor, ICO = 1 μA, then RO FF =

VCC 10 V = = 10 MΩ I CO 1 µA VCC = 10V RC = 5kΩ

IC = 0 mA

+ VCB = 10V − + VBE = 0V

0.7V

+ VCE = 10V −

0 ROFF = ∞

Figure 18.3 Transistor in the OFF state VCC = 10V RC = 5kΩ

IC = ICEO = 0.01 mA

VCB = 9.95V +

− 0.7V

+ VBE = 0V

+ VCE = 10V −

0 ROFF = 1MOhm

Figure 18.4 OFF switch with leakage current

In many applications, even this value of ROFF is not acceptable. However, we know that Si devices are preferred over Ge devices mainly because the leakage currents are smaller. If for the Si device ICO = 5 nA, then RO FF =

VCC 10 V = = 2000 MΩ I CO 1nA

This ROFF is very large; and under this condition, the switch can be said to be in the OFF state. It can be noted that a BJT can be used as a switch. Similarly, an FET can also be used as a switch. But now, the consideration is how fast one can switch the device from the ON state to the OFF state and vice versa. By now, it is known that the stray capacitances in a transistor will limit the switching speed of the device. Obviously, the switching speed depends on the switching times of the transistor.

936

Electronic Devices and Circuits

18.2.1 Switching Times of the Transistor Let a pulse of duration 10 μs and amplitude 1 V be applied as input to the transistor switch (Figure 18.5). 1V

0V

0

10 µs

TTurn-on

TTurn-off TON

IC(sat) 90% of IC(sat) IC 10% of IC(sat) 0

Td = Delay time

T1 = Rise time

Ts = Storage time

Tf = Fall time

Figure 18.5 Switching times of the transistor

At t = 0, when the input abruptly rises to 1 V, IC will not reach the steady-state value of IC(sat) instantaneously, but will take a finite time delay. The time taken for the collector current IC to reach 10 percent of its final value, that is 0.1 IC(sat) is called the delay time Td. The time taken for IC to reach 90 percent of its final value from 10 percent of its final value is called the rise time Tr. From Figure 18.5, it can be noted that when a pulse is applied at t = 0, IC is expected to reach IC(sat) and the transistor is required to go into the ON state. However, the transistor switches ON only after a time delay of (Td + Tr) elapses. This time delay is called the turn-on time of the transistor switch, Tturn-on. Once switched ON, the device is expected to switch into the OFF state when the input abruptly falls to 0. But this is not seen to be happening. This is because, once the device is driven hard into saturation, there exists a large number of stored charges on either side of the forward-biased junction and the current remains at a reasonably large value for a limited time duration called the storage time. The time taken for IC to fall from its initial value (= IC(sat)) to 90 percent of its initial value is called the storage time, Ts. Further, the time taken for IC to fall from 90 percent of its initial value to 10 percent of its initial value is called the fall time, Tf. From Figure 18.5, it is evident that the device switches OFF only after a time delay of (Ts + Tf), and this total time delay is called the turn-off time of the transistor switch, Tturn-off. TON is the time for which the switch is ON. From the above discussion, it is obvious that the transistor takes a fixed time duration to switch from the OFF state into the ON state and may be a different time delay when it switches from the ON state into the OFF state. Therefore, the switching times of the transistor will have to be taken into consideration while switching the transistor at faster switching speeds.

Multivibrators

18.3

937

BISTABLE MULTIVIBRATORS

As mentioned earlier, a bistable multivibrator is two inverters connected back to back. We consider basically two circuit variations: (i) fixed bias bistable and (ii) self-bias bistable. Further, it may be required to drive the ON transistor into saturation, or it can be held in the active region. If in the bistable multi, the ON transistor is driven into saturation, then the bistable multi is called the saturating binary. Alternately, if the ON device is held in the active region, then the binary is called the nonsaturating binary.

18.4

FIXED BIAS BINARY

First, let us consider a saturating binary. A fixed bias binary uses two separate dc sources—a VBB source and a VCC source—for biasing the devices (Figure 18.6). VCC

IC1

RC VC1

IC2

R1

VC2

C1

Q1

RC

R1 VB2

VB1

B2

B1

C2

Q2

ON Saturation

OFF R2

R2

−VBB

Figure 18.6 Fixed bias binary using NPN transistors

Since the binary is a saturating binary, the ON device is assumed to be in saturation. Even if Q1 and Q2 are chosen to be identical transistors, some amount of imbalance may exist between the two devices. As such, the hFE of one transistor may be slightly larger than the other. Hence, the transistor that has a larger hFE will switch into the ON state and the other transistor will switch into the OFF state. Therefore, the basic requirement that if one device is ON, the other should be OFF is usually satisfied. Now, it is also possible that Q1 may be ON and Q2 may be OFF, or vice versa. (i) Let it be arbitrarily assumed that in one of the stable states, Q1 is OFF and Q2 is ON and is in saturation. When Q1 is OFF, the voltage at its collector VC1 is ideally VCC since IC1 = 0. When Q2 is ON, the voltage at its collector VC2 is VCE(sat), which is typically 0.2 V for Si and 0.1 V for Ge. The voltage at its base is VBE(sat) = Vσ, which is typically 0.7 V for Si and 0.3 V for Ge. In the stable state, therefore, with Q1 OFF and Q2 ON, VB2 = Vσ , VC1 = VCC , IC1 ≈ 0, VC2 = VCE (sat), IC2 = IC(sat) (ii) To drive the binary into the other stable state, that is, Q1 ON (saturation) and Q2 OFF, a trigger (external pulse) of proper polarity and magnitude needs to be applied at one of the bases to either drive the ON device into the OFF state or to drive the OFF device into the ON state. Therefore, one can apply a negative pulse at the base of the ON device to

938

Electronic Devices and Circuits

drive it into the OFF state or a positive pulse at the base of the OFF device to drive it into the ON state. But, when it is attempted to drive an OFF device into the ON state by the application of a positive pulse, unless the magnitude of the pulse reaches Vγ the cut-in voltage, there can be no current in the device. As such, wherever it is possible, it is preferable to drive an ON device into the OFF state by the application of a negative trigger, since the devices used are NPN devices to get better triggering sensitivity. Let a negative pulse of proper magnitude be applied at B2. Before the application of the trigger VC2 = VCE(sat), which is of the order of 0.2 V, if Si transistors are used. Now when trigger is applied, IB2 decreases, therefore IC2 decreases. Then, VC2 rises from VCE(sat), resulting in a positive step change at C2. This positive step change is coupled to B1 through R1 and R2. Consequently, there can be a small base current IB1 in Q1 which results in a small collector current IC1. Earlier, VC1 = VCC, a large positive voltage. When IC1 flows through Q1, VC1 falls from VCC to a smaller value, resulting in a negative step change at its collector. This negative step change at C1 is coupled to B2 through R1 and R2. IB2 of Q2 further reduces, IC2 reduces and there results a larger positive step at C2 which is now coupled to B1. Q1 now draws a larger IB1, and hence a larger IC1 resulting in a larger negative step change at C1, thereby reducing IB2 further. Thus, we say that regenerative action takes place and Q1 which was earlier in the OFF state will now switch into the ON state and Q2 which initially was in the ON state will switch to the OFF state. The multi is now in the other stable state. To once again change the state of the devices, another trigger pulse is required.

18.4.1 Calculation of the Stable-State Currents and Voltages To calculate the stable-state currents and voltages, we first establish that Q1 is OFF and Q2 is ON and in saturation. (i) To verify that Q2 is in saturation: We first assume that Q2 is in saturation and make the necessary calculations and justify the assumption. To verify that Q2 is in saturation, we calculate IC2 and IB2, using the circuit in Figure 18.7. VCC I1

RC

IC2

RC VC2 = VCE(sat)

VC1 R1

Q1 OFF

VB2

ON

IB2

Q2

R2 I2 −VBB

Figure 18.7 Circuit to verify that Q2 is in saturation

Multivibrators

939

From the base loop, I1 =

VCC − VB2 VCC − Vs = RC + R1 RC + R1

(18.1)

I2 =

VB2 − ( −VBB ) Vs + VBB = R2 R2

(18.2)

and

Therefore, IB2 = I1 − I2

(18.3)

From the collector loop, I C2 =

VCC − VCE(sat)

(18.4)

RC

If hFE is known, then IB2(min) to keep Q2 in saturation is calculated as follows: I B2(min) =

I C2 hFE

(18.5)

If IB2 calculated using Eqn. (18.3) is much greater than IB2(min) calculated using Eqn. (18.5), then Q2 is really in saturation as per the assumption made. If Q2 is verified to be in saturation, then it can be concluded that VC2 = VCE(sat) and VB2 = Vσ (ii) To verify that Q1 is OFF: To verify whether Q1 is OFF or not, we calculate VB1. If VB1 is a negative voltage that reverse biases the base-emitter diode of Q1, then Q1 is really OFF as assumed. To calculate VB1, consider the circuit in Figure 18.8. R1 C2 Q1 OFF

VB1 Q2

VCE(sat)

R2 VBB

Figure 18.8 Circuit to calculate VB1

VB1 is due to two sources, one is −VBB source and the other is VCE(sat) source. Therefore, VB1 is calculated using the superposition theorem. Consider VCE(sat) source only, then the resultant circuit is as shown in Figure 18.9.

940

Electronic Devices and Circuits R1 C2 Q1 OFF

VB11 VCE(sat)

Q2 R2

VBB = 0

Figure 18.9 Circuit of Figure 18.8 when VCE(sat) source alone is considered

From Figure 18.9, VB11 = VCE(sat) ×

R2 R1 + R2

(18.6)

Consider −VBB source only, then the resultant circuit is as shown in Figure 18.10. R1 C2 Q1 OFF

VB12

Q1 Q2

VCE(sat) = 0

VB12 R1

OFF R2

R2 VBB

VBB

Figure 18.10 Circuit of Figure 18.8 when −VBB source alone is considered

From Figure 18.10, VB12 = −VBB ×

R1 R1 + R2

(18.7)

Combining Eqs (18.6) and (18.7), the net voltage at B1 is VB1 = VB11 + VB12 = VCE(sat ) ×

R2 R1 + ( −VBB ) × R1 + R2 R1 + R2

(18.8)

If VB1 is negative, then Q1 is OFF as assumed and VC1 = VCC. However, VC1 < VCC because, when Q1 is OFF Q2 is ON and a current I1 flows through RC and R2 (Figure 18.7). Therefore, VC1 = VCC − I1RC

(18.9)

Multivibrators

941

Example 18.1 For the fixed bias binary shown in Figure 18.6,VCC = VBB = 10 V, RC = 4 kΩ, R1 = 15 kΩ, R2 = 30 kΩ, VCE (sat ) = 0.2 V, Vs = 0.7 V, and hFE(min) = 50. Verify that Q2 is in saturation and Q1 is OFF. List the stable-state currents and voltages. Solution: I1 = and

VCC − Vs 10 − 0.7 = = 0.489 mA RC + R1 4 + 15 I2 =

Vs + VBB 0.7 + 10 = = 0.357 mA R2 30

I B 2 = I1 − I 2 = 0.489 − 0.357 = 0.132 mA

I C2 =

VCC − VCE(sat ) RC

I B2(min) =

I C2 hFE ( min )

=

10 − 0.2 = 2.45 mA 4

=

2.45 = 0.049 mA 50

I B2 » I B2(min). Hence, Q2 is in saturation. Therefore,

VB2 = 0.7 V and VC2 = 0.2 V

VB1 = VCE(sat ) ×

= 0.2 ×

R2 R1 + ( −VBB ) × R1 + R2 R1 + R2

30 15 − 10 × = 0.133 − 3.33 = −3.197 V 15 + 30 15 + 30

Therefore, Q1 is OFF and VC1 should be VCC = 10 V . But VC1 = VCC − I1RC = 10 − (0.489 mA )( 4 kΩ ) = 10 − 1.956 = 8.044 V VC1 is smaller than VCC because of loading by the cross-coupling network comprising R1 and R2 .

18.4.2 Heaviest Load the Binary Can Drive The output of the binary (collector of the OFF transistor) is sometimes connected to drive another circuit that is called the load for the binary (Figure 18.11). It is pertinent to know as to the maximum load current the binary can deliver keeping the ON transistor in saturation.

942

Electronic Devices and Circuits

Example 18.2 For the circuit considered in Example 18.1, determine the heaviest load the binary can drive. Solution: Consider the circuit in Figure 18.11. VCC I

RC

I1(min)

RC

R1

VC2 VCN1(min)

R1

VB2

Q1 IB2(min)

Q2

ON Saturation

OFF

RL(min)

R2

R2 IL(max)

I2 −VBB

Figure 18.11 Circuit to calculate IL(max) and RL(min)

From Figure 18.11 and Example 18.1, I1(min) = I 2 + I B (min) 2

(18.10)

= 0.357 + 0.049 = 0.406 mA VC1(min) = I1(min) R1 + VB2 = (0.406) (15) + 0.7 = 6.79 V

(18.11) (18.12)

I=

VCC − VC1(min) RC

=

10 − 6.79 = 0.8 mA 4

(18.13)

I L (max ) = I − I1(min)

= 0.8 − 0.406 = 0.394 mA

RL(min) =

VC1(min) I L(max )

=

6.79 = 17.23 kΩ 0.394

Multivibrators

943

18.4.3 Collector-Catching Diodes When RL the load to the binary is a small resistance, VC1 becomes very small. To ensure that VC1 (when Q1 is OFF) and VC2 (when Q2 is OFF) do not fall below a threshold level, collector-catching diodes are used (Figure 18.12). VCC V < VCC

D1

RC

D2

RC VC2

VC1

R1

R1

ON

Q1 IB2(min)

OFF RL(min)

Q2

R2

R2 IL(max)

I2 −VBB

Figure 18.12 Circuit of Figure 18.11 with collector-catching diodes D1 and D2

In the circuit shown in Figure 18.12, V is smaller than VCC. When Q1 switches OFF, VC1 rises to VCC. At the instant VC1 ≥ V , D1 conducts and connects V to the collector of Q1. VC1 now held at V. As the diodes D1 and D2 hold the voltage at the collector of the OFF transistor at V, these diodes are called collector-catching diodes. Example 18.3 Design a fixed bias binary using Si transistors and having I C(sat ) = 4 mA and hFE (min) = 40. Choose supply voltages of ±9 V. Solution: RC =

VCC − VCE (sat ) I C (sat )

=

9 − 0.2 = 2.2 kΩ 4

From Figure 18.7, I C(sat ) 4 Choose I 2 = = = 0.4 mA 10 10 R2 =

Vσ − ( −VBB ) I2

=

0.7 + 9 = 24.25 kΩ 0.4

Choose R2 = 24 kΩ I B2(min) =

I C(sat ) hFE(min)

=

4 = 0.1 mA 40

For a transistor in saturation I B » I B(min). Therefore, choose I B = 1.5I B(min).

944

Electronic Devices and Circuits

I B2 = 1.5 × 0.1 = 0.15 mA I1 = I 2 + I B2 = 0.4 + 0.15 = 0.55 mA RC + R1 =

VCC − Vs 9 − 0.7 = = 15.1kΩ I1 0.55

Therefore, R1 = (RC + R1 ) − RC = 15.1 − 2.2 = 12.9 kΩ Choose R1 = 12 kΩ. Example 18.4 For the fixed bias binary shown in Figure 18.6, VCC = VBB = 5 V. Si transistors with hFE(min) = 20 are used. If I CBO at 25°C is 10 μA, (i) design the circuit that can function satisfactorily from 25°C to 75°C. Neglect VCE of the ON transistor and VBE of the OFF transistor. (ii) determine the maximum temperature up to which Q1 is OFF, if VBE1 = −0.1V. Solution: (i) I CBO is the leakage current from the collector to base of the OFF transistor and gets doubled for every 10°C rise in temperature. Change in temperature, ∆T = 75 − 25 = 50°C 50

∆T

I CBO(max ) = I CBO 2 10 = 10 × 10 −6 × 2 10 = 10 × 10 −6 × 32 = 0.32 mA The base circuit of the OFF transistor Q1 is as shown in Figure 18.13. I 2 = I CBO(max ) + I1 Therefore, VBB VCE2 = + I CBO(max ) = I CBO(max ) R2 R1 since VBE1 = VCE2 = 0 Hence, R2 =

VBB 5 = = 15.625 kΩ I CBO(max ) 0.32

Choose R2 = 15 kΩ. RC =

VCC − VCE2 5 − 0 = = 1 kΩ I C2 5

I B2 =

I C2 5 = = 0.25 mA hFE(min) 20

Multivibrators VCC = 5V IC2 ICBO(max)

Q1 OFF

RC

R1

VCE2 = 0 I1

VB1

Q2

VBE1 =0 I2

ON Saturation

R2 −VBB = −5V

Figure 18.13 The base circuit of the OFF transistor Q1

The base circuit of the ON transistor Q2 is as shown in Figure 18.14. I B2 = I 3 − I 4 Therefore, 0.25 =

VCC − VB2 VBB 5 − 0 5 5 − = − = − 0.32 RC + R1 R2 1 + R1 15.625 1 + R1 5 = 0.57 1 + R1 5 = 8.77 0.57 R1 = 7.77 kΩ

1 + R1 =

Choose R1 = 7.5 kΩ . VCC = 5V RC

R1 I3

Q1 OFF

IB2 VB2 = 0 I4

Q2 ON

R2

−VBB = −5V

Figure 18.14 The base circuit of the ON transistor Q2

945

946

Electronic Devices and Circuits

(ii)From Figure 18.15, I1 =

VCE2 − VBE1 0.2 − ( −0.1) = = 0.04 mA R1 7.5 VCC = 5V IC2 ICBO(max)

Q1 OFF

7.5

VCE2 = 0.2V I1

VB1

Q2 ON

VBE1 = −0.1V I2

RC

R1

R2 15 −VBB = −5V

Figure 18.15 Circuit to calculate voltage across R2

   I CBO(max ) + I1  R2 = VB1 − ( −VBB ) = − 0.1 + 5 = 4.9 V

I CBO(max ) + I1 =

4.9 = 0.33 mA 15

I CBO(max ) = 0.33 − 0.04 = 0.29 mA ∆T

I CBO(max ) = I CBO 2 10

∆T

2 10 =

I CBO(max ) I CBO

=

0.29 × 10 −3 = 29 10 × 10 −6

∆T = 48.84°C

T2 = ∆T + 25 = 48.84 + 25 = 73.84°C

Multivibrators

947

18.5 RESOLUTION TIME AND MAXIMUM SWITCHING SPEED OF THE BINARY A binary can be triggered by using a dc voltage (dc triggering) or a pulse (pulse triggering). In dc triggering, a small negative dc voltage is momentarily applied at the base of the ON transistor to drive it into the OFF state. In pulse triggering, a negative pulse is applied as trigger at the base of the ON transistor (Figure 18.16). VCC IC1

RC

IC2 R1

C2

VCC

VC2

B2

B1

Q1

RC

R1

Q2

VCE(sat) ON Saturation

OFF R2

R2

0

C −VBB

Trigger

Figure 18.16 Pulse as trigger to binary

Prior to the application of the trigger VC2 = VCE(sat ). However, when trigger is applied at t = 0, Q2 is driven into the OFF state, and hence VC2 abruptly jumps to VCC . A step voltage of magnitude Vi = VCC − VCE(sat ) is developed at the second collector. This change in voltage is coupled to the

(

)

first base through R1 and R2 to drive Q1 ON (Figure 18.17). R1 VB1

VC2 VCC R2

Vi VCE(sat)

Figure 18.17 Voltage change at C2 coupled to B1

The circuit in Figure 18.17 is a resistive attenuator. As the voltage changes at C2, a corresponding change takes place at B1 instantaneously and Q1 can be driven into the ON state almost at the instant the trigger is applied at B2. However, a stray capacitance Ci exists at the input terminals of Q1 (Figure 18.18). The output of the circuit in Figure 18.18 is frequency dependent. R1

VB1 Ci

VCC R2

Vi VCE(sat)

Figure 18.18 Attenuator with Ci at the input of Q1

948

Electronic Devices and Circuits

To calculate the output, reduce the two-loop network into a single-loop network using the Thévenin’s theorem: R2 VTH = Vi = aVi (18.14) R1 + R2 where R2 a= (18.15) R1 + R2 and (18.16)

RTH = R1 || R2 The circuit in Figure 18.18 now can be redrawn as in Figure 18.19. RTH VB1 90%

+ Ci

αVi −

tr

Figure 18.19 Redrawn circuit of Figure 16.18

The circuit in Figure 18.18 is a RC low-pass filter. Its rise time is tr = 2.2RTHCi

(18.17)

If in this circuit, R1 = R2 = 1MΩ and Ci = 20 nF, then tr = 2.2 × 0.5 × 106 × 20 × 10 −9 = 22 ms For the given circuit conditions, it is noted that the rise time of this RC circuit is 22 ms. Assume that Q1 goes into the ON state only when the output of the low-pass circuit reaches 90 percent of its final value. This means that from the instant the trigger is applied to the instant Q1 switches ON, it takes a time delay of 22 ms, which is an abnormally long time delay and is not acceptable if faster switching is required. Hence, it now becomes necessary to switch Q1 ON as quickly as possible after the application of the trigger. To achieve this, condenser C1 is connected in shunt with R1 (Figure 18.20). This is called a perfectly compensated attenuator when C1 = Ci. Its output is independent of frequency. The response of the perfectly compensated attenuator is shown in Figure 18.21. C1

R1

VB1 C1 = Ci R1 = R2

VCC Ci

R2

Vi VCE(sat)

Figure 18.20 Perfectly compensated attenuator

Multivibrators

949

Vi Vo = αVi

t=0

t=∞

Figure 18.21 Response of the perfectly compensated attenuator

The circuit in Figure 18.20 is redrawn as in Figure 18.22. This circuit is in the form of bridge with R1, R2, C1, and C2 (= Ci) comprising the four arms of the bridge. The bridge is said to be balanced when C1R1 = Ci R2 .�When the bridge is balanced, the current in the arm XY is zero. At t = 0 +, the capacitor combination decides the output (Figure 18.23) and as t → ∞, the resistance combination decides the output (Figure 18.24). C1 = Ci

+

R1 = R2

R1

VB1

C1

X

Y

Vi

Ci

R2

−

Figure 18.22 Redrawn circuit of Figure 18.20

C1 VB1

+ Vi

C2

−

Figure 18.23 Circuit at t = 0+

+

R1 VB1

Vi R2

−

Figure 18.24 Circuit at t = ∞

VB1 (t = 0 + ) = Vi and VB1 (t = ∞ ) = Vi

C1 V = i C1 + Ci 2

R1 V = i R1 + R2 2

(18.18)

(18.19)

950

Electronic Devices and Circuits

It is now clear that a compensated attenuator ensures that change in voltage at the second collector can be almost instantaneously transmitted to the first base so that Q1 switches into the ON state in no time. Transition time, tt is the time taken for conduction to be transferred from one device to the other. Initially, Q2 is ON. To transfer conduction from Q2 to Q1 trigger is applied. When an uncompensated attenuator is used, it takes a relatively long time to transfer conduction from Q2 to Q1. However, when a compensated attenuator is used, conduction is transferred in no time from Q2 to Q1. Capacitor C1 in shunt with R1 has reduced the transition time and therefore this capacitor is called speed up capacitor, commutating capacitor or transpose capacitor. Therefore to reduce the transition time in the binary, C1 and C1 are connected in shunt with R1 and R1 (Figure 18.25). Now the trigger can be applied at the collector of Q1 to drive Q2 to OFF state and the trigger signal is coupled to the second base through C1. Now refer to Example 18.1, in the stable state VA = VC1 − VB 2 = 8.044 − 0.7 = 7.344 V and VB = VC2 − VB1 = 0.2 − ( −3.197 ) = 3.397 V VCC

+ VA −

− VB

+

RC

RC C1

0

C1

VC2 VCE(sat)

C

R1

R1 Trigger

VCC

Q1

ON Q2

Saturation

OFF

R2

R2

−VBB

Figure 18.25 Fixed bias binary with commutating condensers

Although C1 and C1 are connected across R1 and R1, to make a distinction between the two let one condenser be called as C1 and the other as C1′ (C1 = C1′ ) . In the stable state, a voltage VA (= 7.344 V) exists across C1 and a different voltage VB (= 3.397 V) exists across C1′ . When trigger is applied, the commutating condensers enable conduction to be transferred from Q2 to Q1 almost instantaneously. But now, since Q2 is OFF and Q1 is ON whatever is the voltage on C1 should change to C1′ and that on C1′ should change to C1. It takes a finite time delay for the voltages across these

951

Multivibrators

condensers to interchange. The time taken for the voltages across the condensers to interchange is called the settling time. To find out the settling time, the recharging time constants associated with C1 and C1′ need to be considered. (i) To calculate the recharging time constant associated with C1, consider the circuit in Figure 18.26. To draw this circuit, short VCC. Then RC appears between the collector of Q1 and ground. The OFF resistance of Q1 is very large when compared to RC and hence is omitted. Further from the other end of R1, C1 network, R2 appears between the base of Q2 and ground. Also between the input terminals of ON Q2, a very small input resistance Ri is present. Q2 base

C1

Q1 collector

R1

RC

R2

Ri

Figure 18.26 Circuit to calculate the recharging time constant associated with C1

R2 || Ri is approximately very small when compared to RC. Hence, the circuit in Figure 18.26 can be redrawn as in Figure 18.27. C1 Q1 collector

Q2 base R1

RC

Figure 18.27 Simplified circuit of Figure 18.26

The effective resistance R = R1 || RC and the time constant of the circuit is (18.20)

t = RC1

(ii) To calculate the recharging time constant associated with C1¢, consider the circuit in Figure 18.28. C1¢ Q1 base R2

C1¢ Q2 collector

R1

RC

Q1 base

Q2 collector R1

R2

Figure 18.28 Circuit to calculate the recharging time constant associated with C1¢

952

Electronic Devices and Circuits

The effective resistance R ′ ≈ R1 || R2 , (since RC « R1 ) and the time constant of the circuit is t ′ = R′C 1′

(18.21)

From Eqs (18.20) and (18.21), t ′ > t . Assuming that the voltages across C1 and C1¢ interchange in a time period 2t , the settling time is tst = 2t ′ = 2R ′C 1′ =

2C ′1 R1R2 R1 + R2

(18.22)

Thus, having applied a trigger to drive the binary from one stable to the other, it is imperative that one should wait for a time interval of (tt + tst ) to once again drive the binary into the initial stable state. This is the minimum time interval allowed between successive trigger pulses and is called the resolution time of the binary, tres. Thus resolution time is defined as the minimum time interval needed between successive trigger pulses to be able to reliably drive the binary from one stable state to the other. Since tt is very small tres = tst =

2C 1′ R1R2 2C R R = 1 1 2 R1 + R2 R1 + R2

(18.23)

The reciprocal of the resolution time is the maximum switching speed of the binary. fmax =

1 tres

=

R1 + R2 2C1R1R2

(18.24)

Example 18.5 For the circuit designed in Example 18.3, find the value of C1 for a maximum switching frequency of 10 kHz. Solution: From Example 18.3, R1 = 12 kΩ and R2 = 24 kΩ fmax =

R1 + R2 2C1R1R2

Therefore, C1 =

18.6

R1 + R2 (12 + 24 )103 = = 6.25 nF 2 fmax R1R2 2 × 10 × 103 × 12 × 103 × 24 × 103

METHODS OF TRIGGERING A BINARY

In pulse triggering, there are basically two methods of triggering a binary. (i) unsymmetric or asymmetric triggering and (ii) symmetric triggering.

18.6.1 Unsymmetric Triggering Unsymmetric triggering is a method of pulse triggering in which one trigger pulse taken from a trigger source is applied at one collector to drive the multi into the second stable state. However, the next trigger pulse taken from a different source is applied at the second collector to drive the multi back into the initial stable state (Figure 18.29).

Multivibrators

953

VCC

D2 0

C1

RC

C1

RC

D4

B

A

C

Trigger pluse 1

0

VCC

D3 C

D1 OFF Q1

R1

R1

ON

ON Q2 OFF

Trigger pluse 2

R2

R2

−VBB

Figure 18.29 Unsymmetric triggering

Let Q1 be OFF and Q2 be ON. To drive Q2 OFF and Q1 ON trigger pulse 1 is applied at node A. As a result D1 is ON and pulse 1 is now applied to the base of Q2 through C1 driving Q2 OFF and consequently Q1 ON. The next trigger pulse 2 is now applied at node B. D3 is now ON and the trigger is connected to the base of Q1 through C1 driving Q1 OFF and Q2 ON. D2 or D4 is OFF when a trigger pulse is present and offers a large reverse resistance to avoid loading the source. When the trigger is removed, D2 or D4 conducts and offers negligible resistance and removes quickly the charge built up on C1 when D2 or D4 is OFF. Consider the voltage changes at the collectors of Q1 and Q2 (Figure 18.30). It is evident from Figure 18.30 that unsymmetric triggering produces a pulse of duration T—the duration of the pulse being dependent on the spacing between the successive trigger pulses. Thus, unsymmetric triggering is used to generate a gated output. Trigger pulse 1 0

Trigger pulse 2 0

VCC VC2

T

0 VCC VC1 0

Figure 18.30 Voltages at the collectors of Q1 and Q2

18.6.2 Symmetric Triggering Symmetric triggering is the method of pulse triggering in which successive trigger pulses taken from the same source and applied at the same point in the circuit will drive the multi from one stable state to the other (Figure 18.31).

954

Electronic Devices and Circuits 0

C Trigger pulse 1

VCC

Trigger pulse 2

D3 RC

RC D1

C1

A

D2

C1 VC2

VC1 OFF

R1

R1

Q1

Q2

ON OFF

ON R2

R2

−VBB

Figure 18.31 Symmetric triggering

Trigger pulse 1 taken from a source is applied at point A that switches D1 ON and connects the negative pulse through C1 to the base of Q2 driving Q2 OFF an Q1 ON. The next trigger pulse 2 also taken from the same source and applied at the same point A will now switch D2 ON and couples this pulse to the base of Q1 driving Q1 OFF and Q2 ON (Figure 18.31). Symmetric triggering is used in counters. It can be noted from Figure 18.32 that for every two trigger pulses, the multivibrator generates one output pulse and hence the name scale of two circuit, meaning that the input frequency is reduced by a factor 2. 0

1

2

3

4

Trigger pulses VCC VC1 0

VCC VC2 0

Figure 18.32 Timing diagram for the binary

5

Multivibrators

955

18.6.3 Nonsaturating Binary We have discussed in Section 18.2 that a transistor driven hard into saturation will have a longer storage time which will limit the switching speed of the binary. To ensure that the switching speed is not limited by the longer storage time of the transistor, where there is a specific need, the ON transistor is held in the active region. Then, the binary is called nonsaturating binary (Figure 18.33). D1 and D2 are ordinary semiconductor diodes and D3 and D4 are Zener diodes with breakdown voltage VZ. When Q1 is OFF and Q2 is ON, D2 and D4 conduct. Consequently, VCB2 = VZ (Figure 18.34). Hence, Q2 is held in the active region. The advantage is that the storage time is small. VCC

RC

RC

R1

R1 D2

D1

Q2 Active ON region

Q1 OFF

D3

D4

R2

R2

−VBB

Figure 18.33 Nonsaturating binary

VCC RC

RC

R1 ON

Q1 OFF

D4 D2

Q2 ON

Active region

VZ VCB2

+

−

Figure 18.34 Circuit to determine VCB2 with Q1 OFF and Q2 ON

956

18.7

Electronic Devices and Circuits

SELF-BIAS BINARY

In a fixed bias binary, two separate dc sources are used to bias the devices, and the currents in the ON devices need not necessarily remain constant. However, in a self-bias binary, one of the sources is done away with and the necessary bias voltage is derived using RE in the emitter leads (Figure 18.35). As there is a substantial emitter resistance, the currents in the devices remain constant. N is the reference terminal with respect to which the voltages in the circuit are measured. Here, again one device is required to be ON and in saturation and the other device is to be in the OFF state. Let it be arbitrarily assumed that Q1 is OFF and Q2 is ON. When Q2 is ON, there exists a sufficient emitter current in RE which produces a voltage drop VEN = VEN2 in it. The voltage at the base of Q1 is VBN1. If VEN2 > VBN1, then Q1 can be OFF as assumed. Let us verify that Q1 is OFF and Q2 is ON and in saturation. (i) To verify that Q2 is ON and is in saturation: To verify whether Q2 is really ON and is in saturation, we write down KVL equations of the base and emitter loops of Q2 and calculate IC2 and IB2 and verify whether IB2 is very much larger than IB2(min) or not. If IB2 > IB2(min), then Q2 is really in saturation as per the assumption made. Having verified this condition, it is now possible to calculate the stable-state voltages in the circuit.

VCC

RC

RC

R1

R1

VCN1

VCN2 VBN2

OFF Q1

+ VBE1

Q2 ON

VBN1

− R2

R2

VEN

RE N

Figure 18.35 Self-bias binary

To calculate the voltage in the base loop of Q2, consider the circuit in Figure 18.36 and obtain the Thévenin voltage and its internal resistance (Figure 18.37). To calculate the voltage in the collector loop of Q2, consider the circuit in Figure 18.38 and obtain the Thévenin voltage and its internal resistance (Figure 18.39).

Multivibrators

957

VCC RC

R1

VTHB

Q1 ON

R2 RE N

Figure 18.36 The base loop of Q2

From figure 18.36 VTHB = VCC ×

R2 and RTHB = R2 ||(R1 + RC ) R1 + R2 + RC

(18.25)

R1 + R2 and RTHC = RC || ( R1 + R2 ) R1 + R2 + RC

(18.26)

From Figure 18.38 VTHC = VCC ×

VCC R1

RC VTHC

RTHB Q2 ON

Q2 ON

Q1

IB2 VTHB

R2

+ VEN2 −

RE

RE

N

N

Figure 18.37 Simplified circuit of Figure 18.36

Figure 18.38 The collector loop of Q2 RTHC

Q2 ON VTHC

+ VEN2 −

RE N

Figure 18.39 Simplified circuit of Figure 18.38

958

Electronic Devices and Circuits

The base and collector loops of Q2 are obtained (Figure 18.40), by combining the circuits in Figure 18.37 and 18.39. VCN2 RTHB

VTHB

IB2

+

VBN2

+ Vs −

RTHC

IC2

Q2 VCE(sat)

VTHC

− IC2

IB2

+ VEN2

RE

−

N

Figure 18.40 The base and collector loops of Q2

From Figure 18.40, the KVL equations of base and emitter loop are VTHB − Vs = I B2 ( RTHB + RE ) + I C 2 RE

VTHC − VCE(sat ) = I B2 RE + I C2 ( RTHC + RE )

(18.27)

(18.28)

Solving Eqs (18.27) and (18.28) I B2 and I C2 are obtained From Figure 18.40, VEN = VEN2 = ( I B2 + I C2 ) RE

(18.29)

Hence, VCN2 = VEN2 + VCE(sat )

(18.30)

VBN2 = VEN2 + Vσ

(18.31)

and

From Figure 18.35, VBN1 = VCN2 ×

R2 R1 + R2

VBE1 = VBN1 − VEN2

(18.32)

(18.33)

If VBE1 is negative then Q1 is OFF. Hence, VCN1 = VCC. But in practice, VCN1 is smaller than VCC because of a small current in RC when Q2 is ON.

Multivibrators

959

Example 18.6 For the self-bias binary shown in Figure 18.35 VCC = 15 V , RC = 3.3 kΩ , R1 = 15 kΩ , R2 = 30 kΩ, and RE = 0.5 kΩ , (i) what is the value of hFE that keeps the Q2 in saturation? (ii) Verify that Q1 is OFF. List the stable-state voltages. Solution: VTHB = VCC ×

R2 30 = 15 × = 9.32 V 15 + 30 + 3.3 R1 + R2 + RC

and RTHB = R2 // ( R1 + RC ) =

VTHC = VCC ×

30 × 18.3 = 11.37 kΩ 48.3

R1 + R2 45 = 15 × = 13.98 V 48.3 R1 + R2 + RC

and

RTHC = RC // ( R1 + R2 ) =

3.3 × 45 = 3.07 kΩ 48.3

From Eqn. 18.27, 11.87 I B2 + 0.5I C2 = 8.62

(18.34)

From Eqn. 18.28, 0.5I B2 + 3.57 I C 2 = 13.78

(18.35)

Solving Eqs (18.34) and (18.35) using Cramer’s rule (given on page 1004):

I B2

8.62 0.5 11.87 8.62 13.78 3.57 0.5 13.78 = and I C2 = 11.87 0.5 11.87 0.5 0.5 3.57 0.5 3.57

I B2 = 0.56 mA (i) hFE =

I C2 = 3.78 mA

I C2 3.78 = = 6.75 I B2 0.56

(ii) VEN2 = ( I B2 + I C2 ) RE = (0.56 + 3.78) 0.5 = 2.17 V VCN2 = VEN2 + VCE (sat ) = 2.17 + 0.2 = 2.37 V VBN2 = VEN2 + Vs = 2.17 + 0.7 = 2.87 V VBN1 = VCN2 ×

R2 30 = 2.37 × = 1.58 V 45 R1 + R2

960

Electronic Devices and Circuits

VCC = 15 V

3.3

RC

RC

I1

VCN1 = 13.78 V

VCN2 = 2.37 V

R1 VBN2 = 2.87 V

30

Q2 ON

OFF Q1 IB2

15 R2

I2

VEN = 2.17 V RE

N

Figure 18.41 Circuit to calculate exact VCN1

VBE1 = VBN1 − VEN2 = 1.58 − 2.17 = −0.59 V As VBE1 is negative, Q1 is OFF. Hence, VC1 should be VCC = 15 V. However, VC1 is not VCC because of I1 in Q1 (Figure 18.41). I1 =

VCC − VBN2 15 − 2.87 = = 0.66 mA 3.3 + 15 RC + R1

VCN1 = VCC − I1RC = 15 − (0.66 ) 3.3 = 12.82 V The stable-state voltages are as follows: VCN1 = 12.82 V, VBN1 = 1.58 V , VEN2 = 2.17 V , VBN2 = 2.87 V , and VCN2 = 2.37 V

Example 18.7 (i) Design a self-bias binary shown in Figure 18.35. Assume VCC = 9 V, VCE(sat) = VBE(sat) = 0, IC(sat) = 5 mA and IB(sat) = 1.5 IB(min), hFE = 40, and VBE(OFF) = 0 V. (ii) Find the value of C1 for fmax = 10 kHz. Solution: (i) From the circuit in Figure 18.35, Q2 is ON and is in saturation and Q1 is OFF. IC2 = 10 mA and IB2 = 1.5 IB2(min). A simple procedure in the design is to make the suitable valid assumptions.

Multivibrators

961

Assume 1 9 VEN = VEN 2 = VCC = = 3 V 3 3 I B2(min) =

(18.36)

I C2 5 = = 0.125 mA hFE 40

I B2 = 1.5I B2(min) = 0.1875 mA

I E2 = I C2 + I B2 = 5 + 0.1875 = 5.1875 mA

RE =

(18.37)

VEN2 3 = = 579 Ω ≈ 0.5 kΩ I E2 5.1875

VBN2 = VEN2 + VBE2(sat ) = 3 + 0 = 3 V VCN2 = VEN2 + VCE(sat ) = 3 + 0 = 3 V Assume I2 in R2 as I2 =

1 5 I C2 = = 0.5 mA 10 10

I1, the current in ( RC + R1 ), when Q1 is OFF and Q2 is ON is I1 = I 2 + I B2 = 0.5 + 0.1875 = 0.6875 mA

RC + R1 =

RC =

VCC − VBN 2 9−3 = = 8.73 k Ω I1 0.6875

VCC − VCE(sat ) − VEN 2 IC

=

(18.38)

9−3 = 1.2 kΩ 5

R1 = (RC + R1 ) − RC = 8.73 − 1 = 7.73 kΩ ≈ 7.5 kΩ

R2 =

(ii) C1 =

VBN2 VEN 2 3 = = = 6 kΩ 0.5 I2 I2

R1 + R2 (6 + 7.5 )103 = = 0.015 µF 2 fmax R1R2 2 × 10 × 103 × 7.5 × 103 × 6 × 103

(18.39)

962

Electronic Devices and Circuits

Example 18.8 For the circuit in Figure 18.42, R1 = R2 = 10 kΩ, RC = 1 kΩ,RE = 500 Ω, VCC = 15 V, and hFE = 40. Find the heaviest load the binary can drive. Solution: VTHB = VCC ×

R2 10 = 15 × = 7.14 V 10 + 10 + 1 R1 + R2 + RC

and RTHB = R2 // ( R1 + RC ) =

VTHC = VCC ×

10 × 11 = 5.23 kΩ 21

R1 + R2 20 = 15 × = 14.29 V 21 R1 + R2 + RC

and RTHC = RC // ( R1 + R2 ) =

1 × 20 = 0.95 kΩ 21

Using Eqns. 18.27 and 18.28, 5.73I B2 + 0.5I C2 = 6.44 0.5I B2 + 1.45I C2 = 14.29 Using Cramer’s rule, I B2

6.44 0.5 5.73 6.44 14.29 1.45 0.5 14.29 = and I C2 = 5.73 0.5 5.73 0.5 0.5 1.45 0.5 1.45

I B2 = 0.27 mA

I C2 = 9.76 mA

VEN2 = ( I B 2 + I C2 ) RE = (0.27 + 9.76 ) 0.5 = 5.01 V VBN2 = VEN2 + Vσ = 5.01 + 0.7 = 5.71 V I B2(min) =

I C2 9.76 = = 0.24 mA hFE 40

I2 =

VBN2 5.71 = = 0.57 mA R2 10

I1(min) = I B2(min) + I 2 = 0.24 + 0.57 = 0.81 mA VCN1(min) = I1(min) R1 + VBN2 = ( 0.81)(10 ) + 5.71 = 13.81 V

I=

VCC − VCN1(min) RC

=

15 − 13.81 = 1.19 mA 1

Multivibrators

963

15 V 1 RC

I

RC

VCN1(min)

R1

10

R1

VCN2 10 I1(min) RL(min)

IB2(min) VBN2

OFF Q1

Q2 ON

VBN1

+ VBE1 −

IL(max)

10

I2

R2

R2

10

VEN

500

RE N

Figure 18.42 Self-bias binary

I L(max ) = I − I1(min) = 1.19 − 0.81 = 0.38 mA

RL(min) =

18.8

VCN1(min) I L(max )

=

13.81 = 36.34 kΩ 0.38

MONOSTABLE MULTIVIBRATORS

It is already known that a mnostable multivibrator has one stable state and one quasistable state. In the stable state, one transistor is ON (say Q2) and the other transistor (Q1) is OFF. A trigger is applied to drive the multi into the quasistable state (i.e. Q1 ON and Q2 OFF) and the multi automatically will return back to the initial stable state after finite time interval, decided by the time constant used in the circuit. For the period for which Q2 is OFF in the quasistable state, a pulse is generated at its collector. Two types of monostable multivibrator circuits can be considered here: (i) collector-coupled monstable multivibrator and (ii) emitter-coupled monostable multivibrator. Only collector-coupled monostable multivibrator is considered here.

18.8.1 Collector-Coupled Monstable Multivibrator The collector-coupled monostable multivibrator circuit is shown in Figure 18.43. In the stable state when Q1 is OFF and Q2 is ON and is in saturation, C charges to VCC through RC of Q1 and a small input resistance of the ON transistor Q2 (Figure 18.44).

964

Electronic Devices and Circuits VCC

I1

RC

IC2

R C

RC

R1 VC2

VC1 VB2

VB1 Q1

Saturation

VC2 ON

OFF t=0

t = tp 0

R2 I2

Ci −VBB

Figure 18.43 Collector-coupled monostable multivibrator

iC RC C C1 Q1 VCC OFF

B2 iC Q2

ON

Ri

Figure 18.44 Charging of C when Q1 is OFF and Q2 is ON

Now to drive the multi into the quasistable state, a negative trigger of duration tp is applied at t = 0 at the base of the ON transistor, Q2 (Figure 18.43). As a result, Q2 switches OFF and because of the cross coupling from the second collector to the first base through R1 and R2, a positive step is connected to the first base thereby driving Q1 ON. Consequently, there is a current I1 in Q1 and the voltage at the first collector falls by I1RC. Since the first collector and the second base are connected through C, whatever is the sudden change in voltage that has taken place at the collector of Q1, an identical voltage change takes place at the base of Q2.

Multivibrators

R

VA C1

+

965

− C

Q1 ON

VCC

VB2

iD

Figure 18.45 Discharge of C when Q1 is ON and Q2 is OFF

As Q1 is now ON and Q2 is OFF, the charge on C discharges through R and the small resistance between the collector and emitter terminals of Q1, and hence the voltage at the base of Q2 changes as a function of time (Figure 18.45). If allowed to discharge, VB2 will try to reach VCC. However, once again when VB2 is Vg , Q2 switches into the ON state and Q1 will switch into the OFF state, thereby ending the quasistable state. The multi now returns to the initial stable state of Q1 OFF and Q2 ON. This situation is presented in Figure 18.46, and it is now possible to calculate the time period for which Q2 is OFF in the quasistable state, which is called the gate width or pulse duration or pulse width of the monostable multivibrator. The voltage variation at the base of Q2 is given as follows: VCC

VB2 VCC

Vσ 0

Vr T

I1RC

τ = RC

Figure 18.46 Voltage variation at the base of Q2 in the quasistable state

966

Electronic Devices and Circuits

−t

VB2 (t ) = Vf − (Vf − Vi ) e t

(18.40)

Vi = Vs − I1RC and Vf = VCC

(18.41)

where t = RC, the time constant. From Figure 18.46,

Substituting these conditions in Eqn. (18.40), −t

VB2 (t ) = VCC − VCC − (Vs − I1RC ) e t

(18.42)

At t = T , VB2 (t ) = Vg ∴ Vg = VCC − VCC − (Vs − I1RC ) e

−T t

(18.43)

From Eqn. (18.43), VCC − Vs + I1RC VCC − Vg

T = t log n

(18.44)

Using Eqn. (18.44) it is possible to calculate the gate width of the monostable multivibrator. However, from Eqn. (18.44) it can be noted that the gate width depends on I1, the current in Q1 in the quasistable state. Only if I1 is stable, the gate width can be stable. But I1 is not necessarily stable because there is no provision in the circuit-like feedback to stabilize I1. Hence, T cannot be stable. Alternately, consider the situation when Q1, in the quasistable state, is driven into saturation. Then (18.45)

I1RC = VCC − VCE(sat ) Substituting Eqn. (18.45) in Eqn. (18.44), T = t log n

= t log n But

(

VCC − Vs + VCC − VCE(sat )

2VCC − Vs + VCE (sat ) VCC − Vg

(V

VCC − Vg

) = t log 2 × n

VCC −

(V

s

+ VCE (sat )

2 VCC − Vg

) (18.46)

) ≈V

(18.47)

T = t log n 2 + t log n 1 = t log n 2 = 0.69RC

(18.48)

s

+ VCE(sat ) 2

g

Substituting Eqn. (18.47) in Eqn. (18.46),

Multivibrators

967

From Eqn. (18.48), it is evident that T can now be stable provided of course that R and C are stable. The gate width now is independent of I1. Therefore, it may be concluded that to make the gate width of the collector-coupled monostable multivibrator stable, it is preferable to drive the ON transistor, in the quasistable state, into saturation. At the same time, the resulting disadvantage is that the storage time becomes longer.

18.8.2 Calculation of Stable-State Currents and Voltages For the circuit in Figure 18.43, to plot waveforms the currents and voltages in the stable state, in the quasistable state, and at the end of the quasistable state need to be calculated. (i) In the stable state, that is prior to the application of the trigger, t < 0. In the stable state, Q1 is OFF and Q2 is in saturation. This is only an assumption made. To justify the assumption, calculate IC2 and IB2 for the given circuit based on the assumption and then verify whether IB2 is much greater than IB2(min) or not. If this condition is satisfied, then it can be said that Q2 is verified to be in saturation. The voltages at the collector and base of Q2 are known. Then it becomes necessary to verify whether Q1 is in the OFF state or not. To establish this, the voltage at the base of Q1 is calculated, and if this voltage is reverse biases, the base-emitter diode of Q1, then Q1 is OFF as assumed. The voltages at the collector and base of Q1 are now known. Example 18.9 For the circuit in Figure 18.43, R = R1 = R2 = 30 kΩ, RC = 3 kΩ, VCC = 15 V, and VBB = 5 V. Si transistors with hFE = 40 are used. Calculate the currents and voltages in the stable state. Solution: To verify that Q2 is in saturation, we need to calculate IC2 and I B2 . To calculate IC2, consider the circuit in Figure 18.47. VCC = 15V 3 30

RC

I2

R1

IC2

I3 Q1

Q2 ON

OFF

30

R2

−VBB = −5V

Figure 18.47 Circuit to calculate IC2

+

VCE(sat) = 0.2V −

968

Electronic Devices and Circuits

From Figure 18.47, I2 =

I3 =

VCC − VCE(sat ) RC

=

15 − 0.2 = 4.93 mA 3

VCE(sat ) − ( −VBB ) R2 + R1

=

5.2 = 0.087 mA 60

I C2 = I 2 − I 3 = 4.93 − 0.087 = 4.843 mA To calculate IB2, consider the circuit in Figure 18.48. VCC = 15V

RC

R= 30

IB2 Q2

Q1

ON

+

OFF

Vσ −

Figure 18.48 Circuit to calculate IB2

I B2 =

VCC − Vs 15 − 0.7 = = 0.477 mA R 30

I B 2(min) =

I C 2 4.843 = = 0.12 mA 40 hFE

Since I B2 > I B2(min), Q2 is in saturation. Hence, VC2 = 0.2 V , VB2 = 0.7 V . To verify that Q1 is OFF, calculate VB1 using the circuit in Figure 18.49.

Multivibrators

969

R1

30 VB1

Q1 OFF

+ Q2 in saturatoin

VBE1 −

VCE(sat) = 0.2V

R2

30

−5V −VBB

Figure 18.49 Circuit to calculate VB1 = VBE1

The voltage VB1 is due to two sources: the VCE(sat) source and the −VBB source. Using the superposition theorem, VB1 = VBE1 = VCE(sat )

= 0.2 ×

 R2 R1  +  −VBB R1 + R2  R1 + R2 

(18.49)

30 30 −5× = 0.1 − 2.5 = −2.4 V 30 + 30 30 + 30

Hence, Q1 is OFF. Therefore, VC1 = VCC = 15 V. The voltage VA across the capacitor C is VA = VC1 − VB2 = 15 − 0.7 = 14.3 V

Therefore, in the stable state VC2 = 0.2 V , VB2 = 0.7 V , VB1 = −2.4 V ,

VC1 = 15 V, and VA = 14.3 V . (ii) In the quasistable state, that is at t = 0 + At t = 0, when trigger is applied, Q2 is driven into the OFF state and Q1 into saturation. Once again, it may be necessary to find out whether Q1 is really in saturation. To make sure that Q1 is in satura-

970

Electronic Devices and Circuits

tion, calculate IC1 and IB1 and verify whether IB1 is much larger than IB1(min) or not. If IB1 >> IB1(min), then Q1 is in saturation. I C1 is calculated using the circuit in Figure 18.50, with the assumption that the voltage VA remains unchanged immediately after the application of the trigger. From Figure 18.50,

I1 =

VCC − VCE(sat )

or

RC

(18.50)

I1RC = VCC − VCE (sat )

(18.51)

I R R = I1RC + VA

Using Eqs (18.50) and (18.51), I1 and IR are calculated. (18.52)

I C1 = I1 + I R

VCC

I1

IR

RC + VA

R

−

VC1 C IC1

Saturation

Q1

Q2

ON

OFF

Figure 18.50 Circuit to calculate IC1

To calculate IB1, consider the circuit in Figure 18.51.

Multivibrators

971

VCC = 15V 3 30 R1

RC

I2

VC2

Q1

IB1

Q2 Vσ

OFF 30

ON

I4

R2

−VBB = −5V

Figure 18.51 Circuit to calculate IB1

From Figure 18.51, I2 =

VCC − Vs RC + R1

(18.53)

I4 =

Vs + VBB R2

(18.54)

and

I B1 = I 2 − I 4

(18.55)

I C1 hFE

(18.56)

I B1(min) = If I B1 > I B1(min), then Q1 is in saturation. From Figures (18.50) and (18.51),

VC 2 = VCC − I 2 RC

(18.57)

VB2 = VCC − I R R

(18.58)

and

972

Electronic Devices and Circuits

Example 18.10 Using the calculations made in Example 18.9, calculate the voltages in the quasistable state. Solution: Using Figure (18.50), I1 =

15 − 0.2 = 4.93 mA 3

or I1RC = 15 − 0.2 = 14.8 V

I R R = 14.8 + 14.3 = 29.1 V Therefore, IR =

29.1 = 0.97 mA 30

I C1 = 4.93 + 0.97 = 5.9 mA From Figure 18.51, I2 =

15 − 0.7 = 0.43 mA 3 + 30

I4 =

0.7 + 5 = 0.19 mA 30

and

I B1 = I 2 − I 4 = 0.43 − 0.19 = 0.24 mA

I B1(min) =

5.9 = 0.15 mA 40

Since I B1 > I B1(min), then Q1 is in saturation. From Figures (18.50) and (18.51), VC2 = 15 − ( 0.43) 3 = 13.71 V and VB2 = 15 − (0.97 ) 30 = −14.1 V (iii) At the end of the quasistable state, that is at t = T + At the end of the quasistable state, once again Q1 is OFF and Q2 is ON. As the transistors suddenly switch from one state to the other, there can be overshoots at the base of Q2 and at the collector

Multivibrators

973

of Q1. To account for the overshoots, the base-spreading resistance, rbb′ is considered (Figure 18.52). ′ ′ But since R » RC , I R « I B2 . Hence, the total current is assumed to be I B2 (Figure 18.53).

R RC B2 C1

C rbb′ I¢B2

VCC

Vσ

Figure 18.52 Circuit at the end of quasistable state

RC V¢B2 B2 C1 V¢C1

C

VCC

rbb′ I¢B2 Vσ

Figure 18.53 Simplified circuit of Figure 18.52

From Figure 18.53, ′ ′ VC1 = VCC − I B2 RC

(18.59)

and ′ VB2′ = I B2 rbb ′ + Vσ

(18.60)

974

Electronic Devices and Circuits

Let the overshoot at the collector Q1 be δ and that at the base of Q2 be δ¢ ′ ′ δ = VC1 − VCE(sat) = VCC − I B2 RC − VCE(sat)

(18.61)

′ δ ′ = VB2′ − Vγ = I B2 rbb ′ + Vσ − Vγ

(18.62)

and

As the first collector and the second base are connected through C, if a change takes place at C1 an identical change takes place at B2. Hence, d = d ′. From Eqs (18.61) and (18.62), ′ ′ VCC − I B2 RC − VCE(sat ) = I B2 rbb ′ + Vσ − Vγ

Therefore, ′ I B2 =

VCC − Vσ + Vγ − VCE(sat ) RC + rbb ′

(18.63)

′ ′ Once I B2 is known VC1 and VB2′ are calculated using Eqs (18.59) and (18.60).

Example 18.11 For the circuit in Example 18.9, calculate the voltages at the end of the quasistable state. Assume rbb′ = 200 Ω. ′ Solution: I B2 =

15 − 0.7 + 0.5 − 0.2 = 4.56 mA 3 + 0.2 ′ ′ VC1 = VCC − I B2 RC = 15 − ( 4.56) 3 = 1.32 V

d = 1.32 − 0.2 = 1.12 V and ′ VB2′ = I B2 rbb ′ + Vσ = ( 4.56 )( 0.2 ) + 0.7 = 1.61 V

δ ′ = 1.61 − 0.5 = 1.11 V

Using the calculations in Examples 18.9, 18.10, and 18.11, the waveforms are plotted in Figure 18.54.

Multivibrators

VB2

975

1.61 V Vσ

δ = 1.11 V Vγ

0 t 14.8 V

τ = RC 13.71 V T

VC2

0

t 0.7 V

VB1

0

t

–2.4 V 15 V VC1 1.32 V

0.2 V 0

t

Figure 18.54 Waveforms of the collector-coupled monostable multivibrator

Example 18.12 Design a collector-coupled monostable multi using Si transistors having hFE = 20. VCC = VBB = 12 V , I C(sat ) = 4 mA, T = 20 ms. Assume VCE(sat ) = Vs = 0. Solution: RC =

VCC − VCE(sat ) I C(sat )

=

VCC 12 = = 3 kΩ I C(sat ) 4 I B2(min) =

IC2 4 = = 0.2 mA hFE 20

I B2 = 1.5I B2(min) = 0.3 mA R=

VCC − Vσ VCC 12 = = = 40 kΩ I B2 I B2 0.3 T = 0.69RC

976

Electronic Devices and Circuits

Or C=

20 × 10 −3 T = = 0.725 mF 0.69R 0.69 × 40 × 103

When Q1 is ON and Q2 is OFF, I 2 in R2 is

I C (sat ) 10

. I2 =

I C(sat ) 10

=

4 = 0.4 mA 10

I B1 + I 2 = 0.3 + 0.4 = 0.7 mA

RC + R1 =

VCC − Vσ 10 = = 14.29 kΩ I B1 + I 2 0.7

R1 = ( RC + R1 ) − RC = 14.29 − 3 = 11.29 kΩ

18.8.3 Voltage-to-Time Converter A collector-coupled monostable multivibrator can be used as a voltage-to-time converter (Figure 18.55). The difference between the circuit in Figure 18.55 and that in Figure 18.43 is that in Figure 18.55, the top end of R is returned to a separate source V but not to VCC as in Figure 18.43, where V < VCC . VCC

V I1

RC

IC2

R

RC

R1

C

VC2

VC1

Q1

VB2

VB1

Q2

Saturation

ON

OFF

t=0 R2

t = tp 0

Ci

−VBB

Figure 18.55 Voltage-to-time converter

Multivibrators

977

The voltage variation at B2 is shown in Figure 18.56.

V

VB2 Vs Vγ

0 t I1RC τ = RC

Figure 18.56 Voltage variation at B2

-t

VB2 (t ) = Vf − (Vf − Vi ) e τ

(18.64)

where t = RC, the time constant. From Figure 18.56, Vi = Vs − I1RC = Vs − VCC + VCE(sat ) ≈ −VCC and Vf = V −t

(

)

VB2 (t ) = V − V − ( −VCC ) e τ At t = T , VB2 (t ) = Vg ≈ 0. Therefore,

0 = V − [V + VCC ] e T

eτ =

−T τ

(18.65)

V V + VCC = 1 + CC V V

Therefore,  V  T = t log n 1 + CC   V  By changing V, T can be varied. Hence, this circuit is called the voltage-to-time converter.

(18.66)

978

18.9

Electronic Devices and Circuits

ASTABLE MULTIVIBRATOR

An astable mutivibrator is a square wave oscillator, which is usually used as a clock in digital circuits. The circuit of the collector-coupled astable multivibrator is shown in Figure 18.57. VCC

R1

RC

R2

C1

RC C2 VC2

VC1

Q1

VB2

VB1

Q2

Saturation

ON

OFF

Figure 18.57 Collector-coupled astable multivibrator

In Figure 18.57 if R1 = R2 = R and C1 = C2 = C , then the circuit is called a symmetric astable multivibrator; otherwise, it is called an unsymmetric astable multivibrator. To explain the working of the circuit, let it be arbitrarily assumed that at this instant of time that Q1 is OFF and Q2 is ON and in saturation. Since the circuit is an oscillator, prior to this instant Q1 must have been in the ON state and Q2 must have been in the OFF state. When Q1 was ON, C2 must have been charged to VCC through RC of Q2 and the small input resistance of Q1. When suddenly Q2 switches ON, the voltage at its collector is approximately zero and hence a large negative voltage is coupled to the base of Q1 driving Q1 into the OFF state (Figure 18.58). VCC

I2

R2

RC

C2

− VCC

Q1 OFF

+ Q2

Saturation ON

Figure 18.58 When Q2 is suddenly switched ON the voltage on C2 drives Q1 OFF

Multivibrators

979

However, Q1 does not remain in the OFF state forever, since VB1, the voltage at the base of Q1 changes as a function of time as the charge on C2 discharges through R2 and a negligible resistance between the collector and emitter terminals of Q2 (Figure 18.59). Once again when VB1 = Vg , Q1 switches into the ON state. When Q1 is OFF and Q2 is ON, C1 charges to VCC and when Q1 switches ON a large negative voltage is now coupled to the base of Q2 driving Q2 OFF. This process is repeated.

R2 C2 VB1

+

− VCC

Q2

VCC

Saturation

ON

iD

Figure 18.59 Discharge of C2 through R2

18.9.1 Calculation of the Time Period T 2 for Which Q 2 is OFF The voltage variation at the base of Q1 is shown in Figure 18.60.

VCC

VB1

T1

0

I2RC t2 = R2C2

Figure 18.60 Voltage variation at the base of Q1

980

Electronic Devices and Circuits

VB1 (t ) = Vf − (Vf − Vi ) e

−t t2

(18.67)

Vf = VCC and

(

)

Vi = Vs − I 2 RC = Vs − VCC − VCE(sat ) = Vs − VCC + VCE(sat ) Substituting the values of Vf and Vi in Eqn. (18.67), we obtain

(

)

VB1 (t ) = VCC − VCC − Vs + VCC − VCE(sat ) e

−t t2

(18.68)

At t = T1, VB1 (t ) = Vg

(

)

(

)  e

−T1

∴ 2VCC − Vs + VCE (sat )  e t = VCC − Vg    Vs + VCE(sat ) 2 VCC −  2 

2

−T1 t2

= VCC − Vg

 

(18.69)

But,

(V

s

+ VCE(sat ) 2

) ≈V

g

∴ T1 = t 2 log n 2 = 0.69t 2

(18.70)

T2 = t 1 log n 2 = 0.69t 1

(18.71)

∴ T = T1 + T2

(18.72)

Similarly,

And f the frequency of oscillations is f =

1 T

(18.73)

The waveforms of the collector-coupled astable multivibrator are given in Figure 18.61.

Multivibrators

VB1

981

V� 0

t

I2RC τ2 = R2C2

VCC

VC1

T1

VCE(sat) 0

VB2

t

V� 0

t

I1RC τ1 = R1C1

VCC VC2

T2

VC2(sat) 0

Figure 18.61 Waveforms of the collector-coupled astable multivibrator

From Figure 18.61, it can be noted that when a transistor switches OFF, the voltage at its collector does not abruptly rise to VCC, but rounding off of the rising edges is seen. This is because when Q1 switches into the OFF state, Q2 switches into the ON state, and there is a small charging current of C1which will not allow the voltage at the collector of Q1 to jump to VCC (Figure 18.62). It takes a finite time delay when this voltage reaches VCC. This time delay is called the recovery time.

982

Electronic Devices and Circuits

VCC

RC

C1

iC

VC1 VB2

VB1

Q1

Q2

Saturation

ON

OFF

Figure 18.62 C1 charges when Q1 is OFF and Q2 is ON

18.9.2 Condition for the ON Transistor to be in Saturation Consider the circuit in Figure 18.63. VCC

IC2 RC

R1 IB2

+ Q2 +

ON Vs

VCE(sat) −

−

Figure 18.63 Conditions in the circuit when the ON transistor is in saturation

Writing the KVL equations of the base and the collector loops, VCC = I B2 R1 + Vs

(18.74)

Multivibrators

983

and (18.75)

VCC = I C2 RC + VCE(sat ) From Eqs (18.74) and (18.75), I B2 R1 + Vs = I C2 RC + VCE(sat ) But Vs ≈ VCE(sat ) Therefore, I B2 R1 = I C2 RC or R1 =

I C2 RC I B2

Therefore, for the ON transistor to be in saturation, R1 ≤

I C2 RC I B2

or

(18.76)

R1 ≤ hFE RC

18.9.3 Recovery Time of Symmetric Astable Multivibrator When Q1 is switched OFF, the variation of VC1 is shown in Figure 18.64. VCC

90% VC1

10% VCE(sat)

trec

Figure 18.64 Recovery time of astable multivibrator

The time taken for VC1 to reach 90 percent VCC is approximately the rise of the RC circuit comprising RC and C1 (Figure 18.64).

984

Electronic Devices and Circuits

trec ≈ tr = 2.2RCC1

(18.77)

For a symmetric astable multi, R1 = R2 = R and C1 = C2 = C , T = 0.69 RC 2

(18.78)

From Eqs (18.77) and (18.78),

From Eqn. (18.76),

trec 2.2RCC 3.2RC = = T 0.69RC R 2 R = hFE RC

(18.79)

(18.80)

Substituting Eqn. (18.80) in Eqn. (18.79), trec 3.2 = (18.81) T hFE 2 From Eqn. (18.81), it can be noted that the recovery time depends on hFE. If hFE = 32, then trec =

3.2 T T × × 100% = 10% of 32 2 2

(18.82)

T T , and hFE = 64, trec = 5% of 2 2 The larger the value of hFE, the smaller the recovery time. Alternately, hFE = 16, trec = 20% of

Example 18.13 For an unsymmetric astable multivibrator, R1 = 60 kΩ, R2 = 40 kΩ, and RC = 4 kΩ. Calculate the value of C needed to oscillate at 10 kHz. Solution: Let C1 = C2 = C T1 = 0.69R2C and T2 = 0.69R1C Therefore, T = T1 + T2 = 0.69C ( R1 + R2 ) = 0.69C (60 + 40 ) × 103 = 0.69C × 105 Given that f =10 kHz. Therefore, T=

1 1 = = 0.1 × 10 −3 s f 10 × 103 0.1 × 10 −3 = 0.69C × 105

C=

0.1 × 10 −3 = 1.45 nF 0.69 × 105

Multivibrators

985

Example 18.14 Calculate the frequency of oscillations of a symmetric astable multivibrator given that R = 10 kΩ and C = 10 nF. Solution: T = T + T = (0.69RC + 0.69RC ) = 1.4RC 2 2 f =

1 0.7 0.7 7 kHz = = 1.4RC RC 10 × 103 × 10 × 10 −9

Example 18.15 Design a symmetric astable multivibrator using Si NPN transistors having hFE = 20 to oscillate at 10 kHz . Assume VCC = 10 V and I C (sat ) = 5 mA . VCC − VCE(sat ) 10 − 0.2 Solution: RC = = = 1.96 kΩ I C(sat ) 5 Choose RC = 2 kΩ I B2(min) =

I C(sat ) hFE

=

5 = 0.25 mA 20

Choose I B2 = 1.5I B2(min) = 1.5 × 0.25 = 0.375 mA . R=

VCC − Vs 10 − 0.7 = = 24.8 kΩ I B2 0.375

Choose R = 25 kΩ For a symmetric as table, T = 1.4RC Therefore, C=

T 1.4R

Given that f = 10 kHz. Therefore, T=

1 = 0.1 ms 10 × 103

Therefore, C=

0.1 × 10 −3 = 2.86 nF 1.4 × 25 × 103

Example 18.16 Design an unsymmetric astable multivibrator using Si NPN transistors having hFE = 30, to oscillate at 5 kHz and a duty cycle of 40 percent. Assume VCC = 9 V and I C(sat ) = 5 mA . VCC − VCE(sat ) 9 − 0.2 Solution: RC = = = 1.76 kΩ I C(sat ) 5 Choose RC = 2 kΩ T=

1 1 = = 0.2 ms f 5 × 103

986

Electronic Devices and Circuits

Duty cycle =

T1 T = 1 = 0.4. Therefore, T1 + T2 T T1 = 0.4T = 0.4 × 0.2 = 0.08 ms

Hence, T2 = T − T1 = 0.2 − 0.08 = 0.12 ms Choose C1 = C2 = C = 0.01 mF T1 = 0.08 ms = 0.69R2C

R2 =

0.08 × 10 −3 = 11.59 kΩ 0.69 × 0.01 × 10 −6

R1 =

0.12 × 10 −3 = 17.39 kΩ 0.69 × 0.01 × 10 −6

Choose R2 = 12 kΩ T2 = 0.12 ms = 0.69R1C

Choose R1 = 18 KΩ For the ON transistor to be in saturation, the condition that must be satisfied is R ≤ hFE RC

R ≤ 30 × 2 = 60 kΩ

As both R1 and R2 are less than 60 kΩ, they are acceptable.

18.9.4 Voltage-to-Frequency Converter If the frequency of oscillations of the astable multivibrator is to be changed the circuit components R or C need to be changed. Alternately, by simply changing a supply voltage, it is possible to change the frequency of oscillations. Such a circuit is called the voltage-to-frequency converter (VFC) or voltage-controlled oscillator (VCO) (see Figure 18.65). VCC V

RC

R

RC

R C

C

VC2

VC1

Q1 OFF

VB1

VB2

Q2

Saturation

ON

Figure 18.65 Voltage-controlled oscillator

Multivibrators

987

The voltage variation at B2, the base of Q2 is shown in Figure 18.66.

T/2

V

VB2 Vs Vγ

0 t

I1RC τ = RC

Figure 18.66 Voltage variation at B2 −t

VB2 (t ) = Vf − (Vf − Vi ) e t

(18.83)

where t = RC, the time constant. From Figure 18.66, Vi = Vs − I1RC = Vs − VCC + VCE(sat ) ≈ −VCC and Vf = V −t

(

)

VB2 (t ) = V − V − ( −VCC ) e t At t =

T , VB2 (t ) = Vg ≈ 0. Therefore, 2 0 = V − [V + VCC ] e T

e 2t =

−T 2 t

V + VCC V = 1 + CC V V

Therefore,  V  T = 2t log n 1 + CC  (18.84)  V  By changing V, T can be varied and hence the frequency. Therefore, this circuit is called the voltage-to-frequency converter.

18.9.5 Astable Multivibrator with Vertical Edges for the Collector Waveforms In Figure 18.61, it can be noted that the voltage variations at the collectors when transistors switch into the OFF state are not abrupt, because of a small charging current of a condenser through the collector resistance of the OFF transistor. If an alternate path is provided for the charging current

988

Electronic Devices and Circuits

the voltage at the collector of the OFF transistor can abruptly switch to VCC. The circuit in Figure 18.67 helps in deriving the collector voltages having vertical edges. When Q1 switches OFF, D1 is OFF and VC1 rises to VCC. The charging current to C is now provided through R1. VCC

R1 RC

R

R

R1

RC

D1

D2

VC1

VC2 C

C

Q1

Q2

VB1

Saturation

ON

OFF

Figure 18.67 Astable multivibrator with vertical edges for collector waveforms

18.10

SCHMITT TRIGGER

The circuit of the Schmitt trigger, also called an emitter-coupled binary, is shown in Figure 18.68. VCC

RC1

RC2

R1

IC2

VCN1 Rs

VBN2

Q2

+

+

+ Vs

−

Vi

−

R2

Vg

+ Q2 VO =VCN2

− IE2

RE

+ VEN2 − N

Figure 18.68 Schmitt trigger

−

Multivibrators

989

From Figure 18.68, it can be noted that there is no cross coupling from the second collector to the first base as in the case of self-bias binary. Here again, when one transistor is ON, the other transistor is OFF. If the external signal Vs is not applied, Q1 is OFF and hence VCN1 = VCC , which is coupled to the base of Q2 through R1 and R2, thereby driving Q2 into the active region. As a result, VCN2 = VCC − I C2 RC2 and VEN = VEN2 = I E2 RE. If the input signal is now applied and if Vi ≥ VEN2, Q1 is ON. If the loop gain is less than 1 when Vi increases, VO also increases linearly. When Vi is increased further VO reaches VCC . The transfer characteristic for this condition is shown in Figure 18.69. Q1 ON

VO

Q2 ON

Q1 ON

Q2 OFF VCC

VCC-IC2RC2

Q1 OFF

Q2 ON

0 Vi

Figure 18.69 Transfer characteristic when the loop gain is less than 1

The loop gain can be increased by increasing the collector resistances. If now the loop gain is 1, the transfer characteristic is as shown in Figure 18.70. Q1 ON Q2 ON

VO

Q1 ON

VCC

Q2 OFF VCC-IC2RC2

0

Vi

Figure 18.70 Transfer characteristic when the loop gain is 1

If the loop gain is greater than 1, then Schmitt exhibits hysteresis (Figure 18.71).

990

Electronic Devices and Circuits VO VCC

VCC-IC2RC2

0

V2

V1

Vi

LTP

UTP Range of hystersis

Figure 18.71 Transfer characteristic when the loop gain is greater than 1

From Figure 18.71, it can be noted that when the loop gain is greater than 1, then Schmitt trigger exhibits hysteresis, which is a requirement in certain applications. (V1 − V2 ) is called the range of hysteresis, VH. Calculation of V1, the upper trip point (UTP): V1 is the input voltage at which Q2 switches OFF. Till this voltage is reached Q2 is ON and Q1 is OFF. Thevenizing the circuit in Figure 18.68, to draw the base and collector loops of the ON transistor Q2, we have V ′ = VCC × and

R2 R1 + R2 + RC1

R ′ = R2 // (RC1 + R1 )

(18.85)

The circuit in Figure 18.68 can be redrawn as in Figure 18.72. The effective voltage in the base-emitter loop is (V ′ − VBE2 ), and this voltage appears across R´ and (1+ hFE ) RE (since I B2 is the current in R´ and (1+ hFE ) I B2 is the current in RE ). Therefore, as far as I B2 is concerned RE is seen to have increased by a factor (1+ hFE ) . Let RE′ = (1 + hFE ) RE . VEN = VEN2 is calculated using the circuit in Figure 18.73. VEN = VEN2 = (V ′ − VBE2 ) × since (1+ hFE ) RE »R ′.

(1 + hFE ) RE ≈ V ′ −V BE2 (1 + hFE ) RE + R′

(18.86)

Multivibrators

991

VCC

VCC RC2

IC2

RC1 VCN1

R′

Q1

+ +

Q2

Vγ 1

−

−

V1

−

+ VBE2

IB2 V′

+ IE2

RE

VEN2

− N

Figure 18.72 Circuit to calculate VEN2 R′

+

(1+hFE) RE

IB

+ V ′ – VBE2

VEN2

–

N

Figure 18.73 Simplified circuit to calculate VEN2

From Figure 18.72, V1 ( UTP ) = VEN2 + Vg 1

(18.87)

V1 (UTP ) = V ′ − VBE2 + Vg 1 = V ′ − 0.1

(18.88)

Using Eqn. (18.86),

since for both Ge and Si −VBE2 + Vg 1 = −0.1 Therefore, V1 ( UTP ) is practically V ¢.

992

Electronic Devices and Circuits

Example 18.17 Si transistors having hFE = 50 are used in the Schmitt trigger circuit shown in Figure 18.68. VCC = 15 V, RC1 = 2 kΩ, RC2 = 1 kΩ, R1 = 2 kΩ, R2 = 6 kΩ, and RE = 3 kΩ. Calculate the exact and approximate values of UTP. Solution: Exact value: V ′ = VCC ×

R2 6 = 15 × =9V 2+6+2 R1 + R2 + RC1

R ′ = R2 // ( RC1 + R1 ) = VEN2 = (V ′ − VBE2 ) ×

6×4 = 2.4 kΩ 10

(1 + hFE ) RE = 8.4 × (51) 3 = 8.227 V (51) 3 + 2.4 (1 + hFE ) RE + R′

V1 = VEN2 + Vg 1 = 8.27 + 0.5 = 8.77 V Approximate value: V1 = V ′ − 0.1 = 9 − 0.1 = 8.9 V Calculation of V2, Lower trip point (LTP): Once the input voltage is V1, Q2 is OFF and Q1 is ON. With further increase in the input voltage beyond V1, the output of the Schmitt trigger remains at VCC only. To bring the Schmitt trigger to the other state, that is Q1 OFF and Q2 ON, the input needs to be decreased. Suddenly, when the input is V2, the output falls to a smaller value. This voltage V2 is the LTP. Till such time that the input is V2, Q2 is OFF and Q1 is ON (Figure 18.74). When Vi = V2, the voltage at the base of Q2 is VEN1 + Vg 2 and Q2 switches into the ON state. From Figure 18.68, thevenizing the circuit at the collector of Q1,

(

)

VTH = VCC

(R1 + R2 ) RC1 + R1 + R2

(18.89)

and RTH = ( R1 + R2 ) // RC1 =

(R1 + R2 ) RC1 RC1 + R1 + R2

(18.90)

VCN1 is the voltage at the collector of Q1, and this is coupled to the base of Q2 through R1 and R2 . Therefore, the voltage at the base of Q2 is VBN2 = VCN1 ×

R2 = aVCN1 R1 + R2

(18.91)

Using Eqs (18.89), (18.90), and (18.91), the circuit in Figure 18.68 is drawn as shown in Figure 18.74.

Multivibrators

993

VCC VTH RC2

IC1

RTH

VCN1

Q2

Q2

ON

+

+

VBE1

+ V2

−

+

OFF

Vγ 2 αVCN1

−

− + IC1 + IB1

RE

VEN1

−

−

N

Figure 18.74 Circuit to calculate V2

From Figure 18.74,  I  VEN = VEN1 = ( I C1 + I B1 ) RE = I C1 1 + B1  RE  I C1   1  = I C1 1 + RE = I C1RE′  hFE 

(18.92)

 1  RE RE′ = 1 +  hFE 

(18.93)

VCN1 = VTH − I C1RTH

(18.94)

aVCN1 = VEN1 + Vg 2

(18.95)

where

Substituting Eqn. (18.94) in Eqn. (18.95), a (VTH − I C1RTH ) = VEN1 + Vg 2

(18.96)

Substituting Eqn. (18.92) in Eqn. (18.96), a (VTH − I C1RTH ) = I C1RE′ + Vg 2

(18.97)

994

Electronic Devices and Circuits

Therefore, I C1 = But aVTH =

aVTH − Vg 2

(18.98)

aRTH + RE′

(R1 + R2 ) = V × R2 R2 =V′ × VCC CC R1 + R2 RC1 + R1 + R2 RC1 + R1 + R2

Therefore, I C1 =

V ′ − Vg 2 aRTH + RE′

(18.99)

V2 = VBE1 + VEN1 = VBE1 + I C1RE′

(18.100)

V2 = VBE1 +

(V ′ − Vg 2 )RE′ aRTH + RE′

(18.101)

Example 18.18 For the circuit considered in Example 18.17, calculate V2. Solution: From Example 18.17, V ′ = 9 V.  1  1  RE = 1 +  3 = 3.02 kΩ RE′ = 1 +  50   hFE 

a=

RTH =

R2 6 = = 0.75 R1 + R2 2 + 6

(R1 + R2 ) RC1 = (2 + 6) 2 = 1.6 kΩ

RC1 + R1 + R2

10

aRTH = 0.75 × 1.6 = 1.2 kΩ

V2 = VBE1 +

(V ′ − Vg 2 )RE′ aRTH + RE′

= 0.6 +

(9 − 0.5) (3.02 ) = 6.68 V 1.2 + 3.02

Example 18.19 Design a Schmitt trigger to have UTP = 8 V and LTP = 4 V. Choose NPN Si transistors having hFE = 40, VCC = 18 V, and I C (sat ) = 5 mA . Assume that the ON transistor is in saturation. Solution: Consider the Schmitt trigger circuit in Figure 18.75.

Multivibrators

VCC

RC1

IC2

RC2

R1

+ VBN2 I1

Q1

+

R2

OFF

Vγ

+

I2

−

IB2 + VBE2 −

Q2

VCE2

ON

−

V1

+ −

IE1

RE

VEN

− N

Figure 18.75 Schmitt trigger

Q1 OFF and Q2 ON: Choose I 2 =

IC 5 = = 0.5 mA 10 10 V1 = VEN + Vg ∴VEN = V1 − Vg = 8 − 0.5 = 7.5 V RE =

VEN 7.5 = = 1.5 kΩ I C2 5

Assume Q2 is in saturation. VCE(sat ) = 0.2 V RC2 =

VCC − VCE2 − VEN 18 − 0.2 − 7.5 10.3 = = = 2.06 kΩ I C2 5 5 VBN2 = VBN1 = 8 V R2 =

VBN2 8.0 = = 16 kΩ I2 0.5

I B2(min) =

I C2 5 = = 0.125 mA hFE 40

995

996

Electronic Devices and Circuits

I B2 = 1.5 × 0.125 = 0.1875 mA I1 = I B2 + I 2 = 0.1875 + 0.5 = 0.6875 mA RC1 + R1 =

VCC − VBN2 18 − 8.0 = = 14.55 kΩ 0.6875 I1 R1 = 14.55 − RC1

Consider the circuit in Figure 18.76 when Q1 is ON and is in saturation and Q2 is OFF. VCC

RC1 IC1 Q1

VBN1

+

+ Vs

I1 VBN2

R1

Q2 R2

−

V2 IE1 RE

−

+ VEN1 −

+ V2

−

N

Figure 18.76 Circuit when Q1 is ON and Q2 is OFF

At VBN1 = V2, VBN2 = V2 . Since Q2 is OFF, the entire I1 flows through R1. I1 =

V −V V2 4 4 − 0.7 = = 0.25 mA and I C1 = BN1 s = = 2.2 mA RE 1.5 R2 16

VCC = ( I C1 + I1 ) RC1 + I1 ( R1 + R2 ) = ( I C1 + I1 ) RC1 + I1 (14.55 − RC1 + R2 ) VCC = I C1RC1 + I1 (14.55 + R2 ) I1 (14.55 + R2 ) = 0.25 (14.55 + 16 ) = 7.64 V

RC1 =

18 − 7.64 = 4.71 kΩ 2.2

R1 = 14.55 − 4.71 = 9.84 kΩ

Multivibrators

997

18.10.1 Elimination of Hysteresis in Schmitt Trigger In some applications, hysteresis in a Schmitt trigger is provided (squaring circuit); whereas in comparators, hysteresis needs to be eliminated. Eliminating hysteresis means making V1 = V2 . To ensure that V2 = V1, resistance Re1 is added in series with emitter of Q1 so that the drop across it will increase V2 to V1 (Figure 18.77). VCC

RC1 VCN1

IC2

Q2

Q1 ON

+ Vγ

+

RC2

R1

Re1

OFF

R2

−

V2

−

+ VEN1 −

RE

(IB1 + IC1)hFE

N

Figure 18.77 Elimination of hysteresis by increasing V2 to V1

Re1 is chosen such that VH = ( I B1 + I C1 ) Re1

(18.102)

To ensure that V1 = V2 , resistance Re2 is added in series with emitter of Q2, so that the drop across it will decrease V1 to V2 (Figure 18.78). Re2 is chosen such that VH = ( I B2 + I C2 ) Re2

(18.103)

VCC

RC1

Q2

Q1 OFF Re2

+ Vi

−

VEN2

+ −

RE

IC2

RC2

R1

R2

ON

(IB2 + IC2)Re2

N

Figure 18.78 Elimination of hysteresis by decreasing V1 to V2

998

Electronic Devices and Circuits

18.10.2 Applications of Schmitt Trigger (i) Schmitt trigger can be used as a squaring circuit, that is, any arbitrarily time-varying signal can be converted into a square wave output, provided of course that the input signal amplitude is above V1 and below V2 (Figure 18.79). Vi V1 V2 t

0 VCC VCC−IC2RC2

t

0

Figure 18.79 Schmitt trigger as a squaring circuit

(ii) The Schmitt trigger can be used as a binary. To use a Schmitt trigger as a binary Q1 is V biased at V = H . If the output is LOW, to drive it into the HIGH level, apply a positive 2 trigger whose amplitude is more positive than (V1 − V ). If the output is HIGH, to drive it into a LOW level, apply a negative trigger whose amplitude is more negative than (V − V2 ). (iii) The Schmitt can be used as an amplitude comparator. In a Schmitt trigger in which hysteresis is eliminated, the moment the input reaches the trip point (the reference level), the amplitude of the signal at the output changes from LOW level to HIGH, indicating that the input has reached the predetermined voltage level.

Additional Solved Examples Example 18.20 Design a collector-coupled monostable multivibrator shown in Figure 18.43, to derive an output pulse of 100 µs. Silicon transistors with hFE (min) = 25 and having rbb′ = 0.2 kΩ are used and the supply voltages are ±10 V. Also, calculate the overshoot. Assume I C(sat ) = 5 mA . VCC − VCE(sat ) V 10 Solution: RC = = CC = = 2 kΩ 5 I C(sat ) I C(sat ) I B2(min) =

I C2 5 = = 0.2 mA hFE 25

I B2 = 1.5I B2(min) = 0.3 mA

R=

VCC − Vσ VCC 10 = = = 33 kΩ I B2 I B2 0.3

Multivibrators

T = 0.69RC

or

C=

I2 ≈

999

T 100 × 10 −6 = = 4.39 nF 0.69R 0.69 × 33 × 103

1 I = 0.5 mA 10 C(sat )

When Q1 is ON and Q2 is OFF, R2 =

V s −( −VBB ) 10 = = 20 kΩ 0.5 I2

I B1 + I 2 = 0.3 + 0.5 = 0.8 mA RC + R1 =

VCC − VO 10 = = 12.5 kΩ I B1 + I 2 0.8

R1 = ( RC + R1 ) − RC = 12.5 − 2 = 10.5 kΩ From Eqn. (18.63), ′ I B2 =

VCC − Vs + Vg − VCE (sat ) RC + rbb ′

=

10 − 0.7 + 0.5 − 0.2 9.6 = = 4.36 mA 2 + 0.2 2.2

VB′2 = I B′2 rbb ′ + Vs = ( 4.36 )( 0.2 ) + 0.7 = 1.57 V

d ′ = 1.57 − 0.5 = 1.07 V

Example 18.21 For the astable multivibrator shown in Figure 18.67, assume Q2 is in saturation and justify your assumption with appropriate calculations. Neglect junction voltages. Assume R = 30 kΩ, R1 = 2 kΩ, RC = 2 kΩ, hFE = 50, and VCC = 15 V. Solution: When Q2 is in saturation, D2 is ON and the collector load for Q2 from Figure 18.80 is RL = RC || R1 = 2 || 2 = 1 kΩ

I C2 =

VCC − VCE(sat ) RL

VCC R1

R

RC ON D2

+ Vs

IC2 Q2 + ON VCE(sat)

− −

Figure 18.80 Circuit when D2 is ON

=

15 = 15 mA 1

1000

Electronic Devices and Circuits

I B2 =

VCC − Vs 15 = = 0.5 mA R 30

I B2(min) =

I C 2 15 = = 0.3 mA hFE 50

IB2 needed to keep Q2 in saturation is 1.5I B2(min) = 1.5 × 0.3 = 0.45 mA As the actual I B2 = 0.5 mA , then Q2 is indeed in saturation, as assumed. Example 18.22 For the circuit in Example 18.21, if C = 0.1 µF , determine its frequency. T = 1.4RC = 1.4 × 30 × 103 × 0.1 × 10 −6 = 4.2 ms

f =

1 1000 = = 238.1Hz T 4.2

Summary • Multivibrators are regenerative switching circuits and are classified as (i) bistable, (ii) monostable, and (iii) astable circuits. • A bistable multivibrator has two stable states and only on the application of a trigger the multi switches from one stable state to the other. It is used as a one-bit memory element in digital circuits. • There are two methods of triggering a binary: (i) symmetric triggering and (ii) unsymmetric triggering. • Transition time is the time taken for conduction to be transferred from one device to the other, and this time interval can be drastically reduced by using commutating condensers. Settling time is the time required for the voltages on commutating condensers to interchange. • The minimum time interval required between the successive trigger pulses to be able to reliably drive the multi from one stable state to the other is called the resolution time and the reciprocal of it is the maximum switching speed of the binary. • A Schmitt trigger is an emitter-coupled binary. This circuit can be used for many applications, such as as a binary, squaring circuit, comparator, etc. • A monostable multivibrator, also called as one-shot multi, has one stable state and one quasistable state. An external signal is required to be applied to drive the multi into the quasistable state. This circuit is used to generate a pulse of finite time duration known as the gate width, pulse width, or pulse duration. • A monostable multivibrator can be used as a voltage-to-time converter. • An astable multivibrator, also called a free-running multi, has two quasistable states. This circuit is used to generate either a symmetric or unsymmetric square wave of desired frequency. • An astable multivibrator can be used as a voltage-controlled oscillator(VCO)

Multivibrators

1001

multiple ChoiCe QueStionS 1. In an ideal transistor switch, (a) RON = 0 and ROFF = ∞ (c) RON = ∞ and ROFF = 0

(b) RON = 0 and ROFF = 0 (d) RON = ∞ and ROFF = ∞

2. Turn-on time of a transistor is (a) delay time plus rise time (c) delay time plus storage time

(b) delay time plus switching time (d) storage time plus fall time

3. Turn-off time of a transistor is (a) delay time plus rise time (c) delay time plus storage time

(b) delay time plus switching time (d) storage time plus fall time

4. To ensure that that the voltage at the collector of the OFF transistors does not fall below a threshold level, when the load resistance becomes small, the collectors of the transistors are connected to an auxiliary source through diodes. The diodes in this case are called (a) power diodes (b) switching diodes (c) collector catching diodes (d) signal diodes 5. Commutating condensers C1 and C1 are connected in shunt with the cross coupling resistors R1 and R1 in a bistable multivibrator to (a) to convert an uncompensated attenuator into a compensated attenuator (b) to reduce the storage time (c) to reduce the fall time (d) to switch the transistors into the OFF state simultaneously 6. In a binary, the time taken for conduction to be transferred from one device to the other, on the application of a trigger, is called (a) rise time (b) fall time (c) transition time (d) recovery time 7. Once conduction is transferred from one device to the other, on the application of a trigger, it takes a finite time delay for the voltages across the commutating condensers to interchange. This time delay is called the (a) settling time (b) reverse recovery time (c) storage time (d) delay time 8. The minimum time interval allowed between successive trigger pulses to be reliably able to drive the binary from one stable state to the other is called the (a) settling time (b) transition time (c) storage time (d) resolution time 9. The method of triggering a binary, in which successive trigger pulses taken from the same source and applied at the same point in the circuit will cause a change of state of the devices Q1 and Q2 in either direction, is called (a) unsymmetric triggering (b) dc triggering (c) symmetric triggering (d) monostable triggering

1002

Electronic Devices and Circuits

10. In a binary, when the ON transistor is driven into saturation, the storage time of the transistor becomes longer and the switching speed is limited. To overcome this problem, the ON transistor is held in the active region. Then the binary is called a (a) nonsaturating binary (b) saturating binary (c) Schmitt trigger (d) self bias binary 11. In the collector-coupled monostable multivibrator, the quasi-stable state is accounted for by the (a) RC coupling (b) dc coupling (c) transformer coupling (d) RR coupling 12. To make sure that the gate width of the collector-coupled monostable multivibrator is independent of the current in the ON device in the quasistable state, (a) the ON transistor is driven into saturation (b) both the transistors are driven into the active region (c) both transistors are driven into the OFF state (d) One transistor is driven into the active region and the other into saturation 13. A symmetric astable multivibrator oscillates at f = 1000 Hz and the transistors have hFE = 32. Then its recovery time is (a) 0.05 ms (b) 0.05 s (c) 0.5 ms (d) 0.5 s 14. A collector-coupled monostable is converted into a voltage-to-time converter by (a) connecting the timing resistor R to VCC (b) connecting the timing resistor R to an auxiliary dc source V (c) connecting collector catching diodes (d) connecting commutating condensers 15. UTP in a Schmitt trigger is defined as (a) the input voltage at which Q1 switches ON and Q2 switches OFF (b) the input voltage at which Q1 switches OFF and Q2 switches ON (c) the input voltage at which both Q1 and Q2 switches ON (d) the input voltage at which both Q1 and Q2 switches OFF 16. LTP in a Schmitt trigger is defined as (a) a lower input voltage at which Q2 once again switches ON and Q1 switches OFF (b) the input voltage at which Q1 switches OFF and Q2 switches ON (c) the input voltage at which both Q1 and Q2 switches ON (d) the input voltage at which both Q1 and Q2 switches OFF 17. Schmitt trigger can be used as a squaring circuit (a) only when the periodic input signal amplitude is above V1 and below V2 V + V2 (b) only when the periodic input signal amplitude is 1 2 V1 − V2 (c) only when the periodic input signal amplitude is 2 (d) none of the above 18. The expression for the time period of the voltage to time converter is  V   V  (a) T = t log n 1 + CC  (b) T = 2t log n 1 + CC    V  V    V V   (c) T = log n 1 + CC  (d) T = log n 1 +  V   VCC 

Multivibrators

1003

Short anSwer QueStionS 1. Name the different types of multivibrators. 2. What is a bistable multivibrator? 3. What are the different names by which a bistable multivibrator is also known as? 4. What is the main application of a binary? 5. What is the main limitation of the saturating binary and how is it overcome? 6. Why are collector-catching diodes used in a binary? 7. Define transition time and suggest how this can be drastically reduced? 8. Define the resolution time of the binary. 9. Name the two different methods of pulse triggering. 10. What is meant by unsymmetric triggering and when is it used? 11. What is meant by symmetric triggering? Name one application. 12. Write down the expression for the gate width of the collector-coupled monostable multivibrator and express the condition under which it is valid. 13.. Write down the expression for the frequency of the symmetric collector-coupled astable multivibrator. 14. Name some of the applications of the Schmitt trigger. 15. What is meant by range of hysteresis or dead zone in a Schmitt trigger?

long anSwer QueStionS 1. Draw the circuit of the fixed bias binary and explain its operation. Explain the procedure to calculate its stable currents and voltages. 2. Draw the circuit of the self-bias binary and explain its operation. 3. Draw the circuit of the collector-coupled monostable multivibrator and explain its working. Derive the expression for its gate width. 4. Explain, with the help a neat circuit diagram, the principle of working of a collector-coupled astable multivibrator and draw its waveforms. Derive the expression for its frequency. 5. Explain the working of the Schmitt trigger and derive expressions for V1 and V2. 6. (a) (c) (e)

Write short notes on the following: Methods of triggering a binary (b) Resolution time of the binary Voltage-to-time converter (d) Voltage-to-frequency converter Nonsaturating binary (f) Applications of Schmitt trigger

1004

Electronic Devices and Circuits

unSolved problemS 1. Design a collector-coupled monostable multi using Si transistors having hFE = 20, VCC = 12 V, I C(sat ) = 4 mA, T = 20 ms, and VBE(OFF) = −1 V . Assume VCE(sat ) = Vs = 0 and R1 = R2 2. For the fixed bias binary shown in Figure 18.6, VCC = VBB = 15 V , RC = 5 kΩ, R1 = 15 kΩ, R2 = 30 kΩ, VCE(sat ) = 0.2 V , Vσ = 0.7 V, and hFE(min) = 40. Assume that Q2 is in saturation and Q1 is OFF. (i) Determine the stable state voltages and (ii) the value of RL (min) 3. (i) Design a VCO using Si NPN transistors having hFE = 30, to oscillate at 5 kHz, assuming VCC = 9 V and V = 6 V, I C(sat ) = 2 mA. (ii) What is its frequency if V = 3V? 4. Design an unsymmetric astable multivibrator using Si NPN transistors having hFE = 40, to oscillate at 1 kHz and a duty cycle of 60 percent. Assume VCC = 12 V and I C(sat ) = 4 mA 5. Si transistors having hFE = 40 are used in the Schmitt trigger circuit shown in Figure 18.68. VCC = 12 V , RC1 = 2 kΩ, RC2 = 1 kΩ, R1 = 2 kΩ, R2 = 6 kΩ, and RE = 3 kΩ. Calculate the values of UTP and LTP. 6. If f1 is the frequency of oscillations of a voltage-controlled oscillator when V = VCC , find the V ratio of CC for the frequency f2 = 2 f1 V Cramer’s Rule Given a system of linear equations, Cramer’s rule is a handy tool to solve for the variables. Consider the following system of equations: a1x + b1 y = c1   a2 x + b2 y = c2 

(1)

Equation (1) in the matrix form is written as follows: b1   x   c1  = b2   y  c2 

 a1 a  2

(2)

Assuming that a1b2 − a2 b1 is nonzero, then, x and y can be found with Cramer’s rule as follows:

x=

c1

b1

a1

c1

c2 a1 a2

b2 a and y = 2 b1 a1 b2 a2

c2 b1 b2

(3)

19

TIME-BASE GENERATORS

Learning objectives After reading this chapter, the reader will be able to  Understand the need for a sweep generator  Learn the principle of working of a UJT exponential sweep generator  Learn the methods of linearizing an exponential sweep using Miller and bootstrap sweep circuits  Obtain the interrelationship between slope error, displacement error, and transmission error  Understand the need and the principle of working of a current sweep and the method to linearize the exponential current sweep.

19.1

INTRODUCTION

A cathode ray oscilloscope (CRO) is used to display electrical signals and measure their amplitude, frequency, and phase difference between two signals. The signal to be displayed on the cathode ray tube (CRT) screen is applied as input through an amplifier to the vertical deflecting plates. To be able to display time-varying signals, it is not only required to shift the spot (electron beam) along the Y-axis but also along the X-axis as a linear function of time. The waveform generator that is used to move the spot along the X-axis (time axis) is called the sweep generator or time base generator. An ideal time-base signal is a signal that varies linearly from 0 to VS during the time interval 0 to TS , the sweep duration and ideally falls off to 0 at TS (Figure 19.1(a)). This type of waveform is called the saw-tooth waveform as it resembles the teeth of a saw. However, a practical sweep may not necessarily be linear (Figure 19.1(b)). The sweep voltage may not increase linearly. In addition, there is a finite time delay before the sweep amplitude reaches 0 at the end of the sweep duration, TS . This time duration is called the retrace time, Tr or the fly-back time, Tf . Ideally, this time period should be 0. Basically, the horizontal deflection of the electron beam in a CRO can be due to the application of a voltage between the pair of X-deflecting plates or due to the current flowing through a coil (called the yoke) that is placed behind the gun structure. The principle used in the former is called electrostatic deflection and that in the latter is called electromagnetic deflection. Sweep generators are classified as (i) voltage sweep generators and (ii) current sweep generators. Voltage sweep generators are used in CROs and current sweep generators are used in television and radar receivers.

1006

Electronic Devices and Circuits

VS

vs

0

t

TS (a)

vs

VS

0 t

TS Tr (b)

Figure 19.1 (a) Saw-tooth waveform and (b) nonlinear sweep with retrace time

19.2 VOLTAGE SWEEP GENERATORS Voltage sweep generators are classified as (i) exponential sweep generator, (ii) Miller’s sweep or Miller integrator sweep, and (iii) bootstrap sweep generator.

19.2.1 Exponential Sweep Generator A simple voltage sweep generator consists of a capacitor C charging to a voltage V through a resistor R. Charging and discharging of C is controlled by a switch S (Figure 19.2). Initially, let there be no charge on C. Let S be open, then C tries to charge to V. However, when the charge on C is VS , let the switch close. Then the charge on C discharges to 0 instantaneously, if the ON resistance of the switch is ideally 0. If there is a small ON resistance of the switch, then the charge on C falls to 0 with small time constant resulting in a small retrace time. V vs

VS

R + V

C

S

vs −

0 TS

Figure 19.2 (a) Exponential sweep generator and (b) output

t

Time-Base Generators

1007

The circuit of Figure 19.2(a) is a low-pass RC circuit. As such, its output for step input can be obtained from the following relation: −t

u s ( t ) = Vf − (Vf −Vi ) e t

(19.1)

where t = RC We have Vi = 0 and Vf = V Therefore, Eqn. (19.1) can be written as follows: −t −t   u s ( t ) = V − (V − 0 ) e t = V 1 − e t   

(19.2)

From Eqn. (19.2), it is evident the resultant sweep voltage is nonlinear. In the circuit of Figure 19.2(a), a switch S is placed, which opens and closes at predetermined voltage levels across C. This switch should obviously be an electronic device, which in the physical form is a unijunction transistor (UJT).

Unijunction Transistor A unijunction transistor is a three-terminal device, but it has only one PN junction. The device consists of a lightly doped N-type silicon bar and a heavily doped P-type block on one side. From either end of the N-type bar, two terminals are externally brought out, which are identified as B 1 (base1) and B 2 (base2). The P-type block is called the emitter E (see Figure 19.3(a)). Figure 19.3(b) represents the dc equivalent circuit and Figure 19.3(c) gives the schematic representation of UJT. RB1 and RB2 depend on the amount of doping in the N-type bar. B2 B2 B2

E N P

RS

IE

VEE

+ VE IEO −

RB2 V1

E

VBB

E

RB1 B1 B1

B1 (a)

(b)

(c)

Figure 19.3 Unijunction transistor

(i) When the externally applied bias voltage, VBB = 0 , as VEE is increased from 0, the UJT simply behaves as a diode and the resultant V–I characteristic is simply the diode characteristic (Figure 19.4). (ii) When the bias voltage VBB is now set at a desired value, V1 , the dc voltage at the junction of RB1 and RB2 is

1008

Electronic Devices and Circuits

V1 = VBB

RB1 R = VBB B1 = hVBB RB1 + RB 2 RBB

(19.3)

where RBB is the resistance between the two bases (interbase resistance) and h =

RB1 is called the RBB

intrinsic stand-off ratio. h typically varies between 0.74 and 0.86. If now the input voltage, VE is varied from 0 to larger value, till such time this voltage is equal to V1, the diode is reverse biased. Hence, only leakage current I EO flows as shown in Figure 19.3(b). However, when VE is slightly more than V1 , the diode is forward biased. As the P-type emitter is heavily doped, large number of charge carriers are injected in to the RB1 region, resulting in decrease in the resistanceRB1. Decrease in RB1 reduces the voltage drop across it. Hence, the diode is more heavily forward biased. This further increases the emitter current, I E. There will now be more charge carriers that will reduce RB1 further. This results in further increase in I E and the process becomes regenerative. Hence, VE decreases and I E increases to a maximum value as determined by the source resistance of VEE source. From Figure 19.4, it can be noted that at a voltage called the peak voltage, VP which is slightly more than V1 , the UJT conducts (goes in to the ON state) and the corresponding current is called I P. As I E increases, VE decreases and eventually reaches a voltage called the valley voltage, VV . Any further increase in I E will place the device in saturation. The current at VV is called I V . The UJT is now said to be in saturation. Between VP and VV , the devise exhibits negative resistance. A positive resistance is one that obeys Ohm’s law. This means as V increases, I increases and vice versa. But in the case of UJT, between VP and VV , as I E increases, VE decreases. In this region, the device is said to be behaving as a negative resistance. The VE vs I E relationship is shown in Figure 19.4. Cut-off region

Negative resistance region

VE

Saturation region

Peak point VP

VE(sat) VV

Valley point When VBB = 0

IEO 0 IP

IV

IE

Figure 19.4 V–I characteristic of UJT

From Figure 19.4, it is evident that a UJT can be used as a switch that is ON when VE = VP and is OFF when VE = VV . Thus, UJT can be used as a switch in sweep generators.

Time-Base Generators

1009

UJT Parameters Some of the parameters of UJT are listed below: (i) Interbase resistance, RBB : This is the sum of RB1 and RB2 when I E = 0 . Normally, the minimum and maximum values of RB1 and RB2 are specified in the data sheet. The maximum value of VBB is usually determined by knowing PD( max ) and RBB as (19.4)

VBB( max ) = RBB PD( max )

(ii) Intrinsic stand-off ratio, h: It is the ratio of RB1 to RBB . The peak voltage is determined knowing h, VBB , and VF , the forward voltage of the diode as (19.5)

VP = VF +hVBB (iii) Peak-point emitter current, I P : For the UJT to be ON, the minimum current required is I P . If I E is not larger than I P , the UJT can not be switched ON. If VEE source resistance is very large, then I E cannot be more than I P . Hence, using Figure 19.5 it is possible to determine the maximum resistance RE , by knowing I P as RE ( max ) =

VBB −VP IP

(19.6)

R2

RE(max)

R1

IP B2 VBB

+ E VP −

B1

Figure 19.5 Circuit to calculate RE(max) (iv) Emitter saturation voltage, VE (sat ) : It is the emitter voltage when the UJT is in saturation and is approximately the same as VV . (v) Valley point emitter current, I V : If RS is so low that I E ≥ I V , the UJT will remain ON, once it is triggered. It cannot be brought to the OFF state. Hence, the minimum value of RE can be determined by knowing I V as

RE ( min ) =

VBB −VE (sat ) IV

(19.7)

Example 19.1 A UJT has RBB( min ) = 4 kΩ and PD = 100 mW . (i) Determine the value of VBB . (ii) Determine the maximum and the minimum triggering voltage levels for the value of VBB calculated, if h varies from 0.74 to 0.86. (iii) Determine RE ( min ) and RE ( max ) , if I V = 2 mA , I P = 0.75 mA , and VE (sat ) = VV = 2.4 V. Solution: (i) VBB( max ) = PD RBB = 100 × 4 = 20 V (ii)

VP (min) = VF + h(min)VBB = 0.7 + 0.74 × 20 = 15.5 V VP ( max ) = VF + h( max )VBB = 0.7 + 0.86 × 20 = 17.9 V

1010

Electronic Devices and Circuits

(iii) R = E ( max ) RE (min) =

VBB − VP (min) IP VBB − VE (sat ) IV

=

=

20 − 15.5 = 6 MΩ 0.75

20 − 2.4 = 8.8 kΩ 2

Example 19.2 For the UJT circuit shown in Figure 19.6, RBB = 3 kΩ , VBB = 20 V, h = 0.75, R1 = 100 Ω , and RB1 = 100 Ω when the UJT is ON. I V = 10 mA , I P = 0.01 mA , and VE (sat ) = VV = 2.4 V . Calculate (i) RB1 and RB2 under quiescent condition, (ii) the peak voltage VP , (iii) the permissible value of R, and (iv) the voltage level VB1 , when the UJT is OFF and when it is ON.

R

E

+ VP

B2 B1

VBB

R1

−

Figure 19.6 UJT circuit with R1 connected externally

Solution: (i) h =

RB1 or RB1 = hRBB = 0.75 × 3 = 2.25 kΩ RBB

RB2 = RBB − RB1 = 3 − 2.25 = 0.75 kΩ (ii) VP = VBB

(iii) R(max ) =

R(min) =

(RB1 + R1 ) + V = 20 × (2.25 + 0.1) + 0.7 = 15.86 V 3 + 0.1 (RBB + R1 ) F

VBB − VP 20 − 15.86 = = 414 kΩ IP 0.01 VBB − VV 20 − 2.4 = = 1.76 kΩ IV 10

R should lie between R( max ) and R( min ). (iv) When the UJT is OFF, VB1 = VBB ×

R1 0.1 = 20 × = 0.645 V 3 + 0.1 (RB1 + R1 )

Time-Base Generators

1011

When the UJT is ON, VB1 = (VP − VF )

R1 0.1 = (15.86 − 0.7) × = 7. 58 V 0.1 + 0.1 (RBB + R1 )

The voltage change at B1, VB1 from 0.645 to 7.58 V is in form of a pulse, which can be used to trigger a circuit.

UJT as a Relaxation Oscillator (Sweep Generator) UJT can be used as a relaxation oscillator as shown in Figure 19.7(a), and the waveform of the sweep voltage is shown in Figure 19.7(b). VBB R

VP

B2 +

VBB B1

C

vs VV

vs

TS

0

− (a)

(b)

Figure 19.7 (a) UJT sweep generator (b) Waveform

In Figure 19.7(a), the UJT is simply used as a switch that closes when the voltage across C is VP and opens when the voltage across C is VV . Initially, when the capacitor is uncharged, the UJT switch is open, and hence C tries to charge to VBB. However, at t = TS , when the voltage across C reaches VP , the UJT switch closes and the charge on C is expected to discharge to 0. But when the voltage across C reaches VV , UJT switches into the OFF state and once again C tries to charge to VBB, and so on. The result is the sweep waveform shown in Figure 19.7(b). The charging time constant t C = RC. The frequency of oscillations is calculated as given below: From Eqn. (19.1), us (t ) = Vf − (Vf − Vi ) e

t tC

We have Vi = VV and Vf = VBB , ∴ us (t ) = VBB − (VBB − VV ) e

−t tC

(19.8)

At t = TS , u s ( t ) = VP , Substituting in Eqn. (19.8), −TS

TS

tC

tC

VP = VBB − (VBB − VV ) e

or

TS = t C ln

e

(VBB −VV ) (VBB −VP )

=

(VBB −VV ) (VBB −VP ) (19.9)

1012

Electronic Devices and Circuits

fS =

1 TS

(19.10)

Alternately, TS can also be calculated using the value of h. us (t ) = Vf − (Vf − Vi ) e

−t tC

We have Vi = 0 and Vf = VBB ∴

us (t ) = VBB − (VBB − 0 ) e

−t tC

(19.11)

At t = TS ,u s (t ) = hVBB Substituting in Eqn. (19.11), −TS

hVBB = VBB − (VBB − 0 ) e

or

tC

TS = t C ln

hVBB

−TS   t = VBB 1 − e C   

1

(19.12)

(1 − h )

Calculation of Retrace Time, Tr At the end of the

sweep duration, the UJT switch closes and C discharges (Figure 19.8). When the UJT switch is ON, RB1 = 0.1 kΩ, through which the charge on C discharges. The discharging time constant t d = RB1C = 0.1 ´ 103 ´ 0.5 ´ 10 -6 = 0.05 ms.

VP vs

TS

Again using Eqn. (19.1),

Tr

VV

0

us (t ) = Vf − (Vf − Vi ) e

Figure 19.8 Calculation of retrace time

−t td

Considering TS as the reference time, Vi = VP and Vf = 0 Substituting this condition in Eqn. (19.1), us (t ) = 0 − (0 − VP ) e

−t td

At t = Tr ,u s ( t ) = VV ∴

VV = VP e

−Tr td

Hence, V  Tr = t d ln  P   VV 

= VP e

−t td

(19.13)

Time-Base Generators

1013

Example 19.3 For the UJT relaxation oscillator, R = 10 kΩ , C = 0.05 mF , VV = 3 V , h = 0.75, VF = 0.7 V , and VBB = 18 V. Calculate fS (i) assuming that the fly-back time is negligible and (ii) considering the fly-back time also, if RB1 = 0.1kΩ Solution: VP = VF + hVBB = 0.7 + ( 0.75)(18) = 14.2 V (i) TS = t C ln

(VBB -VV ) (VBB -VP )

(VBB −VV ) = 18 − 3 = 3.95 (VBB −VP ) 18 − 14.2 t C = RC = 10 × 103 × 0.05 × 10 −6 = 0.5 × 10 −3 s TS = 0.5 × 10 −3 ln 3.95 = 0.69 ms fS =

1 = 1.45 kHz TS

V  (ii) Tr = t d ln  P  , t d = RB1C  VV  VP 14.2 = = 4.73 3 VV Tr = 0.1 ´ 103 ´ 0. 05 ´ 10 -6 ln ( 4.73) = 0.0 078 ms T = TS + Tr = 0.69 + 0.0078 = 0.6978 ms fS =

1 = 1.43 kHz T

Example 19.4 Design the UJT sweep generator circuit to oscillate at 10 kHz. The supply voltage is 18 V. The UJT has VV = 3 V , VF = 0.7 V , I P = 5 mA , I V = 2 mA , and h = 0.65 – 0.85. Find the peak-to-peak amplitude of the output. Solution: Average value of η =

0.65 + 0.85 = 0.75 2

VP = VF + hVBB = 0.7 + ( 0.75 )(18 ) = 14.2 V Rmax =

VBB − VP 18 − 14.2 = = 760 kΩ IP 5 × 10 −6

Rmin =

VBB − VV 18 − 3 = = 7.5 kΩ IV 2 × 10 −3

1014

Electronic Devices and Circuits

R must lie between Rmax and Rmin . Choose R = 47 kΩ TS =

1 1 = = 0.1 ms = 100 µs fS 10

TS = t ln

(VBB −VV ) (VBB −VP )

(VBB −VV ) = 18 − 3 = 3.95 (VBB −VP ) 18 − 14.2 RC =

ln 3.95 = 1.37

TS 100 × 10 −6 = = 72.99 × 10 −6 1.37 1.37

C=

72.99 × 10 −6 = 1.55 nF 47 × 103

VS(p - p) = 14.2 - 3 = 11.2 V Sometimes to derive positive spikes that can be used to trigger some other circuit, a small resistance R1 of the order of 0.1 kΩ is connected to B1, and to derive negative spikes a resistance R2 which can be 5–10 times larger than R1 is connected to B2 (Figure 19.9). VBB

R2 R B2

VBB VP

C B1 R1

vs VV TS 0

Figure 19.9 Spikes derived in a UJT circuit

Programmable Unijunction Transistor Programmable unijunction transistor, or PUT is, in fact, a four-layer device and consists of an anode A, a cathode K, and a gate connected as shown in Figure 19.10(a). Figure 19.10(b) shows the schematic representation of the device, and Figure 19.10(c) gives the relation between the anode voltage V A and anode current I A. Although this is a four-layered device, it is called UJT because its V–I characteristic is similar to the V–I characteristic of a UJT. However, in the case of this device, it is possible to control h by the choice of the external resistances R1 and R2 ; whereas in the case of UJT, RB1 and RB2 are the bulk resistances (Figure 19.11). Hence, this device is called PUT.

Time-Base Generators A

1015

+

+ VAG

P J1 N

G +

VA J 2

VA

A

−

VP

G

P J3

VGK

N

VV

K IGA IP

− K (a)

IV

IA

− (b)

(c)

Figure 19.10 Programmable unijunction transistor: (a) construction, (b) schematic representation, and (c) V–I characteristic

Figure 19.11 shows the biasing of the PUT. The device is said to be programmable because the intrinsic stand-off ratio h and the breakdown or the firing voltage VP can be programmed to any desired values through external programming resistors R1 and R2 and the supply voltage VBB. When

IG = 0, VG = VBB

and

R1 = hVBB R1 + R2

VBB B2 E

G

VA

VG IA

(19.14)

R1 K

(19.15)

VP = hVBB + VF

R2

A

B1 where VF is the forward voltage of the anode-gate diode. The anode-gate diode is forward biased when VAG is 0.7 V more than VG . When this occurs, the device is turned ON. The anode-to-cathode voltage VA than drops to a low level, and the Figure 19.11 PUT equivalent circuit device conducts heavily until the input voltage become too low to sustain conduction. The anode of the device acts as the emitter of UJT. Figure 19.12(a) shows the PUT relaxation oscillator and Figure 19.12(b) shows the waveforms. VBB VP R2 R

vs VG

+

0

vs

C

vR R3

−

t TS

+ R1

vR 0

(a)

(b)

Figure 19.12 PUT relaxation oscillator and waveforms

1016

Electronic Devices and Circuits

When VBB is switched on, C tries to charge to VBB. However, when the voltage across C equals VP, the device fires (conducts heavily) and anode current IA flows. The charge on C discharges rapidly through the low ON resistance of the PUT and R3. As a result, a voltage spike u R is produced across R3 during the discharge. As soon as C gets discharged, the PUT turns OFF and the charging cycle starts once again. The time period of the relaxation oscillator is given as follows:  VBB  T = RC 1n    VBB −VP 

(19.16)

Example 19.5 For the relaxation circuit in Figure 19.12, VBB = 18 V , R1 = 20 kW , R2 = R = 10 kΩ , and C = 0.1 mF . Calculate f . Solution: VG = VBB

R1 20 = hVBB = 18 × = 12 V R1 + R2 20 + 10

VP = hVBB + VF = 12 + 0.7 = 12.7 V  VBB   18  T = RC ln  = 10 × 103 × 0.1 × 10 −6 ln  = 1.22 ms   18 − 12.7   VBB − VP  f =

1 1000 = = 819.7 Hz T 1.22

The output of an exponential sweep generator as shown in Figure 19.7(b) is not linear. Consequently, the spot does not move linearly as function of time along the X-axis in a CRO. The deviation from linearity is expressed by three types of errors: (i) slope error or sweep speed error, (ii) transmission error, and (iii) displacement error. (i) Slope error: It is defined as ratio of the difference in the slope at the beginning and the end points of a sweep to the initial slope and is expressed as a percentage (Figure 19.13).

dvs/dt at t = TS vs

dvs/dt at t = 0 0

t TS

Figure 19.13 Calculation of slope error

du s du at t = 0 − s at t = Ts Initial slope - final slope dt dt Slope error = es = = du s Initial slope at t = 0 dt The expression for the output voltage of the exponential sweep generator from Eqn. (19.2) is −t   us = V 1 − e t   

−t −t dus −1 V t = −Ve t × = e dt t t

Time-Base Generators

1017

−Ts du s V d us V at t = 0 = and at t = Ts = e t dt t dt t

V V − e ∴ es = t t V t

−Ts t

= 1− e

−Ts t

(19.17)

At t = TS , u s =VS . Therefore, Eqn. (19.2) is written as follows: −TS   VS = V 1 − e t    −TS

∴

1− e

t

=

VS V

(19.18)

Substituting Eqn. (19.18) in Eqn. (19.17), es =

VS V

(19.19)

From Eqn. (19.2), at t = 0,u s = 0 and at t = ∞,u s = V . Therefore, V is the peak to peak swing of the output. Hence, Eqn. (19.19) says that the slope error of a sweep generator can be calculated as a ratio of the sweep amplitude and the peak-to-peak swing of the output voltage. Obviously, the smaller the slope error, the more linear the sweep voltage generated. However, for es to be small V � VS . Consider that VS = 10 V , then for es to be 10 percent, V should be 100 V, for es to be 1 percent, V should be 1000 V. Therefore, if the sweep amplitude is large, to limit the error to a small value (in other words derive a linear sweep), V should be prohibitively large. This is the main limitation of the exponential sweep generator. Alternately, Eqn. (19.2) can be written as follows: −t   t   t 2   Vt  t  u s = V 1 − e t  = V 1 − 1 − + 2   = 1 −  2 t t t 2 t       

(19.20)

Let VS be the amplitude of the nonlinear sweep and VS′ , the amplitude of the linear sweep at t = TS . For a linear sweep, consider only the first term of the expansion in Eqn. (19.20). Then, VS′ =

VTS V′ T or S = S = eS t V t

(19.21)

If V cannot be made excessively large to limit the slope error to a small value, alternately, Eqn. (19.21) tells that the slope error can be made small if the time constant of the circuit, t is very much larger than the time duration of the sweep. (ii) Transmission error: When a ramp is applied to a high-pass circuit, the output falls away from the input (Figure 19.14). The resultant error is called the transmission error et .

Electronic Devices and Circuits

′ From Eqn. (19.21), VS =

and

VS =

VTS t

VTS t

VS′

(19.22)

 TS  1 − 2t 

Sweep voltage

1018

(19.23)

Using Eqs (19.22) and (19.23), transmission is calculated as follows:

VS

0

VTS VTS  TS  1− − ′ V −V t t  2t  TS et = S ′ S = = VTS 2t VS t

TS

Figure 19.14 Calculation of the transmission error

(19.24)

From Eqs (19.21) and (19.24), it can be noted that

et =

eS 2

(19.25)

(iii) Displacement error: Displacement error is the ratio of the maximum displacement between the practical sweep and the linear sweep, which passes through the beginning and end points of the practical sweep, to the sweep amplitude (Figure 19.15). (vs′−vs)max

vs

VS

vs′

0 TS /2

TS

Figure 19.15 Calculation of displacement error

us′ =

Vt  t  Vt and u s = 1 −  t  2t  t

us′ − us = Maximum displacement occurs at t =

Vt Vt  t  Vt t − 1 −  = × t t  2t  t 2t

(19.26)

TS . Substituting in Eqn. (19.26), 2

(u

′ s

− us

)

max

=

VTS TS × 2t 4t

(19.27)

Time-Base Generators

u s′ = VS

t = TS

At

∴VS =

VTS t

1019

(19.28)

Substituting Eqn. (19.28) in Eqn. (19.27),

(u Displacement error = ed =

′ s

− us

(u

′ s

)

max

− us VS

)

=

max

VS TS × 2 4t =

(19.29)

TS es = 8t 8

(19.30)

From Eqs (19.25) and (19.30), (19.31)

es = 2et = 8ed

From Eqn. (19.31), it can be noted that if one type of error is calculated, the other type of error can be directly calculated.

Linear Voltage Sweep Generators In an exponential sweep generator, the charging current of C varies exponentially, and hence the resultant sweep is not necessarily a linear sweep. If a linear sweep is to be desired, then C must be charged with a constant current. In Miller and bootstrap sweep generators C is charged with a constant current, and hence these two types of sweep generators produce a near linear sweep.

19.2.2 Miller’s Sweep Generator Consider the circuit in Figure 19.2(a). Now an auxiliary generator u is introduced in the circuit such that at any given instant of time the voltage u across the generator terminals is equal in magnitude to the voltage u c across the capacitor terminals but opposite in polarity (Figure 19.16). The result is that the net voltage in the loop is V . Hence, the current i in loop is V /R , which is constant. As the capacitor C charges with a constant current, the resultant sweep generated is a linear sweep. R

i

X

R

X + +

Y − v

Vi

vc

C

V

−

C

V

+

vc

−

−

+

v Z

+

−

Y

Figure 19.16 Linearizing an exponential sweep

Z

Figure 19.17 Principle of Miller’s sweep

Three nodes X, Y, and Z are identified in Figure 19.16. Let us assume that node Z is grounded. Then, the circuit in Figure 19.16 can be redrawn as shown in Figure 19.17. Consider that X and Z as the input terminals and Y and Z as the output terminals of an amplifier. Then the input to the amplifier Vi is 0; and hence to derive a finite output, the amplifier is required to have a gain of infinity. Therefore, the auxiliary generator u can be replaced by an amplifier whose gain is ideally infinity. This type of sweep generator is called the Miller’s sweep generator.

1020

Electronic Devices and Circuits

Slope Error in a Miller’s Sweep If in Figure 19.16, consider Z is the ground terminal, X and Z are the input terminals of the amplifier, and Y and Z are the output terminals; the resultant circuit is drawn as in Figure 19.18. Here ideally R o is taken as 0 to simplify the analysis. Thevenizing the input circuit (Figure 19.18), V′ =V

Ri and R ′ = R Ri R + Ri

(19.32)

The corresponding circuit is shown in Figure 19.19. C

X

Y

R

Y

R′ A = −∞

V

C

X

+

Ri

+ AVi Vo

−

+ V′

A = −∞

+

Vi

−

−

Z

+ AVi Vo −

Z

Figure 19.18 Miller’s sweep

Figure 19.19 Thevenized ciruit

At t = 0 , when V is switched ON, Vi = 0 and hence Vo = AVi = 0. At t = ∞ , C is fully charged and hence is an open circuit for dc. Therefore, Vi = V ′ and Vo = AV ′. Peak-to-peak excursion of the output swing = Vo (t = ∞ ) −Vo (t = 0 ) = AV ′

Hence,

es(Miller) =

VS = AV ′

VS VRi A R + Ri

  R R 1 +  1 +  Ri  Ri  V = S × = es(exponential) ×  V A A

(19.33)

Equation (19.33) tells that the slope error of the Miller’s sweep is very much smaller than that of the exponential sweep because A is very large. Small Ri of the amplifier will not have much, say, as far as es (Miller) is concerned.

A Practical Miller’s Sweep Generator A practical Miller’s sweep generator consists of a transistor switch Q 1, which initially is in the ON state and in saturation and another transistor Q 2 connected in the CE mode for large voltage gain. The Miller capacitor C is connected between the input and the output terminals of the amplifier (Figure 19.20). When Q 1 is ON, Q 2 is OFF and Vo = VCC . At t = 0 when the trigger is applied Q 1 switches into the OFF, state and Q 2 into the ON state and is driven into saturation and V o is required to fall to V CE(sat) ≈ 0 . As C charges through R, V o decreases linearly to V CE(sat) ≈ 0. If the charging time constant is large, the charging current iC remains constant. Hence, the sweep variation is linear. When the input pulse is removed, the transistor Q 1 once again turns ON and Q 2 turns OFF, and the charge on C discharges through R C and V o returns to V CC at the end of the recovery time, T r.

Time-Base Generators

1021

VCC R

RC

C

RB

T +

Q1

Ts

0

Q2

+

VCC vs

Vo

Vi

0

Ts

Tr

−

−

Figure 19.20 Miller integrator sweep generator

Calculation of the Sweep Time Ts At t = 0+, when the trigger pulse goes negative, C charges through R as Q 2 switches into saturation. The charging current iC ≈ us =

iC V t × t = CC C RC

At t = Ts, us = Vs = VCC. Substituting in Eqn. (19.34), VCC = ∴

Ts = RC

Similarly,

VCC . R

(19.34) VCCTs RC (19.35)

Tr = RCC

(19.36)

T = Ts + Tr

(19.37)

For the Miller’s sweep circuit shown in Figure 19.20, VCC = 18 V , 1 R = 4.7 kΩ, RC = 1 kΩ, and C = 0.05 mF . The transistor has hfe = 100, hie = 1 kΩ, = ∞ , and hoe hre = 0. Calculate (i) f and (ii) slope error. Example 19.6

Solution: (i) Ts = RC = 4.7 × 103 × 0.05 × 10 −6 = 0.235 ms Tr = RCC = 1 × 103 × 0.05 × 10 −6 = 0.05 ms T = Ts + Tr = 0.235 + 0.05 = 0.285 ms f =

1 1 = = 3.51 kHz T 0.285

(ii) For the CE amplifier, Ri = hie = 1 kΩ and RL = RC = 1 kΩ ∴ A = −hfe

RL 1 = −100 × = −100 Ri 1

1022

Electronic Devices and Circuits

Hence, es(Miller) =

VCC VCC

 R 4.7 1 + R  1 + i 1 × 100 = 5.7% × = A 100

19.2.3 Bootstrap Sweep Generator In the circuit in Figure 19.16, consider Y as the ground terminal, X and Y as the input terminals, and Z and Y as the output terminals of an amplifier (Figure 19.21). uc, the input to the amplifier and v the output of the amplifier have the same phase and the same magnitude. If the auxiliary generator is replaced by an amplifier with gain 1, the output of the amplifier changes in an identical manner as the input (Figure 19.22). Hence, the sweep generator is called the bootstrap sweep generator. The amplifier is an emitter followor with unity gain, large Ri and small Ro. R R

Z

X +

V

C

Z

+ vc

−

V

v Y

X A=1 +

+

Ri

Vi S

Ro

AVi

Vo

−

C Y

−

Figure 19.21 Principle of bootstrap sweep generator

+

−

Figure 19.22 Auxiliary generator replaced by unity gain amplifier

At t = 0, let switch S be open. If C is initially uncharged, Vi = 0. Then AVi = 0. Then, the circuit in Figure 19.22 at t = 0 can be drawn as in Figure 19.23. R X R

+ Y −

V Vo

Ro

+

V

Ri − Y − ARi + + Ro −

− Vo +

Z

Z

(a)

(b)

Figure 19.23 (a) Circuit to calculate Vo at t = 0 and (b) circuit to calculate Vo at t = ∞

From Figure 19.23(a), Vo ( t = 0 ) = −V As t → , C is an open circuit.

Ro ≈ 0 , since Ro � R R + Ro

 Ro A− Ri ( ARi − Ro )  From Figure 19.23(b) Vo ( t = ∞ ) = V =V Ro Ri + Ro + R − ARi (1 − A) + Ri

   R + Ri

≈

V

(1− A) +

R Ri

Time-Base Generators

V

Peak-to-peak excursion of the output swing = Vo (t = ∞ ) −Vo (t = 0 ) =

(1 − A) + Vs V

Therefore, slope error of bootstrap sweep generator =

=

1023

R Ri

 R (1 − A) +  Ri  

Vs V

R Ri

(1 − A) +

 R R es ( bootstrap ) = es ( exponential ) (1 − A) +  ≈ es ( exponential ) × Ri  Ri 

(19.38)

since A ≈ 1. If, R = Ri , then es ( bootstrap ) = es ( exponential ) . In such a case, there is no improvement in linearity. For the bootstrap sweep to be linear, Ri >> R. This condition is easily satisfied in the circuit since Ri of the emitter follower is large.

A Practical Bootstrap Sweep Generator A practical bootstrap sweep generator is shown in Figure 19.24. To ensure that Q 2 always remains in the active region, the bottom end of R E is returned to −V EE. Q 1 acts as a switch and Q 2 is an emitter follower. VCC IB1

D

+ VF − IC1 = I IB2

R RB

+

0

Ts

+ Vi

VCE(sat) C1

Q1

−

+

C2

Q2

+ VBE2 C −

VCC

+ RE

Vo

− −VEE

Figure 19.24 Bootstrap sweep generator

Quiescent Condition Prior to the application of the trigger Q 1 is ON and Q 2 is in the active region. As I B 2 TS) = IL e

iL

t

0

Ts

0 (b)

ILRd VCC VC t

0 0 (c)

Figure 19.28 Waveforms of the current sweep

The above relations are derived based on the assumption that the inductor is ideal. However, a practical L will have an associated RL. Further, when Q is ON, the resistance between the collector and emitter terminals is assumed ideally to be zero. But, in practice, there exists a small collector saturation resistance RCS. Above all, the inductor current varies exponentially. Hence, iL can be expressed as follows:

1028

Electronic Devices and Circuits

iL =

(

− (RL + RCS )t  VCC  L  1− e  RL + RCS   

)

− RL + RCS t

e

L

= 1−

(19.49)

(RL + RCS ) t + (RL + RCS )2 t2

(19.50)

2 L2

L

Substituting Eqn. (19.50) in Eqn. (19.49), 2 2 VCC   (RL + RCS ) t (RL + RCS ) t   1 − 1 − iL = +    RL + RCS   L 2 L2  

(19.51)

After simplification Eqn. (19.51) can be written as follows: iL =

VCC t  ( RL + RCS ) t  1 −  2L L  

(19.52)

VCC The peak-to-peak excursion of iL = and I L ( max ) is the sweep amplitude. Therefore, RL + RCS slope error es is es =

I L (max ) VCC RL + RCS

=

I L (max ) (RL + RCS )

(19.53)

VCC

If es is to be small, then I L ( max ) ( RL + RCS ) � VCC . Only when this condition is satisfied, the current sweep is linear. However, a more practical method to derive a linear current sweep is by adjusting the driving waveform.

19.3.1 Linear Current Sweep by Adjusting the Driving Waveform Consider the circuit in Figure 19.29 where the driving signal is u s and the requirement is that iL is a linearly varying current, di that is, iL = Kt . Then, L = K . The KVL is written down as dt follows: us = L

diL + iL ( RL + RCS ) = KL + Kt ( RL + RCS ) dt

Rs RL

+

vs

(19.54) −

L

Equation (19.54) comprises a step KL followed by a ramp Kt ( RL + RCS ) . This type of waveform is called a trapezoidal waveform (Figure 19.30). Equation (19.54) indicates that if a linear current sweep is to be generated, then the driving signal should be a trapezoidal waveform.

iL = Kt

Figure 19.29 Driving signal

Time-Base Generators

1029

19.3.2 Generation of Trapezoidal Waveform The circuit in Figure 19.31 is used to generate a waveform like the one shown in Figure 19.30. VCC R2 +

(Rs + RL)Kt

vs

R1 S

vs C1

LK 0

Trapezoidal waveform

0

−

t

Figure 19.30 Trapezoidal waveform

Figure 19.31 Circuit to generate trapezoidal waveform

R1 At t = 0, C1 in uncharged, and hence u s (0 ) = Vi = VCC . As t → ∞, C1 behaves as an open R1 + R2 circuit, and hence u s ( ∞ ) = Vf = VCC . −t

u s (t ) = Vf − (Vf − Vi ) e t In the circuit in Figure 19.31, t = (R1 + R2 )C1 −t

 R1  ( R1 + R2 )C1 ∴ us (t ) = VCC − VCC − VCC e R1 + R2   −t

(19.55) −t

 R1  ( R1 + R2 )C1 R2 ( R + R )C us (t ) = VCC − VCC 1 − e = VCC − VCC e 1 2 1  R1 + R2  R1 + R2 

u s (t ) =

VCC ( R1 + R2 ) − VCC R2 e R1 + R2

−t ( R1 + R2 )C1

(19.56)

Diving by R2, R  VCC  1 + 1 − VCC e  R2  us (t ) = R1 +1 R2

−t  R    R2  1 +1 C1    R  2  

VCC =

R1 + VCC − VCC e R2 R1 +1 R2

−t  R   R   1 +1 C1   2  R  2  

(19.57)

Usually, R2 � R1 . Therefore, Eqn. (19.57) reduces to us (t ) = VCC

−t   R1 RC + VCC 1 − e 2 1    R2

(19.58)

1030

Electronic Devices and Circuits

Expanding

−t e

R2C1

as a series, −t e

R2C1

= 1−

t t2 + R2C1 2 (R2C1 )2

(19.59)

−1     t  t t2 t  R2C1 VCC 1 − e − = VCC 1−  = VCC 1 − 1 + 2    R2C1 2( R2C1 )  R2C1  2R2C1  

But

t � 1 . Therefore, Eqn. (19.60) reduces to 2R2C1 −t   t RC VCC 1 − e 2 1  = VCC   R2C1

(19.60)

(19.61)

Substituting Eqn. (19.61) in Eqn. (19.58), u s (t ) = VCC

R1 t + VCC R2 R2C1

(19.62)

R1 t and a ramp VCC . R2C1 R2 A practical linear current sweep uses a trapezoidal waveform as the driving signal (Figure 19.32).

The output u s comprises a step VCC

VCC RL

Rd iL

L

D RB

R2 Q2 +

Q1 R1

Vi

0 0

vs Ts

RE

C1 −

Figure 19.32 A practical linear current sweep

A trapezoidal driving signal us is generated using Q1, R2, R1, and C1. A suitable RE is included in the emitter lead of Q2 to ensure large input resistance so as not to load the driving source. The resultant current sweep is a linear sweep. Example 19.8 For the current sweep generator shown in Figure 19.27, VCC = 15 V , L = 100 mH , RL = RCS = 10 Ω, Rd = 100 Ω, iL = I L ( max ) at t = 0.5 ms. Calculate the slope error.

Time-Base Generators

Solution: iL =

VCC t  ( RL + RCS ) t  15t 1 − = L  2L × 10 −3 100 

1031

 (10 + 10 ) t  1 − −3   2 × 100 × 10 

iL = 150t (1 − 100t ) At t = 0.5 ms, iL = IL(max)

(

∴ I L ( max ) = 150 × 0.5 × 10 −3 1 − 100 × 0.5 × 10 −3

)

= 75 (1 − 0.05) = 71.25 mA es =

I L ( max ) ( RL + RCS ) VCC

=

71.25 × 10 −3 (10 + 10 ) 15

× 100 = 9.5%

Additional Solved Examples Example 19.9 For the UJT relaxation oscillator shown in Figure 19.7, VBB = 24 V , R = 100 kΩ, C = 0.1 mF , VV = 3 V , and h = 0.6. Calculate (i) the sweep amplitude, (ii) the displacement error, (iii) the sweep duration, and (iv) the sweep frequency. Solution: (i) VP = hVBB + VF = 0.6 × 24 + 0.7 = 15.1 V Sweep amplitude = VS = VP − VV = 15.1 − 3 = 12.1 V (ii) Peak-to-peak excursion of the output swing = VPP = VBB −VV = 24 − 3 = 21 V es =

VS 12.1 = × 100 = 57.62% VPP 21

ed =

es 57.62 = = 7.2% 8 8

 V − VV   21  (iii) T = RC ln  BB = 100 × 103 × 0.1 × 10 −6 ln  = 8.59 ms   24 − 15.1  VBB − VP  (iv)

f =

1 1000 = = 116.4 Hz T 8.59

Example 19.10 For the Miller’s sweep circuit shown in Figure 19.20, R = 10 kΩ, RC = 1 kΩ, C = 0.1 µF, VCC = 18 V , and VS = 18 V . The transistor has the following parameters: hfe = 50, hie = 1 kW , 1 hre = 2.5 × 10 −4 , and = 40 kΩ. Calculate (i) Ts , (ii) Tr , (iii) f, and (iv) es . hoe Solution: (i) TS =

VS 18 × RC = × 10 × 103 × 0.1 × 10 −6 = 1 ms 18 VCC

1032

Electronic Devices and Circuits

(ii) Tr =

VS 18 × RCC = × 1 × 103 × 0.1 × 10 −6 = 0.1 ms 18 VCC

(iii) T = TS + Tr = 10 + 0.1 = 10.1 ms (iv) AI =

f =

1 1000 = = 99 Hz T 10.1

− hfe −50 = = − 48.78 1 1 + hoe RC 1+ 40 Ri = hie + hre AI RC = 1000 + 2.5 × 10 −4 ( − 48.78)1 × 103 Ri = 1000 − 12.2 = 987.8 Ω

A = AI ×

RC 1000 = − 48.78 × = − 49.38 Ri 987.8

 R 10 1+  1+  R VS  18 i 0 . 988 × 100 = 22.52% Hence, es (Miller ) = × = × A VCC 18 49.38 Example 19.11 For the bootstrap sweep generator shown in Figure 19.24, the supply voltages are ±15 V , RB = 30 kΩ , R = 10 kΩ, C = 0.3 mF , and RE = 1.5 kΩ. The trigger signal has an amplitude of −2 V and duration of 5 mS. The parameters of the transistor are hfe = 50, hie = 1 kW , 1 = 40 kΩ . All forward-biased junction voltages are negligible. Calculate (i) the hoe sweep speed and the sweep duration, (ii) the retrace time, and (iii) the slope error. Also, plot the waveforms. hrc = 1, and

Solution: (i) The voltage across C, u C = Sweep speed =

I t C

du C I VCC 15 = = = = 5 × 103 V/s dt C RC 10 × 103 × 0.3 × 10 −6

VCC = Sweep speed × TS TS =

(ii) Tr =

(iii) AI =

C hFE 1 − RB R

=

VCC 15 = = 3 ms Sweep speed 5 ´ 103

0.3 × 10 −6 0.3 0.3 × 10 −6 = = 0.19 ms = −3 50 1 10 (1.67 − 0.1) 1.57 − 30 × 103 10 × 103

1 + hfe 51 = = 49.75 1 + hoe RC 1 + 1 40

Time-Base Generators

1033

Ri = hie + AI RE = 1 + ( 49.75)1.5 = 75.63 kΩ hie 1 = = 0.013 Ri 75.63

1− A =

 R 10 es ( bootstrap ) = (1 − A) +  = 0.013 + = 0.013 + 0.133 = 0.146 Ri  75.63  % error = 14.6% VCC 15 = = 0.5 mA RB 30

I B1 =

I C1 = hFE I B1 = 50 × 0.5 = 25 mA VCC 15 = = 1.5 mA R 10 The waveforms are shown in Figure 19.33. 0 0

TG 5 ms

Vi

t

−2V VCC Vo 3 ms

0 0

Ts 25 mA

1.5 mA

IC1

t Tr 0.19 ms

hFEVCC/RB t

0

Figure 19.33 Waveforms

Example 19.12 In the current sweep circuit shown in Figure 19.27, the transistor has VCE ( max ) = 45 V , RL = RCS = 0, L = 100 mH , and iL increases linearly from 0 to 150 mA in 1 ms. Determine the maximum values of Rd and VCC . Also determine Tr . Solution: iL =

VCC t L At t = TS , iL = I L ( max )

∴

I L (max ) =

VCCTS L

I L ( max ) = 150 mA , L = 100 mH and TS = 1 ms

1034

Electronic Devices and Circuits

∴

VCC(max) =

I L (max) L TS

Rd (max ) =

=

150 × 10 −3 × 100 × 10 −3 = 15 V = VCC 1 × 10 −3

VCE (max ) − VCC IL

=

45 − 15 = 200 Ω 0.15

− Rd t

iL (t > Ts ) = I L (max ) e

L

At t = Tr , iL = 0.1I L ( max ) − RdTr

∴

0.1I L(max ) = I L(max ) e Tr =

L

L ln 10 Rd

RdTr

e

L

= 10

RdTr = ln 10 L

L 100 = = 0.5 ms Rd 200

Tr = 2.3 × 0.5 = 1.15 ms

Summary • Voltage sweep generators are used in CROs and the principle employed is electrostatic deflection. The purpose of a sweep generator is to move the electron beam horizontally along the X-axis. • Current sweep generators are used in Television and Radar receivers and the principle employed is electromagnetic deflection. • In a simple exponential voltage sweep generator the charging of the capacitor is exponential and hence the resultant sweep is non-linear, • Slope error, transmission error and displacement error define deviation from linearity and their inter-relationship is given as es = 2 et = 8 ed . • The non-linear exponential sweep can be linearized by charging the capacitor with a constant current. Miller and bootstrap sweep generators employ this principle to generate a linear voltage sweep. • A simple current sweep is once again a non-linear sweep and can be linearized by choosing trapezoidal waveform as the driving waveform.

multiple ChoiCe QueStionS 1. The signal that is to be applied between the X-deflecting plates to sweep the spot (electron beam) linearly as a function of time in a CRO is a (a) step voltage (b) sinusoidal signal (c) square wave (d) saw-tooth waveform 2. A time-base generator in which the output voltage varies linearly as a function of time is called a (a) square wave generator (b) pulse generator (c) voltage sweep generator (d) sinusoidal generator

Time-Base Generators

1035

3. A time-base generator in which the output current varies linearly as a function of time is called a (a) square wave generator (b) pulse generator (c) current sweep generator (d) voltage sweep generator 4. Of the three types of errors that define deviation from linearity the following error is the smallest in an exponential sweep generator: (a) displacement error (b) slope error (c) transmission error (d) none of these 5. Of the three types of errors that define deviation from linearity the following error is the largest in an exponential sweep generator: (a) displacement error (b) slope error (c) transmission error (d) none of these 6. In a UJT sweep generator, for the slope error to be small, the condition to be satisfied is that (a) the sweep amplitude should be very much larger than the supply voltage (b) the sweep amplitude should be very much smaller than the supply voltage (c) the UJT should have large hFE (d) the UJT should have small h FE 7. In a UJT sweep generator, for the slope error to be small, the condition to be satisfied is that (a) the time constant of the sweep circuit must be very much larger than the sweep duration (b) the time constant of the sweep circuit must be very much smaller than the sweep duration (c) the UJT should have large hFE (d) the UJT should have small h FE 8. The fictitious generator in a Miller’s sweep circuit is to be replaced by (a) an inverting amplifier with gain infinity (b) a noninverting amplifier with unity gain (c) sinusoidal oscillator (d) square wave generator 9. The fictitious generator in a bootstrap sweep circuit is to be replaced by (a) an inverting amplifier with gain infinity (b) a noninverting amplifier with unity gain (c) sinusoidal oscillator (d) square wave generator 10. For the sweep voltage generated to be linear in a bootstrap sweep circuit, it is essential that the following condition is satisfied: (a) The input resistance of the amplifier should be very much larger than the charging resistance. (b) The input resistance of the amplifier should be very much smaller than the charging resistance. (c) The input resistance of the amplifier should be equal to the charging resistance. (d) The input resistance of the amplifier should be zero.

1036

Electronic Devices and Circuits

11. The principle used for the deflection of the electron beam in a CRO using a voltage sweep generator is called (a) electromagnetic deflection (b) electrostatic deflection (c) slope error (d) magnetostatic deflection 12. The principle used for the deflection of the electron beam in a television receiver using a current sweep generator is called (a) electromagnetic deflection (b) electrostatic deflection (c) slope error (d) magnetostatic deflection 13. To generate a linear current sweep, the driving signal should be a (a) sinusoidal signal (b) square wave (c) pulse (d) trapezoidal waveform 14. A trapezoidal waveform is (a) a ramp followed by a step (c) a step followed by an exponential

(b) a step followed by a ramp (d) an exponential followed by a step

15. In an exponential sweep generator, the sweep amplitude is 10 V and the supply voltage is 1000 V, then the displacement error is 1 (a) 1% (b) % 8 (c) 10% (d) 100% 16. In a UJT sweep generator, t = 5 ms and Ts = 0.5 ms , then, es is (a) 100% (b) 50% (c) 10% (d) 20% 17. A UJT is a (a) charge-controlled device (c) current-controlled device

(b) voltage-controlled device (d) resistance-controlled device

18. For a UJT RB2 = 3 kΩ , RBB = 9 kΩ , then h is (a) 0.67 (b) 0.75 (c) 1 (d) 0.85

Short anSwer QueStionS 1. What is sweep circuit? 2. What are the different types of errors that define deviation from linearity? 3. For a UJT sweep circuit, of the three types of errors that define deviation from linearity, which error is the smallest? 4. For a UJT sweep circuit, of the three types of errors that define deviation from linearity, which error is the largest? 5. What is the main limitation of the UJT sweep circuit? 6. What is the principle used in Miller and bootstrap sweep generators in deriving a linear voltage sweep? 7. In the Miller’s sweep circuit, by what type of amplifier is the fictitious generated is represented?

Time-Base Generators

1037

8. In the bootstrap sweep circuit, by what type of amplifier is the fictitious generated is represented? 9. What is meant by the recovery time in a bootstrap sweep generator? 10. What is the principle used to generate a linear current sweep?

long anSwer QueStionS 1. Draw the circuit of a UJT sweep generator and explain its working. Derive the expression for its time period. Determine the slope error. 2. Explain the principle of linearizing an exponential sweep. Calculate the slope error of Miller’s and bootstrap sweep circuits. 3. Define the three errors that define deviation from linearity and obtain their interrelationship. 4. Draw the circuit of the Miller’s sweep circuit and explain its operation. Derive the expressions for the sweep duration and retrace time. Plot the waveforms. 5. Draw the circuit of the bootstrap sweep circuit and explain its operation. Derive the expressions for the sweep duration and retrace time and recovery time. Plot the waveforms. 6. Draw the circuit of a simple current sweep and explain its working. Explain the method to linearize the current sweep. Plot the waveforms.

unSolved problemS 1. For a UJT sweep circuit, R = 100 kΩ , C = 0.01 mF , VBB = 24 V , and VV = 2 V . The forwardconducting voltage of the diode is 0.7 V and h = 0.7. Calculate its frequency. 2. Design the UJT sweep generator circuit to oscillate at 5 kHz. The supply voltage is 24 V. The UJT has VV = 3 V , VF = 0.7 V, I P = 5 mA , I V = 5 mA , and h = 0.75. Find the peak-to-peak amplitude of the output. 3. For the Miller’s sweep circuit shown in Figure 19.20, VCC = 20 V , R = 5 kΩ, RC = 1 kΩ, 1 and C = 0.05 mF . The transistor has hfe = 60, hie = 1.1 kW , = 40 kΩ and hre = 2.5 × 10 −4. h oe Calculate (i) f and (ii) slope error. 4. For the bootstrap sweep generator shown in Figure 19.24, the supply voltages are ±18 V . RB = 100 kΩ , R = 20 kΩ, C = 0.05 mF , RE = 10 kΩ, C2 = 05 mF , Ts = 1000 ms, 1 Q2 has hfe = hFE = 100 , hic = 1 kΩ, = 40 kΩ, and hrc = 1. The transistor junction voltages hoc are negligible. The trigger signal has an amplitude of 5 V and duration of 1000 µs. Determine the sweep duration, sweep amplitude, and frequency. Also calculate the (i) retrace time, (ii) recovery time, and (iii) slope error. 5. Design the bootstrap sweep generator shown in Figure 19.24, VCC = 24 V and 1 hFE = 40. TS = 1000 ms and VEE = −12 V . Q2 has hfe = 50 , hic = 1 kΩ, = ∞ , and hrc = 1. hoc The transistor junction voltages are negligible. The trigger signal has a duration of 100 µs. RE = 3.3 kΩ . The slope error cannot be more than 1.5%. 6. For the current sweep generator shown in Figure 19.27, VCC = 18 V , L = 150 mH , RL = RCS = 10 Ω , Rd = 100 Ω, iL = I L ( max ) at t = 1 ms. Calculate the slope error.

20

INTEGRATED CIRCUITS

Learning objectives After reading this chapter, the reader will be able to      

20.1

Realize the need for integrated circuits (ICs) Learn about the classification of IC fabrication processes Understand the procedure to fabricate monolithic ICs Realize resistors, capacitors and transistors to fabricate an IC circuit Appreciate the need and methods of packaging ICs Understand MOS technology for greater circuit density

INTRODUCTION

An amplifier is an analog circuit, whereas an AND gate is a digital circuit. The wiring and the principle of working of such circuits have already been considered. However, as the complexity of the circuit increases, wiring the circuit using discrete components becomes complicated and also the reliability of the circuit so wired cannot be assured. Further, circuits using discrete components occupy more space. As such, they find no place in military and space applications, where the need is not only reliability, reduced cost, and increased speed of operation by minimizing the effects of stray capacitances but also miniaturization. This resulted in the development of microelectronics. A monolithic integrated circuit (IC) is fabricated on a single silicon chip, having a typical cross-section of 50 by 50 mil (1 mil = 0.001 in = 25.4 µm = 0.0254 mm), in which hundreds of diodes, transistors, resistors, capacitors are formed on a single substrate (mounting surface) and interconnected. The word monolithic is derived from the Greek words, monos (= single) and lithos (= stone). A monolithic IC is fabricated on a single chip.

20.1.1 Classification of ICs Integrated circuits are of three types: (i) monolithic, (ii) film, and (iii) hybrid. (i) Monolithic integrated circuits are those that are formed completely within a Silicon substrate. All the circuit devices and components are fabricated on a single substrate. Monolithic integrated circuits are commonly called as silicon chips. The monolithic implementation is very convenient for low-cost mass production. However, the main limitation is the range of component values and their tolerances. As such, this technology is more suitable in the fabrication of digital circuits and some analog circuits.

Integrated Circuits

1039

(ii) Film components are made of either conductive or nonconductive material that is deposited in desired patterns on a ceramic or glass substrate. Film technologies are used to fabricate passive circuit components such as resistors and capacitors. Film-integrated circuits are further classified as: (a) thin film and (b) thick film ICs. (a) In thin film technology, the passive circuit elements are deposited on an insulating substrate (ceramic or glass) of 0.001 mm. The most widely used methods are (1) vacuum evaporation and (2) cathode sputtering. (b) In thick-film technology, the various layers and their patterns are produced by screen printing of conducting and insulating materials on ceramic substrates. A thick film is a film of material with a thickness of approximately 0.01 mm. (iii) A hybrid circuit is essentially a combination of monolithic technology and thin-film technology. It retains the advantages in both the fabricating technologies. The primary advantage of hybrid microcircuits is design flexibility.

20.2 THE MONOLITHIC INTEGRATED CIRCUIT The substrate used in monolithic ICs is usually silicon, which becomes an active part of the IC. Glass or ceramic substrates are used only to provide support for the components. Through planar fabrication processes all circuit elements are simultaneously fabricated and interconnected on the same silicon chip. All the fabrication steps are performed at the surface of a silicon crystal, and all contacts lie in one plane; hence, the process is called planar fabrication process. Then, the following are the processes involved in the fabricating monolithic ICs: (i) substrate production, (ii) wafer preparation, (iii) epitaxial growth, (iv) oxidation, (v) photolithography, (vi) diffusion, (vii) metallization, and (viii) packaging. All the above processes are explained in detail hereunder: (i) Substrate Production: Integrated circuits are fabricated on semiconductor substrates that are produced by growing artificially cylindrical crystals of pure Silicon. To produce singlecrystal ingots, it is the Czochralski crystal growth process that is most often used (see Figure 20.1). Highly purified (99.99999%) polyRaise crystalline silicon is put in a quartz crucible. The Rotate crucible is then placed in a furnace and is heated to a temperature greater than 1420°C at which the silicon melts. A precisely controlled quantity of the dopant is added to the melt. A small single Seed crystal crystal rod of silicon called a seed crystal is lowered until it comes in contact with the molten silicon. Silicon ingot When the molten silicon is in contact with the seed Quartz crystal, it solidifies around the seed because the crucible: Rotate seed crystal is at a lower temperature than the Molten silicon molten silicon. The seed crystal is then rotated and raised very slowly as indicated by the arrow; Heating coil and at the same time, the crucible is rotated in opposite direction so as to produce ingots of circular cross-section and desired length. The diameter of the ingot is controlled by the pulling Figure 20.1 Czochralski crystal growth process

1040

Electronic Devices and Circuits

rate and the melt temperature. Typically, the crystals are of 25 mm in diameter and have a length of 250 mm. These values can vary depending on the requirements of the industry (ii) Wafer Preparation: The crystal is then cut by a diamond saw into thin slices called wafers of thickness 23–40 mil. The silicon wafers thus obtained have very rough surface due to slicing. Then, one side of the wafer is polSilicon crystal Wafers ished to give a mirror-smooth finish, whereas the other side is lapped to produce a flat surface. After this process of polishing and lapping, wafers of 16–32 mil thickness are produced. These serve as the base or substrate on which hundreds of ICs are produced (see Figure 20.2). The wafers can also be rectangular. Figure 20.2 Circular silicon wafers

20.2.1 Fabrication of an NPN Transistor (iii) Epitaxial Growth: The epitaxial process involves depositing a very thin layer (25 µm) of silicon to form an N-type uniformly doped crystalline region (epitaxial layer) on the P-substrate. For this, the wafers are placed in a diffusion furnace and are inductively heated to N-type epitaxial layer a temperature of 1,200°C. The gaseous mixture 25 µm of silicon and pentavalent atoms is introduced into the system through a control console, and 200 µm P-type substrate thus an N-type epitaxial layer is formed, on which all active and passive components of the IC are formed. Consider a rectangular wafer of Figure 20.3 Formation of epitaxial layer typical chosen dimensions (see Figure 20.3). (iv) Oxidation: SiO2 has the property of preventing the diffusion of almost all impurities through it, and therefore serves as a hard protective coating with thickness of the order of 0.02–2 µm, to prevent any contamination. In addition, by a process called selective etching and diffusion of impurities through well-defined windows in the SiO2, various components can be fabricated. In this oxidation process (also called thermal oxidation), SiO2 layer is grown by exposing the epitaxial layer to an atmosphere of oxygen at 1,000°C (Figure 20.4).

SiO2 layer 25 µm N-type epitaxial layer 200 µm P-type substrate

Figure 20.4 Formation of SiO2 layer

(v) Photolithography: It involves two processes:(a) photomasking and (b) photoetching. (a) In photomasking, first the artwork (lay out) is done to an enlarged scale and is then reduced to the actual dimensions of the chip. This artwork is then decomposed into several mask layers, each corresponding to a process step in the fabrication schedule, for example, a mask for base diffusion, another for collector diffusion, another for metallization, and so on.

Integrated Circuits

1041

(b) Photoetching is used for the removal of SiO2 from desired regions so that the desired impurities can be diffused. To achieve this, the wafer is coated with a film of photosensitive emulsion Kodak photoresist (KPR). The thickness of the film is in the range of 5,000–10,000 Å (1 Å = 0.1 nm). KPR is placed over the photoresist-coated wafer as shown in Figure 20.5(a) and is now exposed to ultraviolet light so that KPR becomes polymerized (hardened) beneath the transparent regions of the mask. The mask is then removed and the wafer is developed using trichloroethylene, a chemical that dissolves the unexposed/unpolymerized regions on the photoresist and leaves the pattern. The chip is immersed in the etching solution of hydrofluoric acid, which removes the SiO2 from the areas that are not protected by KPR as shown in Figure 20.5(b).

UV radiation

Polymerized photo resist

Mask SiO2 N-type epitaxial layer

SiO2 N-type epitaxial layer

P-substrate

P-substrate

(a) Masking and UV radiation

(b) Removal of SiO from areas which are not proteced by KPR

Figure 20.5 Steps in the photoetching process: (a) masking and UV radiation and (b) removal of SiO2 from areas that are not protected by KPR

(vi) Isolation Diffusion: The remaining SiO2 layer serves as mask for the diffusion of acceptor impurities. The wafer is now subjected to isolation diffusion at a temperature of about a 1,000°C and for an appropriate time period allowing P-type impurity (may be boron) to penetrate into the N-type epitaxial layer through the openings in SiO2 layer. A carrier gas, such as dry oxygen or nitrogen is normally used for sweeping the impurity to the hightemperature zone. The temperature and time period of diffusion are required to be carefully controlled. The process results in formation of N-type regions, known as the isolation islands, called so because they are separated by back-to-back P–N junctions that permit electrical isolation between various components of IC. Each electrical element is later on formed in a separate isolation island. The bottom of the N-type isolation island ultimately forms the collector of an N–P–N transistor. Isolation diffusion is controlled so as to cause high acceptor concentration P+ (typically NA = 5 × 1026 atoms/m3) in the region between the isolation islands. This concentration is much higher than that of P-type substrate. This is for preventing the depletion region of the reverse-biased isolation island-to-substrate junction from extending into P+ region and from possibly connecting two adjacent isolation islands. Two adjoining isolation islands are connected to the P-type substrate by a barrier capacitance or transition capacitance. The parasitic capacitance has two components: the capacitance C1 from the bottom of the N-type region to the substrate and capacitance

1042

Electronic Devices and Circuits

C2 from the sidewalls of the isolation islands to the P-region (Figure 20.6). The bottom component C1 is essentially due to step junction formed SiO by epitaxial growth and, therefore, varies as the square + root of the voltage V between the isolation region and P+ P C2 substrate (i.e. C1 is directly proportional to V ). The sideN wall capacitance C2 is associated with a diffused graded −1

C

Collector

Emitter Base

P-substrate 1 junction and hence varies as V 2 . The total capacitance is of the order of a few pF. After diffusion of impurities, Figure 20.6 Isolation diffusion the photoresist is removed with a chemical solvent (hot H2SO4) and mechanical abrasion (Figure 20.6). (a) Base diffusion: A new layer of SiO2 is grown over the entire wafer, and a new pattern of openings is formed using photolithographic technique. In these openings, P-type impurities such as boron SiO2 are diffused under regulated environments to form P P+ P-regions. This forms the base region of an N–P–N P+ transistor or as well as resistors, the anode of diode, N and junction capacitor (Figure 20.7). In this case, P-substrate the diffusion time is so controlled that the P-type impurities do not reach the substrate. The resistivity Figure 20.7 Base diffusion of the base layer is usually much higher than that of the isolation regions. SiO2 (b) Emitter diffusion: A layer of SiO2 is again formed N P+ P+ over the entire surface and openings in the P-type P regions, as shown in the figure, are formed again by N using masking and etching processes. The N-type P-substrate impurities such as phosphorous are then diffused through these windows under controlled environFigure 20.8 Emitter diffusion ments to form the transistor emitter (Figure 20.8). (vii) Metallization: In this process, a thin metal film layer of aluminum is deposited to make interconnections of the various components on the chip. The metallization is done by vacuum evaporation of aluminum and then selectively etching away the aluminum over the entire SiO2 surface. The base, emitter, and terminals can now be N P+ connected to various circuit components in the IC P+ P (Figure 20.9). N

20.2.2 Fabrication of the Diode

P-substrate

Integrated diode is constructed on similar lines as a bipolar Figure 20.9 Metallization transistor fabrication process. N-type epitaxial layer is grown on the P-type substrate. A thin layer of Silicon dioxide SiO2 is grown over the N-type layer. Then, P-type impurities are diffused into N-type layer. Once again the entire wafer is covered with Silicon dioxide. Using masking and etching techniques, the, contact surfaces for the device terminals are defined. The entire wafer is now covered by Aluminum layer and final mask defines the desired interconnection pattern. The excess Aluminum is removed by etching technique. This completes the fabrication process of diode (Figure 20.10).

Cathode

Anode

Integrated Circuits

1043

C 1 SiO2

1

2 2 SiO2

P N P-substrate

Figure 20.10 Fabrication of a diode

P N P-substrate

Figure 20.11 Diffusion capacitance

20.2.3 Fabrication of Capacitor Since a P–N junction has a capacitance, it suggests that capacitors may be produced by fabricating suitable PN junctions. The P- and N-regions form the capacitor plates and depletion region between them is the dielectric. The width of the depletion region and therefore, the junction capacitance also varies with change in reverse bias. Capacitors up to 100 pF can be fabricated using this procedure (Figure 20.11). The junction C capacitor type has a drawback that the value of 2 1 capacitance varies with the voltage. IC capacitors 2 1 may also be fabricated by utilizing the SiO2 surface SiO2 layer as a dielectric. A thin film of Aluminum acts as a top plate. The bottom plate consists of heavily doped N+ region, which is formed during either the N+ emitter diffusion in bipolar process or the implantaN tion of the drain and source regions in MOS process. The capacitance of MOS or junction capacitor is up P-substrate to about 100 pF (Figure 20.12).

20.2.4 Fabrication of Resistors

Figure 20.12 Thin film capacitor

The resistance of a semiconductor material can be controlled by varying the concentration of doping impurity. In the fabrication of resistors using IC technology, the value of the resistance can be controlled by varying the amount of doping as well as the depth of diffusion. Resistors of the order of kilo-ohms are formed during the base diffusion of the integrated transistor as the base is the high-resistivity region (Figure  20.13(a)). 2 For low resistance values, emitter region is 1 used as it has low resistivity. Since diffused SiO2 resistors can be processed while diffusing transistors, the diffusion technique is the P cheapest and, therefore, the most widely used. The resistance of diffused layer is N given by the following relation: R12= R =

rl rl = a Wt

P-substrate

Figure 20.13(a) Fabrication of IC resistor-emitter diffusion

1044

Electronic Devices and Circuits

where r = average resistivity of diffused layer, l = length of diffused layer, W = width of diffused layer, t = thickness of diffused layer, and a = cross-sectional area of diffused layer. The range of values obtainable with diffused resistors are limited by the size of the area required by the resistor. Practical range of resistance is 20 Ω–30 kΩ for an emitter-diffused resistor.

R12 1

l

2

(i) Straight resistor

1

2

t (ii) Serpentine resistor

2 W

1 2

A

1

2

2

1

1

2B (iii) Serpentine resistor

Figure 20.13(b) Various types of fabrication

To derive large resistors, the fabrication methods shown in Figure 20.13(b) can be used. Resistors for ICs can also be produced by using thin-film technique. In this process, a metal film is deposited on a glass or SiO2 surface. The resistance value can be controlled by varying the thickness, width, and length of the film.

20.3

FABRICATION OF A TYPICAL CIRCUIT AS A MONOLITHIC IC

Consider the circuit in Figure 20.14. 3 R 2 4 1 Q C

D 5

Figure 20.14 Circuit to be fabricated as a monolithic IC

Integrated Circuits

1045

The following are the steps for the fabrication of the circuit in Figure 20.14 as a monolithic IC. (i) Preparation of the Wafer: The starting material called the substrate is a P-type silicon wafer. The wafers are usually of 10 cm in diameter and 0.4 mm(L1~ 400 µm) thick. The resistivity is approximately 10 Ω-cm corresponding to concentration of acceptor atom, NA = 1.4 × 1015 atoms/cm3 (Figure 20.15). Layer 1 is the silicon substrate upon which the integrated circuit is fabricated.

NA = 1.4 x 1015 atoms/cm3

L1 = 400 µm

P-type substrate

Figure 20.15 Wafer preparation

(ii) Epitaxial Growth: An N-type epitaxial film (L2 = 5–25 µm) is grown on the P-type substrate as shown in Figure 20.16. This ultimately becomes the collector region of the transistor, or an element of the diode and diffused capacitor associated with the circuit. Therefore, in general, it can be said that all active and passive components are fabricated within this layer. The resistivity of N-type epitaxial layer is of the order of 0.1–0.5 Ω-cm. N-type

L2 = 5 to 25 µm NA = 1.4 x 1015 atoms/cm3

L1 = 400 µm

P-type substrate

Figure 20.16 Epitaxial growth

(iii) Oxidation: A SiO2 layer, L3 of thickness of the order of 0.02–2 µm is grown on the N-type epitaxial layer (Figure 20.17). SiO2 L3 =0.02-2 µm N-type

L2 = 5 to 25 µm NA = 1.4 x 1015 atoms/cm3 P-type substrate

L1 = 400 µm

Figure 20.17 Oxidation

(iv) Isolation Diffusion: As seen from the circuit in Figure 20.14, four components have to be fabricated; hence, we require four islands that are isolated. For this, SiO2 is removed from five different places using photolithographic technique (Figure 20.18). The wafer is next subjected to heavy P-type diffusion for a long time interval so that P-type impurities penetrate the N-type epitaxial layer and reach the P-type substrate. The areas under the SiO2 are N-type islands that are completely surrounded by P-type moats. As long as the PN junctions between the isolation islands are held at reverse bias, that is, the P-type substrate is held at a negative potential with respect to the N-type isolation islands, these

1046

Electronic Devices and Circuits

regions are electrically isolated from each other by two back-to-back diodes, providing the desired isolation. The concentration of acceptor atoms (NA ≅ 5 × 1020 cm−3) in the region between isolation islands is generally kept higher than the P-type substrate for which NA = 1.4 × 1015 atoms/cm3. This ensures that the depletion region of the reverse biased diode will not extend into P+ region to the extent of electrically connecting the two isolation islands. However, isolation diffusion may be the cause for a significant amount of barrier or transition capacitance. Diffusion of P-type impurities

SiO2 L3 =0.02-2 µm P+

Island1 N

P+

Island2 N

Island3 + P N

P+

Island4 + P N

L2 = 5 to 25 µm L1 = 400 µm

P-type substrate

Figure 20.18 Isolation diffusion

(v) Base Diffusion: A new layer of SiO2 is grown over the entire wafer, and a new pattern of openings is formed using photolithographic technique. Now, P-type impurities, such as boron, are diffused through the openings into the islands of N-type epitaxial silicon. The depth of this diffusion must be controlled so that it does not penetrate through the N-layer into the substrate. This diffusion is utilized to form base region of the transistor (Figure 20.19). SiO2 P+

P

N

P+

P

P+

N

P

P+

P

N

N

Transistor

Resistor

P+

P-substrate

Capacitor

Diode

Figure 20.19 Base diffusion

(vi) Emitter Diffusion: A new layer of SiO2 is again grown over the entire wafer and selectively etched to open a new set of windows, and the N-type impurity (phosphorus) is diffused through them. This forms transistor emitter and cathode region of diode. Windows (W1 and W2) are also etched into the N-region where contact is to be made to the N-type layer. Heavy concentration of phosphorus (N+) is diffused into these regions simultaneously with the emitter diffusion (Figure 20.20).

Integrated Circuits

N+

1047

N+

W1

W2 SiO2

P+

-

N

P+

P

N

+

N

P+

P+

P

P

P

N

N

N

Transistor

Resistor

P+

P-substrate

Capacitor

Diode

Figure 20.20 Emitter diffusion

(vii) Metallization: The N+ layer makes a good ohmic contact with the aluminum layer (L4 = 1μm). To realize the circuit in Figure 20.14, interconnections are made as shown in Figure 20.21.

2

Alumimum layer 1 L4=1µm

5

4

3

N+

P+

P+

SiO2 P+

P

P+

N+

P+

P N

N

P

P

N

N

Transistor

Resistor

P-substrate

Capacitor

Diode

Figure 20.21 Metallization and interconnections

(viii) Packaging: A large number of identical ICs are manufactured simultaneously on a silicon wafer. After the completion of the metallization process, the wafer is scribed with a diamond-tipped tool and separated into individual chips. Each chip is then mounted on a ceramic wafer and is attached to a suitable header. Next the package leads are connected to the IC chip by stitch bonding of 25 µ aluminum or gold wire from the terminal pad on the IC chip to the package lead.

1048

20.4

Electronic Devices and Circuits

PACKAGE TYPES OF ICs

Once the IC has been produced, it requires housing or a package that supports the electrical contacts that connect the device to a circuit board. The packaging protects the device from moisture, dirt, heat, radiation, or other sources and aids in its handling and connection into the 0.08 – 0.31 mils system in which the IC is used. In addition, the IC Metal contacts package acts as a mechanism to spread apart the connections from the tight pitch (center to center spacing of two parallel conductors) on the IC die Bond wire to the relatively wide pitch required by the printed 6 circuit board or PCB (Figure 20.22). The package acts as a bridge between the two sizes, effectively spreading apart the spacing from the IC chip Inside IC dimensions to the PCB dimensions. The three most common types of packages are (i) transistor-outline, (TO) package, (ii) flat Metal package, and (iii) dual inline package (DIP). package (i) Transistor-Outline Package: The transistor40 mils outline (TO) package can have leads PCB normally numbering between 2 and 12, with 10 being the most common for IC applications. TO-5 is a standardized metal semiconductor package that has a base Metal trace on PCB diameter of 8.9 mm, a cap diameter of 8.1 Figure 20.22 IC to PCB lead spacing mm, and a cap height of 6.3 mm. Once the IC has been attached to the header, bonding wires are used to attach the IC to the leads. Figure 20.23 shows an actual TO-5 with the cover removed. The cover provides the necessary protection for the device. TO-5 round packages are limited to 10 leads only. Metal Cap Header

Bonded leads 5

Tab Die and wire bonding

Leads

6

7

4

8

3

9 10

2

1

Tab

Bootom view

Figure 20.23 TO-5 package

(ii) Flat Package: Integrated circuits needed more leads to take full advantage of increasing device density. The flat packages are smaller and lighter than the round TO-5 packages. A flat package is a rectangular or square package with leads parallel to base plane attached on two opposing sides of the package periphery, Figure 20.24(a).This is the package used

Integrated Circuits

1049

for early ICs in military and space applications. The pitch on this package is 50 mils. The flat packs were rarely used in commercial applications because of expensive board processing. With larger circuit density Quad-flat packages are used (Figure 20.24(b)). 1 2

10 9

3

8

4

7 6

5

Top view TAB Top view

2 1 14 13 12 3 11 4 5 10 6 7 8 9

Top view (a)Flat package

(b)Quad-flat package

Figure 20.24 Flat packages

(iii) Dual Inline Package or DIP: DIPs are of plastic and ceramic. A DIP (or DIL) is a rectangular housing with two parallel rows of electrical connecting pins, both with 100 mil pitch. A DIP is usually referred to as a DIPn, where n is the total number of pins. Therefore, a package with two rows of seven vertical leads is a DIP14 (Figure 20.25). The number of leads can vary from 4 to 64. Many analog and digital integrated circuit types are available in DIP packages. Bonded Gold wire for connecting the chip to the lead frame

IC chip

Key for pin location 14 13 12 11 10 9

8

1

7

2

3

4

5

Top view

10 mils

Indexing notch Leads

Figure 20.25 DIP14 package

6

1050

Electronic Devices and Circuits

With increased circuit complexity, as in microprocessors, there is the need to provide more leads than could be put on a DIP package. This has lead to the development of higherdensity packages.

20.5

IC TRANSISTOR AMPLIFIER

A CE amplifier is shown in Figure 20.26. It has four circuit elements that can be fabricated and interconnected as shown in Figure 20.27. The components are seen to be fabricated in cascade. However, the chip dimensions are very small, and all the components are to be accommodated and interconnected in the limited area. Now consider the amplifier circuit in Figure 20.28, wherein another condenser C2 is connected at the output to block dc. Then, it is advisable to design the component layout in an optimum fashion.

VCC RL Vo Q Vs

C

RB G

Figure 20.26 Amplifier circuit

G

Vs C

P+

Vo

VCC RL

RB P+

P

N+

P+

P+ P

P

P N

P+

N

N

N

P-substrate Figure 20.27 IC fabrication and interconnections–cross section VCC VCC RL RL

N+

P Vo RB

C2 Q

Vs

P

C1

C1

RB N+

Vo C2

E B

Vs

C

Q G G TOP VIEW

Figure 20.28 Amplifier with component layout and wiring

Integrated Circuits

20.6

1051

FABRICATION OF NMOS ICs

A wafer of about 75–150 mm in diameter and 0.4 mm thick is doped with Boron with impurity concentration of 1015/cm3 to 1016/cm3. This forms the Polymerized photo-resist substrate. SiO2 of typically 1 µm thick is grown over the surface. The surface is now covered with the KPR layer that is then exposed to UV light through masking which SiO2 defines the regions into which diffusion is to take place. Areas exposed to UV radiations are polymerized (hardSi Substrate ened) and areas shielded by the mask remain unaffected. The unaffected areas are subsequently etched away along Figure 20.29 UV radiation and etching with SiO2. A window is formed as defined by the mask (Figure 20.29). Thin layer of SiO2

(i) The remaining photoresist is removed and a thin layer of SiO2 of 0.1µm is grown over the entire chip surface (Figure 20.30). (ii) Then polysilicon is deposited on the top of this thin SiO2 layer to form the gate structure (Figure 20.31).

SiO2 Si Substrate

Figure 20.30 Growing thin layer of SiO2 Thin layer of SiO2 Poly-Silicon SiO2 Si Substrate

Figure 20.31 Depositing polysilicon

(iii) Next, the photoresist coating and masking allows the polysilicon to be patterned. The thin oxide layer is then removed to form widows. The N-type impurities are diffused by heating the wafer to a high temperature and passing a gas containing the desired N-type impurity to form the source and drain. Aluminum is deposited over the chip surface to a thickness of typically 1 µm. This metal layer is then masked and etched to form the required interconnections (Figure 20.32). Source

Gate

Drain

Poly-Silicon SiO2 G

N+

N+ P-type bulk Si

Figure 20.32 NMOS device

S

D

1052

Electronic Devices and Circuits

20.6.1 Simple Fabrication of IC MOS Transistors To fabricate enhancement IC MOS transistor, only one diffusion step is required. In this method, two heavily doped N-type regions are diffused into a slightly doped P-type substrate. The two N-type regions are the drain and the source, respectively (Figure 20.33).This method of fabrication gives greater circuit density. S

S

D

N+

N+

G

D

SiO2 N+

P-Substrate

N+

P-Substrate

Figure 20.33 Diffusion of N+ regions

Figure 20.34 N-channel enhancement-type MOSFET

SiO2 layer is grown and holes are etched and metal contacts are provided to the drain, source, and gate terminals (Figure 20.34).

20.6.2 MOS Transistor as a Resistor Large values of resistance can be fabricated by using a MOS transistor as shown in Figure 20.35. The gate is tied to the drain. This becomes a CG configuration, for which the output resistance, Ro =

1 1 . If gm = 10 × 10 −6 A / V, then Ro = R = = 100 kΩ. gm 10 × 10 −6

VDD

D G S

Ro = 1/ gm

Figure 20.35 MOS resistor

Integrated Circuits

1053

Summary • An integrated circuit is a low-cost miniature electronic circuit that contains active components such as diodes and transistors and passive components such as resistors and capacitors, all fabricated on a single silicon chip. • Integrated circuits are of three types: (a) monolithic, (b) film, and (c) hybrid. • Monolithic-integrated circuits are those that are formed completely within a silicon substrate. All the circuit devices and components are fabricated on a single substrate • Film components are made of either conductive or nonconductive material that is deposited in desired patterns on a ceramic or glass substrate. Film technologies are used to fabricate passive circuit components such as resistors and capacitors • A hybrid circuit is essentially a combination of monolithic technology and thin film technology. It retains the advantages in both the fabricating technologies. • The following are the processes involved in the fabrication monolithic ICs: (i) substrate production, (ii) wafer preparation, (iii) epitaxial growth, (iv) oxidation (v) photolithography, (vi) diffusion, (vii) metallization, and (viii) packaging.

multiple ChoiCe QueStionS 1. How are monolithic ICs made? (a) On ceramic wafers (b) By batch processing on silicon wafers (c) As miniature assemblies of discrete parts (d) On aluminum wafers 2. What is the core process used in making monolithic ICs called? (a) Photolithography (b) Wave soldering (c) Electron-beam fusion (d) Acid etching 3. How are capacitors formed in monolithic ICs? (a) By forming PN junctions and reverse biasing them (b) By using transistors (c) Both (a) and (b) (d) Capacitors cannot be formed in ICs 4. Which type of IC combines several types of components on a substrate? (a) Monolithic (b) Silicon (c) Digital (d) Hybrid 5. A monolithic integrated circuit contains all of its components (a) on a ceramic substrate (b) in a single chip of silicon (c) on a miniature printed circuit board (d) on a printed circuit board 6. Monolithic IC consists of (a) only active components (c) both active and passive components

(b) only passive components (d) PCB with discrete components

1054

Electronic Devices and Circuits

7. The most popular form IC package is (a) thin film (c) monolithic

(b) thick film (d) hybrid

8. Oxidation, in IC fabrication, means (a) removing Si by using SiO2 (b) adding impurity atoms by heating (c) growing a protective layer of SiO2 on the surface of the silicon wafer (d) none of these 9. SiO2 layer in an IC acts as (a) a capacitor (c) a resistor

(b) an insulating layer (d) an inductor

10. The components mentioned in one of the options given below cannot be fabricated on IC (a) resistors (b) capacitors (c) transistors (d) large inductors

Short anSwer QueStionS 1. What is an integrated circuit? 2. List some of the major advantages of ICs over circuits with discrete components. 3. What are the basic IC manufacturing technologies? 4. What is a monolithic IC? 5. What are the basic processes involved in fabricating a monolithic IC using planar technology? 6. What are the two processes involved in photolithography? 7. Define the process of diffusion. 8. What is metallization? 9. What are the three most common types of IC packages? 10. What are the two important properties of SiO2?

long anSwer QueStionS 1. Explain, in detail, the processes involved in the fabrication monolithic ICs. 2. Explain the three common types of packaging methods used in ICs.

21

555 TIMER AND APPLICATIONS

Learning objectives After reading this chapter, the reader will be able to � � � � �

21.1

Understand the principle of operation of IC 555 timer Learn the principle of working of 555 timer as a monostable circuit Use 555 timer in an astable circuit to derive fixed and variable duty cycles Appreciate the numerous other applications of 555 timer such as voltage-controlled oscillator, frequency divider, bistable circuit, etc. Understand the advantage of using 556 timer

INTRODUCTION

A 555 timer is a versatile linear IC capable of producing accurate time delays and oscillations. The supply voltages range from 5 to 18 V. SE 555 operates over a temperature range of −55 to 125°C and is used in military applications. NE 555 is a general-purpose commercial device that operates over a temperature range of 0 to 70°C. These ICs are manufactured using both bipolar and CMOS technologies. The IC can source or sink a current of the order of 200 mA. The IC finds applications in analog, digital or mixed signal applications. The basic building blocks of the 555 timer are two-voltage comparators C1 and C2, an RS flip flop, an inverting output buffer and 2 a discharge transistor Q1.The reference voltage to C1 is set at VCC at the inverting input and that 3 1 for C2 is set at VCC at the noninverting input through a voltage divider network comprising three 3 identical resistors R1 , typically of value 5 kΩ. Figure 21.1(a) shows the functional block diagram, and Figure 21.1(b) shows the pin diagram of a 555 timer.

21.1.1 Pin Details Pin 1 is the ground or reference pin. The circuit is operated from positive- supply voltages. All the voltages are measured with respect to the ground terminal. Pin 2 is the trigger input terminal. This is the inverting input terminal of comparator C2 and is used to set the flip flop. Initially, pin 2 is HIGH, which in turn causes the output Q to go HIGH. Triggering is accomplished by the application of a pulse of short duration that takes pin 2 to a 1 voltage level below . The trigger pulse must be of shorter duration than the time interval deter3 mined by the external R and C.

1056

Electronic Devices and Circuits

8

VCC

6 Threshold

R1 Control 5 voltage 1

2/3 VCC

+ C � 1

7 Discharge

R

R1

3 VCC R1

Q1 Flip flop

+ C � 2

Q

3 Output GND 1

S

Trigger 2 Q2

Output 3

4 Reset

2 Trigger

555

7 Discharge 6 Threshold

Rest 4

VREF Ground 1

8 VCC

5 Control (b)

(a) Functinal block diagram

(b) Pin diagram

Figure 21.1 555 timer: (a) functional block diagram and (b) pin diagram

Pin 3 is the output terminal. The output of the 555 comes from a high-current totem-pole stage. The logic level at this pin Q is the inverse of the logic state of the flip flop, Q. The load is connected to the output terminal in two ways: (i) between pin 3 and ground pin (pin 1), in which case the load is called the normally OFF load and the timer is said to be used as a current source (Figure 21.2(a)) and (ii) between pin 3 and supply pin (pin 8), in which case the load is called the normally ON load and the timer is said to be used as a current sink (Figure 21.2(b)). VCC

VCC

ISink 8

8 RL

555

1

(a)

3

ISource RL

555

3

1

(b)

Figure 21.2 555 timer as (a) current source and (b) current sink

Pin 4 is the reset pin and is used to reset the flip-flop. In the normal operating mode, the reset transistor, Q2, is OFF with its base held HIGH. When the base of Q2 is grounded, it turns ON, providing base drive to Q1, turning it ON. This discharges the timing capacitor, resets the flip-flop and drives the output low. The reset overrides all other functions within the timer. When not used, the reset pin is tied to VCC (pin 8) to avoid false triggering

555 Timer and Applications

1057

Pin 5 is the pin to which external control voltage is applied, which is directly connected to the 2 inverting input terminal of the comparator C1 at which the voltage level is VCC . The function of 3 this terminal is to control the threshold and trigger levels. By applying a voltage to this pin, it is possible to vary the timing of the device independent of the external RC network. When not used, pin 5 is connected to ground through a 0.01 µF for noise immunity. Pin 6 is the threshold input pin that is connected to the non-inverting input terminal of comparator C1. The amplitude of voltage applied to this terminal is used to reset the flip flop. Q goes 2 HIGH when the voltage at this pin goes above VCC . 3 Pin 7 is called the discharge pin and is the collector terminal of Q1. When Q1 is ON pin 7 is shorted to ground and discharges the timing capacitor connected between pin 7 and ground. When the transistor is OFF, the capacitor charges at a rate determined by the external R and C. Pin 8 is the pin to which the positive-supply voltage VCC is applied with respect to ground. The supply voltage ranges from +5 V to +18 V The operation of a 555 timer depends on an external capacitor C to determine the ON–OFF time intervals of the output pulses. It takes a finite period of time for C to charge or discharge through a resistor R.

21.2

OPERATING MODES OF 555 TIMER

The 555 timer can be operated in three modes: (i) Monostable multivibrator that generates a single pulse of a fixed time duration, T each time a trigger pulse is applied. It is also used to generate delays. (ii) Astable multivibrator that is essentially a square-wave oscillator. The frequency of the square wave and its duty cycle depend on the external RC components. (iii) Time delay is slightly different from the monostable mode of operation. In the monostable mode, a pulse is generated immediately after the trigger is applied. However, in the time delay mode, the output is not allowed to change state immediately after triggering, but only after a predetermined time interval.

21.2.1 555 Timer as a Monostable Multivibrator The circuit arrangement of a 555 timer used as a monostable multivibrator is shown in Figures 21.3 and 21.4. R and C are the external timing components. The truth table for the RS flip-flop is shown in Table 21.1. Table 21.1 Truth table of the RS flip-flop _ S R Q Q – 0 0 Q Q

Comment No change

0

1

0

1

Reset state

1

0

1

0

Set state

0

0

?

Unpredictable

1058

Electronic Devices and Circuits VCC 8

6

7 R

R1

+ C − 1

5

Reset

R1

Q1 Flip flop

+ C − 2

R1

+ Q

3

Q

Set

+ RL

0.1µF Q2

1

2

VCC

VREF

Vo −

C

Vc −

4 Reset

0

Figure 21.3 555 timer as a monostable multivibrator

Monostable Circuit Operation The behavior of the circuit at various time instants is 1 presented below: The output of C2 goes HIGH only when the voltage at pin 2 is below VCC. At 3 1 t = 0−, inverting input of C2 is at VCC and the noninverting input is at VCC. As such, set = 0. The 3 2 output of C1 goes HIGH only when the voltage at pin 6 is above VCC . But pin 6 (the noninverting 3 2 input of C1) is at 0 V, and the inverting input is at VCC . Therefore, reset = 0. As a result, Q is 3 HIGH. Consequently, Q1 is driven into saturation, and the voltage across C, Vc = VCE (sat ) ≈ 0. As Q is HIGH, Q, the output of the inverting buffer at pin 3, is 0. 1 At t = 0+, when the trigger is applied, inverting input of C2 goes below VCC and the nonin3 1 verting input is at VCC. As such, set = 1. The output of C1 is 0, that is, reset = 0. As a result, Q is 3 LOW. Consequently, Q1 is driven into the OFF state, and the voltage across C, Vc increases as a function of time and tries to reach VCC . As Q is LOW, the output of the inverting buffer at pin 3 is VCC (Figure 21.5). 2 However, at t = T , when Vc is slightly larger than VCC , reset = 1. As the trigger signal is no 3 longer present at pin 2, set = 0. As a result, Q is HIGH. Consequently, Q1 is once again driven into the ON state, and the voltage across C, Vc almost abruptly falls to 0. As Q is HIGH, the output of the inverting buffer at pin 3 is 0. It must be noted here that the trigger duration must be smaller than the time duration T of the pulse.

555 Timer and Applications

1059

The waveforms are shown in Figure 21.5. VCC

4 VCC

8

2

0

R 7 NE 555 +

6 3

+

C V c

5

Normally

Vo

RL

1

OFF load

0.1mF

−

−

Figure 21.4 Monostable multivibrator VCC Trigger 1/3 VCC 0

VCC 2/3 VCC

Vc T

0

VCC Vo 0

Figure 21.5 Waveforms of the monostable multivibrator

Calculation of the time period, T When trigger is applied Q1 is OFF and C charges through R. The voltage Vc across C is given by the following relation: −t

Vc ( t ) = Vf − (Vf −Vi ) e RC

(21.1)

1060

Electronic Devices and Circuits

From Figure 21.5, Vf = VCC and Vi = 0. Substituting in Eqn. (21.1), we obtain −t

Vc ( t ) = VCC − (VCC − 0 ) e RC 2 At t = T ,Vc (t ) = VCC 3 Therefore,

−T  2 VCC = VCC 1 − e RC 3 

  

−T

(21.2)

T

1 or e RC = 3 3

e RC =

T = RC ln ( 3 ) or

(21.3)

T = 1.1RC

The value of R cannot be more than Rmax . Rmax is determined by the threshold current, I th . which is the minimum current required to trip the threshold comparator, C1 and is typically 0.25 µA. Rmax For VCC = 15V, Rmax = For VCC = 5V, Rmax =

2 VCC − VCC 3 = I th

(21.4)

15 − 10 = 20 MΩ 0.25 × 10 −6

5 − 3.33 = 6.6 . MΩ 0.25 × 10 −6

Figure 21.6 shows the time delay T for different combinations of R and C. For example, if R = 10 MΩ and C = 10 µF, then T = 100 s. 100 R=1

10

100

10

1 10 1=1kΩ

C in µF

1

1=1MΩ 0.1

0.01

0.001 10µs 100µs 1ms

10ms 100ms 1s

10s

100s

T-time delay

Figure 21.6 Time delay T for different combinations of R and C

555 Timer and Applications

1061

Example 21.1 In the monostable circuit shown in Figure 21.4, determine the value of R that generates an output pulse of 100 ms, if C = 0.1 µF. Solution: T = 1.1RC R=

100 × 10 −3 = 1.1× 0.1× 10 −6 R

100 × 10 −3 = 909.09 kΩ 1.1× 0.1× 10 −6

21.2.2 555 Timer as Astable Multivibrator The basic configuration of an astable multivibrator is shown in Figure 21.7. An astable multivibrator does not need external trigger pulses. As such pin 2 is tied with pin 6 so that the timer triggers itself during operation. Further, R is split into two resistors RA and RB, and pin 7 connected 1 2 to the junction of RA and RB. C charges and discharges between trigger levels VCC and VCC . 3 3

Operation of the Astable Multivibrator Assume that at t = 0, the output at pin 3 is HIGH. is LOW. Hence, Q1 is OFF. C charges through RA and RB with the time constant, 2 t c = ( RA + RB )C . At t = T , when the voltage Vc across C reaches VCC ,the flip-flop resets and the 3 1 charge on C falls with a time constantt d = RBC. However, when Vc = VCC, the flip flop once again 3 Q

sets and C once again charges and so on. The waveforms are shown in Figure 21.8. VCC 4

8

RA 7 RB

NE 555

6 +

+ Normally

Vo

2

3 RL

1

C V c

5

OFF load

0.1µF

−

−

Figure 21.7 A stable circuit

Calculation of the Frequency T1, T2, and T are calculated using Figure 21.8. Calculation of T 1 The voltage Vc (t ) at any instant of time is calculated using Eqn. (21.1). −t

VC (t ) = Vf − (Vf − Vi ) e t

C

(21.5)

1062

Electronic Devices and Circuits

1 Vf = VCC and Vi = VCC 3 Substituting in Eqn. (21.5), we obtain Vc (t ) = VCC

−t

1   − VCC − VCC  e t   3

(21.6)

C

2 t = T1, Vc ( t ) = VCC 3

At

Substituting in Eqn. (21.6), we obtain −T1

2 1   VCC = VCC − VCC − VCC  e t   3 3

−T1

1 2 VCC = VCC e t 3 3

C

C

T1 = 0.693t C = 0.693 ( RA + RB )C 2

(21.7)

3 VCC

Vc 1 VCC 3

T2

T1

t

VCC Vo t

0 T

Figure 21.8 Waveforms of the astable

Calculation of T 2 Using Eqn. (21.5), Vc ( t ) = Vf − (Vf −Vi ) e

−t td

(21.8)

2 Vf = 0 and Vi = VCC 3 Substituting in Eqn. (21.5), we obtain −t

2   Vc ( t ) = 0 −  0 − VCC  e t 3  

d

(21.9)

555 Timer and Applications

1063

1 t = T2 , Vc ( t ) = VCC 3

At Substituting in Eqn. (21.9), −T2

1 2 t VCC = VCC e 3 3

d

T2 = 0.693t d = 0.693RBC

(21.10)

T = T1 + T2 = 0.693 ( RA + RB )C +0.693RBC = 0.693 ( RA + 2RB )C

(21.11)

f =

1 1 1.44 = = T 0.693 ( RA + 2RB )C ( RA + 2RB )C

Duty cycle = D =

0.693 ( RA + RB ) C ( RA + RB ) × 100 T1 = = T 0.693 ( RA + 2 RB ) C ( RA + 2 RB )

(21.12)

(21.13)

Since T1 > T2, D is always greater than 50%. Example 21.2 For the astable multivibrator shown in Figure 21.7,RA = 10 kΩ, RB = 20 kΩ, and C = 0.1 µF. Calculate T1, T2, f , and D. Solution: T1 = 0.693 ( RA + RB )C = 0.693 (10 + 20 )103 × 0.1× 10 −6 = 2.08 ms T2 = 0.693RBC = 0.693 × 20 × 103 × 0.1× 10 −6 = 1.39 ms T = T1 + T2 = 2.08 + 1.39 = 3.47 ms 1 1000 = = 288.2 Hz T 3.47 T 2.08 D = 1 × 100 = × 100 = 60% T 3.47 f =

Figure 21.9 gives f for different ( RA + 2RB ) and C.

Astable Multivibrator with 50% Duty Cycle The main limitation of the astable circuit shown in Figure 21.7 is that the duty cycle is always more than 50 per cent. To derive duty cycle of 50 per cent, a slight modification to the circuit is made as shown in Figure 21.10. Two diodes D1 and D2 are added. While charging, D1 is ON and D2 is OFF. The charging time constant t C = RAC and T1 = 0.693RAC . While discharging, D2 is ON and D1 is OFF. The discharging time constant t d = RBC and T2 = 0.693RBC . Hence, D =

T1 × 100. If RA = RB , D = 50%. T1 + T2

1064

Electronic Devices and Circuits 100

10

1 C in µF

1 100

10

1 0.1 RA + 2RB

10

0.01

0.001 0.1

1

10

100

1k

10k

100k

f in Hz

Figure 21.9 Frequency in terms of ( RA + 2RB ) and C

Astable Multivibrator with Variable Duty Cycle Figure 21.11 shows an astable circuit with variable duty cycle. A pot R3 is included in the circuit and depending on the position of the center tap RA and RB are decided.

VCC

4

RA

8 7

RA = RB RB D1

NE 555 6

D2

2 + Vo

+

3 5 RL

C

1

Vc

0.1µF −

−

Figure 21.10 Astable with 50% duty cycle

555 Timer and Applications

1065

(i) When the center tap of the pot R3 is at X, then RA = R1 and RB = R2 + R3 T1 = 0.693RAC = 0.693R1C T2 = 0.693RBC = 0.693 ( R2 + R3 )C

and

Dmin =

0.693R1C R1 = . 0.693 ( R1 + R2 + R3 )C R1 + R2 + R3

(ii) When the center tap of the pot R3 is at Y, then RA = R1 + R3 and RB = R2 T1 = 0.693RAC = 0.693 ( R1 + R3 )C and

T2 = 0.693RBC = 0.693R2C Dmax =

0.693 ( R1 + R3 )C 0.693 ( R1 + R2 + R3 )C

=

( R1 + R3 ) ( R1 + R2 + R3 ) VCC

4

R1

8

RA

X 7 R3 D1

NE 555

Y RB

R2

6 D2 2 +

+

3 C

5 Vo

RL

1

Vc

0.1µF −

−

Figure 21.11 Astable with variable duty cycle

Example 21.3 For the astable circuit shown in Figure 21.11, R1 = R2 = R3 = 5 KΩ, and C = 0.1 µF. Find the maximum and minimum values of D and value of f. Solution: (i) When the center tap of the pot R3 is at X, then

1066

Electronic Devices and Circuits

RA = 5 kΩ and RB = 5 + 5 = 10 kΩ T1 = 0.693RAC = 0.693 × 5 × 103 × 0.1× 10 −6 = 0.35 ms T2 = 0.693RBC = 0.693 × 10 × 103 × 0.1 × 10 −6 = 0.693ms

and

T = T1 + T2 = 0.35 + 0.693 = 1.043 ms 0.35 × 100 = 33.56% 1.043 (ii) When the center tap of the pot R3 is at Y, then Dmin =

RA = R1 + R3 and RB = R2 T1 = 0.693RAC = 0.693 × 10 × 103 × 0.1× 10 −6 = 0.693 ms and

T2 = 0.693RBC = 0.693R2C = 0.693 × 5 × 103 × 0.1× 10 −6 = 0.35 ms T = T1 + T2 = 0.693 + 0.35 = 1.043 ms 0.693 × 100 = 66.44% 1.043 1 1000 f = = = 959 Hz T 1.043

Dmax =

Voltage-Controlled Oscillator An astable multivibrator is a square-wave generator with a fixed frequency as RA, RB, and C are unique for the circuit. If f is to be changed, these component values need to be changed. However, this astable circuit can be modified to change the frequency of oscillations by just changing an externally connected voltage. Then, the circuit is called the voltage-controlled oscillator (VCO) or voltage-to-frequency converter or VFC (see Figure 21.12). VCC

4

RA

8 7

Vo

3 RB 555

R

6 2

5 + V

+ C V c

1

−

Figure 21.12 Voltage-controlled oscillator

−

555 Timer and Applications

1067

In the astable multivibrator (see Figure 21.10), the reference voltage for the comparator C1 is 2 VCC . This is called the trip point of C1 and is termed as the upper trip point (UTP). Similarly, the 3 1 reference voltage for the comparator C2 is VCC. This is called the trip point of C2 and is termed 3 as the lower trip point (LTP). 1 LTP = UTP. In Figure 21.11 the control pin 5 is connected to ground through a 0.1 µF 2 condenser. If alternately, pin 5 is connected to an external voltage source V, this changes the trip points. From Figure 21.3, it can be noted that if the voltage at pin 5 (the inverting input of C1) is V V V then the voltage at the noninverting input of C2 is . Consequently, C charges from to V dur2 2 V ing T1 and discharges from V to during T2 (Figure 21.13). The frequency of oscillations can be 2 calculated as shown under. V

Vc 1 V 2

T1

T2

t

VCC Vo t

0 T

Figure 21.13 Waveforms of the VCO

Calculation of T 1 The voltage Vc (t ) at any instant of time is calculated using Eqn. (21.5). Vf = VCC and Vi =

V 2

Substituting in Eqn. (21.5), we obtain −t

V  Vc (t ) = VCC − VCC −  e t  2

(21.14)

C

At t = T1, Vc ( t ) = V Substituting in Eqn. (21.14), we obtain −T1

V = VCC

V  − VCC −  e t  2

C

−T1

V t  VCC −  e = VCC − V 2 C

1068

Electronic Devices and Circuits

−T1

2VCC − V t e = VCC − V 2 C

T1

et = C

2VCC − V 2 (VCC − V )

T1 = t c log n

2VCC −V 2VCC −V = ( RA + RB )C log n 2 (VCC −V ) 2 (VCC −V )

(21.15)

Calculation of T 2 Using Eqn. (21.8), we obtain Vc (t ) = Vf − (Vf − Vi ) e

−t td

Vf = 0 and Vi = V Substituting in Eqn. (21.8) Vc (t ) = 0 − (0 − V ) e t = T2 , Vc ( t ) =

At

−t td

(21.16)

V 2

Substituting in Eqn. 21.16 −T2

V = Ve t 2

d

T2 = 0.693t d = 0.693RBC T = T1 + T2 = ( RA + RB )C log n

f =

1 = T

(21.17) 2VCC −V + 0.693RBC 2 (VCC −V )

1 2VCC −V + 0.693RBC ( RA + RB )C log n 2 (VCC −V )

(21.18)

(21.19)

Example 21.4 For the VCO circuit shown in Figure 21.12,R1 = R2 = R3 = 5 kΩ, VCC = 15 V, and C = 0.1 µF. Calculate f if (i) V = 5 V and (ii) V = 10V. Solution: (i) T1 = ( RA + RB )C ln

( 2VCC − V ) 2 (VCC − V )

= (5 + 5) × 103 × 0.1 × 10 −6 ln

(30 − 5) = 0.223 ms 2 (15 − 5)

T2 = 0.693RBC = 0.693 × 5 × 103 × 0.1× 10 −6 = 0.35 ms T = T1 + T2 = 0.223 + 0.35 = 0.573 ms

555 Timer and Applications

f = (ii) T1 = ( RA + RB )C ln

1069

1 1000 = = 1745.2 Hz T 0.573

( 2VCC − V ) . 2 (VCC − V )

= (5 + 5) × 103 × 0.1 × 10 −6 ln

(30 − 10) = 0.693 ms 2 (15 − 10 )

T2 = 0.693RBC = 0.693 × 5 × 103 × 0.1 × 10 −6 = 0.35 ms T = T1 + T2 = 0.693 + 0.35 = 1.043 ms f =

1 1000 = = 958.8 Hz T 1.043

Alternately, T1 = ( RA + RB ) C ln

(VCC − 0.5V ) (VCC − V )

= (5 + 5) × 103 × 0.1 × 10 −6 ln

(15 − 5)

(15 − 10)

= 0.693 ms

T2 = 0.35 ms T2 = T1 + T2 = 0.693 + 0.35 = 1.043 ms f =

1 1000 = = 958.8 Hz T 1.043

21.2.3 Some other Applications A few more application of 555 timer are discussed here.

Triggered Linear Ramp Generator A linear triggered sweep generator is shown in Figure 21.14. For the sweep to be linear C is charged with a constant current I, Figure 21.14(a). VCC RE

VCC VCC 0

2

VCC 0

8

4

8

4

+ VE

2

I

7

NE 555

R1 VBE −

7 NE 555 6

3

+

+ Vo

C Vc

5

1

0.1µF

−

6

3

+

−

1

+ C Vc

5

Vo −

(a)

0.1µF (b)

Figure 21.14 Triggered linear sweep generator

VB R2

IC

−

1070

Electronic Devices and Circuits

The circuit in Figure 21.14(a) is essentially a monostable circuit shown in Figure 21.4, where R is replaced by a constant current I. The constant current, I = I C in practice, is supplied by transistor Q (current mirror), Figure 21.14(b). From Figure 21.14(b) IC =

VCC −VE R

VB = VCC

(21.20)

R2 R1 + R2

(21.21) (21.22)

VE = VB + VBE ∆Vc =

IC ∆t C

2 ∆Vc = VCC and ∆t = Ts 3

I 2 ∴ VCC = C Ts 3 C Sweep speed S =

(21.23)

IC C

(21.24)

where IC is in Amps and C is in µF. Therefore, 2 VCC = STs 3 or

Ts =

(21.25)

2 VCC 3 S

(21.26)

The waveforms are the same as shown in Figure 21.5.

Free-running Linear Ramp Generator Figure 21.15 shows a free-running linear ramp generator. The circuit in Figure 21.15 is the same as that shown in Figure 21.14(b), except for the fact that pin 2 is tied to pin 6, to operate in the astable mode. The transistor Q is used as a current mirror. The sweep waveform is also shown in Figure 21.15. I = IC =

VCC −VD R

(21.27)

From Figure 21.15, ∆Vc =

IC ∆t C

1 ∆Vc = VCC and ∆t = Ts 3

I 1 ∴ VCC = C Ts 3 C Ts =

VCC C 3 IC

(21.28)

555 Timer and Applications

fs =

3I C 1 = Ts VCCC

1071

(21.29)

VCC + VD

8

4

VE

D

−

R

Q IC

7 NE 555 3

I

6

+

5

C Vc

+ Vo

1

2/3 VCC

2

0.1µF

−

1/3 VCC

−

Ts

Figure 21.15 Free-running linear sweep

555 Timer as Schmitt Trigger The output of the 555 timer is VCC when the voltage at pin 1 2 VCC, and its output is 0 when the voltage at pin 6 is VCC. The two comparator inputs 3 3 2VCC VCC + 3 = VCC through a voltage divider R and (pins 2 and 6) are tied together and biased at 3 2 2 V R. For the circuit to work satisfactorily, the input signal must swing at least by CC above and 6 VCC VCC VCC VCC VCC VCC 2VCC below (since and + = ). If the input is a sinusoidal, the output − = 2 2 6 3 2 6 3 is a symmetric square wave. The circuit of the Schmitt trigger and its waveforms are shown in Figures 21.16 and 21.17, respectively. 2 is

VCC R 4

8

2 0.1 µF

3

555 +

Vi

½ VCC

+

6 1

5

Vo

R 0.1 µF

−

−

Figure 21.16 555 timer as a Schmitt trigger

1072

Electronic Devices and Circuits

2/3VCC Vi

1/2VCC

t

1/3VCC VCC Vo t

0

Figure 21.17 Waveforms

555 Timer as Bistable Circuit Figure 21.18 is the bistable circuit and Figure 21.19 shows the waveforms. The trigger pin 2 and the reset pin 4 are held at HIGH level through pull-up resistors R1and R2 . The threshold pin 6 is at ground potential. When the switch is in position S, the voltage at pin 2 falls to zero and a negative pulse is seen to be applied at pin 2 and the flip-flop is set and the output at pin 3 is HIGH. The output continues to remains HIGH till the reset trigger is applied. When the switch in position R, the flip-flop is reset and the output goes LOW. The result is a pulse of duration T at pin 3 and the duration of this pulse depends on the spacing between the set and reset trigger pulses.

VCC C R1

R2

Decoupling condenser

RL

8 2

1µF

3 555

4 S

R

6

1

5 0.1µF

Figure 21.18 Bistable circuit

555 Timer as a Pulse Width Modulator Pulse width modulation (PWM) is an analog modulation technique in which the width of the pulse is varied in accordance with instantaneous amplitude of the modulating signal. The PW modulator circuit using 555 timer is shown in Figure 21.20, and the waveforms are shown in Figure 21.21.

555 Timer and Applications VCC Set trigger

0 VCC

Reset trigger

0

VCC Vo 0

Figure 21.19 Waveforms

VCC

4 Modulating signal

+

R

8

5 7

vm NE 555 − VCC

6 3

2

C

+

Trigger

1 Vo −

Figure 21.20 Pulse width modulator

Modulatin Signal vm

t

PWM output Vo

t

Figure 21.21 Waveforms

1073

1074

Electronic Devices and Circuits

If pin 5 is connected to ground through a 0.1 µF, the circuit in Figure 21.20 is basically a monostable circuit for which a train of trigger pulses is applied at pin 2. The output at pin 3 under this condition will once again be a pulse train whose duration will be 1.1 RC. In the absence of the 2 modulating signal, the trip point of the upper comparator is VCC . However, when a sinusoidal 3 modulating signal,vm is applied at pin 5, the trip point of the upper comparator changes accordingly, and the width of the output pulses changes as per the amplitude of the modulating signal. The output of the circuit is a PWM signal. 2 The pulse width in the absence of the modulating signal, T = 1.1RC and the UTP = VCC . 3 With the modulating signal present, UTP varies between UTPmax and UTPmin. UTPmax = UTP + vm and UTPmin = UTP − vm The pulse width is calculated as presented below: −t

Vc ( t ) = Vf − (Vf −Vi ) e RC Vf = VCC and Vi = 0 Therefore, −t

−t

Vc ( t ) = VCC − (VCC − 0 ) e RC =VCC −VCC e RC At

t = T ,Vc (T ) = UTP

Therefore −T

UTP = VCC −VCC e RC

−T

VCC e RC = VCC − UTP

−T

e RC = 1 −

UTP VCC

 UTP  T = −RC ln 1 − VCC  

(21.30)

 UTPmax  Tmax = −RC ln 1 − VCC  

(21.31)

 UTPmin  Tmin = −RC ln 1 − VCC  

(21.32)

555 Timer as Frequency Divider Let the monostable circuit shown in Figure 21.4 be triggered by a square wave instead of a pulse. Let it also be assured that the time period T of the monostable is larger than the time period TP of the trigger signal. The monostable is triggered by the first negative edge of the square wave and a pulse of duration T is generated (Figure 21.22). The second and the third negative edges cannot change the state of the monostable output. However, the fourth negative edge again triggers the monostable and a new pulse is generated. The square

555 Timer and Applications

1075

wave trigger and the output of the monostable are divided in the ratio 3:1. In a divider, the time period of the monostable, TM is assumed to be 20 per cent larger than T. TM = {0.2 + ( n − 1)}TP

(21.33)

For n = 3, TM = {0.2 + ( 3 − 1)}TP = 2.2Tp TP VCC Trigger 0 1

3

2

4

3 cycles VCC Vo

0.2 T

T

0

TM 1 cycle

Figure 21.22 Waveforms of the frequency divider

555 Timer as FSK Generator In an FSK generator, a 1 is identified by a frequency f1 and a 0 is identified by a different frequency f2. The FSK generator is an astable circuit, but a transistor Q with collector resistance RC is included as shown in Figure 21.23. When the input is 1, Q is OFF and the circuit is simply the astable circuit seen in Figure 21.7 having a frequency f1 =

1.44 ( RA + 2RB )C

(21.34)

Alternately, when the input is 0 Q is ON and RA and RC are in parallel and the effective resistance is R = RA || RB . Hence, the new frequency f2 is f2 =

1.44

(21.35)

( R + 2RB )C

Example 21.5 For the FSK generator shown in Figure 21.23, RA = 50 kΩ, RB = 42.25 kΩ, RC = 75 kΩ, and C = 0.01 µF. Find f1 and f2 . Solution: f1 = R=

1.44

=

1.44

( RA + 2RB )C (50 + 2 × 42.25 )103 × 0.01×10−6 RA RC 50 × 75 = = 30 kΩ RA + RC 125

= 1070 Hz

1076

Electronic Devices and Circuits

1440 = 1257 Hz (30 + 2 × 42.25) × 0.01

f2 =

VCC Rs 4

RA

8

Q 0 1 0 1

7 RC

RB NE 555

2

3

+

6

C

5 Vo

1 0.1µF

−

Figure 21.23 555 timer as FSK generator

21.2.4 556 Dual Timer A 556 timer is two 555 timers on a single chip. Figure 20.24(a) shows the functional block diagram and Figure 21.24(b) shows the pin diagram of IC 556. The two timers share the common VCC and ground bus lines. 556 timers are ideal for sequential timing applications. Figure 21.25 shows the sequential timer. The output of the first timer is connected to the input of the second timer through a 0.001 µF coupling capacitor. The waveforms are shown in Figure 21.26.

Discharge Thresold Control voltage Reset

14

1

13 12

2 C1A 3

11

4

10 FFA

9

5 6

Threshold Control voltage Reset

FFB 556

Output

Trigger Gnd

VCC Discharge

C2A

C2B

8

Output

Discharge Threshold Control voltage Reset Output Trigger Gnd

1 2 3 4 5 6 7

556

14 13 12 11 10 9 8

Trigger

7

(b) Pin diagram

(a) Functional block diagram of 556 timer

Figure 21.24 556 timer

VCC Discharge Threshold Control voltage Reset Output Trigger

555 Timer and Applications

1077

The duration of the first pulse (output A), T1 = RA1CA1 The duration of the second pulse (output B), T2 = RA 2CA 2 VCC RA2

RA1 10

4

14 12

1 2

CA1

CA2

13 NE 556 8

Trigger input VCC

6

0.001µF Output A

5 9

0

7

11

0.01µF

Output B

3 0.01µF

Figure 21.25 Sequential timer Trigger input

Output of the first monostable T1 = RA1CA1

Output of the second monostable

T2 = RA2CA2

Figure 21.26 Waveforms of the sequential timer

Additional Solved Examples Example 21.6 For the astable circuit shown in Figure 21.7, specify suitable components for f = 50 kHz, D = 75%. Assume C = 500 pF.

1078

Electronic Devices and Circuits

Solution:

RA + 2 RB = D=

1.44 = 57.6kΩ 50 × 10 × 0.5 × 10 −9 3

RA + RB = 0.75 RA + 2 RB

0.75 RA + 1.5 RB = RA + RB

0.25 RA = 0.5 RB

RA = 2 RB Therefore, 4 RB = 57.6 kΩ RB = 14.4 kΩ RA = 28.8 kΩ Example 21.7 If RB = 5 kΩ, calculate RA and C for the astable circuit in Figure 21.7, f0 = 1 MHz, D = 75%. Solution:

1 1 = = 1 µs f 1× 106

T=

D=

T1 T

T1 = DT = 0.75 × 1 = 0.75 µs

T2 = T − T1 = 1 − 0.75 = 0.25 µs D=

RA + RB = 0.75 RA + 2 RB

0.25 RA = 2.5

0.75 =

RA + 5 RA + 10

0.75 RA + 7.5 = RA + 5

RA = 10 kΩ

T2 = 0.693RBC

C=

T2 0.25 × 10 −6 = = 72 pF 0.693RB 0.693 × 5 × 103

Example 21.8 For the triggered ramp generator shown in Figure 21.14(b), VCC = 15 V, C = 0.1 µF, R1 = 50 kΩ, R2 = 100 kΩ, and RE = 3 kΩ. Calculate (i) the sweep speed, (ii) the peak-to-peak swing of the generated ramp, and (iii) sweep duration. Solution:

VB = VCC

R2 100 = 15 × = 10 V R1 + R2 50 + 100

VE = VB + VBE = 10 + 0.7 = 10.7 V IC =

VCC −VE 15 − 10.7 = = 1.43 mA RE 3

(i) Sweep speed, S =

I C 1.43 × 10 −3 = = 14.3V / ms C 0.1 × 10 −6

(ii) peak-to-peak swing = (iii) Ts =

2VCC 2 ×15 = =10 V 3 3

2 VCC 2 ×15 = = 0.699 ms 3 S 3 ×14.3

555 Timer and Applications

1079

Example 21.9 The monostable circuit shown in Figure 21.4 is triggered with a frequency division of 4:1. Find the value of RA, if C = 0.1 µF and the frequency of the trigger signal is 1 kHz. Solution: The duration of the trigger, Tp =

1 = 1 ms 1× 103

The time period of the monostable, TM = {0.2 + ( n − 1)}Tp = {0.2 + ( 4 − 1)}1 = 3.2 ms TM ≈ 1.1RAC

RA =

TM 3.2 × 10 −3 = = 29.09 kΩ 1.1C 1.1× 0.1× 10 −6

Example 21.10 For the free-running ramp generator in Figure 21.15, R = 4.7 kΩ, C = 0.1 µF, VCC = 10 V, and VD = 0.7 V. Calculate the sweep frequency.

Solution:

IC =

VCC −VD 10 − 0.7 = = 1.98 mA R 4.7

fs =

3I C 3 × 1.98 × 10 −3 = = 5.94 kHz VCCC 10 × 0.1 × 10 −6

Example 21.11 The pulse width modulator, as shown in Figure 21.20, has VCC = 15 V, R = 5 kΩ, and C = 0.2 µF. The trigger pulses are applied at pin 2 with pulse repetition frequency (PRF) of 2 kHz. Calculate (i) T, the quiescent pulse duration. (ii) What are the values of Tmax and Tmin, if the modulating signal varies as 2 sin wt. Solution: (a) The quiescent pulse duration is T = 1.1RC = 1.1 × 5 × 103 × 0.2 × 10 −6 = 1.1 ms 2 2 (b) Quiescent UTPQ = VCC = × 15 = 10 V 3 3 UTPmax = UTPQ + 2 = 10 + 2 = 12 V  UTPmax   12  Tmax = −RC ln 1 − = −5 × 103 × 0.2 × 10 −6 ln 1 −    15  VCC   = −1 × 10 −3 ( −1.61) = 1.61 ms Tmax = 1.61 ms UTPmin = UTPQ − 2 = 10 − 2 = 8 V  UTPmin  8  Tmin = −RC ln 1 − = −5 × 103 × 0.2 × 10 −6 ln 1 −    VCC  15  

1080

Electronic Devices and Circuits

= −1 × 10 −3 ( −0.755) = 0.755 ms Tmin = 0.755 ms

Summary • A 555 timer is monolithic timing circuit that can produce accurate and highly stable time delays or oscillations. • The basic building blocks of the 555 timer are two voltage comparators C1 and C2, an RS flip-flop, an inverting output buffer and a discharge transistor Q1. The reference voltage to 2 1 C1 is set at VCC and that for C2 the reference voltage is set at VCC. 3 3 • The time period of the monostable multivibrator using 555 timer is given as T = 1.1RC . • In the astable circuit if the frequency of oscillations can be varied by just changing an externally connected voltage, then the circuit is called the voltage-controlled oscillator (VCO) or voltage-to-frequency converter (VFC). • A 555 timer can be used for many applications, some of them are bistable multivibrator, pulse width modulator, frequency divider, FSK generator, etc. • A 556 dual timer is an IC in which two 555 timers are provided on a single chip

multiple ChoiCe QueStionS 1. The gate width of the monostable multivibrator using 555 timer is (a) 1.1 RC (b) 0.693 RC (c) 2 RC (d) RC 2. The pulse width of the circuit shown below is (a) 0.693 ms (b) 1.1 ms (c) 2.2 ms (d) 1 ms +VCC

10 kΩ

4

8

7 6 Trigger input 0.1µF

3

555 timer

2 1

5 .01µF

C

Vo

555 Timer and Applications

1081

3. The T1 (HIGH) and T2 (LOW) of the astable circuit using 555 timer having RA = 10 kΩ, RB = 5 kΩ, and C = 0.1 nF are (a) 1.04 µs, 0.347 µs (b) 3.0 µs, 1.0 µs (c) 0.5 µs, 1.5 µs (d) 1.5 µs, 0.5 µs 4. The duty cycle of the astable circuit for which T1 (HIGH) = 1 ms and T2 (LOW) = 1 ms is (a) 100% (b) 50% (c) 25% (d) 75% 5. The expression for the duty cycle of the 555 astable multivibrator in which RA is the resistor connected between pin 8 and pin 7and RB is the resistor connected between pin 7 and pin 6 is given by the relation (a)

RA RA + RB

(b)

RA + RB RA + 2RB

(c)

2RA RA + RB

(d)

2RB RA + RB

6. In the monostable operation, the output of the 555 timer switches high when a (a) negative-going trigger pulse is applied at pin 2 (b) positive-going trigger pulse is applied at pin 2 (c) negative-going trigger pulse is applied at pin 3 (d) positive-going trigger pulse is applied at pin 3 7. One of the applications of monostable operation using 555 timer is as a (a) free-running oscillator (b) Schmitt trigger (c) frequency divider (d) bistable multivibrator 8. The UTP and LTP for 555 timer, respectively, are VCC 2VCC 2VCC VCC , (b) , 3 3 3 3 V V V V (c) CC , CC (d) CC , CC 3 2 2 3 9. The control voltage in 555 timer is used to (a) change threshold and trigger voltage levels (b) change threshold only (c) change trigger voltage only (d) None of the above (a)

10. If RA = RB when 555 timer is used in the symmetric astable, its duty cycle is (a) 75% (b) 100% (c) 25% (d) 50% 11. The reset terminal 4 is usually connected to VCC in order to (a) avoid false triggering (b) to get constant current (c) to reset the timer (d) None of the above 12. In astable operation of 555 timer, the charging time constant is (a) (RA + RB)C (b) RBC (c) (RA + 2 RB)C (d) (2 RA + 2 RB)C

1082

Electronic Devices and Circuits

13. In astable operation of 555 timer, the discharging time constant is (a) (RA + RB)C (b) RBC (c) (RA + 2 RB)C (d) (2 RA + 2 RB)C 14. In astable operation of 555 timer, the capacitor voltage Vc varies between (a) 0–VCC (b) 0–VCC/3 (c) VCC/3–2 VCC/3 (d) 2 VCC/3–VCC 15. In astable operation of 555 timer, which does not use any diodes, (a) the charging time constant is greater than the discharging time constant (b) the charging time constant is less than the discharging time constant (c) the charging time constant is equal to the discharging time constant (d) None of the above

Short anSwer QueStionS 1. 2. 3. 4. 5. 6.

What are the basic building blocks of IC 555 timer? What is the expression for the pulse width of a monostable circuit using 555 timer? What is the expression for the duty cycle of the astable circuit? What are the trip voltages set for the lower and upper comparators in the 555 timer? What happens when external control voltage is applied to control pin? Explain how a 555 timer monostable circuit can be used as a pulse width modulator.

long anSwer QueStionS 1. Draw the circuit of the monostable multivibrator using 555 timer and explain its working. Derive the expression for its gate width. Draw the waveforms. 2. Draw the circuit of the astable multivibrator using 555 timer and explain its working. Derive the expression for its frequency and duty cycle. Draw the waveforms. 3. Suggest a suitable arrangement by which the duty cycle in an astable multivibrator using 555 timer can be varied. 4. Write short notes on the following applications of the monostable circuit: (a) ramp generator and (b) frequency divider 5. Explain, with the help of a neat circuit diagram, how an astable circuit can be used as a voltage-controlled oscillator.

unSolved problemS 1. For the monostable multivibrator shown in Figure 21.27, find the pulse width when the position of the switch is varied from 1 to 3.

555 Timer and Applications

1083

VCC R1 4 VCC

R2

10

R3

1

8

100

2

2

3

1

0

SW 7 NE 555 6 3

+

C 0.1 µF

5 1

Vo

0.1 µF −

Figure 21.27 Monostable multivibrator with variable pulse width

2. For the astable multivibrator shown in Figure 21.7, RA = 10 kΩ, RB = 47 kΩ and C = 0.01 µF. Calculate f and duty cycle. 3. Design the astable multivibrator shown in Figure 21.7, to give pulse repetition frequency (PRF) of 5 kHz and duty cycle D of 60 per cent. For 555 timer, I trig = 0.5 µA. Choose VCC = 15 V and I C(min) = 1, 000 I trig 4. Design the astable multivibrator shown in Figure 21.28 to oscillate at f = 5 kHz and having a duty cycle variable from 40 to 80 per cent. Choose VCC = 10. V and C = 0.01 µF. VCC

4

R1

8

R2

7

R3 D1 NE 555

RA X

Y

RB

R4

6 D2 2

+

3

+ C

5 Vo

1

Vc

0.1 µF − −

Figure 21.28 Astable multivwith variable duty cycle

1084

Electronic Devices and Circuits

VCC

4

RA

8 7

RA = RB RB D1

NE 555 6

D2

2

3

+

+ 5 Vo

C

1

Vc

0.1 µF

LED

−

−

Figure 21.29 Astable multivibrator

5. For the astable multivibrator in Figure 21.7, RA = 5 kΩ, RB = 10 kΩ, and C = 0.01 µF. Calculate T1, T2 , and f . 6. Design the astable multivibrator shown in Figure 21.29, to ON the LED for 5 s and OFF for 5 s.

22

SPECIAL ELECTRONIC DEVICES, OPTOELECTRONIC DEVICES, AND MEASURING INSTRUMENTS

Learning objectives After reading this chapter, the reader will be able to ˆ ˆ ˆ ˆ ˆ

22.1

Understand the principle of working some of the power electronic devices such as SCR, TRIAC, DIAC, etc. Appreciate the need and applications of optoelectronic devices such as photoconductors, LEDs, and laser diodes Understand the working of display devices such as seven segment LED displays, LCDs, and plasma display panels Understand the working of various measuring instruments such as multimeter, power meter, and energy meter Appreciate the importance of measurements such as frequency, time, distortion, and spectral analysis

POWER ELECTRONIC DEVICES

Initially, power diodes, capable of handling large currents and voltages, were used as one directional switches in power electronic circuits. Silicon-controlled rectifier (SCR) was developed in 1957. Since then, it was mainly used in power control and industrial applications, as the device has voltage ratings, typically of the order of 7000V and current ratings of the order of 5000A, the upper operating frequency being 1kHz. Presently, many varieties of power electronic devices such as TRIAC, DIAC, GTO, etc., are available, which can be appropriately used in power control circuits. The construction, characteristics, and simple applications of these devices are considered in the following sections.

22.1.1 Silicon-Controlled Rectifier A silicon-controlled rectifier (SCR) is simply an ordinary rectifier with an additional controlling element called the gate. The gate current controls the instant at which the device conducts. It is already known that silicon devices have smaller leakage currents when compared to their germanium counterparts. Hence, SCRs are mainly made of silicon only. An SCR, also called a thyristor, is extensively used in power-control applications. Thyristor is an acronym for THYRatron transISTOR. An SCR consists of four layers of semiconductor materials, with P and N materials alternating as shown in Figure 22.1. Based on this type of construction, the SCR is also called a four-layer diode or a PNPN device. The four layers are identified as P1, N1, P2, and N2. Consequently, there are three

1086

Electronic Devices and Circuits

PN junctions, identified as J1, J2, and J3. Three terminals, namely, anode, cathode, and gate, are externally brought out. Figure 22.2 gives the schematic representation. Anode A

P1 J1 N1 J2 Gate G

P2 J3

A

N2 N2

G K

Cathode K

Figure 22.1 Construction of SCR

Figure 22.2 Schematic representation

Anode

P1

Q1 N1A

N1B

P2A

P2B

P1 A Q2

Gate G

N1A Q1

N1B

P2A N2

Cathode K

Figure 22.3 Two-transistor construction

G

P2B

Q2

N2 K

Figure 22.4 Two-transistor equivalent circuit

To understand the working of SCR, let N1 be split into two parts:N1A and N1B. Similarly, let P2 be split into two parts:P2A and P2B. However, there still exist connections between N1A and N1B and P2A and P2B (Figure 22.3). P1, N1A, and P2A can now be thought of as a PNP transistor and N1B, P2B, and N2 can be considered as an NPN transistor (Figure 22.4). The base of Q1 and the collector of Q2 are connected together and the base of Q2 is connected to the collector of Q1. The emitter of Q1 is the anode of SCR, the collector of Q1 and base of Q2 junction is the gate of SCR, and the emitter of Q2 is the cathode. Let us now consider the behavior of the SCR (i) when it is reverse biased and (ii) when it is forward biased.

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1087

When Reverse Biased Reverse biasing an SCR means a negative voltage VAK is connected between the anode and the cathode as shown in Figure 22.5. Let the gate be open circuited, that is the gate current IG = 0. Let the voltage VAK be relatively small. Anode A

P1 Reverse biased J1 N1 VAK

IG = 0

Forward biased J2 P2

Gate G

Reverse biased J3 N2

Cathode K

Figure 22.5 Reverse-biased SCR

It can be noted from Figure 22.5 that with reverse biasing, junctions J1 and J3 are reverse biased, whereas junction J2 is forward biased. It is already known that in a reverse-biased junction diode, only a small leakage current called the reverse saturation current flows. Hence, the SCR current is negligibly small. If now VAK is increased from a small value to a reasonably larger value VR(max), at which avalanche breakdown occurs, the current in the SCR suddenly increases to a large value, which should be limited to a safe value, IR(max) (Figure 22.6). Reverse breakdown voltage VAK

VR(max)

0

Reverse blocking region

IR(max) IR

Figure 22.6 Reverse characteristic of SCR

When Forward Biased Let the SCR now be forward biased, that is VAK is now positive (Figure 22.7). However, assume that. the gate is open, that is, IG = 0. Then, the equivalent circuit is shown in Figure 22.8. When the gate is open circuited, IB2 = 0 and therefore IC2 = ICO. The base current of Q1, that is, IB1 = IC2 = ICO, which is practically zero. Hence, both Q1 and Q2 are OFF. Hence, high impedance is offered between the emitters of Q1 and Q2. The SCR is said to be in the

1088

Electronic Devices and Circuits

OFF state, as long as VAK is relatively small. Under this condition, junctions J1 and J3 are forward biased and junction J2 is reverse biased. When VAK is increased further, at one value of voltage known as the forward breakover voltage, VFBO breakdown of the reverse biased, J2 junction takes place. Then, Q1 and Q2 are switched ON and are driven into saturation. Suddenly, the current in the device, IA increases to a large value and at the same time the voltage across the device is reduced to a small value. This IA must be limited to a safe value. Even if IG is made zero, the SCR is still ON, with only a small anode to cathode voltage drop. The ability of the SCR to conduct heavily even when IG = 0 is called latching. Anode A

P1

A IA = ICO

Forward biased J1

IB1

N1 VAK

IG = 0

Reverse biased J2

Q1

Gate G

P2

IC2 = ICO VAK

IB2

Forward biased J3

G N2

IG = 0

Q2 + VBE2 −

Cathode K

K

Figure 22.7 Forward biased SCR with VGK = 0

Figure 22.8 Equivalent circuit of Figure 22.7

A practical way to trigger an SCR is to select a reasonable VAK and provide a positive voltage at the gate, VGK sufficient enough to drive Q2 in to saturation (Figure 22.9). When VGK = VBE(sat), IB2 = IB(sat). Then IC2 = IB1 = IC(sat). Hence, both Q1 and Q2 are driven into saturation and the SCR is said to be turned ON. By reducing the gate current, the device cannot be switched into the OFF state once again. Hence, it is said that the gate loses control once the SCR is switched into ON state or when the SCR fires. IA

A

IB1 Q1 G + VGK −

IG

IC2 = IC(sat) VAK

IB2 Q2

+ VBE2 −

IA K

Figure 22.9 Circuit when VGK is positive

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1089

IA Forward conduction region

IG2 Holding current IH 0

IG1 IG = 0

VFB2 VFB1

VFBO VF

Forward blocking egion

Figure 22.10 Forward characteristics of the SCR

From Figure 22.10, it can be noted that higher levels of gate current can make the SCR to conduct at lower anode-to-cathode voltages. Figure 22.11 shows the forward and reverse characteristics of the SCR. IA Forward conduction region

IG2

Reverse breakdown voltage

VAK

VR(max)

Holding IH current 0

IG1

IG = 0

VFB2 VFB1

Reverse blocking region

VFBO VF

Forward blocking region

IR(max) IR

Figure 22.11 Forward and reverse characteristics of SCR

Some definitions that are pertinent to SCR are as follows: (i) Forward breakdown voltage: It is the minimum forward voltage at which the SCR starts conducting heavily or turned ON, with I G = 0. This is also called the breakover voltage. (ii) Holding current, IH: It is the current below which the SCR switches from the conduction state to the forward blocking region. (iii) Forward and reverse blocking regions: These are the regions in which the flow of current from anode to cathode is blocked. (iv) Reverse breakdown voltage: It is the reverse voltage at which the SCR behaves as a Zener or avalanche diode operating at breakdown. (v) Forward current rating of an SCR: It is the maximum anode current the SCR can handle safely.

1090

Electronic Devices and Circuits

Forced Commutation to Switch Off SCR It is noted that once the SCR fires, the gate VA loses control. Some SCRs may be turned OFF by applying a negative pulse. But in some SCRs, to drive the ON device into the V Q OFF state, forced commutation technique IA IC(sat) may have to be used. By forced commutation, 0 G it is meant “forcing” a current that is equal and opposite of the forward conduction IG VB current to drive the SCR into the OFF R L state. A simple circuit that accomplishes this task is shown in Figure 22.12. When the SCR is conducting normally, the externally connected NPN transistor Q is OFF as its Figure 22.12 Forced commutation to switch off SCR base current is zero, when the voltage at its base is zero. Hence, the resistance between its collector and emitter terminals is very large. As such, this additional circuit will not influence the normal operation of the circuit. This means that the SCR continues to be in the ON state. If, however, the SCR is to be driven into the OFF state, a positive pulse of proper magnitude V is applied to the base of Q so that Q is driven into saturation. As the ON resistance of Q is very small, for all practical purposes, the battery voltage is directly connected across the anode and the cathode of the SCR, resulting in a current I C(sat) that flows opposite to the forward current, I A. As I A = I C(sat), the net current in the SCR is zero. Hence, the SCR is switched OFF.

SCR as a Half-Wave Rectifier Consider the circuit in Figure 22.13, where the SCR is used as a controlled half-wave rectifier. During the negative-going half cycle of the input, the SCR is OFF. During the positive-going half cycle, the SCR conducts when a gate current I G flows. The larger the gate current, the smaller the voltage at which the SCR conducts. Hence, the angle of conduction can be controlled by I G . The variable resistance R controls I G . Let for one particular value of I G , the voltage at which the SCR conducts be V1 and the corresponding angle be a,the firing angle. Then, the angle for which the SCR conducts is called the angle of conduction and is (180° − a ).

V1

IL RL Mains supply

v

IG

SCR R

0

Output V1 π

α

2π

VG Input

Figure 22.13 (a) SCR as a controlled half-wave rectifier (b) Waveforms

Vdc =

1 2p

180°

∫V

m

a

sin qdq =

180° V Vm [ − cosq ]a = 2pm [cos a − cos180°] 2p

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

Vm [1 + cos a ] 2p

Vdc =

If a = 0, Vdc = and if a =

1091

(22.1)

Vm p

V p , Vdc = m (output of the half-wave rectifier using PN junction diode) 2 2p

Example 22.1 For the half-wave rectifier shown in Figure 22.13, I G = 1 mA. The SCR conducts at a forward voltage of 120V. A sinusoidal voltage, having Vm =240 V, is applied as input. RL = 120 Ω . Determine (i) firing angle, (ii) conduction angle, (iii) Vdc (iv) I dc , and (v) the output power. Solution: (i)

v = Vm sinq

⇒ 120 = 240 sinq 120 ⇒ sinq = = 0.5 240 ⇒ q = a = 30° (ii) Conduction angle =180° − 30° = 150° V 240 (iii) Vdc = m [1 + cos q ] = [1 + cos 30°] = 71.31 V 2p 2p V 71.31 (iv) I dc = dc = = 0.5943 A RL 120 (v) Output power = Vdc I dc = 71.31 × 0.5943 = 42.38 W The circuit of the full-wave rectifier is shown in Figure 22.14(a) and the waveforms are shown in Figure 22.14(b). IG R v Mains supply

0

RL

V1

VG 0

IL

α

Output

V1

π

α

2π

v R

VG

Input

IG

Figure 22.14 (a) SCR as a controlled full-wave rectifier (b) Waveforms

Vm [1 + cos a ] p

(22.2)

Vm [1 + cos a ] pRL

(22.3)

The dc voltage,

Vdc =

and

I dc =

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Electronic Devices and Circuits

An SCR is used in power electronics for control applications. Hence, protective circuit must be provided to avoid damage to the device. A snubber is a circuit used to protect an SCR. It is used for limiting the rate-of-rise of currents ( di /dt ) through the semiconductor device at turn-on and for limiting the rate-of-rise of voltages ( dv /dt ) through the SCR at turn-off. A simple snubber circuit is shown in Figure 22.14(c). Let initialy R be zero. When switch SW is closed, a sudden voltage V appears across the circuit, C behaves as a short circuit, therefore voltage across SCR is zero. Subsequently, C charges at a slow rate such that dv /dt across C and therefore across SCR is less than the specified maximum dv /dt rating of the device. C is sufficient to limit dv /dt. However, if R is not used, before SCR is fired by gate pulse, C charges to full voltage V. When the SCR is turned ON, C discharges through the SCR, and this results in a current approximately equal to V /RON , where RON is the ON resistance of the SCR, which is very small. Hence, the turnon di /dt will be excessive. It is possible that the SCR may be destroyed. Now with the inclusion of R, when SCR is turned ON, initial discharge current V /R is relatively small and turn-on di /dt is reduced. A snubber is commonly used with inductive loads such as electric motors. R

C

id +

SW

V Load

−

Figure 22.14 (c) Simple RC snubber

22.1.2 TRIAC An SCR can be used in unidirectional switching applications. For bidirectional switching applications, as in a full-wave power control, two thyristors need to be connected in inverse parallel as shown in Figure 22.15. Flow of current, during both halves of the ac input, is depicted in Figure 22.16. But, using two SCRs increases the circuit complexity. In such applications, a TRIAC, which

V1 SCR1 Drive circuit

Inverse parallel connection of SCRs

SCR2

¬ Output

a 0 a

p

Input ¬

2p ¬ Output

−V1

Figure 22.15 Inverse parallel connection of SCRs

Figure 22.16 Bidirectional switching using two SCRs

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1093

is the acronym for TRIode for Alternating Current, is conveniently used. TRIAC is a bidirectional switch of the thyristor family. A TRIAC can be triggered into conduction by both positive and negative voltages applied to its anode and with both positive and negative trigger pulses applied to its gate terminal. Thus, a TRIAC can be considered as a two-quadrant switching gate-controlled device. TRIAC means a three-terminal bidirectional switch. TRIAC, in fact, comprises two thyristors connected together in inverse parallel, but they share a common gate terminal. As the TRIAC conducts in both directions, the anode terminal is identified as main terminal 2(MT2) or anode 2 and the cathode as main terminal 1(MT1) or anode 1. The two gate terminals are connected together and one single gate terminal is brought out externally. Usually, MT1 is taken as the reference. The structure, equivalent circuit, and the circuit symbol are shown in Figure 22.17. TRIAC is a four-layer three-terminal bilateral switch. The gate terminal G makes ohmic contacts with both the N and P materials. This allows both positive and negative trigger pulses to start conduction. P1N1P2N2 forms one SCR and P2N1P1N4 forms the other SCR. MT2 N4

MT2

Anode 2 P1

P2N1P1N4

N1

Inverse parallel MT1 connection of SCRs

Gate

P2 N3

N2

G

MT1

Anode 1

(a) Basic structure

Anode 2 MT2

P1N1P2N2

Anode 1

Gate

MT1

(c) Circuit symbol

(b) Equivalent circuit

Figure 22.17 TRIAC

When MT2 is positive with respect to MT1 and a positive pulse is applied to the gate, SCR P1N1P2N2 conducts and when MT2 is negative with respect to MT1 and a negative pulse is applied to the gate, SCR P2N1P1N4 conducts. One major drawback of the TRIAC is that it may switch at different gate voltages during each half of the cycle that results in generating high-level harmonics. V–I characteristics of TRIAC are shown in Figure 22.18. IMT

Forward conduction

IL IH

−VMT21

0

Reverse conduction

IH

IL

−IMT

Figure 22.18 V–I characteristics of TRIAC

VFBOVMT21

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Electronic Devices and Circuits

One simple application of TRIAC is seen in Figure 22.19. When the switch is open, the TRIAC does not conduct as there is no gate current, and hence the lamp is OFF. When the switch is closed, the gate current is supplied and the TRIAC conducts both during the positive and negative half cycles of the input. The lamp is ON for the entire input period. As both halves of the sine wave are controlled, this type of switching control is called full-wave control. TRIAC is used in domestic light dimmers, electric fan speed controls, small motor controls, and control of small AC-powered domestic appliances.

Lamp Switch + MT2 Vs

R G

TRIAC −

MT1

Figure 22.19 TRIAC as a bidirectional switch

22.1.3 DIAC A DIAC, which is an acronym for DIode for Alternating Current, is a two-terminal, four-layered silicon device. The device can be switched ON or OFF by a signal of either polarity. The diodes are avalanche diodes that conduct only when the breakdown voltage, VBO, is reached. The basic structure and circuit symbols are shown in Figure 22.20. From Figure 22.20, it can be noted that a DIAC is a gateless TRIAC designed to conduct at small breakdown voltages. A DIAC is a uniformly doped PNPN layer. As a result of this uniform doping, the V–I characteristic has bidirectional symmetry. A DIAC can be considered as having two avalanche diodes connected in inverse parallel. MT1 and MT2 are the external terminals. The current waveform in a DIAC is shown in Figure 22.21. When the applied voltage is small, only leakage current flows through the device, which is very small. When the applied voltage makes MT2 positive with respect to MT1 and is large enough to cause breakdown, then one diode is ON. When the polarity of the voltage is reversed, the other diode conducts. The V–I characteristic of DIAC is shown in Figure 22.22. Since the switching characteristic of DIAC is even, DIAC is used to trigger a TRIAC. A lamp dimmer circuit using a DIAC for triggering a TRIAC is shown in Figure 22.23. The firing angle is adjusted by adjusting R. When the input reaches the breakdown voltage of the DIAC, it conducts and the gate trigger for the TRIAC is generated. MT2

N1 P1 MT2 N2 P2 N3

MT1

MT1

Figure 22.20 DIAC

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

Breakdown Voltage Input

Breakdown Voltage

Figure 22.21 Current waveform in a DIAC IMT

Forward conduction IBO

−VMT21

0 IBO

VBO VMT21

Reverse conduction

−IMT

Figure 22.22 DIAC V–I characteristic Lamp

+

R MT1

Vs

MT2 −

DIAC C

G

MT2 TRIAC MT1

Figure 22.23 Lamp dimmer circuit using a DIAC for triggering a TRIAC

1095

1096

Electronic Devices and Circuits

22.1.4 The Gate Turn-Off Thyristor or GTO Thyristor When a thyristor fires, gate loses control; and for it to be switched OFF, a commutation circuit is to be provided. This problem is avoided in a GTO thyristor. A GTO thyristor is turned ON by the application of a positive trigger signal to the gate and the device can be turned OFF by the application of a negative trigger pulse to the gate. The basic structure, equivalent circuit, and the circuit symbol are shown in Figure 22.24. This device is again a four-layered device and can be thought of as being one PNP and one NPN transistor being connected in a regenerative configuration (Figure 22.24(b)). A

A A

P1+ N−

Q1

1

G

P2 N+

G

G

Q2

K

1

K (a) Structure

K (b) Equivalent circuit

(c) Circuit symbol

Figure 22.24 GTO thyristor

When a potential that makes the anode positive with respect to the cathode is applied, the device remains in the OFF state until the positive trigger pulse is applied to the gate. When it is in the OFF state, the thyristor is said to be in its forward blocking mode. To turn ON the device, a positive pulse is applied to the gate to inject gate current. This turns ONQ2. Then, VCE of Q2 becomes zero. The collector of Q2 is now at the same potential as its emitter. This turns ON Q1 and hence Q1 has a large emitter current, which keeps Q2 ON. The device remains in the ON state. To turn off the device, a negative trigger is applied to the gate, which switches OFF Q2. The voltage at its collector rises and the emitter diode of Q1 is reverse biased. Q1 is OFF and no base current is provided to Q2. The device is turned OFF.

22.1.5 Light-Activated SCR or Photo SCR A light-activated SCR (LASCR) is a three-terminal, four-layered unilateral device similar to an SCR, except that it is light triggered. Some LASCRs have clear windows in their cases so that light sources can be coupled to them. Some LASCRs have the light source encapsulated in the same package. When light falls on depletion layer, the LASCR turns ON, as a normal SCR does. For maximum sensitivity to light, the gate is left open (Figure 22.25). LASCRs are used in high voltage DC (HVDC) transmission.

22.1.6 Light-Activated TRIAC or Photo TRIAC Light-activated TRIAC or a photo TRIAC is a conventional TRIAC, except for the fact that it is triggered by an incident light radiation (Figure 22.26).

VCC

R

Open

Figure 22.25 LASCR

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1097

MT2

MT1

Figure 22.26 Photo TRIAC

22.2

OPTOELECTRONIC DEVICES

Optoelectronic devices find applications in display systems and in communications. Some of the devices are considered in this section.

22.2.1 Photoconductivity An optoelectrical phenomenon in which a semiconductor material becomes more electrically conductive due to the absorption of electromagnetic radiation is called photoconductivity. This radiation can be in the form of visible, ultraviolet and infrared light, or gamma radiation. The energy of a photon is given as follows: E=

hc l

(22.4)

where h =Planck’s constant = 6.626 × 10 −34 J-s l= wavelength of the incident light radiation c = velocity of light = 3 × 109 m/s

1eV = 1.602×10−19 J

hc = 1.99 × 10−25J-m =1.24 × 10−6eV-m

(

)(

)

= 1.24 × 10 −6 eV-m 1.0 × 106 mm/m = 1.24 eV-µm ∴

E=

hc 1.24 = eV l l

(22.5)

where l is in micrometers. Therefore, the energy imparted by the photon depends on the wavelength of the incident light radiation. A semiconductor may have both donor and acceptor impurities. When a photon having enough energy is absorbed by a donor electron, it moves into the conduction band; or when it is absorbed by an acceptor electron, it moves into the acceptor band. Electron–hole pairs are generated, resulting in increased electrical conductivity. When the conductivity increases, its resistivity decreases. If the semiconductor is connected in a circuit with proper bias voltage, it will behave like a light-controlled resistor (Figure 22.27).

1098

Electronic Devices and Circuits

I Light radiation

+V

H

L W

Figure 22.27 Photoconductor

At thermal equilibrium, the conductivity of the semiconductor material is (22.6)

s = ne me + pe mp

Let ∆n and ∆p be the excess electron and hole density per unit volume due to incident light radiation. At equilibrium the rate of recombination is equal to rate of regeneration. Therefore, (22.7)

∆n = ∆p = rgt c

where rg is the average rate of generation of electron–hole pairs and t c is the life time of the charge carriers. The increase in conductivity due to illumination is

(

∆s = ∆ne me + ∆pe mp =∆ne me + mp

)

(22.8)

Using Eqn. (22.7),

(

∆s =rgt c e me + mp

)

(22.9)

On the application of a voltage V, electrons and holes move in the opposite directions, thereby constituting a photocurrent.  mp  I p = ∆J A = ∆sEA = rgt c e me + mp AE = rgt c eEAme 1+   me 

(

)

(22.10)

where ∆J = ∆sE , E is the electric field, and A = WH =cross-sectional area of the semiconductor. The drift velocity of the electron = meE The transit time,tt is the time taken by the electron to cover the distance L, which is the length of the semiconductor. tt =

L L or meE = me E tt

(22.11)

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1099

Substituting Eqn. (22.11) in Eqn. (22.10), I p = rg eAL

Rate of electron flow =

Ip e

rg eAL =

tc tt

 mp  1+ m  e

 mp  1 + m  t e = rg AL c e tt

tc tt

(22.12)

 mp  1 + m  e

(22.13)

Rate of electron photogeneration =Volume × rg = ALrg

Photoconductor gain =

Rate of electron flow = Rate of electron photogeneration

Photoconductor gain=

tc tt

 mp  1+ m  e

(22.14)

rg AL L

 mp  1+ m  e ALrg

tc tt

(22.15)

22.2.2 Photodetectors Photodetectors are used to convert light into electricity. The principle that applies to photodetectors is the photoelectric effect. When a surface is exposed to sufficiently energetic electromagnetic energy, light gets absorbed and electrons get emitted. The threshold frequency is different for different materials. Some of the photodetectors discussed subsequently are (i) light-dependent resistor or LDR, (ii) photodiode and photovoltaic or solar cells, (iii) phototransistor, and (iv) light-emitting diode (LED).

Light-Dependent Resistor An LDR or a photoresistor offers resistance in response to the incident light. This means LDR exhibits photoconductivity. An LDR is made up of cadmium sulfide (CdS), whose resistance decreases as the intensity of incident light increases, and vice versa. When no light falls, LDR offers a resistance of the order of mega-ohms. When light falls, its resistance decreases to a few hundred ohms. Since the resistance of the LDR varies with varying light, the voltage drop across it can be directly calibrated in terms light intensity. Thus, it can act as a sensor. LDR is used in light meter, photo relay, burglar alarm, etc. LDR is fabricated by depositing CdS as a thread pattern on an insulator. The larger its length, the better the sensitivity. Therefore, the shape is usually a zigzag track (Figure 22.28). The cell is then encapsulated in a transparent resin or encased in glass to protect the CdS from getting contaminated due to atmosphere. It is a bilateral device; that is, it conducts in both directions in the same manner and pattern. The variation of LDR’s resistance with light intensity is shown in Figure 22.29.

1100

Electronic Devices and Circuits

Cadmium sulphide track

Figure 22.28 (a) Zigzag CdS track (b) Circuit symbol

Resistance in kΩ

1000 100 10 1 0.1 0.1

1

10

100

1000 10000 Lux

Figure 22.29 Variation of LDR resistance with flux

The intensity of light at a distance of 1m from a standard candle is 1m candle or 1lux. Lux is a unit of light measurement. One simple application for an LDR is to automatically turn ON/OFF the street light (Figure 22.30). As long as the light is sufficient, LDR offers low resistance and Q is OFF. When it is dark, the resistance of the LDR increases and Q switches ON and the relay is energized and a change over contact will switch ON the light. VCC Relay coil Relay contact

R

Q

LDR

RE

Figure 22.30 LDR to turn on Q when it is dark

230V ac

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1101

Photovoltaic or Solar Cell A photovoltaic or solar cell consists of a thick N-type crystal covered by a thin P-type layer. A load resistance RL is connected across the junction (Figure 22.31). Incident solar radiation results in the generation of electron–hole pairs and produces an electric field in the depletion layer that drives the electrons to the N-type side and the holes to the P-type side. This, to a larger extent, prevents recombination of the electrons and holes. Thus, solar radiation is converted into electrical energy. Photons in the ultraviolet and visible regions of the solar spectrum impart energies greater than the energy gap and electron–hole pairs are created. Only a part of this energy is converted into electrical energy. The excess energy is dissipated as heat. But photons in the near infrared having wavelengths of 0.7– 1.1 µm have energies only slightly greater than the energy gap. Hence, most of the energy imparted is converted into electrical energy. Therefore, the upper limit to the efficiency of a silicon solar cell is typically 45 percent. Recombination of the electrons and holes reduces the efficiency further. Solar radiation

I +

P N

V −

RL

Figure 22.31 Photovoltaic solar cell with load

Phototransistor A photodiode is like a Ge or Si PN junction diode, encased in a plastic or glass casing so as to allow light to fall on the junction. However, to provide better sensitivity, a phototransistor is normally used. The operation of a phototransistor depends on the biasing arrangement and light frequency. For instance, if a PN junction is forward biased, the increase in current through the junctions due to incident light will be very small. Alternately, if the junction is reverse biased, the current increases many folds and is a function of the light intensity. Therefore, reverse bias is the normal mode of operation. A phototransistor can be an NPN transistor, with biasing provided as shown in Figure 22.32. From Figure 22.32, it can be noted that the collector junction JC is reverse biased and the emitter junction JE is forward biased by a small voltage. The physical base lead of the transistor can be left as an open terminal. A small amount of current can flow in the phototransistor even when no light is present, and this current is called the dark current, and represents a very small number of carriers that are injected into the emitter. This is subject to the amplification by the transistor action (CE mode), and the collector current is given as follows: I C = (1 + bdc ) I CO

(22.16)

However, when light falls on the reverse-biased collector–base junction of the phototransistor, the light-induced current is effectively the base current. In a transistor, a small increase in the base

1102

Electronic Devices and Circuits

current can cause a significant increase in the collector current. Thus, light stimulation causes an increase in base current, which in turn causes a larger increase in collector current. The collector current when light falls is I C = (1 + bdc ) ( I CO + I L )

(22.17)

whereI L is the component of reverse current with incident light radiation. The characteristics of the phototransistor under different light intensities are shown in Figure 22.33. They are very similar to the characteristics of a conventional bipolar transistor, but with base current source replaced by light intensity. IC C RL N Light radiation P

JC JE

B

+ VCE −

C

VCC

N

E

E

Figure 22.32 Phototransistor IC(m A ) 8

9

7 7

6 5

5

4 H = mW/cm2

3

3 2

2

1

H =1 0

2

4

6

8

10

12

VCE(V )

Figure 22.33 Characteristics NPN phototransistor

Light-Emitting Diode A light-emitting diode (LED) is a semiconductor light source. LEDs can emit bright light across the infrared, visible, and ultraviolet wavelengths. LED is a special type of PN junction diode that is made from a very thin layer of fairly heavily doped semiconductor compounds such as gallium arsenide (GaAs), gallium phosphide (GaP), gallium arsenide phosphide (GaAsP), silicon carbide (SiC), or gallium indium nitride (GaInN), all mixed at different ratios are used. The color of the light emitted is determined by the wavelength, l of the light emitted, which in turn is determined by the semiconductor compound used in the PN junction.

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1103

When an LED is forward-biased (turned ON), electrons from the conduction band recombine with holes from the valence band, releasing sufficient energy in the form of photons that emit a monochromatic (single-color) light. This effect is called electroluminescence and the color of the light is determined by the energy gap of the semiconductor. The wavelengths and frequency ranges of infrared, visible, and ultraviolet ranges are tabulated in Table22.1. The frequency indicator in these ranges is usually a terahertz (THz). A terahertz is one trillion hertz (1012 Hz). LEDs convert electrical energy into light energy. Table 22.1 Wavelengths and frequency ranges of infrared, visible, and ultraviolet spectrum. Range

Wavelength, l (m)

Frequency, f (Hz)

Frequency, f (THz)

Infrared

300 × 10−6 to 0.74 × 10−6

1 × 1012 to 4.05 × 1014

1– 405

Visible

0.74 × 10−6 to 390 × 10−9

4.05 × 1014 to 7.69 × 1014

405 –769

Ultraviolet

390 × 10−9 to 10× 10−9

7.69 × 1014 to 3 × 1016

769–30,000

Table 22.2 gives the list of semiconductor compounds used to get the monochromatic light of the most commonly used LEDs and their typical forward voltages. Table 22.2 Semiconductor compounds and the color of the light emitted. Semiconductor compound

Wavelength (nm)

Color

Typical VF(V)

GaAs

850–940

Infrared

1.2

GaAsP

630–660

Red

1.8

GaAsP:N

585–595

Yellow

2.2

AlGaP

550–570

Green

3.5

Construction An N-type epitaxial layer is grown upon a substrate and the P-region is created by diffusion (Figure 22.34(a)). The anode A and cathode K terminals are brought out externally through metallic contacts. The conducting surface connected to the P-material is very small so as to enable maximum number of photons to emerge. The PN junction is mounted on a cup-shaped reflector and is encapsulated in an epoxy plastic lens (Figure 22.34(b)). The photons emitted

1104

Electronic Devices and Circuits

by the junction are reflected from the surrounding substrate and are focused upward toward a hemispherical-shaped dome.

Anode, A

Visible light

Metal contact

Electron-hole pairs −Recombination

P-type compound semiconductor

N-type compound semiconductor Metal contact Cathode, K

(a) PN junction of LED Plastic dome

PN junction

A

K

(c) Schematic representation of LED Reflector

Cathode, K Anode, A

(b) Construction of LED Figure 22.34 LED construction and conduction in LED

V–I Characteristic An LED practically being a PN junction diode, its forward current to voltage characteristic curve is similar to the diode curve. If, on the other hand, the LED is reverse biased the depletion region acts as an insulator, resulting in a negligible reverse current. An LED is used only in forward-biased condition. The V–I characteristics of some LEDs are shown in Figure 22.35.

1105

Green

IF

Yellow

(mA )

Red

Infrared

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

50 40 30 20 10

1

0

2

3

4

5

VF (V )

Figure 22.35 V–I characteristics of LEDs under forward-biased condition

Maximum forward current, maximum forward voltage, average forward current, and maximum power dissipation will be specified by the manufacturer. To limit the LED current to a safe value, a series limiting resistance RS is included the circuit (Figure 22.36). If V = 5 V, VF = 2 V, and IF = 30 mA, then RS =

V − VF 5 − 2 = = 100 Ω IF 30

IF RS V A

+ VF

K

−

Figure 22.36 Limiting the LED forward current to a safe value

LASER Diode LASER is an acronym for Light Amplification by the Stimulated Emission of Radiation. The basic structure of a laser diode is shown in Figure 22.37. The thickness of the active region in a laser diode is typically of the order of 0.1 µm. The two end surfaces are accurately cut and polished (cleaved) to create reflecting mirrors. The refractive index of GaAs is about 3.6. As such, more than 30 percent of incident light will be reflected back into the active region at the GaAs–air interface.

1106

Electronic Devices and Circuits

Pump forward current I

Metal Active region (N-type material)

Cleaved surface (mirror)

Light

P-GaAs N-GaAs

Metal

Cleaved surface (mirror)

Figure 22.37 Basic structure of LASER diode

Photoemission occurs when light passes through the laser diode junction. When an electron is in an excited energy state E2, it must decay to a lower energy level E1, giving off a photon of radiation. This phenomenon is called spontaneous emission. In this case, the photon is emitted in a random direction with a random phase. Alternately, let an electron be at a higher energy state E2, and is decaying to E1. However, before it spontaneously decays to E1, a photon having an energy that is approximately (E2−E1) may pass by. Then, there is a possibility for the passing photon to cause the electron to decay such that another photon is emitted, and the photon thereby emitted has exactly the same wavelength, moves in exactly in the same direction, and also has exactly the same phase as that of the passing photon. This process is called stimulated emission (Figure 22.38). The energy to put these atoms in excited states is provided by an external energy source called the pump.

E3 E2

Light amplification

Photon

Energy input E1 (a)

(b)

(c)

(d)

Figure 22.38 Stimultaed emission

The following steps explain the principle of stimulated emission: Figure 22.38(a) —Light energy enters the system and pumps electrons to a higher energy level. Figure 22.38(b) — Pumping is unstable, therefore electron quickly jumps to a slightly lower energy level. Figure 22.38(c) —When electron loses energy and relaxes back to original level, a photon is emitted. Figure 22.38(d) —When this photon encounters another electron in an exited state, it stimulates this electron also to emit a photon. The second photon will have the same wavelength and phase as that of the first photon; these two photons get combined so that light gets doubled.

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1107

The distance between these reflecting end surfaces is an exact multiple of one complete wave, so that as the photons reflect from each end of the cavity, they stay in phase, and the amplitude of the reflected wave adds to the amplitude of other waves within the cavity. The waves thus keep adding as they bounce back and forth between the mirrors. The material forms, in effect, a resonant cavity that aids the amplification of the light. In a nutshell, a cascading effect occurs and a large number of photons of the same wavelength and phase are present. This is called light amplification (Figure 22.39). As a result, monochromatic, single-phase light leaves the resonant cavity of the laser through the semireflecting mirror. This light will then pass through a collimating lens that focuses the laser light into a parallel beam.

Fully reflecting surface

Laser medium

Partially reflecting surface

Coheremt laser beam

Resonant cavity

Figure 22.39 The resonant cavity effect in a laser

22.3

OPTOCOUPLERS

In communication systems, there arises the need to transfer signals and data either from one subsystem to another within the same electronic equipment or from one electronic equipment to another, without making a direct ohmic electrical connection. This type of situation may arise because the source (transmitter) and the destination (receiver) may operate at different voltage levels. The need, now, is to establish an isolated link between the source and destination, avoiding damage due to overvoltage. One may be prompted to use relays to satisfy this requirement. But relays tend to be bulky, have slower operating speeds, and lesser reliability. Therefore, optocouplers or photocouplers are used in applications where small size, higher speed, and greater reliability are the primary concerns. Optocouplers use a light beam to transmit the signals or data (analog or digital) across an electrical barrier, with excellent isolation. An optocoupler consists of (i) light emitter (ii) light detector. (i) The light emitter is on the input side that converts the input signal into a light signal. Typically, the light emitter is an LED. (ii) The light detector within the optocoupler detects the light from the LED and converts it back into an electrical signal. The light detector can be any one of a number of different types of devices—a photodiode, a phototransistor, photo-Darlington transistor, photo SCR, and so on. The LED and the detector are chosen such that they have the same wavelengths to ensure maximum coupling.

1108

Electronic Devices and Circuits

22.3.1 Photodiode Optocoupler Figure 22.40 shows a photodiode optocoupler.

Photo diode

LED

II

IO A

K

+

R

R1

VI K

A

VO −

Figure 22.40 Photodiode optocoupler

As the input signal, VI, varies, it will vary the intensity of the infrared light. The output current, IO, will also change, causing the output voltage, VO, to change in the same manner. A small change in II will produce a proportionate change in IO. The photodiode optocoupler is used to couple low-level analog signals or small dc voltage variations with practically no distortion. The current transfer ratio(CTR) of an optocoupler is defined as follows: CTR =

IO II

(22.18)

For a diode optocoupler, CTR is extremely low, i.e. about 10–15 percent. If the photodiode is replaced by a phototransistor, depending on the value of b , the CTR can be high, typically of the order of 50–70 percent. It is possible to increase or decrease the sensitivity by increasing or decreasing the forward-bias voltage at the base. Sometimes, the base may even be left unconnected (Figure 22.41). If a Darlington phototransistor is used, the CTR improves further (Figure 22.42).

1

6 5

2 3

4

Figure 22.41 Optocoupler with phototransistor

1

6 5

2 3

4

Figure 22.42 Optocoupler with Darlington phototransistor

It is well known that power systems may operate from 11kV to more than 132 kV. The purpose of an optoisolator is to isolate power systems while transmitting and receiving analog or digital data between the systems. In general, optoisolators are also called optocouplers. Figure 22.43 shows an SCR optocoupler. The SCR gate current is supplied through the photovoltaic action produced by the incident infrared light radiation on the SCR gate, while optically isolating the input and output circuits of the optocoupler. Figure 22.44 shows a photo DIAC optocoupler.

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1109

6

1

5 1

6 5

2

2 3

4

3

Figure 22.43 Photo SCR optocoupler

4

Figure 22.44 Photo DIAC optocoupler

A simple application of an optocoupler is shown in Figure 22.45. When the switch is open, the phototransistor is OFF and Vo = VCC . When the switch is closed, the phototransistor is ON and Vo = 0. D is used to ensure that the LED is not reverse biased by stray input.

VCC

Optocoupler R

1

RC

D

V

5

Vo

2 4

3 6

Figure 22.45 Application of an optocoupler

22.3.2 Cold Cathode or Nixie Displays Nixie tubes are cold cathode gas filled indicators. Nixie tubes consist of a common anode and 10 individual metallic cathodes (to display 0–9) arranged at different depths (Figure 22.46). The cathodes can also be formed in the shape of alphabetical characters or special symbols. A voltage V, enough to

Number shaped cathodes

2

2 (a) Front view Figure 22.46 Nixie tube

(b) Side view

1110

Electronic Devices and Circuits

cause discharge, is applied through a limiting resistor R (to limit the current), to the selected character with respect to the common anode. The cathode of a gas discharge diode displays the character (Figure 22.47). Only the selected character is visible, the display typically being of orange-red color. The cathode can also be a common terminal. R Anode

0

1

2

3

4

5

6

7

8

9 V

Figure 22.47 Circuit of a common anode nixie tube

22.3.3 Seven-Segment LED Display A 7 segment display is a 9 pin display device with 7 LEDs placed inside it to display numbers from 0 to 9. Some displays may even provide a dot pin. All the 7 LEDs may have either their anodes as a common terminal (common anode 7-segment LED) or cathodes as a common terminal(common cathode 7-segment LED). A common cathode 7-segment display is shown in Figure 22.48. Seven LEDs are arranged in the figure-8 pattern. When working with a common cathode 7-segment display, suitable voltage must be applied externally to each of the anodes with respect to the common cathode for that particular LED to glow. Current-limiting resistors need to be provided to limit the amount of current flowing through each LED segment. In practical applications, a BCD to 7-segment decoder driver is used to switch the LEDs ON, depending on the binary pattern of the input (Figure 22.49, Table 22.3). a 1

14 a f

2 Common 4 cathode 6

b g

a b f f

13

b g

g c e

c

e

c

e d

7

8

d d

Common cathode

Figure 22.48 Seven-segment, common cathode LED display

1111

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

A (LSB)

BCD decoder driver

B C (MSB) 5V

D 10 kW each

470 kW each a b c d e f g

a f e

g

d

b c

Cathode

Figure 22.49 Seven-segment display using a BCD decoder driver

Table22.3 Seven-segment LED display. BCD inputs

LED segments Display

D

C

B

A

a

b

c

d

e

f

g

0

0

0

0

ON

ON

ON

ON

ON

ON

OFF

0

0

0

1

OFF

ON

ON

OFF

OFF

OFF

OFF

0

0

1

0

ON

ON

OFF

ON

ON

OFF

ON

0

0

1

1

ON

ON

ON

ON

OFF

OFF

ON

a b

f

e d c

b c

a g

b

e

d

a g

b c

d

f

0

1

0

0

OFF

ON

ON

OFF

OFF

ON

ON

0

1

0

1

ON

OFF

ON

ON

OFF

ON

ON

f

0

1

1

0

ON

OFF

ON

ON

ON

ON

ON

f

0

1

1

1

ON

ON

ON

OFF

OFF

OFF

OFF

1

0

0

0

ON

ON

ON

ON

ON

ON

ON

f

1

0

0

1

ON

ON

ON

OFF

OFF

ON

ON

f

b g

c

a

g d

c

g

a

e d c

a b c

a g b

e d c

a b g c

1112

Electronic Devices and Circuits

The basic construction of 14-segment and 16-segment LED displays and the characters are shown in Figures 22.50 and 22.51. a f

j b

h i g1

e m

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

g2 l

k c

1dp

d

Figure 22.50 14-segment LED display

a1

a2

f h i g1

j b

0000

0001

0010

0011

0100

0101

0110

1001

1010

1011

1100

1101

1110

1111

0111

1000

g2

e m l k c d1

1dp

d2

Figure 22.51 16-segment LED display

1

LED1

In a dot matrix display, the LEDs are arranged as a 4 × 5 or 5 × 7 or 8 × 8 array as shown in Figure 22.52.

Row selector

5

Column selector 1 23 4 2

3

4

6

7

8

2 3 4 5

12

9

10

13

14

15

16

17

18

19

20

11

COL. 1 2 3 4

1 2 3 4 5 ROW

Figure 22.52 Dot matrix display

A ROM memory and the desired segments are selected to display the characters as shown in Figure 22.52.

22.3.4 Liquid Crystal Display In a solid, the molecules have fixed orientation; whereas in a liquid, they can move around to different positions. Liquid crystals are neither solids nor liquids. The molecules in liquid crystals tend to maintain their orientation, such as the molecules in a solid, but at the same time can move around to different positions, such as the molecules in a liquid.

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1113

Liquid crystal display (LCD) consists of a liquid crystal material embedded between a pair of transparent electrodes. The characteristic of a liquid crystal is that it controls the phase of the light passing through it by the application of the voltage between the electrodes. If such a unit is placed between a pair of plane polarization plates, then light can pass through it only if the correct voltage is applied. Consider a single-pixel area in LCD. There are two polarization filters oriented at 90° to each other. The vertical polarization filter polarizes the incident unpolarized light vertically and the horizontal polarization filter polarizes the light horizontally. If no voltage is applied between the electrodes, the orientation of molecules will remain twisted at 90°, and the light passes through the outer polarization filter, thus pixel is illuminated (Figure 22.53). Alternately, if reasonably large voltage is applied, the molecules in the liquid crystal layer untwist. The orientation of the light also changes. The result is that light is blocked by the horizontal polarization filter, and hence the pixel appears black (Figure 22.54). This is how black and white images or characters are produced. By arranging small pixels together as a matrix, it is possible to show different sizes of images and characters. By controlling the voltage applied between liquid crystal layers in each pixel, light can be allowed to pass through outer polarization filter in various amounts, so that it is possible to produce different gray levels on the LCD screen. Horizontally polarized light

V

Vertically polarized light

Light output

Unpolarized light

Orientation of liquid crytal molecules Transparent glass eletrodes Vertical polarization filter

Horizontally polarized filter

Figure 22.53 Twisted liquid crystal molecules with no voltage applied

Vertically polarized light

Horizontally polarized light

V

No Light output

Unpolarized light

Orientation of liquid crytal molecules Transparent glass eletrodes Vertical polarization filter

Horizontally polarized filter

Figure 22.54 Untwisted liquid crystal molecules on the application of voltage

1114

Electronic Devices and Circuits

There are a variety of liquid crystal substances. A nematic liquid crystal is one in which the molecules have a definite order or pattern. Molecules in a twisted nematic (TN) are naturally twisted. On the application of a voltage to these liquid crystals, the molecules untwist to varying degrees, depending on the voltage. LCDs use these liquid crystals because they react predictably to electric current in such a way as to control light passage.

22.3.5 Plasma Display Panels A plasma display consists of fluorescent lights that cause the formation of an image on screen (Figure 22.55). In plasma display, millions of tiny cells containing gases such as xenon and neon are sandwiched between two sealed glass plates having horizontal and vertical gold electrodes. These gold electrodes are covered with dielectric material with parallel electrodes deposited on their surfaces. The gold electrodes placed in right angles create pixels. Each pixel has three composite colored subpixels. When they are mixed proportionally, the correct color is obtained. Under normal conditions, the gas has only uncharged particles. When a voltage pulse passes between two electrodes, the gas breaks down and produces weakly ionized plasma, which emits UV radiation. The UV radiation activates color phosphors and visible light is emitted from each pixel. Rear glass plate Horizontal gold electrodes Neon gas panel Cells Vertical gold electrodes

Front glass plate

Figure 22.55 Plasma display

22.4

FIBER OPTICS

Fiber optics deals with the transmission of light along transparent fibers of glass, plastic, or a similar medium. Optical fibers are long, thin strands of glass (SiO2) about the diameter of human hair. When optical fibers are arranged in bundles, then the bundle is called an optical cable. Optical fibers are used to transmit information through light signals over long distances. Optical fibers offer the following advantages: Optical fibers have (i) a wider bandwidth, ranging from 1 to 1000 GHz, (ii) lower transmission loss per unit distance, and (iii) are free from electromagnetic interference (EMI). An optical fiber consists of a core having a refractive index n1 and a cladding having a refractive index n2 and n1 > n2 (Figure 22.56). The core transmits an optical signal, whereas the cladding guides the light within the core. Since light is guided through the fiber, it is sometimes called an optical waveguide. Light rays travel through tiny optical fibers based on the principle of total internal reflection.

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1115

Cladding refractive index n2 Core refractive index n1

n1 > n2

Figure 22.56 Optical fiber

22.4.1 Refractive Index Light travels at 299,792,458 meters/s or 186,282 miles/s in vacuum. Refractive index, n of a transparent material is defined as follows: n = c/v (22.19) where c and v are the velocities of light in vacuum and the transparent material, respectively. The velocity of light is smaller when it passes through a transparent material and the decrease in the velocity depends on the refractive index of the material. Light travels in straight lines through optical materials. But the rays bend when they pass through a boundary between two materials having different refractive indices. This phenomenon is called refraction (Figure 22.57). Normal

Air rarer medium B

q2 O

v1

n1

v2

n2

q1 A

Denser medium glass

Figure 22.57 Refraction of light

Snell’s law states that

or

sin q1 n1 v2 = = sin q 2 n2 v1

(22.20)

n2 sin q1 = n1 sin q 2

(22.21)

where v1 and v2 are the velocities of light in rarer medium(air) and denser medium (glass), respectively. n1 ( = 1) and n2 ( = 1.5 ) are the refractive indices of rarer medium(air) and denser medium (glass), respectively. q1 is the angle of incidence and q 2 is the angle of refraction. From Eqn. (22.21), 1.5 sin q1 = 1sin q 2 or q 2 > q1 (22.22)

1116

Electronic Devices and Circuits

Equation (22.22) tells that light is bent away from the normal. As q1 increases to q c , q 2 = 90° and sin q 2 = sin 90° = 1. The refracted wave just grazes the interface. q c is called the critical angle. When the incidence angle q1 > q c , Snell’s law tells that refraction cannot take place and all light rays are reflected back into the glass. This phenomenon is called total internal reflection (Figure 22.58). n  q c = sin −1  1   n2 

(22.23)

If n1 = 1 and n2 = 1.5 as in the present case  1  q c = sin −1   = 41.81°  1.5 

B

B2

r1

A

X

Rarer medium (Air)

B1

A1

A2 i2

i1

r2

A3 r3 qc

B3

A4 r4

i3

Y

i4 B4

O Denser medium (Glass)

Figure 22.58 Total internal reflection

Consider an optical fiber with the core having refractive index of n1 and the cladding a refractive index of n2 .Let a light ray (ii) meet the core at an angle a , which eventually will result in a ray that meets the core-cladding interface at the critical angle, q c . Any light ray incident at the fiber core with an angle greater than a [ray (i) ] will not be refracted sufficiently to undergo total internal reflection at the core–cladding interface. Therefore, although ray (i) enters the core, it will not be accepted into the fiber for onward transmission. This ray will be lost in the cladding (Figure 22.59). The rays that fall in the range 2a will propagate in the fiber. Figure 22.60 shows the acceptance cone.

Air n3

Cladding n2 Core n1

B

Ray outside acceptance angel is lost in cladding

qc

A a Acceptance angle

(ii)

C

(i)

Figure 22.59 Acceptance angle

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1117

Cladding n2 Core n1

qc a

Acceptance cone

Figure 22.60 Acceptance cone

Acceptance angle is measured in air (n3 ≈ 1) outside the fiber. The acceptance angle is usually called as Numerical Aperture (NA) and is given as NA = n3 sin a = 1 × sin a = n12 − n22

(22.24)

If for a typical fiber n1 = 1.48 and n2 = 1.46, then from Eqn. (22.24), NA = n12 − n22 =

(1.48)2 − (1.46)2

= 0.242

If NA = 0.242, then a = sin −1 ( 0.242 ) =14°. This means that if a > 14°, the ray is not accepted for transmission through the core. Let Δ be the relative refractive index. Δ is defined as follows: ∆=

n1 − n2 n12 − n22 ≈ n1 2 n12

(22.25)

when Δ is small. From Eqn. (22.25), 2 ∆ n12 = n12 − n22 or

n12 − n22 = n1 2 ∆

(22.26)

Substituting Eqn. (22.26) in Eqn. (22.24), NA = n12 − n22 = n1 2 ∆

(22.27)

Equation (22.27) says that NA depends only on n1 and Δ.

22.4.2 Types of Optical Fibers Optical fibers are used to transmit information in the form of light through an optical waveguide made of glass fibers. Information is transferred through the fiber as a series of light pulses. The advantages with optical fibers are (i) less attenuation (ii) higher bandwidths, and (iii) immunity from electromagnetic disturbances. Optical fibers have a transparent core surrounded by a transparent cladding material which are made from a type of glass known as silica (SiO2), which is almost transparent in the visible and near-infrared. Light is made to travel through the core by total internal reflection. Fibers are classified in terms of mode of transmission as follows: (i) Fibers that support a single propagation path or transverse mode are called single-mode fibers. Single-mode fibers are used

1118

Electronic Devices and Circuits

for long distance communication links. A single-mode fiber optical cable has a core of small diameter that allows only one mode to propagate. In a single-mode fiber, the core to the cladding diameter ratio is 9–125 µ.(ii) Fibers that support many propagation paths or transverse modes are called multimode fibers. Multimode fibers generally have a wider core diameter that allows multiple modes to propagate and are used for high-power short-distance communication links. Based on the refractive index profile of the core and cladding, optical fibers are classified into two types:(i) step index fibers and (ii) gradedindex fibers.

Step-Index Fiber A step-index fiber is an optical fiber that exhibits a step-index profile, that is, the refractive index remains constant throughout the core of the fiber, while there is an abrupt decrease in the refractive index at the interface between the core and the outer covering, or cladding. The light in the fiber propagates by bouncing back and forth from core–cladding interface. In a multtimode fiber, the core-to-cladding diameter ratio is 50–125 µ and 62.5–125 µ. The step-index profile can be used for both single-mode transmission (Figure 22.61) and multimode transmission (Figure 22.62).

r

r

n(r) Core

a Cladding

n1 n2

Figure 22.61 Single-mode step-index fiber

r Refractive index n(r)

r

a Core Cladding

n1 n2

Figure 22.62 Multimode step-index fiber

Multimode step-index fibers have the problem of dispersion. Dispersion is the spreading out of a light pulse in time as it travels through the fiber. Each mode enters the fiber at a different angle and thus travels at different paths in the fiber. Since each mode ray travels a different distance as it propagates, the rays arrive at different times at the fiber output. Therefore, the light pulse spreads out in time that can cause signal overlapping, which means that the signals cannot be distinguished from one another (Figure 22.63).

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1119

Input

Output Mode 1 Mode 2 Mode 3

Figure 22.63 Modal dispersion in a multimode step index fiber

In an optical fiber, the normalized frequency, V (also called the V number), is given by V=

2pa 2 2pa n1 − n22 = ×NA l l

(22.28)

The total number of guided modes M for a step-index fiber is approximately related to the V number (for V> 20) as follows: M=

V2 2

(22.29)

Equations (22.28) and (22.29) indicate that the total number of modes increases with increasing NA. Example 22.2 Calculate the V number and number of modes propagating through the fiber having a = 50 μm, n1 = 1. 53, n2 = 1.50, and l = 1μm. Solution:

2pa 2p × 50 × 10 −6 = = 314 l 1 × 10 −6 2

2

n12 − n22 = (1.53) − (1.50 ) = 0.091 n12 − n22 = 0.091 = 0.30 V=

2pa 2 n1 − n22 = 314 × 0.30 = 94.2 l 2

M=

V 2 (94.2 ) = = 4437 2 2

Example 22.3 A single-mode step-index fiber transmits a light wave having l=850 nm. Find the radius of the core with n1 = 1.480 and n2 = 1.465. Assume that V = 2.405.

1120

Electronic Devices and Circuits

Solution: V =

2pa 2 2 2 n1 − n22 ⇒ n12 − n22 = (1.48) − (1.465) = 0.044 l n12 − n22 = 0.044 = 0.21 Vl

a=

2p n12 − n22

=

2.405 × 850 × 10 −9 = 1.550 µm 6.28 × 0.21

Graded-Index Fiber In a graded-index fiber, the refractive index of the core is made to vary as a parabola with refractive index being maximum at the center of the core (Figure 22.64). The parabolic variation of the refractive index in the core smoothly bends the light rays as they approach the cladding. This reduces modal dispersion. n2

r

r

n1 a O Cladding n2

Figure 22.64 Multimode graded-index fiber

For a graded-index fiber M=

V2 4

(22.30)

22.4.3 Optical Communication Link An optical communication link consists of the transmitter, the cable, and the receiver. An optical fiber link is shown in Figure 22.65. Information source

Modulator

Received signal

Fiber optic channel

Optical source

Amplifier

Photo detector

Figure 22.65 Optical fiber link

Optical signal processing

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1121

The data to be transmitted is fed to the modulator that encodes the data appropriately for transmission through the fiber. The modulator drives the light source (LED or laser) and the light is focussed into the fiber. As the light travels through the channel, it undergoes dispersion and attenuation. An optical signal processor processes the signal and the signal is detected by a photodetector. The electrical output of the photodetector is amplified and the transmitted signal is received at the output of the receiver. The important feature of light propagation in a fiber is that it can bend around corners and the light will be guided without losses at the bends. For minimal loss around the bend, the radius of the bend should be relatively large (Figure 22.66). When a bend is encountered, the angle of incidence of the ray with core–cladding interface may become greater than the critical angle. As such, some light may leak to the cladding and may be lost.

Figure 22.66 Propagation around a bend in a fiber

22.5

MEASURING INSTRUMENTS

When electrical quantities such as current, voltage, power, frequency, etc., are to be measured, there is a need for measuring instruments. Some of the electrical quantities to be measured may be either dc current and voltage or ac current and voltage. The measuring instruments can either be analog or digital instruments. The two basic instruments that are meant for measuring current and voltage are presented below:

22.5.1 DC Ammeter D’Arsonval galvanometer is a dc ammeter. It is an instrument for measuring small electrical currents by deflection of a light-weight moving coil. The D’Arsonval instrument consists of a coil of wire suspended from a metallic ribbon between the poles of a permanent magnet. The magnetic field produced by a current passing through the coil produces a torque. The coil, to which an indicating needle is attached, rotates under the action of the torque. The angle through which the needle or pointer rotates to balance the torsion of the suspension provides a measure of the current flowing in the coil (Figure 22.67). The leads of the coil are the meter terminals. The coil resistance Rm determines the current I m .

scale Spring Pointer S Permanent magnet

N

Moving coil Spring

Core

Figure 22.67 PMMC instrument

1122

Electronic Devices and Circuits

PMMC meter can carry only small currents in the order of μA to 1mA, because the coil winding is small and light. To be able to measure a large current, an external shunt resistor is to be connected so that only a fraction of the total current passes through the meter (Figure 22.68). From Figure 22.68, I m Rm = I s Rs ⇒ I s =

I m Rm Rs

(22.31)

I +

Im Is Rs

V

Rm

−

Figure 22.68 Extending the range of the ammeter

Also

(22.32)

Is = I − I m From Eqs (22.31) and (22.32), I m Rm = I − Im Rs

Rs =

⇒

I m Rm I − Im

(22.33)

Equation (22.33) implies that to get a full-scale deflection of I, Rs is the required shunt resistance. Example 22.4 A PMMC meter has an internal resistance of 10 Ω and full-scale range of 1mA. Find Rs needed to increase the meter range to 5A. Solution: Rs =

I m Rm 1 × 10 −3 × 10 0.01 = = = 0.002 Ω −3 I − Im 5 − 0.001 5 − 1 × 10

A multirange ammeter can be designed by selecting shunt resistances depending on the fullscale deflection and using a range selector switch (Figure 22.69).

I +

Im Rs3

V

−

Is3

Is2 3 Range selector swithc

Rs2 Is1 2

Rs1

1

Figure 22.69 Multirange ammeter

Rm

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1123

Example 22.5 A PMMC meter has an internal resistance of 10 Ω and full-scale range of 1 mA. Design a multirange meter to give full-scale ranges of 10 mA,100 mA,1 A, 10 A, and 100 A. Solution: I m = 1 mA and Rm = 10 Ω Rs =

I m Rm I − Im

Rs1 =

I m Rm 1 × 10 −3 × 10 = = 1.11 Ω I − I m (10 − 1)10 −3

Rs3 =

I m Rm 1 × 10 −3 × 10 = = 0.01 Ω I − I m (1000 − 1)10 −3

Rs5 =

Rs 2 =

I m Rm 1 × 10 −3 × 10 = = 0.101 Ω I − I m (100 − 1)10 −3

Rs 4 =

I m Rm 1 × 10 −3 × 10 = = 0.0010 Ω I − I m (10000 − 1)10 −3

I m Rm 1 × 10 −3 × 10 = = 0.00010 Ω I − I m (100000 − 1)10 −3

The designed circuit is shown in Figure 22.70. The problem with this arrangement is that when the switch moves from one position to another, say from position 1 to position 2, for a short duration Rs is infinity, resulting an excessive current through the meter that may damage it. To avoid such a contingency, the rotary switch having make-before-break contact can be used (Figure 22.71). The wiper contact is so wide that it makes contact with position 2 before breaking the contact with position 1.

I Im

+ Rs4

Rs5

Rs3

Rs2

Rs1 Rm

Is5

Is4

Is3

Is2

4 5 −

2

3

V

100A

Is1

1

1A 100mA 10A

10mA

SW

Figure 22.70 Designed multirange ammeter

1124

Electronic Devices and Circuits

2

1 Wiper

3

4

A

Figure 22.71 Make-before-break contact

Example 22.6 A PMMC instrument used as an ammeter has a coil resistance of Rm = 10 Ω and FSD current of 1 mA. If Rs = 1Ω, determine the total current passing through the ammeter at (i) FSD, (ii) 0.5 FSD, and (iii) 0.25 FSD. Solution: (i) At FSD, I m = 1 mA. Therefore, V = I m Rm = 1 × 10 −3 × 10 = 10 × 10 −3 V Also, V = I s Rs = 10 × 10 −3 V

Is =

10 × 10 −3 = 10 mA 1

I = I m + I s = 1 + 10 = 11 mA (ii) At 0.5 FSD, I m = 0.5 × 1 = 0.5 mA. Therefore, V = I m Rm = 0.5 × 10 −3 × 10 = 5 × 10 −3 V Also, V = I s Rs = 5 × 10 −3 V

Is =

5 × 10 −3 = 5 mA 1

I = I m + I s = 1 + 5 = 6 mA (iii) At 0.25 FSD, I m = 0.25 × 1 = 0.25 mA. Therefore, V = I m Rm = 0.25 × 10 −3 × 10 = 2.5 × 10 −3 V Also, V = I s Rs = 2.5 × 10 −3 V I = I m + I s = 1 + 2.5 = 3.5 mA

Is =

2.5 × 10 −3 = 2.5 mA 1

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22.5.2 DC Voltmeter A PMMC meter can be converted as a dc voltmeter by connecting a series resistance as shown in Figure 22.72. I +

Im

Rs

Rm

V

−

Figure 22.72 DC voltmeter

From Figure 22.72, The total resistance in the series loop is R = Rs + Rm or (22.34)

Rs = R − Rm Also, Rs + Rm =

V V or Rs = − Rm Im Im

(22.35)

Example 22.7 A PMMC having Rm = 10 Ω and the current through the meter is 1mA. The meter is to read a full-scale deflection of 10V. Find Rs. Solution: Rs =

V 10 − Rm = − 10 = 9.99 kΩ Im 1 × 10 −3

22.5.3 Multirange Voltmeter In a multirange voltmeter, the rotary switch selects a required series resistance that gives the desired full-scale deflection as shown in Figure 22.73. V1

I

1

Rs1 Im Rm

2 Rs2

+

V2 3

V3

Rs3

Figure 22.73 Multirange voltmeter

Meaured voltage −

1126

Electronic Devices and Circuits

Rs1 =

V V V1 − Rm , Rs2 = 2 − Rm , and Rs3 = 3 − Rm Im Im Im

Example 22.8 A PMMC meter has a coil resistance 100Ω and a full-scale deflection current of 100μA is used in the voltmeter circuit as shown in Figure 22.73. Determine the required values of resistances if the voltmeter ranges are 1V, 10V, and100V. Solution: Rs1 =

V1 1 − Rm = − 0.1 = 9.9 kΩ Im 100 × 10 −6

and

Rs2 =

V2 10 − Rm = − 0.1 = 99.9 kΩ Im 100 × 10 −6

Rs3 =

V3 100 − Rm = − 0.1 = 999.9 kΩ Im 100 × 10 −6

22.5.4 Moving-Iron Instruments Moving-iron instruments are used to measure alternating currents and voltages. Moving-iron instruments are of two types: (i) repulsion type and (ii) attraction type. Repulsion-type movingiron instrument consists of two cylindrical soft iron vanes mounted within a fixed current-carrying coil. One iron vane is held fixed to the coil frame and the other iron vane, fixed to a pointer, can rotate freely. Current flowing through the coil creates a magnetic field, which magnetizes the two irons. The similarly magnetized vanes repel each other, resulting in a proportional rotation. Rotation is opposed by a hairspring that produces the restoring torque. The deflecting torque is proportional to the square of the current in the coil (Figure 22.74). As in the case of the dc meter, here also a shunt may be connected to extend the range of the ammeter. But a shunt used in this

Pointer Hair spring

Shaft attached to moving vane

Fixed cylindrical coil

Coil leads Moving iron vane

Fixed iron vane

Figure 22.74 Repulsion-type moving-iron meter

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1127

case also will have to have an inductor, and it is difficult to design a shunt with the appropriate inductance (Figure 22.75). As such, a shunt is not used in a moving iron ammeter to extend its range. However, the range of the ammeter can be extended by using multiple range coils that can be connected in series, parallel, or series–parallel combination. Lm I

Rm I

Im Is Ls

Rs

Figure 22.75 Shunt to change the range

22.5.5 Moving-Iron Voltmeter Voltmeter range may be altered connecting a resistance in series with the coil (Figure 22.76).

Rs Rm

V v

Load

Lm

Figure 22.76 MC voltmeter

2

v = Rm2 + (wLm )

Range multiplier =

V = v

V=

(Rm + Rs )2 + (wLm )2

(Rm + Rs )2 + (wLm )2 2 Rm2 + (wLm )

(22.36)

22.5.6 Ohm Meter An ammeter can be used to measure resistance. To convert an ammeter into an ohmmeter, an external battery is attached in series with the ammeter (Figure 22.77(a)). This will drive a current through an external unknown resistance, RX and measure the resulting current using the galvanometer. The ammeter can be calibrated in terms of ohms. From Figure 22.77(b), it can be noted that when current is maximum the resistance is minimum and when the current is zero, the resistance is .

1128

Electronic Devices and Circuits

Resistance

V Ammeter measures resistance

Rx

0

¥ 0

Current

(a) Circuit

(b) Meter reading Figure 22.77 Measurement of resistance

22.5.7 Multimeter A multimeter is a versatile measuring instrument that can be used as a voltmeter, ammeter, and ohmmeter. It can be used to measure ac and dc voltages and currents, and resistance. An analog multimeter is shown in Figure 22.78. A selector switch SW1 is used for selecting the variable to be measured, namely, current (A), voltage (V), or resistance (Ω). When SW1 is in position A, any of the shunt resistors, Rs1, Rs2, or Rs3, may be selected by SW3 as one of the shunt resistances for the ammeter to have the desired full-scale deflection. When SW1 is in position V, any of the series resistors, Rm1, Rm2, or Rm3, may be selected by SW2 as one of the range multipliers to have the desired full-scale deflection. While SW1 is in Ω position, V1 or V2 is selected by SW4, for measuring resistance. Ammeter

OFF Rs1

A

Rm1 SW3

SW2 V SW1 Rm2

Rs2 Common terminal

Rs3

Ω

Rm3

SW4

A V Ω

R

V2

V1

Figure 22.78 Analog multimeter

The resistance offered for volt of full-scale deflection by the multimeter is called its sensitivity. If V is the voltage to be read by the meter and Im is the FSD of the PMMC, then Meter resistance =

V Im

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

and meter sensitivity = resistance per volt full-scale deflection =

1129

V /I m 1 = Ω /V V Im

1 = If a multimeter has a full-scale deflection current of 0.1mA, then its sensitivity is 0.1 × 10 −3 10,000Ω/V.

22.5.8 Electronic Voltmeters The analog multimeter has small input resistance. The main advantage with electronic voltmeter is its very high input resistance, which avoids loading the source.

Electronic Voltmeter for dc Measurement Electronic voltmeters for measuring dc voltages can be of two types: (i) dc voltmeter using a direct-coupled amplifier and (ii) dc voltmeter using a chopper-type dc amplifier. (i) Dc voltmeter using a direct coupled amplifier: The block diagram of the dc voltmeter is shown in Figure 22.79.

DC input to be measured

Range selector

DC amplifier

PMMC meter

Figure 22.79 Block diagram of a dc voltmeter

A practical dc voltmeter circuit is shown in Figure 22.80. The circuit is a symmetric circuit. Therefore, when the dc input voltage is zero, the voltages at the drain terminals of Q1 and Q2 are required to be the same. However, there can be some imbalance between the two halves that may VDD

Zero adjust RX RD 1V

VG1

6MΩ 3V 2.1MΩ DC input to + be measured −

10V 0.6MΩ

Range selector

Q1

RD

Calibration Y

X

Q2 RY

MC meter

Rs

30V 210MΩ 100V 90KΩ

Figure 22.80 A practical electronic voltmeter

1130

Electronic Devices and Circuits

result in the meter reading a small voltage. To make the reading of the meter zero when the input dc voltage is zero RX is included and by adjusting RX, the meter can be made to read zero volts. By applying an input voltage of 1V, the calibration resistance RY is adjusted for full-scale deflection to read 1V. When 10V is applied as input, the range selector switch is kept at 10V position. In this position, the voltage applied to the gate of Q1 is VG1 = 10 ×

900 × 103 =1V 9 × 106

since 10V appears across 900kΩ and the total resistance is 9MΩ.1V at the gate of Q1 gives fullscale deflection of the meter. Obviously, the measured voltage is 10V. Alternately, when 100V is applied as input, the range selector switch is kept at 100V position. In this position, the voltage applied to the gate of Q1 is VG1 = 100 ×

90 × 103 =1V 9 × 106

since 100V appears across 90kΩ and the total resistance is 9MΩ.1V at the gate of Q1 gives fullscale deflection of the meter. Obviously, the measured voltage is 100V. (ii) Chopper-type dc voltmeter: The main drawback of the type of dc voltmeter shown in Figure 22.80 is that it is difficult to design a dc amplifier without drift. Alternately, it is relatively much easier to design an ac amplifier. In a chopper-type dc voltmeter, the dc voltage is first converted into a square wave by the chopper modulator and this ac voltage is amplified by an ac amplifier. The output of the amplifier is again converted into dc by the chopper demodulator and is measured by the meter (Figure 22.81). DC input

Chopper modulator

AC amplifier

Chopper demodulator

Lowpass filter

PMMC meter

Figure 22.81 Block diagram of chopper-type dc voltmeter

Photodiodes are used in chopper amplifier as modulators and demodulators. It is already known that the resistance of a photodiode becomes very small (in the order of ohms) when illuminated by a light source and its resistance becomes very large (few mega-ohms) when not illuminated. This characteristic can be used to convert a dc voltage into a square wave (Figure 22.82).D1 and D2 are photodiodes. D1 - Not illuminated

D1 - illuminated D2 - Not illuminated

Vdc

D1 Vdc

D2

D2 - Illuminated

Vo T/2

T/2

Figure 22.82 Chopper modulator

0

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1131

T , the resistance of D2 is 2 T very small and that of D1 is very large. Hence, Vo ≈ 0. If now for another time duration , D1 is 2 illuminated and D2 is not illuminated, then Vo ≈ Vdc . The circuit diagram of a chopper-type dc voltmeter using photodiodes is shown in Figure 22.83. When D2 is illuminated and D1 is not illuminated for a time duration

AC amplifer C

DC input to + be measured −

C

D1

D4

D2

Square wave oscillator (Chopper driver)

N1

D3

Neon tube

Lowpass filter C

Amplified dc output

N2 Neon tube

Figure 22.83 Chopper-type dc voltmeter

A square wave generator drives the neon tubes N1 and N2. The input to N2 is inverted, which means that when N1 is ON, N2 is OFF. N1 illuminates D1 and D4, whereas and N2 illuminates D2 and D3. The input dc voltage is converted to square wave (ac signal) by chopping. The peak amplitude of the square wave is equal to the input dc voltage. The chopped voltage is fed to an ac amplifier. The amplified signal is chopped in synchronism with the input chopper. The synchronized chopping gives a dc output voltage that is proportional to the input voltage. This output is passed through the low-pass filter to remove any residual ac component. Now this dc output voltage is measured by the PMMC meter. The chopper amplifier dc voltmeter is highly sensitive voltmeter and has input resistance of the order of hundred mega-ohms.

Electronic Voltmeter for ac Measurement In the block diagram shown in Figure 22.84, the ac voltage to be measured is attenuated to an acceptable level and then is rectified and filtered. This dc voltage is the input to a dc amplifier that amplifies the signal and is read by a dc meter. However, the main limitation of this method of measurement of ac voltages is the design of the dc amplifier with sufficient temperature compensation, to avoid the problem of drift.

AC input to be measured

Attenuator

Rectifier and filter

DC amplifier

Meter

Figure 22.84 Block diagram for an electronic ac voltmeter

AC voltmeters can be classified as (i) average reading voltmeters, (ii) peak reading voltmeters, and (iii) peak-to-peak reading voltmeters.

1132

Electronic Devices and Circuits

(i) Average reading voltmeter: This meter reads the average value of a positive half cycle or a negative half cycle of the ac input depending on how the diode D is connected. For the given diode representation as shown in Figure 22.85, the diode conducts only during the positive half cycle of the ac input and develops a dc voltage across R. This dc voltage is amplified by the dc amplifier and is read by the meter. If the diode terminals are reversed, the meter indicates a negative voltage. D

AC input

R

To dc amplifier

Figure 22.85 Circuit arrangement for an average reading voltmeter

(ii) Peak reading voltmeter: The circuit in Figure 22.86 enables the measurement of the peak of the input ac voltage. C +

− Vm AC input

D

R To dc amplifier

Figure 22.86 Circuit arrangement for peak reading voltmeter

During the negative-going half cycle of the input ac voltage, D conducts and C charges to Vm , the peak of the input. During the positive going half cycle D is OFF. The output corresponds to the positive peak of the input that is applied as input to the dc amplifier. (iii) Peak-to-peak detector D2

Vm +

− + AC input

To dc amplifier

C1

+ D1

C2

2Vm −

−

Figure 22.87 Circuit diagram for a peak-to-peak reading voltmeter

During the negative-going half cycle of the ac input, diode D1 becomes forward biased. C1 charges up to Vm the negative peak voltage. When voltage V1 goes positive, D1 is OFF and D2 is ON. C2 charges to2Vm (Figure 22.87).

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1133

Alternately, it is much easier to design an ac amplifier. Therefore, the block diagram of an ac voltmeter shown in Figure 22.88 uses an ac amplifier and its output is rectified and is measured by the dc meter.

AC input to be measured

Attenuator

Rectifier and filter

AC amplifier

Meter

Figure 22.88 Alternate block diagram for an electronic ac voltmeter

22.5.9 Digital Voltmeters In analog voltmeters, the display is by a pointer reading on a PMMC meter. Digital voltmeter enables a numerical readout, which eliminates strain on the observer. Only ramp-type and dualslope digital voltmeters are considered.

Ramp-Type Digital Voltmeter In a ramp-type digital voltmeter, the time taken for the ramp to reach from 0V to the level of the input voltage or to decrease from the input voltage to 0V is measured. A start–stop mechanism is incorporated. The measurement starts on receiving a start signal that enables the gate to count the pulses using a counter. At the end of the time period, a stop signal is received, which disables the gate. The number of pulses counted by a counter during this time interval is a measure of the input voltage. The block diagram of the ramp-type voltmeter and the waveforms are shown in Figures 22.89 and 22.90, respectively. Input voltage

Comparator 1

Attenuator Start pulse Clock

Gate

Counter

Digital readout

Stop pulse

Ramp generator Comarator 2 Sample rate multivibrator

Figure 22.89 Block diagram of ramp-type digital voltmeter

The voltage to be measured is applied as input to a range selector attenuator. The sample rate multivibrator triggers the ramp generator. The output of the ramp generator and the attenuated input voltage are the two inputs to comparator1. When the amplitude of the ramp is equal to the input voltage to be measured, the start pulse from comparator 1 generates the gating signal and the clock pulses will be counted by the counter. When the ramp voltage reaches 0V, comparator 2 sends the stop pulse, ending the gate pulse. The gate is enabled for a time T, for which duration the counter counts the clock pulses. The number of pulses counted is a measure of the input voltage. The sample rate multivibrator generates the next pulse to initiate the next ramp. The main

1134

Electronic Devices and Circuits

limitation of this type DVM is that the integrator must produce a linear ramp for the count to be a measure of the input voltage.

+15V

Voltage measured

Ramp 0

t Start pluse

Stop pluse

-15V Gating pulse

T

Clock pulses to the counter

Figure 22.90 Waveforms of the ramp-type digital voltmeter

Dual-Slope Integration-Type Digital Voltmeter In the dual-slope digital voltmeter, the output of the integrator has positive slope for a fixed time interval t1 and has negative slope for a different time interval t2 , and hence the name dual-slope meter. The block diagram of the dual-slope voltmeter is shown in Figure 22.91. VX is the input voltage to be measured. If VX is positive, it is inverted to get positive slope at the output of the integrator. At the start of measurement, the counter is reset. When VX is connected, the output of the integrator increases linearly with a positive slope for a fixed time interval t1 (starting at Vo = 0V). Depending on the magnitude of VX, the output increases with a variable slope. At t = t1, let Vo = V1. V1 =

−VX t1 RC

(22.37)

At t = t1, the switch is connected to VR. At this instant, the control logic enables the counter to start counting the clock pulses. The output of the integrator now decreases with a negative slope and at t = t2, when the output of the integrator reaches 0V, the control logic sends stop pulse to the counter and the counter stops counting. V2 =

−VRt2 RC

Since

V1 = V2 ,

−VX t1 −VRt2 = RC RC

or

VX = VR

t2 = Kt2 t1

(22.38)

(22.39)

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1135

where K=

VR t1

(22.40)

VX is directly proportional to t2 . The counter is run for a duration t2 and its display is a measure of VX. C Vx

Comparator

R Vx

Vo

− +

VR

− +

Vc

Integrator

Control logic Clock

Counter

Readout

Figure 22.91 Block diagram of the dual-slope voltmeter

The integrator output for different values of VX is shown in Figure 22.92. Constant slope proportional to VR

Vairable slope proportional to VX

V1 = V2 Vo

0

t1

t

t2 t′2 t2’’

Figure 22.92 Integrator output for different VX

1136

Electronic Devices and Circuits

1 1 A DVM sometimes may be called as a 3 or a 4 digit meter and so on. A 3-digit meter will read 2 2 from 000 to 999. Another digit is provided to the left of the 3 digits and this can take the values of 0 or 1 only and hence is called a half digit. A 3-digit meter will read from 000 to 999 mV, if 1 the full-scale range is 1V and the smallest increment is 1mV. The resolution of a DVM, R = n , 10 1 where n is the number of digits. Therefore, for a 3-digit meter R = 3 = 0.001 or 0.1 percent. 10 A 3½-digit meter can read from 0000 to 1999. It can resolve the input signal into 1999 parts. A meter with enabled half-digit is used to indicate that the applied input has exceeded the meter’s measurement capability (Figure 22.93).

Half digit (0 to 1)

Full digit (0 to 9)

Figure 22.93 3

1 digital display 2

The simplified block diagram of the digital multimeter is shown in Figure 22.94. The meter enables the measurement of ac and dc voltages, dc current, and resistance.

Attenuator DC V DC V SW1A Input

AC V

Compensated attenuator

SW1B AC V DC mA W

Rectifier

DC mA W

ADC

Current to voltage converter

Counter Constant current source

Display

Figure 22.94 Digital multimeter

In each of the measurements, further range selection switches are to be used.

Measurement of Power If V is the voltage across a resistance in a circuit and I is the current through it, then the dc power in it is VI . Also I 2 R =

V2 . R

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1137

However, when it comes to measuring power in an ac circuit, if v and i are the ac components of voltage and current, where v = Vm sin wt = V sinq and i = I sin (wt − j ) = I sin(q − j ) Therefore, p = vi = V sin q × I sin(q − j ) The average power P is 2p

P=

1 VI sin q sin(q − j )dq = VI cosf 2p ∫0

(22.41)

where V and I are the RMS values of current and voltage, j is the phase angle between V, and I and cosj is the power factor. At power-line frequencies, a wattmeter is used to measure power. A dynamometer-type wattmeter is shown in Figure 22.95. Two fixed current coils are connected in series with the load and I is the current through them. The movable pressure coil is placed in the magnetic field of the two fixed current coils and is connected across the input with a series resistance R, which is very large to make the current through it negligible. Moving coil Pressure coil I Current coil V Fixed coil

Current coil Fixed coil

R

Load

Figure 22.95 Dynamometer-type wattmeter

The deflecting torque is proportional to the true power. Td a VI cos j

(22.42)

Measurement of Power Using a Bolometer RF power is measured using the bolometer method. A bolometer may be a short ultra-thin wire having a positive temperature coefficient(called baretter) or a bead of semiconductor having a negative temperature coefficient (called thermistor). In the bolometer method of power measurement, the power to be measured is made to heat a bolometer element. The rise in temperature changes the resistance of the bolometer. The change in the bolometer resistance is measured by an auxiliary bridge circuit (Figure 22.96).

1138

Electronic Devices and Circuits

R1

R1 R G E

Bolometer element

Audio and/or RF generator

DC bias

R1

Rx

V

Figure 22.96 Measurement of power using bolometer

The bolometer element is heated by the dc, audio, and the RF power simultaneously. The resistance of the bolometer depends on the total power. An audio voltage V is superimposed on the RF signal whose power is required to be measured. The dc current from the bias source E is varied by adjusting R such that the bolometer resistance RX balances the bridge and the current in the galvanometer G is zero. Let V = V1, when the RF power is ON. Now the RF power is switched OFF. As a result,RX changes and the bridge is unbalanced. The bridge is once again balanced by increasing V to V2. The RF power is given as follows: P=

V22 − V12 4R1

(22.43)

Bolometer method is used to measure powers of the order a few microwatts to a small fraction of a watt. However, calorimeter method is used to measure large RF powers. In this method, the RF power is converted into heat. This heat is absorbed in water and the rise in temperature of water is measured.

22.5.10 Energy Meter Energy meter is an instrument that is used to measure energy. It is also sometimes referred to as watt-hour meter. Energy is the total power delivered or consumed over an interval of time t and may be expressed as follows: t

Wh = ∫v (t ) i (t ) dt 0

If v(t) is expressed in volts, i(t) in amperes and t in seconds, the unit of energy is joule or watt second. The commercial unit of electrical energy is kilowatt-hour (kWh). For measurement of energy in ac circuits, an electromagnetic induction-type instruments may be used (Figure 22.97).

Construction of Induction-Type Energy Meter Induction-type energy meter essentially consists of following components: (i) driving system, (ii) moving system,(iii) braking system, and (iv) registering system. (i) Driving system: The induction-type energy meter consists of two electromagnets, called shunt magnet and series magnet, of laminated construction. A coil having large number of turns of fine wire is wound on the middle limb of the shunt magnet. This coil is known

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1139

as pressure or voltage coil and is connected across the supply mains. This voltage coil has many turns and is arranged to be as highly inductive as possible. In other words, the voltage coil produces a high ratio of inductance to resistance. This causes the current, and therefore the flux, to lag the supply voltage by nearly 90°. Adjustable copper shading rings are provided on the central limb of the shunt magnet to produce a phase angle of approximately 90° between magnetic field set up by shunt magnet and the supply voltage. The copper shading bands are also called the power factor compensator or compensating loop. The series electromagnet is energized by a coil, known as current coil, is connected in series with the load so that it carries the load current. The flux produced by this magnet is proportional to the load current and is in phase with the load current. Gear train to dials

Voltage coil Magnetic brake Rotating disc Current coils

Figure 22.97 Induction-type energy meter

(ii) Moving system: The moving system consists of a light rotating aluminum disk mounted on a vertical spindle or shaft. The shaft that supports the aluminum disk is connected by a gear arrangement to the clock mechanism on the front of the meter to provide information on the consumed energy by the load. The time-varying fluxes produced by shunt and series magnet induce eddy currents in the aluminum disc. The interaction between these two magnetic fields and eddy currents sets up a driving torque in the disc. The number of rotations of the disk is therefore proportional to the energy consumed by the load in a certain time interval and is commonly measured in kilowatt-hours. (iii) Braking system: Damping of the disk is provided by a small permanent magnet, located diametrically opposite to the ac magnets. The disk passes between the magnet gaps. The movement of rotating disc through the magnetic field sets up eddy currents in the disc that react with the magnetic field and exerts a braking torque. By changing the position of the brake magnet or diverting some of the flux there from, the speed of the rotating disc can be controlled. The braking torque is given as follows: Tb ∝j b i b ∝ j b

Nj b eb ∝ jb ∝ N j b2 r r

(22.44)

1140

Electronic Devices and Circuits

where j b = brake magnetic flux N = speed of rotation of the disc ib = eddy current in the aluminum disc r = eddy current path resistance Since j b is constant, this implies that Tb ∝ N The deflecting torque Td ∝ VI cosq Tb = Td or

(22.45)

VI cosq ∝ N

Therefore, the speed of the disc is proportional to the power consumed by the load.

∫VI cosqdt = ∫Ndt ∝ energy consumed (iv) Registering or counting system: The registering or counting system consists of gear train, driven either by worm or pinion gear on the disc shaft, which turns pointers that indicate on dials the number of times the disc has turned. The energy meter thus determines and adds together or integrates all the instantaneous power values so that total energy used over a period is thus known. Therefore, this type of meter is also called an integrating meter.

22.5.11 Digital Frequency Meter Figure 22.98 shows the block diagram of the digital frequency meter. The input signal, whose frequency is to be measured, is amplified and is fed to the Schmitt trigger. The output of the Schmitt trigger is a square wave with very fast rising and falling edges. The output of the Schmitt trigger is then differentiated and clipped. Consequently, the input to the AND gate is a train of pulses, one

Amplifier Input signal

Schmitt trigger

Schmitt trigger

Digital readout Gate FF

Timebase selector 1s

1µs 10µs 1MHz crystal oscillator

Schmitt trigger

÷10

÷10

100µs

100ms

1ms 10ms ÷10

÷10

÷10

Figure 22.98 Block diagram of the digital frequency meter

÷10

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1141

pulse for each cycle of the input signal. The time base signal is derived from a stable 1MHz crystal oscillator. The output of the crystal oscillator is converted into a square wave by a Schmitt trigger and its frequency is divided successively by a factor 10. The output pulses from this Schmitt trigger are fed to the start stop gate. The first pulse enables the start/stop gate and the input pulses are counted by the counter. The second pulse disables the start/stop gate and the counting is stopped. If N is the number of counts displayed by counter and t is the time interval between start and stop pulses, then the frequency of unknown signal f = N/t. The timing diagram is shown in Figure 22.99.

Time base signal

Main gate F/F

t N

Input to counter

Input signal

Figure 22.99 Timing diagram of the frequency counter

Time Period Measurement The measurement of frequency using a frequency meter is advisable at high frequencies where the number of pulses counted is reasonably large, and hence the accuracy of measurement is definitely better. However, at low frequencies it is 1 better to measure the time period T and then calculate f as . The block diagram for time T period measurement is shown in Figure 22.100. The only difference here when compared to the circuit in Figure 22.98 is that the input signal generates the gating signals and the timebase pulses are counted by the counter. Amplifier Input signal

Schmitt trigger

Schmitt trigger

Digital readout Gate FF

Timebase selector 1s

1µs 10µs 1 MHz crystal oscillator

Schmitt trigger

÷10

÷10

100µs

100ms

1ms 10ms ÷10

÷10

÷10

Figure 22.100 Digital meter for measuring time period

÷10

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Electronic Devices and Circuits

Measurement of Distortion If a sinusoidal signal is applied to an amplifier, it may be possible that the output may not necessarily be a sinusoidal signal, that is, there can be amplitude distortion, which will give rise to frequency distortion. Also, if two frequencies are applied as input to an amplifier, it is possible to get a signal at the output due to the sum and difference frequencies. This type of distortion is called intermodulation distortion. A distortion meter may measure the amplitudes of various harmonic components. In such a case, the distortion meter is called a wave analyzer. Alternately, the fundamental component may be rejected and the total distortion can be measured. In this case, the distortion meter is called distortion analyzer.

Wave Analyzer A wave analyzer can also be called a frequency-selective voltmeter. The instrument is used to measure individually the magnitude of each harmonic component. Alternately, the meter can be calibrated to read the ratio of the harmonic to fundamental component and express this ratio as percentage.

Dn =

Bn × 100 B1

(22.46)

where Bn is the magnitude of the harmonic term and B1 is the magnitude of the fundamental component. A heterodyne wave analyzer is shown in Figure 22.101. The input signal fs is heterodyned or mixed with a tunable local oscillator frequency fo1 in a balanced-type mixer, which gives sum and difference frequencies ( fo1 + fs ) and ( fo1 − fs ). By using a filter, ( fo1 + fs ) can be rejected and only ( fo1 − fs ) can be selected. ( fo1 − fs ) = fi1 is the first intermediate frequency. A doubletuned IF amplifier amplifies the signal uniformly. The output of the first IF amplifier is fed to a second mixer, for which the local oscillator frequency is fo2 which is made to produce a second intermediate fi2 = 0 Hz. The bandwidth is controlled by an active filter. The output of the active filter is fed to an amplifier and detector and is displayed on a meter that may be directly calibrated in dB. This type of meter can be used right from audio frequency range to radio frequency range. Wideband amplifier fs

Attenuator Attenuator

IF amplifier Fist mixer First mixer

fi1

Second mixer fo2

fo1

Local osillator 2

Local osillator 1

Output meter Amplifier and detector

Active filter

Figure 22.101 Heterodyne wave analyzer

fi2

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1143

As such, the input signal can range from 0 to 18MHz and can be divided into10 ranges. As an example, if fo1 = (30 − 48) MHz, then fi1 = 30 MHz . If fo2 = 30 MHz , then fi2 = 0 Hz . The bandwidth of the active filter may be chosen as 1500Hz. The tunable local oscillator frequency is varied to get the signal amplitudes of the fundamental, second harmonic, third harmonic, etc. The total harmonic distortion can be measured as follows: D = D12 + D22 + � + Dn2

(22.47)

Distortion Analyzer A distortion analyzer is used to measure the total harmonic distortion. The fundamental component is eliminated from the output by using a notch filter (a narrow band-elimination filter). A bridged T-network is used as a notch filter. The block diagram of the distortion analyzer is shown in Figure 22.102.

Tunable band-pass filter

Amplifer

Output meter

Set Input

Attenuator SW1

Distortion

SW2

Tunable notch filter 0 Attenuation in db

f1

Figure 22.102 Distortion analyzer

SW1 is switched to set position. The band-pass filter passes the fundamental and the harmonics components. The attenuator is adjusted for full-scale deflection. Now, SW1 is switched to distortion position. Once again, the attenuator is adjusted for full-scale deflection. The attenuator setting gives the total harmonic distortion.

Spectrum Analyzer A signal may contain a number of frequency components; each frequency may be having different amplitude. A spectrum analyzer is a versatile instrument that displays the amplitudes of the various frequency components, that is, it displays a frequency domain plot. A cathode ray oscilloscope (CRO) on the contrary displays a timedomain plot. Spectrum analyzers can be of two types: (i) parallel filter bank spectrum analyzer or real time multichannel spectrum analyzer and (ii) swept frequency spectrum analyzer. (i) Parallel filter bank spectrum analyzer: The parallel filter bank spectrum analyzer uses a series of fixed band-pass filters in parallel. The center frequencies and the bandwidths of these filters overlap such that the entire frequency range of interest is covered by the filter bank. The input is applied to all the filters simultaneously (in parallel). An electronic

1144

Electronic Devices and Circuits

switch selects the output of each detector and this signal is fed to the vertical deflecting plates of the CRO. A sweep generator produces the horizontal deflection, in synchronism. The resultant display on the cathode ray tube (CRT) screen is a display of frequency versus amplitude (Figure 22.103).

Detector 1

Filter 2

Detector 2

Filter 3

Detector 3

Filter n

Detector n

Amplifer CRTdisplay

Electronic switch

Input

Filter 1

Sweep generator n-1 n

V 1 2 3

Filter bank

f

Figure 22.103 Parallel filter bank spectrum analyzer

(ii) Super-heterodyne spectrum analyzer: A simple super-heterodyne spectrum analyzer is shown in Figure 22.104. The input signal fs is heterodyned with a local oscillator frequency fo in a mixer and the output of the mixer is tuned to ( fo − fs ) = fi, the intermediate frequency. This amplified and detected output causes vertical deflection of the electron beam on the CRT screen. A sweep generator that sweeps the CRT beam horizontally also tunes the local oscillator. The CRT displays frequency versus amplitude.

fs Input

Attenuator

LPF

fs

fs Mixer

IF filter

Amplifer and detector

fo Local osillator

Sweep generator

Figure 22.104 A heterodyne spectrum analyzer

Let a signal fsi = fs + 2 fi be present at the input and let fo = fs + fi, then fsi − fo = ( fs + 2 fi ) − ( fs + fi ) = fi

CRT display

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1145

The output of the mixer is fi when the input is fs and also fsi. fsi is called the image frequency, which gives the same intermediate frequency, fi. To reject fsi a low-pass filter is used in Figure 22.104. fo < fs is called low-side injection and fo > fs is called high-side injection. To be able to separate two input signals that are closely placed, narrow IF bandwidths are used. To achieve this, more number of mixers are to be used.

22.5.12 Cathode Ray Oscilloscope A CRO basically consists of (i) CRT, (ii) time-base generator, and (iii) horizontal and vertical deflecting amplifiers. A CRT is a sealed tube in which a hot cathode emits electrons. These electrons are accelerated as a beam through a relatively high-voltage anode. The accelerated electrons are then focused and deflected both vertically and horizontally and are finally made to strike a fluorescent screen for visual display. The block diagram of the CRO is shown in Figure 22.105. Input signal

Vertical amplifier

Delay line

Cathode

Filament

Grid

Vertical deflecting plates

Accelerating electrode

Accelerating Horizontal focusing electrode deflecting electrode plates

Trigger circuit

Timebase generator

Florescent screen

Electron beam

Horizontal amplifier

Figure 22.105 Cathode ray oscilloscope

The screen consists of a glass that is coated with a florescent material, which is usually phosphor. Phosphor emits light when its atoms are excited, and this phenomenon is called fluorescence. When the high velocity electron beam strikes the screen, it emits light. The brightness, color, and persistence of the illumination depend on the type of phosphor used on the CRT screen. Phosphors can have persistence ranging from less than 1 µs to several seconds. For visual display of brief transient events, a long persistence phosphor is preferred. For display of high-frequency repetitive signals, a short-persistence phosphor is generally the choice. CRTs are used in CROs, television and radar receivers, and computer monitors. The beam is deflected horizontally by the time-base signal and the input signal causes the deflection of the beam vertically.

Measurements Using CRO A CRO is a versatile instrument that gives visual indication of the waveforms. Electrons from the cathode are accelerated and focused on the fluorescent screen. A spot of light appears on the screen. The spot is moved vertically by the application of the signal (to be displayed) between the Y-deflecting plates through an amplifier (Figure 22.106(a)). To sweep the spot linearly as a function of time along

1146

Electronic Devices and Circuits

the X-axis a saw-tooth waveform is applied between the X-deflecting plates through an amplifier (Figure 22.106(b)). This enables the waveform to be displayed on the CRT screen (Figure 22.107). The deflection of the spot per unit change of voltage between the deflecting plates is called the deflection sensitivity of the CRT. If 10V is applied between the Y-deflecting plates and if the spot shifts vertically by 3mm, then the deflection 3 mm sensitivity is = 0.3mm/V. 10 The deflection of the spot = deflection sensitivity ×applied voltage.

Y1

2

1

5

X1

2 1, 3, 5 4

3

X2

12345

5

4 Y2

4

0

(a) vertical deflection

3

t

2 1 (b) Horizontal deflection

Figure 22.106 Deflection of the spot on the CRT screen

In all the present-day CROs, the time base is calibrated. For example, if the time-base switch is in 1µs/div position and if the time period of the signal applied to the vertical deflecting plates measures 1 two divisions, then the time period of the signal is 2 µs and its frequency f = = 500 kHz. 2 × 10 −6 Similarly, the vertical axis is also calibrated as V/div. If the attenuator switch is 1 mV/div position and if the peak-to-peak voltage measures 2 divisions, then the peak-to-peak voltage is 2 mV, its 1 mV peak is 1 mV and the RMS value of the applied sinusoidal signal is = 0.707mV. 2 2

2

3

5

1

5

1

3

4

4

5

4 0 3

t

2 1

Figure 22.107 Displaying waveform on the CRT screen

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1147

In case the time base is not calibrated, then the frequency of an unknown signal generator can be found out by using a standard signal generator, whose frequency is known, by using Lissajous patterns on the CRT screen (Figure 22.108). To display the patterns, the internal time base is cutoff and the signal from the unknown signal generator is applied to one set of deflecting plates, say X-deflecting plates. The signal from the standard signal generator is connected to the Y-deflecting plates. Then the patterns seen on the CRT screen, if one frequency is an integer multiple of the other, are as shown in Figure 22.108. Let fh be the frequency applied to the horizontal deflecting plates and fv be the frequency applied to the vertical deflecting plates, then fv Number loops cut by the horizaontal line = fh Number loops cut by the vertical line

1

1

1 2 2 3 (a)

(b)

(c)

Figure 22.108 Lissajous patterns

From Figure 22.108(a),

fv 2 f = or fh = v . If fv = 2 kHz, then fh = 1 kHz fh 1 2

From Figure 22.108(b),

fv 1 = or fh = 2 fv. If fv = 2 kHz, then fh = 4 kHz fh 2

From Figure 22.108(c),

fv 1 = or fh = 3 fv . If fv = 1 kHz, then fh = 3 kHz fh 3

Spot Wheel Pattern for the Measurement of Unknown Frequency Take a sinusoidal signal of known frequency from a standard signal generator and produce a phase shift of 90° by using an 1 RC network. Set R = and apply signals from Y and X to the vertical and horizontal deflecting wC plates of the CRT. Then the resultant pattern seen on the CRT screen is a circle. Z-mod terminals (for intensity modulation) are provided at the back of the instrument, which are the terminals through which an external voltage can be applied to the control grid terminals of the CRT. If the unknown frequency, which is greater than the standard signal generator frequency, is applied to the Z-mod terminals, then during the positive-going half cycle of the unknown signal the spot becomes brighter and during the negative-going half cycle the spot is blanked. Thus, the number of spots on the circle gives the ratio of frequencies (Figure 22.109).

Electronic Devices and Circuits Rear panel of CRO

Y

Z-mod terminals

Known frequency

R

1/wC

Unknown frequency

1148

Spot wheel

C

R = 1/wC X

Figure 22.109 Spot-wheel method of measuring unknown frequency

Measurement of Phase Using CRO Consider two signals having the same frequency and let the phase shift between the two signals be zero. When these two waveforms are applied to the X and Y deflecting plates of the CRO, the resultant Lissajous pattern is a straight with orientation as shown in Figure 22.110.

A 1

4

5

O

6

2 3 C D a b c d e f

Figure 22.110 Lissajous pattern when the phase shift is zero

Similarly, if the two signals have the same frequency and the pattern seen on the CRT screen is an ellipse with the orientattion of the major axis as shown in Figure 22.111,  1 division   A then q = sin −1   = sin −1  = 30°, where B is  B  2 divisions  the peak amplitude (number of divisions) and A is the amplitude at which the ellipse crosses the major axis (number of divisions).

B A

0

Figure 22.111 Measurement of phase shift using Lissajous pattern

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1149

For two signals having the same frequency, if the Lissajous patterns are as shown in Figure 22.112, then phase shifts are as indicated.

0

45°

90°

135°

180°

Figure 22.112 Phase shift for typical Lissajous patterns

The phase angle is obtained knowing the direction in which the spot rotates (clockwise or anticlockwise) and the orientation of the major axis of the ellipse.

Dual-trace CRO In a dual-trace CRO, a single beam in a CRT is shared by two channels, and hence two waveforms can be displayed simultaneously using a single-beam CRO. There is another type of CRO called dual-beam CRO in which the CRT has two electron guns and can have two independent displays on the same CRT. There are two methods of obtaining dual traces: (i) ALT (alternate) mode and (ii) CHOP mode. (i) ALT mode: The ALT mode of obtaining a dual trace uses the technique of electronic switching or gating between sweeps. In this method of control, the signal that is applied to Channel 1 is displayed in its entirety. Then, the switch changes position to Channel 2 and now this signal is displayed in its entirety. This method of display is continued alternately between the two channels (Figure 22.113). At slow switching speeds, one trace begins to fade while the other channel is being gated. Consequently, the ALT mode is used only at high sweep speeds. Channel 1

Channel 2

Amplifer

Amplifer

Beam switch

Sweep generator CRT

Figure 22.113 Dual-trace-ALT mode

(ii) CHOP mode: ALT mode does not operate satisfactorily at low speeds. For this reason, at low sweep speeds CHOP mode is used (Figure 22.114). In this method, the switching from Channel 1 to Channel 2 and vice versa takes place at high speeds, using a high-frequency

1150

Electronic Devices and Circuits

multivibrator. If the frequency of the multivibrator is large, say, 1MHz, then the two traces are seen on the CRT screen as continuous lines. The CHOP mode will produce a satisfactory dual sweep at low speeds, whereas the ALT mode will produce a satisfactory dual sweep at high speeds. Therefore, both the methods are used in dual-trace oscilloscopes to complement each other and give the scope a better dynamic range of operation.

Channel 1

Channel 2

Amplifer

Beam switch

Amplifer

Sweep generator 1000 kHZ square wave generator

CRT

Figure 22.114 Dual-trace-CHOP mode

Summary • A silicon-controlled rectifier, also known as a thyristor, is a four-layered solid-state-controlled rectifier that is extensively used in power control applications. Once the SCR fires, the gate loses control. To drive the ON device into the OFF state, forced commutation technique may have to be used. • TRIAC, DIAC, GTO, and LASCR are the other members of the SCR family. • When compared to a PN junction diode, the optoelectronic devices such as photodiodes, solar cells, LEDs, and LASER diodes are specifically designed to optimize the light absorption and emission, resulting in a high conversion efficiency. Optoelectronic devices find applications in display systems and in communications. • An LED is a PN junction diode that emits light under forward-bias conditions due to the energy that is released when electrons and holes recombine. The color of the light emitted depends on the band gap of the material. LEDs are fabricated from materials like GaAs. It is used as a light source at the transmitter end. • Photodiode is a PN junction operated under reverse bias and is used to convert optical signal into electrical signals. It is used as a detector at the receiver end. • Optical fibers are used to transmit information in the form of light through an optical waveguide made of glass fibers. Depending on the mode of transmission, fibers are classified as (i) single-mode fibers and (ii) multimode fibers. Further, based on the refractive index profile of the core and cladding, optical fibers are classified into two types: (i) step index fibers and (ii) graded-index fibers.

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1151

• Where there is need to transfer signals and data from one subsystem to another within the same electronic equipment, or from one electronic equipment to another, without making a direct ohmic electrical connection, then optocouplers or photocouplers are used. • Optocouplers use a light beam to transmit the signals or data (analog or digital) across an electrical barrier, with excellent isolation. An optocoupler consists of (i) light emitter (ii) light detector. • Measuring instruments measure electrical quantities like current, voltage, power, frequency etc.; The electrical quantities to be measured may be either dc current and voltage or ac. current and voltage. The measuring instruments can either be analog or digital instruments. • A cathode ray oscilloscope (CRO) is a versatile instrument that gives visual indication of the waveforms. It can be used for the measurement of ac and dc voltages, time period, frequency, and phase.

multiple ChoiCe QueStionS 1. One of the following devices can conduct current in either direction and is turned ON when a breakover voltage is exceeded. (a) SCR (b) SCS (c) DIAC (d) TRIAC 2. One of the following devices is a DIAC with gate terminal (a) SCR (b) SCS (c) DIAC (d) TRIAC 3. An SCR can be triggered by a pulse at this terminal (a) Gate (b) Anode (c) Cathode (d) None of these 4. An SCR acts to control the speed of an electric motor by ________ the ________ of the pulse delivered to the motor. (a) varying, width (b) increasing, amplitude (c) decreasing, gate width (d) none of these 5. LEDs are made out of (a) silicon (c) silicon and germanium

(b) germanium (d) compounds of Gallium

6. The resistance of a photoconductive cell, when approximated (a) increases linearly with increase in light intensity (b) decreases linearly with increase in light intensity (c) increases linearly with decrease in light intensity (d) decreases linearly with decrease in light intensity 7. One of the following combinations of materials is used in optical fibers (a) Iron core and glass cladding (b) Copper core and glass cladding (c) Glass core and plastic cladding (d) Plastic core and glass cladding 8. In a graded-index fiber, the total reflected light takes one of the following paths: (a) Circular (b) Parabolic (c) Elliptical (d) Straight line

1152

Electronic Devices and Circuits

9. The internal resistance for milliammeter must be very low for (a) high sensitivity (b) high accuracy (c) maximum voltage drop across the meter (d) minimum voltage drop across the meter 10. A voltmeter should be of very high internal resistance so that (a) its range is high (b) its accuracy is high (c) it may draw current minimum possible (d) its sensitivity is high 11. Which of the following instruments can be used for both ac and dc measurements? (a) PMMC type (b) Induction type (c) Moving-iron type (d) None of these 12. A dynamometer type wattmeter responds to the (a) average value of the active power (c) peak value of the active power

(b) average value of the reactive power (d) peak value of the reactive power

13. An ohmmeter is basically (a) an ammeter (c) a multimeter

(b) a voltmeter (d) none of these

14. A 1000 W light bulb burns on an average of 10 h a day for 1week. The weekly consumption of energy will be (a) 0.7 units (b) 7 units (c) 70 units (d) 700 units 15. An ammeter has a resistance Rm and a range of I amperes. The shunt resistance required to convert it into an ammeter to read nI amperes is (a) ( n − 1) Rm (b) nRm Rm R (d) m n −1 n 16. A voltmeter has a resistance Rm and a range of V volts. The series resistance required to convert it into an voltmeter to read nV volts is (a) ( n − 1) Rm (b) nRm (c)

Rm n −1

Rm n 17. A photodiode conducts on the principle of (a) photoconductive effect (c) photomultiplier effect

(b) photovoltaic effect (d) photoelectric effect

18. GaAs LED emits radiation in the (a) UV region (c) visible region

(b) RF region (d) infrared region

(c)

(d)

19. LCD displays are preferred over LED displays because they (a) are cheaper (b) are costlier (c) are more reliable (d) consume less power

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

20. A thyristor can be termed as a (a) controlled switch (c) controlled amplifier

1153

(b) dc amplifier (d) ac amplifier

21. A thyristor turns ON when (a) its anode is positive with respect to cathode (b) its anode is negative with respect to cathode (c) its anode is positive with respect to cathode and there is a positive gate pulse (d) its anode is positive with respect to cathode and there is a negative gate pulse 22. After firing if the gate pulse is removed in an SCR, the current (a) remains the same (b) falls to zero (c) increase to infinity (d) decays exponentially 23. The current in an SCR when conducting is 20A. If its gate current is reduced to zero, then the SCR current is (a) 0 (b) 40 A (c) 20 A (d) 30 A 24. A TRIAC is used in ac switching applications because (a) it can control the flow of current in both halves of the ac input (b) it can control the flow of current in only one half of the ac input (c) it cannot control the flow of current in both halves of the ac input (d) none of the above 25. When a thyristor fires, gate loses control, and for it to be switched OFF (a) a commutation circuit is to be provided (b) its gate current is made zero (c) a negative pulse is applied at its anode (d) none of the above 26. A GTO thyristor is turned ON by the application of a ______________trigger signal to the gate and can be turned OFF by the application of a ____________ trigger pulse to the gate. (a) positive, negative (b) positive, positive (c) negative, negative (d) negative, positive 27. An electronic voltmeter is preferred over a multimeter for measuring voltage across a reverse biased diode because it has (a) low input resistance (b) high input resistance (c) high gain (d) low distortion 28. The purpose of an input attenuator in measuring instruments like CRO and electronic voltmeters is to (a) attenuate the current (b) increase the input resistance (c) attenuate the frequency (d) attenuate the input signal amplitude without changing the frequency 29. A chopper stabilized dc amplifier type electronic voltmeter overcomes the effect of (a) drift in the amplifier (b) power loss in the amplifier (c) less gain in the amplifier (d) distortion in the amplifier 30. Which of the following measurements can be made using Lissajous figures? (a) Time interval between pulses (b) Pulse duration (c) Frequency (d) Bandwidth

1154

Electronic Devices and Circuits

31. In a CRO a ramp voltage is applied between (a) X-deflecting plates (c) anode and cathode

(b) Y-deflecting plates (d) anode and control grid

32. A dual beam CRO has (a) two vertical inputs and one horizontal input (b) two vertical inputs and two horizontal inputs (c) one vertical input and two horizontal inputs (d) one vertical input and one horizontal input 33. An optoelectrical phenomenon in which a semiconductor material becomes more electrically conductive due to the absorption of electromagnetic radiation is called (a) photosensitivity (b) photoconductivity (c) photovoltaic effect (d) photomultiplication

1 2

34. A 4 -digit DVM can read from (a) 00000–19999 (c) 11111–19999 35. At RF frequencies power is measured using a (a) wattmeter (c) bolometer

(b) 0000–1999 (d) 11111–09999 (b) electronic voltmeter (d) distortion meter

36. A wave analyzer is used to measure (a) total harmonic distortion (b) measure the magnitude of each harmonic component individually (c) even harmonic distortion (d) odd harmonic distortion 37. A distortion meter is used to (a) total harmonic distortion (b) measure the magnitude of each harmonic component individually (c) even harmonic distortion (d) odd harmonic distortion 38. A spectrum analyzer is an instrument that displays (a) the phase of the various frequency components as a function of time (b) the amplitudes of the various frequency components as a function of time (c) the amplitudes of the various frequency components as a function of frequency (d) the frequency of the various frequency components as a function of time 39. Both ALT/CHOP modes are used in dual-trace oscilloscopes to complement each other and give the scope (a) a better voltage range (b) a better dynamic range of operation (c) a better sensitivity (d) a display without distortion 40. The spreading out of a light pulse in time as it travels through the fiber is called (a) amplitude modulation (b) frequency modulation (c) harmonic distortion (d) dispersion

Special Electronic Devices, Optoelectronic Devices, and Measuring Instruments

1155

Short anSwer QueStionS 1. What is an SCR? 2. Once the SCR fires, the current in the device becomes excessively large. How is this current limited to a safe value? 3. What is the forward breakdown voltage of an SCR? 4. What is the forward current rating of an SCR? 5. What is forced commutation to switch off SCR? 6. What is a snubber circuit? 7. What is a TRIAC? 8. What is a DIAC? Mention its principal application. 9. What is the main difference between an SCR and GTO? 10. What is LASCR? 11. What is photoconductivity? 12. What is an LDR? 13. What is dark current in a photodiode? 14. What is a photovoltaic or solar cell? 15. What is a light-emitting diode? 16. What are optocouplers? 17. Explain the principle of working of LCDs. 18. Classify optical fibers based on modes of transmission. 19. Classify optical fibers based on the refractive index profile of the core and cladding. 20. What is the difference between an electronic voltmeter and an analog multimeter? 21. What is the main advantage of a DVM over an analog voltmeter? 22. What is meant by resolution of digital voltmeter? 1 23. What is the difference between 3-digit and 3 digit DVM? 2 24. What are the various measurements that can be made using a CRO? 25. What is meant by deflection sensitivity of a CRO? 26. What is the type of signal applied to the X-deflecting plates of the CRO to move the spot linearly as a function of time along the X-axis? 27. What are Lissajous patterns? 28. What is a dual trace CRO? 29. What is the difference between the dual beam and dual trace CRO? 30. What is the application of a spectrum analyzer?

long anSwer QueStionS 1. Explain, with neat relevant diagrams, the principle of working of an SCR. Explain forced commutation. 2. Explain how an SCR can be used as a HW and FW rectifier. Derive the expressions for the dc output voltage in each case. 3. Write short notes on (i) TRIAC,

(ii) DIAC,

(iii) GTO,

(iv) LASCR

1156

Electronic Devices and Circuits

4. Explain the principle of operation of the following opto-electronic devices: (i) LED,

(ii) LCD,

(iii) LASER diode,

(iv) LDR

5. What are optocouplers? Where are they used? Explain with a neat illustration the working of an optocoupler. 6. Write short notes on(i) seven-segment displays and (ii) LCD displays. 7. Explain the principle of working of optical fibers. Also explain with suitable diagrams the method of propagation in (i) step-index fibers and (ii) graded-index fibers. 8. Explain, with the help of a neat circuit diagram, the working of an electronic voltmeter. 9. Explain the principle of working of (i) ramp-type digital voltmeter and (ii) dual-slope integration-type digital voltmeter. 10. Explain how you measure the following quantities: (i) time period, (ii) frequency, and (iii) distortion. 11. Explain how phase and frequency are measured using a CRO.

unSolved problemS 1. Design a multirange dc milliammeter with a basic meter having a resistance 100 Ω and full-scale deflection for the current of 5 mA. The required ranges are 0–10 mA, 0–50 mA, 0–100 mA. 2. A moving coil meter takes 15 mA to produce full-scale deflection and the voltage across its terminals is 75 mV. Suggest a suitable scheme for using the instrument as a voltmeter reading 0–100V and as an ammeter reading 0–50mA. 3. For the voltmeter shown in Figure 22.115, determine the resistance values to give full-scale deflection of 10 V, 50 V, and100 V. R3

R2

R1 100V

5mA

Im Rm 50 Ohms

V1 V2

50V 2

3

1 V3 10V

+ Meaured voltage −

Figure 22.115 Voltmeter 4. A PMMC meter has a coil resistance 10 Ω and a full-scale deflection current of 1 mA. How can the meter be used to measure 5 A, 10 A, 10 V, and 100 V?

23

DIGITAL ELECTRONICS

Learning objectives After reading this chapter, the reader will be able to ˆ ˆ ˆ ˆ ˆ

Learn the basics of different number systems Understand the techniques to minimize Boolean expressions Understand the analysis and design of combinational circuits Understand the working of the logic gates in TTL and CMOS families Understand A/D and D/A converters

Dear student, for detailed chapter on Digital Electronics, please scan the QR code given here OR Visit http://highered.mheducation.com/sites/9332901155/information_ center_view0/chapter_23.html

24

MICROCOMPUTERS AND MICROPROCESSORS

Learning objectives After reading this chapter, the reader will be able to ˆ Understand the history and structure of microcomputer ˆ Identify the basic architecture of microprocessor ˆ Realize the bus structure of the 8085 ˆ Use the instruction set of 8085 ˆ Enter a program into the 8085 microprocessor ˆ Understand the difference between 8085 and 8086 microprocessors

Dear student, for detailed chapter on Microcomputers and Microprocessors, please scan the QR code given here OR Visit http://highered.mheducation.com/sites/9332901155/information_ center_view0/chapter_24.html

A

APPENDIX

ANSWERS TO MULTIPLE CHOICE QUESTIONS Chapter 1 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28.

(c) (b) (a) (a) (c) (b) (c) (d) (a) (c) (c) (a) (b) (c) (a) (b) (d) (a) (c) (d) (c) (a) (b) (b) (a) (b) (d) (d)

Chapter 2 1. (a) 2. (c)

3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26.

(c) (a) (a) (a) (a) (b) (d) (c) (b) (d) (c) (a) (c) (b) (a) (a) (b) (a) (d) (c) (b) (a) (b) (a)

Chapter 3 1. 2. 3. 4. 5. 6. 7.

(b) (a) (b) (b) (a) (b) (b)

8. 9. 10. 11.

(c) (a) (a) (b)

Chapter 4 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.

(b) (a) (c) (a) (b) (a) (b) (b) (c) (a) (b) (c) (c) (a) (a)

Chapter 5 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

(b) (a) (c) (a) (b) (c) (a) (a) (d) (b)

Appendix

11. (a) 12. (b) 13. (a)

Chapter 6 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19.

(b) (d) (a) (c) (a) (d) (c) (a) (b) (c) (b) (c) (a) (a) (d) (b) (c) (d) (c)

Chapter 7 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21.

(c) (a) (a) (d) (a) (a) (b) (b) (b) (c) (a) (b) (a) (a) (c) (b) (a) (a) (b) (b) (a)

Chapter 8 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

(a) (c) (a) (c) (c) (a) (b) (a) (c) (b)

Chapter 9 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.

(a) (c) (b) (d) (a) (c) (a) (b) (a) (d) (c) (b) (a) (b) (b)

Chapter 10 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

(b) (a) (c) (a) (b) (a) (a) (a) (d) (a)

Chapter 11 1. 2. 3. 4.

(c) (c) (d) (c)

5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.

(b) (a) (b) (a) (a) (a) (b) (a) (a) (b) (b)

Chapter 12 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

(c) (a) (a) (a) (a) (b) (b) (d) (a) (d)

Chapter 13 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12.

(a) (a) (b) (a) (b) (c) (b) (c) (a) (d) (c) (a)

Chapter 14 1. 2. 3. 4. 5. 6. 7.

(d) (a) (a) (c) (c) (c) (c)

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1234

Appendix

8. (b) 9. (a) 10. (a)

Chapter 15 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

(c) (c) (a) (a) (a) (b) (a) (a) (c) (a)

Chapter 16 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12.

(b) (d) (b) (a) (a) (a) (b) (c) (c) (d) (a) (a)

Chapter 17 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14.

(a) (a) (b) (b) (b) (d) (c) (a) (a) (c) (b) (a) (c) (d)

15. 16. 17. 18. 19. 20.

(a) (b) (a) (a) (a) (b)

Chapter 18 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18.

(a) (a) (d) (c) (a) (c) (a) (d) (c) (a) (a) (a) (a) (b) (a) (a) (a) (b)

Chapter 19 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18.

(d) (c) (c) (a) (b) (b) (a) (a) (b) (a) (b) (a) (d) (b) (a) (c) (b) (a)

Chapter 20 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

(b) (a) (a) (d) (b) (c) (c) (c) (b) (d)

Chapter 21 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.

(a) (b) (a) (b) (b) (a) (c) (b) (a) (d) (a) (a) (b) (c) (a)

Chapter 22 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12.

(c) (d) (a) (a) (d) (b) (c) (b) (d) (c) (c) (a)

Appendix

13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38.

(a) (c) (d) (a) (a) (d) (d) (a) (c) (a) (c) (a) (a) (a) (b) (d) (a) (c) (a) (a) (b) (a) (c) (b) (a) (c)

39. (b) 40. (d)

Chapter 23 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.

(b) (b) (d) (c) (a) (c) (c) (d) (a) (c) (b) (a) (d) (c) (b)

Chapter 24 1. 2. 3. 4. 5.

(d) (a) (a) (b) (d)

6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30.

(d) (c) (d) (a) (d) (b) (a) (a) (d) (c) (b) (d) (c) (c) (a) (b) (c) (d) (c) (d) (a) (c) (d) (b) (b)

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B

APPENDIX

ANSWERS TO SHORT ANSWER QUESTIONS Chapter 1 1. The effective resistance R = R1 + R2 + R3 = 30 + 30 + 30 = 90 kΩ. 2. The effective resistance R = R1 � R2 � R3 =

R1R2 R3 30 × 30 × 30 = 10 kΩ . = R1R2 + R2 R3 + R3 R1 30 × 30 + 30 × 30 + 30 × 30

3. The effective capacitance C1C2C3 30 × 30 × 30 = 10 mF . C = C1 � C2 � C3 = = C1C2 + C2C3 + C3C1 30 × 30 + 30 × 30 + 30 × 30 4. The effective capacitance C = C1 + C2 + C3 = 30 + 30 + 30 = 90 mF. 5. Materials are classified as conductors, insulators, and semiconductors. Conductors have high conductivity or low resistivity (reciprocal of conductivity). Conductors have a typical resistivity of the order 10 −8 to 10 -3 W - m and insulators have a resistivity of the order 106 to 1018 Ω − m . Semiconductors have resistivity, which lies between that of conductors and insulators, that is, −3 to 106 W - m. 6. Any material has two distinct energy bands called valence band and conduction band in which electrons may exist. The energy gap between the valence band and the conduction band is called the forbidden gap. For insulators the forbidden gap is more than 5 eV and for semiconductors it is relatively smaller, of the order of 1 eV. However, in the case of metals, there exists an overlap between the conduction band and valence band. 7. A semiconductor material in its pure form is called an intrinsic semiconductor. The impurity atoms are of the order of 1 in 100 million. At 0 K, an intrinsic semiconductor behaves as an insulator. 8. Germanium and silicon are the most preferred semiconductor materials because the energy required to break the covalent bonds is low, typically 1.12 eV for Si and 0.72 eV for Ge. 9. When a suitable amount of impurity is added to a pure semiconductor during crystal growth so as to increase its conductivity, the resultant semiconductor is called an extrinsic semiconductor. 10. When a small amount of fifth group impurities such as arsenic, antimony, bismuth, or phosphorous is added to pure Ge or Si during crystal growth, the resultant semiconductor is called an N-type semiconductor. As the impurity atoms have five valence electrons and

Appendix

11.

12.

13. 14.

15.

16. 17.

18.

19.

20.

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the Ge or Si atom has four valence electrons, only four covalent bonds are completed and the fifth valence electron of the impurity atom is not part of any covalent bond. As such this electron donated by the impurity atom is called a free electron and becomes the majority charge carrier. The impurity atoms that donate free electrons are called donor atoms. When a small amount of third group impurities such as boron, gallium, indium, or aluminum is added to pure Ge or Si during crystal growth, the resultant semiconductor is called a P-type semiconductor. As the impurity atom has three valence electrons and the Ge or Si atom has four valence electrons, only three covalent bonds are completed and there exists a vacancy in the fourth covalent bond, which is called a hole and is the majority carrier in the P-type semiconductor. As the impurity atom accepts a free electron from the lattice to complete the covalent bond, the impurity atom is called an acceptor atom. The average time that elapses from the instant a free electron is created to the instant it disappears due to recombination is called the mean lifetime of an electron. This time may typically vary from few nanoseconds to even few microseconds. Electrons move in the conduction band and holes move in the valence band. In an intrinsic semiconductor, for the material to be electrically neutral, the electron concentration and the hole concentration are both equal to the intrinsic concentration, that is, n = p = ni. Adding an N-type impurity to the semiconductor increases n and decreases p. Similarly, adding a P-type impurity increases p and decreases n. The product np = ni 2, is constant and is independent of the doping type and the doping level. This relation is called the mass action law. When an electric field is applied to a semiconductor material the electrons and holes drift to the positive and negative terminals of the battery, respectively, thereby constituting electron and hole currents. Diffusion current exists in a semiconductor due to migration of electrons and holes (diffusion) from high concentration region to low concentration region. When P- and N-type semiconductors having equal doping of impurity atoms are formed as a junction, electrons move from the N- to P-type and holes move region is created near the junction, where on the P-side there are negative ions (because a hole left an atom) and on the N-side of the junction there are positive ions (because an electron left an atom). This region, which is devoid of any mobile charge carriers, is called the depletion region and a potential, called barrier potential, is developed near the junction, which prevents the further diffusion of electrons and holes. The energy required to move an electron from the valence band into the conduction band at room temperature is more for Si (1.12 eV) than that required in the case of Ge (0.72 eV). Hence, at room temperature, Ge has larger conductivity than Si. If a thin, flat, uniform semiconductor bar is placed in a transverse magnetic field and direct current is passed through it, then an electric field is induced across its edges in a direction perpendicular to both the current and the magnetic field. This phenomenon is called Hall effect. It is possible to determine the sign of the mobile charges in a current-carrying conductor by measuring the Hall voltage. If the voltage is positive then the mobile charges are positive (assuming proper magnetic field and the current orientation), whereas if the voltage is negative then the mobile charges are negative.

1238

Appendix

Chapter 2 1. I S gets doubled for every 10°C rise in temperature. 2. The capacitance offered by the junction diode when forward biased is the diffusion capac tI  itance, CD and is proportional to the diode forward current I  CD ≈  hVT   3. The reverse recovery time is the sum total of the storage time and the transition time and is the time required to switch a forward-biased diode into the OFF state. 4. Forward biasing. 5. The Zener diode is a heavily doped semiconductor diode. At a voltage VZ, known as the breakdown voltage, the covalent bonds break due to the potential gradient and the current in the device abruptly becomes large. 6. When a large reverse-bias voltage is applied in a PN junction diode, the minority charge carriers in the P and N materials acquire large kinetic energy, aided by the external voltage. When a charge carrier collides with an atom, it may knock off an electron, which in turn can acquire large energy, may in turn knock off another electron from a different atom. This results in a large number of charge carriers, due to the process called avalanche multiplication, resulting in a large reverse current. 7. When a signal associated with a dc component is passed through a high pass RC circuit, the dc component is lost, as the capacitor blocks the dc. A clamping circuit reintroduces the dc component or restores the dc component. 8. Clamping circuit theorem states that for any input, under steady-state condition, the ratio of the area under the output curve when the diode is forward biased, Af to the ratio of the A R R output curve when the diode is forward biased, A r is equal to the ratio f or f = f . Ar R r Rr 9. When the doping is very high in a diode, the potential barrier becomes so thin that electrons can penetrate or punch through the junction with the velocity of light, even though they do not possess enough energy to overcome the potential barrier. This phenomenon is called tunneling. 10. A varactor diode is a reverse-biased diode in which the junction capacitance or the transition capacitance, CT varies as the width of the depletion region varies. 11. (1) Schottky diode is a unipolar device. (2) Storage time is small as the depletion layer is negligibly small. (3) As the forward resistance of the Schottky diode is small, noise becomes smaller. (4) The reverse breakdown potential of a Schottky diode is very small. 12. The process in which two dissimilar materials in close contact produce an electrical voltage due an incident light or other radiant energy is called photovoltaic effect. 13. GaAs is a semiconductor having closely spaced Γ, L, and X energy valleys in the conduction band. When the electric field is low, majority of the electrons remain in the Γ valley, which has lower energy. As the electric field is increased, the electrons get transferred to L and X valleys where the effective mass of the electrons becomes larger resulting in lower mobility and decreased conductivity. Therefore, the resistivity increases, and hence the current decreases. This is called the transferred electron effect or the Gunn effect.

Appendix

1239

14. An IMPact ionization Avalanche Transit-Time (IMPATT) diode makes use of the avalanche multiplication and transit time effect to display a negative dynamic resistivity suitable for millimeter wave communication.

Chapter 3 1. The three main limitations of a half-wave rectifier are (i) smaller dc output voltage, (ii) excessive ripple, and (iii) relatively poor efficiency. 2. (i) Double the value of the dc output voltage, (ii) smaller ripple, and (iii) better efficiency 3. It is the maximum voltage that appears across the diode terminals when it is reverse biased. PIV of the diode in a HW rectifier and in a bridge rectifier is Vm and that of the diode in a FW rectifier is 2Vm , where Vm is the maximum swing of the sinusoidal input. 4. For a HW rectifier, g = 1.21�and that for a FW rectifier its value is 0.48. 5. The output of a rectifier comprises unwanted ac components at 50c/s (power supply frequency) and integer multiples (harmonics) of this frequency. This unwanted ac in the output is called ripple. As a result of ripple, the dc output voltage will have fluctuations. A filter is used to eliminate the fluctuations in the output dc voltage. 6. Transformer utilization factor is useful in determining the rating of the transformer and is defined as the ratio of the dc power delivered to the load ( Pdc ) to the ac power rating of the transformer secondary Pac TUF =

Pdc Pac

7. The ratio of the rms value of the output voltage (current) of the rectifier to the dc value of voltage (current) is known as the form factor. F=

I rms V or F = rms I dc Vdc

8. If the PIV rating of the diode used in a circuit is less that required, then another diode is connected in series with the first diode. This is known as stacking the diodes. If n identical diodes are stacked, then the PIV of the diode stack is n times the PIV of the individual diode. 9. The two main advantages of a bridge rectifier are the following: (i) The PIV of each diode is half the PIV of the diode used in conventional FW rectifier. (ii) There is no need for a center-tapped transformer. However, the disadvantage is that four diodes are used in place of two diodes. 10. g is inversely proportional to L and directly proportional to RL. Hence, for g to be small, L should be large and also RL should be small. It implies that inductor filter is better used to reduce ripple when the load current is large. 11. Ripple becomes small when C is large or RL is large. Hence, it may be concluded that a capacitor filter is best used with lower load currents. 12. In an inductor filter, the ripple is small only when the load current is large, and in the case of a capacitor filter the ripple is small only when the load current is small. Combining L- and C-type filters, the ripple can be reduced at all values of load current, which means that the ripple is now independent of load resistance.

1240

Appendix

13. The current i in the inductance, in an LC filter, contains a dc component Idc. As the value of L increases, i decreases. L should be chosen so that i does not become 0. This value of inductance is called critical inductance. 14. In an LC filter, if for any reason suddenly RL → ∞, the output voltage abruptly jumps to no-load voltage, resulting in poor regulation. A fixed resistance that is connected in shunt with the load RL at the output terminals of the filter so as to ensure minimum inductor current is called the bleeder resistance. 15. Multiple filters are used to reduce ripple to a value as small as possible.

Chapter 4 1. As the conduction in a transistor is mainly due to two types of charge carriers, namely electrons and holes, a transistor is called a bipolar device. Electrons are the majority carriers in the N-type material and holes are the majority carriers in the P-type material. 2. Charges are injected from the highly doped emitter into the base. Base is made very thin and is lightly doped so as to enable these injected charges to diffuse into the collector region, thereby constituting a current in the device. 3. When the base–emitter diode is forward biased by a voltage more than Vg and the base– collector diode is reverse biased, the transistor is said to be in the active region. This type of biasing is used when the transistor is used for linear and nonlinear applications as well. 4. Only when there is a base current, there exists a collector current. The output collector current can be controlled by the base current. This is the reason why a transistor is called a current-controlled device. 5. A silicon transistor is preferred over a Germanium transistor mainly because it has smaller leakage current (ICO), which assures better thermal stability. 6. A transistor is operated in the following three basic configurations: (i) common emitter (CE) configuration, (ii) common base (CB) configuration, and (iii) common collector (CC) configuration. 7. a dc is the dc current gain in the CB configuration and is the ratio of IC to IE. Its value is typically of the order of 0.98 (less than 1). 8. The ratio of IC to IB is the dc current gain in the CE configuration and is designated as bdc . Its value is usually much larger than 1. 9. The interrelationship between mdc and bdc is shown below: bdc =

a dc bdc or a dc = 1 − a dc 1 + bdc

10. The CC configuration has the maximum current gain and is given as follows: g dc =

1 = 1 + bdc 1 − a dc

11. Breakdown can occur in a reverse-biased transistor due to (a) reach through or punch through and (b) avalanche multiplication. 12. When the reverse-bias voltage at the collector junction is increased, at some value of this reverse-bias voltage, the transition region can penetrate completely into the base to reach the emitter junction, thereby reducing the effective base width practically to zero. Under

Appendix

13. 14.

15.

16.

1241

this condition, the collector voltage has practically reached through the base region. This is known as reach through or punch through. When avalanche breakdown occurs atVCB = VCBO(max ), the current in the transistor increases many folds, say M nICO, where M n is the avalanche multiplication factor. The dc values of the collector current IC and the collector to emitter voltage VCE specify the operating point. The operating point specifies the dc condition set under no signal condition or quiescent condition. If the amount dissipation in the transistor is more than the dissipation the device can handle, the junction gets heated, the temperature of the junction increases, leakage current increases, and the junction still further gets heated and so on, resulting in what is called thermal runaway of the junction. The resultant self-destruction of the transistor is called thermal runaway. As the reverse bias on the base–collector diode is made to increase, the width of the depletion region penetrates much more into the base region than into the collector region as the base is lightly doped. The variation of the effective base width with VCB is known as Early effect or base width modulation.

Chapter 5 1. The application of external dc voltage/voltages so as to establish a required value of IC (dc or quiescent collector current) and VCE (dc or quiescent collector to emitter voltage) is called biasing. 2. The three basic methods of biasing a transistor are (i) forward–forward basing (transistor is in saturation), (ii) forward–reverse basing (transistor is in the active region), and (iii) reverse–reverse biasing (transistor is in cut-off). 3. The coordinates of the Q-point are ICQ and VCEQ. 4. When the quiescent collector current ICQ is chosen such that ICQ = IC(sat)/2, then VCE ≈ VCC/2. This type of biasing is called mid-point biasing. The advantage is that when an input signal is applied, there results a maximum possible output swing with respect to the quiescent values of collector current and collector-to-emitter voltage. 5. Usually in fixed bias arrangement, two separate dc sources are needed, a VBB source to forward bias the base–emitter diode and a VCC source to reverse bias the base–collector diode. Its main limitation is that the operating point is liable to change with temperature. 6. As bdc changes with temperature variations, the operating point also changes. Maintaining the operating point stable, even if there are temperature variations, is called bias stabilization. 7. A resistance RE is included from the emitter to the ground terminal (in CE configuration), which is essentially meant for ensuring the stability of the operating point, that is, the operating point remains stable even with temperature variations. 8. Although the collector-to-base feedback bias provides stability to the operating point, the feedback resistor from the collector to the base also produces negative feedback under ac condition and reduces the gain of the amplifier. This is why this type of biasing is not preferred. 9. In a biasing circuit, the stability of the operating point can be ensured by providing negative feedback. However, with negative feedback, the gain of the amplifier gets reduced. To overcome this problem, circuit elements such as diodes, thermistors, and sensistors are connected in such a way that any variation in leakage currents is nullified by an identical variation in these devices.

1242

Appendix

10. A thermistor is a temperature-sensing element that exhibits a large change in resistance proportional to a small change in temperature. Thermistors can have both positive temperature coefficient (its resistance increases with temperature) and negative temperature coefficient (its resistance decreases with temperature). 11. Sensistor is a temperature-sensing element that exhibits a large change in resistance proportional to a small change in temperature. Its resistance increases with temperature, that is, its temperature coefficient is positive. 12. The stability factor S is defined as the ratio of the incremental change in IC to the incremental change in ICO, assuming that bdc and VBE remain constant.

Chapter 6 1. A CE amplifier is widely used because its current gain, voltage gain, and power gain are large. Its main limitations are relatively small input resistance ( ≈ hie ) and relatively large  1  output resistance  ≈  hoe  2. The main application of a CC amplifier is as a buffer amplifier, mainly because it has unity voltage gain, high input resistance, and a small output resistance. 3. The CB configuration has the smallest current gain and its value is approximately 1. 4. The CC configuration has the largest current and its value approximately is − hfc = −(1 + hfe ). 5. Amplitude distortion occurs is an amplifier when the input signal swing is large in which case the operation of the transistor is not limted to the linear region in the dynamic transfer characteristic around the operating point. Amplitude distortion gives rise to harmonic distortion. 6. Half-power frequency is the frequeny at which the power is half the power in the midband range. If P is the power in the mid-band range, then at the half-power frequency, the power is P/2. 7. Bandwidth is defined as the difference between the two half-power frequencies, f1 and f2. In the simplest of the terms, by bandwidth it may mean as the frequency range in which if the amplifier is operated, the gain almost remains constant. 8. In a CE amplifer, to provide bias stability a resistance RE is connected from the emitter to the ground. However, under ac conditions, this resistor reduces the gain of the amplifier. Hence, to avoid loss of gain, a large condenser CE is connectd in shunt with RE to effectively produce a short-circuit path for the flow of ac component of current. As CE is mainly meant to bypass ac component of current, it is called a bypass condenser. 9. Miller’s theorem is often used to replace an impedance that appears between the input and output terminal of an amplifier by two impedances: one connected in shunt with the input terminals and the other connected in shunt with the output terminals. The theorem is used to reduce the feedback amplifier configuration into an amplifier configuration without feedback. 10. A CE amplifier with unbypassed emitter resistance RE is essentially a feedback amplifier. The dual of the Miller’s theorem enables the replacement of RE by two resistances: one connected in series with the input terminals and the other connected in series with the output terminals. Thus, it helps in reducing the feedback amplifier configuration into an amplifier configuration without feedback.

Appendix

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Chapter 7 1. An FET is called a unipolar device because conduction is only due to the majority carriers that can be either electrons or holes. 2. A transistor is a current controlled device, whereas an FET is voltage-controlled device. 3. As the reverse-bias voltage between the gate and source terminals is increased, the depletion region penetrates more and more into the channel, thereby reducing the conduction in the channel. The reverse-bias voltage at which the channel is pinched-off (no more current flows in the channel) is called the pinch-off voltage. 4. The transfer characteristic is a curve that relates a variable ID on the output side and a variable VGS on the input side. This curve helps in the proper choice of the operating point. 5. The parameter rd is called the drain resistance of the FET and is defined as the ratio of an incremental change in VDS and a corresponding change in ID with VGS constant and is given by rd =

∆VDS ,VGS = constant ∆I D

6. The transconductance, gm is defined as the ratio of an incremental change in ID for a corresponding change in VGS at VDS constant and is given by ∆I D ,VDS = constant ∆VGS

gm =

7. The amplification factor, m is defined as the ratio of an incremental change in VDS for a corresponding change in VGS at constant ID and is given by m=

∆VDS , I D = constant ∆VGS

8. From the characteristics of the N-channel JFET, it can be seen that for small values of VD, ID increases linearly, and the value of ID becomes smaller as VGS becomes more and more negative. It can, therefore, be concluded that an FET behaves as a voltage variable resistance—the value of this resistance becomes larger as VGS becomes more and more negative. 2 I DS I DSS 9. gm = VP 10. A MOSFET is also called an insulated gate field effect transistor (IGFET) because in this device the gate is insulated from the channel. 11. The expression for the voltage gain of the CS amplifier is A=

− mRL rd + RL

and that of the CS amplifier with un-bypassed source resistance is A=

− mRL rd + RL + RS ( m + 1)

1244

Appendix

12. A CD amplifier is also known as a source follower. The corresponding BJT circuit is called the emitter follower.

Chapter 8 1. Since the gain of a single-stage amplifier is limited, in order to get a large desired output for a small given input, it becomes necessary to cascade a number of amplifier stages. 2. The three popular interstage coupling techniques used in multistage amplifiers are (i) RC coupling, (ii) transformer coupling, and (iii) direct coupling 3. The mid-band range in an RC-coupled amplifier is defined such that at the highest limit of the mid-band range, the coupling capacitor behaves as a short circuit and the lowest limit of the mid-band range, the shunt condenser behaves as an open circuit. 4. This effect of AV approaching 1 makes the amplifier exhibit a property popularly known as bootstrapping. The term bootstrapping implies that Vi and Vo change simultaneously in a similar manner in both magnitude and phase. 5. Miller effect accounts for an increase in the equivalent input capacitance of an inverting voltage amplifier (CE) due to amplification of capacitance between the input and output terminals. Miller effect can modify the amplifier input impedance. 6. A CE–CB amplifier is called a cascode amplifier. The two main advantages are the following: (i) As the input resistance of the CB stage which acts as the load for the CE amplifier is small, its gain approximately reduces to 1 and the bandwidth increases. Hence, a cascode amplifier is suitable for high-frequency applications. (ii) As the output stage is a CB amplifier that has high output impedance, a cascode amplifier can be used as a good current source. 7. The main advantage of the Darlington pair is its high current gain, since the collector current of Q1 is the base current of Q2. The hFE of the composite transistor is the product of hFE1 and hFE2 of the individual transistors. Normally, hFE1 = hFE 2 = hFE. 8. The input resistance of an emitter follower using a Darlington transistor is very high because of its high current gain. Therefore, where there is need for large input resistance, to avoid loading the driving voltage source, a Darlington emitter follower is used. 1

9. As f2 c = f2 2 3 − 1, the bandwidth of the three-stage amplifier is f2 c = 0.510 f2. 10. The dc voltage at the output of the amplifier is required to change only when an input signal is present. However, due to temperature changes, hFE changes, the collector current changes; and therefore, the output voltage changes. The change in the dc voltage at the output of the amplifier due to the device parameter variation is called the drift.

Chapter 9 1. Negative feedback is used in an amplifier essentially to stabilize its gain. 2. The gain with negative feedback in an amplifier becomes smaller when compared to the gain without feedback. 3. The following are the advantages, when negative feedback is provided in an amplifier: (i) Improved gain stability, (ii) Improved bandwidth, and (iii) Reduced harmonic distortion and noise 4. Vs’ = DVs , where D = 1 + Ab

Appendix

5. Af =

1245

A 100 = = 10 1 + Ab 1 + 100 × 0.09

6. Basically, there are two methods of sampling used: (i) voltage or node sampling and (ii) current or loop sampling. 7. Basically, there are two methods of mixing: (i) series and (ii) shunt. 8. With series mixing, the input resistance of the amplifier increases as Rif = Ri D . R 9. With shunt mixing, the input resistance of the amplifier decreases as Rif = i . D 10. (i) To draw the input loop of the amplifier without feedback,set, Vo = 0, if the sampled signal is a voltage and set I o = 0 if the sampled signal is a current. (ii) To draw the output loop of the amplifier without feedback, set, I i = 0 if it is case of series mixing and set Vi = 0, if it s case of shunt mixing. 11. The new bandwidth with feedback is f2’ = f2 (1 + Ab ). 12. A voltage series feedback amplifier is also called an emitter follower.

Chapter 10 1. An amplifier is one that gives an output depending on the magnitude of the input, and the gain of the amplifier and the output frequency is essentially the same as the input frequency. There is the need for an external input signal to derive an output. However, an oscillator is an amplifier in which, if the Barkhausen criterion is satisfied, gives a sinusoidal output with zero input. The frequency of the output signal depends only on the components employed in the tank circuit. 2. The condition, 1 + Ab = 0 , is called the Barkhausen criterion. It stipulates two conditions that need to be satisfied for the oscillations to build up sustain in an oscillator: (i) The loop gain, Ab ≥ 1. This is known as the amplitude condition. (ii) The overall phase shift around the circuit must be 360° (zero) or 2p radians to provide positive feedback. This is known as the phase condition. 3. LC oscillators are not preferred in the audio frequency range mainly because of the fact that LC components tend to become bulky and occupy more space. 4. A Colpitts oscillator is preferred over a Hartley oscillator for the following reasons: (i) It is possible to get ideal capacitors but not ideal inductors. (ii) When two coils are wound on a common core, as in a Hartley oscillator, there exists mutual coupling between the coils. 5. The two main advantages of the Clapp oscillator over the Colpitts oscillator are the following: (i) The frequency of oscillations is independent of the effect of the stray capacitances and the transistor parameters. (ii) Frequency of oscillations can be varied comfortably by using C3 as a variable condenser. 6. Crystal oscillators are used in transmitters and receivers mainly because of their very high frequency stability 7. Amplitude stability is achieved in a Wien bridge oscillator by employing negative feedback using a tungsten lamp. 8. Beat frequency oscillator is preferred in the audio frequency range because of its improved frequency stability. However, its main limitation is that the circuit becomes more complex and expensive.

1246

Appendix

Chapter 11 1. A voltage amplifier is a small-signal amplifier, which can be analyzed by using the lowfrequency model of the transistor or by using the graphical procedure. No harmonic distortion is present in its output. Voltage gain is the only requirement in this amplifier. A power amplifier is a large-signal amplifier in which the requirement is power gain. It can only be analyzed by using the graphical procedure. Harmonic distortion is invariably present in its output. 2. As a power amplifier is a large-signal amplifier, so as to have a sufficient input signal drive, a voltage amplifier is used as a preamplifier to a power amplifier. 3. A class-A power amplifier is one in which there is an output for the entire input cycle period. To accomplish this, under class-A condition, the transistor is operated in the active region and is provided mid-point biasing. 4. The main limitations of a class-A series-fed power amplifier are the following: (i) conversion efficiency is only 25 percent, (ii) maximum dissipation occurs in the transistor under no signal conditions, that is PD(max) = 2PL, and (iii) harmonic distortion is present in the output of the amplifier. 5. Conversion efficiency improves by a factor 2. The conversion efficiency of the class A single-ended transformer-coupled power amplifier is 50 percent. Its main limitation is that, as large dc collector current flows through the primary winding of the transformer, the magnetic circuit may saturate, giving rise to distortion. 6. The advantages of class-B operation are (i) hmax = 78.5%; (ii) as even harmonics are eliminated, the harmonic distortion reduces drastically; and (iii) as center-tapped transformer is used, dc collector currents of equal magnitude flow in the opposite directions in the primary winding of the output transformer, thereby saturation problem of the magnetic circuit is eliminated. 7. The two major limitations of class-B operation are (i) as each transistor is biased at cutoff, cross-over distortion is present in the output of the amplifier and (ii) difficult to get transformers with exact electrical center tap. 8. As the transformers on the input and output sides have efficiencies of the order of 70–75 percent, the output power is reduced. 9. A class-D amplifier is one in which the transistors are used as switches, so that the power wasted in the devices is practically zero, resulting in near 100 percent efficiency. 10. The advantages are the following: (i) No need for center-tapped transformer (ii) Reduced size and cost (iii) temperature compensation can be easily provided in the circuit

Chapter 12 1. The Miller capacitance in shunt with the input terminals is CMi = C ′ (1 − A)and the Miller capacitance that appears in shunt with the output terminals is CMo = C ′. 2. The resistance offered by the thin base region in a transistor is called the base-spreading resistance. Its value depends on the effective width of the base and the amount of doping and varies typically between 100 Ω and 1000 Ω.

Appendix

1247

3. The b cut-off frequency of a CE amplifier is the frequency at which the short-circuit current gain0.707 hfe . 4. fT is the frequency at which the short-circuit current gain of a CE amplifier falls to unity. 5. fT = hfe fb . 6.

fa =

fb 1 − hfb

Chapter 13 1. In certain applications, like in an AM transmitter and receiver, there arises the need for amplifiying signals of narrow bandwidth. Therefore, tuned amplifiers are used where there is a need to derive a large gain with narrow bandwidth. 2. Q is the figure of merit of the tank circuit. The response of a resonant circuit is highly selective for large Q, or relatively flat for small Q. The tank circuit is usually a parallel resonant circuit comprising L (with R as the associated resistance) and C, for which, Q = wL R = wCR. 1 A 3. The expression for the relative gain is = Ar 1 + j 2dQe 4. The relation between bandwidth and resonance frequency in a single-tuned amplifier is f given as follows: BW = o . Qe 1

5. The bandwidth of n identical stages is BWn = BW1 2 n − 1. 6. Double-tuned amplifiers are classified as (i) synchronously tuned amplifiers and (ii) stagger-tuned amplifiers. 7. A synchronously tuned double-tuned amplifier has two mutually coupled tuned circuits and both the tuned circuits are tuned to the same center frequency. However, although a stagger-tuned amplifier also has two tuned circuits, these are tuned to two resonant frequencies that are separated by the bandwidth of a single-tuned amplifier. 8. The bandwidth of the synchronously tuned double-tuned amplifier is 3.1 times the bandwidth of the single-tuned amplifier. 9. The bandwidth of stagger tuned amplifier is 2 times the bandwidth of a single-tuned amplifier. 10. At high frequencies, noise and random variations and feedback through stray capacitances may drive the tuned amplifier into generating oscillations. This means that the amplifier no longer behaves as an amplifier as is expected but behaves as an oscillator. 11. The problem of instability in a tuned amplifier can be eliminated by using the following methods of stabilization: unilateralization, mismatching, and neutralization. 12. A tuned class-C amplifier may be used as an amplitude modulator and as a harmonic generator. 13. In the high-frequency range, because of Miller effect, the gain of an amplifier is likely to fall. Shunt compensation is provided to keep the response flat and thus improve the bandwidth.

1248

Appendix

Chapter 14 1. An op-amp is a multistage, high-gain direct-coupled amplifier in which negative feedback and temperature compensation are provided to stabilize its gain. Since it was developed to perform mathematical operations such as addition, subtraction, multiplication, division, integration, and differentiation in analog computers, it is named as operational amplifier. 2. The following are the basic building blocks of an op-amp: (i) dual-input, balanced-output differential amplifier (ii) dual-input, unbalanced-output differential amplifier, (c) DC-level shifter, and (d) complementary symmetry output power stage. 3. The ideal characteristics of an op-amp are as follows: (i) Ad, the open-loop gain is infinity, (ii) Ri, the input resistance is infinity, (iii) Ro, the output resistance is zero, (iv) bandwidth is infinity, and (v) VO = 0, when V1 = V2, where V1 and V2 are the inputs. 50 + ( −50 ) V + V2 4. The common-mode signal, Vc = 1 = = 0 and the differential signal, 2 2 Vd = V1 −V2 = 50 − ( −50 ) = 100 mV 5. When CMRR is very large. 6. Since the output of the second stage (dual-input, unbalanced-output differential amplifier) in an op-amp contains a dc component, which when applied to the output power stage will alter the bias conditions, resulting in distortion. To avoid this situation, a dc-level shifter is provided so as to translate the output dc level of the second stage to a zero level. 7. To derive a large input resistance, sometimes Darlington transistors are used in a differential amplifier, since Darlington transistors have large current gain. 8. The bias current is IB =

I B1 + I B2 600 + 400 = = 500 nA 2 2

and the off-set current is I io = I B1 − I B 2 = 600 − 400 = 200 = nA 9. Slew rate of an op-amp is defined as the maximum time rate of change of the output voltage under large signal conditions. It is expressed as follows: S=

2pfVm 10 −6

V mS

10. It is required that the op-amp should not break into oscillations in the frequency range of operation. Therefore, frequency compensation networks are connected so as to make sure that the internal phase shift in the desired frequency range of operation with the required value of gain never reaches 180° and thus oscillations are not generate.

Chapter 15 1. A =

−RF R1

2. A = 1 +

RF R1

Appendix

1249

3. A summing amplifier is one in which the output voltage is proportional to the sum of the input voltages. 4. A subtracting amplifier is one in which the output voltage is proportional to the difference of the input voltages. 5. The advantages of buffer amplifier are (i) large input resistance that will not load the driving source. (ii) low output resistance that ensures that the entire output signal is connected to the load. (iii) Large bandwidth. Since gain is 1, the bandwidth is UGB and for IC741 it is 1 MHz. 6. The two main limitations of this circuit are (i) At f = 0, A = ∞. This large gain can give rise to a large output offset voltage, which can cause distortion in the presence of a signal and (ii) the 3 dB bandwidth tends to be very small. A practical integrator overcomes these limitations, in which a resistance RF is connected in shunt with the feedback capacitor. R The main advantage in this circuit is that at f = 0, A = F ,�since C behaves as an open R circuit. 7. The main requirements of instrumentation amplifiers are (i) high gain and gain stability (ii) high input resistance (iii) low output resistance (iv) high CMRR and low dc offset voltage drift. 8. Based on how the load is connected, V − I converters can be classified as (i) V – I converter with floating load and (ii) V − I converter with grounded load. 9. A comparator can be used as a zero-crossing detector and level detector. In addition to these applications, a comparator can also be used as a window detector and as time-marker generator. 10. The output of this amplifier can change with temperature, since I S and VT are temperature dependent parameters.

Chapter 16 1. A filter is a circuit that passes electric signals at certain frequency ranges while preventing the passage of others. 2. As the roll-off is only −20 dB/decade in a first-order filter, to derive a steeper roll-off, n filter stages can be connected in tandem. 3. When compared to an ideal filter, an RC low-pass filter lacks in the following characteristics: (i) The pass-band gain decreases well before the corner frequency, fH, thus amplifying the lower pass-band frequencies more than the upper pass-band frequencies. (ii) The transition from the pass-band into the stop-band is not sharp, but happens gradually. (iii) The phase response is not linear. Therefore, the signal gets distorted significantly 4. The main limitations of passive filters are (i) the amplitude of the output signal is less than that of the input signal, (ii) the load impedance affects the filters characteristics, (iii) in cascaded filter stages attenuation becomes quiet severe, and (iv) when multiple stages are cascaded there can be loading effect between successive filter stages, which results in further loss of signal. 5. Active filter circuits contain active components such as operational amplifiers, transistors, or FETs with the main objective of providing amplification. The two main advantages of

1250

6.

7. 8.

9. 10.

Appendix

active filters are (i) the loss of signal can be made up by using active filters and (ii) isolation can be provided between successive stages by using buffers to avoid loading. An all-pass filter has a constant gain across the entire frequency range, and a phase response that changes linearly with frequency. Because of these properties, all-pass filters are used in phase compensation and signal delay circuits. Active filters can be of four configurations: (i) Butterworth, (ii) Chebyshev, (iii) Bessel, and (iv) elliptic filters. A Butterworth filter is one which has the Butterworth polynomial in the denominator of the transfer function. These filters have a flat amplitude-frequency response up to the cutoff frequency and have a monotonic drop in gain with increase in frequency in the stop band region, with the roll-off rate of − n × 20 dB/decade for f > fc , the cut-off frequency. Butterworth filter is also called as maximally flat or flat flat filter. Higher-order filters are used to obtain the stop band characteristic of an ideal filter. A notch filter is a narrow band reject filter that rejects a narrow band of frequencies around the center frequency and allows all other frequencies to the output.

Chapter 17 1. The output of the TRF power supply can change mainly due to the following factors: (i) The input voltage Vi to the circuit can change due to fluctuations in mains voltage. As a result the DC output voltage as well as the ripple in output can change. (ii) Due to changes in load resistance RL, the load current IL can change, resulting in a change in the output voltage. (iii) Due to changes in temperature the device parameters can change, which in turn could change the output voltage. 2. Ripple rejection is the ability of the power supply to reject ripple and is usually expressed in dB. It is defined as the ratio of the peak-to-peak ripple voltage, Vor(pp) in the output to the peak-to-peak to ripple voltage, Vir(pp) at the input. Vor(pp) Ripple rejection = 20log10 dB. Vir(pp) 3. The output voltage of a TRF power supply can change due to many factors. Hence there arises the need for voltage regulators, whose purpose is essentially to ensure that the output voltage almost remains constant, irrespective of the variations in the input voltage, load current, or temperature. 4. The main limitations of the simple Zener regulator are as follows: (i) The Zener current varies by larger amounts, (ii) relatively poor regulation, and (iii) large amount of dissipation occurs both in the Zener diode as well as in the series limiting resistance, RS, when compared to RL. 5. The main limitations of the transistor shunt regulator are as follows: (i) An appreciable power loss across the series resistance RS. (ii) A large current flows through the transistor. Hence the transistor chosen should have a larger power dissipation capability. (iii) Overload or short-circuit protection cannot be implemented in a shunt regulator. (iv) The output strictly cannot be maintained constant because VBE and VZ are likely to change with temperature 6. The main advantage of the transistor series regulator is that overload or short-circuit protection can be implemented

Appendix

7.

8. 9.

10.

11. 12.

13. 14.

1251

However, its limitations are that (i) VO strictly cannot be maintained constant because both VBE and VZ can change with temperature, and (ii) the power dissipation in the series pass transistor, PD (=VCEIC) becomes larger for larger load currents. When a regulated power supply is used, it is possible that there could be an overload, that is, RL may decrease. Hence, the load current increases with the resultant decrease in output voltage. Or sometimes, it may be possible that the output terminals of the power supply may accidentally get shorted, resulting in a very large load current, which will damage the regulator and the associated components. To avoid these problems, overload or short-circuit protection is usually provided in the regulated power supplies. The two methods used to provide current limit and overload protection are (i) constant current limit and (ii) fly-back current limit. The various types of protection mechanisms implemented in a regulated power supply are (i) overload or short-circuit protection, (ii) overvoltage protection, (iii) reverse polarity protection, and (iv) thermal shutdown. Some of the advantages of the IC regulators are (i) low cost, (ii) wiring and operation is simple, (iii) compact in construction, (iv) low output ripple, and (v) features such as overload and short-circuit protection and thermal shutdown can be integrated into the IC, which makes the IC versatile. IC regulators are broadly classified as (i) linear regulators and (ii) switching regulators. The main limitation of a linear regulator is the excessive amount of power dissipation in it, mainly because the series pass transistor operates in the active region. The efficiency of the linear regulator as such is small. In a switching regulator, the unregulated dc input is switched ON and OFF at a rate decided by an external source. As the transistor is simply used as a switch, the dissipation in the regulator is negligible and the efficiency of the regulator is very much improved. Switching regulators are (i) buck-type regulator, (ii) boost-type regulator, and (ii) buck– boost-type regulator. An SMPS is an electronic power supply that uses a switching regulator to convert electrical power efficiently.

Chapter 18 1. Multivibrators are of three types: (i) bistable, (ii) monostable, and (iii) astable. 2. A bistable multivibrator is a regenerative switching circuit, in which two inverters are connected back to back. It has two stable states: Q1 ON and Q2 OFF is one stable state and Q1 OFF and Q2 ON is the other stable state. 3. A bistable multivibrator is also known as binary, scale of two circuit, flip-flop, and Eccles–Jordan circuit. 4. A binary is basically used as a one-bit memory element in digital circuits. 5. In a saturating binary, the ON transistor is driven hard into saturation resulting in a longer storage time and reduced switching speed. To reduce the storage time and improve the switching speed, a nonsaturating binary is used. In the nonsaturating binary, the ON transistor is held in the active region. 6. When the output of the binary is made to drive a load, it may be possible that the voltage at the collector of the OFF transistor may fall to a value much below VCC . Consequently, the second transistor may not be driven into saturation. To ensure that this collector

1252

7.

8.

9. 10.

11.

12.

13. 14. 15.

Appendix

voltage is not allowed to fall below the set threshold, an auxiliary dc source V ( < VCc ) is connected at the collector through the collector-catching diode. Transition time, tt is the time taken for conduction to be transferred from one transistor to the other, after the application of the trigger. This time delay can be drastically reduced by connecting commutating condensers C1 and C1 in shunt with R1 and R1, the cross-coupling resistors. Resolution time of the binary is the minimum time interval that needs to be allowed between the successive trigger pulses so as to be reliably able to drive the multi from one stable state to the other. It is the sum of the transition time and the settling time. The two methods of pulse triggering a binary are (i) un-symmetric or asymmetric triggering and (ii) symmetric triggering. Unsymmetric triggering is a method of pulse triggering in which one trigger pulse taken from a trigger source is applied at one collector to drive the devices into second stable state. However, the next trigger pulse taken from a different source is applied at the second collector to drive the devices back into the initial stable state. This method of triggering is used to generate a gated output and the width of the gate depends on the spacing between the successive trigger pulses. Symmetric triggering is the method of pulse triggering in which successive trigger pulses taken from the same source and applied at the same point in the circuit will drive the multi from one stable state to the other. This method of triggering is used in counters. The expression for the gate width of the collector-coupled monostable multivibrator is T = 0.69RC . This expression is valid only when the ON transistor is driven into saturation, in the quasistable state. 0.7 f = RC A Schmitt trigger is used as (i) a binary, (ii) a squaring circuit, (iii) a comparator, etc. The voltage difference between the upper trip point V1 and lower trip point V2 is called the range of hysteresis, VH and is also called dead zone.

Chapter 19 1. A sweep circuit is one that is used to deflect the electron beam linearly as a function of time along the X-axis in CROs and television and radar receivers. 2. There are three types of errors that define deviation from linearity, namely, slope error or sweep speed error, displacement error, and transmission error. 3. For a UJT sweep circuit, displacement error is the smallest of the three types of errors. 4. For a UJT sweep circuit, slope error is the largest of the three types of errors. 5. The main limitation of the UJT sweep circuit is that the sweep voltage generated is not necessarily linear unless the supply voltage is very much larger than the sweep amplitude or the time constant of the circuit is very much larger than the sweep duration. 6. In Miller and bootstrap sweep circuits, to derive a linear sweep, the capacitor is charged with a constant current. 7. In the Miller’s sweep circuit, the fictitious generated is represented by an inverting amplifier of gain infinity. 8. In the bootstrap sweep circuit, the fictitious generated is represented by an non-inverting amplifier of gain unity.

Appendix

1253

9. The time required for the bootstrap capacitor C2 to regain the charge lost during the sweep formation is called the recovery time. 10. A linear current sweep is generated by driving the current sweep circuit by a trapezoidal waveform.

Chapter 20 1. An integrated circuit is a low-cost miniature electronic circuit that contains active components such as diodes and transistors and passive components such as resistors and capacitors, all fabricated on a single silicon chip. 2. The following are some the major advantages of ICs over the discrete component circuits: Small size and weight, low cost, reliability, low power consumption, easy trouble shooting, and increased speed of operation due to elimination/minimization of parasitic capacitances. 3. The basic IC manufacturing technologies are monolithic, thin and thick film, and hybrid. 4. Monolithic IC is one in which all the circuit components (both passive and active) and their interconnections are formed completely within a silicon substrate. 5. The basic processes involved in the fabrication of monolithic IC using planar technology are (i) substrate production, (ii) wafer preparation, (iii) epitaxial growth, (iv) oxidation, (v) photolithography, (vi) diffusion, (vii) metallization, and (viii) packaging. 6. The two processes involved in photolithography are (i) preparation of the mask and (ii) photoetching. 7. Diffusion is the process of introducing impurities into the selected regions of the silicon wafer. The impurity atoms have the tendency to move from regions of higher concentrations to regions of lower concentrations. 8. Metallization is the process of depositing a thin-film aluminum layer that is required for the interconnecting the various circuit components on the chip. 9. The three most common types of packages are (i) transistor-outline (TO) package, (ii) flat package, and (iii) dual inline package (DIP). 10. (i) It serves as a hard protective coating to prevent any contamination of the epitaxial layer. (ii) By selective etching of SiO2, impurities can be diffused through carefully defined windows to fabricate both active and passive components.

Chapter 21 1. IC 555 timer consists of two comparators, one RS flip flop, a discharge transistor, a reset transistor, an inverting buffer, and a resistive voltage divider network. 2. The expression for the pulse width is,

T = 1.1RAC .

3. The duty cycle is given by the following relation: 4. In the 555 timer, the UTP is set at

D=

RA + RB RA + 2RB

2VCC , and the LTP is set at VCC . 3 3

5. The control voltage changes the threshold and trigger levels. 6. If the modulating signal applied to the control terminal is a sinusoidal signal, then the pulse width of the monostable circuit varies in accordance with the instantaneous amplitude of the sinusoidal signal.

1254

Appendix

Chapter 22 1. An SCR is an acronym for silicon-controlled rectifier. It is a three-terminal, four-layered device that can be thought of as an interconnection of PNP and NPN transistors, in which regenerative feedback is provided by the gate current pulse. It can be considered as a controlled rectifier, where the period of conduction of the device can be controlled by the external gate pulse. 2. The current in SCR when it is conducting is controlled by an external impedance. 3. It is the minimum forward voltage at which the SCR starts conducting heavily or turned ON, with I G = 0. This is also called the breakover voltage. 4. It is the maximum anode current the SCR can handle safely, that is, without being damaged. 5. It is known that once the SCR fires the gate loses control. Some SCRs may be turned OFF by applying a negative pulse. But in some SCRs, to drive the device into the OFF state once it is driven into the ON state, forced commutation technique may have to be employed. By forced commutation it is meant forcing a current which is equal and opposite of the forward conduction current to drive the SCR into the OFF state. 6. An SCR is used in power electronics for control applications. Hence protective circuit must be provided to avoid damage to the device. A snubber is a circuit used to protect an

7.

8.

9.

10.

11.

 di  SCR. It is used for limiting the rate-of-rise of currents   through the semiconductor  dt   dv  device at turn-on and for limiting the rate-of-rise of voltages   through the SCR at  dt  turn-off. TRIAC is an acronym for TRIode for Alternating Current, meaning that it is a three terminal bidirectional switch. TRIAC, in fact, comprises two thyristors connected together in inverse parallel, but they share a common gate terminal. A DIAC is a two-terminal, four-layered silicon device. The DIAC is an acronym for DIode for Alternating Current. The device can be switched ON or OFF by a signal of either polarity. The diodes are avalanche diodes that conduct only when the breakdown voltage, VBO, is reached. An SCR, once ON, can be switched OFF by forced commutation. GTO is like an SCR, the only difference being that the device can be turned ON by the application of a positive gate trigger pulse and can be switched OFF by a negative gate trigger pulse. A light-activated SCR (LASCR) is a three-terminal, four-layered unilateral device just like an SCR, except that it can also be light triggered. Some LASCRs have clear windows in their cases so that light sources from other devices can be coupled to them. Some LASCRs have the light source encapsulated in the same package. When light falls on depletion layer, the LASCR turns on just like a normal SCR. An optoelectrical phenomenon in which a semiconductor material becomes more electrically conductive due to the absorption of electromagnetic radiation is called photoconductivity. This radiation can be in the form of visible, ultraviolet and infrared light, or gamma radiation.

Appendix

1255

12. A light-dependent resistor (LDR) or a photoresistor offers resistance in response to the incident light. This means LDR exhibits photoconductivity. It is made up of cadmium sulfide (CdS) and its resistance decreases as the intensity of incident light increases, and vice versa. When no light falls, LDR offers a resistance of the order of mega-ohms. 13. Dark current is the current in the photodiode when no light is incident on the device. 14. A photovoltaic or solar cell consists of a thick N-type crystal covered by a thin P-type layer. The electron–hole pairs generated due to solar radiation produce an electric field in the depletion layer that drives the electrons to the N-type side and the holes to the P-type side. This, to a greater extent, prevents recombination of the electrons and holes. Thus, solar radiation is converted into electrical energy. 15. A light-emitting diode (LED) is a semiconductor light source. LEDs can emit light across the infrared, visible, and ultraviolet wavelengths, with very high brightness. LED is special type of P–N junction diode, made from a very thin layer of fairly heavily doped semiconductor compounds such as gallium arsenide (GaAs), gallium phosphide (GaP), gallium arsenide phosphide (GaAsP), silicon carbide (SiC), or gallium indium nitride (GaInN), all mixed at different ratios. The actual color is determined by the wavelength, l of the light emitted. l is determined by the semiconductor compound used in forming the P–N junction. 16. Optocouplers are devices used to transfer data from one subsystem to another within the same electronic equipment, without making a direct ohmic electrical connection. Optocouplers are used to transmit either analog or digital information from one voltage level on the transmitter side to another to another voltage level on the receiver side, maintaining isolation. An optocoupler consists of a light source such an LED as a transmitter and a light detector like a photodetector as a receiver. 17. Liquid crystals are neither solids nor liquids. The molecules in liquid crystals tend to maintain their orientation, like the molecules in a solid, but also move around to different positions, like the molecules in a liquid. Liquid crystal display consists of a liquid crystal material embedded between a pair of transparent electrodes. The characteristic of a liquid crystal is that it controls the phase of the light passing through it by the application of the voltage between the electrodes. If such a unit is placed between a pair of plane polarization plates, then light can pass through it only if the correct voltage is applied. 18. Fibers are classified in terms of mode of transmission as (i) fibers that support a single propagation path or transverse mode are called single-mode fibers. A single-mode fiber optic cable has a core of small diameter that allows only one mode to propagate. In a single-mode fiber, the core to the cladding diameter ratio is 9–125 µ and (ii) fibers that support many propagation paths or transverse modes are called multimode fibers. Multimode fibers generally have a wider core diameter that allows multiple modes. 19. Based on the refractive index profile of the core and cladding, optical fibers are classified as (i) step-index fibers and (ii) graded-index fibers. A step-index fiber exhibits a step-index profile, that is, the refractive index remains constant throughout the core of the fiber, while there is an abrupt decrease in the refractive index at the interface between the core and the outer covering, or cladding. In a graded-index fiber, the refractive index of the core is made to vary as a parabola with refractive index being maximum at the center of the core.

1256

Appendix

20. A multimeter enables the measurement of ac and dc voltages and currents and also resistance. An electronic voltmeter, however, can be used to measure only ac and dc voltages and resistance. There is usually no direct provision for measuring current in an electronic voltmeter. Current is measured by knowing the voltage drop across a known resistance. The main advantage of electronic voltmeters over multimeters is their high input resistance. 21. In analog voltmeters, the display is by a pointer reading on a PMMC meter. Digital voltmeter enables a numerical readout, which eliminates strain on the observer. 22. A 3-digit DVM will read from 000 to 999 mV, if the full-scale range is 1 V and the smallest 1 increment is 1 mV. The resolution of a DVM, R = n , where n is the number of digits. 10 1 23. For a 3-digit DVM, the resolution, R = 3 = 0.001 or 0.1%. A 3½-digit meter can read 10 from 0000 to 1999. It can resolve the input signal into 1999 parts. A meter with enabled half-digit is used to indicate that the applied input has exceeded the meter’s measurement capability. 24. A CRO can be used to measure amplitude, frequency, and phase of electrical signals. 25. The deflection sensitivity of a CRO is defined as the amount of vertical deflection of the electron beam per unit deflecting voltage. 26. A sawtooth waveform is applied to the X-deflecting plates to move the spot linearly as a function of time along the X-axis. 27. Lissajous patterns are patterns displayed on the screen of an oscilloscope when the horizontal and vertical deflecting plates are driven by two different sinusoidal waveforms having frequencies in a certain ratio and certain phase shift. 28. A dual-trace CRO is one in which there is only one electron gun and deflecting system. However, two signals can be displayed on the CRT screen by switching the electron beam between the vertical deflecting plates. 29. A dual-beam CRO has two electron guns and two deflecting systems to display two waveforms simultaneously on the CRT screen. However, a dual-trace CRO has only one electron gun and deflecting system, but two signals can be displayed simultaneously by beam switching. 30. A spectrum analyzer is a versatile instrument meant to display the amplitudes of various frequency components in a given signal on the CRT screen.

Chapter 23 1. Law 1: This law states that the complement of a sum of variables is equal to the product of their individual complements, A + B = A.B Law 2: This law states that the complement of a product of variables is equal to the sum of their individual complements

AB = A + B

2. A bubbled gate is one whose inputs are inverted. Let the inputs to the AND gate be A and B, then the bubbled inputs to the AND gate are gate with bubbled inputs is ( A + B) = ( A ⋅ B ) .

A and B . The output of the AND

( A ⋅ B ) . The output of the NOR gate with inputs A and B is

Appendix

1257

Hence, bubbled AND gate works as NOR gate, (Figure . 23.52). A B

A

A.B

BUBBLED AND

B

=

A.B NOR

Figure 23.52 3. Ans: NAND AND NOR gates are called universal gates, because with a combination NAND and NOR gates only it is possible to create all other logic gates like AND, OR, XOR, etc.

(

)

(

)

4.

F = A + ( BC ) ′ ′ = A′ ( BC ) ′ ′ = A′ BC

5.

A = 1 and ( A + B)′ = 0 ⇒ (1 + B)′ = B ′ = 0 ⇒ B = 1

6.

f(x, y, z) = x + yz = x + yz(x + x′ ) = x(y + y′ ) + xyz + x′yz = xy(z + z′ ) + xy′(z + z′ ) + xyz + x′yz = xyz + xyz′ + xy′z + xy′z′ + xyz + x′yz Eliminating redundant terms,

f(x, y, z) = xyz + xyz′ + xy′z + xy′z′ + x′yz = ∑(3, 4, 5, 6, 7) 7. Product of maxterms form is f(a, b, c) = ∏M(0, 1, 4) 8. Using Boolean algebra,

x + x′y = x(y + y′ ) + x′y xy + xy′ + x′y = xy + xy′ + xy + x′y = x(y + y′ ) + y(x + x′ ) Since x + x′ = 1 or y + y′ = 1 Therefore, x + x′y = x + y 9. (001010011)2

1258

Appendix

10.

Logic familes

Bipolar logic family

Saturated logic families (i) Resistor–transistor logic (RTL) (ii) Direct–coupled transistor logic (DCTL) (iii) Integrated–injection logic (I2L) (iv) Diode–transistor logic (DTL) (v) High–threshold logic (HTL) (vi) Transistor–transistor logic (TTL)

Unipolar logic family

Non–saturated logic families (i) Schottky TTL (ii) Emitter–coupled logic (ECL)

(i) PMOS (ii) NMOS (iii) CMOS

11. TTL gates have faster switching speed and CMOS gates have lesser power dissipation. 12. The fan-in of a logic gate is the maximum number of inputs that it can accept, without degrading its normal operation. Fan-out specifies the number of standard loads that the output of a gate can drive without degrading its normal operation. 13. LOW-state noise margin (LNM) = VIL(max)_ VOL(max) where VIL(max) = maximum input voltage that can be treated as a LOW (Logic 0) level and VOL(max) = maximum output voltage that can be treated as a LOW (Logic 0) level HIGH state Noise Margin (HNM) = VOH(min) _ VIH(min) where VOH(min) = minimum output voltage that can be treated as a HIGH (Logic 1) level and VIH(min) = minimum input voltage that can be treated as a HIGH (Logic 1) level. 14. Noise immunity is the ability of the logic gate to tolerate a certain amount of unwanted voltage fluctuations at the input due to noise without altering its output state. It is usually specified as poor, fair, good, or excellent. 15. The propagation delay for a gate is the time required for the output to respond to a change at the input. Propagation delay is measured as follows: tp = Propagation delay =

tPHL + tPLH 2

where, tPHL = Delay for the output to change from HIGH to LOW tPLH= Delay delay for the output to change from LOW to HIGH 16. The analog signal is first required to be sampled at the Nyquist rate; hence, the need for the sampling circuit. However, the amplitude of the sampled signal may vary during the sampling period. The amplitude sampled signal is held constant by a HOLD circuit. 17. Minterms contain literals corresponding to all the variables in ANDed form and maxterms contain literals corresponding to all the variables in ORed form. 18. SOP form is a logic expression in the form of ANDed terms ORed together and POS form is a logic expression in the form of ORed terms ANDed together.

Appendix

1259

Chapter 24 1. A microprocessor is a multipurpose, programmable logic device that reads binary instructions from a storage device called memory, accepts binary data as input and processes data according to those instructions and provides the result as the output. The power supply of 8085 is +5 V and clock frequency is 3 MHz. 2. It is used for the following purposes: (i) Measurements, display, and control of current, voltage, temperature, pressure, etc. (ii) Traffic control and industrial tool control (iii) Speed control of machines 3. The accumulator is the register associated with the ALU operations and sometimes I/O operations. It is an integral part of ALU. It holds the data to be processed by ALU. It also temporarily stores the result of the operation performed by the ALU. 4. Stack pointer (SP) and program counter (PC) 5. SID is an input line through which the microprocessor accepts serial data. SOD is an output line through which the microprocessor sends output serial data. 6. The part of the instruction that specifies the operation to be performed is called the operation code or Op-code. 7. It is a status signal. It is used to differentiate between memory operations and I/O opera— tions. When this signal is low (IO/(M) = 0), it denotes the memory related operations. — When this signal is high (IO/(M) = 1), it denotes an I/O operation. 8. The data on which the operation is to be performed are called an operand. 9. There are 74 operations in the 8085 microprocessor. 10. 1. Data transfer group—MOV, MVI, LXI. 2. Arithmetic group—ADD, SUB, INR. 3. Logical group—ANA, XRA, CMP. 4. Branch group— JMP, JNZ, CALL. 5. Stack I/O and machine control group— PUSH, POP, IN, HLT. 11. A JMP instruction permanently changes the program counter. A CALL instruction leaves information on the stack so that the original program execution sequence can be resumed. 12. The IN instruction is used to move data from an I/O port into the accumulator. The OUT instruction is used to move data from the accumulator to an I/O port. The IN and OUT instructions are used only in microprocessors that use a separate address space for interfacing 13. A rotate instruction is a circular instruction. That is, the data are moved out at one end is put back in at the other end. The shift instruction loses the data that are moved out of the last-bit locations. 14. HOLD and HLDA. 15. Disable interrupts (DI) Enable interrupts (EI) Read interrupt masks (RIMs) Set interrupt masks (SIMs) 16. Interrupt is an external signal that causes a microprocessor to jump to a specific subroutine.

1260

Appendix

17. The 8085 microprocessor has five interrupt inputs: TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. These interrupts have a fixed priority of interrupt service. If two or more interrupts go high at the same time, the 8085 will service them on priority basis. The TRAP has the highest priority followed by RST 7.5, RST 6.5, RST 5.5 and INTR. 18. The instruction set is grouped into the following formats: 1-byte instruction—MOV C, A 2-byte instruction—MVI A, 39H 3-byte instruction—JMP 2345H 19. The various formats of specifying the operands are called addressing modes and are used to access the operands or data. The different types are as follows: 1. Immediate addressing 2. Register addressing 3. Direct addressing 4. Indirect addressing 5. Implicit addressing 20. It is used to increase the driving capacity of the data bus. The data bus of a microcomputer system is bidirectional; therefore, it requires a buffer that allows the data to flow in both directions.

C

APPENDIX

ANSWERS TO UNSOLVED PROBLEMS Chapter 1 1. n = 5 ×1014 / cm 3 , p = 0.45 × 106 / cm 3 and, s n = 0.12 ( Ω − cm ) −1 2. s = 4.33 × 10 −4 ( Ω − m ) and R = 29.4 M

−1

3. r = 0.431Ω − m 4. ri = 2.08 × 103 Ω − m 5.

(i)

N A = 1.25 × 1020 atoms / m3

(iii) n = 1.8 × 1012 atoms / m3 6.

n = N D = 2.40 × 1016 electrons / m3

(ii) p = N A =1.25 ×1020 atoms / m 3 n (iv) = 0.12 ×10 −3 ni

Chapter 2 1. 2. 3. 4. 5.

1024 20.72 (a) 0.23 Ω (b) 455.5 kΩ h = 1.97; hence, the diode is a Si diode. The transfer characteristic is shown in the below figure. Vo 10 V

−40 V 0

−20 V

20 V

V

1262

Appendix

6. 10 V Vi 0

t

−10 V

5V Vo

0

t

−15 V

Chapter 3 1. Im = 1.414 A, Idc=0.9 A, Idc (each diode) = 0.45 A, Pdc = 72.9 W, h = 72.07%, regulation = 10.07%, PIV of each diode = 282.8 V 2. Im = 1.285 A, Idc = 0.818 A, Idc(each diode) = 0.409 A, Pdc = 60.22 W, h = 65.57%, % Regulation = 18.26%, PIV of each diode = 141.4 V 3. (a) 45.45 mA (b) 45.45 V (c) 2.64 V (d) 0.058 4. (a) 42.43 V, (b) 0.116 5. 57.8 mF 6. RL = 40 Ω, L = 10 H, and C = 26.69 mF

Chapter 4 1. 2. 3. 4. 5. 6.

0.98, Ic = 5.145 mA and IE = 5.245 mA IC = 9.905 mA, IB = 0.095 mA, bdc = 99 and ICEO = 0.5 mA 111.11 kΩ IB = 0.023 mA, IC = 4 mA and VCB = 7.3V VCE = 6V and IB = 0.06 mA (i) 1.96 mW (ii) 1 µW and (iii) mW

Chapter 5 1. 2. 3. 4. 5. 6.

IC = 3.2 mA, RB = 282.5 kΩ, RC = 1.875 kΩ, and VCE = 6 V IBQ = 32.5 mA, ICQ = 2.925 mA, VCEQ = 7.9 V, and IC(sat) = 5.85 mA IC = 1.5 mA, VCE = 5.4 V, and RB = 210 kΩ q = 1°C/mW and Tj = 100°C RE = 1.4 kΩ, R2 = 7 kΩ, and R1 = 5.44 kΩ RE = 1.25 kΩ, R2 = 14.25 kΩ, R1 = 23.25 kΩ, and RC = 1.14 kΩ

Appendix

1263

Chapter 6 1. 2. 3. 4. 5. 6.

Rii = 924.44 Ω, AV = −51.51, Ro = 52.49 k Ω Ri = 50.86 kΩ, AV = 0.978 and Ro = 42 Ω Ri = 21.88 Ω, AV = 44.79, Ro = 1.32 MΩ Ri = 99.66 kΩ, AV = 0.98, and R ′ o = 1 kΩ Ri = 1.433 kΩ, R ′ i = 1.36 kΩ and AV = −122.54 Ri = 1.433 kΩ, R ′ i = 1.41 kΩ, and AV = −118.19

Chapter 7 1. 2. 3. 4. 5. 6.

(i) ID = 2.5 mA, (ii) gm0 = 3.33 mA/V, and (iii) gm = 1.67 mA/V A = −2.36, Ri = 1 MΩ and Ro = 101 kΩ ID = 2.82 mA, VGS = −2.82 V, VDS = 3.9 V, gm = 1.77 mA/V, AV = −3. 54 AV = 0.946, Ri = 0.67 MΩ, and Ro′ = 200 Ω AV = 17.03, Ri = 214 Ω, and Ro′ = 3.393 kΩ AV = 1.75, Ri = 0.67 MΩ, and Ro′ =1.77 kΩ

Chapter 8 1. 2. 3. 4. 5. 6.

AI = 10201, Ri = 10.201 MΩ, AV = 0.990, Ro = 10.1 Ω R i = 1000 Ω, AV = −196, and Ro = ∞ AV = −390 Am = −33.3, Cc = 2.65 µF, and CS = 2.39 nF CE = 100 mF AV = 0.976

Chapter 9 Af = 16.67, Rif = 6.6 kΩ, and Rof′ = 740 Ω b = 0.02 , Af = 40, and Vs′ = 0.25 V b = 1, AV = 100, D = 101, AV = 0.99, Rif = 202 kΩ, and Rof = 20 Ω b = 0.5 kΩ, GM = −40 mA/V, D = 21, GMf = −1.90 mA/V, AV = −3.8, Rif = 52.5 kΩ, and Rof = ∞ 5. b = −0.0025 mA/V, RM = −448.09 kΩ, D = 2.12, RMf = −211.83 kΩ, AV = −21.183, Rif = 429 Ω, Rof = 4.36 kΩ, and Ro′ = 2.33 kΩ 6. b = 0.0476, AI = 426.3, D = 203.9, AIf = 2.09, AV = 1.045, Rif = 4.27 Ω, Rof = ∞, and Rof′ = 5 kΩ 1. 2. 3. 4.

f

f

f

f

Chapter 10 1. Cmax = 25 nF and Cmin = 0.25 nF 2. (i) f0 = 480 kHz (ii) f0 = 478 kHz and f0 = 482 kHz 3. f = 1.233 MHz and Amin = 5 4. f = 1.3 kHz and F = 67.79° 5. fmax = 33.88 kHz and fmin = 33.88 Hz

1264

Appendix

Chapter 11 1. (i) 21.3% (ii) 8% 2. P L′ = 5.56 W, PBB = 7.05 W, h = 78.85% 3.

(i)

PL′ (max) = 0.5 W

( ii ) I C = 0.1 A ( iii ) a =

N1 = 3.16 N2

4.

(i) 50% (ii) 25%

5.

( i ) PBB = 61.20 W ( ii ) PL (max ) = 34.56 W ( iii ) PD(each) = 13.32 W

6.

( iv ) % h = 56.47% (i) PD = 0.833 W (ii) PD = 2.5 W

Chapter 12 1. AV = −29.41, fb = 10 MHz s

2. Ce = 50.0 pF, fT = 305.73 MHz 3. gm = 0.192 mhos, rb ′ e = 260 Ω, rbb ′ = 740 Ω, rb ′ c = 2.6 MΩ, rce = 210.53 kΩ, Ce = 609.47 pF 4. fb = 2.04 MHz and fT = 204 MHz 5. gm = 0.192 mA/V, rb ′ e = 1 kΩ, hfe = 192, Ce = 150 pF, fa = 204.88 MHz, fb = 0.995MHz and fT = 9.95 MHz 6. AV = −50 and Ci = 156.5 pF

Chapter 13 1. 2. 3. 4. 5. 6.

L = 7.96 mH and C = 3.14 pF. L = 0.05 mH, fmax =3.185 MHz, R = 3.14 Ω fo =5 MHz, Qe = 5.22 and BW = 957.85k � Hz L = 3.185 mH, R = 0.135 Ω and C = 78.49 pF C = 766 pF and L = 130.5 mH (i) BW2 = 6.43 kHz and BW3 = 5.1 kHz (ii) BW2 = 8.02 kHz and BW3 = 7.14 kHz

Chapter 14 1. VC 1 = VC 2 = 7.85 V, VC 3 = VC 4 = 10.01 V 2. Ad1 = 160.6, Ad1 = 142.29, Ad = 22852, Ri = 3.64 kΩ and R0 = 5 kΩ

Appendix

3. 4. 5. 6.

1265

(i) 19.5% (ii) 0.195% and (iii) 0.0195% R2 = 2.28 kΩ, R3 = 580 Ω, and RE = 1.86 kΩ I B = 90 mA and I io = 20 mA RC = 9.3 kΩ

Chapter 15 1. 2. 3. 4. 5. 6.

A = −80.8, Ri = 500 kΩ Vo = 3 V (i) 24.87 mV (ii) 259 mV Vo = −2.22 V f = 60.61 Hz and duty cycle = 33% R1 = R2 = R3 = 40 kΩ, R4 = 30 kΩ, R5 = 60 kΩ

Chapter 16 1. R2 = 79.6 kΩ, R3 = R = 10 kΩ, C1 = 0.01 mF, Q = 0.56 2. C2 = 0.01 mF, R2 =15.92 kΩ, C1 = 0.01 mF, R1 =79.6 kΩ, R3 =R = 10 kΩ, R4 = 12 kΩ, and RC = 4 kΩ 3. C2 = C3 = C = 0.01 mF, R5 = 159 kΩ, R1 = 1.59 kΩ, R4 = 531.6 Ω 4. R1 = 10 kΩ , R2 = 5.85 kΩ, R = 1.85 kΩ , and C = 0.086 mF 5. R1 = 10 kΩ , R2 = 5.85 kΩ, R = 1.85 kΩ , and C = 0.086 mF 6. C = 0.01 mF, R =3.98 kΩ, R1 = 10 kΩ, and R2 = 30 kΩ

Chapter 17 1. 2. 3. 4. 5. 6.

I L (min) = 40 mA, RL (min) = 143 Ω, and RL (max ) = 250 Ω Vi(min) = 35 V and Vi(max ) = 50 V Vo = 6.1 V, I L = 12.2 mA, I B = 0.20 mA, and I Z = 89.8 mA R2 = 8 kΩ VO(max ) = 15 V and VO(min) = 10 V RL(min) 300 Ω, Wattage of RL = 75 W, VZ = 7.5 V, PZ = 0.19 W, PD1 = 7.8 W, PD2 = 123 mW, R1 = R2 = R3 ≈ 1 kΩ, and R4 = 415 Ω

Chapter 18 1. VBB = 2 V, R = 40 kΩ , C = 0.725 mF, and R1 = R2 = 30 kΩ 2. (i) VB2 = 0.7 V, VC2 = 0.2 V , VB1 = −4, 87 V, VC1 = 11.425 V and (ii) RL (min) =13.61 kΩ 1 3. (i) RC = 4.4 kΩ, C = 0.01 mF , R = 10.9 kΩ and (ii) f = = 3.31 kHz T 4. RC = 3 kΩ, C1 = C2 = C = 0.01 mF, R1 = 58 kΩ , R2 = 86.96 kΩ 5. UTP = 7.56 V, LTP = 4.82 V VCC 6. = 0.414 V

1266

Appendix

Chapter 19 1. fs = 819.7 Hz 2. R = 47 kΩ, C = 3.09 nF, VS(p − p) = 15.4 V 3. (i) f = 3.92 kHz, (ii) es (Miller ) = 9.25% 4. (i) Ts = 833 mS , Vs = 18 V, (ii) Tr = 53 mS, f =1.13 kHz, 5. R = 1.5 kΩ, C = 0.067 mF, RB = 50 kΩ, and C2 = 0.67 mF 6. es = 12.44%.

(iii) % error = 2.1%

Chapter 21 1. 2. 3. 4. 5. 6.

0.11ms, 1.1ms, 11ms f = 1.385kHz and D = 54.81% RA = 6 kΩ, RB = 4kΩ, CA = 0.029mF R1 = 11.52 kΩ, R = 11.52 kΩ, R4 = 5.76 kΩ T1 = 0.104 ms, T2 = 0.028 ms and f = 757.58 Hz C = 10mF and RA = 721.5 kΩ = RB

Chapter 22 1. 2. 3. 4.

Rs1 = 100 Ω, Rs2 = 8.93 Ω, and Rs2 = 5.26 Ω Rs = 2.14 Ω, Rs1 = 20 kΩ R1 = 10 kΩ , R2 = 8 kΩ, and R3 = 1.95 kΩ Ammeter: Rs1 = 0.002 Ω and Rs2 = 0.001 Ω, voltmeter: Rs1 = 9.99 kΩ and Rs2 = 99.99 kΩ.

Chapter 23 1. (i) 23.610 = 10111.10011002 and (ii) 65.53510 = 41.88F5C2816 2. (i) (6)10 = (0110)2, (ii) (10)10 = (1010)2 3. SOP form is F = A·BC + CD + BD + AD POS form is F = (A + B+C) · (C + D) (B + D) (A + D) 4. A + B + C 5. A(B + D) + C(B + D) 6. −0.039 V

Chapter 24 [The answers are not unique and may vary depending on the skills of the programmer. And hence not included]

I

INDEX

For entries corresponding to pages 1157 to 1207, please refer to Chapter 23. For entries corresponding to pages 1208 to 1231, refer Chapter 24. Chapters 23 and 24 are given through QR codes. b-network 426 Ac characteristics of Op-amp 727 Advantages of negative feedback 433 Avalanche multiplication 177 Bandwidth of n-stage amplifier 392 Barkhausen criterion 493 Beat frequency oscillator 519 Bias Compensation 221 Bias compensation 736 Bias stability 200 Biasing JFETs 317 Bleeder resistance 134 Breakdown diodes 65 Bulk resistance of the diode 56 Carbon composition resistor 1 Carrier lifetime 95 Cascaded differential amplifier 722 Cascaded filters 135 Clamping circuit theorem 79 Clamping circuits 75 Class A push-pull power amplifier 555 Clipping circuits 67 CMRR 708 Collector feedback bias 211 Compound amplifiers 364 Continuity Eqation32 Cross-over distortion 559 Crystal oscillators 517 Dark current 92

Darlington emitter follower 378 Dc characteristics of Op-amp 725 DC level shifter 723 DC load line 198 Derating factor 546 Differential amplifier 707 Diffusion current 30 Diffusion or storage capacitance 58 Direct coupled amplifier 395 Distortion in amplifiers 264 Distortion in Power amplifiers 539 Double tuned amplifiers 667 Drift current density 29 Dynamic resistance of the diode 56 Early effect or base width modulation 159 Ebers-mole model of the transistor 173 Einstein’s Equation 31 Emitter bias 204 Energy associated with electron orbits 13 Energy band diagram 43 Energy level diagram 15 Feedback amplifier 425 Fermi energy level 21 FET amplifiers 334 FET as a voltage variable resistance 333 Film resistor 1 Filters 122

Fixed bias 202 Forward biased junction diode 45 Frequency compensation in Op-amp 732 Full wave rectifier 115 Half wave rectifier 109 Hall Effect 33 Heat sinks 568 h-parameter conversion 270 h-parameter model 247 Impedance adjustment through tapped circuits 666 Instability in tuned amplifiers 678 Insulators, conductors and semiconductors 18 Intrinsic or pure semiconductors 19 Law of the junction 47 LC oscillators 493 Mass action law 24 Measurement of Op-amp parameters 739 Miller effect 373 Miller’s theorem and its dual 278 Noise 265 N-type semiconductors 24 Operating point 199 Parameters of the FET 307 Peak inverse voltage 108 Pinch-off voltage 304 P-type semiconductors 26 Quality factor of L and C 646

1268

Index

RC coupled amplifier 381 RC oscillators 506 Reach through or punch through 177 Reverse biased junction diode 46 Sampling network 425 Semiconductor resistor 2 Series-fed class A power amplifier 540 Single tuned amplifiers 647 Specification of a resistor 5 Switching times in a diode 63 The universal bias curve 328 Thermal resistance 226 Thermal runaway 167 Transferred electron effect 97 Transformer coupled amplifier 393 Transistor current components 154 Transition capacitance 59 Tuned power amplifiers 680 Tunneling 81 Types of capacitors 8 Voltage divider bias 213 Wideband amplifier 687 Wire-wound resistor 2

Linear applications Op-Amp Adder-subtractor 763 Current to voltage converter 785 Differentiator 773 Instrumentation amplifier 779 Integrator 767 Inverting amplifier 749 Non-inverting amplifier 754 Subtracting amplifier 760 Summing amplifier 758 Voltage to current converter 783

Non-linear applications Op-Amp All-pass filter 855 Antilog amplifier 802 Astable multivibrator 788

Butterworth filter 829 Comparator 791 Constant current limit 883 Divider 806 Feedback regulator 891 Fold-back current limit 885 Linear IC regulators 896 Logarithmic amplifier 800 Monostable multivibrator 786 Multiple feedback topology 845 Multiplier 805 Notch filter 852 Passive filters 823 Precision rectifiers 807 Sallen-Key topology 832 Schmitt trigger 798 Switched capacitor filters 856 Transistor series regulator 878 Transistor shunt regulator 874 Zener shunt regulator 868

Switching regulators 555 timer 1055 Boost-type regulator 908 Bootstrap sweep generator 1022 Buck-boost regulator 909 Buck-type regulator 905 Collector catching diodes 943 Collectror-coupled astable multivibrator 978 Collectror-coupled monostable multivibrator 963 Commutating condensers 950 Compensated attenuator 948 Current sweep generator 1026 Displacement error 1018 Exponential sweep generator 1006 Fixed bias binary 937 Heaviest load the binary can drive 941 Maximum switching speed of the binary 952 Miller’s sweep generator 1019 Monolithic integrated circuit 1039 Non-saturating binary 955 Programmable Uni-junction transistor 1014

Resolution time of the binary 952 Schmitt trigger 988 Self-bias binary 956 Settling time 951 Slope error 1016 Switched mode power supply 909 Switching times of the transistor 936 Symmetric triggering of a binary 953 Transistor as a switch 933 Transition time 950 Transmission error 1017 UJT relaxation oscillator 1011 Uni-junction transistor 1007 Unsymmetric triggering of a binary 952 Voltage multipliers 911 Voltage to frequency converter 986 Voltage to time converter 976

Applications of 555 timer 16-bit microprocessor 1223 1s complement 1161 2s complement 1161 556 dual timer 1076 8085 addressing modes 1221 8085 Bus structure 1209 Arithmetic Logic Unit 1213 Arithmetic operations 1218 Assembly language 1216 Astable multivvibrator 1061 Average reading voltmeter 1132 Binary arithmetic 1160 Bistable circuit 1072 Boolean algebra 1165 Branching operations 1220 Cathode ray oscilloscope 1145 Characteristics of logic families 1193 CMOS gates: CMOS NAND gate 1190 CMOS NOR gate 1191 CMOS NOT gate 1189 DC ammeter 1121 DC voltmeter 1125 De Morgan’s laws 1168

Index

Diac 1094 Digital frequency meter 1140 Distortion analyzer 1143 Don’t care conditions 1183 Dual slope integration type digital voltmeter 1134 Dual trace CRO 1149 Electronic voltmeters 1129 Energy meter 1138 Exclusive OR gate 1174 Frequency divider 1074 FSK generator 1075 Graded index fiber 1120 GTO thyristor 1096 Hexadecimal numbers 1164 Instruction formats 1222 Instruction set 1217 Interrupt control 1213 Karnaugh map 1176 Laser diode 1105 Latching 1088 Light activated SCR 1096 Light dependent resistor 1099

Light emitting diode 1102 Liquid crystal display 1112 Logical operations 1219 Machine language 1216 Measurement of power 1136 Monostable multivibrator 1057 Moving iron voltmeter 1127 Multimeter 1128 Multi-range voltmeter 1125 Nixie displays 1109 Octal numbers 1162 Ohm meter 1127 Opto-couplers 1107 Peak reading voltmeter 1132 Peak to peak detector 1132 Photo conductivity 1097 Phototransistor 1101 Plasma display panels 1114 Pulse width modulator 1072 R-2R D/A converter 1195 Ramp type digital voltmeter 1133 Refractive index 1115

1269

Register array 1210 Representation of negative numbers: Seven-segment LE display 1110 Silicon controlled rectifier 1085 Solar cell 1101 Spectrum analyzer 1143 Step index fiber 1118 Successive approximation type ADC 1200 Time period measurement 1141 Triac 1092 TTL gates: TTL NAND gate with to tem-pole output 1187 TTL NOR gate with totem-pole output 1188 TTL NOT gate 1186 Universal gates 1171 Voltage controlled oscillator 1066 Wave analyzer 1142