Westinghouse silicon controlled rectifier designers handbook. [2d ed.]

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Westinghouse SILICON CONTROLLED RECTIFIER DESIGNERS HANDBOOK

Leslie R. Rice — Editor

Contributing Authors H. Ferree D. Knott A. MeyerliofT R. M. Roth G. M. Sherbondy H. A. Steinbruegge

Second Edition September, 1070

Westinghouse Electric Corporation Semiconductor Division Youngwood, Pennsylvania

U-70.HA

Primed 1» U.S.A.

The circuit diagrams included in this handbook are included for illustration of typical SCR thyristor applications and arc not intended as constructual information.

Although reasonable care

has been taken in their technical correctness, no responsibility is assumed by the Westinghouse Electric Corporation for any conse¬ quences of their use. The semiconductor devices, circuits and arrangements disclosed herein may be covered by patents of Westinghouse Electric Corpo¬ ration or others, Neither the disclosure of any information herein nor the sale of semiconductor devices by Westinghouse Electric Corporation conveys any license under patent claims covering circuits or combinations of the semiconductor devices with other devices or elements. In the absence of an expressly written agreement to the contrary, Westinghouse Electric Corporation assumes no liability for patent infringement arising out of any use of the semi¬ conductor devices with other devices or elements by any purchaser of semiconductor devices or others.

FOREWORD Since its introduction more than ten years ago, the silicon con¬ trolled rectifier has become a key building block in control systems of almost every conceivable application. The development of devices with improved frequency and power handling capabilities in recent years has created an urgent need for a publication with the most up-to-date information on device design and application. This handbook has been designed by its editor to give the equip¬ ment designer and the user this kind of information. The goal has been to make this book not only more comprehensive but more useable as well. New Sections on noise, transients and harmonics and a tabulation of DC switching circuits and nominal design data plus enhanced sections on power conversion (including inverters), choppers, and polyphase circuits for the conversion of AC power make the coverage more complete. Added illustrations, examples and design aids - especially the directly useable polyphase waveforms for current analysis in Chapter 12 - make this handbook more useable. A number of our most experienced applications and ratings engineers and our customers have all had a hand in the production of this handbook. Wc published our first handbook in 10(14. Us outstanding popu¬ larity was a result of its unique design point-of-view. We promised a revised handbook when warranted by new techniques. That time we feel lias now most assuredly arrived. To make this handbook the most complete ever done on SCR design technique, the entire book has been rewritten. Every recommendation, word, and diagram has been examined for relevance to today's needs. Wc believe that this thoroughness has paid off in a truly useful publication. We hope that you'll agree. J. C. Marous, General Manager

V

TABLE OF CONTENTS

1.0 Principles ami Basic Theory of Operation 1.) P-N Construction. 1.2 Voltage Blocking Capabilities. 1.3 Turn-On and Conduction Characteristics. 1,-1 Turn-Off and “Gate Control1' Characteristics.

1-1 I-:} l-(i 1-10

2.0 Device Construction and Processing 2.1 Silicon Wafer Preparation. 2.1.1 Crystal Cutting. 2.1.2 Lapping. 2.2 Formation of the P-N Junctions. 2.3 Evaluation of the Wafer after Junction Formation. 2.3.1 Determination of the Impurity Concentrations and Their Distribution in the Silicon Wafer. 2.3.2 Determination of Carrier Lifetime. 2.4 Joining the Silicon Wafer to a Metallic Substrate. 2.5 Junction Contouring and Surface Passivation.. . 2.5.1 Junction Contouring. 2.5.2 Surface Passivation. 2.0 Encapsulation of the Semiconductor Element. 2.0.1 Attaching the Semiconductor Element to a Suitable Mousing can be Performed in a Number of Ways. 2.0.2 I lard Solder Construction. 2.0,3 Compression Bonded Encapsulation Technique. 2.7 Mechanical Designs for Device Encapsulation. 2.7.1 Stud Mounted. 2.7.2 Flat Base Construction. . 2.7.3 The Integral Heat Sink SCR Thyristor. 2.7.4 The Disc Construction for Double Sided Cooling. 2.7.5 Epoxy Encapsulated SCICs.

2-12 2-12 2-12 2-14

3.0 Terminology and Symbols 3.1 Terminology. 3.1.1 Voltage Terminology. 3.1.2 Current Terminology. 3.1.3 Gate Parameters. 3.1.1 Power Conditioning Terminology. 3.1.5 Switching Time Terminology. 3.1.0 Gate Turn-Off Terminology. 3.2 Symbols. 3.2.1 Rectifier Symbols. 3.2.2 Transistor Symbols. 3.2.3 Thyristor Symbols.

3-1 3-2 3-3 3-4 3-5 3-6 3-8 3-1) 3-1) 3-1) 3-10

4.0 SCR Ratings and Characteristics 4.1 Blocking Characteristics.. 4.1.1 Reverse Voltage V'kH.. 4.1.2 Reverse Blocking Transient VrBt. 4.1.3 Forward Voltage YVu. 4.1.4 Forward Blocking Transient V|rBT. 4.1.5 Forward Breakover Voltage V»o.. 4.2 Gate Characteristics. 4.3 Junction Temperature.

4-1 4-1 4-2 4-2 4-2 4-2 4-2 4-2

2-1 2-1 2-1 2-1 2-3 2-3 2-0

2-7 2-8 2-S 2-8 2-8 2-8 2-8 2-10 2-12 2-12

TABLE OF CONTENTS (Cont’d)

4.4

Forward Current Characteristics. 4-3

4.5

Thermal Resistance. 4-5 4.5.1 Ratings for Thermal Resistance. 4-5 4.5.2 Transient Thermal Impedance. 4-6 4.5.3 Thermal Impedance Calculations for Irregular Current Waveforms. 4-9

4.0

Additional Current Ratings for the Thyristor. 4-9 4.0.1 RMS Current. 4-11 4.6.2 l2t Rating. 4-11 4.6.3 Surge Current Rating I pm.. 4-12

4.7

Dynamic Characteristics. 4-12 4.7.1 di/dt or the Rate of Rise of Anode Current. 4-12 4.7.2 Dynamic Turn-On Voltage. 4-12 4.7.3 dv/dt Critical Rate of Rise of Forward Voltage. 4-12 4.7.4 Re-applied dv/dt. 4-15

4.8

1„h Turn-Off Time. 4-16

4.9

Gate Controlled Switch (CCS). 4-17 4.9.1 Variables of Gate Turn-Off.. 4.9.2 Gate Input Characteristics.

4-17 1-17

4.9.3 Low Frequency Gate Turn-Off. 4-18 4.9.4 Pulsed Gate Turn-Off. 4-19 5.0 Test Circuits and Procedures 5.1

Introduction. 5-1

5.2

Static Tests. 5-1 5.2.1 AC Forward and Reverse Blocking Characteristics. 5-1 5.2.2 Peak On-State Voltage. 5-1 5.2.3 DC Gate Characteristics. 5-2 5.2.4 Holding and Latching Current....

5.3

5-2

Dynamic Tests. 5-4 5.3.1 Rate of Rise of Forward Voltage, DV/DT. 5-4 5.3.2 Circuit Commutated Turn-Off Time. 5-5 5.3.2.1 Turn-Off Time Test Circuit Details. 5-0 5.3.3 Turn-On Time. 5-7 5.3.4 Dynamic Forward Voltage Drop. 5-8 5.3.5 Reverse Recovery Charge. 5-8

5.4

Life Tests. 5-8 5.4.1 AC Blocking Life. 5-8 5.4.2 Operating Life. 5-9 5.4.3 Rate of Rise of Forward Current DI/DT. 5-12

6.0 Gate Characteristics and Firing Circuits 6.1

Gate-Cathode Characteristics. 0-1 6.1.1 Device Turn-On Equivalent Circuit. 0-1 6.1.2 Gate Cathode V-l Characteristics Prior to Triggering. 6-2 6.1.3 Gate-Cathode V-l Characteristics During Anode Conduction. 6-4

6.2

Device Characteristics vs Gate Conditions. 6-4 6.2.1 Gate Bias-Current effects. 6-5 6.2.2 Gate Bias-Voltage Effects. 6-5 6.2.3 Gate Impedance Effects. 6-6

6.3

Gate Ratings and Firing Circuit Design Criteria...... 6-7 6.3.1 Average Gate Dissipation r* G(AV). 6-7 viii

TABLE OF CONTENTS (Cont’d)

6.3.2 Non-Triggering Characteristics Vqnt. 6-7 6.3.3 High Drive and Soft Drive Conditions. 6-9 0.3.4 Gate Supply Load Lines. 6-12 6.4 Gate Firing Circuits. 6-13 6.4.1 Resistive and R-C Trigger Circuits. 6-13 6.4.2 Saturable Reactor Control. 6-14 6.4.3 Synchronization and Timing. 6-18 6.4.4 The Unijunction Transistor Relaxation Oscillator. 6-18 6.4.5 Shockley Breakdown Diode Relaxation Oscillators. 6-21 6.4.6 Blocking Oscillator Gate Drive. 6-22 6.4.7 Hard Firing Gate Circuitry. 6-25 7.0 AC Phase Controlled Applications 7.1

Principle of Phase Control. 7-1

7.2

Commutation in AC Circuits. 7-2 7.2.1 Commutation with Circuit Transients.. 7-2 7.2.2 Commutation with Reduced Reverse Bias. 7-4

7.3

AC Current Transients with SCR Controllers. 7-4

7.4

The Single Phase AC Switch. 7-6 7.4.1 The AC Switch with Inductive Loads. 7-8 7.4.2 Harmonic Disturbances with the AC Switch.7-8 7.4.3 Overcurrent Protection. 7-8

7.5

Three Phase AC Switch Configurations. 7-11 7.5.1 The Three-Phase Three SCR Circuit. 7-15 7.5.2 The Three-Phase Six SCR Switch Using the Ground Return and "Inside the Delta” Configuration.. 7-16 7.5.3 The Six SCR Three-Phase AC Switch for In-Line Connection. 7-16 7.5.4 The Three SCR Three Diode In-Line Switch. 7-17 7.5.5 The Four SCR Three-Phase Switch. 7-18 7.5.6 Summary of Characteristics. 7-20

7.6

Special Purpose AC Switches and Load Tap Changers. 7-27 7.6.1 Operating Characteristics of Tap Regulators. 7-27 7.6.2 SCR Regulation Systems and Flicker..

. 7-27

7.7

Variable DC Voltage Converters. 7-30

7.8

A Comparison of Three-Phase Converters. 7-30 7.8.1 Rectifier Characteristics. 7-31 7.8.2 Delay Angle vs System Res|x»nses. 7-34 7.8.3 Gate Firing Circuit Considerations. 7-34 7.8.4 Inductive Loads. 7-38 7.8.5 Inverter Operation. 7-43

7.9

DC Motor Control and Characteristics. 7-44 7.9.1 Speed Control Techniques. 7-44 7.9.2 Speed-Torque Characteristics of DC Machines. 7-46 7.9.3 Motor Reversing SCR Controls. 7-48 7.9.4 Factors Affecting Accurate Motor Speed. 7-49 7.9.5 Motor Acceleration and Armature Currents. 7-53 7.9.6 Applications of DC Motor Control. 7-54

7.10 AC Motor Control. 7-60 7.11 Battery Charging. 7-61 7.12 Special Lighting Controls. ix

7-63

TABLE OF CONTENTS (Cont’d)

8.0 DC Service and Force Commutated Applications 5.1

Turn-OIT Time Parameters and Variations. 8-1

8.2

Turn-Off Circuits and Techniques. 8-3 8.2.1 Device ToI| Time and Application Requirement. 8-3 8.2.2 Auxiliary Transistor Switch Commutation. 8-3 8.2.3 Pulse Transformer Commutation. 8-7 8.2.4 Capacitor Commutated Circuits. 8-7 8.2.5 Resonant Load Commutation. 8-7 8.2.6 l.-C Free Commutated Circuits. 8-11 8.2.7 Auxiliary L-C Commutating Circuits. 8-15 8.2.8 The Gate Controlled Switch. 8-18

8.3

Application of Thyristors for DC Motor Control. 8-10

8.4

In-Line Chopper Controller. 8-20 8.4.1 Chopper Requirements for Motor Control. 8-20 8.4.1.1 "Plugging" Chopper Controls. 8-22 8.4.1.2 Maximum Speed Connections. S-22 8.4.2 Component Selection and Design Procedure. 8-22

8.5

Application of Thyristors for DC to DC Voltage Regulation. . .. 8-20 8.5.1 Fixed Frequency, Variable Pulse Width DC Chopper Regulation. 8-31 8.5.2 Chopper Operation. 8-33 8.5.3 Design Method. 8-35 8.5.4 Design Example. 8-40 8.5.5 Conclusions. 8-42

8.0

Thyristors in Static Inverters. 8-42 S.0.1 Inverter Connections. 8-43 8.6.2 Inverter Output. 8-47 8.6.2.1 Harmonic Attenuation Via Filter Design. 8-47 8.0.2.2 Wave Shaping by Resonating the Load. 8-54 8.6.2.3 Sine Wave Synthesis.

. 8-54

8.G.2.4 Inverter Frequency Control and Voltage Regulation. 8-54 8.6.3 Inverter Design Examples.

... 8-57

8.6.3.1 Design of a Single-Phase Bridge Inverter with Tuned Output Filter - The Basic Circuit. 8-57 8.G.3.2 Design of Basic Single-Phase Parallel Inverter. 8-64 S.0.3.3 Design of a High Frequency Fluorescent Lighting Power Inverter. 8-67 8.G.3.4 The Series Inverter for Ultrasonic Generator. 8-72 8.7

Circuitry Employing the Gate Controlled Switch (GCS). 8-79

9.0 Serlesing Techniques 9.0.1 Turn-On. 9-1 9.0.2 Turn-Off. 9-2 9.0.3 Transient Voltages in the Off State. 9-3 9.0.4 Steady State Voltages in the Off State. 9-3 9.0.5 Practical Voltage Dividing Networks. 9-5 9.0.6 Power Dissipation in Shunt and Series Resistors. 9-G 9.1

Parallel Operation. 9-6

9.2

Fusing.

9.3

Sources of Transient Voltages. 9-12

... 9-8

9.4

Measurement Techniques.

9-13

TABLE OF CONTENTS (Cont’d)

0.5

Overvoltage Protection Techniques. 0-15 0.5.1 RC Surge Suppression Networks. 0-16 0.5.1.1 Basic Qualifications. 0-10 0.5.1.2 Capacity Calculations. 9-10 9.5.1.3 Capacitor Voltage Ratings. 0-17 9.5.1.4 Resistor Wattage Ratings. 9-17 9.5.2 "Crowbar” Transient Protection Circuit. 9-17

0.0

9.5.3 Capacitor Transient Protection Circuit. 0-18 RI'I Sources and Interference from SCR Circuits. 9-18 9.0.1 Radiated RPI Interference. 0-10 9.0.2 Interference and Rectifier Harmonics. 9-20

10.0 Thermal Designs 10.1

Introduction.10-1

10.2

Heat Transfer in Thyristors-Gencral Theories anti Practices.10-1 10.2.1 Sources of Heat in Thyristors.10-1 10.2.2 Modes of Heat Transfer.10-1 10.2.3 Thermal Resistance.10-1 10.2.3.1 Equations.10-2 10.2.3.2 RojC, Junction-to-Case Thermal Resistance.10-2 10.2.3.3 ROCS, Case-to-Sink Thermal Resistance.10-4 10.2.3.4 RoSA, Heat Sink-to-Ambient Thermal Resistance.10-4

10.3

General Thermal Design Data for SCR Thyristors.10-0

10.4

Measuring Techniques.10-7 10.4.1 Thermocouple Practices.10-7 10.4.2 Measuring Coolant Flow.10-7 10.4.3 Testing Procedure.10-8

10.5

Thermal Impedance Data.10-9

10-0

Typical Example of Plate Designs Using Natural Convection..

10-7

Typical Example Using Extruded-Sink Design.10-22

. 10-21

11.0 Reliability, Quality Control and Failure Mechanisms (General) 11.1

Reliability Terminology.11-1

11.2

Reliability Prediction Techniques.11-2

11.3

Reliability Assurance in Military, Space, Industrial and Commercial Applications.1.1-0

11.4

Quality Control Techniques to Achieve Reliable Product.11-0 11.4.1 Frequency Distribution.11-9 11.4.2 Control Charts.11-11 11.4.3 x Using S.11-11 11.4.4 x Using R.11-12 11.4.5 Acceptance Sampling.11-13

11.0

Device Failure Mechanisms.11-10 11.5.1 Device Contaminants in the Bulk Region.11-10 11.5.2 Device Contaminants on the Junction Surface.11-10 11.5.3 Encapsulated Related Problems.11-17 11.5.4 Mechanical Related Failures.11-17 11.5.5 Electrical Failure Modes.11-17

12.0 Design Data 12.1

Conversion Charts.12-1

12.2

Constants and Standards.12-1

TABLE OF CONTENTS (Cont’d)

12.3

Impedance Relations.12-1

12.-1

Waveform Information.12-1

12.5

Circuit Configurations and Constants.12-2

12.0

Definitions and Symbols..12-3

13.0 Technical Data.13-1

1.0

PRINCIPLES AND BASIC THEORY OF OPERATION

This Handbook is intended as an aid in the application of the reverse blocking triode thyristor. Thyristor is a generic term applying to a wide variety of semicon¬ ductors, such as the GCS or gate controlled switch, bidirectional switch, Shockley diodes and SCR’s or reverse blocking triode thyristor. These devices are constructed of alternate layers of p and n type silicon semiconductor material to achieve the de¬ sired operating characteristic. A brief summary of the common thyristors and their application mode is illustrated in Figure 1-1. Note that these devices, unlike the simpler rectifier, exhibit control of the point in the cycle wherein conduction is initiated. CIRCUIT USE

SYMBOL

DEVICE

-D— Gate Controlled Switch

V

'''1

OUTPUT VOLTAGE

DEVICE VOLTAGE

OUTPUT VOLTAGE Bi-Directional Switch OEVltE VOLTAGE

iv

— OUTPUT VOLTAGE

Shock lev Diodo

/DEVICE VOLTAGE Combinations ol th# included sketches plus transistor and zoner actions. Silicon Controlled Switch

OUTPUT VOLTAGE Silicon Controlled Rectifier SCR Reverse Blocking Triode Thyristor

~>tr

DEVICE VOLTAGE

FIG. 1-1—Commonly Used Thyristor Symbols Since this book is intended for the SCR thyristor the discussion concerns itself with its features and use. Where applicable, additional thyristors will be discussed for clarity and completeness. However, unless noted, the text pertains to the SCR alone, The SCR is a four layer PNPN device that can block voltages in either direction. If we inspeel the four alternate layers, it is obvious that there is at least one reverse biased PN junction as we pass through the device from cither direction. It is this characteristic that gives tiie SCR blocking capabilities in either direction. This chapter discusses the means and techniques whereby these control features are in¬ corporated into the device, and application. 1.1 PN CONSTRUCTION The successful fabrication of SCR's depends on the nature and quality of the PN junctions previously discussed. Therefore, great care is exercized in material selection and process techniques so us to provide superior junctions and high manufacturing yields. During the manufacturing process, the basic N type material (i.e.,-N type impurities) lias a P type region (i.e.,-1’ type impurities) alloyed or diffused onto its l - l

surface. The two extrinsic materials meet at a point in the N type material anti form a PN junction, as shown in Figure 1-2. + +

+

0

+

P Type Material

0

© 4

Depletion

4

+ © +

eg)

Region

+

O

+

eg)

©

+

0

4-

/0S

©

.

©

N Type Material

© ■

© Donor Ions 0 Accepior Ions +

Holes

“ Electrons

FIG. 1-2—Basic Silicon Junction Details

At the junction of the extrinsic materials, electrons leave the N region and holes leave the P region. This leaves a net charge across the junction and forms a field in a fashion similar to that seen in capacitors. As this field increases in intensity it forces electrons back to the N region and holes to the P region. This condition reaches equilibrium and sets up the space charge or depletion region that is required for satisfactory operation. The nature and quality of the depletion region is governed by the materials and processing that will be discussed in Chapter 2.0.

(c) P-N VI Characteristic FIG. 1-3—Basic Relations

for the P-N Junction

As the external bias across the PN junction is varied the field in the depletion region varies forsatisfactory operation. The nature and quality of thedepletion region changes accordingly so as to aid or inhibit conduction. For the forward biased junction the 1 -2

external circuit voltage overcomes (lie field in the depletion region. This causes hole and electron currents from the respective P and N regions and therefore circuit current as shown in Figure I -Ufa). However, as the external voltage is re¬ versed, it aids the electric field in the depletion region as that conduction is limited to the inherent leakages of the junction. This condition is illustrated in Figure l-3(b). The two characteristics can he combined to illustrate the V-l characteristics shown in Figure l-3(c). The single PN junction will block reverse voltages below its PKV rating but will allow current to flow in a circuit controlled fashion while forward biased. To achieve another order of control two PN junctions are formed within a single piece of silicon as shown in Figure 1-4. First quadrant control can be achieved with this structure by controlling the gate potential. As electrons arc injected into the Pl+) region some of these drift to the Pt+,N region and are drawn to the N material by the reverse bias gradient. Under proper gating conditions, this causes avalanche multiplication so that conduction occurs.

v AK

PIG. 1-4—A

PNPN

Structure with Porward liias

1.2 VOLTAGE BLOCKING CAPABILITIES The desired characteristics of an SCR involve the first and third quadrant opera¬ tion depicted in Figure 1-5. This requires that the blocking junctions be capable of supporting forward and reverse voltage in a predictable fashion. When a PN junction junction is reverse biased with low voltage only a small current flows. This current has two components. One is called the saturation current related to the type of ma¬ terial being used (low for silicon). The other is the "generation current” due to the carriers captured and released at the so called trapping centers within the depletion layer of the junction. The latter is a major current contributor in silicon. As the blocking voltage is increased, the field across the junction is also increased. It thus accelerates the few carriers in the junction region to the point that they possess enough energy to knock loose more electron-hole pairs and thus increase the leakage current. This carrier multiplication process is prevalent in the multiplica¬ tion region. As voltage increases in a silicon junction, the multiplication process will generate carriers to acquire sufficient energy within a short distance to regenerate more car¬ riers. As soon as this condition is reached, leakage current increases rapidly to a value limited only by circuit loop impedance. This is called the avalanche breakdown voltage of the junction.

Figure 1-6 shows the generalized logarithmic plot of the reverse-biased charac¬ teristics to illustrate the various regions discussed. In the regeneration region, Ir varies with the depletion layer width as the

to JjJ power of the junction voltage.

In the multiplication region, the current departs from the \-CURVE FOR HIGH OPERAT ING TEMP.

Ir

FIG. 1-6—Generalized Reverse Biased Junction Characteristics

N! PER

CM3

FIG. 1-7—Avalanche Breakdown Voltage for Uniformly Doped Abrupt Junction

1.3 TURN ON AN1) CONDUCTION CHARACTERISTICS In Figure 1-5 the forward characteristic of the SCR was characterized at different gate currents. The reason for this is due to the inherent action of the device coming into conduction via increased forward leakage currents. The PNPN structure may be visualized for simplicity by thinking of it as a specially coupled transistor pair as shown in Figure 1-8. This representation assumes that the entire device is operating as a whole. However areas remote from the gate are actually brought into conduction by other means. Therefore, this simplification does not repre¬ sent dynamic situations wherein high di/dt and cathode "spreading time" are in¬ volved. However, for conventional operation and conduction initiation the treat¬ ment is satisfactory. If the reader refers to Figure 1-8 it is obvious that the transistor pair is a regenera¬ tive connection. Current gain for the internal loop is the product of the individual transistor DC common emitter gains. It is obvious that the described connection is positive and regenerative as Ins=Ici and Ics=Iin- When the loop gain reaches unity, the base currents will be markedly increased so that saturation results or is maintained after the removal of the gate signal. At this time all the junctions are forward biased and high currents may flow from anode to cathode. This actually occurs when hpgi . ligE*->1 and ran result from leakage currents within the device as depicted in Figure 1-8 as iga, igj and ig3 which caused increased leakages due to slight biasing of the transistor pair. Several other parameters are effective in bringing about conduction of the SCR prematurely, they are: (1) Overtemperature

SCR’s exhibit a positive coefficient on leakage currents.

A rule of thumb is that the leakage current doubles for each 8°C increment. As the temperature is increased, the increasing lien's and leakage will cause con¬ duction. For reverse biased devices a thermal runaway and destruction may result.

(2)

Overvoltage—As the forward voltage is increased the leakage current in¬ creases into the avnlanehe mode. At this point the current level is such that the transistor gains are unity ami conduction results.

(3) dv/dt

The device junctions exhibit capacitance due to the separation of the

charge during blocking operation. If we refer to our analog of Figure 1-8 we can see that during rapid changes in voltage if

\_y

* tm«liiir«ol = VJ!

(ICJ« -|-t i r)■; tlvJ* (—

From this we can see how the two base currents see charging current and may bring the loop gain to unity and cause conduction. For each transistor in the complementary pair, the saturation voltage is the sum of two voltages, either Vp + Vja or

Vjj+Vjj.

Since Vjs is opposing Yp or Vp, the satura¬

tion voltage can be very low if properly designed, When all three junction voltages are added together in the device,

Vjj

will cancel one of them and the forward drop

approaches that of a single forward biased junction. The discussion thus far has treated the SCR via a transistor analog. It was also mentioned that areas remote from the gate were brought into conduction by other methods. This assumes that the device is of a filamentary or one dimensional type, meaning that the variation is only a function of distance in one direction. Since the area of a practical SCR is quite large it may he visualized as a large number of filamentary SCR's connected in parallel. Figure 1-9 illustrates the situation with live filaments An to A|S. When lc is applied to An to turn it on. J» becomes forward biased shortly afterward so that the depletion layer is shown very narrow. This small delay is necessary due to redistribution of charges. Meanwhile A.-, An, An, and An are still blocking with a wide depletion layer.

1-6

7

= *

U— DEPLETION LAYER (WIDTH ' RELATED TO VOLTAGE )

FIG. 1-9—Filamentary Representation of PNPN Structure

At this moment the complete loatl current, limited only by the total loop impedance including the SCR, is rushing into a small cross section area of one filament. The current density in (his area is extremely high, the forward drop may reach 30 to 50 volts. At the same time the anode current I a Hows in a pattern depicted by the "dash" lines. The lateral component of the current flowing in l’i and N'i regions function ex¬ actly as if two gate currents are applied to An, and both arc in the proper direction to cause Ai2 to conduct. Thus, once the gate current is applied to one filament for tiring, the action spreads rapidly into the most remote part of the structure. As the conduct¬ ing area is spreading, the current density reduces accordingly and so docs the forward drop. Due to the serial nature of action described, there is a time factor in each infini¬ tesimal sequential event. A one-dimensional spreading velocity for the ordinary SCR is shown to be in order of I O' cm see. The forward current and voltage, after the initial firing, is a function of time and load loop impedance since the device impedance is low when conducting area includes all the anode and cathode area. In a practical SCR, the structure is more than one layer of filaments. 11 is a threedimensional structure as symbolized in l'igurc 1-10. The above consideration covers the spread from An; to An; with a gate current of IB. If the same amount of Misapplied into each of the bottom filaments An through An, the spreading will he the same as in the first layer, if I,, is applied to An only, the spreading is then two dimensional and requires a longer time to reach Au,;. This is the primary reason for concentric gate-cathode location in the Westinghousc SCR's as against the side or corner firing. We have so far considered that IR is only entering An. The Pi region between filaments is actually not insulated although there is definitely a potential drop due to the finite lateral resistance of the Pi material. The I„ applied, therefore, is acting on more than one filament. The higher the I,,, the larger the area that can be turnedon initially. Conversely, as has been the experience in transistors, the delay time of turn-on will increase if the driving current or voltage is reduced. In the SCR, how¬ ever, [K is not very effective beyond a certain distance. For a large SCR the lateral drop is very significant and the spreading speed is predominantly controlled by the extremely high overdrive due to lateral (low of the load current as described in the previous paragraphs. If tlie initial forced spreading is absent, the spreading velocity is even lower. It is now obvious, for fast current rise applications, such as radar pulse modulator, etc., a conceit trie structure and a high I„ will be necessary to assure fast spreading and a larger area to be turned on initially to avoid junction burn out. To accomplish the latter requirement there are two directions to follow. The first approach is application oriented wherein the circuit designer uses gate overdrive of 3.3-5 times the Igt to in¬ sure a larger area during turn-on. The second is in device design where the SCR is designed to give better or higher initial conducting area. This is illustrated in

N|

(c) Power Integrated Circuitry

Pi

NZ

P2

(d) Interdigitated Cathode

FIG. 1-11—Cathode Geometries to Increase Dynamic Turn-on

Figure 1-11. An initial concept in device construction was to place the gate at the cathode periphery for packaging convenience. Westinghouse and other manufacturers of fast switching, high power SCR’s selected the center gate configuration for the spreading action previously described. I -9

Certain industry requirements have gone beyond the capabilities of the conven¬ tional device's high frequency characteristics so that a device with increased switch¬ ing capabilities is required. To accommodate these requirements, new cathode geom¬ etries and device constructions are available. The Power Integrated Circuit con¬ struction utilizes a pilot thyristor, fabricated on the same silicon wafer to drive a truly large area gate and thereby achieve greater turn-on areas and superior high frequency ratings. A second option is to interdigitate the cathode so that greater initial turn-on area is available. In high frequency inverters, crowbar circuits, etc., the spreading time is such that a large area device may not be completely turned on before the conduction interval ends. Therefore, these later designs are intended to bring about high initial area unit time ratios and therefore increase high frequency ratings. A pictorial presentation of the Westinghouso rff/namic gate SCR using power integrated circuit construction, is shown in Figure 1.12,

CATHODE EQUIVALENT ELECTRICAL CIRCUIT FIG. 1-12—The Power Integrated Circuit for Hifth Frequency Operation

1.4 TURN-OFF AND “GATE CONTROL” CHARACTERISTICS When the SCR is in its conducting state, each of the three junctions arc forward biased and the two base regions are saturated with charge. This situation is de¬ picted in Figure 1-13, for a device in equilibrium. To bring this device back into Lite blocking mode the carriers must be removed. This can be done in several ways. The obvious method is to open the circuit; how¬ ever, this generally proves impractical. Naturally, if lhe anode current is diverted I - to

J1

J2

J3

FIG. 1-13—Basic Thyristor In Conduction Equilibrium

or reduced below the holding current, the charge carriers will decrease through re¬ combination and the device proceeds to its blocking state. In AC circuits, this proc¬ ess is aided by the reversing line voltage; however, DC operation requires an artificial means of achieving this operation. Turn-off in DC circuits is accomplished by special commutation circuits that re¬ verse bias the device to bring about the desired commutation process. The reverse current sets up a diffusion of electrons and holes front Js towards Ji and J3. This action manifests itself as an external circuit current until the outer junctions are ready to support voltage. During this time the device voltage remains at about .7-.8 volts. When these junctions recover, the device assumes circuit voltage. However, recovery is not complete until the center junction recovers via a recombination of the holes and electrons at junction Js- This process is device dependent and inde¬ pendent of circuit action. Therefore the reverse bias must be maintained until this process is complete. When Js has been formed, the device is ready to block forward voltage. The voltage may then be reapplied in a manner consistent with the rating procedures. The time interval between forward current zero and the application of a positive blocking voltage is the turn-off lime and is in the order of 8-100 microsec¬ onds, depending on circuit conditions and the devices.

REFERENCES /, “GaUd Turn-On of Tour Layer Switch," R. I..I.ongini. IEEE Transactions, May, ltd3, pp ITS-IS5. 2. “An Introduction to Semiconductor Electronics." K, Nanavati, McGrow Hill, Hew York, 196.1. .?. “Transistors and Active Circuits." Linrill and Gibbons. AtcGraw Hill, New York, 1061. 4. “Breakdown Phenomena in Silicon Setnieonilnctni Devices" C. Perkins. Solid State Technology, February 1065.

2.0

DEVICE CONSTRUCTION AND PROCESSING

'Flic heart of the SCR Thyristor is the semiconductor element. All other materials and parts associated with the final device provide electrical and thermal access and protect the semiconductor element from its environment. The manufacture of a SCR Thyristor consists of several steps: 1. Silicon wafer preparation 2. Formation of several P-N junctions 3. Evaluation of the wafer after junction formation 4. Joining the wafer to a suitable substrate 5. Junction contouring and surface passivation 0. Encapsulation This chapter explains these steps. 2.1 SILICON WAFER PREPARATION 2.1.1 Crystal Cutting Cylindrical rods of silicon are cut perpendicular to the symmetry axis. Generally this axis is coincident with the crystallographic 1-1-1 axis. Abrasive cutting wheels, impregnated with diamond particles, are used for this purpose. Some manufacturers prefer to use small diameter wires or multiple steel bands tensioned in a heavy steel frame which is passed back and forth over the crystal rod. These methods are aimed at causing as little damage as possible at the crystal surface. Severe surface damage can cause preferential alloying or etching in subsequent processing. 2.1.2 Lapping To further reduce the surface damage and obtain exact thickness tolerances, the wafers are lapped. Planetary lapping machines which abrade both sides of the silicon wafer simultaneously are often used for this step. Figure 2.1 is an example of the equipment used to perform the lapping operation. The silicon wafers are located off center in the geared holders to keep the wafers moving continually. 2.2 FORMATION OF TIIE P-N JUNCTIONS Various Junction Formation Processes are in use. The most common processes are: 1. Alloy-diffused 2. All-diffused 3. Epitaxially grown junctions in combination with diffused junctions 4. Planar-diffuscd Each of these techniques result in acceptable SCR’s but some of these processes are better suited for specific types of SCR's. For example the planar-diffused process offers a number of advantages in the manufacture of inexpensive, low power SCR’s where high blocking voltages are not required. The all-diffused and the epitaxial-diffuscd constructions are often applied where high quality and reliability arc of major importance. The all-diffused process is most common because it offers good reproducibility and process precision. The alloy diffused construction offers ad¬ vantages on switching speed, but process control is more difficult. The all-diffused manufacturing process is as follows. First the N-type silicon wafer is etched and cleaned. The etching process further reduces any surface damage that may remain from the previous lapping procedure and simultaneously removes 2-1

Figure 2.1—A tapping Machine fur Silicon Wafers

metallic deposits left on the surface. Failure to remove these metal deposits can cause undesirable electrical characteristics in the completed SCR. Elements such as iron or copper easily diffuse into the crystal lattice and result in undesirable recombination centers which can cause an unwanted increase in the forward voltage drop. After the N-lype silicon wafers have been etched, rinsed, and carefully dried, the slices are loaded in holding fixtures which are usually made of quartz. Fixtures and slices are placed into a high temperature furnace. Two diffusion processes are commonly used. The closed or sealed tube diffusion process and the open tube process. Either process gives acceptable results. The choice largely depends on whether a gallium, aluminum, or boron diffusant is to be employed. Each of the diffusion processes offers distinct advantages and their selection depends on the type of SCR desired. The closed and open lube process is illustrated in Figure 2.2. Following the E-type diffusion, the silicon wafers are oxidized. A silicon oxide layer of several thousand angstroms is grown on the silicon surface. This layer acts as a barrier to the subsequent N-diffusion. The slices are then removed from the oxidation furnace, cooled, and covered with an organic, light-sensitive emulsion. A stencil or mask having the desired geometric pattern of opaque and transparent areas is placed over the silicon wafer and the photo sensitive emulsion is exposed to a strong ultraviolet light. In the exposed areas the photosensitive emulsion polymerizes. The unaltered or unpolymerized region is washed off. The polymerized emulsion is cured at elevated temperatures. Next, the silicon slices are subjected to an acid etch which removes the unpro¬ tected silicon oxide layer in the regions not covered by the polymerized organic emulsion. This is followed by stripping the remaining organic emulsion chemically. The silicon wafer is now readv for the second N-type diffusion which penetrates the silicon crystal lattice in the regions unprotected by the silicon oxide layer. Finally 2-2

(a) Closed Tube Diffusion

HOLDING FIXTURE

Wafers ready for diffusion using closed or sealed tube process. CARRIER GAS

Figure 2.2— Diffusion Processes the silicon oxide layer is removed and the I’-N junction formation process is com¬ plete. This sequence is* shown in Figure 2.11. After the silicon oxide is removed, the first “p" diffusion material is still shorting the p-n and n-p junctions. This shunt is removed chemically, or, by a junction con¬ touring procedure which excises the device junctions and completes the basic manufacturing process.

2.3 EVALUATION OF THE WAFER AFTER JUNCTION FORMATION 2.3.1 Determination of the Impurity Concentrations and Their Distri¬ bution in the Silicon Wafer Evaluation of the diffusion process can be determined by selecting a representative sample of silicon wafers from each diffusion run and testing them on the spreading resistance probe. The silicon wafers are angle lapped on a little jig to expose the various P-N junctions. (See Figure 2.4). The jig and silicon wafer are then placed on a microscope stage and two ball type probes measure the spreading resistance under the contact area. (See Figure 2.5).

2-3

P-TYPE l\\\

1. Diffuse P-Type into N-Type Silicon VvVJ

Wafer

2. Grow a Silicon Oxide Layer

~Si02 Laver

3. Coat with Light Sensitive Emulsion

-Photo Resist Emulsion

Light Rays

Photo Mask Consisting ol Opaque and Transparent Areas Light Sensitive Emulsion 4. Cover with Mask having Desired Geometric Pattern and Expose with Ultraviolet Light

5. Wash Off and Remove Unpolymerized Light Sensitive Emulsion and Cure Remaining Emulsion

2-4

P-TYPE

Figure 2.4—A Sample Wafer for Evaluation Via Spreading Resistance Techniques

Figure 2.5—Sample and Probe Configuration During a Spreading Resistance Resistivity Profile in the Thickness Direction of an Angle-I.appcd Silicon Wafer.

The wafer is then traversed under the probe contacts in small increments and the measured spreading resistance are plotted on an X-Y plotter as illustrated in Fig¬ ure 2.6. Spreading resistance measurements determine the impurity concentrations re¬ sulting from the diffusion process.

2-5

JUNCTION

Figure 2.6—Resistance Profile of a Junction Slice

2.3.2 Determination of Carrier Lifetime Impurity concentrations, junction depths and base width alone are not sufficient to characterize the diffused wafer. The lifetime of excess carriers is a parameter of major importance for the SCR, which operates at very high injection levels in flic forward conducting state. Westinghouse R&D has developed a technique to determine carrier lifetime over a wide range of injection levels from open circuit voltage decay measurements. The procedure is to prepare a P + N diode from a diffused wafer. Any undesired diffused layers must be removed by successive lapping until the proper diode structure is obtained. Contacts are made to the sample ultrasonically with a low temperature solder. The circuit for the OCVD measurements includes the diode under study, a forward-bias power supply and a fast transistor to rapidly switch the forward current pulse. The open circuit voltage decay is monitored by an oscillo¬ scope using axes of voltage and time. Figure 2.7 shows a typical OCVD trace. High injection level carrier lifetime can be approximated by the relationship,

q

* Av

Where K = BoItzman's Constant T =Temperature °K q = clectronic charge At/Av = time_(tieO volts t=carrier lifetime Given the carrier lifetime in addition to the impurity profile the diffused wafer can be fully characterized, since SCR parameters as turn-off time and forward drop can be predicted as well as voltages.

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Figure 2.7—Typical OCVD Trace

2.4 JOINING THE SILICON WAFER TO A METALLIC SUBSTRATE Because the silicon wafer is extremely fragile it is advisable to mctallurgically bond or contact the silicon slice to a mechanically sturdy substrate. The substrate should have a number of properties. 1. Match the thermal coefficient of expansion of silicon for Compression-l!ond-Encapsulation or hard-soldered constructions. This will minimize the stresses caused by temperature changes in operation. 2. The material should be a good electrical and thermal conductor, to minimize resistance losses. 3. It should be mechanically strong, to withstand handling, vibrations and mechanical shock. Molybdenum and tungsten meet these requirements. Brazing materials, like gold or aluminum, are used to mctallurgically join the substrate to the silicon wafer. Vacuum furnaces should be employed for the brazing process to prevent oxidation of the materials which interferes with proper alloying. A typical element is shown in Figure 2.8. ~NTvn SILICON - OIXUSE0 - PARENT til ICON N TrPl

? TYPE Sll ICON - 0l»«U5*0

ALUVIMIV EUTECTIC AlLO» »0"MS MlTALLUPGtCAL 30*»0 WITH THE •ADL'lQf NUU Si'UTRATE

f TV« SILICON - ft (GROWN

Figure 2.8—Basic Semiconductor Element After Junction Contouring

2-7

2.5 JUNCTION CONTOURING AND SURFACE PASSIVATION 2.5.1 Junction Contouring In Figure 2.3, Step 8, the oxide coating was shown removed. 1 lowever, inspection reveals that two junctions of the SCR are still shorted by the "P” layer of the first diffusion. Therefore, this material must be removed to expose I he I’-N-P-N structure. This is done either chemically or by lapping. Lapping is preferred in large area devices as the minimum of material is removed. This is done in a double step in which the shorting material is removed first and then a shallow angle is beveled as depicted via the dotted line in Figure 2.3-S. This allows the forward voltage stress to be distributed over a larger area and gives better voltage capabilities. For smaller devices where a number of SCR’s arc made on one wafer, the individual device is separated by scoring the silicon slice with a diamond scriber, followed by breaking the wafer along the scored lines. 2.5.2 Surface Passivation After the P-N junctions have been isolated the semiconductor element is etched tn remove any surface damage resulting from the contouring process as well as any metallic deposits. Metal deposits can cause a surface leakage current when voltage is applied across the P-N junctions. Finally, the etched silicon surface is covered with an insulating material to avoid contamination. 2.6 ENCAPSULATION OF THE SEMICONDUCTOR ELEMENT 2.6.1 Attaching the semiconductor element to a suitable bousing can be performed In a number of ways: a. ) Soldering with tin-lead alloys (soft solder) b. ) Hard solder construction

using gold-silicon and aluminum-silicon cutcctie

alloys c. ) Compression bonded encapsulation Each method has certain advantages. For small SCR's—used in consumer appli¬ cation-soldering the silicon wafer directly to a copper pad is used to make a minimum cost device. Since these devices do not require overload capabilities as do heavy commercial applications, this technique is satisfactory. 2.6.2 Hard Solder Construction As the semiconductor element increases in size, and the applications are for industrial installation, a more fatigue-free construction is desired. Because of differ¬ ences in the coefficient of expansion between the molybdenum substrate and the copper base, to which the semiconductor element is attached, the interface between molybdenum and copper is subjected to shear stresses. Specifically in applications where the devices must operate over a large temperature range repeatedly, the life expectancy of soft soldered thyristors is severely limited. Evidence shows this limitation is due to fatigue rupture of soft solder joints when they are subjected to cyclic thermal stress. (Ref: W. B. Green's paper “A Fatigue-Free Silicon Device Structure”, Communications and Electronics Vol 80, pp 170-101, May 1901). Among the early silicon rectifier cell applications, a number of installations were encountered where unusually high failure rates were recorded. A common feature of these installations was that there were present a large number of "off-on” operations each day. To further evaluate this type of failure, a carefully controlled experiment was performed that applied power to the device to cycle the junction over various ranges of temperature. The maximum AT cycled tile device between its maximum 2-8

rated junction temperature and ambient temperature. A 35% duty cycle was used with ten minutes as the total time for one complete cycle.

NUMBER OF CYCLES TO FAILURE

Figaro 2.9—Curve of Junction Temperature Versus Number of OFF-ON Cycles to Fracture %" Junction Assembly Using this cycle and by varying the circuit current to obtain various AT incre¬ ments. the curve of Figure 2.9 was obtained showing the number of “on-off" cycles to solder fracture for 5^-inch junction cells. Simply stated, this data says that the greater the temperature above ambient to which the junction rises, the fewer times it may lie turned on and off before failure. Data collected on several size junctions over a range of junction temperatures may be summarized in the relation: ND*(AT)«=CS where N is the number of cycles to failure; D, the junction diameter in inches; AT, the change in junction

temperature; and C, a constant of about 3500. The

lower temperature portion of the curve shown by dashed lines in Figure 2.9 is added because germanium units cycled to this temperature apparently show little or no such deterioration. It is of course unreasonable to derate the silicon junction temper¬ ature to SO degrees, for then its principle advantage would be lost. Thus, one may assume that a germanium device, when conservatively rated and correctly applied, will have practically indefinite life; however, to take advantage of its inherently higher junction temperature capability, a silicon device with soft-soldered construc¬ tion, properly rated and applied, has an operating lifetime determined by cyclic conditions. All of the Westinghouse SCR’s manufactured for industrial applications employ a fatigue free construction such as hard solder or (1UE. 2-9

2.6.3 Compression Bonded Encapsulation Technique In keeping with the fatigue-free construction philosophy outlined previously, the CBE technique was developed in conjunction with a recently designed "Pow-R-Disc" SCR. The basic feature of the technique is the elimination of the solder joint by the use of force to maintain the electrical and thermal contact between the SCR semiconductor clement and the encapsulation base. The concept is not new. It has been widely accepted as good engineering practice in a variety of applications in the electrical industry—from simple wall switches in the home to high-power industrial switchgear apparatus. Moreover, it is well established in the semiconductor industry, viz., in the application of installing a semiconductor device on a heat sink. In the latter example the threaded stud of the encapsulation base, a nut and a spring force washer are used for mounting the device, The reliability and durability experience of such an assembly—usually in an uncontrolled atmosphere—can be obtained from any user of semiconductor devices. Thus, it is immediately obvious that the same principle is applicable within a semiconductor device assembly, particularly since a very carefully controlled atmosphere is maintained inside the device. Figure 2.10 illustrates the structure of a typical SCR which utilizes the CBE concept.

Figure 2.10—Cutaway View of a CUR Package Illustrating Internal Construction

Before using fatigue-free construction in an actual device, a number of experi¬ ments were conducted to establish its reliability and durability. Some were basic

2- it)

material measurements; others were directly related to the SCR structure. Results are briefly outlined in the following. The compressive strength of single-crystal silicon. (1-1-1) orientation, was tested. Results indicate a value in excess of -10,000 psi. It was next determined through tensile tests that the encapsulation base assembly could easily withstand pressures several times that normally used in encapsulation of the actual devices. These tests served to prove the reliability and durability of the brazed and welded joints. The final area of study was that of mating surfaces between the SCR semi¬ conductor element and its encapsulation. It was determined that pressures as low as 60% of the standard assembly pressure continue to provide good operating char¬ acteristics whereas a pressure of twice that of the assembly did not generate a significant improvement in contact resistance. The loading force used in "CBE” construction is accomplished by Belleville spring washers. Optimum loading of the Belleville spring washer is accomplished when it has been deflected from 70% to S0% of its "free” cone height. Figure 2.11, illustrates a typical load deflection curve for a Belleville spring. It is noted that the optimum load range has been selected so changes in deflection of the spring, typical of thermal expansions by the package, result in minor changes in component loading. These minor changes in component loading are well within the desired component loatl range of the device package to insure optimum electrical and thermal transfer from the “basic semiconductor element" to the mechanical assembly.

Figure 2.11—Load-Deflection Characteristics of Constant-Load Disc Spring

Finally, the construction of the mating copper pieces have been thoroughly inves¬ tigated. Westinghouse semiconductors for industrial use are made of a special highstrength copper which does not anneal at high temperatures. Thus, the base thick¬ ness has been optimized for thermal heat transfer as well as minimum deflections resulting from the compressive loading force. Consequently, the major questions concerning the effectiveness of the CBE technique have been experimentally evalu¬ ated. The successful results prove the basic concept to be sound in principle and practice.

2.7 MECHANICAL DESIGNS FOR DEVICE ENCAPSULATION 2.7.1 Stud Mounted This mechanical design has the advantage of versatility and ease of application to a variety of different heat sinks. However, it has the highest thermal impedance due to the small thermal contact area and the remoteness of the semiconductor element from the heat sink. Surge current ratings are nearly ns high as for other packages, but continuous ratings arc usually less for the same size semiconductor element. Stud-mounted types should not be used where front access is necessary. For example, on a large heat sink onto which a number of different components are mounted, access to the nut in the back of the heat sink may be difficult. See Figure 2.12

MOUNTED THYRISTOR

Figure 2.12—Stud anil Flat Base SCR Mounting Techniques

2.7.2 Flat Base Construction The case style is very similar to the stud-mounted device, but the large area base is advantageous for mounting to certain types of beat sinks, especially the watercooled beat sinks. In addition, the bolt holes in the mounting base affords mounting to large plates and extrusions without the rear access. As indicated previously the llat base construction is ideally suited for front access mounting. 2.7.3 The Integral Heat Sink SCR Thyristor This construction provides the most efficient, design for high velocity forced air How cooling. External thermal contact resistances have been eliminated and the en¬ capsulation and heat sink have been combined into an optimized package with maxi¬ mum performance for the given cooling conditions. I bis package was developed for heavy industrial systems which are used for controlling the speed of motors with dynamic load demands. Because these designs are optimized for specific cooling con¬ ditions a certain amount of versatility is lost. See Figure 2.13. Integral heat sinks are designed for front or rear access mounting. The fin design includes a set of air flow “spoilers” which direct the air flow toward the heavy round copper base and generate a certain amount of turbulence to break up the stagnant air films, thereby improving cooling efficiency. As a consequence the thermal impe¬ dance of these device are optimum for single sided cooling. 2.7.4 The Disc Construction for Double Sided Cooling This package offers the advantage of a very versatile construction and the possi¬ bilities of increased ratings by double sided cooling. A number of devices can be easily "stacked", for series-connected SCR's or the connected in parallel via back-lo-

2-12

Figure 2.13—Integral Beat Sink Thyrlator

back arrangement shown in Figure 2.14. An application problem arises in dirty envi¬ ronments for this design. Because of its design the creepage path of the insulator in the package is usually shorter than what can be obtained with the stud-mounted construction. If the creepage path is made longer, the copper contact pieces usually become extended and the thermal impedance increases. Recent designs employ con¬ volutions in the ceramic insulator to increase the creepage path. This results in an increase of the package diameter and takes up more space.

Ill HACK TO BACK APPLICATION

OISC PACKAGES STACKEO IN AN APPLICATION OF SERIES CONNECTED THYRISTOR

Figure 2.14—Pow-R-Dtac Mounting

If a customer wishes to do his own heat sinking, greater know-how is required than for other device encapsulations. Not only is it important that the sink surfaces mating with the device be Hat and smooth to reduce thermal contact resistances as with conventional packages, but the loading forces must be applied at the geometric center to assure a uniform distribution of the contact pressure. A clamp for fas¬ tening the Pow-k-Disc to the heat sink developed by Westinghouse has become an industry standard. See Figure 2.15. 1 n summary, the disc encapsulation of thyristors has been one of the most versatile package innovations developed recently.

2- 13

Heat Sink POW-R DISC

Exaggerated Sketch Showing Direct Clamping Causes Bending ol Heat Sink Exaggerated Sketch Showing Non-Parallelism of Heat Sink Without Swivel Contact, Even a Slight Swivel Contact

Difference in the Tightening of the Bolts Causes Uneven Pressure on POW-R-DISC Device and an Excessive "Air Gap" Between Device and Heat Sink. This in Turn Causos Poor Thermal Contact and Excessive Device Heating.

POW-R-DISC Heat Sink

Exaggerated Sketch Showing That Although Clamp is Misaligned The Sink Is Held Parallel To POW-R-DISC Thus Assuring Even Pressure On Contact Area Between Sink And POW-R-DISC

.1?) I 4-20 Soc. HD Cap Screw -131 Spring Cadmium Plated 4) Heat Sink ITop)

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erattire whereas many applications may dictate utilizing the sink temperature and parameters. If we now impose a step power input to this network, the junction temperature will rise in an exponential fashion as prescribed by the network parameters. Should this power pulse last long enough we would, of course, go to steady state and con¬ ventional calculations would prevail. However, if the power pulse is interrupted before that, the junction cools anti a waveform as shown in Figure 4-9 results. The definition of the transient thermal impedance is depicted from Figure 4-9. The AT 4-6

4-7

experienced is divided by the power pulse and a point for a transient thermal im¬ pedance curve is generated. The total plot is obtained by monitoring the junction temperatures at the end of well defined power pulses. Using these procedures and the thermal impedance rating techniques, an accurate curve, such as Figure 1-10, is generated. This curve represents the highest value of thermal impedance of any device of this type. Therefore the designer may use this curve with confidence. An additional design advantage is a rating guard band that is built into the rating to account for variances in repetitive pulse loads.

FIG. 4-10—Transient Thermal Impedance vs Time

For those persons utilizing the device at very short times, i.e., a few microseconds, this presentation is not valid. The curve is predicated on the entire cathode surface being in conduction. However, at short times, as in inverters, high di/dt, pulse dis¬ charges, modulators, etc. this is not llte case. For these and similar applications a small pari of the cathode is actually used and additional factors must be considered in the rating of the device for good life time in the application. As an example, let us first look at a typical SCR construction in Figure 4-11. If only a very minimum gate signal is applied, only the point on the cathode I.D. with the highest gain will be switched on. The conduction will then spread across the entire cathode area at a relatively slow rate of approximately 1 cm per lOOgsec. The peak power during switching normally occurs within one microsecond of the start of conduction and at this time il is obvious that the dissipation is still concentrated in the region where conduction was initiated. This extremely high power density is the reason that hot¬ spot temperatures may be extremely high. On the other hand if the gale current is in the order of ten or more times the minimum required, the entire circumference of I he cathode I.D. may be switched on. The rise time of the gate current must be very short to get the entire ring into conduction at approximately the same time. The area in conduction under high gate drive may be many times the area in con¬ duction at low gate drive and one microsecond after the start of conduction. High gate drive will, therefore, increase the switching capability substantially due to the Westinghouse patented center fired construction.

4-8

A

FIG. 4-11—Typical Wcsllnfthouse SCR Construction

4.5.3 Thermal Impedance Calculations for Irregular Current Waveforms In many applications a very accurate knowledge of the behavior of the junction temperature is not required. A conservative approximation is that if the junction temperature is below a fixed limit it is usually adequate. A very handy worst case approximation is to replace an irregularly shaped power pulse by a square wave power pulse with the same peak and the same peak to average ratio as the irregular pulse. In certain cases this will give much higher temperatures than the more exact solutions, and for this reason the more tedious methods should be attempted if the worst case approximation gave a temperature only slightly too high. The reason for this higher temperature is that the square wave concentrates a higher heating power pulse into a shorter time with the net effect of less cooling during the pulse. To utilize this rating the arbitrary waveform under question must be simulated by an equivalent square wave or pulse train. A typical example of this is shown in Figures 4-12 and 4-13. Steady state operation of thyristors often requires a train of power pulses of various geometry. The exact solution to eacli problem requires the summary of very many numbers to bring the device to an equilibrium condition wherein the temperature rise on eacli cycle is stabilized. A number of these problems have been solved in other applications. The solutions are shown in Figure 4-14. For other waveforms a similar technique must be utilized.

4.6 ADDITIONAL CURRENT RATINGS FOR THE THYRISTOR The discussion covered in this section deals with those special current ratings arising from special considerations for temperature, partial utilization of device area and high current density operation. These ratings arise in many power circuits requiring clearing of fuses, opening of circuit breakers, fault currents or high device dissipation clue to high frequency inverter applications. Some of tlie ratings discussed in this section will be non-recurrent in nature. These ratings are the result of special applications that cause the junction temper¬ ature to rise above the maximum rating. Therefore blocking capability may be lost while repeated overtemperature cycles shorten the device life. Therefore these cycles are limited in the number of occurrences by standard ratings.

4-9

POWER

POWER

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TIME—►

(a)

(b)

X WATTS

! + X WATTS

-X WATTS ONE PULSE: IS IDENTICAL TO THE SUM OF TWO STEPS

(c)

(d)

FIG. 4-12—Example of Transforming An Arbitrary Wave Into a Series of Steps

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TIME —FIG. 4-13—A More Detailed Drawing Showing the Super Position of Waveforms in Figure 4-9(a), (b) and (c)

4-10

Load Condition

Waveform ol Power Loss at Junction

po

Solution tor Junction Temperature 9 ~ Steady-Stale Thermal Resistance 0 (■ ■ 1 " Transient Thermal Impedance at Time l| 9 Itj-nl - Transient Thermal Impedance at Time (t2 - If). Etc.

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Waveform of Junction Temperature Rise ITa * Reference Temp. 1

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ig

FIG. 4-14—Junction Temperature Calculations Using Transient Thermal Impedance

4.6.1 RMS Current The RMS current rating is always used in the rating procedure for a device but is often overlooked by the user. The reason is that the circuit designer is more.fre¬ quently looking for the average current that must be delivered to the load. There¬ fore the rating presentation takes this into account and presents device capability in terms of average current. However, the different form factors associated with the RMS/AVE waveforms in controlled rectifiers causes the RMS value to exceed the AVE value considerably (sec Figure 12-23). Therefore, as the conduction angle de¬ creases, the RMS current, for a trail average current, increases. This RMS current flows through the resistive portion of the lead assembly, device wiring and the inter¬ nal assembly parts so that temperatures are continually increasing. At a fixed value of RMS current the temperature of these parts begin to contribute heal to the de¬ vice instead of carrying heat away. At this point the RMS value of the device is fixed and the average current curves are cut off. If we refer to Figure 4-5 these points of constant RMS current are noted by the break points in the case temperature vs average current plot for various conduction angles. It should be noted in passing that the curves such as 4.5 are generated by selecting the worst combination of lead assembly, forward drop and thermal impedance. In addition, a unity power factor load is used in calculating the break points. For inductive waveforms and the usual cases wherein the load is slightly inductive, the form factor is lower. Therefore the user has a conservative rating.

4.6.2 IJt Rating The I2t term describes the short time-thermal capacity of the fusion and is helpful in selecting a fuse or providing a co-ordinated protection scheme for the equipment, During overloads, line faults anti short circuits, the device must survive under con¬ ditions which give rise to junction temperatures exceeding 125°C. Since the ratings are based on 125°C it is obvious that any fault will cause overtemperatures. 4- II

This rating is intended specifically for operation less than one half cycle. During this interval the device is resistive with a fixed thermal capacity and negligible power handling capacity. Therefore the designer should set his fusing or overcurrent protection so that this value is not exceeded. The I value of the term is the RMS value of the fault current and t is the time in seconds. To utilize this value, care should be taken so that switching ratings are not exceeded when turning on into a fault. In addition, forward blocking capability cannot be guaranteed at values near the maximum Ft.

4.6.3 Surge Current Rating IFM The surge current rating defines a particular capability that is used in case of fault conditions in equipment. As in the case of the Ft rating, the junction temper¬ ature of the device exceeds max. rating during this operation, therefore the leakage currents, blocking capability etc. are severely affected. For these reasons the device is guaranteed for a maximum of 100 cycles. This rating is based on peak current values and 1.80 degree conduction periods. It is frequently given in tabular and graphical form and is based on the ability of the device to support rated PRV at elevated junction temperatures. However, the high leakage currents at the elevated temperatures severely reduce forward block¬ ing capability. Therefore the device may immediately conduct with reapplieation of forward bias until the load is reduced or interrupted.

4.7 DYNAMIC CHARACTERISTICS In certain designs, the dynamic properties of the device become important. This section covers the parameters and details thal are important in these instances.

4.7.1 di/dt or the Rate of Rise of Anode Current There arc a variety of applications wherein the anode current is derived from a stiff current source. This gives rise to high dissipation due to excessive current density which exists in the small part of the cathode area that, is in conduction. This condition arises in inverter service, crowbar and capacitor discharge systems or more common—low impedence R-C dv/dt networks. The value of di/dt that a device can accommodate safely must be measured independently so that contributing factors do not alter the test value. In addition the test data must be conducted for a period that is long enough to insure that deg¬ radation of a key parameter is not happening. Therefore the test data is taken in a circuit, as described in Figure 4-15, for 10s cycles. Shorter lest times are used in the industry but are invalid for long time use. The circuit in Figure 4-15 uses a steep rising waveform during the first u-secoild. It has been found that this time-current relationship generates local hot spots as high current densities result in the cathode. The combination of high switching voltages and high current densities gives this “worst” case test method. The circuit is designed for a "damped" response so that voltage reversal losses do not occur. This then allows the manufacturer to segregate the effects of this con¬ dition and relate it to associated application procedures.

4.7.2 Dynamic Turn-On Voltage In inverter service, crowbar applications and related applications, the switchingloss during turn-on is related to the time required to reach the low impedance “on state”. This procedure is a method to indicate the greatest amount of cathode area in conduction at a predetermined time. This indicates better switching devices, high di/dt capability and definite "voltage clamping” properties. 4-12

I»l>& Temp

GO pi>5 125° C

Vfu

Rated

Duroiion

108 Cycles

Gate Current

3.3 Igt *

3.3 igt ♦

‘rise MCecv

FIG. 5-1—Test Circuit for Forward and Reverse Blocking Characteristics

5.2.2

Peak On-State Voltage

(JEDEC Standard 0.202.1.3)

Figure 5-3 shows a typical circuit for measuring peak on-state voltage. This test determines the power dissipation of a given thyristor. Because of the high power dissipation in this test, a low repetition rate (1-3 pulses per second) should be used. A typical display of voltage-current characteristics is shown in Figure 5-4. The high initial voltage appearing on the display is caused by the turn-on characteristics

5-

/ - »D\

FIG. 5-3—Test Circuit for On-State Voltage

of the device and is a function of the applied gate drive. For tin's reason, on-state voltage should not be measured until the device is fully turned on. 5.2.3 DC Gate Characteristics (JEDEC Standard 0.201.1.8) DC gate testing determines the gate voltage and current required to reduce the device blocking capability below a specified value. Supply * 1 in Figure 5-5 is ad¬ justed lo a predetermined value, normally 12 volts. Supply #2, initially at zero voltage, is gradually increased until meter Mi indicates a decrease in anode voltage. The gate current and voltage arc read on meters M- and Ma respectively. 5.2.4

Holding and Latching Current

(JEDEC Standards 0.201.1.6, 6.201.1.7)

1 lolding current is defined as the minimum current that can flow through a device without the device reverting to the off state. Initially, the device is turned on to a current level of sufficient magnitude to turn the device completely on. The gate drive is then removed and the anode current is gradually reduced. The current flowing through the device immediately prior to turn off is defined as the holding current. This test may be performed on the circuit shown in Figure 5-6. Switches

5-2

SW1-SW4 are closed and the minimum resistance is selected in the anode circuit. Switches SWa and S\Y6 arc closed, then SW6 is opened. The anode resistance is gradually increased and the current is read on M,. The value of current on the meter immediately before the current goes to zero is the holding current. Latching current is defined as the minimum anode current required to turn the device on and beep it on after removal of gate signal. The circuit in Figure 5-6 can also be used to perform this test. Initially switches SW2-SW4 are open anti SWT is closed with maximum resistance set on Ri. Switches SW’5 and SW'6 are closed, causing a gate pulse lo be applied repeatedly on the device. As the anode resistance is gradually lowered, meter Mi will show a very low current value. When the de¬ vice has enough anode current to remain on between gate pulses, the current level indicated on the meter will rise rapidly to the latching current of the test device. 5.3 DYNAMIC TESTS 5.3.1 Rate of Rise of Forward Voltage, DV/DT (JKDKC Standard 6.205) The SCR is sensitive to fast rising forward voltage which causes current to flow through the gale-cathode junction. This current becomes an artificial gale drive and may force the device into the on state. The faster the rate of rise the more likely the device will turn on below its rated voltage. Thyristors may he rated as being capable of supporting a linear dv/dt or an ex¬ ponential one (as defined in Figure 5-7) without switching to the on state. The test circuit shown in Figure 5-8 is capable of testing either of these conditions. Depressing the “test" button introduces a series of pulses on the device under test. Should the device break over during test, resistor R limits the current, thus protecting the device, The rate of rise is adjustable, as shown in Figure 5-8. CRITICAL RATE OF RISE ■= TEST VOLTAGE X .632

FIG. 5-7—Exponential Dv/Dt Definition

110:110

SCR3 at t3

FIG. 5-10—Simplified Turn-Off Circuit anil Firing Sequence

A simplified circuit diagram and firing sequence is shown in Figure 5-10. At time ti the test device, SCR|, is fired, causing a forward current to he applied to the lest device. After approximately 50 microseconds (t2) SCR... is fifed, causing a reverse current to be applied to the test device. Variation of \\ will change the peak reverse current applied to the device and I., will change the rale. At an adjustable interval after firing SCR;, SCImeac

(b) Resistor Phase Control

(al Static Switch

FIG. 6-14—Resistor Gate Circuitry

6- 13

The problem associated with the preceding circuits lies in their inability to utilize the device control capability over the full range. In the static switch the de¬ vice continually repeats its trigger point. In the second instance, delay is achieved, but never beyond the 90° point. If the device has not triggered here then the IG is too low and will decrease again after the 90° point. To achieve further delay an in¬ tegrating effect must be used to delay the IGt conduction point past 90°. The basic circuit to do this is shown in Figure 0-15. In this circuit the R-C values should be set so that thecharging current is high compared to IGT and that the R value at max. delay will still produce IGT. For larger devices, the R-C components will get: relatively large in size, so a trigger device and smaller R-C values may be more economical.

FIG. 6-15—Phase Delay Gate Circuit Using R-C Delay and Anode Voltage

The use of anode voltage to trigger a thyristor into conduction causes problems with the variation in input voltage. For different supply voltages the triggering point and range of control are variable. To alleviate this, a standard R-C circuit can be designed to fit all the voltage ranges by using a circuit similar to that shown in Figure 6-16. In this circuit the gate is connected to the wiper of a variable resistor in an R-C network, which is connected across the secondary of a transformer. Using this circuit the gate control is variable from approximately 0° to > 180°.

FIG. 6-16—Phase Delay Gate Circuit for Vnrinhlc Application Uses

6.4.2 Saturable Reactor Control Saturable reactors and magnetic amplifiers form a basic control function in power control circuits. The basic feature of these devices is to control the flow of power by 6- 14

varying the impedance of an inductive component. In this fashion they are similar to thyristors. The operation of a magnetic amplifier is easily explained by referring to Figure 0-17 which shows the B-H curve of a magnetic amplifier core. If we assume for discussion, that we are at the point A on the curve and that the core is energized in the positive direction, the flux in the core is increased along the path A-B-C due to magnetizing current. At C, the core is saturated and will not support additional flux so that point I) is quickly reached,whereupon current is limited by the external circuit. If the sig¬ nal is now removed, we reverse the trace DEF due to a reset bias in the winding. Using this procedure a control of timing pulses may be accomplished by varying the magnetic bias in the core as in Figure 6-18.

The properties of the core may be utilized by arranging the bias and energizing sources to achieve delay and control of a timing pulse. A typical half wave self saturating magnetic amplifier is illustrated in Figure 6-19. In this circuit WDl! #1 establishes the bias level in the core and resets the core during the negative half cycle. WDg #2 performs the actual switching function for the amplifier and drives the thyristor gate. An additional winding (#3) is included to show the versatility of these devices in the control mode. A number of sense windings may sample circuit parameters, at various potential levels, and change the control set point. In this fashion feedback levels may be summed using this versatile tool. An additional note on this circuit is shown by resistors R] and Ra. The resistors serve as a path for magnetizing current so that VGNT is not generated, and also to limit current flow once Ti is saturated. A second solution to this problem is to couple the gales with a pulse transformer whose magnetizing current exceeds the leakage current of the saturable or magnetic reactor so that only the sharp firing pulse is transferred to the gate. In the preceding section the control function was performed by the current from a regulated DC Source. Using this system, voltage fluctuations in the line may cause a shift in the control point. A second connection to alleviate this is to use VVDg S3 as the control source and feed it with an AC signal as shown in Figure 6-20. In this fashion the AC input resets the core on the control cycle. Therefore, as the line volt6-15

(c) The Magnetic Path FIG. 6-18—Circuit Operations for a Saturable Reactor with Magnetic Reset

age (lips, l lie reset point on the H-l-I curve of Figure 0-17 conies back to A1 instead of A. Then during the conduction cycle the lower voltage requires less volt-seconds to saturate the core T-l. In this fashion the magnetic amplifier tends to minimize the firing point drift by a built-in feedback process. During voltage rise a similar situation exists with the bias going to A". When a saturable reactor or magnetic amplifier is used to control a thyristor, the designer should account for certain magnetic characteristics in system perform¬ ance. The system functions and control characteristic are somewhat dependent on these parameters and should not be overlooked. 6-16

V

FIG. 6-19—Half Wave Self Saturating Magnetic Amplifier for Triggering Thyristors

AC Input

FIG. 6-20—Half Wave Self Saturating Magnetic Amplifier with Reset Control

a. On To Off Ratio

As negative current is supplied to\VDg. # 1 of Figure 6-19,

the magnetic amplifier is turned off. However, if the negative current is not lim¬ ited, the output of the magnetic amplifier will increase again and cause false firing. Therefore the reset control must lie limited. 1). Signal Rise Time—In high di/di applications, saturable reactors and certain magnetic amplifiers will exhibit long pulse rise times. To alleviate this, one of the shaping circuits on Figure 6-21 should be used. C.

Snap-On—The degree of filtering in the bias circuit affects linearity, sensi¬ tivity and "snap-on". The device may be turned off smoothly but as it is turned on from full off the magnetic amplifier may snap on from 10 to 70 per¬ cent of full output. 6-17

d. Load Balance—In full wave or polyphase applications the imbalance in the firing point of the magnetic amplifier can cause a DC component in the load. In the case of a power transformer, excessive excitation and thyristor overcurrent results. Therefore the linearity of the firing pulses and tracking should be checked, e. Response Time—If the magnetic amplifier is used to current limit, the circuit designer should carefully consider the amplifiers response time. A single core half wave design inherently has a one cycle response time. That is, on sensing overcurrent it waits till the next cycle to reset the firing point. In the full wave circuit, the coupling between cores opposes the change being fed to it. As a result, each core changes a small amount in its reset cycle, Therefore step changes in the feedback circuit do not occur as fast in the load circuit.

C - to supply initial gata energy only Ideal

Min.

Cap Value

C'

Cap Value

3.3 lGT

lGT

dv/dt

dv/dt

(a) Speed-Up Capacitor

r'mirr*»*frrr »n rnvn

n

ut

"

*

2

s g

s

§

8 §

§

*

Frequency of Oicillnllon • f • Cyclei per Socond

K «

*

I

U

a

f

I I I

inn

O

vn

i |"'i| '' ' i trrr i p-p i"Tri' r 111 i i i rT' Ii rr-r | n r r fr, r| V

(1

fN

—

r-

o'

Cw)«clunc«t ■ C,

~

8

S 5 8

8

Mrcrotnijidl

FIG. 6-25—Nomogram for Determining the Period of UJT Oscillator

(i -• .6.1)

6.4.5 Shockley Breakdown Diode Relaxation Oscillators The Shockley diode is a two terminal, four layer, unilateral thyristor device that switches rapidly from the blocking to the conducting state. Its characteristics are listed in Section 3.2.3 and it performs a function similar to the UJT. However, the turn-on waveforms experienced with a Shockley diode arc markedly improved. The turn-on or switching time for a Shockley diode is a function of device and circuit parameters. The device limitations are based on the storage time of the base layers and the rate at which this charge is stored. Therefore, if the gate circuit is of low value and resistive, the device turn on time and current rise time can he as low as 100 n sec. For this reason the Shockley diode makes an excellent trigger source for SCR's under heavy loading. In addition, the relatively low impedance of the device in the on stale does not affect the current shape. A typical trigger circuit is shown in Figure 0-28. This family of devices may be used as voltage discriminators, pulse shaping service or to filter noise from the gate of the thyristor. In addition to their turn on capability, these devices can be used to supply sustaining current to the thyristor as they have an average current capability that the UJT emitter doesn’t possess. However in AC service this device should be protected in the reverse direction as it avalanches at voltage levels below the forward switching voltage. In addition, a reset is suggested on the timing capacitor to assure that the charge is completely removed with SCR conduction. If this is not done, the residual bias may introduce a low frequency oscillation into the gating control circuit. An example to prevent these oscillations is illustrated in Figure 6-29. In this circuit the reset diode assures

6-21

MINIMUM SUPPLY VOLTAGE TO TRIGGER SCR vi

CAPACITANCE

Curve

Rbi

A B

47S) 75 U Pulse Eng PE 2231 F 47S1 75! 1

c 0 E

0.01

0.1

1.0

F

Sprague 312204 1

E

•tzn

F

75S1

G

Sprague 31Z204 1

SCR Type @ 25°C

IGT UP ,0 200 ma VQT up lo 3.5 v

•GT up to 150 ma Vqt up to 3 v

Iqt up to 50 ma"j

i

J

2N4361. 2N4371 @ Type 260,

?61 2N681. 2N1842 ® Types 250, 251, 240 241 205, 210’ 2N1770, ?N1R?q @ Type 201

Vqt up to 3 v

t or equivalent

10

C^ • Capacitance - p t

FIG. 6-26—U.IT Trigger Circuits for Typical Gate Firing of Thyristors at 25°C

that capacitor C, is reset by bleeding off the charge through the thyristor as it conducts. An additional control feature of this circuit is that a feedback signal may be introduced to vary the firing point, and control load dominated fluctuations. For these control features an additional diode is inserted in the gate circuit to protect the thyristor gate from excessive reverse bias.

6.4.(i Blocking Oscillator Gate Drive In achieving fast rising gate signals for SCR's In high di/dt service at various potentials, a blocking oscillator may be a useful tool. Blocking oscillators may be used in conjunction with slowly rising voltages that call for SCK triggering. The cir¬ cuit action then generates a sharp rising gate pulse to fire the SCR. Two types of blocking oscillators may be used. The monostable circuit supplies a current pulse for a prescribed input signal while (lie astabledesign generates a train of pulses unless it is inhibited or clamped. The successful application of a blocking oscillator trigger is related to the load current and the pulse train or pulse that is to be supplied. In Figure 0-30 the rela¬ tionship of gate signal for various load di/dt's is compared. In this plot the device delay time is plotted as a constant for ease of discussion; however, as per Section 6.3.3, this is a variable. In referring to Figure 0-30 it can lie seen that the blocking oscillator 6-22

PW

C(fif)

‘Approximate Pulse Width (psi

.47 1.0 1.5 2.0

20 50 70 100

Ra= ih/vbb

A Multi Pulse UJT Generator with Ramp and Pedestal Control

FIG. 6-27—UJT Trigger Circuits with Improved Output Signals

ITT

® 250H

Note: BD1

111 w/o Feedback 4E20-8 IITTI (21 with Feedback 4E40-8 IITTI

FIG. 6-29—Shockley Diode Control with Timing Capacitor Reset

pulse train A is insufficient to trigger the device. In a similar fashion pulse train B will not fire the device properly for Load Line C. This is because the gate signal is extinguished prior to the device reaching the latching level for load C. The last pulse train (pulse train C) is sufficiently wide to successfully trigger loatl lines A, B and C. A second related design problem for blocking oscillators (and all pulse train firing) is the off space between gate pulses. If the load current slope is erratic or slightly oscillatory, the thyristor may extinguish itself. For this reason the designer is cau¬ tioned to assure that all snubber circuits or related circuit reactances do not form an oscillatory circuit. The design of the blocking oscillator rise time, pulse width, duty cycle, etc. are related to the application needs. A wide variety of blocking oscillator transformer designs are available. Two typical designs for this type gating circuit are shown in Figure 6-31.

6-24

FIG. 6-30—Blocking Oscillator Goto Pulse Width for Various Load dl/dt's

6.4.7 Hard Firing Gate Circuitry la applications requiring high di/dt, minimum delay time and maximum system performance, high gate drive circuitry is used. The details of high gate drive are given in Figure 6-11. They outline the requirements for the leading edge of the gate pulse and the width of the sustaining current region. A number of circuits are avail¬ able to generate these waveforms. Two examples are given in Figures 6-32 and 6-33. In Figure 6-32, diode D2 charges capacitor Ci to the peak of the AC wavefront. When the line goes through zero, the two capacitors redistribute the voltage so Ca has lhe peak supply voltage. When the pilot thyristor is fired, a low impedance path (i.e. Cs, Rs and thyristor gate) is available and a sharp current spike is available. Then as Ca is discharged, capacitor Ci reverses its charge through the transformer leakage reactance, gate and circuit resistance. Using this circuit, the desired leading edge of the high drive pulse is generated and the sustaining portion insures sufficient gate drive during the conduction interval. The schematic of Figure 6-33 uses a direct amplification to achieve gate drive as per Figure 6-11. The problem with transistor circuitry for high drive is the change in collector and gate current required and the transformer problem of sup¬ plying sufficient volt second capability in a core to carry this signal. The problem is neatly solved in this circuit by driving the transformer as a current transformer and changing collector and gate drive by various primary collector impedances. In this fashion the transistor base drive is kept constant and the R-C circuit generates the sharp leading edge. Then, when the capacitor is fully charged, the 100 ohm resistor takes over to supply the needed sustaining current.

6-25

Ramp

mm

(a) MonoiUble Blocking Oicillalo* jbl Clampnd Aitablo Blocking Oicillatoi

FIG. 6-SI—Typical mocking Oscillator Designs

FIG. 6-32—A lligli Drive Firing Module Using a Thyristor Trigger

6 - 26

+ 30VDC

FIG, j.jj_\ nigh Drive Firing Module Using a Transistor Amplifier References: I. E. Bauman, "Neon Lamp Triggering oj SCR's in Proportional Power Control Applications", Signalise A ppl. News, Vol. Z, No. A. Z, T. Bergensen, "Theory and Characteristics of the Unijunction Transistor", AN-Z93, Motorola Semiconductor Products. 3. Linville if Gibbons, "Transistors and Active Elements", McGrow Hitt, New York, IVM. 4. ITT Semiconductors, Inc., "Four-Layer Diode Multivibrator Circuits", Bulletin E-506. 5. McGregor, “UJT's Regulate Battery Charge", ED It, Nov.S, 1907. 0. Millman if Taub, "Pulse, Digital and Switching Waveforms", McGraw Hill, New York, 1965. 7. Namoali, "An Introduction to Semiconductor Electronics", McGraw Hilt, New York, 1963. X. Schwartz, "A Handbook of Selected Semiconductor Circuits", Bureau of Ship's, Dept, of the Navy, Publ. AM VSIIIPS 934S4. V. Strauss, "Wave Generation and Shaping", McGraw Hill, New York, 1960. 10. Transistor Manual, 7tli Edition, General Electric Company, Syracuse, N. V. 11. Transistor Manual, RCA Corporation, Harrisiou, N. J. 1Z, Vincent, "Transistors Replace Four-Layer Devices", EDN, May 15, 1969. 13. Wechsler if Hinder, "Triggers for Thyristors". 14. Hinder, " Unijunction Trigger Circuits for Gated Thyristors", A N-4J3, Motorola Semiconductor, Inc. 15. Zimmerman and Mason, "Electronic Circuit Theory", Wiley and Sons, New York, I960.

6-27

7.0 AC PHASE CONTROLLED APPLICATIONS This section discusses uses of the SCR in modifying the load circuit voltages by controlling the amount of AC input available. Power circuits have three general modes of operation. First, as on-off control to vary the duty cycle to the load; second, to control the point on the input waveform where conduction begins so voltage and power reduction to the loatl is affected; third, control mode is to combine the first two modes with converter circuits to generate variable DC sources. Some typical circuit configurations using these principles arc illustrated in Figures 12-51 and 12-52. Typical response characteristics are given for design purposes. 7.1 PRINCIPLE OF PHASE CONTROL A wide variety of applications exist wherein the load responds to RMS or average values of current and power. Typical of these arc resistive loads such as furnaces, heaters or lamp loads which utilize different RMS currents. Another large application area is the AC and DC motor which derives its torque from variable average or special RMS current waveforms. The SCR is ideally suited to control these loads in that it governs the amount of available system KVA that is transferred to the load. Varying the initiation of thyristor conduction directly affects the RMS or average value of current and voltage that will appear at the load terminals. Therefore, these two parameters are important in the rating and application process. The thyristors are rated for a maximum RMS current for a range of conduction angles, whereas the average current (which is most popular), is portrayed against stud temperature. In Figures 7-1 and 7-2 the RMS and AVE values of a resistive circuit arc illustrated for various delay angles.

90° Delay Angle a

FIG. 7-1—Rms and Ave Relationship for One-half Control Waveforms for Resistive Load

From these curves the desired power can easily be translated to the average cur¬ rent required from the SCR. Since this information is a data sheet parameter a satisfactory device is easily sized for the application and the remaining application parameters may be quickly selected. 7- I

FIG. 7-2—Kins and Ave Relationship for Full Controlled Waveforms

7.2 COMMUTATION IN AC CIRCUITS Commutation in AC resistive circuits up to 1 KHz ordinarily do not present a problem to the designer. As the AC waveform reverses the thyristor junctions, stored charge is swept out and the following reverse voltage allows sufficient recom¬ bination time so the thyristor easily supports forward voltage when the AC line goes positive again. However, at higher frequencies and for certain application problems, additional considerations are required. 7.2.1 Commutation with Circuit Transients Certain applications, by nature of circuit inductance, give rise to commutation transients which far exceed the power frequencies dv/dt. For example consider the Westinghouse 2S2ZZ Pow-R-Disc thyristor in a circuit whose input voltage is 960 V-RMS at 1 KHz, the max. supply frequency dv/dt is: v = 1340 Sin cot dv/dt = w. Vp Cos wt dv/dtmas = w. 1340 (10‘°) ” 2ir(1000). 1340 x 10'° dv/dt*8.4 volts//i second This is well below the critical dv/dt rating of the device where false anode triggering is effected. The circuits in Figure 7-3 illustrate two typical applications where critical dv/dt voltages may be generated at even lower supply frequencies. The waveforms illustrated in Figure 7-3(a) are found in high power systems or in applications where the load KVA demand is a major part of the transformer capacity. The various discontinuities in the waveform are due to the commutation of other devices in the converter circuit. During the commutation period two phases of (he transformer are shorted together by the incoming and outgoing devices. This causes a dip in the phase voltage which appears across the non-conducting devices in the converter. At the end of the discontinuity a sharp rise in voltage occurs which may exceed critical dv/dt and cause false firing and erratic operation. This type of dv/dt firing mentioned above is described in detail in Section 6.2.2. When dv/dt triggering gives rise to inverter shoot through excessive current surges may result in a shorted DC bus. If, for example, (he inverter is controlling a motor in the inverting mode, to apply braking via load regeneration, dv/dt firing

7-2

(A) Conwtar dV/dt VoRaga TrenMno

(6) SCR Of Wv'vfoirm for an AC Switch with an Inducltva Load

FIG. 7-3—Circuit Connections Generating Critical dv/dt Voltage

results in severe overcurrents in the series SCR. These devices form a free-wheeling circuit that rmisl handle all the motor and load energy, To circumvent this commutation transient in all converter circuits, an RC snubber circuit should be provided to suppress the rate of rise of voltage across the device to a value below the critical dv/dt rating. In Figure 7-3A a set of commutating reac¬ tors were included in the converter circuit (i.c.,I-c). These reactors, with an appropri¬ ate R-C snubber circuit, are effective in maintaining dv/dt requirements for this circuit configuration. (See reference 1-5 for reference and design procedure.) The second illustration in Figure 7-:l shows the effect of operating an AC switch into an inductive load. The lagging load power factor causes a device to conduct beyond the zero voltage point in the waveform so a positive voltage is available when the conducting thyristor drops below its holding current. In addition to the positive line voltage an L(di/dt) voltage is generated when the load current abruptly ends. This voltage magnitude is dependant on device holding current, device re¬ covery characteristics and system impedance values. To alleviate these problems a number of options are available - - use of all diffused devices with high dv/dt capa¬ bility, high voltage devices or R-C snubber circuitry to reduce the device dv/dt. An example is given in Figure 7-4.

Optional

f

'M

Wcstinghouse

'1

i*. nun

C in pfd

75 50

.05

201,202. 203

.1 .22

250, 251,254,219 260, 261,276

.5

1270, 271,282, 283

35 35

Ltot Rtyp

Device

dV

'^max" dt

'For PRV to 1000 volls *For high drive applications FIG. 7-4—Typical Snubber Circuits for SCRs

7.2.2 Commutation with Reduced Reverse Bias I n AC and I X' circuits where ..omy is desired, an SCR is often used in the cir¬ cuitry described in Figure 7-5. In circuit (a) the inductive load being turned off generates an I .(cli/clt) voltage that is fed to the thyristor. This transient voltage has a double effect. First, it may exceed critical dv/dt and bring about false firing and perhaps equally important it reduces the amount of time available to assure that the t hyristor is t urned off, prior to reapplication of voltage, There are several approaches to this problem, (1) R-C Snubber Circuit on the input terminals A-U; (2) R-C Snubber Circuit on the thyristor; (3) Select Rectifiers for tRR > l„(l (thyristor). Of these options the first is preferred whereas the third will work on "selected" products. The second option is interesting in that it supplies latching and holding current for the inductive loads, I lowcver, a resistive bleeder path is required around the inductive load for holding current. An additional point of concern with circuitry of this type is the amount of time that is available to assure the turn-off interval in the single thyristor circuit. With increasing line voltage the turn-off time available for the thyristor drops remark¬ ably. Therefore, higher voltage circuits are better served with two thyristor circuits. In Figure 7-5(b) the load circuit has been placed in the DC part of the converter with the thyristor. For the inductive load, a free-wheeling diode is included. This allows the circuit to function as a resistive load in that the inductive voltage reversal of the load causes a free-wheeling current to How. This allows the thyristor the commutation interval at voltage zero for turning off. However, voltage considera¬ tions as described above, also limit these circuits to low line voltages. 7.3 AC CURRBNT TRANSIENTS WITH SCR CONTROLLERS The application of thyristors as AC Switches, primary controls for resistance welding and. ns solenoid drivers can give rise to current magnitudes in excess of design values. These transients occur when low duly cycle switches arc energized or gated at some delay angle that does not properly account for the steady state phase relationship between load current and voltage. When the circuit is gated at a dis¬ similar angle, an asymmetrical current results in the line. In Figure 7-6 the first cycles

7-4

VD (forward volt)

«- time in /l/Mconcis -* hi dV/dt and turnoff Tima in Single SCR. AC Switch for Various Input Conditions

FIG. 7-5—Circuit Connections with Reduced Commutation Times

of current through an AC switch configuration illustrate the effect of varying the delay angle for this circuit configuration. The transients illustrated in circuits (a) and (c) die down after a few cycles and steady state current and voltage results. However, for short conduction intervals, a few cycles of transient energy may be sufficient to cause overheating of components and inadequate system performance. To prevent this problem the designer must trigger his switch at the natural current zero so transients do not occur.

-tf-

FIG. 7-6—Effect of tinting an AC Switch at Various Delay Angles

The problem illustrated in Figure 7-0(tl) represents a problem common in many AC Switch applications. For synchronous controls and EMI reduction, the designer often switches at the natural voltage zero of the power frequency. However, if the transformer is energized at zero voltage, il sets up a demand for maximum Dux density (i.e„ e= -N(d$/dt)). Unfortunately the core is often at some remnant Hux position as illustrated in Figure 7-7. Therefore as the input voltage increases to the flux density increase to a peak value equal to (BR+2 Bm„«) 90° later. Unless die transformer is overdesigned or used well below its rating, saturation results. The transformer core now acts like an air core inductor and the line current increases to a level governed by core material, line impedance and the original value of BR. To design for this detrimental operation the designer must use high delay angles on startup or know the core history and circuit conditions as previously described. 7.4 THE SINGLE PHASE AC SWITCH The AC Switch is a basic circuit configuration to control the power flow in the AC circuit. The circuit is illustrated in Figure 7-S. It utilizes two thyristors in the inverseparallel connection. The point in the cycle where conduction is initiated determines the load KVA, as per Figure 7-2. Another option used in some economy circuits is to replace one thyristor with a conventional rectifier. However, care must be exercized with this connection as it 7-6

introduces a DC component in the output waveform. If the load is inductive or if the switch load represents a major portion of a transformer load, then this connection should not be used. 7.4.1 The AC Switch with Inductive Loads In section 7-3 some gating problems causing line transients were discussed. These problems arose specifically due to the magnetic status of a transformer and improper gating procedures. If the load is inductive the general problem of half wave rectifi¬ cation becomes critical. When narrow gate pulses are utilized, half wave rectification may result as the AC Switch delay angle is rapidly changed. Conduction will not occur in a given thyristor unless the current through the opposite device has gone to zero. Therefore, during the phase advance a narrow gate pulse may be ineffective and current pulses exceeding ISO” may result in the conducting device due to the inductive load. There are a number of design approaches to solving this problem. Each has its advantages, disadvantages and economics. They are tabulated iit Fig¬ ure 7-9 for review. Figure 7-10 illustrates the effect of inductive loads.

Triggering Method

Comments

(1) Narrow gate pulses with restricted a range

This procedure is restrictive and failure prone un¬ der transient operation

(2) Continuous gate signal or extended pulse exceeding load power factor angle

This procedure will trigger the device and afford commutation at current zero at the expense of gate complexity

(3) Using line voltage as synchroniza¬ tion

This approach makes for the simpler gating tech¬ niques but docs not account for load power factor

(4) Using device voltage as synchroni¬ zation

Eliminates half wave rectification as firing pulses are synchronized at current zero regardless of load conditions. However this method is complex and difficult to use at high delay angles

FIG. 7-9—Firing Considerations for an AC Switch on Inductive Loads

The effects illustrated in Figure 7-10 arc quite variable anil very dependant on the load power factor. In general, the effect of low |x>wer factors is to increase the con¬ duction interval , increase the line current, increase the load voltage and decrease I he load power, The effect of the loading is described in Figures 7-11 thru 13. For other configurations - i.e.: parallel R-L loads, these curves are rather representative for approximation of device ratings. In the case of capacitive loads di/dt and surge currents require imlividna! consideration. 7.4.2 Harmonic Disturbances with the AC Switch In any thyristor converter I lie chopped AC waveforms may give rise to radio and communication interference. The elimination and interpretation of these disturb¬ ances are covered in Chapter 9.0. To illustrate the likelihood of communication dis¬ turbances, the harmonics present in ail AC Switch are illustrated in Figure 7-14. Additional inductance will reduce the magnitude of these harmonics in the line and reduce interference. 7.4.3 Overcurrent Protection Overcurrent protection is conventionally handled by fusing and circuit breakers where the system impedance will allow. However, the application of AC Switches as welder controllers utilizes the devices at low duty cycles which allows the designer to utilize the thyristors near their surge current ratings. Other applications utilize the 7-8

1'IG. 7-12—Variation of Conduction Interval for AC Switch with Various R-L Loads at Different Delay Angles

devices at or near their maximum ratings wherein small, slow rising overloads can exceed device ratings before a fuse or breaker may operate. In these applications, a circuit to inhibit gate action could shut the system down by inhibiting gating before the device junction temperature is exceeded from the current overload. A system to do this is shown in Figure 7-15. In the described circuit SCR| and SCR.., thyristors fire the AC switch with an extended gate pulse to assure proper operation with low power factor circuits. To start the circuit the momentary switch SI is thrown to reset the bistable circuit formed by transistors Q| and Q». This removes the bypassing effect on the timing circuit so the unijunction circuit might function. The unijunction stage is coupled through a transformer-amplifier circuit that triggers the extended pulse triggering circuit for the main AC Switch. During the operation of the AC switch, current transients may be experienced which exceed design limits. To protect against this, a lock-out provision is included to shut down the trigger circuits, when overcurrents are experienced. This circuit is shown with transistors

Q., ami Qi. When the set

point

is exceeded, this stage reverses so that the collector of Q3 goes |>ositive. This triggers Qi of the binary stage which locks into conduction and inhibits the UJT trigger stage and AC Switch operation until a manual reset is made. This circuit will function well when sufficient circuit reactance is available to limit the initial surge current peaks below the thyristor Ij-m ratings. For values equal to or exceeding Ism a fast acting fuse must be included. Kxccssive current levels will exceed the device junction temperature so that blocking capability will lie impaired. Therefore this circuit tech¬ nique should be used only for applications within the device ratings. 7-10

FIG. 7-13—Variation of Line Current in an AC Switch with R-L Loads at Various Delay Angles

7.5 THREE PHASE AC SWITCH CONFIGURATIONS Using thyristors as AC Switches is a logical proposition as the power level in¬ creases. This is due in part to the desire to balance large loads on the AC network and accomplish certain control schemes. In Figure 7-16 the common polyphase con¬ nections for AC Switches are illustrated. Each of these circuits has particular ad¬ vantages. These advantages vary in economy, special uses and technical performance. The designer wall have to investigate his own requirements to determine the circuit selection.

0

20

40

60

80

100

120

140

160

180

Delay Anglo tt-*Degrees FIG. 7-14—Harmonic Content of the l.lno Current in an AC Switch with a Resistive Load

Of the seven circuits described in Figure 7-10, five have use in general applications. These circuits (A, B, C, D Sr K) are basic building configurations for resistive and inductive loads. The circuit shown in 7-101*' is useful in reversing the rotation of AC motors. As an example when switches 1 and 4 are operated, the output phase se¬ quence is the same as the input sequence (i.e., ABCS 1-2-3). However when switches 2 anti 3 are operated the output phase sequence is reversed on lines 1 and 2. Therefore the load phase rotation changes from A-B-C and 1-2-3 to A-B-C- anil 2-1-3. Front AC motor theory it follows that rotation direction will also reverse. Circuit 7-l fiC is a variation of 7-16F in I hat 2 switches and two phases arc controlled. This circuit can be used to turn the AC power on and off in switch service. However, load 7- 12

1

Figure 7- 16 -B.

Three tp Sin SCR Switch Using Ground Return as a Currant Carrying Conductor

Figure 7- TG~C. Three ipSix SCR Swirch Using the Power Leads Only

imbalances make i( impractical for large phase controlled applications. The wave¬ forms for this switch are shown in Figure 7-22. For comparative purposes the remaining circuits are analyzed and described be¬ low. For particular loads and special configurations a summary is also included.

7- 14

Figure 7- 16-D.

Three Three SCR Three Rectifier Switch Using Power Leeds Only

Figure 7• 16 E.

Figure 7- 16-F.

Three $ Six SCR A C Switch Using en "inside the Del to" Configuration

Three $ Eight SCR AC Switch for Changing Phase Rotation to Motor Loads

7.5.1 The Three-Phase Three SCR Circuit This circuit, described in Figure 7-16A, is an economy circuit requiring three thyristors for control. However it requires that the 3 load consist of individual loads that may be connected in an "open wye” configuration. This is somewhat restrictive unless single phase loads or transformers are to lie used. Gating control

Figure 7- 16 -G.

Three Phase Four SCR AC Switch

FIG. 7-16—Various Configurations for the Control of AC Power

of this circuit requires a range of 210° to achieve full control. The current and voltage waveforms are as illustrated in Figure 7-17.

7.5.2 The Three-Phase Six SCR Switch Using the Ground Return and “Inside the Delta” Configuration The two circuits, described in Figures I! and K, are polyphase circuits that behave as three single phase circuits with 120° phase displacement. This is quite apparent in Figure 7-1611 where the fourth wire, or ground return wire, is used as a current carrying conductor. This is an unusual practice in industry and is used only with a special transformer or bus system. The details for this switch are the same as for the single phase AC switch, described in Section 7.4. The circuit in Figure 7-16E is a three wire equivalent of circuit B. As in circuit B the SCR’s do not conduct through one anolher as is the case for switches connected in the line. Therefore higher line currents than in circuits C anil D may be accommo¬ dated with this configuration. This affords a higher KVA rating to this system than the line switch connections. If the reader refers to Figure 7-10, the 30° phase shift and amplitude variations can be seen for the phase and line currents. This, therefore, makes this configuration appear like a wye-connected load but without the disad¬ vantage of a current carrying ground wire. As with circuit 7-1611 full control requires a 180° range in gate signals.

7.5.3 The Six SCR Three-Phase AC Switch for In-Line Connection The circuit shown in Figure 7-IGC is a three wire configuration that allows the designer freedom to select the load configuration of his choice i.e., delta, wye or direct rectifier. However, the resulting circuitry is necessarily more complex in that thy¬ ristor pairs, in different switches, must conduct simultaneously for up to 60° (at maximum conduction). At retarded angles, double conduction intervals result so that double pulsing or extended gate pulse widths (i.e., >6(1°) must be used. One of the advantages of this circuit connection is the low harmonic content of the output. This is due to line currents being symmetrical so only odd harmonics can exist. Of these, the third harmonic is cancelled out so this circuit reduces the filtering problem for noise reduction in neighboring communication lines. The waveforms for this circuitry are illustrated in figure 7-20. As indicated bv

7-16

Phase I Voltage

SCR, Voltage

Phase I Current

SCR, Current

Delay Angle

o = ao"

a - r.o°

o * go°

o = 1 T0°

Jv

a» tso°

Q » 180°

a = jio°

FIG. 7-17—Waveforms for Hie Three SCR 30 Controller (Resistive I,on« sen Four Wtim Circuit

Harmonic Currants for Various Loads on Rosxttve Loading (Circuits 7.16 A. B & El

FIG. 7-24—Comparison of Harmonic Content of Various Three 0, AC Switches

7-26

7.6 SPECIAL PURPOSE AC SWITCHES and LOAD TAP CHANGERS In many applications AC line regulation is such that constant voltage regulation systems arc employed. The regulation schemes vary from the small "bench type” constant voltage transformers to huge load Lap changers on commercial power lines or on electric furnaces. The equipment listed is not practical to cover the full range of usage in that size and costs are limiting factors. The constant voltage power source becomes uneconomical for power installation whereas tap changing is bulky and impractical in low power systems. Special thyristor circuits can be used to accommodate the needs of a wide variety of regulating functions. In Figure 7-25 three typical circuit arrangements are illus¬ trated. In circuit A, voltage regulation is effected by simply energizing the desired thyristor pair, in appropriate sequence, to either step up or down. Circuit li is a modification of A in that a tap change is made al a point other than current zero. This arrangement offers a wider RMS current range then in circuit (A). However, it introduces harmonic currents to the line. Circuit C is a hybrid arrangement allowing the designer to utilize the SCRs at low duty cycles and high currents, so very large KVA tap changers can switch the load current without interrupting. This reduces contact arcing and can add significant life to the large contacts of a lap changer.

7.6.1 Operating Characteristics of Tap Regulators The three basic circuits shown in Figure 7-25 have gating considerations that must be studied closely. On resistive or unity power factor circuits a step change is effected when SCR,, at maximum potential, at time A. commutates SCR- and car¬ ries the load current. At point B, 180° earlier in time. SCR, is commutated by the positive tap voltage so SCRs will conduct. At Voltage Zero the devices drop out of conduction and the opposite device begins conduction. This is the ordinary transfer point for circuit A whereas circuits B and C may begin conduction anywhere in the cycle. If the load on the tap changer is reactive, as depicted in 7-26 (2) & (3) a triggering signal derived from the voltage waveform may well result in a tap short circuit or loss of load power. Consider the lagging waveform shown on (3). A short circuit results at point (C) when, as SCRi is still conducting, a stepdown is called for by the triggering of SCR:. The same condition can result from a variety of circum¬ stances and is prevented by the generation of logic circuits that control the gate drive circuitry. One of the initial steps to prevent tap shorting is to trigger the de¬ vices individually in proper sequence. A simpler scheme is to trigger the AC switches from the same trigger source. However, if this is done, the logic circuit must remove the gate drive prior to a tap change in accordance with the existing load power factor. An additional point of concern in this type of circuitry is the voltage stress on the SCRs. For conventional AC voltage ranges the tap arrangement shown in 7-25 A and B can be used to approximately 700 V-RMSwith single devices (i.e., such as Westinghouse 2S6ZZ). However, the conventional thyristor PRV limits this appli¬ cation to the 480 VAC circuit. Circuit 7-25C, on the other hand, is limited only by the tap voltage that it sees during a switching sequence.

7.6.2 SCR Regulation Systems and Flicker The possibilities of maintaining the regulation on an AC bus are quite diverse. Chopping, sequencing and transformer tapping are just a few. The techniques that might be utilized vary with power level, circuit responsecharacteristicsand public utility restrictions. For example, consider the wave forms shown in Figure 7-27. A variation of the regulation scheme is shown in (B). This system removes an AC lobe or inserts some similar asymmetric component via in-cycle tap switching. However, the effect

7-27

A. Load Voltage Control by SCR Tap Switching 11-30 KVA)

Tungsten material

allows the voltage drop to assure

current transfer to the SCR’s

FIG. 7-25—SCR Switching Configurations for AC Voltage Regulation

A

Voltage

I

FIG. 7-26—V-l Relationship for Tnp Gltnngors on Various Power Factor Loads

of the DC component resulting from this makes the procedure unworkable at all power levels. In circuit 7-27A an in-cycle response characteristic is indicated. This in-cycle regulation, is accomplished by varying the amount of voltage boost per cycle, (i.e,, varying point A) gives very fast regulation of the line. However, the harmonics as¬ sociated with the introduction of chopped sine wave current waveforms gives rise to noise and filtering problems in the power lines.

(A) In Cycle RMS Regulation

(Bl Duty Cycle RMS Regulation

FIG. 7-27—RMS Regulation Waveforms

Conventional Lap changing utilises the characteristics shown in Figure 7-27(B). For regulation purposes the line voltage is sampled over a relatively long period (typically 1 change per 15 min) and tap changes arc then made. A solid-state system can be employed that offers superior regulation in that the switching frequency can be increased. This affords a better regulation characteristic. However, these rela¬ tively low frequency fluctuations can introduce a flicker problem if a lighting load is on the bus. Cyclic recurring voltage fluctuations to a lamp load can be very annoy¬ ing and objectionable to people working in the area. The degree of annoyance is directly related to the nature of the disturbance. The sensitivity is plotted for various voltage and frequency fluctuations below. 7-29

Frequency of Voltage Pulsation (Cycles Per Sec.) Cyclic pulsation of voltage at which flicker of 115 volt tungsten iilament lamp is just perceptible-derived from 1104 observations by 05 persons in field tests of 25-watt, 40-watt, and 60-watt lamps conducted by Commonwealth Edison Company. Figures on curves denote percentages of observers expected to perceive flicker when cyclic voltage pulsations of indicated values and frequencies are impressed on lighting circuits. Plotted points denote medians of observation - at various frequencies, number of observations in cacli case being indicated by adjacent figures.

It should be noted that this type of regulating system introduced Dicker frequen¬ cies from 30 cycles and under. Therefore the maximum nuisance factor is to be ex¬ pected on this system.

7.7 VARIABLE DC VOLTAGE CONVERTERS In Section 7.1 the basic principles and advantages of phase controlled voltage control was illustrated. Figure 7-2 illustrated the special case where the sine wave segments were “steered1' so as to yield full wave DC control. By similar techniques Figure 7-1 illustrates the effect of half wave control. In Figures 12-51 and 12-52 the common circuits using phase control are tabulated for the readers’ review and design aid. The type of circuit selected affects ripple content in the DC, filtering required and the amount of power that can be drawn from a given source. Low KVA loads are typically handled with single phase controllers such as that shown in Figure 7-28. By varying the triggering point, the output voltage, the available DC Power, Output I larmonics, and power factor are varied as shown in Figure 7-20. Therefore this circuit is readily adapted to those applications requiring a variable DC voltage. Examples are motors, solenoids, magnets, battery chargers, etc. The advantages of lull control arc very apparent from Figures 7-1 and 7-2. With increased KVA demands the AC imbalance forces the designer to three phase con¬ verters to achieve line balance. The type of circuitry just described can be extended into polyphase circuits. However, a further review of the problem accents the ad¬ vantage of selecting the proper converter.

7.8 A COMPARISON OF THREE-PHASE CONVERTERS fit three phase controlled rectification, two basic circuit techniques are utilized. One circuit utilizes six thyristors as shown in Figure 7-30(a) while the second em¬ ploys three thyristors and i lu ce rectifier diodes, shown in Figure 7-30(b). Each circuit

Line Voltage

Line Current

vfb|

vrb{

'SCR,

,«8«

VLoad

FIG. 7-28—Circuit V-I Characteristics for Single Phase Full Wave Bridge at o = 45°

lias certain application advantages or disadvantages. This section discusses the differences.

7.8.1 Rectifier Characteristics Line Voltage and Commutation Control of both circuits is achieved by varying the point in the AC cycle where conduction is initiated. This (joint of reference is denoted as “A” in Figure 7-31 and is the piont from which the delay angle a is measured. The delay angle a is the amount

7-31

of gate signal delay used to reduce the output voltage of the converter. Reviewing three phase waveforms, note that point "A" is the point wherein the “incoming” phase voltage becomes more positive than all other phase voltages. Similarly, point "B" is the point wherein the negative-going phase voltage becomes more negative than all other phases. The electrical difference between points "A" and "B” is 60° and gives rise to ripple and commutation differences between the circuits. In the semiconverter circuit, voltage control is achieved by varying the gate signal between /LsAT C = 4L/R2 t

> SCR^ t off

Note t ” in p sec L = in p henry C = in p farad

FIG. 8-13—Commutation with Saturable Transformer

illustrations arc shown in Figure 8-1 fi. In the series resonated load, the trapped energy on the capacitor must be removed by a long time discharge circuit, or by using a second thyristor to dissipate the energy in a short time tlischarge circuit. 8.2.6 L-C Free Commutated Circuits The circuits of section 8.2.5 are limited, as the load circuit itself must be part of a tuned circuit. This places restrictions on the control range of the circuit. Therefore, 8- It

- R-C Discharge

IE r\ RL

INPUT pulse

is
toff C = 3 t off/R L dv/dt = 1.2VJ/CRL Rl st.IVt FIG. 8-14—Transformer Commutated Circuit

r' t

-V _L

uJR2 ®c®scR2

K

dv/dt

Nominal Design Criteria R, = R2 t - in it sec C

- in F fd

SCR Parameters di/dt - V-,/L

T"

'R2

VFB “V, VFB=V1 VRB -V, VRB"V1 dv/dt - 1.2 V|/RC V^RC C

- t/.6R

t*

S t off off

'SCR2

I-1_^_ . SN ^ I 1--1-

vSCR2

4^--

FIG. 8-15—Capacitor Commutation

wide swings in load impedance are not easily accommodated. To get around this problem the tuned circuit can lie connected differently to avoid these limitations. Figure 8-17 illustrates two examples.

Nominal Design Criteria SCR-] Characteristics di/dt

- Vj/L

•PRV, PFV = 3.0 qLOAD

*dv/dt=5V1/v'LC for

•

t

= vTC tan

1(4) > SCR. t off

* * FIG. 8-16—Resonant Load Commutation

I n circuit (a) the capacitor charge is indicated for the condition prior to triggering SCRi. When SCRi is triggered the resonant action of the tuned circuit causes the capacitor voltage to reverse and bring about a current reversal. This reversal will commutate the SCR off so that the capacitor current flows through a new patli con¬ sisting of C, I., R,_ and the battery. This path allows the capacitor and SCR voltage to reverse and come back to battery potential. An improved version of this type circuit is shown in Figure (b) and is commonly referred to as the "Morgan Circuit". The advantage of this circuit lies in the satur¬ able reactor which allows improved switching characteristics and smaller reactors. The capacitor charge for (B) is shown for the initial conditions due to battery voltage or a previous commutation cycle. Either of these occurrences also effect positive reactor saturation via capacitor charge. When SCRi is triggered, the voltage causes the reactors to be forced out of their saturated state by the load current IrL. 8- 13

SCR,

fv7 T 1Irl

rr^c lL

Nominal Design Criteria

Nominal Design Criteria

SCR Parameters

SCR Paramaters

di/dt

= V,/L

di/dt

=V1/L2

Circuit Stress Volt. =V,

Circuit Stress Volt. = 1.8 V,

dv/dt

= 1.25 V,/R,_C

dv/dt

= 1.5 V,/RC

t

= .6 RC > SCR, toff

t

- .6RC>SCR, to(f

Circuit (a)

Circuit (b)

lfIO. 8-17—L-C Free Running Commutation Circuits

I luring ibis interval, the positive capacitor charge is being depleted by Li, C & SCRi action. During this time, the reactor Li is supporting the capacitor voltage. However, when the volt-second capability of the core is exceeded, saturation occurs as shown at time ti. The resonant reversal of (he capacitor charge now occurs at a new fre¬ quency, determined primarily by the saturated inductance of I.,.

8- 14

As the reactor voltage reverses (it—peak current midway between ti and t2) the core comes out of saturation and the last part of the resonant charging interval is controlled by the unsaiurated inductance of Li. When the capacitor is at peakreverse voltage, the cycle repeats in the opposite direction, thus saturating the core in the positive direction at t». The SCR is now commutated olT and the capacitor is reset to the initial condition, via the path of C, Li, I.?, Rl and battery. Using circuits illustrated in Figure 8-17, the designer may utilize a wide load range and have considerable load current control. In these circuits, the L-C time constant may be made quite short so that greater control of the load power is achieved, than in the examples of Section 8.2,5. 8.2.7 Auxiliary L-C Commutating Circuits The preceding L-C commutated circuits are restricted in operation in that the turn-off time constants directly control the amount of time that load current may llow. I f the capacitor charge is trapped by a second switching device, the energy may be released on command and afford increased control features. This class of auxiliary controlled switches uses at least two SCR's; one controls the load current; the second controls the commutating currents. Figures 8-18 thru 8-21 illustrate the common circuits utilizing an auxiliary SCR and a resonant L-C section. Circuit No. 1 The circuit illustrated in Figure 8-18 is used in chopper circuits, as an in-line switch which does not require reactive power flowing to the battery. To make this circuit function properly, SCRa must he triggered first so the capacitor is charged as shown. SCR- drops out. of conduction when the charging current for C drops below its holding current. When SCR] is triggered, the charge on the capacitor is reversed via the path SCRi, L, Di, and C. The diode in this path traps the charge reversal and C is left with a reverse charge of approximately .5 to .8 Vj. Care should he exercised in selecting Di, as any leakage currents bleed the capacitor charge and degrade system performance. The reason for a lower than expected reverse charge on the capacitor is due to resonant circuit losses, such as SCR] turn-on plus Di recovery losses.

& SCR2’

:

L-tfh C-iild I •

V,

Nominal Dnlgn Criteria SCR, dl/dl

- Vl/L IPwt. Loop)

Circuit Strata Volt. • V, dv/dl

• 1.25 V,/RiC

t,

-.eRC*SCRtoff

scr2 di/dt

- 2 Vl/L (Pwr. Loop)

Circuit Strata Volt, - 1.8 V, dv/dt t

FIG. 8-18—III Line Chopper Switch

8- 15

To cause circuit interruption, SCRi is again triggered. This places the reversecharge across SCR, and turns it off. The capacitor charge is then reset to the initial condition through the load. Circuit No. 2—The Jones Circuit A drawback on the in line circuit is the requirement that the capacitor must be initially charged before commutation can be achieved. The circuit in Figure 8-19 overcomes this drawback by a novel reactor connection. As SCR- is fired, the close coupling between the reactors causes the capacitor to be charged as shown. Diode Di traps the capacitor charge until SCR« is triggered. This action forces SCR, off via reverse bias, and the charge on C is reversed through the path Vi C, SCR,,, I.. and R|_.

Nominal Design Criteria SCR, di/dt =vl/L2 Circuit Stress Volt. = 1.8 V, O

dv/dt

= 1.5/RC

t,

= .6 RC

SSCRl’off scr2 di/dt

= (V, + Vq)/I_2

Circuit Stress Volt. = 1.8 V, dv/dt

=> 1.5 RC

t off

= when lc

S'H KltJ. K-19—The .1ones Circuit

Alternate operations of SCRt continually charge the capacitor for commutation. The voltage oa the capacitor varies with load and depends on whether the reset or load current is greatest. As the load is increased, the higher load currents result in higher capacitor voltages. Since the SCR turn-off time lengthens with current, the additional charge aids circuit operation as the circuit t„rf time t will increase with capacitor charge. Circuit No. 3 A disadvantage of the L-0 commutated circuit is that reactive currents flow through the load circuit, A circuit which avoids this problem is shown in Figure

8- 16

8-20. In this circuit, the capacitor is resonantly charged to between 1.5 and 1.8 Vi according to circuit losses. To achieve commutation, SCR* is triggered and the voltage developed across I... reverse biases SCRi turning it off. The charge on C then reverses and commutates SCRa. Next, C is again resonantly charged via Vi, Li, Di and C. Circuit losses are sufficient to prevent the capacitor voltage from "ratcheting" up to destructive levels. In very high Q L«-C circuits, a long time constant load may be used to guard against this. This connection is depicted with resistor Ri.

Jl

'■1

C-pfd t -imc

>82 Nominal Design Criteria

Jl

SCR

di/dt ,v1/l2 Circuit Stress Volt. “ V, dv/dt - ,5V./L2 *1

” -25 yj L^C

'SCR2

MY

vSCR2

scr2

di/dt

-1.8V1/L2

Circuit Stress Volt. - 1.8 V,

VC

- ■6V1/v/Tjg “ 1.5^/L^C

dv/dt t2

FIG. 8-20—Auxiliary t.-C Commutation w/o Reactive Load Current

In designing this circuit, care should be exercised in selecting l-i and I.;. Since the action of l.« and t‘ is not isolated from the battery source, l.i must be much larger than U, or Di must be replaced by a third SCR. Another alternative is replacing I., with a resistor. Whichever passive option is used, the designer must assure that proper turn-off of SC'Ra occurs before the charging current to (’ reaches the holding current level of SCK>. Circuit Variations The needs of an application give rise to many variations of the general classes of circuits just discussed. In Figure 8-21, some of the common variations are depicted. In Figure (a), a variation of Figure 8-18 is used. For this connection, the capacitor is charged immediately via triggering SCRi so that the drawback of 8-18 is removed, Figure (b) is a modified Morgan circuit which utilizes two additional thyristors to control the circuit timing and achieve better control range. Circuit (c) replaces a diode inductor combination of Figure 8-20. The advantages are: capacitor ratcheting is avoided, and the problems with the timing of two tuned circuits are eliminated. 8-17

SCR,

(a)

With Resonant Charging Sliunt Circuit

°2

(c)

Modified L-C Commutation

(d)

Ckt. for Greater Freq.

Capacitor Commutation With Low Stand By Power

Characteristics

FIG. 8-21—Examples of Circuit Variations In Turn-off Schemes

III Figure 8-15, (he extra anode resistor is replaced with a transistor. This reduces the stand-by power losses in small vehicle controls. A similar feature may be utilized by replacing the resistor with an SCR-inductor combination. This also reduces standby losses, and by resonant charging capacitor C, superior turn-off capabilities result. 8.2.8 The Gate Controlled Switch All the illustrations thus far utilize conventional techniques to achieve turn-off. This procedure is described in Section 8.0 and requires control of anode power. A specially designed thyristor is available which can commutate current by controlling gate terminal power. These gale controlled switches or GCS's can commutate load currents up to 100 amperes by generating an appropriate gate turn-off signal. The illustrations in Figure 8-22 indicate two methods of achieving current inter¬ ruption with this device. In circuit A, turn-on is achieved by coupling a positive gate signal to the device via V'-.., R,, C and the GCS gate. The anode current rises causing the device to conduct while the capacitor charges as shown. To interrupt load current, transistor Qi is driven into saturation so that the charged capacitor is placed across the GCS in a fashion that brings about a negative gate current and device turn-off. 8-18

FIG. 8-22—Examples of Circuit Commutation with the GCS

The circuit in (b) operates on the energy stored in an inductor. As device Q2 is driven into saturation the collector voltage is supported by the inductor L. This allows current to flow in the parallel path of the gate. After the load current is "on” the inductor no longer supports voltage and the gate current is minimal (dependent on inductor Q). When Qi is triggered, the binary action brings Q» out of saturation. However, the inductor resists the change in current and generates an - L di/dt voltage. This voltage causes a reverse gate current and device turn-off. 8.3 APPLICATION OF THYRIS TORS FOR DC MOTOR CONTROL The control of battery operated series wound motors involves control of motor voltage and current. The tractive force of a vehicle is proportional to armature torque, while the steady state speed is inversely proportional to the magnetic flux developed by the field winding. Since these traction motors have scries connected armatures and field the motor flux and torque are proportional to armature current. Typical traction motor characteristics are shown in Figure 8-23.

FIG. 8-23—Scries Traction Motor Characteristics

8- 19

The illustrations show the primary advantage of a series motor, in that high torques exist at low speeds. This is useful in accelerating high loads. To utilize this feature, the designer simply controls the motor armature current to control the speed. An old control scheme is to use a set of “starting” resistors to achieve the control characteristics of 8-23(d). In this operation, the motor accelerates from a to b for the initial resistor, then a second resistor R,_> is placed in series with the motor and causes the speed to rise from c to d, and last, the motor is placed on resistor R3 to bring the motor from e to f and steady state speed. Control characteristics such as this causes jerky operation and low efficiencies at maximum series resistance. 8.4 IN LINE CHOPPER CONTROLLER A superior technique for controlling DC traction vehicles is a chopper drive to control armature voltage and current. In this fashion the motor may be brought smoothly to its rated speed by better control of the armature current. 8.4.1 Chopper Requirements for Motor Control As the motor sizes increase, there comes a point in the range of application wherein worst case armature current cannot be commutated oil’ realistically with a given device. To gel about this problem, the designer should calculate the armature current worst case turn-on waveform, or perform a locked rotor test to measure the rate of rise of load current. The design must include a circuit to turn the main thyristor off before the maximum commutating current is reached. The waveforms illustrating this are shown in Figure 8-24. This worst case waveform is then utilized to design the commutating control circuitry. For small motors and low supply voltages, the preceding problem may be insignificant due to resistive loading, and can therefore be neglected,

FIG. 8-24—V-I Characteristics of a Series Connected Traction Motor for “Chopper Application"

The actual control of armature average current may be brought about in several ways. In Figure 8-25 three common "chopping" techniques are illustrated. In Figure S-25(a) motor control is achieved by varying the conduction time for each switching cycle. This method controls the motor average current and torque, and 8-20

with increasing on/off ratios the motor speed is varied. In Figure 8-25(b), a similar technique is utilized except that the chopping circuit simply increases the number of switching cycles to increase speed. Though (a) anil (b) yield similar results, circuit (b) suffers from the increased switching losses. The last set of waveforms, shown in 8-25(c), are for a controller where the average current is a control para¬ meter, In this scheme a maximum peak-lo-peak range of load current (A) is used as a parameter to control the chopping rale.

r-pr

7']

!

'arm

35

I \

■

i

\

.

_1^._1

-i-

Minimum Speed

Vi

ARM Maximum Speed (a) Pulse Width Chopping Technique

IT/' \

A

'arm Minimum Speed

■V / \ 1

-TV

ir

/ N 1

V

/v

PN

7y

\

|

Sf'

V/'

'

>

\' bg( lime

Ave. Charging Current = IPi(X-

....

1

|

tr-ht(

/I clinmic Rev.

Rms Charging Current = I,*y—

I otal Rms Current = y Irms" rov'h Irme-chg* (8) Power Components (a) Main Thyristor

Total Device Current Waveform

Resonant Reset Current

Load Current

i

_ *(Ai+A>) | 2ip ,1V0~ "

I rino

—

2T

It •[ i!d,

t

+ ir XT

+

,—' . /1 _'PV2T .

t(Ai! + -V + Ai A») 3T

8-25

>'2

+

'"V2T

(b) Free Wheeling Diode

Bi + Bj 1

ti X2T,

(9) Load Currents (a) Locked Rotor Waveform

t, (Bi+A,) + t, (13, + Bj) 2T

2T

(b) Full Speed Waveform

, r

t V

l! 1

n

T

.

ti

Ci

Uvo-^x-r

Design Example For a design example, the preceding procedure will be used to determine the components in a motor control system. For the motor, the characteristics outlined in Figure 8-32 will be used. The system parameters arc: Battery 90 v nominal (i.e. 75-125 volts). Motor Current—160 amperes at rated value. “Breakaway” Current—700 amperes. Device t0rr time—30 /i seconds. Device Q.,50 a coulombs. Reviewing these characteristics, keep in mind that the described current is to generate a breakaway torque. Once the vehicle is moving, or for normal loading, the load waveform is as shown in 9(b) above. The reason for the variation in chopping 8 - 26

mode is to achieve commutation at high currents in heavy loading, but to use lower chopping rates for normal service. This change in mode will allow breakaway torque yet keep the device and capacitance switching losses at a minimum for extended life and reliability. To select proper values the worst case conditions will be assumed —i.e. heavy loading and high chopping rates. Once the components are sized for this service the normal chopping technique is relatively simple. (A) Capacitor Size During reset, assume that circuit losses will only afford .SV,. To recover the power thyristor a capacitor is required to supply the 50(ic Q„. 50 mc

100

75 x .5

75

1.32 nf

To assure turn-off _ I f x t„ff \ — —' * .5V„„

800x 30 , - ill 37.5

C = G40 g(—allow 10% tolerance. C = 750 (if to lit standard cases of 125 gf/case. (B) Inductor Design and Selection of Commutating Diode Since min. lc (i.e.—pwr thyristor on) for stalled rotor conditions is 1.0 milliscc. tch„« = .25tc = .25 x 10-J = !r -i/Ec .0625 x 10 11 9.8 x 750 x 10‘6 L = 8.5 fill—use 8.0 jih design. Ipb= 125/ V8-0 /750= 125/V-0107 ipii = 1,220 amperes

I 250 x 106 irms — 1,220

= 122-^2.5

10,000 x 10-«

irms= 196 amperes .25 ipve = 1,220 x .036 x — =39 amperes o.U

Wire Size—to reduce the circuit losses of the reset circuit, wind the inductor with 250 MCM cable with Type AVB insulation. Rectifier—Select rectifier on the basis of switching speed and equivalent Rms rating of the charge reversal current. Equivalent Diode at 60 Hz rating I peak (mi) =2 ir,in, =392 amps. 1 pvp („,,) = 392/ir—125 amps, use ® Type 400 with selected t„ of 3.0 jiscc. (C) Capacitor and Commutating Thyristor Data 1.5 x (1254-00) Reset Time =

800

750 x 10'c X

= 259(i Sec

1

259 x 10'6 . , to reset cap = 800xg_00()— =40.5 A

8-27

I nils to reset cap = 800 x ^259/5,000

= 179 A

total rm9 cap current = yi96’+179s =265 amps. Worst case rm, current/case—44.2 amps, for starting. Commutating Thyristor •10.5 amps ovc 179 Ampsrnu di/clt = .5 Viu,limx/Stray Inti.—for power layout wiring use I pit. di/dt = 02.5/1 (ill =62.5 A/pscc to motor current. Use

® Type

261 with a gate signal with rise time of 1,0 psec and 3.33 Igl to

account for this di/dt value (See AD Sheet 54-560). (D) Main Thyristor Current Rating 1.0 (075+800) x]0'3 +39=180.5

" lo.o x nr3

^/U) (676)*+ (800)*+(675)(800) 11[[q. 15

= 374

from capacitor reset. i = lm Sin «l di/dt = wlm Cos tj = wlm at t=0 di/dt =

2?r. x ———, x. 1,220 = ! 5 a/psec .5 x I O'3

from load current assume 10 pit loop inductance in pwr circuiting from battery to load 125 di/dt = ——- = 12.5 a/pscc. 10 ph di/dt rating = 27.5 a/psec. Select

®

Type 223 with 30 psec t„fr from 800 amps.

(E) Free Wheeling Diode

I avo =

800 + 075 4 ---x — = 590 amps.

Select 2

®

770 matched at 300 amps to V|. limit

50 mv.

(F) Control Characteristics A wide variety of logic is available to control the required switching functions. One design is included in Figure 8-33. The circuit provides for speed control via pulse width modulation. In the event of locked rotor or stalled starting conditions, a separate circuit turns off the main thyristor in advance of ex¬ cessive load currents as was described in the preceding "worst case" design. This allows the switching mode to change from pulse width modulation to armature current control by ripple regulation. In the latter case, breakaway torque is achieved by allowing tlie maximum armature current. However, the circuit turns off the main device within its commutating capabilities so that maximum ratings may be achieved. After the starting transient has ended, the circuit reverts to pulse width modulation and the reduced switching require¬ ments. Tlie preceding "worst case" analysis assumed that the motor current could be commutated within the circuit capabilities. To accomplish this, a reference and an analog of the current is required so the proper turn-off signal can be generated. To 8-28

accomplish this, the circuitry in can number two uses a magnetically coupled multi¬ vibrator to drive a chopper amplifier. The chopper amplifier has the current sensing shunt as its input and this voltage is amplified by the transformer turns ratio. The transformer output is rectified and fed into VR2. This signal, or some portion of it, is fed to Qn which acts as a current source fora low impedance R-C network Rsi-Cs. This voltage from R»rCs is used to trigger a UJT-transistor amplifier which ‘'over¬ comes" the controllers conventional turnoff circuitry. In high loading, this circuitry, and the turn-on circuitry is used to assure the desired stalled rotor current and keep within device turn-off capabilities. Calibration is achieved by setting VR2 in a posi¬ tion that adjusts motor, peak currents by the tj of Qn>. An additional feature of tin's controller is shown in can number four. T he stage of Qn is used to inhibit controller action when the armature is generating due to residual magnetizing flux, and the armature rotation due to vehicle motion. This circuit detects the generated cmf and damps the turn-on capacitor so that the controller does not turn on into an excessive motor current anti suffer commutation failure. The trigger circuits for this controller are conventional UJT oscillators with transistor amplifiers to achieve the desired gate characteristics. The circuitry in can number two is used to trigger the commutating thyristor SCRs while can number one controls the power thyristor SCRi. As you might expect from uncontrolled UJT oscillators, good synchronization is almost impossible for all the permissable ranges of frequency and device parameters (especially the UJT ij). To solve this problem, a binary stage is used as shown in can number 1. The collectors are connected to the UJT timing capacitors through resistor diode networks. In this fashion only one oscillator and gate pulse can he generated for a given binary state. Synchronization is achieved by changing the binary state and damping the oscillator after a gate pulse is generated. This is affected by a separate winding of the pulse generator that changes the state of the binary. This frees the opposite oscillator to bring about the trigger signal for the other thyristor in accordance with the controller settings. In the discussion of the in line chopper it was noted that the commutating capac¬ itor musl be charged prior to turning on the power thyristor. To assure this, the speed controller lias two switches that short the gate terminals of the power thyristor and damp the binary ill a fashion that allows the turn-off UJ'F oscillator to free run at maximum frequency. This assures that the commutating thyristor is charged before the controller is turned on. During normal operation the pulse width modulation feature is achieved by varying the operating time of the UJT' oscillators in opposite directions. This is accomplished by wiring VRI-A and VRI-1J in opposite connections and connecting them to a common shaft. The circuitry described above (Section 8.4.3) is shown in Figures 8-2!) to 8-31, and is not intended to illustrate the best design, but to present a design procedure. Other commutating schemes and control circuitry are available to perform the same or similar function. The designer should consider nil (lie variations in light of his particular conditions before selecting his method.

8.5 APPLICATION OF THYRISTORS FOR DC TO DC VOLTAGE REGULATION The use of thyristors in phase delayed rectifiers operating from AC mains is an established method for generating a regulated DC source. However, when the input power is a I >C main or buttery, a slightly different approach is required. One method is via a series pass clement, or series regulator. However, this technique allows only for regulated voltages below the minimum bus voltage and at low efficiencies for all other voltages. A much more efficient technique is to chop the DC input and then filter the output to achieve the desired regulation. An added advantage of this

8-29

Semiconductors D(i.j)

IN1353

D 1-6.7-12

IN34A IN645

Ds-8.1J.1J.I6

D„

®R510 F with t„ = 3.0 «sec.

D]8 (2 units)

© RGOO F

Du

® 359 F

SCR,

® 27(1 F with t,,„ select at 30 jisccTQ„ = 50 jic @261 F

SCR,

2N696

Qi-mi Qt-S-15

2N1671B

Qh-o

2N497

Qio-n

2N1039

Qit-ii

2N1379

Qh.,7

2N697

Resistors

Suppressors ®7CA12FC

Capacitors

R. Rs-a

200n-50w

Ci

15fl-2w

Cj

1OOjif/150v-clcctrol ytic 100jifd/150v-clectrolytic

R4.2s.2a

lOOO-lw

Ca

2jifd/200v-niet paper

Rs-b

3.3k-lw

C«

2jifd/200v-rnet paper

R«--

lOk-lw

Cs

. ljifd/200v-met paper

RlO-12-26

1508-1w

Cr.

6

Rmi

2.2k-lw

Rl3-14

2.7k-lw

Ris-io

75fi-1 w

cans-125jifd/130v-rms

met paper & ext. foil construction Inductor L,

8 jih

Rl?-18

1800-1

Rj9

2200-lw

R,o

4.7k-ltv

Ti-Tj-KMC

T-5684

R21.22.27

51fi-lw

Ta

- KMC

T-5683

Raa

1.5k-lw

T1

- Core-M agnetics

R,4

1.5 -lw

S 51091-2A-AS052

Rao

1.5 x 10'5S2-6 pcs .030 in1.

Wdg. Info.

Transformers

304 stainless steel, 6 in.

1

& 2—10T B,Filar

x .75 in. (parallel connection)

3 & 4—5T B|Filar

VR,

Dual 25k, Sw—DI’ST and NC

5 & 6—OT B,Filar

VRa

50k-2w Fiji. *-30 I’urts I.ist for Vehicle Controller

scheme is that a transformer may be added to a chopper circuit so that step up as well as slep down regulation is available. 8.5.1 Fixed Frequency, Variable Pulse Width DC Chopper Regulator This section discusses one form of a voltage regulated DC chopper using Silicon Controlled Rectifiers. It contains a complete description of the operation of the regulator including the function of each component. For illustration, an example of the design procedure of this regulator is included in detail. An efficient means of providing a regulated DC voltage to a load, when a noilregulated DC voltage is applied, is to cause alternate on and off series switching to permit a constant amount of energy to be delivered to the loatl regardless of the input voltage. This applies only when the desired voltage is always less than the available DC voltage minimum. There are two basic types of “switching" regulators;

fixed frequency variable pulse width, or fixed pulse width variable frequency. Both types can be combined to form a third, i.e., variable pulse width variable frequency. This section concerns itself with a general approach to the design of a fixed frequency variable pulse width type of chopper for [tower levels from 1 to 15 KW. Characteristics This chopper is convenient for situations where a fixed frequency set of drive signals is already available in the overall system, e.g., when a fixed frequency in¬ verter is being used as part of the system. The chopping frequency should be high enough to minimize the size of the output filter elements. It must he remembered that a certain period is required to l urn off an SCR, and this must not be a significant portion of the cycle time if a large regulating range is required. A convenient and use¬ ful frequency for the 40(1 11z inverter is 800 Hz,, which can be obtained by full wave rectification of the 400 Hz inverter drive pulses. A limitation on this type of chopper is that it cannot be completely unloaded, i.e., there is a minimum as well as a maxi¬ mum limitation on the load which must be present for proper operation of the chopper. This must be supplied In' means of a dissipative "dummy” load or, as in the case of the integration of this chopper and a static inverter to form a regulated conversion system, the no-load losses of the inverter. These aims can be satisfied by the use of this chopper in a regulated DC to 400 Hz inverter circuit. A wide range of regulation (1.7:1 range of input DC) has been demonstrated including no-load to full load and an output voltage adjustment range of 15%. A situation requiring careful packaging techniques arises when a large regulating range is required. The charging current (described in section S.5.2) becomes a high frequency, high current, semi-sinusoid which can cause spurious drive pulses in other circuits. The above system has proven itself in the low to medium range of chopper-inverter combinations. 8.5.2 Chopper Operation (Refer to Figure 8-32). Two paths are presented for current when SCR, is turned on. The principal path is through I,2 into C3 and the load. The secondary path is used to establish the necessary conditions for turn-off. An I-i, R,. Ci, CR, path is presented to the approximate step function of voltage applied when SORi turns on. The resonant frequency of L,Ci is high, compared to the operating frequency. C| is charged to nearly double the line voltage, i.e., 2K, and prevented from discharging by diode CR,. After a lime determined by the regulator control system, SCR? is fired. Again two paths present themselves for current flow from ( V One through l.i, Ri, SORi, (A and SCR-; the other through I.,, Rlt ],2, the load, C.i and SCR*. Since Ci is charged to 2K, SCRi becomes back biased by F.. SCRi has been conducting forward current until this time and, therefore, continues to be a low impedance until its junctions recover, at which time it blocks reverse voltage. After a time, dependent on the load impedance, SCRi is required to support forward voltage reapplied at a relatively slow time rate, again a function of the load impedance. When C'i is dis¬ charged, the inductor, L«, forces the current to continue into the load resistor through the free wheeling diode CR-, completing the cycle. A detailed account of the chopper operation follows. In this discussion Lj is as¬ sumed to be wound in part or entirely on a saturating magnetic core to aid in the recovery of CRi and to prevent undesirable commutation of SCRi during the recovery time of CRi due to an attempted reversal of the current. This may not be necessary in many circuits, but is included in this discussion for completeness. Tile effect of this saturating inductor is to produce time delays at intervals through¬ out the operation. These time delays should be omitted if the saturating inductor is not included. SCR, is driven into conduction, presenting a steep wave front to the

Lj

remainder of the circuit. Initially, the saturating core presents a very large induct¬ ance and supports the voltage since it has been saturated in the reverse direction by the free wheeling diode current mentioned above and described below. When saturation occurs, resonant charging of the capacitor, Ci, follows. The voltage on the inductor, Li, goes, co-sinusoidally, from + E to — E as the current is sinusoidal for the first half cycle. At this time, the capacitor is fully charged. Since diodes are not ideal, some time is required to achieve the reverse blocking characteristic and, therefore, CRj will allow reverse current flow until recovered. When the current reverses in the resonant circuit, the nonsaturating part of U presents a large in¬ ductance which, in turn, controls the reverse current until CRi recovers. When the diode recovers, a time less than that required to saturate Li, the current is rapidly decreased in Li, causing the voltage across I-i to change rapidly.

Ri dissipates

the energy during this transient, after which the voltage on Li goes to zero. When the voltage across the free wheeling diodes is changed from 2E to a reduced value, i.e., when the charging diode recovers, the voltage rapidly falls to E, as the voltage rises across the turn-off SCR, SCR). While this has been happening, load current has been flowing through SCRi and U into C> and the load. This is the completion of the turn-on transient of the chopper. At a time after the completion of this tran¬ sient (for proper operation, the entire transient must be completed), SCR; is fired by the regulator control circuit. The turn-off path is from C, through Li, Ri, SCRi, C, and SCRj. The saturating part of Li is at its remnant flux level in the opposite direction to the desired direction of current flow. It saturates and permits voltage, E, to be placed across l-i and SCRi since Ci is charged to about 2E and C; is charged to E. SCRi maintains a low voltage (approximately 1 volt) while permitting current to flow in the reverse direction until the junctions reform. I.i is required to limit this peak reverse current to a value below the rated average forward current of the SCR for maximum reliability. When the junction of SCRi reforms, the SCR will block reverse voltage, but it is not yet ready to support forward voltage. The effect thus far is that an amount of charge necessary to turn off SCRi has been rapidly removed from Ci, causing a rapid reduction in its voltage in a relatively short time. The voltage across ('- increases slightly, but since Cj is approximately 150 times Ci, this increase is insignificant and for a very short time. Ci must now discharge through l.i, Ri, L- into the load anil Cj and through SCRj. To complete SCRi turn-off it is necessary that the time required for Ci to discharge to E after SCRi blocks in the reverse direction, be greater t han t5, as specified by the manufacturer, as indicated in Figure 8-33. It is also necessary that the time rate of reapplied forward voltage not exceed the reapplied dv/dt rating which is also specified. The load and Lj are the most influential of the components affecting the fulfillment of these requirements. It should be noted that the load has a two-fold effect on this situation since it affects 8-34

the slope of the reapplied voltage and the point at which it starts. The latter because it takes more charge out of Ci to commutate a heavy current in SCRi than a light one, thus reducing the voltage further than in the light load case. The current through 1,2 begins to decrease when the voltage across L2 becomes negative, due to the dis¬ charge of Ci and the constant voltage on (V The voltage across the free wheeling diode, CR,. becomes 2E tit the start of the SCRi commutation sequence and de¬ creases until Ci becomes discharged. L; is of such an inductance, i.c., greater than critical value, so that the voltage developed across it when the current attempts to decrease to zero is such to force current to flow from Cj through CRj, l-i, Ri, and I.1 and not decrease to zero during any portion of the cycle. Hence the core of l.i is saturated in a direction to oppose the voltage wave front when SCRi is fired to initiate the succeeding cycle. 8.5.3 Design Method The most important passive component in the chopper is the commutating capac¬ itor, Ci, in Figure 8-32. The functions performed by this capacitor are: 1. Supply load current during switching 2. Reverse bins SCRi until it is able to support forward voltage 3. Control the reapplicalion of the forward voltage on SCRi at a time rate less than the rated dv/dt for the device. It is reasonable to assume that l-i is a large inductor which maintains a constant current during discharge (actually, in a practical case, there is a decrease in this current during part of the olT-time of SCRi, but AI is small for the period of com¬ mutation). The capacitor is thus required to supply this constant current until it is discharged, at which lime the inductor, 1.2, continues the current How through CR2 and the load. Then if the maximum peak load current is known, it becomes relatively easy to determine a value of Ci to accomplish this purpose. However, one significant feature lias been neglected In this discussion. Ifefore SCRi recovers its reverse blocking capability, a large reverse current may flow. It is desirable, for quick recovery, to have some reverse current flow, reforming the end junctions, but this peak current should be restricted to some low value, e.g., the forward rated current as an experimental rule, to insure maximum reliability against failure. This function (as mentioned above) is provided by Li. Thus, for a short time a large dis¬ charge of Ci occurs. This has the effect of reducing the charge on Ci by an amount, V], as indicated in Figure 8-33. Hot li discharge opera!ions, (the constant current dis¬ charge to provide turn-off time, and the fast discharge to provide reverse recovery), must be taken into consideration when calculating Ci. The fundamental capacitor voltage relationship is:

rT

v=l/CI

idt, which is, for

8-35

constant current V = (I (')At. If we assume that a‘11 the discharges arc- constant current, we may make the following calculations. The initial discharge during the time interval, 11, is given by Vi = [(1 + Irev)/Ci] ti. Although constant current is not the true situation in this case, this approximation has been experimentally verified. Then the remaining discharge is represented by: 2E — Y’i = (I/Ci)(ts). If the slope of the discharge line from t = 0 to ta is considered, it can be readily seen that ti-ta E

t, =E—V,

since they both represent the slo|>e of the same line. It is now possible to write _Eta_

E-[‘

+ 'REv)j

C,=

t,

I REvij

which yields the following quadratic equation in C.

CV

(I + Irev) b+^ I>2

„ . (I + Irev)1 tl!+I(l + lREv) ti ts

„

C, +-21?

°

This has the solutions

f 1T I rev) tl+jltj

+

J

|.

[(I + lREv)tl+^l>5j

-pi |ll+lREv)Sl|S + I(lREv)tlll

It is necessary to know the input voltage at the highest current condition (Emi„), the peak current at the highest current condition (1), and the reverse recovery time ti. The turn-off time t2 and Irev arc a function of the selected device. It is also neces¬ sary that the tlv/dt at turn off,

Emin

.. .

.

•-- < the reapplied voltage rating. tj —tj The input voltage (E) is given, along with the output power rating of the regu¬ lator. The peak current may be approximated by the output power divided by the output voltage

I.MAX =

Pout'S \ OUT

(!) This equation is true only for the chopper if an infinite choke is used as I.j. The equation should include a ‘weighting factor s, which can he represented by

K= I

Ls

where i.c is the critical inductance

cit maximum output current. This may he neglected in cases where Li is determined from no-load conditions which require much larger [... than the full-load conditions. The calculation of critical value of is covered at the conclusion of this section.

The average voltage output of the chopper as applied to the filter l.j, t 3 can be determined from the following analysis. Figure 8-34 indicates the wave shape applied to this filter as a function of SCKi conduction angle f«) and the discharge slope (m). First consider the discharge portion. We may write, in general, that v = mt+b. For 8-36

IV1 —

1

Voltage

I

a

2E

0

tj

Time —— T

FIG. 8-34—Voltnfto Applied to Output Filter

the condition of I =0, v = 2K —Vi, and then b = 2K —W The discharge time (la from previous consideration) can be determined from 0 = mla +2E —Vi;

thust, = ^zY, —m The contluetion lime «, is thus restricted such that 2j*_y *ir/« the maxi¬ mum value of the saturated part: of L,. Clearly « must be greater than 0 and, in fact, must be a finite time. The minimum « can be related to the average output voltage and the least value of output current Imin. First assume that « = 0 and Vi = 0. Then to a first approximation C, VAv=

2tImin

(4

Emax).

This determines the minimum possible current. Since terms have been neglected in the above expression for VAv there is always a positive value of « which can be determined, using the complete relationship as written below solved for «.

a=i [Vav_S(4E2—'4EV.+Vi2j If «min >s determined, one method permits a calculation of a value of l-iMAX since

and 1.; *max“’12 E2 >2

= >’21

where

Ei

+ J'22

(3) (4)

1-2

vn, and y22 are the short circuit admittances of a four-

terminal network It is also readily seen that l2 = — K2yL

(5)

where yL is the load admittance. From equations (4) and (5) the voltage transfer ratio can be shown that:

E2=

>12

(6)

Ei ya+yL The above equation (6) shows the voltage transfer function in general to be a function of the load admittance. The synthesis method employed in a synthesis of a two terminal pair ladder net¬ work is based upon the following two observations: 1. In a purely reactive ladder network, the poles of y,8 are simple. Moreover, y22 and y,, possess these same poles 2. Every zero of the transfer admittance yi2 of a reactive ladder network, must be either a zero of a shunt clement or a pole of a series element Hence, the method consists (a) of appropriately identifying the form of the y22 and y,2 functions, (b) synthesizing the susccptance y22 as a ladder network, but in such a way that the zeros of yi2 are produced.

*

It can be shown that for a function to be realizable as a reactance (or susccptance) it must be expressable as a Hurwitz polvnominal. For reactive elements:

KS (S2W) (S’+y,2) ■ ■ ■ ■

(7)

H- (SW)(S2W) .... where U1-1—SCR Voltage Division with or without Divider Resistors

A general equation for determining this unbalance is: Percent imbalance

N -

100

1

I Min + Ir)

1+ [N—1]

I Max + lit)

N

-number of devices in series

I Ml

= leakage current of SCR having lowest leakage

I Max = leakage current of SCR having highest (usually rated) leakage Ir

“Current flowing through shunting resistor with rated SCR voltage across resistor. All currents should be expressed in the same units.

For our example Percent imbalance

100

2 : 5 -i- is

1 + (2 - 1)

9-4

;i5 + is.

-1

-l

i+H =

-1 = 1.2-1

=

1.67

.2

We also want to know how much voltage a series string of SCR's will block. This can be found by multiplying the denominator of the equation by the rated peak repetitive voltage of the devices being used. In the example the denominator was 1.67 rated voltage of SCR string = 1500 x 1.67 = 2500 V. The equations are for the worst case; they both assume that only one SCR has minimum leakage and all the remaining SCR’s have maximum leakage. 9.0.5 Practical Voltage Dividing Networks The circuit indicated in Figure 9-5a was devised by early experimenters to alleviate some of the problems associated with many series devices for HVDC. This circuit uses a very low resistance value in the R-C circuit so that voltage imbalances will not result when hundreds of devices are seriesed. To alleviate the turn on problems in such a large series string, an anode reactor was used. This reactor is of the saturable core type to minimize the delay time variation in devices. In addition, it controls the turn-on wave form by shaping the discharge current from the R-C network and "reflected” bushing capacitance.

FIG. 9-5a—Early Prototype Connection for liVDG Strings

FIG. 9-5b—An Improved Connection for IIVDC Strings

This combination of a suitable R-C value and a delay reactor was of great help to the original experimenters. Successful operation was achieved by parallel firing the devices with a 1 ampere signal at 1 /isec rise time via special gating circuitry at a bias voltage difference of 200 Kv. Improved circuit techniques can bring about further simplicity to the seriesing problem. For example, the circuit shown in Figure 9-5b portrays one of a number of connections that permit removal of the bulky anode reactors. In such a circuit the designer should set the Ci capacitance value and the gating characteristics with care. The removal of the delay reactors dictates a high gate drive that will minimize the delay time variations from device to device. Failure to provide properly for wide delay times as experienced in low amplitude skip gate firing will bring about device destruction.

Novel circuitry such as this allowed series packaging of many1 devices using the compression bowled pucks or Pow-R-Discs. Gating requirements are as those de¬ scribed for Figure 9-5a and are easily achieved. 9.0.6 Power Dissipation in Shunt and Series Resistors After the ohmic value of the shunting resistors has been determined, the power dissipation must be calculated. For phase control applications the maximum power dissipation occurs at zero conduction angle;

For square wave inverter chopper:

»1 EP2 t2 Rs

For sawtooth.

tl

Ep2

3t2

Rg

9.1 PARALLEL OPERATION Should an application require current capacity beyond that offered by existing controlled rectifiers, the required current can be achieved by' parallel operation. The waveform applied to the gates of units becomes an important factor in reliable operation. The uniform firing of all units in a parallel bank must be guaranteed. The gate signal must be applied for a sufficient duration to ensure build up of load current through the devices to a value of several times the maximum holding current of the devices. It is desirable to provide isolated gate drives in the form of square wave with a rise time of one microsecond or less. Sufficient gating can be achieved from a single stiff source. The variation of gate impedance must be swamped out through the insertion of resistance or a combination or resistance and capacitance. Further elaboration of gating requirements are discussed in Section 5.0. All controlled rectifiers of the same type do not have identical forward voltage characteristics and, therefore, tend to share current poorly, as illustrated in the bottom pairs of curves in Figure 9-0. It is, therefore, necessary to provide an ex¬ ternal means of forcing current within specification. Several techniques are avail¬ able to the design engineer to accomplish the desired results. Manufacturers will supply units with forward drops matched within bands of 50 millivolts over the desired operating current range. Care must be taken in equal¬ izing the temperature fluctuations and resistance and inductance in series with 9-6

FIG. 9-6—Imlmlnncc Currents in Parallel SCR Circuits

the controlled rectifiers. Matching will lie nullified should voltage imbalance be generated external to the device. Another consideration is the economics involved in replacing matched units. It may be difficult to replace faulted units in a bank of many units in parallel. Insertion of series resistance will increase the slope of the forward drop, ns shown by the upper pair of curves in Figure 9-0, decreasing the possible imbalance of current. This method provides current sharing under overload conditions as well as normal load conditions. It does, however, increase power dissipation and de¬ creases the efficiency anil regulation of the system. Whereas the power dissipation of the shunting resistors in series strings is usually small compared to the power being dissipated is in SCR the power in the series resistor can be very high. This follows because the series resistor carries the same RMS current as the thyristor and the high current levels are dictated by parallel operation. An equation to determine current imbalance is: % current imbalance

I

100 1 -I- (N - 1)

+ VR [Vptmnx) T

N

= number of devices in parallel

Vi-1,,,1,,1

= Minimum forward voltage drop at peak rated current

Viinmxi Vk

= Maximum forward voltage drop at peak rated current - resistive voltage drop of that part of the circuit common to only one SCR at peak rated current

This equation is for the worst case; it assumes that only one SCR is low Vv and all remaining SCR's have maximum V,.-. The most dependable method to provide current sharing is the use of balancing reactors as illustrated in Figures 9-7 and 9-.S. Briefly, should an unbalance in current through one cell exist, a counter e.m.f. is induced, tending to force down the in¬ creasing current and increase Che lower current. A state of equilibrium is thus reached. Should a controlled rectifier fire before a complimentary unit, c.m.f.'s are induced as described above; and the voltage across the unfired unit rises ap¬ preciably assisting rapid firing. Design details of a balancing reactor that is effective up to 100 amperes per device is shown in Figure 9-9. It is recommended that a high speed fuse be connected in series witli each parallel controlled rectifier, whichever method is used for current sharing. In addition current relays or similar sensing devices are recommended for the detection of a

9-7

FIG. 9-7—Current Itulnnce Using Reactors; Schematic Diagram of "Closed Chain" Circuit

FIG. 9-8—Current Ualnnce Using Reactors: Pictorial Representation of "Closed Chain" Circuit

fuse failure or an unfired controlled rectifier, unless sufficient parallel paths are included to allow for some becoming open-circuit. Spurious forward breakover must be prevented. If spurious forward breakover is riot prevented, there is a strong possibility that, in the event of an overvoltage, one SCR will breakover, thus having to carry the total load current for up to half a cycle. It is mainly to protect the controlled rectifiers against such occurences that individual fusing is recommended. The paralleling system to be used will be largely determined on economic grounds, but it is suggested that where more than a few parallel paths are required, reactors should prove to be the most satisfactory method. 9.2 FUSING The ability of a fuse to be current limiting is basically a balance between the geometry of the fuse link, the metallurgy of the link material and the characteristics of the filler surrounding the fusible element. By controlling these parameters and others, the ability of a fuse to open a circuit quickly (hence current limiting) can be

© CORE

438

B-B

A-A

FIG. 9-9—Design Data on 100 Ampere Blanclng Ronctor

evaluated. With the exception of dual-element fuses, the faster the fuse opens under short-circuit conditions the less will be the availability of any usable time lap in the overload region, hence fuses which open exceedingly fast should not be applied close to their ampere ratings since transient current surges may cause the fuse to open where a damaging outage would not be indicated. There are two basic phenomena involved when a fuse clears a fault which will vary with the changing of available short-circuit current. The time that it takes from the initiation of the fault until the fuse element melts and an arc is struck is called melting time. From the initiation of the arc until the arc has been extinguished is called arcing time. The summation of melting plus arcing time is known as total clearing time as shown in Figure 9-10. Where heavy short-circuits are available the geometry of the fuse link inherently controls the melting time. Heat is generated very quickly in the short-circuit strips and docs not have time to bleed off into the surrounding media, hence this heat remains essentially at the point where it is being developed and melts out the fuse 9-9

FIG. 9-10—Definition of Total Clearing Time of Fuse

element. Thus under heavy short-circuit conditions the amount of energy necessary to melt out the fuse link will remain substantially constant regardless of the avail¬ able short-circuil current. Under low overload conditions, that is a long time blow, heal is developed slowly and there is time for thermal conduction to take place wherein the heat developed by the fusible element bleeds ofl into the filler material, fuse mounting as well as the external circuit. Therefore, the thermal capacity of the system must be taken into consideration when establishing the fuse rating.

Available Short Circuit "8"

_ Available Short \

Circuit "A”

FIG. 9-11—Curves Illustrating Decreasing Fuse Melting Time with Increasing Available Fault Current

Under heavy short-circuit conditions where melting energy is substantially con¬ stant, the higher the available fault current, the sooner the necessary energy will he obtained to melt out. the fuse link. On that basis, melting time-current curves, that is the available fault current versus melting time, show the melting time de¬ creasing as the available fault current increases (Figure 9-11). For total clearing time curves under heavy short-circuit conditions the arcing time is added to the molting time, making the total clearing time and melting time curves divergent. The total clearing time curve and (he melting time curve would coincide for the long time blow. For instance, if a fuse were to open in two or three seconds, the addition of a quarter or half cycle of arcing (1/60 second on a 80 cycle basis) would have a negligible effect on the overall elapsed time as indicated in Figure 9-12.

ID

(E a:

Total Clearing Time

D ' Melting Tlmo

TIME IN SECONDS

FfG. 9-12—Curves of Fuse Clearing Time and Melting Time as a Function of Available Fault Current

9- 10

I ime-current curves for fuses can be plotted using prospective current and virl ual lime. This allows the fuse curves to be plotted easily for times shorter than .01 second (approximately cycle). By definition the prospective current is the current that would flow in a circuit if no protection were in the circuit and the available fault current was allowed to reach its natural maximum values controlled only by the circuit constants (Figure 9-13). Employing a curve of this type the prospective current is plotted on a symmetrical rms basis, Under heavy short-circuit conditions, that is in the current limiting range, a fuse tested would not allow the available fault current to build up to its natural maximum values and an oscillogram showing the trace of current would essentially be triangular with the apex of the triangle being the maximum peak let-thru current allowed by the fuse and the total elapsed clearing time would be shown by the length of the triangle base as shown in Figure 9-14. Copper Bar

Short

(No Fuso)

Circuit Sourco’

•Only Impodonco of System Controls Available Fault (Prospective Current) Short Circuit Current Time

FIG. 9-13—Definition of Prospective Current

Fuso Limits Build Up Of Fault Current

Peak Lot Thru ^ Curront /

Total Clearing Time

FIG. 9-14—Curve Defining Peak Lot-Thru Curront and Total Fuse Clearing Time

In plotting a prospective current versus virtual time curve as in Figure 9-15, for the long time blows the prospective current would be the actual rms symmetrical quantity of current flowing which could be measured with an ammeter. (This meets the requirements since only the circuit parameters are limiting the available fault current which may flow for several cycles or several seconds depending upon the magnitude of the current.) The time that it takes this overload current to blow can be recorded and we will later see that this is not only the actual time but also the virtual time. Prospective

_

RMS Symmetrical Available Current

l2T = K (Actual)

— I2 Prospective * t

FIG. 9-15—Curve of Prospective Current versus Virtual Time

9-11

In effect the same data could be plotted for the long time blow if the prospective current scale were changed to energy and shown as I3t. This would be very confusing since normal applications of electrical equipment deal with current versus time not amperes5 seconds versus time, but the concept can be used to great advantage to allow the plot of current versus time wherein subcycle blows occur. Under the heavy short-circuit condition the small triangular shape of current shown on the oscillo¬ gram can be translated into an amperes5 second

form. From

the oscillogram

itself it would be difficult to ascertain the available fault current on the system since the fuse had cut it off long before the maximum available fault current could flow. In testing fuses, from calibrations on the test station, the symmetrical rms current the test station has been set to deliver is accurately known. This can be then used to translate useful data on a prospective current versus virtual time plot. The translation is thus: If we assume that the available symmetrical short-circuit current on an rms basis flows instantaneously, as soon as the fault is energized, we can then determine bow long this fault current would have to flow to produce the same amount of energy as actually occurred when the fuse blew. In other words, the correlation is between a square wave pulse of current whose l3t value is equal to the l't of the triangular trace on the oscillogram. The symmetrical rms value of fault current that the station was set to deliver is called prospective current. The length of time that this prospective current must flow to produce the same energy as the actual blow is called virtual time. Utilizing this concept the correlation of prospective current and virtual time on the long blows is also acceptable since the prospective current is the actual current and the virtual time is the actual time. When a fuse opens the circuit before the peak current of the first major loop is reached, it is said to be current limiting. As the available fault currents increase the maximum peak current that can flow through the system also increases. Since the I5 factor appears both in the thermal as well as the magnetic consideration, the ability of the fuse to prevent a large build-up of current can he an important param¬ eter, especially when the problem involves the protection of equipment that has limited thermal capacity or is lightly braced. Several basic considerations should he remembered when applying fuses. 1. Always use a fuse with an l5t smaller than the device being protected. 2. Co-ordinate the fuse voltage with the circuit voltage. If a 250 volt fuse is used in a 600 V circuit, the voltage will he able to sustain the arc until current zero, drastically increasing I5t. If a 600 V fuse is used in a 250 V circuit the arc voltage will he greater than 600 V and may cause voltage failures of other semicon¬ ductors in the same circuit. 9.3 SOURCES OE TRANSIENT VOLTAGES Externally generated transient voltages and currents must he included in con¬ sidering which device to use for a particular application. Figure 9-17 shows several examples of common sources of transient voltages. Figure 9-l7a shows an example of the voltage generated by the decaying flux in a transformer core when a breaker in the primary is opened. Moving the contact to secondary of the transformer would eliminate this problem. In Figure 9-17b the initial magnetizing current of the primary must be allowed to flow in the secondary. The transient can be suppressed by an R-C network across the secondary or by switching the secondary. Figure 9-17c shows how the primary voltage can couple across the interwinding capacitance. A capacitor across the secondary will cause voltage division which will suppress this transient.

9-12

B

AVAILABLE

SHORT-CIRCUIT CURRENT-

ASYMMETRICAL RMS AMPERES (1.4 x SYMMETRICAL IN FIRST HALF

CYCLE)

FIG. 9-16—Current Limiting Effect Chari: Peak Lot-Thru Current versus Available Short-Circuit Current

Figure 9-17ci demonstrates how the inductive kick of parallel circuits can affect semiconductors controlled by a common switch. This example demonstrates the advisability of placing the switch as close to the semiconductors as practicable. Figure 9-17c shows the transient generated by load switching. This transient can be suppressed by an R-C network across the a-c terminals of the bridge. Figure 9-17f shows the resonant charging of a capacitor by a current carrying inductor and the resultant transient voltage. Voltage variable resistors such as Zener diode and Voltrap surge suppressor across the inductor and/or capacitor can limit these voltages. Figure 9-l7g demonstrates how the counter emf of an active (motor) load can cause high stress on the SCR. A voltage variable resistor can be used across the motor. In Figure 9-17h a three phase, full wave bridge converter is shown with the equiv¬ alent circuit of the R-C snubber networks. The amount of overshoot is a function of the values of R and C in the snubber network and is usually a compromise of several circuit parameters. 9.4 MEASUREMENT TECHNIQUES Two basic parameters that must be considered in applying SCR’s are dv/dt and di/dt. Typical device ratings are 300 V/jis and 100 A/gs. To evaluate circuits that 9- 13

FIG. 9- 17(a)—Voltage Transient Due to Interruption of Transformer Magnetiz¬ ing current

EIG. 9-l7(b)—Voltage Transient Due to Energizing Transformer Primary.

FIG. ''-17(c)—Voltage Transient Due to Energizing Step-Down Transformers.

EIG. 9-17(d)—Voltage Transient Due to Switching Rectifier with Inductive Load Across Input.

FIG. 9-17(e)—'Voltage Transient Due to Load Switching.

FIG. 9-17(0—'Voltage Transient Due to Dropping Load from LCl-Type Filter with High L/C Ratio.

n

SHUNT fi£L0

FIG. 9-17(g)—Overvoltage Due to Regenerative Load.

9-14

n FIG. 9-17b—Cyclical Voltage Transients Due to R-l.-C Networks in Recovery Paths

FIG. 9-17—Typical Transient Producing Circuits and Conditions In Thyristor Applications

have voltage and current rates of change of this magnitude requires sophisticated instrumentation techniques. It is very important to use oscilloscopes, amplifiers, probes and shunts that have the rise time and bandwidths necessary to observe these waveforms. Oscilloscope rise times should be less than 100 nanoseconds. Oscilloscope manufacturers sell voltage and low current probes that they recommend for their equipment. For high current measurements transformers such as those sold by Pearson Electronics, Inc. and Power Designs give good results. When current with a large d-c component must be, viewed a non-inductive, current viewing resistor must be used, The frequency range should extend beyond 100 ml lz. 9.5 OVERVOLTAGE PROTECTION TECHNIQUES Overvoltage may come from various sources such as lighting surges, switching transients from elsewhere in the power system, switching transients from within the SCR equipment itself, and regenerative voltages to name some of the more obvious sources. Controlled rectifiers are susceptible to overvoltages of either polarity, and tran¬ sient suppression techniques must be employed to prevent device destruction. Con¬ ventional transient techniques such as RC networks, non-linear resistors, and selenium voltage suppressors appear to be adequate for most transients. VOLTRAPS are available with RMS ratings ranging from .10 volts to 480 volts in 30-volts steps connected in common circuit configurations. The clamping voltage at. rated discharge currents is approximately 2.5 times the RMS voltage rating. The most common and troublesome case of transient voltage is the interruption of transformer magnetizing current with no load on the equipment. The following relation will give a conservative value for the current rating of device such as a VOLTRAP: Discharge amperes = 0.7 x (secondary full-load AC amperes) x the % magnetizing current. In many systems, it would he difficult to select a VOLTRAP with a clamping voltage sufficiently below the voltage rating of the configuration of controlled rec¬ tifiers. In such applications, basic RC transient suppression lias been found sufficient. Considerable experience with overvoltage protection has demonstrated that a voltage safety factor generally be used. The value of this safety factor should be governed by the magnitude and duration of the system transients and the degree of control exercised over the transients. No specific value of safety factor can be recommended because of the wide variety of systems and applications in which the SCR is applied.

9.5.1 RC Surge Suppression Networks If the load cannot absorb transient energy (because, for example, it is inductive or can be disconnected) then some kind of surge suppressor should be used. A network of proven worth is shown in Figure 9-18.

FIG. 9-18—Network with Surge Suppressor

The basic transient suppressor is C and K, and the selection of the components is discussed below. The remaining components in Figure 9-18 arc optional refine¬ ments. The rectifier serves to reduce ripple current through C, and R2 discharges C for safety reasons after the rectifier is de-energized. The rectifier should be chosen to pass the initial inrush current when C is charged, and to withstand the peakload voltage when the rectifier is switched off. The resistor R2 is commonly chosen so R2C presents a two-second time constant. 9.5.1.1 BASIC QUALIFICATION’S (1) A series RC network should be connected either from line to line or line to neutral of a three-phase system. In single-phase, connect across secondary of transformer. (2) In very high voltage applications where external stack shunting capacitors are used, transformer secondary suppression may not be required. (3) Recommendations are based on maximum system percent impedance of 25%. 9.5.1.2 CAPACITY CALCULATIONS

(1)

(19 va) (60) ' v,„„-

microfarads

( f )

f=supply line frequency (a) Single-phase va«= total transformer va capacity Vrm, = secondary rnts voltage across which network is connected (b) Polyphase “Y” secondary with networks connected line to neutral total transformer va

Vil"-TTno. ot phases Vr,n. = line-to-neutral rnts voltage (c) Three-phase system with networks connected line-to-line total transformer va

V„„, = line-to-line rnts voltage (d) Where va of transformer is not specified, use: (1) For three-phase with networks connected line-to-line

9- 16

c _ 10 vv„. (00)

vrm82

(f)

where: Wrm5 = line-to-line rms volts ^'jc = \'dc I,|c (2) For single-phase with networks connected across secondary winding

c

15Wdc (00) Vrll„2

(f)

9.5.1.3 CAPACITOR VOLTAGE RATINGS (1) General Oil or Askarel filled capacitors should be used. (Inertcen and Pyranol are Wcstinghouse and G. E. trade names for Askarel.) (2) Capacitors are usually rated in WVDC (working volts DC). For these applications: WVDC > 3 x Vtm, at f < 400 cps. 9.5.1.4 RESISTOR WATTAGE RATINGS (1) K =s 5

except where wattage becomes unpractically largo. In this case, R Idc

may be reduced to not less than to r_Vdc Idc (2) Wattage Rating of R P„„ > 5 IRC2 R where: Irc-V,™, (2irfC) where C is in farads: f“supply line frequency 9.5.2. “Crowbar” Transient Protection Circuit A circuit which has been found useful to protect against voltage transients is shown in Figure 9-1!) .Two SCR’s are connected in opposing polarity across the power line as "crowbars.” In normal operation, they have no effect on the circuit. How ever, if a voltage transient in excess of the scries shockley diode voltage should occur, gate current is supplied to that SCR which is blocking forward voltage at that instant by means of two of the diodes. This SCR then fires and remains broken over for the remainder of the half-cycle, during which time, the output voltage is reduced to a low value by the line impedance. The speed of operation is limited only by the turn-on time of the SCR’s which is typically the order of 1 to 3 microseconds.

FIG. 9-19—“Crowbar” Transient Protection Circuit

9- 17

•>.5.3 Capacitor Transient Protection Circuit Another transient protection circuit is illustrated in Figure 11-20. In this circuit a capacitor is charged to the peak value of the sinusoidal line voltage by the recti¬ fier bridge. In normal operation the capacitor "floats" at this voltage, requiring only a slight charging current pulse each half-cycle to compensate for the bleeder current. However, it presents a low impedance to voltage transients whose ampli¬ tude is appreciably higher than the normal sine wave peaks. Part of the energy in the transient is dissipated in the line impedance and limiting resistance. The remainder of the energy appears as a slightly higher stored charge in the capacitor. If the charging time constant is much greater than the duration of the transient, the increase in capacitor voltage is negligible. It should be noted that in contrast with the previous circuit, this circuit conducts only during the transient, instead of the remainder of the half-cycle.

FIG. 9-20—Capacitor Transient Protection Circuit

'). RFI SOURCES AND INTERFERENCE FROM SCR CIRCUITS The preceding sections have dealt primarily with those application problems that are primarily system coni rolled. There are a class of transients however, that can be traced to the switching device. These transients are the direct result of the switching speed of the thyristor involved. The power lines have distributed induc¬ tance and capacitance that is spatially controlled. When the thyristor "chops” the AC wave, the resulting wave front may give rise to spurious oscillations at the leading edges. These oscillations typically have a frequency range of about 100 kilo¬ hertz to approximately 2-3 megahertz. In the home this can cause interference to AM type receivers. Howevei, FM equipment such as FM receivers and TV will be unaffected by any radiated energy. For industrial systems this noise may be coupled into control circuitry via the power lines and may cause trouble with level and frequency dependant circuitry. The degree to which RFI is objectionable is dependent to a great deal on the system itself. In the home, radiated energy wherein the power lines become an antenna may become objectionable to AM reception. For the most pare however this type of noise is generally well below the level from fluorescent fixtures, precipitrons, and commutator noise from the brushes of sewing machine and sweeper motors. For the industrial system a similar situation exists in that telemetry etc. is generally above the noise frequencies from SCR circuits. The second type of noise level is probably of most concern, wherein the inter¬ ferences are brought to other equipment by the power connections. This conducted 9- 18

noise couples between power and communication lines in the same bus duct or is coupled into other sensitive equipment which may cause erratic performance. These conducted energies are a direct result of rectifier operation and the large har¬ monic currents in the phase controlled loads. Attempts to reduce these harmonics generally depend on commutation impedance of transformers or specific harmonic filters on the AC mains. Regulation characteristics generally negate the first ap¬ proach (except on small converters). Therefore the filter approach is the most com¬ mon solution to harmonic reduction on the AC mains. 9.6.1 Radiated RFI Interference Radiated Noise or RFI is an established problem that arose during the tube tech¬ nology. To a great extent, the solutions and approaches to the problem are similar. The initial problem is to isolate the undesirable noise from the equipments noise energy-bandwidth spectrum. As an example an extremely sensitive receiver instal¬ lation will involve a complex energy distribution for the frequency spectrum of interest. A second specification may allow 200 gv (across 3000) within the equip¬ ment involved. While another ill defined requirement would be that AM reception should not be impaired in the home. For either of these cases proper circuit layout or filter design can reduce the radiated RFI below that of the level of most power lines. The initial and most significant design approach to reducing the thyristor RFI level is to determine the filter cutoff frequency and rolloff characteristic that will achieve the desired noise level reduction. As the thyristor conducts into a resistive load the leading edge of the current wave has a frequency distribution that is con¬ tinuous and exhibits an amplitude characteristic that decreases at 20 db/decade. This puts most of the radiated noise in the low frequency range of commercial and I.F communications. Therefore, tiic design problem is to select the cutoff frequency and rolloff characteristic to bring the noise level within tolerable limits. A single element filter (inductor) may be used. However, as with rectifier harmonics, the size becomes critical. Therefore conventional filters, as shown in figure 9-21 are utilized.

FIG. 9-21—Considerations to Reduce RFI Levels for AM Broadcast Receivers

A second consideration for RFI reduction is the circuit layout. There arc several techniques the designer can try and then follow in production items. Some helpful aids are listed below. (1) Radiated RFI (a) Try to establish a good RF ground to bypass all the high frequency en¬ ergy. A few examples of good grounds are large metal enclosures or plates. A poor RF ground is the third wire or conduit box. in a house. (b) Try to maintain small currenl loops as these become antennas. (c) Be careful so that heat sink distributed capacitors do not form a tuned circuit with circuit inductance. (2) Conducted RFI (a) For thyristors, the best suppression of conducted RFI is an appropriate filter. (b) With wide ranges of loading care should be exercised as the l.-C filter stage Q will be excessive. This may cause current reversal and thyristor turn-off. If this occurs filter damping should be employed. (c) Try to maintain a lagging power factor for the system so sharp rising current waveforms do not occur. (d) Avoid power supply loops by running the leadsjn the same tray if possible and arrange other magnetic components at 90 relation. (e) For control circuitry utilizing shielded cable, care should be exercised as below 3 KHz the external magnetic field is the same as unshielded cable. This is due to ground current flowing in ground paths. Therefore noise in this frequency range may couple into sensitive circuitry. 9.6.2 Interference and Rectifier Harmonics Another major disturbance factor that arises from rectifier operation, and similar equipment, is the order and number of harmonics that are produced ns the line currents deviate front a sine wave. These harmonics may be coupled into sensitive communication circuits by electric and magnetic means and give rise to serious interference problems. As an illustration of the magnitude of this interference the amplitude and sensitivity of the receiver must be known. If we refer to Figures 9-22 and 9-23 the harmonic content of some familiar waveshapes and circuits arc depicted. (magnitodt)

Harmo*uc C< Wavwform

Nam

I _

.. [Zizl _r^ k

n

U

•

/

7^1

—

E *

•

■*- *

Fund

Snua»r

-A

■

1127X1

r

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Output

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(OX)

S' (75 5X1

6th

0

10X1

»l 1187V

181V

(0X1

(9X1

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f.'

(636X1

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(15 0X1

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171 2X1

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Output I63 6M

A. Harmonic Content of Familiar Current Waveforms.

9-20

Prr Unit Magnitude

Flfluro 9 22lbl. Delay Angle «. In Degtovt

li. Harmonic Content of A Symetrlcally Phase Delayed Sine Wave Current.

°

°

120

Component

Harmonic

Zero AC Irnpedence Si Voltage Symmetry, i.e. Solid Lino (AC Irnpedence, & Delayed \ Operation, i.e.

Dashed Line

\

j

11

1

led 1/5 i/7

°

60

T7T1

°

120

13

°

60

17

i7T3 TTT7

120

19

i7T9

23

25

T/23 1/25

Less than above and depends commutating inductance and delay angle

C. Line Harmonic Composition for A Three Phase Full Convertor. FIG. 9-22—Harmonic Content of Various Waveforms Found in Practical Convertor Circuits.

Disturbances in communication systems due to convertor harmonics may be classified into three groups; (1) Telegraph circuits (2) Signal circuits (3) Telephone circuits

S 300Hz £ 300 Hz 200 Hz-4 KHz

Of these the telephone circuits are the most important as the small line currents represent speech intelligence that is easily masked, garbled or rendered useless by induced harmonic energy. The immediate concern in reducing the interference level is the frequency res|x>nse of the telephone receiver and the human ear. The ear is the most sensitive of the 9-21

70 r

PERCENTAGE RIPPLE OF MAX VOC

Toial ripple (up to 24ih har I

DELAY ANGLE

1.14

65.

HsO

Oil (Transformer) 285. Air (S.T.P.) Thermal Grease

= 740.

.496

1G30.

3.2 x 10"‘

5.63

.0361 .0321 = 4.3 x 10"’

60.

(a) Figures given are believed to be suitable working values, but for precise calcula¬ tions one should check the manufacturer's data for a specific material and tem¬ perature. (b) Interpolated for 125°C from Manufacturing data. (c) Temperature range 20-200°C (d) Temperature range 20-300°C (e) Properties vary to twice given values depending on treatment; best properties occur after solution treatment, cold working >80%, and precipitation harden¬ ing. (f) Temperature range 20-100°C (g) at 20°C (h) Temperature range 80-400’C (i)

Temperature range 20-G50°C

(j)

Temperature range 25-200°C

* For a more complete listing, refer to the Design Data in Chapter 12.0.

10-5

where t| is the rate of heat transfer, watts hc is the coefficient of convective heat transfer, watts/ft.2-°C. As is the surface area, ft.2 ts is the temperature difference between the heated surface and the main fluid stream, °C. The value of the heat transfer coefficient, he. is influenced by many factors, in¬ cluding the properties of the fluid such as viscosity, density, etc., and the flow conditions, surface characteristics and geometry of the parts as well.

10.3 GENERAL THERMAL DESIGN DATA FOR SCR THYRISTORS This section is intended to aid the designer who is involved in a complete thermal design. Table 10.1 gives data for materials used in the design of encapsulations and heat sinks. Table 10.2 gives some typical dielectric strengths for the common elec¬ trical insulations. These values have been compiled and/or calculated from various sources and converted into the “hybrid” units,

TABLE 10.2 TYPICAL DIELECTRIC STRENGTHS OF BASIC INSULATION MATERIALS* Dielectric Constant (Volts/Mil) 1,800

Insulating Material M ica Transformer Oil

2,000

65 250 130 450

Air (at Std. T and P) Alumina Glass (hard) TFE Fluorocarbons Steatite

200

Silicone Elastomers

350 400 450

Epoxies Thermal Grease (Silicone-Metal Oxide)

* For a more complete listing, refer to the design data in Chapter 12.0. These values can vary greatly within a class of materials and are strongly influ¬ enced by surface conditions and dimensions. Glass varies over a wide range, even for one type, but it is still suitable for various electronic glass-to-mctal seals. An example is an eyelet type of seal used for a pin connector which one manufacturer rates at 200 volts in air with a 30 mil creepage distance across the glass. This amounts to approximately 7 volts/mil for glazed ceramic-to-metal seals in air. In transformer oil, which is virtually devoid of moisture or ionic substances, the value could be much higher. In referring to Table 10.2, it becomes obvious that these applications are "creeplimited” well below the dielectric strength of the material. In fact, the highest voltage stress levels appear across the device junctions (in a controlled atmosphere). In practical applications, the “conductive” deposits across the seal, or the strike potential of some sink geometry, may severely restrict these ratings. Therefore, the designer is cautioned to exercise good engineering practice in sink geometry and control conductive deposits via air flow, device positioning and regular preventative maintenance in “dirty” atmospheres. 10-6

10.4 MEASURING TECHNIQUES Heat flux densities are so high in SCR thyristors that manufacturers exercise great care to obtain accurate data and control on their thermal parameters. Signifi¬ cant temperature differences may occur even in thick copper sections. Junction tem¬ peratures are difficult to measure directly. Therefore appropriate techniques to assure these ratings had to be generated.

10.4.1 Thermocouple Practices The thermocouple is the most practical sensor for temperature measurements on SCR's. It is simple, rugged, small and has good accuracy. However, proper measure¬ ment techniques must be used to realize the thermocouple's advantages. In the operating temperature range of SCR's, the coppcr-constantin thermocouple is the best choice. A suitable wire size is No. 30 gage (0.010 inch diameter). This is small enough that a negligible amount of heat is transferred through the thermocouple leads from the surface being measured. The wire may also be purchased as twin lead insulated pair for improved accuracy. The thermocouple junction must be carefully made by brazing or soldering so the "bead" is well defined and of minimum size. Arc welding can be used to form a bead. The procedure is to touch the twisted wires to a carbon electrode while holding the wires near the ends with an alligator clip which is connected to a power supply capable of producing the weld with a single spark. Continuous currents should be avoided so the thermocouple leads tire not overheated during the coupling operation. In operation, bare wires must not be twisted together other than at the couple bead, because any contact between the wires constitutes a new thermocouple junction. This will introduce serious metering errors. The thermocouple junction should have good thermal contact with the bottom of the measuring hole. In the case of a deep hole this can be achieved cither by apply¬ ing mechanical force to the wires or by coating the junction with a cement or a thermally conductive compound. But, while achieving this firm contact at the bottom of the hole, it is also important to see that the leads retain their insulation up to the thermocouple junction. The best readout instrument for the thermocouples is the null-balancing potenti¬ ometer with cold-junction compensation. Moving-coil millivoltmeter instruments are inconvenient as they must be calibrated for lead length. An ideal instrument is a null-balancing type that incorporates automatic servo self-balancing and is di¬ rectly calibrated in temperature. In most instances, it is best to use an isolation transformer to supply power to the measuring instrument if it is not battery-powered. This prevents damage to the instrument due to leakage currents from the SCR power circuit and obtains more accurate readings. For an abbreviated listing of instruments refer to Table 10.3.

10.4.2 Measuring Coolant Flow Water flow can easily be measured by a simple flowmeter available from several manufacturers. It is a little more difficult to measure air flow through air-cooled heat sinks. Several techniques exist to measure air flow, the most common of which is the hot wire velomcter. Readings are taken on the downstream side somewhere near the center of the stream. If the flow is not uniform, the duct area should be sectioned into smaller areas and a mean value calculated to determine the average flow. The velometer is a refinement of the impact tube principle, which, in a more ac¬ curate form becomes the pitot tube. The pitot tube is used with an inclined tube manometer which permits the user to determine the velocity of an air stream in different regions so an actual velocity distribution plot may be generated for the duct. However, this technique is limited to flow rates of 500 LFM or greater.

An accurate means of determining the volume flow rate is by using a metering orifice. By using the correct size orifice, nearly any flow rate can be accurately measured. Complete information on these basic instruments can be found in the Mechanical Engineer's Handbook4 or nearly any thermodynamics text. For an abbreviated listing of instruments refer to Table 10.3.

10.4.3 Testing Procedure The most difficult problem in evaluating Re is the testing to determine Tj for the calculation of AT and thus Re.

TABLE 10.3 ABBREVIATED LISTING OF INSTRUMENTATION FOR _ MEASURING THERMAL PARAMETERS OF SCR’s. Temperature Indicators Instrument Description Leeds & Northrup Speedomax H — Potentiometric, Model R Indicator

self-balancing,

usually

0-

200°C range with a Cu-Const. thermocouple. Accuracy is ±0.3%

United Systems Corporation Model 564 Digital Thermometer

High input impedance servo-balancing me¬ chanical

digital

readout.

Has

two

ranges

—200.0° to 000.0°C and 000.0° to 400.0°C with a Cu-Const. thermocouple. Overall in¬ strument accuracy is ± 1.5°C Dctccto Temp paint from W. H. — are useful for indicating a maximum tempera¬ Brady Co. or Tempilaq from

ture excursion when it is difficult or undesir¬

the Tcmpil Corp.

able to use a thermocouple or other sensor requiring lead wires.

Measuring Coolant Flow Air Alnor Velometer—Relatively

low cost but pressure sensing jets are large and

difficult to position. Air flow is disturbed.

Alnor Thermo-Anemometer, Type 8500—Uses

hot wire principle. Has 10-300

and 100-3000 PPM ±2 FPM or ±3% (larger of) within limits of +20°F and 150°F. Probe is only ]4 inch diameter and permits more specific points of measurement. For increased accuracy and smaller probe configuration, but at substantially more cost, the hot-wire instruments from Datemetrics Division of CGS Scientific Cor¬ poration should be considered.

Biran Anemometer—Types

A/1, A2, A/4—Used to measure air speed or

quantity of air (Lpjj) that is passing or leaving a known duct opening.

Liquids For water flow, tube and float indicators are available front Brooks Instrument Company, Inc.—Brooks Rotameters Fischer & Poeter Co.—FP Fiowrators Duyer Instruments, Inc.—Various models To facilitate the device evaluation, a procedure is needed wherein a dependable, temperature-sensitive parameter can be measured to accurately indicate the junction temperature. The most dependable method is to calibrate the device Vr against Tj at a very low power level. For this method, the SCR is first heated, either in an oven or with forward current and minimum cooling, until the device reaches temperature equilibrium. (Equilibrium is determined when a case thermocouple equals oven temperature, or stops increasing as is the case for power heat up.) Due to the low power levels, this case temperature represents Tj. Y( is then measured on an oscillo10-8

scope by pulsing (lie device with (lie calibrnting currcnl. After calibration, the thermal resistance evaluation begins by operating the SCR near rated current levels. This is done in a circuit that periodically drops the rated current to the calibrating current level for an evaluation of Vf. Simultaneously, the device is cooled so as to remove (lie heat and lower the case tempera!lire. Rated junction temperature is indicated by interrupting (be main current for about 1% of the lest cycle and measuring

Vf at

(he low calibration current level. When this

Vf value

agrees with

the calibrating voltage the thermal resistance may be evaluated using the device dissipation and the temperature difference (Tj=T test point). Other temperatures needed can be obtained directly with thermocouples, and P,lv,, is obtained from

Vf at

the main currcnl level. 10.5 THERMAL IMPEDANCE DATA Most of the thermal impedance data needed by the designer can be obtained direel ly from the technical dala sheets. However, it is also helpful to have some additional data tabulated for the different products and for certain application problems. The following tabulations are for that purpose. TABLE 10.4 THERMAL RESISTANCE DATA ON WESTINGIIOUSE SEMICONDUCTOR DEVICES

Type Number

Product Type Rectifier*

ThyrUtnn

Stud Size

IN 1311 Sent309, IMIWSnc* 110 ■102, INI 1 Ml A Hi'lien •I0U. 1N4587 Srfirn iN:«w) 7io, 720. ;;n IN 1011 Serif

.100-32 I0U-32 26-28 ■ 2.9-28 ..'175-2-1 -75-1(1 .75-10 76-10

ROOO K700 ;s:i 781 780

.75-10 .75-10 1.00" Ml*. Din. 3.0 s 3.11 plntu 1.73" MIR. Din. 25-28

201. 202. 203. SIN AS 1 Seri®. 2X1342 S..lf * 2XIM2A Scclc*

T ins Serif 2N 11*011 A JN 171*2 Senes 2NHIU. 2N41I7I Serif and Type* 250, 251. 2M-I ft 2. 251.1. 2606 A 2101-2 TS07 Serif TOOO. 2X.W4 Sun anil 1 vpe. 2161-2. 220. 2201-2. 2tt). 2005 A 2013 218, 2161-2 A 2(11 2248 273 Til20 ami Ty|K* 272 Type 228 Type 203 T700. Type* 270 ft 271 T720 and 'lypea 292-293

Torquu 1S0° conduction. (b) Select the device with maximum half-wave average exceeding the current requirement-

Westinghouse 201 —2N081.

(c) Refer to the data sheet ( I D 54-564) and find the power dissipated per device, and the maximum allowable stud temperature for this current condition. 50 t3-c,l

20

25

Mainnum power dissipation based on maximum lor* ward voltaue drop lor sinusoidal currant waveform.

t

Mailmum allowable stud lam para lure lor sinusoidal currant waveform.

= -- watts

= 90°C (d) Determine the sink plate size using PllVo & Rocs from Table 10.3. I rnrtpfmnx)

AT,., = F»vc Rocs = 22 x .25 AT„„ = 5.5°C 10-21

Tsini. »mx = 00-5.5 = 84,5T AT„.u{ml„, = S‘1.5°C—30°C = 54.5°C Refer lo Figures 10-0 (r> 10-11. Note that the 3 x 3 plates give a fi0°(' rise for 10 watts and can be eliminated. The next most economical design would utilize 5 \ 5 aluminum plates as per Figure 10-11. On Figure 10-11 a horizontal line is drawn through the >l°(

AT point. This line intersects the 5 x 5 x ) s plate

curve at 22.7 watts ami mat' be used for each device. I lowever, in slacking the plates llte tin efficiency sutlers, as illustrated on the second curve. The stacking curve indicates the "assembly" design would be inadequate on 5 x a x aluminum. Repeat the process, using Figure 10-10 and note that lie" stacked copper plates can accommodate the losses, (e) Assemble the bridge, using the practices explained in Figures 10-3, 10-1 ami Table 10.1. Verify your calculations anil design. 10.7 TYPICAL EXAMPLE USING EXTRUDED-SINK DESIGN Consider the circuit ami application illustrated below. Design the cooling system to allow the circuit to function properly ("

I0°C.

480 Volts ± 10% at 60 Hz.

Load

Shunt Motor I)clny Angle

Current

0°

300

1)0"

210

I. Determine SCR @0° Delay l„v„ = 3°°- 100 A @ 120° sq. wave

@90° Delay Iav„ = =1? = 70 A (,, 30°-Sine

30° 30L

u

JV

Obviously t lie 90° delay condition is more severe so that this becomes the l hernial criteria. Select the thyristor with average current capabilities matching the loath How¬ ever. care should be exercised in that the 70 amps is comprised of two 30° con¬ duction intervals. Therefore the power should be twice the P„VP at 35 A for 30° sine wave. This uses the lower, more representative value of P:,ve for the exact waveform. I he reason for this procedure is the device losses for a single 30° sine 10-22

pulse exceeds the losses of two 30° sine waves for the same average current. P„v,,=53 watts for the Type 2G0 at 30° and I„ve = 30 amps. Pnvrilo!)= Id5 watts

T„,c(rn,,x, = 360C 2. Select sink for natural convection cooling. ATc.a = 100 x Rocs where Rocs = .OS (Table 10.3) ATM=106 x.08 = 8.48°C T.ink =!>60C-8.48°C=87.520C AT„.„ = 1 T.iiilc — l'nmb = 87.52 — -I0°< AT,.„ = 47.52 (a 100 watts Refer (o Figure 10-0. Select the appropriate sink for 106 watts, a 0M x Hj£ x !) will dissipate 132 walls. However, the volume may be prohibitive. 3. Select a forced convection sink. a 4 x 4 x 4 sink will not accommodate 100 watts and must be fan-cooled at 100 walls, the AT is 75°C. Required AT reduction = 75—47.52 = 27.48 Rosa reduction = "^^ = .258

10.0 Refer to Figure 10-7 and note that .258 reduction in RttjA for a 4 x 4 x 4 sink is obtained with 140 LFM. This reduces the volume by 82%. 4. Free-Wheeling Diode For a passive R-L load the current in the free-wheeling diode is .05 l'-i..i. R|,. However, for motors, this value may lie considerably higher at stalled rotor conditions and small conduction angles. For these drives the converter current must be kept within RMS limits of the SCR’s. However, the diode current is s( ill a function of motor characteristics and must be sized for these particular condi¬ tions. For the purpose of this example, a suitable diode can be selected by choosing the rectifier with an RMS rating equivalent to the SCR. References /. BuShips, Department of Ike .Vary, "Design Manuel of Methods of Cooling Electronic Equipment," Report No. HF-S45-D-9, published by Sup!, of Documents, Washington, D.C. 2. A. I. Brawn and S. M. Marco, INTRODUCTION TO HEAT TRANSFER, McGraw-Hill Booh Co., New York. J. M. II. McAdams, HEAT TRANSMISSION, McGraw-Hill Book Co., New York. ■I. L. S. Marks, MECHANICAL ENGINEER'S HANDBOOK, McGraw-Hill Book Co., New York. 5. Max Jakob, "Heat Transfer," John Wiley £' Sons, Inc., New York, N. Y. 1949. 6. R. Holm, ELECTRIC CONTACTS HANDBOOK, Berlin: Springer- Verlag, I95S. 7. II. Fenceh and W. M. Rohsenow, "Prediction of Thermal Conductance of Metallic Surfaces in Con¬ tact," ASME Paper No. 62-HT-32, ASME-AICIIE Ileal Transfer Conference and Exhibit, 1962. .V, II. Kolt and J. E. A. John, "The Effect of Interfacial Metallic Foils on Thermal Contact Resistance," ASME Paper No. 65-HT-44, ASME-AICIIE Ileal Transfer Conference and Exhibit, 1965. 9. D. M. Knot! and J. C. Taylor, "Heat Sink Analysis for Thyristor Applications."

11.0 RELIABILITY, QUALITY CONTROL AND FAILURE MECHANISMS 11.0 GENERAL One of the inherent advantages of semiconductors is increased reliability. Since the introduction of this technology, applications have ranged from consumer pro¬ ducts to the heavy industrial field, and into the very demanding military and space area. The basic reason for this wide acceptance is the increased dependability of the equipment using solid stale components. To utilize the advantages of the thyristor, industry has invested considerably, in time and money, in an effort to control and predict device reliability. This section discusses techniques that bring about desired reliability. This includes device and procedural methods. 11.1 RELIABILITY TERMINOLOGY Chapter 3.0 discussed the terminology and symbols relating to thyristors. Reli¬ ability is the probability of performing a specified function under given conditions for a specified time. Although there are many other qualitative definitions of reli¬ ability that define it quantitatively in a fashion similar to the definitions previously described. Although reliability is defined as a probability and therefore has a numerical value between zero and one, Lite terms usually used to express reliability are not, strictly speaking, probabilities. For power thyristors and other component parts the term generally used for expressing reliability is failure rate. Failure rate may be defined ns the number of devices replaced per unit-time due to failure of the device. It is normally expressed in failures per hour (or failures per cycle) of operation. Since a period of time over which the failure rate is calculated must be specified, a one thou¬ sand hour life test has become a standard for many components, including power thyristors, and the failure rale per thousand hours is the most common term. The terms generally used for expressing reliability of systems arc mean life and mean time between failures (MTBF). Both terms generally use an hour as the unit of time. The term "mean time between failures” presumes a repairable system. Mean life is defined as the average time in hours that the systems operate between failures. MTBF is the reciprocal of the failure rate. Associated with failure rate is another important term in reliability terminology, namely "confidence level". Except in rare cases the true reliability of a system or component is not known. The reliability must therefore be predicted by the evalu¬ ation of a sample of the systems or components or from prediction techniques which make use of information from samples of devices. Reliability prediction is subject to a certain amount of variability or possible error because it is based on information from a sample of devices rather than information from 100% of the devices. The amount of confidence that can be placed in the reliability prediction as a result of the variation due to sampling is known as the confidence level. A few other basic terms used quite frequently in reliability, knowledge of which is essential for a better understanding of reliability predictions, are given below: Acceptance Tests—Tests conducted to determine conformance to specifications or design as a basis for acceptance. Acceptance Sampling—Science that deals with procedures in which decisions to reject or accept product lots or processes are based on the examination of samples. Acceptable Quality Level (AQL)—A nominal value expressed in terms of per¬ cent defective for a given group of a product. 11-1

Acceptance Number (Ac)—The largest number of defectives in the sample or samples under consideration that will not prevent the acceptance of an inspection lot. Rejection Number (RE)—The smallest number of defectives in (lie sample or samples under consideration that will prevent the acceptance of an inspection lot. (Re = Ac + 1) Lot Tolerance Percent Defective (LTPD)—That percentage which will bo accepted by a sampling plan 10% of the time. Operating Characteristics Curve for Acceptance Sampling (OC CURVE) —A curve showing the relation between the lot quality or process average quality, whichever is applicable, and the probability of acceptance. Failure—The inability of an item to perform its required function within previ¬ ously established limits. Failure Mechanisms—Dynamic process which leads to degradation of a device parameter through changes in geometric or material properties. Failure Mode—The way in which device requirements are not met. Application Stress—Stress that occurs as the result of a primary duty perfor¬ mance of an item that is allowed for in the basic physics of an item's design. Environmental Stress -Stress that occurs as the result of the environment in which an item is performing a design function. 11.2 RELIABILITY PREDICTION TECHNIQUES As stated previously, the reliability of a component is usually expressed as a failure rate per 1000 hours. This value is used, along with values for other circuit compo¬ nents, to predict the overall circuit and system reliability. However, a single number often does not give a complete description of component reliability. The extent to which a single number can be used depends on the validity of the assumptions con¬ cerning the failure distribution for the component. For electronic components, it is generally assumed that failures follow an exponential distribution, the exponential probability density function (p.d.f.), expressed as f(t) =Xc-Xt Many convenient properties result when this assumption is valid. One of the most important is that the failure rate for any given time is constant. If tiic failure rates of components are constant over time, properties of the standard reliability terms and the relationships between these terms are greatly simplified. For example, if a constant failure rate can be assumed, the failure rate of a device is the reciprocal of the mean life of the device and the terms "mean life" and "mean time between fail¬ ures” are equivalent. Thus, if the assumption that "the failure rate of components is constant” can be made, the determination of the mean life of a system is greatly simplified. If the failure rate of a component such as a power thyristor is constant over time, the percentage of devices that would be expected to fail in the first interval of time (such as the first thousand hours) is the same as the percentage of devices that would be expected to fail in each succeeding equal interval of time. In the electronics industry, the constant failure rate assumption is almost univer¬ sally used although, in recent years, it has been demonstrated that the failure rate of semiconductor devices, including power thyristors, decreases with time rather than being constant. For the most part, however, the reliability predictions for semi¬ conductor devices still assume a constant failure rate. This is probably due to the fact that it is much more difficult to estimate the reliability of a device for which the failure rate is not constant, and the estimates of reliability obtained under the as¬ sumption of a constant failure rate when a decreasing failure rate actually applies will be conservative. If the exponential distribution does not apply, then the failure rate is not constant with time, and reliability cannot be denoted by a simple failure rate per 1000 hours. 11-2

There arc several distributions that can be used as alternatives such as Weibull, Lognormal, and Gamma distributions. Their probability density functions being expressed as: (t denoting time-to-failure) Weibull p.d.f. f fif

{ )-

fl(tT)g'1 x exp

^

•

>7 (location parameter) /3(shaft parameter) >0 X(scale parameter) >0

Lognormal p.d.f. f(t) = 0 a

u=mean

0 0 = shape parameter X = scaling parameter Figures 11-1, 11-2, 11-3, and 11-4 illustrate density functions as plotted as a function of time. '

Mt)

fit)

FIG. 11-2—Wolbull p.d.f.

Ml)

I It)

FIG. 11-3—Lognormal p.d.f. 11-3

Frequent use of the Weibull has been made by the semiconductor industry. Be¬ cause the failure rate changes over time, it is necessary to indicate the period of time at which failure rate is computed or over which the failure rate is averaged. Terms such as failure rate per 1000 hours during the first 1000 hours are applicable. In addition to failure rate, confidence level is used to describe the confidence that can be placed in a reliability prediction. For example, we may say that the reliability of a given power thyristor is 0.1 percent per 1000 hours with 00 percent confidence. If we need a higher degree of confidence, based on the same amount of data, the es¬ timate of failure rates must be increased. On the other hand, for a lower confidence level for the same amount of data, the failure rate estimate can be reduced. The upper boundary on the true failure rate for any confidence level may be found by means of the x2 (chi square) distribution, which is tabulated in most statistics text books. To determine a confidence level, a chi square table is referred to for the value of x2 at the desired confidence level and the required degrees of freedom (which is equal to 2 (f+1), where f is the number of failures). The value of x2 is then used in the expression:

where \ is the failure rate in percent per 1000 hours, n is the number of devices on test, and t is the test time in hours. From this expression, it is noted that in any given situation, the higher the confidence level, the higher the estimate of failure rate will be. As the number of tested devices increases, the confidence level increases for any specific failure rate. A confidence level of 90 percent is the standard accepted in the semiconductor industry. In some cases, however, a confidence level of 00 per¬ cent has been accepted. The main reason for using this lower level is the reduction in the sample size required to demonstrate extremely low failure rates. Use of the two confidence-level standards has caused some confusion, particularly in comparing one reliability level with another. Care should be taken in using the 00 percent con¬ fidence level for it could be too low a confidence to warrant use in a failure-rate es¬ timate. Present electronic systems (industrial as well as missile and space) often re¬ quire component failure rates in the range of 0.1 to 0.001 percent or even lower per 1000 hours. Testing to assure such low failure rates is difficult and in the case of power thyristors is expensive. Table 11.1 lists the sample sizes (failure-rate constant) for a 1000 hour test required to demonstrate failure rates in this range with 90 per¬ cent confidence. TABLE 11.1 SAMPLE SIZES FOR 90-PERCENT CONFIDENCE, 1000-IIOUR TEST Sample size Failure rate (%/1000 hr) 0.1 0.01 0.001

No failures allowed

One failure allowed

2.303 23.02G 230.260

3.891 38.898 388.980

As was stated previously, the number of devices required to demonstrate a speci¬ fied failure rate level can be reduced by lowering the confidence level. Table 11.2 lists sample sizes required to demonstrate the same failure rates as in Table 11.1, but at only GO percent confidence.

11-4

TABLE 11.2 SAMPLE SIZES FOR 60-PERCENT CONFIDENCE, 1000-HOUR TEST Sample size Failure rate (%/1000 hr)

No failures allowed .915 9.150 91.500

0.1 0.01 0.001

One failure allowed 2.020 20.200 202.000

It is possible to reduce the test dimensions if the failure rate is not constant but decreases with time. Analysis of lifetest data for semiconductor devices, including power thyristors, reveals that a decreasing failure rate is, in fact applicable. Table 11.3 lists the sample sizes and unit-hours of test required to demonstrate the same failure rates with the same confidence as in Table 11.1, but for a decreasing failure rate over the first thousand hours of test. The failure rates are characterized by a Weibull distribution with a shape parameter of /3 = 0.5. This value may be consi¬ dered typical of a semiconductor device, although for any particular power thyristor, a higher or lower value of 8 may be appropriate, depending on whether failure rate decreases more gradually or more rapidly. TABLE 11.3 SAMPLE SIZE AND UNIT-HOURS FOR A WEIBULL DISTRIBUTION AT 90-PERCENT CONFIDENCE, 500-IIOUR TEST Sample size Failure rate (%/1000 hr) 0.1 0.01 0.001

No failures allowed 3.270 32.700 327.000

Unit-hours, thousands

One failure allowed

No failures allowed

One failure allowed

5.520 55.200 552.000

1.635 16.350 163.500

2.760 27.600 276.000

A comparison of Table 11.3 with Table 11,1 will reveal that a 20 percent reduc¬ tion in unit-hours of test, can be obtained with tests based on a decreasing failure rate. (The unit-hours of Tables 11.1 and 11.2 are simply the sample sizes multiplied by 1000.) Further analysis of Table 11.3 will also reveal that although the unit hours of test are lower for a decreasing failure rate, the sample size for the reduced test period is actually higher than for the constant failure rate and thus intuitively a more precise estimate of reliability can be had. In adapting a sampling plan employing a decreasing failure-rate it is difficult to determine the extent of the decrease for each device type situation and also to de¬ monstrate on a continuous basis that the particular failure-rate pattern does not change. The benefits derived from using decreasing-failurc-rate sampling plans are not sufficient to overcome the practical problems that exist at the time of this writing. It is therefore recommended that constant-failure-rate sampling plans be employed. An example of such a plan is illustrated in Table 11.4. The plan illu¬ strated is derived from a plan presented in M II.-S-I9500, “General Specification for Semiconductor Devices" approved by the U.S. Department of Defense for use by all service departments.

11.3 RELIABILITY ASSURANCE IN MILITARY, SPACE, INDUSTRIAL AND COMMERCIAL APPLICATIONS The great improvement in component ami system reliability achieved in military and space applications is well known. There has also been achieved during the past few years a corresponding emphasis and improvement in the reliability of systems and components for industrial and commercial application. In the next few para¬ graphs the approaches used to achieve improvement in reliability will be reviewed. A contrast will be made between military and space applications and industrial and commercial applications. A key part of most high reliability specifications for semiconductor devices is a quality assurance acceptance testing program. The quality assurance tests con¬ sist of sample electrical tests which verify that electrical characteristics are met; and sample environmental and life tests assure that quality objectives arc met. The environmental and life tests are evaluated by electrical end point measurements similar to the initial measurements. The initial electrical tests are usually known as Group A tests. The environmental and life tests that must be performed on samples from every inspection lot are designated Group B tests, whereas those tests which need be performed periodically are usually designated Group C tests. Specific samp¬ ling plans and quality levels are specified for each environmental and life test con¬ ducted. Group B and (' tests include such environmental stress tests as soldering heat, temperature cycling, thermal shock, moisture resistance, mechanical shock, vibration (fatigue and variable frequency), acceleration, terminal strength, baro¬ metric pressure, corrosion resistance, high temperature storage; and application stress tests such as steady state and/or intermittent operation life, transient power and low temperature operational tests. In recent military and high reliability space specifications there is the tendency to state a reliability objective for the device being procured. The objective is generally stated in terms of failure rate per thousand hours when operated at maximum and/ or at a reduced power level. Intended applications for the devices .being procured have resulted in extremely low failure rate objectives being specified. The approaches used in the specifications to assure that reliability objectives are met vary consider¬ ably but usually can be grouped into three general categories, any combination or all of which may lie specified in a given case. These approaches arc as follows; 1. The reliability objective is demonstrated statistically by testing on a specified life test the number of sample devices required to assure the objective with a given degree of confidence (usually 90%). 2. 100% screening tests are employed to assure selecting the best devices for appli¬ cation use. Screening tests usually include visual inspection prior to final seal, x-ray examination, hermetic seal tests, environmental stress tests (shock, vibra¬ tion or acceleration), and application stress tests such as power transients and power burn-in (100 percent operating life test at reduced or maximum power levels.) Artificially strict definitions of failure on these tests may be employed, such as the allowance of only a small percentage change in a prime electrical param¬ eter from its value before the environmental stress and/or application stress was applied. 3. Controls are specified in procedures and systems which must be initiated and maintained in connection with the manufacturing operation and quality control program. Information that must be generated and sent to the contractor to assure proper operation of the controls is also specified. A few examples of the controls specified arc the requirements that the quality control system include a defective material review, drawing and procedure change control systems, effective calibration, a failure analysis and corrective action pro¬ gram, a reliability program plan detailing all steps to be performed in the reli¬ ability and quality control evaluation program and the requirement that all 11-6

TABLE 11.4—MINIMUM SIZE OF SAMPLE TO BE TESTED TO ASSURE. WITH A 90 PERCENT CONFIDENCE, A LOT TOLERANCE PERCENT DEFECTIVE OR X NUMBER GREATER THAN THE LTPD SPECIFIED

changes in processing or controls be submitted to the customer for approval. In many instances surveillance by a customer quality control representative is speci¬ fied to assure that the controls are properly operating. Many of the approaches used to assure reliability of semiconductor devices for military and space applications are also used for industrial and commercial applica¬ tions. I he prime difference is that the "ultimate" in reliability is required in many military and space applications regardless of the cost to achieve that reliability, whereas a greater economic balance between reliability improvement and its cost must be maintained in industrial and commercial applications. In industrial and commercial applications, expenditure for reliability improvement is increased nearly to the point at which the cost of obtaining further improvement is no longer bal¬ anced by the total reduction in manufacturing and warranty cost resulting from the reliability improvement. It was slated previously that the la-y part of all military and high reliability space specifications is a quality assurance acceptance testing program. Such a program has been recognized also to be of extreme importance for semiconductor devices in in¬ dustrial and commercial applications. Experience shows that the use of a quality assurance acceptance testing program combined with strong in-process controls, provides one of the best assurances for meeting desired reliability levels on a con¬ tinuing basis at minimum costs. An integral part of the program, of course, is cor¬ rective action (using failure analysis when necessary) taken when production lots fail to pass the acceptance tests. Whereas the concept of the quality acceptance tests program specified for mili¬ tary and space applications is the same as that used for industrial and commercial applications, there are differences in what is specified. This results in lower cost for industrial-commercial programs with only small sacrifices in effect. One of the differ¬ ences is the length of time specified for life tests. The standard life test for military and space specifications is 1000 hours. As stated previously, semiconductor devices, including power t hyristors, exhibit a decreasing failure rate. The highest percentage of failures will thus occur during the initial period of time. Because of this fact, life test time specified in industrial and commercial specifications can be shortened con¬ siderably while still maintaining most of the effectiveness of the 1000 hour life test in detecting lots having substandard reliability. Life test times of 90 hours and less are frequently specified. A second difference between the programs is that some of the environmental tests that are performed on every inspection lot in the military and space programs can be performed on a periodic basis for industrial anti commercial applications once the product has been observed to consistently pass the tests. Failure to pass a periodic type environmental test of course requires reverting to testing every lot until a suit¬ able history has again been compiled. A third difference between the programs is the quality levels specified. The quality levels met in environmental and life tests in industrial and commercial specifications arc generally not ns high as those met in military and high reliability space specifi¬ cations; cost consideration generally being the prime cause for difference of levels specified. To demonstrate achievement of high quality levels it is necessary to use large sample sizes. Since many of the environmental tests are usually considered destructive tests, the cost of increasing sample sizes over many tests increases ra¬ pidly. The sample sizes for operating life tests must also be kept to a minimum be¬ cause of the extremely high cost of procurement and maintenance of operating life test equipment. Costs of 100 to 100 dollars per position are very frequently encoun¬ tered. Whereas semiconductor device specifications for industrial and commercial ap¬ plications also include screening tests to be performed on a 100% basis beyond the tests normally performed by the manufacturer, the number of tests specified are 11-8

much fewer than those contained in military and high reliability space specifications. The tests that are specified tend to be those required for quality assurance in a speci¬ fic application.

11.4 QUALITY CONTROL TECHNIQUES TO ACHIEVE RELIABLE PRODUCT In high volume production, that is prevalent in the industry, the manufacturing process must be controlled so all design parameters are maintained within limits. To properly control any process the basic materials, workmanship, equipment main¬ tenance and the various testing procedures must be routinely policed. This assures that a good product design will bring about the desired quality and reliability, The YVestinghouse quality-control programs perform many necessary functions in the control of the manufacture of high quality Silicon Control Rectifiers. These functions include the inspection of incoming materials, process controls, lot evalu¬ ations, and the inspection of completed products prior to shipping. A great number of statistical concepts arc employed in the institution and maintenance of a qualitycontrol program in an ever increasing effort to produce the highest quality devices for ils many industrial and military customers, A review of some of these statistical "tools” is beneficial. 11.4.1 Frequency Distribution A frequency distribution as given in Figure 11-5 can serve many purposes in the manufacture or use of semiconductors such as the description of the thickness variation of a dimension within a group of incoming parts, the voltage distribution of a product manufactured during a given time period, or the reverse leakage vari¬ ation within a shipment of product. .Lower Specification Limit *1

I I

X2

llll

*3

I III

*4

llll llll

Mill

|X6

llll

111111 II I

?X7 3

Mil

nil

Sx8

llll

inn

2X9

I 111 I

X|0

I III I

X|| X|2

.Upper Specification Limit

Frequency PIG. 11-5—Typical Frequency Distribution Curve 11-9

Two characteristics which define a frequency distribution are the average measure¬ ment and variation. The average measurement of the distribution is often approxi¬ mated by the measurement which has the greatest number of observations and is at the center of the distribution. The variation is the manner and distance the tails of the distribution curve fall from the average measurement. A desirable distribution of the thickness of a machined part might be similar to Figure 11-5 in which the peak of the distribution is approximately mid point between the upper and lower specification limits and the variation is uniform and narrow in both directions. A desirable distribution for reverse leakage might be as in Figure 11-6 where the concentration of observations are a considerable distance from the specification limit, and the dispersion is such that all observations are well within the specifi¬ cation limit. Many frequency distributions are described mathematically by the formula for the NORMAL CURVE which is: C*t)* _ 2cr minute

1

0.1047

second 1.745X10"

Radians per second Revolutions per minute

0.1067

9.549

i

Revolutions per second

2.778X10"

0.1592

1.667X10-

FIG. 12-4—Angular Velocity Conversion Chart

Revolutions ikt second

\ v x. 'v n.

vx

to Obtain

1

Multiply Number of —P

Centimeters per second per second

Feet per second |K‘r second

Kilometers per hour per second

Meters per second per second

Miles per hour per second

i

30.48

27.78

100

44.70

3.281 X10”

1

0.9113

3.281

1.467

0.030

1.097

1

3.6

1.609

0.01

0.3048

0.2778

1

0.4470

2.237X10”

0.6818

0.0214

2.237

1

'NX'S. Vy

XN

Centimeters per second l>cr second Feet per seond per second Kilometers per hour per second Meters per second per second Miles per hour per second

FIG. 12-5—Llncnr Acceleration Conversion Chart

^

Multiply Number of ->

x.

Radians |K*r second per second

Revolutions per minute per minute

Revolutions per minute per second

Revolutions per second per second

1

1.745X10”

0.1047

6.283

573.0

1

60

3600 60

1° Obtain

Radians per second per second Revolutions per minute per minute Revolutions per minute per second

9.649

1.607X10”

1

Revolutions per second per second

0.1502

2.778X10”

1.667X10”

1

KIG. 12-6—Angular Acceleration Conversion Chart Dielectric Strengths (Average Values)

Dielectric Material

Dielectric

Strength in

Material

Kilovolts per Meter

Strength in Kilovolts per Meter

Air.

3,000

Paraffin.

29,000

Bakelite.

21,000

Polyethylene.

40,000

Ebonite.

70,000

Polystyrene.

30,000

Class.

35,000

Porcelain.

10,000

Gutta percha.

14,000

Pyranol.

20,000

Lava.

4,000

Quartz (fused).

60,000

Mica.

50,000

Rubber.

70,000

Mycalex.

14,000

Steatite.

8,000

Transil Oil.

10,000

FIG. 12-7—Dielectric Parameters

12-6

Specific Dielectric Constants (Average Values)

Material

Specific

Specific

Dielectric

Dielectric

Material

Constant

Constant I

vCtOr U»*irio Ihil C-nog Ih* Wo of tho equipment in which «t ii oiiQinellr installed, piovidvii suld dovice is used wltlin manuraciurws published ».itlivil» and eppr-ed In accordance with guoi) oiMilrmoilivu ptncUco. Tlun wnminiy inoll eonotitula ,i futllllmonl at ell WfUingltouM Jlabitlliei In roipact to Hid pioducts. This wermnty is In lion o< all oth«< njnsniioi eiprenml c* implied. Wesloighoot* thill not be liibto fo* iny comeqoentiit demeges. Wouinghou o typt

ocily Ilex loads or flag terminal*

Mux turn-off tunc, l„u; 2191 sene;., 15 j.iioc; 21S2 notion, 20 »uoc

58 5 ♦

Wostmghouse lifetime Guarontco applies Max repetitive peak forward blocking voltage® 01 Tj-l26’C, Mux mpolitivo punk rovorso vollago®, Tjr-125’C, voltn. Max non-repetitive transient peak forwmtl nnd rovorso volingo, volt* 8,0 msec..

VfB Vno VfOl Vno>

3 5 Si 5 SR

r*~'

♦

+

♦

♦

♦

50 50

100 too

200 300 400 200 300 400

500 500

GOO 000

700

m

8C0 800

900 U01)

1000 1000

150

200

300

500

700

000

900

1000

1100

♦ 1

♦

400

500

♦

Max nverago foiword current, amperes Symbol Max irm forward current, amporor,. . Max ft-cyclo'D outgo current, ampi., Max 3-cyclo'i1 nurgo curront, nmpn. . .Max lO-cycIryp surge curront, ampn. . Max I't for fusing (at CO cps half-wuvo), ampere' second*. Max forward blocking current ot Tj 12B’C and rated VIB, rnAdc"- . . Max rovorso loakngo current at Tj" 1 ?b’C and rntod Vmi, mAdc®Mux forward voltugo drop at If" BO Adc and Tj = i2B’C. Vdc. Max forward voltage drop at If = 500 Adc and Tj**125’C. Vdc. Max gate current to trigger at VFn' 5 V, Tj = 25'C. rnA. Max gate voltage lo trigger at Vf0 = 5 V, Tj=2S'C, volts.

55 1,200 950 800

It

6.000

*70

10

Inn

10

Vf v*

8

2.0 37

•gt

200

Vgt

3

«••* lo WrU'f'g’-xm tp VMh rfconnmiM gslt drive See AD S«-fi«0

Symbol

All Type*

■fMdurge) iFM(iutge) •fMduroe)

Max non-triggoring gate voltage, Tj" 126‘C and rntod Vm, voltn.

VONT lor vonM Pom Pfl(AV) Max oper. junction temporaturo. "C... Tj Min storage temporaturo, ’C. tsiq Max throad torquo, lubricated, In.-lb... Mux thermal impedance Junction to cane, 'C/wntt. "JC Cave to sink, lubricated, ’C/wntt. . f*cs Max turn-on time, I*-BOA. 10-90%. vfp“10 volts.TJ»2B,C,. .. ten *en Max turn-off time. If “50 A. Tj = 12&'C, dl|,/dl°20A/u3oc, dv/dt = 20V/p»OC to«r(2ioi) linear to 0.8 Vf|t.. . »o»((2102) Mm dv/dt. exponontlal to VFB ot Tj" 125’C, voUs/bSoc. dv/dt di/di Dnovinber. I960 Niiw Information I, U, C/2115/00: f, C/2117

13-15

All Typos 0.1 B 4 0 15 3 -40 lo -40 to 130 0.20 0.12 3.5 80 15 20 100 50

Avonxjr forward Cunwil, l||Ay|, AiivwO'i Pl|>u>a I. Power diialprltlori vn lor word current, rftcliinjjulnr

AiroUBB I or ward cumuli, Imlf.wovo siniiauHI.

fcrwvd Ciyrwil. if. (To* «-w>n Figure 5 Iinward voltage vt forward currant WostlniihouBO Eloctrin Coriioration Semiconductor Division, Voungwood. Pa. 1!>097 Printed ill USA

'coord Current, lriiv/|, Arrow «•. Fiuurti 2. Chm tumporntuni vn forward cui

Averwj* forward Current, I,

ll» rectangular wave,

Arapwtrt

Flnurn 4. Cum tonipurnturn v« forward currant, Irnlt-wuve ntnueoltl,

Figure 8. Iran»lont thermal impmUnci

TD 64-565

Pooo 7

Thyristor Silicon Controlled Rectifiers Westinghouse Type 251 ♦

Westinghouse

Forward Current 63 Amp* RMS 40 Amperes Half-Wnvo Avorago Forward Blocking Voltages to 1500 Volt*

The Westinghouse Typo 251

Dimonsion8 in Inches

Series Fontures • • • • • •

AH Oiffusod Design Guaranteed dv/dt (300V/»»ec) Low Gate Current Guaranteed Value of di/dt Low Thermal Impodance High Surge Current Capability

Tho exclusive WottinghouM COE construc¬ tion tochnkjuo provides a THERMAL FA¬ TIGUE-FREE device by eliminating solder .•oints. In addition, tha entire series carries tho WESTINGHOUSE LIFETIME GUARAN¬ TEE.

Maximum Ratings and Characteristics Westinghouse Type

Repetitive Peak Forward and VPB Reverse Voltage.® volts.. - VRB Non - repetitive! ransient Peak Forward and Revorso VoltVn ago. volts < 5.0 msec.... VRBT Peak Forward and Reverse lFB Leakane Current. mA. i»=

60

100

Q jo ^

si

i

a> 2 1 ns

a 2 |

ioo; 200 300 400

500 600 700 800

150 300 400 500

950

_

Conducting Stato (Tj-125*C)

Symbol

RMS Forward Current, amps. Avo. Forward Curront (180‘ Conduclion) amps. Sumo Current (at 601 It): 'A Cycle,amps. 3 Cycles, amps. 10 Cycles, amps. I't for Fusing (at 60 cpi half-wave). amps* sec. Forward Voltage Drop at Tj=25'C

■aus Iave I'M I'M I'M It

Vf lr - GOO Adc. volu. Vf

700

850

s

500

1100

An Types 63 40 1200 950 800 6.000

1100

1200

1200 1400 : 1500

1200

1300

1450

1550

1700

1800

10_ Gate Parameters (Tj = 25*C)

Symbol

Gate Current to Trigger (VIB-12V). ma. GatoVoliagotoTnggei (Vf 0 «■ 12V), volts. Non-Triggering Gate Voltage at Tj = 125-C (Rated Vfb). volts. Peak Forward Gate Cunenl. amps. Peak Reverse Gate Voltogo. volts. Peak Gate Power, watts . Average Gale Power, watts.

■gt vGt Vgnt •gfm Vgiim Pgm PM*V)

All Types 100 3 0.16 4 5 15 3

Switching State

1.7 3.7

-40 to * 125 -40 to *150 0 28 130

s

1000

,

—15

Thornial Characteristics Opor. Junction romp Mange. C. *J Storago Temperature Range. ‘CMax. Thermal Impedance. ’C/Watt: Junction to Case. fjc Max. Thread Torque. Lubricated, in. lbs.

600

jo

N

251ZH

co

251 ZD

|


a«0 Urtv*, • ‘flora 1 Ponai dmipition vi forwartJ currant.

Awn>g» rvMftf Currant, |f|MI,aimnr»t Plgura J. Powar dittlpitlon v» forward currant, haltwava unutoid

=Ie !iiii=s!!ii

iVfnoil C^rara. I((w|t Ampoat •Igura 2. Cue tampaxtura v* forward currant, roctanqular wava.

Awrogo (umihj Currant, !ria«rtfroura d. Cat* tamparatura vi forward currant. half.wava elnutold-

TD 54-565

Page 9

Thyristor High Temperature Silicon Controlled Rectifiers Westinghouse Type 2515+

Westinghouse

Forward Cuttutil 03 Amps RMS 40 Amperes Half-Wave Average Forward Blocking Voltages to 1000 Volts

Tho Westinghouse Type 2515 High Tempornturo Series

Dimensions in Inches

Features • 1G0‘C Junction Temperature • Guorantood dv/dt (300V/*scc) • Low Gate Current • Guaranteed Value of di/dt • Low Thermal Impedance • llioh Surge Cunenl Capability The oxclusivo WoMlr»i|houso CBE construc¬ tion tuchmquo ptovldos a THERMAL FA¬ TIGUE-FREE dovicn liy eliminating noldor |olnts. In addition, tiro entire series carries tho WESTINGHOUSE LIFETIME GUARANTEE. •f Wostinghouso Lifetime Gunrnntno Wc-umfihauM mwnmln lo I ho miulnsl puroliMor that II will conus! liny iloftnm tu woikmaaitilp. tiy oapnir nr ioi»»cnmanl f.o.b. foclary, fur uny silicon iiawin utmlcondueior kean'ig thH symbol + r« (Mima the hto ol (ho oqolpmont in which il Is artginally ImiaIIdiL p»c»ulad Hid douico it u»otl wlrhin fiHmit»e«ur»r'» pvtlnh«d r*!le«j» o«d ojiplwd M KCOnMnco with ooea ens««nnB DIWW, tho locoing woironty it ticluino and in h»u ot »N oiner worrontW* of nuolity whother wtltion, oral, or imp'-rd (meluiiino uhi warientyol inotchiintitui.lv cr Mno«» tnr pui|K>t»). WmIiiioImkim ihnll not tin liililo for ony coninquim11*1 iliiinuoor.

Blocking State (Tj-160'C)

Symbol | Westinghouse Type o

a

u.

5

in

1 5 '

s

s

8

8

8

8

a

IDO

200

300

400

500

600

700

800

900

1000

150

300

400

600

600

700

850

950 i 1100

1200

Ropollllve I’ouk Forward and Hovorso Voltagri, voile .. Non-rapatllive Transient Peak Fnrwardand Reverse Voltage, volts S6.0 msec.

Vpo Vpn 60 Vpr VneT 1 100

Peak Finward ond Revorse Loakoge Current. mA

}|£

Conduction Sfto (T.,

IhO’C)_Symbol

RMS Forward Curroni, ninps.. *nMS Avo. Forward Curroni (180* Conduc¬ tion) amps. Iav( Surge Current (at 60Hr) V, Cyclo, amps. Irv 3 Cycles, amps lrv 10 Cycles, amps. W%, Pt for Fusing (at 60 Hr half-wave), omph^ sec. Pt Forwiml Voltage Drop til Tj**26‘C lr~ 00 Adc, vollH.. Vp Ip-BOO Adc, volts.Vp

_ All Type;. 63 40 1200 950 800 6,000

® Anpiios fty »oro or nognpvu auto vallagn. i® Ecu Manor volMgvs refer to WoituiohouM.

-40 to - 150 "40 TO *150 0.2B 130

&

a

3

a

3 8

•16-!_

Onto Paromotore (Tj"25*C)

Symbol

Onto Current in 1 rlggur (Vro«12V). inn Gate Voltage to 1 rlggor (Vpg ■ 12V), volts Non-Triggering Guto Voltage at Tj ' 25‘C (Rated Vp0). volts. Peak Forward Gate Current, amps. Peak Reverse Goto Voltage, volt*. Peak Gate Power, watts. Avorogo Gate Power, walls.

Igt VOT V0»T 10 ' M Vc«M PGM I’OfAV)

All Typos 10Q 3 0.16 4 5 15 3

Switching Stnto (Tj-150*C)

1.7 3.7

Thermal Characteristics Ooet Junction Temp Mongo. 'C . . . 1j Storage Tompcratute Range, "C.T„0 Max. Thermal Impedance. ‘C/Walt: Junction to Cose.ffjc Mux. Thread Torque, Lultrlcnlod, in. Ihs. .

i

1 5

Typical 1 urn-On lime. Ip = 50 A, 10-90% VpD = 10 vollstt. Tj-25-C. usee,. .. Min. di/dt. Linear to 6.0 Uve-® ampr-'-sec. Typical Turn-Off Time. Ip = 50 A. diR/dt = 20 A/risoc., dv/dt = 20V/U5oc. Linear to B Vrg. usoc. . Min. dv/dt. Exp. to Vfn, vults/jisoc.

ton

40

•oil rlv/dt

120 300

@ With racommomlntl goto drive. Suo AD 64-tit)0.

October. ’9*0 Mow Infornulon E. D, C/2”5.'l)D; C. 0. C/2117

13 • 19

4

di/dt

Thyristor High Temperature Silicon Controlled Rectifiers Westinghouse Type 2515 Forward Currant 03 Amps RMS •iO Amperes HaII* Wove Average Forward Blocking Voltages 10 1000 Volts

Electrical Characteristics

A*»op rcr»onlCv*»*«, IrisvtiAmfam Figure 1. Power dltalpatlon v* lorwaril currant, rectangular wan

*cr«arg Gsroni, Univ).*'T*c«"n 3 Cilia tamooraturo vi forward currant, rectangular wove

mm An)ii>;a fniwuil Curanr, I ri 0v l • A,i|o'tiQ llguro 3. Powei illailpntlon va foiwnnl currant, half.wave iliniioltl.

Atardija IUraanlCurijnt, l|iavi> AmpotM Figure «. Cotu tomporoturo v» fuiwmd curiant. tiolt*wnva ainuaoli

|T =

i

II if i !! ; jj I

I

1 ..= i •^

TD S4-S6S

Westinghouse

Pago 3

Thyristor Silicon Controlled Rectifiers JEDEC Types 2N4361 and 2N4371 Westinghouse Type 254 Forward Current 110 Amps RMS 70 Amperes Hall-Wave Average Forward Blocking Voltages lo 1400 Volts

Application Designed lor cycling loads. JEDEC typos 2N4361 and 2N4371 thy.istor SCR (type 254) with then 1600 ampere surge rating, are especially suitable lor such application* at motor control, starters, primary controlled power systems, and inverters where high inrush currents are encountered. This sorgo rating. combmod with 10.700 amp* soc I't rating allows optimum lusa coordination. The exclusive Westmghouso CBE construc¬ tion techmquo ulmimatos failures cauMHl lay thermal stresvos by doing away with voider loints. In addition the entire senes earn?* a guaranteed minimum dv/dt rating, and the Westinghouse lifetime Guarantee Guarantee Wntwyhouie It* P,.(hii« ihM i in" cenett *~i a**c. 01 I«pix*t»*nt fob Uctorr. tor tow— lerr.co^Soctor twanne lha swnbol •fo’Tju-.-* w* M» ot IM *0-p"-nl In which ■ n o-gmalr imtafcd. powCrt t*d dwK« » uwd wrttua au out *1**1 * tUAshed >Mr^p one apfiUd in aceatdsnc# with good engiMmne (*acbc« IWs war*.I, shall conittutr a WW«ant ol *« Wntwphcusc hab-St-. in wspKI :o swd (redact* ttvi warranty .5 in lieu ol •a other warrant** nerniM cr rrsfced. Antrglhaa nor be Latte far any COMeoetriM

10

JEDEC Number or Westinghouse type 2N4361 Senes. Re* Leads; 2N4371 Series, Rag Terminals. For Westi e types specify lle» leads or llog twmlnats.

Ratings and Characteristics

u.

< £ Westinghouse Lifetime Guarantee applies ‘Min forward blocking voltage at Tj 12S*C. volts.. . "Max repetitive peak reverse voltage’ Tj = 125"C, volts. Max transient peak reverse voltage, volts.. Max repetitive peak forward voltage, volts Max average forward current, amporos.. Max rms forward current amperes.. ’Max 'A-eyelet- surge current amps Max 3-cycle' surge current amps. Max 10-cyder surge current, amps. Max Ft lor (using (at 60 cps hattwavo). ampere* seconds. ‘Max forward blocking current at T,125’C and rated Vy§. mAdc . ‘Max reverse leakage current at T;125‘C and ratod PRV. mAdc. Typ. holding current at Tj » 12S‘C, ma Max forward voltage drop at If =50 Adc and T,«26‘C. Vdc. Max forward voltage drop at If “500 Adc and T, ■ 25‘C. Vdc. Max gate current to logger at V»* 5 V. T|“2S'C. mA. • JEDtC Roeisurad ParuMtarv Applio* lor rmo ur nogrii.o C*'•» fiQu/*» 4. V 17 anil 1

1300

1400

Current

Onto Current Select Order Codfl 4 Same for all devices on this shoot.

Select Older Code 70 c Conducting Stain (Tj 125C) Mi. Mr* lonvnril Cunint, ampon M.i. .».i« iiiiof eirnnl amp* Ma • 3 tv.ln .nigii c.iinim, iii'ln Mill H>eysw • iiiiu-»fiu*renl,amp* Mi. ..In* mi O' • » i '"'1 imp.ia' i«onili Mi • i'i tin twmm pur linnnt •1.0 mn ■iiit’ II i " O. ..‘ .'"■mill Va. larwiml "illiiii" .In.. till Am .mil T j - 76*C. Vile. . V... fuiwillll viilIihi.i (ln>|) ill tiM- tmi) Am .mil t, - /tpc. V.I.

Symbol ir(nv$i 'tswi'^un iisr.K*“ ui'an ii/'iium, «nt|i* Mu. I'I llll luting I fill 1.Mi•• * ■ II 3 .•!*) ampul*' iccomli Mu I'I lo> r.i.il.uili.1 III).. 1 ti 1... an • & >25 Amps RMS 80 Amperes HnH-Wevo Average Forward Blocking Voltages to >000 Volta

Electrical Characteristics

A.wogt tvmvti Current. Ic(ar>. A"***™ t 1. Power dlttlpatlon vs forward currant, rectangular

V-«or |oao altil Cur r a" l,tr. A“0»rei Flguro B. Potwunl voltage v» forward ourient. Wor.tlngltonnn Eloctrlo Corporation Semiconductor Division, Youngwood, F'o. 16897 PtmiM »n USA

t-rragr ‘»ii*i 1 noil J. daied Aun ii*t. 11IGU E. D, C/2110/0 5; t. D. C/211V

13-33

5.0

60 300

TD 54-567

Page 2

Thvristor Silicon Controlled Rectifiers Westinghouse Type 261 FofWiiffl Current 200 Amps RMS 125 Amperes Half-Wave Average Forward Blocking Voltages to 1500 Volts

Eloctricol Characteristics

’

1

r— 360*—

[

3

[w. W: A 50*

ACO'

U

sSo AIM* S\

.-j

i

1

l>-a.sCo..^a> Figure V M... power dUilpetton. lull cycle average. rectangular wave

1L A-.p«.rt

Figure 2. Me*, allowable alud temperature. rectangular wave.

aretute. Iiall-wave alnueold.

Figure 3 Me* power dissipation. lull cycle average. Hall-wave emueoxl

WdBtlnghoume Electric Corporation Semiconductor Division. Youngwood. Pa. 15697 Pnnted in USA

13-34

S00

TD 54-567

Westinghouse

Pogo 5

Thyristor High Temperature Silicon Controlled Rectifiers Westinghouse Type 2615* Forward Curron: 200 Amen RMS 125 Amperes Half-Wave Average Ferv/ard Blocking Voltages to 600 Volts

The Westinghouse Type 2615 High Temperature Series Features • 150'C junction temperature ■ Guaranteed dv/dt (300V,Vsec) • Low gate current • Guaranteed value of di/dt • Low thormol impedance • High surgo current capability The exclusive Westinghouao CBE construc¬ tion tochnique provides a thermal fatiguefroo dovico by eliminating solder joints. In addition, the entire series cacrios the WestJnghoMBO lifetime guarantee.

♦ Westinghouse Lifetime Guarantee v.vutn jr.ouio warrants to the c/ifjint/ gurohaier that it will cweci nny dsfrcli in wgrkmtnship, By ropair nr replacement f o.t>. fiCIOiy. lor any silicon power tuirlcondualor o«a/in» ihis jyim-ol ♦ tm during thn '•In o' rtouipmont In which i: is or'ginally mtillcd, pinvldaii sain Covlce it uiM within tnsnjfacdJ.-or'n piililishait ratings nr.it acoi«ti in sseotdars# wifi OOPtl anij nse'lnp pi»:L«". Too tsraiO'nu wsnanty li meh.nvu and waf imnieonOueioi baarinj ihli symbol duiing Wib Ufa ol ihn equipment in which il it oflginolly innnllod, pruvidsd »

0.15 .075 4.0 8.0 20 30 100 75

Thyristor Fast Switching Silicon Controlled Rectifiers Westinghouse Typo 2181 Type 2182 Forward Current 200 Amps RMS 125 Amperes Half-Wave Average Forward Blocking Voltages to 1000 Volts

Cl©CtriC-al CharactnrifttiCft

Figure 1. Power dmipeiion >■ forward current recte-guti

TD S4-S68

Pago 5

Thyristor Silicon Controlled Rectifiers Westinghouse Type 260*

Westinghouse

Forward Current 275 Amps RMS 175 Amperes Half-Wave Average Forward Blocking Voltages to 1500 Volts

Application Designed for cycling loads. thyristor SCR Type 260 with its 5000 ampere surge rating, s especially su-table for sucn applications at motor control, starters, and primary con¬ trolled power systems, where nigh inrush currents are encountered. This surge rating combined w«ih 100.000 amp* sec It rating allows optimum fuse coordination. The exclusive Westinghouse CBE construc¬ tion technique eliminates failures caused by thermal stresses by doing away with solder jomt*. In addition the entre series carries a guaranteed m.nimum dv/dt rating, and the Westinghouse Lifetime Guarantee. ♦ Westinghouse Lifetime Guarantee Arttinesosi* *»'i"’i ro l1* cngwU (•u'cnatei that • «•!! remct **» ea’aets -srtnunViip. by rep** r.. lab factory, tor any iWcan t>o».r towe Ki tyafcal ♦>- dunng Ihe '•'» or i"e k.s*u«i m wtueh k n or^naOy Imiaded. i'o.e+1 ...» an*• .* u«a within manulactuiert pjb.iWM ratiees and KH-'+a «” *:u*d»nce with good enfiaeeano practic*. Tha laragamg warranty 1* • •ctouva 1*1 m l»u ol ae a*w< wanamiat o< .0* eat be W* H 10 93 Cate Maximum Ratings an I Characteristics Block Stain (Tj»126X) Symbol | Westinghouse Type

S Hopotltivo P Rovorso Voltngo.® voles.. Non-ropelilivo Transient Penh Forward and (Inverse Voleage. volls £5.0 msec Peak Forward and Reverse Leakage Current. mA. Conducting State (fj

126X)

V,D V„n V«« VyBT V«t VRBr ly0 I„„ Ian '«0

v.„

i 1

100 100 200 200 300 300 400 400

500 600

200 200 300 300 400 400 500 600 600 4Symbol Symbol

RMS Forward Current, amps Ave. Forward Current (180' Conduc lion, amps.IAV| Surge Current (at 60 Hi) * Cycle, amps lrM 3 Cycles, amps i»M 10 Cycles, amps lfu 1*1 for Fusing (at 60 Mi half-wave). amps'-sec. IT Forward Voltage Orop at T,-2SX l» * 100 Adc. volts ..... V, If "625 Adc. volts. ... Vr

All Types

175 6.000 3.600 3-100 100.000 1.15 1.55

Thermal Charecteriatlca_ Oper. Junction Tomp Range. X ! ~ Storage Temperature Rarge. X TISg Ms*. Thermal Impedance. X/Watt Junction to Case. $JC Case to Sink. Lubhcated. Max. Thread Torque. Lubricated, in..lb*. ® F01 hiBher voltage* f*'»r to WettmeneoM

-40 to -125 -40 to *150 0.13 0 075 240

700

700, 800

850

900

950

1100

1000 [1100

1200

1200; 1300 j 1450

13C0

1400

1500

1550 j 1700j 1000

1 -r Gate Parameters (Tj* 25X)

symbol

Gate Voltage to Tngger (V,B -12V). volts . Non-Triggenng Gate Voltage K Tj-125'C (Rated V,B). volts. Peak Forward Gate Current amps Peak Reverse Gate Voltage, volts. Peak Gate Power, watts. Average Gate Power, watts.

VGT

VCRN P0M PC(A,

Switching State_ Typical Turn-On Time. U = 100A. 10-90%. VfD = 10 volts*. Tj*25X. Msec. Mm. di/dt Linear to 5.0 lAVf.® amps/^sec. Typical Turn-Off Time. If*150A. Tj* 125’C. d'R/dt*50A/*isec, dv/dt* 20V/m*cc. Linear to .8 VfB. usee. Mix dv/dt Exp. to Full VfB. volts/Miec.. . ® -ti t* rtco or naeavre Qizt vsCapt. ® Avm iKOW'^j gu Snve. Sec AO 54-553.

t^ di/dt

ton dv/dt

March. 19W New Information t 0. C/2115/OB: E, 0, C/2117

All Typos

Thyristor Silicon Controlled Rectifiers Westinghouse Type 260 Forward Cunem 275 Amps RMS 175 Ampeies Half-Wave Average Forward Blocking Voliages lo 1500 Voln

Electrical Characteristics

Forwc/B Current, ir illtllpailon

roeiangular wave.

forward currant. racfanguUr

MmwmmiUmt ;iii? -= i--=.!?>s»Sll ^giiasiigiiiiiiini Awioga rv«o>d Current, flgura 3 Power dlttlpation vt forward currant, holt

5. forward voltaga v» forward currani. Westinghouso Electric Corporation Semiconductor Division. Youngwood. Pa. 15697 Prtnrrd in USA

r-T^r 'w-art Cu ran • rj • ?»•:. T* » * «J> '*

3

w

»oc

w

*»

bx

TOO

TW

ttu

va

■»

• t; • —«• ?»mt .• : • ir*(. ». »• *»» * -T". .*n W-TtUj*'U* >1. T-1W * 1MM4 T»>). •».»•.*i*T hhwi VT«, ..V;» toDM) MM n;uti, >U...• ..Jr•*•*«*• H~W. -«». T«H’»M nt.t

?»wi .Vfy»nniu

»■. TV.- I.M-

» II IS II II II

s au m*.

«•> NMN w»• uitu

18

w

V? sm

•»*i— >«•»;», if • ix*. i>«4, *n • •» «*»• * • »3 • n’t, - .. 41/M. «. 3.1 !«..)5 • »jm! tj*«. mV. «W« - » »'—*•. •.;« . fOvMf*. ■i*. i./h,

13-45

.SS1SS!

»• -Pin, •««•/»«.. . *•/«

& IIU l-WM

lrt«. «. *3 V-J*0.

I w

r ilCW ll«

Thyristor Silicon Controlled Rectifiers Westinjhouse Type 2201

Electrical Characteristics

PiSUlHiSI

FiQura 3 Power d.aa.pat-

-

—

I

]H ~M EE

mas

ram ft*-on) Currant,i|.(Sal Ainoarat Flgura • Forward vollaga ira forward currant. Waatlnghouaa Electric Corporation Samicomlucior Orvlalon, Youngwood. Pa. 15897 Pm Mad in USA

ill 2== ‘ |1 i^Saal^l =ass ■ i==i —f : =Er : =r: = = r SSssfillMsf - - ; 5;===iP==l! : EZE = III

TD 54-569

Pago 1

Thyristor Silicon Controlled Rectifiers Westinghouse Type 2248*

Westinghouse

Forward Current 475 Amps RMS 303 Amperes Hall-Wave Average Forward Blocking Voltages to 1200 Volts

Application Designed (or cycling loads, thyristor SCR Types 2248 with then 5000 smpero surge rating, are especially suitable (or such ap¬ plications as motor control, siartois. primary controlled power systems, end inverters where high inrush current*, wo oncounlcrod. This surge rating, combined with 100.000 amp* sec I'l rating aluws optimum luso coordination. The exclusive Westinghouse CBE construc¬ tion technique eliminates fatfurcs caused by thermal stresses by doing away with solder feints. In addition tho entire sonos carries a guaranteed minimum dv/dt rating, and tho Westinghouse Lifetime Guarantee.

Dimensions in Inches

♦ Westinghouse Lifetime Guarantee V.n’fsSxw mtntrai to Vm or^nd i*ur it » - ee^tet any - »c-i-i»wp b, i«w a resiaeemtnt lob. 'Ktc/y. «o» a-y mU i» n.c-i-*3 nr~s» »vJ I5>*r -I MiotiKi Pioe .-e —' -e e««a t*. »*v*i ««». r-tvt« a -r-e-t o« a- A«i^sv>.u babMea m to w«J P^OvCti. T*>i nenanTy aniwrl Hle-nr»..-*«»« « .-U.- , Watiwgreuse shat "01 U *t»e k» any soc. ® M* irciw>T

fu

|

2

I rv

s

|

S

700

800

900

800

960

1100

K

100

: 200

300 ' 400

500

600

200

300

400 | 600

eoo

700

o

Q.

273V

o

a

3 N

1000! 1100

Ev

1200 1300 | 1400

1200' 1300 1450 1550 j 1700

-1!

3! 5 Iavi Ifm Ifm Ifm

l*t Forward Voltage Drop nt Tj"26*C If if = ‘uu 100 *oc, Adc, volts. vans. • V, vf If. = 625 Adc, volts. - Vf

Gate Current to Trigger rt(M.I».P*0« Airp«>ri figure 6. Forwerd votiage «■ forward current.

Figure #. Transient thermal Impedance ve time

Weatinghouse Electric Corporation Semiconductor Division. Young wood. Pa. 15697 Printed in USA

IJ - 56

TO 64-570

Page 7

Pow-R-Disc™ Thyristor Silicon Controlled Rectifiers Westinghousc Type 272+®

Westinghouse

Forward Current 470 Amps RMS 300 Amperes Half-Wave Average Forward Blocking Voltages to 1500 Volts

Type 272 Full Capacity Series Features: • All diffused design • Guaranteed dv/dt (300 v/*s) • Low Qate current • Low V, • low Thermal Impedance • High surge current capability

Dimensions in Inches WC D-oemri * .CtOMwirum Gera Stele ICo-ncCel MC'baiwi * OTOWnurun Cera ne e

The Pow-R-Ditc thyristor package oilers: • Smgle or double-nded cooling • RevemNe mounting potjnty • Compact we and weight • Center -fue gate. Eiduuve Westinghouse CBE (Compression Bonded Encapsulation) provides a THER¬ MAL FATIGUE-FREE device by eliminating solder joints Easy mounting, man mum surface contact, and top performance is assured when using the Westinghouse double -spnng. doubleswivel contact damp* In addition, the entire senes carries the:

020Mi«

• Westinghouse Lifetime Guerantee Maximum Ratings and Characteristics^' Blocking State (Tj-125*C)

Symbol t Westing! “j

RoDOtitivo Peak Forward and Reverse Voltage®, volts. Non-ropotitivo Transient Peak Forward ond Rovorsa Voltago. volts "fl awey rwlh (older (oMta. I" addition the eni.r* ear lee carries • p.ararteed mliumem d»/- Sr* or -*~d t-X’-dne *•» mtntrft Cl "t"CVOtaf( C* lorn So* pvpoul s*4< »o be *»r '» am cawan* laldawaat* Shipping rresffu 16 m. Maximum Ratlngi and Charactanitic* Block Stata JTj - 125°C) Symbol

Westinghtw Type

z

*

3

£ Repetitive Peak Forward and Revere* Voitaga.C&olo ... Nonrapetlthra Tr intrant Peek forward end Rweree VoTp ega. volt* 5.0 n-aec. Peak forward and Harare*

a.

%

100 200

3C0

400

500

800

700

fe

200 poo

400

500

600

700

860

'PB Isa

Conducting Sate IT. - 125°CJ *»• forward Currant 1180° Conducnon. amja. Surge Current tax 60Hj>: % Cycle. ax* 3 Cyciaa. amc*. 10 Cycle* amp* lJi to* Fueino III 60 H| hell-.**!. «nps?-a*c. forward Voltage Croc at T , • 25°C iF - 500 Adc. voia. Thermal Ch*ract«rlitici Oper. Junction Tamp. Pang*. °C Storage T am pent u-a Range. °C. Mae. Thermal Impedance. °OVI*n Junction lo Cam Cat* to Smk. Lubncatad Ma*. TVeed Tor Qua. Lubncatad. .

in rj

_K 800

900 1000 1100 1200 1300 1400

980 1100

1200 1300 I4S0 1560 1700

•15 -

'.us

All T»pe* aoo

•avc >FU 'FM •fM

2BO 5500 3^00 3A00

Symbol

Pt

120.000

VF

1.3S

tj Trig

20 to *125 -40 to *160

«JC •C3

0.10 .06 3C0

Gita Paramantan (Ti - 25°C)_Symbol Gata Current to Trigger (Vfg - 17VI. ma Iqt Gate Voltage to Trigger (VFB - ITVI.rdB VGT lion Triggering Gelt Voltage et Tj - 125°C tRatedVFBl. volte. VGNT baa* Forward Gate Current, arrpa. iQFU Ptea Rererae Gaia Volta*, volte. VGRM Peak Gata Power. Matte. PGM A-arage Gate Powa*. watte . ^GIAVI

Ail Typae 160 4 0-18 4 2 18 3

Swi trying Stata_ Typical Turt*On Tima. Ip - 100A. 10-90%. «F0“ 10voU*S)Tj- »®Cuaec . . .. Ion 88 Min. OVdt. Linear to B.O UVC ® ampa/jaac. fll/dt 100 Typical TunvOtf Time. IF - 16CA. Tj . 1»°C dip/di • bOAJymc.. Otldx XVI y*€. Linear »JVFB.>aac .... Mn.d>/d«. Cap eo OB VFB.vo«ti/>CS

SynPot •GT vot

»"Tn-

UGM •gfm VORM PGM PG|AV1

0.16 4 7

4

to 3

1J0 Tvmc* TinrOn TM 1; - tOGA. 1G00V Vf o - 10 vo»tA$ Tj - TVKjHmc toV0lAvC.® *rmJ/mc. lypxoi TurrvOff Tima. If • 160A. Tj .

-70 to • 176 -40 to.160 0.10 06 300

' 76°C dlR/0t - 60 A//nee, OrftJt 70V/>-acL Lina- to B Vf0, J— Min. dr/dt. E«|» to 0 6 Vm. volti/>jaBc .

ton

60

dl/dt

too

«oH dr/dt

300

® Aootta* lor rare or nagatF a gata voitaga. @Wtt* racommandW (W Cyclo, amps. Itsm 3 Cycles, arnps Itsm 10 Cycles, amps Ijsm |7| for Fusing (at CO Hr half-wave), amf»2-see. (8.3rm).. . . I2t

(Rated VpBl.volU. Peak Forward Guto Current, amps. Peak Reverse Gale Voltage, volts .... Peak Gate Power, watts. . Averego Gate Power, watts.

Forward Volition Diop nt Tj » 20°C Ip * 02D Adc, volts.Vtm

Symbol 'GT VGT . Vqd 'GFM VORM PGM PGIAV)

All Typos :wo 4 0. ID 4 3 16 3

Switching Stoto __ Typical Turn-On Tlmo. Ip-IOOA, 1690%.

Thermal Characteristics _ Oper. Junction Temp Range, . 7 Tj Storage Temperature Range, °C . . . . • -T„g Mo«. Thermal Impedance, °C/Wot1 Junction to Ambient. . . . I'ermlssable Anodn Stud Torque, N on-lubricated ..... ® ®

-to to 026 40 to 050

vTIDYNr10vo,«' . Tj-2S°C. usee. Min dl/dt. Linear to 2.0 lAV£. ® ampi/psec. C16C20 . 1)00CIO . . Typical Turn Off Time. IT » 160A, Tj - 125°C, (llH/dt■ BOA/pwc.. rtv/dt1 20V/«icc. Linear to BVfb.hwc. . Min. dv/dt. E

*r. Junction Temp. Hang*. °C. Storage 1 mtparetura llang*. * . .. » • Mb*. Hi trine* l.i.—« °C/V»*nQ: Junction to Caaa. Caae to Sir*. Lubricated

(2) FM >FM >FM

AJlTypa. 6» 400 6.600 a.700 f.CCO

|J.

170. OCO

vf

1*

Tj r«

-40 to *126 40 to* ire

Ox oca

006 002

For Inlormetion on Mounting Froeedure* and Technique*. iefw to AD 54460. All rating* and charectaHdlce am bawd on doutowddad cootirp

Shipping Weight: 9 or.

Gaa Pwanwtao {Tj ■ 25°C1_Syrtool Gat* Current to Trigger (VfB-17V). fra 1^7 Gat* Voluga to Trggar IVpg-ITVI. volt* VGT NonTnggarmgGat* Volu^at 1r 126°C [Rated Vp qI. *Olt*. VGNT P«a» Forward Gala Currant, amp* .... iGFM Fa* Havana Gat* Voitaga. wait*. Vqrm Pew Gata Fower. nett*. PqM Arw^a Gn Fewer, warn. PG(AVI Switching State Twie. f 2rv*n 1W .f-100A idtttm. VFO-tOwXt* 8. Tj-26»c. uaac . Min. dl/dt. Linear to 6 0 lAVE

1®

R

8

900

1000 1100 1200 J3M 1400

950 1100

1200 1300 1450 1550 1700

800

VRB VFT VRBT 'F3

Conducting State (Tj - 12W*CI Hits Forward Current. «mpi A.e. Forward Current