Radio Frequency and Microwave Power Amplifiers, Volume 2: Efficiency and Linearity Enhancement Techniques 9781839530388

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IET MATERIALS, CIRCUITS AND DEVICES SERIES 71

Radio Frequency and Microwave Power Amplifiers

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Analogue IC Design: The current-mode approach C. Toumazou, F.J. Lidgey and D.G. Haigh (Editors) Analogue–Digital ASICs: Circuit techniques, design tools and applications R.S. Soin, F. Maloberti and J. France (Editors) Algorithmic and Knowledge-Based CAD for VLSI G.E. Taylor and G. Russell (Editors) Switched Currents: An analogue technique for digital technology C. Toumazou, J.B.C. Hughes and N.C. Battersby (Editors) High-Frequency Circuit Engineering F. Nibler et al. Low-Power High-Frequency Microelectronics: A unified approach G. Machado (Editor) VLSI Testing: Digital and mixed analogue/digital techniques S.L. Hurst Distributed Feedback Semiconductor Lasers J.E. Carroll, J.E.A. Whiteaway and R.G.S. Plumb Selected Topics in Advanced Solid State and Fibre Optic Sensors S.M. Vaezi-Nejad (Editor) Strained Silicon Heterostructures: Materials and devices C.K. Maiti, N.B. Chakrabarti and S.K. Ray RFIC and MMIC Design and Technology I.D. Robertson and S. Lucyzyn (Editors) Design of High Frequency Integrated Analogue Filters Y. Sun (Editor) Foundations of Digital Signal Processing: Theory, algorithms and hardware design P. Gaydecki Wireless Communications Circuits and Systems Y. Sun (Editor) The Switching Function: Analysis of power electronic circuits C. Marouchos System on Chip: Next generation electronics B. Al-Hashimi (Editor) Test and Diagnosis of Analogue, Mixed-Signal and RF Integrated Circuits: The system on chip approach Y. Sun (Editor) Low Power and Low Voltage Circuit Design With the FGMOS Transistor E. Rodriguez-Villegas Technology Computer Aided Design for Si, SiGe and GaAs Integrated Circuits C.K. Maiti and G.A. Armstrong Nanotechnologies M. Wautelet et al. Understandable Electric Circuits M. Wang Fundamentals of Electromagnetic Levitation: Engineering sustainability through efficiency A.J. Sangster Optical MEMS for Chemical Analysis and Biomedicine H. Jiang (Editor) High Speed Data Converters A.M.A. Ali Nano-Scaled Semiconductor Devices E.A. Gutie´rrez-D (Editor) Nano-CMOS and Post-CMOS Electronics: Devices and modelling Saraju P. Mohanty and Ashok Srivastava Nano-CMOS and Post-CMOS Electronics: Circuits and design Saraju P. Mohanty and Ashok Srivastava Oscillator Circuits: Frontiers in design, analysis and applications Y. Nishio (Editor) High Frequency MOSFET Gate Drivers Z. Zhang and Y. Liu RF and Microwave Module Level Design and Integration M. Almalkawi Design of Terahertz CMOS Integrated Circuits for High-Speed Wireless Communication M. Fujishima and S. Amakawa System Design with Memristor Technologies L. Guckert and E.E. Swartzlander Jr. Functionality-Enhanced Devices: An alternative to Moore’s law P.-E. Gaillardon (Editor) Digitally Enhanced Mixed Signal Systems C. Jabbour, P. Desgreys and D. Dallett (Editors) Negative Group Delay Devices: From concepts to applications B. Ravelo (Editor) Understandable Electric Circuits: Key concepts, 2nd Edition M. Wang Magnetorheological Materials and Their Applications S. Choi and W. Li (Editors) IP Core Protection and Hardware-Assisted Security for Consumer Electronics A. Sengupta and S. Mohanty VLSI and Post-CMOS Devices, Circuits and Modelling R. Dhiman and R. Chandel (Editors) High-Quality Liquid Crystal Displays and Smart Devices vol. 1 and vol. 2 S. Ishihara, S. Kobayashi and Y. Ukai (Editors) Fibre Bragg Gratings in Harsh and Space Environments: Principles and applications B. Aı¨ssa, E.I. Haddad, R.V. Kruzelecky, W.R. Jamroz Self-Healing Materials: From fundamental concepts to advanced space and electronics applications, 2nd Edition B. Aı¨ssa, E.I. Haddad, R.V. Kruzelecky, W.R. Jamroz

Radio Frequency and Microwave Power Amplifiers Volume 2: Efficiency and Linearity Enhancement Techniques Edited by Andrei Grebennikov

The Institution of Engineering and Technology

Published by The Institution of Engineering and Technology, London, United Kingdom The Institution of Engineering and Technology is registered as a Charity in England & Wales (no. 211014) and Scotland (no. SC038698). † The Institution of Engineering and Technology 2019 First published 2019 This publication is copyright under the Berne Convention and the Universal Copyright Convention. All rights reserved. Apart from any fair dealing for the purposes of research or private study, or criticism or review, as permitted under the Copyright, Designs and Patents Act 1988, this publication may be reproduced, stored or transmitted, in any form or by any means, only with the prior permission in writing of the publishers, or in the case of reprographic reproduction in accordance with the terms of licences issued by the Copyright Licensing Agency. Enquiries concerning reproduction outside those terms should be sent to the publisher at the undermentioned address: The Institution of Engineering and Technology Michael Faraday House Six Hills Way, Stevenage Herts, SG1 2AY, United Kingdom www.theiet.org While the authors and publisher believe that the information and guidance given in this work are correct, all parties must rely upon their own skill and judgement when making use of them. Neither the authors nor publisher assumes any liability to anyone for any loss or damage caused by any error or omission in the work, whether such an error or omission is the result of negligence or any other cause. Any and all such liability is disclaimed. The moral rights of the authors to be identified as authors of this work have been asserted by them in accordance with the Copyright, Designs and Patents Act 1988.

British Library Cataloguing in Publication Data A catalogue record for this product is available from the British Library

ISBN 978-1-83953-038-8 (Hardback Volume 2) ISBN 978-1-83953-039-5 (PDF Volume 2) ISBN 978-1-83953-036-4 (Hardback Volume 1) ISBN 978-1-83953-037-1 (PDF Volume 1) ISBN 978-1-83953-040-1 (Hardback Volumes 1 and 2)

Typeset in India by MPS Limited Printed in the UK by CPI Group (UK) Ltd, Croydon

Contents

Preface List of contributors

1 High-efficiency power amplifier design Andrei Grebennikov, Mury Thian and Narendra Kumar 1.1

1.2

1.3

1.4

1.5

1.6 1.7

Class-F circuit design 1.1.1 Idealized Class-F mode 1.1.2 Class F with maximally flat waveforms 1.1.3 Class F with quarterwave transmission line 1.1.4 Effect of saturation resistance 1.1.5 Load networks with lumped and distributed parameters 1.1.6 Design examples of Class-F power amplifiers Inverse Class F 1.2.1 Idealized inverse Class-F mode 1.2.2 Inverse Class F with quarterwave transmission line 1.2.3 Load networks with lumped and distributed parameters 1.2.4 Design example of inverse Class-F power amplifier Class E with shunt capacitance and series filter 1.3.1 Optimum load-network parameters 1.3.2 Effect of saturation resistance, finite switching time, and nonlinear shunt capacitance 1.3.3 Load network with transmission lines 1.3.4 Practical Class-E power amplifiers Class E with finite dc-feed inductance 1.4.1 General analysis and optimum load-network parameters 1.4.2 Parallel-circuit Class E 1.4.3 Even-harmonic Class E 1.4.4 Load networks with transmission lines Class E with shunt capacitance and shunt filter 1.5.1 Basic analysis and optimum load-network parameters 1.5.2 Load network with transmission lines 1.5.3 Design example of transmission-line Class-E power amplifier Biharmonic Class-EM power amplifier High-efficiency broadband power amplifiers 1.7.1 Broadband Class E with shunt capacitance

xi xv

1 1 3 7 11 14 16 19 23 25 27 28 31 35 35 40 43 45 48 48 52 56 59 62 62 67 68 70 76 76

vi

2

3

4

Radio frequency and microwave power amplifiers, volume 2 1.7.2 Broadband parallel-circuit Class E 1.7.3 High-efficiency mixed-mode broadband power amplifier References

82 90 92

High-efficiency Doherty power amplifiers Andrei Grebennikov

99

2.1 Basic Doherty amplifier structure 2.2 Asymmetric Doherty amplifiers 2.3 Multistage Doherty amplifiers 2.4 Inverted Doherty amplifiers 2.5 Integrated Doherty amplifiers 2.6 Broadband Doherty amplifiers References

99 102 107 113 117 122 132

Envelope tracking techniques Florinel Balteanu

137

3.1 Envelope tracking technique 3.2 Envelope tracking for cellular LTE FDD and TDD 3.3 Power amplifier under envelope tracking operation 3.4 Envelope tracking systems 3.5 Envelope tracking circuitry 3.6 Envelope tracking for high power 3.7 Local ET linearization 3.8 Multilevel supply envelope tracking 3.9 Envelope tracking calibration 3.10 Envelope tracking noise References

138 141 142 146 149 159 162 163 164 166 170

Outphasing power amplifiers Taylor Wallis Barton and Paolo Enrico de Falco

175

4.1

177 177 178 178 179 180 183 186 189 191 192 197

4.2

4.3

A brief history 4.1.1 1935–1960: origins 4.1.2 1974: linear amplification with nonlinear components 4.1.3 2000s: resurgence in interest Outphasing operation 4.2.1 Isolating combining: LINC 4.2.2 Nonisolating combining: load modulation 4.2.3 Chireix combining 4.2.4 Mixed-mode operation Power combiner variants 4.3.1 Multiway power combining networks 4.3.2 Co-design of PAs and combiner

Contents 4.4

Analysis of outphasing branch PA design 4.4.1 Load modulation mechanisms 4.4.2 Ideal load modulation trajectories 4.4.3 Optimal load trajectories with nonlinear model 4.4.4 Implications for outphasing PA design 4.5 Input signal synthesis 4.5.1 RF-input outphasing 4.5.2 Arbitrary input drives 4.5.3 Conclusion References 5 Combiner synthesis for active load-modulation-based power amplifiers ¨ zen, William Hallberg and Christian Fager Mustafa O 5.1 5.2

Introduction Generalized combiner synthesis technique for Doherty and outphasing PAs 5.3 Applications of the novel Doherty continuous design space 5.3.1 Solving for maximum efficiency 5.3.2 Solving for efficiency and linearity 5.3.3 GaN HEMT Doherty PA design 5.4 Applications to outphasing PA design 5.4.1 A 2.14 GHz GaN HEMT outphasing PA design 5.5 Summary and future outlook 5.5.1 Summary 5.5.2 Future outlook References 6 Power amplifier design based on nonlinear embedding models with design examples Patrick Roblin and Karun Rawat 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8

Introduction Motivation for nonlinear embedding Embedding model Class-B example and harmonic injection Class-F theory and design example Doherty PA design example Chireix PA design example Continuous Class-B/J power amplifier 6.8.1 Design space analysis with nonlinear-embedding technique 6.8.2 Broadband Class-B/J mode PA design using model-based nonlinear-embedding technique

vii 198 198 200 205 208 208 210 216 216 217 225 225 227 234 235 238 240 246 248 250 250 251 251

255 255 257 260 264 267 272 277 281 282 286

viii

Radio frequency and microwave power amplifiers, volume 2 6.9

Continuous Class-F power amplifier 6.9.1 Investigating feasible design space 6.9.2 Broadband continuous Class-F PA design using model-based nonlinear-embedding technique References 7

8

9

288 289 291 293

CMOS power amplifiers Andrei Grebennikov and Mustafa Acar

297

7.1 Device modeling 7.2 Basic structures and techniques 7.3 Stacked power amplifiers 7.4 Millimeter-wave power amplifiers 7.5 Broadband power amplifiers 7.6 High-efficiency Class-E and Class-F power amplifiers 7.7 Doherty architectures 7.8 Linearization References

297 301 304 308 313 319 329 333 338

Behavioral modeling and linearization Richard Neil Braithwaite

345

8.1

Wireless communication overview 8.1.1 RF channel and channel capacity 8.1.2 BTS transmitter 8.2 Power amplifier nonlinearities 8.2.1 PA nonlinearities 8.2.2 Measurements of nonlinear behavior 8.2.3 Behavioral modeling 8.3 Linearization 8.3.1 Digital predistortion 8.3.2 Feedforward compensation 8.4 Further explanations 8.4.1 Using odd and even polynomial basis waveforms 8.4.2 Effect of PA saturation on DPD coefficient estimation 8.4.3 Modifications to descent-based estimators 8.4.4 Least squares (LS) estimation using batch processing 8.4.5 Recursive least squares 8.5 Conclusion References

345 346 347 348 349 350 354 359 359 367 372 372 373 374 375 377 382 383

Multiband/multichannel power amplifier linearization Meenakshi Rawat and Patrick Roblin

387

9.1 9.2

387 388

Distortion inducing elements in multichannel transmission Distortion in multiband transmission

Contents 9.3

Distortion components in MIMO transmission 9.3.1 Nonlinear distortion 9.3.2 Linear distortion 9.4 Digital predistortion techniques for multichannel transmission 9.4.1 Digital predistortion techniques for multiband transmission 9.4.2 Digital predistortion techniques for multiple-channel transmission 9.5 Digital predistortion techniques for multiband/multichannel transmission in the presence of modulator imperfections 9.6 Application considerations of DPD models for multiband/multichannel transmission References 10 Distributed power amplifiers Andrei Grebennikov and Narendra Kumar 10.1 Basic principles of distributed amplification 10.2 Microwave GaAs FET and HEMT distributed amplifiers 10.2.1 Basic configuration with microstrip lines 10.2.2 Basic configuration with lumped elements 10.2.3 Capacitive coupling 10.2.4 Bandpass configuration 10.2.5 Parallel and series feedback 10.3 Distributed amplifiers with tapered lines 10.4 Cascode distributed amplifiers 10.5 Extended resonance technique 10.6 Cascaded distributed amplifiers 10.7 CMOS distributed amplifiers References Index

ix 390 391 391 392 394 408 411 415 417 421 421 427 428 432 434 435 437 439 449 456 458 462 466 473

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Preface

The main objective of this two-volume edited book is to present by world-class technical experts all relevant information required for RF and microwave power amplifier design including well-known historical and recent novel schematic configurations, theoretical approaches, circuit simulation results, and practical implementation techniques. This comprehensive book can be very useful for lecturing to promote the systematic way of thinking with analytical calculations, circuit simulation, and practical verification, thus making a bridge between theory and practice of RF and microwave engineering. As it often happens, a new result is the wellforgotten old one. Therefore, the demonstration of not only new results based on new technologies or circuit schematics is given, but some sufficiently old ideas or approaches are also introduced and clearly explained that could be very useful in modern design practice or could contribute to appearance of new general architectural ideas and specific circuit and system-design techniques. As a result, this unique two-volume comprehensive book is intended for and can be recommended to university-level professors as a comprehensive reference material to help in lecturing for graduate and postgraduate students, to researchers and scientists to combine the theoretical analysis with practical design and to provide a sufficient basis for innovative ideas and circuit and system-design techniques, and to practicing designers and engineers as an anthology of many well-known and novel practical circuits, architectures, and theoretical approaches with detailed description of their operational principles and applications. The book is divided into two volumes. Volume 1 comprises six chapters and Volume 2 comprises ten chapters. Volume 1 begins with introductory Chapter 1 explaining the basic principles of power amplifier design including basic classes of operation, load-line definition, power gain and stability, impedance matching concept and application aspects, push–pull and balanced structures, transmissionline transformers and combiners. Chapter 2 covers basics of the empirical nonlinear device models implemented in CAD tools focusing on GaN HEMT including its physical phenomena like thermal effects, breakdown, dispersion, and self-heating. Harmonic load-pull tuners are important systems for characterizing power transistors and amplifiers and finding the impedances needed for gaining optimum performance levels. Chapter 3 includes history, techniques, progress, and challenges in power amplifier load-pull characterization using passive and active tuning. Different matching network design techniques are described in Chapters 4–6 with many practical examples performed using MATLAB programing software.

xii

Radio frequency and microwave power amplifiers, volume 2

Chapter 4 is dedicated to automated Darlington synthesis to construct the lossless matching networks with lumped and distributed elements via correction techniques using low-pass, bandpass, and high-pass network functions. Chapter 5 covers basic “real-frequency” techniques to construct lossless matching networks by assessing the best performance and solving the generalized single and double-matching problems. Chapter 6 describes the design of broadband RF and microwave singlestage and multistage power amplifiers based on the “simplified real frequency” techniques using lumped elements, commensurate transmission lines, and mixed lumped and distributed elements. Modern commercial and military communication systems require highefficiency long-term operating conditions. In Volume 2, Chapter 1 describes in detail the possible load-network solutions to provide a high-efficiency power amplifier operation based on using Class-F, inverse Class-F, and different Class-E operation modes depending on the technical requirements. In Class-F power amplifiers analyzed in the frequency domain, the fundamental and harmonic load impedances are optimized by short-circuit termination and open-circuit peaking to control the voltage and current waveforms at the drain of the device to obtain maximum efficiency. In Class-E power amplifiers analyzed in the time domain, an efficiency improvement is achieved by realizing the on/off switching operation with special current and voltage waveforms so that high voltage and high current do not exist at the same time. Chapter 2 describes the basic Doherty approach to the power-amplifier design, operational principle, and modern trends in Doherty amplifier design techniques using asymmetric multi-way, multistage, inverted, and broadband architectures with examples of the integrated and monolithic Doherty amplifier implementations. Envelope-tracking technology is used in actual smartphone to improve efficiency as well as linearity for RF and microwave power amplifiers for LTE and Wi-Fi communication signals. Chapter 3 presents the envelope tracking fundamentals as well as the architecture implementation such as fast dc–dc, multilevel supply, and hybrid architectures. Outphasing architectures generate load modulation through phase control of multiple nonlinear PAs, offering the potential for linear amplification with high efficiency over a wide range of output powers. Chapter 4 describes an overview of outphasing history, fundamental principles, modern techniques, and implementation approaches that are making outphasing an attractive option for linear-efficient RF and microwave power amplifiers. Chapter 5 has focused on the importance of the combiner in the design of Doherty and outphasing power amplifiers that plays a detrimental role for the efficiency enhancement in both these architectures since it provides the desired mutual active load modulation between two amplifying branches. Several of the functions that traditionally are part of the combiner realization, such as impedance matching, offset lines, impedance inversion, transistor scaling, are absorbed into the synthesized combiner network. This results in a continuum of new outphasing and Doherty solutions that were used to design power amplifiers with higher efficiency, better linearity, greater gain, and smaller size.

Preface

xiii

It is now well established that power amplifier designers need to control the internal mode of operation of transistors at the current-source reference planes to better optimize the efficiency of power amplifiers. The traditional approach has been to rely on multi-harmonic load and source pulling while monitoring the load lines at the current-source reference planes using a de-embedding model. However, given the tremendously huge search space for the load and source multi-harmonic terminations required to find the desired internal waveforms; it is greatly preferable to use a nonlinear embedding device model described in Chapter 6 to obtain in a single simulation, the required multi-harmonic impedances at the package or extrinsic reference planes which implement the desired class of operation. Various examples of design techniques for high-efficiency single-ended power amplifiers, two-way and four-way Chireix and Doherty structures are presented. Chapter 7 focuses on the basic circuit schematics of the CMOS power amplifiers for different RF and microwave applications including common-source, common-gate, cascode, differential pair, and stacked configuration techniques including power combining. CMOS performance issues such as low breakdown voltage, hot carrier degradation, effect of substrate and device parasitics, and practical integrated circuit implementation features are discussed, as well as efficiency-enhancement techniques for microwave and mm-wave CMOS power amplifiers. Chapter 8 describes the basic principles of behavioral modeling and analog and digital linearization of power amplifiers used in radio frequency transmitters and presents the analog linearization structures such as feedforward compensation and analog predistortion. Measures and models of the power amplifier nonlinearity are reviewed. Most of the spectrum-efficient techniques proposed in modern communication systems such as carrier aggregation require either wideband operation (in-contiguous carrier aggregation) or multiband operation (in the case of noncontiguous operation). Chapter 9 focuses on investigating the practical implementation of spectrum-efficient techniques proposed for 4G/5G communication systems and provide software-defined solutions for the power-efficient operation of transmitter/receiver system. Finally, the basic principles of distributed amplification and circuit implementation of microwave GaAs FET distributed amplifiers are introduced and described in Chapter 10. Different architectures such as cascode and cascaded distributed power amplifiers and different techniques based on using tapered lines and extended resonant approach are given, with several examples of monolithic implementation of distributed-power amplifiers based on pHEMT, GaN HEMT, and CMOS technologies. Andrei Grebennikov

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List of contributors

Mustafa Acar

NXP Semiconductors, Netherlands

Iltcho Angelov Florinel Balteanu

Chalmers University of Technology, Sweden Skyworks Solutions, USA

Taylor Wallis Barton Richard Neil Braithwaite

University of Colorado Boulder, USA Consultant, USA

Christian Fager Paolo Enrico de Falco

Chalmers University of Technology, Sweden University of Colorado Boulder, USA

Andrei Grebennikov

Sumitomo Electric Europe Ltd., UK

William Hallberg Narendra Kumar ¨ zen Mustafa O

Chalmers University of Technology, Sweden University of Malaya, Malaysia

Karun Rawat

Ericsson AB, Sweden Indian Institute of Technology Roorkee, India

Meenakshi Rawat Patrick Roblin

Indian Institute of Technology Roorkee, India Ohio State University, USA

Mury Thian

Queens University Belfast, UK

Mattias Thorsell Christos Tsironis

Chalmers University of Technology, Sweden Focus Microwaves, Canada

Tudor Williams Siddik Yarman

Mesuro, UK Istanbul University-Cerrahpasa, Turkey

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Chapter 1

High-efficiency power amplifier design Andrei Grebennikov1, Mury Thian2, and Narendra Kumar3

High efficiency of the power amplifier can be obtained by using Class-F and Class-E operation modes or their different approximations, depending on the technical requirements. In all cases, an efficiency improvement in practical implementation is achieved by providing the nonlinear operation conditions when an active device can operate in pinch-off and saturation regions during most of the period, resulting in the nonsinusoidal collector current and voltage waveforms, symmetrical for Class-F and asymmetrical for Class-E operation modes. In Class-F power amplifiers analyzed in frequency domain, the fundamental-frequency and harmonic load impedances are optimized by short-circuit termination and open-circuit peaking to control the voltage and current waveforms at the device output to obtain maximum efficiency. In Class-E power amplifiers analyzed in time domain, an efficiency improvement is achieved by realizing the on/off active device switching operation (saturation and pinch-off regions) with special current and voltage waveforms so that high voltage and high current do not concur at the same time.

1.1 Class-F circuit design The possibility to maximize efficiency in a vacuum-tube amplifier was first demonstrated in the late 1910s by a suitable choice of grid voltage with the corresponding anode arrangement to produce an anode current or voltage waveform which is composed principally of the fundamental frequency and third harmonic and has a “Meander”-like form [1]. It was proposed to use the load network with a third- or higher-harmonic trap in series to the anode in practical implementation, as shown in Figure 1.1(a) [2,3]. However, effect of the inclusion of a third-harmonic resonator was described and analyzed in detail only 1.5 decades later [4,5]. It was shown that the symmetrical anode voltage waveform and level of its depression can be provided with opposite phase conditions at the waveform midpoints between the fundamental and third harmonic and optimum value of the ratio between their 1

Sumitomo Electric Europe Ltd., Hertfordshire, United Kingdom ECIT Institute, Queen’s University Belfast, Belfast, United Kingdom 3 Faculty of Engineering, University of Malaya, Kuala Lumpur, Malaysia 2

2

Radio frequency and microwave power amplifiers, volume 2 3f0 RL

f0

(a)

3f0

5f0 f0

RL

(b)

Figure 1.1 (a) Biharmonic and (b) polyharmonic Class-F power amplifiers voltage amplitudes. In addition, it was noted that high operation efficiency can be achieved even when impedance of the third-harmonic resonator is equal or slightly greater than that of the fundamental tank. To maximize efficiency of the vacuumtube amplifier with better approximating a square voltage anode waveform, it was also suggested to use an additional resonator tuned to the fifth harmonic, as shown in Figure 1.1(b) [6]. Figure 1.2 shows that the shapes of the voltage and current waveforms can be significantly changed with increasing fundamental voltage amplitude by adding even one additional harmonic component being properly phased. For example, the combination of the fundamental-frequency and third-harmonic components being 180
out-of-phase at center points results in a flattened voltage waveform with depression in its center. It is clearly seen from Figure 1.2(a) that the proper ratio between the amplitudes of the fundamental and third-harmonic components can provide the flattened voltage waveform with minimum depression and maximum difference between its peak amplitude and amplitude of the fundamental component. Similarly, the combination of the fundamental-frequency and secondharmonic components, being in phase at the center points, flattens the current waveform corresponding to the maximum values of the voltage waveform and sharpens the current waveform corresponding to the minimum values of the voltage waveform, as shown in Figure 1.2(b). The optimum ratio between the amplitudes of the current fundamental-frequency and second-harmonic components can maximize a peak value of the current waveform, with its minimized value determined by the device saturation resistance in a practical circuit. Thus, power loss due to the active device can be minimized because the results of the integration over period when the minimum voltage corresponds to the maximum current will give a small value compared with the power delivered to the load.

High-efficiency power amplifier design v

3

n = 1, 3

Vcc

(a)

0

i

p

2p

ωt

p

2p

ωt

n = 1, 2

I0

(b)

0

Figure 1.2 Fourier (a) voltage and (b) current waveforms with third and second harmonics, respectively

1.1.1 Idealized Class-F mode Generally, an infinite number of the odd-harmonic tank resonators can maintain a square collector voltage waveform, also providing a half-sinusoidal current waveform. Figure 1.3(a) shows such a Class-F power amplifier with a multiple-resonator output filter to control the harmonic content of its collector (anode or drain) voltage and current waveforms, thereby shaping them to reduce dissipation and to increase efficiency [7]. To simplify an analysis of a Class-F power amplifier, whose simplified equivalent circuit is shown in Figure 1.3(b), the following several assumptions are introduced: ●

● ●

● ●

Transistor has zero saturation voltage, zero saturation resistance, and infinite off-resistance, and its switching action is instantaneous and lossless; RF choke allows only a dc current and has no resistance; Quality factors of all parallel resonant circuits have infinite impedance at the corresponding harmonic and zero impedance at other harmonics; There are no losses in the circuit except only into the load RL; and Operation mode with a 50% duty ratio.

4

Radio frequency and microwave power amplifiers, volume 2 3f0

5f0

(2n + 1)f0 RL

f0

(a) + Vcc – 3f0 I0 Vcc

5f0

(2n + 1)f0

i v

vodd

ieven

f0

iR

RL

(b)

Figure 1.3 Basic circuits of Class-F power amplifier with parallel resonant circuits To determine the idealized collector voltage and current waveforms, let us consider the distribution of voltages and currents in the load network, assuming the sinusoidal fundamental current flowing into the load as iR(wt) ¼ IRsin(wt), where IR is its amplitude. The voltage v(wt) across the switch can be represented as a sum of the dc voltage Vcc, the fundamental voltage vR ¼ iRRL across the load resistor, and the voltage vodd across the odd-harmonic resonators: vðwtÞ ¼ Vcc þ vodd ½ð2n þ 1Þwt þ vR ðwtÞ

(1.1)

Because the time moment t was chosen arbitrarily, by introducing a phase shift of p, (1.1) can be rewritten for periodical sinusoidal functions as vðwt þ pÞ ¼ Vcc  vodd ½ð2n þ 1Þwt  vR ðwtÞ

(1.2)

Then, the summation of (1.1) and (1.2) yields: vðwtÞ ¼ 2Vcc  vðwt þ pÞ

(1.3)

From (1.3), it follows that the maximum value of the collector voltage cannot exceed a value of 2Vcc and the time duration with a maximum voltage of v ¼ 2Vcc coincides with the time duration with a minimum voltage of v ¼ 0. Because the collector voltage is zero when the switch is turned on, the only possible waveform for the collector voltage is a square wave, composing of only dc, fundamentalfrequency, and odd-harmonic components. During the interval 0 < wt  p when the switch is turned on, the current i(wt) flowing through the switch can be written as iðwtÞ ¼ I0 þ ieven ð2nwtÞ þ iR ðwtÞ

(1.4)

High-efficiency power amplifier design

5

whereas during the interval p < wt  2p when the switch is turned off, the current i(wt þ p) is equal to zero, resulting in 0 ¼ I0 þ ieven ð2nwtÞ  iR ðwtÞ

(1.5)

Then, by substituting (1.5) into (1.4), we can rewrite (1.4) as iðwtÞ ¼ 2iR ðwtÞ ¼ 2IR sinðwtÞ

(1.6)

from which it follows that the amplitude of the current flowing through the switch during the interval 0 < wt  p is two times greater than the amplitude of the fundamental current. Thus, in a general case of entire interval, (1.4) can be rewritten as iðwtÞ ¼ IR ðsin wt þ jsin wtjÞ

(1.7)

which means that the switch current represents half-sinusoidal pulses with the amplitude equal to double load current amplitude. Consequently, for a purely sinusoidal current flowing into the load, which is shown in Figure 1.4(a), the ideal collector voltage and current waveforms can be represented by the appropriate normalized waveforms shown in Figure 1.4(b) and (c), respectively. Here, a sum of the fundamental and odd harmonics approximates a square voltage waveform and a sum of the fundamental and even harmonics approximates a half-sinusoidal collector current waveform. As a result, the shapes of the collector current and voltage waveforms provide a condition when the current and voltage do not overlap simultaneously. Such a condition, with symmetrical collector voltage and current waveforms, corresponds to an idealized Class-F operation mode with 100% collector efficiency. A Fourier analysis of the current and voltage waveforms allows us to obtain the following equations for the dc current and the fundamental voltage and current components in the collector voltage and current waveforms. The dc current I0 can be calculated from (1.7) as ð 1 p 2IR (1.8) 2IR sin wt dwt ¼ I0 ¼ p 2p 0 The fundamental current component can be calculated from (1.7) as ð 1 p 2IR sin2 wt dwt ¼ IR I1 ¼ p 0 The fundamental voltage component can be calculated using (1.3) as ð 1 2p 4Vcc 2Vcc sinðwt þ pÞdwt ¼ V1 ¼ VR ¼ p p p

(1.9)

(1.10)

where VR ¼ IRRL is the fundamental voltage amplitude across the load resistor RL.

6

Radio frequency and microwave power amplifiers, volume 2 iR/I0

1.5 1.0 0.5 wt,°

0 60

120

180

240

300

60

120

180

240

300

wt,°

60

120

180

240

300

wt,°

–0.5 –1.0 –1.5 (a) v/Vcc

2.0 1.5 1.0 0.5 0 0 (b)

i/I0

3.0 2.0 1.0 0

0

(c)

Figure 1.4 Ideal waveforms of Class-F power amplifier

Then, the dc power and output power at the fundamental frequency are calculated by 2Vcc IR p

(1.11)

V1 I1 2Vcc IR ¼ 2 p

(1.12)

P0 ¼ Vcc I0 ¼ and P1 ¼

High-efficiency power amplifier design

7

respectively, resulting in a theoretical collector efficiency with maximum value of h¼

P1 ¼ 100% P0

(1.13)

In this case, the impedance conditions seen by the device collector for an idealized Class-F mode must be equal to Z1 ¼ R1 ¼ Z2n ¼ 0

8 Vcc p 2 I0

(1.14)

for even harmonics

(1.15)

Z2nþ1 ¼ 1 for odd harmonics

(1.16)

1.1.2 Class F with maximally flat waveforms Although it is impossible to realize the ideal harmonic impedance conditions in practical implementation, the peaking of at least several current and voltage harmonic components can be provided to achieve a high operation efficiency of the power amplifier. The more the voltage waveform provided by higher-order harmonic components can be flattened, the less power dissipation due to flowing of the output current (when the output voltage is extremely small) occurs. To understand the basic design principles and to numerically calculate the power amplifier efficiency according to the contribution of an appropriate number of the harmonic components of voltage and current waveforms, it is convenient to use a design technique based on a Class-F approximation with maximally flat waveforms [8]. In this case, the load network is assumed ideal to deliver only the fundamentalfrequency power to the load without loss. The active device represents an ideal multiharmonic current source with zero saturation voltage and output capacitance for providing instant switching between saturation and pinch-off operation regions. Flattening of the voltage and current waveforms to realize a Class-F operation can be accomplished by using odd-harmonic components to approximate a rectangular voltage waveform and even-harmonic components to approximate a half-sinusoidal current waveform given by vðwtÞ ¼ Vcc þ V1 sin wt þ

1 X

Vn sin nwt

(1.17)

n¼3;5;7;:::

iðwtÞ ¼ I0  I1 sin wt 

1 X

In cos nwt

(1.18)

n¼2;4;6;:::

For the symmetrical flattened voltage waveforms shown in Figure 1.5, the medium points where the voltage waveform reaches its maximum and minimum values are at wt ¼ p/2 and wt ¼ 3p/2, respectively. Maximum flatness at minimum voltage requires the even-order derivatives to be zero at wt ¼ 3p/2. As the odd-order

8

Radio frequency and microwave power amplifiers, volume 2 v/Vcc n = 1, 3 2.0 1.5 1.0 0.5

(a)

0

p/2

p

3p/2

wt

v/Vcc n = 1, 3, 5 2.0 1.5 1.0 0.5

(b)

0

p/2

p

3p/2

wt

v/Vcc n = 1, 3, 5, 7 2.0 1.5 1.0 0.5

(c)

0

p/2

p

3p/2

wt

Figure 1.5 Voltage waveforms for nth-harmonic peaking derivatives are equal to zero because cos(np/2) ¼ 0 for odd n, it is necessary to define the even-order derivatives of the voltage waveform given by (1.17). For the third-harmonic peaking when only the third-harmonic component together with the fundamental one is present, their optimum amplitudes are defined as 9 V1 ¼ Vcc 8

1 V3 ¼ Vcc 8

(1.19)

High-efficiency power amplifier design

9

The voltage waveforms for the third-harmonic peaking (n ¼ 1, 3), fifthharmonic peaking (n ¼ 1, 3, 5), and seventh-harmonic peaking (n ¼ 1, 3, 5, 7) are shown in Figure 1.5. For the symmetrical current waveforms shown in Figure 1.6, the medium points where the current waveform reaches its minimum and maximum values are i/I0

n = 1, 2

2.5 2.0 1.5 1.0 0.5 (a)

0

p/2

i/I0

p

3p/2

wt

p

3p/2

wt

3p/2

wt

n = 1, 2, 4

2.5 2.0 1.5 1.0 0.5 (b)

0

p/2

i/I0 n = 1, 2, 4, 6 2.5 2.0 1.5 1.0 0.5 (c)

0

p/2

p

Figure 1.6 Current waveforms for nth-harmonic peaking

10

Radio frequency and microwave power amplifiers, volume 2

at wt ¼ p/2 and wt ¼ 3p/2, respectively. As the odd-order derivatives are equal to zero because cos(p/2) ¼ 0 and sin(np/2) ¼ 0 for even n, it is sufficient to determine the even-order derivatives of the current waveform given by (1.18). Maximum flatness at minimum current requires the even-order derivatives to be zero at wt ¼ p/2. For the second-harmonic peaking when only the second-harmonic component together with the fundamental one is present, their optimum amplitudes are defined by 4 I1 ¼ I0 3

1 I2 ¼ I0 3

(1.20)

The current waveforms for the second-harmonic peaking (n ¼ 1, 2), fourthharmonic peaking (n ¼ 1, 2, 4), and sixth-harmonic peaking (n ¼ 1, 2, 4, 6) are shown in Figure 1.6. The effectiveness of the operations modes with different voltage and current harmonic peaking can be compared by calculating the collector (drain) efficiency h of each operation mode according to h¼

P1 1 V1 I1 ¼ : P0 2 Vcc I0

(1.21)

The resultant efficiencies for various combinations of the voltage and current harmonic components are given in Table 1.1, which shows that the efficiency increases with an increase in the number of voltage and current harmonic components. To increase efficiency, it is more desirable to provide harmonic peaking in consecutive numerical order (both for voltage and current harmonic components) than to increase the number of the harmonic components into only voltage or current waveforms. Class-F operation becomes mostly effective in comparison with Class-B operation if at least third-voltage harmonic peaking and fourth-current harmonic peaking are realized. An inclusion of fifth-voltage harmonic component increases the efficiency to 83.3%. An additional inclusion of sixth-current harmonic component into the current waveform and a seventh-voltage harmonic component into the voltage waveform leads to efficiencies up to 94%.

Table 1.1 Resultant efficiencies for various combinations of voltage and current harmonic components Voltage harmonic components

Current harmonic components

1

1, 3

1, 3, 5

1, 3, 5, 7

1, 3, 5, . . . , ?

1 1, 1, 1, 1,

1/2 ¼ 0.500 2/3 ¼ 0.667 32/45 ¼ 0.711 128/175 ¼ 0.731 p/4 ¼ 0.785

9/16 ¼ 0.563 3/4 ¼ 0.750 4/5 ¼ 0.800 144/175 ¼ 0.823 9p/32 ¼ 0.884

75/128 ¼ 0.586 25/32 ¼ 0.781 5/6 ¼ 0.833 6/7 ¼ 0.857 75p/256 ¼ 0.920

1225/2048 ¼ 0.598 1225/1536 ¼ 0.798 245/288 ¼ 0.851 7/8 ¼ 0.875 1225p/4096 ¼ 0.940

2/p ¼ 0.637 8/3p ¼ 0.849 128/45p ¼ 0.905 512/175p ¼ 0.931 1 ¼ 1.000

2 2, 4 2, 4, 6 2, 4, . . . , ?

High-efficiency power amplifier design

11

1.1.3 Class F with quarterwave transmission line Ideally, a control of an infinite number of the harmonics maintaining a square voltage waveform and a half-sinusoidal current waveform at the device output can be provided by using a serious quarterwave transmission line and a parallel-tuned resonant circuit, as shown in Figure 1.7. This type of a Class-F power amplifier was initially proposed to be used at higher frequencies, where implementation of the load networks with only lumped elements is difficult and the parasitic device output (lead or package) inductor is sufficiently small [9]. In this case, the quarterwave transmission line transforms the load impedance according to R¼

Z02 RL

(1.22)

where Z0 is the characteristic impedance of a transmission line. For even harmonics, the short circuit on the load side of the transmission line is repeated, thus producing a short circuit at the drain. However, the short circuit at the load produces an open circuit at the drain for odd harmonics with resistive load at the fundamental. Generally, at low drive level, the active device acts as a current source (voltage-controlled in the case of the MOSFETs or MESFETs and currentcontrolled in the case of bipolar transistors). As input drive increases, the active device enters saturation resulting in a harmonic-generation process. Because the quarterwave transmission line presents the high impedance conditions to all odd harmonics, all odd harmonics provide a proper contribution to the output voltage waveform. As a result, at high drive level, the output voltage waveform approximates a square wave, and the transistor is saturated for a full half-cycle. In this case, the transistor acts as a switch rather than a saturating current source. An alternative configuration of the Class-F power amplifier with a shunt transmission line located in between the dc power supply and the device collector is shown in Figure 1.8(a). In this case, there is no need to use an RF choke and a series blocking capacitor because a series fundamentally tuned resonant L0C0 circuit is Vdd

Cb

vin

Z0, l/4

R

C0

L0

RL

Figure 1.7 Class-F power amplifier with series quarterwave transmission line

12

Radio frequency and microwave power amplifiers, volume 2 Vcc

Cb

λ /4 C0

L0

R

(a)

vrefl, irefl vinc, iinc

l Vcc

L0

iT

x λ /4

0

C0

iR

i v

R

(b)

Figure 1.8 Class-F power amplifier with shunt quarterwave transmission line

used instead of a parallel fundamentally tuned resonant circuit. However, unlike the case with a series quarterwave transmission line, such a Class-F load-network configuration with a shunt quarterwave transmission line does not provide an impedance transformation. Therefore, the load resistance R, which is equal to the equivalent active device output resistance at the fundamental frequency, must then be transformed to the standard load resistance RL. Let us now derive analytically fundamental properties of a quarterwave transmission line. The transmission line in time domain can be represented as an element with finite delay time depending on its electrical length. Consider a simplified load network of the Class-F power amplifier shown in Figure 1.8(b), which consists of a parallel quarterwave transmission line grounded at the end through the dc power supply, a series fundamentally tuned L0C0 circuit, and a load resistance R. In an idealized case, the intrinsic device output capacitance is assumed to be negligible to affect the power amplifier performance. The loaded quality factor QL of the series resonant L0C0 circuit is high enough to provide the sinusoidal output current iR flowing into the load R.

High-efficiency power amplifier design

13

To define the collector voltage and current waveforms, consider the electrical behavior of a homogeneous lossless quarterwave transmission line connected to the dc voltage supply with RF grounding [10,11]. In this case, the voltage v(t, x) in any cross section of such a transmission line can be represented as a sum of the incident voltage vinc(wt  2px/l) and the reflected voltage vrefl(wt þ 2px/l), generally with an arbitrary waveform. When x ¼ 0, the voltage v(t, x) is equal to the collector voltage: vðwtÞ ¼ vðt; 0Þ ¼ vinc ðwtÞ þ vrefl ðwtÞ

(1.23)

At the same time, at another end of the transmission line when x ¼ l/4, the voltage is constant and equal to Vcc ¼ vðt; p=2Þ ¼ vinc ðwt  p=2Þ þ vrefl ðwt þ p=2Þ

(1.24)

Because the time moment t was chosen arbitrarily, let us rewrite (1.24) using a phase shift of p/2 for each voltage by vinc ðwtÞ ¼ Vcc  vrefl ðwt þ pÞ

(1.25)

Substituting (1.25) into (1.23) yields: vðwtÞ ¼ vrefl ðwtÞ  vrefl ðwt þ pÞ þ Vcc

(1.26)

Consequently, for the phase shift of p, the collector voltage can be obtained by vðwt þ pÞ ¼ vrefl ðwt þ pÞ  vrefl ðwt þ 2pÞ þ Vcc

(1.27)

For an idealized operation condition with a 50% duty ratio when during half a period the transistor is turned on and during another half a period the transistor is turned off with overall period of 2p, the voltage vrefl(wt) can be considered the periodical function with a period of 2p: vrefl ðwtÞ ¼ vrefl ðwt þ 2pÞ

(1.28)

As a result, the summation of (1.26) and (1.27) results in the basic expression for collector voltage in the form: vðwtÞ ¼ 2Vcc  vðwt þ pÞ

(1.29)

From (1.29), which is similar to (1.3), it follows that the maximum value of the collector voltage cannot exceed a value of 2Vcc and the time duration with maximum voltage of v ¼ 2Vcc coincides with the time duration with minimum voltage of v ¼ 0. Similarly, the equation for the current iT flowing into the quarterwave transmission line can be obtained by iT ðwtÞ ¼ iT ðwt þ pÞ

(1.30)

which means that the period of a signal flowing into the quarterwave transmission line is equal to p because it contains only even harmonics, because a shorted

14

Radio frequency and microwave power amplifiers, volume 2

quarterwave transmission line has an infinite impedance at odd harmonics at its input. Let the transistor operate as an ideal switch when it is turned on during the interval 0 < wt  p where v ¼ 0 and turned off during the interval p < wt  2p where v ¼ 2Vcc according to (1.29). During the interval p < wt  2p when the switch is turned off, the load is directly connected to the transmission line and iT ¼ iR ¼ IR sin wt. Consequently, during the interval 0 < wt  p when the switch is turned on, iT ¼ IR sin wt according to (1.30). Hence, the current flowing into the quarterwave transmission line at any wt can be represented by iT ðwtÞ ¼ IR jsin wtj

(1.31)

where IR is the amplitude of current flowing into the load. Because the collector current is defined as i ¼ iT þ iR, then: iðwtÞ ¼ IR ðsin wt þ jsin wtjÞ

(1.32)

which means that the collector current represents half-sinusoidal pulses with the amplitude equal to double load current amplitude. Consequently, for a purely sinusoidal current flowing into the load due to the infinite loaded quality factor of the series fundamentally tuned L0C0 circuit shown in Figure 1.4(a), the ideal collector voltage and current waveforms can be represented by the corresponding normalized square and half-sinusoidal waveforms shown in Figure 1.4(b) and (c), respectively, where I0 is the dc current. Here, a sum of odd harmonics approximates a square voltage waveform, and a sum of the fundamental and even harmonics approximates a half-sinusoidal collector current waveform. The waveform corresponding to the normalized current flowing into the quarterwave transmission line shown in Figure 1.9 represents a sum of even harmonics. As a result, the shapes of the collector current and voltage waveforms provide a condition where the current and voltage do not overlap simultaneously.

1.1.4

Effect of saturation resistance

It is useful to analytically estimate the effect of a saturation (or on-resistance) rsat that is not equal to zero in a real transistor, and transistor therefore dissipates some amount of power due to the collector current flowing through this resistance when iT/I0

1.5 1.0 0.5 0 0

60

120

180

240

300

wt, °

Figure 1.9 Ideal current waveform in quarterwave transmission line

High-efficiency power amplifier design

15

the transistor is turned on. The simplified equivalent circuit of a Class-F power amplifier with a quarterwave transmission line where the transistor is represented by a nonideal switch with the saturation resistance rsat and parasitic output capacitance Cout is shown in Figure 1.10. During the interval 0 < wt  p when the switch is turned on, the saturation voltage vsat due to the current i(wt) flowing through the switch can be written as vsat ðwtÞ ¼ Vsat sin wt ¼ 2IR rsat sin wt

(1.33)

where, by using (1.10), the saturation voltage amplitude Vsat can be obtained by Vsat ¼ 2VR

rsat 8Vcc rsat ¼ R p R

(1.34)

The corresponding collector current and voltage waveforms are shown in Figure 1.11, where the half-sinusoidal current flowing through the saturation resistance rsat causes the deviation of the voltage waveform from the ideal square waveform. In this case, the bottom part of the voltage waveform becomes sinusoidal with the amplitude Vsat during the interval 0 < wt  p. From (1.29), it follows that the same sinusoidal behavior will correspond to the top part of the voltage waveform during the interval p < wt  2p. The power losses and collector efficiency due to presence of the saturation resistance rsat can be evaluated using (1.6), (1.8), and (1.10) as ð 2p ð Psat 1 2p i2 ðwtÞrsat rsat ¼ dwt ¼ ð2IR Þ2 sin2 wt dwt P0 I0 Vcc 2pI0 Vcc 0 2p 0 (1.35) rsat IR IR rsat IR VR 2rsat ¼ ¼ ¼ Vcc I0 R I0 Vcc R Hence, the collector efficiency can be calculated from: h¼1

Psat 2rsat ¼1 P0 R

(1.36)

In practice, the idealized collector voltage and current waveforms can be realized at low frequencies when effect of the device output capacitance is negligible. λ/4

iR

iT i

Vcc

rsat

L0

C0

iC Cout

vR

Figure 1.10 Effect of parasitic on-resistance and shunt capacitance

R

16

Radio frequency and microwave power amplifiers, volume 2 i/I0 3.0 2.0 1.0 0

(a)

0

60

120

180

240

300

wt,°

300

wt,°

v/Vcc 2.0 1.5 1.0 8 rsat π R

0.5

(b)

0

0

60

120

180

240

Figure 1.11 Idealized (a) collector current and (b) voltage waveforms with nonzero on-resistance At higher frequencies, effect of the output capacitance contributes to a nonzero switching time, resulting in time periods when the collector voltage and collector current exist at the same time when simultaneously v > 0 and i > 0. Consequently, such a load network with shunt capacitance cannot provide the switching-mode operation with an instantaneous transition from the device pinch-off to saturation mode and vice versa. Therefore, during a nonzero time interval, the device operates in the active region as a nonlinear current source.

1.1.5

Load networks with lumped and distributed parameters

Theoretical results show that the proper control of only second and third harmonics can significantly increase the collector efficiency of the power amplifier by flattening the output voltage waveform. Because practical realization of a multielement high-order LC resonant circuit can cause a serious implementation problem, especially at higher frequencies, it is sufficient to be confined to a threeor four-element resonant circuit composing the load network of the power amplifier. In addition, it is necessary to take into account that, in practice, the combined extrinsic and intrinsic transistor output capacitance has a substantial effect on the efficiency. The device output capacitance Cout can represent the collector capacitance Cc in the case of the bipolar transistor or the sum of the drain-source capacitance and gate-drain capacitance, Cds þ Cgd, in the case of the FET device. For a lumped-circuit power amplifier, a special three-element load network can be used to approximate the ideal Class-F mode by providing both high impedance

High-efficiency power amplifier design

17

at the fundamental and third harmonics and zero impedance at the second harmonic at the collector (or drain) by compensating for the influence of Cout. Examples of such load networks with additional parallel and series resonant circuits located between the dc power supply and device output are shown in Figure 1.12 [12,13]. Here, the output circuit of the transistor is represented by a multiharmonic current source, and Rout is the equivalent output resistance at the fundamental frequency defined as a ratio of the fundamental voltage at the device output to the fundamental current flowing into the device. The reactive part of the output admittance (or susceptance) Bnet ¼ Im(Ynet) of the load network with a parallel resonant tank shown in Figure 1.12(b), including the device output capacitance Cout, can be written as Bnet ¼ wCout 

1  w2 L2 C2 wL1 ð1  w2 L2 C2 Þ þ wL2

(1.37)

Ynet

From device output

Impedancepeaking circuit

To output matching circuit and load

(a)

Vcc

Vcc

Cbypass

Cbypass

L2

C2

C2 L1

L2 L1

Cout Rout

(b)

To output matching circuit

Cout

To output matching circuit

(c)

Figure 1.12 Load networks with (a) parallel and (b) series resonant circuits

18

Radio frequency and microwave power amplifiers, volume 2

By applying three-harmonic impedance conditions at the device collector (or drain), open-circuited for the fundamental and third harmonic when Bnet(w0) ¼ Bnet(3w0) ¼ 0 and short-circuited for the second harmonic when Bnet(2w0) ¼ ?, the parameters of this impedance-peaking load network can be derived as L1 ¼

1 6w2o Cout

5 L2 ¼ L1 3

C2 ¼

12 Cout 5

(1.38)

where the sum of the reactance of the parallel resonant tank, consisting of an inductor L2 and a capacitor C2, and an inductor L1 create resonances at the fundamental and third-harmonics, whereas the series capacitive reactance of the tank circuit in series with the inductance L1 creates a short-circuited series resonance condition at the second harmonic [12,13]. Applying the same conditions for the load network with a series resonant circuit L2C2 shown in Figure 1.12(c) results in the ratios between elements given by L1 ¼

4 9w20 Cout

L2 ¼

9 L1 15

C2 ¼

15 Cout 16

(1.39)

where an inductance L2 and a capacitance C2 create a short-circuited condition at the second harmonic, and all elements create the parallel-resonant tanks at the fundamental and third harmonics [14]. As a first approximation for comparison between different operation modes, the output device resistance Rout at the fundamental frequency required to realize a Class-F operation mode with third-harmonic peaking can be estimated as the equivalent resistance determined at the fundamental frequency for an ideal Class-F ðFÞ operation and written as Rout ¼ R1 ¼ V1 =I1 , where V1 and I1 are the fundamentalfrequency voltage and current amplitudes at the device output, respectively. For the same supply voltage Vcc and output power P1 at the fundamental, assuming zero saturation voltage and using (1.14) yield: ðFÞ

R1 ¼ ðBÞ

8 Vcc 8 V2 ¼ 2 cc ¼ 2 p I0 p P1

 2 4 ðBÞ R1 p

(1.40)

2 where R1 ¼ Vcc =2P1 is the output resistance at the fundamental in an ideal Class-B mode. The ideal Class-F power amplifier with all even-harmonic short-circuit termination and third-harmonic peaking achieves a maximum drain efficiency of 88.4% [8]. Such an operation mode can be very conveniently realized by using the transmission lines in the load network. The impedance-peaking load-network topology of such a transmission-line power amplifier is shown in Figure 1.13 [12,13]. In this case, a quarterwave transmission line TL1 located between the dc power supply and the drain terminal provides short-circuit termination for even harmonics. The electrical length q3 of an open-circuit stub TL3 is chosen to have a quarter wavelength at the third-harmonic component to realize a short-circuited condition

High-efficiency power amplifier design

19

Vdd Cbypass

TL1

q1

q3

TL3

Z0,q2 TL2 Cout Rout

To output matching circuit

Figure 1.13 Transmission-line impedance-peaking circuit for Class F at the right end of the series transmission line TL2, whose electrical length q2 should provide an inductive reactance to resonate with the device output capacitance Cout at the third harmonic. As a result, the electrical lengths of the transmission lines at the fundamental frequency can be obtained as   p 1 1 1 p q2 ¼ tan (1.41) q1 ¼ q3 ¼ 2 3 3Z0 w0 Cout 6 where Z0 is the characteristic impedance of the series transmission line TL2 and w0 is the fundamental angular frequency.

1.1.6 Design examples of Class-F power amplifiers The effectiveness of the Class-F load-network design technique is demonstrated based on the example of high-power 1.25-mm LDMOSFET amplifiers. The circuit schematic of the simulated 500-MHz single-stage lumped LDMOSFET power amplifier is shown in Figure 1.14, where its load network corresponds to that shown in Figure 1.12(b) and their parameters are calculated from (1.38). In this case, the total gate width of a high-voltage LDMOSFET device is 7  1.44 mm to achieve 8 W of output power. The drain efficiency and power gain of the power amplifier versus input power Pin for the case of ideal inductors are given in Figure 1.15(a). The drain efficiency over 75% is obtained due to a short-circuited condition at the second-harmonic and open-circuited condition at the third harmonic. Generally, it is important to provide high-impedance conditions at higher-order harmonics that can be readily done by using an output matching circuit with the series inductor as a first element. This shortens the switching time from pinch-off region to voltagesaturation region by better approximating the idealized drain voltage square waveform, as shown in Figure 1.15(c). As follows from (1.17) for a symmetrical voltage waveform, the initial phases for the fundamental-frequency and higher-order harmonics should be equal, which

20

Radio frequency and microwave power amplifiers, volume 2

–

24 V 100 pF 1.5 kΩ

4.5 nH 10 pF

300 Ω

500 Ω 2 pF

25 nH

3.6 nH 15 nH

3.5 pF Pout

Pin

6 pF

1.1 pF

Figure 1.14 Simulated lumped LDMOSFET Class-F power amplifier

is easy to realize by short-circuited and open-circuited conditions. However, according to (1.18) for a half-sinusoidal current waveform, the phases for any higher-order harmonic component should differ from the phase for the fundamental frequency by 90
. This condition is easily realized in a Class-B load network, where the fundamental component of the drain voltage is in phase with the fundamental component of the drain current, but, for all higher-order current harmonics, the impedance of the resonant circuit will be capacitive because the drain current harmonics mostly flow through the shunt capacitor. Therefore, the accurate harmonic phasing is very important to improve effectiveness of a Class-F load network. The amplifier drain efficiency and power gain will be significantly reduced if the values of the quality factor of the load-network inductors are sufficiently small. For example, the maximum value of the drain efficiency can reach only 71% when an inductor quality factor at the fundamental frequency is Qind ¼ 30, as shown in Figure 1.15(b). Therefore, it is preferred at high power level to use the load networks with microstrip lines. Figure 1.16 shows the equivalent circuit of a simulated 500-MHz single-stage microstrip LDMOSFET power amplifier using an active device with the same geometry. The input and output matching circuits represent a T-type matching circuit each, consisting of a series microstrip line, a parallel open-circuit stub, and a series capacitor. To provide even-harmonic short-circuit termination and third-harmonic peaking for a Class-F mode, an RF grounded quarterwave microstrip line and a combination of the series short-length microstrip line and open-circuit stub with electrical length of 30
at the fundamental frequency are used. Such an output circuit configuration approximates the square drain voltage waveform with a good accuracy, as shown in Figure 1.17(a), and provides the drain efficiency over 75% with a maximum output power of 8 W, as shown in

Gain, dB

Efficiency, %

60

18

40

16

20

14

10

12.5

15

17.5

20

22.5

Pin, dBm

(a) Efficiency, %

Gain, dB

60

18

40

16

20

14

10

12.5

15

17.5

20

22.5

(b)

Pin, dBm

vd, V

40

20

0

1.0

2.0

3.0

(c)

t, nsec

Figure 1.15 Drain efficiency, power gain, and voltage waveform 24 V

1.5 kΩ

100 pF

300 Ω

2.5 pF

Pin

50 Ω 75° 50 Ω 45°

500 Ω

30 Ω 90° 30 Ω 12° 30 Ω 30°

50 Ω 73°

4.5 pF Pout

50 Ω 13°

Figure 1.16 Simulated microstrip LDMOSFET Class-F power amplifier

22

Radio frequency and microwave power amplifiers, volume 2 vd, V

40

20

1.0

0 (a)

3.0

2.0

Efficiency, %

t, nsec Gain, dB

60

18

40

16

20

14

10

12.5

15

17.5

20

22.5

Pin, dBm

(b)

Figure 1.17 Drain voltage waveform, efficiency, and power gain Figure 1.17(b). The resulting smaller value of the drain efficiency compared to the theoretically achievable one can be explained by the nonoptimized impedances at higher-order harmonics since, unlike a lumped inductor, the transmission line exhibits an equidistant impedance performance in the frequency domain with consecutive poles and zeros at the characteristic frequencies. This means that using a simple T-type transmission-line transformer does not provide high impedance conditions at all higher-order harmonics simultaneously. Figure 1.18 shows the circuit schematic of a 2-GHz microstrip GaN HEMT power amplifier operating in a Class-F mode [15]. The GaN HEMT device on a SiC substrate used in this power amplifier was provided by Cree having a 3.6-mm gate periphery and maximum operating frequency of about 40 GHz. Both input and output matching networks terminate the second, third, and fourth harmonics and some of the higher-order even harmonics using the quarterwave transmission lines. The device output impedance at the fundamental of 70 W was chosen for the design as it was a good tradeoff of efficiency and output power. In this case, the load network provides the impedance matching at the fundamental and the corresponding Class-F harmonic control at the second, third, and fourth harmonics simultaneously. The fundamental matching was provided by choosing the optimum value of the transmission-line characteristic impedances Z2 and Z3. Tuning the output matching network which includes the device output capacitance resulted in a very high third-harmonic impedance of about 400 W, whereas the impedances at

High-efficiency power amplifier design Vdd

Vg

TL1 TL6

TL4

θ6

23

90°

90° TL2, θ2 Z2

Pin

R1

TL5, θ5

C1

R2

TL3, 30°

Z3

RL

C2

Figure 1.18 Circuit schematic of transmission-line Class-F GaN HEMT power amplifier the second and fourth harmonics were of about 0.5 W and 0.7 W, respectively. Note that high impedance at the fundamental with corresponding high supply voltage was chosen to minimize the effect of the parasitic bondwire and package inductors to provide the near short-circuited Class-F conditions at the second and higherorder even harmonics, whose effect becomes significant at higher operating frequencies. An input matching network was designed to provide a second-harmonic short by using a quarterwave transmission line close to the gate and conjugate matching at the fundamental. Two shunt RC networks at the input were added to provide the stability of operation. As a result, the power amplifier achieved the maximum drain efficiency of 87% and power-added efficiency (PAE) of 83% at an output power of 11.8 W and at a drain supply voltage of 42.5 V, with a maximum power gain of 15.8 dB and its compressed value of 13.4 dB at peak PAE.

1.2 Inverse Class F Effect of the inclusion of the parallel resonant circuit tuned to the second harmonic and located in series at the anode, as shown in Figure 1.19(a), was first described and analyzed in the early 1940s [5,16]. It was shown that the symmetrical anode current waveform and level of its depression can be provided with the opposite phase conditions between the fundamental-frequency and second-harmonic components and an optimum value of the ratio between their voltage amplitudes. It was noted that high operation efficiency can be achieved even when impedance of the tank circuit to second harmonic is equal or slightly greater than that of the tank circuit to fundamental frequency. In practical vacuum-tube amplifiers intended for operation at very high frequencies, the peak output power and anode efficiency can therefore be increased by 1.15 to 1.2 times [17]. In addition, it was suggested to use an additional resonator, tuned to the fourth harmonic and connected in series with the secondharmonic resonator, as shown in Figure 1.19(b), to maximize the anode efficiency of the vacuum-tube amplifier with approximate square voltage-driving waveform [18].

24

Radio frequency and microwave power amplifiers, volume 2 2f0 RL

f0

(a) 2f0

4f0 f0

RL

(b)

Figure 1.19 (a) Biharmonic and (b) polyharmonic inverse Class-F power amplifiers As a simple solution to realize 180
out-of-phase conditions between the voltage fundamental-frequency and second-harmonic components at the device output in vacuum-tube amplifiers, it was proposed to use a second-harmonic tank resonator connected in series to the device input [16]. Such an approach makes it possible to flatten the anode voltage waveform in active region avoiding the device saturation mode. In this case, the driver stage is loaded by the nonlinear diode-type input grid impedance of the final-stage tube providing a flattened grid voltage waveform, which includes the fundamental-frequency and second-harmonic components. The presence of the strong second-harmonic component results in a second-harmonic voltage drop across the resonator. The loaded quality factor of the second-harmonic resonator must be high enough to neglect the voltage drop at the fundamental frequency. As a result, the second-harmonic resonator has no effect on the voltage fundamental-frequency component. However, it provides a phase shift of 180
for the second-harmonic component, as increasing in a voltage drop across the resonator results in decreasing in the voltage drop across the grid-cathode terminals. Figure 1.20 shows that the shapes of the voltage and current waveforms can be significantly transformed with increased voltage peak factor and current flattening by adding one additional harmonic component with a proper phase. For example, the combination of the fundamental-frequency and third harmonic components with 180
out-of-phase shift at the center of symmetry results in a flattened current waveform with depression in its center, as shown in Figure 1.20(a), which can be minimized by using the proper ratio between the amplitudes of the fundamental and third harmonics. Similarly, the combination of the fundamental and second harmonics, which are in phase at the center of symmetry, sharpens the voltage waveform corresponding to minimum values of the voltage waveform, as shown in Figure 1.20(b).

High-efficiency power amplifier design i

25

n = 1, 3

I0

0



2

ωt



2

ωt

(a)

v

n = 1, 2

Vcc

0 (b)

Figure 1.20 Fourier (a) current and (b) voltage waveforms with third and second harmonics

1.2.1 Idealized inverse Class-F mode Generally, an infinite number of even-harmonic tank resonators can maintain a square current waveform with a half-sinusoidal voltage waveform at the collector. Figure 1.21(a) shows the basic schematic of an inverse Class-F power amplifier with a multiple-resonator output filter to control the harmonic content of its collector (anode or drain) voltage and current waveforms, thereby shaping them to reduce dissipation and to increase efficiency. The term “inverse” means that collector voltage and current waveforms are interchanged compared to a conventional case under the same idealized assumptions. Consequently, for a purely sinusoidal current flowing into the load, the ideal collector current waveform is composed by the fundamental component and odd harmonics approximating a square waveform. At the same time, the collector voltage waveform is composed by the fundamental component and even harmonics approximating a half-sinusoidal waveform. As a result, the shapes of the collector current and voltage waveforms provide a condition when the current and voltage do not overlap simultaneously, similarly to a conventional Class-F mode. Such a condition, with symmetrical collector voltage and current waveforms, corresponds to an idealized inverse Class-F operation mode with 100% collector efficiency.

26

Radio frequency and microwave power amplifiers, volume 2 2f0

2nf0

4f0

RL

f0

(a) Vcc 2f0 I0 Vcc

4f0

2nf0

i v

veven

iodd

f0

RL

iR

(b)

Figure 1.21 Basic circuits of inverse Class-F power amplifier with parallel resonant circuits

Similar analysis of the distribution of voltages and currents in the inverse Class-F load network as for a conventional Class-F mode results in equations for the collector current and voltage waveforms as iðwtÞ ¼ 2I0  iðwt þ pÞ

(1.42)

where I0 is the dc current, and vðwtÞ ¼ VR ðsin wt þ jsin wtjÞ

(1.43)

where VR is fundamental-frequency amplitude at the load. From (1.42), it follows that maximum value of the collector current cannot exceed that of 2I0, and the time duration with maximum amplitude defined as i ¼ 2I0 coincides with that with minimum amplitude defined as i ¼ 0. Because the collector current is zero when the switch is turned off, the only possible waveform for the collector current is a square wave composing of only dc, fundamental-frequency, and odd-harmonic components. By using a Fourier analysis of the current and voltage waveforms, the following equations for the dc voltage, fundamental voltage and current components in the collector voltage and current waveforms can be obtained: The fundamental current component can be calculated using (1.42) as ð 1 2p 4I0 (1.44) 2I0 sinðwt þ pÞdwt ¼ I1 ¼ IR ¼ p p p The dc voltage Vcc can be calculated from (1.43) as ð 1 p 2VR 2VR sin wt dwt ¼ Vcc ¼ p 2p 0

(1.45)

High-efficiency power amplifier design

27

The fundamental voltage component can be calculated from (1.43) as ð 1 p 2VR sin2 wt dwt ¼ VR : (1.46) V1 ¼ p 0 Then, the relationship between the dc power P0 and the output power at the fundamental frequency P1 can be given as P1 ¼

V1 I1 1 pVcc 4I0 ¼ ¼ P0 2 2 2 p

(1.47)

resulting in a theoretical collector efficiency of 100%. The impedance conditions seen by the device collector for an idealized inverse Class-F mode must be equal to p2 Vcc 8 I0

(1.48)

Z2nþ1 ¼ 0 for odd harmonics

(1.49)

Z2n ¼ 1 for even harmonics

(1.50)

Z1 ¼ R1 ¼

1.2.2 Inverse Class F with quarterwave transmission line An idealized inverse Class-F operation mode can be represented by using a sequence of the series resonant circuits tuned to the fundamental and odd harmonics, as shown in Figure 1.22(a). In this case, it is assumed that each resonant circuit has zero impedance at the corresponding fundamental frequency f0 and oddharmonic components (2n þ 1)f0 and infinite impedance at even harmonics 2nf0 realizing the idealized inverse Class-F square current and half-sinusoidal voltage waveforms at the device output terminal. As a result, the transistor which is driven to operate as a switch sees the load resistance RL at the fundamental frequency, whereas the odd harmonics are shorted by the series resonant circuits. An infinite set of the series resonant circuits tuned to the odd harmonics can be effectively replaced by a quarterwave transmission line with the same operating capability. Such a circuit representation of an inverse Class-F power amplifier with a series quarterwave transmission line loaded by the series resonant circuit tuned to the fundamental frequency is shown in Figure 1.22(b) [7,19]. The series-tuned output circuit presents a load resistance at the frequency of operation to the transmission line. At the same time, the quarterwave transmission line transforms the load impedance according to R¼

Z02 RL

(1.51)

where Z0 is the characteristic impedance of a transmission line. For even harmonics, the open circuit on the load side of the transmission line is repeated, thus producing an open circuit at the drain. However, the quarterwave transmission line

28

Radio frequency and microwave power amplifiers, volume 2 f0 I0

Vdd

i v

3f0

5f0

iR

(2n + 1)f0

RL

(a) Vdd

Cb

vin

Z0, λ/4

L0

C0

R

RL

(b)

Figure 1.22 Inverse Class-F power amplifier with (a) series resonant circuits and (b) transmission line converts the open circuit at the load to a short circuit at the drain for odd harmonics with resistive load at the fundamental frequency. Consequently, for a purely sinusoidal current flowing into the load due to infinite loaded quality factor of the series fundamentally tuned circuit, the ideal drain current and voltage waveforms can be represented by the corresponding normalized square and half-sinusoidal waveforms, respectively. Here, a sum of odd harmonics approximates a square current waveform, and a sum of the fundamental and even harmonics approximates a half-sinusoidal drain voltage waveform. As a result, the shapes of the drain current and voltage waveforms provide a condition when the current and voltage do not overlap simultaneously. The quarterwave transmission line causes the output voltage across the load resistor RL to be phaseshifted by 90
relative to the fundamental-frequency components of the drain voltage and current.

1.2.3

Load networks with lumped and distributed parameters

Theoretical results show that the proper control of the second harmonic can significantly increase the collector efficiency of the power amplifier by flattening of the output current waveform and minimizing the product of integration of the voltage and current waveforms. Practical realization of a multielement high-order LC resonant circuit can cause a serious implementation problem, especially at higher frequencies and in monolithic integrated circuits, when only three harmonic components can be effectively controlled. Therefore, it is sufficient to be confined to the three- or four-element resonant circuit composing the load network of the

High-efficiency power amplifier design

29

power amplifier. In this case, the operation with the second-harmonic open circuit and third-harmonic short circuit is a promising concept for low-voltage power amplifiers [20]. In addition, it is necessary to take into account that, in practice, both extrinsic and intrinsic transistor parasitic elements such as the output shunt capacitance or serious inductance have a substantial effect on the efficiency. The output capacitance Cout can represent the collector capacitance Cc in the case of the bipolar transistor or the sum of drain-source capacitance and gate-drain capacitance, Cds þ Cgd, in the case of the FET device. The output inductance Lout is generally composed of the bondwire and lead inductances for a packaged transistor, whose effect becomes significant at higher frequencies. Figure 1.23 shows the equivalent circuit of the second-harmonic impedancepeaking load network, where the series circuit consisting of an inductor L1 and a capacitor C1 creates a resonance at the second harmonic. Because the device output inductance Lout and capacitance Cout are tuned to create an open-circuited condition at the second harmonic, the device collector sees resultant high impedance at the second harmonic. To achieve the second-harmonic high impedance, an external inductance may be added to interconnect the device output inductance Lout directly at the output terminal (collector or drain) if its value is not sufficient. As a result, the values of the load-network parameters are defined as Lout ¼

1 4w20 Cout

L1 ¼

1 4w20 C1

(1.52)

As a first approximation for comparison between different operation classes, the output device resistance Rout at the fundamental frequency required to realize an inverse Class-F operation mode with second-harmonic peaking can be estimated as ðinvFÞ determined at the fundamental frequency for an equivalent resistance Rout ¼ R1 an ideal inverse Class-F mode. For the same supply voltage Vcc and output power P1 at the fundamental, assuming zero saturation voltage and using (1.14) and (1.48) yield:  2 2 p2 p2 Vcc p ðinvFÞ ðFÞ ðBÞ ¼ ¼ R1 ¼ R1 (1.53) R1 8 I0 8 2

Lout

Cout Rout

L1

To output matching circuit

C1

Figure 1.23 Second-harmonic impedance-peaking circuit

30

Radio frequency and microwave power amplifiers, volume 2 ðFÞ

where R1 is the output resistance at the fundamental frequency in a conventional ðBÞ Class-F mode and R1 is the output resistance at the fundamental frequency in an ideal Class-B mode. The ideal inverse Class-F power amplifier cannot provide all the voltage required by the third- and higher-order odd harmonic short-circuit termination using a single parallel transmission line, as can be easily realized by a quarterwave transmission line for even harmonics in the conventional Class-F power amplifier. In this case, with a sufficiently simple circuit schematic convenient for practical realization, applying the current second-harmonic peaking and voltage thirdharmonic shorting can result in a maximum drain efficiency of more than 80% [21]. The output impedance-peaking load network of such a microstrip power amplifier is shown in Figure 1.24, and its circuit structure is similar to that used to provide a conventional Class-F operation mode. As it follows from (1.53), the equivalent output resistance for an ideal inverse Class-F mode is higher by more than 2.4 times compared to a conventional Class-B mode. Therefore, using an inverse Class-F mode simplifies the corresponding loadnetwork design by minimizing the impedance transformation ratio. This is very important for high output power level with a sufficiently small load impedance. However, maximum amplitude of the output voltage waveform can exceed the supply voltage by about three times. In this case, it is required to use the device with high breakdown voltage or to reduce the supply voltage. The latter, however, is not desirable because it may result in lower power gain and efficiency. For such an inverse Class-F microstrip power amplifier, it is necessary to provide the following electrical lengths for the transmission lines at the fundamental frequency: "  # p 1 1 1 1 p q3 ¼ q2 ¼ tan (1.54) 2Z0 w0 Cout þ pffiffiffi q1 ¼ 3 2 4 3

Vdd Cbypass

TL1

θ3

θ1

TL3

Z 0, θ 2 TL2 Cout Rout

To output matching circuit

Figure 1.24 Transmission-line impedance-peaking circuit for inverse Class F

High-efficiency power amplifier design

31

where Z0 is the characteristic impedance of the microstrip lines. The transmission line TL1 with electrical length q1 ¼ 60
at the fundamental frequency provides a short-circuited condition for the third harmonic and introduces a capacitive reactance at the second harmonic. The open-circuit stub TL3 with electrical length q3 ¼ 45
creates a short-circuited condition at the right end of the transmission line TL2 at the second harmonic. Thus, the transmission line TL2 having an inductive reactance is tuned to the parallel resonance condition at the second harmonic with the device output capacitance Cout and short-circuited transmission line TL1.

1.2.4 Design example of inverse Class-F power amplifier In a hybrid power amplifier where the packaged device is used, the presence of a transistor output series bondwire and lead inductance Lout creates some problems in providing an acceptable second- or third-harmonic open- or short-circuit termination. In this case, it is convenient to use a series transmission line as a first element of the load network connected to the device output, as shown in Figure 1.25(a), where the transmission line TL1 is placed between the device drain and shunt shortcircuited quarterwave transmission line TL3. However, if the length of a combined series transmission line TL1 þ TL2 becomes very long in a Class-F mode with a short circuit at the second harmonic and an open circuit at the third harmonic and Vdd

TL3

90°

TL1, θ1

TL2, θ2

Z1

Z1 TL4

Z2

RL

30°

(a) Device output

Cout R

Lout

θ1

θ2

90°

30°

RL

(b)

Figure 1.25 Transmission-line (a) inverse Class-F power amplifier and (b) its equivalent circuit

32

Radio frequency and microwave power amplifiers, volume 2

additional fundamental-frequency matching circuit is required, then such a load network in an inverse Class-F mode is compact, convenient for harmonic tuning, and very practical. Figure 1.25(b) shows the equivalent circuit of a transmission-line inverse Class-F load network, where the complex-conjugate load matching is provided at the fundamental frequency. Both high reactance at the second harmonic and low reactance at the third harmonic are created at the device output by using two series transmission lines TL1 and TL2, whose electrical lengths depend on the values of the device output shunt capacitance Cout and series inductance Lout, quarterwave short-circuit stub TL3, and open-circuit stub TL4 with electrical length of 30
[10,22]. The output shunt capacitance Cout can represent both intrinsic biasdependent drain-source capacitance Cds and extrinsic bias-independent drain padcontact capacitance Cdp of the nonlinear large-signal equivalent circuit for GaN HEMT device, whereas the series output inductance Lout is modeled by a combined effect of the metallization, bond wire, and package inductances [23]. The harmonic conditions for an inverse Class-F load network seen by the device multiharmonic current source derived from (1.48) through (1.50) for the first three harmonic components including fundamental are Re Znet ðw0 Þ ¼ R

(1.55)

Im Znet ð2w0 Þ ¼ 1

(1.56)

Im Znet ðw0 Þ ¼ Im Znet ð3w0 Þ ¼ 0

(1.57)

where the load resistance (or equivalent output resistance) R seen by the device output at the fundamental frequency is defined in an ideal inverse Class-F mode by (1.53). Figure 1.26(a) shows the transmission-line load network seen by the device multiharmonic current source at the fundamental frequency, where the combined series transmission line TL1 þ TL2 (together with an open-circuit capacitive stub TL4 with electrical length of 30
) provides an impedance matching between the optimum equivalent output device resistance R and the standard load resistance RL by proper choice of the transmission-line characteristic impedances Z1 and Z2, where Cout and Lout are the elements of the matching circuit. For simplicity of calculation, the characteristic impedances of the transmission lines TL1 and TL2 are set to be equal to Z1. The load network seen by the device current source at the second harmonic (considering the short-circuit effect of the grounded quarterwave transmission line TL3) is shown in Figure 1.26(b), where the transmission line TL1 provides an opencircuited condition for the second harmonic at the device output by forming a second-harmonic tank together with the shunt capacitor Cout and series inductance Lout. Similar load network at the third harmonic is shown in Figure 1.26(c), where the open-circuit effect of the grounded quarterwave transmission line TL3 and short-circuit effect of the open-circuit stub TL4 at the third harmonic are used. In this case, the combined transmission line TL1 þ TL2, which is short-circuited at

High-efficiency power amplifier design R at fundamental

Lout

33

TL1 + TL2 Z1, θ1 + θ2

Cout

TL4

Z2 30°

RL

(a) Infinite reactance at second harmonic

Lout

Z1, 2θ1 TL1

Cout

(b) Zero reactance at third harmonic

Lout

Z1, 3(θ1 + θ2) TL1 + TL2

Cout

(c)

Figure 1.26 Load networks seen by the device output at (a) fundamental, (b) second, and (c) third harmonics

its right-hand side and connected in series with an inductance Lout provides a shortcircuited condition for the third harmonic at the device output. Depending on the actual physical length of the device package lead, the on-board adjustment of the transmission lines TL1 and TL2 can easily provide the required open-circuited and short-circuited conditions (as well as an impedance matching at the fundamental frequency) because of their series connection to the device output. By using (1.56) and (1.57), the electrical lengths of the transmission lines TL1 and TL2, assuming the same characteristic impedance Z1 for both series transmission-line sections, can be defined from: 2w0 Cout 

1 ¼0 2w0 Lout þ Z1 tan 2q1

3w0 Lout þ Z1 tan 3ðq1 þ q2 Þ ¼ 0

(1.58) (1.59)

34

Radio frequency and microwave power amplifiers, volume 2

with the maximum total electrical length q1 þ q2 ¼ p/3 or 60
at the fundamental frequency or 180
at the third harmonic when Lout ¼ 0. As a result, the electrical lengths of the transmission lines TL1 and TL2 as analytical functions of the device output series inductance Lout and shunt capacitance Cout are obtained as 1 1  ð2w0 Þ2 Lout Cout q1 ¼ tan1 2Z1 w0 Cout 2 q2 ¼

(1.60)

p 1 1 3w0 Lout  tan  q1 Z1 3 3

(1.61)

where the transmission-line characteristic impedance Z1 can be set in advance. In order to omit an additional matching section at the fundamental frequency, the inverse Class-F load network can also be used to match the equivalent device fundamental-frequency impedance R with the standard load impedance RL (usually equal to 50 W). In this case, it is necessary to properly optimize both characteristic impedances Z1 and Z2. Figure 1.27(a) shows the test board of a transmission-line inverse Class-F power amplifier based on a 28-V 10-W Cree GaN HEMT power transistor

(a) Drain efficiency 100

16

80 60

14

40 12

20

10

Efficiency (%)

Gain (dB)

Power gain 18

0 0 (b)

5

10

20 15 Pin (dBm)

25

30

Figure 1.27 Transmission-line 10-W inverse Class-F GaN HEMT power amplifier: (a) test board and (b) simulated performance

High-efficiency power amplifier design

35

CGH40010P and transmission-line load network with the second- and thirdharmonic control, as shown in Figure 1.25(a). The input matching circuit provides the fundamental-frequency complex-conjugate matching with the standard 50-W source. The parameters of the series transmission line in the load network were optimized for implementation convenience. In this case, the device input and output package leads as external elements were properly modeled to take into account effect of their inductances, and their models were then added to the simulation setup. The simulation results of a transmission-line inverse Class-F GaN HEMT power amplifier shown in Figure 1.27(b) are based on a nonlinear device model supplied by Cree and technical parameters for a 30-mil RO4350 substrate. The maximum output power of 41.3 dBm, power gain of 13.3 dB (linear gain of about 18 dB), drain efficiency of 80.3%, and PAE of 76.5% are achieved at an operating frequency of 2.14 GHz with a supply voltage of 28 V and a quiescent current of 40 mA. The experimental results of the test board shown in Figure 1.27(a) were very close to the simulated results obtaining a maximum output power of 41.0 dBm, a drain efficiency of 76.0%, a PAE of 72.2%, and a power gain of 13.0 dB at an operating frequency of 2.14 GHz (gate bias voltage Vg ¼ 2.8 V and drain supply voltage Vdd ¼ 28 V), achieved without any tuning of the input matching circuit and load network [10].

1.3 Class E with shunt capacitance and series filter In late 1940s and early 1950s, during experimental tuning of the vacuum-tube amplifiers operating in a saturation mode, it was noticed and then concluded that, when the second- and higher-order harmonics are properly phased, efficiency significantly increases when the load contains reactive components for harmonics, which form the proper shapes of anode voltage and current [24]. In this case, detuning of the resonant circuit is provided in the direction of higher frequencies when the operating frequency is lower than the resonance frequency of the resonant circuit. As a result, anode efficiencies of about 92% to 93% were achieved for the phase angles of the output load network within 30
to 40
, resulting in the proper inductive impedance at the fundamental frequency and capacitive reactances at the harmonic components seen by the anode of the active device [25]. A few years later, it was discovered that very high efficiencies could be obtained with a series resonant LC circuit connected to a transistor [26]. The exact theoretical analysis of the single-ended switching-mode power amplifier with a shunt capacitance and a series LC circuit was then given by Kozyrev [27].

1.3.1 Optimum load-network parameters The single-ended switching-mode power amplifier with a shunt capacitance was introduced as a Class-E power amplifier by Sokals in 1975, and it has found widespread application because of its design simplicity and high operation efficiency [28,29]. This type of high-efficiency power amplifiers was then widely used in different frequency ranges and with different output power levels ranging from

36

Radio frequency and microwave power amplifiers, volume 2

several kilowatts at low RF frequencies up to about 1 W at microwaves [30]. The characteristics of a Class-E power amplifier can be determined by defining its steady-state collector voltage and current waveforms. The basic circuit of a Class-E power amplifier with shunt capacitance is shown in Figure 1.28(a), where the load network consists of a capacitor C shunting the transistor, a series inductor L, a series fundamentally tuned L0C0 circuit, and a load resistor R. In a common case, a shunt capacitance C can represent the intrinsic device output capacitance and external circuit capacitance added by the load network. The collector of the transistor is connected to the supply voltage by an RF choke with high reactance at the fundamental frequency. The transistor is considered an ideal switch that is driven in such a way as to provide the instant device switching between its on-state and offstate operation conditions. As a result, the collector current and voltage waveforms are determined by the switch when it is turned on and by the transient response of the load network when the switch is turned off. To simplify the analysis of a Class-E power amplifier, whose simplified equivalent circuit is shown in Figure 1.28(b), the following assumptions are introduced: ●

●

● ●

● ●

the transistor has zero saturation voltage, zero saturation resistance, infinite off-resistance, and its switching action is instantaneous and lossless; the total shunt capacitance is independent of the collector and is assumed linear; the RF choke allows only a constant dc current and has no resistance; the loaded quality factor QL ¼ wL0/R ¼ 1/wC0R of the series resonant L0C0 circuit tuned to the fundamental frequency is high enough for the output current to be sinusoidal at the switching frequency; there are no losses in the circuit except only in the load R; and for simplicity, a 50% duty ratio is used. L

L0

C0

R

C vb

Vbe

Vcc

(a) L0

L I0 Vcc

iC

i v

C0

iR C

R

(b)

Figure 1.28 Basic circuits of Class-E power amplifier with shunt capacitance

High-efficiency power amplifier design

37

For a lossless operation mode, it is necessary to provide the following optimum conditions for voltage across the switch (just prior to the start of switch on) at wt ¼ 2p, when transistor is saturated: vðwtÞjwt¼2p ¼ 0  dvðwtÞ  ¼0 dwt wt¼2p

(1.62) (1.63)

where v(wt) is the voltage across the switch. The detailed theoretical analysis of a Class E power amplifier with shunt capacitance for any duty ratio is given in [31], where the load current is assumed to be sinusoidal: iR ðwtÞ ¼ IR sinðwt þ jÞ

(1.64)

where j is the initial phase shift. When the switch is turned on for 0  wt < p, the current through the capacitance: iC ðwtÞ ¼ wC

dvðwtÞ ¼0 dwt

(1.65)

and, consequently: iðwtÞ ¼ I0 þ IR sinðwt þ jÞ

(1.66)

under the initial on-state condition i(0) ¼ 0. Hence, the dc current can be defined as I0 ¼ IR sin j

(1.67)

and the current through the switch can be rewritten by iðwtÞ ¼ IR ½sinðwt þ jÞ  sin j

(1.68)

When the switch is turned off for p  wt < 2p, the current through the switch i(wt) ¼ 0, and the current flowing through the capacitor C can be written as iС ðwtÞ ¼ I0 þ IR sinðwt þ jÞ

(1.69)

producing the voltage across the switch by the charging of this capacitor according to ð 1 wt iС ðwtÞdwt vðwtÞ ¼ wC p : (1.70) IR ½cosðwt þ jÞ þ cos j þ ðwt  pÞsin j ¼ wC Applying the first optimum condition given by (1.62) enables the phase angle j to be determined as   2 ¼ 32:482
(1.71) j ¼ tan1  p

38

Radio frequency and microwave power amplifiers, volume 2

As a result, the normalized steady-state collector voltage waveform for p  wt < 2p and current waveform for 0  wt < p are   vðwtÞ 3p p  cos wt  sin wt (1.72) ¼ p wt  Vcc 2 2 iðwtÞ p ¼ sin wt  cos wt þ 1 I0 2

(1.73)

Figure 1.29 shows the normalized (a) load current, (b) collector voltage waveform, and (c) collector current waveforms for an idealized optimum (or nominal) Class-E mode with shunt capacitance. From collector voltage and current waveforms, it follows that, when the transistor is turned on, there is no voltage across the switch, and the current i(wt), consisting of the load sinusoidal current and dc current, flows through the device. However, when the transistor is turned off, this current is flowing through the shunt capacitor C. The jump in the collector current waveform at the instant of switching off is necessary to obtain nonzero output power at the fundamental frequency delivered to the load, which can be defined as an integration of the product of the collector voltage and current derivatives over the entire period [32]. The peak collector voltage Vmax and current Imax can be determined by differentiating the appropriate waveforms given by (1.72) and (1.73), respectively, and setting the results equal to zero, which gives: Vmax ¼ 2pjVcc ¼ 3:562 Vcc ! pffiffiffiffiffiffiffiffiffiffiffiffiffiffi p2 þ 4 þ 1 I0 ¼ 2:8621 I0 Imax ¼ 2

(1.74) (1.75)

The fundamental-frequency voltage across the switch consists of two quadrature components, whose amplitudes can be found using Fourier formulas and (1.72) as ð  1 2p IR  p VR ¼  sin 2j þ 2 cos 2j (1.76) vðwtÞsinðwt þ jÞdwt ¼ pwC 2 p 0 ð  1 2p IR  p VL ¼  þ p sin2 j þ 2 sin 2j vðwtÞcosðwt þ jÞdwt ¼  (1.77) pwC 2 p 0 As a result, the optimum series inductance L, shunt capacitance C, and load resistance R for the supply voltage Vcc and fundamental-frequency output power Pout can be obtained by wL VL ¼ ¼ 1:1525 VR R wCR ¼ R¼

wC VR ¼ 0:1836 IR

2 2 8 Vcc Vcc ¼ 0:5768 p2 þ 4 Pout Pout

(1.78) (1.79) (1.80)

High-efficiency power amplifier design

39

iR/I0 1.5 1 0.5 0 60

120

180

240

300

ωt,°

60

120

180

240

300

ωt,°

60

120

180

240

300

ωt,°

–0.5 –1 –1.5 (a) v/Vcc 3.5 3 2.5 2 1.5 1 0.5 0 0 (b) i/I0 2.5 2 1.5 1 0.5 0 0 (c)

Figure 1.29 Normalized (a) load current, (b) collector voltage, and (c) current waveforms for idealized optimum Class E with shunt capacitance

40

Radio frequency and microwave power amplifiers, volume 2

Finally, the phase angle of the load network seen by the switch at the fundamental frequency required for an idealized optimum (or nominal) Class-E mode with shunt capacitance can be obtained through the load-network parameters using (1.78) and (1.79) as 0 1   wL wCR B C  tan1 @ (1.81) f ¼ tan1 A ¼ 35:945
wL R wCR 1 R When realizing a Class-E operation mode, it is very important to know up to which maximum frequency such an idealized efficient operation mode can be extended. In this case, it is important to establish a relationship between the maximum operation frequency fmax, shunt capacitance C, output power Pout, and supply voltage Vcc by using (1.79) and (1.80) when:  2 fmax ¼ 0:0507 Pout =CVcc (1.82) where C ¼ Cout is the device output capacitance limiting the maximum operation frequency of an idealized optimum Class-E power amplifier with shunt capacitance. The high-QL assumption for the series resonant L0C0 circuit can lead to considerable errors if its value is substantially small in real circuits [33]. For example, for a 50% duty ratio, the values of the load-network parameters for the loaded quality factor QL less than unity can differ by several tens of percentages. At the same time, for QL  7, the errors are found to be less than 10% and they become less than 5% for QL  10. To match the required optimum Class-E load-network resistance R with a standard load impedance RL, usually equal to 50 W, the series resonant L0C0 circuit should be followed (or fully replaced) by the matching circuit, in which the first element represents a series inductor to provide high impedance at the second- and higher-order harmonics [27].

1.3.2

Effect of saturation resistance, finite switching time, and nonlinear shunt capacitance

In practical power amplifier design, especially when a value of the supply voltage is sufficiently small, it is very important to predict the overall degradation of power amplifier efficiency due to finite value of the transistor saturation resistance. Figure 1.30(a) shows the simplified equivalent circuit of a Class-E power amplifier with shunt capacitance, including the saturation resistance (on-resistance) rsat connected in series to the ideal switch. To obtain a quantitative estimate of the power losses due to the contribution of rsat, the saturated output power Psat can be obtained with a simple approximation when the current i(wt) flowing through the saturation resistance rsat is determined in an ideal case by (1.73). An analytical expression to calculate the power losses due to the saturation resistance rsat, whose value is assumed constant, can be represented in the normalized form as ðp Psat rsat ¼ i2 ðwtÞdwt (1.83) P0 2pI0 Vcc 0

High-efficiency power amplifier design C0

L0

L

41

rsat C

Vcc

R

(a) i

τs τ1 (b)

i(θs) τ

θs τ2

2 + τ1 L

Vcc

L0

C

C0

R

(c)

Figure 1.30 Equivalent Class-E load networks (a) with saturation resistance, (b) current waveform with finite time delay, and (c) nonlinear capacitance where P0 ¼ I0Vcc is the dc power. As a result, (1.83) can be rewritten as rsat p2 þ 28 Psat rsat I0 p  2 rsat ¼ 1:365 p þ 28 ¼ ¼ P0 2p Vcc 8 2R p2 þ 4 R

(1.84)

The collector efficiency h can be calculated from: h¼

Pout P0  Psat Psat ¼ ¼1 P0 P0 P0

(1.85)

Consequently, the presence of the saturation resistance results in finite value of the saturation voltage Vsat, which can be defined from: Vsat 1 ¼1 Vcc 1 þ 1:365 rRsat

(1.86)

where Vsat is normalized to the dc supply voltage Vcc [34]. More detailed theoretical analysis of the time-dependent behavior of the collector voltage and current waveforms shows that, for finite value of the saturation resistance rsat, the optimum conditions for idealized operation mode given by (1.62)

42

Radio frequency and microwave power amplifiers, volume 2

and (1.63) do not correspond anymore to minimum dissipated power losses, and there are optimum nonzero values of the collector voltage and its derivative at switching time instant corresponding to minimum overall power losses [24,35]. For example, even for small losses with the normalized loss parameter wCrsat ¼ 0.1 for a duty ratio of 50%, the optimum series inductance L is almost two times greater, whereas the optimum shunt capacitance C is of about 20% greater than those obtained under nominal conditions. Thus, generally the nominal switching conditions given by (1.62) and (1.63) can be considered optimum only for idealized case of a Class-E load network with zero saturation resistance providing the switchingmode transistor operation when it operates in pinch-off and saturation regions only. However, they can be considered as a sufficiently accurate initial guess for further design and optimization in a real Class-E power amplifier design. For an ideal transistor without any memory effects due to intrinsic phase delays, the switching time is equal to zero when the rectangular input drive results in a rectangular output response. Such an ideal case assumes zero device feedback capacitance and zero device input resistance. However, at higher frequencies, it is very difficult to realize the driving signal close to the rectangular form, as it leads to the significant circuit complexity. Fortunately, to realize high-efficiency operation conditions, it is sufficient to drive the power amplifier simply with a sinusoidal signal. The finite-time transition from the saturation mode to the pinch-off mode through the device active mode takes place due to the device inertia when the base (or channel) charge changes to zero with some finite delay time ts, as shown in Figure 1.30(b). To minimize the switching time interval, it is sufficient to slightly overdrive the transistor with a signal amplitude by 20% to 30% higher than is required for a conventional Class-B power amplifier. The power dissipated during this on-to-off transition can be calculated assuming zero on-resistance as 1 Ps ¼ 2p

ðp qs

iðwtÞvðwtÞdwt

(1.87)

where the collector voltage during the transition time ts ¼ p  qs is defined as v ðq s Þ ¼

1 wC

ðp qs

iC ðwtÞdwt:

(1.88)

The short duration of the switching time and the proper behavior of the resulting collector (or drain) waveform allows us to make an additional assumption of a linearly decreasing collector current during fall time ts ¼ p  qs, starting at i(qs) at time qs and decaying to zero at time t2 ¼ p [36]. As a result, the power dissipated during transition can be then written by assuming in view of a short transition time that i(qs) ¼ i(p) ¼ 2I0 as Ps I0 t2s t2 ¼ ¼ s P0 12pwCVcc 12

(1.89)

High-efficiency power amplifier design

43

As a result, the collector efficiency h can be estimated as h¼1

Ps t2 ¼1 s P0 12

(1.90)

As follows from (1.89), the power losses due to nonzero switching time are sufficiently small and, for example, for ts ¼ 0.35 or 20
, they are only about 1%, whereas they are approximately equal to 10% for ts ¼ 60
. A more exact analysis assuming linear variation of the collector current during on-to-off transition produces similar results when efficiency degrades to 91.72% for ts ¼ 30
and to 90.76% for ts ¼ 60
[37]. Considering an exponential collector current decay rather than linear during the fall time shows similar result for ts ¼ 30
when h ¼ 96.8%, but the collector efficiency degrades more significantly at longer fall times when, for example, h ¼ 86.6% for ts ¼ 60
[38]. In a common case, the intrinsic output device capacitance is nonlinear, as shown in Figure 1.30(c). If its contribution in overall shunt capacitance is sufficiently large, it is necessary to consider the nonlinear nature of this capacitance when specifying the breakdown voltage. For example, the collector voltage waveform will rise in the case of the output capacitance described by abrupt diode junction in comparison with the linear capacitance, and its maximum voltage can be greater by about 20% for a 50% duty ratio [27,39]. However, stronger nonlinearity of the shunt capacitance causes the peak voltages to be higher [40]. At the same time, the deviations of the optimum load-network parameters are insignificant, less than 5% in a wide range of supply voltages. Because the nonlinear capacitance is largest at zero voltage, the collector waveform will rise more slowly than in the linear case. As the collector voltage increases, the capacitance will decrease, and hence the voltage should begin to rise faster than in the linear case. If the shunt capacitance consists of both nonlinear and linear capacitances, the collector voltage waveform is intermediate and located between the two extreme cases of entirely nonlinear or entirely linear capacitance [41].

1.3.3 Load network with transmission lines The transmission lines are often preferred over lumped inductors at microwave frequencies for high-power amplifiers because of the convenience of their practical implementation, more predictable performance, less insertion loss, and less effect of the parasitic elements. For example, the matching circuit can be composed with any types of the transmission lines, including open- or short-circuit stubs, to provide the required matching and harmonic suppression conditions. In this case, to approximate the idealized Class-E operation mode of the microwave power amplifier, it is necessary to design the transmission-line load network satisfying the required idealized optimum impedances at the fundamental-frequency and harmonic components. The device output capacitance can fully represent the required shunt capacitance, whose nominal value is defined by (1.79). Consequently, the main challenge is to satisfy the idealized optimum requirements for the

44

Radio frequency and microwave power amplifiers, volume 2

fundamental-frequency impedance ZL(w0) shown in Figure 1.31(a) and harmonic impedances ZL(nw0) shown in Figure 1.31(b), which can be written using (1.78) as   wL ¼ Rð1 þ j tan 49:052
Þ (1.91) ZL ðw0 Þ ¼ R þ jwL ¼ R 1 þ j R ZL ðnw0 Þ ¼ 1

(1.92)

where w0 is the fundamental angular frequency and n  2 is the harmonic number. Generally, it is practically impossible to realize these conditions for an infinite number of harmonic components by using only transmission lines. However, as it turns out from the Fourier-series analysis, a good approximation to Class-E mode may be obtained with the dc, fundamental-frequency, and second-harmonic components of the voltage waveform across the switch [42,43]. Figure 1.31(c) shows the collector (drain) voltage waveform containing these two harmonic components (dashed curve) plotted along with an ideal voltage waveform (solid curve). In practical implementation, the two-harmonic Class-E load network designed for microwave applications will include the series microstrip line l1 and open-circuit stub l2, as shown in Figure 1.32(a). The electrical lengths of microstrip lines l1 and l2 are chosen to be of about 45
at the fundamental frequency to provide an opencircuit condition seen from the device output at the second harmonic, according to (1.92). Their characteristic impedances are calculated to satisfy the required inductive impedance condition at the fundamental frequency given by (1.91). L

Transistor output

Cout

Transistor output

Cout

R ZL(ω0)

ZL(nω0)

(a)

(b)

v/Vcc 3 2 1 0



ωt 2

3

4

(c)

Figure 1.31 Optimum load impedance and two-harmonic Class-E voltage waveform

High-efficiency power amplifier design

45

l1

Transistor output

l2

Cout ZL

RL Vdd

(a) Transistor output

l1

Cout

l2

90° @ 1.8 GHz 90° @ 2.7 GHz

RL Vcc

(b)

Figure 1.32 Equivalent circuits of Class-E power amplifiers with transmission lines

However, for a packaged active device, its output lead inductance should be accounted for by shortening the length of l1. In some cases, a value of the device output capacitance exceeds the required nominal value for a Class-E mode with shunt capacitance. In this situation, it is possible to approximate Class-E mode with high efficiency by setting a properly optimized load at the fundamental frequency and strong reactive load at the secondand third-harmonic components [44]. Such a harmonic-control network consists of open-circuit quarterwave stubs at the second- and third-harmonic components separately, as shown in Figure 1.32(b), where the third-harmonic quarterwave stub is located before the second-harmonic quarterwave stub. As a result, a very high collector efficiency can be achieved even with values of the device output capacitance higher than conventionally required at the expense of lower output power, while keeping the load at the second and third harmonics strictly inductive (inverse mode).

1.3.4 Practical Class-E power amplifiers High level of output power with very high operational efficiency can be easily achieved in a Class-E mode by using high-voltage power MOSFET devices at high (HF) and very high (VHF) frequencies. Figure 1.33(a) shows the circuit schematic of a 27.12-MHz, 500-W Class-E MOSFET power amplifier with a drain efficiency of 83% at a supply voltage of 125 V [45]. The input ferrite transformer provides the

46

Radio frequency and microwave power amplifiers, volume 2 125 V 0.1 μF

10 nF

10 nF

0.1 μF

6 μH

ARF448A 210 nH

30 nF Pout

T1

Pin

75-380 pF

25 Ω 75-380 pF

(a) 470 pF –13.5 V

30 V

90 nH

1 nF

90 nH 220 nH Pin 50 Ω

12 pF

56 pF

47 nH

82 pF

CRF24060

24 pF

47 nH

68 pF

47 nH

47 pF

56 nH

Pout 50 Ω

22 pF

(b)

Figure 1.33 High-power lumped Class-E power amplifiers

2:1 transformation voltage ratio to match the gate impedance, which is represented by the parallel equivalent circuit with a capacitance of 2200 pF and a resistance of 210 W. Use of the external parallel resistor of 25 W simplifies the matching procedure and improves the amplifier stability conditions. The transformer secondary winding provides an inductance of 19 nH, which is required to compensate for the device input capacitance at the fundamental. High-quality passive components are necessary to use in the low-pass L-type output network, where the quality factor of the bare copper wire inductor was equal to 375. The series blocking capacitor consists of three parallel disc ceramic capacitors. To realize a Class-E operation with shunt capacitance, it is sufficient to be limited to only the output device capacitance with a value of 125 pF. This is just slightly larger than that required to obtain the idealized optimum drain voltage and current Class-E waveforms. Figure 1.33(b) shows the simplified circuit schematic of a silicon carbide (SiC) MESFET Class-E power amplifier that provides a maximum drain efficiency of 86.8% at an output power of 20.5 W at 145 MHz reached at a drain voltage of 30 V, with an input drive power level of 27 dBm [46]. The nominal Class-E impedance of

High-efficiency power amplifier design

47

approximately 18 W was matched to a 50-W load with a low-pass three-section L-type matching network to suppress harmonics by at least 60 dB below the carrier. The input of the active device was matched to 50-W source by means of a high-pass filter network to prevent the attenuation of the high-frequency harmonic components of the driving signal. Because this power amplifier was designed to provide linear amplification by restoring the input signal envelope with drain amplitude modulation, the drain bias network was built with a low-pass filter that allows drain modulating frequencies of up to a few megahertz to pass through it with minimum attenuation, while at the same time achieving acceptable isolation at the carrier frequency and its harmonics. Figure 1.34 shows the circuit schematic of a K-band transmission-line Class-E power amplifier using a single-section load network, which is well suited for monolithic implementation at upper microwave frequencies [47]. The electrical parameters of the capacitive stubs TL2 and TL3 were designed to provide low impedances at the second and third harmonics by making the electrical length of the stubs exactly one quarter-wavelength at a particular harmonic. At the same time, the characteristic impedances of the stubs are chosen to provide the desired capacitive reactance for load impedance transformation at the fundamental frequency. The electrical parameters of the series transmission line TL1 are determined by the requirements to provide the optimum inductive impedance with a load angle of 49.05
at the fundamental and to transform the low impedance of the stub inputs toward higher reactances at the selected harmonics. As a result, by using GaAs pHEMT technology and coplanar waveguides for transmission-line implementation, an output power of 20 dBm, a drain efficiency of 59%, and a power gain of 7.5 dB were achieved at an operating frequency of 24 GHz with a supply voltage of 2.4 V when both the second and third harmonics are suppressed by more than 30 and 35 dB, respectively.

Vg

R1 TL2 TL1

TL5

Pout

TL4 Pin C2

C1

TL3

Figure 1.34 Circuit schematic of transmission-line Class-E power amplifier

48

Radio frequency and microwave power amplifiers, volume 2

1.4 Class E with finite dc-feed inductance In practice, it is impossible to realize RF choke with infinite impedance at the fundamental frequency and other harmonic components. Moreover, using a finite dc-feed inductance has an advantage of minimizing size, cost, and complexity of the overall circuit. The detailed approach to analyzing the effect of a finite dc-feed inductance on the idealized Class-E mode with shunt capacitance and series filter was first described in [48]. An analysis was based on the Laplace-transform technique to solve a second-order differential equation describing the behavior of a Class-E load network with finite dc-feed inductance. Later this approach was extended to the load network with finite QL-factor of the series filter and finite device saturation resistance [49,50]. However, because the results of excessive analytical and numerical calculations are given only for a few special cases, it is difficult to figure out the basic behavior of the load-network elements and derive simple equations for their parameters. Later, it was analytically shown for a 50% duty ratio based on the optimum Class-E conditions that the series excessive reactance can be either inductive or capacitive depending on the values of the dcfeed inductance and shunt capacitance [51,52].

1.4.1

General analysis and optimum load-network parameters

The generalized second-order load network of a switching-mode Class E power amplifier with finite dc-feed inductance is shown in Figure 1.35(a) [53–55]. The load network consists of a shunt capacitor C, a parallel inductor L, a series inductor

Lb

jX

L0

C0

L

C

R Vcc

(a) Lb

i iC v

L0

C0

jX iLb C

iL

VX

L

iR VR

R

Vcc (b)

Figure 1.35 Equivalent circuits of the Class-E power amplifiers with generalized load network

High-efficiency power amplifier design

49

Lb, a series reactance X, a series resonant L0C0 circuit tuned to the fundamental frequency, and a load resistance R. In a common case, a shunt capacitance C can represent the intrinsic device output capacitance and external circuit capacitance added by the load network, a series inductor Lb can be considered a bondwire and lead inductance, a parallel inductance L represents the finite dc-feed inductance, and a series reactance X can be positive (inductance), negative (capacitance), or zero depending on the certain Class-E mode. The active device is considered an ideal switch that is driven to provide the device instant switching between its onstate and off-state operation modes. To simplify an analysis of the general-circuit Class-E power amplifier, whose simplified equivalent circuit is shown in Figure 1.35(b), it is best to introduce the preliminary assumptions similar to those for the Class-E power amplifier with shunt capacitance, assuming that the losses in the reactive circuit elements are negligible, the duty ratio is 50%, the loaded quality factor of the series L0C0 circuit is sufficiently high, and to set an inductance Lb to zero. For a lossless operation mode, it is necessary to provide the optimum zero-voltage and zero-voltage-derivative conditions for voltage v(wt) across the switch just prior to the start of switch on, when transistor is saturated, given by (1.62) and (1.63). The output current flowing through the load is written as sinusoidal by iR ðwtÞ ¼ IR sinðwt þ jÞ

(1.93)

where IR is the load current amplitude and j is the initial phase shift. When the switch is turned on for 0  wt < p, the voltage on the switch is v(wt) ¼ Vcc  vL(wt) ¼ 0, the current flowing through the capacitance is iC(wt) ¼ wC(dvL/dwt) ¼ 0, and iðwtÞ ¼ iL ðwtÞ þ iR ðwtÞ ¼ ¼

1 wL

ð wt

Vcc dwt þ iL ð0Þ þ IR sinðwt þ jÞ

0

Vcc wt þ IR ½sinðwt þ jÞ  sin j wL

(1.94)

where the initial value for the current iL(wt) flowing through the dc-feed inductance L at wt ¼ 0 can be found using (1.93) for i(0) ¼ 0 as iL(0) ¼ IRsin j. When the switch is turned off for p  wt < 2p, the switch current i(wt) ¼ 0, and the current iC(wt) ¼ iL(wt) þ iR(wt) flowing through the capacitance C can be rewritten as dvðwtÞ 1 ¼ wC dwt wL

ð wt p

½Vcc  vðwtÞdwt þ iL ðpÞ þ IR sinðwt þ jÞ

under the initial off-state conditions v(p) ¼ 0 and iL ðpÞ ¼ iðpÞ  iR ðpÞ ¼

Vcc p  wLIR sin j wL

(1.95)

50

Radio frequency and microwave power amplifiers, volume 2

Equation (1.95) can be represented in the form of the linear nonhomogeneous second-order differential equation: w2 LC

d 2 vðwtÞ d ðwtÞ2

þ vðwtÞ  Vcc  wLIR cosðwt þ jÞ ¼ 0

(1.96)

the general solution of which can be obtained in the normalized form: vðwtÞ q2 p ¼ C1 cosðqwtÞ þ C2 sinðqwtÞ þ 1  cosðwt þ jÞ Vcc 1  q2

(1.97)

where 1 q ¼ pffiffiffiffiffiffiffi w LC p¼

(1.98)

wLIR Vcc

(1.99)

and the coefficients C1 and C2 are determined from the initial off-state conditions [36]. The dc supply current I0 can be found using Fourier formula and (1.94) by I0 ¼

1 2p

ð 2p

iðwtÞdwt ¼

0

  IR p2 þ 2 cos j  p sin j 2p 2p

(1.100)

In an idealized Class-E operation mode, there is no nonzero voltage and current simultaneously that means a lack of power losses and gives an idealized collector efficiency of 100%. This implies that the dc power P0 and fundamental output power Pout are equal: I0 Vcc ¼

VR2 2R

(1.101)

where VR ¼ IRR is the fundamental voltage amplitude across the load resistance R. As a result, by using (1.100) and (1.101) and considering that R ¼ VR2 =2Pout , the optimum load resistance R for the specified values of a supply voltage Vcc and fundamental output power Pout can be obtained by R¼

  2 1 VR 2 Vcc 2 Vcc Pout

(1.102)

where   VR 1 p2 þ 2 cos j  p sin j ¼ Vcc p 2p

(1.103)

High-efficiency power amplifier design

51

The normalized load-network inductance L and capacitance C can be appropriately defined using (1.98) through (1.100) as   wL p 2 ¼p= þ cos j  sin j (1.104) R 2p p   2 wL wCR ¼ 1= q (1.105) R The series reactance X, which may have an inductive, capacitive, or zero reactance in special cases depending on the load-network parameters, can be generally calculated using two quadrature fundamental-frequency voltage Fourier components: 1 VR ¼  p VX ¼ 

1 p

ð 2p

vðwtÞsinðwt þ jÞdwt

(1.106)

vðwtÞcosðwt þ jÞdwt

(1.107)

0

ð 2p 0

The fundamental-frequency current flowing through the switch consists of two quadrature components, whose amplitudes can be found using Fourier formulas and (1.94) by ð 1 2p iðwtÞsinðwt þ jÞdwt IR ¼ p 0 (1.108)

 IR p cos j  2 sin j p þ  sin 2j ¼ p p 2 ð 2p 1 IX ¼  iðwtÞcosðwt þ jÞdwt p 0 (1.109)

 IR p sin j þ 2 cos j 2  2sin j ¼ p p Generally, (1.97) for normalized collector voltage contains three unknown parameters q, p, and j, which must be analytically or numerically determined. In a common case, the parameter q can be considered a variable, and the other two parameters p and j are calculated from a system of two equations resulting from applying two optimum zero-voltage and zero-voltage derivative conditions given by (1.62) and (1.63) to (1.97). Figure 1.36 shows the dependences of the optimum parameters p and j versus q for a Class E with finite dc-feed inductance. Based on the calculated optimum parameters p and j as functions of q, the optimum load-network parameters of the Class-E load network with finite dc-feed inductance can be determined using (1.102) through (1.105). The series reactance X

52

Radio frequency and microwave power amplifiers, volume 2 p

φ,°

20

80

15

60

10

40

5

20

0 0.8

1.1

–5

1.4

1.7

q

0 –20

Figure 1.36 Optimum Class-E parameters p and j versus q

can be calculated by the ratio of two quadrature fundamental-frequency voltage Fourier components given in (1.106) and (1.107) as X VX ¼ R VR

(1.110)

The dependences of the normalized optimum dc-feed inductance wL/R and series reactance X/R are shown in Figure 1.37(a), whereas the dependences of the 2 are normalized optimum shunt capacitance wCR and load resistance RPout =Vcc plotted in Figure 1.37(b). Here, the value of the series reactance X changes its sign from positive to negative, which means that the inductive reactance is followed by the capacitive reactance. As a result, there is a special case of the load network with a parallel circuit and a load resistor only when X ¼ 0 at q ¼ 1.412. In this case, the maximum value of the optimum load resistance R can be provided for the same supply voltage and output power, thus simplifying the matching with the standard load of 50 W. In addition, the values of a dc-feed inductance L become sufficiently small, making Class-E mode with a parallel circuit very attractive for monolithic applications. The maximum operation frequency fmax is realized at q ¼ 1.468, where the normalized optimum shunt capacitance wCR reaches its maximum.

1.4.2

Parallel-circuit Class E

The theoretical analysis of a switching-mode parallel-circuit Class-E power amplifier with a series filter, whose basic circuit schematic is shown in Figure 1.38(a), was first published by Kozyrev with calculation of the voltage and current waveforms and some graphical results [27,56]. The load network consists of a finite dc-feed inductor L, a shunt capacitor C, a series L0C0 resonant circuit tuned to the

High-efficiency power amplifier design X/R

ωL/R

15

1.5

10

1.0

5

0.5

0

53

0.8

1.1

1.4

1.7

0

q

–5

–0.5

–10

–1.0

–15

–1.5

(a) 2

RPout /Vcc

ωCR

1.25

1.25

1.0

1.0

0.75

0.75

0.5

0.5

0.25

0.25

0.5

0.8

1.1

1.4

1.7

q

(b)

Figure 1.37 Normalized optimum Class-E load network parameters

fundamental frequency, and a load resistor R. In this case, the switch sees a parallel connection of the load resistor R and parallel LC circuit at the fundamental frequency, as shown in Figure 1.38(b), where also the real and imaginary collector fundamental-frequency current components IX and IR and the real collector fundamental-frequency voltage component VR are indicated. In the case of a parallel-circuit Class-E load network without series phaseshifting reactance, because the parameter q is unknown a priori, generally it is necessary to solve a system of three equations to define the three unknown parameters q, p, and j. The first two equations are the result of applying two optimum

54

Radio frequency and microwave power amplifiers, volume 2 C0

L0

ϕ

L

R

C Vcc

(a)

IR IX C

L

VR

R

(b)

Figure 1.38 Equivalent circuits of parallel-circuit Class-E power amplifier zero-voltage and zero-voltage-derivative conditions given by (1.62) and (1.63) to (1.97). Because the fundamental-frequency collector voltage is fully applied to the load, this means that its reactive part must have zero value, resulting in an additional equation: ð 1 2p vðwtÞcosðwt þ jÞdwt ¼ 0 (1.111) VX ¼  p 0 Solving the system of three equations with three unknown parameters numerically gives the following values [57,58]: q ¼ 1:412

(1.112)

p ¼ 1:210

(1.113)

j ¼ 15:155




(1.114)

Figure 1.39 shows the normalized (a) load current, (b) collector voltage, and (c) current waveforms for an idealized optimum parallel-circuit Class-E operation mode. From collector voltage and current waveforms, it follows that, like other Class-E subclasses, there is no nonzero voltage and current simultaneously. When this happens, no power loss occurs and an idealized collector efficiency of 100% is achieved. By using (1.102) through (1.105), the idealized optimum (or nominal) load resistance R, parallel inductance L, and parallel capacitance C can be appropriately obtained by R ¼ 1:365

2 Vcc Pout

(1.115)

High-efficiency power amplifier design

55

iR/I0 1.0 0.5 0

60

120

180

240

300

ωt,°

60

120

180

240

300

ωt,°

60

120

180

240

300

ωt,°

–0.5 –1.0

(a) v/Vcc

3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 (b) i/I0

2.5 2.0 1.5 1.0 0.5 0

0

(c)

Figure 1.39 Normalized (a) load current, (b) collector voltage, and (c) current waveforms for idealized optimum parallel-circuit Class E L ¼ 0:732 C¼

R w

0:685 wR

(1.116) (1.117)

The dc supply current I0 can be calculated from (1.100) as I0 ¼ 0:826IR

(1.118)

56

Radio frequency and microwave power amplifiers, volume 2

The phase angle f seen from the device collector at the fundamental frequency can be represented either through two fundamental-frequency current quadrature Fourier components IX and IR given by (1.108) and (1.109) or as a function of the load-network elements by   R 1  wRC ¼ 34:244
(1.119) f ¼ tan wL If the calculated value of the optimum Class-E load resistance R is too small or differs significantly from the standard load impedance (usually equal to 50 W), it is necessary to use an additional matching circuit to deliver maximum output power to the load. It should be noted that, among a family of the Class-E load networks, a parallel-circuit Class-E load network offers the largest value of R, thus simplifying the final matching design procedure. In this case, the first series element of such matching circuits should be the inductor to provide high impedance conditions for harmonics, as shown in Figure 1.40. The peak collector current Imax and peak collector voltage Vmax can be determined from (1.94), (1.97), and (1.118) as Imax ¼ 2:647I0

(1.120)

Vmax ¼ 3:647Vcc

(1.121)

The maximum frequency fmax can be calculated using (1.115) and (1.117) when C ¼ Cout, where Cout is the device output capacitance, as fmax ¼ 0:0798

Pout 2 Cout Vcc

(1.122)

which is 1.57 times higher than the maximum operation frequency for an optimum Class-E power amplifier with shunt capacitance given by (1.82).

1.4.3

Even-harmonic Class E

The well-defined analytic solution based on an assumption of the even-harmonic resonant conditions when the finite dc-feed inductance and parallel capacitance are Matching circuit

C

C2

L1

Device output

L

R

C1

RL

Figure 1.40 Parallel-circuit Class-E power amplifier with lumped matching circuit

High-efficiency power amplifier design

57

tuned to any even-harmonic component was given in [59]. The load network of an even-harmonic Class E is shown in Figure 1.41, where the series capacitor CX is needed to compensate for the excessive inductive reactance caused by the preliminary choice of the specified load-network parameters. The value of this capacitance can be found from the consideration of two fundamental-frequency voltage quadrature components across the switch given by (1.106) and (1.107). Since, for an even-harmonic Class-E operation mode, the dc-feed inductance is restricted to values that satisfy an even-harmonic resonance condition and it is assumed the fundamental-frequency voltage across the switch and output voltage across the load have a phase difference of p/2, the two unknown parameters can be set in this specified case as q ¼ 2n

(1.123)

j ¼ 90


(1.124)

where n ¼ 1, 2, 3, . . . . The third parameter p can be found using an idealized optimum zero voltagederivative condition given by (1.63) as p¼

4n2  1 p 8n2

(1.125)

The dc supply current I0 can be found from (1.100) by ð 1 2p 1 IR iðwtÞdwt ¼ I0 ¼ 2 2p 0 2ð4n  1Þ

(1.126)

As a result, the normalized steady-state collector voltage waveform for p  wt < 2p and current waveform for period of 0  wt < p are vðwtÞ p p sinð2nwtÞ  cosð2nwtÞ ¼ 1  sin wt þ Vcc 2 4n

2   2 iðwtÞ 8n 2 wt  4n þ 1 þ 4n  1 cos wt ¼2 p I0

(1.127) (1.128)

Figure 1.42 shows the normalized (a) load current, (b) collector voltage, and (c) collector current waveforms for an idealized optimum even-harmonic Class-E mode. If the collector voltage waveform corresponding to even-harmonic CX

ϕ

L

C

L0

C0

R

Vcc

Figure 1.41 Equivalent circuit of the even-harmonic Class-E power amplifier

58

Radio frequency and microwave power amplifiers, volume 2 iR/I0

4 2 0

ωt, °

60

120

180

240

300

60

120

180

240

300

ωt, °

60

120

180

240

300

ωt, °

–2 –4 –6 (a) v/Vcc 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0

0

(b) i/I0 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 (c)

Figure 1.42 Normalized (a) load current, (b) collector voltage, and (c) current waveforms for idealized optimum even-harmonic Class E

Class E is very similar to the collector voltage waveform corresponding to Class E with shunt capacitance, then the behavior of the collector current waveform is substantially different. For even-harmonic Class-E configuration, the collector current reaches its peak value, which is four times as high as the dc current, at the end of the conduction interval. Consequently, in the case of a sinusoidal driving

High-efficiency power amplifier design

59

signal it is impossible to provide close to the maximum collector current when the input base current is smoothly reducing to zero. The optimum load-network parameters for the most practical case when n ¼ 1 can be calculated from: R¼

2 1 Vcc V2 ¼ 0:056 cc Pout 18 Pout

(1.129)

L¼

9p R R ¼ 3:534 8 w w

(1.130)

C¼

2 1 1 ¼ 0:071 9p wR wR

(1.131)

CX ¼

4p 1 1 ¼ 0:204 2 32 þ 3p wR wR

(1.132)

The main problem of an even-harmonic Class-E operation mode is a substantially small value of the load resistance R, which is over an order of magnitude smaller than for a Class E with shunt capacitance and much smaller than for a parallel-circuit Class E. The phase angle f between the fundamental-frequency voltage and current components seen by switch is equal to f¼

3 R 1 þ ðwCX RÞ2 1 ¼ 22:302
 4 wL ðwCX RÞ2 wCX R

(1.133)

whereas the maximum frequency fmax, up to which an idealized optimum evenharmonic Class-E mode can be realized, is calculated from: fmax ¼

2 Pout Pout ¼ 0:203 2 2 Cout Vcc p2 Cout Vcc

(1.134)

where Cout is the device output capacitance.

1.4.4 Load networks with transmission lines At microwave frequencies, the parallel inductance L can be replaced by a shortlength short-circuited transmission line TL according to Z0 tan q ¼ wL

(1.135)

where Z0 and q are the characteristic impedance and electrical length of such a transmission line, respectively [60]. By using (1.116) defining the idealized optimum (or nominal) parallel inductance L for a parallel-circuit Class-E mode, (1.135) can be rewritten as tan q ¼ 0:732

R Z0

(1.136)

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Radio frequency and microwave power amplifiers, volume 2

Generally, the load-network circuit can be composed with any types of transmission lines, including open-circuit or short-circuit stubs to provide the required matching and harmonic-suppression conditions. In some cases, for example, for compact small-size power-amplifier modules designed for handset or small-cell wireless transmitters, the series microstrip lines and shunt chip capacitors are usually used in the external output matching circuits. However, to maintain the optimum-switching conditions at the fundamental frequency, such an output matching circuit should contain the series transmission line as the first element. Figure 1.43(a) shows an example of the transmission-line Class-E load network of a two-stage 1.75 GHz GaAs HBT power amplifier with an output power of 33 dBm, which was designed for a cellular handset transmitter, and includes the series microstrip line with two shunt chip capacitors [57]. However, because of the fixed electrical lengths of the transmission lines, it is impossible to realize simultaneously the required inductive impedance at the fundamental frequency with the purely capacitive reactances at higher-order harmonics. For example, at the second harmonic, the real part of the load network impedance Znet(2w0) is sufficiently high, as shown in Figure 1.43(b). Nevertheless, even such an approximation provides a good proximity to the parallel-circuit Class-E operation mode, resulting in a high operating efficiency of the power amplifier. In this case, there is no need to use an additional RF choke for dc supply current, because its function can be performed by the same short-length parallel microstrip line required to provide an optimum inductive impedance at the fundamental frequency.

Znet(ω0)

3.5 V Znet(2ω0) Cbypass

Znet(3ω0)

50 Ω 12°

(b)

30 Ω, 8°

Cout Znet(ω)

5 pF

50 Ω, 16°

4 pF

10 pF

50 Ω

R

(a)

Figure 1.43 Transmission-line load network of parallel-circuit Class-E power amplifier for handset application

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61

The circuit schematic of a two-stage InGaP/GaAs HBT power amplifier intended to operate in the WCDMA handset transmitters is shown in Figure 1.44(a) [61]. The MMIC part of this power amplifier contains the transistors with emitter areas of the first and second stage as large as 540 mm2 and 3600 mm2, input matching circuit, interstage matching circuit, and bias circuits on a die with overall dimension of less than 1 mm2. The broadband capability of the PA was verified with regard to the DCS1800 and PCS1900 frequency bands. Without any tuning of the output matching circuit, a saturated output power greater than 30 dBm and a PAE greater than 50% were obtained. Using high-Q capacitors in output matching circuit can improve the power-added efficiency by about 8%. The power gain of 22.5  0.5 dB and the input return loss greater than 13 dB were measured from 3.5 V

Z0 = 50 Ω θ = 15°

2.7 V

Bias circuit

Bias circuit

Pout

Pin

MMIC

(a) Vdd

Vg 1 kΩ

1 nH λ/4 470 pF 12 Ω 470 pF Pin

Pout MRF21010 9.1 pF

15 pF

(b)

Figure 1.44 Schematics of Class-E power amplifiers with transmission-line matching

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Radio frequency and microwave power amplifiers, volume 2

1.6 GHz to higher than 2 GHz. At the same time, this power amplifier without any additional tuning could provide the high-linearity performance for WCDMA band (1920–1980 MHz) at a 3.5-dB backoff output power of 27 dBm with a power gain of 22.6 dB and a sufficiently high efficiency. The measured PAE reached value of 38.3% at center bandwidth frequency of 1.95 GHz with an adjacent channel leakage power ratio (ACLR) of –37 dBc at a 5-MHz offset. Figure 1.44(b) shows the circuit schematic of a 1-GHz 12-V LDMOSFET parallel-circuit Class-E power amplifier with a drain efficiency of 70.4% and an output power of more than 38 dBm [62]. In this case, the series LC resonant circuit is replaced by a low-pass L-type output matching circuit with a series transmission line to match the low optimum Class-E resistance to a 50-W load, having almost zero series excessive reactance X. The quarterwave transmission line in the gate bias circuit provides RF isolation from the dc-voltage supply, and the 12-W gate resistor is required for stability reason.

1.5 Class E with shunt capacitance and shunt filter Class E with shunt capacitance and shunt filter represents an alternative to Class E with shunt capacitance and series filter when high loaded quality of the shunt filter is provided by higher value capacitance rather than inductance, thus making such a Class-E power amplifier more compact when no need to use high-value inductors in both dc-supply and resonant circuits. In this case, much better harmonic suppression can be achieved by using a high-Q shunt filter with a low-value shunt capacitance. The theoretical analysis and practical implementation of a vacuumtube Class-E amplifier with shunt filter was first provided in late 1960s [24]. This circuit was analyzed by solving the second-order differential equation for voltage across shunt capacitor but the final design equations for the load-network parameters were not derived in explicit form. The anode voltage and current waveforms were analytically derived and numerically calculated for the specific case of q ¼ 2.

1.5.1

Basic analysis and optimum load-network parameters

The optimum parameters of a single-ended Class-E power amplifier with shunt capacitance and shunt filter can be determined based on an analytical derivation of its steady-state collector voltage and current waveforms. Figure 1.45(a) shows the basic circuit configuration of a Class-E power amplifier with shunt capacitance and shunt filter, where the load network consists of a shunt capacitor C, a series inductor L, a blocking capacitor Cb, a shunt fundamentally tuned L0C0 circuit, and a load resistor R [63,64]. In this case, the shunt L0C0 circuit operates as a harmonic filter creating zero impedance at the second- and higher-order harmonics instead of the open-circuit harmonic conditions corresponding to classical Class-E power amplifier with shunt capacitance and series filter. In a common case, a shunt capacitance C can represent the intrinsic device output capacitance and external circuit capacitance added by the load network. The dc power supply is generally

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63

Cb

L

C

C0

L0

R

Vcc (a)

Vcc

L iC

i v

iR

iL I0

C

L0

C0

R

vR

Vcc (b)

Figure 1.45 Basic circuits of Class-E power amplifier with shunt filter

connected by an RF choke with infinite reactance at the fundamental and any higher-order harmonic component. The active device is considered an ideal switch that is driven at the operating frequency to provide instantaneous switching between its on-state and off-state operation conditions. To simplify the analysis of a Class-E power amplifier with shunt filter, whose equivalent circuit is shown in Figure 1.45(b), the following several assumptions are introduced: ●

● ●

● ●

the transistor has zero saturation voltage, zero saturation resistance, infinite off-resistance, and its switching is instantaneous and lossless; the shunt capacitance is assumed to be constant; the shunt L0C0 filter has zero impedance at the second- and higher-order harmonics; there is no loss in the circuit except the load R; and for simplicity, a 50% duty ratio is used.

For idealized lossless operation mode, it is necessary to provide the zerovoltage and zero-voltage-derivative conditions for voltage across the switch (just prior to the start of switch on) at the instant wt ¼ 2p, when transistor is saturated. Then, expressions for the collector current (0  wt < p) and voltage (p  wt < 2p) for ideal L0C0-circuit tuned to the fundamental frequency when the sinusoidal current iR ¼ IR sin(wt þ j) flows into the load can be written as Vcc VR wt þ ½cosðwt þ jÞ  cos j wL wL

(1.137)

þ vðwtÞ  Vcc þ VR sinðwt þ jÞ ¼ 0

(1.138)

iðwtÞ ¼ iL ðwtÞ ¼ w2 LC

d 2 vðwtÞ d ðwtÞ2

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Radio frequency and microwave power amplifiers, volume 2

where j is the initial phase shift and VR ¼ IRR is the voltage amplitude across the load resistance R [63]. The general solution of (1.138) can be given in the normalized form as V ðwtÞ q2 VR ¼ C1 cos qwt þ C2 sin qwt þ 1 þ sinðwt þ jÞ (1.139) 1  q2 Vcc Vcc pffiffiffiffiffiffiffi where q ¼ 1=w LC and the coefficients C1 and C2 are determined from the initial off-state conditions. The fundamental-frequency voltage across the switch consists of two quadrature components with an amplitude of the real component defined by Fourier formula as VR ¼ 

1 p

ð 2p

vðwtÞsinðwt þ jÞdwt:

(1.140)

0

As a result, by solving a system of three equations—two of them defined by the Class-E switching conditions given by (1.62) and (1.63) and the third one for VR given by (1.140)—the three unknown parameters can be calculated as j ¼ 41:614


(1.141)

q ¼ 1:607

(1.142)

VR ¼ 0:9253 Vcc

(1.143)

The dc current I0 can be determined by applying a Fourier-series expansion to (1.137). Then, the optimum normalized series inductance L and shunt capacitance C can be defined using (1.141) through (1.143) and assuming an idealized collector efficiency of 100% given by (1.101) as L ¼ 1:4836 C¼

R w

0:261 wR

(1.144) (1.145)

whereas the optimum load resistance R can be obtained for the given supply voltage Vcc and fundamental output power Pout by R¼

  2 1 VR2 1 VR 2 Vcc V2 ¼ ¼ 0:4281 cc : Pout 2 Pout 2 Vcc Pout

(1.146)

Figure 1.46 shows the normalized collector (a) voltage and (b) current waveforms for idealized optimum Class-E mode with shunt filter during the entire interval 0  wt  2p. From the collector voltage and current waveforms, it follows that, when the transistor is turned on, there is no voltage across the switch and the current from the inductor flows through the switch. However, when the transistor is turned off, this current flows through the capacitor C. In this case, there is

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65

v/Vcc 3.0 2.0 1.0

0 (a)



2

ωt



2

ωt

i/I0

2.0 1.0

0 (b)

Figure 1.46 Normalized (a) collector voltage and (b) current waveforms for idealized optimum Class E with shunt filter no nonzero voltage and current simultaneously, which means a lack of the power losses that gives an idealized collector efficiency of 100%. The phase angle f of the load network at fundamental seen by the switch which is required for an idealized optimum (or nominal) Class-E mode with shunt capacitance and shunt filter can be determined through the load-network parameters using (1.144) and (1.145) as 0 1   wL wCR B C  tan1 @ (1.147) f ¼ tan1 A ¼ 32:945
wL R wCR 1 R The peak collector voltage Vmax and current Imax are defined as Vmax ¼ 3:677 Vcc Imax ¼ 2:768 I0

(1.148) (1.149)

that shows that the voltage peak factor is as high as in classical Class E with shunt capacitance and series filter [36]. In Table 1.2, the optimum impedances seen by the device collector at the fundamental-frequency and higher-order odd and even harmonic components are illustrated by the appropriate circuit configurations. As it is seen, Class-E mode

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Radio frequency and microwave power amplifiers, volume 2

Table 1.2 Optimum impedances at fundamental and harmonics Class-E load network

f0 (fundamental)

(2n þ 1)f0 (odd harmonics)

2nf0 (even harmonics)

L

Class E with shunt capacitance and series filter

C

Class E with quarterwave line and series filter [36]

C

R

C

L C

C

R

C

L

R

C

L

L

Class E with shunt capacitance and shunt filter

C

C

L

Table 1.3 Load-network parameters for different Class-E modes Normalized load-network parameter

Class E with shunt capacitance and series filter

Class E with quarterwave line and series filter [36]

Class E with shunt capacitance and shunt filter

wL R wCR Pout R 2 Vcc

1.1525

1.349

1.4836

0.1836 0.5768

0.2725 0.465

0.261 0.4281

0.0507

0.093

0.097

2 fmax Cout Vcc Pout

with shunt capacitance and shunt filter shows different impedance properties from other alternative Class-E load networks. At even harmonics, its optimum impedances can be established by the parallel LC circuit, similarly to Class E with quarterwave line and series filter. However, at odd harmonics, the optimum impedances for Class E with shunt capacitance and shunt filter differ from Class E with series filter and Class E with quarterwave line where impedances are defined by the shunt capacitances, because they are also provided by the parallel LC circuits. The optimized load-network parameters of the different Class-E modes including Class E with series filter, Class E with quarterwave line, and Class E with shunt filter are shown in Table 1.3 in a normalized form. As can be seen, Class E with shunt filter offers the larger value of the shunt capacitance C for the same load

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67

R and much higher value of the maximum operating frequency fmax for the same dc supply voltage Vcc, device output capacitance Cout, and output power Pout, compared to Class E with shunt capacitance and series filter. At the same time, difference between Class E with quarterwave line and Class E with shunt filter is not so significant because the quarterwave line being grounded at its end through bypass capacitor operates for even harmonics as a shunt filter. Note that generally the shunt capacitance can differ from its nominal Class-E value defined by (1.145) at high operating frequencies because the value of the device output capacitance is too large. To compensate for the excess capacitance, need to add an additional reactive element between the shunt filter and the load resistance, similar to Class E with finite dc-feed inductance. An example of such a Class-E load network with an additional reactance where the value of the circuit parameter q is smaller than its nominal value given by (1.142) was analyzed in [65]. In this case, a shunt capacitance with optimum value was connected in parallel to the load resistance.

1.5.2 Load network with transmission lines Figure 1.47 shows the circuit schematic of a high-efficiency Class-E power amplifier with transmission-line shunt filter and output matching circuit, where the nominal load resistance R ¼ ReZnet(w0) is matched to the standard load impedance RL ¼ 50 W at the fundamental frequency using an output transmission-line L-type impedance transformer. Here, the shunt harmonic filter is composed of 45
short-circuit and open-circuit stubs to create short-circuited conditions at even harmonics. To create a short-circuited condition at the third harmonic at the right-hand side of the series inductor represented by a short-length series transmission line with the characteristic impedance Z0 and electrical length q, the series transmission line with electrical length of 60
and an open-circuit stub with electrical length of 30
are used. For electrical length of a sufficiently short series transmission line with the characteristic impedance Z0 and electrical length q of less than 45
, the required Vdd

45° Z0, θ

C

Z1, 60°

45°

Znet

Z2, 30°

RL

Figure 1.47 Schematic of Class-E power amplifiers with transmission-line load network

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Radio frequency and microwave power amplifiers, volume 2

optimum value of q for Class-E mode with shunt capacitance and shunt filter using (1.144) can be approximated by   R (1.150) q ¼ tan1 1:4836 Z0 The output matching circuit is necessary to match to the required optimum Class-E resistance R calculated in accordance with (1.146) to the standard load resistance of 50 W. In addition, it is required to provide a short-circuit condition at the third harmonic component. This can be easily done using the output matching topology in the form of an L-type transformer with the series transmission line and open-circuit stub. Its load-network impedance Znet at the fundamental can be written as Znet ¼ Z1

RL ðZ2  Z1 tan 30
tan 60
Þ þ jZ1 Z2 tan 60
Z1 Z2 þ jðZ1 tan 30
þ Z2 tan 60
ÞRL

(1.151)

where Z1 and Z2 are the characteristic impedances of the series transmission line and shunt open-circuit stub, respectively. Consequently, the complex-conjugate matching with the load at the fundamental can be provided by proper choice of the characteristic impedances Z1 and Z2. Separating (1.151) into real and imaginary parts and considering that ReZnet ¼ R and ImZnet ¼ 0, the system of two equations with two unknown parameters can be written as ðZ1 þ 3Z2 Þ2 R2L R  3Z12 Z22 ½4RL  3R ¼ 0 3Z12 Z22

þ

R2L ðZ1

þ 3Z2 ÞðZ2  Z1 Þ ¼ 0

(1.152) (1.153)

which enables the characteristic impedances Z1 and Z2 to be properly calculated. This system of two equations can be explicitly solved as a function of the parameter r ¼ RL/R, resulting in pffiffiffiffiffiffiffiffiffiffiffiffiffi Z1 4r  1 ¼ pffiffiffi (1.154) RL 3r Z1 r  1 (1.155) ¼ Z2 r As a result, for specified value of the parameter r with the required optimum load resistance R, corresponding to Class E with shunt capacitance and shunt filter, and standard load RL ¼ 50 W, first the characteristic impedance Z1 is calculated from (1.154) and then the characteristic impedance Z2 is calculated from (1.155). For example, if the required optimum load resistance is equal to R ¼ 20 W, resulting in r ¼ 2.5, the characteristic impedance of the series transmission line is equal to Z1 ¼ 35 W and the characteristic impedance of the open-circuit stub is equal to Z2 ¼ 58 W.

1.5.3

Design example of transmission-line Class-E power amplifier

Figure 1.48 shows the simulated circuit schematic, which approximates the transmission-line Class-E power amplifier with shunt filter and based on a 28-V

High-efficiency power amplifier design

69

28 V

–2.45 V Subst = RO4350 W = 45 mil L = 250 mil

R = 10 Ohm

Subst = RO4350 W = 150 mil L = 270 mil

Subst = RO4350 W = 350 mil L = 380 mil

C = 3 pF

Subst = RO4350 W = 67 mil L = 415 mil Subst = RO4350 W = 180 mil L = 450 mil

C = 5 pF

CGH40010F Pin Z = 50 Ohm

Subst = RO4350 W = 67 mil L = 415 mil

Subst = RO4350 W = 180 mil L = 520 mil

Z = 50 Ohm

Subst = RO4350 W = 120 mil L = 230 mil

Figure 1.48 Circuit schematic of transmission-line Class-E GaN HEMT power amplifier with shunt filter

Drain efficiency 100

25

80

20

60

15

40

10

20

5

Drain efficiency (%)

Power gain (dB)

Power gain 30

0 0

5

10 15 20 Input power (dBm)

25

30

Figure 1.49 Simulated results of transmission-line Class-E GaN HEMT power amplifier with shunt filter

10-W Cree GaN HEMT power transistor CGH40010F and transmission-line load network including a shunt filter and a transmission-line matching section. The input matching circuit provides a complex-conjugate matching with the standard 50-W source. The load network was slightly modified by optimizing the parameters of the series and shunt transmission lines because the device output capacitance Cout and series inductance Lout formed by drain bondwires and package lead do not match the required exact values of C and L for a nominal Class-E mode with shunt filter. For the transmission-line GaN HEMT Class-E power amplifier with shunt filter using a 30-mil RO4350 substrate, the simulated drain efficiency of 83%, a PAE of 80.4%, and a power gain of 15 dB at an output power of 40.3 dBm with a quiescent current of 30 mA are achieved at an operating frequency of 2.14 GHz with a supply voltage of 28 V, as shown in Figure 1.49. The second and third harmonics were suppressed by greater than 50 dB.

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Radio frequency and microwave power amplifiers, volume 2

1.6 Biharmonic Class-EM power amplifier A basic limitation of a Class-E operation mode at higher frequencies is significant efficiency degradation due to the increased switching power losses with increasing values of the turn-off switching time. To minimize this undesirable effect, it is necessary to find a solution without instant jump in an ideal collector current waveform at turn-off to allow efficient operation at frequencies high enough that the switch turn-off transition would occupy a substantial fraction of the waveform period, of 30% and more. However, the Class-E power amplifier can deliver nonzero output power only if at least one of the switch waveforms, either voltage or current, has a jump under assumption that the circuit comprises an ideal switch and linear passive components [32]. To satisfy the requirements of both jumpless voltage and current waveforms and sinusoidal load waveform with nonzero output power delivered to the load, it is necessary to allow power flow in the system at two or more harmonically related frequencies. This can be done by using nonlinear reactive elements in the load network to convert the fundamental-frequency power to a desired harmonic frequency or by injecting the harmonic-frequency power into the load network from an external source. The simplest low-order implementation approach having jumpless switch voltage and current waveforms, called the biharmonic Class-EM mode and described in [66], comprises the two-part output stage including ●

●

main amplifier that consumes dc power equal to approximately 75% of the load power and converts this power and the power generated by the auxiliary amplifier to power at the output frequency f and smaller auxiliary amplifier (or varactor frequency multiplier) phased locked to the main amplifier, which generates approximately 25% of the load power at the frequency 2f.

The main amplifier has jumpless switch voltage and current waveforms, whereas the auxiliary amplifier can be a conventional Class-E power amplifier. If the frequency multiplier is fed from the output of the main amplifier, the load power is reduced by the amount of power converted by the frequency multiplier from frequency f to frequency 2f to change the waveform shapes to continuous ones. The higher-order implementations can use harmonic components of order higher than two, or multiple harmonics. For operation at higher frequencies, the biharmonic Class-EM power amplifier can be energetically superior to a conventional Class-E power amplifier using the same power device and supplying the same output power at the same operating frequency. That is because it can tolerate slow transistor turn-off with much less efficiency loss. In addition, less input drive is needed for the biharmonic Class-EM power amplifier because slower switching times are tolerable when considering that switching times are inversely proportional to the square root of the input driving power.

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71

11.5 V

Z = R + jX

179.8 μH

6.4 μH IRFZ24N

603 pF 3.5 MHz

50 Ω

11.5 V

100 μH

110 pF

4.78 μH Zinj = Rinj + jXinj

IRFZ24N 510 pF 7 MHz

Injection auxiliary generator

Figure 1.50 Biharmonic Class-EM power amplifier schematic Figure 1.50 shows the circuit schematic of a biharmonic Class-EM MOSFET power amplifier designed to operate at 3.5 MHz with second-harmonic power injection from an auxiliary amplifier operating at 7 MHz. The derivation of the ideal drain waveforms of the main amplifier assumes that the resultant current of the active device, operating as a switch, and its shunt capacitor contains only dc, fundamental, and second-harmonic components written as iðwtÞ ¼ I0 þ I1A cos wt þ I1B sin wt þ I2A cos 2wt þ I2B sin 2wt

(1.156)

where I0 is the dc current, I1A and I1B are the quadrature fundamental current components and I2A and I2B are the quadrature second-harmonic current components, respectively. The shunt capacitances at the transistor drains can be composed of the device output capacitances and external capacitances. For a 50% duty ratio when the switch is turned off during 0 < wt  p, the current through the switch i(wt) ¼ 0, and the current iC(wt) flowing through the capacitor C fully represents the current i(wt) given in (1.156), reproducing the voltage across the switch by charging of this capacitor according to ð 1 wt iðwtÞdwt (1.157) vðwtÞ ¼ wC 0

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Radio frequency and microwave power amplifiers, volume 2

The conditions for a biharmonic Class-EM optimum operation with jumpless voltage and current waveforms, v(wt) and i(wt), are written as iðwtÞjwt¼0 ¼ 0

(1.158)

iðwtÞjwt¼p ¼ 0

(1.159)

vðwtÞjwt¼p ¼ 0  vðwtÞ  ¼0 dwt wt¼0

(1.160) (1.161)

Substituting (1.156) into (1.157) and applying the boundary conditions given by (1.158) through (1.161) yield: I1A ¼ 0 I1B

p ¼  I0 2

(1.162) (1.163)

I2A ¼ I0

(1.164)

p I0 4

(1.165)

I2B ¼

As a result, the normalized steady-state idealized switch voltage waveform for a period of 0  wt < p and current waveform for a period of p  wt < 2p are obtained by iðwtÞ p p ¼ 1  sin wt þ sin 2wt  cos 2wt I0 2 4

(1.166)

vðwtÞ 2 ¼ ð8wt þ 4p cos wt  p cos 2wt  4sin 2wt  3pÞ Vdd p

(1.167)

where Vdd is the dc supply voltage. Figure 1.51(b) shows the normalized switch voltage and current waveforms for an idealized optimum biharmonic Class EM with second-harmonic power injection. From switch voltage and current waveforms, it follows that, when the transistor is turned on, there is no voltage across the switch and the current i(wt) consisting of the dc, fundamental, and injected second-harmonic components flows through the device. However, when the transistor is turned off, this current flows through the shunt capacitance C. There is no jump in the switch current waveform at the instant of switching off compared to the switch current corresponding to a Class E with shunt capacitance, the voltage and current waveforms of which are shown in Figure 1.51(a). However, the voltage peak factor is higher in a biharmonic Class-EM mode exceeding a value of 4. Note that injecting a higher-order harmonic component will generally increase the voltage peak factor even more. Also, there is no solution for a biharmonic Class-EM mode with third-harmonic injection and duty ratio of 50%. The voltage peak factor can exceed a value of 7 for a thirdharmonic injection with a duty ratio of 33%. The voltage and current waveforms of

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73

v/Vdd, i/I0 3.5 3 2.5 2 1.5

Current

Voltage

1 0.5 0 0

60

120

180

240

300

360

300

360

ωt, °

(a) v/Vdd, i/I0 4 3.5 3 2.5 2 1.5

Current

Voltage

1 0.5 0 0

60

120

180

240

ωt, °

(b)

Figure 1.51 Normalized ideal switch waveforms of (a) Class-E with shunt capacitance and (b) biharmonic Class-EM with second-harmonic power injection

the auxiliary amplifier are the usual waveforms corresponding to a Class E with shunt capacitance. In a biharmonic Class-EM mode, it is assumed that the dc power P0 ¼ I0Vdd is equal to approximately 75% of the output load power Pout delivered to the load that results in I0 Vcc ¼

3 Pout 4 Vdd

(1.168)

The fundamental-frequency load-network impedance of the main amplifier and the second-harmonic injection-port impedance of the auxiliary amplifier can be determined by a Fourier-series analysis of the voltage and current waveforms. As a result, the optimum shunt capacitance C and load-network impedance Z ¼ R þ jX

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Radio frequency and microwave power amplifiers, volume 2

for the main amplifier as a function of the dc supply voltage Vdd and output power Pout are written as C¼

3p Pout 2 64 wVdd

(1.169)

R¼

2 128 Vdd 9p2 Pout

(1.170)

X ¼

2 32ð3p2  32Þ Vdd Pout 9p3

(1.171)

whereas the optimum injection-port impedance Zinj ¼ Rinj þ jXinj for the auxiliary amplifier can be calculated from: Rinj ¼

2 128 Vdd 9ðp2 þ 16Þ Pout

Xinj ¼ 

2 16ð3p2 þ 16Þ Vdd 9pðp2 þ 16Þ Pout

(1.172) (1.173)

The measured output power of a second-harmonic Class-EM power amplifier was 13.2 W with overall PAE of 85.2% at an operating frequency of 3.5 MHz. The injected power at 2f necessary to achieve jumpless drain waveforms was measured as 29.8% of the total dc power of the main amplifier instead of the theoretical value of 25% due to the resistive power losses in reactive components, finite loaded quality factors of the series filters, and harmonic power conversions in the nonlinear device capacitances. To achieve simple and accurate design for the Class-EM power amplifier with higher-order circuits, the numerical design procedure can be applied [67]. The analytical expressions for Class-EM power amplifier considering the fundamental-frequency and harmonic components in the output currents of the main and auxiliary circuits are given in [68]. Figure 1.52 shows the comparison between power-added efficiencies of the second-harmonic Class-EM and classical Class-E power amplifiers as functions of the normalized transistor switching time ts [66]. It is assumed that the switching time is inversely proportional to the input-drive power. The plots were simulated for power amplifiers delivering the output power 3.2 W at an operating frequency of 870 MHz using a pHEMT device with a gate periphery of 0.5 mm  50 mm in the main amplifier. The peak value of a PAE for the biharmonic Class-EM power amplifier is 3.3% lower than that for the classical Class-E power amplifier. However, a PAE for the Class-EM power amplifier varies by just 2% for all switching times from 6% to 30% of the period, whereas a PAE for the Class-E power amplifier drops monotonically from its peak to 73.5% of its peak value for switching times of 30% of the period. In an alternative configuration of the biharmonic Class-EM power amplifier, one of the harmonics existing at drain of the main stage is filtered, amplified, phase shifted, and injected back to output of the main stage [69]. As a result, with second harmonic injection scheme delivering a 250-mW power while consuming 370 mW of power, an output power of 29 dBm

High-efficiency power amplifier design

75

PAE, % Class EM 80 Class E

60 40 20 0

0

5

10

15

20

25

τs/T, %

Figure 1.52 Efficiency versus switching time for Class-EM and Class-E power amplifiers

is1

S1

vs1

ZM

Main circuit

LC1

CS1

L1

TL1

iDC1

TL2 λ/4

λ/4

C1 jX1 Isolation circuit

iR Ropt

VDC1 jX2 L2 is2

S2

vs2

Auxiliary circuit

CS2

LC2

iinj

C2

iDC2

VDC2

Figure 1.53 Circuit schematic of Class-EM power amplifier with isolation circuit with a power gain of 14 dB and a peak PAE of 63% was obtained at 2.4 GHz using a 0.25-mm pHEMT technology. An analysis of the Class-EM power amplifier can be simplified and accurate explicit design equations for the load-network parameters can be derived by using an isolation circuit incorporated between the main and auxiliary circuits, thus resulting in a new configuration of the Class-EM power amplifier as shown in Figure 1.53 [70]. Here, the main and auxiliary circuits each consists of a shunt

76

Radio frequency and microwave power amplifiers, volume 2

capacitance (Cs1, Cs2), an RF choke (LC1, LC2), a series resonant circuit (L1C1 tuned at the fundamental f0, L2C2 tuned to 2f0), and a series reactance (X1, X2), respectively. The isolation circuit consists of a series quarterwave transmission line (TL1) and an open-circuit quarterwave stub (TL2), providing a short-circuited termination at fundamental and odd harmonics with the corresponding open-circuited termination due to TL1. Thus, the impedance ZM presented by the auxiliary circuit to the main circuit is sufficiently high with good isolation of the main circuit from auxiliary one at fundamental and odd harmonics. In this case, an analysis of the main and auxiliary circuits can be done separately.

1.7 High-efficiency broadband power amplifiers 1.7.1

Broadband Class E with shunt capacitance

The conventional design of a high-efficiency Class-E power amplifier requires a high loaded QL-factor of the series filter to satisfy the necessary harmonic impedance conditions at the device output and to provide sinusoidal current flowing to the load. However, if a sufficiently small value of the loaded quality factor QL is chosen, a high-efficiency broadband operation of the Class-E power amplifier can be realized by applying the reactance compensation technique. For example, a simple network consisting of a series resonant LC circuit tuned to the fundamental frequency, a parallel inductor, and a load resistor provides a constant load phase angle of 50
in a frequency bandwidth of about 50% around the center bandwidth frequency [71]. Usually, the bandwidth limitation in power amplifiers comes from the device low transition frequency fT and large output capacitance Cout. Therefore, silicon LDMOSFET technology has been the preferred choice for broadband applications up to 2 GHz. As an alternative, GaN HEMT technology enables high efficiency, large breakdown voltage, high power density, and significantly higher broadband performance due to higher transition frequency and smaller periphery, resulting in smaller input and output capacitances and less parasitics. It is very difficult to maintain efficiency at a high level over very wide frequency bandwidth. For a Class-E load network with shunt capacitance, a PAE above 50% was achieved within the frequency range from 1.9 to 2.4 GHz [72]. To increase high-efficiency frequency bandwidth, the broadband Class-E technique based on a reactance compensation principle with a combination of the series and shunt resonant circuits can be used [73]. To describe reactance compensation technique, let us consider the simplified equivalent load network with a shunt capacitor C, a series inductor L, a shunt L0C0 circuit tuned to the fundamental, and a load R, as shown in Figure 1.54. In order to maintain the load phase angle constant in a wide frequency range, the positive slope of the reactance provided by the L-type circuit should be cancelled by the negative slope of the reactance provided by the shunt L0C0 circuit. In this case, the loadnetwork admittance Ynet ¼ 1/Znet can be written as Ynet ¼ jwC þ

1 þ jw0 C0 R Rð1  jww0 LC0 Þ þ jwL

(1.174)

High-efficiency power amplifier design

77

L

Znet

C

L0

C0

R

Figure 1.54 Equivalent circuit of Class E with shunt capacitor and shunt filter

where   w20 (1.175) w ¼w 1 2 w pffiffiffiffiffiffiffiffiffiffi and w0 ¼ 1= L0 C0 is the resonant angular frequency. Here, for a nominal Class-E mode with shunt capacitance and shunt filter, the normalized series inductance L and shunt capacitance C are determined by (1.144) and (1.145), respectively. The frequency bandwidth with a constant load phase angle will be maximized if, at midband frequency w0:  dBnet ðwÞ  ¼0 (1.176) dw w¼w0 0

where the load-network reactive admittance (or susceptance) Bnet ¼ ImYnet is defined by Bnet ¼ wC þ

w0 C0 R2 ð1  jww0 LC0 Þ  wL R2 ð1  jww0 LC0 Þ2 þ ðwLÞ2

As a result, an additional equation can be derived as   w0 L 2 þ1 w0 L R 2w0 C0 R   w0 CR  ¼0  R w0 L 2 1 R

(1.177)

(1.178)

Finally, the shunt capacitance C0 and inductance L0 can be obtained from (1.178) by 1:0896 w0 R

(1.179)

L0 ¼ 1=w20 C0

(1.180)

C0 ¼

Figure 1.55(a) shows the example of a reactance compensation load network for Class-E power amplifier with shunt filter using lumped elements. In this case, the reactance of the circuit with shunt capacitor and series inductor varies similar to

78

Radio frequency and microwave power amplifiers, volume 2 2.7 nH

Znet

0.76 pF

25 Ω

1.7 pF

3.2 nH

(a) 85

46

80

42

75

38

70

34

65

30

60

26 1

55

22

50

18

45

14 1.8

(b)

Phase(Znet), degree

Re(Znet), Ohm

2

2.0

2.2

2.6 2.4 Frequency, GHz

2.8

3.0

3.2

Figure 1.55 Class-E reactance-compensation load network with lumped elements and its performance

that of the series resonant circuit with positive slope, whereas the required negative slope is provided by the parallel resonant circuit. Selection of the proper loadnetwork parameters according to (1.144) through (1.146) for Class-E mode with shunt filter together with (1.179) and (1.180) for optimum parameters of the shunt filter enables the magnitude of two slopes to be made identical, so as to achieve a constant total reactance the load-network impedance Znet over a wide frequency range. The simulation results at the fundamental frequency show that the real resistance ReZnet varies from 50 W at 1.9 GHz to 65 W at 3.0 GHz, as shown in Figure 1.55(b) by curve 1, whereas the load-network phase varies between 31.5
and 41
from 1.9 to 3.2 GHz (curve 2). Figure 1.56(a) shows the example of a reactance-compensation load network for a Class-E power amplifier with shunt filter using both lumped elements and transmission lines. In this case, the shunt filter is represented by the open-circuit and short-circuit stubs replacing the corresponding lumped capacitor and inductor, each having a characteristic impedance of 50 W and electrical length of 45
at 2.2 GHz. The series inductive reactance is created by lumped inductor that can be represented by the device bondwire and package lead and short transmission line. The simulation results at the fundamental frequency demonstrate that the

High-efficiency power amplifier design

79

50 Ω 45° 2.2 GHz 20 Ω

2.3 nH

20° @ 2.2 GHz Znet

50 Ω 45° 2.2 GHz

0.9 pF

25 Ω

(a) 120

50

Re(Znet), Ohm

40 2

80

30

60

20 1

40

Phase(Znet), degree

100

10

20

0 1.8

2.0

2.2

2.4 2.6 Frequency, GHz

2.8

3.0

3.2

(b)

Figure 1.56 Class-E reactance-compensation load network with lumped elements and transmission lines and its performance load-network resistance ReZnet and phase vary between 40 W and 57 W (curve 1) and between 25
and 41
(curve 2) from 1.8 to 3.2 GHz, as shown in Figure 1.56(b). Figure 1.57 shows the idealized simulation setup of a broadband 10-W Class-E power amplifier circuit with shunt filter designed to operate across the frequency band from 1.7 to 2.7 GHz and based on a GaN HEMT Cree CGH40010F device, where both the input matching circuit and load network are composed of ideal microstrip lines. The nominal Class-E load resistance calculated for Pout ¼ 10 W and Vdd ¼ 24 V from (1.146) is equal to about 25 W. In this case, the transmissionline broadband Class-E load network with shunt filter having a 25-W load is represented by the open-circuit and short-circuit stubs replacing the lumped capacitor and inductor, respectively, each having a characteristic impedance of 50 W and electrical length of 45
at 2.0 GHz. An additional series transmission line with 35 W characteristic impedance and of a quarter wavelength at high bandwidth frequency of 2.7 GHz is used to match an idealized 25-W load with a standard 50-W load. As a result, an output power of more than 41 dBm with a power gain of around 10 dB was achieved for an input power of 31 dBm, as shown in Figure 1.58(a).

80

Radio frequency and microwave power amplifiers, volume 2 –2.4 V

24 V

Z = 50 Ohm E = 45° F = 2.0 GHz

Z = 50 Ohm E = 45° F = 2.0 GHz

Z = 22 Ohm E = 42.5° F = 2.0 GHz

100 Ω 50 pF

Z = 75 Ohm E = 18° F = 2.0 GHz

Pin 50 Ω

Z = 10 Ohm E = 57° F = 2.0 GHz

Z = 35 Ohm E = 90° F = 2.7 GHz 50 pF

Z = 50 Ohm E = 18° F = 2.0 GHz

CGH40010F

Z = 50 Ohm E = 45° F = 2.0 GHz

50 Ω

25 Ω

45

17

43

15

41

13

39

11

37

9

35

7

33 1.7

1.9

2.1 2.3 Frequency, GHz

2.5

2.7

2.9

85

85

80

80

75

75

70

70

65

65

60

60

55

55

50

50 45

45 1.5 (b)

PAE, %

Drain efficiency, %

5 1.5

(a)

Power gain, dB

Output power, dBm

Figure 1.57 Schematic of broadband Class-E GaN HEMT power amplifier with shunt filter

1.7

1.9

2.1 2.3 Frequency, GHz

2.5

2.7

2.9

Figure 1.58 Output power, power gain, and efficiency versus frequency

High-efficiency power amplifier design

81

In this case, a drain efficiency over 73% and a PAE over 67% were achieved across the required frequency range from 1.7 to 2.7 GHz, as shown in Figure 1.58(b). Ideally, the requirements to the output matching network for a broadband Class-E power amplifier should include not only achieving the inductive fundamental-frequency impedance across the desired bandwidth, but also it is necessary to provide high reactance at harmonics. In this case, to provide an impedance matching with high transformation ratio and satisfy Class-E requirements over octave bandwidth with minimum in-band ripple, at least three stages for the low-pass ladder-type matching network are needed. Here, the series inductor as a first matching element can provide high-impedance condition at harmonics and the device output capacitance should provide the required capacitive harmonic reactances. By using a three-stage six-order low-pass filter-matching load network in a GaN HEMT Class-E power amplifier where the series inductors are replaced by the short-length high-impedance transmission-line sections and the shunt capacitors are replaced by the open-circuit low-impedance stubs, a drain efficiency of 63%–89% with an output power of 10 to 20 W and a power gain of 10–13 dB was measured in a frequency bandwidth from 0.9 to 2.2 GHz at a supply voltage of 26 V [74]. Generally, by providing an open-circuit termination for the second- and thirdharmonic components, the collector efficiency of a Class-E power amplifier at high microwave frequencies can be increased by 10% [75]. In this case, the secondharmonic termination has the most impact on the collector efficiency, while effect of an open-circuit termination for the fourth harmonic is negligible. Moreover, the variation of the second-harmonic load reflection coefficient by 10% in magnitude from 1 to 0.9 and 20
in phase angle results in an insignificant efficiency variation within 1% only. Figure 1.59(a) shows the circuit schematic of a monolithic broadband Class-E power amplifier with a chip size of 2  2.2 mm2. The load network is a compromise solution between having a low insertion loss and meeting the necessary requirements for the optimum Class-E operation with nonzero voltage and voltage-derivative switching conditions [76]. This is accomplished by using two open-circuit stubs in conjunction with a shunt capacitor, where the first open-circuit stub in combination with the series transmission line presents broadband high-impedance terminations for the second harmonics within 18–22 GHz, while the combination of the second open-circuit stub and the shunt capacitor presents broadband low impedances at the third harmonics within 27–33 GHz and also transforms the optimum load impedances at the fundamental frequencies. The simulated loading conditions presented to the output of the device at the fundamental (inductive impedance), second (high impedance), and third harmonic (low impedance) frequencies are shown in Figure 1.59(b), which are proved to be adequate for broadband Class-E power amplifiers. As a result, using an indium phosphide (InP) double HBT (DHBT) technology, a PAE of 49%–65% with an output power of 18–22 dBm was achieved over the frequency bandwidth from 9 to 11 GHz [6]. Based on an InP DHBT technology, a single-stage broadband X-band Class-E power amplifier can also achieve a PAE of 45%–60% with an output power of 19–21.5 dBm and a power gain of 9–11.5 dB over a 34% bandwidth, from 8.2 to 11.6 GHz [77].

82

Radio frequency and microwave power amplifiers, volume 2

Vb

1.5 μm × 30 μm × 4 Pout

Pin Znet

(a) Znet(ω0) Znet(2ω0) Znet(3ω0)

(b)

Figure 1.59 Broadband X-band In DHBT Class-E power amplifier and impedance conditions

1.7.2

Broadband parallel-circuit Class E

The reactance compensation technique can be directly applied to the switchingmode parallel-circuit Class-E power amplifier because its load-network configuration represents the same structure with shunt and series resonant circuits, as shown in Figure 1.60(a) [61,78]. Consider the load-network admittance Ynet corresponding to a single-reactance compensation circuit shown in Figure 1.60(a), which can be written as   1 1 (1.181) þ Ynet ¼ jwC þ jwL R þ jw0 L0 where   w20 w ¼w 1 2 w pffiffiffiffiffiffiffiffiffiffi and w0 ¼ 1= L0 C0 is the resonant angular frequency. 0

(1.182)

High-efficiency power amplifier design C0

L0

Znet

L

C

83

R

(a) L0

C0

L

C

L1

C1

R

(b) ϕ, degree

40 1

2 35

30 100

(c)

120

140

160

180

f, MHz

Figure 1.60 Single- and double-reactance compensation circuits

By maximizing the frequency bandwidth according to (1.156), an additional equation can be written as Cþ

1 2L0  2 ¼0 2 w L R

(1.183)

based on which the values of the series components L0 and C0 can respectively be obtained through the values of the shunt components L and C. As a result, by substituting (1.116) and (1.117) into (1.183), the series inductance L0 and capacitance C0 can be calculated for a specified load resistance R at a resonant angular frequency w0 by L0 ¼ 1:026 C0 ¼

R w0

1 : w20 L0

(1.184) (1.185)

84

Radio frequency and microwave power amplifiers, volume 2

Wider frequency bandwidth with high-efficiency performance can be achieved using a double-reactance compensation circuit shown in Figure 1.60(b), where L0C0 and L1C1 are the series and parallel resonant circuits, respectively [79]. In this case, similarly to the broadband design in a Class-E mode with shunt capacitance using a double-reactance compensation, the parameters of the series and shunt resonant circuits for the broadband design in a parallel-circuit Class-E mode with the corresponding loaded quality factors Q0 ¼ w0L0/R and Q1 ¼ w0C1R are close to unity. Such a load network can be considered as a broadband matching-forming circuit which provides simultaneously the Class-E switching conditions and matching with a standard 50-W load over wide frequency bandwidth [80]. The circuit simulations for these two types of reactance compensation load networks were performed at a center bandwidth frequency f0 ¼ 150 MHz for a standard load resistance R ¼ 50 W. Figure 1.60(c) shows the frequency dependences of the load-network phase angle f for the single-reactance (curve 1) and double-reactance (curve 2) compensation circuits, demonstrating their very broadband operation capability. Using just a single-reactance load network yields a significant widening of the operating frequency bandwidth with a minimum deviation of the magnitude and phase of the load-network impedance. A doublereactance compensation load network obtains a maximum deviation from the optimum value of about 34
by only 3
in a frequency range from 120 to 180 MHz. To achieve high-efficiency broadband operation mode with a high-power gain in VHF frequency band, it is best to design the power amplifier based on silicon LDMOSFET devices. In this case, it is easy to provide a very broadband input matching using lossy-matching circuit, especially at operating frequencies about 10 times lower than the device transition frequency fT. Figure 1.61(a) shows the circuit schematic of an LDMOSFET power amplifier designed to operate in a 2:1 frequency bandwidth from 100 to 200 MHz using a double-reactance compensation load network [73]. The input lossy-matching circuit includes a simple L-transformer connected in parallel with a series circuit consisting of an inductor of 20 nH and a resistor of 50 W. This provides a minimum input return loss at 200 MHz of about 15 dB and an input voltage standing wave ratio (VSWR) less than 1.4 over the entire frequency bandwidth. From Figure 1.61(b), it follows that, for such an octave-band VHF Class-E power amplifier with an input power of 1 W using a 1.25-mm LDMOSFET device with a total gate width of 28  1.44 mm, a power gain of 10 dB with deviation of only 0.5 dB (curve 2) can be achieved with a drain efficiency of about 70% and higher (curve 1). A drain efficiency of 74% with an output power of 8 W across the frequency range from 136 to 174 MHz with a power flatness of 0.7 dB was measured for a parallel-circuit Class-E LDMOSFET power amplifier with a low supply voltage of 7.2 V [81]. A power-added efficiency can be increased to 80% and more in a frequency range of 140–180 MHz with an output power of 34.4  1.5 dBm using a GaN HEMT device [82]. Figure 1.62(a) shows the circuit schematic of a broadband high-efficiency microstrip LDMOSFET power amplifier with an output power of around 20 W and a power gain of more than 12 dB in a frequency range from 225 to 400 MHz at a

High-efficiency power amplifier design

10 nF

85

28 V

1.5 kΩ

300 Ω 50 Ω 10 nF 20 nH 1 nF

w = 28 × 1.44 mm l = 1.25 μm

62 nH 64 nH 20 pF

50 nH

Pout Pin

10 pF

10 pF

10 pF

110 nH

(a) Efficiency, % 76

Gain, dB 1 10.5

74 2

72

10.0

70 68 100 (b)

9.5

120

140

160

180

f, MHz

Figure 1.61 Simulated broadband Class-E LDMOSFET power amplifier

supply voltage of 28 V. Here, to approximate the parallel-circuit Class-E mode in a wide frequency range, the load network was designed to realize a single-reactance compensation technique using a parallel short-length transmission line in conjunction with a single L-type transmission-line transformer, since a ratio between the device equivalent output resistance required for an optimum Class-E operation and the standard load of 50 W is not significant. The input matching circuit includes two lowpass L-type matching sections to compensate for the device input capacitance over the entire frequency range. A lossy parallel resistance of 75 W is necessary to simplify the matching procedure and improve the input return loss. As a first step, each matching network structure is calculated at the center-band frequency based on the technical requirements and device equivalent circuit parameters. Then, to optimize the power amplifier performance over the entire frequency band, the simplest and fastest way is to apply an optimization procedure using computer simulators to

86

Radio frequency and microwave power amplifiers, volume 2 Vg

30 pF

50 Ω , 21°

Pin = 1 W 50 pF

28 V

1 nF

1 nF

10 μF

75 Ω

w = 28 × 1.44 mm l = 1.25 μm

50 Ω 30°

50 Ω , 27°

50 Ω , 50°

80 pF

33 pF Pout

8 pF

(a) Pout, dBm

Efficiency, %

45.0

100

42.5

75

40.0

50

225 250

275

300

325

350

375 f, MHz

(b)

Figure 1.62 Broadband high-efficiency microstrip LDMOSFET power amplifier satisfy certain criteria. For such a broadband power amplifier, the minimum output power ripple and input return loss with maximum power gain and efficiency can be chosen as the criteria. Generally, by applying a nonlinear broadband optimization technique and setting the ranges of electrical length of the transmission lines between 0
and 90
and parallel capacitances from 0 to 100 pF, the parameters of the input matching circuit and output load network can be optimized. However, to speed up this procedure and eliminate potential problems with convergence using software simulators, it is best to optimize circuit parameters separately for the input and output circuits. In this case, the input matching circuit is loaded by the device equivalent input series RC circuit, consisting of its gate resistance and gate-source capacitance. The load network must include at its input the device equivalent output shunt RC circuit consisting of an optimum Class-E load resistance required for a specified output power and supply voltage and drainsource capacitance. In this case, it is sufficient to use a linear optimization process, which will take only a few minutes to complete the circuit design procedure. Finally, the resulting optimized values are incorporated into the overall power amplifier circuit for each element and final optimization is performed using a nonlinear active device model. The optimization process is finalized by choosing the nominal level of input power with optimizing elements in narrower ranges of their values of about 10%–20% for most critical elements. For practical

High-efficiency power amplifier design

87

convenience, it is better to choose the characteristic impedances of all transmission lines of 50 W if possible. Figure 1.62(b) shows the simulated broadband high-efficiency power amplifier performance achieving an output power of 42.5–44.5 dBm, a power gain of 13.51 dB, and a drain efficiency of 64  10% in a frequency bandwidth from 225 to 400 MHz. The circuit schematic of a broadband two-stage InGaP/GaAs HBT power amplifier intended to operate in the WCDMA handset transmitters is shown in Figure 1.63 [61,78]. The MMIC part of this power amplifier contains the transistors with emitter areas of the first and second stage as large as 540 mm2 and 3,600 mm2, respectively, input matching circuit, interstage matching circuit, and bias circuits on a die with overall size of less than 1 mm2. The MMIC packaged in a 3  3 mm2 package was mounted on a FR4 substrate which contains the output matching circuit and microstrip lines. Standard ceramic chip capacitors were used in the output matching circuit, and no further additional tuning was necessary. In this case, a very short microstrip line operating as a dc-feed inductance is required to approximate parallel-circuit optimum Class-E switching conditions. Figure 1.64(a) shows that the small-signal gain varies within 22.5  0.5 dB and the input return loss is greater than 13 dB in a frequency range from 1.6 GHz to about 2.1 GHz, thus confirming the broadband operation of the power amplifier. Without any tuning of the output matching circuit, a saturated output power greater than 30 dBm and a PAE greater than 50% were obtained across the bandwidth. Figure 1.64(b) demonstrate the single-tone measurements at the respective centerband frequencies 1.75 GHz and 1.88 GHz. Using high-Q capacitors in output matching circuit can improve the power-added efficiency by about 8%, resulting in a PAE close to 60%. At the same time, the power amplifier provides high-linearity 3.5 V

Z0 = 50 Ω θ = 15°

2.7 V

Bias circuit

Bias circuit Pout

Pin

MMIC

Figure 1.63 Circuit schematic of parallel-circuit GaAs HBT Class-E MMIC power amplifier

0

25

–5

20

–10

15

–15

10

–20

5

S21 (dB)

Radio frequency and microwave power amplifiers, volume 2

S11 (dB)

88

0

–25 1.6

1.7

1.8

(a)

1.9

2

2.1

Freq (GHz) 25

55 50 45

20

35

15

30

DCS 1800 efficiency PCS 1900 efficiency DCS 1800 gain PCS 1900 gain

25 20

10

Gain (dB)

Efficiency (%)

40

15 5

10 5

0

0 0 (b)

5

10

15 Pout (dBm)

20

25

30

Figure 1.64 Input return loss, gain, and efficiency versus frequency performance in a handset WCDMA band (1920–1980 MHz) at a 3.5-dB backoff output power of 27 dBm with a power gain of 22.6 dB and a sufficiently high efficiency. The measured PAE reached value of 38.3% at 1.95 GHz with an ACLR1 of –37 dBc at a 5-MHz offset and an ACLR2 of –56 dBc at a 10-MHz offset. Figure 1.65 shows the circuit schematic of a two-stage broadband Class-E power amplifier implemented in a 0.5-mm pHEMT process with a chip size of 2  2 mm2, which is intended to operate in a frequency range from 1.5 to 3.8 GHz with a PAE better than 62% and an output power of greater than 27 dBm at Vdd ¼ 6 V [83]. In this case, to provide high operation efficiency in a wide frequency range, the Class-E load network with reactance compensation technique followed by the low-pass matching network is used. The driver stage is designed to operate

High-efficiency power amplifier design

89

Vdd Vdd 32 pF

Lp 5 nH

20 Ω

32 pF

Cp Ls 1.7 nH 4 pF

2.7 nH

20 Ω

1.4 nH Pout

Cp 0.7 pF

1.67 pF Pin

Matching network

1.67 pF

3.1 nH 1.4 nH

32 pF

Vg1

Vg2

32 pF 20 Ω

20 Ω

Figure 1.65 Circuit schematic of broadband Class-E pHEMT power amplifier Vg

Vdd

l/4

Rstab 300 Ω 0.45 nH

2.4 nH L0 7.5 nH

47 Ω

C0 0.59 pF Pout

Cds

Pin 3.3 pF 1.4 nH

15 pF

0.42 nH 2.6 pF 2nd-harmonic trap

Figure 1.66 Circuit schematic of broadband Class-E GaN HEMT power amplifier in a Class-AB mode with a sufficiently small quiescent current for high gain and high efficiency when both input and interstage matching circuits are conjugately matched. Figure 1.66 shows the circuit schematic of a compact single-stage broadband Class-E GaN HEMT power amplifier, where the load network is based on reactance compensation technique with a parallel circuit followed by the low-Q series resonant circuit [84]. The use of a finite dc-feed inductance has advantages in terms of the output power and maximum frequency of operation and results in a higher load

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Radio frequency and microwave power amplifiers, volume 2

resistance than in the classical Class-E configuration with infinite RF choke. To shape the gate voltage waveform, the second-harmonic signal is short-circuited at the gate by the series resonant circuit representing a second-harmonic trap. The high- and low-pass matching sections form a bandpass input matching circuit, where a 300-W parallel resistor together with a 47-W bias resistor provide an unconditional stability of the power amplifier both at low and high frequencies. The actual size of a broadband Class-E power amplifier with input matching circuit and load network implemented in a two-layer Rogers substrate with a dielectric permittivity of 3.5 is only 1.1  1.6 cm2. As a result, a drain efficiency above 74% and an output power greater than 7 W with an input power of 600 mW at Vdd ¼ 40 V can be achieved across the bandwidth of 2.0–2.5 GHz. Wider frequency bandwidth of 2.1–2.7 GHz with a drain efficiency exceeding 63% and an output power above 9.3 W can be provided without input second-harmonic trap by retuning the finite dc-feed inductance.

1.7.3

High-efficiency mixed-mode broadband power amplifier

High-efficiency ultra-broadband power amplifiers are usually designed using GaN HEMT technology and different load-network techniques. Depending on the operating frequency bandwidths and implementation capabilities, different Class-C, Class-E, or Class-F modes based upon a finite number of harmonics can be used to achieve high efficiency of the power amplifier operation. In this case, lower drain voltage peak factors can be obtained by using the conventional Class-F or inverse Class-F lumped or transmission-line load networks. When operating in a Class-F mode with the second- and third-harmonic control, the maximum efficiency greater than 81% can be achieved [85]. A drain efficiency of greater than 70% was measured over the frequency bandwidth from 1.45 to 2.45 GHz with output power of 40.4–42.2 dBm using a 10-W Cree GaN HEMT device [86]. By combining Class-F and inverse Class-F modes with optimized dc supply voltages, a wide frequency range from 1.3 to 3.3 GHz was covered achieving the drain efficiencies of 60%–84% with output power of 10–11 W [87]. In contrast to the conventional Class-C power amplifiers with a parallel resonant circuit resulting in a sinusoidal collector voltage waveform, the mixedmode Class-C configuration with a series resonant circuit was widely adopted for most VHF and UHF transistor power amplifiers, which could provide better efficiency performance [88,89]. By simply optimizing the fundamental-frequency and second-harmonic impedances across the frequency bandwidth from 525 to 1,325 MHz, the drain efficiency over 70% and output power over 39 dBm were achieved [90]. Much broader frequency bandwidths can be achieved with resistive harmonic loading and lossy input matching. For example, a broadband lossy matched GaN HEMT MMIC power amplifier achieved the drain efficiency of 44.9%–63.6% and output power of 9–13.6 W over the frequency bandwidth of 0.5–2.5 GHz [91]. A decade bandwidth of 0.4–4.1 GHz with a drain efficiency of 40%–62% was achieved by a GaN HEMT power amplifier with a

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91

simplified broadband load network delivering the output power greater than 40 dBm [92]. Figure 1.67 shows the reactance compensation load network with a low-pass matching section which includes the third-harmonic resonant circuit to approximate Class-F mode at higher bandwidth frequencies to increase efficiency at these frequencies. The third-harmonic resonant circuit Lm3Cm3 provides a capacitive reactance at the fundamental frequency and an open-circuit condition seen by the device output at the third harmonic due to parallel resonant circuit formed by the shunt capacitor Cp and equivalent inductor composed of the shunt inductor Lp and series LsCsLm circuit having an inductive reactance at the third harmonic. The reactive part of the input impedance ImZnet should be set to infinite at the third harmonic to approximate Class-F mode at an operating frequency: 1 1 w0 ¼ pffiffiffiffiffiffiffiffiffiffi ¼ pffiffiffiffiffiffiffiffiffi Ls Cs Lp Cp

(1.186)

where the third-harmonic resonant circuit Lm3Cm3 is tuned to zero, thus resulting in w 0 Cp 

Lp þ Lm þ 89 Ls  ¼0 w0 Lp Lm þ 89 Ls

(1.187)

For the simplified case of equal loaded quality factors when Q ¼ w0CpR ¼ w0Ls/R ¼ w0Lm/R, from (1.187) it follows that Q ffi 0.25, the low value of which allows the high efficiency across very wide frequency bandwidth to be achieved using mixed-mode operation. Figure 1.68(a) shows the simulated circuit schematic of a high-efficiency ultrabroadband GaN HEMT power amplifier using a 10-W Cree CGH40010F device with an output shunt capacitance of 1.3 pF at Vdd ¼ 28 V [93]. The input lossy matching circuit includes a parallel RC circuit connected in series to the gate to improve stability at low frequencies and power gain at higher bandwidth frequencies, as well as a 3:1 voltage ferrite-based transformer and a shunt RL circuit to provide broadband input matching with minimum return loss. Here, the series resonant circuit is tuned to 1.0 GHz, whereas the third-harmonic circuit is optimized to 6.5 GHz (referring to higher fundamental frequency). As a result, a drain efficiency of 70  5% with an output power of 40.8  1.2 dBm shown in Ls

Cs

Lm Cm3

Znet

Cp

Lp

R

Lm3

RL

Figure 1.67 Broadband matching network with third-harmonic trap

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Radio frequency and microwave power amplifiers, volume 2 −2.4 V

28 V

20 nH

70 Ω

15 nH 20 Ω

10 nH 3:1

1 nF

1.0 GHz 1.6 nH 16 pF

1.6 nH

5Ω

1 pF

CGH40010F

Pin 50 Ω

50 Ω

6.5 GHz 0.6 nH

10 pF

(a) Efficiency 80

70

70

60

60

50

50

40

40

30

30 20

20 0.3 (b)

Output power (dBm)

Efficiency (%)

Output power 80

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

Frequency (GHz)

Figure 1.68 Simulated (a) circuit schematic and (b) performance of broadband mixed-mode GaN HEMT power amplifier Figure 1.68(b) and a power gain of 11.3  1.2 dB was achieved across the frequency bandwidth from 500 MHz to 2.5 GHz.

References [1] Gesellschaft fur Drahtlose Telegraphie. “An arrangement for minimising loss in the production of oscillations by means of vacuum tubes.” German Patent 304360, September 1919 (filed December 1917). [2] Prince D.C. “Vacuum tubes as power oscillators, part III.” Proc. IRE, 1923, vol. 11(9), pp. 527–550. [3] Zenneck J., and Rukop H. Lehrbuch der Drahtlosen Telegraphie. Stuttgart: Ferdinand Enke, 1925. [4] Fomichev I.N. “A new method to increase efficiency of the radio broadcasting station (in Russian).” Elektrosvyaz, 1938(6), pp. 58–66.

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[5] Sarbacher R.I. “Power-tube performance in Class C amplifiers and frequency multipliers as influenced by harmonic voltage.” Proc. IRE, 1943, vol. 31(11), pp. 607–625. [6] Round H.J. “Wireless telegraph and telephone transmission.” U.S. Patent 1,564,627, December 1925. [7] Raab F.H. “An introduction to Class-F power amplifiers.” RF Design, 1996, vol. 19(5), pp. 79–84. [8] Raab F.H. “Class-F power amplifiers with maximally flat waveforms.” IEEE Trans. Microw. Theory Tech., 1997, vol. 45(11), pp. 2007–2012. [9] Raab F.H. “FET power amplifier boosts transmitter efficiency.” Electronics, 1976, vol. 49(6), pp. 122–126. [10] Grebennikov A. “Load network design technique for Class F and inverse Class F power amplifiers.” High Frequency Electronics, 2011, vol. 10(5), pp. 58–76. [11] Borisov V.A., and Voronovich V.V. “Analysis of switching transistor amplifier with parallel forming transmission line (in Russian).” Radiotekhnika i Elektronika, 1986, vol. 31(8), pp. 1590–1597. [12] Grebennikov A.V. “Circuit design technique for high efficiency Class F amplifiers.” IEEE MTT-S International Microwave Symposium Digest; Boston, MA, June 2000, pp. 771–774. [13] Grebennikov A.V. “Effective circuit design techniques to increase MOSFET power amplifier efficiency.” Microw. J., 2000, vol. 43(7), pp. 64–72. [14] Trask C. “Class-F amplifier loading networks: a unified design approach.” IEEE MTT-S International Microwave Symposium Digest; Anaheim, CA, June 1999, pp. 351–354. [15] Schmelzer D., and Long S.I. “A GaN HEMT Class F amplifier at 2 GHz with >80% PAE.” IEEE J. Solid-State Circuits, 2007, vol. 42(10), pp. 2130–2136. [16] Kolesnikov A.I. “A new method to improve efficiency and to increase power of the transmitter (in Russian).” Master Svyazi, 1940(6), pp. 27–41. [17] Glazman E.S., Kalinin L.B., and Mikhailov Y.I. “Improving VHF transmitter efficiency by using the biharmonic mode.” Telecommun. Radio Eng., Part 1, 1975, vol. 30(7), pp. 46–51. [18] Tyler V.J. “A new high-efficiency high-power amplifier.” Marconi Rev., 1958, vol. 21(fall), pp. 96–109. [19] Kazimierczuk M.K. “A new concept of Class F tuned power amplifier.” Proceedings of 27th Midwest Circuits and Systems Symposium; Morgantown, WV, June 1984, pp. 425–428. [20] Heymann P., Doerner R., and Rudolph M. “Harmonic tuning of power transistors by active load-pull measurement.” Microwave J., 2000, vol. 43(6), pp. 22–37. [21] Wei C.J., DiCarlo P., Tkachenko Y.A., McMorrow R., and Bartle D. “Analysis and experimental waveform study on inverse Class-F mode of microwave power FETs.” IEEE MTT-S International Microwave Symposium Digest; Boston, MA, June 2000, pp. 525–528.

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Grebennikov A. “High-efficiency transmission-line inverse Class F power amplifiers for 2-GHz WCDMA systems.” Int. J. RF Microw. Comput.-Aided Eng., 2011, vol. 21(7), pp. 446–456. Jarndal A., Aflaki P, Negra R., Kouki A.K., and Ghannouchi F. “Largesignal modeling methodology for GaN HEMTs for RF switching-mode power amplifiers design.” Int. J. RF Microw. Comput.-Aided Eng., 2011, vol. 21(1), pp. 45–51. Grebennikov A., and Raab F.H. “A history of switching-mode Class-E techniques.” IEEE Microw. Mag., 2018, vol. 19(5), pp. 26–41. Khmelnitsky E.P. Operation of Vacuum-Tube Generator on Detuned Resonant Circuit (in Russian). Moskva: Svyazizdat, 1962. Ewing G.D. “High-efficiency radio-frequency power amplifiers.” PhD Dissertation, Oregon State University, June 1964. Kozyrev V.B. “Single-ended tuned switching power amplifier with filtering resonant circuit (in Russian).” Poluprovodnikovye Pribory v Tekhnike Svyazi, 1971(6), pp. 152–166. Sokal N.O., and Sokal A.D. “Class E  a new class of high-efficiency tuned single-ended switching power amplifiers.” IEEE J. Solid-State Circuits, 1975, vol. 10(3), pp. 168–176. Sokal N.O., and Sokal A.D. “High-efficiency tuned switching power amplifier.” U.S. Patent 3,919,656, November 1975. Sokal N.O. “Class E high-efficiency power amplifiers, from HF to microwave.” IEEE MTT-S International Microwave Symposium Digest; Baltimore, MD, June 1998, vol. 2, pp. 1109–1112. Raab F.H. “Idealized operation of the Class E tuned power amplifier.” IEEE Trans. Circuits Syst., 1977, vol. 24(12), pp. 725–735. Molnar B. “Basic limitations on waveforms achievable in single-ended switching-mode tuned (Class E) power amplifiers.” IEEE J. Solid-State Circuits, 1984, vol. 19(1), pp. 144–146. Kazimierczuk M., and Puczko K. “Exact analysis of Class E tuned power amplifier at any Q and switch duty cycle.” IEEE Trans. Circuits Syst., 1987, vol. 34(2), pp. 149–158. Raab F.H., and Sokal N.O. “Transistor power losses in the Class E tuned power amplifier.” IEEE J. Solid-State Circuits, 1978, vol.13(6), pp. 912–914. Bruevich A.N. “About optimum parameters of switching-mode tuned power amplifier with filtering resonant circuit (in Russian).” Poluprovodnikovaya Elektronika v Tekhnike Svyazi, 1977(18), pp. 43–48. Grebennikov A., Sokal N.O., and Franco M.J. Switchmode RF and Microwave Power Amplifiers. Waltham, MA: Academic Press, 2012. Kazimierczuk M. “Effect of the collector current fall time on the Class E tuned power amplifier.” IEEE J. Solid-State Circuits, 1983, vol. 18(2), pp. 181–193. Blanchard J.A., and Yuan J.S. “Effect of collector current exponential decay on power efficiency for Class E tuned power amplifier.” IEEE Trans. Circuits Syst.  I: Fundamental Theory Appl., 1994, vol. 41(1), pp. 69–72.

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[39] Chudobiak M.J. “The use of parasitic nonlinear capacitors in Class E amplifiers.” IEEE Trans. Circuits Syst.  I: Fundamental Theory Appl., 1994, vol. 41(12), pp. 941–944. [40] Alinikula P., Choi K., and Long S.I. “Design of Class E power amplifier with nonlinear parasitic output capacitance.” IEEE Trans. Circuits Syst.  II: Analog Digital Signal Process, 1999, vol. 46(2), pp. 114–119. [41] Suetsugu T., and Kazimierczuk M.K. “Analysis and design of Class E amplifier with shunt capacitance composed of nonlinear and linear capacitances.” IEEE Trans. Circuits Syst.  I: Regul. Pap., 2004, vol. 51(7), pp. 1261–1268. [42] Mader T.B., and Popovic Z.B. “The transmission-line high-efficiency Class-E amplifier.” IEEE Microw. Guided Wave Lett., 1995, vol. 5(9), pp. 290–292. [43] Mader T.B., Bryerton E.W., Marcovic M., Forman M., and Popovic Z. “Switched-mode high-efficiency microwave power amplifiers in a freespace power-combiner array.” IEEE Trans. Microw. Theory Tech., 1998, vol. 46(10), pp. 1391–1398. [44] Ortega-Gonzalez F.J., Jimenez-Martin J.L., Asensio-Lopez A., and TorregrosaPenalva G. “High-efficiency load-pull harmonic controlled Class-E power amplifier.” IEEE Microw. Guided Wave Lett., 1998, vol. 8(10), pp. 348–350. [45] Frey R. “500 W, Class E 27.12 MHz amplifier using a single plastic MOSFET.” IEEE MTT-S International Microwave Symposium Digest; Anaheim, CA, June 1999, pp. 359–362. [46] Franco M., and Katz A. “Class-E silicon carbide VHF power amplifier.” IEEE MTT-S International Microwave Symposium Digest; Honolul, HI, June 2007, pp. 19–22. [47] Negra R., Ghannouchi F.M., and Baechtold W. “Study and design optimization of multiharmonic transmission-line load networks for Class-E and Class-F K-band MMIC power amplifiers.” IEEE Trans. Microw. Theory Tech., 2007, vol. 55(6), pp. 1390–1397. [48] Zulinski R.E., and Steadman J.W. “Class E power amplifiers and frequency multipliers with finite dc-feed inductance.” IEEE Trans. Circuits Syst., 1987, vol. 34(9), pp. 1074–1087. [49] Avratoglou C.P., Voulgaris N.C., and Ioannidou F.I. “Analysis and design of a generalized Class E tuned power amplifier.” IEEE Trans. Circuits Syst., 1989, vol. 36(8), pp. 1068–1079. [50] Smith G.H., and Zulinski R.E. “An exact analysis of Class E power amplifiers with finite dc-feed inductance at any output Q.” IEEE Trans. Circuits Syst., 1990, vol. 37(4), pp. 530–534. [51] Li C.H., and Yam Y.O. “Maximum frequency and optimum performance of Class E power amplifiers.” IEE Proc. Circuits Devices Syst., 1994, vol. 141(3), pp. 174–184. [52] Ho C.K., Wong H., and Ma S.W. “Approximation of non-zero transistor on resistance in Class-E amplifiers.” Proceedings of 5th IEEE International Caracas Conference on Devices, Circuits and Systems; Punta Cana, Dominican Republic, November 2004, pp. 90–93.

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Grebennikov A. “Load network design techniques for Class E RF and microwave amplifiers.” High Frequency Electronics, 2004, vol. 3(7), pp. 18–32. Grebennikov A., and Sokal N.O. Switchmode RF Power Amplifiers, New York: Newnes, 2007. Acar M., Annema A.J., and Nauta B. “Analytical design equations for ClassE power amplifiers.” IEEE Trans. Circuits Syst.  I: Regul. Pap., 2007, vol. 54(12), pp. 2706–2717. Grebennikov A. “Class E high-efficiency power amplifiers: historical aspect and future prospect.” Appl. Microw. Wireless, 2002, vol. 14(7), pp. 64–71, vol. 14(8), pp. 64–72. Grebennikov A.V., and Jaeger H. “Class E with parallel circuit – a new challenge for high-efficiency RF and microwave power amplifiers.” IEEE MTT-S International Microwave Symposium Digest; Seattle, WA, June 2002, vol. 3, pp. 1627–1630. Grebennikov A. “Switched-mode RF and microwave parallel-circuit Class E power amplifiers.” Int. J. RF Microw. Comput.-Aided Eng., 2004, vol. 14(1), pp. 21–35. Iwadare M., Mori S., and Ikeda K. “Even harmonic resonant Class E tuned power amplifier without RF choke.” Electron. Commun. Jpn., 1996, vol. 79(1), pp. 23–30. Grebennikov A.V., and Jaeger H. “High efficiency transmission line tuned power amplifier.” U.S. Patent 6,552,610, April 2003. Jaeger H., Grebennikov A.V., Heaney E.P., and Weigel R. “Broadband highefficiency monolithic InGaP/GaAs HBT power amplifiers for 3G handset applications.” IEEE MTT-S International Microwave Symposium Digest; Seattle, WA, June 2002, vol. 2, pp. 1035–1038. Xu Y., Zhu X., and You C. “Analysis and design of Class-E power amplifier using equivalent LDMOS model with drift region effect.” Microw. Opt. Technol. Lett., 2010, vol. 52(8), pp. 1836–1842. Grebennikov A. “High-efficiency Class-E power amplifier with shunt capacitance and shunt filter.” IEEE Trans. Circuits and Systems  I: Regul. Pap., 2016, vol. 63(1), pp. 12–22. Makarov D., Rassokhina Y., Krizhanovski V., and Grebennikov A. “Transmission-line load network design technique for Class-E power amplifiers.” High Freq. Electron., 2017, vol. 16(10), pp. 22–35. Thian M., and Fusco V. “Idealised operation of zero-voltage-switching series L/parallel-tuned Class-E power amplifier.” IET Circuits Devices Syst., 2008, vol. 2(3), pp. 337–346. Telegdy A., Molnar B., and Sokal N.O. “Class-EM switching-mode tuned power amplifier  high efficiency with slow-switching transistor.” IEEE Trans. Microw. Theory Tech., 2003, vol. 51(6), pp. 1662–1676. Miyahara R., Sekiya H., and Kazimierczuk M.K. “Novel design procedure for Class-EM power amplifiers.” IEEE Trans. Microw. Theory Tech., 2010, vol. 58(12), pp. 3607–3616.

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[68] Wei X., Nagashima N., R. Miyahara, Kazimierczuk M.K., Sekiya H., and Suetsugu T. “Analysis and design of Class-EM power amplifier.” IEEE Trans. Circuits Syst., 2014, vol. 61(4), pp. 976–986. [69] Ershadi A., and Medi A. “Investigation of integrated smooth transistor’s switching transition power amplifier  2.4-GHz realization of Class-EM.” IEEE Trans. Microw. Theory Tech., 2017, vol. 65(8), pp. 3046–3055. [70] Safari Mugisho M., and Thian M. “Closed-form design equations foe ClassEM power amplifier with isolation circuit.” Proceedings of IEEE International Workshop on Integrated Nonlinear Microwave and Millimeter-Wave Circuits; Brive la Gaillarde, France, July 2018, pp. 1–3. [71] Everard J.K.A., and King A.J. “Broadband power efficient Class E amplifiers with a non-linear CAD model of the active MOS device.” J. IERE, 1987, vol. 57(2), pp. 52–58. [72] Xu H., Gao S., Heikman S., Long S.I., Mishra U.K., and York R.A. “A highefficiency Class-E GaN HEMT power amplifier at 1.9 GHz.” IEEE Microw. Wireless Comp. Lett., 2006, vol. 16(1), pp. 22–24. [73] Grebennikov A. RF and Microwave Power Amplifier Design. New York: McGraw-Hill, 2015. [74] Chen K., and Peroulis D. “Design of highly efficient broadband Class-E power amplifier using synthesized low-pass matching networks.” IEEE Trans. Microw. Theory Tech., 2011, vol. 59(11), pp. 3162–3173. [75] Quach T.K., Watson P.M., Okamura W., et al. “Ultra-high efficiency power amplifier for space radar applications.” IEEE J. Solid-State Circuits, 2002, vol. 37(9), pp. 1126–1134. [76] Watson P., Neidhard R., Kehias L., et al. “Ultra-high efficiency operation based on an alternative Class-E mode.” 22nd Annual IEEE Gallium Arsenide Integrated Circuits Symposium Technical Digest; Seattle, WA, November 2000, pp. 53–56. [77] Watson P., Quach T., Axtel H., et al. “An indium phosphide X-Band Class-E power MMIC with 40% bandwidth.” IEEE Compound Semiconductor Integrated Circuit Symposium Digest; Palm Springs, CA, November 2005, pp. 220–223. [78] Jaeger H., Grebennikov A.V., Heaney E.P., and Weigel R. “Broadband highefficiency monolithic InGaP/GaAs HBT power amplifiers for wireless applications.” Int. J. RF and Microwave Computer-Aided Eng., 2003, vol. 13(3), pp. 496–519. [79] Grebennikov A. “Simple design equations for broadband Class E power amplifiers with reactance compensation.” IEEE MTT-S International Microwave Symposium Digest; Phoenix, AZ, May 2001, vol. 3, pp. 2143– 2146. [80] Degtev V.I., and Kozyrev V.B. “Transistor single-ended switching-mode power amplifier with forming circuit (in Russian).” Poluprovodnikovaya Elektronika v Tekhnike Svyazi, 1986, vol. 26, pp. 178–188. [81] Kumar N., Prakash C., Grebennikov A., and Mediano A. “High-efficiency broadband parallel-circuit Class E power amplifier with reactance-compensation

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Chapter 2

High-efficiency Doherty power amplifiers Andrei Grebennikov1

Although invented more than 80 years ago, the Doherty amplifier architecture plays and will continue to play an important role in the development of energy-efficient radio transmitting systems for a variety of wireless communication applications including digital radio and television transmitters, handset and cellular infrastructure transmitters, and millimeter-wave transmitters for next generation wireless communication systems [1–3]. This chapter describes some examples and explains different techniques of Doherty amplifier design using asymmetric, multistage and inverted structures, integrated and monolithic Doherty amplifier implementations, and broadband inverted Doherty amplifiers.

2.1 Basic Doherty amplifier structure A new power amplifier technique for amplitude-modulated (AM) radio-frequency signals was invented by William H. Doherty in broadcasting in the mid-1930s as a more efficient alternative to both conventional amplitude-modulation techniques and Chireix outphasing [4]. The amplifier was configured in a grounded-cathode structure where two vacuum tubes were connected in parallel, one as a Class B carrier tube and the other as a Class C peaking tube, and the tubes were split and combined through þ90 and 90 phase shifting networks. This novel power amplifier architecture removed limitation of low efficiency inherent in a conventional power amplifier circuit, permitting efficiencies of 60% to 65% to be realized, while retaining the principal advantages associated with low-level modulations systems and linear power amplifiers. The simplified block diagram of a two-stage Doherty system is shown in Figure 2.1(a), where the key elements are the use of two power amplifiers, carrier and peaking, and the quarter-wavelength transmission line at the output of the carrier amplifier providing load modulation function as an impedance transformer. The quarter-wavelength line at the input of the peaking amplifier is used to compensate for the 90 phase shift occurring due to the presence of the quarterwavelength line at the output of the carrier amplifier. The basic operation principle 1

Sumitomo Electric Europe Ltd., Hertfordshire, United Kingdom

100

Radio frequency and microwave power amplifiers, volume 2 λ/4

I1

I3

Carrier R1

Z2

R3

IL

λ/4

Input Z1 λ/4

I2

RL = 50 Ω

Peaking R2

(a) Efficiency, % 80 Doherty 60 40

Class B

20 0 −18

−12

3 dB Input

−6

0

Backoff power level, dBc

(b)

50 Ω Carrier λ/4

Peaking

Z0 = 35 Ω

50 Ω

λ /4

R

RL = 50 Ω

(c)

Figure 2.1 Doherty amplifier structures and efficiency performance of a conventional Doherty amplifier architecture can be analyzed for low, medium, and peak output power regions separately [5]. At low output levels, the carrier amplifier operates linearly with Class B bias, reaching saturation corresponding to maximum efficiency at some transition voltage below the system maximum output voltage, and the peaking amplifier is turned off due to Class C bias. In a classical Doherty system, the transition voltage is half of the maximum output voltage. At higher output power levels, the carrier amplifier remains saturated, but the carrier amplifier operates linearly. As a result, the maximum amplifier efficiency is achieved at both the transition point and maximum output power.

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Assuming the lossless matching circuits of the carrier and peaking amplifiers, the impedance seen at the output of the transmission line in the carrier-amplifier path is R3 ¼

I2 þ I3 Z12 Z2 ¼ 1 I3 RL bRL

(2.1)

while the peaking power amplifier sees the impedance: R2 ¼

I2 þ I3 Z12 Z12 ¼ I2 RL ð1  bÞRL

(2.2)

where the current division ratio b is defined as b¼

I3 I2 þ I3

(2.3)

Because at maximum output power both carrier and peaking amplifiers are saturated, the resultant drain efficiency is equal to the maximum achievable efficiency of 78.5% for an ideal Class-B operation. For the conventional Doherty amplifier architecture shown in Figure 2.1(a), when both carrier and peaking amplifiers produce equal output powers, their load impedances are equal to R1 ¼ R3 ¼ R2 ¼ Z2 ¼ 2Z12 =RL . If the characteristic impedance of the output transmission line is chosen to be Z1 ¼ 35 W, then R1 ¼ R3 ¼ R2 ¼ Z2 ¼ RL ¼ 50 W. In a low power region, the peaking amplifier is turned off due to insufficient input drive to overcome the negative Class-C bias and appears as an open circuit. The carrier amplifier is operated in the active region, and sees the load impedance according to
2 Z2 RL (2.4) R1 ¼ Z1 which results in R1 ¼ 2RL ¼ 100 W when Z1 ¼ 35 W and Z2 ¼ RL ¼ 50 W. Because the output power of the carrier amplifier in saturation is four times less than the maximum output power, the drain efficiency of the carrier amplifier in an ideal Class-B mode will be two times greater than that of a conventional Class-B power amplifier obtaining maximum of 78.5% at 6 dB power backoff, as shown in Figure 2.1(b). Figure 2.1(c) shows the alternative two-stage transmission-line Doherty amplifier architecture, where a quadrature directional coupler is used at the input of the Doherty amplifier to eliminate the quarter-wavelength transmission line at the input of the peaking amplifier. In this case, it is only necessary to include the quarter-wavelength at the output of the carrier amplifier to separate it from the peaking amplifier and the output quarter-wavelength transformer which has the capability to invert impedances according to R¼

Z02 RL

(2.5)

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where Z0 is the characteristic impedance of the transmission line. From (2.5), it follows that the input impedance R increases inversely with the load impedance RL for thepsame Z0ffi. In this case, the output quarter-wavelength transmission line with ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Z0 ¼ 25  50 ¼ 35 W is required to match the standard load impedance of 50 W to achieve maximum power when both carrier and peaking amplifiers are turned on and each of which is designed to operate to a 50-W load.

2.2 Asymmetric Doherty amplifiers There is a possibility to extend the region of high efficiency over a wider range of output powers if the carrier and peaking amplifiers are designed to operate with different output powers: smaller for the carrier amplifier and larger for the peaking amplifier. For instance, for a power division ratio a ¼ Pcarrier/ (Ppeaking þ Pcarrier) ¼ 0.25, the transition point with maximum drain efficiency corresponds to the backoff power level of 12 dB from peak output power [5]. At maximum output power when the carrier and peaking amplifiers shown in Figure 2.1(a) are saturated, it follows from consideration of their output powers that R1 ¼ Z2 ¼ R3 ¼ 3R2. As a result, I2 ¼ 3I3 and b ¼ 0.25. The output impedances R2 and R3 as functions of the load resistance RL and characteristic impedance Z1 can be obtained from (2.1) and (2.2). For example, if one can choose the characteristic impedance of the output transmission line and load resistance equal to Z1 ¼ 15 W and RL ¼ 50 W, respectively, then the characteristic impedance of the quarterwave transformer and load impedance for the carrier amplifier are Z2 ¼ R1 ¼ 18 W, while the output impedance of the peaking amplifier is equal to R2 ¼ R1/3 ¼ 6 W. Because, from (2.1) and (2.2), it follows that R1 ¼

Z22 bR3

(2.6)

consequently, at lower power levels when the peaking amplifier is turned off, the output impedance R1 is four times higher than that at maximum output power where R1 ¼ Z2 ¼ R3. In this case, the power ratio between the peaking and carrier amplifiers should be 3:1. However, if the proper device sizes cannot be properly selected due to their physical availability, especially this is a concern for packaged devices, then other device size ratios can be chosen. For example, due to availability issues of the power GaAs HBT devices, a scaling ratio of 4:1 was chosen, with total emitter areas of 3360 mm2 and 840 mm2 for the peaking and carrier amplifiers, respectively, to implement the extended Doherty technique into the monolithic power amplifier developed for CDMA handset applications. As a result, the power-added efficiency (PAE) of 45% and 23% were measured at the highest output power of 25 dBm and at 10-dB backoff level, respectively [6]. The conventional Class-AB power amplifiers designed for the same application normally have the PAE of about four times lower at this backoff power. To optimize linearity and efficiency of the asymmetric Doherty amplifier, it is very important to optimize the biasing conditions for the carrier and peaking amplifiers [7].

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For the packaged devices when it is difficult to choose the proper power ratio between the devices, it is convenient to use the identical power amplifiers that can compose ideally the N-way Doherty architecture where one carrier amplifier is in parallel with (N1) numbers of the peaking amplifiers. This is the simplest hybrid approach to acquire an (N1) times larger-sized peaking amplifier compared with the carrier amplifier for an asymmetric two-way Doherty amplifier configuration [8]. Figure 2.2(a) shows the schematic diagram of an N-way Doherty amplifier with a parallel connection of one carrier amplifier and (N1) identical peaking amplifiers. The ideal drain efficiencies of the N-way Doherty amplifier (DA) architectures with peak values at 6 dB, 9.5 dB, 12 dB, and 14 dB

N-way splitter

Carrier Offset line PA Z0

Offset line

l/4

PA l/4 Peaking 1

Input

RL Peaking (N–1) PA l/4

(a)

Offset line

5-way DA 4-way DA 3-way DA Efficiency, %

2-way DA

80 60 40 20 Class B PA 0 –24 (b)

–18

–12 Backoff power level, dB

–6

0

Figure 2.2 Block schematic of (a) asymmetric N-way Doherty amplifier and (b) efficiencies

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power backoff points according to Pbackoff ¼ 20log10N for the two-, three-, four-, and five-way structures, respectively, and the conventional Class-B power amplifier are shown in Figure 2.2(b). Generally, the N-way Doherty amplifier is composed of the N-way power splitter, identical fully matched carrier and (N1) peaking amplifiers, N offset lines, and an output combiner representing a quarterwave impedance transformer. The characteristic impedance of a quarterwave pffiffiffi transmission line for converting the load of the carrier amplifier is Z0 ¼ R0 = a and the common load resistance is RL ¼ R0/(a þ 1), where R0 is the matched load for both carrier and peaking amplifiers, usually equal to 50 W [9]. For asymmetric two- and three-way Doherty amplifiers with optimized individual bias conditions and load matching for the carrier and peaking amplifiers, applying an uneven drive results in more linear operation and produces more power than an even drive [10,11]. For example, a three-way Doherty amplifier based on Class-F load networks and fabricated using 10-W GaN HEMT devices achieved a PAE of 45.9% and an adjacent channel leakage ratio (ACLR) of 49.2 dBc for a single-carrier WCDMA signal with a PAR of 10 dB at 2.14 GHz using a digital feedback predistortion technique [12]. Despite the efficiency improvement offered by the asymmetric N-way Doherty amplifier over its symmetric two-way Doherty amplifier counterpart, its total power gain, which significantly depends on the power gain of the carrier amplifier, will be reduced due to the corresponding insertion loss in the required input N-way power splitter. This issue is circumvented by using distributed amplification because distributed amplification is a technique whereby power combining is performed directly at the transistor level without the need for an N-way power combiner. Figure 2.3 shows the simplified schematic of a distributed Doherty amplifier, where the powers of both N-carrier and N-peaking amplifiers are combined using half-wave and quarterwave microstrip lines [13,14]. The desired location of peak efficiency points of such a distributed N-way Doherty amplifier can be given in decibels by
Pbackoff ¼ 20 log10

 K þ1 M

(2.7)

where K and M are the numbers of the peaking and carrier amplifiers, respectively. Practically, in order to design a high-efficiency three-way distributed Doherty amplifier, the two peaking amplifiers can be combined using a dual-fed distributed structure. The measured results of a three-way distributed 2.14-GHz Doherty amplifier using three 45-W LDMOSFET devices indicated that a PAE of 39.5% with a power gain of 11 dB was achieved at 9.5-dB backoff. For a high-power amplifier with very low output impedance, the width of the matching microstrip line should be very wide being comparable to its length, and the overall size of the matching circuit, including an offset line to create an opencircuit condition when the peaking amplifier is turned off and a quarterwave transforming line, becomes sufficiently large and it is very difficult to physically connect the output of the peaking amplifier directly to the main amplifier path.

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N-way carrier amplifier Offset lines Input matching circuit

Pin

Output matching circuit

Z0, l/4 Input matching circuit

Output matching circuit

Pout

l/2

l/2 Input matching circuit

Output matching circuit

l/2

l/2

Input matching circuit

l/4

ZT, l/4

Output matching circuit

N-way peaking amplifier

l/4

Figure 2.3 Distributed N-way Doherty amplifier Therefore, for implementation convenience, the classical N-way Doherty amplifier configuration can be modified by including an additional half-wave line at the output of each peaking amplifier. Figure 2.4(a) shows the block schematic of a three-way asymmetric Doherty amplifier configuration, where the output combiner includes one quarterwave microstrip line in a carrier path, two quarterwave microstrip lines in each peaking path, and one combining quarterwave microstrip line [15]. Here, each amplifying path includes the packaged device of the same die size and input and output matching circuits using microstrip lines. Offset lines are necessary to provide open-circuit conditions at their ends for peaking amplifiers when they are turned off. Then, two quarterwave microstrip lines with different widths required for the corresponding impedance transformation translate this open-circuit condition in each peaking path to open circuit seen by the carrier path at output power levels lower than 9 dBc at a common node in the output combiner. For example, for identical amplifiers having optimum load impedance each RLffiffiffiis the standard 50-W load impedance, Z0 ¼ 5pW ffiffiffiffiffiffiffiffiffiffi p ffiffiffiffiffiffiffiffiffi ffi and Z2 ¼ RL ¼ 50 W,pwhere Z1 ¼ Z0 Z2 ¼ 15:8 W and Z3 ¼ Z2 RL = 3 ¼ 28:9 W. There may be different combinations of the characteristic impedances between quarterwave microstrip lines in the output combiner. The quarterwave microstrip line in the input path of the carrier amplifier is used to compensate for the delay provided by the output combiner.

106

Radio frequency and microwave power amplifiers, volume 2 Input matching

Output matching

Offset lines

Output combiner

Z0

l/4

Peak1 Z1

High impedance when turned off

Pin 50 Ω

Input three-way in-phase divider

Z2

Z0

l/4

l/4

l/4

l/4

Z1

Z3

Pout 50 Ω

Main

High impedance when turned off Z

Z2

l/4

l/4

0

Peak2 Z1

(a) 18

90

70

2.11 GHz 2.14 GHz 2.17 GHz

17 16

60

Gain (dB)

Drain efficiency (%)

80

50 40 30

14 13

11

10

(b)

15

12

20

0 +30

2.11 GHz 2.14 GHz 2.17 GHz

+35

+40

+45

+50

Output power (dBm)

+55

+60

10 +30

+35

+40

+45

+50

+55

+60

Output power (dBm)

Figure 2.4 (a) Block schematic and (b) performance of high-power three-way Doherty amplifier The test board of a modified three-way Doherty amplifier based on three dual-path GaN HEMT devices in metal-ceramic flange packages, each including a pair of 180-W GaN HEMT dies with internal input matching, was fabricated on a 20-mil RO4350 substrate. The input three-way divider, input and output matching circuits, offset lines, output combiner, and gate and drain bias circuits (having bypass capacitors on their ends) are fully based on microstrip lines of different electrical lengths and characteristic impedances. Special care was taken for device implementation process to minimize the output lead inductances of the packaged GaN HEMT device. As a result, the measured output power at 1-dB gain compression point P1dB of 60 dBm and peak efficiency of 80% with a power gain of about 15 dB were achieved at a supply voltage of 55 V within the frequency range of 2.11–2.17 GHz. Figure 2.4(b) shows the plots of the drain efficiency and power gain versus output power, with a drain efficiency of about 70% at around 8.5 dB power backoff [15]. For a 20-MHz LTE signal with a peakto-average power ratio (PAR) of 8 dB, an average power of 52 dBm was obtained with a drain efficiency of about 65%. In this case, a power gain of about 15 dB was achieved in a linear operating region having 2-dB flatness over the entire output power range up to 60 dBm when its value reduces by just 1 dB compared to its value in linear region.

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2.3 Multistage Doherty amplifiers Generally, an asymmetric Doherty architecture exhibits a significant drop in efficiency in the region between the efficiency peaking points, especially for large power ratios between the carrier and peaking amplifiers. However, it is possible to use more than two power amplifiers to prevent significant deterioration of efficiency at backoff output power levels. This can be provided by the so-called multistage Doherty amplifiers, whose operation is somewhat similar to that of a two-stage Doherty amplifier as having a low-power region when only the carrier amplifier is turned on and a high-power region when all peaking amplifiers are turned on [5]. In this case, unlike the asymmetric Doherty amplifier when all peaking amplifiers are turned off simultaneously, the peaking amplifiers in a multistage Doherty amplifier are turned off consecutively at the corresponding peak efficiency points, beginning from (N1) peaking amplifier. The basic multistage Doherty power amplifier architecture shown in Figure 2.5(a) comprises more than one peaking amplifier, with quarterwave transmission lines to combine their output powers [16]. The characteristic impedances N-way splitter

Carrier

ZN-1

PA

ZN-2

l/4

Input

l/4

PA l/4

Peaking 1

Z1 l/4

RL

PA (N-1)l/4

(a) 3-way splitter

Carrier

Peaking (N-1)

120 Ω

PA

30 Ω

l/4

Input 50 Ω

50 Ω

l/4

27 Ω

PA l/4

Peaking 1 l/4

50 Ω

RL = 15 Ω

50 Ω

PA l/2

Peaking 2

(b)

Figure 2.5 (a) Multistage and (b) three-stage Doherty amplifier architectures

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of each output quarterwave transmission line depend on the levels of backoff power and can be calculated from: Zi ¼ RL

i Y

gj

(2.8)

j¼1 ðiþk YÞ=2

gð2jkÞ ¼ 10ðBi =20Þ

(2.9)

j¼k

where i ¼ 1, 2, . . . , N  1, k ¼ 1 (for odd i) or 2 (for even i), N is the total number of amplifier stages, and Bi is the backoff level (positive value in decibels) from the maximum output power of the system, at which the efficiency peaks. The maximum level of backoff BN1 is set by the carrier amplifier, while the number of efficiency peaking points is directly proportional to the number of amplifier stages used in the design. Figure 2.6 shows the theoretical instantaneous drain efficiencies of the multistage DA architectures for the two, three, and four stages, having maximum efficiencies at the transition points of 6 dB, 12 dB, and 18 dB backoff output power levels, respectively. From Figure 2.6, it follows that the multistage architecture provides higher efficiencies at backoff levels between the efficiency peaking points compared with an asymmetric Doherty architecture and significantly higher efficiency at all backoff output power levels compared with the conventional Class-B power amplifier. For the most practical case of a three-stage Doherty amplifier, whose block schematic is shown in Figure 2.5(b), the characteristic

4-stage DA 3-stage DA 2-stage DA

Efficiency, % 80 60 40

Asymmetric 4-way DA

20 Class B PA 0 –24

–18

–12

–6

0

Backoff power level, dB

Figure 2.6 Theoretical efficiencies of different Doherty amplifier architectures

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109

impedances of each output quarterwave transmission line can be obtained from (2.8) and (2.9) to be Z1 ¼ g1 RL

(2.10)

Z2 ¼ g1 g2 RL

(2.11)

where g1 ¼ 10ðB1 =20Þ , g2 ¼ 10ðB2 =20Þ , B1 ¼ 6 and B2 ¼ 12 for peak efficiencies at 6 dB and 12 dB backoff points, respectively, resulting in Z1 ¼ 30 W and Z2 ¼ 120 W for RL ¼ 15 W. For a 1.95-GHz WCDMA application, a three-stage Doherty amplifier structure using GaAs MESFET devices with the device periphery ratio of 1:2:4 and microstrip power combining elements provides a PAE of 48.5% and a power gain of 12 dB at P1dB ¼ 33 dBm. The peak power-added efficiencies of 42% and 27% were measured at 6 dB and 12 dB backoff levels [16]. Efficiencies at backoff points can be increased by optimizing the input drive conditions for the peaking amplifiers [17]. Moreover, further efficiency improvement of a three-stage Doherty amplifier at maximum output power and backoff points can be achieved by using the highly effective GaN HEMT devices and applying a digital predistortion technique for linearization. In this case, the drain efficiency at 12 dB output power backoff point can be increased to be higher than 60% [18]. A typical problem associated with the conventional three-stage Doherty amplifier is that the load-line modulation of the carrier stage stops at a certain power level, leaving the carrier amplifier in deep saturation and leading, consequently, to a significant degradation of its linear performance. In addition, when the carrier and peaking amplifiers have equal configurations with the same device periphery sizes, similar performance is obtained with regards to the symmetrical two-stage Doherty amplifier, with the efficiency peaking points at 3.5 dB and 6 dB backoff output powers. These problems can be partially solved by using a modified three-stage Doherty amplifier architecture with a parallel combination of one carrier and one Doherty amplifier used as a peaking amplifier, as shown in Figure 2.7(a) [19]. In this case, a novel way of combining enables high instantaneous efficiencies at 6 dB and 9.5 dB backoff output powers with a single device size. The characteristic impedances quarterwave transpffiffiffi of the transforming pffiffiffi  3=2 RL , and Z3 ¼ RL, where mission lines are calculated as Z1 ¼ 3RL , Z2 ¼ RL is the load resistance [20,21]. Figure 2.7(b) shows the schematic of modified classical three-stage Doherty architecture with power ratio 1:1.75:1 and half-wave electrical lengths from intrinsic drains of main and second peaking devices to corresponding combining points for convenience of practical implementation [22]. By using 28 V LDMOSFET devices having a peak power of 150 W for peaking amplifiers and 260 W for carrier amplifier, an average output power of 49 dBm with a drain efficiency greater than 55% and a power gain above 15.5 dB were achieved in the frequency range of 1805–1880 MHz for a 20-MHz WCDMA signal with a PAR of 9.9 dB.

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Radio frequency and microwave power amplifiers, volume 2 3-way splitter

Carrier l/4

Offset lines

l/4

PA Z1 = 87 Ω Peaking 1 Input

l/4

l/4

Z3 = 50 Ω

Z2 = 43 Ω

PA RL = 50 Ω

Peaking 2 l/4 PA

(a) Peaking 2 3 dB

Output quasi-l/4 matching

Z1 = 50 Ω, l/4

PA

3 dB

l/4

Carrier

Z1 = 18.2 Ω, l/4

Z4 = 25.8 Ω

PA l/4 l/4 Input

Peaking 1

Z2 = 28.6 Ω, l/4

RL = 50 Ω

PA

(b)

Figure 2.7 Modified three-stage Doherty amplifier architectures with (a) 3-way splitter and (b) two hybrid 3-dB couplers After applying a digital predistortion system, the linearity was improved from 29 dBc to 60 dBc. Figure 2.8 shows the theoretical instantaneous drain efficiencies of the multistage (three and four stages) and four-way asymmetric DA architectures for different power (or device size) ratios, with peak efficiencies ranging from 12 dB power backoff levels. From Figure 2.8, it follows that the four-way or any asymmetric multiway Doherty architecture provides significantly lower efficiency between the corresponding peak efficiency points. However, for a multistage Doherty configuration, the peak efficiency points at lower power backoff levels can be achieved using an optimum device size ratio. For example, a peak efficiency at the lowest backoff point of 12 dB is achieved for a device periphery ratio of 1:3:4 in a three-stage Doherty amplifier, whereas the lowest backoff of about 9.5 dB corresponds to the peak efficiency for an equal device periphery size of 1:1:1 in the modified three-stage Doherty amplifiers shown in Figure 2.7(a) [16,21]. In a classical four-stage Doherty power amplifier with the corresponding peak efficiencies at 6 dB, 12 dB, and 18 dB backoff output power points, the maximum ratio between the characteristic impedances of the quarterwave transmission lines is equal to 16 [16]. For example, for RL ¼ 6 W, the characteristic impedances of the consecutive quarterwave transmission lines are Z1 ¼ 12 W, Z2 ¼ 48 W, and Z3 ¼ 192 W, respectively. These values are difficult to correctly implement using microstrip lines on a single substrate with a fixed thickness and

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4-stage DA: 1:1:1:1 [23] 3-stage DA: 1:3:4 [16] 3-stage DA: 1:1:1 [19]

Efficiency, % 80 60 40

Asymmetric 4-way DA

20 0

–18

–12

–6

0

Backoff power level, dB

Figure 2.8 Theoretical efficiencies of different Doherty amplifier architectures

Carrier 3 dB

Offset line

50 Ω

PA l/4 Offset line

3 dB

Peaking 3

Offset line

25 Ω

PA l/4 3 dB Pin

Offset line

Peaking 2

25 Ω

Offset line

l/4

50 Ω

PA

Offset line

Peaking 1

Offset line

50 Ω

PA l/4

Figure 2.9 Modified four-stage Doherty amplifier architecture dielectric permittivity. In a modified four-stage Doherty configuration with the device size ratio of 1:1:1:1, as shown in Figure 2.9, where the two conventional two-stage Doherty amplifiers are combined in a final four-stage Doherty configuration, the maximum ratio between the transmission-line characteristic impedances is equal to 50 W/25 W ¼ 2 only [23]. Figure 2.8 also shows the three efficiency peaking points provided by the modified four-stage Doherty amplifier with equal gate bias voltages for the second and third peaking amplifiers. Furthermore, the optimization of these gate bias

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voltages can change the efficiency profile between the maximum power and 6 dB backoff points and contribute to linearity improvement. Because of the device input and output parasitics such as the gate-source and drain-source capacitances, additional input offset lines are implemented at the input of the peaking amplifiers and identical output offset lines that introduce the compensating inductive reactances are connected in series to each output circuit. This is a very practical version of a four-stage Doherty amplifier, capable of achieving high output powers with high drain efficiency and having three commercially available 90 hybrid couplers at the input and four quarterwave microstrip lines at the output. Figure 2.10 shows the test board of the modified four-stage GaN HEMT Doherty power-amplifier architecture based on four 25-W Cree CGH40025F devices and fabricated using a 30-mil RO4350 substrate. The carrier and peaking amplifiers are designed to operate in an inverse Class-F mode with the second- and third-harmonic control by using a transmission-line load-network technique. The input dividing network includes three 90 hybrid couplers, while a 30-dB directional coupler required to sampling output power for linearization loop needs to be connected to the output port. In a continuous-wave operation mode when all

Figure 2.10 Test board of 2.14 GHz 100-W four-stage Doherty GaN HEMT amplifier

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113

Z4, λ/4

3 dB CA –180°

High impedance when turned off

Z6 λ/4

RL

PA1 Z5, λ/4

–90°

3 dB

High impedance when turned off

3 dB –90°

PA3

RFin

High impedance when turned off 0°

Z7 λ/4

Z8 λ/4

PA2

Figure 2.11 Modified four-stage Doherty amplifier architecture transistors are biased with the same gate voltage of 3.4 V, an output power of 50 dBm (100 W) and a drain efficiency of 77% were achieved at a supply voltage of 34 V. In a single-carrier 2.14-GHz WCDMA operation mode with a PAR of 6.5 dB, a drain efficiency of 61% was obtained at an average output power of 43 dBm (20 W) with an ACLR of 31 dBc. Figure 2.11 shows the block schematic of another modification of a four-way Doherty configuration with the device size ratio of 1:1:1:1, where one carrier and three peaking amplifiers are combined in a four-stage Doherty configuration providing the maximum backoff peak efficiency point of 12 dBc [24]. Here, the input power divider includes only three quadrature couplers to split equally input power over the main and peaking amplifiers and provide the required phase shifts, but with extended number of the quarterwave lines in the load network.

2.4 Inverted Doherty amplifiers An inverted Doherty amplifier structure is an alternative configuration when, in view of presence of the parasitic device drain-source capacitance and series bondwire and package lead inductor, it can be easier to provide a short circuit rather than an open circuit at the output of the peaking amplifier when it is turned off. The schematic diagram of an inverted Doherty amplifier configuration with an impedance inverter based on a quarterwave transmission line connected to the output of the peaking amplifier is shown in Figure 2.12. The quarterwave transmission line can also be implemented in a compact form suitable for use in mobile applications

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Radio frequency and microwave power amplifiers, volume 2 Carrier amplifier

Offset lines ZT, λ/4

Output matching circuit

Input matching circuit

Pout Z0, λ/4

Pin

Output matching circuit

Input matching circuit

Peaking amplifier

Short at low power

Figure 2.12 Block schematic of inverted Doherty amplifier

[25]. In this case, a quarterwave transmission line operating as an impedance inverter is used at low-power levels to transform very low device output impedance after the offset line to high impedance seen from the junction point where both peaking and carrier amplifying paths are directly connected followed by an optimized output quarterwave transmission-line transformer or matching circuit [26,27]. Because the quarterwave transmission line is now physically presented in a peaking amplifying path rather than in a carrier amplifying path corresponding to a conventional structure, such a Doherty was called an inverted Doherty amplifier, although impedance matching in a carrier amplifying path to increase impedance seen by the carrier device at low-power region is provided by the corresponding output matching circuit, or in a simplified case, by a lumped low-pass L-type transformer composing of the shunt drain-source capacitance and series bondwire and package lead inductance. The operation principle of an inverted Doherty amplifier can be more clearly explained by considering the load network separately, as shown in Figure 2.13(a), where the peaking amplifier is turned off. In a low-power region, the short-length offset line with electrical length q will shift initial capacitive reactance at the output of the peaking amplifier (including output matching circuit) to zero impedance point, ideally equal to 0 W. The short circuit at the end of the quarterwave transmission line is then translated to the open circuit at its input so that it prevents power leakage to the peaking path when the peaking transistor is turned off. At the same time, the matching circuit together with offset line provides the required impedance transformation from 25 W to the optimum high impedance Zopt seen by the carrier device output at 6-dB power backoff, as shown in Figure 2.13(b). In a highpower region, both the carrier and peaking amplifiers are operated in a 50-W environment in parallel, and the output quarterwave line with the characteristic impedance of 35.3 W transforms the obtained 25 W to the required 50-W load. Generally, in practical implementation, when both Class-AB carrier and Class-C peaking amplifiers are not fully isolated from each other, the load impedances presented to both transistors should be optimized around the idealized conditions [28,29]. Figure 2.14 shows the block schematic of an inverted high-power three-way Doherty amplifier where the carrier and peaking amplifiers are matched to 25 W at

High-efficiency Doherty power amplifiers Offset lines Carrier

Matching circuit On

25 Ω

50 Ω

λ/4

Output

θ

35.3 Ω

50 Ω

Zmatch_on

Zopt Peaking

50 Ω λ/4 50 Ω

Matching circuit

θ

Off Zmatch_off

Zout_off

115

Short

(a) 0.

2 .0

5

3 .0

0Ω

R /ZO =0.2

CZmatch_on

-1

Zopt 1

25 ΩA

Гr

- 0.2 O= X/Z

-3

Zout_off

.0

0

-0

-1 . 0

.5

Zmatch_off

. -2

(b)

Figure 2.13 (a) Load-network schematic and (b) impedance curves on Smith chart Peaking 1 Output matching circuit

Input matching circuit

Pin 50 Ω

3-way in-phase splitter

Offset line

25 Ω θ1 λ/4

Carrier

8.3 Ω

Output matching circuit

Input matching circuit

50 Ω λ/4

Peaking 2 Input matching circuit

Output matching circuit

Pout

25 Ω θ2

Figure 2.14 Block schematic of high-power three-way inverted Doherty amplifier

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Radio frequency and microwave power amplifiers, volume 2

a high input power level [30]. In this case, the output matching at the output of the carrier amplifier is necessary to transform the load impedance of 8.3 W at low input power level. As a result, a saturated output power of 600 W and peak drain efficiency greater than 57% across the frequency bandwidth of 1.9–2.2 GHz were measured using three 200-W Cree GaN HEMT devices for a 10% duty ratio pulsed signal. After digital predistortion (DPD) linearization, an average drain efficiency of 40% at 1.92 GHz and 2.025 GHz was obtained for a single-carrier 10-MHz LTE signal with an ACLR lower than 47 dBc. Figure 2.15 shows the three-stage inverted Doherty amplifier configuration, where the quarterwave transmission lines were added at the outputs of the carrier and two peaking amplifiers as impedance inverters to provide the corresponding low- and high-impedance conditions to properly achieve three efficiency peaking points [31]. By introducing the device size ratio between the carrier, first peaking, and second peaking amplifiers as 1:m1:m2, the characteristic impedances of the quarterwave transmission lines can be defined as rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 ZT ¼ Z1 (2.12) 1 þ m1 þ m2 rffiffiffiffiffiffi Z3 1 Z4 ¼ Z1 (2.13) Z2 m1 rffiffiffiffiffiffi Z3 1 (2.14) Z5 ¼ Z1 Z2 m2 when the carrier and peaking amplifiers are operated in a 50-W environment. In this case, for equal device sizes of the carrier and peaking amplifiers when m1 ¼ m2 ¼ 1, Z2 ¼ Z3 ¼ 50 W, and Z1 ¼ 70 W, from (2.12)–(2.14), it follows that ZT ¼ 40.4 W and Z4 ¼ Z5 ¼ 70 W. Carrier

Offset lines Output matching circuit

Input matching circuit

Z1, λ/4

ZT, λ/4

Pout 50 Ω

Z2, λ/4 λ/2 Z3, λ/4

Peaking 1 Pin 50 Ω

3-way in-phase splitter

Output matching circuit

Input matching circuit

Z4, λ/4

Z5, λ/4 Output matching circuit

Input matching circuit Peaking 2

Figure 2.15 Schematic diagram of three-stage inverted Doherty amplifier

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2.5 Integrated Doherty amplifiers At microwave and millimeter-wave frequencies, the transmission-line Doherty amplifier is usually implemented into the monolithic microwave integrated circuit (MMIC) by using a pHEMT, GaN HEMT, or CMOS process. For example, a fully integrated Ku-band MMIC Doherty amplifier using a 0.25-mm pHEMT technology achieved a two-tone PAE of 40% at 17 GHz, while a PAE of 38.5% at 1-dB gain compression point was obtained for a 20-GHz MMIC Doherty amplifier using a 0.15-mm pHEMT technology [32,33]. Based on a 0.13-mm RF CMOS process, the transmission-line MMIC Doherty amplifier using cascode configurations of the carrier and peaking amplifiers achieved a saturation output power of 7.8 dBm at 60 GHz [34]. However, at lower frequencies, it is difficult to provide a high level of integration of a Doherty amplifier, mainly because of the physical size of the quarterwave transmission lines. For example, for an FR4 substrate with effective dielectric permittivity of er ¼ 3.48, the geometrical lengths of the quarterwave transmission lines are 48 mm, 19 mm, and 8.7 mm at 900 MHz, 2.4 GHz, and 5.2 GHz, respectively. In this case, the most attractive solution to fabricate smallsize integrated Doherty amplifiers is to replace each quarterwave line in the input divider and output impedance transformer by its low-pass P-type equivalent with a short-length series transmission line and two shunt capacitors connected to its both ends [35,36]. At the same time, simple and small-size second-harmonic terminations can be provided by integrated metal-insulator-metal (MIM) capacitors and bondwires at the device collectors [35]. High substrate loss can be minimized and high level of integration to implement the Doherty amplifier in a CMOS process can be provided if the branch-line coupler and quarter-wavelength transformer are fully substituted by their lumped equivalents [37]. Comparing the transmission ABCD-matrices for a quarterwave transmission line of Figure 2.16(a) and a low-pass lumped P-type LC circuit of Figure 2.16(b), the ratio between the corresponding matrix elements can be written as Z0 wC ¼

Z0 ¼1 wL

(2.15)

where Z0 is the characteristic impedance of the quarter-wavelength line. A highpower Doherty amplifier using LDMOSFET or GaN HEMT technology can be Z0, λ/4

L

C

(a)

C

(b)

Figure 2.16 Quarterwave transmission line and its single-frequency lumped equivalent

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integrated with lumped elements in a standard discrete device package, with external input and output matching circuit required to match with 50-W source and load [38]. For example, an integrated solution based on four parallel 10-W MMIC Doherty amplifier cells could provide a drain efficiency of 39.8% at an average output power of 7.5 W with an ACLR of 50 dBc using DPD linearization for a two-carrier 2.14-GHz WCDMA signal with a PAR of 7.6 dB [39]. Figure 2.17 shows an example of the simplified schematic of a two-stage lumped Doherty amplifier, where the quarterwave transmission line connected to the carrier amplifier output and the input phase-shifting quarter-wavelength transmission line connected to the peaking amplifier input are replaced by their lumped low-pass P-type LC equivalents. Here, the output quarterwave impedance transformer is replaced by an L-type high-pass LC equivalent, whereas the input matching of the carrier and peaking amplifiers is provided by two low-pass L-type LC matching circuits. To minimize the number of matching components, the shunt capacitor at the right-hand side of the equivalent quarterwave LC phase shifter and the shunt capacitor at the left-hand side of the input low-pass L-type matching circuit can be combined into a single shunt capacitor. To minimize size and cost and to simplify the design complexity of a highpower integrated Doherty amplifier implemented into the standard discrete package, a P-type low-pass LC circuit to equivalently replace the quarterwave line can be formed by the device drain-source capacitances and bondwire placed between the device drains [40]. In this case, the input splitter can be similarly designed using the device gate-source capacitances and bondwire connected between the device gates including a dc-blocking capacitor, as shown in Figure 2.18 [41]. As a result, a maximum power gain of 15.9  0.2 dB and an average drain efficiency of 47  1% at 6-dB backoff from the maximum output power of 50 dBm were achieved for a 10-MHz LTE signal with a PAR of 7.2 dB from 1.805 to 2.17 GHz based on silicon LDMOSFET technology in a compact package of 50  50 mm2. Figure 2.19 shows the circuit schematic of a three-stage integrated Doherty amplifier where a Wilkinson-type asymmetric input splitter and an output combiner based on lumped low-pass LC prototype impedance inverters absorb the device gate-source and drain-source capacitances, respectively [42]. With a device size

Pout Pin

Figure 2.17 Circuit schematic of lumped Doherty amplifier

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Carrier Pin Cds

Cgs LG

LD Peaking Pout Cds

Cgs

Figure 2.18 Basic schematic of two-stage integrated Doherty amplifier

Li1

Carrier

Pin C Lo1

Li2

Li3

Peaking 1

C Lo2

Li4

Li5

Peaking 2 Pout

C

Figure 2.19 Circuit schematic of three-stage integrated Doherty amplifier ratio of 1:4:4, the measured results show the capability to achieve a power gain of 12  1 dB and a PAE of 45%–55% at 12-dB backoff power level from a maximum output power of 47 dBm across the frequency bandwidth of 1.8–2.2 GHz using a compact package of 3  5 mm2 suitable for small cell applications. Similarly, a four-stage Doherty amplifier based on two basic 50-W two-stage structures with

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a device size ratio of 1:1:1:1 and implemented in a dual-path package, as shown in Figure 2.20, achieved a power gain of 13.4  0.2 dB with an average drain efficiency of 47  1 dB at 8-dB backoff from the peak output power of 100 W across the frequency range of 1.805 to 2.17 GHz for a 20-MHz LTE signal with a PAR of 7.2 dB [43]. The half-wave 25-W open-circuit stub in the load network is used for bandwidth extension using effect of reactance compensation. Figure 2.21 shows the MMIC implementation of a wideband asymmetric GaN HEMT Doherty power amplifier, where the input network consists of a lumpedelement Wilkinson power divider and phase shifter using spiral inductors and MIM capacitors, whereas the load network represents a T-type microstrip-line impedance transformer with optimized characteristic impedances and electrical lengths of microstrip lines [44]. The Doherty power amplifier was implemented in a 0.25 mm GaN HEMT process, having a 100 mm thick SiC substrate, a relative permittivity of 9.7, a maximum drain current density of 900 mA/mm, and a maximum power density of 5 to 7 W/mm, with a total chip size of 2.1  1.5 mm2. To obtain the highest possible output power with model verified device sizes, the total gate widths of the carrier and peaking devices were chosen as 4  100 mm and 10  100 mm, respectively. As a result, a PAE above 30% at 9-dB power backoff across 6.7–7.8 GHz and a maximum output power of 35  0.5 dBm across 6.6–8.5 GHz were achieved. For a symmetric 10-GHz MMIC Doherty power amplifier with Class-E mode in both carrier and peaking amplifiers using 140-nm GaN HEMTs of a 1-mm gate Dual path package Peaking 3

Input matching circuit

Pin Peaking 2

Output matching circuit

50 Ω Hybrid splitter iDPA 50 W

25 Ω λ/4

Peaking 1

Output matching circuit

Input matching circuit

25 Ω, λ/4

Pout 50 Ω

25 Ω λ/2 Carrier

iDPA 50 W

Figure 2.20 Block schematic of four-stage integrated Doherty amplifier

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121

Vd

1.5 mm

RFin

RFout

2.1 mm

Figure 2.21 Test chip of wideband monolithic GaN HEMT Doherty power amplifier [44] Carrier amplifier 50 Ω Input Phase compensation

Output matching circuit

Input matching circuit

Impedance transformer 50 Ω 100 Ω

50 Ω Input matching circuit

Output matching circuit

Peaking amplifier

Offset line 100 Ω Open at low power

Figure 2.22 Block schematic of 10-GHz monolithic GaN HEMT Doherty amplifier width each, the simulated two-tone results demonstrated a PAE of 40.4% at maximum output power of 25.6 dBm and a PAE of 24% at 6-dB backoff [45]. To improve linearity of a microwave Doherty amplifier, the input divider can be implemented without coupler by using an unequal-power reactive divider, as shown in Figure 2.22 [46]. In this case, the input divider changes the ratio of power delivered to each device as input power increases due to increased difference in the device gate-source capacitances over the input drive under different biasing conditions. The increased gate-source capacitance of the peaking amplifier reduces the load impedance presented to the input divider at the peaking amplifier port and therefore, as input power increases, more power is delivered to the peaking amplifier to relax saturated conditions for the carrier amplifier. To simplify the output network, both the carrier and peaking amplifiers were matched to 100 W for parallel combining. The fabricated MMIC of a Doherty amplifier based on 0.15-mm GaN on SiC

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Figure 2.23 Image of 24-GHz monolithic two-stage pHEMT Doherty amplifier [47] process demonstrated a saturated output power greater 36 dBm at peak PAE of 47% at 10 GHz, with a power gain greater than 9 dB up to 25 dBm of input power and a PAE of 41% at 6-dB output power backoff at a supply voltage of 20 V [46]. To increase power gain of a Doherty amplifier at very high frequencies, especially for K-band applications, the complete structure of Doherty amplifier should include a high-gain driver. In this case, the solution with drivers in the carrier and peaking paths provide higher PAE than an approach with a single driver for a final Doherty amplifier stage [47]. To achieve better linearity performance, the peaking device can be biased in Class AB or B, while the peaking driver biased in Class C is responsible for correctly turning on the peaking branch. To preserve stability of operation across the entire frequency range, it was necessary to insert shunt resistors (with a series dc-block) in parallel to the dc-bypass capacitors at drain and gate of each stage and to proper dimension the drain-feed stub lengths of the power stage. The cascaded Doherty amplifier was implemented in a commercially available 0.15-mm pHEMT process with dimensions of 1.43  3 mm2, as shown in Figure 2.23, and achieved an output power of 30.9 dBm with a PAE of 38% at saturation and 20% at 6-dB output power backoff with a power gain of 12.5 dB at 24 GHz in continuous-wave operation conditions. However, better performance at K-band for a two-stage cascaded Doherty amplifier can be achieved using a 0.15-mm GaN on SiC HEMT process when the measured results could demonstrate over 5 W of saturated output power having a PAE of 48% at P1dB, with a PAE of 25% at 8 dB of power backoff from P1dB with a power gain of 16 dB [48].

2.6 Broadband Doherty amplifiers To maximize the frequency bandwidth performance of a Doherty amplifier, it is very attractive to use an inverted Doherty architecture which can significantly simplify the entire design procedure and make design more compact and straightforward. In this case, there is an opportunity to use a single multistepped transmission-line output transformer to match any impedance at the common junction where the carrier and peaking amplifiers are connected to be matched to the standard load of 50 W. Figure 2.24(a) shows the simplified load network of an

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Carrier On

30 Ω

42 Ω

Output

λ/4

λ/4

50 Ω

PA 25 Ω

Peaking 50 Ω Off

PA λ/4 Short

(a)

Magnitude S21 (dB)

0.0 2

–0.2 1 –0.4 –0.6 –0.8 0.2

(b)

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

f/f0

Figure 2.24 (a) Load-network schematic and (b) its broadband performance

inverted Doherty amplifier with a two-section transmission-line output impedance transformer, where each quarterwave transmission line has a different characteristic impedance to match first the initial 25 W to intermediate 35.3 W and then to 50-W load. Such a 25-W to 50-W transformer provides wide frequency bandwidth, as shown in Figure 2.34(b) by curve 1. However, broader frequency range with flatter frequency response can be obtained using a quarterwave open-circuit stub at the input of the output transformer when the peaking amplifier is turned off, as shown in Figure 2.24(b) by curve 2, resulting in greater than octave bandwidth in a lowpower region at output power levels less than 6 dB backoff point. Figure 2.25 shows the simulated circuit schematic of a tri-band inverted GaN HEMT Doherty amplifier, where the carrier and peaking amplifiers using Cree CGH40010 devices are based on the same broadband transmission-line Class-E power amplifiers, and the broadband load network corresponds to the impedancetransforming structure shown in Figure 2.24(a) [49]. In this case, the entire combining load-network represents a very simple structure in implementation and tuning to achieve broader frequency response. The broadband quadrature hybrid coupler additionally provides a 90 phase shift at the input of the carrier amplifier across the entire frequency bandwidth. The impedance conditions of the peaking amplifier when it is turned off indicate near-zero reactance at high bandwidth frequency of 2.7 GHz and increasing capacitive reactance when the operating

Vgc

W = 28.5 mil L = 450 mil

Zcarrier

W = 28.5mil L = 500 mil

W = 45 mil L = 130 mil

50 Ω 20 pF

Vdd

Substrate: 20-mil RO4360

W = 100 mil L = 400 mil

50 pF

W = 300 mil L = 200 mil CGH40010F

50 Ω

W = 12 mil L = 130 mil

W = 85 mil L = 700 mil

W = 28.5mil L = 320 mil

Pout

Zpeaking

Pin W = 28.5 mil L = 150 mil

W = 28.5 mil L = 320 mil

W = 12 mil L = 130 mil

W = 45 mil L = 550 mil Zmatch

CGH40010F 20 pF

W = 100 mil L = 400 mil

W = 28.5 mil L = 450 mil

Vgp

W = 300 mil L = 200 mil W = 45 mil L = 130 mil

50 Ω

W = 40 mil L = 670 mil

50 pF W = 28.5 mil L = 500 mil

Vdd

Figure 2.25 Circuit schematic of tri-band inverted GaN HEMT Doherty amplifier

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frequency reduces to 1.8 GHz for Zmatch, and an open-circuit condition at higher bandwidth frequencies with sufficiently high inductive reactances at lower bandwidth frequencies for Zpeaking. Figure 2.26 shows the simulation results for the small-signal S21-parameters demonstrating the bandwidth capability of an inverted transmission-line GaN HEMT Doherty amplifier, which potentially can cover a wide frequency range of 1.6 to 3.0 GHz with a linear power gain over 11 dB. Figure 2.27 shows the simulated large-signal power gain and drain efficiencies of a transmission-line tri-band inverted GaN HEMT Doherty amplifier at dc-supply voltage of 28 V. In this case, the drain efficiencies of 59.0%, 57.0%, and 53.5% at backoff output powers of 38 dBm (6-dB backoff) were simulated at center bandwidth frequencies of 1842.5 MHz, 2140 MHz, and 2655 MHz, respectively, with a linear power gain above 11.5 dB. The tri-band transmission-line GaN HEMT Doherty amplifier was fabricated on a 20-mil RO4360 substrate using commercially available broadband coupled-line coupler. Figure 2.28 shows the test board of a tri-band inverted Doherty amplifier based on two 10-W Cree GaN HEMT devices in metal-ceramic pill packages (CGH40010P) [49]. For a single-carrier 5-MHz WCDMA signal with a PAR of 6.5 dB, the drain efficiencies of 58%, 50%, and 42% at an average output power of 38 dBm with a power gain of more than 11 dB were achieved at the operating frequencies of 1.85 GHz, 2.15 GHz, and 2.65 GHz, respectively, with an ACLR (at 5-MHz offset) measured from 32 dBc at 1.85 GHz to 37 dBc at 2.65 GHz. The gate bias voltages for carrier (Class-AB mode with a quiescent current of 100 mA) and peaking (Class-C mode) amplifiers were the same for all three frequencies. A high-power operation of the GaN HEMT device can be achieved with larger gate periphery resulting in a higher power capability in a given package. The corresponding increase in gate-source capacitance when multiplicity of basic device cells is connected in parallel reduces the input impedance to very low values, close to one or a few tenths of ohm. Therefore, it is very important for matching circuits to be partly implemented inside the device package to achieve an average output power 15

dB(S(2,1))

12 9 6 3 0 1.55

1.75

1.95

2.15 2.35 2.55 Frequency (GHz)

2.75

2.95

3.15

Figure 2.26 Simulated small-signal S21 versus frequency

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Radio frequency and microwave power amplifiers, volume 2 Power gain

Efficiency 80

15.0 Power gain (dB)

60 10.0 1842.5 MHz

7.5

40

5.0 20 2.5 0.0

Drain efficiency (%)

12.5

0 14

19

24

29

34

39

44

Output power (dBm)

(a)

80

15.0 12.5 Power gain (dB)

2140 MHz

7.5

40

5.0 20 2.5 0.0

Drain efficiency (%)

60 10.0

0 14

19

(b)

24

29

34

39

44

Output power (dBm) 80

15.0

60 10.0 7.5

40

2655 MHz

5.0 20 2.5 0.0

0 14

(c)

Drain efficiency (%)

Power gain (dB)

12.5

19

24

29

34

39

44

Output power (dBm)

Figure 2.27 Simulated power gain and drain efficiencies of tri-band inverted Doherty amplifier at (a) 1842.5 MHz, (b) 2140 MHz, and (c) 2655 MHz of 20 W (43 dBm). Figure 2.29(a) shows the complete structure of the device inside the package with input matching elements and the small-signal S11-parameters at the input of the internal input matching circuit including package leadframe [50]. Here, the Sumitomo 50-V device represents six basic 15-W GaN HEMT cells

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Figure 2.28 Test board of tri-band inverted GaN HEMT Doherty amplifier connected in parallel and capable to provide the output power greater than 80 W at saturation across the entire frequency bandwidth of 1.8–2.7 GHz. The three-section microstrip transformer was implemented using a ceramic substrate with high permittivity of 250 and thickness of 0.16 mm for compact structure to transform the device input impedance to the input impedance of 10 W with the S11 magnitude less than 25 dB. Figure 2.29(b) shows the schematic diagram of an inverted broadband Doherty amplifier configuration with an impedance inverter based on a quarterwave line connected to the output of the peaking amplifier. To better understand the operation principle of an inverted Doherty amplifier, consider separately the load network shown in Figure 2.30(a), where the peaking amplifier is turned off. In a low-power region, the phase adjustment of the offset line with electrical length q causes the peaking amplifier to be short-circuited (ideally equal to 0 W), and the matching circuit in conjunction with offset line provides the required impedance transformation from 25 W to the high output impedance Zout seen by the carrier device output at the 6-dB power backoff (ideally equal to 100 W with a quarterwave transformer), as shown in Figure 2.30(b). In this case, short circuit at the end of the quarterwave line translates to open circuit at its input so that it prevents power leakage to the peaking amplifying path when the peaking transistor is turned off. In a high-power region, both carrier and peaking amplifiers are operated in a 50-W environment in parallel, and the output quarterwave transmission line with the characteristic impedance of 35.3 W transforms the obtained 25 W to the required 50-W load. The impedance conditions at different points of the load network of the peaking amplifier when it is turned off are shown in Figure 2.31, where Zmatch shown in Figure 2.31(a) indicates low reactance at the output of the load network of the peaking amplifier over the required frequency range from 1.8 to 2.7 GHz, having near zero reactance at midband frequency with some inductive and capacitive reactances when operating frequency approaches to the bandwidth edges. At the same time, by using a series transmission line of a quarter-wavelength long at

IND ID=L8 L=0.005 nH

PORT P=1 Z=50 Ohm

MLIN ID=TL11 W=6.3 mm L=1.55 mm MSUB=MSUB3

IND ID=L6 L=0.1 nH

MLIN ID=TL12 W=0.45 mm L=2.544 mm MSUB=MSUB3

MLIN ID=TL10 W=2.01 mm L=2.487 mm MSUB=MSUB3

MLIN ID=TL9 W=3.32 mm L=1.875 mm MSUB=MSUB3

PORT P=2 Z=50 Ohm

IND ID=L2 L=0.0005 nH

2 1 Gate

Graph 1 0

MLIN ID=TL13 W=1.55 mm L=1.55 mm MSUB=MSUB2

SUBCKT ID=S1 NET=”SEDI_GaN_HELMT” Vdq=50 Remove_BW_inductane1 Temperature=5 self_healting=0 Ugw=27.3 3 Source N=0

Drain

MSUB Er=10 H=0.5 mm T=0.002 mm Rho=1 Tand=0.0001 Ernom=10 Name=MSUB2

DB)IS(1.1)I) SP_sim_A IND ID=LS L=0.00639 RH

–10 PORT P=3 Z=50 Ohm

–20

MSUB Er=250 H=0.16 mm RHO=1 Tand=0.001 Ernom=250 Name=MSUB3

–30

–40 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900

(a)

Figure 2.29

Frequency (MHz)

Complete structure of (a) packaged device with input matching and (b) block schematic of high-power two-stage broadband inverted Doherty amplifier

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Offset lines

2x80W GaN HEMT Carrier

Pout

Broadband matching λ/4 Peaking Broadband matching

Pin

Short at low power (b)

Figure 2.29 (Continued ) 25 Ω Carrier Lout Cout

On

θ

35.3 Ω

Load 50 Ω

50 Ω λ/4 Offset line

Lout

θ

Cout

Off

λ/4

Zmatch_on

Zout Peaking

Offset line

Zmatch_off

Short

(a)

Zmatch_on

0Ω

(b)

25 Ω

Zout

∞Ω

Zmatch_off

Figure 2.30 (a) Load-network schematic and (b) impedance curves on Smith chart

Radio frequency and microwave power amplifiers, volume 2

S(1,1)

S(1,1)

130

Zmatch

Freq (1.800 GHz to 2.700 GHz) (a)

Zpeaking

Freq (1.800 GHz to 2.700 GHz) (b)

Figure 2.31 Impedances for peaking amplifier high bandwidth frequency, an open-circuit condition seen from the carrier amplifying path is provided at higher bandwidth frequencies with sufficiently high inductive and capacitive reactances across the frequency bandwidth, indicating by Zpeaking shown in Figure 2.31(b). Hence, the broadband performance of such an inverted Doherty structure can potentially be achieved in a practical realization. Figure 2.32(a) shows the load-network equivalent circuit for the carrier amplifier with a frequency behavior of the impedance Zcarrier seen by the internal carrier device, whose real component slightly varies around 10 W, as shown in Figure 2.32(b). This means that, taking into account the device output shunt capacitance Cout of about 5 pF and series output inductance Lout provided by the overall bondwire and package leadframe inductances, the impedance seen by the device multiharmonic current source at the fundamental frequency across the entire frequency bandwidth of 1.8– 2.7 GHz has been increased by two times from initial 5 W at the input of the broadband output impedance transformer, which is high enough to achieve high efficiency at backoff output power levels. In this case, the device output capacitance and bondwire inductor constitute a low-pass L-type matching section to increase the load impedance seen internally by the device multiharmonic current source at the fundamental frequency. The test board of a tri-band inverted Doherty amplifier based on two 80-W GaN HEMT power transistors with internal input matching in metal-ceramic flange packages was fabricated on a 20-mil RO4350 substrate [50]. An input splitter represents a broadband 90 hybrid coupler from Anaren, which provides maximum phase balance of 5 and amplitude balance of 0.5 dB across the frequency range of 690–2700 MHz. The input matching circuit, output load network, and gate and drain bias circuits (having bypass capacitors on their ends) were fully based on microstrip lines of different electrical lengths and characteristic impedances. Special care was taken for device implementation process to minimize the output lead inductances of the packaged GaN HEMT device.

High-efficiency Doherty power amplifiers 5Ω

Carrier device Lout

Offset line

Broadband matching

Cout

Zcarrier

131

50 Ω Open circuit: peaking device is turned off

(a)

S(1,1)

Zcarrier

(b)

Freq (1.800 GHz to 2.700 GHz)

Figure 2.32 (a) Matching network and (b) load impedance for carrier amplifier

Figure 2.33 shows the measured power gain and drain efficiency of a transmission-line GaN HEMT high-power inverted Doherty amplifier across the entire frequency bandwidth for five frequencies. In this case, a power gain of more than 9 dB was achieved in a frequency range of 1.8–2.7 GHz. At the same time, the drain efficiencies greater than 55% at an output power corresponding to 3-dB gain compression point (P3dB) and around 50% at 7-dB backoff output powers were measured across the entire frequency bandwidth, with maximum drain efficiency greater than 70% at lower bandwidth frequencies below 1.95 GHz and peak efficiency points at maximum backoff output powers of around 6 dB over the entire frequency range. For concurrent transmission of four-carrier GSM signal and 10-MHz LTE signal with a PAR of 8 dB, the drain efficiency of 51% with an average total output power of 45.5 dBm (18.2 W for GSM signal and 17 W for LTE signal) was achieved, with the out-of-band intermodulation level lower than 70 dBc for fourcarrier GSM signal and ACLR lower than 57 dBc for 10-MHz LTE signal after dual-band DPD linearization. By using a high-power broadband inverted Doherty amplifier architecture with a 2  120-W dual-path GaN HEMT transistor, a saturated output power P3dB of

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Radio frequency and microwave power amplifiers, volume 2 80

Efficiency (%), Gain (dB)

70 60 50 40

Efficiency @ 1.85 GHz Gain @ 1.85 GHz Efficiency @ 1.95 GHz Gain @ 1.95 GHz Efficiency @ 2.15 GHz Gain @ 2.15 GHz Efficiency @ 2.45 GHz Gain @ 2.45 GHz Efficiency @ 2.65 GHz Gain @ 2.65 GHz

30 20 10 0 25

30

35

40

45

50

55

Pout (dBm)

Figure 2.33 Test performance of high-power broadband inverted Doherty amplifier greater than 54 dBm with a drain efficiency of greater than 65%, a linear power gain of greater than 13 dB and a drain efficiency of greater than 50% at 7-dB power backoff in a frequency bandwidth of 1.8–2.7 GHz were obtained [51].

References [1] Grebennikov A., and Bulja S. “High-efficiency Doherty power amplifiers: historical aspect and modern trends.” Proc. IEEE, 2012, vol. 100(12), pp. 3190–3219. [2] Pengelly R.S., Wood S.M., Milligan J.W., Sheppard S.T., and Pribble W.L. “A review of GaN on SiC high electron-mobility power transistors and MMICs.” IEEE Trans. Microw. Theory Tech., 2012, vol. 60(6), pp. 1764–1783. [3] Pengelly R., Fager C., and Ozen M. “Doherty’s legacy: a history of the Doherty power amplifier from 1936 to the present day.” IEEE Microw. Mag., 2016, vol. 17(2), pp. 41–58. [4] Doherty W.H. “A new high efficiency power amplifier for modulated waves.” Proc. IRE, 1936, vol. 24(9), pp. 1163–1182. [5] Raab F. H. “Efficiency of Doherty RF power-amplifier systems.” IEEE Trans. Broadcast., 1987, vol. 33(3), pp. 77–83. [6] Iwamoto M., Williams A., Chen P.-F., Metzger A.G., Larsson L.E., and Asbeck P.M. “An extended Doherty amplifier with high efficiency over a wide power range.” IEEE Trans. Microw. Theory Tech., 2001, vol. 49(12), pp. 2472–2479. [7] Kim J., Fehri B., Boumaiza S., and Wood J. “Power efficiency and linearity enhancement using optimized asymmetrical Doherty power amplifiers.” IEEE Trans. Microw. Theory Tech., 2011, vol. 59(2), pp. 425–434.

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[8] Yang Y., Cha J., Shin B., and Kim B. “A fully matched N-way Doherty amplifier with optimized linearity.” IEEE Trans. Microw. Theory Tech., 2003, vol. 51(3), pp. 986–993. [9] Takayama Y., Harada T., Fujita T., and Maenaka K. “Design method of microwave Doherty power amplifiers and its application to Si power MOSFET amplifiers.” Electron. Commun. Jpn. Part II: Electronics, 2005, vol. 88(4), pp. 9–17. [10] Kim J., Cha J., Kim I., and Kim B. “Optimum operation of asymmetrical-cellsbased linear Doherty power amplifiers  uneven power drive and power matching.” IEEE Trans. Microw. Theory Tech., 2005, vol. 53(5), pp. 1802–1809. [11] Kim I., Cha J., Hong S., et al. “Highly linear three-way Doherty amplifier with uneven power drive for repeater system.” IEEE Microw. Wireless Comp. Lett., 2006, vol. 16(4), pp. 176–178. [12] Moon J., Kim Ja., Kim I., Kim Ju., and Kim B. “Highly efficient three-way saturated Doherty amplifier with digital feedback predistortion.” IEEE Microw. Wireless Comp. Lett., 2008, vol. 18(4), pp. 539–541. [13] Cho K.J., Kim W.J., Stapleton S.P., et al. “Design of N-way distributed Doherty amplifier for WCDMA and OFDM applications.” Electron. Lett., 2007, vol. 43(10), pp. 577–578. [14] Kim W.J., Cho K.J., Stapleton S.P., and Kim J.H. “N-way Doherty distributed power amplifier.” U.S. Patent 7,688,135, March 2010. [15] Wong J, Watanabe N., and Grebennikov A. “Efficient GaN Doherty amplifier peaks at 1 kW from 2.11 to 2.17 GHz.” Microwaves RF, 2017, vol. 56(5), pp. 64–69, 149. [16] Srirattana N., Raghavan A., Heo D., Allen P.E., and Laskar J. “Analysis and design of a high-efficiency multistage Doherty power amplifier for wireless communications.” IEEE Trans. Microw. Theory Tech., 2005, vol. 53(3), pp. 852–860. [17] Neo W.C.E., Qureshi J., Pelk M.J., Gajadharsing J.R., and de Vreede L.C.N. “A mixed-signal approach towards linear and efficient N-way Doherty amplifiers.” IEEE Trans. Microw. Theory Tech., 2007, vol. 55(5), pp. 866–879. [18] Pelk M.J., Neo W.C.E., Gajadharsing J.R., Pengelly R.S., and de Vreede L. C.N. “A high-efficiency 100-W GaN three-way Doherty amplifier for basestation applications.” IEEE Trans. Microw. Theory Tech., 2008, vol. 56(7), pp. 1582–1591. [19] Gajadharsing J., Neo W.C.E., Pelk M., de Vreede L.C.N., and Zhao J. “3way Doherty amplifier with minimum output network.” U.S. Patent 8,022,760, September 2011. [20] Kim B., Kim I., and Moon J. “Advanced Doherty architecture.” IEEE Microw. Mag., 2010, vol. 11(5), pp. 72–86. [21] Kim I., Moon J., Jee S., and Kim B. “Optimized design of a highly efficient three-stage Doherty PA using gate adaptation.” IEEE Trans. Microw. Theory Tech., 2010, vol. 58(10), pp. 2562–2574. [22] He J., Zhang T., Zhang Y., Wang Y., Zhang B., and Gajadharsing J. “A 500-W high efficiency LDMOS classical three-way Doherty amplifier for base-station

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Chapter 3

Envelope tracking techniques Florinel Balteanu1

The growing demand for high data rate cellular systems has pushed the adoption for 4G/5G long-term evolution (LTE) which uses high peak-to-average power (PAPR) modulation schemes with rapid deployment and replacement. 5G will bring high data capacity and low latency using sub-6 GHz and mm-Wave spectrum, with the first deployment using sub-6 GHz bands. The increased adoption of powerful worldwide smartphones has been in part possible due to increase of CMOS technology in lower feature nodes as FinFET 7 nm/14 nm [1–7]. This has made also possible to essentially enhance RF CMOS through digital signal processing (DSP) and digital calibration which are part of smartphone modem and application processor. Also, this has made possible the adoption of an “old” techniques such as envelope tracking (ET) into smartphone. The ET technique was mentioned back in 1952 [8] by Leonard R. Kahn who introduced a related technique envelope elimination and restoration (EER). Envelope tracking improves the linearity and efficiency RF for power amplifier. The RF power amplifiers are typically the most power-hungry components and take a lot of area in a wireless transmitter. With explosive band proliferation as well as the use of carrier aggregation (CA) and multiple input multiple output (MIMO) techniques, the research area of improving the cost, size, and the performance of RF transmit solution is very active with many developments and product deployment over the last years. The performance metrics for a wireless transmitter are the following: ● ●

●

●

●

1

Efficiency at different power levels—Eff; Coexistence for transmitter and receiver as expressed as receive band noise in FDD systems at duplex space—RxBn; Coexistence with close adjacent similar transmitters expressed through adjacent channel leakage power ratio ACLR and spectral mask; Coexistence with radios transmitters expressed through ACLR, RF spectral mask, and noise; and Operation with efficiency at low power levels and reduced memory DSP requirements.

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3.1 Envelope tracking technique A number of techniques have been used to meet linearity and efficiency challenges, the most extensively used and researched are Doherty power amplifier [8,9] and envelope tracking (ET) [10–12]. Doherty techniques provide high efficiency but have limitation in terms of broadband operation [13,14] and load mismatch operation [15] compared with ET techniques [10,16–26]. In mobile applications, such as smartphones, ET is used with a broadband PA for low, middle, and high bands together with antenna tuners [27]. In ET technique the power supply voltage delivered to a RF PA is following the envelope signal (Figure 3.1) through a shaping table circuit and therefore provides the required voltage for the PA to operate in linear region without clipping. If the supply voltage for the PA is kept constant as in conventional application called average power tracking (APT) the difference between the required voltage and the supply voltage multiplied by the PA current will be lost and dissipated without producing any useful RF energy as presented in Figure 3.2. This explains in a simple way why ET technique is able to improve the efficiency for a RF PA under variable envelope operation. The envelope signal as presented in Figure 3.3 carries the instantaneous power information and is expressed by pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi (3.1) EnvðtÞ ¼ I 2 ðtÞ þ Q2 ðtÞ The envelope bandwidth is higher than the bandwidth for individual components I(t) and Q(t) as presented in Figure 3.4. From this prospective the envelope tracking signal which is applied to the collector/drain of the power amplifier is shaped mainly to reduce the bandwidth and to flatten the AM-AM characteristic of the PA as presented in Figure 3.5. Vsupply

DC-DC

Envelope

Amp Vdd_trck

RF_out RF_in

PA

Figure 3.1 Power amplifier with envelope tracking

Envelope tracking techniques Supply voltage

139

Supply voltage

Envelope voltage

Envelope voltage

Figure 3.2 Power amplifier under APT and ET

I(t)

I(t)

0 RF(t) fRF

Env(t) ϕ(t)

90 Q(t)

I(Q)

Figure 3.3 Envelope signal

The cellular LTE bands as well as WiFi use complex digitally modulated signals, such as 16/64 QAM and place stringent demands on the RF power amplifier (PA) to achieve high efficiency and linearity for a wide power range and high peak-to-average power ratio (PAPR) signals as depicted in Figure 3.6. The cellular LTE bands use complex digitally modulated signals, such as 16/64 QAM and place stringent demands on the RF power amplifiers (PAs) to achieve high efficiency and linearity for a wide power range and high PAPR signals, as depicted in Figure 3.3. To increase the data stream bandwidth there are discussions to use 256 QAM modulation for LTE bands in 5G with up to 10.5 dB PAPR. Typically, to operate a power amplifier under high PAPR, the amplifier is operated under back-off mode which reduces the efficiency; for example, a WiFi PA operated at 256 QAM ends up with a power added efficiency (PAE) around 12%–15% [28].

Radio frequency and microwave power amplifiers, volume 2 0 –10 IQ signal Power spectrum density (dB/Hz)

140

–20 –30 Envelope signal –40 –50 –60 60 dB

–70 –80 –90 –15

–10

–5

5

10

15

Frequency (MHz)

Figure 3.4 Envelope signal versus I(t) and Q(t)

Envelope Shaping

shape

(I2 + Q2) Envelope Tracker

(I2 + Q2)

Baseband

I

L coupling

I

(I2 + Q2)

0

LO

Q

Driver Σ

RF_out

RF_in

90 Q

(I2 + Q2)

Figure 3.5 Envelope tracking system

ET Power Amplifier

Envelope tracking techniques

141

5G LTE WiFi 256QAM

Relative power dissipation

5

4G LTE 200RB

4 4G LTE 100RB 3

4G LTE QPSK

2 WCDMA GSM 1

1

2

3

4

5

6

7

8

9

10

11

Peak-to-average power ratio (dB)

Figure 3.6 Relative power dissipation versus PAPR

3.2 Envelope tracking for cellular LTE FDD and TDD TDD LTE systems with asymmetrical uplink/downlink ratio (such as 1/3) stress more the transmit uplink chain. In this scenario the bandwidth requirements for TDD-LTE to have the same uplink data stream throughput is at least five times higher assuming the required gaps in uplink TDD. Therefore at least 40 MHz TDDLTE bandwidth is required to reach a similar peak bandwidth as for 10 MHz FDDLTE, as depicted in Figure 3.7. Noise power is proportional to bandwidth and therefore the TDD power required to have the same signal to noise ratio (SNR) as in FDD is given by PoutTDD ¼ PoutFDD þ 10 logðBw ratioÞ

(3.2)

From (3.2) in LTE-TDD operation the PA has to deliver 27 dBm to achieve the same SNR as a 20 dBm LTE-FDD signal, assuming the same propagation environment. From this perspective for higher modulation bandwidth the PA operates most of the time at peak power as compared with 3G WCDMA systems where the PA operates in back-off mode and for this reason using ET is required to improve the efficiency.

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Radio frequency and microwave power amplifiers, volume 2 FDD_LTE

uplink

TDD_LTE

downlink

uplink

downlink

downlink

SNR Noise

Figure 3.7 FDD/TDD LTE uplink/downlink schedule

3.3 Power amplifier under envelope tracking operation A typical PA structure is presented in Figure 3.8. The efficiency is given by   Pout Re V load  I load h¼ ¼ (3.3) 2  V dd  I dd Pdc In order to maximize the efficiency of the PA the source degeneration has to be minimized. In general PAs are classified in three classes according to their mode of operation: ●

●

●

linear mode when the active device is operated in the linear portion of the active device; critical mode when the operation for the active device extends beyond the linear portion up to saturation and cut-off regions; and nonlinear mode when the active device current cease to flow during a portion of each cycle, with a duration that depends on the bias.

In nonlinear mode as the input power continues to increase the amplifier goes into compression where no further output power increase occurs. For high efficiency operation the third-class PA are used because the presence of harmonics contributes to higher efficiency. Depending on the PAPR a linear PA is operated in back-off mode from compression as in Figure 3.9. The PAE for the Waterfall Curve [29,30] is given by the formula:  Vkn  (3.4) PAEðVdd Þ ¼ Eff ideal 1  Vdd

Envelope tracking techniques

143

Vdd Idd

R_lopt

RF_in

Input Impedance Match

RF_out

Output Impedance Match

Vload Iload

M1 Rload

Ground Connection

Figure 3.8 FDD/TDD LTE uplink/downlink schedule

Psat

p1 p2 PAPR-3dB

PDF (%)

PAPR-5dB

Efficiency (%)

p3

Output power (dBm)

Figure 3.9 Power probability and efficiency for PAPR for constant Vdd where Eff_ideal is the peak/ideal efficiency and Vkn is the knee voltage for the active device as presented in Figure 3.10. Increasing Vdd voltage (until the device reaches the avalanche region) will increase the PAE. This is valid for GaAs HBT as well CMOS devices, although Vdd can be higher for GaAs devices. The slope of the PAE versus Vdd is determined by several factors such as capacitive loading ( fcV2) as well as biasing at peak Ft. In general GaAs HBT devices exhibit a higher Eff_ideal but steeper slope compared with CMOS devices. The relation between Idd and Vdd for an active device provides the load line of the amplifier and the load resistance Rload [31,32]. In linear mode, such as Class A for PA, the load line is

144

Radio frequency and microwave power amplifiers, volume 2 Idd (mA) I2

Knee (triode) region

Punchthrough region

2

Imax

R_lopt

1 3 Vkn

Vdd

Vds (V) V2 2×Vdd

Figure 3.10 Power amplifier load line Table 3.1 Pout versus Vdd Vdd (V)

Rlopt (ohm)

Pout (dBm)

2.7 3 3.3 4 4.5 3 3.5

5 5 5 5 5 4 4

26.8 27.9 28.9 30.8 32.1 32.0 33.5

determined by the slope of the Idd(Vdd) curve. In Class B mode when the device conducts 180 the load resistance and the output power is given by Pout

max

¼

ðV dd  V kn Þ2 2Rlopt

(3.5)

where Rlopt is the optimum impedance which has to be matched at the output load through the marching network. Table 3.1 presents the output power for different voltage supplies, assuming a knee voltage Vkn  0.5 V. When the device is turned on and conducts, such as in Class E and F, the load line is determined by conduction angle as well the time of conduction. There is an analytical formula for these cases, but for ET operation the optimal Rload is obtained through load pull and large signal simulations [32]. During ET, Vdd is changing and therefore the optimum load line for power transfer is changing as well, as depicted in Figure 3.10 and

Envelope tracking techniques Output power (efficiency)

145

ET trajectory Vdd1 < Vdd2 < Vdd3 < Vdd4

APT trajectory Vdd4 Vdd3

Vdc_dc_rms

Vdd2 Vdd1

V_m

Input power

V_M

Figure 3.11 Voltage supply trajectory and efficiency for Vdd changes 0

Efficiency loss (%)

2 4

Power Amplifier PAE (%)

6 8

35 40 45

10

55 55

12 0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Output match loss (dB)

Figure 3.12 Power amplifier efficiency losses as back-off the envelope we can use (4). During ET operation the PA is presented with instantaneous voltage supply Vdd as presented in Figure 3.11. Typical power amplifier are fabricated in GaAs HBT technologies where a semi-insulating substrate is used so devices fabricated will have reduced parasitic capacitances and higher fT devices. Also, GaAs technologies usually feature backside TSVs that connect the front side metallization of the die to the backside ground plane. These features provide a low impedance path to the common ground plane and a good thermal conductor. In order to deal with these limitations, a CMOS PA designs have tried to use flip-chip techniques or transformers as well as laminate substrate for output matching networks to minimize the losses in the output match. For high efficiency PA any 0.1 dB loss translates into 1% efficiency loss, as depicted in Figure 3.12. Table 3.2 presents the losses [33] due to the output match for different materials used for a PA matching network in band 7 (2.5 GHz).

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Radio frequency and microwave power amplifiers, volume 2 Table 3.2 Measurements results Substrate material

Insertion loss for band 7–2.5 GHz

CMOS High res CMOS SOI Laminate Glass IPD

1.3 dB 0.4 dB 0.35 dB 0.2 dB 0.15 dB

3.4 Envelope tracking systems ET is an old technique [4] which has made inroads recently due to increasing power for digital integration with the low feature CMOS nodes such as 28 nm/14 nm. As presented in Figure 3.13 ET is distributed between tracker itself and the system-onchip (SOC), comprised of modem, transceiver, and application processor. Using the ET technique, the power supply provided to the PA is actively changed in accordance with envelope of the RF signal. Doing this will reduce the headroom for PA to the required instantaneous Vdd for normal operation and therefore increase the efficiency. The mapping of instantaneous RF amplitude to the ET controller is defined digitally in SOC by a shaping table, usually for constant gain [7,11]. The shaping table can be designed to de-crest the PA and increase the efficiency even more and can be changed to trade off linearity and efficiency based on the probability density function (PDF) of the LTE signal as in Figure 3.14. A hard de-crested or hard de-through shaping table [34] will decrease the linearity which might be a problem for EVM, especially in the WiFi ET case. The basic architecture used for an ET system combine the DC voltage provided by a DC–DC converter with the fast, variable envelope signal through an error amplifier, as presented in Figure 3.15. This architecture is called hybrid architecture and is the most used ET architecture. The error amplifier can be AC or DC [35] connected to the output each with its own pros and cons. The most efficient way is with AC coupling of the error amplifier. For an ET AC coupling system [36–39] there is the need to use a DC tracking loop which provides envelope tracking at low frequencies, making them slightly more complex. The AC systems have better efficiency and work better for LTE TDD cases. The main part of the energy provided to the Vdd terminal of the PA is delivered by DC–DC converter (around 80%) with the rest delivered by the fast error amplifier (around 20%), as shown in Figure 3.16. The envelope reconstruction through two paths, one for low frequency (DC–DC) and one for high frequency (Fast Error Amplifier) is not perfectly aligned in time and therefore there is no flat gain and phase response over frequency of the envelope signal. This effect is present in both DC and AC coupling configurations. There is also an interaction from the error amplifier operation and DC–DC switching operation; the error amplifier requires a lower capacitor load Cfil to operate at the modulation

Vbatt

Envelope tracking system

SOC

CORDIC SQR(I^2+Q^2)

Drivers

Analog Buffer

LUT Shaping

Envelope Envelope

DAC

Envelope Envelope Tracker Tracker

Antenna VCC_PA_t Vdc_trck rck

Delay

Antenna Tuner

I(t)

I(s) Baseband TX

SPI SPI

DAC Delay

Q(s)

flo

DPD

RF_in RF_in 90

RF_out RF_out Coupler Power Power Amplifier Amplifier

DAC Q(t) Feedback (Observation) Receiver

I(s)

Q(s)

MIPI SPI

SPI

Ifdbk(t) IMn

s

IMn

I(s)

A/D

Q(s)

A/D

Qfdbk(t)

flo

Fwd_cpl Rev_cpl

BW= 3×–5× SignalBW

Tuner Control

Controller Controller

SPI

Figure 3.13 Envelope tracking structure

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Radio frequency and microwave power amplifiers, volume 2

ET_Voltage (V)

Vmax

Vdc_dc

Vdd RMS Waveform PDF

Vmin Vknee

Input power

Power bin (dBm)

Figure 3.14 Envelope shaping form

Laux

Cdc

ET combiner

Auxiliary DC-DC Vbatt

Vdc_dc

DC-DC Ldc_dc Hysteretic Control

Lpa

Drivers Cfil Cpa

MIPI SPI

Cac

Digital Control Amplifier

Vdc_trck C_pa_fil

Env_p IQ Amplitude DAC

Env_n

Envelope Supply

Envelope RF_in

RF_out

Figure 3.15 Envelope tracking controller bandwidth required. A low capacitor load requires a higher switching frequency for DC–DC and therefore higher losses. This configuration generates switching noise which propagates through the RF PA. One way to significantly reduce the switching noise and reduce the interaction from DC–DC and error amplifier is to split the DC–DC output inductor into a LCL ET combiner [36,37] as presented in Figure 3.17.

Envelope tracking techniques Fixed DC

149

80% Envelope

Vbatt

Variable Env 15%–20%

Figure 3.16 ET energy transfer

Vdc_dc

DC-DC Ldc_dc

Lpa Vdc_trck Rload

Cfil

Envelope

Cpa Cac

Fast tracker

RF_in

RF_out

Figure 3.17 ET combiner The fast tracker sees the Rload of the RF PA as the load in parallel with high impedance at baseband modulation frequency provided by isolation inductor Lpa. The DC–DC can also work on a high Cfil capacitor reducing the switching noise and isolating from the interaction with the error amplifier. This configuration can be used for multiple PAs working with ET and sharing the same DC–DC such as in uplink CA, as presented in Figure 3.18. Using a single output from the DC–DC requires a mechanism to adjust/tune the PA load line for the same Vdc_rms, which is easier using CMOS SOI compared with GaAs HBT.

3.5 Envelope tracking circuitry The more detailed ET circuitry is presented in Figure 3.19. The DC–DC part of the ET system sets the optimum voltage supply Vdc_dc for the PA and is used for backoff mode of the PA. For high modulation bandwidth, as well for TDD-LTE, the PA is used most of the time at full power and there is no need to optimize the power consumption for back-off mode. The location of the error amplifier relative to PA, as presented in Figure 3.5 as L coupling [26], has an impact on the intermodulation distortion as shown in Figure 3.20 as well as the increased PA memory effects and noise for high modulation LTE signals (10 MHz, 20 MHz, and 40 MHz).

Vbat

Vdc2

Vdc1

Lm_pa_ex

MIPI SPI

PMIC DC-DC

Front End Low Band Mid Band

Cfil2

Lm_pa

Vdc_trck1

Cfil1 ET combiner

RF_in

Vdc_dc

C_trk

Vdc_ctrl

Vdc_dc

Vdc_trck1

C_ac

CMOS PA B7, 38, 40, 41

Vdd

ByPass Sw

MB Sw

Gnd

Rx_B7

Tx_B41 Tx_B38

T/R

T/R

B41

HB_LTE

B38

Gnd

Gnd Fast Track

Env_n

RF_out

B7

Duplexer

Tx_B7

RFout

Tx_B40

T/R

B40

MIPI RX_SW

VIO

Sdata

Sclk

Digital Env_p

Envelope

LB/ MB_LTE

WiFi Notch

Rx_B38, B41 Rx_B40

LNA

Antenna Switch

2.3GHz-2.7GHz LTE Front End

Figure 3.18 High band 2.3 GHz–2.7 GHz front-end module

Envelope tracking techniques Vref_dc_dc

DC-DC

Ldc_dc

8 DAC DAC_ref

ET combiner Vdc_dc

Cfil Voffset_ctrl

Ihi

a1

Hysteretic Current comparator

Vdc_trck

I sense

kp Ilo

Cf

Env_p

Lpa Cpa

Vcor

Rf

Error Amplifier

V2

2R2

Is_n

a2

Env

Vcac

V3

Cac Fast Tracker

Is_p

R1

Env_n

151

2R2

Differential Amplifier

Offset Control

Figure 3.19 Envelope tracking structure –40 10 MHz –60

20 MHz 40 MHz

IM3 – (dB)

–80 –100 –120 –140 –160

0

5

10

15

20

25

30

Lcoupling – (nH)

Figure 3.20 Intermodulation distortions versus coupling inductor The envelope signal is provided usually by the modem as presented in Figure 3.13 and uses a differential signal [40] to allow noise common mode rejection and to avoid any offset calibration (Figure 3.21). The ET has to provide a single ended signal to the PA power port and therefore doing this and there is the requirement of a differential to single ended circuit to process the envelope signal. One method to convert the differential analog signal into a single ended signal is presented in Figure 3.22 which is using a dual input transconductor circuit.

152

Radio frequency and microwave power amplifiers, volume 2 Envelope Env_p

V_cm

Env_n

Time

Figure 3.21 Envelope differential input signal Input filter Env_p Rf

Cf

Gm_in

a1 Env

Env_n C

I0

R1

Gm_fbk Gain

Common mode setting

R2

R3

Figure 3.22 Envelope input differential to single ended circuitry This stage is used also to set the common mode voltage for the output stage which is the core for the error amplifier. The detailed of the circuit is presented in Figure 3.23, both inputs use the same architecture based on a input where the differential current is approximatively determined by DI ¼

Vin

p

 Vin R

n

(3.6)

To increase the transfer function precision for the input transconductor conversion an input circuit as presented in Figure 3.24 can be used. This circuit improves the precision of the input transconductor which is determined just the input resistor matching, also improves the linearity of the input stage. The post gain after the input stages should be high enough to provide enough open loop gain for DC common mode rejection. The single ended envelope signal feeds an error amplifier which uses class AB amplifier with degenerated input (Figure 3.25) to increase the slew rate (SR) of the amplifier.

Envelope tracking techniques

153

Vdd M7 Ibias

Ibias

M8

Ibias_AB Mp

R R

Vin_p_fd

Vin_n_fd

Class AB Bias

Out

M3 M4 M1 M2 Vin_p

Vbias

Vin_n

M5

M6

a1

Mn

Figure 3.23 Dual transconductor circuit

Ibias1

Ibias1 R

Vin_p

M1

Vin_n

M2

Ibias2

Ibias2

Figure 3.24 Linear transconductor input The overall SR of the amplifier is determined by the minimum of input SR and the output SR. The input SR rate is SRin ¼

2Ibias Csl

(3.7)

154

Radio frequency and microwave power amplifiers, volume 2 Vdd M5i Ibias_AB ctrl_p

Mp

Psense

Ibias

Ibias

Is_p Vin_p

Rb M1

Class AB Bias

Vin_n

Cc Out

M2 Vbias

M3

M4 Cc

Is_n

Mn a2 Is

ctrl_n Nsense

Csl

Figure 3.25 Class AB error amplifier The output SR is determined by the maximum variation of the output voltage swing over time and is dependent of the Cpa and the PA load line Rlopt. For a typical amplifier the SR is determined by the input SR; however, for an ET system the load seen by the amplifier has few ohms and the output SR is lower and is the dominant factor for SR. The maximum frequency Fmax for which the error amplifier has an undistorted signal is given by Fmax ¼

SR 2pVoutpk

(3.8)

where Voutpk is the peak voltage for the output envelope signal and is determined by the maximum power which has to be delivered under ET for different PAPR waveforms. The error amplifier should operate at the output on a load which is changing with the power level and therefore the stability conditions can change. Because the output load is low and is determined by the load line of the PA increasing the SR requires an increase on the input current which will determine also an increase of the open loop gain and therefore push the amplifier into instability. To alleviate this one method is to add a degeneration resistor at the input stage. The class AB output stage is set to have a quiescent current using a schematic as shown in the Figure 3.26. A higher quiescent current will determine fewer distortions but will increase the current and decrease the efficiency for the error amplifier. Also, different quiescent currents can be set when the ET is operating at different LTE modulation bandwidths. Ibias_n and Ibias_p set the operating points for the output transistors PFET_out and NFET_out. Choosing the ratio for Ibias_n /Ibias_p as well the individual values determine the amplifier distortion which is part of overall ET intermodulation products and therefore can determine

Envelope tracking techniques

155

Vdd M3

Ibias_n

M4 PFET_out Ctrl_n OUT

Mn Mp Ctrl_p NFET_out M1

M2

Ibias_p

Figure 3.26 Class AB error amplifier bias circuits

VDD M1

M2

Vbias1 PFET_out M3

M4 Class AB Bias

OUT

Vbias2 M5

M6 NFET_out

gm

Figure 3.27 Class AB amplifier output stage detail One of the methods to increase the gain for the error amplifier stage is to use several servo amplifiers as presented in Figure 3.27. This method decreases the error amplifier gain dependence due to Vds. The servo amplifier maintains the voltages on the cascode devices to be approximatively the same during large signal

156

Radio frequency and microwave power amplifiers, volume 2

operation and therefore keep the transfer function constant. The internal structure for this servo amplifier is shown in Figure 3.28 and doesn’t include any compensation capacitors. This method is useful for relatively lower operation frequency due to extra delays introduced. Also the servo amplifiers take extra current and therefore increase the overall current consumption. The output power train has two sense transistors which provide the Isense current into a hysteretic current comparator. The hysteretic comparator output controls the low frequency envelope signal through the DC_DC control reference control pin (Figure 3.19). The offset control circuitry for the error amplifier is presented in Figure 3.29 and provides the bias required to keep the AC coupling capacitor at the desired voltage. This voltage is the difference between PA Vdc_rms and the error

Ibias

Ibias

M1

V_p

M2

V_out

V_n

Figure 3.28 Class AB servo amplifier

Vdc_trck

2R

– +

Error amplifier

Env

Cac Ri

a2

R

2R

Rc

gm

Ci

Ictrl Rc Vset

gm

+ –

Figure 3.29 Offset control circuitry

Reference

Envelope tracking techniques

157

amplifier common mode voltage. The offset control circuitry consists from a slow integrator and two gm stages which set the current through integrator. One of the gm stages senses the voltage on the AC capacitor and this voltage is compared with a reference voltage which is applied to the second gm stage. For start-up condition and TDD mode there is an additional start-up circuit which speeds up the control [41]. Usually the frequency response for the error amplifier is limited by the compensation capacitor. In ET case the amplifier should be compensated for different resistive loads due to impedance presented by the PA at different PA levels under a high PAPR signals. To increase the frequency response for the error amplifier one of the methods is to use a current feedback amplifier (CFA) approach as presented in Figure 3.30. The SR for CFA is increased compared with the voltage feedback amplifier (VFA). The closed loop gain for the amplifier working under ET conditions is changing due to PA impedance presented at Vdd port for a voltage feedback amplifier which is not the case for a CFA. This explains the increase in SR for the current mode approach. One of the problems with the CFA which is not the case for a VFA is the voltage gain precision and the bias current on the negative input of the amplifier determines a significant offset. One method to alleviate the bias current is presented in Figure 3.31. Under ET condition the PA operates close to compression for a short period of time, and most of the operation is in the linear mode (Figure 3.32). In order to provide broadband characteristic the PA used for ET typically is using a class-E structure with additional third harmonic 3fo trap as shown in Figure 3.33. The class E

Vdd_high Vdd M7i

M16i

Ibias3

Ibias1

Mp

M14

M3

M1

M9

M11

Ibias

M5 Class AB Bias

Itrans

Vin_p

M2

M4

M6 M10

Vin _ n

M12 M15

Mn

Ibias4

Ibias2

M8i Vctrl

Figure 3.30 Current feedback amplifier

M17i

out

Ib=0

Vin_p

Current feedback amplifier Out

Ibias

Vctrl Vin_p R1

R2

NxR1

NxR2

Figure 3.31 CFA offset compensation circuitry Compressed

Envelope shaped

Linearity optimized shaping Linear

Input envelope

Figure 3.32 PA operation regions under ET

Vdc_dc Lpa

ET combiner

Cpa Vdc_trck

Isense

Cac

Class E L RF_out

Envelope 2fo

Error Amplifier RF_in

C Q

Vbias

Cp 3fo PA Module

Figure 3.33 Power amplifier class E output stage with error amplifier

Envelope tracking techniques

159

power amplifier concept has been introduced in [42]. The optimum series feed inductance L and parallel capacitance C can be obtained by L ¼ 0:732 C¼

R w

(3.9)

0:685 wR

(3.10)

The optimum load line Rlopt for the specified values of supply voltage Vdd and the output power Pout can be calculated as Rlopt ¼ 1:365

V 2dd Pout

(3.11)

During ET operation Vdd is dynamically changed and therefore Rlopt is different, therefore as an approach the Rlopt is determined through load pull [32], being a value closer to the value defined in (3.5). Equations (3.9)–(3.11) provide the design values, which need to be optimized, especially for high PAPR waveforms. One of the Class E power amplifiers characteristic is the high Vpeak on the active device. Theoretically Vpeak and Ipeak [31,42] are given by the relations: Vpeak ¼ 3:647  Vdd

(3.12)

Ipeak ¼ 2:647  Io

(3.13)

where Io is the load current. In reality, the voltage peak is lower due to operation in nonideal Class E conditions as well the operation not close to PA compression.

3.6 Envelope tracking for high power With the adoption of 5G where two or more transmitters are active at a time the linearity requirements such as ACLR and noise are tightened. Adjacent channel interference ratio (ACIR) is the total leakage between two transmitters on adjacent channels which depends on ACLR and adjacent channel selectivity (ACS) as defined by ACIR ¼

1 1 1 þ ACLR ACS

(3.14)

To increase ACIR is desired to have an ACLR better than 38 dBc, usually lowered to 45 dBc using ET and DPD. Figure 3.34 presents the power budget for FEM transmit path, the loss for this path typically being around 3 dB. This loss increases for 5G application when a diplexer (0.3 dB) and/or a dual pole dual through (DPDT) silicon on insulator switch are added. The LTE power delivered at the antenna required by 3GPP standard is 23 dBm and assumes 3 dB loss due to filters/duplexers, switches, diplexers, and board losses. The PA has to deliver at least 26 dBm for LTE 20 MHz. For LTE 5G, there is an increase from 20 MHz to 40 MHz/60 MHz for the modulation uplink bandwidth

Radio frequency and microwave power amplifiers, volume 2 Total Loss Output Matching network

Band Switch

Tune Route

RF_in

RF_out

3 dB

Match

Tune Route

SOI

PA

0.3

Antenna Switch

Coupler

Vdc_trck

Duplexer

160

SOI

0.25

1.4

0.15

0.1

0.6

0.2

Figure 3.34 Front-end module power loss budget

as well as an increase in antenna power with 3 dB to 26 dBm for high power user equipment (HPUE) for some bands which allows for a better-balanced downlink and uplink coverage in TDD. Based on (3.5) increasing the power delivered by the PA to 31 dBm will require the increase of the voltage supply and the decrease of the load line. If the PA is operated in ET mode Vdd ¼ Vdc_trck is changing based on the envelope (instantaneous power level). The Vdc_trck_peak is the peak voltage and is determined by the maximum power which has to be delivered under ET for different PAPR waveforms:   Vdc trck peak (3.15) PAPR ¼ 20 log Vdc trck rms To reduce the peak voltage requirement and increase the load line an ET architecture as presented in Figure 3.35 can be used. This architecture can support high power ET applications such as HPUE. The output SR is determined by the output voltage swing over time and is dependent of Cpa and Rload. For a high-power PA, the Rload is very low (3.5) and will be the dominant factor for the error amplifier SR. To increase the maximum frequency to 40/60 MHz and to increase of the output power for the PA the structure is split into two identical sections having two error amplifier output stages, two identical PAs, and a class E PA output match combiner, as presented in Figure 3.36. Assuming Rload 5.5 ohm for each PA as shown in Figure 3.37 for three envelope tones set at 2 MHz, 43 MHz, and 45 MHz the peak load voltage reaches 8 V operating over 5.5 ohm load. Vdc_dc is set at 5.5 V. Considering (3.5) and assuming Vkn ¼ 0.5 V the peak power which can be delivered by one PA under ET operation is 37 dBm. For PAPR of 8.5 dB for LTE 40 MHz and 0.3 dB loss in the output matching/combiner network the linear power delivered by one amplifier is 28.3 dBm: Pout

lin

¼ Ppeak  8:5 dB  0:3 dB ¼ 28:3 dBm

Pout ¼ Pout

lin

þ 3 dB ¼ 31:3 dBm

(3.16) (3.17)

Envelope tracking techniques

161

DC-DC Vbat

Lpa1

Ldc_dc

Vdc_trck1

Cfil

Vdc_dc Rload1

Cpa1

Vctrl

Cac1 FT Amp1

Envelope

Matching RF PA1 Combiner/ RF PA2 Matching

RF_in

RF_out

Matching Power amplifier FT Cac2

Amp2

Vdc_trck2

Rload2

Cpa2

Lpa2

Figure 3.35 ET for high power applications

Lb1

Vdd_trck1

L11

Rb1

C31

M1

Rb2

C11

C21

Cin1

Combiner/ matching

M2

Vbias_1

RF_out

L2 Rbias1 Vdd_tck2

Harmonic Trap

Lb2 L12

Rb3

RF_in

C32

L3

M3 C12

Rb4 Cin2

C22

L4

C4

M4

Vbias_2 Rbias2

Figure 3.36 Dual ET PA with class E output match/combiner For two PA systems as shown in Figure 3.36 the output power which can be delivered is 31.3 dBm. Increasing the transmit power improves the data rate capacity C for transmission channel as expressed by Shannon formula:  S (3.18) C ¼ Bw log2 1 þ N

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Radio frequency and microwave power amplifiers, volume 2

Output load voltage, V

8 7 6 5 4 3 2.5

3 Time, µs

3.5

Figure 3.37 ET measurements for three-tone envelope signal (2 MHz, 44 MHz, and 45 MHz) for Rload ¼ 5.5 ohms

3.7 Local ET linearization In order to provide broadband characteristic, the CMOS PAs are using a class-E structure with additional third harmonic 3fo trap [33,42,43]. To improve the PAE and linearity these PAs are integrated on the same die with the ET [18], as shown in Figure 3.38. The ET works together with a buck DC–DC converter, providing approximately 15%–20% of the power required by the PA. For an output power of 26.5 dBm the buck DC voltage Vdc–dc is set at low DC voltage and provides the 80% of the PA power with more than 94% efficiency. This low DC voltage provides protection for CMOS devices, but it does require the PA to operate with low load line. The envelope signal is used to dynamical bias of the top cascode transistor and keeps the main RF gain transistor M1–M1i in the constant gm region. This presents a local ET linearization effect. The dynamic bias loop Rb1, Rb2 Csc, and M2-M2n provides a DC ET loop for the RF power transistor core M1–M1i and linearize the RF gain operation. The ET linearization has been observed and described in several papers [1,44,45] and is more pronounced for CMOS devices compared with GaAs HBT due to strong dependence of the gm and Id in relation to VDS. For CMOS the relation between drain current and voltage is given by 1 W (3.19) ID ¼ mCox ðVGS  VTH Þ2 ð1 þ lVDS Þ 2 L The small signal output impedance of the cascode structure is dependent of the impedance presented at the drain of M2-M2i and strongly dependent of impedance presented by M1-M1i: Rout ¼ ð1 þ gm Rout 2 ÞRout 1 þ Rout

2

(3.20)

Envelope tracking techniques Ldc_dc Vdc_dc Envelope

Tracker

163

Vdc_dc Cfil

Lpa

ET combiner Cpa

Cac

Vdc_trck

Rb1

Output match

M2

Local ET

fdbk

Rb2

M2n

Cb2 Vbias1

Input match

RF_out

Cb1

Dynamic bias

RF_in

Lm

Vbias2 Vds M1

M1n PA core

Figure 3.38 CMOS PA and ET on the same die

where R1 is the output impedance presented by M1-M1i. The Early Voltage expressed through l is lower in CMOS than for GaAs HBT and therefore the linearization mechanism is stronger for CMOS PAs. Also, without a linearization mechanism CMOS PAs have lower linearity compared with traditional GaAs HBT PAs. The RF PA core M1-M1n is using a DC tracker linearizer and from this perspective there is constant frequency and phase response for the PA core and the result is a very tight AM-AM and AM-PM. Through ET linearization the output impedance from the cascade structure is higher and therefore the AM-AM characteristic for linear region is independent of the voltage supply Vdd. The main tracker provides the AC path to the drain of the PA. This tracker has a very low dynamic load, determined by the load line of the PA in the range of 3–20 ohms. The amplifier load is changing the AC corner frequency and might alter the AM-AM of the PA. The second DC tracker, working as dynamic bias, alleviates this and improves the overall characteristic.

3.8 Multilevel supply envelope tracking The design of an efficient modulator is the main ET development. The most used architecture is the hybrid architecture which is free of ripple issues and has lower noise. On the other hand, for high PAPR new 5G signals using hybrid architecture is limited by the reduced bandwidth of the class AB error amplifier. Class D/G/H operation can be used to increase the efficiency of the linear modulator [46–50].

164

Radio frequency and microwave power amplifiers, volume 2

L_dc_dc

Cdc2

Vdc2

Ldc_dc

Vdc1 Cdc1

Vbatt

SPI

Multilevel supply Baseband MLS modulator Digital control

Lfil_1

Lfil_2

Cfil_1

Cfil_2

Cac

Control PA_Vdc_trck Envelope

IQ Amplitude

RF_out DAC

Rf_in

Figure 3.39 Multilevel supply ET with AC coupling The modulators based on class D/G/H amplifiers can have two or more voltage supplies and provide an envelope signal based on these discrete levels. The higher and lower supply levels are determined using (3.5) and calculated based on the maximum output power and the minimum power level. Ideally this method should use many supply levels but in practice it’s limited by the cost and size. The envelope can change based on the discrete levels and use a filter to restore the desired analog envelope waveform. Different combinations of two levels with PWM modulation, multiple levels, and hybrid modulators can be imagined and used. The most used structure is presented in Figure 3.39 where a DC voltage is combined with the variable part of the envelope (15%–20%) to provide the ET signal to the Vdd port of the power amplifier Vdc_trck. The baseband MLS modulator is followed by a programmable LCLC filter to reconstruct the variable part of the envelope. Based on the modulation bandwidth the filter is set but unfortunately there is not an optimum efficiency setting. The DC path of the modulator provides the core envelope energy and is used in APT mode to provide the DC RMS voltage for the required maximum output power. The modulator presented in Figure 3.39 can be used for other PA operating in the same time as the main PA which is the case for CA and MIMO.

3.9 Envelope tracking calibration The baseband envelope signal and the RF signal are provided separately to the ET PA and the delay mismatch between these two paths is a source of distortions [51].

Envelope tracking techniques

LTE 10 MHz

165

LTE 20 MHz

E-UTRA ACLR1 (dBc)

–30

–40 LTE 1.4 MHz –50

–5

–10

0 Delay mismatch (ns)

5

10

Figure 3.40 ACLR versus envelope delay mismatch

According to [52,53] the intermodulation distortion introduced by delay mismatch is given by IMDl;r ¼ 2pB2RF D2t

(3.21)

where BRF is the bandwidth of the RF signal and D is the delay mismatch. The minimum between left and right intermodulation distortion determines the ACLR of the ET PA and Tracker: ACLR ¼ minðIMDl;r Þ þ k

(3.22)

where k is a correction factor determined by PAPR and by how much in compression the PA is operated. A typical curve for ACLR versus delay mismatch is presented in Figure 3.40. For high data-bandwidth, such as LTE 20 MHz, the delay should be calibrated below 1 ns for an ACLR1 lower than 40 dBc. The delay mismatch calibration is done using the SOC feedback observation receiver, as depicted in Figure 3.41 through correlation techniques and ACLR and/or EVM feedback measurement. The ET PA is used in a front-end module with high Q acoustic filter such as SAW and BAW filters, as presented in Figure 3.41, and due to this reason the ACLR measurements are influenced by these filters. Also, ACLR and EVM measurements require a long calibration time. To accommodate these the most used method for calibration consist in applying a slow envelope signal which has to be aligned through convolution methods with a RF signal pushing the PA in compression. The RF signal can be applied as in Figure 3.42 together with an envelope signal. The delay calibration circuitry will try to equalize the two RF peaks which are detected by the observation receiver.

166

Radio frequency and microwave power amplifiers, volume 2 Look-up table Envelope

Delay

I

DAC

I(t)

ET Vdc_trck

0 Modulator DAC

Envelope tracker

BB filter

Q(t)

Rf_in

RF(t)

fc Q

Env(t)

DAC

Duplexer Coupler Rf_out

90 Driver BB filter

Power amplifier

Rx

fw

response

rv

Observation receiver

Figure 3.41 ET delay calibration system

Envelope RF_pk1 RF_in

RF_pk2

Figure 3.42 Delay calibration signals for envelope tracking

3.10 Envelope tracking noise During ET operation the PA provides an instant output power which is depended on both RF_in at the input of the PA as well the Vdd which provides the ET voltage for the PA. From this perspective the ET operation will add and degrade the noise at the output of the PA. Operating the PA close to compression will make the noise profile for envelope signal to be very clean due to RF up-conversion effects. The most challenging case is for FDD LTE cases especially when the duplex space between transmit (Tx) and receive (Rx) is very close as presented in Figure 3.43 for band 17 where the duplex space between Tx and Rx is 30 MHz. Typically, the duplexer uplink to downlink rejection (UpDnR) is around 50 dB and the noise level at the input of the Rx path (LNA input) should be at least 10 dB below thermal noise level 174 dBm/Hz (Figure 3.43) but this is very hard to achieve with/without ET when the FDD duplex space is very narrow. Figure 3.44 presents a solution where the error amplifier and the DC tracking loop has been integrated together with the MMPA for 703 MHz–915 MHz LTE bands 5, 8, 13, 17, and 28 in the same MCM package [26]. Using an ET combiner as presented in Figure 3.18 reduces the distortions due to parasitic coupling inductor. For characterization purpose the band

Envelope tracking techniques

167

0 –20 –40

TX

Antenna

dB –60 –80 –100 630

675

720

765

810

Frequency (MHz) 0 –20

RX

–40

ACLR1

dB –60 –80 –100 630

675

720

765

810

TX

RX

Frequency (MHz)

Figure 3.43 Band 17 duplexer response

HBT amplifier

CMOS control and tracker

Figure 3.44 Photograph detail for MMPA with error amplifier integrated switches as well the filter and duplexers have not been integrated on the same module. Table 3.3 presents the measurements for LTE 10 MHz, 710 MHz, band 17 (defined up to 10 MHz LTE bandwidth), with good efficiency and noise for 40 dBc ACLR1 without DPD. The use of ET combiner [18] as presented in Figure 3.18 provides very good noise isolation to reduce the interaction of the DC–DC switching noise with the

168

Radio frequency and microwave power amplifiers, volume 2

Table 3.3 Measurements for LTE 10 MHz 16 QAM at 710 MHz, band 17 Pout (dBm)

Gain (dB)

Efficiency (%)

ACLR1 (dBc)

RxBn@30 MHz dBm/Hz

25 27 28

26.9 26.8 26.1

38 42 44

44 41 40

124.3 124.1 121.9

Vdc_trck Output Matching network

Band Switch

Tune Route

Duplexer

PA_in RF_in/out SOI

PA

Isolation

RF_in

Signal + Noise LNA

Figure 3.45 FDD diagram for LTE under PA ET operation linear PA. Also, the close proximity of the error amplifier with the PA reduces the Ldi/dt noise. Figure 3.45 presents the PA and LNA noise interaction. The noise at the LNA input Nlna is determined by the formula: Nlna ¼ NPA

IN

þ NfPA þ GainPA  UpDnR þ DnðEtÞ

(3.23)

During ET operation the goal is to keep the Nlna below 184 dBm/Hz and to allow a maximum degradation of 0.5 dB–1 dB of the noise when ET is activated. Also, it is important to provide enough isolation between PA and LNA, usually accounting for output match, band switch, and duplexer losses the isolation must be around 60 dB–70 dB. This forces the MCM integration and not using a single die for PA and LNA design. Actual smartphone uses 3–4 antennas, but the next ones will increase the number of antennas to 6–8 and share some antennas for different TX/RX LTE and WiFi usage. A typical 4G/5G RF front end structure is presented in Figure 3.46. From this prospective high linearity transmitters integrated into a front-end module are required especially with the deployment of MIMO WiFi and LTE assisted access LAA [54]. The module presented in Figure 3.16 has to coexist, operate, and reuse the same antennas without jamming the 2.4 GHz WiFi bands as well the new 5G LTE bands such as 3.2 GHz–4.9 GHz as presented in Figure 3.46.

Envelope tracking techniques Antenna 1a

RX

DRX

Coupler

RX/TX 4G/5G LB_LTE 600MHz-940MHz ET RX/TX

5G

UHB_LTE 3.3GHz-4.9GHz

ET RX/TX

Coupler Antenna 1b Antenna 2

Filter Extractor

Coupler

Diplexer

4G/ 5G HB_LTE

ET RX/TX WiFi 2.4 GHz WiFi ET

PMIC

RX/TX

WiFi

ET RX/TX

169

Isolation

Coupler Wi_Fi Filter

Antenna 3

Coupler Diplexer

2.4 GHz WiFi

WiFi

5GHz WiFi

Coupler

ET

Figure 3.46 4G/5G RFFE structure for a smartphone

2320

2496

2370

2690

B7 Tx TDD-LTE

TD-SCDMA Wi-Fi …..Ch1-Ch13

Band 41

Band E Band 40

Uplink band 7

Wi-Fi

TDD-LTE

TDD-LTE 2500 2300

Downlink Band 7

Band 38

2400 Noise

2570

2620

2690

2483 ACLR

ACLR

Figure 3.47 High band 2.3 GHz–2.7 GHz LTE/WiFi frequency bands For this reason, the FEM should be very linear and therefore the adjacent channel rejection (ACLR) and noise requirements are very challenging. In Figure 3.47 the frequency allocation for 2.3 GHz–2.7 GHz LTE cellular space and the sharing for 2.4 GHz WiFi space are presented.

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References [1] S. Seth, D.H. Kwon, S. Venugopolan, et al., “A dynamically biased multiband 2G/3G/4G cellular transmitter in 28 nm CMOS,” IEEE Journal of Solid-State Circuits, 2016, 61(51), pp. 1096–1108. [2] T. Georgantas, K. Vavelidis, N. Haralabidis, et al., “A 13 mm2 40 nm Multiband GSM/EDGE/HSPAþ/TDSCDMA/LTE Transceiver,” in 2015 International Solid- State Circuits Conference (ISSCC) – Digest of Technical Papers, San Francisco, February 2015, pp. 160–161. [3] T. Buckel, S. Tertinek, T. Mayer, et al., “A highly reconfigurable RF-DPLL phase modulator for polar transmitters in cellular RFICs,” IEEE Transactions on Microwave Theory and Techniques, 2018, 66(6), pp. 2618–2627. [4] T. Nomiyama, Y. Youn, Y. Choo, et al., “A 2Tx supply modulator for envelope-tracking power amplifier supporting intra-and inter-band uplink carrier aggregation and power class-2 high-power user equipment.” in 2018 International Solid- State Circuits Conference (ISSCC) – Digest of Technical Papers, San Francisco, February 2018, pp. 434–436. [5] M. Fulde, A. Belitzer, Z. Boos, et al., “ A digital multimode polar transmitter supporting 40MHz LTE Carrier Aggregation in 20nm CMOS.” in 2017 International Solid-State Circuits Conference (ISSCC) – Digest of Technical Papers, San Francisco, February 2017, pp. 218–219. [6] V. Bhagavatula, D. Kwon, J. Lee, et al., “A SAW-less reconfigurable multimode transmitter with a voltage-mode harmonic-reject mizer in 14 nm FinFET CMOS,” in 2017 International Solid- State Circuits Conference (ISSCC) – Digest of Technical Papers, San Francisco, February 2017, pp. 220–221. [7] F.H. Raab, P. Asbeck, S. Cripps, et al., “Power Amplifiers and Transmitters for RF and Microwave,” IEEE Transactions on Microwave Theory and Techniques, 2002, 50(3), pp. 814–826. [8] L.R. Kahn, “Single-sideband transmission by envelope elimination and restoration,” Proceedings of Institute of Radio Engineering, 1952, 40(7), pp. 803–806. [9] W.H. Doherty, “A new high efficiency power amplifier for modulated waves,” Proceedings of Institute of Radio Engineering, 1936, 24(9), pp. 1163–1182. [10] P. Asbeck, and Z. Popovic, “ET comes of age,” IEEE Microwave Magazine, 2016, 17(3), pp. 16–25. [11] B. Kim, J. Kim, D. Kim, et al., “Push the envelope,” IEEE Microwave Magazine, 2013, 14(3), pp. 68–81. [12] A. Kwan, M. Younes, R. Darraji and F.M. Ghannouchi, “On track of efficiency,” IEEE Microwave Magazine, 2016, 17(5), pp. 46–59. [13] D. Kang, D. Kim and B. Kim, “Broadband HBT Doherty amplifiers for handset applications,” IEEE Transactions on Microwave Theory and Techniques, 2010, 58(12), pp. 4031–4039. [14] M. Elmala, J. Paramesh and K. Soumyanath, “A 90-nm CMOS Doherty power amplifier with minimum AM-PM distortion,” IEEE Journal of SolidState Circuits, 2006, 41(6), pp. 1323–1332.

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[15] E. Zenteno, M. Isaksson and P. Handel, “Output Impedance Mismatch Effects on the Linearity Performance of Digitally Predistorted Power Amplifiers,” IEEE Transactions on Microwave Theory and Techniques, 2015, 63(2), pp. 754–765. [16] J. Kim, D. Kim, Y. Cho, D. Kang, B. Park and B. Kim, “Envelope-tracking two-stage power amplifier with dual-mode supply modulator for LTE,” IEEE Transactions on Microwave Theory and Techniques, 2013, 61(1), pp. 543–552. [17] D. Kang, B. Park, D. Kim, J. Kim, Y. Cho and B. Kim, “Envelope-tracking CMOS power amplifier module for LTE applications,” IEEE Transactions on Microwave Theory and Techniques, 2013, 61(10), pp. 3763–3773. [18] F. Balteanu, “Single die broadband CMOS power amplifier and tracker with 37% overall efficiency for TDD/FDD LTE applications,” in IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Dig., San Francisco, May 2016, pp. 322–323. [19] J.L. Woo, S. Park, U. Kim and Y. Kwon, “Dynamic stack-controlled CMOS RF power amplifier for wideband envelope tracking,” IEEE Transactions on Microwave Theory and Techniques, 2014, 62(12), pp. 3452–3464. [20] R. Wu, Y.T. Liu, J. Lopez, C. Schecht, Y. Li and D. Lie, “High-efficiency silicon-based envelope-tracking power amplifier design with envelope shaping for broadband wireless applications,” IEEE Journal of Solid-State Circuits, 2013, 48(9), pp. 2030–2040. [21] B. Park, D. Kim, S. Kim, et al., “High-performance CMOS power amplifier with improved envelope tracking supply modulator,” IEEE Transactions on Microwave Theory and Techniques, 2016, 64(3), pp. 798–809. [22] D. Kang, B. Park, D. Kim, J. Kim, Y. Cho and B. Kim, “Envelope-tracking CMOS power amplifier module for LTE applications,” IEEE Transactions on Microwave Theory and Techniques, 2013, 61(10), pp. 3763–3773. [23] S. Park, J.L. Woo, U. Kim and Y. Kwon, “Broadband CMrS stacked RF power amplifier using reconfigurable interstage network foe wideband envelope tracking,” IEEE Transactions on Microwave Theory and Techniques, 2015, 63(4), pp. 1174–1185. [24] Y. Li, J. Ortiz and E. Spears, “A highly integrated multiband LTE SiGe power amplifier for envelope tracking,” in IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Dig., Phoenix, May 2015, pp. 131–234. [25] R. Wu, Y.T. Liu, J. Lopez, C. Schecht, Y. Li and D. Lie, “High-efficiency silicon-based envelope-tracking power amplifier design with envelope shaping for broadband wireless applications,” IEEE Journal of Solid-State Circuits, 2013, 48(9), pp. 2030–2040. [26] F. Balteanu, H. Modi, S. Khesbak, S. Drogi, and P. DiCarlo, “Envelope tracking LTE multimode power amplifier with 44% overall efficiency,” 2017 IEEE Asia Pacific Microwave Conference (APMC), Kuala Lumpur, November, pp. 37–40. [27] M.A. de Jongh, A. van Bezooijen, T. Bakker, K.R. Boyle and J. Stulemeijer, “A low-cost closed-loop antenna tuner module for mobile phone single-feed

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Chapter 4

Outphasing power amplifiers Taylor Wallis Barton1 and Paolo Enrico de Falco1

Radio frequency (RF) transmitters have two simultaneous and conflicting requirements: linearity and efficiency. In the majority of transmitters, the element with the largest influence on both these characteristics is the large-signal, power-hungry power amplifier (PA). Conventional single-transistor amplifiers exhibit a direct tradeoff between linearity and efficiency: the transistor can be operated either in a linear (but inefficient) current-source mode, or as an efficient (but nonlinear) switch. One strategy to avoid this design tradeoff is to employ multiple efficient nonlinear PAs within an architecture that provides linear output power control. The outphasing PA architecture has been developed as one means of addressing the linearity-efficiency tradeoff. The generalized outphasing system consists of the following three components, working backwards from the output: ●

●

●

Power combining network, implementing the phase-to-amplitude output power control mechanism; Efficient branch PAs, operated at or near saturation for high efficiency, and often assumed to behave as voltage sources due to the constant-amplitude output; and Signal component separator, which performs the amplitude-to-phase conversion that is the inverse of the power combining network’s behavior, thereby producing an overall linear response.

The basic concept of operation is summarized in Figure 4.1, along with a vector representation of the two branch signals. The amplitude-modulated input signal with envelope EðtÞ is decomposed into two phase-modulated signals with phases yðtÞ, where the differential phase between these two branches ultimately determines the output power. Then, the two phase-modulated signals are upconverted to the carrier frequency – in theory, as constant-amplitude signals although it will be seen that this is not the best approach in practice – and applied to the branch PAs. Any phase information of the original signal can be applied as a common phase offset to the two branch signals. After amplification, the two signals are applied to the outphasing combining network, which can be considered a vector 1

Department of Electrical, Computer and Energy Engineering, University of Colorado Boulder, Boulder, CO, USA

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E(t)

S1 ψ

ψ

S2

f

Branch PAs +ψ(t) E(t)

S1 = V0e j(f (t) + ψ (t)) Combiner cos(ωt + f (t))

cos−1(E)

RL −ψ(t)

VL

S2 = V0e j(f (t) – ψ (t))

Signal separation and upconversion

Figure 4.1 Conceptual overview of the outphasing architecture. The signal component separator performs an amplitude-to-phase conversion on the input signal envelope, producing two constant-envelope, phasemodulated signals shown in vector representation, top, which are then amplified and applied to the power combining network

summation element. For a typical implementation, the combiner can be thought of as constructively adding the in-phase components of the two applied signals, producing an output proportional to the cosine of the outphasing angle yðtÞ. Thus the overall architecture will provide a linear gain characteristic. The combiner will also, depending on implementation, implement load modulation of the two branch PAs, enhancing efficiency at output power back-off. Several features of the outphasing architecture make it an attractive solution for linear and efficient transmitter design, namely: ●

●

Saturated branch PAs: all branch PAs are operated at or near saturation, making operation efficient compared to, for example, the Doherty PA architecture in which at least one PA is operated in the linear regime; and Phase control: linear output power control is provided through modulation of low-power phase signals, compared to, for example, envelope tracking techniques in which the supply modulator efficiency is critical because it operates on a high-power signal.

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Based on these and other promising attributes, there has been a recent resurgence in outphasing transmitters. At the same time, there are several drawbacks in outphasing architectures that make implementation difficult in modern systems. Primary among these is that the outphasing architecture is not a true power amplifier but rather a transmitter architecture, as it requires two modulated RF inputs. These inputs are synthesized from the bandwidth-limited baseband input through a nonlinear function, resulting in bandwidth expansion and requiring increased sample rates in the digital baseband. Although this dual-drive nature is not problematic in all systems, in applications without access to digital baseband the conventional dual-drive outphasing architecture is not appropriate. Additionally, the conventional description of outphasing as relying purely on phase control is misleading; practical systems will modulate both phase and amplitude of the branch PAs in an approach called mixed-mode outphasing. Finally, in its conventional form the outphasing combining network tends to be narrowband, which is increasingly limiting in modern systems. This chapter will, after introducing the more conventional outphasing analysis, highlight recent developments that address some of these drawbacks.

4.1 A brief history The outphasing architecture was developed around the same time as the nowpopular Doherty PA architecture, and for the same application: high-power AM radio transmitters. The term outphasing first appeared in the literature in 1935, introduced by Henri Chireix1 in his paper “High Power Outphasing Modulation” [2]. The goal of this approach was to obtain high-fidelity amplitude modulation from vacuum tubes with poor linearity. Since this invention, the technique has seen varying degrees of interest as transmitter requirements have evolved.

4.1.1 1935–1960: origins Chireix’s approach targeted vacuum-tube amplification of AM signals, demonstrating that controlling load impedance can keep efficiency high while modulating the output power. As will be described in this chapter, the load control is implemented by applying a phase difference to the two branch PAs, which interact through a power combining network. Chireix furthermore introduced shunt reactances, limiting the outphasing dynamic range but also reducing the reactive loading at large outphasing angles and consequently boosting the tubes’ efficiency for large output power back-off. His invention was commercially utilized until the 1970s in RCA “Ampliphase” high power radio broadcast transmitters operating in the range of 50 to 150 kW [3]. In this system, the outphasing approach was refined to include both amplitude and phase variation of the input of the branch amplifiers. Details of the analog techniques used to generate these outphasing signals are described in Section 4.5. 1

“Chireix” is pronounced similarly to “she wrecks” [1].

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1974: linear amplification with nonlinear components

Little activity in outphasing systems can be found in the literature until 1974, when Cox proposed the linear amplification with nonlinear components (LINC) architecture in [4]. Here, the outphasing principle is applied to a system using an isolating Wilkinson power combiner. The target application was linear amplification of single-side band suppressed carrier wireless communication signals. The Wilkinson combiner provides an advantage in terms of linearity, in that the branch PAs always drive a well-controlled 50-W load and the power-combining relationship to outphasing angle can be more readily determined. On the other hand, this approach has the negative side effect of “dumping” the difference power into the isolating resistor, eliminating the efficiency enhancement benefits compared to Chireix’s nonisolating approach. For the following 30 years most of the research effort was placed into the development of efficient and accurate signal component separators (SCSs) and techniques to reuse the outphased power of the LINC approach. The complexity of the initial analog SCS requiring mixers, low pass filters, and phase control was improved with other technique such as CALLUM and eventually replaced by digital signal processing techniques successfully implemented in DSP and FPGA.

4.1.3

2000s: resurgence in interest

The first outphasing Chireix prototypes at GHz frequencies were presented in the literature between 2004 and 2009 with HEMT devices by Nokia Research Laboratories in [5], with GaAs in [6] and with LDMOS devices in [7,8]. These works targeted W-CDMA medium-power base stations (10–20 W) and low-power WLAN transmitters, showing promising efficiency performance in back-off. In the last decade, driven by the advent of LTE, DVB-T2, and other modern wireless communications standards having waveforms with large PAPR, interest in the outphasing technique and its potential surged again, both from academic and industrial research groups. One area of research has focused on the improvement of back-off efficiency of the LINC technique, otherwise limited by the vector summation which dissipates the out of phase content in an isolation resistor. Techniques include recovering energy lost in the isolation resistor by replacing it with a rectifier [9,10], and limiting the outphasing angle range by adding supply modulation as a “coarse” amplitude with fine control provided by outphasing [11–23]. These variations are described in Section 4.2.1. For load-modulating outphasing systems, research in the 2000s has addressed the selection of branch PAs for best efficiency under load modulation conditions (Section 4.4), reduced the reactive loading of two-way outphasing by introducing multiway outphasing systems (Section 4.3), challenged the assumption that the power combining network should present resistive loading at all, and dealt with the potentially problematic requirement for dual-drive operation (Section 4.5).

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The outphasing technique has successfully been demonstrated at X-band [24,25] and has been shown at this frequency in combination with a discrete supply modulator [26,27] and a power recycling circuit [9]. Outphasing load modulation trajectories have also been measured in situ on a 10 GHz outphasing system [28], demonstrating the validity of the analysis in [29]. Between 2009 and 2013, Delft University in collaboration with NXP investigated using GaN class-E PAs (20–70 W) in Chireix outphasing systems, developing a packaged integrated solution and CMOS drivers to further boost efficiency [30–33]. Following on the work of NXP and Delft on class-E outphasing, in 2015 a methodology to synthesize a lossless combiner based on a black-box approach was developed at Chalmers University, incorporating both combiner and matching network design [34,35]. This approach leads to a reduction in size and potentially an improvement in bandwidth as shown in [34]. A 25 W GaN outphasing prototype including CMOS drivers was demonstrated employing continuous class E theory in combination with an optimization strategy to provide the largest fractional bandwidth reported in the art for an outphasing transmitter (33%), described further in Chapter 5 of this book.

4.2 Outphasing operation Outphasing systems can be broadly classified based on the type of power combiner utilized: isolating or nonisolating outphasing. To distinguish between these two very different approaches, in this chapter we will refer to systems with isolating combiners as LINC systems, and ones with nonisolating combiners as nonisolating, direct, or Chireix outphasing. The two techniques are differentiated in how the branch PAs are loaded during outphasing operation. In LINC systems, the PAs see a constant, well-controlled impedance, compared to nonisolating outphasing systems which employ load modulation of the branch PAs. Advantages of LINC include the constant load to the PAs, so that the branch PAs can be optimized for a specific loading condition and good linearity which stems from the well-known relationship between outphasing angle and output power. When nonisolating combiners are used, on the other hand, variation of the outphasing angle causes a modulation in the load seen by each branch PA. The output power delivered by each branch PA is controlled through this load modulation mechanism, and efficiency can be maintained over a wider output power dynamic range. The linearity of this approach tends to be worse than in LINC due to the greater challenge to control and determine the load to output power relationship, and the design is significantly more challenging due to the PAs operating over a wide range of load impedances. For either type of outphasing system, the commonality lies in the treatment of the input signal. If the input signal has some amplitude AðtÞ and phase jðtÞ, expressed in phasor notation as Sin ðtÞ ¼ AðtÞejjðtÞ

(4.1)

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then the signal decomposition can be performed as S1 ðtÞ ¼ V0 ejðjðtÞþyðtÞÞ

(4.2)

S2 ðtÞ ¼ V0 e

(4.3)

jðjðtÞyðtÞÞ

where V0 is the envelope of the PA output, assumed constant, and y(t) is the outphasing angle. The exact outphasing angle selection depends on whether additive or subtractive combining takes place at the output (or, whether more than two branches are used). Assuming the combiner is additive, and therefore the output goes as the cosine of the outphasing angle, the outphasing angle is selected based on the normalized amplitude as
 1 AðtÞ (4.4) yðtÞ ¼ cos Amax For the cosine example, the outphasing angle therefore varies over a 0 to 90 range, although in practice this range may be reduced as will be seen later in this chapter.

4.2.1

Isolating combining: LINC

Equivalent circuit representations of the LINC system with Wilkinson and hybrid 3-dB combining networks are shown in Figure 4.2. When isolating combiners such as these are used, the impedance seen by each PA remains ideally constant throughout the outphasing range. Because the drive power is also fixed, each branch PA delivers to the combiner the same amount of RF power, PPA , and draws the same amount of dc current from the supply throughout outphasing operation. Z0

Z0√2 V1 = V0e jψ

λ 4

V1 = V0e jψ Z0

√2

Z0 Z0

Riso Z0√2 λ 4

V2 = V0e –jψ Riso = 2Z0

(a)

Z0 = RL

λ 4 λ 4 Z 0

Z0

λ 4

Riso

√2

RL

V2 = V0e –jψ

λ 4

RL

Riso = Z0 = RL

(b)

Figure 4.2 Simplified LINC outphasing systems based (a) Wilkinson and (b) hybrid 3-dB coupler combining networks. Power not delivered to the load resistance RL is dissipated in the isolation resistor Riso , ensuring isolation between the two branch PAs at the expense of efficiency

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The power delivered to the load at the fundamental frequency, PL , is related to the outphasing angle as PL ¼ 2PPA cos2 ðyÞ

(4.5)

The power dissipated in the isolating resistor is found from the two out-of-phase components of the outphasing vectors as PRiso ¼ 2PPA sin2 ðyÞ

(4.6)

The two branch PAs will consume a total dc power of PDC ¼ 2

PPA hPA

(4.7)

where hPA is the dc to RF efficiency of each branch PA. The system efficiency is therefore hLINC ¼ hPA cos2 ðyÞ

(4.8)

Note that the system efficiency drops off in proportion to output power, that is, when output power is reduced by 6 dB the efficiency drops to 25% of the peak value. This is similar to how efficiency drops off in a class A PA. By contrast, class B PAs lose efficiency in proportion to back-off voltage, or with the square root of power [36]. The efficiency versus output power of ideal LINC, class A, and class B PAs are compared in Figure 4.3, showing that even though LINC has the potential for higher efficiency than the single-ended alternatives, it does not have a clear advantage for high-PAPR signals. To improve system efficiency, one possibility is to recover the power lost in the isolation resistor by replacing the resistor with a rectifier [9,10]. In that case the

Efficiency (%)

100 80 60

Class A Class B LINC

40 20 0 –10

–8

–6

–4

–2

0

Normalized output power (dB)

Figure 4.3 Ideal LINC efficiency over output power, assuming 100% efficiency for the two branch PAs, compared to ideal class A and class B amplifiers. Although the LINC system’s efficiency at peak output power is much higher, by around 2 dB output power back-off the efficiency drops below that of class B

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system efficiency depends on the efficiency of the power rectification, hR , and is determined as hLINC;recycle ¼

PL hPA cos2 ðyÞ ¼ PDC  hR PRiso 1  hPA hR sin2 ðyÞ

(4.9)

The drain efficiency of a LINC system using class-B PAs, for different values of rectification efficiency is shown in Figure 4.4. Complicating this approach, the input impedance to a rectifier varies with input power [10]. This means that the rectifier will only properly terminate the power combining network at one power level, and therefore isolation between the two branches is degraded at all other levels. One solution to this problem is to insert a resistance compression network (RCN) between the combining network and multiple rectifiers. The RCN is a specialized matching network that presents a reduced input impedance variation when loaded with multiple varying loads [37–39]. It has been demonstrated to improve efficiency and isolation in LINC systems in [10], and a four-way version based on transmission lines is demonstrated in [40], applied to wireless power transfer systems. An alternative approach to improving LINC efficiency involves applying supply modulation to the branch PAs. This limits the outphasing angle (and therefore loss) at lower power levels. By using discrete power supply levels, the efficiency of the supply modulator can be kept high, with dynamic supply modulation used as coarse amplitude control and outphasing used to fill in the fine control between levels. The first implementations of this multilevel LINC (ML-LINC) approach were presented between 2007 and 2009 [11–13], followed by further development at Aachen University and MIT. Research published between 2011 and 2014 at Aachen University demonstrated various algorithms for the selection and placement of the multiple voltage levels, optimized for linearity, efficiency, or a compromise of both, in a ML-LINC architecture using GaN PAs [14–17]. Static and iterative calibration techniques to address gain and phase imbalance between the PA paths were presented [18,19] and the ability to linearly amplify noncontiguous LTE signals was shown [20]. By introducing the option to use different supply voltage levels for the two branches, the asymmetric multilevel

System efficiency (%)

80 60 40

LINC LINC + rect. ηr = 30% LINC + rect. ηr = 50% LINC + rect. ηr = 70%

20 0 –15

–10

–5

0

Normalized output power (dB)

Figure 4.4 System efficiency versus output power in a LINC system with energy recovery, for different rectifier efficiencies

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outphasing (AMO) technique enabled further reduction in outphasing angles, as suggested in [12] and [21–23]. Alternative methods to modulate the magnitude of the LINC vectors without supply modulation include for example using pulsewidth modulation [22] or implementing the two branch PAs using RF DACs [41].

4.2.2 Nonisolating combining: load modulation Outphasing systems with nonisolating power combining networks differ substantially from LINC systems in that load modulation is used to improve efficiency at output power back-off. Sections 4.2.3 and 4.2.4 present the theory of load modulation, and the operation of Chireix outphasing systems. A number of simplifying assumptions are made, primarily that the two branch PAs behave as ideal voltage sources and that they therefore want to see resistive load variation. Typically, the voltage-source assumption is justified by assuming the PAs are driven into a clipping mode, and so the output swing is determined by the voltage rails. It is important to note that clipping operation (and the associated assumption of a constant-amplitude input drive) should be controlled within outphasing operation. In other words, the input drive amplitude is also modulated, along with the phase, to enforce the constant voltage condition and a fixed amount of clipping. This approach, called mixed-mode outphasing, will be examined in greater detail at the end of this section. A similar end result can be achieved by treating the PAs as voltage-controlled current sources and modulating the input drive amplitude appropriately. The analysis presented here assumes the output power of the voltage-sourcelike branch PAs is ideally controlled using resistive load modulation, with output power from each PA varying as V02 =R for resistive load variations. This assumption is certainly valid for ideal voltage sources, and goes along with the further assumption that the efficiency of the sources is proportional to the power factor of the load. At microwave frequencies, of course, significant parasitics exist between the current generator plane of the device and the reference plane at the input of the combining network. As a result, either the device can be pre-matched such that it operates efficiently over a resistive load trajectory, or complex load trajectories should be presented by the combiner. For the purposes of the theoretical analysis in this section, it is assumed that the combiner can be designed at the current generator plane of the device, that is, resistive load variation will be considered. Load modulation in outphasing systems is best understood based on the simplified circuit shown in Figure 4.5(a), in which two voltage sources drive a differential load. The two sources are assumed to have fixed, equal amplitudes V0 , and equal and opposite phases y. In fact, because it is the relative phase between the two sources that will be important, there is essentially a single input to this system which is the difference in phase, 2y. With the two voltages set as V1 ¼ V0 ejy

and

V2 ¼ V0 ejy

(4.10)

the current through the differential load resistor is IL ¼ I1 ¼ I2 ¼

V0 ejy  V0 ejy RL

(4.11)

184

Radio frequency and microwave power amplifiers, volume 2 Y1

Y2

Y1

∆V = V1 – V2 I1

V1 = V0e jψ (a)

RL

IVS1

TL1 Z01, θ01

I2

V2 = V0e –jψ V1 = V0e jψ

A

I1

B I2

IL

RL

Y2 TL2

IVS2

Z02, θ02

V2 = V0e –jψ

(b)

Figure 4.5 Outphasing architectures with nonisolating power combiners: (a) simplified architecture with differential load; and (b) a more practical implementation using quarter-wavelength lines to convert the floating load to single-ended

The load admittances “seen” by the two voltage sources can therefore be found as Y1 ¼

I1 2 sin2 y sin 2y ¼ þj ¼ G þ jB V1 RL RL

(4.12)

Y2 ¼

I2 2 sin2 y sin 2y ¼ j ¼ G  jB V2 RL RL

(4.13)

That is, the two sources see complex conjugate impedances, with both the real and complex parts determined by the outphasing angle y. These complex load admittances are plotted as a function of y in Figure 4.6(a). The resistive loading of the two branch PAs is the desirable outcome of outphasing: phase controls load impedance, which in turn controls output power. For an ideal voltage source as is assumed here, the output power depends on outphasing angle as shown in Figure 4.6(b). On the other hand, the significant reactive loading is problematic, and will degrade efficiency performance in a practical system. The load trajectories are shown on a Smith Chart in Figure 4.7, which demonstrates the severely reactive loading. A more practical combiner implementation, particularly for microwave frequencies, is shown in Figure 4.5(b). Here, quarter-wavelength transmission lines are used to transform the differential floating load to single-ended without otherwise changing the system operation. As derived in [29], the output currents flowing into the output node can be determined as function of the outphasing angle using the ABCD parameters of the l=4 transmission line: 2 3   0 jZ0 A B 5 (4.14) ¼4 j 0 C D Z0

Outphasing power amplifiers

1

Upper branch

1

0 0

 8

 3 4 8 Outphasing angle (ψ)

Susceptance

{Y1,2}

Lower branch

Upper branch

1

0.75 0.5 0.25 0 0

0 (b) –1 0

(a)

 2

Norm. output power

{Y1,2}

2

Conductance

Lower branch

185

 8

 4

3 8

 8

 4

3 8

 2

Outphasing angle (ψ)

 2

Outphasing angle (ψ)

Figure 4.6 Simplified outphasing operation showing (a) the real and imaginary parts of the admittances seen by the outphasing branch PAs as a function of outphasing angle; and (b) the output power relationship to y when ideal voltage sources are assumed +j1.0 +j0.5

ψ=

Upper branch 3π 2

+j2.0

+j5.0

ψ=

5.0

2.0

1.0

0.5

0.0

0.2

+j0.2

π 2

∞ ψ=0

–j5.0

–j0.2

–j0.5

ψ= –j1.0

3π 2

–j2.0

Lower branch

Figure 4.7 Load impedance trajectories of the two branch PAs in a differential outphasing amplifier as outphasing angle is swept. The complex conjugate trajectories are denoted as “upper branch” for the inductively-loaded side, and “lower branch” for the capacitively loaded side

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Radio frequency and microwave power amplifiers, volume 2

Assuming the characteristic impedances of the quarter-wavelength transmission lines are equal, the current through the load is IL ¼ I1 þ I2 ¼

 V0 e jy V0 ejy V0  jy þ ¼ e þ ejy jZ0 jZ0 jZ0

(4.15)

and the voltage across the load is V L ¼ IL RL

(4.16)

The admittances at planes A and B (see Figure 4.5) are YA ¼ I1 =VL and YB ¼ I2 =VL , and these impedances can then be transformed to the voltage source plane to find Y1 ¼

I1 2 cos2 ðyÞ 2 sinð2yÞ ¼ j 0 0 V1 RL RL

(4.17)

Y2 ¼

I2 2 cos2 ðyÞ 2 sinð2yÞ ¼ þj 0 0 V2 RL RL

(4.18) 0

where the impedance transformation parameter RL ¼ Z02 =RL is determined by the load resistor and characteristic impedance of the transmission lines. As with the simple differential load, these impedances can be written as Y1;2 ¼ G  jB with both G and B functions of the outphasing angle. The real power delivered by each PA is 1 V 2 cos2 ðyÞ P1 ¼ P2 ¼ V02 G ¼ 0 0 2 RL

(4.19)

Because the power combining network is lossless, the power at the load is the sum of the powers delivered by each branch PA: P L ¼ P1 þ P 2 ¼

2V02 cos2 ðyÞ R0 L

(4.20)

The load trajectories and output power characteristics follow the same behavior as for the less readily implemented differential-load version, as in Figures 4.6 and 4.7.

4.2.3

Chireix combining

The large reactive variations in load impedance in the simple direct combining structure is problematic, both because the low power factor of the load degrades efficiency, and because it potentially invalidates the assumption that the two branch PAs drive the combiner with identical output swings (most practical PAs will behave differently when presented with a highly inductive vs capacitive load). This shortcoming is addressed in Chireix outphasing systems by adding susceptive elements in each branch to offset the impedance trajectories, as shown in Figure 4.8. In this way, the load reactance can be made zero for two outphasing angles. The complementary shunt reactances, jBcomp , are typically described in terms of

Outphasing power amplifiers Y1

Y2 Z0

Z0

jB

V1 = V0e jψ

187

λ 4

RL

λ 4

–jB

V2 = V0e –jψ

Figure 4.8 Outphasing combining structure incorporating transmission lines and Chireix compensation elements

compensating angle ycomp , that is, the phases at which the load trajectories are purely resistive:   2 sin 2ycomp Bcomp ¼ (4.21) R0 L The new load impedances presented to the branch PAs are now:  ! I1 2 cos2 y 2 sin 2y 2 sin 2ycomp ¼ j  Y1 ¼ V1 R0 L R0 L R0 L  ! I1 2 cos2 y 2 sin 2y 2 sin 2ycomp Y2 ¼ ¼ þj  V1 R0 L R0 L R0 L

(4.22)

(4.23)

The Chireix outphasing load trajectories are shown in Figure 4.9 for an example value of ycomp ¼ p=8. Note that the practical range of outphasing angle is now limited to approximately 3p=8 to p=8. These two phases correspond to the points of zero reactive loading, which will have highest efficiency. Typically, the lower impedance point (here corresponding to y ¼ 3p=8) will be designed to correspond to the Cripps load line impedance Ropt [36], or in other words the impedance corresponding to highest output power. The higher-resistance point of zero reactive loading (corresponding to y ¼ p=8 in the system in Figure 4.9) will, in principle, correspond to a second efficiency peak. The ratio of the powers between the peak and back-off zero-reactance points is given by (4.24): cos2 ðycomp Þ Ppk  ¼ (4.24) PBO cos2 p  y comp 2 For the example ycomp ¼ p=8, this ratio is 7.66 dB. If a 6-dB range is desired between peak and back-off efficiency points, (4.24) can be inverted to find ycomp;6dB ¼ 0:463 rad ¼ 26:5 .

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Radio frequency and microwave power amplifiers, volume 2

+j1.0

Y1ψ= 0

+j0.5

+j2.0

+j0.2

+j5.0

{Z1,2}

Lower branch

4

Resistance

Lower branch

2 1 0 0

5.0

2.0

1.0

Y2 ψ= π

 3  4 8 8 Outphasing angle (ψ)

Y1,2 ψ= π = Y1,2 ψ= π – π 8

2

8

–j2.0

–j0.5

Upper branch

–j1.0

Y2ψ=0

–j5.0

{Z1,2}

Lower branch

2

–j0.2

 2

∞ 5 2.5

Resistance

2

0.5

0.2

Y1 ψ= π 0.0

Upper branch

–2.5

Upper branch

0 0 0

 3  4 8 8 Outphasing angle (ψ)

 2

Figure 4.9 Upper and lower branch differential outphasing load trajectories when the compensating phase is chosen as ycomp ¼ p=8. The practical range of outphasing angles is limited to around 3p=8 to p=8 Determining the efficiency of nonisolating outphasing systems requires specific knowledge of the PA utilized for the branch amplifiers. Ultimately, the branch amplifier efficiency will depend on the shape of the waveforms throughout the outphasing load modulation range. Among other factors such as harmonic terminations and overdrive level, one determiner of efficiency is the technology and device utilized, as technologies will have different “knee” characteristics controlling the compression mechanism of the device. Given these complexities, power factor is commonly used as a way to approximate efficiency for a generalized outphasing system. This metric, not commonly used in RF/microwave engineering, is used in the power electronics field to provide a measure of the ratio of real to total power delivered to a load. In the outphasing system, this is calculated from the two input impedances as PF ¼

ðn1Þ n

(10.48)

(10.49)

which shows that the required interstage characteristic impedance Z0int decreases for the same devices as the stage number n increases [72]. Hence, a cascade of four single-stage FETs with intermediate characteristic impedance of 86.6 W and device transconductance gm ¼ 28 mS should yield a 50-W matched distributed amplifier configuration with a 20-dB available gain over wide frequency band, compared to only 9-dB available gain for a CDA according to (10.48). In a practical case of the 4-CSSDA using low-noise MESFET devices with gm ¼ 55 mS, a power gain of 39  2 dB over a frequency bandwidth of 0.8–10.8 GHz was measured [73]. Due to the typical second-order low-pass filter configurations, the bandwidth of the 2-CSSDA is band limited compared with the CDA. As the number of stages of the amplifier increases, the low-frequency gain also increases, so it is not easy to design a flat-gain performance for a multistage CSSDA. Therefore, to provide wider bandwidth with high-gain performance, the broadband distributed amplifier can combine the CDA and CSSDA with different number of stages [74]. As a

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Radio frequency and microwave power amplifiers, volume 2

result, the forward available gain of the distributed amplifier combining the n-stage CDA and n-stage CSSDA is given by 2ðn1Þ

2n 2 Z0int Z0g Z0d n2 gm Z0g Z0d gm : (10.50) 4 4 Figure 10.32(a) shows the circuit schematic of a monolithic two-stage CDA cascaded with a single-stage CSSDA using a 0.15-mm pHEMT technology, which provides a small-signal gain of 19  1 dB over the frequency range of 0.5–27 GHz. To extend the amplifier gain-bandwidth performance for millimeter-wave applications, a monolithic seven-stage CDA cascaded with a two-stage CSSDA using the same technology with a die size of 1.5 2 mm2 was designed, as shown in Figure 10.32(b), achieving a small-signal gain of 22  1 dB over the frequency range of 0.1–40 GHz with a total dc consumption of 484 mW [74]. The group delay of 30  10 ps is sufficiently flat over whole bandwidth, which is very important for digital optical communications. The gain response and efficiency of the CSSDA is increased if the intermediate impedance Z0int ¼ Rvar þ jwLvar at the drain terminal of each active device is included, as shown in Figure 10.33 for a lumped three-stage cascaded reactively terminated single-stage distributed amplifier (CRTSSDA) [75]. Although the bandwidth of this amplifier is also limited by the gate and drain inductances L, it

G¼

Vg1

Pin Vg2 4×200 µm 4×200 μm Vd1 4×200 μm

Vd2

Pout

(a)

Vg1

Pin Vg2 4×80 μm 4×80 μm 4×80 μm 4×80 μm 4×80 μm 4×80 μm 4×80 μm Vd2 4×80 μm Vd1

Vg3 4×200 μm

Vd3

Pout

(b)

Figure 10.32 Schematics of cascaded conventional and single-stage distributed amplifiers

Distributed power amplifiers Pin

Lg /2

461

L/2 Lvar Rvar L

Lbias C bias

L/2

Lbias

Lvar

C bias

Rvar L

Lbias C bias

L/2

Lbias

Lvar

C bias

Rvar L

Lbias C bias

L/2

Lbias

Lvar

C bias

Rvar

Pout

Figure 10.33 Schematic of three-cascaded reactively terminated single-stage distributed amplifier can be substantially improved by the inclusion of the inductance Lvar and resistance Rvar. The effect of the reactive termination is to enhance the voltage swing across the input gate–source capacitance Cgs of each active device, which results in an increased output drain current from each device. This consequently improves the amplifier overall gain performance over the multioctave bandwidth. In this case, to provide a flat gain response over the desired bandwidth, it is simply necessary to adjust the impedance Z0int, because the effect of the inductance Lvar is negligible at lower frequencies (in the range of 10 kHz to 1 GHz) when the intermediate impedance can be written as Z0int ¼ Rvar. The selection of the bias components Lbias and Cbias also plays a critical role in optimizing the bandwidth and must have minimum intrinsic parasitics. The initial value of the resistance Rvar can be calculated from (10.49), which is dependent on the device transconductance gm and the number of stages n constituting the CRTSSDA. However, the calculated value of Rvar will have to be optimized in order to achieve the required small-signal response. The inductive component Lvar will have an effect on the small-signal gain at higher frequencies (over 2 GHz). The primary effect of this component is to alter the magnitude of the small-signal level at the input port of the respective device of the CRTSSDA chain to be amplified by its device transconductance. The initial value of the inductance can be calculated from: pffiffiffi ðn1Þ n : (10.51) Lvar  gm w

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Radio frequency and microwave power amplifiers, volume 2

The fabricated three-stage CRTSSDA based on a 0.25-mm double pHEMT technology with a gate periphery of 360 mm for each transistor with a self-biased mode of operation (gates are directly grounded through the inductances Lbias) providing a dc current of 120 mA achieved a gain of 26  1.5 dB, the input and output return loss of better than 9.6 dB (VSWR of better than 2:1), and a PAE of greater than 12.6% across the frequency bandwidth of 2–18 GHz [76]. The output power of greater than 24.5 dBm with a PAE of greater than 27% across 2–18 GHz was achieved when a pHEMT device with a gate width of 720 mm was used in a final stage and a pHEMT device with a gate width of 200 mm was used in a first stage [77].

10.7 CMOS distributed amplifiers Unlike the semi-insulating GaAs process which provides higher quality lumped inductors and transmission lines, a CMOS-based implementation is advantageous in which it results in a lower cost and a higher level of integration. One of the first designs of a four-cell CMOS distributed amplifier was based on a 0.6-mm CMOS process with three-layer Al-metal interconnect when a flat gain of 6.5  1.2 dB over a bandwidth from 500 to 4 GHz with approximately linear phase over the passband was achieved [78]. Figure 10.34(a) shows the basic circuit schematic of a four-cell lumped CMOS distributed amplifier. In this case, if the gate- and drain-line inductors are matched, and the drain capacitance is made equal to the gate capacitance for each transistor, then the input and output currents are phase synchronized. Another modification to

RLd

Cd

Ld/2

Cd

Ld

Cd

Ld

Cd

Ld

Ld/2

Lg/2

Lg

Pin

Lg

Lg

Lg/2

Pout

RLg

(a)

RLd

Matching section

Cd

Ld/2

Vdd

Cd

Ld

Cd

Ld

Matching section

Cd

Ld

Pout

Ld/2

Lg/2 Pin Matching section

Lg

Lg

Lg

Lg/2 Matching section

RLg Vg

(b)

Figure 10.34 Schematics of lumped four-cell CMOS distributed amplifiers

Distributed power amplifiers

463

the basic circuit relates to the proper gate- and drain-line termination. The impedance seen looking into the LC artificial transmission lines will exhibit a strong deviation from the nominal impedance near the cutoff frequency of the lines. Ideally, all four ports would be image-impedance matched to the lines to eliminate reflections. However, it is not practical to realize an image-impedance matching directly. Thus, the method used will be to insert the m-derived half-sections between the lines and the input port, output port, and terminations. These halfsections will greatly improve the impedance matching, while also allowing simple resistive terminations to be used. The modified circuit of a lumped four-cell CMOS distributed amplifier with matching sections is shown in Figure 10.34(b) [76]. Based on a 0.18-mm SiGe BiCMOS technology with six-layer metal interconnects and final tow thick-copper layers to realize low-loss inductors and using only nMOS transistors, a frequency bandwidth was extended from 500 MHz to 22 GHz with the flat gain of 7  0.7 dB and input return loss better than 10 dB over most of the bandwidth [79]. Silicon-on-insulator (SOI) CMOS technologies can provide high-gain performance at millimeter-wave frequencies required for low-power broadband microwave and optical systems. For example, a 0.12-mm SOI CMOS process offers a low-parasitic nMOS transistor with a peak fT more than 150 GHz for gate length smaller than 60 nm. Here, since the integration of the low-loss 50-W microstrip lines is difficult, the coplanar waveguide (CPW) structures were implemented on the last 1.2-mm-thick metal layers to reduce the parasitic capacitances to the substrate [80]. As a result, a gain of 4  1.2 dB over the bandwidth of 4–91 GHz and an 18-GHz output 1-dB compression point of 10 dBm were measured for the cascode five-cell distributed amplifier with a power consumption of 90 mW. The cascode three-cell distributed amplifier implemented in a 45-nm SOI CMOS process with a peak fT in excess of 230 GHz, whose value strongly depends on the layout parasitics and may reach 380 GHz, achieved a 3-dB bandwidth of 92 GHz and a peak gain of 9 dB with a gain ripple of 1.5 dB and an input return loss better than 10 dB [81]. It should be noted that the noise behavior of a distributed amplifier over entire frequency band depends significantly on the number of cells n. For example, the best low-frequency noise performance is achieved for larger values of n, whereas the lowest noise figures are reached at high frequencies for smaller values of n [82]. This noise behavior is attributed to the fact that the drain noise is inversely proportional to n, whereas the gate noise is proportional to n. Besides, for the same number of cells, a cascode CMOS distributed amplifier demonstrates better noise performance over most of the frequency bandwidths, especially at higher frequencies, compared to the conventional CMOS distributed amplifier with the transistors in a common-source configuration. By employing a nonuniform architecture for the artificial input and output transmission lines, the CMOS distributed amplifier exhibits enhanced performance in terms of gain and bandwidth. Figure 10.35 shows the circuit schematic of a cascode nonuniform five-cell distributed amplifier using a standard 0.18-mm CMOS technology where the transistor sizes and inductance values of the center cell is 2.5 times as large as those of the other cells [83]. In this design, the

464

Radio frequency and microwave power amplifiers, volume 2 RLd

Ld

Ld/2

7Ld/4

Ld/2

Ld

7Ld/4

Pout Vg2

M2 Lm

Pin

Lg/2

M2 Lm

2.5×M2

M2

Lm

Lm

M1

M1

2.5×M1

M1

Lg

7Lg/4

7Lg/4

Lg

M2 Lm M1 Lg/2

RLg

Vg1

Figure 10.35 Schematic of cascode nonuniform five-cell CMOS distributed amplifier parameters of the common-source transistors are designed in consideration of the cutoff frequency of the input line and the transconductance of the gain stages. On the other hand, the common-gate transistors are designed to provide an output capacitance equivalent to the input capacitance of the gain stages such that matched input and output lines can be utilized to optimize the phase response of the distributed amplifier. The values of the inductive elements Lm between cascode transistors need to be adjusted for maximum bandwidth extension. Finally, the high-impedance CPW structures were employed to realize the required gate and drain inductances, resulting in a pass-band gain of 9.5 dB and a 3-dB bandwidth of 32 GHz for this distributed amplifier. The main drawback of an integrated CMOS implementation of the singleended common-source amplifiers including system-on-chip solutions is that parasitic interconnects, bondwires, and package inductors degenerately degrade their gain-bandwidth performance. Specifically, for a packaged single-ended distributed amplifier which exhibits a unity-gain bandwidth of 4 GHz, there is a bandwidth degradation of 27% compared to its unpackaged performance [78]. Figure 10.36 shows the circuit schematic of a fully differential four-cell CMOS distributed amplifier with the ideal passive components [84]. The characteristic impedances of the gate and drain lines are designed to be 25 W each to provide a load impedance of 50 W for fully differential signals. The highest achievable line cutoff frequency for the 0.6-mm CMOS process is about 10 GHz and is limited by the smallest practical values of the circuit inductances and capacitances. Since high-quality tail current sources are essential for achieving high common-mode and power-supply rejection ratios, a regulated cascode current source is employed in each stage. Such architecture also minimizes undesirable signal coupling between stages through the common substrate. To improve the impedance matching between the termination resistors and the artificial transmission line over a wide range of frequencies, two pairs of m-derived half-sections are used, and the drain and date bias voltages are supplied through the termination ports. As a result, the measured results for this fully differential CMOS-distributed amplifier with transistor gate widths of 400 mm

Distributed power amplifiers

465

0.38 pF

Vdd

0.4 pF

0.42 nH

0.4 pF

0.4 pF

25 Ω

0.64 nH

0.8 nH

0.8 nH

0.8 nH

25 Ω

0.64 nH

0.4 pF

0.4 pF

0.4 pF

50 pF

0.8 nH

0.4 pF 50 pF

0.4 pF

0.8 nH

0.8 nH

Pout

50 pF

0.42 nH

0.38 pF 0.27 pF 50 pF Pin

0.56 nH

50 pF

0.56 nH 0.56 nH

0.56 nH 0.56 nH

0.45 nH 0.56 nH

0.3 nH

Vg 25 Ω

0.45 nH

25 Ω

0.3 nH

50 pF

0.27 pF

Figure 10.36 Circuit schematic of fully differential four-cell CMOS distributed amplifier

demonstrated a bandwidth of 1.5–7.5 GHz, which is about 50% greater than for a single-ended counterpart, but obtained at the expense of increased power consumption, die size, and noise figure. The bisected-T m-derived filter sections at the input and output of the distributed amplifiers are widely used to improve matching and gain flatness near the amplifier cutoff frequency. In this case, a bisected-T-type m-section matches a Ttype k-section (or cascade of them) on one side and matches the constant real impedance on the other side. Thus, the bisected-T m-section can couple power from a real source into a cascade of T-type k-sections over the full frequency range from dc to cutoff frequency. Similarly, the bisected-p m-section can couple power from a real source into a cascade of p-type k-sections over the same frequency range [85]. The capacitance in each k-section unit cell is the gate (or drain) capacitance of a transistor. This can be added together into a single transistor or gain cell which is 80% of the size of a full gain cell, thus resulting in a higher voltage gain by Ap 0:6 ¼1þ AT n

(10.52)

than its T-type equivalent. The second factor 0.6/n comes from extra transistor area in the matching sections at both the beginning and end of the artificial transmission line. As it follows from (10.52), the gain boost is higher for smaller n but gives appreciable improvement over the typical range of n, specifically of 1 dB for n ¼ 5. Besides, since inductors are generally lossy and difficult to accurately model at microwave frequencies, the p-type topology reduces both the number and the size

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Radio frequency and microwave power amplifiers, volume 2

of inductors. In a practical implementation, an overall area reduction of 17% (excluding pads) was achieved for a p-type topology [85]. To extend the flat bandwidth and improve the input matching of a cascode distributed amplifier, the gate artificial transmission line based on coupled inductors in conjunction with seriespeaking inductors in cascode gain stages can be used [86].

References [1] Percival W.S. Improvements in and Relating to Thermionic Valve Circuits. British Patent 460562, Jan 1937. [2] Ginzton E.L., Hewlett W.R., Jasberg J.H., and Noe J.D. ‘Distributed amplification’. Proc. IRE, 1948, vol. 36(8), pp. 956–969. [3] Horton W.H., Jasberg J.H., and Noe J.D. ‘Distributed amplifiers: practical considerations and experimental results’. Proc. IRE, 1950, vol. 38(7), pp. 748–753. [4] Bassett H.G., and Kelly L.C. ‘Distributed amplifiers: some new methods for controlling gain/frequency and transient responses of amplifiers having moderate bandwidths’. Proc. IEE, III: Radio Commun. Eng., 1954, vol. 101(69), pp. 5–14. [5] Chen W.K. ‘Distributed amplifiers: survey of the effects of lumped-transmissionline design on performance’. Proc. IEE, 1967, vol. 114(8), pp. 1065–1074. [6] Chen W.K. ‘Distributed amplification: a new approach’. IEEE Trans. Electron Devices, 1967, vol. 14(4), pp. 215–221. [7] Sarma D.G. ‘On distributed amplification’. Proc. IEE, B: Radio Electron. Eng., 1955, vol. 102(5), pp. 689–697. [8] Thompson F.C. ‘Broad-band UHF distributed amplifiers using band-pass filter techniques’. IRE Trans. Circuit Theory, 1960, vol. 7(5), pp. 8–17. [9] Chen W.K. ‘The effects of grid loading on the gain and phase-shift characteristics of a distributed amplifier’. IEEE Trans. Circuit Theory, 1969, vol. 16(1), pp. 134–137. [10] Chen W.K. ‘Theory and design of transistor distributed amplifiers’. IEEE J. Solid-State Circuits, 1968, vol. 3(2), pp. 165–179. [11] Gallagher J.A. ‘High-power wide-band RF amplifiers’. IRE Trans. Aerosp. Electron. Syst., 1965, vol. 1(2), pp. 141–151. [12] Enloe L.H., and Rogers P.H. ‘Wideband transistor distributed amplifiers’. IEEE International Solid-State Circuits Symposium Digest; Philadelphia, PA, Feb 1959, pp. 44–45. [13] McIver G.W. ‘A travelling-wave transistor’. Proc. IEEE, 1965, vol. 53(11), pp. 1747–1748. [14] Kohn G., and Landauer R.W. ‘Distributed field-effect amplifiers’. Proc. IEEE, 1968, vol. 56(6), pp. 1136–1137. [15] Jutzi W. ‘A MESFET distributed amplifier with 2 GHz bandwidth’. Proc. IEEE, 1969, vol. 57(6), pp. 1195–1196.

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Index

accurate device models 255 adjacent channel interference ratio (ACIR) 159 adjacent channel leakage power ratio (ACLR) 137, 159, 165, 350 adjacent channel selectivity (ACS) 159 amplitude-modulated (AM) signal 347 amplitude-to-amplitude modulation (AM–AM) performance 337 amplitude-to-phase modulation (AM–PM) characteristics 336 analog to digital converter (ADC) 394 anode termination 422 asymmetric Doherty amplifiers 102–6 asymmetric multilevel outphasing (AMO) technique 182–3 augmented complex conjugate PH (ACC-PH) model 411–12 average power tracking (APT) 138 baseband-based linearization techniques 388 base transceiver station (BTS) transmitter 345–8 behavioral modeling and linearization 345 descent-based estimators, modifications to 374–5 digital predistortion (DPD) coefficient estimation, PA saturation on 373–4 least squares (LS) estimation using batch processing 375–7 linearization 359 digital predistortion 359–67 feedforward compensation 367–71

power amplifier (PA) nonlinearities 348–50 behavioral modeling 354–9 measurements of nonlinear behavior 350–3 recursive least squares 377–82 using odd and even polynomial basis waveforms 372–3 wireless communication overview 345 base transceiver station (BTS) transmitter 347–8 radio frequency (RF) channel and channel capacity 346–7 biharmonic Class-EM power amplifier 70–6 Bode–Fano criterion 318 broadband Class-B/J mode PA design 286–8 broadband Class E with shunt capacitance 76–82 broadband continuous Class-F PA design 291–3 broadband Doherty amplifiers 122–32 broadband load impedance matching 316 broadband microwave GaN HEMT 446 broadband parallel-circuit Class E 82–90 broadband power amplifiers 312–19 broadband W-band CMOS power amplifier 313 capacitive coupling 434–5 carrier aggregation (CA) 137, 388 types of 389

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Radio frequency and microwave power amplifiers, volume 2

carrier amplifier 101 cascaded distributed amplifiers 458–62 cascaded Doherty amplifier 122 cascaded reactively terminated singlestage distributed amplifier (CRTSSDA) 460–2 cascode CMOS Class-E power amplifiers 320 cascode distributed amplifiers 449–55 cellular LTE FDD and TDD, envelope tracking for 141–2 Chireix outphasing systems 99, 177, 186–9, 226–7, 246, 250, 272, 277–80 Class-B/J continuum 281–3, 286 Class-B/J mode loads 281 Class-B PA and harmonic injection 264–7 Class-B waveforms 238 Class-E outphasing systems 203 Class-E power amplifiers 1, 323 with shunt filter 63 with transmission-line matching 61 transmission-line load network of parallel-circuit 60 Class E with finite dc-feed inductance 48 even-harmonic Class E 56–9 general analysis and optimum load-network parameters 48–52 load networks with transmission lines 59–62 parallel-circuit Class E 52–6 Class E with shunt capacitance and series filter 35 effect of saturation resistance, finite switching time, and nonlinear shunt capacitance 40–3 load network with transmission lines 43–5 optimum load-network parameters 35–40 practical Class-E power amplifiers 45–7

Class E with shunt capacitance and shunt filter 62 basic analysis and optimum load-network parameters 62–7 design example of transmission-line Class-E power amplifier 68–9 load network with transmission lines 67–8 Class-F circuit design 1 Class F with maximally flat waveforms 7–10 Class F with quarterwave transmission line 11–14 design examples of Class-F power amplifiers 19–23 effect of saturation resistance 14–16 idealized Class-F mode 3–7 load networks with lumped and distributed parameters 16–19 Class-F parallel power amplifier architecture 327–8 Class-F power amplifiers 1, 30 with series quarterwave transmission line 11 with shunt quarterwave transmission line 12 Class-F theory and design example 267–72 CMOS distributed amplifiers 462–6 CMOS power amplifiers basic structures and techniques 301–4 broadband power amplifiers 312–19 Doherty architectures 329–33 high-efficiency Class-E and Class-F power amplifiers 319–29 linearization 333–8 millimeter-wave power amplifiers 308–12 MOSFET device modeling 297–301 stacked power amplifiers 304–7 CMOS technology 137 collector efficiency 15, 41, 43, 81 combiner synthesis for active loadmodulation-based power amplifiers 225

Index applications to outphasing PA design 246 2.14 GHz GaN HEMT outphasing PA design 248–50 future outlook 251 generalized combiner synthesis technique for Doherty and outphasing PAs 227–33 novel Doherty continuous design space, applications of 234 efficiency and linearity, solving for 238–40 GaN HEMT Doherty PA design 240–5 maximum efficiency, solving for 235–8 condition number 396 conjugate 2D-MP model 412 continuous Class-B/J power amplifier 281 broadband Class-B/J mode PA design 286–8 design space analysis with nonlinear-embedding technique 282–6 continuous Class-F power amplifier 288 broadband continuous Class-F PA design 291–3 feasible design space 289–91 continuous wave (CW) performance 242 conventional amplitude-modulation techniques 99 conventional Class-AB power amplifiers 102 conventional distributed amplifiers (CDAs) 435 conventional Doherty PA designs 216, 227, 234 coplanar waveguides (CPWs) 306, 450, 463 coupled-line Lange-type power dividers 447

475

crest factor reduction (CFR) 352 cross-over memory polynomial (COMP) model 408, 415 current feedback amplifier (CFA) approach 157 current generator reference plane (CRP) 281, 283 de-embedding 256 descent-based estimators, modifications to 374–5 design space analysis with nonlinear-embedding technique 282–6 digital predistortion (DPD) 116, 209, 331, 333, 359–67, 373–4, 388, 392 -based linearizer 416 linearization 405–6 for multiband/multichannel transmission in the presence of modulator imperfections 411–15 for multiband transmission 394 dual-band DPD models 394–400 multiband DPD for harmonic distortion dual-band DPD models 402–8 tri-band and higher order DPD models 400–2 for multiple-channel transmission 408 cross-over memory polynomial 408 parallel Hammerstein (PH) model 409–11 digital signal processing (DSP) 137, 209, 392 digital-to-analog converters (DACs) 393 distortion components in MIMO transmission 390 linear distortion 391–2 nonlinear distortion 391

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Radio frequency and microwave power amplifiers, volume 2

distortion inducing elements in multichannel transmission 387–8 distortion in multiband transmission 388–90 distributed amplification, basic principles of 421–7 distributed amplifiers with tapered lines 439–49 distributed N-way Doherty amplifier 104–5 distributed power amplifiers 421 basic principles of distributed amplification 421–7 cascaded distributed amplifiers 458–62 cascode distributed amplifiers 449–55 CMOS distributed amplifiers 462–6 extended resonance technique 456–8 microwave GaAs FET and HEMT distributed amplifiers 427 bandpass configuration 435–6 capacitive coupling 434–5 lumped elements, basic configuration with 432–4 microstrip lines, basic configuration with 428–32 parallel and series feedback 437–9 with tapered lines 439–49 Doherty amplifier architecture 99–102 theoretical efficiencies of 108, 111 Doherty and outphasing combiners 228 Doherty and outphasing PAs generalized combiner synthesis technique for 227–33 Doherty architectures 107, 109–10, 329–33 Doherty-like load modulation mechanism 208 Doherty power amplifiers (DPAs) 138, 330, 236, 238, 243–4, 272 with active phase shifter 332 basic topology of 226 design example 272–7 typical realization of 226

drain efficiency (DE) 257 dual-band Doherty PA 412 dual-band DPD models 394–400 dual-band transmission, distortions in 390 dual-gate GaAs FET device 452 dual pole dual through (DPDT) silicon on insulator switch 159 efficiency enhancement techniques 198, 216, 329 efficient branch PAs 175 embedding 256 embedding model 260–3 embedding transfer network (ETN) 262 envelope elimination and restoration (EER) 137 envelope tracking (ET) techniques 137–41, 321, 333 for cellular LTE FDD and TDD 141–2 ET calibration 164–6 ET circuitry 149–59 ET noise 166–9 ET structure 147 ET systems 146–9 for high power 159–62 local ET linearization 162–3 multilevel supply envelope tracking 163–4 power amplifier with envelope tracking 138, 142–6 error amplifier (EA) 146, 149, 367 error vector magnitude (EVM) 330, 389 even-harmonic Class E 56–9 extended resonance technique (ERP) 456–8 extrinsic package reference plane 281, 283, 290–1 feedforward compensation 345, 359, 367–71 feedforward PA (FFPA) 367, 370 field effect transistors (FETs) 256, 440

Index field programmable gate arrays (FPGA)based dual-band DPD 398 floating point operation (FLOP) 400 four-cascaded single-stage distributed amplifier (4-CSSDA) 458–9 Fourier analysis 5, 26 four-stage Doherty amplifier architecture, modified 111, 113 four-stage Doherty power amplifier 110 four-stage GaN HEMT Doherty amplifier 112 four-stage integrated Doherty amplifier 119–20 GaAs FETs 427 GaAs MESFET devices 109 Gallium Nitride (GaN) 255, 399, 443 GaN HEMT device 106, 109, 117 high-power operation of 125 GaN HEMT Doherty PA design 240–5 gate-oxide breakdown 298–9 generalized combiner synthesis technique, for Doherty and outphasing PAs 227–33 global minimum 364 grid termination 422 Hermitian structure 381 heterojunction bipolar transistors (HBTs) 261–2 high-efficiency broadband power amplifiers broadband Class E with shunt capacitance 76–82 broadband parallel-circuit Class E 82–90 high-efficiency mixed-mode broadband power amplifier 90–2 high-efficiency Class-E and Class-F power amplifiers 319–29 high-efficiency Doherty power amplifiers 99 asymmetric Doherty amplifiers 102–6

477

basic Doherty amplifier structure 99–102 broadband Doherty amplifiers 122–32 integrated Doherty amplifiers 117–22 inverted Doherty amplifiers 113–16 multistage Doherty amplifiers 107–13 high-efficiency power amplifier design 1 biharmonic Class-EM power amplifier 70–6 Class E with finite dc-feed inductance 48 even-harmonic Class E 56–9 general analysis and optimum load-network parameters 48–52 load networks with transmission lines 59–62 parallel-circuit Class E 52–6 Class E with shunt capacitance and series filter 35 effect of saturation resistance, finite switching time, and nonlinear shunt capacitance 40–3 load network with transmission lines 43–5 optimum load-network parameters 35–40 practical Class-E power amplifiers 45–7 Class E with shunt capacitance and shunt filter 62 basic analysis and optimum loadnetwork parameters 62–7 design example of transmissionline Class-E power amplifier 68–9 load network with transmission lines 67–8 Class-F circuit design 1 Class F with maximally flat waveforms 7–10

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Radio frequency and microwave power amplifiers, volume 2

Class F with quarterwave transmission line 11–14 design examples of Class-F power amplifiers 19–23 effect of saturation resistance 14–16 idealized Class-F mode 3–7 load networks with lumped and distributed parameters 16–19 high-performance high electron mobility transistor (HEMT) devices 427, 431 high-power broadband inverted Doherty amplifier 131–2 high-power three-way Doherty amplifier 106 high-power three-way inverted Doherty amplifier 115 high-power two-stage broadband inverted Doherty amplifier 128 high power user equipment (HPUE) 160 high-throughput modulation schemes 388 idealized inverse Class-F mode 25–7 image-rejection ratio (IRR) 411 independent component analysis (ICA) 397 indirect learning architecture (ILA) learning scheme 392 input signal synthesis 208–10 arbitrary input drives 216 RF-input outphasing 210–16 integrated Doherty amplifiers 117–22 integrated passive device (IPD) 320 intermodulation distortion (IMD) 349, 388 intra-band contiguous scheme 389 inverse Class F 23 design example of inverse Class-F power amplifier 31–5 idealized inverse Class-F mode 25–7 inverse Class F with quarterwave transmission line 27–8

load networks with lumped and distributed parameters 28–31 inverted Doherty amplifiers 113–16 isolated lossy combiners 227 Kalman filter models 380–2 large-signal operating point (LSOP) 256, 267, 271 LDMOSFET power amplifier 19–20, 84–6, 117 least squares (LS) estimation using batch processing 375–7 linear amplification with nonlinear component (LINC) system 178, 180–3 linear distortion 391–2 linear Doherty 238, 242 linearization 333–8, 359 digital predistortion 359–67 feedforward compensation 367–71 with interstage feedback network 336 with negative RC feedback network 337 load modulation mechanisms 198–200 load modulation trajectories, ideal current source operation 200–3 switched-mode operation 203–4 load-pull contours 244 load-pull simulations 240, 247–8, 286 local oscillators (LOs) 393 long-term evolution (LTE) 387 lossless combiner, realization of 231–2 lossless harmonic termination 268 LTE-Advanced 388 lumped cascode–cascade Doherty power amplifier 331 lumped Doherty amplifier 118 main amplifier (MA) 367 maximally flat waveforms, Class F with 7–10 maximum available gain (MAG) 434

Index mean square error (MSE) 351 memory polynomial (MP) 354 MESFET distributed amplifier 452–3, 456–7 metal-insulator-metal (MIM) capacitors 117, 442 microwave GaAs FET and HEMT distributed amplifiers 427 bandpass configuration 435–6 basic configuration with lumped elements 432–4 basic configuration with microstrip lines 428–32 capacitive coupling 434–5 parallel and series feedback 437–9 Miller effect 238 millimeter-wave CMOS power amplifiers 337 millimeter-wave power amplifiers 308–12 mixed-mode outphasing 177, 183, 191, 213, 215 model-conditioning methods 417 model-pruning methods 417 monolithic microwave integrated circuit (MMIC) 117, 120, 432 MOSFET device modeling 45, 84, 104, 297–301, 427 multiband DPD for harmonic distortion dual-band DPD models 402–8 multiband/multichannel power amplifier linearization 387 application considerations of DPD models for multiband/ multichannel transmission 415–17 digital predistortion techniques 392 for multiband/multichannel transmission in the presence of modulator imperfections 411–15 for multiband transmission 394–408 for multiple-channel transmission 408–11

479

distortion components in MIMO transmission 390 linear distortion 391–2 nonlinear distortion 391 distortion inducing elements in multichannel transmission 387–8 distortion in multiband transmission 388–90 multiband processing versus broadband processing 393–4 multiband transmission, distortion in 388–90 multiband/wideband designs 251 multichannel transmission 387 digital predistortion techniques for 411–15 distortion inducing elements in 387–8 multi-drive stacked CMOS power amplifier 312 multilevel LINC (ML-LINC) approach 182 multilevel supply envelope tracking 163–4 multiple input multiple output (MIMO) techniques 137, 388 distortion components in 390 multistage architecture, extension to 251 multistage Doherty amplifiers 107–13 multiway power combining networks 192–7 mutual coupling 391 vacuum-tube distributed amplifier with 424 neural network (NN) model 412 NN-based DPD model training 417 performance as DPD model for modulator imperfection and MIMO transmission 412 nMOS transistors 301, 305, 334, 338 nonlinear distortion 391

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Radio frequency and microwave power amplifiers, volume 2

nonlinear embedding 255–6, 261 motivation for 257–60 normalized mean square error (NMSE) 389 Norton transformation 317 novel Doherty continuous design space, applications of 234 GaN HEMT Doherty PA design 240–5 solving for efficiency and linearity 238–40 solving for maximum efficiency 235–8 N-way Doherty amplifier 103–4 odd and even polynomial basis waveforms 372–3 on-chip transmission-line fabrication in CMOS technology 327 orthogonal frequency division multiplexing (OFDM) signal 349 out-of-band (OOB) distortion 389–90 outphasing power amplifiers 175, 227, 246–50 generalized combiner synthesis technique for 227–33 history 177 1935–1960: origins 177 1974: linear amplification with nonlinear components (LINCs) 178 2000s: resurgence in interest 178 ideal load modulation trajectories 200 current source operation 200–3 switched-mode operation 203–4 implications for outphasing PA design 208 input signal synthesis 208–10 arbitrary input drives 216 RF-input outphasing 210–16 load modulation mechanisms 198–200

optimal load trajectories with nonlinear model 205–8 outphasing operation 179 Chireix combining 186–9 isolating combining 180–3 mixed-mode operation 189–91 nonisolating combining 183–6 power combiner variants 191 co-design of PAs and combiner 197–8 multiway power combining networks 192–7 PA-antenna integration 251 parallel-circuit Class E 52–6 parallel Hammerstein (PH) model 409–11, 415 parallel resistive feedback 438 peaking power amplifier 101 peak-to-average power ratio (PAPR) 137, 139, 225, 374 peak-to-backoff power ratio (PBPR) 278 pMOS device 334 pMOS transistor 334, 338 power-added efficiency (PAE) 102, 139, 242–4, 280 power amplifier (PA) 139, 225, 388 with envelope tracking 138, 142–6 power amplifier (PA) design based on nonlinear embedding models 255 Chireix PA design example 277–80 Class-B example and harmonic injection 264–7 Class-F theory and design example 267–72 continuous Class-B/J power amplifier 281 broadband Class-B/J mode PA design 286–8 design space analysis with nonlinear-embedding technique 282–6

Index continuous Class-F power amplifier 288 broadband continuous Class-F PA design 291–3 feasible design space 289–91 Doherty PA design example 272–7 embedding model 260–3 motivation for nonlinear embedding 257–60 power amplifier (PA) nonlinearities 348–50 behavioral modeling 354–9 measurements of nonlinear behavior 350–3 power combiner variants 191 co-design of PAs and combiner 197–8 multiway power combining networks 192–7 power combining network 175 power combining techniques 302 power GaAs HBT devices 102 principle component analysis (PCA)-based pruned 2D-MP model 396 probability density function (PDF) 146 prototype Chireix PA 278–9 pseudomorphic HEMT (pHEMT) amplifier 439 push–pull Class-E CMOS power amplifier 325 quadrature amplitude modulation (QAM) 349, 388 quadrature phase shift keying (QPSK) 349 quarterwave transmission line Class F with 11–14 inverse Class F with 27–8 R&S FSW spectrum analyzer 406 radio frequency (RF) channel and channel capacity 346–7

481

radio frequency (RF) chokes 302 radio frequency (RF) transmitters 175, 389 radio frequency integrated circuits (RFIC) 262 recursive least squares (RLS) method 377–82 regularization 357 resistance compression network (RCN) 182 reverse termination 422 RF cycle 258 RF-input outphasing (RFIO) approach 211–13 semiconductor on insulator metal oxide semiconductor FET (SOI-MOSFETs) 260, 262 serial reactance realization using transmission line networks 233 Shannon formula 161 shunt capacitance and shunt filter, Class E with 62 basic analysis and optimum load-network parameters 62–7 design example of transmission-line Class-E power amplifier 68–9 load network with transmission lines 67–8 SiGe BiCMOS stacked distributed amplifier 456 signal component separators (SCSs) 175, 178 signal to noise ratio (SNR) 141 Silicon Carbide (SiC) process 443 silicon-on-insulator (SOI) CMOS process 306, 463 silicon–silicon dioxide (Si–SiO2) interface 299 singular value decomposition (SVD) 356 slew rate (SR) 152–4 Smith Chart 259 software-defined solutions 392

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Radio frequency and microwave power amplifiers, volume 2

spectral regrowth 389 spectrum efficiency 388 spectrum-saving techniques 388 spurious emissions 390 stacked power amplifiers 304–7 system-on-chip (SOC) 146 10-GHz monolithic GaN HEMT Doherty amplifier 121 thick-oxide nMOS devices 300 thick-oxide transistors 302 Third Generation Partnership Project (3GPP) 388 three-cell GaAs FET distributed amplifier 435 3D-HMP model 403–5 3D-HVS model 405, 408 3D-MP model 400 3D-phase aligned pruned Volterra model (3D-PAV) 401 three-stacked CMOS power amplifier 312 three-stage cascode CMOS power amplifier 308 three-stage Doherty amplifier 107, 109 with 3-way splitter and two hybrid 3-dB couplers 110 three-stage integrated Doherty amplifier 119 three-stage inverted Doherty amplifier configuration 116 three-way Doherty amplifier 104 total FET periphery 435 transformer-coupled CMOS power amplifier 304 transmission-line GaN HEMT high-power inverted Doherty amplifier 131 tri-band and higher order DPD models 400–3

tri-band inverted Doherty amplifier simulated power gain and drain efficiencies of 126 test board of 127, 130 tri-band inverted GaN HEMT Doherty amplifier 123–5 24-GHz monolithic two-stage pHEMT Doherty amplifier 122 2D memory polynomial (2D-MP) model 395–6 independent component analysis-based conditioning of 397 2D-MP-ICA 398 2D-orthogonal memory polynomial (OMP) model 396, 400 2.14 GHz GaN HEMT outphasing PA design 248–50 two-port network parameters, calculation of 228–9 two-stage integrated Doherty amplifier 119 uniform distributed amplifier 441 user equipment (UE) 345 vector modulator (VM) 367 voltage feedback amplifier (VFA) 157 voltage standing wave ratio (VSWR) 84, 452 Volterra series (VS) 355 WCDMA/LTE signals 333 wideband monolithic GaN HEMT Doherty power amplifier, test chip of 121 Wilkinson power divider 447 wireless communication overview 345 base transceiver station (BTS) transmitter 347–8 radio frequency (RF) channel and channel capacity 346–7