Low Power Wireless Receivers for IoT Applications with Multi-band Calibration Algorithms [1 ed.] 3030707288, 9783030707286

Table of contents :
Preface
References
Contents
About the Authors
Chapter 1: Calibration Overview
Chapter 2: SAR A/D Converter
2.1 SAR A/D Converter Implementation
2.2 Digital-to-Analog Converter Design Considerations
2.3 Rail-to-Rail Input Comparator
2.4 Low-Voltage Class AB Operational Amplifier
Chapter 3: Calibration Filter
3.1 Programmable Filter Stage
3.2 Programmable Capacitor with Coarse and Fine Resolution
3.3 Fully Differential OPAMP with Common Mode Control
Chapter 4: Clock Dividers
4.1 Reference Divider
4.2 Divide-by-40 Counter
Chapter 5: Phase-Frequency Detector with No Dead Zone
Chapter 6: Charge Pump with Four Programmable States
Chapter 7: Fifth-Order Chebyshev Tunable Filter
Chapter 8: Filter Calibration Results
Chapter 9: WLAN Receiver Front End
9.1 RX-TX Switch
9.2 Low-Noise Amplifier
9.3 Voltage-to-Current Converter
9.4 Sampling Down-Converter
9.5 Trans-impedance Amplifier
Chapter 10: WLAN Front-End Performance
Appendices
Appendix A: TIA Supplemental Analysis
CMOS LNA Design Considerations
Classical Two-Port Noise Model
MOSFET LNA Noise Model
Impedance Matching
Gain Control
Appendix C: Bipolar LNA Noise Optimization
Bipolar Transistor Noise Model
Bipolar Transistor Frequency Response
Minimum Noise Figure
Optimum Source Impedance
Impedance Matching
Linearity and Distortion Analysis
Effects of Feedback on Distortion
Appendix D: Folded Cascode OPAMP Design
Foundry Process and Constants
Slew Rate
Input Stage
Noise Analysis
The Cascode Stage
Class AB Output Stage
Bias Circuits
Appendix E: Thermometer Decoder (Topology)
References
Index

Citation preview

Michael W. Rawlins

Low Power Wireless Receivers for IoT Applications with Multi-band Calibration Algorithms

Low Power Wireless Receivers for IoT Applications with Multi-band Calibration Algorithms

Michael W. Rawlins

Low Power Wireless Receivers for IoT Applications with Multi-band Calibration Algorithms

Michael W. Rawlins Lake Mary, FL, USA

ISBN 978-3-030-70728-6 ISBN 978-3-030-70729-3 https://doi.org/10.1007/978-3-030-70729-3

(eBook)

© The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2021 This work is subject to copyright. All rights are solely and exclusively licensed by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors, and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, expressed or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Switzerland AG The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland

This book is dedicated in loving memory of author Michael W. Rawlins, whose life’s work went into creating and writing this book. His desire was to give the reader detailed design instruction that could be immediately applied to what they learned. Special thanks and acknowledgment to Michael’s brother, Greg Rawlins (Ph.D.), and Hajnal Rawlins who stepped in with editing the completed manuscript and the submission process to see the book to completion after Michael’s passing.

Preface

As one considers how the Internet impacts so many activities in daily life, it is difficult to imagine how the modern world would function without it. The Internet helps facilitate education, personal and business communication, interstate commerce, travel, scientific research, and various government functions. Humans derive much, if not most, of their daily news from the Internet. In 2020, with a current world population of 7.8 billion, approximately 4.6 billion people have access to and use the Internet frequently [1]. As more and more humans make use of the Internet, the number of Internet-connected devices is also increasing. With billions of computers, cellular phones, industrial machines, and appliances connected to the Internet, we find ourselves in the era of the Internet of Things (IoT). According to research from Strategy Analytics, by the end of 2018, the number of devices connected to the Internet reached 22 billion. The number of IoT devices is expected to reach 38.6 billion by 2025, and 50 billion by 2030 [2]. This number of network-connected devices is being driven by desire for automation and data analytics as the demand increases for various commercial, industrial, and infrastructure products. Smart home applications, industrial and banking security, wearable technology, connected health, and industrial appliances are all facilitated by the Internet of Things (IoT) network. Many of these products support remote monitoring and control capabilities via wireless interface. Devices are often portable and battery powered, having requirements for low power consumption and long battery life while providing desired performance and adequate connectivity. Wearable devices like smart watches and health monitors carry these constraints along with the need to integrate most circuit functions on a single chip to conserve space. Modern deep-submicron CMOS processes facilitate dense integration of radio frequency, analog, digital, and mixed-signal functions on a single die. This work provides design details for such an application, implementing a low-power wireless receiver fabricated in a popular 28nm CMOS process which considers the aforementioned challenges and constraints. All circuits are designed using a sub-1V power supply. vii

viii

Preface

Chapter 1 provides an overview of a filter calibration approach applicable to a tunable filter used in a wireless LAN (WLAN) receiver. Chapters 2, 3, 4, 5, 6 and 7 detail the implementation of the calibration algorithm and provide design insights for the various components of the calibration loop. Designs include a successive approximation A/D converter; an 80 MHz tunable baseband filter; low-voltage, class-AB operational amplifier design; a rail-to-rail input comparator; 5-bit thermometer encoder; and more. Chapter 8 demonstrates the performance limits of the calibration loop. Chapter 9 guides the reader through the design of a 2.4 GHz wireless-LAN receiver. Circuit details are provided for a low noise amplifier (LNA) having 6 programmable gain states with 30 dB of dynamic range. An RF voltage-to-current converter (RF-V2I) is shown having two programmable gain states with 12 dB of dynamic range. A very linear and low-power sampling downconverter loaded with a transimpedance amplifier (TIA) is demonstrated, converting RF to baseband. Chapter 10 provides performance details of the receiver. Several appendices are included which help navigate the reader through design and performance tradeoffs. Included is a detailed TIA analysis, noise figure, distortion analysis and impedance matching of both CMOS and Bipolar LNAs, and a folded-cascode operational amplifier design approach. Lake Mary, FL, USA

Michael W. Rawlins

References 1. Internet world stats, usage and population statistics. https://internetworldstats. com/stats.htm 2. Mercer D (2019) Global connected and IoT devices forecast update. https://www. strategyanalytics.com/. May 14, 2019

Contents

1

Calibration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1

2

SAR A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 SAR A/D Converter Implementation . . . . . . . . . . . . . . . . . . . . 2.2 Digital-to-Analog Converter Design Considerations . . . . . . . . . 2.3 Rail-to-Rail Input Comparator . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Low-Voltage Class AB Operational Amplifier . . . . . . . . . . . . .

. . . . .

5 5 7 11 15

3

Calibration Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Programmable Filter Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Programmable Capacitor with Coarse and Fine Resolution . . . . 3.3 Fully Differential OPAMP with Common Mode Control . . . . . .

. . . .

19 19 20 24

4

Clock Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Reference Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Divide-by-40 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

29 29 30

5

Phase-Frequency Detector with No Dead Zone . . . . . . . . . . . . . . . .

33

6

Charge Pump with Four Programmable States . . . . . . . . . . . . . . . .

37

7

Fifth-Order Chebyshev Tunable Filter . . . . . . . . . . . . . . . . . . . . . .

43

8

Filter Calibration Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

49

9

WLAN Receiver Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 RX-TX Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Low-Noise Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 Voltage-to-Current Converter . . . . . . . . . . . . . . . . . . . . . . . . . 9.4 Sampling Down-Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5 Trans-impedance Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . .

61 61 64 69 70 72

10

WLAN Front-End Performance . . . . . . . . . . . . . . . . . . . . . . . . . . .

75

ix

x

Contents

Appendices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix A: TIA Supplemental Analysis . . . . . . . . . . . . . . . . . . . . . CMOS LNA Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . Classical Two-Port Noise Model . . . . . . . . . . . . . . . . . . . . . . . MOSFET LNA Noise Model . . . . . . . . . . . . . . . . . . . . . . . . . . Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix C: Bipolar LNA Noise Optimization . . . . . . . . . . . . . . . . . Bipolar Transistor Noise Model . . . . . . . . . . . . . . . . . . . . . . . . Bipolar Transistor Frequency Response . . . . . . . . . . . . . . . . . . Minimum Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Optimum Source Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linearity and Distortion Analysis . . . . . . . . . . . . . . . . . . . . . . . Effects of Feedback on Distortion . . . . . . . . . . . . . . . . . . . . . . Appendix D: Folded Cascode OPAMP Design . . . . . . . . . . . . . . . . . Foundry Process and Constants . . . . . . . . . . . . . . . . . . . . . . . . Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Noise Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Cascode Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class AB Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bias Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix E: Thermometer Decoder (Topology) . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . .

79 79 81 81 83 85 87 88 88 89 91 92 93 94 97 99 100 100 102 105 106 108 110 112

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

About the Authors

Michael W. Rawlins was an electrical engineer with 30 years of experience and a patent contributor on more than 100 patents. He graduated from the University of Central Florida in 1989 with a BSEE, emphasis on communication systems theory and analog circuit design. Upon graduation, Michael Rawlins completed additional studies in digital signal processing and random processes. He is recognized by the State of Florida as an Engineer Intern, 1990, No. 489ET333. He began his career with Emerson Electronics and Space while finishing his degree. Michael was a co-founder of Signal Technologies Inc., where he designed discrete and integrated communications subsystems for both government and commercial customers. Michael continued his career with ParkerVision Inc., where he assisted with architecture and design of the “Signal-Max” wireless-LAN family of products. During his time at ParkerVision Inc., he designed integrated transmitter and receiver systems targeting cellular and other wireless applications. Michael was also employed by Lockheed Martin Corporation, working on various programs. Dedicated husband and father (1959-2020).

xi

Chapter 1

Calibration Overview

Filter calibration methods have been cited in literature from pre-tuning a set of filter coefficients that are stored in memory to using precision R-C standards, or applying phase-locked-loop (PLL) techniques in a mixed-signal servo loop. Another commonly used method, detailed in the following chapters, incorporates a quadrature automatic frequency tuning loop with a master-slave filter [1–3]. A high-level block diagram of the proposed calibration approach is shown in Fig. 1.1. Following is the description of the system and circuit functions performing the algorithm. A 40-MHz logic level clock is divided by a factor of eight and used to generate quadrature 5-MHz differential clock signals, 200 mV in amplitude centered about a common mode level of VDD/2, where VDD is the single 900-mV power supply voltage. A single-ended 5-MHz logic level clock is also generated, which is further divided by 40 and used to create a delayed calibration start signal initiating a 5-bit successive approximation analog-to-digital converter. A differential clock of 0/180 phase drives a master filter that is used to measure time constants in the calibration algorithm. This master filter is one quadratic section copied from a fifth-order, continuous-time, Chebyshev baseband filter, with the goal of removing errors caused by process variations of the resistors and capacitors. The nominal cutoff frequency for the master filter is set to 5 MHz. Although this is not one of the channel selections for the slave filter (ultimate filter to be calibrated), it serves as an adequate standard and provides for the desired calibration accuracy to within 5%, over temperature and process, of the desired filter cutoff frequency. If resistors and capacitors within the quadratic filter section are of nominal value (i.e., the resistors and capacitors have the values the designer intended), then the 0/ 180 differential inputs to the master filter arrive at the filter outputs phase shifted by 90 /270 respectively. Given the signal frequency to the master filter is 5 MHz, the resulting delay through the filter will measure 50 ns when perfectly calibrated. This allows for comparison against an “ideal” 90/270 clock standard to determine if the filter is in calibration. A delay is inserted in the 90/270 signal path to compensate for differences in the master filter and quadrature comparison paths. These differences may result from routing variances and from propagation delays in the active devices © The Author(s), under exclusive license to Springer Nature Switzerland AG 2021 M. W. Rawlins, Low Power Wireless Receivers for IoT Applications with Multi-band Calibration Algorithms, https://doi.org/10.1007/978-3-030-70729-3_1

1

2

1 Calibration Overview

Fig. 1.1 Block diagram of filter calibration

themselves. The delay is adjusted under nominal conditions with the pd-r and pd-n inputs set so they are in phase with no error. During filter calibration, if the R-C (resistor-capacitor) product is greater than nominal, delay time through the filter will measure more than 50 ns. The system is linear, so if the R-C product is 10% larger than nominal, for example, then the delay through the master filter will be 55 ns. Likewise, if the R-C product is 10% less than nominal, the delay through the master filter will be 45 ns. The differential master filter analog outputs are converted to a single-ended, logic level output by a comparator. Likewise, the differential 90/270 clock standard outputs are converted to a single-ended, logic level output by a comparator. These limited, logic level signals are then processed by a phase-frequency detector (PFD). The phase-frequency detector facilitates comparison of delay or phase differences between the master filter and the quadrature clock standard, thereby generating an error signal proportional to the correlation of the two signals. The phase-frequency detector outputs are connected to a charge pump, which provides a single-ended output current relative to the difference in delay between the master filter and the quadrature clock standard. This error signal is then converted to a voltage using an error amplifier. The error is then scaled, averaged, and digitized by a successive approximation analog-to-digital converter (SAR-ADC). The error amplifier is an inverting operational amplifier with the reference terminal connected to a voltage of VDD/2. The gain of the amplifier is set to make use of the full 0–900 mV input range of the SAR-ADC. This span allows for calibration of errors in the master filter R-C network of 30%. The charge pump contains programmability to adjust the gain constant (span) due to process variations in the error amplifier feedback resistor. For better accuracy, the feedback resistor may be placed off-chip. The SAR-ADC converts the analog error voltage to a 5-bit, parallel digital word. Conversion begins after receiving a “start” command from a divide-by-40 counter. This divide-by-40 counter provides adequate time for the error voltage to settle before the calibration cycle begins. Once the start command is received, the SAR-ADC converts MSB to LSB at the SAR clock conversion rate until the error voltage is approximated. An “end-of-conversion flag” signals the conversion is

1 Calibration Overview

3

complete, and the final digital value is latched into output registers. This 5-bit digital word sets the inputs to programmable capacitor banks inside the master filter, thus adjusting time constants and finishing the calibration.

Chapter 2

SAR A/D Converter

2.1

SAR A/D Converter Implementation

As described in Chap. 1, a 5-bit successive approximation analog-to-digital converter (ADC) digitizes the analog error voltage (Vin) to a 5-bit digital word, where Vin serves as a control signal in the filter calibration algorithm. Given the digital-toanalog converter (DAC) reference is 900 mV (see Fig. 2.1 below), the smallest step size (LSB) is equal to VREF , where N is the resolution of the data converter. Thus, the 2N minimum step for the 5-bit SAR-ADC described in this book is 28.125 mV. Figure 2.2 details all possible 2N
1 levels within the digital-to-analog converter search range. Each level illustrates a path the DAC output voltage can traverse when approximating the analog input voltage Vin with VREF ¼ 900 mV. A specific example is provided in Fig. 2.3, which illustrates the 5-bit digital output code relative to the analog input (Vin) and the DAC output (Vout). It is only possible to approximate Vin to within the resolution of the DAC, i.e., 1 LSB; therefore, other applications may require greater than the 5-bit resolution provided here. The SAR algorithm initiates by asserting a logic level high to the START input, which begins conversion. The signal is initially low and goes high for the duration of the conversion process. The START signal sets the MSB (bit 4) of the SAR-ADC to a logic 1, while bits 3–0 are reset to logic 0. Consequently, on the next clock cycle, Vout of the digital-to-analog converter transitions to a mid-scale value of VREF/2. A comparator evaluates the output of the DAC against the analog input signal Vin. If Vin is lower than the DAC mid-scale voltage of 1/2 VREF, as is the case in the example given in Fig. 2.3, then the output of the comparator is a logic 0. On the rising edge of the next SAR CLK cycle, the MSB (bit 4) transitions to a logic 0. The MSB value is now established. Meanwhile, a shift register, which was set to a logic 1 at the beginning of the conversion cycle, propagates that logic 1 and sets bit 3 high. The DAC output transitions to 1/4 VREF, and comparison is made once again with the analog voltage Vin. Because Vout of the DAC is lower than Vin, the output of the comparator transitions to a logic 1. Since the comparator latched output (SDATA) is © The Author(s), under exclusive license to Springer Nature Switzerland AG 2021 M. W. Rawlins, Low Power Wireless Receivers for IoT Applications with Multi-band Calibration Algorithms, https://doi.org/10.1007/978-3-030-70729-3_2

5

6

Fig. 2.1 Successive approximation A/D converter block diagram

Fig. 2.2 Digital-to-analog converter search paths

2 SAR A/D Converter

2.2 Digital-to-Analog Converter Design Considerations

7

Fig. 2.3 DAC approximation of Vin

high, on the next clock cycle, bit 3 remains high and is now established. Next, a logic 1 propagates through the register setting bit 2 to a logic 1 and causing the output of the DAC to transition positively by a step of 1/8 VREF. The process continues until the logic 1 propagating through the shift register sets each of the remaining bits. Meanwhile, the output of the digital-to-analog converter converges on the voltage Vin with an accuracy of [1=2N]∙VREF. Once conversion is complete, all digital bits 4–0 are latched into a data register and presented at the SAR-ADC outputs Q4–Q0 (Fig. 2.4). A timing relationship is shown in Fig. 2.5. Both SAR and D/A clocks run at 1MSPS.

2.2

Digital-to-Analog Converter Design Considerations

A digital-to-analog converter architecture is based on a 5-bit, R-2R ladder network. This approach is low power, compact, and simple to integrate into a larger system on chip (SOC). Integrated resistors provide good matching and excellent thermal tracking. Using an R-2R ladder to establish binary weighted currents along with proper switch design virtually guarantees the DAC transfer characteristic is

8

2 SAR A/D Converter

Fig. 2.4 Successive approximation register (5 bit)

monotonic. Resistors having the same value, the same aspect ratio, and the same orientation are used to implement the R-2R network shown in Fig. 2.6 below. Current flow in the ladder is from VREF to the rightmost vertical “2R” resistor with I0 and the ladder termination resistor (Iterm) having equal currents. The currents in each vertical branch are established as VREF VREF VREF VREF VREF , I3 ¼ , I2 ¼ , I1 ¼ , I0 ¼ , Iterm 2R 4R 8R 16R 32R VREF ¼ 32R

I4 ¼

ð2:1Þ

NMOS transistors (Fig. 2.7) are used for the current switches. Because currents are binary weighted, drain-source voltages of the current steering transistors will decrease from left to right if no special measures are taken [4]. This would result in nonlinearity in the response, and the transfer function may be non-monotonic. For this reason, the switches are also binary weighted maintaining the same current densities in all switches (when they are on) and the same drain-to-source (vds)

2.2 Digital-to-Analog Converter Design Considerations

9

Fig. 2.5 SAR-ADC timing relationships

voltage across each switch. For matching considerations, all transistors are multiples of a “unit device” used in the LSB path. Channel resistance, or “on-resistance,” of the switches is highly dependent on the amount of gate overdrive. On-resistance is given by the following equation:

10

2 SAR A/D Converter

Fig. 2.6 DAC, R-2R resistor ladder

Fig. 2.7 DAC current switches

Ron ¼

1
 μn C ox WL V gs
V th

ð2:2Þ

where μn is the electron mobility, Vth is the threshold voltage, Cox is the oxide capacitance, and Vgs is the gate-to-source voltage. “W” and “L” are the width and length of the channel, respectively, and are parameters under the designer’s control. Ron has two temperature-dependent parameters, μn and Vth. The threshold voltage Vth is highly temperature dependent approximated by the following expression: V th ðT Þ ¼ V th ðT 0 Þ
αðT
T 0 Þ,

ð2:3Þ



where α is approximately
2.3mV/ C and is dependent on the substrate doping level and implant dose during fabrication. Temperature dependence of the carrier mobility is given by [5]: 

T μðT Þ ¼ μðT 0 Þ T0


1:5

ð2:4Þ

The temperature dependences we just examined and the 900-mV power supply present a challenge to designing switches with low on-resistance while minimizing die area. To allow for greater gate overdrive while achieving these goals, low threshold voltage (low Vth) devices are used. In this design, the LSB switch of the digital-to-analog converter has an on-resistance of about 145 Ohms. A test bench to measure the transfer function for the DAC is shown in Fig. 2.8. A binary input code is applied to D0–D4, while the converter is clocked at 1 MHz (see

2.3 Rail-to-Rail Input Comparator

11

Fig. 2.8 DAC test bench

Fig. 2.10). The output of the converter is translated from a current to a voltage by OPAMPs which level shift the output around a common mode voltage of VDD/2. Having the input positive terminals of the level shifting amplifiers held to the common mode voltage (VCM) forces, through feedback, the negative terminals of the amplifiers to be held at the same potential. This maintains a constant voltage across the internal R-2R ladder and current switches to provide better linearity. A third amplifier takes the difference between the positive and negative level shifted DAC outputs resulting in the final transfer characteristic (Vout) shown in Fig. 2.9. The feedback resistors of the level shifting amplifiers have the same value “R” as used in the R-2R ladder. These resistors are integrated in close proximity to the resistors in the R-2R ladder network while having the same orientation (Fig. 2.10).

2.3

Rail-to-Rail Input Comparator

The comparator is a decision circuit that provides a binary output based on a comparison between two analog inputs. In the SAR-ADC, the output of the DAC is connected to the inverting terminal of the comparator, while the analog signal of interest to be digitized is connected to the non-inverting terminal as shown in Fig. 2.11 below. The use of a single 900-mV power supply limits the available headroom, so the comparator is designed to accommodate rail-to-rail inputs. Although there are several ways to achieve rail-to-rail input compliance, a simple and robust approach is chosen that maintains reasonably constant gm. The simplified circuit diagram of Fig. 2.11 illustrates the “current spillover method” selected (Fig. 2.12).

Fig. 2.9 DAC transfer function

Fig. 2.10 DAC test bench timing diagram

Fig. 2.11 Comparator

D/A Vout

-

Vin

+

SDATA

2.3 Rail-to-Rail Input Comparator

13

Fig. 2.12 Input stage with current spillover [6]

Transistors M5 and M6 provide the “spilling control” by steering excess current not needed by the input pairs M1, M3 and M2, M4 into the supply rails. When biased in the middle of the common mode range where VCM ¼ Vb, most of the reference current is steered through M5 and M6 where I5 ¼ I6 ¼ 6Iref. Currents through pairs M1, M3 and M2, M4 are equal with the following relationship I1 ¼ I2 ¼ I3 ¼ I4 ¼ Iref. The transconductance of the two input pairs in parallel is gmp þ gmn ¼ 2gmref , where gmref ¼

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2Iref ∙ μCox W=L

ð2:5Þ

For high-input common mode voltages, the N-channel pair operates, while the P-channel pair is off. In this condition, the bias current of the P-channel pair flows completely through M5. In this region, I1 ¼ I3 ¼ I6 ¼ 0, I2 ¼ I4 ¼ 4Iref, and I5 ¼ 8Iref. For low-input common mode voltages, the P-channel pair operates, while the N-channel pair is off, with all the N-channel bias current flowing through M6. In this region, I2 ¼ I4 ¼ I5 ¼ 0, I1 ¼ I3 ¼ 4Iref, and I6 ¼ 8Iref. In these two modes of operation, the transconductance of the input pairs in parallel is the same as when VCM ¼ Vb where

14

2 SAR A/D Converter

gm

total

¼ 2gmref

However, near the end of the common mode range when both input pairs are still active, yet one pair is near cutoff, I1 ¼ I30, I2 ¼ I4 ¼ 3Iref, and the current through M6 ¼ 2Iref or I2 ¼ I40, I1 ¼ I3 ¼ 3Iref, and the current through M5 ¼ 2Iref. The transconductance of the two pairs in parallel then is gmp þ gmn ¼

pffiffiffi 3gmref

ð2:6Þ

Note that this is about 13% lower than the 2gmref when the input common mode voltage is equal to the reference voltage Vb [6, 7]. From the previous description, it is clear this feedforward method is not the lowest power approach, but it does allow for high speed given no feedback loop is needed where delay would be introduced. The P-channel devices M1, M3 are chosen “K” times wider than the N-channel devices due to the differences in mobility between NMOS and PMOS devices by the relationship: μn ¼ Kμp , where K is a constant

ð2:7Þ

The comparator input stage is a folded cascode followed by a second gain stage and an inverter (Fig. 2.13). The circuit is designed to have a gain of 60 dB so it is capable of resolving < 1 mV inputs and translate to a 900-mV logic level output. Although the LSB of the SAR-ADC is only 28.125 mV, the analog input voltage can reside anywhere within the analog input range of the comparator. It is possible, even

Fig. 2.13 Transconductance as a function of common mode input [7]

2.4 Low-Voltage Class AB Operational Amplifier

15

Fig. 2.14 Rail-to-rail comparator schematic

probable, that the analog input Vin will be at or very near the LSB boundary. As the SAR-ADC attempts to approximate the analog input, eventually the DAC will converge on a voltage very near Vin. The comparator is sensitive enough to make a decision that is within 1 mV of any allowed state associated with the search paths shown in Fig. 2.2. In practice, the comparator is non-ideal and will suffer from transistor mismatches that result in input offset voltage. Furthermore, Vin can be noisy, causing the comparator to chatter or glitch as the D/A converter approximates Vin. For these reasons, a data latch follows the comparator to prevent false decisions that may occur due to noise on Vin or during transitions where glitches (overshoot or undershoot) may occur as the DAC is settling. The output of the comparator is only examined on the rising edge of the SAR clk. Furthermore, hysteresis is built into the comparator, which can be asserted by choice of an external resistor in series with the analog input Vin. The upper and lower trip points can be set by the following relationships:  V TRPþ ¼

   Rin Rin V OH , V TRP
¼ V Rin þ 1:1MΩ Rin þ 1:1M Ω OL

ð2:8Þ

where VOH ¼ 450mV and VOL ¼
450mV. The variable “Rin” is the designer’s choice to select a desired hysteresis window. With Rin ¼ 25KΩ, the hysteresis window is ~ 10 mV (Fig. 2.14).

2.4

Low-Voltage Class AB Operational Amplifier

A simplified schematic of a class AB output operational amplifier (OPAMP) is shown in Fig. 2.15. The amplifier is used to convert the DAC output current to a voltage and to create a full-scale output spanning 0–900 mV. This allows the SAR-ADC to use the full available dynamic range. The 900-mV supply voltage strongly influences the OPAMP topology. In this system, the OPAMP input common mode range remains near VDD/2, while the output must provide a rail-to-rail compliance. A desire to maintain high open loop gain for DC accuracy and to facilitate a complementary, rail-to rail output encourages the use of a folded-cascode topology with class AB control.

16

2 SAR A/D Converter

Fig. 2.15 Class AB OPAMP with minimum selector

A traditional feedforward class AB control loop cannot be employed due to lack of headroom. Generally, these techniques require about 2Vgs + 1 Vdsat adding up to between 1.5 and 1.6 V depending on process. So feedback class AB biasing is used where the currents through M1 and M2 (see Fig. 2.15) are measured and compared in a circuit known as a minimum selector. M12 measures the current in M2, and M11 measures the current in M1. The minimum selector comprised of M11, M15, and M17 determines IM (minimum current) corresponding to the smaller of the currents flowing either through M1 or M2. The output current of the minimum selector IM11 flows through M13. The resulting voltage across diode connected M13 is compared against a reference voltage VAB and the error is amplified. The difference amplifier M4 and M6 serves to regulate the gates of the output transistors M1 and M2. The class AB feedback loop forces current IM13 to equal the reference current IAB. Most of the time, M15 operates in the linear region. This is the case when current through the output stage is in the quiescent state. In this region of operation, M15 and M11 behave as a single transistor with double length. This causes the current through M12 and M17 to be a factor of two larger than the current through M13 if transistor aspect ratios are designed properly. Since the loop forces the current IAB to flow through M13, IAB also flows through M11 and M15. IAB is under the designer’s control. The quiescent current flowing in the output stage is a constant “2n” times IAB. The output transistors are sized as M1 ¼ nM11 and M2 ¼ nM12. The P-channel device is designed wider than the N-channel device according to the relationship described in Eq. 2.3. The quiescent current in the output stage is defined by the following relationship:

2.4 Low-Voltage Class AB Operational Amplifier

17

Fig. 2.16 Class AB output response and relationship between Iq and Imin

 IQ ¼ 2

   W 2 L12 W L I AB ¼ 2 1 11 I AB L2 W 12 L1 W 11

ð2:9Þ

When M1 sources current, its gate-source voltage will increase. The gate voltage of current sense transistor M11 follows. As the current through M1 becomes large, the voltage between the positive rail and the source of M11 will be sufficient to allow M15 to operate in saturation. Under this condition, M17, M15, and M11 operate as a cascoded current mirror and therefore mirror the current flowing through M12 to M13. The current through M12 is then regulated to one-half its quiescent state value, driving the current IM12 ¼ IM13 ¼ IAB (Fig. 2.16). When M2 sinks current, its gate-source voltage increases. The gate of M12 follows, causing current to increase in M12 and M17. When the current though M2 gets large, M15 pulls the source of M11 to the positive supply. M1 and M11 now operate as a current mirror with the current of M1 attenuated by a factor of “n” according to the following relationship: M 11 ¼ M 1=n

ð2:10Þ

Consequently, M1 is regulated to one-half of its quiescent state value yielding the minimum current [8]  I min ¼

   W 2 L12 W 1 L11 1 I AB ¼ I ¼ I L2 W 12 L1 W 11 AB 2 Q

ð2:11Þ

For this to hold, M1 M ¼ 2 M 11 M 12

ð2:12Þ

18

2 SAR A/D Converter

Fig. 2.17 Class AB output operational amplifier schematic

Low VTH NMOS devices were chosen for the input stage to make the amplifier more compact and allow sufficient headroom for the input stage current source. The NMOS devices have a lower threshold voltage in the process technology selected for this design. In addition, the mobility of the NMOS transistors is three to four times that of its PMOS counterpart, so the input pair can be sized quite small (Fig. 2.17).

Chapter 3

Calibration Filter

A block diagram of the calibration filter is shown in Fig. 3.1. The filter consists of two fully differential OPAMPs with R-C networks in the feedback paths. R1–R4 are fixed value poly resistors, while C1 and C2 are digitally programmable MOM capacitor arrays. The capacitors have a 2-bit coarse channel selection and a 5-bit fine-tuning resolution. In the master filter, channel selection is fixed, while the programmable capacitor is adjusted to account for process variations.

3.1

Programmable Filter Stage

The filter is configured as a Tow-Thomas biquadratic section and is designed to have a Chebyshev response with 0.1 dB ripple. This mimics one of the quadratic sections in the slave filter, which is ultimately the circuit being calibrated. Choice of resistor and capacitor values is based on the following design equations: 1 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðR2R3C1C2Þ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi R4 1 Q¼ ¼ α2 þ β 2 R1 2α f0 ¼

2π

R3 Gain ¼ R1 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi FSF ¼ α2 þ β2

ð3:1Þ ð3:2Þ ð3:3Þ ð3:4Þ

The parameter f0 is the filter cutoff frequency, Q is the filter stage quality factor, Gain is the DC gain of the filter stage, FSF is the frequency scale factor, α and β are the Chebyshev pole locations that can be calculated or found in look-up tables. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2021 M. W. Rawlins, Low Power Wireless Receivers for IoT Applications with Multi-band Calibration Algorithms, https://doi.org/10.1007/978-3-030-70729-3_3

19

20

3 Calibration Filter

Fig. 3.1 Tow-Thomas programmable biquadratic filter stage

The filter stage used as a standard in the calibration algorithm has a Q ¼ 0.9145 and f0 ¼ 5MHz. The gain of the filter stage is unity [9, 10].

3.2

Programmable Capacitor with Coarse and Fine Resolution

The programmable capacitor has two main sections: a binary-to-thermometer decoder and a capacitor array. A 5-bit binary to 32-bit thermometer decoder is used to select groups of capacitors in the array where the digitally selected capacitor value monotonically increases from some minimum to a maximum. The array is structured such that the nominal capacitor value is selected with a mid-scale binary word of 1 0 0 0 0. A condensed state table is provided in Fig. 3.2. The logic that implements this decoder along with the capacitor array is shown in Figs. 3.3 and 3.4. Capacitors are selected one at a time from left to right in each row when the row is active. The selection of any capacitor is dependent on its position in the array and the digital word b4-b0. For instance, the binary word b4-b0 ¼ [00001] selects the first capacitor in each row when the row is active. An active row is determined by the channel selection decoder (see Fig. 3.4). In the slave filter, coarse channel selection

3.2 Programmable Capacitor with Coarse and Fine Resolution

b4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

b3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Inputs b2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

b1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

b0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

C30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

C29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

C28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1

C27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

Outputs ···· C4 ···· 0 ···· 0 ···· 0 ···· 0 ···· 0 ···· 1 ···· 1 ···· 1 ···· 1 ···· 1 ···· 1 ···· 1 ···· 1 ···· 1 ···· 1 ···· 1 ···· 1 ···· 1 ···· 1 ···· 1 ···· 1 ···· 1 ···· 1 ···· 1 ···· 1 ···· 1 ···· 1 ···· 1 ···· 1 ···· 1 ···· 1 ···· 1

21

C3 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

C2 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

C1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

C0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Fig. 3.2 Binary to thermometer decoder (5–32 bit)

is accomplished with a 2-bit channel selection decoder used to select one of four possible channel frequencies. The truth table is shown in Fig. 3.5. This decoder selects filter bandwidths supporting various WLAN standards and data rates. Logic for the decoder and the coarse channel selector are illustrated in Figs. 3.6 and 3.7. In the case where cs1, cs0 ¼ [1,1], capacitors C2–C8 are switched out of the circuit, so only C1 is selected. In addition, one-half of the capacitors in row one of the programmable capacitor array shown in Fig. 3.4 are selected. When cs1, cs0 ¼ [1,0], capacitors C3–C8 are switched out of the circuit, and C1–C2 are

22

3 Calibration Filter

Fig. 3.3 Binary-to-thermometer decoder logic

selected. In this case, one-half of the capacitors in rows one and two of the programmable capacitor array are selected. When cs1, cs0 ¼ [0,1], capacitors C5– C8 are switched out of the circuit, and C1–C4 are selected. In this case, one-half of the capacitors in rows one to four of the programmable capacitor array are selected. When cs1, cs0 ¼ [0,0], all capacitors (C1–C8) are selected. In this case, one-half of the capacitors in rows one through eight of the programmable capacitor array are also selected. Figure 3.8 summarizes channel selection truth table.

3.2 Programmable Capacitor with Coarse and Fine Resolution

23

Fig. 3.4 Programmable capacitor array (fine selection) Fig. 3.5 Channel selection truth table

Fig. 3.6 Channel selection logic

Fig. 3.7 Coarse channel selector

Channel Bandwidth 10 MHz 20MHz 40MHz 80MHz

cs1 0 0 1 1

cs0 0 1 0 1

24

3 Calibration Filter

Decoder cs1 cs0 0 0 0 1 1 0 1 1

C1 on on on on

C2 on on on off

Coarse Channel Selector C3 C4 C5 C6 on on on on on on off off off off off off off off off off

C7 on off off off

C8 on off off off

Array rows 1-8 1-4 1-2 1

Fig. 3.8 Channel selection truth table

Fig. 3.9 Fully differential OPAMP for master filter

3.3

Fully Differential OPAMP with Common Mode Control

A fully differential operational amplifier illustrated in Fig. 3.9 serves to implement all stages in both the calibration and slave filters. This amplifier has a class AB output as well as common mode output control. The circuit is a folded-cascode amplifier with an NMOS input stage. Common mode control is achieved through a common mode feedback amplifier consisting of M30–M33. A common mode control reference voltage “vcm” is nominally set to VDD/2 but can be adjusted to level shift the common mode output voltage. R1 and R2 facilitate common mode measurement, while C1 and C2 help with compensation for the common mode feedback loop. Figure 3.10 shows the output common mode response, the OPAMP having a sinusoidal input stimulus, with “vcm” swept from 350 mV to 750 mV in 100 mV steps. Outputs Voutp and Voutn are displayed versus common mode control.

3.3 Fully Differential OPAMP with Common Mode Control

25

Fig. 3.10 Output common mode response

The amplifier must support very broad bandwidth given the maximum corner frequency of the filter is 80 MHz and the highest quality factor is approximately 3.3. So the unity gain bandwidth of the amplifier in the highest Q stage must be >>260 MHz for the OPAMP poles to have minimal impact on the filter transfer function. It can be challenging to design the amplifier for such large bandwidth while maintaining unity gain stability under the load conditions imposed by the filter. The OPAMP bias current is compensated to minimize variations in stability and cutoff frequency versus temperature. Phase and gain margins as a function of temperature are shown in Fig. 3.11. The limiting pole frequency of the OPAMP when loaded by capacitance CL is determined by f1 ¼

gm1 þ gm2 2π ∙ CL

ð3:5Þ

where gM1 + gM2 is the sum of the transconductances of M1 and M2. For stability with approximately 60 of phase margin, the crossover frequency f0 where the loop gain is 0 dB must be 14 f 1 given by

26

3 Calibration Filter

Fig. 3.11 Phase and gain margins versus temperature

  gm21 1 1 gm1 þ gm2 f0 ¼ f1 ¼ ¼ 4 4 2π ∙ C L 2π ∙ CM1 þ C M2 þ CM3 þ C M4

ð3:6Þ

where gm21 is the transconductance of M21 and CM1, CM2, CM3, and CM4 are Miller capacitances of equal value. Note that in the fully differential OPAMP of Fig. 3.9, gm21 drives four Miller capacitances. From these equations, each Miller compensation capacitor must meet the constraint [11] CM ¼ CL

gm21 gm1 þ gm2

ð3:7Þ

A phase margin of >60 degrees is maintained along with a gain margin >12.8 dB. Under these conditions, the simulated 3-dB bandwidth of the operational amplifier is approximately 900 MHz without capacitive loading. Figure 3.12 shows the transient response as a function of temperature (40  C to +85  C) to an 80-MHz, 200 mVp-p sine wave. The solid waveform is the input, and the dashed waveform is the output (Fig. 3.13).

3.3 Fully Differential OPAMP with Common Mode Control

27

Fig. 3.12 Transient response versus temperature

Fig. 3.13 Fully differential class AB output operational amplifier

The power dissipation of the OPAMP varies from 1.17 mW at  40  C to 1.48 mW at + 85  C.

Chapter 4

Clock Dividers

Two clock frequency dividers are used in the filter calibration system. The clock reference divider provides the input reference used in the filter calibration algorithm. A second clock divider, the divide-by-40 counter, determines the start time for the calibration measurement.

4.1

Reference Divider

The reference clock divider, shown in Fig. 4.1, is driven from an external, singleended, TCXO clock source running at 40 MHz. The circuit divides the 40-MHz reference frequency by eight while providing differential quadrature outputs at 5 MHz. In addition, a logic level 5-MHz clock output is provided to drive an additional divider circuit described in Sect. 4.2. The in-phase and quadrature (I and Q) outputs are amplitude scaled to 400 mVp-p and level shifted to a common mode voltage. Both in-phase and quadrature outputs are buffered by fully differential OPAMPS similar to the one described in Sect. 3.2. Level translation is accomplished by logic inverter buffers and resistor networks. The logic buffers “differentially drive” resistor voltage divider networks that amplitude scale the I and Q signals. The logic buffers are powered from the logic power supply “VDD.” Because the logic buffer outputs contend with one another through the resistor voltage divider network, this serves to establish a common mode level near VDD/2 (Fig. 4.2). The complementary in-phase outputs (0/180 ) drive the master filter section followed by a limiter, whereas the complementary quadrature outputs (90/270 ) drive an R-C delay element followed by a limiter (see Fig. 1.1).

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2021 M. W. Rawlins, Low Power Wireless Receivers for IoT Applications with Multi-band Calibration Algorithms, https://doi.org/10.1007/978-3-030-70729-3_4

29

30

4

Clock Dividers

Fig. 4.1 Reference clock divider

Fig. 4.2 D flip-flop schematic CLK 0>1 0>1 x

D 0 1 x

rsb 1 1 0

Q 0 1 0

Qn 1 0 1

Fig. 4.3 D flip-flop truth table

The D flip-flops are made of logic and transmission gates and can run at very high speeds while using little power. They are designed with complementary outputs and a reset function. The truth table for the device is shown in Fig. 4.3.

4.2

Divide-by-40 Counter

A counter is used to initiate the SAR-ADC described in Chap. 1. The simplified circuit illustrated in Fig. 4.4 receives a 5-MHz clock, and frequency divides the clock by a factor of 40, generating a rising edge “start flag” at the end of count. This start flag is delayed by 8 us. The delay allows the calibration error voltage to settle prior to starting the SAR-ADC. Once the start flag rises to initiate the ADC, counting terminates until the “divide-by-40” circuit is reset.

4.2 Divide-by-40 Counter

31

Fig. 4.4 Divide-by-40 counter

Fig. 4.5 Counter decode timing

The counter is held in reset until receiving a rising edge “calstart” enable signal to the rsb input, which brings the counter out of its reset state and allows the count to begin. Initially, rsb is low, and the Q outputs of all D flip-flops are reset to logic 0 that enables NOR gates 1 and 2 and places the counter in a ready state. When rsb is asserted high, all flip-flops are free to toggle and the count begins. Counter states at nodes C, Dbar, E, and F are decoded by NOR gate 3 (see Fig. 4.5). When all four states are logic 0, the NOR gate outputs a pulse at node TC which is two clock periods in duration. That signal is then delayed by one clock cycle before it toggles DFF2 causing the start signal to transition high. When the start signal transitions

32

4

Clock Dividers

Fig. 4.6 Divide-by-40 timing diagram

high, NOR gate 1 receives a logic high input which forces its output to logic 0. This disables the counter until rsb is toggled to start another counter divide cycle. The overall timing diagram is shown in Fig. 4.6.

Chapter 5

Phase-Frequency Detector with No Dead Zone

Figure 5.1 illustrates the phase-frequency detector that is used to measure the difference in delay between the master filter output and a clock standard. As described in Chap. 1 (see Fig. 1.1), a logic level output from the clock standard connects to the reference “R” input, while a logic level signal from the master filter output connects to the “N” input. When the R and N inputs are unequal in frequency and/or phase, the up (Up) and down (Dn) outputs will provide pulse streams, which, when subtracted and averaged, provide an error voltage proportional to the phasefrequency difference seen at R and N. If the reference R leads input N, the output Up transitions low on the falling edge of R having a pulse width proportional to the phase difference between R and N, while the output Dn remains low (Fig. 5.2). If the reference R lags input N, the output Up remains high, and the output Dn transitions high on the falling edge of N having a pulse width proportional to the phase difference between N and R (Fig. 5.3). Even when R and N are in phase, Up and Dn still pulse (glitch) proportionally to the builtin delay in the reset path in order to prevent the possibility of a DC (static) output. Otherwise, the integrator following the charge pump would drift toward either the positive or negative voltage rail. Note that the width of the active Up or Dn signal is proportional to the phase difference Δ∅ between the falling edge of R and the falling edge of N according to the following relationship: Δ∅ ¼

Δt ∙ 2π TR

ð5:1Þ

where Δt is the time difference between the falling edge of R and the falling edge of N and TR is the period of the reference. The phase-frequency detector (PFD) transfer characteristic is shown in Fig. 5.4. By inspection, we determine the gain constant KPFD to be

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2021 M. W. Rawlins, Low Power Wireless Receivers for IoT Applications with Multi-band Calibration Algorithms, https://doi.org/10.1007/978-3-030-70729-3_5

33

34

5 Phase-Frequency Detector with No Dead Zone

Fig. 5.1 Phase-frequency detector simplified schematic

Fig. 5.2 Pulse relationship when R leads N

5 Phase-Frequency Detector with No Dead Zone

Fig. 5.3 Pulse relationship when R lags N

Fig. 5.4 Phase-frequency detector transfer characteristic

35

36

5 Phase-Frequency Detector with No Dead Zone

K PFD ¼

900 mVolts=radian 2π

ð5:2Þ

where 900 mV is the power supply voltage. The characteristic in Fig. 5.4 is average voltage of the Up and Dn outputs versus phase difference between R and N.

Chapter 6

Charge Pump with Four Programmable States

A simplified diagram of the programmable charge pump is shown in Fig. 6.1. The circuit utilizes four independent charge pumps connected in parallel, each having equal weighting. Not shown in the diagram is the control logic for independently selecting cp1–cp4. At least one of the charge pumps is active at all times. Each charge pump is capable of delivering
40uA current to a passive or active integrator connected to Iout. Each charge pump consists of two current sources that are switched on and off at the proper instants in time by the Up and Dn outputs of the PFD described in the previous section. Logic buffers condition the Up and Dn signals from the PFD, and these signals are translated to the charge pump switches. The switches and the current sources are complementary having PMOS and NMOS transconductances matched to maintain balance. Aspect ratios are chosen to support symmetric rise and fall times. Placement of the switches relative to the current sources is not arbitrary. Three main possibilities exist. First, gates of the current mirrors can be switched. This approach complicates the circuitry and generally suffers from poor switching speeds and charge coupling through the switch to the integration capacitor. Second, the switches may be placed at the drains of the current source transistors. This architecture also suffers from charge injection issues. When the switches turn on, the current sources are initially in the triode region leading to a low impedance path between the output and the supply rails, which draws a large current and consequently produces large current spikes. These current spikes may lead to systematic DC offsets once averaged. Also, switching speed is diminished since the switches are connected directly to the integration capacitor. Third, the switches may be connected at the sources of the current source transistors and to their respective supply rails as is the case in Fig. 6.1. Switching speed is increased given one terminal of the switch is connected to a low impedance at all times and the other terminal is isolated from the integration capacitor by a current source.

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2021 M. W. Rawlins, Low Power Wireless Receivers for IoT Applications with Multi-band Calibration Algorithms, https://doi.org/10.1007/978-3-030-70729-3_6

37

38

6 Charge Pump with Four Programmable States

Fig. 6.1 Charge pump simplified schematic

Figures 6.3, 6.4 and 6.5 illustrate the operation of the charge pump shown in Fig. 6.2 when driven by the phase-frequency detector and followed by an active integrator. From Fig. 6.3, when R and N are in phase and have the same frequency, the system is in steady state with Iout ~0 A and Verror ¼ Vcm (common mode voltage of VDD/2 or 450 mV). But when R leads N, as is the case in Fig. 6.4, Iout sources current. In this case, the error voltage Verror is less than Vcm having a value proportional to the phase difference between R and N. When R lags N (see Fig. 6.5), Iout sinks current, so Verror is greater than Vcm having a value proportional to the phase difference between R and N. Figures 6.7, 6.8 and 6.9 illustrate the operation of the charge pump shown in Fig. 6.6 when driven by the phase-frequency detector and followed by a passive integrator. The signal identified as “Vout” is the voltage across the integration capacitor. When R leads N (see Fig. 6.7), the charge pump output voltage across C2 ramps upward. When R lags N, as is the case in Fig. 6.8, the charge pump output voltage ramps downward.

6 Charge Pump with Four Programmable States

39

Fig. 6.2 Phase detector, charge pump, and active integrator

Fig. 6.3 Phase detector-charge pump waveforms: R and N in phase

The rate of change of each step is determined by ΔV C2 iout ¼ Δt C2

ð6:1Þ

40

6 Charge Pump with Four Programmable States

Fig. 6.4 Phase detector-charge pump waveforms: R leads N by 30

Fig. 6.5 Phase detector-charge pump waveforms: R lags N by 30

6 Charge Pump with Four Programmable States

41

Fig. 6.6 Phase detector, charge pump, and passive integrator

Fig. 6.7 Phase detector-charge pump waveforms: R leads N by 60

where ΔVΔtC2 is the change in voltage with respect to time across the capacitor C2 and iout is the charge pump output current. From Figs. 6.6 and 6.9, we can determine the magnitude of the charge pump output current as iout ¼ C2

h

i ΔV C2 53:6mV  160uA ¼ 500pF 166:7ns Δt

ð6:2Þ

This is the magnitude of the output current when the charge pump is programmed to its maximum value.

42

6 Charge Pump with Four Programmable States

Fig. 6.8 Phase detector-charge pump waveforms: R lags N by 60

Fig. 6.9 Charge pump output voltage across C2 with R lagging N by 60

Chapter 7

Fifth-Order Chebyshev Tunable Filter

One of the most important functional blocks within any communication system is the baseband filter, which provides for adjacent channel and alternate channel rejection. This filter’s performance is critical in networking applications given the channel space is crowded with many users. The filter described in this paper is applied in wireless local area networks (WLANs) where the minimum adjacent channel and alternate channel rejection requirements are on the order of 35 dB. The adjacent channel rejection (ACR) requirement establishes the minimum filter order to meet the specification. For instance, if the designer attempts to use a Butterworth topology to meet the specification, a sixth-order filter would be required. Although a Butterworth approximation adds phase distortion, it is maximally flat in its amplitude response and is a reasonable choice for processing OFDM signals. Any required equalization can be achieved in the baseband processor. Trade-offs must be made between channel rejection, power consumption, silicon area, and distortion when considering which filter topology to select. For instance, by choosing a 0.1-dB ripple Chebyshev response, the filter order can be reduced to five poles while providing better adjacent channel rejection than the same order Butterworth approximation. Figure 7.1 illustrates some possibilities for filter selection. Of the four filter responses shown, the fifth-order Butterworth (marker 1) provides the least adjacent channel rejection of only 30 dB, thus falling short of the desired 35 dB. The fifthorder Chebyshev response with 0.1-dB ripple (marker 2) meets the requirement. The target channel rejection specification can also be achieved with a sixth-order Butterworth (marker 3) at the expense of greater silicon area and power consumption. The additional area is significant given another operational amplifier stage is required along with tunable capacitors and/or resistors. A fourth option is shown where the cutoff for the Chebyshev filter is set to 19 MHz instead of 20 MHz (marker 4). This provides for an adjacent channel rejection of 37 dB. The consequence is the attenuation at 20 MHz is approximately 1 dB. It should be noted that the Butterworth responses have 3 dB attenuation at 20 MHz. If these responses are adjusted such that they have only 1 dB attenuation at 20 MHz, even the sixth-order Butterworth would © The Author(s), under exclusive license to Springer Nature Switzerland AG 2021 M. W. Rawlins, Low Power Wireless Receivers for IoT Applications with Multi-band Calibration Algorithms, https://doi.org/10.1007/978-3-030-70729-3_7

43

44

7 Fifth-Order Chebyshev Tunable Filter

Fig. 7.1 Filter responses: Vout (dB) vs frequency

Fig. 7.2 Fifth-order Chebyshev tunable filter with 0.1-dB ripple

not meet the desired adjacent channel rejection target. In practice, the analog filter order can be somewhat relaxed given some filtering can be achieved in the digital domain to meet the overall requirement. With the various options and trade-offs discussed above, a fifth-order Chebyshev filter topology is chosen having 0.1-dB passband ripple. A simplified schematic diagram of the tunable filter is shown in Fig. 7.2. The filter uses logic and programmable capacitors to facilitate channel selection as described in detail in Chap. 3, Sect. 3.1. This channel selection circuitry allows the filter to be programmed for 10 MHz, 20 MHz, 40 MHz, and 80 MHz bandwidths.

7 Fifth-Order Chebyshev Tunable Filter

45

The first stage of the filter, which forms a single pole, is connected as a transimpedance amplifier (TIA) and interfaces to a direct conversion demodulator (see Sect. 9.4). The TIA provides for a current-to-voltage conversion and helps establish the baseband noise floor. When designing the TIA filter stage, the overall receiver front-end performance must be considered. This is because design of the TIA will influence the receiver front-end cascaded noise figure, the input referred third-order intercept point, input compression point, and gain. For these reasons, it is necessary to assemble a test bench of the receiver front end which includes the TIA. A second test bench is created to measure the overall filter response and performance. The pole location for the TIA filter stage is determined by the filter approximation chosen by the designer and the corner frequency required by the application. As mentioned earlier, the filter can be programmed to four discrete corner frequencies. The gain of the first stage is determined by the cascaded requirement of the RF V OUT DIFF receiver front end. The gain for the TIA is simply I IN DIFF ¼ R1, where VOUT _ DIFF is the TIA differential output voltage, IIN _ DIFF is the differential TIA input current, and R1 is the TIA feedback resistance. With reference to Fig. 7.2, Chebyshev design equations for the three filter stages are given below: First filter stage (TIA) 1 2π ∙ R1C1 V Gain ¼ R1 A

F o1 ¼ FSF1 ∙ f 0 ¼

α ¼ 0:4749, β ¼ 0 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi FSF1 ¼ α2 þ β2 ¼ 0:4749

ð7:1Þ ð7:2Þ

ð7:3Þ

Second filter stage 1 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2π ðR4R5C2C3Þ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi R3 1 Q¼ ¼ α2 þ β 2 R2 2α

F o2 ¼ FSF2 ∙ f 0 ¼

Gain ¼

R4 R2

α ¼ 0:3842, β ¼ 0:5884

ð7:4Þ ð7:5Þ ð7:6Þ

46

7 Fifth-Order Chebyshev Tunable Filter

Fig. 7.3 Filter stage frequency responses, f0 ¼ 80 MHz

FSF2 ¼

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi α2 þ β2 ¼ 0:7027

ð7:7Þ

Third filter stage 1 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2π ðR8R9C4C5Þ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi R7 1 Q¼ ¼ α2 þ β 2 R6 2α

F o3 ¼ FSF3 ∙ f 0 ¼

Gain ¼

R8 R6

α ¼ 0:1468, β ¼ 0:9521 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi FSF3 ¼ α2 þ β2 ¼ 0:9634

ð7:8Þ ð7:9Þ ð7:10Þ

ð7:11Þ

f0 is the filter cutoff frequency to which the filter is nominally tuned. FSF is the frequency scale factor. Note that FSF is the square root of the sum of the squares of the real and imaginary parts of the pole location for a given stage. For a Chebyshev response, the filter is stagger tuned, so the FSF is necessarily different for each stage (see Fig. 7.3). Fo is the cutoff frequency after f0 is scaled by FSF. α is the real part of the Chebyshev filter pole. β is the imaginary part of the Chebyshev filter pole.

7 Fifth-Order Chebyshev Tunable Filter

47

Q is the quality factor of the given quadratic filter stage response. For stage 2, the quality factor is 0.9145, which results in the second filter stage frequency response peaking 0.7662 dB at a frequency 0.4457 f0. For stage 3, the quality factor is 3.2812, which results in the third filter stage frequency response peaking 10.4226 dB at 0.9407 f0. Gain is the dc gain of the filter stage [9, 10]. Figure 7.3 illustrates the individual filter stage frequency responses as well as the overall filter response. In the example, the filter was scaled to an f0 of 80 MHz. Marker 1 shows the 3-dB cutoff of the TIA stage, which lies at 37.9 MHz given the frequency scale factor for the stage is 0.4749 f0. Marker 2 tags the peaking frequency and amplitude for stage 2 resulting from the quality factor of 0.9145 for the stage. Likewise, marker 3 details the peaking frequency and amplitude for stage 3 resulting from the quality factor of 3.2812 for the stage. Finally, marker 4 features the 3-dB frequency of the overall filter response at 80 MHz bandwidth. As alluded to earlier, this corner frequency will be shifted to provide a 1-dB roll-off at 80 MHz while still meeting the desired attenuation of 35 dB at 2 f0.

Chapter 8

Filter Calibration Results

Figure 8.1 illustrates the filter calibration test bench based on the algorithm discussed in Chap. 1. The following plots demonstrate the filter calibration performance over process corners and temperature. Examples of relevant operational signals and controls which contemplate process variation from 5% up to 30% are provided (Figs. 8.2, 8.3, 8.4, 8.5, 8.6, 8.7, 8.8, 8.9, 8.10, 8.11, 8.12, 8.13, 8.14, 8.15, 8.16, 8.17, 8.18 and 8.19).

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2021 M. W. Rawlins, Low Power Wireless Receivers for IoT Applications with Multi-band Calibration Algorithms, https://doi.org/10.1007/978-3-030-70729-3_8

49

50

Fig. 8.1 Filter calibration test bench

Fig. 8.2 SAR error measurement, +5% process variation

8 Filter Calibration Results

8 Filter Calibration Results

Fig. 8.3 Filter calibration, +5% process variation

Fig. 8.4 SAR-ADC output, +5% process variation

51

52

8 Filter Calibration Results

Fig. 8.5 SAR error measurement,

Fig. 8.6 Filter calibration,

5% process variation

5% process variation

8 Filter Calibration Results

Fig. 8.7 SAR-ADC output,

53

5% process variation

Fig. 8.8 SAR error measurement, +20% process variation

54

Fig. 8.9 Filter calibration, +20% process variation

Fig. 8.10 SAR-ADC output, +20% process variation

8 Filter Calibration Results

8 Filter Calibration Results

55

Fig. 8.11 SAR error measurement,

Fig. 8.12 Filter calibration,

20% process variation

20% process variation

56

Fig. 8.13 SAR-ADC output,

8 Filter Calibration Results

20% process variation

Fig. 8.14 SAR error measurement, +30% process variation

8 Filter Calibration Results

Fig. 8.15 Filter calibration, +30% process variation

Fig. 8.16 SAR-ADC output, +30% process variation

57

58

8 Filter Calibration Results

Fig. 8.17 SAR error measurement,

Fig. 8.18 Filter calibration,

30% process variation

30% process variation

8 Filter Calibration Results

Fig. 8.19 SAR-ADC output,

59

30% process variation

Chapter 9

WLAN Receiver Front End

A simplified diagram of the WLAN receiver front end is provided in Fig. 9.1. The direct conversion receiver shown consists of an integrated RX-TX switch, a variable gain LNA, a programmable voltage-to-current converter, an I-Q sampling downconverter, and programmable low-pass filters. Each of these blocks will be explained in detail in the following chapters with the exception of the programmable filters which have already been described. The receiver shown in Fig. 9.1 is generic enough to serve many direct conversion applications. This design targets 802.11 b/g/n in the 2.412–2.484-GHz frequency band. With modification of tuning and matching elements, the circuits will function for the high band as well which spans 4.9–5.825 GHz. The receiver design is implemented using a TSMC 28-nm HPC CMOS process design kit. It is an eight-metal layer process with 900-mV and 1.8-V complementary MOSFETs, low threshold voltage (low Vth) options, finger MOM capacitors, and POLY resistors. Rx chain performance at max gain is as follows: NF
3 dB, 42 dB dynamic range in 6 dB steps, IP3  11 dBm, power gain ~32 dB with TIA OPAMP RL ¼ 1KΩ, input RF impedance nominal 50Ω with nominal return loss at 2.45 GHz >10 dB.

9.1

RX-TX Switch

A single-pole double-throw RX-TX switch is fully integrated into the RF front end to facilitate switching the receiver and transmitter paths to a single pin. Important figures of merit for the switch are insertion loss, isolation, linearity, and power handling capability. Due to the low breakdown voltages and parasitic diodes that exist between source-drain and the body, care must be taken to isolate the n-well and p-well diodes along with stacking an appropriate number of switches to maintain linearity and improve power handling [12, 13]. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2021 M. W. Rawlins, Low Power Wireless Receivers for IoT Applications with Multi-band Calibration Algorithms, https://doi.org/10.1007/978-3-030-70729-3_9

61

62

9 WLAN Receiver Front End

Fig. 9.1 WLAN receiver front-end block diagram

S

cntrl

vss s

vdd

R1

nmos_rf_18_5t

d

R3 RØ

R2

net9

Øn vss vss net6 net10 wr=3 8u “nmos_rf_18_6t” M1

d

Fig. 9.2 Switch cell

To achieve this goal, the bulk and n-well nodes of a triple-well NMOS device are isolated with resistors to avoid forward biasing of the parasitic diodes under large signal conditions (see Fig. 9.2). In addition, resistors are used in series with the gate terminals to isolate devices from the logic drive circuits and facilitate better linearity and lower loss due to RF signal coupling through the overlap capacitances. The switch input and output terminals are kept at the same DC potential by means of a resistor connected between source and drain. Using the aforementioned techniques allows the voltage to be divided “evenly” across the stack of devices. The p-well and deep n-well are left floating, reducing the parasitic loss by increasing the effective impedance in the body of the device. The p-well is biased at 0 Vdc, and the deep n-well is biased at 1.8 Vdc. 1.8-V tolerant devices are used to improve the power handling capability and linearity at the expense of size. The channel length of the NMOS devices is 150 nm. Six-terminal devices with RF models are used for improved prediction of actual performance.

9.1 RX-TX Switch

63

Fig. 9.3 TX switch

For the TX switch, a series-shunt topology is adopted as shown in Fig. 9.3. The Tx switch must handle peak powers >+27 dBm while providing minimal insertion loss. As designed, TX insertion loss is nominally 0.6 dB to 0.7 dB depending on matching. For this design, a series inductance of ~2nH or a shunt inductance of ~5nH is required at the TX port, which can be part of the PA matching and bias feed if a transformer or inductive pull-up is used. The compression point is near +30 dBm, although the switch may not be capable of surviving 1-watt continuous output power level. MOM coupling capacitors are used to block DC. The return loss is approximately 15 dB with proper impedance matching. The RX switch is partially incorporated into the LNA as shown in Fig. 9.4. The switch stack includes four series switches with one additional switch inside the LNA in series with the degeneration inductor. The series switches provide protection against breakdown of receive path devices during transmit mode. The internal LNA switch opens and prevents the LNA from turning on during transmit mode due to leakage through the main RX switch. An inductor, in series with the RX switch, improves input return loss. Insertion loss of the main receive path switch is

JC > >

 ð r þ r Þ 1 þ þ < b e u 2V T βdc f 2 4βdc f 2 6 7= f T n2 V T 7    þ ðr b þ r e Þu 6 4 JC f 2T f 2T 5> f 2I c > n2 > > ; : 2V T ðr b þ r e Þu 1 þ βdc f 2 þ 4 1 þ βdc f 2 ðC:32Þ

(rb + re)u are the base and emitter resistances of a unit device. (Cje + Cjc)u are the base-emitter and base-collector junction capacitances of a unit device. A unit device is defined as the minimum size transistor in a given bipolar technology. N is a factor which scales the emitter length of a unit device. M is the number of devices placed in parallel (multiplicity). M and N are adjusted to make the real part of Rsopt ¼ 50Ω. The final device size is M∙N∙unit device area. The bias current required is Jcopt∙M∙N.

Impedance Matching The input impedance looking into the input of the inductively degenerated common emitter amplifier shown in Fig. C.2 is given by Fig. C.2 LNA with inductive degeneration

94

Appendices

 1 Z in ¼ Rin þ jX in ¼ r b þ ωT Le þ j ωðLb þ Le Þ  ωC π

ðC:33Þ

where Cπ was defined in Eq. C.14. The choices of Le and Lb are not arbitrary. To achieve a 50 Ω match, Le ¼

50Ω 50Ω ¼ ωT 2π f T

ðC:34Þ

Lb is chosen to cancel the reactance due to the input capacitance of Q1and is given by Lb ¼

1  Le ω2 C π

ðC:35Þ

Lc is chosen to resonate with the capacitance seen at the collector of Q2. This capacitance is the sum of parasitic collector-base and collector-substrate capacitances as well as any load capacitance seen at the collector node of Q2. Lc ¼

ω2




1  Cμ þ C cs þ CL

ðC:36Þ

Linearity and Distortion Analysis A designer must make trade-offs between achieving high linearity and optimizing noise figure and impedance match. Sometimes, meeting a system’s third-order intercept point (IIP3) requirement demands biasing an LNA with a little more DC current than desired or degenerating the LNA transistor a bit more than wanted, resulting in a slight degradation in input return loss and/or noise figure. This can be understood by examining the distortion produced in a common-emitter stage, the most widely used topology in bipolar transistor LNAs. In a bipolar transistor, the collector current is a function of the base-emitter voltage and is given by [19]

I C ¼ I s ∙ exp

V BE þ vbe VT

The quiescent term is given by

 ¼ I s ∙ exp



 V BE v exp be VT VT

ðC:37Þ

Appendices

95

Fig. C.3 Common emitter amplifier

I Q ¼ I s ∙ exp

 V BE VT

ðC:38Þ

With reference to Fig. C.3, we can see io ¼ I Q  I C

ðC:39Þ





V BE vbe exp  IQ io ¼  I s ∙ exp VT VT

ðC:40Þ

Applying Eq. C.39 to C.37,

Substituting Eq. C.38 into C.40 yields

io ¼ I Q



v exp be VT



 1

ðC:41Þ

A power series expansion of the exponential leads to exp ðxÞ ¼

X1 xk x2 x3 ¼ 1 þ x þ þ þ ... k¼0 k! 2 6

ðC:42Þ

If we apply this power series expansion to Eq. C.41, we obtain " io ¼ I Q

#

2

3 vbe 1 vbe 1 vbe þ þ þ ... 6 VT VT 2 VT

ðC:43Þ

We note from Fig. C.3 that vbe ¼ V s Therefore, we can write the amplifier transfer function as

ðC:44Þ

96

Appendices

i o ¼ a1 V s þ a2 V s 2 þ a 3 V s 3 þ . . .

ðC:45Þ

where we identify the coefficients of Eq. C.45 as IQ ¼ gm VT

2 1 1 a2 ¼  IQ 2 VT

3 1 1 a3 ¼  IQ 6 VT a1 ¼ 

ðC:46Þ ðC:47Þ ðC:48Þ

For values of Vs  VT, the circuit is essentially linear and the first term dominates. However, as the amplitude of Vs increases, the Vs2 and Vs3 terms become significant and distortion products are generated. Although the focus here is on second- and third-order distortion, the reader should understand higher-order distortion terms exist. At audio frequencies, these nonlinearities are generally described in terms of harmonic distortion. At radio frequency, it is customary to specify intermodulation distortion. Harmonic distortion (HD) and intermodulation distortion (IM) are directly related as will be shown. If we apply a sinusoidal input to the amplifier of Fig. C.3, we have [19] V s ¼ V sp sin ωt

ðC:49Þ

Substituting Eq. C.46 into Eq. C.42 yields V s ¼ a1 V sp sin ωt þ a2 V sp 2 sin 2 ωt þ a3 V sp 3 sin 3 ωt þ . . .

ðC:50Þ

1 1 ¼ a1 V sp sin ωt þ a2 V sp 2 ð1  cos 2ωÞ þ a3 V sp 3 ð3 sin ωt  sin 3ωt Þ þ . . . 2 4 Equation C.47 shows frequency components exist at ω, 2ω, 3ω. . . . Notice that the distortion terms at 2ω, 3ω. . . are not present in the original input signal. Harmonic distortion is mathematically described as the ratio of the amplitude of the output signal at frequency n∙ω, where n is an integer (2, 3, 4, 5...), to the amplitude of the first harmonic at the fundamental frequency ω. For instance, HD2 can be expressed as follows using Eqs. C.45, C.46, C.47 and C.48. HD2 ¼



 1 a2 1 V sp V sp ¼ 2 a1 4 VT

HD3 can be expressed as follows:

ðC:51Þ

Appendices

97

HD3 ¼



2 1 a3 1 V sp V sp 2 ¼ 4 a1 24 V T

ðC:52Þ

Equation C.51 shows only 10 mV applied to the input of a common emitter amplifier as shown in Fig. C.3 would result in a 10% second harmonic distortion. This result underscores the need for improving the signal handling capability of the common emitter stage. Not considered in the derivation are the effects of the output resistance of Q1 and load resistance (not shown). The relationship between IM2 and HD2 has been shown to be [20]

 a2 1 V sp IM 2 ¼ 2HD2 ¼ V sp ¼ 2 VT a1

ðC:53Þ

Also IM 3 ¼ 3HD3 ¼



2 3 a3 1 V sp V sp 2 ¼ 4 a1 8 VT

ðC:54Þ

Effects of Feedback on Distortion One way to reduce the distortion in a common emitter amplifier is through insertion of an impedance ZE between the emitter and ground as shown in Fig. C.4. This impedance could be a resistor, typical for lower frequency applications, or an inductor which is more suited for use in amplifiers operating at RF frequencies. The benefit of ZE can be seen by considering the following; in the circuit of Fig. C.3, Vs ¼ vbe, indicating the entire magnitude of the input signal appears across the base-emitter junction of Q1. In the circuit of Fig. C.4, the input signal is imposed across the base-emitter junction of Q1 and ZE.Therefore, for a given bias condition, Fig. C.4 Common emitter amplifier with emitter degeneration

98

Appendices

Fig. C.5 Amplifier with feedback

the portion of the input AC voltage seen by the base-emitter junction of Q1 is diminished as the magnitude of the impedance ZE increases. In effect, ZE provides local feedback for the amplifier of Fig. C.4. Consider the amplifier with feedback shown in Fig. C.5. The factor a represents the linear gain (gm) of the amplifier, and f represents the transfer function of the feedback network. If we let A represent the closed loop gain of the amplifier and T represent the loop gain, we determine io a ¼A¼ Vs 1 þ af

ðC:55Þ

T ¼ af

ðC:56Þ

io a ¼A¼ 1þT Vs

ðC:57Þ

This allows us to write

What should be noted from Eq. C.57, is that negative feedback reduces the gain of the amplifier by the factor 1 + T. It is necessary to derive a new set of coefficients bi to account for the effect of adding feedback (emitter degeneration) to the amplifier of Fig. C.4. i o ¼ b1 V s þ b2 V s 2 þ b 3 V s 3 þ . . .

ðC:58Þ

We can use the following analytic function operating on Eq. C.58 to find the coefficients bi [20]:  1 dn io  bn ¼ n! dV s n V s ¼0 b1 ¼

a1 1þT

ðC:59Þ ðC:60Þ

Appendices

99

b2 ¼ b3 ¼

a2 ð1 þ T Þ3

a3 ð1 þ T Þ  2f a22 ð1 þ T Þ5

ðC:61Þ ðC:62Þ

From inspection of Figs. C.4 and C.5 along with Eqs. C.46 and C.55, C.56 and C.57, we find the following: f ¼ ZE

ðC:63Þ

T ¼ gm Z E

ðC:64Þ

We can make substitutions into Eqs. C.60, C.61, C.62 using C.46, C.47, C.48 and C.63, C.64, C.65: a1 1þT a2 b2 ¼ ð1 þ T Þ3 b1 ¼

b3 ¼

a3 ð1 þ T Þ  2f a22 ð1 þ T Þ5

ðC:65Þ ðC:66Þ ðC:67Þ

We can now determine the intermodulation terms from #

" b2 1 V sp 1 IM 2 ¼ 2HD2 ¼ V sp ¼ 2 VT b1 ð1 þ T Þ2 !

 2 V sp 3 b3 1 1  2T 2 IM 3 ¼ 3HD3 ¼ V ¼ 4 b1 sp 8 ð1 þ T Þ2 V T ð1 þ T Þ

ðC:68Þ ðC:69Þ

Appendix D: Folded Cascode OPAMP Design Searching the database of major semiconductor component vendors like Analog Devices, Maxim, or Texas Instruments, it is easy to become overwhelmed by the number and types of operational amplifiers available. Some are designed to accommodate high or low supply voltages, some support high speeds and consume a lot of quiescent power, and others are designed to be low speed and low power with high precision. The varieties of amplifiers exist for good reason given the devices target many differing systems and applications having their own design constraints.

100

Appendices

What follows in this section is a design procedure for a medium-speed, low-power, and low-noise class AB folded-cascode operational amplifier. The amplifier is suitable for use as the first gain block in a communication system baseband signal chain, use in analog filters where gain is required, or use in general purpose amplification.

Foundry Process and Constants The following constants are used in the analysis, calculations, and design procedure which follow. The process specific parameters are taken from a Texas Instruments 350-nm process known as RFSiGe1 with the foundry located in Freising, Germany. Although this process is a bit dated, the design procedures detailed can target any modern process design kit (PDK). Porting this design into IBM’s BiCMOS7WL is straightforward given the similarity between the two processes (Table D.1). • ε0x ¼ 3.9 ∙ ε0 ¼ 3.45x1017F/um ¼ 3.45x1013F/cm • C0x ¼ ε0x/t0x

Slew Rate Most often, the design requirements for an amplifier are dictated by the application. Slew rate, power supply rail, load drive capability, input offset voltage, and Table D.1 Process and physical constants

Appendices

101

quiescent power consumption are some of the key parameters that drive the choice of architecture and transistor aspect ratios. This operational amplifier is designed to meet the following basic requirements: • • • • • • • • •

Power supply: single supply, maximum +3.3 V and minimum +2.5 V Power dissipation: &