Digital Logic Design - Devices and circuits - by Gamal El-Sheikh (9ed) [1, 9 ed.]

Table of contents :
Cairo 2023
Praise and Thanks be to ALLAH
To my wife and our daughters and sons
G.A. El-Sheikh
The Evolution of Electronic Digital Devices can be described by the following stages;
The hierarchy that clarifies the Basic Digital System Concepts including Embedded Systems Technologies is shown in (Fig. 1.1), where;
The process of Digital System Design is shown in (Fig. 1.2);
1.2 Digital Systems
Logic Conventions
Basic Characteristics
Levels of Integrated Circuits
Types of VLSI Chips
Digital Systems
Digital System Design Levels
Building binary digital solutions to computational problems;
Embedded Digital System
A Wireless Microsensor System;
Temporal Representations of Electronic Signals;
Fig. 1.14: Real Analog Signal - Bat Sonar
Digital Computer (Fig. 1.16);
Digital Computer Basic Operation;
2.1.2 Computers and Numbers
Example-2.6.6
Solution
Example-2.6.7
Solution (1)
9’s and 10’s Complement
Forming the 9’s complement
Signed Magnitude
Operations with Negative Numbers
Example-2.7.20
Example-2.7.21
Octal Subtraction
Example-2.7.22
Example-2.7.23
Example-2.7.24
Example-2.7.25
Example-2.7.26
Floating Point Representation of Real Numbers
Advantages of Binary Codes
Classifications of Binary Codes
Weighted Codes
Binary Coded Decimal (BCD) code
Advantages of BCD Codes
Disadvantages of BCD Codes
Basics
BCD in Electronics
Packed BCD
BCD Subtraction
Comparison with pure binary
Advantages
Disadvantages
Application of Gray Code
Binary to Gray Code Conversion
Gray Code to Binary Conversion
Addition of two numbers in Excess-3 Code
Decoding
Example-2.9.6
Zoned Decimal
EBCDIC zoned decimal conversion table
Background
Error Codes
Error-Detecting codes
Error-Correcting codes
Detect and Correct Errors
Parity Checking of Error Detection
Use of Parity Bit
Error Detection
Fiber Optic Transceiver
2.10.1 Binary Numbers in Electronics
2.10.2 Binary Bits of Zeros and Ones
2.10.3 Analogue Voltage Output
2.10.4 Digital Voltage Output
2.10.5 Digital Logic Levels
Digital Value Representation
TTL Input & Output Voltage Levels
Fig. 2.10.4: Digital Voltage Output Representation
Fig. 2.10.3: Analogue Voltage Output Representation
3- Logic Gates
3.1 Binary Logic
3.2 Logic Operations
3.2.1 Inversion (NOT) Operation
3.2.2 OR Operation
3.2.3 AND Operation
3.2.4 Combined OR-AND Operations
3.2.5 Truth Table
3.2.6 Symbols
3.2.7 Types of Logic Gates
The NAND and NOR gates are called universal functions since with either one the AND and OR functions and NOT (basic logic functions) can be generated. A function in sum of products (SOP) form can be implemented using NAND gates by replacing all AND an...
3.4.1 NAND gate (NAND = Not AND)
3.4.2 NOR gate (NOR = Not OR)
3.6 Combinations of Logic Gates
3.6.2 NAND gate Equivalents
The basic logic gates (NOT, AND, OR and NOR) can be realized using NAND gates as shown in the following table:
B
B (1)
F
B (2)
F (1)
B (3)
3.7 Electronics Implementation within Digital Logic Gates
3.7.1 Classification of Integrated Circuits
3.7.2 TTL and CMOS Logic Levels
Logic Levels
Ideal TTL Digital Logic Gate Voltage Levels;
3.7.3 DRL and DTL Logic Gates
3.7.4 TTL Logic Gates
TTL NOR and OR gates;
In order to turn this NOR-gate circuit into an OR-gate, we would have to invert the output logic level with another transistor stage, just like we did with the NAND-to-AND gate example. Of course, totem-pole output stages are also possible in both NOR...
3.7.5 Emitter-Coupled Digital Logic Gates
3.7.6 CMOS Gate Circuitry
3.7.7 Inverter Logic Gate
3.7.8 Static Logic Design of NAND, NOR, XOR and XNOR Gates
A static CMOS gate is a combination of two networks, called the pull-up network (PUN) and the pull-down network (PDN). The function of the PUN is to provide a connection between the output and VDD anytime the output of the logic gate is meant to be 1 ...
Fig. 3.7.12: The circuit diagram for 2-input NAND, NOR, XOR and XNOR gates in CMOS static logic
3.8 Digital Logic Gates Implementation within VHDL
B (4)
4.6.1 K-mapping and Minimization Steps
Solution
Solution (1)
Solution (2)
A
B
C
D
A (1)
B (1)
C (1)
D (1)
A (2)
B (2)
C (2)
D (2)
A (3)
B (3)
B (4)
C (3)
5- Data Processing and Arithmetic Circuits
The design of logic circuits can be started with verbal description into truth tables from which the pertinent logic expressions are obtained. These logic expressions can be realized using any of the logic gates after minimization as shown in Fig. 5.0.
5.1 Comparison
5.2 Addition
5.2.3 Full Adder (FA)
Full adder using NAND or NOR logic
Full adder is a logic circuit that adds two input operand bits plus a Carry in bit and outputs a Carry out bit and a sum bit. The Sum out (Sout) of a full adder is the XOR of input operand bits A, B and the Carry in (Cin) bit. Truth table and schema...
5.2.5 Ripple Carry Adder
5.2.6 Carry Look Ahead Adder
5.3 Negative Numbers and Binary Subtraction
B
6- Combinational Circuits
6.1 Decoders
7-Segment Display Experiment
Pin connections
6.2 Encoders
Magnetic Encoder
Mechanical Encoder
Optical Encoder
War- Field -Flying Robot with a Night Vision Flying Camera
Robotic Vehicle with Metal Detector
RF based Home Automation System
Automatic Wireless Health Monitoring System
Secret Code Enabled Secure Communication
6.3 Multiplexers
6.3.1 Two-Input Multiplexer
6.3.2 Four-Input Multiplexer
6.3.3 Combined Multiplexers
References
Appendices:
Appendix-A:
Digital Principles of System Design Understanding
Appendix-B: Circuits' and Devices' Symbols
Appendix-C:
Electronic Devices and Circuits: Significant Equations
Appendix-D:
Laboratory Experiments and Assignments
Lab-04: Inverters
E.1 Integrated Circuits Functioning
Notes
E.2 Integrated Circuits Pin Configuration
F.1 Integrated Circuits Functioning
The following is a list of CMOS 4000 series digital logic integrated circuits that represent Logic Gates. The 4000-series CMOS logic circuits include several integrated circuits (ICs) that provide several electronic logic gates in a single package. Ea...
F.2 Integrated Circuits Pin Configuration

Citation preview

Digital Logic Design-I: Devices and Circuits (9th Edition)

by

Gamal El-Sheikh

Cairo 2023

G.A. El-Sheikh

Digital Logic Design I: Devices and Circuits

i

Praise and Thanks be to ALLAH

To, in the name of ALLAH, my Father and Mother

To my wife and our daughters and sons

G.A. El-Sheikh Cairo 2023

Copyright, 2023 The copyright of this book belongs to the author under the terms of the international copyrights acts. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without written permission of the Author.

ISBN:

‫لحلول الطباعة المتكاملة‬ ‫ الجيزة‬- ‫ بجوار رئاسة حي الدقي‬- ‫ بين السرايات‬- ‫ش السكري‬7 01124888835 - 01063177771

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Preface The huge technological developments and ever-increasing human requirements motivated many of the manufacturers to develop real world applications using digital systems and naoelectronics. The digital systems are based on logical circuits and logical devices in addition to pertinent application software. Thus, this book is devoted to provide both understanding of the basic principles of digital logic design, and how these fundamental principles can be applied in the building of digital and complex microprocessor circuits using current technologies. Although the basic principles of digital logic design have not changed, the design process and the implementation of the circuits are ever-changing. With the advances in fully integrated modern computer aided design (CAD) tools for logic synthesis, simulation, and implementation of circuits in programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs), it is now possible to design and implement complex digital circuits very easily and quickly. A traditional approach of introducing the basic principles and theories of logic design includes the building of separate combinational and sequential components. These individual components and the way of its utilization to build microprocessors are ultimate goals in digital circuits. One primary goal of this book is to go beyond the logic principles, and the building of individual components. In addition, these principles are utilized with the individual components and combined together to create data paths and control units, and finally the building of real dedicated custom microprocessors and general-purpose microprocessors. With any of the available CAD tools and the FPGA hardware development kits, students or trainee can actually implement these circuits and justify its execution operation both in software simulation and in hardware. The book contains many interesting examples with complete circuit schematic diagrams that can be coded in any of the available simulation software and implementation in hardware. With the hands-on exercises, the students or trainee can learn not only the principles of digital logic design, but also in practice, how circuits are implemented using current technologies. The book is divided into two parts; the first part is devoted to basic principles and combinational networks while the second is devoted to sequential circuits and pertinent applications. The learning objectives of the first part of the book include the following:  Recognize the different numbers' systems and codes in addition to mathematical operations that can be carried with each.  Describe the elements and characteristics that make up logic families; RTL, DTL, TTL, CMOS.  Recognize the types of basic logic gates, universal logic gates and special logic gates in addition to different logic circuits used in digital equipment.  Identify combined logic gates to build circuits and interpret their respective operation via logic functions and Truth Tables.  Design and realize addition and subtraction circuits, comparators, and special purpose circuits.  Design and realize combinational circuits including encoders, decoders, multiplexers, demultiplexers in addition to real case studies.  Design and realize combinational circuits to achieve any of the real world operations; starting from the verbal description, truth table, logic expressions and logic circuit.  Conduct experiments with any of the logic circuits (basic or designed) within the laboratory and validate its performance with the help of laboratory instruments.

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In this edition, many of the Figures had modified to be better in addition to some illustrating examples and extra real applications for different combinational networks. In addition, appendices are added to cover the digital principles of system design towards good understanding and laboratory experiments.

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Table of Contents Preface 1- Introduction 1.1 History of Computational Fabrics Evolution of Electronic Digital Devices Basic Digital System Concepts Digital System Design Hierarchical System Design 1.2 Digital Systems Levels of Integrated Circuits Types of VLSI Chips Digital Systems Digital System Design Levels Advantages of Digital Systems Analog vs. Digital Systems Building binary digital solutions to computational problems Hardware Description Language (HDL) Embedded Digital System A Wireless Microsensor System Temporal Representations of Electronic Signals: Stored Program Digital Computer Digital Computer Basic Operation 2- Numbers Systems and Codes 2.1 Introductory Background 2.1.1 Motivation 2.1.2 Computers and Numbers 2.1.3 Binary Number System Applications 2.2 Decimal (Base 10) Numbers 2.3 Binary (Base 2) Numbers 2.4 Octal (Base 8) Numbers 2.5 Hexadecimal (Base 16) Numbers 2.6 Numbers Conversions 2.6.1 Decimal Conversions 2.6.2 Binary Conversions Binary into Decimal Binary into Octal Binary into Hexadecimal 2.6.3 Octal Conversions Decimal and Octal Conversion 2.6.4 Hexadecimal Conversion Decimal and Hexadecimal Conversion 2.6.5 Generalized Conversions 2.7 Numbers' Arithmetic 2.7.1 Binary Addition 2.7.2 Binary Subtraction 2.7.3 Signed Binary Numbers Complementary Arithmetic 9’s and 10’s Complement

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Signed Magnitude 1’s Complement 2’s Complement Arithmetic Operations with Signed Numbers Operations with Negative Numbers Two’s Complement Motivation 2.7.4 Octal Arithmetic Octal Addition Octal Subtraction 2.7.5 Hexadecimal Arithmetic Hexadecimal Addition Hexadecimal Subtraction 2.8 Binary Multiplication and Division 2.9 Codes 2.9.1 Numerical (Binary) Codes Classifications of Binary Codes 2.9.2 Binary-Coded Decimal (BCD) BCD in Electronics Packed BCD BCD Conversion BCD Addition BCD Subtraction Comparison with pure binary Disadvantages 2.9.3 Gray Code Binary to gray code conversion Gray code to binary conversion 2.9.4 Excess-3 Code Addition of two numbers in Excess-3 Code 2.9.5 Bi-quinary coded decimal Code; Decoding 2.9.6 Character (Alphanumeric) Codes 2.9.6.1 EBCDIC Code 2.9.6.2 ASCII Code Parity Method Cyclic Redundancy Check Background 2.9.7 Error Detection and Correction 2.10 Binary Number System Applications 2.10.1 Binary Numbers in Electronics 2.10.2 Binary Bits of Zeros and Ones 2.10.3 Analogue Voltage Output 2.10.4 Digital Voltage Output 2.10.5 Digital Logic Levels 2.11 Exercises: Numbers' Systems and Codes 3- Logic Gates 3.1 Binary Logic 3.2 Logic Operations 3.2.1 Inversion (NOT) operation 3.2.2 OR Operation

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3.2.3 AND Operation 3.2.4 Combined OR-AND operations 3.2.5 Truth Table 3.2.6 Symbols 3.2.7 Types of Logic Gates 3.3 Basic Logic Gates 3.3.1 The NOT (Inverter) Gate 3.3.2 The OR Gate 3.3.3 The AND Gate 3.3.4 Tristate Logic Gate (Tristate Buffer) 3.4 Universal Logic Gates 3.4.1 NAND gate (NAND = Not AND) 3.4.2 NOR gate (NOR = Not OR) 3.5 Special Logic Gates 3.5.1 EXOR (EXclusive-OR) Gate 3.5.2 EXNOR (EXclusive-NOR) Gate 3.6 Combinations of Logic Gates 3.6.1 Truth Tables and Logic Circuits 3.6.2 NAND gate Equivalents 3.6.3 NOR gate Equivalents 3.7 Electronics Implementation within Digital Logic Gates 3.7.1 Classification of Integrated Circuits 3.7.2 TTL and CMOS Logic Levels 3.7.3 DRL and DTL Logic Gates 3.7.4 TTL Logic Gates 3.7.5 Emitter-Coupled Digital Logic Gates 3.7.6 CMOS Gate Circuitry 3.7.7 Inverter Logic Gate 3.7.8 Static Logic Design of NAND, NOR, XOR and XNOR Gates 3.8 Digital Logic Gates Implementation within VHDL 3.8.1 NOT Gate Code 3.8.2 AND Gate Code 3.8.3 OR Gate Code 3.9 Exercises: Logic Gates and Logic Circuits 4- Boolean Algebra and Karnaugh Maps 4.1 Introduction 4.2 Boolean Algebra Rules Two-Valued Boolean Algebra 4.3 Basic Theorems and Properties of Boolean Algebra Duality Basic Theorems Operator Precedence Boolean Functions Logic Gate Implementation (Basic) Complement of a Function 4.4 Canonical and Standard Forms Minterms and Maxterms Minterms (SOP) Maxterms (POS) 4.5 Simplification of Boolean Functions

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4.5.1 Product of Sums (POS) Simplification 4.5.2 NAND and NOR Implementation 4.5.3 Don’t Care Conditions 4.6 Karnaugh Map (K-map) 4.6.1 K-mapping and Minimization Steps 4.6.2 Two variables map 4.6.3 Three variables map 4.6.4 Four variables map 4.6.5 Five variables map 4.6.6 Six variables map 4.7 Case studies 4.8 Exercises: Boolean Algebra and Logic Gates

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5- Data Processing and Arithmetic Circuits 5.1 Comparison 5.2 Addition 5.2.1 Quarter Adder 5.2.2 Half Adder (HA) 5.2.3 Full Adder (FA) 5.2.4 Parallel Adders 5.2.5 Ripple Carry Adder 5.2.6 Carry Look Ahead Adder 5.3 Negative Numbers and Binary Subtraction 5.4 Subtraction 5.5 Exercises: Decoders, Encoders, and Adders/Subtractors

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6- Combinational Networks 6.1 Decoders 6.1.1 Three-to-Eight-Line Decoder 6.1.2 Two-to-Four-Line Decoder with Enable and NANDs 6.1.3 Expanded Realization 6.1.4 BCD to Seven-Segment Decoder 6.1.5 Combinational Logic Implementation 6.2 Encoders 6.2.1 4-to-2 Bit Binary Encoder 6.2.2 Active High 8-to-3 Line Encoder 6.2.3 Active Low 8-to-3 Line Encoder 6.2.4 Priority Encoder 6.2.5 Eight-to-Three Bit Priority Encoder 6.2.6 Encoder Applications: Positional Encoders

160 160

6.3 Multiplexers 6.3.1 Two-Input Multiplexer 6.3.2 Four-Input Multiplexer 6.3.3 Combined Multiplexers 6.3.4 Multiplexer Expansion 6.4 Demultiplexers 6.4.1 The 1-to-2 Line Decoder/Demultiplexer 6.5 Boolean Functions Realization/ Implementation 6.5.1 Three-Variables Function

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6.5.2 Four-Variables Function 6.5.3 Multiplexers using Three-State Gates 6.6 Exercices: Decoders, Encoders and Multiplexers References Appendices Appendix-A: Digital Principles of System Design Understanding Appendix-B: Circuits' and Devices' Symbols Appendix-C: Electronic Devices and Circuits: Significant Equations Appendix-D: Laboratory Experiments and Assignments Preface Abstract: Logic Laboratories Measuring Instruments Lab-01: Basic Electronic Instruments and Measurements Lab-02: Oscilloscope and Function Generator Lab-03: Voltage, Current, Resistance and Power Measurements Lab-04: Inverters Lab-05: AND Gates Lab-06: OR Gates Lab-07: NAND and NOR Gates Lab-08: XOR and XNOR Gates Lab-09: Half- and Full-Adders Lab-10: Half- and Full-Subtractors Lab-11: 1’S Complement Adder /Subtractor Lab-12: 2's Complement Adder/Subtractor Lab-13: Multiplexers and Demultiplexers Appendix-E: List of 7400 Series Integrated Circuits E.1 Integrated Circuits Functioning E.2 Integrated Circuits Pin Configuration Appendix-F: List of 4000 Series Integrated Circuits F.1 Integrated Circuits Functioning F.2 Integrated Circuits Pin Configuration

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1- Introduction This book is devoted to provide both an understanding of the basic principles of digital logic design, and how these fundamental principles can be applied in the building of complex digital circuits using current technologies. Although the basic principles of digital logic design have not changed the design process and the implementation of circuits are everchanging. With the advances in fully integrated modern computer aided design (CAD) tools for logic synthesis, simulation, and the implementation of circuits in programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs), it is now possible to design and implement complex digital circuits very easily and quickly. That is, the book has the objective to enable readers grasping; 1- The concept and features of digital systems 2- Binary numbers and concepts analysis, 3- Number base conversion, complements and codes, 4- Digital logic gates, Integrated circuits and families, 5- The Boolean Algebra and Boolean functions with applications in logic circuits design, 6- The KMap method with different variables and applications in logic circuits design, 7- POS and SOP simplifications and applications in logic circuits design, 8- Design and realization of combinational logic circuits, including adders/subtractors and code conversions, Decoders and Encoders, Comparators, Multiplexers and Demultiplexers, and 9- Design and realization of sequential logic circuits starting by flip-flops towards registers and counters with different applications.

1.1 History of Computational Fabrics The computational technologies passed different eras that can be summarized as follows;  Discrete devices: relays, transistors (1940s-50s)  Discrete logic gates (1950s-60s)  Integrated circuits (1960s-70s) e.g. TTL packages  Gate Arrays (IBM 1970s): Transistors are pre-placed on the chip and Place and Route software puts the chip together automatically; only program the interconnect (mask programming)  Software Based Schemes (1970’s-present): Run instructions on a general purpose core  Application-Specific Integrated Circuit (ASIC) Design (1980’s to present) 1. Turn Verilog directly into layout using a library of standard cells 2. Effective for high-volume and efficient use of silicon area  Programmable Logic (1980’s to present) 1. A chip that be reprogrammed after it has been fabricated 2. Examples: PALs, EPROM, EEPROM, PLDs, FPGAs 3. Excellent support for mapping from Verilog The Evolution of Electronic Digital Devices can be described by the following stages;  Individual gates constructed from vacuum tubes and discrete passive components (e.g., resistors and capacitors).  Individual gates constructed from transistors and discrete passive components.  Integrated circuits (IC) consisting of several transistors, passive components fabricated in a single package of semiconductors.  IC's are also called chips.

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The hierarchy that clarifies the Basic Digital System Concepts including Embedded Systems Technologies is shown in (Fig. 1.1), where; • Levels of design abstraction and hierarchy – System (behavioral) level; highest level – Register level; widely used for design in industry today – Gate level; level we will deal with most in this class – Transistor level; lowest level • Top-down design: Begins at system level and moves toward transistor level • Typical way for complex digital systems to be designed in industry – CAD tools can synthesize lower levels of design abstraction from higher level descriptions • The point of logic design necessitates CAD tools with matured designer

SOC Programmable

ASIC / ASSP

Full Custom

Standard Cell

Mixte Technology

Logic Device (PLDs)

Gate Array

Processor

Simple PLD

Reconfigurable Processeur

DSP

Structured Asic

CPLD

ASIC - FPGA

Microcontroller

Sea of Gates

FPGA

Gate Array

Fig. 1.1: Embedded Systems Technologies

Embedded Processors

Analog

DSP = Digital Signal Processing ASIC = Application-Specific Integrated Circuit SOC = System On Chip ASSP = Application-Specific Standard Product PLD = Programmable Logic Devices CPLD = Complex Programmable Logic Devices FPGA = Field Programmable Gate Array

The process of Digital System Design is shown in (Fig. 1.2); Fig. 1.2: Integrated circuit design process

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The Hierarchical System Design can be valuable as; • Hierarchy is everywhere; – Systems consist of units – Units consist of printed circuit boards (PCBs) – PCBs consist of integrated circuits (ICs) – ICs consist of logic gates – Logic gates consist of transistors/devices • Allows to partition big design into manageable components • Once the circuit design works, the redesign is devoted to; – reuse it through hierarchical design – educes design time and design errors

1.2 Digital Systems Electronic circuits and systems may be divided into analog and digital;  Analog circuits are generally used with small signals and consequently operating in linear mode (e.g. Operational amplifiers)  Digital circuits are generally used with large signals and consequently operating in nonlinear mode (e.g. remote control of light in a parking area according to sunset –onand sunrise –off-) Analog signals are continuous and all possible values are represented (e.g. temperature sensors, pressure sensors, …) while digital signals are used to represent a finite number of discrete values. In addition, digital circuits and systems can be used to process both analog and digital signals, but not vice versa. Digital electronics involves circuits that have exactly two possible states either 0 or 1. That is, the electronic circuit operation can be described in terms of its voltage levels; one level is more positive than the other (corresponding to 1/H/T and zero/L/F, respectively) Digital signals are characterized by the following parameters (Fig. 1.3): 1- Switching (tsw) is the time required/taken to transfer from one state to the other. 2- Period (T) is the time duration between two successive T pulses tH 3- Frequency f=1/T 4- Rise time (tr) is the time required/taken to raise from 1.1 L to 0.9H of the signal 5- Fall time (tf) is the time required/taken to fall from H to L tL levels of the signal Fig. 1.3: Pulse waveform 6- Duty cycle is a measure of how symmetrical or how unsymmetrical the waveform is; D CH  t H / T, D CL  t L / T

Logic Conventions  The use of 0 (F) and 1(T) must be associated with the H and L voltages. It does not matter which way it is done.  If 1(T) is assigned to H and 0(F) to L we say we are using the positive logic convention.  If 0(F) is assigned to H and 1(T) to L we say we are using the negative logic convention.

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Digital IC is constructed using numerous transistors and resistors to perform a given logic operation, where the transistor is used as an electronic switch. Buffer is used to deliver the necessary load current without affecting the control circuit. Digital operations include the following; 1- Counting 2- Addition and subtraction 3- Logic functions (not, And, Or) 4- Comparison () 5- Input and/or output Basic Characteristics  Signals can assume only a discrete number of values, usually two.  For two-valued systems, it is usual to designate the two signal voltages as L and H (for Low and High) instead of referring to them by the actual voltages of the signals. Advantages of two-valued signals:  Noise immunity  Unlimited precision: use multiple signals  Simple, cheap and stable circuits  Easy to detect one of two values - thresholds Digital system models are based on discrete math and algorithms;  Boolean algebra  Graphical state transition graphs  Algorithms (flow charts, programs), Hardware Description Languages (HDL)

Levels of Integrated Circuits

 Small Scale Integrated circuits (SSI): A few gates per chip, most gate terminals available at chip pins.  Medium Scale Integrated circuits (MSI): Many gates and flip-flops interconnected on a chip (e.g., adder or register). SSI and MSI devices are also called standard chips in textbooks.  Large and Very Large Integrated Circuits (LSI and VLSI): Millions of transistors interconnected form complete systems (e.g., a microprocessor).  VLSI devices have hundreds to thousands of millions of transistors on a single chip.

The number of transistors that can be put on a single chip has been doubled every 1.5 to 2 years.

Types of VLSI Chips  Programmable Logic Devices 1. ROM’s PLA’s and PAL’s 2. Complex PLD’s (CPLD) 3. Field Programmable Gate Arrays (FPGA’s)  Custom or Semi-Custom Chips Applications-Specific Integrated Circuits (ASIC’s)

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Digital Systems  Most general model of a digital system ‒ Often referred to as General Sequential Logic (Huffman model) ‒ It consists of: Combinational logic that performs logical operations and Memory elements that stores data ‒ Combinational Logic: • Control Logic • Arithmetic/Logic Unit (ALU) • Multiplexers (MUX) ‒ Sequential Logic: • Program Memory (MEM) • Program Counter (PC) • Address Register (AR) • Data Register (DR) • Input Register (IN) • Output Register (OR) • Accumulator (AC) • ALU Carry Register (C) • Instruction Register (IR) • Timing Counter (TC)

Fig. 1.4

Digital System Design Levels

 System Design 1. High-level architecture 2. Hardware and software partitioning  Board-Level 1. Printed Circuit Board (PCB) development 2. Combine Integrated Circuits (ICs) to achieve design goals  Integrated Circuit Design 1. Programmable logic (PLAs, PALs, PLDs) 2. Semi-custom design (FPGAs) 3. Full custom (VLSI)  Device Electronics

Analog: Continuously varying signal Digital: Discrete values, assumed instantaneous transition In reality, digital assumption is approximation Fig. 1.5

Advantages of Digital Systems • • • • •

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Reproducible results Relative ease of design Flexibility and functionality High speed High accuracy

• • • • •

Small size Low cost Low power Steadily advancing technology Programmable logic devices

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Analog vs. Digital Systems Analog

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Digital

Continuous time varying Discrete signals sampled in time has two possible values: voltages and/or currents  0V, low, false (logic 0)  5V, high, true (logic 1) i.e. it is represented by binary values; 1/0, True/False, Hot/Cold, On/Off, etc. Basic elements of analog Basic elements of digital circuits: Logic gates: circuits:  AND • Resistors  OR • Capacitors  NOT • Inductors • Transistors Has ambiguity (different Has only one interpretation interpretations) Have additional data added to it to allow for detection and correction of errors Can be transmitted over a medium that introduces errors that are corrected at receiving end Can be used to process both analog and digital signals

Building binary digital solutions to computational problems;

Fig. 1.6

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Hardware Description Language (HDL) Logic synthesis using a Hardware Description Language (HDL) automates the most tedious and error-prone aspects of design;

Fig. 1.7

VHDL has been at the heart of electronic design productivity since initial ratification by the IEEE in 1987. For many years the electronic design automation industry has expanded the use of VHDL from initial concept of design documentation, to design implementation and functional verification. It can be said that VHDL initiated modern synthesis technology and enabled the development of ASIC semiconductor companies. The use of VHDL has evolved and its importance increased as semiconductor devices dimensions have shrunk. In the near past it was common to mix designs described with schematics and VHDL. But as design complexity grew, the industry abandoned schematics in favor of the hardware description language only. The industry has seen the use of VHDL’s package structure to allow designers, electronic design automation companies and the semiconductor industry to experiment with new language concepts to ensure good design tool and data interoperability. The Verilog HDL and VHDL industry standards teams collaborated on the use of a common timing data such as IEEE 1497 SDF, register transfer level (RTL) standards and more to improve design methodologies and the external connections provided to the hardware description languages. The design community continues to see benefits as the electronic design automation community continues to find new algorithms to work from VHDL design descriptions and related standards to again push designer productivity. In addition, as a new generation of designers of programmable logic devices move to the use of hardware description languages as the basis of their design methodology, there will be substantial growth in the number of VHDL users. In addition to the VHDL packages (Modelsim, Multisim, etc.) the MATLAB with SIMULINK can be used to model and simulate the operation of logic circuits. Moreover, the MATLAB with SIMULINK has the capability to transfer circuits into VHDL code towards the intended chip.

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Embedded Digital System

Fig. 1.8

A Wireless Microsensor System;

Fig. 1.9

Temporal Representations of Electronic Signals;

Fig. 1.10: DC or "Step" Signal

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Fig. 1.11a: Low Frequency Sinusoidal Signal

Fig. 1.11b: High Frequency Sinusoidal Signal

Fig. 1.12a: Amplitude Modulated (Analog) Signal

Fig. 1.12b: Frequency Modulated (Analog) Signal

9

Fig. 1.13: Real Analog Signal - Video Luminosity

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Fig. 1.14: Real Analog Signal - Bat Sonar

Real Digital Signal

Idealized Digital Signal

Frequency Modulated Digital Signal

Amplitude Modulated Digital Signal Fig. 1.15

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Digital Computer (Fig. 1.16); • Good example of a digital system • Basic architecture consists of: – CPU: Control Unit, ALU – Memory – Input/Output (I/O) Devices

Central Processing Unit (CPU) Control Unit

Arithmetic Logic Unit (ALU)

Memory: Program Memory (MEM) Data Register (DR) I/O Devices: Input Register (IN) Output Register (OR) Arithmetic-Logic Unit: Arithmetic/Logic Unit (ALU) Accumulator (AC) ALU Carry Register (C) Control Unit: Program Counter (PC) Address Register (AR) Instruction Register (IR) Timing Counter (TC) Control Logic

Memory

I/O Devices

Fig. 1.16: Digital Computer

Digital Computer Basic Operation; It consists of a series of instructions cycles, each consisting of;  Fetch: Fetch instruction from Program Memory (MEM) to Data Register (DR)  Decode: Pass instruction from DR to Instruction Register (IR) and decode using Control Logic  Execute: Perform operations decoded by Control Logic such as, - Get operands from MEM or Input Register (IN) - Arithmetic/logic operations - Store results in MEM or Output Register (OR)

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2- Numbers' Systems and Codes The objective is to be able to explain,  The difference between analog and digital systems and why digital systems are capable of greater accuracy.  The difference between combinational and sequential circuits.  Why two-valued signals and binary numbers are commonly used in digital systems Number systems and conversion; When you complete this chapter, you should be able to solve the following types of problems:  Given a positive integer, fraction, or mixed number in any base (2 through 16); convert to any other base. Justify the procedure used by using a power series expansion for the number.  Add, subtract, multiply, and divide positive binary numbers. Explain the addition and subtraction process in terms of carries and borrows.  Write negative binary numbers in sign and magnitude, 1’s complement, and 2’s complement forms. Add signed binary numbers using 1’s complement and 2’s complement arithmetic. Justify the methods used. State when an overflow occurs.  Represent a decimal number in binary-coded-decimal (BCD), 6-3-1-1 code, excess-3 code, etc. Given a set of weights, construct a weighted code. Objectives  Review the decimal number system  Count in the binary, octal and hexadecimal numbers' systems  Convert from decimal to binary, octal and hexadecimal and from binary, octal and hexadecimal to decimal  Convert between the binary, octal and hexadecimal number systems  Apply arithmetic operations to binary, octal and hexadecimal numbers  Determine the 1’s and 2’s complements of a binary number  Express signed binary numbers in sign-magnitude, 1’s complement, 2’s complement, and floating-point format  Carry out arithmetic operations with signed binary numbers  Express decimal numbers in binary coded decimal (BCD) form Add BCD numbers  Convert between the binary system, BCD, excess-3 and the Gray codes.  Interpret the American Standard Code for Information Interchange (ASCII)  Explain how to detect code errors, and discuss the cyclic redundancy check (CRC)

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2.1 Introductory Background 2.1.1 Motivation Digital systems have such a prominent role in everyday life that we refer to the present technological period as the digital age. Digital systems are used in communication, business transactions, traffic control, spacecraft guidance, medical treatment, weather monitoring, the Internet, and many other commercial, industrial, and scientific enterprises. We have digital telephones, digital televisions, digital versatile discs, digital cameras, handheld devices, and digital computers. We enjoy music downloaded to our portable media player and other handheld devices having high resolution displays. These devices have graphical user interfaces (GUIs), which enable them to execute commands that appear to the user to be simple, but which, in fact, involve precise execution of a sequence of complex internal instructions. Most, if not all, of these devices have a special-purpose digital computer embedded within them. The most striking property of the digital computer is its generality. It can follow a sequence of instructions, called a program that operates on given data. The user can specify and change the program or the data according to the specific need. Because of this flexibility, general-purpose digital computers can perform a variety of information-processing tasks that range over a wide spectrum of applications. One characteristic of digital systems is their ability to represent and manipulate discrete elements of information. Any set that is restricted to a finite number of elements contains discrete information. Examples of discrete sets are the 10 decimal digits, the 26 letters of the alphabet, the 52 playing cards, and the 64 squares of a chessboard. Early digital computers were used for numeric computations. In this case, the discrete elements were the digits. From this application, the term digital computer emerged. Discrete elements of information are represented in a digital system by physical quantities called signals. Electrical signals such as voltages and currents are the most common. Electronic devices called transistors predominate in the circuitry that implements these signals. The signals in most present-day electronic digital systems use just two discrete values and are therefore said to be binary. A binary digit, called a bit, has two values: 0 and 1. Discrete elements of information are represented with groups of bits called binary codes. For example, the decimal digits 0 through 9 are represented in a digital system with a code of four bits (e.g., the number 7 is represented by 0111). How a pattern of bits is interpreted as a number depends on the code system in which it resides. To make this distinction, we could write (0111)2 to indicate that the pattern 0111 is to be interpreted in a binary system, and (0111)10 to indicate that the reference system is decimal. Then 01112 = 710, which is not the same as 011110, or one hundred eleven. The subscript indicating the base for interpreting a pattern of bits will be used only when clarification is needed. Through various techniques, groups of bits can be made to represent discrete symbols, not necessarily numbers, which are then used to develop the system in a digital format. Thus, a digital system is a system that manipulates discrete elements of information represented internally in binary form. In today’s technology, binary systems are most practical because, as we will see, they can be implemented with electronic components. Discrete quantities of information either emerge from the nature of the data being processed or may be quantized from a continuous process. On the one hand, a payroll schedule is an inherently discrete process that contains employee names, social security numbers, weekly salaries, income taxes, and so on. An employee’s paycheck is processed by means of discrete data values such as letters of the alphabet (names), digits (salary), and special symbols (such as $). On the other hand, a research scientist may observe a continuous process, but record

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only specific quantities in tabular form. The scientist is thus quantizing continuous data, making each number in his or her table a discrete quantity. In many cases, the quantization of a process can be performed automatically by an analog-to-digital converter, a device that forms a digital (discrete) representation of analog (continuous) quantity. The general-purpose digital computer is the best-known example of a digital system. The major parts of a computer are a memory unit, a central processing unit, and input–output units. The memory unit stores programs as well as input, output, and intermediate data. The central processing unit performs arithmetic and other data-processing operations as specified by the program. The program and data prepared by a user are transferred into memory by means of an input device such as a keyboard. An output device, such as a printer, receives the results of the computations, and the printed results are presented to the user. A digital computer can accommodate many input and output devices. One very useful device is a communication unit that provides interaction with other users through the Internet. A digital computer is a powerful instrument that can perform not only arithmetic computations, but also logical operations. In addition, it can be programmed to make decisions based on internal and external conditions. There are fundamental reasons that commercial products are made with digital circuits. Like a digital computer, most digital devices are programmable. By changing the program in a programmable device, the same underlying hardware can be used for many different applications, thereby allowing its cost of development to be spread across a wider customer base. Dramatic cost reductions in digital devices have come about because of advances in digital integrated circuit technology. As the number of transistors that can be put on a piece of silicon increases to produce complex functions, the cost per unit decreases and digital devices can be bought at an increasingly reduced price. Equipment built with digital integrated circuits can perform at a speed of hundreds of millions of operations per second. Digital systems can be made to operate with extreme reliability by using error-correcting codes. An example of this strategy is the digital versatile disk (DVD), in which digital information representing video, audio, and other data is recorded without the loss of a single item. Digital information on a DVD is recorded in such a way that, by examining the code in each digital sample before it is played back, any error can be automatically identified and corrected. A digital system is an interconnection of digital modules. To understand the operation of each digital module, it is necessary to have a basic knowledge of digital circuits and their logical function. The first seven chapters of this book present the basic tools of digital design, such as logic gate structures, combinational and sequential circuits, and programmable logic devices.

2.1.2 Computers and Numbers Recall that the ALU performs all the arithmetic and logic operations. To achieve this task it is must be capable of representing the operands as binary digits. For centuries, most civilizations have performed arithmetic by counting in groups of ten and there are societies that even today, count differently, but such groups are rare. Speaking about groups of ten means for example, that one hundred (100) is really ten groups of ten; one thousand is really one hundred groups of ten or more precisely, ten groups of ten groups of ten; one million would actually be ten groups of ten groups of ten groups of ten groups of ten groups of ten. For example; 1 million = 10 × 10 × 10 × 10 × 10 × 10 = 106 or 1 million = 10( 10( 10( 10( 10( 10) ) ) ) ) = 106 The latter representation illustrates the grouping by tens concept perhaps a bit more clearly.

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As man began to build machines to perform computations, it seemed both natural and logical to emulate the human way of counting as well as doing arithmetic. When Sir Charles Babbage built his analytic engine, he devised a series of gears that would mesh with a series of wheels; each wheel represented a numeric position (units, tens, hundreds, thousands, and so forth), and each position was engineered to represent any of ten possible digits. This was truly a 10state machine. The problem was that the machine’s excessive complexity required a science of machined parts that was far beyond the capability of extant technology. Nevertheless, Babbage’s ideas found their way into 20th century adding machines and electric calculators; definitely NOT the hand held kind though. Electrically, it was possible to represent each digit by a different voltage level, and some analog computers successfully used this ploy though serious accuracy was a challenge never readily solvable. When John Atanasoff created the first electronic digital computer in 1933, he devised computational circuits around a different concept. His circuits would represent only two possible states: on and off. This suggested a bivalent system in which only two values could exist: a value of 1 was assigned to the on state and a value of 0 was used to represent the off state. What Atanasoff did was make use of what had been previously an academic concept; performing arithmetic in a numeric base other than ten. In Atanasoff’s system, arithmetic had to be performed using only two digits (0 and 1). He gave us a practical use for the binary number system also referred to as the base 2 system. It turns out that there are an infinite number of number systems, each with its own base. But before we investigate specific number systems that are used in various aspects of computing, it will prove worthwhile to discuss the general attributes ascribed to all number systems. Every number system consists of a group size for counting purposes. This group size is called the base of the number system. For example, the decimal number system with which we are most familiar has a base of 10. The binary system described earlier has a base of two. Each number system consists of a set of digits. Digits are numbered consecutively with zero (0) always being the first digit in sequence. Each remaining digit is generated by adding one to the previous digit until the cardinality of the set of digits equals the size of the base. The cardinality of a set is the number of elements contained in the set. The base number itself is never a digit. With all number systems, when one is added to the largest digit in the system, the resulting number consists of a sum of zero and a carry of one. This phenomenon is represented in the base-ten system as follows: 9 +1 10 In the binary system, we would have 1 + 1 = 10. Note that we have the same two digits for our summation in each case but in the decimal system, our sum represents the value ten whereas in binary system, the sum has an equivalent value of two. One final notion about number systems concerns positional value. Consider the base 10 number 33,333; where each ‘3’ represents a different quantity. The left most ‘3’; also known as the most significant digit (MSD), represents the value thirty thousand, whereas the ‘3’ on the right; also known as the least significant digit (LSD), represents the value of three. Note that in base ten, it appears that the positional values are associated with successive powers of the base. In fact, every number system has a unit's position, the position located immediately

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to the left of the fraction point. The corresponding power of the base is zero for the units position and any number raised to the zero power, does yield one from whence the units position takes its name. As we proceed in the direction of increasing significance (moving left from the fraction point), the powers increase so that we have a tens position, hundreds position, thousands position and so forth. The following diagram, Fig. 2.1, illustrates this idea; Strictly speaking, 101 . . . 102 100 1072 103 computers are modeled on the binary or base-2 units number system where tens the only permissible hundreds digits are 0 and 1. We etc. will also discuss the thousands base-8 (octal) and baseFig. 2.1 16 (hexadecimal) number systems because they bear a close relationship to binary and are often used as shorthand representations of binary numbers. Numbers' Systems: Base Binary (2) Octal (8) Decimal (10) Hexadecimal (16)

Digits

Radix

0,1 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7,8,9 0,1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F

b or B o,O d , D , no radix h or H

Examples 10100111B 451057O 910456D A1079CH

(10100111)2 (451057)8 (910456)10 (A1079C)16

 Number system consists of an ordered set of digits, with relations defined for +, -, * and /.  The radix (r) or base of a number system indicates the total number of digits allowed in the number system; common number system includes: - decimal - binary - octal - hexadecimal Spatial units of measure used in relation to computer storage capacities: Unit Symbol Power of 2 Bytes 0 Byte 2 1 Kilobyte KB 210 1,024 20 Megabyte MB 2 1,048,576 30 Gigabyte GB 2 1,073,741,824 Terabyte TB 240 1,099,511,627,776      

28 bytes = 256 bytes = 100H bytes 10 1 KB = 2 bytes = 1024 bytes = 400H bytes 64 KB = 216 bytes = 65536 bytes = 10000H bytes 1 MB = 220 bytes = 1048576 bytes = 100000H bytes 16 bits (two bytes) is called a word, 32 bits (four bytes) is called a double word, etc.

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2.1.3 Binary Number System Applications The most common application for the binary number system can be found in computers' technology and computerized industrial applications such as robots, CNC (Computer Numerical Control), etc. All computer languages and programming are based on the 2-digit number system used in digital encoding. Digital encoding is the process of capturing data and representing it with discreet bits of information. These discreet bits consist of the 0s and 1s of the binary system. For example, the images you see on your computer screen have been encoded with a binary line for each pixel. If a screen is using a 16-bit code, then each pixel has been told what color to display based on which bits are 0s and which bits are 1s. As a result, 216 represent 65,536 different colors. Also, the binary number system can be found in a branch of mathematics known as Boolean algebra. This field of mathematics is concerned with logic and truth values. Here, statements that are either true or false are then assigned a 0 or 1. Alternatively, concerning electricity, 0 can be defined as any voltage less than 2V, and 1 as any voltage greater than 4V. Then we can use these values to control things and do additional calculations, in pretty much the same way you do calculations with decimal numbers.

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2.2 Decimal (Base-10) Numbers Decimal numbers use the digits 0-9 and powers of 10, where the position of each digit in a weighted number system is assigned a weight based on the base or radix of the system. The radix of decimal numbers is ten (10), because only ten digits (0 through 9) are used to represent any number. The column weights of decimal numbers are powers of ten that increase from right to left beginning with 100 =1; e.g. …105 104 103 102 101 100 For fractional decimal numbers, the column weights are negative powers of ten that decrease from left to right: e.g. 102 101 100. 10-1 10-2 10-3 10-4 … The value of a decimal number can be calculated by multiplying the digit by the value of each place and adding the results for each digit. The value of each place is determined by the powers of 10 starting at 0 (10 to the 0th power is 1) and increasing from right to left. Thus, decimal numbers can be expressed as the sum of the products of each digit times the column value for that digit as follows;  (9240) = (9 x 103) + (2 x 102) + (4 x 101) + (0 x 100) or  (9240) = 9 x 1000 + 2 x 100 + 4 x 10 + 0 x 1 

321 = 1 * 1 (10 to the power 0) + 2 * 10 (10 to the 1st power) + 3 * 100 (10 to the 2nd power) = 1 + 20 + 300 = 321. 100’s place 3

10’s place 2

1’s place 1

321 = 300 + 20 + 1 = 321.

Example-2.2.1: Discuss the number 3027D (302710)  302710 : ‒ The 7 is in the 1s position and is equal to 7 x 100, or simply 7 x 1; ‒ the 2 is in the 10s position and is equal to 2 x 101, or 20; ‒ the 0 is in the 100s position and is equal to 0 x 102, or 0 x 100; and ‒ the 3 is in the 1000s position and is equal to 3 x 103, or 3 x 1000.  Note that starting on the right, the powers start at 0 and increment by 1 for every place moving to the left.

Example-2.2.2: Consider the number 257.56, where each digit has a value of 0 through 9 and has a place value; Express the number as the sum of values of each digit. Solution: 257.76  2  10 2  5  101  7  10 0  7  10 1  6  10 2  200  50 7  0.7  0.06

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Example-2.2.3: Multiplier Digits

x100000 2 Most Significant Bit (MSB)

x10000 3

x1000 1

x100 4

x10 6

x1 7 Least Significant Bit (LSB)

In the decimal system (base 10), you should be able to see that each part of the number increases in multiples of ten. The least significant part is that which has the lowest value in this case 7 units, and the most significant part is the value of the highest multiple, in this case 200000.

2.3 Binary (Base-2) Numbers Binary numbers use the digits 0-1 and powers of 2, where the Binary number system is called Base 2 because there are only two numbers (0 and 1) that make up its set of digits. Binary numbers are the language of electricity, where a 1 = voltage and a 0 = no voltage. More precisely, a value of ‘1’ is represented by a “high” voltage, generally 3-5 volts while a value of ‘0’ is represented by a “low” voltage, Number of 1’s or units normally 0-2 volts. Actually, these binary digits Number of 2’s (called bits for short) are the only numeric forms Number of 4’s a computer can recognize and is the state by Number of 8’s which all data is moved within a computer. The Number of 16’s relative ordering of the digits correspond to Fig. 2.2: Successive powers of two successive powers of two is shown in Fig. 2.2. For digital systems, the binary number system is used which has a radix of two and uses the digits 0 and 1 to represent quantities. The column weights of binary numbers are powers of two that increase from right to left beginning with 20 =1; e.g. …25 24 23 22 21 20 For fractional binary numbers, the column weights are negative powers of two that decrease from left to right: 22 21 20. 2-1 2-2 2-3 2-4… Dec Binary Number A binary counting sequence for numbers from zero to fifteen contains pattern of zeros and ones in each column as shown in the following table: The decimal value of a binary number can be calculated by multiplying the digit by the value of each place and adding the results for each digit. The value of each place is determined by the powers of 2 starting at 0 (2 to the 0th power is 1) and increasing from right to left.

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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

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For example;  111 = 1 * 1 (2 to the power 0) + 1 * 2 (2 to the power 1) + 1 * 4 (2 to the power 2). 4’s place 1

2’s place 1

1’s place 1

(111)2 = 4 + 2 + 1 = (7)10 As the above table indicates, we can count in binary just as readily as we can count in decimal but simply needs more digits to represent the same quantities. Digital counters frequently have this same pattern of digits. Binary Numbers has;  Base or radix 2 number system,  Binary digit is called a bit, and  Numbers are 0 and 1 only. Thus, numbers can be expressed in powers of 2 as follows: 213 212 211 210 29 28 27 26 25 24 23 22 21 20 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1 Bits in computer memory are organized into bytes; each byte has 8 bits. The first 8 values in powers of 2 are 1, 2, 4, 8, 16, 32, 64, 128. So you can store the values 0 to 255 in 1 byte (8 bits).

Example-2.3.1: 

128 64 32 16 8 4 2 1 1 1 1 1 1 1 1 1 (1111 1111)2 = 128 + 64 + 32 + 16 + 8 + 4 + 2 + 1 = (255)10.



128 64 32 16 8 4 0 1 0 0 1 0 (0100 1011)2 = 64 + 8 + 2 + 1 = (75)10

2 1

1 1

Example-2.3.2: Consider the number (1011.0011) in base-2, show its representation as a decimal number. Solution: (1011.0011) 2  (1  2 3  0  2 2  1  21  1  2 0 )  (0  2 1  0  2 2  1  2 3  1  2 4 ) 10





 (11.1875)10 To convert from decimal to binary use the greedy algorithm: Start with the first power of two less than or equal to the decimal number and turn that bit to 1. Then subtract the power of two from the decimal number and continue until done. To convert 9 to binary start by using 1 for the 8’s place and then (9 – 8) is 1 so use the 1 in the 1’s place, i.e. (9)10 = (1001)2

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2.4 Octal (Base 8) Numbers The octal number system (or base 8 number system) uses the digits 0-7 and powers of 8 to represent all numbers. It turns out that groups of three binary digits will represent any octal digit since binary 000 – 111 correspond to the values 0 – 7. Computer programmers made use of the octal number system in the late 1940s to make it easier to remember long strings of binary numbers. At that time, computers were still programmed in machine language, which was a straight binary language. There was no assembler language and certain languages like COBOL and FORTRAN were not even being thought about. In fact, both instructions and data were loaded into the computer’s memory by flipping toggle switches up or down to signify values of one and zero respectively. It seemed natural to one bright soul that the eight 3-binary digit patterns could be mapped to the digits 0 through 7. A simple substitution code was born and programmers quickly learned that they could translate something easy to remember like 31246 into the binary string 011001010100110. This simple substitution code became the first simplification to programming language use. The fact that the substitution patterns exactly portrayed the base 8 (octal) number system was likely not the intent of Number of 1’s or units these early programmers. It just happened to Number of 8’s turn out that way. The octal number system Number of 64’s consists of the digits 0, 1, 2, 3, 4, 5, 6, 7 as Number of 512’s mentioned previously; and like the binary and Number of 4096’s decimal systems, base 8 numbers have Fig. 2.3 position values associated with each digit in a number as shown in Fig. 2.3. For example, the octal number (32467)8 consists of the following: 7 units 6 eights 4 sixty-fours 2 five hundred twelves 3 four thousand ninety-sixes

Dec 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Binary Number 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0

Octal uses eight characters to represent the numbers 0 through 7 and there is no 8 or 9 character in octal. Octal is a weighted number system where the column weights are powers of 8, which increase from right to left beginning with 80 =1; e.g.; 83 82 81 80 For fractional octal numbers, the column weights are negative powers of 8 that decrease from left to right: 82 81 80. 8-1 8-2 8-3 8-4…  Base or radix 8 number system  1 octal digit is equivalent to 3 bits.  Numbers are 0-7.  Numbers are expressed as powers of 8. 80 = 1, 81 = 8, 82 = 64, 83 = 512, 84 = 4096.

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Octal 0 1 2 3 4 5 6 7 10 11 12 13 14 15 16 17 20

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Example-2.4.1: 

(32)8 = 2 * 1 + 3 * 8 = 2 + 24 = (26)10 64’s place 8’s place 1’s place 0 3 2



(110)8 = 0*1 + 1 * 8 + 1 * 64 = (72)10 64’s place 8’s place 1’s place 1 1 0

Example-2.4.2: Express the number (1526.76)8 as the sum of values of each digit. Solution: Start by writing the column weights: (1526.76)8

= (1 x 83) + (5 x 82) + (2 x 81) + (6 x 80) + (7 x 8-1) + (6 x 8-2)

2.5 Hexadecimal (Base-16) Numbers In addition to using powers of 16, the hexadecimal (base 16) number system requires sixteen digits; the first 10-digits are represented by 0-9 while the remaining six digits are represented by A for 10, B for 11, C for 12, D for 13, E for 14, and F for 15. Of course, other symbols could have been chosen just as easily, but the letters were and are now part of a standard notational form. Besides, we could not have permitted ‘10’ to follow ‘9’ because ‘10’ is actually two separate symbols. Hexadecimal numbers look weird and they demand a bit more concentration if we are to work with them readily. Groups of four binary digits can be used to represent Hexadecimal numbers since binary 0000-1111 represents constitutes a range of sixteen different values. Computers use the hexadecimal number system in ways that parallel the use of octal numbers. Prior to 1963, every computer that was programmed to manipulate characters used a special 6-bit code called BCD (Binary Coded Decimal) to represent numeric digits, upper case letters of the alphabet, and a variety of grammatical and arithmetic punctuation marks and symbols. This set of codes representing sixty-four characters could not be expanded to handle lower case letters. IBM engineers solved the problem by creating the framework for an 8-bit code called EBCDIC (Extended Binary Coded Decimal Interchange Code). It was a straightforward conversion to describe these 8-bit binary strings by two hexadecimal digits. Thus, for example, the bit pattern 1001 1100 translated directly into 9C in which the ‘9’ represented ‘1001’ and ‘C’ corresponded to the string ‘1100’; a simple substitution. IBM unveiled this new system for its System 360 (later 370) family of computers and the use of “hex” codes became fairly common. For reasons too lengthy to discuss here, the Number of 1’s or units Federal Government chose not to adopt IBM’s Number of 16’s character code as a national standard, despite Number of 256’s the fact that most computers in use at that Number of 4096’s Number of 65536’s time followed the EBCDIC de facto standard. Instead, the American National Standards Fig. 2.4 Institute (then known as ANSI but later renamed as the National Institute of Standards and Technology (NIST)), part of the Bureau of

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Standards, developed in conjunction with the electronics and telecommunications industries as a whole, the now standard ASCII character codes. Even though the meanings of the bit patterns are different, accustomed usage has caused the hexadecimal codes to remain with us as easy ways to recall large strings of binary data. Below are representations of both the base 16 positional values and the Base 16 equivalencies. Hexadecimal  Base or radix 16 number system  1 hex digit is equivalent to 4 bits.  Numbers are 0-9, A, B, C, D, E, and F.  (A)16 = (10)10, (B)16 = (11)10, (C)16 = (12)10, (D)16 = (13)10, (E)16 = (14)10, (F)16 = (15)10  Numbers are expressed as powers of 16.  160 = 1, 161 = 16, 162 = 256, 163 = 4096, 164 = 65536, … Thus the hexadecimal number (2B4F)16 consists of 15 units 4 sixteens 11 two hundred fifty-sixes 2 four thousand ninety-sixes Weights Dec 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

16 8 4 2 1 Binary Number 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0

Hexadecimal

0 1 2 3 4 5 6 7 8 9 A B C D E F 10

Hexadecimal uses sixteen characters to represent numbers: the numbers 0 through 9 and the alphabetic characters A through F. Hexadecimal is a weighted number system where the column weights are powers of 16, which increase from right to left beginning with 16 0 =1; e.g.; 163 162 161 160 For fractional hexadecimal numbers, the column weights are negative powers of 16 that decrease from left to right: 162 161 160. 16-1 16-2 16-3 16-4…

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Example-2.5.1: 

(A7)16 = A * 16 + 7 * 1 = 10 * 16 + 7 * 1 = 160 + 7 = (167)10 256’s place 0



16’s place A

1’s place 7

(110)16 = 1 * 256 + 1 * 16 + 0 * 1 = 10 * 16 + 7 * 1 = 256 + 16 + 0 = (272)10

Example-2.5.2: Express the number (1A2F.B6)16 as the sum of values of each digit. Solution: Start by writing the column weights: (1A2F.B6)16 = (1 x 163) + (A x 162) + (2 x 161) + (F x 160) + (B x 16-1) + (6 x 16-2) = (1 x 163) + (10 x 162) + (2 x 161) + (15 x 160) + (11 x 16-1) + (6 x 16-2) Colors are made up of red, green, and blue values from 0 – 255 (8 bits). You can specify the amount of red, green, and blue using 2 digit hexadecimal numbers (00 is 0 and FF is 255).

2.6 Numbers' Conversions Conversions from Binary to hexadecimal/octal and hexadecimal/octal to binary are straightforward. An unsigned or a positive integer in base b with n digits: (d n - 1dn decimal (base 10) value:

-2

. . . d2d1d0) has the

 n 1  d n 1 * b n 1  d n 1 * b n 1  d n  2 * b n  2  ......  d 2 * b 2  d 1 * b1  d 0 * b 0   d i * b i   i 0 10 where all the arithmetic is done in base 10.

To convert an unsigned or a positive decimal number to base b; repeatedly divide the number and then each succeeding quotient by b until a quotient of zero is obtained. The remainders from the last to the first; but converted to base b, form the required number. An appropriate number of leading zeroes is prefixed to obtain the required number of bits.

Conversion between Bases: In general, conversion between bases can be done via the following diagram:

 Base r  Decimal ‒ Weighted position notation for integer and fraction  Decimal  Base r - Integer number: repeated division by r - fractions: repeated multiplication by r

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Base-2

Base-2 Base-3 . .

Base-r

Numbers Systems and Codes

Base-3 Decimal . .

Base-r Fig. 2.5: Numbers' Conversion

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2.6.1 Decimal Conversions You can convert a decimal to any other base (2, 8, 16) by repeatedly dividing by that base. In addition, a decimal fraction can be converted to other base (2, 8, 16) by repeatedly multiplying the fractional results of successive multiplications by the other base (2, 8, 16).

Example-2.6.1: Convert the decimal number (49.188) into binary. Solution:  The decimal number 49: the column weights double in each position to the right, thus write down column weights until the last number is larger than the one you want to convert; 26 25 24 23 22 21 20. 64 32 16 8 4 2 1. 0 1 1 0 0 0 1.  Or convert the decimal number 49 to binary by repeatedly dividing by 2; You can do this by “reverse division” and the answer will read from left to right. Put quotients to the left and remainders on top

Fig. 2.6

 Convert the decimal fraction (.188) to binary by repeatedly multiplying the fractional results of successive multiplications by 2 as follows; 0.188 x 2 = 0.376 carry = 0 (MSB) 0.376 x 2 = 0.752 carry = 0 0.752 x 2 = 1.504 carry = 1 0.504 x 2 = 1.008 carry = 1 0.008 x 2 = 0.016 carry = 0 (LSB) Answer = .00110 (for five significant digits) Converting from decimal to binary is carried out using a simple paper and pencil method where the decimal number is taken and repeatedly divide it by 2, keeping track of the integer remainder.

Example-2.6.2: let's convert the decimal value (57) to binary using this method; ____ 2 ) 57 28 with a remainder of 1 (now divide 28 by 2) 14 with a remainder of 0 7 with a remainder of 0 3 with a remainder of 1 1 with a remainder of 1 0 with a remainder of 1. Now take all the remainders starting with the last one and write your binary number: (1 1 1 0 0 1)2 Converting from Decimal (base 10) to Binary (base 2) begins by dividing the decimal number by the binary base number (2) using the division algorithm. This division will produce an

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integer quotient and an integer remainder of either 1 or 0. Note that the use of integer remainders is frequently called modulo division. If the quotient is evenly divisible by the base number, use 0 as the remainder. Otherwise, the remainder will be the digit 1. The next step will require dividing the new quotient by the base number again to find yet another quotient and a remainder. Continue with this process, recording the remainders in order, and writing them from right to left order until you produce a zero with a corresponding remainder of one. This is the last remainder to record. The equivalent number in the new base is the string of integer remainders recorded.

Example-2.6.3: Convert the number (6)10 into binary, LSB MSB 1 3 0 2 3 2 6 2 1 2 6 2 1 0 1  (6)10 = (110)2

Shorthand Method  6 ÷ 2 = 3 R 0 LSD  3÷2=1R1  1 ÷ 2 = 0 R 1 MSD

The shorthand method is presented because many find it convenient to express divisions by two in this manner. If the method makes you uncomfortable, then by all means follow standard long division practices. Now let’s try a more complicated problem. For example; convert (274)10 to its binary (base 2) equivalent; Shorthand Method 274 ÷ 2 = 137 R 0 LSD 137 ÷ 2 = 68 R 1

8÷2=4R0

68 ÷ 2 = 34 R 0

4÷2=2R0

34 ÷ 2 = 17 R 0

2÷2=1R0

17 ÷ 2 = 8 R 1

1 ÷ 2 = 0 R 1 MSD

continue

(274)10 = (100010010)2

Example-2.6.4: Convert (51)10 to binary  51  2 = 25 remainder is 1  25  2 = 12 remainder is 1  12  2 = 6 remainder is 0  6  2 = 3 remainder is 0  3  2 = 1 remainder is 1  1  2 = 0 remainder is 1 Answer = 1 1 0 0 1 1 The answer is read from bottom (MSB) to top (LSB) as (110011) 2

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Example-2.6.5: Convert a decimal number (11.1875) into a binary number. First, look at the integer part: 11; 1. Divide 11 by 2; this gives a quotient of 5 and a remainder of 1. Since the remainder is 1, a0  1 . 2. Divide the quotient 5 by 2; This gives a quotient of 2 and a remainder of 1. Since the remainder is 1, a1  1 . 3. Divide the quotient 2 by 2; This gives a quotient of 1 and a remainder of 0. Since the remainder is 0, a2  0 . 4. Divide the quotient 1 by 2; This gives a quotient of 0 and a remainder of 1. Since the remainder is , a3  1 . Since the quotient now is 0, the process is stopped and the above steps are summarized in the following table: Converting a base-10 integer to binary representation Quotient Remainder 1  a0 11/2 5 5/2 2/2

2 1

1/2

0

1  a1 0  a2 1  a3

Hence

(11)10  (a3 a2 a1a0 ) 2  (1011) 2 For any integer, the algorithm for finding the binary equivalent is given in the flowchart shown in Fig. 2.7a. Now let us look at the decimal part, that is, 0.1875;  Multiply 0.1875 by 2. This gives 0.375. The number before the decimal is 0 and the number after the decimal is 0.375. Since the number before the decimal is 0, a1  0 .  Multiply the number after the decimal, that is, 0.375 by 2. This gives 0.75. The number before the decimal is 0 and the number after the decimal is 0.75. Since the number before the decimal is 0, a2  0 .  Multiply the number after the decimal, that is, 0.75 by 2. This gives 1.5. The number before the decimal is 1 and the number after the decimal is 0.5. Since the number before the decimal is 1, a 3  1 .  Multiply the number after the decimal, that is, 0.5 by 2. This gives 1.0. The number before the decimal is 1 and the number after the decimal is 0. Since the number before the decimal is 1, a4  1 .

Since the number after the decimal is 0, the conversion is complete and the above steps are summarized in Table 2. Table 2: Converting a base-10 fraction to binary representation Number Number after decimal Number before decimal 0  a1 0.1875  2 0.375 0.375 0  a 2 0.375  2 0.75 0.75 1  a 3 0.75  2 1.5 0.5 0.5  2

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1.0

1  a4

0.0

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Hence (0.1875)10  (a1a 2 a3a 4 ) 2

 (0.0011) 2 The algorithm for any fraction is given in a flowchart shown in Fig. 2.7b. Having calculated (11)10  (1011) 2 and (0.1875)10  (0.0011) 2 , we have (11.1875)10  (1011.0011) 2 . Start

Input (N)10

Integer N to be converted to binary format

i=0

Divide N by 2 to get the quotient Q & remainder R

i = i+1

No

ai = R

is Q = 0? Yes

n=i (N)10 = (an. . .a0)2

STOP Fig. 2.7a: Integer Conversion

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Start

Input (F)10

Fraction F to be converted to binary format

i  1

Multiply F by 2 to get the number before decimal, S and after decimal, T

i  i 1

ai = R

No is T = 0? Yes n=i (F)10 = (a-1. . .a-n)2

STOP Fig. 2.7b: Fraction Conversion In the above example, when we were converting the fractional part of the number, we were left with 0 after the decimal number and used that as a place to stop. In many cases, we are never left with a 0 after the decimal number. For example, finding the binary equivalent of 0.3 is summarized in Table 3. Table 3: Converting a base-10 fraction to approximate binary representation Number Number after decimal Number before decimal 0  a1 0.3  2 0.6 0.6 1  a2 0.6  2 1.2 0.2 0  a 3 0.2  2 0.4 0.4

0  a 4 0.4  2 0.8 0.8 1  a 5 0.8  2 1.6 0.6 As you can see the process will never end, in which case, the number can only be approximated in binary format, that is, (0.3)10  (a 1a  2 a 3a  4 a 5 ) 2  (0.01001) 2

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The mathematics behinds this process of converting a decimal number to binary format can be illustrated as follows: Let z be the decimal number written as z  x. y where x is the integer part and y is the fractional part. To find the binary equivalent of x ; it can be written as x  a n 2 n  a n 1 2 n 1  ...  a 0 2 0 If we can now find a0 ,. . ., a n in the above equation then ( x)10  (an an1 . . .a0 ) 2 To find the binary equivalent of y , it can be written as y  b1 2 1  b 2 2 2  ...  b m 2  m If we can now find b1 ,. . ., bm in the above equation then ( y)10  (b1b2 . . .bm ) 2 Let us look at this using the same example as before.

Example-2.6.6 Convert (11.1875)10 to base 2. Solution To convert (11)10 to base 2, what is the highest power of 2 that is part of 11. That power is 3, as 2 3  8 to give 11  2 3  3 What is the highest power of 2 that is part of 3. That power is 1, as 21  2 to give 3  21  1 So 11  2 3  3  2 3  21  1 What is the highest power of 2 that is part of 1. That power is 0, as 2 0  1 to give 1  20 Hence (11)10  2 3  21  1  2 3  21  2 0  1  2 3  0  2 2  1  21  1  2 0  (1011) 2 To convert (0.1875)10 to the base 2, we proceed as follows. What is the smallest negative power of 2 that is less than or equal to 0.1875. That power is  3 as 23  0.125 . So 0.1875  23  0.0625 What is the next smallest negative power of 2 that is less than or equal to 0.0625. That power is  4 as 2 4  0.0625 . So 0.1875  23  24 Hence

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(0.1875)10  2 3  0.0625  2 3  2 4  0  2 1  0  2 2  1  2 3  1  2 4  (0.0011) 2

Since (11)10  (1011) 2 and (0.1875)10  (0.0011) 2 we get (11.1875)10  (1011.0011) 2

Example-2.6.7 Convert (13.875)10 to base 2. Solution For (13)10 , conversion to binary format is shown in Table 4. Table 4: Conversion of base-10 integer to binary format Quotient Remainder 1  a0 13/2 6 0  a1 6/2 3 1  a2 3/2 1 1  a3 1/2 0 So (13)10  (1101)2 Conversion of (0.875)10 to binary format is shown in Table 5. Table 5: Converting a base-10 fraction to binary representation Number after Number before Number decimal decimal 1  a1 0.875  2 1.75 0.75 1  a 2 0.75  2 1.5 0.5 1  a3 0.5  2 1.0 0.0 So (0.875)10  (0.111) 2 Hence (13.875)10  (1101.111)2 You can also convert decimal to hexadecimal in a similar fashion (repeatedly divide by 16 and keep track of the integer remainders) but it might be easier to convert the decimal number to binary first, then simply convert the binary number to hexadecimal.

Example-2.6.8: Convert (77)10 to hex 77  16 = 4 remainder is D 4  16 = 0 remainder is 4 The answer is read from bottom to top as (4D) 16, the same as with the binary case.

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Example-2.6.9: Convert 123 into binary. 2 123  62 remainder 1 2 62  31 remainder 0 2 31  15 remainder 1 2 15  7 remainder 1 2 7  3 remainder 1 2 3  1 remainder 1 2 1  0 remainder 1

Then the required binary number is taken from the remainder values written down at the end of each division as; Binary number = 1 1 1 1 1 0 1

Therefore 12310 = 11111012 Another method of conversion is the successive subtraction of the powers of 2, which sounds very grand but in reality is just about subtracting the largest multiple of 2 away from the number to convert, and then continuing to subtract the next highest multiple until you reach 0.

Example-2.6.10: Convert 20110 into binary. 256

128

64

32

16

8

4

2

1

Starting with the highest multiple of 256; the number to be converted is less than this so we cannot subtract 256 from it, so we enter a 0 in this column. 256 128 64 32 16 8 4 2 1 0 The next multiplier is 128 which we can subtract, so we put a 1 in this column. 256 128 64 32 16 8 4 2 1 0 1 We now have 201-128 = 73 left, our next multiple is 64 which we can again subtract so we place a 1 in this column. 256 128 64 32 16 8 4 2 1 0 1 1 We now have 73-64 = 9 left, so we cannot subtract 32, or 16, but we can subtract 8, so the table now looks like: 256 128 64 32 16 8 4 2 1 0 1 1 0 0 1 We are left with 9 – 8 = 1, and so it is not possible to subtract 4 or 2 but we need to subtract the last 1, so the full table becomes: 256 128 64 32 16 8 4 2 1 0 1 1 0 0 1 0 0 1

Therefore 20110 = 0110010012

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2.6.2 Binary Conversions The decimal equivalent of a binary number can be determined by adding the column values of all of the bits that are 1 and discarding all of the bits that are 0. Converting from Binary (base 2) to Decimal (base 10) begins by determining the position values for each digit in the base number to convert and then using the multiplication algorithm. Start with the right-most position and apply the base number to the power of 0, the next position to the left would apply the base number to the power of 1, and so forth. Next, multiply each integer in the base 2 number by its corresponding positional value. Lastly, sum all of the products; the summation is the base 10 equivalent of the binary number.

Binary into Decimal Example-2.6.11 Convert the binary number (100101.01)2 to decimal. Solution: Start by writing the column weights; then add the weights that correspond to each 1 in the number. 25 24 23 22 21 20 . 2-1 2-2 32 16 8 4 2 1 . ½ ¼ 1 0 0 1 0 1.0 1 32 + 4 + 1 + ¼ = 37¼

Example-2.6.12  The binary number (10010)2 is equal to (starting from the left) 16 + 0 + 0 + 2 + 0, or 18 in decimal.  The binary number (1011101)2 is equal to 64 + 0 + 16 + 8 + 4 + 0 + 1, or 93 in decimal.

Example-2.6.13 Consider the example below, (11101)2 1 1 1 0 1 Beginning Integers 4 3 2 1 0 2 2 2 2 2 Base to positional powers 16 8 4 2 1 Multiples of base number 1x16 1x8 1x4 0x2 1x1 Multiply position’s digit by the multiple of the base number 16 8 4 0 1 Add products to find base 10 Equivalent = 2910 Then, (11101)2 is equivalent to (29)10.

Example-2.6.14 A more complex example, convert (11000111010101)2 to its decimal equivalent; In this case, working from right to left on the binary number, you will need to sum the following: (1 + 0 + 4 + 0 + 16 + 0 + 64 + 128 + 256 + 0 + 0 + 0 + 4096 + 8192) to obtain the correct decimal equivalent value of (12757)10.

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Example-2.6.15 Convert the binary number (110011)2 to decimal. 1 1 0 0 1 1 Beginning Integers 25 24 23 22 21 20 Base to positional powers 32 16 8 4 2 1 Multiples of base number 1x32 1x16 0x8 0x4 1x2 1x1 Multiply position’s digit by the multiple of the base number 32 16 0 0 2 1 Add products to find base 10 Equivalent = 5110 Then, (110011)2 is equivalent to (51)10. Alternatively, the successive process is reversed; for the binary number to be converted we must add together all of the multipliers where there is a corresponding 1 in the binary.

Example-2.6.16: Convert (10011001)2 into decimal. You start with a simple grid as we used before, in this case only 8 cells are needed. 128 64 32 16 8 4 2 1 Fill in the binary number. 128 64 32 16 8 4 2 1 1 0 0 1 1 0 0 1 Add together all multipliers where binary number is a 1 i.e. 128+16+8+1 = 153.

Therefore 100110012 = 15310. Binary into Octal Converting from binary (base 2) to octal (base 8) begins simply by arranging the binary digits into groups of three (triplets). If the total number of binary digits is not divisible by three, leading zeros may be added. It is important to remember to begin grouping from the least significant bit towards the most significant bit. Next, each triplet is converted to the octal number equivalent according to the coding system previously described. Recall that the range of equivalencies is from 0 (000) to 7 (111). This process is referred to as 3-bit substitution code. Binary number can easily be converted to octal by grouping 3-bits at a time and writing the equivalent octal character for each group.

Example-2.6.17 Express (1 001 011 000 001 110)2 in octal: Group the binary number by 3-bits starting from the right yields; (1 001 011 000 001 110)2 = (001 001 011 000 001 110)2 = (113016)8 The conversion from octal to binary is a simple process reversal that begins by converting the most significant octal digit (left most digit) to its binary equivalent. Repeat the conversion with each octal number, working your way towards the least significant digit (right most digit). After converting each octal number, concatenate all binary numbers together.

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Example-2.6.18 Convert (6132)8 into binary MSB LSB 6 = 110 1 = 001 3 = 011 2 = 010 (110 001 011 010)2  (6132)8 = (110001011010)2.

Also, (613.2)8 = (110 001 011.010)2

Group the binary numbers into triplets beginning at the binary point and working outward in both directions. If the number of binary digits is not divisible by three, leading or trailing zeros may be added at either end without altering the value of the number to be converted. Next, each triplet is replaced by its octal equivalent.

Example-2.6.19 Convert (1100110.10)2 into Octal; (1100110.10)2 = (001 100 110.100)2 = (146.4)8

Binary into Hexadecimal Converting from binary to hexadecimal (base 16) is an identical procedure to that used for converting from binary to octal except that we use the 4-bit substitution code instead of the 3bit one. The procedure begins simply by arranging our binary number into groups of four bits. If the number of binary digits is not divisible by four, leading zeros may be added. Next, each group of four binary digits is converted to a corresponding hexadecimal digit. Recall that these hex digits range from 0 (0000) to F (1111). This process is referred to as the 4-bit substitution code. Group the binary numbers into fours beginning at the binary point and working outward in both directions. If the number of binary digits is not divisible by four, leading or trailing zeros may be added at either end. Next, each group of four binary digits is converted to its corresponding hexadecimal digit that, as previously noted, ranges from 0 (0000) to F (1111).

Binary number can easily be converted to hexadecimal by grouping the binary number in groups of 4-bits at a time and writing the equivalent hexadecimal character for each group;

Example-2.6.20 Express (1 001 011 000 001 110.011 11)2 in hexadecimal: Group the binary number by 4-bits starting from the right yields; (1 001 011 000 001 110.011 11)2 = (1001 0110 0000 1110 . 0111 1000)2 = (960E.78)16 Another example, the binary value (111 1000 1010 1001 0011 0101 1100)2 Equals ( 7

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8

A

9

3

5

C) 16

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The conversion from hexadecimal to binary again is similar to the previously explained octal to binary conversion. Simply replace each digit to the left and right of the fraction point with its 4-bit binary equivalent. The process begins by converting the most significant hex digit to its binary equivalent. We repeat the conversion with each successive digit, working our way towards the least significant digit. After converting each hexadecimal digit to its 4-digit binary counterpart, we merge all binary digits together to obtain our answer. That is, after converting each hexadecimal digit, concatenate all the binary digits separated by a binary point positioned appropriately.

Example-2.6.21 Convert (395F.4B)16 into binary

MSB 3 = 0011

9 = 1001

5 = 0101

LSB F = 1111

.

4 = 0100

B = 1011

(0011 1001 0101 1111 . 0100 1011)2

 (395F.4B)16 = (0011 1001 0101 1111. 0100 1011)2

2.6.3 Octal Conversions Decimal and Octal Conversion Converting a decimal number (base 10) to octal (base 8) begins by dividing the decimal number by eight, the octal base number. This will yield an integer quotient and a remainder that ranges between zero and seven. This modulo division is identical to that used to convert decimal numbers into binary. Note that the remainder will be one of the octal digits. The next step requires us to divide the new quotient by eight again to find yet another quotient and remainder. Continue with this process, recording the remainders in order, writing them from right to the left until the last quotient is zero. At this point, the last remainder is the most significant digit of the base 8 number. The equivalent number in the new base is the string of integer remainders recorded.

Example-2.6.22: Convert (161)10 into Octal LSB MSB 2 20 0 8 20 8 161 8 2 16 160 0 4 1 2  (161)10 = (241)8

Shorthand Method  161 ÷ 8 = 20 R 1 LSD  20 ÷ 8 = 2 R4  2÷8=0 R 2 MSD

Example-2.6.23: Convert (177)10 into Octal  177  8 = 22 remainder is 1  22  8 = 2 remainder is 6  2  8 = 0 remainder is 2 The answer is read from bottom to top as (261) 8, the same as with the binary case.

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Converting from octal to decimal requires an understanding of the positional value concept. We begin by determining the positional values for each digit in the octal number being converted. As with any number system, the right-most position value is calculated by raising the base (8 in this case) to the power of 0. Each successive position moving to our left increases the power of the base by one. Next, we multiply each base 8 digit by its corresponding position value. Lastly, we sum all the products and the resulting number is the base-10 equivalent of the original base-8 number.

Example-2.6.24: Convert the number (47326)8 into decimal 4 7 3 2 6 4 3 2 1 8 8 8 8 80 4096 512 64 8 1 4x4096 7x512 3x64 2x8 6x1 16384 3584 192 16 6 Then, (47326)8 yields (20182)10.

Beginning Digits Base 8 positional powers Base 8 positional values Multiply the top row by row 3 yielding these products:

Add products to find base 10 Equivalent = 20182

Example-2.6.25: Convert the number (632)8 into decimal Beginning Digits 6 3 2 2 1 0 Base 8 positional powers 8 8 8 Base 8 positional values 64 8 1 6x64 3x8 2x1 Multiply the top row by row 3 yielding these products: 384 24 2 Add products to find base 10 Equivalent = 410 Then, (632)8 = (410)10.

2.6.4 Hexadecimal Conversions Decimal and Hexadecimal Conversion Converting from base 10 to base 16 begins by dividing the decimal number by sixteen. As before, this modulo division will produce an integer quotient and most likely, an integer remainder as well. When the quotient divides evenly, the remainder will be zero. Otherwise, the remainder will be in the [1-15] interval. The next step will require us to divide the new quotient by sixteen again yielding another quotient and remainder. We continue with this process, until we produce a quotient of zero along with a non-zero remainder. Unlike previous conversions using the division algorithm in which we recorded the remainders in order, and wrote them in a right to the left sequence, we must first identify those remainders that were greater than nine. We must replace remainders 10 through 15 with the corresponding hexadecimal digits A through F. Then we write the sequence as before and the equivalent number in the new base is the string of remainders recorded.

Example-2.6.26: Converts (937)10 into Hexadecimal LSB 58 3 16 937 16 58 928 48 9 10  (937)10 = (3A9)16

Dlogic102-num1

MSB 0 16 3 0 3

Shorthand Method  937 ÷ 16 = 58 R 9 LSD  58 ÷ 16 = 3 R 10 (A)  3 ÷ 16 = 0 R 3 MSD

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Converting from base 16 to base 10 proceeds with positional values and the multiplication algorithm explained previously. In this case, the positional values are functions of successive powers of sixteen. After determining the appropriate positional values (be careful as the numbers get large quickly), simply multiply the hexadecimal digits by their corresponding positional values, and then sum the products to obtain the equivalent decimal value.

Example-2.6.27: Convert the number (F3B6)16 into decimal F 3 B 6 Beginning Integers 3 2 1 0 16 16 16 16 Base to positional powers 4096 256 16 1 Multiples of base number 15x4096 3x256 11x16 6x1 Multiply position’s digit by the multiple of the base number 61440 768 176 6 Add products to find base 10 Equivalent = 62390 Then, (F3B6)16 = (62390)10.

Example-2.6.28: Convert the number (F4C)16 into decimal F 4 C Beginning Integers 162 161 160 Base to positional powers 256 16 1 Multiples of base number 15x256 4x16 12x1 Multiply position’s digit by the multiple of the base number 3840 64 12 Add products to find base 10 Equivalent = 3916 Then, (F4C)16 = (3916)10.

Example-2.6.29: Convert the hexadecimal number (C 2 A B)16 into decimal The following equivalent decimal value: (C 2 A B)16 = C x 163 + 2 x 162 + A x 161 + B x 160 = 1210 x 4096 + 2 x 256+1010 x 16+1110 x 1 = (49835)10 The neat thing about hexadecimal and binary is how easy it is to translate one form into the other.

Example-2.6.30: Convert the hexadecimal number (C 2 A B)16 into Binary We can easily convert it to binary by simply replacing each hex digit with the corresponding 4-bit binary equivalent as follows; C = 11002 2 = 00102 A = 10102 B = 10112 Then, the resulting binary value would be (1100 0010 1010 1011)2.

2.6.5 Generalized Conversions This section is concerned with the conversion between Decimal Numbers and Numbers using any other base. Converting from decimal to any other base n begins by dividing the decimal number by n. This modulo division yields both a new quotient and an integer remainder in

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the range of [0, n – 1]. Continue dividing each new quotient by n until your quotient equals zero. The corresponding remainder will be the most significant digit of the equivalent base n number. As before, write the digits in right to left sequence beginning with the first remainder obtained and the resulting number is the base n equivalent.

Example-2.6.31: Using n = 7, convert (347)10 into its base seven counterpart, Quotient Remainder 347 ÷ 7 = 49 49 x 7 = 343, 347 - 343 = 4 49 ÷ 7 = 7 7 x 7 = 49, 49 – 49 = 0 7÷7=1 1 x 7 = 7, 7-7=0 1÷7=0 0 x 7 = 0, 1–0= 1

Remainders

 (347)10 = (1004)7. Converting from any other base n to base 10 begins by determining the positional values for each digit in the base n number. As always, these values can be expressed as successive powers of n beginning with zero. We then multiply each base n digit by its corresponding positional value and sum these products. The final sum is the base ten equivalent value. Next, multiply each integer in each position by the base number taken to the correct power for the specific position.

Example-2.6.32: Convert the number (24213)5 into decimal 2 4 2 54 53 52 625 125 25 2x625 4x125 2x25 1250 500 50 Then, (24213)5 = (1808)10.

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1 51 5 1x5 5

3 50 1 3x1 3

Beginning Base 5 Digits Base 5 positional powers Base 5 positional values Multiply row 1 digits by their associated positional values

Add products to find base 10 equivalent number 1808

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2.7 Numbers' Arithmetic  Binary addition rules: 0 + 0 = 0 , 0 + 1 = 1 , 1 + 0 = 1 , 1 + 1 = 0 with a carry of 1  Hexadecimal addition rule: Let Nb denote a number N converted to base b. If X and Y are two hexadecimal digits and X10 + Y10 = Z  16 then X + Y = (Z - 16)16 with a carry of 1; otherwise X + Y = Z16  Binary subtraction: A borrow of 1 is worth 2 in decimal.  Hexadecimal subtraction: A borrow of 1 is worth 16 in decimal.

2.7.1 Binary Addition The rules for binary addition are Logic Sum carry 0+0= 0 0 0 0+1= 1 1 0 1+0= 1 1 0 1 + 1 = 10 0 1

+ 0 1

0 0 1

1 1 10

The entry for 1+1 is 10 which indicates a carry of 1

When an input carry = 1 due to a previous result, the rules are;

Cin 1 1 1 1

Addition Logic Sum 1+0+0= 1 1 1 + 0 + 1 = 10 0 1 + 1 + 0 = 10 0 1 + 1 + 1 = 11 1

Multiplication Logic Result 0x0= 0 0 0x1= 0 0 1x0= 0 0 1x1= 1 1

carry 0 1 1 1

Example-2.7.1 Add the binary numbers 00111 and 10101 and show the equivalent decimal addition. Solution: 0111

+

00111 10101 11100

+ =

7 21 28

2.7.2 Binary Subtraction The rules for binary subtraction are Logic Subtract Borrow 0-0= 0 0 0 0 - 1 = 11 1 1 1-0= 1 1 0 1-1= 0 0 0

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Binary Subtraction: Uses the same principle of "borrowing" that decimal subtraction uses; 0 1  0 0 1 (with a borrow from the next column) 1 1 0 Binary Subtraction Table

Example-2.7.2 Subtract the binary number 00111 from 10101 and show the equivalent decimal subtraction. Solution: 111

-

10101 00111 01110

=

21 7 14

2.7.3 Signed Binary Numbers There are several ways to represent signed binary numbers, in all cases, the MSB in a signed number is the sign bit that tells you if the number is positive or negative. Using the signed number notation with negative numbers in 2’s complement form simplifies addition and subtraction of signed numbers. Rules for addition: Add the two signed numbers, discard any final carries and the result is in signed form. The popular scheme used to represent integers is called sign and magnitude representation. In this scheme, the most significant bit is reserved to represent the sign of the integer and the remaining bits used to represent its magnitude. Accordingly, the MSB is referred to as the sign bit; e.g. with eight bits we may represent +127 = 01111111 - 127 = 11111111 Computers store binary numbers in what is called signed magnitude notation, where the most significant (leftmost) binary digit is used to represent the +/- sign. The downside of this action is that the magnitude (or range) of possible numbers a computer word can hold is cut in half. But the upside means that both positive and negative numbers can be stored. For example, an 8-bit word can represent numbers from 20-1(0) to 28-1(255) or 256 different values. If we use the leftmost bit to be the sign bit, we can only store seven numeric bits of data and thus the maximum range of numbers has been cut in half [20-1(0) to 27-1(127) or 128 different values]. Note that the ranges vary with the number of bits allocated to data storage. In modern computers, 64 bits are often used to store numbers and consequently in signed magnitude notation, the integer interval of permissible values would be [ - 263 – 1, + 263 – 1].

Example-2.7.3: 8-bit Word Using unsigned magnitude: Using Signed Magnitude:

1 0 1 1 28 … ± 27 …

0

0

0 1 2 1 20 21 20

Always, in signed magnitude notation, a zero in the sign bit represents a positive number and a one represents a negative number. This is purely by convention but without an agreed upon standard, computers would have difficulty communicating with each other.

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Example-2.7.4: Represents +1 -1 +75 -75 +127 -127

0 1 0 1 0 1

0 0 1 1 1 1

0 0 0 0 1 1

Data Word 0 0 0 0 0 0 0 1 0 0 1 0 1 1 1 1 1 1

0 0 1 1 1 1

1 1 1 1 1 1

So far, we’ve looked at binary numbers that might be stored in an 8-bit register. Computers could have a 16-bit register enabling the storage of a larger range of numbers. C++ handles a range of integers from –32,767 to +32,767 (215 – 1). This requires a 16-bit register, storing the sign bit in the 16th bit. Actually, registers can be as large (or as small) as the designers wish them to be, but typically, the sizes are 8-, 16-, 32- or 64-bits.

Example-2.7.5: Represents +32767: Represents -32767:

Data Word 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Complementary Arithmetic Complements are often used to represent negative numbers and enable both addition and subtraction operations. Computers can add much faster than they can subtract, so a method called complementary arithmetic was devised to enable computers to subtract by adding. The term complement refers to that which must be added to make something else complete. We have already encountered complementary sets which, when joined together in union produce a complete set or universe. Numbers have complements, but to determine them, we must define what our “whole” is to be. For example, if when we add a number and its complement together, we produce a sum in which all the digits are sevens, we might refer to a “7’s complement. That is, the 7’s complement of 214 is 563. When we add 214 + 563, the sum is 777. This seems like a ho-hum concept since there doesn’t appear to be any worthwhile purpose to computing 7’s complements. But in the decimal number system, there are two complements that are of particular value. These are the 9’s complement and the 10’s complement.

9’s and 10’s Complement As you may have surmised by now, the 9’s complement of a number is that number which, when added to the first number, produces a sum in which all the digits are nines. Nine is a mathematically interesting number. Did you know that any number that is a multiple of nine will, when you sum its digits, either produce nine directly or a multiple of nine. Consider the initial sequence of 9, 18, 27, 36, 45, 54, 63, 72, 81, and 90. Observe that the sum of the digits is nine. Continuing with the sequence: 99, 108, 117, 126, 135, 144,… produces either digits which still sum to nine or, as in the case of 99, a sum that is a multiple of nine and whose digits also add up to nine. Even the outlandish case where we multiply 73384542 by 54 (a multiple of nine) to obtain 3,962,765,268; notice that the digits sum to 54 which in turn, sums to nine. Accountants took advantage of the unique properties of the number 9 to determine the likelihood of error when quickly checking summations depicted in business ledgers. The technique was called casting out nines. The 10’s complement of a number can be

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obtained quite easily by simply adding 1 to the 9’s complement of that same number. The 10’s complement is so named because the sum of any number and its 10’s complement yields a number that is a power of ten (our base in the decimal system in case that subtlety slipped your mind.)

Example-2.7.6: Determine both 9’s and 10’s complements for (633) 10 Begin with the decimal number, 633: What number can be added to make 999? Add 1 to the 9’s complement to get the 10’s complement:

Added to 999, we get 1,000 (a power of 10)

633 + 366 999 367 + 999 1000

 9’s Complement  10’s Complement

Since you are most familiar with the decimal number system, the question might arise if you can perform subtraction via addition using the complementation technique. The answer is yes, but with the decimal number system you use a nine’s complement. The nine’s complement of a number is found by subtracting the number from a number that consists of all 9’s. Forming the 9’s complement  Given 36510 , it’s nine’s complement is: 999 – 365 = 63410  Given 3410 , it’s nine’s complement is: 99 – 34 = 6510

Example-2.7.7: Subtraction by Addition Subtract 633 from 840. The answer is 207. Instead of subtracting 633 from 840, suppose we compute the 10’s complement of 633 (recall that this was 367) and add this number to the 840. The sum is 1207 and if we ignore the “overflow” number in the thousand’s position, we have the same answer: 207.

840

840 - 633 + 367 207 1 207 Overflow 842 - 365 477

 10’s Complement of 633

Using 9’s complement:

842 + 634 1 476 + 1 (477)

End-around-carry Answer in base 10

When the larger number is subtracted from the smaller number, no end-around carry will result, but the answer will be in nine’s complement form and of the opposite sign as follows:

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Example-2.7.8: 152

Using 9’s complement:

- 290 - 138

152 + 709 861

No carry is produced so the answer is in 9’s complement form and of the opposite sign. So the answer is: 999 - 861 - 138

Signed Magnitude There are several alternative conventions that can be used to represent negative (as well as positive) integers, all of which involve treating the MSB as a sign bit. Typically, if the MSB is 0, the number is positive; if the MSB is 1, the number is negative. The simplest form of representation that employs a sign bit is the sign-magnitude representation. In an n-bit word, the right-most n-1 bits represent the magnitude of the integer, and the left-most bit represents the sign of the integer. For example, in an 8-bit word the value of +2410 is represented by: 000110002, while the value of –2410 is represented by 100110002. There are several disadvantages to sign magnitude representation. One is that addition and subtraction operations require a consideration of both the signs of the numbers and their relative magnitudes to carry out the required operation. Another disadvantage is that there are two representations of 0. Using an 8-bit word, both 000000002 and 100000002 represent 0 (the first +0, the latter –0). This makes logical testing for equality on 0 more complex (two values need to be tested). Because of these disadvantages, sign-magnitude representation is rarely used in implementing the integer portion of the ALU.

1’s Complement The 1’s complement of a binary number is just the inverse of the digits. That is, to form the 1’s complement, change all 0’s to 1’s and all 1’s to 0’s.

Example-2.7.9 The 1’s complement of 11001010 is 00110101 In digital circuits, the 1’s complement is formed by using inverters as:

2’s Complement Like sign-magnitude, two’s complement uses the MSB as a sign bit, thus making it easy to test if an integer is positive or negative. Two’s complement differs from sign-magnitude in the way the remaining n-1 bits (of an n-bit word) are interpreted. Two’s complement representation has only a single representation for the value of 0. The two's complement of a binary number is found by subtracting each bit of the number from 1 (1's complement) and adding 1. That is, the 2’s complement of a binary number is found by adding 1 to the LSB of the 1’s complement.

Arithmetic Operations with Signed Numbers Rules for subtraction: 2’s complement the subtrahend and add the numbers, discard any final carries and the result is in signed form. Note that if the number of bits required for the answer is exceeded,

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overflow will occur. This occurs only if both numbers have the same sign. The overflow will be indicated by an incorrect sign bit.

Recall that the 1’s complement of 11001010 is (00110101)1s

To form the 2’s complement, add 1:

Computers use a modified 2’s complement for signed numbers. Positive numbers are stored in true form (with a 0 for the sign bit) and negative numbers are stored in complement form (with a 1 for the sign bit).

Example-2.7.10 The positive number 58 is written using 8-bits as 00111010 (true form). Assuming that the sign bit = −128, show that 11000110 = −58 as a 2’s complement signed number: 1 1 0 0 0 1 1 0 Column weights: −128 64 32 16 8 4 2 1  −128 +64 +4 +2 = −58 Negative numbers are written as the 2’s complement of the corresponding positive number; −58 = 11000110 (complement form) An easy way to read a signed number that uses this notation is to assign the sign bit a column weight of −128 (for an 8-bit number). Then add the column weights for the 1’s.

Example-2.7.11 Represent -19 in two’s complement, start with positive 19: 00000000 00000000 00000000 000100112 Then flip all 0s to 1s and all 1s to 0s (this is called the one's complement): 11111111 11111111 11111111 111011002 (one’s complement) Then add a 1 to the flipped values: 11111111 11111111 11111111 11101100 00000000 00000000 00000000 00000001 11111111 11111111 11111111 11101101

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(one’s complement) (a binary 1) (two’s complement form of -1910)

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Example-2.7.12 Using 2’s complement arithmetic, Decimal 11 in binary is: 1’s complement of 11 is: 2’s complement of 11 is: Add the binary 18 Sum of the numbers: The answer is:

find (18 – 11) 00001011 11110100 11110101 + 00010010 1 00000111 18 - 11 = 7

Carry of 1 is ignored Decimal 7 = 111 in binary

Example-2.7.13 Perform the following subtraction: 15 - 9 = 6 Instead of performing a subtraction, we would instead add a negative value: 15 + (-9) = 6 First, let’s find the two’s complement of 9: 00000000 00000000 00000000 00001001 11111111 11111111 11111111 11110110 00000000 00000000 00000000 00000001 11111111 11111111 11111111 11110111

(positive 9) (one’s complement) (add 1) (negative 9)

Now, let’s add the two values 15 and -9: 00000000 00000000 00000000 00001111 11111111 11111111 11111111 11110111 00000000 00000000 00000000 00000110

(15) (-9) (6)

We have added 15 and -9 and our result is 6, as shown above.

Example-2.7.14 111 - 101 (binary representation of (5)10) 010 + 1 “011” (two's complement of (5)10) [note the leading 0 is important] Thus 011 is the twos complement of 101 or the representation of –5.

Example-2.7.15 10 – 6 = 4 in base 10 1010  110 = 100 in base 2 The two’s complement of 6 is 1010 over four bits 1010 + 1010 = 10100 since we are working with 4 bit numbers the MSB is discarded and we are left with 0100 where the MSB is 0 leaving a value of 100 which is binary representation of (4)10. An alternate way of performing a two’s complementation (does exactly the same thing the addition does without thinking about doing the subtraction and the addition) is as follows: beginning with the LSB and progressing toward the MSB, leave all 0 bits unchanged and the first 1 bit unchanged, after encountering the first 1 bit, complement all remaining bits until the

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MSB has been processed. The resulting number is the two’s complement of the original number.

Example-2.7.16: Consider the number 111002 (this is 2810) The two’s complement is: 001002 achieved by: MSB LSB 1 1 1 0 0 original number 0 0 1 0 0 two’s complement form unchanged complemented Note that we get the same answer if we use the original technique. 1 - 1 0 + 0

1 1 1 1 1 0 0 0 1 0 0 0

0 0

1

0

1 0 1 1 0

Operations with Negative Numbers Assuming that all negative numbers are represented in two’s complement form, the question then becomes, how do we know that you are dealing with a negative number when a result is produced.

Example-2.7.17: Suppose we have the expression 10 + (-8), with radix 10 numbers. Using five-bit numbers 1010 is represented as 010102, and 810 is represented as 010002. The two’s complement of 010002 is 110002. Performing the addition yields: Carry

1 1

+

01010 11000 100010

Note that a carry has occurred out of the MSB. In this case we are using 5-bit numbers, so the carry out of the MSB is simply ignored, and the correct answer of 2 10 has been calculated. What would have happened if we had been using 4-bit numbers instead of 5-bit numbers? Well, using 4-bit numbers the two’s complement of 10002 (this is 810) is exactly the same as the non-complemented form. Thus, the two’s complement of 10002 using four-bit numbers is also 10002. This means that you cannot tell the difference between +810 and –810 in four-bit binary words. This is explained in more detail later when we discuss overflow conditions (as a hint: notice in the example that both the addend and the augend have the same sign but the result (in four-bits) has a different sign).

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Carry

48

1 1

+

1010 1000 10010

The bit carried out of the MSB position, reflects that two number of the same sign were added together, yet the result has a different sign. This is reflects an overflow condition.

Example-2.7.18: Suppose we have the expression 4 + (-8), with radix 10 numbers. Using 5-bit numbers, 410 is represented as 001002, and 810 is represented as 010002. The two’s complement of 010002 is 110002. Performing the addition yields: Carry

+

00100 11000 11100

Note that no carry has occurred out of the MSB. Since a two’s complement number was involved in the addition and no carry out of the MSB position occurred and the addend and augend are of different signs, this means that the result is valid and is in two’s complement form and thus represents a negative number. To determine what number this is you must uncomplement the result. The uncomplemented form is determined by complementing every bit (in a right to left pass through the two’s complement number) after the least significant 1 bit. In this case, the uncomplemented form will be (in five-bit form) 001002 which is 410, so the answer represents –410 which is the correct answer.

Two’s Complement Motivation Two’s complement arithmetic allows you to perform addition operations when subtraction is the actual desired operation. This means that any expression of the form: (A – B) can be computed as (A + BC) where (BC) represents the two’s complement form of B. This fact allows the Airthmetic Logic Unit (ALU) inside the CPU to be more compact since circuitry for subtraction is not included. Although it may seem that with two’s complement we have found nirvana as far as representing negative numbers inside a computer is concerned, we unfortunately, have not. For any addition operation, the result may be larger than can be held in the word size of the system. This condition is called overflow. When an overflow occurs, the arithmetic logic unit (ALU) must signal the control unit (within the CPU) that an overflow condition exists and no attempt be made to use the invalid result. To detect overflow, the following rule must be observed: If two numbers are added, and they are both positive or both negative, then overflow occurs if and only if the result has the opposite sign of the operands to the addition. Note that overflow can occur whether or not there is a carry out of the MSB position. The following example illustrates an overflow condition.

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Example-2.7.19: Let A = 710 and B = -710. Then the difference (A – B) (in radix 10) is: 7 – (-7) = 7 + 7 = 14. In binary the value of B will be represented in two’s complement form as: 710 = 01112, -710 = 10012 since it is a negative number. But since this is a subtraction problem we convert (the subtrahend) to its two’s complement form and perform an addition operation. The two’s complement of 10012 (which represents –710) is 01112 The problem then becomes: 0111 + 0111 = 1110 Since the MSB is different in sign than A and B an overflow has occurred.

2.7.4 Octal Arithmetic Octal Addition Table + 0 1 2

3

4

5

6

7

0

0

1

2

3

4

5

6

7

1

1

2

3

4

5

6

7

10

2

2

3

4

5

6

7

10

11

3

3

4

5

6

7

10

11

12

4

4

5

6

7

10

11

12

13

5

5

6

7

10

11

12

13

14

6

6

7

10

11

12

13

14

15

7

7

10

11

12

13

14

15

16

Example-2.7.20 Carry Addend Augend Sum

127 + 42

1 127 + 42 1

127 + 42 71

1 1777 + 777 6

11 1777 + 777 76

+

127 42 171

Example-2.7.21 Carry Addend Augend Sum

1777 + 777

+

111 1777 777 776

1777 + 777 2776

Octal Subtraction This is performed exactly like binary and decimal subtraction with the borrowing technique. Whenever the subtrahend is larger than the minuend, a 1 is borrowed from the next column.

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Example-2.7.22 Borrow Minuend Subtrahend Difference

124 63

-

124 63 1

-

1 124 63 41

2.7.5 Hexadecimal Arithmetic Hexadecimal Addition + 0 1 2 3

0 00 01 02 03

1 01 02 03 04

2 02 03 04 05

3 03 04 05 06

4 04 05 06 07

5 05 06 07 08

6 06 07 08 09

7 07 08 09 0A

8 08 09 0A 0B

9 09 0A 0B 0C

A 0A 0B 0C 0D

B 0B 0C 0D 0E

C 0C 0D 0E 0F

D 0D 0E 0F 10

E 0E 0F 10 11

F 0F 10 11 12

4 5 6 7 8 9 A B C D E F

04 05 06 07 08 09 0A 0B 0C 0D 0E 0F

05 06 07 08 09 0A 0B 0C 0D 0E 0F 10

06 07 08 09 0A 0B 0C 0D 0E 0F 10 11

07 08 09 0A 0B 0C 0D 0E 0F 10 11 12

08 09 0A 0B 0C 0D 0E 0F 10 11 12 13

09 0A 0B 0C 0D 0E 0F 10 11 12 13 14

0A 0B 0C 0D 0E 0F 10 11 12 13 14 15

0B 0C 0D 0E 0F 10 11 12 13 14 15 16

0C 0D 0E 0F 10 11 12 13 14 15 16 17

0D 0E 0F 10 11 12 13 14 15 16 17 18

0E 0F 10 11 12 13 14 15 16 17 18 19

0F 10 11 12 13 14 15 16 17 18 19 1A

10 11 12 13 14 15 16 17 18 19 1A 1B

11 12 13 14 15 16 17 18 19 1A 1B 1C

12 13 14 15 16 17 18 19 1A 1B 1C 1D

13 14 15 16 17 18 19 1A 1B 1C 1D 1E

Hexadecimal Addition Table

Example-2.7.23 Carry Addend Augend Sum

3B2 + 41C E

3B2 + 41C CE

3B2 + 41C 7CE

Example-2.7.24 Carry Addend Augend Sum

+

1 A27 C3B 2

A27 C3B +

01 A27 C3B 62

+

+

101 A27 C3B 662

101 A27 + C3B 1 662

Hexadecimal Subtraction Uses the same principle of "borrowing" that is used with decimal and binary subtraction.

Example-2.7.25 Borrow Minuend Subtrahend Difference

Dlogic102-num1

6E 29

-

6E 29 5

-

6E 29 45

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Example-2.7.26 Borrow Minuend Subtrahend Difference

AC3 604

-

1 AC3 604 F

-

1 AC3 604 BF

-

1 AC3 604 4BF

Floating Point Representation of Real Numbers A Real number, when represented within the computer, has three parts: • Sign bit • Exponent (Abscissa) • Mantissa (Significand or Fraction) To represent a real number using single precision 4 bytes are used, i.e. 4*8=32 bits. The structure of a Real number is as illustrated in Fig. 2.8. However for the IEEE16 standard, the mantissa is composed of 24 bits as indicated in the following table; Part Number of bits Mantissa 23 Exponent 8 Sign 1

Fig. 2.8: Arrangement of typical single precision Real number

Simple arithmetic indicates that it would take 33 bits to store a 4-byte single precision number but we are only using 32. Although the mantissa is quoted as 24 bits only 23 bits are used. Normalization allows us to discard the single ‘1’ bit to the left of the radix point (i.e. binary point for base 2). To illustrate, let us convert the decimal number 12 to binary and then normalize: (12)10 = (1100)2 Normalizing (1100)2 becomes (1.1x23)2 Notice that as a result of the normalization all numbers will be written as 1.?????x2? and as a result the integer part does not have to be stored. The bits after the radix point are the only digits that are stored. Another alteration can be made to the Real number representation in which the exponent is stored as a Biased Exponent where a bias of +127 is added to the exponent. Let us look at a few examples of how Real numbers are represented: +12 (decimal) Normalizing the mantissa we get +1.1x23 Sign = 0 (+ve) Exponent = 3+127 = 130 Mantissa = .1 Therefore the representation of +12 is:

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Similarly, for –12 we get:

To represent a real number using single precision 8 bytes are used, i.e. 8*8=64 bits. The structure of a Real number is as illustrated in Fig. 2.9.

Fig. 2.9: Arrangement of typical double precision Real number With double precision the bias for the exponent is 1023. There are 2 exceptions to the rules for floating point numbers (whether single or double precision): • The number 0.0is stored as all zeros • The number infinity is stored as all ones in the exponent and all zeros in the mantissa. The sign bit indicates (+ /-) 0.0 or (+/-) infinity.

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2.8 Binary Multiplication and Division 2.8.1 Binary Multiplication The four basic rules for multiplying bits are summarized as follows: 0*0=0 0*1=0 1*0=0 1*1=1 Multiplication is performed with binary numbers in the same manner as with decimal numbers. It involves forming partial products, shifting each successive partial product left one place, and then adding all the partial products. This procedure is illustrated in the next Examples; where the equivalent decimal multiplications are shown for reference.

Example-2.8.1 Perform the following binary multiplications: (a) 11 * 11 (b) 101 * 111 Solution (a)

(b)

Example-2.8.2

 Multiply 1101 * 1010  Find the multiplication of 1310 by 1110 in binary. Solution (a) (b) 1101 x 1010 0000 1101 0000 1101

Note that each partial product is either the multiplicand (1101) shifted over the appropriate number of places or is zero.

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2.8.2 Binary Division Division in binary follows the same procedure as division in decimal, as illustrated in the next Examples, where the equivalent decimal divisions are also given.

Example-2.8.3 Perform the following binary divisions: (a) 110 , 11 (b) 110 , 10 Solution: (a)

(b)

Example-2.8.4

 Perform the following binary divisions: Divide 1100 by 100  Find the division of 14510 by 1110 in binary. Solution:

The quotient is 1101 with a remainder of 10. Binary division is similar to decimal division, except it is much easier because the only two possible quotient digits are 0 and 1. In the above example, if we start by comparing the divisor (1011) with the upper four bits of the dividend (1001), we find that we cannot subtract without a negative result, so we move the divisor one place to the right and try again. This time we can subtract 1011 from 10010 to give 111 as a result, so we put the first quotient bit of 1 above 10010. We then bring down the next dividend bit (0) to get 1110 and shift the divisor right. We then subtract 1011 from 1110 to get 11, so the second quotient bit is 1. When we bring down the next dividend bit, the result is 110, and we cannot subtract the shifted divisor, so the third quotient bit is 0. We then bring down the last dividend bit and subtract 1011 from 1101 to get a final remainder of 10, and the last quotient bit is 1.

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2.9 Codes 2.9.1 Numerical (Binary) Codes Concerning coding, when numbers, letters or words are represented by a specific group of symbols, it is said that the number, letter or word is being encoded. The group of symbols is called as a code. The digital data is represented, stored and transmitted as group of binary bits (binary code). The binary code is represented by the number as well as alphanumeric letter.

Advantages of Binary Codes Some of the advantages that binary code offers can be summarized as,  Binary codes are suitable for the computer applications.  Binary codes are suitable for the digital communications.  Binary codes make the analysis and designing of digital circuits if we use the binary codes.  Since only 0 & 1 are being used, implementation becomes easy.

Classifications of Binary Codes The codes are broadly categorized into following categories;  Weighted Codes  Non-Weighted Codes  Binary Coded Decimal (BCD) Code  Alphanumeric Codes  Error Detecting Codes  Error Correcting Codes

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2.9.2 Binary-Coded Decimal (BCD) Weighted Codes Weighted binary codes are those binary codes which obey the positional weight principle. Each position of the number represents a specific weight. Several systems of the codes are used to express the decimal digits 0 through 9. In these codes each decimal digit is represented by a group of four bits as shown in Fig. 2.9.1.

Fig. 2.9.1

Binary Coded Decimal (BCD) code In this code each decimal digit is represented by a 4-bit binary number. BCD is a way to express each of the decimal digits with a binary code. In the BCD, with four bits we can represent sixteen numbers (0000 to 1111). But in BCD code only first ten of these are used (0000 to 1001). The remaining six code combinations i.e. 1010 to 1111 are invalid in BCD. Decimal 0 1 2 3 4 5 6 7 8 9 BCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001

Advantages of BCD Codes  It is very similar to decimal system.  We need to remember binary equivalent of decimal numbers 0 to 9 only.

Disadvantages of BCD Codes  The addition and subtraction of BCD have different rules.  The BCD arithmetic is little more complicated.

BCD needs more number of bits than binary to represent the decimal number. So BCD is less efficient than binary. Nowadays, real applications are full of embedded systems, the main constituents of which are microprocessors/microcontrollers that are integrated circuits designed for data processing and control. Computers and microprocessors/microcontrollers both operate on a series of electrical pulses called words. A word can be represented by a binary number such as 101100112. The word length is described by the number of digits or BITS in the series. A series of four digits would be called a 4-bit word and so forth; the most common are 4-, 8-, and 16-bit words. Quite often, these words must use BCD inputs which is a method of using binary digits to represent the decimal digits 0 through 9.

Dec 0 1 2 3 4 5 6 7 8 9

8 0 0 0 0 0 0 0 0 1 1

BCD 4 2 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0

1 0 1 0 1 0 1 0 1 0 1

BCD is a weighted code that is commonly used in digital systems when it is necessary to show decimal numbers such as in clock displays. The truth table illustrates the difference between straight binary and BCD; the BCD represents each decimal digit with a 4-bit code where the codes 1010 through 1111 are not used. BCD can be though of in terms of column weights in groups of four bits. For an 8-bit BCD number, the column weights are: 80 40 20 10 8 4 2 1.

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What are the column weights for the BCD number 1000 0011 0101 1001? 8000 4000 2000 1000 800 400 200 100 80 40 20 10 8 4 2 1 Note that you could add the column weights where there is a 1 to obtain the decimal number. For this case: 8000 + 200 +100 + 40 + 10 + 8 +1 = 835910 Note that BCD and binary are not the same; For example, 4910 in binary is 1100012, but 4910 in BCD is (0100 1001)BCD, where each decimal digit is converted to its binary equivalent. In computing and electronic systems, binary-coded decimal (BCD) is a digital encoding method for numbers using decimal notation, with each decimal digit represented by its own binary sequence. In BCD, a numeral is usually represented by four bits which, in general, represent the decimal range 0 through 9. Other bit patterns are sometimes used for a sign or for other indications (e.g., error or overflow). Uncompressed (or zoned) BCD consumes a byte for each represented numeral, whereas compressed (or packed) BCD typically carries two numerals in a single byte by taking advantage of the fact that four bits will represent the full numeral range. BCD's main virtue is ease of conversion between machine- and human-readable formats, well as a more precise machine-format representation of decimal quantities. As compared typical binary formats, BCD's principal drawbacks are a small increase in the complexity the circuits needed to implement basic mathematical operations and less efficient usage storage facilities.

as to of of

BCD was used in many early decimal computers. Although BCD is not as widely used as in the past, decimal fixed-point and floating-point formats are still important and continue to be used in financial, commercial, and industrial computing, where subtle conversion and rounding errors that are inherent to floating point binary representations cannot be tolerated.

Basics As most computers store data in 8-bit bytes, it is possible to use one of the following methods to encode a BCD number:  Uncompressed: each numeral is encoded into one byte, with four bits representing the numeral and the remaining bits having no significance.  Packed: two numerals are encoded into a single byte, with one numeral in the least significant nibble (bits 0-3) and the other numeral in the most significant nibble (bits 47). As an example, encoding the decimal number 91 using uncompressed BCD results in the following binary pattern of two bytes: Decimal: 9 1 Binary: 0000 1001 0000 0001

In packed BCD, the same number would fit into a single byte: Decimal: 9 1 Binary: 1001 0001

Hence the numerical range for one uncompressed BCD byte is zero through nine inclusive, whereas the range for one packed BCD is zero through ninety-nine inclusive. To represent numbers larger than the range of a single byte any number of contiguous bytes may be used. For example, to represent the decimal number 12345 in packed BCD, using big-endian format, a program would encode as follows:

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Decimal: Binary :

1 0000 0001

2 3 0010 0011

58

4 5 0100 0101

Note that the most significant nibble of the most significant byte is zero, implying that the number is in actuality (012345). Also note how packed BCD is more efficient in storage usage as compared to uncompressed BCD; encoding the same number in uncompressed format would consume 67 percent more storage. Shifting and masking operations are used to pack or unpack a packed BCD digit. Other logical operations are used to convert a numeral to its equivalent bit pattern or reverse the process.

BCD in Electronics BCD is very common in electronic systems where a numeric value is to be displayed, especially in systems consisting solely of digital logic, and not containing a microprocessor. By utilizing BCD, the manipulation of numerical data for display can be greatly simplified by treating each digit as a separate single sub-circuit. This matches much more closely the physical reality of display hardware; a designer might choose to use a series of separate identical seven-segment displays (Fig. 2.9.2) to build a metering circuit, for example. If the numeric quantity were stored and manipulated as pure binary, interfacing to such a display would require complex circuitry. Therefore, in cases where the calculations are relatively simple working throughout with BCD can lead to a simpler overall system than converting to binary. The same argument applies when hardware of this type uses an embedded microcontroller or other small processor. Often, smaller code results when representing numbers internally in BCD format, since a conversion from or to binary representation can be expensive on such limited processors. For these applications, some small processors feature BCD arithmetic modes, which assist when writing routines that manipulate BCD quantities.

Fig. 2.9.2: 7-Segment Display Pin layout

0 1 2

Inputs (BCD code) D C B A 0 0 0 0 0 0 0 1 0 0 1 0

a 1 0

b 1 1

1

1

0

1

1

0

1

3

0

0

1

1

1

1

1

1

0

0

1

4

0

1

0

0

0

1

1

0

0

1

1

5

0

1

0

1

1

0

1

1

0

1

1

6

0

1

1

0

0

0

1

1

1

1

1

7

0

1

1

1

1

1

1

0

0

0

0

8

1

0

0

0

1

1

1

1

1

1

1

9

1

0

0

1

1

1

1

0

0

1

1

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Outputs (7-segments) c d e f 1 1 1 1 1 0 0 0

Numbers Systems and Codes

Display g 0 0

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Packed BCD A common variation of the two-digits-per-byte encoding is called packed BCD (or simply packed decimal), which has been in use since the 1960s or earlier and implemented in all IBM mainframe hardware since then. In most representations, one or more bytes hold a decimal integer, where each of the two nibbles of each byte represent a decimal digit, with the more significant digit in the upper half of each byte, and with leftmost byte (residing at the lowest memory address) containing the most significant digits of the packed decimal value. The lower nibble of the rightmost byte is usually used as the sign flag (although in some representations this nibble may be used as the least significant digit if the packed decimal value does not have a sign at all, i.e., is purely unsigned). As an example, a 4-byte value consists of 8 nibbles, wherein the upper 7 nibbles store the digits of a 7-digit decimal value and the lowest nibble indicates the sign of the decimal integer value. BCD Sign Digit Sign Notes Standard sign values are 1100 (hex C) for positive 8421 (+) and 1101 (D) for negative (−). This convention A 1010 + was derived from abbreviations for accounting B 1011 − terms (Credit and Debit), as packed decimal coding C 1100 Preferred + was widely used in accounting systems. Other D 1101 Preferred − allowed signs are 1010 (A) and 1110 (E) for E 1110 + positive and 1011 (B) for negative. Some F 1111 Unsigned + implementations also provide unsigned BCD values with a sign nibble of 1111 (F). ILE RPG uses 1111 (F) for positive and 1101 (D) for negative. In packed BCD, the number 127 is represented by 0001 0010 0111 1100 (127C) and −127 is represented by 0001 0010 0111 1101 (127D). Burroughs systems used 1101 (D) for negative and any other value was considered a positive sign value (the processors would normalize a positive sign to 1100 (C)). No matter how many bytes wide a word is, there is always an even number of nibbles because each byte has two of them. Therefore, a word of n bytes can contain up to (2n)−1 decimal digits, which is always an odd number of digits. A decimal number with d digits requires ½(d+1) bytes of storage space. For example, a 4-byte (32-bit) word can hold seven decimal digits plus a sign, and can represent values ranging from ±9,999,999. Thus the number −1,234,567 is 7 digits wide and is encoded as: 0001 0010 0011 0100 0101 0110 0111 1101 1 2 3 4 5 6 7 −

(Note that, like character strings, the first byte of the packed decimal, with the most significant two digits, is usually stored in the lowest address in memory, independent of the endianness of the machine.) In contrast, a 4-byte binary two's complement integer can represent values from −2,147,483,648 to +2,147,483,647.

BCD Conversion Using the above table, conversion of decimal to BCD or BCD to decimal is similar to the conversion of hexadecimal to binary and vice versa.

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Example-2.9.1 Convert the decimal number 26410 into BCD First, write out the decimal number to be converted; then, below each digit write the BCD equivalent of that digit:

The BCD equivalent of (264)10 is (001001100100)BCD. To convert from BCD into decimal, simply reverse the process as shown:

BCD Addition The procedures followed in adding BCD are the same as those used in binary. There is, however, the possibility that addition of BCD values will result in invalid totals. It is possible to perform addition in BCD by first adding in binary, and then converting to BCD afterwards. Conversion of the simple sum of two digits can be done by adding 6 (that is, 16 – 10) when the result has a value greater than 9.

Example-2.9.2: 1001 + 1000 = 10001 = 0001 0001 9 + 8 = 17 = 1 1

In BCD, there cannot exist a value greater than 9 (1001) per nibble. To correct this, 6 (0110) is added to that sum to get the correct first two digits: 0001 0001 + 0000 0110 = 0001 0111 1 1 + 0 6 = 1 7

which gives two nibbles, 0001 and 0111, which correspond to the digits "1" and "7". This yields "17" in BCD, which is the correct result. This technique can be extended to adding multiple digits, by adding in groups from right to left, propagating the second digit as a carry, always comparing the 5-bit result of each digit-pair sum to 9.

Example-2.9.3: Add 9 and 6 in BCD The sum 11112 is the binary equivalent of 1510; however, 1111 is not a valid BCD number. You cannot exceed 1001 in BCD, so a correction factor must be made. To do this, you add 6 10 (0110BCD) to the sum of the two numbers. The "add 6" correction factor is added to any BCD group larger than 10012. Remember, there is no 10102, 10112, 11002, 11012, 11102, or 11112 in BCD: The sum plus the add 6 correction factor can then be converted back to decimal to check the answer. Put any carries that were developed in the add 6 process into a new 4-bit word:

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Now observe the addition of 6010 and 5510 in BCD: In this case, the higher order group is invalid, but the lower order group is valid. Therefore, the correction factor is added only to the higher order group as shown:

Convert this total to decimal to check your answer: Remember that the correction factor is added only to groups that exceed 9 10 (1001BCD). Convert the following numbers to BCD and add:

BCD Subtraction Subtraction is done by adding the ten's complement of the subtrahend. To represent the sign of a number in BCD, the number 0000 is used to represent a positive number, and 1001 is used to represent a negative number. The remaining 14 combinations are invalid signs. To illustrate signed BCD subtraction, consider the following problem: 357 − 432. In signed BCD, 357 is 0000 0011 0101 0111. The ten's complement of 432 can be obtained by taking the nine's complement of 432, and then adding one. So, 999 − 432 = 567, and 567 + 1 = 568. By preceding 568 in BCD by the negative sign code, the number −432 can be represented. So, −432 in signed BCD is 1001 0101 0110 1000. Now that both numbers are represented in signed BCD, they can be added together: 0000 0011 0101 0111 + 1001 0101 0110 1000 = 1001 1000 1011 1111 0 3 5 7 + 9 5 6 8 = 9 8 11 15

Since BCD is a form of decimal representation, several of the digit sums above are invalid. In the event that an invalid entry (any BCD digit greater than 1001) exists, 6 is added to generate a carry bit and cause the sum to become a valid entry. The reason for adding 6 is that there are 16 possible 4-bit BCD values (since 24 = 16), but only 10 values are valid (0000 through 1001). So adding 6 to the invalid entries results in the following: 1001 1000 1011 1111 + 0000 0000 0110 0110 = 1001 1001 0010 0101 9 8 11 15 + 0 0 6 6 = 9 9 2 5

Thus, the result of the subtraction is 1001 1001 0010 0101 (-925). To check the answer, note that the first bit is the sign bit which is negative. This seems to be correct, since 357 − 432 should result in a negative number. To check the rest of the digits, represent them in decimal. 1001 0010 0101 is 925. The ten's complement of 925 is 1000 − 925 = 999 − 925 + 1 = 074 + 1 = 75, so the calculated answer is −75. To check, perform standard subtraction to verify that 357 − 432 is −75.

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Note that in the event that there are a different number of nibbles being added together (such as 1053 − 122), the number with the fewest number of digits must first be padded with zeros before taking the ten's complement or subtracting. So, with 1053 − 122, 122 would have to first be represented as 0122, and the ten's complement of 0122 would have to be calculated.

Comparison with pure binary Advantages  Many non-integral values, such as decimal 0.2, have an infinite place-value representation in binary (.001100110011...) but have a finite place-value in binary-coded decimal (0.0010). Consequently a system based on binary-coded decimal representations of decimal fractions avoids errors representing and calculating such values.  Scaling by a factor of 10 (or a power of 10) is simple; this is useful when a decimal scaling factor is needed to represent a non-integer quantity (e.g., in financial calculations)  Rounding at a decimal digit boundary is simpler. Addition and subtraction in decimal does not require rounding.  Alignment of two decimal numbers (for example 1.3 + 27.08) is a simple, exact, shift.  Conversion to a character form or for display (e.g. to a text-based format such as XML, or to drive signals for a seven-segment display) is a simple per-digit mapping, and can be done in linear (O(n)) time. Conversion from pure binary involves relatively complex logic that spans digits, and for large numbers no linear-time conversion algorithm is known. Disadvantages  Some operations are more complex to implement. Adders require extra logic to cause them to wrap and generate a carry early. 15–20 percent more circuitry is needed for BCD add compared to pure binary. Multiplication requires the use of algorithms that are somewhat more complex than shift-mask-add (a binary multiplication, requiring binary shifts and adds or the equivalent, per-digit or group of digits is required)  Standard BCD requires four bits per digit, roughly 20 percent more space than a binary encoding (the ratio of 4 bits to log210 bits is 1.204). When packed so that three digits are encoded in ten bits, the storage overhead is greatly reduced, at the expense of an encoding that is unaligned with the 8-bit byte boundaries common on existing hardware, resulting in slower implementations on these systems.  Practical existing implementations of BCD are typically slower than operations on binary representations, especially on embedded systems due to limited processor support for native BCD operations.

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2.9.3 Gray Code

Gray code is an un-weighted code that has a single bit change between one code word and the next in a sequence. Gray code is used to avoid problems in systems where an error can occur if more than one bit changes at a time.

BCD

Gray Code is one of the most important codes and it is a non-weighted code (the positional weights are not assigned) which belongs to a class of codes called minimum change codes. In this code, while traversing from one step to Dec Binary Number Gray Code another step only one bit in the code group 0 0 0 0 0 0 0 0 0 changes. That is, in a Gray Code two adjacent 1 0 0 0 1 0 0 0 1 code numbers differs from each other by only one 2 0 0 1 0 0 0 1 1 3 0 0 1 1 0 0 1 0 bit as can be cleared from the shown table. 4 5 6 7 8 9 10 11 12 13 14 15

0 0 0 0 1 1 1 1 1 1 1 1

1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1

0 0 0 0 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 0 0 0 0

1 1 0 0 0 0 1 1 1 1 0 0

0 1 1 0 0 1 1 0 0 1 1 0

It is the non-weighted code and it is not arithmetic codes. That means there are no specific weights assigned to the bit position. It has a very special feature that, only one bit will change each time the decimal number is incremented as shown in fig. As only one bit changes at a time, the gray code is called as a unit distance code. The gray code is a cyclic code. Gray code cannot be used for arithmetic operation.

Application of Gray Code  Gray code is popularly used in the shaft position encoders.  A shaft position encoder produces a code word which represents the angular position of

the shaft. This code is not applicable in any types of arithmetical operations but it has some applications in analog to digital converters and in some input/output devices. A shaft encoder is a typical application where three IR More than one Only one bit emitter/detectors are used to bit changes changes encode the position of the shaft. The encoder in Fig. 2.9.3a uses binary and can have three bits change together, creating a potential error, while the encoder in Fig. 2.9.3b uses gray code with only 1-bit changes, eliminating potential errors. Fig. 2.9.3: Shaft encoder

The equivalent gray code of the decimal numbers can be obtained via the following steps: 1. In case of gray code one bit will change from its previous in each step. One thing must be kept in mind that the change of bit always occurs from the right side i.e. from LSB towards the MSB. At first the first three bits are constant, i.e. 000 and the fourth bit changes from 0 to 1. We know that for binary digit possible combination is 0 and 1, so

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keeping first three bit constant the possible combination of 4th bit is over for decimal 0 and 1 respectively. 2. Now move to the next bit from LSB i.e. 3rd bit that changes from 0 to 1 which is the decimal equivalent for 2. Now one more combination is left for the fourth bit keeping the first three constant i.e. 001. We can change 4th bit from 1 to 0. Thus the gray code for decimal number 3 is 0010. 3. Traverse to the next code. Here we can do only one thing i.e. we can change the second bit as all possible combinations are over. Question may strike in your mind that why can’t we change the third bit again which will also be a one bit change from its previous. But changing third bit would give the equivalent gray code 0000 which has occurred earlier. So you must remember that a number occurring previously must not be repeated. So the equivalent code for 4 will be 0110. Here only the second bit has changed from the previous code. Now again we will keep first and second bit constant and find the possible combinations of the third and the fourth bit by only changing 1 bit in each steps. Now for 5 only the fourth bit has changed. Again for 6 only the third bit is changed keeping others constant. Lastly at 7 again the fourth bit has changed from 1 to 0 where all other bits are constant. In 8 you can see that the equivalent gray code is 1100. Here the 1 st bit changes from 0 to n1 as all the combination of the 2nd, 3rd and 4th bits are completed keeping the 1st constant at 0. Now in same way the 1st bit is kept constant and all the possible combination changing single bit in each step from right to left is done.

Binary to Gray Code Conversion Binary to gray code conversion is a very simple process. There are several steps to do this type of conversions. Steps given below elaborate on the idea on this type of conversion; • The MSB of the gray code will be exactly equal to the first bit of the given binary number. • Now the second bit of the code will be exclusive-or of the first and second bit of the given binary number, i.e. if both the bits are same the result will be 0 and if they are different the result will be 1. • The third bit of gray code will be equal to the exclusive-or of the second and third bit of the given binary number. Thus the Binary to gray code conversion goes on. One example given below can make your idea clear on this type of conversion: Let (01001) be the given binary number 0 1 0 0 01 10 00     0 1 1 0 Thus the equivalent gray code is 01101.

1 01  1

Binary

Gray

Now concentrate on the example where the MSB of the binary is 0 so for it will be 0 for the most significant gray bit. Next, the XOR of the first and the second bit is done. The bits are different so the resultant gray bit will be 1. Again move to the next step, XOR of second and third bit is again 1 as they are different. Next, XOR of third and fourth bit is 0 as both the bits are same. Lastly the XOR of fourth and fifth bit is 1 as they are different. That is how the result of binary to gray code conversion of 01001 is done whose equivalent gray code is 01101.

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Gray Code to Binary Conversion Gray code to binary conversion is again very simple and easy process. Following steps can make your idea clear on this type of conversions. • The MSB of the binary number will be equal to the MSB of the given gray code. • Now if the second gray bit is 0 the second binary bit will be same as the previous or the first bit. If the gray bit is 1 the second binary bit will alter; if it was 1 it will be 0 and if it was 0 it will be 1. • This step is continued for all the bits to do Gray code to binary conversion. One example given below will make your idea clear; Let the gray code be 01101 0 1 1 0 1      0 1 0 0 1

Gray Binary

The MSB of the binary will be 0 as the MSB of gray is 0. Now move to the next gray bit. As it is 1 the previous binary bit will alter i.e. it will be 1, thus the second binary bit will be 1. Next look at the third bit of the gray code. It is again 1 thus the previous bit i.e. the second binary bit will again alter and the third bit of the binary number will be 0. Now, 4th bit of the given gray is 0 so the previous binary bit will be unchanged, i.e. 4th binary bit will be 0. Now again the 5th grey bit is 1 thus the previous binary bit will alter, it will be 1 from 0. Therefore, the equivalent Binary number in case of gray code to binary conversion will be (01001).

2.9.4 Excess-3 (XS-3) Code Excess-3 code is an example of unweighted code (the positional weights are not assigned) and it is obtained by adding 3 and then converting it to a binary format. For instance to find excess-3 representation of the decimal number 4, first 3 is added to 4 to get 7 and then binary equivalent of 7 i.e. 0111 forms the excess-3 equivalent of 4. The table represents excess-3 equivalent of decimal numbers (0-9). Excess-3 code is also known as self complimenting code or reflective code, as 1′s compliment of any number (0-9) is available within these 10 numbers. For example 1′s complement of 9 (1100) is 0011.

The XS-3 code words are derived from the 8421 BCD code words adding (0011)2 or (3)10 to each code word in 8421 BCD Add Decimal XS-3 code . 8421 0011 Numbers

Dec 0 1 2 3 4 5 6 7 8 9

Binary; BCD

8 0 0 0 0 0 0 0 0 1 1

4 0 0 0 0 1 1 1 1 0 0

2 0 0 1 1 0 0 1 1 0 0

1 0 1 0 1 0 1 0 1 0 1

Excess-3 BCD + 0011 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0

Addition of two numbers in Excess-3 Code Example-2.9.4: 0101 (2) + 1000 (5) --------1101 (10) The result 1101 is in excess-6.

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To obtain an excess-3 equivalent, binary 3 needs to be subtracted from the result as follows: 1101 (10) - 0011 (3) -------1010 (7)

Example-2.9.5: 1111 1 0101 1100 (29) + 0110 1100 (39) -------------1100 1000 (95) Considering that 4 leftmost significant bits form column 1 and 4 rightmost significant bits form column 2. If carry is generated in addition, excess-3 equivalent is obtained by adding binary equivalent of 3 to the column generating carry and subtracting binary equivalent of 3 from the column that doesn’t generate any carry. In this example, carry is generated by column 1 and no carry is generated by column 2. Thus, excess-3 equivalent is calculated as follows: 1100 1000 (95) - 0011 + 0011 -------------1001 1011 (68) For excess-3 addition of decimal numbers, first convert the decimal numbers into binary and then perform the addition as explained above.

2.9.5 Bi-Quinary Coded Decimal Code Bi-quinary coded decimal is a numeral encoding scheme used in many abacuses and in some early computers, including the Colossus. The term bi-quinary indicates that the code comprises both a two-state (bi) and a five-state (quinary) component. The encoding resembles that used by many abaci, with four beads indicating either 0...4 or 5...9 and another bead indicating which of those ranges.

Fig. 2.9.4

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Decoding To decode the Biquinary code uses the number 5043210. At each digit multiply the biquinary number by the number 5043210. This will give you one decimal digit. For example take the number 0110000. To change this into decimal: (5 × 0) + (0 × 1) + (4 × 1) + (3 × 0) + (2 × 0) + (1 × 0) + (0 × 0) = 4

Example-2.9.6 Several different representations of bi-quinary coded decimal have been used by different machines. The two-state component is encoded as one or two bits, and the five-state component is encoded using three to five bits. Some examples are:  IBM 650-7 bits (two ‘bi’ bits: 0 5 and five ‘quinary’ bits: 0 1 2 3 4) with error checking. Exactly one ‘bi’ bit and one ‘quinary’ bit is set in a valid digit). In the pictures of the front panel below and in close-up, the bi-quinary encoding of the internal workings of the machine are evident in the arrangement of the lights – the 'bi' bits form the top of a T for each digit, and the 'quinary' bits form the vertical stem (the machine was running when the photograph was taken and the active bits are visible in the close-up and just discernible in the full panel picture). Value 0 1 2 3 4 5 6 7 8 9

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05-01234 Bits 10-10000 10-01000 10-00100 10-00010 10-00001 01-10000 01-01000 01-00100 IBM 650 front panel 01-00010 Close-up of IBM 650 indicators 01-00001

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2.9.6 Character (Alphanumeric) Codes A binary digit or bit can represent only two symbols as it has only two states '0' or '1'. But this is not enough for communication between two computers/devices because there we need many more symbols for communication. These symbols are required to represent 26 alphabets with capital and small letters, numbers from 0 to 9, punctuation marks and other symbols. The alphanumeric codes are the codes that represent numbers and alphabetic characters. Mostly such codes also represent other characters such as symbol and various instructions necessary for conveying information. An alphanumeric code should at least represent 10 digits and 26 letters of alphabet i.e. total 36 items. One of the most common forms of data transmitted between a transmitter and a receiver is textual data. For example, banking institutions that wish to transfer money often transmit textual information, such as account numbers, names of account owners, bank names, addresses, and the amount of money to be transferred. This textual information is transmitted as a sequence of characters. To distinguish one character from another, each character is represented by a unique binary pattern of 1s and 0s. The set of all textual characters or symbols and their corresponding binary patterns is called a data code. The following three alphanumeric codes are very commonly used for the data representation;  American Standard Code for Information Interchange (ASCII).  Extended Binary Coded Decimal Interchange Code (EBCDIC).  Five bit Baudot Code. ASCII code is a 7-bit code whereas EBCDIC is an 8-bit code. ASCII code is more commonly used worldwide while EBCDIC is used primarily in large IBM computers.

2.9.6.1 EBCDIC Code The Extended Binary Coded Decimal Interchange Code is an 8-bit code allowing 256 possible combinations of textual symbols (28 = 256). These 256 combinations of textual symbols include all uppercase and lowercase letters, the 10 digits, a large number of special symbols and punctuation marks, and a number of control characters. The control characters, such as line feed (LF) and carriage return (CR) provide control between a processor and an input/output device. Certain control characters provide data transfer control between a computer source and computer destination.

Zoned Decimal Some implementations, for example IBM mainframe systems, support zoned decimal numeric representations. Each decimal digit is stored in one byte, with the lower four bits encoding the digit in BCD form. The upper four bits, called the "zone" bits, are usually set to a fixed value so that the byte holds a character value corresponding to the digit. EBCDIC systems use a zone value of 1111 (hex F); this yields bytes in the range F0 to F9 (hex), which are the EBCDIC codes for the characters "0" through "9". Similarly, ASCII systems use a zone value of 0011 (hex 3), giving character codes 30 to 39 (hex). For signed zoned decimal values, the rightmost (least significant) zone nibble holds the sign digit, which is the same set of values that are used for signed packed decimal numbers (see above). Thus a zoned decimal value encoded as the hex bytes F1 F2 D3 represents the signed decimal value −123: F1 F2 D3 1 2 −3

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EBCDIC zoned decimal conversion table BCD Digit Hexadecimal

69

EBCDIC Character

0+

C0

A0

E0

F0

{ (*)

1+

C1

A1

E1

F1

A

~ (*)

2+

C2

A2

E2

F2

B

s

S

2

3+

C3

A3

E3

F3

C

t

T

3

4+

C4

A4

E4

F4

D

u

U

4

5+

C5

A5

E5

F5

E

v

V

5

6+

C6

A6

E6

F6

F

w

W

6

7+

C7

A7

E7

F7

G

x

X

7

8+

C8

A8

E8

F8

H

y

Y

8

9+

C9

A9

E9

F9

I

z

Z

9

0−

D0

B0

} (*) ^ (*)

1−

D1

B1

J

2−

D2

B2

K

3−

D3

B3

L

4−

D4

B4

M

5−

D5

B5

N

6−

D6

B6

O

7−

D7

B7

P

8−

D8

B8

Q

9−

D9

B9

R

\ (*)

0 1

(*) Note: These characters vary depending on the local character code page setting.

2.9.6.2 ASCII Code The American National Standard Code for Information Interchange (ASCII) is a government standard in the United States and is one of the most widely used data codes in the world. The ASCII character set comes in a few different forms including a 7-bit version that allows for 128 possible combinations of textual symbols (27 = 128), representing upper and lowercase letters, the digits 0 to 9, special symbols, and control characters. Since the byte is a common unit of data and consists of eight bits, the 7-bit version of ASCII characters usually includes an eighth bit. This eighth bit can be used to detect transmission errors, can provide for 128 additional characters defined by the application using the ASCII code set, or can simply be a binary 0. ASCII is a code for alphanumeric characters and control characters. In its original form, ASCII encoded 128 characters and symbols using 7-bits. The first 32 characters are control characters that are based on obsolete teletype requirements, so these characters are generally assigned to other functions in modern usage. In 1981, IBM introduced extended ASCII, which is an 8-bit code and increased the character set to 256. Other extended sets (such as Unicode) have been introduced to handle characters in languages other than English.

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Parity Method The parity method is a method of error detection for simple transmission errors involving one bit (or an odd number of bits). A parity bit is an “extra” bit attached to a group of bits to force the number of 1’s to be either even (even parity) or odd (odd parity). The ASCII character for “a” is 1100001 and for “A” is 1000001. What is the correct bit to append to make both of these have odd parity? The ASCII “a” has an odd number of bits that are equal to 1; therefore the parity bit is 0. The ASCII “A” has an even number of bits that are equal to 1; therefore the parity bit is 1.

Cyclic Redundancy Check The cyclic redundancy check (CRC) is an error detection method that can detect multiple errors in larger blocks of data. At the sending end, a checksum is appended to a block of data. At the receiving end, the check sum is generated and compared to the sent checksum. If the check sums are the same, no error is detected.

Background The binary-coded decimal scheme described in this article is the most common encoding, but there are many others. The method here can be referred to as Simple Binary-Coded Decimal (SBCD) or BCD 8421. In the headers to the table, the '8 4 2 1', etc., indicates the weight of each bit shown; note that in the fifth column two of the weights are negative. Both ASCII and EBCDIC character codes for the digits are examples of zoned BCD, and are also shown in the following table; IBM 702 IBM 705 BCD Excess-3 BCD 2 4 2 1 BCD ASCII IBM 7080 IBM 1401 Digit 8 4 2 1 or Stibitz Code or Aiken Code 8 4 −2 −1 0000 8421 8421

EBCDIC 0000 8421

0

0000 0011

0000

0000

1010

0011 0000 1111 0000

1

0001 0100

0001

0111

0001

0011 0001 1111 0001

2

0010 0101

0010

0110

0010

0011 0010 1111 0010

3

0011 0110

0011

0101

0011

0011 0011 1111 0011

4

0100 0111

0100

0100

0100

0011 0100 1111 0100

5

0101 1000

1011

1011

0101

0011 0101 1111 0101

6

0110 1001

1100

1010

0110

0011 0110 1111 0110

7

0111 1010

1101

1001

0111

0011 0111 1111 0111

8

1000 1011

1110

1000

1000

0011 1000 1111 1000

9

1001 1100

1111

1111

1001

0011 1001 1111 1001

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2.9.7 Error Detection and Correction Error Codes There are binary code techniques available to detect and correct data during data transmission; Error detection and correction code techniques. Error is a condition when the output information does not match with the input information. During transmission, digital signals suffer from noise that can introduce errors in the binary bits traveling from one Fig. 2.9.5 system to other. That means a 0 bit may change to 1 or a 1 bit may change to 0.

Error-Detecting codes Whenever a message is transmitted, it may get scrambled by noise or data may get corrupted. To avoid this, we use error-detecting codes which are additional data added to a given digital message to help us detect if an error occurred during transmission of the message. A simple example of error-detecting code is parity check.

Error-Correcting codes Along with error-detecting code, we can also pass some data to figure out the original message from the corrupt message that we received. This type of code is called an errorcorrecting code. Error-correcting codes also deploy the same strategy as error-detecting codes but additionally, such codes also detect the exact location of the corrupt bit. In errorcorrecting codes, parity check has a simple way to detect errors along with a sophisticated mechanism to determine the corrupt bit location. Once the corrupt bit is located, its value is reverted (from 0 to 1 or 1 to 0) to get the original message.

Detect and Correct Errors To detect and correct the errors, additional bits are added to the data bits at the time of transmission;  The additional bits are called parity bits. They allow detection or correction of the errors.  The data bits along with the parity bits form a code word.

Parity Checking of Error Detection It is the simplest technique for detecting and correcting errors. The MSB of an 8-bits word is used as the parity bit and the remaining 7 bits are used as data or message bits. The parity of 8-bits transmitted word can be either even parity or odd parity;

Fig. 2.9.6

 Even parity: Even parity means the number of 1's in the given word including the parity bit should be even (2,4,6,....).

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 Odd parity: Odd parity means the number of 1's in the given word including the parity bit should be odd (1,3,5,....).

Use of Parity Bit The parity bit can be set to 0 and 1 depending on the type of the parity required;  For even parity, this bit is set to 1 or 0 such that the no. of "1 bits" in the entire word is even; shown in Fig. 2.9.7(a).  For odd parity, this bit is set to 1 or 0 such that the no. of "1 bits" in the entire word is odd; shown in Fig. 2.9.7(b).

Fig. 2.9.7

Error Detection Parity checking at the receiver can detect the presence of an error if the parity of the receiver signal is different from the expected parity. That Fig. 2.9.8 means, if it is known that the parity of the transmitted signal is always going to be "even" and if the received signal has an odd parity, then the receiver can conclude that the received signal is not correct. If an error is detected, then the receiver will ignore the received byte and request for retransmission of the same byte to the transmitter.

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Besides, Sopto provides not only the classical 1x9 footprint duplex package but also advanced packages such as SFF (small form-factor) fiber optic transceiver, SFP (small form-factor pluggable) transceiver module, GBIC (Gigabit Interface Converter) fiber transceiver, BIDI (single fiber bi-directional) fiber optic transceiver, BIDI-SFP transceiver module, and BIDIGBIC transceiver, SFP+ transceiver module, XFP optical transceiver, Xenpak optical transceiver, X2 transceiver module. In addition, optical transceivers with Digital Diagnostic Function are also available. All optical transceivers are RoHS compliant and could be 100% compatible with branding equipment, such as Cisco, Extreme, Juniper, HP, H3C, Linksys, Huawei, Alcatel-Lucent, Foundry, Nortel, Force10 etc.

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2.10 Binary Number System Applications 2.10.1 Binary Numbers in Electronics In electronics, binary numbers are the flow of information in the form of zeros and ones used by digital computers and systems. Unlike a linear, or Fig. 2.10.1 analogue circuits, such as AC amplifiers, which process signals that are constantly changing from one value to another, for example amplitude or frequency, digital circuits process signals that contain just two voltage levels or states, labeled, Logic “0” and Logic “1”. Generally, a logic “1” represents a higher voltage, such as 5 volts, which is commonly referred to as a HIGH value, while a logic “0” represents a low voltage, such as 0 volts or ground, and is commonly referred to as a LOW value. These two discrete voltage levels representing the digital values of “1’s” (one’s) and “0’s” (zero’s) are commonly called: BInary digiTS, and in digital and computational circuits and applications they are normally referred to as binary BITS.

2.10.2 Binary Bits of Zeros and Ones Because there are only two valid Boolean values for representing either a logic “1” or a logic “0”, makes the system of using Binary Numbers ideal for use in Fig. 2.10.2 digital or electronic circuits and systems. The binary number system is a Base-2 numbering system which follows the same set of rules in mathematics as the commonly used decimal or base-10 number system. So instead of powers of ten, ( 10n ) for example: 1, 10, 100, 1000 etc, binary numbers use powers of two, ( 2n ) effectively doubling the value of each successive bit as it goes, for example: 1, 2, 4, 8, 16, 32 etc. The voltages used to represent a digital circuit can be of any value, but generally in digital and computer systems they are kept well below 10 volts. In digital systems theses voltages are called “logic levels” and ideally one voltage level represents a “HIGH” state, while another different and lower voltage level represents a “LOW” state. A binary number system uses both of these two states. Digital waveforms or signals consist of discrete or distinctive voltage levels that are changing back and forth between these two “HIGH” and “LOW” states. But what makes a signal or voltage “Digital” and how can we represent these “HIGH” and “LOW” voltage levels. Electronic circuits and systems can be divided into two main categories.  Analogue Circuits: Analogue or Linear circuits amplify or respond to continuously varying voltage levels that can alternate between a positive and negative value over a period of time.  Digital Circuits: Digital circuits produce or respond to two distinct positive or negative voltage levels representing either a logic level “1” or a logic level “0”.

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2.10.3 Analogue Voltage Output A simple example of the differences between an analogue (or analog) circuit and a digital circuit are shown in Fig. This is an analogue circuit. The output from the potentiometer varies as the wiper terminal is rotated producing an infinite number of output voltage points between 0 volts and Vmax. The output voltage can vary either slowly or rapidly from one value to the next so there is no sudden or step change between two Fig. 2.10.3: Analogue Voltage Output Representation voltage levels thereby producing a continuously variable output voltage. Examples of analogue signals include temperature, pressure, liquid levels and light intensity.

2.10.4 Digital Voltage Output In this digital circuit example, the potentiometer wiper has been replaced by a single rotary switch which is connected in turn to each junction of the series resistor chain, forming a basic potential divider network. As the switch is rotated from one position (or node) to the next the output voltage, Vout changes quickly in discrete and distinctive voltage levels representing multiples of 1.0 volts on each switching action or step, as shown in the output graph. So for example, the output voltage will be 2 volts, 3 volts, 5 volts, etc. but NOT 2.5V, 3.1V or 4.6V. Finer output voltage levels could easily be produced by using a multi-positional switch and increasing the number of resistive elements within the potential divider network, therefore increasing the number of discrete switching steps. Then we can see that the major difference between an analogue signal or quantity and a digital quantity is that an “Analogue” quantity is continuously changing over time while a “Digital” quantity has discrete (step by step) values. “LOW” to “HIGH” or “HIGH” to “LOW”. A good example of this Fig. 2.10.4: Digital Voltage Output Representation would be a light dimmer in your house that varies the lights intensity (brightness) up or down as it is rotated between fully-ON (maximum brightness) and fully-OFF, producing an analogue output that varies continuously. While on the other hand, with a standard wall mounted light switch, the light is either “ON” (HIGH) or

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it is “OFF” (LOW) when the switch is operated. The result is that there is no in between producing a form of ON-OFF digital output. Some circuits combine both analogue and digital signals such as an analogue to digital converter (ADC) or a digital to analogue converter (DAC). Either way, the digital input or output signal represents a binary number value equivalent of an analogue signal.

2.10.5 Digital Logic Levels In all electronic and computer circuits, only two logic levels are allowed to represent a single state. These levels are referred to as a logic 1 or a logic 0, HIGH or LOW, True or False, ON or OFF. Most logic systems use positive logic, in which case a logic “0” is represented by zero volts and a logic “1” is represented by a higher voltage. For example, +5 volts for TTL logic as shown.

Digital Value Representation First State Logic “0” LOW FALSE

Second State Logic “1” HIGH TRUE

Low Level Voltage Output

High Level Voltage Output

0V or Ground

+5 Volts

Generally the switching from one voltage level, “0” to “1” or “1” to “0” is made as quickly as possible to Fig. 2.10.5 prevent miss switching of the logic circuit. In standard TTL (transistor-transistor-logic) IC’s there is a pre-defined range of input and output voltage limits for defining what exactly is a logic “1” value and what is a logic “0” value as shown below.

TTL Input & Output Voltage Levels Then, when using a +5 volt supply any voltage input between 2.0v and 5v is recognized as a logic “1” value and any voltage input of below 0.8v is recognized as a logic “0” value. While the output of a logic gate between 2.7v and 5v represents a logic “1” value and a voltage output below 0.4v represents a logic “0” value. This is called “positive logic” and is used in these digital logic tutorials. Fig. 2.10.6 Then, binary numbers are commonly used in digital and computer circuits and are represented by either a logic “0” or a logic “1”. Binary numbering systems are best suited to the digital signal coding of binary, as it uses only two digits, one and zero, to form different figures. So in this section about binary numbers we will look at how to convert decimal or base-10 numbers into octal numbers, hexadecimal numbers, and binary numbers. So in the next tutorial about Binary Numbers and the binary number system we will look at converting decimal numbers into binary numbers and vice versa and introduce the concept of the Byte and the Word to represent the parts of a much larger binary number.

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2.11 Exercises: Numbers' Systems and Codes 1- Perform the following numbers’ conversions: (a) 531.3710 into Binary (base 2) (b) 1234.5610 into Octal (base 8) (c) B2F816 into Decimal (base 10) (d) 76428 into Hexadecimal (base 16) (e) -8610 into Binary (base 2) (f) -1610 into 2’s Complement (g) 7210 into BCD (h) 1101.0001012 into Decimal (base 10) (i) 0110111010012 into Octal (base 8) (j) 0110111010012 into Hexadecimal (base 16) (k) 01010011BCD into Decimal (base 10) 2- Perform the following numbers’ conversions: (a) 635.3710 into Binary (base 2) (b) 1236.5610 into Octal (base 8) (c) B2E816 into Decimal (base 10) (d) 6210 into BCD (e) 1101.1001012 into Decimal (base 10) (f) 0110111010012 into Octal (base 8) (g) 0110110110012 into Hexadecimal (base 16) (h) 1010011BCD into Decimal (base 10) 3- Which of the following is a proper binary number? a 102101 b 1010101 c 22101012 d B11 e 2 4- Which of the following is a proper octal number? a A21C1 b 1010101 c 76521 d B11 e 8 5- Which of the following is a proper Hexadecimal number? a A21C1 b 1010101 c 76521 d B11 e 16

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6- Find the result of the following mathematical operations: (a) Addition Binary Octal Carry

10111110 + 10101101

576 + 215

78

Hexadecimal

BE + 8F

Result (b) Subtraction Binary

Octal

Hexadecimal

Borrow

10000110 - 01011101

306 - 217

FE - 8D

Result (c) Multiplication Binary

10111110 x 10001101

Octal

306 x 31

Hexadecimal

BE x 3A

Result (d) Division Binary

Octal

Hexadecimal

Quotient

1110 10110001

31

11526

A5

1EC87

Remainder

7- Find the result of the following BCD operations: (a) Convert each of the following decimal numbers to BCD:  35, 98, 170, 2469 (b) Convert each of the following BCD codes to decimal:  10000110, 001101010001, 1001010001110000 (c ) Add the following BCD numbers:  0011 + 0100, 00100011 + 00010101  10000110 + 00010011, 010001010000 + 010000010111 8- Find the result of the following Gray code operations:  Convert the binary number 11000110 to Gray code.  Convert the Gray code 10101111 to binary.  In a certain application a 4-bit binary sequence cycles from 1111 to 0000 periodically. There are four bit changes, and because of circuit delays, these changes may not occur at the same instant. For example, if the LSB changes first, the number will appear as 1110 during the transition from 1111 to 0000 and may be misinterpreted by the system. Illustrate how the Gray code avoids this problem. 9- Find the result of the following code operations:  Convert the BCD into Gray code.  Convert the BCD into Excess-3 code.

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3- Logic Gates This chapter is devoted to the operation, application, and troubleshooting of logic gates. In addition, it covers the relationship of input and output waveforms of a gate using timing diagrams. Logic symbols used to represent the logic gates are in accordance with ANSI/IEEE Standard 91-1984/ Std. 91a-1991. This standard has been adopted by private industry and the military for use in internal documentation as well as published literature. Most modern electronic devices such as mobile telephones and computers depend on digital electronics. In fact, most electronics about the home and in industry depend on digital electronics to work. Digital electronics are normally based on ‘logic circuits’. These circuits depend on pulses of electricity to make the circuit work. For instance, if current is present, this is represented as ‘1’. If current is not present, this is represented as ‘0’. Digital electronics are based on a series of 1s and 0s. A good example of a digital electronic system is a mobile phone, Fig. 3.1. As you speak into the phone, the digital electronic circuit converts your voice into a series of electronic pulses (or 1s and 0s). These pulses are transmitted towards the receiving mobile phone which converts the digital pulses back into your voice. Digital circuits are used because they are efficient and work well, also, digital signals are easier to transmit than actual sound (for example a persons voice).

Fig. 3.1 The various parts of a computer communicate through the use of electronic pulses (1s and 0s). Consequently digital logic circuits are ideal for the internal electronics. The main part of the computer is the motherboard. This is a complex piece of electronics that processes all the important data. For instance, when word processing, it is very important to display letters and words on the monitor. The motherboard generates the individual letters on the monitor by sending a series of 1s and 0s to the screen. When the computer operator presses the letter ‘H’ on the keyboard, the motherboard converts this into a digital signal composed of 1s and 0s. The ‘H’ in the form of 1s and 0s is displayed on the monitor. When you word-process a paragraph of writing all the letters/words are displayed on the monitor in a similar way. In reality the letters are not composed of 1s and 0s but as black or white pixels. Logic gates take binary values and perform functions on them, similar to the functions found in simple algebra. Binary algebra is the set of mathematical laws that are valid for binary values. A binary value can only be a 1 or a 0. 1 is a high value, representing true and high voltage. 0 is a low value, representing a false value and low voltage. Logic gates are typically packaged in integrated circuits, although they can be constructed using analogue components. Integrated circuits allow multiple logic gates to be packaged in one chip and are usually quite reliable. Logic gates typically come in two flavors, TTL (transistor-transistor logic) and CMOS (Complementary Metal Oxide Semiconductor). One

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must be careful mixing the two types, there logic low and logic high are different voltages. A CMOS might take a TTL high as a LOW and a TTL will accept a CMOS low as a high. Because of this they are generally incompatible, but there are a few CMOS that can accept TTL inputs and vice versa.

3.1 Binary Logic Binary logic deals with variables that take on two discrete values and with operations that assume logical meaning. The two values that variables can take may be called by different names such as true/false, yes/no, on/off, high/low, etc and in terms of bits might be 1/0. Binary logic is used to describe mathematically the manipulation and processing of binary information, specifically the analysis and design of digital systems. The binary logic consists of binary variables (designated by letters) and logical operations (AND, OR, NOT). The logical operation can be described by a truth table, which presents all possible combinations of variables showing the relation between them and the operation output. Therefore,  In binary logic circuits there are only two values, 0 and 1.  The general form of a logic circuit is a switching network  The simplest binary element is a switch that has two states: ON/OFF  If the switch is controlled by x, we say the switch is open if x =0 and closed if x =1

Fig. 3.1.1

Example-3.1.1: Assume the switch controls a light-bulb as shown in figure where the output is defined as the state of the light L;  If the light is on causes L=1  If the light is off causes L=0 The state of L, as function of x is L(x)=x; where  L(x) is a logic function  x is an input variable

Fig. 3.1.2 Logic gates process signals which represent true or false; normally the positive supply voltage +Vs represents true and 0V represents false. Other terms which are used for the true and false states are shown in the table and it is best to be familiar with them all. Logic states True False 1 0 High Low +Vs 0V On Off

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3.2 Logic Operations 3.2.1 Inversion (NOT) Operation In the previous operations, actions occur when a switch is closed while in this case the concern is to look for the possibility of an action occurring when a switch is opened? – L(x)= x – Where L=1 if x=0 and L=0 if x=1 That is, L(x) is the inverse (or complement) of x.

Fig. 3.2.1

3.2.2 OR Operation Using a parallel connection, the light will be on only if either or both switches are closed i.e. – L(x1, x2) = x1+ x2 – L =1 if x1 OR x2 is 1 (or both) The simplified OR gate shown in Fig. has two inputs, switch A and switch B. The bulb Q will light if either switch A or B are closed. This will allow current to flow through the bulb, illuminating the filament. When the bulb lights this represents a ‘1’ as current is running through the filament. Fig. 3.2.2b Fig. 3.2.2a If current is not running through the filament the bulb will not light and this represents a ‘0’ (zero). This is an OR gate circuit; either switch ‘A’ or ‘B’ must be pressed for the bulb to light. The switches do not have to be pressed together.

3.2.3 AND Operation

Fig. 3.2.2c

 Consider the possibility of two switches controlling the state of the light  Using a series connection, the light will be on only if both switches are closed i.e. – L(x1, x2) = x1· x2 – L=1 iff (if and only if) x1 AND x2 are 1

The simplified AND gate shown in Fig. has two inputs, switch A and switch B. The bulb Q will only light if both switches are closed. This will allow current to flow through the bulb, illuminating the filament.

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This is an AND gate circuit and it can be made quite easily. The example shown is built from a modular electronics kit. Both switches ‘A’ and ‘B’ must be pressed together for the bulb to light. If you construct this circuit, you may need to alter the value of the resistors. This will depend on the type of transistors used and whether to bulb or an LED is used. Fig. 3.2.3b Fig. 3.2.3a Transistors represent digital circuits' components that are used as very fast switches in digital logic circuits and they are normally so small in size and weights. When a transistor is switched on it produces a ‘1’ and when it is switched off it produces a ‘0’. Transistors in the circuit of a computer microprocessor can switch on and off thousands of times per second.

Fig. 3.2.3c

3.2.4 Combined OR-AND Operations Various series-parallel connections would realize various logic functions – L(x1, x2, x3) = (x1 + x2) · x3 Fig. 3.2.4

3.2.5 Truth Table A truth table is a table that describes the behaviour of a logic gate. It lists the value of the output for every possible combination of the inputs and can be used to simplify the number of logic gates and level of nesting in an electronic circuit. In general the truth table does not lead to an efficient implementation; a minimization procedure, using Karnaugh maps, the Quine– McCluskey algorithm or a heuristic algorithm is required for reducing the circuit complexity.

3.2.6 Symbols There are two sets of symbols in common use, both now defined by ANSI/IEEE Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and is quicker to draw by hand. It is sometimes unofficially described as "military", reflecting its origin if not its modern usage. The "rectangular shape" set, based on IEC 60617-12, has rectangular outlines for all types of gate, and allows representation of a much wider range of devices than is possible with the traditional symbols. The IEC's system has been adopted by other standards, such as EN 60617-12:1999 in Europe and BS EN 60617-12:1999 in the United Kingdom.

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The goal of IEEE Std 91-1984 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium scale circuits such as a 4-bit counter to a large scale circuits such as a microprocessor. The 1984 version did not include the "distinctive shape" symbols. These were added to the 1991 supplement with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." In the 1980s, schematics were the predominant method to design both circuit boards and custom ICs known as gate arrays. Today custom ICs and the field-programmable gate array are typically designed with Hardware Description Languages (HDL) such as Verilog or VHDL. The need for complex logic symbols has diminished and distinctive shape symbols are still the predominate style.

3.2.7 Types of Logic Gates According to the discussions concerning logic operations, the following points can be considered; • Logic gates are the building blocks of any digital circuit. • Logic gates are electronic circuits/devices which makes the logical decisions. • They have one or more inputs and only one output. • The output is active only for certain input combinations. • Logic gates are also called switches. • Logic gates can be categorized into there groups: – Basic Logic Gates (NOT, OR, AND) – Universal Logic Gates (NOR, NAND) – Special (exclusive) Logic Gates (XOR, XNOR) • Logic Gates/Circuits are described by the following: – Logic Symbol – Logic Function/Expression – Truth Table – Output waveform if the input is in the form of signal

3.3 Basic Logic Gates The basic logic gates are used in various combinations to perform tasks of any level of complexity. Some functions are so commonly used that they have been given symbols of their own, and are often packaged so as to provide that specific function directly. NOT

OR

AND

Gate Traditional symbol IEC symbol

Gates have two or more inputs, except a NOT gate which has only one input and all gates have only one output. International Electrotechnical Commission (IEC) 60417 standard, Graphical symbols for use on equipment.

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3.3.1 The NOT (Inverter) Gate The inverter is a little different from AND and OR gates in that it always has exactly one input as well as one output. Whatever logical state is applied to the input, the opposite state will appear at the output. The NOT function, as it is called, is necessary in many applications and highly useful in others. A practical verbal application might be: The door is NOT locked = You may enter The NOT function is denoted by a horizontal bar over the value to be inverted, as shown in the figure to the left. In some cases a single quote mark (') may also be used for this purpose, however for greater clarity in logical expressions, we will use the over-bar most of the time, where 0  1 and 1  0 ; A QA 0 1 1 0 0 In the inverter symbol, the triangle actually Fig. 3.3.1: NOT Gate denotes only an amplifier, which in digital terms means that it "cleans up" the signal but does not change its logical sense. It is the circle at the output which denotes the logical inversion. The circle could have been placed at the input instead, and the logical meaning would still be the same. The buffer and NOT gates are the simplest of the logic gates. The buffer would be used as a digital signal booster, if a logic signal was to travel for some distance voltage drop from wire resistance would lower a logic high voltage so low that when it reaches its destination its read as a logic low, putting this in between would solve that problem. The buffer's algebra function is B = A. The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It is also known as an inverter. If the input variable is A, the inverted output is known as NOT A. This is also shown as A', or A with a bar over the top, as shown at the outputs. The diagrams below show two ways that the NAND logic gate can be configured to produce a NOT gate. It can also be done using Fig. 3.3.2: NOT Gate Realized by NANDs NOR logic gates in the same way. NOT gates simply change the input from a 1 to a 0 or vice versa. It is also called an inverter and has many uses in logic circuits. For example, you have 2 lights, but you only want 1 on at any one time, you would put a NOT gate between one light so when there is a logic high input 1 light is on and the other connected to the NOT gate is off and when there is a logic low input the second comes on because of the NOT gate. The circle on the end of the triangle indicates that it is an inverting gate and you can recognize any inverting logic device by this circle. The equivalent binary algebra function is B  A , where B is the output and A is an input value. The output is true iff the input A is false. Fig. 3.3.3: NOT and Buffer Gates

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Inverter operation with a pulse input; When the input is LOW, the output is HIGH; when the input is HIGH, the output is LOW, thereby producing an inverted output pulse as shown in Fig. 3.3.3b. Fig. 3.3.3b

Example-3.3.1: A waveform is applied to the inverter in Fig. 3.3.3c; determine the output waveform corresponding to the input and show the timing diagram clarifying the active output state. Fig. 3.3.3c Solution: The output waveform is exactly opposite to the input (inverted), as shown in Fig. 3.3.3d, which is the basic timing diagram. In addition, the active or asserted output state is 0.

Fig. 3.3.3d

3.3.2 The OR Gate

The OR function, like its verbal counterpart, allows the output to be true (logic 1) if any one or more of its inputs are true. Verbally, we might say, "If it is raining OR if I turn on the sprinkler, the lawn will be wet." Note that the lawn will still be wet if the sprinkler is on and it is also raining. This is correctly reflected by the basic OR function. In symbols, the OR function is designated with a plus sign (+). In logical diagrams, the symbol to the left designates the OR gate. 0 The OR function can have any number of inputs, however 1 practical commercial OR gates are mostly limited to 2, 3, and 4 inputs. B 0 0 1 1

A 0 1 0 1

FAB 0 1 1 1

F

Fig. 3.3.4: OR Gate

B 0 0 1 1 Traditional symbol

IEC symbol

A FAB 0 0 1 1 0 1 1 1 Truth Table

The OR gate has a minimum of two inputs and produces an output of 1 if at least one of the inputs has a value of 1. An OR gate could be used to expand the number of reed switches in the previous example. The equivalent binary algebra function is F = A + B + ... + N, where F

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is the output and A and B are two of N total inputs. The output is true iff A is true, or B is true, or both. The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high. A plus (+) is used to show the OR operation. In addition, the operation of the OR gate is described by the waveforms shown in Fig. 3.3.5.

A

0

1

1

1

0

1

0

0

B

0

0

0

1

1

1

0

1

0

1

1

1

1

1

0

1

F Fig. 3.3.5: OR Gate with waveforms

Considering the two input waveforms (A and B) shown in Fig. 3.3.6 are applied to the OR gate, the resulting output waveform is also shown in Fig. 3.3.6 as; The output waveform X of a 2-input OR gate is HIGH when either or both input waveforms are HIGH as shown in the timing diagram. In this case, both input waveforms are never HIGH at the same time.

Fig. 3.3.6

Considering the three input waveforms (A, B and C) shown in Fig. 3.3.7 are applied to the OR gate, the resulting output waveform is also shown in Fig. 3.3.7 as; Fig. 3.3.7 The output is HIGH when one or more of the input waveforms are HIGH as indicated by the output waveform X in the timing diagram.

OR-Gate Applications A simplified portion of an intrusion detection and alarm system is shown in Fig. 3.3.8, which can be used for one room in a home; a room with two windows and a door. The sensors are magnetic switches that produce a HIGH output when open and a LOW output when closed. As long as the windows and the door are secured, the switches are closed and all three of the OR gate inputs are LOW. When one of the windows or the door is opened, a HIGH is

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produced on that input to the OR gate and the gate output goes HIGH. It then activates and latches an alarm circuit to warn of the intrusion. Fig. 3.3.8: A simplified intrusion detection system using an OR gate

3.3.3 The AND Gate The AND gate implements the AND function. With the gate shown in Fig. 3.3.9, both inputs must have logic 1 signals applied to them in order for the output to be logic 1. With either input at logic 0, the output will be held to logic 0; B 0 0 1 1

A 0 1 0 1

F  AB 0 0 0 1

0 1 Fig. 3.3.9: AND Gate

There is no limit to the number of inputs that may be applied to an AND function, so there is no functional limit to the number of inputs an AND gate may have. However, for practical reasons, commercial AND gates are most commonly manufactured with 2, 3, or 4 inputs. A standard Integrated Circuit (IC) package contains 14 or 16 pins, for practical size and handling. A standard 14-pin package can contain four 2-input gates, three 3-input gates, or two 4-input gates, and still have room for two pins for power supply connections. An AND gate truth table is a good way to show the function of its operation. It shows the output states for every possible combination of input states. The symbols 0 (false) and 1 (true) are usually used in truth tables; B A F  AB 0 0 0 F 0 1 0 1 0 0 1 1 1 Traditional symbol IEC symbol Truth Table The AND gate most commonly come in IC packages of 2 and 3 input versions. The output only produces a logical 1 when all of the inputs are 1. An AND gate could be used in an alarm circuit, Fig. 3.3.10, where input A would be a reed switch input and B would be an armed control, So the alarm would only be activated if the alarm was active AND the reed switch was circuit was opened (opened door).

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F

F

F

Fig. 3.3.10: AND Gate with Alarm

The equivalent binary algebra function is F = A * B * ... * N, where F is the output and A and B are two of N total inputs. The output is true if and only if (iff) both A and B are true. The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A dot (.) is used to show the AND operation i.e. A.B. Bear in mind that this dot is sometimes omitted i.e. AB. In addition, the operation of the AND gate is described by the waveforms shown in Fig. 3.3.11.

A

0

1

1

1

0

1

0

0

B

0

0

0

1

1

1

0

1

0

0

0

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1

0

0

F=AB

Fig. 3.3.11: AND Gate with waveforms

Considering the two input waveforms, A and B, shown in Fig. 3.3.12, the output waveform with its proper relation to the inputs is also shown in Fig. 3.3.12 as;

The output waveform is HIGH only when both of the input waveforms are HIGH as shown in the timing diagram.

Fig. 3.3.12: AND gate with timing diagram

Considering the three input waveforms (A, B and C) shown in Fig. 3.3.13, the output waveform with its proper relation to the inputs is also shown in Fig. 3.3.13 as;

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The output waveform X of the 3-input AND gate is HIGH only when all three input waveforms A, B, and C are HIGH. Fig. 3.3.13: 3-Input-AND gate with timing diagram

AND Gate Applications  The AND Gate as an Enable/Inhibit Device: A common application of the AND gate is to enable the passage of a signal (pulse waveform) from one point to another at certain times and to inhibit (prevent) the passage at other times. A simple example of this particular use of an AND gate is shown in Fig. 3.3.14, where the AND gate controls the passage of a signal (waveform A) to a digital counter. The purpose of this circuit is to measure the frequency of waveform A; the enable pulse has a width of precisely 1 ms. When the enable pulse is HIGH, waveform A passes through the gate to the counter; and when the enable pulse is LOW, the signal is prevented (inhibited) from passing through the gate. During the 1 millisecond (1 ms) interval of the enable pulse, pulses in waveform A pass through the AND gate to the counter. The number of pulses passing through during the 1 ms interval is equal to the frequency of waveform A. For example, Fig. 3.3.14 shows six pulses in one millisecond, which is a frequency of 6 kHz. If 1000 pulses pass through the gate in the 1 ms interval of the enable pulse, there are 1000 pulses/ms, or a frequency of 1 MHz.

Fig. 3.3.14: AND gate performing an enable/inhibit function for a frequency counter

The counter counts the number of pulses per second and produces a binary output that goes to a decoding and display circuit to produce the frequency-readout. The enable pulse repeats at certain intervals and a new updated count is made so that if the frequency changes, the new value will be displayed. Between enable pulses, the counter is reset so that it starts at zero each time an enable pulse occurs. The current frequency count is stored in a register so that the display is unaffected by the resetting of the counter.

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 AND in a Seat Belt Alarm System: Figure 3.3.15 shows an AND gate that is used in a simple automobile seat belt alarm system to detect when the ignition switch is on and the seat belt is unbuckled. If the ignition switch is on, a HIGH is produced on input A of the AND gate. If the seat belt is not properly buckled, a HIGH is produced on input B of the AND gate. Also, when the ignition switch is turned on, a timer is started that produces a HIGH on input C for 30 s. If all three conditions exist; that is, if the ignition is on and the seat belt is unbuckled and the timer is running, the output of the AND gate is HIGH, and an audible alarm is energized to remind the driver.

Fig. 3.3.15: A simple seat belt alarm circuit using an AND gate

3.3.4 Tristate Logic Gate (Tristate Buffer) A tri-state buffer has two inputs: − a data input x and − a control input c.

Fig. 3.3.16

A

C 0 1 1

Y

A X 0 1

Y Hi-Z 0 1

Y

A

C 0 0 1

A 0 1 1

Y 0 1 Hi-Z

• The control input acts like a valve; when the control input is active, the output is the input. That is, it behaves just like a normal buffer. • The basic concept of the third state, high impedance (Hi-Z), is to effectively remove the device's influence from the rest of the circuit. If more than one device is electrically connected to another device, putting an output into the Hi-Z state is often used to prevent short circuits, or one device driving high (logical 1) against another device driving low (logical 0). • Three-state buffers can also be used to implement efficient multiplexers ,especially those with large numbers of inputs. • Three-state buffers are essential to the operation of a shared electronic bus. • Three-state logic can reduce the number of wires needed to drive a set of LED's (tri-state multiplexing).

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3.4 Universal Logic Gates The NAND and NOR gates are called universal functions since with either one the AND and OR functions and NOT (basic logic functions) can be generated. A function in sum of products (SOP) form can be implemented using NAND gates by replacing all AND and OR gates by NAND gates. A function written in product of sums (POS) form can be implemented using NOR gates by replacing all AND and OR gates by NOR gates.

3.4.1 NAND gate (NAND = Not AND) This is an AND gate with the output inverted, as shown by the 'o' on the output. The output is true if input A AND input B are NOT both true: F = NOT (A AND B) A NAND gate can have two or more inputs, its output is true if NOT all inputs are true. B 0 0 1 1 Traditional symbol

IEC symbol

A F  AB 0 1 1 1 0 1 1 0 Truth Table

The NAND gate has a minimum of two inputs and is the equivalent of an AND gate with a NOT gate on the output. It produces a 0 only if all of the inputs are 1. A NAND gate could be used to switch a device off if it gets too hot or a cooling fan stops working, so a temperature sensor would be connected to input A and a tachometer output filtered so its a logical high when there is rotation and logical low when there is no rotation, is connected to input B. The equivalent binary algebra function is F  (A  B  C.......  N) , where F is the output and A and B are two of N total inputs. The output is true iff A and B are not both true. This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on the output. The small circle represents inversion.

F

F

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Fig. 3.4.1: NAND Gate & I/O Waveforms Dlogic103-gate1

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Considering the two waveforms A and B shown in Fig. 3.4.2 are applied to the NAND gate inputs, the resulting output waveform is shown in Fig. 3.4.2 as;

Output waveform X is LOW only during the four time intervals when both input waveforms A and B are HIGH as shown in the timing diagram. Fig. 3.4.2 Considering the three waveforms (A, B and C) shown in Fig. 3.4.3 are applied to the NAND gate inputs, the resulting output waveform is shown in Fig. 3.4.3 as; Fig. 3.4.3

The output waveform X is LOW only when all three input waveforms are HIGH as shown in the timing diagram.

Example: Two-Tank Problem Two tanks store certain liquid chemicals that are required in a manufacturing process, where each tank has a sensor that detects when the chemical level drops to 25% of full. The sensors produce a HIGH level of 5 V when the tanks are more than one-quarter full. When the volume of chemical in a tank drops to one-quarter full, the sensor puts out a LOW level of 0 V. It is required that a single green light-emitting diode (LED) on an indicator panel show when both tanks are more than one-quarter full. Show how a NAND gate can be used to implement this function. Solution: Figure 3.4.4 shows a NAND gate with its two inputs connected to the tank level sensors and its output connected to the indicator panel. The operation can be stated as follows:  If tank A and tank B are above one-quarter full, the LED is on. As long as both sensor outputs are HIGH (5 V), indicating that both tanks are more than one-quarter full, the NAND gate output is LOW (0 V). The green LED circuit is connected so that a LOW voltage turns it on. The resistor limits the LED current.

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Example: Two-Tank Problem For the process described in the above Example, it has been decided to have a red LED display come on when at least one of the tanks falls to the quarter-full level rather than have the green LED display indicate when both are above one quarter. Show how this requirement can be implemented. Solution: Figure 3.4.5 shows a NAND gate Fig. 3.4.5 operating as a negative-OR gate to detect the occurrence of at least one LOW on its inputs. A sensor puts out a LOW voltage if the volume in its tank goes to one-quarter full or less. When this happens, the gate output goes HIGH. The red LED circuit in the panel is connected so that a HIGH voltage turns it on. The operation can be stated as follows: If tank A or tank B or both are below one-quarter full, the LED is on. This example and the above Example utilize the same 2-input NAND gate, but in this example it is operating as a negative-OR gate and a different gate symbol is used in the schematic. This illustrates the different way in which the NAND and equivalent negative-OR operations are used.

3.4.2 NOR gate (NOR = Not OR) This is an OR gate with the output inverted, as shown by the 'o' on the output. The output F is true if NOT inputs A OR B are true: F = NOT (A OR B). A NOR gate can have two or more inputs, where its output is true if no inputs are true. B 0 0 1 1 Traditional symbol

IEC symbol

A FAB 0 1 1 0 0 0 1 0 Truth Table

The NOR gate has a minimum of two inputs and is the same as an OR gate with a NOT gate on the output. The NOR gate produces a 1 only if all of the inputs are 0. The NOR gate can be used to shutdown a device if either of 2 temperature sensors measure a temperature too high for the circuit. The equivalent binary algebra function is F  (A  B  C  ......  N) where F is the output and A and B are two of N total inputs; the output is true iff neither A nor B is true.

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This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on the output; the small circle represents inversion.

A

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F

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Fig. 3.4.6: NOR Gate & I/O Waveforms The output waveform for the 3-input NOR gate shown in Fig. 3.4.7 with the proper time relation to the inputs is obtained as follows; Fig. 3.4.7

The output X is LOW when any input is HIGH as shown by the output waveform X in the timing diagram.

Example: Aircraft Monitoring System An aircraft’s functional monitoring system contains a circuit that is required to indicate the status of the landing gears prior to landing. A green LED display turns on if all three gears are properly extended when the “gear down” switch has been activated in preparation for landing. A red LED display turns on if any of the gears fail to extend properly prior to landing. When a landing gear is extended, its sensor produces a LOW voltage. When a landing gear is retracted, its sensor produces a HIGH voltage. Implement a circuit to meet this requirement. Solution: Power is applied to the circuit only when the “gear down” switch is activated. Use a NOR gate for each of the two requirements as shown in Fig. 3.4.8. One NOR gate operates as a negative-AND to detect a LOW from each of the three landing gear sensors. When all three of the gate inputs are LOW, the three landing gears are properly extended and the resulting HIGH output from the negative-AND gate turns on the green LED display. The other NOR gate operates as a NOR to detect if one or more of the landing gears remain retracted when the “gear down” switch is activated. When one or more of the landing gears remain retracted, the resulting HIGH from the sensor is detected by the NOR gate, which produces a LOW output to turn on the red LED warning display.

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Fig. 3.4.8

3.5 Special Logic Gates 3.5.1 EXOR (EXclusive-OR) Gate The output Q is true if either input A is true OR input B is true, but not when both of them are true: F = (A AND NOT B) OR (B AND NOT A). This is like an OR gate but excluding both inputs being true. The output is true if inputs A and B are DIFFERENT. B A F  AB 0 0 0 0 1 1 1 0 1 1 1 0 Traditional symbol IEC symbol Truth Table The XOR gate has a minimum of two inputs. The NOR gate produces a 1 only if one of the inputs is a 1. The equivalent binary algebra F function is F F  ABA B  AB where F is the output and A and B are two inputs; the output is true iff A is not equal to B. The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of its two inputs are high. An encircled plus sign ( ) is used to show the XOR operation. The exclusive OR gate is a modified OR gate that produces a HIGH output when only one of the inputs is HIGH. Fig. 3.5.1a: XOR gate When both inputs are HIGH or when both inputs are LOW, the output is LOW. XOR

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To observe the input and output signals of an X-OR gate, the results would be similar to those shown in Fig. 3.5.1b. At T0, both inputs are LOW and the output is LOW. At T1, A goes to HIGH and remains HIGH until T2. During this time the output is HIGH. At T3, B goes HIGH and remains HIGH through T5. At T4, A again goes HIGH and remains HIGH through T5. Between T3and T4, the output is HIGH. At T4, when both A and B are HIGH, the output goes LOW.

Fig. 3.5.1b: XOR gate timing diagram XOR Operation with Waveform Inputs As we have done with the other gates, let’s examine the operation of XOR and XNOR gates with pulse waveform inputs. As before, we apply the truth table operation during each distinct time interval of the pulse waveform inputs, as illustrated in Fig. 3.5.2 for an XOR gate. You can see that the input waveforms A and B are at opposite levels during time intervals t2 and t4. Therefore, the output X is HIGH during these two times. Since both inputs are at the same level, either both HIGH or both LOW, during time intervals t1 and t3, the output is LOW during those times as shown in the timing diagram. Fig. 3.5.2: XOR gate operation with pulse waveform inputs

3.5.2 XNOR (EXclusive-NOR) Gate This is an EX-OR gate with the output inverted, as shown by the 'o' on the output. The output F is true if inputs A and B are the same (both true or both false): F = (A AND B) OR (NOT A AND NOT B). B 0 0 1 1 Traditional symbol

IEC symbol

A F  AB 0 1 1 0 0 0 1 1 Truth Table

The XNOR gate has a minimum of two inputs. The XNOR gate produces an output of 1 if inputs A and B match. The most obvious application for this logic gate is a comparator, this

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could be used as error checking in data transmission or it can form the basis of a combination keypad. The equivalent binary algebra function is

F  (A B  A B)  A B  A B  A  B where F is the output and A and B are two inputs; the output is true iff A is equal to B. Fig. 3.5.3: XNOR Gate The 'Exclusive-NOR' gate circuit does the opposite to the XOR gate (the exclusive NOR (XNOR) gate is nothing more than an XOR gate XNOR with an inverted output). It will give a low output if either, but not both, of its two inputs are high. The symbol is an XOR gate with a small circle on the output, the small circle represents inversion.

A timing diagram for the X-NOR gate is shown in Fig. 3.5.4. You can see that from T0 to T1, when both inputs are LOW, the output is HIGH. The output goes LOW when the inputs are opposite; one HIGH and the other LOW. At time T3, both inputs go HIGH causing the output to go HIGH.

Fig. 3.5.4: XNOR timing diagram

HW; Using drawing and explanation, discuss different real applications for the XOR and XNOR.

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3.6 Combinations of Logic Gates Logic gates can be combined to produce more complex functions. They can also be combined to substitute one type of gate for another. In addition, Truth tables can be used to work out the function of a combination of gates.

3.6.1 Truth Tables and Logic Circuits Given a truth table, the corresponding logic circuit can be designed as presented in the following examples.

Example 3.6.1: Design a logic circuit to produce an output Q which is Inputs Outputs true only when input A is true and input B is false, as shown in the truth table. A B

Q

0 0

0

0 1

0

1 0

1

1 1

0

Solution: We can combine a NOT gate and an AND gate like the following equation: Q  AB

Fig. 3.6.1: (a) Truth table, (b) Logic circuit

Example 3.6.2: Design a logic circuit to produce an output Q

Inputs Outputs which is dependent on the intermediate outputs D and E, as A B C D E Q shown in the truth table. 0 0 0 1 0 1

Solution: The logic expressions are obtained as, D = NOT (A OR B) E = B AND C Q = D OR E = (NOT (A OR B)) OR (B AND C) These expressions can be rewritten as, DAB E  BC Q  D  E  (A  B)  B C  A B  B C

0

0

1

1

0

1

0

1

0

0

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0

0

1

1

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0

1

0

1

0

0

0

1

1

0

0

0

0

1

1

1

0

1

1

Consequently the logic circuit is shown in Fig. 3.6.2(b).

Fig. 3.6.2: (a) Truth table, (b) Logic circuit

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3.6.2 NAND gate Equivalents The basic logic gates (NOT, AND, OR and NOR) can be realized using NAND gates as shown in the following table: Gate Equivalent in NAND gates NOT

AND

OR

NOR

Example 3.6.3: Re-design the system of Example 3.6.2 using NAND gates only. Solution: Begin by replacing each gate with its NAND gate equivalent, as shown in Fig. 3.6.3(a). Then, simplify the system by deleting adjacent pairs of NOT gates (marked X above). This can be done because the second NOT gate cancels the action of the first. The final Fig. 3.6.3(a) system is shown in Fig. 3.6.3(b). It has five NAND gates and requires two ICs (with four gates on each IC). This is better than the original system which required three ICs (one for each type of gate). Substituting NAND (or NOR) gates does not always increase the number of gates, but when it does (as in this example) the increase is usually only one or two gates. The real benefit is reducing the number of ICs required by using just one type of gate. Fig. 3.6.3(b) Dlogic103-gate1

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3.6.3 NOR gate Equivalents The basic logic gates (NOT, AND, OR and NAND) can be realized using NOR gates as follows:  



AB

 Fig. 3.6.4: NOR Equivalence

Example 3.6.4: Re-design the system of Example 3.6.2 using NOR gates only. Solution: Begin by replacing each gate with its NOR gate equivalent, as shown in Fig. 3.6.5.

ABAB

BC A B

Q

B  C  BC Fig. 3.6.5: Equivalent Logic circuit using NOR-gates only

Q  ( B C  A B)  B C  A B

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3.7 Electronics Implementation within Digital Logic Gates A Digital Logic Gate is an electronic device that makes logical decisions based on the different combinations of digital signals present on its inputs. Digital logic gates may have more than one input, (A, B, C, etc.) but generally only have one digital output, (Q). Individual logic gates can be connected together to form combinational or sequential circuits or larger logic gate functions. Standard commercially available digital logic gates are available in two basic families or forms, Transistor-Transistor Logic (TTL) such as the 7400 series, and Complementary Metal-Oxide-Silicon (CMOS) which is the 4000 series of chips. This notation of TTL or CMOS refers to the logic technology used to manufacture the integrated circuit (IC) or a “chip” as it is more commonly called. Generally, TTL logic IC’s use NPN and PNP type Bipolar Junction Transistors (BJT) while CMOS logic IC’s use complementary MOSFET or JFET type Field Effect Transistors (FET) for both their input and output circuitry. As well as TTL and CMOS technology, simple digital logic gates can also be made by connecting together diodes, transistors and resistors to produce Resistor-Transistor logic gates (RTL), Diode-Transistor logic (DTL) gates or Emitter-Coupled logic (ECL) gates but these are less common now compared to the popular CMOS family. The use of transistors for the construction of logic gates depends upon their utility as fast switches. When the base-emitter diode is turned on enough to be driven into saturation, the collector voltage with respect to the emitter may be near zero and can be used to construct gates for the TTL logic family.

3.7.1 Classification of Integrated Circuits Integrated Circuits (IC’s) can be grouped together into families according to the number of transistors or “gates” that they contain. For example, a simple AND gate my contain only a few individual transistors, were as a more complex microprocessor may contain many thousands of individual transistor gates. Integrated circuits are categorized according to the number of logic gates or the complexity of the circuits within a single chip with the general classification for the number of individual gates given as:  Small Scale Integration or (SSI); Contain up to 10 transistors or a few gates within a single package such as AND, OR, NOT gates.  Medium Scale Integration or (MSI); between 10 and 100 transistors or tens of gates within a single package and perform digital operations such as adders, decoders, counters, flip-flops and multiplexers.  Large Scale Integration or (LSI); between 100 and 1,000 transistors or hundreds of gates and perform specific digital operations such as I/O chips, memory, arithmetic and logic units.  Very-Large Scale Integration or (VLSI); between 1,000 and 10,000 transistors or thousands of gates and perform computational operations such as processors, large memory arrays and programmable logic devices.  Super-Large Scale Integration or (SLSI); between 10,000 and 100,000 transistors within a single package and perform computational operations such as microprocessor chips, micro-controllers, basic PICs and calculators.

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 Ultra-Large Scale Integration or (ULSI); more than 1 million transistors – the big boys

that are used in computers CPUs, GPUs, video processors, micro-controllers, FPGAs and complex PICs. While the “ultra large scale” ULSI classification is less well used, another level of integration which represents the complexity of the Integrated Circuit is known as the System-on-Chip (SOC). Here the individual components such as the microprocessor, memory, peripherals, I/O logic etc, are all produced on a single piece of silicon and which represents a whole electronic system within one single chip, literally putting the word “integrated” into integrated circuit. These complete integrated chips which can contain up to 100 million individual siliconCMOS transistor gates within one single package are generally used in mobile phones, digital cameras, micro-controllers, PIC’s and robotic type applications.

3.7.2 TTL and CMOS Logic Levels There are a large variety of logic gate types in both the bipolar 7400 and the CMOS 4000 families of digital logic gates such as 74Lxx, 74LSxx, 74ALSxx, 74HCxx, 74HCTxx, 74ACTxx etc, with each one having its own distinct advantages and disadvantages compared to the other. The exact switching voltage required to produce either a logic “0” or a logic “1” depends upon the specific logic group or family. However, when using a standard +5 volt supply any TTL voltage input between 2.0v and 5v is considered to be a logic “1” or “HIGH” Fig. 3.7.1 while any voltage input below 0.8v is recognized as a logic “0” or “LOW”. The voltage region in between these two voltage levels either as an input or as an output is called the Indeterminate Region and operating within this region may cause the logic gate to produce a false output. The CMOS 4000 logic family uses different levels of voltages compared to the TTL types as they are designed using field effect transistors, or FET’s. In CMOS technology a logic “1” level operates between 3.0 and 18 volts and a logic “0” level is below 1.5 volts. Then the following table shows the difference between the logic levels of traditional TTL and CMOS logic gates. Logic Levels Device Type Logic 0 Logic 1 TTL 0 to 0.8v 2.0 to 5v (VCC) CMOS 0 to 1.5v 3.0 to 18v (VDD) Then from the above observations, we can define the ideal TTL digital logic gate as one that has a “LOW” level logic “0” of 0 volts (ground) and a “HIGH” level logic “1” of +5 volts and this can be demonstrated as follows:

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Ideal TTL Digital Logic Gate Voltage Levels;

The opening or closing of the switch produces either a logic level “1” or a logic level “0” with the resistor R being known as a “pull-up” resistor.

Fig. 3.7.2

3.7.3 DRL and DTL Logic Gates Simple digital logic gates can be made by combining transistors, diodes and resistors with a simple example of a Diode-Resistor Logic (DRL) AND gate and a Diode-Transistor Logic (DTL) NAND gate given below. The simple 2-input Diode-Resistor AND gate can be converted into a NAND gate by the addition of a single transistor inverting (NOT) stage. Using discrete components such as diodes, resistors and transistors to make digital logic gate circuits are not used in practical commercially available logic IC’s as these circuits suffer from propagation delay or gate delay and also power loss due to the pull-up resistors. Another disadvantage of diode-resistor logic is that there is no “Fanout” facility which is the 2-input AND Gate 2-input NAND Gate ability of a single output to Diode-Resistor Circuit Diode-Transistor circuit drive many inputs of the next Fig. 3.7.3 stages. Also this type of design does not turn fully “OFF” as a Logic “0” produces an output voltage of 0.6v (diode voltage drop), so the following TTL and CMOS circuit designs are used instead.

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3.7.4 TTL Logic Gates The simple Diode-Resistor AND gate above uses separate diodes for its inputs, one for each input. As a transistor is made up off two diode circuits connected together representing an NPN or a PNP device, the input diodes of the DTL circuit can be replaced by one single NPN transistor with multiple emitter inputs as shown in Fig. 3.7.4. As the NAND gate contains a single stage inverting NPN transistor circuit (TR2) an output logic level “1” at Q is only present when both the emitters of TR1 are connected to logic level “0” or ground allowing base current to pass through the PN junctions of the emitter and not the collector. The multiple emitters of TR1 are Fig. 3.7.4: 2-input NAND Gate connected as inputs thus producing a NAND gate function. In standard TTL logic gates, the transistors operate either completely in the “cut off” region, or else completely in the saturated region, i.e. Transistor as a Switch type operation. Fig. 3.7.5: TTL

TTL NOR and OR gates; In order to turn this NOR-gate circuit into an OR-gate, we would have to invert the output logic level with another transistor stage, just like we did with the NAND-to-AND gate example. Of course, totem-pole output stages are also possible in both NOR and OR TTL logic circuits.

NOR-gate

Transistors Q1 and Q2 are both arranged in the same manner that we’ve seen for transistor Q1 in all the other TTL circuits. Rather than functioning as amplifiers, Q 1 and Q2 are both being used as two-diode “steering” networks.

3.7.5 Emitter-Coupled Digital Logic Gates Emitter Coupled Logic (ECL) is another type of digital logic gate that uses bipolar transistor logic where the transistors are not operated in the saturation region, as they are with the standard TTL digital logic gate. Instead the input and output circuits are push-pull connected transistors with the supply voltage negative with respect to ground. This has the effect of increasing the speed of operation of the emitter coupled logic gates up to the Gigahertz range compared with the standard TTL types, but noise has a greater effect in ECL logic, because the unsaturated transistors operate within their active region and amplify as well as switch signals.

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3.7.6 CMOS Gate Circuitry CMOS NAND Gate The schematic diagram for a CMOS NAND gate is shown in Fig. 3.7.6, where transistors Q1 and Q3 resemble the series-connected complementary pair from the inverter circuit. Both are controlled by the same input signal (input A), the upper transistor turning off and the lower transistor turning on when the input is “high” (1), and vice versa. Notice also how transistors Q2 and Q4 are similarly controlled by the same input signal (input B), and how they will also exhibit the same on/off behavior for the same input logic levels. The upper transistors of both pairs (Q1 and Q2) have their source and drain terminals paralleled, while the lower transistors (Q3 and Q4) are series-connected. What this means is that the output will go “high” (1) if either top transistor saturates, and will go “low” (0) only if both lower transistors saturate.

O/P

Fig. 3.7.6: CMOS NAND gate

The following sequence of illustrations shows the behavior of this NAND gate for all four possibilities of input logic levels (00, 01, 10, and 11):

Fig. 3.7.7

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CMOS AND Gate As with the TTL NAND gate, the CMOS NAND gate circuit may be used as the starting point for the creation of an AND gate. All that needs to be added is another stage of transistors to invert the output signal.

Fig. 3.7.8: CMOS NAND Gate

Y

CMOS NOR Gate

As with the NAND gate, transistors Q1 and Q3 work as a complementary pair, as do transistors Q2 and Q4. Each pair is controlled by a single input signal. If either input A or input B are “high” (1), at least one of the lower transistors (Q3 or Q4) will be saturated, thus making the output “low” (0). Only in the event of both inputs being “low” (0) will both lower transistors be in cutoff mode and both upper transistors be saturated, the conditions necessary for the output to go “high” (1). This behavior, of course, defines the NOR logic function.

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Fig. 3.7.9: CMOS NOR Gate

A CMOS NOR gate circuit uses four MOSFETs just like the NAND gate, except that its transistors are differently arranged. Instead of two paralleled sourcing (upper) transistors connected to Vdd and two series-connected sinking (lower) transistors connected to ground, the NOR gate uses two seriesconnected sourcing transistors and two parallelconnected sinking transistors like that shown in Fig. 3.7.9.

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CMOS OR Gate

Fig.3.7.10: CMOS OR Gate

The OR function can be built up from the basic NOR gate with the addition of an inverter stage on the output as shown in Fig. 3.7.10. Since it appears that any gate possible to construct using TTL technology can be duplicated in CMOS, why do these two “families” of logic design still coexist? The answer is that both TTL and CMOS have their own unique advantages. First and foremost on the list of Y comparisons between TTL and CMOS is the issue of power consumption. In this measure of performance, CMOS is the unchallenged victor. Because the complementary P- and N-channel MOSFET pairs of a CMOS gate circuit are (ideally) never conducting at the same time, there is little or no current drawn by the circuit from the Vdd power supply except for what current is necessary to source current to a load. TTL, on the other hand, cannot function without some current drawn at all times, due to the biasing requirements of the bipolar transistors from which it is made. NPN RTL Inverter

3.7.7 Inverter Logic Gate Fig. 3.7.11

An inverter circuit outputs a voltage representing the opposite logic-level to its input. Its main function is to invert the input signal applied. If the applied input is low then the output becomes high and vice versa. Inverters can be constructed using a NPN TTL Inverter single NMOS transistor or a single PMOS transistor coupled with a resistor. Since this 'resistive-drain' approach uses only a single type of transistor, it can be fabricated at low cost. However, because current flows through the resistor in one of the two states, the resistive-drain configuration is disadvantaged for power consumption and processing speed. Alternatively, inverters can be Static CMOS inverter constructed using two NMOS inverter PMOS inverter complementary transistors in a CMOS configuration. This configuration greatly reduces power consumption since one of the

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transistors is always off in both logic states. Processing speed can also be improved due to the relatively low resistance compared to the NMOS-only or PMOS-only type devices. Inverters can also be constructed with bipolar junction transistors (BJT) in either resistor–transistor logic (RTL) or a transistor–transistor logic (TTL) configuration.

3.7.8 Static Logic Design of NAND, NOR, XOR and XNOR Gates A static CMOS gate is a combination of two networks, called the pull-up network (PUN) and the pull-down network (PDN). The function of the PUN is to provide a connection between the output and VDD anytime the output of the logic gate is meant to be 1 (based on the inputs). Similarly, the function of the PDN is to connect the output to VSS when the output of the logic gate is meant to be 0 (based on the inputs). The PUN and PDN networks are constructed in a mutually exclusive fashion such that, one and only one of these networks is conducting in the steady state.

Fig. 3.7.12: The circuit diagram for 2-input NAND, NOR, XOR and XNOR gates in CMOS static logic In order to design 2-input NAND, NOR, XOR and XNOR gates for equal rise and fall time, it is necessary to first design an inverter with equal rise and fall time. This involves compensating for the difference in electron and hole mobility. For silicon material, the electron mobility is about 2.5 to 3 times greater than the hole mobility. For a NAND gate, the worst case charging corresponds to an input combination where only one of the pMOS is ON and discharging takes place only when both nMOS’ are turned ON.

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3.8 Digital Logic Gates Implementation within VHDL VHDL is a hardware description language used to describe the behavior of an electronic circuit or system, from which the physical circuit or system can then be attained (implemented). VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language. The software that can be used includes MODEL-SIM and/or SIMULINK within the MATLAB. VHDL was the original and first hardware description language to be standardized by the Institute of Electrical and Electronics Engineers (IEEE), through the IEEE 1076 standard. An additional standard, the IEEE 1164, was later added to introduce a multi-valued logic system. VHDL is intended for circuit synthesis as well as circuit simulation. A fundamental motivation to use VHDL (or Verilog) is that VHDL is a standard, technology/ vendor independent language, and is therefore portable and reusable. The two main immediate applications of VHDL are in the field of Programmable Logic Devices (PLDs) (including CPLDs; Complex Programmable Logic Devices and FPGAs; Field Programmable Gate Arrays) and in the field of ASICs (Application Specific Integrated Circuits). Once the VHDL code has been written, it can be used either to implement the circuit in a programmable device (Altera, Xilinx, Atmel, etc.) or can be submitted to a foundry for fabrication of an ASIC chip. Currently, many complex commercial chips (microcontrollers, for example) are designed using such an approach. A final note regarding VHDL is that, contrary to regular computer programs which are sequential, its statements are inherently concurrent (parallel). For that reason, VHDL is usually referred to as a code rather than a program.

There are several EDA (Electronic Design Automation) tools available for circuit synthesis, implementation, and simulation using VHDL. Some tools (place and route, for example) are offered as part of a vendor’s design suite (e.g. Altera’s Quartus II, which allows the synthesis of VHDL code onto Altera’s CPLD/FPGA chips, or Xilinx’s ISE suite, for Xilinx’s CPLD/FPGA chips). Every VHDL design description consists of at least one entity / architecture pair, or one Fig. 3.8.1: Design Flow Block Diagram entity with multiple architectures. The entity section of the HDL design is used to declare the I/O ports of the circuit, while the description code resides within architecture portion. Standardized design

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libraries are typically used and are included prior to the entity declaration. This is accomplished by including the code "library ieee;" and "use ieee.std_logic_1164.all;".

3.8.1 NOT Gate Code library ieee; use ieee.std_logic_1164.all; Entity notGate Is Port ( A: in bit; B: out bit ); end notGate; Architecture notGateArch of notGate Is Begin B