Digital Logic Circuits 9789385449062, 9385449060

Table of contents :
TABLE OF CONTENTS
CHP 1-NUMBER SYSTEMAND CODES1.11.2
1.2.21.2.3
1.2.4
1.3
1.3.11.3.1.1
1.3.1.2
1.3.1.3
1.3.1.4
1.3.21.3.2.1
1.3.2.2
1.3.31.3.3.1
1.3.3.2
1.3.3.41.3.3.5
1.3.3.6
1.4
1.4.11.4.1.11.4.1.2
1.4.21.4.2.11.4.2.2
1.5
1.5.1.2
1.5.21.5.2.1
1.5.2.2
1.5.31.5.3.1
1.5.3.2
1.5.41.5.4.1
1.5.4.2
1.6
1.6.1
1.6.2
1.71.7.1
1.7.1.11.7.1.2
1.7.2.1
1.7.1.2.2
1.7.1.2.3
1.7.21.7.2.1
1.7.2.1.1
1.7.2.2
1.7.2.2.1
1.7.2.2.2
1.7.3
1.7.41.7.51.7.6
1.7.6.1
1.7.6.2
1.7.7
1.7.8
Solved Two Marks Questions
Review Questions
CHP2- MINIMIZATIONTECHNIQUES ANDLOGIC GATES2.1
2.2
2.3
2.3.1
2.3.32.3.3.12.3.3.2
2.4
2.4.1
2.4.2
2.4.3
2.4.3.1
2.4.3.2
2.4.3.3
2.5
2.5.12.5.2
2.5.32.5.4
2.5.5
2.5.6
2.5.7
2.5.8
2.5.9
2.6
2.72.7.1
2.7.2
2.82.8.1
2.8.2
2.92.9.1
2.9.2
2.9.3
2.9.3.1
2.9.3.2
2.9.4
2.9.4.1
2.9.4.2
Solved Two Marks Questions
Review Questions
CHP3 - COMBINATIONAL LOGIC CIRCUITS
3.13.2
3.3
3.43.4.1
3.4.2
3.53.5.1
3.5.2
3.63.6.1
3.6.2
3.6.3
3.6.4
3.7
3.83.8.1
3.8.2
3.9
3.10
3.113.11.1
3.11.2
3.11.3
3.12
3.133.13.1
3.13.2
3.13.3
3.13.4
3.13.5
3.13.6
3.13.7
3.13.8
3.14
3.14.1
3.14.2
3.14.3
3.14.4
3.15
Solved Two Marks Questions
Review Questions
CHP 4 - SEQUENTIAL CIRCUITS4.1
4.24.2.1
4.2.2
4.2.3
4.3
4.3.1
4.3.2
4.3.3
4.3.3.14.3.3.2
4.3.4
4.4
4.5
4.5.14.5.2
4.5.34.5.44.5.54.5.6
4.64.6.1
4.6.2
4.6.3
4.6.44.6.5
4.6.6
4.6.7
4.74.7.14.7.1.1
4.7.1.2
4.7.1.34.7.1.4
4.7.2
4.7.2.1
4.7.2.2
4.7.2.3
4.84.8.14.8.2
4.8.34.8.3.1
4.8.3.2
4.8.3.3
4.8.3.4
4.8.3.5
4.8.3.6
4.8.3.7
4.8.4
4.9
4.10
4.11
SOLVED TWO MARKS QUESTIONS
REVIEW QUESTIONS
CHP 5 -SYNCHRONOUS SEQUENTIAL CIRCUITS5.1
5.2
5.3
5.3.2
5.4
5.5
5.6
5.7
Solved Two Marks Questions
Review Questions
CHP 6 - ASYNCHRONOUS SEQUENTIAL CIRCUITS6.16.2
6.3
6.3.1
6.3.2
6.4
6.4.16.4.2
6.4.3
6.4.46.4.56.4.6
6.56.5.1
6.5.2
6.5.2.16.5.2.2
6.5.2.2.1
6.5.36.5.3.1
6.5.3.1.1
6.5.3.1.2
6.5.3.2
6.6
6.7
6.8
6.96.9.16.9.1.1
6.9.1.26.9.1.3
6.9.2
Solved Two Marks Questions
Review Questions
CHP 7 - MEMORY DEVICES7.1
7.2
7.2.17.2.2
7.37.4
7.4.17.4.1.17.4.1.2
7.4.1.37.4.1.47.4.1.5
7.5
7.5.1
7.5.2
7.67.6.1
7.6.2
7.77.7.1
7.7.2
7.7.3
7.87.97.10
7.117.11.1
7.11.27.12
7.12.1
7.12.2
7.13
7.13.1
7.13.2
7.13.3
7.147.14.1
7.14.2
7.14.3
7.15
7.15.17.15.27.15.2.17.15.2.2
Solved Two Marks Questions
REVIEW QUESTIONS
CHP 8 -VHDL8.18.2
8.2.18.2.28.2.38.2.48.2.5
8.2.68.3
8.3.1
8.3.2
8.3.3
8.3.3.1
8.3.3.2
8.3.3.38.3.3.4
8.3.3.5
8.3.3.6
8.48.4.18.4.28.4.38.4.3.1
8.4.3.28.4.3.38.4.3.4
8.4.48.4.4.1
8.58.5.18.5.28.5.38.5.4
8.5.58.5.68.68.6.1
8.6.28.6.38.6.4
8.78.7.18.7.28.88.8.1
8.8.28.98.9.1
8.10
8.11
Solved Two Marks Questions
Review Questions
CHP 9 - DIGITAL LOGIC FAMILIES9.1
9.29.2.1
9.2.2
9.39.3.1
9.3.2
9.3.39.3.4
9.3.5
9.49.4.1
9.4.2
9.5
9.6
9.7
9.7.1
9.7.2
9.7.39.7.3.1
9.7.3.2
9.8
9.9
9.10
9.10.1
9.10.2
9.10.3
9.119.11.1
9.11.2
9.11.3
9.11.4
9.11.5
9.129.12.19.12.29.12.39.12.4
9.12.59.12.6
9.139.14
Solved Two Marks Questions
Review Questions

Citation preview

DIGITAL LOGIC CIRCUITS (For B.E III semester EEE/EIE)

As per the new syllabus of Anna University Regulation R-2013

Dr. P. KANNAN M.E., Ph.D., Professor & Head

M.SARASWATHI M.E., Associate Professor

C. Ramesh Kumar M.E., (Ph.D.,) Associate Professor Department of Electronics and Communication Engineering Panimalar Engineering College Chennai -600123

SREE KAMALAMANI PUBLICATIONS CHENNAI

SREE KAMALAMANI PUBLICATIONS Publised by SREE KAMALAMANI PUBLICATIONS. New No. AJ. 21, old No. AJ. 52, Plot No. 2614, 4th Cross st., 9th Main Road, Anna Nagar -600 040, Chennai, Tamilnadu, India Landline: 91-044-42170813, Mobile: 91-9840795803 Email: [email protected] Copyright © 2018, Dr.P. Kannan, Mrs. M. Saraswathi, Mr. C. Ramesh kumar Published by Sree kamalamani Publications All rights reserved to the publisher. The right of Dr. P. Kannan and M. Saraswathi to be identified as the authors of this work has been asserted in accordance with the Copyright, Act 2013 amended from the 1957 act No part of this publication may be reproduced or distributed in any form or by any means, electronic, mechanical, photocopying, recording or otherwise or stored in a database or retrieval system without the prior written permission of the publishers. Permissions may be sought directly from the publisher from the above said address This edition can be exported from India only by the Publishers, Sree Kamalamani Publications. ISBN (13 digits): 978-93-85449-06-2

Information contained in this work has been obtained by Sree Kamalamani Publications, from sources believed to be reliable. However, neither Sree Kamalamani Publications nor its authors guarantee the accuracy or completeness of any information published herein, and neither; Sree Kamalamani nor its authors shall be responsible for any errors, omissions, or damages arising out of use of this information. This work is published with the understanding that Sree kamalamani publications and its authors are supplying information but are not attempting to render engineering or other professional services. if such services are required, the assistance of an appropriate professional should be sought.

Typeset & Coverpage Designs : Sree Kamalamani PublicationS New No. AJ. 21, Old No. AJ. 52, Plot No 2614, 9th Main, 4th cross st., Anna Nagar-600 040 Chennai, Tamilnadu, India.

EE8351

DIGITAL LOGIC CIRCUITS

LT P C 3104

UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES Review of number systems, binary codes, error detection and correction codes (Parity and Hamming code0- Digital Logic Families ,comparison of RTL, DTL, TTL, ECL and MOS families operation, characteristics of digital logic family. UNIT II COMBINATIONAL CIRCUITS Combinational logic - representation of logic functions-SOP and POS forms, K-map representations minimization using K maps - simplification and implementation of combinational logic - multiplexers and demultiplexers - code converters, adders, subtractors. UNIT III SYNCHRONOUS SEQUENTIAL CIRCUITS 9 Sequential logic- SR, JK, D and T flip flops - level triggering and edge triggering - counters - asynchronous and synchronous type - Modulo counters - Shift registers - design of synchronous sequential circuits – Moore and Melay models- Counters, state diagram; state reduction; state assignment. UNIT IV ASYNCHRONOUS SEQUENTIAL CIRCUITS AND PROGRAMMABLE LOGIC DEVICES Asynchronous sequential logic circuits-Transition table, flow table-race conditions, hazards &errors in digital circuits; analysis of asynchronous sequential logic circuits-introduction to Programmable Logic Devices: PROM – PLA –PAL.36 UNIT V VHDL RTL Design – combinational logic – Sequential circuit – Operators – Introduction to Packages –Subprograms – Test bench. (Simulation /Tutorial Examples: adders, counters, flipflops, FSM, Multiplexers /Demultiplexers).

PREFACE OF THE BOOK This book is extensively designed for the third semester EEE/EIE students as per Anna university syllabus R-2017. The following chapters constitute the following units

Chapter Chapter Chapter Chapter Chapter

1, 9 covers 2 and 3 covers 4 and 5 covers 6 and 7 covers 8 VHDL

:-Unit 1 :-Unit 2 :-Unit 3 :- Unit 4 :-Unit 5

CHAPTER 1: Introduces the Number System, binary arithmetic and codes. CHAPTER 2: Deals with Boolean algebra, simplification using Boolean theorems, K-map method , Quine McCluskey method, logic gates, implementation of switching function using basic Logical Gates and Universal Gates. CHAPTER 3: Describes the combinational circuits like Adder, Subtractor, Multiplier, Divider, magnitude comparator, encoder, decoder, code converters, Multiplexer and Demultiplexer. CHAPTER 4: Describes with Latches, Flip-Flops, Registers and Counters CHAPTER 5: Concentrates on the Analysis as well as design of synchronous sequential circuits, Design of synchronous counters, sequence generator and Sequence detector CHAPTER 6: Concentrates the Design as well as Analysis of Fundamental Mode circuits, Pulse mode Circuits, Hazard Free Circuits, ASM Chart and Design of Asynchronous counters. CHAPTER 7: Discussion on memory devices which includes ROM, RAM, PLA, PAL, Sequential logic devices and ASIC. CHAPTER 8: The chapter concentrates on the design, fundamental building blocks, Data types, operates, subprograms, packagaes, compilation process used for VHDL. It discusses on Finite state machine as an important tool for designing logic level state machines. The chapter also discusses register transform level designing and test benches usage in stimulation of the state logic machines CHAPTER 9: Concentrate on the comparison, operation and characteristics of RTL, DTL, TTL, ECL and MOS families. We have taken enough care to present the definitions and statements of basic laws and theorems, problems with simple steps to make the students familiar with the fundamentals of Digital Design.

‡‡ i

Table of Contents

TABLE OF CONTENTS CHAPTER I

NUMBER SYSTEM AND CODES

1.1-1.78

1.1

Introduction

1.2

1.2

Review of Number System

1.2

1.2.1

Decimal Number System

1.3

1.2.2

Binary Number System

1.4

1.2.3

Octal Number System

1.4

1.2.4

Hexadecimal Number System

1.5

Number Base System

1.6

Conversion from any Radix (r’s) to Decimal number system

1.7

1.3.1.1

Binary to Decimal Number System

1.7

1.3.1.2

Octal to Decimal Number system

1.7

1.3.1.3

Hexadecimal System

to

Decimal

number

1.8

1.3.1.4

Other base System

to

Decimal

Number

1.10

Conversion of Decimal number system to any radix (r) system

1.11

1.3.2.1

Conversion of Decimal integer part to any radix system

1.11

1.3.2.2

Conversion of Decimal fraction number to any radix system

1.13

Special Conversion Method

1.18

1.3.3.1

Binary to Octal conversion

1.18

1.3.3.2

Octal to Binary conversion

1.19

1.3.3.3

Binary to Hexadecimal conversion

1.19

1.3.3.4

Hexadecimal to Binary conversion

1.20

1.3.3.5

Octal to Hexadecimal conversion

1.20

1.3 1.3.1

1.3.2

1.3.3

1.3.3.6

Hexadecimal to Octal conversion

1.21

Complements

1.25

Diminished Radix complement (r-1)’s Complement

1.26

1.4.1.1

One’s (1’s) Complement

1.26

1.4.1.2

Nine’s (9’s) Complement

1.26

Radix (r’s) Complement

1.27

1.4.2.1

Two’s (2’s) Complement

1.27

1.4.2.2

Ten’s (10’s) Complement

1.27

1.4 1.4.1

1.4.2

‡‡ ii

DIGITAL LOGIC CIRCUITS 1.5

Binary subtraction Complements 1.5.1

using

1.28

Subtraction using 1’s complement

1.28

1.5.1.1

Subtraction of Smaller Number (B) from Larger Number (A): A-B

1.28

1.5.1.2

Subtraction of Larger Number (A) from Smaller Number (B): B-A

1.30

1.5.2

Subtraction using 2’s complement

1.31

1.5.2.1

Subtraction of Smaller Number (B) from larger number (A): A-B

1.32

1.5.2.2

Subtraction of larger number (A) from smaller number (B): B-A

1.32

1.5.3

Subtraction using 9’s Complement

1.34

1.5.3.1

Subtraction of Smaller number (B) from larger number (A): A-B

1.34

1.5.3.2

Subtraction of larger number (A) from smaller number (B): B-A

1.35

Subtraction using 10’s Complement

1.36

1.5.4.1

Subtraction of Smaller number (B) from larger number (A): A-B

1.36

1.5.4.2

Subtraction of larger number (A) from smaller number (B): B-A

1.37

Signed Binary numbers

1.38

Signed Binary Arithmetic

1.41

1.5.4

1.6 1.6.1 1.6.2

Signed Binary Subtraction

1.44

Binary codes

1.45

Weighted Binary codes

1.45

1.7.1.1

Binary codes

1.46

1.7.1.2

Binary coded decimal (BCD) code

1.46

1.7 1.7.1

1.7.1.2.1 BCD addtion 1.7.1.2.2 BCD Subtraction complement 1.7.1.2.3 BCD Subtraction complement 1.7.2 1.7.2.1

1.48 using using

9’s

1.50

10’s

1.51

Non-Weighted codes

1.52

Excess-3 Code

1.53

1.7.2.1.1

Excess-3 Addition

1.54

1.7.2.1.2

Excess-3 Subtraction

1.54

1.7.2.2

Gray Code

1.56

1.7.2.2.1

Conversion of Gray Code to Binary code

1.58

1.7.2.2.2

Conversion from Binary to Gray Code

1.58

‡‡ iii

Table of Contents

1.7.3

Self complementing code

1.59

1.7.4

Reflective codes

1.60

1.7.5

Sequential Codes

1.60

1.7.6

Alpha Numeric Codes

1.60

1.7.6.1

American Standard code for Information and Interchange (ASCII)

1.61

1.7.6.2

Extended Binary coded Interchange code (EBCDIC)

1.62

Decimal

1.7.7

Error Detection codes

1.7.8

Error Correcting codes

1.65

Solved two marks

1.681.75

Review questions

1.761.78

CHAPTER II

MINIMIZATION TECHNIQUES AND LOGIC GATES

1.64

2.1-2.144

2.1

Introduction

2.2

2.2

Digital Logic Gates

2.4

2.3

Boolean Algebra

2.9

2.3.1

Rules in Boolean Algebra

2.11

2.3.2

Postulates/Rules

2.11

2.3.3

Laws and Theorems

2.12

2.3.3.1

Basic Laws

2.12

2.3.3.2

Basic Theorems

2.13

Boolean Function

2.14

2.4.1

Algebraic Function

2.14

2.4.2

Complement of function

2.27

2.4.3

Canonical and Standard forms

2.31

2.4.3.1

Canonical Sum of Product Expression

2.34

2.4.3.2

Canonical Product of Sum Expression

2.36

2.4.3.3

Conversion between Canonical Form

2.38

2.4

2.5

K-map Method

2.42

2.5.1

Rules for Simplification of Boolean function in SOP form using K-map

2.43

2.5.2

Two-Variable K-map

2.43

2.5.3

Three Variable K-map

2.44

2.5.4

Four Variable K-map

2.45

2.5.5

Five Variable K-map

2.45

2.5.6

Six Variable K-map

2.46

‡‡ iv

DIGITAL LOGIC CIRCUITS 2.5.7

Essential Prime and Prime Implicants

2.63

2.5.8

Don’t care condition

2.67

2.5.9

Rules for Simplification of Boolean function in POS form using K-map

2.69

Quine-Mc-Cluskey Tabulation method

2.73

2.6 2.7

Method

(or)

Universal gates

2.100

2.7.1

Realization of other logic gates using NAND gate

2.100

2.7.2

Realization of other logic functions using NOR gate

gate

2.101

Conversion of AND/OR/NOT logic to NAND/NOR logic

2.103

2.8.1

NAND Logic Implementation

2.103

2.8.2

NOR Logic Implementation

2.109

2.8

2.9

Two Level Implementation

2.113

2.9.1

Two Level NAND Implementation

2.113

2.9.2

Two Level NOR Implementation

2.118

2.9.3

Other Two Level Implementation

2.123

2.9.3.1

AND-OR-INVERT Implementation

2.124

2.9.3.2

OR-AND-INVERT Implementation

2.125

Multi- Level Implementation

2.127

Multi Level NAND Implementation

2.128

2.9.4 2.9.4.1 2.9.4.2

CHAPTER III

Multi Level NOR Implementation

2.131

Solved Two Marks questions

2.1342.139

Review Questions

2.1402.144

COMBINATIONAL LOGIC CIRCUITS

3.1-3.106

3.1

Introduction

3.2

3.2

Analysis procedure for combinational circuit

3.2

3.3

Design procedure of combinational circuit

3.4

3.4

Binary adder

3.6

3.4.1

Half adder

3.6

3.4.2

Full adder

3.8

Binary Subtractor

3.11

3.5.1

Half Subtractor

3.11

3.5

‡‡ v

3.5.2

Table of Contents Full Subtractor

3.12

n-Bit Binary adder

3.15

3.6.1

Four Bit Binary Adder

3.15

3.6.2

Four Bit Binary Subtractor

3.16

3.6.3

Binary Adder/Subtractor

3.17

3.6.4

3.6

Look Ahead Carry Adder/Fast Adder

3.18

3.7

BCD Adder

3.24

3.8

BCD Subtractor

3.26

3.8.1

BCD Subtractor complement

3.8.2

BCD Subtractor complement

using using

9’s

3.26

10’s

3.28

3.9

Excess-3 Adder

3.29

3.10

Excess-3 Subtractor

3.30

3.11

Binary Multiplier

3.31

3.11.1

Two by Two Binary Multiplier

3.31

3.11.2

Four Bit Binary Multiplier using Shift method

3.32

3.11.3

Four by Four Binary Multiplier

3.33

Binary Divider

3.35

3.12 3.13

Code conversion

3.37

3.13.1

Binary to BCD code converter

3.37

3.13.2

BCD to Binary code converter

3.39

3.13.3

BCD to Excess -3 code converter

3.43

3.13.4

Excess-3 Code to BCD code converter

3.45

3.13.5

Binary to Gray code converter

3.47

3.13.6

Gray code to Binary code converter

3.48

3.13.7

BCD to Gray code converter

3.50

3.13.8

Gray to BCD code converter

3.52

Binary Comparator/Magnitude Comparator

3.53

3.14.1

One Bit Magnitude comparator

3.55

3.14.2

Two Bit Magnitude comparator

3.57

3.14.3

Three Bit Magnitude comparator

3.60

3.14.4

Four Bit Magnitude comparator

3.61

Decoder

3.63

3.15.1

Three to Eight Line Decoder

3.64

3.15.2

Construction of Decoder with NAND

3.65

3.15.3

Construction of a 4 × 16 using two 3 × 8 decoders

3.66

3.14

3.15

‡‡ vi

DIGITAL LOGIC CIRCUITS 3.15.4

Construction of a 4 × 16 Line Decoder from 2 × 4 line decoder

3.67

3.15.5

Design 5 × 32 Line Decoder using One 2 × 4 and Four 3 × 8 line Decoder IC’s

3.68

3.15.6

Design of BCD to seven segment Decoder with common cathode

3.69

Encoder

3.73

3.16.1

Decimal to BCD Encoder

3.74

3.16.2

Octal to Binary Encoder

3.75

3.16.3

Priority Encoder

3.76

Parity generator and checker

3.78

3.17.1

Even Parity Generator

3.78

3.17.2

Even Parity Checker

3.80

Multiplexer

3.81

3.18.1

Two to One line Multiplexer

3.82

3.18.2

Four to One line Multiplexer

3.83

3.18.3

Quadruple 2 to 1 Line Multiplexer

3.85

3.18.4

Boolean function Implementation

3.85

Demultiplexer

3.91

3.19.1

One to Four Demultiplexer

3.92

3.19.2

Boolean function Implementation

3.93

3.16

3.17

3.18

3.19

CHAPTER IV

Solved Two Marks Questions

3.963.103

Review Questions

3.1043.106

SEQUENTIAL CIRCUITS

4.1

4.1-4.76

Introduction

4.2

Classification of Sequential Logics

4.3

Latches

4.4

4.2.1

SR Latch using NOR Gate

4.4

4.2.2

Gated SR latch (using NAND)

4.7

4.2.3

D-Latch

4.10

Synchronous Flip-flops

4.12

4.3.1

Clocked SR Flip-flops

4.13

4.3.2

D Flip-flop

4.16

4.3.3

Clocked JK Flip-flop

4.20

Race Condition or Race Hazard

4.23

4.1.1 4.2

4.3

4.3.3.1

‡‡ vii

Table of Contents 4.3.3.2

4.3.4

Race around condition in JK Flip-flop

4.23

T Flip-flops

4.27

4.4

Asynchronous Flip-flops

4.30

4.5

Characteristics of Flip-flops

4.31

4.5.1

Propagation Delay

4.32

4.5.2

Set up time

4.32

4.5.3

Hold-up time

4.33

4.5.4

Maximum clock Frequency

4.33

4.5.5

Asynchronous active pulse width

4.33

4.5.6

Clock High pulse time and Low pulse time

4.33

Realization of Flip-flop

4.34

4.6 4.6.1

SR Flip-flop to D Flip-flop

4.34

4.6.2

SR Flip-flop to JK Flip-flop

4.35

4.6.3

SR Flip-flop to T Flip-flop

4.36

4.6.4

JK Flip-flop to T Flip-flop

4.37

4.6.5

JK Flip-flop to D Flip-flop

4.38

4.6.6

D Flip-flop to T Flip-flop

4.38

4.6.7

T Flip-flop to D Flip-flop

4.39

Counters

4.40

4.7.1

Synchronous counters

4.40

4.7 4.7.1.1

Two bit counter

4.7.1.2

Three bit synchronous up counter

4.41

4.7.1.3

Four bit synchronous Binary up counter

4.43

Asynchronous counter

4.44

4.7.2

synchronous

Bit

up

Asynchronous

4.40

4.7.2.1

MOD-4 (or) counter

4.7.2.2

Three bit (or) MOD-8 Ripple counter

4.46

4.7.2.3

Propagation Delay

4.49

4.8

2

binary

4.45

Registers

4.49

Buffer Registers

4.49

4.8.2

Shift Registers

4.49

4.8.3

Modes of Operations

4.50

4.8.3.1

Serial In Serial Out Shift Registers (SISO)

4.50

4.8.3.2

Serial In Parallel Out Shift Registers (SIPO)

4.54

4.8.3.3

Parallel In Parallel Out Shift Registers (PIPO)

4.55

4.8.1

‡‡ viii

DIGITAL LOGIC CIRCUITS

4.8.4

4.8.3.4

Parallel In Serial Out Shift Registers (PISO)

4.56

4.8.3.5

Bidirectional Shift Register

4.57

4.8.3.6

Bidirectional Parallel load

4.8.3.7

Universal shift Register

4.60

Shift

Register

with

4.58

Application of Shift Registers

4.60

4.9

Serial Adder

4.64

4.10

Serial Subtraction complement

4.11

Four bit Serial Adder/Subtractor

4.67

Solved Two Marks Questions

4.694.74

Review Question

4.754.76

CHAPTER V

using

2’s

SYNCHRONOUS SEQUENTIAL CIRCUITS

4.66

5.1-5.108

5.1

Introduction

5.2

5.2

Analysis of synchronous sequential circuits

5.5

5.3

Design of synchronous sequential circuit

5.18

5.3.1

State Reduction Algorithm

5.18

5.3.2

State Assignment

5.19

5.4

Design of counter

5.45

5.5

Self correcting circuit

5.68

5.6

Sequence generator using counter

5.73

5.7

Sequence detector

5.80

CHAPTER VI

Solved Two Marks questions

5.995.103

Review Questions

5.1045.108

ASYNCHRONOUS SEQUENTIAL CIRCUITS

6.1

Introduction

6.2

Block diagram of sequential circuit

6.3

Analysis of fundamental sequential circuit

6.1-6.96 6.2

asynchronous mode

6.2 6.3

6.3.1

Circuit without latches

6.4

6.3.2

Circuit with latches

6.5

‡‡ ix

Table of Contents

6.4

Design of fundamental sequential circuit

mode

6.17

6.4.1

Primitive Flow Table

6.18

6.4.2

Reduction of Primitive Flow Table

6.18

6.4.3

State Assignment

6.19

6.4.4

Transition Table

6.20

6.4.5

K-map Simplification

6.20

6.4.6

Logic diagram

6.20

Problems in asynchronous sequential circuits

6.21

6.5.1

Cycles

6.21

6.5.2

Races

6.22

6.5.2.1

Non-Critical Races

6.23

6.5.2.2

Critical Races

6.23

6.5

6.5.2.2.1

Critical Race Free State assignment

6.24

Hazards

6.27

Hazards in combinational circuits

6.27

6.5.3.1.1

Static Hazard

6.27

6.5.3.1.2

Dynamic Hazard

6.31

Hazards in Sequential circuits

6.32

6.6

Analysis of pulse mode sequential circuit

6.58

6.7

Design of Pulse mode circuits

6.63

6.8

Design of Divide-by-N-ripple counter

6.71

6.5.3 6.5.3.1

6.5.3.2

6.9 6.9.1 6.9.1.1 6.9.1.2 6.9.2

CHAPTER VII 7.1 7.2

7.3

Algorithmic state machines chart

6.77

ASM Chart Notations

6.77

State Box

6.77

Decision Box

6.78

Comparison of ASM Chart and State diagram

6.79

Solved Two marks Questions

6.846.91

Review Question

6.926.96

MEMORY DEVICES

7.1-7.62

Introduction

7.2

Basic Memory Operation

7.3

7.2.2

Write Operation

7.4

7.2.3

Read Operation

7.4

Classification of Memory

7.5

‡‡ x

DIGITAL LOGIC CIRCUITS 7.4

Read Only Memory (ROM)

7.5

Types of ROMs

7.6

7.4.1.1

Masked ROM

7.6

7.4.1.2

Programmable ROM

7.6

7.4.1.3

Erasable PROM (EPROM)

7.7

7.4.1.4

Electrically PROM)

7.4.1.5

Flash Memory

7.7

7.4.1

7.5

Erasable

PROM

(EE-

7.7

Random Access Memory (RAM)

7.8

7.5.1

Write Operation

7.9

7.5.2

Read Operation

7.10

Types of RAM

7.11

7.6.1

Static RAM

7.11

7.6.2

Dynamic RAM

7.14

Memory Decoding

7.17

7.7.1

Logical construction of 4 × 4 RAM

7.17

7.7.2

Coincident Decoding

7.18

7.7.3

Address Multiplexing

7.19

7.8

Comparison between RAM and ROM

7.21

7.9

Comparison DRAM

7.21

7.10

Comparison of types of memories

7.21

7.6

7.7

7.11

between

SRAM

and

Memory Expansion

7.22

7.11.1

Word length Expansion

7.22

7.11.2

Word Capacity Expansion

7.23

Programmable Logic devices

7.23

7.12.1

The OR Array

7.24

7.12.2

The AND array

7.25

Types of Programmable logic devices

7.26

7.12

7.13 7.13.1

Programmable ROM

7.27

7.13.2

Programmable Logic array

7.30

7.13.3

Programmable Array logic

7.40

7.14

Sequential Programmable devices

7.48

7.14.1

Sequential Programmable device(SPLD)

Logic

7.48

7.14.2

Complex Programmable Logic Devices (CPLD)

7.49

7.14.3

Field Programmable gate array (FPGA)

7.50

Application of Specific circuits (ASIC’s)

7.52

7.15 7.15.1

Full custom ASIC’s

integrated

7.53

‡‡ xi

Table of Contents

7.15.2

CHAPTER VIII

7.53

Standard cell-based ASIC’s

7.53

7.15.2.2

Gate array-based ASIC’s

7.53

Solved Two Mark questions

7.557.59

Review Questions

7.607.62

VHDL

8.1 8.2

8.1-8.52 Introduction

8.2

Design flow

8.2

8.2.1

Definition of Design requirements

8.3

8.2.2

Description of the design in VHDL

8.3

8.2.3

Stimulation of source code

8.3

8.2.4

Synthesizing, Optimizing and fitting the design

8.3

8.2.5

Stimulation of post layout design model

8.3

8.2.6

Download the program on the device

8.4

Fundamental Building blocks

8.4

8.3.1

Library declaration

8.5

8.3.2

Entity

8.6

8.3.3

Architecture body

8.7

8.3.3.1

Modelling styles

8.8

8.3.3.2

Basic structure of VHDL

8.9

8.3.3.3

Data flow modelling

8.11

8.3.3.5

Structural Modelling

8.13

8.3.3.6

Comparison of data flow behavioural and structural modelling

8.13

8.3

8.4

Data types

8.33

8.4.1

File

8.33

8.4.2

Access type

8.33

8.4.3

Scalar Type

8.33

8.4.3.1

Enumerated type

8.33

8.4.3.2

Real type

8.34

8.4.3.3

Integer type

8.34

8.4.3.4 8.4.4 8.5

Semi Custom ASIC’s 7.15.2.1

Physical type

8.34

Composite type

8.35

Operators

8.36

‡‡ xii

DIGITAL LOGIC CIRCUITS 8.5.1

Logical Operators

8.36

8.5.2

Relational Operators

8.36

8.5.3

Shift Operators

8.36

8.5.4

Adding Operators

8.36

8.5.5

Multiplying Operators

8.37

8.5.6

Miscellaneous Operators

8.37

Subprogram

8.37

8.6.1

The subprogram specification

8.37

8.6.2

Subprogram-item-declaration

8.38

8.6.3

Subprogram-statement

8.38

8.6.4

Subprogram name

8.38

Packages

8.41

8.7.1

Packages Declaration

8.41

8.7.2

Package Body

8.41

Compilation Body

8.41

8.8.1

Design file

8.41

8.8.2

Design library

8.42

Finite state machine

8.42

8.6

8.7

8.8

8.9

Design of FSM

8.42

8.10

8.9.1

Register Transform level (RTL) Design

8.46

8.11

Test benches

8.53

Solved Two marks

8.56

Review Questions

8.62

CHAPTER IX

9.2-9.60

Digital Logic Families

9.1

Introduction

9.2

9.2

Classification of logic families

9.3

9.2.1

Classification integration

9.2.2

Classification based on polarity

9.4

Fundamental characteristics of logic families

9.5

9.3.1

Fan in

9.6

9.3.2

Fan Out

9.6

9.3.3

Power dissipation

9.7

9.3.4

Noise margin

9.8

Switching circuits

9.9

Semiconductor diode

9.9

9.3

9.4 9.4.1

based

on

level

of

9.3

‡‡ xiii

Table of Contents Bipolar Junction Transistor

9.10

9.5

9.4.2

Resistor-Transistor logic (RTL)

9.11

9.6

Diode logic (DTL) circuit

9.13

9.7

Transistor -Transistor logic (TTL)

9.14

9.7.1

Open-Collector output gate

9.15

9.7.2

Totem pole output of TTL circuit

9.18

9.7.3

Three state gate

9.20

9.7.3.1

Tri-state gate

9.20

9.7.3.2

Tri-state inverter

9.22

9.8

Schottky TTL gate

9.25

9.9

Emitter coupled logic (ECL)

9.26

9.10

MOS Transistors

9.29

9.10.1

NMOS inverter logic

9.30

9.10.2

NMOS NAND Logic

9.31

9.10.3

NMOS NOR Logic

9.32

9.10.4

NMOS NOR Logic

9.32

Complementary (CMOS)

9.11

MOS

Transistors

9.34

9.11.1

CMOS inverter Logic

9.34

9.11.2

CMOS NAND Logic

9.35

9.11.3

CMOS NOR Logic

9.37

9.11.4

CMOS inverter as two switches

9.38

9.11.5

CMOS compared to TTL

9.39

Characteristics of Logic Families

9.40

9.12.1

Characteristics of RTL

9.40

9.12.2

Characteristics of DTL

9.40

9.12.3

Characteristics of TTL

9.40

9.12.4

Characteristics of ECL

9.40

9.12.5

Characteristics of NMOS

9.41

9.12.6

Characteristics of CMOS

9.41

9.13

Comparision between of ECL, TTL, CMOS

9.42

9.14

Logic Family Comparison

9.42

Solved Two Marks Questions

9.489.57

Review Questions

9.589.60

9.12

‡‡ 1.1

NUMBER SYSTEM

After reading this chapter you should be able to:  Identify number systems other than decimal.  Determine the weighing factor for each digit position in each of the decimal, binary, octal, and hexadecimal number system.  Convert the number given in one number system into its equivalent form in any other system.  Perform arithmetic calculations.  Manipulate complement numbers.  Describe the classification of binary codes.

‡‡ 1.2

NUMBER SYSTEM AND CODES

t

NUMBER SYSTEM AND CODES

Chapter

1

1.1 INTRODUCTION

Digital is a magic world, where creation, imagination and applications have no bounds and consequently, new vistas have opened up for humans to challenge. The number systems provide the basis for all operations in information processing systems. The early computers were designed with the decimal number system. To represent one decimal digit, 10 vacuum tubes were used; therefore the system design turned complex and was not very efficient to implement. In 1945, John Von Neumann suggested that the numbering system used in computers should deal with the basic electronic states of ON and OFF which we call as binary number system. The computers operate in binary and communicate to us in decimal. A special program was developed to convert decimal to binary on the input and binary to decimal on the output. Normally computers require code converters to represent decimal numbers in terms of binary digits and vice-versa. This number system is called Binary Coded Decimal (BCD) systems. Coding of information is a basic consideration in the use of a digital system. Codes are required for decimal numbers, the letters of the alphabet and a variety of other well used symbols such as = ?, etc., There are variety of other codes available such as Excess-3 code, gray code etc., In practice the most widely used code is 8421 weighted code which is referred as natural Binary Coded Decimal.



1.2 REVIEW OF NUMBER SYSTEM Number system is nothing but set of values used to represent quantity. In digital system, there are many number systems but most commonly used number systems are decimal, binary, octal and hexadecimal systems. The decimal system is the most familiar number system that we commonly use in day to day life and any number system can be differentiated by the radix or base.

‡‡ 1.3

In general any number system with the base or radix 'r', we start counting the digits from 0 to r-1 and the number can be represented as



N = an r n + an −1r n −1 + ............a1r 1 + a 0r 0 where, n =0,1,2,3... (r − 1) ... (1.1) r = base or radix of the system a = number of digiits having values between 0 and r-1

The equation (1.1) is represented only for integer values of any radix system. To represent the number with the integer and fractional values, the equation (1.1) can be written as ... (1.2)

N = a −1r −1 + a −2r −2 + .......a.n +1r −n +1 + a −n r −n

To understand the operations in digital computers it is necessary to study the basic classification of number system. The number system can be classified into four major systems as shown in figure 1.1. They are • Decimal number system • Binary number system • Octal number system • Hexa decimal number system Number system

Decimal number

Hexadecimal number

Binary number

Octal number

Figure 1.1 Classification of Number system

1.2.1 Decimal Number System

The

invention

of

Decimal

number

system

is

the

most

important factor in the development of science and technology. The decimal number system uses positional number representation, which means that the value of each digit is determined by its position in a number. The base, also called as the radix of a number system represents the number of symbols that a system contains. The decimal

‡‡ 1.4

NUMBER SYSTEM AND CODES

system has ten symbols 0,1,2,3,4,5,6,7,8,9. In other words, it has a base of 10. Each position in the decimal system is ten times more significant than the previous position. The numeric value of a decimal number is determined by multiplying each digit of the number by the value of the position in which the digit appears and then adding the products. Thus the number 5327 is interpreted as 5 x 1000 + 3 x 100 + 2 x 10 + 7 x 1 = 5327 Here 7 is the least significant digit (LSD) and 5 is the most significant digit (MSD). 1.2.2 Binary Number System The binary number of the radix is 2. As r = 2 only two digits are needed and they are '0' and '1'. Like decimal system, binary is also positional system except that each bit position corresponds to a power of 2 instead of power of 10. In digital systems, the binary number systems and other number systems are closely related and are used almost exclusively. Hence, digital systems often provide conversion between decimal and binary numbers. The decimal value of a binary number can be formed by multiplying each power of 2 by either '1' or '0' followed by adding the values together. For example, the decimal equivalent of the binary number 101010 is interpreted as N = (101010)2 = 1 x 25 + 0 x 24 + 1 x 23 + 0 x 22 + 1 x 21 + 0 x 20 = (42)10 1.2.3 Octal Number system Digital systems operate only on binary numbers. Since binary numbers are often very long, two shorthand notations octal and hexadecimal are used for representing binary numbers. Octal system use a base or radix of 8. Therefore they have digits from 0 to 7. As in the decimal and binary systems, the positional value of each digit in a sequence of octal numbers is fixed. Each position in an octal number is a power of 8 and each position is 8 times more significant than the previous section. For example, the decimal equivalent of the octal number 342 is interpreted N = (342)8 = 3 x 82 + 4 x 81 + 2 x 80 =(226)10

‡‡ 1.5

1.2.4 Hexadecimal Number System Hexadecimal number system has a base of 16, that is it has 16 symbols. The decimal digits 0 to 9 are used as the first 10 digits as in the decimal system followed by the letters A, B, C, D, E and F which represent the value 10, 11,12,13,14 and 15 respectively. For example, the decimal equivalent of hexadecimal number 7FA is interpreted as N = (7FA)16 = 7 x 162 +15 x 161 + 10 x 160 = (2042)10 Table 1.1 illustrates the comparison between Decimal, Binary, Octal, and Hexadecimal number. Table 1.1 Comparison of Decimal, Binary, Octal, Hexadecimal numbers

DECIMAL (BASE 10)

BINARY (BASE 2)

OCTAL (BASE 8)

HEXADECIMAL (BASE16)

0

00000

0

0

1

00001

1

1

2

00010

2

2

3

00011

3

3

4

00100

4

4

5

00101

5

5

6

00110

6

6

7

00111

7

7

8

01000

10

8

9

01001

11

9

10

01010

12

A

11

01011

13

B

12

01100

14

C

13

01101

15

D

14

01110

16

E

15

01111

17

F

16

10000

20

10

Table 1.2 shows the difference between Decimal, Binary, Octal and Hexadecimal number systems

‡‡ 1.6

NUMBER SYSTEM AND CODES

Table 1.2 Difference between Decimal, Binary, Octal and Hexadecimal number System Decimal System

Binary System

Its base is Its base is 2 10

Its base is 8

This rangIt has only two values either This system es from 0 ‘0’ or ‘1’ from 0 to 7 to 9 Example (439)10

Example (101011)2

The disadvantage of binary This is the system is that it requires universal very long string of 1’s and represen0’s to represent decimal tation number

Hexadecimal System

Octal System

Its base is 16 ranges This ranges from 0 to 9, A to F

Example (452)8

Example (AF2)16

This is advantageous over binary mainly in reducing the size and the digital clock/computers internally work with octal

It is very compact and can easily convert hexadecimal to binary and to hexadecimal

1.3 NUMBER BASE CONVERSION The number base conversion are essential in Digital electronics. Mostly in all digital systems we have the input in decimal format. For example, the internal computer system computations are binary. Therefore, decimal to binary conversion is important. After processing output should be in decimal for us to understand where conversion from binary to decimal becomes essential. Similarly in microprocessor we use hexadecimal code to binary code conversion at the input side and binary code to hexadecimal code conversion at the output side. Therefore it is necessary to have in depth knowledge about number base conversions. The number base conversion can be done by two methods. The first method is conversion of decimal system to any other base system and second method is any other radix system to decimal system. The figure 1.2 shows the possibilities of conversion from one number system to the other. From, this it is clear that conversion of octal number to hexadecimal number and its reverse is not possible directly; whereas, it is necessary to go through a binary or decimal number.

‡‡ 1.7

Octal number

Binary number

Decimal number

Hexa-decimal number Figure 1.2 Number base conversion

1.3.1 Conversion from any Radix (r) to Decimal Number System The conversion of any radix system to decimal number system is given by the following steps Step 1: Write the given number. Step 2: Write the weights of different position. Step 3: Multiply each digit in the given number with the corresponding weight to obtain product number. Step 4: Add all the product numbers to get decimal equivalent. 1.3.1.1 Binary to Decimal Number System Example 1.1 Convert binary number (10111.101)2 to decimal number Solution 24 23 22 21 20 2-1 2-2 2-3 1

0

1

1

1

1 x 24 0 x 23 1 x 22 1 x 21 1 x 20

1

0

1

1 x 2-1 0 x 2-2 1 x 2-3

(1 x 24)+ (0 x 23) +(1 x 22) +(1 x 21) +(1 x 20) +(1 x 2-1) +(0 x 2-2) +(1 x 2-3) =(23.625)10

‡‡ 1.8

NUMBER SYSTEM AND CODES

Example 1.2 Convert binary number (10110.0101)2 to decimal number Solution 2− 1 2− 2 2− 3 2− 4 24 23 22 21 20

1 1 x 24

0

1

1

0

0 x 23 1 x 22 1 x 21 0 x 20

0

1

0

1

0 x 2 − 1 1 x 2 − 2 0 x 2− 3 1 x 2− 4

(1 x 24)+ (0 x 23) +(1 x 22) +(1 x 21) +(0 x 20) +(0 x 2-1) +(1 x 2-2) + (0 x 2-3)+(1 x 2-4) =(22.3125)10 1.3.1.2 Octal to Decimal Number System Example 1.3 Convert octal number (235.23)8 to decimal number Solution 82 81 80 8 −1 8 − 2 3 2 5 2 3 2 x 82 3 x 81 5 x 80

2 x 8 −1 3 x 8− 2

(2 x 82)+(3 x 81) +(5 x 80) +(2 x 8-1) +(3 x 8-2) =(157.296875)10 Example 1.4 Convert (26.24)8 to ( ? )10 Solution 81 2

80 6

2 x 81 6 x 80

8− 1 2

8− 2 4

2 x 8− 1 4 x 8 − 2

(2 x 81)+(6 x 80)+(2 x 8-2)+(4 x 8-2) =(22.3125)10

‡‡ 1.9

1.3.1.3 Hexadecimal to Decimal Number System Example 1. 5 Convert Hexadecimal number (ABC.3C)16 to decimal number Solution 162

161

A

B

C

A x 162 B x 161

16−1 3

160

16− 2 C

3 x 16−1 C x 16− 2

C x 160

=(A x162) + (B x 161) + (C x 160) + (3 x 16 − 1) +(C x 16 −2) =(10 x 162) + (11 x 161) + (12 x 160) + (3 x 16 −1) + (12 x 16 =(2748.234375)10

−2

)

Example 1.6 Convert Hexadecimal number (16.5)16 to decimal number Solution

161 1

160 6

16 −1 5

1 x 161 6 x 160 5 x 16 −1 0 −1 (1 x 16 ) +(6 x 16 ) +(5 x 16 ) =(22.3125)10 Example 1.7 Convert Hexadecimal number (FAFA.B)16 to decimal number Solution 1

163

162

F

A

F x 163

A x 162

161 F F x 161

160

16−1

A

B

A x 160

B x 16−1

=(F x 163)+ (A x 162)+(F x 161) +(A x 160) +(B x 16−1) = (15 x 163) + (10 x 162) + (15 x 161) + (10 x 160) + (11 x 16 =(64250.6875)10

−1

)

‡‡ 1.10

NUMBER SYSTEM AND CODES

1.3.1.4 Other Base to Decimal Number System Example 1.8 Convert radix 5 number (4310)5 to decimal number Solution 50 53 52 51 1 4 3 0 4 x 53 3 x 52 1 x 51 0 x 50 (4 x 53) +(3 x 52) +(1 x 51) +(0 x 50) =(580)10 Example 1.9 Convert radix 12 number(198)12 to decimal number Solution 122 120 121 1 9 8 1 x 122

9 x 121 8 x 12

0

(1 x 122)+(9 x 121) +(8 x 120) =(260)10 Example 1.10 Convert radix 6 number (525)6 to decimal number Solution 62 5

61 2

5 x 62

2 x 61

(5 x 62)+(2 x 61) +(5 x 60) =(197)10

60 5 5 x 60

‡‡ 1.11

1.3.2 Conversion

of Decimal number System to any Radix (r)

System

The decimal number system may have both integer part as well

as fractional part. The method for conversion of decimal system to any radix is shown in figure 1.3 Method of conversion of decimal system to any radix system

Integer part (division method)

Fractional part (Multiplication method)

Figure 1.3 Conversion of decimal system to any radix



The integer part of decimal number is converted to any other base or radix by continuously dividing the number by the base value until further division is not possible. The remainder gives the required number. The fractional part of decimal number is converted to any base or radix by continuously multiplying the number by the base value until the fractional part becomes zero. The carry gives the required number. 1.3.2.1

Conversion of Decimal Integer part to any radix system

The conversion of the integer decimal part to any radix is given as

follows. Step 1 : Repeatedly divide the integer part of decimal number by the base until it cannot be divided further. Step 2: The remainder is taken in reverse order to form new base number. Step 3: First remainder is the least significant digit(LSD) and last remainder is most significant digit(MSD).

‡‡ 1.12

NUMBER SYSTEM AND CODES

Example 1.11

Convert (105)10 to ( ? )2

Solution

LSB 2

105 2

52

1

2 26

0

2

0

13 2

6 2

1 3

0

1 1 MSB Ans: (1101001)2 Example 1.12 Convert (204)10 to ( ? )8 Solution

LSB 8

204 8

25

4

1 3 MSB Ans: (314)8 Example 1.13 Convert (25)10 to ( ? )16 Solution LSB

16 25 9 1 MSB Ans: (19)16

‡‡ 1.13

Example 1.14 Convert (54)10 to ( ? )4 Solution

4

LSB

54 4

13

2

1 3 MSB Ans: (312)4 1.3.2.2 Conversion of Decimal fraction number to any radix system The conversion of the fractional decimal number system to any radix system is given as follows Step 1 : The number to be converted is multiplied by the radix. Step 2 : The product has integer part and fractional part. Step 3 : The integer part is taken as carry Step 4 : The fractional part from step 2 is multiplied by the base Step 5 : The step 3 and 4 is repeated until fractional part becomes ‘0’. Step 6 : Carry is written downwards, which is the required number. Example 1.15 Convert (0.8125)10 to ( ? )2 Solution base product carry 0.8125

x 2 = 1 .625

1

0.625

x 2 = 1 .25

1

0.25 x 2 = 0 .5 0

0.5

x 2 = 1 .0

1 Fractional part zero

Ans: (0.1101)2

‡‡ 1.14

NUMBER SYSTEM AND CODES

Example 1.16 Convert (0.45)10 to (?)8 Solution base product

0.45

x 8 = 3 .60

0.60 x 8 = 4 .80

carry 3

4

0.80

x 8 = 6 .40

6

0.40

x 8 = 3 .20

3 Fractional part continues

Ans: (0.3463…)8 Example 1.17 Convert (0.122)10 to ( ? )16 Solution base product

0.122

carry

x 16 = 1 .952

1

1

0.952

x 16 = 15 .232

15

F

0.232

x 16 = 3 .712

3

3

0.712

x 16 = 11 .392

11

B

Fractional part continues Ans: (0.1F3B…..)16

‡‡ 1.15

Example 1.18 Convert (1305.375)10 to binary, octal and hexadecimal. Solution Decimal to binary number 2

LSB

1305 1

652

2

0

326

2 2

163

0

81

1

2

40

2 2

1

20 2 2

0

5

0

2

1

0.375 x 2

= 0 .75

0

0.75 x 2

= 1 .5

1

0.50

= 1 .0

1

1

0

x 2

Fractional part zero

MSB Decimal to octal number LSD 8

carry

0

10 2

product

base

Ans: (10100011001.011)2 base

product

carry

1305 8

163

8

1

20

0.375 x 8

= 3 .0

3

3 Fractional part zero

4 2 MSD Ans: (2431.3)8 Decimal to hexadecimal number LSD

base

16

1305

16

81

9

5

1

0.375 x 16 =

product 6 .0

carry 6

Fractional part zero MSD Ans: (519.6)16

‡‡ 1.16

NUMBER SYSTEM AND CODES

Example 1.19 Convert (301.12)10 to binary, octal and hexadecimal Solution Decimal to binary number 2

LSB

301

2

150

1

75

0

2

37

2

base

product

carry

0.12 x 2 = 0 .24

0

1

2

18

1

2

9

0

2

4

0

1 0

2

2

0.24 x 2 = 0 .48

1

0.48 x 2 = 0 .96

0

0.96 x 2 = 1 .92

1

0

MSB

Fractional part continues

Decimal to octal number base

LSD 8

product

carry

301 8

MSD

Ans: (100101101.0001…)2

37

5

4

5

0.12

x 8

= 0 .96

0

0.96

x 8

= 7 .68

7

0.68

x 8

= 5 .44

5 Fractional part continues

Ans: (455.075…)8

‡‡ 1.17

Decimal to hexadecimal number product

LSD 16

base

301

1

MSD

0.12 x 16 =

13 D

18

16

carry

1 .92

1

1

x 16 = 14 .72

14

E

x 16 = 11 .52

11

2

0.92

0.72

B

Fractional part continues

Ans: (12D.1EB…)16 Example 1.20 Convert (757.25)10 to binary, octal and hexadecimal number. Solution Decimal to binary number

2

LSB

757 1

378

2

2 2

94

1

47

0

23

2 2 2

product

0

189

2

1

11

1

5

1

0.25 x

0.5

x

carry

base 2 = 0 .5

0

2 = 1 .0

1 Fractional part zero

2 1 2 0 1 Ans: (1011110101.01)2 MSB

‡‡ 1.18

NUMBER SYSTEM AND CODES

Decimal to octal number LSD 8

product

757 8 8

94 11

base 0.25 x 8 = 2 .0

5

carry 2 Fractional part zero

6

3 1 Ans: (1365.20)8 MSD Decimal to hexadecimal number 16 16 MSD

757 47 2

5

5

15

F

carry

product

LSD 0.25 x

base 16 =

4 .0

4 Fractional part zero

Ans: (2F5.40)16 1.3.3 Special Conversion method The conversion between binary, octal and hexadecimal plays an important role in digital computers. Since 23 = 8 and 24 = 16 each octal digit correponds to three binary digits and each hexadecimal digit corresponds to four binary digits. This is called special conversion method. 1.3.3.1 Binary to Octal Conversion The binary number is represented with base of 2 and octal number is 8. Therefore, the octal number can also be represented as 23. The power three is the number of digit in integer portion of number i.e, three bit of binary represents one octal value. The steps for conversion of binary to octal number is given as follows Step 1 : Group the binary number by three digits. Step 2 :Each group is represented by an octal value. Step 3 : All the octal value together gives the equivalent octal number. For example, consider a binary number 111101100 which is grouped as follows

‡‡ 1.19

111 101 100 7 5 4 The equivalent octal number is (754)8 1.3.3.2 Octal to Binary Conversion Octal number can be converted to binary number by representing each octal numbers by three bits of binary. The step for conversion of octal to binary is given as follows Step 1 : Each octal value in the number is represented by three bits of binary. Step 2 : All the binary value together gives the equivalent binary number. For example, consider an Octal number 634 which is grouped as follows (6 3 4)8

110 011 100 The equivalent binary number is (110011100)2 1.3.3.3 Binary to Hexadecimal Conversion The binary number is represented with base of 2 and hexadecimal number is 16. Therefore the hexadecimal number can also be represented as 24. The power four is the number of digit in integer portion of number i.e, four bit of binary represents one hexadecimal value. The steps for conversion of binary to hexadecimal is given as follows Step 1 : Group the binary number by four digits. Step 2 : Each group is represented by an hexadecimal value. Step 3 : All the hexadecimal value together gives the equivalent hexadecimal number. For example, consider a binary number 110110001011 grouped as follows

1101 D

1000 8

1011 B

The equivalent Hexadecimal number is (D8B)16

‡‡ 1.20

NUMBER SYSTEM AND CODES

1.3.3.4 Hexadecimal to Binary Conversion Hexadecimal number can be converted to binary number by representing each Hexadecimal value by four bits of binary. The steps for conversion of hexadecimal to binary is given as follows Step 1 : Each Hexadecimal value in the number is represented by four bits of binary. Step 2 : All the binary value together gives the equivalent binary number. For example, consider a hexadecimal number 3FD which is grouped as follows. (3 0011

F

D)16

1111

1101

The equivalent binary number is (001111111101)2 The binary numbers are difficult to work with because they require three or four times as many digits as their decimal equivalent. For example, a 4 digit decimal number (4095)10 is equivalent to 12 bit binary number (111111111111)2. Though it occupies more space in memory binary number are very important. We can reduce the number of digits by utilizing the relationship between the binary number system with octal or hexadecimal system. The binary number (111111111111)2 which has 12 digits when it is expressed in octal it becomes 4 digits (7777)8 and in hexadecimal as 3 digits (FFF)16 . The octal or hexadecimal representation is more desirable because it can be expressed more compactly with a quarters or third respectively of the number of digits required for the equivalent binary number. Thus most computers use either octal or hexadecimal numbers to specify binary quantities. Therefore it is necessary to understand the procedures to be followed to convert octal to hexadecimal and vice-versa. 1.3.3.5 Octal to Hexadecimal Conversion Octal number cannot be directly converted to hexadecimal numbers because its base cannot be made equal. Therefore this type is converted by an intermediate conversion stage of binary equivalent. The

‡‡ 1.21

steps for conversion of hexadecimal number to octal number is given below Step 1 : First convert each octal value to its equivalent binary number (refer section 1.3.3.2). Step 2 : Then convert the binary number to its equivalent hexadecimal number (refer section 1.3.3.3). Example 1.21 Convert (615)8 to ( ? )16 Solution First convert Octal to binary number 6 110



1

5

001

101

The Binary number is (110001101)2

Binary number is converted into hexadecimal number 0001

1000

1101

1

8

D

The hexadecimal to decimal equivalent of octal number (615)8 is(18D)16

1.3.3.6 Hexadecimal to Octal Conversion Hexadecimal numbers cannot be directly converted to octal numbers because its base cannot be made equal. Therefore this type is converted by intermediate conversion stage of binary equivalent. The steps for conversion of hexadecimal to octal number is given as follows. Step 1 : First convert each hexadecimal value to its equivalent binary number (refer section 1.3.3.4). Step 2 : Then convert the binary number to its equivalent octal number (refer section 1.3.3.1).

‡‡ 1.22

NUMBER SYSTEM AND CODES

Example 1.22

Convert (25B)16 to (?)8

Solution Convert Hexadecimal number to binary number

2

5

0010

B

0101

1011

Binary number is (001001011011)2 Binary number is converted into its equivalent octal

001

001

011

011

1

1

3

3

The octal number is equivalent for (25B)16 is (1133)8 Example 1.23 Convert (30.23)8 to hexadecimal number. Solution First convert Octal number to binary number



3

0

2

011

000

010

3 011

Binary number is (011000.010011)2

The Binary number is converted to its equivalent hexadecimal number



0001

1000

0100

1100

1

8

4

C

The hexadecimal number equivalent for (30.23)8 is (18.4C)16

‡‡ 1.23

Example 1.24 Convert (1.100010)2 to octal number and hexadecimal number. Solution Conversion of the Binary number to its equivalent octal number

001

010

100

1

2

4

The octal equivalent for (1.100010) is (1.42)8 Conversion of the Binary number to its equivalent hexadecimal number is as follows

0001 1000 1000 1

8

8

The hexadecimal equivalent for (1.100010)2 is (1.88)16 Example 1.25 Convert (110.010)2 to octal and hexadecimal number. Solution Conversion of the Binary number to its equivalent octal number is as follows

110

010

6

2

The octal equivalent for (110.010)2 is (6.2)8 Conversion of the Binary number to its equivalent hexadecimal number is as follows

0110 0100 6

4

The hexadecimal equivalent for (110.010)2 is (6.4)16

‡‡ 1.24

NUMBER SYSTEM AND CODES

Example 1.26 Convert (1001000.111)2 to octal and hexadecimal number. Solution Conversion of Binary to octal number is as follows



001

001

000

1

1

0

111 7

The octal number is (110.7)8

Conversion of Binary number to its equivalent hexadecimal number is as follows



0100

1000

1110

4

8

E

The hexadecimal number is (48.E)16

Example 1.27

Convert (375.64)8 to binary and hexadecimal number.

Solution First Octal number is converted to binary number

3

5

7

011

111

6

101

4

110 100



The binary number is (011111101.110100)2



The Binary number is converted to its equivalent hexadecimal

number



1111

1101

F

D

1101 0000 D

The hexadecimal number is (FD.D0)16

0

‡‡ 1.25

Example 1.28

Convert (ADE.B)16 to binary and octal number

Solution

First convert the Hexadecimal number to it equivalent binary

number



A

D

E

1010

1101

1110

B 1011

The binary number is (101011011110.1011)2

The Binary number is the converted to its equivalent octal number



101

011

011

110

101

5

3

3

6

5

100 4

The octal number is (5336.54)8





1.4 COMPLEMENTS The direct method of subtraction requires complicated logic circuits to represent negative integers. To overcome this problem, complements are used in digital computer for simplifying the subtraction operation and for logical manipulation. Complements are taken only for negative number. In practice, when using complement arithmetic, the process of subtraction becomes one of addition. For example let us take two numbers as A and B. The subtraction of A and B using complements is represented as addition of positive A and negative B.

A - B = A+(- B)



Complement Thereby reduces the complexity of the Digital circuit. The Figure 1.4 shows the classification of complements. The complements are classified into two types. They are

‡‡ 1.26

NUMBER SYSTEM AND CODES

1. Diminished radix (r-1) 2. Radix (r)

They are further classified into two types by substituting the

value of base r which is referred to as 2's and 1's complement for binary numbers and 10's and 9's complement for decimal number. Complement radix (r)

Diminished radix (r - 1) 1’s complement

9’s complement

2’s complement

10’s complement

Fig. 1.4 Classification of complement

1.4.1 Diminished Radix Complement (r-1)’s Complement

The diminished radix complements are 1's complement and 9's

complement. The algorithm to find the (r-1)'s complement are given below 1.4.1.1 One's (1’s) Complement

The 1’s complement is taken only for the binary numbers. It is

obtained by Changing ‘0’ to ‘1’ and ‘1’ to ‘0’.

Let

us

consider

the

binary

number

101100

whose

1's

complement is obtained as follows 101100

1’ s complement

010011

The 1's complement for (101100)2 is (010011)2.

1.4.1.2 Nine's (9’s) Complement

The 9’s complement is taken only for decimal numbers. The 9’s

complement is obtained by subtracting each digit from 9.

For example the 9’s complement of 546700 is

‡‡ 1.27

Subtract from 9 9’ s complement of 546700

}

999999 =-546700 = 453299

The 9's complement of (546700)10 is (453299)10

1.4.2 Radix (r’ s) Complement

The radix (r's) complements are 2's complement and 10's comple-

ment. The algorithm to find r's complement are given below. 1.4.2.1 Two's (2’s) Complement

The 2’s complement is taken only for binary numbers. The step

for taking 2’s complement is given as follows Step 1: Change ‘0’ to ‘1’ and ‘1’ to ‘0’ i.e., take 1’s complement Step 2: Add ‘1’ to the least significant bit(LSB). For example 2’s complement of (10101)2 is Take 1’s complement for 10101 Add 1 to LSB 2’s complement of 10101

} }

=01010 +1 =01011

The 2's complement of (10101)2 is (01011)2 1.4.2.2 Ten's (10’s) Complement The 10’s complement is taken only for decimal numbers. The step for taking 10’s complement is given as follows Step 1: Subtract each digit from 9 i.e., take 9’s complement. Step 2: Add 1 to the least significant digit (LSD). For example 10’s complement of 546700 is Subtract from 9 9’ s complement of 546700 Add 1 to LSB 10’ s complement of 546700

999999 =-546700

}

= 453299 +1 = 453300

The 10's complement of (546700)10 is (453300)10

‡‡ 1.28

NUMBER SYSTEM AND CODES

1.5 BINARY SUBTRACTION USING COMPLEMENTS As discussed in the previous section 1.4 the binary subtraction are done using complements. The binary subtraction procedure using diminishes radix and radix complement are compared in table 1.3. Table 1.3 Comparison between (r-1) complement and r’s complement S.No

Diminished radix (r-1)

Larger number-Smaller number

Radix (r) Larger number-Smaller number

1.

Take (r-1)’s complement for the smaller negative number

Take (r)’s complement for the smaller negative number

2.

Add the complemented value with the larger number.

Add the complemented value with the larger number.

3.

If carry exist, do end around carry Smaller number - Larger number

If carry exist, discard carry Smaller number- Larger number

1.

Take (r-1)’ s complement for the larger negative number

Take (r)’s complement for the larger negative number

2.

Add the complemented value with the smaller number

Add the complemented value with the smaller number

3.

If no carry, then once again take (r-1)’s complement and add negative sign.

If no carry, then once again take (r)’s complement and add negative sign

Example 1’s and 9’s complement

Example 2’s and 10’s complement

4.

Note: 1. If carry exist after addition then the answer is positive 2. If no carry exist after addition then answer is negative 1.5.1 Subtraction using 1’s Complement 1.5.1.1 Subtraction of Smaller Number (B) from Larger Number (A): A-B The subtraction of smaller from larger number using 1’s complement is given as follows Step 1: Take 1’s complement for smaller number. Step 2: Add the 1’s complemented value with larger number. Step 3: If carry occurs, take the carry and add it to the sum which is called as end around carry and the answer is positive

‡‡ 1.29

Example 1.29 Find (57)10 - (43)10 using 1’s complement Solution Convert to binary: (111001)2-(101011)2 1’s complement of (101011)2 is 1’s complement 010100 101011 Add the complemented value to the larger number

1’s complement of 43 = 010100 Larger number 57 = +111001 carry exist 1001101 End around carry +1 001110 Ans: (00110)2 Example 1.30

Find (9)10 - (4)10 using 1’s complement

Solution

Convert to binary: (1001)2-(0100)2

(note: number of bit should be equal for subtraction)

1’s complement of (0100)2 is 1’s complement 1011 0100 Add the complemented value to the larger number 1’s complement of 4 = 1011 Larger number 9 = + 1001 carry exist =1 0100 End around carry +1 0101 Ans: (0101)2

‡‡ 1.30

NUMBER SYSTEM AND CODES

1.5.1.2 Subtraction of Larger Number (A) from Smaller Number (B): B-A

The subtraction of larger number from smaller number using 1’s

complement is given as follows Step 1: Take 1’s complement for the larger number. Step 2: Add the complemented value with the smaller number Step 3: If no carry, then the result is negative and it is in

complemented form

Step 4: Therefore once again take 1’s complement and add

negative sign to the answer.

Example 1.31 Find 6710-8410 using 1’s complement Solution Convert to binary: (1000011)2-(1010100)2 1’s complement of (1010100)2 is 1’s complement 0101011 1010100 Add the complemented value to the smaller number 1’s complement of 84 = 0101011 Smaller number 67 = + 1000011 No carry exist → 1101110

Once again take 1’s complement and add negative sign to the answer 1’s complement - (0010001)2 1101110 Ans: - (0010001)2 Example 1.32

Find (3)10 - (8)10 using 1’s complement

Solution Convert to binary: (0011)2-(1000)2 1’s complement of (1000)2 is

‡‡ 1.31

1’s Complement 0111 1000 Add the complemented value to the smaller number 1’s complement of 8 Smaller number 3 No carry exist

= 0111 = +0011 → 1010

Once again take 1’s complement and add negative sign to the answer 1010

1’s Complement

-(0101)2

Ans: - (0101)2 1.5.2 Subtraction using 2’s Complement 1.5.2.1 Subtraction of Smaller Number (B) from Larger Number (A): A-B The subtraction of smaller number from large number using 2’s complement is given as follows Step 1: Take 2’s complement for smaller number. Step 2: Add the 2’s complemented value with larger number. Step 3: If carry occurs, discard the carry. Example 1.33 Find (1010100)2-(1000011)2 using 2’s complement Solution 2’s complement of (1000011)2 1’s complement of (1000011)2 Add 1 to LSB 2’s complement of (1000011)2

}

= 0111100

}

= 0111101

=

+1

Add the complemented value to the larger number

}

2’s complement of (1000011)2 Larger number Discard carry

=

0111101

= + 1010100 → 1 0010001 Ans: (0010001)2

‡‡ 1.32

NUMBER SYSTEM AND CODES

Example 1.34 Find 1710-1110 using 2’s complement Solution Convert to binary (10001)2-(01011)2 2’ s complement of (01011)2 is 1’s complement 01011 10100

}

=10100

}

=10101

1’s complement of (01011)2 Add 1 to LSB 2’s complement of (01011)2

=

+1

Add the complemented value to the larger number

}

2’s complement of = 10101 01011 Larger Number = + 10001 Discard Carry → 1 00110



Ans: (00110)2

1.5.2.2 Subtraction of Larger Number (A) from Smaller Number (B): B-A

The subtraction of larger number from smaller number using 2’s

complement is given as follows Step 1: Take 2’s complement for the larger number. Step 2: Add the complement value with the smaller number. Step 3: If no carry, then the result is negative and it is in

complement form.

Step 4: Therefore once again take 2’s complement and add

negative sign to the answer

‡‡ 1.33

Example 1.35

Find 910-4010 using 2’s complement

Solution Convert to binary: (001001)2-(101000)2 2’ complement of (101000)2 is 1’s Complement 101000 010111 1’s complement of = 010111 (101000)2

}

Add 1 to LSB 2’s complement of (101000)2

=

+1

= 011000

Add the complemented value to the small number

}

2’s complement of = 011000 (101000)2 Smaller number 9 = + 001001 No carry exist → 100001 Once again take 2’s complement and add negative sign to the answer 1’s Complement 011110 100001 1’s complement of (100001)2 Add 1 to LSB 2’s complement of (100001)2

}

= 011110

}

= 011111

=

+1

Ans: - (011111)2

‡‡ 1.34

NUMBER SYSTEM AND CODES

Example 1.36

Find (11001)2-(11111)2 using 2’s complement

Solution 2’s complement of (11111)2 1’s Complement 11111 1’s complement of (11111)2 Add 1 to LSB 2’s complement (11111)2

00000

}

= 00000 =

}

+1

= 00001

Add the complemented value to the smaller number

}

2’s complement of = 00001 (11111)2 = + 11001 Smaller number (11001)2 No carry exist 11010 Once again take 2’s complement and add negative sign to the answer 1’s Complement 00101 11010 1’s complement of (11010)2

}=

00101

Add 1 to LSB = +1 2’s complement of = 00110 (11010)2 Ans: -(00110)2

}

1.5.3 Subtraction using 9’S Complement 1.5.3.1 Subtraction of Smaller (B) from Larger Number (A): A-B The subtraction of smaller number from larger number using 9’s complement is given as follows Step 1: Take 9’s complement for smaller number. Step 2: Add the 9’s complemented value with the larger number. Step 3: If carry occurs remove the carry and add it to the sum. This is called end around carry and the answer is positive.

‡‡ 1.35

Example 1.37 Find (22)10-(11)10 using 9’s complement Solution 9’s complement of (11)10 Subtract from 9 9’s complement of 11

99 = - 11 = 88

Add the complemented value to the larger number 9’s complement of 11 = 88 Larger Number =+ 22 Carry exist → 1 10 +1 End around carry 11 Example 1.38 Find (567)10 - (124)10 using 9’s complement Solution 9’s complement of (124)10 Subtract from 9 9’s complement of 124

Ans: (11)10

999 = - 124 = 875

Add the complemented value to the larger number 9’s complement of 124 = 875 Larger Number = + 567 Carry exist → 1 442 End around carry +1 443

Ans: (443)10

1.5.3.2 Subtraction of Larger Number (A) from Smaller Number (B): B-A The subtraction of larger number from smaller number using 9's complement is given as follows Step 1: Take 9’s complement for the larger negative number. Step 2: Add the complemented value with smaller number. Step 3: If no carry, then the result is negative and it is in complemented form.

‡‡ 1.36

NUMBER SYSTEM AND CODES

Step 4: Therefore once again take 9’s complement and add negative sign to the answer. Example 1.39 Find (11)10 - (22)10 using 9’S complement Solution 9’ complement of (22)10 99 Subtract from 9 = - 22 9’s complement of 22 = 77 Add the complement value to the smaller number 9’s complement of 22 = 77 Smaller Number = +11 No carry → 88 Once again take 9’s complement and add negative sign to the answer 99 Subtract from 9 = - 88 9’s complement of 88 = 11 Ans: -(11)10 1.5.4 Subtraction using 10’S Complement 1.5.4.1 Subtraction of Smaller (B) from Larger Number (A): A-B

The subtraction of smaller number from larger number using 10’s

complement is given as follows Step 1: Take 10’s complement for smaller number Step 2: Add the 10’s complement value with larger number. Step 3: If carry occurs, discard the carry and the result is

positive.

Example 1.40 Find (22)10 - (11)10 using 10’s complement Solution 10’s complement of (11)10 99 Subtract from 9 = - 11 9’s complement of 11 = 88 Add 1 to LSB = +1 10’s complement of 11 = 89

‡‡ 1.37

Add the complement value to the smaller number 9’s complement of 11 = 89 Larger Number = +22 Discard carry 1 11 Ans: (11)10 1.5.4.2 Subtraction of Larger Number (A) from Smaller Number (B): B-A The subtraction of larger number from smaller number using 10’s complement is given as follows Step 1: Take 10’s complement for the larger negative number. Step 2: Add the complemented value with the smaller number. Step 3: If no carry, then the result is negative and it is in complemented form. Step 4: Therefore once again take 10’s complement and add negative sign to the answer. Example 1.41 Find (11)10-(22)10 using 10’s complement Solution 10’s complement of (22)10 Subtract from 9

99 = - 22

9’s complement of 22 = 77 Add 1 to LSB +1 10’s complement of 22 = 78 Add the complemented value to the smaller number 10’s complement of 22 = 78 = +11 Smaller number No carry → 89 Once again take 10’s complement and add negative sign to the answer 99 Subttract from 9 = - 89 9’s complement of 89 = 10 +1 Add 1 to LSB = 11 Ans: -(11)10

‡‡ 1.38

NUMBER SYSTEM AND CODES

1.6 SIGNED BINARY NUMBERS

In a common arithmetic operations, negative numbers are represented by minus sign(-) and positive numbers are represented by plus sign(+).The positive numbers including zeros can also be represented as unsigned numbers. For negative number representation, we need a notation for negative values. In computers every representation is in binary digits. Therefore to represent signed binary numbers, we need to add sign bit to the binary number For positive numbers, sign bit is ‘0’. The representation of (+5)10 is (+5)10 = 0 1 0 1

Number

Sign bit

In signed binary number, the leftmost bit represents the sign bit and the remaining bits represent a number. In the representation of +5, among the bits the leftmost position of the number (MSB) represented as ‘0’ is positive sign (+) bit and the remaining three bits ‘101’ represents the number (5).

For negative numbers, sign bit is ‘1’. The representation of (-5)10 is (- 5)10 = 1 1 0 1 Sign bit

Number

In the representation of -5, among the bits the left most position of the number (MSB) represented as ‘1’ is negative sign (-) bit and the remaining three bits ‘101’ represents the number(5). In unsigned binary numbers all the bits together represent a number.

0101

1101 Number (5)

Number (13)

In this all the four bit represents the number. If we Compare signed numbers and unsigned numbers, we can see that the positive number representation is same in both the case. The negative signed numbers can be represented in three

‡‡ 1.39

different ways, 1. Signed magnitude, 2. Signed 1's complement, 3. Signed 2's complement. The Signed-magnitude representation is given for the number 1101 where 101 represent the number '5' and the last MSB '1' represent the negative sign. Therefore the number is -5. The signed magnitude representation is given as 1101 Number for 5

Negative sign bit

The Signed 1’s complement representation is given for the number 1101 as 1010 where 1's complement be taken only for 101 resulting in 010. The sigh bit (MSB) will not be complemented. The representation for signed 1's complement is given as 1010 Number for 5 (1’s complement for 101)

Negative sign bit

The Signed 2’s complement representation is given for the number 1101 as 1011 where 2's complement is taken only for 101 resulting in 011. The sign bit (MSB) will not be complemented. The representation for signed 2's complement is given as 1011 Number for 5 (2’s Complement for 101)

Negative sign bit

The signed complement system is used when arithmetic operations are implemented in computer. In this system, a negative number is indicated by its complement. The signed complement system can use either 1’s or 2’s complement, but 2’s complement is most common. Table 1.4 shows the 4 bit signed binary number in three ways of representation. Table 1.4 4 bit signed binary numbers in three way of representation Signed 1’s

Signed 2’s

tude

complement

complement

+7

0111

0111

0111

+6

0110

0110

0110

+5

0101

0101

0101

+4

0100

0100

0100

Decimal

Signed

magni-

‡‡ 1.40

NUMBER SYSTEM AND CODES

+3

0011

0011

0011

+2

0010

0010

0010

+1

0001

0001

0001

+0

0000

0000

0000

-0

1000

1111

-

-1

1001

1110

1111

-2

1010

1101

1110

-3

1011

1100

1101

-4

1100

1011

1100

-5

1101

1010

1011

-6

1110

1001

1010

-7

1111

1000

1001

From the Table 1.4 it is found that in all three representation, the positive numbers are identical and have ‘0’ in the leftmost position, for negative numbers the left most bit position will have ‘1’. In signed 1’s complement and signed magnitude representation ‘+0’ and ‘-0’ can be represented separately whereas signed 2’s complement will have representation only for’+0’, i.e, it is always positive ‘0’. For signed magnitude 8-bit binary numbers. The largest magnitude is 127 because we need to represent both positive and negative numbers. The maximum positive number is +127. Its binary signed magnitude representation for +127 is given as

+127 =

01111111

Sign bit

Number (127)

The last seven bits are '1' representing the number 127 and the MSB bit '0' represent the positive sign. The Maximum negative number is -127. Its binary signed magnitude representation for -127 is given as -127 = 1 1 1 1 1 1 1 1 Number (127) Sign bit Here the last seven bits are '1' representing the number 127 and the MSB bit '1' represent the negative sign.

‡‡ 1.41



The signed magnitude representation requires separate handling for sign and magnitude during arithmetic operation and hence it is not suitable in common arithmetic. The signed complement number is normally used in computer arithmetic. The 1’s complement is impossible due to some practical difficulties and is used as a logical operation units since the change of ‘1’ to ‘0’ (or) ‘0’ to ‘1’ is equivalent to a logic complement operation and signed 2’s complement system is most commonly used. 1.6.1

Signed Binary Arithmetic



In the signed-magnitude system the addition of two numbers follows the rules of ordinary arithmetic which is given in the Table 1.5. If both magnitude signs are same,add the two magnitude and give common sign. If both magnitude signs are different, subtract the smaller magnitude from the larger and give the result to the sign of the larger magnitude. For example (+50)+(-25)=+25 and (50)+(-25)=-25 This is the process that requires comparison of signs and the magnitude and then performing either addition or subtraction. Table 1.5 Binary Addition



Input

Output

A

B

Carry

Sum

0

0

0

0

0

1

0

1

1

0

0

1

1

1

1

0

‡‡ 1.42

NUMBER SYSTEM AND CODES

Example: 1.42 Add +20 and +10 in binary arithmetic Solution The signed value of + 20 = 0 1 0 1 0 0 The signed value of +10 = 0 1 0 1 0 ↓ Sign + 20 = 1 0 1 0 0 + 10 = 0 1 0 1 0 + 30 = 1 1 1 1 0

Ans: (11110)2

Example: 1.43 Subtract 5 from 11 in binary arithmetic Solution The operation is written as +11-(+5). The Signed value of + 11 =01011 The signed value of +5 = 0 1 0 1 ↓ Sign Subtract both the signed magnitude value with the number given using binary subtraction rule

Positive Sign

}

Signed magnitude value of + 11 = 0 1 0 1 1 Signed magnitude value of + 5 = - 0 1 0 1 =00110 Number

Ans: (0110)2 Example: 1.44 Add +12 and +5 in 8-bit binary signed magnitude using 2's complement Solution Both are positive numbers. + 12 = 0 0 0 0 1 1 0 0 +5 =00000101 + 17 = 0 0 0 1 0 0 0 1 Ans: (00010001)2

‡‡ 1.43

Example: 1.45 Add +12 and -5 using 8-bit binary 2's complement Solution

Smaller negative magnitude; therefore take 2’s complement

for +5

The signed value of +12 = 0 0 0 0 1 1 0 0 The signed value of +5 = 0 0 0 0 0 1 0 1 Sign The signed value of -5 = 1 0 0 0 0 1 0 1 Sign Signed 1’s complement =11111010 of value of 5 Add 1 to LSB = +1 Signed 2’s complement =11110100 value of 5

} }

Add +12 with the 2’s complement value of 5 to get the answer +12 2’s complement of 5 Discard carry



= 00001100 = +11111011 100000111 Positive sign bit

Number 7 Ans: (00000111)2

Example: 1.46

Add -12 and +5 in 8-bit binary using 2's complement method

Solution

AU. QP N/D 2006 2 marks

The larger number 12 is negative magnitude, therefore take 2’s

complement for 12 is The signed value of + 5 = 0 0 0 0 0 1 0 1 The signed of +12 = 0 0 0 0 1 1 0 0 Sign Similarily, The signed value for -12 = 1 0 0 0 1 1 0 0 Sign Signed 1’s complement binary value for 12 = 11110011 add 1 to LSB = +1 Signed 2’s complement value of 12 = 1 1 1 1 0 1 0 0 Add +5 with the signed 2’s complement value of 12

‡‡ 1.44

NUMBER SYSTEM AND CODES

+5 2’s complement of 12

= 00000101 =11110100 =11111001

Negative sign bit Example: 1.47

2’s complement of number 7 Ans: -(11111001)2

Add -12 and -5 in 8-bit binary arithmetic using 2's complement method. Solution

It has both are negative magnitude, then take 2’s complement for

both the numbers 12 and 5. 2’s complement of 12 = 2’s complement of 5 = Discard carry

11110100 11111011 111101111 2’s complement of number 17

Negative sign bit

Ans: - (11101111)2 1.6.2 Signed Binary Subtraction

The steps to perform binary subtraction is given as follows Step 1: Take 2’s complement of subtrahend including the sign bit. Step 2: Add the complemented value to the minuend including the

sign bit.

Step 3: A carry out of sign-bit position is discarded. Example: 1.48 Subtract (-5)- (-12) Solution Find 2’s complement for both 12 and 5 2’s complement of 12 2’s complement of 5 (11111011-11110100)2 Take 2’s complement of 11110100

= 11110100 = 11111011

‡‡ 1.45

1’s complement of 2’s complement of

(1 1 1 1 0 1 0 0) = 0 0 0 0 1 0 1 1 Add 1 + 1 (1 1 1 1 0 1 0 0) = 0 0 0 0 1 1 0 0

Add both the values 2’s complement of 5 = 11110100 (2’s complement of 11110100) = 00001100 =100000111 Discard carry Positive sign bit Number 7 Ans: (00000111)2 1.7 BINARY CODES

A code is a symbol or group of symbols that stands for something.

Binary bits are often used in groups to stand for things such as decimal or alphanumeric characters. Since binary code is represented only with 0’s and 1’s the implementation process becomes easy. The classification of codes are given in Figure 1.6 Binary codes Self complementing Alphanumeric 2421 Non-weighted Reflective Sequential Excess 3 BCD ASCII 2421 Excess 3 8421 BCD EBCDIC 8421 5211 Gray Excess 3 2421 Excess 3 Error detecting Gray Scale and 5211 correcting 4221

Weighted Binary

Figure 1.6 Classification of codes

1.7.1. Weighted Binary codes Weighted binary codes obey their positional weighting principles. Each position of a number represents a specific weight. In a weighted binary code, bits are multiplied by the weights indicated; the sum of these weighted bits gives the decimal digit. The table 1.6 gives the

‡‡ 1.46

NUMBER SYSTEM AND CODES

relationship between decimal, binary and BCD codes. 1.7.1.1 Binary codes In any digital system, the digital data's are represented, stored and transmitted as a group of binary bits called as binary codes. The binary code is represented by number as well as alpha numeric letters. Table 1.6 Relationship between decimal, binary and BCD Codes Decimal Digit

Binary

BCD code 8421

0

0000

0000

1

0001

0001

2

0010

0010

3

0011

0011

4

0100

0100

5

0101

0101

6

0110

0110

7

0111

0111

8

1000

1000

9

1001

1001

10

1010

0001 0000

11

1011

0001 0001

12

1100

0001 0010

13

1101

0001 0011

14

1110

0001 0100

15

1111

0001 0101

}

}

Same as 4 bit Binary

Each digit is represented by 4 bit binary

The Advantages of binary code are as follows (i) The binary codes are suitable for the computer applications. (ii) Binary codes make the analysis and designing of digital circuits easier since only 0's and 1's are used. The Disadvantages of binary code are as follows

The binary system requires very long string of 1's and 0's to represent the decimal number. For details refer section 1.3.3.4 1.7.1.2 Binary Coded Decimal (BCD) codes

One of the most widely used representation of numerical data is

the binary coded decimal (BCD) form in which each integer of a decimal number is represented by a four bit binary number. It is particularly useful for the driving of display devices where a decimal output is

‡‡ 1.47

desired. Some of the BCD codes are 8421, 2421, 4221, 5211. Among all these binary coded decimal we generally use 8421 code. Sometimes this is written as 8421 BCD to clearly distinguish it from other binary codes. The table 1.7 shows the different BCD code representation Table 1.7 Weighted BCD code Decimal Digit

Weighted BCD code 8421

2421

4221

5211

0

0000

0000

0000

0000

1

0001

0001

0001

0001

2

0010

0010

0010

0011

3

0011

0011

0011

0101

4

0100

0100

1000

0111

5

0101

1011

0111

1000

6

010

1100

1100

1010

7

0111

1101

1101

1100

8

1000

1110

1110

1110

9

1001

1111

1111

1111

The Advantages of using BCD codes are as follows (i) Many non-integral values, such as decimal 0.2, have an infinite place value in binary coded decimal (0.0010). Consequently a system based on binary coded decimal representation of decimal fractions avoids errors in representing and calculating such fractional values. (ii) Scaling by factor of 10 is simple, this is useful when a decimal scaling is needed to represent a non-integer quantity; for example in financial calculations. (iii) Rounding at a decimal digit boundary is simpler. The addition and subtraction in decimal does not require rounding. The Disadvantages of BCD Code are as follows (i) Some operations are more complex to implement. Adders require extra logic to cause them to wrap and generate a carry early. Fifteen to twenty percent of more circuitry is needed for BCD addition compared to pure Binary. Multiplication requires the use of algorithms that are some what more complex than shift - Mask - Add (ii) Standard BCD requires 4 bits per digit, roughly twenty percent more space than a binary encoding when packed so that three digits are encoded in ten bits, the storage overhead is greatly reduced, at the expense of an encoding that is unaligned with the 8 bit byte

‡‡ 1.48

NUMBER SYSTEM AND CODES

boundaries common on existing hardware, resulting in slower implementation on these system 1.7.1.2.1 BCD addition The steps followed for performing BCD addition are given as follows Step 1: Convert the decimal number to BCD codes Step 2: Add BCD number using rules of binary additions Step 3: Check result for each digit

i) It is said to be valid, if binary sum of each digit ≤ 9, then no correction is required ii) It is said to invalid, if binary sum >9 then go to step 4

Step 4: Add (0110)2 of 4 bit binary to the sum to get the correct

result

Example 1.49 Add 5 and 3 in BCD form Solution 5 3 8

= 0101 = + 0011 1000 (valid BCD since Sum 9 Add 6

} 4 Ans: 0100 1.7.1.2.3 BCD Subtraction using 10’s Complement Step 1: Find 10’s complement for the subtrahend. Step 2: Convert the numbers to BCD codes Step 3: Add check BCD validity rules Step 4: If carry exist discard the carry Step 5: If no carry the result in negative and it is in complemented formStep 6: Once again table 10’s complement and add a negative sign

‡‡ 1.52

NUMBER SYSTEM AND CODES

Example 1.57

Subtract 748 from 963 using 10’s complement

Solution

The 10’s complement of 748 is given as 999 = - 748 9’s complement of 786 = 251 Add 1 to LSD +1 10’s complement of 748 = 252 BCD code for 252 = 0010 0101 0010 BCD code for 963 =+1001 0110 0011

} }

1011 1011 0101

+0110 +0110 1 0010 0001 0101

Invalid BCD sum > 9

} } }

add 6 Discard carry

2

1

5

Ans: 0010 0001 0101 1.7.2 Non-Weighted Codes Non-weighted codes are codes that are non-positional weight 3. This means that each position within a binary number is not assigned a fixed value. Excess-3 and gray codes are examples for non-weighted codes. 1.7.2.1 Excess-3 Code Excess-3 is a non-weighted and complementary BCD code. During 1970's Excess-3 code were used on some older computers, in cash registers and in the hand held portable electronic calculators. It is a way to represent values with a balanced number of positive and negative numbers using a pre-specified number 3 as a biasing value. The Excess-3 is derived from 8421 BCD code by adding binary value (0011)2 to each code in 8421.

Decimal number

8421 BCD code + (0011)2

Excess - 3 code

‡‡ 1.53

The relationship between the four bit binary codes and Excess -3 codes are shown in table 1.8 Table 1.8 Relationship between 4 bit binary codes and excess 3 codes BCD code

Decimal

Excess-3 code

8 4 2 1

0

0 0 0 0

0 0 1 1

1

0 0 0 1

0 1 0 0

2

0 0 1 0

0 1 0 1

3

0 0 1 1

0 1 1 0

4

0 1 0 0

0 1 1 1

5

0 1 0 1

1 0 0 0

6

0 1 1 0

1 0 0 1

7

0 1 1 1

1 0 1 0

8

1 0 0 0

1 0 1 1

9

1 0 0 1

1 1 0 0

Example 1.58 Represent the given number (428)10 in excess-3 code Solution The Excess-3 representation for the given number (428)10 is obtained as given below 4 +3 7 0111

2 +3

8 +3

5 11 0101 1011 (excess -3 code) (or)

4 0100 + 0011 0111

2 0010 + 0011 0101

8 1000 8421 code + 0011 Add binary 3 1011 Excess -3 code

Excess -3 of 4 Excess -3 of 2 Excess -3 of 8 Ans: 0111 0101 1011

‡‡ 1.54

NUMBER SYSTEM AND CODES

1.7.2.1.1 Excess-3 addition The steps to perform Excess-3 addition is given as follows Step 1: Convert the given number to excess-3 code. Step 2: Add the two numbers using binary addition rule. Step 3: Check the sum i. If the sum is less than and equal to 9 (SUM ≤ 9) no correction is needed and go to step 4. ii. If the sum is greater than 9 (sum >9) and carry=0, then subtract binary 3 to the sum. iii. If carry=1, then add binary 3 to the sum. Step 4: The resultant number is in excess-3 code. Example 1.59 Add 8 and 6 using excess-3 addition. Solution Excess-3 of 8 = 1011 Excess -3 of 6 = +1001 carry exist 1 0100 +0011 0011 0100 0111

Add binary 3

Excess-3 of 1 Excess 3 of 4 Ans: 0100 0111 Example 1.60 Add 1 and 3 using excess-3 addition. Solution Excess -3 of 1 = 0100 Excess -3 of 3 = +1001 No carry 1010 Subtract 3 - 0011 0111 Excess-3 of 4 Ans : 0111 1.7.2.1.2 Excess-3 subtraction The excess-3 subtraction is performed by the following steps Step 1: Take complement for the negative number. Step 2: Add the complemented number to the other given number. Step 3: Check the sum (i) If the sum is greater than 9 (sum>9) and carry=0, then result is

‡‡ 1.55

negative and subtract binary 3 to the sum and once again take complement and add a negative sign. (ii) If carry=1, then the result is positive so, add binary 3 to the sum and do end around carry. (iii) The resultant number is in excess-3 code. Example 1.61 Find 8 - 6 using 9's complement Excess-3 subtraction. Solution Take 9’s complement for the negative number Subtract from 9 9’ s complement of 6

9 =-6 = 3

Add the complemented number to the other given number Excess-3 of 8 = 1011 Excess-3 9’s complement of 6 = + 0110 Carry exist 1 0001 0011 Add binary 3 End around carry +1 0101 Excess-3 of 2 Ans: +(0101) Example 1.62 Find 6 - 8 using 9's complement Excess-3 subtraction Solution Take 9’s complement for the negative number 9 Subtract from 9 = - 8 9’ s complement of 8 = 1 Add the complemented number to the other given number Excess-3 of 6 = 1001 Excess-3 9’s complement of 8 = + 0100 No carry 1101 Subtract 3 - 0011 1010 Sum >9

Subtract binary 3

Excess-3 of 7 (9’s complement form) Once again take 9’s complement of 7

‡‡ 1.56

NUMBER SYSTEM AND CODES

9 9’s Complement of 7 = - 7 2 Excess of 3 is = 5 = 0101

Ans: (0101)

Example 1.63 Subtract 8 From 5 Using Excess 3 Rule. Solution Take 9’s complement for the negative number 9 Subtract from 9 = 8 9’s Complement of 8 = 1 Add the complemented number to the other given number Excess 3 of 5 Excess 3 of 1 No carry Subtract 3

= 1000 =+ 0100 = 1100 (9’s complement form) - 0011 Excess-3 of 6 1001

Once again take 9’s complement of 6 9 Subtract from 9 = -6 9’ s complement of 6 = 3 Excess-3 of 3 is 0110 Ans : -(0110) 1.7.2.2 Gray code Gray code is an un-weighted code. The bit position in the code group do not have any specific weight assigned to them. Due to this gray code is not suitable for arithmetic operations but it finds operation in analog to digital converters. The most commonly used gray code is a four bit numeric code. Decimal numbers 0 to 15 are represented by 4 bit binary codes. This code is also known as unit distance code because two consecutive codes differs in only one bit positions. Gray Code is also referred to as reflected code Gray code is used for reducing the switching activity .Why do we say switching? It is because we represent a binary operation by a switch. A closed switch is '1' and an open switch is '0', so a switch has to be opened to make '1' as '0' and a switch has to be closed to make a 0 into

‡‡ 1.57

1. So four switches have to be closed or opened. When the circuit has to change the state from 7 to 8. The binary equivalent of '7' is 0111 and '8' is 1000. Therefore it is clear that all the switches have to be operated to change the state. Switching activity represents speed of operation, More the switching activity, more is the delay between change of states and thus lesser is the speed of operation. More is the switching activity between states, more will be the power consumption since switches are primarily made of transistors. The drawbacks of the binary code as switches can be rectified by using Gray code switches. For example, the state transition from 7 to 8 in decimal represented using gray code as 0100 and 1100 respectively. Therefore it is clear that only one switch as to be operated. Due to this one bit switching activity speed is improved, and consumes less power. The relationship between decimal code and gray code as shown in Table 1.9 Table 1.9 Relationship between decimal and gray code Decimal

Gray code

0

0000

1

0001

2

0011

3

0010

4

0110

5

0111

6

0101

7

0100

8

1100

9

1101

10

1111

12

1010

13

1011

14

1001

15

1000

1.7.2.2.1 Conversion from Gray to Binary code The gray to binary code conversion can be done using XOR logic.

‡‡ 1.58

NUMBER SYSTEM AND CODES

The steps for the conversion for the conversion are as follows Step 1: Write down the gray code value Step 2: The most significant bit of gray becomes Step 3: The MSB of binary is XOR with the next bit of gray code Immediately on its right. The result is the next bit of binary Step 4: Continuously XOR the bits following the above steps 3 until all the bits are completed Step 5: The binary equivalent of gray code is the result and the number of bits will be same as the gray code. Figure 1.7 Shows the gray to binary code conversion Gray code

Figure 1.7 Gray to binary code conversion Example 1.64 Convert gray code (1011011)g into binary code 1

0 +

1

1 +

1

1 +

0

0 +

1

1 +

1

1 +

0

1

Ans: (1101101)2 Example 1.65 Covert gray code (1011101)g into binary code 1

0

+ 1

1

1 +

1 +

0

1 +

1

0 +

0

1 +

0

1

Ans: (1101001)2 1.7.2.2.2 Conversion from binary to gray code The binary to gray code conversion is also done using XOR logic by following the steps given below Step 1: Write down the binary number Step 2: The MSB of binary is the MSB of gray code. Step 3: The MSB of binary number is then XOR with the next bit of

‡‡ 1.59

binary to its right. The result the next bit of gray. Step 4: Continuously XOR the bits following the above step until all the bits are completed Step 5: The gray code equivalent of binary is the result and the number of bits will be same as binary Figure 1.8 shows the binary to gray code conversion

Figure 1.8 Binary to gray code conversion

Example 1.66 Covert binary code (1101001)2 into gray code 1

+

1

1

+

0

0

+

1

1

+

1

0

+

1

0

+

0

1 1

Ans: (1011101)g Example 1.67 Covert binary code (1101101)2 into gray code 1

+

1

+

0

+

1

+

0

+

0

+

1

1 0 1 1 0 1 1 Ans: (1011011)g Unit distance code There will be a unit distance between two consecutive codes. The bit pattern for two consecutive number differ in only one bit position. Example: gray code. 1.7.3 Self complementing code The BCD 2421 code and Excess-3 code is an example of self complementary code. In this code the 1’s complement of Excess-3 code is excess 3 code of 9’s complement of corresponding decimal number. The 9's complement of a decimal number is found by subtracting each digit from the number 9. For example, the 9's complement of 4 is 5. The Excess-3 code for digital 4 is 0111. The 1's complement of this 1000, which is the excess 3 code for the decimal five (and 5 is the 9's

‡‡ 1.60

NUMBER SYSTEM AND CODES

complement of 4). The usefulness of the 9's complement and thus excess 3 terms from the fact that subtraction of a smaller decimal number from a larger number can be accomplished by adding the 9's complement (1's complement of Excess-3 code) of the subtrahend (in this case the smaller number) to the minuend and then adding the carry to the result. When subtracting a larger number from a smaller one, there is no carry and the result is in 9's complement form and negative this procedure has a distinct advantage over BCD in certain types of arithmetic logic. For example, the excess 3 code for 2 is 0101 1’s complement of 0101 is 1010 (This is the excess 3 code of 7) 9’s complement of 7 9 -7 2 0101 Therefore the 1's complement of Excess-3 code of 2 is equal to gray code of 9's complement of 2 1.7.4 Reflective codes A code is said to be reflective when the code for 9 is the 9’s complement of the code of 0, 8 for 1, 7 for 2, 6 for 3 and 5 for 4 while 2421, 5211 are reflective code, the 8421 code is not while finding the 9’s complement subtraction, reflectivity is desirable in a code. 1.7.5 Sequential codes A code is said to be sequential when each succeeding code in one binary number is greater than its preceding code. This greatly helps mathematical manipulation of data while 8421 is the sequential data, whereas 2421,5421 codes are not sequential code. 1.7.6 Alpha Numeric Code A binary digit or bit can represent only two symbols and it has only two states '0' or '1'. But this is not enough for communication between two computers, because we need many more symbols for communication. These symbols are required to represent twenty six alphabets with capital and small letters, numbers from 0 to 9, punctuation marks and other symbols. The alphanumeric codes are the codes that represent numbers and alphabetic characters. Mostly, such codes also represent other characters such as symbol and various instructions

‡‡ 1.61

necessary for conveying information. An alphanumeric code should at least represent 10 digits and 26 letters of alphabet, that is totally thirty six items. The following alpha numeric codes are very commonly used for the data representation. They are (i) American Standard Code for Information Interchange (ASCII) (ii) Extended Binary Coded Decimal Interchange Code (EBCDIC) 1.7.6.1 American Standard Code for Information Interchange (ASCII) A code used to represent letters of the alphabet and numerical characters are called as American standard code for information interchange. A 7 bit code for representing alpha numeric and control characters. It is a seven bit code used extensively for printers and large computer system. Many large computer system can also accommodate this code. The characters are assigned in ascending binary numbers. Sometimes an eighth bit 1 (or) 0 is used as parity bit, as shown in table 1.10 Table 1.10 American Standard Code for Information Interchange LSB

MSB 000

001

010

011

100

101

110

111

0000

NUL

DLE

SP

0

@

P

\

P

0001

SOH

DC1

!

1

A

Q

a

q

0010

STX

DC2

c

2

B

R

b

r

0100

EOT

DC4

$

4

D

T

d

T

0101

ENQ

NAK

%

5

E

U

e

u

0011

ETX

DC3

#

3

C

5

e

S

0110

ACK

SYN

&

6

F

V

f

v

0111

BEL

ETB

(

7

G

W

g

w

1000

BS

CAN

(

8

M

X

h

x

1001

HT

EM

)

9

I

Y

i

y

1010

LF

SUB

*

:

J

Z

j

z

1011

VT

ESC

+

1100

FF

FS

1101

CR

GS

1110

SO

1111

SI

;

K

[

k

{




N

US

/

?

0

¬

n

~

0

DEL

‡‡ 1.62



NUMBER SYSTEM AND CODES

The table 1.11 shows the definition of control abbreviations Table 1.11 Definition of control abbreviations ACK -Acknowledge

FS- Form separator

BEL -Bell

GS-Group separation

BS-Backspace

HT-Horizontal tab

CR - Carriage return

LF- Line feed

DC1-DC4- Direct control

NAK -Negative acknowledge

DEL- Delete IDLE

NUL-Null

DLE-Data link space

RS-Record Separator

EM-end of medium

SI-Shift In

ENQ-Enquiry

SO-Shift out

EOT - End of Transmission

SOH-Start of heading

ESC-Escape

SUB-Substitute

ETB-END of Tranmission Block

SYN -synchronous Idle

ETX-End Text

US -Unit separator

FF - Form feed

VT - Vertical

1.7.6.2 Extended Binary Coded Decimal Interchange Code (EBCDIC) Extended Binary coded Decimal interchange code. An 8 bit code for representing alphanumeric and control characters. The table 1.12 shows the definition of control abbreviations for EBCDIC. For proper communication we need to represent numbers, letters and symbols. EBCDIC code as shown in table 1.13 is used most of large computers for communication, it is eight bit code and uses BCD (Binary coded decimal). This code also includes capital alphabets, lower case alphabets, numbers 0-9 and special symbols. eg: C = 11000011 Table 1.12 Definition of control abbreviations for EBCDIC BS-Backspace

LC-Lower case

BYP-Bypass

LF-Line feed

CC-Cursor control

NL-New line

CU1-Customer use (CU1-CU3)

PF-Punch off

DL-Delete

PN-Punch ON

EOB-End of block

PRE-prefix

EOT -End of transmission

RES -Restore

FS-Field separation

RS-Reader start

HT-Horizontal tab

SM-Set mode

IL-IDLE

SP-Space

TM-Tape Mark

UC-Upper case

2,3

Bit position

"

?

1

1111

-

(

-

,

(

1101

# @

'

:

! %

C *

CU3

UC EOT

11

$

CU2

PN RS

-

& ,

10

01


9 Input

Output

S3

S2

S1

S0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

1

1

0

0

1

0

0

0

0

1

0

1

0

0

1

1

0

0

0

1

1

1

0

1

0

0

0

0

1

0

0

1

0

1

0

1

0

1

1

0

1

1

1

1

1

0

0

1

1

1

0

1

1

1

1

1

0

1

1

1

1

1

1

}

}

Valid number. Therefore no change add 0000

Invalid number. Therefore add (0110)2

‡‡ 3.25

From the table 3.8, the logic expressions to check the sum greater than 9 is found using K-map is shown in figure 3.23

S

S2 3

S0 S 1 00

01

11

10

0

1

3

2

4

5

7

6

00



01 12

11

1 8

10

13

1

15

1 9

14

1 11

1

10

1

S3S2 S3S1

= y

S 3S 2 + S 3S1

Figure 3.23 K-map to Check sum > 9 If sum > 9 or carry C out =1, then the BCD sum is invalid In both condition add ( 0110 )2 to convert invalid BCD sum into valid BCD sum. Let us consider two numbers whose sum is greater than 9. For example, 5= 0101 5 = ( + ) 0101 1010 > 9 The logic expression ‘y’ represents the sum is greater than 9. The BCD adder algorithim adds (0110)2 not only for sum is greater than 9 but also when two four bit number are added and the sum result in a five bit value i.e., fifth bit is output carry bit which is equal to ‘1’, then (0110)2 is added. Therefore, let us consider K = y+c which is equal to 1 when either sum > 9 from figure 3.23 or ‘c’ represents the (fifth bit) output carry bit is ‘1’. The two BCD numbers together with input carry are first added in the top 4 bit binary adder to produce a binary sum. When the output carry of binary adder2 is equal to zero (i.e, when sum ≤ 9 and Cout of top 4 bit binary adder1 = 0) then the output carry generated from the bottom binary adder2 can be ignored, since it supplies information already available at the output carry terminal. When the output carry of the bottom binary adder2 is 1, then it becomes the next digit in the BCD adder.

‡‡ 3.26

COMBINATIONAL LOGIC CIRCUIT

Cout Detection circuit Correction factor 0

6

{K 1

0

1

0

B3

B2 B1

1

B0

0

1

0

1

A3 A2 A1 A0

4 binary adder 1

0

Cin=0

S3 S2 S1 S0 1

0

0

1 0

Check sum for validity 1 0 1 0 >9 0 1 1 0 add 6 1 0000

1

{0 1 Cout

0

B3

B2 B1

A3 A2 A1 A0

B0

4 binary adder 2 S3 S2 S1 S0

1

0

0

0

0

}

}

0 0 0 1

Cin

0

Figure 3.24 BCD adder

The BCD system was chosen for the internal number system because it is very easy to convert it to alpha numeric representation for printouts and displays. The compelling advantage of BCD have wanted over time and these digits are supported by more modern hardware simply to provide backward compatibility with earlier generation of machines. 3.8 BCD SUBTRACTOR The BCD subtraction can be performed using several methods. It can be done by 1’s complement, 9’s complement or 10’s complement method. Among all these method 9’s or 10’s complement is the most easiest. 3.8.1 BCD Subtractor using 9’S Complement The steps to perform BCD subtractor using 9’s complement is given below Step 1: Find 9’s complement for the negative number. Step 2: Add two numbers using BCD addition and check its sum. Step 3: If sum > 9, add 6 (0110)2. Step 4: If carry is generated add carry to the result otherwise find 9’s complement of the result. The 9’s complement of negative number is found by first inverting the number and by adding 10 (1010)2 to it with Cin= 0. If carry exist ignore carry.

‡‡ 3.27

0 1 0

1

1

1 1

0 1

1 1

+5V Logic (1)

0

Logic (0)

Cout

0

}

BCD input A

1

0

1

1

A3 A2 A1 A0 B3 4-bit adder 2

0

1

0

Logic (0)

1 0

Cout=1

1

1

0

0

0

Logic (0) Cout Ignored

0

B2 B1

B0

S3

B3 3

0 0

0

1

4-bit adder

0

1

1

A3 A2 A1 A0

0

B2 B1 B0 0 1 0 S2 S1 S0

0

1

1

}

0 1 S1 S0

1 0 0 00 0 0

4 0

0

1

S3

S2

S1

9’s complement circuit

4

1

S1 S0

0 1 1 B2 B1 B0 0 S2

}

9’s complement of BCD input B

1 0 0 0 B3 B2 B1 B0

A3 A2 A1 A0 4-bit adder

0 S3

S2

Cin=0

}

B3 A3 A2 A1 A0 4-bit adder 1 1 S3

Cout=1

9’s complement for -5 -5 = 0101 B =exorinput =1010 A =add 10 = 1010 1 0100

Cin

1 Cin

0 S0

Cin=0

A =0111 B =0100 1011≥9

B C D addition’s check sum > 9 if add 6

}

1+

A= 1011 B = + 0110 1 0001

If carry = 0, A = 0000 find 9’s complement B = 0001 of the sum, Cin = 1 If carry =1 0010 perform end around carry

} Ans = 2

Figure 3.25 BCD Subtractor circuit using 9's complement

The figure 3.25 shows BCD subtractor circuit using 9’s complement. To explain let us take two BCD number 7 and 5 to be subtracted using 9’s complement. The manual method of subtraction as such cannot be implemented in circuit therefore slight modification is done to get the 9’s complement for -5. Convert 5 to its equivalent BCD and invert the number by using Ex-OR is one input to the first 4 bit adder and the other input is (1010)2. Both BCD numbers added gives a sum 0100 and a carry 1 which is ignored. The sum gives the 9’s complement for -5. For the second 4 bit adder one input is sum from the first adder and other is the A value 7 (i.e., 0111). Both values are added and gives a sum of 1011 which is greater than 9. Therefore to check the sum a circuit is implemented and is shown in BCD adder (section 3.7). The result is given to the third 4 bit adder. The two numbers are added and the sum is given to the fourth 4 bit adder where it checks carry and carry out is given to Cin of fourth binary adder. If carry is equal to 0 find 9’s complement of the circuit else carry equal to 1,then it performs end around carry. EX-OR gates are used to check carry. The sum output of fourth adder gives BCD subtractor result (0010)2.

‡‡ 3.28

COMBINATIONAL LOGIC CIRCUIT

3.8.2 BCD Subtractor using 10’S Complement

The steps to perform BCD subtraction using 10’s complement is

given below Step 1: Find 10’s complement of negative numbers Step 2: Add two numbers using BCD addition Step 3: If sum >9, add 6 Step 4: If carry is generated, discard carry to the result otherwise find 10’s complement of the result. Step 5: The 10’s complement of negative number is found by first inverting the number and by adding (1010)2 to it with Cin =1. If carry exist discard carry. 0

0

1 A3

0

1 A2

A1

1 B3

A0

0

1

1

1 0 0 B2 B1 B0

Cin=1

4-bit adder 1 S3 S2 S1 S0

Cout

0 1

0 1

IC7483

Cout

1

0

A2

A3

1 A1

1

B3 B2

A0

4-bit adder S3

S2 1

1

0

1

B1

B0

Cin=0

2

S1 S0 0 0 1

IC7483

0 0 A3

Ignored

1

1

A2

A1

0 1 B3

A0 S3

0

Ignored 0

0 B0

S2 S1 S0 0 0 1 0

0

0

A3 0

0

}

B = 0101 XOR = 1010 A = 1010 Cin = 1 1 0101

0

1

0

1

B C D output

0

0

0 B0

IC7483

Cin

}

A =0111 B =0101 1100 >9

BCD addition check sum >9 carry =1

A =0110 B =1100 1 0010

Sum of A and 10’s complement of B

0

B3 B2 B1 A2 A1 A0 0 0 0 4-bit adder 4 S3 S2 S1 S0 0

Cin=0

IC7483

0

0 Cout

1 0 B2 B1

4-bit adder 3

Cout

10’s complement circuit

10’s complement of BCD input B

}

BCD input (operand 1) A

}

+ 5 V Ex-OR gates act as invertors. Inverted BCD Input B

If carry =0 circuits finds 10’s complement of the result If carry =1 circuit performs 0 + B + 0 = B

A = 0000 B = 0010 0010 Ans

Figure 3.26 BCD Subtractor using 10's complement



The figure 3.26 shows BCD subtraction circuit using 10’s

complement. To explain let us take the same value 7-5 as A-B (ie) A+(-B). Convert 5 of B to its equivalent BCD and invert the number

‡‡ 3.29

by using EXOR and is given as one input to the first 4 bit adder and the other input as (1010)2 and also Cin should be given 1 to get 10’s complement output. Other steps are same as the 9’s complement circuit. Both numbers added gives a sum of 0101 and a carry ‘1’ which is ignored. The sum gives the 10’s complement for -5. For the second 4 -bit binary adder one input is sum from the first adder and the other is the A value 7 (ie., 0111). Both values are added and gives a sum of 1100 which is greater than 9. Therefore to check the sum a circuit is implemented. The result is given to the third 4-bit adder. The two numbers are added and the sum is given to the fourth 4 bit adder where it checks carry and carry out is given to Cin of fourth binary adder. If carry =0 find 10’s complement of the circuit else carry =1, perform discard carry. Ex-OR gates are used to check carry. The sum output of fourth adder gives BCD subtractor result (0010)2. 3.9 EXCESS-3 ADDER

The steps to perform Excess-3 addition is given below

Step 1: Add two Excess-3 number. Step 2: If Carry =1, add (0011)2 to sum If Carry = 0, subtract (0011)2 (ie) add 1101,which is 2’s

complement of 3.

Step 3: Discard carry.

Let us take an example to add excess 3 of 1 with 2.

}

Excess-3 of 1 = 0 1 0 0 Excess-3 of 2 = 0 1 0 1 carry =01001 +1101 discard 10110 the carry

carry Add 3 Add 13

0 0 1 1 1 1 0 1

Complement Excess-3 of 3

Sum

‡‡ 3.30

COMBINATIONAL LOGIC CIRCUIT

The figure 3.27 shows the Excess-3 adder circuit.

Carry = 0

0

1

A3

A2 A1 A0

0

0

1

1 Cout Ignored

} Digit 1

0

1

1

A3

A2 A1 A0

0

1

0

1

B3 B2

B1

B0

0

4-bit adder 1

0

0 0

0

S3

S2

1

0

S1 S0 0

1

B1

B0

Cin=0

1 B3 B2

4-bit adder 2

S3 S2

S1 S0

0

1

1

Cin=0

0

} Digit 0

Figure 3.27 Excess - 3 adder

3.10 EXCESS -3 SUBTRACTOR

The steps to perform Excess -3 Subtraction is given below

Step 1: Take 1's complement for the subtrahend Step 2: Add complemented subtrahend the minuend Step 3: If carry =1, result is positive. Add 3 and endaround carry Step 4: If carry =0, result is negative, then subtract 3 i.e., add 13 and take 1’s complement for the result. Excess-3 subtraction is explained with the example given below

Excess-3 of 8 = 1 0 1 1 Complement of 5 =0111 in Excess-3 10010 Add 3 0011 +1 0110

}

Note: Excess-3 of 5 =1000 1’s complement = 0 1 1 1 of (excess-3) 5 end around carry

}

Ans: Excess-3 of 3

‡‡ 3.31

The Figure 3.28 shows the Excess-3 subtractor circuit B3

Minuent 1 A3

0 A2

1 A1

1

Subtrahend 0 0 0 B2 B1 B0

0 Cout=1

1

1

4-bit parallel adder

0

Cin

1

0

0

A3

A2

1

}

1’s complement circuit

1 Cin

S3 S2 S1 0 0 1 0

M=1

1 A0

S0 0

1

A1

A0 Cout Ignored

4-bit parallel adder 0

0

0

1

0

1

0

0

Figure 3.28 Excess-3 Subtractor

3.11 BINARY MULTIPLIER 3.11.1 Two by Two Binary Multiplier The 2 x 2 binary multiplier requires to half adder and four AND gates. These four AND gates are used to generate partial products while the half adder are used to add the partial products. This results in the multiplication factor of P3, P2, P1, P0. The each multiplication result obtained represents a bit in the total 4 bit answer. The procedure for implementing 2 x 2 binary multiplier is as follows 0 0 1 1

x x x x

0 1 0 1

= = = =

0 0 0 1

A1 A0 1 1 B1 B0 1 1 Carry 1 1 1 11 x 1 0 0 1 P3 P2 P1 P0

Carry of P1 B1A1 P3

P2

A1 x B1 B0A1 B1A0 P1

Carry of P2

A0 B0 B0A0 P0

P0=B0A0 P1=B0A1+B1A0 P2 =B1A1+ Carry out of P1 P3 = Carry out of P2

‡‡ 3.32

COMBINATIONAL LOGIC CIRCUIT

The figure 3.29 shows the logic diagram for a 2 x 2 bit binary multiplier 1

1

1

B1 A1

1

1

B0 A1 1

1 1

1

1

B1 A0

1

1

1

1

B0 A0

1

1

1

1

P3 1

P1

P2

0

0

P0 1

Figure 3.29 Two x Two Binary multiplier

3.11.2 Four bit binary multiplier using Shift method The multiplication can be done using Shift method let us assume two four bit binary numbers 1011 and 1100 then 1 0 1 1 Multiplicand X 1 1 0 0 Multiplier 0 0 0 0 Partial product 1 0000 Partial product 2 1011 Partial product 3 Partial product 4 1011 10000100 P7 P6P5 P4 P3P2 P1 P0

From the above example it is understood that if the multiplier bit is '0' then the partial product is '0' if the multiplier bit is '1' then the multiplicand is simply copied as a partial product. Whenever, a partial product is obtained, it is shifted one bit to the left of the previous partial product. This process is continued until all the multiplier bits are checked and then the partial products are added. Y Register X Register X4 X3 X2 X1 X0 Y3 Y2 Y1 Y0 (Multiplier register) 4 bit parallel adder M3 M2 M1 M0

M Register (Multiplicand register)

Figure 3.30 Four Bit binary multiplier using shift method

‡‡ 3.33



The figure 3.30 shows the 4 bit binary multiplier using shift

method stored in register Y (Y3Y2Y1Y0) the 4 bit multiplicand is stored in register M (M3M2M1M0) and the X register (X4X3X2X1X0) is initially cleared to 00000. Here to perform multiplication the least significant bit of multiplier bit (Y0) is checked whether it is 0 or 1. If Y0 =1 the number in the multiplicand register (M) is added with the least significant 4 bit of X register where X4 is to store carry in addition process and the combined X and Y register is shifted to the right by 1 bit. If Y0 =0 the combined X and Y register is shifted to the right by 1 bit without performing any addition. This process has to be repeated 4 times to perform 4 bit multiplication. The multiplication result will be available in X and Y register. 3.11.3 Four by Four binary multiplier

The 4 x 4 binary multiplier is nothing but parallel multiplier

where the speed of multiplication is increased at the cost of increased hardware. The 4 x 4 multiplier requires three 4 bit binary adders and 16 AND gates. Here the AND gates are used to generate partial products while 4 bit parallel adders are used to add the partial products. Both the operations are done parallel therefore the multiplication results are P7,P6,P5,P4,P3,P2,P1,P0 will be available at the output immediately after the propagation delay in the multiplier circuit. The each multiplication result obtained represent a bit in the total 8 bit answer. The 4 x 4 binary multiplier implementation procedure is given below. A3 B3

A2 B2

A1 B1

A0 B0

B0A3 B0A2 B0A1 B0A0 B1A3 B1A2 B1A1 B1A0 x B2A3 B2A2 B2A1 B2A0 x B3A3 B3A2 B3A1 B3A0



P7 P6

P5

P4

P3

4 bit adder 4 bit adder 4 bit adder

x P2

P1

P0

The Figure 3.31 shows the logic diagram for 4 x 4 bit binary multiplier

‡‡ 3.34

COMBINATIONAL LOGIC CIRCUIT

B0 B1

A3

Y3 CIN = 0

A2

Y2

A1

Y1

A3

A0

X3

Y0

X2

X1

A0

A1

X0

4 Bit Adder1 Cout B2

A3

Y3 CIN = 0

A2

Y2

A1

Y1

S3

S2

S1 S0

A0

Y0

X3

X2

X1

X0

4 Bit Adder2 Cout B3

CIN = 0

A2

A3

A2

A1

S3

S2

S 1 S0

A0

4 Bit Adder3 Cout

P7

S3 P6

S2

S1

S0

P5

P4

P3

P2

P1

P0

Figure 3.31 Four x Four binary multiplier

The product terms obtained by multiplying four by four binary multiplier are as follows. P0=A0B0 P1=B0A1+B1A0 P2=B0A2+B1A1+B2A0+P1 Carry P3=B0A3+B1A2+B2A1+B3A0+P2 Carry P4=B1A3+B2A2+A3A1+P3 Carry P5=B2A3+B2A2+P4 Carry P6=B3A3+P5Carry P7=P6 Carry

‡‡ 3.35

3.12 BINARY DIVIDER The division is the most difficult and time consuming operation for a general purpose computer. The block diagram of a binary divider unit using restoring technique for division is shown in figure 3.32 X Register X3 X2 X1 X0

Y Register Y3 Y2 Y1 Y0 (Dividend register)

4 bit parallel adder/Subtractor D3 D2 D1 D0

D Register (Divisor register)

Figure 3.32 Four bit binary divider Here the dividend is stored in the dividend register Y (Y3Y2Y1Y0) the divisor is stored in the divisor register D (D3D2D1D0) and initially the X register (X3X2X1X0), is cleared. The procedure for division operation using the circuit is explained as follows 1. Shift the combined content of X and Y registers to the left by one bit. 2. Perform trial subtraction by subtracting the content of D register from the content of register. 3. If there is no borrow in the subtraction, put 1 in the LSB of Y register, else restore the original content of X register by adding the contents of D register with the contents of X register. 4. Repeat steps 1 to 3 for n times, where n is the number of bits in the dividend. For a 4 bit division n = 4. Now, the quotient will be available in the Y register and the remainder will be in the X register. The above procedure can be understood in a better manner with the following example. Consider the division 1011(11) by 0011(3). The dividend and divisor are stored in Y and D registers respectively, and the X register is initially cleared to 0. Therefore, Y3Y2Y1Y0 = 1011 X 3 X 2 X1X 0 = 0000 D3D2D1D0 = 0011

Here both divisor and dividend are 4-bit numbers. Therefore,

‡‡ 3.36

COMBINATIONAL LOGIC CIRCUIT

steps 1-3 have to be repeated four times. 1 cycle Step 1 Shift the combined contents of X and Y to the left one bit. Therefore XY = 0001 0110 Step 2 Subtract dividend 0011 from register resulting in X = 1110 with borrow =1 Step 3 Since borrow = 1, restore the original content in X register by adding dividend 0011 with the content of X register 1110. Now, XY = 0001 1100 II Cycle Step 1 Shift the combined contents of X and Y to the left by one bit. Therefore, XY =0010 1100 Step 2 Subtract dividend 0011 from register X resulting in X = 1111 with borrow =1 Step 3 Since borrow =1, restore the original content in X register by adding dividend 0011 with the content of X register 1111. Now, XY = 0010 1100 III cycle Step 1 Shift the combined contents X and Y to the left by one bit. Therefore, XY = 0101 1000 Step 2 Subtract dividend 0011 from register X which results in X = 0010 with borrow = 0 Step 3 Since borrow = 0, put 1 in the LSB of Y register (Y0). Therefore XY = 0010 1001 IV Cycle Step 1: Shift the combined contents of X and Y to the left by one bit. Therefore, XY =0101 0010 Step 2: Subtract dividend 0011 from X register resulting in X = 0010 with = 0 Step 3: Since borrow = 0, put 1 in the LSB of Y register (Y0), Therefore, XY = 0010 0011 Now the quotient 0011(3) is available in the Y register and the remainder 0010 (2) is available in the X register

‡‡ 3.37

3.13 CODE CONVERSION There is a wide variety of binary codes used in digital systems. Some of these codes are binary -coded-decimal (BCD), Excess-3, Gray code and so on. Each code has different advantages and application. Therefore, it is required to convert one code to another. 3.13.1 Binary to BCD Code Converter The truth table for binary to BCD converter is given in table 3.9. Table 3.9 Binary to BCD Code





Input binary code

Output BCD Code

D

C

B

A

B4

B3

B2

B1

B0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

1

0

0

1

0

0

0

0

1

0

0

0

1

1

0

0

0

1

1

0

1

0

0

0

0

1

0

0

0

1

0

1

0

0

1

0

1

0

1

1

0

0

0

1

1

0

0

1

1

1

0

0

1

1

1

1

0

0

0

0

1

0

0

0

1

0

0

1

0

1

0

0

1

1

0

1

0

1

0

0

0

0

1

0

1

1

1

0

0

0

1

1

1

0

0

1

0

0

1

0

1

1

0

1

1

0

0

1

1

1

1

1

0

1

0

1

0

0

1

1

1

1

1

0

1

0

1

‡‡ 3.38

COMBINATIONAL LOGIC CIRCUIT

The logical expression B0, B1, B2, B3 and B4 are obtained by K-map simplification as shown in figure 3.33 (a), (b), (c), (d), (e) BA

DC 00 01 11 10

BA 00 01 11 10 0 2 3 1 0 1 1 0 4 0 1 5 17 06 15 14 13 012 1 1 0 9 8 0 1 111 010

DC 00 01 11 10

B0=A

DC 00 01 11 10 DC CB

00 01 11 0 3 1 0 0 0 4 1 4 1 55 1 7 15 0 12 0 13 1 9 8 0 0 0 11

10 2 0 16 14 1 0 10

B2=DC + CB

(b) K-map for B1 BA DC 00 01 11 10

00 01 11 0 0 0 1 03 4 0 0 5 07 0 12 0 13 0 15 9 8 1 1 0 11

DCB

B3=DCB

(c) K-map for B2 BA 00 DC 0 00 0 4 0 01 12 11 1 12 10 0 8 DC

DB

B1=DCB + DB

DCB

A (a) K-map for B0 BA

00 01 11 10 0 2 3 1 0 0 1 1 4 0 05 17 16 15 14 1 12 113 0 0 9 8 0 0 0 11 0 10

10 02 06 0 14 0 10

(d) K-map for B3 01 11 3 1 0 0 0 5 0 7 15 13 113 1 15 11 0 9 1 11

10 2 0 06 14 1 14 10 1 10

DB

B4=DC + DB (e) K-map for B4

Figure 3.33 K-map Simplification The logic diagram for binary to BCD code converter is implemented using logic gates as shown in figure 3.34.

‡‡ 3.39

}

Input binary code D

C

B

A

}}

B0

B1

LSD

B2

B3

}

B4

BCD code

MSD

Binary to BCD converter

Figure 3.34 Logic Diagram for binary to BCD converter 3.13.2 BCD to Binary Code Converter The truth table for BCD to binary code converter is given in the table 3.10 Table 3.10 BCD to Binary code Input BCD code

Output binary code

B4

B3

B2

B1

B0

E

D

C

B

A

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

1

0

0

0

1

0

0

0

0

1

0

0

0

0

1

1

0

0

0

1

1

0

0

1

0

0

0

0

1

0

0

‡‡ 3.40

COMBINATIONAL LOGIC CIRCUIT 0

0

1

0

1

0

0

1

0

1

0

0

1

1

0

0

0

1

1

0

0

0

1

1

1

0

0

1

1

1

0

1

0

0

0

0

1

0

0

0

0

1

0

0

1

0

1

0

0

1

1

0

0

0

0

0

1

0

1

0

1

0

0

0

1

0

1

0

1

1

1

0

0

1

0

0

1

1

0

0

1

0

0

1

1

0

1

1

0

1

1

0

1

0

0

0

1

1

1

0

1

0

1

0

1

0

1

1

1

1

1

0

1

1

0

1

0

0

0

0

1

0

1

1

1

1

0

0

0

1

1

1

0

0

0

1

0

0

1

0

1

1

0

0

1

1

0

0

1

1



The logical expression for A,B,C,D,E are obtained by K-map simplification as shown in figure 3.35 (a), (b), (c), (d), (e). B4 = 0 B4 = 1 B1B0 B1B0 B3B2 00 01 11 10 B3B2 00 01 11 10 17 18 0 19 16 2 3 1 00 00 0 1 1 0 0 1 1 0 22 4 23 01 01 0 15 17 06 0 20 1 21 1 0 29 28 31 30 15 14 11 11 X 12 X13 X X X X X X 9 8 24 25 27 26 10 10 0 1 X 11 X 10 0 1 X X A=B0 (a) K-map for A B1B0 B3B2 00 0 00 0 4 01 0 11 X 12 8 10 0 B1B4

B4 =0 01 0 1 0 5 X 13 9 0

11 1 3 1 7 X 15 X 11

10 1 2 1 6 X 14 X 10

B4 =1 B1B0 B3B2 00 01 11 10 17 18 00 1 16 1 0 19 0 01 1 20 1 21 0 23 0 22 X 28 X 29 X 31 X 30 11 1 24 125 X 27 X 26 10

B = B1B4+B1B4 = B1 + B4 (b) K-Map for B

B1B4

‡‡ 3.41

B4 = 0 B4 = 1 B1B0 B1B0 B2B1 B3B2 00 01 11 10 B3B2 00 01 11 10 17 18 0 2 3 1 00 0 16 0 1 19 1 0 0 0 00 0 4 01 120 121 0 23 0 22 1 1 5 17 16 01 28 X29 X 31 X 30 11 X 12 X13 X 15 X 14 11 X 9 8 0 24 025 X 27 X 26 0 0 X11 X10 10 10

B4B2B1

C = B4B2+B2B1+ B4B2B1 B4B2

(c) K-map for C

B4 = 0 B1B0 B3B2 00 01 11 10 0 2 3 1 00 0 0 0 0 4 6 7 5 01 0 0 0 0 15 14 13 12 11 X X X X 9 8 11 10 10 1 1 X X B4B3

B4 = B1B0 B3B2 00 01 17 16 00 1 1 20 21 01 1 1 29 28 X X 11 24 25 0 0 10 B4B3B2

1 11

10

19

1 23 0 31 X 27 X

B4B3B1

18

1 22 0 30 X 26 X

D =B4B3+B4B3B2 +B4B3B1 (d) K-Map for D

B4 = 0 B1B0 B3B2 00 01 11 10 0 2 00 0 01 03 0 4 01 0 0 5 07 06 11 X 12 X13 X 15 X 14 9 8 10 0 0 X 11 X 10

B4 = 1 B1B0 B3B2 00 01 11 17 19 16 00 0 0 0 23 01 0 20 0 21 1 29 X 28 X X 31 11 24 25 27 1 1 X 10

10 18

0 22 1 X 30 X 26

B4B2B1 B4B3

E = B4B2B1+B4B3 (e) K-map for E Figure 3.35 K-map Simplification The logic diagram for BCD code to Binary code converter is implemented using logic gate as shown in figure 3.36.

‡‡ 3.42

COMBINATIONAL LOGIC CIRCUIT

}

Input BCD code B4

B3

B2

B1

B0

A B

C

D

E

}

Binary Code

Figure 3.36 Logic Diagram for BCD to Binary Code Converter

‡‡ 3.43

3.13.3 BCD to Excess -3 Code Converter The Excess-3 is modified form of BCD; the Excess-3 code is derived by adding 3 to BCD number. The truth table for BCD to Excess-3 code is given in table 3.11 Table 3.11 BCD to excess -3 code Output

Input BCD

Excess-3 code

B3

B2

B1

B0

E3

E2

E1

E0

0

0

0

0

0

0

1

1

0

0

0

1

0

1

0

0

0

0

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

0

0

1

1

1

0

1

0

1

1

0

0

0

0

1

1

0

1

0

0

1

0

1

1

1

1

0

1

0

1

0

0

0

1

0

1

1

1

0

0

1

1

1

0

0

The logical expression for E0,E1,E2,E3 are obtained by K-Map simplification as shown in figure 3.37 (a),(b),(c),(d). For E0 B1B0 B3B2 00 0 00 1 4 01 1 11 X 12 10 1 8

01 0 1 0 5 X 13 9 0

B0

11 03 07 X 15 X 11

10 2 1 16 X 14 X 10

E0= B0 (a) K-map for E0

B1B0 00 0 00 1 4 1 01 11 X 12 8 10 1

B3B2

B1B0

For E1 01 1 0 0 5 X 13 9 0

11 10 2 3 1 0 1 7 0 6 15 14 X X X 11 X 10

E1= B1 B0+ B1B0 =B1  B0 (b) K-map for E1

B1B0

‡‡ 3.44

COMBINATIONAL LOGIC CIRCUIT

B1B0 B3B2 00 0 00 0 4 01 1 B2B0 11 X 12 10 0 8 B2B1B0

For E2 01 1 1 0 5 X 13 9 1

11 10 13 12 07 06 X 15 X 14 X 11 X 10

E2=B2B1B0+B2B0+B2B1 = B2B1B0+B2(B0+B1) =B2(B1+B0)+B2(B0+B1) =B2⊕(B1+B0) (c) K-Map for E2

B1B0 B3B2 00 0 00 0 4 B2B1 01 0 11 X 12 8 10 1

For E3 01 01 15 X 13 9 1

11 10 03 02 17 16 X 15 X 14 X 11 X 10

B2B1 B2B0 B3

\E3 =B2B0+B2B1+B3 = B3 + B2 (B0+B1) (d) K-map for E3

Figure 3.37 K-map Simplification

The logic diagram for implementation of BCD to excess-3 code using logic gates is shown in figure 3.38 Input BCD Code B3

B2

B1

B0

E0

E1

E2

E3

Figure 3.38 BCD to Excess-3 code converter

}

Excess 3 code

‡‡ 3.45

3.13.4 Excess-3 Code to BCD Code Converter The truth table for the Excess -3 code to BCD Code is given in table 3.12. Table 3.12 Excess -3 to BCD code Input Excess-3 Output BCD E3

E2

E1

E0

B3

B2

B1

B0

0

0

1

1

0

0

0

0

0

1

0

0

0

0

0

1

0

1

0

1

0

0

1

0

0

1

1

0

0

0

1

1

0

1

1

1

0

1

0

0

1

0

0

0

0

1

0

1

1

0

0

1

0

1

1

0

1

0

1

0

0

1

1

1

1

0

1

1

1

0

0

0

1

1

0

0

1

0

0

1

The logical expression for B0, B1, B2, B3 obtained by K map simplification are shown in figure 3.39 (a), (b), (c),(d) E 1E 0 E 1E 0 E 3E 2 E 3E 2 00 01 11 10 00 01 11 10 0 2 0 2 3 1 E 1E 0 X1 03 X 00 X X 0 X 00 X 4 6 4 7 5 6 7 5 1 0 0 1 01 1 0 1 01 0 15 13 12 11 1 X X X14 11 0 12 X13 X 15 X14 E 1E 0 9 9 10 1 8 0 0 11 110 10 0 8 1 011 110 E0

B1= E1E0+E1E0 =E1⊕ E0 (b) K-map for B1

B 0= E 0

(a) K-map for B0 E 1E 0 00 0 00 X 4 01 0 11 0 12 8 10 1

E 3E 2

E 2E 1

01 1 X 05 X13 9 1

11 3 0 17 15 X 0 11

E 1E 0 E 2E 1E 0 E E 10 00 3 2 2 0 X 00 X 6 4 0 01 0 14 E E E 3 1 0 X 11 1 12 10 8 1 10 0

B2=E2E1+E2E1E0+E3E1E0 (c) K-map for B2

01 1 X 05 X13 9 0

11 3 0 07 15 X 1 11

10 2 X 06 14 X 0 10

B3=E3E2+E3E1E0 (d) K-Map for B3

Figure 3.39 K- map simplification

E 3E 2 E 3E 1 E 0

‡‡ 3.46

COMBINATIONAL LOGIC CIRCUIT

The logic diagram for Excess-3 to BCD code converter using logic gates is shown in figure 3.40. Excess 3 Code E3

E2

E1

E0

B0

B1

B2

B3

Figure 3.40 Excess 3 to BCD Code Converter

}

BCD code

‡‡ 3.47

3.13.5 Binary to Gray Code Converter The truth table for binary to gray code converter is shown in table 3.13. The Logical expression for G0, G1, Table 3.13 Binary to Gray code G ,G are obtained by K-Map sim2 3 plification are shown in figure 3.41 Output Gray

Input Binary code

code

D

C

B

A

G3

G2

G1

G0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

1

0

0

0

1

1

0

0

1

1

0

0

1

0

0

1

0

0

0

1

1

0

0

1

0

1

0

1

1

1

0

1

1

0

0

1

0

1

0

1

1

1

0

1

0

0

1

0

0

0

1

1

0

0

1

0

0

1

1

1

0

1

1

0

1

0

1

1

1

1

1

0

1

1

1

1

1

0

1

1

0

0

1

0

1

0

1

1

0

1

1

0

1

1

1

1

1

0

1

0

0

1

1

1

1

1

1

0

0

0

(a),(b),(c),(d). BA DC 00 0 0 00 4 0 01 11 0 12 8 10 0

01 11 10 1 1 03 12 1 5 0 7 16 1 13 0 15 1 14 9 1 0 11 1 10

BA

G0= BA+ BA =B ⊕ A (a) K-map for G0 DC

BA 00 01 11 10

00 01 11 10 0 0 0 1 13 12 1 4 1 5 07 06 1 12 113 0 15 0 14 0 8 0 9 1 11 1 10

CB CB

G1= CB+ CB =C ⊕ B (b) K-map for G1

BA BA DC 00 01 11 10 DC 00 01 11 10 0 0 2 3 1 0 1 03 02 00 0 0 0 0 DC 00 0 4 6 7 5 4 1 1 1 1 6 01 0 5 07 0 01 0 15 14 13 12 11 0 15 14 0 0 0 13 1 1 11 1 12 1 DC 9 8 11 10 9 8 10 1 1 1 1 10 1 1 1 11 1 10 G2= DC+DC =D ⊕ C (c) K-map for G2

BA

D

G 2= D (d) K-map for G3

Figure 3.41 K-map Simplification



The logic diagram for binary to gray code converter using logic

‡‡ 3.48

COMBINATIONAL LOGIC CIRCUIT

gates is shown in figure 3.42 Binary code D C B A

G0 G1 G2 G3

}

Gray code

Figure 3.42 Binary to Gray Code Converter

3.13.6 Gray Code to Binary Code Converter The truth table for Gray code to binary code converter is given in table 3.14 Table 3.14 Gray to binary Code Input Gray code

Output Binary code

G3

G2

G1

G0

D

C

B

A

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

1

1

0

0

1

0

0

0

1

0

0

0

1

1

0

1

1

0

0

1

0

0

0

1

1

1

0

1

0

1

0

1

0

1

0

1

1

0

0

1

0

0

0

1

1

1

1

1

0

0

1

0

0

0

1

1

0

1

1

0

0

1

1

1

1

1

1

0

1

0

1

1

1

0

1

0

1

1

1

0

1

0

1

1

0

0

1

0

1

1

1

1

0

1

1

0

0

1

1

1

1

0

1

0

0

0

1

1

1

1

‡‡ 3.49



The logical expression for A,B,C,D are obtained by k Map

simplification as shown in figure 3.43 (a),(b),(c),(d). G1G0 00 G3G2 0 00 0 1 4 01 11 0 12 10 1 8

01 11 1 1 03 0 5 17 1 13 0 15 9 0 1 11

G1G0 00 01 11 10 G3G2 0 0 1 13 12 00 0 4 1 5 07 06 01 1 11 0 12 013 1 15 1 14 9 10 1 8 1 0 11 0 10

10 12 06 1 14 0 10

(a) K-map for A

G3G2G1 G3G2G1 G3G2G1 G3G2G1

(b) K-map for B

A = G 3G 2G1G 0 + G 3G 2G1G 0 + G 3G 2G1G 0 + G 3G 2G1G 0 + G 3G 2G1G 0 + G 3G 2G1G 0 + G 3G 2G1G 0 + G 3G 2G1G 0 = G 3G 2 (G1G 0 + G1G 0 ) + G 3G 2 (G1G 0 + G1G 0 ) + G 3G 2 (G1G 0 + G1G 0 ) + G 3G 2 (G1G 0 + G1G 0 )

(

)

(

= G 3G 2 (G1 ⊕ G 0 ) + G 3G 2 G1 ⊕ G 0 + G 3G 2 (G1 ⊕ G 0 ) + G 3G 2 G1 ⊕ G 0

{

} {(

}

)

= (G1 ⊕ G 0 ) G 3G 2 + G 3G 2  + G1 ⊕ G 0 (G 3G 2 + G 3G 2 )

(

) (

)

)

= (G1 ⊕ G 0 ) G 3 ⊕ G 2 + G1 ⊕ G 0 (G 3 ⊕ G 2 )

A = (G1 ⊕ G 0 ) ⊕ (G 3 ⊕ G 2 )

B = G 3G 2G1 + G 3G 2G1 + G 3G 2G1 + G 3G 2G1 = G1 (G 3G 2 + G 3G 2 ) + G1 (G 3G 2 + G 3G 2 )

(

)

= G1 G 3 ⊕ G 2 + G1 (G 3 ⊕ G 2 )

B = G1 ⊕ (G 3 ⊕ G 2 )

G1G0 00 01 11 10 G3G2 0 2 3 1 0 0 0 00 0 4 6 7 5 1 1 1 1 01 15 14 13 12 0 0 0 11 0 9 8 11 10 10 1 1 1 1

G1G0 00 G3G2 00 0 G3G2 01 0 11 1 G3G2 10 1

C = G3G2 + G3G2 = G3 ⊕ G2 (c) K-map for C Figure 3.43 K-map Simplification

01 0 0 1 1

11 0 0 1 1

10 0 0 1 1

D = G3 (d) K-map for D

G3

‡‡ 3.50

COMBINATIONAL LOGIC CIRCUIT

Logic Diagram The logic diagram for gray to binary code converter using logic gates is shown in figure 3.44 Gray code G3 G2 G1 G0 A

B C D

}

Binary code

Figure 3.44 Gray code to Binary code converter

3.13.7 BCD to Gray Code Converter The Truth table for BCD to Gray code converter is shown in table 3.15. Table 3.15 BCD TO GRAY CODE OutputGray

Input BCD code

code

B3

B2

B1

B0

G3

G2

G1

G0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

1

0

0

0

1

1

0

0

1

1

0

0

1

0

0

1

0

0

0

1

1

0

0

1

0

1

0

1

1

1

0

1

1

0

0

1

0

1

0

1

1

1

0

1

0

0

1

0

0

0

1

1

0

0

1

0

0

1

1

1

0

1

The logical expression for G0, G1, G2, G3 are obtained from K-map simplification as shown in figure 3.45 (a),(b),(c),(d)

‡‡ 3.51

B1B0 00 01 11 0 3 1 1 0 00 0 4 0 1 5 07 01 11 X 12 X13 X 15 9 10 0 8 1 X 11

B1B0 10 B B 00 01 2 B1B0 3 2 1 0 0 1 00 0 6 1 BB 4 1 5 01 1 1 0 14 X 11 X 12 X 13 9 X 10 8 0 B2B1 10 0 G0= B1 B0+ B1B0 =B1 ⊕ B0 G=BB

B3B2

B1B0 00 0 00 0 4 01 1 11 X 12 8 10 1

01 0 1 1 5 X 13 9 1

11 0 3 1 7 15 X X 11

10 2 0 1 6 14 X X 10

10 2 1 0 6 X 14 X 10

B2B1

+ B2B1 =B2 ⊕ B1 (b) K-map for G1 1

(a) K-map for G0

B3B2

11 1 3 0 7 X 15 X 11

2

1

B1B0 00 01 11 0 3 1 0 0 00 0 4 0 5 07 01 0 15 13 X 11 X 12 X 9 8 1 X 11 10 1

B3B2 B2 B3

G2= B2+B3

10 2 0 06 14 X X 10

B3

G3= B3 (d) K-map for G3

(c) K-map for G2

Figure 3.45 K-map Simplification

The logic diagram for BCD to Gray code converter using logic gates is shown in figure 3.46. BCD Code B3 B2 B1 B0



G0

G1 G2 G3

}

Gray code

Figure 3.46 Logic Diagram for BCD to Gray code Converter

‡‡ 3.52

COMBINATIONAL LOGIC CIRCUIT

3.13.8 Gray to BCD Code Converter The truth table for Gray to BCD code is shown in table 3.16 Table 3.16 Gray to BCD code Gray code

BCD code

G3

G2

G1

G0

E

D

C

B

A

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

1

0

0

1

1

0

0

0

1

0

0

0

1

0

0

0

0

1

1

0

1

1

0

0

0

1

0

0

0

1

1

1

0

0

1

0

1

0

1

0

1

0

0

1

1

0

0

1

0

0

0

0

1

1

1

1

1

0

0

0

1

0

0

0

1

1

0

1

0

1

0

0

1

1

1

1

1

1

0

0

0

0

1

1

1

0

1

0

0

0

1

1

0

1

0

1

0

0

1

0

1

0

1

1

1

0

0

1

1

1

0

0

1

1

0

1

0

0

1

0

0

0

1

0

1

0

1



The logic expression for A,B,C,D,E are obtained from K-Map simplification as shown in figure 3.47 (a),(b),(c),(d),(e) G1G0 00 01 11 10 G3G2 0 1 1 03 12 00 0 1 4 0 5 17 06 01 11 0 12 113 0 15 1 14 10 1 8 0 9 1 11 0 10 (a) K-map for A

A = G 3G 2G1G 0 + G 3G 2G1G 0 + G 3G 2G1G 0 + G 3G 2G1G 0 + G 3G 2G1G 0 + G 3G 2G1G 0 + G 3G 2G1G 0 + G 3G 2G1G 0

= G 3G 2 (G1G 0 + G1G 0 ) + G 3G 2 (G1G 0 + G1G 0 ) + G 3G 2 (G1G 0 + G1G 0 ) + G 3G 2 (G1G 0 + G1G 0 )

(

)

(

= G 3G 2 (G1 ⊕ G 0 ) + G 3G 2 G1 ⊕ G 0 + G 3G 2 (G1 ⊕ G 0 ) + G 3G 2 G1 ⊕ G 0

(

)

= (G1 ⊕ G 0 ) (G 3G 2 + G 3G 2 )  +  G1 ⊕ G 0 (G 3G 2 + G 3G 2 )   

)

‡‡ 3.53

(

) (

)

A = (G1 ⊕ G 0 ) G 3 ⊕ G 2 + G1 ⊕ G 0 (G 3 ⊕ G 2 ) A = (G1 ⊕ G 0 ) ⊕ (G 3 ⊕ G 2 ) G1G0 00 01 11 GG 0 3 1 3 2 0 1 00 0 4 1 5 07 01 1 15 11 0 12 0 13 0 9 8 10 0 0 1 11 G3G2 G1

10 2 1 6 0 14 0 1 10

B =G2G1+G3G2G1 (b) K-map for B

G1G0 00 01 11 10 G3G2 0 0 1 03 02 00 0 0 4 0 5 07 06 01 11 1 12 113 0 15 0 14 10 0 8 0 9 0 11 0 10 D =G3G2G1 (d) K-map for D

G1G0 00 G3G2 0 00 0 4 1 G2G1 01 11 0 12 10 1 8

01 11 3 0 1 0 1 5 17 15 0 13 0 9 1 0 11

10 2 0 G3G2 16 14 0 GGG 0 10 3 2 1

C =G3G2+G3G2G1 (c) K-map for C

G1G0 00 01 11 G3G2 0 0 1 03 00 0 4 0 0 5 07 01 11 0 12 0 13 1 15 9 8 10 1 1 1 11 E =G3G2+G3G1 (e) K-Map for E

Figure 3.47 K-map Simplification

10 2 0 06 14 1 1 10

G3G1 G3G2

‡‡ 3.54

COMBINATIONAL LOGIC CIRCUIT

Logic Diagram The logic diagram for Gray to BCD code using logic gates is shown in figure 3.48 Input Gray code G3

G2

G1

G0

A

B

C

D

E

}

2 digit BCD code

Figure 3.48 Gray to 2 digit BCD code converter

3.14 BINARY COMPARATOR/MAGNITUDE COMPARATOR Binary comparator or digital comparators are combinational circuit that are used for testing whether the value represents by one binary word is greater than, less than or equal to the value of the another binary word. This circuit can be extended to any number of bits. Two types of comparators are used 1) Equality Comparator 2) Magnitude comparator Equality Comparator These type of comparator are used to check only for number to be equal. The 3 bit equality comparator circuit and logic diagram is given in

‡‡ 3.55

figure 3.49 x 0 = A0  B 0 x1 = A1  B1 x 2 = A2  B 2 A = B ⇒ x 0 x1x 2 Should be equal to 1 A0 B0 A1 B1 A2 B2

Figure 3.49 Equality Comparator Applications 1. It is used in address decoding circuitry in computers and microprocessor based device to select a specific input and output device for storage of data. 2. It is used to control applications in which the binary numbers representing physical variables such as temperature, position are compared with a reference value. Then the outputs from the comparator are used to drive the actuators so as to make the physical variables closed to the set value Magnitude comparator The circuit that compares relative magnitude of two binary numbers is called magnitude comparator. The block diagram of magnitude comparator is shown in figure 3.50 A

B

n-bit magnitude comparator

A>B

A=B

AB 0 0 1 0

Output Y YA=B 1 0 0 1

YAB, yA=B, yAB) A 0 1

B 0 0 1

Y(A=B) 1 0 0

A 0 1

B 0 1 0

AB

AB Y(A>B)=AB

Y(AB

B0 B1 00 01 11 A0 A 1 00 1 0 1 0 3 0 01 0 4 1 5 0 7 11 0 12 0 13 1 15 A1A0B1B0 10 0 8 0 9 0 11

10 02 06 0 14 1 10 A1A0B1B0

A1A0B1B0 A1A0B1B0

(b) K-map for yA=B

Y( A =B ) = A1 A0 B1 B 0 + A1A0 B1B 0 + A1A0 B1B 0 + A1 A0B1 B 0

(

)

(

= A1 B1 A0 B 0 + A0B 0 + A1B1 A0B 0 + A0 B 0 = A1B1 ( A0  B 0 ) + A1B1 ( A0  B 0 )

(

= ( A0  B 0 ) A1 B1 + A1B1

Y( A =B ) = ( A0  B 0 )( A1  B1 )

)

)

‡‡ 3.59

B0 B1 00 01 11 A0 A 1 00 0 1 1 1 3 0 01 0 4 0 5 1 7 11 012 0 13 0 15 10 0 8 0 9 1 11

10 12 16 014 010

A1A0B0 A1B1 A0B1B0

Y(A 1 The output should be either '1' or '0' and the equality of each pair of bits can be logically with an exclusion NOR function as

} } }

X 2 = A2  B 2 = A2 ⊕ B 2 = A2 B 2 + A2B 2 = 1

X1 = A1  B1 = A1 ⊕ B1 = A1 B1 + A1 B1

=1

X 0 = A0  B 0 = A0 ⊕ B 0 = A0 B 0 + A0 B 0 = 1 The logical expression for A = B is giiven below Y( A =B ) = X 2 .X1.X 0 Case 2: A>B For checking A>B, start from MSB, check the magnitude of pairs. If two digits of pair are equal, we compare the next lower significant pairing digit. The comparison continues until pair of unequal digits is reached (ie) Ai =1 and Bi =0. To Check 2nd position A2 > B 2 = A2B '2 1st position A1 > B1 = X 2 A1B '1 0th position A0 > B 0 = X1X 2 A0 B 0 ' If anyone is high then A > B Y A >B = A2B 2′ + X 2 A1B1′ + X 2 X1A0 B 0′ (

)

‡‡ 3.61

Case 3: A < B For checking AB, start from MSB check the magnitude of pairs. If two digit of Pair are equal, we compare the next lower significant pairing digits. The comparison continues until pair of unequal digit is reached Ai =1 and Bi =0. To check the 3rd position A3 > B 3 → A3B 3′

2nd position A 2 > B 2 → X 3 A2B 2′ 1st position, A1 > B1 → x 3 x 2 A1B1′ 0th position, A0 > B 0 → x 3 x 2 x1A0B 0′ If any one is high then A > B . Therefore OR operation is used The logical expression for A > B = A3B 3′ + X 3 A2B 2′ + X 3 X 2 A1B1′ + X 3 X 2 X1A0B 0′ Case 3: A