CMOS Past, Present and Future (Woodhead Publishing Series in Electronic and Optical Materials) 0081021399, 9780081021392

Table of contents :
Front Cover
CMOS Past, Present, and Future
Copyright
Contents
Contributors
Preface
Acknowledgments
Chapter 1: Basics of metal-oxide-semiconductor field-effect transistor (MOSFET)
1.1. Introduction
1.2. Basics of MOSFET's operation
1.2.1. Accumulation
1.2.2. Depletion
1.2.3. Inversion
1.2.4. Strong inversion
1.3. Figures of merit of MOSFETs
1.4. Evolution of the MOSFET structure
References
Chapter 2: Scaling and evolution of device architecture
2.1. Introduction
2.2. Dimension and architectural scaling
2.2.1. Scaling principles
2.2.2. Impact of the device architecture
2.2.3. Junctionless transistor
2.3. Lithography for downscaling
2.3.1. The resolution enhancement
2.3.1.1. Wavelength of light source reduce
2.3.1.2. Improvement of NA
2.3.2. Double patterning technology
2.3.3. Extreme ultraviolet lithography (EUVL) technology
2.3.4. Reticle enhancement techniques (RETs)
2.4. Electron-beam lithography (EBL)
2.5. Strain engineering
2.6. Impact of scaling
2.7. Beyond CMOS and beyond Si CMOS
2.7.1. Tunnel FETs
2.7.2. Spintronics
References
Chapter 3: Strain engineering
3.1. Introduction
3.2. Basic definitions of strain type and design
3.3. Strain design in MOSFETs
3.4. Methods to induce strain in the CMOS structure
3.4.1. Epitaxy of stressor materials
3.4.2. Stress memorization technique (SMT)
3.4.3. DSL
3.5. Embedded Si1-yCy(eSi1-yCy) for nMOS
3.5.1. Strain and critical thickness
3.5.2. Critical thickness of SiGe alloys on patterned substrates
3.5.3. Strain measurements
3.5.4. Raman spectroscopy for strain measurement
References
Further reading
Chapter 4: High-κ dielectric and metal gate
4.1. The scaling of MOSFET devices
4.2. SiO2 and poly-Si gate electrode
4.2.1. SiO2 gate dielectric
4.2.2. Poly-Si gate electrode
4.3. High-κ dielectric and metal gate
4.3.1. High-κ gate dielectric
4.3.2. Metal gate electrode
4.4. Hafnium-based high-κ dielectrics
4.4.1. Hafnium oxide
4.4.2. Hafnium aluminate
4.4.3. Hafnium lanthanate
4.5. Integration of HfO2 dielectric with compatible metal gate electrodes
4.6. High-κ dielectric and metal gate electrodes for FinFETs
4.7. Summary
References
Further Reading
Chapter 5: Channel materials
5.1. Introduction
5.2. High-mobility channels
5.3. SiGe channel
5.4. Ge channel
5.5. GeSn channel
5.6. III-V channel
5.7. Two-dimensional channel materials
5.7.1. Graphene channel
5.7.2. Graphene-like channel
References
Chapter 6: Challenges in ultra-shallow junction technology
6.1. Introduction
6.2. Basics of dopant activation and diffusion
6.2.1. Solubility and distribution coefficient
6.2.2. Dopant diffusion
6.2.3. Doping methods
6.3. Shallow boron junctions in silicon
6.3.1. Boron diffusion in silicon
6.3.2. Transient-enhanced diffusion of B in Si
6.3.3. Boron-interstitial clustering
6.4. N-type diffusion in germanium
6.4.1. Diffusion mechanism of n-type dopants in Ge
6.4.2. N-type dopant control in Ge by co-implantation
6.4.3. Point defect engineering
6.5. Summary and outlook
References
Further reading
Chapter 7: Advanced contact technology
7.1. Introduction
7.2. Characterizations of extremely low ρc
7.2.1. MR-CTLM structure
7.2.2. RTLM structure
7.3. Ohmic contacts on Si/SiGe substrate
7.3.1. Modulation of SBHs on Si/SiGe substrate
7.3.1.1. MIS method
7.3.1.2. Interface passivation
7.3.1.3. Dopant segregation
7.3.1.4. Alloying
7.3.2. Ohmic contacts
7.3.2.1. MIS Ohmic contact
7.3.2.2. Ohmic contacts with interface passivation
7.3.2.3. Ohmic contacts with dopant segregation
7.3.2.4. Ohmic contact with higher dopant concentration
7.4. Ohmic contacts on Ge/III-V
7.4.1. Modulation of SBH on Ge/III-V semiconductors
7.4.1.1. MIS method
7.4.1.2. Interface passivation
7.4.1.3. Dipole and dopant segregation
7.4.1.4. SBH modulation on III-V materials
7.4.2. Ohmic contacts on Ge/III-V semiconductors
7.4.2.1. MIS Ohmic contacts
7.4.2.2. Ohmic contacts with interface passivation and dopant segregation
7.4.2.3. Ohmic contacts with higher doping concentration
7.4.2.4. Ohmic contacts on III-V semiconductors
7.5. Ohmic contacts on potential CMOS channel materials
7.6. Summary
References
Chapter 8: Advanced interconnect technology and reliability
8.1. Introduction
8.2. Copper interconnect integration
8.2.1. Damascene integration
8.2.1.1. Single damascene integration
8.2.1.2. Dual damascene integration
8.2.2. Copper resistance with interconnect scaling
8.2.3. New copper integration scheme
8.3. Low-k dielectric characteristics and classification
8.3.1. Low-k characteristics
8.3.1.1. Material composition
8.3.1.2. Porosity
8.3.2. Low-k classification and characterization
8.3.3. Low-k dielectrics integration challenges
8.3.4. Air gap implementation in interconnect
8.4. Copper interaction with silicon and dielectrics
8.4.1. Copper interaction with silicon
8.4.2. Copper interaction with dielectrics
8.5. Metal diffusion barriers
8.5.1. Intermetal barrier material selection
8.5.2. Metal diffusion barrier deposition
8.5.2.1. PVD barrier deposition
8.5.2.2. ALD barrier deposition
8.6. Reliability of copper metallization
8.6.1. Electromigration basics
8.6.1.1. Copper electromigration
8.6.2. Stress-induced voiding
8.7. Reliability of advanced intermetal dielectrics
8.7.1. Leakage mechanism of intermetal dielectrics
8.7.1.1. Electronic transport in silicon thermal oxide
8.7.1.2. Electronic transport in intermetal dielectrics
8.7.2. Breakdown characteristics of intermetal dielectrics
8.7.2.1. Copper diffusion
8.7.2.2. Moisture absorption
8.7.2.3. Porosity influence
8.8. Reliability statistics and failure models
8.8.1. Probability distribution functions
8.8.1.1. Weibull distribution
8.8.1.2. Log-Normal distribution
8.8.2. Breakdown acceleration models
8.8.2.1. Gate oxide models
8.8.2.2. Models for intermetal dielectrics
8.9. The future of interconnect: beyond Cu and low-k
8.10. Summary
References
Final words
Acronyms
Index
Back Cover

Citation preview

CMOS Past, Present, and Future

Related titles Germanium-Based Technologies: From Materials & Devices (ISBN 978-0-08-044953-1) Sputtering Materials for VLSI and Thin Film Devices (ISBN 978-0-8155-1593-7) High Performance Silicon Imaging: Fundamentals and Applications of CMOS and CCD sensors (ISBN 978-0-85709-598-5) Millimeter-Wave Digitally Intensive Frequency Generation in CMOS (ISBN 978-0-12-802207-8)

Woodhead Publishing Series in Electronic and Optical Materials

CMOS Past, Present, and Future Henry H. Radamson Jun Luo Eddy Simoen Chao Zhao

An imprint of Elsevier

Woodhead Publishing is an imprint of Elsevier The Officers’ Mess Business Centre, Royston Road, Duxford, CB22 4QH, United Kingdom 50 Hampshire Street, 5th Floor, Cambridge, MA 02139, United States The Boulevard, Langford Lane, Kidlington, OX5 1GB, United Kingdom Copyright © 2018 Elsevier Ltd. All rights reserved. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying, recording, or any information storage and retrieval system, without permission in writing from the publisher. Details on how to seek permission, further information about the Publisher’s permissions policies and our arrangements with organizations such as the Copyright Clearance Center and the Copyright Licensing Agency, can be found at our website: www.elsevier.com/ permissions. This book and the individual contributions contained in it are protected under copyright by the Publisher (other than as may be noted herein).

Notices Knowledge and best practice in this field are constantly changing. As new research and experience broaden our understanding, changes in research methods, professional practices, or medical treatment may become necessary. Practitioners and researchers must always rely on their own experience and knowledge in evaluating and using any information, methods, compounds, or experiments described herein. In using such information or methods they should be mindful of their own safety and the safety of others, including parties for whom they have a professional responsibility. To the fullest extent of the law, neither the Publisher nor the authors, contributors, or editors, assume any liability for any injury and/or damage to persons or property as a matter of products liability, negligence or otherwise, or from any use or operation of any methods, products, instructions, or ideas contained in the material herein. Library of Congress Cataloging-in-Publication Data A catalog record for this book is available from the Library of Congress British Library Cataloguing-in-Publication Data A catalogue record for this book is available from the British Library ISBN: 978-0-08-102139-2 (print) ISBN: 978-0-08-102140-8 (online)

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Contents

Contributors Preface Acknowledgments

ix xi xiii

1

Basics of metal–oxide–semiconductor field-effect transistor (MOSFET) 1 H.H. Radamson 1.1 Introduction 1 1.2 Basics of MOSFET’s operation 4 1.3 Figures of merit of MOSFETs 9 1.4 Evolution of the MOSFET structure 12 References 16

2

Scaling and evolution of device architecture H.H. Radamson, E. Simeon, J. Luo, G. Wang 2.1 Introduction 2.2 Dimension and architectural scaling 2.3 Lithography for downscaling 2.4 Electron-beam lithography (EBL) 2.5 Strain engineering 2.6 Impact of scaling 2.7 Beyond CMOS and beyond Si CMOS References

19

Strain engineering H.H. Radamson 3.1 Introduction 3.2 Basic definitions of strain type and design 3.3 Strain design in MOSFETs 3.4 Methods to induce strain in the CMOS structure 3.5 Embedded Si1 yCy(eSi1 yCy) for nMOS References Further reading

41

High-κ dielectric and metal gate C. Zhao, X. Wang, W. Wang 4.1 The scaling of MOSFET devices 4.2 SiO2 and poly-Si gate electrode

69

3

4

19 20 26 30 31 31 33 36

41 41 44 47 54 64 67

69 70

vi

Contents

4.3 4.4 4.5 4.6 4.7

5

6

7

8

High-κ dielectric and metal gate 74 Hafnium-based high-κ dielectrics 81 Integration of HfO2 dielectric with compatible metal gate electrodes 90 High-κ dielectric and metal gate electrodes for FinFETs 93 Summary 97 References 97 Further reading 103

Channel materials H.H. Radamson, E. Simeon 5.1 Introduction 5.2 High-mobility channels 5.3 SiGe channel 5.4 Ge channel 5.5 GeSn channel 5.6 III-V channel 5.7 Two-dimensional channel materials References

105

Challenges in ultra-shallow junction technology E. Simoen, H.H. Radamson 6.1 Introduction 6.2 Basics of dopant activation and diffusion 6.3 Shallow boron junctions in silicon 6.4 N-type diffusion in germanium 6.5 Summary and outlook References Further reading

125

Advanced contact technology J. Luo, K.P. Jia 7.1 Introduction 7.2 Characterizations of extremely low ρc 7.3 Ohmic contacts on Si/SiGe substrate 7.4 Ohmic contacts on Ge/III-V 7.5 Ohmic contacts on potential CMOS channel materials 7.6 Summary References

157

Advanced interconnect technology and reliability Y. Li, C. Zhao 8.1 Introduction 8.2 Copper interconnect integration 8.3 Low-k dielectric characteristics and classification 8.4 Copper interaction with silicon and dielectrics 8.5 Metal diffusion barriers

215

105 105 107 108 110 111 114 118

125 127 132 139 146 147 155

157 160 164 180 197 201 201

215 216 221 227 228

Contents

8.6 8.7 8.8 8.9 8.10

vii

Reliability of copper metallization Reliability of advanced intermetal dielectrics Reliability statistics and failure models The future of interconnect: beyond Cu and low-k Summary References

Final words Acronyms Index

231 233 239 242 243 243 249 251 255

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Contributors

H.H. Radamson Institute of Microelectronics of Chinese Academy of Sciences (IMECAS); University of Chinese Academy of Sciences (UCAS), Beijing, PR China K.P. Jia Institute of Microelectronics of Chinese Academy of Sciences (IMECAS); University of Chinese Academy of Sciences (UCAS), Beijing, PR China Y. Li Imec, Leuven, Belgium J. Luo Institute of Microelectronics of Chinese Academy of Sciences (IMECAS); University of Chinese Academy of Sciences (UCAS), Beijing, PR China E. Simeon Imec, Leuven, Belgium G. Wang Institute of Microelectronics of Chinese Academy of Sciences (IMECAS); University of Chinese Academy of Sciences (UCAS), Beijing, PR China X. Wang Institute of Microelectronics of Chinese Academy of Sciences (IMECAS); University of Chinese Academy of Sciences (UCAS), Beijing, PR China W. Wang Institute of Microelectronics of Chinese Academy of Sciences (IMECAS); University of Chinese Academy of Sciences (UCAS), Beijing, PR China C. Zhao Institute of Microelectronics of Chinese Academy of Sciences (IMECAS); University of Chinese Academy of Sciences (UCAS), Beijing, PR China

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Preface

We are in some way or other affected by the enormous impact of integrated electronics and integrated circuits (ICs). They have changed virtually all aspects of our social and professional lives. CMOS is the main unit in ICs and its design and structure have undergone an evolution for many decades to follow the historical Moore’s Law. This book is written in a notably understandable language for readers and provides a good insight from the basics of CMOS to its development toward the advanced transistor structures. The book is dedicated to the students and researchers in the field of electrical engineering, who desire to learn more about the CMOS technology.

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Acknowledgments

Professor Anders Hallen from KTH is acknowledged for his scientific discussions. Many contributors from the Chinese Academy of Sciences have been involved with this book. Our special gratitude to Dr. Huilong Zhu, Dr. Huaxiang Yin, and Dr. Jiang Yan for their remarkable contributions and discussions to the all-last high-k/metal gate integration part. We express our appreciation to Miss Dan Zhang, Mr. Ningyuan Duan, Miss Shujuan Mao, Mr. Jinbiao Liu, and Miss Xuewei Zhao for their valuable help.

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Basics of metal–oxide– semiconductor field-effect transistor (MOSFET)

1

H.H. Radamson Institute of Microelectronics of Chinese Academy of Sciences (IMECAS), Beijing, PR China; University of Chinese Academy of Sciences (UCAS), Beijing, PR China

1.1

Introduction

MOSFETs are the brick units of integrated circuits (ICs) which are used in many devices in our daily life. They are being used for analog and digital applications. The latter application is for a logic device where the transistor acts as a switch and the performance is qualified with switching speed and switching energy. Since the MOSFET structure has been downscaled in size according to Moore’s law, the density and switching speed of transistors have enhanced exponentially where the switching energy has reduced in a similar manner. This evolution of MOSFET structures finally resulted that the planar design was abandoned to three-dimensional (3D) one providing a remarkably better control on the parasitic resistances and capacitances. The idea of operational field effect transistors (FETs) extends to a US patent submitted by Julius Edgar in 1925; meanwhile, the discovery of MOSFETs by Dawon Kahng and Martin Atalla at Bell labs emerged late in the 1950s. In the beginning, the gate material in the transistors was usually metals, for example, Al, which led to a “Metal Oxide Semiconductor” abbreviation for such devices. However, later, heavily doped poly-Si was used as the standard gate material due to its high thermal stability without reacting with gate oxide. Nowadays, the new research introduces the metal gate material to be reused when SiO2 gate oxide was substituted with more advanced high-k dielectrics. The first ICs based on MOS were commercially announced by General Microelectronics in 1964. Although this step was a large technological development, it took almost a decade to solve the fundamental yield and reliability issues allowing MOS as the main component in IC technology. The main benefit of MOSFET in IC production has been that the transistor needs practically no input current to manipulate the carrier current compared to the bipolar transistor. The channel conductance can be controlled by an applied voltage to the gate terminal in different operation modes. MOSFETs operate through four-terminal contacts: gate (G), source (S), drain (D), and substrate body (B) as shown in Fig. 1.1. The body terminal could be connected to the source, resulting in a three-terminal device. CMOS Past, Present and Future. https://doi.org/10.1016/B978-0-08-102139-2.00001-X Copyright © 2018 Elsevier Ltd. All rights reserved.

2

CMOS Past, Present and Future

Metal contact

Gate oxide Spacer

Extended implantation

Gate

SiGe S/D GOX

Gate

Silicide

Source

Drain

Si-fin

Si substrate

Gate oxide

Shallow trench isolation Transistor’s body

Halo implantation Circuit symbols N-channel P-channel MOSFET MOSFET G G S

D

S

D

Fig. 1.1 Figure illustrates a cross section of 2D planar MOSFET (left) and 3D FinFET (right). The circuit symbols have also been shown for nMOSFETs and pMOSFETs.

A complementary field effect transistor (CMOS) may contain an MOS transistor (n-channel) where the drive carriers are electrons; meanwhile, the body is p-type doped and a pMOS transistor (p-channel) where carriers are holes with an n-type doped body. The first microprocessors in the 1970s were all fabricated either from pMOS logic or nMOS logic separately. The coupling of these p- and nMOSFETS in CMOS configuration allows one high/ low switch which could be volume effectively packed in small chips with low-power dissipation and heat generation. In CMOS, if both gates and both drains are connected, then by applying an appropriate high-gate voltage the nMOSFET is active but the pMOSFET does not conduct, and when a low-gate voltage is used the situation is reverse. During the switching time when the voltage changes, the status is that both MOSFETs conduct temporarily. In principle, MOSFETs operate on the modulation of charge concentration through an MOS capacitance formed between the gate and body electrodes when a dielectric layer separates them. The carriers in the conducting channel may be inverted to electrons for transistors with a p-type doped body (n-channel) or holes for n-type doped ones (p-channel). The desired characteristics for a MOSFET are high Ion and low Ioff. In traditional transistor processing, the S/D regions are formed by dopant implantation or epitaxy growth, whereas the gate formation is started by deposition of gate oxide and metal (or polycrystalline material) with nitride/oxide spacers. Further adjustment of dopant profile below the gate region can be performed by a tilted angle implantation (so-called Halo implantation). Such implanted pockets are necessary to have better control over the carrier transport in the channel region. The typical MOSFET’s S/D formation was modified by introducing etch to create recess and later filling it with SiGe material to perform strain engineering. The reason for this

Basics of metal–oxide–semiconductor field-effect transistor (MOSFET)

3

modification was to improve the carrier transport in the channel region. Chapter 3 covers in detail the most important techniques to induce strain in the MOSFET structure. In transistors, the quality of gate oxide determines the leakage current. There is a need to decrease the resistance in MOSFETs’ contacts and silicide layer is applied prior to the metal contact for this purpose. Both the gate oxide and silicide layers were modified in 90-nm technology node and beyond. For example, the gate oxide was silicon oxide for many decades until, in the 45-nm technology node, it was replaced by high-k material. In order to avoid any damage on high-k oxide due to hightemperature annealing steps, the process flow of the transistor was modified to the high-k-last process where these materials are deposited after thermal treatments. In such cases, a dummy gate of silicon oxide is initially formed and the transistor is processed. Afterward, the dummy gate is removed and the real gate containing high-k materials is formed. During the past 40 years, the MOSFET’s size has been shrunk to follow an international technological road map semiconductor (ITRS) to increase the density of transistors and to decrease the power consumption. In this evolution of MOSFET in 2003 in the 22-nm technology node, the conventional 2D transistor architecture was replaced by 3D structure, the so-called trigate design [1]. Trigate transistors were later renamed FinFETs, which were already defined by other research groups a few years before [2]. The main structures of a (two-dimensional) 2D and (three-dimensional) 3D MOSFET are defined in Fig. 1.1 as follows: In order to study the performance of a transistor, different notations have to be defined. The source, drain, and gate for transistors in Fig. 1.1 are written shortly as S, D, and G, whereas other important notations are as follows: VTH: Threshold voltage VDS: Voltage between D and S terminals Vov: Vov ¼ VGS  VTH Cox: Oxide capacitance μe or μh: Channel mobility kn: Coefficient of conductance CGS, CGD: Capacitances between S, D, and G rDS: Resistance between D/S (rDS ¼ 1/gDS) VDD: Supply voltage VGS: Voltage between G and S terminals Vox: Voltage over oxide VG: Gate voltage gDS: Conductance between D/S gm: Transconductance Gint: Intrinsic gain (Gint ¼ gm/gDS) RS, RD, and RG: Resistances of S, D, and G

In order to provide a better understanding of 2D-to-3D transition, the process flow of these transistors is shown in Fig. 1.2. The major differences between 2D and 3D processing are the formation of Si fin in FinFETs, S/D formation, and the planarization step [3].

4

CMOS Past, Present and Future

- Fin patterning vs planar active region patterning - Oxide filling, planarization, and recessing S/D regions - Doping to form well isolation - Gate oxide growth, and dummy gate deposition, planarization and patterning - Doping to form S/D extensions - Spacer deposition and patterning - Epitaxy forming S/D regions (embedded SiGe and raised Si) - Inter level dielectric (ILD) and chemical mechanical polish (CMP) - Dummy gate removal - Replacement of high-k and metal gate stack - Self-aligned contact formation - Back end of line

Fig. 1.2 Process flow for the bulk FinFETs and planar MOSFETs where additional processes for FinFETs are highlighted.

1.2

Basics of MOSFET’s operation

Fig. 1.3A illustrates the band diagram of a typical planar MOSFET. In this figure, a bending of energy bands (qφs) occurs at the Si side because of the work function difference between the gate material (metal or polycrystalline Si) (qψ g) and Si (qψ s), as well as existence of any charges in the gate oxide and interfacial states. By applying a gate voltage, the energy band at the SiO2/Si becomes flat where VG ¼ Vfb ¼ ψ g  ψ s. For a transistor, this is a flat band condition as shown in Fig. 1.3B. In the flat-band condition, the surface electric field in the Si substrate is zero and this makes the electric field in the oxide is also zero. The bandgap of SiO2 is 9 eV. The vacuum level (E0) is defined as the energy required for electrons to be taken outside the material. The difference between E0 and Ec is called electron affinity. This parameter is 4.05 eV for Si, whereas for SiO2 is 0.95 eV. In a MOSFET, the energy difference between Ec of Si and SiO2 is 3.1 eV and this creates a barrier so-called Si–SiO2

Ec Ef Ev

Ec Ef Ev N+ poly gate

(A)

cSi =4.0 eV

qyg

3.1 eV

Ec Ef Ev

Gate oxide

Ec Ef Ev

Vfb

N+ poly gate

Transistor’s body

(B)

qySi = cSi + (Ec - Ef)

Transistor’s body

Gate oxide

Fig. 1.3 (A) The energy band diagram of a p-type silicon substrate with a formed gate when no applied gate voltage is applied and (B) with a gate voltage equal to Vfb.

Basics of metal–oxide–semiconductor field-effect transistor (MOSFET)

5

electron energy barrier. In a similar way, the energy barrier for holes is defined and is estimated to be 4.8 eV. Owing to these energy barriers, Holes and electrons are not able to move through the SiO2 gate dielectric. It is also expected an energy barrier of 3.1 eV at the interface between the polysilicon gate and SiO2. In general, a relationship for the applied voltages in a MOSFET can be written as: VG ¼ Vfb  ϕs  Vox

(1.1)

where for a flat-band situation VG ¼ Vfb and ϕs ¼ Vox ¼ 0; therefore, a simple form of Eq. (1.1) is written as: Vox ¼ VG  Vfb. To study the performance of a MOSFET, a special type of electrical measurement can be performed when a MOS capacitance configuration is established. There are three biasing modes when the gate voltages vary over a range of measurement: accumulation, depletion, and inversion as shown in Fig. 1.4A–C. VG < Vfb

Vfb< VG < VTH

Gate

Gate +++++++ Gate oxide

--------

Gate oxide +

+

+

VTH < VG

+

+ + + + Gate +++++++ Gate oxide -

---------------

-

-

-

---------------

Accumulation charge, Qacc

Depletion

Inversion

qVox

3.1 eV qVox

qfB

Ec, Ef Ev

E0 qVG qfs

qVG

qVG = qVT

Ec, Ef

Gate oxide

(B)

Ei Ef Ev

Depletion region

Ev

Gate oxide

(A)

Ec

fs = 2fB

Gate oxide

(C)

Fig. 1.4 (A) Accumulation, (B) depletion, and (C) inversion operation modes for a MOSFET.

6

CMOS Past, Present and Future

1.2.1 Accumulation This occurs when the gate voltage is more negative than the thermal potential for the p-doped Si substrate. The charge density in the channel region is dependent on the applied gate voltage. An electric field is constituted inside the oxide region where the direction of the field is dependent on the amount of applied gate voltage. Vox ¼ 

Qacc Cox

(1.2)

1.2.2 Depletion When the gate voltage is increased (VG is more positive for p-type and more negative for n-type doped Si), the charge distribution changes and the energy bands bend downward. As a result, a depletion region with a depth of Wdep is formed. At the surface, the electron density (or hole density for n-type doped Si) is stills light. The voltage over the gate oxide can be written as pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qNa2εs ϕs Qacc qN a Wdep ¼ Vox ¼  ¼ Cox Cox Cox

(1.3)

Therefore, φs can be written as ϕs ¼

2 qN a Wdep 2εs

(1.4)

By inserting the Vox and ϕs expression in the original equation for gate voltage: VG ¼ Vfb + ϕs + Vox ¼ Vfb +

2 qN a Wdep qN Wdep + a Cox 2εs

(1.5)

This a quadratic equation and Wdep can be solved as a function of VG(Wdep).

1.2.3 Inversion By further increase of VG, the energy band bends more and EF could be located in the vicinity of Ec. This situation leads to a threshold where the p-type doped semiconductor is inverted to N-type (or vice versa for n-type doped Si) at the interface of the semiconductor and gate oxide. The threshold voltage is usually reached when the surface electron (or hole) concentration (ns) approaches the same doping level as in the bulk (Na). A simple rule can be applied to obtain threshold voltage and that is when the surface potential satisfies the condition: ϕs(TH) ¼ 2ϕB (N-type body : ϕs(TH) ¼  2ϕB).

Basics of metal–oxide–semiconductor field-effect transistor (MOSFET)

7

Therefore, the main equation of gate voltage for threshold voltage (VG ¼ VT) is as follows: pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qNa2εs 2ϕB VTH ¼ Vfb + 2ϕB + Cox

(1.6)

The gate voltage in the vicinity of threshold voltage is also known as the weak inversion region.

1.2.4 Strong inversion Strong inversion in MOS capacitance occurs when VG exceeds beyond VTH. In this situation, both φs and Wdep do not change considerably from the depletion mode since any small variation results in a large electron (or hole) density. This means that the equation of VG is modified as follows: VG ¼ Vfb + 2ϕB 

Qdep Qinv  ¼ Vfb + 2ϕB + Cox Cox

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qNa2εs 2ϕB Qinv  Cox Cox

(1.7)

A summery of all operation modes (as described in Fig. 1.4) including strong inversion is illustrated in Fig. 1.5. In a transistor, no carrier transport occurs between the source and drain terminals (ID ¼ 0) when no gate voltage is applied. As an example, in a MOS transistor, if the gate terminal is set to a positive voltage and VGS > VTH, then a graded voltage is formed across the channel region, leading to channel conductance, which becomes Fig. 1.5 Figure shows an overview of different MOS operation modes.

1000 Accumulation 100

Inversion

Qs/QTH

Flatband 10

Depletion

1

0.1 −20

−10

0

10 fs/VTH

20

30

40

8

CMOS Past, Present and Future

large enough to allow electron transport in the channel. It is important to mention here that the condition VDS < VGS  VTH has to be satisfied in order to avoid a pinch through a situation in the transistor. In the situation where VGS controls the conductance of the channel and the channel operates as a variable resistor, conductance between the source and drain (gDS) is written as gDS ¼

  1 ¼ kn VGS  VTH  VDS rDS 2 1

(1.8)

where rDS is the resistance between drain and source. As a result, the induced charge (Q) in the channel region can be expressed as Q ¼ Cox ðVGS  VTH  ϕs Þ

(1.9)

The channel current can also be obtained by carrier mobility (μe), the formed electric field (εy) along the channel direction (y), channel length (W), and charge (Q) in the channel, according to ID ¼ Wμe Qεy where εy ¼ dψ=dy

(1.10)

Therefore, ID can be rewritten as follows: ID dy ¼ Wμn Cox ðVGS  VTH  ψ Þdψ ) ID W 1 2 Þ ¼ μn Cox ðVGS  VTH ÞVDS  VDS L 2

(1.11)

or ID ¼ μn ε0 εox

  W 1 2 ðVGS  VTH ÞVDS  VDS toc L 2

(1.12)

and the ID in saturation mode is obtained IDðsatÞ ¼

μn Cox W ðVGS  VTH Þ2 2L

(1.13)

Eq. (1.12) shows that ID is a quadratic function of VDS with a maximum point at VTH. This equation is used for transistor characterization where the channel mobility can be obtained from the electrical measurements. An nMOS transistor has three operating modes with the following conditions as illustrated in Fig. 1.6: 1. Cutoff: It occurs when VGS < VTH and the channel current ID ¼ 0 A

This is the state when the transistor is in the turnoff mode. A more detailed study using the Fermi-Dirac distribution shows that some electrons with thermal energy at the source can move inside the channel region and flow to the drain. This causes a

Basics of metal–oxide–semiconductor field-effect transistor (MOSFET)

9

VDS =VGS – VTH

ID Linear (triode)

Saturation VGS VGS VTH and VDS  VGS  VTH. This is also a voltage controlled current source and ID can be rewritten as ID ¼ (1/2) kn (VGS  VTH)2.

It is worth mentioning here that all the above equations for currents and voltages for an nMOS transistor can be written with a reversed sign for pMOS. This means that VTH, VSG, VDS, and VOV become negative and, for example, conditions for saturation mode become: VGS < VTH and VDS < VGS  VTH.

1.3

Figures of merit of MOSFETs

As we mentioned earlier, MOSFETs may be used as a switch or amplifier. N-channel transistors turn on when VGS > VTH; meanwhile, p-FETs are on if VGS < VTH. The transistors in the logic ICs are contacted in a cascaded structure where the output signal of

10

CMOS Past, Present and Future

one gate works as the input for the next gate. The cascaded transistors need a restoration of the signals to guarantee that a logic gate can reliably distinguish whether an input signal is on logic state 1/0. As an example, a NAND component consists of CMOS logic gates where an n-FET is connected to the ground and a p-FET is connected to the positive supply voltage VDD. Such an Si CMOS circuit has excellent performance of signal restoration offering low static power dissipation. This point is crucial for complex logic ICs since power dissipation and the generated self-heating are main problems. Thus, an FET-based successor for Si CMOS logic needs transistors which are able to switch off fast. One of the figures of merit (FOM) of a transistor is how the switching occurs, thus Ion/Ioff ratio has to be high. MOSFETs have to show an Ion/Ioff ratio within 104–107 for logic application. Another FOM for MOSFETs is the subthreshold swing (S) during switching. This FOM is measured in the mV/decade and expresses how the VGS has to be changed to make a change in ID by a factor of 10 as shown in Fig. 1.7. The subthreshold voltage is defined as   dVG kB T εSi tox S¼ 1+  d log 10 ID q log 10 e εox wd

(1.16)

In Eq. (1.16), εSi is the dielectric constant of silicon (11.9) and wd is the drain depletion layer width. T is the absolute temperature, kB is Boltzmann’s constant, q is the electron charge in absolute value, and e is the exponential number. It is clear from Eq. (1.16) that S has a lower limit value of about 0.06 V/decade at room temperature. It therefore constitutes a lower limit for the threshold voltage of scaled logic transistors, as a gate voltage swing of a few kBT/q is required to switch the device from off to on. If a dc VGS is applied to the transistor on an on-state operating mode, then a small RF signal will have to be amplified. This is the situation when a small variation of VG occurs; the number of carriers in the channel as well as the drain current is changed. The amplification behavior of MOSFET is characterized in terms of the unilateral power gain (U), the intrinsic gain (Gint), and the current gain (h21). In general, all these parameters are dependent on frequency as shown in Fig. 1.8.

Iog ID ION

Subthreshold swing, S [mV/dec ] IOff VTH

VDD

VG

Fig. 1.7 Figure illustrates the ID(VG) curve to estimate the subthreshold voltage.

Basics of metal–oxide–semiconductor field-effect transistor (MOSFET)

50 Measured h21 Measured U

U (−20 dB/dec) Gain h21 and U (dB)

40

fmax = 140 GHz

30

20

h21(−20 dB/dec)

11

Fig. 1.8 The frequency dependency of small-signal current gain (h21) and unilateral power gain U in an RF MOSFET [7].

fT = 110 GHz

10

0

1

100

10 Frequency (GHz)

Fig. 1.9 Figure illustrates a small signal equivalent circuit for an FET.

Intrinsic part

RG

RD

Cgd

G

D gmvGS Cgs

rds

Ri Rs

S

The most important FOM of RF transistors are the cutoff frequency (fT) and the maximum frequency of oscillation (fmax).fT is defined as the frequency when the magnitude of h21 has dropped to unity (0 dB) and at fmax when the unilateral power gain is unity. Both fT and fmax determine the frequency limits where the transistor’s amplifying performance is degraded. The frequency characteristics of MOSFETs are described by the small signal equivalent circuit as shown in Fig. 1.9. There are both intrinsic and extrinsic parts for a transistor. The intrinsic part covers the gate and the channel region and it contains CGS, CGD, gm, rDS (see the notations in Fig. 1.1) together with an intrinsic resistance Ri as shown in the figure. The extrinsic elements are RG, RS, and RD. The fT and fmaxfor the intrinsic part are obtained from the following expressions [8]: fT ð intÞ ¼

gm 2π ðCGS + CGD Þ

(1.17)

12

CMOS Past, Present and Future

fmax ð intÞ ¼

gm pffiffiffiffiffiffiffiffiffiffiffiffi 4π CGS gDS Ri

(1.18)

For RF transistors, high fT and fmax are mainly desired and the transistor can be designed for this purpose.

1.4

Evolution of the MOSFET structure

MOSFETs have continuously downscaled to follow an ITRS. Scaling and evolution of device architecture are discussed in detail in Chapter 2, but in this chapter the focus will be on the carrier transport in the channel and short channel effect. The size shrinking of the transistors resulted that the carrier transport in nanoscale transistors becomes more different compared to the classical ones. The classical MOSFET equations are modified for ballistic carrier transport which is explained by carrier injection at the source [9]. The drain current in the saturation mode is given by IDðSatÞ ¼ W hvð0ÞiCox ðVG  VTH Þ

(1.19)

where hv(0)i is the average velocity of carriers at the source side and Cox(VG  VT) is the charge density. When the channel length becomes smaller, hv(0)i can be set to thermal velocity (vT) since the carriers are thermally injected from source [10]. vT is given by sffiffiffiffiffiffiffiffiffiffiffiffi 2kB TL vT ¼ πm∗t

(1.20)

where TL denotes the lattice temperature. The drain current in nanotransistors can be rewritten as sffiffiffiffiffiffiffiffiffiffiffiffi 2kB TL Id ¼ WCox ðvG  vTH Þ πm∗t

(1.21)

This indicates that the drive current is increased by reducing the effective mass of the carrier (or inducing strain) [11]. In order to develop the discussion to a more detailed level, more knowledge about how MOSFETs function has to be provided. Fig. 1.10A and B illustrates how during the evolution of the MOSFET structure the parasitic capacitance and resistances are changed. In general, in an optimized MOSFET, all the undesired resistances and capacitances have to be minimized [5]. The downscaling of transistors leads to an increase in leakage current as a result of the smaller gate length. For industrial applications, CMOS technology has to ensure a negligible dissipated power in the standby state. Therefore, the leakage power of

Basics of metal–oxide–semiconductor field-effect transistor (MOSFET)

13

6 5 4

Total parasitic capacitance

3 2

Channel resistance

Capacitance (F/mm)

7

1200 1000 800

Parasitics dominate!

600

Parasitic resistance

400 200 0

1 120

100

80

60

40

20

0

120

Technology node (nm)

(A)

Resistance (Ohm-mm)

1400

8

Intrinsic channel capacitance

100

80

60

40

20

0

Technology node (nm)

(B)

Fig. 1.10 (A and B) The evolution of the parasitic components over different technology nodes.

transistors has to be controlled for logic application. In principle, there are no limitations for reducing the size of transistors but practically the leakage current rises for planar transistors with a gate length of 20 nm [6]. In nanotransistors, the body of transistor is very thin causing the external resistance becomes comparable in magnitude to the channel resistance. The rapid increase in parasitics in nanotransistors is due to the small space between neighboring devices (a few tens of nanometers) to increase the density. In the chip, the S/D and contact size are also scaled down to be compatible with the transistor size. The S/D contacts and the gate are a few nanometers apart; also, the contact size will lead to magnification of the parasitic problems. The problem with parasitic resistances is a fundamental issue for integration of nanotransistors in logic circuits. This occurs due to the small S/D volume compared to the transistor body which is 5–10 nm thick [12,13]. This problem is even more severe in integration of carbon nanotubes or graphene ribbons as channel material where the transistor body is only one atomic layer [14]. Another issue with downscaling of MOSFETs is the control of the carrier transport through the channel. This problem occurs when the drain voltage decreases source-tochannel barrier height and allows an off-state leakage. This phenomenon is known as drain-induced barrier lowering (DIBL) or short channel effect (SCE). Although control of SCE is a large problem for 2D transistors, this issue had no impact on 3D transistors. For almost 40 years, MOSFETs were manufactured in planar form until 2003 when Intel introduced 3D design, the so-called multigate field effect transistor (MuGFET). MuGFETs are fully depleted transistors and they are categorized to include double gate, Trigate, FinFETs, π-gate, Ω-gate, and the gate-all-around (GAA) transistors. Gate control was continually improved in the MuGFET group starting with double gate to the GAA transistors as shown in Fig. 1.11. The benefits of MUGFETs compared to the 2D MOSFETs are as follows: 1. The problem with doping of the body compared to MOSFETs is solved 2. MuGFETs have a remarkably higher drive current 3. The problem of the random dopant fluctuation is reduced

14

CMOS Past, Present and Future

Gate

Gate

Gate

Gate 1

Bulk-Si

SOI

Gate 2

Planar

UTB planar

Double gate

Fin FET

Gate

Gate

Gate

Gate

GAA

Ω-gate

Pi-gate

Tri-gate

Fig. 1.11 Schematics of different transistor designs starting from the classical to advanced three-dimensional transistors.

The two important points for the performance of MUGFETs are the thickness of BOX to control the transport through the channel and the doping level in the body for a designed threshold voltage. At first, by reducing the BOX thickness, DIBL is decreased. The strategy of BOX thickness in downscaling of the transistors is demonstrated in Fig. 1.12A and B. This is crucial to increase the control of carrier transport as well as high drain current [15]. Following this design, FinFETs were introduced. The distinguishable difference of a FinFET structure with other transistors is that the body of the device is a thin fin of Si (SiGe, Ge, or III–V material) where its thickness is the effective channel length of the transistor. Therefore, all categories of these transistors are also known as multigate FETs (MUGFETs). In principle, MUGFET shave a number of parallel nanowires (the so-called fingers) with a joint gate electrode. In such structures, the drive current drive could be increased by increasing the number of fingers of the transistor. The most benefit of 3D transistors is that by wrapping around the transistor gate, a better control over electrical transport through the channel is provided. Therefore, the SCE, which is an important problem for small gate lengths, is reduced, resulting in a decrease in the leakage current in the transistor. This leakage phenomenon emerges drastically for gate lengths smaller than 20 nm [6]. The performance of FinFETs depends strongly on physical dimensions (length, width, and height), and shape as well as on the crystal orientation of the fin and body doping concentration. The width of the fin is directly coupled to the short channel effect, whereas the height is limited to the etch process. Fig. 1.13 shows the impact of the fin dimensions on DIBEL. The figure shows that careful attention has to be paid on one side on the link of fin width to gate length of transistor but also the fin height [16]. The optimum shape is obtained when the width and height of fins have to be less than a half and onefifth of the gate length, respectively.

Basics of metal–oxide–semiconductor field-effect transistor (MOSFET)

tsi reduction with Lg scaling

Impact of BOX thickness 300

11 Impact of UTBOX

exp. FDSOI (EOT ~ 1.7 nm)

200

100

14 nm 12 nm

8

6

3 15

10

22 nm

BOX = 10 nm

Tox > 1.2 nm BOX = 50 nm

4 5

24 nm

7

5

TBOX = 10 nm 50

0

38 nm

18 nm

9 TBOX = 145 nm

150

0

BOX = 7.5 nm

10

LG = 18 nm EOT = 1.7 nm Tsi (nm)

DIBL (mV/V)

250

15

10

20 Gate length (nm)

TSOI (nm)

with GP 1020cm−3 30

Fig. 1.12 (Left) The impact of oxide thickness of SOI wafer on transistors’ DIBL whereas (right) the correlation between Si cap layer thickness with transistors’ gate lengths.

Tri-Gate FET relaxed fin dimensions WSi > Lg/2; HSi > Lg/5

Lg Gate

hSi

Lg

FinFET Narrow fin WSi ~ Lg/2

Si

hSi

wSi

Gate

Si

Pfin

HSi / Leff

Body dimensions 1.5

required for

1.0

Tox = 1.1 nm

wSi

DIBL = 100 mV/V Lg

0.5 hSi 0.0

0.5

1.0 1.5 WSi / Leff

2.0

Si wSi

Gate UTB FET Ultra thin SOI HSi ~ Lg/5

Fig. 1.13 Correlation of FinFETs’ width and height to the gate length and the impact on DIBIL.

The shape of fins depends on processing and it determines the transistor’s performance. For example, a triangle fin is usually desired not only due to its high structural strength for manufacturing, but also because such fins have a higher area-to-volume ratio compared to rectangular ones. Since its conduction in Si depends on the crystal orientation, the optimum mobility is obtained in (100) and (110) direction for nFETs and pFETs, respectively [17]. From a practical point of view, when the fins are formed in // or ┴ to the wafer flat, the transistor channel is oriented along (110) planes, otherwise a rotation at 45 degrees makes a (100) oriented channel as shown in Fig. 1.14 [17].

CMOS Past, Present and Future

% Idsat Improvement over (100)

16

Lg = 50 nm

30

Lg = 35 nm Lg = 25 nm

20

D

Lg = 18 nm

G

10

(110)

(100)

~(111)

(110)

S (110) Surface

PMOS

0

NMOS

−10 (100)

(111)

(110)

Orientation

Fig. 1.14 Figure illustrates the improvement in saturation current for carrier transport in different orientations in n- and pMOSFETs.

References [1] J. Cartwright, Intel enters the third dimension. Nature (2001), https://doi.org/10.1038/ news.2011.274. [2] D. Hisamoto, et al., FinFET—a self-aligned double-gate MOSFET scalable to 20 nm, IEEE Trans. Electron Devices 47 (2000) 2320–2325. [3] H.H. Radamson, The challenges of advanced CMOS process from 2D to 3D, Appl. Sci. 7 (2017) 1047. [4] E.S. Yang, Microelectronic Devices, Mcgraw-Hill College, New York, 1988 ISBN-10: 0071003746. [5] S.E. Thompson, S. Parthasarathy, Moore’s Law: the future of Si microelectronics, Review feature, Mater. Today 9 (2006) 20–25. [6] S.E. Thompson, R.S. Chau, T. Ghani, K. Mistry, S. Tyagi, M.T. Bohr, In search of "Forever," continued transistor scaling one new material at a time, IEEE Trans. Semicond. Manuf. 18 (2005) 26. [7] F. Schwierz, H. Wong, J.J. Liou, Nanometer CMOS, Pan Stanford, Singapore, 2010. [8] F. Schwierz, Graphene transistors: status, prospects, and problems, Proc. IEEE 101 (2013) 1567–1584. [9] M. Lundstrom, Z. Ren, Essential physics of carrier transport in nanoscale MOSFETs, IEEE Trans. Electron Devices 49 (2002) 133–141. [10] M. Lundstrom, Device physics at the scaling limit: what matters? [MOSFETs], Proceedings of the IEEE International Electron Devices Meeting, 2003, pp. 1–4. [11] N. Mohta, S.E. Thompson, Mobility enhancement: the next vector to extend the Moore’s law, IEEE Circuits Device Mag. (September/October) (2005). [12] A. Dixit, A. Kottantharayil, N. Collaert, M. Goodwin, M. Jurczak, K. De Meyer, Analysis of the parasitic S/D resistance in multiple-gate FETs, IEEE Trans. Electron Devices 52 (2005) 1132. [13] W. Wu, M. Chan, Gate resistance modeling of multifin MOS devices, IEEE Electron Device Lett. 27 (2006) 68.

Basics of metal–oxide–semiconductor field-effect transistor (MOSFET)

17

[14] J. Appenzeller, J. Knoch, V. Derycke, R. Martel, S. Wind, P. Avouris, Field-modulated carrier transport in carbon nanotube transistors, Phys. Rev. 89 (2002) 126801. [15] O. Faynot, in: Benefits and Challenges of FDSOI Technology for 14 nm Node, 2011 IEEE International SOI Conference, 2011, pp. 1–21. [16] J.-W. Yang, J.G. Fossum, On the feasibility of nanoscale triple-gate CMOS transistors, IEEE Trans. Electron Devices 52 (2005) 1159–1164. 5243–5275. [17] L. Chang, M.-K. Ieong, M. Yang, CMOS circuit performance enhancement by surface orientation optimization, IEEE Trans. Electron Devices 51 (2004) 1621–1627.

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Scaling and evolution of device architecture

2

H.H. Radamson*,†, E. Simeon‡, J. Luo*,†, G. Wang*,† *Institute of Microelectronics of Chinese Academy of Sciences (IMECAS), Beijing, PR China, † University of Chinese Academy of Sciences (UCAS), Beijing, PR China, ‡Imec, Leuven, Belgium

2.1

Introduction

Moore’s law was introduced by Intel founder Gordon Moore in 1969 [1] with an initial intention of reducing cost per function on a chip. His business idea was based on doubling of the number of transistors per area on a chip every 12 months. Meanwhile, this requirement was modified to every 18 months in the past decade. Although Moore’s law is basically an economics driven law, it has been the driving force for the semiconductor industry since the early days and has been the guiding principle for developing what has been called the Roadmap of the Semiconductor Industry Association over the years. Initially, scaling involved the reduction of the feature size of a metal-oxide-semiconductor (MOS) transistor by a scaling factor λ, staying in the same planar architecture and in the Si/SiO2 materials’ system. The MOS field-effect transistor (MOSFET) is the workhorse of the leading edge and dominant complementary metal-oxide-semiconductor (CMOS) technology, where every next step is called a technology node. This evolutionary approach worked well until the turn of the century, when the impact of gate tunneling current IG on the off-state current Ioff at zero gate voltage VG could no longer be kept at tolerable levels. This was the onset of what could be called a revolution in the device scaling, where new materials and process modules (gate last versus gate first) have been introduced in CMOS, starting with a metal gate/high dielectric constant or high-κ gate oxide (MG/HK). As will be seen below, the replacement of SiO2 by a high-κ oxide allows use of a thicker gate dielectric, with increasing gate capacitance density (per unit of area). This drastically reduces the direct tunneling current and alleviates the Ioff problem to acceptable levels. The introduction of HfO2 occurred at the 45 nm node. A possible view on the revolutionary scaling road map is presented in Fig. 2.1, defining the approximate node where certain new materials and/or process modules have been introduced. While the introduction of novel materials and/or process modules in planar technologies has been quite successful in boosting the device performance in pace with Moore’s law, this has no longer been sufficient at some point. The main reason is again the Ioff, which becomes more and more degraded by the short-channel effects (SCEs), like the drain-induced barrier lowering (DIBL) and the gate-induced drain leakage (GIDL) current. Mitigation of these SCEs necessitates CMOS Past, Present and Future. https://doi.org/10.1016/B978-0-08-102139-2.00002-1 Copyright © 2018 Elsevier Ltd. All rights reserved.

20

CMOS Past, Present and Future

10 Microtechnology

3 mm 1.5 mm

Size (nm)

1

0.8 mm

Nanotechnology

0.32 mm 1.60 mm

0.1

90 nm

Strain engineering

45 nm

HK & MG

22 nm 11nm

0.01 Evolutionary CMOS

0.001 1970

5 nm

NWs & NTs

Revolutionary CMOS

1980

1990

2000

2010

2020

2030

Production (year)

Fig. 2.1 Revolutionary technology road map for high-performance devices. HK&MG, high-k and metal gate; NWs, nano wires; NTs, nano tubes.

changing to another device architecture from planar to vertical FinFET, which took place around the 22 nm node. The reason for this transition is the fact that a trigate, omega gate, and ultimately a gate-all-around (GAA) architecture allows a much better control over the channel by the gate as discussed in Chapter 1. Alternatively, Ultra-thin film, ultra-thin buried oxide (UTTB) (BOX) silicon-on-insulator (SOI) devices may achieve competitive gate control. The ultimate CMOS-based devices will have a nanowire (NW) architecture—vertical or multiple planar—and possibly in a high mobility (μ) channel material.

2.2

Dimension and architectural scaling

For several decades, the reduction of the device feature size relied mainly on the ability to reduce the wavelength of the exposure light source in optical lithography to the desired minimum feature size, while maintaining the other technological steps. This means that for decades, the processing of planar CMOS transistors hardly changed, based on a polycrystalline silicon/SiO2 gate stack, ion implanted source and drain regions, self-aligned silicidation of gate, source and drain and device isolation, which was originally LOCal oxidation of silicon (LOCOS) and in later nodes replaced by shallow trench isolation (STI).

2.2.1 Scaling principles The basic scaling principles are illustrated in Fig. 2.2 and summarized in Table 2.1. It introduces a constant scaling factor λ ( 0); γ is a numerical constant. Eq. (2.1) is also valid for partially depleted (PD) SOI MOSFETs. The meaning of λb is that the gate length must be larger in order to have a proper scaling of the transistor performance, assuring sufficient gate control over the SCEs [10]. This introduces an additional condition for device scaling, which is not obvious in

Scaling and evolution of device architecture

23

Table 2.1: the junction depth of the source and drain should also become more shallow (tj should reduce accordingly) in order to maintain good device performance (for more details, see Chapter 6). In the case of fully depleted (FD) SOI, on the other hand, the film thickness tSi is smaller than the junction depth or than wdep and wd. In that case, Eq. (2.1) transforms into [11]: rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi εSi λ1 ¼ tSi tox εox

(2.2)

for a single-gate planar transistor in an SOI substrate (tSi is the silicon film thickness). A cross section of the FD SOI MOSFET is given in Fig. 2.3. In the case of a high-κ dielectric transistor, tox in Eqs. (2.1) and (2.2) can be replaced by the EOT (or, more precisely, the equivalent inversion capacitance thickness, including the thickness of the inversion layer for a metal-gate transistor). For good control of the SCEs, the gate length should be three to four times this natural length, as shown in Fig. 2.3 [12]. In the case of FD SOI, this implies that the silicon film thickness should scale with the same factor λ as the gate length and tox in order to maintain the same level of SCE control. However, an alternative way to improve the gate control over the channel is by moving to an alternative device architecture, with two, three, or four gates, as shown in Figs. 2.4 and 2.5 [12]. This follows from the corresponding natural lengths summarized in Table 2.2 and explains the introduction of the fin-type architecture on bulk silicon wafers in the 22-nm CMOS node [13–15], using tapered fins. Vertical fins were introduced in the 14 nm node [16]. As a competing path, planar FD SOI technologies have been developed on UTB SOI wafers [17–20]. One of the advantages of FD SOI technologies is that the back-gate bias can be employed as an additional degree of freedom to optimize the device performance, especially for low-power applications [21].

VS

VG

VD Si film

Sourc

e

Buri

ed o

Si

xide

H

W

L Gate

Drain

STI

VB

Fig. 2.3 Cross section of an ultra-thin buried oxide (UTBOX) ultra-thin film (UTF) SOI transistor. Right: Top view of a trigate FinFET on an SOI substrate.

CMOS Past, Present and Future

Silicon thickness width to gate length ratio

24

Surrounding 4 gates

1

2 gates

0.8 0.6

1 gate

0.4 0.2 0

0

10

20

30

40

50

60

70

80

90

100

Gate length (nm)

Fig. 2.4 Maximum allowed silicon film thickness and device width versus gate length to avoid SCEs in single-, double-, and quadruple-gate SOI MOSFETs [12].

Planar double-gate

Triple-gate

Gate metal

FinFET

Top Si

Gate-all-around or quadruple gate

Si dioxide

Si substrate

Fig. 2.5 Schematic of various multiple gate architectures on SOI substrates.

Table 2.2

Natural length in SOI devices with different architectures

Double-gate

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi εSi εox tSi tox [11] qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi λ2 ¼ 2εεSiox tSi tox [11]

Surrounding-gate

λ3 ¼

Single-gate

λ1 ¼

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi εSi 4εox tSi tox

ðsquare cross

sectionÞ

λ4 ¼

λ5 ¼

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi   εSi εox tSi 1 + 2εox 4εSi tox tSi tox [13]

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi   u 2tox u 2 2 + εox tSi t2εSi tSi ln 1 + tSi 16εox

ðcircular cross

[14]

sectionÞ

Scaling and evolution of device architecture

25

2.2.3 Junctionless transistor One of the challenges with scaling of transistors is the scaling of the junctions: by reducing the junction depth, the sheet resistance increases for the same active doping concentration. This means that the parasitic series resistance and associated dissipation and device performance degradation increase as well. One pathway, to be discussed in Chapter 6, is to increase the active doping concentration even above the equilibrium solid solubility limit, by applying ultrashort (ns or ms) annealing schemes. Alternatively, one can replace the traditional S/D junctions either by Schottky barrier contacts or by relying on a junctionless approach. The issue with Schottky barrier contacts is that a low barrier is, in principle, required for both electrons and holes, which is hard to meet in practice using the same metallization scheme. Generally, two different low-barrier metal contacts are combined in order to have satisfactory n- and p-type conduction. A much simpler case is the fabrication of junctionless transistors (JNTs), schematically shown in Fig. 2.6 [22,23]. Such devices have been initially introduced for SOI structures, where the channel is uniformly doped, typically in the range of 1  1019 cm 3 to 1  1020 cm 3, by a high-dose ion implantation. The channel should be sufficiently thin so that the channel is depleted below the threshold. This requires an appropriate gate metal work function. Applying a more positive gate potential should reduce the depletion width and attract electrons to the surface (accumulation type of transistor). Besides the simplicity of processing, it has been shown that in a realistic CMOS environment, better performance [24] and reliability [25] can be achieved for NanoWire JNT. A JNT can also be fabricated to yield low subthreshold swings in combination with impact ionization effects [23]. Issues could be the degradation of the mobility by Coulomb scattering by the high channel doping and the associated performance variability.

Source

Gate

Drain

Inversion mode short channel length

Source Gate

Drain

Inversion-mode Ultra-short channel length

Source

Gate

Junctionless short channel length

Drain

Source

Gate

Drain

Junctionless Ultra-short channel length

Fig. 2.6 Schematics of the source and drain doping in inversion-mode (IM) for a conventional transistor and a junctionless transistor with both short channel and ultrashort channel.

26

2.3

CMOS Past, Present and Future

Lithography for downscaling

Lithography is a technology which was used by the semiconductor industry for transistor and ICs of very large-scale integration (VLSI) manufacture since the 1950s. In the state-of-the-art ICs, lithography technology has been the first challenge of those processes, which has to be considered and resolved. Therefore, the IC industry has been paying more and more attention to the development of lithography. Lithography technology is a patterning transfer process which transfers the graphics from a designed mask or reticle to the photoresist on a prepared substrate. Resolution of the lithography system is defined by how sharp the smallest critical dimension (CD) can be distinguished. The resolution is determined by Rayleigh’s Law [26]: R¼

k1 λ NA

(2.3)

where R is the resolution, λ is the wavelength of light, k1 represents the proportional coefficient of the lithography process complexity, and NA is the numerical aperture. Eq. 2.3 indicates that the resolution of the lithography system can be improved by decreasing the λ, k1 and increasing the NA.

2.3.1 The resolution enhancement 2.3.1.1 Wavelength of light source reduce The precision of transistor gate dimensions is determined by lithography resolution and it is a key issue in CMOS transistors downscaling. The main method of achieving smaller feature sizes is to apply light sources of shorter wavelengths in a lithography system. Along with the development of IC technology, in order to adapt to the downscaling, the wavelengths of applied light in the lithography process are reduced from 436, 405, and 365 nm in the near ultraviolet (NUV) region to 248 and 193 nm in the deep ultraviolet (DUV) region. In the early times, the light source of the lithography system was Hg lamps. Such a light source produces 400 nm wavelength with different spectral lines at 436, 405, and 365 nm, which are also termed the g-line, h-line, and i-line, respectively. In the development of the industry, the continuous downscaling road map also requested higher throughput to achieve the goals to increase the density transistors in the chip and to reduce the production costs. However, Hg lamp as the light source could not meet these industry’s needs and the next generation of lithography tools with DUV excimer lasers was made. These types of lasers range from the krypton fluoride (KrF) laser, which can generate 248 nm wavelength, to the argon fluoride (ArF) laser whose range goes even to the 193 nm wavelength [27]. At present, most of the IC chip manufacturers use DUV (248 and 193 nm) lithography technology. KrF stepper was first applied in the 0.25 μm technology node and it was developed up to the 130 nm node. Later, ArF stepper was mainly used for 0.11 μm,

Scaling and evolution of device architecture

27

90 nm, and 65-nm technology nodes. Owing to the resolution-enhanced technology, the 193-nm ArF immersion lithography technology can meet the 45-nm technology node requirements [28]. After the further development of lithography technology, the193-nm ArF immersion with multiple patterning is the best developed technique for 22 nm and beyond nodes [29].

2.3.1.2 Improvement of NA Immersion lithography technology is filled with a special purified liquid between the lens of projection and the substrate, which has a higher refractive index (n) than air. In this way, the light beam is focused to obtain a high resolution for smaller nanoscaled patterning [30]. Therefore, the NA of the projection prism can be increased much to obtain the high resolution. Recently, research people reported that ceramic material like Lutetium aluminum garnet (Al5Lu3O12, LuAG) has a high refractive index (2.14), which has been proposed as a high index lens material. This lens material combined with high index liquids in a 193 nm immersion tool can make an outstanding solution for the 10-nm technology node [31].

2.3.2 Double patterning technology Double patterning (DP) is a type of resolution enhancement method in lithography to increase the feature density. Unlike the shrinking reticle patterns to smaller sizes, the double patterning technique is based on exposure to different reticles to offset each other, which is then followed by wafer etching process steps [32]. DP was the key method which was applied in 32 and 22 nm half-pitch nodes by the semiconductor industry [33]. There are several types of double patterning technologies ranging from double exposure (DE) to self-aligned spacer, double expose, and double etch (DE2) [34,35]. DE is two separate exposures on the same photoresist layer using two different masks in sequence. It is usually used for patterns of the same layer, which appear to be very different or have incompatible densities or spaces. Fig. 2.7 is the description of the double exposure lithography process. The DE technique allows the manufacturability of the minimum spacing feature in a layout with various CDs. As long as the DE can be effectively used and is under the control of the alignment tolerance, it is a better patterning method compared to self-aligned spacer, double expose, and double etch (DE2), because it does not require additional subsequent processing steps. A self-aligned spacer patterning method is used on a conformal film deposited on the patterned wafer, where spacers are initially formed and used as hard mask to etch the below layer as shown in Fig. 2.8. The width of the exposed lines depends on the width of the spacer. The spacer lithography technique has most widely been applied in patterning fins for FinFETs. The spacer materials are commonly choosing hard mask dielectric materials (SiN and SiO2), whose etched post-pattern quality tends to be

28

CMOS Past, Present and Future

(A)

(B)

(C)

(D)

Fig. 2.7 Double exposure lithography process: (A) photoresist coating, (B) first exposure, (C) second exposure, and (D) development.

Substrate Dummy gate

(A)

(D)

Spacer materials Hard mask

(B)

(E)

(C)

(F)

Fig. 2.8 A self-aligned spacer patterning lithography process: (A) dummy gate formation, (B) conformal film deposition, (C) spacer formation, (D) dummy gate removal, (E) etching with spacer mask, and (F) spacer mask removal.

superior to the etched photoresist pattern, but it is often desirable to better control the line edge roughness (LER). Among the self-aligned spacer patterning technologies, self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) techniques are other important resolution enhancement methods which might be applied beyond the 7-nm technology node [34].

Scaling and evolution of device architecture

29

2.3.3 Extreme ultraviolet lithography (EUVL) technology EUVL technology is an advanced technology with a light source of 13.5 nm, which is extremely short wavelength and can be applied for beyond the 10 nm node. EUVL enables the use of only one mask exposure instead of multiexposure. However, there are still three issues to be solved before this technique can be applied in mass production: a light power source, resists, and mask infrastructure. Among these issues, to make such a lithography tool, economical production capacity and producing a stable light source are the most difficult issues to be solved. For a wafer-per-hour (WPH) up to 125 in the 12-inch production line, a light source power of 200 W is needed and EUVL has to satisfy this requirement [36]. The development of resist material is one of the critical technical issues of EUVL. This material is necessary to have the excellent characteristics: high resolution, high sensitivity as well as low line-edge roughness (LER) and low outgassing simultaneously [37,38]. When EUVL continues to move toward mass production manufacturing, the availability of a defect-free reflective photomask is also one of the critical challenges which needs to be considered [39]. EUV’s photomasks work in reflective mode. To produce these masks would introduce new materials and surfaces, which might cause high particle adhesion on the surface of masks, creating a cleaning issue [40]. Therefore, a special pellicle is designed to protect the mask from particles adhesion when the EUV scanner is in use. However, an EUV mask with a pellicle has still some remaining issues to be solved. These issues are also addressed: the stress of the protective film module may cause an overlay shift; it may also prevent the film from light absorbing, and the mask inspection can be limited to photochemical light, which reduces the valuable EUV power. In addition to EUV technology, very extremely short wavelength techniques such as using the X-ray lithography (XRL) with 1 nm wavelength [41] and deep X-ray lithography (DXRL) with 0.1 nm wavelength [42] are under development and they belong to next-generation lithography (NGL), which may provide a solution for technology node beyond 5 nm in future.

2.3.4 Reticle enhancement techniques (RETs) As the transistor critical dimensions downscaled, the making of mask started becoming more and more difficult. Different RETs were developed and applied to the mask to avoid diffraction issues. Optical proximity correction (OPC) is one of the RETs used to optimize the mask patterns and to improve the printability on the substrate as shown in Fig. 2.9 [43]. OPC is a technique used to compensate for image inaccuracies that happened during subwavelength lithography, such as a pattern that is less than the wavelength of the used light. These images are inaccurate to include changes in corner rounding, line-end shortening, and changes in linewidth when located in isolated or dense environments. It is possible to apply models for these effects and use complex software to correct the design data [44]. As shown in Fig. 2.9, the corner rounding and line-end shortening were corrected with OPC.

30

CMOS Past, Present and Future

Fig. 2.9 A pattern transfer (A) without and (B) with OPC.

Serif

Mask

Corner rounding

Substrate

Line-end shortening

(A)

(B)

Another type of RET is phase shift masks (PSMs), which are used to extend the resolution capability and the aerial image contrast of the stepper or scanner. The phase shift mask is a photomask that uses the interference generated by the phase difference to improve the image resolution in lithography. There are alternating and attenuated phase shift masks. The phase shift mask relies on the fact that the light which passes through the transparent media undergoes phase change as a function of its optical thickness [45].

2.4

Electron-beam lithography (EBL)

Electron-beam lithography (EBL) is the practice of scanning a focused beam of electrons to write custom shapes on an electron-sensitive resist film [46]. The electron beam changes the solubility of the resist so that it can be selectively removed by immersing the exposed or unexposed areas of the resist in the solvent. The primary advantage of EBL is that it can draw custom patterns (direct-write) with sub-10 nm resolution. However, this technique has a low throughput since the time for writing is relatively high and it is doubtful whether it can be used as a lithography tool in a technology road map in future [47]. One limitation of the EBL technique is that when the small feature is patterned, the number of electrons in the beam must be reduced. This results in a large change in dose due to shot noise effects. The new generation of EBL is based on secondary electrons as the main beam. When the high-energy electrons pull out electrons from the shell of the atom, the secondary electron beam is induced. This type of electron has a significantly lower energy and produces less beam-related defects.

Scaling and evolution of device architecture

2.5

31

Strain engineering

The implementation of high-κ gate dielectric since the 45 nm node alleviates the issue of the gate tunneling leakage current, but raises another concern. As can be seen from Fig. 2.9, n-channel transistors with a poly/HfO2 gate stack suffer from a lower inversion electron mobility, compared with a poly/SiON device [48]. As will be outlined in Chapter 4, this is among others related to the lower quality of the gate dielectric (higher trap density compared with SiO2) and its interface with silicon. A better interface quality, that is, a reduced density of interface states (Dit), can be achieved by fabricating a thin good-quality interfacial oxide (usually SiO2), which also offsets the high oxide trap density from the channel. Nevertheless, there is still a degradation of the inversion layer mobility, pointing toward additional scattering and/or scattering mechanisms. For example, the polysilicon/HfO2 interface is also characterized by a high Dit causing Fermi level pinning, poly depletion (and scattering), and a nonideal threshold voltage. These problems can be resolved by replacing the poly by a metal gate with appropriate work function to fine tune VTH (Chapter 4). This removes part of the remote scattering and improves the mobility in Fig. 2.10. Another knob to turn is the implementation of mechanical strain in the channel, for example, by using a strained-silicon (sSi) substrate. Strain engineering has been implemented since the 90 nm node [49–51] and can be considered as a “beyond geometrical scaling” method to boost the device performance.

2.6

Impact of scaling

Changing from a planar to a fin-type architecture has consequences also for the implementation of strain engineering. A first important aspect is that for narrow fins, the conduction planes change from (100) to (110), which also modifies the low-field mobility and the impact of strain on it. Another facet is that for narrow fins, the strain will relax elastically in the width direction, so that 2D stress transforms into a 1D Fig. 2.10 Inversion layer mobility versus electric field for nMOSFETs with different gate stacks, on a strained or conventional silicon channel, compared with universal mobility [48].

500 400

300 200 100

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

32

CMOS Past, Present and Future

configuration. This implies that the most effective stressor techniques for planar devices cannot be directly translated to FinFETs, so that, for example, a TCAD assessment of the different stressor schemes is very helpful in defining the most optimal choice [52]. A detailed analysis has demonstrated that the use of CESL stressors will be rather ineffective for narrow fins. On the other hand, elevated CVD S/D stressors will remain effective in straining the FinFET channel. For pMOSFETs, this can be achieved by Si1 xGex S/D regions (see more information in Chapter 3), while for nMOSFETs, highly n-type doped Si:C S/Ds should be a good option [53–58]. Alternatively, it has been shown that highly in situ P-doped n+ CVD layers can introduce significant tensile stress, as can be judged from the high-resolution X-ray diffraction (HR-XRD) graph in Fig. 2.11 [59]. One of the issues is to maintain P as much as possible in substitutional sites during subsequent thermal processing, in order to have a maximum electrical activation (lower sheet resistance) and the highest possible tensile strain [60,61]. It has been found, however, that while the sheet resistance can be further reduced by laser annealing, at the same time tensile strain is lost. This has been explained by the removal of inactive PVn complexes, on the one hand, and by the formation of interstitial (or precipitated) P, on the other [61]. Besides optimizing the strain of an individual transistor, one has to consider that in a real circuit, there will be a mutual influence of the strain by neighboring so-called nested devices [62]. As an example, Fig. 2.12 exhibits the channel strain for p- and n-MOSFETs with Si1 xGex and Si:C stressors, respectively, as a function of the poly-to-poly distance Lp/p in nested planar transistors, derived from an analytical model or from finite element simulations (FEM) [62]. It is clear that for a higher integration density, i.e., a lower Lp/p, the maximum absolute channel stress reduces in both cases. From this, it is concluded that not only the process technology, but also the circuit design defines the final performance enhancement in scaled CMOS transistors.

106 105 Intensity (cps)

Fig. 2.11 Rocking curves for blanket layers with different phosphorus concentration. The shift of the peak from 500 to 1200 arcsec indicates increasing tensile strain with increasing P content [59].

Increasing P content

104 103 102 101 –500

0

500 1000 1500 2000 2500 3000 Omega (arcsec)

33

0 –1000 –2000 v –3000

10% Ge 15% Ge 20% Ge 25% Ge v 30% Ge

FEM simulations

0

Analytical model

–1000

10% Ge 15% Ge 20% Ge 25% Ge 30% Ge

–2000 –3000 102

103 Lp/p (nm)

104

Channel stress (MPa) Channel stress (MPa)

Channel stress (MPa) Channel stress (MPa)

Scaling and evolution of device architecture

FEM simulations Si-C S/D

3% C 2.5% C 2% C 1.5% C 1% C 0.5% C

Analytical model Si:C S/D

3% C 2.5% C 2% C 1.5% C 1% C 0.5% C

102

103 Lp/p (nm)

104

Fig. 2.12 Channel stress for pMOSFETs with Si1 xGex S/D stressors (left) and nMOSFETs with Si:C S/D stressors as a function of the device pitch Lp/p for planar nested transistors. Stressors with different Ge or C concentratisons have been considered. The top figures show FEM simulation results, while the bottom shows data from an analytical model. Polysilicon gate with Lg ¼ 20 nm have been considered [62].

2.7

Beyond CMOS and beyond Si CMOS

For the devices beyond CMOS and beyond Si CMOS, the most attractive options are tunnel FETs (TFETs) and spintronics. In the following section, these devices will be discussed shortly.

2.7.1 Tunnel FETs The tunnel field-effect transistor (TFET) is an experimental type of transistor. Though its device structure is very similar to a MOSFET, the fundamental working mechanism differs completely from the MOSFET and this makes TFETs a promising candidate for low power electronics. A basic p-i-n TFET structure and its band diagram is displayed in Fig. 2.13. In contrast to MOSFETs, in which carriers are thermally injected over a barrier at the source, the primary injection mechanism in a TFET is interband tunneling, whereby charge carriers transfer from one energy band into another at a heavily doped p+–n+ junction. In a TFET, interband tunneling can be switched on and off abruptly by controlling the band bending in the channel region by manipulating gate bias. This function can be realized in a reversed-biased p-i-n structure. In principle, the TFET is an ambipolar device, showing p-type behavior with dominant hole conduction and n-type behavior with dominant electron conduction. One challenge for TFETs is to realize high Ion because it critically depends on the transmission probability of carriers through the interband tunneling barrier. To realize a high tunneling current and steep slope for TFETs, the transmission probability of the

34

CMOS Past, Present and Future

Gate electrode n+

i

Gate electrode EC p+ n+

Buried oxide layer

p+

Si substrate

(A)

EV

Tunnel

(B)

Fig. 2.13 Schematics showing (A) a TFET device structure and (B) band diagram when TFET is switched on [63].

source-tunneling barrier should be close to unity for a small change in gate voltage (VG). The Wiener-Kramers-Brillouin (WKB) approximation suggests that the bandgap (EG), the effective carrier mass (m*), and the screening tunneling length (λtun) should be minimized for higher barrier transparency. This makes the III-V semiconductors the ideal channel materials for TFETs. Though EG and m* depend solely on the selected channel material, λtun is strongly affected by many parameters, for instance, device geometry, dimensions, doping profiles, and gate capacitance. A small λtun results in a strong modulation of the channel bands by the gate and this small λtun necessitates a high-κ gate dielectric with low EOT. Other issues in designing TFETs of high Ion are as what follow: (1) thickness of the channel should be minimized, showing in the best case one-dimensional electronic transport behavior; (2) doping profile at the tunneling junction should be as abrupt as possible, that is to say, the high source doping level must decay to the intrinsic level in a distance as short as possible. Recently, the TFETs have been demonstrated using Si, group III-V semiconductors, and carbon-based channel materials [64].

2.7.2 Spintronics Recently, a technology has emerged, called spintronics (spin transport electronics or spin-based electronics), where it is not the electron charge but the electron spin that carries information, and this provides an opportunity for a new generation of devices combining standard CMOS technology with spin-dependent effects. These spindependent effects arise from the interaction between the spin of the carriers and the magnetic properties of the materials. The spintronics technology can be widely applied in both memory and logic devices, due to advantages such as nonvolatility, increased data processing speed, decreased electric power consumption, and increased integration density, compared with conventional CMOS technology [65]. For the logic devices based on spintronics, a prototype was revealed by Datta-Das in 1990 and the scheme of a Datta-Das spin field-effect transistor is depicted in Fig. 2.14. The scheme shows the structure of a usual FET, with a source, a drain, a narrow channel, and a gate for controlling the current. The source (spin injector) and the drain (spin detector) are ferromagnetic metals or semiconductors, with parallel magnetic moments.

Scaling and evolution of device architecture

35

Fig. 2.14 Scheme of a basic spin field-effect transistor (SFET) [66].

Gate

n k W Source

Drain

The injected spin-polarized electrons with wave vector k move ballistically along a quasi-one-dimensional channel formed by, for example, an InGaAs/InAlAs heterojunction or graphene in a plane normal to n. Electron spins precess about the precession vector Ω, which arises from spin–orbit coupling and is defined by the structure and the material properties of the channel. The magnitude of Ω is tunable by the gate voltage VG. The current is large if the electron spins of most electrons at the drain keep the initial direction (toward the right top row) and small if the directions of electron spins are random (bottom row). Note that the precession period should be much larger than the time of flight for electrons. The role of the gate is to generate an effective magnetic field in the direction of Ω in Fig. 2.14, originating from the spin–orbit coupling in the channel material. This generated effective magnetic field causes the electron spins to precess. By tuning the gate voltage, the precession of electron spins in the channel can be manipulated, which leads to either a parallel or antiparallel electron spin at the drain, thus effectively controlling the drain current. The major challenges in the spin logic device that are addressed by experiment and theory include the optimization of electron spin lifetime in the channel, the detection of spin coherence in nanoscale structures, and transport of spin-polarized carriers across the gate with relevant length and heterointerfaces. In detail, there are at least four important requirements for realizing a high- performance SFET [66,67]: (1) the effective spin injection of spin-polarized carriers from the ferromagnetic source into a two-dimensional electron gas (2DEG) is important; (2) ballistic spin-polarized transport should be realized through the channel with a uniform structure inversion asymmetry coefficient by eliminating undesirable electric fields due to interface inhomogeneities; (3) the structure inversion asymmetry coefficient should be effectively controlled by the gate; and (4) the structure inversion asymmetry should dominate over the bulk inversion asymmetry, and the spin precession rate must be large enough to allow at least a half precession during the ballistic transport.

The SFETs using copper and 2D graphene as channel materials satisfied most of these requirements and therefore are extensively explored [68,69].

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CMOS Past, Present and Future

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[25] M. Cho, G. Hellings, A. Veloso, E. Simoen, P. Roussel, B. Kaczer, H. Arimura, W. Fang, J. Franco, P. Matagne, N. Collaert, D. Linten, A. Thean, On and off state hot carrier reliability in junctionless high-K MG gate-all-around nanowires, IEDM Technical Digest, The IEEE, New York, 2015, pp. 366–369. [26] A.H. Pfund, Rayleigh’s law of scattering in the infrared, JOSA 24 (6) (1934) 143–146. [27] D. Williamson, DUV or EUV, that is the question, Proc. SPIE 4146 (2000). [28] K. Mistry, C. Allen, C. Auth, et al., A 45 nm logic technology with high-k + metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging, IEEE International Electron Devices Meeting, 2007 (IEDM 2007), IEEE, 2008, pp. 247–250. [29] F.G. Pikus, A. Torres, Advanced multi-patterning and hybrid lithography techniques, Proceedings of the 2016 21st Asia and South Pacific Design Automation Conference (ASPDAC), Macau, China, 25–28 January 2016, 2016. [30] H. Sewell, P. Graeupner, D. McCafferty, L. Markoya, N. Samarakone, P. van Wijnen, et al., An update on the progress in high-n immersion lithography, J. Photopolym. Sci. Technol. 21 (2008) 613. [31] Y. Liberman, M. Rothschild, S.T. Palmacci, R. Bristol, J. Byers, N.J. Turro, et al., High indeximmersion lithography: preventing lens photocontamination and identifying the opticalbehavior of LuAG. Proc. SPIE 6924 (2008)692416 https://doi.org/ 10.1117/12.771462. [32] M. Levinson, Double double, toil and trouble, Microlithogr. World (2007)286361. [33] C. Bencher, Y. Chen, H. Dai, W. Montgomery, L. Huli, et al., 22 nm half-pitch patterning by CVD spacer self-alignment double patterning (SADP), in: Optical Microlithography XXI, vol. 6924, International Society for Optics and Photonics, 2008, p. 69244E. [34] H. Yaegashi, Pattern Fidelity control in Multi-patterning towards 7 nm node, Proceedings of the 2016 IEEE 16th International Conference on Nanotechnology (IEEE-NANO), Sendai, Japan, 22–25 August 2016, 2016 https://doi.org/10.1109/NANO.2016.7751406. [35] V.S. Basker, T. Standaert, H. Kawasaki, C.C. Yeh, K. Maitra, T. Yamashita, H. Sunamura, A 0.063 μm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch, VLSI Technology (VLSIT), 2010 Symposium on IEEE, 2010, pp. 19–20. [36] A. Pirati, R. Peeters, EUV lithography performance for manufacturing: status and outlook. in: Extreme Ultraviolet (EUV) Lithography VII, vol. 9776, SPIE, San Jose, CA, 2016 https://doi.org/10.1117/12.2220423. [37] D.D. Simone, M. Mao, Metal containing resist readiness for HVM EUV lithography, J. Photopolym. Sci. Technol. 29 (2016) 501–507. [38] D. Mamezaki, M. Watanabe, Development of the transmittance measurement for EUV resist by direct resist coating on a photodiode, J. Photopolym. Sci. Technol. 29 (2016) 749–752. [39] A.O. Antohe, D. Balachandran, SEMATECH produces defect-free EUV mask blanks: defect yield and immediate challenges. in: Extreme Ultraviolet (EUV) Lithography VI, vol. 94221B, SPIE, San Jose, CA, 2015 https://doi.org/10.1117/12.2176126. [40] Leading at the Edge, Technology and Manufacturing Day (Intel), Available at https://www.intc.com/default.aspx?SectionId¼817fbab8-2828-44a2-91a0-f10cb8ac2b03& LanguageId¼1&EventId¼637d959b-e595-4f0e-843e-5ee9af9d6520. Accessed 20 June 2017. [41] Y. Vladimirsky, A. Bourdillon, O. Vladimirsky, W. Jiang, Q. Leonard, Demagnification inproximity X-ray lithography and extensibility to 25 nm by optimizing Fresnel diffraction, J. Phys. D. Appl. Phys. 32 (22) (1999) 114.

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[55] Q. Zhou, S.-M. Koh, T. Thanigaivelan, T. Henry, Y.-C. Yeo, Contact resistance reduction for strained N-MOSFETs with silicon-carbon source/drain utilizing aluminum ion implant and aluminum profile engineering, IEEE Trans. Electron Devices 60 (2013) 1310–1317. [56] M.H. Lee, P.-G. Chen, S.T. Chang, Analysis of Si:C on relaxed SiGe by reciprocal space mapping for MOSFET application, ECS J. Solid State Sci. Technol. 3 (2014) P259–P262. [57] Y.-T. Chuang, K.-H. Hu, W.-Y. Woon, On the doping limit for strain stability retention in phosphorus doped Si:C, J. Appl. Phys. 116 (2014)033503. [58] J.M. Hartmann, J. Aubin, S. Barraud, M.P. Samson, Atmospheric pressure selective epitaxial growth of heavily in situ phosphorous-doped Si(:C) raised sources and drains, ECS J. Solid State Sci. Technol. 6 (2017) P52–P57. [59] E. Rosseel, H.B. Profijt, A. Hikavyy, J. Tolle, S. Kubicek, G. Mannaert, C. L’abbe, K. Wostyn, N. Horiguchi, T. Clarysse, B. Parmentier, S. Dhayalan, H. Bender, J.W. Maes, S. Mehta, R. Loo, Characterization of epitaxial Si:C:P and Si:P layers for source/drain formation in advanced bulk FinFETs, ECS Trans. 64 (6) (2014) 977–987. [60] E. Rosseel, S. Dhayalan, A. Hikavyy, R. Loo, H.B. Profijt, D. Kohen, S. Kubicek, T. Chiarella, H. Yu, N. Horiguchi, D. Mocuta, K. Barla, A.V.-Y. Thean, G. Bartlett, J. Margetis, N. Bhargava, J. Tolle, Selective epitaxial growth of high-P Si:P for source/ drain formation in advanced Si nFETs, ECS Trans. 75 (8) (2016) 347–359. [61] S.K. Dhayalan, J. Kujala, J. Slotte, G. Pourtois, E. Simoen, E. Rosseel, A. Hikavyy, Y. Shimura, S. Iacovo, A. Stesmans, R. Loo, W. Vandervorst, On the manifestation of phosphorus-vacancy complexes in epitaxial Si:P films, Appl. Phys. Lett. 108 (2016) 082101. [62] G. Eneman, E. Simoen, P. Verheyen, K. De Meyer, Gate influence on the layout sensitivity of Si1-xGex and Si1-yCy S/D transistors including an analytical model, IEEE Trans. Electron Devices 55 (2008) 2703–2712. [63] S.M. Turkane, A.K. Kureshi, Review of tunnel field effect transistor (TFET), Int. J. Appl. Eng. Res. 11 (2016) 4922–4929. [64] A.M. Ionescu, H. Riel, Tunnel field-effect transistors as energy-efficient electronic switches, Nature 479 (2011) 329–337. [65] X.Y. Fong, Y.S. Kim, K. Yogendra, D.L. Fan, A. Sengupta, A. Raghunathan, K. Roy, Spin-transfer torque devices for logic and memory: prospects and perspectives, IEEE Trans. Comput. Aided Design Integr. Circuits Syst. 35 (2016) 1–22. [66] I. Zˇutic, J. Fabian, S. Das Sarma, Spintronics: Fundamentals and applications, Rev. Mod. Phys. 76 (2004) 323–410. [67] S.A. Wolf, D.D. Awschalom, R.A. Buhrman, J.M. Daughton, S. Von Molna´r, M.L. Roukes, A.Y. Chtchelkanova, D.M. Treger, Spintronics: A spin-based electronics vision for the future, Science 294 (2001) 1488–1495. [68] W. Han, R.K. Kawakami, M. Gmitra, J. Fabian, Graphene spintronics, Nat. Nanotechnol. 9 (2014) 794–807. [69] S.-C. Chang, R.M. Iraei, S. Manipatruni, D.E. Nikonov, I.A. Young, A. Naeemi, Design and analysis of copper and aluminum interconnects for all-spin logic, IEEE Trans. Electron Devices 61 (2014) 2905–2911.

Strain engineering

3

H.H. Radamson Institute of Microelectronics of Chinese Academy of Sciences (IMECAS), Beijing, PR China; University of Chinese Academy of Sciences (UCAS), Beijing, PR China

3.1

Introduction

In crystalline semiconductors, the electrical, optical, and mechanical properties may change when strain is imposed on the material. Strain is defined as a mechanical distortion resulting from an employed force to the crystal matrix. The dimension and direction of this force is crucial for the effect of the induced strain. For CMOS transistors, the acting force is created by stressor materials over the channel region to change the transport properties. This may occur either by epitaxial growth of Si1 xGex and Si1 yCy in recessed source/drain regions [1–10] or by deposition of nitride dualstress liners (DSL) on the top of the transistor body [3,11–16]. The other ways to generate strain in the channel are stress memorization technology (SMT) [17–22] and high-k metal-gate stress (HKMGS) technology [23]. The epitaxial growth of stressor materials occurs in the source/drain regions on a well designed recess by using the chemical vapor deposition (CVD) technique. In these transistors, additional strain amount is usually created by applying the other aforementioned strain engineering methods. Among the strain engineering techniques, HKMGS provides an easy integration and high efficiency in inducing strain into the channel. In the beginning, Intel employed Al and TiN as the filling metals in the gate region in the 45-nm node n-MOSFETs to induce compressive strain to enhance the performance of transistors [4]. However, as the aspect ratio of the dummy gate trench became larger in the 22-nm node, filling the trench by conventional Al metal without voids confronted an overwhelming challenge. In recent years, ALD W films in combination with SiH4 and B2H6 precursors have been studied as a metal gate. The induced strain in ALD W films is sensitive to the crystalline quality and it is precursor dependent [23].

3.2

Basic definitions of strain type and design

In general, there are two types of strain: compressive and tensile. Consider x, y, and z coordinates for a cubic crystal; if a compressive force acts inward in the x- and y-directions, then the cube becomes elongated in the z-direction and the strain is called compressive. Meanwhile, if the crystal is exposed to an outward force in the x- and y-directions, the lattice in the z-direction shrinks and the strain becomes tensile. Examples for compressive and tensile strained materials could be Si1 xGex on Si and Si1 yCy on Si (or Si on strain-relaxed Si1 xGex), respectively. CMOS Past, Present and Future. https://doi.org/10.1016/B978-0-08-102139-2.00003-3 Copyright © 2018 Elsevier Ltd. All rights reserved.

42

CMOS Past, Present and Future

Strain can be resolved into vertical (ε┴) and in-plane (ε//) components as follows: a?

ε? ¼

ab

(3.1a)

ab

and a== ab ab

ε== ¼

(3.1b)

where the lattice constants are described in Fig. 3.1. The sign of strain components varies depending on the type of strain. In Fig. 3.1, the components of compressive strain are ε┴ > 0 and ε// < 0 but for tensile strain they are ε┴ < 0 and ε// > 0. In many cases, the mismatch components are measured and the values are converted to lattice constants. The vertical and in-plane mismatch components for crystalline layers are written according to f? ¼

a? ab asub

(3.2a)

f== ¼

a== ab asub

(3.2b)

and

Compressive strain a// = asub and a⊥ > asub

ab>asub ab

Strain (partially and totally) compensated a// = asub and a⊥ ≥ asub

e⊥ > 0 and e// < 0 f⊥ > 0 and f// = 0

Substrate asub

Tensile strain

Strain (partially) relaxed

a// = asub and a⊥ < asub ab< asub

a// > asub and a⊥ > asub

e⊥ < 0 and e// > 0 ab

f⊥ < 0 and f// = 0

Fig. 3.1 A drawing of different ways to generate strain in cubic semiconductor alloys.

Strain engineering

43

In strained material, the in-plane component of the grown layer is aligned to the substrate and f// ¼ 0; meanwhile, the vertical mismatch for compressively strained crystals is f┴ > 0 and f┴ < 0 for tensile strain. The initial mismatch for unstrained materials can be formulated in terms of f┴ and f// when the Poisson ratio (ν) of the semiconductor is given as [24–26]
f ¼ f==

1 ν + f== f? 1+ν

(3.3)

The strain relaxation amount (R) is also a significant value which quantifies how much strain has been released upon relaxation. The R value is expressed in percentage and it is obtained from a fraction of R ¼ f///f. In Eq. (3.3), ν is a characteristic value for crystal which shows how a material responds elastically when a force is employed. Therefore, ν is expressed in terms of elastic constants (see Table 3.1) [31]. ν¼

c12 c12 + c11

(3.4)

For an alloy, the elastic constant Cij has to be calculated in order to determine the Poisson ratio. For example, for Ge1 xSix alloys, Cij-values are estimated from the following equation: Cij ðGe1 x Six Þ ¼ ð1

xÞCij ðGeÞ + xCij ðSiÞ

(3.5)

The composition in an alloy can be obtained from Vegard’s law (or other parabolic equations). As an example, for GeSi alloys, the Ge content is obtained from lattice constant values of Ge and Sn according to Eq. (3.6) [32]: f ðxÞ ¼ 3:675  10 2 x

5:01  10 3 x2

(3.6)

The strain can be compensated in an alloy if atoms with a different lattice constant are introduced into the lattice to counteract the induced compressive/tensile strain. Strain compensation may occur either in ternary or quandary alloys, for example, Si1 x yGexCy and Ge1 x y zSnxSiyCz or by highly doping, for example, B-doping in Si1 xGex layers.

Table 3.1

The elastic constants of the group IV materials

Elastic constant

Ge [27]

Sn [28]

Si [29]

C [30]

c11 (Mbar) c12 (Mbar)

1.26 0.44

0.69 0.29

1.67 0.65

10.79 1.24

44

CMOS Past, Present and Future

To estimate the lattice constant of a ternary semiconductor, more complicated equations are usually applied. For example, the lattice constant of Ge1 x ySnxSiy can be obtained from the following equation: aGe1

x y Six Sny

aGe + ΔSiGe x + θSiGe y + θSnGe yð1

where ΔSiGe ¼ aSi

3.3

aGe and ΔSnGe ¼ aSn

yÞ

(3.7)

aGe [33].

Strain design in MOSFETs

The strain can be generated either biaxially (two-dimensional or globally) or uniaxially (one-dimensional or locally) for a MOSFET application. Biaxial strain occurs when the stressor material is deposited over the whole wafer and later is processed for the transistor channel; however, for uniaxial strain the stressor material is embedded in the source/drain region to create strain in the transistor channel. Fig. 3.2 illustrates the methods to induce these types of strain in silicon material. Biaxially tensile-strained Si as channel material on a strain-relaxed SiGe virtual substrate was the first attempt for a MOSFET application. A drawback with such a design is that a relatively thick SiGe with graded Ge content (1 μm, 10% Ge) is necessary to create low defect density virtual substrate. This means that a few micrometers of SiGe layer is required to create high tensile strain. To integrate such thick SiGe layers is not realistic and such a structure design was abandoned after a few years. The main goals of inducing strain in the transistor structure are to reduce the effective mass as well as the carrier scattering during the transport in channel. Global epitaxy

Gate formation

Dopant implantation

Selective etch

Selective epitaxy

Strained layer Buffer layers Si substrate

Gate formation

Si substrate

Fig. 3.2 Schematic of formation of biaxial and uniaxial strain in channel region in a MOSFET structure.

Strain engineering

45

For example, owing to the impact of compressive strain, the curvature of HH and LH bands (effective mass) is changed resulting in a decrease of density of state and intraband scattering rate (where acoustic phonons are involved). The other outcome of strain is to split the HH and LH bands reducing the interband scattering (where optical phonons are involved). This scattering rate is noticeable when the split between the HH-LH bands is comparable to the energy of optical phonons. Overall, the channel mobility in MOSFETS is degraded in the presence of defects and interfacial states, surface roughness, dopant concentration, channel material, and strain in channel. There are two main parameters which have a strong influence on carrier mobility (μ) as shown in the following equation: μ¼

qh τ i m∗

(3.8)

where m* is the effective mass and hτi is the scattering time for the carriers. In order to increase the carrier mobility, the effective mass of the carriers has to be decreased and the scattering time has to be increased. The latter parameter is related to a different scattering mechanism, for example, lattice (or phonon) and ionized scattering in the semiconductors. By inducing strain in the crystal lattice, the band structure is modified in a way that the effective mass and carrier scattering are reduced. In order to observe a reasonable improvement of carrier mobility, a strain amount larger than 1 GPa has to be generated, which corresponds to the Si1 xGex layer with x > 0.25 [34,35]. In the early 1990s, many research centers focused on strain engineering in MOSFETs with a biaxially strained Si channel. The main idea behind this type of design for transistors was to enhance the carrier mobility for both p- and n-MOSFETs simultaneously (see Fig. 3.3A and B) [36,37]. Later, the wafer manufacturer introduced a series of wafers, for example, strained silicon and germanium on insulator (sSOI and GOI) for high mobility applications. Some works also manufactured SiGe on insulator (SGOI) wafers [38]. Such wafers can be processed through oxidation of SiGe layers at high temperatures (1000–1100°C). During this process, Si atoms are mainly oxidized and the Ge atoms are pushed away into the lower SiGe layer. As a result, a strain-free SiGe layer is built up with rich G D

G D

s-Si

S

s-Si1−yGey

SiO2 (Box) Si

s-Si

S

Use as n channel

SR Si1−xGex

Use as p or n channel

SiO2 (Box)

(A)

Use as p channel

Si

(B) Fig. 3.3 (A,B) Different designs of biaxial strained Si channel in MOSFETs [36].

46

CMOS Past, Present and Future

Ge content. The SiGe layer on SGOI wafers can be applied as a buffer layer for the growth of highly tensile strained Si or SiGe layers [39–41]. Such SGOI wafers can be used to process n- and p-MOSFETs for dual channel heterostructures on insulator (DHOI) or bulk Si substrate (DHOB). The s-Si layer can be etched and the remained SiGe can be used in DHOI or DHOB designs, the strained Si and SiGe layers function as the electron and hole channels, respectively (see Fig. 3.3B). Further analysis suggested that embedded stressor materials in the source/drain region can create uniaxial strain which is has superior properties over biaxial strain. Intel Company introduced the uniaxial strain concept using SiGe in S/D regions in 90-nm technology node in 2003. The main reasons for such a revolutionary step are listed below (see Fig. 3.4): 1. Uniaxial stress demonstrates a significantly larger hole mobility at both low and high applied electric fields compared to biaxial strain. This relates to the difference between the surface confinement for HL and HH bands. 2. Larger drive current can be achieved for uniaxial strained Si which is very useful for short channel transistors. The reason originates from the point that the improvement in electron or hole mobility in uniaxial strain is due to the reduction of effective mass and not from a decrease of scattering processes which holds for the biaxial strain case. 3. The uniaxial stress demonstrates nearly a half magnitude smaller threshold voltage shift (ΔVT) in n-channel MOSFETs. This is a crucial point for transistor performance since this shift is usually tuned by the doping concentration in the channel region [1]. Eqs. (3.9), (3.10) show the correlation of threshold voltage when strain σ is induced as follows:

qΔVT ðσ Þ ¼ ΔEc ðσ Þ + ðm

N V ð 0Þ 1Þ ΔEg ðσ Þ + kT ln NV ðσ Þ



Biaxial stress

(3.9)

  NV ð0Þ 1Þ ΔEg ðσ Þ + kT ln Uniaxial stress NV ðσ Þ

Fig. 3.4 Hole mobility in pMOSFETs versus vertical field with biaxial and uniaxial strained Si channels [1].

(3.10)

140 Universal mobility

Biaxial

Uniaxial SiGe S/D

120 Mobility (cm2/ (V s)

qΔVT ðσ Þ ¼ ðm



226 MPa longitudinal Uniaxial compression wafer bending

100 80 60 40 0.0

Biaxial data Uniaxial SiGe S/D Uniaxial wafer bending

2.0

4.0 6.0 8.0 Effective field / (MV/cm)

Unstressed

1.0

1.2

Strain engineering

47

where ΔEc stands for conduction band shift, ΔEg for bandgap narrowing, and NV is density of states in the valence band. Eqs. (3.9), (3.10) reveal two reasons for the threshold voltage shift performance: (I) Biaxial tensile stress creates a larger ΔEc and larger ΔEg in the Si channel compared to uniaxial strain. Thus, in biaxial stress, the maximum energy band is the LH band mean, whereas in uniaxial stress it is the HH energy band. (II) The ΔEc term in Eq. (3.10) is negligible since in uniaxial strain the transistor gate region is only strained.

Therefore, these arguments show that uniaxial stress has remarkable advantages for logic technologies compared to biaxial stress. Uniaxial strain has a central role for improving the carrier transport in MOSFETs in more Moore technology roadmap. The semiconductor industry has integrated a variety of methods to increase the channel mobility: implementation of SiGe layers as a stressor material in S/D regions and SiN stress liners on the transistor and hybrid substrates. The hybrid substrate refers to wafers, for example, with (110) orientation [2,3]. There are also other possibilities to obtain high mobility such as integration of new channel materials, for example, Ge, GeSnSi, and III-V on Si (as well as 2D crystals). Although these materials have outstanding electrical properties, a great deal of issues such as integration with high-k materials and layer quality have to be improved. More discussions have been provided in Chapter 5. In order to describe the carrier transport properties in the channel MOSFETs, for example, in hybrid substrates, the variation of mobility can be expressed in terms of piezoresistance coefficients as follows: Δμ=μ  |π == σ == + π ? σ ? |

(3.11)

where π // and π ? denote the piezoresistance coefficients in longitudinal and transverse directions and σ // and σ ? are the longitudinal and transverse stresses. Furthermore, the piezoresistance coefficients can be defined by fundamental cubic piezoresistance coefficients π 11, π 12, and π 44 or by their combinations for a certain orientation [42]. For compressive strain, the piezoresistance coefficient for holes has the highest value along h110i for both (001) and (110) wafers. Therefore, the h110i channel direction has been commonly employed in the Si industry for pMOS [42,43].

3.4

Methods to induce strain in the CMOS structure

3.4.1 Epitaxy of stressor materials In order to induce high uniaxial strain in the channel region, embedded SiGe (compressive strain for pMOS) [1,2,4–7] Si:C (tensile strain for nMOS) in S/D areas [8–10] is widely employed in the transistors. In pMOSFETs, from 90- to 22-nm technology node, the Ge content in SiGe has been constantly increased from 17% to 40% [1,2,4–7]. The induced strain was further increased when the profile of recess in S/D was carefully designed from the initial round shape to sigma (Σ) shape. In this way, the

48

CMOS Past, Present and Future

SiGe layers is located deeper inside the channel region [44,45] and can induce strain more effectively. A simulation of strain distribution from S/D regions with a Σ-shape recess and filled by an SiGe layer is shown in Fig. 3.5. In FinFETs, the SiGe are grown on Si fins to elevate S/D regions. In this case, the shape of the Si fin could be designed from a round shape to a triangular one in order to further increase the strain amount. SiGe layers are selectively grown commonly at 650–700°C by the reduced pressure chemical vapor deposition (RPCVD) technique at 10–40 mtorr using SiH2Cl2, GeH4 as Ge, and Si precursor, respectively. During the growth, HCl gas is introduced to etch the formed nuclei on the surface of SiO2 and to ensure the selectivity of the deposition. The selectively grown SiGe layers may show several problems such as microloading and a pattern dependency effect [46–52]. These problems can be significantly decreased by optimizing the epitaxy parameters [46–48] but pattern dependency is difficult to eliminate entirely. The reason behind the pattern dependency phenomenon is the variation of size and density of the transistor (or exposed Si coverage) in a chip or over the wafer. As a result, the consumption of reactant gas molecules becomes nonuniform and affects the SiGe growth. As an example, the profile of SiGe (or strain) in chips at the center of the wafer differs from those at the edge of the wafer when more oxide area exists at the edge of the wafer. The pattern dependency can also be seen among the transistor arrays within a chip when the exposed Si coverage is different [7,53–56]. Fig. 3.6A and B illustrates the kinetics of gas molecules during the epitaxy of SiGe layers for planar pMOSFETS and FinFETs. The gas molecules of precursors are transported along the CVD reactor on a path at a certain distance from the wafer depending on the total pressure in the reactor. A gas boundary is established over the wafer when the dangling bonds in the exposed Si areas exert an attractive force on the molecules toward themselves. The SiGe profile is dependent on the gas consumption when the gas molecules from vertical, and lateral direction flow towards the substrate as well as, when the mobile species (from SiH2Cl2, GeH4, and HCl precursors) on oxide surface outside and among the transistor openings move towards the exposed Si areas of the substrate. Therefore, the growth rate in total (Rtot) is a sum of contributions of gas fluxes from different directions as shown in Fig. 3.6A [7,53–56]: SS SC V LG SS SC LG Rtot ¼ RV Si + RSi + RSi + RSi + RGe + RGe + RGe + RGe

RV E

(3.12) RLG RSS RSC E E E where different components are marked in the figure. If the layout changes inside a chip (or between two chips), then the RLG, RSS, and RSC components are not the same and the pattern dependency problem emerges. Eq. (3.12) can be modified for the deposition of SiGe on Si fins in 3D transistors by adding a new component, RCO. This component is generated for the diffusion of molecules on the surface of Si fins. Then Eq. (3.12) is rewritten as [7] LG SC CO SS V LG SO CO SS RTot ¼ RV Si + RSi + RSi + RSi + RSi + RGe + RGe + RGe + RGe + RGe

RV HCl

RLG HCl

RSO HCl

RCO HCl

RSS HCl

(3.13)

Strain engineering

49

Fig. 3.5 (A) SEM micrograph from a Σ-shape recess with its crystal planes and simulated strain of p-MOSFETs when S/D regions contain a Σ-shape recess and are filled with an SiGe layer. In simulation work, recess profiles were calculated when the tip depth is a constant 5 nm but the distances between the channel region and the upper edge of the S/D recess are changed from (B) 20 nm to (C) 10 nm and (D) 0 nm. Further simulation work was performed when the distance between the channel region and the upper edge of the S/D recess is a constant 5 nm; meanwhile the tip depth is changed from (E) 0 nm to (D) 5 nm, and (F) 10 nm [45].

50

CMOS Past, Present and Future

Gas flow Rv

R SS

Si substrate

R LG

R SC

Chip length

(A) Gas flow Rv

R LG

R SC R CO

R SS SiO2 Si substrate

Si

R SC Si

Si

Chip length

(B) Fig. 3.6 Drawings of gas flow over a chip containing (A) S/D oxide openings and (B) Si fins. The dashed circles show volumes where the gas molecules around an array of oxide openings in a chip are attracted.

The RCO component creates a special situation for growth on 3D transistors when the molecules can diffuse among Si fins, resulting in more uniform growth. More detailed information about the models is provided in Refs. [7,53–56]. It is crucial to emphasize that both Eqs. (3.12), (3.13) are applicable when the epitaxy of SiGe is defect-free; otherwise, the diffusion of defects may influence on the movement of the incoming molecules during the growth. The other important thing is that the Si surface prior to epitaxy has to be free from any oxide and carbon residuals. The presence of defects or unclean Si surface strain of SiGe may lead to strain relaxations in the epi-layers. As an example, Fig. 3.7A–F illustrates the significant role of prebaking of Si fins at annealing temperatures from 825 to 750°C for Si surface cleaning. Fig. 3.7B micrograph demonstrates that annealing at 825°C has resulted in damage of the Si fin and a nonuniform strain distribution over the fins can be obtained (according to the

Strain engineering

51

(B)

(A)

(C)

100nm

100nm (E)

(D)

100nm

100nm (F)

100nm

100nm

Fig. 3.7 SEM micrographs of the Si fins with selectively grown SiGe layers when in situ annealing was as follows: (A) Sifin with no annealing, (B) at 825°C, (C) at 800°C, (D) at 780°C, (E) at 760°C, and (F) at 740°C [7].

simulation data not shown here). On the other hand, 740°C annealing is too low a temperature treatment to remove oxide residuals and the growth becomes three dimensional. The strain of SiGe layers is partially relaxed in these fins.

3.4.2 Stress memorization technique (SMT) This method is based on deposition of a highly tensile-strained silicon nitride (SiN) followed by a thermal annealing step (typically >1000°C). In the conventional SMT process, the SiN cap-layer is deposited on the entire Si wafer and it remains on the nMOS region meanwhile is selectively removed from the pMOS region. Strain is mainly generated and memorized during the annealing step for dopant activation in S/D regions. Wet etching is applied after the SMT process to remove the SiN layer before silicide formation. There are a number of theories to explain the mechanisms of SMT [17,18]. The most common theory explains that stress memorization is initiated from compressive stress which is induced vertically by the n-type polycrystalline Si gate under the SiN cap-layer. The volume of polycrystalline material expands during the annealing step

52

CMOS Past, Present and Future

Fig. 3.8 Schematic of a transistor with stress or material showing the stress directions.

Stressor liner

Poly gate

Source

Drain

Tensile strain in channel

and creates a tensile strain along the longitudinal direction in the nMOS channel, as demonstrated in Fig. 3.8. The results of SMT can be affected by several matters, for example, poly amorphorization during implantation, thickness, and the quality of SiN liner, as well as degradation of stress before and after high-temperature annealing [17–22]. This indicates that many issues have to be considered for integration of SMT in order that the process works properly. It is beneficial in many cases to reduce the process temperature in SMT. A modification of standard SMT is done when the cap-layer is deposited at low temperatures and the annealing step will move after the amorphizing implantation [23]. The temperature interval is 600–900°C. In this case, the stress can be memorized in the S/D regions due to volume expansion through amorphization. The effect from the two SMT techniques were shown to be additive. By combining the mentioned SMT techniques, the drive current in nMOS could be improved by >27% [23].

3.4.3 DSL The technique is based on the deposition of SiN liners on the top of transistors in order to induce strain in the channel region. The stress can be enhanced by increasing the SiN thickness and reducing the height of the polysilicon gate or reducing the sidewall spacer thickness [11]. DSL was integrated for the first time in the 90-nm technology node CMOS [12,13]. This technique has been developed that the SiN liners can induce tensile for nMOS or compressive stress for pMOS at the same time. This offers a large advantage compared to other strain engineering techniques. In process flow, DSL is placed after salicidation and it begins with deposition of a highly stressed tensile SiN layer on the whole wafer. This layer is patterned and etched prior to deposition of the second SiN layer which is highly stressed compressive. Finally, the second SiN layer is patterned and removed from the nMOS region. For some applications, only a single SiN is desired. In this case, selective implantation can be applied to release the stress on any particular region [14].

Strain engineering

53

In the DSL process, the SiN layers are removed by plasma reactive ion etching (RIE). The process parameters in RIE have to be optimized in order to avoid any damage to silicide and degrading the contact resistance. It is worth mentioning that RIE optimization is a delicate matter since it depends on the height of the gate and embedded SiGe in S/D as well as the spacer architecture. Fig. 3.9A and B illustrates a successful optimized DSL in 65 nm CMOS [15]. Recent reports have shown that a diamond-like carbon film can be used to obtain tremendous compressive stress (> 6 GPa) on MOS transistors [16]. This discovery inaugurates new stressor material for integration in CMOS technology in the near future. The stress induced by DSL can be further enhanced by applying a complementary method, the so-called stress proximity technique (SPT). The main target is to maximize the stress when the stress liners are located closer to the channel by etching the sidewall spacers. Fig. 3.10 illustrates cross-sectional SEM pictures of MOSFETs

Tensile liner

(A)

Compressive liner

nMOS

(B)

pMOS

Fig. 3.9 Cross-sectional images of (A) nMOS and (B) pMOS with stress or liners [15].

Fig. 3.10 Cross-sectional images of a 32-nm MOSFET (A) with and (B) without spacers under stress liners [12].

54

CMOS Past, Present and Future

with and without SPT. In the gate process, SiN spacers are used as a shield in S/D implantation or salicidation. The SiN spacers are removed prior to the SPT process. The stress is further maximized depending on the stress liners and spacer width. As an example, SPT for 45-nm CMOS illustrated 20% improvement in pMOS; meanwhile, the same process could improve by only 3% for nMOS [17]. The most critical process of SPT is the RIE used for spacer removal. Compared with DSL, although both involve a SiN removal process, the chemistry and condition used for RIE are very different. This is because the DSL RIE requires the removal of the entire tensile stress liner from the pMOS region only, while the SPT RIE requires the removal of spacers along the sidewall of gates for both nMOS and pMOS. A carefully tuned RIE recipe is usually needed to minimize the damage to silicide.

3.5

Embedded Si12 yCy(eSi12 yCy) for nMOS

As opposed to the embedded SiGe layer, which has been integrated from the beginning stage in nanoscaled pMOS, implementation of the Si1 yCy layer to the nMOS process was discovered to be difficult because of the sensitivity of Si1 yCy layers to strain relaxation [8]. Carbon atoms can be implemented in the Si matrix either by implantation or epitaxy. Implantation of carbon atoms in the S/D region, followed by a solid-phase epitaxy (SPE), has demonstrated an improvement of 6% for drive current with 1.65% substitutional carbon in 65-nm baseline nMOS [9]. Although the SPE approach is more cost-effective, it needs high energy and heavy doses which can create defects at the boundary between Si1 yCy in the S/D and Si channel regions. Epitaxially grown eSi1 yCy with 1.85% substitutional carbon in the S/D in a 45-nm baseline nMOS (see Fig. 3.11) has shown an improvement of 9% in drive current which is a better technique to generate stress than others, for example, SMT or tensile liner (TL), as shown in Fig. 3.12 [10]. Major issues with epitaxial growth of embedded Si:C are a relatively low wafer throughput of 3 wafers/h, compared to the SiGe case of >6 wafers/h, and limited low substitutional carbon concentration of 2% due to generation of a high defect amount in the layers.

Silicide

TL Lg

SiC SiC

Fig. 3.11 Cross-sectional TEM image of nMOS with eSi1 yCy in the 45-nm baseline process [10].

Strain engineering

55

1.E−05

Ioff (A/µm)

Cited from Ref.[40]

1.E−06

1.E−07

1.E−08 700

800

Si ctrl, NL Si ctrl, SMT + TL eSiC + TL

9%

21%

900

1000 Ion (µA/µm)

1100

1200

Fig. 3.12 Drive current (Ion) vs off current (Ioff) for a 45-nm nMOS w/wo e Si1 control process with SMT, neutral liner (NL), and tensile liner (TL) [10].

1300

yCy

using a

3.5.1 Strain and critical thickness All kinds of strained alloys possess a stored mechanical energy which may release when their thickness reaches a critical value. This critical thickness depends on the lattice mismatch between two materials (usually a thin film is grown on a substrate), and in case of epitaxial growth the layer thickness of the strained material should be kept below critical thickness in order to avoid any strain relaxation. As a result of this strain relaxation, misfit dislocations (extended defects) are formed which degrade the electrical (and optical) properties of the material. Therefore, there is a large interest to propose a model to predict the critical thickness for different alloys. Historically, the first model to calculate the critical thickness for composites of Si with Ge was presented by Matthews-Blakeslee (MB) >40 years ago [57]. This model was initially applied to estimate the critical thickness of strained SiGe layers grown on the entire Si wafer. The MB model, which is also known as the equilibrium model, takes into account a balance between two revival forces during epitaxial growth: Fa is the force employed by the misfit strain, and FT is the tension force across the dislocation line (see Fig. 3.13). These forces can be formulated for a semiconductor

c

b a

FT

a

b

c

Fa

FT

Fig. 3.13 Formation of dislocations under the acting strain forces and when the multilayers are (a) coherent, (b) critical, and (c) incoherent.

56

CMOS Past, Present and Future

in terms of its shear modulus (G), Poisson ratio (ν), burger vector (b), and induced strain (ε) as follows: 2Gð1 + νÞ bhε cos λ ð1 νÞ

Fa ¼

(3.14)

where λ stands for the angle between the slip direction and the perpendicular direction to intersection of the slip plane and the layer interface. With a simple mathematical approach, FT is written as FT ¼

Gb2
1 4π ð1 νÞ

   h ν cos 2 α ln + 1 b

(3.15)

where α stands for the angle between the dislocation line and its Burgers vector. When the strain increases to a maximum level, three situations may occur as shown in Fig. 3.13. Practically, the maximum strain (εmax) is obtained when εmax ¼ 1/f. Three cases may occur as shown in sections A, B, and C in Fig. 3.13: (1) Fε,max < 2FT then threading dislocations has the geometry drawn in (a) and the layer interface is coherent and strain relaxation is retarded, (2) Fε,max ¼ 2FT, the formation of threading dislocations is at an initial or critical stage as shown in (b), and (3) Fε,max > 2FT, dislocations can form with geometry of (c). This movement of dislocations terminates the coherence of the layer interface. The critical thickness is obtained for case 2 and can be formulated in Eq. (3.16) as follows [57]: hc ¼

  bð1 ν cos 2 αÞ hc ln + 1 2πf ð1 + νÞcos λ b

(3.16)

After a few years, when the epitaxial SiGe layers could be grown with a wide range of Ge content, a large discrepancy between the calculated hc values and experimental data was observed. The reason for this large discrepancy was due to the simplicity of the MB theory which considers only a balance between two acting forces to form misfit dislocations and the other process, for example, the propagation, nucleation, and interaction of misfit dislocations have been ignored. Therefore, the critical thickness values for Si1 xGex layers were significantly deviated from the experimental results. Later an empirical model was introduced by People and Bean et al. and a new equation was presented [58]: pffiffiffi   ð 1 ν Þ 2b2 hc hc ¼ ln b ð1 + νÞ32πaf 2

(3.17)

The difference between Eqs. (3.16), (3.17) originates from how the assumptions of models have been made. In Eq. (3.17), the initial dislocations appear in a stochastic fashion. This is an effort to involve more the relaxation kinetics when the dislocation

Strain engineering

57

formation overcomes a certain energy barrier differently from the equilibrium model where the initial dislocations emerge in a regular rectangular array. A more accurate model was introduced by Dodson and Tsao (DT) when the concept of equilibrium between the mentioned forces in MB was substituted by excess stress σ ex which roots from the difference between these forces [59,60]. Therefore, the strain energy may release when σ ex is set to zero. The MB equation is then revised into an expression for σ ex in a nonequilibrium model as follows: σ ex ð1 ν Þ ¼ 2ε ð1 + νÞ μ

b 1 ν cos 2 θ 4h ln 2πh 1 ν b

(3.18)

where ε is the elastic strain and μ is the shear modulus. Fig. 3.14 demonstrates the experimental data and the calculated thickness curves for Si1 xGex layers. The region which is enclosed between the calculated MB and DT critical thickness curves is called meta-stable. Therefore, the meta-stable region for Si1 xGex is an outcome of both equilibrium and nonequilibrium theories to deal with stress in epi-layers. Fig. 3.14 illustrates a good agreement between the critical thickness of an actual layer thickness and Ge content. For many device applications, the strained layers are deposited with a layer thickness in the metastable region. Another parameter which should not be ignored for hc curves is growth temperature. In general, the stress relaxation is more favorable for high growth temperatures when the barrier for energy release becomes low. This indicates that the metastable region is small for Si1 xGex growth and large for high and low growth temperatures, respectively (see Fig. 3.15).

Fig. 3.14 The critical thickness of SiGe material vs Ge content calculated from DT [59,60] and MB models [57]. The () and (Δ) symbols are experimental data for the grown SiGe layers at different growth temperatures [59,60].

104

Film thickness (h/b)

550°C 750°C

103

102

DT

DT MB

101 0

0.01 0.02 Lattice mismatch

0.03

58

100 Critical thickness of GeSi (nm)

Fig. 3.15 Critical thickness of SiGe layers vs Ge content and growth temperatures [61].

CMOS Past, Present and Future

Partially relaxed layers

T300 T400 T500 T600 T700

10

Metastable MB

1

0.2

0.4

0.6 Ge content, x

0.8

1.0

3.5.2 Critical thickness of SiGe alloys on patterned substrates So far, the critical thickness discussions of SiGe/Si were focused on the growth on the entire Si wafer; however, the situation is quite different on the patterned substrates when the SiGe layers are grown selectively on Si inside an isolator (oxide or nitride) opening [61]. The strain becomes nonuniformly distributed in SiGe inside oxide openings. In the center region of oxide openings, the layer is totally strained but in the areas near to the oxide walls it is partially relaxed. The strain distribution provides the possibility that the dislocations are depleted in the relaxed area and are not able to propagate in the whole layer. As a result, strained SiGe layers can be selectively grown with thickness above the critical thickness for bulk material (see Fig. 3.16).

Fig. 3.16 The experimental data showing thickness of strained (▲) and partially strain relaxed (×) SiGe vs Ge content [61].

1000

Thickness (nm)

x x

x x

100

10 10

15

20 25 Ge content (%)

30

35

Strain engineering

59

A similar phenomena of critical thickness extension occurs for the growth of SiGe material on the nanoscale areas [62]. For example, in FinFETs, SiGe layers are selectively deposited on the Si fins to raise the source/drain regions. In such structures, relaxation of SiGe layers occurs far beyond the reported critical thickness for bulk material (see Fig. 3.17). The shape of Si fin has an important role for the strain distribution due to the fact that the dislocations glide in the {111} planes when minimum energy is required for propagation. In the advanced process, such planes are avoided in order to counteract the dislocation movement. Therefore, the maximum created strain varies in terms of the fin thickness and not directly because of the thickness of SiGe layers.

3.5.3 Strain measurements The strain distribution in nanoscaled transistors can be studied by applying the nanobeam diffraction (NBD) technique in a high-resolution transmission electron microscope (HRTEM). In response to strain, the lattice constant is distorted and the diffraction pattern may change depending on the strain amount. The analysis of diffraction pattern is performed by using the True Crystal Strain package program. In NBD analysis, the interplanar distance of (220) planes is typically obtained and the stress can be estimated when the measured data are compared to the calculated ones. As an example, Fig. 3.18 shows a cross section and diffraction patterns obtained from different areas of a 22-nm planar transistor with an ALD W metal gate which was B-doped by the B2H6 precursor or grown by SiH4 precursor. The NBD analysis was performed by an e-beam on two selected areas of the transistor. The diffraction pattern from the metal gate area has a weak intensity and shows Fig. 3.17 The critical thickness of SiGe layers grown on Si fins with different sizes [62].

105

Critical thickness (nm)

104

103

550°C

102

Equilibrium 27 nm Si

750°C

101

100

625°C on 27 nm Si

625°C on 12 nm Si

Equilibrium 12 nm Si

Matthews and blakeslee

0

20 40 Ge content (%)

60

60

CMOS Past, Present and Future

ALD B2H6W

ALD SiH4W

Fig. 3.18 NBD micrographs from a metal gate, channel, and the body regions of a 22-nm planar transistor [23].

diffused airy rings with a few spots, which is an indication of poor polycrystalline or probably an amorphous phase. The strain in the channel region was calculated from the diffraction patterns for these samples. The B-doped ALD W showed highest strain and it was 0.5 GPa. The strain was obtained from the relationship between the stress amount (ε) and strain (σ) in ε ¼ σ/E, where E is Young’s Modulus for Si material [23]. Although the NBD technique seems to be a very impressive tool for nanoscaled measurement of strain, the results are dependent on how carefully the sample preparation has been performed. This is due to the fact that the strain partially relaxes when the focus ion beam (FIB) tool is used to make the sample thin enough for HRTEM analysis. Another technique to measure strain is the focused beam X-ray diffraction (XRD). Owing to a limited X-ray spot size (1–10 mm), the strain measurements provide a mean value over a series of transistor arrays and not individual transistor compared to HRTEM analysis. The XRD measurement is based on scanning of the incident beam (ω angle) and the detector moves on the path to collect the diffracted beam (angle 2θ) in a scan type, the so-called ω-2θ rocking curve (RC). The diffracted beam is established when the Bragg condition (2d sin θ ¼ λ, where d is the interplanar distance and λ is the wavelength of X-ray radiation) is satisfied. In ω-2θ RCs, two main peaks, substrate and layer peaks are appeared when the Bragg’s condition with certain ω and 2θ values is fulfilled [25,26]. The strain is determined from the split of these peaks. A more precise strain measurement can be performed by using a high-resolution reciprocal lattice map (HRRLM) when the misfit in an in-plane and perpendicular direction (f// and f?, respectively) can be measured around a reflection (or reciprocal point) in reciprocal space. The choice of reflection is an important point which has to be taken into account since depending on incident angle the penetration of X-ray beam is changed and it makes the acquisition from different depth. For example for Si,

Strain engineering

61

reflection (113) with an incident angle of 2.8 degree is more sensitive to the defects located closer to the surface compared to (224) and (115) reflection with incident angles of 8.7 and 31.7 degrees. The angles of substrate (ωsub and θsub) and layer (ωlay and θlay) peaks are obtained from HRRLMs and the misfit parameters are calculated from the following equations [25,26]. f? ¼

sin θsub cos ðωsub
sin θlay cos ωlay

θsub Þ  θlay

f== ¼

sin θsub sin ðωsub
sin θlay sin ωlay

θsub Þ  θlay

1

(3.19)

1

(3.20)

HRRLMs is a characterization tool which can be used to determine the substitutional boron concentration in SiGe as well as the strain relaxation during different process steps, for example, thermal treatment for dopant activation and silicide formation. In general, a successful process flow must preserve the strain in the transistor channel with negligible strain relaxations [25–27]. As an example, the analysis shows that the formation of silicides in the S/D regions results in strain relaxation in SiGe layers [63,64]. This is due to the fact that during the silicide formation a substantial amount of point defects is created when the Si atoms are consumed. Most of the Ge atoms are pushed out to the lower SiGe layer, forming a layer with rich Ge content. As a result, the remaining SiGe underneath the formed silicide layer is partially relaxed. A solution to this strain relaxation problem is to deposit a sacrificial layer which can be used for the silicide formation [64]. An experimental work which applies HRRLM for strain measurements is presented in Fig. 3.18A–C. The figure shows three HRRLMs around (113) reflection from arrays of 22-nm planar transistors with (a) intrinsic Si0.65Ge0.35, (b) B-doped Si0.65Ge0.35, and (c) B-doped Si0.65Ge0.35/NiSiGe in S/D regions [65]. The silicide layer has been formed on a sacrificial Si0.80Ge0.20 cap layer by using RTA treatment at 500°C for 30 s in an N2 ambient. In Fig. 3.18A and B, the SiGe peak is aligned to Si one along the K? direction, indicating a minor strain relaxation in the SiGe layer. In Fig. 3.19B, the position of the B-doped SiGe peak has shifted toward the Si peak due to strain compensation in the presence of B atoms in the SiGe matrix. The boron concentration is estimated to be 2  1020 cm 3 by applying the contraction coefficient of boron in Si [(6.3  0.1)  10 24 cm3/atom] and the shift of strain amount. In Fig. 3.19C, the position of the SiGe peak is constant as in Fig. 3.18B, showing that the strain amount in SiGe is not changed during the Ni silicide formation [65]. Although a conventional high-resolution X-ray apparatus has been mostly used for HRRLM in nanoscaled transistors, they cannot measure strain in very small SiGe crystals in FinFETs because of the weak response signals. Therefore, the HRRLMs from FinFET structures have to be measured by a single X-ray beam in a synchrotron facility as shown in Fig. 3.19 [56]. The high-intensity beam provides the possibility to

62

CMOS Past, Present and Future

Fig. 3.19 HRRLMs from a 22-nm MOSFET with Si0.65Ge0.35 in S/D of areas when (A) the layer is an intrinsic layer and (B) a B-doped layer (C) but the same as in the previous sample with an Si0.80Ge0.20 sacrificial cap layer which was consumed in Ni silicide formation [65].

obtain decent signal levels to determine the misfit parameters in tiny SiGe crystals. In Fig. 3.20, the SiGe peak is aligned with the Si peak along K? showing a negligible amount of strain relaxation.

3.5.4 Raman spectroscopy for strain measurement The Raman technique has been used widely as a fast and nondestructive method to measure strain in epi-layers with a sub-μ resolution. The resolution may extend to sub-100 nm when near-field approaches are applied [66]. The principle of Raman is established on inelastic scattering of light (wave number in cm 1) as a result of lattice vibrations and electronic excitations. A frequency shift of scattered light is observed in the presence of strain and its quantity is interpreted in the layer. In the analysis of the SiGe/Si structure, the three peak positions, SidSi, SidGe, and GedGe phonon modes, are of interest as illustrated in Fig. 3.21 [67]. In the spectra, the relative energies and intensities of the SidSi, SidGe, and GedGe vibrations are dependent on the relative number and distortion of corresponding bonds in the alloy due to composition and strain, respectively [68]. This dependency of phonon frequency in terms of strain amount in SiGe layers, ε, is obtained from the following equations: ωSiSi ¼ 520:2

62x

ωSiGe ¼ 400:5 + 14:2x ωGeGe ¼ 282:5 + 16x

815ε 575ε 385ε

(3.21) (3.22) (3.23)

Strain engineering

63

Strained

Relaxed

Fig. 3.20 HRRLM at ( 115) reflection from a chip of 14 nm FinFET with SiGe material grown selectively on S/D areas [56].

Raman intensity (a.u.)

1 — 0.22 Ge, r = 25% 2 — 0.36 Ge, r = 16% 3 — 0.46 Ge, r = 79%

Si–Sisub (520)

Si–Ge (~400)

Ge–Ge (~300)

Si–Silayer (~500)

3 2

1

250

300

350

400

450

500

550

Wavenumbers (cm−1)

Fig. 3.21 Raman spectra for strained SiGe/Si samples with different Ge contents.

64

CMOS Past, Present and Future

Although it is necessary to develop more Raman spectroscopy for the lateral resolution to study strain in the channel region of MOSFETs, the technique can be used on the test structures with a typical range of 100 nm. Raman measurements require modeling to analyze the data, since the signal does not lead to the entire tensor information associated with the strain distribution.

References [1] S.E. Thompson, G. Sun, K. Wu, J. Lim, T. Nishida, Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs, in: IEDM Tech. Dig., 2004, pp. 221–224. [2] T. Ghani, S.E. Thompson, M. Bohr, et al., in: A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors, IEDM Tech. Dig., San Francisco, CA, 2003 pp. 11.6.1–11.6.3. [3] S. Pidin, T. Mori, K. Inoue, S. Fukuta, N. Itoh, E. Mutoh, et al., in: A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films, IEDM Tech. Dig., Tokyo, Japan, 2004, pp. 213–216. [4] C. Auth, C. Allen, A. Blattner, D. Bergstrom, M. Brazier, M. Bost, M. Buehler, V. Chikarmane, T. Ghani, T. Glassman, in: A 22 nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors, 2012 IEEE Symposium on VLSI Technology, 2012, pp. 131–132. [5] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, et al., in: A 45 nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging, IEEE International Electron Devices Meeting, 2007 (IEDM 2007), 2007, pp. 247–250. [6] P. Packan, S. Akbar, M. Armstrong, et al., in: High performance 32 nm logic technology featuring 2nd generation high-k+ metal gate transistors, IEEE International Electron Devices Meeting, 2009 (IEDM 2009), 2009, pp. 1–4. [7] G. Wang, A. Abedin, M. Moeen, M. Kolahdouz, J. Luo, Y. Guo, T. Chen, H. Yin, et al., Integration of highly-strained SiGe materials in 14 nm and beyond nodes FinFET technology, Solid State Electron. 103 (2015) 222–228. [8] B. Yang, Z. Ren, R. Takalkar, et al., Recent progress and challenges in enabling embedded Si:C technology, ECS Meet. 16 (2008) 317–323. [9] Y. Liu, O. Gluschenkov, J. Li et al., Strained Si channel MOSFETs with embedded silicon carbon formed by solid phase epitaxy, in: Symp. VLSI Tech. Dig., 2007, pp. 44–45. [10] B. Yang, R.Takalkar, Z. Ren et al., High-performance nMOS with in situ phosphorusdoped embedded Si:C (ISPD eSi:C) source-drain stressor, in: IEDM Tech. Dig., 2008, pp. 51–54. [11] S. Pidin, T. Mori, R. Nakamura et al., MOSFET current drive optimization using silicon nitride capping layer for 65-nm technology node, in: Symp. VLSI Tech. Dig., 2004, pp. 54–55. [12] Y. Bin, C. Ming, Advanced strain engineering for state-of-the-art nanoscale CMOS technology, Sci. China 54 (2011) 946–958, https://doi.org/10.1007/s11432-011-4224-9. [13] H. Yang, R. Malik, S. Narasimha et al., Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing, in: IEDM Tech. Dig., 2004, pp. 1075–1077. [14] W. Lee, A. Waite, H. Nii et al., High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-k BEOL, in: IEDM Tech. Dig., 2005, pp. 61–64.

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[15] K. Tan,M. Zhu, W. Fang et al., A new liner stressor with very high intrinsic stress (>6 GPa) and low permittivity comprising diamond-like carbon (DLC) for strained P-channel transistors, in: IEDM Tech. Dig., 2007, pp. 127–130. [16] X. Chen, W. Gao, T. Dyer et al., Stress proximity technique for performance improvement with dual stress liner at 45 nm technology and beyond, in: Symp. VLSI Tech. Dig., 2006, pp. 60–61. [17] C. Ortolland, Y. Okuno, P. Verheyen, et al., Stress memorization technique j fundamental understanding and low-cost integration for advanced CMOS technology using a nonselective process, IEEE Trans. Electron Devices 56 (2009) 1690–1697. [18] C. Chen, T. Lee, T. Hou et al., Stress memorization technique (SMT) by selectively strained nitirde capping for sub-65 nm high-performance strained-Si device application, in: Symp. VLSI Tech. Dig., 2004, pp. 56–57. [19] A. Eiho, T. Samuki, E. Morifuji et al., Management of power and performance with stress memorization technique for 45 nm CMOS, in: Symp. VLSI Tech. Dig., 2007, pp. 218–219. [20] C. Ortolland, P. Morin, C. Chaton et al., Stress memorization technique (SMT) optimization for 45 nm CMOS, in: Symp. VLSI Tech. Dig., 2006, pp. 78–79. [21] A. Wei, M. Wiatr, A. Gehring et al., Multiple stress memorization in advanced SOI CMOS technologies, in: Symp. VLSI Tech. Dig., 2007, pp. 216–217. [22] S. Ito, H. Namba, K. Yamaguchi et al., Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design, in: IEDM Tech. Dig., 2000, pp. 247–250. [23] G. Wang, J. Luo, J. Liu, T. Yang, Y. Xu, J. Li, H. Yin, J. Yan, H. Zhu, C. Zhao, et al., pMOSFETs featuring ALD W filling metal using SiH4 and B2H6 precursors in 22 nm node CMOS technology, Nanoscale Res. Lett. 12 (2017) 306. [24] H.H. Radamson, J. Ha˚llstedt, Application of high-resolution X-ray diffraction for detecting defects in SiGe(C) materials, J. Phys. Condens. Matter 17 (2005) S231517. [25] G.V. Hansson, H.H. Radamsson, W.-X. Ni, Strain and relaxation in Si-MBE structures studied by reciprocal space mapping using high resolution X-ray diffraction, J. Mater. Sci. Mater. Electron. 6 (1995) 292. [26] P.F. Fewster, X-Ray Scattering From Semiconductors, Imperial College Press, London, 2000. ISBN: 1-86094-360-8. [27] S.P. Nikanorov, B.K. Kardashev, Elasticity and Dislocation Inelasicity of Crystals, “Nauka” Publ. House, Moscow, 1985. [28] P. Moontragoon, Z. Ikoni’c, P. Harrison, Band structure calculations of Si–Ge–Sn alloys: achieving direct band gap materials, Semicond. Sci. Technol. 22 (2007) 742–748. Available from: https://doi.org/10.1088/0268-1242/22/7/012. [29] S.P. Nikanorov, Y.A. Burenkov, A.V. Stepanov, Elastic properties of silicon, Sov. Phys. Solid State 13 (1971) 2516–2519. [30] H.J. McSkimin, P. Andreatch, Elastic moduli of diamond as a function of pressure and temperature, J. Appl. Phys. 43 (1972) 2944–2948. [31] J.J. Wortman, R.A. Evans, Young’s modulus, shear modulus and Poisson’s ratio in silicon and germanium, J. Appl. Phys. 36 (1965) 153–156. [32] H.-J. Herzog, X-ray analysis of strained layer configurations, Solid State Phenom. 32 (1993) 523–534. [33] P. Aella, C. Cook, J. Tolle, S. Zollner, A.V.G. Chizmeshya, J. Kouvetakis, Structural and optical properties of SnxSiyGe1 x y alloys, Appl. Phys. Lett. 84 (2004) 888. [34] C.W. Leitz, et al., Hole mobility enhancements and alloy scattering-limited mobility in tensile strained Si/SiGe surface channel metal-oxide-semiconductor field-effect transistors, J. Appl. Phys. 92 (2002) 3745–3751.

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[35] M. Chu, Y. Sun, U. Aghoram, S.E. Thompson, Strain: a solution for higher carrier mobility in nanoscale MOSFETs, Annu. Rev. Mater. Res. 39 (2009) 203–229. [36] A. Chaudry, G. Joshi, J.N. Roy, D.N. Singh, Review of current strained silicon nanoscaled MOSFET structures, Acta Tech. Napocensis Electron. Telecommun. 51 (2010) 15–22. [37] S.H. Olsen, A.G. O’Neill, L.S. Driscoll, K.S.K. Kwa, S. Chattopadhyay, A.M. Waite, et al., High-performance nMOSFETs using a novel strained Si/SiGe CMOS architecture, IEEE Trans. Electron Devices 50 (2003) 1961–1969. [38] D.J. Norris, A.G. Cullis, D.J. Paul, D.J. Robbins, High-performance nMOSFETs using a novel strained Si/SiGe CMOS architecture, IEEE Trans. Electron Devices 50 (2003) 1961–1969. [39] S. Takagi, Understanding and engineering of carrier transport in advanced MOS channels, IEEE 52 (2) (2008) 263–267. [40] T. Mizuno, S. Takagi, N. Sugiyama, H. Satake, A. Kurobe, A. Toriumi, Electron and hole mobility enhancement in strained-Si MOSFETs on SiGe-on insulator substrates fabricated by SIMOX technology, IEEE Electron Device Lett. 21 (2000) 230–232. [41] M.L. Lee, E.A. Fitzgerald, Optimized strained Si/strained Ge dual channel heterostructures for high mobility p- and n-MOSFETs, IEDM 18 (2003) 1–4. [42] C.S. Smith, Piezoresistance effect in germanium and silicon, Phys. Rev. 94 (1954) 42–49. [43] M.D. Giles, M. Armstrong, C. Auth, S.M. Cea, T. Ghani, T. Hoffman, et al., in: Understanding stress enhanced performance in Intel 90 nm technology, VLSI Symp. Tech. Dig., Honolulu, HI, 2004, pp. 118–119. [44] N. Tamura, Y. Shimamune, 45 nm CMOS technology with low temperature selective epitaxy of SiGe, Appl. Surf. Sci. 254 (2008) 6067–6071. [45] C. Qin, H. Yin, G. Wang, et al., Study of sigma-shaped source/drain recesses for embedded-SiGe pMOSFETs, Microelectron. Eng. 181 (2017) 22–28. [46] H.H. Radamson, M. Kolahdouz, Selective epitaxy growth of Si1 xGex layers for MOSFETs and FinFET, J. Mater. Sci. Mater. Electron. 26 (2015) 4584–4603. [47] R. Loo, M. Caymax, Avoiding loading effects and facet growth: key parameters for a successful implementation of selective epitaxial SiGe deposition for HBT-BiCMOS and high-mobility hetero-channel pMOS devices, Appl. Surf. Sci. 224 (2004) 24–30. [48] J. Hartmann, L. Clavelier, C. Jahan, P. Holliger, G. Rolland, C. Defranoux, Selective epitaxial growth of boron- and phosphorus-doped Si and SiGe for raised sources and drains, J. Cryst. Growth 264 (2004) 36–47. [49] S. Bodnar, E. de Berranger, P. Bouillon, M. Mouis, T. Skotnicki, J.L. Regolini, Selective Si and SiGe epitaxial heterostructures grown using an industrial low-pressure chemical vapor deposition module, J. Vac. Sci. Technol. B: Microelectron. Nanometer Struct. 15 (1997) 712. [50] N. Tamura, Y. Shimamune, 45 nm CMOS technology with low temperature selective epitaxy of SiGe, Surf. Sci. 254 (2008) 6067. [51] S. Mujumdar, K. Maitra, S. Datta, Layout-dependent strain optimization for p-channel trigate transistors, IEEE Trans. Electron Devices 59 (2012) 72–78. [52] R. Chau, et al., Benchmarking nanotechnology for high-performance and low-power logic transistor applications, IEEE Trans. Nanotechnol. 4 (2005) 153. [53] C. Qin, G. Wang, M. Kolahdouz, J. Luo, H. Yin, P. Yang, J. Li, H. Zhu, Z. Chao, et al., Impact of pattern dependency of SiGe layers grown selectively in source/drain on the performance of 14 nm node FinFETs, Solid State Electron. 124 (2016) 10–15. [54] M. Kolahdouz, L. Maresca, R. Ghandi, A. Khatibi, H.H. Radamson, Kinetic model of SiGe selective epitaxial growth using RPCVD technique, J. Electrochem. Soc. 158 (2011) H457.

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[55] M. Kolahdouz, L. Maresca, M. Ostling, D. Riley, R. Wise, H.H. Radamson, New method to calibrate the pattern dependency of selective epitaxy of SiGe layers, Solid State Electron. 53 (2009) 858. [56] G. Wang, M. Moeen, A. Abedin, Y. Xu, J. Luo, Y. Guo, C. Qin, Z. Tang, H. Yin, et al., Impact of pattern dependency of SiGe layers grown selectively in source/drain on the performance of 22 nm node pMOSFETs, Solid State Electron. 114 (2015) 43–48. [57] M.I. Alonso, K. Winer, Raman spectra of c-Si1 xGex alloys, Phys. Rev. B 39 (1989) 10056. [58] J.C. Tsang, P.M. Mooney, F. Dacol, J.O. Chu, Measurements of alloy composition and strain in thin GexSi1 x layers, J. Appl. Phys. 75 (1994) 8098. [59] J. Groenen, R. Carles, S. Christiansen, M. Albrecht, W. Dorsch, H.P. Strunk, et al., Phonons as probes in self-organized SiGe islands, Appl. Phys. Lett. 71 (1997) 3856. [60] J.W. Matthews, A.E. Blakeslee, Defects in epitaxial multilayers. I. Misfit dislocations, J. Cryst. Growth 27 (1974) 118. [61] M. Hecker, L. Zhu, C. Georgi, I. Zienert, J. Rinderknecht, et al., Analytics and metrology of strained silicon structures by Raman and Nano-Raman spectroscopy, AIP Proc. 931 (2007) 435 (Frontiers of Characterization and Metrology for Nanoelectronics). [62] B.W. Dodson, J.Y. Tsao, Stress dependence of dislocation glide activation energy in single crystal silicon-germanium alloys up to 2.6 GPa, Phys. Rev. B 38 (1988) 12383. [63] R. People, J.C. Bean, Calculation of critical layer thickness versus lattice mismatch for GexSi1 x/Si strained-layer heterostructures, Appl. Phys. Lett. 47 (1985) 229. [64] H.H. Radamson, A. Bentzen, C. Menon, G. Landgren, Observed critical thickness in selectively and non-selectively grown Si1 xGex layers on patterned substrates, Phys. Scr. T 101 (2002) 42. [65] H. Chen, Y.K. Li, C.S. Peng, H.F. Liu, Y.L. Liu, Q. Huang, et al., Crosshatching on a SiGe film grown on a Si(001) substrate studied by Raman mapping and atomic force microscopy, Phys. Rev. B 65 (2002) 233303. [66] B.W. Dodson, J.Y. Tsao, Scaling relations for strained-layer relaxation, Appl. Phys. Lett. 55 (1989) 1345. [67] O. Nur, M. Willander, L. Hultman, H.H. Radamson, G.V. Hansson, CoSi2/Si1 xGex/Si (001) heterostructures formed through different reaction routes: silicidation-induced strain relaxation, defect formation, and interlayer diffusion, J. Appl. Phys. 78 (1995) 7063–7069. [68] L. Yue, W.D. Nix, P.B. Griffin, J.D. Plummer, Critical thickness enhancement of epitaxial SiGe films grown on small structures, J. Appl. Phys. 97 (2005) 43519.

Further reading [1] T.S. Perova, J. Wasyluk, K. Lyutovich, E. Kasper, M. Oehme, K. Rode, et al., Composition and strain in thin Si1 xGex virtual substrates measured by micro-Raman spectroscopy and X-ray diffraction, J. Appl. Phys. 109 (2011) 033502. [2] J. Hallstedt, M. Blomqvist, P.O.A. Persson, L. Hultman, H.H. Radamson, The effect of carbon and germanium on phase transformation of nickel on Si1 x yGexCy epitaxial layers, J. Appl. Phys. 95 (2004) 2397.

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High-κ dielectric and metal gate

4

C. Zhao*,†, X. Wang*,†, W. Wang*,† *Institute of Microelectronics of Chinese Academy of Sciences (IMECAS), Beijing, PR China, † University of Chinese Academy of Sciences (UCAS), Beijing, PR China

4.1

The scaling of MOSFET devices

In 1930, Lilinfeld filed the first patent of the field effect transistor (FET) [1]. Thirty years later, in the 1960s, it was finally introduced into practice by using Si–SiO2 to form a so-called MOSFET, or metal-oxide-semiconductor FET [2]. MOSFET has become the fundamental active device of logic integrated circuit after the invention of complementary MOSFET (CMOSFET), which connects p- and n-channel MOSFETs together in such a way that both gates and both drains are linked together, respectively. The most important advantage of the CMOS logic is its low power consumption because at its static state, no matter “1” or “0,” there is always one of the MOSFETs at its “off” state; thus, no current flows through the CMOSFET, and no power is consumed. Only in a very short time interval in which the switching is “dynamically” going on, the current flows and power is consumed. This could be summarized as “zero static power consumption” for CMOS. CMOS meets all the requirements for high performance (speed), low static (off-state) power, and a wide range of power supply and output voltages [3]. Combined with developing the ability to perform a reduction of the device dimensions in the circuit or, as practically termed, scaling, it has brought about the rapid progress of the integrated circuit industry since the late 1980s. The scaling strategy has been the major enabler for improving circuit speed, reducing power dissipation and increasing device density [4] for five decades. In 1965, Intel cofounder Gordon Moore forecasted exponential growth in the number of transistors per integrated circuit, and predicted that the trend would continue [5]. This prediction, popularly called “Moore’s Law,” states that the number of transistors on integrated circuits doubles approximately every 24 months, resulting in higher performance at lower cost. In the past 50 years, this simple but profound statement has become a solid “law” and even rules the community use to define their research and development road map. It has stimulated the emergence of generation after generation of new personal computers and mobile smart terminals, and has fueled the worldwide information technology revolution. Fig. 4.1 gives out a schematic depiction of the transistor counts growth for Intel processors (dots) and Moore’s Law (line).

CMOS Past, Present and Future. https://doi.org/10.1016/B978-0-08-102139-2.00004-5 Copyright © 2018 Elsevier Ltd. All rights reserved.

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109 Transistors per chip

Fig. 4.1 Growth of transistor counts for Intel processors (dots) and Moore’s Law (line). Moore’s Law means more performance and decreasing costs.

Itanium(R) CPU Pentium(R) 4 CPU Pentium(R) III CPU Pentium(R) II CPU Pentium(R) CPU 486TM

108 107 106

386TM 80286

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8086

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SiO2 and poly-Si gate electrode

4.2.1 SiO2 gate dielectric The conventional gate stacks in MOSFETs mainly consist of heavily doped polysilicon electrode (poly-Si), SiO2 dielectric, and the Si substrate, as schematically depicted in Fig. 4.2. SiO2 has been used for >40 years as an excellent gate insulator responsible for blocking current flow through the gate stacks in CMOS devices. To improve the device performance, SiO2 thickness has been scaled aggressively, together with other dimensions, to invert the channel to a sufficient charge density to obtain large enough operation current for the given supply voltage and avoid short channel behavior. However, with the rapid downscaling of the devices, SiO2 thickness is reduced from 100 nm 30 years ago to 1.2 at the 90 nm node. Such a thickness means that the oxide layer is composed of only four atom layers in a perpendicular direction. This tendency will cause a problem such that the tunneling leakage across the SiO2 dielectric increases exponentially, which eliminates the advantage of the CMOS in low static power consumption, and shortens the standby time of mobile smart terminals to an unacceptable extent. According to simulation, the heat generated by the gate leakage would melt the whole circuit if it continues to scale the device dimension without suppression of the leakage.

Fig. 4.2 Basic CMOS transistor structure using SiO2 as a dielectric and polysilicon (poly-Si) as metal gates.

High-κ dielectric and metal gate

71

Electron EC EF

EV Hole

Poly-Si

SiO2

Si

Fig. 4.3 Schematic of tunneling current in MOSFETs using polysilicon and SiO2.

The tunneling leakage is a quantum effect. Fig. 4.3 schematically shows the tunneling current of gate stacks in MOSFET, where the SiO2 dielectric is used as a barrier layer for the electrons or holes in the Si substrate. The tunneling leakage current depends on many parameters, as depicted by Eq. (4.1) [6] A Jg ¼ 2 e Tox

2Tox

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi   2m∗ q ΦB ℏ2

Vox 2

(4.1)

where A is an experimental constant, Tox the physical thickness of SiO2 dielectric, ΦB the potential barrier height between the metal and the SiO2, Vox the voltage drop across the dielectric, and m* the electron effective mass in the dielectric. For a defect-free dielectric, the potential barrier ΦB is determined by the energy band alignment between SiO2 and the Si substrate. Fig. 4.4 gives out a schematic description of the energy band diagram of SiO2 and the Si substrate. For electron transportation, the barrier is the conduction band offset given as ΔEC. For hole transportation, it is the valence band offset given as ΔEV. From Eq. (4.1), one can see that the leakage current depends exponentially on the square root of the barrier height. The barrier height is also relative to the defect density in the dielectric. For highly defective films, the electron could be trapped by the defects, forming energy levels in the SiO2 bandgap. The electron transport in it is thus governed by a trap-assisted mechanism such as the Frenkel-Poole emission or hopping conduction [6]. Thickness is another important parameter for the insulation behavior of the barrier. The dependence of the tunneling leakage current on the physical thickness of SiO2 is shown in Fig. 4.5 [7]. For those thinner than 1 nm, the extremely high tunneling

Fig. 4.4 Energy band diagram of SiO2 and the Si substrate. For electron transportation, the barrier is the conduction band offset given as ΔEC. For hole transportation, the barrier is the valence band offset given as ΔEV.

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Fig. 4.5 Gate leakage current density vs. SiO2 physical thickness [7].

leakage current will cause the transistor to stray from its “on/off” behavior or, in other words, it could not be switched off anymore. The International Technology Roadmap for Semiconductors (ITRS) has given the gate leakage current density limit and simulated gate leakage due to direct tunneling for various logic technology requirements, for example, low standby power logic, low operating power logic, and high-performance logic, as shown in Fig. 4.6 [8]. The curves for maximum allowed gate leakage current density are labeled with “Jg, limit”. Obviously, silicon oxide or oxynitride gate dielectrics are projected to be unable to meet the gate leakage current limit by 2006. Without a new solution to solve the leakage issue, Moore’s Law would inevitably hit a wall.

4.2.2 Poly-Si gate electrode Besides the tunneling leakage problem associated with the scaled SiO2 dielectric, the issues related to the heavily doped polysilicon gate electrode are also becoming severe, such as polysilicon depletion effect and boron (B) penetration [9–11]. The process requirements of traditional n+/p + dual-gate CMOS technologies result in a compromise in the achievable electronically active impurity concentration in the polysilicon gate [12]. The implantation and annealing conditions for the polysilicon doping must be carefully selected to avoid impurity penetration through the gate oxide, while keeping the required source/drain junction depth and lateral diffusion length by scaling rules. If the active dopant levels in the polysilicon are not sufficient, a depletion layer might form near the polysilicon/oxide interface when the device is biased in strong inversion, which in turn results in degraded device characteristics (the so-called polysilicon depletion), as schematically shown in Fig. 4.7. This effect adds ˚ to the effective dielectric thickness, which has a remarkable impact on the  3–4 A scaling for sub-0.1-μm technology nodes [13]. It seems that the doping density, activated electronically, is rarely above 1020/cm3 for n + polysilicon and above the mid1019/cm3 for the p + polysilicon electrode. This implies that the inherent capability in

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Beyond this point of cross over, oxynitride is incapable of meeting the limit (Jg,limit) on gate leakage current density

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Fig. 4.6 (A) Low standby power logic scaling-up of gate leakage current density limit and of simulated gate leakage due to direct tunneling [8]. (B) Low operation power logic scaling-up of gate leakage current density limit and of simulated gate leakage due to direct tunneling [8]. (C) High-performance logic scaling-up of gate leakage current density limit and of simulated gate leakage due to direct tunneling [8].

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VG

VS n+

n+ Poly-Si + + + + + + + + ++ SiO2

tox_eff

p

Poly depletion length

VD

−−−−−−−−−−

Inversion charge

Channel electrons

Poly gate depletion

n+

Tox total

Ef

Substrate depletion p-Type Si

VB

Highly doped poly-Si gate metal

Oxide

Fig. 4.7 Schematic diagram of polysilicon depletion effect.

improving device performance is very limited. Suppose more efficient implantation and annealing could add more boron to the p + polysilicon gate to minimize depletion, with the thinning of the gate dielectric, the increase of the boron doping level will result in increased B diffusion. The out-diffused B dopant accumulates in the n-Si substrate where it can change the threshold voltage and reduce dielectric reliability, thereby again degrading the intended device quality in an uncontrollable and unacceptable way [14]. Another concern on the polysilicon gate electrode is its compatibility to high-κ dielectric. It is anticipated that polysilicon will not be stable on most high-κ dielectric materials since it can react with high-κ dielectric to form metal silicides. The polysilicon gate technology has been phased out beyond the 65 nm node, after which it needs to be definitely replaced by metal gate electrodes.

4.3

High-κ dielectric and metal gate

To solve the problems of poly-Si/SiO2/Si gate stack resulted from the aggressive scaling of MOS device dimensions, the use of an alternative gate stack is necessary. In the alternative stack, the dielectric should have a higher dielectric constant, and thus allow a larger physical thickness than SiO2 dielectric under the condition of keeping the same electrical capacitance. The gate electrode in the stack should be metal, which could avoid the formation of depletion and dopant penetration. Remarkable efforts have been devoted to the research work of looking for suitable new gate materials, which not only have the required material properties, but also allow simple integration flow for cheap mass production.

4.3.1 High-κ gate dielectric As mentioned in Section 4.2.1, the tunneling leakage across the dielectric depends on the barrier height and the thickness of the dielectric. The thinner the dielectric, the higher the leakage is. This is why the leakage keeps rising to an intolerable limit when the dimension of the MOS devices is scaled down to a nanometer. If a thicker SiO2

High-κ dielectric and metal gate

75

dielectric is used, the leakage could be easily reduced. The electrical capacitance across the dielectric, however, will be reduced to a large extent, resulting in immediate loss in device performance. The only possible solution to reduce the tunneling leakage without trade-off in performance is to use a dielectric with a higher dielectric constant, which could yield the same electrical capacitance across the dielectric when a thicker dielectric is used. The gate capacitance can be expressed as (ignoring quantum mechanical and depletion effects from an Si substrate and gate) C¼

κε0 A t

(4.2)

where κ is the dielectric constant (also referred to as the relative permittivity) of the material, ε0 the permittivity of free space (¼8.85  10 3 fF/fm), A the area of the capacitor, and t the thickness of the dielectric. This expression for C can be rewritten in terms of teq (i.e., equivalent oxide thickness EOT) and κ ox (¼3.9, dielectric constant of SiO2) of the capacitor. The term teq represents the theoretical thickness of SiO2 that would be required to achieve the same capacitance density as the dielectric. For example, if the dielectric is SiO2, teq ¼ 3.9ε0(A/C), and a capacitance density of C/A ¼ 34.5 fF/μm2 corresponds to an equivalent thickness teq ¼ 1 nm. Thus, the physical thickness of an alternative dielectric employed to achieve the equivalent capacitance density of teq ¼ 1 nm can be obtained from the following expression. teq thigh-κ ¼ κ ox κ high-κ

(4.3)

For example, a dielectric with a relative permittivity of 16 and a physical thickness of 4 nm can give an equivalent thickness of 1 nm. As noted above, the actual performance of a CMOS gate stack does not scale directly with the dielectric due to possible quantum mechanical and depletion effects [15]. Considering the relation of the leakage current with the physical thickness of oxides described above in Eq. (4.1), the increased physical thickness in films with a higher relative permittivity would effectively decrease the tunneling leakage, while keeping the equivalent capacitance density, and consequently drive the current invariable. It is the higher relative permittivity, or κ value, that increases the transistor capacitance so that the transistor can switch properly between “on” and “off” states and have a much lower drain current when off, yet very high drain current when on. To select a high-κ material, many other properties, besides κ value, must be taken into account, such as bandgap, band misalignment, thermal stability, compatibility with gate electrode, and its impact on channel mobility [16–18]. The bandgap of oxide dielectric or, more importantly, the barrier height, tends to decrease with an increasing dielectric constant [16]. Table 4.1 and Figs. 4.8 and 4.9, summarizes the relative dielectric constants, experimental bandgaps, and band offsets of most high-κ candidates [16,19]. The decrease in bandgap would induce a smaller conduction band offset, or the barrier height, and thus an increase in tunneling leakage, and this might

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Experimental bandgaps, relative dielectric constants, and conduction band offset on Si for high-κ candidates Table 4.1

Dielectrics

Dielectric constant

Bandgap Eg (eV)

Conduction band offset (eV)

Si SiO2 Si3N4 Al2O3 ZrO2 ZrSiO4 HfO2 HfSiO4 La2O3 Ta2O5 TiO2

11.9 3.9 7.9 9.5–12 12–16 10–12 16–30 10 20.8 25 80–170

1.1 8.9 5.3 5.6 5.7–5.8 6 4.5–6 6 6 4.4 3.05

3.5 2.4 2.8 1.4–15 1.5 1.5 1.5 2.3 0.36 0

10 SiO2

9

Al2O3 8 Band gap (eV)

MgO CaO

7 ZrSiO4 6

HfSiO4

Y2O3

ZrO2 HfO2

SrO

5

La2O3

Si3N4

4

BaO

Ta2O5

TiO2

3 2

0

10

20

30 K

40

50

60

Fig. 4.8 Dependence of bandgap on dielectric constant for various high-κ candidates. Reprint from J. Robertson, High dielectric constant oxides, Eur. Phys. J. Appl. Phys. 28 (2004) 265–291.

offset the reduction in leakage current caused by the increase in physical thickness of the high-κ dielectrics. Therefore, a balance between κ-value and bandgap is necessary. This is why materials such as ZrO2, HfO2, La2O3, and Al2O3 have been widely studied as the high-κ candidates. These materials have an acceptable high κ-value and, at the same time, a large enough conduction band offset.

High-κ dielectric and metal gate

77 6 4 CB

3.5

Ve > 1 V Energy (eV)

1.1 V 0V

0

0.3

0.8 1.4

1.5

2.3

3.4 3.3

3.4

2.6 3.4

1.5 2.1

−0.1

1.1 1.8

2.3 3.0

−2

1.9

4.4

Vh > 1 V Si

2.8

2.4

2

4.9

VB Oxide

−4 Si

SiO2

SrTiO3 ZrO2 Ta2O5 HfO2 Si3N4 BaZrO3

LaAIO3

Y2O3 ZrSiO4 Al2O3 La2O3 HfSiO4

−6

Fig. 4.9 Schematic diagram of band offset, and the calculated conduction and valence band offsets for a number of potential high-κ candidates on Si. Reprint from J. Robertson, High dielectric constant oxides, Eur. Phys. J. Appl. Phys. 28 (2004) 265–291.

The interface quality of high-κ dielectric and Si underneath is also an important consideration. First, the formation of a poor interfacial oxide between the high-κ dielectrics and the Si substrates during gate stack preparation might increase the leakage as well [18]. The defects near the interface play a role to reduce the barrier height of the dielectric and worsen the tunneling leakage. Second, the quality of the interface is also critical for the carrier mobility in channel for a constant electric field scaling. In an ideal device scaling, the operating voltage and transistor dimensions are reduced by a fixed factor, while in practice the feature dimensions have been reduced more rapidly than the operating voltage, therefore causing a rapid increase in electric field across the gate dielectric. The continual decrease in the EOT value for scaling CMOS increases also the effective electric field in the channel region. As a result, these increases in electric field pull the carriers in the channel closer against the dielectric interface. The more confined carriers have harder phonon scattering and thereby decreases in the channel carrier ˚, mobility. At very high electric fields in the channel, such as established by teq < 10 A interface roughness scattering further reduces carrier mobility. Thermal stability is another selection standard for high-κ candidate, or the high-κ and SiO2 must have low coefficients of interdiffusion, withstanding high processing temperatures, to avoid mixed-oxide formation. In fact, although there are so many films with higher κ values than SiO2, ranging from a κ value of about 7 for Si3N4 to a κ value as high as 1400 for PbLaTiOx [20,21], most of them are not thermodynamically stable with respect to Si, or they are easy to react with Si. Other properties that need to be taken into account include high breakdown voltage, good adhesion with the Si substrate and the metal gate electrodes on top, reasonable deposition temperature, and ability to be patterned with available patterning techniques. Considering all these requirements, recent research on high-κ dielectrics has mainly focused on the oxides and silicates of transition metals such as Hf and Zr, and rare earth metals [22–25]. MOSFETs based on these films showed excellent overall characteristics promising for the application.

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4.3.2 Metal gate electrode Besides the high-κ dielectrics, new metal electrodes are required to replace the conventional polysilicon gate electrode to avoid the polysilicon depletion, boron penetration, and compatibility issues with high-κ dielectrics. The first requirement for the metal gate electrodes is the work function, with which the threshold voltage (Vt) for both pMOS and nMOS can be achieved [6]. This can be realized by using a single mid-gap metal as shown in Fig. 4.10A, or using two different metals with different work functions, one near the bottom of conduction band Ec, and the other near the top of the valence band Ev, as shown in Fig. 4.10B. Over the years, the use of polysilicon gate electrodes has deeply rooted in CMOS device technology. The necessity of finding new gate stack of high-κ and metal gate materials and processes at the time has caused great concern in the industry, which has tried to maintain the baseline they are familiar with. Therefore, the first impulse in selection of a metal gate was to find a single metal near the mid-gap [6]. This metal is expected to maintain the nearly equal but opposite polarity for nMOS and pMOS threshold voltage (Vt) values required for device operation. The main advantage of employing a mid-gap metal arises from a symmetrical Vt value for both nMOS and pMOS. This affords a simpler CMOS processing scheme, since only one mask and one metal would be required for the gate electrode without an ion implantation step. However, from the viewpoint of device performance enhancement, this approach is obviously not feasible for planar MOSFET. The reason is quite simple: the midgap work function induces threshold voltage as high as 0.5 V, resulting in small on-state drain current. It must be noted that the above discussion on the single metal approach applies only for planar bulk Si CMOS technology. For new device architectures such as FinFETs and fully depleted silicon-on-insulator (FD-SOI), which have been introduced into production in recent years, the conclusion might be different [26]. FD-SOI uses ultrathin single-crystal Si bonded on an oxide insulator as a channel of planar MOSFETs. FinFETs is a multiple-gate ultrathin channel MOSFET. For them, undoped channels could be used for both nMOS and pMOS devices, and thus a gate material with a mid-gap work function is desirable [27]. In these devices, the Vt can also be set

Fig. 4.10 Energy diagrams of threshold voltages for nMOS and pMOS devices using (A) mid-gap metal gates and (B) dual metal gates.

Single midgap metal

Dual metals Vacuum level

Si

Ec

Ec nMOS Vt

1.1 eV

pMOS Vt Ev

(A)

FM

Ev

(B)

FM Pt

FM Al

High-κ dielectric and metal gate

79

to the desired value of several tenths of a volt for nMOSFETs and similar negative values for pMOSFETs. The gate electrode work function near mid-gap (quasi-midgap) is thus favorable. In the dual-metal gate strategy shown in Fig. 4.10B, two metals could be chosen based on their work functions, ΦM, such that their Fermi levels line up with the conduction band and valence band of silicon substrate. Simulation considering the quantum effect on the device drive current reveals that the ΦM of the gate electrodes for nMOS and pMOS must be around 4 and 5 eV, respectively [28]. To search for metallic materials with suitable work functions, almost all the metals have been considered. Among them, Ta, V, Zr, Hf, and Ti as metal electrodes with low work functions for nMOS devices, and Mo, W, Co, and Au with high work functions for pMOS devices were investigated systematically. Metal nitrides and alloys are also been in the consideration, such as WNx, TiNx, MoNx, TaNx, TaSixNy, Ru–Ta, Ru–Zr, Pt–Hf, Pt–Ti, Co–Ni, Ti–Ta, and so on. The work functions of metals as the metal gate candidates for CMOS devices are summarized in Fig. 4.11 [29]. Further learning form experiments show that the selection of metal gate electrode candidates is much more complex than it was believed at the beginning. The vacuum work function is not a proper benchmark for metal gate selection and, in some cases, even a misleading one when it is integrated in a high-κ/metal gate stack. The reason lies in the fact that energy band structures of the metal gates, high-κ, the interfacial layer, and the Si substrate in the stack are not the same as what they look like in vacuum separately, and the band of the metal will change when in contact with a specific high-κ. To make the band alignment analysis simple, a new concept termed “effective work function (EWF)” is introduced to replace the vacuum work function. Fig. 4.12 schematically depicts the energy bands of a metal gates, high-κ, the interfacial SiO2 layer and the Si substrate when standing alone in vacuum separately. The vacuum energy levels for the four materials are consistent, while the Fermi level is not. As they were put together, their vacuum levels will shift to make the Fermi level consistent, as displayed in Fig. 4.1B. The vacuum level bending is a result of many different impacts including that of areal charge at the high-κ/SiO2 interface, the bulk Fig. 4.11 Work functions of some potential metals for CMOS devices [29].

80

Fig. 4.12 Schematic energy band of metal, high-κ dielectric, SiO2 and Si. ΦM is the vacuum work function of a metal gate before (left) and after (right) contact.

CMOS Past, Present and Future

FM

FM Ec EF

EF

EF

Ev

High-k Metal SiO2 Si

Ec EF Ev

High-k Metal SiO2 Si

charges in the high-κ dielectric, the dipole at the high-κ/SiO2 interface, and the Fermi level pinning at the metal/high-κ interface. The effective work function of the metal gate is thus defined as the energy difference from EF to the vacuum level of the Si substrate, instead of that of the metal gate itself. As the concept of equivalent oxide thickness (EOT) induced to describe high-κ dielectric, EWF is the work function “equivalent” to that of poly-Si on SiO2. Using the EOT to replace the physical thickness of high-κ, and EWF to place the vacuum work function of the metal electrodes, all the theory for poly-Si and SiO2 stacks applies to modeling the high-κ/metal gate stack and guiding the gate engineering of CMOS devices. Besides the effective work function, compatibility with Si process technology is another factor that needs to be taken into account, which is much more challenging for real application of the metal electrode. In the dual-metal process, for instance, sequential deposition and selective etching of both metals is necessary, in which the etching of the first metal from the top of the gate oxide will cause potential damage, particularly during the over-etching required to assure complete removal of the first metal layer. Since the Vt is so sensitive to the interface states, any residue of the first metal or damage will cause the Vt shift. Considering the number of devices on one silicon wafer and the number of wafers in mass production, it is easy to understand the difficulty in avoiding any Vt variation for good within-wafer and wafer-towafer uniformity. Special arrangements have been proposed based on the specific properties of the materials chosen. In one of them, first metal layer with an effective work function appropriate for nMOS is suggested to be firstly deposited, followed by the deposition of a second metal chosen to form an alloy with the first metal to generate an effective work function appropriate for the pMOS device. A thermal treatment will be conducted to form the alloy [30]. Prior to the thermal treatment, the second metal film is etched off from the nMOS device area, leaving the first metal film in place. By doing these, removal of the first metal directly from the dielectric is avoided. Another technique depends upon the fact that compounds of some metals, for instance, their nitrides, have metallic properties with EWF different from that of the parent metal. As for this process, after deposition of the parent metal layer, appropriate devices are masked photolithographically so that those remaining exposed can be implanted with N2. The nitride is then formed by postannealing [31].

High-κ dielectric and metal gate

81

The chemical stability of the metal during the high temperature process is also a critical concern for metal gate application. The highest temperature step in the conventional CMOS process is the thermal annealing for activation of dopants in the source, drain, and gate regions of the transistors, where rapid thermal annealing (RTP) between 900 and 1100°C is employed. Metal gates must keep stable during this activation. As described above, alternative metal gates could be elemental metals, metal oxides, metal nitrides, metal silicides, or alloys of more than two kinds of metals. Many of them, however, are instable both on SiO2 and on high-κ dielectrics [32,33]. After the activation, their effective work function changes obviously, making the integration fail. Such an instability issue is widely observed in low work function metals on SiO2 or high-κ. A method to overcome the interface instability of the metal gate electrode and high-κ dielectric during the high temperature fabrication process is the gate-last process [34]. After the deposition of the high-κ dielectric, the conventional process for a poly-Si gate is conducted. The poly-Si gate is made as the replacement gate which goes through the following annealing activation of the source and drain regions. After the process at the highest temperature, or so-called “thermal budget,” the poly-Si gate is removed and leaves a trench for the deposition of the metal gate electrode. After filling of the trench with work function metal and conductive metals, a chemicalmechanical polarization is conducted. In such an integration scheme, the source/drain activation annealing is done before the deposition of the metal gate electrode. The Vt shift related to the thermal instability of the metal gate is successfully avoided. Another advantage of the gate-last scheme lies in the readiness of enabling stress enhancement before removing the poly-Si gate from the transistor. Further enhancement of the strain is beneficial for improving the performance of the devices [35,36].

4.4

Hafnium-based high-κ dielectrics

A promising high-κ dielectric material should have a permittivity between 10 and 30, a bandgap above 5 eV, and band offsets with a semiconductor substrate above 1 eV. It should be thermally stable within the thermal budget in order to form a compatible electrical interface with semiconductor substrates. This consideration phases out most of the early high-κ candidates from memory applications such as Ta2O5 [37,38]. Through a careful balance of all relevant requirements for the gate dielectric material, hafnium-based materials emerged over the past decade as the selected dielectrics. In this section, hafnium-based oxides, HfO2, HfAlO, and HfLaO, are assessed in detail for the application in planar CMOS technology.

4.4.1 Hafnium oxide Hafnium oxide was successfully introduced into production in 2007 [38]. It has a dielectric constant, about 25, and a relatively large bandgap, 5.7 eV, large heat of formation ( 271 kcal/mol, higher than that of SiO2: 218 kcal/mol), good thermal and chemical stability on silicon, and large barrier height at interfaces with Si.

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CMOS Past, Present and Future

At an operation voltage of 1–1.5 V, the leakage current through HfO2 dielectric films was reported to be several orders of magnitude lower than that of SiO2 with the same equivalent oxide thickness (EOT) in the range of 0.9–2 nm [34,37]. HfO2 has three different crystalline phases, monoclinic, tetragonal, and cubic. It possesses the monoclinic phase [39] at ambient pressure and temperature and transfers from the monoclinic to the tetragonal phase at 1022°C, and from the tetragonal to the cubic phase at 2422°C, as temperature increases. The dielectric constants of these HfO2 phases are different. For the monoclinic clinic, it is about 18 [40], for the tetragonal phase around 28 [37,40,41], and for the cubic phase as high as 50 [42]. Several attempts have been made to increase the dielectric constant of HfO2 by control of annealing conditions [40,43] or doping stabilizer elements into HfO2 to obtain high dielectric constant crystalline phases [40,43–46]. For example, the addition of a small amount of Si into HfO2 is reported to be able to stabilize the tetragonal HfO2 and yield a dielectric constant of 36 after annealing at 700°C [47]. Alloying La into HfO2 seems to have similar effects [48]. HfO2 on Si shows a band offset >1 eV, which is large enough to reduce the gate leakage current for the scaling in the 45-nm node and beyond [45]. It is found that the chemical composition, crystal structure, and defects have a significant effect on the band alignments of HfO2 on Si [48,49]. As shown in Fig. 4.13, theoretically calculated valence band offsets of the HfO2/Si interface ranged from 2.69 to 3.04 eV and conduction band offsets ranged from 1.54 to 1.89 eV. It is found that they are a function of the interface composition and coordination numbers. In the real HfO2/Si stack, an interfacial layer always exists, which might be SiOx or HfSiOx. Such an interfacial layer will further change the band alignment. Figs. 4.14 and 4.15 show the band alignment of the HfO2/IL/Si, where IL is SiO2 or HfSiO4, respectively. For an HfO2/SiOx/ Si stack, the valence band offsets are 4.75 eV for SiO2 and 2.53 eV for HfO2 [50]. In the HfO2/Hf1 xSixO2/Si heterostructure, the offset is 3.0 for Hf1 xSixO2 and 3.8 eV for HfO2, respectively [51]. Post deposition annealing (PDA) also impacts the band

Si

t-HfO2

t-HfO2-O

HfSiO4 2.19

1.89

1.64

1.54 Energy (eV)

t-HfO2-H

1.12

3.04

2.70

2.94

2.69 1.76

2.50

2.69

Fig. 4.13 Band alignments at the stoichiometric and modified metal-oxide-Si interfaces. The thicker dark lines indicate the partially occupied states for the stoichiometric interfaces and the fully occupied states for the other interfaces. Reprint from R. Puthenkovilakam, J.P. Chang, An accurate determination of barrier heights at the HfO2/Si interfaces, J. Appl. Phys. 96 (2004) 2701–2707.

High-κ dielectric and metal gate

83

Vacuum level 0.9 eV Ec 2.1 eV Ec 1.12 eV Ev 9.0 eV 2.53 eV 4.75 eV

Ev

HfO2

SiO2

Si

Fig. 4.14 Energy band diagram of HfO2/SiO2/Si constructed based on the XPS valence band structure analysis. The bandgap of HfO2 is 5.75 eV. Reprint from I. Geppert, E. Lipp, R. Brener, S. Hung, M. Eizenberg, Effect of composition and chemical bonding on the band gap and band offsets to Si of HfxSi1 xO2(N) films, J. Appl. Phys. 107 (2010) 053701-4.

Fig. 4.15 Energy-band diagram obtained by photoelectron spectra and X-ray absorption spectra in the HfO2/ Hf1 xSixO2/Si heterostructure. Reprint from R. Puthenkovilakam, J.P. Chang, An accurate determination of barrier heights at the HfO2/Si interfaces, J. Appl. Phys. 96 (2004) 2701–2707.

Energy (eV)

1.6 nm

2.7 eV

CBMSi

2.8 nm

∆Ec1 = 3.7 eV

∆Ec2 = 1.0 eV 5.1 eV

8.6 eV

VBMSi ∆Ev2 = 3.0 eV

∆Ev1 = 3.8 eV

0.8 eV HfO2

Hf1−xSixO2

1.1 eV

Si

84

CMOS Past, Present and Future

CB

CB 4.3 eV

Trap level

0.4 eV

2.1 eV Up to 450°C Fermi level 1.5 eV VB

3.9 eV

VB

Fig. 4.16 A schematic diagram of band structure of the HfO2 thin films annealed at different temperatures. These results indicated that band alignment was strongly affected by the crystalline structure and trap levels formed below the conduction band after the recrystallization of HfO2 thin films. Redrawn based on S. Toyoda, J. Okabayashi, H. Kumigashira, M. Oshima, K. Ono, M. Niwa, K. Usuda, N. Hirashita, Chemistry and band offsets of HfO2 thin films on Si revealed by photoelectron spectroscopy and X-ray absorption spectroscopy, J. Electron Spectrosc. Relat. Phenom. 137–140 (2004) 141–144.

alignment at the dielectric/semiconductor interface, due to the chemical modification at the interface, as stated in Fig. 4.16 [50]. One of the main challenges of HfO2 application in CMOS technology is the thermal instability of the HfO2/Si contact. It is found that an interlayer (IL) such as SiOx between HfO2 and the Si substrate forms easily, as shown in Fig. 4.17 [37,52]. If the thickness and κ-value of the interfacial layer cannot be well controlled, the EOT target will not be reached, especially for further scaling. A theoretical study [53] shows that the HfO2/Si system is thermodynamically stable. The experimental evidence of epitaxial HfO2 directly on Si is reported [37], where an amorphous layer deposited first by ALD on Si(111) substrate and then annealed at annealing conditions optimized with great care. The recrystallized HfO2 has been found to be epitaxial on Si, without any interfacial layer, as shown in Fig. 4.18. The epitaxial HfO2 layer has a cubic morphology and a κ value around 50 [54]. The capping layer on top of the HfO2 layer has proved to be able to scavenge the oxygen of the interlayer between HfO2 and the Si substrate and result in an IL-free stack with ultrathin EOT, as shown in Fig. 4.19 [54–58]. Those encouraging data demonstrated the possibility of growing ultrahigh-κ HfO2 directly on Si to obtain an ultrathin EOT high-κ dielectric.

High-κ dielectric and metal gate

85

Fig. 4.17 TEM images of HfCx, TaCx, and TaN on HfO2 after annealing at 950°C for 30 s. Reprint from Z.B. Zhang, S.C. Song, C. Huffman, J. Barnett, N. Moumen, H. Alshareef, P. Majhi, M. Hussain, M.S. Akbar, J.H. Sim, S.H. Bae, B. Sassman, B.H. Lee, Integration of dual metal gate CMOS with TaSiN (NMOS) and Ru (PMOS) gate electrodes on HfO2 gate dielectric, in: IEEE Symposium on VLSI Technology, 2005, pp. 50–51.

HfO2(111) 5 nm

5 nm

Si(111)

Si(100) Si(111)

Fig. 4.18 Magnified TEM images of HfO2 films prepared by RTC at 1000°C on Si(111) and Si(100) substrates. Epitaxial growth is confirmed in both cases. The marks in the images indicate HfO2(111) and Si(111) planes. Reprint from W.S. Hwang, C. Shen, X. Wang, D.S.H. Chan, B.J. Cho, A novel hafnium carbide HfCx metal gate electrode for NMOS device application, in: IEEE Symposium on VLSI Technology, 2007, pp. 156–157.

Fig. 4.19 X-TEM images of the TiN/Ti/ALD-HfO2/Si gate stacks after annealing at 910°C. No SiO2 interfacial layer is observed, and the HfO2 layers crystallize in both the 2.4 (A) and 3.2 nm cases with the EOT of 0.25 nm (B). Reprint from C. Choi, J.C. Lee, Scaling equivalent oxide thickness with flat band voltage (VFB) modulation using in situ Ti and Hf interposed in a metal/high-k gate stack, J. Appl. Phys. 108 (2010) 064107-4.

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Compared to the effort to make an IL-free high-κ/Si stack, it is more practical to make an interfacial layer with higher κ value than SiOx. The formation of the interlayer between HfO2 and the Si substrate, such as HfSiO or SiON, may effectively improve the EOT of the stack. The κ value of the high-κ and the interfacial layer can be extracted from the C-V measurements of a series of samples with high-κ layers of different thicknesses. By plotting the EOT of them as a function of physical thickness, as shown in Fig. 4.20, the κ value of the high-κ dielectric can be easily obtained from the slope of the line, and that of the interfacial layer from the comparison between the intercept of the line on the EOT axis and the physical thickness of the IL by TEM. As the first high-κ material applied in industrial production [34], HfO2 achieved a big success in reduction of the gate tunneling leakage. Fig. 4.21 compared the

EOT

k high-k = kSiO2/slope

Physical thickness

Fig. 4.20 EOT-physical thickness plot for extraction of the κ value of the high-κ dielectric and the EOT of the interfacial layer.

100 Normalized gate leakage

SiON/poly 65 nm [7] 10 1 0.1

SiON/poly 65 nm [7]

0.01 0.001 HiK + MG 45 nm

HiK + MG 45 nm

0.0001 PMOS 0.00001 −1.2 −1 −0.8 −0.6 −0.4 −0.2

0 0.2 VGS (V)

NMOS 0.4

0.6

0.8

1

Fig. 4.21 High-κ + metal gates enable 25–1000 gate leakage reduction [34].

1.2

High-κ dielectric and metal gate

87

leakage current of leakages of similar devices using SiON/polysilicon gate stack and high-κ/metal gate stack, as reported by INTEL. High leakage reduction for both pMOS and nMOS has been achieved.

4.4.2 Hafnium aluminate Hafnium aluminate (HfxAlyO) was widely studied as a high-κ candidate for the gatefirst integration scheme, where an amorphous morphology is preferred to [59–62]. It is found that HfO2 and the Al2O3 alloy deposited by ALD have crystallization temperature as high as 900°C and a band offset to Si >1 eV [62]. An interesting property of the HfxAlyO lies in that it can help to tune the effective work function of a metal gate and shift the work function in a positive direction [59–62]. As shown in Fig. 4.22, the Vt shifts positively by 0.1–0.3 V when a AlO capping layer is inserted in between the HfO2 and the metal gate [63]. The Vt tuning effect of the AlO layer is believed to be related to the alloying of the Al into the HfO2 layer because both studies show clearly the mixing of the AlO and HfO2 layers. The physical origin of the positive shift due to Al doping is still under debate (Fig. 4.23). Capping the HfO2 with an Al2O3 layer has another favorable impact on the stack. It can suppress the growth of the interfacial SiO2 layer during postdeposition annealing (PDA). No increase in the interfacial SiO2 has been found after PDA at temperatures up to 900°C in a stack of 1.2 nm Al2O3/2.6 nm HfO2/0.35 nm SiO2 film [37]. Al2O3 has been used also as a buffer layer between HfO2 and Si to prevent boron penetration

pMOS

pMOS

200 100 Cap above Cap below

0 Cap above Cap below

−100 −200 −300 −400

HLP

MLP

Spike

LLP

nMOS

nMOS HLP

−600

LLP

−500

Spike

∆Vt =Vt –Vt _ no cap (mV)

300

High−K = HfO2

High−K = HfSiO

400

Fig. 4.22 Vt shift with capping layers as a function of location, annealing, and host dielectric. Spike means spike annealing. LLP is annealing by low laser power. MLP is moderate laser power. HLP is high laser power. Reprint from N. Mise, T. Morooka, T. Eimori, S. Kamiyama, K. Murayama, M. Sato, T. Ono, Y. Nara, Y. Ohji, Single metal/dual high-k gate stack with low Vt and precise gate profile control for highly manufacturable aggressively scaled CMISFETs, in: IEEE International Electron Devices Meeting, 2007, pp. 527–530.

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CMOS Past, Present and Future

7

6

Energy (eV)

5

Energy gap (Eg) Valence band offset (∆ Ev)

4

Conduction band offset (∆ Ec)

3

2

1

0.0 (Al2O3)

0.2

0.4

0.6

0.8

1.0 (HfO2)

HfO2 mole fraction x in (HfO2)x (Al2O3)1−x

Fig. 4.23 Dependence of energy bandgap, valence band offset, and conduction band offset of (HfO2)x(Al2O3)1 x on Hf composition. Reprint from H.S. Chang, S.K. Baek, H. Park, H. Hwang, J.H. Oh, W.S. Shin, J.H. Yeo, K.H. Hwang, S.W. Nam, H.D. Lee, C.L. Song, D.W. Moon, M.H. Cho, Electrical and physical properties of HfO2 deposited via ALD using Hf(OtBu)4 and ozone atop Al2O3, Electrochem. Solid-State Lett. 7 (2004) F42–F44.

from the poly-Si gate and suppress the formation of an interfacial layer up to an annealing temperature of 750°C [64,65]. The disadvantages of the HfxAlyO dielectric, similar to Al2O3, are its relatively low permittivity (16) [66] and the inevitable interlayer between HfxAlyO and the Si substrate [64,67], making the downscaling of the EOT difficult. The property of work function tuning makes HfxAlyO an ideal dielectric candidate for pMOS in the integration scheme using dual high-κ material, but it is definitely an unfavorable property for nMOS. This is why HfxAlyO will not find application in the single dielectric scheme in CMOS processing.

4.4.3 Hafnium lanthanate Hafnium lanthanate (HfxLayO) has recently attracted much attention as an alternative gate dielectric for NMOS. It has a relatively large dielectric constant (18–23) [37,64,68] and strong ability to tune the EWF of metal gate to the conduction band edge of the Si substrate [62,63,69–73]. Solid proof is shown in Fig. 4.24, where the VFB of HfSiON-based high-κ dielectric shifts negatively with an increase in the La doping concentration. A research work on integration for 22-nm low operation power (LOP) application has been reported using HfLaO as a high-κ dielectric [74]. As shown in Fig. 4.25,

High-κ dielectric and metal gate

89

MG

La Addition 2.0

x2 x3

0.3

−433 mV

0.4

−331 mV

1.0

−200 mV

0.5 Vt@Ns=5×1011cm−2 (V)

Si sub.

ref (w/o La) La x1

IL

Cgc (μF/cm2)

0.7 nm

HfSiON: La x1,x2,x3

0.2 0.1 0.0

0.0

0.0

1.0 Vg (V)

1.5

Fig. 4.24 The capacitance-voltage curves for different La addition into HfSiON dielectric. Reprint from J. Huang, P.D. Kirsch, D. Heh, C.Y. Kang, G. Bersuker, M. Hussain, P. Majhi, P. Sivasubramani, D.C. Gilmer, N. Goel, M.A. Quevedo-Lopez, C. Young, C.S. Park, C. Park, P.Y. Hung, J. Price, H.R. Harris, B.H. Lee, H.H. Tseng, et al., Device and reliability improvement of HfSiON + LaOx/metal gate stacks for 22 nm node application, in: IEEE International Electron Devices Meeting, 2008, pp. 1–4.

Fig. 4.25 Optimized LaOx cap process type realizes appropriate Vt and reduced Vt variation. Reprint from K. Tatsumura, T. Ishihara, S. Inumiya, K. Nakajima, A. Kaneko, M. Goto, S. Kawanaka, A. Kinoshita, Intrinsic correlation between mobility reduction and Vt shift due to interface dipole modulation in HfSiON/SiO2 stack by La or Al addition, in: IEEE International Electron Devices Meeting, 2008, pp. 1–4.

nMOSFET with the LaOx capped HfSiON/metal gate stack shows a Vt,lin  0.31 V, with good carrier mobility, acceptable interfacial state density, and within-wafer uniformity, as well as good reliability. Comparison between the devices with and without the LaO capping layer shows that the LaO capping induces a Vt shift >400 mV.

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4.0

C (mF/cm2)

3.0

HfSiON (Hf: 74%) ALD-La2O3 30 cycle 5 2 0

2.0

1.0 n-MOS 0.0 −2.0

−1.0

0.0

1.0

Vg (V)

Fig. 4.26 Capacitance-voltage curves for different thicknesses of the La2O3 capping layer on HfSiON dielectric. Reprint from J. Huang, P.D. Kirsch, D. Heh, C.Y. Kang, G. Bersuker, M. Hussain, P. Majhi, P. Sivasubramani, D.C. Gilmer, N. Goel, M.A. Quevedo-Lopez, C. Young, C.S. Park, C. Park, P.Y. Hung, J. Price, H.R. Harris, B.H. Lee, H.H. Tseng, et al., Device and reliability improvement of HfSiON + LaOx/metal gate stacks for 22 nm node application, in: IEEE International Electron Devices Meeting, 2008, pp. 1–4.

In another work [75], the effect of the LaO capping layer in a device with HfSiON/ TaSiN gate stack was studied systematically. The LaO cap layer was deposited by atomic layer deposition (ALD) at a very low growth rate (0.036 nm/cycle). Equivalent oxide thickness (EOT) of the stack is well controlled (x) SiO2

Si3N4 SiO2 Si Si1-xGex SOI sub. (B)

(A)

Poly Si Gate oxide

(C)

(D)

Fig. 5.1 Fabrication of strained SiGe channel MOSFET of high-Ge content by condensation technique [7].

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is more than 10 times compared to that of reference devices without Ge-condensation. It should be mentioned that this condensation technique is employed very commonly for obtaining SiGe channel materials with high Ge-content [4–6]. Another challenge confronted with the SiGe channel material is the relatively higher interface states density than Si, which unfortunately affects the carrier mobility in the channel. An Si capping layer was always deposited on the SiGe channel to reduce the interface density and gate leakage [8–10]. However, it is necessary to avoid the Si capping layer in order to further thin the EOT. An optimal epitaxial SiGe on Si and high-k dielectric/metal gate process is proposed. The formation of high-quality epitaxial SiGe films with optimal Ge concentration and HfSiO2 gate dielectric of improved interface quality and surface roughness is critical. The can be realized by optimizing the temperature and partial pressure during the SiGe epitaxy [11].

5.4

Ge channel

Ge channels can be deemed as the extreme case of SiGe, i.e., when the content of Ge is 100%. Except the same problems with SiGe like band-to-band tunneling leakage, the poor interface quality, and the heterogeneous epitaxy on Si, the large parasitic source/ drain resistance for nMOS arising from the low n-type dopants solubility and poor activation as well as the Fermi-level pinning at the valence band edge also hinder the performance improvement of Ge-based devices. For the heterogeneous epitaxy of Ge on Si, the most attractive approach is the direct epitaxy using a two-temperature scheme due to its relative simplicity [12–16]. In this two-temperature scheme, a first low temperature (450°C, LT) to grow a seed layer full of defects is performed. The strain will be fully relaxed within an approximately 30-nm-thick seed layer due to the generation of misfit dislocation as seen in Fig. 5.2A. Afterward, a Ge layer at high temperature (825°C, HT) is grown and is expected to be of high crystalline quality since (1) higher growth temperature leads to the annihilation of defects and dislocations associated with strain relaxation, and (2) Ge is now growing on a fully relaxed Ge “seed layer” instead of an Si substrate. Another approach of Ge heterogeneous epitaxy of Ge on Si is using the aspect ratio trapping (ART) technique [18,19]. ART begins with the growth of SiO2 on an Si Fig. 5.2 TEM images of Ge layer (A) using a two-temperature scheme [12,17] and (B) using the aspect ratio trapping technique [18].

SiO2

Ge

Ge Si sub. 200 nm

(A)

(B)

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109

substrate followed by patterning and dry etching to form trenches. Then the Ge epitaxy on Si trenches is carried out and the defects will be trapped by the SiO2 sidewall at the beginning of Ge growth. Upon some thickness, the Ge layer will be defect-free as seen in Fig. 5.2B. The aspect ratio of the trench should be >1 in order to effectively trap the defects at the bottom of trenches, thus achieving a top Ge layer free of defects [18]. Experimentally, when high-k dielectrics are deposited directly on a Ge channel, the device performance is usually poor because of a high density of defects that creates electronic states in the bandgap. High-k materials intrinsically have a higher concentration of defects compared to SiO2 due to their higher coordination number [20,21]. Bonds in high-k materials cannot relax and re-bond at defect sites. These defects, particularly those near the interface, have serious consequences for channel mobility. Charge trapped in the defect centers scatters carriers in the channel leading to a degradation of channel mobility. To address this issue, interfacial layers (ILs) such as GeON, GeAlON, GeZrO, or GeZrSiO, etc. are usually inserted between the high-k material and the channel [20–25]. The IL materials generally have a much lower dielectric constant and tend to form a higher-quality interface (fewer defects) with the Ge channel material. The reduction of defects at the interface is often called surface passivation and so these layers are also called passivation layers. The parameter most commonly employed to evaluate the quality of an interface is the interface trap density Dit which is expressed in the unit of charges per cm2-eV. DH includes interface traps, interface charge, and interface states. In addition to interface passivation, a critical role of the ILs is to separate carriers in the channel from the high-k material for some distance. This is highly desirable because high-k materials have been shown to strongly affect channel mobility, even they are not in direct contact with the channel [26]. The common passivation and high-k dielectric are shown in Table 5.2.

Common passivation and high-k dielectrics used in the Ge channel

Table 5.2

High k material SiO2 Si3N4 Al2O3 Ta2O5 TiO2 SrTiO3 ZrO2 HfO2 HfSiO4 La2O3 Y2O3 α-LaAlO3

Gap (eV) 3.9 7 9 22 80 2000 25 25 11 30 15 30

9 5.3 8.8 4.4 3.5 3.2 5.8 5.8 6.5 6 6 5.6

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A key challenge in developing Ge nMOS devices is to obtain low-resistance Ohmic contacts to n-type Ge. Low-resistance contacts are essential for the high-performance Ge nMOS. There are two obstacles for Ge nMOS to realize a good Ohmic contact, i.e., low-dopant activation and Fermi-level pinning (FLP). The typical activated concentration of P in Ge after rapid thermal processing (RTP) is approximately 5  1019 cm 3 and the high activation requires more advanced annealing tools such as microwave annealing and laser annealing. Regarding FLP, the Fermi level of Ge is usually pinned just above the valence band edge. This renders a very high Schottky barrier height to electrons which makes the realization of Ohmic contacts on n-type Ge difficult. There are a number of approaches to depin the Fermi level such as inserting an ultrathin dielectric layer between the metal and the n-type Ge. It has been demonstrated that thin potential barriers with low conduction band offset (CBO) on Ge could enable a high tunneling current. By deliberately facilitating a high tunneling current, the effective contact resistance at the junction is reduced. This is the primary mechanism behind the metal–insulator–semiconductor (MIS) contact with Ge. The insertion of thin potential barriers, such as that provided by thin layers of Al2O3 [27], Si3N4 [28], TiO2 [29,30], ZnO [31], Ge3N4 [32], GeOx [33,34], and MgO [35,36], has been shown to reduce the Schottky barrier height as well as facilitate the depinning of the Fermi level in n-type Ge. Besides the insertion of an insulator to depin the FLP, dipole formation, dopant segregation, and surface passivation are also employed to alleviate the FLP. It has been reported that the formation of a Ti-N, W-N, Ta-N dipole at the TiN-Ge interface can shift the Fermi-level upward which alleviates the FLP [37–39]. Both As- and P-dopant segregation at the NiGe/n-Ge interface were reported to depin the FLP and deliver a low Schottky barrier height of 0.1 eV to electrons [40]. Regarding the interface passivation, a lot of exotic species such as fluorine, selenium, sulfur, etc. were reported to passivate the dangling bonds at the metal/n-Ge interface, which results in the alleviation of FLP [41,42].

5.5

GeSn channel

GeSn(Si) alloys have attracted attention in both photonic and electronic applications. The original problem with such material was the high-quality epitaxial layers with high Sn content. Recent developments in CVD technique using SnCl4 as an Sn precursor have provided the possibility to integrate these GeSn(Si) as channel material in CMOS as well as quantum well materials in laser and detector structures. In principle, the presence of Sn atoms in Ge matrix creates a large amount of compressive strain therefore, the effective mass of holes in GeSn material is remarkably smaller than Ge which makes it a better choice for high-mobility channel material. Although GeSn material offers a great opportunity for strain engineering, there are still a few difficulties with integration of this material in MOSFET structures: (1) the material has to be grown at temperatures (105 cm2 V 1 s 1 at 300 K. This high mobility raised huge expectations regarding its applications in CMOS technology.

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2D materials

X-enes -Graphene, silicene, germanene -Graphene nanoribbons -Bilayer graphene

2D TMDs -MQ2: M = transition metals Q = chalcogens (S, Se, Te) -Mo-based TMDs, e.g., MoS2 -W-based TMDs. e.g., WS2, WSe2

X-anes -Graphane -Silicane -Germanane -Stanane

Fig. 5.6 Schematics showing the families of 2D materials.

Graphene is only one atomic layer but it has carrier sheet densities 1012 cm 2, which is sufficient for FET operation. Graphene is synthesized by different techniques, but the widely used technique is exfoliation [71], 6H-SiC (0001) or 4H-SiC (0001) substrates, and CVD [72,73]). In difference with the energy bands of conventional semiconductors, in graphene, the conduction band and valence band are separated from each other by a very tiny gap size. Owing to the absence, graphene MOSFETs are not able to switch off. If a positive voltage is applied to the gate, the position of the Fermi level EF(A)in the conduction band and n-type conduction occurs in the graphene channel. However, when the gate voltage is decreased, the Fermi level-moves downward, resulting in a reduction of electron density until VGS ¼ VGS(B), and the Fermi-level position is on the Dirac point. At this point, the conductivity type alters from n to p [74]. Further negative voltages (VGS(C)) to the gate causes the conductivity in the channel to become positive and the drain current increases again (ID(C)). This behavior is called ambipolar conduction [17]. This situation is entirely different in silicon as shown in Fig. 5.7C and D. At VGS(A), an n-type channel is occurred similar to the graphene transistor. Meanwhile, by decreasing the gate voltage, the Fermi level moves into the gap when the carrier density in the channel lessens until the transistor suddenly turns off. Therefore, the application of gapless graphene in logics is not optimistic. A lot of work has been done to open the bandgap of graphene and can be basically summarized as two types: (1) fabricate graphene nanoribbons (GNR) [75]; (2) grow bilayer graphene (BLG) [76]. The latter choice can be produced in a specific way, the so-called Bernal stacking, where half of one sheet is placed on the other one and the rest is located exactly above the empty center of the hexagons of the second layer [75–79]. Bernal-stacked bilayer graphene can be synthesized by CVD growth [80,81]. Although the bilayer graphene provides a gap for graphene material, the amount of gap according to theoretical calculations is limited to 150 meV [82]. BLG transistors could demonstrate a gap of 40–140 meV, which is remarkably less than the 0.4 eV limit for a good switching operation of transistors [75,76].

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E ID

Ef (A) ID(A)

Ef (B) Ef (C)

VGS (A)

ID(C)

VGS (C)

VGS(B) = VDirec k

(A)

VGS

(B) ID

E Ef (A) Ef (B) Ef (C)

ID(A) VGS(A) VGS (C) k VGS(B)

(C)

VGS

(D)

Fig. 5.7 (A) Band energy diagram of a graphene sheet, (B) I(V) of a graphene MOSFET and (C) band energy diagram of Si (D) and I(V) of an Si nMOSFET.

The situation for (top-gate and back-gate) GNR MOSFETs looks better [83–85] where the Ion/Ioff ratio improves significantly for ribbon widths less than 5 nm and it exceeds over 106 value. For these transistors, the simulations have demonstrated that edge effects can have a strong negative influence on the performance of the Ion/Ioff ratio of GNR MOSFETs [82,86,87]. Unfortunately, the mobility channel in GNR MOSFETs is dramatically decreased. For example, transistors with ribbons of 20–30 nm demonstrate a mobility value of 2–3  103 cm2 V 1 s 1; meanwhile, the transistors with a ribbons width below 5 nm show only 50–200 cm2 V 1 s 1. These mobility values show a huge degradation of the reported values for large-area graphene which is above 105 cm2 V 1 s 1. It is worth mentioning here that in graphene the hole mobility may even go beyond the electron mobility [88]. This is also shown by calculation work that effective electron and hole masses for both GNR and BLG transistors are almost similar due to the symmetry of the band structure [89,90]. The ratio of μh/μe is 0.3 for Si, 0.05 for GaAs, and 0.01 for other compound semiconductor materials, e.g., InAs and InSb.

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117

All GNR transistors demonstrate outstanding electrostatics and they are remarkably superior and immune against SCE compared to Si MOSFETs [86]. One of the genuine ideas for integration of graphene transistors in future ICs is vertical devices and not planar ones. The first vertical transistor was proposed a decade ago. In principle, the operation mechanism of these transistors is tunneling of the carrier through a thin dielectric layer. For this design, two graphene sheets are separated by a thin tunnel dielectric in a bilayer pseudospin configuration, the so-called BiSFET [91]. In this device, one graphene sheet is p-type and the other one n-type and both are electrostatically coupled to a gate forming a condensate. By applying VGp and VGn, the large resistance between the electrodes is decreased and a tunnel current is generated. At first, the tunneling current increases by increasing the potential difference between the electrodes (Vpn) to a maximum value and later decreases. The power consumption in BiSFET logic is predicted to be remarkably lower compared with Si CMOS logic [92]. A more complicated vertical transistor was proposed when the graphene sheets are separated by a BN dielectric and the stack is sandwiched between another two BN layers. The whole structure is placed on an oxidized doped Si wafer acting as the gate BiSFET [93]. The tunneling current is obtained by applying Vpn to the transistor and the amount of the tunnel current can be tuned by the gate voltage. These devices may demonstrate a high Ion/Ioff ratio, fulfilling the conditions for logic applications. Another innovative vertical transistor is the so-called graphene-based hot electron transistor. In this device, a graphene layer acts as a base layer and is sandwiched between an emitter-base and a base-collector insulator (in the terminology of bipolar transistors). The transistor is in the on/off states depending on the base-emitter voltage. In the on-state, a tunnel current can flow through the emitter-base insulator which later flows to the collector layer. Such transistors may demonstrate outstanding cutoff frequencies for RF applications [94,95]. In a short summary, although many outstanding transistors have been manufactured, more research is required to integrate graphene in future ICs and it is unlikely that graphene transistors could replace Si MOSFETs in the near future. Meanwhile, many research groups are putting in an effort to use graphene for transparent electrodes [96] and flexible and printable electronics [97,98].

5.7.2 Graphene-like channel In similar to graphene, silicene, germanene, and stanane have gapless property as well. Furthermore, synthesis of such exotic materials is a difficult task and new innovative methods have to be invented to achieve reliable growth. Thus, all these difficulties lead to the abandoning of these materials in the fabrication of transistors. The 2D TMDs and X-anes families, on the other hand, have bandgaps between 0.5 and 2.5 eV which are perfect for the fabrication of transistors. Among them, the most investigated 2D materials for potential applications in transistors are monolayer MoS2 and WSe2 for NMOS and pMOS, respectively, thanks to their intrinsic high mobility for electrons and holes (217 cm2 V 1 s 1 for electrons in MoS2 and 500 cm2 V 1 s 1

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for holes in WSe2) as well as the decent bandgap (EG ¼ 1.8 eV for MoS2 and 1.2 eV for WSe2) [99,100]. The perfect subthreshold swing of 60 mV/dec and high Ion/Ioff ration >106 can be easily accomplished. In this regard, MoS2 and WSe2 are highly desirable for use in high-performance electronics with ultralow-power consumption enabled by transistors that are optimized for subthreshold operation. In this operational regime, the on-current near the threshold voltage is governed by the subthreshold swing rather than the carrier mobility, and the use of 2D materials means a very low Ioff, which thus enables an ultra-low power design. This is particularly important for growth in Internet-of-Thing (IOT) technologies, which require low power consumption and low-cost devices. However, several challenges need to be addressed before 2D materials can be considered for practical applications in the mainstream CMOS technology. This requires comprehensive research on the development of materials and devices. In the aspect of material research, the major issue is the availability of 2D materials with sufficiently low defect densities for CMOS applications on a large scale. This requires further development of growth techniques, such as chemical vapor deposition (CVD), to fabricate 2D materials of high performance on the CMOS platform. Regarding the devices development, the mono- and few-layer 2D materials are ideal channel materials to replace Si in sub-10-nm technology. However, so far, most activities have been mainly focused on gate or channel length scaling. Beside such activities, several other issues related to improving the performance of 2D transistors should also be resolved at the same time. In short, the main challenges to be addressed are: (1) high-k dielectric of low interface density to keep the intrinsic high carrier mobility of 2D materials; (2) effective doping of source/drain regions; and (3) associate contact resistance reduction to reduce access resistance.

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Challenges in ultra-shallow junction technology

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E. Simoen*, H.H. Radamson†,‡ *Imec, Leuven, Belgium, †Institute of Microelectronics of Chinese Academy of Sciences (IMECAS), Beijing, PR China, ‡University of Chinese Academy of Sciences (UCAS), Beijing, PR China

6.1

Introduction

Source/drain (S/D) junctions are essential parts of an MOS transistor. Important dimensional parameters are the junction depth xj and the depletion width at the source and drain junction (wd and ws) as they contribute to the natural length of a MOSFET according to Eq. (2.7). This implies that the junction depth should scale along with the transistor dimensions in order to keep good control over the SCE. The junction depth is in the first instance dictated by the diffusion of the dopant atoms under the applied pffiffiffiffiffi thermal budget. In first approximation, x will be defined by the diffusion depth Dt, with D the diffusion coefficient (in cm2/s) and t the time of the diffusion treatment. As the diffusion coefficient D is thermally activated, i.e., it increases exponentially with inverse temperature, one should limit both the maximum T and also t. In other words, one should reduce the applied thermal budget by replacing a rapid thermal annealing (RTA) by spike annealing or even shorter treatments based on flash lamp or laser annealing. This will also affect the steepness of the junction, which is defined by the gradient of the doping concentration at the metallurgical junction. However, as the junction is becoming shallower, its sheet resistance Rs (Ω/sq) will increase, as illustrated in Fig. 6.1 for n-type Ge [1]. Consequently, the contact and series resistance of the junction will increase for a constant active doping concentration, due to the reduced junction depth, resulting in a degradation of the on current. This brings us to the second important parameter: the active doping concentration ND, which should increase with further device scaling. At the same time, there exists a natural upper limit for ND under thermodynamic equilibrium conditions, namely, the equilibrium solid solubility of the dopants Seq [2], which should preferably be as high as possible. Under nonequilibrium annealing conditions, it is possible to activate dopants above this limit, resulting in a metastable active concentration. This explains the interest in ultrafast ms and ns annealing schemes for the activation of shallow junctions [3]. Scaled junction processing should thus achieve two goals at the same time: limit the diffusion of the dopants during the applied thermal budget and, at the same time, activate the dopant atoms as much as possible. For the typical Group III acceptors (B, Ga, In) and Group V donors (P, As, Sb) in Si or Ge, this implies that the dopants should be placed on lattice or substitutional sites. CMOS Past, Present and Future. https://doi.org/10.1016/B978-0-08-102139-2.00006-9 Copyright © 2018 Elsevier Ltd. All rights reserved.

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Fig. 6.1 Sheet resistance versus junction depth for n-type Ge junctions, calculated for different active donor concentrations. The symbols indicate the specifications of the ITRS road map for the 17–22-nm technology node [1].

CMOS Past, Present and Future

600

400

200

0 0

20

40

60

80

Junction depth, Xi (nm)

It is the aim of this chapter to provide insight into the fundamental and technological aspects and challenges of shallow junction formation. In a first part, the basics of dopant diffusion and activation will be given. Usually, dopant diffusion is mediated by intrinsic point defects (vacancies Vs or self-interstitials I) [2,4]. Any source of excess Vs and Is beyond the equilibrium concentration will originate enhanced dopant diffusion. In other words, shallow junction control is in the firstt instance an exercise in point-defect engineering [4]. At the same time, intrinsic point defects also play a role in the activation or deactivation of the dopants, for example, by forming dopant-vacancy pairs. This will strongly depend on how the dopants are introduced in the semiconductor: by gas-phase or solid-source diffusion; by ion implantation; or by in situ doping during the epitaxial deposition of the source and drain regions. As of today, ion implantation (II) followed by a thermal annealing step to repair the damage and activate the dopants is the preferred method in the industry. The requirement of shallower junctions pushes the energy of the ions to lower values ( 950°C, resulting in perfect dislocation loops at the end of range. During TED, these EOR defects act as a source of excess interstitials, until they are completely dissolved, and hence the transient nature of the effect. The insight into the origin of TED also suggests PD engineering solutions. One could consider introducing or injecting vacancies in order to recombine with the interstitials at the EOR. Another possibility is to co-implant with another impurity like C, which is an efficient trap for interstitials through the kick-out mechanism [5]. Simulations of the diffusivity of silicon interstitials indicate a strong suppression by a small amount of C atoms [59]. This has been implemented in real shallow B junction integration schemes [60–66]. Other solutions, like using shorter anneals and faster ramp rates or the role of pre-amorphization, have also been considered (Fig. 6.10) [5].

6.3.3 Boron-interstitial clustering Evidence for the precipitation of B well below the equilibrium solid solubility limit was found more than 40 years ago [67–69]. Thermal annealing after B ion implantation usually results in a part of the B profile which remains electrically inactive and immobile, while the lower concentration part of the profile undergoes TED. The concentration threshold is one order of magnitude below the B solid solubility [69,70]. This is evidenced by the data in Fig. 6.11, representing SIMS profiles corresponding to several B doping spikes deposited by MBE and subjected to a 40 keV 5  1013 at/cm2 silicon implantation, followed by an anneal at 790°C for 10 min. This introduces excess interstitials, with a profile shown in the lower panel of Fig. 6.11 and calculated by the MARLOWE code [71]. It was proposed that the mechanism responsible for the B immobilization through the formation of boroninterstitial clusters (BICs) is the same as for B TED, namely, the local supersaturation of Is [70]. This is also demonstrated by the results of Fig. 6.11: the spikes closer to the silicon surface and subjected to a higher density of implantation-induced interstitials

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Fig. 6.10 Steady-state effective diffusivity of Si interstitials in the presence of different carbon concentrations. The top line represented by 10 2exp(0.9 eV/kBT) is the diffusivity for a sample free of carbon. The other straight lines are fits to simulated data [59].

As deposited 40 keV Si, 5 × 1013 cm–2, 790⬚C, 10 min

1019 1018 Concentration (cm–3)

Fig. 6.11 Chemical profiles of a B multidelta structure grown by MBE and implanted with Si ions in the shallower region (upper panel). Thermal annealing at 790°C induces the B TED in all the spikes, while the BIC formation causing the immobile peaks occurs only in the shallower regions. The lower panel reports the simulations of the Is distribution after implantation and the deconvolution of the B profiles in mobile and immobile fractions [71].

1017 Si interestitial (MARLOWE) Experimental data Mobile B Immobile B

1020 1019 1018 1017 0

2000

4000

6000

Depth (Å)

experience less broadening by TED and show an immobile B peak [71]. Deeper in the substrate, the B spikes mainly experience TED and no B clustering by BIC formation. While the immobilization of B by clustering appears at first sight positive, since it takes away interstitials from participating in TED, it has also the drawback of reducing

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the electrically active fraction of B. Moreover, while they act as a trap for interstitials at shorter annealing times, they can operate as a moderate I source for longer times by cluster dissolution [72–74], thus contributing to TED. In summary, the nonequilibrium clustering of B induced by the supersaturation of Is results in B:Si complexes (BICs) which are electrically inactive and whose size and thermal stability depends on the starting conditions [6]. In addition, BICs have a profound impact on the migration properties of B atoms by changing both the fraction of mobile B and the density of Is. These B-I clusters should thus be carefully considered when modeling the B diffusion process and its sheet resistance.

6.4

N-type diffusion in germanium

The issues of shallow n-type junction formation in germanium are illustrated by Fig. 6.12, showing the SIMS profiles of a 15 keV 5  1015 at/cm3 P implantation in a p-type substrate [75]. As-implanted profiles are compared with the ones after an RTA at 500°C for 30, 60, or 120 s. After annealing, box-like profiles are obtained, which point to a concentration-dependent enhanced diffusion, which drops off steeply for [P]  2  1019 cm 3. For lower implantation doses, no such enhanced diffusion, resulting in deep junctions, has been observed [76]. Compared with electrical measurements obtained by spreading resistance probing (SRP), a maximum active level of about 5  1019 cm 3 has been obtained, well below the maximum solid solubility of around 2  1020 cm 3 for P in Ge. Above the solubility limit, peaks are found in the profile, corresponding to an inactive fraction of clustered P. This clearly demonstrates that it is difficult to achieve shallow, steep n+ profiles in Ge, with an active

As-imp 500°C, 30 s

Concentration (at/cm3)

1021

500°C, 60 s Solid solubility limit

1020 Maximum carrier concentration

500°C, 120 s

Extrinsic diffusion

1019 Intrinsic diffusion 1018 0

20

40

60 Depth (nm)

80

100

Fig. 6.12 SIMS profiles of P, implanted in p-type Ge with an energy of 15 keV and a dose of 5  1015 at/cm2. Profiles are shown as-implanted and after an RTA at 500°C under N2 for 30, 60, or 120 s [75].

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concentration approaching 1  1020 cm 3 by standard ion implantation and RTA [75–80]. It is the aim of this part to first provide insight into the diffusion mechanism of n-type dopants in Ge. Next, possible solutions to this problem will be discussed. These largely rely on vacancy engineering schemes, using co-implants. Alternatively, one can consider making use of the EOR interstitial clusters to recombine the excess vacancies. As will be seen, in order to meet both requirements of a shallow junction, which is highly activated, one has to combine these techniques with nonstandard, fast annealing.

6.4.1 Diffusion mechanism of n-type dopants in Ge In n-type Ge, the double negatively charged vacancy is the dominant intrinsic point defect as it has the lowest formation energy [2]. It is therefore a good first-order approximation to describe the extrinsic diffusion of donors X in terms of a single negatively charged X-V pair, i.e., [7]: XV

1

, Xs 1 + + V 2

(6.11)

The concentration of the V2 species will depend on the Fermi level at the annealing temperature, which thus depends on the active dopant concentration. For intrinsic germanium, the Fermi level will be close to mid gap and there will be a negligible [V2 ]. In that case, intrinsic diffusion conditions prevail for P. As or Sb, as studied by Brotzmann and Bracht [7]. The corresponding diffusivities are summarized in Table 6.1, showing that P is the favorable donor impurity, corresponding to the lowest intrinsic diffusivity. Assuming that enhanced diffusion is mainly assisted by double negatively charged vacancies, one can express the extrinsic diffusivity as [2,7] 1+ DXe ðnm Þ ¼ DXV

Table 6.1

XV 0 nm

+D

ni

XV 1

+D

 2  3 nm nm XV 2 +D ni ni

(6.12)

Parameters for the intrinsic diffusivity of donor impurities

in Ge Donor

H (eV)

D0 (cm2/s)

P As Sb

2.85 2.71 2.55

9.1 32 16.7

After S. Brotzmann, H. Bracht, Intrinsic and extrinsic diffusion of phosphorus, arsenic, and antimony in germanium, J. Appl. Phys. 103 (2008) 033508/1–7.

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With nm the maximum free electron concentration at the diffusion temperature. For nm ¼ni, the extrinsic diffusion coefficient reduces to the intrinsic one, given by [2,7] 1+

0

1

XV DXV + DXV + DXV + DXV i ¼D

2

(6.13)

In practice, it has been shown that the XV1 contribution dominates so that to a good approximation one can rewrite Eq. (6.12) as [2,7] DXe ðnm Þ  DXV

1

(6.14)

The enhancement of the diffusivity in the extrinsic regime, as a function of the free electron concentration (active P level), is calculated in Fig. 6.13 for different temperatures and an RTA time of 1 min [1]. For low T, the diffusion length increases proportionally with nm2, while at 750°C this increase only occurs when nm rises above ni, which increases exponentially with 1/T. This is shown in Fig. 6.14, considering the different available values for ni in Ge as a function of T [7,82]. It also illustrates nicely the opposite requirements of both a shallow n+ junction at a high active level: increasing the doping concentration at the same time increases the extrinsic diffusivity, by increasing the equilibrium V2 concentration. Note also that the formed XV1 pairs behave as acceptors and thus take away two free electrons per dopant atom, corresponding to the two-state of the vacancy. All these factors contribute to the deactivation of the n+ layer in Ge [83–85]. It also forms the first step toward a further clustering/deactivation of donors in Ge by the formation of XnVm complexes [84]. On top of that, ion implantation usually creates excess vacancies which act as a further source for enhanced donor diffusion in Ge. However, it has been shown that the experimentally observed TED by implantation-induced excess vacancies is less than expected [82], implying a significant recombination/capture or out-diffusion

Diffusion length, t = 1min (nm)

100

Fig. 6.13 Calculated diffusion length at different RTA temperatures and 1 min anneal, as a function of the active doping concentration, calculated from the extrinsic diffusion coefficient of Eq. (6.14) [1].

750∞C 10 700∞C 650∞C 600∞C 1 550∞C 500∞C 0.1 450∞C 0.01

400∞C 350∞C

0.001 0.0001 1018

Phosphorus

1019 1020 Concentration (cm−3)

1021

142

1020 Critical carrier concentration (cm-3)

Fig. 6.14 Critical carrier concentration as a function of temperature in n-type Ge defining the boundary between intrinsic and extrinsic diffusion of donor atoms. The data points are diffusion coefficients derived by Matsumoto and Niimi [81].

CMOS Past, Present and Future

Ref. [81] 2ni

1019 Extrinsic diffusion (n>ni )

ni

1018

Intrinsic 17

10

600

700

800 900 1000 Temperature (K)

1100

of the excess vacancies. This opens the path for point-defect engineering to control the dopant diffusion. It has also been demonstrated that the leveling off of the active level at about 5  1019 cm 3 [75–80] can be explained in first order by considering the pairing of donor atoms with V2 [82].

6.4.2 N-type dopant control in Ge by co-implantation In order to fabricate highly activated shallow n+ junctions in Ge, one has to do something about the vacancies. A straightforward but far from simple method to implement is by co-implantation with an efficient vacancy trap. According to ab initio DFT calculations, the strongest binding exists between F and vacancies [86]. This has triggered quite some experimental work to validate this idea [87–94]. In the case of As implantation in Ge, it was shown that a co-implant with F enriches the Ge matrix with vacancies, causing an enhanced diffusion of As within the layer amorphized by both F and As [88]. At the same time, the activation of As was enhanced for temperatures below 450°C [90]. This has been validated by positron annihilation lifetime spectroscopy (PALS) [92]. PALS is a technique which is sensitive to open volume (vacancy-related) defects in a crystalline matrix. The presence of fluorine was shown to enrich the germanium matrix with various types of vacancy-like clusters. A further observation is that F segregates at the moving amorphous/crystalline interface, leading to a pronounced retardation of the solid-phase-epitaxial regrowth (SPER) [91]. In addition, F aggregates at the EOR damage region, significantly enhancing the stability of this damage. In the case of P in Ge, some diffusion retardation has been found at lower annealing temperatures (400°C) [93]. However, as most of the implanted F out-diffused, the thermal window for the beneficial impact of F co-implantation is rather narrow (400–450°C), so that it has only limited practical use.

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Another candidate co-implant impurity is nitrogen [3,95–98]. A strong suppression of the P diffusion has been reported [3]. At the same time, the degree of activation was found to be lower [98], possibly due to the formation of P-N (or GeNx) complexes. There is also a debate on the exact diffusion retardation mechanisms. While DFT calculations support the idea of vacancy trapping by N [99], recent experimental evidence points in another direction [97]. This is based on the observation of a “kink” in the SIMS profile of nitrogen at the original a/c interface, indicating an interaction of N atoms with the Ge self-interstitials at the EOR. This suggests the formation of NxIy clusters, which stabilize the presence of excess interstitials at the initial annealing stages, which later on act as a source of Is, recombining with excess vacancies and thus responsible for the slower P diffusion [97]. According to theory, other group IV impurities like C and Sn also interact with vacancies in Ge [100–102]. Experiments with P + C co-implantations have shown some retarding impact on the diffusion of donors [103–105]. A detailed study has been undertaken in Ref. [103], with some of the key results displayed in Fig. 6.15. It represents the SIMS profiles after a Ge Pre-Amorphization Implant (PAI) at a 20keV and Fig. 6.15 Contribution of carbon co-implantation to phosphorus diffusion in germanium. (A) P SIMS profiles at various C co-implant energies after annealing (the carbon dose is 1  1015 at/cm2). (B) C distribution in Ge after annealing. The a/c interface is indicated by the vertical dashed lines. It is approximately 34 nm, except for the 15 keV C case, where it increases to 41 nm [106].

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6  1014 at/cm2 dose, followed by a C implantation at different energies, going from 3 to 20 keV and doses varying from 5  1014 at/cm2 to 2  1015 at/cm2. At 3 keV, the C profile is completely contained inside the amorphous Ge region, as shown by SRIM simulations, while for 8 and 15 keV the C profile straddles the a/c interface. Next, P was implanted at an energy of 5 keV and a dose of 2  1015 at/cm2. This places the P profile inside the a-Ge region and minimizes channeling effects. RTP was performed in N2 at 600°C for 60 s [106]. During annealing, a 20nm thick SiO2 layer deposited by plasmaenhanced CVD (PECVD) was present, to prevent out-diffusion of P dopants. One can clearly observe in Fig. 6.15 that the P diffusion depth is significantly reduced with C co-implantation. The shallowest profile is found for the 8 keV C implantation, resulting in a junction depth of around 55 nm, while the P-only profile is situated at about 110 nm. However, when considering the extrinsic diffusivity of P at 600°C for 1 min in Fig. 6.13, a diffusion depth of around 20 nm is derived, which is about the observed displacement of the 8 keV profile with respect to the as-implanted one. This indicates that while the C atoms somehow interact with the ionimplantation-induced excess vacancies beyond the a/c interface, it does not affect the equilibrium excess vacancies created by the high carrier concentration at the annealing temperature, indicating that further process optimization is required to use C co-implantation as a useful diffusion control technique. Another concern is also to maintain a high level of dopant activation (or even to enhance it), which is not that obvious, as the formation of XiVjCk clusters drives the deactivation. In the case of Fig. 6.15, it was found that for a not too high C dose (1  1015 at/cm2), activation was preserved or even slightly improved [106]. The binding energy between a donor atom and V in Ge increases going from P, over As to Sb [107,108]. This implies that Sb is a more efficient vacancy trap than P, so that co-implantation of two different donor species in Ge shows potential for diffusion control. This has been confirmed experimentally [109–113], showing favorable junction characteristics and even activation over the 1  1020 cm 3 level for P + Sb co-implants [110,111]. Owing to the high active level, improved contact resistivity for NiGe/Ge contacts has been achieved [113]. As mentioned before, one way to reduce dopant diffusion and possibly achieve nonequilibrium activation is by applying ultrashort annealing, relying on, for example, flash-lamp annealing [114] or laser annealing [115–128]. A combination of ultrashort annealing with co-implantation should yield the best of both worlds, as shown by the case of C + P co-implants in combination with low-temperature microwave annealing [3]. However, it has been observed that laser annealing brings about its specific defect related problems [129–132], among others the interaction between dopants and oxygen, causing deactivation and thus requires a careful fine-tuning of the process conditions.

6.4.3 Point defect engineering While in the previous section diffusion control was targeted by the trapping of vacancies by other impurities or dopant atoms, one can also try to recombine them with self-interstitials. This principle has been demonstrated by performing simultaneous

Challenges in ultra-shallow junction technology

145

Fig. 6.16 Schematic representation of a two-step annealing sequence for performing vacancy control by recombination with EOR-injected self-interstitials. First, an implantation is performed amorphizing the Ge over a certain depth. In a low-T annealing step (350°C, 30 min), the a-Ge layer is recrystallized by SPER. In the following RTA step, dopants are activated and vacancies recombine with the interstitials injected from the dissolving EOR clusters.

annealing and irradiation [133–135]. The proton irradiation provides a source of excess interstitials to recombine with the vacancies in Ge. While this is a valid proof of concept, more practical methods could rely on the reservoir of self-interstitials present at the EOR after an amorphizing implantation. The principle is sketched in Fig. 6.16 [3] and consists of a two-step annealing sequence. In a first low-temperature step, e.g., 350°C for 30 min, the a-Ge layer is recrystallized by SPER and the EOR damage clusters are formed. In a next high-temperature step (50°C), the dopants are further activated and the damage repaired. The interstitial clusters at the EOR region will dissolve, injecting Is to recombine with excess vacancies. This should retard the P-V diffusion and yield shallower junctions. The first question to address is whether such EOR defects form in Ge and what about their thermal stability? EOR damage clusters and defects have indeed been found in amorphized Ge after annealing [136–139], the same as in silicon, although their thermal stability is lower, dissolving between 450°C and 550°C [136] or 600°C [138]. The proximity of the surface is shown to play a decisive role in their annealing [139]: the defects closer to the surface are less stable and dissolve faster. They are shown to cause a deactivation of B in Ge when dissolving at 400°C [140]. At the same time, the damage clusters can be stabilized by the presence of impurities like F [91] or N [97]. One can thus devise annealing strategies like in Fig. 6.16 to exploit the interstitial reservoir at the EOR region for diffusion control of n-type dopants in Ge. Unfortunately, first attempts based on a two-step annealing have been unsuccessful so far [3]. An interesting observation is represented in Fig. 6.17, comparing SIMS profiles for P after either room temperature (RT) or a high-T (350°C or 400°C) implantation, followed by an activation anneal at 500°C for 60 s in N2 [140]. No box-like diffusion profile is found and the profile after annealing overlaps at larger depths with the as-implanted profile. This indicates a suppression of the concentrationenhanced diffusion for the high-T implanted case compared with RT implantations.

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CMOS Past, Present and Future

1021

Concentration (cm−3)

Fig. 6.17 SIMS profiles for P after activation annealing (500°C, 1 min, N2) following a 18 keV 1  1015 at/cm2 implantation at 350°C (sample B) or 400°C (sample C) for 6 min [140a].

Sample C (as implanted) Sample B (post annealing) Sample C (post annealing)

1020

1019

1018 0

20

40

60 80 Depth (nm)

100

120

Shallower profiles have been obtained for the 350°C P implantation, indicating some enhanced channeling at a higher implantation temperature [140]. This is related to the fact that only a few nm of the Ge layer become amorphized due to the dynamic damage annealing. At the same time, a peak in the P concentration is observed in Fig. 6.17 approximately at the EOR. Cross-sectional TEM reveals the presence of a large density of extended defects at that position. This indicates that while high-T implantations avoid amorphization of the Ge substrate, at the same time, interstitial clusters are formed at the position where one would normally expect the a/c interface for a RT amorphizing implantation. These EOR clusters can next be exploited during a following RTA step to counteract the excess vacancies and limit the diffusion of n-type dopants in Ge. Combining a high-temperature P implantation (10 keV at 1  1015 at/cm2 and 150°C) with two-step microwave annealing has yielded high dopant activation and almost no P diffusion [141], highlighting the advantage of advanced implantation and annealing schemes. The impact of the As ion implantation temperature in Ge n the n+ junction profile and activation has been studied in a broad range ( 100°C to 400°C) showing optimal activation for the 50°C implanted samples [142]. This is, among others, related to the better control of the residual defects after activation at 600°C, which usually have an acceptor character and compensate the P active concentration.

6.5

Summary and outlook

Scaling of CMOS technologies, whether Si- or high-mobility-channel based, requires a reduction of the junction depth, in order to control the SCEs. At the same time, the sheet resistance should be kept as small as possible in order to reduce series and contact resistances. In other words, the diffusion of the dopants should be controlled and the degree of activation maximized. These are in some way conflicting requirements, when relying on a traditional ion implantation and annealing scheme. The junction depth can be controlled by implanting at sub-1 keV energy and/or by using heavier

Challenges in ultra-shallow junction technology

147

clusters. In addition, the thermal budget should be reduced—either by lowering the substrate temperature (microwave and flash-lamp annealing) or by reducing the annealing time (laser melt annealing). However, the thermal budget should be sufficiently long to enable recrystallization of the amorphized region and sufficient removal of the point defect complexes. The latter is important from a viewpoint of the fabrication of low-leakage junctions and, at the same time, is also beneficial for the sheet resistance, as most of the ion-implantation-induced point defects and complexes introduce deep levels, which compensate the shallow dopant concentration. Other aspects which have not been covered here include the requirement of conformal doping, which becomes critical for fin-type architectures and requires adaptation of the ion implantation (angle, rotation) or even alternative doping schemes. In addition, when moving to a nanowire technology, where the diameter of the device becomes of the same order as the radius of the ground state wave function of the dopant atoms, dielectric screening effects may have a pronounced impact on the activity of the dopants. All these issues render a junctionless approach quite attractive for end-of-the road map CMOS solutions. It is also evident that as long as ion implantation is going to be used for ultrashallow junctions, point defect engineering will become more and more important. This first of all requires a good insight into the fundamental diffusion mechanisms of dopants and the role played by intrinsic point defects. While over the years a good insight has been acquired, it is expected that for future nanoscale technologies further studies are needed, as the increasing role of the surface (interface) will impact on the equilibrium concentrations of Vs and Is and how they affect dopant diffusion and activation. DFT calculations can be very helpful in providing insight, since it becomes more and more challenging to assess experimentally the essential parameters of ultra-shallow junctions. Metrology of the electrical activity becomes very challenging and continuous developments take place to keep pace with the device scaling.

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[116] W.B. Chen, C.H. Wu, B.S. Shie, A. Chin, Gate-first TaN/La2O3/SiO2/Ge n-MOSFETs using laser annealing, IEEE Electron Device Lett. 31 (2010) 1184–1186. [117] G. Thareja, J. Liang, S. Chopra, B. Adams, N. Patil, S.-L. Cheng, A. Nainani, E. Tasyurek, Y. Kim, S. Moffatt, R. Brennan, J. McVittie, T. Kamins, K. Saraswat, Y. Nishi, in: High performance germanium N-MOSFET with antimony dopant activation beyond 1 1020 cm 3, IEDM Tech. Dig., The IEEE, New York, 2010, pp. 245–248. [118] W.B. Chen, B.S. Shie, A. Chin, K.C. Hsu, C.C. Chi, in: Higher κ metal-gate/high-κ/Ge n-MOSFETs with 30 μm in this case, Lt is in the magnitude of 0.1 μm when ρc is 10 Ω cm2), Rt can be calculated according to [12] R t ¼ R e + Rp

8

(7.4) 



 r i + Sm 1 1 ln + + Lt r i r i + Sm ri

Re ¼

Rs X9 i¼0 2π

Rp ¼


 Rm X9 ri Lt ln i¼1 2π r i Ss + L t

(7.5)

(7.6)

where Rm is easily derived by the four-probe measurement. Ignoring Lt, the Rp is calculated using Eq. (7.6). Parameters Rs and Lt can be extracted by fitting a set of Rt vs. Sm data using Eqs. (7.4)–(7.6). This fitting of Rt vs. Sm can be assisted by softwares, such as Matlab or Excel. The ρc is determined using: ρ c ¼ R s  Lt 2

(7.7)

In the normal CTLM structure, the similar fitting of Rt vs. Sm also leads to the extraction of Rs and Lt. The ρc is also calculated using Eq. (7.7).The following is to explain the advantages of MR-CTLM over CTLM. For the CTLM structure, the extracted nominal contact resistance Rc is approximated by the Lump model [13]: Rc ¼ Rs Lt coth ðLc =Lt Þ + Rm ðLc

Lt Þ

(7.8)

Nowadays, for the typical processing conditions in Ohmic contacts, Rs  100 Ω/□ and ρc  10 8 Ω cm2 lead to the Lt  0.1 μm. On the other hand, Lc is usually a few micrometers. Since Lc ≫ Lt, Eq. (7.8) can be simplified to Rc ¼ Rs Lt + Rm Lc

(7.9)

where RsLt is the effective contact resistance, RmLc stands for the parasitic metal resistance, and the RmLc/RsLt ratio indicates how the parasitic metal resistance affects the accurate ρc extraction. This ratio should be far below 1 in order to have a sensitive and accurate measurement. Taking the typical parameters, for instance, in large-scale CTLM: Rs ¼ 100 Ω/□, Lt ¼ 0.1 μm, Rm ¼ 0.3 Ω/□, and Lc ¼ 50 μm, the RmLc/RsLt is calculated to be 1.5, which is quite large. Of course, the voltage sensing probes P2 and P3 can be placed closer to the ring edges to reduce Lc, but this requires a high precision of probe placement for every measurement. This unfortunately results in large ρc variations, especially when extracting low ρc around 1  10 8 Ω cm2. For the MR-CTLM structure, the Rp/Re ratio, similar to the RmLc/RsLt ratio in the CTLM structure, is an indicator as to how the parasitic metal resistance affects the accurate extraction of ρc. This ratio should also be far below 1. Taking the typical parameters for instance: Rm ¼ 0.3 Ω/□, Rs ¼ 100 Ω/□, Sm ¼ 1 μm, Ss ¼ 10 μm, and Lt ¼ 0.1 μm, the Rp/Re ratio is calculated to be 0.022. Compared with the large

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RmLc/RsLt ratio in CTLM, this extremely small ratio illustrates the superior advantages of MR-CTLM over CTLM structures for suppressing the proportion of parasitic metal resistance in the extracted nominal resistance. For the design of MR-CTLM structures, in consideration of minimizing the Rp/Re ratio to perform an even accurate ρc extraction, the following parameters can still be manipulated: (1) smaller Rm value by depositing a thick metal layer; (2) smaller Ss; (3) smaller r0, caution should be exercised in placing two probes in the smaller inner circle; and (4) more CTLMs in series. Other advantages of the MR-CTLM structure, such as (1) a simple process which requires only one lithography (contact mask), (2) large Re leads to reduced variance of ρc extraction and to improve measurement efficiency, and (3) large Re/Rp ratio alleviates the rigorous requirement for precise probe placement in every measurement, place it a highly appealing and feasible test vehicle for the exaction of extremely low ρc.

7.2.2 RTLM structure The TLM and RTLM test structures are schematically shown in Fig. 7.4A and B [14]. Although the appearances are different for them, the basic idea in extracting ρc accurately is similar. As seen, for both structures, the current flows through the outer two contacts (P1 and P4) and the inner two probes (P2 and P3) detect the voltage drop between two contacts with various contact spacings (d). For contacts with contact length L  1.5 Lt (always valid for CMOS nowadays since L is typically 100 μm and Lt is 0.1 μm), the measured total resistance (Rt) between the inner two contacts is [14] Rt ¼

Rs ðd + Lt Þ w

(7.10)

P1 I Rt

w P2 Lc

L

P4

V

Lc

d

Lc

P2 Slope =

I

P3

Rs w

L

w V P1

(A)

d1

d2

P3

P4

d3

(B)

2Rc

(C)

Lt

Fig. 7.4 Test structures of (A) TLM and (B) RTLM. (C) A plot of Rt vs. d for both TLM and RTLM structures.

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The Rt is measured for various contact spacings and plotted vs. d as shown in Fig. 7.4C. Three parameters, that is, Rs, Lt, and Rc, can be extracted from this plot. Knowing Rs and Lt, the specific contact resistivity ρc can be determined using Eq. (7.7). The advantage of RTLM compared with TLM structures relies in significantly reduced Lc. Taking the typical parameters, for instance, Rs ¼ 100 Ω/□, Lt ¼ 0.1 μm, Rm ¼ 0.3 Ω/□, and Lc ¼ 20 μm for normal TLM structure and Rs ¼ 100 Ω/□, Lt ¼ 0.1 μm, Rm ¼ 0.3 Ω/□, and Lc ¼ 2 μm for RTLM, the RmLc/RsLt ratios are 0.6 and 0.06 for TLM and RTLM structures, respectively. The much smaller RmLc/RsLt ratio for RTLM structures guarantees the accurate and reliable ρc extraction. Except for reduced Lc, the contact spacings d in RTLM are usually much smaller than those used in TLM structures and this improves the portion of contact resistance Rc in the measured total resistance Rt in Eq. (7.10). Consequently, the small variation in the resistance of diffusion layer does not cause large deviation of extracted ρc. For RTLM structures, practical comments for further improving the accuracy and sensitivity in ρc extraction are: (1) smaller d values and (2) smaller Lc. Although smaller d helps in achieving a larger portion of Rc in Rt and smaller Lc suppresses the effect of parasitic metal resistance in measured Rc, their variations due to lithography and dry etching processes may, however, give rise to large uncertainties of extracted ρc values.

7.3

Ohmic contacts on Si/SiGe substrate

Si is the prevailing channel material for CMOS technology; however, SiGe is extensively employed by selectively epitaxial growth (SEG) in the source/drain regions to exert compressive strain on p-type MOSFETs as well as to reduce the source/drain sheet resistance. As a result, the Ohmic contacts on Si/SiGe in the source/drain regions are of paramount importance in reducing the parasitic source/drain resistance. Although there are numerous publications in forming good Ohmic contacts between different silicides/metals and Si/SiGe substrates, their strategies can be summarized into two main categories: (1) reduce the SBHs by Fermi-level depinning using the metal-insulator-semiconductor (MIS) method, interface passivation, dopant segregation, and alloying and (2) increase the doping concentration at the surface of the Si/SiGe substrate using advanced annealing tools or alternative methods. In the following section, the discussions on Ohmic contacts on Si/SiGe will mainly focus on these two categories.

7.3.1 Modulation of SBHs on Si/SiGe substrate If one wants to alleviate the Fermi-level pinning (FLP) for contacts between Si/SiGe and Ge/III-V semiconductors, the origins or the causes of FLP should be figured out first. According to Ref. [15], the FLP for metal/semiconductor contacts has been argued over a long period. There are two main origins of FLP: one, metal-induced gap states (MIGS), and the other, interface states of semiconductors. In Fig. 7.5A,

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Fig. 7.5 Schematic band diagram of (A) MIGS, (B) surface states pinning the Fermi level close to ECNL, and (C) nearly unaltered SBH for different metals contacting with n-Ge showing the strong FLP [17,18].

MIGS are evanescent states in the semiconductor0 s bandgap, which are caused by the decay of free-traveling electron waves from the metal. In Fig. 7.5B, the interface states, on the other hand, are caused by the surface covalent bonds of a semiconductor with unpaired electrons, such as dangling bonds. Besides, when the semiconductor surface is exposed to the air, it will absorb H2O, O2, CO2, etc. to form the native oxide and cause interface states. The MIGS and/or interface states pin the Fermi level close to the charge neutral level (ϕ0, ECNL), implying the SBH independent of the metal work function, as demonstrated in Fig. 7.5C. MIGS are considered to be an intrinsic mechanism, whereas the interface states are usually discussed as an extrinsic mechanism. Obviously, in order to realize Ohmic contact on the semiconductor substrate, the depinning of the Fermi level thus reducing the SBHs is one important concern. In accordance with these two origins, the methods proposed to alleviate FLP can be summarized into four categories: (1) metal-insulator-semiconductor (MIS), (2) interface passivation, (3) dopant segregation, and (4) alloying method. For MIS, the basic idea is to employ an insulator layer to block the penetration of free-traveling electron waves into a semiconductor, which leads to the depinning of the Fermi level. For interface passivation, exotic atoms such as chalcogens and halogens are usually used to passivate the dangling bonds of the semiconductor, thus alleviating the FLP. For dopant segregation, impurity dopants such as B, In, P, and As were introduced at the interface between silicide (germanide) and Si/SiGe or Ge. The segregated dopants result in strong energy band bending, which shifts the Fermi level toward the band edge. For the alloying method, Ni alloying with metals of different work functions is used to tune the SBH for silicides/semiconductor contacts. It should be pointed out that these three methods can work synergistically instead of independently to depin the Fermi level. For example, both the passivation of interface states and the formation of the Si―S or Ge―S dipole employing sulfur passivation leads to the depinning of the Fermi level [16]. In the following section, the modulation of SBHs using these aforementioned methods are reviewed.

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7.3.1.1 MIS method Insulators such as Si3N4, TiO2, AlOx, ZnO, and NiO have been successfully applied to Si to modulate SBH. Si3N4 is one option for the insulator between metals and Si to depin the Fermi level. Connelly et al. [19,20] inserted an ultrathin Si3N4 layer between a wide range of low work function metals (Al, Mg, Er, Yb) and n-Si. Si3N4 layers were grown with a low-energy N source at elevated temperatures in an ultrahigh vacuum (UHV) chamber, and the metals were deposited in situ. The lowest contact resistance was obtained at a properly grown time so that the Si3N4 layer of proper thickness could block MIGS effectively but not increase the tunneling resistance. The achieved results showed that on-state current with MIS contact was drastically increased compared with MS contact, and that the device performance using Mg as the contact metal was better than that using other metals, which was probably due to the optimal thickness and uniformity of the interfacial layer. Using the Si3N4 insulator layer, the low SBH to electrons (ϕbn) of 0.2 eV was realized. In Ref. [21], Grupp et al. also reported that an ultrathin SiNx is introduced at the Mg/n-Si interface to modulate the SBH by alleviating the FLP, and that the ϕbn was reduced from 0.38 to 0.16 eV. A thin layer of AlOx was reported by King et al. to alleviate the FLP on Si [22]. AlOx of thickness 1–2 nm was deposited at 120°C on Si substrates by ALD deposition, forming Ni/AlOx/Si contacts. It was found that the insertion of 1.5-nm-thick AlOx already showed the depinning of the Fermi level by reducing interface states. Effective SBH reductions of 30% (from 0.57 to 0.43 eV) and 20% (from 0.56 to 0.45 eV) were obtained for n-type and p-type MIS contacts, respectively. Wang et al. also used the Al2O3 insulator layer to reduce the mid-gap trap states of Si from 3.45  1011 cm 2/eV to 1.495  1011 cm 2/eV [23]. The FLP for p-Si can be altered by the introduction of a thin NiO layer [24]. NiO of ˚ thickness was deposited on a moderately doped (1016 cm 3) p-type Si wafer 26 A using a radio frequency (RF) magnetron sputtering from an NiO target. In order to compare the SBHs of different metals with and without the presence of NiO, three different metals (Al/Mo/Pt) were deposited. It was shown that for low work function metals like Al, the SBH to holes (ϕbp) increases with the insertion of NiO, whereas for large work function metals like Pt, the ϕbp decreases. It indicates that the inserted NiO alleviates the FLP and tunes SBHs effectively according to the metal work function. In particular, since NiO has proved to be a promising interfacial layer to lower the ϕbp for the contacts between p-Si and metals of large metal work functions, Ni of large work function may be an alternative metal to Pt. For the Pt/NiO/p-Si contact, the SBH to holes (ϕbp) can be reduced to less than 0.1 eV. For the MIS contact, it is known that the total resistance of MIS contact can be split into three key parts: (1) Rtunnel, the tunneling resistance determined by the thickness of the insulator; (2) RTE, the resistance associated with thermionic barrier height; and (3) RIns, the resistance originating from the scattering of emitted electrons after thermionic emission in the insulator [25,26]. The total resistance in MIS contact is a result of competition between a thicker tunnel barrier and a lower thermionic barrier. In other words, the overall resistance of MIS contact depends not only on the depinning of the Fermi level, but also on the tunneling resistance from the insulators. For more

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effective depinning of the Fermi level (thus lower RTF), a more thicker insulator layer is favored, but this unfortunately leads to drastically increased Rtunnel. For different insulators in the MIS contacts, there is an optimal thickness to get the lowest total resistance and this depends strongly on the so-called conduction band offset (CBO) to Si. For the aforementioned Si3N4, AlOx, and NiO insulators with large CBO, the optimal thickness is so small that the depinning of the Fermi level is not significant. As a result, in order to realize an MIS contact with effective depinning of the Fermi level as well as decent total resistance, insulators with low CBO such as TiO2, ZnO, etc. to Si are highly desired. In Ref. [27], Agrawal et al. formed MIS contacts by depositing different metal (Mo, ˚ interfacial TiO2. From the achieved I-V charPt, Ni, Ti) on n-Si with and without 10-A acteristics, without TiO2, negligible changes in the reverse current density were ˚ interfacial observed with varying metal work functions. However, when the 10-A TiO2 was inserted, the reversed current was improved significantly and changed obviously with varying metal work functions. These results indicate that the current for MIS contacts without TiO2 is preliminarily limited by the pinned large ϕbn, and ˚ TiO2 leads to reduced ϕbn by alleviating the FLP effectively. the introduction of 10 A Furthermore, a low ϕbn value of 0.15 eV and a pinning factor of 0.075 (from 0.24 for ˚ TiO2/n-Si MIS contact Ti/n-Si contacts without TiO2) were reported for the Ti/10 A in this work. It is also pointed out in this work that low effective barrier heights, high substrate doping, and high conductivity interfacial layers are identified as key requirements to obtain low-specific contact resistivity for MIS contacts. TiO2 has also been commonly investigated by various groups to lower the ϕbn values by alleviating FLP; for example, ϕbn values of 0.28 and 0.21 eV for Ti/TiOx(1 nm)/n-Si and Yb/Ti/ ˚ TiOx(1 nm)/n-Si, respectively, were accomplished in Ref. [28]. The insertion of 15 A between Zr and n-Si leads to the improvement of drive current by 92% due to lower ϕbn in Ref. [29]. ZnO, another kind of insulator with small CBO to Si, was also employed to alleviate the FLP on n-Si. Paramahans et al. [30] imposed an n+-ZnO highly doped interfacial layer between Ti and the n-Si contact. The insertion of ZnO delivers a significant increase in current density (1000 ) and converts the contacts from rectifying to Ohmic behavior. It is worth noting that like TiO2, ZnO is a suitable candidate for the interfacial layer to realize low-resistance n-type Ohmic contacts due to good conduction band alignment between ZnO and Si/Ge, as well as the high n-type doping possible in ZnO by thermal annealing [30].

7.3.1.2 Interface passivation Electronically, surface states, which originated from dangling bonds and strained surface bonds, often pin the surface Fermi level and cause the bending of the surface energy band. When a metal is deposited on the silicon surface, the interface stages (previously called surface states) pin the Fermi level, making the SBH primarily controlled by interface states and less dependent on metal work function and Si electron affinity [31]. Introduced interfacial S, Se, or Cl atoms can passivate these dangling bonds and reduce the charge density of interface states. As a result, the SBH can

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Fig. 7.6 Atomic structures of (A) clean Si(001) in UHV and (B) Se/S-passivated Si(001) [31].

Dangling bonds

(A) Se/S atoms

(B) be tuned effectively due to alleviated FLP. In Fig. 7.6, the atomic structures of the clean Si(100) surface in an ultrahigh vacuum and passivated surface are schematically shown. Obviously, by introducing exotic atoms like S, Se, or Cl atoms, the interface states are reduced by the passivation of dangling bonds. The exotic atoms are usually introduced by a presilicidation implantation process, in which Se, S, or Cl atoms are implanted into the Si substrate followed by the silicidation process to consume the implanted layer as well as to pile up Se, S, or Cl atoms at the silicide/Si interface. Using this process to form an interfacial passivation layer between silicide and Si, very low ϕbn values below 0.1 eV have been obtained. Zhao et al. [32] modulated the SBH of NiSi on n-Si(100) by the segregation of S atoms at the silicide/Si interface. The Schottky diodes with and without interfacial S were characterized using current-voltage (I-V) measurements. With an increasing S dose, the reverse current is significantly increased, which indicates the continuous reduction of ϕbn values. The ϕbn value is reduced from 0.65 eV without interfacial S to 0.07 eV with S on n-Si(100). It is suggested that during NiSi formation by solid reaction of Ni with Si substrate, NiSi―S chemical bonds are formed at the NiSi/Si interface. The tuning of ϕbn values by interfacial S segregation is mainly due to two effects. First, the formation of chemical bonds between S and NiSi changes the work function of NiSi, and second, the segregation of S at the NiSi/Si interfaces forms a dipole as well as passivates the interface states. S passivation was also reported by Song et al. [16,33]. In Ref. [16], the n-Si(100) surface was passivated in situ with S in an aqueous solution containing ammonium sulfide and ammonium hydroxide at 60°C for 25 min. An extracted low ϕbn of 0.15 eV is obtained for the contact between Ni and the S-passivated Si(100). Similarly, experiments were carried out in Ref. [34] and a record low ϕbn of 0.02 eV has been demonstrated for the contact between Al and the S-passivated Si(100). Lee et al. realized an 87% reduction in ϕbn (from 0.85 to

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0.11 eV) by S segregation at the PtSi:C/Si:C interface and further ϕbn manipulation can be realized by altering the dose of implanted sulfur [35]. Tao et al. [36] have performed the passivation using Se in a molecular beam epitaxy system (MBE) at 224°C/60 s, and one monolayer of Se was formed on the surface of n-Si(100). For the Al―Si and Cr―Si contacts with an Se passivation layer, achieved results demonstrated that the SBH values agree well with their ideal barrier heights. The ϕbn values for Al―Si and Cr―Si contacts are reduced from 0.72 and 0.61 eV to 0.08 and 0.26 eV, respectively. It is argued that the monolayer of Se significantly reduces surface states on the Si(001) by terminating dangling bonds and relaxing strained bonds. With Se passivation, the Ohmic behavior for Ti/n-Si and Mg/n-Si contacts was also easily achieved in Refs. [37,38]. Wong et al. [39] also investigated the modulation of SBH using Se passivation. Se is implanted before the NiSi:C silicidation on the epitaxially grown Si0.99C0.01 substrate. A significant ϕbn reduction was observed for NiSi:C with Se segregation. For NiSi:C/Si0.99C0.01 diodes with a different Se implantation dose, the reverse current gradually increases with an increase in the Se dose. When the dose reaches 2  1014 cm 2, the typical Ohmic characteristics are observed, indicating the sharp reduction of ϕbn by Se segregation. A low ϕbn of 0.1 eV was extracted by activation-energy measurements at low forward voltage biases for the NiSi:C/Si0.99C0.01 diodes with 2  1014 cm 2 Se implantation. Cl is also used to passivate the surface states of the Si substrate. Loh et al. [40] demonstrated a significant lowering of the ϕbn values on n-Si(100) using a presilicide implantation of Cl into the Si substrate. For the NiSi/n-Si diodes with 1  1015 cm 2 Cl implantation, an extremely low ϕbn of 0.08 eV extracted using activation-energy measurements has been reported. Moreover, the NiSi films with Cl showed superior thermal stability and a marginal increase in sheet resistance occurs even at 850°C. In Ref. [38], Tao et al. discussed the detailed mechanisms of interface passivation on the Si substrate with different atoms such as Se, S, and Cl. It is claimed that the dangling bonds of the Si surface are chemically unstable, and the introduction of the S/Se/Cl atoms will suppress the chemical reactivity of these dangling bonds, leading to the depinning of the Fermi level by valence-mending. This technique of interface passivation takes advantage of high thermal stability, low surface recombination, and low contact resistivity. Note that for the Si(111) surface, each surface Si atom possesses one dangling bond, and group VII atoms such as Cl or F are preferable to terminate the dangling bonds. For the Si(100) and Si(110) surface, group VI atoms such as Se and S are more suitable [38].

7.3.1.3 Dopant segregation The dopant segregation technique was initially investigated by Wittmer [41]. In this technique, normal p-type and n-type dopants instead of exotic atoms piling up at the silicide/Si interface have been proposed to modulate the SBH. In principle, there are two main schemes in this technique, namely, Silicidation-induced dopant segregation (SIDS) and silicide as diffusion source (SADS), which are schematically depicted in Fig. 7.7. In SIDS (cf. Fig. 7.7A), the process steps include: (1) implant dopants into the Si substrate; (2) deposit metal films on the Si substrate; and (3) perform silicidation

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Fig. 7.7 Schematics showing the process steps in (A) SIDS and (B) SADS [42].

anneals to form silicide films and at the same time dopants pile up at the silicide/Si interface. Note that in this step the implanted Si layer should be consumed completely in the silicidation process. The segregation of the dopants at the silicide/silicon interface is due to two important observations. First, the solid solubility of B and As in the silicides is very low. Second, the intrinsic diffusion of these dopants at the silicidation temperatures used (1020 cm 3), the reduction in the ρC values is marginal because this reduction of ρC benefiting from the reduced barrier height becomes negligible at high-doping density. As a result, the MIS contacts in reducing ρC present enormous advantage on devices with relatively moderate doped (Nd <  1020 cm 3) semiconductors, but the effectiveness at high-doping levels is not that strong as expected. Moreover, it was also reported that the MIS contacts with TiO2 also suffer from the thermal stability issue of TiO2, since TiO2 will decompose during the rapid thermal process at merely 300–500°C/L min and lose the merit of MIS contact—the insulator passivation and low ϕbn [66]. In Ref. [67], an enhanced thermal stability of Ti/TiO2/n-Ge Ohmic contacts through plasma nitridation of the TiO2 interfacial layer is proposed to solve this problem.

7.3.2.2 Ohmic contacts with interface passivation It was found that tellurium (Te), selenium (Se), and sulfur (S) atoms can be adsorbed at the metal/semiconductor interface which eliminates dangling bonds, leading to a reduction of interface states and specific contact resistivity. This method is similar

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to dopant segregation, in which halogen ions are implanted prior to silicidation. After the silicidation process, the segregation occurs at the contact interface where the dangling bonds or interface states are passivated by halogen atoms. Te was introduced to reduce the contact resistance between PtSi and n+-Si:C [68,69]. Te ions were implanted prior to the deposition of Pt and segregated at the PtSi/n+-Si:C interface during PtSi formation. To investigate the impact of Te ions on effective ϕbn of the PtSi/n+-Si:C contacts, the I-V curves of Schottky diodes with different Te implantation doses were measured at room temperature. The reverse current increases with the increase in the Te implantation dose, indicating a gradual reduction in the effective ϕbn. Compared to the reference PtSi/n+-Si:C contacts without Te, a 106-fold increase in the reverse current occurs for the 1  1015 cm 2 dose, demonstrating a significant reduction of ϕbn to 0.12 eV by the incorporation of Te. A 62% reduction (from 438 Ω μm without Te to 166 Ω μm with Te) in the source/drain parasitic resistance was achieved on strained n-FinFETs. This leads to an increase in the saturation drive current by 22%. Te segregation at the PtSi/n+-Si:C interface does not degrade the short-channel effects and mobility for electrons. Except for the passivation of dangling bonds, the underlying mechanism for the effective reduction in ϕbn for PtSi with Te segregation is interpreted in terms of the presence of charged donor-like states, which leads to enhanced tunneling across the Schottky barrier at the PtSi/n+-Si:C contacts. Se atoms were introduced to the silicide/n+-Si interface for reducing the specific contact resistivity. Wong et al. [70] reported excellent ultrathin-body (UTB) n-MOSFETs with the incorporation of Se segregation at the NiSi/n+-Si interface. During the Ni silicidation process, the implanted Se segregated at the NiSi/n+-Si interface, leading to a significant reduction of ϕbn and thus reduced contact resistance. I-V characteristics of as-fabricated UTB n-MOSFETs displayed that the source/drain resistance (Rsd) is lowered by 74% with Se segregation than the devices without Se. In Ref. [71], Se segregation at the NiSi/n+-Si0.99C0.01 also leads to the excellent Ohmic contact characteristics, as well as an enhancement of 23% in the drive current for strained SOI n-MOSFETs. This enhancement is attributed to the decrease in external series resistance which is primarily due to the reduction of the contact resistance between silicide and Si. Ni et al. [72] studied the effects of Se segregation in TiSix and NiPtSi silicides contact technology. In this study, three process flows were employed: (1) post-NiPtSi Se implantation flow; (2) post-TiSix Se implantation flow; and (3) pre-TiSix Se implantation flow. The achieved results showed that two flows of postsilicide Se implantation and segregation do not lead to significant reduction in ρC, whereas a 40% reduction was obtained in the pre-TiSix Se implantation flow. Moreover, it is suggested that the implanted Se layer should be consumed completely and cannot be located too deep away from the silicide/Si interface. Employing this low energy and presilicide Se implantation in conjunction with the high-temperature annealing process, the ρc can be reduced to 8  10 9 Ω cm2 by Se segregation. Rao et al. [73] also achieved a low ρc value by Se segregation at the TiSix/n+-Si interface. Following the guidance in Ref. [72], Se ions were implanted prior to the formation of TiSix. An even lower ρC of 7  10 9 Ω cm2 is accomplished under the optimal condition of 1.5-keV implantation energy and 850°C dynamic surface annealing.

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Sulfur (S) segregation is another effective approach for achieving low ρc values. Lee et al. [35] demonstrated the advantage of S segregation on PtSi/n+-Si:C contacts. The devices with S segregation showed a 45% improvement in saturation drive current over the devices without S segregation. This improvement in saturation drive current is attributed to the reduction of parasitic source/drain resistance, which is decreased from 722 Ω μm without S to 356 Ω μm with S. An 87% reduction in the ϕbn at the PtSi/n+-Si:C interface by the passivation of S is evident. Koh et al. [74] also studied the reduction in the source/drain resistance and ϕbn for NiSi:C by S segregation. S of 1  1014 cm 2 dose is implanted into Si0.99C0.01 prior to the NiSi silicidation. With S segregation at the NiSi/n-Si0.99C0.01 interface, the reverse current is increased by 104-fold compared with the reference with S and an extremely low ϕbn of 0.1 eV was achieved. For as-fabricated n-FinFETs embedded with Si:C stressors, the source/drain resistance is reduced from 1214 Ω μm without S to 208 Ω μm with S, delivering a drop of 83%. It should be noted that although S segregation can lead to reduced contact resistance, the S out-diffusion at high-temperature anneal required for source/drain dopant activation may rule out the possibility of employing S segregation in practical Ohmic contacts.

7.3.2.3 Ohmic contacts with dopant segregation It has been proved that the ρC values can be reduced remarkably by enhanced dopant segregation (DS) at the silicide/Si interface. In contrast to the normal way for reducing ρC through heavy doping, the DS technique is not limited by the solid solubility of the impurity in Si and has advantageous constraints on the lateral profiling of impurity. Several researchers have reported the accomplishment of low ρC of approximately 10 9 Ω cm2 by the DS technique. As and B DS are always used to achieve low contact resistance in devices. CoSi2 in combination with As DS has obtained >20% improvement in the drive current over conventional n-MOSFETs [75,76] and this is attributed to the reduction in both the sheet resistance of CoSi2 and the ρC. Zhang et al. [77] have employed SADS to reduce the ρC between NiPtSi/n+-Si significantly. B or As ions are implanted into Ni0.9Pt0.1Si films formed on p+- or n+-type Si followed by low-temperature drive-in anneals to induce DS at the NiPtSi/Si interface. Extracted ρc data showed that with B DS, the ρc is reduced from 2.5  10 8 Ω cm2 without B DS to 7  10 9 Ω cm2. Similarly, the ρc is reduced from 1  10 8 Ω cm2 without As DS to 6  10 9 Ω cm2 with As DS. An experiment of the ρc dependence on applied voltage bias was also carried out. It is found that the ρc without DS strongly depends on the bias due to a relatively large SBH. With As or B DS, the bias dependence of the ρc is significantly suppressed, indicating a lower or more transparent barrier. As a result, the reduction of ρc is rather attributed to the lowered barrier height than heavy doping by DS. In Ref. [78], Luo et al. also studied the change of ρc induced by dopant segregation through SADS. As or B to a 1  1015 cm 2 dose were implanted into PtSi films preformed on both p+-Si and n+-Si. After anneals, As or B atoms pile up at the PtSi/Si interface as confirmed by SIMS. The achieved results showed that the As or B DS on the diffusion regions of opposite polarity (B DS on n+-Si and As DS on p+-Si) lead to an increase

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in ρc. However, for As or B DS on the diffusion regions of like polarity (B DS on p+-Si and As DS on n+-Si), the ρc. is decreased. The change in ρc by DS is strongly attributed to SBH modulation based on the formation of an interfacial dipole, instead of the altering of doping concentration. The Sb/As/Ge DS to improve the performance of n-type FinFETs was also reported by Kenney et al. [79]. It is shown that all three impurities DS lead to significantly reduced extrinsic resistance, especially the ρc. There is an optimal dose for the implantation of Sb/As/Ge to achieve the lowest ρc. The optimum dose for As and Ge is 5  1014 cm 2, which gives rise to a reduction in extrinsic resistance by 25% and 20%, respectively. Under the optimal dose of 5  1013 cm 2 for Sb implantation, a total 31% reduction in extrinsic resistance than the devices without Sb implantation is obtained. Furthermore, for this optimal condition of Sb DS, the ρc value was reduced to below 10 8 Ω cm2 by the modulation of SBH. Wong et al. [80] also reported a reduction of contact resistance in NiSi/n+-Si contacts by SbDS. Solid Sb with a thickness of 5 nm was deposited on n+-Si active regions, and an Ni layer of thickness of 10 nm was deposited in an e-beam evaporation system. After the formation of NiSi at 500°C/30 s, the Sb dopants pile up at the NiSi/n+-Si interface. I-V characteristics showed that the devices with Sb DS have an equal forward current and reverse current, indicating a typical Ohmic behavior. A low Schottky barrier to electrons of 0.092 eV is extracted. Without Sb DS, the reverse current is 4 orders lower than the forward current, showing a typical rectifying behavior. The n-type SB-MOSFETs with Sb DS demonstrate a much higher drive current and steeper subthreshold slope in the linear region than the control devices. With Sb DS, the total resistance of devices is reduced from 162 to 88 Ω and this is mainly attributed to the reduction of contact resistance. Additional Al DS has been applied to p-type FinFETs strained by SiGe S/D for reducing the contact resistance. Using Al DS after nickel germane-silicidation at the NiSiGe/SiGe, the lowering of ϕbp for NiSiGe has been demonstrated [81]. Al was implanted at an energy of 10 keV to a dose of 2  1014 cm 2 and all wafers were thermally annealed at 400°C/30 s to form NiSiGe contacts. An enhancement of 30% in the on-current was achieved without degrading the NiSiGe film morphology and short channel effects by Al DS. With an 77% drop in the SBH to holes of NiSiGe from 0.53 eV (without Al DS) to 0.12 eV (with Al DS), the source/drain resistance is reduced from 783 to 617 Ω μm, a drop of 25%, and this is mainly due to the reduction in the contact resistance.

7.3.2.4 Ohmic contact with higher dopant concentration It is well known that with an increase in dopant concentration, the width of the barrier at the metal/semiconductor contacts is narrowed and the tunneling probability of carriers is promoted significantly. Consequently, another very important approach in reducing the contact resistance is to increase the active dopant concentration as heavily as possible. Although the active dopant concentration can be improved by means of in situ doping and advanced thermal anneal, the most common way to enhance it thus to improve the specific contact resistivity is to utilize the idea of the so-called solid-phase epitaxial regrowth (SPER). Solid-phase epitaxial regrowth

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Fig. 7.9 Schematics showing the process flow of typical SPER.

refers to the process of epitaxial recrystallization of an amorphous layer on a singlecrystal Si or SiGe substrate. During the SPER process, the implanted impurity dopants and Si atoms have the same chance to occupy substitutional lattice sites and are activated, thereby enhancing the dopant concentration at the surface. Owing to its low-temperature recrystallization (500–650°C), SPER, in conjunction with advanced thermal annealing, has become an alternative technique to explore the formation of shallow junctions with steep abruptness, above-equilibrium activation levels, and compatibility with high-k and metal gate for 65-nm technology and beyond nodes [82,83]. In Fig. 7.9, the process flow for typical SPER in the contact technology is schematically shown. The surface preamorphization is often formed by Ge, Si, or GeF2 ion implantation, which is followed by dopant implantation into an as-formed amorphous layer. After that, two options can be chosen. One option is to perform thermal anneal to activate dopants as well as to recrystallize the amorphous layer. Another option is to deposit metal films on the amorphous layer and later to perform thermal anneal to recrystallize the amorphous layer as well as to form silicide on top. Considering the simplification of the process, the latter option is more popular in the state-ofthe-art contact technology [1]. Recently, the TiSix/n+-Si and TiSiGe/p+-SiGe Ohmic contacts have been explored extensively. SPER with in situ doping and millisecond laser anneal (dynamic surface annealing, DSA) is popularly applied to enhance doping activation at the surface of the semiconductor. Ni et al. [84] reported an ultralow ρc value of 2  10 9 Ω cm2 of TiSix/n+-Si Ohmic contact with the combination of a highly doped Si:P (HD Si:P) epitaxial layer and millisecond laser anneal. The doping activation process is performed with in situ P doping followed by millisecond laser anneal (DSA) at 1150° C and this has three main advantages compared to the conventional ion implantation: (1) much higher P activation efficiency; (2) better controlled box-shaped profile; and (3) less implant damage. The ρC values were determined at different doping concentrations ranging from 1019 to 1021 cm 3 by a series of contact chain structures. The ρC value as a function of chemical P concentration is achieved and the lowest ρC value of 2  10 9 Ω cm2 is obtained at [P] ¼ 2.5  1021 cm 3. According to this low ρC value and the field-emission model, it can be estimated that the active [P] is close to 1  1021 cm 3, which exceeds the solubility limit of P in silicon. The TiSix

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silicidations were performed using both DSA (800 and 950°C) and RTP soak anneal (575 and 625°C) and the ρC values using both anneal methods were compared. It was found that DSA can deliver lower ρC values compared to RTP soak anneal and DSA at higher temperature is preferable since the ρC degradation after forming gas anneal (FGA) can be minimized. Furthermore, it was proposed that additional P implantation of the HD Si:P epitaxial layer followed by DSA can further improve the ρC for TiSix/n+-Si. This additional P implantation can be implemented through mimicking both top-off implantation (P implantation after source/drain HD Si:P epitaxy) and contact open implantation (P implantation after contact opening) [85,86]. The achieved results show that the resistivity of the n+-Si layer in the source/drain regions can be reduced to 0.35 mΩ cm with top-off implantation and 0.31 mΩ cm with contact open implantation from 0.48 mΩ cm without additional implantation after DSA anneal [85]. Note that postimplantation DSA at higher temperature is beneficial to recover the amorphous Si layer and the strain in the HD Si:P epitaxial layer, but the steepness of the P concentration profile at the surface will deteriorate when the DSA temperature >1150°C due to P out-diffusion. For top-off implantation in this work, beam-line (cryogenic) implantation is applied to enhance the amorphization of the Si layer. For contact open implantation, the plasma implantation, a more preferred technology for reducing ρC, attributed to the improvement of doping conformality over fin without compromising electrical performance, is implemented. A record setting ρC of 1.2  10 9 Ω cm2 is achieved using HD Si:P epitaxy with additional implantation (either plasma or beam-line cryogenic implantation) followed by millisecond laser anneal (800°C DSA). The preamorphization implantation (PAI) can not only boost the dopant concentration by SPER but also enhance the Ti silicidation, which leads to reduced ρC values. Yu et al. [86] has employed the PAI plus Ti silicidation (TiSix) technique to form Ohmic contacts of an extremely low ρC value of 1.5  10 9 Ω cm2 in TiSix/n+-Si contacts. In situ doped HD Si:P with a P concentration of 2  1021 cm 3 is used as an n+-Si substrate, and 9  1020 cm 3 P is activated after 2-pulse 1200°C DSA. As mentioned in Fig. 7.9, after the PAI by Ge implantation, the TiSix silicidation and SPER of top α-Si layer simultaneously occur during RTP anneal at 500–575°C. The grazing incidence XRD (GIXRD) confirms that the formation of TiSix with Ge PAI takes place at lower temperature compared with that without Ge PAI. This suggests the enhancement of TiSix silicidation by Ge PAI. The ρC values for TiSix/n+-Si with and without PAI are 1.5  10 9 and 8  10 8 Ω cm2, respectively. A record low ρC value of 1.5  10 9 Ω cm2 for TiSix/n+-Si contacts is achieved under the sequential processing conditions: (1) HD Si:P epitaxy, (2) DSA for P activation, (3) Ge PAI, and (4) 525°C RTP for TiSix silicidation and α-Si SPER. It is suggested that Ge PAI + TiSix silicidation has the following advantages: (1) Si diffusion during TiSix growth at a relatively low temperature leads to a vacancy injection into the Si substrate, while Ge PAI creates end-of-range (EOR) interstitial defects. These two types of defects can recombine with each other, (2) thermal budget required for TiSix silicidation is lowered by Ge PAI, and (3) high P concentration normally suppresses the TiSix silicidation process, while Ge PAI releases this suppression [86].

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Similarly, Yang et al. [87] demonstrated the TiSiGe/p+-SiGe Ohmic contacts of a low ρc value of 5.9  10 9 Ω cm2, in which a cryogenic (cold) BPAI and subsequent SPER was used. The p+-SiGe in the source/drain regions was formed using a selective SiGe epitaxial process with in situ B doping. After the opening of contact trenches, B was implanted at 1.5 keV to a dosage of 3  1015 cm 2 at different temperatures (cryogenic: 100°C, room temperature and hot: 450°C). The α-SiGe layer caused by B implantation will be recrystallized during TiSix silicidation anneal. The ρc as a function of the 1000/T plot indicates that the optimal low ρc value of 5.9  10 9 Ω cm2 is obtained with a cryogenic B implant. It is explained that the cold implant creates a smooth amorphous/crystal interface and a more complete amorphous layer. After the recrystallization, the defects within an SiGe layer can be reduced significantly. Moreover, this additional B cryogenic implantation would also increase the doping concentration. In Refs. [88,89], Yu et al. achieved a low ρc value of 2.1  10 9 Ω cm2 with the combination of pre-B implantation Ge PAI and ns laser anneal. Based on previous discussions, in the Ti-based contacts in the state-of-the-art CMOS technology, a guidance for achieving low ρc values on n+-Si and p+-SiGe can be summarized: (1) in situ P or B doping as heavily as possible during S:P or SiGe epitaxy; (2) laser anneal to activate dopants; (3) Ge PAI or P/B cryogenic PAI to amorphize the top surface or n+-Si or p+-SiGe; and (4) a low thermal budget post metal anneal to form TiSix or TiSiGe as well as to recrystallize the amorphous top layer by SPER. By optimizing the processing conditions, the ρC value of sub-1  10 9 Ω cm2 will be achievable in the future [89].

7.4

Ohmic contacts on Ge/III-V

Owing to the superior hole mobility for Ge and electron mobility for III-V semiconductors, Ge and III-V like InGaAs are attractive channel materials for p-MOSFETs and n-MOSFETs, respectively. It should be noted that in the family of III-V semiconductors, the popular adoption of InGaAs as the channel material for n-MOSFETs is a result of (1) higher electron mobility with the increase in the percent of Indium, (2) good lattice match on the insulating InP substrate, and (3) addition of In giving rise to alleviated FLP. Consequently, the focus of III-V channel materials in this section is InGaAs though GaAs, InP, and GaN are also popular III-V semiconductors for wide applications in RF, microwave devices, HEMTs, etc. Similar to Si/SiGe, the modulation of SBHs in forming good Ohmic contacts on Ge/III-V is also important. As seen in Fig. 7.10A [90], unlike the FLP at different positions in the bandgap of Si depending on the employed metals, the Fermi level is almost fixed at a very confined shallow region just above the valence band edge of Ge. This FLP raised one serious problem for forming good Ohmic contacts on n-type Ge due to the large ϕbn, apart from the poor dopant activation of n-type dopants [91]. A lot of methods have been studied to alleviate the FLP on Ge and will be discussed in this section. In contrast to Ge, the Fermi level is pinned just below the conduction band edge for metals/In0.53Ga0.47As contacts, which leads to pretty low and desired low

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Fig. 7.10 (A) Schematics showing the Fermi-level pinning for different metals contacting with n-Si and n-Ge and (B) the Schottky barrier heights of metals (Al, Ti, Sn, Ni, Au, and Pt)/n-InGaAs contacts [90,92].

ϕbn as depicted in Fig. 7.10B [92]. This makes the realization of Ohmic contacts on n-type In0.53Ga0.47As easy. The motivation for reducing SBH thus forming good Ohmic contacts on n-type InGaAs is therefore not very strong in this regard. Considering the possible fabrication of p-MOSFETs or metallic Schottky barrier source/drain devices using InGaAs, some methods are also proposed to alleviate the FLP on InGaAs.

7.4.1 Modulation of SBH on Ge/III-V semiconductors 7.4.1.1 MIS method Various dielectric layers can be inserted between metals and Ge to depin the Fermi level. Li et al. reported that an ultrathin yttrium oxide (1-nm-thick Y2O3) is introduced at the Ti/n-Ge interface to modulate the SBH by alleviating the FLP [93]. The formation of this Y2O3 ultrathin layer is a result of thermal oxidation of deposited metal Y layers by electron beam evaporation in air. The ϕbn can be reduced from 0.53 eV without a dielectric layer to 0.37 eV by the insertion of a 1-nm-thick Y2O3. In this work, the alleviation of FLP is attributed to the reduction of interface states by the passivation effect of Y2O3, as verified by the C-V measurement. However, the suppression of MIGS by Y2O3 cannot be ignored while depinning the Fermi level, because of its relatively large bandgap of 6 eV. A thin layer of MgO was also reported by Zhou et al. to alleviate the FLP on Ge [94]. Ultrathin high-quality single-crystalline and atomically smooth MgO layers of different thicknesses were epitaxially grown on the Ge substrate by means of electron beam evaporation at 250°C. It is found that the insertion of a 0.5-nm-thick MgO already shows the depinning of the Fermi level, as the ϕbn is reduced from 0.62 eV for reference without MgO to 0.35 eV. However, the depinning effect displays a weak

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dependence on the MgO thickness, indicating that the interface states due to the surface defects on Ge are likely to play a dominant role in FLP. However, it is also argued that the even the 0.5-nm-thick MgO may already exceed the saturation thickness and it would have blocked all MIGS; this also gives rise to the weak dependence of the depinning effect on MgO thickness. The most natural choice of the dielectric materials is germanium oxide. Indeed, the employment of GeO2 (GeOx) to alleviate the FLP has been reported in Refs. [95–98]. In Ref. [95], when the thickness of GeO2 is increased gradually from 0 to 1.6 nm and beyond for Al/GeOx/n-Ge diodes, the junction properties will be gradually changed from Schottky to Ohmic characteristics, indicating the reduction of ϕbn as a result of the Fermi-level depinning. This evidence suggests that MIGS are the dominant mechanism of the strong FLP for metal/Ge contacts. However, this thermally grown GeO2 layer between Al and Ge is demonstrated to be not thermally stable and the reaction of Al and GeO2 would occur when annealed at 300°C [96]. Consequently, the depinning effect using the insertion of a 2.7-nm-thick GeO2 between Al and Ge vanishes. A 3.5-nm-thick HfNx/GeON stacked layer deposited by sputtering in the N2 atmosphere is proposed to solve this problem. Note that HfNx has a low work function of 4.1–4.55 eV and GeON is not intentionally deposited but a result of nitridation of GeO2 during the HfNx sputtering in N2. The depinning effect of this stacked layer is able to be maintained until 450°C N2 annealing. An ultrathin (1 nm) GeOxNy layer was also fabricated by NH3 plasma pretreatment on n-Ge(100) prior to the deposition of Al. The SBH of 0.65 eV for Al/n-Ge is significantly lowered to 0.19 eV for Al/GeOxNy/n-Ge contacts and it is attributed to the suppression of MIGS [97]. Another interesting work using a GeO2-based dielectric, that is, GeSnOx, to depin the Fermi level was disclosed in Ref. [98]. A thin Sn layer was sputtering deposited on Ge followed by annealing at 130°C for 5 min in N2 to enhance Sn doping into Ge. After the removal of the remaining Sn in HCl solution, the oxidation to form GeSnOx was carried out at 400°C in O2 for different durations and as-formed GeSnOx is less than 3 nm. The ϕbn of Al/n-Ge junctions was modulated from 0.62 eV to the Ohmic range by increasing the oxidation durations of the Sn-doped Ge to 5 min, demonstrating the depinning of the Fermi level. This depinning of the Fermi level by the introduction of a GeSnOx interlayer between Al and Ge is ascribed to the reduction of MIGS, as well as the passivation of interface states like dangling bonds. The FLP for n-type Ge can be altered by the introduction of a thin Ge3N4 layer [18,99], allowing the formation of Ohmic contacts on n-Ge and rectifying contacts on p-Ge. A thin Ge3N4 layer, regardless of whether it is amorphous or crystalline, can effectively eliminate the pinning of the Fermi level at the metal/Ge interface. Note that Ge3N4 is formed by exposing Ge in the N2 plasma and amorphous Ge3N4 (α-Ge3N4) is formed below 500°C on Ge(100), whereas the crystalline Ge3N4 (c-G3N4) is only formed above 600°C on Ge(111) [100]. The metals/1.2-nm-thick Ge3N4/n-Ge contacts show a linear dependence of the SBH with metal work function. The dependence of SBH on the metal work function clearly indicates that the introduction of an ultrathin α- or c-Ge3N4 layer eliminates the FLP, and therefore allows for SBH control by choosing a metal with appropriate work functions. The authors argued that depinning of the Fermi level was accomplished mainly due to the

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passivation of interface states related to defects at the metal/Ge interface, instead of the suppression of the penetration of electron wave functions into the Ge bandgap, since a Ge3N4 thickness beyond 2 nm would be required to completely suppress the penetration of metal wave functions, because of the smaller bandgap and bandgap offset of Ge3N4 [98]. A ϕbn of 0.1 eV for an Al/0.6-nm-thick c-Ge3N4/n-Ge contact was observed and this again indicates that passivation of Ge surface states is the main mechanism to depin the Fermi level. Apart from the passivation of interface states, the partially ionic Ge―N bonds derived from the difference in the Pauling electronegativity of nitrogen and germanium may also limit the number of Ge3N4 surface states, as well as lead to the formation of a dipole at the Ge3N4/Ge interface. Both are beneficial in depinning the Fermi level. By inserting 1.2 nm α- or c-Ge3N4 between Al with work function of 4.17 eV and n-Ge, the ϕbn of 0.09  0.05 and 0.0  0.1 eV are achieved. AlOx or Al2O3 was also used to alleviate the FLP on n-Ge. The aluminum oxide is usually formed by oxidation of aluminum. Nishimura et al. [95] observed that the ϕbn was reduced from 0.57 to 0.2 eV by the insertion of an AlOx layer 0.3 nm and as the increase of AlOx thickness, the ϕbn stayed unaltered. Lin et al. reported that an ultrathin (1 nm) Al2O3 inserted between Al of low work function and Au of high work function leads to the shift of ϕbn from 0.6 eV for reference without Al2O3 to 0.1 eV [101]. In Ref. [102], the effective ϕbn for Ni, Co, and Fe/n-Ge contacts were lowered from 0.54, 0.62, and 0.61 eV without Al2O3 to 0.39, 0.23, and 0.18 eV with a 0.8-nm-thick Al2O3, respectively. It is argued in Ref. [98] that the origin of FLP at the metal/Ge interface is caused by MIGS, since the gradual shift of ϕbn to lower values with increasing thickness of insulators was observed. However, this gradual shift of ϕbn might also result from the more complete passivation of surface states of Ge. What is more, if MIGS is the dominant mechanism for FLP, it is difficult to understand how a 0.3-nm-thick AlOx can fully block the penetration of electron wave functions into the Ge bandgap. SiN is another option for the insulator between metals and Ge to depin the Fermi level. SiN is deposited by the well-controlled sputtering system. The Al/SiN/n-Ge diodes were fabricated by varying the thickness of SiN and the effective SBH modulation for different metals (Pt, Ni, W, Ti, Al, and Er) contacting with n-Ge by inserting an ultrathin interfacial SiN layer was reported in Refs. [17,101,103]. As the thickness of SiN (tSiN) increases from 0 to 2 nm and beyond, the metal/n-Ge contacts change from rectifying to Ohmic behavior gradually, which suggests the gradual reduction of ϕbn. Furthermore, the SBH for different metals (Pt, Ni, W, Ti, Al, and Er)/ 2-nm-thick SiN/n-Ge contacts shows an almost linear relationship with the work functions of used metals, also indicating the effective depinning of the Fermi level by the insertion of SiN. For the Er with the lowest work function of 3.05 eV, a nearly zero ϕbn can be obtained. The dependence of SBH on the thickness of SiN seems a strong indication that the depinning of the Fermi level results from the suppression of the penetration of electron wave functions into the Ge bandgap. However, since more complete passivation of the surface states of Ge using a thicker SiN layer similar to AlOx is anticipated, the passivation mechanism in depinning the Fermi level cannot be ruled out.

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Although the aforementioned insulator dielectrics, that is, Y2O3, MgO, GeOx, GeOxNy, Ge3N4, and SiN, can be used to effectively depin the Fermi level either by passivating the surface states of Ge or by blocking the electron wave functions, their applications into real Ohmic contacts are restricted by the so-called tunnel resistance in association with their own resistances of insulators, as interpreted in Section 7.3.2. As a result, the insulators with a small CBO to the conduction band of Ge (e.g., TiO2, ZnO, etc.) are also highly desired. Moreover, it is reported that the net interfacial dipole effect for oxide insulators is stronger than nitride because M―O bonds are much more polar than M―N bonds [104]. The CBO between TiO2 and Ge is estimated to range from 0.06 to 0.26 eV, so it is easier for carriers to tunnel through the barrier; thus, a lowered tunneling resistance is anticipated. In Ref. [105], the TiO2 was introduced between Al and n-Ge by ALD at 150°C. It is found that with 5.8 and 8.8 nm TiO2, the ϕbn values are reduced from 0.58 eV without TiO2 to 0.104 and 0.065 eV, respectively. Additionally, the current density is high because the tunneling resistance remains very low for the Al/8.8 nm TiO2/n-Ge diodes. In Ref. [106], an ultrathin TiO2 (1 nm)/GeO2 (1.5 nm) interlayer stack, instead of a bare TiO2 layer, is introduced into the contact scheme to alleviate FLP and to reduce the ϕbn. The TiO2 was deposited by ALD at 250°C and the GeO2 layer was formed by plasma oxidation process. It is claimed that the TiO2 interlayer alleviates the FLP by preventing the formation of MIGS with its very low tunneling resistance, and the GeO2 interlayer provides a high quality interface with low interface state density (Dit). Both are beneficial in the alleviation of FLP on Ge. The Ti/TiO2/ GeO2/n-Ge exhibits a ϕbn 0.193 eV, whereas the Ti/n-Ge exhibits a ϕbn 0.55 eV. In Refs. [107,108], three possible mechanisms, that is, MIGS model, dipole model, and fixed charge model, for the SBH modulation in Ti/TiO2/n-Ge contacts are examined. It is found that the main cause is not the release of the FLP effect but the shift of the pinning position. The interface dipole plays more a significant role than the fixed charges. Thermal annealing in vacuum at a temperature as low as 300°C changes the interface dipole due to the short-range ordering of the TiO2 insulator so that the ϕbn changes. The ϕbn of Al/TiO2 (7 nm)/n-Ge increases from 0.03 eV for the TiO2 as-deposited sample to 0.11 eV after 400°C annealing. Beyond 400°C, the ϕbn would be too high to maintain an Ohmic contact. Since the amount of fixed charges in the thin TiO2 layer estimated from a metal-insulator-semiconductor structure is 2  1011 cm2, and is insufficient to produce the observed ϕbn reduction to 0.5 eV compared with the ϕbn without TiO2 (0.58 eV), it is thus recommended that the main depinning mechanism using a TiO2 layer comes from the change of interface dipoles. This work also pointed out that insulators with a low CBO which has good thermal stability should be explored.

7.4.1.2 Interface passivation Disorder-induced gap states (DIGS) are related to defects at the metal/semiconductor interface due to the disorder of the atomic arrangement. Dangling bonds at the surface of semiconductors are typical DIGS which can be can be passivated by introducing

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certain atoms such as Sn, S, Se, Te, F, etc. Similar to Si/SiGe, the SBH modulation on Ge has been extensively explored by interface passivation. Suzuki et al. [109,110] reported the SBH modulation of metal/n-Ge contacts by introducing an ultrahigh Sn content Ge1 xSnx epitaxial interlayer between metals and n-Ge. For the Al/Ge1 xSnx/n-Ge diodes, the current density increases with increasing Sn content. The estimated ϕbn decreases to 0.49 eV with an increase in the Sn content up to 46% in the 3-nm Ge1 xSnx interlayer. The shift of the pinning position toward the conduction band edge of Ge is one of the reasons for the SBH reduction of Al/Ge1 xSnx/n-Ge diodes, because the valence band edge of Ge1 xSnx would rise as the Sn content increases. Additionally, the suppression of DIGS by the formation of a Ge1 xSnx epitaxial interlayer with an ultrahigh Sn content would also be a reasonable mechanism for the reduction of SBH. The epitaxial layer would effectively decrease the density of interfacial states at the Ge1 xSnx interface by terminating dangling bonds of the Ge surface [109]. Interestingly, a reduced effective ϕbn of 0.37 eV is obtained at the NiGe2/Ge(100) interface and this is substantially lower than 0.60 eV at the NiGe/Ge(100) interface. The Fermi-level depinning, similar to the epitaxial Ge1 xSnx on Ge, is attributed to the formation of epitaxial NiGe2 on Ge(100), which is expected to have a lower density of interface states due to the reduced number of dangling bonds [111]. In Ref. [112], F atoms introduced by the CF4 plasma treatment were also used to passivate the dangling bonds at the Ge surface. For Al/n-Ge diodes with different durations of the CF4 surface treatment, they change from rectifying to Ohmic behavior gradually as the duration increases from 0 to 6 min, confirming the depinning of the Fermi level. This depinning is explained by the effective capability in passivating dangling bonds at the Ge surface through fluorine atoms, as well as the formation of Ge―F binding with partial ionic property. Tong et al. [113,114] investigated novel selenium implant and segregation for the reduction of effective ϕbn in NiGe/n-Ge contacts. Both Se and S are found to segregate at the NiGe/n-Ge interface after the 350°C/30 s germanidation process, giving rise to low ϕbn values of 0.13 eV for Se and 0.1 eV for S. The uniformity of NiGe films were also improved probably due to the surface amorphization by Se and S ion implantation [113]. Se is known to act as a donor impurity in Ge and introduces a shallow donor-like trap level at 0.14 eV below the conduction band of Ge. These shallow donor-like traps, owing to Se segregation in the Ge top surface at the NiGe/n-Ge interface, could lead to a sharp upward band bending of Ge, thus narrowing the barrier width for electrons tunneling. Furthermore, the presence of traps in Ge near the contact is expected to increase the probability of trap-assisted tunneling (TAT) of electrons through the barrier, giving rise to a larger reverse bias current which is manifested as a smaller effective ϕbn [114]. During Ni germanidation, the segregation of S atoms at the NiGe/Ge interface is also found to lower the ϕbn successfully in Ref. [115]. The ϕbn of NiGe/n-Ge diodes is decreased gradually from 0.61 to 0.15 eV with an increase in the S dose. In Ref. [116], the S and P cointroduction was found to be most effective in lowering ϕbn. S and P cointroduction has two advantages compared to S or P introduction alone. (1) It increases the doping concentration of P in Ge and (2) passivates the dangling bonds

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by S. Both advantages are helpful in achieving a low ϕbn. In Ref. [117], the depinning of the Fermi level on both p-and n-Ge after S passivation by aqueous (NH4)2S treatment was reported. Examination of the passivated surface using XPS revealed the bonding between Ge and S. Ohmic contacts with n-Ge and a ϕbp of 0.6 eV to p-Ge can be achieved on Zr/S:n- or p-Ge contacts. Both Al and Zr show good Ohmic behavior on S-passivated n-Ge and rectifying behavior on p-Ge. Furthermore, in Ref. [118], the effectiveness of different chalcogen atoms (S, Se, Te) in lowering the ϕbn on n-Ge is compared. It is found that for NiGe/n-Ge diodes annealed at 450°C, the reverse current increases on the order of S, Se, and Te. This demonstrates clearly that the Te atoms are most effective in lowering ϕbn. The mechanism of using chalcogen atoms in depinning the FL, thus lowering ϕbn, is explained in terms of the passivation of dangling bonds [117] and dipole effect due to the partially ionic chalcogen atoms [119]. The SBH modulation of metal/Ge contacts by inserting an amorphous Ge (α-Ge) layer has been demonstrated. When the thickness of α-Ge reaches above 10 nm (10–70 nm), the Al/α-Ge/n-Ge, Fe/α-Ge/n-Ge, and Ni/α-Ge/n-Ge diodes all show Ohmic characteristics compared to the rectification without α-Ge. This observation is explained by two main mechanisms for the modulation of SBH: (1) the interfacial layer may act as a dangling bond terminator at the Ge surface, and consequently reduces the surface charge trap density. Also, the inserted interfacial layer can block the electron wave function from metal to semiconductor and reduce the MIGS. Ge―Ge binding is purely covalent, so there are no dipoles at the interface; (2) localized states of α-Ge play a critical role in the enhancement of electron transportation by hopping [120]. Baek et al. [121] also achieved the alleviation of the FLP at the metal/n-Ge contact by the insertion of multiple layers of single-layer graphene (SLG). As the number of inserted SLG increases from 0 to 2 layers, the ϕbn decreases from 0.6 to 0.2 eV, which supports the contention that FLP at the metal/n-Ge contact probably originates from the MIGS. The inserted SLG layers can be used as the tunnel barrier for spin injection into Ge for spin-based transistors. The optimum number of graphene layers which minimizes the SBH was found to be 2.

7.4.1.3 Dipole and dopant segregation The formation of a dipole at the metal/Ge interface can shift the pinning position toward the conduction band, thereby lowering the ϕbn. Since the mechanism of dopant segregation in tuning the SBH is the formation of a dipole at the metal/Ge interface, dipole, and dopant segregation are discussed in this section. In Ref. [122], by varying the composition of TiNx during sputtering, the SBH modulation was demonstrated for TiNx/n-Ge diodes. From the I-V measurement, the reverse current increases significantly with the introduction of TiNx, and it is almost equal to the forward current when x ¼ 0.8, indicating an Ohmic behavior for TiN0.8/n-Ge contacts. The ϕbn was reduced to 0.45 eV for TiNx/n-Ge, as compared to 0.56 eV for Ti/n-Ge contacts. Considering the difference of the Pauling electronegativities for Ge (2.01) and N (3.04), the N―Ge bond is not pure covalent but partially ionic and the N―Ge bonds can be regarded as interfacial dipoles with the direction

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from the metal nitride side to the Ge side. This as-formed dipole at the interface is proposed to alleviate the FLP, thus leading to reduced ϕbn. Iyota et al. [123] also reported that an Ohmic contact on n-Ge was accomplished by sputtering 50-nm-thick TiN on Ge followed by 350°C anneal. The SBHs for TiN/n-Ge and TiN/p-Ge contacts were 0.18 and 0.50 eV, respectively, and were maintained up to 550°C anneal. This reduction in ϕbn is also ascribed to the likely formation of a dipole since an approximately 1-nm-thick Ti―Ge―N interlayer is formed at the TiN/Ge interface. An Ohmic contact with n-Ge with compositional WNx was reported in Ref. [124]. The WNx films were prepared by the reactive sputtering of W in Ar/N2. By varying the composition of the WNx films, the effective ϕbn is decreased from 0.52 eV for W/n-Ge contact to 0.47, 0.42, and 0.39 eV for WNx/n-Ge with x ¼ 0.06, 0.09, and 0.15. An Ohmic contact was achieved at x ¼ 0.19. An N―Ge dipole across the WNx/n-Ge interface is proposed to alleviate the FLP, thus leading to reduced ϕbn. Both the surface passivation and the removal of dangling bonds using WNx films were also thought to be helpful in alleviating the FLP in this work. The SBH modulation of metal/n-Ge contacts by inserting a TaN layer in between has also been reported [125]. The TaN and contact metals (Al, Fe, and Ni) were all deposited by sputtering. By varying the thickness of TaN to 10 nm, the effective ϕbn, originally pinned at 0.53–0.61 eV for metal/n-Ge contacts, decays to 0.44 eV for metal/TaN/n-Ge contacts, which is independent of the employed metals with different work functions. In Ref. [126], the SBH modulation of TaN/n-Ge contacts by varying the nitrogen concentration in TaN films was disclosed. The TaN films were deposited in a reactive sputtering chamber. The ϕbn decreases from 0.552 to 0.220 eV as the atomic ratio of nitrogen in TaN increases from 0% to 54.2%. For both cases, owing to the difference in the Pauling electronegativity of N (3.04), Ge (2.01), and Ta (1.5), the N―Ge and Ta―N bindings are not purely covalent but partially ionic, and therefore the polarized covalent bindings may create a dipole at the TaN/Ge interface. The dipole formation is proposed as one cause to alleviate the FLP and to shift the pinning level toward the conduction band edge of Ge. Moreover, during the TaN deposition, the sputtered nitrogen ions may passivate the dangling bonds on the Ge surface, thus alleviating the FLP [126]. As, P, and B dopant segregation (DS) is also a promising way to modulate the SBH by dipole effect. In Ref. [127], the As and P segregate at the NiGe/n-Ge interface due to the snowplow effect during the Ni germanidation process. The effective ϕbn for NiGe/n-Ge diodes is reduced from 0.72 eV without DS to 0.19 eV by As DS and to 0.34 eV by P DS. It is found that DS is more effective for PtGe2/n-Ge contacts, where the effective ϕbn is reduced to 0.05 eV by As DS and to 0.07 eV by P DS. Different work functions between NiGe and PtGe2, as well as different segregation and activation efficiencies for dopants, are proposed to interpret the difference in ϕbn lowering by DS. This DS by snowplow effect in NiGe/n-Ge contacts is also reported in Ref. [128], where the ϕbn from 0.72 eV without DS to 0.38 eV by P DS and to 0.19 eV by AS DS demonstrate the superiority of As DS in lowering ϕbn. Contrary to the DS by snowplow effect, a record-low ϕbn of 0.1 eV is achieved by P DS at the NiGe/Ge interface [129]. In this work, the P ions were implanted into NiGe films

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followed by a drive-in anneal to induce P DS at the NiGe/Ge interface. From the SIMS profiles, an obvious P peak is located at the NiGe/Ge interface. Similar investigations were also carried out by various groups. P ions were implanted into NiGe and then driven toward the NiGe/Ge interface to depin the Fermi level. The ϕbn values were all reduced to 0.1 eV in Refs. [130,131]. In Ref. [132], the Pt germanidation induced dopant segregation (P) at the PtGe/Ge interface leads to the lowered ϕbn of 0.16 eV (from 0.67 eV).

7.4.1.4 SBH modulation on III-V materials To use III-V materials for CMOS applications, it is critical to develop a method to controllably tune the SBH for devices that employ the Schottky barrier source/drain and scalable nonalloyed Ohmic contacts. Hu et al. [133] modulated the SBH of Metal/ III-V contacts by inserting an ALD high-k dielectric between metals and III-V semiconductors. The ϕbn of Metal/n-GaAs can be reduced from 0.75 to 0.17 eV by inserting a thin SixNy or Al2O3. Dielectrics including ALD HfO2, TiO2, and ZrO2 lead to a similar reduction in ϕbn. It is discovered that the presence of high-k/high-k dipoles in HfO2/TiO2 will further reduce the ϕbn and contact resistance beyond that of a single high-k dielectric, despite an overall thicker dielectric layer, and this is explained by the presence of dipoles. The dipole formation within HfO2/TiO2 is a result of different areal oxygen density (σ HfO2 > σ TiO2) and this difference leads to a dipole pointing toward HfO2 [134]. A novel nonalloyed contact structure for n-GaAs and n-In0.53Ga0.47As by using single metals in combination with a thin dielectric to tune the SBH of metal/III-V contacts was reported in Ref. [134]. A lot of metal/n-GaAs and metal/n-In0.53Ga0.47As contacts are verified (Y, Er, Al, Ti, and W). It is found that by the insertion of ALD Al2O3 and sputtered SiN between metal and n-GaAs or n-In0.53Ga0.47As, the ϕbn can be reduced from 0.75 to 0.2 eV. This reduction in ϕbn supports that the insertion of a dielectric layer can be applied to the Ohmic contacts in III-V MOSFETs, as well as near zero SBH contacts for III-V Schottky barrier MOSFETs. In this work, two possible mechanisms are discussed as the cause of the reduction in ϕbn by the insertion of thin dielectrics, one based on the formation of a dielectric dipole and the other based on the blocking of MIGS. Similar experiments were also carried out by Chauhan et al. [135]. Al2O3 was deposited by ALD between Pt (high work function)/Al (low work function) and n-/p-type In0.53Ga0.47As. Rectifying behavior on Al/p-In0.53Ga0.47As contacts becomes Ohmic behavior on Al/Al2O3/p-In0.53Ga0.47As contacts, indicating a sharp reduction in ϕbp. In Ref. [136], the contacts between metal and both n- and p-type In0.53Ga0.47As are investigated by inserting an ALD Al2O3 interlayer. The results indicate that SBH tuning is more effective at the n-In0.53Ga0.47As interface than at the p-In0.53Ga0.47As interface for the same Al2O3 thickness. However, the Fermi level at the metal/In0.53Ga0.47As interface is still weakly pinned even after inserting 2-nm Al2O3. The mechanism of SBH tuning could be attributed to the creation of an electric dipole at the Al2O3/In0.53Ga0.47As interface, which induces a barrier shift [136].

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7.4.2 Ohmic contacts on Ge/III-V semiconductors 7.4.2.1 MIS Ohmic contacts The contact resistance can be reduced significantly by inserting an ultrathin dielectric layer between metal and Ge. In Ref. [137], the insertion of ALD, Al2O3, and HfO2 between metal and n-Ge was employed to reduce the contact resistance. The ϕbn of Al/n-Ge contacts was reduced from 0.7 eV without insulators to 0.28 eV with a 2.8-nm-thick Al2O3 interfacial layer. For Al/insulators/n-Ge contacts with Al2O3 exceeding 2.8 nm and HfO2 exceeding 1.5 nm, the contact resistance starts increasing because tunneling resistance dominates for thicker Al2O3 and HfO2 dielectric layers. A thinner critical thickness of 1.5 nm for HfO2 than 2.8 nm for Al2O3 is ascribed to the larger dielectric constant of HfO2. In Ref. [138], different dielectric materials are studied in order to understand the feasibility and limitations of this MIS technique in making good Ohmic contacts with n-type Ge. It is found that only insulators with a very low CBO can provide the low ρc while depinning the Fermi level. Insulators with large CBO will have a large tunneling resistance, thereby producing poor contacts even if they can alleviate the FLP. In Ref. [139], a physic-based approach is investigated to evaluate the ρc for metal/n-Ge contacts inserted with various interfacial layers (ILs). It is indicated that using TiO2, ZnO, and Sn-doped In2O3 (ITO) ILs of low CBO to the conduction band of Ge ( 0.06, 0.1 and 0.1 eV respectively), good Ohmic contacts with low resistance are readily formed for metal/n-Ge contacts. However, it is also shown that applying the ZnO into Ti/ZnO/n-Ge contacts with a 3  1020 cm 3 doping concentration does not lead to a noticeable decrease in the ρc value. This could be explained by the shadow effect of heavy substrate doping on the SBH lowering. Moreover, in this work, doping of the ILs is proposed as an additional knob for lowering the ρc value in the MIS contacts. In Ref. [140], a ρc value of 1.3  10 6 Ω cm2 was achieved by inserting a TiO2 of low CBO between Al and n+-Ge, which represents a 70 reduction from conventional Al/Ge contacts. The reduction in ρc is attributed to an electronic dipole at the metal/ TiO2 interface, which effectively pins the metal Fermi level closer to the Ge conduction band. Additionally, compared to Al2O3, TiO2 is advantageous since the tunneling resistance of Al2O3 becomes significant from a very small thickness (2 nm or so). In Ref. [105], by inserting a 7.1-nm-thick TiO2 between Al and n-Ge, the current density is increased by about 900  at 0.1 V and 1200 at 0.1 V compared to contacts without TiO2. The fact that the I-V characteristics of the samples with 5.8 and 8.8 nm TiO2 look similar is an indication that thicker TiO2 does not lead to increased tunneling resistance significantly, as predicted by CBO estimations. Metals of different work functions (Yb, Ti, Ni, and Pt)/ALD TiO2 x/n-Ge contacts were investigated in Ref. [141]. It is found that Yb/1 nm TiO2 x/n-Ge contacts show higher current density and lower ϕbn compared with Ti/1 nm TiO2 x/n-Ge contacts and this is attributed to the lower work function of Yb compared with Ti. The contact of Yb/1 nm ALD TiO2 x/n+-Ge(2.5  1019 cm 3) is shown to have a low ρc value of 1.4  10 8 Ω cm 2, 10  lower than Ti/1 nm ALD TiO2 x/n+-Ge control contact. Note that in this work, the TiO2 x is doped by oxygen vacancies which is helpful in reducing the ρc in MIS contacts.

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The effect of hydrogen annealing on reducing the ρc of metal/TiO2/n-Ge contacts was also studied in Ref. [142]. The postdeposition H2 annealing (PDHA) has two effects on the Ti/1 nm TiO2/n-Ge contacts: (1) reducing TiO2 to oxygen-deficient TiO2 x (TiO2 x doping similar to Ref. [141]), which is more conductive; thus, the tunneling resistance is decreased; (2) interface control by H2 annealing since H2 acts as a terminator of dangling bonds on the Ge surface, which leads to the reduction of the density of interface traps (Dit), thus depinning the Fermi level. The ρC values are reduced significantly for the Ti/TiO2/n-Ge contacts with H2 annealing compared with the contacts without H2 annealing. 1-nm TiO2 is found to be the optimal interlayer thickness, since the H2 PDHA can exert the best passivation effect at the TiO2/Ge interface, even though 2-nm TiO2 may provide more effective depinning of the Fermi level. A ρc value of 5.6  10 5 Ω cm2 on a relatively low doped n-Ge (9  1018 cm 3) substrate is accomplished in this work. Besides the H2 annealing to doping TiO2, a novel doping technique for the TiO2 interfacial layer at low temperature using Ar plasma treatment was proposed to improve the MIS Ohmic contact [143]. The Ar plasma treatment of the TiO2 layer was performed in a plasma etching tool. The mechanism of this doping technique is that Ar ion bombardment can form nonlattice oxygen atoms, that is, oxygen vacancies. For the Ti/TiO2/n-Ge (6  1016 cm 3) contact with 1-nm TiO2IL treated by Ar plasma for 20 s, a minimum ρc of 3.16  10 3 Ω cm2 is obtained, which is a 584  reduction compared with the Ti/n-Ge contact and a 11  reduction for Ti/1-nm untreated TiO2/n-Ge contacts. Doping of TiO2 IL does not induce the depinning of the Fermi level, but instead reduces the effective tunneling thickness of IL and leads to additional SBH lowering. ZnO is another attractive IL option for MIS contacts on Si, Ge, and SiC because of (1) low CBO to n-Ge; (2) heavy doping possible in ZnO (Ti/ZnO annealing to create oxygen vacancies (VO) in ZnO at the Ti/ZnO interface [144]); (3) low FLP factor for metal/ZnO contacts [30].Compared to other ILs like Al2O3 and TiO2, n+-ZnO gives a significantly higher current density on n-Ge due to the low tunneling barrier. The ρC of (0.8–1.5)  10 6 Ω cm2 is obtained on Ti/n+-ZnO/n-Ge (1  1019 cm 3). In Ref. [145], a model to demonstrate the effect of heavily doped IL insertion on the ρc reduction in metal/n-Ge contacts (Ti/n+-ZnO/n-Ge) is presented. It is found that the doping of IL results in lowering ϕbn significantly. The abrupt reduction in ρc is observed in heavily doped condition as the ZnO thickness is increased to 1.5 nm. Besides, the tunneling probability through the ZnO IL has been boosted by ZnO doping, resulting in a 25 reduction of the contact resistivity compared to un-doped ZnO contacts. In Ref. [146], TaN/2.5nm-thick n or n+-ZnO (1  1020 cm 3)/n+-Ge (3  1019 cm 3) contacts were investigated. The TaN/n+-ZnO contacts generate a much lower ρc value of 2  10 9 Ω cm2 and are less prone to variation. TCAD simulations demonstrate that MIS contacts with an n+-IL can achieve a much lower current variation and a higher on-state drive current (lower ρc). In Ref. [147], the impact of varying IL doping on the performance of Ti/IL/n-Ge contacts is demonstrated using un-doped ZnO, aluminum-doped ZnO (AZO), and O-vacancy-doped n+-ZnO ILs having similar CBO to Ge. It is shown that ρC-n+-ZnO < ρC-AZO < ρC-ZnO for doping concentration Nn+-ZnO > NAZO > NZnO. Though FLP occurs for all ILs, the ρc and its dependence on the IL thickness decrease with increasing IL doping owing to the reduction of tunneling resistance. Doped ILs for MIS contact not only help in depinning the FL, but are also helpful in reducing the

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101

n-Si

n-Ge

10−3 10

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ρc by minimizing the series tunneling resistance, especially for thicker ILs. Using a heavily doped (3.4  1020 cm 3) ITO layer, a ρc value of 1.4  10 7 Ω cm2, which is independent of the ITO thickness up to 5 nm, is obtained on n-Ge with a very low doping concentration (1  1017 cm 3). Agrawal et al. [148] proposed a comprehensive, physics-based unified model for studying the low resistivity MIS contacts. For n-Si, n-Ge, and n-InGaAs, the reduction in MIGS and the FLP in semiconductors as a function of insulator thickness is coupled with electron transport including tunnel resistance through the MIS contacts to calculate the ρC at each insulator thickness, as shown in Fig. 7.11. It is found that a low CBO results in ρc values of 1  10 9 Ω cm2 with a TiO2 insulator on n-Si, of 7  10 9 Ω cm2 with TiO2 and ZnO insulators on n-Ge, and of 6  10 9 Ω cm2 with a CdO insulator on heavily doped n-In0.53Ga0.47As. With low CBO insulators, the ultralow ρc values can be maintained at relatively large insulator thickness as shown in Fig. 7.11A. It is proposed that inserting a thin insulator between the metal and semiconductor attenuates the metal electron wave function in the insulator prior to penetration in the semiconductor. This would result in fewer charges available to drive the Fermi level toward the charge neutral level (ECNL), and thus an FLP is alleviated to some degree [148].

Fig. 7.11 (A) Calculated specific contact resistivity as a function of insulator thickness for Al/ insulator/n-Si, n-Ge, and n-In0.53Ga0.47As with La2O3, ZnS, ZnSe, ZnO, TiO2, Ta2O5, SrTiO3, GeO2, CdO, and SnO2 as interfacial insulators. (B) Summary of minimum specific contact resistivity along with optimal insulator thickness using various insulators on n-Si, n-Ge, and n-InGaAs [148].

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7.4.2.2 Ohmic contacts with interface passivation and dopant segregation Kim et al. [149] studied Fermi-level depinning and contact resistance reduction for metal/n-Ge contacts by surface passivation using SF6 plasma treatment. A ρc value of 1.14  10 3 Ω cm2 and ϕbn of 0.31 eV are achieved for Ti/SF6-treated n-Ge (1  1017 cm 3) contacts, which is a 1700  reduction in contrast to a Ti/untreated n-Ge contact. The ρc value as a function of SF6 plasma treatment time demonstrates that there is an optimal duration time for the plasma treatment to obtain the lowest ρc, for example, 30 s in this work. More than 30 s treatment by the SF6 plasma, the Ge surface is rather etched by the plasma than passivated by S and F atoms. Consequently, the density of the interface trap (Dit) increases due to the reduction of Ge―F and Ge―S bonds and the degradation of the Ge surface. There are two effects of FL depinning: (1) the passivation of dangling bonds at the Ge surface by both F and S atoms and (2) formation of polarized Ge―F and Ge―S covalent bonds. The thermal stability of SF6 plasma treatment in improving the Ohmic contacts was confirmed by exerting an extra thermal annealing at 400°C/30 min. The effect of P and As DS on the NiGe/n-Ge contacts was studied by experiments and first-principle calculations [150]. P and As ions were implanted before NiGe formation (IBG) or after NiGe (IAG) formation. Compared to Al/n-Ge contacts, the NiGe/n-Ge contacts always show higher forward current because of germanidation induced DS. First-principle calculations predict that P tends to segregate at the NiGe side while As tends to segregate at the Ge side. The P IBG and As IAG achieve the lowest ρC value of 2  10 6 Ω cm2 and the average ρc value of 6.7  10 6 Ω cm2 with a 1  1015 cm 2 implantation dose and 350°C/5 min NiGe formation. In Ref. [151], a P/Sb codoping and germanidation induced dopant segregation to achieve a record low ρc on n+-Ge (7  1019 cm 3) was reported. P (90 keV, 6  1014 cm 2) and Sb (65 keV, 6  1014 cm 2) are implanted and activated at 500°C/10 s RTA in N2. After NiGe formation at 350°C/30 s in N2, it was found that P/Sb peak concentrations are located near the NiGe/Ge interface. The NiGe/n+-Ge contact with DS achieved a ρc value of 5.5  10 7 Ω cm2, much lower than the Al/Ti/n+-Ge contact (2.1  10 6 Ω cm2) because of lowered ϕbn by P and Sb DS [151]. In Ref. [152], NiGe/n+-Ge contacts with ultralow ρc were realized by two-step P ion implantation. The first P implantation and 600°C/1 min anneal are to activate dopants. After the second P implantation and 350°C/1 min anneal, 10- or 20-nm-thick NiGe films are formed and P DS occurs at the NiGe/Ge interface. A ρc value of 3  10 8 Ω cm2 was obtained using this two-step P implantation approach. The Pt germanidation induced P DS for PtGe/n+-Ge contacts (3  1019 cm 3) delivers a low ρc of (6.8  2.1)  10 8 Ω cm2 [153]. Compared to the contacts between NiGe, Al, Ni, Pt and n+-Ge, PtGe/n+-Ge contacts show the lowest ρc value due to the strong P DS. It is claimed that DS at the interface and increased interface roughness caused by the PtGe formation are crucial in further reducing the ρc.

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7.4.2.3 Ohmic contacts with higher doping concentration It is most common to achieve low ρc values by increasing the doping concentration in Ge as high as possible. There are a lot of methods to increase the doping concentration in Ge such as multiimplantation multiannealing (MIMA), codoping, laser annealing (LA), and SPER. In Ref. [154], a P ion multiple implantation and multiple annealing (MIMA) technique was proposed to reduce the ρc. P ion was implanted at 50 keV to a dose of 5  1014 cm 3 followed by 600°C anneal to activate the dopants and this process repeats for several cycles. For Al/Ti/n-Ge contacts with MIMA, the ρc value is significantly reduced to 3.8  10 7 Ω cm2 by this technique, since an enhanced doping concentration of >1  1020 cm 3 was obtained. The lowest ρc occurs for 4 cycles and a further increase in the P implantation leads to the increase in ρc. This increase is probably ascribed to the saturation of dopant activation and surplus implantation may result in crystal damage. Improved donor activation by MIMA technique is related to the reduced implantation damage, as confirmed by Raman analysis. Diode ideality factor by MIMA is smaller than that of the single implanted diode (with the same dose), also suggesting the reduced defects density by MIMA technique. Except MIMA, the codoping of P and Sb in Ge after rapid thermal annealing can also deliver n-type dopant activation beyond 1  1020 cm 3. In Ref. [155], P (90 keV, 6  1014 cm 2) and Sb (65 keV, 6  1014 cm 2) were implanted into Ge and followed by RTA at 500°C/10 s in N2 to activate dopants. For as-fabricated Al/Ti/n+-Ge contacts, a pretty low ρc value of 8  10 7 Ω cm2 has been demonstrated. Combining the aforementioned MIMA, codoping, and germanidation induced dopant segregation, further improvement on the ρc value is anticipated [156]. For P/Sb coimplantation on n-Ge, the active concentrations were 8.6  1019 cm 3 with RTA and 1.9  1020 cm 3 with LA, respectively, in Ref. [157]. For p-Ge with Ge preamorphization implantation (PAI) and B implantation, the active concentration was 8.4  1020 cm 3 with LA. By employing LA to achieve heavy doping concentrations in Ge, the ρc values of 2.3  10 9 Ω cm2 and 1.9  10 8 Ω cm2 for NiGe/p+- and n+-Ge contacts were obtained, which are 4 orders of magnitude lower than those values achieved with RTA. Firrincieli et al. [158] also reported the formation of Ohmic contacts using two different approaches: (1) dopant activation by LA prior to NiGe formation and (2) snowplow effect during Ni germanidation without previous dopant activation. The ρc value, 8  10 7 Ω cm2, is much lower for the approach using LA to activate dopants, compared to 2  10 5 Ω cm2 for the snowplow approach and this indicates the advantage in obtaining heavy doping using LA. However, after the annealing at 400°C, the ρc values deteriorate to one order of magnitude higher than low-temperature samples for both approaches. The poor thermal stability of shallow junctions activated by LA is also reported in Ref. [159], leading to P deactivation after postannealing and this deteriorates the ρc values. Other than activating dopants by LA, Shayesteh et al. [160] investigated the Ohmic contacts between germanide and n-Ge where the germanides were formed by LA or conventional RTA. 20-nm-thick Ni films were deposited and the NiGe formations

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were performed with 250–350°C/30 s RTA or 0.25–0.55 J/cm2 LA. The surface topography, interface quality, crystal structure, and material stoichiometry were explored in this work. A NiGe/epitaxial NiGe2 double layer is formed by LA which produces a uniform contact with a remarkably smooth NiGe2/n-Ge interface. Epitaxial NiGe2 on (001) Ge is not thermodynamically favorable, and may be formed as a result of minimization of the interfacial energy. The ρc value of 2.84  10 7 Ω cm2 is achieved for optimized LA energy density conditions, which is two to three orders of magnitude lower than the RTA cases. The improved ρc could be attributed to improved interface with reduced FLP as well as to dopant segregation induced by LA. However, the postannealing at 200–500°C leads to the deterioration of ρc especially 400°C due to the agglomeration of NiGe films. In Ref. [161], selectively grown n+-Ge of 7  1019 cm 3 by LPCVD achieved a high activation rate of 73%. The contact between Ti and this n+-Ge exhibits Ohmic behavior in contrast to the rectifying behavior for the contact between Ti and P-implanted Ge. The ρc of 1.2  10 6 Ω cm2 were obtained for the 65-nm-thick n+-Ge epitaxial layer, but Ti/n+-Ge with P-implantation (2  1019 cm 3) shows non-Ohmic behavior because of the FLP. During the epitaxy of the n+-Ge layer, there is a trade-off between the increase in dopant activation by increasing the flow of P(GeH3)2 precursors and dopant deactivation by the formation of inactive P-V pairs. The Ti/p+-Ge and NiGe/p+-Ge Ohmic contacts are compared on both planar-and finbased devices [162]. Ti/p+-Ge contacts show low ρc values, while NiGe/p-Ge devices show short circuit problems due to the lateral encroachment of Ni. As a result, Ti is more suitable for p-Ge contacts. A low Ti/p+-Ge ρc of 1.1  10 8 Ω cm2 is achieved using multipulse LA for B activation. However, as in Ref. [158], the thermal stability of ultra shallow junctions of B activated by LA should be examined. Solid-phase epitaxial regrowth (SPER) technique, as depicted in Section 7.3.2, is also employed to enhance the dopant concentration and suppress dopant diffusion in Ge. Cryogenic ion implantation has been shown to enable SPER and to realize ultra shallow junctions. In Ref. [163], B ion implantation was carried out at 100°C in order to fully amorphize the Ge surface layer by avoiding the dynamic thermal annealing. After a low temperature 400°C anneal, the amorphous Ge recrystallizes into c-Ge and, at the same time, full activation of B occurs during SPER. The cryogenic B ion implantation leads to 5 lower Rsh along with a shallower junction compared to room temperature implantation. A high activation of 4  1020 cm 3 is achieved which delivers a low ρc value of 1.7  10 8 Ω cm2 [163,164]. Miyoshi et al. [165] reported a carrier activation enhancement technique (CAE) in which P/Sb coimplantation for n-type dopants and Ge PAI plus B implantation for p-type dopants were used. A high electron concentration of 8.6  1019 cm 3 using the former CAE and a record high hole concentration of 8.4  1020 cm 3 using the latter CAE were achieved. The key idea for CAE technique is SPER in which nearly full dopant activation happens. Using this CAE technique, low ρc values of 6.4  10 7 Ω cm2 for NiGe/n+-Ge and 4.0  10 8 Ω cm2 for NiGe/p+-Ge are obtained. An in situ doped thin Si epitaxial layer (P, 1  1020 cm 3) was grown on n-Ge (300°C due to In out-diffusion from the semiconductor into the contact metal. In Ref. [169], multilayer Ohmic contacts with different first metal layers (Mo, Pd, Pt) beneath a Ti/Pt diffusion barrier and Au cap were fabricated on n+ and p+-InGaAs. As in Ref. [5], Pd-based contacts still offered the lowest ρc value of 3.2  10 8 Ω cm2 and 1.9  10 8 Ω cm2 to n+- and p+-InGaAs, respectively. On the other hand, the Mo-based contacts with n+ and p+-InGaAs have much higher ρc values, even though its ρc values on lightly doped n-InGaAs were nearly the same as that of the Pd-based contact. The cause of this discrepancy was identified to be the native oxide layer that remained between the contact and semiconductor in the Mo-based contacts. This native oxide can be penetrated by Pd but not be easily penetrated by Mo metal. As a result, appropriate surface preparations should be addressed in order to achieve low ρc values in Mo-based Ohmic contact on n+-InGaAs. The advantages of using Mo as the metal in contact with n+-InGaAs dwell on its high melting point, relative ease of deposition, and shallow reaction depth. Baraskar et al. [7] reported an ultralow ρc value with ex situ Mo contacts with heavily doped n-type In0.53Ga0.47As. Importantly, two surface cleaning techniques were applied to n+-In0.53Ga0.47As (5  1019 cm 3): (1) UV/O3 exposure plus a dilute HCl etch; (2) Mo contact metal was deposited in an electron-beam evaporation chamber without breaking vacuum after H cleaning, where H was thermally cracked for 20–40 min at 375–420°C. The ρc values obtained with UV/O3/HCl cleaned and UV/O3/HCl/H cleaned contacts were (1.5  1.0)  10 8 and (1.1  0.9)  10 8 Ω cm2, respectively. The ρc values achieved in this work are comparable to that obtained with in situ Mo contacts [6], demonstrating the effective removal of surface contaminants. The ρc value of (1.1  0.6)  10 8 Ω cm2 was also reported by the same research group using in situ Mo Ohmic contacts with heavily doped n+-InGaAs (6  1019 cm 3), where the contacts were formed by depositing Mo immediately after the In0.53Ga0.47As growth without breaking vacuum. This low ρc value results from the high carrier concentration as well as a metal-semiconductor interface free of oxides and other contaminants [6]. Low ρc values of (1.3  0.4)  10 6 Ω cm2 [170] and 1.3  10 8 Ω cm2 [171] using in situ Mo onto n-type In0.53Ga0.47As were also reported and Mo contacts can be thermally stable up to about 400°C [6,172].

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Ohmic contacts on potential CMOS channel materials

In the next decade, new materials and transistor geometries will be needed to address the formidable challenges of transistor scaling. Low dimensional materials, including transition metal dichalcogenides (TMDs), topological insulators, graphene, and carbon nanotubes (CNTs), provide the option of ultimate thin channel transistors and the opportunity for new device concepts. It is predictable that there are a variety of challenges for low dimensional materials to be applied into real devices. One of the most difficult challenges is the contact resistance between metal and low dimensional materials, which will inevitably limit the device performance if not handled properly. In this section, recent work on reducing the contact resistance and different strategies for optimizing the Ohmic contacts between metals and low dimensional materials are discussed. Graphene is the first separated two-dimensional material which has extremely high carrier mobility. The high carrier mobility, however, on the other hand, imposes a strict requirement on the contact resistance in graphene-based devices. Although Ohmic contacts can be formed between different metals and graphene due to graphene0 s zero bandgap, the specific contact resistivity is intrinsically high because of the small density of state in graphene. In order to maximize the potential of high performance graphene in practical applications, it is of great importance to reduce the contact resistance. To date, a couple of methods have been proposed to improve the Ohmic contact between graphene and metals, such as pretreatment of graphene prior to metallization [173–176], postmetallization annealing [177,178], and end/edge-contacts [179–183]. The pretreatment of graphene prior to metallization is an effective way to improve the Ohmic contact and has been implemented by gentle oxygen plasma and ultraviolet ozone (UVO) [173–176]. Chen et al. have shown that the surface of graphene can be cleaned in the optimized UVO process. The contact resistance between graphene and Ti/Au is improved by three orders of magnitude (3  10 6 Ω cm2) compared to untreated surfaces (4  10 3 Ω cm2) [174]. The effects of various plasmas (Ar, O2, N2, and H2) on the bonding properties of graphene to metals were investigated by Choi et al. [173]. It is found that the functional groups such as hydrogen, oxygen, and hydroxide generated during the plasma treatment process make the graphene surface hydrophilic, which improved the Ohmic contact between graphene and metals. On the basis of the oxygen plasma treatment, Robinson et al. studied different metals/ graphene contacts (Ti/Au, Al/Au, Ni/Au, Cu/Au, Pt/Au, and Pd/Au) [176]. The optimal specific contact resistivity for treated Ti/Au contacts is found to be define the dielectric trench for copper filling. PR

IMD IMD

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Plasma etch/ash + ESL opening-> ESL is used to define the trench depth and protect the layer below from plasma etch/ash treatments.

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Fig. 8.2 Schematic flow of a typical single damascene integration process.

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IMD

IMD

(7)

(8)

(9)

Excess metal removal by CMP IMD

Fig. 8.3 Schematic flow of a trench first dual damascene integration process.

In the dual damascene integration flows, it is noted that only one metal fill and one metal CMP (chemical-mechanical planarization) are required for each metal level (wiring + via) fabrication, resulting in less steps and thus a lower process cost as compared to the single damascene process. The dual damascene approach also leads to lower via resistances and improved resistance to electromigration by: (1) reducing the number of interfaces in the via (one bottom interface for copper dual damascene scheme vs. one top and one bottom interfaces for copper single damascene scheme); (2) providing full wire/via overlap at the top of the via (although the overlap of the via with the underlying metal is still subject to misalignment error).

However, dual damascene schemes are more complex and have several integration concerns, as shown in Fig. 8.5.

8.2.2 Copper resistance with interconnect scaling For 22- and 14-nm technology nodes, over 10 levels of interconnects with copper and SiOCH low-k dielectrics are already in mass production, as shown in Fig. 8.6. For the 14-nm technology node of Intel, the interconnect pitch (metal line width + line

Advanced interconnect technology and reliability

219 PR deposition, exposure and development -> via define PR

IMD deposition

ESL deposition ESL

IMD

IMD

(1)

(2)

(3)

Via etch/strip + ESL opening

Via filling with a sacrificial material

PR deposition, exposure and development -> trench define

IMD

IMD

IMD

(4)

(5)

(6)

Trench etch/strip and via filling decomposition

Diffusion barrier/copper seed deposition Barrier/seed

Copper plating Copper

IMD

IMD

IMD

(7)

(8)

(9)

Excess metal removal by CMP IMD

(10)

Fig. 8.4 Schematic flow of via first dual damascene integration process.

spacing) is 52 nm. Also, it is continuing to scale following Moore’s law. On such a small scale, the resistance of copper lines is determined not only by the bulk copper resistivity, but also by the electron scattering at the interface and grain boundaries. As shown in Fig. 8.7, with the copper line width scaling, the effective copper resistivity increases dramatically, due to surface and grain boundary scattering. This will lead to RC delay time increase and thus significantly degrade the circuit performance. To keep the metal resistance in a reasonable range, some alternative barrier and seed metals are under investigation, for example, Mn-based barrier and Co, Ru seed layers [7].

8.2.3 New copper integration scheme Another way to reduce effective copper resistivity in an ultra-narrow interconnect is to reduce the electron scattering at grain boundaries, that is, to increase the copper grain size in the nanoscale interconnect. However, in the copper damascene integration scheme, the metal line is deposited and crystalized after the trench patterning in

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CMP interface: defects, residue lead to poor BTS reliability

Metal adhesion: etch polymer; barrier coverage on rough sidewalls SiN

Interface adhesion leakage current, CVD cap process must be optimized

SiO2

Low-k SiN Metal fill: voids, Low-k scums. Cu SiN adhesion Low-k SiN SiO2

Cu

Weak via: nitride undercut

Si substrate

Via resistance: Cu oxide, etch residue

Barrier effectiveness: Cu diffusion through weak spots, Cu berried under barrier due to etch

Cu oxide: adhesion, blisters

Fig. 8.5 Challenges and concerns in dual damascene integration schemes [2].

22 nm process 14 nm process

80 nm minimum pitch

52 nm (0.65x) minimum pitch

Fig. 8.6 Cross section of Intel 22- and 14-nm technology chips with over 10 metal layers of Cu interconnects in the BEOL part (http://www.anandtech.com/show/8367/intels-14nmtechnology-in-detail).

the intermetal dielectric. The narrow trench limits the copper grain growth, which means with copper line width decreasing, the copper grain size also decreases and more electron scattering at the grain boundary seems inevitable. However, if the metal line patterning sequence can be reversed, that is, metal copper is first deposited as a blanket and then patterned, then the initial copper grain size will not be limited by the line width and therefore electron scattering at grain boundaries can be reduced. The implementation of this route is strongly dependent on the

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MPU M1 half pitch (nm)

40

10

35

8

30 25

6

20 15

4

10 5

2

0 2010

2015

M1 half pitch (nm)

2020

2025

Effective cu resistivity (µΩ cm)

12

45

0 2030

Effective Cu resistivity (µΩ cm)

Fig. 8.7 ITRS prediction of copper line width (half-pitch) scaling and effective copper resistivity evolvement. Source: ITRS 2013.

Fig. 8.8 TEM cross section and EDS mapping of directly etched narrow Cu lines with a full dielectric passivation [8].

dry etch equipment and process development. Copper dry etch by-products are normally nonvolatile, which makes the continuous etch challenging. Some demonstration [8] shows that a 44-nm line-width copper interconnect can be patterned by copper direct dry etch (Fig. 8.8) and achieves corresponding lower resistivity and promising electromigration performance (Fig. 8.9).

8.3

Low-k dielectric characteristics and classification

The process integration and reliability of intermetal low-k dielectrics are closely correlated with the low-k material properties. The thermal, mechanical, and electrical properties of low-k dielectrics are inferior to those of silicon oxide. Therefore, in most cases, a trade-off between achieving a lower dielectric constant (k) value and maintaining reasonable thermal, mechanical, and electrical properties should be carefully carried out.

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Fig. 8.9 Direct etched Cu resistivity versus cross-sectional area, benched with ITRS data and damascene Cu data [8].

8.3.1 Low-k characteristics Reduction of the interline capacitance is critical for the continuous scaling of on-chip interconnects. The capacitance between neighboring metal wires consists of three components: an area component, a fringing field component and a wire-to-wire capacitance component [3]. To reduce the capacitance, the prevalent solution is to replace chemical vapor deposition (CVD) deposited silicon oxide with low-k materials in the intrametal dielectric stack. CVD silicon oxide has a k value of  4.2 and is the model material for low-k dielectrics. Currently, there are mainly two approaches to reduce the k value of the dielectric films: material composition modification and porosity introduction.

8.3.1.1 Material composition The dielectric constant of a material is closely connected with the polarizability, which is a measure of the molecule’s ability to respond to an electric field and acquire an electric dipole moment. There are three polarization phenomena, that is, electronic polarization (αe), distortion polarization (αd), and orientation polarization (μ). The quantitative relation between the relative permittivity and the three polarities can be described by the Debye equation
 Er 1 N μ2 ¼ αe + αd + Er + 2 3E0 3kT

(8.1)

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Table 8.1

223

Electronic polarizability and bond enthalpies [5,9]

Bond

˚ 3) Polarizability (A

Average bond energy (Kcal/mol)

C–C C–F C–O C–H O–H C¼O C¼C CC CN Si–C Si–H Si–Si Si–N Si–O Si–F Si–Cl Si–Br

0.531 0.555 0.584 0.652 0.706 1.020 1.643 2.036 2.239

347.27 485.34 351.46 414.22 426.77 736.38 610.86 836.8 891.19 451.5 299.2 326.8 10.0 47015 799.6 13.4 552.7 21 406 367.8 10.0

where ε0 is the permittivity of the vacuum, N the molecule density, k the Boltzmann constant, and T is the temperature in Kelvin [4]. If the polarizability of the molecule can be reduced, the dielectric constant will decrease correspondingly. For silica-based low-k dielectrics, the main method to reduce the polarizability is to replace part of the Si–O bond with bonds that can reduce the polarity of the molecule structure. A summary (Table 8.1) of some typical electronic polarizabilities and the associated bond enthalpies is shown to demonstrate the different polarities indifferent chemical bonds [5]. It is indicated that single C–C and C–F bonds are among those with the lowest ionic polarizability, thus making fluorinated and nonfluorinated aliphatic hydrocarbons potential candidates for low-k applications. Fluorine, if not tightly bound, is very corrosive to metals and fluorinated films often show adhesion problems. Hence, nowadays carbon doping is the most popular method for low-k film preparation. The extreme of carbon doping low-k materials is organic polymer, which contains almost 90% of carbon in the chemical composition, but it is often much softer than the rigid, network bonded oxide-like dielectric materials and can also decompose at lower temperatures.

8.3.1.2 Porosity Beside modification of the chemical composition of the skeleton material, inclusion of air pores into the skeleton of solid dielectrics is also widely employed to achieve a lower k value. Since air/vacuum has the lowest permittivity, a common way to reduce the dielectric constant (k) of dielectric materials is to introduce porosity into the

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skeleton material structure. The k value (or ε) of a solid dielectric is composed of two basic components and can be written as [4] Er 1 E1 1 ¼P
+ ð1 Er + 2 E1 + 2

PÞ


E2 1 E2 + 2

(8.2)

where ε1 is the permittivity of the material mixed into the skeleton, ε2 the permittivity of the skeleton material, and P is the film porosity. When the mixed material is air (ε1 ¼ εair ¼ 1), Eq. (8.2) is simplified to Eq. (8.3). Er 1 ¼ ð1 Er + 2

PÞ


E2 1 E2 + 2

(8.3)

For most low-k dielectrics, silica is still the skeleton material. When the porosity increases, the k value decreases. Although introducing air pores into solid dielectrics successfully lowers the effective k value, the apparent side effects are also inevitable: significant degradation of the chemical, physical, and mechanical properties of the intermetal dielectric and significant challenges to the integration process of copper/ low-k interconnects [4,5].

8.3.2 Low-k classification and characterization Currently, there are many low-k materials available on the market and in the labs, which can be categorized by different classification methods, including the chemical composition, pore size distribution, and deposition method. According to the chemical composition, most low-k dielectrics can be categorized into silsesquioxane (SSQ)-based, silica-based, and organic polymers [4]. The silsequioxanebased low-k dielectrics include hydrogen-silsesquioxane (HSQ) and methyl-silsesquioxane (MSQ) and usually a silsequioxane-based low-k dielectric is a mixture of both HSQ and MSQ. Silica-based low-k dielectrics have the tetrahedral basic structure as silicon oxide. Each silicon atom is at the center of a regular tetrahedron of oxygen atoms. All types of silica have dense structures and high chemical and thermal stability. According to the pore size distribution, low-k materials can be classified into two groups: mesoporous and microporous. Mesoporous low-k dielectrics have an average pore size larger than 2 nm and micro-porous low-k dielectrics have an average pore size smaller than 2 nm. Low-k dielectrics can also be classified in terms of the deposition methods: CVD and spin-on. When we describe a low-k material, it is usually not possible to show all the physical and chemical properties at one time. The most common way is to present the type, the k value, the porosity, and the average pore size. Nowadays, most industry standard low-k dielectrics are silica based and usually porosity and carbon doping of the skeleton material are employed together. To understand the composition and properties of different low-k materials, there are many characterization techniques (Table 8.2) that can show the material properties from different aspects.

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Table 8.2

225

Common characterization techniques for low-k dielectrics

[4,5,10] Category

Property

Characterization methods

Structural

Average film density Average pore size

Specular X-ray reflectivity (SXR) Small-angle neutron scattering (SANS) Ellipsometric porosimetry (EP) SXR using pore wall density from SANS, EP EP, small-angle X-ray scattering (SAXS) SANS, positronium annihilation lifetime spectroscopy (PALS) SXR, Rutherford backscattering spectroscopy (RBS) Variable-angle spectroscopic ellipsometry (VASE), EP SANS EP, PALS Fourier transform infrared spectroscopy (FTIR), time-of-flight secondary ion mass spectroscopy (ToF-SIMS) X-ray photoelectron spectroscopy (XPS) Elastic recoil detect analysis (ERDA) EP, RBS, Energy filtered electron transmission spectroscopy (EFTEM) EFTEM Nuclear magnetic resonance (NMR) 3-ω method SXR, Spectroscopic ellipsometry (SE) Dual substrate bending system or nanoindentation SAXS Dual substrate bending system nanoindentation, surface acoustic wave spectroscopy (SAWS) Brillouin light scattering (BLS), EP MIS or MIM dot capacitors FTIR, water EP, SANS

Mesoporosity Pore structure

Total porosity

Compositional

Thermal

Mechanical

Electrical

Pore wall density Pore connectivity Chemical composition and bond structure

Atomic composition Bond polarity Thermal conductivity Out-of-plane CTE Lateral CTE and glass transition temperature (Tg) Modulus

k value (1 MHz) Moisture uptake

8.3.3 Low-k dielectrics integration challenges For advanced BEOL structures with ultrafine features and low-k dielectrics, there are many integration challenges [11], including l

l

l

l

Resist poisoning Compatibility of low-k materials with wet cleaning Compatibility of metallic diffusion barriers with low-k materials Pore sealing

226

3.5 Bulk dielectric constant

Fig. 8.10 Prediction gap in the bulk low-k dielectric constant between ITRS 2003 and ITRS 2013. Source: ITRS.

CMOS Past, Present and Future

ITRS 2003 ITRS 2013

3 2.5 2 1.5 1 2000

2010

2020

2030

Year

l

l

Processing damage to low-k films CMP compatibility

As shown in Fig. 8.10, the prediction of BEOL low-k development in the ITRS road map of 2013 was significantly lagging behind that of 2003, which is very different from the comparison in Fig. 8.1. To overcome these challenges, there are quite some variations of damascene integration schemes. For example, in dual damascene integration, a buried mask can be used to enhance the etch selectivity and/or a top hard mask can be applied to reduce the plasma damage to the intermetal dielectric.

8.3.4 Air gap implementation in interconnect To reduce further the RC delay, low-k dielectrics with a lower dielectric constant are being searched for. The most direct way is to implement air gaps between copper liners so that the bulk dielectric constant value goes down to 1.0, the lowest one among all dielectrics. As shown in Fig. 8.11 [12], it is feasible to implement this by using some sacrificial dielectric during the damascene process and then replace it with air gaps. However, there are a lot of engineering and reliability issues to be solved before introducing air gaps into the real CMOS chips. Therefore, the first place to implement air gaps is not in the densest M1 layer but in the less dense metal layers, as shown in Fig 8.12 [13]. Fig. 8.11 Air gap formation by means of sacrificial materials [12].

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Fig. 8.12 Intel 14-nm technology with air gaps in the M4 and M6 layers. Source: INTEL website.

8.4

Copper interaction with silicon and dielectrics

Copper diffusion/drift is a big concern in silicon-based CMOS technology. The interaction of copper with silicon and dielectrics is discussed below.

8.4.1 Copper interaction with silicon Copper is generally regarded as a fast interstitial diffuser in silicon, which is mobile at and below room temperature and can form various defect complexes [14]. It can also be trapped by a vacancy, become a substitutional defect, and act as an immobile trap for other impurities like hydrogen or interstitial copper [15–19]. Furthermore, the Schottky barrier height (SBH) and its temperature dependence are affected by copper and copper silicide [20].

8.4.2 Copper interaction with dielectrics Copper is not only a major notorious impurity for silicon devices, but also a significant reliability concern for dielectrics. The existence of copper in intermetal dielectrics may also increase the leakage current and degrade the dielectric lifetime. In the literature, quite a few works have shown that copper can also diffuse fast in dielectrics and degrade the breakdown lifetimes. Wendt et al. [21] investigated the copper contamination effects on gate oxide reliability and reported two failure mechanisms: copperrich silicide induced penetration into the oxide layer at high supersaturation condition and lens-shaped copper silicide formation at the Si/SiO2 interface at lower temperatures. Shacham-Diamand et al. [22] found that the CV characteristics of an MOS capacitor made up of copper and silicon oxide change drastically when copper reaches the Si/SiO2 interface under a bias-thermal stress and a 5-nmTi barrier can isolate the oxide from this copper effect. Gupta et al. [23] studied copper diffusion in amorphous phosphorus silicate glass and hydrogenated silicon nitride and found that the copper diffusion coefficient is temperature dependent and the activation energies are 0.5 and 1.1 eV, respectively. Raghavan et al. [24] investigated the copper diffusion related leakage current through several dielectric films as a function of electric field and

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CMOS Past, Present and Future

temperature and reported 1.2 eV activation energy for copper diffusion in thermal oxide and proposed a three-step model to explain the I-t characteristics. Loke et al. [25] systematically explored copper drift in six low-k organic polymer dielectrics and found that polymer cross-linking can slow down copper drift and polar functional groups in polymers can accelerate copper drift. Du et al. [26] investigated the competition between bulk and surface copper diffusion in a fluoropolymer low-k dielectric and found that below the glass transition temperature, plasma treatments, and sputtering limit copper diffusion into the bulk of the polymer and increase the surface reactivity. Rogojevic et al. [27] investigated the copper diffusion behavior in nanoporous silica and found two copper diffusion paths: bulk and surface. They also established a model to simulate the leakage current during bias-thermal stress. Lanckmans et al. [28] found that the copper drift rate increases when the k value of SiOC:H low-k dielectrics decreases, but remains always lower than that of plasma-enhanced chemical vapor deposited (PECVD) oxide. They also found that the copper drift mobility is lower in a porous inorganic dielectric than in thermal oxide. Chen et al. [29] found that copper ions existing in α-SiCN would act as trap states and could enhance the carrier transport.

8.5

Metal diffusion barriers

From the previous section, it is shown that copper diffusion into silicon and intermetal dielectrics can cause severe material property degradation and reliability concerns. Therefore, a copper diffusion barrier is indispensable to achieve a reliable ULSI chip with copper interconnects. This has already been briefly touched upon earlier in the copper damascene integration section. Nowadays, there are primarily two categories of copper diffusion barrier sin integrated damascene structures: intermetal and interlevel diffusion barriers. Intermetal diffusion barriers are composed of metals and/or metal compounds and are deposited on the low-k dielectric trench and via sidewalls as well as at the bottoms before copper seed deposition. The diffusion barrier serves as cladding to isolate the copper wire from the low-k dielectric and as an adhesionenhancement layer for copper. Inter-level diffusion barriers are generally nonconductive dielectrics and are deposited on the post-CMP surface to seal the top (and/ or bottom) surface of the copper wire. To reduce the inter-line capacitance, the k value of inter-level dielectric barriers should be as low as possible. Silicon carbide (SiC) or silicon carbon nitride (SiCN) films are mostly used as the inter-level dielectric barrier materials [30], because their k values are lower than silicon nitride and their mechanical properties suffice. In some rare cases, silicon carbide is also attempted to be used as the intermetal diffusion barrier material [31]. Other possibilities include materials that combine SiCN and SiCO.

8.5.1 Intermetal barrier material selection The integration of intermetal diffusion barriers is much more challenging and the barrier material selection is very critical. Typically, the three material properties that most strongly affect the degree of intermetal barrier failure are (a) intrinsic barrier

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229

chemical or metallurgical reactivity with copper or substrate material, (b) density, and (c) microstructure. Therefore, the barrier material selection specifications for copper interconnects include [32,33] l

l

l

l

l

l

l

l

high thermal and structural stabilities against neighboring insulator and conductor materials, excellent adhesion characteristics to adjacent metallization layers, good continuity and conformality in aggressive device structures, suitable texture to drive the nucleation and growth of subsequent copper conductor layers with the desirable morphology, enhanced resistance to thermal and mechanical stresses, acceptable thermal and electrical conductivities, low overall contact resistance for the resulting metallization stack, and excellent compatibility with integrated circuitry fabrication flows, including the ability to be deposited within the thermal budget limitations of microelectronics processing.

Currently, most intermetal diffusion barriers are refractory metal or metal compounds. With the continuous dimension scaling of the metal wire width to effectively reduce the interconnect resistance, more copper is required to be accommodated within the limited space of intermetal low-k dielectric trenches. Therefore, owing to the higher resistivity of metal diffusion barriers, the thickness of intermetal diffusion barriers is expected to continuously scale in the next decade (Fig. 8.13), that is, the proportion of barrier materials in the low-k trench should be minimized. However, with the continuous shrinking of the metal barrier thickness, the metal diffusion barrier integrity arises as an integration and reliability challenge. Furthermore, metal diffusion barrier scan influence the morphology of the copper seed layer and that of the plated copper [34]. Assessing the metal diffusion barrier integrity is a challenging task. For blanket films, ellipsometric porosimetry (EP) technology is demonstrated to be a fast, simple, and accurate evaluation method [35,36], in which low-density killer defects are visualized by toluene trapped around the defect beneath the barrier. The method is applicable to patterned structure as well [36]. However, the barrier integrity characterization for electrical reliability is more challenging and is widely discussed in the literature. 3 MPU M1 barrier thickness (nm)

2.5 2 1.5 1 0.5 0 2010

2015

2020 Year

Fig. 8.13 M1 barrier thickness scaling prediction. Source: ITRS 2013.

2025

2030

230

CMOS Past, Present and Future

8.5.2 Metal diffusion barrier deposition There are several technology options to deposit thin intermetal diffusion barriers on the low-k trench sidewall, including physical vapor deposition (PVD), CVD, atomic layer deposition (ALD),and self-assembled monolayer (SAM). Typical intermetal diffusion barrier materials include Ti, Ta, W, and their nitride compounds due to the quite low copper diffusion coefficient in these materials [37,38]. Kaooyeros et al. investigated the applicability of different refractory metals and their binary and ternary nitride compounds as the diffusion barrier and liners for advanced copper interconnect and predicted that ALD or ALCVD barriers would be the future technologies to satisfy the close-to-zero barrier thickness [32,33]. Zeng et al. [38] compared the interaction of several refractory metal diffusion barriers with HSQ and found an inhibited phase transformation of the Ta film on HSQ upon annealing, contrary to that of PE-TEOS. This finding indicates that the realization of ultrathin metal barriers on low-k dielectrics is extremely challenging. In the remaining part of this section, the most important barrier deposition technologies, PVD and ALD, will be introduced.

8.5.2.1 PVD barrier deposition PVD is the mainstream technology for metal diffusion barriers in modern copper interconnect integration. Various sputtering-based PVD technologies have been developed to enhance deposition on modest (>1:1) aspect ratio (AR) features, such as high sample temperatures, bias sputtering, collimated sputtering, and ionization [39]. Nowadays, the most widely used PVD technology for interconnect application with a very high aspect ratio is a derivative of PVD—ionized PVD (i-PVD) [40–42]. i-PVD barriers have the merits of good step coverage, wide range of candidate materials, and high deposition rate. Among the material candidates for PVD metal diffusion barriers, Ta is more frequently adopted. To enhance the adhesion between Ta and low-k dielectrics, a PVD TaN layer is usually deposited on the low-k trench sidewall before Ta deposition. The Ta(N)/Ta bi-layer is thus the typical intermetal diffusion barrier stack for current technology nodes and is being under optimization.

8.5.2.2 ALD barrier deposition PVD technologies are limited by their step coverage, especially for high AR features. Exploration of alternative deposition technologies is mandatory for advanced interconnects, among which ALD is the most promising one, due to the uniform and conformal step coverage, ultrafine thickness control, and diverse material options. ALD technology makes use of alternating inflating and purging of precursor gases or vapors to forma stable film with a constant growth rate by the surface absorption or surface reaction, which is meant to provide exceptional control of the thickness of the thin film. Leskel€a et al. [43] discussed the principle of the ALD method and the application of plasma in ALD technology. There are already a lot of reports on the successful application of ALD technology for interconnects. Moreover, Lim et al. [44] even

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231

demonstrated a wide range of material options (copper, cobalt, iron, and nickel) by a hydrogenation mechanism, which could extend ALD technology to ultrathin copper seed deposition. As chip features shrink below the 45 nm technology node, ALD is becoming an essential technology for making such small chips. However, the drawback of ALD technology is also apparent. For porous low-k dielectrics, the precursor of the ALD barrier materials can diffuse into the bulk dielectric and degrade the physical and electrical properties of the low-k dielectric. Therefore, a well-controlled pore sealing the prior ALD process is critical for the successful application of ALD barriers on porous low-k. Currently, the common technologies for pore-sealing are mainly pre-ALD treatments which include thin film deposition, plasma surface interaction, and surface reconstruction [4].

8.6

Reliability of copper metallization

Metallization reliability mainly refers to electromigration (EM) and stress induced voiding (SIV), and has already a long history of investigation. However, with the replacement of aluminum by copper, the differences in material properties and integration schemes make most of the experiences gained from the aluminum era not applicable to the copper interconnect, and require systematic reliability studies [45]. In this section, the reliability of copper interconnects will be briefly discussed.

8.6.1 Electromigration basics Electromigration was first identified as a failure mechanism in aluminum interconnects 50 years ago [46,47] and has been a major BEOL reliability concern ever since, due to the continuous dimension scaling and the accompanied increase in current density. The basic physics behind electromigration is the electron wind driven metallic ion diffusion [48]. J¼


DC Z
eE kT

Ω

∂σ ∂x



(8.4)

where J is the atomic flux, D the diffusivity, C the atom concentration, K the Boltzmann’s constant, T the temperature, Z the effective charge number, e the fundamental electronic charge, E the electric field, x the atomic volume, and ∂ σ/∂ x the stress gradient along the metal line. The stress evolution with time can be described by the Korhonen model [49] 
 ∂σ ∂ DBΩ ∂σ Z
eE ¼ + ∂t ∂x kT ∂x Ω

(8.5)

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where B is the effective modulus of the metal dielectric composite. On the other hand, most often, the semi-empirical Black’s Law is used to analyze the electromigration data at accelerated conditions and do the extrapolation to use condition [47]
n
 1 Ea MTTF ¼ A exp j kT

(8.6)

where A is an empirically determined constant, j the current density, n the current density exponent, Ea is the thermal activation energy to electromigration failure. The use lifetime can be written as [50]
n 
TTFuse jtest Ea 1 exp ¼ MTTFtest k T use juse

1 T test



exp ð Nσ Þ

(8.7)

where TTFuse is the time to failure at use conditions and represents the required lifetime of the product, MTTFtest the median time to failure at accelerated test conditions, jtest the test current density, Ttest the test temperature, Tuse the use temperature, N a constant that relates MTTF with a time-to-failure at a different fail percent and is determined by product specifications, σ the deviation in time to failure.

8.6.1.1 Copper electromigration With the introduction of copper as the metallization material for advanced interconnect, the existing knowledge on aluminum electromigration must be updated due to the different material properties and integration schemes than aluminum. Copper has a higher melting point and is more electromigration resistant. Therefore, for overall reliability, the differences in material properties favor copper interconnects over aluminum interconnects. However, the integration schemes for copper interconnects differ significantly from those for aluminum and may introduce new reliability concerns [45]. For copper interconnects, the damascene process integration scheme induced electromigration formation has the following features: 1. Via related failure dominant. Owing to the copper mass flow divergence near the copper via bottom, for dual damascene copper interconnect via/line structures, there are two distinct electromigration failure modes: via depletion (Fig. 8.14A) and line depletion (Fig. 8.14B). Copper interconnects without via connections typically demonstrate more robust electromigration behavior than structures with via connections, assuming no obvious process defects [45,51,52]. 2. Interface dominant copper diffusion. As shown in Table 8.3, the copper migration rate of copper damascene interconnects can be either along the copper/dielectric barrier (top surface of copper wires) or copper/metal diffusion barrier interface, depending on the sample preparation [52].

To improve the electromigration resistance of the copper interconnect, there are mainly two approaches: alloying (with Ti or Sn) and metal layer capping (CoWP, TaN/Ta), both of which have shown apparently improved electromigration resistance [52].

Advanced interconnect technology and reliability

233

Void

(A)

via depletion

(B)

line depletion

Fig. 8.14 Two examples of electromigration failure locations. (A) Via depletion. (B) Line depletion.

Melting point and diffusivities of Cu and Al (DI is lattice diffusivity and Dgb is grain boundary diffusivity) [53]

Table 8.3

Cu

Al

Melting point (K)

Temperature ratio 373 K/(T m)

Diffusivities at 100°C (cm2/s)

Diffusivities at 350°C (cm2/s)

1356

0.275

DI ¼ 7  10 28 Dgb ¼ 3  10 15 Ds ¼ 10 12 DI ¼ 1.5  10 19 Dgb ¼ 6  10 11

DI ¼ 5  10 17 Dgb ¼ 1.2  10 Ds ¼ 10 8 DI ¼ 10 11 Dgb ¼ 5  10 7

933

0.4

9

8.6.2 Stress-induced voiding Stress-induced voiding (SIV) or stress migration is the migration of the ions of a metal conductor due to the high tensile stresses in the interconnect after processing (e.g., after passivation deposition) and results in void formation. The stresses are caused by the difference in thermal expansion between the metal layer and the Si-substrate on the one hand and the metal and the passivation layer or intermetal dielectric on the other. The effects of SIV include resistance change, void induced open circuits, hillocks, or whisker growth induced shorts between lines or layers. These can significantly degrade the electrical properties of the ULSI chip, and therefore SIV is also an important reliability concern for advanced copper metallization.

8.7

Reliability of advanced intermetal dielectrics

Dielectric reliability includes two major fields: mechanical reliability and electrical reliability. In this chapter, only electrical reliability is addressed. The electrical reliability of intermetal dielectrics can be divided into two parts: leakage and breakdown. Both parts will be discussed in this section.

8.7.1 Leakage mechanism of intermetal dielectrics In copper damascene structures, under an electrical stress, there will be a minuscule level of electrical transport through the insulator between two neighboring copper wires, which behaves as a stressed metal-insulator-metal (MIM) capacitor. On the

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CMOS Past, Present and Future

one hand, the leakage current will increase the power consumption of the chip and heat the chip, but on the other hand, the leakage current can degrade the low-k dielectric and erode the lifetime margin. With the continuous line width scaling, this leakage current could become a critical reliability concern. Moreover, it is believed that there is some correlation between the leakage current mechanism and the dielectric reliability model. Therefore, an insight into the electronic transport mechanism of low-k dielectrics is essential for maintaining a reliable semiconductor chip. In general, under electrical stress, the current through an insulator consists of two components—the transient and steady state conductions. At a low electric field, the following phenomena may take place [54]: 1. Charging of the geometrical vacuum capacitance 2. Fast kinds of polarization, for example, resonance and some types of dipole orientation polarizations 3. Slow types of dipole relaxation polarization 4. Flow of conduction current caused by the motion of charges injected from the electrodes or generated by thermal ionization of impurities or of the dielectric itself, or produced by photoionization or high-energy radiation ionization 5. Relaxation polarization of the Maxwell-Wagner type caused by micro or macroheterogeneities of a continuous or discrete nature 6. Electrode polarization due to complete or partial electrode blocking 7. Trapping of charge carriers in the bulk of the dielectric

In insulating films, the basic conduction processes include Schottky emission, Frenkel-Poole emission, tunneling, space-charge limited, ohmic, and ionic conductions [55]. A lot of research on electronic conduction of insulators have been published, especially on silicon oxide. This forms the background knowledge for the low-k leakage/conduction mechanisms.

8.7.1.1 Electronic transport in silicon thermal oxide Silicon thermal oxide is widely used in semiconductor device structures and in most cases functions as the insulation layer in MOS structures. Although an MOS structure is significantly different from a damascene structure, which is more like a MIM configuration, the in-depth knowledge of electrical transport in silicon oxide can help our understanding of the leakage mechanism in low-k dielectrics, because most low-k dielectrics are silica based. For three decades, silicon dioxide formed the perfect gate dielectric material, successfully scaling from a thickness of 100 nm 40 years ago to a mere1.2 nm at the 65 nm process node. The line spacing in the advanced copper damascene structure is already in the similar range as the gate oxide thickness four decades ago. Therefore, a comprehensive understanding of the conduction mechanism evolution of gate oxide with thickness is also very directive for the BEOL dielectrics. Functioning as the isolation layer between the silicon channel and the doped polysilicon electrode, gate oxide bears a high field stress under normal operating conditions, leading to a quantum mechanical tunneling current.

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qVox Fb

FN DT

SiO2

n+ silicon

p silicon

Direct tunneling Fowler-Nordheim tunneling

Fig. 8.15 Energy band diagram for an NMOS structure under a negative gate bias.

Fowler-Nordheim (FN) tunneling and direct tunneling are the main conduction mechanisms for gate oxide. FN tunneling refers to the electron tunneling from the gate to the substrate when a negative bias is applied in an NMOS device, as shown in Fig. 8.15, and the current density JFN can be formulated as [56] J FN ¼ A
E2OX exp




B EOX



(8.8)

q3 me 16π 2 ℏΦb m∗

(8.9)

pffiffiffiffiffiffiffiffi 3=2 4 2m∗ Φb B¼ 3qℏ

(8.10)

A¼

where EOX is the electric field across the gate oxide, q the elementary charge, ℏ the reduced Planck constant, me the electron rest mass, m* the effective mass of electrons in the dielectric, and Φb is the barrier height at the silicon/dielectric interface. FN tunneling dominates at a high field, and at a low field direct tunneling becomes the major mechanism due to the change of the potential barrier shape, as shown in Fig. 8.15. Direct tunneling is only significant in ultrathin dielectric films ( 0 is the shape parameter, η > 0 the scale parameter, and γ is the location parameter of the distribution.

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The Weibull failure rate function, λ(T), is given by λðT Þ ¼


 f ðT Þ β T γ β ¼ Rð T Þ η η

1

(8.17)

Hence, the shape parameter, β, determines the evolution trend of the failure at eλ(T), that is, l

l

l

β < 1 ! decreasing failure rate; β ¼ 1 ! constant failure rate; β > 1 ! increasing failure rate.

8.8.1.2 Log-Normal distribution The Log-Normal distribution is the probability distribution of any random variable whose logarithm is normally distributed. The corresponding probability density function is [73] 1 f ðT Þ ¼ pffiffiffiffiffi exp Tσ 2π

"

ð ln T μÞ2 2σ 2

#

(8.18)

for T > 0, where μ and σ are the mean and standard deviation of the variable’s logarithm. By adjusting these parameters, Log-Normal distribution can also express increasing and decreasing failure rates and be used to represent one of the three life periods (infant mortality, useful life, and wear-out).The difference between the Weibull and Log-Normal distributions mainly resides in the lower 5% region. For a small sample size, these two models can be interchanged. The relationship between the shape parameter (β) of Weibull distribution and the standard deviation of the variable’s logarithm (σ) is as follows [74]: π σ  pffiffiffi 6β

(8.19)

8.8.2 Breakdown acceleration models Most TDDB measurements are carried out at accelerated conditions, for example, high electric fields and high temperatures. To predict the lifetime at use condition, an appropriate acceleration model is needed to do the extrapolation. There are several popular models developed for gate oxide and some of them are also used for intermetal dielectrics.

8.8.2.1 Gate oxide models Currently, there are mainly three breakdown acceleration models for gate oxide, that is, the 1/E model, the E-model, and the power-law model [11].

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1. The 1/E model is based on the anode hole injection model and the time-to-breakdown (tBD) is given as


G tBD ¼ τ0
exp Eox



(8.20)

where τ0 is a constant, Eox the oxide field, and the values for G ¼ B + H vary from 290 to 350 MV/cm, depending on oxide thickness and stress type [55]. 2. The E model predicts a linear dependence of the time-to-breakdown on the logarithm of the oxide field: tBD ¼ t0
exp ðγ
Eox Þ

(9.21)

where t0 and γ are constants. The E-model was first an empirical model and was given a physical explanation later [75]. 3. The power-law model has a shorter history and is firstly used for ultrathin layers stressed at low voltages where direct tunneling dominates [76–79]. The equation is given as tBD ¼ t0
V nG

(9.22)

where VG is the gate voltage and n on the order of 40–45. All the three models have similar behaviors at high electrical stresses and only deviate from each other when extrapolated to a low field.

8.8.2.2 Models for intermetal dielectrics The accelerated breakdown models for intermetal dielectrics are mainly inherited from gate oxide. The E model was the one most widely adopted. As already discussed before, a copper diffusion-based physical explanation has been developed for the application of the E model in intermetal dielectrics [67]. More package level dielectric reliability tests show that the power-law model is a more appropriate model.

8.9

The future of interconnect: beyond Cu and low-k

For an advanced interconnect, which consists of a copper metal line and low-k intermetal dielectrics, the continuous downscaling is so challenging that some alternative technology is needed for the future on-chip interconnect. For the conductor, nanowire and graphene are under investigation by some institutions. For intermetal dielectrics, air gap, which has the targeted dielectric constant, will be the endpoint. The challenge for air gap integration is the degraded mechanical property. Now, air gap is only implemented in interconnect structures in higher metal levels. Device and memory can also be implemented in the BEOL part. For example, the newest memory product from INTEL, Optane128-GbXPointmemory, has the storage array between Metal4 and Metal5. There is also research work to include FET devices in the BEOL to create an active interconnect. Therefore, functional interconnect or

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active interconnect will be another important direction for the future interconnect technology research and development. Another aspect of the future interconnect technology is the emerging Si-photonics technology. For signal transmission at low levels, electron movement-based interconnect is and will be the only feasible technology. However, for signal transmission at higher levels (e.g., module level or chip level), photon-based interconnect is very promising in terms of RC delay and power consumption [80].

8.10

Summary

In summary, on-chip interconnect is evolving together with CMOS technology. It is and will be one of the most important technologies in integrated chip technology. The interaction between the interconnect material, process integration, and reliability is so complicated that for each technology node, in-depth process optimization and reliability characterization and analysis are critical to the success of the whole CMOS chip process flow development.

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Final words

As presented in different chapters of this book, there are several issues and challenges to be solved or considered in the development of complementary field effect transistor (CMOS). The aggressive downscaling causes the parasitic transistors to grow fast and to play a crucial role in transistor performance. Therefore, we need more revolutionary ideas to take CMOS technology forward into the future. The chipmakers have to find new paths not only to continue the 3D design, but also to optimize the power gain and cost-effective manufacturing when we approach the era beyond CMOS. FinFETs will continue to be dominant for high-performance logics; meanwhile, its original design may change to the gate-all-around (GAA) design to obtain a better transport in the channel. There is also a high potential for a transition to vertical nanowire transistors when there will be no possibility for further the effect of gate length downscaling due to the limitation of fin width scaling. These vertical transistors may further be developed to a GAA design, as a final step in the evolution of these devices. It is also a strong attitude to integrate high-mobility materials, for example, silicon germanium, germanium, or possibly III-V materials to enhance the drive current in the transistors probably by an order of magnitude. After all, the Si technology is approaching the end of International Technology Roadmap for Semiconductors (ITRS) and we will face the historical brick wall by 2024. The scaling of poly pitch, metal pitch, and cell-height scaling will gradually slow down by the close of the doom year. It is expected that a new roadmap, the so-called International Roadmap for Devices and Systems (IRDS), will be introduced where the development of new transistor architectures, chip stacks, and systems will be included. The beyond-CMOS era will aim at making technologies that complement CMOS and not replace it. Therefore, a deep understanding of how the device fabrication and its performance are connected to a higher-level circuit or system function is necessary. The interesting point is which challenges and difficulties we must conquer in the future.

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Acronyms

1D 2D 3D ac BD BEOL BJT BTBT CAFM CB CBKR CD CMOS CVD CTLM D DB DE DE2 DOS DP DUV DXRL EUVL EBL FD FLP FGA FN GB GeOI GR HEMT HJ HP IL IOT M MI MESFET MIS

one-dimensional two-dimensional three-dimensional alternating current breakdown back end of line bipolar junction transistor band-to-band tunneling conducting atomic force microscopy conduction band cross-bridge Kelvin resistor critical dimension complementary metal-oxide-semiconductor chemical vapor deposition circular transmission line measurement drain dangling bond double exposure double etch density of states double patterning deep ultraviolet deep X-ray lithography extreme ultraviolet lithography electron-beam lithography Fermi-Dirac Fermi-level pinning forming gas annealing Fowler-Nordheim (tunneling) grain boundary germanium-on-insulator generation-recombination high electron mobility transistor hetero-junction high-purity interfacial layer internet-of-things metal the first metal layer metal-semiconductor field effect transistor metal-insulator-semiconductor

252

MOSFET NUV NGL OPC PD PDA PSM QW RT RET S SADP SAQP SAM SBH SCC SI SIV SOI SRB SRH SSRM STM TAT TCAD TD TDD TDDB TLM TMD TEM TRPL TFET VB VS XRL XTEM

Acronyms

metal-oxide-semiconductor field-effect transistor near ultraviolet next-generation lithography optical proximity correction point defect post-deposition anneal phase shift mask quantum well room temperature reticle enhancement technique source self-aligned double patterning self-aligned quadruple patterning self-assembled monolayer Schottky barrier height space charge cylinder semiinsulating stress-induced voiding silicon-on-insulator strain-relaxed buffer Shockley-Read-Hall scanning spreading resistance microscopy scanning tunneling microscopy trap-assisted tunneling technology computer-aided design threading dislocation threading dislocation density time-dependent dielectric breakdown transmission line measurement transition metal dichalcogenide transmission electron microscopy time-resolved photoluminescence tunnel FET valence band virtual substrate X-ray lithography cross-sectional transmission electron microscopy

Symbols A0 (cm V21 s21 K23/2) aed (nm21) af (nm) as (nm) b b (nm) c (nm) C (F)

constant line density of occupied states on a dislocation lattice parameter of relaxed film lattice parameter of relaxed substrate Burgers vector magnitude of the Burgers vector spacing dangling bonds in the dislocation core capacitance

Acronyms

cmaj (cm3 s21) cmin (cm3 s21) cn (cm3 s21) cp (cm3 s21) Dit (cm22) E0 (eV) EA (eV) EAj (eV) EC (eV) Ed (eV) EDe (eV) EDh (eV) EF (eV) EG (eV) Ei (eV) EM (eV) en (s21) ep (s21) ET (eV) EV (eV) f (s21) F (V cm21) fed fm(%) gAj gDi gn gm h (nm) I (A) Idefect (A) Ion (A) kB (J K21) KT (s21 K22) L (nm) mn* (g) mp* (g) n (cm23) NAj (cm23) NC (cm23) Nd (cm22) NDi (cm23) ni (cm23) NMF (cm21) Nnuc (cm22) nT (cm23) NS (cm22) NT (cm23)

253

capture coefficient for majority carriers capture coefficient for minority carriers capture coefficient for electrons capture coefficient for holes density of interface states energy level of a dislocation at zero charge activation energy energy level of acceptor j bottom of the conduction band dislocation level in the band gap shallow intrinsic dislocations levels at the CB shallow intrinsic dislocation levels at the VB Fermi level band-gap energy intrinsic energy level level of metals in the band gap emission rate for electrons emission rate for holes trap energy level top of the valence band frequency electric field fractional occupation of the dislocation level lattice mismatch degeneracy factor of acceptor j degeneracy factor of donor i degeneracy factor of an acceptor level transconductance thickness of epi layer current current per defect on-current Boltzmann constant prefactor emission rate size of heteroepitaxial mesa (island) effective mass of free electrons effective mass of free holes free electron density concentration of acceptor j density of states in the conduction band dislocation density concentration of donor i intrinsic carrier density misfit dislocation density dislocation nucleation density free electron concentration corresponding with the Fermi level at ET sheet carrier density deep level density

254

N0T (cm23) 23 N2 T (cm ) 23 NV (cm ) p (cm23) pT (cm23) q (C) Q (C) R (cm) T (K) tepi (cm) tp (s) V (V) VTH (V) vthn (cm s21) vthp (cm s21)

Acronyms

density of neutral deep levels density of negatively charged deep levels density of states in the valence band free hole density free hole concentration corresponding with the Fermi level at ET elementary charge (¼1.602  10 19 C) charge on a dislocation radius of the space charge cylinder temperature epilayer thickness duration of a filling bias pulse voltage threshold voltage thermal velocity of electrons thermal velocity of holes

Greek Symbols α (o ) Δp (cm23) ε (%) ε0 (F cm21) εs ΦB (V) η (%) λ (cm) λD (cm) μ (cm2 V21 s21) μ0 (cm2 V21 s21) μd (cm2 V21 s21) μn (cm2 V21 s21) μp (cm2 V21 s21) μsat (cm2 V21 s21) σ d (cm2) σ n (cm2) σ p (cm2) τ d (s) τ en (s) τ g (s) τ gdis (s) τ min (s) τ cn (s) τ cp (s) τ r (s) τ rdis (s) τ SRH (s)

angle between dislocation axis and Burgers vector excess (injected) hole density strain permittivity of vacuum (8.85  10 14 F cm 1) dielectric constant of a semiconductor potential barrier built up around a charged dislocation internal quantum efficiency screening length debye screening length low-field mobility low-field mobility without dislocation mobility carrier mobility associated with dislocation scattering electron mobility hole mobility saturation mobility minority capture cross section for dislocations capture cross section for electrons capture cross section for holes carrier lifetime associated with dislocations emission time constant for electrons generation lifetime generation lifetime of dislocations minority carrier lifetime capture time constant for electrons capture time constant for holes recombination lifetime recombination lifetime of dislocations shockley-read-hall lifetime

Index

Note: Page numbers followed by f indicate figures and t indicate tables. A Alloying method, 165, 172 Ambipolar conduction, 115 Aspect ratio trapping (ART) technique, 108–109, 108f Atomic layer deposition (ALD), 90, 92–97, 96f, 230–231 AuGeNi contact scheme, 114 B Back-end-of-line (BEOL), 215 Bernal stacking, 115 Bilayer graphene (BLG), 115–116 Bilayer pseudospin field-effect transistor (BiSFET), 117 Bi-Modal distributions, 240 Black’s Law, 231–232 Boltzmann carrier distribution, 21–22 Boltzmann’s constant, 10, 231–232 Boron-interstitial clusters (BICs), 137–139 Boron (B) junctions in silicon boron-interstitial clustering, 137–139 chemical profiles, SIMS, 132, 132f diffusion mechanism, 132–135 TED, 126–127, 136–137 Bragg’s condition, 60 Breakdown acceleration models, 241–242 Burgers vector, 55–56 C Carbon nanotubes (CNTs), 197, 200 Carrier activation enhancement (CAE) techniques, 194 CBO. See Conduction band offset (CBO) Channel materials Ge channels, 108–110, 109t GeSn channel, 110–111 high-mobility channels, 105–106, 106t III-V materials, 111–114

Si CMOS technology, 105 SiGe channel, 107–108 two-dimensional channel materials graphene channel, 114–117 graphene-like channel, 117–118 IOT, 114 TMDs, 114 Channel resistance (Rc), 157 Chemical mechanical polish (CMP), 113f Chemical vapor deposition (CVD), 41, 110, 115, 118, 222, 236 Circular transmission line measurement (CTLM), 160–163 CNTs. See Carbon nanotubes (CNTs) Complementary metal-oxide-semiconductor (CMOS), 110, 114, 117–118 advantage of, 69 channel materials, Ohmic contacts as-formed end-contacts, 197–198 CNTs, 200 edge-contacts and end-contacts, 198 graphene, 197 hetero-contacts, 199 low dimensional materials, 197 PEI doping, 199–200 postmetallization annealing, 197–198 TMDs, 198–199 UVO process, 197 SiO2 dielectric and poly-Si gate electrode, 70, 70f strain, SiGe layers DSL, 52–54 epitaxy of stressor materials, 47–51 SMT process, 51–52 zero static power consumption, 69 Condensation technique, 107–108, 107f Conduction band offset (CBO), 110, 166–167, 174, 189 Constant electric field scaling, 20–22, 21f, 21t Contact technology. See Ohmic contacts

256

Copper interconnect system BEOL, 215–216 copper metallization reliability electromigration (see Electromigration (EM)) SIV/stress migration, 233 damascene integration dual damascene integration, 217–218, 218–219f single damascene integration, 217, 217f FEOL, 215 interaction dielectrics, 227–228 silicon, 227 intermetal dielectrics (see Intermetal dielectrics) low-k dielectrics air gap implementation, 226 classification and characterization, 224, 225t integration challenges, 225–226 material composition, 222–223 porosity, 223–224 Manhattan/diagonal (X-architecture), 216 metal diffusion barriers ALD barrier deposition, 230–231 intermetal barrier material selection, 228–229 PVD barrier deposition, 230 new copper integration scheme, 219–221 on-chip interconnects, 215 reliability statistics and failure models breakdown acceleration models, 241–242 probability distribution functions, 240–241 resistance, 218–219 ULSI circuits, 215 Critical dimensions (CD), 26, 215 Critical thickness, strained SiGe layers empirical model, 56–57 growth temperatures, 57, 58f MB and DT models, 57, 57f MB model, 55–56, 55f patterned substrates, 58–59 Cross-bridge Kelvin resistor (CBKR) structure, 160 Cryogenic implantation, 130–131 CVD. See Chemical vapor deposition (CVD)

Index

D Damascene integration dual damascene integration, 217–218, 218–219f single damascene integration, 217, 217f Datta-Das spin field-effect transistor, 34–35 Deep X-ray lithography (DXRL), 29 Density functional theory (DFT), 200 Density-of-states (DOS), 105–106 DIBL. See Drain-induced barrier lowering (DIBL) Diffusion barriers ALD barrier deposition, 230–231 intermetal barrier material selection, 228–229 PVD barrier deposition, 230 Diffusion coefficient, 128–129 Dimensional scaling, device architecture constant electric field scaling, 20–22, 21f, 21t generalized scaling, 21t, 22 generalized selective scaling, 21t, 22 junctionless transistors, 25 SCEs, impact of FD SOI, 23 natural transistor length, 22–23 Direct tunneling, 235–236 Disorder-induced gap states (DIGS), 184–185 Dissociative mechanism. See Frank-Turnbull mechanism Distribution coefficient, 127–128 Dodson and Tsao (DT) model, 57, 57f Dopant diffusion, 128–130 Dopant segregation, 165, 169–172, 176–177, 186–188 Double exposure (DE) lithography process, 27, 28f Double patterning (DP) technology double exposure, 27, 28f self-aligned spacer patterning method, 27–28, 28f Drain-induced barrier lowering (DIBL), 13–14, 15f, 19–20 Dual channel heterostructures on insulator (DHOI), 45–46 Dual damascene integration, 217–218, 218–219f Dual metal/dual dielectric (DMDD), 90–91 Dual-metal process, 80 Dual metal/single dielectric (DMSD), 90–91

Index

Dual stress liners (DSL), 41, 52–54 Dynamic surface annealing (DSA), 178–179

E EBL. See Electron-beam lithography (EBL) Effective work function (EWF), 79–80 Elastic constants, 43, 43t Electromigration (EM), 215–216, 220–221 BEOL reliability, 231–232 copper electromigration, 232 electron wind driven metallic ion diffusion, 231–232 failure locations, 233f Korhonen model, 231–232 use lifetime, 231–232 Electron-beam lithography (EBL), 30 Ellipsometric porosimetry (EP) technology, 229 Embedded Si1–yCy (eSi1–yCy), nMOS carbon atoms, implantation/SPE approach, 54 critical thickness empirical model, 56–57 growth temperatures, 57, 58f MB and DT models, 57, 57f MB model, 55–56, 55f patterned substrates, 58–59 drive current vs. off current, 54, 55f HRRLMs, 60–62, 62–63f NBD analysis, HRTEM, 59–60, 60f 45-nm baseline process, 54, 54f Raman spectroscopy, 62–64 XRD measurement, 60 E model, 242 End-of-range (EOR) implantation, 130–131 Energy band diagram Frenkel-Poole emission, 236f NMOS, 235f Schottky emission, 236f Equilibrium model. See Matthews-Blakeslee (MB) model Equivalent oxide thickness (EOT), 75, 80–82, 86, 86f, 90 EWF. See Effective work function (EWF) Exfoliation technique, 115 Exponential distributions, 240 Extreme ultraviolet lithography (EUVL) technology, 29

257

F Fermi-Dirac distribution, 8–9 Fermi-level pinning (FLP), 110, 164–165 Fick’s first law, 128–129 Field-effect-transistors (FETs), 115, 198–199 Figures of merit (FOM), 9–12 FinFETs, 14 bulk silicon FinFET, 93–97, 94–95f length, width, and heigh, 14, 15f process flow of, 3, 4f PVD TiAl and ALD TiAlC, 95–97, 96f Flash-lamp annealing, 131, 144 Forming gas anneal (FGA), 178–179 Fowler-Nordheim (FN) tunneling, 235–236 Frank-Turnbull mechanism, 129 Frenkel-Poole emission, 71, 234, 236–237, 236f Front-end-of-line (FEOL), 215 Fully depleted silicon-on-insulator (FD-SOI), 78–79 G Gas-phase doping, 130–131 Gate-all-around (GAA) transistors, 13–14, 14f Gate-induced drain leakage (GIDL) current, 19–20 Gate-last process, 81 Gate oxide models, 241–242 Ge-condensation, 107–108 Ge/III-V semiconductors ALD, 188 AuGeNi, 195 CMOS applications, 188 dipole segregation, 186–188 dopant segregation, 186–188, 192 higher doping concentration, 193–195 interface passivation, 184–186, 192 MIS, 181–184, 189–191 Mo-based contacts, 196 MOSFETs, 188 Ni-InGaAs contacts, 195 nonalloyed contacts, 195–196 specific contact resistivity, 196 surface cleaning techniques, 196 Generalized scaling, 21t, 22 Generalized selective scaling, 21t, 22 Germanium (Ge) channels, 108–110, 109t GeSn channel, 110–111

258

Germanium (Ge) (Continued) n-type Ge junctions, 126–127 co-implantation, 142–144 intrinsic and extrinsic diffusion, 140–142 ion implantation, 141–142 point defect engineering, 144–146 p-type substrate, P implantation in, 139–140, 139f sheet resistance vs. junction depth, 125, 126f SiGe layers, strain engineering (see Strain engineering) Germanium on insulator (GOI), 45 Graphene channel, 114–117 Graphene-like channel, 117–118 Graphene nanoribbons (GNR), 115–117 H Hafnium aluminate (HfxAlyO), 87–88 Hafnium-based high-κ dielectrics hafnium aluminate, 87–88 hafnium lanthanate, 88–90 hafnium oxide (see Hafnium oxide (HfO2)) Hafnium lanthanate (HfxLayO), 88–90 Hafnium oxide (HfO2) band alignments HfO2/Hf1–xSixO2/Si heterostructure, 82–84, 83f HfO2/SiO2/Si, 82–84, 82f post deposition annealing, HfO2 thin films, 82–84, 84f stoichiometric and modified metal-oxide-Si interfaces, 82–84, 82f bandgap, 81–82 CMOS integration, 92–93, 92f dielectric constant, 81–82 EOT-physical thickness plot, 86, 86f gate leakage reduction, 86–87, 86f HfCx, TaCx, and TaN, 84, 85f HfO2(111) and Si(111), 84, 85f monoclinic phase, 82 nMOSFET, 92–93, 93f replacement gate process flow, 91, 91f tetragonal and cubic phase, 82 TiAl and TiN metals, 91 TiN/Ti/ALD-HfO2/Si gate stacks, 84, 85f Halo implantation, 2–3

Index

Hard-breakdown (HBD), 238 Heterogeneous epitaxy, 108–109 High-κ dielectric and metal gate bandgaps, dependence of, 75–76, 76f conduction band offset, 75–76, 76t, 77f dual metal gates, nMOS and pMOS threshold voltage, 78f, 79 effective work function, 79–80 equivalent capacitance density, 75 equivalent oxide thickness, 75 experimental bandgaps, 75–76, 76t FinFETs bulk silicon FinFET, 93–97, 94–95f PVD TiAl and ALD TiAlC, 95–97, 96f gate-last process, 81 hafnium-based high-κ dielectrics hafnium aluminate, 87–88 hafnium lanthanate, 88–90 hafnium oxide (see Hafnium oxide (HfO2)) high temperature fabrication process, 81 interface quality, 77 relative dielectric constants, 75–76, 76t relative permittivity, 75 single mid-gap metal, nMOS and pMOS threshold voltage, 78–79, 78f SiO2 interface and Si substrate, energy bands, 79–80, 80f SMSD, SMDD, DMSD, DMDD, 90–91 thermal budget, 81 thermal stability, 77 thermal treatment, 80 valence band offsets, 75–76, 77f work functions, CMOS devices, 79, 79f High-k metal-gate stress (HKMGS) technology, 41 High-mobility channels, 105–106, 106t High-resolution reciprocal lattice map (HRRLM), 60–62, 62–63f High-resolution transmission electron microscope (HRTEM), 59–60, 60f High temperature fabrication process, 81 Hopping conduction, 71 Hydrogen-silsesquioxane (HSQ), 224 I Integrated circuits (ICs), 1, 69 Intel 14-nm technology, 227f

Index

Intel processors, transistor counts growth, 69, 70f Interface passivation, 165 Interfacial layers (ILs), 109 Intermetal dielectrics breakdown acceleration models, 241–242 breakdown characteristics copper diffusion, 237–238 moisture absorption, 238–239 porosity influence, 239 leakage mechanism, 233–237 International technological road map semiconductor (ITRS), 3, 72 Internet-of-things (IOT), 114, 117–118 Interstitialcy diffusion mechanism, 129–130 Intrinsic point defects, 126–129 Ion implantation (II), 126–127, 130–131, 141–142, 146 J Junctionless transistors (JNTs), 25 K Kickout mechanism, 129 Korhonen model, 231–232 L Laser annealing, 110 Leakage mechanism conduction process, 234 electronic transport intermetal dielectrics, 236–237 in silicon thermal oxide, 234–236 low electric field, 234 power consumption, 233–234 Lithography double patterning technologies, 27–28 electron-beam lithography, 30 EUVL technology, 29 patterning transfer process, 26 resolution enhancement, 26–27 Rayleigh’s Law, 26 RETs, 29–30 LOCal oxidation of silicon (LOCOS), 20, 107–108 Log-Normal distributions, 240–241 Low-k dielectrics

259

air gap implementation, 226 classification and characterization, 224, 225t integration challenges, 225–226 material composition, 222–223 porosity, 223–224 Lowly doped drains (LDDs), 22 Low operation power (LOP), 88–89 M Matthews-Blakeslee (MB) model, 55–57, 55f, 57f Metal-induced gap states (MIGS), 164–165, 165f Metal-insulator-metal (MIM), 233–234 Metal–insulator–semiconductor (MIS), 110, 113, 165–167, 173–174, 181–184, 189–191 Metal–oxide–semiconductor field-effect transistor (MOSFET), 110–113, 115–116, 116f accumulation, 5–6, 5f applications, 1 biaxial and uniaxial strained Si channels, 44–47 characteristics for, 2 depletion, 5–6, 5f devices, scaling of, 69 discovery of, 1 FOM, 9–12 gate formation, 2–3 Halo implantation, 2–3 IC production, 1 inversion operation mode, 5–7, 5f MOSFET structure, evolution of, 12–15 nMOSFETs and pMOSFETs, 1–2, 2f notations, 3 p-type silicon substrate, energy band diagram of, 4, 4f Si–SiO2 electron energy barrier, 4–5 strong inversion operation mode, 7–9, 7f terminal contacts, 1 3D FinFET, 1, 2f, 3, 4f tunneling current, SiO2 gate dielectric, 71, 71f 2D planar MOSFET, 1, 2f, 3, 4f Methyl-silsesquioxane (MSQ), 224 Microwave annealing, 110, 131, 146

260

Index

Nanobeam diffraction (NBD) technique, 59–60, 60f Next-generation lithography (NGL), 29 Normal distributions, 240

low specific contact resistivity characterizations multiring CTLM structure, 160–163 refined TLM structure, 163–164 modern vs. traditional CMOS, 159f Si/SiGe substrate alloying method, 172 dopant segregation, 169–172, 176–177 FLP, 164–165 higher dopant concentration, 177–180 interface passivation, 167–169, 174–176 MIGS, 164–165 MIS, 166–167, 173–174 Optane128-GbXPointmemory, 242–243 Optical proximity correction (OPC), 29, 30f

O

P

Ohmic contacts, 110, 114, 162 channel resistance, 157 CMOS channel materials as-formed end-contacts, 197–198 CNTs, 200 edge-contacts and end-contacts, 198 graphene, 197 hetero-contacts, 199 low dimensional materials, 197 PEI doping, 199–200 postmetallization annealing, 197–198 TMDs, 198–199 UVO process, 197 contact-to-poly pitch, 157 Ge/III-V semiconductors ALD, 188 AuGeNi, 195 CMOS applications, 188 dipole segregation, 186–188 dopant segregation, 186–188, 192 higher doping concentration, 193–195 interface passivation, 184–186, 192 MIS, 181–184, 189–191 Mo-based contacts, 196 MOSFETs, 188 Ni-InGaAs contacts, 195 nonalloyed contacts, 195–196 specific contact resistivity, 196 surface cleaning techniques, 196 ITRS roadmap requirements, 158f

Pattern dependency, 48 Phase shift masks (PSMs), 30 Physical vapor deposition (PVD), 230 Piezoresistance coefficients, 47 Planck’s constant, 159, 235 Plasma enhanced atomic layer deposition (PEALD), 95 Plasma-enhanced chemical vapor deposited (PECVD) oxide, 227–228, 237 Point defect (PD), 126–129, 144–146 Poisson distributions, 240 Poisson ratio, 43, 55–56 Polyethyleneimine (PEI), 199–200 Polysilicon depletion effect, 72–74, 74f Polysilicon (poly-Si) gate electrode boron penetration, 72–74 CMOS transistor structure, 70, 70f high-κ dielectric, compatibility to, 72–74 MOSFETs, tunneling current in, 71, 71f polysilicon depletion effect, 72–74, 74f Positive-bias-temperature instability (PBTI), 90 Positron annihilation lifetime spectroscopy (PALS), 142 Post deposition annealing (PDA), 82–84, 87–88 Postdeposition H2 annealing (PDHA), 190 Power-law model, 242 Pre-amorphization implantation (PAI), 143–144, 179

Molecular beam epitaxy system (MBE), 169 Moore’s law, 19, 69, 70f, 218–219 Multigate field effect transistor (MuGFET), 13–14, 15f Multiimplantation multiannealing (MIMA), 193 Multi-Model distributions, 240 Multiring circular transmission line measurement (MR-CTLM), 160–163 N

Index

Probability distribution functions (PDF), 240–241 Pseudobreakdown (PBD), 238 R Raman analysis, 193 Raman spectroscopy, 62–64 Rapid thermal annealing (RTA), 81, 125 Rapid thermal processing (RTP), 110 Rare earth (RE) silicides, 172 Rayleigh’s Law, 26 Reactive ion etching (RIE), 53–54 Reduced pressure chemical vapor deposition (RPCVD) technique, 48 Refined transmission line measurement (RTLM), 160, 163–164 Relative dielectric constants, 75–76, 76t Relative permittivity, 75 Replacement gate process flow, 91, 91f Reticle enhancement techniques (RETs), 29–30 Richardson constant, 236–237 Roadmap of the Semiconductor Industry Association, 19 S SBHs. See Schottky barrier heights (SBHs) Scaling, device architecture, 69 dimensional scaling constant electric field scaling, 20–22, 21f, 21t generalized scaling, 21t, 22 generalized selective scaling, 21t, 22 junctionless transistors, 25 SCEs, impact of, 22–24 impact of, 31–32 lithography for downscaling (see Lithography) MOS transistor feature size, reduction of, 19 revolutionary technology road map, 19–20, 20f spintronics, 34–35 tunnel field-effect transistor, 33–34 Schottky barrier heights (SBHs), 227, 237 Ge/III-V semiconductors ALD, 188

261

CMOS applications, 188 dipole and dopant segregation, 186–188 interface passivation, 184–186 MIS method, 181–184 MOSFETs, 188 Ohmic contacts, Si/SiGe substrate alloying method, 172 dopant segregation, 169–172 FLP, 164–165 interface passivation, 167–169 MIGS, 164–165 MIS method, 166–167 Schottky emission effect, 236–237 Secondary ion mass spectrometry (SIMS), 132, 132f Selectively epitaxial growth (SEG), 164 Self-aligned double patterning (SADP), 28 Self-aligned quadruple patterning (SAQP), 28 Self-aligned spacer patterning lithography process, 27–28, 28f Self-assembled monolayer (SAM), 230 Shallow junctions boron junctions in silicon boron-interstitial clustering, 137–139 chemical profiles, SIMS, 132, 132f diffusion mechanism, 132–135 TED, 126–127, 136–137 dopant diffusion, 128–130 doping methods, 130–131 n-type Ge junctions, 126–127 co-implantation, 142–144 intrinsic and extrinsic diffusion, 140–142 ion implantation, 141–142 point defect engineering, 144–146 p-type substrate, P implantation in, 139–140, 139f sheet resistance vs. junction depth, 125, 126f scaled junction processing, 125 solubility and distribution coefficient, 127–128 Shallow trench isolation (STI), 20, 113f Short-channel effects (SCEs), 13–14, 19–20, 22–23 SiGe layers, strain engineering. See Strain engineering SiGe-on-insulator (SGOI), 45–46, 107–108

262

Silicidation-induced dopant segregation (SIDS), 169–171 Silicide as diffusion source (SADS), 169–171 Silicon carbon nitride (SiCN) films, 228 Silicon thermal oxide, 234–236 Silsesquioxane (SSQ), 224 Single damascene integration, 217, 217f Single-layer graphene (SLG), 186 Single metal/dual dielectric (SMDD), 90–91 Single metal/single dielectric (SMSD), 90–91 SiO2 gate dielectric CMOS transistor structure, 70, 70f direct tunneling, simulated gate leakage, 72, 73f electron transportation, energy band diagram, 71, 71f gate leakage current density limit, 72, 73f leakage current density vs. physical thickness, 71–72, 72f MOSFETs, tunneling current in, 71, 71f Si/SiGe substrate dopant segregation, 176–177 higher dopant concentration, 177–180 interface passivation, 174–176 MIS, 173–174 Solid-phase-epitaxial regrowth (SPER), 142, 177–178, 194 Solid-phase epitaxy (SPE), 54 Source/drain (S/D) junctions, 125 Specific contact resistivity, 157–159 Spin field-effect transistor (SFET), 35, 35f Spintronics, 34–35 Spreading resistance probing (SRP), 139–140 Strained silicon on insulator (sSOI), 45 Strain engineering, 31 CMOS structure DSL, 52–54 epitaxy of stressor materials, 47–51 SMT process, 51–52 compressive and tensile, 41–43, 42f elastic constants, 43, 43t embedded Si1–yCy for nMOS carbon atoms, implantation/SPE approach, 54 critical thickness (see Critical thickness, strained SiGe layers) drive current vs. off current, 54, 55f HRRLMs, 60–62, 62–63f NBD analysis, HRTEM, 59–60, 60f

Index

45-nm baseline process, 54, 54f Raman spectroscopy, 62–64 XRD measurement, 60 HKMGS, 41 lattice constant values, 43–44 MOSFETs, biaxial and uniaxial strained Si channels, 44–47 strain compensation, 43 strain, definition of, 41 strain relaxation, 43 Vegard’s law, 43 vertical and in-plane components, 42–43, 42f Stress-induced voiding (SIV), 233 Stress memorization technology (SMT), 41, 51–52 Stress migration, 215–216 Stress proximity technique (SPT), 53–54 Subthreshold voltage, 10, 10f Sulfur (S) segregation approach, 176 Surface passivation, 109 T Thermal annealing, 81 Thermal budget, 81 Threshold voltage, 78–79, 78f Time dependent dielectric breakdown (TDDB), 215–216, 238–239, 238f Titanium tetrachloride (TiCl4), 95 Transfer length method, 195 Transient-enhanced diffusion (TED), 126–127, 136–137 Transistor counts growth, 69, 70f Transition metal dichalcogenides (TMDs), 114, 197–199 Transmission line measurement (TLM), 160, 163–164 Trap-assisted tunneling (TAT), 185 Triethylaluminum (TEA), 95 Trigate transistors, 3 Trimethylaluminum (TMA), 95 Tunnel field-effect transistor (TFET), 33–34 Two-dimensional channel materials graphene channel, 114–117 graphene-like channel, 117–118 IOT, 114 TMDs, 114 Two-temperature scheme, 108, 108f

Index

263

U

W

Ultra-shallow junction. See Shallow junctions Ultrathin-body (UTB), 175 Ultraviolet ozone (UVO), 195–197

Weibull distributions, 240–241 Wiener-Kramers-Brillouin (WKB) approximation, 33–34 X

V Vegard’s law, 43

X-ray diffraction (XRD), 60 X-ray lithography (XRL), 29

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