Analog Circuit Design: A Tutorial Guide to Applications and Solutions [1 ed.] 0123851858, 9780123851857

Table of contents :
Cover
Title
Copyright
Dedication
in memoriam
Publisher’s Note
Acknowledgments
Introduction
Foreword
PART 1
Section 1
Ceramic input capacitors can cause overvoltage transients
Plug in the wall adapter at your own risk
Building the Test Circuit
Turning on the switch
Testing a portable application
Input voltage transients with different input elements
Optimizing Input Capacitors
Conclusion
Minimizing switching regulator residue’in’linear regulator outputs
Introduction
Switching regulator AC output content
Ripple and spike rejection
Ripple/spike simulator
Linear regulator high frequency rejection evaluation/optimization
References
Power Conditioning for notebook and palmtop systems
Introduction
LT1432 driver for high efficiency 5V and 3.3V buck regulator
Circuit description
BICMOS switching regulator family provides highest step-down efficiencies
Surface mount capacitors for switching regulator applications
High efficiency linear supplies
Power switching with dual high side micropower N-channel MOSFET drivers
LT1121 micropower 150mA regulator with shutdown
Cold cathode fluorescent display driver
Battery charging
Lead acid battery charger
NiCAD charging
LCD display contrast power supply
A 4-cell NiCad regulator/charger
Power supplies for palmtop computers
2-Cell input palmtop power supply’circuits
LCD bias from 2 AA cells
4-Cell input palmtop power supply’circuits
A CCFL backlight driver for palmtop’machines
2-Wire virtual remote sensing for’voltage’regulators
Introduction
“Virtual” remote sensing
Applications
VRS linear regulators
VRS equipped switching regulators
VRS based isolated switching supplies
VRS halogen lamp drive circuit
References
 
Outline placeholder
Introduction
Design procedure
RSENSE selection
Section 2
LT1070 design manual
Introduction
Preface
Smaller versions of the LT1070
Inductance calculations
Protecting the magnetics
New switch current specification
High supply voltages
Discontinuous “oscillations” (ringing)
LT1070 operation
Pin functions
Input supply (VIN)
Ground pin
Feedback pin
Compensation pin (Vc)
Output pin
Basic switching regulator topologies
Buck converter
Boost regulators
Combined buck-boost regulator
’Cuk converter
Flyback regulator
Forward converter
Current-boosted boost converter
Current-boosted buck converter
Application circuits
Boost mode (output voltage higher than input)
Inductor
Output capacitor
Frequency compensation
Current steering diode
Short-circuit conditions
Negative buck converter
Output divider
Duty cycle
Inductor
Output capacitor
Output filter
Input filter
Frequency compensation
Catch diode
Negative-to-positive buck-boost converter
Setting output voltage
Inductor
Output capacitor
Current steering diode
Positive buck converter
Duty cycle limitations
Inductor
Output voltage ripple
Output capacitor
Output filter
Flyback converter
Output divider
Frequency compensation
Snubber design
Output diode (D1)
Output capacitor (C1)
Totally isolated converter
Output capacitors
Load and line regulation
Frequency compensation
Positive current-boosted buck converter
Negative current-boosted buck converter
Negative input/negative output flyback converter
Positive-to-negative flyback converter
Voltage-boosted boost converter
Negative boost converter
Positive-to-negative buck boost converter
Current-boosted boost converter
Forward converter
Frequency compensation
Check margins
Eliminating start-up overshoot
External current limiting
Driving external transistors
Output rectifying diode
Input filters
Efficiency calculations
LT1070 operating current
LT1070 switch losses
Output diode losses
Inductor and transformer losses
Snubber losses
Total losses
Output filters
Input and output capacitors
Inductor and transformer basics
Cores with gaps
Inductor selection process
Transformer design example
Heat sinking information
Troubleshooting hints
Warning
Subharmonic oscillations
Inductor/transformer manufacturers
Core manufacturers
Bibliography
Switching regulators for poets
Basic flyback regulator
−48V to 5V telecom flyback regulator
Fully-isolated telecom flyback regulator
100W off-line switching regulator
Switch-controlled motor speed’controller
Switch-controlled peltier 0°C’reference
Acknowledgments
Step-down switching regulators
Basic step down circuit
Practical step-down switching regulator
Dual output step-down regulator
Negative output regulators
Current-boosted step-down regulator
Post regulation-fixed case
Post regulation-variable case
Low quiescent current regulators
Wide range, high power, high voltage regulator
Regulated sinewave output DC/AC converter
References
 
A monolithic switching regulator with 100μV output noise
Introduction
Switching regulator “noise”
A noiseless switching regulator approach
A practical, low noise monolithic regulator
Measuring output noise
System-based noise “measurement”
Transition rate effects on noise and’efficiency
Negative output regulator
Floating output regulator
Floating bipolar output converter
Battery-powered circuits
Performance augmentation
Low quiescent current regulator
High voltage input regulator
24V-to-5V low noise regulator
10W, 5V to 12V low noise regulator
7500V isolated low noise supply
References
 

History
Measuring noise
Low frequency noise
Preamplifier and oscilloscope selection
Ground loops
Pickup
Poor probing technique
Violating coaxial signal transmission—felony case
Violating coaxial signal transmission— misdemeanor case
Proper coaxial connection path
Direct connection path
Test lead connections
Isolated trigger probe
Trigger probe amplifier
Breadboarding and Layout Considerations
5V to 12V Breadboard
5V to±15V breadboard
Demonstration board
Testing ripple rejection
Transformers
Inductors
Hints for lowest noise performance
Noise tweaking
Capacitors
Damper network
Measurement technique
Noise test data
Pot core
ER core
Toroid
E core
Summary
Conclusion
Rectifier reverse recovery
Ringing in clamp Zeners
Paralleled rectifiers
Paralleled snubber or damper caps
Ringing in transformer shield leads
Leakage inductance fields
External air gap fields
Poorly bypassed high speed logic
Probe use with a “LISN”
Conclusion
Summary
Powering complex FPGA-based systems using highly integrated DC/DC μModule regulator systems
Innovation in DC/DC design
DC/DC μModule Regulators: Complete Systems in an LGA Package
48A from four parallel DC/DC μModule regulators
Start-up, soft-start and current sharing
Conclusion
Powering complex FPGA-based systems’using highly integrated DC/DC µModule regulator systems
60W by paralleling four DC/DC μModule regulators
Thermal performance
Simple copy and paste layout
Conclusion
Diode Turn-On Time Induced Failures in Switching Regulators
Introduction
Diode turn-on time perspectives
Detailed measurement scheme
Diode Testing and Interpreting Results
References

400ps rise time avalanche pulse generator
Circuit optimization
When to roll your own and when to pay the money
Section 3
Performance verification of low noise, low dropout regulators
Introduction
Noise and noise testing
Noise testing considerations
Instrumentation performance verification
Regulator noise measurement
Bypass capacitor (CBYP) influence
Interpreting comparative results
References
References

Noise minimization
Pass element considerations
Dynamic characteristics
Bypass capacitance and low noise performance
Output capacitance and transient response
Ceramic capacitors
AC voltmeter types
Rectify and average
Analog computation
Thermal
Performance comparison of noise driven AC voltmeters
Thermal voltmeter circuit
Section 4
Parasitic capacitance effects in step-up transformer design
High efficiency, high density, PolyPhase converters for high current applications
Introduction
How do PolyPhase techniques affect circuit performance?
Current-sharing
Output ripple current cancellation and’reduced output ripple voltage
Improved load transient response
Input ripple current cancellation
Input ripple current cancellation
Design considerations
Selection of phase number
PolyPhase converters using the LTC1629
Layout considerations
Design example: 100A PolyPhase power supply
Design details
MOSFETs
Inductors
Capacitors
Test results
Summary
Section 5
Ultracompact LCD backlight inverters
Introduction
Limitations and problems of magnetic CCFL transformers
Piezoelectric transformers
Developing a PZT transformer control scheme
Additional considerations and benefits
Display parasitic capacitance and its effects
References
 

“Good Vibrations”
Piezowhat?
Alchemy and black magic
The fun part
A resonant personality
Piezoelectricity
Piezoelectric effect
Axis nomenclature
Electrical-mechanical analogies
Coupling
Electrical, mechanical property changes with load
Elasticity
Piezoelectric equation
Basic piezoelectric modes
Poling
Post Poling
Applied voltage
Applied force
Shear
Piezoelectric benders
Loss
Simplified Piezoelectric Element Equivalent Circuit
Simple stack piezoelectric transformer
Conclusion
A thermoelectric cooler temperature’controller for fiber’optic’lasers
INTRODUCTION
Temperature Controller Requirements
Temperature Controller Details
Thermal Loop Considerations
Temperature Control Loop Optimization
Temperature Stability Verification
Reflected Noise Performance
REFERENCES
Current sources for fiber optic lasers
Introduction
Design criteria for fiber optic laser current sources
Detailed discussion of performance issues
Required power supply
Output current capability
Output voltage compliance
Efficiency
Laser connection
Output current programming
Stability
Noise
Transient response
Detailed discussion of laser protection issues
Overshoot
Enable
Output current clamp
Open laser protection
Basic current source
High efficiency basic current source
Grounded cathode current source
Single supply, grounded cathode current source
Fully protected, self-enabled, grounded cathode current source
2.5A, grounded cathode current source
0.001% noise, 2A, grounded cathode current source
0.0025% noise, 250mA, grounded anode current source
Low noise, fully floating output current source
Anode-at-supply current source
References
 
Outline placeholder
Electronic laser load simulator
Isolated trigger probe
Trigger probe amplifier
Bias voltage and current sense circuits for avalanche photodiodes
Introduction
Simple current monitor circuits (with’problems)
Carrier based current monitor
DC coupled current monitor
APD bias supply
APD bias supply and current monitor
Transformer based APD bias supply and current monitor
Inductor based APD bias supply
200μV output noise APD bias supply
Low noise APD bias supply and current monitor
0.02% accuracy current monitor
Digital output 0.09% accuracy current monitor
Digital output current monitor
Digital output current monitor and APD bias supply
Summary
References
 

Divider current error compensation—“low’side” shunt case
Divider current error compensation—“high side” shunt case
Ground loops
Pickup
Poor probing technique
Violating coaxial signal transmission—felony case
Violating coaxial signal transmission— misdemeanor case
Proper coaxial connection path
Direct connection path
Test lead connections
Isolated trigger probe
Trigger probe amplifier
Section 6
Developments in battery stack voltage measurement
The battery stack problem
Transformer based sampling voltmeter
Detailed circuit operation
Multi-cell version
Automatic control and calibration
Firmware description
Measurement details
Adding more channels
References
Things that don’t work
PART 2
Section 1
Some techniques for direct digitization of’transducer outputs
The care and feeding of’high’performance ADCs: get’all the’bits’you’paid for
Introduction
An ADC has many “inputs”
Ground planes and grounding
Supply bypassing
Reference bypassing
Driving the analog input
Switched capacitor inputs
Filtering wideband noise from’the’input’signal
Choosing an op amp
Driving the convert-start input
Effects of jitter
Routing the data outputs
Conclusion
Family features
High speed A/D converters — world’s best power/speed ratio
A standards lab grade 20-bit DAC with 0.1ppm/°C drift
Introduction
20-bit DAC architecture
Circuitry details
Linearity considerations
DC performance characteristics
Dynamic performance
Conclusion
References
Approach and error considerations
Circuitry details
Construction
Results
Acknowledgments
Delta sigma ADC bridge measurement techniques
Introduction
Low cost, precision altimeter uses direct digitization
How Many Bits?
Increasing Resolution with Amplifiers
How Much Gain?
ADC Response to Amplifier Noise
How Many Bits?
Faster or More Resolution with the LTC2440
How Many Bits?
RMS vs Peak-to-Peak Noise
Psychological Factors
1ppm settling time measurement for’a’monolithic 18-bit DAC
Introduction
DAC settling time
Considerations for measuring DAC settling time
Sampling based high resolution DAC settling time measurement
Developing a sampling switch
Electronic switch equivalents
Transconductance amplifier based switch equivalent
DAC settling time measurement method
Detailed settling time circuitry
Settling time circuit performance
Using the sampling-based settling time circuit
References
 

Delay compensation
Circuit trimming procedure
Ohm's law
Shielding
Connections
Settling time circuit performance verification
Section 2
Applications for a switched-capacitor instrumentation building block
Instrumentation amplifier
Ultrahigh performance instrumentation amplifier
Lock-in amplifier
Wide range, digitally controlled, variable gain amplifier
Precision, linearized platinum RTD signal conditioner
Relative humidity sensor signal conditioner
LVDT signal conditioner
Charge pump F→V and V→F converters
12-bit A→D converter
Miscellaneous circuits
Voltage-controlled current source—grounded source and load
Current sensing in supply rails
0.01% analog multiplier
Inverting a reference
Low power, 5V driven, temperature compensated crystal oscillator
Simple thermometer
High current, “inductorless,” switching regulator
Application considerations and circuits for a new chopper-stabilized op amp
Applications
Standard grade variable voltage reference
Ultra-precision instrumentation amplifier
High performance isolation amplifier
Stabilized, low input capacitance buffer (FET’probe)
Chopper-stabilized comparator
Stabilized data converter
Wide range V→F converter
1Hz to 30MHz V→F converter
16-bit A/D converter
Simple remote thermometer
Output stages
References
Designing linear circuits for 5V single supply operation
Linearized RTD signal conditioner
Linearized output methane detector
Cold junction compensated thermocouple signal conditioner
5V powered precision instrumentation amplifier
5V powered strain gauge signal conditioner
“Tachless” motor speed controller
4-20mA current loop transmitter
Fully isolated limit comparator
Fully isolated 10-bit A/D converter
Application considerations for an instrumentation lowpass filter
Description
Tuning the LTC1062
LTC1062 clock requirements
Internal oscillator
Clock feedthrough
Single 5V supply operation
Dynamic range and signal/noise ratio
Step response and burst response
LTC1062 shows little aliasing
Cascading the LTC1062
Using the LTC1062 to create a’notch
Comments on capacitor types
Clock circuits
Acknowledgement
Micropower circuits for signal conditioning
Platinum RTD signal conditioner
Thermocouple signal conditioner
Sampled strain gauge signal conditioner
Strobed operation strain gauge bridge signal conditioner
Thermistor signal conditioner for current loop application
Microampere drain wall thermostat
Freezer alarm
12-Bit A/D converter
10-Bit, 100μA A/D converter
20μs sample-hold
10kHz voltage-to-frequency converter
1MHz voltage-to-frequency converter
Switching regulator
Post regulated micropower switching regulator
Thermocouple measurement
Introduction
Thermocouples in perspective
Signal conditioning issues
Cold junction compensation
Amplifier selection
Additional circuit considerations
Differential thermocouple amplifiers
Isolated thermocouple amplifiers
Digital output thermocouple isolator
Linearization techniques
References
 
Take the mystery out of the switched-„capacitor filter
Introduction
Overview
The switched-capacitor filter
Circuit board layout considerations
Power supplies
Input considerations
Offset voltage nulling
Slew limiting
Aliasing
Filter response
What kind of filter do I use? Butterworth, Chebyshev, Bessel or Elliptic
Filter sensitivity
How stable is my filter?
Output considerations
THD and dynamic range
THD in active RC filters
Noise in switched-capacitor filters
Bandpass filters and noise—an illustration
Clock circuitry
Jitter
Clock synchronization with A/D sample clock
Clock feedthru
Conclusions
Bibliography
Bridge circuits
Resistance bridges
Bridge output amplifiers
DC bridge circuit applications
Common mode suppression techniques
Single supply common mode suppression circuits
Switched-capacitor based instrumentation amplifiers
Optically coupled switched-capacitor instrumentation amplifier
Platinum RTD resistance bridge circuits
Digitally corrected platinum resistance bridge
Thermistor bridge
Low power bridge circuits
Strobed power bridge drive
Sampled output bridge signal conditioner
Continuous output sampled bridge signal conditioner
High resolution continuous output sampled bridge signal conditioner
AC driven bridge/synchronous demodulator
AC driven bridge for level transduction
Time domain bridge
Bridge oscillator—square wave output
Quartz stabilized bridge oscillator
Sine wave output quartz stabilized bridge oscillator
Wien bridge-based oscillators
Diode bridge-based 2.5MHz precision rectifier/AC voltmeter
References
High speed amplifier techniques
Preface
Introduction
Perspectives on high speed design
Mr. Murphy's gallery of high speed amplifier problems
TUTORIAL SECTION
About Cables, Connectors and Terminations
About Probes and Probing Techniques
About Oscilloscopes
About Ground Planes
About Bypass Capacitors
Breadboarding Techniques
Oscillation
Applications Section I — Amplifiers
Fast 12-bit digital-to-analog converter (DAC) amplifier
2-Channel Video Amplifier
Simple Video Amplifier
Loop Through Cable Receivers
DC stabilization — summing point technique
DC stabilization — differentially sensed technique
DC stabilization — servo controlled FET input stage
DC stabilization — full differential inputs with parallel paths
DC stabilization — full differential inputs, gain-of-1000 with parallel paths
High Speed Differential Line Receiver
Transformer Coupled Amplifier
Differential Comparator Amplifier with Adjustable Offset
Differential Comparator Amplifier with Settable Automatic Limiting and Offset
Photodiode Amplifier
Fast Photo Integrator
Fiber Optic Receiver
40MHz fiber optic receiver with adaptive trigger
50MHz high accuracy analog multiplier
Power Booster Stage
High Power Booster Stage
Ceramic Bandpass Filters
Crystal Filter
Applications Section II — Oscillators
Sine Wave Output Quartz Stabilized Oscillator
Sine Wave Output Quartz Stabilized Oscillator with Electronic Gain Control
DC Tuned 1MHz-10MHz Wien Bridge Oscillator
Complete AM radio station
Applications section III — Data conversion
1Hz–1MHz voltage-controlled sine wave oscillator
1Hz–10MHz V→F Converter
8-bit, 100ns sample-hold
15ns current summing comparator
50MHz adaptive threshold trigger circuit
Fast Time-to-Height (Pulsewidth-to-Voltage) Converter
True RMS wideband voltmeter
APPLICATIONS SECTION IV — MISCELLANEOUS CIRCUITS
RF Leveling Loop
Voltage Controlled Current Source
High Power Voltage Controlled Current Source
18ns circuit breaker
References

ABC's of probes – Tektronix, Inc
The vital link in your measurement system
Why not use a piece of wire?
Benefits of using probes
How probes affect your measurements
Scope Bandwidth at the Probe Tip?
How ground leads affect measurements
How probe design affects your measurements
Tips on using probes
Introduction:
Measuring Amplifier Settling Time
The Oscillation Problem — Frequency Compensation Without Tears
Measuring Probe-Oscilloscope Response
An Ultra-Fast High Impedance Probe
Additional Comments on Breadboarding
FCC licensing and construction permit applications for commerical AM broadcasting stations
About Current Feedback
Current Feedback Basics
High Frequency Amplifier Evaluation Board
The contributions of Edsel Murphy to the understanding of the behavior of inanimate objects
I. Introduction
II. General Engineering
III. Mathematics
IV. Prototyping and Production
V. Specifying
References**In some cases where no reference is given, the source material was misplaced during preparation of this paper (another example of Murphy's Law). In accordance with the law, these misplaced documents will turn up on the date of publication of this paper.
A seven-nanosecond comparator for’single supply operation
Introduction
The LT1394 — an overview
The rogue's gallery of high speed comparator problems
Tutorial section
About pulse generators
About cables, connectors and terminations
About probes and probing techniques
About oscilloscopes
About ground planes
About bypass capacitors
Breadboarding techniques
Applications
Crystal oscillators
Switchable output crystal oscillator
Temperature-compensated crystal oscillator (TXCO)
Voltage-controlled crystal oscillator (VCXO)
Voltage-tunable clock skew generator
Simple 10MHz voltage-to-frequency converter
Precision 1Hz to 10MHz voltage-to-frequency converter
Fast, high impedance, variable threshold trigger
High speed adaptive trigger circuit
18ns, 500μV sensitivity comparator
Voltage-controlled delay
10ns sample-and-hold
Programmable, sub-nanosecond delayed pulse generator
Fast pulse stretcher
20ns response overvoltage protection circuit
References
 
Understanding and applying voltage references
Essential features
Reference pitfalls
Current-hungry loads
“NC” pins
Board leakage
Trim-induced temperature drift
Burn-in
Board stress
Temperature-induced noise
Reference applications
Conclusion
For further reading
 
Instrumentation applications for’a’monolithic’oscillator
Introduction
Clock types
A (very) simple, high performance oscillator
Platinum RTD digitizer
Thermistor-to-frequency converter
Isolated, 3500V breakdown, thermistor-to-frequency converter
Relative humidity sensor digitizer-hetrodyne based
Relative humidity sensor digitizer—charge pump based
Relative humidity sensor digitizer—time domain bridge based
40nV noise, 0.05μV/°C drift, chopped bipolar amplifier
45nV noise, 0.05μV/°C drift, chopped FET amplifier
Clock tunable, filter based sine wave generator
Clock tunable, memory based sine wave generator
Clock tunable notch filter
Clock tunable interval generator with 20×106:1 dynamic range
8-bit, 80μs, passive input, A/D converter
References
Slew rate verification for wideband amplifiers
Introduction
Amplifier dynamic response
LT1818 Short form specifications
Pulse generator rise time effects on measurement
Subnanosecond rise time pulse generators
360ps rise time pulse generator
Circuit optimization
Refining slew rate measurement
References
 
Instrumentation circuitry using RMS-„to-„DC converters
Introduction
Isolated power line monitor
Fully isolated 2500V breakdown, wideband RMS-to-DC converter
Low distortion AC line RMS voltage regulator
X1000 DC stabilized millivolt preamplifier
Wideband decade ranged ×1000 preamplifier
Wideband, isolated, quartz crystal RMS current measurement
AC voltage standard with stable frequency and low distortion
RMS leveled output random noise generator
RMS amplitude stabilized level controller
References
 
Additional reading
775 nanovolt noise measurement for’a’low noise voltage reference
Introduction
Noise measurement
Noise measurement circuit performance
References
 
Section 3
LT5528 WCDMA ACPR, AltCPR and noise measurements
Introduction
Measuring phase and delay errors accurately in I/Q modulators
Introduction
Measurements
First measurement—null out the I/Q modulator image signal with normal signal connections (Figure 41.6)
Second measurement—null out the I/Q modulator image signal with reversed differential baseband signals to the modulator's differential I-channel inputs (Figure 41.7)
Third measurement—null out the I/Q modulator image signal after reversing the I and Q inputs to the modulator (Figure 41.8)
Calculation of phase impairments
Applying the method
Conclusion
Subject Index

Citation preview

Analog Circuit Design A Tutorial Guide to Applications and Solutions

Analog Circuit Design A Tutorial Guide to Applications and Solutions

Edited by

Bob Dobkin Jim Williams

Amsterdam  Boston  Heidelberg  London  New York  Oxford Paris  San Diego  San Francisco  Singapore  Sydney  Tokyo Newnes is an imprint of Elsevier

Newnes is an imprint of Elsevier The Boulevard, Langford Lane, Kidlington, Oxford OX5 1GB, UK 225 Wyman Street, Waltham, MA 02451, USA First edition 2011 Copyright Ó 2011, Linear Technology Corporation. Published by Elsevier Inc. All rights reserved See separate Publisher's Note for copyright details of Trade Marks used in this book The right of Linear Technology Corporation to be identified as the author of this work has been asserted in accordance with the Copyright, Designs and Patents Act 1988 No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means electronic, mechanical, photocopying, recording or otherwise without the prior written permission of the publisher Permissions may be sought directly from Elsevier’s Science & Technology Rights Department in Oxford, UK: phone (+44) (0) 1865 843830; fax (+44) (0) 1865 853333; email: [email protected]. Alternatively you can submit your request online by visiting the Elsevier web site at http://elsevier.com/locate/permissions, and selecting Obtaining permission to use Elsevier material Notice No responsibility is assumed by the publisher or authors/contributors for any injury and/or damage to persons or property as a matter of products liability, negligence or otherwise, or from any use or operation of any methods, products, instructions or ideas contained in the material herein. Because of rapid advances in the medical sciences, in particular, independent verification of diagnoses and drug dosages should be made British Library Cataloguing in Publication Data A catalogue record for this book is available from the British Library Library of Congress Cataloging-in-Publication Data A catalog record for this book is availabe from the Library of Congress ISBN: 978-0-12-385185-7

For information on all Newnes publications visit our web site at books.elsevier.com Printed and bound in The United States of America 11 12 13 14 15 10 9 8 7 6 5 4 3 2 1

For Jerrold R. Zacharias, who gave me the sun, the moon and the stars. For Siu, who is the sun, the moon and the stars.

In memory of Jim Williams, a poet who wrote in electronics.

Publisher’s Note This book was compiled from Linear Technology Corporation’s original Application Notes. These Application Notes have been re-named as chapters for the purpose of this book. However, throughout the text there is a lot of cross referencing to different Application

CHAPTER NUMBER

Notes, not all of which have made it into the book. For reference, this conversion table has been included; it shows the book chapter numbers and the original Application Note numbers.

APPLICATION NOTE

CHAPTER NUMBER

APPLICATION NOTE

1

88

22

86

2

101

23

96

3

51

24

120

4

126

25

3

5

19

26

9

6

25

27

11

7

35

28

20

8

70

29

23

9

119a

30

28

10

199b

31

40

11

122

32

43

12

83

33

47

13

39

34

72

14

77

35

82

15

81

36

93

16

89

37

94

17

90

38

106

18

92

39

124

19

112

40

99

20

7

41

102

21

71

Publisher’s Note

Trademarks These Trademarks all belong to Linear Technology Corporation. They have been listed here to avoid endless repetition within the text. Trademark acknowledgment and protection applies regardless. Please forgive us if we have missed any. Linear Express, Linear Technology, LT, LTC, LTM, Burst Mode, FilterCAD, LTspice, OPTI-LOOP, Over-The-Top, PolyPhase, SwitcherCAD, TimerBlox, mModule and the Linear logo are registered trademarks of Linear Technology Corporation. Adaptive Power, Bat-Track, BodeCAD, CLoad, Direct Flux Limit, DirectSense, Easy Drive,

xii

FilterView, Hot Swap, LinearView, LTBiCMOS, LTCMOS, LTPoE++, LTpowerCAD, LTpowerPlanner, LTpowerPlay, MicropowerSwitcherCAD, Multimode Dimming, No Latency DS, No Latency Delta-Sigma, No RSENSE Operational Filter, PanelProtect, PLLWizard, PowerPath, PowerSOT, PScope, QuikEval, RH DICE Inside, RH MILDICE Inside, SafeSlot, SmartStart, SNEAK-A-BIT, SoftSpan, Stage Shedding, Super Burst, ThinSOT, Triple Mode, True Color PWM, UltraFast, Virtual Remote Sense, Virtual Remote Sensing, VLDO and VRS are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

Acknowledgments

Spanning three decades of analog technology, this volume represents the hard work of many individuals— too many to name. The lion’s share of the credit goes to Linear’s dedicated engineer/authors, whose work fills these pages. Jim Williams and Bob Dobkin have given generously of their time and support. I would be remiss not to also acknowledge the contributions of our

dedicated publications team of Susan Cooper and Gary Alexander, who put in the extra hours to get the Application Notes ready for publication. Finally, a word of thanks to our publisher, Jonathan Simpson, who helped pave the road from idea to book, Naomi Robertson and Pauline Wilkinson, who smoothed the book’s production.

John Hamburger Linear Technology Corporation

Introduction

Why write applications? This is seemingly an odd and unlikely way to begin an applications publication, but it is a valid question. As such, the components of the decision to produce this book are worth reviewing. Producing analog application material requires an intensive, extended effort. Development costs for worthwhile material are extraordinarily high, absorbing substantial amounts of engineering time and money. Further, these same resources could be directed towards product development, the contribution of which is much more easily measured at the corporate coffers. A commitment to a concerted applications effort must be made despite these concerns. Specifically, the nature of analog circuit design is so diverse, the devices so sophisticated, and user requirements so demanding that designers require (or at least welcome) assistance. Ultimately, the use of analog ICs is tied to the user’s ability to solve the problems confronting them. Anything that enhances this ability, in both specific and general cases, obviously benefits all concerned. This is a very simple but powerful argument, and is the basis of any commitment to applications. Additional benefits include occasional new product concepts and a way to test products under ‘‘real world’’ conditions, but the basic justification is as described. Traditionally, application work has involved reviewing considerations for successful use of a specific product. Additionally, basic circuit suggestions or concepts are sometimes offered. Although this approach is useful and necessary, some expansion is possible. The applications selected for inclusion in this book are centered on detailed, systems-oriented circuits, (hopefully) similar to users’ actual designs. There is broad tutorial content, reflected in the form of frequent text digressions and liberal use of graphics. Discussions of trade-offs, options and techniques are emphasized, as opposed to brief descriptions of circuit operation. Many of the application notes include appended sections which examine related or pertinent topics in detail. Ideally, this treatment provides enough background to allow readers to modify the circuits presented into solutions to their specific problems. Some comment about the circuit examples is appropriate. They range from relatively simple to quite complex and sophisticated. Emphasis is on high performance, in

keeping with the capabilities of contemporary products and users’ needs. The circuit’s primary function is to serve as a catalyst once the reader has started thinking, the material has accomplished its mission. Substantial effort has been expended in working out and documenting these circuits, but they are not necessarily finessed to the highest possible degree. All of the circuits have been breadboarded and bench-tested at the prototype level. Specifications and performance levels quoted in the text represent measured and extrapolated data derived from the breadboard prototype. The volume of material generated prohibits formal worst-case review or tolerance analysis for production. The content in this volume, while substantial, represents only a portion of the available material. The resultant winnowing process was attended by tears and tantrums. The topics presented are survivors of a selection process involving a number of disparate considerations. These include reader interest, suitability for publication, time and space constraints and lasting tutorial value. Additionally, a minimum 10 year useful lifetime for application notes is desired. This generally precludes narrowly focused efforts. Topics are broad, with a tutorial and design emphasis that (ideally) reflects the reader’s long term interest. While the circuits presented utilize existing products, they must be conceptually applicable to succeeding generations of devices. In this regard, it is significant that some of the material presented is still in high demand years after initial publication. The material should represent a relatively complete and interdisciplinary approach to solving the problem at hand. Solving a problem is usually the reader’s overwhelming motivation. The selection and integration of tools and methods towards this end is the priority. For this reason the examples and accompanying text are as complete and practical as possible. This may necessitate effort in areas where we have no direct stake, e.g., the software presented in Chapter 22 or the magnetics developed for Chapters 6 and 7. Quality, in particular good quality, is obviously desirable in any publication. A high quality application note requires attentive circuit design, thorough laboratory technique, and completeness in its description. Text and figures should be thoughtfully organized and presented, visually pleasing, and easy to read. The artwork and printing should maintain this care in the form of clean text appearance and easily readable graphics.

Application notes should also be efficient. An efficiently written note permits the reader to access desired information quickly, and in readily understandable form. There should be enough depth to satisfy intellectual rigor, but the reader should not need an academic bathyscaphe to get to the bottom of things. Above all, the purpose is to communicate useful information clearly and quickly. Finally, style should always show. Quite simply, the publication should be enjoyable to read. Style provides

psychological lubrication, helping the mind to run smoothly. Clearly, style must only assist the serious purposes of publication and should not be abused; the authors have done their best to maintain the appropriate balance. This book’s many authors deserve any and all forthcoming applause; the named editors accept sole responsibility for philosophical direction, content choice, errors, omissions, and other sins.

Jim Williams Staff Scientist Linear Technology Corporation

Foreword

The fundamental difference between analog and digital is ‘‘information.’’ With digital information the output is always the same: a set of ones and zeros that represents the information. This information is independent of the supply voltages or the circuitry that is used to generate it. With analog, the output information is basic electrical values—volts, current, charge—and is always related to some real world parameters. With analog, the methodology used to arrive at the answers is intrinsic to the quality of those answers. Errors such as temperature, noise, delay and time stability can all affect the analog output and all are a function of the circuitry that generates the output. It is this analog output that is difficult to derive and requires experience and circuit design talent. With integrated circuits (ICs) so prevalent, combined with application-specific integrated circuits (ASICs) in most systems, it is becoming increasingly difficult to find good analog examples for teaching engineers analog design. Engineering schools provide the basics of device terminal characteristics and some circuit hookup information, but

this is not adequate for designing finished circuits or applying modern IC design techniques. The analog circuitry in today’s systems is often difficult to decipher without help from the original designer. The ability to design complex analog systems relies on the ability of engineers to learn from what has gone before. One of the best avenues for learning analog design is to use the application notes and information from companies who supply analog integrated circuits. These application notes include circuitry, test results, and the basic reasoning for some of the choices made in the design of these analog circuits. They provide a good starting point for new designs. Since the applications are aimed at solving problems, the application notes, combined with the capability to simulate circuits on Spice, provide a key learning pathway for engineers. The analog information in most of these application notes is timeless and will be as valid twenty years from now as it is today. It’s my hope that anyone reading this book is helped through the science and art of good analog design.

Robert Dobkin Co-Founder, Vice President, Engineering, and Chief Technical Officer Linear Technology Corporation

PART 1 Power Management

Section 1 Power Management Tutorials Ceramic input capacitors can cause overvoltage transients (1) When it comes to input filtering, ceramic capacitors are a great choice. They offer high ripple current rating and low ESR and ESL. Also, ceramic capacitors are not very sensitive to overvoltage and can be used without derating the operating voltage. However, designers must be aware of a potential overvoltage condition that is generated when input voltage is applied abruptly. After applying an input voltage step, typical input filter circuits with ceramic capacitors can generate voltage transients twice as high as the input voltage. This note describes how to efficiently use ceramic capacitors for input filters and how to avoid potential problems due to input voltage transients.

Minimizing switching regulator residue in linear regulator outputs (2) Linear regulators are commonly employed to post-regulate switching regulator outputs. Benefits include improved stability, accuracy, transient response and lowered output impedance. Ideally, these performance gains would be accompanied by markedly reduced switching regulator generated ripple and spikes. In practice, all linear regulators encounter some difficulty with ripple and spikes, particularly as frequency rises. This publication explains the causes of linear regulators’ dynamic limitations and presents board level techniques for improving ripple and spike rejection. A hardware based ripple/spike simulator is presented, enabling rapid breadboard testing under various

conditions. Three appendices review ferrite beads, inductor based filters and probing practice for wideband, submillivolt signals.

Power conditioning for notebook and palmtop systems (3) Notebook and palmtop systems need a number of voltages developed from a battery. Competitive solutions require small size, high efficiency and light weight. This publication includes circuits for high efficiency 5V and 3.3V switching and linear regulators, backlight display drivers and battery chargers. All the circuits are specifically tailored for the requirements outlined above.

Two wire virtual remote sensing for voltage regulators (4) Wires and connectors have resistance. This simple, unavoidable truth dictates that a power source’s remote load voltage will be less than the source’s output voltage. The classical approach to mitigating this utilizes ‘‘4-wire’’ remote sensing to eliminate line drop effects. The power supply’s high impedance sense inputs are fed from separate, load-referred sense wires. This scheme works well, but requires dedicated sense wires, a significant disadvantage in many applications. A new approach, utilizing carrier modulation techniques, eliminates sense wires while maintaining load regulation.

Ceramic input capacitors can cause overvoltage transients

1

Goran Perica

A recent trend in the design of portable devices has been to use ceramic capacitors to filter DC/DC converter inputs. Ceramic capacitors are often chosen because of their small size, low equivalent series resistance (ESR) and high RMS current capability. Also, recently, designers have been looking to ceramic capacitors due to shortages of tantalum capacitors. Unfortunately, using ceramic capacitors for input filtering can cause problems. Applying a voltage step to a ceramic capacitor causes a large current surge that stores energy in the inductances of the power leads. A large voltage spike is created when the stored energy is transferred from these inductances into the ceramic capacitor. These voltage spikes can easily be twice the amplitude of the input voltage step.

Plug in the wall adapter at your own risk The input voltage transient problem is related to the powerup sequence. If the wall adapter is plugged into an AC outlet and powered up first, plugging the wall adapter output into a portable device can cause input voltage transients that could damage the DC/DC converters inside the device.

Building the test circuit To illustrate the problem, a typical 24V wall adapter used in notebook computer applications was connected to the input of a typical notebook computer DC/DC converter. The DC/DC converter used was a synchronous buck converter that generates 3.3V from a 24V input. The block diagram of the test setup is shown in Figure 1.1. The inductor LOUT represents the lumped equivalent inductance of the lead inductance and the output EMI filter inductor found in some wall adapters. The output capacitor in the wall adapter is usually on the order of 1000 mF; for our purposes, we can assume that it has low ESR—in the 10mW to 30mW range. The equivalent circuit of the wall adapter and DC/DC converter interface is actually a series resonant tank, with the dominant components being LOUT, CIN and the lumped ESR (the lumped ESR must include the ESR of CIN, the lead resistance and the resistance of LOUT). The input capacitor, CIN, must be a low ESR device, capable of carrying the input ripple current. In a typical notebook computer application, this capacitor is in the range of 10 mF to 100 mF. The exact capacitor value depends on a number of factors but the main requirement is that it must handle the input ripple current produced by

[(Figure_1)TD$IG]

Figure 1.1 * Block Diagram of Wall Adapter and Portable Device Connection Analog Circuit and System Design: A Tutorial Guide to Applications and Solutions. DOI: 10.1016/B978-0-12-385185-7.00001-9 Copyright  2011, Linear Technology Corporation. Published by Elsevier Inc. All rights reserved.

Ceramic input capacitors can cause overvoltage transients

CHAPTER 1

Table 1.1 Peak Voltages of Waveforms In Figure 1.2

the DC/DC converter. The input ripple current is usually in the range of 1A to 2A. Therefore, the required capacitors would be either one 10 mF to 22 mF ceramic capacitor, two to three 22 mF tantalum capacitors or one to two 22 mF OS-CON capacitors.

TRACE

Turning on the switch When switch SW1 in Figure 1.1 is turned on, the mayhem starts. Since the wall adapter is already plugged in, there is 24V across its low impedance output capacitor. On the other hand, the input capacitor CIN is at 0V potential. What happens from t = 0s is pretty basic. The applied input voltage will cause current to flow through LOUT. CIN will begin charging and the voltage across CIN will ramp up toward the 24V input voltage. Once the voltage across CIN has reached the output voltage of the wall adapter, the energy stored in LOUT will raise the voltage across CIN further above 24V. The voltage across CIN will eventually reach its peak and will then fall back to 24V. The voltage across CIN may ring for some time around the 24V value. The actual waveform will depend on the circuit elements. If you intend to run this circuit simulation, keep in mind that the real-life circuit elements are very seldom linear under transient conditions. For example, the capacitors may undergo a change of capacitance (Y5V ceramic capacitors will lose 80% of the initial capacitance under rated input voltage). Also, the ESR of input capacitors will depend on the rise time of the waveform. The inductance of EMI-suppressing inductors may also drop during transients due to the saturation of the magnetic material.

LIN (mH)

CIN (mF)

VIN PEAK (V)

CH1

1

10

57.2

R2

10

10

50

R3

1

22

41

R4

10

22

41

The top waveform shows the worst-case transient, with a 10 mF capacitor and 1 mH inductor. The voltage across CIN peaks at 57.2V with a 24V DC input. The DC/DC converter may not survive repeated exposure to 57.2V. The waveform with 10 mF and 10 mH (trace R2) looks a bit better. The peak is still around 50V. The flat part of the waveform R2 following the peak indicates that the synchronous MOSFET M1, inside of the DC/DC converter in Figure 1.1, is avalanching and taking the energy hit. Traces R3 and R4 peak at around 41V and are for a 22 mF capacitor with 1 mH and 10 mH inductors, respectively.

Input voltage transients with different input elements Different types of input capacitors will result in different transient voltage waveforms, as shown in Figure 1.3. The reference waveform for 22 mF capacitor and 1 mH inductor is shown in the top trace (R1); it peaks at 40.8V. The waveform R2 in Figure 1.3 shows what happens when a transient voltage suppressor is added across the input. The input voltage transient is clamped but not eliminated. It is very hard to set the voltage transient’s breakdown voltage low enough to protect the DC/DC converter and far enough from the operating DC level of the input source (24V). The transient voltage suppressor P6KE30A that was used was too close to starting to conduct at 24V.

Testing a portable application Input voltage transients with typical values of CIN and LOUT used in notebook computer applications are shown in Figure 1.2. Figure 1.2 shows input voltage transients for CIN values of 10 mF and 22 mF with LOUT values of 1 mH and 10 mH.

[(Figure_2)TD$IG]

[(Figure_3)TD$IG]

Figure 1.2 * Input Voltage Transients Across Ceramic Capacitors

Figure 1.3 * Input Transients with Different Input Components

5

SECTION ONE

Power Management Tutorials

Unfortunately, using a transient voltage suppressor with a higher voltage rating would not provide a sufficiently low clamping voltage. The waveforms R3 and R4 are with a 22 mF, 35V AVX TPS type tantalum capacitor and a 22 mF, 30V Sanyo OSCON capacitor, respectively. With these two capacitors, the transients have been brought to manageable levels. However, these capacitors are bigger than the ceramic capacitors and more than one capacitor is required in order to meet the input ripple current requirements.

[(Figure_4)TD$IG]

Table 1.2 Peak Voltages of Waveforms In Figure 1.3

TRACE

CIN (mF)

CAPACITOR TYPE

VIN PEAK (V)

R1

22

Ceramic

40.8

R2

22

Ceramic with 30V TVS

32

R3

22

AVX, TPS Tantalum

33

Table 1.3 Peak Voltages of Waveforms In Figure 1.4 with 22 mF Input Ceramic Capacitor and Added Snubber

R4

22

Sanyo OS-CON

35

TRACE

SNUBBER TYPE

Vin PEAK (V)

R1

None

40.8

R2

22 mF Ceramic + 0.5 W In Series

30

R3

22 mF Tantalum AVX, TPS Series

33

R4

30V TVS, P6KE30A

35

Ch1

47 mF, 35V Aluminum Electrolytic Capacitor

25

Optimizing input capacitors Waveforms in Figure 1.3 show how input transients vary with the type of input capacitors used. Optimizing the input capacitors requires clear understanding of what is happening during transients. Just as in an ordinary resonant RLC circuit, the circuit in Figure 1.1 may have an underdamped, critically damped or overdamped transient response. Because of the objective to minimize the size of input filter circuit, the resulting circuit is usually an underdamped resonant tank. However, a critically damped circuit is actually required. A critically damped circuit will rise nicely to the input voltage without voltage overshoots or ringing. To keep the input filter design small, it is desirable to use ceramic capacitors because of their high ripple current ratings and low ESR. To start the design, the minimum value of the input capacitor must first be determined. In the example, it has been determined that a 22 mF, 35V ceramic capacitor should be sufficient. The input transients generated with this capacitor are shown in the top trace of Figure 1.4. Clearly, there will be a problem if components that are rated for 30V are used. To obtain optimum transient characteristic, the input circuit has to be damped. The waveform R2 shows what happens when another 22 mF ceramic capacitor with a 0.5 W resistor in series is added. The input voltage transient is now nicely leveled off at 30V. Critical damping can also be achieved by adding a capacitor of a type that already has high ESR (on the order of 0.5 W). The waveform R3 shows the transient response when a 22 mF, 35V TPS type tantalum capacitor from AVX is added across the input. 6

Figure 1.4 * Optimizing Input Circuit Waveforms for Reduced Peak Voltage

The waveform R4 shows the input voltage transient with a 30V transient voltage suppressor for comparison. Finally, an ideal waveform shown in Figure 1.4, bottom trace (Ch1) is achieved. It also turns out that this is the least expensive solution. The circuit uses a 47 mF, 35V aluminum electrolytic capacitor from Sanyo (35CV47AXA). This capacitor has just the right value of capacitance and ESR to provide critical damping of the 22 mF ceramic capacitor in conjunction with the 1 mH of input inductance. The 35CV47AXA has an ESR value of 0.44 W and an RMS current rating of 230mA. Clearly, this capacitor could not be used alone in an application with 1A to 2A of RMS ripple current without the 22 mF ceramic capacitor. An additional benefit is that this capacitor is very small, measuring just 6.3mm by 6mm.

Conclusion Input voltage transients are a design issue that should not be ignored. Design solutions for preventing input voltage transients can be very simple and effective. If the solution is properly applied, input capacitors can be minimized and both cost and size minimized without sacrificing performance.

Minimizing switching regulator residue in linear regulator outputs Banishing those accursed spikes

2

Jim Williams

Introduction Linear regulators are commonly employed to post-regulate switching regulator outputs. Benefits include improved stability, accuracy, transient response and lowered output impedance. Ideally, these performance gains would be accompanied by markedly reduced switching regulator generated ripple and spikes. In practice, all linear regulators encounter some difficulty with ripple and spikes, particularly as frequency rises. This effect is magnified at small regulator VIN to VOUT differential voltages; unfortunate, because such small differentials are desirable to maintain efficiency. Figure 2.1 shows a conceptual linear regulator and associated components driven from a switching regulator output. The input filter capacitor is intended to smooth the ripple and spikes before they reach the regulator. The output capacitor maintains low output impedance at higher frequencies, improves load transient response and supplies frequency compensation for some regulators. Ancillary purposes include noise reduction and

minimization of residual input-derived artifacts appearing at the regulators output. It is this last category–residual input-derived artifacts—that is of concern. These high frequency components, even though small amplitude, can cause problems in noise-sensitive video, communication and other types of circuitry. Large numbers of capacitors and aspirin have been expended in attempts to eliminate these undesired signals and their resultant effects. Although they are stubborn and sometimes seemingly immune to any treatment, understanding their origin and nature is the key to containing them.

Switching regulator AC output content Figure 2.2 details switching regulator dynamic (AC) output content. It consists of relatively low frequency ripple at the switching regulator’s clock frequency, typically 100kHz to 3MHz, and very high frequency content ‘‘spikes’’ associated with power switch transition times. The switching regulator’s pulsed energy delivery creates the ripple. Filter capacitors smooth the output, but not

[(Figure_1)TD$IG]

[(Figure_2)TD$IG]

Figure 2.1 * Conceptual Linear Regulator and Its Filter Capacitors Theoretically Reject Switching Regulator Ripple and Spikes

Figure 2.2 * Switching Regulator Output Contains Relatively Low Frequency Ripple and High Frequency ‘‘Spikes’’ Derived From Regulator’s Pulsed Energy Delivery and Fast Transition Times

Analog Circuit and System Design: A Tutorial Guide to Applications and Solutions. DOI: 10.1016/B978-0-12-385185-7.00002-0 Copyright
2011, Linear Technology Corporation. Published by Elsevier Inc. All rights reserved.

SECTION ONE

Power Management Tutorials

completely. The spikes, which often have harmonic content approaching 100MHz, result from high energy, rapidly switching power elements within the switching regulator. The filter capacitor is intended to reduce these spikes but in practice cannot entirely eliminate them. Slowing the regulator’s repetition rate and transition times can greatly reduce ripple and spike amplitude, but magnetics size increases and efficiency falls1. The same rapid clocking and fast switching that allows small magnetics size and high efficiency results in high frequency ripple and spikes presented to the linear regulator.

Ripple and spike rejection The regulator is better at rejecting the ripple than the very wideband spikes. Figure 2.3 shows rejection performance for an LT1763 low dropout linear regulator. There is 40db attenuation at 100kHz, rolling off to about 25db at 1MHz. The much more wideband spikes pass directly through the regulator. The output filter capacitor, intended to absorb the spikes, also has high frequency performance limitations. The regulator’s and filter capacitor’s imperfect response, due to high frequency parasitics, reveals Figure 2.1 to be overly simplistic. Figure 2.4 restates Figure 2.1 and includes the parasitic terms as well as some new components.

The figure considers the regulation path with emphasis on high frequency parasitics. It is important to identify these parasitic terms because they allow ripple and spikes to propagate into the nominally regulated output. Additionally, understanding the parasitic elements permits a measurement strategy, facilitating reduction of high frequency output content. The regulator includes high frequency parasitic paths, primarily capacitive, across its pass transistor and into its reference and regulation amplifier. These terms combine with finite regulator gain-bandwidth to limit high frequency rejection. The input and output filter capacitors include parasitic inductance and resistance, degrading their effectiveness as frequency rises. Stray layout capacitance provides additional unwanted feedthrough paths. Ground potential differences, promoted by ground path resistance and inductance, add additional error and also complicate measurement. Some new components, not normally associated with linear regulators, also appear. These additions include ferrite beads or inductors in the regulator input and output lines. These components have their own high frequency parasitic paths but can considerably improve overall regulator high frequency rejection and will be addressed in following text.

[(Figure_3)TD$IG]

Figure 2.3 * Ripple Rejection Characteristics for an LT1763 Low Dropout Linear Regulator Show 40dB Attenuation at 100kHz, Rolling Off Towards 1MHz. Switching Spike Harmonic Content Approaches 100MHz; Passes Directly From Input to Output

Note 1: Circuitry employing this approach has achieved significant harmonic content reduction at some sacrifice in magnetics size and efficiency. See Reference 1.

8

9

Figure 2.4 * Conceptual Linear Regulator Showing High Frequency Rejection Parasitics. Finite GBW and PSRR vs Frequency Limit Regulator’s High Frequency Rejection. Passive Components Attenuate Ripple and Spikes, But Parasitics Degrade Effectiveness. Layout Capacitance and Ground Potential Differences Add Errors, Complicate Measurement

[(Figure_4)TD$IG]

10

Figure 2.5 * Circuit Simulates Switching Regulator Output. DC, Ripple Amplitude, Frequency and Spike Duration/Height are Independently Settable. Split Path Scheme Sums Wideband Spikes with DC and Ripple, Presenting Linear Regulator with Simulated Switching Regulator Output. Function Generator Sources Waveforms to Both Paths

[(Figure_5)TD$IG]

Minimizing switching regulator residue in linear regulator outputs

Ripple/spike simulator Gaining understanding of the problem requires observing regulator response to ripple and spikes under a variety of conditions. It is desirable to be able to independently vary ripple and spike parameters, including frequency, harmonic content, amplitude, duration and DC level. This is a very versatile capability, permitting real time optimization and sensitivity analysis to various circuit variations. Although there is no substitute for observing linear regulator performance under actual switching regulator driven conditions, a hardware simulator makes surprises less likely. Figure 2.5 provides this capability. It simulates a switching regulator’s output with independently settable DC, ripple and spike parameters. A commercially available function generator combines with two parallel signal paths to form the circuit. DC and ripple are transmitted on a relatively slow path while wideband spike information is processed via a fast path. The two

[(Figure_6)TD$IG]

Figure 2.6 * Switching Regulator Output Simulator Waveforms. Function Generator Supplies Ripple (Trace A) and Spike (Trace B) Path Information. Differentiated Spike Information’s Bipolar Excursion (Trace C) is Compared by C1-C2, Resulting in Trace D and E Synchronized Spikes. Diode Gating/Inverters Present Trace F to Spike Amplitude Control. Q1 Sums Spikes with DC-Ripple Path From Power Amplifier A1, Forming Linear Regulator Input (Trace G). Spike Width Set Abnormally Wide for Photographic Clarity

CHAPTER 2

paths are combined at the linear regulator input. The function generator’s settable ramp output (trace A, Figure 2.6) feeds the DC/ripple path made up of power amplifier A1 and associated components. A1 receives the ramp input and DC bias information and drives the regulator under test. L1 and the 1W resistor allow A1 to drive the regulator at ripple frequencies without instability. The wideband spike path is sourced from the function generator’s pulsed ‘‘sync’’ output (trace B). This output’s edges are differentiated (trace C) and fed to bipolar comparator C1-C2. The comparator outputs (traces D and E) are spikes synchronized to the ramp’s inflection points. Spike width is controlled by complementary DC threshold potentials applied to C1 and C2 with the 1k potentiometer and A2. Diode gating and the paralleled logic inverters present trace F to the spike amplitude control. Follower Q1 sums the spikes with A1’s DC/ripple path, forming the linear regulator’s input (trace G).

[(Figure_7)TD$IG]

Figure 2.7 * Linear Regulator Input (Trace A) and Output (Trace B) Ripple and Switching Spike Content for CIN = 1mF, COUT = 10mF. Output Spikes, Driving 10mF, Have Lower Amplitude, But Risetime Remains Fast

11

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Linear regulator high frequency rejection evaluation/optimization The circuit described above facilitates evaluation and optimization of linear regulator high frequency rejection. The following photographs show results for one typical set of conditions, but DC bias, ripple and spike characteristics may be varied to suit desired test parameters. Figure 2.7 shows Figure 2.5’s LT1763 3V regulator response to a 3.3V DC input with trace A’s ripple/spike contents, CIN = 1mF and COUT = 10mF. Regulator output (trace B) shows ripple attenuated by a factor of
20. Output spikes see somewhat less reduction and their harmonic content remains high. The regulator offers no rejection at the spike rise time. The capacitors must do the job. Unfortunately, the capacitors are limited by inherent high frequency loss terms from completely filtering the wideband spikes; trace B’s remaining spike shows no risetime reduction. Increasing capacitor value has no benefit at these rise times. Figure 2.8 (same trace assignments as Figure 2.7) taken with COUT = 33mF, shows 5 ripple reduction but little spike amplitude attenuation.

Figure 2.9’s time and amplitude expansion of Figure 2.8’s trace B permits high resolution study of spike characteristics, allowing the following evaluation and optimization. Figure 2.10 shows dramatic results when a ferrite bead immediately precedes CIN2. Spike amplitude drops about 5. The bead presents loss at high frequency, severely limiting spike passage3. DC and low frequency pass unattenuated to the regulator. Placing a second ferrite bead at the regulator output before COUT produces Figure 2.11’s trace. The bead’s high frequency loss characteristic further reduces spike amplitude below 1mV without introducing DC resistance into the regulator’s output path4. Figure 2.12, a higher gain version of the previous figure, measures 900mV spike amplitude - almost 20 lower than without the ferrite beads. The measurement is completed by verifying that indicated results are not corrupted by common mode components or ground loops. This is done by grounding the oscilloscope input near the measurement point. Ideally, no signal should appear. Figure 2.13 shows this to be nearly so, indicating that Figure 2.12’s display is realistic5.

[(Figure_8)TD$IG]

[(Figure_9)TD$IG]

Figure 2.8 * Same Trace Assignments as Figure 2.7 with COUT Increased to 33mF. Output Ripple Decreases By 5, But Spikes Remain. Spike Risetime Appears Unchanged

Figure 2.9 * Time and Amplitude Expansion of Figure 2.8’s Output Trace Permits Higher Resolution Study of Spike Characteristics. Trace Center-Screen Area Intensified for Photographic Clarity in This and Succeeding Figures

Note 2: ‘‘Dramatic’’ is perhaps a theatrical descriptive, but certain types find drama in these things. Note 3: See Appendix A for information on ferrite beads. Note 4: Inductors can sometimes be used in place of beads but their limitations should be understood. See Appendix B. Note 5: Faithful wideband measurement at sub-millivolt levels requires special considerations. See Appendix C.

12

Minimizing switching regulator residue in linear regulator outputs

CHAPTER 2

[(Figure_0)TD$IG]

[(Figure_1)TD$IG]

Figure 2.10 * Adding Ferrite Bead to Regulator Input Increases High Frequency Losses, Dramatically Attenuating Spikes

Figure 2.11 * Ferrite Bead in Regulator Output Further Reduces Spike Amplitude

[(Figure_2)TD$IG]

[(Figure_3)TD$IG]

Figure 2.12 * Higher Gain Version of Previous Figure Measures 900mV Spike Amplitude – Almost 20 Lower Than Without Ferrite Beads. Instrumentation Noise Floor Causes Trace Baseline Thickening

Figure 2.13 * Grounding Oscilloscope Input Near Measurement Point Verifies Figure 12’s Results Are Nearly Free of Common Mode Corruption

13

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References 1. Williams, Jim, ‘‘A Monolithic Switching Regulator with 100mV Output Noise,’’ Linear Technology Corporation, Application Note 70, October 1997 (See Appendices B, C,D,H,I and J) 2. Williams, Jim, ‘‘Low Noise Varactor Biasing with Switching Regulators,’’ Linear Technology Corporation, Application Note 85, August 2000 (See pp 4-6 and Appendix C)

14

3. Williams, Jim, ‘‘Component and Measurement Advances Ensure 16-Bit Settling Time,’’ Linear Technology Corporation, Application Note 74, July 1998 (See Appendix G) 4. LT1763 Low Dropout Regulator Datasheet, Linear Technology Corporation 5. Hurlock, Les, ‘‘ABCs of Probes,’’ Tektronix Inc., 1990

6. McAbel, W.E., ‘‘Probe Measurements,’’ Tektronix Inc., Concept Series, 1971 7. Morrison, Ralph, ‘‘Noise and Other Interfering Signals,’’ John Wiley and Sons, 1992 8. Morrison, Ralph, ‘‘Grounding and Shielding Techniques in Instrumentation,’’ WileyInterscience, 1986 9. Fair-Rite Corporation, ‘‘Fair-Rite Soft Ferrites,’’ Fair-Rite Corporation, 1998

Minimizing switching regulator residue in linear regulator outputs

CHAPTER 2

[(Figure_1)TD$IG]

Appendix A About ferrite beads A ferrite bead enclosed conductor provides the highly desirable property of increasing impedance as frequency rises. This effect is ideally suited to high frequency noise filtering of DC and low frequency signal carrying conductors. The bead is essentially lossless within a linear regulator’s passband. At higher frequencies the bead’s ferrite material interacts with the conductor’s magnetic field, creating the loss characteristic. Various ferrite materials and geometries result in different loss factors versus frequency and power level. Figure A1’s plot shows this. Impedance rises from 0.01W at DC to 50W at 100MHz. As DC current, and hence constant magnetic field bias, rises, the ferrite becomes less effective in offering loss. Note that beads can be ‘‘stacked’’ in series along a conductor, proportionally increasing their loss contribution. A wide variety of bead materials and physical configurations are available to suit requirements in standard and custom products.

Figure A1 * Impedance vs Frequency at Various DC Bias Currents for a Surface Mounted Ferrite Bead (Fair-Rite 2518065007Y6). Impedance is Essentially Zero at DC and Low Frequency, Rising Above 50W Depending on Frequency and DC Current

Source: Fair-Rite 2518065007Y6 Datasheet.

efficiency; parasitic shunt capacitance allows unwanted high frequency feedthrough. The inductor’s circuit board position may allow stray magnetic fields to impinge its winding, effectively turning it into a transformer secondary. The resulting observed spike and ripple related artifacts masquerade as conducted components, degrading performance. Figure B2 shows a form of inductance based filter constructed from PC board trace. Such extended length traces, formed in spiral or serpentine patterns, look inductive at high frequency. They can be surprisingly effective in some circumstances, although introducing much less loss per unit area than ferrite beads.

Appendix B Inductors as high frequency filters Inductors can sometimes be used for high frequency filtering instead of beads. Typically, values of 2mH to10mH are appropriate. Advantages include wide availability and better effectiveness at lower frequencies, e.g., 100kHz. Figure B1 shows disadvantages are increased DC resistance in the regulator path due to copper losses, parasitic shunt capacitance and potential susceptibility to stray switching regulator radiation. The copper loss appears at DC, reducing

[(Figure_2)TD$IG] [(Figure_1)TD$IG]

Figure B1 * Some Parasitic Terms of an Inductor. Parasitic Resistance Drops Voltage, Degrading Efficiency. Unwanted Capacitance Permits High Frequency Feedthrough. Stray Magnetic Field Induces Erroneous Inductor Current

Figure B2 * Spiral and Serpentine PC Patterns are Sometimes Used as High Frequency Filters, Although Less Effective Than Ferrite Beads

15

SECTION ONE

Power Management Tutorials

Figure C1 shows a believable presentation of a typical switching regulator spike measured within a continuous coaxial signal path. The spike’s main body is reasonably well defined and disturbances after it are contained. Figure C2 depicts the same event with a 3 inch ground lead connecting the coaxial shield to the circuit board ground plane. Pronounced signal distortion and ringing occur. The photographs were taken at 0.01V/division sensitivity. More sensitive measurement requires proportionately more care. Figure C3 details use of a wideband 40dB gain pre-amplifier permitting text Figure 2.12’s 200mV/ division measurement. Note the purely coaxial path, including the AC coupling capacitor, from the regulator, through the pre-amplifier and to the oscilloscope. The coaxial coupling capacitor’s shield is directly connected to the regulator board’s ground plane with the capacitor center conductor going to the regulator output. There are no non-coaxial measurement connections. Figure C4, repeating text Figure 2.12, shows a cleanly detailed rendition of the 900mV output spikes. In Figure C5 two inches of ground lead has been deliberately introduced at the measurement site, violating the coaxial regime. The result is complete corruption of the waveform presentation. As a final test to verify measurement integrity, it is useful to repeat Figure C4’s measurement with the signal path input (e.g., the coaxial coupling capacitor’s center conductor) grounded near the measurement point as in text Figure 2.13. Ideally, no signal should appear. Practically, some small residue, primarily due to common mode effects, is permissible.

Appendix C Probing technique for sub-millivolt, wideband signal integrity Obtaining reliable, wideband, sub-millivolt measurements requires attention to critical issues before measuring anything. A circuit board layout designed for low noise is essential. Consider current flow and interactions in power distribution, ground lines and planes. Examine the effects of component choice and placement. Plan radiation management and disposition of load return currents. If the circuit is sound, the board layout proper and appropriate components used, then, and only then, may meaningful measurement proceed. The most carefully prepared breadboard cannot fulfill its mission if signal connections introduce distortion. Connections to the circuit are crucial for accurate information extraction. Low level, wideband measurements demand care in routing signals to test instrumentation. Issues to consider include ground loops between pieces of test equipment (including the power supply) connected to the breadboard and noise pickup due to excessive test lead or trace length. Minimize the number of connections to the circuit board and keep leads short. Wideband signals to or from the breadboard must be routed in a coaxial environment with attention to where the coaxial shields tie into the ground system. A strictly maintained coaxial environment is particularly critical for reliable measurements and is treated here1.

[(Figure_1)TD$IG]

[(Figure_2)TD$IG]

Figure C1 * Spike Measured Within Continuous Coaxial Signal Path Displays Moderate Disturbance and Ringing After Main Event

Figure C2 * Introducing 300 Non-Coaxial Ground Connection Causes Pronounced Signal Distortion and Post-Event Ringing

Note 1: More extensive treatment of these and related issues appears in the appended sections of References 1 and 2. Board layout considerations for low level, wideband signal integrity appear in Appendix G of Reference 3.

16

Minimizing switching regulator residue in linear regulator outputs

CHAPTER 2

[(Figure_3)TD$IG]

Figure C3 * Wideband, Low Noise Pre-Amplifier Permits Sub-Millivolt Spike Observation. Coaxial Connections Must be Maintained to Preserve Measurement Integrity

[(Figure_4)TD$IG]

[(Figure_5)TD$IG]

Figure C4 * Low Noise Pre-Amplifier and Strictly Enforced Coaxial Signal Path Yield Text Figure 2.12’s 900mVP-P Presentation. Trace Baseline Thickening Represents Pre-Amplifier Noise Floor

Figure C5 * 2 Inch Non-Coaxial Ground Connection at Measurement Site Completely Corrupts Waveform Presentation

17

Power conditioning for notebook and palmtop systems

Robert Dobkin Tim Skovmand

Carl Nelson Milt Wilcox

Dennis O’Neill

Steve Pietkiewicz

Introduction Notebook and palmtop systems need a multiplicity of regulated voltages developed from a single battery. Small size, light weight, and high efficiency are mandatory for competitive solutions in this area. Small increases in efficiency extend battery life, making the final product much more usable with no increase in weight. Additionally, high efficiency minimizes the heat sinks needed on the power regulating components, further reducing system weight and size. Battery systems include NiCad, nickel-hydride, lead acid, and rechargeable lithium, as well as throw-away alkaline batteries. The ability to power condition a wide range of batteries makes the ultimate product much more attractive because power sources can be interchanged, increasing overall system versatility. A main rechargeable battery may be any of the four secondary type cells, with a back-up or emergency ability to operate off alkaline batteries. The higher energy density available in non-rechargeable alkaline batteries allows the systems to operate for extended time without battery replacement. The systems shown here provide power conditioning with high efficiency and low parts count. Trade-offs between complexity and efficiency have been made to maximize manufacturability and minimize cost. All the supplies operate over a wide range of input voltage allowing great flexibility in the choice of battery configuration.

low-loss saturating NPN switch that is normally configured with the negative terminal (emitter) at ground. The LT1432 allows the switch to be floated as required in a step-down converter, yet still provides full switch saturation for highest efficiency.

[(Figure_1)TD$IG]

LT1432 driver for high efficiency 5V and 3.3V buck regulator The LT1432 is a control chip designed to operate with the LT1170 or LT1270 family of switching regulators to make a very high efficiency (Figure 3.1) 5V or 3.3V step-down (buck) switching regulator. These regulators feature a

3

Figure 3.1 * LT1432 5V Efficiency

Analog Circuit and System Design: A Tutorial Guide to Applications and Solutions. DOI: 10.1016/B978-0-12-385185-7.00003-2 Copyright
2011, Linear Technology Corporation. Published by Elsevier Inc. All rights reserved.

Power conditioning for notebook and palmtop systems

Many other features have been incorporated into the LT1432 to enhance operation in battery powered applications. An accurate current limit uses only 60mV sense voltage, allows for foldback, and uses ‘‘free’’ PC board trace material for the sense resistor. Logic controlled shutdown mode draws only 15mA battery current to allow for extremely long shutdown periods. The switching IC is powered from the regulator output to enhance efficiency and to allow input voltages as low as 6.5V. The LT1432 has optional Burst Mode operation to achieve high efficiency at very light load currents (0mA to 100mA). In normal switching mode, the standby power loss is about 60mW, limiting efficiency at light loads. In burst mode, standby loss is reduced to approximately 15mW. Output ripple is 150mVP-P in this mode, but this is normally well within the requirements for digital logic supplies. Burst Mode operation would typically be used for ‘‘sleep’’ conditions where IC memory chips remain powered for data retention, but the remainder of the system is powered down. Load current in this mode is typically in the 5mA–100mA range. The operating mode is under logic control. The LT1432 is available in 8-pin surface mount and DIP packages. The LT1170 and LT1270 families are available in a surface mount version of the 5-pin TO-220 package.

CHAPTER 3

Circuit description

controlled by the voltage on the VC pin with respect to the GND pin. This voltage ranges from 1V to 2V as switch currents increase from zero to full scale. Correct output voltage is maintained by the LT1432 which has an internal reference and error amplifier. The amplifier output is level shifted with an internal open collector NPN to drive the VC pin of the switcher. The normal resistor divider feedback to the switcher feedback pin cannot be used because the feedback pin is referenced to the GND pin, which is switching many volts. The feedback pin (FB) is simply bypassed with a capacitor. This forces the switcher VC pin to swing high with about 200mA sourcing capability. The LT1432 VC pin then sinks this current to control the loop. C4 forms the dominant loop pole with a loop zero added by R1. C5 forms a higher frequency loop pole to control switching ripple at the VC pin. A floating 5V power supply for the switcher is generated by D2 and C3 which peak detect the output voltage during switch ‘‘off’’ time. This is a very efficient way of powering the switcher because power drain does not increase with regulator input voltage. However, the circuit is not selfstarting, so some means must be used to start the regulator. This is performed by an internal current path in the LT1432 which allows current to flow from the input supply to the V+ pin during start-up. In both the 5V and 3.3V regulators, D1, L1, and C2 act as the conventional catch diode and output filter of the buck converter. These components should be selected carefully to maintain high efficiency and acceptable output ripple. Current limiting is performed by R2. Sense voltage is only 60mV to maintain high efficiency. This also reduces

The circuit shown in Figure 3.2 is a basic 5V positive buck converter which can operate with input voltages from 6.5V to 25V. The power switch is located between the VSW pin and GND pin on the LT1271. Its current and duty cycle are

[(Figure_2)TD$IG]

Figure 3.2 * High Efficiency 5V Regulator with Manual Burst Mode Operation

19

Power Management Tutorials

SECTION ONE

the value of the sense resistor enough to utilize a printed circuit board trace as the sense resistor. The sense voltage has a positive temperature coefficient to match the temperature coefficient of copper. The basic regulator has three different operating modes, defined by the mode pin drive. Normal operation occurs when the mode pin is grounded. A low quiescent current Burst Mode operation can be initiated by floating the mode pin. Input supply current is typically 1.3mA in this mode, and output ripple voltage is 100mVP-P. Pulling the mode pin above 2.5V forces the entire regulator into micropower shutdown where it typically draws less than 20mA. What are the benefits of using an active (synchronous) switch to replace the catch diode? This is the trendy thing to do, but calculations and actual breadboards show that the improvement in efficiency is only a few percent at best. This can be shown with the following simplified formulas: Diode loss FETswitch loss

¼ ¼

Vf ðVIN  VOUT ÞðIOUT Þ=VIN ðVIN  VOUT ÞðRSW ÞðIOUT Þ2 =VIN

The change in efficiency is: ðDiode loss  FET lossÞ ðEfficiencyÞ2 =ðVOUT ÞðIOUT Þ This is equal to: ðVIN  VOUT ÞðVf  RFET  IOUT ÞðEÞ2 =ðVIN ÞðVOUT Þ If Vf (diode forward voltage)=0.45V, VIN=10V, VOUT=5V, RFET=0.1W, IOUT=1A, and efficiency=90%, the improvement in efficiency is only: ð10V  5VÞð0:45V  0:1 W  1AÞ ð0:9Þ2=ð10VÞð5VÞ ¼ 2:8% This does not take FET gate drive losses into account, which can easily reduce this figure to less than 2%. The added cost, size, and complexity of a synchronous switch configuration would be warranted only in the most extreme circumstances.

Burst Mode efficiency is limited by quiescent current drain in the LT1432 and the switching IC. The typical Burst Mode zero-load input power is 17mW. This gives about one month battery life for a 12V, 1.2AHr battery pack. Increasing load power reduces discharge time proportionately. Full shutdown current is only about 15mA, which is considerably less than the self-discharge rate of typical batteries.

BICMOS switching regulator family provides highest step-down efficiencies The LTC1148 family of single and dual step-down switching regulator controllers features automatic Burst Mode operation to maintain high efficiencies at low output currents. All members of the family use a constant offtime, current mode architecture. This results in excellent line and load transient response, constant inductor ripple current, and well controlled start-up and short circuit currents. The LTC1147/LTC1143 drive a single external P-channel MOSFET, while the LTC1148/LTC1142 and LTC1149 drive synchronous external power MOSFETs at switching frequencies up to 250kHz. Table 3.1 gives an overview of the family with applicability to common notebook DC to DC converter requirements. The LTC1147 is available in an 8-pin SOIC and drives only a single power MOSFET, giving it the smallest PC board footprint at a slight penalty in efficiency. The LTC1148HV/LTC1142HV offer synchronous switching capability at input voltages from 4V to 18V (20V abs max) with a low 200mA quiescent current. The LTC1149 extends synchronous switching operation up to input voltages of 48V (60V abs max) with a slight penalty in quiescent current. The rated current level for all device types is set by the external sense resistor according to the formula IOUT=100mV/RSENSE. The maximum peak inductor current and Burst Mode current are also linked to RSENSE. The peak current is limited to 150mV/RSENSE, while Burst Mode operation automatically begins when the

Table 3.1 LTC1148 Family Applications

LTC1147

LTC1148

LTC1143

LTC1142

LTC1148HV

LTC1142HV

Continuous VIN < 48V

X

Continuous VIN < 18V Continuous VIN < 13.5V

X

X

X

X

Low Dropout 5V

X

X

X

X

X

X

Dual 5V and 3.3V Adjustable

20

LTC1149

X

X

X

X

X

X

X X

X

Power conditioning for notebook and palmtop systems

CHAPTER 3

[(Figure_3)TD$IG]

Figure 3.3 * High Efficiency 3.3V Regulator with Manual Burst Mode Operation

output current drops below approximately 15mV/ RSENSE. In this mode, the external MOSFET(s) are held off to reduce switching losses and the controller sleeps at 200mA supply current (600mA for the LTC1149), while the output capacitor supports the load. When the output capacitor discharges 50mV, the controller briefly turns back on, or ‘‘bursts,’’ to recharge the capacitor. Complete shutdown reduces the supply current to only 10mA (150mA for the LTC1149). The first application shown in Figure 3.4 converts 5V to 3.3V at 1.5A output current. By choosing the LTC11473.3, a minimum board space solution is achieved at a slight penalty in peak efficiency (the LTC1148-3.3 driving synchronous MOSFETs in this application would add

approximately 2.5% to the high current efficiency). Figure 3.5 shows how Burst Mode operation maintains high operating efficiencies at low output currents. In the second application (Figure 3.6), an LTC1148HV-5 is used as the controller for a 10W high efficiency regulator. This circuit can be used with as few as 5 NiCad or NiMH cells thanks to its excellent low dropout performance. Like other members of the family, the LTC1148HV goes to 100% duty cycle (P-channel MOSFET turned on DC) in

[(Figure_5)TD$IG]

[(Figure_4)TD$IG]

Figure 3.4 * High Efficiency Surface Mount 5V to 3.3V Converter Delivers 1.5A in Minimum Board Area

Figure 3.5 * High Operating Efficiency for Figure 3.4 Circuit Spans Three Decades of Output Current

21

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Power Management Tutorials

[(Figure_6)TD$IG]

[(Figure_8)TD$IG]

Figure 3.6 * High Efficiency Low Dropout 5V Switching Regulator Needs Only 200mV Headroom at 1A Output

Figure 3.8 * Operating Efficiency for LTC1149-5 High Efficiency Converter

dropout. The input to output voltage differential required to maintain regulation then simply becomes the product of the load current and total resistance of the MOSFET, inductor, and current sense resistor. In the Figure 3.6 circuit, this total resistance is less than 0.2W. For operation at low input voltages, logic-level MOSFETs must be used. While the 18V input voltage rating of the LTC1148HV and LTC1142HV can generally accommodate most battery packs, the AC wall adapters used in conjunction with notebook systems often dictate significantly higher input voltages. This is the primary home for the LTC1149, shown in the Figure 3.7 application. This 2.5A regulator can operate at input voltages from 8V (limited by the standard MOSFET threshold voltages) to 30V, while still providing excellent efficiency as shown in Figure 3.8. The

synchronous switch plays an increasing role at high input voltages due to the low duty cycle of the main switch. Board layout of Figures 3.4, 3.6 and 3.7’s circuits is critical for proper transition between Burst Mode operation and continuous operation. The timing capacitor pin and inductor current are the two most important waveforms to monitor while checking an LTC1148 family regulator. The timing capacitor pin only goes to 0V during sleep intervals, which should only happen when the load current is less than approximately 20% of the rated output current. Consult the appropriate data sheet for information on proper component location and ground routing.

Surface mount capacitors for switching regulator applications A good rule of thumb for the output capacitor selection in all LTC1148 family circuits is that it must have an ESR less than or equal to the sense resistor value (for example, 0.05W for the Figure 3.6 circuit). In surface mount applications multiple capacitors may have to be paralleled to meet the capacitance, ESR, or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalum capacitors, available in case heights ranging from 2mm to 4mm. For example, if 440mF/10V is called for in an application, 2AVX 220mF/10V (P/N TPSE227K010) could be used. Consult the manufacturer for other specific recommendations.

[(Figure_7)TD$IG]

High efficiency linear supplies Figure 3.7 * High Efficiency 5V/2.5A Regulator Operates from AC Wall Adapters as High as 30V

22

The switching supplies operate over a wide input range while maintaining high efficiency. Alternative notebook systems have been developed for narrow supply operation

Power conditioning for notebook and palmtop systems

using for example, four NiCad batteries and a linear regulator to provide the 5V output. At full charge, four NiCad batteries can be as high as 6V and are allowed to discharge down to 4.5V while directly powering the system. A high efficiency low dropout linear regulator suited for this technique is shown in Figure 3.9. This is a complete IC in a very low cost TO-92 3-pin package driving a low saturation PNP transistor. Many power PNP transistors can be used. The Motorola MJE1123 and Zetex ZBD949 are specified for this application. The dropout voltage of this regulator depends on the PNP transistor saturation and can be in the range of 0.25V at 3A output current — lower at lower current. The simplicity of this system is attractive for notebook applications and efficiency is good since little power is lost across the linear regulator at low input voltages. For input voltages of 5.2V* and above, the output is regulated at 5V. As the battery voltage decreases below 5.2V*, the transistor saturates and the output voltage follows the input voltage down with the saturation voltage of the transistor subtracted from the input voltage. The LT1123 low dropout driver can supply up to 125mA of base current to the pass transistor. At dropout this current is supplied continuously into the base of the pass transistor as the transistor remains in saturation. If

CHAPTER 3

[(Figure_0)TD$IG]

Figure 3.10 * LTC1155 Dual Micropower N-Channel MOSFET Driver

lower drive current is desired an optional resistor (R2) can be inserted in series with the base of the transistor to minimize the drive current and decrease the power dissipation in the IC. An N-channel FET can be inserted in series with the drive lead of the LT1123 to electrically shutdown the system.

Power switching with dual high side micropower N-channel MOSFET drivers [(Figure_9)TD$IG]

Figure 3.9 * LT1123 Dropout Voltage *Actual voltage depends on load current.

The LT1155 dual high side N-channel FET gate driver allows using low cost N-channel FETs for high side switching applications. No external components are needed since an internal charge pump boosts the gate above the positive rail, fully enhancing an N-channel MOSFET. Micropower operation, with 8mA standby current and 85mA operating current, allows use in virtually all battery powered systems even for main power switching. Included on the chip is over-current sensing to provide automatic shutdown in case of short circuits. A time delay can be added in series with the current sense to prevent false triggering on high in-rush loads such as capacitors or lamps. The LTC1155 operates off a 4.5V to 18V supply input and safely drives the gates of virtually all FETs. It is particularly well-suited for portable applications where micropower operation is critical. The device is available in 8-pin SO and DIP packages. The LTC1157 is a dual driver for 3.3V supplies. The LTC1157 internal charge pump boosts the gate drive voltage 5.4V above the positive rail (8.7V above ground), fully enhancing a logic-level N-channel MOSFET for 3.3V high side switching applications. The charge pump is completely on-chip and therefore requires no external components to generate the higher gate voltage. The charge pump has been designed to be very efficient, requiring only 3mA in the standby mode and 80mA while delivering 8.7V to the power MOSFET gate. 23

SECTION ONE

Power Management Tutorials

[(Figure_1)TD$IG] [(Figure_3)TD$IG]

Figure 3.11 * LTC1157 Dual 3.3V MOSFET Driver

[(Figure_2)TD$IG] Figure 3.13 * LT1121 Input Current

Figure 3.12 * LT1121 Micropower Low Dropout Regulator

Figure 3.11 demonstrates how two surface mount MOSFETs and the LTC1157 can be used to switch two 3.3V loads. The gate rise and fall time is typically in the tens of microseconds, but can slowed by adding two resistors and a capacitor as shown on the second channel. Slower rise and fall times are sometimes required to reduce the start-up current demands of large supply capacitors.

LT1121 micropower 150mA regulator with shutdown The LT1121 is a low dropout regulator designed for applications where quiescent current must be very low when output current is low. It draws only 30mA input current at zero load current. Ground pin current increases with load current, but the ratio is about 1:25, so the efficiency of the regulator is only about 4% below theoretical maximum for a linear regulator. More importantly, the ground pin current does not increase significantly when the input voltage falls below the minimum required to maintain a regulated output. These characteristics allow the LT1121 to be used in situations where it is desirable to have the output track the input when the input falls below its normal range. Previous regulators drew such high input current in this condition that micropower operation was not possible. Extra effort was taken to make the LT1121 stable with small output capacitors that have high ESR. A 1mF 24

tantalum output capacitor is suggested, as compared to 10mF for previous designs. Larger output capacitors can be used without fear of instabilities. The LT1121 is ideal for the backup and/or suspend mode power supply in notebook computers. A shutdown pin allows the regulator to be fully turned off, with input current dropping to only 16mA. Careful design of the IC circuitry connected to the input and output pins allows the output to be held high while the input is pulled to ground or reversed, without current flowing from the output back to the input. The input pin can be reversed up to 20V. The LT1121 is available with a fixed output voltage of 3.3V or 5V and as an adjustable device with an output voltage range of 3.75V to 30V. Fixed voltage devices are available in 3-pin SOT-223, and 8-pin SO packages. Adjustable devices are available in an 8-pin SO package. The LT1129, a 700mA version of the LT1121 is also available. The LT1129 includes all of the protection features of the LT1121. No load quiescent current is slightly higher at 50mA and the LT1129 requires a minimum of 3.3mF of output capacitance. The LT1129 is also available with fixed output voltages of 3.3Vand 5Vand in an adjustable version with an output range of 3.75V to 5V. The device is available in a 5-pin DD package.

Cold cathode fluorescent display driver New backlight systems seem universally to use cold cathode fluorescent tubes. Electroluminescent backlights have limited light output and limited life for notebook systems, and have limited usage among notebook and notebook manufacturers. The cold cathode fluorescent, on the other hand, has high efficiency, long life, and high light output. Typically the cold cathode fluorescent wants to be driven with 1mA to 5mA at 30kHz to 50kHz. The driving voltage and current are a function of the manufacturer and tube geometry.

Power conditioning for notebook and palmtop systems

Optimally the current through the tube should be regulated to control its brightness. To understand the operation of the cold cathode fluorescent display driver in Figure 3.14, the circuit should be looked at as two sections; 1. The regulating loop, 2. The high voltage oscillator/driver. The regulating loop consists of an LT1172 switching regulator in a buck mode configuration driving constant current into a self-oscillating converter coupled to a high voltage transformer. The architecture of the driver allows a wide input range of battery voltage while maintaining fluorescent tube current constant. In negative buck mode, the LT1172 periodically connects inductor L1 to ground via the switch pin. This creates a flow of current in L1 which is steered by self-oscillating transistors Q1 and Q2 to the primary of transformer L2. The output of L2 is a high voltage AC waveform that is partially ballasted by the 15pF capacitor. To achieve the desired regulation of actual bulb current, D1 and D2 rectify bulb current and pass one

[(Figure_4)TD$IG]

CHAPTER 3

[(Figure_5)TD$IG]

Figure 3.15 * Two Bulb Adaption for Color

phase through R1. This rectified current is converted to a voltage by R1 and filtered by R3 and C6. The filtered signal becomes a feedback signal to the LT1172, which maintains it at 1.25V. Enclosing the cold cathode fluorescent bulb in a feedback loop allows precise control of its operating current and allows microprocessor control of its brightness. Voltage fed through a resistor to the top of C6, either from a D/A converter or from logic, will control the current through the fluorescent tube, allowing brightness to be varied from a keyboard input. This architecture of a buck converter driving a self-oscillating inverter was chosen because it allows a wide range of input voltages. It is also tolerant of winding ratios on the cold cathode fluorescent transformer. One caution with this circuit is the voltage applied to the bulb terminals is not limited if the feedback loop is broken, so care must be taken to minimize the possibility of power being applied to this circuit with the fluorescent tube removed. Cures for this problem and much more detail on backlight engineering and circuits appear in LTC Application Note 55, ‘‘Techniques for 92% Efficient LCD Illumination.’’

Battery charging Lead acid battery charger

Figure 3.14 * CCFL Inverter

Though not as popular as NiCad, lead acid rechargeable gel cells are attractive because of their high energy density per unit volume. These cells have a long life expectancy when treated properly, but often suffer premature failure because of improper charging. The circuit shown in Figure 3.16 provides a near ideal charging system for lead-acid cells. It has precise nonlinear temperature compensation, constant voltage charging with constant current override, and high efficiency over a wide range of input and battery voltages. The basic charger is a flyback design to allow operation with input voltages above or below battery voltage. The LT1171 IC switcher operates at 100kHz and can deliver up to 15W into the battery. A dual op amp is used to control constant voltage and constant current modes. A1 activates as a current limiter when charging current through R7 25

SECTION ONE

Power Management Tutorials

[(Figure_6)TD$IG]

Figure 3.16 * Lead Acid Battery Charger

exceeds a preset limit determined by R3, R6, and R7. This current limit is included to prevent excess charge current for heavily discharged batteries. Losses in R7 are kept low because the voltage drop across R7 is kept to several hundred millivolts. Lead acid batteries have a nonlinear negative temperature coefficient which must be accurately compensated to ensure long battery life and full charge capacity. R5 is a positive temperature coefficient thermistor (tempsistor) whose +0.7%/ C linear TC is converted to the required nonlinear characteristic by the parallel connection with R2. The combination of R2, R3, and R4 multiply the 1.244V feedback level of the LT1171 to the proper 2.35V level required by one cell at 25 C. A2 is used as a buffer to drive the resistor network. This allows large resistors to be used for the cell multiplier string, R9 and R10. R9 is set at 200k for each series cell over one. R9 current is only 12mA, so it can be left permanently connected to the battery. R1 is added to give the charger a finite output resistance (0.025W/cell) in constant voltage mode to prevent low frequency hunting. 26

NiCAD charging Battery charging is a very important section of any notebook system. The battery charging circuits shown here for nickel cadmium or nickel metal hydride batteries control the current into the battery but do not detect when full battery charge is reached. The first circuit, Constant Current Battery Charger (Figure 3.17), is built around a flyback configuration. This allows the battery voltage to be lower or higher than the input voltage. For example, a 16V battery stack may be charged off of a 12V automobile battery. The charge current is sensed by R4, a 1.2W resistor and set at approximately 600mA. Resistors R5 and R6 limit the peak output voltage when no battery is connected. Diode D3 prevents the battery discharging through the divider network when the charger is off, while transistor Q1 allows electronic shutdown of the charger. The next two chargers are a high efficiency buck charger configuration. The input voltage must be higher than the battery voltage for charging to occur. These chargers are

Power conditioning for notebook and palmtop systems

CHAPTER 3

[(Figure_7)TD$IG]

Figure 3.17 * Constant Current Battery Charger

90% efficient when charging at maximum output current. No heat sinks are needed on either the switching regulator or diodes because the efficiency is so high. The dual rate battery charger in Figure 3.18 uses a logic signal to toggle between a high charge rate, up to 2A, or a trickle rate for keep alive. An LT1006 amplifier senses the current into the battery and drives the feedback pin of an LT1171 switching regulator. The entire control circuit is bootstrapped to the LT1171 and floats at the switching frequency, so stray capacitance must be minimized. A gain setting transistor changes the gain on the LT1006 by shorting or opening resistor R1. This changes the charge rate, for the value shown, between 0.1A and 1A. The charger in Figure 3.19 is programmable with a voltage from D-A converters. The charging current is directly proportional to the program voltage. A small sense resistor in the bottom side of the battery senses the battery charging current. This is compared with the program voltage and a feedback signal is developed to drive the LT1171 VC pin. This controls the charging current from the LT1171 and with appropriate control circuits any battery current may be programmed. Efficiency during high charge currents is 90%.

LCD display contrast power supply LCD display typically requires between 18V and 24V to set the contrast of the display. Usually, a switching regulator is needed in the system to generate this voltage

although it runs at low power. The LT1172 generates the voltage with a minimum parts count. The circuit in Figure 3.20 works by generating +18V to +24V in a boost configuration and then inverting the voltage by charge pumping. This allows the use of a small inductor for the converter rather than a transformer.

A 4-cell NiCad regulator/charger The new LTC1155 Dual Power MOSFET Driver delivers 12Vof gate drive to two N-channel power MOSFETs when powered from a 5V supply with no external components required. This ability, coupled with its micropower current demands and protection features, makes it an excellent choice for high side switching applications which previously required more expensive P-channel MOSFETs. A notebook computer power supply system in Figure 3.21 is a good example of an application which benefits directly from this high side driving scheme. A 4cell, NiCad battery pack can be used to power a 5V notebook computer system. Inexpensive N-channel power MOSFETs have very low ON resistance and can be used to switch power with low voltage drop between the battery pack and the 5V logic circuits. Figure 3.21 shows how a battery charger and an extremely low voltage drop 5V regulator can be built using the LTC1155 and three inexpensive power MOSFETs. One half of the LTC1155 Dual MOSFET Driver controls 27

SECTION ONE

Power Management Tutorials

[(Figure_8)TD$IG]

Figure 3.18 * High Efficiency Dual Rate Battery Charger (Up to 2A)

the charging of the battery pack. The 9V, 2A current limited wall unit is switched directly into the battery pack through an extremely low resistance MOSFET switch, Q2. The gate drive output, pin 2, generates about 13V of gate drive to fully enhance Q1 and Q2. The voltage drop across Q2 is only 0.17Vat 2A and, therefore, can be surface mounted to save board space. An inexpensive thermistor, RT1, measures the battery temperature and latches the LTC1155 off when the temperature rises to 40 C by pulling low on pin 1, the Drain Sense Input. The window comparator also ensures that battery packs which are very cold ( > =

> > > ;

ð15Þð0:5Þð18þ5Þ 0:5 ð2:64Þ2 ð0:2Þ þ þ ¼2:92A 0:8ð18Þð5Þ 2 5 2:64A

The transformer must be sized so that the core does not saturate with 2.92A in the primary winding. Note that there is plenty of margin on 5A maximum switch current. A smaller core could be used if DI were increased to 1A,

Load and line regulation are affected by many ‘‘open loop’’ factors in this circuit because the actual output voltage is not sensed—only the primary. Some of these factors are core nonlinearities, diode resistance, leakage inductance, winding resistance, (including skin effect) capacitor ESR and secondary inductance. A typical load regulation for this circuit with a load variation from 20% to 100% is
3%. Line regulation at light loads is better than 0.3% for VIN = 4.5V to 5.5V, but degrades to
1% for full loads. With multiple output supplies obtained from a single switching loop, the problem of cross regulation appears. In this supply, and increase in load current from 50mA to 200mA on one output, with a constant 50mA load on the second output, will cause the loaded output to drop 280mV and the constant load output to rise 100mV. If improved line and load regulation are necessary, a modification can be made to the basic circuit as shown overleaf:

87

SECTION TWO

Switching Regulator Design

Frequency compensation The frequency compensation capacitor C2 is much lower in this design than in others because the gm of the LT1070 is much lower in the isolated mode than in the normal mode. See frequency compensation section for details.

Positive current-boosted buck converter

R2 is split into two resistors with the center tap coupled to the ground pin of the LT1070 through CW. A small resistor RW is inserted in series with the ground pin. When a load is applied to the output, input current flowing through RW causes the voltage drop across R2 to increase. This increases regulated primary voltage and thereby output voltage, cancelling the open-loop load regulation effects mentioned earlier. Line regulation is also significantly improved at full load. The value of RW is found from: RW ¼

ðRO ÞðVIN ÞðEÞðR2Þ ðVOUT Þð7kÞðNÞ*

ð101Þ

RO ¼ output resistance without compensation ¼ DVOUT =DIOUT E ¼ efficiency
0:75 *Multiply N by two for dual outputs For the circuit in Figure 5.25, RO is found by loading both outputs simultaneously and summing the changes of the two outputs. With 3% load regulation, at DIOUT = 200mA, this is a total output change of 900mV. RO is then 900mV divided by a current change of 200mA, or 4.5W. VOUT is the sum of the two outputs, =30V, N is (0.875)(2) = 1.75 and R2 is
1.2k: RW ¼

ð4:5Þð5Þð0:75Þð1; 200Þ ¼ 0:055W ð30Þð7kÞð1:75Þ

This low value of resistance preserves the efficiency of the converter, but is sometimes hard to find ‘‘off the shelf.’’ A 1500 length of #26 hookup wire was used for the breadboard. To minimize inductance, the wire is folded in half before winding around a form. CW must be made large enough to prevent loop oscillation problems. The product of CW times the parallel resistance of the two halves of R2 should be several times larger than the basic regulator settling time constant. With load regulation compensation, the effects of cross regulation are worse than with no compensation. Multiple output supplies should be carefully evaluated for all expected conditions of output loading. 88

A current-boosted buck converter is shown in Figure 5.26. It can supply more output current than a standard buck converter or a flyback converter for larger input-output differentials because current flows to the output both when the switch is on and when it is off. The ‘‘on’’ cycle can supply up to 5A to the load. The off cycle will deliver 1/N times that much current. With N = 1/3, current delivered to the load during switch off time will be 15A. Total available load current will depend on switch duty cycle, which in turn is fixed by input voltage. An operational amplifier must be added to generate a feedback signal which floats on top of the regulated output because that is where the ground pin of the LT1070 is tied. A1 is an LM308 selected because its output goes low when both its inputs are equal to the op amp negative supply voltage. This condition occurs at VOUT = 0V during start-up. If the op amp output went high during this condition, the LT1070 would never start up. R1 and R2 set output voltage, with the bottom of R1 returned directly to the load for ‘‘low’’ sensing. R4 and R5 force Kelvin sensing between the output and the ground pin of the LT1070. It appears that these resistors are shorted out, but the voltage drop across the wire from the ground pin of the LT1070 to the output will cause load regulation problems unless it is ‘‘sensed’’ by R4 and R5. These resistors can be eliminated if that wire is heavy gauge and less than 200 long. The following equations should be helpful in designing variations of this circuit. R5 ¼

ðVOUT ÞðR1Þ ðVOUT Þð1:24kÞ ¼ VREF 1:244V

NðMINÞ ¼ DC ¼

ð102Þ

R5 R1 ¼ R4 R2

ð103Þ

VOUT þ VF VM  VIN  VSNUB

ð104Þ

VOUT þ VF VOUT þ VF þ NðVIN  VOUT Þ

ð105Þ

LT1070 design manual

CHAPTER 5

Figure 5.26 * Positive Current Boosted Buck Converter




LPRI ¼

VOUT

ðDIÞðf Þ N þ

VOUT VIN  VOUT



ð106Þ




 VOUT þ VIN  VOUT ð1  NÞ N VPP ¼ ðESRÞðIOUT Þ VIN ð107Þ

IOUTðMAXÞ ¼
  DI VIN IP  ð0:8Þ 2 VOUT þ VF þ NðVIN  VOUT Þ

IPRI ¼

IOUT ½VOUT þ NðVIN  VOUT Þ VIN

ð108Þ

ð109Þ

DC = switch duty cycle DI = peak-to-peak primary ripple current ESR = effective series resistance of C2 IPRI = average primary current during switch-on time VP-P = peak-to-peak output ripple voltage IP = maximum rated switch current for LT1070 The value for NMIN is based on switch breakdown. Low values give higher output current, but also higher switch voltage. DI is normally chosen at 20% to 40% of IPRI. Note that the ripple equation contains the term (1 – N) in the numerator, implying that output ripple current and voltage will be zero for N = 1. This is because of the simplifying assumption that ripple current into the output capacitor is the difference between primary and secondary current. This difference is zero for N = 1 and the equation is no longer valid.

Negative current-boosted buck converter

(Add DI/2 for peak primary current) N = turns ratio VM = LT1070 maximum switch voltage VSNUB = snubber voltage (see flyback section) VF = forward voltage of D1

The negative buck converter in Figure 5.27 is capable of much higher output current than the standard buck converter upper limit of 5A. For design details, see positive current-boosted buck converter and standard negative buck converter sections.

89

SECTION TWO

Switching Regulator Design

Figure 5.27 * Negative Current Boosted Buck Converter

Negative input/negative output flyback converter

Positive-to-negative flyback converter

This circuit in Figure 5.28 is normally used for negative output voltages higher than the negative input. If voltages lower than the input are required, see negative buck converter or negative current-boosted buck converter and standard negative buck converter sections. The voltage divider, R1 and R2, is required to prevent forward bias on Q1. Connect R1, R2 and R3 exactly as shown for proper output sensing. Further design details may be taken from positive flyback converter section.

The positive input-negative output flyback converter in Figure 5.29 requires an external op amp to generate the feedback signal for the LT1070. R1 and R2 set output voltage with R1 scaled at 1kW/V. The bottom of R1 goes directly to the output for sensing. R3 and R4 provide the ground (low) sense. Any voltage drop between the ground pin of the LT1070 and the actual ground (+) output can cause load regulation problems. These are eliminated if R3 and R4 are connected exactly as shown. R3 and R4 can be

Figure 5.28 * Negative Input-Negative Output Flyback Converter

90

LT1070 design manual

CHAPTER 5

Figure 5.29 * Positive Input-Negative Output Flyback Converter




 N volts ðVOUT  VIN Þ 1þN

eliminated if the LT1070 ground pin is connected directly to output ground with a very short heavy wire. For design details, see positive flyback converter.

Voltage-boosted boost converter The standard boost converter has a maximum output voltage slightly less than the maximum switch voltage of the LT1070. If higher voltages are desired, the inductor can be tapped as shown in Figure 5.30. The effect of the tap is to reduce peak switch voltage by:

[(Figure_0)TD$IG]

A large value for N will allow high output voltages to be regulated without exceeding maximum switch voltage. A snubber is needed now to handle leakage inductance of the tap point. The following formulas will be helpful for variations on this design. NðMINÞ ¼

VOUT  VM þ VSNUB ðuse max VIN Þ VM  VIN  VSNUB

DC ¼

VOUT  VIN VOUT þ NðVIN Þ

ð111Þ

IP DI 2 ðVIN Þ VOUT þ NðVIN Þ

ð112Þ

IOUT ½VOUT þ NðVIN Þ VIN

ð113Þ

IOUTðMAXÞ ¼

IPRI ¼

ð110Þ

Average during switch-on time. For peak, add DI/2. LPRI ¼ Figure 5.30 * Voltage-Boosted Boost Converter

VIN ðVOUT  VIN Þ ðDIÞðf Þ½VOUT þ NðVIN Þ

ð114Þ

DI
20% to 40% of IPRI

91

SECTION TWO

Switching Regulator Design

ðIOUT ÞðESRÞ½VOUT þ NðVIN Þ VP-P ¼ VIN ðN þ 1Þ

ð115Þ

DC = switch duty cycle VSNUB = snubber voltage (see flyback section for details) VM = maximum allowed LT1070 switch voltage IP = maximum LT1070 switch current DI = peak-to-peak primary current ripple ESR = effective series resistance of C VP-P = peak-to-peak output voltage ripple L1 should be wound for minimum leakage inductance by using bifilar winding or interleaved windings. R3 and C2 are selected using the technique described in the frequency compensation section. For snubber details see flyback description section. This regulator is not short-circuit proof because L1 and D1 short input to ground when output is shorted.

Negative boost converter The LT1070 can be used as a negative boost regulator as shown in Figure 5.31 by using the same diode-coupled feedback technique used in the positive buck mode. Basically, D2 and C3 create a peak detector which gives a voltage across C3 equal to the output voltage. R1 and R2 act as a voltage divider to set output voltage at: ðVREF ÞðR1 þ R2Þ=R2

compensate for the series resistance of D1 as it affects load regulation.

Positive-to-negative buck boost converter This positive-to-negative converter uses the same feedback technique as the positive buck converter. Normal feedback cannot be used because the ground pin of LT1070 is switching back and forth between +VIN and VOUT. To generate a floating feedback signal, D2 peak detects the output voltage during the LT1070 switch-off time. This voltage appears across C3 as a floating DC level which is used as feedback to the LT1070. Output voltage is set by the ratio of R1 to R2. R4 is used to limit the effect of turnon spikes across the main catch diode, D1. Without this resistor, D1 turn-on spikes would cause C3 to charge to an abnormally high voltage and the output voltage would sag down at high load currents. D3 and C4 are used to generate a floating supply for the LT1070. The voltage across C4 will peak detect to (VOUT) volts. R5 is added to ensure start-up. R6 is a preload, required only if the normal load can drop to zero current. For further design details on this circuit, the basic formulas from the negative-to-positive buck/boost converter may be used, along with the feedback explanation from the positive buck converter.

C3 also acts as a floating power supply for the LT1070. The ground pin of the LT1070 switches back and forth between the output voltage and ground to drive the inductor, L1. For proper circuit operation, a minimum preload of 10mA is required on the output (shown as R0). For further design information, see positive boost converter section for details on L1, C1, D1 and output filters. The feedback scheme used here is discussed in more detail in the positive buck section. A refinement in the feedback is that the power transistor driver current flowing into the VIN pin must come from D2 and C3. This tends to

[(Figure_1)TD$IG]

Current-boosted boost converter

Figure 5.31 * Negative Boost Regulator

92

This tapped inductor version of the boost converter can offer significant increases in output power when the inputoutput voltage differential is not too high. The ratio of output current for this converter compared to a standard boost converter is:

LT1070 design manual

IOUT ¼ IBOOST

CHAPTER 5

Nþ1  VIN N 1 þ1 VOUT


If VOUT ! VIN, the increase in output current approaches N + 1. Maximum N, however, is limited by switch breakdown voltage: NðMAXÞ ¼

VM  VOUT  VSNUB VOUT  VMIN

VM = maximum LT1070 switch voltage VSNUB = snubber voltage (see flyback section) VMIN = minimum input voltage For VM = 60V, VOUT = 28V, VSNUB = 8V, VMIN = 16V: NðMAXÞ ¼

60  28  8 ¼2 28  16

Forward converter

The increase in output current is: IOUT IBOOST

2þ1

¼ ¼ 1:62 ¼ 62% 2 1  16 28 þ 1

Actual maximum output current is: IOUTðMAXÞ ¼

IP  DI=2 5  0:5 ¼ ¼ 4:15A VOUT N 28 2   VMIN N þ 1 16 3

IP = maximum LT1070 switch current DI = increase in inductor current during switch-on time DI ¼

VOUT  VIN  N ðLÞðf Þ VVOUT  Nþ1 IN

L = total inductance Operating duty cycle is given by: DC ¼

VOUT  VIN  N VOUT  Nþ1 ðVIN Þ

A reasonable value for total inductance is found by assuming that this circuit is used near peak switch current of 5A and allowing a 20% increase in switch current during switch-on time!Dl = 1A: LTOTAL ¼

¼

VOUT  VMIN
 VOUT N ðf ÞðDIÞ  VMIN N þ 1 28  16
 ¼ 277mH 28 2 ð40  103 Þð1Þ  16 3

Snubber values are empirically selected to limit snubber voltage to the value chosen (
8V). For lowest snubber losses, the ‘‘1’’ and ‘‘N’’ sections of the inductor should be wound for maximum coupling (consult manufacturers).

Forward converters can use smaller cores than flyback converters because they do not need to store energy in the core. Energy is transferred directly to the output during switch ‘‘on’’ time. The output secondary (N) is positive and delivering current through D1 when the LT1070 switch is on (VSW low). At switch turn-off, the output winding goes negative and output current flows through D2 as in a buck regulator. A third winding (M) is needed in a single switch forward converter to define switch voltage during switch-off time. This ‘‘reset’’ winding, however, limits the maximum duty cycle allowed for the switch. The voltage across the switch during its off state is: VIN þ VSNUB VSW ¼ VIN þ M VSNUB = snubber voltage spike caused by leakage inductance By rearranging this formula, a minimum value for M can be found: VINðMAXÞ MðMINÞ ¼ VM  VINðMAXÞ  VSNUB VM = maximum LT1070 switch voltage VIN(MAX) = maximum input voltage For the circuit shown, with VIN(MAX) = 30V, and selecting VSNUB = 5V and VM = 60V: MðMINÞ ¼

30 ¼ 1:2 60  30  5

The value of M will define maximum switch duty cycle. If the LT1070 attempts to operate at a duty cycle above this limit, the core will saturate because the volt-second product across the primary in the switch-off state will not be enough to keep flux balance. Duty cycle is limited to: DCðMAXÞ

1 1 ¼ ¼ 45% 1 þ M 1 þ 1:2 93

Switching Regulator Design

SECTION TWO

For maximum output current, N should be as small as possible. Smaller values of N, however, require larger duty cycles, so N is limited to a minimum of: NðMINÞ ¼

ðM þ 1ÞðVOUT þ VF Þ VINðLOWÞ

VF = D1 and D2 forward voltage VIN(LOW) = minimum input voltage For the circuit shown, with VF = 0.6V, VIN(LOW) = 20V: NðMINÞ ¼

ð1:2 þ 1Þð5 þ 0:6Þ ¼ 0:62 20

To avoid core saturation during normal operation, primary inductance must be a minimum value determined by core volume and core flux density:     VOUT þ VF 2 ð0:4pÞðme Þ LPRI  ðNÞðBM Þðf Þ ðVe Þð108 Þ BM = maximum operating flux density f = LT1070 operating frequency (40kHz) Ve = core volume me = effective core permeability For BM = 2000 gauss (typical for ferrites), Ve = 6cm3, and me = 1500, VOUT + VF = 5.6V, N = 0.62:  2   5:6 ð0:4 pÞð1500Þ LPRI  ð0:62Þð2000Þð40  103 Þ ð6Þð108 Þ ¼ 400mH The operating flux density of forward converters is often limited by temperature rise rather than saturation. At 2000 gauss, the core loss of a typical ferrite is 0.25W/cm3. Total core loss at Ve = 6cm3
1.5W. When this is combined with copper winding losses, there may be excess core temperatures. Larger cores will allow more space for

94

copper, or can be operated at lower flux density with the same copper loss. See transformer design guide for further details. Conventional forward converters use a flip-flop to limit maximum duty cycle to 50% and set M = 1. The LT1070 will let duty cycle go to
95% during start-up and low input voltage conditions. This would cause core saturation and subsequent primary and switch currents of up to 10A. To avoid this, Q1 and R5 have been added. Onset of core saturation will cause a voltage drop across R5 high enough to turn on Q1 at each cycle. This pulls down on the VC pin, reducing duty cycle and maintaining normal switch currents. R6 and C4 filter out spikes. Operating duty cycle is given by: DC ¼

VOUT þ VF ðNÞðVN Þ

The output filter inductor (L1) is chosen as a trade-off between maximum output power, output ripple, physical size and loop transient response. A reasonable value is one which gives a peak-to-peak inductor ripple current (DIL) of
20% of IOUT. This leads to a value for L1 of: L1 ¼

VOUT ½ðNÞðVIN Þ  VOUT ½ð0:2ÞðIOUT Þ ½ðNÞðVIN Þðf Þ

For IOUT = 6A, VIN = 25V, VOUT = 5V, N = 0.62: L1 ¼

5½ð0:62Þð25Þ  5 ¼ 70mH ½ð0:2Þð6Þ ½ð0:62Þð25Þð40  103 Þ

Larger values of L1 will increase maximum output current only slightly. Output ripple voltage will go down inversely with larger L1, but physical size will quickly become a problem for large values because the inductor must handle large DC currents. Peak inductor current is equal to IOUT + DIL/2.

LT1070 design manual

Maximum output current for this forward converter is given by:
 IP DIL DIPRI   ð0:9Þ IOUTðMAXÞ ¼ N 2 N IP = maximum LT1070 switch current DIPFI = peak primary magnetizing current =VOUT/(f)(N)(LPRI) DIL = peak-to-peak output inductor current 0.9 = fudge factor for losses For IP = 5A, N = 0.62, DlL = 1.2A, DIPFI = 0.5A:
 5 1:2 0:5 IOUTðMAXÞ ¼   ð0:9Þ ¼ 6A 0:62 2 0:62 Output voltage ripple (P-P) is assumed to be set by L1 and the ESF of C1: VPP ¼ ðDIL ÞðESR1Þ ¼

ESR1ðVOUT Þ½NðVIN Þ  VOUT ðL1Þðf ÞðNÞðVIN Þ

ESR1 = effective series resistance of C1 If we assume 0.02W for ESF1, and VIN = 25V, VP-P

¼

ð0:02Þð5Þ½ð0:62Þð25Þ  5 ð70  106 Þð40  103 Þð0:62Þð25Þ

¼

24mVPP

If less output ripple is desired, the most effective method may be to add an LC filter. See section on output filters.

Frequency compensation Although the architecture of the LT1070 is simple enough to lend itself to a mathematical approach to frequency compensation, the added complication of input and/or output filters, unknown capacitor ESR, and gross operating point changes with input voltage and load current

CHAPTER 5

variations all suggest a more practical empirical method. Many hours spent on breadboards have shown that the simplest way to optimize the frequency compensation of the LT1070 is to use transient response techniques and an ‘‘R/C box’’ to quickly iterate toward the final compensation network. There are many ways to inject a transient signal into a switching regulator, but the suggested method is to use an AC coupled output load variation. This technique avoids problems of injection point loading and is general to all switching topologies. The only variation required may be an amplitude adjustment to maintain small signal conditions with adequate signal strength. Figure 5.32 shows the setup. A function generator with 50W output impedance is coupled through a 50W/1000mF series RC network to the regulator output. Generator frequency is noncritical. A good starting point is
50Hz. Lower frequencies may cause a blinking scope display which is annoying to work with. Higher frequencies may not allow sufficient settling time for the output transient. Amplitude of the generator output is typically set at 5VP-P to generate a 100mAP-P load variation. For lightly loaded outputs (IOUT < 100mA), this level may be too high for small signal response. If the positive and negative transition settling waveforms are significantly different, amplitude should be reduced. Actual amplitude is not particularly important because it is the shape of the resulting regulator output waveform which indicates loop stability. A 2-pole oscilloscope filter with f = 100kHz is used to block switching frequencies. Regulators without added LC output filters have switching frequency signals at their outputs which may be much higher amplitude than the low frequency settling waveform to be studied. The filter frequency is high enough to pass the settling waveform with no distortion. Oscilloscope and generator connections should be made exactly as shown to prevent ground loop errors. The oscilloscope is sync’d by connecting channel ‘‘B’’ probe to the generator output, with the ground clip of the second probe

Figure 5.32 * Testing Loop Stability

95

SECTION TWO

Switching Regulator Design

connected to exactly the same place as channel ‘‘A’’ ground. The standard 50W BNC sync output of the generator should not be used because of ground loop errors. It may also be necessary to isolate either the generator or oscilloscope from its third wire (earth ground) connection in the power plug to prevent ground loop errors in the ’scope display. These ground loop errors are checked by connecting channel ‘‘A’’ probe tip to exactly the same point as the probe ground clip. Any reading on channel ‘‘A’’ indicates a ground loop problem. Once the proper setup is made, finding the optimum values for the frequency compensation network is fairly straightforward. Initially, C2 is made large ( 2mF) and R3 is made small (
1k). This nearly always ensures that the regulator will be stable enough to start iteration. Now, if the regulator output waveform is single-pole overdamped, (see the waveforms in Figure 5.33) the value of C2 is reduced in steps of about 2:1 until the response becomes slightly underdamped. Next, R3 is increased in steps of 2:1 to introduce a loop ‘‘zero.’’ This will normally improve damping and allow the value of C2 to be further reduced. Shifting back and forth between R3 and C2 variations will now allow one to quickly find optimum values. If the regulator response is underdamped with the initial large value of C, R should be increased immediately before larger values of C are tried. This will normally bring about the overdamped starting condition for further iteration. Just what is meant by ‘‘optimum values’’ for R3 and C2? This normally means the smallest value for C2 and the largest value for R3 which still guarantee no loop oscillations, and which result in loop settling that is as rapid as possible. The reason for this approach is that it minimizes

the variations in output voltage caused by input ripple voltage and output load transients. A switching regulator which is grossly overdamped will never oscillate, but it may have unacceptably large output transients following sudden changes in input voltage or output loading. It may also suffer from excessive overshoot problems on startup or short circuit recovery. To guarantee acceptable loop stability under all conditions, the initial values chosen for R3 and C2 should be checked under all conditions of input voltage and load current. The simplest way of accomplishing this is to apply load currents of minimum, maximum and several points in between. At each load current, input voltage is varied from minimum to maximum while observing the settling waveform. The additional time spent ‘‘worst-casing’’ in this manner is definitely necessary. Switching regulators, unlike linear regulators, have large shifts in loop gain and phase with operating conditions. If large temperature variations are expected for the regulator, stability checks should also be done at the temperature extremes. There can be significant temperature variations in several key component parameters which affect stability; in particular, input and output capacitor value and their ESR and inductor permeability. LT1070 parametric variations also need some consideration. Those which affect loop stability are error amplifier gm and the transfer function of VC pin voltage versus switch current (listed as a transconductance under electrical specifications). For modest temperature variations, conservative overdamping under worst-case room temperature conditions is usually sufficient to guarantee adequate stability at all temperatures.

Figure 5.33 * Output Transient Response

96

LT1070 design manual

Check margins One measure of stability ‘‘margin’’ is to vary the selected values of both R and C by 2:1 in all possible combinations. If the regulator response remains reasonably well damped under all line and load conditions, the regulator can be considered fairly tolerant of parametric variations. Any tendency towards an underdamped (ringing) response indicates that a more conservative compensation may be needed. There are several large signal dynamic tests which should also be done on a completed regulator design. The first is to check response to the worst-case large amplitude load variation. A sudden change from light load to full load current may cause the regulator to have an unacceptably large transient dip in output voltage. The simplest cure for this is to increase the size of the output capacitor. Lower inductor values and less conservative frequency compensation also help. A second consideration is the output overshoot created when a large load is suddenly removed. This is potentially more dangerous than a dip because a large overshoot may destroy loads still connected to the regulator output.

Eliminating start-up overshoot Another transient condition to be checked is start-up overshoot. When input voltage is first applied to a switching regulator, the regulator dumps full short-circuit current into the output capacitor attempting to bring the output up to its regulated value. The output can then overshoot well beyond its design value before the control loop is able to idle back the output current. The amplitude of the overshoot can be anywhere from millivolts to tens of volts depending on topology, line and load conditions and component values. This same overshoot possibility exists for

CHAPTER 5

output recovery from output shorts. Again, larger output capacitors, smaller inductors and faster loop response help reduce overshoot. There are also several ways to force slow start-up to eliminate the overshoot. The first is to put a capacitor across the output voltage divider. This creates a time-dependent output voltage setting during start-up and usually eliminates overshoot. This capacitor also has an effect on feedback loop characteristics during normal operation and it can create unacceptably large negative transients on the feedback pin if the output voltage is high and a sudden output short occurs. The transient problem is eliminated by inserting a resistor in series with the feedback pin (see feedback pin part of pin description section). If undesirable loop characteristics are created by the capacitor, they can be eliminated by diode coupling the capacitor as shown in Figure 5.34 Another general technique for forcing slow start-up is to clamp the VC pin to a capacitor, C4. The value of R4 is chosen to give a voltage across RZ of 2V at worst-case low input voltage (IR4 = 100mA). C4 is then selected to ramp VC slow enough to eliminate start-up overshoot. C4 should be made no larger than necessary to prevent long reset times. A momentary drop to zero volts at the input may not allow enough time for C4 to discharge fully. If input dropouts of less than 5R4C4 seconds are anticipated, R4 should be paralleled with a diode (cathode to input) for fast reset.

External current limiting The LT1070 has internal switch current limiting which operates on a cycle-by-cycle basis and limits peak switch current to
9A at low duty cycles and
6A at high duty cycles. The actual output current limit value may be much higher or lower depending on topology, input voltage and

Figure 5.34 * Eliminating Start-Up Overshoot

97

SECTION TWO

Switching Regulator Design

output voltage. The following formulas give an approximate value for output current limit under short-circuit output conditions and at the point where output voltage just begins to fall below its regulated value.

OVERLOAD CURRENT (AMPS)

SHORT CIRCUIT CURRENT (AMPS)

Buck

5 to 8


8

Boost

(5to8)(VIN/VOUT)

Not Allowed

Buck-Boost (Inverting)

5 to 8 1þVOUT =VIN Þ


8

CurrentBoosted Buck VoltageBoosted Boost Flyback (Continuous)

 VIN
8/N ð5 to 8Þ VOUT þNðV IN VOUT Þ  IN ð5 to 8Þ VOUT VþNðV Þ IN

Not Allowed

5 to 8 ðVOUT =VIN ÞþN


8/N

Flyback Depends on L (Discontinuous)


8/N

CurrentBoosted Boost

5 to 8 ðVOUT =VIN ÞðN=Nþ1Þ

Not Allowed

Forward

5 to 8/N


8/N

These formulas show that short-circuit current can be much higher than full load current for some topologies. If either full load current or short circuit is much higher than is required for a specific application, external current limiting can be added. This has the advantage of reducing stress on external components, avoiding overload on the input supply and reducing heat sink requirements on the LT1070 itself. The LT1070 is externally current limited by clamping the VC pin. The techniques shown in Figures 5.35 to 5.39 are just a few of the ways this can be accomplished. The relationship between switch current limit point and VC clamp voltage is approximately: ISWðMAXÞ ¼ 9ðVC  1Þ  3  ðDCÞ amps DC = switch duty cycle This relationship is somewhat temperature dependent. The current limit point falls at about 0.3%/ C, so the value set at room temperature should be factored to allow for adequate current limit at higher temperatures. Also, the factor ‘‘9’’ and ‘‘3’’ vary W 30% in production, so a conservative design will normally clamp switch current to about twice the value needed for maximum load current. This

98

can result in rather high short-circuit currents, so the current limit scheme may want to include ‘‘foldback,’’ wherein the peak switch current is clamped to a lower value with VOUT = 0V. By varying the amount of foldback, the short-circuit current can be made greater than, equal to, or less than full load current. Simple current limiting is shown in Figure 5.35. VX is an external voltage which could be a separate regulated voltage or the unregulated input voltage. R2 is selected to give approximately 2V across R1. The value of R1 is kept to 500W or below to keep the knee of the current limit as sharp as possible. If individual adjustment is not necessary, R1 can be replaced with a fixed resistor. (Note that in some topologies the ground, VC and FB pins of the LT1070 are switching at high voltage levels. This will require VX to be referenced to the LT1070 ground pin, not system ground.) In Figure 5.36, D1 has been replaced with a PNP transistor to reduce the current drain through R1 to 100mA. This is helpful in situations where the LT1070 is used in the total shutdown mode. In Figure 5.37, foldback current limiting is generated by clamping the VC pin to an output voltage divider. This will reduce short-circuit current by an amount which depends on the relative values of R3, R4 and R5. R5 is needed to prevent ‘‘latch off,’’ wherein the output current drops to zero during short circuit and stays at zero even if the short is removed. If this latch-off action is desirable, R5 can be eliminated. A normally closed ‘‘start’’ switch can then be placed in series with D1. If nonzero short-circuit current

[(Figure_5)TD$IG]

Figure 5.35 * External Current Limit

[(Figure_6)TD$IG]

Figure 5.36 * External Current Limit

LT1070 design manual

CHAPTER 5

[(Figure_9)TD$IG] [(Figure_7)TD$IG]

Figure 5.37 * Foldback Current Limit Figure 5.39 * External Current Limit

is desired, R5 is selected to give desired short-circuit current and R4 is adjusted for full load current limit. There is some interaction, so R4 should be set to about midspan for initial selection of R5. If less interaction is desired between R4 and R5 adjustments, a 470W resistor can be inserted in series with the wiper on R4 to form a voltage divider with R5. A current transformer (T1) is used in Figure 5.38 to generate a more precise current limit. The primary is placed in series with the output switching diode for buck, flyback and buck/ boost configurations. Output diode peakcurrent is limited to:
 N VOUT  R4 VBE þ IPEAK ¼ R5 R3 þ R4 VBE = base-emitter voltage of Q1 The R3/R4 divider provides foldback as shown in the formula, with short-circuit diode current limited to N(VBE/ R5). In a typical application, R3 is selected to set the voltage across R4 to
1V at normal output voltage. Then R5 is calculated from: R5 ¼

NðVBE þ VR4 Þ IPEAKðPRIÞ

The effective secondary current limit sense voltage is VBE + VR4 at full output voltage and just VBE during short circuit, giving
2.7:1 foldback ratio. The diode in T1 secondary allows the secondary to ‘‘reset’’ between

[(Figure_8)TD$IG]

Figure 5.38 * Transformer Current Limit

current pulses, so that true peak-to-peak diode current is controlled. C1 is used to filter out spikes and noise. In Figure 5.39 a current limit sense resistor (RS) is placed in series with the ground pin of the LT1070. Peak switch current is limited to VBE(Q1)/RS. This circuit is useful only in situations where the negative input line and the negative output line do not have to be common. Power dissipation in RS will be fairly high; P
(0.6V) (IPEAK)(DC), where DC is the duty cycle of the switch. R1 and C1 filter out noise spikes and catch diode reverse turn-off current spikes.

Driving external transistors High input voltage applications using the LT1070 require an external high voltage transistor. The transistor is connected in a common gate or common base mode as shown in Figures 5.40 and 5.41. This allows the LT1070 internal current sensing to continue functioning and operates the external transistor in a mode which maximizes both operating voltage and switching speed capability. In Figure 5.40, the LT1070 drives an N-channel power MOSFET. A separate low voltage supply is used to power the LT1070 and to establish forward gate drive to the MOSFET. Typical gate drive requirement is 10V, with 20V as a typical maximum. The forward gate drive applied to the MOSFET is equal to the supply voltage minus the saturation voltage of the LT1070 switch (saturation voltage

[(Figure_0)TD$IG]

Figure 5.40 * Driving External MOSFET

99

SECTION TWO

Switching Regulator Design

[(Figure_1)TD$IG] provides a forward base current surge at turn-on. Typical values are in the range of 0.005mF to 0.05mF. D1 clamps the emitter voltage at turn-off. It prevents full collector current from flowing out the base lead during the turn-off delay time (0.5m to 2ms). D2 and R1 establish the reverse base turn-off current. The voltage across R2 during turn-off delay time is approximately one diode drop. With R2 = 3W and a diode drop of 800mV, this would create
270mA reverse base current during turn-off. Reverse leakage in the ‘‘off’’ state is not a problem with this circuit because D1 and D2 force the emitter-base voltage to zero bias when the LT1070 switch is off. D1 should be selected for fast turnon. It must handle current equal to collector current for times equal to the turn-off time of the transistor. D2 can be any medium speed diode rated for several hundred milliamps forward current spikes (1N914, etc.).

Figure 5.41 * Driving External NPN

is typically under 1V). D1 is used to clamp the source during turn-off; it does not slow down turn-off. Diode requirements are that it withstand narrow (100ns) current spikes equal to drain current and that it turn ‘‘on’’ rapidly to provide proper clamping. In Figure 5.41, the LT1070 drives an NPN bipolar transistor. These devices require high surge base currents at turnon and turn-off to ensure fast switching times. R1 establishes DC base drive which might be
1/5 of collector current. C1

Output rectifying diode The output diode is often the major source of power loss in switching regulators, especially with output voltages below 10V. It is therefore very important to be able to calculate diode peak current and average power dissipation to ensure adequate diode ratings. The chart in Figure 5.42 lists average diode power dissipation and peak diode current for

[(Figure_2)TD$IG]

Figure 5.42

100

LT1070 design manual

normal loads. It also lists diode current under shorted output conditions where the diode duty cycle approaches 100%, and peak and average currents are essentially the same. The value for diode forward voltage (VF) used in the average power formulas is the voltage specified for the diode under peak current conditions listed in the next column. The peak current formulas assume no ripple current in the inductor or transformer, but average power calculations will be reasonably close even with fairly high ripple. Boost converters in particular are hard on output diodes when the output voltage is significantly higher than the input voltage. This gives peak diode currents much higher than the average, and manufacturers current ratings must be used with caution. The most stressful condition for output diodes is overload or short-circuit conditions. The internal current limit of the LT1070 is typically 9A at low switch duty cycles. This is almost a factor of two higher than the 5A rated switch current, so that even if the regulator is used near its limit at full load, the output diode current may double under current limit conditions. If full load output current requires only a fraction of the 5A rated switch current, the ratio of diode short-circuit current to full load current may be much higher than two to one. A regulator designed to withstand continuous short conditions must either use diodes rated for the full short-circuit current shown in the fourth column, or it must incorporate some form of external current limiting. See current limit section for more details. The last column in Figure 5.42 shows maximum reverse diode voltage. When calculating this number, be sure to use worst-case high input voltage. Transformer or tapped inductor designs may have an additional damped ‘‘ringing’’ waveform which adds to peak diode voltage. This can be reduced with a series R/C damper network in parallel with the diode. Switching diodes have two important transient characteristics: reverse recovery time and forward turn-on time. Reverse recovery time occurs because the diode ‘‘stores’’ charge during its forward conducting cycle. This stored charge causes the diode to act like a low impedance conductive element for a short period of time after reverse drive is applied. Reverse recovery time is measured by forward biasing the diode with a specified current, then forcing a second specified current backwards through the diode. The time required for the diode to change from a reverse conducting state to its normal reverse nonconducting state, is reverse recovery time. Hard turn-off diodes switch abruptly from one state to the other following reverse recovery time. They, therefore, dissipate very little power even with moderate reverse recovery times. Soft turn-off diodes have a gradual turn-off characteristic that can cause considerable diode dissipation during the turn-off interval. Figure 5.43 shows typical current and voltage waveforms for several commercial diode types used in an LT1070 boost converter with VIN = 10V, VOUT = 20V, 2A.

CHAPTER 5

Figure 5.43 * Diode Turn-Off Characteristics

Long reverse recovery times can cause significant extra heating in the diode or the LT1070 switch. Total power dissipated is given by: PtRR ¼ ðVÞðf ÞðtRR ÞðIF Þ V = reverse diode voltage f = LT1070 switching frequency tRR = reverse recovery time IF = diode forward current just prior to turn-off With the circuit mentioned, IF is 4A, V = 20V and f = 40kHz. Note that diode ‘‘on’’ current is twice output current for this particular boost configuration. A diode with tRR = 300ns creates a power loss of: PtRR ¼ ð20Þð40  103 Þð300  106 Þð4Þ ¼ 0:96 W If this same diode had a forward voltage of 0.8V at 4A, its forward loss would be 2A (average current) times 0.8V equals 1.6W. Reverse recovery losses in this example are nearly as large as forward losses. It is important to realize, however, that reverse losses may not necessarily increase diode dissipation significantly. A hard turn-off diode will shift much of the power dissipation to the LT1070 switch, which will undergo a high current and high voltage 101

SECTION TWO

Switching Regulator Design

condition during the duration of reverse recovery time. This has not shown to be harmful to the LT1070, but the power loss remains. Diode turn-on time can potentially be more harmful than reverse turn-off. It is normally assumed that the output diode clamps to the output voltage and prevents the inductor or transformer connection from rising higher than the output. A diode that turns ‘‘on’’ slowly can have a very high forward voltage for the duration of turn-on time. The problem is that this increased voltage appears across the LT1070 switch. A 20V turn-on spike superimposed on a 40V boost mode output pushes switch voltage perilously close to the 65V limit. The graphs in Figure 5.44 show diode turn-on spikes for three common diode types, fast, ultrafast and Schottky. The height of the spike will be dependent on rate of rise of current and the final current value, but these graphs emphasize the need for fast turn-on characteristics in applications which push the limits of switch voltage. Fast diodes can be useless if the stray inductance is high in the diode, output capacitor or LT1070 loop. 20-gauge hookup wire has
30nH/inch inductance. The current fall time of the LT1070 switch is
108A/sec. This generates a voltage of (108)(30  10–9) = 3V per inch in stray wiring.

Keep the diode, capacitor and LT1070 ground/switch lead lengths short.

Input filters Most switching regulator designs draw current from the input supply in pulses. The peak-to-peak amplitude of these current pulses is often equal to or higher than the load current. There is significant high frequency energy in the pulses which can cause EMI problems in some systems. The addition of a simple LC filter between the supply and the switching regulator can reduce the amplitude of this EMI by more than an order of magnitude at the switching frequency and several orders of magnitude at higher harmonic frequencies. The basic filter shown in Figure 5.45 can be added to any switching regulator. The two major design considerations for the filter are the reverse current transfer function which determines ripple attenuation and the filter output impedance function which must satisfy regulator stability criteria. The stability problem occurs because switching regulators have a negative input impedance at low frequencies: ðVIN Þ2 ðVOUT ÞðIOUT Þ

ZIN ðDCÞ ¼ 

The output impedance of the filter has a sharp peak at the LC resonant frequency. If the output impedance is not well below the negative input impedance of the regulator at frequencies up to the bandwidth of the regulator control loop, the possibility for oscillation exists. There is a basic conflict in the two filter requirements. High ripple attenuation is obtained with a large LC product with high Q, but this also tends to aggravate oscillation problems. This conflict is minimized by using large C with smaller L to get the required LC product, but size requirements may also limit this approach. An additional ‘‘fix’’ is to lower the Q of the filter by paralleling L with a small resistor (RF). This has the disadvantage of limiting the filter attenuation at high frequencies. Filter Q is also reduced by the ESR (RS) of the capacitor, but deliberately increasing ESR exacts a heavy penalty in ripple attenuation and power loss.

[(Figure_5)TD$IG]

Figure 5.44 * Diode Turn-On Spike

102

Figure 5.45

LT1070 design manual

Ripple attenuation of an input filter may be calculated from: IOUTðP-PÞ RS RS ðDCÞð1  DCÞ ¼ þ ð LÞ ð f Þ IINðP-PÞ RF RS= effective series resistance of C DC = switching regulator duty cycle Note that this formula does not contain the value of C. This is because large electrolytic capacitors have a total impedance at 20kHz and above which is essentially equal to ESR. For ripple attenuation, therefore, the value of C is not important; the capacitor is selected on the basis of its ESR. A typical filter might consist of a 10mH inductor and a 500mF capacitor with RS = 0.05W. Filter attenuation is least effective at 50% duty cycle (DC = 0.5), so we will use this number now for worst-case purposes. Ripple attenuation of this filter with RF = ¥ is: IOUT ð0:05Þð0:5Þð1  0:5Þ ¼ ¼ 0:031 ¼ 32 : 1 IIN ð10  106 Þð40  103 Þ The formula assumes rectangular wave inputs with triangular outputs and yields the ratio of peak-to-peak values. Higher frequency components of the square wave current are attenuated much more than the overall attenuation figure. Output impedance of the filter given by: ZOUT ¼

1 1 J JvC RS ðvCÞ2  þ þ RF vL 1 þ ðvRS CÞ2 1 þ ðvRS CÞ2

v = radian frequency = 2p(f) This formula has a DC (v = 0) value of zero and a high frequency value equal to RS in parallel with RF. If RS is simply the ESR of the capacitor, both high and low frequency output impedance of the filter is very low. Unfortunately, the output impedance of the filter at its resonant frequency can be significantly higher, and this resonant frequency is typically in the range where switching regulators have negative input impedance. Resonant frequency and peak output impedance formulas are shown below: f ¼

1 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 p LC  ðRS Þ2 ðCÞ2

If RS is simply the ESR of C, the filter resonant frequency is usually closely approximated by: " # 1 ðR S Þ2 ðC Þ pffiffiffiffiffiffi

1 f ¼ L 2 p LC RF ðLCÞ ZOUTðPEAKÞ ¼ LC þ ðRS ÞðRF ÞðCÞ2 Resonant frequency for a 500mF, 10mH filter is
2kHz. Peak output impedance with RF = ¥ and RS = 0.05W is
0.4W.

CHAPTER 5

The criterion for regulator stability is that the filter impedance be much lower than the input impedance of the regulator: RF ðLCÞ

ZIN LC þ ðRS ÞðRF ÞðCÞ2 The worst case occurs with switching regulators that have low input voltage. If we let VIN = 5V, and VOUT = 20V, IOUT = 1A, regulator input impedance at low frequencies is (52)/(20)(1) = 1.25W. The peak filter impedance was calculated at 0.4W, so it seems that stability criterion is met. There is the problem, however, of the too good a capacitor in the filter. If the ESR of C drops to 0.02W, peak filter impedance rises to 1W and stability becomes questionable. To bring peak filter impedance down, RF may have to be added. If RF is set at 1W, peak filter impedance drops to 0.5W. The penalty in ripple attenuation is a reduction from 32:1 to 12:1 for RS = 0.05W. In all this discussion, the output impedance of the actual input source was assumed to be zero. This is not the actual case obviously, and source impedance may have a significant effect on stability. The point of all this is that input filters tend to have resonant frequencies and impedances which fall into the range where they can cause stability problems in switching regulators. It is important, therefore, to include the filter design into the overall regulator design from the beginning. The selected filter must be in place when the regulator is checked for closed-loop stability and the actual source should be used.

Efficiency calculations The primary reason for using switching regulators is efficiency, so it is important to be able to estimate that factor with some degree of accuracy. In many cases, the overall efficiency is not as critical as the power loss in the individual components. For reliable operation, each power dissipating component must be properly sized or heat sunk to ensure that maximum operating temperature is not exceeded. Overall efficiency is then found by dividing output power by the sum of all losses plus output power: E¼

ðIOUT ÞðVOUT Þ SPL þ ðIOUT ÞðVOUT Þ

Sources of power loss include the LT1070 quiescent current, switch driver current and switch ‘‘on’’ resistance; the output diode; inductor/transformer winding and core losses; and snubber dissipation.

LT1070 operating current The LT1070 draws only 6mA quiescent current in its idle state, but this is specified with a voltage on the VC pin such 103

Switching Regulator Design

SECTION TWO

that the output switch never turns on—duty cycle equals zero. When the VC pin is servoed by the feedback loop to initiate switching, supply current at the input pin increases in two ways. First, there is a DC increase proportional to VC pin voltage. This is the result of increasing bias current for the switch driver to ensure adequate switch drive at high switch currents. Second, there is driver current which is ‘‘on’’ only when the output switch is on. The ratio of switch driver current to switch current is
1:40. Total average current into the LT1070 VIN pin is then: IIN
6 mA þ ISW ð0:0015 þ DC=40Þ ISW = switch current DC = switch duty cycle Use of this formula requires knowledge of switch duty cycle and switch current. This information is available in the sections that deal with each particular switching configuration. A typical example is a buck converter with 28V input and 5V, 4A output. Duty cycle is
20% and switch current is 4A. This yields a total supply current of: IIN ¼ 6mA þ 4ð0:0015 þ 0:2=40Þ ¼ 32mA Total power loss due to bias and driver current is equal to input voltage times current: PBD ¼ ðIIN ÞðVIN Þ ¼ ð32mAÞð28VÞ ¼ 0:9W

Schottky switching diodes are recommended for minimum forward voltage and reverse recovery time. Diode losses for most topologies can be approximated by the following formula, but please consult the output diode section for further details: PD
ðIOUT ÞðVF ÞðKÞ þ ðVÞðf ÞðtRR ÞðIF Þ VF = diode forward voltage at peak diode current V = diode reverse voltage tRR = diode reverse recovery time IF = diode forward current at turn-off K = 1 – (VOUT/VIN) for buck converters and 1 for most other topologies In the buck regulator example, with IOUT = 4A and letting VF = 0.7V, tRR = 100ns: PD ¼ ð4Þð0:7Þð1  5=28Þ þ ð28Þð40  103 Þð107 Þð4Þ ¼ 2:3 þ 0:45 ¼ 2:75W

Inductor and transformer losses See section on inductors and transformers.

Snubber losses See section on flyback design.

LT1070 switch losses Switch ‘‘on’’ resistance losses are proportional to the square of switch current multiplied times duty cycle: PSW ¼ ðISW Þ ðRSW ÞðDCÞ RSW ¼ LT1070 switch 00 on00 resistance 2

The maximum specified value for RSW is 0.24W at maximum rated junction temperature, with 0.15W typical value at room temperature. If we use the worst-case number of 0.24W, this yields a switch loss in this example of: PSW ¼ ð4Þ ð0:24Þð0:2Þ ¼ 0:77W 2

It is pure coincidence that switch and driver losses are nearly equal in this example. At low switch currents and high input voltages, PBD dominates, whereas switch losses dominate at low input voltages and high switch currents. AC switching losses in the LT1070 are minimal. Rate of switch current rise and fall is
108A/sec. This reduces switching times to under 50ns and makes the AC losses small compared to DC losses. An exception to this is the AC switch loss attributable to output diode reverse recovery time. See output diode section.

Output diode losses For low to moderate output voltages, the output diode is often the major source of power loss. For this reason, 104

Total losses In this example of a buck regulator, inductor losses might be
1W and snubber losses are zero. Total losses therefore are: SPL ¼ PBD þ PSW þ PD þ PL þ PSNUB ¼ 0:9 þ 0:77 þ 2:75 þ 1 þ 0 ¼ 5:42 W Efficiency is equal to: E¼

ðVOUT ÞðIOUT Þ ð 5Þ ð 4Þ ¼ 78:7% ¼ SPL þ ðVOUT ÞðIOUT Þ 5:42 þ ð5Þð4Þ

This number is typical of a fairly high efficiency 5V buck regulator. The efficiency of 5V switching supplies is lower than higher voltage outputs because of the high diode losses. A 15V output, for instance, might have E
86%.

Output filters Output voltage ripple of switching regulators is typically in the range of tens to hundreds of millivolts if no additional output filter is used. A simple output filter can reduce this ripple by a factor of ten to one hundred at little additional cost. The high frequency ‘‘spikes’’ which may be superimposed on the ripple are attenuated even more.

LT1070 design manual

The presence of high amplitude spikes at the output of switching regulators is often puzzling to first time designers. These spikes occur in switching regulators which, by their topology, cannot use the energy storage inductor as an output filter. These include boost, flyback and buck/boost designs. The output of these converters can be modeled as a switched current source driving the output capacitor as shown in Figure 5.46. The output capacitor is shown as COUT. Its model includes parasitic resistance (RS) and inductance (LS). It is the inductance which creates the output voltage spike. The amplitude of this spike can be calculated if the slew rate (dI/dT) of the switch is known. For simple inductor designs operating at full switch current, dI/dT for the LT1070 switch is approximately 108A/sec. Voltage across LS is:


dI ¼ LS 108 V ¼ LS dT Straight wire has an inductance of about 0.02mH per inch. If we assume one inch of wire on each end of the output capacitor, including board trace length, this represents 0.04mH. Allowing an additional 0.02mH internal inductance, LS has a total value of 0.06mH, yielding:



V ¼ ð0:06Þ 106 108 ¼ 6V These spikes are very narrow ( ‘e ¼effective magnetic path length ðcmÞ=

Ae ¼effective core area ðcm2 Þ me ¼effective permeability ðwith gapÞ

CHAPTER 5

> ;

supplied on core data sheets

Using the ferrite example, and assigning ‘e = 9cm, Ae = 1.2cm2, me = 100, a 200mH inductor would require: sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ð200106 Þð9Þ N¼ ¼34:6 turns ðuse 35Þ ð100Þð1:2Þð0:4 p108 Þ To calculate wire size, the usable winding window area (Aw) must be ascertained from the core dimensions. Many data sheets list this parameter directly. The usable window area must allow for bobbin thickness and clearances. Total copper area is only about 60% of window area due to air gaps around the wire. We can now express the required wire gauge in terms of N and Aw:
 ð0:08ÞðNÞ Wire gauge ðAWGÞ¼10 log ð0:6ÞðAwÞ 0.08 factor = area of #1 gauge wire 0.6 factor = air space loss around wire

FP ¼

ðTL þ 1ÞðNC ÞðDÞ LW

TL = turns per layer NC = number of paralleled conductors (bifilar ! NC = 2) D = wire diameter LW = length of winding (
LB) For 35 turns and 3 layers, TL
12. #14 wire has D = 0.064. NC for a single wire is 1. With LW = 0.900 : FP ¼

ð12 þ 1Þð1Þð0:064Þ ¼ 0:92 0:9

K is now equal to: qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi K ¼ D ðf ÞðFP Þ ¼ 0:064 ð40  103 Þð0:92Þ ¼ 12:3 This is a very high K factor; in fact it is slightly off the graph in Figure 5.48, but for now it illustrates the importance of AC resistance calculations. The various lines on the graph represent the number of layers. With three layers, the AC resistance factor is off scale at approximately 23. This means that AC resistance is 23 times DC resistance. Now we can calculate winding losses. DC winding resistance is found from:

If we assume a value for Aw of 0.2in2 and use N = 35: AWG ¼ 10 log

ð0:08Þð35Þ ¼ 13:68 ðuse #14Þ ð0:6Þð0:2Þ

[(Figure_8)TD$IG]

The next step is to determine the number of winding layers. This is determined by bobbin length, or toroid inside circumference: 2

Layers ¼

NðD þ 0:01Þ ¼ LB

0

3 AWG 1 N4ð0:32Þ@10 20 A þ 0:015 LB

D = wire diameter in inches LB = bobbin length or toroid inside circumference 0.01 = allowance for enamel and spacing

Figure 5.48 * AC Resistance Factor

109

Switching Regulator Design

SECTION TWO

RDC


 ðNÞð‘m Þ AWG 10 4 ¼ 12 10

DI is the ripple current in the winding. It is the change in winding current during the time current is flowing in the winding. For L = 200mH, DI = 2A, N = 35 and Ae = 1.2cm2:

‘m = mean turn length (core specification) For N = 35, ‘m = 2.400 , AWG = #14: RDC

ð35Þð2:4Þ  AWG 4 10 10 ¼ ¼ 0:0176W 12

AC resistance is then DC resistance multiplied by AC resistance factor (FAC): RAC ¼ ðRDC ÞðFAC Þ ¼ ð0:0176Þð23Þ ¼ 0:404W To calculate total losses, DC and AC losses are summed: PW ¼ ðIDC Þ2 ðRDC Þ þ ðIAC Þ2 ðRAC Þ

BAC ¼

ð200  106 Þð2Þ ¼ 476 gauss ð35Þð1:2Þð108 Þ

Core loss per unit volume (Ffe) is found from the manufacturers tables (see Figure 5.49) of Ffe vs flux density and frequency or from the following formula for typical MNZN ferrite material (ferroxcube type 3C8):



Ffe ¼ 1:3  1014 ðBAC Þ2 f 1:45 For BAC = 476 gauss, f = 40kHz:



1:45 ¼ 0:014 W=cm3 Ffe ¼ 1:3  1014 ð476Þ2 40  103 Total core loss is Ffe times core volume:

Formulas for IDC and IAC are shown in Figure 5.50. If we assume IDC = 5A and IAC = 1A, total winding losses are:

PC ¼ ðFfe ÞðVe Þ ¼ ð0:014Þð10Þ ¼ 0:14 W Ve ¼ effective core volume ðcm3 Þ

Pw ¼ ð5Þ2 ð0:0176Þ þ ð1Þ2 ð0:404Þ ¼ 0:44 þ 0:4 ¼ 0:94 W

Core loss for a powdered iron core is approximately 25 times higher than for ferrite. At a lower flux density of 150 gauss, a powdered iron core would still have core losses 2.5 times that of ferrite. Copper losses would also be higher because of the higher inductance required to reduce AC flux density. Powdered iron cores must be carefully designed to avoid overheating. Overall losses in the ferrite core are the sum of winding losses plus core losses:

In this example, AC losses are about equal to DC losses. Simple inductors used in buck, boost and buck/boost designs may have the ratio of AC to DC losses in the range of 0.25 to 4.0. Transformer designs like flyback usually have AC losses much higher than DC losses. Losses in the primary and secondary are calculated separately. In many cases, multiple strands of smaller wire or copper foil must be used to reduce the AC resistance factor to acceptable limits. After winding losses are found, core loss must be calculated. The first step is to find peak AC flux density: BAC ¼

LðDIÞ ð2NÞðAe Þð108 Þ

DI = peak-to-peak winding ripple current

[(Figure_9)TD$IG]

P ¼ PW þ PC ¼ 0:94 þ 0:14 ¼ 1:08W This loss reflects on regulator efficiency, and more importantly, core temperature rise. A 10cm3 core might have a typical thermal resistance of 20 C/W. Temperature rise in this core with P = 1.08W = (1.08)(20) = 21.6 C. 40 C rise is considered a typical design criterion, so this core is being under utilized.

Transformer design example Requirements: A flyback converter with VIN = 28VDC, VOUT = 5V, IOUT = 6A. From previous calculations it is found that N = 1/3, LPRI = 200mH and IPRI(PEAK) = 4.5A, with DI = 1A. 1.

Calculate volume of core required with a gapped core. First assume an effective permeability of ffi150 and B0 = 2500 gauss: ðIPRI Þ2 ðLÞðme Þð0:4 pÞ ðB0 Þ2 ð108 Þ ð4:5Þ2 ð200  106 Þð150Þð0:4 pÞ ¼ 12cm3 ¼ ð2500Þ2 ð108 Þ

Ve ¼

Figure 5.49

110

*

Core Loss vs Flux Density

A Pulse Engineering core #0128.005 has Ve = 13.3cm3, Ae = 1.61cm2, ‘e = 8.26cm, m = 2000.

LT1070 design manual

2.

3.

Calculate required gap:
 m ‘e 1 me g¼
m  2000 1 8:26 00 150 ¼ 0:051cm ¼ 0:02 ¼ 2000

7.

If an ungapped core is used with spacers, spacer thickness should be 0.02/2 = 0.0100 .

8.

Calculate DC winding resistance:  AWG RDC ¼ ðNÞ12ð‘m Þ 10 10 4  16



Calculate required turns: sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ð LÞ ð ‘ e Þ N¼ ðme ÞðAe Þð0:4 p  108 Þ

¼

Calculate wire size. Allocate 1/2 the window space for the primary winding. Window height (build) for the 0128.005 core is 0.2500 and coil length is 0.78200 , giving a window area = (0.25) (0.782) = 0.196in2:

9.

h

Layers ¼

N ð0:32Þ

10.

AWG 10 20



16

23 ð0:32Þ 10 20

¼ 0:023 W

Calculate AC winding resistance:

Calculate primary winding losses. First, primary AC RMS current must be calculated. From the chart in Figure 5.50:



IOUT ¼ E

IDC

i

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ð1=3Þð5Þ ¼ 1:95A 28 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi IOUT VOUT ðVOUT þ N  VIN Þ ¼ E ðVIN Þ2

þ0:01



6 ¼ 0:75

i þ0:01

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 5ð5 þ 1=3  28Þ ¼ 2:4A ð28Þ2

Power loss in the primary winding is:

0:782

Calculate K factor (#16 wire has D = 0.05):
 23 þ 1 ð1Þð0:05Þ ðTL þ 1ÞðNC ÞðDÞ 2 ¼ FP ¼ ¼ 0:8 LW 0:782 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi K ¼ D ðf ÞðFP Þ ¼ 0:05 ð40  103 Þð0:8Þ ¼ 8:94

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðNÞðVOUT Þ VIN

6 ¼ 0:75

¼ 1:79 ðassume 2 layersÞ 6.



Use graph to find AC resistance factor. Interleaving of primary and secondary reduces effective layers by two only if primary and secondary conduct simultaneously, which they do not in a flyback design. Use layers = 2 line:

IAC

LB

h ¼



00

RAC ¼ ðRDC ÞðFAC Þ ¼ ð0:023Þð8:3Þ ¼ 0:19 W

0:08N ð0:08Þð23Þ
 ¼ 10 log 0:196 ð0:6ÞðAwÞ ð0:6Þ 2 ¼ 14:95 ðuse #16Þ

Calculate layers:

12

‘m for this core is
3

AWG ¼ 10 log

5.

4 ð23Þð3Þ 10 10

FAC ¼ 8:3 ðfrom graph; for K ¼ 8:95Þ

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ð200  106 Þð8:26Þ ¼ 23:3 ¼ ð150Þð1:61Þð0:4 p  108 Þ 4.

CHAPTER 5

PW ¼ ðIAC Þ2 RAC þ ðIDC Þ2 RDC ¼ ð1:95Þ2 ð0:19Þ þ ð2:4Þ2 ð0:023Þ ¼ 0:85W 11.

Calculate secondary winding loss. Turns ratio is 1/3, so the secondary will have 23/3 = 7.67 turns. Use 8 turns: AWG ¼ 10 log

0:08 N ð0:08Þð8Þ

¼ 10:4 ¼ 10 log 0:6 Aw ð0:6Þ 0:196 2

111

Switching Regulator Design

SECTION TWO

[(Figure_0)TD$IG]

Figure 5.50 * AC and DC Winding Currents (RMS Equivalent)

This is rather large, stiff wire and the large diameter will lead to large AC winding losses. A good solution might be to use multiple smaller diameter wire wound in parallel. If we use the length of the coil divided by 2N, it will tell us what diameter wire can be bifilar wound to just fill one layer: D¼

With two wires, total RDC = 0.013/2 = 0.0065W. ðTL þ1ÞðNC ÞðDÞ ð8þ1Þð2Þð0:04Þ ¼0:92 ¼ LW 0:782 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi K¼D ðf ÞðFP Þ ¼0:04 ð40103 Þð0:92Þ ¼7:7 FP ¼

From graph, with layers = 1, FAC = 2.3:

LB 0:782 00 ¼ 0:049 ¼ 2N ð2Þð8Þ

RAC ¼ ðRDC ÞðFAC Þ¼ ð0:0065Þð2:3Þ¼0:015 W From the chart in Figure 5.50: sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðVOUT Þ 5 IAC ¼IOUT ¼4:4A ¼6 NðVIN Þ 1=3ð28Þ sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi VOUT þNðVIN Þ 5þ1=3ð28Þ ¼7:4A ¼6 IDC ¼IOUT NðVIN Þ 1=3ð28Þ

The next smallest standard wire diameter is 18. Two #18 wires have three times the DC resistance of a single #10 wire, but AC resistance will not increase nearly that much. Assume one layer bifilar wound #18 secondary interleaved between the two primary layers (to reduce leakage inductance):

 ðNÞð‘m Þ ð 8Þ ð 3Þ AWG 18 4 ¼ 10 4 10 10 12 10 12 ¼0:013 W per wire

RDC ¼

112

PW ¼ð4:4Þ2 ð0:015Þþð7:4Þ2 ð0:0065Þ¼0:65W 12.

Calculate core loss. Core loss is proportional to AC flux density which is determined by change in

LT1070 design manual

primary current (DI) during primary current flow period. For DI = 1A: BAC ¼

LðDIÞ ð200  106 Þð1Þ 8 ¼ 2ðNÞðAe Þð10 Þ 2ð23Þð1:61Þð108 Þ

¼ 270 gauss



Ffe ¼ ð1:3  1014 ÞðBAC Þ2 f 1:45 ¼ 0:0045W=cm3 PC ¼ ðFfe ÞðVe Þ ¼ ð0:0045Þð13:3Þ ¼ 0:06W

uHS

CHAPTER 5



TJ  TA  ðPÞ uJC ¼ P

uHS = heat sink thermal resistance P = LT1070 power dissipation uJC = LT1070 junction-to-case thermal resistance (2 C/W) TJ = LT1070 maximum junction temperature TA = maximum ambient temperature For TJ = 100 C, TA = 60 C, P = 5W:

Total power loss with this core is: uHS ¼

P ¼ PW þ PC ¼ 0:85 þ 0:65 þ 0:06 ¼ 1:56W The 0128.005 core is specified at 2.78W for a 40 C temperature rise, yielding u = 40/2.78 = 14.4 C/W

100  60  ð5Þð2Þ ¼ 6 C=W 5

Troubleshooting hints



DTðcoreÞ ¼ ðPÞðuÞ ¼ ð1:56Þð14:4Þ ¼ 22 C This is a very conservative design. If minimum core size is required, the procedure now is to go back to step 1 and assume a lower effective permeability (me), perhaps 100. This would reduce core volume and require a larger gap. More turns would be required and the available space for copper would go down, so copper losses would go up. Flux density remains constant, so core loss drops. Thermal resistance goes up however, so the smaller core gets hotter. In addition, the increased number of turns will increase leakage inductance, which will increase snubber losses. It isn’t easy, folks!

The following is a list of ‘‘gotchas’’ we’ve put together to help you avoid some of the pitfalls of switching power supply design. They range from obvious to subtle and serious to hilarious. The LT1070 was specifically designed to eliminate many of the problems commonly found in power supply design and be easy to use. The problem is that there are a significant number of easily overlooked mistakes in breadboarding switching regulators which result in either instant death of the IC or electrical characteristics which are puzzling to even highly experienced power supply designers. So here’s the list we’ve collected so far. We hope your problem is on it to save you time and frustration. If not, give us a call and we’ll help fix the problem.

Heat sinking information The efficiency of the LT1070 allows it to be used without a heat sink in many applications, but for full-power output a heat sink is required. The equations contained in the efficiency section of this application note will allow the user to estimate fairly accurately the total power dissipation of the chip under full load conditions. Short-circuit power dissipation can be either more or less than full load, depending on the topology. Calculation of short-circuit power dissipation in the LT1070 is very complicated because the ‘‘on’’ time of the switch is strongly dependent on parasitic effects such as diode and inductor series resistance, wiring losses and leakage inductance. If continuous output shorts must be tolerated, it is strongly suggested that a temperature probe be used to ensure that maximum junction is not exceeded. Thermal resistance from junction to case is 2 C/W maximum, and short-circuit power dissipation almost never exceeds 10W, so a case temperature of 100 C for commercial units and 130 C for military units will ensure that maximum junction temperature is not exceeded. Heat sink size for the LT1070 can be calculated if maximum power dissipation and maximum ambient temperature are known.

Warning Before reading this section, be aware that the intent of the author is not to insult, but rather to relate in an attentiongetting manner a list of goofs that, in many cases, he personally has had to own up to. 1.

Transformer wired backwards Those dots indicate polarity, not smashed flies.

2.

Electrolytic capacitors installed backwards This is no problem until you bend over to see what is wrong—then ‘‘bang,’’ a personal demonstration of explosive venting.

3.

LT1070 input and switch pins reversed The catalog and some preliminary data sheets got out with the wrong pinout for the plastic T0-220 package. Our apologies. Pin 5 is input on T0-220 packages.

4.

No input bypass capacitor Switching regulators draw current from the input supply in pulses. Long input wires can cause dips in the input voltage at the switching frequency. 113

SECTION TWO

Switching Regulator Design

Breadboards should have a large (100mF) input capacitor up close to the regulator.

to avoid overvoltage stress on other components (see diode section).

5.

Fred’s inductor (or transformer) Inductors are not like lawn mowers. If you want to borrow the one out of Fred’s drawer, make sure it’s the right value for your application. A50mH inductor with 50V applied will have a current increasing with time at the rate of 1A per microsecond. It doesn’t take a calculator to see that things can get out of hand quickly during the 25ms period of a 40kHz switcher. Likewise, if ‘‘Fred’s inductor’’ is 50 millihenries, it will probably saturate at such low current levels that it is useless, not to mention the fact that the transient response can be measured on a Simpson VOM. Use the formulas in the application note to get a ball park inductance value before starting a breadboard.

10.

Something from nothing The first step in designing with the LT1070 is to see if it will provide the required power level. Each topology has a different maximum output power that it can provide, depending on things such as input voltage, output voltage and transformer turns ratio. Secondary effects such as inductance values and switch resistance may also limit power. The power graph on the next page is a rough guide to maximum power levels. Use it as a quick guide only. More exact formulas are contained in the application section. Oh, by the way, if you thought about paralleling LT1070s for more power—sorry, it won’t work. You cannot get to the internal 40kHz oscillator to get them in sync.

6.

Wimpy magnetic cores Core sizes for the LT1070 will vary from 3cm3 to 20cm3 of core material for properly designed inductors or transformers. A thumbnail size core will simply saturate and get hot when asked to operate at ampere current levels. Breadboard with man-sized cores, then optimize the core size for production.

11.

7.

Rat’s nest wiring The LT1070 is not a jelly bean op amp that can be wired up with 2-foot clip leads. It achieves its high efficiency by switching current at very high speeds. Long wires will cause every component connected to them to look like an inductor at these speeds. This not only causes totally unpredictable operation; it can generate fatal (to components) transient voltages. Use very short wires to interconnect power components on the breadboard, including bypass capacitors, catch diodes, LT1070 pins, transformer leads, etc.

Input supply gets clobbered The LT1070 can draw input currents of up to 6A during start-up. It has to charge up the large output capacitor and it does this at a rate set by the internal current limit unless optional soft start is added. The start-up surge may trip overcurrent latches on some supplies, causing them to stay off until power is recycled. Steady-state problems can also occur. Switching regulators try to deliver constant load voltage. With a given load, this means constant load power. For a high efficiency system, input power also remains constant, so input current increases as input voltage decreases. Low input voltage conditions may require such high input currents that the input supply current limits. This causes the supply voltage to drop further, forcing a permanent latch condition. See current limit and soft start sections.

12.

Didn’t read the data sheet Then you shall have no pie.

13.

Stray coupling to the VC or FB pins Voltages on the FB and VC pins are referenced to the LT1070 ground pin. In some topologies the ground pin is switching between input voltage and system ground. Stray capacitance between VC or FB pins and system ground will act like coupling to a switching source. Minimize this capacitance. The problem is particularly acute when using an RC box to iterate frequency compensation on the VC pin. Even configurations which have the LT1070 ground pin ‘‘grounded’’ may have problems if the RC box picks up switching energy.

8.

9.

No snubber network The LT1070 will tolerate a lot of abuse, but it cannot be overvoltaged on the switch pin and survive to tell the tale. The 65V maximum switch voltage must be observed. Any design using a transformer or tapped inductor will have enough leakage inductance to cause transients well above 65V if no snubber network is used. Load currents and input voltages should be increased slowly while monitoring switch voltage to ensure that the initial snubber design is adequate. 60Hz diodes The LT1070 will eat 1N914 and 1N4001 diodes and not even burp. Diode currents, especially during start-up, can exceed 5A. This takes care of the 1N914s. The 1N4001s will last for a little while, until the heat generated by their horribly slow turn-off characteristics causes them to self-destruct. Use diodes designed for switching applications, with adequate current ratings. Turn-on time is also important 114

Subharmonic oscillations Current mode switching regulators which operate with a duty cycle greater than 50% and have continuous inductor current can exhibit a duty cycle instability known as

LT1070 design manual

subharmonic oscillations. This effect is not harmful to the regulator and in many cases it does not even affect the output regulation. Its most annoying effect is to produce a high pitched squeal from power components which effectively have their 40kHz operating frequency modulated by submultiple frequencies; 20kHz, 10kHz, etc. Subharmonic oscillations do not depend on the closed-loop characteristics of the regulator. They can occur even when zero feedback is used. Ordinary closed-loop instabilities can also cause audible sounds from switching regulators, but they tend to be in the range of hundreds of hertz to several kilohertz. The source of subharmonic oscillations is the simultaneous conditions of fixed frequency and fixed peak amplitude of inductor current as shown in part a of the accompanying figure.

reduced so that the minimum current point is increased by Dl + DIS2/S1. This will cause the minimum current on the next cycle to decrease by (DI + DI S2/S1)(S2/S1). On each succeeding cycle the current perturbation is multiplied by S2/S1. If S2/S1 is greater than 1, the system is unstable. The condition S2/S1  1 occurs at a duty cycle of 50% or higher. Subharmonic oscillations can be eliminated if an artificial ramp is superimposed on the inductor current waveform as shown in part b of the figure. If this ramp has a slope of SX, the requirement for stability is that SX + S1 be larger than S2. This leads to the following equation: SX 

S1ð2DC  1Þ 1  DC

DC = duty cycle For duty cycles less than 50% (DC = 0.5), SX is a negative number and is not required. For larger duty cycles, SX takes on values dependent on S1 and duty cycle. S1 is simply VIN/L. This yields an equation for the minimum value of inductance for a fixed value of SX: LMIN 

The inductor current starts at l1, at the beginning of each switch on cycle. Current increases at a rate (S1) equal to input voltage divided by inductor value. When current reaches the trip level, I2, the current mode loop shuts off the switch and current begins to fall at a rate S2 until the switch is again turned on by the oscillator. Now watch what happens when the point T1 is perturbed so that the current exceeds I2 by DI. The time left for the current to fall is

CHAPTER 5

VIN ð2DC  1Þ SX ð1  DCÞ

The LT1070 has an internal SX voltage ramp fed into the current amplifier whose equivalent current referred value is 2 (105A/sec). A sample calculation for minimum inductance with VIN = 15V, DC = 60% is shown: LMIN ¼

ð15Þð2  0:6  1Þ ¼ 37:5mH ð2  105 Þð1  0:6Þ

Remember that for discontinuous operation, no subharmonic oscillations can occur. Likewise, with duty cycle less than 50%, there is no restriction on inductor size.

115

SECTION TWO

Switching Regulator Design

ABSOLUTE MAXIMUM RATINGS (Note 1) Supply Voltage LT1070/LT1071 (Note 2) ............................. 40V LT1070HV/LT1071HV (Note 2) .................... 60V Switch Output Voltage LT1070/LT1071 .......................................... 65V LT1070HV/LT1071HV ................................. 75V Feedback Pin Voltage (Transient, 1ms) ......... W15V

Operating Junction Temperature Range Commercial (Operating) ................. 0 C to 100 C Commercial (Short Circuit) .............0 C to 125 C Industrial ................................  40 C to 125 C Military ...................................  55 C to 150 C Storage Temperature Range ......  65 C to 150 C Lead Temperature (Soldering, 10 sec) ..........300 C

ELECTRICAL CHARACTERISTICS VIN = 15V, VC = 0.5V, VFB = VREF, output pin open unless otherwise specified

SYMBOL

PARAMETER

CONDITIONS

VREF

Reference Voltage

Measured at Feedback Pin, VC = 0.8V

IB

Feedback Input Current

VFB = VREF

gm

Error Amplifier Transconductance

DIC = W 25mA

Error Amplifier Source or Sink Current

VC = 1.5V

Error Amplifier Clamp Voltage

Hi Clamp, VFB = 1V Lo Clamp, VFB = 1.5V

Reference Voltage Line Regulation

3V  VIN  VMAX, VC = 0.8V



MIN

TYP

MAX

UNITS

1.224 1.214

1.244 1.244

1.264 1.274

V V

350

750 1100

nA nA

3000 2400

4400

6000 7000

mmho mmho

150 120

200

350 400

mA mA

2.30 0.52

V V

0.03

%/V







1.80 0.25 

0.38

(continued)

116

LT1070 design manual

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

AV

Error Amplifier Voltage Gain

0.9V  VC  1.4V

500

800

Minimum Input Voltage IQ

3V  VIN  VMAX, VC = 0.6V

Control Pin Threshold

Duty Cycle = 0

BV

VSAT

ILIM

ILIM

Flyback Reference Voltage

IFB = 50mA

Change in Flyback Reference Voltage

0.05  IFB  1mA

Flyback Reference Voltage Line Regulation

IFB = 50mA, 3V  VIN  VMAX (Note 3)

Flyback Amplifier Transconductance (gm)

DIC = W10mA

Flyback Amplifier Source and Sink Current

VC = 0.6V, IFB = 50mA (Source) VC = 0.6V, IFB = 50mA (Sink)

Output Switch Breakdown Voltage

3V  VIN  VMAX, ISW = 1.5mA (LT1070/LT1071) (LT1070HV/LT1071HV)

UNITS V/V

3.0

V

6

9

mA

0.8 0.6

0.9

1.08 1.25

V V

0.4

0.45

0.54

V

15 14

16.3

17.6 18.0

V V

4.5

6.8

8.5

V

0.01

0.03

%/V

150

300

650

mmho



15

32

70

mA



25

40

70

mA



65 75

90 90



Normal/Flyback Threshold on Feedback Pin VFB

MAX

2.6



Supply Current

CHAPTER 5





Output Switch ‘‘On’’ Resistance (Note 4)

LT1070 LT1071

Control Voltage to Switch Current Transconductance

LT1070 LT1071

Switch Current Limit (LT1070)

Duty Cycle < 50%, Tj > 25 C Duty Cycle < 50%, TJ < 25 C Duty Cycle = 80% (Note 5)



5

10

A



5

11

A



4

10

A

Duty Cycle < 50%, TJ >25 C Duty Cycle < 50%, TJ 100V) appear across the transformer primary when the LT1071 driven MOSFET turns off. Several measures prevent these spikes from destroying the circuit. The 0.47mF-2k-diode combination, a damper network, conducts during the flyback event. This loads the transformer primary, minimizing flyback amplitude. The damper values are selected empirically, with the tradeoff being power dissipation in them. Very low values markedly reduce flyback potentials but cause excessive dissipation. High values permit low dissipation but allow excessive flyback voltages. The damper values should be selected under fullyloaded output conditions because flyback energy is proportionate to transformer power levels. Appendix C contains additional information on damper network considerations. Even with the damper network, the flyback voltage is too high for the LT1071 output transistor. Q5 prevents the LT1071 from seeing the high voltage. It is connected in series with the LT1071’s output transistor. This 127

SECTION TWO

Switching Regulator Design

[(Figure_6)TD$IG]

Figure 6.6 * Fully-Isolated
48V to 5V Regulator

connection, sometimes called a cascode, lets Q5 stand off the high voltage and the LT1071 operates well within its breakdown limits. Development and testing of this configuration is detailed in Appendix D. Q5 has large parasitic capacitances associated with all terminals. During switching, these capacitances can cause excessive transient voltages to appear. The 18V zener diode insures against gatesource breakdown (VGSMAX = 20V) and the diode clamps the VSW pin to the VIN potential. Mention of these considerations appears in Appendix C. The transformer’s rectified and filtered secondary produces the 5V output. This output is galvanically isolated from the circuit’s input. To preserve this desired feature, the feedback path must also be galvanically isolated. A1, the optoisolator and their associated components serve this function. A1, powered by the 5V output, compares a resistively-sampled portion of the output with the LT1004 1.2V reference. Operating at a gain of 200, it drives the optoisolator’s LED. The optoisolator’s output transistor biases the LT1071’s VC pin, closing a regulation loop. The feedback amplifier inside the LT1071 is essentially bypassed by the A1 optoisolator combination and is not used. Normally, the optoisolator’s drifty transmission characteristics over time and temperature would result in unstable feedback. 128

Here, A1’s gain is placed ahead of the optoisolator. This attenuates these uncertainties, providing a stable loop. This approach is not too different from inside-the-loop booster transistors and buffers used with op amps. Both schemes rely on the op amp’s gain to eliminate uncertainties and drifts. Returning the optoisolator to VREF instead of ground forces the op amp to bias well above ground, minimizing saturation effects during output transients. Frequency compensation is somewhat more involved in this circuit than the previous examples. A1 is rolled off by the 0.1mF unit. This keeps gain low at high frequency, preventing amplified ripple and noise from being fed back to the LT1071. Local compensation at the LT1071 VC pin stabilizes the loop. The 100W resistor at the 5V output, a deliberate sink path, allows loop stability at light or no load. Appendix B discusses frequency compensation. Additional transformer secondary windings could be added if desired. The input zener clips transient voltages. Circuit waveforms appear in Figure 6.7. Trace A is Q5’s drain voltage and Trace B the drain current. Trace A shows that the MOSFET sees about 100V due to flyback effects, but this is well within its rating. The ringing on turn-off is normal and is similar to the waveform observed in Figure 6.4’s circuit. Trace B shows that the current flow

Switching regulators for poets

[(Figure_7)TD$IG]

CHAPTER 6

BEFORE PROCEEDING ANY FURTHER, THE READER IS WARNED THAT CAUTION MUST BE USED IN THE CONSTRUCTION, TESTING AND USE OF THIS CIRCUIT. HIGH VOLTAGE, AC LINECONNECTED POTENTIALS ARE PRESENT IN THIS CIRCUIT. EXTREME CAUTION MUST BE USED IN WORKING WITH AND MAKING CONNECTIONS TO THIS CIRCUIT. REPEAT: THIS CIRCUIT CONTAINS DANGEROUS, AC LINE-CONNECTED HIGH VOLTAGE POTENTIALS. USE CAUTION. Figure 6.7 * Fully-Isolated Regulator’s Waveforms

[(Figure_8)TD$IG]

Figure 6.8 * Fully-Isolated Regulator’s Transient Response for a 1A Change on a 2.5A Load

is fast, clean and controlled. Figure 6.8 shows transient response for a 1A step on a 2.5A output. When Trace A goes high the step occurs. Trace B shows that output sag is corrected in about 8ms. When Trace A returns low the 1A load is removed and recovery is similar to the positive step. Broadband output noise, about 75mVP-P, may be reduced with the optional filter shown.

100W off-line switching regulator One of the most desirable switching regulator circuits is also one of the most difficult to design. Figure 6.9’s circuit has many similarities to the previous design but is powered directly from the 115V AC line. This off-line operation is desirable because it eliminates large, heavy and inefficient 60Hz magnetics and filter capacitors. The circuit provides an isolated 5V, 20A output as well as isolated 12V, 1A outputs. Additional features include operation over a 90V AC to 140V AC input range, AC line surge suppression, soft-starting and loop stability under all conditions. Efficiency exceeds 75%.

AC line power is rectified and filtered by the diode bridge–470mF combination. The MOV device provides surge suppression and the thermistor limits turn-on in-rush current. Start-up and soft-start circuitry is similar to Figure 6.6’s circuit, with some changes necessitated by the higher input voltage. Erratic operation at extremely low AC line voltages (70V AC) is prevented by the 220k-1.24k divider. At very low AC line inputs, this divider forces the LT1071 feedback pin to a low state, shutting down the circuit. The high input voltage, typically 160V DC, means that the LT1071’s internal current limit is set too high to protect the regulator if the circuit’s output is shorted. Q6 and its associated components provide about 2A limiting. The LT1071’s GND pin current flows through the 0.3W resistor, turning on Q6 if current is too high. The 22k-50pF RC filters noise, preventing erratic Q6 operation. Q5, a power MOSFET, is cascoded with the LT1071 for high voltage switching. Circuit topology is similar to Figure 6.6, with Q5’s voltage breakdown increased to 500V. Additionally, the 50W resistor combines with the gate capacitance to slightly slow Q5’s transitions, reducing high frequency harmonics. This measure eases layout considerations. The transformer’s damper network borrows from Figure 6.6, with values reestablished for this circuit. The A1-optocoupler-enforced feedback loop preserves the transformer’s galvanic isolation, allowing the regulator output to be ground referenced. The feedback loop is also similar to Figure 6.6. Compensation values at A1 and the LT1071 have changed, reflecting this circuit’s different gain-phase characteristics.

ALL WAVEFORM PHOTOGRAPHS WERE TAKEN WITH AN ISOLATION TRANSFORMER CONNECTED BETWEEN THE CIRCUIT’S 90V AC-140V AC INPUT AND THE AC LINE. USERS AND CONSTRUCTORS OF THIS CIRCUIT MUST OBSERVE THIS PRECAUTION WHEN CONNECTING TEST EQUIPMENT TO THE CIRCUIT TO AVOID ELECTRIC SHOCK. REPEAT: AN ISOLATION TRANSFORMER MUST BE CONNECTED BETWEEN FIGURE 6.9’S CIRCUIT AND THE AC LINE IF ANY TEST EQUIPMENT IS TO BE CONNECTED. 129

130

DANGER! LETHAL POTENTIALS PRESENT—SEE TEXT

Figure 6.9 * 100W Off-Line Switching Regulator

[(Figure_9)TD$IG]

SECTION TWO Switching Regulator Design

Switching regulators for poets

Figure 6.10 shows circuit waveforms at 15A output. Trace A, Q5’s drain, shows the flyback pulse being damped below 300V (for a discussion of the procedures used to design the damper network and other design techniques in this circuit, see Appendix D, ‘‘Evolution of a Switching Regulator Design’’). Trace B, the LT1071’s VSW pin, stays well within its voltage rating, despite Q5’s high voltage switching. Trace C, Q5’s drain current, shows that transformer current is well controlled with no saturation effects. Trace D, damper network current, is active when Q5 goes off. Figure 6.11 is a time and amplitude expansion of Q5’s drain (Trace A) and transformer primary current (Trace B). Switching is clean, with residual noise due to nonideal transformer behavior. The damper network clamps the flyback pulse well below Q5’s 500V rating and the transformer rings off after the flyback interval. The noise on the current pulse, due to resonances in the transformer, has no significant effect on circuit operation. Figure 6.12 shows output noise with the optional LC filter in use. Without the filter, noise is about 150mV. Superimposed, residual 120Hz modulation accounts for trace thickening at the peaks and could be eliminated by increasing the 470mF value. Figure 6.13 shows transient response performance. When Trace A goes high, a 5A transient is added to a 10A steady-state load. Recovery amplitude is low and clean with a first order response. When Trace A goes low, the transient load is removed with similar results. Figure 6.14 shows response for shifts in the line. When Trace A is high, the AC line is at 140V AC. Line voltage drops to 90V AC with Trace A low. Trace B, the regulator’s AC-coupled output, shows a clean recovery with small amplitude error. The ripples in the waveform, 120Hz input residue, could be reduced by increasing the 470mF capacitor. Figure 6.15 shows the 5V output at start-up into a 20A load. Response is slightly underdamped and can be modified by adjusting the frequency compensation. The

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Figure 6.11 * Detail of Off-Line Switcher’s Transformer Primary Voltage and Current Waveforms

DANGER! TAKE THIS MEASUREMENT ONLY WITH AN ISOLATION TRANSFORMER IN USE—SEE TEXT

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Figure 6.12 * Figure 6.9’s Output Ripple at 10A Output with the Optional LC Filter Added—Without the Filter, Ripple Increases to About 150mVP-P

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Figure 6.13 * Figure 6.9’s Circuit Responding to a 5A Change on a 10A Output

Figure 6.10 * Off-Line Switcher’s Waveforms

DANGER! TAKE THIS MEASUREMENT ONLY WITH AN ISOLATION TRANSFORMER IN USE—SEE TEXT

compensation shown in Figure 6.9 is a good compromise between transient response and turn-on characteristics. The delay on turn-on and the controlled rise time are due to the slow-start circuitry. Figure 6.16 plots regulator efficiency. As would be expected, efficiency is best at high currents, where static losses are a small percentage of output power. 131

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Figure 6.14 * Figure 6.9 Responds to a 90V AC—140V AC Line Change—Loading is 10A—120Hz Residue in Output Could be Reduced by Increasing the 470mF Input Filter

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Figure 6.17 * A Simple Motor-Tachometer Servo Loop

Figure 6.15 * Start-Up for Figure 6.9 at 20A Loading—The 10mF Capacitor at the LT1070’s VC Pin Produces the SlowStart Characteristic. If the Small Overshoot is Objectionable, Modified Frequency Compensation Can Eliminate it at Some Cost to Transient Response

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efficiency. Although this circuit controls a motor, it shares many considerations common to voltage regulators. When power is applied, the tachometer output is zero and the feedback pin (FB) is also at zero. This causes the LT1070 to begin pulsing its VSW pin at maximum duty cycle. The motor turns, forcing tachometer output. When the FB pin arrives at the LT1070’s internal voltage reference value (1.24V), the loop stabilizes. Speed is adjustable with the 25k potentiometer in the feedback string. The MUR120 damps the motor’s flyback spike. The characteristics of the motor specified permit no current limiting in series with the diode. Other motors might require this and damper network optimization should be done for any specific unit. Similarly, frequency compensation values will vary with different motor types. The diode at the tachometer output prevents transient reverse voltages due to tachometer commutator switching.

Switch-controlled peltier 0 C reference

Figure 6.16 * Figure 6.9’s Efficiency vs Operating Point

Switch-controlled motor speed controller Voltage regulators are not the only switching power circuits. Figure 6.17 shows a motor speed regulator. The LT1070 provides simplicity and switch-mode control 132

Figure 6.18 is another switch-mode control circuit. Here, the LT1070 controls power to a Peltier cooler, providing a 0 C temperature reference for transducer calibration. A platinum RTD is thermally mated to the Peltier cooler. The RTD combines with a bridge network to give a differential output. A1 provides maximum bridge drive without introducing significant heating in the RTD. The LTC1043 switched capacitor network converts this output to a single-ended signal at A2. A2, operating at a gain of 400, biases the LT1070’s VC pin. This closes a control loop around the Peltier cooler, forcing its temperature low enough to balance the bridge. The 0 C trim adjusts the servo point to precisely 0 C. A standard RTD should monitor Peltier temperature when making this trim. Alternately, the sensor specified should be supplied

Switching regulators for poets

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Figure 6.18 * A Peltier-Cooled Switched-Mode 0 C Reference

with a certified 0 C resistance. With the RTD and Peltier cooler tightly mated, stability is excellent. Figure 6.19, a plot of stability over hours in a 25 C  3 C ambient, shows a 0.15 C baseline.

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Acknowledgments The author acknowledges Carl Nelson’s abundance of commentary, some of which was useful, during preparation of this work. Bob Dobkin’s thoughts and patience are also appreciated. Ron Young made significant contributions towards Figure 6.6’s circuit. Bill McColey and other members of the Engineering staff of Pulse Engineering, Inc.3, supplied invaluable insight and assistance on magnetics issues. As usual, our customers’ requests and requirements provided the most valuable source of guidance, and they are due a special thanks.

Appendix A Physiology of the LT1070 The LT1070 is a current-mode switcher. This means that switch duty cycle is directly controlled by switch Figure 6.19 * Stability of Figure 6.18’s Circuit Over Many Hours with a 25 C  3 C Ambient

Note 3: P.O. Box 12235, San Diego, CA 92112 (619/268-2400).

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Figure A1 * LT1070 Internal Details

current rather than by output voltage. Referring to Figure A1, the switch is turned on at the start of each oscillator cycle. It is turned off when switch current reaches a predetermined level. Control of output voltage is obtained by using the output of a voltagesensing error amplifier to set current trip level. This technique has several advantages. First, it has immediate response to input voltage variations, unlike ordinary switchers which have notoriously poor line transient response. Second, it reduces the 90 phase shift at mid-frequencies in the energy storage inductor. This greatly simplifies closed loop frequency compensation under widely varying input voltage or output load conditions. Finally, it allows simple pulseby-pulse current limiting to provide maximum switch protection under output overload or short conditions. A low dropout internal regulator provides a 2.3V supply for all internal circuitry on the LT1070. This low dropout design allows input voltage to vary from 3V to 6V with virtually no change in device performance. A 40kHz oscillator is the basic clock for all internal timing. It turns on the output switch via the logic and driver circuitry. Special adaptive antisat circuitry detects onset of saturation in the power switch and adjusts driver current instantaneously to limit switch saturation. This minimizes driver dissipation and provides very rapid turn-off of the switch. 134

A 1.2V bandgap reference biases the positive input of the error amplifier. The negative input is brought out for output voltage sensing. This feedback pin has a second function; when pulled low with an external resistor, it programs the LT1070 to disconnect the main error amplifier output and connects the output of the flyback amplifier to the comparator input. The LT1070 will then regulate the value of the flyback pulse with respect to the supply voltage. This flyback pulse is directly proportional to output voltage in the traditional transformer-coupled flyback topology regulator. By regulating the amplitude of the flyback pulse the output voltage can be regulated with no direct connection between input and output. The output is fully floating up to the breakdown voltage of the transformer windings. Multiple floating outputs are easily obtained with additional windings. A special delay network inside the LT1070 ignores the leakage inductance spike at the leading edge of the flyback pulse to improve output regulation. The error signal developed at the comparator input is brought out externally. This pin (VC) has four different functions. It is used for frequency compensation, current limit adjustment, soft-starting and total regulator shutdown. During normal regulator operation this pin sits at a voltage between 0.9V (low output current) and 2.0V (high output current). The error amplifiers are current output (gm) types, so this voltage can be externally clamped for adjusting current limit. Likewise, a capacitor-coupled external clamp will provide soft-start. Switch duty cycle goes to zero if the VC pin is pulled to ground through a diode, placing the LT1070 in an idle mode. Pulling the VC pin below 0.15V causes total regulator shutdown with only 50mA supply current for shutdown circuitry biasing. For more details, see Linear Technology Application Note appropriate chapter-5-19, pages 4-8.

Appendix B Frequency compensation Although the architecture of the LT1070 is simple enough to lend itself to a mathematical approach to frequency compensation, the added complications of input and/or output filters, unknown capacitor ESR, and gross operating point changes with input voltage and load current variations all suggest a more practical empirical method. Many hours spent on breadboards have shown that the simplest way to optimize the frequency compensation of the LT1070 is to use transient response techniques and an R/C box to quickly iterate toward the final compensation network.

Switching regulators for poets

There are many ways to inject a transient signal into a switching regulator, but the suggested method is to use an AC-coupled output load variation. This technique avoids problems of injection point loading and is general to all switching topologies. The only variation required may be an amplitude adjustment to maintain small signal conditions with adequate signal strength. Figure B1 shows the setup. A function of generator with 50W output impedance is coupled through a 50W/1000mF series RC network to the regulator output. Generator frequency is noncritical. A good starting point is 50Hz. Lower frequencies may cause a blinking scope display which is annoying to work with. Higher frequencies may not allow sufficient settling time for the output transient. Amplitude of the generator output is typically set at 5VP-P to generate a 100mAP-P load variation. For lightly loaded output (IOUT 5:1 noise reduction as switch transition time slows from 100ns (20a) to 1ms (20d). Figure 8.20d’s displayed noise is actually lower, as the probing-induced error caused by monitoring the switch corrupts the measurement.9 Figure 8.21 graphically summarizes Figure 8.20’s information. Significant noise reduction coincides with descending transition slew time until about 1.3ms. Little additional noise benefit occurs beyond this point. Figure 8.22 shows efficiency fall-off with slew time. There is a 6% penalty between 100ns and 1.3ms, the same region where noise performance improves by a factor of 5 (per previous figure). There is an additional 6% penalty beyond 1.3ms, although no significant noise reduction occurs (again, per Figure 8.21). As such, operation in this region is undesirable. Figure 8.23 clearly shows the inflection point in the efficiency versus noise trade-off.10

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Figure 8.16 * Ripple at Figure 8.5’s First LC Output Has No Wideband Spikes

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Negative output regulator The LT1533 has a separate feedback input that directly accepts negative inputs.11 This permits negative outputs without the usual discrete level shifting stage. Figure 8.24’s 5V to
12V converter is similar to Figure 8.5’s circuit, except that the negative output is fed back to the negative feedback input. The feedback scale factor change is necessitated by the higher effective reference voltage. In all other respects, the circuit (and its performance) is similar to Figure 8.5.

Figure 8.17 * Time Expansion of Previous Figure. No High Frequency Content Is Visible

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Floating output regulator Figure 8.25’s isolation stage permits a fully floating, regulated output. The LT1431 shunt regulator compares a portion of the output to its internal reference and drives the optoisolator with the error signal. The optoisolator’s collector output biases the LT1431’s VC pin, closing a feedback loop to regulate circuit output. The 0.22mF capacitor stabilizes the loop and the 240kW resistor biases the optoisolator into a favorable operating region. This circuit’s operation and characteristics are similar to Figure 8.5 with the added benefit of the isolated output.

Floating bipolar output converter

Figure 8.18 * Low Frequency Noise in a 10Hz to 10kHz Bandpass

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Grounding the LT1533’s ‘‘DUTY’’ pin and biasing FB forces the device into its 50% duty cycle mode. Figure 8.26’s output is full wave rectified with respect to T1’s secondary center tap, producing bipolar outputs. The forced 50% duty cycle combined with no feedback means

Note 9: See Appendix C, ‘‘Probing and connection techniques for low level, wideband signal integrity’’ for guidance. Note 10: The noise and efficiency characteristics appearing in Figures 8.20 to 8.23 were generated at the bench in about ten minutes. All you CAD modeling types out there might want to think about that. Note 11: See Figure 8.3’s block diagram.

Figure 8.19 * Figure 8.5’s Small Sinusoidal Input Current Variations Contain No High Frequency Content and Are Easily Absorbed by Input Supply

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Figure 8.20 * Output Noise (Trace B) vs Different Switch Slew Rates (Trace A). Highest Slew Rate (a) Causes Largest Noise. Retarding Slew Rate (b and c) Decreases Noise Until Lowest Noise Performance Is Achieved (d)

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Figure 8.21 * Figure 8.5’s Noise vs Slew Time at 40kHz Switching Frequency. Noise Reduction Beyond 1.3ms Is Minimal

Figure 8.22 * Figure 8.5’s Efficiency Drops 6% as Slew Time Extends to 1.3ms. Operation Beyond This Point Gains Little Noise Performance (See Previous Curve) with 6% Efficiency Penalty

Figure 8.23 * Efficiency vs Noise for Figure 8.5. Data Shows Significant Efficiency Fall-Off for Noise Below 80mV

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A monolithic switching regulator with 100mV output noise

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Figure 8.24 * A Negative Output Version of Figure 8.5. LT1533’s Negative Feedback Input Requires Minimal Configuration Changes. Noise Performance Is Identical to Positive Output Version

the outputs are unregulated, proportioning to T1’s drive voltage. An output inductor is usually not required, as in Figure 8.5’s ‘‘forward’’ converter. At the very highest output currents, some inductance may be necessary to limit inrush current. If this is not done, the circuit may not start. Typically, linear regulators provide regulation.12 Figure 8.26’s waveforms appear in Figure 8.27. Collector voltage (Traces A and C) and current (Traces B and D) are shown, along with the indicated output noise (Trace E). In this case linear regulators and an output filter are in use. In Figure 8.28 all probes except the coaxial output connection are removed. This eliminates probing induced parasitics,13 allowing a higher fidelity signal presentation. Here, the switching residuals are barely detectable in the noise floor. Removing the optional output filter (Figure 8.29) allows linear regulator contributed noise and switching spikes to rise, but noise is still below 300mVP-P. As in Figure 8.5’s case, spectrum analyzer measurements are instrument limited. Figure 8.30 shows the analyzer’s noise floor in a 500MHz sweep when monitoring the unpowered Figure 8.26’s breadboard. In Figure 8.31, the breadboard is powered, but analyzer output is noise limited and essentially indistinguishable from the unpowered case. Similarly, Figure 8.32’s 1MHz wide ‘‘power-on’’ plot is identical to Figure 8.33’s noise floor limited ‘‘poweroff’’ sweep. Note that linear postregulation is in use and the 40kHz fundamental components are not detectable. Figure 8.5’s circuit did not have linear postregulation and 40kHz fundamental residue appeared in Figure 8.15b.

Note 12: See Appendix E, ‘‘Selection criteria for linear regulators.’’ Note 13: See Appendix C, ‘‘Probing and connection techniques for low level, wideband signal integrity,’’ for relevant discussion.

Battery-powered circuits The basic configurations may be battery-powered for use in portable apparatus. Figure 8.34, similar to Figure 8.5, runs from 2.7VMIN (e.g., three NiCd batteries), producing 12V output. This design induces no noise-based error when powering a fast 16-bit A/D converter, something almost no DC/DC converter can do. Appendix K contributes compelling testimony to this somewhat boastful claim. Figure 8.35 also operates from three NiCd cells, producing a 9V output. This design achieves 100mV output noise, qualifying it as the electronic equivalent of a 9V battery.

Performance augmentation In some cases it may be desirable to augment LT1533 performance characteristics. Usually, this involves additional circuitry, and may necessitate trading off performance in one area to gain the desired benefit.

Low quiescent current regulator The LT1533 has a quiescent current of about 6mA. Figure 8.36’s circuit reduces this figure to 100mA by running an on-off control loop around the device. The control loop replaces the normal error amplifier, achieving regulation by switching the IC in and out of shutdown in accordance with loop demands. Comparator C1 compares a scaled version of the output with its internal reference and biases the regulators shutdown pin. Loop hysteresis is obtained by utilizing the phase shift (e.g., time delay) of the output LC components. In a 177

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Figure 8.25 * An Optoisolated Output Variant of Figure 8.5. Loop Closure to VC Pin Bypasses LT1533 Error Amplifier, Enhancing Loop Stability. Noise Performance is Maintained

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Figure 8.26 * A Bipolar, Floating Output Converter. Grounding ‘‘DUTY’’ Pin and Biasing FB Puts Regulator into 50% Duty Cycle Mode. Floating, Unregulated Outputs Proportion to T1’s Center Tap Voltage. Linear Regulators Are Optional

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A monolithic switching regulator with 100mV output noise

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Figure 8.27 * Waveforms for the Floating Output Converter at 100mA Loading. Linear Postregulator and Optional LC Filter Are Employed. Slew-Controlled Collector Voltage (Traces A and C) and Current (Traces B and D) Produce Output (Trace E) with Under 100mV Noise

Figure 8.29 * Removing Optional LC Filter Causes Linear Regulator-Contributed Noise and Switching Spikes to Rise. Peak-to-Peak Noise Is Still > Lf > > >  > m  Y <  i    D ð2Þ
I0 ¼ m  mc
V0 T > i¼1 > >
; m ¼ 2; 3 . . .     > m1 > Y i Lf  > >   D þ 1 > : m  m i¼1 The output ripple voltage is estimated to be:
V0;PP