Analog circuit design : scalable analog circuit design, high speed D/A converters, RF power amplifiers 9780306479502, 0306479508, 9780792376217, 0792376218

Table of contents :
Bevat: Scalable high-speed analog circuit design /M. Vertregt and P. Scholtens --
Scalable high resolution mixed mode circuit design /R.J. Brewer --
Scalable "high voltages" integrated circuit design for XDSL type of applications /D. Rossi --
Scalability of wire-line analog front-ends /K. Bult --
Reusable IP analog circuit design /J. Hauptmann, A. Wiesbauer and H. Weinberger.

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ANALOG CIRCUIT DESIGN

Analog Circuit Design Scalable Analog Circuit Design, High Speed D/A Converters, RF Power Amplifiers Edited by

Johan H. Huijsing Delft University of Technology

Michiel Steyaert KU Leuven and

Arthur van Roermund Eindhoven University of Technology

KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

eBook ISBN: Print ISBN:

0-306-47950-8 0-7923-7621-8

©2003 Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print ©2002 Kluwer Academic Publishers Dordrecht All rights reserved No part of this eBook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Kluwer Online at: and Kluwer's eBookstore at:

http://kluweronline.com http://ebooks.kluweronline.com

Table of Contents Preface

vii

Part I: Scalable Analog Circuit Design Introduction

1

Scalable High-Speed Analog Circuit Design M. Vertregt and P. Scholtens

3

Scalable High Resolution Mixed Mode Circuit Design R.J. Brewer

23

Scalable “High Voltages” Integrated Circuit Design for XDSL Type of Applications D. Rossi

43

Scalability of Wire-Line Analog Front-Ends K. Bult

57

Reusable IP Analog Circuit Design J. Hauptmann, A. Wiesbauer and H. Weinberger

71

Process Migration Tools for Analog and Digital Circuits K. Francken and G. Gielen

89

Part II: High-Speed D/A Converters Introduction

113

Introduction to High-Speed Digital-to-Analog Converter Design R. van de Plassche

115

Design Considerations for a Retargetable 12b 200MHz CMOS CurrentSteering DAC J. Vital, A. Marques, P. Azevedo and J. Franca

151

High-Speed CMOS DA Converters for Upstream Cable Applications R. Roovers

171

Solving Static and Dynamic Performance Limitations for High Speed D/A Converters A. Van den Bosch, M. Steyaert and W. Sansen

189

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High Speed Digital-Analog Converters – The Dynamic Linearity Challenge A.R. Bugeja

211

A 400-MHz, 10-bit Charge Domain CMOS D/A Converter for LowSpurious Frequency Synthesis K. Khanoyan, F. Behbahani and A.A. Abidi

233

Part III - RF Power Amplifies Introduction

247

Design Considerations for RF Power Amplifiers demonstrated through a GSM/EDGE Power Amplifier Module P. Baltus and A. van Bezooijen

249

Class-E High-Efficiency RF/Microwave Power Amplifiers: Principles of Operation, Design Procedures, and Experimental Verification N.O. Sokal

269

Linear Transmitter Architectures L. Sundström

303

GaAs Microwave SSPA’s: Design and characteristics A.P. de Hek and F.E. van Vliet

325

Monolithic Transformer-Coupled RF Power Amplifiers in SI-Bipolar W. Simbürger, D. Kehrer, A. Heinz, H.D. Wohlmuth, M. Rest, K. Aufinger and A.L. Scholtz

347

Low Voltage PA Design in Standard CMOS K. Mertens and M. Steyaert

373

Preface

This book contains the revised contributions of the 18 tutorial speakers at the tenth AACD 2001 in Noordwijk, the Netherlands, April 24-26. The conference was organized by Marcel Pelgrom, Philips Research Eindhoven, and Ed van Tuijl, Philips Research Eindhoven and Twente University, Enschede, the Netherlands. The program committee consisted of: Johan Huijsing, Delft University of Technology Arthur van Roermund, Eindhoven University of Technology Michiel Steyaert, Catholic University of Leuven The program was concentrated around three main topics in analog circuit design. Each of these topics has been covered by six papers. The three main topics are: Scalable Analog Circuit Design High-Speed D/A Converters RF Power Amplifiers Other topics covered before in this series: 2000 High-Speed Analog-to-Digital Converters Mixed Signal Design PLL’s and Synthesizers 1999 XDSL and other Communication Systems RF MOST Models Integrated Filters and Oscillators 1998 1-Volt- Electronics Mixed-Mode Systems Low-Noise and RF Power Amplifiers for Telecommunication vii

viii

1997 RF A-D Converters Sensor and Actuator Interfaces Low-Noise Oscillators, PLL’s and Synthesizers 1996 RF CMOS Circuit Design Bandpass Sigma Delta and other Converters Translinear Circuits 1995 Low-Noise, Low-Power, Low-Voltage Mixed Mode with CAD Trials Voltage, Current and Time References 1994 Low-Power Low Voltage Integrated Filters Smart power 1993 Mixed-Mode A/D Design Sensor Interfaces Communications Circuits 1992 Op Amps ADC’s Analog CAD We hope to serve the analog design community with these series of books and plan to continue this series in the future. Johan H. Huijsing

Part I: Scalable Analog Circuit Design Industry has a need to transfer circuit designs from older integratedcircuit processes into newer processes, which have lower device dimensions. This may be relatively simple for digital circuits. But, for analog circuits this is not straight forward at all because the requirements for noise, offset and dynamic range may resist sealing to smaller dimensions. Therefore, redesigns of analog circuits take a lot of effort. The purpose of these first six papers in this book is to help designers with designs, that can be transferred to future processes with smaller dimensions, or to guide in the process of transferring already existing circuit designs. In the first four papers the design for scalability is treated in four special areas: A first paper by Maarten Vertregt of Philips Research, Eindhoven, the Netherlands, presents basic issues of scalable high-speed analog circuit design. A second paper by Bob Brewer, Analog Devices, Newbury, UK, evaluates scalable high-resolution mixed-mode circuit design. A third paper by Dominico Rossi, ST Microelectronics, Italy, discusses solutions for scalable “high-voltage” integrated circuit design for XDSL. The fourth paper by Klaas Bult, Broadcom, Bunnik, the Netherlands, describes scalability issues of wire-line front-ends. The last two papers are of general help on scaling: The fifth paper by Jörg Hauptmann, Infineon Technologies, Villach, Austria, discusses aspects of reusable IP analog circuit design. 1

2

The sixth paper by George Gielen, Catholic University of Leuven, Belgium, helps designers on “porting” CAD analog circuit design. Johan H. Huijsing

Scalable high-speed analog circuit design Maarten Vertregt and Peter Scholtens

Philips Research Eindhoven, The Netherlands [email protected] Abstract The impact of scaling on the analog performance of MOS circuits was studied. The solution space for analog scaling was explored between two dimensions: a “standard digital scaling” axis and an “increased bandwidth and dynamicrange” axis. Circuit simulation was applied to explore trends in noise and linearity performance under analog operating conditions at device level and for a basic circuit block. It appears that a single scaling rule is not applicable in the analog circuit domain.

1 Introduction The two-year cycle of successive technology generations [1] has enabled an ever increasing amount of system integration per chip. For a long time, this increase in integration density was satisfied by adding extra digital functions and memory. Nowadays, interfaces to the analog world (both base-band and RF) are also packed onto these systems-on-chip. In addition to the dominant “constant field” CMOS scaling trend, and the associated continuous decrease of the power supply voltage, there are other major hurdles for system integration. Increasing demands for extended dynamic range and signal bandwidth of modern integrated systems must also be met (Figure 1, dynamic range is plotted in the resolution in bits of an A/D converter). 3 J. H. Huijsing et al., (eds.), Analog Circuit Design, 3-21. © 2002 Kluwer Academic Publishers. Printed in the Netherlands.

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It is not necessarily true that the most advanced technology generation will have the highest value for the product of the dynamic range and signal bandwidth (scaling towards the upper right-hand corner of the graph in Figure 1) [2]. Additional devices (highly linear capacitors, gate-oxide for MOS transistors) can facilitate systemon-chip integration, since those “high quality” passives enable a performance increase, and “previous generation” analog blocks can easily be re-used (voltage levels are maintained). The combination of doing a trend analysis and having additional devices available creates two problems. Firstly (when the total function remains in a previous technology generation, because of the time needed to create and characterize high quality passives), the digital part of the system-to-be-integrated suffers from a lack of function-density and an elevated supply voltage. This has a quadratic effect on the dynamic power dissipation through Secondly (with combined use of state-of-the-art MOS transistors for digital functions, and previous-generation MOS transistors for analog functions), the potential of the new technology is not exploited for these analog functions. The approach of adding devices is therefore useful for porting functions, but is not interesting when identifying scaling issues.

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2 Scaling goals Scaling of digital functions is directly coupled to feature size reduction. Per function, this yields a combination of continuous area reduction, speed increase and dynamic power reduction (see [3] for an example). Static power dissipation becomes a major limitation with the integration of more functions at an increased density. Speed and power improvement for digital functions is then done concurrently by selecting the optimum On/Off ratio of the MOS transistor for a certain application domain. The scaling space basically narrows down to two dimensions: on/off ratio vs feature size [4]. For analog functions, the goals of scaling are diverse. The focus can be on area efficiency, with the continued availability of a function at a fixed power dissipation, bandwidth and dynamic range. Alternately, the focus can be on the exploration of the ultimate bandwidth capability, without limiting the power or area. It could also be on pushing the combined limits of dynamic range, bandwidth and power. The preferred scaling scenario heavily depends on the goal, and we must sacrifice the performance in directions that have a lower priority to obtain a feasible solution. The basic quadratic MOS current/voltage relationships (see [5] for example) are used to choose the relative change of the operating points across technology generations, as well as to approximate (for a limited bias range only) the analog scaling rules of Table 1:

To the first order, the quasi DC distortion is dependent on the variation across the signal amplitude through modulation of the first order derivatives

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3 Scaling scenarios We have applied several methods to explore analog scalability. The focus varies from general “power and SNR” considerations [6], to concurrent “power, SNR, and linearity” optimization for a fixed building block [7]. The focus also ranges from practical device artifacts, through compact model simulation [8, 9], to trend analysis at the functional block level [10, 11]. Here, the solution space for scaling (expressed in the well-known linear scaling factor s=0.7 from generation-to-generation) is explored using three different cases: Relaxed Dynamic Range (Digital scaling I) Standard digital scaling as in [3] for example. The focus is now on area and power reduction-per-function. The performance metrics being sacrificed are linearity [9], and the signal-to-noise ratio (a power ratio, assumed to be dominated by thermal noise in the denominator). Neither linearity nor SNR degradation have to be a limiting factor when scaling a circuit, however, the fact that the will degrade by a factor per generation under this scaling regime requires attention for wide-band circuits. The linearity degradation is consistent with the third harmonic intercept voltage findings in [9]. In case of a dominant third harmonic, the expected signal-to-distortion ratio deteriorates by due to a combination of loss of intrinsic MOS gain and insufficiently scaled with respect to the supply scaling (s). Relaxed area and power (Analog Scaling II) The major consideration is that analog circuits only occupy a minor portion of a system-on-chip. Area reduction is therefore not ranked as a top priority. Instead, with the application demands in mind, the focus during scaling is on the concurrent performance increase in terms of bandwidth and dynamic range increase at a fixed frequency. Maintaining the linearity part of the dynamic range requires the signal amplitude at least to scale with the supply voltage. The effect of the noise part of the dynamic range is treated

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as follows, where signal level:

is the bandwidth of the circuit and

is the rms

Thus, for constant should remain constant, and the active “ Area” is now the metric to be sacrificed:

Applying the part of equation (4), we learn that a constant SNR requires a cubic increase of the transconductance, i.e. a cubic decrease of the impedance level, to compensate for the lower signal amplitude and the higher bandwidth. To reach this goal (bound by the feature-size scaling of L), equation (2) subsequently defines the to scale with and the W with From equation (3), it follows that the foremost sacrificed item is now gds, with For the signal carrying parts of the circuit, the overall decrease in the impedance level on the circuit nodes compensates for this sacrifice. Constant area and constant power (Analog Scaling III) The third scenario is a mixture of the previous two. A minor loss of SNR is accepted to avoid an increased area and power dissipation, whilst the linearity performance is maintained at the level of the “Analog Scaling II” scenario. The results of these three scaling strategies were evaluated using circuit simulation (on both the device and the basic circuit block level). The use of circuit simulation safeguards the inclusion of higher-order impairments on performance (such as moderate inversion), and gives insight into the performance latitude (in signal amplitude, distortion and noise) of the scaled circuit. The scaling rules applied within these three strategies are summarized in Table 1:

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4 Results of scaling 4.1 Single device scaling Compact model simulation of single MOS devices [9] was applied for various technology generations. This identifies the impact of higherorder impairments on these approximate relationships and checks for the validity of the selected operating range.

9

Figures 2 and 3 give an example how this validity check on the usable basic square-law model operating range is done. This is shown for an NMOS device with in the generation. For the and the trans-conductance as function of gate-drive (Figure 2) and for the and the output conductance as function of source-drain voltage (Figure 3).

We use the gate overdrive for all device biasing. By this choice we circumvent that variations in threshold voltage (for different device geometries, or for successive technology generations) will influence the actual analog operating point. At first glance we see for this example in Figure 2 a more or less linear relationship of for the limited range (and for the obvious condition of sustained saturation At the edges of this range, part of the distortion caused by this deviation can be overcome by circuit design techniques such as a differential circuit topology and/or feedback. We will have a better look on the trans-conductance linearity behavior for successive technology generations later on, and first inspect the output conductance for an NMOS example in technology.

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For the the variation for a 300mV signal swing is approximately an order of magnitude, at relatively low . Multiple devices have to be stacked in the 1.8V supply for circuit reasons. A higher value for can therefore not be accommodated. Reliability reasons are not the critical issue. This lack of headroom explains why the signal level and the nominal gate overdrive in subsequent technology generations have to scale down, at least proportionally with the power supply. As shown in Figures 2 and 3, the trans-conductance and output conductance derivatives give a better view on relevant analog device properties (such as linearity) than the current characteristics. We now rearrange these characteristics in a form allowing easy comparisons across technology generations. We do this by looking at the relative variation of these conductance curves with respect to the drain-source current. Figure 4 shows the trend for an NMOS (normalized to q/kT units) against for four subsequent technology generations. According to equation (2), we expected proportionality of with 1/s through . Also this curve is plotted in Figure 4. Higher order impairments present in the simulation model show up as a loss of improvement for (with an increasing deviation for smaller Figure 5 shows the consequence of this effect when an NMOS device is scaled through successive technology generations. is scaled with s, according to the scaling rule choices of Table 1 (from 300mV at the generation to l00mV at the generation).

11

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Higher order impairments, present in the simulation model, show up as a deterioration of the expected scaling across technology generations, with a multiplication factor of approximately (for

We performed a similar exercise for the output conductance. Figure 6 shows the trend for the "early voltage" as a function of where is scaled with in the simulation. According to equation (3) we would expect proportionality of with through L.

We therefore verify this relationship in Figure 7 with a graph of vs minimum feature size of successive technology generations. Higher order impairments show up as a deterioration of scaling, with a multiplication factor of approximately

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To summarize these observations on conductance scaling, we found that the intrinsically “obtainable gain” of the MOS transistor is a factor per generation lower than expected from the square-law model. This affects all three scaling rule scenarios. We will now verify the consequences of this deviation on circuit block level. 4.2 Circuit block scaling A basic voltage follower was applied to explore the bandwidth and dynamic range consequences at circuit level (Figure 8). As a starting point, an implementation in with a signal amplitude of 0.3V, targeted for a signal-to-noise-and-distortion of approximately 50dB, was used. The three scenarios listed in Table 1 were subsequently applied, scaling backward to and forward to technology.

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Figures 9 to 11 show the results of the voltage-follower simulation exercise across four technology generations for the performance criteria bandwidth, signal-to-noise ratio (SNR), and signal-todistortion ratio (SDR). The circuit is current driven (with a diode generating the gate voltage of the tail current source), which means that we expect the deviations from the applied scaling rule primarily to show up in the linearity, and not in the or the (being representative for the circuit bandwidth). For this voltage-follower circuit, Figure 9 shows that the “digital I” scaling scenario gives the best bandwidth improvement across technology generations. The improvement factor 1.75x more or less equals the expected value from Table 1. The bandwidth improvement for the generation is slightly less than expected. This means that the parasitic capacitances outside the scaled MOS devices and the scaled external load are not scaling as well as before. Figure 10 shows that, as expected from Table 1, the “digital I” scaling scenario is worst for thermal noise in this wide-band circuit. The aim to keep SNR constant is clearly fulfilled by the “analog II” scenario. The “analog III” scaling scenario creates the expected, minor, degradation in SNR. Due to the combination of a relatively reduced bandwidth and a lower impedance level (due to an increased the generation consistently shows a slightly better SNR.

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16

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Striking in the signal-to-distortion plot of Figure 11 is the tremendous impairment on linearity that occurs throughout technology generations when “digital I” scaling is applied for this kind of wide-band circuit block. The drop in circuit linearity at higher frequencies is a consequence of this generation’s lower bandwidth. We do not get the low-frequency circuit linearity beyond 70dB in “reverse ” scaling from the initial circuit definition in We contribute this to undefined higher order impairments far beyond the initial circuit linearity. The severe degradation across two generations (from to is approximately 10dB/generation (with the generation positioned slightly eccentric). This is a combination of insufficient scaling of (by instead of and an additional degrading factor affecting both analog scaling scenarios as well (see below). Contrary to the original expectation for the “Analog II” and “Analog III” scaling scenarios, we see no systematic linearity improvement across technology generations (and some degradation for the DClinearity in the case). We attribute this lack of voltagefollower linearity improvement to the additional loss of a factor s per generation of the intrinsically “obtainable gain” of a voltage driven MOS transistor (shown by the device level simulations of Figures 4 and 5). The proper current, bandwidth, and conductance levels are maintained at the expense of an increased gate-drive and thus a degraded scaling. Within the context of the voltage follower circuit block the impairment therefore mainly shows up in the linearity performance.

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5 Discussion and functional block examples The application demands from Figure 1 have been confronted with the practical consequences of analog scaling. Concurrent analog building block improvements in area, and bandwidth and dynamic range cannot be created through feature size scaling alone. A drawback of using simulation as a forward-looking scaling tool is the lack of model card parameters with an “analog” quality. This fate is a major reason for the time shift in applied technology generation between state-of-the-art digital circuits and high dynamic range analog circuits. Circuit topology plays a major role in attacking high-dynamic range application problems with low-dynamic range circuitry. Examples are in sigma-delta conversion (where single bit quantization is capable of delivering high dynamic range), in spread spectrum techniques (where a very low or negative SNR is allowed without hampering proper communication), or by applying dynamic correction techniques to compensate for degraded device properties (as in wide-band nyquist A/D conversion). To highlight the last point; a 10bit A/D function was implemented using the technology generation in [12]. In a scaled technology, this A/D function occupies 1 at a 12 bit resolution, thanks to the “mixed-signal chopping and calibration” circuit topology technique [13]. This scaled realization results in a 4-fold increase in dynamic range, and twice the bandwidth Together with times more power consumption and a larger area this means a performance improvement in one generation.

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6 Conclusions We can therefore draw the following conclusions: Concurrent improvement of bandwidth and dynamic range by a feature-size scaling rule results in a power and area increase of signal-carrying devices in critical blocks. Porting fixed functions benefits most from previous generation device availability and/or a higher power supply voltage (maintaining the original operating points and signal levels). However, the scaled technology is not exploited and scaling trends cannot be identified. Down-scaling analog circuits by applying a feature-size scaling rule does not fulfill the application demand. Circuit topology improvement does. Therefore, new application domain demands are best served by employing a mixture of scaling rules and by optimal system level choices.

7 Acknowledgments We are grateful to Anne Johan Annema, Pierre Woerlee and Ronald van Langevelde for their constructive discussions and supporting material.

8 References [1] ITRS 2000, http://public.itrs.net/Files/2000UpdateFinal/2kUdFinal.cfm [2] Kelly, D. et. al.,: "A 3V 340mW 14b 75MSPS CMOS ADC with 85dB SFDR at nyquist", Technical Digest ISSCC, 2001, pp. 134-439. [3] Veendrick, Harry: "Digital goes Analog", Proceedings ESSCIRC 1998, pp. 44-50. [4] Jurczak, M. et.al.: “Dielectric pockets-a new concept of the junctions for deca-nanometric CMOS devices”, lEEE-Transactionson-Electron-Devices (USA), vol.48, no.8, p. 1776-82, Aug. 2001 [5] Razavi, B.: "Design of Analog CMOS Integrated Circuits", McGrawHill, 2001. [6] Vittoz, E.A.: "Low-power design: ways to approach the limits", Proceedings of ISSCC '94, San Francisco, CA, USA, 16-18 Feb. 1994. pp.14-18, 1994.

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[7] Annema, Anne-Johan: "Analog circuit performance and processscaling", IEEE tr. on Circuits and Systems II, Vol. 46, No. 6, June 1999, pp. 717-725. [8] Pelgrom, M.J.M. et. al.: "CMOS Technology for mixed signal ICs", Solid-State Electronics, Vol. 41, No. 7, 1997, pp. 967-974. [9] Woerlee P. et. al.: "RF-CMOS Performance Trends" IEEETransactions-on-Electron-Devices (USA), vol.48, no.8, p. 1776-82, Aug. 2001. [10] Walden, R.H.: "Analog-to-Digital Converter Survey and Analysis" IEEE Journal on Selected Areas in Communications, Vol. 17, No. 4, April 1999, pp. 539-550. [11] Bult, Klaas: "Analog Design in Deep Sub-Micron CMOS", Proceedings ESSCIRC 2000, pp. 11-17. [12] Ploeg, Hendrik van der et. al.: "A 3.3-V, 10-b, 25-MSample/s Two-Step ADC in CMOS", IEEE Journal of Solid-State Circuits (JSSC), Vol. 34, No. 12, December 1999, pp. 1803-1811. [13] Ploeg, Hendrik van der, et. al.: "A 2.5V, 12b, 54MSample/s 0.25um CMOS ADC in Technical Digest ISSCC, 2001, pp. 132–439.

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SCALABLE HIGH RESOLUTION MIXED MODE CIRCUIT DESIGN R.J.Brewer Analog Devices Pembroke Road, Newbury RG14 1BX, U.K. bob. [email protected] ABSTRACT This paper discusses architectures for analog to digital interchange which are suitable for implementation in deep sub-micron CMOS mixed mode technologies. Discussed in detail are successive approximation and low over-sampling ratio sigmadelta converters giving >12 bits resolution at order MHz bandwidth. Also discussed are architectures potentially suitable for operational amplifiers buffering such converters, integrated in the same technology. 1. INTRODUCTION The topic of “scalable high resolution mixed mode circuit design” is potentially broad and the focus of this paper will be architectures suitable for fabrication in deep sub-micron CMOS technology (DSM) which implement analog to digital interchange at bandwidths from DC to several MHz and with resolutions of 12 bits and above. Analog design in DSM is dominated by the reality that the process driver is digital. Typically, a mixed mode DSM technology will lag in development by about a year behind its digital substrate and comprise a digital process with the addition of reasonably linear double polysilicon capacitors with a layer of medium-resistivity polysilicon available to create non-trimmable resistors with matching no better than a few tenths of a percent with realistic values up to several tens of 23 J. H. Huijsing et al. (eds.), Analog Circuit Design, 23-42. © 2002 Kluwer Academic Publishers. Printed in the Netherlands.

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kohms. Moore’s Law famously identifies a trend line of a 70% linear geometry shrink per 18 months; the current range of mixed mode processes widely available run as follows: 0.5um/5v to 0.35um/3v to 0.25um/2.5v to 0.18um/1.8v. In many cases higher voltage devices are also offered on the lower voltage processes; it is tempting to assume these may be used for the analog sections of a mixed-mode circuit, but in some cases these higher voltage devices are intended for digital I/O and have poor electrical properties which make them less, not more, suitable for analog circuits. Thus this paper assumes that scalable means using the small geometry devices. Another subtle assumption is that application forces are driving up signal processing information bandwidth and a driver in scalable design is to use the speed of these processes: so that analog bandwidths of MHz are more interesting than kHz. Although this paper addresses scalable design, it is worth remarking that in many cases this may not be the economically optimum design approach to the implementation of systems combining complex logic and high performance analog. There are several approaches to avoiding rather than solving the problem. In some DSM technologies, high performance analog devices with thicker gate oxide and higher supply voltage are made available permitting what is essentially a hybrid design approach on one substrate. However, this means the digital section must carry the cost overhead of the dual gate oxide and other analog components, such as double polysilicon. If the number of interconnects required between the analog and digital sections is small, it may actually be better to split the die. Package engineers are becoming increasingly comfortable with dual paddle packages with die-to-die bonding, or alternatively low pin-count packages are becoming increasingly small: e.g. an MSOP-8 at just 3mmx4.9mm. 2. TRENDS IN DEVICE PROPERTIES

The most obvious effect of scaling is an approximately linear shrink in permitted supply voltage allowing about 1 volt per 0.1 um minimum gate length. Unfortunately shrinking does little if anything for one of the dominating noise sources in CMOS data conversion design: kTC noise. This results in an approximately linear compression with

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scaling of signal to noise ratio. However, process designers do usually scale the threshold voltages to some degree with the shrink, so that the ability to stack devices in, for example, an opamp design, does become compressed with process scaling but relatively softly. Thus scalable design implies maximising the p-p signal range within the supply voltage whilst some stacking of devices is still acceptable but becomes increasingly undesirable. Some processes may also offer optional low threshold devices for analog design; but note these may be leaky if used as switches. A major problem is a rising 1/f (flicker) noise corner frequency: for example for a minimum length NMOS with W/L=10 at 100uA the 1/f corner may be around 1MHz at 0.35um and escalate to tens of MHz at 0.18um. Amplifier stage gains are low (e.g. 25dB) and decline with scaling and, as already mentioned, stacking devices for cascoding is permitted but increasingly difficult. Finally leakage currents – between all terminals of the MOS device – rise with scaling. Scalable design implies accommodating all these trends. 3. ANALOG to DIGITAL CONVERSION Two architectures are coming to dominate sub-micron and deep-submicron CMOS design in the resolutions and bandwidths discussed here: SAR (successive-approximation) converters with electricallytrimmable capacitor-array DACs [1,2] and low-oversampling-ratio sigma-deltas [14-30]. For very high resolution conversion at low bandwidths sigma-delta converters with high oversampling ratios (>16, perhaps typically 128) are the predominant technology. These typically have architecturally simple single loops with single bit quantization and noise shaping of 2-4 orders. These work very well and are very scalable to very deep sub-micron. It may be expected that they will remain a very commercially important class of converter but will not be discussed further here, where the focus is on medium bandwidth (of order MHz) leading edge architectures. At higher bandwidths (10-1000MHz) flash and pipelined converters dominate; again, these will not be discussed further here.

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In the early to mid 1990s there was a wave of great interest in selfcalibrated ADCs. Typical lithography permits analog element matching to around 12 bits resolution. To achieve high yields at 12 bits, and performance beyond, wafer level laser trimming was the dominant technology. Self-calibration became an attractive alternative apparently better suited to volume-manufactured CMOS technologies [3-5] giving a high resolution ADC capability to designers without access to laser trimming. There are two fundamental approaches. The first uses some slow but high linearity method such as an integrator to create a very linear sequence of voltage levels which are then used to calibrate the capacitor or resistor array which forms the working converter. The second relies on the observation that in an ideal linear binary-weighted element (e.g. capacitor) array each element equals the sum of all the lesser weight elements (plus 1 LSB). Thus a calibration algorithm can clearly be devised which relies solely upon establishing internal equalities, without reference to any absolute calibration standards. In either case, some on-chip memory is then required to store calibration constants which are applied dynamically to some form of trim-DAC during conversions. This all works; however, the trend seems to be away from self-calibration as it increasingly appears that similar performance can be achieved more economically and more conveniently for the user with one-time electrical trimming as discussed below. 3.1 Capacitor Array Successive Approximation ADCs

The core element is a DAC implemented with an array of binary weighted double-polysilicon capacitors. This is usually broken into two similar sections, making the upper and lower bits, linked by a series capacitor which de-weights the lower bits. To achieve >12 bits performance various of these capacitors are trimmed by further small arrays of capacitors which are switched in or out at test [1,2] (Fig 1). The capacitors are usually double plates of polysilicon with silicon dioxide dielectric which are very mechanically and electrically stable. Since these structures are very stable post-manufacturing, the trim is usually once-only with a small on-chip PROM, often comprising electrically-blown polysilicon fuses. This architecture is relatively cheap to manufacture and easy to use in the end application as no

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calibration cycles are needed. There are very few publications describing the internal detail of such converters but they are of great commercial importance.

A problem with SAR converters is that all bit trials are critical and errors are non-recoverable. A popular trend is to incorporate redundancy into the bit trials with an algorithm which permits errors made in the earlier (MSB) bit trials to be corrected later [8-13]. This gives improved noise immunity and permits a higher sampling rate by permitting accelerated bit trials. This also plays well to DSM scaling and mixed mode design. Various methods can be used, although all ultimately serve the same purpose and overcome the same weakness in a conventional binary weighted successive approximation search algorithm. The problem is illustrated in Fig 2a. Assume the true input voltage is slightly below mid-scale, but the comparator makes an error and believes it lies slightly above. This error could be due to allowing insufficient time for DAC settling (e.g. settling to the 10 time constants required for 0.005% accuracy), analog noise, digital noise or reference or ground bounce. It is obvious that with a simple binary

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weighted search path there is no path through the search space which recovers the error. However, consider the search path of Fig. 2b with “one bit per bit redundancy”. After the first bit trial (with erroneous result) the search space is shifted by one quarter of its span in the direction of the result and the bit trial repeated. After this second bit trial the search space is halved normally according to the comparator result, but it is now certain that the true input value lies within the new reduced search space even with an error in the first comparator result of ¼ of the span of the search space. This algorithm converges on the correct result with a tolerance for error of ¼ of the current search space at each bit trial. Twice as many bit trials are required but each may be many times faster with, for example, DAC settling of only a few time constants.

In practice, one redundant bit per bit may be excessive. Some designers favour only one redundant bit in the whole array, typically around half way down the sequence of bit trials. Others favour perhaps one redundant bit per 4 bits; this latter still allows large errors but only increases the number of bit trials by 5/4. A conceptually elegant alternative which achieves the same result is a successive approximation with an array with slightly less than binary weighting, as in Fig 2c. It will be apparent from inspection that this also allows a search path which converges on the correct result despite moderate errors on the way. However, it suffers the major disadvantage of using non-binary-weighted elements. The analog elements, typically capacitors, are difficult to make with accurate non-

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binary weighting, and the results of the non-binary bit trials require significant computation to map onto a binary coded output word. As supply voltages are reduced with scaling there is generally a lessthan-proportional decrease in MOS threshold voltages, together with a need to make the signal range as close to the full supply voltage as possible, so that on-resistance in the input sampling switches become increasingly important as the effective over-voltage reduces. This is eased by pumping or boot-strapping the gate voltage on the NMOS switches but of course this ideally should be as much as possible without exceeding the processes absolute maximum voltage rating. Gate boot-strapping methods have been developed to do this accurately [6,7,17]. The above collection of design features make for cheap, easy to use and robust converters which are suitable for scaling to deep submicron CMOS processes. Successive approximation converters are the subject of very little published work but of great commercial importance which is likely to continue into the foreseeable future. For every paper published on the SAR solutions there are likely ten on the sigma-delta; but for every sigma-delta ADC manufactured there are likely ten SAR. Converters with signal bandwidths in the range 110MHz and resolutions in the range 12-16 bits are likely achievable in the near future at time of writing using both the SAR architectures discussed above and the low oversampling ratio sigma-delta discussed below as the two approaches increasingly converge. 3.2. Low Oversampling Ratio Sigma-Deltas There is an observable architectural evolution or fashion trend at the leading edge: very high order single-bit single-loop: e.g. -order shaping such as the established CS5396 or AD7722 single-bit multi-loop: e.g. 4 loops of order 2+1+1+1 ( order) such as the established more recent AD7723

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multi-bit single-loop or multi-loop designs using bit-shuffling to suppress non-linearity in the multi-bit DAC: e.g. 3 loops of order 2+1+1 order) (3x4)-bit [15] For high resolution at low bandwidths simple (e.g. order) single-bit single-loop modulators appear to have a commercially very important long term future. However, we focus here on the informationbandwidth leading edge, where the performance of interest could be 16 bits at 2Ms/s or 20 bits at 100ks/s (which have the same resolvable information rate). Increasing the order of the noise shaping in single-bit single-loop designs has apparently reached its natural limit as instability limits the benefit of increasing orders of noise shaping. Converters have been made (and are commercially successful products from more than one company) with order loop filtering, but in truth order probably represents a useful maximum. Multi-loop and multi-bit designs achieve higher performance but there exists a very wide range of architectural alternatives. We will now discuss the optimisation of such architectures.

The principle of multi-loop architectures (Fig 3.) is that the quantization noise in the first loop is copied as an analog voltage into

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a second loop where it is measured, to be subtracted in the digital domain. This process may be repeated or cascaded indefinitely, resulting in a theoretical possibility of any desired SNR. The main limitation is the accuracy of the analog copy from the first to second loop; thus the lower the quantization noise in the first loop, the lower the accuracy requirement of this analog amplifier. This suggests that multiple orders of noise shaping and multiple bits of quantization be pushed into the first loop. However, aggressive noise shaping in the first loop may result in stability problems which limit the achievable shaping, as is well known. Also, if multi-bit quantization is used in the first loop, it must be bit-shuffled as its integral non-linearity otherwise appears directly in the digitised output. If the multi-bit quantizers are in second or subsequent loops, which are converting quantization noise and not signal, bit-shuffling is likely not needed. Further, the number of comparators needed in the multi-bit flash converters is minimised if the multi-bit quantization is spread across multiple flash converters in multiple loops: for example, if 6 bits of quantization are chosen, this requires 64 comparators in one converter but ideally 3x3=9 comparators if split into three 2-bit converters. Whether dither is required in the first loop is also arguable: for very low residual tones (e.g. 12 bits resolution over a signal bandwidth from DC to several MHz. In the light of the scaling issues summarised above, we postulate that an opamp architecture is “scalable” if it offers:

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“rail-to-rail” signal swing: this is most important at the output where a reasonable target is a signal p-p swing of >75% of VDD but is also desirable as a common mode range at the input for high impedance unity gain buffering multiple gain stages: e.g. 5 inverter stages suppression of low frequency flicker noise (which of course also brings good DC performance). Rail-to-rail output stage design is well known [32] and the textbook methods appear adequately scalable with stacking of threshold and saturation voltages which can be accommodated within the shrinking supplies. However the equivalent textbook input stages [ibid.] with rail-to-rail common mode (CM) range appear challenging for high performance (MHz bandwidth and low THD) applications because of input offset shifting over the CM range as the input stage transitions between N- and P-MOS conduction. Two scalable architectures are shown. Both can use rail-to-rail output stages to maximise p-p signal swing and thus SNR. Both are scalable in that they further meet the requirements of multiple (five) gain stages at low frequencies and suppression of flicker noise whilst retaining wide signal bandwidth and the capability of low distortion at order MHz bandwidths.

The design shown in Fig. 5 (unpublished) essentially splits the signal by frequency into three paths which are recombined by summing the

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outputs of transconductance stages, with the lowest frequencies passing through a chopped or auto-zeroed path with 5 gain stages while the high frequencies have a short un-chopped 2-stage path. This design only works well over a limited input CM range as the input differential pairs require some voltage headroom and if used in a noninverting configuration the harmonic distortion will be limited by the input pair common mode rejection ratio. Further, the chopped or autozeroed path has a bandwidth much lower than the full signal bandwidth and cancellation of DC offsets and low frequency flicker noise effectively relies on time-averaging the input offset to zero. It is thus intolerant of non-linear transient overloads which will generally not average correctly to zero. The low frequency path in this design can use any of the wide variety of chopping and auto-zeroing methods. This field has itself been the subject of a comprehensive review paper so will not be discussed further here [33]. It is thus suited to applications where the input common mode range and frequency spectrum are well defined and thus known to lie within the architecture’s limitations. It has been used to the author’s knowledge successfully as a D/A converter output reconstruction buffer and driver, with application-specific implementations in both 0.6um with 5v supply and 0.35um and 3v supply. The application in 0.6um delivers 6v p-p (differential) into 1 kohm with –85dB distortion at 300kHz; the 0.35um driver application delivers 4v p-p (differential) into just 8 ohms load with a class A/B output stage with order 10mm wide output MOS devices with –75dB distortion at 140kHz [Hurrell – private communication]. This architecture should scale well to smaller geometries and lower supply voltages.

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The design in Fig. 6 (unpublished at time of writing) has an inherently rail-to-rail wide bandwidth input CM range and is tolerant of nonlinear transients, which makes it better suited as an A/D converter buffer where the input signal is undefined. However it contaminates the signal with some (few millivolts) level of modulator frequency (>100MHz) noise which must then be suppressed by further filtering: for example, when driving an A/D converter with a 20pF capacitance a series resistance of around 500 ohms is necessary to provide the necessary attenuation of modulator feed-through. Alternatively, with some ADC architectures the ADC may be operated synchronously with the modulation at a somewhat reduced modulation frequency and the output of the opamp sampled twice per clock cycle with the signal voltage taken as being the sum or average of the two samples. The input voltage is modulated up to a frequency well beyond the signal bandwidth; in this example a modulation frequency in the range 20-200MHz is practical in geometries in the range 0.6-0.25um with signal bandwidths of a few MHz. It is AC amplified by a 2-stage amplifier and demodulated back to base-band with a demodulator which incorporates a differential to single ended conversion, followed by a 3-stage integrator. With 3 gain stages the integrator requires an internal nested pole to preserve stability. The use of two gain stages in the AC amplifier does not greatly degrade the loop stability as the first stage must be run at quite high current levels to achieve adequately low thermal noise, resulting in it having very low delay.

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Whilst this is a functional design, it benefits greatly from two key improvements, as follows (Fig. 7). It will be apparent that, with 5 gain stages and a nested pole, the amplifier’s transient response will tend to be poor. A transconductor (Gm stage) is thus added leapfrogging the 3-stage integrator. The 3-stage integrator is merged with the transconductor via a resistor with a value R=l/Gm. An analysis of this compound structure shows that it combines much of the low frequency gain of the 3 stages and the transient behaviour of the simple transconductor.

A further improvement is to incorporate the passive current filtering network shown between the demodulator and the integrator. Analysis will show that this network has a band-stop current transfer function with zero phase shift at a selected high frequency (Fig. 8), chosen to be the amplifier’s unity gain frequency.

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In this example, optimised for an opamp with unity gain bandwidth of 40MHz and a maximum signal frequency of 1 MHz, it is seen that the effect of the filter is to permit a factor 3 reduction in integrator time constant to give 3x loop gain increase at the maximum signal frequency with zero phase loss at the unity gain bandwidth. With suitable optimisation of component values this permits a significant reduction in the value of the integrator time constant without loss of overall loop phase margin, with a corresponding increase in gain and thus reduction in harmonic distortion at the higher end of the signal spectrum. This architecture has been implemented in 0.6um with 5v supply achieving –80dB THD at 500kHz as a 2.5v p-p follower.

5. CONCLUSION This review paper has identified the issues facing the designer of ADCs, DACs and buffering opamps which are: inherently robust in DSM CMOS from 0.5um / 5v down to 0.18um / 1.8v and potentially further; and achieve resolutions of >12 bits at bandwidths up to several MHz. Architectures which meet these requirements have been discussed.

6. REFERENCES (successive approximation converters) 1) “A Two-Stage Weighted Capacitor Network for D/A-A/D Conversion” Yee, Terman and Heller, IEEE Jnl. of Solid State Circuits, Vol. 14, pp. 778-781, Aug. 1979 2) “A Low Power 12b Analog to Digital Converter with On-Chip Precision Trimming” de Wit et al. IEEE Jnl. of Solid State Circuits, Vol. 28, pp. 455-461, Apr. 1993 (self-calibration)

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3) “A Self-Calibrating 15 bit CMOS A/D Converter” Lee, Hodges and Gray, IEEE Jnl. of Solid State Circuits, Vol. 19, pp. 813-819, Dec. 1984 4) “Architecture and Algorithm for Fully Digital Correction of Monolithic Pipelined ADCs” Soenen and Geiger, IEEE Trans. Circuits and Systems II, Vol. 42, pp 143-153, March 1995 5) “200mW 1Ms/s 16-b Pipelined Converter with an On-chip 32-b Microcontroller” Mayes et al., IEEE Jnl. of Solid State Circuits, Vol. 31, pp. 1862-1872, Dec. 1996 (pumped switches) 6) “Two-phase Bootstrapped CMOS Switch Drive Technique and Circuit” Singer and Brooks, USP 6118326, Sep. 2000 7) “Very Low-Voltage Digital-Audio Delta-Sigma Modulator with 88dB Dynamic Range Using Local Switch Bootstrapping” Dessouky and Kaiser, IEEE Jnl. of Solid State Circuits, Vol. 36, pp. 349-355, Mar. 2001 (bit trial error correction algorithms) 8) “A 16 bit 500ks/s 2.7v 5mW ADC/DAC in 0.8um CMOS using Error-correcting Successive Approximation” Schofield, Dedic and Kemp, Proc. European Solid-State Circuits Conference, Southampton, 1997 9) “Successive Approximation Type Analog to Digital Converter with Repetitive Conversion Cycles” Dedic and Beckett, USP 5870052, Feb. 1999 10) “Method for Successive Approximation A/D Conversion” Cooper and Bacrania, USP 4620179, Oct. 1986 11) “Analog to Digital Conversion with Multiple Charge Balance Conversions” Cotter and Garavan, USP 5621409, Apr. 1997 12) “Charge Redistribution Analog to Digital Converter with Reduced Comparator Hysteresis Effects” Hester and Bright, USP 5675340, Oct. 1997 13) “Algorithmic Analog to Digital Converter Having Redundancy and Digital Calibration” Kerth and Green, USP 5644308, July 1997 (multibit sigma delta modulators) 14) “An Audio ADC Delta-Sigma Modulator with 100dB Peak SINAD and 102dB DR Using a Second-Order Mismatch-Shaping DAC” Fogleman et al., IEEE Jnl. of Solid State Circuits, Vol. 36, pp. 339-348, Mar. 2001

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15) “A 90dB SNR 2.5MHz Output Rate ADC Using Cascaded Multibit Delta Sigma Modulation at 8x Oversampling Ratio” Fujimori et al., IEEE Jnl. of Solid State Circuits, Vol. 35, pp. 1820-1828, Dec. 2000 16) “113dB SNR Oversampling DAC with Segmented Noise shaped Scrambling” Adams, Nguyen and Sweetland, IEEE Jnl. of Solid State Circuits, Vol. 33, pp. 1871-1878, Dec. 1998 17) “Cascaded Sigma-Delta Pipeline A/D Converter with 1.25MHz Signal Bandwidth and 89dB SNR” Brooks et al., IEEE Jnl. of Solid State Circuits, Vol. 32, pp. 1896-1906, Dec. 1997 18) “Tree Structure for Mismatch Noise-Shaping Multibit DAC” Keady and Lyden, Elec. Letters, Vol. 33, pp. 1431-1432, Aug. 1997 19) “A 74dB Dynamic Range 1.1 MHz Signal Band Order 2-1-1 Cascade Multibit CMOS Sigma Delta Modulator” Madeiro et al., Proc. European Solid-State Circuits Conference, Southampton, 1997 20) “Delta-Sigma Data Converters” Norsworthy, Schreier and Temes, IEEE Press, 1997 21) “A Monolithic 19 bits 800kHz Low Power Multibit Sigma Delta Modulator CMOS ADC Using Data Weighted Averaging” Nys and Henderson, Proc. European Solid-State Circuits Conference, pp. 252-255, Southampton, 1996 22) “A Low Oversampling Ratio 14-b 500kHz Delta-Sigma ADC with a Self-Calibrated Multibit DAC” Baird and Fiez, IEEE Jnl. of Solid State Circuits, Vol. 31, pp. 312-320, Mar. 1996 23) “Linearity Enhancements of Multi Bit Delta-Sigma D/A and A/D Converters using Data Weighted Averaging” Baird and Fiez, IEEE Trans. Circuits and Systems II, Vol. 42, pp753-762, Dec. 1995 24) “A high Resolution Multi Bit Sigma Delta Modulator with Individual Level Averaging” Chen and Leung, IEEE Jnl. of Solid State Circuits, Vol. 30, pp. 453-460, Apr. 1995 25) “Data-directed Scrambler for Multi-Bit Noise-Shaping D/A Converters, Adams and Kwan, USP 5404142, Apr. 1995 26) “Noise Shaped Multi Bit D/A Converter Employing Unit Elements” Schreier and Zhang, Elec. Letters, Vol. 31, pp. 1712-1713, 1995 27) “A High Resolution Multi Bit Sigma Delta Modulator with Digital Correction and Relaxed Amplifier Requirements” Sarhang-Hejad and

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Temes, IEEE Jnl. of Solid State Circuits, Vol. 28, pp. 648-660, June 1993 28) “Fourth Order Two Stage Delta Sigma Modulator using both 1 Bit and Multi Bit Quantizers” Tan and Eriksson, Elec. Letters, Vol. 29, pp. 937-938, May 1993 29) “Multi Bit Sigma Delta A/D Converter Incorporating a Novel Class of Dynamic Element Matching Technique” Leung and Sutarja, IEEE Trans. Circuits and Systems II, Vol. 39, pp. 35-51, Jan. 1992 30) “A 50MHz Multi Bit Sigma Delta Modulator for 12 Bit 2MHz A/D Conversion” Brandt and Wooley, IEEE Jnl. of Solid State Circuits, Vol. 26, pp. 1746-1756, Dec. 1991 31) “Current Distribution Arrangement for Realising a Plurality of Currents having a Specific Very Accurately Defined Ratio Relative to Each Other” van de Plassche, USP 4125803, Nov. 1978 (operational amplifiers) 32) “Design of Low-power Low-voltage Operational Amplifier Cells” Hogervorst and Huijsing, Kluwer Academic Pub., 1996 33) “Circuit Techniques for Reducing the Effects of Opamp Imperfections: Autozeroing, Correlated Double Sampling and Chopper Stabilisation” Enz and Temes, Proc. IEEE, Vol. 84, pp. 1584-1614, Nov. 1996

SCALABLE “ HIGH VOLTAGES” INTEGRATED CIRCUIT DESIGN FOR XDSL TYPE OF APPLICATIONS

Domenico ROSSI Telecommunication and Peripheral/Automotive Group Wireline Communication Division ST Microelectronics, 20041 Agrate Brianza, V.Olivetti 2, Italy

ABSTRACT Service providers are largely adopting ADSL technology and telcos to deliver high-speed data communication over traditional copper twisted pair. Continuous growth of this market has led to new requirements for lower cost, higher transmission bandwidth, improved power efficiency and longer reach. Most of these targets are heavily depending on the electrical performances of XDSL Line Drivers and Receiver which for cost reasons are, nowadays, often embedded with other functions. This paper describes most recent advances in semiconductor technology and design techniques specifically adopted to comply with these technical demands. Practical examples of Line Driver realized in different technologies and adopting different circuit architectures are also reported. INTRODUCTION AND TUTORIAL ON SYSTEM REQUIREMENTS. XDSL technology features significant improvements in data transmission compared to traditional analog modems by combining advanced signal processing techniques (digital modulation, digital equalizat ion, error corrections, etc) with high performance analog interfaces. To better understand what such analog interfaces (from hybrid to the line drivers) asks for and how this translates into specific requirements for semiconductor technologies and design skills, a short tutorial XDSL system top level requirements is here reported. For sake of simplicity, this tutorial is here limited to ADSL, but most of the considerations here done, are easily extendable to any XDLS transmission. 43 J. H. Huijsing et al. (eds.), Analog Circuit Design, 43-56. © 2002 Kluwer Academic Publishers. Printed in the Netherlands.

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Moreover, the electrical characteristics of an ADSL analog front-end, such as line driver linearity are particularly stressed in case of DMT, the mo/demodulation technique typical of this kind of transmission. As said before, ADSL relies on DMT modulation to carry digital data. For instance, ADSL spectrum is composed by individual sub -bands QAM modulated and uniformly spaced in frequency 4.3125KHz apart and extending up to 1.1 MHz (see Figure 1-a).

Viewed in the time domain, a DMT signal appears as a pseudo -random noise typically having low rms voltage level (see Figure 1 -b), but ADSL Line drivers have to be also capable of delivering high voltage peaks that sometimes occur.

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Apart from voltage ratings, intermodulation is another key feature to carefully look at. To preserve signal integrity, the information contained in each sub -band has not to be corrupted by any signal from other sub -bands. MTPR ( multi-tone power ratio) expressed as the relative difference expressed in dBc between the measured power in a sub-band left empty and the power of another sub -band, is the parameter used to quantify this feature. As a consequence, a good line driver is a component featuring high voltage handling capability, high slew-rate and bandwidth and very good linearity.

Summarizing, the minimum specifications required to start the line driver design are: 1. Average power level required on the line (PL), 2. Crest Factor for the modulation chose 3. Line impedance assumed for the average power specification (RL), 4. Transmission frequency band (BW), 5. Target harmonic distortion. The first three of these parameters may be used to compute the initial requirements for any line driver, which at a minimum, has to deliver both the required voltage and current output swings. The maximum required line voltage, VLPP, might be computed by stepping through the following equations

The maximum VLPP on the line has to be taken as a primary design goal. For a given VLPP, the voltage handling capability of the line drivers depends on the characteristics of the hybrid used. The hybrid, for everybody who is familiar with communications over twisted copper pair, is the component used to separate Rx from Tx signals , perform line termination, isolate the line from the modem, and optimize, when possible, the power delivered to the line. Even if an example of fully monolithic line transceivers exists [1, 2], most of today hybrids are transformer based (see Figure 2 -a).

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Transformer is, in fact, an “ almost perfect” component, since ever used to match the load impedance while meeting the obvious constraints in terms of voltage and current of the component it is driven by (changing the transformer turn ratio). In practice, for a given VLPP and impedance, the amplifier’s output voltage and currents can be traded off with the transformer‘s turn ratio. Increasing the turns ratio will not only decre ase the required voltage swing (but at the expenses of a higher current output), but will also allow lower supply voltage and, in turn, the use of low-voltage components/ technologies. There are, however limitations increase the transformer turns ratio. For instance: High peak-output currents will start to limit the available voltage swing impacting the power efficiency of the power supply. A high turns ratio in transformers can limit bandwidth and be more prone to distortion. Often the transformer is in the path of the received signal path coming down the line. An high step-up ratio will a high step-down for the received signal impacting noise characteristics of the RX path and, hence reach. Examples of peak voltage and current output requiremen ts for ADSL line driver Vs. different output power and transformer turns ratio are reported in

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Table 1. It must be noted that 13dBm corresponds to the power transmitted in up stream, 20.4dBm to the power in down stream.

This said, it is also mandatory to matc h line impedance. This can be achieved either by adopting passive, as implemented in Figure 2-a or active impedance synthesis (Figure 2-b).

While for passive impedance synthesis, a series resistor is generally put at the output of the amplifier (but this resistor dissipates significant power, while the load is fed just by a part of the amplifier’s voltage swing), it is nowadays

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common practice to use active impedance synthesis to match line impedance while minimizing the maximum output voltag e swing and the dissipated power. This Driver uses both voltage and current feedbacks (through R3) to independently set the output impedance Rout and voltage gain G. Calculating output voltage and current, it is possible to determine both the line driver output impedance and the gain given as:

By using active impedance synthesis is then possible to minimize the output voltage swing of the line driver. WHAT HIGH VOLTAGE TECHNO LOGY FOR XDSL? Since ever, microelectronics has been driven by the insatiable requirement for better performance and lower cost. This not only translates into smaller size for a given function but also into proper integration of different functions on a single semiconductor substrate. Approaches have been proven often feasible and on a case-by-case basis economically applicable to address different applications and market segments; both approaches have been also adopted in case of XDSL. Common to both th e two approaches is the requirement for high-speed components showing high ft and minimum parasitic capacitances even when withstanding high voltage condition. To better understand the implication involved in realizing such a kind of components it is worth referring, for sake of simplicity, to the voltage limitations of npn transistor. [3]

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As shown in Figure 3, its collector to emitter breakdown voltage with base shorted (Biceps is usually made equal to Bacon) mainly depends on the breakdown voltage of diode D1 and D2. The net epitaxial layer W1, its resistivity and the reach-through mechanism define the breakdown voltage of D1 while the breakdown of D2 mainly depend s on the radius of curvature of the base diffusion. In standard bipolar process processes, an increase maximum sustainable voltage is achieved by increasing the thickness and the resistivity of the epitaxial layer. The bigger these two values, the bigger the lateral diffusion of the isolation layer, the bigger the size of all the junction isolated components. Minimizing the size of all these components means minimizing the epitaxial thickness and the out-diffusion of the buried layer during all thermal step s following the epitaxial growth. In the following two example of one to the other not mutually exclusive are reported Dielectric isolation is another technique often used. This technique often offers significant advantages over junction-isolated process for high-speed analog circuits. Trench lateral isolation of SOI bonded wafers drastically improves circuit density for thick epithaxy because the lateral diffusion of isolation diffusion is eliminated.

Table 2 details the difference between devices featurin g the same current density and realized in the two technologies. The junction isolated PNP transistor’s area is roughly four times the area of a comparable dielectrically isolated PNP, while a junction isolated NPN is roughly 1.5 times as large as the equivalent dielectrically isolated NPN.

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Another way of minimizing the size of high voltage components is the adoption of high voltage DMOS components. Once fixed Bacon, the voltage capability of a bipolar technology is, in fact, defined by the breakdown volt age Bicep (emitter to collector breakdown voltage with open base). [4] Since BVceo is lower than Bvcbo and given by

A bipolar transistor can be regarded as also incapable to fully exploit the maximum technology the technology is capable of. On the contrary, a DMOS component (see Figure 4) is capable of working at a breakdown voltage Beds equal to the Bacon of the parasitic nun component provided that the base to emitter short circuit is good enough. To some extend, DMOS capable junction isolated technologies feature small component size. As an additional advantage (see in the following), DMOS technologies can also be made compatible with CMOS transistors that, in its turn, can enable the realization of highly complex mixed ICs.

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INTEGRATION OF HIGH VOLTAGE DMOS HIGH COMPONENTS INTO SUBMICRON TECHNOLOGIES.

VOLTAGE

Designing highly complex Smart Power IC s requires taking advantage of available low voltage IP s ideally adding high-voltage devices into already existing VLSI process platform. Unfortunately, the evolution of smart power technologies toward finer and finer micro lithography asks to solve conflicting requirements such as merging manufacturing drive-in steps which, for high voltage power components are usually long and at high temperature, while, in case sub -micron technologies, must be “low temperature” to guarantee good yield and process reproducibility (mainly for thin oxide layers). This has been, for instance achieved by exploiting innovative technology steps which have made possible the realization of H.V. fully complementary NChannel and P-Channel DMOS components into a standard VLSI CMOS technologies. [5] High voltage lateral DMOS are impleme nted by realizing the Body region by means of a large angle tilt implantation masked by the gate layer and without requiring any specific thermal treatment. Energy and tilt angle implant are depend on the compromise between lateral/vertical junction depth and doping charge i.e. between required sourceto-drain punch-through sustainable voltage and component threshold voltage (while large tilt angles are more effective in pushing charge in the DMOS active channel, low tilt angles reduce channel charge and length causing premature punch-through). 45° angle is usually found as the best compromise between these two opposite requirements. In BCD6 (0.35um) the N-LDMOS P-body layer is to be directly embedded in CMOS epic-pockets. Scaling down the gate oxide thickness requires also a proper LDMOS drain structure engineering. In BCD6, LDMOS and CMOS share exactly the same gate oxide (70nm). To avoid dangerous overcrowding of the equip -potential lines at the drain side, it is possible to adopt a gate layout stepping over the field oxide, while changing the doping profile of N-Well, it is possible to properly size drain extension region. With different DMOS drain solution a voltage capability from 16V to 20V are achievable. When higher operating voltages are required, dedicated low -doping N-Well is to be added. In this way, breakdown voltages in excess of 60V are achievable. To further increase BVdss, the heavily doped N+ buried layer is replaced with a

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low doping buried well and RESURF technique is to be adopted. In th is case breakdown voltage in excess of 100V is easily achievable. Table3 summarizes the main features concerning N-Channel Lateral DMOS realized in BCD6 (0.35 um CMOS).

Exploiting the flexibility offered by the large tilt implant technique used to realize the N-channel DMOS P-body region, it is possible to implement a Ntype body region to build P -channel DMOS Transistors. As a matter of fact, fully complementary N-channel and P-channel type of components are, nowadays available in low voltage semiconductor processes.

COMPLEMENTARY, DIELECTRICALLY ISOLATED BIPOLAR TECHNOLOGY ON SOI In case of XDSL application, SOI and dielectric isolation is, nowadays, getting more and more acceptance because of the its good characteristics in terms of speed. Minimizing the component size, translates automatically into reduced parasitic capacitances. [6] P and N buried collectors are usually formed by ion implantation after which an n-type epitaxy layer is grown to form the intrinsic collector of the NPN.

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A pwell is added to form the intrinsic collector of the PNP. Lateral isolation is achieved by etching trenches down to the buried oxide. The t renches are usually filled with LPCVD oxide and polysilicon. Transistors emitters can be either Silicon or Poly. Always referring to Table 2, the base to collector junction capacitance of the junction isolated NPN is roughly twice that of the dielectrically isolated NPN’s, and its substrate capacitance is three times bigger. Same applies for PNP’s. Measurements reveal that the cut-off frequency for the bipolar transistors is much higher. Nowadays it is possible to easily obtain NPN and Isolated Collector PNP featuring Ft of more than 2 / 6 GHz for NPN and 2 / 4 GHz for PNP.

AN EXAMPLE OF ADSL LINE DRIVER REALIZED IN MIXED BIPOLAR, CMOS, DMOS MIXED TECHNOLOGY. Even if most of today available Line Driver for C.O. (Central Office) is realized by fully complementary high-speed bipolar processes, an example of line driver realized in Multipower BCD (Bipolar, Cmos, Dmos) technology is here reported. The functional diagram is shown in Figure 5.

It consists of a differential gain stage followed by a class AB output stage. The input stage is a simple emitter coupled pair where low voltage high speed (ft=7GHz ) npn transistors are used to achieve low input referred noise. The

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intermediate is a classical Class AB stage used to guarantee high slew rate while featuring low quiescent current. While low voltage npn transistor (indeed cascaded) are here still used to get low noise features, the unavailability of pnp counterpart, led to the utilization of PDMOS components. The outputs of Class AB intermediate stage (Vp and Vn) directly drive the gate of a push-pull common drain output stage (PDMOS M13 and NDMOS M14). Quiescent current of M13 and 14 is controlled by current mirroring between M12 and M13 closed thorough the OTA. The key features of this ADSL Line driver are reported in Table 4.

AN EXAMPLE OF ADSL LINE DRIVER REALIZED IN HIGH SPEED COMPLEMENTARY SOI TECHNOLOGY Advanced complementary, SOI isolated bipolar processes that some times enable the capability of integrating submicron CMOS have recently developed to allow the realization of high performance ADSL line drivers. [7] High voltage technologies (Bvces>30V) semiconductor technologies offering transistors with ft in excess of 4GHz for pnp and in excess of 6GHz for npn are, as a matter of fact, nowadays available. In these technologies, current feedback is very often adopted (see Figure 6).

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SOI superior characteristics in terms of ft and parasitic capacitances easily allow high small-signal bandwidth and slew rate, while small base resistance (often shown in SOI technologies) and reduced biasing current result in low input voltage and current noise. Some key features of a comme rcially available current feedback C.O. driver realized in SOI are reported in Table 5.

Moreover, examples of SOI technologies allowing also the fabrication of accurate laser trimmed analog filters have been recently announced [XX].

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CONCLUSIONS The analog front-ends (AFE) of XDSL modems are typically partitioned into two technologies. Data converters, analog filters and Rx amplifiers are fabricated on low voltage technologies, while XDSL line drivers employ higher voltage processes. However, nowadays available high voltage process often embedding submicron CMOS components make it possible to conceive a different system partitioning with data converters, analog filters and Rx amplifiers integrated together with line drivers. Examples exists of ICs economically integrating all these functions and realized either on a fully complementary bipolar or on CMOS, DMOS centered technology.

REFERENCES (1) Zojer et al.,” A Broadband High-Voltage SLIC for a Splitter and Transformerless Combined ADSL-Lite /POTS Line Card “ ISSCC Digest of Technical Papers, pp.304-305, Feb.2000 (2) Berton et al., “ A High Voltage Line Driver (HVLDR) for Combined Data and Voice Services “ ISSCC Digest of Technical Pap ers, pp.302303,Feb.2001 (3) “Power Integrated Circuits: Physics, Design, and Applications” P.Antognetti, Editor, Mc Graw-Hill p.p.4.13-4.17. (4) “Smart Power ICs: Technologies and Applications” B.Murari, F.Bertotti, G.A.Vignola, Springer pp. 179-180. (5) C. Contie ro et al., LDMOS Implementation by large Tilt Implant in 0.6 BCD Process, Flash memory Compatible, Proceedings ISPS’99 (6) “A 30V Complementary Bipolar Technology on SOI for High Speed Precision Analog Circuits” R.Patel et Al. IEEE BCTV 2.3 pp 48 -50 (7) M.Cresi et al.,”An ADSL Central Office Analog Front-End Integrating Actively-Terminated Line Driver, Receiver and Filters” “ ISSCC Digest of Technical paper, pp.304-305, Feb.2001.

SCALABILITY OF WIRE-LINE ANALOG FRONT-ENDS Klaas BULT Broadcom Netherlands B.V. Bunnik, The Netherlands.

ABSTRACT Analog design in deep sub-micron technologies is a reality now and poses severe challenges to the circuit designer. Trends in technologies as well as their effects on circuit design are discussed. It is shown that, specifically for Wire-Line AFE’s, the power required for a certain dynamic range and bandwidth decreases with minimum feature size as long as a constant ratio between signal swing and supply voltage can be maintained. However, below channel-length, predictions of the threshold voltage endanger that requirement.

1. INTRODUCTION In Wire-Line applications (like Ethernet, Gigabit, Set-Top Boxes, Cable Modem’s, etc.), analog integration in deep sub-micron CMOS has become an economic necessity. Several papers already discussed the problems and design challenges of analog circuits integrated in purely digital deep sub-micron CMOS technologies [1] - [16]. This paper will discuss trends in technologies and their effects on circuit design, specifically focussed on Analog Front-End’s (AFE’s) for Wire-Line applications. Emphasis will be on the effect of supply voltage scaling on circuit design and performance. After discussing a generic Wire-Line Analog Front-End in section 2, section 3 deals with process scaling. Section 4 then deals with the effect of process scaling on Power Dissipation and in section 5 experimental data from literature corroborates the findings of section 4. Section 6 puts the previous results in perspective by discussing some details and caviats. In section 7, finally, the scalabitiy of Wire-Line AFE’s is discussed. Section 8 summarizes the conclusions. 57 J. H. Huijsing et al. (eds.), Analog Circuit Design, 57-70. © 2002 Kluwer Academic Publishers. Printed in the Netherlands.

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2.

WIRE-LINE ANALOG FRONT-END’S Wire-Line IC’s are a typical example of ULSI integration dominated by digital circuitry, with some peripheral analog circuitry. Analog signal processing is usually kept to a minimum. A generic AFE is depicted in Fig. 1. The analog input-signal either comes from the wireline hybrid (like in Ethernet), or through an RF Tuner (like in Cable applications). Gain, Gain-Control and Filtering may or may not be applied, dependent on application. The Track and Hold (T&H) and ADC function however are mandatory and form the core of the AFE. 3. PROCESS SCALING Of all the aspects of design in deep sub-micron technologies, the scaling of the Supply Voltage is the most obvious and most severely affects analog circuit design [5, 10, 12, 14, 15]. Fig. 2 shows the 1999 International Technology Roadmap for Semiconductors predicting a maximum 0.6V supply voltage for the year 2010 [17]. To get a feeling of how process-parameters have changed over time and will change in the near future, Table 1 gives an overview of 14 different processes, ranging from down to of which only the last two are predictions (data from [15, 17, 18, 21]). The Supply Voltage Oxide Thickness Threshold Voltage and Matching parameter of these 14 processes are plotted on a log-log scale in Fig. 3. For technologies larger than (or equal to) stays flat and equals 5.0V In smaller technologies, scales roughly linear with minimum feature size (although it follows a

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staircase function). Fig. 3 shows that both oxide thickness as well as matching scale down linearly with technology. Fig. 3 also shows threshold voltage clearly not scaling linearly, but more like a square-root function. The effect of that on voltage headroom is still not that strong as is still only 25% of This might change

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below as preliminary estimates show of approximately 300mV.

to have a lower limit

4. VOLTAGE SCALING AND POWER DISSIPATION Due to the continual down-scaling of the supply voltage over time, the Dynamic Range (DR) requires extra attention in circuit design. It has been shown that, especially in ADC front-end circuitry, matching is more dominant in determining the low-end of the dynamic range than noise [4,5]. Matching is reported to scale with oxide thickness which is clearly visible in Fig.3. Defining the Dynamic Range (DR) as the ratio between and (Fig.

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4a), and defining [20,21], where n is the number of sigma’s necessary for a certain yield, we find:

with being the voltage efficiency Fig. 4a depicts the DR and the terms it consists of, where sqrt(WL) (height of lower

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shaded area) is adjusted such that a constant DR is obtained over all processes. Using the inverse of (1):

the gate capacitance may be derived:

where a constant depending purely on technology. This capacitance is the gate capacitance of the transistor with a matching requirement to support a certain Dynamic Range (DR). Assuming a maximum signal frequency the Slew-Rate current to support a swing of at frequency is:

If this current is delivered by a driver with an efficiency than the power dissipation P follows:

The relationship described by (5) is depicted in Fig. 4b. The process data of Table 1 is used in Fig. 5, where power (P) is plotted against technology according to equations (5). As can be seen from this figure, the data follows the same shape as predicted by the curves in Fig. 4a and 4b. Expression (5) consists of 4 separate terms. The first term is process dependent only and is mainly dependent on oxide thickness. The second term is the product of voltage efficiency and current efficiency and reflects circuit “smartness”. The third term is the a result of yield requirements and the last term depicts the system needs. These components are also visible in Fig. 4b. If constant circuit smart-

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ness, yield and system requirements are assumed, power scales down with oxide thickness. From this point of view the future of analog design in deep submicron does not seem so bleak. The crux of the above assumption obviously lies in maintaining a constant product As can be clearly seen from Fig.3, will be negatively affected by the fact that is not scaling linearly with

5. EXPERIMENTAL DATA FROM LITERATURE As a test to the above derivation of circuit performance versus technology, data was gathered from 15 different 6-bit ADC’s [24-38]. An overview of this data is shown in Table 2. A figure of merit for 6-bit ADC’s can be defined as:

and is plotted against technology

in Fig.6. Assuming the majority

of the layout scales with (i.e. source and drain diffusion area’s, contacts and wiring) and (5) predicting the power P to scale with

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is expected to scale with as is shown clearly in Fig. 6. Compensating for this effect yields a technology independent figure of merit and is show in Fig. 6 by the open dots. The best fitting straight line indeed is independent of technology (i.e. has a slope of 0).

6.

DISCUSSION The derivation of Power Dissipation as a function of Technology scaling given in section 4 was done under the assumption of Matching and Slew-Rate being the dominant design issues. Fig. 7 shows the Power Estimate versus Technology based on this assumption (curve a). It also shows 2 other Power Estimates. Curve b) is based on the assumption Matching and Bandwidth are dominant. It can be shown that this requirement is basically independent of Technology and is currently Technology) still significantly less important than Bandwidth and Slew-Rate. Curve c) shows the required Power Dissipation to meet the Thermal Noise specifications. As is shown also by other authors [4,5], the required Power under this condition is currently still several orders of magnitude lower than curve a), but increases with smaller Technologies. Flicker Noise still has to be added to that, but Flicker Noise predictions for future technologies

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have proven to be hard. In any case, the effect of Flicker Noise is that curve c) will be raised dramatically and ultimately, Noise will be the dominant requirement as far as Power Dissipation is concerned. The question is how many Technology generations we are away from this point. Moreover, all of the above estimates are the required Power for one single Transistor meeting either the Matching, Slew-Rate, Bandwidth or Noise specifications. To obtain the Power dissipation of a complete circuit, one has to multiply this estimate with the number of Transistors (or rather branches) in the circuit having to comply with these requirements. Moreover, the estimated power dissipation also assumes no circuit tricks such as Dynamic Element Matching [39], Chopping

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[39], Auto-Zero Techniques [29, 34] or Averaging [40]. Use of such techniques can reduce the power requirements based on matching by as much as an order of magnitude and will lower curves a) and b) in Fig. 7 equivalently. Noise usually is affected for lower frequencies only and as a result curve c) remains more or less at its place. Although the effect on the current situation is not dramatic, it does however move the cross-over point several Technology generations earlier.

7.

SCALING OF WIRE-LINE ANALOG FRONT-ENDS Consider again the generic block diagram of Wire-Line AFE’s in Fig.l. The PGA and the LPF, if present, are usually primarily passive

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and do not contribute considerably to the overall Power Dissipation. The main blocks to consider are the Track & Hold Amplifier and the ADC. As discussed above, the ADC is a perfect example of a circuit dominated by Matching and Noise is much less of a problem. Therefor, ADC Power Dissipation will follow curve a) as a result of Technology scaling. Amplifier design is usually not affected by Matching and is usually governed by it’s Noise requirements. However, as the Load-Capacitance of the Track & Hold circuit is formed by the input capacitance of the ADC and hence is dominated by Matching requirements, also T&H Power Dissipation will follow curve a) as a result of Technology scaling. This leads to the conclusion that Wire-Line AFE’s will require less Power as a result of Technology scaling. Flicker Noise however, may change that picture at some point in the future.

8. CONCLUSION Analog design in deep sub-micron technologies has become a reality now and poses severe challenges to the circuit designer. Trends in technologies and their effects on circuit design have been discussed. It has been shown that specifically for Wire-Line AFE’s the power required for a certain Dynamic Range and Bandwidth decreases with minimum feature size. This is primarily due to the fact that Wire-Line AFE’s are dominated by the ADC design, which in turn is dominated by Matching requirements and Matching improves with thinner Oxides. The reduction of power dissipation with Technology scaling is based however, on a constant voltage and current efficiency. This is where the design challenge lies, as below predictions of the threshold voltage endanger that requirement.

REFERENCES [1] W. Sansen, “Mixed Analog-Digital Design Challenges”, IEEE Colloq. System on a Chip, pp. 1/1 - 1/6, Sept. 1998.

[2] B. Hosticka et al., “Low-Voltage CMOS Analog Circuits”, IEEE Trans, on Circ. and Syst., vol. 42, no. 11, pp. 864-872, Nov. 1995. [3] W. Sansen, “Challenges in Analog IC Design in Submicron CMOS Technologies”, Analog and Mixed IC Design, IEEE-CAS Region 8 Workshop, pp. 72-78, Sept. 1996.

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[4] Peter Kinget and Michiel Steyaert, “Impact of transistor mismatch on the speed-accuracy-power trade-off of analog CMOS circuits”, Proc. IEEE Custom Integrated Circuit Conference, CICC96, pp.333-336, 1996. [5] M.Steyaert et al., “Custom Analog Low Power Design: The problem of low-voltage and mismatch”, Proc. IEEECustom Int. Circ. Conf., CICC97, pp.285-292, 1997. [6] V.Prodanov and M.Green, “Design Techniques and Paradigms Toward Design of Low-Voltage CMOS Analog Circuits”, Proc. 1997 IEEE International Symposium on Circuits and Systems, pp. 129-132, June 1997. [7] W.Sansen et al., “Towards Sub 1V Analog Integrated Circuits in Submicron Standard CMOS Technologies”, IEEE Int. Solid-State Circ. Conf., Dig. Tech. Papers, pp. 186-187, Feb. 1998. [8] Q. Huang et al., “The Impact of Scaling Down to Deep Submicron on CMOS RF Circuits”, IEEE J. Solid-State Circuits, vol. 33, no. 7, pp. 1023-1036, July 1998. [9] R.Castello et al. “High-Frequency Analog Filters in Deep-Submicron CMOS Technologies”, IEEE Int. Solid-State Circ. Conf., Dig. Tech. Papers, pp. 74-75, Feb. 1999. [10] Klaas Bult, “Analog Broadband Communication Circuits in Deep Sub-Micron CMOS”, IEEE Int. Solid-State Circ. Conf. Dig. Tech. Papers, pp.76-77, Feb. 1999. [11] J. Fattaruso, “Low-Voltage Analog CMOS Circuit Techniques”, Proc. Int. Symp. on VLSI Tech., Syst. and Appl., pp. 286-289, 1999. [12] Daniel Foty, “Taking a Deep Look at Analog CMOS”, IEEE Circuits & Devices, pp. 23-28, March 1999. [13] D. Buss, “Device Issues in the Integration of Analog/RF Functions in Deep Submicron Digital CMOS”, IEDM Techn. Dig., pp. 423-426, 1999. [14] A. J. Annema, “Analog Circuit Performance and Process Scaling”, IEEE Trans. on Circ. and Syst., vol. 46, no. 6, pp. 711-725, June 1999. [15] M.Steyaert et al., “Speed-Power-Accuracy Trade-off in highspeed Analog-to-Digital Converters: Now and in the future...”, Proc. AACD, Tegernsee, April 2000.

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[16] J.Burghartz et al. “RF Potential of a 0.18-um CMOS Logic Device Technology”, IEEE Trans, on Elec. Dev. vol. 47, no. 4, pp. 864870, April 2000. [17] Abrishami et al., “International Technology Roadmap for Semiconductors”, Semiconductor Industry Assoc., 1999. [18] C.Hu, “Future CMOS Scaling and Reliability”, IEEE Proceedings, vol. 81, no. 5, pp. 682-689, May 1993. [19] B. Davari et al., “CMOS Scaling for High Performance and LowPower - The Next Ten Years”, IEEE Proceedings, vol. 83, no. 4, pp. 595-606, April 1995. [20] K. Lakshmikumar et al., “Characterization and Modelling of Mismatch in MOS Transistor for Precision Analog Design”, IEEE J. of Solid-State Circ., vol SC-21, no. 6, pp. 1057-11066, Dec. 1986 M.Pelgrom et al., “Matching Properties of MOS Transistors”, [21] IEEE J. of Solid-State Circ., vol 24, no. 5, pp. 1433-1439, Oct. 1989. [22] T. Mizuno et al., “Experimental Study of Threshold Voltage Fluctuation Due to Statistical Variation of Channel Dopant Number in MOSFET’s”, IEEE Trans. on Elec. Dev. vol. 41, no.11, pp. 22162221, Nov. 1994. M.Pelgrom et al., “Transistor matching in analog CMOS applica[23] tions”, IEEE IEDM Techn. Dig., pp. 915-918, 1998. [24] K.McCall et al. “A 6-bit 125 MHz CMOS A/D Converter”, Proc. IEEE Custom Int. Circ. Conf., CICC, 1992. [25] M.Flynn and D.Allstot, “CMOS Folding ADCs with CurrentMode Interpolation”, IEEE Int. Solid-State Circ. Conf., Dig. Tech. Papers, pp.274-275, Feb. 1995. [26] F.Paillardet and P.Robert, “A 3.3 V 6 bits 60 MHz CMOS Dual ADC”, IEEE Trans. on Cons. Elec., vol. 41, no. 3, pp. 880-883, Aug. 1995. [27] J.Spalding and D.Dalton,”A 200MSample/s 6b Flash ADC in 0.61m CMOS”, IEEE Int. Solid-State Circ. Conf., Dig. Tech. Papers, pp. 320-321, Feb. 1996. [28] R.Roovers and M.Steyaert, “A 175 Ms/s, 6b, 160 mW, 3.3 V CMOS A/D Converter”, IEEE J. of Solid-State Circ., vol 31, no. 7, pp. 938-944, July 1996.

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[29]S.Tsukamoto et al., “A CMOS 6-b, 200 MSample/s, 3 V-Supply A/D Converter for a PRML Read Channel LSI”, IEEE J. of SolidState Circ.,vol 31, no. 11, pp. 1831-1836, Nov. 1996. [30]D.Dalton et al., “A 200-MSPS 6-Bit Flash ADC in 0.6-1m CMOS”, IEEE Trans. on Circ. and Syst., vol. 45, no. 11, pp. 14331444, Nov. 1998. [31]M.Flynn and B.Sheahan, “A 400-MSample/s 6-b CMOS Folding and Interpolating ADC”, IEEE J. of Solid-State Circ., vol 33, no. 12, pp. 1932-1938, Dec. 1998. [32]S.Tsukamoto et al., “A CMOS 6-b, 400-MSample/s ADC with Error Correction”, IEEE J. of Solid-State Circ., vol 33, no. 12, pp. 1939-1947, Dec. 1998. [33] Y.Tamba and K.Yamakido, “A CMOS 6b 500MSample/s ADC for a Hard Disk Drive Read Channel”, IEEE Int. Solid-State Circ. Conf., Dig. Tech. Papers, pp.324-325, Feb. 1999. [34]K.Yoon et al., “A 6b 500MSample/s CMOS Flash ADC with a Background Interpolated Auto-Zero Technique”, IEEE Int. SolidState Circ. Conf., Dig. Tech. Papers, pp. 326-327, Feb. 1999. [35]I.Mehr and D.Dalton, “A 500-MSample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications”, IEEE J. of Solid-State Circ., vol 34, no. 7, pp. 912-920, July 1999. [36]K.Nagaraj et al., “Efficient 6-Bit A/D Converter Using a 1-Bit Folding Front End”, IEEE J. of Solid-State Circ., vol 34, no. 8, pp. 1056-1062, Aug. 1999. [37]K.Nagaraj et al., “A 700MSample/s 6b Read Channel A/D Converter with 7b Servo Mode”, IEEE Int. Solid-State Circ. Conf., Dig. Tech. Papers, pp.426-427, Feb. 2000. [38]K.Sushihara et al., “A 6b 800MSample/s CMOS A/D Converter”, IEEE Int. Solid-State Circ. Conf., Dig. Tech. Papers, pp.428-429, Feb. 2000. [39]R.v.d.Plassche, “Integrated Analog-to-Digital and Digital-to-Analog Converters”, Kluwer Academic Publishers, Dordrecht, The Netherlands, 1994. [40]K.Bult and A.Buchwald, “An embedded 240-mW 10-b 50-MS/s CMOS ADC in IEEE J. o7 Solid-State Circ., vol 32, no. 12, pp. 1887-1895, Dec. 1997.

Reusable IP Analog Circuit Design Jörg Hauptmann, Andreas Wiesbauer, Hubert Weinberger Infineon Technologies, Design Centers Austria GmbH Villach, Austria

ABSTRACT As ‘Time to market’ plays a crucial role for successful System on Chip (SoC) business, all chip companies try to drastically reduce development cycle times. Especially in analog circuit design this is an extraordinarily challenging target. Decreasing supply voltages along with the fast introduction of new sub micron technologies and increased performance and functionality would rather suggest an increase of design efforts. But making use of IP-reuse can help a lot to achieve development cycle time reduction. A review of possible reuse methods and comments on their feasibility are presented in this paper

1) INTRODUCTION In the last 10 years the development and introduction of new submicron technologies was very aggressive, as every other year a new technology was released. Today’s sub micron technologies allow integration of millions of digital gates on one silicon die, thereby creating complex SoC designs, which are requested by the market. Due to the cost saving potential, the market demands to migrate existing system solutions into the most recent and smallest technologies available, additionally trying to further increase the onchip functionality. 71 J. H. Huijsing et al. (eds.), Analog Circuit Design, 71-88. © 2002 Kluwer Academic Publishers. Printed in the Netherlands.

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Not only the size of the transistors is scaled down, but also the supply voltage has to be drastically reduced. Coming from 5V for 0.5u technologies and 3.3V for 0.35u technologies, the voltage has been reduced to 1.8V for 0.18u or even below for 0.13u and 0 . 1 u (see Fig.1). Deep sub-micron processes are optimized for digital circuits, making it more difficult for analog designers to shrink designs into more recent technologies. Down to a feature size of the threshold voltage decreased almost proportional with the supply voltage. For smaller feature sizes the threshold voltage decreases more slowly, leaving less room for linear analog voltage swing. In addition,

the specific capacitance is reduced and gds is increased. There are also some beneficial changes, such as increased speed and improved matching properties, which help to implement the analog functionality [4]. All these circumstances however, ask for changing building-block topologies in order to fulfill the specified performance. Since direct shrinking without architectural changes is almost impossible, maintaining an efficient reuse strategy is difficult. Many of these systems, such as xDSL transceivers, Ethernet PHY’s or first IF wireless receivers, need complex analog functions on the same die with complex digital circuits. In other cases the analog

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functionality is rather simple, e.g. in micro controllers one or two analog building blocks are sufficient. According to the complexity of the analog functions different levels of reuse can be defined: Section 2 deals with the reuse of complete analog front-ends (AFE) for SoC designs, basically showing that there is a huge challenge for the system architects and concept engineers to define several SoCs such that the same AFE can be reused without major changes. Another type of reuse, focusing on standard building blocks is described in Section 3. Here, the strategy is to design one analog building block with some overhead for reusability and make it available to many SoC designers. Very often the reused block is not optimized for the specific application and therefore consumes more power and/or more silicon area than necessary. Whenever the efforts in power consumption and silicon area for the analog functionality are much smaller than the efforts for the digital part, this approach seems to be feasible. Limits of this strategy, such as competitiveness, power optimization, performance optimization and number of necessary reuses are discussed. Section 4 describes possibilities of reuse for high volume state of the art designs, where, for reasons of competitiveness, compromises in performance or power consumption are not acceptable. Usually this AFE’s take a significant part in area and/or power consumption of the SoC. Also the performance is typically close to the physical limits of the used sub-micron technology. Thus optimum AFE design is required, challenging the designers to find efficient reuse possibilities. Within each reuse level we will be discussing different types of reuse. Plug & play is given, if a specific building block can be inserted in the design without changing anything inside the macro. Of course, there might be some programming features to adapt the module to the specific application. Essentially, the designer does not need a module specific know how. Mix & match reuse, on the other hand, is somewhat less restrictive. A module from a different design is taken as a basis and then adapted to the new requirements. The designer needs to know the building block very well and can change it at the required nodes, e.g. changing aspect ratios or bias currents. While plug & play reuse requires library type of modules with all kind of different views, mix & match reuse can be handled less formal and is based on interpersonal contacts towards IP reuse of the designer. In

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terms of quality assurance, mix & match reuse is much more person specific than plug & play reuse. The ‘time to market’ issue together with a limited number of available analog resources leads to a very strong demand for IP reuse in analog circuit design. Additional aspects towards cycle time reduction, such as the use of appropriate design tools and the need for innovative project structures are discussed in Section 5.

2) Reuse of complete analog front-ends for SoC In this section several examples on the reuse of complex Analog Front Ends (AFE’s) are presented. Several applications allow defining one analog module (front-end macro), which can be reused in all these applications in the same manner. A macro can be even standardized, like it is done for 10/100base-T Ethernet PHY’s. If a macro is once defined carefully by the system engineers, it can be used in several derivatives of a whole product family. An often proven example is the standard analog voice macro, which could be used in many different ISDN or plain old telephony services (POTS) applications. Only with a strict discipline in system definition and sometimes also draw-backs in digital design, a common AFE design specification is possible.

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Technology roadmap, supply voltage, functionality and power consumption are only a few parameters, which have to be aligned in all the different applications. Bug fixing problems may also occur, if several of these projects are done in concurrent engineering, together with the macro itself. Figure 2 shows the block diagram of a cable-modem AFE, designed for SoC usage [5]. It consists of two downstream channels, one upstream channel, a biasing block, an automatic filter tuning and a low jitter PLL, designed in 0.18µm CMOS with 1.8V power supply only. The architecture was defined in such a way, that its downstream part fits also a digital terrestrial TV receiver (DVB-T) SoC application [1], Since also the PLL, the central biasing and the filter tuning could be reused, a total reuse of 95% could be achieved. The most significant changes were the use of a different sampling rate (PLL) and a different filter order for the anti-aliasing filter. This AFE also fits quite nicely to the requirements of a hiperlan or LMDS SoC application, such that a reuse rate of more than 90% would be possible.

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Some system solutions may have similar architectures per definition, as it is in the family of xDSL products. Then it is possible to adopt the circuits with low efforts to the new system requirements. For example it was possible to design a complete analog front-end for HDSL2 within 2 months by making reuse of an existing ADSL analog frontend. Fig.3 shows the architecture of the ADSL frontend chip [2]. The main difference between the Analog Front Ends (AFE) for ADSL and HDSL2 from system point of view is the analog bandwidth, which is 1.1MHz for ADSL and 450kHz for HDSL2 respectively. Of course, the modulation schemes are different (PAM for HDSL2 and DMT for ADSL) and also the data rates. However, the requirements for the AFE’s are nearly the same: We need 14bit A/D and D/A converter’s and Harmonic Distortion better than 75dBc at half Full Scale Signals. In Table 1 the key perfomance date of both systems are shown.

As you can see in Table 1 the AGC has the same dynamic range for both AFE’s, so no change in the topology was necessary. We only reduced the powerconsumption due to the lower bandwidth. By simply reducing the bias current of the opamp no layout effort was necessary for this adaptation. The PREFI had to be redesigned for the lower cornerfrequency and therefore also a new layout had to be done. In theA/D converter, a order multibit sigma delta converter, we just redesigned the OTA’s of the integrators for the lower clockfrequency, thereby reducing the power consumption dramatically. Only minor layout changes were necessary. In the D/A converter - a 7 bit current steering DAC - we only optimized the power consumption by reducing the bias current of the opamp, so also no layout effort had to be spent. For the POFI the same effort had to be spent as for the

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PREFI. Also no change was necessary for the Linedriver, only a change in the supply voltage due to different output voltage swings. The reuse rate in this case was very high and came close to 80%. Reuse of AFE’s always requires the concept engineering, digital designers and analog designers to work closely together when specifying the system requirements. For all the mentioned products the necessary changes could be done in a very short time-frame, because the analog design team was not changed for one product family.

3) Reuse of analog standard building blocks In chapter 2 we briefly discussed the reuse of complete analog cores. Another approach for reuse can be found in the building blocks itself. Here we have to distinguish between standard building blocks, which have moderate performance and can be standardized, and high performance state of the art building blocks, which have to be designed in a particular way for each project. Standard building blocks, which can be designed as ‘ready to use’ modules are for example comparators, bandgaps, power-on-resets, standard PLL’s and oscillators. These basic plug & play building blocks need additional design effort in order to guarantee quality and reusability without the need of special knowledge of the block or even analog design knowledge. Due to the additional efforts, the reuse rate (# of reuses per technology) must be larger than 3 to benefit from this library element. Table 2 shows elementary building blocks and gives an estimation of their reuse number within the same process technology. The numbers are for a mid size SoC group with approximately 100 employees, including designers, concept engineers layout and product definition. Especially high potential for saving efforts can be seen for standard PLL’s and standard ADCs, used for example in micro-controllers as standard interface to the analog world.

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A 10 bit SAR ADC was designed once with a design effort of 15MM. This was the basis for 28 ADC modules with an average effort of about 2MM per module. Fig.4 shows the tree of all these converters. The converters were designed in different technologies by means of mix & match strategy, and were reused in most of these technologies several times in a plug & play manner by digital designers. All these modules have been delivered with very high quality – an important aspect for plug & play macros in digital projects.

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A similar strategy is possible for standard PLLs, used for generating appropriate clocking for digital IC’s. The design must have some overhead for flexible programming of the output in order to have more plug & play reuse possibilities of one dedicated design. Digital crystal oscillators and central biasing are candidates for almost 100% reuse. But again care has to be taken in the grounding strategies of the central bias, which may differ from application to application.

4) Reusable IP in high volume, state of the art designs In products designed for state of the art technologies (xDSL, cable applications, fiber optics), the probability of finding modules ready for reuse is low. The performance of the blocks has to be close to the physical limits of state of the art circuitry and the area and power consumption must be absolutely optimized in order to be competitive.

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Too many parameters besides the used technology, such as bandwidth, signal swing, appropriate load, supply voltage, open loop gain for opamp’s on one hand, or bit accuracy, signal bandwidth, clock rate, supply voltage for ADC’s and DAC’s on the other hand, have to match the specification. This makes it hardly possible to reuse blocks in different projects. But this doesn’t mean that there is no reuse at all and everything has to be designed from scratch. The IP in analog design teams is usually very high and can be reused in all different blocks. Opamps: The IP reuse in opamps is very high (about 70%), so that new opamps are ready including layout within 2 days. Mathematical documents and schematics from former projects ease the design of new opamps drastically, so that the design can be done within one day. 60% of this effort is simulations, which can be additionally reduced by using automatic simulation shells. The fact, that the pin structure of opamps didn’t change at all (2 inputs, 2 outputs for diff. opamps), automatic simulation shells for opamps can be always reused and are also suitable for the future. The IP in opamp design can be further programmed into commercial tools for automatic design including layout, but this is limited to fixed structures, which may change with decreasing supply voltage and in this way quickly limit the capability of such tools. Anyway, compared to the overall design effort of a project - about 40 to 60 MM initial design and 100 MM till production release - the contribution of opamp design effort is minor. Amplifiers, Filters: For designing amplifiers and filters, nearly the same mix & match approach can be used, only the IP reuse is in this case in average lower (40-50%) and the design takes about 1 to 2 men weeks. Automatic simulations are in this case also not very useful. Converters: ADC’s and DAC’s are usually the most critical parts in high performance products (e.g. xDSL, cable modem,...) and need a lot of design effort. New technologies with low supply voltages and state of the art specifications always require to find new circuit structures and circuit improvements. Nevertheless, in Fig.5 it can be seen, that there are only a few topologies of ADCs commonly used for telecommunication applications.

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Sigma Delta converters are widely used in high resolution, medium bandwidth applications, like ADSL, HDSL and SDSL, whereas 2 step flash sub-ranging converters are best suited for medium resolution (up to 11 bits) and high bandwidth, needed in VDSL, cable modem, DVBT and Gigabit Ethernet. Although each of the mentioned products has more or less different specifications, IP can be reused in a highly manner (60 to 70%). Once you have designed one converter type in a typical technology, the design effort and risks are significantly reduced for each additional converter of the same topology and technology. A typical IP reuse is described next: A 2step flash converter (Fig. 6) with 10bit eff resolution and 150MHz sampling rate with 1.8V supply voltage in technology was designed for a cable modem frontend, using the IP of a version with 5V supply. The identical converter could be reused afterwards in a COFDM project, a terrestrial receiver for digital TV (DVB-T). By introducing oversampling and adding digital filters, the same converter core was again suitable for VDSL with 11 bit effective resolution and 12 MHz

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signal bandwidth. Only the driver circuit and the reference buffers had to be optimized for the VDSL-requirements.

Fig.7) shows the layout of this converter type in a) technology 5V supply voltage and in b) technology 1.8V. Both converters have the same performance of about 11bit effective for 12 MHz signal bandwidth. The power consumption could be reduced from 250mW to 180mW and the silicon area is drastically reduced for 0.18u version.

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Using available parts of this converter and adapt them to new specifications (different bit resolution, different bandwidth) is a good mix & match approach to come easily to converters suitable also for a QPSK satellite-receiver (DVB-S) or Gigabit Ethernet. It is the same mix & match strategy, as for opamps, amplifiers or filters. Similar reuse is possible for multi-bit Sigma Delta converters, needed in xDSL products, with the need of adjustments to different resolutions and bandwidth. The reference design was a order multi bit sigma delta converter used in an ADSL-RT (Remote Terminal) chip, see Fig. 8 for the block diagram. A cascade 2-1 structure with 3bit resolution in the first stage and 5bit resolution in the second stage was chosen [3]. The analog bandwidth is 1.1 MHz with 14 bit resolution and a sampling frequency of 26 MHz. The first design was done in a technology with 5 volts supply, designed with an effort of 15 MM.

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Then this converter was redesigned for a HDSL2 application with 450kHz bandwidth in the same technology. Due to the smaller bandwidth the second stage resolution could be reduced to a 3 bit structure and also the sampling frequency was reduced to 16MHz, which resulted in a smaller area and lower power consumption of the converter. The design and layout effort for this converter was only 5MM. The next step was a redesign for an ADSL-COT (Central Office Terminal) application with a bandwidth of 250kHz. Again we changed the structure of the second stage to 4bit resolution and the sampling frequency to 4MHz. The effort reduced to 3MM. This two reuse designs where done in the same technology, the next step was a technology change from to for the ADSLCOT converter. Due to the very fast technology we could again change the topology. We increased the sampling frequency to 53MHz and we decreased the converter order from 3 to 2 with 3 bit resolution, resulting in a very small silicon area as you can see in Fig. 9. Since we made a technology change, each block had to be designed new, and also a completely new layout was made. The effort for this new converter increased to 7MM.

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As a summary, in table 3 several projects are listed to demonstrate the percentage of IP- and schematic reuse by means of mix & match. The percentage of reuse can differ from block to block from 5% up to 90%. Although the probability of 100% reuse of designed blocks is pretty low, 60% to 90% reuse capability in some projects is still very high by just using available IP, schematics, simulation shells, layout cells, testing facilities etc. and doing the new design by means of mix & match.

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5) Additional aspects towards cycle time reduction Up to now, the paper was focused on cycle time reduction in analog layout and analog design by reuse within these tasks. However, the product development speed can also benefit from improvement in tooling and speeding up of other tasks besides analog layout and analog design. High potential for tooling is in support and automation of standard design tasks such as: definition and execution of block specific simulation runs, efficient (higher level) modeling of analog building blocks, interactive back annotation of layout data and re-simulation, efficient modeling and simulation of substrate effects, thermal coupling of building blocks and packaging impact. Some of the tooling aspects target towards quality improvement, which can help to make the design first time right. Tools for automatic design of specific building blocks are not very efficient due to their restrictions to low circuit complexity, predefined circuit topology and the minor saving potential in design time. As a typical example an Opamp was discussed in section 4.

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For a typical project, Fig. 9 shows the percentage of effort for design, definition, architecture, layout and management with respect to the overall project effort. Design and layout makes about half of the product development efforts. Clearly, minimum cycle-time can be achieved only by attacking all tasks in the product development. For sure, a lot of IP reuse is possible in definition and architectural work.

Reuse strategies require good cooperation within a design team and between different design teams. Thus the human component must be considered as well. Team-building, motivation and information flow are essential to make reuse work. Besides reuse and adaptation work, each project should have some innovative parts. This helps to have motivated engineers and keep their know-how up-to date.

6) Conclusions Driven by technology roadmap, increasing system requirements and ‘time to market’ targets, reuse of analog IP is nowadays very important. But this does not only mean using plug & play analog modules or macros, it also means IP reuse with a so-called mix & match strategy. Architectural considerations should also not be neglected as an important factor in this strategy. The key enabler for IP reuse is the team spirit within a company and thus special attention

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has to be paid to interpersonal relations. Last but not least with all the reuse don’t forget to design new and innovative circuits in order to have innovative steps in the product roadmap and to keep up with the leading edge of mixed signal design.

7) Acknowledgements Special thaks to B. Seger for the contributions concerning layout, F. Cepl for providing the SAR ADC reuse-tree, R. Schledz for contributing table of reuse categories. Furthermore we appreciate the valuable discussions with M. Clara, Ch. Fleischhacker and Ch. Sandner.

8) References [1] M. Christian, et. al, “0,35u CMOS COFDM Receiver Chip for terrestrial Digital Video Broadcasting”, ISSCC 2000, page 76-77 [2] H. Weinberger, et. al., “A 800mW, Full-Rate ADSL-RT Analog Frontend IC with integrated Line Driver” CICC 2001 [3] A. Wiesbauer, et. al., “A 13.5 Bit Cost Optimized Multi-Bit Delta Sigma ADC for ADSL” , Proceedings of ESSCIRC, September 1999, pp 82-88 [4] K. Bult, "Analog Design in Deep sub micron CMOS", Invited Paper, Proceedings of ESSCIRC, September 2000, pp 11-17 [5] A. Wiesbauer, et. al.,“ A Fully Integrated Analog Front-end Macro for Cable Modem Applications in CMOS”, submitted to ESSCIRC 2001, unpublished.

PROCESS MIGRATION TOOLS FOR ANALOG AND DIGITAL CIRCUITS Kenneth FRANCKEN, Georges GIELEN Katholieke Universiteit Leuven, ESAT-MICAS Kasteelpark Arenberg 10, B-3001 Leuven, Belgium e-mail : francken [email protected] ABSTRACT The rapid progress in CMOS VLSI technologies together with the shortening time-to-market constraints of a competitive market and the shortage of designers necessitates the use of computer-aided design (CAD) tools for the automatic porting of existing designs from one technology process to another. Both horizontal and vertical technology porting are considered, where during vertical porting the intrinsically better capabilities of the new process can be exploited to either improve the performance of the circuit, or to keep the same performance while reducing power and/or chip area consumption. This paper presents CAD techniques for the automatic porting of both analog and digital circuits. Both the circuit resizing and the layout regeneration are discussed. For the circuit resizing, a scaling step is followed by a finetuning step. For the layout regeneration, a template-based approach is suggested. Experimental results illustrate the capabilities of the presented methods. Finally, the importance of proper design documentation will be stressed as a necessary means to facilitate easy technology porting. 1. INTRODUCTION Advances in very deep submicron CMOS VLSI integrated circuit processing technologies offer the possibility to integrate more and more functionality on one and the same die, enabling today the integration of complete systems that before occupied one or more printed circuit 89 J. H. Huijsing et al. (eds.), Analog Circuit Design, 89-112. © 2002 Kluwer Academic Publishers. Printed in the Netherlands.

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boards onto a single piece of silicon. An increasing part of these integrated systems contain digital as well as analog circuits, and this in application areas like telecommunications, automotive and multimedia among others. The growing complexity of these integrated systems in combination with the tightening time to market constraints, however, poses a serious challenge to the designers’ productivity. That is why new design methodologies are being developed, such as the use of platform-based design, object-oriented system-level design refinement flows, hardwaresoftware co-design, and IP reuse, on top of the already established use of CAD tools for logic synthesis and digital place & route. For analog circuits the basic level of design abstraction, however, is still the transistor level, although commercial CAD tool support for cell-level circuit and layout synthesis is emerging [1], allowing designers to concentrate more on the high-level architectural design issues as well as on the design of key critical blocks only. One serious problem that challenges both analog and digital designers is the extremely fast pace of the introduction of new deeper and deeper submicron CMOS technologies, at a rate which is even faster than the predicted technology roadmaps [2]. Before any new process can be used, however, a library of digital standard cells or selected IP blocks, such as a processor core or a memory generator, has to be developed and qualified. Developing this from scratch is very time-consuming and expensive, and delays the production use of the new process. At the same time, many existing analog and digital blocks are reused in new system designs for new applications, or in newer versions of an existing system that is redone in a newer process to reduce cost. The effort, however, that is needed to guarantee at least the same performance for these blocks in the new technology is not negliglible and is not at all regarded as very creative by designers. Computer-aided or even automated technology porting of integrated circuit blocks, both analog and digital, is therefore getting more and more attention today. Two types of process migration or process retargeting can be distinguished, as shown in Fig. 1. The first one is called horizontal porting where the same cell performance has to be obtained in a process with the same minimum transistor length but from a different foundry (e.g. CMOS of company ABC to CMOS of company EDF). The second one is called vertical porting where the same cell performance or better has to be obtained in a process with a smaller minimum transistor length from the same or another foundry (e.g. CMOS of company GHI to CMOS of company JKL). For the vertical porting, the intrinsically better

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capabilities of the new process can be exploited to either improve the performance of the circuit, or to keep the same performance while reducing power and/or chip area consumption.

This paper will discuss techniques for the automatic process porting (both vertical and horizontal) of both analog and digital cells. Both advantages and limitations will be presented. Section 2 will describe a possible flow for an automatic porting tool, distinguishing between the sizing retuning phase and the layout retargeting phase. Section 3 will then illustrate this for an analog design case (a modulator), while section 4 will illustrate this for the porting of a digital standard cell library. Guidelines or measures to be taken into account during design to facilitate an easy porting of that design later on will be discussed in section 5. Finally, conclusions will be drawn in section 6.

2. PORTING METHODOLOGY While digital circuits can often be retargeted to a new technology by geometrically scaling the layout, this procedure does not automatically guarantee success for analog circuits and not even for digital standard cells. This is due to the different scaling needed for different components in the circuit to keep at least the same performance. We can distinguish two steps in the technology porting task (see Fig. 2) : 1) the circuit tuning or resizing in which the device sizes and biasing are modified such that at least the same performance is obtained in the new process, and 2) the regeneration of the layout with the new layout rules and the updated device sizes. Since new technology parameters can influence the circuit performances, it is imperative to perform simulations at the circuit level to verify the correct performance of the circuit after tuning and after layout. Both the tuning and the layout steps will be further discussed in the next sections. Note that for a more complex circuit, like

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an analog-to-digital converter, this process will be performed hierarchically, first at the level of the converter and secondly at the level of the circuit blocks, as will be illustrated for the modulator later on.

In the remainder of this paper, we assume that the new technology process (called the target process) is compatible with the original process (called the source process) in the sense that we can use the same circuit topology. If this is not the case, for instance because the target process has a supply voltage that is much lower than the source process (e.g. 1.8 V versus 3.3 V), then new topology structures (e.g. low-voltage structures) will have to be used and the design becomes a completely new design instead of the process migration of an existing design. We exclude such cases here. The largest difference between the porting of a design on the one hand and the creation of a new design, be it by manual handcrafting or with a circuit and layout synthesis tool, on the other hand, is that, in the case of porting, a good reference design exists that serves as a basis to start from. This is not the case with a new design that basically starts from scratch.

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In the case of porting, the existing design has already proven to be working, and only needs updating in the sense of slight modifications to the device sizes and a regeneration of the layout tailored to the new layout technology rules and the tuned device sizes. In many cases the designers even prefer the new layout to look very much like the old one, which makes it easier for them to “read” the new layout. Therefore, advantage can be taken of both the existing device sizes and the existing layout to reduce the complexity of the porting task. This will be discussed in detail in the next section.

3. PORTING OF ANALOG CELLS 3.1. Sizing step For the porting of analog cells, we perform the resizing in two steps. Keeping the same topology, the first step is to perform an initial scaling of the original design, which gives us a starting point already close to the final solution in the target technology process. Following this step, a finetuning phase using optimization takes place to correct for possible violations of certain performance specifications or to reduce power and/or area while keeping the same performance. This is graphically illustrated in Fig. 3. Both steps can be automated, although they require some information from the original design.

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3.2.1. Initial scaling The first step taking place in the resizing process is an initial scaling. The existing netlist is linked to the new technology file and all transistor model parameters are updated. Then the biasing currents and transistor widths W (relative to ) are altered. If the supply voltage stays the same and bias currents and W's are scaled, we choose not to alter the bias voltages. The scaling factor is determined by writing down the current equations (we neglect the Early effect) under constant constraint. (Note that other scaling factors are obtained if other constraints are used.) If index A stands for the source process and index B indicates the target process, we get:

Or: with

and The minimal transistor lengths of the two processes are known. The parameters KP (both for n and for pMOS) and (consisting of and a term dependent on the body effect) are - on the contrary – typically not given in the technology file of deep-submicron CMOS processes. They can be obtained by simulating a test circuit in SPICE and then fitting the output data. For a digital circuit we can take but for analog circuits this is dependent on the sizing. We assume that the supply voltage is the same in both technologies and we assume that the transistors will be designed with the same gate overdrive voltage in the new technology, which is equivalent to making equal to 1. Hence, we get for the scaling of the transistor widths :

with The numerical value of these factors is different for nMOS and pMOS transistors. Capacitor values on the other hand are scaled depending on the function

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of the capacitor. To keep poles and zeros at the same frequency, their value is kept constant, and their area is updated according to the new perunit capacitance value. When the matching of the capacitors is important (like for sampling and integration capacitors in switched-capacitor circuits), the scaling is performed according to the new mismatch data (i.e. keep the ratio, but alter the size to meet the matching specification). This depends on the function of the capacitor in the original design and this information should therefore be available from the original designer (see section 5). Capacitors can cause even more difficulty during porting when the same type of capacitor implementation (e.g. poly-poly capacitor) is not present in the new technology. New CMOS deep-submicron processes will always be first available in the digital-only version. Analog extensions or analog options to this technology (like a poly/poly capacitor) will only be available in a later phase, if at all. Therefore, if the original design was implemented with poly-poly capacitors, these might now have to be replaced with metal-sandwich (MiM) capacitors (if linearity is important) or MOS gate capacitors (otherwise, because of small area). Similar problems can arise for other passive components like resistors and certainly for on-chip spiral inductors, which completely have to be regenerated based on the new technology data (especially the substrate resistivity is important).

Table 1 summarizes the initial scaling factors for different device parameters. Applying these formulas results in a sized circuit in the new process. The circuit is verified with numerical simulations (e.g. SPICE) which yields numerical data for all performances of concern. We can then compare these performances with the specifications to see whether they are all satisfied or not. If they are, the whole porting process has successfully finished, unless we want to additionally reduce power and/or chip area. In this case and in the case when not all the specifications are satisfied, we have to continue with the finetuning step.

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3.2.2. Finetuning step After the initial scaling, the next step is to simulate the circuit blocks, verify their performances and - if necessary - adjust some device sizes. This problem can be cast as an optimization problem in which an optimization algorithm minimizes a cost function. This cost function consists of terms that penalize any violations of the performance characteristics compared to the original design, and possibly in addition contains the implementation cost of the solution, i.e. power consumption and/or chip area, that has to be minimized. The optimization variables are the device sizes and biasing. The mathematical formulation is as follows:

with where is a penalty function that assumes a large value when performance does not satisfy specification and and are weighting coefficients. As compared to circuit optimization during synthesis [1], the optimization algorithm used here is preferrably a local method, since a good starting point is already available from the original design after the scaling. In addition, the method can even be speeded up using information from qualitative reasoning, which indicates in a tabular format, called dependency matrix, which parameter has to be improved to improve a certain performance [3]. This is close to the human way of thinking. The information in the table can for instance be generated using sensitivity analysis, and the different possible parameter changes are prioritized according to their impact on the violated specifications but also considering their (possibly negative) impact on already satisfied specifications.

3.1.3. Example : resizing of a

modulator

The approach is now illustrated for the resizing of a modulator designed for ADSL specifications from the Alcatel Microelectronics CMOS technology with analog options (poly-poly capacitor) to the digital CMOS technology of Alcatel Microelectronics. As no poly-poly capacitors could be used in this target process, a 5-metal-layer sandwich capacitor was chosen instead for sampling and integration capacitors.

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Circuit structure The ADSL specification requires an accuracy of 12 bits, but the goal of the prototype was set higher, namely a 13-bit accuracy. This means a dynamic range of 80 dB. The required signal bandwidth for ADSL is 1.1 MHz Furthermore, an oversampling ratio (R) of 24 was chosen for the original design, resulting in a sampling frequency of 52.8 MHz. A 2-1-1 (4th-order) cascade structure was selected for the original implementation as shown in Fig. 4. The complete block diagram is shown in Fig. 5. More details on this original design can be found in [4].

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In the original design, the size of the sampling capacitor of the first stage was determined by the required kT/C noise floor. From with a and OSR=24, the minimum size of C turned out to be 3pF. The capacitor size of the last stage was mainly determined by matching considerations. A matching of 1% was sufficient for these capacitors, so a unit capacitance of 0.25 pF was chosen, which has a matching that is smaller than 1%. The other capacitors were scaled down from the first to the last integrator. This means that the capacitive loads of all the integrators are reduced and the OTA’s were scaled down as

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well over the different stages. From behavioral simulations a minimum OTA gain of 80 dB, a closed-loop OTA pole of 190 MHz, a minimum slew rate of 400 and a maximum switch resistance of were derived. For the comparator the requirements for offset and hysteresis were maximum 100 mV and 40 mV, respectively. All building block specifications are summarized in Table 2.

We will now discuss the integrator and the comparator. We used 3 scaling factors to perform the initial scaling: scale_n (for nMOS transistors), scale_p (for pMOS transistors) and scale (for capacitances and bias currents). All three have been calculated using Table 1 as 0.54065, 0.51639 and 0.7 respectively.

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The integrator. Table 3 illustrates the specifications and the performances of the integrator building block in the and the process after the initial scaling step. As can be seen, the switch resistance specification is violated, and thereforee a second step, namely the finetuning phase, is necessary to correct for this violated specification. The finetuning is also used to reduce the power consumption of the integrator as Table 3 shows that there is margin on performances like GBW and slew rate. The schematic of the employed OTA, a gain-boosted differential folded-cascode, is shown in Fig. 6 (without common-mode feedback or biasing circuitry).

The sizes for the OTA, for the gain-boosting stages and for the switchedcapacitor integrator together with their scaling factors are shown in Table 4, 5 and 6 respectively. Note that – due to the finetuning – the effective scaling factors are different from the initial ones, precluding a simple geometric scaling. The bias current of the OTA was changed with a factor 0.7 from 2.5 mA to 1.75 mA. Due to the different parasitics of the metal-sandwich capacitor, Cload was changed from 18 pF to 12 pF. The 3 other integrators were scaled in the original design by factors 0.5, 0.35 and 0.35 compared to the first integrator (due to the sampling capacitances decreasing in each stage). The same factors were applied during the porting.

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Part of the qualitative dependency matrix that can be used to finetune the performance is shown in Table 7. Possible parameters to tune the

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performance are the bias current of the input transistors qualitative numbers in the table.

and the width as illustrated by the

An additional finetuning step was performed to correct for the violated switch resistance specification (see Table 2) and to additionally reduce the power consumption by means of the OTA bias current while keeping the performances at least equivalent to the ones in the original design. The scaling factors of the switches are determined to be 0.6758 and 0.6455 for nMOS and pMOS transistors respectively (see Table 6). This results in a switch on-resistance of like in the original design. As can be seen from Table 3, the limiting performance was the slew rate. If we want to make the slew rate in C035) equal to the original design ( in C05), the current can be reduced with 15% down to 1.5 mA. After comparing the simulated results of this final design with the performances of the original design, we can see that the tuned version performs at least equally well as the original design with a 40% lower power consumption for the integrator.

The comparator. Table 8 illustrates the specifications and the performances for both processes of the comparator building block. The schematic of the comparator is shown in Fig. 7. Table 9 summarizes all device sizes for both the source and the target process, together with the

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effective scaling that was applied. To avoid kickback noise, the input of the comparator is sampled on a 0.25 pF capacitor of which the value is left unaltered. The design variable Ibias was scaled from 100 to Like in the original design, the second comparator is a scaled version of the first one to reduce the load on the C2a clock signal; the third one is identical to the second one.

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existing layout as much as possible, a template-based approach is preferred in this case [5,6]. The layout then looks like the original layout, and also the parasitics will likely be similar (in a scaled sense). The template fixes the relative position and interconnection of the devices. The layout is then completed by correctly regenerating the devices (with the possibly updated device sizes) and the wires for the new process according to this fixed geometric template, thereby trying to use the area as efficiently as possible. These approaches work best when the changes to the circuit’s device sizes are not too large, so that there is little need for global alterations in the general circuit layout structure and hence the existing template can be used. Fig. 8 shows for example three different instances of the layout of a circuit generated with a template-driven layout methodology [7]. The main problem, however, as already stated above, is the automatic extraction of the template from an existing layout. Most template-based approaches published in the past [5,6] a priori generated a template for every circuit and stored that in some library, to be used during layout generation. If no such template is available, then it will have to be extracted from the layout, which is much more difficult. In practice, this will often be the case, unless the design has been documented properly, as will be discussed in section 5 later on.

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3.2. Layout step Analogous to the sizing problem, we want to take as much advantage of the original layout as possible to synthesize the new layout based on the new device sizes. This means that we want to generate the new layout as much as possible with the original layout as guide or reference, called a “template”. The preferred layout approach here is therefore “templatedriven” layout. There are however a few practical limitations. One of them is that, with the original layout at our disposal, we still are confronted with the fact that we must be able to automatically recognize all the devices of the original circuit and their interconnections on that layout. This is a very complex task that to some extent is also performed in LVS tools, but these tools don’t provide the full information needed to build up a template from an existing layout. Another practical inconvenience that one is likely to encounter when trying to recognize and resynthesize devices is a possible different technological implementation of certain devices. For analog circuits this can be the case for special resistor and capacitor layers available in one technology but not in the other. For both analog and digital circuits the number of metal layers (used for interconnection) can differ between the two processes. We will distinguish between the top-level layout or floorplan, which is needed for more complex cells, and the layout regeneration of the basic cells.

3.2.1. The floorplan For more complex cells like a modulator, the layout is generated hierarchically according to a floorplan that is defined first. The layout of the floorplan is an important step which has impact on all blocks that are part of it. Mostly, a lot of reasoning has preceded the final floorplan of the original layout. It is therefore only logical to reuse the original floorplan in the new target process, or more specifically : to keep the relative positions of the building blocks to keep the aspect ratios of the building blocks All of this should be done as far as practically managable.

3.2.2. Template-based cell layout generation Once the floorplan has been determined, the layout of the different blocks can be generated accordingly. In order to take advantage of the

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4. PORTING OF DIGITAL CELLS Digital standard cell libraries are a key element in every modern VLSI design flow. The most important issues are compactness and speed of the cells. Therefore, the performance of these cells and their layout are individually tuned. This job is not only complex, but also very timeconsuming considering the fact that this is mostly handcrafted work. Of course, this only needs to be done once for every technology. But also in the case where multiple foundries are used for reasons of multi-sourcing or where different flavors of the same process (e.g. with or without germanium option) are used, a new optimized library is needed. Let us also keep in mind that new and smaller feature-size technologies are becoming available at an increasingly faster rate [2] and that even “older” processes get tweaked over time to increase performance and yield. On the other hand, market pressure demands quick product introductions and the availability of the standard cell library is therefore often a bottleneck to adopt a new technology today. It would therefore be beneficiary to have very quickly access to a first version of the new library, generated by the computer from an existing previous library, and which can still be tuned manually afterwards if the need arises to squeeze out the last square micrometer. We will now discuss such a porting methodology for digital standard cell sizing based on a genetic algorithm. Since we use a SPICE –level circuit simulator for the transient delay simulations of the cells, accurate performance results are guaranteed. Our approach is optimization-based in combination with SPICE simulations, as this is the only approach that provides the necessary accuracy for the library cell performances similarly to what is normally used in hand–crafted sizing. The optimizer therefore iterates for different values of the device sizes to tune the cell’s performances to the required specifications while minimizing cost such as power and/or chip area. At each iteration transient SPICE simulations are performed to extract the desired performance characteristics (propagation delays, rise or fall times, etc.). To this end, parameterizable netlist descriptions for the different cells have been developed. These descriptions are standard SPICE syntax and the desired performances are also represented in each netlist as measured variables, which are automatically parsed by a tool implementing the porting approach. For the porting itself, a user can choose that the performances in the target process can be kept equal to those in the source process or they can be tuned by relaxing some specifications or making them more stringent. Of course, in practice, one will set the specifications – mainly in terms of

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delays – more stringent for the target technology; otherwise there would be no need for the new process.

4.1. Flow of the tool Fig. 9 shows the flow of the tool. The user provides the specifications of the performances, mainly delays and rise/fall times, that have to be evaluated by means of the measurement statements in the SPICE netlist. These specifications for the target technology can be chosen to be the same as in the source technology or other, more stringent, values can be specified. The properties of both source and target technology are specified in an ASCII configuration file. The tool then returns the optimum cell sizes that ensure that every performance satisfies its specification.

As optimization algorithm guiding the parameter selections we employed the differential–evolution genetic–based program described in [8], which we altered slightly. It is a genetic algorithm that searches for a global optimum and uses continuous parameter values. Among the changes compared to [8] are the inclusion of parameter bounding and stop criteria. Every population member in the genetic algorithm is represented as shown in Fig. 10. The different genes represent the lengths and widths of the transistors in the circuit. These parameters are passed to the simulator which performs the requested analyses. The simulation results together with the specifications are then used to evaluate the fitness of the

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member by means of the following cost function :

This is a minimax problem formulation. The algorithm will try to minimize the cost, which is equal to the maximum normalized deviation of a performance from its specification. Each performance is thus normalized to have an equally important influence. Also, a weight factor W is included which is different when the specification is met (100) or not (100000). Note that with W = 100 and a cost threshold stop criterion of 1, a tolerance of 1% is achieved. It is, however, also possible that the genetic algorithm proposes bad combinations of parameters (e.g. out of range). Then, a “high” cost is assigned (e.g. 1e+8) to such solutions. 4.2. Digital standard cell porting examples We will now demonstrate the capabilities of the tool to automatically find the scaling factors for the transistor widths (nMOS and pMOS) that are necessary to migrate digital standard cells from one technology to a newer one. To have an optimal performance, the scaling factors are not necessarily the same for each type of cell. The source technology is a CMOS process and the target process has a gate length. Since all cells have minimum gate length, we don’t optimize the transistor lengths. A first experiment keeps the performance specifications of the original cell. We migrate a simple inverter cell from a CMOS to a process, where we try to keep the performances. So, the question is: how small can the transistors be sized in the technology as to still have the same performance as in the technology? Note that the scaling factor for the transistor length is 0.714 (1/1.4). The results

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are given in Table 10, where a comparison is made with actual (“real”) data of cells that were hand–crafted by the manufacturer in the same target technology process. The final cost function value is given together with the time taken by the tool and the number of generations of the genetic algorithm. Although a genetic algorithm is very well suited for parallel execution, the numbers presented here are the results of execution on a single host computer (SUN Ultra 30). We can conclude from the table that the optimized performances are within the given tolerance of 1% (0.5% for low–to–high (PLH) and 0.2% for high–to– low propagation delay (PHL) respectively). Nevertheless, the optimized parameters – the nMOS and pMOS scaling factors – deviate by as much as 62 % from the “real” values that we had in the manufacturer’s library. This is, of course, due to the fact that the speed specification for a standard cell library in practice is always increased when moving to a faster technology process; otherwise no advantage of the faster process would be taken.

Hence, in the second experiment, also the speed specification is increased. In Table 11, we present the results of an experiment similar to the first but where the target performance specification is entered to be equal to the real simulated target cell specifications from the manufacturer’s hand–crafted library. This is done for three different cells (inverter, 2–input and, exor). Again, a comparison has been made between results from the tool and the actual cell data. It is clear that the scaling factors now match better with the real values. Nevertheless, they deviate by 3 to 8%, even though the optimized performance is within 1% of the specification (as requested). This is likely due to extra design margins that are taken in a real design. The above mentioned experiments show that the migration flow for digital standard cells works and that the user can arbitrarily set the target specifications. The performances of the optimized cells are within the accuracy specified by the user (1% in our example). Also, the optimization times are well within reasonable limits since the library migration will be done only once for every new process. In addition, we didn’t make use of parallel execution on different host computers, which would speed up the optimization even further. Therefore, by making templates of the library cells only once, a fast migration at the level of

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cell sizing is possible for every subsequent technology. Again, it is assumed that the cell topology does not change when porting to the new process.

5. DOCUMENTATION FOR PORTING In order to allow an easy porting, the original design should be somehow “prepared” for the porting. It is difficult for another designer unfamiliar with the previous design, and even more so for a computer tool, to understand all the details, the intent and the little “twists” in the mind of the original designer when completing his/her original design. Therefore, to facilitate porting, a minimum amount of documentation should be generated by the original designer and should be delivered together with the design itself. This small initial overhead certainly pays off on the long run for the company when the design has to be ported to other processes later on. And it is only the original designer who has the information that is needed for this and who therefore has to provide this. Besides, “design flow capturing” tools that operate in the background could be set up here to help the designer in this job. Also, standardized verification tools that generate a standardized datasheet for each circuit would certainly be useful here. As a start in this discussion, we will specify here what kind of information should be included in the documentation accompanying the original design. For a design to be portable, we propose the following mandatory set : 1. System specifications + derivation of the specifications of each block (top-down) in order to ensure that the system will work, together with other essential specifications/performances 2. Top-level architecture + external PIN connections + the topology of

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all blocks in the hierarchy + their interconnections to form the system ( = hierarchical netlist) 3. The circuit sizes for each block together with a list of the critical devices, possible problems and the relation between important performances and the device sizes having the most impact on these specifications/performances (e.g. the GBW increases with increasing channel width of the input transistors, etc.) 4. Simulation or verification method, applied inputs, outputs to be checked, how to verify that the specification is met, simulation examples (graphs) We understand the extra effort needed for the original designer of the circuit to document all this information in an orderly fashion. On the other hand, almost all of the information in the list is generated at some point of time in one or another file during the course of the design anyway. Moreover, the designer him/herself can also benefit from this documentation, either for a next design or for some kind of reporting. Finally, we want to point to the fact that documentation will play an increasingly important role in the trend towards complex integrated systems-on-a-chip. Organisations like the VSI (Virtual Socket Interface) Alliance [9] have acknowledged this need and have proposed an open interface to make design re-use possible. The circuit that is being reused is then a so-called VC (Virtual Component) and will have to be accompanied by a minimum standardized set of documentation. Retargeting benefits from the same documentation.

6. CONCLUSIONS This paper has presented CAD techniques for the automatic horizontal and vertical porting of both analog and digital circuits. Both the circuit resizing and the layout regeneration are discussed. In both cases, advantage is taken as much as possible of the existing design as a reference to start from. For the analog circuit resizing, a scaling step was followed by a finetuning step. For the layout regeneration, a templatebased approach was presented. For the digital standard cells, a simulation-based optimization approach was adopted. Experimental results have illustrated the capabilities of the presented methods. Also the importance of proper design documentation has been discussed as a necessary means to facilitate easy technology porting. Future work will have to concentrate on improving the methods and integrating them into a flawless automated environment for both analog

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and digital circuit porting. Also the role of documentation and techniques to minimize the overhead of design for reuse will have to be further investigated and implemented.

ACKNOWLEDGEMENTS This work has been supported in part by the ESPRIT project NAOMI and the IWT project FRONTENDS.

REFERENCES

[1] G. Gielen, R. Rutenbar, “Computer-aided design of analog and [2] [3] [4]

[5]

[6] [7]

[8] [9]

mixed-signal integrated circuits,” Proceedings of the IEEE, Vol. 88, No. 12, pp. 1825-1854, December 2000. “International Technology Roadmap for Semiconductors,” 1999 version + 2000 update, http://public.itrs.net. K. Francken, G. Gielen, “Methodology for analog technology porting including performance tuning,” proceedings International Symposium on Circuits and Systems (ISCAS), June 1999. Y. Geerts, A. Marques, M. Steyaert, W. Sansen, “A 3.3 V 15-bit ADC with a signal bandwidth of 1.1 MHz for ADSL applications,” IEEE Journal of Solid-State Circuits, Vol. 34, No. 7, pp. 927-936, 1999. G. Beenker, J. Conway, G. Schrooten, A. Slenter, “Analog CAD for consumer ICs,” chapter 15 in “Analog circuit design” (edited by J. Huijsing, R. van der Plassche and W. Sansen), Kluwer Academic Publishers, pp. 347-367, 1993. H. Koh, C. Séquin, P. Gray, “OPASYN: a compiler for CMOS operational amplifiers,” IEEE Transactions on Computer-Aided Design, Vol. 9, No. 2, pp. 113-125, February 1990. R. Castro-López, M. Delgado-Restituto, F. Fernández, A. Rodríguez-Vázquez, “Reusability methodology for IC layouts,” proceedings Workshop on Advanced Mixed-Signal Tools, ESDMSD Mixed-Signal Design Cluster initiative of the European Union, March 2001. R. Storn, “On the usage of differential evolution for function optimization,” in NAFIPS, pp. 519–523, 1996. Virtual Socket Interface Alliance, several documents including VSIA Architecture Document and Analog/Mixed-Signal Extension Document, http://www.vsi.org.

Part II: High Speed D/A Converters Michiel Steyaert

Introduction The never ending story of better performances has resulted today in the development of DA converters with conversion rates as high as 1GHz, bit accuracies in the range of 10 bit and all that in CMOS technologies. In this section, the trends, limitations and design issues for high speed CMOS DA converters is covered. The first paper addresses the different effects on the degradation of the well known DAC parameters such as INL, DNL and SFDR. The design of high speed DAC requires a delicate trade-off between the different design specifications, both towards static and dynamic specifications. The second paper discusses the effect of the system trade-offs and the resulting specifications of the DAC. Shifting more to the digital area is anyhow the trend, but regarding the sometimes high ‘impact factor’ of systems on the DAC performances, such as wireless systems, results in unacceptable speed accuracy power trade-offs. A clear optimization on high level and the different building blocks can save drastically the power in the whole system The next two papers study design cases of current DAC’s. Both are heavily based on the impact of transistor mismatch considerations and careful layout floor-planning to obtain the static performance. Detailed analysis of the different design issues to achieve dynamic performances in current DAC architectures have resulted in high performance high speed DAC’s. The fifth paper investigates the use of track-and-hold output topologies to avoid retiming and latency issues in the current DAC’s Finally a design case of a charged-based architecture is discussed. Due to the inherent passive charge-redistribution architecture, DAC’s with very low glitches can be achieved. The limitations are however again back in 113

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the design of a high performance operational amplifier where any slewrate effect should be avoided. So in the trends of the never ending story of better performances, we can summaries it in the four tens: we are on track towards 10 bit CMOS DAC’s, 10 GHz conversion speed within 10 years from now, hopefully with a power drain of 10 mW. The last one is really questionable but we can only hope...

Introduction to High-speed Digital-to-Analog Converter Design Rudy van de Plassche Broadcom Netherlands BV Bunnik Abstract

In this paper limitations in static linearity (INL, DNL) and dynamic range (Effective Number of Bits, ENOB’s) of digital-to-analog converters due to clock jitter, finite linearity, component matching and switching uncertainty will be calculated. Secondly quantization error spectra are analyzed and the influence on distortion and cross modulation effects is derived. Practical design examples will be discussed.

1

Introduction

Digital-to-analog converters are the link between digital signal processing and the analog world. In Fig. 1 the different signal conditions present in a converter are given. From Fig. 1 it is seen

that a digital signal is a discrete time, discrete amplitude signal. 115 J. H. Huijsing et al. (eds.), Analog Circuit Design, 115-150. © 2002 Kluwer Academic Publishers. Printed in the Netherlands.

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An analog signal is a time continuous, amplitude continuous signal. To convert from digital into analog a signal reconstruction takes place. Sampling limits the maximum frequency range to the Nyquist frequency. A filtering operation is needed to limit the maximum signal frequency and avoid aliasing. Amplitude quantization discretizes the amplitude into well known steps. A quantization error is introduced. This quantization error limits the dynamic range of a system. The quantization error depends on the number of steps used in the system.

2

Ideal converter

In an ideal converter the sampling time is fixed and constant and does not introduce any error. Only the amplitude quantization error causes a limitation to the system. Because all errors discussed in this paper will be referred to the quantization error this error will be calculated first. In Fig. 2 the quantization of a signal at the sampling moment to the amplitude level is shown. The quantization error determines the error between the analog signal and the quantization level In the lower part of Fig. 2 the probability density of the error over the quantization interval is shown. Here is the quantization step of the converter. The uniform probability error function shows that there is no correlation between the signal frequency and the sampling frequency. The quantization error power can be calculated using as the quantization step. The average quantization error power becomes: Solving this equation we get the well known result:

Applying a sine wave with a peak-to-peak amplitude of to an n-bit system, then the RMS signal am-

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plitude can be calculated as:

The dynamic range (Signal-to-Noise ratio) of the n-bit system becomes:

Inserting values for amplitude and quantization error we get:

Converting this into Decibels we obtain:

These results give a global analysis of quantization error. To obtain a better knowledge about what quantization errors are an analysis of the quantization error spectra will be given. This model can be applied to analog-to-digital and digital-to-analog converters.

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2.1 Quantization error spectra Suppose a quantized ramp signal shown in Fig. 3 is reconstructed then the error signal can be determined as a sawtooth with amplitude and repetitions as shown in Fig. 4. Note that at this moment ONLY AMPLITUDE QUANTIZATION is used. SAMPLING of the signal will be performed at a later stage. By shifting the DC value of the signal as shown in Fig. 4 then a Fourier analysis of that signal gives only odd harmonics described as:

In case a sine wave is applied then the output spectrum becomes

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more complex. From [1] we obtain:

Simplifying this equation we get:

With

defined by:

The amplitude of the harmonic with index is given by from equation 10. The quantization error spectra can be plotted using this equation. In Fig. 5 a spectrum with up to 30.000 odd components of a 10-bit quantizer is shown. The spectrum slowly decreases with increasing number of harmonics and has a length of infinity. The spectrum shows furthermore peaks that can mathematically be determined to occur at the harmonic of the input signal. A more detailed part of the frequency spectrum of the same quantizer of Fig. 5 is shown in Fig. 6. Lower order odd harmonic amplitudes can be estimated from this figure. Third harmonic is about 90 dB down with respect to full scale. A relation between for example the third harmonic component and the number of bits of a converter needs some mathematical manipulations that go beyond the scope of this material. The result for the third order distortion, however, can be expressed as: As a result a 10-bit converter has a third order distortion component 90 dB down with respect to full scale. Increasing the

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resolution of the converter with 1-bit, then the distortion component reduces with In Fig. 7 the quantization error, the third order distortion component and the intermodulation component (IM3) as a function of the number of bits are shown. The

IM3 products will be described in one of the following sections.

2.2 Amplitude dependence of the quantization components So far the calculation of the quantization spectra has been performed for signals exactly fitting within the quantization levels. In case a signal varies within a quantization level then the total spectrum changes. Suppose that the amplitude varies as [0 1], then equation 10 is modified into:

With Taking as an example p=3 and p=31 then the result for a 6-bit converter is shown in Fig. 8. This figure (8) shows that depending

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on the signal amplitude distortion components can be reduced to zero. Maximum third order distortion is found roughly at the quantization levels.

2.3 Multiple signal distortion At the moment two or more signals are quantized, then it is important to know what the so called cross-modulation or intermodulation products (IM3) will be. A formula for two input signals will be given. Suppose we apply the following signals

Using the previously described analysis and using some mathematical manipulations we get for the cross-modulation:

Applying signals with equal amplitude then the intermodulation product changes with the number of bits of

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the converter as This means that with an increase in resolution of 1-bit, the intermodulation product will decrease with 12 dB. Again this needs some mathematical manipulations of the equations to obtain this result. Quantization of analog signals results in errors that are correlated with the signal mostly as odd harmonics of the signal. The analyzed spectra show basically an infinite number of spectral components.

3

Sampling of a quantizer

In a converter a quantization and a sampling operation is performed as has been shown in the introduction. At the moment the quantizer spectra are sampled using a sampling frequency then a large distortion called aliasing occurs for all frequencies outside the band As a result of this aliasing all higher order frequency components are shifted to this baseband. This operation is shown in Fig. 9. This figure shows a single sided frequency picture of the sampling operation. From this figure

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it can be seen that if a correlation between the sampling frequency and the signal frequency exists, then distortion products will add, while in the case of uncorrelated sampling and signal frequencies these components fall in between the harmonics and result into a ”noise-like“ quantization error. Increasing the sampling frequency will result in a reduction of the amplitude of the quantization error components, however, the total power of all the error components in the baseband never exceeds

4

Non-ideal converter

Practical converters show deviations from the above given analysis. Especially the finite matching of practical elements such as resistors and transistors show a big influence on the maximum performance of a converter. These non-idealities can be split up in timing errors and non-linearity errors. The timing errors can be random due to noise and jitter introduced by the sampling clock and systematic errors mostly introduces by the layout of a converter. These systematic errors must be avoided as much as possible, but at a certain moment are unavoidable. Sometimes a change in converter architecture is needed to avoid systematic timing errors. In a layout for example an interconnection wire of about 100 introduces a time error of about 1 psec. At high signal and clock speeds these errors will introduce glitches and/or mostly third order distortion products of the signal frequency. First we will start with timing errors.

4.1

Timing

Timing in a practical system is not ideal. Timing errors can be: Random timing errors due to clock jitter or noise on clock circuits Systematic errors due to layout, differences in wire lengths or the system architecture

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Random timing errors result mostly in an increase of quantization errors at high signal frequencies. Systematic errors result in distortion that in term results in a reduction of dynamic range. Mostly systematic errors are architecture or layout dependent. Wires from the sampling clock to the bit-switches can have different lengths in case a layout is not carefully designed.

4.2 Random timing errors In practical systems sampling clocks show a certain instability called clock jitter, while additional to this clock jitter noise in the clock distribution circuitry can increase this jitter. In Fig. 10 the influence of clock jitter on the sampling of an analog signal is shown. The influence of this clock jitter on the amplitude

quantization of an analog signal can be calculated. From Fig. 10 it is seen that clock jitter only has influence on the amplitude quantization at high input frequencies. This random clock jitter exhibits itself as an extra quantization error and thus reduces the dynamic range of the converter. This effect will be calculated in case of an n-bit converter with quantization steps. A sine wave will be applied as signal because it is the highest frequency possible in a band limited system avoiding aliasing. With we obtain after differentiation:

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With The step size

and A the amplitude of the signal. of the converter equals:

A quick indication about the peak-to-peak clock jitter can be obtained stating that the amplitude uncertainty may not exceed the quantization step we obtain after rearranging of the equation:

The worst case condition is found if tion simplifies into:

so this equa-

With MHz and n = 10 bit, the peak-to-peak clock uncertainty must be below 65 psec. However, we want to know the influence of the RMS clock jitter on the Effective Number Of Bits (ENOB’s) of a converter. With ENOB defined as:

Here is the ”measured“ effective resolution of a converter in dB and includes all the non-ideality effects of a practical converter. The error power due to jitter equals: In this power equation the slope of the signal determines the sensitivity of the converter to clock jitter. We can average this slope over the signal period and get:

Inserting 26 into 25 gives:

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With The total error power due to quantization and jitter becomes:

Where

defined as:

Using equation 28 we can rearrange equation 29 and obtain for

We will call the sample clock phase noise (rms). The dynamic range of the converter due to clock jitter noise power changes according to:

The reduction in ENOB’s as a result of jitter then equals:

If then the ENOB’s reduce with bit or 3 dB. The ratio between the clock jitter and the signal frequency can be calculated as a function of the number of bits in the converter. In Fig. 11 the decrease in ENOB’s as a function of is shown for converters having a resolution between 4 and 16 bits.

4.3 Glitches Glitches can be seen as a systematic error occuring in the reproduction of an analog signal via a digital-to-analog converter. Especially when a binary weighted converter architecture is used and a small signal around a major carry transition is converted, then a glitch can be produced. As an example of this phenomenon

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a binary weighted converter with offset binary coding reproducing an LSB code step at the 011111.. to 100000.. transition. At this code transition the MSB value will be switched on or off at the same time that all other values are switched off or on. In case switching time errors occur, then the output code can reach full scale (1111..) or all zeros (0000..) during a short period of time. This produces an unwanted signal glitch. Filtering off this glitch will reduce the amplitude, but will NOT reduce the amount of distortion produced by this glitch. Suppose that the MSB switch is faster in switching then all the other bits, then the influence of the glitch energy can be calculated. With is the LSB step size, then half scale equals The glitch area becomes:

With

is the sample time, then the LSB area is found as:

Suppose that an acceptable reduction in dynamic range is obtained when the glitch energy equals the LSB energy then we have:

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With and n = 14 bits we obtain that psec. Such a small value indicates that an accurate layout of the converter concerning the switching is needed. Changing the architecture into a step by step switching of the information having 1023 switches with unit currents for example in a 10-bit converter avoids the glitch problem. However, at high output frequencies close to the Nyquist frequency a switching time uncertainty is introduced by the layout of a converter. Every single switch can be seen as having a certain switching uncertainty compared to an ideal switching system. As a result the reproduced signal moves in time giving after filtering a third order distortion. Again this third order distortion depends on the signal frequency and the timing accuracy that can be designed in the layout.

4.4

Linearity

In a non-ideal (practical) converter the quantization steps have a limited accuracy because of finite matching of components. This results in an Integral Non-Linearity (INL) and a Differential NonLinearity (DNL) of the converter. The INL is important for large signals because it determines the overall linearity, while the DNL of a converter is important for small signals [2]. Basically the DNL determines the accuracy of the quantization step from quantization level to quantization level. This non-ideality results in distortion of the signal and thus in a reduction of the dynamic range. Mostly the INL is specified as ± LSB. DNL depends on the construction of the converter but is at maximum 2*INL in case of a binary weighted converter. In Fig. 12 the INL and DNL characteristics of a converter are shown. Note that sometimes codes are missing giving a large DNL or even the output signal can step back with an increase in digital input code. Nonmonotonicity of the converter is observed at that moment.

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4.5

Matching accuracy of converter elements

When designing converters with resolutions from 8 to 16 bits the following question arises: How accurate do I need to design the unit currents or resistors to obtain a certain INL and/or DNL? To answer this question a Matlab program has been used to obtain information about the INL and ENOB’s of converters. The converter has been modeled using unit current sources or unit resistors to determine every quantization level. In Fig. 13 the results of this program for a 10-bit converter are shown. A total number of 1000 ”converters“ have been analyzed using this program. At the same time the ratio between the largest distortion component and the signal component defined as Spurious Free Dynamic Range (SFDR) is analyzed too. The matching of the unit elements has a of 2.5 % in this simulation. In Fig. 14 a histogram of the converters as a function of the INL is shown. This

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histogram shows that of the converters reaches ± LSB INL and are within 1 LSB INL. In the range of 8 to 12 bits of resolution of a converter identical simulations have been performed. As a result of these simulations Fig. 15 shows the relation between the required unit element matching and the number of effective bits (ENOB’s). Results for and yield of a converter are shown too. It must be noted, that in case a segmented or binary weighting in a converter is used, then the matching accuracy between the segmented elements or the binary weighted elements increases according to the value or the amount of elements used to obtain the required weight. In practice mostly a number of elements is put in parallel to increase the unit value. As a result the accuracy increases with The finite matching of components in a converter results in a limited linearity of such a converter. A very useful relation between INL and reduction in ENOB’s of a converter is proposed. The finite INL results in a systematic error signal that introduces

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distortion. Because the INL is directly related to the LSB of a converter the distortion introduced will be related to the quantization error using a simple ”fitting“ model. Identical to what has been done with clock jitter the dynamic

range of a converter changes according to:

Here is the peak to peak systematic signal distortion component due to finite converter accuracy. This value gives the worst case condition, because it is not known how the INL curve as a function of the signal value behaves. A Fourier analysis would give exactly the value of the different distortion components and in that way a better estimation of the total distortion can be obtained. To verify the model the ENOB reduction will be calculated. The ENOB’s reduce with:

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This model is valid for yield of converters. In Fig. 16 the simplified model is inserted into the ENOB simulation using Mat Lab. In this figure only a limited range of INL is shown. However, the model has been verified over larger variations of INL. In Fig. 17 the worse case reduction in ENOB’s of a converter as a function of the INL is shown. This graph is very usefull to get quick information about the converter resolution and the linearity.

5

MOS matching models

Designing converters with unit elements, then the matching accuracy between the elements as a function of the number of bits is known. A 10-bit converter needs for yield and ± LSB INL a matching of 2.5 %. In case we want to increase the yield to then the matching must be increased to 1.25 %. In MOS technology information about matching of components is available as a function of technology and a limited amount of model parameters

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[3]. Suppose the MOS devices axe in saturation then:

The first condition that will be considered is: 1) Equal Drain Currents so:

This results in:

Defining small difference between the two MOS devices using:

We obtain:

Working out this equation we obtain:

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The matching of an MOS pair is equally influenced by the threshold matching or by the slope mismatch if:

In practical MOS technologies

In Fig. 18 the threshold matching of MOS devices having a by device size versus the gate oxide thickness of the technology is shown. From this figure it can be seen that the mismatch reduces with decreasing gate oxide thickness. The validity of this relation has been proven even for submicron technologies. The

gain mismatch of MOS devices versus gate oxide is shown in Fig. 19. From this figure we see that the gain mismatch is nearly independent of the gate oxide thickness. This means that

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with increasing drain current the mismatch of a differential pair or a current mirror will become independent of technology limited). If

then In practice this means that the current density in the MOS device must be below a value corresponding with the given gate-source voltage. The calculated offset is valid for MOS devices with a by gate size. Increasing the size of the devices it is known from literature that the offset decreases with increasing device area or:

In Fig. 20 the measured threshold mismatch has been plotted against the device size of an MOS transistor. Increasing the size reduces the mismatch according to equation 57. The designer has the option to size the devices regarding offset. In a

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practical situation the device size variations are limited. A 1 to 100 size variation is still possible, however, the capacitance of the devices increases. This results mostly in an increase in biasing current and thus power. 2) Equal gate-source voltage:

With the devices in saturation we obtain:

Solving these equations for a difference in drain currents:

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Inserting small difference between the drain currents using:

we obtain

Using a first order approximation for the square root we get:

The variable

can be replaced by:

Then we obtain for the current mismatch:

At small current densities we have that:

The current mismatch at small current densities can be simplified into:

At large current densities the matching is determined by:

Note that the calculated current offset is again valid for 1x1 sized devices! When the size of the devices is changed then the offset varies depending on of the gate area.

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The final mismatch a small current densities and device size dependent becomes:

In case of large current densities we obtain finally for the current mismatch:

In Fig. 21 the measured gain mismatch versus the device size WL is shown. The designer has again the option to scale the

device size to reduce the current offset.

6

Digital-to analog converter architectures

In this part different architectures to construct digital-to-analog converters in CMOS technology will be given. What architecture will be used depends on the application field and the choices a designer makes. Only a few examples can discussed. Output signals can be a current or a voltage. Mostly differential structures

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will be used producing the converted output signal and its complement. In a differential operation of a system mostly a very good symmetry exists resulting in the absence of even order distortion components in the output signal and in the quantization error. Differential systems can furthermore apply a twice as large output signal to the load. This is important in CMOS submicron technologies that have smaller breakdown voltages (about 1 V). Single ended systems on the other hand might show odd and even distortion components at half the output swing. A large output swing is preferred to improve the dynamic range in a system application. Cross-talk from other system parts may limit the dynamic range in such an application. Differential operation improves the performance by rejecting part of the cross-talk.

6.1

10-bit current mode digital-to-analog converter

Suppose we want to design a 10-bit digital-to-analog converter with a 1σ INL of ± .5 LSB. The technology we have shows a of 2 % and we want to use 1023 equal devices to generate all the current steps [4]. The DC current is set at a value that the threshold mismatch equals the gain mismatch. This means that the average element mismatch becomes:

To obtain a 1 INL of ± .5 LSB an element matching accuracy of 2.5 % is required. This means that we have to increase the unit device size to at least Depending on how the output signal is generated, a cascode current source construction might be needed to make the matching independent of the drain-source voltage of the current generating elements. Mostly cascoded stages are used to avoid output signal dependent matching problems. The next design choice is: switching unit current sources using 1023 switches or using a binary weighted construction of the digital-to-analog converter. The unit current switch-

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ing has the advantage of generating small glitches and having a good Differential Non-Linearity. A problem is the systematic error that can be introduced because of different lengths in clock wires to control the switches in the layout. A very careful layout is needed having in mind that 100 metal interconnect gives a systematic timing error of 1 psec. The binary weighting of the currents by connecting over a layout area distributed current sources to get the binary weighting causes mostly larger glitches because of a more accurately needed timing in the on and off switching of the currents and increase the DNL to about ± 1 LSB. In many designs a combination of segmented current sources (equal to 8 or 16 times the LSB current) and unit weighting is used. In Fig. 22 an example of a 10-bit digital-to-analog current generating network is shown. In this network only equal sized MOS devices are used. Note that in a layout of such a network at least one row of dummy transistors must be added at the outside to improve the overall matching. In case a current to voltage converter is used to sum the output currents of this network, then a cascode current source may not be needed. However, the voltage drop across the switches must be equal in all cases to avoid current modulation due to a variation in the drain-source voltage of this network.

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6.2 10-bit Coarse-Fine voltage mode digital-to-analog converter In most IC processes the matching of resistors is a lot better than the matching of the active elements. Resistor matching depends on size and mask accuracy of the technology [5, 6]. Without too much difficulty a resistor matching better than 0.25 % is obtained. This means that the resolution and accuracy limits of resistor matching dominated designs are between 12 to 14 bits without needing special precautions. In Fig. 23 an example of a 10-bit coarse-fine resistor matched digital-to-analog converter is shown. As is seen from Fig. 23 the system consists of a coarse

ladder using rather low valued resistors to obtain the coarse converter levels. Across each coarse converter level a fine ”ladder“ is connected to obtain the fine steps. At each step a switch has been connected that will be controlled by the input digital data and then an output voltage is generated. Analyzing this system we can see, that the output impedance of the total system depends on the digital code applied to the converter. Furthermore

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all these switches are at the output terminal connected together giving a large output capacitance. As a result of this variable output impedance a different signal dependent delay of the analog output signal is found resulting in distortion. Secondly a high impedance loading is required. A buffer amplifier can be used to decouple the output load from the converter, however, this buffer can introduce distortion due to slew rate limitations and finite bandwidth. Furthermore generating output voltages from 0 to makes the buffer difficult to design.

6.3

Continuous current calibration converter

When the resolution of a converter increases, then the matching accuracy of the individual elements must increase. However, the increase in matching can so far be only obtained by increasing the device size WL. In submicron technology, however, this increase in size can become unpractically large. At that moment other techniques are required to obtain the high accuracy [7]. Furthermore scaling of technology does NOT reduce the size of the current network because the gain mismatch dominates the accuracy. As has been shown the gain mismatch is technology independent and therefore the sizing of the devices can not be used. Calibration or Dynamic Element Matching techniques can be used to improve matching accuracy without increasing size. The continuous current calibration principle is another possibility. In Fig. 24 the basic idea of current calibration is shown. As is seen from Fig. 24 the calibration principle has two states. During calibration the MOS device is via connected as a diode and switch supplies the calibration current to the diode. At this moment across the gate input capacitor a voltage is generated that fits exactly the input current During the operation of the system, the switch is opened and the switch connects the drain of to the output terminal. The voltage on the gate in principle remains fixed, resulting in an output current to be exactly equal to In a practical situation, however, the

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operation of the system is not as expected before. Because of leakage currents introduced by the drain-substrate diode of the switching MOS and the charge feed through of this switch, a rather large error is found. To overcome these problems the basic system has to be modified into the circuit shown in Fig. 25. The

basic operation of the system is identical to the circuit shown in Fig. 24. However, in this system an extra constant current

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being 95% of is added. The calibration now takes place on the ERROR signal and NOT on the full signal This means that errors only influence the accuracy of the calibrated ERROR signal. An improvement of at least a factor 20 with respect to the original system is obtained. The application of the continuous current calibration system into a 16-bit digital-to-analog converter is shown in Fig. 26. The 16-

bit converter consists of 65 current sources that are continuously calibrated using an interchanging system. One output current of this high-accuracy 6-bit coarse converter network is subdivided using a MOS only 1024 element binary weighted current divider. The output currents of the coarse and the fine elements are supplied to the output switches. These switches are controlled by the digital input signals and so the digital-to-analog conversion

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takes place. Depending on the practical design limitations the switching spikes and small calibrated current mismatches extra quantization errors are introduced. As long as the sampling clock and the calibration/interchanging clock are not correlated these errors can be below the quantization error. In that case only a slight deterioration of the dynamic range of the converter is found.

7

Conclusion

The following conclusion can be obtained from this paper: Spectra of quantization errors and the influence of the amplitude on distortion and cross-modulation products have been calculated. Quantization errors have minor influence on the performance of practical converters with finite linearity A relation between element matching and overall linearity (INL and DNL) has been practically determined A practical ”fitting“ model giving the relation between linearity and Effective Number of Bits has been demonstrated Distortion in a converter is dominated by the matching accuracy of the elements used The influence of sampling clock jitter on the Effective Number of Bits of a converter has been determined Systematic layout problems resulting in timing errors have been determined and analyzed Matching parameters of MOS devices have been determined Practical solutions for converters using element matching parameters and system solutions to obtain a very high accuracy have been discussed Depending on the required performance of a digital-to-analog converter a designer can find a number of design rules to help with architectural and circuit design issues.

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8

Acknowledgment

The author wants to thank Frank van der Goes of Broadcom Netherlands for the Mat Lab programming.

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References [1] N.M. Blachman, “The Intermodulation and Distortion due to Quantization of Sinusoids” IEEE Transactions on Acoustics, Speech and Signal Processing, vol. ASSP-33, No. 6, pp. 1417-1426, December 1985. [2] R.J. van de Plassche, “Integrated Analog-to-Digital and Digital-to-Analog Converters” Kluwer Academic Publishers, ISBN 0-7923-9436-4, 1994. [3] M.J.M. Pelgrom, A.C.J. Duinmaijer, A.P.G. Welbers, “Matching properties of MOS transistors” IEEE Journal of Solid-State Circuits, vol. 24, pp. 1433-1439, October 1989. [4] H.J. Schouwenaars, D.W.J. Groeneveld, H. Termeer, “A stereo 16-bit CMOS D/A converter for digital audio” IEEE Journal of Solid-State Circuits, vol. SC-23, pp. 1290-1297, Dec. 1988. [5] M.J.M. Pelgrom, “A 10-b 50-MHz CMOS D/A converter with buffer” IEEE Journal of Solid-State Circuits, vol. 25, pp. 1347-1352, December 1990. [6] P. Holloway, “A trimless 16-bit digital potentiometer” ISSCC Digest of Technical Papers, pp. 66-67, February 1984. [7] D.W.J. Groeneveld, H.J. Schouwenaars, H. Termeer, “A self calibration technique for monolithic high-resolution D/A converters”, IEEE Journal of Solid-State Circuits, vol. SC-24, pp. 1517-1522, Dec. 1989. [8] A.W.M. van den Enden, N.A.M. Verhoekx, “Discrete-time signal processing,” Prentice Hall, 1989. [9] W.R. Bennett, “Spectra of quantized signals” Bell System Technical Journal, vol. 27 pp. 446-472, July 1948. [10] M. Schwartz, “Information transmission, modulation, and noise,” McGraw-Hill, 1980.

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[11] A.B. Carlson, “Communication systems” McGraw-Hill 1975. [12] K-C. Hsieh, Th.A. Knotts, G.L. Baldwin, T. Hornak, “A 12-bit 1-Gword/s GaAs digital-to-analog converter system,” IEEE Journal of Solid-State Circuits, vol. 22, pp. 10481055, Decemebr 1987. [13] G. Wegmann, E.A. Vittoz, “Analysis and improvements of accurate dynamic current mirrors”, IEEE Journal of SolidState Circuits, vol. 25, pp. 699-706, June 1990.

Design Considerations for a Retargetable 12b 200MHz CMOS Current-Steering DAC J. Vital, A. Marques1, P. Azevedo, J. Franca ChipIdea-Microelectrónica, S.A., Porto Salvo, Portugal

Abstract This paper addresses design considerations for highspeed moderate-to-high resolution current-steering digital-to-analogue converters (DACs) in CMOS technology. A design example of a 12b 200MHz DAC in CMOS digital technology is used to illustrate the design techniques, which are then validated through experimental results obtained from the integrated prototypes. Additionally, some techniques used to render the layout of this DAC easily retargetable are also explained.

1. Introduction High-speed, medium-to-high resolution digital-to-analog converters (DACs) are essential blocks in graphical interfaces and in many transmit ports of modern communication systems. In these applications, the current-steering DAC architecture has become a widely used platform, owing it to its linearity, dynamic behaviour, robustness and power efficiency. This paper makes an overview of the most well known techniques for designing current-steering DACs, and describes in more detail a specific implementation of a 12b 200 MHz DAC in a CMOS 1

Augusto Marques was with ChipIdea - Microelectrónica, S.A. until May 2000. Since then he has been with Silicon Laboratories, TX., U.S.A.

151 J. H. Huijsing et al. (eds.), Analog Circuit Design, 151-170. © 2002 Kluwer Academic Publishers. Printed in the Netherlands.

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technology. Section 2 is dedicated to various aspects of importance for architecture selection, and in Section 3 the requirements for static performance are analysed. Section 4 is dedicated to the circuit design alternatives, focusing on the implementations used in the 12-bit design example. Finally, the integrated prototype is described in Section 5, together with the experimental results.

2. Architecture Selection 2.1 Basic Architecture The basic topologies of a current-steering DAC are shown in Fig. 1. The simpler forms of this type of DACs are just digitally programmable current sources/sinks that dump their output current into the load. The resistive part of the load is responsible for the static current-to-voltage conversion function, whereas the capacitive part represents the ultimate limitation for the settling behaviour of the resulting output voltage. As a remark, it is important to notice that most of the implementations use, in fact, two complementary outputs, such that the internal elementary current sources can be steered from one output to the other without the need to be shut-off. This is extremely important for achieving the best performance at high frequency.

The basic topologies can be further refined by adding a fixed halfscale current sink/source, such that the total output current can assume both positive and negative values, as represented in Fig. l(c). Finally, a generic topology employing an additional output block can also be considered, as shown in Fig. l(d). This block can represent a

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transimpedance amplifier for current-to-voltage conversion, allowing more flexible driving capabilities, and/or an output re-sampler for more sophisticated output formats other than the zero order hold, which have benefits from the frequency domain performance point of view [1]. In this paper only the simplest topologies will be considered, since they are the most suitable alternatives for very high update rates. 2.2 Decoding Options One of the most important distinguishing factors in current-steering DACs is the way the digital input data is decoded to drive the internal elementary current sources and implement the digitally programmable output current. The two opposite alternatives for an N-bit DAC are represented in Fig. 2. The simplest scheme is obtained by organising the current sources in N elementary binary weighted current sources, as represented in Fig. 2(a). This requires no decoding, because the bit weights are directly assigned to the current sources, resulting in a digital part with low complexity. However, there are significant drawbacks of this scheme, especially related to major bit transitions [2]. In this topology, major bit transitions result in the most significant bit (MSB) current source being switched to one output and all the others being switched to the other. On one hand, it is very difficult to guarantee good differential nonlinearity (DNL) and monotonicity, since it is necessary to ensure that the MSB current source matches to within 0.5 least significant bit (LSB) the sum of all the other current sources plus one unity. This imposes a very stringent requirement on the allowable mismatch on the elementary current sources. On the other hand, the fact that all the elementary current sources are simultaneously switched at these major bit transitions produces large glitch areas, resulting in large spurious components in the frequency domain. The opposite decoding scheme uses a thermometer decoder to individually control all the elementary current sources. This has advantages in terms of required matching to guarantee good DNL and monotonicity, because the unit current sources are incrementally

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switched from one output to the other as required. In addition, the glitch area is proportional to the amplitude of the transition steps in the output current. This means that glitches are linearly related to the signal, resulting in signal filtering rather than distortion [2]. The only drawback of this decoding scheme is area, because the number of decoding elements is now proportional to The best alternative for thermometer decoding is achieved by organising the current sources in a matrix and by using fast row-column decoders, which, in turn, address local decoders associated to the current sources.

2.3 Segmentation In order to get the advantages of the thermometer decoding without penalising too much the area of the DAC, some sort of segmentation of the input digital word is normally introduced. In the most popular segmentation scheme, the M MSBs address elementary current sources of value using thermometer decoding, whereas the L least significant current sources have a binary weighted arrangement directly addressed by the LSBs [3].

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The selection of the right segmentation into thermometer decoding and binary-weighted arrangement depends on the trade-off between such factors as required area for DAC implementation, simplicity of the decoding scheme and tolerable level of dynamic non-idealities. The decoding scheme must be kept simple and compact to allow very high update rates without significant degradation of the dynamic behaviour [4]. A 6-bit (3+3) row-column decoder uses 3-input gates, whereas an 8-bit (4+4) row-column decoder uses 4-input gates. As the number of inputs required in the basic gates is increased, their intrinsic speed is progressively decreased if no pipelining schemes are employed. Therefore, in high-speed practical implementations the number of MSBs involved in the thermometer decoding scheme has been limited to a maximum of 6 to 8. The selected segmentation for the 12-bit design example considered here is 6+2+4 [4]. The M=6 MSBs use a 3+3 row-column decoding to simultaneously address four 6-bit DACs connected in parallel and arranged in a fully symmetrical way with respect to the centre. This specific arrangement, together with the adopted switching scheme, implements an effective compensation for the systematic errors present across the matrix of current sources. This will be further analysed in the next section. The I=2 intermediate bits also use thermometer decoding and are implemented with the non-used current source in the 8×8 matrix of each of the four 6-bit DACs. The required scaling factor of 4 between the MSB elementary current source and the one for the intermediate bits is intrinsically obtained in this way [4]. The remaining L=4 LSBs directly address 4 binary weighted current sources, which are obtained by subdivision of the elementary current sources in the matrixes. The overall segmentation is, in fact, logically identical to the one presented in [4], but its electrical and physical implementation was simplified and made more compact.

3. Static Performance The static behaviour of the DAC is affected by a number of factors, the most important of which are random mismatches in the current sources, systematic errors due to gradients on process, stress and

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temperature, errors due to voltage drop in the power distribution lines, and finite output impedance. These factors are discussed in the following sections. 3.1 Random Mismatch of Current Sources Due to the adopted segmentation, the current source matching requirements to satisfy the condition DNL