Using digital and analog integrated circuits 9780139394881, 0139394885

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• using

digital·. and analog integrated circuits

USING DIGITAL AND ANALOG INTEGRA·T ED CIRCUITS L. W. SHACKLETTE & H. A. ASHWORm Seton Hall University South Orange, New Jersey

PRENTICE-HALL, INC. Englewood Cliffs, New Jersey 07632

Library of Congress Cataloglng in Publication Data

w (dnte) Using digital and analog Integrated circuits.

SHACKLETT£, L

Includes index. I. Tategrnted circuits-Laboratory mnnunls. I. Ashworth, Harry A., (date) joint author. IL Title. TK7874.S45 621.381 '73 76-30880 ISBN 0-13-939488-S

©

1978 by Prentice-Hall, Inc., Englewood Cliffs, N.J.

All rights reserved. No part of this book may be reproduced in any form or by any means without permission in writing from the publisher.

Printed in the United States of America 10 9 8 7

6

5 4 3 2

London Sydney PRENTICE-HALL OF CANADA, LTD., Toronto PRENTICE-HALL OF INDIA PRIVATE LIMITED, New Delhi PRENTICE-HALL OF JAPAN, INC., Tokyo PRENTICE-HALL OF SOUTHEAST ASIA PTE. LTD., Singapore WHITEHALL BOOKS LIMITED, Wellington, New Zealand PRENTICE-HALL INTERNATIONAL, INC.,

PRENTICE-HALL OF AUSTRALIA PTY. LIMITED,

07632

contents

preface

ix

Introduction 1: DIGITAL CIRCUITS EXPERIMENTS

experiment DI: Cl: D2: C2: D3: C3: D4: D5: CS: D6: D7: C7: D8: CB: D9: DIO: CJO:

logic gates (TTL) 4 logic gates (CMOS) 13 Boolean algebra (TTL) 17 Boolean algebra (CMOS) 26 buffers (TTL) 28 buffers (CMOS) 35 astable multivibrator and Schmitt trigger (CMOS) 40 monostables (TTL) 45 monostables (CMOS) 51 flip-flops I (TTL) 55 flip-flops II (TTL) 60 flip-flops (CMOS) 66 decoders and displays (TTL) 69 BCD-to-seven segment latch decoder driver (CMOS) 76 binary counters (TTL) 79 divide-by-N counters (TTL) 83 divide-by-N counters (CMOS) 87

v

CONTENTS

vi Dll: CJJ: Dl2: DJ3: CJ3: Dl4: Dl5:

full and half-adder (TTL) 91 full and half-adders (CMOS) 97 subtractors: arithmetic logic unit (TTL) registers (TTL) 104 registers (CMOS) 110 universal shift register (TTL) 113 memories (TTL) 118

Introduction 2: ANALOG CIRCUITS EXPERIMENTS experiment A I: A2: A3: A4: A5: A6: A7: AB: A9: AJO:

A 11: A12: A13:

Introduction 3: PROJECTS

125

operational amplifier 127 noninverting amplifier 135 sum and difference circuits 140 real op amps 146 integrating and d((ferentiating circuits 158 comparators 164 op amp Schmitt trigger 170 logarithmic amplifier 176 constant voltage and current sources 182 power amplifier 188 driving relays and silicon-controlled rectifiers active filters 199 oscillators 207

213

project P 1: P2: P3: P4: P5: P6: P7:

PB: P9:

PIO: P JI : P12:

99

voltage regulators 214 555 timer 223 temperature controller 227 audio power amplifier 233 sample and hold circuits 236 encoding and conversion 240 multiplexers 244 electronic music box 248 Boolean puzzles 252 reaction time game 257 minutes timer 261 frequency counter 264

194

CONTENTS

APPENDICES

vii

269 equipment and supplies 270 understanding data sheets 275 references 288 logic probe 290 regulated power supplies for integrated circuits 293 F: glossary 296

appendix A: B: C: D: E:

index

310

preface

The electronic problems that an engineering or science student encounters tend to be of two types: "state of the art" problems which require the purchase of commercial electronics or relatively easy problems which can be solved by a simple circuit of the student's own design. The advent of integrated circuits has greatly reduced the difficulties in designing electronic circuits. Now the widespread use and low cost of integrated circuits (ICs) such as the 741 linear operational amplifier and the 7400 TTL series for digital circuits means that someone relatively inexperienced in electronics can construct and understand a large number of useful circuits. Today it is a very rare problem indeed that requires someone to design a transistor circuit from scratch. Most problems can be solved more efficiently and cheaply by using an IC in place of the discrete components. This text is intended to accompany a one or two semester course intended principally for scientists or technicians. The choice of topics and the approach to the circuits studied are intended to give the student familiarity with ICs and some confidence in using ICs to "make something work." The text emphasizes practical application whenever possible. To this end a series of useful projects has been included. This laboratory textbook is best suited to accompany a second course in electronics which follows a one semester course covering discrete components. However, since we do not draw heavily on any specific knowledge from such a course, the text c~n function as part of a first course in electronics if the instructor devises some introductory labs on the use of voltmeters, ammeters, oscilloscopes and perhaps resistors and capacitors. The text may also be used to provide the all important "hands-on" part of a self-study course. Since integrated circuits are relatively new on the ix

x

PREFACE

market, many people who have already completed their formal education now wish to learn how to use ICs. The emphasis which we have placed on the practical aspects of integrated circuits makes this series of experiments particularly appropriate for anyone wanting to learn how to use I C's in their work. Supporting Texts: A formal bibliography which includes several widely used texts is given in Appendix C. While no particular text is required to accompany this one we would recommend that use be made of these references or their equivalent. For analog circuits (operational amplifiers), we particularly recommend the Hoenig and Payne book ("How to Build ... ") for its conversational· tone and the sense of confidence (sometimes false) that it instills in students. We also highly recommend the use of manufacturers' databooks. We suggest that the databooks be made available to students in the laboratory at a rate of one book for every five or six students. Supplies: We have tried wherever possible to use only those parts which are inexpensive and readily available. Most parts can be obtained from the surplus market (these parts are new, but cost 110 tot the list price). Appendix A provides a list of suppliers (both surplus and regular). All parts required by this manual can be obtained from these sources. We have made use of TTL and CMOS digital logic and "common" op amps such as the 741 and 555. We have specifically stayed away from more exotic (and more expensive) ICs and modules whenever possible. Projects: We have found that a student taking a conventional electronics course and laboratory can receive a legitimate "A" for his or her course work and laboratory yet be helpless when asked to construct a small circuit outside the context of the course itself. Consequently, this text includes a series of projects of varying difficulty which a student should be able to construct in one three-hour Jab session. In general the projects are less rigidly structured and require more self-reliance than the experiments. Course Outline: Ideally, in a two semester course with 30 laboratory sessions, all of the twenty basic experiments could be performed along with a few of the projects that appeal to the instructor. In a one semester course we would suggest perhaps two introductory labs, followed by Experiments Al, A2, A4, A6, Al2, DI, D2, D3, D4, D7, D9, Dl3, and finally two projects. Equipment: We recommend that each "set-up" have no more than two students. Each set-up should include a function generator, a single or dualtrace oscilloscope, a couple of socket-boards, and a variable voltage power supply. Fixed voltage + 5 V and ± 15 V power supplies are also convenient but are not absolutely required (see Appendix E). A digital voltmeter is a highly recommended option to replace the conventional VTVM. Appendix A lists sources of suitable inexpensive equipment.

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digital and analog integrated circuits

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INTRODUCTION

I:

DIGITAL CIRCUITS EXPERIMENTS

Experiments DI-DIS are concerned with nonlinear circuits in which there are only two possible voltages: high and low. Most experiments are performed using transistor- transistor logic (ITL) or complementary-symmetry metal oxide semiconductor (COS/MOS) circuits. We shall shorten the latter abbreviation to CMOS: A few rules must be kept in mind whenever performing digital experiments: l. Every device must be connected to a power supply. For ITL devices the power supply should provide Vee (+5 V) and ground (GND). For CMOS circuits the power supply terminals are labeled VDD and Vss· The quantity VDD - Vss can range from + 3 to +15 V, and there is no restriction on making VDD and Vss negative. Frequently encountered power supply ranges are VDn = 5 V and Vss = 0, VDD = IO V and Vss = 0, or VDD = 5 V and Vss = -5 V. The actual connections to a ITL and a CMOS integrated circuit (IC) are shown in the figure on the opposite page. The contacts are made under the board. Any set of five holes such as those indicated by arrow A are connected together. There are no internal connections across the central channel. To identify the pins on an IC, look for an indentation or small circle at one end. When the indentation is placed on the left with the IC viewed from the top, pin 1 is in the lower left comer. The pins are then numbered consecutively in a counterclockwise direction. In the case of the 7402, pin 14 is directly across the IC from pin 1 and is connected to the + 5-V power supply. Pin 7 is connected to ground. For the CMOS circuit on the right, pin 14 goes to VDD and pin 7 goes to Vss· Also shown in the figure are three light-emitting

+

1

2

INTRODUCTION I

diodes (LEDs) connected to the appropriate pins through dropping resistors to ground. The actual TTL circuit shown is equivalent to procedure 2 of Experiment D2. Procedure 2 would be carried out by using another wire to touch pins 2 and 3 (the input A) alternately to high ( + 5) and low (ground). The output state at pin 10 is monitored with an LED being on (high) or off (low). 2. The inputs to a TTL device will usually be high if not connected externally to low. If you experience difficulty with a circuit, connect the unused inputs to high. Highs and lows are explained in Experiment DI. 3. CMOS circuits do not have predictable inputs or outputs if left unconnected. To protect the devices, unused inputs should be connected to high or low through a large resistor, such as 100 kilohms (kQ). Now that we have repeated the usual caution about unused inputs, the truth is that unless you are using a very expensive ($1 perhaps) CMOS circuit you probably will not damage enough devices to warrant the trouble of protecting unused inputs. This same philosophy extends to other precautions for CMOS: protecting a device from static charges by storing it in conductive foam, grounding yourself and your soldering iron (if you ever use one), never changing connections with the power on, etc. These precautions are similar to the injunctions we receive to exercise regularly, get eight hours sleep, avoid any food that tastes good, and so on. To be safe, all precautions should be taken. We suggest living dangerously with the inexpensive circuits. We shall repeat the one rule that must be followed: If a CMOS input is to be high or low, it must be connected to high or low. You may not cheat on this rule. 4. Do not apply input signals that exceed the power supply voltages. TTL circuits only wish to "see" inputs between 0 and 5 V. There is a slight margin for error but not much (10 percent). For example, if you were to apply a ground-referenced 2-V rms signal to a TTL gate, the device would most likely self-destruct. CMOS behavior is similar. However, CMOS devices will accept zero-crossing signals if a bipolar (± ) power supply is used. You must still obey the dictum that the power supply voltages must not be exceeded (on either end).

5. Manufacturers prefixes and suffixes: we refer to devices by their "generic" numbers, such as 7400. A large number of companies manufacture the same device but attach a distinctive prefix for identification. For example, an SN7400 is manufactured by Texas Instruments; an N7400 by Signetics. All TTL devices identified with the number 7400 are equivalent. Occasionally, a letter is inserted in the middle of the number (74LOO, 74SOO). These letters can usually be ignored (see Experiment D3). Suffixes, e.g., N7400-A or N7400-W, refer to the type of package. For example, A indicates a 14-pin dual-in-line (DIP) plastic package and Wis a

DIGITAL CIRCUITS EXPERIMENTS

3

DIP ceramic package. For all the circuits in this manual, the pin assignments will be the same, regardless of any particular suffix that your digital IC has. There is a slight modification to these rules for CMOS. A 4001B IC will be able to supply a larger output current than a 4001A (or 400IAE). Unless otherwise stated, you may use either A- or B-suffix devices. The B-suffix devices also can tolerate a power supply voltage as high as 18 V, versus 15 V for A-suffix devices. 6. Anything TTL can do, CMOS can do better. This statement is debatable, but you should be aware of a few of the advantages and disadvantages. In any such broad comparison, an advocate of either type of logic can point to an exception, or special modification. The following generalities will be disputed by some: a. CMOS uses far less power, by a factor of I 000. (There are, however, low-power TTL devices indicated by such numbers as 74LOO. The L means low power.) b. TTL is cheaper (somewhat; but CMOS is also "cheap," and becoming more so). c. CMOS is slow. T rue, but delays in CMOS might typically be 30 nanoseconds (nsec), whereas TTL has 10 nsec. Unless you are designing high-speed computers or frequen cy counters, the difference in speed is not important. d. There is a wider variety of TTL devices. We have no argument here, but the most widely used TTL circuits have CMOS equivalents. e. CMOS is difficult to interface (meaning to connect with the outside world through LEDs or to other circuits). Simply not true. f. CMOS is more immune to noise. True; but for many applications noise is not a problem in TTL. g. Power supply regulation is critical for TTL and not critical for CMOS. The choice between CMOS and TTL may reduce in many cases to the fact that a CMOS IC can get by with a less expensive power supply. h. If battery operation is desired, CMOS is clearly the preferred choice. TTL logic is an industry standard, and it would be foolhardy to become expert at CMOS to the exclusion of TTL. Fortunately, most of the experiments in this manual illustrate concepts that are quite independent of the choice between CMOS and TTL.

experiment

DI:

logic gates (TTL)

The earliest digital computer used relays and switches to perform binary arithmetic and logical analysis. The state of a switch, open or closed, can correspond to a 1 or a 0, the only two numbers necessary for binary arithmetic. In logical analysis, "true" and "false" may also be represented by a switch being open or closed. A logic gate is a circuit that has two or more "logic" inputs and one output. Diodes and transistors are natural devices to use in gating circuits since they can be driven so as to be either "on" (conducting) or "off" (not conducting). The easiest way to understand the operation of a gate is to analyze the circuit shown in Fig. Dl-l(a). The output of the circuit is V, and V1 and V2 are two inputs. If V1 and V2 are both 0, the output, V, will be almost equal to 0. The diodes are both conducting and will have a small voltage drop across them. If V 1 equals 5 V and V2 equals 0, D, is reverse-biased, and Vis still equal to 0. When V2 equals 5 V and V 1 equals 0, Vis again equal to 0. However, if V1 and V2 are both equal to 5 V, V will rise to 5 V. In digital electronics, voltages are normally restricted to two levels which can be called "logical 1" and "logical O" or "true" and "false," or "high" and "low," or "on" and "off." If we designate any voltage of 0.6 V or less to be 0, and any voltage greater than 3 V (for example) to be 1, the input-output characteristics of the circuit of Fig. Dl-l(a) can be summarized in Table D 1-1. If you were to replace all the Is with " true" and the Os with "false," you would have the truth table for the logical expression AND. In words, Table Dl-1 says, " if V 1 and V2 are both high (>3 V), the output

4

5

LOGIC GATES (TTL)

o,

v,

c C>-N-_.--o v

v

1 kU

1 kil

5V

v,

Y2

v

A

B

c v

0.6 0.6

0

0 0

0.6

0

1

0 0 0

0

1

5

0 5 0

5

5

5

1

1

1

1

0 0

1

1

(b)

(a)

Fig. DI-1. (a) Diode logic used for AND. The voltages recorded are also

represented in Table D l -1; (b) diode logic used for a triple-input OR.

Table DI-I AND

V1

V1

v

0 0 1

0 I 0 l

0 0 0 1

- -- - - -- - -

1

is high. Otherwise, the output is low." Notice that the designations high and 1, as well as low and 0, can be used interchangeably. A second kind of gate is shown in Fig. Dl -l(b). The logical OR statement in words is, "If any one of the inputs is 1 (or true or high), then the output is 1." The analysis of the circuit is very simple, since if any one of A, B, or Chas a positive voltage, V will be a positive voltage. If A, B, and C were

6

EXPERIMENT DJ

allowed to have different positive voltages, we could not be sure of the output voltage. In a digital system, A, B, and C will all have the same voltage corresponding to I, commonly 5 Y, so that V will be approximately 5 V (minus the forward-bias voltage on the diodes). Another logic operation which is of interest is NOT which says, "NOT A is 0 if A is 1, or if A is 0, NOT A is I." We will write NOT A as A. You may also find A described as the complement of A or the inverse of A . A generally does not mean the negative of A, in volts. The logic statements and their circuit symbols are summarized in Fig. Dl-2. Although all possible digital operations can be performed by using just these three gates, it is actually more convenient to use two other gates as basic building blocks for digital circuits. A NAND or NOT-AND gate is simply an AND gate followed by an inverter. The truth table and circuit symbol are shown in Fig. Dl-2. At first glance, the NAND symbol may look identical to the AND symbol, but notice the extra circle in the NANO drawing. A small circle following a logic symbol means that the operation is inverted (or negated or barred). The NAND function in words is, "If A and B are high, C is low; otherwise, C is high." You can wire relays together in such a way that they will perform any of the logic statements in Fig. Dl-2. In the not-too-distant past, discrete components such as diodes and transistors were used to make logic gates. Today, integrated circuits are available that contain combinations of diodes, transistors, and resistors to perform fast and efficient gating. For example, an IC that contains several AND gates made from diodes and resistors, such as in Fig. D 1-1, is referred to as a DL (diode-logic) IC. A variety of different logic families are available. Each family has something to recommend it, but we have arbitrarily chosen to use only the most common and cheapest Logic family (TTL) and the more recent and very versatile logic referred to as Complementary MOS (CMOS). Most of the texts in Appendix C have discussions of the various logic families. The difficulty with a theoretical discussion of the pros and cons of two logic families is that a very practical consideration is frequently ignored. TTL logic has swamped the digital electronics industry, and the other logic families have been relegated to relatively minor positions. The following are the most common types of logic gates: 1. Resistor- transistor logic (RTL): common in the middle of the 1960s, cheap, but only of historical interest. A typical circuit is a RTL923.

2. Diode-transistor logic (DTL): somewhat slow (compared to TTL) and more expensive than RTL. 3. Emitter-coupled logic (ECL): very fast but expensive. High power consumption. A typical circuit is the 1004.

AND

:=ere C= A·B

OR

:~c

A~C

C = A+B

C=A

A

B

c

A

B

c

0

0 0 0

0 1 0

0 0

0

0

0 0 1

1

1 1

1

1

1

1

1

1

1

NANO

NOT

::[)--oc ::[)-c

E!J 1

0

Fig. DJ-2. Logic symbols and thei r truth tables.

-l

NOR

C= A·B

C=A+8

A

B

c

A

B

0 1 0

0

1

0

0

0

1 1

1

1

0 1

1

1

0

0

C

0 0 0

EXPERIMENT D J

8

4. Transistor-transistor logic (TTL): moderately fast, cheap, and moderately immune to noise. A typical circuit is the 7400 used in this experiment. 5. Complementary metal oxide semiconductor (CMOS): very low power, good noise immunity. Easy to match (interface) to other digital or analog circuits. Potentially very cheap. Typical circuit is the 4001. There is, of course, one overriding similarity among all logic families. The logic operations remain the same. An AND in TTL means exactly the same thing as an AND in any other family. The differences among the families are confined to practical matters such as power supply voltages, voltage levels corresponding to logical 1 or logical 0, and the number of gates that can be connected together. If you can design a circuit in terms of the NAND and N OR symbols of Fig. Dl-2, you will be able to construct the circuit using any available logic family.

PARTS Diodes: general-purpose diodes (3) (1N914 or similar). Resistors: 5 kQ. I Cs: 7400, 7402. Pulse generator or oscillator with sine and square wave outputs. Power supplies: variable 0-5 V; fixed 5

± 0.25-V de supply.

PROCEDURE 1. AND Gate. Construct the circuit of Fig. Dl-l(a). It is not necessary to use three separate power. supplies. We wish to make Vi and V2 alternate·ty equal to 0 and 5 V, and we can simply touch V1 and V2 to ground or the 5-V power supply. Try to arrange your diodes and wires so that you can alternate V 1 and V2 between the two voltage levels without wrenching the circuit apart. Construct a truth table similar to the table contained in Fig. Dl-l(a).

2. NAND Gate. The integrated circuit, 7400, is a TTL device that contains four NAND gates on a 14-pin chip. Connect a 7400 to a 5-V power supply, as shown in Fig. D 1-3. TTL devices are very sensitive to overvoltage. Before completing the connection, verify that the supply voltage is within the range from 4.75 to 5.25 V. Measure and record the voltages at pins 1, 2, and 3. The voltage at pins 1 and 2 will not be close to 0 or 5 V. The voltage at pin 3 will represent a logical 0. Can you tell by examining the truth table in Fig. Dl-3 whether the voltages at pins I and 2 represent highs or lows?

LOGIC GATES (1TL)

9

7400

+ 5V

Fig. Dl-3. Quad NAND-7400. Pins I and 2 serve as inputs.

The voltage at pin l would be A in Fig. Dl -2 ; pin 2 is B, and pin 3 is the output C. Attach wires to pins I and 2 and monitor the output with a voltmeter. Construct the truth table for a NAND gate by making the voltage at pins 1 and 2 alternately 5 V or ground. For the TTL family, a logical I is any voltage greater than 2.4 V, and logical 0 is any voltage less than 0.4 V. 3. Inverter (NOT). Use the 7402 as shown in Fig. Dl-4. Connect pins 5 and 6 together. Construct the truth table for the output at p in 4 versus the input at pin 6 or 5. Obviously, there are only two cases since pins 5 and 6 are wired together. Connect the output (pin 1) of the first gate to the inputs of the second gate (pins 5 and 6 together). Make a truth table for pin 4 with pins 2 and 3 as inputs. Pins 2 and 3 are not to be wired together. Draw the block diagram of these two gates in series. Identify the truth table as one of the five in Fig. Dl-2. A NAND or a NOR gate can be made into an inverter simply by tying the two inputs together. An OR or AND can be formed by inverting the output of a NOR or NAND. 4. Properties of TTL. We shall see how to mathematically combine logic function s like NAND and NOR in the following experiments. There

EXPERIMENT DJ

10

+

7402

5V

Output Fig. Dl-4. Quad NOR-7402.

are certain practical features of using TTL circuits that we must understand first. a. Power Supply. The power supply voltage is given on the data sheet and should lie within 5 percent of 5 V. To estimate the current demand on the power supply, you may assume that each gate uses 10 milliwatts (mW) of power. Quick calculation indicates that each gate uses 2 milliamperes (mA). The round-number estimate for a 7400 would be 10 mA. b. V; •. The symbol V10 (or Vw) indicates the input voltage that represents a logical I. TTL specifications indicate that if V;. exceeds 2 V it will be considered a 1. Similarly Vi.co> (or VIL) is required to be less than 0.8 V to ensure that the 7400 will treat the input as a zero. c. v.UI' The typical output voltage Vout ( I ) (or Von) that represents logical l is 3.3 v, but is guaranteed to be at least 2.4 v. vout(O) (or VoL) is specified to be less than 0.4 V. Connect a variable de power supply to pin I (V1 ) of a 7400 and connect pin 2 to the fixed 5-V supply. Measure and record the output voltage for V 1 equal to 0, 0.5, I, 1.5, 2, and 2.5 V. Does the 7400 meet its specification for Vin0. 1f your oscillator has a de offset control, simply adjust the offset to about +2 V and set the amplitude of the output to be about 4 V, peak-to-peak, 200 hertz (Hz). Before completing the connection at A, monitor the output of the oscillator with your scope and be sure it does not go negative. If your oscillator has no offset control, simply add a diode clamp as shown in Fig. Dl-5. Use the voltage of the oscillator as the input to the X axis of your scope (internal sweep disabled, of course) and the voltage from pin 3 as the Y axis. Make a detailed drawing of the result, indicating on the drawing which points )'OU WOUld USe tO measure Vin ( !)> Vin(O)> Vout(I)> and Vout(O)'

+5

v

r ------ 1 I

I

I I

....__ _..High

: 1 µF

2 14

v,

7

x

Low

Osei Iloscope ....__ _ __, High y

!

7400

Low

I I

___ ___ JI

See text Fig. Dl-5. Oscillator used as input to one section U 7400) of a 7400. The input to the gate is the horizontal axis of an oscilloscope; the gate output is the vertical axis on the scope. The diode clamp (I µF and diode) is needed only if the oscillator output crosses 0 (goes negative) during any part of its cycle.

6. Input Current. When a logical 1 is presented to a TTL gate, the current drawn will be between 40 microamperes (µA) and 1 mA. Leave pin 2 connected to 5 V and connect a IO-kn resistor between pin 1 and the 5-V supply. By measuring the voltage drop across the 10-kn resistor, calculate the input current. Is it within specifications?

EXPERIMENT DI

12

When the input to a TTL gate is low, current flows from the gate to ground through the input source. The maximum current that flows out of a gate when a 0 is present is 1.6 mA. This situation is described by the statement, "the input source must be able to sink I.6 mA." Connect a decade box between pin 1 and ground (pin 2 still at 5 V). Increase the resistance of the box until the output of the gate goes to a logical 1 (2.4 V). Measure the voltage at pin 1 and calculate the current being sinked by the resistor to ground.

NOTE Semiconductor component manufacturers require very little raw material in terms of weight or bulk. Thus, one might expect that the semiconductor industry would have grown at random around the country. In fact, the industry is widely distributed, with manufacturing centers on both coasts as well as in Texas. There is one area of the country, however, that is as strongly associated with the semiconductor industry as Detroit is with automobiles or Pittsburgh with steel. California's "Silicon Valley," a region 30 miles long and IO miles wide, southeast of San Francisco, is home to an enormous number of integrated-circuit and related high-technology companies. The "valley," extending from Palo Alto to Santa Clara, includes such addresses as Sunnyvale, Mountainview, and Cupertino. Industry giants such as National, Fairchild, and Signetics (aU in the valley) inevitably give birth to a variety of spin-off companies, which are fed by the personnel and technology of the larger firms. Stock market analysts and other economists have been rumored to judge the true health of the semiconductor industry from the number of "house for sale" signs visible in "Silicon Valley."

TROUBLESHOOTING I. The most common error for beginner and expert alike is simply misidentifying the pins on the IC. Check the data sheets again and perhaps reread the introduction to be sure you understand how the pins are numbered. 2. If the IC gets hot, either you have reversed the power supply or shorted an output pin to ground or your power supply voltage is too high. 3. Any input pin to a TTL device that is not wired to 5 V or ground will most likely sit at 1.6 V, and will be considered a logical l. 4. Do not expect a reading of 0.00 V for a logical 0 or 5.0 V for logical I or high. All that matters is that the voltage levels are within specifications.

experiment Cl:

logic gates (CMOS)

All the introductory material in Experiment DI, which explains the concepts of logic gates, applies equally well to CMOS or TTL gates. We shall assume that you have read this material. The important differences between TTL and CMOS gates occur in the input voltage levels corresponding to logical 1 and logical 0 and in the effective input and output impedances of the devices. Table Cl-1 compares the input characteristics of TTL and CMOS gates. Table Cl-1 Value Property

TIL 2.0V < 0.8V -----1-1---11.....-_

I I I

_.,.

9 I n----'-----1

Wire-AND

is D

F

I I

7 I

_

I I

r~----- ! Fig. D3-2. Outputs of three NAND gates with open-collector output are

shown connected together to form a wire-AND. The configuration requires only a single pull-up resistor, Re- The wireAND "gate" shown is not really a gate. It actually denotes only the connection between the output pins 3, 6, and 8.

30·40 µA). The 7437, 7438, and 7439 buffers have a maximum high-Jevel output voltage (V0H) of 5.5 V. Thus, these devices cannot be used to produce output voltages higher than the standard TTL supply voltage (5 V).

Buffers with High Voltage Outputs. The 7400 series does contain buffers that can be used with high voltage outputs: the 7406, 7416 inverter bufferdriver with open-collector outputs, or the 7407, 7417 buffer-driver with open-.:ollector outputs. These devices can be used to interface TTL circuits with high voltage and/or high current loads such as lamps, relays, or MOS !Cs. The specifications for these buffers are listed in Table 03-2. The current, ! 08 (sometimes called output reverse current), represents the maximum current that flows through the output transistor when the output is high at V0 H (output transistor off). The value of 250 µA is typical of all 7400 series devices with open-collector outputs. The value of ! 0 " puts an upper limit on the value of the pull-up resistor, R,. For example, guaranteeing that the high output is

32

EXPERIMENT DJ

Table DJ-2

7406 7416 7407 7417

Von

foL

1011

(max., V)

(max., mA)

(max., µA)

30 15 30 15

40 40 40 40

250 250 250 250

Vee= 5

~

7417

A

v

,- - -J~

V5 = 5 V

1kS1

12

I

I I I I

B

I

3 I

fL___

I

I I I

A·B

14

I

J

Fig. DJ-3. Wire-AND circuit constructed with two noninverting buffers from a 7417.

within 2.5 V of Vs [see Fig. D3-l (b)] requires a value of Re less than Re= 2.5 V/ 250 µA = IO kQ. T he minimum value of Re for a buffer from T able D3-2 is R. = Vs/l ot.• where Vs::::;; V011 • Using the value of V0 u and IoL for a 7417, Re = 15 V/40 mA = 375 Q. The diagram in Fig. D3-3 illustrates a wire-AND circuit constructed with a pull-up resistor between these extremes. Figure 03-4 shows a 7417 driving a relay. The coil resistance of the relay must lie within the extremes stipulated for Re. The voltage Vs should be chosen to equal the coil voltage specified for the particular relay used. This voltage must be under 15 V for a 7417 or under 30 V for a 7407.

33

BUFFERS (TTL)

Load

Input

~ 7417

Fig. D3-4. A 7417 buffer-driver connected to operate a relay. The current available to the load is restricted only by the current capacity of the relay contacts.

PARTS IC:

7400, 7403 (or 7401), 7417 (or 7407), and a 7437.

Resistors:

1 kQ, decade box.

Relay: any relay with a coil voltage < 15 V (or A 2 , A*, and Ac. Strangely, A*= A 1 · A 2 (if pin 10, A*, is o pen), or A* can be used as an independent input if A 1 and A 2 are connected to ground. The actual A input is A*· Ac, where A* is either a direct input (A 1 , A 2 grounded) or derived from A, · A 2 (A* left open). The B input rules are iden+5

v

10

B"

9

8

7480

s Gnd

3

4

5

c,, from hal f·adder Fig. DJJ-3. Gated full adder.

6

*

7400

FULL AND HALF-ADDERS (TTL)

95

ti cal. We will wire A 1 and A 2 together and connect our data a 1 to pin 8, A 1 • By leaving A* open, as shown in Fig. Dll-3, A*= ii1 • If Ac= 1 (by tying pin 11 to 5 V), then A = A* = a, . Following the same procedure for Band b, means that the truth table, Dl 1-2, now applies to the bits a 1 and b 1 of the 2-bit number we wish to add. A final feature of the 7480 is the inversion of the final carry. The carry output at pin 4 is actually Cn+t · Consequently, an inverter must be inserted between the LED representing S'}., aud the carry output. By setting al> a 0 , bi, and b0 to the proper levels, perform the additions 0 plus 0, I plus 0, 1 plus I, 2 plus 1, 3 plus 1, 3 plus 2, and 3 plus 3. Use LEDs or the logic probe in Appendix D to monitor S 2 , S 1 , and S 0 • Make a table showing a,, a0 , bi, b 0 and S 2 , S 1 , S 0 for these seven cases. 3. (Optional.) If you have retained the decoder-display constructed in Experiment D8, you may display the output of the addition in decimal form. Merely treat S 2 , S 1 , S 0 as inputs CBA to the decoder, and wire the D input to 0. For example, if you use a 7448 decoder-driver and a seven-segment display, S 0 goes to pin 7 of the 7448, S 1 to pin l, S 2 to pin 2, and pin 6 should be grounded.

HISTORICAL NOTE In the future we are certain that most respectable museums will include among their exhibits a slide rule and a mechanical adding machine. For those readers who are too young to have used an adding machine, you will have to imagine an instrument that was roughly the size and weight of a typewriter, that "chugged away" at division with an impressive clanging, and that completed calculations about twice as fast as a person with pencil and paper. In the early 1970s, companies such as Bowmar and Ragen Precision introduced the first small, desk-top calculators. These instruments sold for $200 to $300 and were called "four-bangers," because operations were limited to add, subtract, multiply, and divide. By 1972 kits were available for around $100, and within three years the price for a simple hand-held calculator had dropped to below $15. Such drastic price reductions are certainly good news for consumers, but usually bad news for many companies in the field. The fortunes of many such companies have followed a roller-coaster path. In the early 1970s one new field that seemed sure to grow and prosper was the repair and servicing of electronic calculators. However, the subsequent decline in sales price coupled with the skill required to service several different brands of calculators has virtually eliminated the independent

96

EXPERIMENT DJ1

repairman from the electronic calculator field. In fact, the declining price of calculators has nearly eliminated repair work altogether by making the repairing of the least expensive calculators economically infeasi ble. The era of the "disposable" calculator is upon us!

experi111ent Cll:

lull and half.,adders (CMOS)

You should refer to the text and figures of Experiment D 11 for a discussion of full and half-adders. The CMOS device, 4008, four-bit full adder, is inexpensive but still contains four full adders on a single chip. Rather than construct a half-adder from an exclusive-OR (4030 or 4070 in CMOS), we shall use one section of the 4008. One important feature of the 4008 is a look-ahead carry. The TTL equivalent to the 4008 is the 7483, which possesses a look-ahead carry. The carry is generated within the ch ip by a series of AND and OR gates, whkh are independent of the full adders. This method of construction greatly reduces the delay in generating the carry because there is no need to wait for all four adders to complete their summations. If the final carry goes to another set of adders, the next addition can begin before the first set of adders is finished. The carry-out (final carry) is generated in about 45 nsec for CMOS (4008A) and in about 15 nsec for TTL (7483).

PARTS IC: 4008; 5- or 10-V power supply. LEDs and dropping resistor or logic probe of Appendix D.

PROCEDURE 1. Half-Adder. Use the 4008 (Fig. Cll-1) with C, = 0, pin 9 to Vss· Use A 1 (pin 7), B , (pin 6), and S 1 (pin 10) as the inputs A, B, and sum S of

97

EXPERIMENT CJJ

98 +5 v

16

15

14

13

12

11

10

9

s,

A, 1

2

3

4

5

6

7

8

4008 Fig. Cll-1. Pin diagram for the 4008 four-bit full adder.

the half-adder. You may use S 2 (pin 11) as the carry C from the half-adder if B2 (pin 4) and A 2 (pin 5) are wired to Vss· Construct the truth table for A, B, S, and C, and compare to Table Dll-1. In your report, explain how you would use the 4070 (exclusive-OR) and a 4001 or 4011 to construct a half-adder. 2. Full-Adder. Add the numbers A= A 4 A 3 A 2 A 1 = 0101 and B = B 4 B 3 B2 B 1 = 1001. Record the results of A plus B for C, = 0 and Ci= I. If your decoder-display from Experiment C8 is still connected, you may use it to monitor the output of the adder. Make S4 equal to D, S 3 equal to C, and so on. Obviously, the largest output of the four adders exceeds the capacity of a single digit display. Check a few sums such as 2 plus 3, 3 plus 4, etc. What is the largest number that can come out of the 4008? What must the inputs be to give this number? 3. (Optional.) Use a 4001 or 4011 to make inverters. Subtract A ( = 0101) from B ( = llOO) by tbe two's complement method described in Experiment Dl2. The rule is to invert A, sum tbe inverse of A with B, and then add I to the sum. How do you add 1 to the sum of B 4 B 3 B 2 B 1 and A 4 A 3 A 2 A 1 ? Give your results in binary and decimal form.

experiment 012:

subtractars: arithmetic logic unit (TTL)

There are a number of schemes for performing the subtraction of two binary numbers. In all cases a smaller number must be subtracted from a larger number. If you instruct a subtractor circuit to perform A - B, where B > A, the circuit must be able to detect that A - B will be negative and then proceed to take B - A. If this sounds unnecessarily complicated, recall how you perform 51 - 62. The rules we learn in grammar school tell us to take 62 - 51 and attach a minus sign to the answer. The rules for binary subtraction are 0 - 0 = 0, I - 0 = 1, 0 - 1 = -1, and 1 - 1 = 0. We shall refer to 0 - 1 = -1 as being a difference of 1 and a borrow (analogous to a "carry") of 1. The borrow is used in binary subtraction in exactly the same way that we borrow in digital arithmetic. For example, if we take 101 minus 011, we perform

101 - 011 010 Proceeding from right to left, 1 - 1 gives 0, 0 - I gives a difference of 1 and a borrow of 1, and 1 - 0 minus a borrow of 1gives0. Table Dl2-1 for a half-subtractor is quite similar to the table for a halfadder. Notice that tl1e difference is A EBB (EB means exclusive-OR) and the borrow is A·B. Table Dl2-l is for A - B. A table for B - A is identical except that the borrow is A· B. We can construct half-subtractors from exclusive-OR and NOR gates as shown in Fig. Dl2-l(a). A full subtractor is shown in Fig. Dl2-l(b). The

99

EXPERIMENT Dl2

100 Table D12-1 SUBTRACTION OF

A - B

A

B

Difference

Borrow

0 I 0

0 0 1

0 I 1 0

0 0 l 0

(a)

c"

:?

(inpu t borrow)

Borrow

•;.•I,___.,.

HS

i- --1/::::::~"'

.____ ___, (b)

Fig. D12-J. (a) Half-subtractor, A - B; (b) full-subtractor formed from two half-subtractors (HS) and an OR gate.

scheme for connecting a half-subtractor and n full subtractors in parallel to subtract two numbers of n + I bits should be evident. The subtraction of two 4-bit numbers requires the use of one half-subtractor and three full subtractors. If buiit from scratch, 17 simple gates and 7 exclusive-ORs would be required. The preferred method of subtraction is called the two's complement. Briefly stated, if B is to be subtracted from A, one forms the complement of B by inverting each bit. For example, the com-

SUBTRACTORS: ARITHMETIC LOGIC UNIT (TTL)

101

plement (sometimes called the one's complement) of 1011 is 0100. The complement of Bis then added to A, and the sum is A minus B minus 1. If I is added to the result and the final carry, if any, ignored, the answer will be A minus B. The advantage to this method is that no subtractor need be constructed since only adcLition and inversion are involved. Both methods of snbtraction require the designer to be sure that smaller numbers are subtracted from larger ones. A general subtractor would have to inspect the two numbers to be subtracted, decide which is larger, invert the smaller, add the

Pin Number

2

23

Pin Number

24

22

21

20

19

18

9

10

11

Function

Arithmetic Operations: M =L

Selection S3

S2

L L L L L L L L H H H H H H H H

L L L L H H H H L L L L H H H

1-1

s,

So

L L H H L L H H L L H H L L H H

L H L H L H L H L H L H L H L H

en

= 0;

en

= H= 1

F =A F=A+B F =A + B F =minus 1 1!wo's complement) F =A plus AB F = (A + B) plus AB F = A m inus B minus 1 F =AB minus 1 F =A plus AB F =A pluj_ B F = (A + B) plus AB F =AB minus 1 F =A plus A F = (A+~) plus A F = (A + 8) plus A F = A minus 1

Fig. Dl2-2. Pin assigoments for the arithmetic logic unit (ALU).

12

EXPERIMENT Dl2

102

larger number and the complement of the smaller, add 1 to the sum, and indicate whether the answer is po~itive or negative. Fortunately, there is a versatile type of IC called an arithmetic logic unit (ALU) that can add, subtract, compare magnitudes, and perform a variety of logical operations. Although a n ALU is somewhat expensive, costing about six to ten times as much as a full adder, its versatility makes it attractive for any application except the simplest additions. A quick inspection of the data sheet for the 74181 (Fig. DJ2-2) shows the 48 operations that the unit performs on two input words, A and B, each having 4 bits. There are fo ur selection inputs, a mode selection input (M), a nd two possibilities for the carry inputs. The 74181 generates a look-ahead carry as explained in Experiment Cl 1. Among the most useful operations are: I. Subtractio11. Set S3 S2 S1 S0 to 0110, set pin 7 (C0 ) to 0. With pin 8 (M) at 0, the F outputs will be equal to A minus B. Notice that the input carry is inverted at pin 7. The chip actually performs A plus the complement of B. If I is added to the answer by making the input carry, C0 , equal to 1 (i.e., pin 7 = 0), the output is A m inus B.

2. Additio11. The inverse of the carry from any previous addition goes to pin 7. T he selection lines are set to 1001. The output at the F pins is A plus B plus c.. Pin 16 will have the inverse of the final carry, C.+4 •

3. Comparator. It is frequently necessary in digital systems to determine the relative sizes of two binary numbers. The 74181 has an output called simply A = B (pin 14). This output is open collector, so a pull-up resistor of I kQ must be connected between pin 14 and + 5 V for experimentation. If A and Bare equal, the A = B output is high. To operate in this mode, the selection lines, S3 S2 S1 S0 must be placed at 0110 and M = 0. Another useful comparison is available at pin 16 (Cn+4)· If pin 7 (c.) is high, then cn+4 will be low if A < B and high is A > B.

PARTS I Cs:

7486, 7402, 74181.

Resistors:

I kQ.

(Optional:

LEDs and dropping resistors or BCD decoder-display.)

PROCEDURE 1. Construct a ha lf-subtractor as indicated in Fig. Dl2-1. Verify the truth table fo r A - B. What is the truth table for~ - A? Suppose that you

SUBTRACTORS: ARITHMETIC LOGIC UNIT (TTL)

103

were to subtract a two-digit number B 1 B0 fromA 1 A 0 using a half-subtractor and a full subtractor. What would be the output if B 1B0 = 11 and A 1 A 0 = 01 ? What should the output be?

en

2. ALU. Use the 74181 to subtract 1001 from 101 1. (pin 7) must be a O; M must also be 0. Explain how pin 16 indicates the sign of your answer. Complete Table Dl 2-2 and write the mathematical expression for F in each case. The first line is F = A - B = I I - 9 = 2. The fifth line is F = A + B = 3 + 3 = 6. Notice that = 1 implies no carry. 3. Comparato1-. Verify the comparator action at pin 14, using a 1-kQ pull-up resistor between pin 14 and +s V. Specifically, record the output at pin 14 for A = llll, B = 1111; A= 1110, B = 1111; and A= 0000, B = 0000. Does it make a difference whether pin 7 is high or low?

en

Table D12-2 S3

S2

s.

So

Cn(7)

A

B

0 0 0 0 1 1 1

l 1 1 1 0 0 0

1 1

0 0 0 0 1 1 1

0 0 0 0 1 1 0

1011 1100 0 100 0000 0011 1000 0000

1001 0011 1000 1111 0011 1001 0001

1

1 0 0 0

Cn+406)

F

0010

experiment

013:

registers (TTL)

Registers are commonly found in the input and output sections of digital circuits. Here they function as a form of memory capable of storing or delaying input-output information. They may also be used to convert a binary number in serial representation into a binary number in parallel representation (serial-to-parallel conversion) or the reverse (parallel-to-serial conversion). In Experiment Dl4 we shall see how registers can be used in computational circuits to multiply or divide binary numbers by factors of 2. A simple 4-bit serial shift register is shown in F ig. D I3-l. This register is designed with master-slave JK flip-flops, so information presented at the J K input is read while the clock is high and transferred to the outputs (A, B, C, D) as the clock goes low. If we wish to store the number 1010 in the register as DCBA = 1010, we must present the most s ignificant bit (MSB) first, as illustrated in Fig. Dl3-l. Also, t he input information must be presented in phase with the clock signal. After four clock pulses, the entire n umber is entered in the register, with the MSB appearing as D and the least significant bit (LSB) as A. Notice that the number must be entered in serial form but that the output is available in either parallel or serial form. The serial output is obtained from Q 0 by pulsing the clock an additional four times. The information stored in the register is transferred out, one bit .at a time, during the four clock pulses. During these same four pulses, new information may be entered through the JK input. Since the contents of the register are "lost," the use of the serial output is said to be destructive. You should also realize that the serial output is delayed from the input by a time which depends on the number of stages in the register. For a series of n MS J K FFs

104

c

D

-

B

A

.

'

_n___ri__ Oo

Oc

J

J

Qo

K

Oe

J

b-

b-

ac

K

QA

b-

I:>QB

K

-

J

QA

K

\1

~

-

Input

JK

-

JlJU1SL

-

Clock

Fig. DH-1 . Four-stage shift register constructed from master-slave JK flip-flops. The operation of the register is synchronous since the clock pulse arrives at each nip-flop simultaneously.

~

0

Ul

EXPERIMENT DJJ

106

regulated by sharp clock pulses of period T, the serial output obtained from the last :flip-flop is delayed from the input by a time t = (n - l)T. The major drawback of this serial register is that it requires three clock periods (n - l periods for the general case) to read the input information . T his difficulty is eliminated by the parallel input capability of the 5-bit register (7496) illustrated in Fig. D 13-2. The preset inputs can be used to simulOutputs Clear

Outputs Oe

QA

Oo

Oe Serial input

7496

G

Ck

A

Clock

Serial inpu t

B

A

c

D

Preset enable

D Preset

E

Preset

Fig. D/3-2. A 7496 5-stage shift register with serial or parallel input and output. Parallel input is accomplished through the present terminals when the preset enable is high. The register must have been previously cleared to zero. (Courtesy of Texas Instruments)

taneously enter input information into all five stages when the preset enable is allowed to go high. This IC is composed of five MS RS FFs, which are set to trigger on the positive-going edge of the clock pulse. To enter serial information, the data must be present at the serial input pin p rior to the rising edge of the clock waveform. The 7496 is primarily intended for storage, serial-to-parallel, or parallelto-serial conversion, but it can also be used as a circulating register (or ring counter). R ing counters are frequently used to generate repetitive signals necessary for control operations within or between digital circuits. As an example, one might use a ring counter to generate a carriage return command for a teletypewri ter. This command in ASCII requires the sending ofOOO and 1101.

REGISTERS (TTL)

107

A ring counter can be fashioned from the 7496 IC by connecting a11y one of its outputs back to the serial input. A 5-bit ring counter is produced by tying Qe to serial input, as illustrated in Fig. Dl3-3. The desired binary number must be entered by first clearing all outputs to 0, and then entering the required ls by using the appropriate preset inputs. When the clock is allowed to pulse, the entered number circulates continuously, passing from the output Qe back to the serial input. An output waveform consisting of ls and Os in the sequence originally entered is available from any of the five outputs.

r

Clear

Operate

o5V

QA

Go

Ge Serial input

Clear

G

Ck A

B

c

D

Preset inputs

From bounce· free

E

Preset inputs

Circulate

~ From pulse generator

Hold

Fig. D13-3. Ring counter produced by feeding an output back to the serial input. The AND gate controls the counter when the clear is high. The ring counter must be loaded through the preset inputs while the counter is on "Hold" with the clear held at high .

EXPERJMENT DJ3

108

PARTS !Cs:

7496 (2), 7400.

Other: 5 LEDs with dropping resistor or the logic probe (Appendix D); (optional) pulse generator.

PROCEDURE 1. Wire the 7496 using the pin connections shown in Fig. D 13-2. Connect your bounce-free switch t o the clock input. Tie preset enable to low and for the moment leave the preset inputs unconnected. (You may wish to monitor the outputs with LEDs.) Turn on the power and clear t he outputs to 0 by momentarily setting clear to ground. Make sure that the clock is low as well. Now con nect clear and serial input to a high. Monitor the five outputs (QA through Qe) while the clock is pulsed. On what edge o f the clock waveform is the information transferred? How many pulses are required to load all l s into the register? After the register has all l s at the outputs, put the clock low, tie serial input to low, and then resume clocking. Determine the number of clock pulses required to completely "unload" the register.

2. Now tie the preset inputs D and E to ground and A, B, and C to 5 V. With the clock low and the outputs cleared to 0, allow preset enable to go high. Verify that the outputs are now in the state QA Q» Qc Q0 Qe = 11100. With preset enable back to low, pulse the clock and observe what happens. Draw the waveforms (voltage versus time) that appear at clock, QA> Q», Qc, Q0, and QE for five complete pulses of the clock. If the state of the register before the first pulse is taken to be the binary number 11100 (or in decimal, 28), does the serial output from Qe present the MSB or the LSB first? 3. Now wire the second 7496 (call this R2) so that the Q8 output of the first register (R 1) is connected to the serial input of R2. Wire the clock terminals of R 1 and R2 together and tie the preset enable of R2 to ground. (Leave the preset inputs open.) Connect LEDs to monitor the output of R2. Turn on the power to both chips and clear them to zero. LoadABCDE= 10100 into RI. Now, with both clears at high, enter five pulses to the clock input of both registers. What is the state of R2? In what form (serial or parallel) are the data transmitted from RI to R2? Note that only two wires a re required for the transmission (a high and ground). 4. Disconnect R2 and set up the ring counter shown in Fig. D l3-3. Use a pulse generator (or offset square wave) to provide the clock signal. Let the

REGISTERS (TTL)

109

output of your bounce-free switch operate the clock gating circuit (7400). Make sure that you have connected Q.e to serial input. Now, with the clock gate off (bounce-free switch at low), load the state ABCDE = 10100. Set the clock frequency to 1 kHz and allow the gate to come on. Observe the output from Qe and the clock input with your oscilloscope (simultaneously, if you have a dual-trace scope). Make a drawing of the clock and output waveforms. Repeat this procedure for an original state ABCDE = 10000.

NOTE As any student of electronics is well aware, technical jargon, acronyms, and abbreviations permeate electronic publications. You might want to test yourself on the following list. The answers can be found at the end of Appendix A. If you miss more than ten it's possible that you have understood all the concepts but will have trouble reading some technical publications. If you miss fewer than/our, feel confident that you can hold up your end of any jargon-filled conversation. RAM DIP LED Modulo-8 JFET MOS

sos TTL PL RTL MSI PROM M/SFF DTL

WOM MOSFET LSI

µP I/O DPDT A/D

LSB CMRR S/N BW BCD ASCII

vco SCR

experiment

Cl3:

registers (CMOS)

The C MOS device 4035 [Fig . Cl3- l(a)] is essentia.Uy a universal shift register. It accepts either parallel o r serial input and provides either parallel or serial output. With connections made as illustrated in Fig. CI3-J(b), the 4035 becomes a shift left-shift right register. The outputs provide either the true contents of the register (T/C a t VDD) or the complement of the contents (T/C at Vss). The parallel o r serial mode for loading data is selected by the state of P/S. When P/ S is low, input is taken in serial form thro ugh the JK terminals. When P/ S is high, data arc loaded through the parallel inputs. In both the serial and parallel modes information is transferred on the positive-going edge of the clock waveform.

PARTS

res:

4035, 4011 (or 4081).

LED:

LED logic monitor, or 4050 (or 4010) and 4 L EDs.

PROCEDURE 1. If you do not already have an LED monitor, wire 4 LEDs directly to the outputs of fo ur buffers in the 4050 (or 4010) package. Yo u may refer to Fig. C3-1 for a pin diagram of the 4050. You may wish to construct the logic probe in Appendix D and leave this probe permanently in place on your breadboard. 110

4035 9 4 Serial in

3 6

Clock Ser.

~

Operate

J

16

K

Voo

Ck

o Vss 7

Voo

10 11 12

PI 1 PI 2 PI3 PI4

P/S

8

5

o Vss

Vss

Reset

o, 1

02 0 3 04

15 14 13

(a) Shift right register

Shift left input Pl 1

PI 2

Pl 3

Pl4

02

03

04

J

Shift right input

K

Clock Right o Vss

Ck

P/S Left

Voo

TIC

Reset

o

Vss

o,

Shift right output

Shift left output (b) Shi ft right - shift left register

Fig. Cl3-l. (a) Shift right register constructed from a 4035 four-stage register. The mode of operation is controlled by P/S; fo r serial loadiogP/S = Vssand for parallel loadingP/S = VDD; (b) shift right- shift left register constructed from the 4035.

111

112

EXPERIMENT C/3

2. Bui ld the shift right register shown in F ig. C13-l(a). Let VDv = 5 V and Vss = 0 V. Connect your bounce-free switch to Clock and your LED monitor to each of the four outputs. Now set up the following condition: JK = I, Ck = 0, P/S = 0 (serial loading), and T/ C = 1 (true contents). Touch Reset to l to clear the counter. Now investigate what happens to the output when T/ C = 0. Restore T/Cto I , and begin pulsing the clock. Describe what happens. How many pulses are required to load all ls into the register ? Now tie the serial input (JK) to 0, and resume clocking. How many pulses are required to completely "unload" the register? 3. Connect PI1 , PI, to Vvv (!)and PJ2 , P/4 to Vss (0). With the clock at low, tieP/S to VDv (parallel loading). Now let the clock go high. What is the state of the output? Return P/S to Vss (with JK still at Vss)and begin pulsing the clock. Draw the waveforms that appear at clock, Q1 , Q2 , Q3 , and Q4 for four complete pulses of the clock. 4. We will now build a ring counter similar to that illustrated in Fig. 013-3 ...Use a 401 l (or 4081) NANO (or AND) to construct a clock gating c ircuit as shown. Set your pulse generator for approximately 1 Hz. Tie the Q 4 output (pin I 3) back to the JK input (pins 3 and 4). This feed back connection will allow the data loaded in the ring counter to flow repetitively through the counter and back to the input. The waveform generated at any of the outputs depends on the initial state of the counter. Any desired initial state can be set up by using the parallel inputs. We begin by loading the state Q1 Q1 Q 3 Q 4 = 1010 as in step 3. Verify that the parallel inputs are still in the condition P/1 = Pl3 = 1 and P/2 = Pl4 = 0. With the power on, place the counter in the "hold" mode as indicated in Fig. 013-3, and let P/S = 1 (parallel loading). Now Jet the clock gate go to "circulate" fo r a short time, and then return the gate to " hold." Verify that the output is in the state 1010. The counter is now in the desired initial state. You may now allow this information to circulate by tying P/S to low and allowing the clock gate to go high ("circulate"). Observe the action of the clock gate. Now raise the clock freq uency to I kHz and d isplay the ou tput from Q4 and the clock input (Ck) on your oscilloscope. Make a drawing of the clock a nd o utput waveforms. 5. (Optional.) With the circuit set up as in step 4, tie T/ C to Vss· The outputs now become the complement of their actual state. When the complement of an output is returned to the input, the register should behave as a shift counter (see Experiments Dl4 and CIO). Make a truth table that describes the behavior o f your circuit (see Fig. D 14-2). 6. (Optional.) Wire the 4035 as illustrated in Fig. Cl3-l to produce a shift right-shift left register. Describe the behavior of this register.

experiment 014:

universal shift register

(TTL)

The TTL universal shift register 74194 illustrated in Fig. DI4-I is a 4-bit bidirectional shift register with four possible modes of operation: ParaUel loading (S1 S0 =II). Serial loading, shift right (S 1 S0 = 01). Serial loading, shift left (S1 S 0 = 10). Clock inhibited (S1 S 0

= 00).

The device incorporates nearly every feature required of a shift register. In this experiment we shall use the 74194 to build a computational circuit that divides or multiplies by 2. We shall also use it to construct a special form of counter known as a shift (or Johnson) counter. The multiplication of a binary number by 2 can be accomplished by simply shifting the number 1 bit to the left (which means adding a 0 to the right side). As an example, consider 5 x 2 = 10, or, in binary notation, 101 x IO = 1010. Multiplying again by 2 gives 1010 x 10 = 10100, or 20. Division is accomplished in a similar manner by shifting the number to the right (or removing a 0 from the right). This process works until the LS.B (the right bit) becomes a I. If the 1 is removed, an error results (e.g., l Ii --;-. 10 is not equal to 011). The error may be rectified by producing a carry which indicates that 0.5 must be added to the decimal equivalent of the resulting number. In this experiment, we shall simply restrict ourselves to numbers divisible by 2. By now you must have noticed that the 74194 can multiply or divide by 2 without the aid of any additional circuitry. The only requirement is that the shift left and shift right serial inputs must be held at ground while the number is 113

114

EXPERJMEN T Dl4

Clear

Clear

Shift right seri al input

Control inputs

s, 0 0 1 1

0 1 0 1

Clock

S1

S0

D

Shift

Gnd

74 194

A

C

leh Parallel inputs

serial input

Mode of operation Clock inhibited (do no thing) Shift r ight (input from pin 2) Shi ft left (input from pin 7) Para llel load (input from pins 3, 4, 5, 6)

Fig. DU -I. The 74194 universal shift register. (Courtesy of Texas Instruments)

shifted. If this p recaution is not ta ken , the shifting of the number results in the addition of ls. Unlike the ring counter (Experiment DI 3), the shift (or Johnson) counter is a true counter. The basic circuit for a shift counter is closely related t o that for a shift register. In fact, the register illustrated in Fig. D13- l can be converted to a shift counter by simply wiring the QDoutput to the input. This counte r will behave as a synchronous counter because the clock input is fed simultaneously to all flip-flops. To understand the operation of the circuit, suppose that the counter is initially in the state QDQcQoQA = 0000 (and Q0 = I). On the next clock pulse, the 1 that is present at the input will be passed on to Q,., but QD, which is applied to the input, will remain equal to I until the fo urth clock pulse. Thus, the outputs will become all l s in four clock pulses. In another four p ulses they will return to all Os. This shift counter, which is comp osed of four flip-flops, will divide the clock frequency by 8. For

UNIVERSAL SHIFT REGISTER (ITL)

115 Clock

5V

Clear

R

0

5V

A

c

B

D

L

1_ -=-

Truth table: three-stage shift counter Pulse

c

B

A

0 1

0 0 0 1 1 1 0

0 0

0 1 1 1 0 0 0

2

3 4 5

6

1 1 1

0 0

Decimal equivalent

0 1 3 7

6 4 0

Fig. D14-2. A 74194 used as a divide-by-6 shift counter.

a shift counter composed of n flip-flops, the division will be by a factor of 2n. This result contrasts with the behavior of an n-stage binary counter, which divides the clock frequency by a factor of 2". Our 74194 universal shift register can be converted into a three-stage shift counter as diagrammed in Fig. Dl4-2. The external inverter is necessary because the 74194 is not provided with complementary outputs. You should notice immediately that the shift counter does not provide an output in any standard form (i.e., BCD, decimal, seven-segment, etc.). Also note from the

EXPERIMENT D14

116

list of decimal equivalents (Fig. D14-2) that states 2 and 5 do not appear. These states represent illegal states. If the counter finds itself in either state 2 or.5, it will become locked into an illegal sequence and will not proceed according to the table given in Fig. DI4-2. A counter can come up in an illegal state when the power is first turned on. Therefore, to ensure the reliable operation of a shift counter, some provision must be made to prevent the counter from finding itself in an illegal state. One method involves sensing the presence of an illegal state with a logic gate and using the output of the gate to reset the counter to 0.

PARTS !Cs:

74194, 7400 (or 7404).

LED:

LED monitor for 4 outputs.

PROCEDURE 1. Connect your bounce-free switch to the clock input of the 74194. Tie pin 7 to ground and pin 2 to 5 V. Monitor the four outputs with LEDs. Turn on the power and clear the output to 0 by momentarily touching Clear to ground. Set up the control inputs (S1 , S0 ) to enter ls from the right (i.e., input to pin 2) (consult Fig. D14-1). Pulse the clock and verify that the ls proceed from QA to Q 0 . Now set up the control inputs for shift left and pulse the clock again. What happens? What would happen if the shift left serial input were high? 2. We will now test the ability of the register to multiply and divide by 2. First connect the serial inputs (pins 2 and 7) to ground. Next set up the parallel inputs to load the number 3, ABCD = 0011. (Caution: A and B must be tied to ground.) Clear the register to 0 by touching pin l to low for a moment. This operation is necessary because Os cannot be entered through the parallel inputs. For example, if A = 0 as the clock goes high, Q,, remains in its former state (0 or l). On the other hand, if A = 1, then QA must become 1. Now load the 3 by setting S 1S 0 = 11 and applying a clock pulse. Now shift the number two p laces to the left. What are the decimal equivalents of the numbers that are produced? 3. Build the shift (or Johnson) counter as shown in Fig. Dl4-2. Disconnect the LED from Q 0 • Since a Qc output is not provided, the Qc output must be inverted. Use a 7400 NAND or a 7404 inverter for this purpose. Clear the counter and begin pulsing the clock. Observe the state of the outputs after

UNIVERSAL SHIFT REGISTER (TTL)

117

each clock pulse. Draw a waveform diagram showing the state of Clock, Q,., QB, and Qc for six clock pulses. 4. Our shift counter has no safeguard against illegal states. To examine the consequences of an illegal state, use the parallel inputs to load a 5. You must use the following sequence : a. Tie B to ground and A and C to 5 V. b. Place Clear to ground and both S, and S 0 to I. c. Allow Clear to return to a high and then connect S 1 to 0. The counter should now be in the state Q,.QBQc = 101. Apply several clock pulses and observe what happens. Can you suggest a way of preventing the counter from entering an illegal state? Give a diagram. [Hint: consider using a logic gate(s).] 5. Now connect the clock of your shift counter to a pulse generator (or offset square wave) set to I kHz. Display the clock and output waveforms on your oscilloscope. Clear the counter to ensure that it is no longer in an illegal state. Draw the waveforms that you observe. Change the feedback connection from Qc to QB and then from QB to QD. By what factor is the clock frequency divided in each case? Optional: Place the counter in an illegal state as outlined in step 4. What happens in this case?

experiment 015:

• memories (TTL)

There is a rich variety of acronyms in the electronics industry, and the field of digital memories is no different. So that you will become acquainted with two of these acronyms, we shall perform an experiment using a randomaccess memory (RAM), which is quite different from a read-only memory (ROM). In Experiment Dl3 on registers, we learned how to enter a sequence of bits into a register and then retrieve the bits one at a time by shifting the register. This is a form of memory with sequential access, meaning that, if we wish to look at, for example, the fifth bit stored in a register, we must first read out the four preceding bits. A more desirable memory is one that alJows us to specify the location of a bit and immediately read that bit out. Magnetic discs on a large computer or semiconductor chips such as 7489 (TTL) or 1101 (MOS) are examples of random-access memory units. Data can be stored (written into) or read out from any location of an RAM simply by presenting the data, a location code, and a Read/ Write command. Like the RAM, an ROM is a memory device which contains data that can be read out randomly; however, unlike RAM, ROM contains permanent data which cannot be altered. The memory of an ROM is nonvolatile, meaning that, if the ROM is removed from the circuit, its memory is unaffected. Information such as a diode-matrix encoder (see Project P6) or set of binaryencoded commands to a computer can be entered onto a ROM and stored indefinitely. The ROM is usually programmed by the manufacturer to the customer's specifications. There are, however, a few "standard" ROMs, such as the 2513 (character generator). RAM may be volatile, as in the case of all semiconductor RAMs, or nonvolatile, as in the case of a magnetic disc or 118

MEMORIES (ITL)

119

magnetic tape memory in a computer. A memor y is described as volatile if the stored information is lost when the power is tu med off. Examples of both ROMs and RAMs are qu ite common in today's hand-held calculators. If a calculator can store several numbers but can only access them sequentially, it contains a register but does not have an RAM (sometimes called a scratch-pad memory). In order fo r a calculator to use any one of several stored numbers, it must make use of an RAM. Scientific calculators have complex instructions that are executed when a key such as "log" or "exp" is struck by the user. These instructions are stored in an ROM. "Programmable" calculators use RAMs and therefore lose all entered data and programs when the calculator is turned off, unless this information is stored on magnetic tape or cards as it is entered into the RAM. An interesting exception to this rule is possible when CMOS memories are used in batteryoperated calculators. CMOS circuits use so little power that it is possible to keep the memory on continuously, even when the main body of the calculator is off. Information can be held in this way for months. The organization of an RAM refers to the fashion in which the number of usable bits are divided among the number of words and the number of bits per word. For example, a memory of 32 bits could use 4-bit words, in which case there would be 8 words in the memory. If there are 8 words in the memory, there would be 8 addresses and we would need three wires (2 3 = 8) for the binary addresses, as shown in Fig. D 15-1 (a). Most memories of N bits are arranged in an N x l format, meaning that a 256-bit memory is likely to consist of 256 words of I bit each. To provide for 4-bit words, four such memories have to be wired in parallel as in Fig. Dl5-l(b). Notice that when the memories are in parallel the address locations are wired together. The normal sequence for writing and reading begins with the memory control off. If the chip is not enabled, whatever information is contained on the chip cannot be read nor can any new information be entered. The chip must be given the proper control signal (high or low depending on the device) before reading and writing can commence. A locatio n is then presented in binary form to the word selection or address inputs. 1f the input to the R/W (read/ write) terminal is high (e.g., in the 7489), the contents of the address given will be available for reading at the output terminals. If the R/W input is low, the bits present at the input terminals will be written into the address given. After the R/W input goes low, it should be returned to 11igh (or the chip disabled) before the address o r data inputs are changed. If the address changes while the R/ W is in the write mode, the input may be written in several unpredictable locations. For this reason the "write" command is u sually a pulse. If high-speed operation is necessary, the manufacturer's data sheets will specify the m inimum possible access time, as well as the minimum times before and after a write pulse that the address information can be changed.

120

EXPERIMENT DJS

Inputs

Outputs

Io

Do

11

D1

12

D2 03

13

Memory 8x4

A2 A1 Ao Addresses la!

1/0 lines

I I 16 x 1

Ao

I I

I

I

16 x 1

16 x 1

Ao

A,

A1 16 x 1

A1

A1

I

I

l( )

I I

I

A0 A 1 A2

Address lines (b)

Fig. Dl5-I. (a) A 32-bit memory; 8 words of 4 bils each; (b) four 16-bit mem ories connected to give 16 words of 4 bits each.

PARTS IC:

7489.

Optional: decade counter and decoder-display (Experiment D8); pulse generator (1 Hz or slower).

MEMORIES (TTL)

121

PROCEDURE I. Scratch-Pad Memory. The 7489 is a 64-bit memory organized in an array of 16 words, 4 bits each. There are four address lines (2 4 = 16), four inputs, four outputs, one enable line, and one R/ W line. The outputs are open collector, so pull-up resistors are needed (see Experiment D3) between the output pins and +5 V, as shown in Fig. DI5-2. To check the operation, present an arbitrary location to the address pins (e.g., 1101 = 13). We can use the fact that open TTL inputs are usually high. With pin 2 (CE) high, record the outputs and inputs. Set pin 2 to low and leave pin 3 (R/W) open. Check the outputs again. Now wire an arbitrary number (7 = 0111 is easy) at the input pins. Has the output changed? Now connect R / W to low mo men+5 v

+5 v

+5 v 1 kn

15

14

13

12

1 kn

11

10

6

7

9

A,

7489

CE

R/W

I,

D,

2

3

4

5

lkS?. +5

v

+5

v

l Fig. DIS-2. Random-access memory (RAM). With switches as shown, the chip reads out the 4-bit word from location 14. If the R/W switch is closed momentarily, the word 1011 will be stored. (Note: We are taking advantage of the fact that open TTL inputs are usually high. If difficulty is experienced, the inputs can be tied to 5 V through 10-kn resistors.)

EXPERIMENT D15

122

tarily and return it to high. What are the outputs? Check the contents of two other locations, word 3 and word 15, for example. Notice two m inor peculiarities. The chip enable pin is actua lly inverted so that a logical zero t urns the chip o n. Also, you should have found that the output data arc inverted. 2. J>i. Memories are difficult to p lay with unless you have a great deal of patience (four wires for the address, four for the bits). Relief can be had by arranging to have so me of t he work done for you. One entertaining t rick is to use a decade counter (with BCD output) to address the chip and a decoderdisplay to look at t he output. Use a pulse generator or bounce-free switch connected to the decade counter to generate bit numbers to use as data. You can generate the address locations by hand or by using a second counter. If there are several groups working in a given labo ratory, this is an excellent opportunity for collaborati on. l f you have r etained your decoder-display fro m Experiment D8, you can easily decode the contents of the memory, as shown in Fig. D15-3. D ata must be entered in the proper sequence. Address locatio ns and data to be stored must be put o n the appropriate pins while the R / W line is high. Data a re stored by momentarily touching the R / W input to 0. We suggest storing the sequence 3.14159265. You might wonder how to store the decimal point. If your display is a simple seven-segment type, with no decimal point, you must blank the disData In

+5

+SV

I•

5 12 9 7490 8 2 3 6 7 11

14 10

7489

v 7448

4

16

+5

v

6

10 12

7 To display

9 11

7490

8

Address -:-

1

point

-:-

Fig. Dl5-3. Decade counters used to address aod load a 7489 memory.

Pull-up resistors at tbe output of the 7489 arc not showo.

MEMORIES (TTL)

123

play. For the 7448, presenting 1111 to the inputs gives a blank. You can use an extra LED as the decimal point by noticing that, when 0000 emerges from the memory, the two most significant Os do not occur in any other digit. Consequently, the NOR gate in Fig. D15-3 lights the LED when 0000 is the memory output. Once the information is stored in the memory, you should be able to read 7t as rapidly as desired by using a pulse generator. F or your report, assume that you wish to be able to display n in parallel form. If you were given eight memories of 64 x I (64 one-bit words), explain how 1t could be stored in the fifty-ninth word. (You will not be able to store all of the digits previously given for n.) How many digits can be stored? Make a block diagram showing the input-output lines, address lines, and decoder-display unit. Assume that the output is not inverted.

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• •

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• • •

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INTRODUCTION 2:

ANALOG CIRCUITS EXPERIMENTS

The circuits studied in this section are all of the analog variety, meaning that the output is somehow proportional to the input. Inexpensive operational amplifiers (op amps) are used for all the circuits, from simple amplifiers to logarithmic amplifiers and active :filters. While tbe circuits were chosen for their educational value, every effort has been made to make the circuits as practical and useful as possible. One great advantage of modern IC op amps is that almost any one of the op amps listed in Appendix B could be used to perform all of the experiments. If you wish to improve the performance of your circuit (higher frequency response, smaller power consumption, etc.), you can select the appropriate op amp from Table I in Appendix B. The op amps we most frequently specify are the 741 and 307 simply because they are cheap and readily available. Most of the op amps used in this section require a bipolar (meaning p lus and minus with respect to ground) power supply within the range of ± 3 to ± 18 V. In practice, a value of ± 15 Vis usually chosen. A ±15-V supply is equivalent to two 15-V batteries connected in series (plus to minus) with the common (or ground) point taken at the interconnection of batteries. The voltages, 15 and - 15 V, are available at the two remaining connections. In the following experiments the common point of the supply is always connected to the point that is shown connected to ground in t~1e circuit diagram. The photograph on the opposite page shows the actual connections required to build a simple inverting amplifier. The amplifier is constructed from a 741C op amp in a 14-pin dual-in-line package (DIP). The picture will probably seem confusing until you become familiar with the board upon which the IC is mounted. First locate the central channel that the IC strad-

+

125

126

INTRODUCTION 2

dies. There are no internal connections across this channel. H owever, any hole that borders the channel on the top is connected to the four holes in a vertical row directly above it. The same is true of the vertical rows below the channel. There are no horizontal connections between these holes. The pins on the IC are numbered consecutively, starting with the lower left (pin 1) and finishing with the upper left (pin 14). The correct orientation of the IC is determined by the notch on the left end. To test your understanding of the circuit connections, you should convi nce yourself that the resistors meet at pin 4 and that they are connected to each other and to pin 4 by the unseen connections within the board. The power supply common (or ground) connection is made to pin 5, the -15-V connection to pin 6, and the + 15-V connection to pin 11.

experiment

Al: operational amplifier

An operational amplifier is a high-gain de amplifier with a differential input. Figure Al-I represents an op amp with a gain of A0 • The op amp is said to be differential because it amplifies the difference between the voltages applied to its input terminals. The output voltage V0 is A 0 (V2 - V,) . A 0 is called the open-loop* gain of the amplifier and is usually greater than 50,000. See Appendix B for typical values. The ( - ) input of the op amp is called the inverting input since Vout = -A0 V 1 if V 2 = 0. The (+)input is called the noninverting input since V00 • = +A0 V 2 if V 1 is grounded. The operational amplifier is seldom used in the open-loop configuration shown in Fig. Al-1. External components (resistors, capacitors, etc.) are used to form a loop, which causes a portion of the output to be returned to the input. This feedbackt is usually negative (meaning applied to the minus input) and determines the closed-loop gain, Ar, which is generally much less than the open-loop gain. Negative feedback causes the performance of the circuit to be controlled almost entirely by the feedback network. Thus, the same op amp can be used in a wide variety of circuits: ac and de amplifiers, integrators, oscillators, filters, regulators, and much more. The circuit in Fig. Al-2 shows an op amp used in the inverting configuration . In the diagram, Z 1 represents an input impedance and Zr a feedback impedance. Both impedances are provided by external components. Frequently, Z 1 and Zr will simply represent resistors. Input and feedback con*In the open-loop condition, there is no feedback from the output to either input. "[Feedback voltages add algebraically. Negative feedback subtracts from the input voltage and positive feedback adds to the input voltage.

127

EXPERIMENT Al

128

Vo

ll

l

Fig. AJ-1. Ideal op amp. Output

= Ao(V2 -

V1).

Z1 (or R1 1

i,

Z; (or R;l S

T VOU1

-=(a)

1V'" 15V

v+ 330 n. 1 w

15 v

15 v. 1 w

Common or ground

40 v -:-

-:-

15 v

Gnd

l

15V. 1 W 0

v- =-

15

v-

v (b)

Fig. Al-2. (a) Inverting op amp circuit with a gain equal to -Z1/Z 1• The ( - ) or inverting input is labeled as the point S and the ( + ) or non inverting input is labeled as the point T; (b) configuration of a bipolar power supply constructed from two separate supplies and from a single supply.

129

OPERATIONAL AMPLIFIER

nections are both made to the inverting ( - ) input. The noninverting ( +) input is connected to ground. Since the open-loop gain, A 0 , is so large, the voltage at S must be essentially zero (vs = v 0 u,/A 0 ::::;; 0). The point Sis said to be maintained at "virtual ground." Making the assumption that v3 = 0, we can write v,n = i,Z, and Vout = i,Z,. Now we need to make use of another important characteristic of op amps: the resistance between the(-) and ( +) inputs is essentially infinite. The open-loop input resistance* Rio,o• is at least 106 n. Almost no current flows into or out of the ( +) and (-) inputs ; therefore, is::::::: 0 ~ i, - i,. The combination of high gain and high input resistance leads to an expression for closed-loop gain that depends only on the values of the external components: (1) When resistors are used as input and feedback components,

A,= -R,

R,

(2)

This is a very important result. It says that the closed-loop gain (we call it A,) depends on nothing but Rr and R,. The output is linearly related to the input. The closed-loop input impedance is (3)

which again is independent of the characteristics of the particular op amp. The closed-loop output impedance is essentially zero for moderate output currents (i0 < 5 mA). Most real op amps are short-circuit protected and limit the output current to some safe value. For the 741 and 307 op amps, the maximum output current is typically 25 mA.

PARTS IC:

Internally compensated op amp, such as the 741 or 307.

Voltage source: de source, 1 V . .Resistors: decade boxes (2) and a I-kn fixed resistor such as a -}-W carbon resistor. Standard equipment:

J- or

de power supplies, digital multimeter.

*A subscript o will be added to all quantities that stand for the intrinsic (open-loop) characteristics of the op amp (e.g., Ao and Rin,o).

EXPERIMENT Al

130

PROCEDURE 1. We will use the op amp in the inverting configuration shown in Fig. Al-2 with resistors forming the input and feedback networks. By referring to the pin assignment sheet at the end of this experiment, wire tbe circuit in Fig. Al-2 using Z, = R, = 1 kQ (the fixed resistor) and Z 1 = R1 = IO kQ (a decade box). Use a bipolar power supply ( 15 and -15 V versus ground) to power the amplifier. Note that the ground of the power supply should be connected to the noninverting input (Fig. Al-2).

+

2. DC Gain. Apply an input of 1 V de versus ground (Vi. = 1 V) and measure the output versus ground. Compare your results with Eq. (1). Repeat this procedure for R 1 = l, 2, and 5 kQ. 3. Virtual Ground. With the resistors restored to R, = 1 kQ and R 1 = 10 kQ, measure the voltage at S with a digital multimeter (DMM). Can you say that the inverting input (point S) is at virtual ground when compared to the input voltage, V, 0 ? A good vacuum tube voltmeter (VTVM) is an acceptable substitute for a DMM. 4. Input Impedance.

Measure the voltage across R 1 (which we will call Vin· Calculate the input impedance from V10 /I1• Your answer, of course, will be very close to R,.. With the input at 1 V and R, = 1 kQ, increase the feedback resistance from 5 to 20 kQ in 2-kQ steps. At what point does the amplifier cease to be linear? Remove the feedback resistor. At what output voltage does the op amp saturate? Repeat this procedure for an input of - 1 V. How are the saturation voltage levels related to the power supply voltages? V,) and use this value to calculate 11• Now measure

5. Output Impedance. Set R 1 back to l kQ and R 1 to 10 kQ. Apply a 1-V input, but now connect a variable resistor, RL, between the output and ground. You can calculate the output current by measuring V0 " ' and knowing the value of RL· Record V0 u, for RL = oo, IO, 5, 2, and 1 k.Q, and 500, 200, and 100 n. Make a plot of V0 u, (vertical) versus Ir. (horizontal). When the op amp is operating in its linear region, V0 u, should be independent of IL. The output resistance, R 0 " " of the amplifier in a closed-loop circuit is A 1 R 0 u,, 0 / A0 • Rout,o is the open-loop output resistance of the op amp as given in the specifications of the op amp. For the 741, Rout,o is approximately 75 n. In principle, to find R 00 , from your data, you should find the difference between Vout when RL = oo (open circuit) and when RL = 10 kQ, and then divide this difference by IL at IO k.Q. However, the difference in V00 t is too small to measure unless you have access to a precise DVM (four and a half or five and a half digits).

OPERATIONAL AMPLIFIER

131

The conclusion must be that the closed-loop output resistance is essentially zero. The slope of your graph of V0 u1 versus h should be given by Rout

_ -

-~Vout ~h

(~is

read as "the change in"). From your graph of V0 u, versus IL> estimate the maximum possible value of Rou•· Be careful to stay in the proper operating region: RL greater than 2 kQ or h less than 5 mA. At higher currents (10 mA and above), you will notice that V0 u, begins to decrease as IL increases. In this region, the short-circuit protection of the op amp is beginning to limit the output current. Estimate the maximum possible output current from your graph.

HISTORICAL NOTE The engineers who are responsible for the development of modern integrated circuits perform their work in relative anonymity. Recognition is seldom given to an individual for development of any particular IC. Most of the work is done by teams and the results are frequently shrouded in industrial secrecy. Also many new ICs are "spin-offs" or derivatives of previous ICs. The fundamental physics of semiconducting materials are more likely to involve famous names (Bardeen, Shockley, Esaki, Zener, etc.) and Nobel prizes. The 741 op amp used in these experiments is a direct descendant of what many consider the original integrated-circuit op amp, the Fairchild semiconductor µA 709. One individual, Robert Widlar, headed the group at Fairchild that developed the 709, and it is Widlar who authored a pivotal paper (in IEEE Transactions in Circuit Theory, January 1966) describing several innovative techniques for producing IC op amps. At the time of the intensive work on the µA 709 (and its early cousins), Widlar had obtained his bachelor's degree less than three years earlier. The journal of the IEEE in which Widlar's paper appeared carries biographical sketches of all the authors contributing to a particular issue. In the January 1966 issue there were many distinguished contributors, most with Ph.D.'s, and several lengthy, scholarly articles. We are safe in asserting that none of these papers will match the impact of Widlar's brief and deceptively simple paper. After working on IC development until 1970, Widlar retired (!) at the venerable age of 32 to an abode somewhere in Mexico. In late 1975, Engineering Times announced, in a front page headline, Widlar's return to the industry as a consultant for National Semiconductor. Widlar's working arrangement with National reportedly allows him to work out his circuit designs without leaving his residence in Mexico.

EXPERIMENT Al

132

TROUBLESHOOTING When elementary circuits such as the ones in thjs experiment do not work, there are several steps that should help to localize the trouble.

+

I. Check for 15 and - 15 V at the pins of the IC itself. Checking the power supply does not guarantee that the voltage is actually getting to the IC. If the power supply voltage is inexplicably low, you are drawing too much current (a short or a poor design). 2. If the IC gets hot, the output is shorted or the polarity of the power supply is reversed. 3. The most common error for expert and beginner alike is simply using the wrong pins on the IC. Look closely at the specification or data sheet : the pin diagram is usually a top view.

4. If Vou• remains satu rated at one of the power s upply voltages, then Rr is open (R 1 = oo ), Re is shorted (Re = 0), the noninverting input is not grounded, or the input s ignal ground is not the same as the op amp ground. You might also find that you have exceeded the common mode voltage range. Make sure that the average voltage between the input pins does not exceed either power supply voltage. 5. Measure the voltage Vsr between pins 2 and 3. If you get more than a few millivolts, the trouble may be that Re is shorted, that R 1 is open, or that the IC has actually failed .

6. If you apply an ac signal and get n othing out, be sure that the output is not saturated at + L5 or - 15 V by an unwanted de component on the inp ut.

741 High performance operational amplifier Typical specifications for ±15 V supply:

A ·Package (top view)

Open-loop gain (A0 ): 200,000 1. NC 2. NC Input resistance (R ;n, 0 ): 2 Mn 3. Offset null 13 4. Inv. input 5. Non-inv. input Output resistance (Rout. 0 ): 75 n 12 6. yInput offset voltage (V0 ,): 2 mV 11 7. NC 8. NC Input offset current (10 ,): 20 nA 10 9. Offset null 10. Output Input bias current (1 6 ): 80 nA s 11. v• 12. NC Supply voltage (max.): ±18 V a 13. NC 14. NC 14

2 3 4

Differential input voltage (max.): ±30 V T Package (top)

Common mode voltage range (min.): ±12 V

1. 2. 3. 4. 5. 6. 7. 8.

Offset nul I Inverting input Non-inverting input yOffset null Output

v·•·

Output voltage swing: ±14 V Common mode rejection ratio (CMRR): 90 dB Short·circuit output current: 25 mA Slew rate : 0.5 V /µsec.

NC

V Package (top)

1. 2. 3. 4. 5. 6. 7.

8

3

6

4

5

Offset null Inv. input Non-inv. input yOffset nul I Output

Open loop voltage gain as a function of frequency

120

y+

8. NC

v,

co ~ c

'iii

"' Q)

"' !!l 0

v

= ±15 TA= 25° C

100

80 60 40

> 20 0 10

5

v-

100

1K

10K 100K 1 M

10M

Frequency (Hz)

Offset voltage compensation: (pin nos. for T and V packages)

133

~ T Package (top view)

1. NC 2. Inverting input 3. Noninvert ing input 4. v5. NC

6. Output 7. v+ 8. NC

307 General-Purpose Operational Amplifier: t ypica l specifications for± 15·V supply: Open -loop gain (A0 ): 160,000 Input resistance ( R;n. 0 ): 2 Mn Input offset voltage V 05 : 2 mV Input offset curren t l os : 3 nA Input bias current (1 8 ): 70 nA Supply voltage (max.): ± 18 V Differential input voltage (max.): ±30 V Common -mode voltage range (min.) : ± 12 V Ou tput voltage swing: ± 14 V Slew rate : 0.5 V/µ.sec Common·mode rejection ratio (CMRR): 90 dB

Open-loop frequency response 120 V Package

100 al

1. NC

1

2 3 4

8 7 6 5

2. lnvening input 3. Noninverting input

4. v5. NC

6. Ou tput 1. v+ 8. NC

~

'""'

80

c:

·~

60

Q)

O'l

....ro

40

>

20

~ ~

·-

~

0

!"\

0 - 20

TA= 25° C V5 •± 15V-

.....

i\ 1

10 100 1 k 10 k 100 k 1 M 10 M Frt!quency (Hz)

experiment

A2:

noninverting a111plifier

Inverting amplifiers, such as those studied in Experiment Al, have input and feedback at the inverting ( - ) terminal. If the op amp is to function as a linear amplifier (output proportional to input), the external connections must provide negative feedback. A linear amplifier always has feedback to the inverting input. This is not to say, however, that the input connection must also be made at the inverting input. Figure A2-1 shows an alternative configuration. To find the closed-loop gain (the gain with feedback), Ai, for this circuit, we must use the fact that the open-loop gain, A0 , of the op amp is very large. Since Vout is limited to + 15 V (or to the maximum voltage of your power supply), the voltage between the ( +) and ( - ) inputs must be essentially zero. Notice that we are not considering a "virtual ground" for this configuration. Neither the ( +) nor the (-) input is at ground. Both input terminals are, however, at the same voltage. The capacitor is present because v 1n will be an ac signal, and we wish to block any de voltage that might accompany the ac signal. If we choose the value of C correctly, it will act like a short circuit for all signals of interest. The capacitor, C, and the resistor, R 6 , function as a high-pass filter. The voltages at the inverting and noninverting input terminals will both be equal to v10 .* Thus, the current through R 1 is i, = v10 /R;. All of i; must pass through R 1 since no current flows into or out of the op amp. The voltage drop across the feedback resistor is i1R 1 , and this must equal Vout - Vin· *Lowercase letters, such as v; 0 , refer to ac quantities. Any de voltage present in the input signal is removed by t he capacitor and does not contribute to Vout·

135

136

EXPERIMENT A2

R,

Fig. A2-1. Noninvcrting ac amplifier.

We can say that VOUI -

Using the fact that

V;,,

=

v,. = ;, R, = i1R1

(1)

i,R11 we can show that Voul _

°V;:- -

R, + Rt R,

(2)

This analysis has assumed that A0 is much larger than A1 . You can show fairly easily that if you include A 0 the result is

(3)

+

In Eq. (3), -P = R,/(R, R1 ). pis the feedback ratio. If you examine Eq. (3) and let A 0 be very large (1 million for example), you will see that A1 ~ -1/ p, which is just Eq. (2). As long as the gain of the circujt is much less than A 0 , Eq. (2) is sufficient. There is one more important feature of the noninverting configuration. The input resistance is essentially determined by R 6 , which is actually in parallel with the closed-loop input resistance of the amplifier itself. This closedloop resistance is the input resistance from the ( +) terminal to ground when R 11 is removed and the amplifier is operating with feedback. For a 741 op amp operating with a gain of JO in the noninverting configuration, the closed-loop input resistance is more than 10 10 Q. We will use an ac signal to measure the gain of the noninvertingamplifier. The open-loop gain of all op amps decreases with increasing frequency. This roll-off in gain will be dealt with in more detail in Experiment A4. For now, the results of step 2 in the following procedure will show that, for a given frequency, the roll-off in open-loop gain causes problems only at hjgh closedloop gain (small p).

NONINVERTING AMPLIFIER

137

PARTS Op amp:

internally compensated, such as 741, 307, or equivalent.

Voltage sources: 1-V de, variable-frequency oscillator, 0 to 1 MHz (0 to 200 kHz is acceptable). Resistors: 1 and 100 kn and a decade box. Fixed resistors of 1, 5, 10, and 100 kn may be substituted for the box. Capacitors:

1 µF or larger.

Optional: 10 µF, 20-WV de (working volts de) capacitors; one aluminum, one tantalum. Most ordinary capacitors are aluminum; tantalum capacitors must be specifically ordered and a1£e more expensive.

PROCEDURE 1. Noninverting Amplifier. Build the noninverting amplifier shown in Fig. A2-1. Use decade boxes for the resistances if you have them. The resistor R, should be about 100 kn. Start with R 1 = 1 kn and R1 = 1 kn. Apply a 1-V ac, 10-kHz input. Make C equal to 1 µFor larger. Measure the gain and compare your result with Eq. (I). Do this for R 1 = 5 and 10 kQ as well. In your report, make a table comparing your experimental value for the gain with that computed from Eq. (I). (Note: we have stopped indicating op amp power supply connections. Remember that these connections must be made.) Calculate the impedance of the capacitor at a frequency of 10 kHz. Js it necessary to include this in your gain calculations? Can you tell from what you see on the scope whether or not the output is inverted? If your scope is dual beam, it is easy to see an inversion. If not, is it possible to arrange to trigger your scope in such a way that you can tell whether the input and output of the amplifier are in phase? Explain. 2. Frequency Response. You will measure the gain of the circuit in Fig. A2-1 at l, IO, and 100 kHz and 1 MHz, with R 1 = I, 10, and 100 kn keeping R; = 1 kn. Although in principle you must measure the input and output voltages for 12 cases, the input should stay constant if your oscillator and oscilloscope have good frequency response. To check the response, put your scope on the input and tune the oscillator from 1 kHz to 1 MHz with the oscillator output voltage set at 0.1 V peak.* If there is no significant (5-percent) change with frequency, you can simply measure the output voltage as a function of frequency and assume that the input is constant. *If your oscillator output cannot be turned this low, build an J J: 1 voltage divider using 1- and JO-kn resistors.

EXPERIMENT A2

138

Use your data to fill in a graph like the one shown in Fig. A2-2. You should notice that the high gain circuit begins to roll off sooner than the lower gain circuits.

100

R1

= 100 kn

=

R1 10 kU ---0- - 10 R1 = 1 kn

10

100

1000

Frequency (kHz)

Fig. A2-2. Closed-loop gain A1 as a function of frequency. The lines are

to be completed with the data obtained from step 2 of the procedure.

Use your data and Eq. (3) to calculate A0 for a frequency of 100 kHz and a feedback resistor of 100 kn. The feedback ratio, fl, is determined by R 1 and R,, while A 1 is the measured gain at the given frequency. Repeat for 100 kHz alld 10 kQ. Comment on the trend of your values fo r A 0 • 3. Voltage Followe1·. Now eliminate R1, R1 , R 8 , and C from your noninverting amplifier as illustrated in Fig. A2-3. Notice that the output is tied directly to (-) input. This direct connection will cause the output to follow (equal) the input as long as the input is within the common-mode range(± 12 V for the 741). [Notice that this behavior is predicted by Eq. (2).) This circuit

l

l Fig. A2-3. Voltage follower.

NONJNVERTING AMPLIFIER

139

bas a very large input resistance and a low output resistance. As such, it is useful for impedance matching purposes. You should verify that Vin = Vout· Also find the maximum (positive) and minimum (negative) voltages where this stops being true. 4. (Optional.) We shall use the voltage follower to compare the leakage currents of two capacitors, a high-quality tantalum electrolytic and an ordinary aluminum electrolytic. Wire the circuit in Fig. A2-4 using the tantalum capacitor. Close the switch to charge the capacitor to 1 V. Now open the switch and measure the time required for the voltage to decay by 5-percent (to 0.95 V). To show that the voltage follower is important, repeat the measurement with the voltmeter directly across the capacitor. Why doesn't using the voltmeter by itself work'?

+ 1v

Leakage

10 µF

v

i Fig. A2-4. Measuring the leakage current of a capacitor using a voltage follower.

Now restore your circuit to that shown in Fig. A2-4 and repeat the measurement for the aluminum capacitor. Calculate the leakage currents for the two capacitors. Recall that i = C(!1V/ !1t). What is the effective resistance of the two capacitors when charged to 1 V? How do these values compare with the input impedance of your voltmeter? (Consult the voltmeter's manual for the latter information.) How does the value compare with input resistance of the voltage follower? (R1n = A0 R; 0 , 0 , where R111 , 0 is the open-loop input resistance of your op amp and A0 is the open-loop gain. Consult Appendix B . .If a 536 FET-input op amp is used here, R 10 can be as high as 10 19 Q!)

experiment A3:

sum and difference circuits

We have previously considered circuits that accept signals at only one of the two input terminals of the op amp (the inverting or the non inverting inputs). So far, the differential character of operational amplifiers has been ignored. In this experiment we shall work with an op amp circuit that provides for simultaneous inputs at the inverting and noninverting terminals. Such a circuit is called a differential amplifier (see Fig. A3-l). In analyzing this circuit, we must again make use of two important principles of op amps: I. Essentially no current flows into or out of either input terminal. 2. The voltage at S must nearly equal the voltage at T (Vs~ Vr)·

The first principle leads to the statement that 11 = 1,

/2 = / 3

and

(1)

The second principle allows us to say (2) where V 3 is the voltage across the ground resistor, R 3 • Looking again at Fig. A3-l, you should observe that the voltages across R 1 and R 1 are, respectively, V1 - V 3 and V3 - V0 w The currents 11 and 11 a re I i-

V1 - V3

R1

(3) I i -

140

V3 - V out R,

SUM AND DIFFERENCE CIRCUITS

141

v,

Fig. A3-J. Differential amplifier.

Now combining these results with Eq. (1) and solving for V0 " " we obtain, after some manipulation, Vout

= V3 ( 1

+ ~~) -

V1 ~:

Finally, we can eliminate V 3 from this expression by using the results given in Eq. (2). We now have an expression for the output voltage, V0 ut• which depends only on the input voltages, V1 and V2 , and the values of the external resistors used in the circuit: u I'

_ out -

V

2 Ri

R 3 R 1 + R1 -1- RJ R,

_

V R1

IR ,

( 4)

The result in Eq. (4) works for all choices of resistor values. If we choose R 1 = R 2 = R, and R 1 = R 3 , the result is considerably simplified: (5) The output is directly proportional to the difference of the inputs. If a floating (ungrounded) source* is attached to the inputs, then V0 " 1 = (R1 / R 1)V;n, where Vin = V2 - V1 • For a floating source, the input resistance of the differential op amp is 2R,. It is important to note that a floating source is maintained above ground. That is, neither side of the input is connected directly to a ground. Differential circuits can be used to connect a floating source to a grounded load without causing the source to be grounded. A circuit designed specifically for matching a floating source to a grounded load is illustrated in Fig. A3-2. Notice that both terminals of the input are maintained at least 2 M.Q above ground. *The simplest example of a floating source is a battery when neither side of the battery is connected to the power supply common (or ground).

142

EXPERIMENT AJ 1 M.\1

1 MU

1 MU 1 MU

Fig. A3-2. Op amp circui t that matches a floating source lo a grounded input.

In addition to the applications mentioned already, the differential op amp circuit is commonly used as a part of an analog computer. You can see from Eq. (4) that the output voltage can be written as V0 u1 = AV2 - BV1 , where A and Bare arbitrary constants. The circuit in Fig. A3-l can be used to perform the analog subtraction of the two algebraic quantities, AV2 and B V1 • The constants A and B are determined by the choice of resistance values in Eq. (4). Another circuit that finds use in analog computing devices is the adder (or summer), illustrated in Fig. A3-3. In this circuit our two op amp principles dictate that 11 + 12 + /3 ~ ! 1 and Vs~ 0. Notice that if we take 11 as flowing from S to V0 u 1 then V0 u 1 = - I1 R1 . If the input voltages are positive, the currents flow in the directions indicated and Vout is negative. Our

v,

R, R2

I,

R3

12

R,

I,

V2

V3 l3 VOUI

Fig. A3-3. Adding circuit.

SUM AND DIFFERENCE CIRCUITS

143

condition on the input currents and the feedback current dictates that

v, +

R1

Vi

R2

+ V3 = R3

Vout

R1

The output voltage of the adder depends on the weighted sum of the inputs (6) The output is the analog equivalent of the algebraic expression, V0 u, = AV, + BV2 + CV3 • If all the resistors are equal, then A = B = C = I. One of the more obvious uses of the adder circuit is the finding of simple (or weighted) averages. The circuit in Fig. A3-4 finds the average of the two inputs [v0 " ' = t(v 1 + v2 ) ] . We should emphasize that none of these circuits is restricted to de inputs. When a time-varying input is connected, the output is the instantaneous weighted difference (Fig. A3-l) o r the instantaneous weighted sum (Fig. A3-3). 10 kS?.

5kS?.

Fig. AJ-4. Simple averager.

P ARTS ICs:

741, 307, or equivalent.

Resistors :

IO kn (3), 47 kn (2).

Voltage sources:

IJ and 3-V de.

PROCEDURE 1. Adder.

= R, =

Build the circuit in Fig. A3-1 using resistances R 1 = R 2 IO k.Q and R 3 = R 1 = 47 kn. Apply de voltages of V2 = 3 V and

144

EXPERJMENT A3

V, = 1.5 V to the inputs. (Note: you may use ordinary dry cells or two de power supplies.) Measure and record the actual values of V 1 and V2 • Measure the output voltage, Vout• and compare your results with the predictions of Eq. (5). 2. Measure the voltages at points Sand T with respect to ground. Are your results in accord with the op amp principle 2? Verify that the voltage measured at Tis approximately given by Eq. (2). Change the value of R 3 to I 0 kn, keeping the other resistance values unchanged. Measure the output and compare with Eq. (4). 3. Floating Source. Restore R 3 to 47 kn. Attach a floating source having voltage V = 1.5 V between the inputs. The only ground connection is made to R 3 as shown in Fig. A3-2. What is the gain of the amplifier? Measure the voltage drops across R 1 and R 2 to obtain the input current. What is the measured input resistance (closed loop) of this amplifier when used with a floating input? In your report, make a diagram of this circuit and indicate with arrows the direction of the currents flowing in each resistor ( /1 , / 2 , / 3 , and I ,.). 4. AC Adder. Build the circuit in Fig. A3-4 with the feedback resistor equal to 10 kn. Connect two separate. ac sources that originate from the same supply (if possible). For example, add a sine wave to a square wave, or a pulsed waveform to a square wave, etc. Check the inputs and the output to verify that the circuit is summing the inputs. lOkn (100 Hz)

si n wt

Vl

(300 Hz) v 2

! sin 3wt 30 kn 1o kn

(500 Hz) v3

i sin 5wt so kn

Fig. A3-5. Summing circuit that approximates a 100-Hz square wave using three terms of the Fourier series.

SUM AND DIFFERENCE CIRCUITS

145

5. Fourier Synthesizer (Optional). A summing circuit can be used to generate the first three terms in the Fourier series expansion for a 100-Hz square wave (Fig. A3-5). The square wave is approximated by the sum, sin mt + -l sin 3 rot +-}sin Smt + . ... The symbol OJ equals 2n times the frequency of the wave. The output of the circuit in Fig. A3-5 will approximate a 100-Hz square wave with a peak amplitude of 1 V if v 1 = 1 VP' 100 Hz; v2 = l VP, 300 Hz; and v 3 = I VP, 500 Hz. As more terms are added to the series, the approximation becomes better and better. (Caution: this part requires the use of phase-locked sources. All three sources must be kept in phase with each other. Oscillators with a phase-locking capability may be purchased from Gen Rad Co.)

experiment A4:

real op amps

Operational amplifiers can be considered to be "ideal" for the majority of circuit designs. An ideal op amp has infinite gain, infinite input impedance, zero output impedance, and no voltage or current offsets. However, the lim itations of every op amp are specified by its manufacturer, and these lim itations must be considered if you intend to use au op amp in any "extreme" situation . The extremes that most commonly cause trouble are low voltages, high frequencies, small current inputs, or large current outputs. Table A4-l will give you some idea of when to expect such problems. Some of the problems of real op amps can be circumvented by purchasing a special op amp intended for specific applications (see Appendix B). For example, JFET or MOSFET input (CA3140, 536, and 356) op amps are excellent fo r use with low current levels and/or high source impedances. The 307 op amp has a very small current offset, while the 318 op amp has a very large maximum slew rate as well as excellent frequency response. Both op amps are intended as a pin-for-pin replacement for the 741. Perhaps your application requires that the op amp be powered by batteries. In this case, power consumption is important, and your best choice may be a 308 micropower op amp. If your application does involve one of these "extremes," you will have to agonize over a common problem: is it necessary to spend more money on a better op amp or will a 741 and some extra external circuitry suffice? In the following sections we shall treat each problem in some detail.

Output Current and Input lmpetlance. The problem of current offset will be taken up in Experiment A8 (cure: buy a better op amp). The other

146

REAL OP AMPS

147 Table A4-1

Extreme

Problem

Typical (741) Specification

Cure

Differential input voltage < JOmV

Offset voltage

2mV

Internal or external offset circuit

Common Mode Voltage > 12 v

Restricted input voltage range (the common mode range)

± 12 v

Voltage dividers on the inputs of the op amp

Frequency > 10 kHz

Ao decreases as frequency increases, slew rate

A 0 = 1000,10 KHz = 100,100 KHz .5 V/µscc

Better op amp such as 318

Input current < 0.1 µA

Input bias current

SOnA

Better op amp such as 308 or CA3J40

Input signal impedance > lM.Q

Finite input impedance

2M.Q

Voltage follower (See Experiment A3)

Output current > lOmA

Output current limitation

25 mA

Current booster or power amp (see Experiment AIO)

extreme, large output current, is more difficult to solve. If you need power, you must pay for it either in money (buy a power amplifier such as a Kepco BOP) or in time (use a power output stage as in Experiment AJO). The finite input impedance of an op amp is infrequently a problem, but, if an input impedance in excess of 10 MD. is needed, you can use a noninverting amplifier circuit called a voltage follower. A 741 op amp used as a voltage follower has an input impedance in excess of 10 1 1 Q (see Experiment A2). Slew Rate. The slew rate is a parameter that specifies the maximum rate at which the output voltage can change. It is usually stated as the number of volts per microsecond. For example, if an op amp has a slew rate of 1 V/µsec, and the output changes from 0 to lOV, it will take more than 10 µsec to do this, regardless of how rapidly the input is changed. Refer to Fig. A4-1 for the response of a 741 op amp to a step input. Occasionally, a slew rate limitation will leave the amplitude of the output signal unaffected, but wiU introduce distortion. See Table A4-2 for the minimum slew rates necessary to faithfully reproduce a variety of IO-kHz, 1 VP-P waveforms. The slew rate can be calculated quite simply from information

EXPERIMENT A4

148

Fig. A4-1. Response of a gain-of-100 amplifier to a step change in input voltage. The amplifier is constructed from a 741 op amp with a slew rate specified to be 0.5 V/µsec. Input is shown by the lower trace, output by the upper trace.

Table A4-2 Waveform (lV,p - p)

Max Slew Rate (V/µscc)

10-kHz sine wave 10-kHz triangle wave 10-kHz square wave Square wave with 0.5-µs rise time

0.063 0.02 Infinite 2

obtained from an oscilloscope trace: slew rate =

(!:l.~ou•) LJ.t

= maximum slope of output versus time max

Notice from Table A4-2 that for a good square-wave signal having a 0.5-µsec rise time (0 to I Vin 0.5 µs), the requ ired slew rate is 2 V/µsec which already exceeds the typical value for a 741 op amp (0.5 V/µsec). Offset Voltage. Although there is no input signal (v1n = 0) in Fig. A4-2, the output, V0 • ., will not equal 0. Even when via = 0, every op amp has a small voltage, Vos = V ST> appearing between the inverting and noninverting

REAL OP AMPS

149

t10 kil -15

v

Fig. A4-2. Internal offset circuit for 741 op amp. Pin numbers shown are

for eight-pin packages.

inputs. The error caused in the output is Output voltage error

=6.

Vout

= Vos R,

J, R,

(I)

This error adds to the output voltage when the input is not equal to 0. For our inverting amplifier, v0 u1 = -(R1 /R,)v 1a + 6.V0 ui· The offset voltage is usually not a problem for ac signals since a capacitor can be put in series with Voui· The capacitor will block any de voltage from reaching subsequent instruments or amplifiers. For de signals, however, a 1-mV offset and a gain of 100 combine to give a 0.1-V error in the output. The input offset voltage can be canceled by adding a small voltage between the noninverting input and ground. The voltage divider circuit in Fig. A4-3 will provide a small positive or negative voltage to cancel the offset voltage of the 741. T o analyze the maximum and minimum offsets this circuit can cancel, you should simply consider the 68-k.Q and 47-n resistors to be in series between 15 V and ground. The 10-k.Q pot is so large compared to 47 n that the circuit funct ions as a simple voltage divider. Wben the pot .is turned from one extreme to the other, the offset correction changes from its maximum positive value to its maximum negative value. Jn order for the correction circuit to function properly, the ground between the two 47-n resistors is absolutely necessary. If all the resistors have only 10 percent tolerances, the junction of the 47-.Q resistors could be as much as 1 V above or below 0. Consequently, we must "tie" (connect) this junction to ground. The 741 is unusual in that it has a "built-in" internal offset circuit which can be connected as shown in Fig. A4-2. This feature of the 741 eliminates the necessity for the external correction circuit in Fig. A4-3. We should point out that occasionally one needs to build an amplifier with an

EXPERIMENT A4

150 +15 v

68 k!1

-15 V Fig. At/-3. External offset circui t.

adjustable zero point. In this case the required offsets are large and can only be accomplished by using an external circuit, such as that shown in Fig. A4-3. Frequency Response. At high frequency, all capacitors become increasingly like short circuits and all inductances like open circuits. T hese effects limit the maximum possible gain of any circuit at high frequencies. An additional effect that becomes a problem in op amp circui ts is the dependence of phase shift on frequency. Op amps are designed to have a phase shift of 180° between the inverting input and the output, but at high frequencies this shift can be reduced by as much as 90° or more. Oscillations can occur if the total phase shift in the closed loop is reduced to 0 or increased to 360°. By connecting a capacitor between output and input, the high-frequency gain of a circuit is reduced and the circuit is said to be compensated. For reasons beyond the scope of this text, a roll-off (decrease in gain) of 6 decibels/ octave (dB) (or 20 dB/decade) is sufficient to ensure that the amplifier is stable and does not oscillate even at high frequency. Some op amps, like the 741, 318, CA3 140 and 307, are internally compensated, meaning that beyond some frequency (JO H z for the 741) the openloop gain, A0 , falls at a rate of 6 dB/octave. Other op amps, such as the 709, 301, and 308, require external capac.itors and/or resistors for compensation.

REAL OP AMPS

151

Data must be obtained from the manufacturer to determine the values of the external components and the proper connections. The oscilloscope photograph in Fig. A4-4 shows the response of a 741 op amp used with a gain of 100 for input frequencies extending from 50 to 500 kHz. Notice that the gain falls by about a factor of 10 in going from 50 to 500 kHz. Thus, the output of the amplifier is rolling off at a rate of 20 dB/ decade(6 dB/octave) over this range of frequency. Within this region the gain of the amplifier is limited by the open-loop gain of the 741.

Fig. A4-4. Response of a gain-of-100 amplifier constructed from a 741

op amp to an input within the frequency range of 50 to 500 kHz. Output o f the amplifier is shown by the upper trace.

PARTS Op amps: 741, 709, and 3 18 o r CA3140 (recommended); or 301 A in place of 709. Resistors:

47 Q (2), 120 n, 1.2 kQ (2), 12 Q (2), 120 kQ, 1.2 MQ.

Capacitors : 3 pF, 10 pF, 0.1 µF.

PROCEDURE I . Maximum Slew Rate. Set the amplitude of an oscillator with a square-wave output to 1 V and the frequency to IO kHz. If your oscillator has an appreciable de voltage in addition to its ac output, it will be necessary

152

EXPERIMENT A4

to block this de signal with a capacitor between the oscillator and amplifi er. Observe the square wave at the output of the oscillator and determine the time required for the wave to fall from its maximum to its minimum output. If your oscillator is very good, the time interval may be so short that you can only place an upper limit on the "rise time." Make a drawing of the squarewave edge as you observe it on the scope and be sure to label both axes. (If your rise time is greater than l µsec, your oscrnator is not good enough to complete the rest of this part of the experiment accurately.) Construct an inverting amplifier with a gain of 10 using an input resistor of about lO kQ. Build the circuit with a 741 op amp. If your square-wave generator has a de component of0.2 V or more, place a capacitor with a value of "'0.1 µ F between the generator output and the input resistor of the amplifier. Apply the oscillator signal to the op amp circuit (using the capacitor if necessary). Now observe the output of the gain-of-10 amplifier. You will notice that the square wave no longer rises (or fa Us) as sharply as the oscillator output did. Calculate the slew rate (change in voltage/change in time). Take the change in voltage as the difference between the maximum and minimum output. There will be rounding of the square wave, so the time will be somewhat bard to judge. Make a drawing of the output square wave and indicate the points on the curve you used to determine the slew rate. Compare your calculated slew rate with that given on the 741 data sheet. Comment. If a 318 or CA3140 op amp is available, substitute it for the 741 and measure the slew rate. (Both are pin for pin compatible with the 741.) 2. Input Offset Voltage. Construct an inverting amplifier using a 741 op a mp to give a gain of approximately 100. Apply a 0 input signal by connecting R, to ground as shown in Fig. A4-2. Measure the output signal, V0 " " with a DMM. Use Eq. ( I) to calculate the input offset voltage, Vsr, causing this output. If your voltmeter is sensitive enough, measure the voltage offset between the(- ) and (+)input terminals and compare to the calculated voltage. Connect a potentiometer (10 kQ) as shown in Fig. A4-2. Measure the output voltage at both extremes of the potentiometer's travel. Can you set the output to 0 within the limits of your digital voltmeter? Short the inverting and noninverting inputs directly. Measure and record the output voltage. Could you have anticipated this result from your previous calculation of offset voltage ? 3. Extel'flal Offset Circuit. Remove the pot from pins I and 5. Most op amps do not have internal offset circuitry, and an external circuit similar to that in Fig. A4-3 must be used. If you do not have the exact resistor values shown , select anything close. Using the component values you have chosen, calculate the limits of the voltage provided by your offset circuit. Before completing the connection between the offset circuit and the noninverting input, measure the voltage Umits with your DMM. Compare these measured values

REAL OP AMPS

153

to your calculated values. Complete the connection to the (+)input and test the effectiveness of this circuit by measuring the extremes of V0 " 1• Record these values. Can you set V0 " 1 to 0 more easily with this external circuit or with the internal offset of step 2? 4. Frequency Compensation. Use a 709 op amp as shown in Fig. A4-5. Verify that your circuit works by applying the oscillator through a 120-kQ resistor to the (-) input and check for the proper gain with an input signal of 10 kHz and 1-V amplitude. Use C 1 = 10 pF, C2 = 3 pF, and R; = 0. (If the 301. A is substituted for the 709, tie C 1 between pins 1 and 8.) These component values are not critical. Remove the input signal and then remove C2 as well. In many cases, the circuit will go into an interesting high-frequency oscillation of several volts amplitude. If your op amp does not cooperate and you would still like to see t his spontaneous output, try a gain of 1000, using the l .2-k!1 input resistor of Fig. A4-5. 1.2MS1

Fig. A4-5. The 709 op amp with the external components necessary for

frequency compensation.

To use the 709 with a gain of 1000 (60 dB), we must limit the input to about 10 mV maximum. If your oscillator is unstable at this low level, set the oscillator to I V, make R,i = I k!1, R8 = IO n, and the input to the op amp circuit will be about IO m Y. This voltage division and then amplification will inevitably cause the output to be "noisy." There is nothing that can be done about the noise for the time being. Set the input at about 10 mV and let R 1 = 1.2 k!1 as shown in Fig. A4-5. Measure the gain at 10, 20, 40, 100, 200, 400, a1Jd 800 kHz. Does the gain at high frequencies agree with the data sheet for the 709? (For the 301 A compare your results with curve 2 on the 709 sheet.) Calculate the roll-off in decibels/octave (above 100 kHz). Compare this to the response of the 741 op amp measured in Experiment A2. If you do not have any results for Experiment A2, the characteristics for the 741

EXPERIMENT A4

154 are similar to a 709 with C1 = 5000 pF, R 1 (or C 1 = 30 pF for the 301 A).

=

1.5 k!1, and C2

=

200 pF

HISTORICAL NOTE In a peculiar way, success in making a useful and widely accepted IC like the 741 or 709 breeds an inevitable disaster. If the circuit is successful, many companies will rush to produce the same item, and this competition drives the price of the IC drastically lower. The µA 709 was introduced by Fairchild Semiconductor in 1965, and by mid-1967 several companies were offering their versions of the 709. To gauge the actual cost to the consumer of the 709 in the "early days," we can find an advertised price of $4.50 in the surplus marketplace during the summer of 1968. A year and a half later the surplus price had fallen to $1.50, and after one more year a µA 709 could be purchased for about $0. 50. The pricing policies of the semiconductor industry are clearly based on vigorous competition. Today's most widely used linear IC, the 741, was introduced in the late 1960s and was available as a surplus item for $3 in 1970. In a year and a half its price had fallen by a factor of 3. This pattern of falling prices is' very familiar and very beneficial to the users ofICs. It is almost axiomatic that if a new integrated circuit is a truly useful device it will soon be cheap.

Pin Assignment Sheet: 709 (See Appendix 8 for other specifications) DIP (A package):

T0-5 (T package) :

1. NC 2. NC

1. 2. 3. 4. 5.

Input compensation A Inverting input, inv. Non inverting input, NJ. Nega tive supply, vOutp ut compensation 6. Ou tpu t, V0 u 1 7. Positive sup ply, v+ 8. Input compensation B

3. Comp. A 4. Inv 5. NJ. 6. v7. NC 8. NC 9. Outcomp. 10. V OUt 11.

v•

12. Co mp. 8 13. NC 14. NC

Open-loop gain vs frequency

2

3

·~ External com pensatio n components: pin nos. for T0-5

40 1---1-----'~~d---+--'1.--+----l

CJ

10 100 1000 10,000 Frequency (kHz)

C1 (p F) 5000 500 10

1.5 1.5 0

200 20 3

155

Pin Assign ment Sheet : 318 (See Appendix B for other specifications) To-5 package:

DIP package:

1. Balance compensation 1, BC 1 2. Inverting input , Inv. 3. Noninverting inpu t, N. 1. 4. Negative supply, v5. Balance compensation 3, BC3 6. Output, V0 " ' 7. Positive supply, v• 8. Compensation 2, C2

1. NC 2.NC 3. BCl 4. Inv. 5. N.I. 6. v7. NC 8. NC 9. BC3 10. V OUl 11. v• 12. C2 13. NC 14. NC

Offset balancing circu it:

v·

2

3

v

156

Pin Assignment Sheet: 301 A (See Appendix B for other specification) To·5 or m inidip package: 1. Freq. comp/offset null 2. Inverting input, Inv. 3. Noninterting input, N.I. 4. Negative supply, V5. Offset null 6. Output, V0 u, 7. Positive supply, v+ 8. Freq. comp.

DIP package: 1. NC 2. NC 3. Comp/offset 4. Inv.

5. 6. 7. 8. 9. 10. 11. 12. 13. 14.

N.I.

v-

NC NC Offset Output

v·

Comp. NC NC

Typica l offset null and compensation: Pin nos. for T0-5 or minidip

2

30 p f

157

experi111ent

AS:

integrating and differentiating circuits

Operational amplifiers are frequen tly used to perform the electronic analog of mathematical integration and differentiation. The integrator produces an output signal that is proportional to the area under a curve of input voltage versus time (written as f v,dt). The differentiator produces a signal proportional to the slope of the input voltage (v,) at a given instant (i.e., the rate of change in v,, written as dv,/dt). A differentiating op amp circuit is shown in Fig. A5-1. The output of this ci rcuit is given by Vo = -

R I C, -dv, , (.{

(1)

Since the circu it uses the inverting configuration (signa l input and feedback to the inverti ng input), the gain for a sine wave is

(2) Notice that the gain depends directly o n frequency. The large gain at high frequencies tends to drive the circuit into oscillation. This difficulty can be eliminated by the addition of an input resistor and/or a feedback capacitor as shown in Fig. A5-2. As long as z,::::: Xe, and Z 1 ::::: R1 , the circuit will continue to function as a differentiator. These conditions m ean that R, is small compared to l/ 2nfC1, and 1/ 2nfC1 is small compared to R 1 . The presence of the other components, R 1 and/ o r C1 , acts primarily to limit the gain at high frequency. Suppose that we add just the resistor R 1 • For

158

159

INTEGRATING AND DIFFERENTIATING CIRCUITS

R,

C; V; o-------j 1 - - - --

--i

>--

-- 0.

To obtain a functioning Schmitt trigger, we must also agree on a circuit that produces a nearly constant reference level. In Experiment A9, you will learn how to build a reference voltage supply that has great stability. For now, either of the circuits in Fig. A7-4 will suffice. To maintain a constant output, the reference source must have an effective internal resistance that is small in comparison to its effective load resistance. In this case, the effective load resistance is close to the value of Rfl . The circuits in Fig. A7-4 have been designed with an internal resistance of about 1 kn, so R 11 should have a value of 100 kQ or more.

PARTS Op amps:

318 (or CA3140) and 741 (or 307).

Resistors:

470, 47, 10, 4.7, 2.2, and J.5 kn; and a 1-kn pot.

174

EXPERIMENT A7 +15

+15

v

v

v,., 2.5 kn

(a)

- 15 v (b)

Fig. A7·tl. Two simple circuits for obtaining a reference voltage.

PROCEDURE 1. Build the Schmitt trigger as shown in Fig. A7-2. Use a 741 or 307 op amp. Let R, = 10 kfl, R 11 = 470 Hl, and R12 = 47 kQ. For the moment, tie point A to ground (V•• r = 0). Apply a 50-Hz triangle- or sine-wave input of about 5 V peak and observe the output with your oscilloscope. If you have a dual -trace scope, observe the input and output simultaneously.* Estimate the values ofV0 N and VoFF· Is there a negative or a positive edge in the output when V1n = V0 N? When V; = VoFF? Measure and V~ 1 • 2. Increase the frequency to 3 kHz and observe the effect of the finite slew rate of your op amp. Measure the slope of the transition from low to high (in microvolts/second). Now insert a 318 or CA3140 op amp. Measure the new slew rate. (You may wish to increase the frequency further.) 0

v:..

3. Now disable the sweep on your oscilloscope and connect the output to. the vertical channel and the input to the horizontal. Reduce the frequency to the lowest possible value (or 0.2 Hz) and compare your pattern with that shown in Fig. A 7-3. Make a drawing indicating the path that the trace follows. *If you have a single-trace oscilloscope, monitor the input while you trigger your scope with the output of the Schmitt trigger. Use the ± slope selector on your oscilloscope to trigger on the positive or negative edge of the output.

OP-AMP SCHMITT TRIGGER

175

4. Increase the frequency to 50 Hz. Measure VoN and~ V for R12 = 47, 4.7, and 1.5 kQ. You may wish to reduce the peak-to-peak value of the input for the lower values of R 12 . Do your results agree with Eq. (3)? 5. Now build the reference voltage circuit in Fig. A7-4(a). Connect the reference voltage to point A. With Rf'l, = 4.7 kQ, measure VoN and~ V when Vr.r = I, 2, and 3 V. Do you find agreement with Eq. (4)?

experiment

AB:

logarithmic amplifier

An amplifier that has an input-output characteristic of

= B 1og10 V + C

(1) is called a logarithmic amplifier. In Eq. (1), B and Care simply constants whose value depends on the details of the amplifier design. MultipJjcation and division are the most obvious uses of a logarithmic amplifier. If the outputs of two log amps are added and the sum used as the input to an antilogarithmic amplifier, the final output wiH be proportional to the product of the two input signals. The operations of division, squaring, or raising to a higher power can be accomplished in a similar manner (at least in principle). Logarithmic amplifiers are commonly used to compress an input signal that ranges over several decades in magnitude into an output signal that varies over a relatively narrow range of voltage or current. For example, we might wish to use a 1-Y, full-scale meter to monitor a voltage that ranged from 10 m V to 100 V. Using nothing but a voltage divider to reduce the maximum 100 V down to a usable 1 V would cause the low end of the range to be reduced to 100 µV. A better solution would be a logarithmic amplifier. Suppose that the constant Bin Eq. (1) is set to be 0.060 V and C to 0.400 Y. Then an input of 10 mV gives an output of0.280 V, while 100 V gives 0.520 V out. Clearly, the logarithmic amplifier bas a disadvantage: it is difficult to detect small changes in the input signal. All logarithmic amplifiers make use of the current-voltage relation for a forward-biased pn (or np) junction: Vout

I 176

= /0 [exp k~

1

-; IJ

(2)

LOGARITHMIC AMPLIFIER

177

In Eq. (2), / 0 is a constant, usually about 10- 1 1 amperes (A), and + q/kT is another constant term that depends on temperature. At room temperature, q/kT equals 1/0.040 V. The voltage across the junction (forward biased) is V, and the current that flows is /. If Vis considerably larger tban 0.04 V, Eq. (2) reduces to I = / 0 exp(V/ V0 ), where V0 = 0.04 V. Jfwe take the logarithm (base 10) of our expression for I, we find log 10 I - log 10 10 =

_1 0 060

V

(3)

The trick to making a logarithmic voltage amplifier is to notice that, if we can make the current through the pn junction directly proportional to an input voltage, Vin, we can rewrite Eq. (2) to obtain a result similar to Eq. (1). For the circuit in Fig. A8-l, we can say that the input current, I,, is equal

I; Vin 0-___,_J\/\f',,/\.-_._-1

Fig. AB-1. Simple logarithmic amplifier.

to Vi 0 / R,. Also the current through the diode D 1 is equal to Ir, and Ir = I,. You should notice that since the inverting terminal is at virtual ground the voltage across the diode is simply equal to V ut' The diode will be forward biased when V0 u, is positive. In this case we can use Eq. (2) to write 0

Ir = lo exp qVout = 11 = Vin kT R;

or simply

I0 exp q Vout _ Vi• kT - R 1 Taking the base 10 logarithm of both sides yields an expression similar to Eq. (1): + V0 u1

=

0.060 log 10

Vin - 0.060 log 10 ! 0 R1

(4)

If we take / 0 to be 10- 11 A and R, to be l 00 kn, the last term in Eq. (4) will be +0.360 V. There are restrictions on the use of Eq. (4). The most serious condition is that Vin must be negative so that the diode will be forward biased. Also, V0 "' should be larger than 25 m V to allow us to ignore the -1 in Eq. (2). The

178

EXPERIMENT AB

current in t he feedback loop may be quite small. A typical value for I1 is 1 µA; thus, an input bias current of greater than 0.1 µA will cause an appreciable error. Finally, if the current through the junction is appreciable, the "bulk" resistance (usually less than 100 Q) can no longer be ignored. These difficulties indicate that if accuracy and predictability are required, it may be wise to buy a commercial logarithmic amplifier.* If an inexpensive op amp is used, the specified input bias current should be chosen to be as low as possible. A glance at the table of op amps in Appendix B suggests that the best choice is an FET input op amp such as the CA3140, 536, or 356. Another possibility is the 308 op amp. Tbe choice of which kind of pn junction to use is rather difficult. The best resu lts are usually obtained with silicon junctions-either a rectifier diode or the base-emitter junction of~ transistor.

PARTS Op amps: CA3140, 356, 536, or 308, or equivalent op amp having a low bias current (four for the optional experiment). Capacitors : 30 pf for frequency compensation if 308 is used. Resistors: 100 kQ (optional part requires one 10-kQ and seven 100-kQ resistors, and one 10- or 25-kQ potentiometer). Diodes: one silicon-rectifier type. Voltage source: one de source capable of l mV to l 0 V.

PROCED URE 1. Construct the circuit in Fig. AS-1 using a CA3 l40, 356, 536, or 308 op amp. A 741 op amp may be substituted if a low bias current device is not available. There are a large number of silicon diodes that can be used in this experiment. The kind that usually works the best is a relatively large rectifier diode or one arm of an encapsulated bridge rectifier. Virtually any diode will work for large values of input voltage, but the response for inputs of less than 100 mV depends critically upon the particular diode. To measure the input-output characteristics of the circuit, measure V0 • 1 and V. when V;. = -1, -10, and -JOO mV, and - 1 and - 10 V. If your de power supply cannot provide. usable 1- and 10-mV signals, make a 0

•Two companies, Analog Devices and Philbrick-Nexus, sell a wonderful variety of high-performance op amps (FET inputs, chopper-stabilized, etc., as well as log amps) and also have very nice catalogs. You can find the addresses in Appendix A, but don't expect any bargains.

179

LOGARITHMIC AMPLIFIER

voltage divider circuit that divides by 1000 (use a 100-kQ and a 100-Q resistor). You can generate the required millivolt signals by using the voltage divider in conjunction with your power supply. Compare your data to the graph in Fig. A8-2. The slope of your graph should theoretically be 60 mV/ decade; that is, the output should change by 0.060 V when the input changes by a factor of 10. How does the value of the input resistor affect the graph? 0.5

0.4

VOUl

0.3 -

0.2

0.1

1 mV

10 mV 100 mV

1V

10 V

Fig. AB-2. Data obtained using a 307 op amp and a general-purpose

silicon diode in the circuit of Fig. A8-J.

2. Two difficulties limit the response of the logarithmic amplifier: input bias current and input voltage offset. If the bias currents of the op amp are appreciable compared to the input current, the output will be affected. Would the bias current be a problem for an input of 1 mV using a 307? a 308? a 356? A second difficulty, the input offset voltage, becomes important when the input voltage is small. An input signal of I mV is smaller than most voltage offsets encountered with inexpensive op amps (see Appendix B). For this part of the experiment, construct an input-offset correction circuit. (See Fig. A4-3 if you are using a 308; or see the pin assignment sheet for the CA3140, 536, 356 at the end of Experiment A6.) To zero the output, temporarily replace the diode with a 1-MQ or larger resistor. Set Vi to 0 (ground it) and vary your offset control until V0 " ' is 0. Now replace the diode and repeat your measurements at - 1 m V, -10 m V, etc. There are many clever schemes for improving the performance of logarithmic amplifiers, but the time and expense involved usually indicate the wisdom of purchasing a commercial unit. One low-cost logarithmic amplifier is the CA3091, available from several surplus supply houses. 0

180

EXPERIMENT AB

3. Antilog Amplifier. To perform the mathematical operation of inverse log (which is actua!Jy exponentiation), the diode need only be connected to the op amp as shown in Fig. A8-3. Measure the input-output characteristics of this circuit. You will notice that the expected resu It,

AVin + B range of Vi. (usually

log 10

Vout

(5)

=

is obtained only for a limited between 0.3 and 0.6 V). Clearly, if you wish to use an antilog amplifier, the input signal must be "conditioned" to lie in the usable range of the amplifier. 4. Analog M ultiplier (Optional) . The circuit shown in Fig. A8-4 bas an output that is proportional to the product, V1 x V2 • The first two logarithmic amplifiers feed their outputs to a simple adder. At the output of the adder, the signal is equal to 0.060 log V 1 0.060 log V2 , plus a constant. Since

+

100 kQ

Fig. AB-3. Antilogarithmk amplifier.

R 100k~

100 kn

-=-

100 kn

10 kn

-15V~

Fig. AB-4. Analog multiplier.

LOGARITHMIC AMPLIFIER

181

+

adding logarithms is the same as multiplication (log xy =log x logy), the input to the antilog stage is just 0.060 log ( V1 V2 ), plus a constant. Since the antilog circuit works for only a limited range of input voltage, there is an offset control added to the noninverting input. Typically, the output of the adder might be between - 0.6 and - 0.8 V, and the desired offset would be in the range of - 0.3 V. For input signals of approximately 1 Veach (negative), vary the offset control until V00 , is approximately 1 V. By varying V 1 and V2 , can you verify that V00 , is proportional to V1 x V2 ? What is the effect of varying R? Once the multiplying circuit of Fig. A8-4 is completed, it is very easy to construct an analog "square" or "square-root" circuit. By eliminating V 2 (or keeping it constant) and changing the value of R 1 , you can make the V 00 , proportional to the square, cube, square root, etc., of Vi •. Can you explain bow to do this? (Hint: if you multiply a logarithm by 2, the result is the same as squaring the number.) If time permits, check the operation of the circuit with the value of R 1 set to take a square root. You will have to readjust the offset control after R1 is changed from its original value of JOO kil. Pin Assignment Sheet: 308, 308A (See Ap pendix B for o ther specifications) To·5 package or mini dip: 1. 2. 3. 4. 5. 6. 7. 8.

Frequency compensation 1 Inverting input, Inv. Noninverting input, N. I. Negative supply, vNC Output, V0 u 1 Positive supply, Frequency compensati on 2

v•

Standard frequency compensation ci rcuit:

2

6

308

3

v-

c

experiment

AB: constant voltage and current sources

Operational amplifiers can be used in the design of stable constant voltage and current sources. The addition of an op amp to a voltage reference source such as a Zener diode or a Weston* cell preserves the constancy of their voltage over an extended range of output current. An example of such a circuit is shown in Fig. A9-l. The reference diode is connected to a variable load through a voltage follower. If the voltage fo llower were not used, variations in the load current would produce variations in the Zener diode current, 12 • These variations would lead to a variation in the output voltage, fJ. V, as illustrated in Fig. A9-2. The voltage follower draws very little current from the diode, keeping l z constant and fJ. V = 0. The circuit in Fig. A9- l produces an output voltage that is fixed by the breakdown voltage of the Zener. An adjustable output can be obtained by making the modifications shown in Fig. A9-3. This circuit uses a noninverting amplifier; therefore, the output is given by (1)

The output current is restricted to the maximum current that can be provided by the op amp. For a 741 or 307, the output current should be held under 5 mA to ensure the constancy of the output voltage. Once we have a constant voltage source, we can use it to construct a *A Weston cell is a precise battery with a voltage of approximately 1.02 V. These cells are very stable over long periods of time, but are quite bulky and have a relatively high internal resistance. ]l is possible to buy "wet" cells that are calibrated to within 0.005 percent of their stated value.

182

CONSTANT VOLTAGE AND CURRENT SOURCES

183

+V

R

Reference zener

Fig. A9-1. Reference Zener used with a voltage follower to extend the

usable current range.

6V

- 11~~i-i---:;=======~-1"""---~~~~~--- v

Fig. A9-2. 1-V characteristic for a Zener diode.

constant current source. The constant current source illustrated in Fig. A9-4 converts a constant voltage to a constant current through the grounded load resistance, RL. To find the conditions under which the current will be constant, we must start by applying our two op amp principles (see Experiment A3). We may write that

=11

(2)

12 + h= 13

(3)

Vr =Vs= VL

(4)

/ 1

where Vi. is the voltage across the load resistance. The diagram shows the conventional direction of the cunent t hat flows through each component.

184

EXPERIMENT A9

v R Vz _ ___,__ __ _ ___, +

lz

Fig. A9-3. Adjustable voltage reference source.

R,

RI

s

Voltage

Io Vo

Reference T

R2

R3

v1. 12

13

-:-

RL

Fig. A9-4. Proposed constant current source with a grounded load.

The output voltage, V0 , is assumed to be negative because a positive voltage is applied to the resistor connected to the inverting terminal. We begin our analysis by solving for h from Eq. (3), and using Ohm's law, IL= [3 -

=

VL - VL

(5)

VL - [ - VL- Vo

(6)

fz

Vo -

R3 In addition, combining Eqs. (2) and (4) gives I I=

v,.r R1

-

1 -

R2

R1

185

CONSTANT VOLTAGE AND CURRENT SOURCES

We can now eliminate the dependence of IL on V0 by solving Eq. (6) for V0 - VL and substituting the result in Eq. (5) IL =

- ~( V,.r R 1R 3

VL) -

VL

R2

Rearranging terms, IL = _ R,V,.r _ (R 1R 3

R 1R 3

R1R1) VL R 1R 2 R 3

(7)

As long as h has a dependence on VL, it will not be constant with changes in RL. We must choose resistances that satisfy the condition R 1R 3 - R2 R1 = 0. Then,

(8) I

A final simplification can be achieved by taking R 3 = R 1 in addition to taking R 1 = R 2 • These simplifications are included in the diagram in Fig. A9-5.

v,•• O---

R, -'Wv.------1

Fig. A9-5. Final design for a constant current source.

The load current depends only on the values of R, and are constant.

v,.r,

both of which (9)

The negative sign means that when V,0 r > 0, the current is drawn from ground, as shown in Fig. A9-4.

186

EXPERIMENT A9

PARTS Op amps:

741, 307, o r equivalent (2).

Diode: Any Zener diode with Vz < 10 Y. Ideally, the diode should be a reference Zener for the greatest thermal stability ; however, the added expense is not necessary for the purposes of this lab. Resistors : I 0 kQ (3), 6.8 kQ (2), decade boxes (2). Also, select several possible resistors for R in Fig. A9-3.

PROCEDURE I. To build the circuit in Fig. A9-3, you must choose a value of R that is appropriate fo r your particular Zener diode. First use the power rating of t he diode to calculate the maximum allowed reverse current, (lz)m.x- A good value for / 2 is one fifth of(/z)mu· Given that 15 V = lzR V2 , calculate an appropriate value for R. Select the standard resistor that comes closest to your computed value fo r R. Complete the rest of the circuit taking R, = 10 kQ and use decade boxes for R1 and RL. Adjust the va lue of R 1 until the output voltage, V0 u1 , is 10 V. Measure Vz and compare V0 u1 calculated from Eq. (I) with the actual V w The voltage, V00 " is comprised of a 10-V de signal plus some small ac component. Consequently, if you use the "ac coupling" mode on your oscilloscope, the sensitivity may be set to a high value since the scope will ignore the de level. Use the oscilloscope to measure the size of the ac noise present in the output. Find the ratio of the ac noise level to the de level.

+

0

2. Decide how the circuit must be modified to give an output of -10 V. Test your design by actually building the circuit. Include a circuit diagram in your report. 3. Restore your circuit to the des ign of Fig. A9-3. Measure V0 u1 for 100, 20, 5, and 1 kQ. Calculate the load current for each of these resistor values. Estimate the maximum current that the circuit can supply without having the output voltage differ by more than I percent of its low current (RL = 100 kQ) value.

RL

=

4. Construct the constant current source (Fig. A9-5) using the output of the constant voltage source (Fig. A9-3) to provide the reference voltage, V,0 r. The resistor, RL, in F ig. A9-3 should be eliminated. The circuit of Fig. A9-5 takes its place. Let

R, = lOkQ

R 1 = 6.8 kQ Load

=

decade box

+ ammeter

CONSTANT VOLTAGE AND CURRENT SOURCES

187

Set vrcr = 10 v and RL = 100 n. To determine the resistance, RL, you must add the internal resistance of your ammeter to the resistance set on the decade box. Measure the load current and compare your result to that predicted by Eq. (9). Suppose that you want t o ensure that the condition R 1 R 3 - R 2 R1 = 0 is precisely met. What simple circuit could you build and test that would help you to be sure that this condition is satisfied? Give a diagram. 5. Adjust v,.r to make IL = 1.00 mA when RL = JOO n. Measure IL for RL = I, 5, and 10 kn. At what value of RL does the load current stop being constant? Why does the constant current source fail for high load resistances? How could the component values be changed to keep the current constant up to at least RL = IO kn? (A detailed answer is required; some experimentation may be helpful.)

experiment AID: power a1Dp/ifier

The majority of inexpensive op amps provide only a modest amount of output power. Op amps such as the 741, 307, or 318 produce linear amplification up to an output power of about 0.1 W. In addition, the absolute maximum output ratings for these op amps are :l: 15 V (output current = 0) and 25 mA (output shorted). These maximum ratings cannot be achieved simultaneously. Many applications of op amp circuits, such as running a beater, driving a speaker, or closing a relay, require more power than 0.1 W. Op amps with higher output power ratings can certainly be p urchased. Indeed if you have the proper credit rating, you can buy operational amplifiers with output power in excess of 100 W ! This expenditure can bring low noise, low distortion, and high power; in short, the best of everything. If you are willing to compromise somewhat on noise and distortion levels, there is a rather simple alternative that will allow the continued use of an inexpensive op amp. This alternative requires the addition of a power output stage that uses discrete components which can withstand bigh current and/ or high voltage. Frequently, the most important limitation of an inexpensive op amp is its low output current. This difficulty is remedied by adding a current booster stage, such as that shown in Fig. Al0-1. The circuit uses either an NPN or a PNP power transistor. We will call the output current of the op amp 18 , since it flows into the base of the transistor. As noted earlier, the op amp limits 10 to an absolute maximum of 25 mA. For best (most linear) results, 10 should be kept under 5 mA. The transistor will provide an intrinsic current gain, which is specified by its hybrid parameter, hFE (hpe is sometimes called ft). Generally, the value of hFE lies somewhere between 20 and 100. Thus, with a base current of 5 mA, we have a potential output current as high as -!- A.

188

POWER AMPLIFIER

189 R,

v

+1 5

R, vm

c

B

NPN

E -:-

vout

Re - 15

v

-1 5

v

(al

Rr

R,

c

V ll'I

B

PNP

E vout -:-

Re +1 5

v

(b)

Fig. AJO-J. Current booster circuit that employs either (a) an NPN or (b) a P NP power transistor.

This current is provided by the bipolar power supply that drives the transistor stage. The normal op amp power supply often cannot produce such a high current. An auxi liary power supply may be needed (see Appendix E). You should a lso note that the transistor is used in the common-collectororemitterfollower configuration. T his arrangement gives an ac voltage gain of approximately 1 for the transistor stage. The voltage at B approximately equals the voltage at E. The other important characteristic of the emitter-follower configuration is that the open-loop output impedance is low (less than 10 0.). Since the feedback is taken from the o utput after the transistor stage, the voltage gain of the complete circuit is unaltered by the add ition of the

EXPERIMENT AJO

190

transistor. The feedback current is equal to -V0 u 1/R 1 , and equating lp to the input current, Vin/Ri, shows that the familiar result, A1 = -Ri/Ri, still applies. The only djfference is that the output power can now be as high as 7.5W. We shall now consider in some detail a practical design for a de amplifier with a voltage gain of 10. The circuit illustrated in Fig. Al0-2 accepts inputs in the range of 0 to 1.4 V, 0 to 0.13 mA, and amplifies them to 0 to 14 V, 0 to 140 mA. The potentiometer attached to the inverting input provides offset correction. The circuit as shown corrects for negative offset. If positive offset correction is needed, the positive supply can be connected in place of the negative. - 15

v

+ 15

Offset

v

R,

680

10 kQ

100 2N3055

R;

-;;-

+

1kr2

Vin

10 k.\1

2.2

kn

Re

-15

v

Fig. AJ0-2. Gain-of-10 de amplifier.

The 2N3055 power transistor that we have chosen has the following characteristics: Current gain:

hFE = 20 to 70.

Maximum collector-to-emitter voltage: Maximum coJlector current:

(Jdmax

=

(Vc 50 )max

=

60 V.

15 A.

There are numerous transistors that might be substituted for the 2N3055. The only requirements are that ( VcEO)m ,. be greater than 30 V and that (lc) 01 ax be greater than the proposed maximum load current.

POWER AMPLIFIER

191

Since the useful range of 18 is limited to 5 mA by the op amp, the collector current V e) should not exceed hPE x 5 mA. Since the transistor passes current only in the forward direction, the range of collector current is given by 0 < le < hpe x 5 mA. We shall examine the significance of this range by finding the maximum and minimum output voltages that a re permitted for a 100-Q load resistance. When the collector current, le, equals 0, the emitter current, 1£, and the load current, IL, must be nearly equal, since current in the feedback path will be negligible. By taking le = /" we can consider the resistors R£ and RL to form a simple voltage divider. The minimum output voltage is

(V.,.,,)mln

=

-15 R.s

+

R

RL = -0.65 V

(!)

The maximum output voltage should be near 15 V. This condition requires a collector current of le= 30 V/2.2 k.Q + 15 V/100 .Q = 184 mA. The base c urrent (10 ) necessary to produce this m uch collector current is 184/hPE = 3.5 mA (taking hFs = 50), a value that is comfortably below our 5-mA limit. In summary, we have found that regardless of the input voltage level the output voltage must lie within the range - 0.65 < Vout < 15 V. If we wish to vary the load resistance, it is important to find the minimum value that is allowed. This minimum value will produce a maximum base current of 5 mA or a collector current of about 250 mA. It is a simple matter to show that (RL)m1n = 60 Q for o ur design. You may now be wondering what would happen if the output were accidentally shorted (RL = 0). (If you are going to try this, wear asbestos gloves. The transistor may be hot!) The situation can be analyzed as follows: a short to ground means V0 . , = 0 and V0 ~ 0. The op amp will deliver its maximum output current, 25 mA. Thus, the collector current will run to 1.25 A, and any transistor with Ue)max < l A will burn out. Short-circuit protection can be built in by including a collector resistor, Re, between the collector and the + 15-V supply. A collector resistance of 15 .Q will limit the collector current to I A regardless of what you do to the input or output. However, the addition of R e reduces the maximum output voltage. (When Re = 15 Q and RL = lOOQ, (V0 u 1)mu = 15 (100/(100 15)) = 13 V.) A better solution is to use a current-limiting power supply to run the transistor output stage (see Project P 1 and Appendix E). A few rather simple modifications will convert our de amplifier to a class A ac power amplifier with a voltage gain of 11. The amplifier shown in Fig. Al0-3 has a low frequency cutoff (3-dB point) below 50 Hz. For ac input signals, the amplifier has the noninverting configuration (point A is at ac ground). Ideally, one would like to have the de level at point E near the center of the a llowed output voltage range. The de offset control accomplishes this task.

+

EXPERIMENT AJO

192

+15 v

- 15 v 1o kn

2N3055

E

100 µF

10 kn 270 .n

100 n

- 15 v

Fig. Al0-3. Class A power amplifier with a voltage gain of I J.

PARTS Op amp: 741, 307, or equivalent. Transistor : 2N3055 or any NP N power transistor with ( Vci:;)1110 , = 30 V and l cE > 500 mA. Resistors: 270, 680, 1 kn (2), l 0 kn (2), 2.2 kn, a I 00-n resistor with a power rating of at least 2 W; a 100-n pot. Capacitors : 0.47 µF, 15 WV de unpolarized; 100 µF, 15 WV de. Power supply: bipolar, 15-V supply with at least 250-mA output, or equivalent.

PROCEDURE 1. Build the circuit in Fig. Al0-2 without connecting the transistor stage. The feedback resistor should be temporarily connected to the output terminal of the op amp. Apply a de input and verify that the circuit functions as a gain-of-JO amplifier. Now connect a 100-Q load resistor between the output of the op amp and ground . With the input grounded, adjust the offset control until the output is 0. Now measure the output voltage fo r inputs of 0.05, 0.10, 0.15, 0.20, and 0.30 V. Calculate the output current in each case.

POWER AMPLIFIER

193

At what output current does the op amp cease to be linear (gain no longer equals 10)? What is the maximum output current? the maximum output power? 2. Now add the transistor stage. Your circuit should now be exactly like the circuit in Fig. Al0-2 with the feedback and output taken from the emitter of the transistor. (Caution: be sure that your power supply can provide a current of at least 200 mA.) Use the offset control to set V00 , to 0 when Vi. is equal to 0. Connect a negative input and compare the minimum output voltage with that predicted by Eq. (1). Now with a positive input find the maximum output voltage. (Do not spend too long taking this measurement. Your transistor and/ or load resistor are likely to become quite hot.) Calculate the maximum output current and power. Check whether the amplifier is linear over its full range of output voltage at several points between (V001 )min and (Voui)max· 3. Modify your circuit by adding capacitors C, and C0 and changing RE to 2700, as shown in Fig. AJ0-3. Apply a sine-wave input of 1-Vp- p• 300 Hz. While monitoring the output with your oscilloscope, adjust tbe potentiometer so that the output is not clipped. Determine the ac gain of your amplifier. Find the high- and low-frequency 3-dB points.* 4. Set the input back to I vp-p• 300 Hz. Measure Voul for RL = 100, 500, I 0,000 n. Is there any observable effect of output current on output voltage? What can you say about the effective output resistance of your amplifier? •The 3-dB point is defined by the following equation: -3 dB = 20 Jog [A(f)/A], where A is the gain at midband and A(/) is the gain at the frequency extremes (the 3-dB points). The equation states that the gain at the 3-dB points is given by A(f) = 0.707A.

experiment All:

driving relays and siHcan~cantroHed

rectifiers

In the previous experiment we considered ways of enhancing the power ratings of linear amplifiers. The problem of low power arises for nonlinear circuits as well. Occasionally, one needs to turn large voltages and/or currents on and off with op-amp circuits (see Project P3). One convenient way to accomplish this task is by using a relay. Figure Al 1-1 illustrates the connection of a zero-crossing detector to a relay. When vin < 0, current runs through the relay coil and the relay switch is closed. When v10 > 0, current is shunted through the diode and the relay is open. You should notice that the load loop is completely isolated from the input and floating (ungrounded). Any type of voltage source-alternating or direct current, grounded, or floating- can be used on the relay contacts. The only restrictions on the size of the voltage and Sou rce Load loop ------....

300·S1, 4.8·V coil A

Fig. All-1. Relay output.

194

DRIVING RELAYS AND SILICON-CONTROLLED RECTIFIERS

195

the current that can be switched are those imposed by the maximum ratings of the relay contacts. The relay coil must have a voltage and current rating that is less than the maximum output ratings of the op amp (15 V, 25 mA). This statement notwithstanding, you will occasionally find yourself in possession of a relay with a 24-V coil (because this is one of the most common types, a constituent of many $5 electronics grab bags). Fortunately, there is an ingenious trick that will allow you to use this relay. Point A in Fig. Al 1-1 can be connected to -15 V rather than ground. Now when the output is high (v10 < 0), the voltage across the relay can be as large as 30 V, enough to power the 24-V coil provided the current rating of the coil is not greater than about 10 mA. The diode would not be needed if A were connected to -15 V. Another method for switching large voltages and currents involves using a silicon-controlled rectifier (SCR) in place of the relay. A "burglar alarm" circuit using an SCR is shown in Fig. Al 1-2. As long as the switch remains

Vz .. 5 V

Anode

Switch

2N1595 - 15 V

U---'\J\1\1\r-~

10kn

Gate

Cathode

Fig. All-2. Burglar alarm.

closed, the gate (G) of the SCR is held at 0 V because the Zener will conduct in the forward direction. (If you are not comfortable with this result, you should refer to Experiment A6, which deals with comparators.) When the switch is opened, the output will go to 5 V, the reverse breakdown voltage of the Zener. The SCR will be turned on, and the alarm will be activiated. The alarm will remain on even if the switch is closed again (provided Vs is a de source). The alarm stays on because of a special characteristic of SCRs. Once an SCR becomes conducting, it conducts until the anode-to-cathode current falls nearly to 0 regardless of subsequent changes in the gate voltage.

EXPERIMENT All

196

The design of the circuit in Fig. Al l-2 depends on the ratings of the particular SCR that is chosen . The pertinent ratings for the 2N1595 SCR are as foJJows: Peak forward blocking voltage :

VFoM =

Maximum forward current (de):

IF= 1.6 A

Maximum current to trigger gate : I 0. Compare the power available to the load circuit for the triac and the SCR. Type47 Bulb

2 Triac ±5 V de

o to 10 kn

G

Fig. Ail-4. Triac circuit.

6.3

v

llc

1~5V hne

experiment

Al2: active filters

Filters can be conveniently divided into four catagories: bigb-pass, low-pass, bandpass, and notch. Figure Al2-l shows the response curves or transfer function for the four kinds of filters. An "active" filter simply implies that an op amp is used in addition to resistors, capacitors, and inductors.

Low· pass

- - - - - - - High pass

Bandpass

-

- - - - - Notch

Frequency-

Fig. A12-1. Ideal response curves for the four different kinds of filter.

199

EXPERIMENT All

200

If your work reqµires the use of an active filter, you must choose one of two methods of attack: the first approach involves copying someone else's design, adapting the component values for your application. The other approach req·uires starting from scratch and working your way through a circuit design book and the requisite mathematics. The latter approach is educational, but the former generally produces equally good results with much less effort. We shall, therefore, devote our efforts to explaining how an existing design may be adapted for one's own use. If you glance at the figures in this experiment, you will notice that there are no inductors. Mathematically, inductors work as well as capacitors; practically, inductors are best left to communications (RF) engineers. Virtually all modern filter and function generator designs utilize RC networks rather than LC or RLC circuits. Our first example will be the familiar RC low-pass filter. The analysis of the series RC network begins by finding, in Fig. Al2-2, the total impedance

- 10dB

c

:;:_-

>&

o;

- 20 dB

0

0

N

- 30dB

(a)

-40dB1---~~~~~~~~~~~---''--~~~~~~~-'-~~~--'

0.10

10

1.0 f/f 0

{bl

Fig. A12-2. (a) Simple RC filter; (b) response for simple filter (11

and higher-order Butterworth filters.

=

1)

ACTIVE FILTERS

201

Z = R - jXc. where Xe = l/2n/C. We shall proceed on the assumption that the notions of complex impedance are familiar to you. The current i = V;n/Z and the voltage across the capacitor, v0 " " is -jXci. If we use O> = 27t/, our result is Vout = - jvin/wC(R - j/wC), which can be simplified to A (w) - IVou•I 1 f = "V;:- - (0>2Rzcz

+ 1)112

(1)

The response curve (or transfer function) is shown in Fig. A 12-2, labeled as 11 = I. While we are familiar with the series RC circuit as an ordinary lowpass filter, it is also characterized as a filter of order I and cut-off frequency w0 = I/ RC or lo= 1/2nRC. The response curve of Fig. A 12-2 for n = 1 is very different from the ideal response curve of Fig. A 12-1 for a low-pass filter. By cascading simple RC fi lters, we can improve the sharpness of the roll-off and the flatness of the response for frequencies below cut off. Examining the results of Eq. (1) shows that at w = 0 (de), A 1(w) = V0 u1/v 1• = 1. Also, at O> = w 0 (the c ut-off frequency), A J(w0 ) = I/~= 0.71 When v0 u1/v;n has decreased to 71 percent of its maximum, the gain has decreased by 3 dB (gain in decibels = 20 log vout/vin). fn the case of filters, the 3-dB point is called the cut-off frequency. You can determine the roll-off at higher frequency by substituting 0> = 10w0 , and then w = 200> 0 • The result (approximately) is A J(IOw 0 ) = ~rr and A 1(200> 0 ) = rt;. The gain goes down by a factor of 2 per octave or 10 per decade. In electronic terms, the roll-off is 6 dB/ octave or 20 dB/ decade. To design a circuit using this filter, you simply choose component values for Rand C so that RC= l / 2n/, where f is the desired cut-off frequency. You should pick R so that at high frequency sees a suitable resistance. For example, if v 10 is an oscillator with a 600-Q output impedance, make R = I kQ or larger. [t is possible to improve our filter by using more Rs and more Cs. There arc a bewildering number of possible ways to do this. The most common filter designs use the Butterworth polynomial method. Briefly, you must decide upon the network of Rs and Cs t hat you intend to use, analyze the circuit as a function of frequency, and write the results in a form that looks like AJ(w) = A/(a.(w/w0 )" + a._1(w/w 0 )" - 1 + .. . + I]. The constants, a., are functions of the R and C values in the circuit, as is w0 • The gain of the circuit for direct current is A. At this point you must consult a table of Butterworth polynomials (Table Al2-l) to determine what values to choose for the constants a., a._1, etc., in order to come as close as possible to the ideal response of Fig. Al2-I. This is a complicated procedure and usually involves computer assistance for higher-order filters. Fortunately, we can make good use of the results without carrying out the entire design ourselves. Returning to the RC series network, we can rearrange the terms so that

v,.

202

EXPERIMENT Al2

Table A12-1 BUTTERWORTH POLYNOMIALS

n 1 2 3 4

Polynomial*

S+l s2+,,/Zs+1 (S -1- l)(S2 -1- S + l) (S2 + 0.77S-!- l)(S2

+ 1.85S + 1)

*For our work, S = j(J)/(J)o

Eq. (I) looks like Ar(co) = 1/(jw/w 0 + I). This transfer function corresponds to a Butterworth filter of order n = I and cut-off frequency ro 0 = l /RC. A second-order filter (n = 2) has the general form shown in Fig. Al2-3. The analysis is considerably more difficult but the result is

A

A,(co) = ((jco/co 0) 2

+ (3 -

A)(jco/coo) + 1]

(2)

where A is just the gain of the op amp in the noninverting configuration. For this circuit, A = (R, + R 1)/ R1• For the second-order filter we have again chosen co 0 = l /RC. (Caution: there are filter designs where ro 0 :;t: 1/RC.) To use the Butterworth polynomials, we find that if we make 3 - A = 1.414 or A = 1.59, the transfer function in Eq. (2) is a Butterworth polynomjal of order 2. The response versus frequency is then determined from Fig. Al2-2, using n = 2. To design a fourth-order filter, you can connect two second-order filters in series. When two filters are placed in series (output of first becomes input of second), the total transfer function is just the product of the two individual

' > - - - - - 4 - --- v ou c

c,

Fig. A12-3. Second-order low-pass filter.

ACTIVE FILTERS

203

transfer functions. If you consult Table A12-l, you can see that the fourthorder polynomial can be factored to be the product of two second-order polynomials. Consequently, if the gain of the first amplifier is equal to 2.2 and the gain of the second is equal to 1.5, we will have a fourth-order Butterworth filter.

Bandpass Filter. A series RLC circuit has a well-known resonant frequency response. T he transfer function is A (co) _ vR = 1 - Vin

- C0

2

R(jcoL)

+ (I /LC) + jcoR/L

(3)

For the series RLC resonance, co0 = 2nf0 = l/(LC) 112 . The bandwidth (~co) is defined as the frequency range between the points at which AtCco) is 0.707 of its maximum. The quality factor, Q, is simply COo/~co = COoL/R. If we make the filter an active one by connecting vR to an amplifier of gain A, the result is

A (co)= -j(l)((l)of Q)A 1 (j(I)) 2 Wo/ Q)jco

+(

+ co5

(4)

To design a bandpass filter using only Rs and Cs, we must first find a suitable network (usually by copying from a published circuit) and then analyze the circuit to find A 1(co) in terms of Rs and Cs. The most common bandpass configuration is shown in Fig. Al2-4. The analysis of this circuit is straightforward but lengthy. The transfer function is

AtCw)

=

where RP = (R 1 R2 )/(R 1 say

{wfR1C1 2 2 -jco + ~'r"C.g2 jw + R~1C1C2

+R

2 ).

(5)

By comparing Eqs. (4) and (5), we are able to

> - ---+----Q vout

Fig. A12-i/. Bandpass filter.

204

EXPERIMENT AJ2

We can then proceed to design an a rbitra ry bandpass filter. For example, we will choose a Q of 20 (reasonably sharp), a gain of 20, and a center frequency of 1 kHz. The bandwidth of the filter should be/0 /Q or 50Hz. You may notice that we have three determined quantities (Q, A, and/0 ) and five component values (R 1, R 2 , R 1 , C 1 , and C 1 ) to choose. There is no substitute at this point fo r trial and error. For the sake of convenience, ·we will pick C 1 = C2 • We would a lso prefer to have no resistors larger than 1 M.Q or smaller than a few hundred ohms. Also, the capacitors should have a reasonable impedance a t 1000 Hz (a few kilohms). These vague rules would suggest C = 0.1 µFas a good starting point. You then substi tute this value into R 1 = Q/ Aw0 C 1 to get R 1 = 1600 n , a reasonable value. You find R1 = Q(C 1 C 2 )/w0 C 1 C 2 to be 64 kn. Finally, we get RP= 1 /(w~Ci R1) to be 40 n. This is an example of a good effort and a questionable result. Altho ugh, thcorctica!Jy, RP = R 1 R1 /(R 1 R 2 ) could be made equal to 40 n, we would prefer a design tbat works out to have reasonable-sized resistors and capacitors. We must simply start again with a different value for C and repeat our procedure. One possible fin al design is given in the procedure section. T he task of finding reasonable component values becomes increasingly difficult at higher values of Q. The gain requirements are relatively easy to achieve but must be limited to less than the open-loop gain of the op amp at the center frequen cy.

+

+

PARTS Op amp:

741 or equivalent.

Resistors: box.

1.5 k.Q (2), 10 k.Q (2), 15 k.Q, 8.2 kn, 330 k.Q, 220 .Q, decade

Capacitors:

0.01 µF (I), 0.1 µF (2), 0.02 µF (2).

PROCEDURE I. Single-pole RC Filter. Build the ci rcuit in Fig. Al2-3 using R 2 = 15 kn , C 2 = 0.01 µF, R; = 10 kn , and R 1 = 10 kn, and eliminate R 1 and C 1 (Input directly to R 2 , no connection from v 0 u, to vi0 . ) Measure the output of the op amp for an input signal of 1-V amplitude and frequencies 125, 250, and 500 Hz, and 1, 2, 4, 8, and 16 kHz. Vary the frequency until the output is 71 percent of the amplitude at low frequency (50 Rz, for example). Row does this cut-off frequency (or 3-dB point) compare with the predicted / 0 ( = 1/2nRC).

ACTIVE FILTERS

205

Present your data in a log-log graph similar to Fig. AI2-2. Plot 20 log,o vou1/ Vma:< on the vertical axis and loglO f!lo on the horizontal. Use your experimentally determined cut-off frequency for lo· Determine the roll-off at high frequency by finding the ratio of the output at 8 kHz and the output at 4 kHz. Since going from 4 to 8 kHz constitutes an octave, the roll-off can be stated as a certain number of decibels/octave. You should note that this same result could have been obtained by using the slope of your graph between 4 and 8 kHz. How does your answer agree with the predicted roll-off for a filter of order n = l? 2. Second-Order Filter. Construct the circuit in Fig. Al2-3 using R 1 = Ri = 1.5 kQ, C 1 = C2 = 0.10 µF , R, = 10 kQ, and R 1 = 15 kQ (a decade box is preferable for R 1 and should be set to 16 kQ). Apply a 1-V amplitude sine-wave input at frequencies of 250, 500, and 750 Hz, and 1, 1.25, 2, and 4 kHz. Plot the output in the format described in step 1. Find from your graph the 3-dB point and roll-off per octave. Compare the roll-off to that predicted from Fig. Al2-2 for a second-order (n = 2) filter. One bothersome phenomenon in active :filter design is caJJed peaking. Without recording and plotting the output, simply observe Vout as you vary the input frequency from lOOHz to 10 kHz. You should notice a "peaked" response rather than a flat response followed by roll-off. 3. Bandpass Fi/tel'. We will construct a bandpass filter with a center freq uency lo = 1 kHz, A = 20, and Q = 20. A set of components (Fig. AJ2-4) that gives the required response is C 1 = C 2 = 0.02 µF, R 1 = 8 kQ, R1 = 318 kQ, and R 2 = 201 Q. Natu rally, you should use standard resistor values. For example, a 330-kQ resistor will do instead of 318 kn, 220 Q instead of 201 n, etc. Apply a 0.1-V amplitude sine wave and monitor the output with an oscilloscope. As you vary the frequency from 100 Hz to 2 kHz, you should notice a sharp increase in the output at a frequency near 1 kHz. Determine the center frequency lo of the maximum output. Now, carefully determine the frequencies above and below / 0 where the output drops to 71 percent of the output at/0 (the 3-dB points). The difference between these frequenci es (Ill) defines the bandwidth of the filter. Also measure the output (approximately) at 250, 500, and 750 Hz, and l , 1.25, 1.5, and 2 kHz. Plot a response curve of the filter's gain in decibels (20 log v0 u, / V1n) versus loglflo· Use your measured bandwidth to calculate the measured value of Q. How well do the measured values ofl0 , A, and Q compare with the design values? 4. Spectrum Analysis. Any periodic waveform may be synthesized or "built-up" from a series of sinusoidal waves. For example, the note middle C is equal to 512 Hz. However, the quality of the middle C actually prod ucecl by an instrument depends on the harmonic content (number and strength of the overtones at 1024, 1536, 2048 Hz, etc.) as well as the fundamental frequency .

EXPERIMENT A12

206

Spectrum analysis is the process of determining which frequencies (sine waves) are actually present in any given waveform. We can use our bandpass fi lter to perform a spectrum analysis of a square wave. If we apply a square wave of some arbitrary frequency, our bandpass amplifier will respond to only the 1000-Hz component of the square wave. For most periodic waveforms, like a square or triangle wave, we can calculate or look up the Fourier series for the wave. For example, if we look up the Fourier series for a 1-V (peak) square wave, we find that square wave= : (sin 27tft ++sin 6nft

+ } sin IOnft + ...)

This expression tells us that a square wave of frequency f has a sine-wave component of 4/n at/, 4/3n at 3/, etc., and no components at 2/, 4f, etc. To check this experimentally, find the output of the filter for squarewave input frequencies of 1000 Hz, and then 500, 333, 250, and 200 Hz. Do your observed outputs agree with what would be expected from the Fourier series 7

expe ri111ent

Al3: oscillators

Most of the op amp circuits that we have considered have used negative feedback. Positive feedback (or regeneration) is produced by returning a portion of the output voltage to the input so that the input and feedback voltages add. The effect of positive feedback can be understood as follows. The input voltage is increased by a portion of the output being fed back to the input; the larger input voltage is in turn amplified making the output still larger, and so on. You should recall that in the case of the comparator and Schmitt trigger circuits there was positive feedback between output and input voltages. The undamped output was limited only by the power supply voltages. We can also use this kind of instability to construct phase-shift oscillators. The mathematical condition for oscillation can be derived simply by looking at the formula for the closed-loop gain of a real op amp:

Ao

'Vout _

'V;:- -

1

+ PAo

(1)

In Eq. (1), pis the feedback ratio which represents the fraction of the output voltage that is added to the input. The feedback ratio can be positive or negative, real or complex. If the denominator in Eq. (1) equals 0, then v0 • 1/vin becomes infinite (mathematically, at least). When the Barkhausen criterion is met, that is, -pA 0 = 1, the circuit will oscillate. In general, p will be determined by resistors and capacitors so that the Barkhausen criterion really bas two parts: 1. The total phase shift between output and input must be zero (or 2n, 4n, etc.). The frequency at which the phase shift equals 0 is the frequency of oscillation.

207

EXPERIMENT Al3

208

2. The absolute value of PAo should be equal to I for stable oscillations. These two conditions can best be explained by examining the pbasesbift oscillator circuit shown in Fig. A13-l. T o begin the analysis, we shall consider o nly the R C network and ignore the op amp connections (switch in

v~

0.1 µ F

1.5kS1

0.1 µF

1.5 k.\1

1.5 kS1

Fig. A13-l. Phase-shift oscillator.

down position). You should recall that capacitors in a series circuit shift the phase of the current by an angle between 0 and 90°. For a simple RC circuit, the exact amount is given by ¢ = tan- 1 (1/2nfRC). Notice that the phase shift depends on frequency, and that the limits on¢ are¢ = 0° (when!:::::::: oo) and ¢ = 90° (when!= 0). In Fig. A 13-1 the phase of v~ is shifted with respect to v0 . , by some angle that depends on the frequency of oscillation. Each of the three sections contributes a phase shift, so that at the end of the network Vs will be out of phase with v0 . , by an angle between 0 and 270°. For any particular value of Rand C there will be one frequency at which the phase shift between Vs and Vout will be 180°. When the voltage Vs is fed back to the inverting input, another 180° phase shift is introduced by the amplifier. A total phase shift of360° means Vs and v 0 • 1 are exactly in phase at that one frequency. Oscillation occurs since we have met one of the Barkhausen criteria. To find the frequency of oscillation, we must analyze the network of Rs and Cs to find an expression for Vs/v0 • 1 • This expression will contain real and imaginary parts. The imaginary part (coefficient of j, where j = J=T) equals 0 only when the phase shift equals 0°, 180°, 360°, etc. The c ircu.it will oscillate when the RC network p roduces 180° shift, which can add to the 180° shift caused by the amplifier (which inverts). We find that the imaginary part of Vs/Vout vanishes when -JO'= 1/2nf0 RC. The second criterion for oscillation requires that the amplifier have an open-loop gain, A 0 , of 29 at the resonant frequency. The number 29 comes from substituting the value of / 0 , R, and C into the result for Vs/v0 . , and finding Vs/Vout = - P = at resonance. The second Barkhausen criterion

-n

OSCILLATORS

209

requires that IPA 0 I = A 0 / 29 = I. Th us, the amplifier must have au openloop gain of 29 (a low value for modern op amps). In practice, the requirement is not this stringent. Stable oscillation is achieved whenever IPA 0 I> l (or A 0 ~ 29). The least distorted si nusoidal output occurs when IPA J is just slightly greater than 1. This condition can be approached by adding resistive feedback to reduce the gain. A better, more sinusoidal oscillator can be constructed from a Wien bridge (Fig. A13-2). The analysis is much simpler (mathematically) than for the previous oscillator. The first criterion says that Vr - Vs (the input to the op amp in Fig. Al3-2) must be in phase with v0 w Notice that Vs = VoutR 2 /

s T

Fig. A13-2. Wien-bridge oscillator.

+

(R 1 R 2 ) =a real number, so V r must have no imaginary component. We find Vr by first finding the current iz and then multiplying by Z 2 , whereZ2 is the parallel impedance of R and C. Defining Z 1 as the series impedance of R and C, the result is Vr = Z 2 v0 u 1/(Z 1 + Z 2), where Z 1 = R - j /(J)C and Z 2 = R/(l + jmRC). Finally, we arrive at Vr Vout

= 2wRC

+mR 2

2

(J)RC C 2 - j(l - w 2 R 2 C 2)

(2)

This expression is not hard to interpret. By simply taking 1 - w2 R 2 C 2 = 0, we may get rid of the complex number and thereby satisfy the first Barkbausen criterion . This requirement gives a resonance (oscillation) at f = f 0 = 1/2nRC. At this frequency Vr/ Vou < = !· The Wien bridge circuit is tuned into oscillation whenever Vr - Vs > 0 at a frequency f = l/2nRC. Notice that oscillations will start when R 1 is in-

EXPERIMENT Al3

210

creased to a value just above 2R 2 • When R 1 is less than 2R2 , (vr - Vs) will be less than 0 at the resonant frequency, the feedback will be negative, and oscillations will die out. Relaxation Oscillators. Many applications for oscillators do not require sinusoidal outputs. There are many integrated circuits presently available that can supply square-wave, triangle-wave, and pulse outputs. The best of these !Cs require a minimum of external components (usually one capacitor and a couple of resistors). Another excellent feature of many oscillator chips is a voltage-controlled oscillator (VCO) input or "programmability." This means that the oscillator outputfrequency is proportional to an input 10/tage level. Such circuits are also referred to as V-to-F converters (voltage-tofrequency). No general analysis can be performed for these ICs since the actual circuit giving rise to the oscillation varies considerably from device to device. Many chips contain a constant current source that is used to charge a capacitor to a certain preset level. The time required to charge the capacitor depends on the size of the capacitor and the magnitude of the constant current. The voltage control of the oscillator can be introduced by using the input voltage either to determine the magnitude of the constant current or to set the level to which the capacitor charges. 1

PARTS Op amps: 741 or 307; 566. Capacitors: 0.1 µF (3). Resistors:

1.5 kn (3), 10 kn, decade box, 10-kn pot.

Optional: Zener diodes (2), breakdown voltage less than 10 V.

PROCEDURE l. Phase-Shift Oscillator. Construct the circuit of Fig. Al3-1 but do not connect the output or input of the op amp. Apply a 10-V sine wave from the oscillator as shown in the figure. Monitor Vs with an oscilloscope as you vary the input frequency from 100 to 1000 Hz. If you have a dual-trace scope, observe the phase shift between Vou• and Vs. If your scope has a horizontal amplifier input, use vout as the x axis and Vs as they axis, with the gains in x and y adjusted so that the pattern extends for about one half the screen along either axis. When the phase shift equals

OSCILLATORS

211

180°, the Lissajous pattern will be a straight line. At what frequency does the phase shift = 180° ? Compare this value to I/,J02nRC. 2. Now connect your phase shift network to the op amp. The oscillator should be removed (switch in diagram in up position). The circuit should oscillate with no further adjustments. Draw the shape of the oscillations and record their frequency. How does the frequency compare with the value determined in step 1? This oscillator saturates because IPA 0 I» I, and consequently the frequency will not be equal to the predicted value. The agreement with theory is improved if you prevent the oscillator from saturating. The output can be clamped with two Zener diodes (breakdown voltage Jess than 10 V) connected in a back-to-back configuration between the op amp output and inverting input. If you cannot recall how to connect the Zeners, consult Fig. A6-2. 3. Wien-Bridge Oscillator. Construct the circuit shown in Fig. Al3-2 using a decade box as resistance, R 1 • Increase R 1 from a value of 10 kn in 1-kn steps. At what value does the circuit begin to oscilJate? How does the ratio R 2 /R 1 + R 2 compare with the predicted value of -j·? Record the frequency of the oscillation and compare to the predicted value. 4. Relaxation Oscillator. An example of the recent wave of"oscillator011-a chip" integrated circuits is the 566 function generator (Signetics). The pin connections for this device are shown in Fig. A 13-3. Consulting the manufacturer's data sheet shows that the output frequency depends on R 1 , C1, and the voltage applied to pin 5. The frequency of oscillation is approximately equal to 2(V+ - Vs)/ R 1C 1 v+. In addition, Vs is restricted to values between +15 +15

v

v

R, 0 to 20 kQ (decade box) y+

o to 10 kn

R 5

o--1 v,n

c in

8

6

{pot.)

3

SLfL

4

~

566

V5

7

Fig. A13-3. A 566 IC function generator.

212

EXPERIMENT A13

0.75V+ and v+. Using a fixed value of the capacitor C 1 (= 0.1 µF), with R 1 equal to 2 kQ, vary the voltage at pin 5 (Vs) by varying R. Measure the output frequency at pin 3 and the correspondi ng de voltage level for several values of Vs within the range o.1sv+ < Vs < v+. For this procedure V1o and C1n are not needed. Repeat fo r R 1 = 10 kQ and finally 20 kQ. Make a plot of output frequency versus (V+ - V 5 )/V+. You should have three distinct curves, one for each value of R 1 • For R 1 = JO kQ and Vs= 12 V, measure the output a t pin 4 and compare the frequency to pin 3. Comment. In the course of changing the component values, you may notice that the circuit functions when Vs is wel l below 0.75V+ and when R 1 < 2 kQ and R 1 > 100 kQ. The manufacturer docs not imply that oscillations will not occur for voltages or resistances outside the allowed range. However, the full specifications concerning pulse shape are not guaranteed outside the specified ranges.

5. (Optional.) The 566 can be used to generate a frequency-modulated (FM) signal. Connect an oscillator to V 5 through C10 (:::::::: 0.1 µF). Set the oscillator at/ = 100 Hz, 4-V amplitude, and tune the 566 to 1000 Hz. Interpret the output waveform at pin 4. Triggering your oscilloscope may be di fficu lt. Can you explain why? What is the purpose of C10 ?

INTRODUCTION

3:

PROJECTS

The following projects are designed to provide interesting and practical applications of the principles that you have studied in the previous two sections. The projects emphasize the actual construction of practical circuits. We recommend that you try your hand at "hard wiring" (soldering together) the one or two that interest you most. Projects may be done in any order that you wish.

213

project Pl:

voltage regulators

Most of the experiments in this manual require a power supply whose output is independent of the current being drawn by the load. The output of a regulated voltage source is immune to changes in its output current and to changes in the ac line voltage. Good voltage regulators will also reduce any output ripple (fluctuations at 60 or 120 Hz). An ordinary power supply may be thought of as a battery and an internal series resistor. The series resistor is the output impedance of the supply. As more current is drawn by the load, more voltage appears across the internal resistor and the power supply voltage drops. By one clever means or a nother, a regulator suppresses this natura l tendency. However, as you might suspect, the range of output current over which the regulator can keep the output voltage constant is strictly limited . A rule of nature also dictates that the regulated output voltage must always be less than the unregulated input voltage (nothing is free). A crude form of regulation can be achieved by using a single transistor in the emitter-follower (common-collector) configuration. [see Fig. Pl -l(a)]. This circuit has a very low output impedance as a regulator should. The output voltage is approximately equal to v,.r (less VB£= 0.6 V, for a silicon transistor). The reference voltage can be generated by a stable voltage source, such as the one that was constructed in Experiment A9. Note that very little current is drawn from the reference source. Since the collector current is much larger than the base current, most of the output power is generated by the unregulated supply. To make the output varia ble a nd independent of V85 , we can add an op amp as illustrated in Fig. Pl -l(b). The op amp is used in the noninverting 214

VOLTAGE REGULATORS

215 Unregulated voltage, Ve

c

v,.,

B

E

(al

Ve (unregulated)

R,

R; + R

V OUI

=

v,., -R-.- 1 I

(b)

Fig. Pl-1. (a) Emitter follower that produces a regulated output voltage near V,0 r; (b) variable regulated output based on v,.r; note

that Ve must be greater than

v•• ,.

configuration; thus, the circuit should have a gain of A 1 = (R 1 + R 1 )/R 1, and the output should be A 1 V,.r. As long as V. is greater than V00 u the circuit should maintain an output that is as constant as V,.r. The noninverting op amp circuit can be considered to be an error amplifier. Its function can be understood by the following train of hypothetical events. Suppose that V00 t becomes less than A 1 V,.,. In this case the amount of negative feedback is reduced. The output of the op amp that is tied to the base of the transistor will increase. This increase in the base current will cause more emitter current to flow through RE, thereby acting to correct the "error" by increasing V0 w All the features of our voltage regulator can be obtained in a single commercially available package. This particular IC is called a 723 precision

216

PROJECT Pl

voltage regulator. As described by the manufacturer, the device contains a temperature-compensated reference amplifier, an error amplifier, a series pass transistor, and a current limiter with access to remote shutdown. The pin connections and equivalent circuit for this device are shown in Fig. Pl-2. Not surprisingly, the 723 has great versatility. It can provide regulation for either positive or negative voltages, and can be equipped with a variety of currentlimiting options. This versatility does not come without a price. The 723 requires more than the usual number of external comp onents (resistors, capacitors, pass-transistors, etc.). It is often easier and more appropriate to use a fixed-voltage regulator, such as those described in Appendix E.

Fig. PI-2. (a) Pin diagram for 723 precision voltage regulator; (b) equivalent circuit for a 723 precision voltage regulator; the power supply connections, v+ and v-, have been eliminated for clarity.

VOLTAGE REGULATORS

217

PARTS IC: 723. Capacitors:

1 µF, IO WV de; IOO pF, 50 WV de; .001 µF, 50 WV de

Resistors: IO and 15 n, and 1, 2.2, 2.7, and 4.7 kQ; a 10 ill pot; two decade boxes or variable resistances (0 to IO kQ). Transistor: any NPN transistor with (/c)max

> 250 mA (e.g., a 2N3055).

PROCEDURE 1. We shall begin by constructing a high-voltage regulator (7 to 37 V) as illustrated in Fig. Pl-3(a). Notice that the equivalent circuit in Fig. Pl-3(b) has essentially the same form as the regulator shown in Fig. Pl-l (b). The output voltage of this circuit using the 723 must also be given by the gain equation for a noninverting amplifier, V,08 = V, 0 r

(R, 1, Ri)

(1)

The voltage reference amplifier inside the 723 provides a reference voltage of v,.r ::: 7 V. Equation (1) requires that the minimum output voltage be equal to v,.r for this configuration. The minimum output of 7 V occurs when R 1 = 0. The resistor, R, is employed to minimize temperature drift and input current offset. Its value should be chosen so that

R=

R,R1 R, + R 1

(2)

The current-limiting feature can be understood by looking back at Fig. Pl-2(b). The short-circuit protection resistor, Rsc, is in series with the output current. The voltage across this resistor is applied between the base (CL) and the emitter (CS) of the silicon transistor that composes the current limiter. We shall label this voltage between CL and CS as V••n••· When V1 • 0 , 0 reaches 0.6 V, the limiter transistor, QL, turns on, causing the base of the internal pass transistor to become negative with respect to its emitter. Consequently, Qp is abruptly turned off and the output is shut do\vn. The maximum collector current allowed for the pass transistor is 150 mA T he resistor, Rsc, must be at least 4 Qin order to afford burn-out protection. (Rsc = V, •• ,./lsc = 0.6 V/lsc, where lsc is the short-circuit current.) We shall take Rsc = IO Q , which limits lout to 60 mA. We may now use our results to select the components necessary for constructing a voltage regulator with an output of 15 V.

218

PROJECT Pl V;n (unregulated)

V"

Vo VOUl

v,.,

Rsc

v rog (regulated)

CL 723

R

cs Inv.

N.I.

v-

Freq. comp.

c (a)

R,

R ...___ _ __ --

v,..g

(b)

Fig. Pl-3. (a) High-voltage regulator adjustable from 7 to 37 V; (b)

equivalent circuit for the regulator neglecting the currentlimiting feature.

R 1 = 4.7 kn R 1 = decade box or 10 kn pot

R = 2.2kn Rsc

= io n

C =JOO pF RL = decade box

219

VOLTAGE REGULATORS

You may use any input (Vi that has a minimum voltage of 17 V at 60 mA, but to truly appreciate the functioning of the regulator it is best to use an unregulated source. You should never apply a voltage that is greater than 40 V. Use R 1 to adjust the output to 15 V. Note the value of R 1 and compare with the prediction of Eq. (I). Find the maximum current (a load, RL, of IO Q is sufficiently small for this task). Find the range of output current for whlch 14.85 V < V,.g ~ 15 V (i.e., l percent regulation). Do changes in Ve have any measurable effect on the output provided that Ve > 17 V? 0

)

2. Now modify your circuit as shown in Fig. P l-4(a) in order to make a low-voltage regulator (2 to 7 V). The equivalent circuit [Fig. Pl-4(b)] consists of a voltage divider connected to a pass transistor through a voltage follower. The value of R1 can be 0, but is chosen for minimum temperature d rift to equal

R _ R1R2 r - Ri + Rz

(3)

The output of this regulator is easily determined from its equivalent circuit:

V:

_ V

rea -

r ef

R1

Rz

+ Rz

(4)

Build the circuit using R 1 = 2.7 kQ R 2 = decade box or 10 kQ pot

R 1 = 2.2k!1 R sc

=

10 !1

C = 100 pF

C,0 , = 1 µF Apply an input voltage that is greater than 9 V at 60 mA (but < 40 V). Adj ust the output to V, 08 = 5.00 V, a nd test your circuit as in step 1. 3. (Optional.) We shall now build a low-voltage fold-back currentlimitiog regulator with an external pass transistor. A circuit with fold-back limiting has an output as shown by the graph in Fig. P l-5(b). A power supply with such a limiter is useful when transient demand for current is high but when bum-out protection in the short-circuit condition requires that current be held to a much lower value. T he external pass transistor in Fig. P l -5(a) extends the possible current range from 150 mA (using the internal transistor) to 15 A (using a 2N3055). Si nce the feedback to the inverting termfoal is still taken from the actual output point, the output voltage is not affected by the additional pass transistor. The voltage, V,.,, is still given by Eq. (4). The analysis of the current-limiting featu re is a bit more complicated.

220

PROJECT Pl

v• v,.r

Ve VOU\

v,.q

Rsc

CL

723 N.I.

c,.,

cs RL

Inv. F.C.

v-

Rr '7

c

-:-

(a)

R, Ve

(b)

Fig. Pl-4. (a) Low-voltage regulator with adjustable output in the range from 2 to 7 V; (b) equivalent circuit.

You should satisfy yourself that

V: - V _ VoutR4 cs = ..... - RJ + R4 It should also be clear that V

CL -

Vou1

= V,.8

+ I.u,Rsc

We can now solve these two expressions for / 001 : lout

= R v,.. + (R + R4) v..... 3

RscR 4

3

R scR 4

(5)

VOLTAGE REGULATORS

221

2N 3055 15U v+

Ve

v,. ,

2.7 kU

R1

10-kS1 pot

R2

v out

v,.g

Rsc

1 kU

RL

CL 723

1 µF

cs Inv F.C.

N.l. v-

c,.,

R3

lout

C

R4 4.7 kU -:-

1 nF

1

(a)

>~

Operating range

.,;

c:n

l3

~

... s:J :J

0

Output cu rrent, lout (b)

Fig. Pl-5. (a) Fold-back current-limiting regulator with an external pass transistor; (b) output voltage versus output current for a foldback current-limiting regulator.

The knee in the output curve [as in Fig. Pl-S(b)] should occur when

v••

0 ,.

~o. 6V :

(6)

PROJECT Pl

222

When the output is actually shorted to ground (V,.2 = 0), the shortcircuit output current , fsc' can be immediately obtained from Eqs. (5) and (6): (1)

These expressions can be rearranged to give the design conditions for constructing a regulated power supply with a particular V,. 2 , !knee• and 18 c:

R4

=

R3

R

_ R3

sc -

_ l

V,.,lsc

v••oseUknee -

+ R4 V,....

R4

l sc

(8)

lsc) (9)

Equations (8) and (9) allow you to choose the appropriate values of R 3 , R 4 , and R sc to obtain a particular fsc and !knee for a given V,.2 • Build the fold-back limiting regulator as diagrammed in Fig. Pl-5(a). Adjust the pot, R 2 , until the output, V,.8 , equals 5 V. Measure the short-circuit current, lsc. by using a load resistance of IO Q. If you use an ammeter to measure lsc, be sure that its internal resistance is !GT. Remember that the maximum output voltage of the op amp is fixed by the op-amp power supply (usualJy ± 15 V). Be sure to connect the cathode of the SCR and the bridge to the same ground. Since this ground should be the universal ground, the transformer must be isolating.

TEMPERATURE CONTROLLER

231

6. You should now be ready to turn the full circuit on and begin controlling temperature. Adjust the set point to about 10 to 15°C above room temperature. Slowly decrease the set-point resistance while monitoring the temperature with a second calibrated thermistor or thermocouple. After the temperature has settled down near the set point, you should measure the duty cycle for a given setting of the Variac (R) (about 100 V). The duty cycle equals time on/(time off+ time on), where times arc measured usu1g the LED and a wristwatch. Repeat this measurement for a different setting (80 V, for example) of the Variac. Calculate the average power delivered to the heater over a full on-off cycle for the two cases above. Use an oscilloscope to measure the peak voltage (V,,) across the heater. The power delivered by the half-wave rectified signal of the SCR is P 0 n = v;/4R 11• (The time average over the full cycle of the controller is P 0 n x duty cycle.) 7. Measure the temperature oscillations around the set point. Note how these oscillations are affected by the length of the duty cycle. Vary the gain of the controller by changing R1 and observe the effects on the controlling process.

ALTERNATIVES Substitution of a R elay . A relay may be used as diagrammed in Fig. P3-4. In this case only the coil need be grounded. The high-current part of the circuit may be connected directly to a Variac or the line.

6 n----0..------........

4.8-V, 300-U coil

Fig. P3-4. Relay circuit that may be substituted for the SCR in Fig. PJ-3. The relay should close at 12 V or Jess and draw less than I0 mA.

Proportional Control. Since the controller itself provides an output that is proportional to the temperature error (when used with R 1 ), the entire controller will operate in the proportional mode if a suitable power controller is provided. In this case you might use any programmable power supply of sufficient output.

232

PROJECT P3

Practical Applications. In actual usage, controllers are very often required to handle more power than used here. The basic circuits discussed are still applicable ; the only changes necessary are the choice of components with higher ratings. For example, to operate the power controller with a 500-W capacity directly from the line, use a relay with 125-V, 5-A contacts. The SCR or triac can also be used in a direct line connection if the bridge, power controller, a nd an op amp power supply are all operated versus a floating common. This common can be tied directly to the low side of the line (neutral). The previous example requires a 5-A SCR with a 200-V PRY. These circuits are very useful in the maintenance of a constant temperature bath. Here, you must use an immersible thermistor and an immersion heater (or even an ordinary light bulb with just the glass part submersed).

project P4:

audio power amplifier

The power output of an op amp can always be increased by adding an external power boosting stage, such as the one used in Experiment AlO. In this case the absolute maximum power is determined by the power rating(s) of the transistor(s) used. It is quite easy to obtain an output power of 10 W or more by using this technique. This power level represents more than 100-fold increase over the power level available from an op amp such as a 741 or 307. Since the addition of external components adds to the cost and complexity of a circuit, it is often better to use an IC power amp in place of an inexpensive low-power op amp. There.are a variety of IC audio power amplifiers on the market that can provide up to 2 W into an 8-.Q load. The 380 audio power amp is an example of this sort of device. Its full specifications are provided at the end of this project, but for the moment you should note that the 380 has a gain of 50 (34 dB). This gain is fixed at 50 by an internal feedback resistor. It will normally not be necessary (or appropriate) to use external feedback with this amplifier. The amplifier is really not an operational amplifier in the true sense; however, it is provided with at least two familiar features, inverting a nd noninverting inputs. The amplifier is not intended for de signals, so the inverting input is provided in order to allow a 180° phase reversal between input and output. The 380 has differential inputs that float 150 k.Q above ground. That is, the input impedance at either terminal is 150 k.Q to ground. A unique input stage of the 380 allows the amplifier to use a single (monopolar) power supply and to accept zero-crossing input signals. The output is pegged at one half the power supply voltage when the input is at 0 (grounded). Thus, the maximum output swing is obtained for an ac input 233

PROJECT P4

234

that is referenced to ground. For example, if the power supply voltage is 10 V, the output will equal 5 V when the input is 0 V. If an input signal of ±0.1 V is applied, the output oscillates between 0 and 10 V (i.e., the amplitude oftbe output signal is 5 V). This power amplifier can be used by itself if a gain of 50 is sufficient, or it may be used in conjunction with a preamplifier when higher gain is required.

PARTS !Cs:

741 (or 318), 380.

Resistors: 100 Q (2 W), 100 and 220 k.Q, and 0 to 1-kQ pot, and a decade resistance box. Capacitors: Optional: capacitor.

I µF (unpolarized), 500 µF (15 WV de). Microphone and speaker, 250-kQ pot, and 0.0022-µF

Power supply: ± 15-V supply (the current of at least 500 mA).

+ 15-V supply must have an output

PROCEDURE I. Build the circuit as shown in Fig. P4- l, but without the optional tone control. Connect a sine-wave input signal (::s;;;0.2 V peak, 500 Hz). Verify that the preamplifier (741) is functioning properly before making the connection to the power amp (380). If the de offset at the output of the preamp is greater than 0.2 V de, you will have to build a de offset circuit. (See Experiment A4 or AlO.)

2. Now complete the rest of the circuit using a 100-Q load resistor on the output of tbe 380. Monitor the output with your scope and find the maximum power that can be delivered to the 100-Q load before the output waveform clips. Try a variable resistor as a load . Set the output voltage to 2 V peak and vary the load resistance from 10 Q to 100 kQ. What range of output resistance is permitted? Restore the 100 Q load resistor and test the frequency response of your amplifier. What are the 3-dB points (output decreased by 30 percent)? 3. Connect the microphone to the input and the speaker to the output. Test your PA system. If you have trouble with distortion, try connecting a 100-Q resistor in parallel with the speaker. Monitor the output with your oscilloscope. Can you whistle a sine wave?

AUDIO PO WER AMPLIFIER

235

380 Audio power amp: 14

Bypass

N.I.

v-·{ Inv.

v-

2

13

3

12

4

11

5

10

6

9

7

8

v· NC

}v-·

150kU Input resistance (Z,n ): Gain IA): 50 Bandwidth (BW): 65 kHz Supply voltage ra nge: 8 to 22 V Short·circuit cu rrent !Isc ): 1.3 A

NC VOUI

Top view • Pins 3, 4, 5, 10, 11, 12 are connected togeth er as a heat sink.

0.002~µF Tone control rl (optional) f 250kU

220kD.

+15

v +15

1µF

v

o---j f - -J\/\JV\....---4>---1 Input

6 500µF

1 ki1

______,____

__~:+_:v:~~ l"'

3, 4, 5 10,11,12

· 0.1 µF optional for improved ripple rejection.

Fig. P4-1. 380 Audio Power Amp used to make a 2-W audio amplifier.

4. You may wish to add the tone control shown in Fig. P4- l. Try to deduce its effect before you test it. It is also instructive to connect your function generator as an input. Listen to sine waves and square waves at 1 kHz. Observe the effect of your tone control on the sine and square waves (with your ear and your scope). When do the sine and square waves sound the most alike? Explain.

project PS:

sample

and hold circuits

A sample and hold circuit functions as an analog memory. A voltage level presented at the input is stored upon command as a de voltage, which is continuously available at the output. The output remains unchanged until another command causes the circuit to again look at the input. Such circuits are invariably bulky when compared to their digital counterparts. Analog memories also have the disadvantage that the stored information is gradually lost over a period of ti me. The major advantage is that the use of sam pie and hold circuits in analog circuits eliminates the necessity of analog to digital (A/D) conversion. Keeping the circuit purely analog markedly reduces the cost and complexity. The sample and hold circuit is useful when a simple memory operation is required, such as the averaging of two voltages that do not occur simultaneously. One voltage can be sampled and held until the second voltage is available to be averaged with it. For instance, this technique can be used to find the average of the positive and negative peaks ofa time-varying signal. A simple circuit that iUustrates the basic features of a sample and hold circuit is shown in Fig. P5-l. The analog voltage level is stored on the capacitor. The RC input network filters high-frequency noise, and the voltage on the capacitor is continuously read by the voltage follower. As was seen in Expcrimen t A2, the output voltage will decay slowly in the hold mode because of leakage currents in the capacitor. A practical sample and hold circuit is illustrated in Fig. P5-2. The voltage range over which the circuit operates must be kept under ± 7.5 if the 4016A bilateral switch is used (i.e., v+ - v- = 15 V; see Experiment C3). The voltages at in (pin 1) and control (pin 13) must never exceed the

236

SAMPLE AND HOLD CIRCUITS

Hold

'237

>-~~-o Output

Input~ 0-----'1.llJIR,,,,__--+-1 Sample

Fig. PS-I. Simplified sample and hold circuit.

supply voltage levels, v+ and v- . If a simple MOSFET is used in place of the 4016, the voltage range can be raised to ± 15 V. A high-quality polycarbonate or mylar capacitor is used to minimize output voltage drift in the hold mode. The minimum time required for sampling an input voltage is con· trolled by the "on" resistance of the 4016 (about 300 fl) multiplied by the capacitance. For the circuit as designed, RC= 14 msec. The circuit is basically a voltage follower. Note that the memory capacitor and the sampling switch are placed within the feedback loop. This feature eliminates any problems resulting from voltage losses across the switch or the JFET. The voltage-follower configuration ensures that the voltages in the feedback loop will be automatically adjusted to cause the output to exactly equal the input.

PROCEDURE I. Build the circuit shown in Fig. P5-2 using v+ = 5V and v- = -5 V. If a :1: 5-V supply is not readily available, you may convert your standard ± 15-V op amp supply as shown in Fig. P5-2(b). 2. Use an input of + 1 V. Monitor the output as Ve is cycled between sample (Ve= 5 V) and hold (Ve = -5 V). With Ve tied to -5 V, set the input (Vi 0 ) to 0. The output (V0 u 1 ) should continue to read IV. You sbould repeat this test for an input of - 1 V. Record the voltage on the capacitor in each of these cases. You must use a high-impedance voltmeter (DVM or VTVM). 3. With the circuit holding at 1 V and the input at 0, try to determine the amount of drift in the output. Obtain an answer in terms of volts/minute. 4. The sample and hold function can be controlled electronically by any circuit capable of providing an output -1- 5 V (sample) and - 5 V (hold). The gate can be driven directly by any CMOS logic device operating from a ± 5-V bipolar supply. Here we have taken VDD = +5 V (logical 1) and Vss = -5 V

v100kS1 Output (Vou1)

v•

o-----t...-- -- - -- -- -- - -- - -- -- --, 02 A1

v+

v•

14

01 6

2

4016

In

Out

Control 13

7

v-

v-

v•

v-

0

Hold

Ve

Sample

r

(a) Components: A1 : CA3140, 318, or equivalent. 0 1: 4016 CMOS quad bilateral swi tch, or MOSFET transistor. 02: HEP80 1. N-channel JFET, or equivalent. C: 0.047 -µ F nonpolarized. preferably polycarbonate or mylar.

+15

v 100

n. 1 w

- - --ov+= 5V Z l, Z2: 5-V. l ·W Zener regulator diodes

- - --o v - = -5 v 100 n, 1 w

- 15 v (b)

Fig. P5·2. (a) Practical sample and hold circuit; (b) circuit to convert ± 15-V supply to ±5V.

238

239

SAMPLE AND HOLD CIRCUITS

(logical 0). If the gate is to be driven by TTL logic ( + 5 V for 1, 0 V for 0), an additional circuit is needed. The comparator circuit pictured in Fig. P5-3 interfaces TT L logic with CMOS logic. The switching level is adjusted to be in between the TTL on and off levels. Build the circuit in Fig. P5-3 and adjust R 2 and R 3 so that Vtui = 15(R2 /R 1) = Vvv = -1- 5 Y, and V;u 1 = -15(R3 /R 4 ) = Vss = - 5 V. Connect the comparator to the circuit in Fig. P5-2 and verify that a TTL low causes the circuit to sample and a TTL high causes it to hold. +15 v

IN914B Sample: V;n < 0.4 V

V;n

R;

R2

2

o to 2.5 kn

47 kn Hold: 2.4 or Vi.cz>· Improvements. If you wish to experiment with an external oscillator such as a square-wave generator, as the clock, remove the connections to pins 13 and 5 of the 4016 and replace them with the outputs of a 4027 JK FF. The external oscillator must have a signal that goes positive and negative with respect to ground. The threshold voltage of the 4027 will be between - 3 and +3 V for a power supply voltage of ± 7.5 V. Another common use of an analog multiplexer is the conversion of a strip-chart recorder or xy plotter into a multichannel device. The only modification required would be a time constant of a few seconds. If C = 50 µF and R = 100 kll, the alternating period is a few seconds, which is suitable for most recorder applications. The extension of our circuit to several channels is not difficult. Perhaps the easiest method is to use a 4017 (or 4022) counter with decimal output wired with a 4001 gate as a divide-by-4 counter. The counter outputs corresponding to 0, 1, 2, and 3 should be used as the control voltages for the 4016 (pins 13, 5, 6, and 12). The clock of course would be the input for the 4017. Two additional 74ls would be needed as well.

PA RTS !Cs: Resistors:

4016, 4001, 741 (2) or 747 (or 324). 1 MQ (8), JO kQ pots (2), 100 kQ (1).

Capacitor:

0.1 µF.

project

PB:

electronic music box

One advantage of digital electronics is the wealth of intriguing output devices such as LEDs, MAN-4, or Nixie tube displays. In this project we use a combination of digital and analog I Cs to produce a low-grade electronic organ that can remember a tune. To complete this project, you should read Experiment Dl3 first. The 7489 is a volatile RAM that can store 16 words of 4 bits each. When the R/W switch (Fig. P8-l) is open, the output of the RAM is the 4 bits contained at the address given by the 7493 outputs (0 to 15). To enter the sequence 1 2 3 4 2 1 into locations 0 through 6, we would first put 0 0 0 1 on the data lines, reset the 7493 to 0, and then touch R/ W to ground momentarily. One more clock pulse to the 7493 moves the address to 0 0 0 1, and we put 0 0 1 0 on the data lines. Touch R/W to ground, and so on. We can read the contents of the memory by setting the clock frequency to 1 Hz and monitoring the output lines (pins 11, 9, 7, 5) with LEDs or a decoder- display (Exp~riment 08). You will notice that the output is inverted and open collector (hence the four pull-up resistors between the output pins and 5 V). We shall explain how best to generate data and clock frequencies shortly. The output of the memory is a number in binary form, which must be converted to an analog voltage. Our output is inverted (the binary number 0 0 1 1 or 3 will appear at the output as 1 1 0 0), but, as we shall see, this inversion does not matter. The output voltages are fed directly to a noninverting adder similar to circuits built in Experiment A3. Tbe output of the adder is

v.out = R, R, + R, (v,2 T, V24 T, v38 + 16 v4)

248

+ 5V

I

+5 v

+15 v

Rt

-

mo kn 1 kn

5

50 kn

.. .

+15 v

22 kn

__lJ

7 11 Clock

-----i 14 4 2

9 3

6

8 15

C0unt

5

V4 80 kn

7

5

o~"610

A

~

4

~1 kn ~1 kn T

I

~ 10; kn -1~ v -::-

2

T A

3

I

7489

I

3

\

-::-

4' son

8 --'-

l

Fig. PB-1. Electronic music box. T he resistor values are not critical. Data

~

8

566

7

3

""'"+~ V;). ~

V3 40 kn

to the 7489 must be in binary form. The clock input to the 7493 should be from a variable-frequency oscillator (0.2 Hz and greater).

250

PROJECT P8

The voltages Vi through V 4 are equal to either 5 V or 0. Since the RAM inverts, a binary 0 1 I 1 comes out as l 0 0 0, or Vi = 5 V and V2 , V 3 ,

v4 = o.

The next unit is a 566 function generator. These ICs operate on a supply voltage of 15 V and give an output signal whose period is dependent on the input voltage to pin 5. In practice, the 566 shuts off for voltages below 9 V and above 14 V, approximately. Notice that if we choose the op amp components R; = 50 k.Q and R 1 = JOO k.Q, when V 1 , V2 , V 3 , V4 = 5 V, V0 ut is approximately 15 V, and when Vi = 0, V2 , V3 , V 4 = 5, Vout is 7.5 V. These two conditions are the same as "data in" equal to 0 0 0 0 (V0 u, = 15) and 1 0 0 0 (Vout = 7.5 V). The 566 will give a low frequency for 0 0 0 0 and a somewhat higher frequency for 0 0 0 l until, by entering I 0 0 0 and causing V0 ", = 7.5 V, there will be no output from the 566. The RC combination for the 566 determines its frequency range. By choosing R = 22 k.Q, C = 0.01 µF, the maximum output frequency will be slightly less than 1 kHz. The output (either square wave or triangle wave) of the 566 can drive a 50-.Q headset directly. If you use an 8-.Q speaker, a power amplifier (Experiment AIO or Project P4) or a matching transformer is required. Operation. Wire the RAM and be sure you are able to read and write numbers in different locations. Remember that the contents of the RAM vanish when the power is turned off. The 7493 is convenient to use as an address generator because it gives a binary number out, 0 0 0 0 through 1 I 1 1. The clock input to the 7493 can be either a bounce-free switch or an oscillator capable of 0.2 Hz. We suggest using a decoder-display to monitor the DCBA outputs of the 7493. Next connect the 741 as shown. You can use any combination you like for R1 , but R1 must be varied from 100 k.Q to about 150 k.Q. Exact values for the resistors are not too critical for your first attempt. Select an input to the RAM ofO 0 0 0, tap the R/W switch, and check that Vi = V 2 = V3 = V 4 = 5 V. Set the output of the 741 to about 14 V. Select an input of 0 I 1 1, write this into memory, and then verify that tbe output of the 741 is about 7 or 8 V. Connect the output of the 741 to the function generator, 566. You should get a low frequency for an entry 0 0 0 0 and no sound at all for I 0 0 0. To program the music box, enter a sequence of notes (0 0 0 0 is low frequency, 0 I 0 0 is high, 1 0 0 0 is a blank) by addressing the memory manually or with a frequency of 0.2 Hz. You must create the data, and depress R/W momentarily for each location. We strongly urge the use of an encoded keyboard (P6) or the output of a counter for the input data. As an example, the numbers 3 8 3 8 3 8 1 1 1 8 8 8 8 8 8 represent sometbjng like the opening bars of Beethoven's Fifth Symphony. The easiest way

ELECTRONIC MUSIC BOX

251

to enter the sequence is to present an 8 (I 0 0 0) to the input and hit the R/W switch as the address counter goes through the locations 1, 3, 5, 9 to I 5. Then apply a 3 (0 0 I I) to the RAM input and enter th is 3 in locations 0, 3, 5. Finish by entering ls in locations 6, 7, and 8. Now, play back the melody at a frequency of about 5 Hz. Electronic music is a burgeoning field; if you're interested, back issues of Popular Electronics and Radio-Electronics have many excellent articles on music synthesizers.

Improvements. Using a CA3140 op amp eliminates the necessity for tbe ± 15-V supply. The CA3140 may be operated using pin 7 connected to 5 volts and pin 4 to ground. If the 566 is replaced by a 555, an 8 .Q speaker (witha l µF series capacitor) can be driven directly from pin 3 on the 555 IC.

PARTS ICs:

7493, 7489, 741, 566.

Capacitors: Resistors:

0.01, 1.0 µF. 1 kn. (4), 10, 20, 22, 40, 50 (2), 80, 100 k.Q, 100 kn. pot.

Miscellaneous:

high impedance head set or speaker.

project

PB:

Boolean puzzles

A digital system is often used to monitor or to respond to particular events or sequences of events. In such applications, digital electronics is used not as a computational tool but as a controller and recorder. For example, imagine a burgla r alarm that requires you to open a door, turn on an entrance light, and turn off a second light in the proper sequence within 20 sec to prevent au alarm from ringing. Other examples include the control of industrial processes requiring a fixed sequence of events. Designing digital control circuits requires little in the way of theoretical knowledge (a little Boolean algebra helps) and a maximum of ingenuity and inventiveness. The two circuits presented in this project are relatively simple, since each requires only one quad-NA ND and one quad-NOR gate for logic. However, the circuits are quite interesting to use and will entertain anyone who is normally entertained by puzzles. From some experience, we caution trying out the puzzles on any friends who either (I) continually bemoan the dehumanization of man by machines or (2) refer to their stereo as a phonograph.

Combination Lock. There is a seq uence in which the three switches of Fig. P9-l can be closed that will light the OK lamp and not extinguish the alarm light. You may object that, when all three switches are in the closed position, the OK light is on and so is the alarm light. However, if you had started with a closure of switch I, the alarm would have gone off until the switch was opened or some other switch closed. If we had connected a negative-edge-triggered monostable (74121) in place of the ala rm light, the monostable would stay on for a considerable time (time enough to set off an

252

BOOLEAN PUZZLES

253

t 7400

t 7400

1

t 7400 OK

9

·11-o

10

\ t 7402

3

t 7400

t 7402

Pin 14 of 7402 and 7400 to +5 V Pin 7 of 7402 and 7400 to ground

Fig. P9-J. Only one sequence of switch closures will light OK without turning off alarm. The pin numbers assume that a 7400 is used for the inverters and the NANO gate, while a 7402 is used for

the NOR gates. Pin 14 of both ICs goes to 5 V and pin 7 goes to ground. (All switches are maintained-action.)

automatic telephone dialing system to call the police, for example). In fact , only one of the six possible orders (1 2 3, l 3 2, 2 1 3, etc.) will work. You might wonder what would happen if you try to close all three switches simultaneously. The answer of course is that "simultaneously" would mean closing all three switches within less than a microsecond of one another, and without any contact bounce. Because a monostable stays on even if the trigger pulse drops to 0, any deviation from the correct sequence, even for a microsecond, would sound the alarm. An analysis of the p uzzle can take two routes. The scientific method is to make a truth table in which the eight possible states of Sw 1, Sw2, and Sw3 are listed along with ALARM and OK. You should then recognize that you start in state 1 1 1 (all open) and must end in 0 0 0. You must proceed from state to state by closing one switch at a time, and the only valid states are the ones for which ALARM equals I. The second route is "hit-and-miss." Try 2 3 1 as an order, since we already decided closing SWJ first causes ALARM to go low. When you see that this order does not work, try 3 1 2, and so on. The correct order? The sequence is given at the end of Appendix B.

PROJECT P9

254

Meclianica/ Ri11gs. This puzzle is the digital analog of an ancient toy in which rings of descending size are to be transferred from one stake to another by using yet a third stake. The 011ly rules are that only one ring at a time can be moved and at no time can a larger ring be placed on a smaller ring. In our puzzle, four momentary contact switches, Swl through Sw4 control four LEDs, LI through L4. As Fig. P9-2 shows, each switch is made bounce-free by using simple inverters (7404) rather than the NAND gates of Experiment D7. This design actually exposes the high output of the inverters to a momentary short as the switch cycles. However, the inverters are sturdy enough to withstand this slight bending of the TTL rules. Bach cycle of a given switch causes the flip-flop connected to that switch to change state. There is no "cross talk" between switches: no switch can turn on or off any light other than the light corresponding to that switch. All lights can be turned on by closing the clear switch momentarily. To operate the puzzle begin by turning all the LEDs on. Operate Sw2 and notice that L2 can be turned on and off. Leave L2 on and tum LI off by operating Swl. Notice that L2 cannot be toggled (turned on and off) as long as Ll is off. The trick of the puzzle is to turn all the lights off. The operation of L2, L3, L4 depends on the state of the preceding Ugbts. An analysis of the NAND and NOR gates controlling the JK FFs should lead you to the correct sequence. If you are interested in a quick answer turn to the end of Appendix B. The analysis is not very difficult. LI toggles all the time. L2 can toggle only when 1Q is low. lf 1 Q is low (meaning LI on) then the NOR gate labeled A will have a low output since the Q of Sw2 is normally high. When Sw2 toggles, the Q output of Sw2 drops low, momentarily causing N OR gate A to give a 1 output momentarily. The JK FF (2) will trigger on the negative edge of the pulse and L2 will toggle. If 1Q is high, NOR gate A stays low regardless of whether or not Sw2 is toggled. A similar analysis works for L3 and L4. If you wish to extend the puzzle, it is important to choose the Q and Q outputs of the bounce-free switches properly. For example, if we had used the Q output of the second switch, L2 would bave gone out wben LI went out. The extension is simplified because the condition on the first two lights is the same for toggling L4 as it is for toggling a proposed LS (or any number). If you continue, L6 requires the same condition on Ll, L2, and L3 as would LS, and so on.

PARTS Combination Jock: SPST switches (3) 7400, 1402, LEDs (2) and dropping resistors (2)

N

Sw3

a

Q

A

+5

v

+5 v

c 14

c

1

3

4

FF2

FF1 11

10

12

- - - 2 --- 10- - 13

/L 1

-;-

Clear

5

7 10

-

8 - - - ---

~

9

6

20

II

FF3

13

2

I

30

/L2

..,.

Clear

1

4 14 3

!~

/I L3

I Clear

-=-

~

8l

Fig. P9-2. Mechanical rings puzzle: all fou r bounce-free switches can be

put together using only 8 of 12 inverters contained in two 7404s. The momentary contact switches are shown in their rest (or normal) position. FFl a nd FF2 are both contained in a single 7473 package; FF3 and FF4 are in the second 7473 IC.

5

(__;

F4

6

40

J< -=-

!Clear

i

Clear

256

PROJECT P9

Mechanical rings: SPST momentary-contact switches (4) ; ICs, 7473 (2), 7404 (2), 7400, 7402, LEDs (4) and dropping resistors, 370 n (4). [The dropping resistors may be eliminated by using the four previously unused inverters in the 7404s to drive the LEDs. Since those buffers are inverting, their inputs must be taken from Q outputs of the flip-flops (pins 12 and 9).]

project

PIO:

reaction tinJe ganJe

This is an instructive " toy" in which the prize goes to the quickest finger. Two players each control a switch [Fig. PIO- l(a)] that can light an LED. Whoever pushes his switch first lights his LED and prevents the opponent from lighting his. Both players should close their switches in response to a signal. We use the circuit of Fig. D5-2 to light an external LED a few seconds after the trigger switch is closed. The lighting of this LED is the signal for each player to push his button. Sophisticated version: After playing the game, you will notice that there is no penalty for jumping the gun. F igure Pl0-2 suggests how to make a circuit that will turn on your opponent's light if you close your switch prematurely. The trigger LED is normally on, but goes out when the trigger switch is operated. When the light comes on again, each player closes his switch.

PARTS Simple version ICs: 7400, 74121 (2). Capacitors: 50 µF (2). Resistors: I 00 kQ (2), 370 Q (2); switches (SPST)(2), LEDs (2). Sophisticated version: one additional item of everything Jjsted above. 257

PROJECT PIO

258 NC

17400

3 sec

}

74121

j_

A

Q

-:-

NC

a

I•

~

Q A

1-

74121

*

a

I•

3 sec

7400 (a )

2 3 4 5

NC

lOOkn

11 +5 v

50µF

6 7

•I

l'

+5 v

14

10

+

14

7412 1

2

13

3

12

4

11

5

10

+5 v

6

9

lOOkn

7

8

-:-

•I

1 3 4

14

5

11

6 7

50 µF

-=-

7400

INC

10 74121

-:-

-:-

(b) Fig. PIO-I. (a) Block diagram of the reaction time game; (b) schematic diagram.

Player A

iJ~NC Cir

QT

to AA

QB

Aa

Play er B

QJ

All gates are

t 7400

74121 ·1~1

NC

50µF

l ~

\0

QA

6QA 7

10

74121 5V

1

14 100H2

-:-

+

...__._ Player A

Fig. PJ0-2. Sophisticated reaction time game.

5"

14

~ 100 kn

I T+

50 µF

10

06

I 3 As 4 11 5 86 6QB 7 10

.........-... Trigger

1 AA

A8

3 AA 4 11 5 BA

11

6 QT 7

1

100kU

· 1~~5Br

Or

74121

~v

3 4

°" ---!__,/l

":"

Player B

.l- 50 µF

PROJECT PIO

260

PROCEDURE Start with the simple version. The LEDs should stay on for a few seconds. If their behavior is erratic, you may have to reduce R to 47 kfl or less and increase C. The value of 100 kfl is technically outside of the specifications for the 74121.

NOTE The switches shown are normally closed so that, when operated, the NAND gate inputs will both be high and the output will drop from high to low (negative edge). If your switches a re normally open, you can use one extra gate as follows: connect pin 13 [Fig. PIO-l(b)] to the switch and ground the other side of the switch. Connect pin 12 to high (pin 14). Finally, connect p in 11 to pin 1. The switch, of course, is no longer connected directly to pin 1. When the switch is closed, pin JI goes from low to high and pin 1 goes high ; if pin 2 is stj)J high, then the output at pin 3 will drop from high to low. The second switch would be wired using pins 8, 9, and 10 with pin 8 connected to pin 4.

project

Pll:

minutes timer

Digital circuits are especially well suited for building various types of clocks. A simple timer that uses only CMOS devices is shown in Fig. Pll-1. This circuit uses the 60-Hz line frequency as its time base. The line signal is stepped down and clipped to a safe value within the power supply voltage range of 10 V (V00 = 10 V, Vss = 0). The NAND Schmitt trigger (4093) shapes the clipped sine wave into a pulsed waveform suitable for triggering CMOS counting circuits. The first counter (4018 presettable divide-by-n) divides the input frequency (60 Hz) by 6 (see Experiment Cl 0). The output of this shift counter begins at a high and six pulses later returns to a high. This output is fed to another 4018 counter, which is wired to divide by 10. Since all 4018 counters trigger on the positive edge of the clock waveform, the modulo-10 counter will count each time the preceding 4018 counter has made a complete cycle of six counts (modulo-6). Consequently, the output of the modulo-10 counter pulses once every second. This 1-sec pulse rate is again divided by 6 (third 4018) and divided by IO (first section of 4518 dual BCD decade counter). Notice that it is once more necessary for each counter to trigger on the positive edge of the waveform. Now, the output at Q4 (pin 14) of the first BCD decade counter provides a single pulse for every 3600 oscillations of the line voltage. This pulse at Q4 ends (negative edge) after I min bas elapsed from the beginning of the count. The negative-going edge from Q4 is used to trigger the final decade counter in the 4518 package. Negative-edge triggering is obtained by connecting the input signal to CE (CLOCK ENABLE) and grounding Ck (CLOCK) (see Fig. Cl0-2).

261

45188

45119

10

v

10

+-

N

~ Ck

° 10 Vat 100 mA Vss = 0

Power supply : V 00

al

l

LT

A

2 8 6 c D

02

03

Re~

LE

14

5

8

-:-

4018A

10

..,...,4

12~11

3

60 Hz

1

15

6.3 V ac -:RcsetD lOV

l Count l

PE

6,

Ck

02

Data

03

Reset

B Vss

I

V 00

a.

05

:

10 V

4018A 10 V

5

10

4

-:-1 4

6

1

11

15

13

a

0.,

PE

Ck

~,~ ~

Ck

Da ta Reset

3

o.

-

05

11

10 V

--iJ

1 ~Data B

13

10 v

4018A

PE

Reset

v

I

3 7

o,

~Ck CE

lO V

10 0

16

CE Reset

v

6, 62

- I6 03

a. Os

-:-

Fig. PJl-1. Minutes timer that flashes its decimal point once a second.

MINUTES TIMER

263

The output of the last counter (pins 3 through 6) keeps track of the number of minutes elapsed. This information is decoded by the 4511 , and the result of the minutes count is displayed by the seven-segment LED. You should also notice that the Q 5 output of the modulo-JO 4018 counter is used to cause the decimal p oint on the display to flash once a second. In the interest of keeping a minimum package count, unused sections of the 4093 are employed as the buffer shown in the diagram. A 4069 (or 4049) hex inverter may be substituted for the 4093. (For information on how to use an inverter as a Schmitt trigger see Experiment D4.) The adjustable resistor (5-kO trimpot) attached to the output of the buffer allows the brightness of the decimal point to be adjusted to match that of the display.

PARTS !Cs: 4018 (3), 4518, 4511B, and 4093 (or 4069). Resistors: Diodes:

1kO,0- to 5-kO trimpot, and 1.5 kO (7). 6.8-V Zener.

Transformer:

120 V ac primary, 6.3 V ac (or 12.6 V ac).

PROCEDURE I . Build the time base section composed of the transformer, Zener, and Schmitt trigger (at the extreme left side of your board). Use your oscilloscope to verify that the line signal has been successfully converted into a pulsed waveform. 2. Now begin at the extreme right side of your circuit board and wire the display section (4511B and MAN-4) and the dual BCD counter (4518). Verify that this section is working by using pulses directly from your time base to Ck (pin 9). How often should the numeral change? 3. Now complete your timer by adding the three 4018 presettable divideby-n counters as shown. Verify that the timer works. This timer is very useful in darkrooms for measuring development and fixing times. If you wish to make it self-contained, you will need to refer to Appendix E to learn bow to build an appropriate 10-V power supply.

project

Pl2:

frequency counter

A frequency counter has four main sections: l. counter, 2. display, 3. control, and 4. power supply. The counting section is composed of cascaded decade counters (Experiments DlO and CJO). The display can have a variety of forms, but the most common type is the seven-segment LED (Experiments D8 and C8). The control section is responsible for converting the circuit from a simple counter to a calibrated frequency counter. For example, if the counters are allowed to count for precisely I sec, the count total will equal the frequency of the incoming pulses. The heart of the control section is an input gate controlled by an internal time base (see Fig. Pl2-l). The time base produces pulses that turn the gate on and off at precise intervals. The input gate used in the frequency counter shown in Fig. Pl2-l is a TTL four-input NAND Schmitt trigger (see Table Pl2-l ). This device functions as a pulse shaper as well as a gate. The input signal must lie between 0 and 5 V, but can be slowly varying and/or noisy. With timing pulses spaced Table Pl2-l TTL DEVICES

Control section

74 l 3 7473 74121

Counter

7490

Decade BCD counter (negative-edge triggered)

Display

7475

Quad bistable latch BCD-to-seven-segment decoder-driver Seven-segment LED (common cathode)

7448

MAN-3

264

Four-input dual NAND Schmitt trigger Dual MSJK FF Monostable multivibrator

To latch enable of next stage

1 sec Timing pulses

To reset of next stage

To Am of next stage

From RBO of next stage, or from ground

5V 5V

7473

5V

7490

7

-=-

Input -~§

'

~ 7413

....._,

Gate ON I

Control waveforms:

•1 sec+

~

I

I

I

Reset~

11!"""re~t Latch enabled to update display

N

6

I

I

I

Y1

.., v -

7475

I

[

7448

I

7448

5V

._.,Ain

d R0

A D

5V

ng Rg

B

c I

7490

-=-

7475

5 v-

Fig. P12-1. Two-digit frequency counter using TTL devices. Additional

digits may be added by making the connections shown (arrows).

-=-

PROJECT P12

266

I sec apart (1-sec period), the 7473 MS JK FF supplies a waveform that is high for I sec and low for 1 sec. Input pulses are counted while the waveform is high (gate ON). At the end of this interval, the negative-goi11g edge of the control waveform triggers the first 74121 (see diagram), which produces a sharp positive pulse ( ~ 30 nsec). This positive pulse causes the latches to transfer the results of the latest count to the display. Once the pulse goes low, this new information is held until the next latch-enabling pulse arrives (after the next counting interval). In addition, the falling edge of the latch signal causes the second 74121 to produce a second pulse, which resets the counters to 0. The 7490 decade counters can be cascaded by connecting the D output of each stage to the A input of a follow ing stage. The magnitude of the count is determined by the length of the timing pulses. For a 1-sec gate time, display A represents l's (i.e., 1 through 9 Hz) and display B represents !O's. If the gate time is decreased to 0.1 sec, then A = 1O's and B = 1OO's, and so on . Our frequency counter is also set up to blank nonsignifican t zeros . For example, 6 Hz will be displayed as 6. not 06., but 60 Hz will appear as 60. The 7448s are equipped with an automatic blanking control. When the RBI (ripple-blanking input) is at 0, the display is off (unlighted) when DCBA = 0000 (i.e., 0 will not be displayed). Also, when these conditions are met (RBI = 0, DCBA = 0000), the RBO (ripple-blanking output) is low. Connecting the RBO of display B to the RBI of display A ensures that A will not display a 0 if Bis 0 as well. However, if B =.: 0, then RB08 = 1 and display A is allowed to light a 0.

PARTS !Cs: 7413 (or 7400), 7473, 74 121 (2), 7490 (2), 7475 (2), 7448 (2). Display : MAN-3 LED (or equivalent); displays from Fig. D8-l, C8-l, or Cl0-2 (b) can also be used.

PRO CEDURE I. You may use the counting unit from Fig. Cl0-2(b) if the latch and reset pulses are lengthened by using a capacitor (0.01 to 0.001 µF) between pins 10 and 11 on the 7412ls. The actual latch pulse required for the 451 lB is the inverse of the pulse shown in Fig. P 12- I. This pulse may be obtained from Q (pin I) on the first 74121. (The Q output must still be used to trigger the second monostable.) If you are bui lding your frequency counter from scratch, follow the diagram. Build and test the counting and display sections first (see Experiments DlO and D8).

FREQUENCY COUNTER

267

2. Now build the control circuit as shown (with the modifications suggested above if you are using a 451 lB). If you have a dual-trace scope, look at outputs of the two 7412l s simultaneously. 3. Interconnect the various sections of the counter as shown (bold lines in the diagram). Apply 1-sec timing pulses to the clock of the 7473. In our case these pulses must come from an external source (function generator or timing from Project P l 1). Apply an offset sine wave or pulsed waveform to the input (pin 5 of the 7413). Vary the frequency between 0 and 100 Hz and observe the results. What happens when the timing signal is changed to a period ofO.l or 10.0 sec?

SIMPLIFIED OPTION If this project is to be done as part of another experiment, a quicker and less sophisticated frequency counter can be made as shown in Fig. PJ 2-2. This counter eliminates the use of latches on the display. As a result, the display will change as the count is being made (i.e., during "gate ON"). Timing

pulses

5V

5V 0

1 2 3 4

14

14

Ck

3 Al 4 A2 5 74121

- 13 Q 12 Q

7473

6 Q

9

7

11

' - - - - -- - -- - - To all resets

1, 2, 4

Input

6

o---- -- - - 5 --t.__

o - -- - - --+- To A ;n of first 7490

_.

~ 7413

Fig. PJ2-2. Simplified version. No latches used.

APPENDIXES

4:

269

appendix

A: equipment ;ind supplies

The experiments and projects in this manual require the use of certain standard pieces of equipment. A well-outfitted experimenter should have an oscilloscope, a function generator, a digital multimeter, power supplies, and some type of breadboard system. The following is a brief description of the types of equipment available, along with a list of their manufacturers and suppliers: Oscilloscope. Dual-trace scopes with 10-MHz response are recommended. Inexpensive models are available from Tektronix, Philips, and others. Function Generators. There are a variety of reasonably good and inexpensive models available thanks to the marvels of LSI (large-scale integration). Try Wavetek or Hewlett-Packard. Digital Multimeter. Getting cheaper a ll the time. Three and half digit units for $200 are available from Hickok. Slightly more expensive units are available from Fluke and Keithley. Powe1· Supplies. You will need a regulated variable voltage supply with current limiting (available from Lambda and others). The current-limiting feature means that the supply automatically crosses over to a constant current source when the output current a ttempts to exceed a given preset level. The alternative is to buy a cheaper fused supply and wear a bandolier loaded with extra fuses and ICs. If t he variable supply can provide an output voltage in excess of 35 V, it can be used to supply both linear and digital I Cs (see Experiment Al).

270

EQUIPMENT AND SUPPLIES

271

If you want to use any of the IC circuits in an outside application, you will need a supply tailored to the job. There are basically two choices: (1) build your own- cheap but painful (Appendix E has some simple circuits); (2) buy modular +5- and ± 15-V supplies on the surplus market (these run about $20 per module). Plug-in Socket Boards. These have been a tremendousboonforstudents and experimenters. E&L has pioneered the field. Breadboard Systems. E&L markets a box with a 5- and ± 15-V power supply, switches, potentiometers, and a socket board. They also supply a unit devoted to digital designing. We find these units invaluable for our own tinkering (designing). Students who are just beginning seem to learn more from seeing separate sources for oscillator, power supply, and potentiometers. The specially constructed "designers" may actually make things too easy for the students. Integrated Circuits and Components. Consult the last five pages in Radio-Electronics or Popular Electronics for surplus suppliers. We like Hanifin for discrete components and any of the surplus houses for I Cs. There is little reason to buy any thing mentioned in this manual at list price. However, if you cannot find it surplus, Allied or Newark Electronics will usually have it. You should also make the acquaintance of your local electronics parts store.

ADDRESSES Mail-order suppliers Allied Electronics 1355 Sleepy Hollow Road Elgin, Illinois 60120 Newark Electronics 500 N. Pulaski Road Chicago, Illinois 60624

Device manufacturers Analog Devices 221 Fifth Street Cambridge, Massachusetts 02142 Burr-Brown Research Company 6730 S. Tucson Boulevard Airport Industrials Park Tucson, Arizona 85706

272

APPENDIX A

Philbrick/Nexus Research 25 Allied Drive at Rt. 128 Boston, Massachusetts 02026 Components manufacturers

Motorola Semiconductor Products 5005 E. McDowell Road Phoenix, Arizona 85008 RCA, Solid State Division Sommerville, New Jersey 08876 Signetics Corporation 811 E. Arques Avenue Sunnyvale, California 94086 Texas Instruments, Inc. P.O. Box 5012. Dallas, Texas 75222 Surplus suppliers

Ancrona Corporation P.O. Box 2208R Culver City, California 90230 Poly Paks P.O. Box 942R Lynnfield, Massachusetts 01940 Hanifin Electronics Corp. P.O. Box 188 Bridgeport, Pennsylvania 19405 Solid State Sales P.O. Box 740 Sommerville, Massachusetts 02143 Equipment manufacturers

E & L Instruments 61 First Street Derby, Connecticut 06418 General Radio (Gen Rad) 300 Baker A venue Concord, Massachusetts 01742 John Fluke Manufacturing Co., Inc. P.O. Box 7428 Seattle, Washington 98133

EQUIPMENT AND SUPPLIES

273

Hewlett-Packard 1501 Page Mill Road Palo Alto, California 94304 Hickok Electronic Instruments 10514 Dupont Avenue Cleveland, Ohio 44108 Keithley Instruments 28775 Aurora Road Cleveland, Ohi9 40660 Lambda Electronics Corporation 515 Broad Hollow Road Melville, Long Island, New York 11746 Philips Test and Measuring Instruments 400 Crossways Park Drive Woodbury, New York 11797 Tektronix Incorporated Box 500 Beaverton, Oregon 97005 Wavetek Box 651 San Diego, California 92112

SOLUTIONS Experiment D13

RAM DIP LED Modulo-8 JFET MOS

sos

TTL PL

RTL MSI PROM M/S FF

DTL WOM

Random-access memory Dual-in-line package Light-emitting diode See the glossary Junction field effect transistor Metal-oxide semiconductor Silicon-on-sapphire Transistor-transistor logic Injection logic Resistor-transistor logic Medium-scale integration Programmable read-only memory Master-slave flip-flop Diode-transistor logic Write-only memory (ajoke)

APPENDIX A

274

MOSFET

LSI µP I/O DPDT A/D

LSB CMRR S/N

BW BCD ASCII

vco SCR

Metal-oxide semiconductor field effect transistor Large-scale integration Microprocessor Input-output Double-pole, double-throw switch Analog-to-digital Least significant bit Common-mode rejection ratio Signal-to-noise Bandwidth Binary-coded decimal American Standard Code for Information Interchange Voltage-controlled oscillator Silicon-controlled rectifier

Project P9. The correct order of switch closures for the combination lock is 321. The lights in the mechanical rings puzzle will turn off if the order of switch action is 2 l 4 l 2 l 3 1 2 I . To operate any light, aU the lights in front of it must be off except the one immediately before it.

appendix

B:

understanding data sheets

DIGITAL I Cs , TTL The most important aid to understanding data sheets is a precise understanding of the terms and symbols used. Referring to the data sheet for the 7400 quad NAND gate, you will notice that the first table gives recommended operating conditions. The column labeled N OM lists the nominal (or best) values for power supply voltage and operating temperature. The columns labeled MIN and MAX together determine the recommended operating range. These limits are not absolute, but if operating conditions are allowed to stray very far from the recommended range, the device can be expected to operate erratically or fail. The statement concerning fanout means that the manufacturer guarantees that each gate can drive up to IO TTL unit loads (i.e., 10 TTL inputs). In practice, you may find that a particular gate may successfully drive more than 10 unit loads, but this level of performance is not guaranteed. We shall now turn our attention to the table entitled "Electrical Characteristics." The best approach here is to simply study the following list of definitions and note the values specified by the data sheet.

DIGITAL PARAMETERS, TTL Vin : Higll-/evel ilput voltage (also abbreviated Vm). Any input to both terminals exceeding the minimum of VinSol'.

RL

=- 4000

'oc1m

Proo1gat10n delay time

Ct•15oF .

AL

·•oon

10 to91cal 1 tevel

• f-o r eondit1on1 thown ut M IN or MAX, ..,,. tho i1pt) rol)riat11 "• IV~ •PGCltted unoer recornm&ndt1CI tft1\llco tvP•· 0 • • All typical ....,tu11 ., • • , Vee . 5V, TA .. 2& u1 Offset Currt:nt Input s ..s C4J,,tnl ln~ul Aes.1st~nce

Rs '"° 10k$l

mV

50

Ovtrshoo1

0.3

tnpu1 Capaolanc:e O H M.it V0113o!JC A cJjU\;Hnt1n1 Range L&•Q&•$ign!'I Voltogci G1t1n

mV nA nA

M1l pF

2.0

! 1S ! 13 90 10 ?.00.000 ! 14 !13 75 2S

...

OutOt.1 1 Shou°C11cu1t Cuuent Sut)f)ly Current Powtt" ConS'Jm pt ion Tr1nd1n1 R~sponl4! fun11v gainl R1tct•me Slow Ritt The follo-.ving spr.dtlc11lons apply lotO"C