Telecommunication Electronics 1630817368, 9781630817367

Table of contents :
Contents
Preface
1 Radio System Architectures
2 Transistor RF Amplifiers
3 Frequency Conversion Circuits
4 Phase-Locked Loops: Operation, Circuits, and Applications
5 Analog-to-Digital and Digital-to-Analog Conversion
Acronyms and Abbreviations
List of Symbols
About the Authors
Index

Citation preview

Telecommunication Electronics

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For a complete listing of the Artech House Telecommunications and Network Engineering Series, turn to the back of this book.

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Telecommunication Electronics Dante Del Corso Vittorio Camarchia Roberto Quaglia Paolo Bardella

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Library of Congress Cataloging-in-Publication Data A catalog record for this book is available from the U.S. Library of Congress.

British Library Cataloguing in Publication Data A catalogue record for this book is available from the British Library.

Cover design by John Gomes ISBN 13: 978-1-63081-736-7

© 2020 ARTECH HOUSE 685 Canton Street Norwood, MA 02062

All rights reserved. Printed and bound in the United States of America. No part of this book may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying, recording, or by any information storage and retrieval system, without permission in writing from the publisher. All terms mentioned in this book that are known to be trademarks or service marks have been appropriately capitalized. Artech House cannot attest to the accuracy of this information. Use of a term in this book should not be regarded as affecting the validity of any trademark or service mark. Many product and company names that occur in this book are trademarks or registered trademarks of their respective holders. They remain their property, and a mention does not imply any affiliation with or endorsement by the respective holder.

10 9 8 7 6 5 4 3 2 1

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Contents Preface

xi

1

Radio System Architectures

1

1.1

Radio System Architectures

2

1.1.1 Tasks of a Radio Receiver

3

1.1.2 Basic Receiver

4

Heterodyne Structures

5

1.2.1 Benefits and Drawbacks of Heterodyne Receivers

7

1.2.2 Image Removal with RF Filter

8

1.2.3 Multiple Conversion Receivers

8

1.2.4 IF Filter Technologies

9

1.2

1.3

Complex Mixer: I/Q Processing and Image Rejection 10 1.3.1 Single Sideband Transmitter

11

1.3.2 Image Rejection Mixer

12

1.4

Zero IF and Low IF Structures

15

1.5

Digital and Software-Defined Radio Systems

17

1.5.1 Mixing and Sampling

19

1.5.2 Subsampling and Folding

21

1.5.3 Sampling Signals with Spurious Components and Noise

22

1.5.4 Frequency Division Multiplexing Channel Separation

22

1.5.5 Effect of Sampling Jitter

23

1.5.6 How Many Bits Are Required?

25

1.5.7 Direct Radio Frequency Sampling

26

v

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1.6

Complete Transceiver Architectures

27

References

29

Selected Bibliography

29

2

Transistor RF Amplifiers

31

2.1

Transistor Modeling

32

2.2

Small-Signal Amplifiers

33

2.2.1 Amplifier Bias Network

34

2.2.2 Small-Signal Models

39

2.2.3 High-Frequency Transistor Models

40

2.2.4 Single-Stage Configurations

42

2.2.5 Analysis of a Common Emitter Amplifier

46

2.2.6 Nonlinearity and Distortion

50

2.2.7 SPICE Transistor Models

53

Low-Noise Amplifiers for RF Receivers

54

2.3.1 Fundamentals

57

2.3.2 Design

63

Power Amplifiers for RF Transmitters

66

2.4.1 Power Amplifiers Figures of Merit

66

2.4.2 Power Amplifier Classes

71

2.4.3 High-Efficiency PAs: Switching and Harmonic Tuning

76

2.4.4 Efficiency in Back-Off: Doherty and Envelope Tracking

80

SPICE Netlists

83

References

86

Selected Bibliography

88

3

Frequency Conversion Circuits

89

3.1

Frequency Mixers

89

3.1.1 Mixer Figures of Merit

94

3.1.2 Mixer Architectures

96

2.3

2.4

2.5

3.1.3 Switching Mixers

101

3.1.4 Diode Passive Mixers

106

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Contents

3.2

4 4.1

4.2

4.3

4.4

vii

3.1.5 Transistor Passive Mixers

110

3.1.6 Transistor Active Mixers

113

3.1.7 Mixer Nonidealities

116

Frequency Multipliers

119

3.2.1 Frequency Multipliers Figures of Merit

120

3.2.2 Frequency Multiplier Architectures

121

3.2.3 Diode-Based Frequency Multipliers

122

3.2.4 Transistor-Based Frequency Multipliers

126

References

127

Selected Bibliography

128

Phase-Locked Loops: Operation, Circuits, and Applications

129

Analysis of PLL Systems

130

4.1.1 Definition of PLL

130

4.1.2 PLL Linear Analysis

131

4.1.3 PLL Transfer Function

133

4.1.4 Steady State Phase Error

137

Phase-Frequency Behavior

141

4.2.1 Loop Analysis and Butterfly Diagram

141

4.2.2 Capture Range and Lock Range

144

4.2.3 PLL Equivalent Noise Bandwidth

147

Phase Detectors and Voltage-Controlled Oscillators

153

4.3.1 Phase Detectors for Analog Signals

153

4.3.2 Phase Detectors for Digital Signals

155

4.3.3 Mixed-Signals Phase Detectors

157

4.3.4 VCO Circuits

160

PLL Applications

163

4.4.1 FM and AM Demodulation

163

4.4.2 Coherent AM Demodulation

167

4.4.4 Digital Modulation and Demodulation

169

4.4.5 Frequency Synthesizers

173

4.4.6 Direct Digital Synthesizers

175

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4.5

4.6

5 5.1

5.2

5.3

5.4

5.5

4.4.7 Data Resynchronization and Clock/Data Recovery

179

Examples of Integrated PLLs

182

4.5.1 General Purpose PLL: CD4046

183

4.5.2 Tone Decoder PLL: NE567

186

4.5.3 All-Digital PLLs

191

MATLAB Scripts

192

References

194

Selected Bibliography

194

Analog-to-Digital and Digital-to-Analog Conversion

195

Digital Representation of Analog Quantities

196

5.1.1 Analog Quantities and Digital Quantities

196

5.1.2 Sampling Process

197

5.1.3 Quantization Process

202

5.1.4 Analog-to-Digital Conversion Systems

208

Digital-to-Analog Converters

212

5.2.1 Static and Dynamic Parameters

212

5.2.2 Errors in Digital-to-Analog Converters

213

5.2.3 Circuits for Digital-to-Analog Conversion

217

Analog-to-Digital Conversion: Basic Techniques

227

5.3.1 Static and Dynamic Parameters

228

5.3.2 ADC Taxonomy and Basic Structures

231

5.3.3 Mixed ADC Architectures

236

Analog-to-Digital Converters for Specific Applications 244 5.4.1 Oversampling and Differential Converters

244

5.4.2 Logarithmic Analog-to-Digital Converters

249

5.4.3 Model Encoding

253

Signal Conditioning

255

5.5.1 Input Protection

256

5.5.2 Input Amplifier

257

5.5.3 Anti-Alias Filter

260

5.5.4 Multiplexer

261

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Contents

ix

5.5.5 Sample&Hold

263

5.5.6 Total ADC System Errors and ENOB

268

References

270

Selected Bibliography

271

Acronyms and Abbreviations

273

List of Symbols

277

About the Authors

281

Index

283

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Preface This book describes the overall structure of telecommunication radio systems, from block diagram structures to circuit details and examples. The emphasis is on the functions that characterize these systems, such as radio frequency amplifiers at the receiver input (low noise amplifiers) and at the transmitter output (power amplifiers), mixers, phase lock loops, and—due to the steady migration of functions to a digital implementations—analog-to-digital and digital-to-analog conversion systems and circuits. The overall goal is to provide an understanding of the various solutions and trade-offs for radio communication hardware, with guidelines for the design and/or selection of the functional units characterizing such systems.

Prerequisites The book assumes a preliminary knowledge of basic applied electronics: BJT and MOS transistors, operational amplifiers, feedback principles and basic analog and digital circuits. Other prerequisites include communication concepts like spectral analysis, amplitude distribution, analog, and numeric modulations.

Contents The book is organized in five chapters, covering topics from radio systems to amplifiers, from mixers and the frequency multipliers, to phase-lock-loops and analog/digital conversion systems. Chapter 1 describes the structure of a radio transceiver and provides a first view of all functional units, discussing the migration to software-defined radio. The following chapters describe in detail the various functional units, addressing discrete device radio frequency amplifiers for receivers and transmitters (Chapter 2), mixers and frequency multipliers (Chapter 3), phase-locked loops (PLLs) (Chapter 4), and finally a variety of analog-to-digital and digital-to-analog conversion circuits and systems (Chapter 5). Each chapter starts with a functional identification of the units described (i.e., what the module does); it then presents the details of the most used circuits (i.e, how the required function is carried out), with some examples xi

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of commercial integrated devices. This sequence reflects the design procedure: function definition first, then research and analysis of solutions, detailed design, and finally critical review. This procedure allows a fair comparison of the various solutions and design trade-offs.

Learning Outcome This book is aimed at designers of telecommunication equipment at both system and circuit level. It has been designed for university-level courses that describe and analyze the structure and the details (down to circuit level) of functional units for such systems. The focus is on system parameters and structures, with an overview of the various implementation choices, and, for some specific solutions, a detailed discussion of key design issues, down to circuit level.

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1 Radio System Architectures This introductory chapter describes the architectures and functional blocks of radio receivers and transmitters, which are analyzed and described in detail in the following parts of this book. Specific problems are highlighted, such as image frequency rejection and channel separation. The impact of the characteristics of various modules on global system performance is also discussed. Radio system architectures have continuously evolved since the first wireless transmission by Marconi in 1894; the most important steps in this evolution are outlined in Table 1.1. The definition of radio spectrum range is not unique; according to the International Telecommunication Union (ITU) allocation it ranges between 3 Hz and 300 GHz [1], as shown in Figure 1.1. This book covers systems extending up to a few gigahertz. The heterodyne architecture, based on frequency translation, is presented here as a basic reference. Then, other important variations such as multiple conversion and zero intermediate frequency (ZIF) will be discussed as well. Section 1.1 introduces the basic receiver structures and parameters; heterodyne receivers are introduced in Section 1.2, and complex in-phase and quadrature (I/Q) mixer structures in Section 1.3; ZIF systems (Section 1.4) and software defined radio (SDR) systems (Section 1.5) are then presented. Moving to the transmitter, the basic architectures are briefly described in Section 1.6, highlighting the main differences with respect to their receiver counterparts; the transceiver structure discussed later in this book is presented.

1

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Table 1.1 Most Relevant Steps in the Evolution of Radio System Architectures Event or System First wireless transmission (G. Marconi) Discrete devices (R, C, L, tubes) Solid state discrete devices (R, C, L, transistors) Integrated circuits for low-frequency functions Integrated circuits for radio frequency functions Radio circuit in a single integrated component Multiple radio systems in a single integrated component Radio as functional unit inside integrated circuits

Year 1894 Since 1900 Since 1950 Since 1960 Since 1980 Since 1990 Since 2000 Since 2010

Figure 1.1

Radio spectrum with AM and FM broadcast bands.

Figure 1.2

The wireless information transfer chain. The focus of this chapter is on radio receivers; most of the issues discussed here are also relevant to transmitters.

1.1 Radio System Architectures The architecture of a radio system, shown in Figure 1.2, contains the following functions: • Information source: For example a microphone, or some digital data source. This unit provides the input baseband signal. • Transmitter (TX): The functional unit that transforms the baseband signals into modulated radio frequency (RF) signals. Transmitters are complex systems that include several functional blocks. • Transmission channel: Antennas and in-air channel, or an optical fiber, or any other transmission medium. • Receiver (RX): The functional unit that transforms the high-frequency signal into a baseband signal from which the information is recovered. This block includes several units and can be realized in different

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Radio System Architectures

Figure 1.3

3

Basic operation of the radio receiver. The input signal va (t ) from the antenna contains the desired signal (usually weak), plus many sources of noise and interferences. The receiver output signal vo (t ) should be a copy of the original modulation, with as little as possible noise and/or distortion added. (a) System block diagram, receiver side; (b) antenna signal Va (f ) (frequency domain); (c) receiver output signal Vo (f ) (frequency domain). Real signals have conjugate symmetric Fourier transforms, but in this book the attention is focused on the positive frequencies axes only.

technologies and topologies. The receiver chain is used as reference guide for the following Chapters. • Information user: For example, a person listening to an audio signal, electronic equipment for data analysis, etc. The reference examples are an amplitude modulation (AM) radio, followed by heterodyne receiver, I/Q structures, and ZIF and SDR systems. As for any electronic system, a radio can use analog or digital signals and circuits. Digital communications are intrinsically more reliable and robust than analog communications. Moreover, the use of digital circuits leads to less expensive and more flexible radios. For these reasons, the world of radio systems has moved from the full analog systems of the early days to the almost-completely digital circuits used in modern radios, where only few critical functions are still based on analog circuits. 1.1.1 Tasks of a Radio Receiver A radio receiver (Figure 1.3) is a system that handles a modulated RF signal (Va (f ) in the diagram1 ), collected by an antenna, and extracts the information contained in one of the channels (e.g., a broadcast radio station). This information is converted into a suitable representation, such as an electric signal vo (t), able to drive a transducer such as earphones or a digital recorder. The desired signal is mingled with a variety of other signals, originated by other channels, electro magnetic interferences (EMI), and noise. Therefore, the receiver must have a tuning capability to select different channels as well as selectivity to isolate the desired signal. 1 In the following, the notation x (t) = X + x (t) is generally used to indicate the total signal a A A (xA (t)), its DC component (XA ) and its time dependent component (xa (t)). The Fourier transform of the same signal is generally indicated as Xa (f ).

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The electrical signals collected by the antenna may have very low levels (down to a few microvolts), or—in the case of nearby transmitters—medium levels (such as a few hundred millivolts). In both cases, they must be demodulated and amplified to a power level useful to drive output transducers. Before the circuit output, information must be extracted from RF signal by a demodulator. 1.1.2 Basic Receiver The block diagram in Figure 1.4(a) shows the simplest receiver architecture, which must provide the following sequence of functions: 1. Tuning and selectivity, to isolate the wanted channel from the large number of RF signals collected by the antenna; 2. Amplification, to increase the power of the selected signal; 3. Demodulation, for information recovery from the RF signal. The response of the input filter must be shifted (e.g., using a resonant circuit, tuned by changing the L or C reactive parameters) to select different channels. In order to suppress undesired channels, the input band-pass filter (BPF) needs steep a frequency response, that corresponds to a high Q, defined as the ratio between the center frequency of the filter and its bandwidth. The design of such a filter is not easy, especially when the tuning requirement is considered [2, 3]. These constraints drive the development of various receiver architectures, as described in the following sections. Figure 1.5 shows a crystal receiver, which is an old radio receiver using the architecture described in Figure 1.4. The crystal is a point-contact diode (usually

Figure 1.4

The basic receiver. The input filter can be tuned to different frequencies (fa , fb , . . .). In this example Va (f ) is an amplitude-modulated signal, and the demodulator is a rectifier. (a) Block diagram (the amplifier is optional), (b) signals in the frequency domain; tuning is achieved shifting the frequency response of the resonant circuit, (c) signals in the time domain.

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Radio System Architectures

Figure 1.5

A crystal receiver. (a) Block diagram, and (b) schematic diagram. For both views: (1) antenna, (2) BPF (tuning), (3) demodulator (e.g., cat’s whiskers diode), (4) low-pass filter, and (5) audio transducer (earphone, loudspeaker).

built from a natural mineral form of lead sulfide, or galena), which allows us to build the AM demodulator. The antenna can be a large coil, which is also part of the RF band-pass resonant circuit. Tuning is achieved by changing the value of the capacitance of the filter thanks to a variable capacitor. This device can operate as AM receiver in long-wave (LW), medium-wave (MW), and short-wave (SW) radio band ranges. This solution does not contain amplifiers, and the output power comes directly from the RF signal. As a result, this receiver can drive only a pair of earphones, and requires a high power transmitter with high gain antenna. Since no power supply is required, the system is always operational, without the need for batteries or other power sources. A similar architecture is currently used in the receiver of passive radio-frequency identification (RFID) devices, where the energy to operate the device is extracted directly from the RF signal. The following sections present the evolution of radio receiver structures.

1.2 Heterodyne Structures The product of two sine waves, with frequencies fa and fb respectively, contains both the sum beat, at frequency fS = fa + fb and the difference beat, at frequency fD = fa − fb : 1 sin(2πfa t) sin(2πfb t) = [cos(2π fS t) + cos(2πfD t)] 2

(1.1)

In the frequency domain, the mixing can be seen as a translation of the sine wave centered at fa around fa + fb and fa − fb . Since the attention is focused on the positive part of the frequencies axes, it is common to indicate the difference beat frequency as fa − fb if fa > fb and fb − fa otherwise, in such a way that fD > 0; this is possible since the cosine in (1.1) is an odd function. Considering a more general case, if a signal with spectrum X (f ) is multiplied by
a sine wave with frequency fb , the spectrum of the resulting signal is  1 2 j X (f + fb ) − X (f − fb ) .

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Figure 1.6

Heterodyne receiver. (a) Block diagram: (1) Input BPF, (2) LO and mixer, (3) IF filter and amplifier with narrowband, frequency fIF = fa − fLO . (b) Signals in the frequency domain. The input signal, with bandwidth Ba is shifted to a frequency fIF = fa − fLO . Tuning shifts the frequency fLO of the LO. (1) local oscillator LO, (2) input signal spectrum, (3) input BPF, (4) difference beat IF signal and IF BPF, and (5) sum beat (not used).

This technique can be applied to a radio receiver as shown in Figure 1.6, where fa is the RF signal from the antenna, and fb = fLO comes from a local oscillator (LO). The spectrum of the input signal (e.g., a modulated signal centered at fa ) is translated to the difference and sum positions. This frequency translation is the key operation of the heterodyne receiver. In the structure shown in Figure 1.6, the RF signal Va from the antenna is filtered (band-pass input filter) to remove out-of-band signals and noise, then multiplied by the LO signal: this causes a shift in the frequency domain to the sum and difference beat positions. The IF channel includes a BPF to isolate one of the beats (usually the difference beat), which is then amplified and demodulated. The IF signal after the beat is then centered at fIF = fLO − fa or fIF = fa − fLO . With this heterodyne architecture, all the circuits after the mixer (i.e., the IF chain) operate at a fixed frequency, which allows us to improve performances, especially for the filters. Channel separation is achieved by the IF filter, which operates at a fixed frequency; its design is therefore simpler than at RF, and the Q factor is improved by one of more orders of magnitudes. On the other hand, the requirements on the RF filter are relaxed, and it is designed to pass all the possible channels that the radio must be able to receive. Only fIF can go through the IF filter; to receive another channel the system moves the frequency of the LO to a new value f˜LO , so that the mixer brings the RF signals to IF around the frequency fIF = f˜a − f˜LO or fIF = f˜LO − f˜a .

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7

1.2.1 Benefits and Drawbacks of Heterodyne Receivers The heterodyne radio receiver structure has several benefits: • Tuning is achieved by shifting the LO frequency; • Channel isolation is achieved by fixed-frequency IF filter and there is no need for tunable narrowband filter; • Amplifiers and demodulator operate at fixed IF and can use narrowband circuits, which are easier to design and test. However, this structure also presents a drawback: two RF signals actually contribute to the received IF frequency. The first one is the wanted signal, RFa , centered around fa = fLO −fIF . The second signal, RFb , is derived from the down conversion of the frequencies around fb = fLO + fIF ; this unwanted component is called the image frequency because it is mirrored around the local oscillator fLO , as shown in Figure 1.7. The spectrum in the frequency band of the image frequencies can come from other transmitters and can be stronger than the useful signal, causing interferences and blocking since high-level signals can drive the low-noise amplifier (LNA) or the mixer into saturation, making the receiver unable to detect the useful signal. A number of variations of the basic heterodyne architecture have been introduced to handle the problem of the image signal, removing the IF signal components coming from RFb . Since in the IF chain image and wanted signal are in the same frequency range, they cannot be separated by filtering. Removing the image is the major problem in the heterodyne receivers and can be accomplished in several ways: • • • •

Figure 1.7

Filters at RF level, before the mixer; Multiple conversions; Image rejection mixers; ZIF and I/Q architectures.

Drawback of heterodyne receivers. The wanted signal and the image are moved to the same IF frequency and cannot be separated by IF filters.

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Figure 1.8

Removal of the image (fb ) by RF filter (1). The IF filter (2) isolates the desired channel (fa ). (a) Block diagram; (b) signals in the frequency domain.

1.2.2 Image Removal with RF Filter Image components can be removed at RF level. The RF input filter allows all channels within the desired bandwidth to reach the mixer, but blocks images (see Figure 1.8). For multichannel receivers, the RF filter needs a wide bandwidth, which makes image rejection more difficult. An RF input wide-bandwidth BPF removes noise and out-band interferers; all desired channels are still present at the mixer input. The mixer translates the spectrum of the desired channel to the IF frequency. The RF input filter (wide band) isolates the set of channels, then the IF filter (narrow band) keeps only the single channel. The tuning, i.e. the selection of the desired channel, is achieved by shifting the LO frequency fLO . A good channel separation filter requires steep edges (high Q); this is difficult to achieve with variable frequency at the RF level, but easier at the fixed-frequency IF. The combined effect of frequency translation and narrow IF filtering can be seen as a narrow BPF (with IF bandwidth) on the RF signal. When the LO is moved, the effect is the same as shifting a tunable band-pass with a high Q on the RF signal, as shown in Figure 1.9. The main benefit of the heterodyne technique is that narrowband filtering is moved to the fixed frequency IF chain. The IF filters can be designed to comply with tight specifications, such as high Q and controlled shape. The image is removed by an RF BPF before the mixer, which must allow all channels to go through, and provide high out-band attenuation. Such a filter is easier to design and build if the distance between the desired channels and the images is large, and this is the case in high IF solutions. Receivers designed for multiple frequency ranges (e.g., cell phones) use a set of input filters, one for each RF band, to further reduce noise and interferers. 1.2.3 Multiple Conversion Receivers As shown in Figure 1.10, when high IF is used, image frequencies are far from the wanted signal (the actual distance is 2fIF ). On the other hand, a low IF can

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9

Figure 1.9

Isolation of a single channel from noise and interferers. Out-band signals (1), wideband noise (2) and image are removed by RF filter after the antenna (3); adjacent channels (dashed vertical lines) are rejected by the IF filter (4). The wanted channel (5) can go through the RF and the IF filters.

Figure 1.10

Effect of IF value on images. (a) Low IF: image is close to correct signal, it requires high-Q RF filter; and (b) high IF: the image fb2 is far from correct signal, it allows low-Q RF filter.

achieve good channel separation with IF filters having a relatively low Q factor. A structure that brings together the benefits of high IF (image rejection) and low IF (channel isolation) is the double conversion heterodyne shown in Figure 1.11. The IF channel at fIF1 is moved to a lower frequency fIF2 with a second beat; since fIF2 is lower, the same bandwidth can be achieved with lower Q. The first higher frequency IF (fi1 ) makes the image removal easier and the second lower frequency IF (fi2 ) allows simpler channel filters. Tuning can be achieved by shifting either local oscillator (LO1, associated to fi1 or LO2, associated to fi2 ). The dual frequency conversion has the benefits of both high and low IF: • Easy image removal, due to the larger separation between wanted signal and image; • Good channel isolation, due to narrow bandwidth of the filter at frequency fi2 . 1.2.4 IF Filter Technologies High-Q BPFs are expensive and difficult to build with standard LC technology. Other possible technologies include mechanical resonators (surface acoustic wave (SAW)), ceramic, and quartz. LC tuned circuits (Figure 1.12(a)) require tuning and are rather expensive. Bandwidth control requires multiple stages. These filters are difficult to integrate

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Figure 1.11

Double conversion heterodyne. (a) Block diagram with wideband LNA and filter (1), IF1 filter and amplifier (2), IF2 filter and amplifier (3). (b) IF1 signals, (c) IF2 signals.

Figure 1.12

Examples of IF filters. (a) LC tuned circuit; (b) basic structure of a SAW resonator filter.

due to the inductors and can be replaced by SAW devices, which exploit mechanical resonance and can provide high Q at low cost (Figure 1.12(b)) [4]. In SAW filters, the electrical signals are converted to a mechanical wave that travels across a piezoelectric crystal or a ceramic plate. The wave propagates with minimum attenuation at the mechanical resonant frequency, and at the other end is converted back to an electrical signal. The SAW uses ceramic materials and is less expensive than quartz crystals. RF filters for cellular phones use SAW technology. Better performance can be obtained with quartz lattice filters, which consist of a combination of several high-Q mechanic resonators (e.g., quartz, crystals). Single crystals have a unique resonant frequency; multiple crystals can be combined in lattice structures to obtain wider bandwidth. Due to their high cost, these crystal filters are used mainly in high-end instrumentation and equipment.

1.3 Complex Mixer: I/Q Processing and Image Rejection Another approach to obtain good image frequency rejection is based on sine/cosine beat combination. The starting point is represented by Werner’s

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formulas:  1 sin(a − b) + sin(a − b) (1.2) 2  1 cos(a − b) + cos(a + b) (1.3) cos a cos b = 2  1 cos(a − b) − cos(a + b) . (1.4) sin a sin b = 2 Adding together (1.3) and (1.4), the sum beats cancel out, and the result is the difference beat: sin a cos b =

cos a cos b + sin a sin b = cos(a − b) = cos(b − a).

(1.5)

The operation requires in-phase (I) and quadrature (Q) components (the sine and the cosine), and it is the basis of I/Q signal processing. This approach does not require sharp RF filters and can be used both in receivers (to get only the difference or the sum beat from the mixer, Figure 1.13), and in transmitters (to generate single sideband (SSB) signals). In a receiver, the I/Q mixing alone brings little benefit, since the difference and sum beats have wide separation and can be easily isolated by filters in the IF chain. Separate I/Q processing can be used for image frequency rejection without RF filters, as described in the following sections. 1.3.1 Single Sideband Transmitter An application of I/Q processing is represented by SSB transmitters. A standard AM signal includes the carrier and two sidebands; since each sideband carries all information, an higher spectral efficiency is achieved keeping only one of the sidebands. No power is wasted for useless signals (e.g., the no-modulation carrier), and the spectrum occupation is reduced. The sidebands can be isolated by filters, which can be quite complex and expensive. A more convenient solution is to use I/Q frequency translation, with

Figure 1.13

I/Q mixer in heterodyne receiver. Block (1) is a wideband phase shifter. The complex mixer output (2) delivers only the difference (or sum) beat.

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Figure 1.14

I/Q mixer in SSB transmitter. The spectrum of vB (t ), centered around fb , is translated around frequency fa to build the SSB signal. (a) Transmitter block diagram, and (b) signals in the frequency domain: SSB is obtained canceling one of the sidebands.

cancellation of one sideband, as shown in Figure 1.14. The technique is not new, but in the past it has been used mainly in professional equipment. Since a good cancellation requires tight gain and phase matching between the two paths, it is now used directly inside integrated systems without trimming thanks to the improvements in RF IC technology. Another critical circuit is the phase shifter. The LOs can be designed to provide both sine and cosine signals at the same frequency (e.g., with the direct digital synthesizer (DDS) technique, Section 4.4.5). The RF path needs a wideband phase shifter to get a good cancellation of the unwanted signals. Integrated 90-degree power dividers can be used to derive the quadrature components at good level of phase and amplitude matching; they are introduced in Section 3.1.2.

1.3.2 Image Rejection Mixer Beside generating SSB signals, I/Q signal processing can be used to cancel the image signals in the receivers. The diagram in Figure 1.15 shows how to remove the image component from the difference beats (the sum beats can be easily removed by filters). The sequence of operation is the following: 1. The RF signal includes RFa (wanted signal, at frequency fa = fLO − fIF ) and RFb (image, fb = fIF − fLO ): xi (t) = Aa sin(2π fa t) + Ab sin(2π fb t).

(1.6)

2. Two mixers multiply the RF signal respectively by LOI (sine) and LOQ (cosine) components; the high-frequency components resulting at the

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Figure 1.15

Image rejection with I/Q processing. The wanted signal is located at frequency fa = fLO + fIF , while the frequency of the image signal is fb = fLO − fIF . (a) Received RF signal, (b) multiplication by sine and cosine signals generated by the LO to generate I and Q components; in-phase components are shifted by π/2, and (c) the output signal; sum of XQ and X
I contains only the wanted signal.

sum of the frequencies are filtered out:   xI = Aa sin(2πfa t) + Ab sin(2π fb t) sin(2πfLO t)|filtered Ab Aa cos(2π(fb − fLO )t) (1.7) cos(2π(fa − fLO )t) − 2 2 Ab Aa cos(2π fIF t) = cos(2πfIF t) + 2 2   = Aa sin(2πfa t) + Ab sin(2π fb t) cos(2πfLO t)|filtered =

xQ

Aa Ab sin(2π(fa − fLO )t) + sin(2π(fb − fLO )t) 2 2 Ab Aa sin(2π fIF t). = sin(2πfIF t) − 2 2

=

(1.8)

After each mixer, the IF signal includes both the wanted signal and the image, overlapped to the same frequency, but thanks to the use of I/Q LO signals, the phases are different in the two branches. 3. A π/2 phase shift is applied to one channel; this generates I and Q image components with opposite signs in the two channels: xI
=

Aa Ab sin(2πfIF t) + sin(2π fIF t). 2 2

(1.9)

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Figure 1.16

Block diagram of the image rejection with I/Q processing presented in Figure 1.15.

Figure 1.17

Example of commercial GPS receiver (Maxim MAX2745 [5], ©Maxim Integrated Products. Used by permission.) with I/Q image rejection and VGA controlled by a AGC unit. A: RF filter, LNA, and I/Q mixer; B: image rejection unit; C: output VGA; D: I/Q LO with PLL synthesizer.

4. The two channels are added; only the RFa beat (the wanted signal) remains: xo = xI
+ xQ = Aa sin(2π fIF t). (1.10) This technique, shown as block diagram in Figure 1.16 is called Hartley image rejection. The I/Q components from the LO can be directly generated while the second phase shifter operates on fixed frequency (IF, narrowband). A good matching of gain and phase in the two channels is critical to achieve a high image cancellation. Figure 1.17 presents an example of a complete radio chain with image cancellation using I/Q Hartley structure in a commercial device (Global Positioning System (GPS) receiver). Another structure for image rejection is the Weaver architecture, shown in Figure 1.18, where the mixer circuit generates the I and Q IF components. The complete structure is an example of a complex mixer. The main benefit of image rejection mixers is the removal of the complex RF and IF BPFs. Their drawback is the need for a tight matching of gain and phase

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Figure 1.18

Example of image rejection with Weaver complex mixer [6].

Figure 1.19

Receiver with double conversion; the second mixer uses separate I/Q (complex mixer). (a) Block diagram, and (b) vector signal representation.

shift in the two I/Q channels to achieve good cancellation, which in turn requires an analog technology with good matching capabilities. In any case removing the image with these techniques relaxes the requirements on the RF input filter. An example of a receiver with double conversion and separate I/Q demodulation is shown in Figure 1.19. Such I/Q demodulation techniques are mandatory to recover information from complex phase/amplitude modulated signals. A critical requirement for this architecture and for all the I/Q structures is excellent channel amplitude and phase matching, which in turn determines the amount of image cancellation.

1.4 Zero IF and Low IF Structures The heterodyne approach moves the signal spectrum to the intermediate frequency; ZIF receivers apply the same principle but move the signal spectrum to DC. The LO has the same frequency as the desired channel, the IF frequency is centered on zero, and these structures are called ZIF. ZIF uses low-pass filters in the IF chain, and this allows a better control of IF parameters: a change in

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Figure 1.20

Basic ZIF operation. (a) Received signal at fa is directly moved to baseband; lowpass filter in the IF channel; (b) signal and image are overlapped; separation is not possible.

Figure 1.21

I/Q ZIF receiver. The wanted signal and the image can be separated using I/Q components.

the IF bandwidth requires only a change of the cutoff frequency of a low-pass filter (LPF). Moreover, a LPF is easier to design and build than a BPF inside an integrated circuit (IC), thereby making the architecture suitable for system-on-chip (SOC) devices. A first block diagram of these architectures is shown in Figure 1.20. With this single-branch structure, the received signal at frequency fa is directly moved to baseband; the IF channel uses a low-pass filter, but the signal and the image overlap, and separation is not possible. The most critical issues in ZIF architectures are: • Offset: DC is an in-band signal, therefore high-pass filters (to remove offset and DC unbalances) cannot be used. • LO-to-RF leakage in the mixer (oscillator pulling): This causes a DC beat, which cannot be isolated from actual RF because it overlaps the same frequency band. • The image is the same signal flipped on the frequency axis and cannot be removed by filters; image cancellation by I/Q processing is therefore mandatory, as shown in Figure 1.21. ZIF radio architectures are widely used into ICs, mainly due to the fact that the low-pass filters are easier to design and build than the band-pass filters. ZIF radio structures can be recognized by the low-pass filters in the IF chains instead of the usual BPFs. The ZIF structure is also called homodyne or direct conversion and is not new but is difficult and expensive to build with discrete components due to the critical

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matching of the I/Q paths. ZIF has been extensively used in high-end professional equipment. Integration in a single-chip device allows better matching, and now this technique is widely used in consumer systems. Offset and balance must be tightly controlled; therefore these circuits use differential signals and circuits. On the other hand, direct conversion is extensively used in upconversion within transmitters. As an example of integrated ZIF transceiver, a detailed diagram for a complete transceiver (Maxim MAX2820 2.4 GHz 802.11b ZIF transceiver [7]), with the external components required for correct operation, is shown in Figure 1.22.

1.5 Digital and Software-Defined Radio Systems All the systems previously analyzed are based on analog functional blocks for filters, amplifiers, mixers, and local oscillators. The same functions can

Figure 1.22

Commercial ZIF radio system (Maxim MAX2820 [7] ©Maxim Integrated Products. Used by permission.), with fully differential structure, from RF to outputs. A: VGA at RF front-end, with external control for AGC; B: PLL-based LO (frequency synthesizer); C: I/Q mixer with phase shifter to get sine and cosine from LO; D: LPF in the IF chain (this is a ZIF system), E: IF amplifiers with AGC; F: output amplifiers; G: filters; H: mixed pair; I: PA; J: baluns (differential- to single-ended adapters).

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be obtained also with digital circuits, with benefits in terms of design ease, fabrication cost, and flexibility. Moving from analog to digital requires an analogto-digital converter (ADC) somewhere in the receiver chain. The various ADC locations bring different trade-offs between complexity, performance, and power consumption. This section describes these choices, discussing the corresponding benefits and drawbacks, while ADCs are discussed in detail in Section 5.3. The basic concept of digital (radio) systems is to exploit the benefits of digital technology by moving complexity from the analog to the digital domain. This trend applies to all types of electronic systems and to many applications. In the case of radio systems, the limitations and drawbacks come from the high frequency and bandwidth of RF signals, which require high sampling rate. To preserve the signal-to-noise ratio (SNR), the digital processing must use a high number of bits, corresponding to a high resolution in the ADCs and digital-to-analog converters (DACs). Sampling rate and resolution both impact the complexity and power required for the digital processing; nevertheless, analog circuits are still a good choice in the system front-end, especially when a low power consumption is required. A first possibility for the digital radio is to place the ADC at the end of the receiver chain, after the demodulator, as in Figure 1.23(a). The demodulated signal is represented by numerical samples; in these structures error correction, encryption, and other functions can be easily implemented with hardware (HW) or software (SW) techniques. Carrying out similar operations with analog circuitry

Figure 1.23

Migration of functions from analog to digital. (a) ADC after demodulation, (b) ADC after IF, before demodulation, (c) ADC after the mixer, before the IF chain, and (d) frequency translation merged with sampling. Gray areas indicate analog circuits.

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is not impossible but is more complex and expensive due to signal degradation caused by noise intrinsically added at each analog processing step. A second possibility is to place the ADC at the end of the IF chain just before the demodulator (Figure 1.23(b)). In this case, the ADC samples at the IF band and requires a sampling rate higher than in the previous case. The digital demodulator provides high versatility, can handle complex modulations and use proprietary algorithms in the software, achieving improved noise immunity and robustness. Moreover, the generation of quadrature components is not affected by phase and amplitude unbalance. With digital demodulation, the same HW can support different modulation types, provided they utilize the same processing before the IF. Different information flows (e.g., voice, data, video) can be easily combined and separated. Since digital processing can be carried out by a processor (microprocessor or digital signal processing (DSP)) with SW defined algorithms, this can be viewed as the first step towards SDR. Two intermediate steps toward SDR are presented in Figures 1.23(b) and 1.23(c). The S/H, shown in these schematics as a separate functional unit, is generally integrated with the ADC. In Figure 1.23(b), the IF filter acts also as antialias filter, but signals out of IF band can be folded into baseband. While this solution is theoretically feasible, it has no practical applications. Similar considerations also apply for the circuit in Figure 1.23(c), where the mixer output must be filtered before the S/H-ADC unit. In the final configuration shown in Figure 1.23(d), the S/H acts as a mixer and carries out the downconversion. The antialias filtering is carried out by the input RF filter. For this structure, a high sampling rate increases the distance with the aliases and simplifies the channel isolation. The key benefit of the SDR is a high signal processing capability with increased flexibility, since the digital IF filter allows to modify the IF parameters via software. 1.5.1 Mixing and Sampling From a signal theory perspective [8], the sampling process applied to a continuous signal va (t) results in the sampled representation va,s (t). This process can be modeled as the product of va (t) and a train of Dirac delta functions δ(t) spaced by the sampling period Ts = 1/fs : va,s (t) = va (t) × IIITs (t)

(1.11)

where va,s (t) is a generalized function and IIITs (t) is the Dirac comb which can be written as IIITs (t) =

∞ 

δ(t − kTs )

(1.12)

k=−∞

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or, using its expansion in a Fourier series, as   ∞ ∞ 
 1  j 2πk 1 t cos 2π kfs t . 1+2 e Ts = IIITs (t) = Ts Ts k=−∞

(1.13)

k=1

Equation (1.11) can be then rewritten as va,s (t) =

 1  1 va (t) cos(2π fs t) + va (t) cos(4πfs t) + . . . . (1.14) va (t) + Ts Ts

The sampling of va at a rate fs corresponds to mixing the RF signal with cosines at frequencies kfs . The IF filter allows only the first-order beat to go through, and blocks other products with higher order harmonics. Figure 1.24 shows the effect of sampling a signal spectrum at a sampling rate fs that is at least twice the signal frequency bandwidth. The sampling creates spectral replica (aliases). The bandwidth of input antialias filter is related with desired signal bandwidth Ba . Compliance with the Nyquist-Shannon rule (fs > 2Ba ) guarantees that aliases are not overlapped, and the original signal can be recovered by the reconstruction low-pass filter. In a radio receiver, the desired signal is in the RF range, usually with a rather high carrier frequency. Applying the above rule to the carrier leads to very high sampling rates. The actual minimum sampling rate is related to the signal bandwidth, not to the carrier frequency. This rule can be applied in a digital receiver to get the frequency translation required for heterodyne structures. For a standard heterodyne (basic structure in Figure 1.6) the RF signal beats with the local oscillator signal fLO to move the input signal spectrum to the IF frequency range. In a digital heterodyne receiver, the frequency translation is performed by sampling. Figure 1.25 shows the effect of direct sampling a RF signal with spectrum just above 3fs and bandwidth Ba . The sampling at fs > 2Ba creates a set of aliases but, since Ba < fs /2, these aliases are not overlapped and no information is lost. In the example of Figure 1.25, the alias around (S − 3fs )

Figure 1.24

Spectrum folding caused by sampling at fs rate. (a) Input signal and sampling pulses; (1) signal spectrum, with bandwidth Ba ; (2) antialiasing filter, and (b) sampled signal spectrum with aliases caused by sampling.

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Figure 1.25

21

Frequency translation by sampling at a fs rate. S is the original signal bandwidth. (a) Input RF signal and antialiasing filter (dotted line), and (b) sampled signal moved to baseband (S − 3fs ), and other beats (gray areas, dotted contour).

corresponding to the baseband contains all information available in the original RF signal, with no spectral overlapping (aliasing error). The sampling process can therefore be seen as a frequency translation, like the one introduced by heterodyne. If the Nyquist rule (with respect to signal bandwidth, not carrier frequency) is fulfilled, the various aliases do not overlap, and one of the aliases (usually the baseband, with lowest frequency) can be isolated by the output reconstruction filter. Digital processing in the IF chain can shape the transfer function and isolate single channels within the IF frequency range. The structure is basically like an analog heterodyne radio, with the beat carried out by the sampling. The ADC sampling rate is related to signal bandwidth, but the exact sampling instant is affected by jitter, a noise in the time domain that moves the actual sampling instant. The time jitter of the sampling circuit causes an amplitude error related with the carrier frequency, which decreases SNR as discussed in Chapter 5.

1.5.2 Subsampling and Folding As seen in Figure 1.26, the appearance of aliases from sampling can be visualized as a folding operation. The spectrum is drawn on a strip of paper, which is folded at fs /2, fs , and integer multiples of fs /2. As folds are overlapped, the signals in each fold are copied (by the sampling operation) to all the other segments. This process is known as spectral folding and shows how a RF signal X (f ) is moved to baseband by sampling. To avoid aliasing, the sampling rate must be higher than twice the signal bandwidth, as discussed in Section 5.1. Spectral folding overlaps several parts of the spectrum; in the example of Figure 1.26 the wanted signal (continuous line) has significant power only in the range [fs , 3fs /2]. Unwanted signals (dotted lines) are folded in the useful band by the sampling operation. All ranges [kfs /, (k + 1)fs /2], with nonnegative

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Figure 1.26

Spectrum folding. Continuous line: signal of interest; dotted lines: out-band signals. (a) Original spectrum before sampling, (b) folding at kfs /2, and (c) final overlap of frequency ranges.

integer k, are folded and overlapped; due to sampling, unwanted signals in various frequency ranges are folded in the same band and cannot be removed. To preserve the wanted signal integrity, the folding width must be larger than the signal bandwidth and other folds must have 0 (or very low) signal power. Therefore, to eliminate or reduce out-of-band noise and interferers, the input signal must be filtered in the analog domain before sampling with BPF having a maximum bandwidth B = fs /2. After the ADC, further filtering and channel separation can be carried out by digital processing. As an example, a sampling frequency of at least 600 MHz is required to avoid aliasing in a signal with a set of 20 channels, with a bandwidth of 15 MHz each, for a total bandwidth equal to 300 MHz. The individual channels can be isolated after the ADC by digital filtering, as discussed in the following. 1.5.3 Sampling Signals with Spurious Components and Noise An RF signal also contains wideband noise and out-of-band components. Sampling the RF without preliminary filtering causes overlapping of the various spectral segments, as discussed before. This is shown in Figure 1.27, where the results discussed in Figure 1.26 are presented on a straight linear axis: out-of-band signals become in-band noise, which cannot be isolated by a reconstruction filter. For correct operation, the RF signal must be filtered before the sampling, as shown in Figure 1.28. The RF BPF keeps only the useful signal components, removing wideband noise and other out-of-band signals. To keep aliases separated, the sampling rate must be higher than twice the filter bandwidth. The original signal translated to baseband can be recovered by the reconstruction filter. Further narrowband filtering (e.g., for channel separation) can be carried out by digital processing of the translated signal, as discussed in the following Section. 1.5.4 Frequency Division Multiplexing Channel Separation In many cases the communication system uses Frequency Division Multiplexing (FDM), and the RF signal includes several channels. Single channels are usually

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Figure 1.27

Effect of sampling an unfiltered RF signal. (a) Spectrum of sampling pulses, with sampling rate fs , (b) input signals, including spurious and noise, and (c) input signals folded by the sampling operation.

Figure 1.28

Sampling a filtered (narrowband) RF signal. (a) Spectrum of sampling pulses, with sampling rate fs ; (b) input signals, including spurious and noise, and (c) input signals folded by the sampling operation.

quite narrow (e.g., 100 kHz), and it is very hard to isolate them at the RF level (such operations require high Q filters). Subsampling based on channel bandwidth (e.g., at 200 kHz or slightly higher) is therefore not feasible. A solution is represented by the double conversion introduced in Section 1.2.3: an RF filter isolates a block of channels in the receiver frequency range (bandwidth BRX in Figure 1.29); this is rather wide, hence relaxes filter requirements. The channel block is sampled at a frequency fs > 2BRX ; this operation moves the signal spectrum of the whole channel set to baseband (Figure 1.29). Channel isolation is achieved by digital processing of baseband signals (corresponding to subsampled RF). 1.5.5 Effect of Sampling Jitter Sampling jitter in the time domain is called aperture jitter (Tj ), and it introduces an amplitude error δvj = Tj SR proportional to the signal Slew Rate (SR). Sampling RF signals with low δvj requires sampling clocks with low jitter. Details of this behavior are discussed in Section 5.5.5 (Sample&Hold circuits). The basic concept is that the ADC sampling rate required for a correct signal processing is

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Figure 1.29

Channel isolation with double conversion. (a) Multichannel FDM RF signal, (b) channel set moved to baseband by the analog mixer with aliased copies caused by sampling, and (c) single channel moved to baseband by the second mixer filtered with digital processing after the ADC.

related to the signal bandwidth, while the time precision of the sampling circuit (i.e., the allowed aperture jitter) is related to the carrier frequency. The RF filter near the antenna must be large enough to keep all useful channels; professional receivers split the RF in several channels and use a filter on each channel to get better SNR. The sampling rate depends on the RF filter bandwidth; lower sampling rates reduce the processing requirements and the power consumption, but they pose severe constraints on the filter because the aliases generated by sampling are closer to the desired signal. Sampling a channel block requires a sample rate higher than the minimum required by a single channel, which means that the large number of samples from the channel block is highly redundant if the goal is to receive a single channel. The system operates with oversampling : this allows the use of wider bandwidth antialias filters, but increases the digital processing requirements. To isolate a single channel the number of samples can be reduced with a decimation process (actually a digital filter) as shown in Figure 1.30. With oversampling and decimation the complexity of antialias filtering is moved from the analog to the digital domain. The specifications of the analog antialias filter before the ADC are relaxed because of the higher sampling rate, and the input filter is partially replaced by the digital post-ADC processing and decimation. The benefit is the reduced complexity of the analog parts (the RF BPF); the cost is an increased complexity and higher power consumption in the digital processing. An example of these techniques is the integrated circuit shown in Figure 1.31 (AD6655, by Analog Devices [9]), which can be used in the receiver section of Global System for Mobile Communications (GSM) cell phones with various standards (TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE). This device includes two receiver chains to allow diversity operation, each chain uses digital I/Q downconversion, decimation (to reduce the number of processed

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Figure 1.30

Effect of sampling and decimation. (a) Sampling rate fs1 , much higher than Nyquist frequency, (b) effects of a high sampling rate on a low bandwidth signal, and (c) signal after decimation (new sampling rate fs2 ).

Figure 1.31

Example of GSM receiver with digital downconversion (AD6655, by Analog Devices [9], used by permission.). A: RF input (analog, differential); B: digital RF ADC; C: I/Q first conversion (with tunable numeric LO); D: first IF I/Q chains, with filters and decimation; E: second conversion - translation to baseband; F: 14-bit output.

samples), and reconstruction (adding I/Q components). The analog input signal is applied in input (A); after sampling and Analog-to-Digital conversion (B), the digital signal is downconverted (C), decimated (D), filtered, translated to RF band (E), and then reconstructed from I/Q components (F). 1.5.6 How Many Bits Are Required? RF signals have a wide dynamic range, from microvolts to volts; this requires many bits of resolution (the usual number of bit ranges from 12 to 16), which leads to high power consumption and higher cost. Another technique is to insert

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Figure 1.32

Digital receiver with gain control before the ADC (typical of GPS receivers). A VGA keeps the signal level within the ADC range.

Figure 1.33

SDR receiver (I/Q heterodyne). (a) LO = RF + IF (the IF chain uses a BPF), and (b) LO = RF, I/Q with ZIF (the IF chain uses a low-pass filter).

a VGA, with gain controlled by the signal amplitude, before the ADC, as shown in Figure 1.32. A key parameter in complex digital processing is the resolution/precision of the computation. To ensure a higher resolution, the ADC must provide a high number of bits containing useful information. The gain is controlled by a feedback from the ADC; as the output approaches full-scale, the gain is reduced. Most GPS receivers use this technique: the ADC has low resolution (e.g., 2 bits) with a VGA placed before the ADC. For local area network (LAN) communications and GSM, the modulations exploit also signal amplitude, and the gain-control loop can interact with demodulation; therefore the receivers need ADCs with higher resolution (e.g., 12 to 16 bits). 1.5.7 Direct Radio Frequency Sampling The block diagram in Figure 1.33(a) shows a direct sampling I/Q receiver, with no mixer (presented as single-channel structure in Figure 1.23(d)). All functions after the RF filter and the LNA are carried out by digital circuits (after the ADC). When the digital processing is carried out by microprocessors or DSPs, these functions are performed via software. This leads to the term software radio. A more accurate definition could be “radio system where almost all the functions are carried out by digital (programmable) circuits.” This definition includes systems which use field-programmable gate arrays (FPGAs) to get high digital processing speed. Since the ADC operates directly on RF signals, image cancellation can be achieved by I/Q digital processing.

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This zero IF technique is used in I/Q structures (Figure 1.33(b)): the RF is moved directly to baseband, and the carrier is shifted to DC. The IF chain now uses low-pass filters, and the problems come from offset and drift, since DC is within useful signal bandwidth. For both structures the sampling rate is related to the bandwidth of the RF filtered signal, not to the RF frequency. In these structures, the RF signals are moved to IF by the sampling operation, and the most critical parameter is the sampling jitter, which causes an amplitude error proportional to the carrier frequency. Another example is presented in Figure 1.17, which shows a commercial GPS receiver [5], where the image rejection is achieved by combining the I/Q IF components.

1.6 Complete Transceiver Architectures The previous sections focus only on receivers; transmitters have similar architectures, with an inverted signal path. The first operation is the direct synthesis of the I/Q baseband components using DACs; these signals usually include the modulation (this block replaces the sequence of carrier generation and modulation). The next step is the frequency shifting and combination of I/Q signals and, finally, an output PA drives the antenna. The first two steps can be merged with direct in-band generation of RF signals with high-speed DACs. An example of transmitter section for an integrated transceiver is shown in Figure 1.22. This device (Maxim MAX2820 [7]) has already been used in the previous section as an example of ZIF receivers. In the transmitter section, the ZIF structure can be recognized because of the use of the low-pass filter in the IF chain. This IC receives modulated I/Q components, which are amplified (F) and filtered (G). These I/Q baseband components are moved to the RF range by a mixer pair (H). The frequency translation signals are generated by a PLL-based synthesizer (B), which provides sine and cosine signals with precise phase shift (as described in Section 4.3). Both receiver and transmitter chains use differential signaling and provide excellent balancing for image cancellation. External baluns (differential to single-ended RF adapters) provide the interface with the unbalanced antennas. With the ZIF structure, IF filters (both in the RX and in the TX) are lowpass filters, and the DC offsets are within useful signal bandwidth, and therefore they must be tightly controlled. For this reason, the device internal operation uses differential signals, both in the receiver and in the transmitter chains. The block diagram for a complete transceiver system, with the ZIF transceiver core (Maxim MAX2820), RF power amplifier (Maxim MAX2242), and the baseband ADCs, DACs, and control circuits is presented in Figure 1.34 (ADCs and DACs are described in Chapter 5).

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Figure 1.34

Complete block diagram of a commercial ZIF transceiver (Maxim MAX2820 [7]), with external PA (MAX2242 [10] ©Maxim Integrated Products. Used by permission.).

Figure 1.35

Block diagram of the transceiver used as a guideline in this book.

Besides the DACs and ADCs in the I/Q RX and TX signal chains, the system uses other auxiliary DACs for gain control in the receive and transmitting chains and for power control of the RF transmitter amplifier. Low-pass antialiasing filters are used before the receiver ADC and after the transmission DACs. The requirements for these filters are discussed in Section 5.1. The contents of this book follow the structure of the transceiver outlined in Figure 1.35 (dual-band cell phone handset): • In/out RF units interfacing with the antenna (LNA and PA) and IF amplifiers (Chapter 2);

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• Mixers and frequency multiplies (Chapter 3); • PLL and synthesizers (Chapter 4); • Analog-to-digital and digital-to-analog interface and converters (Chapter 5).

References [1]

National Academies of Sciences et al., Handbook of Frequency Allocationsand Spectrum Protection for Scientific Uses, Second Edition, National Academies Press, 2015.

[2]

Dimopoulos, H. G., Analog Electronic Filters: Theory, Design and Synthesis, Dordrecht, Netherlands: Springer, 2011.

[3] Taylor, F., and A. Williams, Electronic Filter Design Handbook, Fourth Edition, McGraw-Hill Education, 2006. [4]

Morgan, D.P., Surface-Wave Devices for Signal Processing. Studies in Electrical and Electronic Engineering, Elsevier, 1985.

[5]

Maxim MAX2745 Single-Chip Global Positioning System Receiver Front-End, rev. 0. https://www.maximintegrated.com/products/MAX2745.

[6]

Meng, C., et al. “2.4/5.7-GHz CMOS Dual-Band Low-IF Architecture Using Weaver– Hartley Image-Rejection Techniques,” IEEE Transactions on Microwave Theory and Techniques, Vol. 57, No. 3, March 2009, pp. 552–561.

[7]

Maxim MAX2820 2.4GHz 802.11b Zero-IF Transceivers, www.maximintegrated.com/products/MAX2820.

[8]

Bracewell R. N., and R. Bracewell, The Fourier Transform and Its Applications, New York: McGraw Hill, 2000.

[9]

AD6655 IF Diversity Receiver, rev. B. https://www.analog.com/media/en/technicaldocumentation/data-sheets/AD6655.pdf.

[10]

Maxim MAX2242 2.4 GHz to 2.5 GHz Linear Power Amplifier, rev. 0. https:// www.maximintegrated.com/products/MAX2242.

rev.

5.

https://

Selected Bibliography Antique Radios, the Collectors Resource. https://antiqueradios.com/. Brannon, B., “Some Recent Developments in the Art of Receiver Technology: A Selected History on Receiver Innovations over the Last 100 Years,” Analog Dialogue, Vol. 52, No. 8, August 2018. https://www.analog.com/en/analog-dialogue/articles/a-selected-historyonreceiver-innovations-over-the-last-100-years.html. Del Corso, D., Elettronica per Telecomunicazioni, CD-ROM, Collana di istruzione scientifica, Serie di elettronica, McGraw-Hill Companies, 2002. DeMartino, C., “Focus on Mixers,” in Focus on Mixers (ed. by Microwaveand RF Library), 2016, https://www.electronicdesign.com/test-measurement/microwaves-and-rf-libraryfocusmixers-e-book-compendium.

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Foster, D. E., and S. W. Seeley. “Automatic Tuning, Simplified Circuits, and Design Practice,” Proceedings of the Institute of Radio Engineers, Vol. 25, No. 3, March1937, pp. 289–313. DOI: 10.1109/JRPROC.1937.228940. Kearney, F., and D. Frizelle, “Complex RF Mixers, Zero-IF Architecture, and Advanced Algorithms: The Black Magic in Next-Generation SDR Transceivers,” Analog Dialogue, Vol. 51, No. 2, February 2017, https://www.analog.com/media/en/analog-dialogue/volume-51/number1/articles/complex-mixers-zif-architecture-advancedalgorithms-black-magic-nextgeneration-sdr-transceivers.pdf. Love, J., RF Front-End: World Class Designs, World Class Designs, Elsevier Science, 2009. (RF frontend design from antenna and filter design fundamentals to IF channel, with a strong pragmatic emphasis. Links between theory and applications. Pace, P. E., Advanced Techniques for Digital Receivers, Norwood, MA: Artech House, 2000, Chapters 2, 3, 5, 6. van der Puije, P. D., Telecommunication Circuit Design, Wiley, 2002, Ch. 2: AM radio communications, Chapters 3, 5. Sayre, C., Complete Wireless Design, Third Edition, McGraw-Hill Education, 2015. (General reference manual, good for understanding radio architectures and complete radio system.) Tomasi, W., Advanced Electronic Communications Systems, Pearson/Prentice Hall, 2004, Chapters 1, 4.

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2 Transistor RF Amplifiers Amplifiers are widely used in any electronic system; their general goal is to allow the designer to increase the power of an analog signal, modifying its voltage, or current, or both. Depending on the application-related requirements, it is possible to find four basic types of amplifiers, summarized in Table 2.1. A key parameter for the specification of amplifiers is the operating frequency range, which can go from DC (typical of operational amplifiers) up to several gigahertz. The amplifier circuits described in this chapter are designed to work in high-frequency systems (from RF up to millimeter-waves). DC and lowfrequency amplifiers, usually based on operational amplifiers, are briefly described in Section 5.5.2. The main parameter of an amplifier is its gain; however, other parameters are needed to describe in detail the behavior of the specific amplifier in the targeted application. These include output power, noise, linearity, efficiency, dynamic range, and so forth. All these parameters are related to the type of active device and depend on the actual circuit configuration. This section describes the basic circuits adopted for the design of amplifiers based on bipolar junction transistors (BJTs) and field-effect transistors (FETs) (Figure 2.1) and starts from the analysis of the bias network, continues with the small-signal linear analysis, and finally moves to a detailed description, including nonlinear effects related to the semiconductor junctions. The nonlinearity leads to the generation of harmonics and as a consequence to gain compression. In this framework, the BJT is used to introduce the reader to nonlinear analysis because it can be described with a unique, rather simple equation. FET devices exhibit similar behavior, but the mathematical description when moving to the nonlinear regime is more complex because the model depends on the signal amplitude. The effects of nonlinearity for BJT and FET can be somehow mitigated applying specific circuit-oriented solutions like the feedback or specific complementary 31

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Table 2.1 Amplifier Types

Figure 2.1

Input

Output

Voltage v i Voltage v i Current i i Current i i

Voltage vo Current io Current io Voltage vo

Amplifier Type Voltage Transconductance Current Transresistance

Constitutive Relation vo = Av v i io = gm v i io = Ai i i vo = rm i i

Symbols of bipolar transistors and MOSFETs with the adopted convention of currents and voltages. (a) npn BJT, (b) pnp BJT, (c) n-channel (enhancement) MOSFET, and (d) p-channel (depletion) MOSFET.

nonlinearity. A more detailed analysis of those approach can be found for example in [13, 20, 24].

2.1 Transistor Modeling Transistors are complex structures with a physical behavior that is dependent on a large number of parameters and variables. A transistor model is a representation of the device behavior in a form that is convenient for analysis, simulation, or design. Transistor models can be classified into two main categories: physics-based and behavioral. A physics-based model starts from the equations governing the transport and diffusion of charges (electrons and holes) at nanoscale to obtain equations that describe the interaction between the transistor’s current, voltage, and temperature. This type of model provides the best accuracy and tends to describe each aspect of the transistor behavior. However, it is rarely used in circuit design due to its complexity, computational burden, and disclosure of intellectual property (the transistor manufacturer must disclose detailed information on the transistor geometry and material structure). On the other hand, behavioral models describe transistors from an external observer point of view by modeling the macroscopic interaction between the variables of interest without any requirement for understanding the physics behind that behavior. They have advantages in comparison with physics-based models in terms of simplicity, therefore becoming more useful for circuit analysis

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33

and design and simulation speed. However, they lack accuracy and completeness. In fact, a behavioral model will only be valid in the domain of variables on which it has been extracted. For example, a behavioral model created for a transistor by observing the response to drain current between 0 and 100 mA will potentially provide incorrect answers if used at 100 mA. However, most of circuit models used in amplifier design are in reality a mix between the physical and behavioral approaches. In fact, they normally use topology and general definitions that are linked to the physics of the device, while, on the other hand, the assignment of the circuit component values (the model extraction) is normally done with a behavioral approach. This means testing and observing voltage, current, and sometimes temperature at the external nodes of the transistor. The other classification of models is in terms of their implementation. An analytical model will use equations to describe the relations between variables. A circuit model is very similar, with the difference that the equations are embedded in circuit elements and it is more practical to be used in a computer-aided engineering (CAE) tool. A bit different is a look-up-table model, where instead of an equation describing the relation between variables there is a large table that is filled during model extraction (instead of filling parameters) and then recalled during simulation. Interpolation is normally used to return values that fall within the discrete values of the table. A dynamic nonlinear model is needed to design power amplifiers, oscillators, and mixers, as well as to determine the DC bias point of the transistor in a circuit. However, for other types of design, small-signal models are sufficient. Small-signal models are used to model the transistor around a quiescent bias point and are widely adopted to design gain and low-noise amplifiers. In practice, they correspond to the linearization of the nonlinear dynamic model around the quiescent point. It is important to note that nonlinear models are not biasdependent, since the dependency on the bias is intrinsic in their equations. In other words, they can be used when changing the bias settings. On the other hand, small-signal models are bias-dependent, since they describe the circuit only around a single quiescent point; therefore, a different model (or more commonly, same model structure with different parameters) must be used at each bias point. The models discussed in this section are circuit models that at times embed complex equations within some circuit elements. Their topology is physics-based, while the model extraction is normally behavioral. In many cases, the simplified proposed model resemble what would be the ideal behavior of a transistor.

2.2 Small-Signal Amplifiers A large part of the amplifiers adopted in modern communication systems are small-signal amplifiers. For these applications, BJTs are generally required to work in their forward active region, while the FETs should operate in saturation.

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Figure 2.2

Example of linearization of the equation relating the drain current to the gate-source voltage. If the variation of voltage around the quiescent point Q is sufficiently small, then the circuit analysis can be carried out using a linear approximation of the real characteristics.

The analysis of these amplifiers can use, as a first approximation, models obtained from proper linearization of the device constitutive equations around the bias point, as shown in Figure 2.2; the superposition principle can be used to separate the study of the bias point and the small-signal response. The accuracy of the small-signal models reduces as the signal amplitude increases. This section includes a review of bias technique for single BJT and FET amplifiers; small-signal linear models are then introduced to evaluate the amplifier transfer function based on transconductance (gm ) or hybrid parameters (hxx ). In more details, the analysis sequence is: 1. Approximate the transistors with their steady state models; 2. Calculate the bias point, verifying that the correct models were used; 3. Approximate the transistors with their small-signal models, using smallsignal parameters for the calculated bias point; 4. Compute the frequency response. 2.2.1 Amplifier Bias Network A key task of an amplifier bias circuit is to make the operating point as stable and independent as possible from device, circuit tolerances, and ambient parameters. For example, the BJT current gain β can vary over a wide range for the same nominal device due to fabrication tolerances, temperature, aging of the component, bias point itself, and so forth. Moreover, the quiescent point is affected by variation of resistors and voltage supplies present in the bias circuit. In order to evaluate the dependence of a parameter y on another parameter x, it is possible to calculate the relative sensitivity of y with respect to x, defined as y

Sx = y

dy x dx y

(2.1) y

The value of Sx indicates how a change of x propagates on y (e.g., if Sx = −0.5 y and x varies by δx = +10%, then y varies by δy = Sx δx = −5%). Obviously, y if Sx = 0 then x and y are independent parameters.

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2.2.1.1 BJT Bias

A simple model of a BJT amplifier operating in forward active region, suitable for an approximated analytical calculation of the bias point, is shown in Figure 2.3. The npn BJT is modeled by a constant voltage source to describe the forwardbiased base-emitter (BE) junction and by a current-controlled current source relating the collector current IC to the base current IB through the approximated relation IC = βIB . An a posteriori check of the results is required in order to confirm that the transistor operates in the forward active region [20]. A similar approach can be used to describe pnp bipolar transistors (Figure 2.3(b)). Figure 2.4(a) presents a simple bias circuit called a fixed base bias circuit. With this configuration, IC can be written as IC = βIB = β

VCC − VBE RB

(2.2)

with VCC voltage supply and VBE voltage of the directly polarized emitter-base junction. The relative sensitivity of IC with respect to β is SβIC =

dIC β =1 dβ IC

(2.3)

which indicates that a variation of the β parameter causes the same relative variation of IC .

Figure 2.3

DC model for npn (a) and pnp (b) bipolar transistor, valid when the bipolar transistor operates in the forward active region.

Figure 2.4

Bias networks for a npn BJT. (a) Fixed base bias, (b) collector feedback, (c) emitter resistor feedback, and (d) four-resistor bias network.

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This behavior can be improved adding a collector feedback, as shown in Figure 2.4(b). The collector current is now IC = β

VCC − VBE RF − βRC

(2.4)

and its relative sensitivity with respect to β is SβIC = −

RF RF + βRC

(2.5)

if β is large, then SβIC → 0, as desired. Unfortunately, the relative sensitivity with respect to the temperature-dependent junction voltage VBE is not null: SVICBE = −

VBE . VCC − VBE

(2.6)

Moreover, the bias point depends on RC : this resistor can represent, for certain applications, the external load of the amplifier. This dependence can be overcome with the bias circuit in Figure 2.4(c), where the collector current is IC = β

VCC − VBE RB − (β + 1)RE

(2.7)

and does not depends on RC but only on the emitter resistor RE . Finally, in the circuit shown in Figure 2.4(d), the BJT is polarized with the four resistors bias network or voltage divider bias network. This configuration provides stable IC versus current gain thanks to emitter feedback; the base voltage is mainly determined by the two resistances RB1 and RB2 , reducing the temperature dependence; finally, IC does not depend on RC : IC = β

Veq − VBE , RBB + (β + 1)RE

Veq = VCC

RB2 , RB1 + RB2

RBB = RB1  RB2 . (2.8)

The collector-emitter (CE) voltage is
VCE = VCC − IC

β +1 RC + RE β

 (2.9)

and must be larger than VCE,sat to ensure that the BJT operates in forward active mode. For silicon transistors, VCE,sat ≈ 0.2 V. The previous analysis can be simplified assuming large current gain (β → ∞), and therefore IB = 0 and IC  IE . For the circuit shown in Figure 2.4(d), the voltage of the base node VBB equals Veq and the collector current is fixed by

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the BE mesh, while VCE is set by the CE mesh: IC ≈ IE ≈

VBB − VBE RE

VCE ≈ VCC − IC (RC + RE ) ;

(2.10) (2.11)

From a designer point of view, an assigned value of IC can be obtained with different combinations of RB1 and RB2 . Large values of VBB provide good stability of IC versus variations of VBE at the expenses of a reduced output dynamic range. On the other hand, small values of RBB provide good stability toward variations of β but results in an higher power consumption of the VBB voltage divider. 2.2.1.2 MOSFET Bias

For MOSFET amplifiers, the quiescent point is identified by the drain current ID and the drain-source (DS) voltage VDS . A common model for the analysis of the bias point is presented in Figure 2.5(a), where the gate current ID is supposed to be zero thanks to the oxide layer blocking any current flow, which forces the source current IS to equal ID . A quadratic law relates then ID to the gate-source (GS) voltage VGS of the saturated MOSFET: 1 ID = k (VGS − VTH )2 . (2.12) 2 In (2.12), VTH is the threshold voltage and k = µCox W /L depends on the carriers mobility µ, the gate oxide capacitance pr unit area Cox , the gate width W , and the gate length L. A proper choice and design of the bias network reduces the sensitivity of the quiescent point on these parameters. After the calculations, it is necessary to verify that ID > 0, VGS > VTH , and VDS > VGS − VTH to ensure that the device operates in saturation as expected. Also for the MOSFET case, the four-resistor network shown in Figure 2.5(b) represents a valid circuital solution. In this case, VGG = VDD

Figure 2.5

RG2 RG1 + RG2

(2.13)

(a) DC model for an n-channel enhancement MOSFET, and (b) four resistors bias network.

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and the source voltage is VSS = RS ID , thus k (VGG − VTH − RS ID )2 2 and ID is root of the second order equation   kRS2 ID2 − 2ID 1 + kRD (VDD − VTH ) + (VDD − VTH )2 = 0 ID =

(2.14)

(2.15)

corresponding to VGS > VTH . To verify that the MOSFET operates in saturation, the inequalities  VGS > VTH (2.16) VDS = VDD − ID (RD + RS ) ≥ VGS − VTH must be satisfied. 2.2.1.3 MESFET Bias

Compared to BJTs and MOSFETs, metal-semiconductor field-effect transistors (MESFETs) have a more complex DC current versus voltage relation, as shown in Figure 2.6 where a depletion mode MESFET is considered. Therefore, a graphical approach to identify the quiescent bias point is often used. First, the output current/voltage pair (ID , VDS ) must be identified according to the desired specifications of the amplifier (for example, maximum gain, maximum power, minimum noise), shown in Figure 2.6(b). Then, the input voltage VGS is identified by observing the transfer characteristic as in Figure 2.6(c). Note that, a negative VGS is needed. Several solutions are available for biasing MESFET. Figure 2.7(a) shows a solution relying on a choke inductor on the drain to provide the bias voltage. This method avoids DC power dissipation on the drain bias elements, and it is most often adopted in power amplifiers where energy conservation is crucial. A large resistor RG can be used on the gate since no DC current is absorbed by the gate; an inductor can also be used as well on the gate. In this configuration, the bias setting is  VGG = VGS (2.17) VDD = VDS .

Figure 2.6

(a) General DC model for depletion-mode MESFET, (b) output DC characteristics, and (c) transfer characteristic.

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Figure 2.7

Bias circuits for a MESFET. (a) Inductor based, (b) resistor based, and (c) self-biasing.

The circuit of Figure 2.7(b) uses a resistor RD on the drain, a solution used in low-noise amplifiers where the resistor helps stabilizing the circuit. In this configuration, the bias setting is  VGG = VGS (2.18) VDD = VDS + RD ID . Both solutions (a) and (b) require a negative voltage for the gate. To avoid this, a self-biasing circuit can be used, as shown in Figure 2.7(c). The gate is grounded at DC through a large resistor RG , while the source potential is lifted by using a resistor RS whose value is chosen as RG = −VGS /ID . The bias setting is then VDD = VDS + (RD + RS ) ID .

(2.19)

2.2.2 Small-Signal Models 2.2.2.1 BJT Small-Signal Model

The hybrid-π low-frequency model for the small-signal analysis of a bipolar transistor is called the Giacoletto model and is presented in Figure 2.8(a). The transconductance gm describes the variation of collector current with respect to a variation of the BE voltage, around the bias point:   diC  dIS e vBE /VT  IC gm = = = (2.20)   dvBE Q dvBE VT Q with VT thermal voltage (25.9 mV at 25 ◦ C). The admittance gπ = 1/rπ describes the variation of base current with respect to a variation of vBE , around the bias point:  diB  IC gm gπ = = = (2.21) dvBE Q β0 VT β0 with β0 small-signal current gain. In general, β0  = β due to the dependence of the transistor current gain on the collector current. This model neglects high-frequency effects and can be used for input signal frequencies up to a few hundreds of kilohertz. These simplified models are not

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Figure 2.8

Small-signal models for (a) BJT, and (b) MOSFET.

accurate enough to design an optimized amplifier; however, they are widely used to perform circuit analysis and understand the theoretical limitations of amplifiers. 2.2.2.2 MOSFET Small-Signal Model

A model for the small-signal analysis of a MOSFET is presented in Figure 2.8(b). The main parameter appearing in the model is the amplifier transconductance gm , defined as the variation of the drain current with respect to a variation of the GS voltage, around the bias point:   diD  W 2ID gm = = k (VGS − VTH ) = = 2k ID . (2.22)  dvGS Q VGS − VTH L 2.2.2.3 MESFET Small-Signal Model

MESFET can be modeled as in Figure 2.9(a) by splitting the Schottky junction of the gate into two diodes, one toward the drain and one toward the source. In the active region both junctions will be in reverse bias, and their effect is modeled by a strong nonlinear capacitance, as shown in Figure 2.9(b). Some intrinsic loss is normally also included at the input with the resistance RI , but the control voltage v˜ (t) is the one across the input capacitance only. The output capacitance is often considered linear. The gate-source capacitance is the dominant one, with the drain-source capacitance around five times lower, and the gate-drain capacitance is one order of magnitude lower. The nonlinear model can be linearized leading to the schematic shown in Figure 2.10, where the capacitances are linear and the current source is split into a constant transconductance and an output resistance to represent the dependence on output voltage. 2.2.3 High-Frequency Transistor Models High-frequency transistors models have an extra level of complexity compared to low-frequency models, since they must be able to accurately describe the transistor in nonlinear dynamic operation also when the dimensions of the transistor are not negligible compared to the wavelength. In this condition, distributed or parasitic effects manifest themselves altering our observation of the transistor behavior.

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Figure 2.9

41

Nonlinear model for MESFET. General model (a) and dynamic model in the saturation region (b).

Figure 2.10

Linearized MESFET small-signal model.

Figure 2.11

Separation between intrinsic nonlinear model (nonlinear core) and extrinsic model (parasitics) for bipolar (a) or field-effect (b) transistors.

The most common approach is then to separate conceptually the transistor in two parts, as shown in Figure 2.11; a nonlinear core that describes all the driftdiffusion phenomena within the transistor, and a linear model of the parasitic or extrinsic components that describes the effects of interconnections, pads, and access structures. At the interface between the two parts of the model there are the intrinsic nodes that are virtual nodes of the transistor core. The distinction between core and parasitics is also maintained when generating linearized or small-signal models. In practice, the parasitic part should

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Figure 2.12

Giacoletto model for bipolar transistors including parasitic elements.

be identical since it is linear by definition, while the intrinsic part is linearized and transformed into an equivalent model. For high-frequency design and analysis, the capacitive effects of the pn junctions must be included, as shown in Figure 2.12(b). The BE capacitance is called Cπ , while the base-collector (BC) capacitance is Cµ . Extrinsic parameters are used to model the parasitic effects of the access structures connecting the pads of the transistors to the transistor active region. In general, these are complex structures that can be modeled by data obtained from electromagnetic simulations. However, a more common approach relies on lumped elements modeling using series resistance and inductance to model lengths of wire or metal trace (for example, a gate finger) and shunt conductance and capacitance to model the cross coupling between traces and the coupling to ground. Also, by parametrising these quantities as functions of length, width, and distance of traces it becomes quite easy to scale the parasitic parameters as a function of the transistor size. For bipolar transistors, Figure 2.12 shows a Giacoletto model including the series parasitics on base, collector, and emitter, and the parasitic capacitance at the output. Figure 2.13 shows a small-signal model of a MESFET transistor including the series parasitics on gate, drain, and source. The output current is modeled with a complex valued transconductance gm that is the linearization of the function around the bias point. It includes the module of the transconductance and a delay parameter that account for the transition time in the channel. The output conductance is used to model the dependence on the output voltage. A MOSFET model is very similar, but it might include parasitics between the nodes and the body for generality. If the body is set at the same potential of the source, these elements might collapse with other parasitic elements. 2.2.4 Single-Stage Configurations Single-stage BJT amplifiers are typically designed in the common emitter (C-E), common collector (C-C), or common base (C-B) configuration, each one presenting

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Figure 2.13

Small-signal model for field-effect transistors including parasitic elements.

Figure 2.14

Single-stage BJT configurations. (a) Common emitter with bypass capacitance CE connected to the emitter, (b) common emitter with splitting of the emitter resistance, (c) common collector, and (d) common base.

particular advantages and drawbacks. These typical configurations are presented in Figure 2.14, while their small-signal properties are summarized in Table 2.2 in terms of signal amplification and input and output resistance. A similar classification is possible for MOSFET-based single-stage amplifiers; the common drain (C-D), common source (C-S), and common gate (C-G) configurations are shown in Figure 2.15 and their small-signal properties are listed in Table 2.3. The high-frequency (HF) response of these single-stage configurations depends on L and C parasitics. The effects of load capacitance can be reduced

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Table 2.2 Approximated Characteristics of the Single BJT Amplifier Stages Calculated in Passband Assuming Large Current Gain (RB = RB1  RB2 ; rb,eq = rπ (1 + gm RE )) C-E Voltage gain Current gain at BJT terminals Input resistance Ri Output resistance Ro

Figure 2.15

−gm RC −β0

C-E+RE RC RE1 −β0

→−

RB  rπ

RB  rb,eq

RC

RC

C-C

C-B

→1

gm RC

1 + β0

→1

RB  rb,eq

≈ RE +

1 gm

RC

≈ RE +

1 gm

Single-stage MOSFET configurations. (a) Common source with bypass capacitance CS connected to the source, (b) common source with splitting of the source resistance, (c) common drain, and (d) common gate.

with an isolation stage (C-C or C-D). printed circuit board (PCB) parasitic L and C can be controlled with proper technology choices, such as a careful PCB layout design, and the use of surface-mounted device (SMD) devices. In common circuits the key active device parasitic element is the BC capacitance (CBC ) because it is multiplied by the Miller effect. To counteract its impact at high frequency, specific design solutions can be adopted, both in terms of proper technologies

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Table 2.3 Approximated Characteristics of the Single MOSFET Amplifier Stages Calculated in Passband Assuming Large Current Gain (RG = RG1  RG2 ) C-S −gm RD

Voltage gain

C-S+RS

C-D

C-G

RD RS1

→1

gm RD →1 1 gm

→−

Current gain at FET terminals

−gm

−gm

1 + gm

Input resistance i

→∞

→∞

→∞

RD

RD

Output resistance Ro

≈ RS +

1 gm

RD

(HF devices with low CBC (GaAs, SiGe, etc.) or at topological level by suitable circuit solutions (C-B, cascode). 2.2.4.1 Common Emitter (Source) Configuration

The C-E and C-S basic circuits are shown in Figures 2.14(a,b) and 2.15(a,b), respectively. The parasitic Cµ capacitance is connected between two nodes with voltage gain −Av . The current iµ flowing in Cµ is iµ = jωCµ (vb − vc )

(2.23)

= jωCµ (vb + Av )

(2.24)

= jωCµ (Av + 1)vB

(2.25)

Due to the gain from base to collector, the admittance is multiplied by the Miller effect by a factor (Av + 1). The actual equivalent capacitance at base node is Cactual = CBC (Av + 1).

(2.26)

This capacitance limits the high-frequency response, which can be improved using circuit configurations that do not cause the Miller effect, with low voltage gain. 2.2.4.2 Common Collector (Drain) Configuration

The C-C and C-D basic circuits are shown in Figures 2.14(c) and 2.15(c), respectively. They key characteristics are • • • •

High input impedance Zi ; Low output impedance Zo ; No Miller effect (because the voltage gain is low: Av ≈ 1); Possible high current gain.

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The C-C/C-D circuit is mainly used for load separation: it can drive a low Zo load providing high input impedance Zi . 2.2.4.3 Common Base (Gate) Configuration

The C-B and C-G basic circuits are shown in Figures 2.14(d) and 2.15(d), respectively. They key characteristics are • Low input impedance Zi ; • High output impedance Zo ; • CBC connected to ground, therefore no capacitance increase for Miller effect; • Low current gain Ai ≈ 1; • Possible high voltage gain Av ≈ gm RC . The C-B/C-G circuit is mainly used for RF input stages; the low input impedance provides good adaptation to antennas. 2.2.4.4 Cascode Amplifier

Some specific circuit configurations allow to improve the frequency response of an amplifier. The cascode amplifier uses a C-E stage directly coupled to a C-B. The effects of the parasitic CBC are reduced because the C-E stage has low voltage gain (due to the low load impedance), and in the C-B stage this capacitance is from collector to ground, so it is not increased by the Miller effect. In this configuration the current gain is provided by the lower device while the top transistor provides the voltage gain. The overall result is a higher gain at high frequency. An example of a cascode circuit is shown in Figure 2.16. This configuration is used also in input stages of operational amplifiers, with several variations, such as using pnp-npn pairs (folded cascode), to allow operation with low supply voltages. Figure 2.16 shows the basic circuit without bias network. The transistor Q1 is used in a C-E stage with low impedance load on the collector (Zc is the impedance seen on the emitter of transistor Q2). Therefore, the stage Q1 provides low voltage gain Av1 , but good current gain Ai1 . The low VCE brings a low Miller effect. The transistor Q2 is used in a C-B stage with good voltage gain and no Miller effect. 2.2.5 Analysis of a Common Emitter Amplifier Figure 2.17(a) presents a common emitter amplifier with four-resistor bias networks and capacitors used to shape the frequency response of the amplifier. In a properly designed circuit, the capacitors CS and CL introduce two zeros in DC, decoupling the bias network from the signal source (represented by voltage source VS and the resistance RS of its Thévenin equivalent) and the load RL .

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47

Figure 2.16

Example of a cascode amplifier (bias network not shown). Q1: C-E stage. Q2: C-B stage.

Figure 2.17

(a) Exemplary C-E amplifier with bandpass frequency response, (b) circuit for the determination of the bias point, (c) circuit for the small-signal analysis, and (d) circuit in passband, with capacitors replaced by short circuits or open circuits.

The collector capacitor CC introduces a zero at infinite frequency and a pole at high frequency, introducing an upper limit for the amplifier passband. The bypass capacitance CE allows to obtain a stable bias point (since the emitter resistance in DC is RE1 + RE2 ); in passband, where it can be approximated as a short circuit, it bypasses RE2 , reducing the emitter resistance and increasing the

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voltage gain of the amplifier. In this scenario, CS , CL , and CE behave in band as short circuits, while CC can be approximated with an open circuit. The model for the analysis of the bias point is presented in Figure 2.17(b): all the decoupling capacitors are replaced by open circuits, signal generator and load are disconnected from the bias network, and the BJT is described by the bias model presented in Figure 2.3(a) with the base resistive network replaced B2 by its Thévenin equivalent (VBB = VCC RB1R+R , RB = RB1  RB2 ). From the B2 base-emitter mesh it is possible to obtain the base current as IB =

VBB − VBE , RB + (1 + β0 ) (RE1 + RE2 )

(2.27)

while the C-E voltage is VCE = VCC − RC βIB − (RE1 + RE2 ) (β + 1) IB .

(2.28)

The circuit for the analysis of the small-signal response of the amplifier is presented in Figure 2.17(c); the resistance rπ is given by IC /(βF VT ). Since the analysis now focuses on signal variations, the DC bias voltage VCC can be considered zero for the AC signal. The upper cutoff frequency fH is fH =

1 , 2π CC RC  RL

(2.29)

being RC  RL the equivalent resistance seen by CC . In order to determine the lower cutoff frequency fL of the amplifier passband, it is possible to use the short-circuit time constant method [20]: fL can be estimated as  1 fL = (2.30) sc 2π R n Cn n with Rnsc resistance seen by capacitor n when the other capacitors closing below the passband are replaced by short circuits. Since CC intervenes at high frequency, the summation must be carried out calculating the resistances seen by CS , CE , and CL : RCscS = RS + RB  (rπ + RE1 (1 + β0 )) 
rπ + RB1  RB2  RS sc RCE = RE2  RE1 + 1 + β0

(2.31)

RCscL = RL

(2.33)

(2.32)

In-band, the circuit can be simplified replacing CS , CE , and CL with short circuits and CC with an open circuit, as shown in Figure 2.17(d). The voltage

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gain Av is Av =

vO 1 =− β0 RC  RL . vI rπ + RE1 (1 + β0 )

(2.34)

For large values of the current gain, (2.34) reduces to Av = −

RC  RL , RE1

(2.35)

The gain of the C-E configuration can be increased reducing the RE1 but for RE1 → 0 the gain becomes more dependent on the operating point: lim Av = −gm RC  RL = −

RE →0

IC RC  RL . VT

(2.36)

The small-signal input resistance is Ri = RB  (rπ + RE1 (1 + β0 )) while the output resistance Ro is just RC ; finally, the current gain Ai is Ai =

il RB RC =− β0 . is RB + Ri RC + RL

(2.37)

With the following components values: RS = 50 , RB1 = 120 k, RB2 = 82 k, RE1 = 330 , RE2 = 12 k, RC = 12 k, RL = 10 k, CS = 4.7 µF, CC = 1 nF, CL = 4.7 µF, CE = 1 µF, VBE = 0.7 V, β = β0 = 200 and with VDD = 12 V, then the bias point is IC = 330 µA and VCE = 3.95 V. Since IC > 0 and VCE > 0.2 V, the hypothesis on the forward active region operation is confirmed. The value of the transconductance gm is ≈15.75 mS. The voltage gain L is AV ≈ 22.4 dB, close to the asymptotic value AV = − RCRR = 24.4 dB. The E1 input resistance Ri ≈ 30.6 k. Finally, the passband extends from fL ≈ 404 Hz up to fH ≈ 29 kHz. Manual calculation can be verified using with SPICE circuital simulations [25], using, for example, LTSpice [3]; in order to reproduce the numerical results, it is necessary to re-create in the netlist the circuits presented in Figures 2.17(b) and (c). Examples with the more realistic BJT models available in SPICE are presented in Section 2.2.7. The current-controlled current source can be inserted using an F component, which generates a current proportional to the current flowing in a voltage source, the proportionality factor being in this case the BJT current gain. The .op analysis of the circuit in Figure 2.18(a) confirms the correctness of the manual calculation. The SPICE schematic for small-signal analysis is presented in Figure 2.18(b). In this case, a null voltage generator V0 is placed in series with the resistor rπ to allow the F component in the C-E branch to generate a current proportional the base current. The voltage gain, calculated with the .ac analysis, is shown in Figure 2.18(c). The in-band amplification is AV ≈ 13.3 (22.3 dB); the lower cutoff frequency is fL ≈ 390 Hz while the upper cutoff frequency is fH ≈ 30 kHz.

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Figure 2.18

LTSpice simulations of the C-E amplifier shown in Figure 2.17. (a) Bias point calculation, (b) small-signal circuit, and (c) frequency response of the voltage gain. The netlists for the schematics in a,b are reported in Listings 2.1 and 2.2, respectively.

2.2.6 Nonlinearity and Distortion The key effect of nonlinearity is distortion, which in turn means generation of harmonics, intermodulation, and gain changes related to signal amplitude. The amount of harmonics depends on signal level; a parameter that specifies this behavior is the intercept point (IP). This section focuses on class A/B/C narrowband configurations using BJT circuits. The analysis presented here focuses on BJT because for this kind of device a unified mathematical model that describes the junction behavior across a wide range of operating conditions is available. FET circuits can be analyzed with the same technique, but the models for FET devices are more complex.

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Figure 2.19

Class A BJT band-pass amplifier (a) and the corresponding simplified version (b).

2.2.6.1 Large-Signal BJT Model

The complete circuit for a BJT class A amplifier in band-pass configuration is shown in Figure 2.19(a). A simplified version, which moves all the bias control elements in a single current source IE is shown in Figure 2.19(b). This configuration works for class A, B, and C amplifiers; the same model can be used for other configurations, such as differential amplifier, C-B, C-C. In the following analysis, the emitter capacitor CE is considered a short circuit in-band. In a real BJT, the collector current iC presents a logarithmic dependence with respect to vBE [20]. In Figure 2.19(b), the input signal is vi (t) = Vi cos ωt; it is convenient to define the normalized input signal amplitude x = Vi /VT . The total actual voltage on the BE junction can be written as vBE = vi + vE and the collector current is defined by the junction equation: vBE

iC ≈ iE = IS e VT .

(2.38)

Assuming in input a purely sinusoidal signal, VE

iC = IS e VT e x cos ωi t

(2.39)

the term e x cos ωi t can be expanded in Fourier series as e x cos ωi t = I0 (x) + 2

∞ 

In (x) cos nωi t

(2.40)

n=1

where the In are modified Bessel functions of first kind, order n. The expression of the collector current with nonlinear junction model results in

∞ VE  iC = IS e VT I0 (x) + 2I1 (x) cos ωi t + 2 In (x) cos nωi t (2.41) n=2

and it includes 1. A DC term proportional to I0 (x);

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Figure 2.20

Harmonic amplitude versus input signal amplitude. In,0 = In (x )/I0 (x ). Table 2.4 Collector Current Components Calculated with MATLAB® Function Besseli x 0.01 0.05 0.10 0.50 1.00 2.00 3.00 5.00 7.00 10.00 15.00 20.00

I1 (x ) I0 (x )

2

I2 (x ) I0 (x )

2

I3 (x ) I0 (x )

I2 (x ) I1 (x )

0.010 0.050 0.100 0.485 0.893 1.396 1.620 1.787 1.851 1.897 1.932 1.949

0.000 0.001 0.003 0.060 0.214 0.605 0.920 1.285 1.471 1.621 1.742 1.805

0.000 0.000 0.000 0.005 0.035 0.187 0.393 0.759 1.010 1.249 1.468 1.588

0.003 0.016 0.025 0.124 0.240 0.433 0.568 0.719 0.795 0.854 0.902 0.926

2

2. A contribution at the signal frequency, with an amplitude-dependent gain proportional to I1 (x); 3. Harmonics, created by the nonlinearity (n = 2, 3, . . . harmonics). If x > 0, it is possible to collect the term I0 (x) in (2.41), obtaining

∞ VE  (x) I n iC = IS e VT I0 (x) 1 + cos nωi t ; 2 I0 (x)

(2.42)

n−1

an overall view of the harmonic amplitude versus input signal amplitude is reported in Figure 2.20 while numerical results are listed in Table 2.4. The DC component IC of the collector current is IC = IS e

VE (x) VT

I0 (x).

(2.43)

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The current IC is defined by the emitter bias generator, and cannot be modified by the input signal. The DC voltage at the emitter changes with signal amplitude x: VE (x) = VT log

IC . IS I0 (x)

(2.44)

This analysis shows how a 0-DC signal (vi ) causes a DC shift in the circuit; this can not happen in a linear circuit, but here it is an effect of the junction nonlinearity. The change in VE (x) compensates the variable DC caused by I0 (x). 2.2.7 SPICE Transistor Models Numerical software devoted to simulation at electronic circuits level, such as SPICE, implement transistors models which are more complex than the ones described in this section [2]. For example, they typically take into account nonlinear effects, (voltage-dependent) junction capacitances, transit times, lateral carrier diffusions, body effect, and so forth. For bipolar transistors, SPICE implements the Gummel-Poon BJT model [18], which, when some parameters are not specified, reduces to the Ebers-Moll model [35]; both models are four-quadrant ones, since they can describe the BJT transistor in all the combinations of positive and negative voltage at the ports. Other models, such as the vertical bipolar intercompany model [23] are also available in specific SPICE implementations. SPICE simulations taking advantage of the built-in models can be used for the analysis of complex circuits, also considering, for example, uncertainty in the parameters values and thermal effects. Three examples are provided here of bias point calculation, small-signal response, and large-signal temporal analysis. In Figure 2.21, the dependence of the BJT bias point with the temperature is estimated for the collector feedback circuit and the four-resistor bias network. The three circuits, whose schematic is shown in Figure 2.21(a), are designed to have the same bias point at 27 ◦ C. The simulation uses the model describing the behavior of the commercial npn BJT 2N2222 by NXP [27]. The variation of the observed quantities are much more limited when the four-resistor network is used. The effect of tolerances of the components of the C-E amplifier previously analyzed in Figure 2.17 is investigated with a Monte-Carlo simulation in Figure 2.22. The simulation uses the model for the npn 2N222 BJT; the maximum gain current (BF parameter) is customized and set to 200, thanks to the LTSpice A Kinf Of (AKO) keyword. Resistances, capacitances, BF, and voltage supply values are defined by means of the MC(x,δx) function, causing the values used in the simulations to be randomly chosen in the interval [x(1 − δx), x(1 + δx)] with uniform distribution. A 5% tolerance is assumed for resistors and supply voltage, while larger tolerances are used for capacitors (20%); an incertitude as big as 50% is assumed for BF. The .ac analysis is repeated 1,000 times thanks to the .step

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Figure 2.21 Sensitivity of the bias point to temperature for the bias configurations in Figure 2.4(a) (dotted lines), 2.4(b) (continuous lines), 2.4(d) (dashed lines). (a) LTSpice schematics; simulations results of the collector current, (b) and collectoremitter voltage, and (c) drift versus temperature. The bias point is more stable with the four-resistor bias network. The schematic netlist is reported in Listing 2.3.

directive. The LTSpice schematic for the analysis is presented in Figure 2.22(a), while voltage gain curves calculated with 1000 independent simulations are shown in Figure 2.22(b); the inset shows the histogram, calculated with MATLAB, of voltage gains at 4 kHz, in linear scale. The average gain is −13.0 (22.3 dB); the standard deviation is as low as 0.431, showing that the bias network is effectively able to compensate for large variations of the BJT BF parameter. Finally, the C-E amplifier is simulated in the time domain in order to observe the generation of higher-order harmonics and the effect of the splitting of the emitter resistor. The schematic of the circuit is shown in Figure 2.23. For the analysis, an input sine wave at a frequency fs = 4 kHz is considered, with 40-mV amplitude. With the emitter resistor RE1 inserted in the circuit, the output voltage vo is similar to a sine wave (Figure 2.24(a)); in the spectrum, higher harmonics are suppressed by more than 30 dB with respect to the fundamental line at fs (Figure 2.24(b)). When the resistance RE1 is replaced by a short circuit (dashed line in Figure 2.23), the output voltage is clearly distorted (Figure 2.24(c)) and the line at 8 kHz is suppressed by only 12 dB with respect to the main one (Figure 2.24(d)).

2.3 Low-Noise Amplifiers for RF Receivers In a classical RF transceiver, the received signal coming from the antenna has suffered propagation through up to several kilometers in air and has gone through impairments by propagation issues (such as rain and multipath) and transmitter nonidealities (such as nonlinearity and noise). The LNA is the first block of the receiver chain responsible of amplifying this weak input signal without adding too much noise being the most critical of the amplification chain.

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Figure 2.22

Monte-Carlo simulations of the C-E amplifier. (a) LTSpice schematic, and (b) voltage gain curves obtained in 1000 runs with randomly generated values of resistance (5% tolerance), capacitances (20% tolerance), supply voltage (5% tolerance), and BF (50% tolerance); inset: histogram of the voltage gain at 4 kHz. The schematic netlist is reported in Listing 2.4.

Recalling the Friis’ formula of noise for a chain of N devices with gains Gk and individual noise factors Fk , the overall noise factor F can be computed as [30] N  Fk − 1 F2 − 1 F3 − 1 F = F1 + = F1 + + + ... k−1 G1 G1 G2 Gk 1 k=2

(2.45)

This leads to the fact that as long as the gain of the first stage G1 is sufficiently large, the overall noise factor is dominated by the noise factor of the first stage, whereas successive contributions are made negligible by the term G1 at the denominator.

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Figure 2.23

LTSpice schematic of the C-E BJT amplifier (with and without RE1 ) for large-signal analysis. The schematic netlist is reported in Listing 2.5.

Figure 2.24

Large-signal analysis of C-E BJT amplifier. Waveforms of the collector (vC ), the emitter(vB ), the base (vB ) and the output voltage (vO ) with (a) and without (b) emitter resistance RE1 , and corresponding spectrum (c,d) of the output voltage.

In practice, therefore, a LNA stage must be placed as early as possible in the RX chain to avoid degrading the received SNR. As a link budget example for a point-to-point transmission system in Ku band (from 12 GHz to 18 GHz), the following parameters can be considered: • • • •

Frequency: f ≈ 17 GHz; Transmitted power: PTX ≈ 25 dBm; TX/RX antenna gain: GTX = GRX ≈ 30 dB; Link length: d = 8 km.

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Figure 2.25

Simplified link budget.

Applying the Friis transmission formula [14, 30] to the simple model in Figure 2.25, the received power results: PRX = PRX GTX GRX

λ2 16π 2 d 2

(2.46)

or, in decibels, 4π d (2.47) λ that for the considered numerical example gives PRX ≈ −50 dBm. This is a typical power the LNA must be able to manage. The gain of a RF and microwave LNA is usually of the order of 10 dB to 15 dB, which is not enough for the ADC. In fact, an ADC usually requires voltage variations of at least a few tenths of volts, thus powers of about −20 dBm with a 50  load, while the typical power of the received signal is, as expressed earlier, of the order of −50 dBm), but sufficient to limit the effect of noise from the other stages. As explained later, an increased gain usually involves higher noise figures and an accurate trade-off between the two must hence be chosen. PRX,dBm = +GTX,dB + GTX,dB + GRX,dB − 20 log 10

2.3.1 Fundamentals The complete theory for the design of LNAs goes beyond the scope of this book. Here the fundamentals are briefly recalled, leaving the interested reader to explore more specific texts. Considering an arbitrary two-port stage, the figure of merit (FOM) of efficiency and linearity already introduced in power amplifiers (Section 2.4) can be adopted also for LNAs, but their importance is lower, in favor of the primary objectives of low noise and sufficient gain. 2.3.1.1 Definitions

The reference scheme with the quantities of interest is shown in Figure 2.26. The following definitions of gain are used [16, 30]: Operating gain:

GO =

PL Power delivered to load = PI Power delivered to amplifier

(2.48)

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Figure 2.26

Main quantities used for the derivation of characteristics in a generic two-port device.

GA =

Available gain:

PL,av Power available to load = PS,av Power available to amplifier

GT =

Transducer gain:

PL Power delivered to load = PS,av Power available to amplifier

(2.49) (2.50)

Practical considerations are often based on the transducer gain, as it represents the capacity of the stage to amplify a signal from the input (available power from the generator) to the actual load. A single-tone quantity x(t) = A cos(2π ft + φ) at the frequency f can be represented in terms of phasors as X = Ae jφ , so that the time-dependent quantity can be computed as x(t) = (Xe j2πft ). The real power dissipated by an arbitrary impedance Z = R + jX = Y1 = 1 G+jX (with all real parameters except for Z and Y ), at which ends a voltage phasor with absolute value |V | exists, is PZ =

|V |2 1 = |V |2 G. ∗ 2Z 2

(2.51)

where the ∗ notation represents complex conjugation. The available power is the maximum power from a generator with internal (series) impedance ZG and takes on the expression PG,av =

|VG |2 . 8 {ZG }

(2.52)

In order to transfer the available power to the load, the amplifier must be conjugately matched to the internal generator: ZL = ZG∗ . In practice, the load resistance must equal the generator’s internal resistance, whereas reactances must be opposite. Briefly recalling the scattering formalism, the scattering matrix S on forward (+ ) and backward (− ) voltage waves of a two-port network is defined as S=

S1,1 S2,1

S1,2 S2,2

with

+ V1− V1 = S . V2− V2+

(2.53)

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Dealing only with two-port devices, the comma in the subscripts is omitted in the following so that two equations can be written: V1− = S1,1 V1+ + S1,2 V2+

(2.54)

V2−

(2.55)

=

S2,1 V1+

+ S2,2 V2+ .

The characteristic impedance Z0 (typically 50 ) is used to relate voltages and currents and it is assumed here common at all the ports: In± =

Vn± Z0

(2.56)

where the currents associated to incoming waves are conventionally entering the positive terminal of the port toward the device, whereas the opposite is assumed for outgoing waves. The voltage input and output reflection coefficients seen from ports 1 and 2 result in S12 S21 S S12 S21 L i = S11 + . (2.57) and o = S22 + 1 − S11 S 1 − S22 L and

S12 S21 S (2.58) 1 − S11 S The source and load impedances, ZS and ZL , are related to the corresponding ZL −Z0 0 reflection coefficients S = ZZSS −Z +Z0 and L = ZL +Z0 . out = S22 +

2.3.1.2 Stability

The previous definitions are valid for an arbitrary linear two-port device. The conditions | i | < 1 and | o | < 1 must be verified to assure a stable behavior of the amplifier and correspond to enforcing positive input and output resistances. The two inequalities define two circular regions for L and S called stable regions. The equality | i | = 1 (2.59) corresponds to a circle in the complex plane for L . If both stable regions (in input and output) cover the unit disk, the device is unconditionally stable: no combination of passive L and S yields an unstable system. Alternatively, another small-signal check for unconditional stability is based on the Rollet’s stability coefficient [15, 33]: k=

1 + |det S|2 − |S11 |2 − |S22 |2 . 2|S12 ||S21 |

(2.60)

If k > 1 and another condition on the input or output (e.g., |det S| < 1), then the device is unconditionally stable. Otherwise, the test does not provide a definitive answer.

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Single-parameter coefficients also exist [11] based on the parameter µ, which guarantees unconditional stability if µ=

1 − |S11 |2 ∗ | + |S S | > 1. |S22 − S11 12 21

(2.61)

Otherwise, the stable regions must be checked as the test is not conclusive. Several techniques can be used to narrow the unstable regions or enforce unconditional stability. These typically involve placing resistive components at the input, increasing losses, lowering the gain, and introducing more noise. In case a conditional stability is accepted, L and S must be chosen within their stable regions and at a sufficiently safe distance from the borders to account for manufacturing tolerances and model approximations. 2.3.1.3 Constant Gain Circles

The transducer gain in (2.50) can be written considering the scattering parameters GT =

2 1 − |S11 |2 2 1 − | L | |S | . 21 |1 − S11 S |2 |1 − o L |2

(2.62)

At the right-hand side of (2.62), the first fraction accounts for source mismatches, whereas the last one introduces the effect of load mismatches. The central factor S21 is the intrinsic amplification term due to the active stage. Active devices are, in general, nonreciprocal and often |S21 |  |S12 |. The assumption S12 = 0 leads to the so called unilateral approximation, which neglects the reverse gain from the output to the input but provides the simpler expressions i = S11 and o = S22 regardless of S and L . In general, the device is not unilateral, and the maximum transducer gain can be found by analytically solving the simultaneous conjugate matching: S = i∗ and L = o∗ . In this case however, i depends on L and o depends on S ; the analytical solution for S,opt and L,opt is then more complex [30]. For conjugate matching, the maximum transducer gain results in    |S21 |   2−1  Maximum available gain: G k − = k MAG   |S12 | if unconditionally stable   |S21 |   Maximum stable gain: GMSG = otherwise |S12 | (2.63) Conversely, a potentially unstable device can often exhibit a higher gain. The relation between operating gain and L in (2.48) (or between available gain and S in (2.49)) can be also exploited to define “constant gain circles” in the complex plane for L (or S ) [8, 30] as a function of the scattering parameters and the desired gain. An example of constant gain circles is shown in Figure (2.27).

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Figure 2.27

Constant gain circles.

The constant gain circle collapses to a single point for the maximum attainable value. Once a suitable termination for operating (or available) gain has been selected, the other termination, S (or L ), can be chosen for conjugate matching, yielding the transducer gain to equal the max of the operating (or available) gain. 2.3.1.4 Noise Figure

A noisy two-port device can be seen as a noiseless two-port with series noise sources on its ports. To minimize the noise figure with a proper choice of source impedance, the noise source on the output port is transformed into a shunt noise current In at the input by means of the ABCD matrix formalism, where its own noise voltage source is already placed (Vn ). A noisy source Is , with its internal reference impedance Zs = Y1s connected to the input, completes the model sketched in Figure 2.28. Since the two-port device is noiseless it does not modify the SNR of the system. The noise factor can be evaluated from (2.45) and only the degradation introduced by the two equivalent sources must be considered. Since the noise sources are uncorrelated their powers add up, and the noise figure is given by F =

Ps + Pn |In + Ys Vn | 2 =1+ Ps |Is | 2

(2.64)

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Figure 2.28

Model for evaluation of noise figure of a two-port device with equivalent noise sources In and Vn connected to a noisy source Is , Yn .

where · indicates the temporal average, Pn is the combined noise due to In and Vn , whereas the last equality exploits the fact that all noise powers are referred to an arbitrary reference impedance whose value cancels out in the ratio. An optimum source impedance Ys,opt = Gs,opt + jBs,opt can be defined to give the minimum F : Bs,opt = −Bc ,  Gs,opt =

(2.65)

Gc2 +

Gu . Rn

(2.66)

This result shows that the optimum source impedance for noise does not coincide in general with the maximum power transfer condition (conjugate matching of input). Notice that the optimum value is difficult to achieve and the noise factor can be computed as a function of the minimum noise factor (attained when the optimum load impedance is used) and the chosen source impedance Ys : F = Fmin + with

Rn |Ys − Ys,opt |2 Gs 

Fmin = 1 + 2Rn Gc +

 Gu Gc2 + Rn

(2.67)  (2.68)

In most cases, commercial datasheets provide Rn , Fmin , and Ys,opt , so that the noise figure corresponding to any other source termination can be computed. Similar to power gains circles, constant-noise figure circles can also be drawn for values of the input reflection coefficient S for which F takes on a specified value greater than Fmin . These circles are centered on s,opt and are often plotted with gain circles to allow a trade-off between the two performances. For F = Fmin the constant noise circle collapses to a single point, which is S = S,opt corresponding to Figure 2.29. For higher values of F , the circles typically increase in radius similarly to the situation depicted in Figure 2.29, from where the relationship between input termination and noise figure appears evident.

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Figure 2.29

63

Constant noise circles.

2.3.2 Design Conventional design of LNAs for micrometer and millimeter-wave frequencies requires to bias the transistor to minimize its noise figure. Source termination is chosen to achieve minimum source noise whereas load termination is selected to achieve the required gain, designing reactive matching networks on both sides. The main limitation of this approach is the trade-off between power gain and noise figure, to limit the noise without reducing the gain too much. In a modern front-ends however, an important feature is to reduce as much as possible the number of passive components leading to the removal of the passive reactive matching networks in favor of active matching, where the bias of the transistor helps in reducing the real part of the optimum noise source termination and of the input impedance. This technique can be applied to different transistor type (i.e., FET or BJT) and in different semiconductor technologies (Si, SiGe, GaAs, GaN, InP, etc.). In summary, the key factors for a successful design of LNAs yielding to good trade-offs between noise figure, power gain, and die area can be summarized as follows [36]: 1. Active matching by proper bias and topologies in spite of reactive matching networks;

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2. Power consumption determined by biasing current related to the desired optimum source termination; 3. After setting the bias, gate width or emitter length do not affect the minimum noise figure of the transistor; 4. Real part of the optimum noise termination tuned by transistor dimensions; 5. Real part of the input impedance controlled by the reactive feedback element. To give to the reader an idea of the possible topologies, in the following the two main topologies for LNAs will be briefly introduced outlining also their common properties: • C-E or C-S; • Cascode. 2.3.2.1 Characteristics

C-E (or C-S) and cascode topologies success is mainly related to the relative simplicity of the structures and to the capacity to achieve active matching with noncomplex structures. The scheme of principle of the two topologies is presented in Figure 2.30. As previously stated, the cascode topology is the combination of a C-E (or C-S) structure and a C-B (or C-G) amplifier. The C-B configuration exhibits a wider bandwidth than the C-E even if its input impedance is often too low for practical matching, and thus a C-E section is placed as buffer input stage for its moderately high input impedance and its low gain is boosted by the C-B stage.

Figure 2.30

Common LNAs with bipolar transistors. (a) C-E configuration, and (b) cascode topology. The circuits can be implemented with an identical structure in MOS technology.

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Compared to a single-stage amplifier section, the cascode advantages are • • • • •

Higher input-output isolation; Higher input impedance; Higher output impedance; Higher gain; Wider bandwidth.

The use of two active devices instead of only one is the main drawback of this configuration. Furthermore, the voltage drop on the transistors is larger, reducing voltage swing and negatively, thus affecting the linearity figures. The input impedance Zi of the inductive-feedback networks of both structures reported in Figure 2.30 can be written at the operating frequency (ωo = 2πfo ) from the simplified equivalent circuit and result
Zi ≈ Rb + rE + ωT LE + j ωo LE + ωo LB −

1 ωo Ci

 (2.69)

with Ci =

gm,eff ωT

(2.70)

being ωT the cutoff angular frequency. From (2.69) it is clear that the amplifier has a resonant input series RLC network with a constant real part over frequency. If the LNA is connected to a 50  source impedance, like an antenna or filter, the real part of the input impedance must be matched to this value while the imaginary part should be canceled. The feedback inductance LE can be used for the first task while the base inductance for the second. The LE inductance degrades the fT independently of the operating frequency, transistor size, and bias point but depending on the bias current, which affects fT and LE . Normally, the emitter inductance LE is small enough to allow the designer to neglect the emitter series resistance, while the base inductance is usually larger and must be considered. The LNA output is capacitive, and a reactive network can be implemented by an inductance toward the power supply and a capacitance between the transistor and the load, also achieving at the same time DC blocking toward the following stages. Linearity is normally improved setting the bias to provide high current densities for peak transconductance but minimizing the noise figure. A suitable trade-off between these two must be found.

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From the basic cascode configuration shown in Figure 2.30(b), with small modifications it is possible to obtain 1. LNA with external resistance (Rex ) between gate and emitter in heterojunction bipolar transistor (HBT) or drain and source in MOSFET devices [26]; 2. LNA with inductance between the collector/drain of the transconductance amplifier (Q1) and the emitter/source of the transistor in C-B configuration (Q2) [38]; 3. LNA with inductance between the power supply and the base/gate of the transistor in C-B configuration (Q2) [22]; 4. LNA with a -network in order to improve the input matching [12].

2.4 Power Amplifiers for RF Transmitters Power amplifiers (PAs) add to the main task of any amplifier, which is the amplification of the input signal, other characteristics often more stringent than the mere stage gain. In fact, a PA needs to amplify the input signal, but assuring the required power level at the output, keeping under control distortion, size, weight, and achieving this goal in the most energy-efficient way as possible. Additionally, the devices adopted to build this kind of amplifier must satisfy specific requirements related to the nonlinear large-signal behavior that they will experience during normal operation: high breakdown voltage, maximum current, and maximum power. Focusing on radio frequency applications, the PA is normally the last stage of a transmitter and most likely the most critical block of it for the large impact on the power consumption of the system, related to the stimulus, the frequency of operation, and the bandwidth. Several sources are available to thoroughly analyze solid-state RF and microwave PAs in terms of design, efficiency, and linearity, or bandwidth enlargement (e.g., [7, 9, 21]). 2.4.1 Power Amplifiers Figures of Merit The behavior of a RF amplifier is described by its FOMs, a set of numerical values summarizing the how good its performances are. The most important FsOM of PAs are the power gain (i.e., the ratio between the output and input power), the efficiency of the DC to AC energy conversion (i.e., the ratio between the AC output power and the power coming from the DC source), and the linearity (i.e., the capability to preserve the quality of the information during the signal boosting, keeping the additional distortions to the minimum). Ideally, the output of a PA should be a perfect replica of the input with constant modulus and linear phase behavior as a function of frequency. The large-signal regime experienced by PAs leads to nonlinear behavior resulting in spurious frequency components at the output not present in the input signal but

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Figure 2.31

Main quantities related to PA operation.

generated within the PA itself and to frequency dispersion of gain in the amplifier bandwidth. The main specifications of a PA are normally given referring to a continuous wave (CW) single-tone stimulus (i.e., using a single input sinusoidal signal at frequency f0 ). In this case, the statistic of the signal is very simple, since average and peak power coincide and it is possible to identify the PA output power PO in the operative frequency range as the power delivered to a load, typically a 50  antenna for HF. In general, radio frequency systems signals are digitally modulated and spread over a certain frequency band. Considering the signal data rate, for the optimization of the frequency spectrum resources, mixed amplitude-to-amplitude (AM) and amplitude-to-phase (PM) modulations are very often adopted. As a result, the PA will work with nonconstant envelopes, varying in time according to the statistic distribution of the input signals, and to the associated modulations. In these conditions, the application influences signal bandwidth and power statistic distribution, in particular the ratio between peak and average power. Figure 2.31 highlights the main quantities needed to describe a PA, always referring to a single-tone scenario. The output power PO at f0 can be expressed as  1  PO (f0 ) = VO (f0 )IO∗ (f0 ) 2

(2.71)

while the corresponding input power PI is  1  PI (f0 ) = VI (f0 )II∗ (f0 ) . 2

(2.72)

The amplifier gain results as the ratio between output and input power. Different gains can be defined depending on the position where the power is considered (e.g., the power effectively entering the PA PI rather than the one available from the previous stage PAV ). In the former case, it is possible to define the operative gain GP :   PO f0  , (2.73) GP = PI f0

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while in the latter the transducer gain GT is introduced:   PO f0  . GT = PAV f0

(2.74)

For a matched PA, PAV = PI , and the two gains coincide. The efficiency η of a PA is defined as the ratio between the output power at fundamental and the DC power needed from the supply PDC :   PO f0 η= . (2.75) PDC Another important FOM related to the efficiency of the PA includes also the input power of the amplifier in the budget and is called power-added efficiency (PAE):     
PO f0 − PI f0 1 PAE = . (2.76) =η 1− PDC GP The higher the gain is, the closer the PAE and η are. Practically, for gain larger than approximately 15 dB to 20 dB the difference between η and PAE is negligible. At radio frequency, where the gain is typically low, PAE and η can differ significantly. This is not normally a major issue being the main task of the PA to boost the power level, leaving the task of increasing gain to intermediate stages. The nonlinear regime experienced by PAs leads to a nonconstant gain and efficiency because they depend on the input/output power at which they are evaluated, as illustrated in Figure 2.32. The figure highlights how the gain versus input power of a PA is not constant when the PA is driven towards the device physical boundaries in terms of voltage or current maximum excursions, bringing to the compression region where the gain deviates from the small-signal theoretical behavior. The maximum power of the PA is called saturated power (PO,sat ), and

Figure 2.32

Typical PO , GP , η and PAE versus PI for a power amplifier.

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it is related to pinch-off voltage, gate direct conduction, knee voltage, breakdown voltage, and maximum current. The difference between small-signal and power gain is called compression level. For example, the 1-dB compression level identifies a power level where the gain has decreased of 1 dB with respect to the small-signal gain GSS . The corresponding output power, η and PAE can be referred as PO,1dB , η1dB , and PAE1dB , respectively, as shown in Figure 2.32. The same considerations can be applied for different levels of compression. The highest efficiency of the PA is usually achieved for output power close to PO,sat . Classic high-efficiency design strategies maximize the performance at saturation, ensuring good efficiencies; however, at the cost of poor PA linearity. Alternatively, gain, PAE, and η, can be expressed as a function of the output back-off (OBO) or the input back-off (IBO), representing how far from PO,sat , or PI,sat the amplifier is OBO|dB = 10 log 10 IBO|dB = 10 log 10

PO,sat , PO PI,sat . PI

(2.77) (2.78)

Gain compression and power saturation deeply affect the linearity of the PA and different FOMs have been introduced to quantify the degree of distortion of a PA. Several measurement setups are available, from simple scalar measurements carried out with spectrum analyzers or power meters up to real digital transceiver system emulators. Among them it is worth highlighting the harmonic intercept points of order n-th (IPn ), the intermodulation distortion (IMD) and the carrierto-intermodulation ratio (CIMR). For IPn measurements, linearity is evaluated in CW conditions either from simulations or in measurement extrapolating the value of the power level where the output power at the fundamental tone equals the n-th harmonic one. Figure 2.33 shows the PA response to a single-tone test in terms of fundamental, second, and third harmonic. The third-order intercept points in output (OIP3) and input (IIP3) are also reported. The same characterization, but with two-tone excitation, can be adopted for the IMDs; an example again of third-order crossing between fundamental and (2f1 − f2 ) IMD product is shown in Figure 2.34. CIMRn requires two-tone measurements around the carrier frequency as a function of the two-tone amplitude. It is given by the ratio between the two tones and the n-th order intermodulation product power. In this case the information is more complete since it provides insight, in terms of intermodulation power, on the PA behavior as a function of the instantaneous power level, something extremely important when dealing with nonconstant envelope signals.

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Figure 2.33

Single-tone test response of a PA in terms of fundamental, second and third harmonic. The third order intercept points OIP3 and IIP3 points are also reported versus frequency (a) and versus input power (b).

Figure 2.34

Two-tone test response of a PA as a function of frequency (a) and input power (b).

When dealing with complex signal modulation, another popular FOM is the adjacent channel power ratio (ACPR), a quantitative measure of the spectral regrowth as an interference to a nearby channel in the presence of actual input signals. While the detection step at the PA output can be rather simply carried out with a spectrum analyzer, the PA must be fed in with a digitally modulated input signal. In fact, a signal generator is required that able to provide the data stream with proper statistic and symbol codification. Figure 2.35 shows an example of spectral regrowth for a modulated signal and the corresponding amplitude and phase variation versus input amplitude in terms of AM/AM compression and AM/PM conversion. A well-adopted linearity indicator, extremely useful for complex modulation schemes, is the error vector magnitude (EVM), which quantifies the difference between the ideal constellation signals and the ones measured at the PA output (Figure 2.36). The measurement setup represents at a digital transceiver system

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Figure 2.35

Typical spectral regrowth for a modulated signal (a) and the corresponding amplitude and phase variation versus input amplitude in terms of AM/AM compression and AM/PM conversion (b).

Figure 2.36

Error vector magnitude.

since the data at the input of the PA has to be digitally modulated, and from the PA output the baseband constellation has to be reconstructed. It yields extremely significative results since it is directly reporting the effects at baseband of the distortion introduced by the PA nonlinearities. In fact, it can give straightforward insights to PA effects on system-level behavior and performance, for example providing a time domain evaluation on the baseband digital I and Q symbols. 2.4.2 Power Amplifier Classes Power amplifiers can be classified according to their operation modes and classes. The PA classification in A, AB, B, and C is determined by the quiescent bias point,

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Figure 2.37

Transcharacteristics (a) and output characteristics (b) of the ideal device used in the analysis, with bias points of different PA classes.

as explained in Figure 2.37, where the different bias points are indicated on the output- and trans- characteristics of the ideal FET-like device.1 Considering the simple scenario of a single-ended amplifier where the active device is modeled with an ideal nonlinear voltage-controlled current source (VCCS), an approximation typically adopted is to classify the operational classes by the bias point selected, and to analyze the current/voltage waveforms to maximize power and efficiency. Any amplifier stage drives the load taking the required energy from the supply. At low frequency, the peak-to-peak voltage swing on the load is covered, remaining in the boundaries fixed by the supply voltage VDD . At radio frequency, the bias network includes inductors and capacitors for decoupling DC and high-frequency components (bias-T, Figure 2.38), and the bias supply is then given through an inductor. This allows for having swings on the load that can reach voltages as high as 2VDD . The inductive load is adopted to maximize the dynamics of the load, a fundamental feature in a PA. Notice that the stress for the active device is doubled, being necessary to sustain, even if only dynamically, a voltage higher than VDD . In order to maximize the voltage swing, the voltage VDD is normally chosen at the center of the possible dynamics, VDD = (VDS,br + VDS,k )/2, where VDS,br , VDS,k are the device breakdown and knee voltages, respectively. Drain current iDS is limited between 0 and the current for null gate controlling voltage IDSS . The gate bias voltage VGG determines the drain current quiescent value IDD , identifying the PA class. Table 2.5 lists the PA classes with the corresponding VGG and IDD . VTH is the gate-to-source pinch-off voltage. 1 Being today FET-like the reference choice for radio frequency power amplifiers, in the following

the discussion will be focused on this kind of devices but the applies also to bipolar transistors.

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Figure 2.38

Example of radio frequency bias-T circuit: (a) Lumped elements, and (b) with transmission line. Table 2.5 PA Classe Bias Points

Figure 2.39

Class

V GG

I DD

φ

A AB B C

VTH /2 VTH < ... < VTH /2 VTH . . . < VTH

IDSS /2 0< ... < IDSS /2 0 0

360◦ ◦ 180 < ... < 360◦ 180◦ ... < 180◦

PA simplified scheme modeling active device with ideal nonlinear voltagecontrolled current source.

Considering the scheme of Figure 2.39, where the single-ended device is connected in a C-S configuration, drain and gate are biased through RF-chokes, and DC current is decoupled by DC-block capacitors. In the output section a resonator is employed to filter out harmonic components at the load. The signal generator provides a pure sinusoidal input. At full input drive (i.e., when the input

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Figure 2.40

Class A PA waveforms at full drive with ideal device. Output characteristics with dynamic load line (a) and time domain waveforms (b).

voltage vGS (t) reaches 0 V), the maximum drain current IDSS is achieved. Under this condition and assuming a constant transconductance for VTH < vGS < 0, in class A, the drain current iD (t) is a perfect sine wave. The load seen by the device is RL at fundamental and a short circuit at all harmonics (Figure 2.39), and determines the drain-source voltage (vDS ). The maximum output power is achieved if the voltage and current dynamics are simultaneously maximized on the device. To this aim the load must be RL = ROPT =

VDS,br − VDS,k IDSS

(2.79)

where ROPT is the optimum load for maximum output power. A resistor with value RL < ROPT limits the voltage swing to a value below the maximum, while for RL > ROPT the voltage reaches knee or breakdown before current is at full swing. Both conditions correspond to a reduced power with respect to the ROPT case. The voltage and current waveform, and the corresponding load line (i.e., the plot of current waveform versus voltage waveform curve) on the output characteristic for a class A device at full drive are shown in Figure 2.40. The maximum output power generated by a class A power amplifier is easily evaluated: 1 VDS,br − VDS,k IDSS PO,max = (2.80) 2 2 2 The maximum DC power absorbed from the supply is instead given by the product of average current and the value of the DC voltage supply VDD = (VDS,br − VDS,k )/2: PDC,max =

VDS,br − VDS,k IDSS 2 2

(2.81)

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In a class A amplifier, the DC power supply PDC is independent of the power level. The maximum efficiency is then achieved at maximum output power, and, neglecting the knee voltage, its value is 50%. At the same time, the power dissipated by the device corresponds to PDC,max and PDC,max /2 at zero and maximum input drive, respectively. This behavior suggests that a device biased in class A dissipates the maximum power when no input signal is applied, while the best (coldest) thermal regime coincides with the maximum output power conditions. Reducing the bias current, the device moves toward class AB, B, and finally C: still referring to maximum input drive (i.e., when vGS reaches zero, the iDS results as a cut sinusoidal signal). In terms of amount of time during the period where the device is on, a convenient description is possible introducing the conduction angle φ, and write the iDS as a function of it and of quiescent current IDD :  IDD + (IDSS − IDD ) cos (θ) if − φ/2 ≤ θ ≤ φ/2 iDS (θ ) = (2.82) 0 otherwise. Table 2.5 reports the correspondence among φ and different PA classes. The value of φ can be related to the quiescent current:
 
IDD IDD /IDSS φ = 2 arccos . (2.83) = 2 arccos IDD − IDSS IDD /IDSS − 1 where is highlighted that IDD is commonly expressed relatively to IDSS . The cut iDS waveform contains harmonic components that are filtered by the output resonator of Figure 2.39 in order to provide a purely sinusoidal output. For this reason, these PA classes are referred to as tuned load class AB/B1 . It has to be noticed that in this configuration also the vDS voltage becomes sinusoidal. Figure 2.41 shows the waveforms and dynamic load line in the class B case. Notice that fundamental components of drain current and voltage are identical in class A and class B. As a consequence, also maximum output power and optimum load coincide for class A and tuned load class B. On the other hand, the power absorbed from DC supply in class B is PDC,max =

VDS,br − VDS,k IDSS . 2 π

(2.84)

Thus, the maximum efficiency in class B is π/4 ≈ 78%. In this case the dissipated power is null for no input, meaning that its power management is improved with respect to the class A. On the other side, gain in class B is theoretically 6 dB lower 1 Other methods to reject harmonics are available, such as the push-pull PA. Its usage is limited

at radio frequency by many factors: a description of push-pull pros and cons can be found in [9].

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Figure 2.41

Class B PA waveforms at full drive with ideal device. Output characteristics with dynamic load line (a) and time domain waveforms (b).

than in class A, since the same output power is obtained for a doubled input drive. In the middle of the two previous classes there is the class AB, today the most adopted for the design of radio frequency PAs because it represent a trade-off among different FoMs, efficiency, gain, and linearity. A first significant difference of a class AB PA with respect to both class A (φ = 360◦ ) and class B (φ = 180◦ ) is that the conduction angle φ is no more constant versus input power (as well as for class C PA), and as a consequence the maximum output power, efficiency, and dissipated power depends on the value of it. For small input drive the class AB PA works as a class A one, φ = 360◦ , and the device is never pushed below the pinch-off, then increasing the stimulus φ decreases. Figure 2.42 shows, for class AB bias points, the values at full input drive of the maximum efficiency and of the output power and absorbed power normalized to PDC,max in class A. Note that the efficiency monotonically decreases from class B to class A, and the DC absorbed power increases. The output power at fundamental is not constant, and has a maximum in class AB: this situation is verified selecting RL accordingly, to avoid early vDS saturation. It is also interesting to consider as a figure of merit the product of efficiency and fundamental output power: Figure 2.42 shows, on the right graph, this value together with efficiency, and it can be noticed that there is a wide range of class AB bias points close to class B (i.e., deep class AB) sharing almost the same efficiency. 2.4.3 High-Efficiency PAs: Switching and Harmonic Tuning The traditional PA classes from A to C act on the bias point to reduce the power consumption while keeping the output current a sine wave or a section of it. If

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Figure 2.42

Variation of class AB point: impact on performance at full input drive. Top axis: conduction angle. Bottom axis: IDD /IDSS . Efficiency, DC absorbed power and output power (a). Efficiency and product of efficiency and output power (b).

this assumption is removed, the harmonics can be exploited to increase the stage efficiency. The overall power balance of a PA in case of CW excitations leads to PI + PDC

∞      = Pdiss + PO f0 + PO nf0

(2.85)

n=2

where Pdiss is the power wasted by heat dissipation within the PA by the active devices, and PO (nf0 ) is the power associated to the harmonic components generated within the PA and sent to the load and input termination. From (2.85) it is clear that Pdiss and PO (nf0 ) need to be reduced (ideally zeroed) to maximize the efficiency of the PA. 2.4.3.1 Switching-Mode Amplifiers: Class D and Class E

In class D and class E amplifiers, the active device acts as a switch. The drainto-source voltage is ideally zeroed when the current flows, zeroing the power dissipated in the device as well and achieving, in theory, a 100% efficiency. Class D PAs derives from the classical low-frequency push-pull configuration, with the active devices biased in class B but using a square-wave driving signal, causing the device to work in active region for half of the signal period. The active devices are driven with opposite phases, splitting the input signal by a transformer and deliver in output current or voltage square waves that needs to be filtered to keep the fundamental component only (Figure 2.43). The theoretical waveforms of class D amplifiers are shown in Figure 2.44. The output circuit (Lo and Co ) is a filter to keep only the fundamental component

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Figure 2.43

Scheme of principle of a class D PA (a) and corresponding equivalent circuit (b).

on the load R: 2VDD sin(θ) π 2VDD sin(θ) iO (θ) = πR

vO (θ) =

(2.86) (2.87)

The output power is PRF =

2 2 VDD 2 VDD ≈ 0.203 π2 R R

(2.88)

2 2 VDD . π2 R

(2.89)

and the DC power is equal to PDC =

In this condition, the ideal efficiency is 100%. Notice how the same configuration with the active devices biased in class B (classic push-pull) would lead to a maximum efficiency of 78%. Clearly, in real devices it is impossible to have a zero voltage drop across the transistor when it is saturated because a Ron is always present. Another issue related to this configuration is the presence, at high frequency, of the transformer limiting the exploitation of this technique below 1 GHz. Class E amplifiers, introduced in 1975 [34], are nonlinear amplifiers realized following the scheme of Figure 2.45). In this case a single device is employed as

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Figure 2.44

Class D ideal waveforms.

Figure 2.45

Scheme of principle of a class E PA.

79

a switch. The ideal working conditions are 1. A null voltage across the active device when ON and the current is maximum; 2. A null current flowing in the transistor drain when the device is OFF and the voltage is maximum; 3. A delayed rise of the drain voltage until the current is zero; 4. A voltage that goes to zero before the current starts to flow; 5. A minimized transition time; 6. A very steep slope of the voltage waveform during the OFF-ON transition. The simultaneous fulfillment of the previous conditions leads to the ideal waveforms of Figure 2.46. These class E amplifiers achieve, in theory, 100% efficiency. However, the range of applicability at high frequency results limited

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Figure 2.46

Waveforms for a class E PA.

by the duration of the transition ON-OFF, influenced by the technological parameters of the active devices. For these reasons class E amplifiers can be practically used today only up to few gigahertz even if examples are becoming available also at higher frequency, especially in silicon RFICS. Another possible issue of this configuration is represented by the stress induced on the active device that works as a switch. The gain of the stage is just the result of the design, an amplitude sufficient to drive the active device from saturation to interdiction being the only requirement. Design equations of class E amplifiers are beyond the scope of this book and are presented, for example, in [1]. 2.4.3.2 Harmonic-Tuned Amplifiers: Class F

The harmonics generated by the nonlinear stages can be controlled to boost the amplifier efficiency, providing a different approach with respect to the one seen for switching mode PAs. In real cases, no more than the first three harmonics are used, both for limiting the network complexity and because higher harmonics are oftened shorted by the device parasitic effects. The class F amplifier is a classical example of this strategy. Instead of using the active device as a switch to shape the voltage (current) into a square wave, the active device works in its active region and higher-order harmonics are shaped and summed to the fundamental one to get an almost square wave. The bias and the load at the fundamental are the same of class B stages, but the tuned circuit L2 C2 is open for the second harmonic while L3 C3 is a short for the third. Figure 2.47 shows an example realization of low-order class F amplifier. 2.4.4 Efficiency in Back-Off: Doherty and Envelope Tracking The schemes presented so far share the same issue of an efficiency drop with backoff: when the input driving level decreases the output power is decreasing faster

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Figure 2.47

Low-order class F PA. Only fundamental, second, and third harmonics are controlled by the two resonators included in the output matching network.

Figure 2.48

Block schemes of Doherty PA (a) and Envelope Tracking architecture (b).

than the DC from the supply. In class A, DC power is constant; therefore the efficiency drops linearly with the input level reduction. In class B, the DC current follows the behavior of the output fundamental current that drops with the square root of the input driving level. PAs with both DC current and voltage modulated by the input driving level would have constant efficiency independently of the power level, which would be perfect to handle nonconstant envelope modulations. This issue can be mitigated by adopting ad hoc solutions for keeping the efficiency degradation at back-off limited. In this section, the Doherty power amplifier (DPA) and the envelope tracking (ET) are briefly introduced. They both try to minimize the dissipated power at back-off by allowing the drain voltage to reach zero at its minimum, but they apply this countermeasure through radically different approaches. Moreover, the DPA can be seen as an analog technique, while the ET requires a system-level modification. Their schemes of principle are shown in Figure 2.48. The DPA, proposed in 1936 [10], adopts the load modulation concept to increase the voltage swing at back-off. The basic DPA is composed by two devices, the main and the auxiliary, which drive current into a common node. Typically, maximum efficiency is obtained at saturation (PO,sat ) and at 6 dB of OBO (PO,sat /4). For power lower than PO,sat /4 (i.e., half of maximum input voltage), only the main device, biased in class B in the original version, is active, and it is loaded with 2ROPT . This allows

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Figure 2.49

Waveforms (a) and dynamic load lines (b) for the main stage an ideal Doherty with neglected knee voltage, at full input drive and half input drive.

Figure 2.50

Waveforms (a) and dynamic load lines (b) for the microwave device of an ideal ET with neglected knee voltage, at full input drive and half input drive.

to maximize the voltage swing at half maximum current, as shown in Figure 2.49. For PO,sat /4 < PO < PO,sat , the auxiliary device is on and injects current into the common node. This increases the total output power of the Doherty, and it modulates the load seen by the main device from 2ROPT to ROPT . The correct load modulation requires an impedance inverter. Input splitter and phase delay line provide the correct phase and amplitude relationship of currents at the common node. The auxiliary stage turning on is controlled by biasing the auxiliary device in class C. Several modifications to the basic Doherty structure have been proposed to optimize some of its features and to overcome its inherent limitations. A more ample discussion on DPAs can be found in [5, 7, 9, 17]. Specific examples of DPAs applications are available in [4, 6, 19, 28]. These prototypes are still at research level, since their introduction in commercial products is still limited by the intrinsic bandwidth and linearity issues of the Doherty technique, as pointed out in [29, 31, 32]. In contrast, in the ET technique [37] a linear amplifier stage acts as the PA (e.g., a class AB), but its drain bias follows dynamically the envelope of the input signal (Figure 2.50), minimizing in this way the dissipated power. As

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an example, the drain bias voltage is reduced from VDD to VDD /2 to achieve maximum efficiency for an input envelope half of its maximum. The range of drain bias adaption, the selection between a continuous or stepped control, and the technique for designing the envelope amplifier are driven by the application, in terms of power levels, signal bandwidth, and linearity constraints. In general, there is a trade-off, for a given power level, between the bandwidth of the envelope amplifier and its efficiency.

2.5 SPICE Netlists Listing 2.1 NETLIST for the bias point analysis of the C-E BJT amplifier presented in in Figure 2.18(a),

VCC VCC 0 12 VBE B E 0.7 F_beta C E VBE 200 Re1 E 1 330 Re2 1 0 12k Rb2 B 0 82K Rb1 VCC B 120k Rc VCC C 12K .op .end

Listing 2.2 NETLIST for the small-signal analysis of the C-E BJT amplifier presented in Figure 2.18(b)

vs 1 0 AC 1 V0 4 2 0 F_beta0 C 2 V0 200 RB1 0 B 120k RB2 B 0 82K RE1 2 3 330 RE2 3 0 12k rpi B 4 15.75k RL OUT 0 10k RS IN 1 50 C 0 C 12k CC 0 C 1n CE 3 0 1u CL OUT C 4.7u

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CS B IN 4.7u .ac dec 100 100m 100K .end

Listing 2.3 NETLIST for the analysis of the sensitivity if different BJT bias networks to temperature shown in Figure 2.21.

VCC VCC 0 12 QBasic 3 5 0 0 2N2222 RB1 VCC 5 6.98Meg RC1 VCC 3 24.5k

QCollectorFreedback 2 6 0 0 2N2222 RC2 VCC 2 24.40k RF 2 6 1.929Meg QFourResistors 4 7 8 0 2N2222 RB3 7 0 82k RB2 1 7 120k RC3 VCC 4 12k RE 8 0 12.330k .model NPN NPN .model PNP PNP .lib \LTspiceXVII\lib\cmp\standard.bjt .step temp -10 80 10 .op .param temp 27 .end

Listing 2.4 NETLIST for the Monte-Carlo analysis of the small-signal voltage gain of a 2n2222-based BJT C-E amplifier presented in Figure 2.22.

vi N001 0 AC 1 VCC VCC 0 {mc(12,tolVal)} Q1 C B E 0 CustomBJT Ri IN N001 {mc(50,tolR)} RC VCC C {mc(12k,tolR)}

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RE1 E N002 {mc(330,tolR)} RE2 N002 0 {mc(12k,tolR)} RB2 B 0 {mc(82k,tolR)} RB1 Val B {mc(120k,tolR)} RL OUT 0 {mc(10k,tolR)} CE N002 0 {mc(3.3u,tolC)} CS B IN {mc(100n,tolC)} CC Val C {mc(1n,tolC)} CL OUT C {mc(10n,tolC)} .model NPN NPN .model PNP PNP .lib \LTspiceXVII\lib\cmp\standard.bjt .ac dec 10 10m 1MEG .step param myrun 1 1000 1 .param tolC=0.2 tolR=0.05 tolBF=0.5 tolVal=0.05 .model CustomBJT AKO:2N2222 (BF={mc(200,tolBF)} .end

Listing 2.5

NETLIST for the large-signal analysis presented in Figure 2.23.

VCC VCC 0 12v vs 1 0 SINE(0 40m 4k) AC 1 Q1 C B E 0 2N2222 RE1 E 2 330 RE2 2 0 12k RB2 B 0 82k RB1 VCC B 120k RC VCC C 12k Rs IN N001 50 RL OUT 0 10k CE 2 0 1u CC VCC C 1n CL OUT C 4.7u CS B IN 4.7u .model NPN NPN .model PNP PNP .lib \LTspiceXVII\lib\cmp\standard.bjt .tran 1 .end

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References [1]

Albulet, M., RF Power Amplifiers, Electromagnetic Waves. Institution of Engineering and Technology, 2001.

[2]

Antognetti, P., and G. Massobrio, Semiconductor Device Modeling with SPICE, McGraw-Hill, 1988.

[3]

G. Brocard. The LTSpice IV Simulator: Manual, Methods and Applications. Würth Elektronik, 2013.

[4]

Camarchia,V., et al. “7 GHz MMIC GaN Doherty Power Amplifier with 47% Efficiency at 7 dB Output Back-off,” IEEE Microw, Wireless Compon. Lett, Vol. 23, No. 1, January 2013, pp. 34–36, DOI: 10 . 1109/LMWC.2012.2234090.

[5]

Camarchia,V., et al. “The Doherty Power Amplifier: Review of Recent Solutions and Trends,” IEEE Trans. Microw. Theory Techn., Vol. 63, No. 2, 2015, pp. 559–571, DOI: 10.1109/TMTT.2014.2387061.

[6]

Campbell, C. F., et al., “A K-Band 5W Doherty Amplifier MMIC Utilizing 0.15 µm GaN on SiC HEMT Technology,” Compound Semiconductor Integrated Circuit Symposium (CSICS), 2012 IEEE, October 2012, pp. 1–4, DOI:10.1109/CSICS.2012.6340057.

[7]

Colantonio, P., F. Giannini, and E. Limiti, High Efficiency RF and Microwave Solid State Power Amplifiers, Microwave and Optical Engineering, John Wiley & Sons, 2009.

[8]

Collin, R.E., Foundation for Microwave Engineering, Second Edition, New York: McGrawHill, 1992.

[9]

Cripps, S.C., RF Power Amplifiers forWireless Communications, Norwood, MA: Artech House, 2006.

[10]

Doherty, W. H., “A New High Efficiency Power Amplifier for Modulated Waves,” Proc. IRE Vol. 24, No. 9, September 1936, pp. 1163–1182, DOI: 10.1109/JRPROC.1936.228468.

[11]

Edwards, M. L., and J. H. Sinsky, “A New Criterion for Linear 2-Port Stability Using a Single Geometrically Derived Parameter,” Microwave Theory and Techniques, IEEE Transactions on, Vol. 40, No. 12, December 1992, pp. 2303–2311, DOI: 10.1109/22.179894.

[12]

Egels, M., et al., “Design Method for Fully Integrated CMOS RF LNA,” Electronics Letters, Vol. 40, No. 24, November 2004, pp. 1513–1514, DOI: 10.1049/el:20046396.

[13]

Franco, S., Design with Operational Amplifiers and Analog Integrated Circuits, Third Edition, Boston: McGraw-Hill, 2002.

[14]

Friis, H. T., “A Note on a Simple Transmission Formula,” Proceedings of the IRE, Vol. 34, No. 5, May 1946, pp. 254–256, DOI: 10.1109/JRPROC.1946.234568.

[15]

Gentili, C., Microwave Amplifiers and Oscillators, McGraw-Hill, 1987.

[16]

Gonzalez, G., Microwave Transistor Amplifiers: Analysis and Design, Prentice Hall, 1996.

[17]

Grebennikov, A., and S. Bulja, “High-Efficiency Doherty Power Amplifiers: Historical Aspect and Modern Trends,” Proceedings of the IEEE, Vol. 100, No. 12, December 2012, pp. 3190– 3219, DOI: 10.1109/JPROC.2012.2211091.

[18]

Gummel, H. K., and H. C. Poon, “An Integral Charge Control Model of Bipolar Transistors,” The Bell System Technical Journal, Vol. 49, No. 5, May 1970, pp. 827–852, DOI: 10.1002/j.1538-7305.1970.tb01803.x.

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[19]

Gustafsson, D., et al., “A Wideband and Compact GaN MMIC Doherty Amplifier for Microwave Link Applications,” IEEE Trans. Microw. Theory Techn., Vol. 61, No. 2, February 2013, pp. 922–930, DOI: 10.1109/TMTT.2012.2231421.

[20]

Jaeger, R., and T. Blalock, Microelectronic Circuit Design, Fifth Edition, McGraw-Hill Higher Education, 2015.

[21]

Kenington, P.B., High Linearity RF Amplifier Design, Norwood, MA: Artech House, 2000.

[22]

Lavasani, S.H.M., and S. Kiaei, “A New Method to Stabilize High Frequency High Gain CMOS LNA,” Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems, Vol. 3, December 2003, pp. 982–985, DOI: 10.1109/ICECS.20031301673.

[23]

McAndrew, C. C., et al, “VBIC95, the Vertical Bipolar Inter-Company Model,” IEEE Journal of Solid-State Circuits, Vol. 31, No. 10, October 1996, pp. 1476–1483, DOI: 10.1109/4.540058.

[24]

Millman, J., and A. Grabel. Microelectronics, Second Edition, McGraw-Hill, 2001.

[25]

Nagel, L. W., and D.O. Pederson, SPICE (Simulation Program with Integrated Circuit Emphasis), technicalreportUCB/ERL M382, EECS Department, University of California, Berkeley, April1973.

[26]

Nguyen, T.-K., and S.-G. Lee, “Noise and Gain Optimization Technique for RF-Integrated CMOS Low Noise Amplifier,” 2003 IEEE Conference on Electron Devices and Solid-State Circuits, December 2003, pp. 221–224, DOI: 10.1109/EDSSC.2003.1283518.

[27]

P2N2222A NPN Silicon Amplifier Transistors, rev. 7. URL: https://www.onsemi.com/ pub/Collateral/P2N2222A-D.PDF.

[28]

Piazzon, L., et al., “15% Bandwidth 7 GHz GaN-MMIC Doherty Amplifier with Enhanced Auxiliary Chain,” Microwave and Optical Technology Letters, Vol. 56, No. 2, February 2014, pp. 502–504, DOI: 10.1002/mop.28108.

[29]

Piazzon, L., et al., “Effect of Load Modulation on Phase Distortion in Doherty Power Amplifiers,” IEEE Microw. Wireless Compon. Lett., 2 Vol. 4, No. 7, June 2014, pp. 505–507, DOI: 10.1109/LMWC.2014.2316507.

[30]

Pozar, D. M., Microwave Engineering, Second Edition, Chapter 11, John Wiley & Sons, Inc., 2004, pp. 536–576.

[31]

Quaglia, R., et al., “Experimental Investigation of Bias Current and Load Modulation Effects in Phase Distortion of GaN HEMTs,” Electronics Letters, Vol. 50, No. 10, May 2014, pp. 773–775, DOI: 10.1049/el.2014.0983.

[32]

Quaglia, R., et al., “Linear GaN MMIC Combined Power Amplifiers for 7-GHz Microwave Backhaul,” IEEE Trans. Microw. Theory Techn., Vol. 62, No. 11, November 2014, pp. 2700– 2710, DOI: 10.1109/TMTT.2014.2359856.

[33]

Rollett, J. M., “Stability and Power-Gain Invariants of Linear Two-ports,” IRE Transactions on Circuit Theory, Vol. 9, No. 1, March 1962, pp. 29–32, DOI: 10.1109/TCT.1962.1086854.

[34]

Sokal, N. O., “Analog Circuit Design: Scalable Analog Circuit Design, High Speed D/A Converters, RF Power Amplifiers,” Boston: Springer, 2002, pp. 269–301, https://doi.org/10.1007/0-306-47950-8_14.

[35]

Sze, S. M., Semiconductor Devices: Physics and Technology, Second Edition, Wiley India, 2008.

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[36] Voinigescu, S., High-Frequency Integrated Circuits, Cambridge University Press, 2013. [37] Wang, Z., Envelope Tracking Power Amplifiers for Wireless Communications, Norwood, MA: Artech House, 2014. [38]

Zhang, C., D. Huang, and D. Lou, “Optimization of Cascode CMOS Low Noise Amplifier Using Interstage Matching Network,” 2003 IEEE Conference on Electron Devicesand Solid-State Circuits, December 2003, pp. 465–468, DOI: 10.1109/EDSSC.2003.1283574.?hrefsection:4i?

Selected Bibliography Collin, R. E., Foundation for Microwave Engineering, Second Edition, New York: McGraw-Hill, 1992. Franco, S., Design with Operational Amplifiers and Analog Integrated Circuits, Third Edition, Boston: McGraw-Hill, 2002. Jaeger, R., and T. Blalock, Microelectronic Circuit Design, Fifth Edition, McGraw-HillHigher Education, 2015. Millman, J., and A. Grabel, Microelectronics, Second Edition, McGraw-Hill, 2001.

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3 Frequency Conversion Circuits Frequency conversion circuits provide an output signal that is a copy of the input signal but centered around a different frequency. Although frequency conversion happens in any nonlinear system, frequency conversion circuits are those where this effect is sought and optimized. This chapter will treat two main categories of frequency conversion circuits; namely frequency mixers and frequency multipliers.

3.1 Frequency Mixers In a mixer, the output frequency is the sum (or the difference) of the input signal frequency and that of a reference signal, LO). In upconversion mixers, the input signal frequency (intermediate frequency (IF), fIF ) is relatively low, while the output signal frequency RF, fRF ) is higher. The relation between these frequencies and the LO frequency fLO is fRF = fLO ± fIF .

(3.1)

Normally, a SSB mixer is desired since it gives the most efficient use of spectral resources (see Chapter 1), meaning that either the sum or difference of frequencies is used only. In downconversion mixers, the input signal is at fRF , while the output is at fIF and the relation with fLO is
fIF = +fLO − fRF fLO ≥ fRF (3.2) fIF = −fLO + fRF fLO ≤ fRF . Figure 3.1 shows the circuit symbols and ideal behavior of up- and downconversion mixers. 89

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Figure 3.1

Upconverter (a) and downconverter (b) mixers with ideal behavior.

Figure 3.2

Response of a linear, time-invariant system.

The demonstration of mixing for generic signals requires the use of convolution in the frequency domain, but the theoretical picture can be simplified by considering the input signals as single tones. Therefore, in the analysis provided here, the input signals will be, for upconverters, vLO (t) = VLO cos(2π fLO t) vIF (t) = VIF cos(2π fIF t),

(3.3)

while for downconverters, the stimuli will be vLO (t) = VLO cos(2π fLO t) vRF (t) = VRF cos(2π fRF t).

(3.4)

To simplify the notation, the following instantaneous phases are defined: θRF = (2π fRF t) θLO = (2π fLO t)

(3.5)

θIF = (2πfIF t). In linear, time-invariant systems, the frequency content at the output port is identical to that at the input. In fact, if the system of Figure 3.2 is considered with a constitutive equation: y(t) = ax(t)

(3.6)

and the input x(t) is expressed as the sum of two tones x(t) = vLO (t) + vIF (t), then it is straightforward to observe that the output is y(t) = aVLO cos θLO + aVIF cos θIF (i.e., it has the same frequency content of the input). On the other hand, any nonlinear system will lead to frequency mixing. To demonstrate this, the

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Figure 3.3

Response of a general nonlinear system.

Figure 3.4

Spectrum of the quadratic response of (3.11).

nonlinear system of Figure 3.3 can be expressed in terms of a reduced polynomial expansion: y(t) = a1 x(t) + a2 x(t)2 + a3 x(t)3 (3.7) and the same two-tone input can be applied, and each term of the polynomial calculated separately. The linear one is trivial, leading to two tones at the output. The second-order term is x(t)2 = [VLO cos θLO + VIF cos θIF ]2 2 = VLO cos2 θLO + 2VLO VIF cos θLO cos θIF + VIF2 cos2 θIF .

(3.8)

By recalling some notable trigonometric identity (1.2–1.4): 1 1 + cos(2θ) 2 2 1 1 cos θ cos φ = cos(θ + φ) + cos(θ − φ). 2 2 cos2 (θ) =

(3.9) (3.10)

Equation (3.8) leads to: q(t) = x(t)2 =

2 V2 VLO + IF 2 2 2 V V2 + LO cos(2θLO ) + IF cos(2θIF ) (3.11) 2 2 VLO VIF VLO VIF cos(θLO − θIF ). cos(θLO + θIF ) + + 2 2

Equation (3.11) brings up some important observations. First, a quadratic function will lead to a constant, DC, term, and second harmonics of the tones (2fLO and 2fIF ). Second, it will provide the sum and difference terms between the two frequencies as a result of the product term between the two cosines. Figure 3.4 shows the spectrum deriving from a quadratic function of two tones.

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Figure 3.5

Spectrum of the cubic response.

The cubic term can be expanded as c(t) = x(t)3 = [VLO cos θLO + VIF cos θIF ]3 3 = VLO cos3 θLO + VIF3 cos3 θIF 2 = +3VLO VIF cos2 θLO cos θIF + 3VLO VIF2 cos θLO cos2 θIF . (3.12)

By decomposing the higher-order terms in linear and quadratic terms, the trigonometric identities can be used once more: cos3 θ = cos θ cos2 θ 1 1 cos θ + cos θ cos(2θ) 2 2 1 3 = cos θ + cos(3θ) 4 4 1 1 cos2 θ cos φ = cos φ + cos φ cos(2θ) 2 2 1 1 1 = cos φ + cos(2θ + φ) + cos(2θ − φ). 2 4 4 =

(3.13)

(3.14)

The results in (3.13) and (3.14) show that the cubic terms lead to output frequency terms that are not desired; in fact, there are terms at the fundamental and third harmonic of the LO and of the IF and higher-order mixing terms. Moreover, there are the terms θLO ± 2θIF that are particularly critical since they sit near the useful terms θLO ± θIF . Figure 3.5 shows the spectrum deriving from a cubic function. By using (3.11), (3.13) and (3.14), the overall output y(t) can be finally evaluated: y(t) = + Y0,0 + Y1,0 cos θLO + Y0,1 cos θIF + Y2,0 cos(2θLO ) + Y0,2 cos(2θIF ) + Y1,1 cos(θLO + θIF ) + Y1,1 cos(θLO − θIF ) + Y2,1 cos(2θLO + θIF ) + Y2,1 cos(2θLO − θIF )

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Figure 3.6

Spectrum of the polynomial response including linear, quadratic, and cubic terms.

+ Y1,2 cos(θLO + 2θIF ) + Y1,2 cos(θLO − 2θIF ) + Y3,0 cos(3θLO ) + Y0,3 cos(3θIF ) where

 Y0,0      Y1,0       Y0,1       Y2,0 Y0,2    Y2,1      Y1,2      Y3,0     Y0,3

=

a2 2



2 +V2 VLO IF

(3.15)



3 = a1 VLO + 34 a3 VLO + 32 a3 VLO VIF2 2 V = a1 VIF + 34 a3 VIF3 + 32 a3 VLO IF 2 = 12 a2 VLO

= 12 a2 VIF2

(3.16)

2 V = 34 a3 VLO IF

= 34 a3 VLO VIF2 3 = 14 a3 VLO

= 14 a3 VIF3

There are numerous observations that could be made from the derived equations, and the corresponding spectrum shown in Figure 3.6; the most important from a mixer point of view is that only the quadratic term provides the spectral lines of interest, while all the other terms generate unwanted frequencies only. The LO and IF frequencies have contributions from both the linear and cubic terms. However, also the quadratic term generates an output signal at DC and second harmonics. In particular, they derive from the quadratic term of the cosines while the mixing term derives from the product term. This gives an important hint: if the input IF signal is multiplied with the LO signal, a double sideband (DSB) output only will be obtained, as shown in Figure 3.7: cos θLO cos θIF =

1 1 cos(θLO + θIF ) + cos(θLO − θIF ). 2 2

(3.17)

To summarize, two signals can be mixed with a resulting DSB spectrum in at least two ways: 1. By injecting the sum of the two signals into a nonlinear component, in particular a quadratic nonlinearity. There will be a large number of unwanted frequency components that will need to be filtered out.

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Figure 3.7

DSB mixer using a multiplier.

Figure 3.8

DSB mixer using a linear time-variant system.

2. By multiplying the two signals with no unwanted components at the output. In both cases, the output is still a DSB signal, therefore occupying twice the bandwidth that is practically needed. The unwanted sideband will need to be rejected. Finally, it is also possible to achieve mixing with a linear, time-variant system, as shown in Figure 3.8. In fact, the output will be the product of the input and the linear scaling factor A; however, if the system has a time-varying characteristic at the rate of an LO frequency (A(t) = A0 cos θLO ), then the output will be the mixing: vo (t) = VI [cos(θLO + θIF ) + cos(θLO − θIF )] . (3.18) In practice, the linear, time-variant system is a simplified way of modeling nonlinear components whose response to the small-signal input is locally linear, but that are driven under a strong LO signal so that the characteristic changes at the LO rate. For example, a FET switch driven by a LO square wave will appear linear (short or open circuit) to the applied signal, but time-varying at LO rate. 3.1.1 Mixer Figures of Merit This section will discuss the main FOMs that characterize a mixer circuit. Where not otherwise indicated, an upconverter mixer will be considered. The frequency range of a mixer is the range of frequencies where the declared electrical specifications are met. A mixer has three independent frequency ranges, although usually the RF and LO frequency ranges are similar. Regarding the IF frequency range, some mixers are DC coupled so that the IF ranges from zero to a maximum frequency, while AC coupled mixers will have a band-pass IF range. Intuitively, it can be understood that mixers with narrow frequency ranges will have better performance compared to broadband mixers, but will be less flexible. Also, a

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higher frequency of operation for LO and RF normally corresponds also to a wider IF frequency range. The LO signal does not carry information and is often referred to as pump since its function is to provide energy for the frequency conversion. For the correct operation of the mixer, the LO power must be at an optimized level, called LO pump level, normally expressed in decibels per milliwatt (dBm). All other FOMs are provided at the specified LO pump level. The value can range between 0 dBm up to 27 dBm. The conversion gain (Gconv ) is the ratio, normally expressed in decibels (Gconv |dB ), of the power of the output signal at the wanted frequency and the power of the input signal:  PO (fRF ) Gconv |dB = 10 log 10 . (3.19) PI (fIF ) The value of Gconv |dB will be positive in active mixers that consume DC power to provide an output signal with larger magnitude than the input. In passive mixers, Gconv |dB is a negative number, so the term usually adopted is conversion loss (Lconv ) that expressed in decibels becomes a positive number:  PO (fRF ) Lconv |dB = −Gconv |dB = −10 log 10 . (3.20) PI (fIF ) Passive mixers normally show a conversion loss greater than 4 dB to 5 dB in narrowband designs, and 7 dB in broadband designs. Active mixers normally have a gain lower than 10 dB. The gain is difficult to increase in mixers without compromising other FOMs. Therefore, if a higher output level is needed, the only solution is to cascade RF amplifiers in the upconverter chain after the mixer. As has been seen from the mixing analysis, a nonlinear circuit will generally output frequency components that are not wanted, except in the case of a pure multiplier. Most notably, there will be some residual of the LO frequency at the RF port. The LO-RF isolation, normally expressed in decibels, is the ratio between the LO pump power and the output power at the LO frequency. The same performance is expressed sometimes in terms of LO rejection (i.e., the ratio in decibels between the output power at the RF frequency and the output power at the LO frequency). Both figures are normally dependent on the RF power level and frequency; therefore the worst minimum value is normally provided. Similar parameters can be defined for the other unwanted frequencies, for example the LO-IF isolation or the image or sideband rejection. The maximum level of any spurious can also be provided. Contrary to the LO, the IF and RF signals carry information; therefore distortion parameters must be used to characterize the quality of the frequency translation in terms of linearity. If a single-tone test is used to test the linearity, then 1-dB power compression point (P1dB) and third-order intercept point at the input or output

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Figure 3.9

Single-tone test of a mixer to measure distortion parameters. (a) Block diagram, and (b) Po versus Pi curves; x and y scales in decibel.

(IIP3 or OIP3, respectively) are used, and normally expressed in decibels per milliwatt. P1dB represents the limit at which the input power can be driven at before introducing strong nonlinearities, so it can be seen as a hard limit for the use of the mixer. On the other hand, the IIP3 or OIP3 are an idealized extrapolation of the RF and third-order spurious responses (the ones at fLO ± 2fIF ), at low input power (Figure 3.9). Therefore, it provides an indication of the linearity back from the P1dB point. Two-tone test can also be used to characterize the mixer linearity, and in this case the intermodulation distortion parameters (such as carrier-to-third-order intermodulation ratio (CIMR3)) are normally adopted. The noise figure is usually provided as the FOM to describe the noise introduced by the mixer. For passive mixers, the noise figure in decibels equals the conversion loss in decibels. For active mixers, the noise figure mainly depends on the active device technology adopted. Other mixer parameters provided are the reflection loss or matching at the different ports, the temperature ratings, the bias voltage/current in transistor based mixers, and the maximum input power at the ports. 3.1.2 Mixer Architectures Single-component mixers, also refered to as mixer cores, provide a DSB output plus other spurious frequencies, in particular residual LO and IF. They can be passive or active and are based on diodes or transistors. By using a single mixer core, the rejection of unwanted frequencies must rely on the intrinsic characteristics of the nonlinear device and on filters. This might prove particularly critical if some frequency bands of the LO, RF, and IF signals are close or overlapping. By properly combining two cores in a single-balanced mixer, rejection can be achieved without filters. The 180◦ hybrid is a key component in balanced mixer configurations, as shown in the block diagram in Figure 3.10. It is a four-port, reciprocal passive component where the output voltage at ports S and D are,

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Figure 3.10

Symbol and definition of a 180◦ hybrid coupler.

respectively:



√1 (vA + vB ) 2 vD = √1 (vA − vB ) . 2

vS =

(3.21)

Alternatively, center-tap transformers can be used as well to generate sum or difference signals, or balun (balanced to unbalanced transformers) can be used to generate differential signals. Figure 3.11 shows a block diagram of the single-balanced mixer configuration in upconversion. The RF output is proportional to the difference of the currents from the two nonlinear cores vRF ∝ (i1 − i2 ) that are nonlinear functions of the signals applied to the diodes, approximated as

i1 = a1 (VLO cos θLO − VIF cos θIF ) + a2 (+VLO cos θLO − VIF cos θIF )2 i2 = a1 (VLO cos θLO + VIF cos θIF ) + a2 (VLO cos θLO + VIF cos θIF )2 . (3.22) By applying the trigonometric rules previously used, the following is obtained:  a2 2  (VLO + VIF2 ) + a1 (VLO cos θLO − VIF cos θIF ) i1 =    2   a2 2   + (VLO cos(2θLO ) + VIF2 cos 2θIF )   2   a2    − VLO VIF [cos(θLO + θIF ) + cos(θLO − θIF )] 2 (3.23) a2 2 2   i (V = + V ) + a (V cos θ + V cos θ ) 2 1 LO LO IF IF  IF  2 LO   a  2 2  cos(2θLO ) + VIF2 cos 2θIF ) + (VLO    2   a2   + VLO VIF [cos(θLO + θIF ) + cos(θLO − θIF )] . 2 Finally, the RF output is vRF ∝ 2a1 VIF cos θIF + a2 VLO VIF [cos(θLO + θIF ) + cos(θLO − θIF )] (3.24) The spectrum at the RF port, shown in Figure 3.11, contains the DSB upconversion, plus an IF residual. Figure 3.12 shows the same mixer, but used as a downconverter. The current to the IF port is the difference between the currents in the nonlinear components

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Figure 3.11

General schematic (a) of a single-balanced mixer in upconversion, with the output spectrum (b) in the case of a truncated polynomial of the second order.

Figure 3.12

General schematic (a) of a single-balanced mixer in downconversion, with the output spectrum (b) in the case of a truncated polynomial of the second order.

iIF = (i2 − i1 ). The currents are once again a nonlinear function of the applied voltages that can be approximated as

i1 = a1 (VLO cos θLO + VRF cos θRF ) + a2 (VLO cos θLO + VRF cos θRF )2 i2 = a1 (VLO cos θLO − VRF cos θRF ) + a2 (VLO cos θLO − VRF cos θRF )2 . (3.25) Therefore, the resulting currents after trigonometric expansion are  a2 2 2  (V + VRF ) + a1 (VLO cos θLO + VRF cos θRF ) i1 =    2 LO   a2 2  2   + (VLO cos 2θLO + VRF cos 2θIF )   2   a2    + VLO VRF [cos(θLO + θRF ) + cos(θLO + θRF )] 2 (3.26) a2 2 2   i (VLO + VRF = ) + a1 (VLO cos θLO − VRF cos θRF ) 2   2    a2 2  2  + (VLO cos 2θLO + VRF cos 2θRF )   2    a2   − VLO VRF [cos(θLO + θRF ) + cos(θLO − θRF )] . 2

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Finally, the resulting voltage at IF port is vIF ∝ 2a1 VRF cos θRF + a2 VLO VRF [cos(θRF + θLO ) + cos(θLO − θRF )] (3.27) whose spectrum is shown in Figure 3.12. It is clear that this architecture is able to reject the LO but not the RF. Moreover, the signal at the image frequency is downconverted a the same IF frequency. In case the simultaneous rejection of IF and RF (or LO and RF) is desired, then double-balanced mixers (DBMs) can be used, as shown in the block diagram in Figure 3.13 for an upconverter. The output at the RF port is proportional to the difference of the branch currents vRF ∝ (iB1 −iB2 ), with each branch currents being the sum of the currents from the respective diodes:
iB1 = i1 − i4 (3.28) iB2 = i2 − i3 , that results into vRF ∝ (i1 − i2 + i3 − i4 ). The currents are approximated with the following functions:  i1 = a1 (+VLO cos θLO + VIF cos θIF ) + a2 (+VLO cos θLO + VIF cos θRF )2    i = a (+V cos θ − V cos θ ) + a (+V cos θ − V cos θ )2 IF 2 LO LO IF IF LO IF 2 1 LO  i3 = a1 (−VLO cos θLO − VIF cos θIF ) + a2 (−VLO cos θLO − VIF cos θRF )2    i4 = a1 (−VLO cos θLO + VIF cos θIF ) + a2 (−VLO cos θLO + VIF cos θIF )2 . (3.29)

Figure 3.13

General schematic (a) of a DBM in upconversion, with the output spectrum (b) in the case of a truncated polynomial of the second order.

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It is evident that all the linear terms in (3.29) cancel out. Moreover, the cos2 terms cancel also out and since they are all positive two of them are added, while the other two are subtracted. The mixing terms, instead, have a positive sign in i1 and i3 , and a negative sign in i2 and i4 ; therefore they all sum together with a positive sign, hence being conserved at the output: vRF ∝ [cos(θLO + θRF ) + cos(θLO − θIF )] .

(3.30)

The spectrum at the RF port is shown in Figure 3.13, where it is shown that only the double-side converted signals are present. Figure 3.14 shows the schematic and layout for a double-balanced downconverter mixer with corresponding spectrum. The calculations are very similar to the upconversion case, and therefore are not repeated here, and they result in vIF ∝ [cos(θLO + θRF ) + cos(θLO − θRF )] .

(3.31)

The first term in (3.31) is at very high frequency; therefore it is filtered out easily, while the second term is the useful IF term. However, if θLO > θRF or θLO < θRF , the useful IF term is always cos(θLO − θRF ); this means that both the RF and its image are downconverted to the same IF frequency. Therefore, this architecture does not reject the image frequency. The obtained results are also valid with higher-order linearities, but the quadratic approximation has been used for simplicity. To summarize: • A single cell mixer will provide the wanted mixing products plus all the unwanted spurious;

Figure 3.14

General schematic (a) of a DBM in downconversion, with the output spectrum (b) in the case of a truncated polynomial of the second order.

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• A single-balanced mixer uses two nonlinear elements and can cancel out either the LO or the IF in upconversion (either LO or RF in downconversion). • A DBM uses four nonlinear elements and can cancel out both LO and IF in upconversion (both LO and RF in downconversion). 3.1.3 Switching Mixers The demonstration provided with LO as a single-tone stimulus is very intuitive since it provides results directly from basic trigonometric rules. However, in practice, the LO signal is often used as a command signals for nonlinear elements used as switches. From a mathematical point of view, it means that now the LO signal is represented by a square wave (Figure 3.15), but the mixer function is still that of a multiplication. To approach the calculations in a similar way to what was done until now, the new LO signal can be expressed using a Fourier series; in particular, a square has odd harmonics and, in the example of Figure 3.15, only the cosine components [11]: ∞ 1 2  (−1)(n−1) vLO (t) = + cos [(2n − 1)θLO ] . 2n − 1 2 π

(3.32)

n=1

If the upconverter case is considered, the output at the RF port will be vIF (t) ∝ + V0 cos(θIF ) ∞ 1  (−1)(n−1) {cos [(2n − 1)θLO + θIF ]} + π 2n − 1

+

1 π

n=1 ∞  n=1

(3.33)

(−1)(n−1) {cos [(2n − 1)θLO − θIF ]} . 2n − 1

Therefore, the output spectrum will be comprised of the wanted RF components plus a number of copies of the double sideband signal around the odd harmonics

Figure 3.15

Upconversion mixer using a multiplier and a square-wave LO equivalent to a switching mixer.

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of the LO. The amplitude of those will follow the decay of harmonics of a square wave that is of 20 dB per decade. Being the harmonic components low in power and reasonably distanced from the useful frequency, they are normally quite easy to filter out. Therefore, the switched mixer is effectively used in practice. Note that, the residual IF comes from the DC component of the square wave; by applying a zero-DC square wave the residual IF can be rejected, which corresponds in practice to a balanced configuration. Figure 3.16 shows the schemes of principle of switching mixers in single-ended, single-balanced, and double-balanced configuration. Finally, if the product between the input and an LO harmonic different from the fundamental is selected, then the mixer is called a harmonic or subharmonic mixer. This approach is quite common for millimeter-wave mixers. 3.1.3.1 In-Phase and Quadrature (I/Q) Mixers: Single Sideband and Image Rejection

The I/Q mixer is composed by two mixer cells, normally double-balanced, whose LO is provided with a 90◦ shift between the two, as shown in Figure 3.17. The IF ports of the mixer are fed by independent I/Q signals and the RF ports are summed together in an upconverter, while in a downconverter the RF is split equally to the two RF ports and the I/Q signals are collected at the IF ports. The LO is distributed to the two branches of the transmitter with a 90◦ difference,

Figure 3.16

Upconversion mixers using switches. (a) Single-ended, (b) single-balanced, and (c) double-balanced.

Figure 3.17

I/Q mixer used as a vector modulator/demodulator. (a) TX structure, and (b) RX structure.

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Figure 3.18

103

Symbol and definition of a 90◦ hybrid coupler.

providing the orthogonal base on which the I/Q signals can be transmitted using the same spectrum resources and without interfering with each other. The 90◦ delay is achieved by using a 90◦ hybrid coupler (Figure 3.18), whose constitutive relation, in terms of phasors, is 

1  V0 (f ) = √ VA (f ) − jVB (f ) 2 (3.34)

1  V−90 (f ) = √ −jVA (f ) + VB (f ) . 2 If the IF is DC-coupled, the I/Q mixer can be used for direct I/Q modulation from baseband I/Q signals to an RF frequency (quite common in RF transmitters), or as a first step in a heterodyne upconverter (a choice normally implemented at very high frequency, for example millimeter-wave). Also, the downconverter structure can be used as I/Q demodulator. The demonstration of the use of I/Q mixers to transmit two independent signals is quite straightforward. Once again, assuming single-tone stimuli for simplicity,   vLO (t) = VLO cos(θLO ) vI (t) = VI cos(θIF ) (3.35)   vQ (t) = VQ cos(θIF ). The output of the upconverter is the sum from the two branches that are the products between LO and I or Q signals, respectively, where is it easy to see that cos(θLO − π/2) = sin(θLO ): vRF (t) ∝ VI cos(θIF ) cos(θLO ) + VQ cos(θIF ) sin(θLO ).

(3.36)

The signals received by each branch of the downconverter are then

vRX,I (t) ∝ +VI cos(θIF ) cos(θLO ) cos(θLO ) + VQ cos(θIF ) sin(θLO ) cos(θLO ) vRX,Q (t) ∝ VI cos(θIF ) cos(θLO ) sin(θLO ) + VQ cos(θIF ) sin(θLO ) sin(θLO ). (3.37) By simple trigonometric expansion, the received I signal is 1 vRX,I (t) ∝ + VI cos(θIF ) 2

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1 + VI [cos(2θLO + θIF ) + cos(2θLO − θIF )] 4 1 + VQ [sin(2θLO + θIF ) + sin(2θLO − θIF )] 4

(3.38)

while the Q signal is 1 vRX,Q (t) ∝ + VQ cos(θIF ) 2 1 − VQ [cos(2θLO + θIF ) + cos(2θLO − θIF )] 4 1 + VI [sin(2θLO + θIF ) + sin(2θLO − θIF )] . 4

(3.39)

It is now clear that a low-pass filter is needed in order to remove the higherfrequency components and complete the I/Q reconstruction. In a DBM, the output of the upconverter will still contain both sidebands; this means the usage of double spectrum resources compared to what would be really needed. At the same time, if used as a downconverter, the mixer will downconvert both sideband, the one at the RF frequency, and also the one at the image frequency, increasing the noise at IF port. To avoid these issues, an I/Q mixer can be used to reject one of the sidebands or the image. Figure 3.19 shows the use of the I/Q mixer as an SSB upconverter. The IF signal is also split through a 90◦ hybrid coupler, therefore providing


vI = VIF cos θIF vQ = VIF sin θIF

(3.40)

to the I/Q mixer. Its output becomes vTX (t) ∝ cos(θIF ) cos(θLO ) + sin(θIF ) sin(θLO ) = cos(θLO − θIF )

Figure 3.19

(3.41)

SSB upconverter using I/Q mixer. (a) Block diagram, and (b) spectral content.

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that is by definition an SSB signal. To obtain the other sideband, it is sufficient to swap one of the two 90◦ hybrid, for example the IF one:
vI = VIF cos θIF (3.42) vQ = −VIF sin θIF and, as a result: vTX (t) ∝ cos(θIF ) cos(θLO ) − sin(θIF ) sin(θLO ) = cos(θLO + θIF ).

(3.43)

In a downconverter instead, shown Figure 3.20, the IF components before the hybrid are:
vIF,A (t) ∝ cos(θLO − θRF ) (3.44) vIF,B (t) ∝ − sin(θLO − θRF ). In the case with RF frequency larger than LO frequency, therefore with θIF = θRF − θLO , the two signals become
vIF,0 (t) ∝ cos θIF (3.45) vIF,90 (t) ∝ sin θIF , and by considering that cos(θ − π/2) = sin θ and sin(θ − π/2) = − cos θ, the two outputs of the hybrid are
vIF,A (t) ∝ cos θIF − cos θIF = 0 (3.46) vIF,B (t) ∝ sin θIF + sin θIF = 2 sin θIF . On the other hand, in the case with LO frequency larger than the RF one, the outputs are
vIF,A (t) ∝ cos θIF + cos θIF = 2 cos θIF (3.47) vIF,B (t) ∝ − sin θIF + sin θIF = 0.

Figure 3.20

Image rejection mixer using an I/Q mixer. The sideband of interest can be selected at the output of the IF 90◦ hybrid.

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Therefore, the output at port A will only contain the downconverted energy from the lower sideband and no energy from its image, while the signal at port B will only contain the energy from the upper sideband and nothing from its image. 3.1.4 Diode Passive Mixers The simplest nonlinear component used for building mixers is the diode. The Schottky equation provides the relation between current iD and voltage vD in a diode:   v (t) D ηV T −1 , (3.48) iD (t) = IS e with IS reverse saturation current, η ideality factor, and VT thermal voltage. The exponential in (3.48) can be approximated with its Taylor expansion, resulting in     vD (t) 1 vD (t) 2 1 vD (t) 3 iD (t) ≈ IS + + + ... (3.49) ηVT 2 ηVT 6 ηVT making evident the polynomial terms and allowing us to apply all the considerations given when studying the general polynomial of (3.7). A singlediode mixer can be built as in the Figure 3.21. Being that diode is a two-terminal element, it is characterized by a unique voltage. Therefore, the only way to separate the LO, RF, and IF signals in this case is by using filters. Figure 3.22 shows possible realizations of single- and double-balanced diode mixers using hybrids or transformers. The DBM is also known as diode-ring mixer; if used with a square-wave LO, its behavior can be explained following the schematics in Figure 3.23. Assuming an upconverter when the LO is positive, diodes 1 and 2 are ON only, and therefore the IF finds a path to ground through the inverted side of the RF transformer, changing polarity on the RF port. When the LO is negative, diodes 3 and 4 are ON only, and the IF flows to ground coupling to the IF port with same polarity. Therefore, the overall behavior is that of multiplication between IF signal and the LO square wave. There is another family of frequency translation circuits based on a diode that is worth mentioning, called AM diode detectors. They are also known as crystal detectors since in their first implementations they were realized by attaching an electrode on a piece of crystal, creating a sort of metal-semiconductor junction. As discussed in Section 1.1, the most popular was the cat whisker detector, named

Figure 3.21

Block diagram of a single-diode mixer. Input: vD ; output iD .

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Figure 3.22

Block diagrams of balanced diode mixers using hybrid (a,c) and transformers (b,d).

Figure 3.23

Operation of a diode-ring mixer used in switching operation during the positive and negative cycles of LO.

after the very thin wire used as an electrode, and based on a lead sulfide crystal, known as galena. A schematic of AM detectors is shown in Figure 3.24; these detectors became incredibly successful in the first radio implementations for their great simplicity, since no LO signal was needed and they required a minimal amount of components. The circuit works effectively as an AM detector when it operates as a half-wave rectifier, with a low-pass filter at the output, with the great advantage of not needing any battery to operate. However, the signal received by radios is often very weak, therefore the diode operation has a dominant quadratic effect that makes it nonlinear. Therefore, considering the amplitude-modulated signal x(t) = G(t) sin(θRF )

(3.50)

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Figure 3.24

Block diagram (a) and possible circuit implementation (b) of an AM detector.

where G(t) varies at much lower rate than the RF signal, it is easy to see that the filtered detector output will be approximately 1 y(t) ≈ (G(t))2 . 2

(3.51)

Does this mean that the AM detector is in reality not an amplitude, but a power detector, therefore introducing a huge distortion? In reality, yes and no, because AM signals were generated with a low modulation depth. For example, assuming a single tone at the AM modulation frequency (that was normally an audio frequency, fAM ), the modulated signal was actually created as G(t) = C (1 + m cos(2πfAM t))

(3.52)

with m the modulation index, and C the carrier power. Therefore, applying the quadratic equation once more: y(t) ≈

     C 2  2 + m2 + 4m cos(2πfAM t) + m2 cos(4π fAM t) , 4

(3.53)

from which it can be noted that for m 1, even. An =  2 (3.63) π n −1 2 For example, the second harmonic amplitude is A2 = 3π . This means that, even in the best case of no added losses, a doubler realized with a half-wave rectifier will have a loss of ≈ 13.5 dB. On the other hand, to generate odd harmonics, squaring of the waveform is sought, therefore the diode is used as a clipping device instead of a rectifier (see Figure 3.45(b)). It is interesting to note that in order to have a good evenorder multiplier that generates the lowest amount of odd-order components, a diode with the lowest forward turn-on voltage is preferred. On the other hand, if used as a clipping device, the low-voltage diode would definitively lead to a small output power of the odd-mode multiplier. For this reason, diodes in series can be employed, as depicted in Figure 3.45(b). For low-frequency applications, Zener diodes can also be used to increase the magnitude of the clipped signal. Assuming a square waveform is realized, the odd harmonics only are present, and their amplitude is normalized to the amplitude of the square wave:

An =

4 πn

n > 1, odd.

(3.64)

Doublers are the most common type of multiplier realized with diodes at RF and microwave frequencies due to the efficacy of diodes to act as rectifiers

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Figure 3.46

Half-bridge (a) and full-bridge (b) rectifiers used as frequency doublers.

compared to as limiters. In particular, as shown in Figure 3.46, half- and fullbridge rectifiers are normally adopted to realize these designs since they provide full-wave rectifier. The normalized amplitude of the nth order even harmonic is An =

π

4



n2



−1

n > 1, even,

(3.65)

meaning that the ideal conversion loss is ≈7.4 dB that compared to half-wave rectifiers is 6 dB better. The full-bridge solution has the advantage of not requiring a center-tap transformer, and therefore it is better suited for very high frequency applications where a balun can be used to realize the transformer. These doublers are generally quite broadband, since they are based on a resistive effect in the diode, but their practical loss is quite high, normally around 10 dB. Diodes have a varactor behavior, generating harmonics due to the nonlinear relationship between charge and applied voltage; this effect is still present even at frequencies so high that the diode stops working as a rectifier. Therefore, a third way of using diodes for frequency multiplication is as varactor multipliers instead of resistive multipliers. The main advantage of varactor multipliers is the lower loss, particularly important where power is precious as at extremely high frequency. On the other hand, they need to be tuned very carefully to resonate at the right output frequency, and therefore they are very narrowband and, as a consequence, highly sensitive to fabrication tolerance of the diodes and the other components. A way of employing varactors in multipliers is by building nonlinear transmission lines (NLTL); an example is shown in Figure 3.47. A simple explanation of the operation of nonlinear transmission lines is by thinking of a reinforcing distortion effect along the transmission line. As the single tone is injected at the input of the NLTL, a wave will travel along the line and each varactor will add up an amount of distortion, practically sharpening the wave and approximating a sequence of pulses at the output. From a theoretical point of view, a periodic sequence of Dirac’s delta in the time domain will lead to Dirac’s delta in the frequency domain with constant amplitude and at the harmonics of the repetition frequency. If the pulse widens its duration and its edges are smoothed, the higher harmonics are attenuated. Having more sections for the same length of line increases the maximum frequency of operation of the NLTL; however, since

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Figure 3.47

NLTL frequency multiplier realized with lumped elements (inductors and varactor diodes).

Figure 3.48

Frequency multiplier realized with SRD.

real varactor have a resistive parasitic effect, it leads to higher losses. Therefore, a compromise must be sought between maximum frequency and loss. The fourth way of using diodes as multipliers is also a method of generating very sharp, short pulses through a step-recovery diode (SRD). An SRD is a p − n junction with a graded doping profile that is minimum at the junction. This means that the recovery time of the diode is extremely quick compared to a normal diode. In particular, if an alternate signal at high frequency is applied, the diode will accumulate charges in the depletion region during the positive cycles. When passing to the negative cycle, a small amount of charge will need to move from the junction by flowing in the opposite direction, meaning that for a short time the diode will conduct in the negative cycle as well. However, as soon as the charge is exhausted, the current stops suddenly, giving rise to a very sharp negative voltage pulse. Therefore, the SRD can be used to generate a sequence of very sharp pulses in what is called a comb generator. By filtering the wanted harmonic, a frequency multiplier is achieved; see the implementation example in Figure 3.48 where the circuit symbol of an SRD can be noted. An example of diode doubler is the MMD-2060L from Marki Microwave [5]. It operates in the output frequency range of 30 GHz to 60 GHz, with a typical conversion loss of 12 dB across the operation band. The input can range between 3 dBm and 10 dBm, with an harmonic rejection for f0 and 3f0 around 40 dB and of 14 dB for 4f0 . The component can be acquired both as a die chip or as a module with coaxial connectors. Another example of diode frequency multiplier is the family of quadruplers LNDQ from Wenzel Associates Inc. [2]. They are based on two passive doubler

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stages, each followed by a buffer amplifier; as a result, the net conversion loss is 0 dB. The frequency options available are up to 1 GHz for the output, and the operation is optimized for an input of 13 dBm. These quadruplers are optimized for minimum phase noise; in fact they provide a residual phase noise, when referred to the input, between −170 dBc/Hz and −176 dBc/Hz at 1-kHz offset. 3.2.4 Transistor-Based Frequency Multipliers Transistor multipliers are normally active, therefore have positive conversion gain. They can be studied effectively as a nonlinear amplifier; in fact, they are very similar to power amplifiers, except that the input is matched at f0 while the output is matched at Nf0 and includes a filter to reject the other harmonics (see the schematic in Figure 3.49). This way, the output power at the harmonic of interest is maximized. The amplitude of harmonics can be controlled by changing the conduction angle of the transistor, in practice by changing class of operation as discussed for power amplifiers in Chapter 2. It is not surprising that most of transistor frequency multipliers operate in class B (for even-mode harmonics) or C (for even- and odd-mode harmonics) that are the classes with the richest harmonic content. Moreover, for odd harmonics, the amount of harmonics will increase considerably if the device is pushed well into compression, leading to hard clipping of the current waveform to result in a square-wave approximation. Figure 3.50 shows an example of circuit implementation of a FET frequency doubler using a self-biasing network that allows to operate the multiplier with a single positive DC supply. The resistor connected to the source raises the source potential making the gate-to-source voltage negative, while the capacitance shunts the resistor minimizing the source impedance at high frequency. From a design point of view, there are many tricks and solutions to optimize the conversion gain, minimize the DC power consumption, and reject the unwanted harmonics. More details and examples of active frequency multipliers design can be found in [9]. An example of commercially available active multiplier is the MAFC004403 doubler from Macom [3] that operates at an output frequency of 16 GHz to 24 GHz and it is used to distribute the LO signal in point-to-point microwave radios. The output power is 20 dBm for an input between 0 dBm and 6 dBm, meaning a conversion gain up to 20 dB, while the DC supply is 7 V, 140 mA. The

Figure 3.49

Active frequency multiplier realized with a transistor.

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Figure 3.50

127

Example of active frequency doubler realized with a FET using a self-biasing network.

f0 rejection is around 30 dB across the operation band, while the 3f0 rejection is 15 dB in the worst case. Another example of commercial frequency multiplier is the SFA753114616-10SF-E1 6× multiplier from Sage Millimeter Inc. [13]. This component is sold as a module with waveguide output to accommodate the output frequency range of 75 GHz to 110 GHz, while the input is coaxial. The typical output power is of 16 dBm, and the conversion gain is of 13 dB. Biased at 7 V, it consumes 550 mA, providing an harmonic rejection of at least 15 dB.

References [1]

500 MHz Four-Quadrant Multiplier, rev. F, https://www.analog.com/media/en/technicaldocumentation/datasheets/AD834.pdf.

[2]

Diode Quadrupler (LNDQ), http://www.wenzel.com/model/diode-quadrupler-lndq/.

[3]

Frequency Doubler 16–24 GHz Output, rev. V2, https://cdn.macom.com/datasheets/ MAFC-004403.pdf.

[4]

Frequency Mixer wide band MAC-42+, rev. G, https://ww2.minicircuits.com/pdfs/MAC42+.pdf.

[5]

GaAs MMIC Millimeter Wave Doubler, rev. A. URL: https://www.markimicrowave.com/ Assets/datasheets/MMD-2060L.pdf?v=110518.

[6]

Gardiner, J. G., and M. A. M. Ali Zaid. “Parametric Upconvertors as Receiver First Mixers at High Frequencies,” Proceedings of the Institution of Electrical Engineers, Vol. 121, No. 5, May 1974, pp. 324–332, DOI: 10.1049/piee.1974.0064.

[7]

HMC207AS8/207AS8E, GaAs MMIC SMT Double-Balanced Mixer, 0.7–2.0 GHz, v01.0112, https://www.analog.com/media/en/technical-documentation/data-sheets/ hmc207a.pdf.

[8]

Maas, S. A., “A GaAs MESFET Mixer with Very Low Intermodulation,” IEEE Transactions on Microwave Theory and Techniques, Vol. 35, No. 4, April 1987, pp. 425–429, DOI: 10.1109/TMTT.1987.1133665.

[9]

Maas, S. A., Nonlinear Microwave and RF Circuits, Norwood, MA: Artech House, 2003.

Del-Corso:

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[10]

Magierowski, S., et al. “RF CMOS Parametric Downconverters,” IEEE Transactions on Microwave Theory and Techniques, Vol. 58, No. 3, March 2010, pp. 518–528, DOI: 10.1109/TMTT.2010.2040332.

[11]

Oppenheim, A.V., A.S. Willsky, and S.H. Nawab, Signals and Systems, Prentice Hall, 1997.

[12]

SA602A Double-Balanced Mixer and Oscillator, rev. 3, https://www.nxp.com/docs/en/datasheet/SA602A.pdf.

[13] W-Band, X6 Active Frequency Multiplier, 75 to 113 GHz, +16 dBm Pout, https:// www.sagemillimeter.com/content/datasheets/SFA-753114616-10SF-E1-1.pdf. [14] Yhland, K., N. Rorsman, and H. H. G. Zirath, “Novel Single Device Balanced Resistive HEMT Mixers,” IEEE Transactions on Microwave Theory and Techniques, Vol. 43, No 12, December 1995, pp. 2863–2867, DOI: 10.1109/22.475647.

Selected Bibliography Gunnarsson, S., D. Kuylenstierna, and H. Zirath, “A 60 GHz MMIC pHEMT Image Reject Mixer with Integrated Ultra Wideband IF Hybrid and 30 dB of Image Rejection Ratio,” 2005 Asia-Pacific Microwave Conference Proceedings, Vol. 1, December 2005, DOI: 10.1109/APMC.2005.1606255.

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4 Phase-Locked Loops: Operation, Circuits, and Applications

The PLL is a key component of communication systems. It is used to generate, synchronize, and demodulate many types of signal, both in the analog and in the digital domains. This chapter describes the structure and the operation of a PLL system, identifies the relevant parameters, and provides examples of the many applications of PLLs. The overall goal is to make a possible motivated selection of devices or subsystems for PLL specific applications. The transceiver used as reference for this book needs signals with precise and stable frequencies, in some cases related to the input signal parameters (amplitude, frequency and phase). These signals cannot be obtained with free-running oscillators, because they cannot provide the required stability or—for some applications—a defined phase or frequency relation with other signals. This chapter analyzes the PLL starting from its working principle, discussing its block diagram and functional units (Section 4.1). Then, it moves to the analysis of operation and definition of relevant PLL parameters (Section 4.2). In Section 4.3 examples are given of circuits for each functional unit: phase detector (PD), voltage-controlled oscillator (VCO), and LPF. Applications for signal processing, demodulation, timing recovery, synthesizers, and DDS are presented. A more detailed analysis can be found in [3].

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4.1 Analysis of PLL Systems This section defines the PLL behavior in the phase and in the frequency domains. The most relevant parameters are identified and discussed for the various loop configurations.

4.1.1 Definition of PLL The PLL can generate a signal vo (t) with specified phase or frequency relations with respect to an input signal vi (t). The input signal can be affected by heavy noise or adopt some type of modulation, but the local signal rebuilt through the PLL has well defined phase, frequency, and amplitude parameters. All oscillators (or any signal source) exhibit tolerance and drift; two separate oscillators, even with nominally equal parameters, cannot provide exactly the same frequency. Figure 4.1 clarifies how a PLL can be seen as a narrowband filter, which removes wideband noise, distortion components, and unwanted signal modulation. This result is easy to understand for analog signals, but the same concept can be applied to digital signals (square wave or pulses). Some preliminary remarks are required before starting the analysis presented in this section. Let x(t) = sin(θ(t)) be a generic sinusoidal signal. Then, its angular frequency ω(t) and its instantaneous phase θ(t) are related: ω(t) is the temporal derivative of θ (t): ω(t) =

dθ(t) dt

(4.1)

and conversely the instantaneous phase can be obtained integrating the angular frequency:
t θ (t) = θ0 + ω(t)dt. (4.2) 0

Figure 4.1

Examples of input (noisy) signal vi and rebuilt (clean) signal vo in the (a) time domain and in the (b) frequency domain.

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Figure 4.2

(a) PLL symbol and (b) block diagram with functional units. PD: phase detector; LPF: loop filter; VCO: voltage-controlled oscillator; Vi : input voltage; Vd : phase detector output voltage; Vc : VCO control voltage; Vd : VCO output.

If θ (t) exhibits a linear variation with respect to time, then ω = ωc is a constant, and the well known expression x(t) = sin(ωc t + θ) can be used; θ is the phase of the sinusoidal signal1 . In general, if θ (t) contains a term that linearly varies with respect to time, plus other terms, we can write x(t) = sin(ωc
t + θ
(t)) with θ
(t) = θ(t) − ωc
t. In this case, however, ωc
is not the temporal derivative of the instantaneous phase anymore. This possibility to expand the instantaneous frequency in different, equivalent, ways will be used in the following to analyze the static and dynamic properties of the PLL. If two sinusoidal signal (e.g., xa = sin(θa (t)) and xb = sin(θb (t))), share the same instantaneous frequency, then they are locked, and their instantaneous phases can only differ by a constant shift: ωa (t) = ωb (t)

⇐⇒

θa (t) = θb (t) + constant.

(4.3)

4.1.2 PLL Linear Analysis As shown in the block diagram in Figure 4.2, the key signals in the PLL system are: • the input (external) signal vi (t) = Ai sin(θi (t)); • the output signal (from the VCO) vo (t) = Ao sin(θo (t)). with θi (t) and θo (t) time dependent instantaneous phases of the two signals. The phase error θe (t) is θe (t) = θi (t) − θo (t)

(4.4)

which in the Laplace s-domain reads θe (s) = θi (s) − θo (s).

(4.5)

1The instantaneous phase θ (t) is often shortly indicated as “phase”, the context helps clarifying

if this term indicates either θ (t) or θ.

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The PD output signal Vd (s) is a function of θe (s). As a first approximation, the PD output is assumed to depend linearly on θe through the PD gain Kd : Vd (s) = Kd θe (s).

(4.6)

The LPF can be a passive network but may also include active devices; its transfer function is indicated as F (s). The filter receives in input the signal Vd (s) and provides in output Vc (s) = Vd (s)F (s). The VCO generates a local signal Vo (s), with a frequency related to the control signal Vc (s); as a first approximation, the angular frequency of the signal at the VCO output is supposed to linearly depend on Vc (s) through the VCO gain Ko : ωo (s) = ωo,r + Ko (Vc (s) − Vc,r ). (4.7) The following analysis assumes the resting value Vc,r = 0, but this assumption is not mandatory. Using the above relations it is possible to define the loop gain in the frequency domain GL (s) = Kd Ko F (s) and the DC loop gain GL (0) = Kd Ko F (0). Thank to the properties of the Laplace transform, (4.1) can be written in the s-domain as ωo (s) = sθo (s) (4.8) and, using (4.4)–(4.8) it is possible to retrieve the VCO instantaneous phase θo (s): Ko Kd F (s) θo (s) = θi (s) . (4.9) s + Ko Kd F (s) For a PLL, the input signal is the instantaneous phase θi and the output signal is the instantaneous phase θo ; the PLL transfer function is therefore H (s) =

θo (s) Ko Kd F (s) = . θi (s) s + Ko Kd F (s)

(4.10)

The degree of the polynomial in the denominator of H (s) defines the PLL order. The phase gain from θi to θe is θe (s) s . = s + Ko Kd F (s) θi (s)

(4.11)

From (4.10), the phase error θe (s) = θi − θo can be written as θe (s) = θi − θo = θi (1 − H (s))

(4.12)

When the terms θe and θo have the same denominator as H (s), therefore the same parameters apply for time and frequency responses: for second order systems, they are the damping ζ and the resonant pulsation ωn . The PLL is locked when ωo = ωi . With an input signal having a constant frequency, the phase difference and therefore vd do not change. As ωi changes, also θe and vd are modified. The changes in vd , filtered by the LPF, shift the VCO

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frequency. As long as ωo = ωi , θe and vd changes continuously: in this case, the steady state condition imposes ωo = ωi , which gives a constant θe . The behavior of a PLL is now analyzed starting from a stable state, where the input signal frequency is fixed. The lock keeping mechanism can be summarized as follows. When the VCO and the input signal have the same frequency, the phase shift is fixed, and in these conditions Vd and Vc are DC voltages. If the frequency of the input signal frequency vi is modified, a change occurs in the phase relation between vi (t) and vo (t), which in turn modifies Vd and Vc , and therefore changes the VCO frequency. The loop feedback tunes the VCO to get again ωi = ωo . Therefore, the PLL can be seen also as a phase follower, with a behavior similar to a voltage follower, but operating in the phase domain instead of the voltage domain. This analysis assumes that PD and the VCO operate in linearity, but in most cases they both exhibit a nonlinear transfer function that can be approximated as linear only in a limited range. The linear analysis is a first order approximation to define relevant PLL parameters and behavior. Detailed analysis (and design) of a specific PLL should take into account the actual nonlinearities. 4.1.3 PLL Transfer Function The parameters of the loop filter influences the behavior of the PLL. The most common types of filters are analyzed in the following, assuming a linear operation of both the VCO and the PD. 4.1.3.1 1 – Zero Order H(s): no LPF (Direct Connection)

The simplest PLL configuration is a direct connection of the PD output to the VCO control input (i.e., without LPF), as shown in Figure 4.3(a). This is a first example of loop connection is not used in real systems. Here, F (s) = 1, Vc (s) = Vd (s). The transfer function and the phase errors can be written as Ko Kd s + Ko Kd s . θe (s) = s + Ko Kd θi (s)

H (s) =

Figure 4.3

(4.13) (4.14)

LPF with F (s) = 1 (direct connection). (a) F (s): no filter, and (b) phase transfer function |H (jω)|.

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Figure 4.4

RC LPF. (a) F (s): first order low-pass, and (b) Phase transfer function.

The LPF transfer function F (s) has order 0; H (s) has order 1, with the low-pass frequency response shown in Figure 4.3(b). This same analysis applies when the LPF has a DC gain: F (0) = Kf ; the gain modifies the position of the loop pole, which moves to Ko Kd Kf . 4.1.3.2 2 – First Order H(s): RC Cell Filter

The simplest type of low-pass filter is the RC cell in Figure 4.4, with transfer function 1 F (s) = . (4.15) 1 + sRC The loop transfer function is H (s) =

Ko Kd 1 1 RC s 2 + s RC +

Ko Kd RC

=

s 2 RC

K o Kd . + s + K o Kd

(4.16)

Equations (4.15) and (4.16) show that the first order LPF leads to a second order low-pass response, as shown in Figure 4.4(b). A second order system is defined by three parameters: • the resonant frequency ωn :

 ωn =

Ko Kd ; RC

(4.17)

• the damping factor ζ : ζ =

1 1 1 = √ ; 2 Ko Kd RC 2RC ωn

(4.18)

• the DC gain H (0) = 1. The system has only two degrees of freedom, namely Ko Kd and RC , therefore it is not possible to get independent values for ωn , ζ , and H (0). 4.1.3.3 3 – First Order H(s): R-RC Cell Filter

A second type of order 1 filter is obtained with the R − RC circuit shown in Figure 4.5. The new resistor R2 provides an additional degree of freedom, and now the transfer function can be designed with independent resonant frequency

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Figure 4.5

R − RC LPF. (a) F (s): order 1 pole-zero low-pass, (b) effect of damping ζ on the transfer function, and (c) effect of resonant frequency ωn on the transfer function.

and damping. This is the most widely used type of LPF. The filter transfer function F (s) and the loop transfer function H (s) can be written respectively as sR2 C + 1 s(R1 + R2 )C + 1 K o Kd . H (s) = 2 s RC + s + Ko Kd F (s) =

(4.19) (4.20)

The loop transfer function H (s) is similar to the one presented in (4.16) for the RC case, but now the additional degree of freedom on R2 allows to set independently R, C , K0 Kd and R2 , and as a consequence gain, damping and frequency:   Ko Kd 1 1 R2 C + (4.21) ζ = 2 Ko Kd (R1 + R2 )C  Ko Kd ωn = (4.22) (R1 + R2 )C H (0) = 1

(4.23)

4.1.3.4 4 – Filter with Gain: Active RC Cells

The previous filter cells do not use active elements, therefore their DC voltage gain can not be larger than 1. An active element with F (0) > 1 reduces the steady state phase error. Examples of LPF with DC gain provided by an operational amplifier are shown in Figure 4.6. For these configurations, the DC filter gain F (0) is negative; the stability requires a negative feedback loop, and the overall feedback sign depends on PD, LPF, and VCO (i.e., Kd , Ko and F (0)). A sign inversion in the LPF transfer function can be compensated by a shift of the PD operating point (provided that the PD has branches with opposite polarity). The circuits in Figure 4.6 show a first order transfer function, leading to a second order H (s), with two free parameters, namely R2 /R1 and R2 C ; the

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Figure 4.6

Filters with operational amplifiers. (a) F (0) = −R2 /R1 , (b) F (0) → ∞, assuming an ideal amplifier, and (c) F (0) → ∞, with pole-zero frequency response.

Figure 4.7

Charge pump filter for the Finite State Machine phase detector. A and B are the commands from the PD logic. (a) Charge pump with current sources, and (b) charge pump with RC cell.

(b) and (c) configurations receive DC feedback through the VCO-PD loop (as standalone circuit their output saturates to the supply rails). As the loop DC gain increases, the phase error θe required to get an assigned ω is reduced: higher loop gains provide lower phase errors. 4.1.3.5 5 – Charge Pump PD Filter

The circuit in Figure 4.7a is a charge pump phase detector. The switches A and B are controlled by the signals vi and vo , as shown in Figure 4.8. The switch A is closed by the rising edge on vi and opened by the rising edge of vo . The reverse applies for switch B, as shown in the timing diagram of Figure 4.8. The capacitor C is charged when A is closed, and discharged when B is closed. When edges of vi and vo are aligned, both switches are always open, and the charge on the capacitor is not modified. If there is an edge misalignment charges are injected (or removed) into C . The voltage on C can remain constant only when edges are aligned (phase error is 0). This PD can be realized as a finite state machine (FSM), which drives an integrator. Any phase error modifies the charge of the capacitor: lead pulses move the integrator up, while lag pulses drive the integrator down. With no phase shift,

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Figure 4.8

Charge-pump PFD. (a) vi leads vo , pulses on A have the same duration as the lead, (b) vi lags vo , pulses on B have the same duration as the lag, and (c) synchronized edges, resulting in no pulse on A, B.

the integrator output is not modified. These circuits are well suited for CMOS technology, where good switches and amplifiers with very high input impedance are available. 4.1.3.6 Loop Gain and Phase Error

In the steady state, Vc = Vd F (0); to change ωo , both Vc and θe must change. The ratio between the phase error θe and the control signal Vc depends on Kd and F (0). With very high F (0) (ideal integrator, with DC open loop), it is possible to achieve an output of the integrator Vc  = 0 even when Vd is 0. Therefore an infinite-gain PLL can lock with phase error θe = 0. Two ways to get very high gain have been already discussed, namely the high gain DC amplifier and the charge pump circuits. 4.1.4 Steady State Phase Error This section analyzes the behavior of the PLL for various changes of the instantaneous phase of vi . This first analysis discusses the steady state response (i.e., the phase error θe when the transient is settled and the PLL is again locked). The steady state phase error θe,ss is θe,ss = lim θe (t) t→∞

(4.24)

or, applying the final value theorem [10], θe,ss = lim sθe (s) s→0

(4.25)

which, thanks to (4.11), can be written as s 2 θi (s) . s→0 s + Ko Kd F (s)

θe,ss = lim

(4.26)

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The actual value of the steady state phase error θe,ss depends on the DC loop transfer function F (0) and on the input signal θi (t). Two cases apply for the DC loop gain: F (0) can be either a finite constant value A (A ≤ 1 for passive filter cells, and A > 1 for active cells), or it may be very large (F (0) → ∞), which corresponds to cells with a DC open loop operational amplifier, or switched-capacitor integrator (Section 4.2). In the following analysis, the sinusoidal input signal has a constant frequency and null phase (θi t = ωi t) for t < 0; three basic signal modulations, which cover the most common applications, are considered for t ≥ 0: 1. Phase step (discrete phase modulation); 2. Frequency step, phase ramp (discrete frequency modulation (FM), constant-speed Doppler effect); 3. Frequency ramp, parabolic instantaneous phase (variable-speed Doppler). For each case, the following analysis calculates the steady-state instantaneous phase error associated to the perturbation, showing the input signal first in the amplitude domain (i.e., what can be observed by an oscilloscope), then in the frequency domain (what can be observed with a spectrum analyzer), and finally in the phase domain (that can be observed with a vector signal analyzer). In the former case, to improve the readability, the term proportional to ω (evaluated before the modulation) is removed from the instantaneous phase. 4.1.4.1 Input Signal with a Phase Step

The input signal vi (t) has a phase change θi in t = 0 as shown in Figure 4.9: vi (t) = Ai sin(ωi t + θi hs (t))

(4.27)

with hs (t) unit step function. Such a signal can come from discrete phase modulation (phase-shift keying (PSK)). The phase step does not cause a frequency change. In the s-domain, the instantaneous phase change associated to this variation is θi (s) =

θi s

θe,ss = lim

s→0

(4.28) sθi = 0. s + Ko Kd F (s)

(4.29)

The LPF has no DC attenuation, therefore the steady state phase error θe,ss is always zero. The input signal vi (t), with the input and output frequencies and phases, is presented in Figure 4.9. If the only change in the input signal is the phase, then there is no need to change the VCO frequency. The steady state phase error is always zero, for finite and infinite values of the loop gain.

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139

Figure 4.9

Phase step signals. (a) Input voltage vi (t ), (b) input (ωi ) and output (ωo ) frequency (no change), and (c) input (θi ) and output (θo ) phase.

Figure 4.10

Frequency step signals. (a) Input voltage vi (t ), (b) input (ωi ) and output (ωo ) frequency, and (c) input (θi ) and output (θo ) phase (linear change).

4.1.4.2 Input Signal with Frequency Step (Linear Phase Ramp)

A frequency step can be described introducing a linear phase rotation in the input signal (Figure 4.10): vi (t) = Ai sin(ωi t + ωi hs (t)t);

(4.30)

such frequency shift can occur for relative motion of RX and TX with constant relative speed (Doppler effect), or for discrete FM (FSK), or for frequency misalignment or drift of TX and RX. For the change in the input signal: θi (s) =

ωi . s2

(4.31)

With this input signal, the VCO frequency must be modified to keep the locking. The steady state error is θe,ss = lim

s→0

ωi ; s + Ko Kd F (s)

(4.32)

with finite DC loop gain, F (0) = A and the steady state phase error is θe,ss =

ωi . Ko Kd A

(4.33)

With high loop gain (F (0) → ∞), for example with an operational amplifier in the loop, the steady state phase error θe,ss can be very small and can tend to zero.

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Figure 4.11

Continuous frequency change (ramp). (a) Input voltage vi (t ), (b) input (ωi ) and output (ωo ) frequency (linear change), and (c) input (θi ) and output (θo ) phase (parabolic change).

Table 4.1 Transient Response and Steady State Instantaneous Phase Error for Various Input Signals and Loop Filter Input signal

Filter type

Frequency

Inst. phase

No change Step

Step Linear

Linear

Parabolic

RC, RRC filter

Active, DC gain A

Active, DC gain → ∞

θe = 0 ω θe = K K i

θe = 0 ω θe = K K iA o d θe → ∞

θe = 0 θe = 0

o d

θe → ∞

ω

θe = K K i o d

4.1.4.3 Input Signal with Linear Frequency Ramp (Quadratic Phase Ramp)

Transmitter and receiver with relative motion at constant acceleration (i.e., with linear speed change), generate a Doppler effect with constant frequency change speed. Such a signal corresponds, for instance, to a satellite or a space vehicle with constant acceleration; the phase can be expressed as second order polynomial in t (Figure 4.11): vi (t) = Ai sin(ωi t + θi t 2 hs (t)) θi =

(4.34)

θi s3

(4.35)

1 θi . s→0 s s + Ko Kd F (s)

(4.36)

θe,ss = lim

If the LPF has finite DC gain (F (0) = A) the phase error diverges. An unbounded phase error means that ωi is always different with respect to ωo and therefore the lock is not achieved. With infinite loop gain (F (0) → ∞), the phase error can be written as θe,ss = θi Ko Kd .

(4.37)

For this input signal, the PLL can lock only with infinite DC gain in the loop, or with second order LPF. These results for the various input signals are summarized in Table 4.1.

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141

4.2 Phase-Frequency Behavior The behavior of a PLL can be described by a diagram that plots the frequency ωo of the signal generated locally by the VCO (defined by the control voltage vc ) versus the angular frequency ωi of the input signal vi . This section describes the procedure to get these diagrams, and identifies the key parameters for any PLL through the closed loop analysis, where vc is used to control the VCO frequency. The results are described by the butterfly diagram, a comprehensive view of the PLL behavior which identifies two key parameters, namely the capture range and the lock range. The capture range is the frequency range where an unlocked PLL can get the lock (capture), while the lock range identifies the frequency range where an already locked PLL keeps the lock (lock-in). The lock mechanism is then discussed in detail, considering closed-loop VCO frequency modulation, and the possibility to lock on harmonics (both of input and of local signals). Finally, the effect of noise on the PLL input signal are described, showing how the PLL acts like a BPF with bandwidth defined by the loop parameters. 4.2.1 Loop Analysis and Butterfly Diagram The phase comparator used for this analysis is an analog multiplier. The product vd (t) of two sine waves vi (t) = Ai sin(ωi t + θi ) and vo (t) = Ao sin(ωo t + θo ) at the PD inputs includes both the sum beat ωS = ωi + ωo and the difference beat ωD = ωi − ωo : vd (t) =

Ai Ao sin(ωS t + θi + θo ) + sin(ωD t + θi − θo ). 2

(4.38)

The term with ωS is blocked by the loop low-pass filter, therefore the VCO control voltage vc is only the filtered difference beat: vc (t) =

Ai Ao sin(ωD t + θi − θo )|F (ωD )|. 2

(4.39)

4.2.1.1 Open Loop

In a first step, the loop is open and the VCO is driven by a quiescent voltage Vc,q corresponding to the midrange VCO operating range frequency ωor (Figure 4.12). The input signal Vi is a sine wave with constant amplitude and frequency ωi , which is varied from ω1 ωo,m to ω2  ωo,m . The output from the PD is the difference beat; as ωi changes the difference beat changes from a rather highfrequency value (high difference) to DC (when the input signal and the same frequency) then to high frequencies again. The analysis starts with an input signal at a frequency ωa smaller than ωor . The output from the PD includes the difference and sum beats; the latter is blocked by the low-pass filter.

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Figure 4.12

Open loop analysis. (a) Open loop circuit, and (b) Vd (dotted lines) and Vc envelopes versus input signal frequency.

Figure 4.13

Closed loop analysis. (a) Closed loop circuit, and (b) Vd and Vc envelopes versus input signal frequency, and VCO ωo (Vc ) (inclined line).

The amplitude of Vc after the low-pass filter depends on the beat frequency (i.e the difference ωi − ωo,m ). For sufficiently large differences, the beat is attenuated by the low-pass filter, and the amplitude of Vc is very small; as ωi approaches ωor , the difference beat frequency decreases, as well as the attenuation in the LPF. When the beat is in the band-pass of the filter (i.e, ωi ≈ ωo,m ), no attenuation is observed. As ωi continues to increase above ωor , the difference beat frequency increases and the LPF again attenuates the control signal Vc . An overall plot of the amplitudes of Vd and Vc versus ωi is presented in Figure 4.12b. 4.2.1.2 Closed Loop

The virtual experiment previously described is now repeated with closed loop, as shown in Figure 4.13. In this case, Vc can change the frequency of the VCO according to the VCO characteristic. The analysis starts again with an input signal at frequency ωa far lower than ωor ; the PD generates the sum and the difference beats, and the sum beat is blocked by the LPF. For large frequency differences, the Vc amplitude is very small because the high-frequency beat is attenuated by the low-pass filter. The sequence lock acquisition—lock keeping—loss of lock is outlined in Figure 4.14. As ωi approaches ωor , the difference beat frequency decreases, the attenuation in the LPF decreases, and the amplitude of the control signal Vc increases (region A in Figure 4.14), until the change in the VCO frequency

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Figure 4.14

143

Generation of the butterfly diagram for increasing input frequency ωi . The VCO characteristic corresponds to the dotted line. The gray line and area correspond to the VCO control voltage Vc . A: no lock; B: lock achieved; C: lock keeping; D: lock lost; E: no lock, F: lock lost for decreasing frequency.

allows to obtain ωo = ωi (B). As soon as the lock is achieved, the difference beat becomes a DC, and therefore it is not attenuated by the LPF. If the input frequency continues to increase, the operating point of the VCO moves on the ωo (Vc ) characteristic and the loop remains locked (C); this continues as long as there is enough correction signal Vc , and the maximum frequency of the VCO is reached (D). As the lock is lost, the beat is no longer a DC but becomes a couple of sine waves, attenuated by the LPF (E). To get again the lock, the operating frequency must return into the range defined by intersection of VCO characteristic with the Vc envelope. Once the lock is achieved for decreasing frequency, it is kept till the other extreme of the VCO characteristic is reached (F, symmetric of D in Figure 4.14). The overall Vc (ω) relation builds the butterfly diagram, which describes the PLL operation, and allows to point out several issues: • • • •

Difference between lock achieving and lock loss; Effect of LPF bandwidth on PLL parameters; Relation between VCO parameters and PLL operating range; Limits of PLL operation.

This description applies to slow changes of input frequency; too fast changes may cause lock loss. The lock can be lost (i.e., ωo  = ωi ) for two different reasons: • When the correction Vc is larger than Vc,max (D), • When the input frequency goes outside the VCO range (VCO saturation). As soon as the lock is lost, Vc returns near 0. The same sequence just described occurs whenever the frequency of the input signal moves from a condition where ωi is very large to a condition with small ωi . As ωi approaches ωor , the beat frequency decreases and the amplitude

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Figure 4.15

Complete butterfly diagram. As ωi moves toward ωor , VC and the VCO frequency increase. When the VC amplitude forces ωo = ωi , then the loop can lock (pull-in). When the PLL is locked, Vd is a DC voltage, with no attenuation through the LPF.

of Vc increases. When the VCO command Vc is adequate to bring ωo = ωi , the PLL can lock again, and the lock is maintained till the maximum allowed value of Vc . The complete Vc versus ωi diagram that shows lock acquisition and loss for increasing and decreasing input frequency is called butterfly diagram; an example is shown in Figure 4.15. 4.2.2 Capture Range and Lock Range The butterfly diagram defines two intervals on the ω axis in Figure 4.15: • Capture range (or lock-in): the frequency range where the PLL moves from unlock to lock condition; • Lock range: the frequency range where the PLL remains locked. The lock range depends on the DC loop gain, which in turn depends on Kd , F (0), and Ko . For some types of PDs (e.g., analog PD) the PD gain Kd depends on the signal amplitude. In this case, also the lock range depends on Vi and Vo amplitudes. With digital PDs Kd is fixed; some circuits (e.g., the charge-pump PD) provide a high F (0) → ∞, and this increases the capture and the lock range. In any case, the lock range is limited by the VCO frequency range. The capture range (or pull-in range) is defined as the range where the transition from not-locked (ωo  = ωi ) to locked (ωo = ωi ) state can occur. The capture range depends on the frequency behavior of the loop gain (i.e., on Kd , F (s), and Ko ). With some types of PDs (e.g., charge-pump or ideal integrator), F (0) can be very high (→ ∞), which makes the phase error very small (→ 0). With these circuits the phase errors are accumulated (not averaged), and the

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capture range corresponds to the lock range; in any case both are limited by the VCO nonlinearity. It has to be mentioned that some authors (e.g., [2]) use slightly different definitions: in the lock range, the PLL locks within one single beat; in the pull-in range the PLL locks after a number of beats, and finally in the pull-out range the PLL unlocks. 4.2.2.1 Effect of Parameter Changes

In the butterfly diagram, the vertical calibration depends on the DC loop gain Kd Ko F (0). The peak value of Vc depends on Kd and F (0), and the VCO slope depends on Ko . Capture and lock ranges depend on all these parameters. Moving the F (s) cutoff frequency modifies the horizontal (x) calibration; this has no effect on Vc (ω) but modifies Vd (ω) and therefore the capture range. 4.2.2.2 Effects of VCO Modulation

The VCO frequency is controlled by Vc , and when the PLL is not locked ωo moves around ωor and the actual beat is ωi − ωo , not ωi − ωo,m . Since ωo changes, the beat frequency ωo − ωi changes as well; as a result the actual Vd signal is a distorted sine wave. As ωo approaches ωo,m , the frequency of the difference beat decreases, and Vd is less attenuated by F (s); the capture range increases slightly. No change occurs for the lock range, since it depends only on DC parameters. This effect is shown in Figure 4.16.

Figure 4.16

Effects of VCO frequency modulation before the capture; the actual beat envelope is represented by continuous lines. The capture range becomes wider; the lock range does not change since it depends only on DC parameters. Continuous line: actual beat in the time domain; with the new butterfly diagram the beat envelope shifts the capture point from B (ω1 ) to B
(ω2 ).

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Figure 4.17

Setup for the experimental measurement of the butterfly diagram.

Figure 4.18

Example of butterfly diagrams with (a) narrow, and (b) wide capture ranges, with PD saturation. Vertical axes: VCO control voltage vc ; horizontal axes: input frequency variation. Both axes are in normalized units.

4.2.2.3 Butterfly Characteristic Visualization

The phase-frequency characteristic can be visualized on a scope using the setup shown in Figure 4.17. The PLL input signal is a sine wave vI , with linear frequency sweep controlled by a ramp (or triangular wave) vT ; this same signal drives the scope x-axis. The VCO control signal vC drives the scope y-axis. For unlocked state, vC contains the sum and difference beats; as soon as lock is achieved, it becomes a DC signal. In order to observe the complete diagram, a sweep with a triangular waveform is recommended. To avoid distortion of the various signals, all scope inputs must be DC coupled. For single-supply PLLs, vC contains a significant DC offset, which must be compensated with a proper oscilloscope setup to obtain an unsaturated diagram. The experiments show the changes in capture (C) and lock range (L) for different LPF parameters (Figure 4.18). The same setup can show secondary lock ranges coming from harmonic lock: the lock here corresponds to 0 beat (DC) between harmonics of Vi and Vo : ωi = ωo , (main lock range), ωi = 3ωo , . . ., as shown in Figure 4.19. Harmonics can be present for Vi and/or Vo because of signal distortion (e.g., sine turned into

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Figure 4.19

Example of butterfly diagrams with (1) main lock and (2) harmonic lock. Same axes as in Figure 4.18.

Figure 4.20

Effect of the PLL as a filter. (a) Low-pass in the phase domain, F (s) = θo /θi , and (b) band-pass in the frequency domain, H (s) = Vo /Vi .

square waves), or they can come from PD multiplier saturation. The zero-beat— and therefore the lock—can occur between any harmonic pair. These are called harmonic lock or secondary lock ranges; an example is shown in Figure 4.19. 4.2.3 PLL Equivalent Noise Bandwidth The PLL is often used to recover or demodulate signals affected by strong noise; this Section analyzes the PLL behavior with noisy input, and introduces the equivalent noise bandwidth, defined as the bandwidth of a filter that provides the same improvement of SNR as the PLL. In comparison with traditional BPFs, the PLL-filter can track signal frequency changes and it provides better control of the bandwidth: the band-pass bandwidth depends on the low-pass LPF transfer function F (s), which can be made as narrow as needed. This behavior is summarized in Figure 4.20, where the PLL basically turns a low-pass filter (the LPF) into a band-pass one, with bandwidth controlled by low-pass cutoff. Noise parameters are defined in the amplitude domain, but the PLL operates on the signal phase, therefore the analysis here is carried out in two steps: 1. Determination of PLL behavior with additive (amplitude) noise at the input;

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Figure 4.21

PLL seen as a BPF. The gray areas indicate noise power spectrum. (a) Input signal power versus frequency, (b) PLL equivalent low-pass effect on input phase, and (c) Filtering effect of the PLL.

2. Definition of the input phase noise that has the same effects (equivalent phase noise). This analysis describes the PLL as a BPF and defines its equivalent bandwidth BL . The output residual noise can be evaluated from BL and from the input SNR. In the following analysis, Ao is the amplitude of the VCO signal. 4.2.3.1 Additive Input Noise

To measure the bandwidth of a filter, it is possible to apply wideband noise with known power density at its input, and to measure the noise power at its output. Assuming a unity gain in band-pass, the input/output power ratio corresponds to the bandwidth ratio. The same approach is used here to find the equivalent bandwidth of the PLL used as a filter, by evaluating the noise power at the PLL output from the input noise power spectral density. The analysis uses a PLL with analog phase detector (e.g., a multiplier); the input signal vi
is a sine wave with angular frequency ωi , plus additive white noise ni (t), with flat power distribution and bandwidth Bi , as in Figure 4.21: vi
(t) = Ai sin(ωi t + θi ) + ni (t).

(4.40)

Usually, the analysis of communication systems provides information on additive noise in the amplitude domain, while the PLL operates on phases. Amplitude must therefore be translated into the phase, in order to obtain the equivalent phase noise θi,n (t) that has the same effects of a known amplitude noise ni (t). The input signal for the PLL is then described as a sine affected by a phase

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noise θi,n : vi (t) = Ai sin(ωi t + θi,n ).

(4.41)

Moving from amplitude noise to phase noise allows to use the already known relations to find the PLL behavior with input noise. In the following, a linear phase detector (or small phase changes) is assumed. The analysis is carried out in the following sequence: • Input signal 1: only noise; compute Vd power Pd,1 ; • Input signal 2: sine wave with phase noise (phase jitter); compute Vd power Pd,2 ; • Evaluate the equivalent phase noise by imposing Pd,1 = Pd,2 ; • Evaluate spectral power density of equivalent phase noise from the closed loop noise power, • Define and evaluate the PLL equivalent noise bandwidth. The equivalent noise bandwidth can be seen as the bandwidth of a BPF on vi (t) which brings a SNR improvement equal to the one provided by the PLL. 4.2.3.2 Noise-Only Input

The first step is to consider as input signal a narrow band noise ni (t), centered at ωor , with bandwidth Bi , determined by the channel or by an input filter, and spectral power density Ni . Such noise can be written in terms of I/Q components [5]: ni (t) = nc cos ωo t + ns sin ωo t.

(4.42)

The phase detector is an analog multiplier, operating in linearity. With locked PLL, ωi = ωo , and the PD output caused by this noise is: v¯d,n (t) = Km Ao cos(ωo t + θo ) [nc cos ωo t + ns sin ωo t] .

(4.43)

The sum beat appearing in (4.43) is removed by the low-pass filter; the remaining difference beat is vd,n (t) =

Km Ao [nc (t) cos θo (t) + ns (t) sin θo (t)] . 2

The Vd power caused by the input noise can be evaluated as   Km Ao 2 2

vd,n (t)  =

[nc (t) cos θo (t) + ns (t) sin θo (t)]2  2

(4.44)

(4.45)

where · indicates the temporal average. The expression in (4.45) can be simplified since the mean of a sum is the sum of means, and, for statistically

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independent terms, the mean of a product is the product of the means:  2  A K m o  nc2 (t) cos2 θo (t)

vd,n (t)2  = 

 2

(4.46)

A

− 2 nc (t) ns (t) cos θo (t) sin θo (t) 



(4.47)

B



ns (t)2  sin2 θo (t) . 



(4.48)

C

Since nc (t) and ns (t) have both zero mean (zero DC value), it follows that the term B in (4.46) is zero. Moreover, for narrowband noise,

nc (t)2  = ns (t)2  = ni (t)2 .

(4.49)

Since sin2 x + cos2 x = 1, the power of vd at PD output with ni (t) noise at input is:   Km Ao 2 2

vd,n (t)  =

ni (t)2 . (4.50) 2 4.2.3.3 Equivalent Phase Noise

In the next step the input signal is a sine wave with phase noise; it is possible to evaluate the phase noise θi,n (t), which has the same effect of the ni (t) noise: vi (t) = Ai sin(ωi t + θi,n (t))

(4.51)

vo (t) = Ao cos(ωo t + θo ).

(4.52)

The signal at PD output in lock condition (ωi = ωo ) is the difference beat between vi (t) and vo (t): vd,n (t) =

Km Ai Ao θi,n (t) 2

and the power of vd at PD output can be now written as   Km Ai Ao 2 2

vd,n (t)  =

θi,n (t)2 . 2

(4.53)

(4.54)

By equating the effects of amplitude noise ni (t) and of phase noise θi,n (t) it is possible to find the equivalent phase noise, which is the phase noise having the same effect as ni (t):     Km Ai Ao 2 Km Ai 2 2

θi,n (t)  =

ni (t)2 . (4.55) 2 2

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The noise power is Pn = ni (t)2  and the signal power is Ps = Ai2 /2; the equivalent phase noise can be written as

θi,n (t)2  =

ni (t)2  Pn = . 2 2Ps Ai

(4.56)

The noise spectral power density considering Bi bandwidth is Ni =

ni (t)2  , Bi

(4.57)

while the phase noise spectral power density  (on Bi /2 bandwidth) is: =

ni (t)2  2 Ni

θi,n (t)2  = = 2 2. 2 Bi /2 Ai Bi Vi

(4.58)

The amplitude noise spectral power density Ni can be turned into the phase noise power density , and the PLL can be seen as a BPF in the phase domain: θo (s) = H (s)θi (s).

(4.59)

4.2.3.4 PLL Equivalent Noise Bandwidth

The output noise can be evaluated from the transfer function in the phase domain H (s) = θi /θo . The output noise power is
Bi /2 1 |H (jω)|2 dω. (4.60)

θo,n (t)2  = 2π 0 The power density  is constant, and the input filter has bandwidth Bi /2, that is |H (jω)| = 0 for ω > Bi /2. There is no contribution to θo power for f > Bi /2, and the integration limit can be extended to infinity. Equation (4.60) becomes
∞ 1 |H (jω)|2 dω (4.61) 

θo,n (t)2  = 2π 0 and can be written as the product of the input spectral density  and the noise bandwidth BL :

θo,n (t)2  = BL . (4.62) BL is therefore the equivalent noise bandwidth of a filter which has the same effect on noise as the PLL:
∞ 1 BL = |H (jω)|2 dω. (4.63) 2π 0 While Bi is a parameter of the input signal, BL is a parameter of the PLL and depends on Kd , Ko , and F (s). The key element which defines the value of BL and the related trade-off is the position of F (s) poles.

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A low cutoff frequency for F (s) leads to a low cutoff frequency for H (s), and therefore to a narrow BL ; the effects of noise are mitigated and the loop response speed is reduced. A high cutoff frequency for F (s) means high cutoff frequency for H (s), and therefore wide BL , and less filtering effect; the consequence is more noise but also a faster response. 4.2.3.5 SNR

The SNR at the input is defined as SNRi = Ps /Pn ; from (4.56) it follows that SNRi =

1 2 θi,n (t)2 

(4.64)

while the SNR at the output can be defined as SNR o =

1 . 2 θo,n (t)2 

(4.65)

From (4.58), (4.64), and (4.65) it follows that

θo,n (t)2  = 2 θi,n (t)2  SNR o =

BL Bi

Bi 1 1 = . 2  = SNR i 2 (t) 2 θ i,n 2θo,n 2BL BL Bi /2

(4.66) (4.67)

Equation (4.67) shows that a narrow bandwidth BL leads to a higher SNRo : this confirms how the phase filtering effect of a PLL depends on the loop parameters. The input filter bandwidth Bi has no effect on SNRo ; the filtering effect on the input noise is related to the loop bandwidth BL . This analysis shows the filtering effect of PLL. The input signal vi has variable amplitude and is affected by amplitude and phase noise; the output signal vo has fixed amplitude and clean phase, mainly because the VCO control signal vc is filtered by F (s). The PLL therefore can be seen as a BPF with input vi and output vo , with bandwidth BL . This PLL filter is more flexible than a conventional one: the bandwidth is controlled by the cutoff frequency of the low-pass filter transfer function; the cutoff can be placed in any position, allowing to achieve easily a very narrow bandwidth for H (s). From Figure 4.22 it can be observed that the band-pass bandwidth BL is controlled by the loop LPF. A low-pass filter is more flexible and easy to design than a band-pass one. Moreover, the center frequency of the BPF ωo tracks the input signal frequency, thanks to the PLL lock mechanism, and therefore high-precision devices or trimming are not required. When a PLL is used to generate a clock (or any type of time reference), the phase noise modifies the edge positions. Edges in turn are used to synchronize

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Figure 4.22

153

Transfer function of a PLL used as tunable BPF. The center frequency ωo can track the input signal in the ωo range, keeping the same bandwidth BL .

signal sampling: a jitter in edge position becomes an error in the sampling time, which causes an amplitude error related with the signal slew rate (i.e, signal frequency). This issue is discussed in detail in Section 5.5.

4.3 Phase Detectors and Voltage-Controlled Oscillators This section describes the circuits used for two specific functions inside a PLL: the phase detector and the voltage-controlled oscillator. Several circuits can be used for the PD; the choice depends on the type of signal to be processed (analog, digital square wave, pulses), and on the required operating frequency range. A VCO is a signal source whose frequency is controlled by an input voltage (or a by a current, current-controlled oscillator (CCO)). A variety of circuits can be used for this task, with different parameters in terms of frequency range and span. 4.3.1 Phase Detectors for Analog Signals The PD used for analog signals (e.g., sine waves) is an analog multiplier. As discussed in Chapter 3, several circuits can perform this task. The actual choice depends mainly on the frequency range of signals to be processed: for example, a multiplier designed for 1 kHz cannot operate at 1 GHz. This section describes the use of multipliers as phase detectors independently of the actual operating frequency range. As already outlined in Section 4.2, when two sine waves vi (t) = Ai (sin ωi t + θi ) and vo (t) = Ao (sin ωo t + θo ) are multiplied, then the output vd = vi (t)vo (t) includes the sum beat (ωi + ωo ) and the difference beat (ωi − ωo ) (Eq. (4.38)). If the two signals have the same frequency (as occurs in a locked PLL), the difference beat is a DC which provides the phase difference information vd =

Ai Ao sin(θi − θo ) + V2ωi 2

(4.68)

where the term V2ωi contains the sum of contributions at frequency 2ωi . This sum term is blocked by the LPF, and in the following only the difference beat

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Figure 4.23

Transfer function of the multiplier used as phase detector. (a) Periodic transfer function for phase difference higher than 2π, and (b) changes in the input signals amplitude modify the PD gain Kd .

θe = θi − θo is considered: vd =

Km Ai Ao sin θe . 2

(4.69)

The transfer function from phase difference θe to Vd has a sine shape as shown in Figure 4.23(a); the slope around θe = 0 is Kd = dvd /dθe =

Km Ai Ao Km Ai Ao cos θe = 2 2

(4.70)

and, since sin(θe ) ≈ θe if |θe | 1, then (4.69) can be written as vd =

Km Ai Ao θe . 2

(4.71)

As the phase error θe increases, the deviation from the linear approximation becomes more relevant. Moreover, the quantity sin(θe ) has 1 as maximum value, which is not true for the approximation as θe . These effects, and the variation of Kd with signal amplitude, bring to the set of transfer functions represented in Figure 4.23b. The gain Kd of this phase detector depends on the amplitude of the processed signals. The amplitude of vo , from the local oscillator, is usually known and fixed, but this is not true for vi , coming from the field. An automatic gain control (AGC) or a nonlinear dynamic range compressor can be used at the input to get more defined parameters. As outlined in Chapter 2, any nonlinear circuit generates product terms (beats); the phase information is associated with the difference beat, and can be isolated with a low-pass filter (such as the LPF unit already in the loop), and used as the PD useful output. The actual transfer function of this PD is periodic, as shown in Figure 4.23(a): Kd has both positive and negative slope. For stable operation,

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Figure 4.24

155

Definition of phase shift for digital signals; θe = 2πτ/T.

the overall feedback must be negative, therefore only a π range can be used ([−π/2, +π/2] or [+π/2, 3π/2]). Multiplier saturation causes the sine transfer function to be clipped, as shown in Figure 4.23(b). The same effect is caused by compression or other nonlinearity on X or Y multiplier inputs. Very high-amplitude input signals (saturated to high and low levels) make the multiplier operate as XOR gate. In this case the phase detector transfer function becomes linear. The actual shape of the PD transfer function can modify Vd (θe ) for various frequencies, but does not affect the basic loop operation; (i.e., the locking of the VCO with the input signal). 4.3.2 Phase Detectors for Digital Signals For square waves, the phase can be seen as the delay in zero crossing. A delay of a complete period T corresponds to a phase shift θe = 2π; a delay τ corresponds to a phase shift θe = 2πτ/T , as shown in Figure 4.24. This definition works both for square waves and pulses, provided that the delay τ is measured between the same edges (rising or falling) of the two waveforms. A delay of a full period corresponds to a 2π phase error. The digital signals can have various duty cycles, and the phase detector can retrieve the phase information from edges or levels. This brings to different PD circuits: • Level-based PD: XOR gate, good for 50% duty cycle signals; • Edge-based PD: set-reset flip-flop (SR-FF), best for low duty-cycle signals; • Other dedicated sequential circuits (duty cycle independent PD). 4.3.2.1 Digital PD with XOR Gate

For a first analysis, both vi and vo are assumed to be square waves with 50% duty cycle. A circuit that can be used as a PD for such signals is the XOR gate: the output consist of pulses with a duration equal to the time shift between the two square waves, as shown in Figure 4.25. As for the analog PD described in Section 4.3.1, the characteristic of the XOR PD has two branches, with opposite slope (sign of Kd ), as shown in

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Figure 4.25

Waveforms for XOR phase detector. (a) vi = vo ; θe = 0; vd = 0; (b) vi shifted with respect to vo ; pulses on vd have the same duration as the phase shift (in figure, θe = π/2); (c) Further shift, resulting in wider pulses and increased DC component on vd ; (d) θe = π; vd = 1. The XOR phase detector characteristic is shown in (e).

Figure 4.25(e). In the PLL, the feedback must be negative for loop stability and the actual operating point is automatically placed on the branch that corresponds to a negative feedback, the other branch having unstable operating points. 4.3.2.2 Digital PD with Set-Reset Flip-Flop

A digital signal can use pulses instead of square waves; the edge-based phase definition introduced above still works, but the PD must use a different circuit. As a first step, a PD for signals made of pulses with low duty cycle is considered; the next step will be to define circuits which can operate as phase detector for any duty cycle. The SR-FF is a suitable PD circuit when pulsed signals are directly applied to the S and R inputs (Figure 4.26). The logic operation for this FF is: • R pulse: Q = 0 (ground); • S pulse: Q = 1 (supply voltage VDD ). The characteristic of this phase detector, shown in Figure 4.26(e), has a single branch; the sign of Kd is uniquely defined. Combined with other constants (LPF, VCO gain Ko ), the overall feedback in the loop must be negative for stability. 4.3.2.3 Effects of Intermediate Duty Cycle

With XOR PD, if one signal or both have a duty cycle which is not 50%, then shifting a pulse shorter than half-period does not change the vd mean value. This

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Figure 4.26

157

Operation and waveforms of FF phase detector. (a) vi ≈ vo : θe ≈ vd ≈ 0, sequence of very short pulses to high state; (b) vi shifted with respect to vo : pulses on vd , same duration as phase shift; (c) same as (b), with higher phase shift: higher DC on vd ; (d) similar to (a), but now vo pulses are before vi : θe ≈ 2π, vd ≈ VH , sequence of very short pulses to ground. The FF phase detector characteristic is shown in (e).

PD cannot sense some θe changes; the actually usable part of the characteristic depends on the signal duty-cycle (Figure 4.27). With the SR-FF, the presence of wide S, R pulses increases the command overlap probability. If both S and R inputs are active at the same time, the FF enters into a forbidden condition, which may cause a metastable state, with undefined final state. The usable PD range is reduced, as shown in Figure 4.28. 4.3.3 Mixed-Signals Phase Detectors Phase detectors based on XOR and SR FF have constraints on the signal duty cycle; to obtain a duty-cycle independent PD various techniques can be used. The signals can be changed into square waves, and used with an XOR circuit. If pulses are sent to a divide-by-two circuit (e.g., a JK-FF), the result is a square wave that keeps the phase information, because one edge of the pulses becomes edges of the square wave. Another possibility is to convert signals into pulses and use a RS-FF phase detector. Finally, a PD that senses edges instead of levels can be used. These are asynchronous FSM, which can provide both phase and frequency difference information (phase frequency detector (PFD)). An example of such a PFD is the charge pump circuit described in the following. 4.3.3.1 Charge Pump Phase Frequency Detector

The circuit shown in Figure 4.29 is an example of PFD. As previously shown in Figure 4.8, the lag or lead between vi and vo edges is signaled using two outputs,

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Figure 4.27

Effect of input signals duty cycle on XOR PD characteristic. (a) Timing diagrams for various θe , and (b) Vd (θe ) characteristic (gray areas indicate ranges where θe changes are not sensed).

Figure 4.28

Set-Reset FF used as PD with long input pulses. (a) Timing diagrams; gray areas indicate Vi edge positions with FF input rules violation, and undefined output; (b) Vd (θe ) characteristic: gray areas indicate the edge positions which may cause undefined output.

respectively, QA and QB in the diagram. When the edges are aligned, no pulse is produced at the outputs. An edge of vi sets QA = 1, while an edge of vo sets QB = 1; after the arrival of both vi and vo edges, QA and QB are reset to 0. The pulse width corresponds to the phase difference. The circuit in Figure 4.29 can be merged with the loop filter: the output phase pulses are integrated with two controlled current sources, which charge/discharge a capacitor (Figure 4.7(a)), or averaged with a low-pass RC cell

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Figure 4.29

159

Phase frequency detector. vi edge sets QA = 1, vo edge sets QB = 1. After arrival of both vi and vo edges, QA and QB are reset to 0.

(Figure 4.7(b)). This circuit is a charge pump phase detector or PFD. The key difference from other PD-filter circuits is that here the phase error is integrated instead of averaged, therefore the only stable operating condition is θe = 0. PLLs with this PD-filter combination provide a zero phase error over the complete operating range. 4.3.3.2 Mixed-Signals PD

The input and output signal of the VCO can be of different type. In most cases vi is a analog signal from the field, while vo comes from the local VCO, and is a square wave. In this case, it is possible to change one of the signals into the other domain (analog or digital), and use one of the circuit previously described. Analog signals can be turned into square waves with a voltage comparator, but the process removes information, because only edge position is used. Also, square waves can be turned into sine waves, but this operation requires some filtering. A different approach is represented by the use of mixed A/D phase detectors, for example multipliers with one analog input and a ±1 gain switch. In general, analog signals with continuous amplitude provide more information than digital signals, where the only information is edge the position. Keeping all available information (i.e., using analog representation) whenever possible is usually a better choice. 4.3.3.3 Phase Detector Comparison

The behavior and the parameters of the various phase detector circuits are summarized in Table 4.2. Mathematical expressions containing sine and cosine functions are used for analog signals, leading to a zero phase difference for the time relation shown in Figure 4.30(a). For digital signals, the phase difference θe is imposed to be 0 for aligned edges (Figure 4.30(b)) (i.e., for identical signals on vi and vo ). As a result, a π/2 shift in vd (θe ) appears in relations for analog and digital signals, as shown in Figure 4.31.

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Table 4.2 Summary of PD Operations Analog Multiplier (Analog Signals)

Characteristic Usable θe range PD gain Kd Features

vd = (Km Vi Vo π/2) sin(θe ) [−π/2, π/2] or [π/2, 3π/2] Kd = Km vi vo π/2 for small θe Non linear (sine); linear PD for θe 1:vd = Kd θe .

Characteristic Usable θe range PD gain Kd Features

Linear: vd = VDD θe /(π/2) [0,π] or [π , 2π ] Kd = VDD /2π Linear characteristic

Characteristic Usable θe range PD gain Kd Features

Linear: vd = VDD θe /π [0, 2π ] with forbidden areas caused by overlapping pulses Kd = VDD /π [0, 2π ], single field, unique sign for Kd no self-selection of Kd sign to get negative feedback

Characteristic Usable θe range PD gain Kd

Linear: vd = VDD θe /π [0, 2π ] Kd = VDD /π

XOR Gate (50% DC Signals)

Flip-Flop (Pulse Signals)

Phase-Frequency Detector (Edge Sensitive)

Figure 4.30

(a,b) Phase shift definition for analog and digital signals in the time domain and (b,d) corresponding Vd (θe ) transfer functions. (a,b) Analog signals (sine and cosine) with phase shift θe = 0; (c,d) digital signals with phase shift θe = 0.

4.3.4 VCO Circuits Voltage (or current) controlled oscillators can generate signals where the frequency depends on an external control voltage (or current). A large variety of circuits can

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Figure 4.31

161

Correspondence between the analog (gray) and digital (black) phase detectors Vd (θe ) characteristic.

provide this function; the parameters to be considered to select or design a VCO circuit are: • Amount of frequency change ω. The parameter can be expressed in percentage of the central frequency ωo,r . • Frequency range: Examples for signals up to about 10 MHz are presented; in this range signals can be easily generated with circuits using operational amplifiers. For higher frequencies, circuits generally use simpler amplifiers (e.g., single transistors or differential pairs), to reduce the effect of parasitic. 4.3.4.1 Low-Frequency VCO Circuits

The circuits for low frequencies use charge/discharge of a capacitor, and achieve frequency control by varying either the charge/discharge current or the threshold for charge/discharge switching. For fixed threshold, variable charging current, the current ic depends on the VCO control voltage vc . As vc reaches the comparator threshold vth , the current ic is inverted. In these circuits the current can change across a wide range, therefore they can achieve a wide frequency change, related with the ratio between minimum and maximum current, which can go up to three or four decades in current ICs. An example of variable current VCO circuit is presented in Figure 4.32. This is the circuit used in the CD4046 integrated PLL described in Section 4.4. The circuit in Figure 4.33 uses a different approach: the current in the capacitor C is fixed, but the switching thresholds vth1 and vth2 are controlled by vc . As vc reaches vth , the current (or capacitor) is inverted. In this case, the dynamic of frequency changes is limited, because low voltages are affected by noise. This circuit is used in the NE567 integrated PLL. 4.3.4.2 High-Frequency VCO Circuits

High-frequency VCOs are oscillators with LC tuned circuits or other resonators, where the parameters defining the resonant frequency can be modified by the control voltage. In most cases the variable element is the capacitor; it can use a junction where the reverse bias controls the thickness of the depletion layer

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Figure 4.32

Example of VCO circuit with wide frequency dynamic range. C is charged through the current mirror M with a current ic = ±i2 controlled by vc . As vA reaches the T1 threshold Vth , SWA and SWB toggle, the current ic is inverted, and vA = 0 while vB starts to raise. As vB reaches the T2 threshold Vth , SWA and SWB toggle, the current ic is inverted, and vB = 0 while vA becomes negative and starts to raise.

Figure 4.33

Example of variable threshold VCO. Voltages vth,1 and vth,2 depend on control voltage vc (voltage divider between R1 and R2 ). As vc reaches vth,1 , Q is set to logic 0, vo = 0, and the capacitor starts discharging. As vc reaches vth,2 , Q is set to logic 1, vo = VDD , and the capacitor starts charging.

and therefore the capacitance. Any junction shows this behavior; however, some devices are optimized for this function and allow wide C change: the varicap or varactor diodes. An example of tuned circuit with varicap-controlled resonant frequency is shown in Figure 4.34. The inductor La isolates the control loop from the RF voltage. The capacitor Cb isolates the RF section from the control voltage vc . The resonant frequency depends on total equivalent capacitance including Cb , Cc , Cd : ωr = 



1

Lb Cc +

Cb Cd Cb +Cd

.

(4.72)

The variable frequency can also come from the beat between two oscillators: a fixed frequency one and a VCO.This technique allows to obtain a wide frequency change. 4.3.4.3 Phase Noise and Spurs

When the control voltage vc has no change, the VCO generates pure sine signals; changes of vc cause phase and frequency modulation. For noise and random

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Figure 4.34

Resonant circuit with varactor diode.

Figure 4.35

Actual spectrum from a VCO. Black line: sine signal with no noise or modulation. Light gray area: effect of noise (random changes) in the control voltage. Dark gray lines (1) are caused by periodic changes in the control voltage (spurs).

changes the effect is phase noise, which turns the delta-like spectrum of vo into a wider curve. Periodic changes in the control voltage cause new spectral lines (spurs), as shown in Figure 4.35.

4.4 PLL Applications This section focuses on applications of the PLL and describes how the PLL can be used to assist information recovery from various types of modulated signals. When demodulation techniques are based on carrier recovery with the PLL, they are called synchronous or coherent demodulation. 4.4.1 FM and AM Demodulation 4.4.1.1 FM Signals

In an FM signal, the carrier frequency ωp,0 varies linearly with respect to a modulating signal g (t) with K modulation strength: ωp (t) = ωp,0 + K g (t).

(4.73)

The modulated signal vFM can be written in a general way as vFM = A sin θ(t) with


θ (t) = 0

t

(4.74)


ωp (τ )dτ = ωp,0 t + K

t

g (τ )dτ .

(4.75)

0

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Figure 4.36

Example of frequency modulated signal: a 150 kHz carrier is modulated by a 10 kHz sinusoidal signal. (I): Time domain; (II): frequency domain. (a): carrier; (b): modulation; (c): FM signal. The corresponding MATLAB script is presented in Listing 4.1 at the end of this Chapter.

and, as a result, the FM modulated signal is vFM

 
t = A sin ωp,0 t + K g (τ )dτ ;

(4.76)

0

if a cosine modulation is considered at frequency ωFM , (4.76) becomes 

vFM

 K = A sin ωp,0 t + sin(ωFM t) . ωFM

(4.77)

An example of such a signal in both time and frequency domains is shown in Figure 4.36. The actual spectrum depends on the modulation index K ; higher values of K (corresponding to larger frequency changes) cause higher harmonic content. Several techniques are available for demodulation of these FM signals. A simple one is to exploit the transition region of a steep filter: a high-Q resonant circuit tuned on the carrier turns FM into AM (Figure 4.37(a)), which can be demodulated using a standard AM detector. A suitable circuit is the Foster-Seeley discriminator [4] shown in Figure 4.37(b). Another possibility is to use synchronous demodulation, i.e., a PLL locked on the FM signal. As long as the loop is locked, the VCO control voltage vc tracks the input frequency changes and vc (t) is proportional to g (t), as shown Figure 4.38.

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Figure 4.37

(a) FM detection using the slope of a tuned circuit, and (b) Example of Foster-Seeley FM discriminator.

Figure 4.38

Butterfly diagram for a PLL used as FM detector. vo (t ) is the demodulated output. FM demodulation occurs within the capture range.

4.4.1.2 AM Modulation and Demodulation

The AM signal vAM is obtained [6] multiplying the carrier A sin ωC t by (c + mg (t)), with g (t) modulating signal having zero average and max|g (t)| = 1, and c offset; the modulation index m defines the amount of amplitude change. If c = 1, then vAM (t) = A(sin ωC t)(1 + mg (t)) is the AM signal. In the time domain, g (t) is proportional to the envelope of the carrier sin ωC t. In the frequency domain, this signal is represented by the carrier ωC and the sidebands; if g (t) is a sinusoidal signal at angular frequency ωAM then the sidebands are spaced by ωAM from the carrier. Examples of AM signals in the time and in the frequency domains are shown in Figures 4.39(a) and 4.39(b). If c = 0, vAM (t) = mA(sin ωC t)g (t) is the AM double side band suppressed carrier: as shown in Figure 4.39(c), in this case no carrier can be observed in the spectrum and no power is wasted for informationless signals (the carrier). If both the carrier and one sideband are suppressed, a SSB AM is obtained, which provides high efficiency for long-range communications. These types of AM require specific techniques for demodulation.

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Figure 4.39

Examples of amplitude modulated signals. (I): Time domain, with modulating signal c + ag(t ) (dashed line) and modulated signal vAM (t ) (solid line); (II): modulated signal in the frequency domain. For all the cases, A = 1, ωC = 2π150 kHz, g(t ) = sin (2π 10 kHzt). (a): c = 1, m = 0.5 (50% modulation); (b) c = 1, m = 1 (100% modulation); (c) c = 0, m = 1. The corresponding MATLAB script is presented in Listing 4.2 at the end of this Chapter.

Figure 4.40

Envelope AM detector. (a) Schematic diagram, and (b) modulated input vi and demodulated output vo .

4.4.1.3 AM Asynchronous Demodulation (Envelope Detectors)

The goal of an AM demodulator is to extract the envelope of the modulated signal; this can be achieved with two basic approaches, namely the asynchronous (half- or full-wave rectifier), or envelope demodulator, and the synchronous demodulation. In any case, the AM demodulator must be followed by a low-pass filter, which removes the carrier and other higher order components of the modulated signal. The asynchronous AM demodulator is basically a peak detector with losses (Figure 4.40). The capacitor C is charged to the maximum value of the modulated signal, then discharged through the resistance R. A full-wave version can be realized with two diodes and direct/inverted signal sources, or with a bridge. These circuits are very simple, but have also several drawbacks. First, the peak detector requires a minimum input voltage to cross the diode threshold. Moreover, noise peaks at the input influence the

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Figure 4.41

Example of full-wave AM demodulation with active rectifier.

Figure 4.42

Synchronous AM demodulator block diagram (single branch). A: pass-band input filter; B: PPL; C: AM detector; D: analog multiplier; E: low-pass AM output filter.

output. Finally, for modulation index m > 1, the output is not correct since it does not consider the phase. The input threshold can be reduced with the active rectifier shown in Figure 4.41, while handling modulation index higher than 1 requires a different approach, such as the coherent demodulation described in the following. 4.4.2 Coherent AM Demodulation Better performance can be obtained with the synchronous or coherent demodulation, which basically performs the inverse operation with respect to modulation: the RF signal is multiplied by the carrier, and the difference beat corresponds to baseband modulating signal. This technique requires a reference signal, synchronous with the carrier, which can be obtained using a PLL. The complete block diagram of a synchronous AM detector is presented in Figure 4.42: the input low-pass filter removes out-band noise; the PLL generates the reference signal, and the multiplier M operates as demodulator, translating vi to baseband. Synchronous demodulation generates sum and difference beats; the demodulation filter Fdem isolates the baseband (difference) signal. The operating frequency range depends on PLL capture range, which in turn is controlled by the PLL LPF.

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Figure 4.43

Effect of frequency drift on a synchronous AM demodulator. For an assigned frequency shift ω1 , a lower loop gain (dotted line) causes a higher amplitude error VA .

Figure 4.44

Examples of experimental AM synchronous detector characteristic and butterfly diagram. (a) VCO control signal Vc (butterfly diagram); (b) Synchronous AM detector output (cosine, as in Figure 4.43).

The complete block diagram for synchronous AM demodulation is shown in Figure 4.42. The signal vo comes from the PLL VCO, with a π/2 phase shift with the signal used to lock the PLL. The integrated PLL NE567, described in Section 4.5, is an example of synchronous AM demodulator. 4.4.2.1 Effect of Frequency Drift

Changes in the carrier frequency cause a change in the phase error θe in the PLL, which in turn causes an output error. The demodulated output signal VA (ω) is a cosine, centered on ωo,r , therefore VA = (1 − cos θe ), as shown in Figure 4.43. An example of experimental AM demodulation from an actual device (LM567, described in Section 4.5.2) is presented in Figure 4.44. The influence of frequency on the output of a AM detector is an example of cross-demodulation. A FM causes output change from the AM detector. To reduce

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169

Figure 4.45

I/Q AM demodulator. (a) Block diagram, and (b) vector representation, VI = VP cos ωt, VQ = VP sin ωt.

Figure 4.46

ZIF structure with digital I/Q output. (a) Analog mixer and filter, baseband ADC, and (b) IF or RF ADC, digital mixer and filter.

the error it is possible to increase the loop gain, thus reducing θe and keeping cos θe ≈ 1, or to use in-phase/quadrature (I/Q) demodulator. 4.4.2.2 I/Q Demodulation

I/Q amplitude demodulation can be used to overcome the effects of frequency/phase shift, as shown in Figure 4.45. The two components (I and Q) are evaluated using I/Q reference signals, then the actual amplitude is evaluated from Pythagorean’s theorem. Here the output VA is independent of phase (and frequency) shifts as long as the PLL is locked. Analog input signals can be converted into digital; this can be done at various position in the chain, as shown in Figure 1.23. Analog-to-Digital conversion after the mixer (baseband) is shown in Figure 4.46(a), while A/D conversion at the input (RF), followed by digital I/Q mixer, is presented in Figure 4.46(b). 4.4.3 Digital Modulation and Demodulation The modulation techniques previously described for analog signals can be applied also to digitally modulated signals: • Amplitude shift keyed (ASK), or pulse amplitude modulation (PAM); amplitude modulation with two (or N ) discrete amplitude values;

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Figure 4.47

Modulated signals in the (I) time and (II) frequency domains, for a random sequence of bits. Spectra are evaluated on a sequence of 200 bits at 50 kHz; the first 5 bits are shown in the temporal traces. (a) bit sequence (01001); (b) FSK: amplitude: 1 V, logic 0 frequency: 100 kHz, logic 1 frequency: 300 kHz; (c) ASK: logic 1 amplitude: 1 V, logic 0 amplitude: 0.5 V, frequency: 100 kHz; (d) PSK: amplitude: 1 V, frequency: 100 kHz. The corresponding MATLAB script is presented in Listing 4.3 at the end of this Chapter.

• FSK: frequency modulation with two (or N ) discrete frequency values; • PSK: phase modulation with two (or N ) discrete phase values; • Mixed amplitude/frequency/phase modulation: quadrature amplitude modulation (QAM), quadrature phase-shift keying (QPSK), and several others. Examples of modulated signals are shown in Figure 4.47. 4.4.3.1 Digital FM or FSK Signal

FSK can be demodulated with the same techniques as analog FM. Another choice is a BPF bank, with envelope demodulators on each channel, followed by comparison of outputs with winner takes all (WTA) comparators (the output corresponds to the highest input). An example of FSK signal is presented in Figure 4.47(b). For all these circuits the key parameter is the output filter cutoff frequency; it acts as symbol BPF, and defines the speed/noise immunity trade-offs. Wideband filters allows for a fast response, but are noise-sensitive, while narrowband filters have a slow response, which provides high noise rejection, but requires several carrier periods for each bit.

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4.4.3.2 PAM/ASK Demodulators

PAM/ASK signals are shown in Figure 4.47(c). ASK is basically a discrete AM (with 2, . . . , N levels); demodulation can use the same techniques of analog AM, with envelope detector and coherent demodulation. The detection core is followed by decision logic which assigns to digital values the analog demodulator output. A key design decision for this application for all circuits is the bandwidth of the post-detection filter. Wideband filters ensure a fast response but are noise-sensitive; narrowband filter have better noise rejection, but slow response. 4.4.3.3 Phase-Shift Keying Demodulation

PSK considers a signal where information is associated to discrete phase. The time and frequency domain representation for this type of signals are presented in Figure 4.47(d). 4.4.3.4 Eye Diagram

For synchronous AM and phase modulation (PM) signals, a clear overall view of the performances of the signal recovery correctness is provided by the eye diagram, a time domain representation of signals with various symbol, overlapped on a single time frame. The parameters for a (simplified) eye diagram are defined in Figure 4.48(a), and an example showing the signal at the transmitter and at the receiver is shown in Figure 4.48(b). The eye diagram identifies the following parameters • Correct operation area, or eye opening area (i.e., amplitude) from VIH to VIL , and the time window from Tsu (before the clock edge) to Th (after the edge); • Errors in the time axis, namely the frequency error and drift (long term), and the clock edge shift caused by skew and jitter (in each clock slot); • Errors in the amplitude axis, such as the actual values and drifts of VOH , VOL , VIH , VIL , the edge slope (related to channel bandwidth), noise, and ISI. 4.4.3.5 Examples of Complex Multibit Signals

In order to better exploit the available bandwidth, digital modulations moved towards more complex techniques that combine amplitude and phase (and sometimes also frequency) modulations to pack more information in each symbol. The key parameters for these modulated signals are the bit rate and the symbol rate (or baud rate). The bit rate (Br ) is the number of bits transmitted per second. The symbol rate (Sr ) is the number of symbols (signal units) transmitted per second. Since each symbol can encode N bits, then Br = NSr ≥ Sr .

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Figure 4.48

Example of eye diagram for binary NRZ signal. (a) Simplified eye diagram with examples of correct signal waveforms (black lines); (b) TX clock, and accepted shift range for RX clock. Tck represents the allowed clock jitter.

The bit rate depends on logic circuits and system parameters, while the symbol rate depends on data encoding and transmitter/channel/receiver parameters. This section provides some examples of these modulations, and discusses how these signals can be demodulated with PLLs or other techniques. The example signals are represented in the I/Q space by the signal constellation. For ideal systems, each signal state is represented by a point; when noise modifies the I and Q components, each points becomes a cloud. As long as the clouds are separated, signals can be correctly demodulated. In real systems the overall bit error rate will be determined by the separation of the clouds, which in turn depends on amplitude of the noise. 4.4.3.6 8 QAM Signal

A first example is the phase/amplitude combined modulation technique (QAM, ASK + PSK). Information bits are grouped in 3-bit packets; two bits are encoded in phase shift (four states), while a third bit modifies signal amplitude (two levels). This QAM uses 8 symbols, represented by the signal constellation shown in Figure 4.49(a). The amplitude has two values, and the lower one is not 0. This guarantees the possibility to synchronize on the carrier for any bit stream. To maximize the distance between constellation points, the phase is different for low- and high-level symbols. Since noise moves the signal points away from the

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Figure 4.49

Example of constellations. (a) QAM (8 symbols), and (b) QPSK 16 (16 symbols).

Figure 4.50

Basic frequency synthesizer loop.

ideal position, the increased distance improves the noise tolerance in additive white Gaussian noise (AWGN) channels. 4.4.3.7 16 QAM Signal

The second example (Figure 4.49(b)) is a signal with 16 symbols; in the I/Q plane it can be seen as combinations of 4 possible I values and 4 possible Q values. Each symbol carries 2 + 2 = 4 bits. In general, all digital modulations can be demodulated using an I/Q architecture and then remapping the demodulated code in the digital part. 4.4.4 Frequency Synthesizers A PLL can be used to generate a signal with frequency related to an external reference through a fixed ratio. This technique, called signal synthesis, is widely used in RF equipment and digital signal processing, to generate several signals with stable and accurate frequency from a single frequency reference. The block diagram of a basic synthesizer is shown in Figure 4.50. The PLL and the frequency dividers define fixed ratios between signal frequency in the various part of the circuit. In the synthesizer loop, fc = fr /M , and fs = fo /N ; as a result the output frequency fo is fo = N /Mfr .

(4.78)

This circuit is a frequency synthesizer, and can provide various frequencies from a unique reference fr . It is widely used in signal sources, in radio systems, and in processing systems. 4.4.4.1 Settling Time and Resolution

When the output frequency must be modified (e.g., to tune the radio on a different channel) N and/or M must be modified; the new frequency is obtained after a

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settling time, which depends on the PLL response speed (i.e., on the PLL loop filter) and on the required precision. The minimum frequency change or resolution corresponds to changing N to N + 1; the output frequency is modified from fo
to fo
+ fo , with fo = fc = fr /M . Achieving a high-frequency resolution requires low values of fc and fs , but this brings some drawbacks: to remove the sum terms from the PD output vd a low cutoff is required in the LPF, which causes a slow transient response for vc , that is a long response time to frequency changes. For a defined channel spacing, higher fc and fs can be used to speed up the transient response, which allow for higher cutoff in the LPF. 4.4.4.2 Integer Synthesizer: Numeric Example

In this example, the goal is to generate signals with a frequency starting from 100 MHz, with step f = 100 kHz, using a reference signal with frequency fr = 10 MHz. The required divider factor is M = fr /f = 100. With fc = 100 kHz, the various output frequencies can be obtained with N = 1000 (→ 100 MHz), N = 1001 (→ 100.1 MHz), N = 1002 (→ 100.2 MHz), . . . For a loop filter cutoff at about fc /10, it follows that fs ≈ 10 kHz. With such a low-pass filter, the settling time to 0.1% is about 7τ , that is 0.7 ms, and for settling to 1 PPM is 16 µs, which can be too long for some applications (e.g., channel handover in cellular systems). Basically, the need for fast response is conflicting with the requirement for a high resolution and in general highfrequency resolution requires long settling time. The delay can be reduced using the fractional synthesizer technique. 4.4.4.3 Fractional Synthesizer

The main problem of synthesizer circuits is that high resolution and fast settling are conflicting parameters: high M and N values require low fc and fo , and this in turn brings to a provide high resolution but slow transient response. For a fast response, both N and M must be low, and the solution is to use noninteger M , N numbers. This leads to larger fc and fo , higher cutoff for the LPF, and finally faster response of the loop. It is possible to periodically change the divide factor N in order to divide by noninteger numbers; in actual circuits the change is from N to N + 1. The effective divide ratio is related with the duty cycle of the N /(N + 1) command. Due to periodic frequency change, this technique brings to a residual FM that can be seen as phase noise. Since this parameter if known, it can be corrected. Since the operation can be seen as dividing by a fractional number, these circuits are called fractional synthesizers (block diagram in Figure 4.51). To evaluate the actual synthesizer frequency, it is convenient to assume that the divider ratio changes with duty cycle D: for a portion of the period T × D a

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Figure 4.51

175

Fractional frequency synthesizer.

division by N is performed, while for the remaining T × (1 − D) the division is by N + 1. The average reference frequency for the PD is fs =

fo fo D+ (1 − D) N N +1

(4.79)

which corresponds to an equivalent average divider ratio N (N + 1)/(D + N ); it provides an output frequency fo = fs N

N +1 . D+N

(4.80)

Fractional synthesizers provide high resolution at the expense of periodic change of divide factor; this frequency ripple can be reduced with proper techniques. 4.4.4.4 Fractional Synthesizer: Numeric Example

To provide some figures on this approach it is possible to analyze various solutions for a synthesizer providing 400 channels from 900 MHz to 920 MHz, with a corresponding channel spacing of 50 kHz. With an integer synthesizer, the PLL must operate at a frequency corresponding to the channel spacing: fi , fo = 50 kHz. The bandwidth of the LPF, with the rule 1/10 of frequency step is fB,1 = 5 kHz and τ ≈ 30 µs. The settling time within 1 kHz (1 PPM of fu ) is about 14τ , that is Ts,1 = 420 µs. For a fractional synthesizer, with ratio 20/21, fi , fo = 1 MHz; using the same rule previously used, the LPF bandwidth is fB,2 = 100 kHz, and τ = 1.6 µs. The settling time within 1 kHz is about 14τ , that is Ts,2 = 22 µs. This analysis of frequency synthesizers shows that integer synthesizers may suffer from long settling time, and fractional synthesizers are affected by frequency ripple. A more flexible solution to generate precise signals from a unique reference is represented by the DDS. 4.4.5 Direct Digital Synthesizers The DDS can be used to generate signals of various frequency (and shape) from a unique reference. This system operates in two main steps: first, it provides

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Figure 4.52

(a) Block diagram and (b) vector signal representation of a DDS. φ: phase step (sample-to-sample phase difference); P : pointer to sample table; D: digital value of samples; A: sequence of analog samples; O: final filtered output.

a sequence of numeric values corresponding to output signal samples; then, it turns these numbers into analog values, with adequate conditioning (filtering) to remove harmonics. The DDS structure and operation are represented in Figure 4.52. The phase accumulator generates time positions (phases, P) spaced by a phase step φ. This function is usually performed by an adder loop or by a variable-step counter. The phase accumulator operates at fixed clock rate. The output of the phase accumulator is used as pointer in a table of output signal values. The content (D) of this table defines the output waveform. When the scan step is changed, a full period is scanned with different number of samples and the frequency of the output signal is modified without the need of changing the clock. The sample table contains output signal samples (the pointer could be directly used to generate a saw-tooth signal). The frequency of the output signal depends on the scan rate and the scan step; usually a DDS operates with fixed scan rate and variable step. Figure 4.53 provides an example of scan results with different steps. The phase accumulator (Figure 4.54) computes the sequence of addresses for the sample table. It uses a loop with an adder and an accumulator register. Direct digital synthesis works for any signal shape; for instance this is the technique used in wavetable sound boards to generate music from different instruments. Compared to the PLL synthesizer approach described in the previous section, the benefits of DDS are: • Direct commands to set frequency and phase, without transients; • No loop to settle, therefore no transient in frequency change; • Ability to generate any waveform. The size of the sample table can be reduced exploiting symmetry in the waveform (e.g., in a sine wave only samples of 1/4 period are actually required), or using interpolation logic.

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Figure 4.53

Examples of DDS operation with constant sample rate and various scan steps S and number of samples/period N. Sample table with 10 samples (number of samples in the table K = 10, full period); scan rate fs = 1 MSPS; scan step period TS = 1 µs. To = TS × K/S, fo = 10 MHz × S/K.

Figure 4.54

Structure of the phase accumulator.

Figure 4.55

Modulation of DDS output signal.

DDS technique allows direct generation of modulated signals, by changing the proper parameter, as shown in Figure 4.55: • FM, by modifying the scan step φ; • PM, by adding a constant θ to phase accumulator; • AM, by multiplying the wavetable output samples by the modulation signal M . For digital modulations (PAM/ASK), the amplitude ratio is a power of 2, which corresponds to a 1-bit shift for amplitude ratio 2, or N -bit, for 2N ratios.

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The frequency of the synthesized output signal can be evaluated from the following parameters: • Table with K samples (full period); • Table scanned with a step S, corresponding to K /S samples per period; • Scan rate fs , sample interval Ts = 1/fs . The period of the output signal is To = Ts K /S, and accordingly the output signal frequency is fo = fs S/K . The ratio K /S can be noninteger, meaning that in successive scans of the wavetable different samples will be selected. DDS are sampled data systems and, as a consequence, they always need a reconstruction filter at the output. The key DDS parameter is the frequency resolution, which in turn depends on the phase accumulator resolution (N bit), and on the minimum change in the scan step. To limit the size of the sample table, the table pointer resolution is smaller than the accumulator resolution. Only most significant bits (MSBs) of phase accumulator are actually used for the pointer, but all bits are used in the accumulation loop (see the bit numbers in the example of Figure 4.56). The output spectral purity is defined by the spurious free dynamic range (SFDR) and it depends on quantization noise, distortion and output spectrum aliasing. The quantization noise depends on sample table and DAC resolution; with N bits, SNRq |dB = 20N log 2 = 6N (see Section 5.1). The distortion (or harmonics content) depends on the number of available samples (defined by the wavetable size), while the output spectrum aliasing depends on the sample rate fs , which creates aliases at frequencies that are integer multiples to fs . The signal accuracy can be improved using more bits (i.e., reducing the quantization noise), and using more samples per period (i.e., moving aliases to higher frequencies); in both cases larger tables are needed, but the size of the sample memory can be reduced exploiting signal symmetries (with odd waveforms, it is possible to use a sign inversion between half-periods, and scan inversion at quarter-period), evaluating intermediate samples with linear or higher order interpolation, or using a nonlinear DAC with higher resolution for lower levels. Numeric-controlled oscillators (NCOs) are DDS with square wave output. The output can be directly the MSB of the sample pointer; the NCO has no memory, no DAC, and the resolution is limited by the sample clock frequency. For higher frequency resolution, the circuit can use also other bits to evaluate the position of the zero crossing (edge of the square wave). An example of commercial DDS (Analog Device AD7008) is shown in Figure 4.56. The main characteristics of this device are: • 32-bit phase accumulator; • Two frequency internal registers (for fast switch); • Additional adder for phase modulation;

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Figure 4.56

• • • •

179

Example of commercial CMOS DDS Modulator (AD7008, Analog Devices [1]).

12-bit address pointer; Two channels (I/Q components); 10-bit DAC; Direct PM-FM-AM modulation capability.

The accumulator loop works with 32 bits, but only the 12 MSBs are used for the pointer in the sine sample ROM. The high number of bits guarantees high-frequency resolution. The final output is a weighted sum of the generated I/Q components. 4.4.6 Data Resynchronization and Clock/Data Recovery PLLs are used also in digital systems for applications such as clock multipliers (Figure 4.57), clock re-synchronization with delay lock loops (DLLs), timing recovery from data signal (clock-data recovery (CDR)), lock on phase-modulated signals, and demodulation. The structures used for these applications are derived from the PLL synthesizers described in Section 4.4.4; they are used in digital systems to provide several timing signals from a single reference with stable and precise frequency, or clock signals with a defined phase relation with a specific signal. 4.4.6.1 High-Speed Digital Systems

In high-speed digital systems, clock distribution is a critical issue because clock signals and data reach the various device and subsystems with different delays as shown in Figure 4.58. The consequent clock/data skew modifies timing relations and can cause synchronization errors, such as metastability in FFs.

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Figure 4.57

High-speed internal clock from external reference; fi = Nfr .

Figure 4.58

Different delays in the clock paths cause different switching times of FF outputs.

Subsystems that use the same clock must be designed to occupy a compact area in order to keep these problems under control limiting the skew. A local clock, that synchronizes circuits across a small surrounding area, can be faster than a global clock, which has to synchronize units spread over a wide area, with a variety of propagation delays and consequent high skew. As general rule, a local clock can be fast, while a global clock requires wider time margins, and therefore it is be slower. In an ideal system all devices switch at the same time, but in a real IC clocks reach internal FFs at different times because of skew. The key problem is the synchronization of clocks among various subsystems in a large IC. Time errors increase with physical distance; the basic technique is therefore to have a rather slow global clock, which can synchronize fast local clocks, driving smaller areas. This can be done with local frequency multiplication and resynchronization based on PLL synthesizers. Complex systems need clocks at various frequencies, with known phase relation and time margins for data setup and hold. They can be obtained from a unique reference frequency with PLL integer synthesizers, which can also operate as clock multipliers. A technique to reduce the skew (and therefore increase the usable clock rate) is to generate the internal clock with a PLL, with the VCO signal coming from

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Figure 4.59

181

Compensation of internal propagation delays with phase lock: local clocks LCK 1/2 have different distribution trees and different delays (Delay 1/2), but the clocks to output registers (CLK1/2) are synchronized with reference clock CLK. (a) PLL loops closed to the output register clock; (b) timing diagrams: CLK1 and CLK2 are synchronized with the input clock CLK.

the actual clock inputs of registers (i.e, the leaf of the clock distribution tree), as shown in Figure 4.59. The internal clock phase is automatically adjusted by the loop negative feedback to compensate for the clock distribution tree delay, and clocks to all FFs are synchronized. 4.4.6.2 Resynchronized Outputs

When the clock tree is included in the PLL loop, the clock-to-output registers (CLK3 in Figure 4.60(a)) is synchronized with the external clock CLK, independently from internal clock delays. The internal clock is obtained from the input clock through a variable delay (such as a buffer chain with controlled supply, as in Figure 4.60(b)). This DLL does not need a VCO, since only phase adjustment are required. 4.4.6.3 Clock/Data Synchronization

When data and clock use two separate distribution channels (e.g., two tracks on a PCB), the different delays can cause skew, which modifies the timing relations, and can cause violation of timing constraints (register setup Tsu and hold Th , plus the skew margin Tk .) This skew is the actual limit to data rate in digital systems, because the minimum clock period Tck,min is Tck,min = Tsu + Th + Tk .

(4.81)

Delays must be matched to reduce skew; this can be achieved with proper design of the active circuits (drivers and receivers) and tight control of signal transmission delays in the interconnections (PCB tracks or other media such as cables, optical fibers, and radio channels).

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Figure 4.60

Output register clock synchronization with delay lock loop. CK3 edges are synchronized with CK1 (with 1 period delay), CK2 timing depends on internal delays. (a) DLL block diagram, and (b) voltage-controlled variable-delay circuit.

4.4.6.4 Embedded Clock and Clock Recovery Circuit

A different solution is to merge data an timing in a single signal; this embedded clock technique guarantees matched delays, but requires proper encoding/modulations at the transmitter and clock/data separation circuits at destination. Clock embedding can use specific symbols or modulation at bit level, or data formatting that guarantees some periodic resynchronization. The added timing information increase the number of edges and requires wider channel bandwidth. Examples of self synchronizing codes are shown in Figure 4.61. To allow synchronization at the receiver side, the signal must have an adequate rate of transitions; this can be achieved with proper modulation techniques (e.g., PSK 180◦ or Biφ-L in Figure 4.61), or using bit stuffing (inserting additional bits to limit the interval between transitions), or with specific coding (e.g., 8B/10B [12]). The clock oscillator at the receiver side can be synchronized to some periodic event of the input signal (e.g., edges), using a PLL or other techniques.

4.5 Examples of Integrated PLLs This section describes the internal structure of exemplary integrated PLLs: the CD4046, the NE567, and an analog-digital PLL (ADPLL). The first two are rather old (developed before 1970), but still used, and are good examples of structures tailored for different applications. Their last versions use new technologies (CMOS), but the basic operation and applications have been maintained.

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Figure 4.61

183

Examples of synchronous modulations (time domain). (a) NRZ; (b) Bi-Phase Level, 0: H → L transition, 1: L → H transition; (c) Bi-Phase Mark, 0: fixed level, 1: transition at T/2 (H → L or L → H); (d) Modified FM; (e) M2 FM.

The CD4046 is based on digital technology, includes several digital functions, and provides independent functional units (VCO, PD). This makes possible its use for applications like frequency synthesizers, clock recovery, and synchronous demodulation. The NE567 is fully analog, and has a fixed configuration. Its applications are centered on synchronous AM demodulation. In the ADPLL most of internal circuits are programmable and some functions are performed by DSP software. This approach guarantees maximum operation flexibility usually at the expense of a higher power consumption.

4.5.1 General Purpose PLL: CD4046 The integrated circuit CD4046 (Figure 4.62) belongs to the 4000 CMOS family, developed around 1967, characterized by a wide power supply range (3 V to 18 V), and rather low-frequency operation (few megahertz). The last versions (74HC4046, 1990) got a higher operating frequency (tens of megahertz) and a third phase detector. The main features, common to all versions, are: • • • •

Wide range VCO; Infinite loop gain (with PD 2); Possibility to open the loop after the PD and after the VCO; Analog or digital input signal capability.

Phase detectors and VCO use independent circuits, and the LPF is completely external. This structure allows the use of various RC and R − RC filter configurations. Frequency dividers can be inserted in the loop to get a frequency synthesizer.

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Figure 4.62

Block diagram of the CD4046 integrated PLL [9]. Courtesy Texas Instruments.

Figure 4.63

Input DC bias network. (a) The inverter with feedback sets the DC level at vi,DC = v0 , corresponding to the threshold Vth , and (b) input bias circuit; the DC operating point automatically set on the threshold.

4.5.1.1 Input Comparator

Analog signals are turned into digital with a threshold comparator. As shown in Figure 4.63, the input circuit includes a bias network which automatically places the DC level on the threshold Vth ; in this way—using AC coupling—also very low-level input signals cross the threshold and are sensed by the comparator.

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Figure 4.64

185

Signals with various PDs. (a) XOR gate: vc is a DC voltage with some ripple, (b) async FSM PFD: vc is a DC voltage; changes only when θe  = 0, and (c) FF, only for 74HC46: vc is a DC voltage with some ripple.

4.5.1.2 Phase Detectors

Several phase detectors are available in this circuit, as shown in Figure 4.64: • XOR gate PD, for signals with 50% duty cycle; this PD achieves lock with θe = π/2 (at center frequency). • Asynchronous sequential circuit PFD (Section 4.3.2); this circuit operates with signal of any duty cycle. It provides a charge pump output, with infinite loop gain. Lock is always with θe = 0. • Flip Flop PD (only in the HC family): this circuit changes transitions into pulses, and operates with any duty cycle. Lock is achieved with θe = π/2. 4.5.1.3 VCO Circuit

The variable frequency oscillator of the CD4046 is a CCO. The control current i is obtained from the input voltage vc with the circuit in Figure 4.65, through the current mirror M : i = i1 + i2 (4.82)

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Figure 4.65

CD4046 VCO circuit. (a) Block diagram, and (b) fo versus vc characteristic.

where i2 is determined by the resistance R2 , and i1 is controlled by vc through R1 . Assuming for the transistors a gate-source voltage vgs much smaller that both vc and Vdd , the two currents can be expressed as i1 = vc /R1

(4.83)

i2 = VDD /R2 .

(4.84)

The complete CD4046 VCO circuit is shown in Figure 4.65. The capacitor C is charged with the current iT ; for the configuration shown in Figure 4.65 (node B connected to ground) the voltage across the capacitor is vA = iT /C . The threshold of the comparator T1 is reached after a time proportional to 1/iT , therefore the frequency is directly proportional to the charging current iT . As the threshold is reached, the SR-FF changes state and the capacitor starts to discharge at the same rate. The total charge/discharge current is controlled by vc : vc VDD + . (4.85) iT = R1 R2 The frequency fo for vc = 0 is set by R2 ; the slope of fo (vc ) is set by R1 . The overall fo (vc ) characteristic is shown in Figure 4.65(b). 4.5.2 Tone Decoder PLL: NE567 The NE567 IC is a synchronous AM detector (tone decoder), available from several manufacturers in bipolar and CMOS technologies, with slightly different structures. Depending on the manufacturer, it can be labeled as NE567, LM576, LMC567, or, in general, as xx567. 4.5.2.1 Tone Decoder Operation

A tone decoder can recognize a carrier (tone) within a frequency interval, even with strong interferences by noise and other signals. Such circuits are used to recognize commands (e.g., phone signaling numbers), even if overlapped with other signals and noise. The tone decoder consists of a PLL for analog signals,

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Figure 4.66

187

Block diagram of the NE567 integrated PLL by Texas instruments [7]. Courtesy Texas Instruments. (A): Input BPF; (B): PLL phase detector; (C): CCO with sine/cosine outputs; (D): PLL low-pass filter (R2 and external C2 ); (E): Synchronous AM detector multiplier; (F): AM detector filter (R3 and external C3 ; (G): threshold comparator with OC output.

combined with an AM synchronous demodulator. The block diagram of the NE567 is presented in Figure 4.66. The internal PLL generates the reference signal for synchronous AM demodulation (single branch, E in the diagram), then the demodulated signal is filtered and compared versus a threshold (G) to provide the tone/no tone information. This device is characterized by a very narrow bandwidth, which makes it possible to recognize the tone even when mixed with other signals and noise, and provides an ON/OFF output (tone detected/no tone). Intermediate taps in the AM detector chain (low-pass filter F) provide information on tone amplitude, and this allows us to use the device as a synchronous analog AM demodulator. The complete AM detector system includes three filters, as shown in Figure 4.66, namely the input BPF (A), the loop low-pass filter (D), and the AM detector output low-pass filter (F). The parameters of the tone decoder system are defined and discussed in the following, with reference to excerpt from the LM567 datasheet presented in Table 4.3. 4.5.2.2 Amplitude Domain Parameters

The input amplitude range (Table 4.3A and Figure 4.67) is defined by two parameters, namely the smallest detectable input voltage and largest no-output

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Table 4.3 Electrical Characteristics of the LM567 Parameter

Min

Value Typical

Max

A Input detectable amplitude range

Smallest detectable input voltage Largest no-output input voltage

10 mVrms

20 mVrms 15 mVrms

25 mVrms

B Noise performance parameters

Largest simultaneous out-band signal to inband signal ratio Minimum input ratio wideband noise ratio

6 dB −6 dB

C Frequency range

Largest detection bandwidth Largest detection bandwidth skew Largest detection bandwidth variation with temperature Largest detection bandwidth variation with supply voltage

Figure 4.67

14% of fo 1% of fo ±0.1%/◦ C ±1%/V

Capture range versus input signal amplitude and filter parameters, with linear (A) operation and (B) saturation regions [7].

input voltage. For a single device a single threshold is present: a tone with higher amplitude is detected, a lower one is not. When a set of ICs is addressed, ranges must be considered, due to fabrication tolerances, and not single values. The minimum parameter value is the smallest input that is definitely recognized by the tone decoder (maximum of the minimum levels among several devices); the

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maximum value is the largest input that is not recognized by the tone decoder (minimum of maximum levels). Input signals lower than 10 mV are never sensed; signals higher than 25 mV are always sensed. This is similar, to some extent, to the VIH and VIL specifications for logic circuits. 4.5.2.3 Effect of Noise and Interferers

The parameters for tone detection capability with noise or interferers are defined in Table 4.3B; a tone can be detected also if mixed with noise stronger than the tone itself, both for narrowband and wideband noise. 4.5.2.4 Frequency Domain Parameters

The frequency domain parameters are listed in Table 4.3C. The device is designed to recognize a specific frequency in a rather small range; for such application the PLL should lock only within a narrow frequency range, and the frequency shift required to the VCO is minimum. These characteristics drive the design of the VCO circuit. The frequency range in which the tone is detected is the largest detection bandwidth, which depends on the LPF (R2 , C2 ). This parameter refers to the key function of the device (tone detector), and it is specified also versus temperature and supply voltage changes. 4.5.2.5 Bandwidth and Filter Parameters

The relation between input signal amplitude, LPF parameters, and detection bandwidth is presented in Figure 4.67. Two regions with different operating conditions are shown. In the linear operation region (A), for amplitudes of the input signal smaller than 100 mVrms , the bandwidth is related to signal amplitude since the multiplier used as phase detector operates in linear region. In saturation (B), for signals higher than approximately 200 mVrms , the phase detector saturates, and the bandwidth (capture range) does not depend anymore on signal amplitude. 4.5.2.6 Detailed Internal Circuits: PD and AM Demodulators

The PLL phase detector and the AM synchronous demodulation use the Gilbert cell multiplier configuration described in Chapter 3 of this book. The multiplier core and the detailed circuit around the Gilbert cell are presented in Figure 4.68. The input differential stage is linearized by emitter feedback thanks to resistances R26 and R27. More details on Gilbert cells are provided in Section 3.1.6. 4.5.2.7 I-C Fixed Time Constant VCO

The circuit diagram presented in Figure 4.69 uses a single time constant (τ = RC ); frequency control is achieved by changing the thresholds (Vs1 , Vs2 ) of the comparators. This solution allows for limited frequency changes only, but

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Figure 4.68

Phase detector and AM demodulator multipliers [7]. (1): Gilbert multiplier core (double differential pair: Q34, Q35, Q36, Q37, plus differential Ie drivers: Q32, Q33); (2): vx input (vo from the VCO); (3): va input (vo from the VCO); (4): vy input (vi from the field); (5): output (current iZ ).

Figure 4.69

VCO with I/Q outputs. The quadrature signal vA is provided by the comparator T2. (a) Schematic diagram, and (b) waveforms on the capacitor (vC ), vA (dotted line), and vO (continuous line).

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Figure 4.70

191

Alternate VCO with I/Q outputs. (a) Block diagram of LMC567 [8]. Courtesy Texas Instruments, and (b) I/Q signals vcos and vsin obtained from the double frequency square wave v2o .

the circuit is used for intrinsic narrowband applications. The basic VCO uses two comparators; an additional one provides the quadrature signal for the AM detector. I/Q signals for loop lock and AM detection can be generated also with the technique shown in Figure 4.70. The VCO operates at double frequency, and I/Q signals are obtained from frequency dividers with inverted clocks. This approach guarantees the phase shift over any frequency range (with 50% duty cycle input clocks).

4.5.3 Analog-Digital PLLs The PLL operations can be carried out with analog or digital signals and circuits, resulting in a variety of mixed ADPLLs, where some function are performed by

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Figure 4.71

Example of DSPLL with analog PD and digital LPF and digitally controlled VCO (DVCO).

digital circuits, either wired (standard gates and FFs), programmable (FPGA), or in DSP software. A summary of choices can be: • Fully analog PLLs: both vi and vo are analog signals; the loop uses analog circuits for all functional units. • PLL with square wave VCO: vi is analog, vo is a square wave. This is a common case, since a square wave VCO is simpler than a sine wave one. Since vi is analog, all information is used. • PLL with square wave VCO and digital vi (square wave or pulses). If the original vi is an analog signal, then some information is lost in the transition to digital (the comparator senses only threshold crossing). These are sometimes called digital PLLs. • True digital PLL: most functional units use digital circuits: the PD, the filter, the VCO (which becomes a DVCO, e.g., using a synthesizer). The all-digital solutions include the digital signal processing PLL (DSPLL) (® by Silicon Labs [11]). Software solutions can provide programmable parameters, with better control of all functions. An example of DSP based PLL is shown in Figure 4.71.

4.6 MATLAB Scripts Listing 4.1

FM modulation

A=1; %Signal amplitude [V] fp0=150; %Central frequency [kHz] K=60; %Modulation index fM=10; %FM modulation frequency SamplesPerPeriod=25; %Number of points per period TEnd=1; %Considered time interval [ms] t=linspace(0,TEnd,TEnd*fp0*SamplesPerPeriod); %Time series [ms] N=length(t); %Number of points m=cos(2*pi*fM*t); %Modulation signal Im=sin(2*pi*fM*t)/(2*pi*fM); %Integral of the modulation signal y=A*sin(2*pi*fp0.*t); %Carrier yFM=A*sin(2*pi*(fp0*t+K*Im)); %FM signal %% Frequency domain df=1/t(end); %Freq. resolution [kHz]

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ff=-N/2*df:df:(N/2-1)*df; YFM=abs(fftshift(fft(yFM)));

Listing 4.2

%Frequency series [kHz] % FFT of the FM signal

AM modulation

A=1; %Signal amplitude [V] fp0=150; %Central frequency [kHz] fAM=10; %Modulation frequency [kHz] SamplesPerPeriod=25; %Number of points per period TEnd=1; %Considered time interval [s] t=linspace(0,TEnd,TEnd*fp0*SamplesPerPeriod); %Time series [ms] N=length(t); %Number of points Carrier=A*sin(2*pi*fp0.*t); %Carrier Mod1=1+0.5*sin(2*pi*fAM*t); %50% modulation, c=1, m=0.5 AM1=Carrier.*Mod1; Mod2=1+sin(2*pi*fAM*t); %100% modulation, c=1, m=1 AM2=Carrier.*Mod2; Mod3=sin(2*pi*fAM*t); %100% modulation, c=0 AM3=Carrier.*Mod3;

Listing 4.3

Digital signals modulation

A=1; %Signal amplitude [V] fs=100; %Frequency [kHz] Tbit=0.020; %Bit duration [ms] NumBits=100; %Number of bits to consider TEnd=Tbit*NumBits; %Sequence duration SamplesPerBit=200; %Samples in 1 bit dt=Tbit/SamplesPerBit; %Sampling time [ms] t=linspace(0,TEnd,SamplesPerBit*NumBits); %Time series [ms] N=length(t); %Number of samples bits=rand(1,NumBits)>0.5; %Random NumBits bits bits=repelem(bits, SamplesPerBit); %Value of the bit at each time %% FSK modulation fp0=fs; %Frequency of logical 0 [kHz] fp1=3*fs; %Frequency of logical 1 [kHz] fp=fp0+(fp1-fp0)*bits; %Modulated frequency yFSK=A*sin(2*pi*fp.*t); %FSK signal %% ASK modulation A0=A/4; %Amplitude of logical 0 [V] A1=A; %Amplitude of to logical 1 [V] yASK=sin(2*pi*fs.*t).*(A0+(A1-A0)*bits);%ASK signal %% PSK modulation yPSK=A*sin(2*pi*fs.*t).*(2*bits-1); %PSK signal

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References [1]

AD7008 CMOS DDS Modulator Tone Decoder, rev. B, https://www.analog.com/ media/en/technical-documentation/obsolete-data-sheets/389856510ad7008.pdf.

[2]

Best, R. E., Phase-Locked Loops: Theory, Design, and Applications, McGraw-Hill, 1993, Chapters 2, 3, 7.

[3]

Egan, W. F., Phase-Lock Basics, Wiley, 2007.

[4]

Foster, D. E., and S. W. Seeley. “Automatic Tuning, Simplified Circuits, and Design Practice,” Proceedings of the Institute of Radio Engineers, Vol. 25, No. 3, March 1937, pp. 289–313, DOI: 10.1109/JRPROC.1937.228940.

[5]

Gardner, F. M., Phaselock Techniques, John Wiley&Sons, 2005.

[6]

Gibson, J. D., Principles of Digital and Analog Communications, Macmillan, 1993.

[7]

LM567xTone Decoder, rev. December 2014, http://www.ti.com/lit/ds/symlink/lm567c.pdf.

[8]

LMC567 Low-Power Tone Decoder, rev. December 2015, http://www.ti.com/lit/ds/ symlink/lmc567.pdf.

[9]

Morgan, D. K., CD4046B Phase-Locked Loop: A Versatile Building Block for Micropower Digital and Analog Applications, http://www.ti.com/lit/an/scha002a/scha002a.pdf.

[10]

Oppenheim, A.V., A.S. Willsky, and S.H. Nawab, Signals and Systems, Prentice Hall, 1997.

[11]

Silicon Labs DSPLL Technology, https://www.silabs.com/products/timing/oscillators/dspll.

[12] Widmer, A. X., and P. A. Franaszek, “A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code,” IBM Journal of Research and Development, Vol. 27, No. 5, September 1983, pp. 440–451, DOI: 10.1147/rd.275.0440.

Selected Bibliography Banerjee, D., PLL Performance, Simulation, and Design, Dean Banerjee Publications, 2003. Blanchard, A., Phase-Locked Loops: Application to Coherent Receiver Design, Wiley, 1976. (Emphasis on theory, few details of applications.) Collins, I., “Phase-Locked Loop (PLL) Fundamentals,” Analog Dialogue, 2018, https://www.analog .com/media/en/analog-dialogue/volume-52/number-3/phase-locked-loop-pllfundamentals. Franco, S., Design with Operational Amplifiers and Analog Integrated Circuits, McGraw-Hill, 2002, Chapter 13. Goldberg, B. G., Digital Frequency Synthesis Demystified: DDS and Fractional-N PLLs, Demystified Series, LLH Technology, 1999. Lee, T. H., The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, 2004, Chapters 15, 16. Sayre, C. W.,Complete Wireless Design (Second Edition), McGraw-Hill Education, 2008, Chapter 5: PLL. Stephens, D. R., Phase-Locked Loops for Wireless Communications: Digital and Analog Implementation, Springer, 2012.

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5 Analog-to-Digital and Digital-to-Analog Conversion The signals exchanged between the real world and an electronic systems are physical quantities represented by analog voltages and currents; that means they can assume any value within defined ranges, and are defined at any time within an interval. Such signals are processed by the electronic system, transmitted over a communication channel, or stored on a media. All these processes add noise to the signal. If the signal is maintained in analog form, this noise addition is not reversible. On the other hand, if the signal is converted into a digital form, the noise can be removed, within certain limits. The robustness of digital representation of quantities compared to the analog counterpart is a reason for the success of digital systems and for the continuous shift of electronics toward fully digital solutions. In addition, digital systems are more easily made programmable via software. For these reasons, almost all electronic systems have today a digital core, with an ADC front-end at the input and a DAC back-end to interact with the external analog world. This chapter describes the most relevant ADC and DAC techniques, with an emphasis on telecommunication applications. In the transceiver used as guideline in this book (Figure 1.35), the boundary between analog and digital circuits is close to the user side, in the audio frequency section, but it can actually be placed in several positions, depending on available technology and design choices, as already outlined in Chapter 1. Most radio structures use analog circuits in the RF section, close to the antenna, and digital circuits towards the user end. Moving the ADCs and the DAC closer to the respectiveTX and RX antennas is an enabling factor for the development of SDR, as outlined in Chapter 1. 195

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In this Chapter, the first Section addresses the fundamental operations for analog-to-digital conversion, (i.e., sampling and quantization), and discusses the effects of sample rate and quantization on the information carried by a signal. The following sections describe techniques and circuits for the various parts composing a conversion system: DACs (Section 5.2), ADCs (Sections 5.3 and 5.4), the various functional units for the signal conditioning chain, and circuits for the sample&hold (Section 5.5).

5.1 Digital Representation of Analog Quantities The operation of turning a signal from analog to digital is the analog-to-digital conversion process; the opposite is the digital-to-analog conversion. Both these operations have intrinsic limitations and errors which cause loss of information. This section analyzes the conversion processes, in order to identify and evaluate these errors, and identifies the conditions which keep them within assigned limits. The analysis here is only at the functional level, independent of the actual circuits used for the ADC and DAC units. 5.1.1 Analog Quantities and Digital Quantities An analog quantity is continuous in the time and in the amplitude domains; it is defined at any time position (in a defined interval), and can assume any value (within a defined range). A digital (or numeric) quantity is basically a sequence of numbers that can assume a limited set of values (related to the number of digits used in the representation), and defines the quantity only at a discrete set of time instants. An example of analog and digital representations for the same variable is shown in Figure 5.1. Therefore, the conversion from analog to digital requires two steps: 1. Change the time-continuous quantity (solid line in Figure 5.1(a)) in a time-discrete one (arrows). This process is the sampling, and the discrete time quantities are the samples. 2. Approximate each sample (which is an analog quantity) with a numeric representation, which can assume only a discrete set of values (filled dismonds in Figure 5.1(b)). This process is called quantization. The final result is a sequence of numbers, representing information defined only at discrete time points and which can assume only a finite set of values. Numbers represented with N digits base B can have B N different values. Analog signals can assume any value, and additive noise cannot be separated from the signal value. With discrete amplitude digital signals a limited amount of noise can be tolerated (noise margin), and the clean signal can be reconstructed using threshold comparators. This is one of the reasons for the increasing use of digital techniques.

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Figure 5.1

Steps for analog-to-digital conversion of signal A(t ). (a) Sampling: the solid line represents an analog quantity, the arrows indicate the sampling process occurring at discrete times spaced by Ts , and (b) quantization: the black points and the value numbers represent the digital quantity corresponding to each sample.

Going from analog to digital potentially implies a loss of information: sampling describes the signal values only at specific time positions, and quantization approximates continuous quantities with discrete values. This section discusses the amount of these losses. 5.1.2 Sampling Process An analog quantity is defined at any point in time, and can assume any value (in limited time and value ranges); it is continuous in the time and in the amplitude axis. The first step of the analog-to-digital conversion process is called sampling, which moves the signal representation from continuous to discrete time. Let x(t) be an input signal continuous in time (a voltage, for instance). As shown in Figure 5.2, the process of sampling with a sampling interval Ts = 1/fs turns the signal x(t) first into a pulse train xs (t), which is then converted to a discrete time sequence x[k], with k integer. The amplitude of each sample x[k] corresponds to the value of x(t) at the sampling time tk = kTs : x[k] = x(kTs ).

(5.1)

The sequence of samples x[k] represents the original signal x(t) at the sampling times; the values at intermediate times are lost in the sampling process. This can be seen as loss of information in the time domain, which corresponds to a limit in the signal bandwidth that can be quantified operating in the frequency domain. As discussed in Section 1.5, the impulse train xs (t) in the time domain is given by xs (tk ) = x(t) ×

∞


δ(t − kTs )

(5.2)

k=−∞

and in the frequency domain, its spectrum Xs (f ) can be obtained as the convolution (
) of the continuous signal spectrum X (f ) and the Fourier

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Figure 5.2

Effects of sampling in the time (I) and in the frequency (II) domains. (a) Original baseband signal x(t ), X(f ); (b) sampling function (sequence of pulses): s(t ), S(f ); (c) sequence of samples: xs (t ), Xs (f ); gray areas represent the aliases generated by sampling.

Figure 5.3

Sampling process. The signal x(t ) is first converted into the continuous time pulse train xs (t ), and then into the discrete time series x[k ].

transform of the Dirac comb:    ∞ ∞  
1
k δ(t − kTs ) = X f − Xs (f ) = X (f )
F  T  Ts k=−∞

 ∞ 1
k 1 . X f − = X (f ) + T T Ts

(5.3)

k=−∞

(5.4)

k=−∞ k=1

Figure 5.3 shows how the sampling changes the spectrum of a signal. The sampling creates aliases, and as a result frequency-limited signals become unlimited in the frequency domain. This corresponds to a basic principle: signals limited in time are unlimited in frequency, and any signal limited in frequency is unlimited in time. For the analysis in this chapter, the relevant frequency range is [0, 2fs ].

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Figure 5.4

Sampling a band-limited signal. The RF signal with bandwidth B is moved to baseband, and several other aliases are created. (1) Sampling rate fs ; (2) RF signal; (3) aliases created by sampling; (4) baseband alias.

Figure 5.5

Reconstruction of time-continuous signals from samples with low-pass filter. X(f ): input signal (black lines); Xs (f ) sampled signal (gray lines) (a) signal at frequency f1 < fs /2 (complies with Nyquist rule): a low-pass filter can recover the original signal; (b) signal at frequency f2 > fs /2: the violation of the Nyquist rule creates fake in-band signals (gray line at fs − f2 ) and low-pass filters cannot recover the original signal.

5.1.2.1 Sampling Theorem

Sampling a limited spectrum signal creates an unlimited spectrum signal; secondary spectra (aliases) are separated by intervals fs = 1/Ts , as shown in Figure 5.4. The aliases must be removed with a low-pass filter in order to reconstruct the original signal x(t) from the sequence of samples. Real filters can attenuate—but not completely remove—unwanted frequencies. Therefore, in the real world any signal should be considered to have unlimited bandwidth: the spectra in the right side of Figure 5.3a are only approximations. However, the power in some frequency ranges can be very low, and signals with power lower that a defined threshold can be considered zero. A sampled signal can be reconstructed, under this approximation, by keeping only the main part of the spectrum, as shown in Figure 5.5. The isolation of the main spectrum is feasible only if aliases do not overlap (i.e., if the sampling rate fs is higher than twice the signal bandwidth 2B).

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Figure 5.6

Real signals and aliasing noise. (1) Baseband signal; (2) first alias; (3) aliasing noise, folded into baseband.

It is important to observe that what matters is the bandwidth of the signal, and not its specific signal frequency: a 1 GHz signal can be correctly sampled at 1 kSPS, provided that all its spectral components are within 1 kHz of the 1 GHz central frequency. To satisfy the Nyquist criterion and to avoid loss of information, a signal must be sampled at a rate at least twice the bandwidth. Therefore, the input signal must be band-limited to B < fs /2 using a low-pass filter on the input: this is the anti-aliasing filter. Filters have finite attenuation, and signals in the real word have finite duration, which means unlimited bandwidth. Therefore some energy above fs /2 will always reach the ADC system, and these high-frequency components that are folded into baseband cause aliasing noise, as shown in Figure 5.6. The amount of this noise depends on the input signal frequency spectrum, on the frequency response of the anti-alias filter, and on the sampling frequency fs . The same issues are found at the transmitter side of the processing chain: the time-discrete sequence of analog values from the digital-to-analog converter has multiple spectra. A low-pass filter or a BPF must be used after the DAC, to deliver only the desired frequency components. 5.1.2.2 Oversampling and Undersampling

Sampling just above the Nyquist limit requires a sharp cutoff anti-aliasing filter, which can be expensive and difficult to design. Another choice is to sample at a rate much higher than the Nyquist limit, to relax the specifications of the antialiasing filter. This oversampling generates a larger throughput of digital data. The higher bit rate places more heavy requirements on the digital processing, and requires wider bandwidth for the transmission. The bit rate however can be reduced after the ADC using digital filters (instead of the analog one required to limit bandwidth before the ADC). Oversampling basically moves the complexity from the analog to the digital part of the system, allowing more flexible and lower cost solutions. An example of the Nyquist criteria that a signal must be sampled at least twice the signal bandwidth: a 1 GHz carrier with 100 kHz AM (side lobes 100 kHz from the carrier, total bandwidth 200 kHz) can be safely sampled at rate higher than 400 kSPS (and not GSPS). That means far less stringent specifications for RF

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ADCs, but tighter requirements for the sampling circuit, because the sampling jitter error is related to carrier frequency, not to signal bandwidth. Sampling at a rate lower than twice the signal frequency may create aliases overlapped with the original signal, as in Figure 5.6. This undersampling, however, can be performed on band-limited signals under proper conditions. Undersampling is used in digital radio receivers (and transmitters) to move the analog-to-digital transition closer to the RF section, as discussed in Chapter 1. 5.1.2.3 Sample&Hold Operation

The ADC operates on single samples, and each conversion requires some amount of time. The input signal must not change during the conversion time, therefore two operations are required before the A/D conversion: 1. Sample: read the analog signal value at a specific time; 2. Hold: keep that value for some amount of time. These operations are carried out by a sample&hold (or track&hold ) unit, as shown in Figure 5.7. The hold operation modifies the spectrum. Pulses originated by sampling become steps, with a width TH , and the signal spectrum is multiplied by sinc(πTH f ): this function has zeros at f = 1/TH . This causes an attenuation of high frequency components, as shown in Figure 5.8, which results in a distortion of the sampled signal. As Hold commands become narrower, the spectrum envelope of the sampled signal becomes wider: for TH = Ts (hold till next sample), the spectrum envelope is 0 at f = fs ; for TH = 0 (delta function), the spectrum envelope becomes flat. Time and frequency behavior for sampled and held signals is presented in Figure 5.8. The hold operator can be written as: H1 (f ) =

Figure 5.7

sin(πTS f ) −jπTS f e . πf

(5.5)

Sample&hold operation: continuous signal samples (vertical arrows) and values held till the next sampling operation (horizontal bars).

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Figure 5.8

Sample&hold effect in the (a) time and in the (b) frequency domains. The signal spectrum is multiplied by a sinc function.

Figure 5.9

Correction of spectral attenuation caused by hold: sinc curve (1), hold attenuation caused by sampling (2), Hold attenuation compensation (3). (a) Spectral attenuation caused by the hold operation. (b) Overall block diagram.

The attenuation of signal components near fs can be corrected with a peaking of the HF response, in the anti-alias input low-pass filter or in the reconstruction filter after the DAC. The spectral distortion caused by the hold operation can be corrected by a compensation filter H2 (f ), which modifies the spectrum in a complementary way (Figure 5.9). This compensation can occur in the ADC chain or in the DAC chain, in the reconstruction filter: H2 (f ) =

πf H0 (f ) = e jπ TS f . H1 (f ) sin(πTS f )

(5.6)

5.1.2.4 Reconstruction Filter

At the output of the digital processing chain, the signal to the DAC is a sequence of samples, therefore includes secondary spectra (aliases). To get a smooth continuous signal the spectral replicas are removed by a low-pass reconstruction filter at the DAC output. The reconstruction filter can correct spectral attenuation caused by hold with peaking near the high band limit, as shown in Figure 5.9(a). 5.1.3 Quantization Process In analog-to-digital conversion, a number D is assigned to an analog value A within a defined range [−S/2, +S/2] or [0, +S]; in the following the latter

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Figure 5.10

DAC output in the (a) time and (b) frequency domains. Steps (1) represent the direct DAC output; continuous line (2) is the filtered DAC output; (3) aliases are removed by the (4) reconstruction low-pass filter.

Figure 5.11

The quantization process. Conversion for a [0,S] analog range to 2N digital values, close-up of a quantization interval AD and definition of the quantization error q .

definition will be used. Since the analog quantity can assume infinite values, and numbers represented by N digits on a base B can assume only B N values, a rule for relating the analog ranges to the digital values is required. If binary numbers are used, B = 2, and 2N digital values are possible. This process is graphically described in Figure 5.11. Different analog values within the same AD range are represented by the same digital number, and this introduces a quantization error q . A digital value D defines an interval, not an exact value. With linear (also called uniform) quantization the range [0, S] is divided in 2N equal intervals; for linear quantization the maximum quantization error qm is S (5.7) |qm | ≤ AD /2 = N +1 . 2 For some specific applications, nonlinear quantization can reduce the error power, as discussed in Section 5.4. The quantization process can be represented on an X , Y diagram, as in Figure 5.12. The input quantity A is on the horizontal axis, and the output D (a set of integer numbers) is reported on the vertical axis. Each D value represents a set of analog A values, therefore the transfer function is a staircase: each interval AD corresponds to a single D value.

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Figure 5.12

X,Y representation of the quantization process.

Figure 5.13

Quantization error q versus A input

Figure 5.14

Model for the errors introduced by the two steps in the analog-to-digital process. (1) Sampling with spectral folding; (2) quantization with quantization error.

The quantization error q varies between ±AD /2 (or ±1/2 LSB), and is maximum at the edges of the interval AD , as shown in Figure 5.13. When the number of digital values increases (i.e., as the digital representation uses more bits), the staircase step amplitude becomes smaller, and the diagram looks more like a line (a straight line for linear/uniform quantization). The quantization error cannot be recovered: a single digital value identifies all analog values in the range AD , not the exact value within that interval. Quantization is equivalent to an operation that adds a noise q to the analog signal. The power of this noise depends on the quantization interval and the error amplitude distribution. This noise adds to errors caused by sampling described in the previous section; an overall model can be defined for the effects of sampling and quantization, as shown in Figure 5.14.

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Figure 5.15

205

Examples of amplitude distribution. (I) Time domain signal A(t ); (II) signal amplitude Probability Distribution Function. (a) Triangular wave with power Ps = S2 /12; (b) sine wave, Ps = S2 /8; (c) voice, Ps = S2 /36; shaded areas indicate out-of-range values.

5.1.3.1 Signal Amplitude Distribution

For a fixed signal range, it is possible to calculate the ratio between the signal power and the power of the quantization noise, which is generally indicated as SNRq , and depends on signal shape and on the number N of bits of the digital representation. It also depends on the amplitude distribution of the signal, which defines the probability for the signal values to be in a defined interval. This distribution is called probability density function (PDF) and is related to signal waveform; examples of PDFs for some signal waveforms are presented in Figure 5.15. When only statistical parameters are known, the signal power can be evaluated from the amplitude distribution. Assuming a small quantization interval AD , the probability of finding any value of the input signal within AD is approximately equal, therefore for any input waveform the PDF of quantization error q is approximately flat. 5.1.3.2 Quantization Noise Power

The power of a signal can be obtained from its amplitude distribution; for the quantization noise:

+AD /2 σ2q = q 2 ρ(q )dq (5.8) −AD /2

but since AD is supposed to be small, the amplitude distribution of ρ(q ) in this interval can be considered flat: 1 ρ(q ) = (5.9) AD

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and the power of quantization noise Pq can be finally calculated as  A2 1 AD 3 2 = D. Pq = σ2q = 12 3 2 AD

(5.10)

5.1.3.3 SNRq for Some Specific Signals

The signal-to-quantization noise power ratio SNRq is defined as the ratio of the signal power Ps and the power Pq of the quantization noise q : SNRq =

Ps . Pq

(5.11)

The signal power depends on the waveform and the amplitude; the quantization noise power is related to the quantization step size AD , which in turn depends on full-scale amplitude S and bit number N since AD = S/2N . Table 5.1 summarizes SNRq for various waveforms with the same peak amplitude S. Since signal power Ps depends on the waveform, different values of SNRq are obtained depending on the waveform. For example, a sinusoidal waveform x(t) with frequency f0 = 1/T0 and spanning the full range [−S/2, +S/2] can be written as x(t) = S2 sin(2πf0 t). The associated power is

T0 2 S2 S 1 S2 1 Ps = sin2 (2π f0 t)dt = = . (5.12) T0 0 4 4 2 8 The value of SNRq can be calculated as SNRq =

Ps (2N AD )2 12 = = 1.5 × 22N , 2 Pq 8 AD

(5.13)

and can be expressed in decibels recalling that log 10 2 ≈ 0.301 and log 10 1.5 ≈ 0.176: 

Ps  2N SNRq |dB = = 10 log 1.5 × 2 ≈ (6N + 1.76) dB. (5.14) 10 P  q dB

Table 5.1 Signal Power and SNRq for Common Waveforms Waveform Sine Triangular wave Square wave, 50% duty cycle Voice, assuming a Gaussian PDF with S/2 = 3σ

Power P s

SNRq |dB

S2 /8 S2 /12 S2 /4 S2 /36

6N + 1.76 6N 6N + 4.80 6N − 4.77

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Figure 5.16

207

SNRq versus resolution N and amplitude A. (a) SNRq versus the number of bits N for various notable waveforms; (b) SNRq versus signal amplitude A for sine wave (SNRq,max |dB = 6N + 1.76); 6 dB/octave or 20 dB/decade slope.

Results obtained for other signals commonly found in telecommunication are presented in Table 5.1; the reported examples confirm that signals with narrow PDF have reduced power, resulting in a lower associated SNRq . 5.1.3.4 SNRq versus Signal Amplitude and Number of Bits

For full-scale signals, SNRq can be written in a general form as SNRq |dB = 6N + K

(5.15)

with K depending on the signal waveform (amplitude distribution). Each additional bit divides the maximum quantization error q by a factor of 2, and it adds 6 dB to SNRq , as shown in Figure 5.16(a). For signals having a peak amplitude As smaller than the full-scale S, the SNRq decreases with unitary slope (−20 dB/decade or −6 dB/octave), and can be expressed as (5.16) SNRq |dB = As /S + 6N + K . For out-of-range signals (As > S) the A/D conversion saturates at full-scale. This situation is called the overload condition; in this zone the SNRq decreases very rapidly.

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The correct operating range for an ADC is shown in Figure 5.16. For signals with low amplitude levels, the boundary is the quantization noise; for signals exceeding the limits of the analog range, overload causes saturation of the ADC, quickly decreasing SNRq . If the number of bits N is reduced (increased), the SNRq versus As curve is moved 6 dB down (up) for each 1 bit decrease (increase) of N . 5.1.3.5 Quantization Noise Spectrum

The quantization noise has a flat power distribution from 0 to fs /2 [2]. The spectral power density of quantization noise Nq (f ) is therefore: Nq (f ) =

2 AD 2 S2 1 1 = . 12 fs 12 22N −1 fs

(5.17)

To reduce the quantization noise power density (and therefore improve the SNRq for a defined bandwidth) it is possible to increase the number of bits N in the ADC, thus reducing the quantization step amplitude and in turn the power of quantization. Another possibility is to increase the sampling rate fs (oversampling ), in order to spread the quantization noise power over a wider bandwidth. 5.1.4 Analog-to-Digital Conversion Systems The previous sections presented the fundamental steps for analog-to-digital conversion: 5.1.4.1 Sampling

The sampling process provides the value of analog input at specific time instants. This operation is carried out by the sample&hold function. In most systems the unit is actually a track&hold: the output tracks the input signal, and holds the same value at the track-to-hold transition. For a correct operation the sampling rate fs must be higher than twice the signal bandwidth B: (5.18) fs > 2B which means that the sampled signal must have a known bandwidth; therefore an anti-aliasing filter must be placed before the ADC. 5.1.4.2 Quantization

Mapping a continuous value (A) into a discrete one (D) implies a loss of information. To minimize this error, the ADC must operate as close as possible to full-scale, but not exceed it. This means an amplifier must be placed before the ADC to bring the signal close to full-scale, and a limiter added to avoid overload. The above conditions are performed by proper signal conditioning at the input of the ADC system; before sampling and ADC some elements are needed: • Input protection devices, to limit input voltage and avoid damages to the system;

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• A conditioning amplifier, to adapt signal level to ADC full-scale and buffer the signal source from the ADC input; • An anti-alias filter, to limit signal bandwidth. A single S/H-ADC pair can be used for several channels by placing a multiplexer before the S/H, as shown in Figure 5.17. Each channel must have an independent signal conditioning chain (protection, amplifier and filter). The digital-to-analog chain includes the same functional units as the ADC system, in reverse order: • A DAC, which translates binary numbers into analog values; • A low-pass filter, to remove aliases coming from the time-discrete signal; • A conditioning amplifier, to adapt voltage/currents from the DAC to the load. 5.1.4.3 Total Error

In the ADC system, each unit introduces errors and noise: • Amplifier: gain, offset, nonlinearity, band limits; • Filter: limited attenuation of out-band signal; • Sample&hold: aliases folded into useful band, sampling jitter, input feed-through; • Multiplexer: feed-through from unused channels; • ADC: quantization error and distortion due to nonlinearities in the converter. The actual accuracy of the conversion system depends on all these elements, not just on the number of bits N of the A/D. The key parameter is the total signalto-noise ratio (SNRT ) which takes into account aliasing, quantization, sampling jitter, and other errors (amplifier, multiplexer, nonlinearities, etc.). These errors are not correlated, and the evaluation of the total error sequence is possible

Figure 5.17

Complete multichannel data acquisition and delivery chain. P: input protection; A1: input amplifier; F: input anti-alias filter; Mux: (optional) multiplexer; S/H: sample&hold unit; ADC: analog-to-digital converter; C: digital transmission or processing channel, DAC: digital-to-analog converter; R: reconstruction anti-alias filter; A2: output amplifier.

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as follows: 1. Evaluate the power Pn,i associated to the error source i: Pn,i = Ps 10−

SNRi 10

.

(5.19)

2. Evaluate the total error power Pn,T as the sum of the single errors power:
Pn,i . (5.20) Pn,T = i

3. Evaluate the signal-to-noise ratio SNRT :

 
Pn,i Ps . → SNRT |dB = −10 log 10 SNRT = Pn,T Ps

(5.21)

i

5.1.4.4 Effective Number of Bits

The Signal-to-Noise ratio of the complete ADC system (SNRT ) can be expressed using the effective number of bits (ENOB), a parameter that includes all noise/error sources (quantization, aliasing, sampling jitter, etc.) An expression of this quantity can be obtained by solving (5.14) for N , and using the total SNR:  1 SNRT |dB ENOB = − 0.3dB. (5.22) SNRT |dB − 1.76 = 6 6 The ENOB represents the number of ADC output bits which can be considered correct (i.e., not modified by errors of the A/D conversion system). Usually, it takes into account quantization, aliasing, and sampling jitter errors. The sampling operation translates all spectral lines into the [0 − fs /2] range; this creates a mixed spectrum, where harmonics and other distortion terms are moved in the Nyquist zone (below fs /2). This effect is called harmonic folding. A key parameter for ADC system overall performance is the SFDR. An example of harmonic folding is presented in Figure 5.18. It includes effects of sampling, anti-alias filter, and distortions in the chain. In the example of Figure 5.18, the third harmonic is the largest spurious, and it is therefore used to evaluate the SFDR. 5.1.4.5 Summary of Error Terms

The various errors of an analog-to-digital conversion system, and the related SNR parameters, are: • Pn : Noise power (generic); • Pd : Power of the harmonics (up to a defined order, typically 5, sometimes 7 or 9); • Ph : Power of the highest spurious signal a harmonic in most cases;

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Figure 5.18

Spectrum of sampled signal: error terms from harmonic folding and distortion. (1) Fundamental; (2) sampling rate; (3) SFDR; (4) largest spurious component (harmonic 3); (4-i) i -th harmonic (dark gray); (5) folded fundamental; (5-i) folded i -th harmonics (light gray); (7) other spurious components (dotted lines); (8) usable bandwidth (half of sampling rate).

• Pa : Aliasing noise power; • Pj : Jitter noise power; • Pq : Quantization noise power. The following specific figures of merit describe the errors related to these parameters • Total Harmonic Distortion THD THD = 10 log 10

Ps ; Pd

Ps ; Ph • Signal-to-Noise And Distortion ratio SINAD SINAD = 10 log 10 Ps . It can be measured in decibel towards the carrier (dBc) or Pd + Pn decibel towards full-scale (dBfs); Ps • Signal-to-Noise Ratio SNR SNR = 10 log 10 . For ADC systems, the Pn SNR can be referred to specific types of noise or errors, such as; Ps • Signal-to-Aliasing Noise Ratio SNRa = 10 log 10 ; Pa Ps • Signal-to-Sampling Jitter Ratio SNRj = 10 log 10 ; Pj Ps • Signal-to-Quantization Noise Ratio SNRq = 10 log 10 . Pq • Spurious Free Dynamic Range SFDR SFDR = 10 log 10

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These errors are not correlated, therefore the total error power Pe,T is the sum of single error powers (jitter, noise and quantization). The total signal-to-noise ratio SNRT can be evaluated from  Pn,i 1 Pe,T . (5.23) = → SNRT |dB = −10 log 10 PS PS SNRT 5.1.4.6 Binary Representations

The digital representation of analog quantities can use different representations. Most of the issues discussed in this chapter do not depend on the representation used. Translation from a representation to another requires only combinatorial logic. In linear codes, all bits have the same weight; they are used for, flash ADC and delta/sigma ADC. Other ADCs use weighted codes, where the value of a digit depends on its position, with various possibilities to represent negative numbers. Binary codes represent quantities as binary numbers. In binary code decimal (BCD) each 4-bit group represents a decimal digit. In Gray codes a value change of 1 LSB modifies only 1 bit in the digital representation; they are used to avoid temporary spurious states in time-varying signals. A summary of the most-used binary representations, including negative numbers encoding, is presented in Table 5.2. The examples of ADC and DAC circuits in this chapter uses only positive numbers, represented as straight binary, unless differently specified.

5.2 Digital-to-Analog Converters Digital-to-analog converters transform the input digital number into an analog quantity (usually a voltage or a current) at its output. They will be firstly analyzed as a black box focusing on external behavior, defining the main parameters and introducing the error taxonomy, and then presenting the most common techniques and circuits. The circuits described as examples are unipolar DACs; some solutions to obtain bipolar output and full four-quadrant converters are presented at the end of this section. 5.2.1 Static and Dynamic Parameters During this analysis, the static DAC behavior will be discussed at first, then the dynamic behavior of the digital-to-analog conversion will be presented. For a DAC, the input variable is a digital quantity D, which is intrinsically discrete; therefore its transfer function A(D) is a sequence of dots, as shown in Figure 5.19(a), where each dot represents the output value Ai corresponding to the input number Di . On the x-axis (input D), the dot spacing is one least significant bit (LSB), while on the y-axis (output A) the dots are spaced by a quantity AD ,

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Table 5.2 Comparison of Different Encoding

Value

Fraction of Full-Scale S

7 6 5 4 3 2 1 0+ 0− −1 −2 −3 −4 −5 −6 −7 −8

+7/16 6/16 5/16 4/16 3/16 2/16 1/16 0 0 −1/16 −2/16 −3/16 −4/16 −5/16 −6/16 −7/16 −8/16

Figure 5.19

Offset Binary

Value and Sign

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

111 110 101 100 011 010 001 000 111 110 101 100 011 010 001 000 –

111 110 101 100 011 010 001 000 000 001 010 011 100 101 110 111 –

Two’s Complement 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

111 110 101 100 011 010 001 000 000 111 110 101 100 011 010 001 000

One’s Complement 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

111 110 101 100 011 010 001 000 111 110 101 100 011 010 001 000 –

Gray Code 1000 1001 1011 1010 1110 1111 1101 1100 1100 0100 0101 0111 0110 0010 0011 0001 0000

DAC characteristic. (a) Actual (discrete) characteristic, and (b) continuous representation (many points, small steps).

which corresponds to a 1 LSB change in input. The total number of points is M = 2N ; for sufficiently large values of N the diagram has many closely spaced dots, so that the dot sequence appears as a continuous line. If the dot spacing is constant in both the horizontal and vertical directions, then the dots are aligned on a straight line: this corresponds to a linear DAC. This ideal transfer function AI (D)I is shown in Figure 5.19. 5.2.2 Errors in Digital-to-Analog Converters In a real system, the vertical amplitude steps AD have different values, therefore the dots are not aligned, and two types of errors can be identified. Static errors occur for constant input, and define the DAC steady state behavior. These errors

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Figure 5.20

Error taxonomy for DAC characteristic, with definition of inl . (a) Ideal (1) and actual (2) characteristics, (b) actual characteristic (2) versus linear approximation (3) with inl integral nonlinearity error, (c) ideal (1) versus linear approximation (3) with gain error (g ) and offset error (o ), and (d) complete view and overall error mask (4) as maximum deviation from ideal.

are shown in the Cartesian A(D) transfer function diagram. Dynamic errors occur with a variable input signal, and define the frequency response and the transient behavior. In the (A, D) Cartesian diagram, the transfer function should be a straight line, ranging from the origin (0, 0) to full-scale (S, M ). The actual transfer function is not a straight line, and may not even include the above specified points. The error analysis is performed in two steps, as detailed in Figure 5.20: 1. First, the straight line AL (D) is calculated (1) which best approximates (using 1st order least square approximation) the actual AR (D) transfer function (2); 2. Then, the actual AR (D) characteristic is compared to the ideal transfer function AI (D), to extract linear and nonlinear errors. The linear errors, namely offset and gain, can be obtained observing the difference between the linear approximation AL (D) and the ideal transfer function AI (D). The nonlinearity errors result from the analysis of the difference between the linear approximation AL (D) and the actual transfer function AR (D); 5.2.2.1 Linear Errors: Offset and Gain

As shown in Figure 5.20, the approximating straight line ideally goes across (0, 0) and (M , S) and can be written therefore as A = kD. The straight line ˜ and an which approximates the real transfer function has a different slope (k)

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Figure 5.21

215

Differential nonlinearity with (1) actual transfer function and (2) best linear approximation. (a) Definition of differential nonlinearity dnl , and (b) slope inversion (3), and nonmonotonic behavior: dnl,i < −1 LSB.

offset (o ), thus: k˜ =k + g

(5.24)

˜ + o = (k + g )D + o A =kD

(5.25)

where o is the offset error and g is the gain error. The offset error can be removed by adding a constant offset to the output. The gain error is defined as the difference between the ideal slope and the linearly approximated slope of the real device, and can be removed by gain correction. A relative gain error can also be defined as g G = . (5.26) k 5.2.2.2 Nonlinear Errors

In the ideal transfer function, the dot spacing on A-axis corresponding to 1 LSB on D-axis is AD . As shown in Figure 5.21, in the actual transfer function dot   − A is the differential nonlinearity spacing is AD,i = AD . The difference AD,i D (DNL) dnl,i :  − AD . (5.27) dnl,i = AD,i The DNL defines the local behavior of the transfer characteristic and is specific to each step. If the differential nonlinearity error is smaller than −1 LSB, then the A(D) transfer function has a slope inversion, as shown in Figure 5.21(b); the DAC is nonmonotonic because the output decreases with increasing input code. The maximum deviation from the linear approximation defines an integral nonlinearity error inl , which corresponds to the sum of the discrete differential nonlinearities: inl,i =

i


dnl,n

(5.28)

n=0

dnl,i = inl,i+1 − inl,i

(5.29)

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Figure 5.22

Transient response of a DAC for a stepped input from D1 to D2 , and definition of the settling time Tt . (1) Slew-rate limit; (2) order 2 transient; (3) final value.

The integral nonlinearity error inl specifies the maximum deviation of the transfer function from a straight line generally drawn through the endpoints of the actual transfer function. A sequence of dnl,i with the same signs creates a high inl on the overall transfer function. If the differential nonlinearities have alternate signs, the total deviation from 0 to any point can be small. Taking as reference the minimum square linear approximation is mathematically correct but hard to measure in a real system. For this reason inl is usually measured taking as reference the straight line drawn through the endpoints of the transfer function (endpoint linearity). Also, gain and offset errors are in most cases specified for the endpoints straight line. The complete set of gain, offset and nonlinearity errors is shown in Figure 5.20(d).

5.2.2.3 Dynamic Parameters: Settling Time and Glitches

As for any signal in a real system, the DAC output requires some time to reach a new value; this time is called settling time (Tt ). The output is considered settled when it permanently enters the interval ±1/2 LSB from final value, as shown in Figure 5.22. The settling time depends on dynamic parameters of the circuit providing the analog output, usually a series of switches often followed by an operational amplifier. Two key elements can be identified studying these dynamic effects, namely the linear behavior which can be modeled as a second order response (defined by its resonant frequency fR and its damping ζ ) and the slew rate (SRa) limit of the active circuits. During the transient, the DAC output can temporarily move to either 0 V or full-scale S, because of different switching delays of various bits, as shown in Figure 5.23. The temporary states may cause short pulses (glitches) at the output. Glitches are more likely to occur in MSB transitions such as from 0111 to 1000, where the temporary state during the transient can be 0000 or 1111, and they

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Figure 5.23

Output glitch from a DAC. (a) Different delays in switch operation cause faulty temporary states (e.g., 1111 and 0000 when moving from 0111 to 1000), and (b) glitch caused by a delay on MSB higher than other delays (from 0111 to 0000 to 1000).

Figure 5.24

Basic DAC block diagram. Linear DACs: M = 2N − 1; weighted DACs: M = N.

can be reduced by a synchronization register, which switches all the DAC input bits at the same time, or by limiting the output slew rate. The errors in a DAC can be specified as • Fraction of an LSB (e.g., 1/2 LSB, 1/4 LSB); • Percentage of full-scale; • Actual value, expressed, (e.g., expressed in millivolts or microvolts). The acceptable error depends on the number of bits. Large errors can make the LSBs meaningless: for example, in a 12-bit DAC (212 = 4096 values) with 1% errors (≈ 40 values, i.e. ≈5 bits), only the 7 MSBs are meaningful (27 = 128 values). 5.2.3 Circuits for Digital-to-Analog Conversion The DAC builds the analog output as the sum of elementary quantities (voltage V or current I ), controlled by the digital input D. The basic quantities are generated from a reference (again, V or I ), as shown in Figure 5.24. The elementary quantities can be either uniform (all with the same values: 1, 1, 1, . . .) or weighted (with values: 1, 2, 4, . . ., 2N ). With a uniform quantities DAC, the output is the sum of elementary weights with the same value (corresponding to a LSB); the input digital value controls the

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Figure 5.25

Uniform current DAC: the current IB is the same in each branch; IO = (D/2N )Vref /R. (a) Complete circuit, and (b) simplified equivalent circuit. Output IO typically drives an I/V converter.

number of units to be added. For example, the decimal quantity 13 is reproduced in output as the sum of thirteen unitary weights. With a weighted quantities DAC, the output is obtained as the sum of elementary weights corresponding to power of 2 (1 for LSB, then 2, 4, 8, . . .). Each branch i is controlled by the value (1/0) of the corresponding bit Di . The decimal value 13D , corresponding to the binary representation 1101B , is given as 8 × 1 + 4 × 1 + 2 × 0 + 1 × 1. 5.2.3.1 Uniform Quantities Digital-to-Analog Converters

The circuit presented in Figure 5.25 is an example of uniform elements DAC. The output current IO is the sum of a variable number of identical elementary currents controlled by the digital value D. An N -bit converter requires M = 2N − 1 identical branches, as shown in Figure 5.25. The same technique can be used for voltage output: the circuit in Figure 5.26 generates the output VO summing elementary voltage drops on a resistor chain. Since all resistors have the same value, all voltage drops are the same. The output tap is selected by the digital value D. This structure is a potentiometric DAC, sometimes called a string or thermometric DAC. 5.2.3.2 Weighted Quantities Converters

In a weighted element DAC the basic elements (usually currents) are obtained from a reference (e.g., the voltage Vref ) through a weighted network. The i-th current element Ii is enabled or blocked to the adder by the switch SWi controlled by bit Di of the digital input data D. In the circuit of Figure 5.27 the output current IO is the sum of a variable number of binary weighted elementary currents Ii ; the current flows in branch i when the bit Di is set to 1. The voltage drop on the Vref output resistance Rref is proportional to IO and modifies the actual Vref , causing a nonlinearity error. The circuit can be

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Figure 5.26

Uniform voltage drop (potentiometric) DAC: VO = (D/2N )Vref . (a) Complete circuit, and (b) simplified equivalent circuit.

Figure 5.27

Weighted currents DAC. (a) Complete detailed circuit, and (b) equivalent circuit.

Figure 5.28

Weighted currents DAC with current switches.

rearranged using current switches that steer currents towards nodes at the same voltage (ground). The new circuit is presented in Figure 5.28; compared to the previous one, now the load on the reference voltage source is equal to the parallel of all the weighted resistors and thus constant. Now the voltage drop on the Vref output resistance Rref is constant, and causes only a gain error because it modifies the actual Vref .

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Figure 5.29

If I1 = D(V1 ), then the same relation applies in the reciprocal network: I2 = D(V2 ).

Figure 5.30

Weighted currents DAC with voltage switches. The load on the reference voltage source is not constant, therefore Rref causes nonlinearity error.

5.2.3.3 Voltage and Current Switches

Linear passive networks are reciprocal : as shown in Figure 5.29, if the input V and the output I are exchanged, the I (V ) relation is maintained. By applying this principle to the network in Figure 5.28, it is possible to obtain the circuit of Figure 5.30, which is again a DAC. The weighted network uses voltage switches, which operate between nodes at different potential (Vref , ground). Now the current in Rref depends on D (as in Figure 5.27), and this may cause nonlinearity errors. The two circuits shown in Figure 5.28 and Figure 5.30 carry out the same function (D/A conversion), using respectively: • Current switches, which steer a current towards nodes at the same voltage (ground); • Voltage switches, which connect the weighted resistors to nodes at different voltages (ground, Vref ). For the circuit in Figure 5.30 the output equivalent resistance RO is constant; the equivalent circuit can use Thévenin/Norton equivalent V /I sources, keeping the same relation with the digital input D (Figure 5.31). That means that the output can be either the short circuit current to ground (as in the previous examples), or the no-load output voltage. A problem common to all these structures is the use of weighted elements (the resistors) with values spread over a wide range (from R to 2N −1 R). This can be an issue for integrated circuits: a wide range of resistor values would require large

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Figure 5.31

Norton and Thévenin equivalent circuits for the I-SW network DAC.

Figure 5.32

Ladder network: sequence of current dividers to generate I, I/2, I/4, I/8, . . ..

221

areas or different technologies, which makes matching difficult. This problem can be overcome using a ladder structure. 5.2.3.4 Weighted Network with Ladder Structure

In each branch of the weighted network, currents are scaled down by a factor of 2; the same current ratio can be obtained with a sequence of current dividers, where currents are divided among branches having the same impedance, as shown in Figure 5.32. Each cell of this network splits the current in two equal parts, then the splitting is repeated in the next cell. The structure is a ladder network, and it brings several benefits to the weighted currents generation structure. In fact, the network can be used for any number of bits; it uses only resistors with values R and 2R, which can exploit the same technology, with similar temperature and aging matching behavior. Following the same approach as for weighted-resistors network, the DAC converter with ladder weighted networks can use voltage switches or current switches, and the output can be either a current IO flowing to ground or the noload output voltage VO . The basic configurations are presented in Figure 5.33. For the circuits in Figure 5.33(a) and 5.33(c) the resistance Rref does not affect linearity, since the circuits sink a constant current from Vref . On the contrary, for the circuit Figure 5.33(b) the drop on Rref depends on D, potentially causing nonlinearity errors. 5.2.3.5 Capacitive Weighted Networks

The weighted network can also use charges instead of currents, with resistors replaced by capacitors. For a capacitor charged to a fixed voltage V , the amount of stored charge Q = CV is proportional to the capacitance C . With proper switch arrangements, charges can be added and converted into voltages. An example of

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Figure 5.33

Configurations for ladder-based DAC. (a) Current output, current switches, (b) current output, voltage switches, and (c) voltage output, voltage switches.

Figure 5.34

Example of DAC with capacitive weighted network.

a DAC with a capacitive weighted network is shown in Figure 5.34. For these circuits, the output accuracy depends on the capacitors matching. This technique is better suited for metal-oxide semiconductor (MOS) technology, where capacitor fabrication utilizes metallization and adds little cost during the manufacturing process, and the capacitance matching depends on area ratios.

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5.2.3.6 Error Analysis

Linear errors do not depend on the value D, and can be compensated because a unique correction value works across the complete dynamic range. Gain error can be caused by • Errors in the reference voltage Vref ; • Systematic error in the weighted network. Offset error can be caused by • Offset of operational amplifiers; • Leakage current of switches. Nonlinearity errors are related to the input digital value D; due to this dependence they are more difficult to compensate. Besides errors in the weighted network, they come from: • The equivalent resistance of switches Ron , which modifies the total branch resistance. The effect is the same as the weighted resistor errors. It can produce a linearity error unless the weighted resistors are modified to take Ron into account. • The leakage current of switches (Ioff ) causes an output current even when D = 0. This constant leakage causes an offset error; since the leakage is temperature dependent, it may also cause an offset drift. For weighted DACs, the errors in each branch affect the output proportionally to the branch weight. Each branch contributes to the output when the corresponding bit is 1 by a quantity related to the bit position: MSB weight is 1/2 (MSB-1 weight is 1/4, etc.). The output error corresponds to the branch error multiplied by branch weight, therefore the same percentage error in different branches causes different errors at the output. The effect is higher for the MSBs, so these branches must be more precise. In the example of Figure 5.35(a), the actual contribution from the MSB to the output is larger than ideal, and the effect is to raise the upper half of the characteristic, where the MSB is 1. Since the MSB contributes to 1/2 of the fullscale, a 10% branch error causes a 5% output error. In Figure 5.35(b), the error on MSB-1 is negative, and this causes a slope inversion when MSB-1 changes from 0 to 1. On the MSB-1 branch, the actual contribution is lower than ideal; the effect is to lower the odd quarters (1, 3) of the characteristic (Figure 5.35(b)). Since MSB-1 contributes to 1/4 of the full-scale, a 10% branch error causes a 2.5% output error. The sequence continues: a 10% error on MSB-2 branch causes an 1.25% output error, and so on. The critical parameter in these structures is the differential nonlinearity.

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Figure 5.35

Differential linearity errors dnl in weighted networks. (a) Positive error on MSB branch, and (b) negative error on MSB-1 branch causing slope inversion. (1): ideal A(D), (2) error on MSB, (3) errors on MSB-1 and slope inversion.

Figure 5.36

Effect of differential linearity errors with the same polarity in uniform networks. from 0000... to 0111... (1) dnl < 0 and the actual slope is lower than the ideal one; from 1000... to 1111... (2), dnl > 0 and the slope is higher than ideal. The integral nonlinearity error inl is maximum at S/2 (C).

With any DAC structure, the output error corresponds to the ratio of the branch error to the branch weight. Since in uniform D/A networks each branch has the same weight (1 LSB), and the output is the sum of elements with the same sign, the A(D) characteristic is intrinsically monotonic (no slope inversion). Errors of all branches sum up at the output. The critical parameter here is the integral nonlinearity. For instance, consider a potentiometric converter with systematic error in the resistor chain: +R in the upper half, −R in the lower half. The resulting DAC characteristic is shown in Figure 5.36: moving from 0 to full-scale, the errors sum up and, since they have the same sign, this causes a high integral nonlinearity. 5.2.3.7 Mixed Linear/Weighted (Segmented) D/A Converters

Uniform and weighted networks have different characteristics: weighted networks are rather simple (order N ), but need high precision, at least on the MSBs

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Figure 5.37

Mixed linear/coded DAC 2 MSBs: linear DAC; uses 2N − 1 = 3 branches (3 resistors and 3 switches). 4 LSBs: weighted DAC; uses N = 4 branches: weighted R or ladder network (4 resistors and 4 switches).

Figure 5.38

Example of mixed or segmented 10-bit DAC, 5 + 5 structure. (1) Weighted 10-bit input; (2) decoded 5 MSBs → 31 lines; (3) binary encoded 5 LSBs; (4) register for synchronization of bit changes; (5) current output.

branches, while uniform networks are more complex (order 2N ), but intrinsically monotonic. It is also possible to use mixed or segmented DAC structures, with uniform branches for more critical bits (MSBs), and weighted branches for LSBs, thus combining the benefits of both structures. An example of mixed D/A converter with linear DAC on 2 MSBs and weighted DAC on 4 LSBs is presented in Figure 5.37, while the block diagram for a 10-bit DAC with 5 bit linear + 5 bit coded sub-DACs is presented in Figure 5.38 Some devices use mixed structures with a different approach: bit groups are decoded into linear values, which drive branches of different weights. An example is presented in Figure 5.39. 5.2.3.8 Indirect Digital-to-Analog Converters

A DAC can use an intermediate quantity, such as time, to generate an analog output. The structure shown in Figure 5.40 translates the digital value D into the pulse width T1 , then a low-pass filter generates a DC proportional to the pulse areas. The circuit is very simple, and does not require precision elements; it is often used to get analog values directly from digital outputs and it is sometimes called a pulse width modulated (PWM) DAC. The drawback is its intrinsically slow response, due to the low-pass filter used to remove the ripple. For some applications (e.g., driving lamps or electric

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Figure 5.39

Example of 14-bit DAC with mixed structure (AD9775 TxDAC 14-Bit CMOS DAC Core, [6]). (1) Weighted 14-bit input; (2) decoded (linear) signals from 9 MSBs; (3) 5 LSBs direct drive to switches; (4) register for synchronization of bit changes; (5) 5 MSBs network (31 switches); (6) 4 intermediate bit network (15 switches); (7) 5 LSBs switches.

Figure 5.40

Example of indirect DAC: (1) D to duty-cycle converter, and (2) average (low-pass filter. (a) Block diagram, (b) D to pulse rate (fixed width Tw , variable rate Tr ), and (c) D to pulse width (fixed rate Tr , variable width Tw ). Often called a PWM DAC.

motors) the low-pass filter is intrinsic in the transducer, and PWM DACs are often used in these applications. 5.2.3.9 Multiplying D/A Converters

A multiplying DAC is obtained when the reference voltage Vref can vary. It is possible to have a multiplying DAC with 1/2/4 quadrant capability, depending

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Figure 5.41

227

Gain control with a DAC; VO is used as reference (Vref ) for the DAC in the feedback loop: IO = (Vref D)/Req = (VO D)/Req , IO = −Vi /R, VO = −(Vi /D)(Req /R).

on acceptable polarity of Vref and Vo Applications for multiplying DACs include: • Variable gain amplifier (VGA): the DAC network controls the gain; • Bipolar DAC (with Vref inversion); • Ratiometric ADC (Section 5.3.2.5). An example of variable gain amplifier control with a DAC is presented in Figure 5.41. The DAC is used as feedback or input variable transconductance element. With bipolar signals, this circuit requires DAC structures with switches able to handle a bipolar reference VR . 5.2.3.10 Bipolar Digital-To-Analog Converters

A bipolar output DAC can be obtained with three basic techniques: • Translation of a unipolar characteristic (constant added using an output buffer); • Sign inversion of the output voltage VO (gain polarity switch controlled by the sign bit); • Bipolar reference voltage Vref controlled by the sign bit (requires switches able to handle bipolar currents).

5.3 Analog-to-Digital Conversion: Basic Techniques Following the same method used in the previous section for DACs, ADCs are described first in terms of external parameters and errors, then organized in a taxonomy and finally exemplary circuits are analyzed in detail. With this approach it is possible to describe and compare the various architectures in terms of cost (complexity) and performance (speed) parameters. An ideal analog-to-digital converter should provide a high number of correct bits in a very short time; obviously such a device is difficult to implement, but the various techniques available for analog-to-digital conversion provide the ability to make trade-off between the performance objectives. Integrated circuit ADCs are available in a wide variety of types, with different parameters, optimizations,

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Figure 5.42

Ideal ADC transfer function: (a) Large step view (N = 3 bits), and (b) transfer function for large N. S: analog full-scale, M : maximum digital output.

and trade-off for speed, precision, and cost. A good understanding of the basic principles and techniques of analog-to-digital conversion allows the designer to select the most suitable device for each application. 5.3.1 Static and Dynamic Parameters The ADC converts a physical quantity A (voltage V or current I ) into a number D, usually expressed in binary form. An unique output number is associated with each input value; a variable input signal is converted into a sequence of numbers. The ADC operation requires a finite conversion time; during this time the input must remain constant, or change less than 1 LSB. This condition is guaranteed by the sample&hold function. The variable in input to an ADC is a continuous quantity that can assume any value in the range [0, S] for unipolar ADCs, or [−S/2, +S/2] for bipolar ones. This input range is divided into quantization intervals AD , and a Di value corresponds to each interval AD,i . The transfer function D(A) is a staircase, as shown in Figure 5.42(a). The step width on x-axis (input A) corresponds to a quantization interval AD . The step spacing on y-axis (output D) is 1 LSB; with N -bit digital values D, the total number of steps in the stair is M = 2N . If the the quantization intervals AD have constant width, the ADC is linear. For large values of N , the many small steps make the ADC transfer function look like a straight line (Figure 5.42(b)), but an expanded scale reveals the step-wise shape. The ADC has a different transfer function than a DAC, but the error analysis can follow the same approach and define the errors using the same taxonomy as DACs: • Linear errors: offset and gain; • Nonlinearity errors: differential and integral errors; • Dynamic parameters.

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Figure 5.43

229

Error taxonomy for ADC characteristic. (a) Overall comparison: (1) ideal DAC; (2) actual ADC; (3) linear approximation with gain (g ) and offset (o ) errors. (b) Definition of the integral nonlinearity error (4) inl as maximum deviation of the actual transfer function from the best approximating straight line.

Figure 5.43 uses the same transfer function taxonomy used in Figure 5.20 for DACs. The analysis sequence for ADCs static errors is the following: 1. Linear approximation DI (A) of the actual transfer function DR (A); 2. Comparison of linear approximation versus ideal transfer function, to identify linear errors: offset O and gain G ; 3. Comparison of actual transfer function versus linear approximation, to identify the integral nonlinearity inl ; 4. Detailed quantization interval analysis, and definition of the differential nonlinearity error dnl . As for DACs, the linear errors can be eliminated by rotation and translation of the transfer function, (i.e., with gain and offset corrections in the signal chain). Nonlinearity errors are code-dependent; therefore compensation is possible (e.g., with a lookup table), but difficult and expensive. 5.3.1.1 Differential Nonlinearity Error

All quantization intervals should have the same amplitude AD , but actual intervals  may have a different width: Adnl,i  = AD . As a result, the transfer function is modified as in Figure 5.44. The change in step amplitude from ideal is the differential nonlinearity error dnl,i :  dnl,i = Adnl,i − AD .

(5.30)

Quantization intervals wider than AD reduce the adjacent ones; when dnl,i > 1 LSB the interval completely suppresses an adjacent interval, causing a missing code error; this corresponds to a differential nonlinearity dnl,i < 1 LSB in DACs. This error occurs in feedback ADC structures when the feedback DAC has a high differential nonlinearity. For an increasing input, the digital output jumps from Di to Di+2 ; for a decreasing input the digital output moves from Di+2 to Di . As a result, the code Di+1 is never generated (missing). The missing

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Figure 5.44

ADC transfer function and errors. (a) Ideal (gray, 1) and actual (black, 2) transfer function, with definition of the differential nonlinearity error dnl,i = Adnl,i − AD , and (b) missing code error: code (3) is never generated (dnl,i > 1 LSB).

code corresponds to a widening of the quantization interval from AD to 2AD , as shown in Figure 5.44(b). Integral nonlinearity is related to the differential error dnl (local change for each step, defined above) and describes the deviation of the complete transfer function from a straight line. The integral nonlinearity at a specific point is the sum of differential nonlinearities from 0 to the point itself: inl,i =

i


dnl,n .

(5.31)

n=0

Sequences of differential nonlinearities dnl with the same sign accumulate and cause a high integral nonlinearity inl , while alternate sign dnl bring a smaller contribution to overall inl . This corresponds to the DAC behavior described in Section 5.2.1. 5.3.1.2 Dynamic Parameters

The conversion from A to D occurs with some delay: the conversion time Tc . The dynamic performance of an ADC can be specified by Tc or by the maximum conversion rate fc = 1/Tc . In most cases the actual conversion rate is controlled by the system interface: the ADC receives a conversion start (CS) command and, after a delay Tc , it raises a end of conversion (EOC) flag. Tracking ADCs follow a (slowly) changing signal. The maximum slew rate SRmax of the signals which can be correctly tracked depends on the conversion time: for correct operation the signal must change less than 1 LSB during the conversion. The above defined errors can be then summarized as follows: • Static errors: • Linear errors: gain g and offset o ; • Nonlinearity errors: integral nonlinearity inl and differential nonlinearity dnl .

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Table 5.3 ADC Taxonomy Organization Type Parallel (flash) Pipeline Residue Successive approximations Tracking and differential

Complexity nc

Conversion time Tc

high (≈ 2N )    

low (1)    

low(1)

high (≈ 2N )

• Dynamic parameters: • Conversion time Tc ; • Maximum tracking slope. These errors can be specified as percentage of full-scale (e.g., 1%), absolute value (e.g., 10 mV), or fraction of an LSB for a specified number of bit N (e.g., 1/ LSB for N = 4). 2 5.3.2 ADC Taxonomy and Basic Structures An ideal ADC should require few external components and provide a high number of bits N in a short time. Real ADCs can only make trade-offs between these characteristics, and can be classified as shown in Table 5.3 according to two parameters: • The complexity (i.e., the number of comparators nc the lower, the better); • The conversion time Tc (or the conversion rate fc = 1/Tc ), which indicates the number of conversions per second (the higher fc , the better, since a high conversion rate allows tracking high-frequency signals). In Table 5.3 these parameters are normalized to the number of comparators (nc = 1 meaning a single comparator), and to the delay (Tc = 1 corresponding to the delay of a single comparator), respectively. High-speed converters are generally complex, while high resolution ADCs are generally slow. The various ADC structures provide different trade-offs, which must be evaluated for each specific application. 5.3.2.1 Parallel (Flash) ADC

The flash (or parallel ) ADC (Figure 5.45) compares the input signal A directly with a series of thresholds AS , corresponding to the boundaries of the quantization intervals AD . For a N -bit conversion, this structure requires M = 2N − 1 comparators. The comparator outputs correspond to a linear or thermometer representation, and can be converted to a standard N -bit weighted code by a priority encoder.

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Figure 5.45

Flash ADC with output encoder. (2) The output code corresponds to (1) input value A between A1 and A2 . (3) The encoder converts the (4) M-bit thermometer output from the comparator bank into a binary coded N-bit output D.

Figure 5.46

Feedback ADC structure. A is the approximation signal generated by the DAC. (1) Comparator output, (2) counter (up/down or with enable), (3) DAC to build the approximating signal A , (4) digital output.

For a steady input A the digital output is available after the conversion time Tc , corresponding to the sum of the comparator delay Tcomp and the encoding logic delay Tenc : (5.32) Tc = Tcomp + Tenc . The flash converter parameters are therefore characterized by the following indicators: • Complexity: 2N − 1 comparators; • Delay (from A input stable to the D result): 1 comparator delay (plus combinatorial logic). These converters are fast, because all comparison operations are carried out at the same time (the normalized conversion time is equal to 1), but expensive and use high power, because they require many comparators. 5.3.2.2 DAC – Feedback Converters

The ADC can be built with a comparator and a DAC connected in a feedback loop, as shown in Figure 5.46. This structure is a negative feedback system, where the control logic modifies D until A becomes a suitable approximation of A

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(within the N -bit resolution). This process can use two approaches: 1. One LSB steps, used in staircase converters. This technique requires 2N steps for full-scale change of A, therefore the maximum conversion time is Tc = 2N Tck . 2. Variable amplitude steps, used in successive approximation converters. A conversion is carried out with N steps, starting from the MSB. This technique requires N steps, therefore the conversion time is Tc = NTck . 5.3.2.3 1-LSB Steps: Staircase and Tracking Converters

For a staircase ADC, the control logic is a counter with enable command (EN) provided by the comparator:  if A' < A EN = 1 (counter enabled) (5.33) if A' > A EN = 0 (counter disabled) The operation of this ADC is shown in Figure 5.47: As long as A < A, the counter is enabled (EN = 1); the A signal goes up 1 LSB for each clock tick. As A > A either the comparator disables the counter (and A is held at its current value), or the counter is reversed so that A decreases by 1 LSB and A < A; if A is constant, on the next clock ticks the counter will oscillate up and down. The latter technique is used to create a tracking ADC. The DAC output changes from 0 to S with 2N steps, therefore the maximum conversion time Tc,max is Tc,max = 2N Tck .

(5.34)

With the up/down counter, variable signals with dv/dt ≤ AD /Tck can be tracked, as shown in Figure 5.48. Signals with slew-rate higher than SRmax = AD /Tck cannot be tracked, and they cause an overload error.

Figure 5.47

Feedback converters with counter and 1 LSB steps. The comparator controls an up/down counter (tracking ADC).

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Figure 5.48

Tracking of variable signals. (1): analog input A, (2) reconstructed tracking signal Ar . Overload occurs when dv/dt > AD /Tck .

In summary, the parameters of an N -bit tracking converter are • Complexity: 1 comparator; • Delay (from A input stable to the D result): 2N comparators delay. This ADC is slower than the flash ADC due to the fully sequential decisions, and has limited dv/dt tracking capability, however it is simpler than flash ADCs because it uses a single comparator. 5.3.2.4 Variable Steps: Successive Approximation Converters

The approximation of A with A can follow another approach: instead of modifying A of 1 LSB on each clock tick, steps can be of variable amplitude, controlled through a successive approximation register (SAR): this creates a successive approximation ADC. An example of the step sequence is shown in Figure 5.49. The input signal A is compared to S2 : the first attempt is to set MSB=1, which makes A' = 12 S < A, therefore confirming MSB = 1. The 0 − 12 S range is removed from possible A values. A is then compared to the mid-value of the remaining range: the guess MSB-1 = 1 makes A' = 34 S. Since A < 34 S, MSB-1 = 0, The 34 S − S range can be removed from possible A values. A is compared to the mid-value of possible range: MSB-2 = 1 makes A' = 58 S. Since A < 85 S, MSB-2 = 1; the 12 S − 58 S range can be removed from possible A values.The sequence continues: since A < 11S/16, 3 MSB-3 must be 0; 11 16 S − 4 S range can be removed from possible A values. The complete decision tree for 5 bits (i.e., the sequence of A values compared step by step with A), is presented in Figure 5.50. Compared to flash ADCs, this structure is simpler, because it uses only one comparator versus 2N , but slower, since it uses N steps instead a single one. Compared with tracking

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Figure 5.49

Successive approximation 4-bit ADC. (a) Block diagram, and (b) sequence of approximation steps.

Figure 5.50

Complete decision tree for a 5-bit SAR ADC.

ADC this structure has the same complexity (1 comparator), but is faster, because it uses N steps instead of 2N . With the ADC circuits presented in this section it is possible to fill other rows of the complexity/speed table. The parameters for an N -bit successive approximation converter are • Complexity: 1 comparator; • Delay (from A input stable to the D result): N comparators delay. 5.3.2.5 Ratiometric Configuration

When the ADC is used to measure the output from a voltage divider or a bridge, the voltage source which drives the divider or the bridge can be used as the ADC reference voltage Vref , as shown in Figure 5.51. This makes the digital output independent of the actual value of the reference. This ratiometric ADC configuration requires ADCs with single external Vref , such as the flash, the SAR, and the tracking converters.

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Figure 5.51

Ratiometric analog-digital conversion. The output D depends only on the R /R ratio.

5.3.3 Mixed ADC Architectures New ADC structures having better cost/performance figures can be obtained from the basic ones previously described. The starting point is a detailed analysis of the operation sequence in the SAR ADC described in Figure 5.51. In the following, the simplified notation b = Z > Y is used to indicate that the bit b is set to 1 (true) if Z > Y , and to 0 (false) otherwise. Starting with the MSB (bit 0, b0 ), the value of the bit is the result of the comparison between A and S2 : b0 = A > S2 . The value of the next bit (MSB-1, b1 ) depends on the value of b0 : • If b0 = 0, A is compared to S4 : b1 = A > S4 ; • If b0 = 1, A is compared to

S 2

+ S4 : b1 = A >

S 2

+ S4 .

The two tests can be synthesized as  S S b1 = A > b0 + 2 4

(5.35)

and, introducing the residue of the MSB, R0 = A − b0 S2 , the test for b1 can be finally written as   S S b1 = R0 > = 2R0 > . (5.36) 4 2 In a similar way, the value of the third bit (MSB-2, b2 ) can be written as b2 = A > S/4 + b0 S/2 + b1 S/4

(5.37)

or, introducing the MSB-1 residual R1 = A − b0 S/2 − b1 S/4, as b2 = 2R1 > S/2.

(5.38)

The order i residue is the difference between A and the i-bit approximation of A; on each step the residue Ri is doubled to cover the [0, S] range, and compared again with S/2 to find the next bit. It is possible to express Ri as Ri = A −

i
k=0

bk

S 2k+1

,

for i ≥ 0

(5.39)

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Figure 5.52

237

Successive approximation with gain stages. (a) Step 1, MSB decision, and (b) steps 1-3, with decisions on MSB-1 and MSB-2.

and recursively as



R0 = A − b0 S/2 S Ri = Ri−1 − bi 2i+1

for i > 0.

(5.40)

The SAR algorithm finds the value of bit i + 1 by comparing twice the Ri with S/2. A graphic description of these operations is given in Figure 5.52. This architecture uses a sequence of identical units (comparator, 1-bit DAC, adder, amplifier), where stage i operates on the residue between A and the (i − 1) bit approximation of A. This sequence can also be seen as a deconstruction of a successive approximation structure, as shown in Figure 5.53, where three MSBs are shown: 1. Initially, the input value A is compared to S2 ; since A > S2 , the MSB is b0 = 1. The MSB residue is R0 = A − b0 S2 . 2. The residue R0 is amplified by a factor of two and compared to S2 ; since 2R0 < S2 , then the value associated to MSB-1 is b1 = 0. The MSB-1 residue is R1 = R0 − b1 S2 = R0 ; 3. The residue R1 is amplified by a factor of two and compared to S2 ; since 2R1 > S2 , then the value associated to MSB-2 is b2 = 1. The MSB-2 residue is R2 = R1 − b2 S4 ; 4. The residue R2 is amplified by a factor of two and compared to S2 and so on.

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Figure 5.53

Structure of a Residue ADC (3 MSBs).

Figure 5.54

Example of algorithmic ADC [3].

The same basic operation can also be obtained with a loop circuit, where each bit decision corresponds to a rotation around the loop. An example of this algorithmic ADC is shown in Figure 5.54 [3]. 5.3.3.1 Hopfield Network ADC

In the residue ADC shown in Figure 5.53 each comparator-adder-DAC group can be replaced by a multiple-input adder and a zero-crossing detector, as shown in Figure 5.55(a) (MSB) and in Figure 5.55(b) (MSB-2). The complete structure for a 4-bit ADC is shown in Figure 5.55(c): the horizontal lines represent adders, with variable weight inputs from the vertical lines. Each row corresponds to 1 bit, obtained from the weighted sum of input A, reference S, and LSBs, with weight corresponding to the position. The structure is a Hopfield neural network [8]. The weights in Figure 5.55 correspond to a linear ADC; but it is also possible to use different weight sequences to get a nonlinear conversion characteristic. 5.3.3.2 Errors in Mixed ADCs

In subranging converters, any error in residue evaluation is propagated to the following stages, therefore each residue must be evaluated with a precision related

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Figure 5.55

239

Hopfield ADC structure (4-bit). (a) From comparator to adder and zero crossing detector (MSB, D1 ), (b) circuit to get D3 from the residue of D1 and D2 , and (c) complete 4-bit Hopfield ADC.

to the remaining number of bits. This impacts all elements of the chain, namely the amplifiers, the elementary ADCs, and the DACs. A key issue is that the required precision depends on the bit position in the chain and is higher for elements related to MSBs. For an N -bit converter the first stage (MSB) needs full precision in ADC and DAC to allow residue evaluation with N − 1 bit precision. N -bit residue/subranging converters are characterized by the following parameters: • Complexity: N comparators; • Delay (from A input stable to the D result): N comparators delay. This figure (N , N ) looks worse than Flash (2N , 1) and SAR (1, N ) ADCs. The residue structures should be considered only a first step to build pipeline ADCs, a family of architectures described in the following, which can provide better cost/performance figures. 5.3.3.3 Pipeline ADC

The next step is to use a similar organization, with ADC stages separated by Sample&Hold analog memory elements. The structure can be seen as an analog pipeline; the S/H allows the various ADCs to operate on different samples at the same time, as shown in Figure 5.56. An example of operation for a sequence of three samples is presented in Table 5.4.

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Figure 5.56

Pipeline ADC with 1-bit stages (same as in Figure 5.54, plus inter-stage S/Hs). (sample labels refers to a snapshot at t3 ) At t1 : Stage 1 processes sample A; get MSB(A); At t2 : Stage 1 processes sample B, and stage 2 processes sample A; get MSB-1(A) and MSB(B) At t3 : Stage 1 processes sample C, stage 2 processes sample B, stage 3 processes sample A; this generates MSB-2(A), MSB-1(B), and MSB(C).... Table 5.4 Operation Sequence in a Pipeline ADC for the Input Samples Sequence A0 , A1 , A2 , . . . Processing Stage

t1

t2

t3

t4

Result A0

1 2 3 4

A0 − − −

A1 A0 − −

A2 A1 A0 −

A3 A2 A1 A0

MSB (b0 ) MSB-1 (b1 ) MSB-2 (b2 ) MSB-3 (b3 )

The pipeline architecture can be used for any multistage ADC, including multi-bit stages. The fundamental benefit is a faster equivalent conversion rate fs , allowed by the reduction of the equivalent conversion time Tct . An N -bit pipeline ADC can accept a new sample at every sampling clock pulse, uses N comparators, and requires N cycles to complete the conversion of each sample. The parameters for an N -bit converter are therefore • Complexity: N comparators; • Actual delay (from stable Ai input to Di result): N comparators delay. • Equivalent delay (inverse of sample per second): 1 comparator delay.

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Table 5.5 Complete ADC Taxonomy Type Flash Pipeline Residue SAR Tracking

Figure 5.57

Complexity nc

Conversion Time T c

Latency Time TL

2N − 1 N N 1 1

1 1 N N ≈ 2N

1 N N N ≈ 2N

Speed versus complexity figures for various 12-bit ADC architectures (logarithmic scales).

With the pipeline architecture it is possible to process multiple samples at the same time, at the expense of an increased complexity and latency. Additional analog memory elements, represented by the the S/H units, are required. It is possible to get the same equivalent speed of a flash converter but using only N comparators instead of 2N . The complete speed/complexity figures of ADCs are summarized in Table 5.5, while the positioning of the ADC architectures in the speed/complexity plane is shown in Figure 5.57. 5.3.3.4 Multibit Residue / Subranging Architectures

Residue and pipeline architectures can use multibit stages. Comparators (actually 1-bit ADCs) are replaced by M -bit ADCs, and the approximation is built using M -bit DACs. The residue has a max value AD = S/2M , and the interstage gain required to bring residue to full-scale S is 2M . Multibit-residue provides further degree of freedom for the speed/complexity trade-off, namely • Higher speed (with the same number of comparators); • Lower complexity (less comparators for the same speed). A key problem with multistage ADCs is that the first stage, which provides MSBs, must have a precision corresponding to the total number of bits in order

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Figure 5.58

Comparison of 2×4 and 4×2 residue ADC. (a) 8-bit residue ADC: 2×4-bit cells, total conversion time: Tc,T = 2Tc,A/D + TA,D/A , and (b) 8-bit residue ADC: 4×2-bit cells, total conversion time: Tc,T = 4Tc,A/D + 3TA,D/A .

to generate correct residues. To release this constraint, these structures can use additional comparators to detect out of range levels of the first ADC. The second stage (which provides LSBs) can issue additional information to correct the MSBs stage output. In other words, the additional comparators add redundancy, which can be used to correct the errors. This technique was first described in [10], and is discussed in detail in [6]. The key benefit is that error correction occurs fully in the digital domain. These architectures allow better tuning of design to specifications. An example for 8-bit ADC (4×2 and 2×4 architectures) is presented in Figure 5.58. The parameters of these “mixed” structures are summarized in Table 5.6, which compares flash, SAR, and two residue architectures. An example of the parameters for 12-bit residue architectures with Flash and SAR ADCs used in the basic stage is shown in Table 5.7. A summary of speed/complexity trade-off for all structures presented in this section is presented in Table 5.8. 5.3.3.5 Speed Versus Complexity with Multibit Residue

The multibit residue structures can use flash or SAR basic units, with different complexity and speed trade-off parameters: • Flash ADC: equivalent Tc,T = Tc + Tda ≈ Tc ; • SAR ADC with K bits per stage: equivalent Tc,T = KTc + (K − 1)Tda ≈ KTc .

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Table 5.6 Choices for an 8-Bit ADC Type

Complexity nc Total Conver. Time Tc,T Latency Time TL 8Tc + 7Tda 4Tc + 3Tda 2Tc + Tda Tc

SAR (Figure 5.49) 1 Res. 4×2-bit flash (Figure 5.58b) 4(22 − 1) = 12 Res. 2×4-bit flash (Figure 5.58a) 2(24 − 1) = 30 Standard flash (Figure 5.45) 28 − 1 = 255

8 4 2 1

Table 5.7 ADC Structures with Multibit Residue Pipeline

Type Parallel (flash) Pipeline Residue Residue K -bit Flash Residue K-bit SAR Successive approximations Tracking

Complexity nc

Total Conversion Time Tc,T

Latency Time TL

2N − 1 N N 2K N/K N/K 1 1

1 1 N N/K N N 2N

1 N N N/K N N 2N

Table 5.8 Example of Multibit Residue ADCs with N = 12 and K = 3

Type

Single-Stage Complexity nc

Total Complexity

Single-Stage Conversion Time Tc

Total Conversion Time Tc,T

Flash SAR

2K − 1 = 4095 1

2K N/K = 32 N/K = 4

1 K=3

N/K = 4 N = 12

Speed and complexity for various structures of a 12-bit residue ADCs are compared in Figure 5.59. A detailed analysis for these architectures is presented in [4]. As an example, the possible design choices to get an 8-bit ADC with total conversion time Tc,T < 60 ns based on comparators with Tc = 10 ns are now presented. The conversion time for a SAR ADC with these comparators is Tc = 8 × 10 ns = 80 ns; this conversion time is too long and therefore this solution cannot be used. On the other hand, conversion time of a flash DAC is just Tc = 10 ns, which is much faster than the requirement, and the solution is complex since it requires 255 comparators. Intermediate performances can be achieved using multibit residue sub-ranging. With two cascaded 4-bit flash, 2(24 −1) = 30

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Figure 5.59

Complexity and speed for various 12-bit residue ADC.

comparators are needed, and Tc,T = 2Tc +Tda , TL = 2, while with four cascaded 2-bit flash requiring 4(22 − 1) = 12 comparators, Tc,T = 4Tc + 3Tda , TL = 4.

5.4 Analog-to-Digital Converters for Specific Applications With the ADC structures described in the previous sections an increase of the number of bits (that is a higher accuracy of the analog input signal representation) requires more precise elements (e.g., resistors of the ladder network). This section introduces other conversion techniques, which exploit specific characteristics of the signal, such as a limited bandwidth, or with limited slew rate. This is the case of differential converters: delta () and sigma-delta (), which allow to obtain a high number of bits without high precision devices, at the expense of a lower conversion rate and additional digital signal processing. These techniques were originally developed for signals with limited bandwidth or limited slew rate, such as voice. The analog-to-digital conversion process can also exploit other characteristics of the signal, such as the amplitude distribution. When the signal remains mainly at low amplitude levels, it is possible to optimize the overall SNRq using smaller quantization steps around those intervals. An example is the logarithmic encoding, widely used for voice. Finally, ADCs can be optimized for specific signals, with the definition of a signal source model, which allows the extraction of signal parameters on the ADC side, and to reconstruct the signal in the DAC. This model encoding technique is widely used for voice conversion. 5.4.1 Oversampling and Differential Converters The starting point for a discussion of differential conversion techniques is the tracking ADC. The output information, instead of the N -bit counter status (value Dpar in Figure 5.60), consists of the sequence Dser of up/down commands from the comparator to the counter. Dpar is a parallel representation of the counter

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Figure 5.60

Counter-based tracking ADC with serial output Dser .

Figure 5.61

Differential ADC structure (delta modulation). The switch SW closes for a short time, creating the bipolar pulses L. (a) Block diagram, (b) sequence of L pulses, and (c) waveforms. L is a sequence of positive or negative pulses, with rate fck = 1/Tck ; on each pulse the reconstructed signal Ar changes one step γ (positive or negative).

status, and the sequence of up/down command Dser is a serial version of the same information. A complete ADC-DAC chain with serial data transfer is shown in Figure 5.60. In this ADC + DAC arrangement, the parallel digital representation Dpar , based on weighted bits, is replaced by the sequence of comparator output states Dser , a serial flow of bits with the same weight (1 LSB). Figure 5.61 represents the same structure, where the comparator output is converted into bipolar pulses (B) by the closure of the switch SW, and the counterDAC group is replaced by an integrator (I ): the structure is now a  (delta or differential ) ADC (the technique is sometimes referred to as delta modulation). On each pulse the locally reconstructed signal Ar changes of one (positive or negative) step γ corresponding to 1 LSB following the changes on the input signal Ai . To reconstruct the DC level, the system must include a procedure to align the starting points by setting to the same value both integrators (e.g., 0 V).

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Figure 5.62

Input signal limits for differential ADC. (1) Idle; (2) correct operation; (3) overload: slope larger than γ /Tck .

These differential converters do not require high precision elements, and they are now used in high resolution ADCs, when a lower conversion rate is acceptable. Other techniques that allow us to reduce the bit rate but operate after the ADC are not discussed here. The differential ADC structure has bounds on the dynamic range for lowlevel and fast-changing signals, as shown in Figure 5.62. Signal changes smaller than the minimum step γ cannot be sensed; in this condition the output is a sequence of alternated zeros and ones (idle noise). Signals changing faster than γ /Tck cannot be tracked and cause a slew rate overload. For a signal with frequency fa and peak value Va , the amplitude range that can be correctly tracked is: γ γ fck < Va < . 2 2 πfa

(5.41)

This differential converter does not require formatting of serial output data, because all bits have the same weight. The drawbacks are the high digital throughput time (a full-scale change requires 2N bits, versus N for coded representation), and a limited range for input signals amplitudes and frequencies: • Low amplitude limit: signals with an amplitude smaller than the idle noise are not detected (this corresponds to the 1 LSB resolution of classic ADCs); • High amplitude limit: fast signals, with slew rate SR > γ fck , cannot be tracked. To increase the resolution one can use a smaller step γ , but this reduces the achievable slew rate (γ fck ). The clock rate fck can be increased to improve the ability to track fast signals, but the digital information flow is also increased.

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Figure 5.63

247

Effect of oversampling on power distribution of quantization noise. (1) Signal spectrum; (2) steep anti-alias filter; (3) quantization noise; (4) aliases. In (a) Nyquist sampling requires a steep filter (2) to remove aliases (2), while with oversampling (b) aliases (4b) are far from baseband and quantization noise (3b) is spread across a wider bandwidth: the same SNRq of (a) can be achieved with a smoother filter (2b). In (c), with combined oversampling and steep reconstruction filter, most quantization noise is removed (3c) and the lower in-band quantization noise (5) improves the SNRq .

The signal-to-quantization noise power ratio SNRq depends on γ , but as γ is reduced to improve SNRq , a higher fck is needed to track signals with an assigned slew rate, resulting in a higher bit rate. In most cases, these ADCs operate in an oversampling mode: the sampling rate is much higher than the Nyquist limit. For instance, a 3 kHz audio signal with Nyquist sampling rate 6 kSPS is usually sampled at 8 kSPS with standard ADCs, and at 1 MSPS with differential oversampling ADCs. As with any design choice in the real world, oversampling brings benefits but also drawbacks. Moving the aliased spectra far from baseband reduces the aliasing noise, and relaxes the specifications on the anti-alias input filter. The total power of quantization noise depends on the quantization step amplitude, but with higher sampling rate fs the quantization noise is spread over a wider band (0, fs /2). Therefore, oversampling reduces the spectral density of quantization noise in the useful signal bandwidth. These effects are shown in Figure 5.63. The combination of a steep filter and oversampling reduces the quantization noise power, as shown in Figure 5.63(c). The higher bit rate from oversampling can be reduced with digital filters; the combined use of oversampling and digital filtering can optimize the system performance versus channel bandwidth, moving complexity from the analog to the digital domain, as shown in Figure 5.64.

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Figure 5.64

Analog and digital anti-aliasing filtering. (a) Low sampling rate (Nyquist) requires a complex analog anti-alias filter before the sampling, while (b) oversampling allows for simpler anti-alias filter, but requires a digital filter to reduce the bit rate.

Figure 5.65

Example of adaptive differential ADC/DAC. L alternating sequences (0101...) indicate small changes of the signal (idle condition); the step S can be reduced; L continuous sequences (0000... or 1111...) indicate an overload; the step S must be increased.

5.4.1.1 Differential Converter Dynamic Range

In a differential ADC, the step γ corresponds to the quantization step AD in a standard ADC. According to (5.41), the input dynamic range is the ratio of γ /2 to γ fck /2πfa , which corresponds to an amplitude ratio fck /πfa that does not depend on γ and can be increased with two techniques: • Constant γ : increase fck , leading to a higher bit rate; • Variable γ : change the step amplitude to allow small steps with idle noise or low-level signals, and large steps for high slew rate signals (adaptive converters). The variable quantization step is controlled by the signal level or from the sequence of error signals. The minimum γ should be used in the idle condition (output sequence 010101...); the maximum when the ADC operates near overload (i.e., for output sequences corresponding to 00000... or 11111...). A digital circuit can detect these conditions and properly modify the step γ (power estimation unit, Figure 5.65). Since power estimation uses the digital output, the inverse process can be applied at the receiver to cover the complete signal dynamic range. All the differential structures described here can evaluate the difference as a single bit or as multibit words. This corresponds to replacing the comparator in the basic structure with an ADC, with the analog integrator driven by a DAC. The analog integrator can also be replaced by a numeric accumulation loop. This

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Figure 5.66

249

Example of multibit adaptive differential ADC/DAC. (a) Feedback loop with analog integrator (after the DAC), and (b) feedback loop with digital integrator (accumulator, before the DAC).

brings several variations to the basic structure; two examples are presented in Figure 5.66. 5.4.1.2 Sigma-Delta Converters

In the differential converter the input dynamic range is limited by the signal slew rate; to get a wider range the slew rate can be limited with an integrator that decreases the signal amplitude as the frequency goes up. This leads to the sigma-delta () structure, shown in Figure 5.67. After the integrator, the maximum slew rate of a sine wave is independent of frequency. The inverse operation (derivative) must be included at the output to correctly reconstruct the signal, as shown in Figure 5.67(a). The decoder now is an integrator followed by a differentiator, which cancel each other. On the input side, the comparator input is the sum of two integrals, which becomes the integral of the sum. The rearranged system is shown in Figure 5.67(b). These diagrams do not include the (mandatory) input anti-alias and output reconstruction low-pass filters. The comparator introduces a quantization Nq (s); a model used to analyze this noise in the  is shown in Figure 5.68 and the transfer function from the noise input Nq (s) to the output Y (s) is Y (s) 1 s = = . Nq (s) 1 + 1/s s+1

(5.42)

The  ADC provides a high-pass noise-to-output transfer function Y (s)/Nq (s), therefore the noise power spectral density is higher at high frequencies. This behavior is called noise shaping : the noise power spectral density in the baseband is reduced, and this allows simpler reconstruction filter. The overall effect is shown in Figure 5.69. The complete  conversion chain is presented in Figure 5.70. 5.4.2 Logarithmic Analog-to-Digital Converters The logarithmic conversion, discussed in this section, exploits specific characteristic of the signal to get a high SNRq without increasing the word size. The technique

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Figure 5.67

Sigma-Delta () ADC and DAC structures (input and output anti-alias filters not shown). (a) Addition of integrator and differentiator unit, and (b) merging the two integrators of the ADC into a single one, and merging the integration and differentiator into a direct connection in the DAC.

Figure 5.68

Model for quantization noise analysis.

Figure 5.69

Noise shaping in  differential converters. (a) Signal (1), quantization noise (2), and first alias (3) spectra. (b) Shaped quantization noise (4) in  ADCs, (c) residual quantization noise (5) after DAC reconstruction filter (6).

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Figure 5.70

251

Complete  conversion chain (coder and decoder). (1) Anti-aliasing input filter (to define input signal bandwidth; oversampling allows simpler filters); (2) differential  ADC order 1, 2, . . ., N: produces a high speed, unweighted bit stream; (3) serial, high rate; (4) digital decimator, which changes the high speed bit stream into a lower rate word sequence; (5) transmission channel (or storing unit) operating at the low data rate; (6) interpolator, to reconstruct the high bit rate serial flow; (7) differential  DAC, which reconstructs the analog signal; (8) output reconstruction filter, to remove aliases.

was developed for voice signals, but can be used also for other sources with a known amplitude distribution. The logarithmic conversion can be performed before or inside the ADC, or with digital processing after a standard linear ADC (with high number of bits). Embedding the technique within the ADC allows lower power consumption and reduced system complexity. The procedure here presented in detail applies for audio signal (voice), but similar techniques can be used for other sources. 5.4.2.1 Benefits of Logarithmic A/D and D/A Conversion

The linear ADCs presented in the previous sections use the same quantization interval AD for any signal amplitude. Now the quantization error power does not depend on signal level; the SNRq is optimum for high-power signals, close to full-scale, and worse for lower amplitude signals. The linear A/D conversion gives poor results for voice coding because this signal is at low levels for most of the time, but all AD intervals have same amplitude, and the quantization error does not depend on signal amplitude, making the SNRq worse for low-level signals. For signals with a defined amplitude distribution, a conversion with variable quantization intervals (smaller where the signal lies for most of the time) can give better results in term of average signal to quantization noise ratio SNRq . The variable quantization requires nonlinear A/D conversion (i.e., different AD quantization intervals), chosen to optimize SNRq for the specific signal amplitude distribution, thus achieving optimum quantization. As discussed in Section 5.1.3, voice signals have an approximate exponential amplitude distribution: the signal is at low levels for most of the time, but can use a wide dynamic range. When the signal is close to 0, small quantization steps minimize the quantization noise power, while large steps allow tracking of fast changes. A logarithmic A/D conversion fulfills these requirements, and can achieve constant SNRq over a wide signal dynamic range, allowing good SNRq using fewer bits. Such a D(A) characteristic is shown in Figure 5.71.

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Figure 5.71

Shape of the A to D transfer function for linear (1, black) and logarithmic (2, gray) ADC.

Figure 5.72

SNRq comparison for linear (1) and logarithmic (2) ADCs.

With variable AD intervals, the quantization noise power is related to signal level, and SNRq can be made almost constant. Since the amplitude distribution of voice can be approximated by an exponential function, the best nonlinear quantization law for voice is logarithmic. The conversion of logarithm signal log A with a quantization error q gives the numeric value D = log A + q .

(5.43)

Letting q = log B K (i.e., K = B q ), the sum can be expressed as the logarithm of the product; with base B logarithms (5.43) can be expressed as D = log B A + q = log B KA.

(5.44)

Equation (5.44) shows how the additive error term q becomes a constant multiplying error K = B q , independent of the signal level A. This is the key benefit of logarithmic quantization, since the SNRq does not depend on the signal amplitude. The SNRq for linear and logarithmic quantization versus signal amplitude are compared in Figure 5.72. Audio signals are bipolar (range [−S/2, +S/2]), so the D(A) logarithmic curve must be mirrored in the III quadrant. For very small values of A the logarithmic curve can be only approximated, and two approaches are used: • A-law, which approximates the logarithm close to 0 with a straight line; • µ-law, which shifts the I and III quadrant segments to align in the origin.

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Figure 5.73

253

SNRq comparison between linear, A-law, and µ-low A/D conversion.

These approximations have negligible effects for high values of A, but modify SNRq at low levels as shown in Figure 5.73. 5.4.2.2 Logarithmic Conversion Circuits

A logarithmic analog-to-digital conversion can use three basic approaches: • Logarithmic amplifier, followed by linear ADC; • High resolution linear ADC, followed by digital log encoding (the most used technique); • Intrinsic logarithmic ADC. The nonlinear ADC and DAC techniques have other applications also: the DDS described in Section 4.4.5 can use a nonlinear DAC to generate a sine waveform with reduced harmonics. In this case, the D to A transfer function must follow a sine shape (instead of the logarithmic shape). 5.4.3 Model Encoding Besides a sequence of samples, a signal can be represented by a set of parameters, such as the shape, the frequency, the amplitude, and the phase. In this model encoding the signal is represented by specifying its wave shape and parameters. For the sine wave in Figure 5.74 these parameters are the shape (a sine), the frequency, the phase and the amplitude. With this information the signal can be reconstructed (e.g., using a properly set up signal generator), with the same characteristic as the original one. The model encoding conversion technique requires a preliminary definition of a signal source model, and the evaluation of the model parameters. For these reasons, this technique is convenient only for specific signal types, for example voice or video, with defined characteristics in the frequency and amplitude domains.

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Figure 5.74

Signal representation. (a) Waveform: sequence of samples, and (b) model: signal shape and parameters.

With the standard waveform encoding, the signal accuracy depends on the sampling rate and on the resolution (bit number) of samples, while with model encoding the key elements are the model accuracy and the accuracy of the parameters. An example of this technique is the linear predictive coding (LPC) for voice signals [7], based on a vocal segment (larynx) model. The signal is divided into frames (10 to 30 ms each) and for each frame the coder evaluates the following parameters: • Voiced/unvoiced, where voiced segments exhibit a repetitive pattern and unvoiced are more similar to noise; • Pitch (periodicity step); • Coefficients for a filter that matches the signal waveform. The signal is reconstructed using the functional units shown in Figure 5.75. Voiced segments are synthesized sending pulses with the period defined by the pitch through a filter with parameters evaluated to match the original signal. Unvoiced segments are obtained from properly filtered noise. With this technique, the bit rate required for voice with quality comparable to a 64 kbit/s logarithmic pulse code modulation (PCM) encoding (defined as phone quality) is around 2.4 kbit/s. Both have SNRq performance similar to a 12-bit linear standard encoder. The encoding technique used for standard GSM phones uses 13 kbit/s. 5.4.3.1 Comparison of Speech Encoding Performance

The criteria used to verify the quality of speech coders are based on the ability to confirm the identity of the speaker (speaker recognition) and to understand the words, even without speaker recognition (speech understanding ). Speaker recognition requires better quality, and is the standard requirement for civil phone communication where the speaker recognition confirms the identity of the person at the other end of the link. The more limited speech understanding (lacking of speaker recognition) is used mostly for professional

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Figure 5.75

Block diagram of LPC coder. Table 5.9 Comparison of Bit Rates Required for Various Encoding Techniques

Coding Technique

Speed

Waveform encoding Standard /linear ADC Logarithmic ADC Differential ADC Adaptive differential PCM (ADPCM) without speaker recognition

120 kbit/s 64–32 kbit/s 32–16 kbit/s 4 kbit/s

Model encoding LPC (GSM phones) Frequency-slot vocoder LPC (low quality)

13 kbit/s 4.8 kbit/s 2.4 kbit/s

communication, where the correspondent identity is confirmed by other elements (e.g., the use of the link itself ). The bit rates required for the various techniques are summarized inTable 5.9.

5.5 Signal Conditioning This section describes the front-end functional units of an analog-to-digital conversion system. As already outlined in Section 5.1, correct sampling and quantization operations can be performed on signals with known characteristics in the amplitude and frequency domains. The signal conditioning functions described in this section provide signals with controlled parameters for correct sampling and quantization processes. The discussion follows the sequence of functional units in a typical data acquisition system, as already shown in Figure 5.17: • Input protection, to block signals that may damage the other circuits; • Input amplifier, to adapt the signal level to the input range of the ADC; • Anti-alias filter, to limit the signal bandwidth, and make it compatible with the sampling rate;

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• Multiplexer, to allows a single sample&hold and ADC to handle multiple channels; • Sample&hold or track&hold amplifier, to carry out sampling, generating a time discrete signal. This signal conditioning front-end drives the ADC already analyzed in finally, Sections 5.3 and 5.4. Modules with similar functions can be used in the inverse sequence for the DAC chain: first the DAC, then the low-pass filter, and finally the output amplifier. Section. 5.5.6 analyses the key parameter of an ADC system: the ENOB, which reflects the actual overall performance of the complete system, along with other typical FOMs such as SFDR, SINAD, and THD.

5.5.1 Input Protection Signals from the field, besides the useful information, may include EMI, noise, high-voltage spikes from electrostatic charges, or direct contacts. To avoid damages, the voltage applied at the system input must remain within safe limits, as shown in Figure 5.76. This is the task of the input protection circuit, which must be the very first unit in the chain. A clipping circuit can limit the input voltage between Vmax and Vmin . This input protection circuits may use diode clamps, or other devices, such as Zener diodes, transient voltage supressors (TVSs), and varistors. Suitable circuits are shown in Figure 5.77. In most ICs, input voltages that exceed the power supply range ±Vsu cause forward-bias of junctions to the substrate, with possible high current flow and latch-up. Therefore the safe input range usually depends on the power supply. With power off, Vsu = 0, and any input voltage should be considered unsafe. All input protection circuits introduce parasitic capacitances and nonlinear impedances into the signal path, which cause distortion and must be carefully evaluated for the specific frequency ranges expected for the input signal.

Figure 5.76

Input protection. (a) Clipping the input voltage to the safe input range (Vmax −Vmin ), and (b) transfer function of the protection unit.

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Figure 5.77

Limiting circuits; the resistor limits the input current and voltage when the protection is active. (a) Schottky diode clamp to power supply: vo (t ) is limited between vsu + and Vsu −, (b) Zener diodes to ground: vo (t ) is limited to the Zener breakdown voltage, and (c) nonlinear devices Z (e.g., a varistor): vo (t ) is limited by the voltage versus current characteristic of the device.

Figure 5.78

Basic non-inverting voltage amplifier.

5.5.2 Input Amplifier To maximize the SNRq , the signal must fill the ADC input dynamic range; this may require an amplifier (or an attenuator), and/or a level shifter (e.g., from bipolar to unipolar voltages). The ADC accepts specific signal types (generally, voltages or currents), in single-ended (S) or differential (D) configurations. The amplifier that matches the dynamic range and the signal type from system input A to the ADC is the conditioning amplifier. The same amplifier can be used as a voltage-to-current converter, or viceversa, and this leads to the four possible amplifier types summarized in Table 2.1. Each amplifier type can have single-ended and/or differential input and output. All these configurations can be obtained using traditional operational amplifiers with proper feedback; this section analyzes in detail the most used configuration, which is the voltage amplifier. 5.5.2.1 Voltage Amplifier Configurations

The single-ended voltage amplifier is presented in Figure 5.78. The key features of this configuration are a high input resistance Ri and a low output resistance Ro ; in this way the source impedance Rs and the load RL do not affect the voltage gain Av A transresistance amplifier (current-to-voltage converter) is presented in Figure 5.79. The input network can be reduced to a Thévenin equivalent, and the same circuit becomes an inverting voltage amplifier.

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Figure 5.79

(a) Basic transresistance amplifiers (I/V ) and (b) inverting voltage amplifier (V /V ) circuits. With an ideal operational amplifier, i− = 0 and vd = 0. (a) vO = −ii Rm ; (b) vO = −vi RF /RI .

Figure 5.80

Effect of signaling method on noise. (a) Single-ended signaling is sensitive to noise, and (b) differential signaling allows removal of common mode noise.

When the input signal comes from transducers in the field, it can be affected by noise. Differential configurations (Figure 5.80) can be used to reduce noise picked up by long interconnection wires. If the two wires pick up the same noise, this noise is canceled by the common mode rejection of the differential amplifier. 5.5.2.2 Differential Amplifier Configurations

Some transducers have differential outputs, and many fast ADCs operate with differential input signals. Differential amplifiers are therefore needed to handle differential signals. A differential amplifier must amplify differential signals by a defined quantity Ad , and keeps common mode signals at a low level utilizing its low common mode gain Ac . The key parameter is the common mode rejection ratio (CMRR), defined as the ratio between Ad and Ac . For an ideal differential amplifier, CMRR approaches infinity; in a real circuit its value depends primarily on component matching. A differential amplifier can be obtained with an operational amplifier using the circuit shown in Figure 5.81. The differential and the common mode gain for this circuit can be evaluated from vo = A1 v1 − A2 v2 = Ad vd + Ac vc

(5.45)

with vd = v1 − v2 differential voltage and vc = (v2 + v1 )/2 common mode voltage, Ad = (A1 + A2 )/2, Ac = A1 − A2 . It follows that vo = Ad (v1 − v2 ) + Ac (v1 + v2 )/2 = (Ad + Ac /2)v1 − (Ad − Ac /2)v2 . (5.46)

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Figure 5.81

Differential amplifier. With ideal input voltage sources and R3 /R1 = R4 /R2 , the common mode gain Ac is equal to zero.

Figure 5.82

Effect of input impedance unbalance in basic differential amplifier. Zi1 = R1 , v1 = vS1 R1 /(R1 + Rs1 ); Zi2 = R2 + R4 , v2 = vS2 (R2 + R4 )/(R2 + R4 + RS2 ).

For an ideal differential amplifier, Ac = 0 and therefore A1 = A2 ; the differential gain is then Ad = vo /vd = −R3 /R1 .

(5.47)

Since the common mode gain Ac is zero, the circuit amplifies only differential signals and CMRR approaches infinity. Real-world transducers have equivalent resistance RS , which can unbalance the channels of the differential amplifier. With different source resistances RS1 = RS2 , a purely common mode signal (vS1 = vS2 ) generates a differential component, which is amplified and causes a lower CMRR, as shown in Figure 5.82. To preserve CMMR, the circuit must remove the effects of RS1 and RS2 unbalance using high input impedance Zi on both inputs. A first solution is to add voltage followers, but to reduce the overall noise and offset the first stages should have some gain; this consideration leads to the instrumentation amplifier configuration shown in Figure 5.83. This circuit provides high Zi on both inputs; this means the voltage division of vs on RS /Zi can be neglected, and high CMRR can be obtained since the differential gain is balanced for any value of RS .

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Figure 5.83

Instrumentation amplifier. R3 /R1 = R4 /R2 = Dd , R7 = R5 , v2 − v1 = (v2 − v1 ) (2R5 /R6 + 1).

Figure 5.84

Example of single-ended to differential conversion using a fully differential operational amplifier.

The inverse transformation (from single-ended to differential) can use two amplifiers with the same Av and inverting/noninverting gain, but such configurations introduce different delays in the two paths, and requires many precision resistors. A better solution is to use operational amplifiers with differential outputs, as shown in Figure 5.84.

5.5.3 Anti-Alias Filter Every signal in the real world has a nominal bandwidth where useful information is contained, but also includes out-of-band components such as noise, harmonics, and EMI. The Nyquist rule is to sample at a rate higher than twice the useful signal bandwidth; sampling folds out-band signals inside the useful band, and causes aliasing noise. The amount of aliasing noise depends on the sampling rate and on the shape of out-band spectrum, as shown in Figure 5.85. The parameters of the anti-alias filter can be defined by a frequency ratio and the required attenuation. From B to fs − B the frequency ratio is R = (fs − B)/B. A single-pole filter provides an attenuation corresponding to the frequency ratio R (unity slope in Bode plot); p poles provide a R p attenuation. A single pole provides 6 dB/octave (or 20 dB/decade) attenuation. From B to fs − B, the attenuation Ap corresponds to the frequency ratio: Ap =

fs − B fs − B fs − B → Ap |dB = 6 log 2 = 20 log 10 B B B

(5.48)

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Figure 5.85

261

Effect of sampling. (1) Primary spectrum (baseband); (2) secondary spectra (aliases); (3) folded in band noise (aliasing noise). (a) Ideal signal: input signal band-limited to B: main spectrum and aliases can be separated with a filter, and (b) real signal: input signal spectrum is not limited: main spectrum cannot be separated from first alias.

and the number of poles required to get an attenuation ATOT is p=

ATOT . Ap

(5.49)

This is a worst case scenario; near cutoff some types of filters can drop faster than 20 dB/decade for each pole, and the actual attenuation depends from filter type (Bessel, Butterworth, Chebischeff, elliptic, etc. [5, 9]). The required number of poles can be evaluated using proper design tools [1]. To reduce the aliasing noise, a steeper input filter can be used, but it is also possible to use a higher sampling rate fs ; this leads to the oversampling technique, which moves alias spectra away from baseband, but brings higher digital bit rates and requires a faster ADC. The actual choice comes from the trade-off between analog and digital complexity, as discussed in Sections 5.1.2 and 5.5.1.

5.5.4 Multiplexer The same S/H and ADC can be used for several channels provided that a multiplexer is placed between the single channels conditioning chain elements (input protection, amplifier, filter) and the S/H and ADC block. In a practical system, signals are constantly changing with respect to time on all channels, even on the one selected by the multiplexer. The S/H function should keep the ADC input at a fixed value, but DC and AC cross-talk between channels affects all multiplexers. The multiplexer structure consists of a set of switches and related control circuitry, as in Figure 5.86. Switches are in most cases built with MOS transistors; often a p/n channel pair is used to obtain a lower and constant ON resistance. Errors of a multiplexer can be derived from the MOS parameters; the following analysis uses a simplified model, which considers the ON equivalent resistance Ron , the leakage current Ioff , and the drain-source parasitic capacitor Cds .

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Figure 5.86

Multiplexer unit. (a) Functional diagram, and (b) CMOS switch circuit: parallel n and p-channel devices.

Figure 5.87

Equivalent circuits for gain (a) and offset (b) errors evaluation.

Figure 5.88

Equivalent circuit for dynamic errors. The effects of parasitic capacitance are: OFF state: feed-through (partition from Cds and Cgd to output); ON state: frequency roll-off (low-pass cell Rs , Cgd ). The parasitic capacitance Cp between the output and ground is not shown.

The circuits to evaluate static ON and OFF errors are shown in Figure 5.87. The ON channel has an attenuation from vi to vo caused by the Ron /RL voltage divider. The leakage currents Ioff from the open switches (OFF channels) cause an offset at the output. The dynamic parameters depend on the parasitic capacitors shown in Figure 5.88. The effects include: • An RC low-pass cell (Rs + Ron , Cp ) that causes a roll-off in the frequency response and defines the usable bandwidth; • A parasitic capacitor Cds which causes feed-through from the OFF channels; • A parasitic capacitor Cgd which causes feed-through from the control signal.

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The multiplexing operation changes the signal spectrum: for instance, two multiplexed DC signals become a square wave. A single filter cannot be used to process multiple channels; each input channel requires an independent antialiasing filter, and the multiplexer must be placed after the filter bank. Since each sampling and conversion is independent of the previous ones, a single S/H and ADC can be used to process many channels. There are a number of modern ICs that contain a complete multi-channel data acquisition system on a chip, including input buffers, multiplexer, S/H, and ADC. This level of integration greatly simplifies the use of the converters. 5.5.5 Sample&Hold The value of the input signal to the ADC must remain constant during the complete A to D conversion process. The sample&hold function reads the input value at t = Ts (sample time), and keeps this value at the output (hold operation) as long as required for the complete analog-to-digital conversion. Since before hold the output tracks the input, the unit is better defined as track&hold, although the terms are often used interchangeably. The sample&hold is basically an analog memory; the simplest S/H structure uses a switch (SW) and a memory capacitor (Cm ). The complete operation sequence is shown in Figure 5.89: when the switch is closed vo = vi (tracking); when the switch is open the capacitor keeps the last voltage value (hold). Besides this simple description, in a real circuit many effects introduce various errors, as detailed in the following. 5.5.5.1 Tracking Phase Errors

During tracking, vo = vi (Figure 5.90): the S/H input drives directly the output (in most cases through a unity gain buffer or a K -gain amplifier). Static errors

Figure 5.89

Sample&hold operation and circuit. (a) Basic circuit: S is the Sample command, and (b) Sequence of track/sample/hold operations. (1b) Track; (1c) sample; (1d) hold; (2a) new acquisition; (2b) track; (2c) sample, (2d) hold; (3a) new acquisition, and so on.

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Figure 5.90

Equivalent circuit in the tracking phase.

Figure 5.91

Settling time definition. (1) Input; (2) output.

are the same as discussed for the amplifiers: gain, offset, and nonlinearity errors. Dynamic parameters are the bandwidth and the settling time, which in turn depends on the slew rate and on the required precision. The gain error comes from the attenuation of vi between Rs + Ron and RL . The circuit is a low-pass RC cell, and this causes bandwidth limiting. Considering the various LC parasitic elements, with a step vi in input, the output vo settles with 2nd order transient. The narrower the allowed error margin, the longer the time required to settle, as shown in Figure 5.91: the settling time depends on the precision required by the following ADC. It is worth observing that, while the simple model in Figure 5.90 is a first order network, the actual circuit has a typical higher order response as shown in Figure 5.91. 5.5.5.2 Track to Hold Transient Errors

The switch opens with an aperture delay Tap after the hold command; this delay has a random jitter Tja , which causes an aperture jitter error Vja : Vja = Tja SRmax .

(5.50)

For a full-scale sinusoidal input signal with frequency fa and peak-to-peak amplitude S, the maximum slew rate is SRmax =

 d  S/2 sin(2π fa t) |max = πSfa dt

(5.51)

and the corresponding aperture jitter error is therefore Vja = πSfa Tja .

(5.52)

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Figure 5.92

Equivalent circuit to evaluate the pedestal error. (1) Switch command; (2) pedestal error.

Figure 5.93

Examples of pedestal error compensation using (a) complementary devices (CMOS) and (b) a dummy device Q2 . The charges injected through Cgdn are compensated by the charges through Cgdp and Cgdp , respectively.

The jitter error has a flat distribution; therefore the error power is Pj = (Vja )2 /12; the signal-to-aliasing noise) power ratio the for a sinusoidal input signal is SNRj =

12 Ps S2 1 = = 1.5 2 Pj 8 (πfa Tj S) (πfa Tj )2

(5.53)

which can be written in decibel as SNRj |dB = 1.76 − 20 log 10 (πfa Tj ).

(5.54)

On switch opening, the gate-source parasitic capacitance Cgs of the switch causes a charge injection to the storage capacitor Cm : this is the pedestal error Vp , on the voltage Vo stored on Cm , as shown in Figure 5.92. If Vc is the command signal, Vp = Vc

Cgs . Cgs + Cm

(5.55)

The pedestal error can be limited using CMOS switches with complementary commands, or with a dummy device that injects opposite charges at switching (Figure 5.93). A complete view of track-to-hold errors is presented in Figure 5.94.

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Figure 5.94

Track-to-hold errors and timing. (1) input signal; (2) S/H command; (3) S/H output; (4) pedestal error (command feed-through); (5) error from switch delay jitter Tja . For a Hold command issued at t = 0, the conversion can start after TC = Tap + Tja + TS .

Figure 5.95

Hold phase errors. (1) Input signal; (2) ideal S/H output, (3) effect of decay, (4) actual S/H output with decay and input signal feed-through.

Figure 5.96

Equivalent circuit for decay (1) and feed-through errors (2) (hold phase).

5.5.5.3 Hold Errors

The charge stored on the capacitor after sampling changes over time and modifies the output voltage, as shown in Figures 5.95 and 5.96. After sampling the hold capacitor discharges through the load RL and the switch leakage current Ioff ; this causes a decay error. The input signal can reach the output through switch parasitic capacitances: this is the feed-through error. Moreover, the voltage on Cm has a slow drift; this is a long term effect, related to the type of insulator in the capacitor, and is called dielectric absorption; (not shown in Figure 5.95). 5.5.5.4 Acquisition Errors

In the hold-to-sample transition the output reaches the input after the acquisition time Tacq . This parameter depends on bandwidth, slew rate, and the required

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Figure 5.97

267

Charge flow from/to Cm for various error causes. (1) Decay; (2) pedestal; (3) feed-through. Table 5.10 S/H Errors and Related Countermeasures Error

Caused by

Countermeasures

Decay

SW leakage currents

Isolate the load (e.g., with a voltage follower) Increase the value of the memory capacitor Cm

Pedestal

SW parasitic capacitance

Use switches with low parasitic capacitor Cgd Increase the value of the memory capacitor Cm Compensate with opposite sign charge injection (e.g., with dummy CMOS, Figure 5.93)

Feed-through

SW parasitic capacitance

Use low parasitic (Cds ) switch Increase the value of the memory capacitor Cm

tracking precision. This last element depends on ADC resolution: the same S/H can have different acquisition times when used for ADCs with a different number of bits. 5.5.5.5 Selection of the Hold Capacitor C m

Figure 5.97 and Table 5.10 summarize the origin of S/H errors and the countermeasures to limit them. The memory capacitor Cm is a key element for these errors: • Feed-through error comes from the partition of vi between Cds and Cm ; • Pedestal error comes from a partition of the vgs command step between Cgd and Cm ; • Decay error is caused by discharge of Cm on the load. A general rule to reduce decay, pedestal, and feed-through is to increase the value of the hold capacitor Cm . On the other hand, acquisition time also depends on the value of Cm ; higher values of Cm reduce errors but increases the acquisition time Tacq . For this reason most integrated S/H have a basic Cm (low value) inside, with the possibility to add external capacitors to increase Cm . The external capacitor must be selected to limit dielectric polarization errors.

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Figure 5.98

Isolation of memory cell (Cm ) from input and load.

Figure 5.99

S/H circuits with switch referred to ground. (a) Inverting amplifier/integrator, and (b) single-feedback voltage follower.

5.5.5.6 Examples of S&H Circuits

The basic S/H circuit can be modified to minimize errors; a first step is to isolate the SW-Cm group from the signal source and the load. A suitable circuit is presented in Figure 5.98 where the two voltage followers isolate the memory capacitor Cm from the input source and the output load. To avoid the sum of gain and offset errors from the two stages, the feedback can be closed around the complete S/H, to create a unique voltage follower. This single feedback loop provides higher loop gain, which reduces gain and offset errors, but may cause stability problems. This circuit requires a floating switch; the configurations in Figure 5.99 use switches with one side tied to ground (or to a fixed voltage), with simpler command circuits. Modern high-speed high-performance IC ADCs generally have an internal S/H circuit. The user has just to provide a sampling clock. The overall ADC DC and AC specifications include the effects of the internal S/H. The addition of the internal S/H function therefore greatly simplifies the selection and application of integrated ADCs, and changes the design into a device selection process, which still requires a good understanding of the system and device parameters. 5.5.6 Total ADC System Errors and ENOB The accuracy of an ADC system is not just given by the resolution N of the ADC, but depends on several elements: each functional unit introduces errors and noise, which impacts a specific SNR contribution, as summarized in Table 5.11 The actual relevant figure is the total error of the complete system, defined by the total signal-to-noise ratio: SNRT , measured taking into account all

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Table 5.11 Functional Units and Corresponding Error Sources Functional Unit

Error Source

Error Parameter

Amplifier Filter Sample&hold ADC

Gain, offset, nonlinearity, band limits Out-band signal Sampling jitter Quantization

SNRa SNRj SNRq

error sources: quantization, aliasing, sampling jitter, and errors in the signal conditioning chain (linear and nonlinear). The maximum instantaneous error and noise voltage is the sum of specific noise voltages:
Vn,T = Vn,i . (5.56) Since errors (like noise) are uncorrelated random variables, the parameters should be expressed in units of power. The total error and noise power Pn,T can be obtained as sum of specific error and noise power contributions:
Pn,T = Pn,i (5.57) i

and for each term i it is possible to write SNRi Pn,i = 10− 10 . Ps

(5.58)

The overall signal-to-noise ratio SNRT can be computed from (5.57) and (5.58): 1 Pn,T = SNRt Ps

(5.59)

or, in decibel, SNRT |dB =

10 log 10

1  i

Pn,i /Ps

.

(5.60)

The number of bits N (resolution) of the ADC is just one of many system parameters; it describes the behavior of the ADC, that corresponds only to the quantization noise figure SNRq . The performance of the complete conversion system is described by SNRT , which can be evaluated from specific SNR as previously described. This parameter can be expressed in terms of ENOB, defined by solving the equation for SNRq for sinusoidal signals as a function of N (Section 5.1): SNRq |dB = 6N + 1.76. (5.61)

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Solving (5.61) for N gives the number of effective bits provided by the system: ENOB =

1 1 (SNRT − 1.76) = SNRT − 0.3. 6 6

(5.62)

This parameter includes all noise and error sources (such as quantization, aliasing, and sampling jitter), and represents the number of actually useful bits of the analog-to-digital conversion system. As described in Section 5.1, the errors of an ADC system are defined by several parameters (ENOB, SNR, THD, bandwidth, etc.). These specifications have become industry standards for modern IC ADCs with internal T/H functions, and provide a method for customers to select and evaluate ADCs for specific applications.

References [1]

Analog Filter Wizard by Analog Devices, filterwizard/.

https://www.analog.com/designtools/en/

[2]

Bennett, W. R., “Spectra of Quantized Signals,” The Bell System Technical Journal, Vol. 27, No. 3, July 1948, pp. 446–472, DOI: 10.1002/j.1538-7305.1948.tb01340.x.

[3]

Crovetti, P. S., R. Rubino, and F. Musolino,“Relaxation Digital-to-Analogue Converter,” Electronics Letters, Vol. 55, No. 12, 2019, pp. 685–688, DOI: 10.1049/el.2019.0784.

[4]

Del Corso, D., and C. Passerone, “A Taxonomy of ADC Architectures for ICT Engineering Curricula,” AEU—International Journal of Electronics and Communications, Vol. 84, 2018, pp. 394–402, DOI: https://doi.org/10.1016/j.aeue.2017.11.006.

[5]

Dimopoulos, H. G., Analog Electronic Filters: Theory, Design and Synthesis, Analog Circuits and Signal Processing, Springer Netherlands, 2011.

[6]

Kester, W., Data Conversion Handbook, Analog Devices series, Elsevier Science, 2005, Chapter 3, https://www.analog.com/en/education/educationlibrary/data-conversionhandbook.html.

[7]

Rabiner, L. R., and R.W. Schafer, Introduction to Digital Speech Processing, Foundations and Trends in Technology, Hanover, MA: Now Publishers, 2007.

[8] Tank, D., and J. Hopfield, “Simple ’Neural’ Optimization Networks: An A/D Converter, Signal Decision Circuit, and a Linear Programming Circuit,” IEEE Transactions on Circuits and Systems, Vol. 33, No. 5, May 1986, pp. 533–541, DOI: 10.1109/TCS.1986.1085953. [9] Taylor, F., and A. Williams. Electronic Filter Design Handbook, Fourth Edition, New York: McGraw-Hill Education, 2006. [10] Verster, T. C., “A Method to Increase the Accuracy of Fast-Serial-Parallel Analog-to-Digital Converters,” IEEE Transactions on Electronic Computers, Vol. EC-13, No. 4, August 1964, pp. 471–473, DOI: 10.1109/PGEC.1964.263853.

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271

Selected Bibliography Bellamy, J., Digital Telephony, Wiley, 1991. (Voice digital conversion, linear and logarithmic PCM, differential converters.). Carusone, T. C., D. Johns, and K.W. Martin, Analog Integrated Circuit Design, Wiley, 2012.(Broad content, good chapters on integrated ADCs and DACs.) Hoeschele, D. F., Analog-to-Digital and Digital-to-Analog Conversion Techniques, Wiley-Interscience 1994. (Circuits for ADC and DAC, sampling.) Jung, W., and Analog Devices, Inc., Op Amp Applications Handbook, Analog Devices Series, Elsevier Science, 2005, https://www.analog.com/en/education/education-library/opampapplications-handbook.html. Kaneko, H., “A Unified Formulation of Segment Companding Laws and Synthesis of Codecs and Digital Compandors,” Bell System Technical Journal, Vol. 49, No. 7, 1970, pp. 1555–1588, DOI: 10.1002/j.1538-7305.1970.tb01843.x. (A and mu coding laws for vocal signal.) Kester, W., “A Brief History of Data Conversion: A Tale of Nozzles, Relays, Tubes, Transistors, and CMOS,” IEEE Solid-State Circuits Magazine, Vol. 7, No. 3, 2015, pp. 16–37, DOI: 10 . 1109 / MSSC . 2015 .2442371. Kester, W. K, “ADC Input Noise: The Good, The Bad, and The Ugly. Is No Noise Good Noise?,” Analog Dialogue, 2006, https://www.analog.com/media/en/analog-dialogue/volume-40/number1/articles/adc-input-noise.pdf. Murmann, B., “The Race for the Extra Decibel: A Brief Review of Current ADC Performance Trajectories,” IEEE Solid-State Circuits Magazine, Vol. 7, No. 3, 2015, pp. 58–66, DOI: 10.1109/MSSC.2015.2442393. Razavi, B., “A Tale of Two ADCs: Pipelined Versus SAR,” IEEE Solid-State Circuits Magazine, Vol. 7, No. 3, 2015, pp. 38–46, DOI: 10.1109/MSSC.2015.2442372. Robertson, D. H., “Problems and Solutions: How Applications Drive Data Converters (and How Changing Data Converter Technology Influences System Architecture),” IEEE Solid-State Circuits Magazine, Vol. 7, No. 3, 2015, pp. 47–57, DOI: 10.1109/MSSC.2015.2442391. Steele, R., Delta Modulation Systems, Pentech Press Ltd., 1975, http://www.ti.com/dataconverters/learning-center.html. (Tutorials and detailed references for DACs and ADCs from TI website.) Verhelst, M., and A. Bahai, “Where Analog Meets Digital: Analog-to-Information Conversion and Beyond,” IEEE Solid-State Circuits Magazine, Vol. 7, No. 3, 2015, pp. 67–80, DOI: 10.1109/MSSC.2015.2442394.

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Acronyms and Abbreviations AC ACPR ADC ADPCM ADPLL AGC AM ASK AWGN BC BE BJT BPF C-B C-C C-D C-E C-G C-S CAE CCO CDR CE CIMR CIMR3 CMRR CS CW DAC DBM DC DDS

Alternating current Adjacent channel power ratio Analog-to-digital converter Adaptive differential PCM Analog-to-digital PLL Automatic gain control Amplitude modulation Amplitude shift keyed Additive white Gaussian noise Base-collector Base-emitter Bipolar junction transistor Band-pass filter Common base Common collector Common drain Common emitter Common gate Common source Computer-aided engineering Current-controlled oscillator Clock-data recovery Collector-emitter Carrier-to-intermodulation ratio Carrier-to-third order intermodulation ratio Common mode rejection ratio Conversion start Continuous wave Digital-to-analog converter Double-balanced mixer Direct current Direct digital synthesizer 273

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274

DLL DNL DPA DS DSB DSP DSPLL EMI EN ENOB EOC ET EVM FDM FET FF FM FOM FPGA FSK FSM GPS GS GSM HBT HF HW I/Q IBO IC IF IMD IP ISI ITU LAN LF LNA LO LPC LPF LSB

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Delay lock loop Differential nonlinearity Doherty power amplifier Drain-source Double sideband Digital signal processing Digital signal processing PLL Electromagnetic interferences Enable command Effective number of bits End of conversion Envelope tracking Error vector magnitude Frequency division multiplexing Field-effect transistor Flip-flop Frequency modulation Figure of merit Field-programmable gate array Frequency-shift keying Finite state machine Global Positioning System Gate-source Global System for Mobile Communications Heterojunction bipolar transistor High frequency Hardware In-phase and quadrature Input back-off Integrated circuit Intermediate frequency Intermodulation distortion Intercept point Intersymbolic interference International Telecommunication Union Local area network Low frequency Low-noise amplifier Local oscillator Linear predictive coding Low-pass filter Least significant bit

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Acronyms and Abbreviations

LTCC LW MESFET MOS MOSFET MSB MW NCO OBO P1dB PA PAE PAM PCB PCM PD PDF PFD PLL PM PSK PWM QAM QPSK RF RFID RX SAR SAW SDR SFDR SINAD SMD SNR SOC SR SR-FF SSB SW SW THD TVS

Low-temperature cofired ceramic Long-wave Metal-semiconductor field-effect transistor Metal-oxide semiconductor Metal-oxide semiconductor field-effect transistor Most significant bit Medium-wave Numeric-controlled oscillator Output back-off 1-dB power compression point Power amplifier Power-added efficiency Pulse amplitude modulation Printed circuit board Pulse code modulation Phase detector Probability density function Phase frequency detector Phase-locked loop Phase modulation Phase-shift keying Pulse width modulated Quadrature amplitude modulation Quadrature phase-shift keying Radio frequency Radio-frequency identification Receiver Successive approximation register Surface acoustic wave Software-defined radio Spurious free dynamic range Signal-to-noise and distortion Surface-mounted device Signal-to-noise ratio System-on-chip Slew rate Set-reset flip-flop Single sideband Short-wave Software Total harmonic distortion Transient voltage supressor

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275

276

TX VCCS VCO VGA WTA ZIF

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Transmitter Voltage-controlled current source Voltage-controlled oscillator Variable gain amplifier Winner takes all Zero intermediate frequency

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List of Symbols β β0 g inl o q η η i o µ ω ωS ωD ωor θe θe,ss vc,q θc θ (t) θi,n ζ A A(D) Ac Ad AD Ai An Ar As Av B

BJT current gain in DC BJT small-signal current gain Gain error Integral nonlinearity error Offset error Quantization error Amplifier efficiency Junction ideality factor Voltage input reflection coefficient Voltage output reflection coefficient Carrier mobility Instantaneous pulsation Sum beat Difference beat VCO center frequency Phase error Steady state phase error Quiescent voltage Constant phase Instantaneous phase Equivalent phase noise Damping Generic continuous value DAC transfer function Common mode gain Differential mode gain Quantization interval amplitude Current amplification Amplitude of n-harmonic component Rebuilt signal Signal full amplitude Voltage amplification Signal bandwidth 277

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278

BL Br BRX C Cm Cox D Dpar Dser Vja F fa fAM fb Fdem fH fIF fL fLO fo fr fs F (s) fS GA Gconv gm GMAG GMSG GP GRX GSS GT GTX iB iC iD ID iE iG IIP3 IS

Telecommunication Electronics

PLL equivalent bandwidth Bit rate Receiver bandwidth AM carrier power Memory capacitor Oxide capacitance per unit area Generic digital value Parallel representation of a binary sequence Serial representation of a binary sequence Aperture jitter error Noise factor Phase noise spectral power density Central frequency of generic Channel A AM modulating signal frequency Central frequency of generic Channel B Demodulation filter Lower cutoff frequency Intermediate frequency Upper cutoff frequency Frequency of local oscillator Operating frequency Resonant frequency Sampling frequency Loop filter transfer function Sum of two frequencies Available gain Conversion gain Amplifier transconductance Maximum available gain Maximum stable gain Operative gain Receiver antenna gain Amplifier small-signal gain Transducer gain Transmitter antenna gain BJT base current BJT collector current MOSFET drain current Diode current BJT emitter current MOSFET gate current Third-order intercept points in input Reverse saturation current

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List of Symbols

iS k L Lconv m g (t) nc Nq (f ) OIP3 Pa Pa PAE PAV Pb Pd Pe,T Ph PI Pj Pn Pn,i Pn,T PO Pq Pq PRX Ps Psat PTX Q Q Ri RL Ro ROPT rπ Rs SNRi SNRo SNRq SNRT SR Sr

MOSFET source current MOSFET DC transconductance MOSFET channel length Conversion loss AM modulation index Modulating signal Number of comparators in a DAC Spectral power density of quantization noise Third-order intercept points in output Power associated to generic channel A Aliasing noise power Power-added efficiency Amplifier previous stage power Power associated to generic channel B Power of harmonics (up to a defined order) Total error power Power of highest spurious signal Input power Jitter noise power Generic noise power Power associated to single error i Total error power Output power Quantization noise power Power of quantization noise Receiver power Signal power Amplifier saturated power Transmitter power Quality factor Stored charge Input resistance Load impedance Output resistance Optimum load for maximum output power BJT small-signal base-emitter resistance Source impedance Signal-to-noise ratio of input signal Signal-to-noise ratio of output signal Signal-to-quantization noise power ratio Total signal-to-noise ratio Slew rate Symbol rate

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279

280

SRmax y Sx Tacq Tap Tc Tce Tck Tc,max Tcomp Tenc Th TH Tja Tk TL Ts Tsu Tt VA Va (f ) vAM (t) vA (t) VA (t) vBE vc VCC vCE VDD vDS VDS,br VDS,k vGS vIF vLO Vref vRF Vsu VT Vth W

Telecommunication Electronics

Maximum slew rate Relative sensitivity of y with respect to x Acquisition time Aperture delay Conversion time Equivalent conversion time Clock period Maximum conversion time Comparator delay Encoding logic delay Hold time of a flip-flop Hold time of a sample&hold unit Aperture jitter Skew margin Latency time Sampling period Setup time Settling time Voltage associated to signal A (DC component) Voltage associated to signal A (frequency domain) Amplitude modulated (AM) signal Voltage associated to signal A (total) Voltage associated to signal A (AC component) BJT base-emitter voltage Maximum value of PLL correction signal Supply voltage BJT colector-emitter voltage Supply voltage MOSFET drain-source voltage MOSFET drain-source breakdown voltage MOSFET drain-source knee voltage MOSFET gate-source voltage Intermediate frequency voltage Local oscillator voltage Reference voltage RF voltage Power supply voltage Thermal voltage Threshold voltage MOSFET channel width

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About the Authors Dante Del Corso became a full professor of electronics at the Politecnico di Torino in 1986. He carried out research and design activities on analog and digital circuits, multiprocessor architectures, high-speed interconnections, signal integrity, artificial neural networks, and on design methodologies for multimedia educational packages. He retired from teaching in 2017. He was editor in chief of IEEE MICRO magazine from 1991 to 1994, and a member of the IEEE-CS publication board and the editorial boards of several publications. Since 1989 he has been the director of the BSC courses in microelectronics engineering at the Politecnico; from 2001 he coordinated the BSC and master courses in electronic engineering. He was the coordinator of the EU 5th framework IST project 3DE: Design, Development, and Delivery Electronic Environment for Educational Multimedia. Dante Del Corso authored or coauthored 150 papers and 8 books and CDROMs in the field of applied electronics, multiprocessor architectures, and use of ICT in education.

Vittorio Camarchia received a Laurea degree in electronic engineering and a Ph.D. degree in electronic and communications engineering from the Politecnico di Torino, Turin, Italy, in 2000 and 2003, respectively. In 2001, 2002, and 2003, he was a visiting researcher in the Electrical and Computer Engineering Department, Boston University, Boston, MA. He is currently an associate professor of electronics in the Electronics and Telecommunication Department, Politecnico di Torino, Turin, Italy. His research is focused on the design and experimental characterization of hybrid and integrated circuits and systems for microwave RF applications both linear and nonlinear (scattering, source/load-pull technique, system-level characterization) and large-signal circuit and system-level modeling of microwave power devices. He is the author or coauthor of around 140 technical publications in journal papers and conference proceedings, a book on electronics for microwave backhaul, plus two book chapters and many technical reports. 281

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Roberto Quaglia received a Laurea degree in electronic engineering in 2008, and his Ph.D. in electron devices in 2012, both from Politecnico di Torino, Torino, Italy. After three years as a post-doc researcher at Politecnico di Torino, he joined Huawei Technologies Italia and later Cardiff University, Cardiff, UK, with a European Fellowship. He is currently a lecturer at Cardiff University, teaching first-year electronics and master-level courses in high-frequency electronic circuits and systems. He has authored or coauthored more than 80 peer-reviewed scientific publications, and his research interest is in the characterization, design, and linearization of high-frequency power amplifiers. Paolo Bardella received a Laurea degree in electronic engineering and a Ph.D. degree in electronic and communications engineering from the Politecnico di Torino, Turin, Italy, in 2002 and 2005, respectively. He is currently an associate professor of electronics in the Electronics and Telecommunication Department, Politecnico di Torino, Turin, Italy. His research is focused on the analysis, simulation, and design of optoelectronic devices. He is author or coauthor of more than 100 technical publications in journal papers and conference proceedings.

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Index transistor RF, 31–85 transresistance, 257 variable gain (VGA), 227 voltage, 257–58 Amplitude distribution, 205 Amplitude modulation (AM) radio, 3 Amplitude shift keying (ASK), 169, 171 Analog-digital PLL (ADPLL), 182, 191–92 Analog quantities, 196–97 Analog signals phase detectors for, 153–55 phase shift for, 160 Analog-to-digital conversion basic techniques, 227–44 defined, 196 logarithmic, 249–53 operations required before, 201‘ steps for, 197 systems, 208–12 Analog-to-digital converters (ADCs), 18, 19, 23–24, 26 about, 195–96 algorithmic, 238 binary representations, 212 complete taxonomy, 241 conversion time, 228 with DAC - feedback converters, 232–33 differential, 244–49 differential nonlinearity error, 229–30 dynamic parameters, 230–31 effective number of bits (ENOB), 210, 268–70 error taxonomy, 229 Hopfield network, 238, 239 mixed, errors in, 238–39 mixed architectures, 236–44 multibit residue, 241–44 with output encoder, 232 parallel (flash), 231–32

A Acquisition time, 266–67 Acronyms, this book, 273–76 Active mixers defined, 114 dual-gate FET, 114, 115 Gilbert cell, 114–16 using single BJT (or FET), 115 See also Mixers Active RC cells, 135–36 Added phase noise, 121 Additive input noise, 148–49 Algorithmic ADC, 238 Aliasing noise, 260 AM demodulation about, 165–66 asynchronous, 166–67 coherent, 167–69 full-wave, with active rectifier, 167 I/Q, 169 NE567, 189, 190 synchronous, block diagram, 167 AM diode detectors, 106 AM double side band suppressed carrier, 165 AM modulation, 165–66 Amplifiers bias network, 34–39 cascode, 46, 47, 65 common emitter, analysis, 46–50 conditioning, 257 differential, 258–60 harmonic-tuned (class F), 80 instrumentation, 259–60 inverting voltage, 257 low-noise, for RF receivers, 54–66 power, for RF transmitters, 66–83 small-signal, 33–54 switching-mode (class D and class E), 77–80 283

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pipeline, 239–41 quantization, 208–9 radiometric configuration, 235–36 residue, 238 sampling, 208 staircase and tracking, 233–34 static and dynamic parameters, 228 static errors, analysis sequence for, 229 successive approximation, 234–35, 237 summary of error terms, 210–12 taxonomy and basic structures, 231–36 total error, 209–10 total system errors and ENOB, 268–70 tracking, 230 transfer function, 228, 230 Anti-aliasing filter, 200, 248, 260–61 Aperture delay, 264 Aperture jitter, 23, 264 Available gain, 58 B Back-off efficiency in, 80–83 input (IBO), 69 output (OBO), 69 Balanced multipliers, 121, 122 Band-pass filter (BPF), 4 Bandwidth, 20, 21 Base-collector (BC) capacitance, 42 Base emitter (BE) junction, 35 Bias BJT, 35–37 linearity and, 65 MESFET, 38–39 MOSFET, 37–38 T circuit, 73 Binary code decimal (BCD), 212 Bipolar DACs, 227 Bipolar junction transistors (BJTs) bias, 35–37 in forward active region, 33, 36 introduction to, 31 large-signal model, 51–53 normalized input signal amplitude, 51 polarization, 36 single-stage configurations, 42–43 small-signal model, 39–40 Bit rate, 171 Bit stuffing, 182 Butterfly diagram complete, 144

Del-Corso:

defined, 143 example with main lock and harmonic lock, 147 example with narrow and wide capture ranges, 146 generation of, 143 for PLL used as FM detector, 165 setup for experimental measurement, 146 Bypass capacitance, 47 C Capacitive weighted networks, 221–22 Capture range defined, 144 effect of parameter changes, 145 effects of VCO modulation, 145 Carrier-to-intermodulation ratio (CIMR), 69 Carrier-to-third-order intermodulation ratio (CIMR3), 96 Cascode amplifiers, 46, 47, 65 Cat whisker detectors, 106–7 CD4046 about, 182, 183 block diagram, 184 input comparator, 184 main features of, 183 phase detectors (PD), 185 VCO circuit, 185–86 Characteristic impedance, 59 Charge pump PD filter, 136–37 Charge pump phase PFD, 157–59 Clipping circuit, 256 Clock-data recovery (CDR) clock/data synchronization and, 181–82 defined, 178 embedded clock and clock recovery circuit and, 182 high-speed digital systems and, 179–81 resynchronization outputs and, 181 Closed loop, 142–43 Coherent demodulation, 167–69 Collector capacitance, 47 Collector-emitter (CE) voltage, 36, 48 Collector feedback, 36 Comb generator, 125 Common base (gate) configuration, 46 Common collector (drain) configuration, 45–46 Common emitter (source) configuration, 45 Common emitter amplifier

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Index

analysis of, 46–50 BJT, 56 exemplary, with bandpass frequency response, 47 LTSpice simulations of, 50 Monte Carlo simulations of, 55 simulation of, 54 Common mode rejection ratio (CMRR), 258 Complex mixer, 14 Conditioning amplifiers, 257 Constant gain circles, 60–61 Constant noise circles, 62–63 Continuous wave (CW) stimulus, 67 Conversion gain, 95 Conversion start (CS), 230 Conversion time, 228, 230, 231 Crystal detectors, 106 Crystal receiver, 4–5 Cubic response, spectrum, 92 Current switches, 219, 220–21 D Decay error, 266 Decimation process, 24, 25 Delay lock loops (DLLs), 179 Dielectric absorption, 266 Difference beat, 5 Differential amplifiers, 258–60 Differential converters about, 244–46 dynamic range, 248–49 example of, 248, 249 formatting of serial output data and, 246 structure, 245, 246 See also Analog-to-digital converters (ADCs) Differential nonlinearity (DNL), 215 Differential nonlinearity error, 229–30 Digital modulation and demodulation ASK, 170, 171 examples of complex multibit signals, 171–72 eye diagram, 171, 172 FSK, 170 PAM, 169, 171 PSK, 170, 171 QAM, 170, 172–73 QPSK, 170, 173 Digital quantities, 196–97 Digital signal processing (DSP), 19 Digital signals

Del-Corso:

duty cycles, 155 modulation, MATLAB script, 193 phase detectors for, 155–57 phase shift for, 155, 160 Digital-to-analog conversion, 196 Digital-to-analog converters (DACs) about, 195–96, 212 bipolar, 227 capacitive weighted networks, 221–22 circuits, 217–27 current switches, 219, 220–21 defined, 18 differential nonlinearity (DNL), 215 error analysis, 223–24 errors in, 213–17 error taxonomy, 214 gain error, 215 glitches, 216–17 indirect, 225–26 integral nonlinearity, 215–16 ladder networks, 221, 222 linear codes, 213 linear errors, 214–15, 223 mixed linear/weighted, 224–25 multiplying, 226–27 nonlinear, 223 nonlinear errors, 214, 215–16 nonmonotonic, 215 offset error, 215 potentiometric, 218 pulse width modulated (PWM), 225–26 reconstruction filter, 202 relative gain error, 215 settling time, 216 slew rate (SR), 216 static and dynamic parameters, 212–13 static errors, 213–14 thermometric, 218 transient response of, 216 uniform quantities, 218 weighted quantities, 218–20 Diode-based multipliers defined, 122–23 half-bridge, 124 rectifier, 123 SRD, 125 varactor behavior, 124 See also Frequency multipliers Diode mixers about, 106–8

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block diagrams, 106, 108 defined, 106 design tips, 108–9 examples of, 109–10 See also Mixers Dirac comb, 19 Dirac delta function, 19 Direct digital synthesizers (DDSs) benefits of, 176 block diagram, 176 commercial, example of, 178–79 example operation of, 177 frequency resolution parameter, 178 output signal, modulation of, 177 sine and cosine signals with, 12 structure and operation, 176 use of, 175–76 vector signal representation, 176 Direct radio frequency sampling, 26–27 Diversity operation, 24 Doherty power amplifier (DPA), 81–82 Doppler, 138 Double-balanced mixers (DBMs) defined, 99 in downconversion, 100 nonlinear elements, 101 in upconversion, 99 Double-balanced upconverter, 117, 118 Double conversion, 23, 24 Double conversion heterodyne, 9, 10 Double sideband (DSB), 93, 94 Drain-source (DS) voltage, 37 Dual-gate FET mixer, 114, 115 Duty cycles digital signals, 155 intermediate, 156–57 E Effective number of bits (ENOB), 210, 268–70 Electro magnetic interferences (EMI), 3 Embedded clock, 182 End of conversion (EOC) flag, 230 Endpoint linearity, 216 Equivalent circuits, 262 Equivalent noise bandwidth additive input noise, 148–49 defined, 147 equivalent phase noise, 150 noise-only input, 149–50

Del-Corso:

PLL, 147–53 SNR, 152–53 Equivalent phase noise, 148, 149, 150 Error vector magnitude (EVM), 70, 71 Eye diagram, 171, 172 F Feed-through error, 266 FET resistive mixers balanced, 111 block diagram, 110 circuit schematic, 112 defined, 110 design tips, 111–12 integrated, 112 Field-effect transistors (FETs) introduction to, 31 in saturation, 33 Field-programmable gate arrays (FPGAs), 26 Figure of merit (FOM) defined, 57 frequency multipliers, 120–21 mixer, 94–96 power amplifiers, 66–71 Fixed base bias circuit, 35 FM signals, 163–65 Folded cascode, 46 Folding, spectral, 20, 21, 22 Fractional synthesizer, 174–75 Frequency conversion circuits about, 89 mixers, 89–119 multipliers, 119–27 Frequency division multiplexing (FDM), 22–23 Frequency doubler, 127 Frequency drift, 168–69 Frequency modulation, 138 Frequency multipliers about, 119–20 architectures, 121–22 balanced, 121, 122 diode-based, 122–26 figure of merit (FOM), 120–21 mixers in creation of, 122 noise figure, 121 realized with SRD, 125 saturation, 155 single-ended, 120, 121 symbol and ideal behavior, 119 transistor-based, 126–27

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287

Index

Frequency ramp, 140 Frequency range, 94, 120 Frequency resolution, 178 Frequency shift keying (FSK), 170 Frequency step signals, 139 Frequency synthesizers about, 173 fractional synthesizer, 174–75 integer synthesizer, 174 settling time and resolution, 173–74 Friis’ formula, 55 G Gain available, 58 conversion, 95 loop, 137, 138 operating, 57 phase, 132 transducer, 58 Gain error, 215 Galena, 107 Gate-source (GS) voltage, 37 Giacoletto model, 39, 42 Gilbert cell mixer, 114–16 Glitches, 216–17 Global System for Mobile Communications (GSM), 24, 25 Gray codes, 212 H Hardware (HW), 18 Harmonic lock, 147 Harmonic-tuned amplifiers (class F), 80 Heterodyne architecture, 1 Heterodyne receivers about, 5–6 benefits and drawbacks of, 7 block diagram, 6 defined, 6 double conversion, 9, 10 IF filter technologies, 9–10 image removal with RF filter, 8 I/Q mixer in, 11 multiple conversion receivers, 8–9 Heterojunction bipolar transistors (HBTs), 66 High-efficiency PAs about, 76–77 harmonic-tuned (class F), 80

Del-Corso:

switching-mode (class D and class E), 77–80 See also Power amplifiers High-frequency transistor models, 40–42 Homodyne structures, 16 Hopfield network ADC, 238, 239 I Idle noise, 246 IF filter technologies, 9–10 Image frequency, 7 Image rejection block diagram, 14 downconverter, 118 Harley, 14 with I/Q processing, 13 sequence, 12–14 Weaver architecture, 14, 15 Image rejection mixer, 12–15 Image removal by RF filter, 8 Indirect DACs, 225–26 Information source, 2 Information user, 3 In-phase and quadrature (I/Q) structures, introduction to, 1 Input amplifier conditioning amplifier, 257 differential amplifier, 258–60 signal conditioning, 257–60 voltage amplifier, 257–58 Input-back-off (IBO), 69 Input protection, 256–57 Instrumentation amplifier, 259–60 Integer synthesizer, 174 Integral nonlinearity, 215–16 Integrated PLLs analog-digital PLL (ADPLL), 182, 191–92 CD4046, 182, 183–86 examples of, 182–92 NE567, 182, 186–91 See also Phase-locked loops (PLLs) Intercept point (IP), 50 Intermodulation, 50 Intermodulation distortion (IMD), 69 Inverting voltage amplifier, 257 I/Q demodulation, 169 I/Q mixer defined, 102 in heterodyne receiver, 11 image rejection mixer using, 105

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288

Telecommunication Electronics

in SSB transmitter, 12 SSB upconverter using, 104 as vector modulator/demodulator, 102 I/Q signal processing, 11 I/Q unbalancing, 118 J Jitter aperture, 23 defined, 21 sampling, 23–24 L Ladder networks, 221, 222 Least significant bit (LSB), 212–13 Limiting circuits, 257 Linear codes, 212 Linear DAC, 213 Linear predictive coding (LPC), 254, 255 Linear quantization, 203 Linear time-invariant system response, 90 Link budgets, 57 Local area network (LAN), 26 Local oscillator (LO), 6 Lock range defined, 144 effect of parameter changes, 145 effects of VCO modulation, 145 Logarithmic conversion benefits of, 251–53 circuits, 253 defined, 249–51 LO-IF isolation, 95 Long-wave (LW) range, 5 Loop analysis, 141–44 Loop gain, 137, 138 Loop transfer function, 134 LO pump level, 95 LO rejection, 95 LO-RF isolation, 95 Low IF structures, 15–16 Low-noise amplifiers (LNAs) about, 54–57 characteristics, 64–66 common, with bipolar transistors, 64 constant gain circles, 60–61 definitions, 57–59 design, 63–66 as first block of receiver chain, 54 fundamentals, 57–63 high-level signals and, 7

Del-Corso:

noise figure, 61–63 output as capacitive, 65 power management, 57 for RF receivers, 54–66 stability, 59–60 See also Transistor RF amplifiers Low-pass filter (LPF), 16 M Matched PA, 68 MATLAB scripts AM modulation, 193 digital signals modulation, 193 FM modulation, 192–93 Medium-wave (MW) range, 5 Metal-oxide semiconductor (MOS) technology, 222 Metal-oxide semiconductor field-effect transistors (MOSFETs) bias, 37–38 DC model, 37 single-stage configurations, 43–45 small-signal model, 40 symbols of, 32 Metal-semiconductor field-effect transistors (MESFETs) bias, 38–39 bias circuits for, 39 DC model, 38 defined, 38 nonlinear models for, 41 small-signal model, 40 Mixed linear/weighted DACs, 224–25 Mixed-signals phase detectors, 157–60 Mixer cores, 96 Mixers architectures, 96–101 in creating multipliers, 122 diode passive, 106–10 double-balanced (DBMs), 99–101 downconversion, 89, 90 DSB, 94 dual-gate FET, 114 FET resistive, 110–13 figure of merit (FOM), 94–96 frequency, 89–119 Gilbert cell, 114–16 image rejection, 12–15 impairments, 116–17 I/Q, 11, 12, 102–6 nonidealities, 116–19

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289

Index

single-balanced, 96–98 SSB, 89 switching, 101–6 switching FET, 113 transistor active, 113–16 transistor passive, 110–13 Model encoding, 253–55 Modulation index, 165 Monte Carlo simulations, 55 Most significant bits (MSBs), 178 Multibit residue ADCs benefits of, 241 defined, 241 example of, 243 speed versus complexity with, 242–44 structures, 243 Multiplexers, 261–63 Multiplier factor, 120 Multiplying DACs, 226–27 N NE567 about, 182, 186 amplitude domain parameters, 187–89 bandwidth and filter parameters, 189 block diagram, 187 effect of noise and interferers, 189 electrical characteristics, 188 frequency domain parameters, 189 I-C fixed time constant VCO, 189–91 PD and AM demodulators, 189, 190 tone detector operation, 186–87 NETLISTS for analysis of sensitivity, 84 for bias point analysis, 83 for large-signal analysis, 85 for Monte-Carlo analysis, 84–85 for small-signal analysis, 83–84 Noise bandwidth, 147–53 Noise figure, 61–63, 121 Noise margin, 196 Noise-only input, 149–50 Noise power, 151, 205–6 Noise shaping, 250 Nonlinear system response, 91 Nonlinear transmission lines (NLTL), 124, 125 Nonmonotonic DAC, 215 Nyquist criterion, 200 Nyquist rule, 21 Nyquist-Shannon rule, 20

Del-Corso:

O Offset error, 215 1-dB power compression point (P1dB), 95 Open loop, 141–42 Operating gain, 57 Optimum quantization, 251 Output back-off (OBO), 69 Oversampling, 200–201, 244–49, 261 P Parallel (flash) ADC, 231–32 Passive mixers diode, 106–10 transistor, 110–13 See also Mixers Phase accumulator, 177 Phase detectors (PD) for analog signals, 153–55 CD4046, 185 comparison, 159–60 defined, 129 digital, with set-reset flip-flop, 156 digital, with XOR gate, 155–56 for digital signals, 155–57 FF, operation and waveforms of, 157 mixed-signals, 157–60 NE567, 189, 190 operation in linearity, 133 operations summary, 160 transfer function of multiplier used as, 154 XOR, waveforms for, 156 Phase error, 137–38 Phase follower, 133 Phase-frequency behavior about, 141 capture range and lock range, 144–47 loop analysis and butterfly diagram, 141–44 PLL equivalent noise bandwidth, 147–53 Phase frequency detector (PFD), 157–59 Phase gain, 132 Phase-locked loops (PLLs) about, 129 defined, 129, 130–31 equivalent noise bandwidth, 147–53 integrated, examples of, 182–92 linear analysis, 131–33 locked, 132 lock with phase error, 137 as multipliers, 119

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290

Telecommunication Electronics

overall goal, 129 phase-frequency behavior and, 141–43 symbol, 131 system analysis, 130–40 transfer function, 133, 151 See also PLL applications Phase modulation (PM), 138, 171 Phase-shift keying (PSK), 138, 170, 171 Phase step signals, 139 Pipeline ADC, 239–41 PLL applications coherent AM demodulation, 167–69 data resynchronization and clock/data recovery, 179–82 digital modulation and demodulation, 169–73 direct digital synthesizer (DDS), 175–79 FM and AM demodulation, 163–67 frequency synthesizers, 173–75 See also Phase-locked loops (PLLs) PLL order, 132 Polynomial response, spectrum, 93 Potentiometric DAC, 218 Power-added efficiency (PAE), 67 Power amplifiers class A waveforms, 74 class B waveforms, 75 class D, schematic principle of, 78 class D waveforms, 79 class E, schematic principle of, 79 classes, 71–76 class E waveforms, 80 class F, low-order, 81 Doherty, 81–82 figures of merit (FOMs), 66–71 high-efficiency, 76–80 linear amplifier stage as, 82 linearity, 69 matched, 68 operation quantities, 67 output, 66–67 output power, 67 PAE, 67 for RF transmitters, 66–83 simplified scheme, 73 single-tone test response, 70 tuned load class AB/B, 75 two-tone test response, 70 See also Transistor RF amplifiers Printed circuit board (PCB), 44

Del-Corso:

Probability density function (PDF), 205 Pulse amplitude modulation (PAM), 169, 171 Pulse code modulation (PCM), 254 Pulse width modulated (PWM) DACs, 225–26 Push-push architecture, 121 Q Quadrature amplitude modulation (QAM), 170, 172–73 Quadrature phase shift keying (QPSK), 170, 173 Quantization amplitude distribution, 205 analog-to-digital converters (ADCs), 208–9 defined, 196 error, 203, 204 illustrated, 203 intervals, 228 linear, 203 noise analysis, model for, 250 noise power, 205–6 noise spectrum, 208 operation equivalence, 203 optimum, 251 process, 202–8 SNRq , 206–8 Quartz lattice filters, 9, 10 R Radio-frequency identification (RFID), 5 Radiometric analog-digital conversion, 235–36 Radio spectrum, 1, 2 Radio system architectures about, 1–2 evolution of, 1 functions, 2–3 heterodyne structures, 5–10 receiver, 3–5 transceiver, 27–29 zero IF and low IF structures, 15–17 RC cell filter, 134 Receivers amplification, 4 basic, 4–5 basic operation of, 3–4 block diagram, 4 crystal, 4–5 demodulation, 4

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291

Index

functions of, 2–3, 4 GSM, 25 heterodyne structures, 5–10 low-noise amplifiers for, 54–56 tasks of, 3–4 tuning capability, 3, 4 ZIF, 15, 16 Reconstruction filter, 202 Reflection loss, 96 Relative gain error, 215 Relative sensitivity, 34 Residue ADC, 238 R-RC cell filter, 134–35 S Sample&hold operation acquisition errors, 266–67 defined, 201, 263 effect, 202 errors and related countermeasures, 267 example circuits, 268 hold errors, 266 illustrated, 201, 263 selection of hold capacitor, 267–68 settling time, 264 signal conditioning, 263–68 tracking phase errors, 263–64 Samples defined, 196 reconstruction of time-continuous signals from, 199 Sampling ADC rate, 23–24 analog-to-digital converters (ADCs), 208 band-limited signal, 199 defined, 196, 197 direct radio frequency, 26–27 effect of, 25 effects of, 198 of filtered RF signal, 23 frequency translation by, 19 jitter, 23–25 oversampling, 24, 200–201, 244–49, 261 process, 197–202 signals with spurious components and noise, 22 subsampling, 21–22 theorem, 199 undersampling, 201 of unfiltered RF signal, 23 Scattering matrix, 58

Del-Corso:

Secondary lock, 147 Self synchronizing codes, 182 Set-reset flip-flop (SR-FF), 155, 156 Settling time, 173–74, 216, 264 Short-wave (SW) range, 5 Sigma-delta structures, 249, 250 Signal conditioning about, 255–56 anti-aliasing filter, 260–61 defined, 255 input amplifier, 257–60 input protection, 256–57 multiplexer, 261–63 sample&hold operation, 263–68 See also Analog-to-digital converters (ADCs) Signal constellation, 172 Signal synthesis, 173 Signal-to-noise ratio (SNR), 18, 24, 152–53 Single-balanced mixers, 96–98 Single-ended multipliers, 120, 121 Single sideband (SSB) signals, 11 transmitters, 11–12 upconverter, 104 Single-stage configurations BJT, 42–43 cascode amplifier, 46 common base (gate), 46 common collector (drain), 45–46 common emitter (source), 45 high-frequency response, 43–44 MOSFET, 43–45 Slew rate (SR), 23, 216, 246 Small-signal amplifiers about, 33–34 analysis sequence, 34 bias network, 34–39 BJT small-signal model, 39–40 common emitter, analysis, 46–50 for field effect transistors, 43 high-frequency transistor models, 40–46 MESFET small-signal model, 40 models, 39–40 MOSFET small-signal model, 40 nonlinearity and distortion, 50–53 SPICE transistor models, 53–54 Software (SW), 18 Software-defined radio (SDR) bit requirements, 25

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292

Telecommunication Electronics

direct radio frequency sampling, 26–27 FDM, 22 intermediate steps towards, 19 introduction to, 1 mixing and sampling, 19–21 sampling jitter effects, 23 sampling signals with spurious components and noise, 22 subsampling and folding, 21–22 Speaker recognition, 254 Spectral power density, 149 Spectrum folding, 20, 21, 22 Speech understanding, 254 SPICE circuital simulations, 49 NETLISTS, 83–85 simulations of C-E amplifier, 50 transistor models, 53–54 Spurious free dynamic range (SFDR), 178 Stability, LNAs, 59–60 Staircase ADC, 233–34 Steady state phase error about, 137–38 defined, 137 input signal with linear frequency ramp, 140 input signal with phase step, 138–40 Step-recovery diode (SRD), 125 Subsampling, 21–22 Successive approximation ADC, 234–35, 237 Successive approximation register (SAR), 234 Sum beat, 5 Surface acoustic wave (SAW) filters, 9, 10 Surface-mounted device (SMD), 44 Switching FET mixers, 113 Switching mixers, 101–6 Switching-mode amplifiers (class D and class E), 77–80 Symbol rate, 171 Symbols, list of, 277–80 Synchronous demodulation, 164 System-on-chip (SOC) devices, 16 T Thermometric DAC, 218 Third-order interception points (IIP3 and OIP3), 95–96 Total error, 268 Track&hold defined, 201, 263 errors and timing, 266

Del-Corso:

transient errors, 264–66 See also Sample&hold operation Tracking ADCs, 230 Transceiver architectures, 27–29 Transceivers architectures, 27–29 block diagram, 28 structure, 28–29 ZIF, 27–28 Transconductance, 39 Transconductance mixer, 114 Transducer gain, 58 Transfer function ADC, 228, 230 loop, 134 multiplier used as phase detector, 154 phase detectors (PD), 154 PLL, 133, 151 Transient voltage suppressors (TVSs), 256 Transistor active mixers, 113–16 Transistor-based multipliers, 126–27 Transistor modeling, 32–33 Transistor passive mixers, 110–13 Transistor RF amplifiers about, 31–32 small-signal, 33–54 transistor modeling, 32–33 Transmission channel, 2 Transmitters function of, 2 power amplifiers for, 66–83 single sideband, 11–12 Transresistance amplifier, 257 U Undersampling, 201 Uniform quantities digital-to-analog converters (DACs), 218 Upper cutoff frequency, 48 V Variable gain amplifier (VGA), 227 Varicap (varactor) diodes, 162, 163 Voltage amplifiers, 257–58 Voltage-controlled current source (VCCS), 72 Voltage-controlled oscillators (VCOs) actual spectrum from, 163 CD4046, 185–86 circuits, 160–63 control voltage, 161 defined, 129

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293

Index

gain, 132 high-frequency circuits, 161–62 input signal with same frequency, 133 local signal generation, 132 lock range and capture range and, 145 low-frequency circuits, 161 NE567, 189–91 phase noise and spurs, 162–63 W Weaver architecture, 14, 15 Weighted codes, 212 Weighted networks capacitive, 221–22 defined, 218 with ladder structure, 221

Weighted quantities digital-to-analog converters (DACs), 218–20 Winner takes all (WTA) comparators, 170 Wireless information transfer range, 2 Z Zero intermediate frequency (ZIF) architecture use, 16 commercial radio system, 17 as homodyne structure, 16–17 introduction to, 1 operation, 16 receivers, 15, 16 transceiver, 27–28

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