Surface and Interface Effects in VLSI [1st Edition] 9781483217765

Table of contents :
Content:
VLSI Electronics Microstructure SciencePage ii
Front MatterPage iii
Copyright pagePage iv
List of ContributorsPage ix
PrefacePages xi-xiiROBERT S. BAUER
Chapter 1 - Interfaces and DevicesPages 3-26ROBERT S. BAUER, THOMAS C. McGILL
Chapter 2 - Characterization of the Si-SiO2 InterfacePages 29-77S.A. SCHWARZ, M.J. SCHULZ
Chapter 3 - Fundamental Studies of Interfaces: The Unified Defect Model and Its Application to GaAs Integrated CircuitsPages 79-117WILLIAM E. SPICER, STEPHEN J. EGLASH
Chapter 4 - Heterostructure Device Physics: Band Discontinuities as Device Design ParametersPages 121-166HERBERT KROEMER
Chapter 5 - Interface Constraints on MESFET and MISFET ArchitecturesPages 167-236H.H. WIEDER
Chapter 6 - The Role of Boundary Conditions in Near- and Submicrometer-Length Gallium Arsenide Structures*Pages 237-321H.L. GRUBIN, J.P. KRESKOVSKY
Chapter 7 - Carrier Transport at the Si–SiO2 InterfacePages 323-361J.A. COOPER JR, D.F. NELSON, S.A. SCHWARZ, K.K. THORNBER
IndexPages 363-375
Contents of Other VolumesPages 377-383

Citation preview

VLSI Electronics Microstructure Science A Treatise Edited by Norman G. Einspruch

VLSI Electronics Microstructure Science Volume 10 Surface and Interface Effects in VLSI Edited by

Norman G. Einspruch College of Engineering University of Miami Coral Gables, Florida

Robert S. Bauer Xerox Corporation Palo Alto Research Center Palo Alto, California

ACADEMIC PRESS, INC. (Harcourt Brace Jovanovich, Publishers)

Orlando San Diego New York London Toronto Montreal Sydney Tokyo

COPYRIGHT © 1985, BY ACADEMIC PRESS, INC. ALL RIGHTS RESERVED. NO PART OF THIS PUBLICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS, ELECTRONIC OR MECHANICAL, INCLUDING PHOTOCOPY, RECORDING, OR ANY INFORMATION STORAGE AND RETRIEVAL SYSTEM, WITHOUT PERMISSION IN WRITING FROM THE PUBLISHER.

ACADEMIC PRESS, INC. Orlando, Florida 32887

United Kingdom Edition published by ACADEMIC PRESS INC. (LONDON) LTD. 24-28 Oval Road, London NW1 7DX

Library of Congress Cataloging in Publication Data Main entry under title: Surface and interface effects in VLSI. (VLSI electronics; v. 10) Includes index. 1. Integrated circuits-Very large scale integrationAddresses, essays, lectures. 2. SemiconductorsSurfaces-Addresses, essays, lectures. I. Einspruch, NormanG. II. Bauer, Robert S. III. Series. TK7874.V56 vol. 10 621.3819'5835 s 84-19122 ISBN 0 - 1 2 - 2 3 4 1 1 0 - 4 (alk. paper) [621.3819'5835]

PRINTED IN THE UNITED STATES OF AMERICA

85 86 87 88

9 8 7 6 5 4 3 2 1

List of Contributors Numbers in parentheses indicate the pages on which the authors' contributions begin.

Robert S. Bauer (3), Xerox Corporation, Palo Alto Research Center, Palo Alto, California 94304 J. A. Cooper, Jr.* (323), AT&T Bell Laboratories, Murray Hill, New Jersey 07974 Stephen J. Eglash (79), Department of Electrical Engineering, Stanford University, Stanford, California 94305 H. L. Grubin (237), Scientific Research Associates, Inc., Glastonbury, Con­ necticut 06033 J. P. Kreskovsky (237), Scientific Research Associates, Inc., Glastonbury, Connecticut 06033 Herbert Kroemer (121), Department of Electrical and Computer Engineer­ ing, University of California, Santa Barbara, Santa Barbara, California 93106 Thomas C. McGill (3), Thomas J. Watson, Sr., Laboratory of Applied Phys­ ics, California Institute of Technology, Pasadena, California 91125 D. F. Nelsonf (323), AT&T Bell Laboratories, Murray Hill, New Jersey 07974 M. J. Schulz (29), Institute of Applied Physics, University of Erlangen, Erlangen, Federal Republic of Germany S. A. Schwarz (29,323), Bell Communications Research, Inc., Murray Hill, New Jersey 07974 William E. Spicer (79), Department of Electrical Engineering, Stanford University, Stanford, California 94305 K. K. Thornber (323), AT&T Bell Laboratories, Murray Hill, New Jersey 07974 H. H. Wieder (167), Department of Electrical Engineering and Computer Sciences, University of California, San Diego, La Jolla, California 92093 * Present address: School of Electrical Engineering, Purdue University, West Lafayette, In­ diana 47907. t Present address: School of Electrical Engineering, Purdue University, West Lafayette, Indiana 47907. IX

Preface A series of books dealing with the science of microstructures underpinning VLSI electronics would be terribly incomplete without a detailed treatise on surface and interface effects. Concern for the role of surfaces and interfaces in solid-state devices dates to the earliest work on electronics. The most famous example is the transistor, which led to Bardeen's detailed investiga­ tion of surface state effects on semiconductor interfaces. With the advent of integrated circuitry, much of the early concern for the effects of the surface has moderated. Today, high-frequency, optical, and VLSI electronics offer possibilities for dramatic advances in circuit functionality through utiliza­ tion of smaller-geometry devices and novel materials. It is time for engineers, designers, and scientists to focus attention on the limitations and opportuni­ ties provided by a better understanding and control of surface- and inter­ face-related properties. This set of papers by experts in the field illuminates aspects of microstructure that may dominate components whose dimen­ sions are reduced to a scale small enough that their interfaces become an intimate part of the device structure. This special volume presents advances achieved during the past decade in the science of semiconductor surface and interface phenomena on an at­ omistic scale. Following an introductory chapter by Bauer and McGill on the intimate link between interfaces and devices, the book is divided into two parts. First, the chemical and geometric structures of prototypical VLSI interfaces are discussed. Schwarz and Schulz begin with the technologically most important interface, Si-Si0 2 . Spicer and Eglash present extensive evidence of the interplay between interface chemistry and the causes for metal-semiconductor contact behavior, primarily in the III-Vs. This is followed by the second part on electronic properties of interfaces. Com­ pound semiconductors receive the most attention because they are no longer materials of the future, but rather are appearing in real integrated devices. Kroemer discusses the semiconductor-semiconductor interface and how novel barriers can be realized in such heterostructures. Wieder continues with constraints that the microscopic interface places on architectures inxi

XII

Preface

volving metal-semiconductor (MESFET) compared with insulatorsemiconductor (MISFET) device structures. "Ohmic" contacts can control the behavior of very small, high-speed devices, as discussed by Grubin and Kreskovsky. In the final chapter, Cooper, Nelson, Schwarz, and Thornber show that the Si - Si0 2 interface can play a major role in determining carrier transport when MOSFETS are scaled down to ULSI dimensions. These seven chapters provide an entry point into the vast array of ad­ vances that have been made in surface and interface science as they relate to electronics. It is my hope that the reader will gain an appreciation for the importance of linking a fundamental understanding of the interface microstructure with properties of electronic barriers in small devices. These con­ cepts can lead the way to new opportunities for novel materials, devices, processes, and circuits. Future advances in electronics and optoelectronics may well depend on exploiting such knowledge in order to achieve even more exotic components than those with which we deal in today's VLSI world. Palo Alto, California December 8, 1984

ROBERT

S. BAUER

VLSI ELECTRONICS: MICROSTRUCTURE SCIENCE, VOL. 10

Chapter 1 Interfaces and Devices ROBERT S. BAUER Xerox Corporation Palo Alto Research Center Palo Alto, California

THOMAS C. McGILL Department of Applied Physics California Institute of Technology Pasadena, California

I.

II.

III.

IV. V.

Introduction A. Purpose B. Overview Electrical Properties of Interfaces A. Dipole Layers B. Interface Barrier Heights in Devices C. Energy Levels at Interfaces Structure of Interfaces A. Heteroj unctions B. Non-Lattice-Matched Semiconductor Interfaces Reproducibility and Stability Summary and Prognosis References

3 3 4 5 6 8 9 12 12 16 18 20 21

I. INTRODUCTION A. Purpose

We are all very familiar with the marvels of the modern electronics age. These marvels are made possible by one of the great gifts of nature, the Copyright © 1985 by Academic Press, Inc. All rights of reproduction in any form reserved. ISBN 0-12-234110-4

4

Robert S. Bauer and Thomas C. McGill

Si-Si0 2 interface [1,2]. With proper processing, this interface is electrically inactive, making possible planar devices and the advances that we have all come to enjoy. While this rather celebrated interface is the basis for Si VLSI technology, other interfaces such as ohmic contacts [3-7] and Schottky barriers [8] play an important role as well. In spite of this obvious success of silicon technology, future developments in the modern electronics industry will depend heavily on the development of novel materials interfaces. For example, there has been an attempt in recent years to fabricate electronics in III - V semiconductors [8-12]. While small feature devices fabricated in these materials have some very clear advantages (i.e., speed, and compatibility with lasers and light emitting diodes), these technologies are particularily sensitive to the semiconductor interfaces. Atomic-scale properties can determine the kinds of electronic devices that may be successfully fabricated. In this introductory chapter, we explore some of the broad, basic consider­ ations that have led to the research that is described in detail in the other chapters in this volume. An extensive list of references is included to guide the reader to recent advances in this forefront field of VLSI microstructure science. B. Overview

The physical and chemical properties of interfaces are key to the suitability of materials for various applications. Some of the key factors include electri­ cal properties, ease of fabrication of device structures, and long-term integ­ rity. The electrical properties are one of the most important aspects of the interface. Some of the features that determine electrical behavior include the relative position of electronic levels on either side of the interface, the elec­ tronic states present at the interface, and the response of the interface to applied voltages and currents. For example, in metal-semiconductor sys­ tems, the relative position of the Fermi level in the metal with respect to the conduction or valence band edge of the semiconductor is the important parameter governing the Schottky barrier, while for ohmic contacts, the metal-semiconductor interfacial voltage drop must be small under high current injection conditions. In semiconductor-semiconductor systems, the electrical barrier is determined by the band offset between the valence band and conduction band edges of the two semiconductors; defect levels at such heteroj unction interfaces can act as nonradiati ve recombination levels, limiting the usefulness of a given interface in optoelectronic devices. Device fabrication techniques must be consistent with desired interface structures and capable of producing large-area, high-quality layers. New fabrication technologies are being exploited to make a whole new set of

1. Interfaces and Devices

5

electronic devices based on heteroepitaxy [13-17]. These include heteroj unction bipolar transistors [10], selectively doped, high-electron-mobility transistors [18-21], superlattice detectors [22-24], ultra-high-frequency sources [25], as well as high-speed devices [26-28] and quantum well lightemitting structures [29-31]. Each of these new device technologies is pro­ foundly influenced by the properties of the interfaces and the changes that may occur in them during processing. Reproducibility, stability, and reliability of interfaces are the key ingre­ dients in guaranteeing that once made, devices can function for reasonable times. For example, the interfaces in standard devices must withstand nu­ merous electrical and temperature cycles and rather large currents. There are two major breakdown mechanisms for devices. Structural changes can result in the growth of defects or gross interdiffusion across material interfaces. The second mechanism is electrical in that during the operation of the device the population of various defect levels is changed and hence the electrical state of the interface changes. Understanding interface mixing and the effects of thermal and electrical stress on the atomic scale structure is central to the long-term suitability of a given materials couple for devices. We consider here general interface phenomena that have been obtained during the last decade with the advent of controlled preparation techniques and application of sophisticated atomic-scale materials probes. We first present a discussion of the electrical properties of interfaces and then con­ sider the role of chemical structure in determining performance features of devices. A unified view is presented, with interspersed examples chosen from metals, insulators, and other semiconductors interfaced with various semi­ conducting materials. Our discussion stresses compound semiconductors, though many of the observations provide the basis for advanced Si device considerations as well. II. ELECTRICAL PROPERTIES OF INTERFACES

The central feature necessary for creating any solid-state device is a barrier formed between different material regions by a change in the basic substance or its impurities. In order to relate such an alteration in chemical or physical structure to the behavior of the barrier, we must first understand what features of an interface control desired device properties. We use the concept of dipoles to provide a consistent viewpoint in dealing with interfaces. Then we consider the potential step that occurs at barriers and examine features of individual interface types that set its height at such material transitions. Finally, the role of localized energy states in the semiconductor bandgap is discussed.

6

Robert S. Bauer and Thomas C. McGill

A. Dipole Layers

The general problem of determining the relative positions of two elec­ tronic levels across an interface in a solid consists of deciding what contrib­ utes to charge dipole layers that can result in an offset in the electrostatic potential. The interface contribution to both Schottky barriers and heterojunction band offsets may be discussed in terms of such dipole layers [32,33]. One essential feature of any dipole layer is that it contains charge of both signs. The simplest way to look at the effect of a complex-charged dipole layer is to consider the interface region in terms of a simple parallel plate capacitor (see Fig. 1). If the charge per unit area density on each plate of the

DIPOLE LAYERS

+

+ + + + + + + + +

-

+

+ (a)

-H

d

K-

(b)

Fig. 1. Dipole layers: (a) real interface and (b) parallel plate capacitor analog; d, thickness of interface area; σ, charge per unit area density; e, dielectric constant. The density, spatial distri­ bution, presence of charges having both signs, and relative energies across the interface (for heterojunctions) all contribute to the magnitude of the dipole contribution relative to features intrinsic to the bulk materials. This in turn places stringent requirements on the atomic scale structure.

7

1. Interfaces and Devices

capacitor is σ and the dielectric constant is given by €, then the potential step across the interface is given by ΑΦ = ad/ee0, where d is the thickness of the interface layer and e0 is the permittivity of free space. This very simple idea can be translated into any interface problem in which the interface region can be viewed as consisting of charged dipole layers that determine the relative positions of the electronic levels. For these dipoles to be considered part of the interface, they must be sufficiently thin so that they cannot be detected by the appropriate experiments. To see this idea more clearly, let us consider the case of a heteroj unction interface. We can assume that we can define the internal levels of a semicon­ ductor with respect to the vacuum level once we have excluded the surface dipole layers that normally exist on the perfect surface. We can define the difference in the position of, say, the valence band edges in this reference to be the intrinsic band offset. In computing the total band offset, we need to add to this intrinsic band offset the value of the dipole layers that exist between the two materials. The total of the two gives the value of the valence band offset. Hence, we see that the band offset may be thought of as consisting of two terms: one interface related and the other bulk related. To provide some perspective on the values of parameters required to produce a significant dipole layer, assume that e = 1 0 and d= 10 À; then the preceding equation becomes Δ Φ = 181σ

eVÀ 2 ,

where a is the charge per unit area measured in units of the electron charge e. Hence, to produce ΔΦ = 0.1 eV, the areal density of charges is about 5 X 1012/cm2. This is quite a considerable amount of charge, which must be present in both signs within a 10-À region across the interface. Further, the success of purely bulk semiconductor methods for predicting the band off­ sets (the common anion rule [34,35] and Harrison's LCAO theory [36]) suggests that the interface dipole layer contribution is small for perfect, epitaxial systems. Variations in the band offset that can be induced by fundamental changes in processing parameters [37] represent deviations that are not interesting for device applications. Similar arguments can be made for the Schottky barrier. In this case, we assume that there are well-defined levels in the metal and in the semiconduc­ tor (i.e., the conduction band edge) that are referenced to the vacuum level after all surface dipoles have been removed. The value of the barrier height is given by the difference between the energy position of these two levels plus the contribution from the interface dipole layer. Hence we see that, as for

8

Robert S. Bauer and Thomas C. McGill

semiconductor-semiconductor junctions, the Schottky barrier consists of two terms: the interface dipole contribution and an intrinsic contribution from the bulk of the two materials. For metal - semiconductor interfaces that exhibit so-called pinning [38-41], the value of the dipole layer must adjust with each metal in such a way that the resulting barrier height is always approximately the same regardless of the electronegativity of the metal. Any explanation of Schottky barriers must take into account the origin (i.e., sources of charge), sign, and magnitude of such an interface dipole layer. B. Interface Barrier Heights in Devices

Having emphasized the central role of interface dipoles, we must consider the origin of all contributions to the net change in potential across interfaces (in other words, shift of energy levels within device structures at equilib­ rium). We characterize such features by the values of the Schottky barrier height, band offset, and the electronic states at the interface. This in turn determines the suitability of a given interface structure for device applica­ tions. For example, the Schottky barrier height determines how effective a metal electrode-semiconductor field effect transistor (MESFET) structure will be for integrated circuitry. For GaAs, the energy difference between the Fermi level of the metal and the conduction band edge of the semiconductor is many tenths of an electron volt. This large barrier height means that it is easy to form low leakage barriers to «-type material. On the other hand, InP has a relatively small value for this barrier height and, hence, is unsuitable for the fabrication of MESFETs. Such interface electrical properties can drive the choice of VLSI architectures [8,11,12]. Offsets at the edge of the forbidden bandgap play a similar role in heterojunction systems [10,42]. The smaller value of the band offset between the valence compared to conduction band edges in GaAs - AlAs heterojunctions makes it possible to fabricate heterojunction devices such as lasers in which the holes can easily be transferred from one layer to the other. Historically, the relative position of the various electronic levels on either side of an interface has been understood in terms of a set of empirical rules. For band offsets in a semiconductor-semiconductor heterojunction, we now have linear scaling methods [43] and rules of thumb [34,35] that pro­ vide predictions of unmeasured offsets to about ± 150 meV. The widely used free-surface electron affinity rule [44] has been shown to be an improper method for constructing band diagrams for heterojunctions [45-47]. Theo­ retically, the models that have been most successful [48] have assumed that the band offsets are governed by bulk properties without accounting for the interface. At present, we do not have an a priori method for predicting this

1. Interfaces and Devices

9

all-important parameter to the accuracy that is required for various device applications [42]. Similarly, the origins of Schottky barrier heights are not fully explored, and most of our understanding is empirical [49]. Yet by using ideas and observations developed from surface physics experiments, the device properties of Schottky barriers can be converted from rectifying to injecting by depositing a monolayer of foreign atoms at the interface, as shown in Fig. 2 [50]. C. Energy Levels at Interfaces

The density of the interface states at a semiconductor-insulator interface determines whether it can be used for metal - insulator - semiconductor field effect transistors (MISFET) [12]. For GaAs, all of the insulators tried to date produce a high density of interface states that pin the Fermi energy at near midgap. This makes it very difficult to produce inversion at the GaAsinsulator interface. In contrast, insulators have been found that produce interface state distributions at the InP-insulator interfaces that pin the Fermi level near the conduction band edge [41]. This makes it relatively easy to move the Fermi level into the conduction band and, hence, to produce inversion. The successes in making MISFETs using InP is based on this phenomenon. The energy levels at interfaces then determine that MESFETs are the most suitable GaAs device technology, while MISFETs will be more optimum for making InP electronics. Note that heterojunctions provide attractive alter­ natives for both, if the materials science and device physics can be under­ stood. In recent years, there have been some very important observations about states localized within a few atomic layers of the interface. For example, the position of the cleaved GaAs(l 10) surface Fermi level has been found to be the same for a variety of metal overlayers and oxygen [38-40]. This has suggested that the Fermi level is pinned by the electronic states that are intrinsic to the semiconductor and are present at both types of interfaces. These states are thought to be due to defects or defect clusters at the semicon­ ductor interface that are produced during the formation of the interface [38-40,51]. Such ideas can be extended across a series of ternary III-Vs in actual device structures [52], as shown in Fig. 3. Electronic levels at the interface can produce a number of effects. They can act as sources of charge for the pinning of the Fermi level in the case of metal - semiconductor interfaces [32]. They can also holdfixedcharge in the case of insulator-semiconductor interfaces [2,41]. This receptacle of charge can compete with the free charge in the semiconductor so as to reduce the

10

Robert S. Bauer and Thomas C. McGill

Fig. 2. Current - voltage characteristics of Au - CdS( 1010) Schottky diodes as a function of ultrathin reactive Al interlayer thickness. Insert shows cross-sectional schematic of interlayer structure. The effective barrier height can be continuously tuned over the full range from 0 to 0.8 eV. These transport properties have been correlated with observed features of atomic interdiffusion chemistry and valence electronic structure. (From Brucker and Brillson [50].)

free charge under the gate of a MISFET. As discussed earlier for GaAs, these intrinsic interface states are the limitation in fabricating MISFET devices with a given insulator-semiconductor interface. Interface states at semiconductor-semiconductor heteroj unctions can also be very detrimental to the use of that interface in devices. In these

11

1. Interfaces and Devices 1.0

I

1

1

1

1

1

1

1

1

1 it

> °·6

u

L

/ A

0.4 h-

0.2

^

Qr

... 1

L^l

0 In As

1

nfsj ' θ

\-h G

-0.2

^

A /

0.1

0.2

^

1 _ 0.3

1 0.4

1 0.5

1 0.6

MOLE F R A C T I O N GaAs ( x )

1 0.7

1 0.8

1 0.9

1.0 G a As

Fig. 3. Schottky barrier heights ΦΒη and surface Fermi levels E% of «-type Ga^In^As alloys. The Fermi level pinning position is given by a single energy level located ~ 0.5 eV above the valence band and invariant with x as derived from the solid line fit to the data: ΦΒη(χ) = E£x) - 0.53 eV, where Eg(x) = ^(InAs) + 0.56.x + 0.53x2. While the nature of defects is un­ determined, this behavior is consistent with the presence of a single energy level in the semicon­ ductor band gap capable of pinning the Fermi energy. (From Wieder [52].)

structures, the interface states frequently act as recombination centers that will cut down on the performance of devices that are fabricated with these interfaces. These considerations are very important in all optoelectronic devices. The possibility of either controlling the presence or compensating the effect of these defects has led to the suggestion that barrier heights and pinning positions can be controlled in these systems, hence making it possi­ ble to adjust Schottky barrier heights [50,53] and heterostructure potential steps [33,37]. The precise origin of most interface states that are technically important is not known. In the case of a freshly cleaved, clean semiconductor surface, Si has surface states in the gap region while most III - V semiconductors do not. Yet oxidation causes interface states in the gap of both; these are related to incomplete Si-Si0 2 bonding [2,54,55] and growth effects [51] rather than the properties of these starting surfaces [56]. In general, interface states have little ifany connection with states that are present at the clean surface prior to device fabrication. In the case of the metal - semiconductor interface, intrin­ sic states are created near the middle of the semiconductor gap in the pres­ ence of the metal electrode [57,58]. However, all the technically important Schottky barrier states have in recent years been attributed to the presence of defects at the interface [41]. The precise origin of such defects is not known, and we can at present only speculate as to their character and origin [59-61].

12

Robert S. Bauer and Thomas C. McGill

III. STRUCTURE OF INTERFACES

The position of atoms in the region of an interface specifies the properties of the resulting device barrier. Interface structure has presented both theorist and experimentalist with one of the most difficult problems in the field. Broadly, interfaces can be classified as those that are abrupt layers and those with diffuse interfaces. The abrupt interfaces are characterized by deviations in the bulk structure of the constituent materials that occur over a few atomic layers. In contrast, diffuse interfaces have significant deviations in atomic species and/or positions over at least tens of atomic layers. Such deviations from bulk structure may occur not only because of the presence of atoms from the companion material, but also because of defects in the bulk mate­ rial. In this section, we illustrate some of the extremes that have been ob­ served in structure and note some of the effects on interface behavior. The structure of an interface may depend on the method of preparation. The precise parameters that will determine the interface structure are un­ known. In some cases, it would appear that simple thermodynamic argu­ ments based on heats of formation can act as an adequate guide [53,62,63]. In others, the details of the kinetic processes play a role in determining the metastable states that are obtained [64,65]. Impressive control of interface structure has been achieved by such different methods as thermal oxidation (for Si0 2 -Si), thin film annealing (for Pd2Si-Si), metal-organic chemical vapor deposition (MO-CVD) (for GaAlAs-GaAs), and molecular beam epitaxy (MBE) (for III-Vs in general). A. Heterojunctions

To illustrate some of these points, consider the two heteroj unction couples GaAs-Ga^^Al^As and GaAs-Ge. We might expect these systems to be­ have very similarly since both have semiconductors with the same bulk crystal structure and very close lattice match to 0.1%. The GaAsGa^^Al^As heteroj unction on the one hand can be easily grown with a hyperabrupt, monolayer interface transition by either MBE [66] or MOCVD [67]. The TEM photograph in Fig. 4 illustrates the precision in growth and atomic scale characterization that has been achieved. The GaAs-Ge heterojunction, on the other hand, can produce a diffused interface region. Figure 5 is a TEM photograph that illustrates the kind of intermixing that can occur when group IV and III - V compounds having the same crystal lattice are grown together [68]. The segregated nucleation occurs when the compound semiconductor (e.g., GaAs) tries to form epitaxially on an elemental semiconductor substrate (e.g., Ge). A columnar growth

13

1. Interfaces and Devices

ß^-*Si0 2 + 2F2+.

(2)

The presence of oxygen vacancies or trapped holes near the interface would obviously influence the formation of interfacial states. Recently, objections to the charged diffusant hypothesis have been raised [10]. Charges due to excess oxygen are not detected in Si0 2 by C- V techniques or electron paramagnetic resonance (EPR) following oxidation. Raleigh [47] has pro­ posed an alternate explanation for the field dependence experiments based on battery action. The charge state of the diffusant is currently an unresolved issue. B. Initial Growth Phase

Several models of the rapid initial growth phase in dry oxidation have appeared recently. Blanc [48] has proposed a variation of the Deal-Grove model in which molecular oxygen dissociates prior to reacting with the silicon. Tiller [49] has examined the oxidation process in detail and supports an electric field enhancement of diffusi vity in the interfacial region. Tiller and others [10] have noted that the reaction of oxygen to form Si0 2 at the interface requires an excess volume which necessitates the production of interstitials and/or consumption of vacancies. Tiller postulates a dense nearcrystalline oxide in the interfacial region with a large concentration of inter­ stitial Si and SiO depending on the flux of oxygen. Fargeix et al [50] have argued that diffusion is actually retarded and limited by a dense stressed oxide near the interface and have shown their model to be consistent with experimental data. This model has received additional experimental support from Ng et al. [50a]. The more open silica structure on steam-grown oxides might then account for the shorter initial phase in wet oxidation. The effect of stress on oxide growth has been observed in TEM studies by Marcus and Sheng [51]. A recent model of two-dimensional oxidation [52] clearly dem­ onstrates the importance of stress at the interface and its effect on viscous oxide flow during growth. Studies of oxygen incorporation and thefirstfew monolayers of growth by surface techniques may provide additional insights into the nature of inter­ face traps [53]. Low-energy electron diffraction (LEED) studies indicate that the silicon surface layer is rapidly amorphized by oxygen absorption [54]. Dangling-bond silicon states observed by photoemission [55,56] are rapidly

2. Characterization of the Si-Si0 2 Interface

39

quenched by oxygen. Hollinger and Himpsel [57] recently observed four oxidation states of Si as the first monolayer of oxide is formed. Another recent study by Derrien et al. [58] examined the growth of very thin Si0 2 layers using in-situ Auger electron spectroscopy (AES) and electron energy loss spectroscopy (EELS). (Auger electron spectroscopy detects near-surface electron emission with electron energies characteristic of the emitting atom and its bonding environment. The Si0 2 layer thickness is assessed from the decreasing magnitude of the pure Si signal as oxidation progresses). An intermediate SiO state was observed during growth, characteristic of a rela­ tively abrupt interface as discussed in the following section. The authors interpreted their results in terms of a model in which a surface dipole is formed by chemisorbed oxygen. The dipole reverses when the oxygen is incorporated below the surface. Lassabetere et al employ the Kelvin method to monitor the change in work function during the initial stages of oxidation [58a]. The work function increases during the first 20 À of growth and then decreases. The influence of dipole fields at the surface and the Si-Si0 2 interface is a topic of current interest. C. Dopant-Enhanced Oxidation

The oxidation of heavily phosphorus-doped silicon was investigated by Ho et al [59]. The Deal-Grove interface reaction rate was observed to increase radically for phosphorus concentrations greater than 1019/cm3. The Si vacancy concentration is known to increase as the Fermi level moves toward the conduction band edge due to the production of charged vacan­ cies. The effect of this increased vacancy concentration on the diffusion of phosphorus had been previously observed by Fair [60]. Ho and Plummer demonstrated a clear correlation between the rate of oxidation and the vacancy concentration at the interface. The observed activation energy of the interface reaction rate was somewhat less than the predicted value for vacancy generation and migration to the interface or for vacancy generation alone [61]. The mechanism remains unresolved. Their samples were further investigated by Schwarz et al [62] using AES. A spike of phosphorus at the interface, which had been observed previously [63] was monitored as a function of oxidation time as shown in Fig. 7. Initially, phosphorus was found to diffuse from the substrate to the interface and stick there, indicating that the interface acts as a chemical potential well and (possibly) as a vacancy sink. Subsequent annealing studies by Barton et al [64] showed an activa­ tion energy for the phosphorus concentration in the spike. This could be related to the observed Auger shift toward high binding energy for phospho­ rus in the spike [62],

40

S. A. Schwarz and M. J. Schulz

200 r

800 1700 1800 1900 2000 600 700 DEPTH (X) Fig. 7. Six oxides of increasing thickness on a Si substrate (2 X 1020 phosphorus) exhibit a P pileup at the interface as observed by AES. (From Schwarz et al. [62]. Reprinted by permission of the publisher, The Electrochemical Society, Inc.) 100

500

D. Oxidation Effects on Bulk Defects

Observations and models of oxidation-induced stacking faults (OISF) by Hu [65], Murarka [66], and Lin et al [67] demonstrate the production of silicon interstitials at the interface. Stacking faults are essentially chains of Si interstitials that nucleate and grow at defect sites in the Si substrate. The growth of stacking faults and retrogrowth (shrinkage) at high temperatures is illustrated in Fig. 8. Retrogrowth occurs when emission of interstitials from the faults [65,66] or absorption of vacancies [67] exceeds the interstitial generation rate. Murarka has also attributed the decreased retrogrowth tem­ perature in the presence of a Cl ambient to vacancy production. Fair and Carim [68] observe an OISF shrinkage-rate dependence on phosphorus dop­ ing consistent with an increased vacancy concentration. High-temperature vacancy production at the interface may be correlated with increased Qit and ft (drifts VII and XVII, Table I). Oxidation-enhanced diffusion (OED) and more recently oxidation-re­ tarded diffusion (ORD) have been observed for various dopants in silicon. A recent review of these effects by Tan et al [69] argues forcefully for the coexistence of interstitials and vacancies. In general, enhancement of dopant diffusion can be explained by an interstitialcy mechanism while retardation, which occurs at high temperatures or in the presence of a Cl ambient, must proceed via a vacancy mechanism. The correlation with growth and retro­ growth of OISF is striking. Recent experimental evidence for short oxidation

2. Characterization of the Si-Si0 2 Interface

41

TEMPERATURE (°C)

100

1250

1200

1

1150

Γ

1100

Ί

1

80 h

60 I 40

10

6.4

6.6

6.8 10

7.2

7.0 4

T( K

_1

7.4

)

Fig. 8. Oxidation-induced stacking fault growth versus temperature for 3-hr dry oxidation; · , (100); O, (111). (From Fair [41].)

times [70] indicates the existence of a barrier against recombination of interstitials and vacancies. In summary, these studies suggest a denser stressed oxide containing Si or SiO interstitials on the Si0 2 side of the interface. On the Si side, interstitials are generated and vacancies consumed under normal processing conditions; however, at very high temperatures, heavy doping, or in the presence of Cl, vacancies are generated or migrate to the interface. Spectroscopic studies, examined in the next section, shed further light on this model.

42

S. A. Schwarz and M. J. Schulz

IV. INTERFACE MORPHOLOGY

The physical attributes of the Si-Si0 2 interface have been intensively studied by spectroscopic and electrical techniques. Indeed, this well-charac­ terized and relatively well-behaved interface has proven to be an excellent testing ground for the evaluation and improvement of high resolution tech­ niques. Experimental evidence of interfacial abruptness, irregularities, im­ purities, and stress will be presented in this section. Pantiledes [2], Lu­ co vsky et al [3], and Nicollian and Brews [10] are excellent sources for further information on this material. A. Interface Width

In the mid-1970s, several spectroscopic techniques were employed to determine the width of the transition from Si0 2 to Si. Depth profiling of the interface was generally accomplished by ion sputter etching or by chemical means. Depth resolution was limited by sputter-induced atomic mixing and by the inherent surface sensitivity of the spectroscopic technique. Auger electron spectroscopy [71-73] and x-ray photoemission spectroscopy (XPS) [74,75] studies placed upper limits on the transition of— 20 À and suggested an atomically abrupt interface. A model of sputter-induced mixing by Schwarz and Helms [76] (extended recently by Taubenblatt and Helms [77] ) indicated that the measured width was substantially due to this effect. Some dependence of measured width on processing conditions, however, was ob­ served [65]. Helms et al[13] suggested that an undulating interface could account for measured widths greater than a few angstroms. The Rutherford backscattering spectroscopy (RBS) study by Feldman et al [78] on (110)-oxidized Si provided a nondestructive measurement of the interfacial width. Thin oxides were bombarded by 0.8-MeV He+ ions and backscattered He+ was detected at grazing incidence. The background of emission from the Si substrate was low owing to the direction of the incident He+ beam along Si crystal channels. The energy of backscattered He + is a function largely of the scattering atom with a small modification propor­ tional to the distance traveled by the He+ ion in the material. Depth profiles may therefore be obtained from an energy profile of the backscattered He+. Additional scattering will also be observed from Si atoms in the interfacial region that are not registered with the Si lattice. Feldman and coworkers measured the backscattered component as a function of oxide thickness, and by extrapolating to zero thickness, determined a concentration of disordered Si atoms of ~ 2 X 1015/cm2. This value most likely corresponds to one layer of nonregistered Si beneath an Si-O layer. This further limits the interface width to ~ 6 À.

2. Characterization of the Si-Si0 2 Interface

43

Aspnes and Theeton [78a] have employed an ellipsometric technique to study thin oxides on (100), (110), and (111) surfaces. They observed interface widths in the 4 - 9-À range with some dependence on crystal orien­ tation and oxide thickness. B. Interface Roughness

Cross-sectional transmission electron microscopy (TEM) has been used to obtain direct images of the interface [79-81]. In this method, a slice is cut from a sandwich of Si-Si0 2 layers. The slice is thinned by ion milling to a thickness of less than 200 À. The electron beam is diffracted through the Si lattice and the diffracted beams converge in the optics of the instrument. Images obtained by Krivanek et al [80] are shown in Fig. 9. An abrupt interface is observed with occasional atomic steps having a periodicity of ~ 30 À and some modulation to the interface with a wavelength of hundreds of angstroms. The abrupt loss of crystallinity may not actually correspond to the Si - Si0 2 interface however [ 10]. A TEM study by Chen and Sugano [82] in the plane of the interface indicated small Si clusters in the interfacial region ~ 20 À in width with a density of ~ 5 X 1017cm2. Clusters were also observed by Irene [83]. The cluster density was found to be a strong function of oxidation conditions. A LEED study by Hahn and Henzler [84] has examined the dependence of interface roughness on oxidation parameters. Oxides were etched by HF and

Fig. 9. Transmission electron microscopy (TEM) images of 900-Â long segments at (100), ( 111 ), and (911 ) interfaces. (From Krivanek et al [80].)

44

S. A. Schwarz and M. J. Schulz

reoxidation prevented by methanol coverage. A periodicity of step heights is revealed in the technique by observing interferences in the diffracted elec­ tron beam as a function of energy. Beam shapes also reveal information on the distribution of atomic ledges along the surface. Step atom densities varying from 3 to 27% were observed at various growth and anneal tempera­ tures for dry and wet oxidation. Roughness was found to increase as the oxidation rate was increased or the oxidation temperature decreased, corre­ sponding to a balance between reaction-induced roughening and diffusioninduced smoothing. C. Chemical Structure of the Interface

A careful examination of energy profiles from AES sputter profiles of the interface by Chang [71] and Helms et al [85] revealed a chemical state intermediate between Si0 2 and Si in the interfacial region. The integrated concentration of Si in this state corresponded to ~ 1015/cm3 or one monolayer, again indicating an abrupt interface. The XPS studies of Grunthaner et al [75] yielded a more detailed view of the chemical structure at the inter­ face. Chemical etching was used to avoid sputtering artifacts. A complex deconvolution scheme was employed to remove intrinsic and instrumental broadening from the profiles of electron emission energy. The deconvoluted profiles reveal the distribution of Si-O binding energies in the interfacial region. Depth deconvolution was also required as the inherent resolution of XPS is somewhat inferior to AES owing to the higher energy of emitted electrons. A theoretical analysis by Nucho and Madhukar [86] permits a correlation of the various energy peaks with charge transfer from Si to O in the bridging O - Si - O bonds as a function of the bonding angle. These peaks can then be associated with multimembered rings in the oxide as evidenced in Fig. 6 previously. The net result is an abrupt interface with Si+1, Si+2, and Si+3 states present, and an altered 40-60-Ä oxide region near the interface containing primarily odd-numbered ring structures. This result is also con­ sistent with the 30-À region of altered Si0 2 observed by Williams and Goodman [87] by measuring water droplet contact angles on thermal oxides. Grunthaner and co workers observed the production of Si+3 following hot electron injection into thin oxides. They correlated this signal with Si - O - Si bond cleavage resulting in a Si dangling bond and a nonbridging oxygen atom. Electron paramagnetic resonance studies by Poindexter and Caplan [88,89] suggest the presence of trivalent Si at the interface. The EPR tech­ nique detects, the absorption of energy by unpaired electrons from an oscil­ lating magneticfield.The orientation of the sample in a static magnetic field

2. Characterization of the Si-Si0 2 Interface

45

SiO

SiO PbO

V :

;

Λ

C (111) Silicon

V

~\\ ^

SiO

Fig. 10. Model of tri valent Si defects at the Si-Si0 2 interface; O, oxygen; · , silicon. (From Poindexter and Caplan [89].)

determines the energy level splitting at which absorption occurs. Poindexter and coworkers observe a state that is present in neither Si0 2 or Si and thus may be associated with the interface. Correlation with centers in damaged Si suggest that this state (P^) is trivalent Si, that is, Si bonded to three Si atoms with a fourth dangling bond. The orientation dependence of this center on (111), (110), and (100) wafers reveals only simply oriented dangling bonds consistent with an abrupt interface model. The density of centers is strongly correlated with midgap Qit states as observed from growth and annealing experiments. On (100) an additional interfacial center (Pbl) with similar orientational behavior is observed and has been assigned to a dangling bond on a Si atom bound to two Si atoms and one O atom. The proposed struc­ tural model of the (100) interface is shown in Fig. 10. Charging and discharg­ ing of the centers by applied voltage, photon absorption, and UV bleaching is consistent with the Qit correlation. D. Impurity Distributions

Secondary-ion mass spectroscopy (SIMS) has been used by several workers to examine impurity distributions in the interfacial region. This technique simply detects ions emitted during sputter etching. Care must be taken to avoid field-induced movement of ions in Si0 2 during profiling [90]. Johnson et al [90,91] have observed an accumulation of deuterium at the interface that is correlated with DLTS measurements of interface state den­ sity to yield information on hydrogen annealing. Chlorine pileup at the interface has been observed by several workers [64,92,93]. The SIMS profile

46

S. A. Schwarz and M. J. Schulz Τ

1

-Τ

!

Γ

10

8

m

F

o

o

O

6

— o

U

2

-20 -10 0 10 20 DISTANCE FROM INTERFACE (nm)

Fig. 11. Secondary-ion mass spectrometry (SIMS) measurement of Cl pileup at the Si - Si02 interface following TEC/0 2 oxidation. (From Frenzel and Balk [93].)

of Frenzel and Balk [93] observed after oxidation in a Cl ambient is shown in Fig. 11. The tail of Cl extending into the Si is an ion-beam-induced artifact. The Cl peak is located within the oxide as opposed to the P peaks in Fig. 7, which are located on the Si side of the interface. The position of the Cl peak is identical to that of Na+ ions that are drifted to the interface by an applied field. The Na+ distribution has been measured by Kriegler [94] using radio­ active tracers and chemical etchback. A Cl - Na interaction accounts for the reduction of Qm in chlorinated oxides. E. Electrical Studies of Interface Morphology

Several electrical measurement techniques have provided information on the physical attributes of the Si - Si0 2 interface. (Techniques for the study of interface state behavior are described in the following sections.) Photoinjection studies of the Si - Si0 2 interface were pioneered by Williams [95], Powell [96], and DiStefano [97]. The application of a large electric field across the oxide results in a potential barrier at the interface with a height and width that decrease with increasing field. The potential maximum (due to the image force) lies in the oxide, several angstroms from the interface. Photon absorption may be used to inject carriers into the oxide. The barrier (and

2. Characterization of the Si-Si0 2 Interface

47

hence the injected current) is affected by space charge in the oxide. Powell and Berglund [98] demonstrated that photoinjected current is least affected by charge at the interface. Their measurements indicated that Q{and Qit were located within 20 Â of the interface. Brews [99] refined this technique and observed a distribution of interfacial charge with its centroid located ~ 10 À from the interface. These results were supported by photothermal [100] and admittance [101] measurements as described by Nicollian and Brews [10]. DiStefano [102] examined the energy threshold for photoemission over the barrier versus applied field and determined that the oxide conduction band edge was flat (corresponding to stoichiometric Si02) to within 4.5 Â of the interface. Tunneling / - V measurements through thin oxides also were shown by Maserjian [103] to be consistent with an abrupt interface. The scanning internal photoemission (SIP) technique was developed by DiStefano [97] to map potential variations in the interfacial plane. A rasterscanned laser beam is employed in this technique. The induced photocurrent modulates the intensity of a CRT display. DiStefano and Lewis [104] and Williams and Woods [105] observed a marked effect of Na4" on the interfacial potential barrier and also noted a tendency of the Na to agglomer­ ate at the interface. DiStefano and Viggiano [106] examined Na movement in Si0 2 in heavily phosphorus-doped Si and obtained the image shown in Fig. 12. One interpretation of these results is a nonuniform pileup of phos­ phorus at the interface. Most recently, Bouthillier et al. [107] used SIP to examine Na agglomeration as a function of annealing conditions and Cl oxidation. Chlorine oxidation largely negated the effects of Na. Experiments have not determined whether the agglomeration is due to nucleating defects or to a positive feedback effect resulting from barrier lowering at Na clusters. Carrier mobility in the Si MOSFET inversion layer is strongly affected by interfacial charge, phonon scattering, and surface roughness. Mobility stud­ ies have been reviewed by several workers [108,109] and are the subject of Chapter 7 in this volume [ 1 ]. Pioneering studies of mobility at low tempera­ ture by Fang and Fowler [110] indicated that surface roughness is a predomi­ nant effect. Quantum mechanical models of mobility reduction by a peri­ odic surface roughness were employed by Cheng and Sullivan [111], Hartstein et al. [112], and others in the interpretation of their data. Rough­ ness of a few angstroms in height with a period of several to tens of angstroms along the interface was predicted from this work and later found to be in accord with TEM and LEED measurements. Recent room temperature measurements [1] show clear correlations of mobility with Q{ and tempera­ ture, again confirming the location of Q{ at the interface. The MOSFET noise measurements have also been correlated with Qf and Qit [113]. Stress at the interface has a marked and predictable effect on surface mobility, as observed in measurements of Tsaur et al. [114], which results from the

48

S. A. Schwarz and M. J. Schulz

Fig. 12. Scanning internal photoemission study of Na agglomeration at the Si - Si02 inter­ face. The sample is known to have a large interfacial concentration of phosphorus. (From DiStefano and Viggiano [ 106]. Copyright © 1974 by International Business Machines Corpora­ tion; reprinted with permission.)

perturbed Si energy gap and its effect on carrier effective masses. Pepper [115] has described the potential utility of low temperature localization experiments for Si-Si0 2 interface studies. This work continues at a rapid pace. V. INTERFACE TRAPS

At the Si-Si0 2 interface of MOS device structures, the change in the lattice and the electronic structure of the material causes trap levels. Similar to bulk traps in semiconductors, these interface traps rapidly interact with free charge carriers in the semiconductor substrate. The traps arefilledwith majority carriers when the interface is biased into accumulation. When the interface is biased into depletion or inversion, the charge in the interface states is changed. In contrast to these so-called fast interface states, the fixed and mobile charge centers that are located in the bulk of the oxide do not

49

2. Characterization of the S i - S i 0 2 Interface

interact with the silicon substrate except after charge carrier injection across the high interface barrier (e.g., by photoexcitation or by strong heating of charge carriers in silicon in a high electric field). Only interface states that have an energy position within the band gap of the silicon substrate affect devices—and are therefore considered here— because charge trapping is possible at interface states in the same manner as at bulk traps in the forbidden gap of silicon. As shown schematically in Fig. 13, the density of the interface states peaks at the Si - Si0 2 interface. This trap density, which is continuously distributed in the energy gap of silicon, is denoted by Dit in units per square centimeter electron volt. It is not clear today whether the interface states are located in a monolayer at the interface or whether they are distributed within a tunneling depth of a few angstroms into the Si0 2 . Traps in the bulk silicon substrate may also originate from the Si-Si0 2 interface. Such traps will be treated as bulk traps at concentration Ντ(χ). The concentration of bulk traps is generally less than the dopant concentration. They are distributed throughout the space-charge layer width (on the order of micrometers). Their total concentration in the space charge layer may be comparable to the interface state density. Despite 20 years of research, the origin of the residual interface state density achieved in state-of-the-art MOS structures is still unknown. The approach in this section, therefore, is to try to collate the vast amount of available information and to interpret the data using models that have been proposed. Si0~ +

+

+

Si

+

+

E,

·+ + + + + + + + +

; -

- -E t,

,18 10 oxide t r a p s ^ j dopant

210

bulk trap 10

10

A~* "~ μηη interface depth

Fig. 13. Energy and spatial distribution of interface states.

50

S. A. Schwarz and M. J. Schulz

A. Measurement Techniques 7. Quasistatic Capacitance-Voltage (C-V) Technique

The C- V measurement on MOS capacitor structures is the standard method in laboratory practice for determining the distribution of interface states in the forbidden gap of silicon. The method is usually automated, and the high-frequency ( 1 -MHz) differential capacitance CHF( V) is recorded by a commercial bridge. The low-frequency static curve is obtained by recording the displacement current for a slow (~ 10 mV/sec) voltage ramp. The dis­ placement current /is proportional to the low-frequency differential capaci­ tance CLF(V) I=CLF(V)(dV/dt).

(3)

The interface state density is determined in the depletion region (dip of the C- Fcurves) from the difference between the high- and low-frequency capa­ citance

c

At=At(n

-

4

^LF/^o: 1

-

3

-

^LF/^ox

QÌF/Q>:

1

^ H F / ^ ( ;)·

(4)

2 1 0 1 2 3 VOLTAGE ( V ) Fig. 14. Capacitance-voltage ( C - V) plot of an MOS capacitor on p- type silicon substrate; , forward scan; , backward scan. The interface state density Dit = 10 8 /cm 2 eV cannot be determined from this measurement.

51

2. Characterization of the Si-Si0 2 Interface

where Cox is the oxide capacitance, q the elementary charge, and A the area of the capacitor. Various methods exist that relate the bias voltage F applied to the band bending at the interface so hat the energy position Eit of the inter­ face state density measured may be determined [35]. A typical set of capacitance curves for a high-quality MOS capacitor on a p-type silicon substrate is shown in Fig. 14. No separation of the high- and low-frequency capacitance curves is observed on this sample except in the inversion region. An interface state density cannot be extracted from this data because the error in the measurement of the difference signal in Eq. (4) is too large. From this measurement, we deduce only that the interface state density must be less than 1010/cm2 eV. In fact, the interface state density measured by transient spectroscopy (see below) is as low as Dit ~ 108/cm2 eV, which represents the state of the art today. The quasistatic C - F measurement can only be used to check the quality of the interface, i.e., the upper limit of the interface state density and the flat-band voltage, which is a measure of the oxide charge. Electrical measure­ ment techniques that exhibit sufficiently high sensitivity are the conduc­ tance technique [116,117] and transient spectroscopy [118- 120]. 2. Conductance

Technique

In the conductance technique, the full-frequency dispersion of the MOS capacitance is analyzed, rather than just the high- and low-frequency capaci­ tance. In the same manner as for the quasistatic technique, the Fermi energy is used to probe the energy position of the interface states (Fig. 15). The conductance signal Gm of the MOS capacitor assumes a maximum at fireM

Si0 2

Si

ίΓτπτπτ

M

Fig. 15. Basic measurement principle of the quasistatic C- V and the conductance tech­ nique. The Fermi energy is used to probe the energy position of interface states. V = V0 + SV(w); Dit(EF) = -Gp/œ; comax = 2anvthns(EF).

52

S. A. Schwarz and M. J. Schulz

quency =fr°vthns~œt

ω„

= 2avthns

(5)

which is approximately determined by the trapping frequency ωχ. Here^ is a correction factor on the order of 2, which takes into account surface poten­ tial fluctuations; σ is the capture cross section, v^ the thermal velocity of charge carriers in silicon, and ns the charge carrier density at the interface, which is dependent on the position of the Fermi energy. The maximum reduced conductance Gp that is obtained by subtracting the effect of the series oxide capacitance, GJcoCo:

coCox

( 1 - CJCJ2

(6)

+ (GJcoCJ2 '

is directly proportional to the interface state density 1

qAfn \(oC0J

(7) max

where fN is a correction factor on the order of 0.4, which again takes into account surface-potential fluctuations. Conductance measurements are usually quite elaborate, because a wide frequency range must be used for each position of the Fermi energy. The sample temperature must be lowered to reduce the trapping frequency into the measurement range for interface states at shallow energy positions. Figure 16 shows a normalized diagram of the conductance Gp/œ as a function of frequency co/œmax. The width of the maximum is wider than the ideal curve ag = 0 without surface potential fluctuations. The curves mea­ sured can be fitted by assuming a Gaussian surface potential fluctuation at variance σ% on the order 40-70 mV [117].

3

10

I

o ω N

o E O

c

T

^^x>c/

Q.

^-—93K

0.8 0.6 I* Γ

0.4 0.01

σ

9

4.38

V — 1 9 0 K 2.68

/ ideal\

/ I

0.1

\-—296K

Og=0x

1

»

1.0 ω/ω η

1

10

1.7

1

100

Fig. 16. Normalized Gp/co curves obtained at various temperatures by the conductance technique. The variance crg in units kT/q is obtained by curvefitting.(From Deuling et al. [ 117].)

53

2. Characterization of the Si-Si0 2 Interface

3. Transient Spectroscopy

Deep-level transient spectroscopy [118,119,121] (DLTS) is also useful to determine interface traps in MOS capacitors and MOSFETs [ 120,122]. The measurement principle is illustrated in Fig. 17. Interface states are filled by biasing the semiconductor surface into accumulation. The spectrum of emission time constants is analyzed in depletion. Because the emission rate is thermally activated (similar to bulk traps), l/τ = avihNc

exp(-Eit/kT),

(8)

with Nc the effective density of states in the band, a trap spectrum may be obtained in a temperature scan of the transient signal when a fixed time constant is selected in the DLTS analysis [123]. In CC (constant capacitance)-DLTS, the bias voltage is adjusted by feeding back the capacitance signal in order to maintain a constant capacitance. The interface state den­ sity is then simply determined by

c„ SV, Atto = AkT\n(t lt )

(9)

2 x

where ôVis the voltage of the DLTS signal and tU2 are the DLTS sampling times. The energy position Eix of the interface state is approximately given by (10) Eit = kT 1η[σι^ίι/1η(ί 2 Λι)]. The capture cross section σ is obtained from two or more temperature scans taken at different delay time constants tx in the DLTS analysis [119,123]. The evaluation, however, assumes a constant cross section that generally is not valid. The exact evaluation must take into account the energy-depenM M

Si0 2

Si0 2

Si

Si

ππτττΆ

Vat

fe^0_

Voi"

ΤΤΤΤΤΤΆ

(a)

(b)

Fig. 17. The basic measurement principle of transient spectroscopy CC-DLTS. (a) Trap filling: V— Vacc and (b) emission: Cdep, = const., D(x) = δν(τ), 1/τ = vnvthNc exp(—Et/kT).

54

S. A. Schwarz and M. J. Schulz

dent capture cross section [124]. Usually it is quite appropriate to assume a constant average capture cross section in Eq. (10). CC-DLTS is independent of the position of the Fermi energy and thus of the surface potential of the semiconductor. Because CC-DLTS is independent of the potentials, bulk traps are mea­ sured in the full width of the space charge region, independent of the band bending. The bulk trap signal size may be comparable to that of the interface states in CC-DLTS. Potential fluctuations do not hamper the energy resolu­ tion in CC-DLTS; only the size of the signal is reduced when states submerge in the Fermi energy and do not reemit the trapped charge. The problem with DLTS is the deconvolution of the time constant spectrum Ν(τ) into an energy spectrum. 4. Measurement of Interface State Properties

The analysis of interface state properties is explained in Fig. 18. The diagram shows the possible distributions of interface states with the energy position in the x dimension and the capture cross section in the y dimension on a logarithmic scale. A discrete level (e.g., a bulk level having a definite energy position and a definite capture cross section) is represented in Fig. 18 by a dot. A continuum of interface states in the forbidden gap of silicon is represented by a continuous line; it can cover an area if the capture cross section for a state at a given energy is also distributed. This may occur when the states are spread out into the depth of the Si0 2 and the capture and the emission rate are dominated by tunneling into traps at a variable depth. This case is indicated in Fig. 18 by the lined area. States may also be distinguished by the magnitude of the capture cross section. Electrons bound to a positive fixed charge (see the discussion of the charge model, Subsection VI.D) are expected to be rapidly trapped by the attractive coulombic force. Bulk donor centers in silicon have capture cross sections on the order of σ= 10~1210 -13 cm2 for electrons. The capture probability for states deep in the Si0 2 is assumed to be low because the tunneling barrier is several volts at the inter­ face, which inhibits the capture to states deeper than a few angstroms in the Si0 2 . The quasistatic C- F technique senses all traps, independent of the mag­ nitude of the capture cross section, along the vertical line in Fig. 18 that is determined by the position of the Fermi energy. In the conductance tech­ nique, where the full-frequency dispersion is measured, a spot on the vertical line is resolved. In principle, the full interface-state area of the diagram in Fig. 18 can be analyzed by the conductance technique. In practice, the resolution is limited by the potential fluctuations at the interface, which smear the energy resolution of the position of the Fermi energy (indicated by the bars along the vertical line).

55

2. Characterization of the Si-Si0 2 Interface quasistatic CV -12f\ 10

charge

CC-DLTS xe = constant

(NI

! io"15

-18 10 C

C

^Fermi

S

Fig. 18. Measurement of interface state properties.

The CC-DLTS technique is not affected by potential fluctuations. It de­ tects all the interface states that emit at the same time constant τ = constant. These interface states and bulk traps are located at a given sample tempera­ ture on the diagonal straight line in Fig. 18. From this diagram, we can see that additional information on interface state properties may be obtained when results of both techniques—the conductance technique and CCDLTS— are carefully compared. 5. Other Measurement Techniques

There are many variations of the quasistatic C - K[35], the conductance and the CC-DLTS technique [125-136]. The transfer loss of charge-coupled devices allows an accurate determination of interface state densities and capture cross sections [137]. Illumination of the sample with band gap light during C-V measurement offers additional possibilities to determine ma­ jority and minority carrier cross sections independently [125] and to speed up slow states [138]. Photoexcitation of interface states using infrared light in combination with the electrical measurement of the charge exchange has been used to determine the cross section of the optical transition [139-141]. Basically, these electrical measurements sense the charge exchange near the Fermi energy or the quasi-Fermi energy or the transient. Density of states and capture cross sections are determined, but information on the incorpo­ ration of the defect is rarely obtained. Information on the crystallographic structure of the defects at the interface may be obtained by electron paramagnetic resonance (EPR), which has recently been applied to interface state characterization [88,142- 145]. In comparison to the electrical measurement of interface states, EPR is rather

56

S. A. Schwarz and M. J. Schulz

insensitive. Identifying contributions from interface states to the EPR signal is possible only for rather high densities, in excess of At— 10 n /cm 2 eV [144]. Fowler-Nordheim tunneling yields information on the depth distribution profile of interface charges in thin tunnel structures that have a high interface state density after stressing by current injection [146]. B. Energy Distributions

Measurements of interface state distributions within the energy gap of silicon have often been reported [125,138,147,148]. The shape of the inter­ face state distribution shown in Fig. 3 is now generally accepted. The results of the static method and the conductance method are in good agreement for this sample, which shows a rather high density of states (Dit > 10 n /cm 2 eV) where the measurements could be easily performed at reasonable accuracy. A U-shaped distribution is observed; the state density increases towards both band edges. One or more peaks are frequently observed at this high density, indicating that more than one type of interface state is present [149]. Peaks near the band edges [33,150] could not be confirmed; they seem to be an artifact of the measurement [151]. If there is a peak, it is very near or in the conduction band [152]. A similar result of Sher et al. [138] taken on a sample having a high density of states is shown in Fig. 19. The quasistatic C- ^measurement result (curve 1) represents the total density of interface states measured. Three different 10 U

io13 „ Ί>

io11

0.2

0.5 E-E v (eV]

Q

"

1010 0.9

Fig. 19. Distribution of the interface state density Dit as a function of energy E — Ev. Oxidation of the «-type (100) silicon sample to a thickness of 250 À was performed in dry 0 2 at 1150°C with no exposure to hydrogen. A 250-À film of LaF3 was deposited on the oxide by e-gun evaporation. 1. Quasistatic C- V, total; 2. conductance, slow states; 3. conductance, fast states; 4. conductance, fluorine states. (From Sher et al. [138].)

57

2. Characterization of the Si-Si0 2 Interface

I

I

I

!

!

I

I

I

I -I- I

I

Ü10

Ec0

0.5 1.0 E v ECeV] Fig. 20. Distribution of interface state density versus energy. A continuous decay from the conduction band edge is usually observed. The density drops with hydrogen annealing. (From Schulz [9].)

types of states could be separated by the conductance technique (curves 2-4). The density of one type of fast interface states decays more than four orders of magnitude from the conduction band edge towards the valence band edge. This curve (3) is shown again in Fig. 20, together with other results taken on samples that show a lower density of interface states. A general trend is noticed. The highest density is observed in the thin oxide without hydrogen anneal. The standard dry oxide measured by CC-DLTS shows the same decay towards the valence band. The CCD measurement (dashed line) of Kriegler et al [ 137]fitsvery well into this group. Data from Poon and Card [ 125, p. 6273], Tredwell and Viswanathan [ 130], and Monta et al. [ 153], among others, also match this data. Their curves are not included in the graph for clarity. The lowest curve [ 154] and the two points [ 155] in Fig. 20 are measured by CC-DLTS on a sample that received a strong hydrogen anneal [156,157]. The two measurement dots are the lowest interface-state-density values yet reported. Only 108 states/cm2 are observed in the lower half of the band gap. On average, one state is observed in an area of 1 μτη2. Why the increase in a tail of states near the valence band is not observed is not yet clear. These states may not occur in hydrogen-annealed samples [91,123], or they may exhibit a very slow time constant, so that they are not detected in the fre-

58

S. A. Schwarz and M. J. Schulz

quency/time-constant range under investigation. From the general trend, we conclude that all the curves describe the same type of interface states, the density of which may be reduced by strong hydrogen annealing [158]. The characteristic peak in the interface state distribution in Fig. 19 located at approximately 0.3 eV above the valence band maximum is frequently observed [35,91,159 - 161 ]. It is also strictly related to hydrogen and deute­ rium annealing [91,118,160,161]. The capture cross section determined is σ= 5 X IO-14 cm2 [161]. The defect could be related to the Pb spin center observed in EPR results, which show the same annealing threshold [88,91,159,160]. A second peak 0.25 eV below the conduction band edge exhibits the same annealing kinetics. The variation of the spin density with gate voltage identifies both levels to an amphoteric center that is attributed to the dangling orbital on the trivalent silicon defect at the Si0 2 -Si interface [161]. Other peaks are observed in the Dit spectrum, especially after bias-temper­ ature stressing [ 162,163] and after irradiation [ 164 - 170]. The origin of these states is not well established; it may be impurities in the interface region or it may be specific oxide defects [166,171]. C. Capture Cross Sections

Typical capture cross sections measured for electrons in the tail of the fast interface traps from the conduction band are shown in Fig. 21. Values range from ση = 10~17 to 10~14 cm2 in a plateau near midgap [35,172]. Near the conduction band edge, the capture cross section drops several orders of

I

1 O

I

I

' dry oxide -o ° Ö - ^ ~ " ° * - - ^o \ .

annealed oxide

I

"

10,-tt

io' 16

0\0

\ .

\

c

Ί 10

1

I

0.5

0.4

I

0.3 E-E leV)

I

0.2

I

0.1

I

0

^

18

,-20 10

Fig. 21. Electron capture cross section ση of fast interface states near the conduction band.

2. Characterization of the Si-Si0 2 Interface

59

magnitude to values of less than 10~19 cm2. The cross section is independent of (or barely independent of) temperature [ 137,173]. The magnitude of the cross section seems to depend on processing and on the substrate orienta­ tion. The results shown in Fig. 21 are consistent with other measurements [125,153,174]. Only one definite time constant is measured for states at a given energy. The conductance measurement shows only one discrete resonance peak with a symmetrical smear to high and low frequencies (Fig. 16). The sym­ metry indicates that the increased width is a result of potential fluctuations rather than tunneling into states in Si0 2 , which would cause an unsymmetrical resonance peak [117,175,176]. Potential fluctuations are also visi­ ble in transient measurements when the Fermi energy is varied [130]. The hole-capture cross section is measured inp-type silicon. The measure­ ment probably is somewhat obscured by the discrete peak approximately 0.3 eV above the valence band. However, the hole cross section seems to assume high values (σρ = IO - 1 4 - IO -13 cm2) near the valence band rather than de­ crease as the electron cross section does near the conduction band. Although slow time constants are reported for hole capture, especially for low inter­ face-state densities, these properties are yet to be confirmed. Slow capture rates may be a result of the valence band tail of interface states [ 138] which is not observed by CC-DLTS or the conductance technique [123,172]. The magnitude of the cross sections suggests that the fast states behave like acceptors, in agreement with the charge variation in the C- V analysis [141,177,178]. However, it is very difficult to determine the absolute charge value of interface states—especially at the low densities that are state of the art—because in capacitance measurements only the charge change is mea­ sured. The problems associated with C- F measurement in the determina­ tion of trap charge (e.g., donor- or acceptor-type) are discussed in [34]. The properties of charge fluctuations, for example, are in favor of donor-type behavior of the fast interface states. The trap type is therefore still uncertain. D. Effects of Processing

The continuous reduction in interface state density in the past 20 years suggests that impurities and technology may play an important role, because cleanliness standards in semiconductor technology have been continuously improved. The interface state density is greatly reduced with hydrogen annealing, as was shown in Fig. 20. Both the fast interface states near the conduction band and those in the peak near 0.3 eV above the valence band maximum are reduced in the presence of hydrogen or water at elevated temperatures. This

60

S. A. Schwarz and M. J. Schulz

effect of hydrogen is confirmed by many other studies [34,158,177,179]. It is generally accepted that hydrogen saturates some forms of unsaturated bonds within the oxide and at its interface to silicon, thus removing interface states from the silicon band-gap energy region [180,181]. The results of detailed processing studies of interface state and oxide charge [26,34,177,178] are not conclusive because of the complex nature of interface states. The interface state density is frequently proportional to the fixed oxide charge [177,182]; both follow Deal's oxidation triangle, which predicts an increased density of oxide charge and interface state density for decreasing oxidation temperature [26]. The (111) orientation generally yields higher values of both oxide charge and interface state density [26,34,35,183]. Hydrogen annealing is not as effective in removing the oxide charge as it is in reducing the fast interface states [177]. The processing seems to affect the energy dependence of the capture cross section (Fig. 20). Annealing in dry nitrogen and argon may reduce the oxide charge and increase the interface state density [158,177]. Recent results show that the energy distribution of interface traps is also changed after annealing at re­ duced temperatures [184]. A minimum of the interface state density is ob­ served after annealing at temperatures around 950°C (Fig. 22). At tempera-

12

10

is E o

ID

^

6

Q~

U

2

400

600 800 1000 1200 ANNEAL TEMPERATURE (°C)

U00

Fig. 22. Interface state density as a function of postoxidation annealing temperature. The two curves are for deep (Ec — 0.4 eV) (■) and shallow (Ec — 0.15 eV)(#) interface traps. (From Hofmann and Schulz [184].)

2. Characterization of the Si-Si0 2 Interface

61

tures lower than 900 ° C, the interface state density increases strongly. The tail of interface states from the conduction band changes to a distribution with a maximum near midgap (with anneal temperature less than 600 °C in Fig. 22). It is not yet possible to draw conclusions on the origin of interface states based on technological behavior. The effects may be caused indirectly by the reaction kinetics and its influence on an interfacial layer, rather than directly by creating and annihilating interface states [49,53,61,185-187]. E. Impurity Effects

Impurities have sometimes been introduced into the Si-Si0 2 system in­ tentionally in order to examine specific effects. Ion implantation was used to introduce many different impurities [ 165,174]. Many discrete defects in the interface region have been observed; these defects, however, are primarily related to ion implantation effects. Very often, radiation damage levels of the silicon substrate are observed [133,165]. Introduction of heavy metals into the interface before oxide growth shows little direct effect on interface state densities that can be attributed to a specific defect caused by the impurity [188-190]. In thin Si0 2 films, the contact metal may penetrate to the interface and cause discrete peaks [191]. The interface state density increases when the semiconductor substrate is doped by donors or acceptors in excess of n > 1017/cm3 [192]. This effect may be related to oxidation kinetics, which is also affected by large doping concentrations [49,61,185]. Gold is found to be gettered at the Si0 2 -Si interface, although the diffusion of gold to the interface is reduced by the generation of intrinsic defects during oxide growth [61,193]. Alkali ions cause a positive charge in the oxide [28,194,195]. For example, sodium causes a drift instability in devices [196] and must be removed or neutralized by chlorine [197]. Cesium generates a stable positive charge in Si0 2 [35,198,199]. A trap level associated with the sodium ion in Si0 2 , which is located well above the silicon conduction band edge, cannot be related to interface states. An impurity band of fast states, which is related to Na + ions in Si0 2 , is observed in the conductivity of MOSFET channels at low (4 - 70 K) temper­ atures [200-205]. The charge model of interface states [206-207] assumes that electrons in silicon are bound to positively charged Na+ ions in Si0 2 as to a donor center in silicon (see Subsection V. J). The bound electron, however, remains in silicon because the interface barrier repels the charge carriers. The experimental results of the impurity band conductivity just below the con­ duction band seem to be in good agreement with the theoretical predictions

62

S. A. Schwarz and M. J. Schulz

of a shallow binding energy for the accumulation of Na+ ions close to the interface. This accumulation occurs farther away from the interface [200]; the sodium also tends to agglomerate and to cause gross potential fluctua­ tions at the interface. The resolution of an impurity state at 10-30 meV below the conduction band edge requires potential fluctuations of less than 30 meV. This is less than the fluctuations observed in state-of-the-art clean samples [208 - 212]. With the presence of sodium, the fluctuations should be even worse. However, if the interface states are donor centers, the charge fluctuations may disappear at low temperatures when all the donor states are neutral and the charge is well screened. The variation of charge fluctuations at shallow energies in clean samples [210] also seems to confirm a donor-type charge behavior of the centers. Transient spectroscopy measurements [119,121,213] indicate very small contributions to fast interface states for sodium. The coulombic centers visible in the channel conductivity are too fast to be resolved in transient spectroscopy. An increase in density observed near the conduction band edge [119,213] is probably caused by lattice distortions in the interface region. F. Thin Si0 2 Films

For oxides thinner than 40-20 À, most studies have been tunneling ex­ periments [214,215]. Interface states are difficult to determine because of the tunneling current through the Si0 2 and the high capacitance of the thin oxide. Structures in the transition region from thin to thick oxides (which is approximately ^ 40 À) already permit an interface state measurement. Tun­ neling [146] and conductance measurements [191,216,217] show that the general behavior of the interface state density is the same as in thick oxides; however, the density observed is much larger (approximately Dit= 10 11 1012/cm2 eV) than for state-of-the-art thick oxides. The high density may be caused by the oxidation technology, which must accommodate the low growth rate required; it may also be an effect of the transition interfacial layer, which is present in thick oxides but is not well developed in thin oxides. Thin oxides may be easily studied by standard MOS techniques when a top layer of nitride or another insulating film is deposited so that a normal capacitor is obtained [9]. The density of interface states is high (on the order of 1017cm2 eV). The measured density may, however, be affected by tunnel­ ing through the thin Si0 2 to nitride traps and by the stress induced by the insulator cap. Annealing or stressing of the multilayer structure influences the interface state density distribution because chemical reactions and interpenetration of the nitride and the oxide take place [218-220].

63

2. Characterization of the Si-Si0 2 Interface

G. Lateral Nonuniformities

Potential fluctuations are observed in the conductance technique (Fig. 16) [174,176,208,212,221] and are also observed in transient spectroscopy [124,130]. The fluctuations are uniformly distributed in the capacitor, with a minimal fluctuation length of λ « 70-200 À [208-210]. In state-of-the-art MOS samples, the variance of the potential fluctuations is a few kTaX room temperature, corresponding to 30 - 70 meV (Fig. 16) or more [174,176,209 211]. In presence of sodium or after stressing, the fluctuations may be con­ siderably larger. A considerable number of interface states may occur at boundaries of small gate structures [154]. The double-gate structure shown in Fig. 23, which has a large boundary-to-area ratio, has been used in CC-DLTS mea­ surements to study the interface state density at gate boundaries. The result obtained is shown in Fig. 24; CC-DLTS is advantageous in this measurement because it is not affected by the potential variations inherent to the boundary region. One gate of the double-gate structure is used as a guard electrode to vary the contribution of interface states in the boundary region to the tran­ sient measurements. The interface state density is increased by a factor of 100 from the value Dit < 109/cm2 eV in the bulk gate area to Dit > 10 n /cm 2 eV in the immediate boundary of the gates. The origin of these interface states is not known. It may be related to strain induced by the processing technology. The defect density is especially high at the boundary of the polysilicon where underoxidation and protrusions occur. The large defect density is also observed in high leakage currents of the device structure [222]. GATE1 -11 μΓη

GATE 2 *►!-*

11 μηη -

p-type

I

substrate

-

/

Fig. 23. Schematic view of the double-gate striped MOS capacitor structure used in the study of the interface state boundary effect. The structure consists of 2 X 32 narrow 700-μιηlong stripes adding up to a total gate area of 2 X 0.26 mm2. (From Zheng et al. [154].)

64

S. A. Schwarz and M. J. Schulz

0 I 0.0 GATE2

1 00 5

1 0.10 DEPTH [μιη]

1 015

L^_^J\ 0.20 GATE 1

Fig. 24. Interface state density Dit as a function of depth in the transition region of the striped structure in Fig. 23. Two sets of curves are obtained depending on different evaluations in the accumulation and depletion/inversion regions of gate 1, respectively. The discrepancy indicates the error of the measurement. A large density of interface states is present in the immediate boundary of the two gates. (From Zheng et al. [154].)

The large defect density could be reduced by using a deposited oxide cap in order to protect the gate boundary during subsequent processing steps [223]. Edge effects are also visible in the transfer inefficiency of charge couple devices (CCDs) [224]. H. Irradiation Effects

Irradiation effects in Si0 2 may be broadly classified into two major catego­ ries [166], ionizing effects and atomic displacement damage. In the first category, an electron-hole pair is generated in the Si0 2 inherent with a buildup of interface states [225,226]. In Si0 2 films thinner than 50 Â, no additional interface states have been detected [227]. Traps, which become effective after carrier injection, are also induced in the oxide [ 167,228 - 230]. It is generally accepted that electron-hole pairs generated by irradiation are partly separated in the Si0 2 before recombining. Because electrons have a high mobility, they can reach the electrodes, leaving behind the rather immobile holes that are trapped in the Si0 2 [225]. A high concentration of hole traps exists near the Si - Si0 2 interface in the interfacial layer [231]. The presence of an electricfieldserves to separate the electron-hole pairs and to redistribute the charge, depending on the orientation of the electric field [232]. The interface state buildup has been found even for nonpenetrating radia­ tion [233] and occurs only after the positive charge has been transported to

2. Characterization of the Si-Si0 2 Interface

65

the interface [234]. This behavior again suggests the charge model for the interface states. The interface states created are not limited to the vicinity of the conduction band edge, so chemical bond breaking [75,235] and trans­ port of H and OH ions are also very likely [ 166,226,236]. The dependence of radiation-induced interface trap density on the Al gate thickness in MOS structures suggests that bond strain assists in the creation and migration of trap-related defects [236a]. The model speculations for the interpretation of interface states are more or less also valid for the irradiation effects [226,237]. I. Hot Carrier Injection

In short channel MOSFETs, a high electricfield(and, thus, charge carrier heating) occurs near the drain electrode [238-244]. The device characteris­ tics degrade because charge trapping occurs in the oxide and interface traps are generated. The carrier injection is usually visible in a gate current. The absence of a gate current, however, does not eliminate trapping. Especially in the case of hot holes, all the carriers may be trapped in the oxide [238]. Injected hot carriers can also return to a low-field region (e.g., the drain in the substrate). The hot carrier instability of devices stimulated much research on carrier injection and trapping in the oxide. Avalanche injection is usually employed in the study. Traps in the oxide may be related to implantation damage [250], sodium [251], e-beam irradiation [252], or γ irradiation [237]. The origin of the interface trap generation is still a controversy. It may be related to hydrogen or water in the oxide [249-253]. J. Bulk States in Silicon

Deep-level transient spectroscopy frequently reveals bulk trap centers in MOS structures, especially after ion implantation [9,119,121,133], because DLTS is sensitive to the total number of bulk states in the space charge region. Bulk levels are identified by their sharp and discrete structure. The DLTS signal due to bulk states decreases when the width of the space charge region is reduced [9]. An intrinsic bulk level at Ec — 0.49 eV (ση = 2.9 X IO"16 cm2) associated with the Si-Si0 2 interface is frequently observed. This level which appears after high-temperature annealing of the MOS structure is remarkable be­ cause it is also observed in bulk silicon containing swirls [254,255]. It may be a level of interstitial silicon that is expected to be generated during oxide growth [49,61,185]. The generation of bulk levels by postoxidation annealing has been studied by Hofmann and Schulz [ 184]. Several bulk deep levels have been observed

66

S. A. Schwarz and M. J. Schulz

\D

1016

Δ

\ \ \

m

Έ

o ■—

>H

u10

\

15

Q

\

\a \ \

-

Ï7)


0.725 the surface would be accumulated «-type (see Fig. 8), and VB should increase monotonically with decreasing Xln below Xln = 0.725. The Al^Ga^^As system appears to obey the common anion rule for x < 0.3, but not at larger X^ as the/and L conduction band minima become more important. Okamoto et al [30] studied Al Schottky barriers on Al^Ga^^ As. Their entire structures were grown by MBE, so they had atomically clean interfaces. They found some dependence of the barrier height on the surface Ga : As ratio before depositing the Al. Excess As at the GaAs-Al interface probably allows a thin layer of AlAs (or at least Al^Ga^^As with high XA1) to form at the metal-semiconductor interface. Note the good agreement between the data of Okamoto et al and the unified defect model for GaAs. The Au Schottky barriers on chemically etched «-type Al^Ga^^As were measured by Best [31]. He obtained consistently larger barriers with Au than Okamoto et al with Al, in agreement with the photoemission measurements of the unified defect model [20] and as expected from conventional device measurements. Finally, for comparison we have plotted the well-known data of Mead et al for the three binary semiconduc­ tors [32]. Given the difficulties of the calculations and experiments, the agreement is good, and some trends may be noted. The pinning position is invariant with Xln in In^Ga^^As within —0.2 eV, in agreement with the common anion rule. This explains the ease of fabrication of ohmic contacts to «-InAs.

96

William E. Spicer and Stephen J. Eglash

In fact, Woodall et al have graded fr^Ga^As layers on «-type GaAs to lower the barrier and make an improved ohmic contact [33]. Consistent with this, Schottky barriers become increasingly leaky with increasing In concen­ tration in In^Ga^^As. These Schottky barriers may be increased by using interfacial doped layers (see Section VI, as well as Chen et al [34]) or by using other techniques [35]. The MOS and MIS structures are expected and observed to be more difficult as the states go deeper in the band gap in the series: InAs —» GaAs —> AlAs. However, this issue is subtle. Although levels near midgap are clearly deleterious to MOS and MIS devices, we must have low interface state densities throughout the entire band gap if we are to make a good MOS or MIS structure. VI. SCIENTIFICALLY ENGINEERED SCHOTTKY BARRIER HEIGHTS

As discussed earlier in this chapter, the Schottky barrier height on GaAs is surprisingly insensitive to the choice of metal. The unified defect model has explained that this is due to a high density of electronic states at a few discrete energies at the metal-semiconductor interface. This high density of states has created numerous device problems, most notably poor ohmic contacts to GaAs (see Section VII) and poor Schottky barriers to «-type InP and «-type InAs. Thus, we were led to modify this Fermi level pinning by intro­ ducing a high density of donors or acceptors in the semiconductor near the interface [36,37]. The structures used for decreased and increased barrier heights are shown in Fig. 9. This approach has allowed us to controllably modify the barrier height from near zero (that is, ohmic; see also Section VII) to near band gap. Modification of the barrier height does not result solely from compensation of interface states, but also from band bending in the highly doped layers (see Fig. 9). In fact, barrier height modification through the use of interfacial doped layers had been tried previously [34,37,38] and has been tried since [39], but our work was the first to develop out of an atomic understanding of interface states, as well as thefirstto utilize MBE to grow the semiconductor epitaxial layers and the metal Schottky contact. The details of the growth procedures have been presented elsewhere [36,40]. The use of MBE to prepare atomically clean Al-GaAs contacts allowed us to prepare nearly ideal interfaces. Transmission electron microscopy (TEM) lattice imaging [41] revealed that these interfaces were free of oxides and other contamination and that the Al metal layers had grown epitaxially. A lattice image of this interface and the corresponding crystal structure are shown in Figs. 10 and 11. The thick «-GaAs was Si-doped to n = 5 X 1016/cm3. Interfacial layers were p+ Be-doped (NA = 1 X 1018-6 X 1019/cm3; tp+ = 50-360 Â) for in-

3. Unified Defect Model and GaAs Integrated Circuits

n+ GaAs Al

97

n GaAs

F^i

tn+.

ITI (a) Fig. 9. Band diagrams and charge densities in the device structures used for decreased and increased barrier heights. Donors and acceptors in the thin n+ and/?"1" regions may compensate interface states and modify V0, as well as simply modifying the band bending, (a) Al- «+-GaAs«-GaAs structure. Electrons tunnel through that portion of the potential barrier in the n+ region. Thus, measured barrier height VB is reduced from the unmodified barrier height VQ. (b) Al-p+GaAs-«-GaAs structure. The potential barrier is increased by negative space charge in the depleted p+ layer, and the barrier height increases to VB from V0.

creased barrier heights, and n+ Si-doped (ΝΌ = 5 X 1018/cm3; tn+ = 50-150 Â) for decreased barrier heights. Following the growth of the GaAs epitaxial layers, the substrate was cooled in the UHV environment of the MBE sys­ tem. Aluminum was then evaporated onto the clean GaAs surface in the MBE system and subsequently patterned into dots using standard photoli­ thography techniques. The semiconductor ohmic contact was made through the «+-GaAs substrate. Referring to Fig. 9, note that the high dopant densities of the interfacial layers produce a large second derivative of the electrostatic potential. (This follows trivially, of course, from Poisson's equation.) Increasing either the dopant density or the thickness of the interfacial layers increases the change in barrier height. In the extreme, a thick and highly doped n+ layer will give an ohmic contact, and thick p+ layers result in a p- n junction. For proper choices of interfacial layer thickness and doping density, however, engi­ neered Schottky barriers behave as majority carrier rectifying contacts with a tailored barrier height. Charge neutrality must always be maintained at the (thermal equilibrium) interface, so we have ÖM-S+ß,„ +0SCR = O, -tn+/p+

(2)

98

William E. Spicer and Stephen J. Eglash

Fig. 10. Transmission electron microscope lattice image of the Al( 110)-GaAs( 100) inter­ face. This structure was prepared by depositing Al on a GaAs(lOO) surface below 80 °C in the ultra-high-vacuum environment of an MBE system. (From Ponce and Eglash [41].)

where ß M -s *s the charge at the metal-semiconductor interface, Qtn+/p+ the net charge in the depleted interfacial layer, and ß SCR the charge in the space charge region of the «-type GaAs. Parameter QM_S is the sum of the charge in semiconductor interface states and any metal surface charge that may exist. At this time there is no known method of separating QM-s into these two components. The barrier heights have been measured by / - V, C- V, and temperaturedependent I-V techniques. These results have been reported previously [36,40] and will only be reviewed briefly here. Some of our barrier heights as determined by room temperature / - F measurements are shown in Fig. 12. These diodes are well behaved; the log(/)- V curves were fit by the ideal diode equation from 10"10 to 1.0 A/cm2 of forward current, at which point the series resistance became significant. The diode ideality factor n varied slightly (as predicted) due to the bias dependence of the barrier height which results from the interfacial layer but was always near n = 1.1. Devices in which the Al gate was deposited directly on «-GaAs with no interfacial layer

3. Unified Defect Model and GaAs Integrated Circuits

99

3.84 Â Fig. 11. Ball-and-stick model of the interface imaged in Fig. 10. Analysis of the lattice structure and diffraction pattern (not shown) of the image in Fig. 10 yielded this orientation. We are not sensitive to small amounts of Al in the GaAs lattice or very small amounts of Ga or As in Al.

100

William E. Spicer and Stephen J. Eglash n

1

r

1.4 1.2

>_ 1-0 I o w 0.8

£θ.6 < 00

0.4 0.2 DECREASED BARRIER HEIGHTS J 150 n

+

L 100

50

o0

LAYER THICKNESS [Â] N D= 5 * 1 0

18

cm"

3

INCREASED BARRIER HEIGHTS 100

200

300

400

+

p LAYER THICKNESS [Â] N A=1 x10

18

cm"

3

Fig. 12. Observed and predicted dependence of the barrier height on interfacial layer thick­ ness and doping for engineered Schottky barriers. Note the systematic dependence of barrier height on the interfacial layer, the ability to vary the barrier from ohmic to nearly band gap, and the good agreement with theory.

exhibited an ideality factor n = 1.04, in agreement with other workers [42] and indicating the potential of this technique for producing excellent diodes. The C - F characteristics were also well behaved, giving linear 1/C2 versus V curves that had voltage-axis intercepts in agreement with our calculations [40]. Temperature-dependent / - V measurements confirmed the above conclusions. The applications of this technique of barrier height modification to dis­ crete and integrated III-V semiconductor devices are significant. Increased barrier height devices should facilitate MESFETs on «-type In0 53Gao 47As and InP [34], in which small Schottky barriers have previously forced people to use JFET or MISFET structures. Larger barriers should improve noise margins even on «-channel GaAs FETs, especially in enhancement mode devices. Increased barrier diodes have been used as solar cells and photodiodes [43,44] as well. Similarly tailored barrier heights may be obtained with so-called camel or planar doped barrier diodes [44a,b]. In a related study, these increased barrier diodes have allowed us to ob­ serve a IkT current at low voltages that we believe is a trap-assisted deple­ tion-region recombination current present in all «-GaAs Schottky diodes and FETs [36]. Experiments designed to determine whether this is a surface or bulk recombination current are under way. Increased barrier devices,

3. Unified Defect Model and GaAs Integrated Circuits

101

therefore, are proving useful in studies of surface recombination and carrier transport at rectifying contacts in general. Similarly, reduced barrier devices are useful in studies of ohmic contact phenomenon, especially tunneling. They also show promise as microwave mixers and detectors. In one detector application a zero-bias small-signal rectifier is desired for good thermal stability [45]. This is accomplished by a diode having a barrier height of only a couple of tenths of a volt. However, good rectification is also desired, thus the barrier cannot be too small and the diode ideality factor n should be as near to 1.0 as possible. The good perform­ ance and reproducibility of engineered Schottky barriers cause us to be very encouraged about this application. We expect the extension of this technique to metals other than Al, and to p-type GaAs and other n- or p-type semiconductors to be straightforward. As the barrier height in these structures is relatively insensitive to the interfacial chemistry, we anticipate these diodes will have good thermal stability at elevated temperatures.

VII. OHMIC CONTACTS

By definition, good ohmic contacts have small resistances and inject (or extract) few minority carriers. By a small resistance, we mean that the voltage drop across the contact is negligible compared with the rest of the device. There is a large amount of literature on ohmic contact technology reviewed quite thoroughly elsewhere [46-49]. Here, we will take a more fundamental approach and discuss some insights into ohmic contacts that may be gleaned from surface and interface studies. There are various physical mechanisms that may be responsible for pro­ ducing ohmic contacts. Which mechanisms dominate will be determined by the particular circumstances. The conventional view considers thermionic emission over a potential barrier and quantum mechanical tunneling through a potential barrier. The metal-semiconductor interface is taken to be uniform and smooth. Under these conditions, two limiting cases have been investigated [50,51]. For low doping thermionic emission dominates and for the contact resistance Rc we have Rc ~ egVB/kT,

thermionic emission.

(3)

In heavily doped material, tunneling (field emission) dominates and Rc ~ eVB/E°°, field emission, £00 = iM^ D /™*€ s ] 1/2 ,

.

102

William E. Spicer and Stephen J. Eglash

e"—

U I

Metal Semiconductor Metal Semiconductor Fig. 13. Ohmic metal-semiconductor contacts, (a) If there is no barrier (or only a barrier height ~ kT) the contact will be ohmic—most likely on «-type InP and In As. (b) Even if there is an appreciable barrier, it may be made transparent by sufficiently heavy doping. Electrons may then pass through the barrier by quantum-mechanical tunneling—the applicable case for GaAs and AlAs.

where 6S is the semiconductor permittivity. Between these limits thermally assisted tunneling (thermionic field emission) occurs. Note that in lightly doped material the contact resistance increases rapidly with increasing bar­ rier height, and that in heavily doped material, the contact resistance de­ creases with increasing doping. The best ohmic contacts, therefore, will be those in which the barrier height is small (to facilitate thermionic emission), the barrier width is narrow (to enhance tunneling), or both (Fig. 13). The above analysis assumes a smooth and planar metal-semiconductor interface. Some workers have pointed out that many practical ohmic con­ tacts may be highly spatially nonuniform. Using transmission electron mi­ croscopy they have observed nonuniform contacts and postulated that large electric fields at the nonuniformities may result in enhanced tunneling. If this occurs, ohmic behavior would result. Here we will consider planar smooth contacts, and discuss what the impli­ cations of the unified defect model are for ohmic contacts to the III-Vs. Recall that in GaAs there is a high density of interface states near midgap, and that approximately the same barrier height is observed on «-type GaAs, regardless of the metal used [11,50]. This strongly suggests that in ohmic contacts to GaAs the Fermi level is pinned near midgap as well. In this case, there would be a significant Schottky barrier present at «-GaAs ohmic con­ tacts, and the GaAs must be heavily doped if tunneling through the barrier is to result in a good ohmic contact. In practice, «+-GaAs layers are fabricated at the metal-«-GaAs interfaces to enhance tunneling. Presently, this n+GaAs layer may either be produced by ion implantation, diffusion, or epi­ taxial growth prior to forming the metal contact. It may also be formed from some element in the metal layer and be produced by a heat treatment after the metal contact has been deposited.

3. Unified Defect Model and GaAs Integrated Circuits

103

Although the effects of oxygen are not well understood [52], it is likely that forming the metal - semiconductor interface in as clean a way as possible will help because GaAs oxides are probably insulators and would present an added barrier to tunneling. Although this interfacial oxide may be dissolved during alloying, at least in nonalloyed ohmic contacts the best contacts will probably minimize oxygen contamination, perhaps by growing the entire structure in a UHV environment such as an MBE system. However, there is a technique for removing the barrier between a metal and GaAs, as mentiond in Section V. To see this, refer to Fig. 8 showing the Fermi level pinning position in In^Ga^^As alloys. Note that as we move from GaAs towards In As, the high density of interface states moves towards and then into the conduction band. This agrees with what is observed in practice; ohmic contacts to ft-InAs are easy, and Schottky barriers difficult. This fact was exploited by Woodall et al [33] who grew a graded nIn^Ga^^As layer on «-GaAs to form an ohmic contact. It is important to not form an abrupt InAs-GaAs interface, as the resulting conduction band discontinuity would produce an electron barrier. As mentioned earlier, we will form good ohmic contacts when the barrier is small or the doping is high. In collaboration with Hewlett-Packard Labora­ tories, we have investigated the possibility of growing «+-GaAs layers by MBE for ohmic contacts to «-GaAs. Silicon is the donor most commonly used in MBE, but there are difficulties in doping greater than ~ 5 X 1018/cm3 with Si. However, Sn doping allows for concentrations to 1 - 2 X 1019/cm3 [53]. In preliminary experiments, we grew n+ Sn-doped GaAs on moderately Si-doped (ΝΌ = 5 X 1016/cm3) GaAs completely by MBE. We then removed the wafer from the MBE system (exposing the «+-GaAs to air) and evapo­ rated a layered structure of Au and other metals. This metal structure can be alloyed with the GaAs (sintered) to produce ohmic contacts,* however we were interested in determining the quality of the ohmic contact due only to our n+ doping. Thus, we did not alloy these contacts. This followed a strategy similar to that which had been used to make modified Schottky barrier heights (Section VI), but here we used an n+ interfacial layer to facilitate tunneling. This is a so-called nonalloyed ohmic contact. Our results were quite encouraging. By using a transmission line technique, we measured specific contact resistances rc ^ 10~6 ohm cm2, comparable to the best ever reported. Even better results were obtained by Stall et al [54] who grew n+-Gt on «-GaAs by MBE, and achieved contact resistances below 1 X 10~7 ohm cm2. Our contacts were fabricated using ex situ metallization. As men­ tioned earlier, oxygen at the metal-semiconductor interface is likely to * Ohmic behavior in alloyed contacts of this type arises from heavy doping in the semicon­ ductor by one of the metal constituents (e.g., Sn or Ge on «-type GaAs), from the creation of spikes at the metal - semiconductor interface where large electricfieldsmay enhance tunneling, or from both.

104

William E. Spicer and Stephen J. Eglash

degrade the performance of nonalloyed ohmic contacts. We are presently repeating this experiment by depositing the metal layers in the MBE system to form atomically clean interfaces. VIII. CHEMISTRY AND INTERMIXING AT III - V SEMICONDUCTOR-METAL INTERFACES A. Introduction

Important chemical reactions and intermixing at metal-semiconductor interfaces often occur. A variety of metal - semiconductor systems have been studied, and a wide range of interfacial reactions observed. Here the power of surface-sensitive analytical techniques is dramatically demonstrated; reac­ tions and intermixing can be observed as they are occurring. These processes have surprisingly little effect on the type of defect levels formed; however, they may have strong effects on the relative numbers of different defects. For example, InP clearly has more than one type of defect, while GaAs may well have only one physical defect that may act as a donor (at lower energy) and an acceptor (at higher energy). We have recently taken an important step towards characterizing and systematizing these interfacial reactions. We have found, as have others, that the vast store of information on the thermodynamics of bulk reactions is sometimes of limited usefulness when applied to surfaces and interfaces. Why should bulk thermodynamics break down at surfaces and interfaces? Basically, there is no reason to expect it to apply directly. Many of the characteristics of bulk systems—infinite and isotropie with negligible boundaries—simply are not realized at surfaces and interfaces. Further­ more, thermodynamic data are derived from systems in thermal equilib­ rium, and thus kinetics are not considered. In fact, kinetics control most interfacial reactions.* As an example, the equilibrium or thermodynamically favored phase between Si and oxygen is Si0 2 . The oxidation of Si to form Si0 2 (a process that is in large part responsible for the success of the Si IC industry), of course, proceeds at a finite rate. This is due to kinetic limitations on the oxidation reaction. We have found it useful to systematize reactions at surfaces and interfaces in terms of their correspondence with or divergence from comparable bulk systems. The room temperature reactions of metals on semiconductors are also often controlled by kinetics rather than bulk thermodynamics. Even a reac­ tion that is thermodynamically favored may not proceed due to an activa* Bulk thermodynamics do not break down at interfaces under all conditions. At sufficiently elevated temperatures reactions often proceed according to thermodynamics; liquid phase epitaxy is an example.

3. Unified Defect Model and GaAs Integrated Circuits

105

tion energy barrier that is large compared to the available thermal energy. In the simplest case we have Rate oc e-EJkT9

(5)

and the rate becomes vanishingly small (that is, the reaction does not pro­ ceed) if Ea is much larger than kT. Most chemical reactions require some movement of the reacting atoms. Then, Ea can often be visualized as the energy required for this atomic motion.* In the Si-Si0 2 case, Ea is in­ fluenced by the movement of oxygen to the Si - Si0 2 interface. In the case of Al reacting with GaAs to form AlAs and Ga (to be discussed later), the activation energy is that required for the movement of Ga atoms out of the GaAs lattice and the movement of Al atoms into these sites. Note that as the (O + Si) or the (Al + GaAs) reactions proceed, reacted layers of Si0 2 or AlAs (respectively) form on the surface. The effective activation energy will in­ crease as the thickness of this reacted layer increases, because the reacted layer presents a diffusion barrier to the reacting species. It is useful to divide GaAs interfacial reactions into two different classes: reactions that are not predicted by bulk thermodynamics, but occur due to the particular character of the interface and reactions that are favored by bulk thermodynamics. Reactions of this first class may be limited to only a monolayer of reacted species at the interface, and because of their interfacial nature may have no driving force to extend over more than a monolayer. Even in cases where true bulk reactions can occur, interfacial reactions can be critical in determining the activation energy. Interactions at the AuGaAs interface (to be discussed later) appear to be strongly affected by interfacial reactions. An interesting example that does not fit easily into either class is Ag on GaAs. Of all the metals studied on GaAs to date, Ag is the only one that has almost no reaction of any type with GaAs. B. Reactions Unique to Interfaces

We will first consider two reactions that occur only at interfaces and are not predicted by bulk thermodynamics. These reactions give special insights into interactions which are unique to interfaces. 1. Cesium on GaAs

The Cs bond to GaAs is due to the formation of an electrostatic dipole at the interface [20,55]. The Cs atom is highly polarized so that the Cs valence electron has appreciable probability of being found in the GaAs. As the Cs concentration on GaAs increases from submonolayer to monolayer cover* This is a somewhat unconventional definition of activation energy, but this intuitive and operational definition will be useful in the following discussion.

106

William E. Spicer and Stephen J. Eglash

ages, the Cs-Cs dipole interactions reduce the magnitude of the Cs atomic dipole and the Cs binding energy [56] until the binding energy approaches that of Cs on bulk Cs at approximately one monolayer coverage. Because of the interactions of the Cs dipoles, the electron affinity of this system de­ creases most rapidly with Cs coverage at the lowest coverages and less rapidly as the coverage increases. By one monolayer, the electron affinity has de­ creased by about 3 eV. In fact, the binding energy of isolated Cs atoms on GaAs is over 60 kcal/mole, about three times that of Cs on bulk Cs. For coverages over one monolayer there is no additional dipole, and the binding energy is just that of Cs on bulk Cs. 2. Antimony on GaAs

When Sb is deposited on GaAs, a monolayer of Sb bonds covalently to both Ga and As atoms at the interface. Antimony-antimony bonds are also formed in such a way that for a monolayer of Sb there are no dangling bonds at the surface (as there were at the original GaAs surface) [10,57,58]. As a result, this is a relatively inert structure and reacts with oxygen much less rapidly than does pure Sb. C. Reactions Predicted by Bulk Thermodynamics

Let us now turn to the other class of interfacial reactions. These are reactions predicted (or favored) by bulk thermodynamics. Even these reac­ tions, of course, are controlled by activation energy barriers. We will con­ sider three examples of this class: replacement reactions, formation of new bulk compounds, and metallic alloy formation. 1. Replacement Reactions

In a replacement reaction the foreign atom substitutes for one of the constituents of the semiconductor lattice. Consider the example of Al metal on GaAs semiconductor GaAs + Al -* AlAs + Ga.

(6)

At room temperature this does not proceed sufficiently to allow it to be observed by LEED [59]; however, it has been detected by the surface sensi­ tive photoemission methods described in Section II [57,58,60]. This indi­ cates a strong activation energy control at room temperature. At tempera­ tures above about 400 °C, the reaction proceeds to the extent that it can be seen by LEED [61], indicating that it has taken place in a uniform manner. The LEED data indicate that Ga atoms remain in the top layer of the GaAs lattice, with Al atoms replacing Ga atoms in the second and possibly deeper layers. This can be understood in terms of minimizing the interfacial energy.

3. Unified Defect Model and GaAs Integrated Circuits

107

2. Formation of New Bulk Compounds

The formation of bulk compounds with a new lattice may occur at the metal-semiconductor interface. We have observed the formation of arse­ nides at Cu and transition metal interfaces to GaAs. These arsenides are analogous to the suicides that are so important to IC technology, except that excess Ga remains following the arsenide formation and must be accommo­ dated. Nickel is an example Ni + xGaAs -> NiAsx + xGa.

(7)

Photoemission spectra taken during Ni deposition on GaAs are shown in Fig. 14 [62]. Here a new metallic compound appears to be formed at the interface. Johannesson has reported evidence from Auger spectroscopy mea-

KINETIC ENERGY (eV) Fig. 14. Soft x-ray photoemission spectra of (a) Ga 3d (hv = 80 eV) and (b) As 3d (h v = 100 eV) core levels as a function of Ni coverage on the «-type GaAs(llO) surface. Photon energies were chosen to yield maximum surface sensitivity. This cleave was partially pinned before metal deposition, so little movement of the core levels due to band bending is observed. At higher coverages, note the strong shift of the Ga 3d level towards higher kinetic energy (lower binding energy), characteristic of free (metallic) Ga. The As 3d level shifts slightly towards lower kinetic energy (higher binding energy), suggestive of the formation of Ni-As bonds. (From Williams et al [62].)

108

William E. Spicer and Stephen J. Eglash

surements for the formation of Ni2GaAs [63]. More work needs to be done to clarify this. Arsenide formation may have great technological importance for future III-V IC fabrication. 3. Metallic Alloy Formation

In some cases a metallic alloy is formed between the metal overlayer and the metallic component (Ga) of the GaAs lattice. A very surprising reaction is that of Au with GaAs. From the atomic studies described in Section II, it is clear that Au attacks the GaAs lattice and considerable amounts of Ga and As intermix with Au near the interface (Figs. 15 and 16). Comparing the effects of Ni and Au on GaAs, note the stronger As 3d shifts in Fig. 14, and the stronger Ga 3d shifts in Fig. 15, providing information on the different chemistries of Ni and Au on GaAs. It seems most likely that this reaction for Au on GaAs is driven by the formation of a Au-Ga alloy; however the large

I

52

■

■

■

I

54

■

■

■

I

■ ; l

i

I

!

56 74 KINETIC ENERGY (eV)

i

i

L

76

Fig. 15. Soft x-ray photoemission spectra of the As 3d (left) and Ga 3d (right) core levels on «-type GaAs( 110) as function of Au coverage (hv = 100 eV). The photon energy was chosen to yield maximum surface sensitivity. The initial rapid shift in core levels is due to band bending. Note that the As 3d level is relatively unchanged at higher Au coverages, while the Ga 3d level shifts continuously towards higher kinetic energies (lower binding energies). This may be due to the formation of a metallic Au-Ga (eutectic) alloy. (From Petro et al. [64].)

109

3. Unified Defect Model and GaAs Integrated Circuits 1.43 BAND BENDING REGION 1.0 LL

I

INTERMIXING REGION

LU

>

LU —I

0.5

LU

Q:

o o

6

JL 8

10

-V

20

80

AU COVERAGE [Θ] (ML)

Fig. 16. Positions of the peaks from Fig. 15 plotted relative to their initial positions. Initial position is defined to be 1.43 eV because the initial position of the Fermi level was 1.43 eV above the valence band maximum. Note that the As 3d (D) is relatively constant after a few monolayers of Au, while the Ga 3d (O) continues to move towards higher kinetic energy (lower binding energy). Data may be explained by the formation of a metallic Au-Ga alloy. (From Petroso/. [64].)

atomic electron affinity of Au may be playing a role by attracting electrons from the GaAs surface and weakening the GaAs bonds, allowing Ga and As atoms to move into the Au [20]. IX. OTHER APPLICATIONS TO VLSI DEVICES A. Introduction

Surfaces and interfaces will have increasing impacts on devices as dimen­ sions shrink and speeds increase. As one example, smaller and higher-speed FETs have shallower channels and, hence, are more susceptible to mechani­ cal strain induced by the gate or the neighboring dielectric. This strain may cause crystallographic defects in the channel that would degrade device performance and reliability. At the time of this writing, present generation GaAs ICs consist of MESFETs fabricated by ion implantation into a semi-insulating substrate. A device structure typical of this technology is shown in Fig. 17. In this device

110

William E. Spicer and Stephen J. Eglash

DIELECTRIC

^m

-DEPLETION REGION DRAIN

-OHMIC CONTACT

^M—f/m^^^m^. rc SEMI-INSULATING GaAs

REGIONS

Fig. 17. Cross section of a conventional ion implanted MESFET. Source-drain contacts should be high quality ohmic contacts, while the gate should be a good Schottky barrier. Dielectric or passivation layers should be resistive and stable.

we can identify several critical bulk and interfacial materials issues. The bulk issues include the nature of semi-insulating GaAs, the effects of ion implan­ tation and subsequent annealing, and transport in the channel. Here, as throughout this chapter, we emphasize the critical role of surfaces and inter­ faces. The most critical interface in Fig. 17 is the gate-channel interface, because it is through variations in gate bias that we control the channel depletion width and achieve gain. This contact should be rectifying and stable. The source-drain contacts inject and extract large electron currents in this device. They should be ohmic and have as small resistances as possi­ ble. The dielectric or passivating layer is critical as well. It should allow no leakage between the gate and the source or drain. Furthermore, the electro­ static potential at the GaAs-dielectric interface should be constant in time. The unified defect model is one body of work that sheds light on these issues. In this section we touch on some of these and other specific applications of the unified defect model to III-V devices and integrated circuits. B. Success of Schottky Gates on GaAs and MOS on InP

It is now well known that Schottky gates are good on GaAs and oxidesemiconductor interfaces (MOS structures) are poor, whereas on «-type InP it is the other way around: Metal - semiconductor contacts have barriers that are too small and, thus, are leaky, while MOS structures perform fairly well. These facts, though, were learned only after a long and expensive process of trial and error, and much effort was expended unsuccessfully trying to over­ come these facts in an empirical way. In retrospect, we can see that this approach was inefficient. Often, as is the case here, a basic understanding of phenomena allows for scientific—as opposed to empirical—engineering. In this case, the understanding can come from the unified defect model.

3. Unified Defect Model and GaAs Integrated Circuits

111

The experimental data leading to the unified defect model indicated that both Schottky barrier and oxide interface states formation were unified in that they were determined by the same process: the formation of electronic energy levels (interface states) at specific energies in the band gap near the semiconductor surface. In GaAs these levels are near midgap, while in InP they are near the CBM (see Section IV). This produces the observed differ­ ences in Schottky barrier heights between GaAs and InP. In GaAs the interfacial position of the Fermi level is near midgap and the barrier height is several tenths of a volt. In InP the Fermi level is in the upper third of the band gap, and the barrier on «-type InP is only a few tenths of a volt.* The use of interfacial doped layers for increasing Schottky barrier heights was discussed in Section VI. This technique could be used to form a pseudo-MESFET on «-InP. Also, a JFET could be used. The success or failure of MOS structures is more subtle. In a MOSFET we want to modulate the semiconductor charge by varying the gate voltage. As the semiconductor charge is modulated from accumulation to depletion to inversion, the Fermi level position at the metal-semiconductor interface must move throughout the entire band gap. For this to happen there must not be a high density of interface states, or they will have to be charged, too, leading to poor transistor behavior and destructively high electric fields across the oxide. In fact, the interface state density is so high in GaAs that it is impossible to completely fill or empty them, and the Fermi level stays pinned near midgap. Insulator-semiconductor interface states in MOS structures may also cause hysteresis and noise in the transconductance and the gate capacitance. Interface states may also contribute to the well-known 1 //noise. On /?-type InP, since the Fermi level is already near the conduction band, we have the possibility of fabricating inversion-mode MOSFETs. In this device the gate would be biased positively to attract electrons in the InP channel. C. Metal-Semiconductor Interfacial Chemistry and Self-Aligned Gates

Figure 17 indicates a conventional MESFET. Improved MESFETs utilize the gate metallization to mask and, hence, define the source and drain contact implants. This is the so-called self-aligned gate technology. Damage * In InP there is an added complication due to a donor state probably lying above an accepter state. In this case, the states compensate each other and the position of the Fermi level is influenced by the relative densities of the states. Fermi level behavior in InP and other semicon­ ductors has been systematized in terms of chemical and thermodynamic factors by Brillson [65].

112

William E. Spicer and Stephen J. Eglash

resulting from the source and drain implants must be annealed out at high temperature. Since the gate metallization is already in place, it must with­ stand these high temperatures without degradation of its rectifying proper­ ties. It is this problem, in part, that has stimulated us to begin studying the chemistry of semiconductor interfaces, especially at elevated temperatures. In a preliminary series of experiments, Newman et al of our group have begun making / - Fand C - F measurements on diodes fabricated by a vari­ ety of metal evaporations on cleaved GaAs surfaces [66]. Of course, devices on cleavage surfaces are not technologically useful, but as these surfaces are atomically clean and well understood they provide a useful vehicle for fun­ damental studies. Newman et al have looked at the barrier heights of Al and Au Schottky barriers to «-type GaAs as a function of annealing temperature. The Al barriers vary slightly around 0.8 eV during anneals up to 500 °C. These results suggest that changes occurring during low-temperature anneals tend to saturate. Therefore, moderate anneals may be used to improve the stability of Al-GaAs contacts. With Au, very different behavior is observed. Following deposition and after anneals to very low temperatures, the AuGaAs barrier is relatively constant around 0.9 eV. Annealing to 500°C produces ohmic behavior, which is removed by mesa etching the diodes to remove the GaAs around the periphery of the metal dots. We are working to understand this behavior and explore its implications for ohmic and rectify­ ing contacts. We mention here that this transition from rectifying to ohmic behavior is observed to occur at approximately the Au-Ga eutectic temper­ ature, as mentioned briefly in Subsection VIII.C. D. Carrier Recombination at Bulk Deep Levels

The perfect semiconductor has no electronic states in the band gap. How­ ever, as we have discussed throughout this chapter, the situation is dramati­ cally different at III-V semiconductor surfaces and interfaces. Crystallographic defects such as dislocations and grain boundaries appear to induce electronic states at the same energies as we observe at surfaces and interfaces, and the same types of defects may even be responsible in both cases. For example, midgap states have been detected by deep-level transient spectroscopy (DLTS) at GaAs grain boundaries [67]. States near midgap are usually effective for nonradiative recombination of excess electrons and holes. In nonradiati ve recombination the energy of the recombining electron-hole pair is given off as phonons (lattice vibrations), that is, heat. This energy may drive further defect formation. Aspnes [68] has recently reviewed recombi­ nation and carrier lifetimes in the III - V semiconductors and interpreted the data within the context of the unified defect model.

3. Unified Defect Model and GaAs Integrated Circuits

113

If dislocations act similarly to surfaces in inducing electronic levels at nearly the same energies demonstrated for surfaces and interfaces, then the phenomenon of dark-line defects in lasers and light emitting diodes (LEDs) can be understood. Dark-line defects are crystallographic defects within a laser or LED that do not radiate. Dark-line defects are observed in GaAs LEDs, and AlGaAs-GaAs double heterostructure lasers, but not in InP and InGaAsP-InP devices. The crystallographic defects are present in both cases, but only appear as dark lines in the GaAs-based materials. Recall that the surface and interface states in GaAs are near midgap, whereas in InP they are near the conduction band minimum. States near midgap are more effec­ tive nonradiative recombination centers than states near the band edges. Therefore, if bulk defects in GaAs- and InP-based compounds have elec­ tronic states at the same energies as surface and interface states, then the occurrence of dark-line defects in GaAs but not InP can be explained. In fact, Daw and Smith [13-15] found in their calculations of anion vacancies that the defect energies shift only slightly in moving the defect from the semicon­ ductor surface to deeper layers. This same phenomenon of recombination at defect states can explain the much higher surface recombination velocities observed in GaAs compared with InP [68]. E. Deep Levels at Surfaces and Interfaces

The MESFET indicated in Fig. 17 required no semiconductor epitaxial growth. The channel and contact regions were fabricated by ion implanta­ tion directly into a semi-insulating substrate. Other more advanced devices require semiconductor epitaxial growth on a substrate. Deep levels may be present at these substrate-epitaxial layer interfaces, and they are certainly present at the semiconductor surface (for example, between the gate and the source and drain in Fig. 17), whether it is passivated with a dielectric or not. States at the substrate-epitaxial layer interface produce a depletion region and modify the electrostatic potential. Changes in this potential as the states change occupancy could produce a phenomenon known as backgating. Similarly, states at the surface produce a depleted surface and an electric field extending into the channel. Hot electrons traversing the channel in a GaAs FET may be scattered over this barrier and into the interface states, possibly effecting the threshold of the device. The interface between the passivation layer and the GaAs may contribute to leakage currents. Thermodynamic data suggests that Ga may reduce As oxides, leaving free As. Excess As or Ga, if present at the GaAs-dielectric interface, may be partially conductive. The resulting leakage currents could supply charges that would change the operating points of neighboring de-

114

William E. Spicer and Stephen J. Eglash

vices, a process known as sidegating. The interface at the corner of the gate that is between the gate metal, semiconductor, and passivating dielectric is especially critical because of the high electric fields that are present there. Many of these things are just coming under investigation. We anticipate that as they are understood, it will become possible to control and exploit them. X. SUMMARY AND CONCLUSIONS

The works described in this chapter provide insights into some phenom­ ena taking place in III - V devices and integrated circuits. Surfaces and inter­ faces have a critical impact on VLSI electronics. In fact, the processing and operation (and failure) of many electronic and electro-optic devices depend critically upon surface and interface effects. This chapter has focused on one significant development in a continuing and far reaching investigation of semiconductor surfaces and interfaces: the unified defect model for Schottky barrier and oxide interface states on the III-V semiconductors. This model has widespread implications of relevance to the fabrication and operation of III - V devices and integrated circuits, and we have addressed several of these here. The semiconductor materials and device communities are just beginning to appreciate the importance of these issues. The surface and interface com­ munity is attacking these problems with increased vigor. This chapter and this entire volume are an indication of this increasing interest and a progress report of some results to date. Perhaps more importantly, in this publication we have attempted to relate some fundamental knowledge of surfaces and interfaces to practical problems. This should be looked upon as an early and sometimes tentative attempt at what we consider a very important process. If this process is carried out well, it can contribute strongly to the optimization of III-V semiconductor technology. ACKNOWLEDGMENTS This work was supported by DARPA and ONR. The joint effort utilizing MBE (see especially Section VI) was made possible through the generous cooperation of Hewlett-Packard Laborato­ ries. Useful discussions with T. McGill and H. Wieder are gratefully acknowledged. One of us (SJE) would like to thank D. M. Collins, R. A. Burmeister, and many others at Hewlett-Packard Laboratories, Palo Alto, California, for useful discussions and significant technical support. We would like to express our gratitude to R. S. Bauer and N. G. Einspruch for their encouragement

3. Unified Defect Model and GaAs Integrated Circuits

115

in all phases of writing this chapter. Our thanks to C. Y. Su and C. E. McCants for a critical reading of the manuscript. All errors and omissions, of course, are the responsibility of the authors. W. E. Spicer holds the Standord W. Ascherman Professor of Engineering endowed chair at Stanford University. S. J. Eglash is also at the Materials Research Laboratory, Hewlett-Packard Laboratories, Palo Alto, California.

REFERENCES 1. J. Bardeen, Phys. Rev. 71, 717 (1947). 2. I. Lindau and W. E. Spicer, in "Synchrotron Radiation Research" (H. Winick and S. Doniach, eds.), Chap. 6. Plenum, New York, 1980. 3. W. E. Spicer, P. R. Skeath, C. Y. Su, and I. Lindau, J. Phys. Soc. Jpn., Suppl. A 49, 1079 (1980). 4. W. E. Spicer, S. Eglash, I. Lindau, C. Y. Su, and P. R. Skeath, Thin Solid Films 89, 447 (1982); S. Eglash, W. E. Spicer, and I. Lindau, Thin Solid Films 89, L35 (1982). 5. /. Vac. Sci. Technol. Bl, 519 (1983); /. Vac. Sci. Technol. 21, 285 (1982); and previous proceedings of Conferences on The Physics and Chemistry of Semiconductor Interfaces. 6. I. Lindau, and W. E. Spicer, J. Electron Spectrosc. Relat. Phenom. 3, 409 (1974). 7. M. P. Seah, and W. Dench, Surf. Interface Anal. 1, 2 (1979). 8. W. E. Spicer, P. W. Chye, P. R. Skeath, C. Y. Su, and I. Lindau, /. Vac. Sci. Technol. 16, 1422(1979). 9. W. E. Spicer, P. W. Chye, P. R. Skeath, C. Y. Su, and I. Lindau, Inst. Phys. Conf. Ser. 50, 216(1980). 10. C. B. Duke, Appi Surf. Sci. 11/12, 1 (1982) and references therein. 11. W. E. Spicer, I. Lindau, P. R. Skeath, and C. Y. Su, J. Vac. Sci. Technol. 17,1019 (1980). 12. W. Monch, and H. Gant, Phys. Rev. Lett. 48, 512 (1982). 13. M. S. Daw, and D. L. Smith, Phys. Rev. B 20, 5150 (1979). 14. M. S. Daw, and D. L. Smith, /. Vac. Sci. Technol. 17, 1028 (1980). 15. M. S. Daw, and D. L. Smith, Appi. Phys. Lett. 36, 690 (1980). 16. R. E. Allen, and J. D. Dow, J. Vac. Sci. Technol. 19, 383 (1981). 17. R. E. Allen, and J. D. Dow, Phys. Rev. B 25, 1423 (1982). 18. A. Zur, T. C. McGill, and D. L. Smith, J. Vac. Sci. Technol. Al, 608 (1983). 19. A. Zur, T. C. McGill, and D. L. Smith, Phys. Rev. B 28, 2060 (1983). 20. W. E. Spicer, S. Pan, D. Mo, N. Newman, P. Mahowald, T. Kendelewicz, and S. Eglash, J. Vac. Sci. Technol. B2, 476 (1984); T. Kendelewicz, R. S. List, M. D. Williams, I. Lindau, and W. E. Spicer (submitted for publication). 21. A. Nedoluha, J. Vac. Sci. Technol. 21, 429 (1982). 22. T. Kendelewicz, W. G. Petro, I. Lindau, and W. E. Spicer, J. Vac. Sci. Technol. B2, 453 (1984). 23. J. M. Woodall, and J. L. Freeouf, J. Vac. Sci. Technol. 21, 574 (1982). 23a. J. Tersoff, Phys. Rev. Lett. 52, 465 (1984). 24. H. H. Wieder, Appi. Phys. Lett. 38, 170 ( 1981 ). 25. H. H. Wieder, Inst. Phys. Conf. Ser. 50, 234 (1980). 26. J. O. McCaldin, T. C. McGill, and C. A. Mead, J. Vac. Sci. Technol. 13, 802 (1976).

116 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 44a. 44b. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64.

William E. Spicer and Stephen J. Eglash T. F. Kuech, and J. O. McCaldin, J. Vac. Sci. Technol. 17, 891 (1980). M. S. Daw, and D. L. Smith, Solid State Commun. 37, 205 (1981). K. Kajiyama, Y. Mizushima, and S. Sakata, Appi. Phys. Lett. 23, 458 (1973). K. Okamoto, C. E. C. Wood, and L. F. Eastman, Appi. Phys. Lett. 38, 636 (1981). J. S. Best, Appi. Phys. Lett. 34, 522 (1979). C. A. Mead, Solid State Electron. 9, 1023 ( 1966). J. M. Woodall, J. L. Freeouf, G. D. Pettit, T. Jackson, and P. Kirchner, /. Vac. Sci. Technol. 19,626(1981). C. Y. Chen, A. Y. Cho, K. Y. Cheng, and P. A. Garbinski, Appi. Phys. Lett. 40,401 ( 1982). D. V. Morgan, and J. Frey, Electron. Lett. 14, 737 (1978). S. J., Eglash, N. Newman, S. Pan, W. E. Spicer, D. M. Collins, and M. P. Zurakowski, Proc. Int. Electron. Devices Meet. Washington, DC. p. 119 (1983). H. K. Bûcher, B. C. Burkey, G. Lubberts, and E. L. Wolf, Appi. Phys. Lett. 23,617 ( 1973). J. M. Shannon, Appi. Phys. Lett. 25, 75 (1974). J. M. Woodcock, and J. J. Harris, Electron. Lett. 19, 93 (1983). S. J. Eglash, S. Pan, D. Mo, W. E. Spicer, and D. M. Collins, Jpn. J. Appi. Phys. 22, Suppl. 22-1,431(1983). F. A. Ponce, and S. J. Eglash, unpublished (1982). A. Y. Cho, and P. D. Dernier, J. Appi. Phys. 49, 3328 (1978). J. P. Ponpon, and P. Siffert, J. Phys. Lett. (Orsay, Er.) 36, L149 (1975). S. S. Li, Solid State Electron. 21, 435 (1978). J. M. Shannon, Appi. Phys. Lett. 35, 63 (1979). R. J. Malik, T. R. Aucoin, R. L. Ross, K. Board, C. E. C. Wood, and L. F. Eastman, Electron. Lett. 16,836(1980). C. C. Chang, D. L. Lynch, M. D. Sohigian, G. F. Anderson, T. Schaffer, and G. I. Roberts, IEEE MTT-S Dig. 206 (1982). V. L. Rideout, Solid State Electron. 18, 541 (1975). B. L. Sharma, "Semiconductors and Semimetals," (R. K. Willardson and A. C. Beer, eds.), p. 1, Academic Press, New York, 1981. N. Braslau, Thin Solid Films (to be published). A. Piotrowska, A. Guivarc'h, and G. Pelous, Solid State Electron. 26, 179 (1983). E. H. Rhoderick, "Metal-Semiconductor Contacts." Clarendon, Oxford, 1980. A.Y.C. Yu, Solid State Electron. 13, 239 ( 1970). S. P. Kowalczyk, J. R. Waldrop, and R. W. Grant, /. Vac. Sci. Technol. 19, 611 (1981). P. A. Barnes, and A. Y. Cho, Appi. Phys. Lett. 33, 651 (1978). R. Stall, C. E. C. Wood, K. Board, and L. F. Eastman, Electron. Lett. 15, 800 (1979). J. Derrien, and F. A. D'Avitaya, Surf. Sci. 65, 668 (1977). K. H. Kingdon, and I. Langmuir, Phys. Rev. 21, 380 (1923). P. Skeath, C. Y. Su, I. Lindau, and W. E. Spicer, /. Vac. Sci. Technol. 17, 874 (1980). P. Skeath, I. Lindau, C. Y. Su, and W. E. Spicer, J. Vac. Sci. Technol. 19, 556 (1981). C. B. Duke, A. Paton, L. J. Brillson, A. Kahn, D. Kanani, J. Carelli, G. Margaritondo, and A. Katnani, Phys. Rev. Lett. 46, 440 (1981). R. Z. Bachrach, and R. S. Bauer, /. Vac. Sci. Technol. 16, 1149 (1979). A. Kahn, J. Carelli, K. Kanani, C. B. Duke, A. Paton, and L. J. Brillson, J. Vac. Sci. Technol. 19,331 (1981). M. D. Williams, W. G. Petro, T. Kendelewicz, S. H. Pan, I. Lindau, and W. E. Spicer, Solid State Commun. 51, 819 (1984). J. Johannesson, private communication (1983). W. G. Petro, I. A. Babalola, T. Kendelewicz, I. Lindau, and W. E. Spicer, J. Vac. Sci. Technol. Al, 1181 (1983).

3. Unified Defect Model and GaAs Integrated Circuits

117

65. L. J. Brillson, Surf. Sci. Rep. 2, 123 (1982) and references therein. 66. N. Newman, T. Kendelewicz, D. Thomson, S. H. Pan, S. J. Eglash, and W. E. Spicer, submitted to Solid State Electron. 67. M. Spencer, Ph.D. dissertation, Cornell University (1980). 68. D. E. Aspnes, Surf Sci. 132, 406 (1983).

VLSI ELECTRONICS: MICROSTRUCTURE SCIENCE, VOL. 10

Chapter 4 Heterostructure Device Physics: Band Discontinuities as Device Design Parameters HERBERT KROEMER Department of Electrical and Computer Engineering University of California, Santa Barbara Santa Barbara, California

I. II.

Introduction: Why Heterostructures? Band Offsets A. The Problem B. The Harrison Atomiclike Orbital (HAO) Theory of Band Lineups C. Experimental Band Lineups D. Comparison of the HAO Theory with Experiment and Critique of the Theory E. Alternate Theoretical Approaches F. Linearity and Transitivity G. Recent Revisions and Updates III. Band Bending and Space Charge Layers at Abrupt Heterojunctions A. The Electrostatics of Depletion and Accumulation Layers B. Abrupt n-n Heterojunctions C. Abruptp-n Heterojunctions IV. The High Electron Mobility Transistor (HEMT): A Device Example A. The Idea B. Elements of a Quantitative Theory of the HEMT References

121 125 125 127 129 133 135 137 139 140 140 144 149 156 156 160 164

I. INTRODUCTION: WHY HETEROSTRUCTURES?

Traditional semiconductor devices are called homostructure devices. The basic semiconductor employed is the same throughout the device; only the 121 Copyright © 1985 by Academic Press, Inc. All rights of reproduction in any form reserved. ISBN 0-12-234110-4

122

Herbert Kroemer

doping of the semiconductor depends on position within the structure. Heterostructures are semiconductor structures in which the basic semiconduc­ tor itself is different in different portions of the structure. (For an excellent review, see Casey and Panish [1]; older reviews that are still useful are Sharma and Purohit [2] and Milnes and Feucht [3].) The currently most widely used semiconductor heterostructures involve the binary III-V com­ pound GaAs combined with the ternary alloy (Al^Ga1_x)As, where x is a compositional parameter that may assume any value between 0 and 1. Two examples of other important semiconductor heterojunction pairs are InPGa 047 In 053 As and GaSb-AlSb. The combinations listed are not arbitrary; they are lattice-matched pairs with very similar lattice constants. Lattice matching is important, because it minimizes the number of broken bonds at the interface, which would act as undesirable electronic defects. There are several reasons why the incorporation of heteroj unctions into device structures is advantageous. The dominant one, more important than all other reasons combined, is the fact that the abrupt change in the basic semiconductor implies an abrupt change in the energy band structure. This invariably leads to discontinuities, or offsets, in the conduction and valence band edges (Fig. 1). These offsets act as potential steps like abrupt electro­ static potential steps but independently of (and in addition to) whatever purely electrostatic potential variations are present. Such quasielectric po­ tential steps provide an extraordinarily powerful new design parameter to aid in the control of the flow and distribution of the mobile charge carriers in device structures. They may be utilized either to aid the purely electrostatic forces or to oppose them, and in devices in which both electrons and holes are present, band offsets may be used in conjunction with purely electrostatic forces to control the distribution and flow of electrons and holes separately and independently of each other. (For a detailed review see Kroemer [4];

(a)

(b)

(c)

Fig. 1. Band discontinuities at abrupt semiconductor heteroj unctions. Three different pos­ sible band lineups are shown: (a) straddling lineup, (b) staggered lineup, and (c) broken-gap lineup. (From Kroemer [9].)

123

4. Heterostructure Band Discontinuities

Kroemer [5] gives a brief discussion of this idea, and Kroemer [6] applies it specifically to the heterostructure bipolar transistor.) As an example, consider the straddling band lineup shown in Fig. la. The two band offsets act as potential steps that push both electrons and holes into the same direction, namely, towards the narrower-gap semiconductor. This is entirely different from purely electrostatic forces acting on electrons and holes, which are necessarily of equal magnitude but opposite direction. The most direct utilization of this idea is the quantum well laser (for a review, see Holonyak et al [7], an advanced form of heterostructure laser in which pairs of abrupt heteroj unctions create very narrow (= 100 À) potential wells (Fig. 2) capable of confining both electrons and holes within the same thin layer, something inherently impossible by purely electrostatic forces. Such lasers are expected to play a central role in the future of optoelectronics, including specifically the optical ICs that are likely to play an important part in the future of VLSI technology. The utilization of band offsets is by no means restricted to bipolar devices such as lasers and bipolar transistors [6]. In most device structures there are strong true electricfieldspresent in addition to the quasielectricfieldscaused by the band offsets. Whatever the direction of the purely electric field at an abrupt heteroj unction with a straddling lineup, the total force on one of the two carrier species is opposite to the purely electrostatic force on that species. This force reversal may be used as a powerful design tool in its own right, even in devices that contain only one carrier species. The most striking utilization of this idea occurs in an advanced form of heterostructure field effect transistor (FET), in which the conduction takes place inside a thin

V >> > >> >

"ΓΓΓΓΓΓλ

!>%>Ψ?Κ

w

fr* téift Ύ/SSSf

Fig. 2. Simple two-well quantum well laser structure. Electron - hole pairs are injected into and trapped within narrow potential wells, generated by pairs of oppositely directed straddlinglineup heteroj unctions. There they recombine with emission of light. The number of wells may vary from one to a large number; structures with a large number of wells are commonly referred to as superlattices.

124

Herbert Kroemer

layer of high-purity semiconductor, along the hetero-interface with a differ­ ent semiconductor that is heavily doped and whose conduction band has a higher energy ec (Fig. 3). The potential step downward from the doped layer causes the electrons to drain from the doped layer into the high-purity layer and prevents them from returning into the doped layer, despite the coulombic attraction exerted by the unneutralized donors, which pulls the electrons towards the interface. Such FETs, variously referred to as high electron mobility transistors (HEMTs), modulation-doped FETs (MODFETs) or two-dimensional electron gas FETs (TEGFETs) are expected to play a cen­ tral role in future high-speed device technology, including specifically high­ speed VLSI. (For a recent review see Mimura [8]; see also Delagebeaudeuf and Linh [8a].) The quantum well laser and the HEMT are by no means the only exam­ ples of the utilization of heterostructure band offsets to achieve new and/or improved devices; they were simply chosen to illustrate the basic idea under­ lying almost all heterostructure devices. The reader interested in additional examples is referred to the literature [4-6]. It is clear that in order to be able to utilize heterostructure band offsets as device design parameters, it is necessary to know the magnitude of the band offsets. Section II of this chapter summarizes the present status of our knowl­ edge on this matter. Section III then discusses the complete energy band diagram of a single heteroj unction in the presence of the band bending caused by the space charges that accompany heteroj unctions just as they accompany p-n homojunctions. The last section discusses the HEMT in detail, as the prototypical device for VLSI applications that draws on abrupt hetero-interfaces in an essential way.

Fig. 3. Electron transfer from a heavily doped semiconductor with an energetically high conduction band into an undoped semiconductor with a lower-energy conduction band. The conduction band offset step blocks the coulombic attraction between the electrons and the donors.

4. Heterostructure Band Discontinuities

125

II. BAND OFFSETS A. The Problem

The treatment of the heteroj unction band offset problem given here is based on a more extensive recent critical review [9] of the theory of heterojunctions, hereafter often referred to simply as CR. That paper is in itself a sequel to an earlier review [4] on the role of hetero-interfaces in devices. The problem of the band offsets at an abrupt heteroj unction can be di­ vided into two independent parts [10]: (i) The problem of the lineup of the energy bands in each semiconductor relative to the periodic potential in the same semiconductor, (ii) the problem of the alignment of the two periodic potentials relative to each other. Thefirstproblem is not itself a heteroj unction problem but one in bulk band theory. The central problem of band lineup theory is that of the lineup of the two periodic potentials relative to each other. It is useful to discuss the problem of the potential lineups in terms of a simple first-order reference model of a linear superposition of atomiclike potentials (LSALP) [9]. Given the two periodic potentials within the two individual bulk semiconductors, we may always view them as a linear super­ position of overlapping atomiclike potentials. Near the atomic nuclei, the atomiclike potentials resemble the potentials inside the free atoms. But in the regions between the atoms, especially within the interstices in the diamond and zincblende structure, these potentials will be different from free-atom potentials; hence our designation atomiclike potentials. For any given peri­ odic potential, such atomiclike potentials can always be defined, although their actual extraction appears to have been performed rarely. But concep­ tually at least, the bulk band structure may be viewed as being known relative to the atomiclike potentials in the crystals. The simplest possible atomic theory of band lineups is obtained if the potential throughout the entire structure is approximated as a superposition of unmodified overlapping atomiclike potentials (Fig. 4). In the immediate vicinity of the interface itself, the potential would contain contributions from atoms on both sides of the interface, but with each atomiclike potential still being the same as deep inside the bulk of the particular semiconductor. In such a model, the relative lineup of the two bulk potentials is well defined. The band lineups are then also well defined, and the only problems are those of calculational technique. In fact, the most successful of the lineup theories, the Harrison theory [11,12], is conceptually of this kind.

126

Herbert Kroemer

Fig. 4. Simple model of the potential energy within a few atoms of a hetero-interface as a linear superposition of overlapping atomiclike potentials. Within each semiconductor the individual atomiclike potential for each atomic species is the same for all atoms ofthat species. Near the interface the potentials from the two sides overlap. (From Kroemer [9].)

In the strict LSALP model there is no place for any crystallographic orientation dependence or technology dependence of the band lineups. All those must be due to deviations from the model. In the vicinity of the interface we must expect charge and potential re-ad­ justments relative to the predictions of a simple linear superposition of atomiclike bulk charges and potentials. The charges will re-adjust in re­ sponse to various forces, such as image forces, quantum mechanical ex­ change forces, and tunneling. The overall result of these re-adjustments is an electronic interface re-adjustment dipole, which shifts the bands relative to one another, compared to the linear superposition model. In addition to these electronic dipoles we must expect atomic (or ionic) interface dipoles to occur if, for whatever reason, atoms from one semicon­ ductor cross over the ideal interface into the other semiconductor. At least in mixed-column systems this can produce large net dipoles. These dipoles—of either origin—do not appear to be large (usually at most a few tenths of an electron volt). But they are the major bottleneck in the use of lineup theories for accurate predictions on the level of accuracy desired for device applications. For example, for the GaAs-(AlGa)As heterosystem, variations of band lineups with technology and with crystallo­ graphic orientation have been reported [9,13]. Such variations are inherently outside the possibility of the simple LSALP model and are therefore neces­ sarily consequences of dipole shifts, presumably atomic ones.

4. Heterostructure Band Discontinuities

127

B. The Harrison Atomiclike Orbital (HAO) Theory of Band Lineups 1. The Idea

If we ignore theories that are in hopeless disagreement with experimentally observed band lineups of the conceptually and technologically simplest hetteroj unctions, between two nearly lattice-matched III-V compounds, the simplest remaining theory is Harrison's atomiclike orbital (HAO) theory [ 11 ; 12, Section 10F]. It also appears to give the best agreement with experi­ ment, a combination that makes it the standard of comparison against which all others must be measured. Conceptually, HAO comes closest to the simple LSALP model introduced earlier. Harrison never explicitly calculates an atomiclike potential, but instead proceeds as follows. He sets up the linear combination of atomic Orbitals (LCAO) band structure calculation formalism (for nearest neighbors only) as if true atomiclike potentials and energy eigenfunctions were known. This formalism does not require the knowledge of either the full atomiclike potential or the full wave functions; All that is needed are selected unper­ turbed atomic energy eigenvalues and four different kinds of matrix ele­ ments coupling the relevant atomic states between nearest neighbors. Harri­ son simply takes as unperturbed atomic energy values accurately known (calculated) values for free atoms. This choice specifies the energies of all bands relative to the energy at infinity ofthefree atoms. To the extent that the free-atom potentials differ from the atomiclike potentials inside the solid, this choice is only an approximation, but it is what makes the problem tractable. Harrison's approximation for the matrix elements is just as daring. In principle, we would need a different set of matrix elements for each semiconductor. But Harrison argues persuasively that the principal reason for differences between matrix elements for different compounds is the difference in interatomic distance d. He asserts that each of the four kinds of matrix elements can be approximated very well for all compounds by writing it in the form ηΗ2/ηιά2, where η is a constant that is the same for all zinc blende-type semiconductors, and d the nearest-neighbor distance in the particular semiconductor. There remains then only a set of four η parame­ ters, and these are determined by adjusting them in such a way that certain accurately known experimental bulk properties of selected III-V com­ pounds (especially selected band structure data) are fitted to the theory to give the best possible overall agreement. Up to this point, HAO is simply a (surprisingly successful) attempt to match the energy band structures of the III-V compounds to a simple LCAO model with a minimum number of parameters. It becomes a theory

128

Herbert Kroemer

of band lineups by postulating that the zero of the energy scale, which is established by the use of the free-atom energy levels, may be used as the energy at infinity for the atomiclike potentials introduced by us earlier as the conceptual basis of the lineup theory, but never calculated in HAO. Note the wording: "may be used as . . . ."The point is that even a large error in this zero is irrelevant if the error is the same for each III - V compound. It is only any difference in errors that would falsify the final lineups. TABLE I Band-Edge Energies (eV) of Various Semiconductors Relative to the Valence Band of GaAs. a III-V Compounds Cation Al CB* VBC Ga CB VB In CB VB

P

As

Sb

.Xd\ 1.95 (3.\)e -0.50

X: 2.17 (2.52) -0.04

X: 2.44 (3.08) + 0.86

X: 1.79(2.31) -0.47 + 1.24 -0.11

+ 1.42 0.00

+ 1.57 + 0.84

+ 0.68 + 0.32

+ 1.29 + 1.12

II-VI Compounds Cation

S

Zn CB VB Cd CB VB

Se

Te

+ 1.93 -1.87

+ 1.82 -1.05

+ 2.42 +0.03

+ 0.97 -1.59

+ 1.02 -0.82

+ 1.81 + 0.21

Si and Ge Edge CB VB a

Si

Ge

Δ: +-1.15(4.21) + 0.03

L: +1.08 (1.22) + 0.41

After Harrison [11,12]. * CB = conduction band edge. c VB = valence band edge. d X, Δ, and L preceding the conduction band value indicates an indi­ rect gap. e Values in parentheses indicate a direct gap.

4. Heterostructure Band Discontinuities

129

Because the valence band structure of the zincblende-type semiconduc­ tors fits an LCAO model much more accurately than the conduction band structure, Harrison expresses the band lineup in terms of the valence band offsets. The conduction band offsets are then obtained indirectly from the predicted valence band offsets by adding the difference between the accu­ rately known experimental energy gaps. 2. The Harrison Lineup Tables

We express here the results of the Harrison theory in Table I. For conve­ nience, we have re-expressed all energies relative to the top of the valence band of GaAs rather than using Harrison's pseudo-vacuum level. The col­ umns for III - V and II - VI compounds represent equal anions, and the rows equal cations. The bottom entry in each box is the energy of the valence band edge, the top entry the conduction band edge, obtained by adding the experi­ mental 300-K energy gaps. For the III-V compounds the gaps were taken from the excellent compilation in Casey and Panish's book [1], which are believed to be more accurate than the values used by Harrison. In those cases where the conduction band edge is not at k = 0, the notation X, Δ, or L has been added to indicate the location of the band edge, and the value at the Γ point has been given in parentheses. Table I represents the best theoretical estimates that can currently be given for heterojunction band lineups. As we shall see shortly, the agreement tends to be better than ± 0.2 eV, even for lattice-mismatched heterojunctions and for some heterojunctions involving semiconductors from different columns of the periodic table. (See Subsection II.G for recent revisions that change this assessment.) C. Experimental Band Lineups 1. The Problem

In order to assess the validity of any theory of band lineups, it is necessary to compare its predictions with band offsets that are already known experi­ mentally with a degree of reliability sufficient to permit a meaningful test. As was discussed extensively by Kroemer [4], although the literature contains a very large number of lineup data for many different semiconductor pairs, few can be considered reliable enough to permit a meaningful test of lineup theories. Often the scatter of data signals their unreliability. For the widely studied Ge-GaAs system, conduction band offsets ranging from 0.09 to 0.54 eV have been claimed in the literature, a range corresponding to 68% of the energy gap of Ge. For GaP-GaAs, the range of claims goes from 0.0 to

130

Herbert Kroemer

0.65 eV. Many of those values must be wrong, and this makes all data suspect. Ignoring ordinary measurements inaccuracies, we can identify three problem areas. a. Indirect Measurement Techniques. Many techniques that have been employed to extract band offsets determine those offsets only very indirectly by projecting the results of whatever measurement is employed upon a preconceived model of the heterojunction. If the model is not valid, the resulting offset values may be invalid, too. In particular, small residual interface charges tend to distort grossly the results of some measurement techniques. The author has given a critical assessment of various measure­ ment techniques in another publication [4], the results of which may be summarized as follows. Probably the most reliable data are those obtained from ultraviolet (UPS) or x-ray photoelectron spectroscopy (XPS) photoemission experiments [14] on very thin heterojunctions, provided the heterojunction itself was pre­ pared by a technology yielding high structural perfection. A close second to UPS-XPS measurements are optical absorption (not emission!) measure­ ments on multi-quantum well structures (superlattices) [15]. (See Subsec­ tion II.G for recent revisions that change this assessment.) Capacitancevoltage (C- V) measurements on heteroj unctions may or may not be reliable, depending on the exact nature of the measurement [4]. Least reli­ able are / - F measurements; many are essentially worthless [4]. b. Technology Problems. Heterojunction band offset data tend to de­ pend somewhat on technological details of how the heterojunction is pre­ pared. Presumably, different technologies lead to somewhat different atomic arrangements at the interface and, hence, to varying atomic interface dipoles. Exactly why this is so is in itself an unsatisfactorily solved problem. But whatever the reason, it is clear that we cannot fully trust data that were taken on structures prepared under conditions significantly different from those employed for the high-quality device structures whose lineups are the real object of the theory. c. Chemically Induced Interface Dipoles. Many heteroj unctions that have been studied involve two semiconductors from different columns or column pairs of the periodic table, such as Ga-GaAs, Ge-ZnSe, GaAsZnSe, InP-CdS, and many others. In all such systems, any interchanges of atoms across the interface will introduce atomic dipole moments that change the band offsets. Such atom interchange effects cannot, in general, be pre­ vented. In fact, it has been shown (see Harrison et al [ 16] and also Kroemer [4]) that for most crystallographic orientations, atom interchanges across the

131

4. Heterostructure Band Discontinuities

interface are necessary in order to prevent the accumulation of a huge inter­ face-destabilizing net interface charge. The final result will be an interface with both a residual interface dipole and interface charge, the magnitudes of which depend sensitively on technology. These effects can be minimized by working with the electrically neutral (110) cleavage planes of the compounds and by growing the junction at a low temperature. But the latter is only a compromise, because the low-temperature growth tends to lead to poor bulk properties not representative a device-equality semiconductor. 2. Reference Systems for Theory Testing

a. Lattice-Matched Isocolumnar Systems. When all these problems are taken into consideration, only two heterosystems remain that can truly serve as standards of comparison for lineup theories: the Al^Ga^^As-GaAs sys­ tem and the InAs-GaSb system. For the first of these, both superlattice absorption data [15] and XPS data [13] for (lOO)-oriented abrupt heterojunctions show that the valence band offset is 15 ± 3% of the direct energy gap at k = 0, both for x in the range 0.2-0.3, and for x = 1. If we assume a linear relationship with x, the data can be described by AeJAl^Ga^As -* GaAs] = (0.19 ± 0.04)x eV. (See Subsection II.G for recent revisions that change this assessment.) To specify the sign of Aev, we adopt the convention that Aey[A —> B] shall be counted positive if the band-edge step is an upward step in going from A to B. For InAs-GaSb, various data [17] show beyond any doubt that this sys­ tem is of the broken-gap variety (Fig. lc), with a break in the gap of about 150 ± 50 meV. Combined with the 300-K energy gap of InAs (0.36 eV), this yields Aev[InAs -> GaSb] = (0.51 ± 0.05) eV. The very unusual nature of this broken-gap lineup makes this system a severe test of any theory of heteroj unction lineups. b. Lattice-Mismatched Isocolumnar Systems. Compared to the (Al, Ga)As-GaAs and InAs-GaSb data, all other lineup data suffer from one uncertainty or another. Most likely to be reliable are the XPS-UPS data for InAs-on-GaAs [18] and for Ge-on-Si [19], for which the following lineups have been reported: Aev[InAs -> GaAs] = -0.17

eV,

Aev[Ge -> Si] = - 0 . 2

eV.

The trouble with both systems is that they are badly lattice mismatched (7

132

Herbert Kroemer

and 4%). We must expect that the exact lineups depend on how exactly this mismatch is accommodated at the interface; hence, they should be technol­ ogy dependent. In the Ge - Si case this criticism is aggravated by the fact that the Ge was grown at an unrepresentatively low temperature. As a result, it is not clear to what extent the band offsets for both systems should agree with any theory that has made idealizing assumptions (even if implicitly) about the atomic structure of the interface and of the crystal itself. c. Mixed-Column Systems. There exist large numbers of lineup data on heteroj unctions in which the two semiconductors come from different col­ umns of the periodic table. As was mentioned earlier, and discussed exten­ sively elsewhere [4,9], all such systems are prone to exhibit technology-de­ pendent interface charges and interface dipoles. These effects depend very strongly on the crystallographic orientation of the interface. The two least suspect orientations are the nonpolar (110) and (112) orientations [4,9,16,20,21 ]. The widely used (001 ) and (111) orientations are highly nonideal for such systems, no matter how ideal they may be for III-V-only heteroj unctions. Of all mixed-column lineup data in the literature the ones we consider least likely to suffer from complications are the XPS data of Kowalczyk et al. [22] for heterojunction of ZnSe grown on GaAs(l 10) at 300°C (not their 23°C growth data): Aev[ZnSe-on-GaAs(l 10)] = (0.96 ± 0.03) eV. In heteroj unctions between one of the column IV elements and a III - V or a II-VI compound, the problem of interface charges and dipoles is greatly compounded by the severe antiphase disorder that is likely to occur if the compound semiconductor is grown on the elemental semiconductor sub­ strate, rather than in the opposite order. There probably does not exist a heterosystem more ill suited to a test of band lineup theories than GaAs grown on (001 )-oriented Ge; yet this combination has been one of the most widely studied—with predictably irreproducible results. In our judgment, such compound-on-element systems should be expected not to satisfy any simple lineup theory. Only systems in which the element was grown upon the compound should be considered for testing such theories. Probably the least suspect data on any element-on-compound system are the XPS data (again of Kowalczyk et al [22]) for Ge grown on ZnSe(l 10): Aev[Ge-on-ZnSe(l 10)] = -(1.52 ± 0.03) eV. It is only with considerable reluctance that we include among the reference systems what is one of the most widely studied heterosystems, Ge-on-GaAs. The lineup data on this system scatter so widely (see, for example, Mönch et

4. Heterostructure Band Discontiniuties

133

al and references therein [23]) that it appears difficult to decide which of the data are least unreliable, and the strong chemical interaction of Ge with As makes the system prone to chemical interface reactions. (See, for example Bauer and Mikkelsen [24], which contains extensive reference to earlier work.) However, recent data on MBE-grown Ge-on-GaAs(l 10) heterojunctions have tended to converge towards what appears to be the most carefully determined value, that of the Rockwell group [25], Aev[Ge-on-GaAs(l 10)] = -(0.53 ± 0.03) eV, obtained again by XPS on junctions grown at 425 °C. 3. Anion Correlation Rule

There is strong independent evidence that in all systems such as (Al,Ga)As-GaAs and InAs-GaAs, in which the anion atom species (As) on both sides of the heteroj unction is the same, the valence band offsets should be much smaller than the conduction band offsets [26]. This common anion rule arises from the theoretically well-established fact that the valence band wave functions derive largely from the anion atomic wave function. (For a very "physical" discussion of this topic, see Harrison [12, Chaps. 1-3, 6].) This, together with the fact that the valence band wave functions tend to be more localized than the conduction band wave functions, yields valence band energies that correlate strongly with the anion species. For semicon­ ductor pairs with a common anion, this leads to valence band offsets that should always be small compared to the conduction band offsets. For semiconductor pairs with the common cation X, the valence band energies at the interface should correlate with the different anion electro­ negativities. For the III-V compounds this implies that ev(XP) < €v(XAs) < €v(XSb).

(1)

If the correlation is strong enough, we might expect Eq. (1) to persist even if both anion and cation are different. The HAO theory [11,12] exhibits this expected correlation, as is readily seen from Table I. D. Comparison of the HAO Theory with Experiment and Critique of the Theory

Figure 5 shows a comparison of the experimental data for those systems selected above as having the most reliable experimental data. The fit speaks for itself. Table II gives the actual data. If we weigh all data points equally, we find a mean eror of only —0.016 eV, with a standard deviation of 0.13 eV. Also included are the data for the CdS-on-InP system, which has been

134

Herbert Kroemer

Δ€ ν (ΗΑΟ) Fig. 5. The experimental valence band offsets (in eV) for the seven reference systems selected in Subsection II.C plotted as a function of the theoretical valence band offsets predicted by the Harrison theory. The value for CdS-InP is also shown. The AlAs-GaAs value is extrapolated from Al^Ga^^As-GaAs for x = 0.3. A numerical tabulation with references is given in Table II. (From Kroemer [9].)

TABLE II Comparison of Valence Band Discontinuities Predicted by the Harrison Atomic Orbital (HAO) Theory for Selected Reference Systems0 Heteroj unction

HAO (eV)

Experimental (eV) [reference]

Error (eV)

AlAs-GaAs InAs-GaSb GaAs-InAs Si-Ge ZnSe-GaAs ZnSe-Ge GaAs-Ge CdS-InP

0.04 0.52 0.32 0.38 1.05 1.46 0.41 1.48

0.19 [13,15] 0.51 [17] 0.17 [18] 0.20 [19] 0.96 [22] 1.52 [22] 0.53 [25] 1.63 [27]

+ 0.15 -0.01 -0.15 -0.18 -0.10 + 0.06 + 0.12 + 0.15

a The AlAs-GaAs value is extrapolated from the Al^Ga^v.As-GaAs value with x = 0.3.

4. Heterostructure Band Discontinuities

135

invoked by Shay et al [27] as a reference system and which fits the HAO theory well, but which has deliberately not been included in the references for reasons discussed in CR [9]. Considering the number and severity of simplifications that the HAO theory makes, the level of agreement with the experimental data is remark­ able indeed. It goes significantly beyond what we might have expected a priori, and beyond what was indeed initially expected of this theory before the present range of reliable data became available. The author has given a detailed critique of the simplifications entering HAO in CR [9]. The level of agreement with experiment certainly suggests that these simplifications are indeed valid to a higher degree than we might have expected, but it is not really clear why this is so. As put forward in CR, this changes the nature of the critique from asking "what is wrong?" to "why is it right—or is it?". (See Subsection II.G for recent revisions that change this assessment.) Some suggestions about this are made in CR, but this is evidently still a fertile field for further research. Nor is this a purely academic point, of interest only to the fundamental interface physicist who is concerned principally with un­ derstanding the basic underlying physical mechanism, and to whom the agreement of a theory with experiment is largely of retrodictive value in the sense of testing the assumptions that went into the theory. The matter is of at least as much interest to the device physicist. He/she would like to have a predictive theory sufficiently accurate to permit actual quantitative device design for heterosystems for which no sufficiently accurate experimental data are available yet, which includes most systems other than (maybe) ( Al,Ga)As - GaAs. The author has addressed this need elsewhere [4], where it is pointed out that even the HAO theory is still far from reaching this ambitious goal. The good agreement shown so far raises the hope, however, that research into the academic question "why is it right?" might also lead to a better predictive theory. Only time will tell. E. Alternate Theoretical Approaches 1. The Frensley-Kroemer Pseudopotential Theory

The HAO theory was not the first attempt to predict heteroj unction band offsets automatically from the periodic potentials actually present inside the semiconductors, the energetic position of the bands within those periodic potentials, and the alignment of the periodic potentials relative to one an­ other. It was preceded by the Frensley-Kroemer pseudopotential (FKP) theory [28], which differed from HAO principally in calculational method­ ology. Although quite successful for some heteroj unction pairs (especially the tricky broken-gap pair InAs-GaSb), its success was not as consistent as

136

Herbert Kroemer

that of H AO, and the required calculations were more complicated. Never in widespread use, it has de facto been superseded by HAO. The interested reader is referred to CR [9], where a critical review and comparison with HAO is given. 2. The Electron Affinity Rule (EAR)

Until the emergence of HAO, the most widely used tool for the prediction of heteroj unction band lineups was the electron affinity rule (EAR) [ 1 3,29], which asserts that the conduction band offset is equal to the difference between the electron affinities χχ and/ 2 of the two semiconductors, with signs such that Aec = ec2 - €cl = - (χ2 - χλ).

(2)

In fact, the EAR continues to be widely used, although this continued use is probably largely due to the fact that the HAO theory and its demonstrably better agreement with existing experimental data are still not widely known. A critical review of the EAR and a comparison with HAO have recently been given in CR [9], to which the interested reader is once again referred. That review reassesses specifically the theoretical foundations of the EAR and the criticism of those foundations made earlier by the present writer [ 10], as well as the defense of the EAR raised by others in return [27,30]. 3. Self-Consistent Interface Potential Theories

All the theories discussed so far achieve their successes—whatever they may be—by ignoring the interface itself, including any redistribution of charge at the interface and with it any electronic interface dipole. To the extent that the theories (especially the HAO theory) are able to account for the experimentally observed band lineups, this disregard may be empirically justified, but conceptually it hardly represents a satisfactory state of affairs. One possible approach toward the problem of heteroj unction band lineups consists of a self-consistent quantum mechanical treatment of the interface region itself. The idea is this: The electron wave functions (and, hence, the charge distribution in the interface region) depend on the exact potential in that region; but this potential is in turn generated (in part) by the charge distribution and, hence, by the wave functions of the electrons in that potential. Evidently, a knowledge of the potential requires a knowledge of the wave functions, and vice versa. It is possible to obtain both kinds of quantities self-consistently by an iterative process. Given an approximate potential we can determine a new and presumably improved potential from the wave functions in that potential. The process may evidently be repeated, and if it converges, it results in a self-consistent set of potentials, wave

137

4. Heterostructure Band Discontinuities

functions, and charge distributions that automatically contain whatever electronic dipole shifts may be present. Convergence of the iteration is not automatic, but can be enforced by systematically applying suitable correc­ tions at each iteration step. The calculational effort required is formidable, but powerful techniques have been developed for handling such self-consistency problems on large high-speed computers at a tolerable cost. Following the pioneering work of Baraff et al [31], several efforts have been made to determine heterojunction band lineups in this fashion, especially by Cohen and his co-workers [3235]. (For an excellent review, see Cohen [32]; see also Pollmann and Mazur [32a].) Unfortunately, these calculations have so far not fulfilled the hope that they would provide a reliable predictive tool for accurate values of the band lineups that is free of the questionable simplifications of the simpler theories, such as HAO, FKP, and EAR. Except for the simple (Al,Ga)As-GaAs heteroj unction, the band lineups predicted by these self-consistent interface potential calculations have been in much poorer agreement with reliable observations than HAO. The discrepancy is especially strong for ZnSeGaAs (110), where Ihm and Cohen [35] predict a staggered lineup quite incompatible with the experimental data. For quantitative details see CR [9]. Apparently, these theories in their present form are not yet satisfactory tools for the prediction of any but the mildest interface discontinuities, and it is not clear that they offer much retrodictive insight beyond AlAs-GaAs either. Considering the outstanding success of pseudopotential theories in simpler problems, the reasons for this unsatisfactory state of affairs are probably not fundamental, but are purely matters of calculational accuracy. Presumably, this could be improved, at least to the point of retrodictively understanding the already observed band lineups. Whether such theories are likely to become accurate predictive tools remains doubtful, for reasons whose discussion goes beyond the scope of this chapter, but which are dis­ cussed in CR [9].

F. Linearity and Transitivity

The Harrison theory, the Frensley-Kroemer theory, and the electron affinity rule assumed that there is a specific absolute energy associated with the various band edges of every individual semiconductor and that the band offsets are simply the differences between the respective absolute band ener­ gies of the two semiconductors. With our sign convention, Aev[A^B]

= ey(B)-ev(A)·

(3)

138

Herbert Kroemer

Such theories may be called linear theories. Presumably, linearity is only an approximation, and we should really write Aey[A - B] = ey(B) - ey(A) + S(A - B\

(4)

where δ(Α —» B) is a correction that cannot be written as a linear difference between two individual properties of semiconductor A and B but is a true property of the specific combination A-B. The excellent agreement of ex­ perimental band lineups with the HAO theory (which is manifestly linear) suggests that δ{Α —► B) is small (below 0.2 eV). Note that the linearity property [Eq. (3)] is a property independent of exactly what theory is employed to calculate ev(A) and ey(B) individually; it is a property of an entire class of theories. It is possible to test experimentally whether or not the experimental data can possibly satisfy a linear theory, without actually invoking a specific theory. Given the band lineups of two different semiconductor pairs A-B and B-C, having one semiconductor (B) in common, the lineup for the third possible pair A - C follows by simple addition. With our sign convention, Aey[A -* C] = Aey[A -> B] + Aey[B -* C]

(5a)

Aey[A -+B] + Aey[B -> C] + Aey[C -> A] = 0.

(5b)

or This property has been referred to as transitivity by Frensley and Kroemer [28]. For example, from the lineups for InAs-GaSb and GaAs-InAs transi­ tivity predicts that the band lineup for GaAs-GaSb should exhibit a valence band discontinuity Aev[GaAs -> GaSb] = 0.51 +0.17 = 0.68 eV, with the GaSb valence band being the higher one. This prediction is indepen­ dent of whatever theory we might wish to invoke for the band lineups, so long as it is a theory of this linear class. Because transitivity should be a common feature of entire classes of theories, tests for transitivity are useful tests of great generality that do not involve fitting experimental data to any particu­ lar lineup theory but may rule out entire classes of theories if unsuccessful. In 1979, Waldrop and Grant [36] studied the lineup for the two highly unconventional heterojunctions CuBr-Ge and CuBr-GaAs by XPS. They found that the lineups, taken together with the already known lineup for Ge-GaAs, violated the transitivity sum rule condition [Eq. (5b)] by 0.64 eV. It was subsequently pointed out by Phillips [30] that this large discrepancy is more likely to be due to antiphase disorder in the CuBr-on-Ge growth — a compound-on-element system—than to a true nontransitivity. In their previously cited ZnSe work [22], the Rockwell group has studied

139

4. Heterostructure Band Discontinuities

the different systems Ge-on-ZnSe and ZnSe-on-GaAs which, together with the old standby Ge-GaAs, form another nearly lattice-matched triplet suit­ able for testing transitivity under difficult conditions. We had specifically included these Ge-on-ZnSe and ZnSe-on-GaAs among the experimental reference systems for theory testing. When the two lineups quoted earlier are combined with the Ge-on-GaAs lineup Δ€ν = 0.53 eV, we find the closure sum Aev[Ge-on-ZnSe] + Aev[ZnSe-on-GaAs] — Aev[Ge-on-GaAs] = - 1 . 5 2 + 0.96+ 0.53 = -0.03

eV,

an extremely small remainder, below the accuracy of the measurements themselves. It would appear then, that transitivity is indeed an excellent assumption for well-prepared heterojunctions. G. Recent Revisions and Updates

After the manuscript for this chapter had been completed, a number of new experimental results appeared [36a,36b] that seriously questioned the validity of the widely-accepted 85:15 value for the ratio of conduction band to valence band offsets in the GaAs- Al^Ga^As system, even though that ratio appeared to have been confirmed by a variety of techniques. As this chapter goes into print, it has become clear beyond a reasonable doubt that the old data are in fact incorrect, and that the true ratio is close to 62:38 [36c], at least for x < 0.4. Linearly extrapolated to x = 1, this would call for a valence band offset of 0.47 eV for pure AlAs on GaAs, rather than 0.19 eV. These new data do not fit the HAO theory at all, which must hence be considered less reliable than was previously thought, although still more reliable than its competitors, which suffer just as much from the change.The reasons for this discrepancy are not known yet. A possible clue is contained in the observation that the large valence band offset also violates a much more basic rule, the common anion rule, which appeared to be so wellfounded on quite fundamental grounds. The author suspects that the origin of both discrepancies lies in the fact that the Al atom does not have any d-electrons. Their absence should greatly weaken the orthogonality repul­ sion of the valence-band wave functions from the Al ion core (compared to other cations), thus weakening the common anion rule whenever the cation is Al. Inasmuch as the HAO theory in its present simple form does not take such atom-specific properties into account, we might expect a similar failure of this theory for all heteroj unctions involving an aluminum compound. These considerations suggest the temporary ad-hoc "fix" of simply lowering the valence band energies of all Al compounds by about 0.4 eV relative to

140

Herbert Kroemer

Harrison's values—at least until the theory itself has been refined. Recent observations on GaSb-AlSb superlattices [36d] lend empirical support to such an "aluminum fix."

III. BAND BENDING AND SPACE CHARGE LAYERS AT ABRUPT HETEROJUNCTIONS A. The Electrostatics of Depletion and Accumulation Layers 1. Potential Distributions

The band lineup considerations discussed in Section II refer to the band lineups immediately at the hetero-interface; they say nothing about the band energies relative to the Fermi level, either at the interface or far away from it. In the absence of a bias and in thermodynamic equilibrium, the Fermi level must be at a constant energy eF throughout the structure. Assuming that nondegenerate statistics is applicable, the electron and hole concentrations n and p are then given by n = Ncexp[-(ec-eF)/kTl

(6a)

p = Nvexv[-(eF-6y)/kT]. (6b) here Nc and Nv are the effective densities of states for the conduction and valence bands (presumably different on the two sides of the heterojunction), while ec(x) and ev(x) are the energies of the conduction and valence band edges, both functions of the position even inside each semiconductor. The lineup considerations of the preceding section specify the disconti­ nuities of ec and ev at the interface x = 0. Inside each semiconductor, the variation is governed by the Poisson equation d2ec

d2ey

ά2φ

w-z?—«*;-^'

q .x

(7)

where φ(χ) is the local electrostatic potential, p(x) the local space charge density, and κ the permittivity of the semiconductor (presumably different on both sides). We use κ rather than e for the permittivity, to avoid confusion with various energies labeled e. The letter E is used for electricfields.At the interface, D = KE = —K (άφ/dx) = continuous.

(8)

If the ionized donor and acceptor concentrations are ΝΌ(χ) and NA(x), then

141

4. Heterostructure Band Discontinuities

the space charge density is given by p(x) = q[NO(x) - NA(x) - n(x) + p(x)l

(9)

where n(x) and p(x) are given by Eqs. (6a) and (6b). We are specifically interested in the case of an n-n heterojunction, in which the donor concentrations on both sides are constant (but not necessar­ ily equal to each other), with both acceptor and hole concentrations negligi­ ble. Far away from the hetero-interface, the conduction band energy ec will be such that the semiconductor is electrically neutral: €c(oc) = 6C00,

«(oc) = ΝΌ = 7VC exp[- (ec - eF)/kT].

(10)

We may then write Eq. (9) in the form p(x) = qNO[l-exp(-y/)l

(11)

where ψ is the potential energy of the electrons inside the semiconductor in units of kT, relative to its asymptotic value at infinity inside the same semi­ conductor (12)

ψ{χ) = [ec(x)-ec-«

q d2 'ΈΓΊΧ1

=

exp(-^)],

exp(-y)] (13)

where in the last equality we have introduced the Debye length associated with the electron concentration n = ΝΌ: LO = (KkT/q2NOy2.

(14)

It is the natural unit of length for space charge problems in semiconductors. For a typical semiconductor with, say, ΝΌ= 1016/cm3, κ= 10/c0, and T= 300 K, we find L D = 37.8 nm, scaling with the square root of all vari­ ables, as given by Eq. (14). Equation ( 13) is evidently nonlinear in ψ, with the attendant mathemati­ cal difficulties. In the limit of small deviations from electrical neutrality, as they must exist sufficiently far way from the hetero-interface, we have | ψ\ x,), the sign of E is opposite that of ψ, while for x 2] designates the conduction band offset in going from semi­ conductor 1 to 2, counted as a positive quantity if the step is upward from 1 to 2, as in Fig. 6. The two potentials at infinity will be the same if NO2/Nc2 = NOl/NQ

c

—.

!

I

Fig. 6. Energy band of an abrupt n-n heterojunction. (From Kroemer [45].)

(29)

145

4. Heterostructure Band Discontinuities

In general, this will not be the case, which adds a term [(ecl - eF) - (ec2 - eF)] _

ND2 Ncl 1 η

kT

(30)

Λ ^

to the right-hand side of Eq. (28). Finally, we assume that the basic relationship [Eq. (17)] remains valid even if an external bias voltage Fapp is applied to the heterojunction, causing a current to flow. If we count the bias as positive when semiconductor 2 is biased positively relative to semiconductor 1, such a bias adds a further term KPP/kTto the right-hand side of Eq. (28), leading to

ψ2-ψι

N Aec[i l ^ + ln ^ D 2 cl kT ΝΌ1 Nc2

kT(y°

^

+ tf^app kT

(31)

^app),

where the meaning of V0 is self-evident. This treatment neglects the resistive voltage drop caused by the current. This is the same approximation as is usually made in the theory of reverse-biased (or only weakly forward-biased) p-n junctions and Schottky barriers. It will in general be an excellent ap­ proximation, if the conduction band offset is large and the applied bias voltage Fapp is a reverse bias (F app > 0) or only a weak forward bias. Equa­ tions (27) and (31) provide a pair of coupled equations for the two interface potentials ψχ and ψ2. They cannot be solved in closed form. The problem can be greatly simplified, however, if one of the two semicon­ ductors (say, 2) is strongly depleted, the case of principal interest to us anyway. We may then neglect the term exp(— ψ2) in Eq. (27) and rearrange the remainder into a functional relationship between ψι and ψ2 — ψχ : Ψι - Ψι = a exp(- ψχ) + ( 1 - α)( 1 - ψχ\

(32)

where a = KiNDÌ/K2NO2.

(33)

With the help of Eq. (31), this is an explicit relationship for the bias voltage necessary to achieve a specified notch depth — ] 0), the height of this barrier is reduced with increasing bias, thus causing the reverse current to increase. To the first order, the current will depend on the barrier height eB proportionally to exp(— eB/kT), that is, proportionally to exp(— ψχ). If a = 1, Eq. (35) then implies a linear increase of reverse current with reverse bias, as if the junction were shunted by an ohmic leakage path. To minimize this reverse leakage and to obtain good rectification characteristics for n - n heteroj unctions, it is necessary to choose the parameter a in Eq. (36) as large as possible, that is, to dope the notch side of the heterojunction much more heavily than the barrier side. With increasing reverse bias, the conduction band edge inside the notch may eventually slip below the Fermi level on the notch side, namely, when — ψχ exceeds ln(7Vcl /NOl). At this point, our treatment is no longer valid, and we must resort to a treatment employing the Joyce-Dixon approximation [38] mentioned earlier. One important result of such a treatment is the following. Once the electron concentration inside the notch becomes degen­ erate, the reverse current will increase with reverse bias more rapidly than linearly, initiating a gradual soft breakdown. (For details, see Kroemer [39].) Even the treatment by the Joyce-Dixon approximation quickly ceases to be a good approximation in such cases. As the conduction band edge drops below the Fermi level, the interface field tends to become very large, and the potential notch tends to become a very narrow potential well with a width comparable to the quantum mechanical wavelengths of the electrons inside. The allowed electron energies then become quantized, and the relationship between electron concentration and potential ceases to be given by Eq. (26); in fact, it ceases to be a strictly local relationship. The local electron concen­ tration then depends on the entire shape of the well, not just on the local potential. A quantitative treatment of this problem becomes complicated indeed and requires purely numerical methods. A further discussion goes

4. Heterostructure Band Discontinuities

147

beyond the scope of this chapter. (For some additional comments see again Kroemer [39].) 2. Interface Charges

Experience has shown that heteroj unctions often exhibit built-in excess charges in the immediate vicinity of the interface, that is, within at most a few nanometers [40-43]. The exact origin of these charges is not clear, but they are probably due to various kinds of interface defects: impurity segregation at the interface during growth, structural interface defects such as antisite defects in the basic semiconductors themselves, or (in mixed-column sys­ tems) a net interface charge due to imperfect cancellation of the ionic charges when the atomic occupancy of each of the two sublattices in the zincblende structure changes from one column of the periodic table to another [4,9,16]. Whatever their origin, even relatively small charge densities (< 1012/cm2) can have a drastic effect on the properties of any heteroj unction and particu­ larly on those of isotype heterojunctions. These complications are easily incorporated into the theory by treating the interface charge as a sheet charge whose density per unit area is qo. The continuity condition [Eq. (8)] for the electric flux must then be replaced by κ2Ε2 = κιΕι + qo.

(37)

In terms of the Eq. (27), it means that we must take the square root on both sides and then add a term qo/(2kT)l/2 to the right-hand side. This clutters up the algebra, and we can usually no longer obtain explicit closed-form expres­ sions such as Eq. (34) for the various quantities of interest. However, the problem remains easily tractable numerically. The effect of an interface charge depends significantly on the sign of the charge. A little reflection shows that a negative interface charge enhances the effect of the conduction band spike and flattens out the accompanying notch, while a positive charge pulls down the spike and deepens the notch (Fig. 7). A sufficiently large negative charge may cause depletion layers on both sides of the interface, while a sufficiently large positive charge will cause dual accumulation and completely obliterate the interface potential barrier, converting it into a potential well. Figure 7 actually assumes these two cases. It should be self-evident that even a small alteration of the overall heterojunction barrier height can have a large effect on the / - V characteristics of any isotype heteroj unction. This is the principal reason why n-n heterojunction / - V characteristics are all but useless for determining the band lineups for heterosystems whose technology is not yet mature enough to exclude the presence of significant interface charges. The point is by no means academic. The conduction band offset in the (Al, Ga)As-GaAs sys-

148

Herbert Kroemer

F'L

(a)

%

^ (b) Fig. 7. Band deformation due to (a) a negative and (b) a positive interface charge.

tern is sufficiently large that any abrupt n-n heterojunction in that system should exhibit pronounced rectification effects in the absence of interface charges, unless the (Al, Ga)As side is appreciably more heavily doped than the GaAs side, and even then it should rectify at sufficiently low temperature. Yet the early literature on that system contains numerous papers reporting either very poor or completely absent rectification at (Al, Ga)As - GaAs n-n heteroj unctions, even at low temperatures and even for heteroj unctions that were demonstrably abrupt metallurgically (see, for example, Garner et al [44] and references therein), eliminating an explanation in terms of a heterojunction barrier that was flattened out by compositional grading. The prob­ lem seems to have gone away with improvements in technology; it was probably due to an appreciable positive interface charge of unknown origin in those early structures. Although we should, in principle, be able to extract the magnitude of any interface charges from / - ^measurements, in practice most such measurements are too indirect to yield trustworthy results. Proba­ bly the most direct (and hence best) method is by C- F profiling through the hetero-interface from an adjacent Schottky barrier [41].

4. Heterostructure Band Discontinuities

149

The problem of interface charges is particularly severe for mixed-column systems, in which the atomic occupation of both sublattices of the zinc blende crystal structure changes at the interface from one column of the periodic table to another. It has been shown [16] that at such interfaces, for most crystallographic orientations, the simplest atomic arrangement (an abrupt compositional transition across a perfect plane) actually corresponds to a huge (σ > 1014/cm2) net interface charge imbalance. A neutral interface requires a very specific kind of compositional grading over several atomic planes that is not likely to arise by itself or to be achievable intentionally during growth. The unfavorable crystallographic orientations include specif­ ically the most widely used (100) orientations. The automatic built-in inter­ face charge is absent for only a few specific orientations (principally the (110) and (112) orientations [16,21]), and even then only if the orientations are exact and if various other complications are absent. To achieve interfaces with interface charges whose magnitude is either negligible for device pur­ poses or sufficiently constant that its variation is negligible requires a degree of technological control that is currently not achievable at all, or only at unacceptable cost. Inasmuch as reproducibility at acceptable cost is essential for VLSI technology, the author believes that for the foreseeable future, the interface charge problem will act as a serious deterrent against the incorpora­ tion of heterocolumnar heteroj unctions into VLSI circuits. C. Abrupt p-n Heterojunctions 1. General Properties

Qualitatively, the properties ofp - n heterojunctions are similar to those of p-n homojunctions, and little need be said about them in a chapter devoted specifically to the differences introduced into devices by incorporating heterojunctions. Those differences are largely quantitative ones. The most significant of these are effects associated with the occurrence of a spike-andnotch potential inside the junction. The case of greatest interest is that of a p-n junction in which the conduction band has a downward step in going from the n side to the p side (Fig. 8). Such junctions play a large role in heterostructure bipolar transistors (HBTs), with the p-type side being much more heavily doped than the «-type side. The conduction band spike then tends to project above the conduction band edge in the flat-band portion of the p-type side, a phenomenon particularly pronounced in the (Al, Ga)AsGaAs system, where most of the energy gap difference occurs in the conduc­ tion band. Such projecting potential spikes are a major problem in HBT design. On the emitter side, they greatly reduce the electron injection current into the

150

Herbert Kroemer

Fig. 8. Energy band diagram of an abrupt n-p (wide-narrow) heterojunction, as it might occur at the emitter junction of a heterojunction bipolar transistor.

base, and hence the ratio of electron to hole current, the increase of which was the primary motivation for introducing the heterostructure emitter in the first place. On the collector side, such a spike almost totally blocks the collection of the electrons injected by the emitter, destroying the transistor action (Fig. 9). Even if the conduction band spike does not project above the bulk con­ duction band edge on the p side, the potential notch still has a considerable nuisance value, because it acts as a trap for electrons, both on the emitter and 6 Γ-^Δ Β

Fig. 9. Electron blocking action for low reverse bias at an abrupt p-n heterojunction collector. The blocking action can be prevented by grading the heterojunction, as indicated by the broken line. (From Kroemer [6].)

4. Heterostructure Band Discontinuities

151

collector sides. On the emitter side, this leads to enhanced recombination; on the collector side the negative charge stored in the notch can actually raise the blocking spike back above the bulk band edge. It has been pointed out [6] that the electron trapping effect on the emitter side could be avoided by the deliberate introduction of a negative interface charge of suitable magnitude, albeit at the cost of further raising the conduction band spike above the bulk conduction band on the p side. It should be clear from this discussion that a large conduction band discon­ tinuity is definitely undesirable in the HBT. One of the principal aims of HBT technology and design has therefore been the reduction of the conduc­ tion band discontinuity. With the (Al, Ga)As - GaAs system, this calls for the use of a graded rather than an abrupt transition between the two semicon­ ductors, and much of the recent work on HBT technology centers around this grading problem [45]. An alternate approach would be the use of a different semiconductor pair with a band lineup that exhibits a smaller conduction band offset and a larger valence band offset. This calls for a semiconductor pair with two different anions. Specifically, the use of Ga0 5In0 5P in lieu of (Al, Ga)As has been proposed [45] as a lattice-matched partner for GaAs. The HAO theory predicts the band offsets Aec = 0.16 eV and Δ€ν = 0.29 eV for this system, much more favorable than the 0.85 Aeg and 0.15 Aeg values in the (Al, Ga)As-GaAs system. However, at the time these lines are written no (Ga, In)P-GaAs HBT has been reported yet. Most writers who have addressed themselves to the problem of HBT emitter design (including this one) have expressed the opinion that the retention of some conduction band discontinuity at the emitter-base junc­ tion is desirable, to act as a ballistic launching ramp that injects the electrons into the base with a high velocity [45,46], thus providing a faster transport through the base, which may in turn be traded off for a thicker base region with a highly desirable lower base resistance [45]. But there exists a consider­ able diversity of opinion about exactly what step height is optimal. This author, as well as Capasso et al [47], have advocated a very small step (< 0.1 eV) combined with a continuously graded base region as preferable over a large step combined with a uniform gap base region. One extreme case of a ballistic launching ramp would be the so-called Auger transistor, discussed in the 1960s by Kroemer [48] (published descrip­ tion is found in Milnes and Feucht [3, pp. 28-29]). When the conduction band spike height exceeds the energy gap in the base of the transistor (Fig. 10), carrier multiplication can occur, potentially leading to transistors with thyristorlike switching characteristics. The idea has apparently not been reduced to practice yet, largely for lack of a technologically practical semi­ conductor pair with the appropriate energy gap and band offsets. From the

152

Herbert Kroemer

Equal energies

rlnjected

electron

-Auger electron

Emitter bias

Fig. 10. Auger transistor. When the conduction band offset step exceeds the energy gap in the base of a heteroj unction bipolar transistor, some of the electrons will generate secondaries, leading to a net current amplification. (From Kroemer [48].)

HAO theory it appears that the AlSb-GaSb system might have the desired property: Aec = 0.87 eV > eg(GaSb) = 0.73 eV. It remains to be seen what will come of this. The idea of using heteroj unction band offsets to achieve carrier multipli­ cation has recently been carried further by Williams et al [49] who have proposed a marvelously ingenious low-noise solid state photomultiplier based on it. Inasmuch as this application lies outside the current mainstream of VLSI technology, the interested reader is referred to the original paper. 2. The C-V Relationship of an Abrupt p-n Heterojunction

The voltage dependence of the capacitance of an abrupt/?-« heterojunc­ tion contains information about the band lineup and about any interface charges that might be present. If the doping level on each side of the junction is uniform with position, a plot of 1/C2 versus the reverse bias Fapp forms a straight line, with a slope that depends on the doping levels on both sides, and an intercept with the voltage axis that depends on the band lineup and any interface charge. The changes compared to a p-n homojunction are subtle and purely quantitative. The measurement, however, is of a quite funda­ mental nature for the elucidation of the band diagram of heteroj unctions [1-3], and it has been used sufficiently often for this purpose that a detailed discussion is in order.

153

4. Heterostructure Band Discontinuities

The capacitance of a p - n heteroj unction may be viewed as two depletionlayer capacitances in series, one for the n side and one for the p side; hence 1/C = (1/C„) + ( 1 / Q ,

(38)

where Cn = Kn/wn9

(39)

CP = KP/WP.

Here κη and κρ are the permittivities of the two semiconductors, and wn and wp are the (effective) widths of the depletion layers on the two sides. From Eqs. (38) and (39),

1 K)VK) 2 + 2M, 2

C

\KJ

\KP)

( 40)

κηκρ

The two depletion-layer thicknesses are not independent; electrical neutral­ ity requires that NAwp-NOwn

= a,

(41)

where σ is the number of any interface charges per unit area. From Eq. (41) o2 = (NOwn)2 + (NAwp)2 - 2NONAwnwp.

(42)

We divide this relationship by κηκρΝΌΝΑ and subtract it from Eq. (40). The result may, after some rearrangement, be written ±2 = ^ + ^ / _ 1 _ + _ Ι _ \ _ σ2 C \ κη κρ )\κηΝΏ KpNJ κηκρΝΌΝΑ We next assume that the potential drops on both sides are sufficiently large that the free charges near the interface have been essentially fully depleted on both sides. In this case we can express wn and wp in a form analogous to Eq. (25) wl = (2Kn/qNO){ Vn - kT/q\

(44a)

wj = (2Kp/gNA)( Vp - kT/q).

(44b)

Here Vn and Vp are the electrostatic potential drops within each depletion layer, both counted positively. If Eq. (44) is inserted into Eq. (43), the result may be further rearranged to read

_L = 2 / _ i _

+ _L_)(V

+ v.2kr_

\

where Va = qa2/(K„ND + KPNA).

(46)

154

Herbert Kroemer

The sum Vn + Vp contains any externally applied bias voltage; we may write Vn+V^V^+Vv,

(47)

where Krev is the applied reverse bias voltage (counted as a positive voltage), and Vbi is the built-in voltage, defined as the value of Vn + Vp in the absence of any external bias. In a homojunction, Vhi is well known to be given by QVH = *g-kT

ln(NcNJNDNA).

(48)

Elementary inspection of the energy band diagram shows that in a heterojunction this result must be replaced by qVhi = €gp + Aec[p ^n]-kT

ln(NcnNJNONA\

(49)

where egp is the energy gap on the p side, and Aec[p —> n] is counted positively if the conduction band step is upwards in going from the p side to the n side, as in Fig. 8. Putting it all together, we may finally write Eq. (45) as

v-\{ik+-èòir-"+r'A

> F(O),where L is the gate length, then yo must be sufficientlyclose to L that yo - L

(17)

where ψ^ is given by Eq. ( 12) and ψ\ represents the additional contribution. The nonspherical contributions are not calculated from first principles. In­ stead, the treatments of fluid dynamics are followed with \dV\

, dV{

2dV\s

1

where it is noted that

Ì>f = 0.

(19)

In one dimension (along x) 4

dVx,

*" — 3»-*t-

(20)

243

6. Role of Boundary Conditions in GaAs Structures

In two dimensions, the derivative of the stress tensor is — ^/-i|(

μ^-

οχ2

+

J4d2vy

Γ +J (

θχ2

+ dxdy

, d2vx , d2vy + +

l ^43"^ ^

3dxdy\

2θ2κ*~Π

^^"3Ä^Jj·

(21)

In the discussion below, an even simpler version of Eq. (21 ) is assumed:

with the constraint Eq. (15) only approximately satisfied. Thus, the relevant equation for momentum balance is à >i à hk\ ., . , δφ d Ί ^ — nx1nk\1 = —n nk\ + enl x~^n k T dt dXi m lx 1 dxj dxj 1 Bx B1 x ßxhd2k{ +3ΤΓ-"ι^Γ mx dxj

3

.

(23)

For the L valley, the relevant momentum balance equation is d , w7 — (w - w ^ i = at

d hk2/ v,, ■ , , A4 (« - nx)hkJ2 + e(« - nxx) — dxi m2 oXj

-(n-nx)hk{r4.

(24)

The third and final pair of balance equations is that associated with energy transport. Straightforward application of the moment equations yields d TT, à hk{Trr , hk{d(f) ^wi = - -Wx + nxe—~-dt dxj mx mx dxj -nxUxr5 + (n-nx)U2r6,

d hk\ .. d „ . ι ι ψ {-^—Fh

(35)

FIELD

LJ Q

DISTANCE

x

Fig. 7. (a) Current-field relationship in Fig. 6a but for a different set of n0Vc and ncVc curves, (b) Schematic of possible cathode adjacent depletion and accumulation followed by broad accumulation for the two bias levels of Fig. 7a.

6. Role of Boundary Conditions in GaAs Structures

253

n0> nc. For a specific distance between the upstream boundary and the interior of the structure, a range of charge depletion forms, as sketched in Fig. 6b. Consider next the higher-current case C2. For this situation n0Vc(Fc).

/

IOkV/cm 1.6

1833 p s e c ^ / ■

. /

/

.·· ■

.·■

' . . . ■ ■

0.8

,y^ 0

0

1

1

1

0.2

0.4

0.6

DISTANCE/1.0/im Fig. 16.

(Continued)

1 0.8

1.0

266

H. L. Grubin and J. P. Kreskovsky

1.5

(a)

1.0 -0.094 psec 0.5

o.o

-0.5

-1.0

1

1

0.0 0.2 0.4 0.6 0.8 1.0 Fig. 17. (a) and (b) Displacement current at 5 instants of time for the parameters of Fig. 15. Initial displacement currents are strong and accompany the moving accumulation layer. J0 = 8X 104A/cm2

6. Role of Boundary Conditions in GaAs Structures

267

1.5

(b)

1.0

0.5

8.810 psec 0.0 1.833 psec

.1 J

-0.5

_,.0 I 0.0

1 0.2

1 0.4

1 0.6

DISTANCE/I.O/im

Fig. 17. (Continued)

1 0.8

1 1.0

268

H. L. Grubin and J. P. Kreskovsky

25 (a)

2.0

1.5

rJ\ A \ /—

0.094 psec

KM Γ VM

V ^

^ Λ

1.0 h

.

/ — 0 . 2 5 0 psec — 0.465 psec

0.5

1

1

1

1

1

0 0.2 0.4 0.6 0.8 1.0 Fig. 18. (a) and (b) Transient distribution of total charge following application of a step change in potential for the parameters of Fig. 15. Note that downstream from the propagating accumulation layer the charge distribution isflatas reflected, additionally in theflatfieldprofile of Fig. 16a. Space charge accumulation occurs during the longer time interval.

269

6. Role of Boundary Conditions in GaAs Structures

2.5 (b)

2.0

1.5

k·· V.

1.833 psec

8.810 psec

1.0

0.5 h

J 0.2

I 0.4

I 0.6

D I S T A N C E / I . 0 μπ\

Fig. 18.

(Continued)

L 0.8

1.0

270

H. L. Grubin and J. P. Kreskovsky

o.o 0.0 0.2 0.4 0.6 0.8 1.0 Fig. 19. (a) and (b) Transient distribution of Γ-valley carrier density for the parameters of Fig. 15. Note that within the first 0.5 psec, very little transfer occurs.

271

6. Role of Boundary Conditions in GaAs Structures

2.5

(b)

2.0

1.5

fe \.

V. I.0

« — Χ ^ -

- ^

J?

/.^

~^um) Fig. 52. Distribution of Γ-valley electron temperature for the three structures A, B, and C. Electron temperature distribution is qualitatively different for structure A. A longer down­ stream « + region is needed before the temperature approaches 300 K.

314

H. L. Grubin and J. P. Kreskovsky 4.0

o.oo

0.25

0.50

0.75

I.00

DISTANCE, {pm)

Fig. 53. Steady state distribution of electricfieldfor the three structures A, B, and C. Note that for structure A, a large residual field remains across the downstream N+ layer.

level associated with the variable rr region. Within these regions and at a bias of 1 V, the potential is calculated self-consistently and is displayed in Fig. 48. It is noted that for rr regions of length 0.266 and 0.416 μιη, most of the potential drop is across the rr region. For the smallest region a substantial potential drop falls across the n+ region. The origins of this enhanced poten­ tial drop may be found in examining the self-consistently computed charge distribution (Fig. 49) which shows the presence of an excess charge accumu­ lation at the downstream n~-n+ interface, resulting in a change in sign of the curvature of the potential. The distribution of Γ-valley carriers is displayed in Fig. 50, where the presence of a substantial electron transfer in the n+ region is noted. The carrier velocity (Fig. 51) and electron temperature (Fig. 52) within the Γ valley display the expected increases for the shorter n~ region. The electricfielddistribution, shown in Fig. 53, displays higher field values within the n+ region. The significance of the preceding result is that while variations in the total charge density tend to screen variations in the doping profile of the structure, the potential drop across the n~ region may be small enough to allow a substantial drop across the downstream n+ regions thereby permitting elec­ tron transfer to occur away from the n~ region. This, of course, is not

6. Role of Boundary Conditions in GaAs Structures

315

unexpected. It is implicit in the design of Gunn oscillators with doping variations assigned the task of domain nucleation sites. The current-voltage characteristics, therefore, are expected to reflect a complex set of electrical phenomena. Figure 54 displays a series of current-versus-voltage curves for n+-n~-n+ structures with the indicated n~ region length. Each curve displays J/JTe{ versus φ/φ^. The / ref is the computed value of current at 0 ref = 0.25 V. The valued Jre{ is indicated in thefigurecaption. Because of the intuitive relation­ ship between the space charge injection properties of the submicrometer n+-n~-n+ structure and those associated with Child's law, a power law ]αφ* was extracted. Note that JKf increases as the n~ region decreases in length. At low bias levels the current-voltage relationship appears to follow a power J=*L7

/

, J = φ' -5

/ / /

L

/ / / *

/ > ^ ^ Q

N

J

=

0.416/xm,

rer°-259jr

l_N = 0.266 p ,

/ Λ ^

Jref·-

J/y

0669j

r

y/ò-φ

l· ^~7~*

*

Jref= 3 ' 52J r

" /

r

i

l_N - 0.1 l6^Lin,

1

i

,

1

1

Fig. 54. Steady state current-voltage characteristics for the three structures A, B, and C. The current level for structure A is higher than that of B which in turn is higher than C. Note that the low-field resistance of structure A is the lowest of the three. Also included for reference are the Child's law / = φι 7, J= φ1·5, and J= φ curves. J4 = 1.6 X 104 A/cm2; 0 ref = 0.25 V.

316

H. L. Grubin and J. P. Kreskovsky

relationship that is slightly less than J/Jref = (φ/φτ^)γ with y = 1.7 (as com­ pared to a Child's law relationship where y = 1.5). At higher values of bias there is enhanced sublinearity in the current-voltage relationship, due in part to electron transfer to the satellite valleys. As indicated above, a considerable amount of electron transfer occurs in the downstream portion of the n+ region when the n~~ region is decreased in length. Indeed, the detailed calculations indicate that the relative amount of electron transfer increases as the n~ region decreases in length. At first glance, this result appears to contradict all that has been discussed about transport in submicrometer devices. But it is not unusual when it is realized that as the n~ region decreases in length a greater fraction of the voltage drop falls across the n+ regions of the device. It is this latter feature that is responsi­ ble for the enhanced transfer. To place this in different terms, the active region length of the device increases as the n~ region becomes insignificantly small.

IV. Conclusions

The major technological interest in transient transport arises from the predictions of unusually high mean carrier velocities. The initial discussions of these high velocity values was for uniform space charge distributions, but the results were thought to be relevant for those situations where the mean carrier energy was insufficient to lead to substantial electron transfer in gallium arsenide. Thus the trend developed toward submicrometer-scale devices. The complication that arises in submicrometer devices is that the boundary conditions will be the determinant as to whether high velocities will be attained. Additionally, the constraints of current continuity dictate whether high velocities will be accompanied by high carrier densities. For example, in the case of injecting contacts the velocity of the entering carriers was significantly below that within the interior of the semiconductor. The situation was reversed for the case of partially blocking contact conditions. Several critical results emerged from the discussion: (1) Transient over­ shoot in submicrometer structures reflects the presence of velocity overshoot and displacement current effects. It is not possible, in a simple way, to separate the two, with the result that transient measurements of overshoot require extreme care in interpretation. (2) Relaxation times to steady state are dominated by the dominating boundary; e.g., either the metal contact or the critical interface. Relaxation times do not scale linearly with device length. The relaxation time scales monotonically with length. (3) Transient overshoot effects are dependent upon rise times and the time for relevant field rearrangement within the structure.

6. Role of Boundary Conditions in GaAs Structures

317

ACKNOWLEDGMENTS The authors benefited greatly from many discussions with their colleagues, particularly, G. J. lafrate, D. K. Ferry, K. Hess, R. F. Greene, M. Silver, and M. P. Shaw. This work was supported by ONR and DARPA to whom the authors are grateful.

REFERENCES 1. K. Hess and G. J. lafrate in "VLSI Electronics" (N. G. Einspruch, ed.). Vol. 9, Chapter 6, Academic Press, New York, 2. M. P. Shaw, P. R. Solomon, and H. L. Grubin, IBM J. Res. Dev. 13, 587 (1969). 3. H. L. Grubin, IEEE Trans. Electron. Devices ED-25, 511 (1978). 4. A. Zur, T. C. McGill, and D. L. Smith, Surf. Sci. 132, 456 (1983). 5. A.W. DeGroot, G. C. McGonigal, D. J. Thomson, and H. C. Card, /. Appi. Phys. 55,312 (1984). 6. M. P. Shaw, P. R. Solomon, and H. L. Grubin, 'The Gunn Hilsum Effect." Academic Press, New York, 1979. 7. A. Sommerfield, "Thermodynamics and Statistical Mechanics." Academic Press, New York, 1956. 8. J. G. Ruch, IEEE Trans. Electron. Devices ED-19, 652 (1972). 9. H. Kroemer, IEEE Trans. Electron. Devices, ED-15, 819 (1968). 10. H. L. Grubin, D. K. Ferry, G. J. lafrate, and J. Berker, in "VISI Electronics" (N. G. Einspruch, ed.), Vol. 3, p. 198. Academic Press, New York, 1982. 11. K. W. Gray, J. Pattison, H. D. Rees, B. A. Prew, R. C. Clarke, and L. D. Irving, Proc. Bienn. Cornell Univ. Conf., 5th 215 (1975). 12. H. L. Grubin, and J. P. Kreskovsky, Surf. Sci. 132, 594 (1983). 13. H. L. Grubin, and J. P. Kreskovsky. J. Vac. Sci. Technol. (in press). 14. R. K. Cook, and J. Frey, IEEE Trans. Electron. Devices ED-28, 951 (1981). 15. K. Tomizawa, Y. Aweno, N. Hashizume, M. Kawashima, IEEE Proc. 129, 131 (1982). 16. J. R. East, and P. A. Blakey, Phys. Submicron Struct. Proc. 1982 Workshop (H. L. Grubin, ed.) p. 287. Plenum, New York, 1984.

APPENDIX. DIMENSIONLESS EQUATIONS USED IN THE NUMERICAL SIMULATIONS The continuity equations in dimensionless form are as follows: (i)

Equation (3): dn* _ dt*

(ii)

dn*V*j dxf

n

*f\ + (w* ~~ n*)fi-

Equation (5): dn* _ dt* ~

d

F 7+ n * ~;n^* * ( * " n*)v*J\ dx?

318

H. L. Grubin and J. P. Kreskovsky

The dimensional terms are identified in the following tabulation: nr = nl/nat,

V*X = VJVK{,

n* = n/nK{,

V^=V2/Vtef,

J\

=

y 2 = r 2 /r r e f ,

Γι/ΓΓβΓ,

X = X/.Xref,

t

=

t/tTe{,

with ^ref

=

χ

κΐ/

K-ef >

rref = 1 /Îref.

The momentum balance equations in dimensionless form are as follows: (i) Equation (23): dnfV? __dn*V?Vf dt* dxf 4-

+ pfr±dr_

m* dxf

l__à_n*R*T* yM2 dxf

_tf d2Vf μι 1 — n*V*if Re ·ra*dx]

(ii) Equation (24): * * m* dx* 1 d :(n*-nì)R%T% yM2 dxf ' Re · m*

to*2

1/2^4

The dimensionless terms and parameters are identified in the following tabulation: Φ* = ΦΐΦτ^ m* = ml /mref,

m\ = m2/mTe{,

R1 = kB/ml9

R2 = kB/rn2,

^ref

=

^ß/ m ref>

Rf = Rl /RTef = —,

i?? = R2/Rref = —* ,

J3= *3/rref,

y 4 = r 4 /r r e f ,

ß*=fil/fiicf>

ß*=ßllhref?

6. Role of Boundary Conditions in GaAs Structures

319

with Pf= βφ,α/η^νΐα, Re =

M = VTJ Va,

xK{VKinn{mTJfiTe{.

The energy balance equations in dimensionless form are as follows: (i) Equation (30): dntT*_ dt*

dntTtV? dxf

un*T*dV*J >l ' dxf

u

I

-km-^

Χτ^Γ U r - ^ T dx

- «,Γ,/, + ί « -

1

!— Re-Prmfc* ni)T2f6

V*jy*j

+ γ(γ - 1 ) Μ 2 - ^ [ 2 « * / 3 - «*/, + (n* - n*)/ 2 ]. (ii) Equation (31): d(n*-nt)TÎ_

„*\τ*ονί'

d(n*-nrmv? +

J

!

d

-(K*d-IÏ\

Te - Pr m%c*2 dxf

\

2

dxf )

vvw X [2(w* - Λ *)/ 4 + n*fx - (/ι* - n*)f2] - ( * * - * ? ) Γ2*/7 + /2*Γ*/8. The dimensionless terms and parameters are identified in the following tabulation:

/s ~ r 5 /r ref , /7 = r 7 /r ref ,

f6 = r 6 /r ref , fs = r 8 /r ref ,

CVx = i-R i ,

Q 2 = fi? 2 ,

^t>, ^r ~

^l'^tta' Qrefi^ref/^ref ·

^^2

^2'Wef'

Qref = l^ ref ,

320

H. L. Grubin and J. P. Kreskovsky

Poisson's equation in dimensionless form: (i) Equation ( 1 ):

ο2φ* dxf2

= Sn[n* + (n* — n*) — n*].

The dimensionless terms and parameters are 0ref^

«ref

The boundary conditions in dimensionless form are: (i) Equation (32): dn* _ dn* _ dV* _ dV* _ dT* _ dT* =0 dx* dx* dx* dx* dx* dx* at

JC = 0,

φ* = 0,

x = L,

φ* = φα.

(ii) Equation (40): dx*2

dx2

U

l

'

dV*

^

μ

Mc

< dx*'

xK{Vj

dT*

= 0,

Γ,-ΓΛ

^

= 0,

*« = 0.

(iii) Equation (41): d2n* = d2nfL = PV* L =&V* £ =d2T*L =&Τ* 2- =η 0 άχ*2 θχ*2 dx*2 θχ*2 dx*2

1 6

° 0.1

Ï.0

10.0

TANGENTIAL FIELD ( V / ^ m )

Fig. 2. Electron and hole drift velocities versus tangential field in Si(100) resistive gate MOSFETs at room temperature. Direction of transport was not specified. (After Coen and Müller [9]).

7. Carrier Transport at the Si-Si0 2 Interface

333

a resistive gate with electrical contacts at each end. By applying appropriate potentials to the source, the drain, and the two gate contacts, a uniform channel could be established. Their results, shown in Fig. 2, agree generally with those of earlier workers for electrons but yield significantly lower ve­ locities for holes, indicating a saturation velocity around 2 X 106 cm/sec. Taking a somewhat different approach, Müller and Eisele [10] reanalyzed data obtained from ordinary MOS transistors using an empirical velocityfield expression in an attempt to account for variations in electric field and carrier density along the channel. Although they were unable to accurately associate corrected velocities with particular values of electric field, the ve­ locity values that they obtained rose well above 6 X 106 cm/sec at high tangential fields, and appeared to saturate at around 8.6 X 106 cm/sec. In a numerical experiment using a two-dimensional computer simulation of the MOSFET, Yamaguchi [12] reexamined the original experiment of Fang and Fowler [7] and concluded that their low velocity values were the result of the nonuniformity of the conditions along the channel. Using a velocity-field relationship scaled from the bulk curve, in which the satura­ tion velocity of 1.04 X 107 cm/sec was assumed, Yamaguchi calculated the terminal currents and voltages of the MOSFET and, following Fang and Fowler's data reduction procedure, was able to duplicate their velocity-field data. Thus Yamaguchi concluded that their results were consistent with a saturation velocity near 1 X 107 cm/sec. B. Time-of-Flight Technique

Several of the problems associated with the conductance technique are avoided by a procedure in which the drift velocity is observed directly. This is the time-of-flight technique, first applied to the study of interface transport by Cooper and Nelson [13] in 1980. In this technique [14], a uniform tangential field is established along the interface by an appropriately biased resistive gate. No source difusion is used, and instead packets of electrons are created at the interface by optical excitation using a picosecond laser. The experimental device, shown in Fig. 3, is an MOS gate-controlled diode biased into deep depletion so that an equilibrium inversion layer cannot form. The optical excitation creates a localized cloud of holes and electrons at the interface. The holes are driven into the substrate by the normal electric field from the gate, giving rise to a current in the substrate. The electrons remain at the surface, where they can be thought of as a localized inversion layer. The electron packet drifts toward the drain in the uniform tangential electric field and produces a current pulse in the external circuit as it enters the drain. In operation, electron packets are injected at two points in the

334

J. A. Cooper, Jr., D. F. Nelson, S. A. Schwarz, and K. K. Thornber V,

■■©*—r

Fig. 3. Schematic cross section of the MOS gate-controlled diode used for time-of-flight measurements of surface electron velocity.

channel, as defined by optical apertures in the metal level, and the difference in arrival times is used to determine the drift velocity at each field. By suitable adjustment of bias voltages Vx and V2i the normal and tangential fields can be independently varied. The transport of a discrete charge packet along the interface differs in several fundamental ways from transport in either an MOS transistor or a bulk time-of-flight device. One interesting property of such transport is that the packet broadens owing to self-induced fields (i.e., mutual repulsion) and that over wide ranges of the normalfield,tangentialfield,and charge density, the packet width increases as the cube root of time [15,16]. The nature of packet transport at the interface is discussed in more detail in Section V. Figure 4 shows electron and hole velocity [ 17] measured on silicon( 100) at room temperature as a function of normal field with tangential field as a parameter. Figure 5 shows low-field mobility as a function of normal field measured on an MOS transistor on the same wafer as the time-of-flight devices. The solid curves in bothfiguresrepresent the best least-squaresfitto both mobility and velocity data using an empirical modeling equation given in Table I. The electron saturation velocity is estimated by extrapolation of the fitting equations to be 9.23 X 106 cm/sec, a value within 10% of the accepted bulk value. The hole data does not show evidence of velocity saturation up to the highest tangentialfieldsmeasured (3 V/μηι). Thus, it is not possible to deter-

7. Carrier Transport at the Si-Si0 2 Interface

Ό

335

5 IO 15 20 EFFECTIVE NORMAL FIELD {V/μΠλ) Fig. 4. (a) Measured velocity of electrons on silicon (100) at room temperature. Charge transport is along the [Oil] direction. The doping density was 1.2 X 1014/cm3 (boron), the oxide thickness 99 nm, and the density of oxidefixedcharge 3.5 X 1010/cm2. The solid curves are the bestfitto the data using Table I as described in the text, (b) Measured velocity of holes drifting in the [Oil] direction on a Si - Si02 ( 100) interface at room temperature. The substrate doping was 3 X 1014/cm3 (arsenic), the oxide thickness 98 nm, and the density of oxide fixed charge 2 X 1010/cm2. Curves represent equations and parameter values given in Table I. (Continued)

336

j . A. Cooper, Jr., D. F. Nelson, S. A. Schwarz, and K. K. Thornber

4 8 12 16 EFFECTIVE NORMAL FIELD (V//xiïi) Fig. 4b.

20

7. Carrier Transport at the Si-Si0 2 Interface

337

TABLE I Empirical Equations and Parameters Used for Fitting Data in Figs. 4 and 5 and for Plotting Fig. 6 Equations βΕχ

[\+(ßEjO%Y\l/a Mo

μ = \+(EJEcr

IOOO

"i

Parameter

Electrons

Holes

//0(cm2/Vsec) Ε0(ν/μτη) c vs (cm/sec) a

1105 30.5 0.657 9.23 X 106 1.92

342 15.4 0.617 1 X 10' 0.968

Γ

Ί

r

(a)

800

"E 600

o 400

200

0, 0

_L

_L

_L

50 10 20 30 40 EFFECTIVE NORMAL FIELD (V/μ,πη) Fig. 5. (a) Mobility as a function of effective normal field reported by Sabnis and Clemens [6] [O] and by Sun and Plummer [23] for electrons on silicon(lOO) (O, Na = 3 X 1014/cm3; · , Na = 1.3 X 1016/cm3) at room temperature, and data obtained from an MOS transistor on the time-of-flight wafer. The solid curve is the least-squaresfitfrom Table I to the mobility from the time-of-flight wafer (D). (b) Hole mobility versus effective normal field data obtained from an MOS transistor on the time-of-flight wafer. The curve represents the equation and parameter values given in Table I. (Continued)

338

J. A. Cooper, Jr., D. F. Nelson, S. A. Schwarz, and K. K. Thornber 500

(b) 400 CO

>

c^ 3 0 0 E o

>d

ω o

200

100

I

0 0

10 20 30 40 EFFECTIVE NORMAL FIELD ( V / > m )

50

Fig. 5b.

mine the saturation velocity for holes from the fit to the equations. In obtaining thefit,the saturation velocity was arbitrarily set to 1 X 107 cm/sec (the approximate bulk value [18]). The experimental data for electrons strongly suggests that the saturation velocity is independent of normal field, implying that for electrons at room temperature, γ(Εη) = 1; i.e., the momentum dependence of the scattering is unchanged by normal field. Of course, the scattering rates are influenced by normal field, as evidenced by the decrease in mobility. Figure 6 shows electron and hole velocities plotted as a function of tan­ gentialfieldwith normalfieldas a parameter. Also shown in thefigureare the data of Fang and Fowler [9] and of Coen and Müller [9]. The topmost data points represent velocity of electrons and holes [ 11,18] in bulk silicon. Here the discrepancies between the time-of-flight results and the results of the conductance technique are most apparent. The velocity-field relationships determined by the time-of-flight technique agree with the results of Fang and Fowler and of Coen and Müller only at the lowest values of tangential field. At higher fields, the drift velocity is found to approach the bulk curve, in agreement with the expectations of Yamaguchi and others. This result is further supported by recent estimates of electron saturation velocity ob­ tained by fitting short-channel MOSFET models to experimental data [19].

7. Carrier Transport at the Si-Si0 2 Interface

O.I

339

I 10 TANGENTIAL FIELD (V/^nn) Fig. 6. (a) Velocity versus tangentialfieldfor several normalfields.The curves are obtained from the model whose parameters are given in Table I; the solid portions indicate the regions where data were actually taken. Also shown are the data of Coen and Müller [9] (D, EN = 8.7; O, £ N = 12.7; · , EN = 24.2) and of Fang and Fowler [7] (■, £ N = 50.5) for electrons on silicon ( 100) (direction of transport unspecified in both cases), and the data of Canali et al. [lì] (Δ) for electrons traveling in the [Oil] direction in the bulk. The effective normalfieldsquoted for Coen and Muller and for Fang and Fowler have been recalculated from the original references using Eq. (25). (b) Hole drift velocity versus tangential field for several normalfieldscalculated from equations and parameter values given in Table I. Comparable data from Coen and Müller [9] (D, £ N = 6.5; · , £ N = 14.5; O, EN = 22.5) as well as bulk silicon data from Ottaviani et al. [ 18] (Δ) are also shown. (Continued)

340

J. A. Cooper, Jr., D. F. Nelson, S. A. Schwarz, and K. K. Thornber 10' (b)

/ΜΛ

o

Φ

////// '//

fll3

50

' / E N (v//im)

/

o o

_l

106

0.1

1

10

TANGENTIAL FIELD ( V / / x m ) Fig. 6b.

We have now considered the experimental methods used to study surface transport at high fields. Although the available data are still somewhat lim­ ited, the electron saturation velocity appears to be within 10% of the bulk value. Moreover, the saturation velocity appears to have no normal field dependence, and no significant variation with processing has been observed. This is in marked contrast to the situation at low tangentialfields,where the electron mobility is known to depend sensitively upon normalfield,fixed charge density, surface roughness, and temperature. In the next section we discuss these dependences in the context of a simple physical model of electron mobility. IV. A MODEL FOR ELECTRON VELOCITY IN SILICON

Accurate expressions for carrier velocity in silicon are required for device simulations but are generally of an empirical nature owing to the complexity of the transport process. The Scharfetter-Gummel expression [Eq. ( 17)] is a prime example. The scaling relationships of Section II provide a powerful tool for the extrapolation of such expressions with the physical parameters of

341

7. Carrier Transport at the Si-Si0 2 Interface

interest. One would, of course, prefer to have an accurate velocity expression derived from physical principles, thereby automatically obeying the scaling relationships. In this section we develop a simple physical model of electron velocity in silicon based on recent experimental and theoretical work. We may anticipate the utility of the model by examining Figs. 6 and 7. Figure 7 illustrates the variation of electron velocity with applied electric field in bulk Si. The solid curve is a plot of the Schaerfetter-Gummel formula [4] and the dashed curve is the prediction of the present model [20]. The Scharfetter-Gummel formula, even in its scaled form, cannot predict the variation of velocity with temperature. Figure 6 plots the empirical equation fit to Cooper and Nelson's time-of-flight velocity data from a Si MOSFET as a function of tangential field (proportional to drain voltage) with normal field (proportional to gate voltage) as a parameter. Figure 6 has several remarkable features. The apparent saturation velocity of electrons is close to the bulk value of 1 X 107 cm/sec. The velocity field profiles are sharper than their bulk counterpart; i.e., the knee of the curve is somewhat more pronounced. The low-field mobility is also observed to be lower at the surface than in the bulk. The present model [20] provides a good fit to this data and permits extrapolation of these experimental results to other temper­ atures and charge densities and into the subthreshold region as well. 1

o CD

1

1

1

I

'

i

'

'

20

C/)

\ E o

CO

o 10

n

—■

> H

8

o o

6

> \U_

4

_

2

-

_l LU

_Q

^

^*gpr^^~ c y * ^ ^ ^

1 i

J _|

yo

cr Q

z

o 1-

o LU

-

/

_l LU

|

1

0.1

1

1

1

1

i

1

i

i

i

10

ELECTRIC FIELD ( V / / i m )

Fig. 7. Electron velocity versusfieldat 300 K in bulk Si( 111 ). The present model ( ) is compared to the Scharfetter-Gummel equation ( ) and to data of Canali et al. (O) [11].

342

J. A. Cooper, Jr., D. F. Nelson, S. A. Schwarz, and K. K. Thornber

A. Bulk Velocity

Wefirstpresent a concise description of the model for electron velocity in bulk Si which will subsequently find use in the surface mobility model. The mobility μ is approximated as μ(Ε) = vJE = qr'/rn* = qV'/rn*v'

(26)

with these and subsequent parameters defined in the List of Symbols at the beginning of the chapter. We now make the crude assumption that the average electron energy is the sum of its zero-field thermal energy Eth and the drift energy \m*v\ such that (27)

^d·

Equations (26) and (27) may be solved simultaneously to yield the desired vd(E) equation with / as the remaining unknown. We define an acoustic scattering length /ac using Eq. (26) as 4c = rrPVtoMo/q,

(28)

and an optical phonon scattering length /op (i.e., the distance required to gain the optical phonon energy Eop) as lop = Eop/qE.

(29)

Assuming that an electron has a probability exp(—///ac) of traveling a dis­ tance greater than / without scattering and zero probability of traveling a distance greater than /op, we obtain /7/ac=l-exp(-/op//ac).

(30)

Equations (26), (27), and (30) yield the following expression for intrinsic silicon

which is plotted as the dashed curve in Fig. 7 (μ0 = 1400 cm2/Vsec). At high fields, Eq. (31) reduces to

-li-l·©

2

Ι1/2Ί 1/2

i

(32)

such that vs(T= OK) is (Eop/m*)1/2. A value of m* = 0.6 m0 is required to fit the data. This value is somewhat higher than expected due, in part, to the non-Maxwellian nature of scattering at highfieldsand to the neglect of other types of high-energy phonon scattering. In Fig. 8, vs is plotted (solid line) as a

7. Carrier Transport at the Si-Si0 2 Interface o ω

1

C.KJ

1—i—H

'

343 1—'—H

1

J

i

'—i—r

in

E

o

o 1.6 O

3 UJ

> -z. o

1.2

S 0.8 < o F 0.4 _J LU

1

i

U

i

i

ü

10

100 1000 TEMPERATURE (K) Fig. 8. Saturation velocity versus lattice temperature in bulk Si(l 11). The present model ( ) is compared to existing data and an empirical equation ( ) from Jacoboni et al. [21].

function of temperature using Eq. (32). A well-known empirical expression of Jacoboni et al [21] is also shown (dashed line). Equation (31) is seen to provide an excellent description of experimental data despite the simplifica­ tions inherent in the model. In extrinsic silicon we must account for diminished coulombic scattering of hot electrons at high fields. We do so by replacing μ0 in Eq. (31) by μ/Γ where Γ is a scaling factor derived in the following manner. A scattering radius may be defined by setting the potential q/es r equal to the hot electron energy \kTt. The coulombic scattering length l{ is inversely proportional to the scattering cross section nr2 and therefore varies as T\. If we employ Matthiessen's rule, that is, assume that scattering rates add such that

μ~ι = Σ^1

(33a)

n

or l//'=l/4c+l//i, it is easily shown that

(33b)

344

J. A. Cooper, Jr., D. F. Nelson, S. A. Schwarz, and K. K. Thornber

At low fields we may substitute Eq. (31) into Eq. (27) and solve for v' (proportional to T\12) to obtain

r e /r=l+(// 2 A4)£ 2 .

(35)

Indeed, this equation provides a good description of the low-field behavior as shown by Schwarz and Russek [20]. As a convenience, we may extrapolate Eq. (35) to higherfieldsin order to account for variations in temperature and doping, although the physical basis for such an extrapolation is dubious. A comparison of Eq. (35) to room temperature Monte Carlo predictions of Jacoboni et al [21] at various doping levels shows reasonable agreement. Reduced coulombic scattering at high fields results in a steeper rise of drift velocity with field as evidenced in the velocity data of Cook and Frey [22] (Fig. 9) from a silicon on sapphire sample. With no Te effect (Γ = 1) and μ = 250 cm2/V sec, curve (a) clearly underestimates the rapid rise in veloc­ ity. With Γ given by Eq. (34), however, curve (b) is obtained and provides

ELECTRIC FIELD ( V//im ) Fig. 9. Experimental velocity-field data of Cook and Frey [22] (O) from a silicon on sapphire sample at 300 K. Curves show the present model, with and without electron heating, and an assumed bulk mobility of 250 cm2/Vsec (a) Γ = 1; (b) Γ is given by Eq. 34.

7. Carrier Transport at the Si-Si0 2 Interface

345

better agreement with the data. The parameter Γ may be used to scale μ in any expression obeying Thornber's scaling rules. Equation (31) provides a good description of drift velocity in Si (111), where anisotropie effects are minimal. In Si(100) at highfields,electrons are preferentially transferred to the heavy longitudinal mass valleys. At room temperature this effect may be modeled by slightly increasing m*. Devia­ tions from the model worsen at low temperatures. Hole transport is moder­ ately well described by Eq. (31 ) with m* = m0 with some deviation resulting from the considerable valence band nonparabolicity [21]. B. Surface Velocity

The prediction of MOS device curents and voltages in any device model depends to first order on the assumed relationship for surface mobiliy. Pre­ vious attempts to develop a functional relationship for the surface mobility as it varies with doping, temperature, surface charge N{, and device voltages have been limited largely by insufficient or unreliable data. Recently, how­ ever, Sabnis and Clemens [6], Sun and Plummer [23], and Cooper and Nelson [14] have published consistent sets of data from electron mobility as it varies with the experimental parameters of interest. In each case, the authors plotted their results as a function of the effective normalfieldEn (i.e., the average field in the inversion layer directed perpendicularly to the SiSi0 2 interface) defined as En = {qles){NB + \n).

(36)

All parameters are defined in the List of Symbols. When plotted as a function of En9 the surface mobility is observed to be independent of the substrate doping level N or substrate bias voltage. Schwarz and Russek [20] have developed a semi-empirical model of surface mobility based on the experi­ mental papers just described and on various theoretical papers in the litera­ ture [24-26]. The chief innovation in this model is the use of a simple semiclassical approximation for the inversion layer thickness Z. The model is described briefly in this section. The classical inversion layer thickness ZCL is given approximately by [24] qEnZ^ = \m*v'* = lkTQ.

(37)

This equation implies that ZCL approaches zero at low temperatures or high fields—a result forbidden by quantum mechanics. A quantum mechanical 0 K inversion layer thickness ZQM may be readily obtained by solving Schrödinger's equation in a sawtooth potential [25] ZQM =

(9h2/4m*qEny\

(38)

346

J. A. Cooper, Jr., D. F. Nelson, S. A. Schwarz, and K. K. Thornber

(The same expression, within a constant factor, is obtained from a simple estimate using the uncertainly principle pZQM ~ h with p2/2rn* = qEn ZQM.) A useful approximation for the actual inversion layer thickness Z is simply Z = ZCL + ZQM.

(39)

This expression clearly has the correct limiting behavior at high and low fields and temperatures. A comparison with theoretical calculations of Stern [25] in Fig. 10 indicates good agreement with Eq. (39) for intermediate fields and temperatures. [The Si (100) longitudinal electron effective mass m* = 0.92 is used here.] We may estimate the mobility due to interfacial scattering/^ using Eq. (26) with a scattering length V = 2Z/p. The Fuch's factor p is the probability of diffusive scattering at the interface [26], as opposed to simply reflecting off the interface. We now employ Matthiessen's rule (after Many et al [27] and Greene [26]) and add the bulk scattering rate defined previously to the surface rate to obtain an expression for the net surface mobility //s, l/μ. = (Et/vd) + (pm*v'/2qZ), 1 0 0 I

1

1

1

1

1 I

I

I

I

I

1

(40)

1

1

1

I

I

i

1—j

1

i

10

l

l

100

EFFECTIVE NORMAL FIELD (V/jilTl)

Fig. 10. Stern's theoretical calculation ( ) [25] of inversion layer width versus effective normalfieldin lightly doped Si( 100) compared to the predictions of the present model ( ) at 2, 77, and 300 K.

347

7. Carrier Transport at the S i - S i 0 2 Interface

with vd defined in Eq. (31). It is interesting to note that with p = 1 and Z = Z CL , Eq. (40) is in close numerical agreement with the erfc expression derived by Schrieffer [24], as demonstrated by Das [28]. In typical MOS devices, however, p is on the order of 0.1. Least-square fits to several sets of data were used to obtain values for//0 in Eq. (31 ) and p as functions of T and N{. At 300 K, μ0 consistently fell in the range of 1100-1150 cm2/V sec for inversion and accumulation data. A T~5/2 dependence of μ0 was also observed. This somewhat low value of μ0 may suggest additional scattering modes in the proximity of the interface. The datafitsyielded the following expression for the Fuchs scattering factor: p = 0.09 r 3 / 2 + 1.5 X

\Q-\n/Z)-x'Ar~'N{.

(41)

The first term lumps surface roughness and surface phonon scattering to­ gether and increases with temperature. The second term is proportional to the fixed interfacial charge density Nf with a T~l dependence typical of screened coulombic scattering. The inversion layer charge density (n/Z) screening term is essential in modeling a perceptible change in the mobility profile shape above threshold as well as the sharp mobility drop below

>

\\J\J\J

^

r

1

1

i

1—

r-

1

1—

CM

E 900

—

o

>_l 0Q

o Έ -z. o tr 1-

o

Ld _l Ixl

cr

UJ

800

122X1015

N

700 1.3X10 1 6 ^

600

>< _l

-z. o 500

_

CD (Z UJ

1.4X1017^^^

>

-z.

/inn

I

L

I

I

J

I

_ J ^2 L I

I

100 10 EFFECTIVE NORMAL FIELD ( V//iim) Fig. 11. Inversion layer electron mobility data of Sun and Plummer [23] and their empirical fit ( ) for Si (100) at room temperature with four different substrate doping levels; , prediction of the present model.

348

J. A. Cooper, Jr., D. F. Nelson, S. A. Schwarz, and K. K. Thomber

threshold. For very low inversion layer charge n, p reaches its peak value of 1. The phonon and N{ terms in Eq. (41 ) are added on the basis of Matthiessen's rule. This semi-empirical expression is valid in the 270-430 K range, which is typical of MOS device operation. Figure 11 illustrates a comparison between this model and electron mobil­ ity data of Sun and Plummer [23] at four doping levels. The dip near thresh­ old for each set of data is accounted for by the screening term. Subthreshold behavior is illustrated by the mobility versus n data of Chen and Müller [29] at four temperatures in Fig. 12. The mobility drops off rapidly as n decreases and levels off (in this model, when p = 1). As En is decreased still further, bulk scattering dominates and the mobility approaches its bulk value. As N{ approaches zero, the dip in mobility becomes less pronounced, in good agreement with the predictions of Brews [30]. Although this modeol sup­ ports the importance of charge screening in the near-threshold region, it does not describe the activated temperature dependence of the mobility in the low n region. The carrier fluctuation models of Chen and Müller [29] and Brews [30] properly accounts or this behavior. Nevertheless, this model provides a

0'

IO 8

IO*

IO,u

IO"

IO" 1

IO1

INVERSION LAYER CARRIER CONCENTRATION ( Cm"2) Fig. 12. Subthreshold mobility data of Chen and Müller [29] for Si(100) with NA = 2.4 X 1016/cm3 and N{ = 2 X 10n/cm2 at four temperatures (D, 276 K; · , 296 K; 0,323 K; O, 346 K) as a function of inversion layer carrier concentration iV, ; ( ) prediction of the present model.

7. Carrier Transport at the Si-Si0 2 Interface

349

reasonable description of electron mobility in the transition from bulk to surface dominated transport. Finally, we examine the time-of-flight data of Cooper and Nelson [14], illustrated in Figs. 6 and 13. As mentioned previously, the curves in Fig. 6 are an empirical fit to the data of Fig. 13 and show sharper knees in comparison to their bulk counterparts. This sharpness was observed in Cook and Frey's [22] data (Fig. 9) to result from electron heating. Indeed, it is impossible to fit Cooper and Nelson's data without accounting for an electron heating effect. We used the following expression for T't which provides a good fit to the Monte Carlo prediction for /-Si of Jacoboni et al [21] T'e= 1 + EJIO4

V/cm.

(42)

However, adequate results are also obtained using Eq. (35) which, in addi­ tion, models the temperature dependence of T'e. It is thus possible to extrap­ olate this important set of data to other values of doping, temperature, and oxide fixed charge. 10 o to

E

o ω O

>O

o

_l LU

> o

tr i-

o

£ o CO

en

LU

>

20 10 EFFECTIVE NORMAL FIELD (V//im) Fig. 13. Time-of-flight electron velocity data of Cooper and Nelson for Si(100) at 300 K as fit by the model of Schwarz and Russek [20].

350

J. A. Cooper, Jr., D. F. Nelson, S. A. Schwarz, and K. K. Thornber

It must be recognized that these models are based on simplistic assump­ tions which neglect, for example, the complex phonon spectra, carriercarrier scattering, anisotropy, and non-Maxwellian behavior. This firstorder physical approach may nevertheless be extrapolated with some confidence over the 270-430 K temperature range. Application of this model to hole transport should be straightforward but awaits a more com­ plete set of data for mobility versus temperature and fixed charge. The physics of carrier transport in silicon is described in another chapter in this treatise [31].

V. CHARGE PACKET TRANSPORT AND BROADENING Both numerical simulations by computer and analytical studies of the transport process have aided the design, interpretation, and understanding of the experiments described in Section III. The approximate analytical theory, summarized in this section, has been particularly helpful in clarifying the meaning of the various velocities involved with the density distribution and with the flux. Its prediction of cube-root broadening, which followed that of Thornber et al. [15], provided a specific form for the broadening rate constant that has been tested experimentally. Those experiments [32] are also summarized in this section. A. Transport Equation

An approximate analytical understanding of the transport and broaden­ ing processes can be obtained through the use of the charge conservation law, ißn/dt) + (d/dx)(nv) = 0,

(43)

as the equation of motion. Here we use n as the one-dimensional carrier density (number/centimeter) in the drift channel and the contribution of diffusion to the flux is omitted as is appropriate to the experiments consid­ ered in Section III. The electric field that is tangential to the surface and drives the electrons has two origins: one externally applied and one self-generated by the charge packet. The tangential electric field is applied along the semiconductor sur­ face by a resistive gate separated from the semiconductor by a thin (^0.1μπή insulating layer (see Fig. 14). The closeness of the resistive gate to the semiconductor leads to the potential drop F along the gate of length L being impressed upon the surface of the semiconductor and so produces the field et = — V/L. In addition to this field, the charge packet itself produces a

351

7. Carrier Transport at the Si-Si0 2 Interface INSULATING LAYER RESISTIVE GATE

V=0

INJECTION

INJECTION

DRAIN JUNCTION

'ν////χ///////////////////)(/////λ

Fig. 14. Coordinate definitions for transport calculation. The positions xn, xf represent the density peaks of the injected charge packets at t = 0, and L is the drain position (and gate length).

tangential electric field [33] proportional to the spatial derivative of the density distribution, — (ql0/e0 wc) dn/dx, where /0 is the thickness of the insu­ lating oxide layer, e0 is the permittivity of the oxide, and wc is the lateral width of the channel (gate). This expression is valid in the gradual chanel approxi­ mation [33] and is accurate when /0 dn/dx 5 V. The self-generated normal field, which is just inside the semiconductor where the charges travel, in the grad­ ual channel approximation [33] is simply one-half the parallel plate capaci­ tancefieldqn/e0 wc in the oxide layer multiplied by e0/es (from continuity of normal elecrtric displacement). The factor of one-half, pointed out by Matsumoto and Uemura [34] and by Sabnis and Clemens [6], arises because the

352

J. A. Cooper, Jr., D. F. Nelson, S. A. Schwarz, and K. K. Thornber

self-generated field lines terminate on the charges of the packet itself such that the averagedfieldwith respect to the coordinate normal to the surface is one-half the total generated field. Thus the total normal electric field is En = ^nW +

qn 2eswc'

*H¥)

(45)

1/2

(46)

We now expand the drift velocity in a series about Et = et and En = En and use the Eqs. (44) and (45) to convert the drift velocity to a function of x, t needed for Eq. (43) v(Eu En) = v(eu Ën) + -^- (Εη - Ên) + f^{Ex-

ex\

(47)

where En is the average normal electric field thatis experienced during transit. Use of first-order expansions in En about En and in Et about the applied field et are justified provided the self-generated fields are small, which thus requires the charge packet density to be not too large. Velocity saturation is accounted for by different values of the coefficients in Eq. (47) for different values of et. Substitution of Eqs. (44) and (45) into Eq. (47) yields ν0-αη-β

where

—

-γβη(χ\

v(euËn)-Ën—, a

_ —q dv 2eswc ΘΕΏ En=En,Ex=ex

ql0 dv e0wc dEt En=En,Et=et _dv_ 7dE, En=En,Et=et

(48) (49) (50) (51) (52)

Introducing Eq. (48) into Eq. (43) gives the nonlinear partial differential equation characterizing the transport process,

353

7. Carrier Transport at the Si-Si0 2 Interface

B. Approximate Solution

An exact solution of Eq. (53) has not been found because of its nonlinearity. However, an approximate solution has been found that accounts for the drift of a charge packet with a time-dependent drift velocity due to a varying normal electricfieldand with a broadening that depends on the cube root of time. The solution does not account for the slow but progressive asymmetrization of the packet that is observed in computer simulations. For the packet sizes and drift times used in the experiments, however, asymmetrization is a small effect. The solution found for the density [16] is

«4 * - £ ( . -w*) I 2

when \ξ/\ν\ < 1 and zero otherwise. Here N is the number of charges in the packet, ξ the traveling coordinate (zero at the density peak) given by ξ = χ-χί-

*~i'o*I υ(τ)άτ,

(55)

where xt is the position of the density peak at / = 0, and w{t) the time-depen­ dent width function given by w{t) = BV\t + toy\

(56)

where t0 is the extrapolated time before t = 0 when the packet would have been a delta function and B is the broadening rate constant. The latter was predicted to be given by B = (9ql0N/2€0wc)(dv/dEt),

(57)

and the time dependent velocity v(t) is given by v(t) = v0 + -^r {En(np(t)) + en(jq + v0t)},

(58)

where np(t) is the peak charge density. The conservation law [ Eq. (43)] can be integrated with respect to x to yield the flux

jtf,t) = -jtf* ntf,t)dx

(59)

354

J. A. Cooper, Jr., D. F. Nelson, S. A. Schwarz, and K. K. Thomber

z

LU

Û

hLU

< LÜ

a: < x o

DRIFT CHANNEL

DISTANCE

Fig. 15. Comparison of the density distribution calculated numerically ( ) with that of the approximate analytical solution ( ). Calculations apply to N= 6.5 X 105 charges, t = 1.4 nsec, and an applied bias of 35 V on a 100-μπι gate.

The approximate analytical solution is compared in Figs. 15- 17 to the numerical solution of the conservation law [Eq. (43)] by utilizing the exper­ imentally found v(Et, En) function [not the first-order series expansion, Eq. (47)], the electricfieldexpressions [Eqs. (44) - (45)] and a realistic initializing condition (injection pulse of 125 psec FWHM distributed uniformly over a 10-//m-long aperture). The difference of the density curves in Fig. 15 results mainly from the omission of the asymmetrizing effect of the normal electric field in the approximate analytical solution. Figure 16 plots the numerical calculation of the packet width [full width at half maximum (FWHM) which is proportional to w(t) of Eq. (56)] versus time measured from the beginning of optical injection. A reshaping of the packet occurs in the first several hundred picoseconds before the width approaches the predicted cube-root dependence [ 15 - 16] on time of the approximate analytical solution. Figure 17 plots the position of the peak of the density distribution from the numeri­ cal calculation and from the approximate analytical solution. During the period of optical injection, the peak position does not move much, as ex­ pected in the numerical calculation. As the packet reshapes itself following the injection period, its peak position approaches that of the analytical solution. The velocity is seen to be nearly constant long after injection; this results from a tendency of the time dependence of the packet velocity from the depletion layer normal field (~r 1/2 ) to cancel that from the self-normal field of the packet (~ t~l/3). The numerical calculations lend credence to the approximate analytical solution for sizable transit times.

7. Carrier Transport at the Si-Si0 2 Interface

355

100

E

x

< < x < X

o Z> LL

TIME (nsec) Fig. 16. Numerical calculation of the charge packet broadening. Injection continues for -300 psec; the pulse reshapes for 1 nsec. At long times the slope (0.31) is very close to the predicted one-third of the approximate analytical solution. Calculations apply to conditions of Fig. 15.

C. Interpretation of Measured Velocity

The measured velocity, which is the difference in distances traveled di­ vided by the difference of arrival times of the flux peaks of two charge packets injected at different positions along the drift channel, differs from the drift velocity that is sought. We wish here to obtain the relationship between them. We denote the position of the flux peak at the moment of injection at the

356

J. A. Cooper, Jr., D. F. Nelson, S. A. Schwarz, and K. K. Thomber 200

1

160

-

F 120

-

^

1

I

1

1

y

/

ÜJ

c; -z.

< h-

co Q

80

40

// /

//

/

0

i

0

1

i

1

i

2

4 6 TIME (nsec) Fig. 17. Comparison of the position of the peak of the density distribution versus time calculated numerically ( ) with that from the analytical solution ( ). Calculations apply to conditions of Fig. 15.

(near, far) aperture as (χζ, xf ) and the drain position as L (see Fig. 14). By the above definition, the measured velocity is

vM =

[(L-xf)-(L-xl)]/(t{-tn).

(61)

Use of Eq. (55) with / = (n, f ) for the (near, far) apertures, x = L, and ξ = ξ*(ί) to indicate it refers to the flux peak position, leads to L - x f = £F(0-£F(0)+

υ(τ)άτ

(62)

Jo

Substitution of this in Eq. (61) for / = (n, f ) and t = (tn, t{) yields -

L

άξ*

vM = v + dt '

(63)

357

7. Carrier Transport at the Si-Si0 2 Interface

where the bar denotes the time average arising out of this substitution. It is given for an arbitrary function F by

f

F i

f