Silicon Analog Components: Device Design, Process Integration, Characterization, and Reliability [2nd ed. 2020] 978-3-030-15084-6, 978-3-030-15085-3

Table of contents :
Front Matter ....Pages i-xlix
The World Is Analog (Badih El-Kareh, Lou N. Hutter)....Pages 1-24
Review of Single-Crystal Silicon Properties (Badih El-Kareh, Lou N. Hutter)....Pages 25-63
PN Junctions (Badih El-Kareh, Lou N. Hutter)....Pages 65-111
Rectifying and Ohmic Contacts (Badih El-Kareh, Lou N. Hutter)....Pages 113-149
Bipolar and Junction Field-Effect Transistors (Badih El-Kareh, Lou N. Hutter)....Pages 151-219
Analog/RF CMOS (Badih El-Kareh, Lou N. Hutter)....Pages 221-306
High-Voltage and Power Transistors (Badih El-Kareh, Lou N. Hutter)....Pages 307-388
Passive Components (Badih El-Kareh, Lou N. Hutter)....Pages 389-446
Process Integration (Badih El-Kareh, Lou N. Hutter)....Pages 447-494
Mismatch and Noise (Badih El-Kareh, Lou N. Hutter)....Pages 495-538
Chip Reliability (Badih El-Kareh, Lou N. Hutter)....Pages 539-619
Back Matter ....Pages 621-648

Citation preview

Badih El-Kareh · Lou N. Hutter

Silicon Analog Components Device Design, Process Integration, Characterization, and Reliability Second Edition

Silicon Analog Components

Badih El-Kareh • Lou N. Hutter

Silicon Analog Components Device Design, Process Integration, Characterization, and Reliability Second Edition

Badih El-Kareh PIYE Cedar Park, TX, USA

Lou N. Hutter Lou Hutter Consulting Dallas, TX, USA

ISBN 978-3-030-15084-6 ISBN 978-3-030-15085-3 https://doi.org/10.1007/978-3-030-15085-3

(eBook)

Library of Congress Control Number: 2019935169 © Springer Nature Switzerland AG 2020 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors, and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Switzerland AG The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland

To my family: Itte-Dorothee, Oliver, Linda, Robert, and Kay B.E.K For my mother L.N.H

Foreword

I came home from work one night sometime in early 2001 and told my wife and kids that I had been promoted to run part of the analog business at Texas Instruments. Both my kids looked at me with an odd expression, then my son said, “Why would you want to be in anything analog—analog is dead and the world is going digital!” Well, he was both right and wrong. Computers have evolved significantly since their invention decades ago. They have moved from being specialized instruments housed in top secret rooms that only a few people knew how to use to being ubiquitous, handheld (or even implanted!) devices that nearly everyone uses on a daily basis, and hardly anyone can live without. The digitization of the world enabled this and has fostered the significant growth of many new markets. To make things digital, you have to first convert them from the “real world”—which of course is analog. And to do this, you need analog components. In fact, every time you make something more digital, you need to use even more analog to do that! Music is a great example. We have moved from records, to 8-track, to cassette, to CD, and now to MP3. It started off analog and progressively became more digital, and with MP3, you have a completely digital manifestation of music: searching for great songs, sampling them, buying them, storing them and listening to them—all done digitally. Yet the MP3 player has more analog content than its predecessors, and the record player had almost none. The analog business is the second largest segment of the semiconductor business and is arguably the most important. Analog chips are used in the widest variety of applications, and their performance—things such as signal-to-noise ratio (SNR), spurious free dynamic range (SFDR), and effective number of bits (ENOB)—can make or break the performance of a system. The analog market is also quite fragmented, with hundreds of thousands of different parts used by hundreds of thousands of customers in countless applications. It is a market that will continue to expand and will continue to provide great opportunities for those of you who study in this field.

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Foreword

I was once asked by a nontechnical friend to tell him the difference between analog and digital. What he knew about digital was that it was made up of a bunch of 1s and 0s and that analog was all about “squiggly lines.” Well, that made me think about how to answer that question. What I came up with was this: In the world, you care about two things: (1) Are you a 1 or a 0? and (2) How fast can you change from a 1 to a 0? In the digital world, you care only about the destination, and what happens in between is irrelevant. In the analog world, you care about what happens in the transition from being a 1 to a 0, or vice versa. You have to care, because what happens in that transition makes all the difference. You care as much about the journey as you do the destination—maybe even more so. That makes analog both difficult and exciting. Badih El-Kareh and Lou Hutter have written a book about an important topic— the world of analog design. They have simplified some of the circuit concepts to help clarify how to build great components that enable great analog chips. And hopefully, this will inspire you to pursue a career in the field, so even greater analog components can enable even more digital products that will continue to revolutionize the markets and create new markets for decades to come. I hope you enjoy the analog world as much as I do. Gregg Lowe CEO, CREE Durham, NC, USA

Preface to the Second Edition

In recent years, the focus on analog integrated circuits has become more pronounced due to their ubiquitous use in electronic products. This has placed more attention on analog process technologies. Whereas analog technology was once the exclusive domain of a small circle of integrated device manufacturers, it has proliferated to foundries worldwide and hence is available to all design houses. At the root of analog technologies are components—transistors, resistors, capacitors, inductors, and varactors—that embody the performance requirements of the analog products. This book was written for undergraduate electrical engineering students and for practicing engineers in the field of analog, power, and RF silicon integrated technologies. The level at which the book is written assumes that the reader has had introductory physics, calculus, statistics, and an undergraduate college level course on semiconductor devices. Its primary purpose is to provide a unified treatment of design, integration, and applications of analog components fabricated on silicon. Silicon is emphasized since this is the main material used in most analog, power, and RF technologies. There are several excellent books available on semiconductor physics, but few if any that have focused on the components and characteristics aimed at analog applications. The authors hope that this book constitutes a foundation, using device physics to help the reader get a deeper understanding of how the components function, and highlighting those salient attributes important for analog applications, with examples to reinforce key concepts and best practices. Overviews of selected product applications are presented, showing how these analog components are used, while avoiding complex circuit analysis. At the end of each chapter, problems are provided to test and stretch the reader’s understanding, and many references are listed, allowing the reader to delve deeper into the topics discussed. The book is based on years of experience by the authors in analog technology at both integrated device manufacturers and foundries; and on industrial and academic teaching. This includes direct experience in defining analog component specifications based on circuit performance and scaling requirements, integrating those components into an analog process technology, validating the reliability, then qualifying that technology and ramping it into production. ix

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Preface to the Second Edition

During the past 4 years, comments from our readers prompted a substantial review of each chapter, with corrections, modifications, and additions of new topics. The new sections added include SiGe and SiGe:C bipolar devices for use in highspeed and RF BiCMOS technologies, and mobility-enhancement techniques, FinFETs, and fully depleted SOI MOSFETs employed in advanced CMOS technologies where analog components are incorporated. The book is organized into 11 chapters and five appendices. Chapter 1 is an introduction to the “world is analog.” It provides an overview, framing the importance of analog products in everyday life. Chapters 2, 3, and 4 give a review of silicon properties, PN junctions, and rectifying and ohmic contacts, establishing the proper device physics background for the reader to move into the more analog-oriented components. While several excellent books on these topics have already been published, these chapters are intended to present engineers and scientists, in a concise form, those parts of semiconductor and device physics that are most important to the discussion of analog components. Chapter 5 covers fundamentals of bipolar junction transistors and junction fieldeffect transistors, which are constructed in a base CMOS technology with no or little added complexity. This is followed by a discussion of advanced bipolar transistors, leveraging SiGe and SiGe:C materials. The chapter also helps in understanding important bipolar effects in CMOS, such as subthreshold current, snapback, and latch-up. Chapter 6 deals with analog and RF CMOS components. The chapter includes a concise description of surface effects and the Metal-Oxide-Silicon (MOS) structure that is a key part of the MOSFET and a powerful device and process characterization tool. Both digital and analog/RF CMOS device topics are then covered. The modes of transistor operation and different transistor types are covered. Transistor currentvoltage characteristics are then detailed with an emphasis on analog applications. In addition, the analog attributes of mobility-enhancement techniques, FinFETs, and fully depleted SOI MOSFETs are discussed. High-voltage and power devices are presented in Chap. 7, focusing on DECMOS and LDMOS transistors. Concepts such as the drift region are covered, and key figures of merit such as specific on-resistance and gate charge are introduced, many of these areas leveraging concepts introduced in Chap. 6. High-voltage effects, such as quasi-saturation, impact ionization, self-heating, and safe operating area are detailed. Chapter 8 describes passive components, which are fundamental components in analog, mixed-signal, RF CMOS, and power applications. Device design and properties of integrated precision resistors, capacitors, varactors, and inductors are covered in detail, with examples of their use in circuit applications. Chapter 9 discusses process integration of active and passive analog components. This includes analog CMOS and BiCMOS, mixed-signal CMOS, RF CMOS, BCD technologies, and SiGe-base BJT. The description is illustrated with many cross sections, highlighting key technology features, trade-offs, and best practices.

Preface to the Second Edition

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Component matching and noise are parameters that can have critical importance in analog applications. They are covered in detail in Chap. 10 for both active and passive devices. Chapter 11 covers component reliability. Basic concepts, models, and distributions are introduced, highlighting their use for specific failure mechanisms and emphasizing analog reliability considerations. Practical examples are provided for illustration. Cedar Park, TX, USA Dallas, TX, USA

Badih El-Kareh Lou N. Hutter

Acknowledgments

The authors acknowledge the many individuals who helped make this book possible, and who improved it through their inputs, suggestions, patient review of chapters and their critique. We could not have written this book without their help. First and foremost, we acknowledge and thank Prof. Carlton Osburn, who tirelessly and meticulously read each chapter and provided invaluable advice throughout this endeavor. Jim Hellums patiently reviewed a number of topics across multiple chapters, providing valuable feedback, as did John Pigott, Marie Denison, John Krick, and Il-Yong Park. Additional thanks go to Dr. Constantin Bulucea, IEEE Life Fellow, for his comments and suggestions. We also acknowledge the following people who read and commented on several parts of the manuscript: Konrad Bach, Jonathan Brodsky, Steve Chaney, Wayne Chen, Sundar Chetlur, Claudio Contiero, Imelda Donnelly, Mark England, Randy Geiger, Sarma Gunturi, David Hannaman, Mark Harward, Alan Hastings, Alan Holden, Felicia James, Clif Jones, David Jones, Taek-Soo Kim, Lars Larsson, Mankoo Lee, Praful Madhani, Ken Maggio, Andrew Marshall, Joe McPherson, Alessandra Merlini, Daniele Merlini, Bill Nehrer, Andrea Paleari, Sameer Pendharkar, Marcel Pelgrom, Angelo Pinto, Wolfgang Ploss, Sam Shichijo, Howard Test, Jim Victory, and Pieter Vorenkamp. Finally, we express our thanks to the process development team at Dongbu HiTek for valuable discussions during the course of preparing the manuscript. Badih El-Kareh Lou N. Hutter

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Contents

1

2

The World Is Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 What’s Different About Analog . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 Digital Design Considerations . . . . . . . . . . . . . . . . . . . 1.2.2 Analog Design Considerations . . . . . . . . . . . . . . . . . . 1.2.3 Analog Technology and Manufacturing Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Integration or Not . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Analog Process Technologies . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.1 Mixed-Signal CMOS Technology . . . . . . . . . . . . . . . . 1.4.2 RF CMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . 1.4.3 RF BiCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.4 Analog CMOS Technology . . . . . . . . . . . . . . . . . . . . . 1.4.5 Bipolar-CMOS-DMOS (BCD) Technology . . . . . . . . . 1.4.6 Nonvolatile Memory . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Analog Technology Roadmaps . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9 12 14 14 16 16 18 19 20 21 22

Review of Single-Crystal Silicon Properties . . . . . . . . . . . . . . . . . . 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Crystal Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Energy Gap and Intrinsic Carrier Concentration . . . . . . . . . . . 2.3.1 Energy Band Model . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 The Boltzmann Distribution . . . . . . . . . . . . . . . . . . . 2.3.3 Fermi–Dirac Distribution and Density of States . . . . . 2.4 Doping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 Dopants from the Fifth Column: Donors . . . . . . . . . . 2.4.2 Dopants from the Third Column: Acceptors . . . . . . . . 2.4.3 Band Model for Impurities in Silicon . . . . . . . . . . . . .

25 25 25 27 28 30 31 34 34 35 37

. . . . . . . . . . .

1 1 3 3 5

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2.5

Carrier Transport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.1 Carrier Transport by Drift: Low Field . . . . . . . . . . . . 2.5.2 Carrier Transport by Drift: High Field . . . . . . . . . . . . 2.5.3 Carrier Transport by Diffusion . . . . . . . . . . . . . . . . . 2.5.4 Total Drift and Diffusion Current Density . . . . . . . . . 2.5.5 Nonuniform Doping Concentration . . . . . . . . . . . . . . 2.5.6 Einstein Relation . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Non-Equilibrium Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.1 Carrier Lifetime and Diffusion Length . . . . . . . . . . . . Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . .

41 42 48 50 51 52 53 54 54 61 62

3

PN Junctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Structure and Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Cylindrical and Spherical Approximations . . . . . . . . . . 3.3 Junction Characteristics at Thermal Equilibrium . . . . . . . . . . . . 3.3.1 Step Junction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Forward-Biased Junction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Effect of Series Resistances . . . . . . . . . . . . . . . . . . . . . 3.4.2 Effect of Surface Recombination . . . . . . . . . . . . . . . . . 3.5 Reverse-Biased Junction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Reverse Leakage Current . . . . . . . . . . . . . . . . . . . . . . 3.5.2 Impact Ionization and Avalanche Breakdown . . . . . . . . 3.5.3 Reverse Recovery Time . . . . . . . . . . . . . . . . . . . . . . . 3.6 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 Zener Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.2 PIN Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

65 65 65 69 69 70 81 84 87 88 90 94 97 100 100 104 107 110

4

Rectifying and Ohmic Contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Rectifying Contacts, Schottky Barrier Diode (SBD) . . . . . . . . . 4.2.1 Metal–Semiconductor Barriers . . . . . . . . . . . . . . . . . 4.2.2 Current–Voltage Characteristics . . . . . . . . . . . . . . . . 4.2.3 Schottky Barrier Diode Applications . . . . . . . . . . . . . 4.3 Ohmic Contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 Specific Contact Resistance . . . . . . . . . . . . . . . . . . . . Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . .

113 113 114 114 119 134 137 139 146 147

5

Bipolar and Junction Field-Effect Transistors . . . . . . . . . . . . . . . . 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Bipolar Junction Transistor (BJT) . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Idealized Structure . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . .

151 151 153 153

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5.2.2 NPN Transistor in a CMOS Technology . . . . . . . . . . 5.2.3 PNP Transistors in CMOS Technology . . . . . . . . . . . 5.2.4 Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.5 High-Performance Bipolar Transistor . . . . . . . . . . . . . 5.2.6 BJT Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Junction Field-Effect Transistor (JFET) . . . . . . . . . . . . . . . . . 5.3.1 Idealized Normally-On NJFET . . . . . . . . . . . . . . . . . 5.3.2 JFET in a CMOS Technology . . . . . . . . . . . . . . . . . . 5.3.3 JFET Applications . . . . . . . . . . . . . . . . . . . . . . . . . . Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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162 185 186 190 200 202 203 211 213 215 218

6

Analog/RF CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Review of MOS Properties . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 Flatband Condition . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 Accumulation and Depletion . . . . . . . . . . . . . . . . . . . 6.2.3 Weak and Strong Inversion . . . . . . . . . . . . . . . . . . . . 6.2.4 MOS C-V Technique . . . . . . . . . . . . . . . . . . . . . . . . 6.3 MOSFETs and CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 Review of MOSFETs, Long and Wide Channel . . . . . 6.3.2 Analog-Specific MOSFETs . . . . . . . . . . . . . . . . . . . . 6.3.3 Small-Size Effects . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Deep Submicron and Nanoscale MOSFETs . . . . . . . . . . . . . . 6.4.1 Mobility Enhancement Techniques . . . . . . . . . . . . . . 6.4.2 Ultrathin Oxide and High-κ Dielectrics . . . . . . . . . . . 6.4.3 FinFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.4 Fully Depleted SOI MOSFET . . . . . . . . . . . . . . . . . . 6.5 Analog CMOS Applications . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.1 Differential Amplifier . . . . . . . . . . . . . . . . . . . . . . . . 6.5.2 Current Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.3 Native NMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.4 Buried-Channel and Depletion-Mode MOSFETs . . . . Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . .

221 221 222 222 227 229 233 238 238 264 272 285 285 289 290 292 293 293 294 296 296 297 299

7

High-Voltage and Power Transistors . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 The Drift Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 On-State Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.1 On-Resistance, RDS(on) . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2 Specific On-Resistance, RSP . . . . . . . . . . . . . . . . . . . . 7.4 Off-State Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.1 A Simple One-Dimensional Analysis of BVDSS . . . . . . 7.4.2 Reduced Surface Field, RESURF . . . . . . . . . . . . . . . .

307 307 308 310 310 311 315 315 318

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7.5

8

Performance Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.1 Ideal RSP Versus BVDSS . . . . . . . . . . . . . . . . . . . . . . . 7.5.2 Switching Performance, RDS(on)
QG . . . . . . . . . . . . . 7.6 Design and Characteristics of DEMOS . . . . . . . . . . . . . . . . . . . 7.6.1 Complementary DEMOS . . . . . . . . . . . . . . . . . . . . . . 7.6.2 Field-Gap DENMOS . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.3 Subthreshold Current . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.4 Asymmetric and Symmetric DEMOS . . . . . . . . . . . . . 7.6.5 Dielectric RESURF . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.6 Key Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.7 Specific On-Resistance Versus Breakdown Voltage . . . 7.7 Design and Characteristics of LDMOS . . . . . . . . . . . . . . . . . . . 7.7.1 NLDMOS Configurations . . . . . . . . . . . . . . . . . . . . . . 7.7.2 PLDMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7.3 Laterally Graded Channel . . . . . . . . . . . . . . . . . . . . . . 7.7.4 The Superjunction Concept . . . . . . . . . . . . . . . . . . . . . 7.7.5 Key LDMOS Dimensions . . . . . . . . . . . . . . . . . . . . . . 7.7.6 SOI Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7.7 LDMOS Trade-Off Between RSP and BVDSS . . . . . . . . 7.8 High-Voltage and High-Current Effects . . . . . . . . . . . . . . . . . . 7.8.1 Quasi-saturation, QS . . . . . . . . . . . . . . . . . . . . . . . . . . 7.8.2 On-State Breakdown Voltage . . . . . . . . . . . . . . . . . . . 7.8.3 Self-Heating and Other Temperature Effects . . . . . . . . . 7.9 Safe Operating Area (SOA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9.1 Electrical SOA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9.2 Electrothermal SOA . . . . . . . . . . . . . . . . . . . . . . . . . . 7.10 Circuit Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.10.1 Half H-Bridge Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 7.10.2 H-Bridge Motor Driver: LDMOS Reverse Recovery . . . 7.10.3 DC–DC Converter: Switching Effects . . . . . . . . . . . . . 7.10.4 AC–DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

324 324 326 329 330 331 332 332 333 334 335 335 335 339 340 341 343 344 346 347 348 360 361 367 367 368 370 370 371 374 377 379 382

Passive Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.1 Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2 Polysilicon Resistor . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.3 Silicon Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.4 Thin-Film Resistors, TFR . . . . . . . . . . . . . . . . . . . . . 8.3 Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.1 Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.2 MOS Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.3 Poly–Insulator–Poly Capacitor, PIP . . . . . . . . . . . . . . 8.3.4 Metal–Insulator–Metal Capacitors, MIM . . . . . . . . . .

389 389 389 391 397 410 412 413 414 418 420 421

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Contents

8.4

Varactors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.1 Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.2 Junction Varactors . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.3 MOS Varactors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 Planar Spiral Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.1 Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . 8.6 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.1 Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.2 Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.3 Inductors and Varactors . . . . . . . . . . . . . . . . . . . . . . Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

xix

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424 424 425 428 432 432 436 436 438 439 440 441

Process Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Analog, Mixed-Signal, and RF Components . . . . . . . . . . . . . . . 9.3 Unit Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.1 Starting Substrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.2 Photolithography . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.3 Oxidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.4 Ion Implantation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.5 Thin-Film Deposition . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.6 Etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.7 Annealing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.8 Silicidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.9 Planarization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.10 Plating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4 Digital CMOS Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.1 Isolation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.2 Well Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.3 Gate-Stack Module . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.4 Source–Drain Module . . . . . . . . . . . . . . . . . . . . . . . . 9.4.5 BEOL Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5 Mixed-Signal and RF CMOS/BiCMOS Integration . . . . . . . . . . 9.5.1 High-Voltage CMOS . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.2 Low-Voltage Analog CMOS . . . . . . . . . . . . . . . . . . . . 9.5.3 Isolated NMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.4 Drain-Extended CMOS . . . . . . . . . . . . . . . . . . . . . . . . 9.5.5 Bipolar Junction Transistors . . . . . . . . . . . . . . . . . . . . 9.5.6 Polysilicon and Silicon Resistors . . . . . . . . . . . . . . . . . 9.5.7 Lateral Flux Capacitor (LFC) . . . . . . . . . . . . . . . . . . . 9.5.8 Vertical MIM Capacitor in Aluminum BEOL . . . . . . . . 9.5.9 Vertical MIM Capacitor in Copper BEOL . . . . . . . . . . 9.5.10 Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

447 447 450 450 450 450 451 451 451 452 452 452 453 453 453 453 456 456 458 459 462 465 465 466 468 469 471 473 473 474 476

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Contents

9.6

Analog CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6.1 HV Analog CMOS Transistors . . . . . . . . . . . . . . . . . 9.6.2 Native NMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6.3 Depletion-Mode NMOS . . . . . . . . . . . . . . . . . . . . . . 9.6.4 Buried-Channel PMOS . . . . . . . . . . . . . . . . . . . . . . . 9.6.5 Junction Field-Effect Transistor Module . . . . . . . . . . 9.6.6 High Sheet Poly Resistor . . . . . . . . . . . . . . . . . . . . . 9.6.7 Thin-Film Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6.8 Poly-Insulator-Poly Capacitor . . . . . . . . . . . . . . . . . . 9.6.9 Buried (Subsurface) Zener Diode . . . . . . . . . . . . . . . 9.7 Bipolar-CMOS-DMOS, BCD . . . . . . . . . . . . . . . . . . . . . . . . 9.7.1 NLDMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.7.2 High-Frequency NLDMOS . . . . . . . . . . . . . . . . . . . . 9.7.3 Low-Complexity NLDMOS . . . . . . . . . . . . . . . . . . . 9.7.4 Isolated-Drain NLDMOS . . . . . . . . . . . . . . . . . . . . . 9.7.5 PLDMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

. . . . . . . . . . . . . . . . . .

476 476 477 477 477 479 479 481 482 484 484 485 487 487 489 490 491 493

Mismatch and Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1 Systematic Mismatch . . . . . . . . . . . . . . . . . . . . . . . . 10.2.2 Random Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.3 Layout Configurations . . . . . . . . . . . . . . . . . . . . . . . 10.2.4 Inverse Area Law . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.5 MOSFET Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.6 Bipolar Transistor Mismatch . . . . . . . . . . . . . . . . . . . 10.2.7 Resistor Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.8 Capacitor Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.1 Classification of Noise . . . . . . . . . . . . . . . . . . . . . . . 10.3.2 1/f Noise in CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.3 1/f Noise in Resistors . . . . . . . . . . . . . . . . . . . . . . . . 10.3.4 1/f Noise in Bipolar Junction Transistors (BJT) . . . . . . 10.3.5 1/f Noise in Junction Field-Effect Transistors (JFET) . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 Circuit Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.1 Mismatch in Current Mirrors . . . . . . . . . . . . . . . . . . . 10.4.2 Noise in Two-Stage Transconductance Amplifier . . . . Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

495 495 495 496 498 499 501 501 506 508 510 513 514 518 523 524 525 526 527 528 530 532

Contents

11

Chip Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Definition of Terms and Basic Reliability Concepts . . . . . . . . . 11.2.1 Population and Sample . . . . . . . . . . . . . . . . . . . . . . . 11.2.2 Reliability and Failure Probability Functions . . . . . . . 11.2.3 Probability Density Function (pdf) . . . . . . . . . . . . . . . 11.2.4 Cumulative Distribution Function (CDF) . . . . . . . . . . 11.2.5 Failure Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.6 The “Bathtub” Curve . . . . . . . . . . . . . . . . . . . . . . . . 11.2.7 Failure in Time (FIT) . . . . . . . . . . . . . . . . . . . . . . . . 11.2.8 Accelerated Testing, Acceleration Factor . . . . . . . . . . 11.3 Reliability Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.1 Exponential Distribution . . . . . . . . . . . . . . . . . . . . . . 11.3.2 Normal Distribution . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.3 Lognormal Distribution . . . . . . . . . . . . . . . . . . . . . . . 11.3.4 Weibull Distribution . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.5 Power Law Model . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Failure Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.1 Dielectric Reliability . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.2 Electromigration and Stress Migration . . . . . . . . . . . . 11.4.3 Hot-Carrier Effects . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.4 Bias-Temperature Instability . . . . . . . . . . . . . . . . . . . 11.4.5 Joule Heating and Resistor Reliability . . . . . . . . . . . . 11.4.6 Plasma Charging and Damage . . . . . . . . . . . . . . . . . . 11.4.7 Latch-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.8 High-Voltage MOSFET Reliability . . . . . . . . . . . . . . 11.4.9 Electrostatic Discharge and Voltage Snapback . . . . . . Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xxi

539 539 540 540 540 541 541 541 543 544 545 545 546 546 549 552 554 556 556 568 577 585 587 589 592 598 604 607 608

Appendix A: Universal Physical Constants . . . . . . . . . . . . . . . . . . . . . . . 621 Appendix B: Properties of Silicon and Germanium Crystals (300 K) . . . 623 Appendix C: Properties of SiO2 and Si3N4 (300 K) . . . . . . . . . . . . . . . . . 627 Appendix D: International System of Units, SI . . . . . . . . . . . . . . . . . . . . 629 Appendix E: The Greek Alphabet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631 Appendix F: Conversion Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633 Periodic Table of the Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637

Abbreviations and Acronyms

2LM 2T 3D 3T AC ADC AF ALD AR AR B BC BCD BCPMOS BEOL BGR BiCMOS BJT Body BOX BPSG BTI Bulk C CCD CDF CDM CLM CM CMOS

2-level metal Two-terminal structure Three-dimensional Three-terminal structure Alternating current Analog-to-digital converter Acceleration factor Atomic-layer deposition Antenna ratio Aspect ratio Base Buried-channel Bipolar CMOS DMOS Buried-channel PMOS Back-end of the line Bandgap reference Bipolar CMOS Bipolar junction transistor MOSFET region between source and drain Buried oxide Boro-phosphosilicate glass Bias-temperature instability Silicon substrate region under the surface Collector Charge-coupled device Cumulative distribution function Charged-device model Channel-length modulation Current mirror Complementary metal-oxide-silicon xxiii

xxiv

CMP CMRR CNL CPU CSOA CT C-t C-V CVD D D DA DAC DC De-biasing DECMOS DEMOS DENMOS DEPMOS DIBL DM DMNMOS DMOS DNW DPPM Drain DSP DTI E EFR EHP EM EOT Epi ESD eV FBSOA FD FEOL Field-gap FIT FN FOM FSG

Abbreviations and Acronyms

Chemical-mechanical polishing Common-mode rejection ratio Charge neutrality level Central processing unit Commutating safe operating area Computed tomography Capacitance-time Capacitance-voltage Chemical-vapor deposition Diode Duty cycle Dielectric absorption Digital-to-analog converter Direct current IR drop of opposite polarity to the built-in voltage Drain-extended CMOS Drain-extended MOS Drain-extended NMOS Drain-extended PMOS Drain-induced barrier lowering Depletion-mode Depletion mode NMOS Double-diffused MOS Deep-Nwell Defective parts per million Collector of channel carriers in field-effect transistor Digital signal processing Deep-trench isolation Emitter Early failure rate Electron-hole pair Electromigration Equivalent-oxide thickness Epitaxy Electro-static discharge Electron volt Forward-biased safe operating area Fully depleted Front-end of the line Field-oxide in drift region under the gate, DEMOS, LDMOS Failure in time Fowler Nordheim (tunneling) Figure of merit Fluorinated silicate glass

Abbreviations and Acronyms

Gap-fill GGNMOS GIDL GOI GPS GPU HBM H-bridge HCI HDP HF High-κ HRS HS HS NLDMOS HSR HTGS HTRB HV HV-CMOS I/O IC IDM IEC IF IFO IFR IGBT ILD IMD IoT IPD ISSG ITRS I-V JFET K LDD LDMOS LED LER LFC LNA

xxv

Filling the gap between conductor lines Grounded-gate NMOS Gate-induced drain leakage Gate-oxide integrity Global positioning system Graphics processor unit Human body model Circuit enabling a voltage to be applied across a load in opposite direction Hot-carrier injection High-density plasma High-frequency High dielectric-constant insulator High-resistivity substrate High-side High-side NLDMOS High-sheet resistor High-temperature gate stress High-temperature reverse-bias stress High-voltage High-voltage CMOS Input/output Integrated circuit Integrated device manufacturer International Electrotechnical Commission Intermediate frequency Interfacial oxide Intrinsic failure rate Insulated-gate bipolar transistor Inter-level dielectric Inter-metal-dielectric Internet of tThings Inter-poly dielectric In situ steam-generated International technology roadmap for semiconductors Current-voltage Junction field-effect transistor Key point Lightly doped drain Lateral double-diffused MOS Light-emitting diode Line-edge roughness Lateral-flux-capacitor Low-noise amplifier

xxvi

LO LOCOS Low-κ LP LPCVD LS LS NLDMOS LSR LV LV-CMOS MESFET MIGS MIM MM MOS MOSFET MS MS CMOS MSR MTF MTTF NBL NBTI NCE N-channel Nitride NJFET NLDD NLDMOS NMOS NO NVM N-well OED ONO OTA OTP OVST PA PBL PBTI PC P-channel pdf

Abbreviations and Acronyms

Local oscillator Local oxidation Low dielectric constant insulator Low-pressure Low-pressure chemical-vapor deposition Low-side Low-side NLDMOS Low-sheet resistance Low voltage Low-voltage CMOS Metal-silicon field-effect transistor Metal-induced gap states Metal-insulator-metal (capacitor) Machine model Metal-oxide semiconductor Metal-oxide semiconductor field-effect transistor Mixed signal Mixed-signal CMOS Medium sheet-resistance Median time to fail Mean time to fail N-type buried layer Negative bias-temperature instability Narrow-channel effect N-type channel between MOSFET source and drain Silicon nitride N-type junction field-effect transistor N-type lightly doped drain N-type lateral-double-diffused MOS N-channel MOSFET Nitrided oxide (gate dielectric) Nonvolatile memory N-type well Oxidation-enhanced diffusion Oxide-nitride-oxide (dielectric) Operational transconductance amplifier One-time programming Over-voltage stress testing Power amplifier P-type buried layer Positive bias-temperature instability Personal computer P-type conductive region between source and drain of MOSFET Probability density function

Abbreviations and Acronyms

PDK PE PECVD PEN PETEOS PIN PIP PJFET PLDD PLDMOS PMD PMIC PMOS PNO POCl3 PoE Poly PSD PSG PVD PWM Q QBD QS RBSOA RC RESURF RF RF BiCMOS RF CMOS RFID RIE RMS RNCE RSCE RTA RTN RTP RTS SAR SBD SC SCE SCR

Process-delivery kit Plasma-enhanced Plasma-enhanced chemical-vapor deposition Plasma-enhanced nitride (deposition) Plasma-enhanced TEOS deposition P-Intrinsic-N diode Polysilicon-insulator-polysilicon (capacitor) P-type junction field-effect transistor P-type lightly doped drain P-type lateral-double-diffused MOS Poly-metal dielectric Power management integrated circuit P-channel MOSFET Plasma nitride-oxide Phosphorus oxychloride Power over Ethernet Polysilicon Power spectral density Phosphosilicate glass Physical vapor deposition Pulse width modulation Quality factor Charge to breakdown Quasi-saturation Reverse-biased safe operating area Resistance-capacitance product Reduced surface field Radio frequency Radio-frequency bipolar CMOS Radio-frequency CMOS Radio-frequency identification Reactive-ion etching Root-mean squared Reverse narrow-channel effect Reverse short-channel effect Rapid-thermal annealing Random telegraph noise Rapid-thermal processing Random telegraph signal Successive approximation register Schottky-barrier diode Surface-channel Short-channel effect Silicon-controlled rectifier

xxvii

xxviii

SI SIC SiGe SiGe:C SILC SJ SJ LDMOS SM SOA SoC SOI SOS SPC SPICE SRAM SRF SRH STI Substrate TCAD TCC TCE TCP TCR TDDB TED TEM TEOS TFR TLP UIS UTB UV Varactor VCC VCO VCR VDMOS VDP Vop Vref WLAN WLR

Abbreviations and Acronyms

International System Selectively implanted collector Silicon-germanium Silicon-germanium-carbon Stress-induced leakage current Superjunction Superjunction LDMOS Stress migration Safe operating area System on a chip Silicon-on-insulator Silicon-on-sapphire Statistical process control Simulation program with integrated circuit emphasis Static random-access memory Self-resonant frequency Shockley-Read-Hall (generation-recombination) Shallow-trench isolation Silicon region under active components Technology computer-aided design Temperature coefficient of capacitance Temperature coefficient of expansion Temperature compensation point Temperature coefficient of resistance Time-dependent dielectric breakdown Transient-enhanced diffusion Transmission electron microscopy Tetraethylorthosilicate (oxide) Thin-film resistor Transmission-line pulse Unclamped inductor switching Ultrathin body Ultraviolet Variable reactor Voltage coefficient of capacitance Voltage-controlled oscillator Voltage coefficient of resistance Vertical DMOS Van der Pauw (Test structure) Operating voltage Voltage reference Wireless local area network Wafer-level reliability

Symbols

Symbols with bar, such as n
, denote thermal-equilibrium or average values; symbols ~ denote effective values. with tilde, such as D, a a a A A* AC Ac Adiff AE AG AI D AP AR AS AV AV T b b B B B B* Bi 1 2

Grade constant, PN junction (cm4) Voltage ramp-rate, quasi-static measurement (V/s) JFET metallurgical channel width (cm) Area (cm2) Richardson constant (A/cm2K2) Collector area (cm2) Contact area (cm2) Differential gain (–) Emitter area (cm2) Gate area (cm2) Drain-current mismatch factor1 (%-μm) Parameter mismatch factor (–) Mismatch constant for resistance (%-μm) Surface area (cm2) Intrinsic voltage gain (¼ gm/ro) (–) Threshold-voltage mismatch factor2 (mV-μm) Mobility ratio (¼ μn/μp) (–) Fitting parameter for 1/f noise (–) Base (–) Fitting parameter (–) Exponential multiplier in FN tunneling current equation (–) Exponential multiplier in direct tunneling current equation (–) Substrate current fitting parameter (–)

ΔID/ID in % and channel area in μm2. ΔVT/VT in mV and channel area in μm2. xxix

xxx

BI B BI C BV BVCBO BVCBS BVCEO BVCES BVCEX BVDGO BVDGS BVDSS BVEBO BVEBS BVeff c C C0 C cA CA CB Cc CD CDB Cdecap Cdeep CDS Cf Cfpar CFB CG CGB CGch CGD CGG CGS CHF CIMD Cinv

3 4

Symbols

Base-current mismatch factor3 (%-μm) Collector-current mismatch factor4 (%-μm) Breakdown voltage (V) Collector-base breakdown voltage with emitter open (V) Collector-base breakdown voltage with base-emitter shorted (V) Collector-emitter breakdown voltage with base open (V) Collector-emitter breakdown voltage with emitter-base shorted (V) Collector-emitter breakdown voltage with base resistor (V) Drain-to-gate breakdown voltage, source open (V) Drain-to-gate breakdown voltage, source and gate shorted (V) Drain-to-source breakdown voltage, source, body, and gate shorted (V) Emitter-base breakdown voltage with collector open (V) Emitter-base breakdown voltage with base-collector shorted (V) Effective breakdown voltage (BVeff) Light velocity (cm/s) Capacitance density (F/cm2) Capacitance at V ¼ 0 (F/cm2) Collector (–) Capacitance density, PN junction (F/cm2) Area capacitance, PN junction (F) Barrier capacitance density, SBD (F/cm2) Compensation capacitance (F) Diffusion capacitance density (F/cm2) Drain-to-body capacitance (F) Decoupling capacitance (F) Capacitance density in deep depletion, MOS (F/cm2) Drain-to-source capacitance (F) Fringe capacitance (F/cm) Fringe parasitic capacitance (F/cm) MOS flatband capacitance area (F/cm2) Gate capacitance density (F/cm2) Gate-to-body capacitance (F) Gate-to-channel capacitance density (F/cm2) Gate-to-drain capacitance (F) Total gate capacitance (F) Gate-to-source capacitance (F) High-frequency capacitance density, MOS (F/cm2) Inter-metal dielectric capacitance density (F/cm2) Silicon inversion capacitance density (F/cm2)

ΔIB/IB in % and emitter area in μm2. ΔIC/IC in % and emitter area in μm2.

Symbols

Cit Cj CjC CjE CL CLF CLL Cmax Cmin CNW Cof Cov Cox cP CP CP Cpar CPMD Cpoly CSi CSBD CSiFB CSimin CSTI CT CTFR Cvarmax Cvarmin D D Dn Dp D D D deq di do E E

xxxi

Interface capacitance due to charge and discharge of interface states (F/cm2) Junction capacitance (F) Collector-base junction capacitance (F) Emitter-base junction capacitance (F) Load capacitance (F) Low-frequency capacitance density, MOS (F/cm2) Line-to-line capacitance (F/cm) Maximum MOS capacitance density in strong accumulation MOS (F/cm2) Minimum MOS capacitance density in strong inversion at equilibrium (F/cm2) N-well to substrate capacitance density (F/cm2) Outer fringe capacitance (F) Overlap capacitance (F) Oxide capacitance density (F/cm2) Capacitance per unit perimeter, PN junction (F/cm) Perimeter capacitance, PN junction (F) Charge pump capacitance (F) Parasitic capacitance (F) Poly-metal-dielectric capacitance density (F/cm2) Poly depletion capacitance density (F/cm2) Silicon capacitance density, MOS (F/cm2) Schottky diode capacitance density (F/cm2) Silicon capacitance at flatband density, MOS (F/cm2) Minimum silicon capacitance density in strong inversion at equilibrium, MOS (F/cm2) STI capacitance density (F/cm2) Total capacitance (F) TFR capacitance density (F/cm2) Maximum varactor capacitance (F) Minimum varactor capacitance (F) Diffusivity (cm2/s) Duty cycle, e.g., ton/(ton + toff) (–) Electron diffusivity (cm2/s) Hole diffusivity (cm2/s) Film thickness (cm) Diameter (cm) Distance (cm) Equivalent-oxide film distance (cm) Inner side length for spiral inductor (cm) Outer side length for spiral inductor (cm) Electric field (V/cm) Emitter (–)

xxxii

E E00 EA Ea EBD Ec EC ED Eeff EF EFn EFp Eg Ei EI Em En EN Eox EP Epeak Eref Es Esat ESi EV Ex Ey f f(t) F(t) fc fc fmax fr fsrf fSW fT g G G G0 Gc

Symbols

Energy (eV) Characteristic tunneling energy (eV) Acceptor energy level (eV) Activation energy (eV) Field to breakdown, dielectric (V/cm) Critical field, silicon (V/cm) Bottom of conduction-band energy level (eV) Donor energy level (eV) Effective electric field (V/cm) Fermi energy level (eV) Electron Fermi energy level (eV) Hole Fermi energy level (eV) Energy gap (eV) Intrinsic energy level (eV) Ionization energy (eV) Metal Fermi energy level (eV) Nitride field (V/cm) Electric field for Poole-Frenkl field-assisted hopping (eV) Oxide field (V/cm) Phonon energy (eV) Peak silicon field (V/cm) Reference energy level (eV) Surface field (V/cm) Field in silicon at onset of saturation velocity (V/cm) Silicon field (V/cm) Top of valence-band energy level (eV) Vertical field in silicon (V/cm) Horizontal field in silicon (V/cm) Frequency (Hz) Probability density function, probability for device to fail within dt around t (%) Cumulative distribution function (%) Cutoff frequency (Hz) Corner frequency (Hz) Maximum frequency of oscillation (Hz) Resonant frequency (Hz) Self-resonance frequency (Hz) Switching frequency (Hz) Gain-bandwidth product, frequency at which β ¼ 1 (Hz) Gravity (m/s2) Power gain (–) Generation rate (cm3 s1) JFET conductance at VG ¼ 0 (S) Collector output conductance (S)

Symbols

Gd Gdlin Gdsat gm gmlin gmsat GR h H hfe hFE I i I0 iA IA IB IB Ibn Ibp IBV IC ICB ICBO ICBS ICE ICEO ICES Icn Icno Ico Icp Icpo ICsat ID ID0 IDD Idiff IDlin IDS IDsat IDsat(0) IE IEBO

xxxiii

Drain conductance (S) Liner drain conductance (S) Saturation drain conductance (S) Transconductance (S) Linear transconductance (S) Saturation transconductance (S) Generation-recombination Planck constant (eV-s, J-s) Heat consuctionn (W) Small-signal grounded-emitter current gain (–) Large-signal grounded-emitter current gain (–) Current (A) Small-signal current (A) Drain current per channel-square fixed-current method (A) Leakage current, PN junction (A/cm2) Area leakage current, PN junction (A) Base current (A) Body current (A) Base current in NPN (A) Base current in PNP (A) Current at breakdown (A) Collector current (A) Collector-to-base current (A) Collector-to-base current with emitter open (A) Collector-to-base current with emitter-base shorted (A) Collector-to-emitter current (A) Collector-to-emitter current with base open (A) Collector-to-emitter current with base shorted to emitter (A) Collector current in NPN (A) Collector-base leakage current in NPN (A) Total leakage current in PNPN structure (A) Collector current in PNP (A) Collector-base leakage current in PNP (A) Collector saturation current (A) Drain current (A) Drain current at which the threshold voltage is measured, ¼ Io
W/L (A) Supply current (A) Diffusion current (A) Linear drain current (A) Drain-to-source current (A) Saturation drain current (A) Saturation drain current with VG ¼ 0 (A) Emitter current (A) Emitter-to-base current with collector open (A)

xxxiv

IEBS IECS IF Igen Igen-surf IGG IH Iit IL IL in In INW Io Ioff Ion IOUT Ip iP IP Ip IPT IPTO IPW IR IR IR Irec Irec-surf IRM IS IS Is Is ISB ISC Isub It1 It2 Itr j jB

Symbols

Emitter-to-base current with collector shorted to base (A) Emitter-to-collector current with base shorted to collector (A) Forward current (A) Generation current (A) Surface generation current per unit area (A/cm)2 Total gate current (A) Holding current (A) Interface charge and discharge current (A) Current through load (A) Inductor current (A) Current noise (A) Electron current (A) N-well current (A) Technology-dependent current per square of channel at which VT is measured (A) Off-current (A) On-current (A) Output current (A) Hole current (A) Leakage current per unit perimeter, PN junction (A/cm) Perimeter leakage current, PN junction (A) Current in primary of transformer (A) Punch-through current (A) Current at onset of punch-through (A) P-well current (A) Reverse current (A) Voltage drop in resistance (V) Resistor current (A) Recombination current (A) Recombination current density at silicon surface (A/cm2) Reverse maximum current during reverse recovery (A) Saturation current (A) Source current (A) Surface generation current (A) Current in secondary of transformer (A) Emitter-base saturation current (A) Collector-base saturation current (A) Substrate current (body current, IB) (A) Trigger current for ESD (A) Secondary breakdown current for ESD (A) Latch-up trigger current (A) Current density (A/cm2) Base current density, BJT (A/cm2)

Symbols

jC jDC jdirect jdrift jE jFN jG jM jM⟶Si jmax jn jn(dif) jn(drift) jp jp(dif) jp(drift) jpeak jPF jR jrms jS jSi⟶M jstress jT juse k k k KF KF0 KFBJT KFR kT kT/q L L L L L0 ℓ LAA Lc Lc LD

xxxv

Collector current density, BJT (A/cm2) Time-average DC current density (A/cm2) Direct tunneling current density (A/cm2) Drift current density (A/cm2) Emitter current density, NJT (A/cm2) Fowler-Nordheim current density (A/cm2) Gate current density (A/cm2) Metal current density (A/cm2) Thermionic emission (metal to silicon) current density (A/cm2) Maximum current density (A/cm2) Electron current density (A/cm2) Electron diffusion current density (A/cm2) Electron drift current density (A/cm2) Hole current density (A/cm2) Hole diffusion current density (A/cm2) Hole drift current density (A/cm2) Absolute maximum current density, conductors (A/cm2) Poole-Frenkl current density (A/cm2) Reverse thermionic current density (A/cm2) Root-mean-square current density (A/cm2) Saturation current density (A/cm2) Thermionic emission (silicon to metal) current density (A/cm2) Current density in stress condition (A/cm2) Tunneling current density (A/cm2) Current density in use condition (A/cm2) Boltzmann constant (eV/K, J/K) Scaling factor (–) Ratio of thicknesses in fringe capacitance calculation (–) Process constant for MOSFET 1/f noise parameter (–) Process constant for MOSFET 1/f noise (–) Process constant for BJT noise (–) Process constant for resistor noise (–) Thermal energy, (ffi 0.0259 eV at 300 K) (eV) Thermal voltage, (ffi 0.0259 V at 300 K) (V) Channel length (cm) Inductance (H) Length (cm) Transistor length (cm) Effective channel length due to pinch-off (cm) Mean-free path (cm) Length of active area (cm) Contact length (cm) Blech length (cm) Debye length (cm)

xxxvi

Symbols

LD LD Ldrift LE LE Leff ℓ eff ℓi Lmet Ln LnB LNBL Lov Lp Lp Lpar LpE Lpoly Ls LSi LT LT M M M M M m* me N A Nþ D n
n n
p n
n0

Drawn length (cm) Drain length (cm) Length of drift region, DEMOS, LDMOS (cm) Electrical length (cm) Emitter length (cm) Effective channel length (cm) Effective mean-free path (cm) Impact-ionization mean-free path (cm) Metallurgical channel length (cm) Electron diffusion length (cm) Electron diffusion length in base (cm) Distance in NBL from collector contact to emitter center (cm) Length of gate-overlap of source or drain (cm) Hole diffusion length (cm) Primary inductance (H) Parasitic inductance (H) Hole diffusion length in emitter (cm) Poly channel-length, line-width (cm) Secondary inductance (H) Length of silicon region (cm) Transfer length contacts (cm) Optical phonon mean-free path (cm) Multiplication factor (–) Mean of logarithms of time to fail (–) Factor for recombination (–) Power transistor naming nomenclature (–) Fitting parameter for doping profile (–) Effective mass (Kg) Free electron mass (Kg) Ionized acceptor concentration (cm3) Ionized donor concentration (cm3) Thermal-equilibrium electron concentration in N-region (cm3) Thermal-equilibrium electron concentration in P-region (cm3) Thermal-equilibrium electron concentration at depletion boundary in N-region (cm3) Thermal-equilibrium electron concentration at depletion boundary in P-region (cm3) Electron concentration (cm3) Ideality factor (–) Number of squares (–) Number of carriers per square (cm2) Total doping concentration (cm3) Empirical exponent for breakdown voltage (usually 2–4) (–) Transformer ratio of turns (–)

n
p0 n n n N N N n

Symbols

N n NA NA(x) NA0 NAC NAE NA-top nb Nbody NC ND ND(x) ND0 Ndrift Neff Nf NG NI ni NI ni0 niB niE ninv Ninv Nit nn nn0 Nox np Np np0 np0 npo Nref ns Ns nS ns0 NSi nsL ns0

xxxvii

Number of turns for spiral inductor (–) Power law exponent (–) Acceptor concentration (cm3) Acceptor concentration as a function of x (cm3) Acceptor concentration at x ¼ 0 (cm3) Acceptor concentration at collector-base junction (cm3) Acceptor doping concentration at emitter-base junction (cm3) Acceptor doping concentration for top layer (double RESURF structure) (cm3) Electron concentration in bulk (cm3) Body doping concentration (cm3) Effective density of states at conduction band-edge (cm3) Donor concentration (cm3) Donor concentration as a function of x (cm3) Donor concentration at x ¼ 0 (cm3) Drift region doping concentration (cm3) Effective doping concentration (cm3) Number of fixed oxide charges, (¼ Qf/q) (cm2) Number of poly grains (–) Ionized impurity concentration (cm3) Intrinsic-carrier concentration (cm3) Number of mobile ions, dielectrics (cm2) Intrinsic-carrier concentration without energy gap lowering (cm3) Intrinsic-carrier concentration in base (cm3) Intrinsic-carrier concentration in emitter (cm3) Inversion electron density (cm2) Inversion-carrier density (cm3) Interface trap density (cm2) Electron concentration in N-region (cm3) Electron concentration at depletion boundary in N-region (cm3) Density of oxide molecules (cm3) Electron concentration in P-region (cm3) Transformer number of primary turns (–) Electron concentration at depletion boundary in in P-region (cm3) Electron minority concentration at depletion boundary (cm3) Minority electron concentration at equilibrium (cm3) Fitting parameter (–) Surface electron concentration (cm2) Transformer number of secondary turns (–) Carrier sheet concentration (cm2) Surface electron concentration at source end of channel (cm3) Density of silicon atoms (cm3) Surface electron concentration at drain (cm3) Surface electron concentration at source (cm3)

xxxviii

Nsub NT NV p
n p
p p
n0 p
p0 P P P p P P0 pb PBV PCOND PDIODE PIN PLOSS pn pn0 POUT pp pp0 ps PSW PSW,G Q Q q QΔps Qb QBD Qbmax Qc Qeff Qf QG QGD Qinv Qit

Symbols

Substrate doping concentration (cm3) Trap density, density of generation-recombination centers (cm3) Effective density of states at valence band-edge (cm3) Thermal-equilibrium hole concentration in N-region (cm3) Thermal-equilibrium hole concentration in P-region (cm3) Thermal-equilibrium hole concentration at depletion boundary in N-region (cm3) Thermal-equilibrium hole concentration at depletion boundary in P-region (cm3) Parameter (–) Probability (–) Power (W) Hole concentration (cm3) Power/heat dissipation (W) Value of arbitrary parameter at time t ¼ 0 (–) Bulk hole concentration (cm3) Peak avalanche power (W) Conduction power loss (W) Power loss in diode (W) Input power (W) Power loss (W) Hole concentration in N-region (cm3) Hole concentration at depletion boundary in N-region (cm3) Output power (W) Hole concentration in P-region (cm3) Hole concentration at depletion boundary in P-region (cm3) Surface hole concentration (cm3) Switching power (W) Switching power loss in the gate (W) Quality factor (–) Charge density (C/cm2) Electronic charge (magnitude) (C) Charge density due to excess holes at surface (C/cm2) Bulk charge density (C/cm2) Charge density to breakdown (C/cm2) Maximum bulk charge density at onset of inversion at equilibrium (C/cm2) Critical charge density (C/cm2) Effective dielectric charge density (C/cm2) Fixed oxide charge density (C/cm2) Gate charge density (C/cm2) Gate-to-drain charge (C) Electron inversion charge density (C/cm2) Interface trap charge density (C/cm2)

Symbols

Qm Qm Qmax Qmax-ideal Qn QN Qninv Qot Qox Qp QP Qpeak Qpinv Qrr QS Qs QSi QSTI QT QT Qtotal R R R R R R(t) r0 R0 R0 r1 r2 Racc rAn rAp RB RB RB0 RBext RBint Rc RC RC Rc

xxxix

Mobile charge density (C/cm2) Gate charge density (C/cm2) Quality-factor maximum (–) Maximum depletion charge density, no interface states (C/cm2) Electron charge density (C/cm2) Charge density in N-side depletion region (C/cm2) Inversion electron charge density (C/cm2) Oxide-trapped charge density (C/cm2) Oxide charge density (C/cm2) Hole charge density (C/cm2) Charge density in P-side depletion region (C/cm2) Peak charge per unit area (C/cm2) Inversion hole charge density (C/cm2) Reverse recovery charge (C) Stored charge density (C/cm2) Surface charge density (C/cm2) Charge in silicon density (C/cm2) Antenna charge collected per STI area (C) Total charge (C) Trap charge density (C) Total plasma charge collected on antenna (C) Resistance (Ω) Radius (cm) Loop radius for circular inductor (cm) Fraction of power supply (for calculating Cdecap) (–) Correlation coefficient (–) Reliability function, ratio of devices that survive to time t (1  F(t)) (–) Output resistance (Ω) Resistance at reference voltage V0 (Ω) Intrinsic drift resistance (Ω) Inner radius of depletion at cylindrical junction edge (cm) Outer radius of depletion at cylindrical junction edge (cm) Resistance of accumulated region, LDMOS, DMOS (Ω) Auger electron recombination rate (cm6/s) Auger hole recombination rate (cm6/s) Base resistance (Ω) Body resistance (Ω) Base resistance without applied bias (Ω) Extrinsic base resistance (Ω) Intrinsic base resistance (Ω) Contact resistance (Ω) Collector resistance (Ω) Time delay (s) Compensation resistance (Ω)

xl

RC1 Rc1 RC2 Rc2 RC3 RC-active Rch RC-sat RD RDIODE Rdrift Rdrift0 RDS RDS(on) re RE Redge Rend Rext RG ri rj RKS RL RL RLDD RM Rn RNBL RNW ro RP Rp RPBL Rpinch Rprobe RPW RR RS Rs RS RS0 RS-drift RSext

Symbols

Vertical resistance of collector sinker (Ω) Contact stud (plug) to silicide resistance (Ω) Horizontal resistance of collector buried layer (Ω) Silicide-silicon interface resistance (Ω) Vertical resistance of collector epi (Ω) Collector resistance in forward active mode (Ω) Channel resistance (Ω) Collector resistance in saturation mode (Ω) Drain resistance (Ω) Diode resistance (Ω) Resistance of drift region, DEMOS, LDMOS (Ω) Resistance of drift region at zero bias (Ω) Drain-to-source resistance (Ω) Drain-to-source on-resistance (Ω) Dynamic (AC, small-signal) emitter resistance (Ω) Emitter resistance (Ω) Normalized source and drain resistance per edge of transistor (Ω-μm) End resistance (Ω) Extrinsic resistance (Ω) Gate resistance (Ω) Median rank using Benard’s empirical approximation (–) Radius metallurgical junction edge (cm) Resistance between key point and source (Ω) Load resistance (Ω) Inductor resistance (Ω) Resistance of lightly doped region (Ω) Metal resistance (Ω) Resistance equivalent noise (Ω) Resistance of buried N-layer (Ω) N-well resistance (Ω) Output resistance (Ω) Parallel equivalent resistance (Ω) Projected range, ion implantation (cm) Resistance of buried P-layer (Ω) Pinch-resistance, base (Ω) Test probe resistance (Ω) P-well resistance (Ω) Ramp-rate, voltage (V/s) Source resistance (Ω) Series resistance (Ω) Sheet resistance (Ω/⎕) Sheet resistance at T ¼ T0 (Ω/⎕) Sheet resistance of drift region (Ω/⎕) Extrinsic sheet resistance (Ω/⎕)

Symbols

RSi RSint RS-inv RSP Rspr Rsub RT Rth Rwell Rwire S S s S S S S S Si SIB SIC SID SIR so Sv SVG t T T T T T0 t50 Tamb tAV tAv tBD TCC TCC(i) TCC(SC) TCC(thermal) TCR tdrift Te

xli

Silicon resistance (Ω) Intrinsic sheet resistance (Ω/⎕) Inversion-layer sheet resistance (Ω/⎕) Specific resistance, DEMOS, LDMOS (¼ RDS(on)
Area) (mΩ-mm2) Spreading resistance (Ω) Substrate resistance (Ω) Total resistance (Ω) Thermal resistance (K/W) Well resistance (Ω) Wiring resistance (Ω) Subthreshold slope, subthreshold swing (V/decade) Varactor sensitivity (–) Standard deviation of logarithms of time to fail (–) W/L ratio (–) Sensitivity (–) Metal-metal spacing (cm) Slope of VOUT vs. VIN in floating capacitor-mismatch measurement (–) Standard deviation of natural logarithm of times to failure (–) Noise current power spectral density, PSD (A2/Hz) Base current noise PSD (A2/Hz) Collector current noise PSD (A2/Hz) Drain current noise PSD (A2/Hz) Resistor current noise PSD (A2/Hz) Surface recombination velocity (cm/s) Voltage power spectral density, PSD (V2/Hz) Input (gate) referred PSD (V2/Hz) Time (s) Absolute temperature (K) Thickness (cm) Transistor naming convention in circuit design (–) Time period (s) Reference temperature (K) Median time to failure, time for 50% of units to fail (MTF) (s) Ambient temperature (K) Average failure time (s) Average duration of avalanche breakdown event (s) Time to breakdown (s) Temperature coefficient of capacitance (ppm/K) Insulator component of TCC (ppm/K) Space charge component of TCC (ppm/K) Thermal component of TCC (ppm/K) Temperature coefficient of resistance (ppm/k) Thickness of drift region (cm) Electron temperature (K)

xlii

teq teq-PMD tFail ti ti Tlattice tM, tm Tn tN tn toff ton tox tpoly ts tSi tSi tSTI Tstress ttop Tuse U V v V 0D V 0S v0 V0 VA VAC Vapp VB VB, VBS VBC VBE Vbi VbiD VbiS Vbn Vbp VBS VC VCB VCBO

Symbols

Equivalent oxide thickness (cm) Equivalent oxide thickness of PMD layer (cm) Time to fail (s) Time for ith device to fail (s) Insulator thickness (cm) Temperature of lattice (K) Metal thickness (cm) Temperature equivalent noise (K) Time for Nth device to fail (s) Nitride thickness (cm) Transistor turn-off time (s) Transistor turn-on time (s) Oxide thickness (cm) Polysilicon thickness (cm) Storage time (s) Silicon thickness (cm) Path length in silicon (cm) STI thickness (cm) Temperature at stress condition (K) Thickness of top layer (double RESURF structure) (cm) Temperature at use condition (K) Recombination rate (cm3 s1) Voltage potential, electrostatic potential (V) Velocity (cm/s) External drain voltage (V) External source voltage (V) Initial velocity (cm/s) Reference voltage (for dielectric absorption) (V) Early voltage (V) AC voltage (V) Applied voltage (V) Barrier height (V) Body, body-to-source voltage (V) Base-to-collector (V) Base-to-emitter voltage (V) Built-in voltage (V) Built-in voltage at drain end of channel (V) Built-in voltage at source end of channel (V) Barrier for electrons (V) Barrier for holes (V) Body-to-source voltage (V) Collector voltage (V) Collector-to-base voltage (V) Collector-to-base voltage with emitter open (V)

Symbols

VCBS VCC VCC VCE VCEO VCES VCEsat Vch VCR vd VD, VDS VDA VDD VDD VDDM VDG VDK VDLin vdn vdp VDS VDsat vdy VEB VEBO VEBS VECS VF VFB VG, VGS VGr VGS VGSmax VH VIN Vin VIN VIN+ Vint VIO Vj VjG VK VKS

xliii

Collector-to-base voltage with emitter shorted to base (V) Voltage coefficient of capacitance (ppm/V) Power supply voltage, BJT (V) Collector-to-emitter voltage (V) Collector-to-emitter voltage with base open (V) Collector-to-emitter voltage with base shorted to emitter (V) Collector-to-emitter voltage in saturation (V) Channel-to-source voltage (position dependent) (V) Voltage coefficient of resistance (ppm/V) Drift velocity (cm/s) Drain, drain-to-source voltage (V) Measured dielectric absorption voltage, capacitor (V) Drain power supply, MOSFET (V) Supply voltage (V) Maximum voltage spike during reverse recovery (V) Drain-to-gate voltage (V) Drain-to-key point voltage, DEMOS, LDMOS (V) Drain voltage in linear region (V) Electron drift velocity (cm/s) Hole drift velocity (cm/s) Drain-to-source voltage (V) Saturation drain voltage, MOSFET (V) Drift velocity along surface (cm/s) Emitter-to-base voltage (V) Emitter-to-base voltage with collector open (V) Emitter-to-base voltage with collector shorted to base (V) Emitter-to-collector voltage with base shorted to collector (V) Forward voltage (V) Flatband voltage (V) Gate, gate-to-source voltage (V) Voltage across grain (V) Gate-to-source voltage (V) Maximum gate-to-source voltage (V) Holding voltage for ESD (V) Input voltage (V) Input voltage (V) Input voltage (inverting) (V) Input voltage (non-inverting) (V) Internal circuit breakdown voltage (V) Input-offset voltage (V) Junction voltage (V) Junction-to-gate voltage, gated diode (V) Key point voltage (V) Voltage between key point and source, DEMOS, LDMOS (V)

xliv

vn vn VN Vn vn(dif) Vo Vop VOUT Vox vp VP Vp VP vp(dif) Vpoly Vpoly VPT VR Vref VREG Vrms VS vsat Vspike VSS Vstress VT Vt1 Vt2 VT-drain vth VT-long Vtr VT-short VT-source Vuse W W W W WB Wbm WC Wc

Symbols

Electron velocity (cm/s) Noise voltage (V) Voltage at N-side depletion boundary (V) Voltage in N-region Electron diffusion carrier velocity (cm/s) Output voltage (V) Operating voltage (V) Output voltage (V) Voltage across oxide (V) Hole velocity (cm/s) Pinch-off voltage (V) Voltage in P-region (V) Voltage at P-side depletion boundary (V) Hole diffusion carrier velocity (cm/s) Volume of polysilicon (cm)3 Polysilicon voltage (V) Punch-through voltage (V) Reverse voltage (V) Reference voltage (V) Regulated voltage (V) Root-mean-squared voltage (V) Source voltage (V) Saturation velocity (cm/s) Voltage spike (V) Typically ground potential (V) Voltage at stress condition (V) Threshold voltage (V) Trigger voltage for ESD (V) Secondary breakdown voltage for ESD (V) Threshold voltage at drain (V) Thermal velocity (cm/s) Long-channel VT (V) Latch-up trigger voltage (V) Short-channel VT (V) Threshold voltage at source (V) Voltage at use condition (V) Width, layout (cm) Channel width (cm) Width (cm) Transistor width (cm) Base width (cm) Metallurgical base width (cm) Collector width (cm) Contact width (cm)

Symbols

WD WD Wdrift WE WE Weff Wm Wn WNBL Wp WSi x x x xacc xC xch xd xdb xdC xdD xddeep xdE xdfield xdℓ xd-lat xdmax xdn xdn( y) xdnc xdne xdp xdp( y) xdp1 xdp2 xdpc xdpe xd-poly xdS xds xi xinv xj xjbn

xlv

Drawn channel width (cm) Drain width (cm) Width of drift region (cm) Emitter width (cm) Electrical width (cm) Effective channel width (cm) Metal width (cm) Width of neutral N-region (cm) Width of N-buried layer (cm) Width of neutral P-region (cm) Width of silicon region (cm) Depth normal to silicon surface (cm) Distance, depth normal to silicon surface (cm) Random variable (–) Depth of accumulation layer (cm) Lightly doped collector width (cm) Depth of channel (cm) Depletion width (cm) Base depletion width (cm) Collector depletion width (cm) Lateral depletion width at MOSFET drain (cm) Depletion width in deep depletion (cm) Emitter-to-base depletion width (cm) Depletion width under field oxide (cm) Lateral depletion width at junction edge (cm) Lateral depletion width (cm) Maximum depletion width (at onset of strong inversion) (cm) Depletion width in N-region (cm) Depletion width in N-region as a function of lateral distance (cm) Depletion edge in NPN collector side at base-collector junction (cm) Depletion edge in NPN emitter side at emitter-base junction (cm) Depletion width in P-region (cm) Depletion width in P-region as a function of lateral distance (cm) Depletion boundary in base side at emitter-base junction (cm) Depletion boundary in base side at base-collector junction (cm) Depletion width in base side at NPN base-collector junction (cm) Depletion width in base side at NPN base-emitter junction (cm) Depletion width in poly gate (cm) Depletion width at MOSFET source (cm) Depletion width at surface (cm) Depth below the surface where silicon is intrinsic, n ¼ p ¼ ni (cm) Depth of inversion layer peak (centroid) below the surface (cm) Junction depth (cm) Depletion-mode NMOSFET, buried N-region junction depth (cm)

xlvi

xjbp xjC xjE xjNBL xℓ xℓ xRef y ydn ydn0 ydp ydp0 Z z α α αF αi αn αp αR α1 α2 αT αT β β β β βF βn βp βR γ γ γn γp δ δL Δf ΔL Δn

Symbols

Junction depth of buried P-channel (cm) Collector-to-base junction depth (cm) Emitter-to-base junction depth (cm) Depth of NBL to substrate junction (cm) Lateral extent of junction at surface (cm) Depth of potential peak, image-force barrier lowering (cm) Reference for calculating RC1 component (cm) Lateral distance (cm) Lateral depletion width in N-region (cm) Lateral depletion width in N-region at zero bias (cm) Lateral depletion width in P-region (cm) Lateral depletion width in P-region at zero bias (cm) Standardized variable (¼ (x  μ)/σ) (cm) Distance in direction vertical to page (cm) Linear expansion coefficient (%/K) Grounded-base current gain (–) Forward grounded-base current gain (–) Impact ionization rate (cm1) NPN grounded-base current gain (–) PNP grounded-base current gain (–) Reverse grounded-base current gain (–) Linear temperature coefficient of resistance, TCR, or capacitance, TCC (ppm/K) Quadratic temperature coefficient of resistance or capacitance (ppm/K2) Base transport factor (–) Tunneling factor (–) Grounded-emitter current gain (–) Frenkel-Poole emission coefficient (cm1/2V1/2) MOSFET parameter (¼ μCoxWeff/Leff) (Ω1 V1) Weibull shape parameter (–) Forward grounded-emitter current gain (–) NPN grounded-emitter current gain (–) PNP grounded-emitter current gain (–) Reverse grounded-emitter current gain (–) Injection ratio (–) Field acceleration factor, reliability (–) Electron injection efficiency ¼ In/(In + Ip) (–) Hole injection efficiency ¼ Ip/(In + Ip) (–) Skin depth (cm) Width of pinch-off region (cm) Bandwidth over which noise is measured (Hz) Change in length, channel length (cm) Incremental increase or decrease electron concentration (cm)3

Symbols

Δp ΔP ΔQn ΔQp ΔV ΔW Δxd Δxdn Δxdp εn εo εox εSi η η θ κ κ κox κSi λ λ λ λ(i) λ(t) λo μ μ0 μeff μI μIn μIp μℓ μℓn μℓp μΔp ρ ρ ρc ρsurf ρ0 σ σ

xlvii

Incremental increase or decrease hole concentration (cm)3 Small change in parameter P, e.g., ΔV: small change in voltage, V (–) Change in charge density in N-region (C/cm2) Change in charge density in P-region (C/cm2) Change in voltage (V) Change in width, channel width (cm) Change in depletion width (cm) Change in depletion width in N-region (cm) Change in depletion width in P-region (cm) Dielectric constant of nitride (7.0) (–) Permittivity of free space, vacuum (8.854
1014 F/cm) (F/cm) Dielectric constant of oxide (3.9) (–) Dielectric constant of silicon (11.7) (–) Power efficiency (–) Weibull scale parameter (–) Mobility degradation factor (V1) Dielectric constant (–) Thermal conductivity (W/cm-K) Oxide dielectric constant, same as εox (–) Silicon dielectric constant, same as εSi (–) Tunneling-attenuation length (cm) Channel length modulation factor (–) Electron mean-free path (cm) Failure rate for device i, probability that device will fail per second (s1) Failure rate, probability that device will fail per second (s1) Wavelength in vacuum (cm) Mobility (cm2/Vs) Low-field mobility (cm2/Vs) Effective inversion-carrier mobility (cm2/Vs) Ionized impurity mobility (cm2/Vs) Electron ionized impurity mobility (cm2/Vs) Hole ionized impurity mobility (cm2/Vs) Lattice mobility (cm2/Vs) Electron lattice mobility (cm2/Vs) Hole lattice mobility (cm2/Vs) Mean of normal distribution of Δp (–) Resistivity (Ω-cm) Volume charge concentration (C/cm3) Specific contact resistance (Ω-cm2) Surface scattering-limited resistivity, TFR (Ω-cm) Bulk resistivity (Ω-cm) Tensile strain (Pa) Conductivity (S)

xlviii

σ σH σ PF σ 2ΔP σ 2ΔQeff σ ΔI B σ ΔI C σ ΔI D σ Δp σ ΔV T σ Δβ τ τ1 τA τAn τAp τB τC τE τn τnB τn-eff τo τp τpE τp-eff τrr τSRH ϕ ϕ ϕ ϕb ϕB ϕB0 ϕBeff ϕbn ϕBn ϕbp ϕBp ϕHCI ϕm ϕms ϕo ϕs

Symbols

Cross section, capture cross section (cm2) Hooge’s constant (–) Poole-Frenkel conductivity (S) Variance of ΔP, P: parameter (–) Variance of Qeff (C/cm2) Standard deviation of ΔIB (A) Standard deviation of ΔIC (A) Standard deviation of ΔID (A) Standard deviation of Δp (–) Standard deviation of ΔVT (V) Standard deviation of drain current factor β (–) Lifetime (S) Time for trap to be unoccupied (S) Auger lifetime (S) Electron Auger lifetime (S) Hole Auger lifetime (S) Base transit time (S) Collector transit and delay time (S) Emitter delay time (S) Electron lifetime (S) Electron lifetime in NPN base (S) Effective electron lifetime (S) Time for trap to be occupied (S) Hole lifetime (S) Hole transit time in NPN emitter (S) Effective hole lifetime (S) Recovery time (S) Shockley-Read-Hall lifetime (S) Magnetic flux (Wb) Potential (V) Ion-Implant dose (cm2) Bulk Fermi potential (V) Barrier height (V) Barrier height without barrier lowering (V) Effective barrier height (V) Electron bulk Fermi potential (V) Barrier height, N-type silicon (V) Hole bulk Fermi potential (V) Barrier height, P-type silicon (V) Barrier height for hot-carrier injection (V) Metal (gate) workfunction (V) Workfunction difference between gate and silicon (V) Surface charge neutrality level (V) Surface Fermi potential (V)

Symbols

ϕSi χ χm χ ox χ Si ψs ψ smax ω

xlix

Silicon workfunction (V) Electron affinity (V) Gate electron affinity (V) Oxide electron affinity (V) Silicon electron affinity (V) Surface potential (V) Maximum surface potential at onset of strong inversion (V) Angular frequency (Radian/s)

Chapter 1

The World Is Analog

Abstract As digital processing extends to more products, an ever-increasing number of analog integrated chips are required. This is because analog processing is essential in allowing the benefits of digital processing to be realized by providing the interface between the real world (analog) and the computer (digital). This chapter covers the diversity of analog applications and voltage requirements and gives a high-level overview of the many process technologies and components that are encountered in the analog world.

1.1

Introduction

The inventions of the microprocessor in 1971 [1] and the digital signal processor (DSP) in 1978 [2] have helped revolutionize the electronics industry. Certainly, looking at the marketplace, one sees a proliferation in the implementation of these digital integrated circuits (ICs) in end applications, such as communication, transportation, entertainment, medical, household appliances, and lighting. Almost every aspect of life is being impacted by this pervasive technology. Hence, there is a sense in the semiconductor industry, and in the media, that this is becoming a digital world. If so, then the reader might question the need for a discussion of analog components in a book such as this. Most of the concepts developed in this book are applicable to both digital and analog components. To understand the need for analog components, one should look more closely at the evolution of digital applications. The march toward a digital world began about 30 years ago, as the PC era was just dawning. Prior to that, it was a world with limited access to computers. Since then, there has been a steady trend of more central processing units (CPUs) per person as a function of time, moving from the era of mainframe systems, where there were maybe hundreds of people to a CPU, to minicomputers and tens of people per CPU, to PCs and a one-to-one relationship, and finally to the Internet age with its proliferation of CPUs per person. The Internet of things (IoT) is a concept that envisions everyday electronic products being interconnected through the Internet [3]. Even a light bulb can be connected via a wireless protocol to communicate with a smartphone [4] to optimize © Springer Nature Switzerland AG 2020 B. El-Kareh, L. N. Hutter, Silicon Analog Components, https://doi.org/10.1007/978-3-030-15085-3_1

1

2

1 The World Is Analog

the lighting in a home at the push of an application. Perhaps the greatest revolution in electronics is the cell phone, with its almost limitless features and applications that have transformed society. This has been enabled by the innovations and evolution of digital technology along the steady path of Moore’s law [5], driving functionality ever higher and costs lower over time, allowing more computing power to enter almost every facet of life. Yet, this digital revolution is not enough to enable the electronics industry to achieve its ubiquitous role in the world or to even enable the aforementioned cell phone to operate. That is because digital computing is based on a man-made construct of 1s and 0s. These signals seldom occur in nature. The world, with which electronics ultimately interacts, is composed of quantities such as pressure, heat, humidity, light, sound, position, and motion, each of which has the attributes of being continuous and varying with time, as opposed to being discrete. They are said to exhibit analog behavior. Hence, for almost every microprocessor or DSP instance, there is typically a series of analog products surrounding it, conditioning and amplifying the signal, and then converting it from its wide-ranging analog roots into the narrow world of 1s and 0s that these digital engines can recognize and process. A typical configuration of analog products around a DSP, the so-called signal chain, is shown in Fig. 1.1. Since the real world is composed of analog signals, the need for analog signal processing to interface to the digital chips continues to exist. And as digital processing extends to more products, both existing ones and ones yet to be created, an ever-increasing number of analog ICs are required. Hence, analog processing is instrumental in allowing the benefits of digital processing to be realized.

Sensor (Analog)

Signal Conditioning (Analog)

Data Conversion (Analog)

Real World Temperature Pressure Position Motion Sound Video Light

Power Management (Analog)

Actuation (Analog)

Signal Conditioning (Analog)

Computation (Digital)

Data Conversion (Analog)

Fig. 1.1 An analog signal chain connects the processor to the “real world”. (Adapted from [6, 7])

1.2 What’s Different About Analog

1.2

3

What’s Different About Analog

If analog products are instrumental in interacting with the outside world, then it is logical to wonder what differentiates these analog ICs. Clearly, if digital ICs could perform the same functions that analog ICs do, there would be an obvious path to integration, that is, the direction the semiconductor industry has been headed for many years. It would be logical to expect analog design considerations, technologies, and manufacturing practices to behave similarly to their digital counterparts. However, in almost every case, this is not so.

1.2.1

Digital Design Considerations

To understand the unique design considerations for analog circuits, one needs to examine the differences in how transistors are used in analog and digital applications. For digital circuit design, the transistor—usually a metal–oxide–semiconductor field-effect transistor (MOSFET)—is typically operated as a voltage-controlled switch, responding to the 1s and 0s necessary for logic implementation. An N-channel MOSFET (NMOS) is shown in Fig. 1.2. The transistor can be viewed as a four-terminal device—gate, source, drain, and body—with the gate used to turn the device on and off through application of the proper voltage (note that all voltages in the MOSFET are referenced to its source terminal). A P-channel MOSFET (PMOS) is also available in complementary MOS (CMOS) logic technologies, commonly used in the industry. The gate material is usually polysilicon (poly) for most CMOS technologies. MOSFETs are discussed in significantly more detail in Chap. 6 but are being shown here briefly to highlight differences between analog and digital considerations. For the NMOS, if the voltage applied to the gate electrode is sufficiently above the threshold voltage (VT) of the transistor, the P-type silicon directly underneath is inverted into a conducting N-type channel, enabling a large current between the source and the drain. In a digital logic configuration, this state can be thought of as a logic level 1 being applied to the gate electrode, biasing the gate in its high state and Gate P-body Source

Gate P+

(a)

P-body

N+

Drain

Drain

Drain

Body

Gate

N+ Gate oxide Channel

(b)

Source

Source

(c)

Fig. 1.2 NMOS transistor. (a) Simplified cross-sectional view. (b) Four-terminal symbol. (c) Three-terminal symbol

4

1 The World Is Analog

turning the transistor on. If the voltage applied to the gate electrode is sufficiently below VT, there is essentially no current between the source and the drain. Here, one can think of the gate as being at a logic level 0, biasing it low, and turning the device off. In digital applications, there are three main parameters of interest—threshold voltage (VT), on-current (Ion), and off-current (Ioff). VT is the voltage at which the transistor becomes conductive, with typical values in the range of 0.4–0.7 V. Ion is a measure of how much current the device conducts when turned on and is driven primarily by device scaling, e.g., channel length and gate oxide thickness—with each new technology generation typically shrinking both through the application of new materials and techniques [8]. Ioff is a measure of the leakage in the MOS switch when the device is turned off. In portable products, battery life is a key concern, and digital circuit blocks, containing anywhere from 10 k to 100 M transistors or more, with each device contributing its own small amount of Ioff, can lead to an unacceptably high system leakage. Hence, Ioff is a primary concern in CMOS logic technology, with low-power technology versions now common, although this can often require a trade-off of Ion performance for reduced Ioff (discussed in Chap. 6). One of the most common building blocks in logic design is an inverter, as shown in Fig. 1.3 for a generic CMOS process. This circuit gives an output at the opposite logic level from the input. In this configuration, the application of a logic level 1 at the input, defined as VIN ¼ VDD, produces a logic level 0 at the output, defined as VOUT ¼ 0 V. This occurs since the NMOS gate-to-source voltage VGS ¼ VDD is well above the NMOS VT, turning it on. The PMOS transistor is off since its input voltage is also VDD so that VGS ¼ VIN  VDD ¼ 0 V, which is below the magnitude of PMOS VT. This pulls VOUT down to 0 V since the NMOS is on. Similarly, if VIN is a logic level 0, or at 0 V, the NMOS is turned off and the PMOS is turned on, pulling VOUT up to VDD, rendering a logic level 1. This is shown in Fig. 1.3. As seen in this example, no other components are required, just an NMOS and a PMOS. This is the simplicity that has made digital CMOS technology the workhorse of the semiconductor industry. As this CMOS technology has scaled, many oncesubtle device effects have become more pronounced. While it is an Fig. 1.3 Schematic view of a CMOS inverter, showing input and output voltage transitions

VDD VDD

VDD

PMOS

VIN

VOUT 0V

0V

NMOS

0 V

1.2 What’s Different About Analog

5

oversimplification to say that a CMOS logic process consists of just a low-voltage NMOS and PMOS, each focused on three key parameters (VT, Ion, and Ioff), this generalization is done to make a point.

1.2.2

Analog Design Considerations

CMOS process technology has likewise become the backbone of most analog designs. However, in many analog applications, the MOSFET is not used as a switch. Rather, it is often operated in the linear mode as a small-signal device, processing signals that are significantly lower than the bias level. By contrast, most digital circuits are large-signal devices, processing 1s and 0s that typically vary in values as high as 1 V. Many aspects of semiconductor devices are inherently nonlinear in their I–V relationships, as can be seen in later chapters. However, at the small-signal level, these nonlinearities can be approximated as straight lines centered at the bias point. This linearization is illustrated in Fig. 1.4a, where the ID– VG characteristics of a MOSFET are shown in the saturation region (discussed in Chap. 6). The bias point in Fig. 1.4b is 1.1 V, but the analog signal (shown as a sine curve) is a few tens of mV. For small enough signal amplitudes, the linear nature of the I–V relationship holds, and the fidelity of the signal can be processed with little distortion or other deleterious effects. The MOSFET is used for sensing, signal conditioning, and amplification, and in transmission gates, among other applications. The operation of the MOSFET is the same as for digital applications; however, the region of operation in its I–V characteristics is often different, as just discussed, and there are frequently many more device design considerations, making its optimization every bit as challenging as its digital counterpart. An application that highlights the many diverse considerations of analog design and their impact on the process technology is a computed tomography (CT) scanner, which embodies both analog and digital ICs in its overall system configuration. This 6 ¥ 10-4 5 ¥ 10-4

2 ¥ 10-4

(a)

(b) ID (A)

4 ¥ 10-4 3 ¥ 10-4

1 ¥ 10-4

2 ¥ 10-4 1 ¥ 10-4 0 0.5

1.0

VG (V)

1.5

2.0

0 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30

VG (V)

Fig. 1.4 IDVG characteristics of an MOSFET operated in the saturation mode. (a) Entire trace. (b) Linear approximation (dashed line) about the VG ¼ 1.1 V bias point and the corresponding smallsignal relationship

6

1 The World Is Analog

Fig. 1.5 Operation of a CT scanner showing an X-ray slice. (Adapted from [9])

is a sophisticated medical imaging device that has seen increasingly widespread use in recent years to provide three-dimensional images of internal body structures. As shown in Fig. 1.5, a CT scanner works by sending a “slice” of X-rays through the patient and then detecting them on an X-ray detector array on the opposite side of the patient. The resulting image collected by the detector array is a function of the relative density of the materials that the X-rays pass through in the patient. By rotating the X-ray generator, and the accompanying detector, about the patient, many different views are collected, which are then processed by a computer to yield a three-dimensional image. Specifically, the X-ray detector array consists of a bank of scintillators that convert the X-rays to visible light. The output of each scintillator is then fed into a photodiode, which converts the light to an electrical signal in the form of a weak current. This current is then converted into a low-level voltage that then must be amplified to a sufficiently high level to enable it to be converted, by means of an analog-to-digital converter (ADC), to the 1s and 0s recognized by the DSP. This signal processing flowchart is shown in Fig. 1.6. While the final imaging computation is done digitally, everything in the signal chain up to the computer involves analog signal processing. The output of each photodiode is on the order of 1 nA and, in this application, is typically converted to a voltage with high precision through the use of an operational amplifier (op-amp) connected as a transimpedance amplifier, as shown in the schematic drawing of Fig. 1.7, which converts current into voltage.

1.2 What’s Different About Analog

7

PhotoDiode

TransImpedance (I to V) Amplifier

Voltage Amplifier

Analog-toDigital Converter

DSP

Analog

Analog

Analog

Analog

Digital

Fig. 1.6 Signal chain flowchart of a typical CT scanner

1 MΩ IIN

+

VOUT

Fig. 1.7 Simplified schematic of an op-amp connected as a transimpedance amplifier, showing inverting (negative sign) and non-inverting (positive sign) inputs to the amplifier

This simple application prompts many analog technology considerations. First, to accurately process a 1 nA input signal, the input bias current of the op-amp must be negligible compared to the signal current in order to minimize errors at the output or the need for extensive error calibration. Both MOSFETs and junction field-effect transistors (JFETs), discussed in Chap. 5, are ideally suited as input devices for these types of applications. Noise is another significant consideration in a low-current application, prompting close attention to the parasitic capacitances associated with the components and particularly the input bias current noise of the input transistors. Finally, for integrating the feedback resistance, a high-valued, accurate, and isolated polysilicon resistor, with minimal parasitic capacitance and resistance change over temperature, must be available in the technology (discussed in Chap. 8). These device and parametric considerations are examples of how even a relatively simple analog function often requires unique process components and parametric considerations. The output of the transimpedance amplifier is a low voltage, approximately 1 mV in this example since the output of the photodiode is 1 nA and the feedback resistor is 1 MΩ. Such a low-level signal is not well suited for the input range of most ADCs, so it must be further amplified before being fed into the converter. This highlights another consideration in analog design—small-signal transistor gain. In analog applications, transistors are routinely used to amplify voltage. A simplified smallsignal model of an MOS transistor in the saturation region (discussed Chap. 6) is shown in Fig. 1.8 [10]. The gate input is represented as an open circuit due to the extremely high input impedance of the device, while conduction is represented by a current source

8

1 The World Is Analog

Fig. 1.8 Simplified smallsignal model for an MOS transistor in saturation

G

D

+

vgs _

ro

gmvgs

Fig. 1.9 MOSFET I–V characteristics (solid lines). The slope of the dash-dot line approximates the resistance, ro, while the horizontal dashed lines show ideal performance

ID (mA/mm)

S

ro

VD (V)

referenced to the gate voltage by a transconductance (gm) that relates voltage to current. If that were all, the MOSFET would be an ideal voltage-controlled current source with infinite voltage gain. However, the presence of a finite output resistance, ro, which is a measure of the slope of the output current of the device, limits the intrinsic voltage gain (Av) of the device (Fig. 1.9). Since the Av of the MOS device is gmro, a primary goal of an analog CMOS technology is to deliver high gm and ro. This is discussed further in Chap. 6. The output resistance of an MOS transistor is influenced by a number of parameters and effects—e.g., channel length, channel doping, drain engineering, draininduced barrier lowering (DIBL), and velocity saturation [11], covered in detail in Chap. 6. While ro is critical for analog performance, it is not an important consideration for a digital technology, where devices are used as switches. Techniques used in digital CMOS technologies to optimize Ion [12] can often seriously degrade not just the output characteristics of an analog device but also its matching and low-frequency noise performance (discussed in Chap. 10) [13]. Returning to the CT scanner example, to achieve a highly accurate representation of the analog signal for the input to the DSP, a successive approximation register (SAR) ADC with 12–16 bits of accuracy is typically used for this conversion [14]. In parts of the ADC, MOSFETs are used as switches, but they must be low-resistance switches to minimize signal losses. Other sections of the ADC depend on highprecision capacitors. Hence, an isolated precision capacitor—either poly–insulator– poly (PIP) or metal–insulator–metal (MIM)—must be added to the process, and these capacitors must exhibit low mismatch, low voltage coefficient of capacitance (VCC), and low dielectric absorption (DA) to enable that high bit-level performance to be achieved. Capacitors are discussed in more detail in Chap. 8. From this brief example, it is apparent that analog applications require additional components—optimized CMOS transistors, poly resistors, and an isolated capacitor

1.2 What’s Different About Analog

9

Table 1.1 Comparison of key MOSFET parametric considerations for digital and analog designs

Parameter VT Ion BVDSS Ioff IDLIN ISUB RSPa ro VT mismatch ID mismatch ID noise a

Digital ✓ ✓ ✓ ✓

Analog ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓

RSP is the specific on-resistance, which is defined as RDS

(on)Area

are at the heart of any analog technology—and these have a lengthy list of requirements. Table 1.1 compares some of the most important MOSFET parametric considerations for analog and digital applications.

1.2.3

Analog Technology and Manufacturing Considerations

The component requirements in analog circuit design necessitate significantly different process technologies than those used in digital applications. Moreover, these requirements change the focus areas in the manufacturing sites where those analog products are built. Operating voltage (VOP) is an important consideration in analog designs. Since analog circuits interface between the highly regulated voltage range of the CPU and the outside world, there is a wide range of voltage conditions that these chips must withstand. Figure 1.10 shows the operating voltage spectrum for analog product applications, with the digital logic case included for reference. A range of almost six orders of magnitude can be seen. The diversity of target applications for ICs is almost limitless, ranging from ingestible sensors [14], to industrial automation, to electronic blasting caps, to automotive engine control. However, the closer in the signal chain one gets to the real-world interface, the more specialized the IC becomes, as it must be tailored to the end application. As one moves toward the DSP, the functions become less specialized, more reusable, and software configurable; hence, the diversity of product types is reduced, as illustrated in Fig. 1.11. This tendency is reinforced by the economics of product development as well. DSPs and microprocessors involve large teams of design and software engineers, designing highly integrated system on chip (SoC) applications and using expensive mask sets in wafer fabrication sites using leading-edge (expensive) technology. By

10

1 The World Is Analog

1000 V 100 V

Electric Vehicles, Trains, Power Distribution LED Lighting, Industrial Telecom, PoE Automotive, LED Drivers, Solar

10 V

Hard Disk Drives, Industrial, Power Management Cell Phones, Power Management, Precision Analog

1V

100 mV 10 mV

1 µV

Digital Logic Audio Signals

Energy Harvesting Signals

RF Signals

Fig. 1.10 The diversity of voltage requirements in analog product applications [7]. Both signal and supply voltages are considered

High Sensor

Diversity of Product Types

Fig. 1.11 Relative diversity in product types along the signal chain, where high means many product types and low means few product types

Amp

ADC

DSP

Low Low

Product Type Complexity

High

contrast, analog ICs are often developed by small teams, with lower integration levels, and utilize less aggressive technology and comparatively cheap mask sets. The difference in the diversity of product types between analog and digital applications has implications in the operating styles of their associated manufacturing sites. Digital logic technology is driven by Moore’s law and is usually at the leading edge of CMOS technology, with a relatively sparse component set and a high number of metallization levels. Hence, a digital CMOS manufacturing site is highly advanced, uses the largest diameter wafers possible, is focused on relatively few technology generations, and is built specifically for the purpose of manufacturing logic technology. Furthermore, such a site typically runs a comparatively low to moderate number of products, most of which run at high volume since these logic products have few variations and cut across many end product applications.

1.2 What’s Different About Analog

11

Table 1.2 Digital versus analog technology manufacturing differences Consideration Number of products Volume per product Technologies used Voltage levels Number of components Second/third order effectsa Number of logic gates Wafer diameter Number of metal levels Feature sizes Manufacturing site age a

Digital case Few to moderate Typically high Few Low Few Few, but increasing Typically > 1 M Typically 300 mm Typically 6–10 Typically < 65 nm Relatively new

Analog case Many Typically low Many Low to very high Many Always many Typically < 200 k Typically 200 mm Typically 3–5 Typically > 90 nm Relatively old

Second-/third-order effects refer to matching, noise, temperature and voltage coefficients

Conversely, analog products focus on applications requiring precision and higher voltage capability. As a result, technologies generally have larger feature sizes, a large component set, and relatively few metallization levels. Correspondingly, manufacturing sites use less-advanced equipment and smaller diameter wafers, handle a wider mix of process technologies, and run a large number of products most of which have low to moderate volume. Manufacturing sites are not built explicitly for analog technologies, but transition from logic usage when the CMOS logic technology roadmap outruns the site’s capabilities. This conversion can be complicated, since the technologies prioritize different needs—e.g., logic uses many metallization levels, whereas analog needs very few layers due to its lower integration level—that can often result in an equipment capacity mismatch to the product applications. Table 1.2 summarizes some of the key technology and manufacturing differences associated with digital and analog technologies and manufacturing procedures. Likewise, Table 1.3 highlights the mind-set change that must permeate different parts of the organizations as it transitions from supporting CMOS logic to analog technologies.

1.2.3.1

Role of Bipolar Transistors in Analog Technology

As stated above, CMOS has become the preferred baseline technology for analog applications. Previously, technologies based on the bipolar junction transistor (BJT) were commonplace. The BJT possessed many properties—current gain, voltage capability, and less dependence on surface cleanliness—that made it an ideal component for analog design. However, as digital CMOS technologies evolved, the lower manufacturing complexity of CMOS ultimately triumphed over the benefits of bipolar (Chap. 9). In modern analog designs, BJTs are typically used only for voltage references and occupy a very small portion of the chip (Fig. 1.12). As such,

12

1 The World Is Analog

Table 1.3 Analog mind-set changes Organization Technology development PDKa SPICEb modeling Electrostatic discharge (ESD) Manufacturing

Product engineering Sales and marketing Management

Mind-set change Higher voltages, more components, more parameters to monitor and specify More components, more sample layout options, more consideration of parasitic effects More second- and third-order effects, more model-to-silicon validation needed Wider assortment of pin applications. ESD development “on the fly” in many cases Low-volume products, time-to-market implications from scrapped lots, high product mix, mask storage in the manufacturing site, long life cycles, more and tighter specs High product mix, mostly low volume, hard to do yield improvement Must go deeper into customer accounts to drive volume business Patience to grow the business, which seldom has “hockey stick” product ramps

a

PDK, Process Delivery Kit SPICE, Simulation Program with Integrated Circuit Emphasis, which is used to simulate generalpurpose circuits [15] b

Fig. 1.12 Die area breakout of typical analog product by component

Saw Street

Resistors

Bond Pads, ESD Capacitors

Metal Routing LV Analog CMOS DECMOS

HV Analog CMOS Power Transistor HV Logic LV Logic BJT CMOS CMOS

there is very little special processing done to optimize the BJT performance. The bipolar transistor is dominant in high-speed analog technologies, to be discussed later, and is still an important component in analog design.

1.3

Integration or Not

One of the key imperatives in semiconductor technology is integration, driven by the approximate doubling of transistor density every 2 years in the case of digital CMOS. This is at the heart of the cost structure of the semiconductor industry,

1.3 Integration or Not

13

enabling this industry to be unique in offering a declining price for its products over time. With this directive, a major trend in the industry is to integrate all system functions on a single SoC. Recently, the distinction between a digital IC and an analog one has blurred as the need for integration at the system level has demanded more functions be on the same chip. This has occurred on both sides of the ledger—digital SoCs adding analog functionality and analog products adding more logic capability. On the digital-intensive side, this has led to technology extensions, such as mixed-signal CMOS (MS CMOS) and radio frequency CMOS (RF CMOS), which incorporate logic CMOS and some basic non-process optimized analog components. This is mainly done for cost reasons since the analog circuitry occupies only a small fraction of the die size. However, the availability of analog enables significant integration in some types of products, e.g., the inclusion of the analog baseband functions on a DSP where the performance is not overlying demanding, thus improving overall system cost. For analog-intensive applications, merging analog and digital functions is commonly referred to as analog CMOS. In this case, analog components dominate the chip area, but some modest amount of logic is added—from fewer than 1000 gates up to as many as 300,000—to simplify the overall system design. In this case, the digital performance may be sacrificed, again for cost reasons. It is reasonable to wonder why stand-alone analog ICs are not simply integrated into the digital SoC, in effect absorbing the entire signal chain illustrated previously. In fact, this occurs routinely, with analog and RF circuitry becoming higher precision, faster, lower power, and cheaper by taking advantage of the advancements in digital technology. However, several factors limit its wholesale application across the product space: Voltage As shown earlier, digital logic levels have dropped to below 1 V to accommodate device scaling, while analog functions cover a tremendous range of voltages, leading to integration incompatibilities (Fig. 1.10). Performance Increasing requirements for signal-to-noise ratio, resolution, etc. often forces the use of dedicated, optimized analog ICs, and accompanying process technologies, to provide an acceptable solution at the system level. Timing Implementing analog functions in a leading-edge logic technology frequently requires new circuit topologies to be developed due to the reduced voltage capabilities of the process. Logic-intensive SoCs migrate quickly from generation to generation, forcing time-to-market pressures for analog solutions. Advanced CMOS processes enable design techniques that leverage the digital transistors for implementing analog functions. Techniques such as dynamic element matching [16–18] utilize averaging techniques, enabled by the availability of dense, low-cost logic gates in the technology. These are used to minimize component mismatch for small device sizes, whereas using conventional analog design methods

14

1 The World Is Analog

would require large device sizes to produce this same mismatch performance. This technique has enabled certain types of ADCs [19, 20] to be realized on standard CMOS processes with improved speed, resolution, and power consumption. The above discussion illustrates a second imperative in the semiconductor industry: performance. Dedicated analog product ICs are generally how new high-performance features enter the market, but over time the evolving digital CMOS technologies enable these once stand-alone functions to be integrated with similar or better performance. Meanwhile, improvements in analog technology and design technique push standalone analog products to new levels of performance, and the cycle repeats.

1.4

Analog Process Technologies

Figure 1.10 highlights the diversity of analog products. To address this, a large portfolio of specialized technologies is required. These are not easily integrated into logic-based technologies; hence, they are unique processes, each finely tuned with its own set of components, voltage capability, and optimized parameters. This large technology portfolio poses a challenge to integrated device manufacturer (IDM) and foundries that must develop and maintain them, particularly when each process supports only a moderate amount of business. Comparatively, digital technologies run very high wafer volumes, with just a few technology generations needed at a given time. Analog processes typically support a large number of components, each with its own set of key parameters that must be specified and monitored, thereby requiring a high level of overhead for the manufacturing team and device technologists. However, this diverse technology requirement also presents an opportunity for nimble and patient IDMs or foundries to specialize in different areas where they can differentiate. Historically, IDMs have dominated in this space, as they have an inherent advantage of having design and technology experts in the same company who can collaborate closely to optimize components to meet specific design needs. However, foundries have begun to compete in this area. Some of the major analog technologies and their key components are reviewed below, where a baseline low-voltage CMOS (LV-CMOS) logic technology is used as a reference point (Table 1.4).

1.4.1

Mixed-Signal CMOS Technology

The most common extension from the logic CMOS base is mixed-signal CMOS, or simply MS CMOS (Table 1.5). It is largely a digital CMOS process with analog components added—mainly a poly resistor, an isolated MIM capacitor, and the optional analog high-voltage CMOS (HV-CMOS) transistors built using several

1.4 Analog Process Technologies

15

Table 1.4 Main features of CMOS logic technology Technology Key components (active)

Logic LV-NMOS and PMOS High-density SRAMa High packing density High Ion Low Ioff 7–45 nm Microprocessors, DSPs, GPUs

Key component requirements

Technology generations Typical products a

SRAM, static random access memory

Table 1.5 Main features of mixed-signal CMOS technology Technology Key components (active) Key components (passive) Key component requirements

Technology generations Typical products

Fig. 1.13 Isolated NMOS transistor

MS CMOS LV digital CMOS HV analog CMOS Poly resistor MIM capacitor Leverage logic CMOS devices Analog CMOS (VOP ¼ 1.8–3.3 V) Drain-extended CMOS, DECMOS VOP ¼ 5 V Resistor RS ~ 300 Ω/☐ Capacitance density ~1 fF/μm2 Low noise and device mismatch 23 generations behind leading-edge digital logic CMOS Digital audio, audio codecs, high-performance data converters

LV Gate Oxide Silicide

Poly Gate N+

STI

STI LV P-well

Deep N-well N LDD P-substrate

LV N-well

dedicated process modules that can operate to 2.5 or 3.3 V compared to the baseline low-voltage CMOS operating at a nominal 1.2 V. Due to noise propagation from the switching logic circuits into sensitive analog function blocks, a deep N-well module is added to create an isolated NMOS (Fig. 1.13). This one-mask adder enables the digital and analog circuit blocks to coexist on one chip, simplifying the design and minimizing unintended cross talk in the circuit [21].

16

1 The World Is Analog Metal

Dielectric

STI

M5

N-well Silicide Block Oxide

M4 P+ Poly

Silicide

P-substrate

(a)

M3 M2

(b)

Fig. 1.14 MS CMOS passive components. (a) Poly resistor. (b) Lateral flux capacitor (dark bars form one electrode and light ones the other)

A poly resistor is realized by utilizing the PMOS or NMOS poly with the low-resistance silicide formation blocked in the body of the resistor by means of an oxide layer using a silicide block masking step (Fig. 1.14a). The MIM capacitor, shown in Fig. 1.14b, sometimes referred to as a lateral flux capacitor (LFC) [22], can be built using existing metallization layers in an interdigitated fashion, without added process complexity. Depending upon the layout methodology, the design rules, and the number of metal levels, a capacitor density comparable to that of a parallel plate capacitor can be obtained. A drain-extended NMOS (DENMOS) is shown in Fig. 1.15 [23]. It is integrated in a CMOS process without added complexity (Chap. 9).

1.4.2

RF CMOS Technology

RF technology has leveraged device scaling more than any other technology, evolving from a bipolar-based technology to a CMOS-based one that is essential in wireless applications [24]. RF CMOS has many of the same component requirements as MS CMOS but adds RF-specific devices such as an inductor and a variable reactor (varactor) with dedicated layouts to enhance their quality factor, Q1 (Chap. 8). RF performance can be degraded by device parasitics, which must be modeled accurately to achieve design success [15]. Table 1.6 shows a summary of the RF CMOS technology considerations.

1.4.3

RF BiCMOS

While RF CMOS processes have become the dominant technology for RF applications, radio frequency bipolar CMOS (RF BiCMOS) still has niche uses in the

1

Q is a measure of the energy loss relative to the stored energy of a resonator.

1.4 Analog Process Technologies Fig. 1.15 Drain-extended NMOS cross-sectional view

17

Source

Body

STI

Gate

NSD Poly

Drain

STI P+

STI N+

P-well Channel

Silicide

N+

N-well Drain-extended drift region using N-well

P-substrate

Table 1.6 Main features of RF CMOS technology Technology Key components (active)

Key components (passive)

Key component requirements

Technology generations Typical products

RF CMOS LV digital CMOS HV analog CMOS LV and HV isolated NMOS DECMOS Poly resistor MIM capacitor Inductor Varactor Leverage logic CMOS devices HV-CMOS (VOP ¼ 1.8–3.3 V) Resistor RS ~ 300 Ω/☐ Capacitance density ~1 fF/μm2 DECMOS VOP ¼ 5 V Inductor Q > 10 Low noise and device mismatch Varactor tuning range > 2 1–2 generations behind leading-edge digital logic CMOS Cell phone radios, transceivers, GPS, WLAN, Bluetooth

Drain-extended CMOS (DECMOS, Chap. 7) is commonly integrated into the RF CMOS SoCs, typically to enable voltage references and high-voltage battery charger circuits

industry. The key component in RF BiCMOS is the bipolar junction transistor (BJT), in particular the NPN device, which is optimized for high-frequency applications using special materials such as silicon–germanium (SiGe) and silicon–germanium– carbon (SiGe:C) [25]. In some cases, fully complementary RF BiCMOS processes, utilizing SiGe [26], have been developed for high-speed analog applications such as amplifiers, comparators, and data converters [27]. A summary of the RF BiCMOS technology is given in Table 1.7. The NPN transistor is discussed in detail in Chap. 5.

18

1 The World Is Analog

Table 1.7 Main features of RF BiCMOS technology Technology Key components (active)

Key components (passive)

Key component requirements

Technology generations Typical products

1.4.4

RF BiCMOS Vertical NPN, PNP (optional) LV digital CMOS HV analog CMOS LV and HV isolated NMOS DECMOS Poly resistor MIM capacitor Inductor Varactor Leverage logic CMOS devices Analog CMOS (VOP ¼ 2.5–3.3 V) Resistor RS ~ 300 Ω/☐ Capacitance density 1–2 fF/μm2 DECMOS VOP ¼ 5 V Inductor Q > 10 Varactor tuning range > 2 65–180 nm RF transceivers, LNAs, PAs, amplifiers, and data converters

Analog CMOS Technology

Analog CMOS technology is similar to MS CMOS but places much more emphasis on the analog attributes of the components such as transistor noise, component matching, temperature and voltage coefficients, and many others. This process is based on logic CMOS, which has been reoptimized for analog performance. Noise is improved by replacing nitrided oxide (NO) gate dielectrics with pure thermal oxides [28]. A variety of poly resistors, including one with high sheet resistance, and a planar parallel plate MIM capacitor with a low-voltage coefficient are typically provided. In addition, higher-voltage DECMOS is provided for applications requiring up to 20–30 V (Chap. 7) [29]. Equally important in analog CMOS is the extensive characterization needed on all components to document the second- and third-order effects, such as matching, temperature coefficients, and voltage coefficients (Chaps. 8 and 10). These subtle component features must then be added to device models and simulations to enable more accurate designs for analog products. Analog CMOS is the baseline technology used for analog-intensive performance. Since the product requirements are diverse, there are often needs for specialized components to be added into the baseline process. Examples are precision thin-film resistors (TFR) [30], low dielectric absorption capacitors [31], buried channel PMOS [32], and JFETs for improved 1/f noise performance. Table 1.8 summarizes the analog CMOS technology.

1.4 Analog Process Technologies

19

Table 1.8 Main features of analog CMOS technology Technology Key components (active)

Key components (passive)

Key component requirements

Technology generations Typical products

1.4.5

Analog CMOS LV digital CMOS (optional) HV analog CMOS LV and HV isolated NMOS DECMOS HV low-VT analog CMOS Poly resistor MIM capacitor Thin-film resistor (optional) Leverage logic CMOS devices Analog CMOS (VOP ¼ 5 V) DECMOS VOP ¼ 20–30 V Resistor RS ~ 1 kΩ/☐ Capacitance density ~ 2 fF/μm2 Low noise and device mismatch TFR temperature coefficient ~ 0 65–250 nm Sensors, amplifiers, and data converters

Bipolar-CMOS-DMOS (BCD) Technology

Power management applications comprise a large and growing market share, driven by energy efficiency and long battery life demands. These require a technology that can integrate switches capable of efficiently handling large currents (up to 20 A) and voltage (typically up to 24 or 60 V). Bipolar-CMOS-DMOS (BCD) technology has become a mainstream process in most IDMs and foundries [33–35]. The BCD process is often based on analog CMOS, with the addition of a power transistor, the lateral double-diffused MOS (LDMOS) shown in Fig. 1.16 (Chap. 7). The goal of the LDMOS is to provide the lowest specific on-resistance (RSP) for a given operating voltage, which means that it consumes the least possible space to meet the product requirements. To optimize the LDMOS for lowest RSP, typically 2–3 masking steps are inserted into the analog CMOS process flow. Additionally, special (thick) metallization is commonly used to reliably accommodate the high on-chip currents while minimizing parasitic metal resistances [36]. Table 1.9 summarizes the BCD process technology. BCD voltage requirements have increased over time as new applications emerge and push the needs above the previous 60 V level that was common for automotive and motor control. Examples of this are Power over Ethernet (PoE), which requires nominal 85 V capability, telecom at 120 V, light-emitting diodes (LED) lighting, and AC/DC converters in the industrial space [37], where up to 700 V or higher capability is required.

20

1 The World Is Analog

Isolation Region

Gate

Drain

STI

Source/Body

Gate

STI N-drift

P+ N+ P-body

P-epi

N-well

Drain Silicide

STI N+

N+

NSD Poly

Channel

STI

STI

N+ N-drift N-well

N+ Buried Layer P-substrate

Fig. 1.16 N-channel LDMOS cross-sectional view Table 1.9 Main features of bipolar-CMOS-DMOS technology Technology Key components (active)

Key components (passive) Key component requirements

Technology generations Typical products

1.4.6

Bipolar-CMOS-DMOS (BCD) LV digital CMOS (optional) HV analog CMOS LV and HV isolated NMOS DECMOS HV low-VT analog CMOS N-channel LDMOS P-channel LDMOS (optional) Poly resistor MIM capacitor Thick power metallization LV-CMOS (optional) Analog CMOS (VOP ¼ 5 V) DECMOS VOP ¼ 12–65 V LDMOS VOP ¼ 12–60 V Resistor RS ~ 1 kΩ/☐ Capacitance density 1–2 fF/μm2 Low noise and device mismatch 65–250 nm LED lighting, cell phone PMICs, solar inverters, class-D amplifiers, catalog power management

Nonvolatile Memory

In addition to the growing need for on-chip SRAM, some amount of nonvolatile memory (NVM) has become a standard requirement in analog ICs and, correspondingly, across most analog technologies. The uses for NVM can vary from simple post-package adjustments of certain parameters, to the storage of calibration

1.5 Analog Technology Roadmaps

21

coefficients, to embedded microcontrollers, each with an increasing number of memory bits required. While NVM is important, it is not a focus of this book.

1.5

Analog Technology Roadmaps

A roadmap is an important tool in showing the evolution of a particular technology over time. This contains the need for a set of components, their specifications and voltage capability, the need for new materials and wafer diameter, and other parameters. A roadmap requires the technology and design teams to collaborate and brainstorm on future needs. A technology development cycle (from start to qualification) can take from 2 to 4 years. Lead times for new equipment can take up to 1 year or more, depending on the technology generation and the process complexity involved, so good planning is required. The International Technology Roadmap for Semiconductors (ITRS) is available for memory technologies, logic-intensive CMOS and its RF CMOS and MS CMOS derivatives [38]. However, there is little published data for the analog-intensive technologies. While analog technology was once the strict domain of IDMs, whose roadmaps were defined separately and held as proprietary information, the emergence of analog foundries has started to change the dynamic in the industry. Foundries use technology roadmaps as part of their competitive marketing materials, so it has become somewhat easier to do analog technology benchmarking. Analog technology roadmaps are defined through constant sampling of the marketplace by the process technology team and discussions with product development and design teams, located either internally (in the IDM case) or externally (for the foundry case). The goal of these interactions is to learn the direction of the market for a particular class of products over time, or to discern the emergence of a new class of products, and then to understand what components and technology are required to build those products. An overview of a roadmap methodology is shown in Fig. 1.17. By driving from the product requirements to the circuit architecture and blocks needed to achieve these product specs, the design team can extract the necessary component specs that can enable the product to meet its performance targets. This often requires extensive iteration between the teams over a period of months, with hypothetical processes defined and hypothetical circuits evaluated, to understand process and design tradeoffs for these future technologies. With this information, the process technologists

Product Specs

Circuit Specs

Component Specs

Technology Specs

Fig. 1.17 A high-level example of the methodology employed for defining a process technology

22

1 The World Is Analog

can create a roadmap into the future, which must be frequently refreshed with current trends. Analog technology can be profoundly affected by events in digital technology. If these “outside” variables are not well understood, major disruptions in the market could be missed. The abrupt shift from RF BiCMOS to RF CMOS was driven by the wireless market dynamics (the low-cost, one-chip cell phone), the vastly improving RF performance of MOSFETs on advanced digital technologies, and evolving circuit techniques that could apply these improvements to new products. Earlier, hard disk drive read channels based on RF BiCMOS were completely replaced by CMOS. Stand-alone analog technologies must continue to shrink to smaller feature sizes, as they have in the past, but likely never approaching the amount observed in digital CMOS technologies. Scaling significantly reduces the area of logic gates and the speed of low-voltage analog and RF devices and enables new “hybrid” design concepts that leverage low-cost digital gates to improve analog circuit characteristics. Component matching and LDMOS on-resistance also benefit from improvements in lithography. Hence, the analog technology roadmaps depend very much on the end application. Technologies targeting high-volume markets should experience faster scaling due to a SoC-based approach that integrates system functions. Meanwhile, technologies aimed at lower volume, less highly integrated products can expect a slower scaling pace. This is where the strength of analog technology lies. It does not require the latest equipment set, the most current manufacturing site, or cutting-edge lithography. It is a technology based less on new tools and materials and more on components, voltage, and precision. There is little published roadmap documentation, leaving room for innovation and positioning in the market. Analog components and technology enable personality to be added to the end products, which is why analog is critical in extending the digital revolution and why a book on analog components was written.

References 1. M.E. Hoff Jr, S. Mazor, F. Faggin, Memory system for a multi-chip digital computer, U.S. Patent 3,821,715, 28 June 1974 2. G. Brantingham and R. Wiggins, Speech synthesis integrated circuit device, U.S. Patent 4,209,836, 24 June 1980 3. N. Gershenfeld, R. Krikorian, D. Cohen, The Internet of things. Sci. Am., 76–81 (2004) 4. J. Yoshida, NXP’s foray into ‘internet of things’ starts with light bulbs. EE Times (May 17, 2011) 5. G. Moore, Cramming more components onto integrated circuits. Electronics 38(8), 114–117 (1965) 6. Texas Instruments, Analog Signal Chain Guide (Rev. A), www.ti.com, technical documents 7. L. Hutter, High-performance technologies for an analog-centric world, in Analog Leaders Forum, (Dongbu HiTek, Seoul, 2011)

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8. S. Natarajan, M. Armstrong, M. Bost, R. Brain, M. Brazier, C.-H. Chang, V. Chikarmane, M. Childs, H. Deshpande, K. Dev, G. Ding, T. Ghani, O. Golonzka, W. Han, J. He, R. Heussner, R. James, I. Jin, C. Kenyon, S. Klopcic, S.-H. Lee, M. Liu, S. Lodha, B. McFadden, A. Murthy, L. Neiberg, J. Neirynck, P. Packan, S. Pae, C. Parker, C. Pelto, L. Pipes, J. Sebastian, J. Seiple, B. Sell, S. Sivakumar, B. Song, K. Tone, T. Troeger, C. Weber, M. Yang, A. Yeoh, K. Zhang, A 32 nm logic technology featuring 2nd generation high-k + metal-gate transistors, enhanced channel strain and 0.171um2 SRAM cell size in a 291 Mb array. IEEE IEDM Tech. Digest, 1–3 (2008) 9. J. Scampini, Introduction to computed tomography (CT) medical imaging, Tutorial 4682., Maxim website http://www.maximintegrated.com/en/app-notes/index.mvp/id/4682, May 2010 10. K.M. Cao, W. Liu, X. Jin, K. Vasanth, K. Green, J. Krick, T. Vrotsos, C. Hu, Modeling of pocket implanted MOSFETs for anomalous analog behavior. IEEE IEDM, Tech. Digest, 171–174 (1999) 11. S. Thompson, P. Packan, M. Bohr, MOS scaling: Transistor challenges for the 21st century. Intel Tech. J. 1-19, Q3 (1998) 12. S. Ekbote, K. Benaissa, B. Obradovic, S. Liu, H. Shichijo, F. Hou, T. Blythe, T.W. Houston, S. Martin, R. Taylor, A. Singh, H. Yang, G. Baldwin, 45 nm low-power CMOS SoC technology with aggressive reduction of random variation for SRAM and analog transistors. VLSI Tech. Symp., 160–161 (2008) 13. R. Baker, IEEE press series on microelectronic systems, in CMOS Circuit Design, Layout, and Simulation, 3rd edn., (Wiley, 2010) 14. Freescale News Release, Freescale introduces Kinetis KL02, world’s smallest ARM powered microcontroller, Feb 26, 2013 15. L. W. Nagel and D. O. Pederson, SPICE (Simulation Program with Integrated Circuit Emphasis), Memorandum No. ERL-M382, University of California, Berkeley, Apr 1973 16. G. Ritchie, J. Candy, W. Ninke, Interpolative digital-to-analog converters. IEEE Trans. Comm. COM-22(11), 1797–1806 (1974) 17. I. Galton, Why dynamic-element-matching DACs work. IEEE Trans. Circuits. Syst. Express Briefs 57(2), 69–74 (2010) 18. G. Temes, J. Candy, A tutorial discussion of the oversampling method for A/D and D/A conversion. IEEE Symp. Circuits Syst., 910–913 (1990) 19. G. Taylor, I. Galton, A mostly-digital variable-rate continuous-time delta-sigma modulator ADC. IEEE J. Solid State Circuits 45(12), 2634–2646 (2010) 20. V. Rentala, V. Srinivasan, V. Wang, S. Ramaswamy, B. Haroun, M. Corsi, Low power ADCs for wireless communications. IEEE Midwest Symp. Circuits Syst., 694–697 (2012) 21. K. Joardar, Substrate crosstalk in BiCMOS mixed mode integrated circuits. Solid State Electron. 39(4), 511–516 (1996) 22. R. Aparicio, A. Hajimiri, Capacity limits and matching properties of lateral flux integrated capacitors. IEEE Conf. Custom Integrated Circuits, 365–368 (2001) 23. J.C. Mitros, C.Y. Tsai, H. Shichijo, K. Kunz, A. Morton, D. Goodpaster, D. Mosher, T.R. Efland, High-voltage drain extended MOS transistors for 0.18um logic CMOS process. IEEE Trans. Electron Devices 48(8), 1751–1755 (2001) 24. D. Buss, B.L. Evans, J. Bellay, W. Krenik, B. Haroun, D. Leipold, K. Maggio, J.-Y. Yang, T. Moise, SoC CMOS technology for personal internet products. IEEE Trans. Electron Devices 50(3), 546–556 (2003) 25. S. Subbanna, G. Freeman, S. Koester, K. Rim, A. Joseph, D. Harame, High-performance silicon-germanium technology. DRC Tech. Digest, 195–196 (2005) 26. B. El-Kareh, S. Balster, W. Leitz, P. Steinrnannl, H. Yasuda, M. Corsi, K. Dawoodi, C. Dirnecker, P. Foglietti, A. Haeusler, P. Menz, M. Ramin, T. Schamagl, M. Schiekofer, M. Schober, U. Schulz, L. Swanson, D. Tatman, M. Waitschul, J.W. Weijtmans, C. Willis, A 5 V complementary-SiGe BiCMOS technology for high-speed precision analog circuits. IEEE BCTM Proc., 211–214 (2003)

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27. R. Payne, M. Corsi, D. Smith, T.-L. Hsieh, S. Kaylor, A 16b 100-160 MS/s SiGe BiCMOS pipelined ADC with 100dBFS SFDR. IEEE Solid-State Circuits Conf., 2613–2622 (2010) 28. K. Chew, K. Yeo, S. Chu, Impact of technology scaling on the 1/f noise of thin and thick gate oxide deep submicron NMOS transistors. IEEE Circuits Devices Syst. Proc. 151(5), 415–421 (2004) 29. Y. K. Choi, I. Y Park, H.-C. Lim, M.Y. Kim, C.J. Yoon, N.-J Kim, K.D. Yoo, and L. N. Hutter, “A versatile 30 V analog CMOS process in a 0.18um technology for power management applications,” ISPSD, 219–222, 2011 30. V. Menon, Applications drive analog technology development and innovation, Key note, ISQED (2012) 31. J. Fattaruso, M. De Wit, G. Warwar, K. Tan, R. Hester, The effect of dielectric relaxation on charge-redistribution A/D converters. IEEE J. Sold-State Circuits 25(6), 1550–1561 (1990) 32. L. Hutter, J. Hellums, Analog CMOS technology. Semicon Japan (1999) 33. C. Contiero, P. Galbiati, A. Merlini, A. Moscatelli, F. Tampellini, L. Vecchiet, Trends and Issues in BCD Smart Power Technologies (ESSDERC, 1999), pp. 111–118 34. S. Pendharkar, R. Pan, T. Tamura, B. Todd, T. Efland, 7 to 30 V state-of-art power device implementation in 0.25um LBC7 BiCMOS-DMOS process technology. ISPSD, 419–422 (2004) 35. K. Ko, I.Y. Park, Y.K. Choi, C.J. Yoon, J.H. Moon, K.M. Park, H.C. Lim, S.Y. Park, N.J. Kim, K.D. Yoo, L.N. Hutter, BD180LV – 0.18um BCD technology with best-in-class LDMOS from 7 V to 30 V. Intnl. Symp. Power Semicon. Devices, 71–74 (2011) 36. A. Kalnitsky, Y. Tseng, T. Chien, C. Chang, F. Tsui, 1 Milli-Ohm/Square Bondable PostPassivation Interconnect for Power Management Technologies (Power SoC, 2012) 37. T. Karino, O. Sasaki, M. Yamaji, H. Sumida, 700 V PIC technology based on 0.35um design for AC/DC power units. Intnl. Symp. Power Semicon. Devices, 209–212 (2012) 38. The International Technology Roadmap for Semiconductors (ITRS) http://www.itrs.net

Chapter 2

Review of Single-Crystal Silicon Properties

Abstract A review of single-crystal silicon properties is essential to understanding silicon components. The objective of this chapter is to highlight only those semiconductor properties that are most important to analog (and digital) silicon device operation and characteristics discussed in the following chapters. The chapter covers carrier concentrations and thermal-equilibrium statistics, carrier transport under lowand high-field conditions, and minority-carrier lifetime and diffusion length.

2.1

Introduction

Solids and liquids contain 1022–1023 atoms/cm3. In crystalline solids, the elements are stacked in a periodic pattern. When the periodicity extends throughout the sample, one speaks of a single crystal (or monocrystal), as opposed to a polycrystal which consists of small crystallites, called grains, arranged in random directions and adhering together at grain boundaries. Noncrystalline solids are said to be amorphous. Typically, solids assume the crystalline state because this is the packing of minimum energy. A review of silicon single-crystal properties is essential to understanding silicon components. The objective of this chapter is to highlight only those semiconductor properties that are most important to analog silicon device operation and characteristics discussed in the following sections. Detailed treatments of semiconductor physics can be found in Refs. [1–6] at the end of the chapter. Important properties of the silicon crystal are given in the Appendix B.

2.2

Crystal Structure

Silicon, germanium, and carbon crystals belong to the cubic crystal system and have the diamond structure represented in three dimensions in Fig. 2.1 and in a two-dimensional projection in Fig. 2.2. The crystal consists of stacked cubes like that shown in Fig. 2.1. Each atom is surrounded by four others with which it forms © Springer Nature Switzerland AG 2020 B. El-Kareh, L. N. Hutter, Silicon Analog Components, https://doi.org/10.1007/978-3-030-15085-3_2

25

26 Fig. 2.1 Three-dimensional representation of unit diamond cell. Dark atoms define the unit sub-cell. Lattice constant a ¼ 0.543 nm

2 Review of Single-Crystal Silicon Properties

a/2

a

Fig. 2.2 Projection of atoms in Fig. 1.1 onto the plane of the page. Numbers indicate vertical distances in fractions of lattice constant a from the page, which is taken to be zero

1/2

0,1 1/4 1/2

3/4

1/2

0,1 1/4

3/4 0,1

0,1

1/2

0,1

covalent bonds, i.e., bonds between two adjacent atoms are formed by two valence electrons, one from each atom contributing to the bond. The bonds are visualized as localized bars along which electrons shuttle back and forth with opposite spins, as illustrated schematically in Fig. 2.3a. This type of bonding is very strong, highly localized, and directional because the distribution of valence electrons becomes shifted to the nearest neighbors. The unit cell configuration in a diamond crystal is best described by projecting the cube onto a two-dimensional plane, as shown in Fig. 2.2 [1]. The plane of the paper is chosen as one of the cube planes. The numbers define the location of the atom centers relative to the plane of the paper in fraction of the cube edge a. For example, atoms located at the centers of cube faces normal to the page are labeled ½. In a unit cube, there are eight corner atoms, each shared between eight adjacent

2.3 Energy Gap and Intrinsic Carrier Concentration Fig. 2.3 Schematic representation of Si bonds. (a) Crystal at about 0 K, all bonds in place. (b) Thermal generation of electron–hole pair. (c, d) Illustration of thermal motion of a hole

Si

Si

27

Si

Si

Si

Si

eSi

Si

Si

Si

Si

Si

Si

Si

Si

Si

(a) Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

(c)

Si

Si

Si

B

h+ Si

Si

(b)

Si

A

h+

Si

Si

Si

h+

Si

(d)

cubes; six face-centered atoms, each shared between two adjacent cubes; and four full atoms within the cube. One should remember that the structure is three-dimensional and that the bonds form a continuous three-dimensional chain throughout the crystal. The electrons are not constrained to one particular bond. Instead, they can move throughout the crystal, exchanging places with other valence electrons without creating current. Thus, the bonding electrons belong to the entire crystal rather than to local atoms. At normal operating temperatures, atoms occupy, on the average, fixed positions relative to each other. The atoms are, however, in constant vibrations about their equilibrium positions.

2.3

Energy Gap and Intrinsic Carrier Concentration

When a pure silicon crystal is near 0 K, all valence electrons remain locally bound to their covalent bonds since they do not have sufficient energy to break loose (Fig. 2.3a). In this case, no free electrons are present and the crystal behaves like a perfect insulator. As the temperature is increased, the amplitude of vibration of lattice atoms also increases around their equilibrium positions. A fraction of the vibrational energy is transferred to valence electrons. Some electrons can acquire sufficient energy to break loose from their bonds and move randomly in the crystal (Fig. 2.3b). A vacancy is left where an electron breaks loose from a bond. The vacancy behaves like a positive carrier that is conveniently called a hole that randomly moves in the

28

2 Review of Single-Crystal Silicon Properties

crystal, independently of the free electron. The motion of holes is illustrated in Fig. 2.3c, d. Figure 2.3c shows a hole at a random position A. A nearby bound electron can move into the hole, completing the bond in Fig. 2.3c, eliminating that hole, and creating a new one nearby, as shown in Fig. 2.3d, and so on. It is convenient to describe this process as the motion of a hole although it is a bound electron that moves in the opposite direction. The charge of electrons and holes are equal in magnitude but opposite in sign. Free electrons and holes are generated in pairs and their number increases with increasing temperature. Under normal operating conditions, the silicon atoms remain fixed around their equilibrium positions. The energy required to break a silicon bond is about 1.1 eV at 25  C.1 The crystal as a whole remains neutral. During their random motion, free electrons and holes may recombine, thus annihilating a positive and a negative charge at the same time. In pure silicon, the concentrations of electrons and holes remain equal since their generation and recombination occurs in pairs. In such a case, silicon is said to be intrinsic.

2.3.1

Energy Band Model

Energy bands in semiconductors are discussed extensively in reference books on solid-state physics [1–6]. The sole objective of this section is to highlight, in simple terms, the energy band model concepts that are most pertinent to understanding the properties of silicon devices. An electron in vacuum is allowed to occupy a continuum of energy levels, similar to the classical case of molecules in an atmospheric column that can occupy any energy level without restrictions. From quantum mechanics, it is known that when an electron is bound, e.g., as in an isolated hydrogen atom, it is allowed only discrete energy levels separated by energy gaps. When two hydrogen atoms are far from each other, they behave as two isolated entities with independent, identical sets of discrete energy levels. As the atoms are brought close to each other, their wave functions begin to overlap so that the electrons of the two atoms begin to interact. Electrons in the first atom can also occupy energy levels in the second and vice versa. A study of energy levels shows that, in the limit, when a hydrogen molecule is formed, each energy level of the isolated hydrogen atom splits into two levels, one above and one below the energy level in an isolated atom. In a silicon crystal of N identical lattice atoms, there exists the possibility of exchange of every valence electron with valence electrons of the remaining N  1 atoms. One expects then that each energy level of the isolated atom would split in the

1 One electron volt (eV) is the energy dissipated or acquired by one electron that goes through a potential difference of 1 V. Since the charge of one electron is 1.6  1019 Coulomb, 1 eV ¼ 1.6  1019 J. In this book, eV and cm are frequently used in place of J and m, as a convenient departure from SI units.

2.3 Energy Gap and Intrinsic Carrier Concentration Fig. 2.4 Simplified silicon energy-band diagram illustrating the increase in band width with increasing electron energy

Electron energy increases

29

Conduction band

Eg @ 1.1 eV for Si at 300 K Hole energy increases

EC EV

Valence band

Innermost electrons essentially undisturbed

crystal into N energy levels, each of which can be occupied by two electrons of opposite spins. Since N is a very large number (~1023 cm3), the levels are too close to each other to be distinguished. They are thus described by a band of energy levels, bounded by a maximum and minimum level (Fig. 2.4). The energy levels of innermost electrons remain sharp because the probability for them to interact is very small. The width of a band increases as the electron energy increases. Of primary interest for conduction are the uppermost two bands, the conduction band of free electrons,2 and the band just below the conduction band, referred to as the valence band, i.e., the band of bound electrons. In terms of the band diagram in Fig. 2.4, the energy to break a bond is the energy gap (or forbidden gap) Eg. The energy gap is a function of the lattice constant [2]. One would thus expect Eg to depend somewhat on temperature and pressure. The temperature dependence of Eg is approximated as [7] E g ffi 1:187  3:6  104 T eV

ð2:1Þ

In semiconductors near absolute zero, the valence band is full (all bound electrons in place), and the conduction band is empty, so the crystal behaves like a perfect insulator. As the temperature increases, some electrons acquire sufficient energy from crystal vibrations to overcome the energy gap Eg and are elevated from the valence band to the conduction band where they are free to move. Holes are created in the valance band where electrons are missing. Since most transitions occur between the band edges, only the bottom of the conduction band, EC, and the top

2

Although the electron is free to move, it is still bound to the crystal. Electrons in the conduction band are sometimes described as quasi-free, i.e., behaving as if they were free. For simplicity, the term “free electron” will be used in this book to describe an electron in the conduction band.

30

2 Review of Single-Crystal Silicon Properties

Fig. 2.5 Simplified band diagram. At near 0 K, the valence band is full; the conduction band is empty. As temperature increases, the number of electron transitions from EV to EC increases

Free electron

EC , conduction band edge Eg @ 1.1 eV

EV , valence band edge Hole

of the valence band, EV, will be considered (Fig. 2.5). The silicon band structure is rather complex. Unless otherwise stated, the simplified model in Fig. 2.5 will be used for most discussions. For a fixed and uniform temperature throughout the crystal and without external disturbances, such as applied voltage directly to the crystal, light, or radiation, the crystal is said to be at thermal equilibrium. For each temperature, there is an associated equilibrium concentration of electrons, n
, and holes, p
. For intrinsic silicon n
¼ p
¼ ni cm3

ð2:2Þ

p
n
¼ n2i cm6

ð2:3Þ

where the bars indicate equilibrium values and ni is the intrinsic carrier concentration, an important property of a semiconductor.

2.3.2

The Boltzmann Distribution

From the kinetic theory of gases, it is known that the average energy of a particle is 3kT/2, where k is the Boltzmann’s constant (k ¼ 8.625  105 eV/K ¼ 1.380  1023 J/K) and T is the absolute temperature in K. It is also known that the probability Pi of an atom or molecule being at an energy level Ei relative to the probability Po of being at an energy level Eo is Pi eEi =kT ¼ E =kT ¼ eðEi Eo Þ=kT Po e o

ð2:4Þ

The inverse exponential dependence indicates that, for a given temperature, the probability decreases as the energy difference increases. This means that it is more likely to find atoms or molecules at low energy than at high energy. The expression also indicates the probability increases as the temperature is increased. One classical example is the distribution of molecules acting under the influence of gravity in a column of an idealized atmosphere which is assumed to be at a

2.3 Energy Gap and Intrinsic Carrier Concentration

31

constant temperature. The number of molecules at a height Δh above a reference height h is N hþΔh ¼ N h emgΔh=kT ¼ N h eΔE=kT

ð2:5Þ

In the above relation, Nh + Δh is the number of molecules at a height Δh above h, Nh is the number of molecule at a height h, m is the molecular mass, g is the acceleration due to gravity, and mgΔh is the increase ΔE in potential energy as the molecule rises from h to h + Δh. The exponential on the right of (2.5) is called the Boltzmann factor.

2.3.3

Fermi–Dirac Distribution and Density of States

The Boltzmann distribution function is applicable to atoms and molecules because they can occupy any energy level without restrictions on how many occupy the same energy level. Electrons in a crystal are, however, subject to Pauli’s exclusion principle and hence allowed to occupy only discrete energy levels, called states, separated by forbidden gaps. Thus, statistics applied for the distribution of electrons and holes is different than used for the distribution of atoms or molecules. At thermal equilibrium, the probability that an energy level E is occupied by an electron is given by the Fermi–Dirac distribution function [1–6]: f ðE Þ ¼

1 1þ

eðEEF ÞkT

ð2:6Þ

where f(E) is the probability of occupancy (from 0 to 1) and EF is the Fermi level, a hypothetical reference energy level that depends on temperature, and also on dopant concentration as discussed in the next section. The Fermi level does not imply an allowed energy level. It is determined by the requirement that the probability of occupancy for all energy levels above and below EF satisfies (2.6) and that the crystal as a whole remains neutral. Since an energy level can be either occupied or not occupied by an electron, the probability that a level E is not occupied by an electron is given by 1  f ðE Þ ¼

1 1 þ eðEF EÞkT

ð2:7Þ

At an energy E ¼ EF, the exponential in the denominator goes to 1 and the probability f(E) ¼ 0.5 (or 50%). This means that there is an equal probability that the level E will be occupied or vacant. In a semiconductor, the Fermi level is typically located within the forbidden gap. As EF approaches EC, (EC  EF) decreases and the probability of finding an electron

32

2 Review of Single-Crystal Silicon Properties

at EC increases, while the probability of not finding an electron at EV, i.e., finding a hole at EV, decreases. This is because the magnitude of the exponential in the denominator of (2.6) decreases and the exponential in (2.7) increases. Similarly, as EF approaches EV, (EF  EV) decreases and EC  EF increases. In this case, the probability of non-occupancy at EV increases, i.e., the probability of finding a hole at EV increases, while the probability of finding an electron at EC decreases. For intrinsic silicon, EF is close to halfway between EC and EV, indicating that there is nearly equal probability of finding an electron at EC and a hole at EV. This particular level is referred to as the intrinsic energy level, Ei. For energies larger than about 3kT above EF, (2.6) can be approximated as f ðE Þ ¼ eðEEF Þ=kT

ð2:8Þ

because the “1” in the denominator becomes negligible compared to the exponential. Similarly, for (EF  E) larger than about 3kT, (2.7) simplifies to f ðE Þ ¼ eðEF EÞ=kT

ð2:9Þ

Because of their similarity to (2.5), the distributions (2.8) and (2.9) are referred to as Boltzmann approximations. Since in intrinsic silicon EC  EF ffi EF  EV ffi 0.55 eV ffi 21kT, the Boltzmann approximation is applicable. At a given temperature, the number of electrons in a small energy interval of a band depends on two factors: The probability that an electron will have this energy and on the number of available energy states in that interval. Each band in Fig. 2.4 consists of a large number of states distributed within the band, but since in most cases transitions occur predominantly between band edges, effective density of states NC and NV, at band edges EC and EV is conveniently introduced to estimate the concentrations of conduction electrons and holes. In the temperature range of 200–425 K, the effective density of states for electrons and holes can be approximated as [7]


 T 1:5 cm3 N C ffi 2:80  10 300
 T 1:5 cm3 N V ffi 1:02  1019 300 19

ð2:10Þ ð2:11Þ

Since by definition there should be no states within the forbidden gap, no electrons should be found within the gap even though the probability of occupancy is finite. Real crystals, however, do not follow this rule because of unavoidable “foreign materials” and defects, as will be discussed in Sect. 2.6 and in the following sections. When the Boltzmann approximation applies, the electron concentration is found as the product of (2.8) and (2.10):

2.3 Energy Gap and Intrinsic Carrier Concentration

n
¼ N C eðEC EF Þ=kT ffi 2:80  1019




33

T 300

1:5

eðEC EF Þ=kT cm3

ð2:12Þ

Similarly, the concentration of holes is found from (2.9) and (2.11) as p
¼ N V eðEF EV Þ=kT ffi 1:02  1019




T 300

1:5

eðEF EV Þ=kT cm3

ð2:13Þ

The p
n
product is found from (2.12) and 2.13) as p
n
¼ n2i ¼ N V N C eðEC EV Þ=kT ¼ N V N C eEg =kT cm6

ð2:14Þ

Example 2.1 How close to the mid-gap is EF located in intrinsic silicon at thermal equilibrium? Assume 300 K. Solution Since silicon is intrinsic, n
¼ p
and EF can be found by equating (2.12) and (2.13) as EF ¼ Ei ¼

EC þ E V kT N V E g 0:02586 1:04 ln ln  0:55  0:013 eV þ þ  2 2 2:8 2 NC 2

EF is about 13 meV below mid-gap, not exactly at mid-gap because of the difference between NC and NV.

Example 2.2 Use the values at 300 K in Table 2.1 to calculate ni for silicon (Si), germanium (Ge), and gallium–arsenide (GaAs). Table 2.1 Values for Eg, NC, and NV for Si, Ge, and GaAs at 300 K Eg (eV) NC (cm3) NV (cm3)

Si 1.08 2.80  1019 1.02  1019

Ge 0.66 1.04  1019 6.00  1018

GaAs 1.42 4.70  1017 7.00  1018

Solution Substituting the values in Table 2.1 in (2.14) gives

ni (cm3)

Si 1.4  1010

Ge 2.3  1013

GaAs 1.8  106

34

2 Review of Single-Crystal Silicon Properties

Taking the variation of Eg with temperature in (2.1) into account, the temperature dependence of ni in silicon can be approximated as ni ¼ 2:63  1016 T 1:5 e6885=T cm3

ð2:15Þ

A plot of ni versus temperature is shown in Fig. 2.6. Fig. 2.6 Temperature dependence of ni

ni (cm-3)

1016 1015

1014 1013 1012 1011 1010 1009 1008 1007 1006 -50

ni ≅ 1.4 × 1010 cm-3 at 300 K

0

50

100

150

200

250

300

Temperature (oC)

2.4

Doping

By adding small and controlled amounts of certain elements to the otherwise pure silicon, the crystal can be doped to have more free electrons than holes and vice versa. To be active, the dopants must occupy substitutional sites, i.e., occupy a lattice site normally occupied by silicon. Doping is performed by implantation and diffusion and discussed in more detail in [8]. Of particular importance to silicon devices is doping with elements from the third and fifth columns of the periodic table (Fig. 2.7).

2.4.1

Dopants from the Fifth Column: Donors

Phosphorus, arsenic, antimony, and bismuth are elements of the fifth column (Group V). These elements have five electrons in their outer shell, i.e., five valence electrons. When they occupy a substitutional site in silicon, only four of the valence electrons are needed to complete the covalent bonding in the crystal. The fifth electron does not contribute to the bonding (Fig. 2.8a). The energy required to set the fifth electron free is very small so that, under normal operating temperatures and for concentrations less than about 1018 cm3, nearly all dopants release (or donate) their fifth electron to the crystal. After donating an electron, the donor cannot lose

2.4 Doping

35

III 5

Acceptors

IV

10.811

6

V 7 14.007

12.011

B Boron

C Carbon

N Nitrogen

13 26.982

14 28.086

15 30.974

Al Aluminum

Si Silicon

P Phosphorus

31 69.723

32 72.610

33 74.922

Ga Gallium

Ge Germanium

As Arsenic

49 114.820

50 118.710

51 121.757

In Indium

Sn Tin

Sb Antimony

81 204.383

82 207.200

83 208.980

Ti Titanium

Pb Lead

Bi Bismuth

Donors

Fig. 2.7 Important semiconductor elements

another one. Each donor left behind becomes a fixed positive ion with four bound valence electrons, the same as the original silicon atom. Note that by ionizing the donor, a conduction electron is generated without creating a hole. Thus, if one assumes that all donor atoms are ionized, N þ D ffi N D . The crystal becomes rich in electrons, N-type, but remains neutral as a whole. Neutrality requires that 3 n
¼ p
þ N þ D cm

ð2:16Þ

At temperatures below approximately 100 K, the probability for electrons to break loose from donors begins to decrease, and an increasing fraction of electrons remains “frozen” to donors. High-dopant concentration effects are discussed in Chap. 5.

2.4.2

Dopants from the Third Column: Acceptors

Boron, aluminum, gallium, and indium are elements from the third column (Group III) in the periodic table. When substituted for silicon, the three available valence electrons in the outer shell take part in the bond structure, so that one electron is

36

2 Review of Single-Crystal Silicon Properties

Hole

(a)

+

Donor ion

+

-

Acceptor ion

(b)

Free electron

a

a

Fig. 2.8 Simplified model for dopants in silicon. (a) Free electron liberated from donor. (b) Nearby bound electron transferred to acceptor to complete bond, hole created

missing from the fourth bond. This vacant state is “attractive” to an adjacent bound electron that easily moves to fill it. Boron, aluminum, gallium, and indium “accept” the fourth electron, creating a hole where the filling electron came from without producing a free electron (Fig. 2.8b). After accepting one electron, an acceptor becomes a negatively ionized and cannot receive another one. When silicon is doped with acceptors, the crystal becomes rich in holes or P-type. As with donors, the ionization energy of typical acceptors such as boron and indium is very small, so one can assume that, at normal operating temperatures and for concentrations below about 1018 cm3, all acceptor atoms are ionized, so N  A ffi NA. Acceptors are fixed, negatively charged ions. Neutrality requires that 3 p
¼ n
þ N  A cm

ð2:17Þ

The thermal equilibrium p
n
product in (2.3) is extremely useful in device analysis. While derived for intrinsic silicon, it also applies to doped silicon since it depends only on temperature and energy gap. The principle of mass action shows that when the concentration of one type of carriers increases, the concentration of other type must decrease so that the product remains constant. Thus, for N-type silicon, electrons are majority carriers, and holes minority carriers with p
¼

n2i n2  i cm3 n
N D

ð2:18Þ

Similarly, for P-type silicon, holes are majority carriers and electron minority carriers of density

2.4 Doping

37

n
¼

n2i n2  i cm3 p
N A

ð2:19Þ

Example 2.3 A silicon crystal is doped with 5  1017 phosphorus atoms/cm3. Assume 25  C and disregard point defects such as Si vacancies. (a) Calculate the thermal equilibrium electron and hole concentrations. (b) Estimate the number of broken bonds per cm3. (c) What is the distance between phosphorus atoms in units of silicon lattice constant? Solution (a) At 25  C, it can be assumed that all phosphorus atoms are ionized and n
ffi N D ¼ 5  1017 cm3 . From Fig. 2.5, n2i ffi 2  1020 cm6 . From (2.9), p
¼ n2i =N D ffi 2  1020 =5  1017 ¼ 400 cm3 . (b) Since donors are ionized without breaking bonds, the number of broken bonds per cm3 is the same as the concentration of holes. (c) Since the P concentration is 5  1017, each P atom occupies a volume of 1 cm3/5  1017, i.e., it fits in a box having dimensions of ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi p 3 1= 5  1017 cm ffi 1:26  106 cm. In terms of lattice constant, this is 1.26  106/5.43  108 ffi 23 lattice constants.

2.4.3

Band Model for Impurities in Silicon

In terms of the band diagram, energy levels of donors such as arsenic (As), phosphorus (P), antimony (Sb), or bismuth (Bi) are represented by short bars just below the conduction band indicating discrete energy states ED (Fig. 2.9). The numbers below the bars are the energies in meV (103 eV), measured from the donor level to the conduction band edge. The energy difference is so small that the probability for an electron to be raised from the donor level to the conduction band edge is very high. When electrons previously bound to silicon atoms are captured by acceptor atoms to complete their fourth covalent bonds with silicon neighbors, they are only a little less tightly held from being free than in silicon bonds. Acceptor levels are thus represented by short bars, indicating discrete energy states EA just above the valence band (Fig. 2.9). The numbers above the bars are ionization energies (in meV) measured from the valence band edge. The probability for an acceptor energy level to be occupied by an electron coming from the valence band is almost 100%.

38

2 Review of Single-Crystal Silicon Properties

Fig. 2.9 Measured ionization energies in meV of donors and acceptors in silicon (Adapted from [9]). Diagram is not to scale

Sb

ED

P

As

Bi

EC 39

45

54

69

Eg ~ 1.1 eV EA

45

B

160

67

72

In

Al

Ga

EC E D

ED EA

EV (a)

EV

EC

EA

EV (b)

Fig. 2.10 Schematic representation of partially compensated impurities. (a) ND > NA, n  ND  NA. (b) NA > ND, p ¼ NA  ND

Thus, practically all acceptors are negatively ionized, each creating a hole in the valence band. In most components, both donors and acceptors are present in the same region of the crystal. In this case, both donors and acceptors will be ionized, but only the net, i.e., the difference between their concentrations, will be available for conduction (Fig. 2.10). The crystal is said to be compensated. In case donors and acceptors are exactly equal in concentration, all donors would be positively ionized without contributing free electrons, and all acceptors negatively ionized without contributing holes for conduction. In this case, n
¼ p
, i.e., the crystal is intrinsic but not pure. The neutrality condition for a compensated semiconductor is 3
þ N ð2:20Þ p
þ N þ D ¼ n A cm For N-type silicon, EF is above Ei and moves toward EC as the net donor concentration is increased. This reflects an increase in electron concentration above the hole concentration (Fig. 2.11a). Similarly, for P-type silicon, EF is below Ei and moves toward EV as the net acceptor concentration is increased, indicating an increase in the hole concentration above the free electron concentration (Fig. 2.11b). The difference (EF  Ei) in Fig. 2.11 is divided by e (charge q) to convert the values from energy (eV) to V. ϕb ¼ (EF  Ei)/q is referred to as the “bulk” Fermi potential. For N-type silicon, EF lies above the intrinsic level Ei and ϕb is positive. For P-type silicon, EF lies below Ei and ϕb is negative. For intrinsic silicon ϕb ¼ 0 (Fig. 2.11c). The Fermi potential is an important parameter used in device analysis.

2.4 Doping

39

fb > 0

EC EF

EC

Ei

Ei

fb < 0

EV (a) N-type

(b) P-type

EF EV

EC f b =0

EF=Ei EV

(c) Intrinsic

Fig. 2.11 Fermi level and definition of Fermi potential for (a) N-type, (b) P-type, and (c) intrinsic semiconductor

For intrinsic silicon EF ¼ Ei and the Boltzmann approximation can be applied. The expression for the intrinsic carrier concentration simplifies to ni ¼ N C eðEC Ei Þ=kT cm3

ð2:21Þ

ni ¼ N V eðEi EV Þ=kT cm3

ð2:22Þ

or

For N-type silicon, the Fermi level above Ei can be determined by taking the ratio of (2.12) and (2.21) as n
EF  Ei kT ¼ ϕb ¼ ln eV ni q q

ð2:23Þ

Similarly, for P-type silicon, Eqs. (2.13) and (2.22) give Ei  EF kT p
¼ ϕb ¼  ln eV q q ni

ð2:24Þ

For fully ionized dopants, the Fermi potential can also be expressed for N-type silicon as ϕb ffi

kT N D V ln ni q

ð2:25aÞ

and for P-type silicon as ϕb ffi 

kT NA ln V ni q

ð2:25bÞ

40

2 Review of Single-Crystal Silicon Properties

Example 2.4 A silicon crystal is doped with phosphorus at a uniform concentration of 2  1017 cm3. Assume full ionization of donors. 1. Find the Fermi potential and carrier concentrations at 50, 27, and 150  C. 2. Repeat for a uniform boron concentration of 5  1016 cm3, and find the difference in Fermi potentials, ϕbn  ϕbp, between the phosphorus- and boron-doped regions. Solution First, the intrinsic carrier concentration is found from (2.15). For a temperature of, e.g., 50  C (223 K) ni  2:63  1016 T 1:5 e6885=T  2:63  1016  2231:5  e6885=223  3:42  106 cm3 The Fermi potential for ND ¼ 2  1017 cm3 is found from (2.25a) as ϕB ffi

kT N D 2  1017 ¼ 8:62  105  223  ln ffi 0:477 V ln ni q 3:42  106

The same procedure is repeated for the other temperatures and for borondoped (P-type) silicon. Table 2.2 summarizes the results. Table 2.2 Fermi potentials for N-type and P-type silicon N-type T ( C) 50 25 150 P-type T ( C) 50 25 150

T (K) 223 300 423

ni (cm3) 3.42  106 1.47  1010 1.95  1013

ϕb (V) 0.477 0.425 0.337

n
(cm3) 2  1017 2  1017 2  1017

p
(cm3) ~0 1.09  103 1.91  109

T (K) 223 300 423

ϕb (V) 0.450 0.389 0.286

n
(cm3) ~0 4.35  103 7.63  109

p
(cm3) 5  1016 5  1016 5  1016

ϕbn  ϕbp (V) 0.927 0.814 0.623

2.5 Carrier Transport

2.5

41

Carrier Transport

Electric current is defined as the flow of charge, i.e., the number of charged carriers transported per unit time across a given surface in a direction normal to it. The transport of carriers can occur in two ways: (a) By drift, under the influence of an electric field. The field forces the otherwise randomly moving holes to drift in the direction of the field and electrons to drift opposite to the electric field. (b) By diffusion, under the influence of a gradient in carrier concentration. In this case, carriers diffuse from regions of high concentration to regions of low concentration and tend to equalize concentrations within the region of diffusion. Both drift and diffusion are involved in different degrees in the transport of carriers. In both cases, the electric current density depends on the concentration of charged carriers free to move and their velocities in the direction of current. For electrons, jn ¼ qnhvi A=cm2

ð2:26Þ

where jn is the electron current density, n is the electron concentration, q is the electron charge (q ¼ 1.6  1019 C), and hvi is the average velocity in direction of current (cm/s). Example 2.5 The electron density in a metal is approximately 1023 cm3. Assume a current density 0.5 mA/μm2. At what velocity do the electrons travel through the metal? How does this compare with the velocity of electrons in silicon doped with ND ¼ 1018 cm3, at the same current density? Solution The current density per cm2 is 0.5  103  108 ¼ 5  104 A/cm2. The average velocity of electrons in the metal is found from (2.26) as h vi ¼

5  104 ¼ 3:13 cm=s 1:6  1019  1023

For silicon doped with ND ¼ 1018 cm3, the velocity is found as h vi ¼

5  104 ¼ 3:13  105 cm=s 1:6  1019  1018

42

2.5.1

2 Review of Single-Crystal Silicon Properties

Carrier Transport by Drift: Low Field

At a given temperature and in the absence of any disturbance, electrons and holes are in random motion in the crystal. The free carriers travel at high speed in all directions making random collisions with lattice atoms. They share their thermal motion with the crystal. The carriers, as a group, do not carry a net current in any direction because, on the average, as many move in one direction as in the other. This is illustrated in two dimensions in Fig. 2.12a. Each carrier acquires an average thermal energy of 3kT/2 that is assumed to be lost after collisions for simplicity. At thermal equilibrium, the free carrier average kinetic energy equals its average thermal energy 3kT/2 so that the average thermal velocity, vth, can be found from the relation 1  2 3 m vth ¼ kT eV 2 2

ð2:27Þ

where m* is the effective mass, which is almost the same as the free electron mass, and hvthi is the average carrier thermal velocity (vth ffi 107 cm/s at 300 K). The lattice atoms vibrate about their mean positions but remain, on the average, in their lattice positions. The vibrations cause collisions with carriers, referred to as scattering events, randomly deflecting their motion. When a voltage is directly applied to the crystal, a field is created causing a current and thus a departure from thermal equilibrium. The conventional direction of electric field is from positive to negative charge. Holes travel in the direction of electric field and electrons in a direction opposite to the field (Fig. 2.12b). For a small electric field, less than about 5  103 V/cm, the disturbance is very small so that the thermal equilibrium carrier distribution can still be assumed. Since electrons are negatively charged and move in opposite direction to holes, both currents have the same sign and the total current is the sum of electron and hole current. An exaggerated two-dimensional representation of the influence of the small electric field on the carrier velocity is shown in Fig. 2.13, illustrating the superposition of a drift velocity component upon the thermal velocity. The force exerted by the field on an electron is F ¼ qE. For a given field, this force is constant. From mechanics, it is known that when a constant force is applied Field, E

Electrons

Holes

(a)

(b)

Fig. 2.12 (a) Schematic representation of random carrier motion at thermal velocity in absence of field; net current is zero. (b) Applied field E: organized electron drift in direction opposite to E

2.5 Carrier Transport Fig. 2.13 Exaggerated two-dimensional representation of the influence of an electric field on the average electron velocity

43

E vy Thermal equilibrium

Field present

Δv vx Drift velocity

to a particle, the particle is uniformly accelerated. Consequently, the drift velocity and hence the current would be expected to increase indefinitely under the influence of a constant electric field. This is in disagreement with the observed Ohm’s law which specifies that, for a given field, the current “settles” at a steady-state value. Therefore, there must be “frictional” forces in a direction opposite to the accelerating force. A balance between the two forces must be reached rapidly so that the drift velocity settles at a constant average value. The motion of carriers in the crystal under the influence of a constant field can be compared with the fall of a steel ball in a viscous medium, such as heavy oil. While the constant force of gravity accelerates the steel ball, the frictional force that the viscous medium exerts on it slows it down. The friction increases as the velocity of the steel ball increases. Eventually, a point is reached where the force of gravity and the frictional forces cancel each other. At this point, there will be no net force exerted on the ball that now falls at a constant limiting velocity. The frictional forces produce a small rise in the temperature of the medium. The electron drift velocity drift velocity can be expressed as vdn ¼ μn E cm=s

ð2:28Þ

where μn is called the electron drift mobility in cm2/Vs and, for simplicity, the average velocity is expressed as vdn instead of hvdni. Similarly, the drift velocity of holes is vdp ¼ μp E cm=s

ð2:29Þ

where μp is the hole drift mobility in cm2/Vs. The electron and hole mobility are important parameters that play a key role in device analysis. It is a measure of the ease with which the carriers move in the crystal and affects the performance of most devices.

44

2 Review of Single-Crystal Silicon Properties

Since electrons and holes move in opposite directions and their charges are of opposite polarity, both terms have the same sign, so that their sum constitutes the total current density:     jn þ jp ¼ q vdn n þ vdp p ¼ qE μn n þ μp p A=cm2

ð2:30Þ

The conductivity of the crystal is3   σ ¼ σ n þ σ p ¼ q μn n þ μp p S=cm

ð2:31Þ

The resistivity is the inverse of conductivity and defined as ρ¼

1 1  Ω-cm ¼  σ q μn n þ μp p

ð2:32aÞ

If only donors at a concentration ND are present, then ρ can be approximated as ρffi

1 Ω-cm qμn N D

ð2:32bÞ

ρffi

1 Ω-cm qμp N A

ð2:32cÞ

Similarly, for only NA

When both donors and acceptors are present at different concentrations, one type is totally compensated by the other. The net carrier concentration is approximated as the difference in concentration between the two impurities. As will be shown, the mobility would be affected by both impurities. The resistance, R, of a conductor or semiconductor of length L, width W, and thickness t is R¼ρ

L L ¼ρ Ω W t A

ð2:33Þ

where A is the cross-sectional area. The sheet resistance, RS, of a conductive layer is the resistance measured between two opposite sides of a square of the layer. Since in this case L ¼ W, RS ¼ ρ

3

The unit Siemens (S) is used for 1/Ω.

L ρ ¼ Ω=□ W t t

ð2:34Þ

2.5 Carrier Transport

45

(a) Scattering Mechanisms The most important scattering mechanisms are lattice scattering and ionized impurity scattering. Other mechanisms, such as scattering by neutral atoms at low temperature, crystal-defect scattering, and carrier–carrier scattering, are less important and will be discussed only where applicable. The carrier mobility is limited by the rate of scattering events along its path. The scattering events are referred to as collisions. Between collisions, carriers gain energy from the electric field and transfer this energy to the atoms of the crystal upon collision. The energy transfer increases oscillations of crystal atoms and causes Joule heating. To simplify the analysis, it is assumed that upon collision, a carrier loses all the energy it gained from the external field and starts over again with a random velocity after a collision. In other words, after collision, the carrier has no memory of what happened before the collision. Lattice Scattering In the presence of thermal vibrations, lattice atoms are compressed or pulled apart over small regions. Such displacements cause a disturbance to the periodic potential, deflecting carriers and decreasing their mobility. This scattering mechanism is referred to as lattice scattering. The probability of collisions with the lattice increases with temperature because the number of vibrational modes and the amplitude of oscillations increase with temperature. As the oscillation amplitude increases, the cross-sectional area for collisions increases. Careful measurements show the following dependence for electron and hole mobility on temperature [10]: μℓn ffi 2:10  109 T 2:5 cm2 =Vs

ð2:35Þ

μℓp ffi 2:34  109 T 2:7 cm2 =Vs

ð2:36Þ

where μln and μlp are the lattice-limited electron and hole mobilities, respectively. Ionized Impurity (Coulomb) Scattering A carrier moving in the vicinity of an ionized impurity is deflected by the Coulomb field of the ion. In their path near the ion, electrons are attracted by donors and repelled by acceptor, while holes are attracted by acceptors and repelled by donors (Fig. 2.14). When the crystal is doped with both donors and acceptors, both contribute to the net impurity scattering. A relation for the ionized impurity scattering-limited

Fig. 2.14 Electron and hole collisions with dopant atoms causing Coulomb scattering

Electron

+

Donor

Hole

Hole

-

Acceptor

Electron

46

2 Review of Single-Crystal Silicon Properties

mobility as a function of temperature and ionized impurity concentration, NI, is adapted from [11] and simplified to μI ¼

AT 3=2
 cm2 =Vs 2 N I ln 1 þ B T2=3 

ð2:37Þ

NI

where A ffi 1.5  1016 for electrons, A ffi 7.3  1015 for holes, and B ffi 2.81  106 for electrons and holes [12]. The dependence of ionized impurity mobility on temperature can be intuitively understood by considering that elevating the temperature increases the carrier thermal velocity. This reduces the time the carrier spends in the vicinity of the ionized impurity and hence the deflection when it passes the ion, increasing the mobility. Matthiessen’s Rule In a simple model, the probabilities for scattering are additive, so that the lattice- and impurity-limited mobilities can be combined to give an effective mobility as 1 1 1 ¼ þ μeff μℓ μI

ð2:38Þ

The combination of different mobilities in the form of (2.38) is referred to as Matthiessen’s rule. The calculated electron and hole mobility is plotted in Fig. 2.15 as a function of dopant concentration N at 25  C. It should be noted, however, that there is appreciable spread in mobility data in the literature, particularly at higher concentrations [13–18].

104

Mobility (cm2/Vs)

: [1.34]

: [1.35]

: [1.36]

: [1.37]

Electrons 103

25 oC

Holes

102

101 14 10

: [1.38]

1015

1016 1017 1018 Dopant concentration (cm-3)

1019

Fig. 2.15 Electron and hole mobility as a function of doping concentration at 25  C

1020

2.5 Carrier Transport

47

Figure 2.15 compares the room temperature mobility as function of the concentration N using the following empirical expression derived from experimental data by [13] and modified slightly by [14–18]: μ0 ¼

μmax  μmin þ μmin cm2 =Vs 1 þ ðN=N ref Þα

ð2:39Þ

The parameter values for μmax, μmin, Nref, and α are shown in Table 2.3. N is the total doping concentration. The temperature dependence of mobility is shown in Fig. 2.16 for N ¼ 1015, 1016, 17 10 , and 1018 cm3

Table 2.3 Values for parameters in (2.39)

1330.1

88.3

Fig. 2.16 Temperature dependence of electron and hole mobilities. (a) N = 1014 cm3 and 1016 cm3. (b) N = 1017 cm3 and 1018 cm3 [18]

α 0.72 0.91

NRef 8.5  1016 1.3  1017

1.295  1017

(a) Mobility (cm2/Vs)

Electrons μmax μmin 1330 65 1360 92

0.891

μmax 495

Holes μmin NRef 47.7 6.3  1016

495 468 461.2

47.7 49.7 54.3

1.9  1017 1.6  1017 2.35  1017

α 0.76 0.76 0.70 0.88

2300 2100 N=1014 cm-3 1900 1700 N=1016 cm-3 1500 1300 1100 mn N=1014 cm-3 900 16 -3 N=10 cm 700 mp 500 300 100 -40 -20 0 20 40 60 80 100 120 140 160

Temperature (∞C)

(b)

800 700

Mobility (cm2/Vs)

Reference [13] [14] [15] [16] [17]

600

mn mp

N=1017 cm-3

500 400 300 200

mn mp

N=1018 cm-3

100 0 -40

-20

0

20

40

60

80

100 120 140 160

Temperature (∞C)

48

2 Review of Single-Crystal Silicon Properties

100 25 oC

Resistivity (Ohm-cm)

10 p

n

1 10-1 10-2 10-3 10-4 1014

1015

1016

1017

1018

1019

1020

NA or ND (cm-3) Fig. 2.17 Resistivity versus impurity concentration at 25  C. Solid lines measured resistivity [19, 20]; dashed lines calculated

Substituting the effective mobility in (2.32b) and (2.32c) provides a good approximation of resistivity as a function of impurity concentration and temperature. Figure 2.17 compares the resistivity obtained from calculations (dashed lines) with measured results from [19, 20] (solid lines).

2.5.2

Carrier Transport by Drift: High Field

The drift velocity of electrons and holes in silicon is shown as a function of electric field in Fig. 2.18. The plots are constructed from an empirical relation that constitutes a best fit to measured data at 27  C [13]: vd  vsat h

E=Esat 1 þ ðE=Esat Þ

β

iβ1 cm=s

ð2:40aÞ

The fitting parameters are summarized in Table 2.4 for high-resistivity silicon [13]. The mobility field dependence is approximated as μ0 2 μh i1 cm =Vs β β 1 þ ðE=Esat Þ

ð2:40bÞ

where μ0 is the low-field mobility given by (2.39). Treating vsat as constant, Esat ¼ vsat/μ0, dependent on doping [13].

2.5 Carrier Transport

49

Table 2.4 Values for fitting parameters in (2.40a, and 2.40b)

Electrons Holes

Esat (V/cm) 8  103 1.95  104

vsat (cm/s) 1.1  107 9.5  106

β 2 1

At a field less than about 5  103 V/cm, the drift velocity is proportional to electric field. The proportionality factor is the mobility, as defined in (2.28) and (2.29). In the range between 5  103 and 5  104 V/cm, the mobility decreases so that the dependence of drift velocity on electric field digresses from linearity. As the field increases above ~5  104 V/cm, the drift velocity begins to saturate to a value vsat close to the thermal velocity of 107 cm/s (Fig. 2.18). The departure from linearity and the saturation of velocity can be qualitatively explained in terms of different vibration mechanisms in the crystal. Oscillation of atoms in the crystal can be visualized by comparing the crystal lattice with a threedimensional periodic set of mass points, spaced a distance a apart and each attached to six adjacent identical springs [4, 6]. In such as system, a multitude of standing waves of different wavelengths can be generated at a frequency that depends on the force constant of the springs, with nodes appearing at the system boundaries. In a crystal, there are two modes of oscillation of different frequencies associated with each wavelength, one in which two atoms in a unit cell oscillate in phase (Fig. 2.19a) and the other where they move out of phase (Fig. 2.19b). As in the case of electrons and photons, an oscillation in a crystal has a frequency v and an associated quantum of energy E ¼ hv called a phonon (h is Planck’s constant). When atoms oscillate approximately in phase, as illustrated in Fig. 2.19a, the relative displacement between atoms is small, and the restoring force is small. 108

Carrier velocity (cm/s)

25 oC

vn=μnE vp=μpE

107

Electrons Holes

106

105

104 102

103

104

Electric field (V/cm) Fig. 2.18 Carrier drift velocity versus electric field [13]

105

50

2 Review of Single-Crystal Silicon Properties

(a)

(b)

Fig. 2.19 Schematic representation of oscillation modes in a crystal. (a) Atoms in phase, acoustical phonons. (b) Atoms out of phase, optical phonons

Therefore, the frequency associated with such oscillations is small and the phonon energy is small. The wave propagation corresponds to ordinary sound waves in the crystal, so the quanta of energy are referred to as acoustical phonons. When the atoms move in approximately opposite directions, as shown in Fig. 2.19b, they are characterized by higher frequencies, hence higher energies than in (a), because of the large restoring force associated with the opposite motion of atoms. This mode of oscillation is called optical and the associated quanta of energy called optical phonons because, if the atoms were oppositely charged, such as in NaCl crystals, the vibrations would give rise to oscillating electric dipole moments and electromagnetic radiation is emitted or absorbed during the process [4, 6]. When the field is smaller than about 5  103 V/cm, the carriers interact predominantly with acoustical phonons because their kinetic energy is not sufficiently high to generate optical phonons. When the field is varied in this range, the carriers rapidly exchange energy with acoustical phonons and reach a new steady-state average velocity that is proportional to the field, i.e., dvd/dE ¼ constant ¼ μ0, where μ0 is the low-field mobility defined in (2.28) and (2.29). In this region, the carrier temperature does not increase appreciably over the crystal temperature. As the field increases above approximately 5  103 V/cm, the carrier energy increases to a point where the probability for generation of optical phonons becomes significant. An increasing fraction of energy gained from the electric field is now lost by generation of optical phonons, and the rate of change in drift velocity decreases, i.e., dvd/dE decreases. Therefore, as the field increases above a certain level, the mobility begins to decrease below its low-field value (μ < μ0). In the limit, the carriers lose all incremental energy gained from the field to the crystal, and their velocity does not further increase, i.e., the velocity reaches a nearly constant saturation velocity vsat. In this range, the energy imparted by the electric field is transferred to the crystal and increases the number of carriers at velocity saturation instead of increasing the carrier drift velocity. In the range above approximately 5  104 V/cm, the carrier temperature increases above the lattice temperature, and carriers are said to be hot carriers. Important hot-carrier effects are discussed in the following sections.

2.5.3

Carrier Transport by Diffusion

Free particles in any system are in constant random thermal motion. For a uniform free carrier concentration and without external disturbance, as many carriers move,

2.5 Carrier Transport

51

on the average, in one direction as in the other and the net number of carriers passing through a unit area per unit time, the carrier flux, in any direction, is zero. In the presence of a concentration gradient, however, the probability for a carrier to move in one direction can be the same everywhere, but there are more carriers in a region of high concentration than outside that region. Hence, there will be a net flux of carriers moving outward from that region. The flow of carriers in response to a concentration gradient is referred to as diffusion. It is the same process that spreads smoke in air. In a semiconductor, electrons and holes are carriers of charge, and their transport by diffusion gives rise to diffusion currents. A thorough analysis shows that the electron diffusion current density in one dimension is jnðdif Þ ¼ qDn

dnðxÞ A=cm2 dx

ð2:41Þ

where q is the charge of an electron (1.6  1019 C), Dn is the electron diffusivity (cm2/s), and dn(x)/dx is the gradient in electron concentration. For electrons flowing in the positive x-direction, dn(x)/dx is negative because it points in the direction of decreasing concentration. Since the electron charge q is negative, jn is positive. Similarly, for holes moving in the x-direction, the hole current density in one dimension is jpðdif Þ ¼ qDp

dpðxÞ A=cm2 dx

ð2:42Þ

where Dp is the diffusivity of holes and dp(x)/dx is the gradient in hole concentration. In this case, the electron and hole currents are in opposite directions because of their opposite charge. The total diffusion current density in the x-direction is then
 dn dp ð2:43Þ A=cm2 jðdif Þ ¼ jnðdif Þ þ jpðdif Þ ¼ q Dn  Dp dx dx The average carrier velocity in the x-direction can be obtained from (2.26), (2.41), and (2.42) as dn 1 cm=s dx n dp 1 cm=s ¼ Dp dx p

vnðdif Þ ¼ Dn vpðdif Þ

2.5.4

ð2:44Þ ð2:45Þ

Total Drift and Diffusion Current Density

Both drift and diffusion contribute in varying degrees to the total current density. The two mechanisms are typically independent events and can be combined to give the total current density. In one dimension, this is for electrons

52

2 Review of Single-Crystal Silicon Properties

jn ¼ jnðdriftÞ þ jnðdif Þ ¼ qμn nE þ qDn

dn A=cm2 dx

ð2:46Þ

jp ¼ jpðdriftÞ þ jpðdif Þ ¼ qμp pE  qDp

dp A=cm2 dx

ð2:47Þ

and for holes

The drift terms in the above equations have the same algebraic sign because the electric field produces conventional current in the same direction for opposite charged particles.

2.5.5

Nonuniform Doping Concentration

So far, only uniformly doped silicon was considered. In most device regions, however, the dopant concentrations are nonuniform. In this case, the bulk Fermi potential ϕb in (2.25a, and 2.25b) becomes a function of position in the doped region, as illustrated in Fig. 2.20 in one dimension for N-type silicon at thermal equilibrium. Since the crystal is at thermal equilibrium, the net current in any direction is zero. When there is no current in any region, the Fermi level is shown flat. For not too high concentrations, the energy gap remains constant but the bands are bent. The electrostatic potential with respect to the arbitrary reference energy level Eref parallel to EF is V ðxÞ ¼ 

EC ðxÞ  Eref V q

ð2:48Þ

Because of the dopant nonuniformity, a built-in field E exists, given by4

Fig. 2.20 Simplified band diagram for nonuniformly doped N-type silicon at thermal equilibrium. The concentration drops from right to left. Eref. is a convenient, arbitrary reference energy level

EC fb

EF

Ei

EV Eref

4

Bold E is used for electric field to distinguish it from energy E.

2.5 Carrier Transport

53

E¼

dϕb 1 dE C 1 dEV 1 dEi ¼ ¼ ¼ V=cm dx q dx q dx q dx

ð2:49Þ

This built-in field induces a drift current component that at thermal equilibrium is exactly balanced by a diffusion current component in the opposite direction. The balance can be visualized by considering that the concentration gradient in Fig. 2.20 causes electrons to diffuse from right to left, but as they diffuse, electrons leave uncompensated positively charged donor ions behind creating a positive field that forces electrons to drift back from left to right. At equilibrium, the drift current is exactly balanced by the diffusion current and the net current is zero. In this case, (2.46) and (2.47) reduce to d
n dx d
p qμp p
E ¼ qDp dx

qμn n
E ¼ qDn

ð2:50Þ ð2:51Þ

where n
and p
are the position-dependent equilibrium electron and hole concentrations.

2.5.6

Einstein Relation

In the above equations, the carrier mobility and diffusivity, D, are both controlled by scattering mechanisms in the crystal. They are connected by an equation known as the Einstein relation: Dn ¼ μn

kT cm2 =s q

ð2:52Þ

Dp ¼ μp

kT cm2 =s q

ð2:53Þ

Substituting the above expressions for the electron and hole diffusivity, Dn and Dp in (2.50) and (2.51) give important relations between the built-in field and the gradient in dopant concentration: E¼ E¼

1kT d
n 1 kT dN D V=cm ¼ n
q dx N D q dx

ð2:54Þ

1kT d
p 1 kT dN A V=cm ¼ p
q dx N A q dx

ð2:55Þ

54

2.6

2 Review of Single-Crystal Silicon Properties

Non-Equilibrium Conditions

When the crystal is at thermal equilibrium, the rate of thermally generated electron– hole pairs in a volume element is balanced by a statistically equal rate of electron– hole pair recombination. In this case, p
n
¼ n2i cm6 A non-equilibrium condition occurs when excess carriers are generated by an external stimulus, such as light, whereby pn > n2i

ð2:56Þ

When the stimulus is removed, the system tends to restore equilibrium by an excess recombination over generation. In situations where the electron and hole concentrations are reduced below their equilibrium values, pn < n2i

ð2:57Þ

In this case, there will be an excess in thermal generation over recombination. Such situations are found in, e.g., reverse-biased PN junctions, as discussed in Chap. 3. This section discusses the mechanisms involved in recombination processes in the silicon bulk.

2.6.1

Carrier Lifetime and Diffusion Length

Excess carriers can be created, for example, by illuminating the crystal with photons of energy  Eg or by forward biasing a PN junction as described in the next chapter. In the case of illumination, if the intensity of light is kept constant, a non-equilibrium steady-state condition is achieved where the electron and hole concentrations are larger than their thermal equilibrium values and a new rate of generation is balanced by a new rate of recombination. Let Δp and Δn be the excess carrier concentrations. The steady-state concentrations are given as follows: p ¼ p
þ Δp

ð2:58Þ

n ¼ n
þ Δn

ð2:59Þ

Because electrons and holes are generated or annihilated in pairs, Δp ¼ Δn and the crystal as a whole remain neutral. An increase in the minority carriers above thermal equilibrium concentration is called minority carrier injection. Consider, for example, a P-type silicon sample with NA ¼ 1016 cm3. At room temperature, where

2.6 Non-Equilibrium Conditions

55

nearly complete ionization occurs, the thermal equilibrium majority hole concentration is about 1016 cm3, and the minority electron concentration is about 2  104 cm3. If the sample is illuminated with light of intensity that caused an increase in the carrier concentrations by, e.g., Δn ¼ Δp ¼ 1012 cm3, the fractional increase in majority hole concentration is negligibly small, Δp=
p ¼ 0:01%, while the minority electron concentration increases by over seven orders of magnitude. When the increase in carrier concentration is small compared to the majority thermal equilibrium concentration, the injection is referred to as low-level injection. The time-dependence of the recombination process is characterized by a carrier lifetime, which is the time for the excess concentration to decay by 1/e of its starting value. If by some means excess majority carriers could be created in silicon without a simultaneous increase in minority carriers and the stimulus instantaneously removed, the excess majority carriers would dissipate in a very short time, typically 1012–1011 s (see Problem 9). In comparison, excess minority carriers have a much longer lifetime, even as long as seconds. Because of the required neutrality, however, excess majority carriers will remain present as long as excess minority carriers are present. It is the minority-carrier lifetime that plays a key role in device applications. At low-level injection, the rate of recombination of excess minority carriers is typically proportional to their concentration: dΔnðt Þ ¼ CΔnðt Þ cm3 dt

ð2:60Þ

where C is a constant. The decay of excess carriers can then be expressed as Δnðt Þ ¼ Δn0 et=τ cm3

ð2:61Þ

In Eq. (2.61), Δn0 is the excess minority concentration at the time t ¼ t0, e.g., when the stimulus was stopped, and τ the average minority-carrier lifetime, i.e., the time when the excess minority-carrier concentration has decayed to 1/e of its value at time t ¼ 0. The minority-carrier lifetime is determined by the rate at which excess electrons and holes recombine or annihilate. Recombination processes are discussed next. (a) Direct Band-to-Band Transitions Band-to-band recombination is a direct transition of an electron from the bottom of the conduction band to the top of the valence band whereby an electron–hole pair is annihilated. The rate of this recombination process is expected to be proportional to the electron and hole concentrations. When such a transition occurs, a photon of energy equal to the bandgap is emitted. The probability for such transitions is high in direct bandgap semiconductors, such as GaAs, where electrons at EC and holes at EV have the same momentum. The actual band diagram of silicon is more complex than in Fig. 2.5. It shows that silicon is an indirect bandgap semiconductor where free electrons at EC have higher momentum than holes at EV. Because energy and momentum must be conserved during transitions between EC and EV, and the electron cannot lose its momentum at once, the transitions become unlikely without

56

2 Review of Single-Crystal Silicon Properties

assistance of other mechanisms that absorb the excess momentum. The energy is transferred in steps to the crystal instead. (b) Transitions Involving Intermediate States The minority-carrier lifetime in silicon crystals is found to be considerably smaller than the lifetime expected from direct band-to-band transition probability. For lowto moderately doped silicon, this can be explained by the presence of recombination centers in the crystal [21, 22]. These are energy states distributed within the bandgap and created by impurities other than dopants, such as heavy metals. The minority carrier can thus orbit for a short time around the center with an energy intermediate between the valence and conduction band edges and give its energy to the crystal in a two- or multiple-step process, transferring to the crystal a smaller amount of energy in each step. The different transitions through intermediate steps are shown schematically in Fig. 2.21 [23]. The centers are shown at mid-gap for simplicity, but in real crystals this is not the case as can be seen from Fig. 2.22 which shows the energy levels associated with a number of different impurity atoms [24]. From statistical analysis, it can be shown that the efficiency of a center to act as a recombination or generation site is at maximum when its energy level is exactly at mid-gap [21–24]. By assuming an effective density of recombination-generation centers, NT, located at mid-gap, the rate of recombination (and generation) of minority carriers can be approximated as U ¼ σvth N T Δn U ¼ σvth N T Δp

ðelectronsÞ cm3 =s

ð2:62Þ

ðholesÞ cm3 =s

ð2:63Þ

where U is the recombination rate (cm3/s); σ is the capture cross section, assumed to be the same for electrons and holes (ffi1015 cm2); vth is the thermal velocity (ffi107 cm/s); and NT is the effective density of recombination-generation centers (cm3).

Before After

Electron capture

Before After

Electron emission

Before After

Before After

Hole capture

Hole emission

Fig. 2.21 Schematic model for transitions through intermediate states. Arrows represent direction of electron transition. (Adapted from [23])

2.6 Non-Equilibrium Conditions

57

0.55(A)

0.49(D) 0.54(A) 0.53(A)

0.26(D)

0.29(D)

Zn

Au

0.35(A) 0.40(A)

Co

0.22(D) 0.30(D)

0.35(A) 0.33(D) 0.53(A) 0.23(A) 0.34(D)

V

Ni

0.14(D)

0.37(D) 0.51(D)

0.40(A) 0.34(D) 0.40(D) 0.24(A) 0.31(D)

Mo

Cu

EC

W

Fe

Ei

EV

Fig. 2.22 Measured ionization energies for selected deep-level impurities in silicon. Levels above Ei are referenced to EC and levels below Ei are referenced to EV. (Adapted from [24])

The density of recombination-generation centers depends on the crystal properties and processing conditions. In good crystals, NT ranges typically from 1010 to 1012 cm3. In case of N-type silicon, the hole lifetime can be approximated as τSRH ¼

Δp 1 s ¼ U σvth N T

ð2:64Þ

A similar relation is found for minority carrier electrons. Generation–recombination through intermediate states is referred to as the Shockley-Read-Hall (SRH) process, and τSRH is the Shockley-Read-Hall lifetime [21, 24]. (c) Auger Recombination Another mechanism for a minority carrier to recombine is to transfer its excess energy and momentum to a third carrier available in its vicinity. This recombination process is known as Auger recombination and illustrated in Fig. 2.23 [25, 26]. Auger recombination requires at least two free majority carriers in the vicinity of the minority carrier, one with which the minority carrier recombines and another to which it gives the resulting energy and momentum. Auger recombination becomes significant, even dominates, in heavily doped regions, in the range 1019–1021 cm3, where free majority carriers are abundant. The Auger recombination lifetime is approximated for holes in N-type silicon as τAp ffi

1 s r Ap n2

ð2:65Þ

1 s r An p2

ð2:66Þ

and for electrons in P-type silicon as τAn ffi

58

2 Review of Single-Crystal Silicon Properties

Fig. 2.23 Auger recombination. Electron (1) recombines with hole (2). An electron (3) in the vicinity absorbs the excess energy and momentum

1 3

3

2

Before

After

where n and p are, respectively, the majority carrier electron and hole concentrations and rAp and rAn are the Auger recombination rates found at room temperature as [25] r Ap ¼ 9:9  1032 cm6 =s

ð2:67Þ

r An ¼ 2:8  1031 cm6 =s

ð2:68Þ

In the presence of Auger recombination, the effective carrier lifetime is limited by a combination of SRH and Auger recombination mechanisms as 1 τpeff 1 τneff

¼ ¼

1 τSRH 1 τSRH

þ þ

1 τAp 1 τAn

s1

ð2:69Þ

s1

ð2:70Þ

(d) Diffusion Length Continuity for each type of carrier relates the net rate of change of carriers within a volume element to the generation, recombination, and the flow of carriers into or out of the volume element. Consider, for example, N-type silicon in which electron–hole pairs are generated, e.g., by light in a volume region of the crystal. The one-dimensional continuity relation for minority carrier holes is dp Δp 1 djp cm3 s1 þ ¼G dt τp q dx

ð2:71Þ

where the three terms represent generation, recombination, and current divergence, respectively. Under steady-state conditions, the rate of change in the minority carrier concentration is dp dΔp ¼ ¼0 dt dt

ð2:72Þ

2.6 Non-Equilibrium Conditions

59

and 1 djp Δp ¼G cm3 s1 q dx τp

ð2:73Þ

If a point is chosen far away from the source of generation, G ¼ 0 and 1 djp Δp ¼ cm3 s1 q dx τp

ð2:74Þ

The current density jp has a drift and diffusion component. Since holes are minority carriers, they do not contribute appreciably to the total drift current. In this case, only the diffusion component of hole current is significant and can be approximated as jp ¼ qDp

dΔp A=cm2 dx

ð2:75Þ

Substituting the above expression in (2.74) gives d2 Δp Δp ¼ dx2 Dp τ p

ð2:76Þ

For regions very far away from the source of generation, one can set x ¼ 1 and Δp ¼ 0. The solution of (2.76) with this boundary condition has the form Δp ¼ Δp0 ex=

pffiffiffiffiffiffiffi Dp τ p

cm3

ð2:77Þ

where Δp0 is the excess hole concentration at the point of reference x ¼ x0. The square root term in the exponent is the average distance at which the excess carrier concentration has decayed to 1/e of its value at the reference point x ¼ x0 (Fig. 2.24). This distance is referred to as the hole diffusion length, Lp, where Lp ¼

pffiffiffiffiffiffiffiffiffiffi Dp τp cm

ð2:78Þ

Similarly, for minority carrier electrons Ln ¼

pffiffiffiffiffiffiffiffiffiffi Dn τn cm

ð2:79Þ

The minority carrier diffusion length depends mainly on its lifetime since the diffusivity, D, which is proportional to μ (2.52), does not vary widely within a doped crystal, yet the lifetime may vary orders of magnitude depending on the concentration of lifetime-killing (i.e., SRH) impurities.

60

2 Review of Single-Crystal Silicon Properties

Excess minority carriers (%)

100 90 80

70 60

L=2.0 μm

50

L=0.75 μm

0.25 μm

40

36.8%

30 20 10 0

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Distance from light source, x (mm) Fig. 2.24 Excess minority carrier concentration versus distance for three diffusion lengths L

Example 2.6 The electron lifetime in a 10 Ω-cm P-type silicon crystal is 0.5 ms at 25  C. Estimate (a) the effective density of recombination centers and (b) the electron diffusion length. Solution (a) Electrons are minority carriers. Assuming a thermal velocity vth ¼ 107 cm/s and a capture cross section σn ¼ 1015 cm2, the effective density of recombination centers is found from (2.63) as NT 

5  10

4

1 ¼ 2  1011 cm3  107  1015

(b) From Fig. 2.16, the acceptor concentration in a 10 Ω-cm silicon crystal is approximated as 1.2  1015 cm3. The electron mobility at this concentration is estimated from Fig. 2.15 as 1300 cm2/Vs. The electron diffusivity is found from (2.52) as Dn ¼ μn

kT ¼ 1300  0:0257 ¼ 33:4 cm2 =s q

Substituting the values in (2.76) gives the electron diffusion length: Ln ¼

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 33:4  5  104  0:13 cm

Problems

61

Problems 1. A region in silicon is uniformly doped with 1018 boron atoms/cm3. Assume the region to have a length of 50 nm, a width of 1 μm, and a thickness of 100 nm, and estimate the number of boron atoms in the region. What is the average distance between two boron atoms? 2. What is the percentage of covalent bonds broken in pure silicon at 100  C? 3. Silicon is doped with 1016 cm3 phosphorus atoms/cm3. At what temperature would the hole concentration be equal to 10% of the ionized impurity concentration? 4. Silicon is doped with 1015 cm3 phosphorus atoms/cm3. At what temperature is n ¼ 0.9 ND? (Use the Fermi–Dirac distribution function.) 5. Calculate the conductivity of pure silicon at 25  C and for silicon doped with 1016 boron atoms/cm3 plus 1016 arsenic atoms/cm3. 6. The sheet resistance RS of a film is defined as the resistance measured between two opposite sides of a square of the film. Show that for a film thickness t, the sheet resistance along the surface is RS ¼

ρ t

where ρ is the average film resistivity. 7. The boron profile in a 0.1-μm-deep transistor region in silicon can be approximated by an exponential function of the form N A ðxÞ ¼ 5  1018 e90x where x is the depth in μm from the surface. (a) Calculate the average sheet resistance at 25  C. (b) Show that the built-in field is constant in the region. 8. An N-type layer in silicon is formed by phosphorus ion-implantation into a 10 Ω-cm substrate. The phosphorus profile after activation can be approximated by a Gaussian distribution as N D ð xÞ ¼

2 2 ϕ pffiffiffiffiffi eðxRp Þ =2ΔRp ΔRp 2π

where ϕ is the implanted dose in atoms/cm2, Rp is the projected range, and ΔRp is the straggle. Assume full ionization, and rind the sheet resistance of the layer at 25  C for ϕ ¼ 5  1012 cm2, Rp ¼ 0.13 μm, and ΔRp ¼ 0.05 μm. 9. Consider a homogeneous conductor of conductivity σ and dielectric permittivity ε. Assume a mobile charge concentration

62

2 Review of Single-Crystal Silicon Properties

ρðx; y; z; t ¼ 0Þ in space at a time t ¼ 0. The following relations stem from electromagnetism: ∇ D ¼ ρ;

D ¼ εE;

J ¼ σE;

∇ J ¼

dρ dt

Show from these facts that ρðx; y; z; t Þ ¼ ρðx; y; z; t ¼ 0Þet=ðε=σÞ Interpret this result to show that mobile charge cannot remain in the bulk of uniform conducting material but must accumulate at surfaces of discontinuity or other places of nonuniformity. Find the value of the “dielectric relaxation time” ε/σ for a typical metal and for P-type silicon with NA ¼ 1015 cm3 and N-type silicon with ND ¼ 1017 cm3 [3]. 10. An N-type region in silicon is uniformly doped with arsenic at a concentration ND ¼ 1020 cm3. Assume full ionization and an effective density of recombination centers NT ¼ 1012 cm3, and estimate the hole diffusion length in the region at 25  C.

References 1. C. Kittel, Introduction to Solid-State Physics (Wiley, New York, 1968) 2. W. Shockley, Electrons and Holes in Semiconductors (D. Van Nostrand Company, 1950) 3. R.B. Adler, A.C. Smith, R.L. Longini, Semiconductor electronics education committee, in Introduction to Semiconductor Physics, vol. 1, (Wiley, 1964) 4. W. Finkelburg, Einfuehrung in die Atomphysik (Springer, 1958) 5. J.L. Moll, Physics of Semiconductors (McGraw-Hill, 1964) 6. A.J. Dekker, Solid State Physics (Prentice-Hall, 1965) 7. F.J. Morin, J.P. Maita, Electrical properties of silicon containing arsenic and boron. Phys. Rev. 96(1), 28–35 (1954) 8. E.M. Conwell, Properties of silicon and germanium. Part II, Proc. IRE 46(6), 1281–1300 (1958) 9. B. El-Kareh, Fundamentals of Semiconductor Processing Technologies (Kluwer Academic Press, 1995) 10. G.W. Ludwig, R.L. Watters, Drift and conductivity mobility in silicon. Phys. Rev. 101(6), 1699–1701 (1956) 11. E.M. Conwell, V.F. Weisskopf, Theory of impurity scattering in semiconductors. Phys. Rev. 77 (3), 388–390 (1950) 12. B. El-Kareh, Silicon Devices and Process Integration, Deep Submicron and Nano-Scale Technologies (Springer, 2009) 13. D.M. Caughey, R.E. Thomas, Carrier mobilities in silicon empirically related to doping and field. Proc. IEEE 55(12), 2192–2193 (1967) 14. G. Baccarani, P. Ostoja, Electron mobility empirically related to phosphorus concentration in silicon. Solid State Electron. 18(6), 579–580 (1975)

References

63

15. D.A. Antoniadis, A.G. Gonzalez, R.W. Dutton, Boron in near intrinsic and silicon under inert and oxidizing ambients – Diffusion and segregation. J. Electrochem. Soc.: Solid-State Science and Technology 125(5), 813–819 (1978) 16. S. Wagner, Diffusion of boron from shallow ion implants in silicon. J. Electrochem. Soc.: SolidState Science and Technology 119(1), 1570–1576 (1972) 17. N.D. Arora, J.R. Hauser, D.J. Roulston, Electron and hole mobilities in silicon as a function of concentration and temperature. IEEE Trans. Electron Dev. ED-29(2), 292–295 (1982) 18. W.W. Gartner, Temperature dependence of junction transistor parameters. Proc. IRE 45(5), 662–680 (1957) 19. J.C. Irvin, Resistivity of bulk silicon and of diffused layers in silicon. Bell Syst. Tech. J. 41, 387–410 (1962) 20. W.R. Thurber, R.L. Mattis, Y.M. Liu, J.J. Filliban, Resistivity-dopant density relationship for phosphorus-doped silicon. J. Electrochem. Soc.: Solid-State Science and Technology 12(8), 1980 (1807) 21. W. Shockley, W.T. Read, Statistics of the recombination of holes and electrons. Phys. Rev. 87 (5), 835–842 (1952) 22. R.N. Hall, Electron-hole recombination in germanium. Phys. Rev. 87(2), 387 (1952) 23. A.S. Grove, Physics and Technology of Semiconductor Devices (Wiley, 1967) 24. S.M. Sze, Physics of Semiconductor Devices (Wiley, 1981) 25. J. Dziewior, W. Schmid, Auger recombination coefficients for highly doped and highly excited silicon. Appl. Phys. Lett. 31(5), 346–348 (1977) 26. G. Augustine, A. Rohatgi, N.M. Jokerst, Base doping optimization for radiation-hard Si, GaAs, and InP solar cells. IEEE Trans. Electron Dev. 39(10), 2395–2400 (1992)

Chapter 3

PN Junctions

Abstract The PN junction is the fundamental building block of most silicon devices. The junction shape, doping profile, and characteristics have a direct impact on device and circuit performance. The chapter begins with a basic description of junction types and their thermal equilibrium characteristics. This is followed by a review of junction forward-bias characteristics under low-level and high-level injection and reverse-biased characteristics under low- and high-field conditions. The junction switching behavior and reverse recovery time are then described, followed by examples of stand-alone junction applications.

3.1

Introduction

A junction is formed when two dissimilar materials come in contact with each other. The junction between a P-type and an N-type semiconductor is called a PN junction. A PN junction has the properties of a rectifier: It exhibits a very low resistance in one voltage polarity, ideally approaching a short circuit, and a very high resistance in the opposite polarity, ideally approaching an open circuit. It is the fundamental building block of most devices. The junction shape, doping profile, and characteristics have a direct impact on device and circuit parameters. A thorough discussion of junction properties is essential to understand the operation of silicon devices and integrated circuits. The first part of the chapter begins with a basic discussion of the different junction types and their characteristics. This is followed by a brief description of junction applications.

3.2

Structure and Types

Consider two uniformly doped N-type and P-type silicon regions and assume for simplicity that the acceptor doping concentration, NA, in the P-type material is the same as the donor concentration, ND, in the N-type material (Fig. 3.1a). Each bar is © Springer Nature Switzerland AG 2020 B. El-Kareh, L. N. Hutter, Silicon Analog Components, https://doi.org/10.1007/978-3-030-15085-3_3

65

66 Fig. 3.1 Idealized PN junction. (a) Separated N-type and P-type crystals. (b) Regions brought in contact. (c) Donor and acceptor profiles near metallurgical junction. (d) Space charge (depletion) region at equilibrium. E: Electric field

3 PN Junctions

(a)

N-type

(b)

P-type

N-type

P-type ND=NA (Metallurgical junction) NA

ND , NA ND (c)

NA partially compensates ND Symbol

ND partially compensates NA

N

P E

xdn

(d)

N-type

xdp

+ + + + + +

P-type

xd

Depletion region

neutral as a whole: Free electrons compensate the positively charged donors in the N-regions, and holes compensate the negatively charged acceptors in the P-region. In a thought experiment, let the two bars be instantaneously brought in contact (Fig. 3.1b). Initially, one would expect to find an infinitesimally thin (abrupt) transition region from P-type to N-type material. In reality, however, such abrupt transitions do not exist because, as the junction is formed at high temperature, the high acceptor and donor concentration gradients at the boundary will cause impurities to diffuse across the boundary. The transition will then have a finite width within which donors and acceptors are partially compensated (Fig. 3.1c). The locus of points where donors and acceptors are exactly equal is called the metallurgical junction. Because holes are majorities in the P-region and minorities in the N-region, a gradient in the hole concentration is established between the two sides. Similarly, a gradient in electron concentration is established between the N-side and P-side. Because of the large carrier concentration gradients, electrons diffuse from the N-region, where they are majority carriers, into the P-region where they become minority carriers. Similarly, holes diffuse from the P-region to the N-region. Will this process continue until the concentration of electrons and holes becomes the same in both regions? No, because when the electrons diffuse away from the N-region, they leave behind a region which is almost void of electrons, consisting of, non-neutralized, positively charged immobile donor ions. Similarly, the diffusion

3.2 Structure and Types

67

of holes leaves a negative charge of non-neutralized, fixed acceptor ions in the P-region (Fig. 3.1d). The region void of free carriers is called the depletion region or space charge region. Thus, the depletion region, or space charge region, straddles the metallurgical junction and creates an electric field which points from positive ions to negative ions, causing electrons to drift back to the N-region and holes to drift back to the P-region. At equilibrium, drift and diffusion current components cancel each other for each carrier type. Although there is a constant traffic of carriers in both directions, the net current is zero. In the following we will assume that a depletion width xd is defined within which the free carrier concentration is zero, i.e., the charge within xd is only due to non-neutralized ionized dopants. We will also assume that the region of transition from N-type to P-type silicon is negligible, compared to xd. This simplifies the junction analysis considerably without introducing an appreciable error. Since the crystal as a whole must remain neutral, the positive ion charge per unit area in the N-region must be neutralized by an equal amount of negative ion charge per unit area in the P-region. This is shown schematically in Fig. 3.1d with field lines drawn crossing the metallurgical junction. Junctions of the form in Fig. 3.1 are only found is special cases such as growing a uniformly doped N-type layer on a uniformly doped P-type substrate. They are referred to as step junctions because the transition from P-type to N-type is nearly abrupt and the concentrations in both regions are uniform. Most modern junctions, however, are formed by implantation followed by a thermal cycle to activate and redistribute impurities. They are hence nonuniformly doped (Figs. 3.2 and 3.3).1 Dopants are implanted through the opening. Activation is required because, immediately after implantation, only a small fraction of dopants occupy substitutional sites and are active. The implant energy, temperature, and duration of the thermal cycle determine the junction depth xj and its lateral extent at the surface xℓ. The impurity distribution and geometrical shape can be complex, requiring sophisticated two-dimensional or even three-dimensional analytical techniques and numerical simulations to predict the junction profile and electrical properties [1]. Figure 3.2a is a schematic cross section of two planar junctions formed at the silicon surface. Both junctions and their depletion regions intercept an interface with oxide. In the junction on the left of Fig. 3.2a, dopants move vertically to a junction depth xj and laterally to a junction extent xℓ from the mask edge. The lateral extent xℓ is typically smaller than xj, ranging from xℓ ffi 0.5xj to xℓ ffi xj. The junction depth and lateral extent depend on several factors, including temperature, duration of thermal treatment, diffusivity, concentration of impurities, junction size, and doping method. The junction on the right of Fig. 3.2a is bounded laterally by oxide-filled shallow trench isolation (STI). While dopants also penetrate the oxide in STI regions, they are inactive there and do not directly impact the junction characteristics. The oxide

1 Doping techniques and other processing steps are described in “Fundamentals of Semiconductors Processing Technologies,” by B. El-Kareh, Kluwer Academic Publishers, Boston, 1995.

68

3 PN Junctions

Boron implantation

Oxide

P+ xj

x

(a)

Blocking Mask

P+ xj

STI

xl

N

STI STI

N

Depletion boundary

10 20

(b)

Net concentration |NA – ND| (cm-3)

Implanted Dose = 1014 cm-2

10 19

xj1

10 18

xj2

xj3

Boron

10 17 Dt = 0.042 μm

0.060 mm

Phosphorus

0.071

10 16 10 15

0

0.1

0.2

0.3

0.4

0.5

Distance x from surface (mm)

Fig. 3.3 One-dimensional profile of deep-implanted phosphorus in a P-type silicon region, followed by the implantation of a shallower P-region, forming a buried junction

Net concentration, |NA-ND| (cm-3)

Fig. 3.2 (a) Illustration of forming junctions by ion-implanting boron into a phosphorus-doped substrate. (b) Vertical boron profiles for three different thermal cycles 10 20 10 19

Jct-1, xj1

10 18

Boron

Phosphorus Boron

10 17 10 16

Jct-2, xj2

10 15

Buried junction

10 14

10 13

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

Distance from surface (mm)

can, however, affect the dopant distribution in silicon and electrical field near the silicon surface and at its interface with the STI, as will be detailed in Chap. 9. Figure 3.2b illustrates the nonuniform profiles of boron implanted into a uniformly doped N-region and subjected to three different pffiffiffiffiffi thermal cycles. The figure shows the junction depth xj for three values of Dt , where D is the temperature-

3.3 Junction Characteristics at Thermal Equilibrium

Drawn image

xl Lateral extent

Lateral junction boundary W

69 Corner rounding after processing.

Patterned image, corner rounding

L

Fig. 3.4 Top view of a junction formed through a rectangular opening illustrating corner rounding and lateral extent

dependent diffusivity and t is the duration of thermal treatment. Figure 3.3 shows the doping profiles of a junction xj2 formed below the surface, i.e., the junction boundaries do not intercept the silicon surface. In this example, phosphorus is implanted into a P-type substrate at high energy to a depth far below the surface, forming a “buried” junction at xj2 with the P-type substrate. The junction at xj1 is of the type of the left junction in Fig. 3.2a and thus intercepts the surface. The importance of a “buried” junction is discussed in Sect. 3.6.

3.2.1

Cylindrical and Spherical Approximations

Figure 3.4 is a schematic top view of a junction formed through a rectangular mask opening. While the corners are typically drawn sharp in the layout, they are typically rounded during processing. For not too small dimensions W and L, the concentration within the opening, away from the boundaries, is only a function of depth x. Near the junction boundaries, however, the concentration becomes also a function of lateral distance from the boundaries. Thus, the dopant profile becomes two-dimensional at edges and threedimensional at corners (Fig. 3.5). For simplicity, junction edges are approximated by cylindrical shapes and junction corners by spherical shapes.

3.3

Junction Characteristics at Thermal Equilibrium

For a uniform junction temperature and without external disturbances such as light or other types of radiation, the junction is at thermal equilibrium. The characteristics of the junction depend on the dopant profiles on both sides of the junction, particularly near the metallurgical junction. The profile can be uniform, as assumed in Fig. 3.1, or of arbitrary shape, as shown in Figs. 3.2 and 3.3. Only simple step junctions are analyzed in this section. They may serve as useful approximations to most real junctions.

70

3 PN Junctions S S: Spherical corner C

xl

Mask boundaries

C

W

L C: Cylindrical edge S

P: Plane floor

C xj S

Fig. 3.5 Approximation of junction edges by cylindrical shapes and junction corners by spherical shapes [2]

qN D+ + D

xdn N = xdp N

− A

p = N , neutral

− A

≠

+

Space charge

-

− qN A−

xdp

xdn

Actual depleted profile xÆ

n − N D− , neutral

xd = xdn + xdp

Depletion approximation Fig. 3.6 Depletion approximation, depletion width, and neutral regions in a step junction

3.3.1

Step Junction

In a step junction, the depletion approximation allows dividing the junction into three distinct regions, a fully depleted region sandwiched between a neutral N-region where ionized donors N þ D are balanced by electrons and a neutral P-region where ionized acceptors N  A are balanced by holes (Fig. 3.6). The neutrality principle requires that the total positive ion charge within xdn, denoted by a single plus sign, is numerically equal to the total negative ion charge within xdp, denoted by a single minus sign, where xdn and xdp are, respectively, the depletion width in the N-type and P-type regions. Thus,

3.3 Junction Characteristics at Thermal Equilibrium

71

xd ¼ xdn þ xdp cm

ð3:1Þ

 2 xdn N þ D ¼ xdp N A cm

ð3:2Þ

Example 3.1 A PN junction is uniformly doped with NA ¼ 1015 cm3 in the P-side and ND ¼ 1016 cm3 in the N-side. The total depletion width is xd ¼ 1 μm. (a) Find xdp and xdn. (b) What are the thermal equilibrium minority-carrier concentrations at room temperature? Solution (a) Combining (3.1) and (3.2) gives xdp N  N D xd  xdn ¼ Dffi ¼ ¼ 10; xdn N þ NA xdn A

xdn ffi 0:091 μm;

xdp ffi 0:91 μm:

(b) The majority-carrier concentrations in the P- and N-regions are pp ffi N A ¼ 1015 cm3 and nn ffi N D ¼ 1016 cm3 . At room temperature, the thermal equilibrium product of majority- and minority-carrier concentrations is nn pn ffi pp np ¼ n2i ffi 2  1020 cm6 . The minority-carrier concentrations are then calculated as pn ffi

n2i 2  1020 n2i 4 3  ffi ffi 2  10 cm ; n ffi ffi 2  105 cm3 p ND NA 1016

(a) The Electric Field The electric field distribution may be visualized by considering the schematic cross section of a step junction in Fig. 3.7a. For each positive ion within the depleted region, there is one field line that points from the positive ion to a negative ion. The number of field lines per unit area is equal to the number of depleted positive or negative ions per unit area. Assume that an imaginary plane moves from the neutral N-region on the right, through the depletion region, to the neutral P-region on the left. In the neutral N-region, positive donors are compensated by electrons, so the net number of field lines crossing the plane is zero. As the plane moves into the depletion region, the number of field lines crossing the plane, and hence the field intensity, increases linearly (Fig. 3.7b). When the plane reaches the metallurgical junction, the number of field lines crossing the plane is at its maximum, and the field reaches its maximum (peak). As the plane moves from the metallurgical junction to the P-region, the field drops linearly with distance from the metallurgical junction. The field is zero again when the plane reaches the neutral P-region.

72

3 PN Junctions

P-type

(a)

Imaginary plane

------- ----- ----- ----- ----- ----- ----- ----- ---xdp

++++++ ++++++ ++++++ ++++++ ++++++ ++++++ ++++++ ++++++ ++++++ xdn xd Depletion region Electric field, E xdn x=0

xdp

N-type

x

x

E

Metallurgical junction

(b) E(x)

Epeak

Fig. 3.7 Schematic of a step junction at thermal equilibrium. (a) Imaginary plane moving from right to left. (b) Field distribution

The rate of change of electric field E with distance is related to the charge density ρ by Gauss law given in one dimension as dE ρðxÞ V=cm2 ¼ dx ε0 εSi

ð3:3Þ

where ε0 ¼ 8.86  1014 F/cm is the permittivity of free space, εSi ¼ 11.7 is the dielectric constant of silicon, and the charge density is given by ρ ¼ qðp  n þ N A  N D Þ C=cm3

ð3:4aÞ

With the depletion approximation and assuming uniform ND and NA, the charge density within xdn is constant and found as ρ ¼ qN D C=cm3

ð3:4bÞ

Similarly, the charge density within xdp is ρ ¼ qN A C=cm3

ð3:4cÞ

The field is calculated by integrating (3.3) with respect to distance. Since ρ is constant, the field magnitude varies linearly with distance from x ¼ 0, as shown in Fig. 3.7. The peak field is calculated as

3.3 Junction Characteristics at Thermal Equilibrium

Epeak ¼

Qpeak qx N D qxdp N A ¼  dn ¼ V=cm ε0 εSi ε0 εSi ε0 εSi

73

ð3:5Þ

Example 3.2 (a) Find the peak field in the depletion region in Example 3.1. (b) What is the field intensity halfway between the neutral P-region and the metallurgical junction? Solution (a) Substituting the values for NA, ND, xdn, and xdp from Example 3.1 in (3.5) gives Epeak ffi

0:091  104  1:6  1019  1016 ffi 1:4  104 V=cm 8:86  1014  11:7

Epeak ffi

0:91  104  1:6  1019  1015 ffi 1:4  104 V=cm 8:86  1014  11:7

or

(b) Since, for a step junction, the field drops linearly from the neutral P-region to the metallurgical junction, E drops to half Epeak.

(b) The Built-In Voltage The presence of an electric field within the depletion region implies the presence of a voltage dropped across the two sides of the junction. This internal voltage is referred to as the contact potential or the built-in voltage, Vbi. The built-in voltage cannot be measured directly. In other words, one cannot just attach leads of a voltmeter to the junction ends and measure the built-in voltage. This is because at every metal-tometal or metal-to-silicon contact, there will also be a built-in voltage (or contact potential) such that the loop sum of all built-in voltages is zero. It is not simple to prove this, but one can argue that if one would be able to measure a voltage between the two ends of the junction without supplying energy to the junction, one would have perpetual motion. The built-in voltage can, however, be calculated or extracted. (c) Equilibrium Band Diagram for Step Junction The energy band diagram is shown for isolated P- and N-regions in Fig. 3.8a and for the PN junction in Fig. 3.8b, assuming uniform doping in both regions. In a junction at thermal equilibrium, there is no net current in any direction, so the Fermi level must align throughout the junction (Fig. 3.8b).

74

3 PN Junctions

EC (a)

fbp < 0 P-type

fbn > 0

Ei

EC EF Ei

EF EV

EV N-type |Vbi| = |fbp|+ |fbn|

(b)

fbp < 0 fbn > 0

P-type

EC EF Ei EV

N-type Fig. 3.8 Energy band diagrams. (a) For separate P- and N-regions. (b) For PN junction at thermal equilibrium

(d) Calculation of the Built-In Voltage The bulk Fermi potentials were defined for uniform P- and N-regions in the previous chapter. They are repeated here for convenience: ϕbp ¼ 

kT NA ; ln ni q

ϕbn ¼

kT ND V ln ni q

ð3:6aÞ

Bringing the two regions in contact results in a potential difference between the two regions [ϕbn  (ϕbp)] ¼ [ϕbn + ϕbp]. This difference is the contact potential or built-in voltage, Vbi, where    kT NAND V bi ¼ ϕbn  ϕbp ¼ ϕbn þ ϕbp ¼ V ln q n2i

ð3:6bÞ

Vbi depends on temperature and on dopant concentrations at the depletion boundaries. In a step junction, the concentrations are uniform and hence the same at the depletion boundaries as in the neutral regions. The built-in voltage acts as a barrier for electrons to move from the N-region to the P-region and for holes to move from the P-region to the N-region. The thermal equilibrium majorityand minority-carrier concentrations at the depletion boundaries follow the Boltzmann distribution law, similarly to molecules in (2.5): np ¼ nn eqV bi =kT ;

pn ¼ pp eqV bi =kT cm3

ð3:7Þ

where np , pn are the minority electron and hole concentrations at xdp and xdn, respectively, and nn , pp are the majority electron and hole concentrations at xdn and xdp, respectively.

3.3 Junction Characteristics at Thermal Equilibrium

75

Example 3.3 The uniform dopant concentrations in a PN junction are NA ¼ 1016 cm3 and ND ¼ 5  1018 cm3. Find the built-in voltage at 50, 25, and 150  C. Assume full ionization at all temperatures. Solution The intrinsic carrier concentration ni is found from (2.15). Substituting the values for ni, NA, ND, and T in (3.6b) gives the built-in voltage. The results are given in Table 3.1. Table 3.1 Built-in voltage results Temperature ( C) 50 25 150

Temperature (K) 223 298 423

ni (cm3) 3.42  106 1.25  1010 1.95  1013

Vbi (V) 0.957 0.858 0.682

(e) The Depletion Width The voltage in the positive x-direction is related to the charge density by the Poisson’s relation d2 V ð x Þ ρð xÞ ¼ 2 dx ε0 εSi

ð3:8Þ

and the electric field is related to the voltage by EðxÞ ¼ 

dV ðxÞ V=cm dx

ð3:9Þ

The voltage Vn between x ¼ xdn and x ¼ 0 in Fig. 3.7 is then found for the step junction by integrating (3.5) as Vn ¼

Epeak  xdn qN D x2dn ¼ V 2 2ε0 εSi

ð3:10aÞ

Similarly, the voltage Vp in the P-region is given by Vp ¼

Epeak  xdp qN A x2dp ¼ V 2 2ε0 εSi

ð3:10bÞ

The total voltage across the depletion region is V bi ¼ V n þ V p V

ð3:10cÞ

76

3 PN Junctions

This voltage should be the same as in (3.6b). Combining (3.5) and (3.10a)– (3.10c), the depletion widths in the N-region and P-region are found as sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ε0 εSi V bi 1 V bi 3 cm ffi 3:6  10 ¼ N D ð1 þ N D =N A Þ q N D ð1 þ N D =N A Þ

xdn

xdp

ð3:11aÞ

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ε0 εSi V bi 1 V bi 3 cm ¼ ffi 3:6  10 q N A ð1 þ N A =N D Þ N A ð1 þ N A =N D Þ

ð3:11bÞ

The total depletion width in a step junction is sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi    ffi 2ε0 εSi 1 1 1 1 3 V bi ffi 3:6  10 V bi cm þ þ xd ¼ q NA ND NA ND

ð3:11cÞ

Example 3.4 Find xd, xdn, and xdp for the three temperatures in Example 3.3. Solution The depletion width is calculated from (3.11a, 3.11b, and 3.11c) as sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffi  ffi 1 1 V bi 3 xd ¼ 3:6  10 V bi ffi 3:6  10 cm þ 1016 1016 5  1018 3

The total depletion width xd is found by substituting in the above equation the values for Vbi found in Example 3.3. The individual depletion widths xdp and xdn are then approximated by combining (3.1) and (3.2). Table 3.2 summarizes the results for the three temperatures. Table 3.2 Depletion width example, NA ¼ 1016 cm3 and ND ¼ 5  1018 cm3 Temperature Vbi (V) xd (nm) xdp (nm) xdn (nm)

50  C 0.957 352 351 0.7

25  C 0.858 333 332 0.7

150  C 0.682 298 297 0.6

From the above example, one can conclude that if one side of the step junction is much higher doped than the other, the depletion region expands almost entirely into the lighter doped side. Thus, if ND  NA, then 1/ND  1/NA and (3.11a, 3.11b, and 3.11c) simplifies to xd ffi 3:6  103

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi V bi =N A cm

ð3:12Þ

For a heavily doped N-region, this type of junction is referred to as an N+P junction. Similarly, for a P+N junction where NA  ND

3.3 Junction Characteristics at Thermal Equilibrium

77

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi V bi =N D cm

ð3:13Þ

Variation of charge F Variatio of voltage

ð3:14Þ

xd ffi 3:6  103 (f) Junction Capacitance The general definition of capacitance is Capacitance ¼

A parallel plate capacitor has the form of parallel conductor plates of area A separated by air of thickness t (Fig. 3.9). If the plates are connected momentarily to the terminals of a power supply, a charge +Q will appear on one plate and a charge Q on the other. If the distance t between the plates is small compared to the plate dimensions, the electric field lines will be uniformly spaced and parallel. There will always be some fringing field lines at the edges of the plates, but they are neglected here. Assuming air or vacuum between the plates (εair ¼ 1), the field intensity is E ¼ Q=ε0 V=cm

ð3:15Þ

where Q is the charge density in C/cm2 and ε0 ffi 8.86  1014 F/cm. For plates made of metal, where the electron density is in the range 1023 cm3, the charge can be assumed to reside entirely at the plate boundaries facing each other. Also, the variation of charge occurs at the plate boundaries. In this case, dQ/dV and Q/V give the same result and2 C¼

dQ Q ¼ F=cm2 dV V

ð3:16Þ

Combining (3.15) and (3.16) and noting that E ¼ V/t gives C¼

dQ Q ε0 F=cm2 ¼ ¼ t dV V

ð3:17Þ

If the space between the plates is filled completely with a charge-free insulator, also called dielectric, of thickness ti and dielectric constant εi, then the capacitance increases by a factor εi as C ¼ ε0 εi =t i F=cm2

ð3:18Þ

Thus, the dielectric constant ε (or κ) is the ratio of capacitance with the dielectric to that without, i.e., air or vacuum. For plates made of metal, the structure is referred to as a metal–insulator–metal (MIM) capacitor. Since the farad (F) is too large a unit for semiconductor dimensions, submultiples of the farad, the microfarad (1 μF ¼ 106 F), the nanofarad (1 nF ¼ 109 F), the picofarad (1 pF ¼ 1012 F), the femtofarad (1 fF ¼ 1015 F), and the attofarad (1 aF ¼ 1018 F) are used as more convenient units.

2

Unless otherwise stated, C denotes capacitance per cm2.

78

3 PN Junctions

+Q +

+

+

+

+

+

+

+

+

+ t

-Q

-

-

-

-

-

-

-

-

-

-

Fig. 3.9 Parallel plate capacitor with conductor plates at distance t apart. Top plate biased positive with respect to bottom plate

Example 3.5 The region between the plates of a parallel plate capacitor is completely filled with silicon dioxide of dielectric constant εox ¼ 3.9 and thickness 0.1 μm. One plate has an area of 100 μm2 and is centered over a second plate of area 300 μm2. Neglect fringe effects and find the total capacitance of the structure. Solution Neglecting fringe effects, the capacitance is proportional to the area common to both plates. For an area of 100 μm2, the capacitance is found from (3.18) as C¼A

ε0 εox 8:86  1014  3:9 ¼ 100  108  ¼ 34:6 fF t ox 0:1  104

A PN junction at thermal equilibrium consists of a depletion region sandwiched between a conducting P-region and a conducting N-region. Since the depletion region is assumed to be totally void of free carriers, it acts as an insulator. Thus, a structure having the geometry in Fig. 3.7a is similar to a parallel plate capacitor with the P-region and N-region acting as the plates and the depleted region as the insulator of dielectric constant εSi ¼ 11.7 between the plates (Fig. 3.10). The difference between a PN junction of the type shown in Fig. 3.10 and a MIM capacitor lies in the distribution of charge. In a PN junction, the charge is distributed between the “plates” rather than at the plate boundaries. For small signals, i.e., very small variations in voltage compared to the built-in voltage, the variation of charge can be assumed to occur at the depletion boundaries without appreciably disturbing the depletion conditions (Fig. 3.10). A typical small signal is a sine wave of amplitude ΔV ¼ 10–15 mV and 1 kHz–1 MHz frequency. At such frequencies, only majority carriers respond to the signal. During one half of the signal, ΔV has the same polarity as Vbi. The voltage across the depletion region increases to Vbi + ΔV, and Xdp and Xdn, respectively, increase infinitesimally by ΔXdp and ΔXdn, exposing additional charge ΔQP at the depletion boundary in the P-side, and +ΔQN at the depletion boundary in the N-side. Neutrality requires that |ΔQN| ¼ |ΔQP| ¼ |ΔQ|. Similarly, during the second half of the signal where ΔV is of opposite polarity to Vbi, the depletion widths decrease by Δxdp and Δxdn, respectively, reducing the total charge by ΔQ at the depletion boundaries. Thus, the junction can be treated as a parallel plate capacitor and the junction capacitance per unit area expressed as

3.3 Junction Characteristics at Thermal Equilibrium

79

E

Contact

Contact

±Dxdp

±Dxdn xj

P-type ΔQp

±

xdp

N-type ± DQn xdn

Equilibrium xd

DV± 10-15 mV signal

C=DQ /DV

Fig. 3.10 Variation of charge at the depletion boundaries in response to a small voltage signal

Cj ¼

ε0 εSi F=cm2 xd

ð3:19Þ

The width of the depletion layer, xd, can be determined from (3.11a, 3.11b, 3.11c), (3.12), or (3.13), depending on the dopant concentrations.3 Example 3.6 A PN junction of area 100  100 μm2 is uniformly doped with NA ¼ 5  1019 cm3 in the P-side and ND ¼ 1017 cm3 in the N-side. Find the total thermal equilibrium capacitance of the planar area at 25  C. Assume full ionization and neglect edge and corner effects. Solution The built-in voltage is V bi ¼

kT NDNA 5  1019  1017 ffi 0:0257 ln ¼ 0:970 V ln q n2i 2  1020

For a P+N junction, the depletion width can be approximated from (3.13) as rffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffi Vb 0:970 3 ¼ 0:112 μm xd ffi 3:6  10 ffi 3:6  10 ND 1017 3

From (3.19), the thermal equilibrium capacitance is found as C jtotal ffi 100  100  108 

3

8:86  1014  11:7 ffi 9:26 pF 0:112  104

At very high frequencies, the distributed series resistances and capacitances (RC components) can impact the frequency response of the junction. As a rule of thumb, the signal frequency should be smaller than RC. Note that RC has the unit time, t: R ¼ V/I, I ¼ Q/t, C ¼ Q/V, RC ¼ t.

80

3 PN Junctions

Mask edge

z

Mask q

y

x

r1

N+

xj

xdl

r2

rj B A

A’

C

B’

xd

D

P D’

C’

Fig. 3.11 Cylindrical edge approximation to estimate capacitance

(g) Effect of Curvature A cross section through the edge in Fig. 3.5 is shown in more detail in Fig. 3.11 [2]. Since a typical junction exhibits rounding at corners, the whole junction perimeter may be approximated as having a cylindrical shape. The edge in Fig. 3.11 can be treated similarly to one quarter of a coaxial cable with the N+ region acting as the core conductor and the P-region as the outer conductor. The radius of curvature of the N+ “core” is approximated as rj and that of the depleted region as r2. Since xd does not expand appreciably into the N+-region, r1 ffi rj. Comparing sections ABCD and A0 B0 C0 D0 , it can be determined that the charge at the edge segment AB in the N+-region is more concentrated than at the planar segment A0 B0 . Thus, because of the curvature, the peak electric field is higher at the metallurgical junction AB than in A0 B0 . The charge in the P-sided depletion region is distributed within a conic section ABCD, while, in the planar region, it is distributed in section A0 B0 C0 D0 of uniform cross section. It can be concluded that, to maintain neutrality, the depletion region expands less at the edge than in the planar part of the junction. Finally, because of the narrower depletion region, the capacitance per unit area is larger at the curved edge than in the planar part of the junction. A detailed analysis in cylindrical coordinates gives qN A r 22  r 21 V=cm 2ε0 εSi r j   qN A r 2 r 2  r 21 V bi ¼ V r 22 ln  2 2ε0 εSi rj 2 Epeak ¼

ð3:20Þ ð3:21Þ

With the approximation r1 ffi rj, and using the expression for Vbi in (3.6b), the above relation can be solved iteratively to give r2 from which the depletion width at the edge can be extracted. A similar relation is found for a P+N junction by replacing NA in (3.20) and (3.21) with ND.

3.4 Forward-Biased Junction

81

The capacitance per unit edge length is found by treating the cylinder as a coaxial transmission line with the edge of the junction constituting one quarter of the assumed cylinder as Cedge ¼

πε0 εSi F=cm 2 ln rr2j

ð3:22Þ

Example 3.7 For a junction depth xj ffi rj ¼ 0.20 μm, find the total edge capacitance in the junction of Example 3.6. Solution The built-in voltage is the same for the planar and edge regions. From Example 3.6, Vbi ¼ 0.970 V. Substituting this value and r1 ffi rj ¼ 0.20 μm in (3.21) gives  2 ! r 22  0:2  104 1:6  1019  1017 r2 2 r ln 0:970 ¼  V 2 2  8:86  1014  11:7 2 0:2  104

Solving the above equation by iteration gives r2 ffi 0.3043 μm, and substituting it in (3.22) gives the total edge capacitance as C edge-total ¼

3.4

4  100  104  3:1416  8:86  1014  11:7 0:155 pF 2 ln 0:3043 0:2

Forward-Biased Junction

In a junction at thermal equilibrium, the net current across the junction is zero. The built-in voltage, Vbi, acts as a barrier that ensures that the drift and diffusion currents are exactly balanced for each type of carrier, so that the net current is zero. This section discusses the characteristics of a junction when a forward-bias voltage is applied to the junction. A junction is forward-biased when a negative voltage is applied to the N-side with respect to the P-side or a positive voltage applied to the P-side with respect to the N-side, as shown in Fig. 3.12. Since a forward voltage VF is of opposite polarity to Vbi, the barrier is reduced from Vbi to (Vbi  VF). According to (3.7), one would expect the minority-carrier concentrations to increase at the depletion boundaries. A steady-state condition is rapidly reached whereby the minority-carrier concentrations at the depletion boundaries increase by Δnp in the P-region and Δpn in the N-region (Fig. 3.13). The distances between depletion boundaries and contacts are denoted by Wn and Wp, respectively, in the N-region and P-region. Ohmic contacts are discussed in Chap. 4. It suffices to say here that an ohmic contact is a region where excess

82

3 PN Junctions Ohmic contact

Ammeter

A xj

Oxide N+

+

xdp at equilibrium

Forward voltage, VF

xdp in forward bias P

Ohmic contact

Ground

Fig. 3.12 Forward-biased N+P junction; P-region at ground

minority carriers immediately recombine and carrier concentrations are at their thermal equilibrium levels. The increase in minority-carrier concentration due to forward bias is called minority-carrier injection. In the presence of excess minority carriers, the majority carriers must also increase by the same amount Δpp ¼ Δnp and Δnn ¼ Δpn to satisfy neutrality. For small values of VF, however, the injected excess minority-carrier concentration is negligible compared to the thermal equilibrium majority-carrier concentration. This condition is referred to as low-level injection. The following discussion applies to low-level injection. High-level injection effects are discussed in Chap. 5. The excess minority carriers create concentration gradients at the depletion boundaries. They hence diffuse from the boundaries into the neutral regions. The distance between the depletion boundary and the contact in the N-side is Wn, and the corresponding distance in the P-side is Wp. The diffusion of minority carriers is illustrated for wide neutral regions (Wn  Lp, Wp  Ln) in Fig. 3.13 and for narrow neutral regions (Wn  Lp or Wp  Ln) in Fig. 3.14. For wide neutral regions, the minority concentrations drop exponentially with distance from the boundaries as the minority carriers recombine with majority carriers supplied at the contacts. The diffusion is characterized by the diffusion lengths Ln and Lp (Chap. 2). Excess majority carriers must also be present and follow the exponential curve to neutralize the excess minority carriers at every point. At low-level injection, however, the fractional increase of majority-carrier concentration is negligible. The narrow structure shown in Fig. 3.14 is of particular importance because in most devices, the minority-carrier diffusion length is considerably larger than device dimensions. In this case, the excess minority-carrier concentrations can be approximated to fall off linearly with distance from the depletion boundaries so that recombination takes place directly at the contacts.

3.4 Forward-Biased Junction

83

xd

Contact

Contact

Wn

Wp pn

pn

Dpn

np Dnp

Lp xdn

xdp

np

Ln

Metallurgical junction Fig. 3.13 Diffusion of excess minority carriers in N- and P-regions where Wn  Lp; Wp  Ln. Slopes at boundaries: Δpn/Lp; Δnp/Ln Fig. 3.14 Linear decay of excess minority carriers in junction with narrow regions where Lp  Wn; Ln  Wp. Slopes: Δpn/Wn, Δnp/Wp

Wn

Wp

xd

pn Contact

Contact

Δpn

pn

np Δnp

np xdn

xdp

x

Metallurgical junction

The spatial gradients in the minority-carrier concentrations (slopes) at the depletion boundaries are Δpn/Lp and Δnp/Ln for wide regions (Fig. 3.13) and Δpn/Wn and Δnp/Wp for narrow regions (Fig. 3.14). It is the gradients that drive the diffusion current. The diffusion current thus consists of excess electrons transported from the N-region to the P-region and excess holes transported from P-region to the N-region. The forward current IF increases exponentially with forward voltage and follows Shockley’s relation

I F ¼ I S eqV F =kT  1 A where IS is referred to as the saturation current (see Problem 3.3). The saturation current for wide regions is

ð3:23Þ

84

3 PN Junctions

 IS ¼

qAn2i

Dp Dn þ Lp N D Ln N A

A

ð3:24aÞ

and for narrow regions is  I S ¼ qAn2i

Dp Dn þ W nND W pNA

A

ð3:24bÞ

where A is the junction area, ni the intrinsic carrier concentration, and Dp, Dn the minority hole and electron diffusivities. The saturation current is proportional to n2i . The product WpNA is referred to as the Gummel number in the P-region and the product WnND the Gummel number in the N-region. The injection ratio for electrons is γn ¼

In 1 ¼ I n þ I p 1 þ Dp W p N A =Dn W n N D

ð3:25aÞ

Similarly, the injection ratio for holes is γp ¼

Ip 1 ¼ I n þ I p 1 þ Dn W n N D =Dp W p N A

ð3:25bÞ

The forward voltage VF in (3.23) can be expressed explicitly as VF

kT IF ln A IS q

ð3:26Þ

Since the saturation current is proportional to n2i (Fig. 2.6), IS increases rapidly with increasing temperature, almost by a factor of 4 every 10  C. Thus, for a given forward current, VF decreases with increasing temperature. The temperature dependence of VF is shown in Fig. 3.15 for a junction with ND ¼ 5  1019 cm3 and NA ¼ 1015 cm3 and a current density 10 A/cm2. VF decreases by about 2 mV/ C. An ideal forward current–voltage characteristic for a junction at 25  C is shown on a semilogarithmic scale in Fig. 3.16. Since kT/q has a small value, approximately 0.026 V at 25  C, the exponential term in (3.23) becomes much larger than “1” as VF increases, so the “1” can be neglected. The slope in Fig. 3.16 is determined from (3.23) as (kT/q) ln 10.

3.4.1

Effect of Series Resistances

The forward voltage VF in (3.23) is the voltage that appears at the depletion boundaries and can be different from the power supply voltage. The “neutral” regions, contacts, and leads to the power supply have finite resistances, referred to

Forward voltage (V)

3.4 Forward-Biased Junction

0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -40

85

NA = 1015 cm-3, ND = 5×1019 cm-3 IF = 10 A/cm2 ~ - 2mV/oC

-20

0

20

40

60

Temperature

80

100

120

140

(oC)

Fig. 3.15 Dependence of VF on temperature for a forward current density of 10 A/cm2, ND ¼ 5  1019 cm3, and NA ¼ 1015 cm3

10-02

Forward current, IF (A)

Fig. 3.16 Ideal I–V characteristic of a forwardbiased PN junction

10-04 10-06 10-08 10-10

60 mV/decade

10-12 10-14 10-16

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Forward voltage, VF (V)

as series and contact resistances. The resistances can cause voltage losses in the form of IR drops between the power supply terminals and the depletion boundaries. In this case, the forward voltage at the depletion boundaries reduces to VF ¼ Vapp  IFR, where Vapp is the applied voltage measured at the power supply terminals and R the sum of all resistances between the power supply terminals and the depletion boundaries. This can be taken into account by replacing VF in (3.23) with Vapp  IFR: h i I F ¼ I S eqðV app I F RÞ=kT  1 A

ð3:27Þ

The voltage drops cause a departure from the exponential behavior at high currents, as shown in Fig. 3.17.

86

3 PN Junctions

Fig. 3.17 Forward-biased N+P junction, non-negligible IR drop

Forward current, IF (A)

10-02

IR

10-04 10-06 10-08 10-10

60 mV/decade

10-12 10-14

10-16 0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Forward voltage, VF (V)

Example 3.8 The forward current in a PN junction at 25  C is measured as 5 pA for an applied voltage Vapp ¼ 0.2 V. Assume the total series and contact resistances to be 200 Ω and find: (a) The saturation current IS (b) The externally applied forward voltage Vapp at 1 μA (c) The externally applied power supply voltage Vapp at 1 mA Solution (a) At 5 pA, the IR drop is negligible, VF ¼ Vapp, and (3.23) can be used. Also, for a forward voltage VF ¼ 0.2 V, the “1” in (3.23) can be neglected. The saturation current is then found as IS

IF eqV F =kT

¼

5  1012 ¼ 2:078  1015 A 0:2=ð8:62105 298Þ e

(b) At 1 μA, the IR drop is 106  200 ¼ 0.2 mV and will be neglected. The forward voltage at 1 μA is then found as VF ¼

kT I F 106 ln 8:62  105  298  ln 0:514 V IS q 2:078  1015

(c) At 1 mA, the voltage drop is 103  200 ¼ 0.2 V and cannot be neglected. Without the IR drop, the forward voltage would be

3.4 Forward-Biased Junction

VF ¼

87

kT I F 103 ln 8:62  105  298  ln 0:691 V IS q 2:078  1015

But because of the IR drop of 0.2 V, the externally applied voltage, Vapp, must increase to 0.891 V. This can be also found from (3.27).

3.4.2

Effect of Surface Recombination

In a typical junction of the type shown in Fig. 3.12, both the metallurgical junction and depletion regions on both sides of the junction intercept the silicon surface at the junction perimeter. The properties of the surface around the perimeter can strongly affect the junction characteristics. Figure 3.18 illustrates the effect of surface recombination on the forward characteristics of a PN junction. For a small voltage, the surface recombination current is comparable or even larger than the expected forward current. As the forward voltage increases, the recombination current becomes a smaller, negligible fraction of the total current. Surface recombination is discussed in more detail in Chap. 6. It is due to the presence of recombination sites where the junction and depleted region intercept the surface. Since the surface constitutes the termination of the periodic arrangement of silicon atoms and is also exposed to process-induced contamination and damage, it is typically a site of high-density generation-recombination sites, mostly in the form of interface traps that are distributed in energy throughout 10-02

Forward current, IF (A)

Fig. 3.18 Forward-biased N+P junction in the presence of high surface recombination

IR

10-04 10-06

Surface recombination

10-08 10-10 10-12 10-14

10-16 0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Forward voltage, VF (V)

88

3 PN Junctions

the bandgap. Also, the surface is subjected to chemical attack, contamination, and radiation from multiple processing steps, resulting in charged traps and defects. Growing a silicon dioxide (SiO2) layer passivates and protects it from most harmful contaminants. The oxide also reduces the number of dangling bonds by completing the bond with oxygen or silicon of SiO2. Passivation with oxide is, however, not perfect. Interface traps are distributed throughout the bandgap and act as generation– recombination sites. At a high concentration, they can seriously impact the junction forward and reverse characteristics. Interface states can be charged and discharged, causing an increase in surface leakage and noise (Chap. 10) and modifying the field at the junction perimeter. The above effects depend strongly on process conditions and are discussed in more detail in Chap. 6.

3.5

Reverse-Biased Junction

A junction is reverse-biased when a positive voltage is applied to the N-side with respect to the P-side or a negative voltage applied to the P-side with respect to the N-side (Fig. 3.19). Because the reverse voltage has the same polarity as the built-in voltage, the barrier height increases from its thermal equilibrium value Vbi to a steady-state value Vbi + VR. The depletion width xd is found by substituting (Vbi + VR) for Vbi in (3.11a, 3.11b, and 3.11c). Thus, xd increases as additional free carriers are pulled away from the edges of the depletion region. Also, the field increases and the junction capacitance decreases as VR increases. For the N+P or P+N junction, the depletion region widens predominantly in the lightly doped region. The dependence of xd on VR can be approximated as

Ground Surface generation

Reverse voltage, VR

Ammeter

Contact

A

xj xdp at equilibrium xdp in reverse bias Contact

N+ +

Thermal generation within depletion

- +

Thermal generation outside depletion

Ground Fig. 3.19 Reverse-biased N+P junction

Oxide

P

3.5 Reverse-Biased Junction 40

Junction Capacitance (nF/cm2)

Fig. 3.20 Dependence of junction capacitance on applied voltage

89

300K

35

VApplied

30

N+

ND=1020 cm-3

25

P 20

NA=1016 cm-3

15 10 5 -0.5

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Applied Voltage (V)

xd ffi xdp

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi V bi þ V R cm ffi 3:6  10 N 3

ð3:28Þ

where N is the doping concentration in the lightly doped region. The dependence of capacitance on xd is ε0 εSi ffi 2:88  1016 C¼ xd

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi N F=cm2 V bi þ V R

ð3:29Þ

Figure 3.20 shows the dependence of junction capacitance on reverse voltage. The plot also extends into a small forward voltage where the injection of minority carriers is negligible. Example 3.9 Find the ratio of junction capacitance at 0 V, C0V, to the capacitance at 5 V reverse bias, C5V. Neglect edge effects. Assume a temperature of 25  C and uniform ND ¼ 5  1015 cm3 and NA ¼ 1020 cm3. Solution The built-in voltage is found from (3.6b) as V bi ¼ 8:62  105  298  ln

1020  5  1015 0:917 V 2:56  1020

The capacitance at zero applied voltage is calculated from (3.29) as

C 0V

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffi N 5  1015 D 2:88  1016 2:88  1016 ¼ 2:13  108 F=cm2 V bi 0:917

For a reverse voltage of 5 V, the capacitance is

90

3 PN Junctions

C 5V

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 5  1015 8:37  109 F=cm2 2:88  1016 0:917 þ 5

Thus, the ratio C0V/C5V is 21.3/8.37 ffi 2.54. The peak electric field is approximated for an N+P junction as Epeak ¼

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Qpeak qN A xd ffi ffi 5:56  104 N A ðV bi þ V R Þ V=cm ε0 εSi ε0 εSi

ð3:30Þ

Similarly, for a P+N junction Epeak ffi 5:56  104

3.5.1

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi N D ðV bi þ V R Þ V=cm

ð3:31Þ

Reverse Leakage Current

Ideally, no current should be measured when the junction is reverse-biased. As VR is increased, however, a small leakage current is typically measured. When the peak field is less than about 5  104 V/cm, the leakage current consists mainly of thermally generated electron–hole pairs, EHP. There are three main contributors to the thermally generated leakage current: generation within the depletion region and subsequent drift to the neutral regions, generation outside the depletion regions and subsequent diffusion toward the depletion region where they drift to the other side of the junction, and surface generation. (a) Thermal Generation Within the Depletion Region Thermal generation occurs everywhere in the junction. While in the neutral region, generation is balanced by recombination, the electron–hole pairs generated within the depletion region are subjected to a high field and swept to the depletion boundaries at velocity saturation, so the probability for the generated carriers to recombine is near zero. Electrons drift to the N-region and holes to the P-region where both become majority carriers, as illustrated in Fig. 3.21. The excess majority carriers drift to the contacts and recombine there. Each generated pair contributes only one electronic charge to the external circuit. This creates a leakage current that is limited by the rate of EHP generation within the depleted regions. It can be shown that this current can be approximated by [3–5] I gen ¼ 8  1028 N T ni xd A ¼ 8  1028 N T ni xd A A

ð3:32Þ

where A is the junction area, xd the depletion width, and NT the effective density of traps within the depleted region, acting as “stepping stones” and assumed to be

3.5 Reverse-Biased Junction

91

Minority-carrier concentration Depletion boundaries

Contact

Slope @

pn Lp

Contact

Wn

pn

Wp Slope @

pn

np Ln

np

np N-region

P-region xdp

Ln

x

xdn Lp

Fig. 3.21 Reverse-biased PN junction with wide neutral regions (Wn > Lp, Wp > Ln). Minority concentrations reduce to near zero at depletion boundaries, resulting in gradient and diffusion

located in energy halfway between the bound and free energy levels (mid-gap). Traps are typically created by contamination with heavy metal, such as Cu, Fe, Mo, Zn, and Au. The current generated within the depletion region is proportional to ni and thus increases with temperature approximately by a factor of 2 every 10 degrees. Since xd widens as VR increases, Igen also increases. For a one-sided abrupt junction, Igen increases approximately with the square root of (VR + Vbi). (b) Thermal Generation Outside the Depletion Region The current due to the generation outside the depletion region is the saturation current IS in (3.23). As the reverse voltage increases, the exponential term becomes negligible compared to “1” and the reverse current saturates to IS. This leakage component may be best described by examining Figs. 3.21 and 3.22. In Fig. 3.21, the gradients (slopes) are taken at the depletion boundaries to simplify the analysis. The gradients increase as the diffusion lengths Lp and Ln decrease. Since the diffusion length decreases as the minority-carrier lifetime decreases (2.78) and the minority-carrier lifetime decreases as the effective density of recombination centers increases (2.64), the slope and hence the diffusion current should increase as NT increases. The concentration gradients in Fig. 3.21 can be written in the form np n2 ¼ i ; Ln Ln N A

n2 pn ¼ i cm4 Lp Lp N D

ð3:33Þ

The total diffusion leakage current component is thus proportional to n2i and expressed as (2.43)  I diff ¼

qAn2i

Dn Dp þ Ln N A Lp N D

 A

ð3:34Þ

92

3 PN Junctions

Minority-carrier concentration Slope at edge @

np

Slope at edge @

Wn

pn

Contact

pn Wp

Contact

pn

np np N-region

P-region Wp

xdp

xdn

x

Wn

Fig. 3.22 Reverse-biased PN junction with narrow regions (Wn  Lp, Wp  Ln). Concentrations drop linearly from contacts to depletion boundaries

The gradients in a PN junction with narrow regions (Fig. 3.22), which is the typical case in most structures, are simply np n2i ¼ ; W p W pNA

n2i pn ¼ cm4 W n W nND

ð3:35Þ

where Wp and Wn are, respectively, the distances between P-side and N-side contact and boundaries of the depletion region. In this case, the total diffusion current is  I diff ¼ I S ¼

qAn2i

Dn Dp þ W pNA W nND

 A

ð3:36Þ

(c) Surface Generation The region of surface generation is highlighted by the dotted box in Fig. 3.19. The rate of surface generation is dominated by the effective density of interface traps. The surface generation current is approximated as [5] I s ffi 8  1028 ni N it xdl P A

ð3:37Þ

where xdl is the lateral depletion width at the surface, Nit the effective density of states in cm2, and P the junction perimeter. Interface states not only increase the rate of generation of carriers in reverse-biased mode and the rate of recombination of carriers in forward-bias mode, they also modify the field distribution near the surface and hence the junction perimeter characteristics, as will be discussed in Chap. 6.

3.5 Reverse-Biased Junction

93

Example 3.10 Assume the perimeter leakage in a 10  20 μm2 junction to be dominated by surface generation through interface states. Estimate the leakage for a plasmainduced effective density of states Nit ¼ 1011 cm2, a lateral depletion width xdl ¼ 0.1 μm, and a junction temperature of 150  C. Solution From (2.15), ni is found as 1.95  1013 cm3. Substituting the values for ni, Nit, xdl, and P ¼ 60 μm in (3.37) gives IS ffi 94 pA.

Example 3.11 For a reverse voltage VR ¼ 5 V and a junction area of 10  10 μm2, estimate the total generation leakage at 40, 25, and 150  C. The N-region (from contact to metallurgical junction) is 1 μm wide and the P-region 5 μm wide. Neglect perimeter effects and assume NA ¼ 1015 cm3 and ND ¼ 1017 cm3 and a uniform trap density NT ¼ 1012 cm3. Solution Several simplifying assumptions are made in the solution. The minority-carrier lifetime τSRH is found from (2.64), ni from (2.15), Vbi from (3.6b), xd from (3.28), Igen from (3.32), the mobility from (2.37) and (2.38), the diffusivity D from (2.52) and (2.53), the diffusion length L from (2.78) and (2.79), and Idiff from (3.34) and (3.36). Table 3.3 summarizes the results. Since Ln  Wp, Lp  Wn, the regions are treated as “narrow.” The generation leakage is typically dominated by Igen at lower temperatures and by Idiff at higher temperatures. Table 3.3 Junction leakage current at 40, 25, and 150  C Parameter ni xd τSRH Igen Dn Dp Ln Lp dn/dx dp/dx Idiff-n Idiff-p Idiff-total

Unit cm3 cm s A cm2/s cm2/s cm cm cm4 cm4 A A A

40  C 1.37  107 2.75  104 104 3.0  1018 45.0 6.4 0.067 0.025 8.4  102 1.9  101 6.0  1021 2.0  1023 6.02  1021

25  C 1.25  1010 2.72  104 104 2.6  1015 33.4 6.2 0.058 0.025 6.9  108 1.6  107 3.7  1015 1.6  1017 3.72  1015

150  C 1.95  1013 2.66  104 104 4.2  1012 20.5 5.0 0.045 0.022 1.6  1015 3.8  1013 5.3  109 3.1  1011 5.33  109

94

3.5.2

3 PN Junctions

Impact Ionization and Avalanche Breakdown

When the reverse voltage is applied, carriers can gain sufficient kinetic energy from the electric field and generate electron–hole pairs by direct impact with silicon bonds. This is referred to as impact ionization, indicating that the affected silicon atom loses an electron and is thus ionized, which means that a free electron and a hole are created. For low peak fields, however, the probability for impact ionization is very small, and the measured impact ionization current is negligible. As the field increases, the probability for impact ionization increases. Incident carriers traversing the depletion region gain sufficient energy from the field to create secondary electron–hole pairs by impact, increasing the total reverse current. Figure 3.23 illustrates the reverse and forward current–voltage characteristics of a junction. The region of increased reverse current above the thermally generated current is referred to as the multiplication range. When the field increases to a critical point where secondary electrons and holes, in turn, create new EHP by impact ionization, the process is referred to as avalanche breakdown. At this point, the current is only limited by resistances in series with the junction. The avalanche breakdown voltage, BV, depends on the dopant profiles in both sides of the junction. For a one-sided abrupt junction, such as an N+P or P+N junction, BV depends predominantly on the concentration in the lightly doped region. This is because impact ionization not only depends on the electric field intensity but also on the path length of carriers in the high-field region. Since in the heavily doped side of the junction, the depletion width is negligibly small, the

IF (A)

Avalanche breakdown voltage, BV

10-3

10-6 0 -15

VR (V)

-10

-5

1

Leakage

Avalanche

-10-11

Multiplication range -10-08 IR (A)

Fig. 3.23 Forward and reverse characteristics of a PN junction illustrating the multiplication region and avalanche breakdown

-10-05

VF (V)

3.5 Reverse-Biased Junction 104

Breakdown voltage (V)

Fig. 3.24 Avalanche breakdown voltage of a planar N+P or P+N junction as a function of dopant concentration at 300 K [2]

95

Impact ionization 103

300 K

Mixed impact ionization and tunneling

102

101

100 13 10

1014

1015

1016

1017

Concentration in lightly-doped side

1018

(cm-3)

number of secondary carriers generated within that region is also small even though the field is high. Thus, most of the secondary carriers are generated within the wider depletion region in the lightly doped side of the junction. Figure 3.24 shows the breakdown voltage of a planar one-sided abrupt junction as a function of dopant concentration in the lightly doped region at 300 K [2]. (a) Effect of Junction Curvature on Breakdown Typical junctions exhibit curvatures at edges and corners (Fig. 3.11). The curvature causes the electric field to be higher at corners and edges than in the planar junction. As the radius of curvature decreases, the field increases; hence, the breakdown voltage decreases. Figure 3.25 shows the effect of curvature on the breakdown voltage for an N+P or P+N junction as a function of concentration in the lighter doped region. The effect of curvature on the breakdown voltage is sometimes referred to as the “lightning-rod effect.” (b) Effect of Temperature on Breakdown The critical field for avalanche breakdown is shown as a function of doping concentration in Fig. 3.26. An empirical fit to the plot is [6]. Ec ffi aN b V=cm

ð3:38Þ

where a ¼ 4010 and b ¼ 0.125 are curve-fitting parameters. The critical field increases with increasing temperature and doping concentration. This is because, as the temperature or dopant concentration increases, the probability for lattice or ionized impurity scattering increases, and an increasing fraction of the carrier energy is lost due to collisions with lattice atoms or ions. This leaves less energy for impact ionization. The voltage must then be increased to achieve the same impact ionization rate at the lower temperature or lower doping concentration [6]. The normalized

96 1000

rj = ∞

N+P or P+N junction at 300 K Plane Cylindrical Spherical

10 mm

Breakdown voltage, BV (V)

Fig. 3.25 Effect of curvature on breakdown voltage in one-sided abrupt junction [2]

3 PN Junctions

100

1 mm

0.1 mm 10

1 1014

1015

1016

1017

1018

Fig. 3.26 Critical field as a function of N [6]

Critical Electric Field (㽢 㽢 105 V/cm)

Concentration in lighter-doped side (cm-3)

6.0 5.0

Ec ≈ 4010 × N D0.125

4.0 3.0 2.0 1.0 0.0 1013

1014

1015

1016

1017

Doping level (cm-3)

breakdown voltage is shown in Fig. 3.27 for an N+P junction as a function of temperature with acceptor dopant concentration as a parameter [7]. The effect of temperature is more pronounced at lower concentrations in the lightly doped side. (c) Tunneling and Zener Breakdown Tunneling is the penetration of carriers through a barrier rather than crossing over it. From quantum mechanics, it is known that carriers can penetrate into a potential barrier for a short distance. If the barrier in a PN junction is sufficiently thin, there is a finite probability for direct transfer of electrons from the valence band (bound state) in the P-side into the conduction band (free state) in the N-side, whereby a free electron and a hole are created. This occurs when both sides of the junction

3.5 Reverse-Biased Junction

97

Fig. 3.27 Normalized avalanche breakdown voltage versus crystal temperature [7]

2.0

NA = 1014 cm-3

BV(T)/BV(300K)

1.5

1015 1016 1.0

0.5

0 0

100

200

300

400

500

600

T (K)

are doped at high concentration, above about 1018 cm3, where the depletion region is very thin. Tunneling does not require carriers to be accelerated and gain kinetic energy. When a reverse voltage is applied to the junction, the peak field can approach ~106 V/cm, and the probability for electron to tunnel increases rapidly, resulting in a large reverse current. The mechanism is also known as field ionization. The breakdown mechanism due to tunneling is also called Zener breakdown after Zener [8]. Below a concentration of about 1018 cm3, avalanche multiplication is the dominant breakdown mechanism. At higher concentrations, the depletion width and hence the path length traveled by hot carriers become so short that the probability for carriers to gain energy and create electron–hole pairs by impact decreases to the point where avalanche multiplication becomes less dominant. Figure 3.28 compares Zener and avalanche breakdown BV of an N+P or P+N junction as a function of the concentration in the lighter doped side. When BV is above ~8 V, avalanche multiplication dominates. When BV is less than about 4 V, the tunneling mechanism dominates. In the range between 4 and 8 V, both mechanisms can be present [8, 9]. The temperature dependence of Zener breakdown is discussed in Sect. 3.6.

3.5.3

Reverse Recovery Time

In the previous sections, the PN junction was treated under thermal equilibrium or steady-state DC conditions where the voltage and current were assumed to be

98 1000

300 K

Breakdown voltage (V)

Fig. 3.28 Comparison of Zener and avalanche breakdown of a P+N or N+P concentration on the lightly doped side [8, 9]

3 PN Junctions

100

10

1 1015

P

P

N

N

1016 1017 1019 1018 Concentration in the lightly-doped side (cm-3)

constant, independent of time. In many applications, particularly when the junction is used as a switch, the speed at which the junction responds to a pulse is very important. Consider, for example, a square wave pulse applied to a P+N junction shown in Fig. 3.29. During the positive part of the signal, the junction is slightly forward-biased, and the depletion region narrows by Δxd ¼ Δxdp + Δxdn. Holes must be supplied at the P+ contact to neutralize the acceptor ion charge within Δxdp and also to inject holes into the N-region. Assume initially that a steady-state forwardbias condition has been reached during the positive pulse before switching from forward to reverse bias, and a charge of excess holes is stored in the N-region. For Wn  Lp, the excess hole concentration drops off linearly from the depletion boundary to the contact, as shown in Fig. 3.29. The initial stored charge is represented by the shaded area and approximated by Qp ¼ (qΔpnWn)/2. Similarly, electrons are supplied at the N+-contact to neutralize the positive charge within Δxdn and to inject electrons into the P-region. Since the electron injection is very small compared to the hole injection, it will be neglected. For an applied voltage much larger than VF, the signal voltage appears almost totally across R, and the current is IF ffi V/R. When the voltage is reversed, say at time t ¼ 0, the stored charge cannot be swept out instantaneously. There is a delay in the forward to reverse transition which is referred to as the reverse recovery time. Immediately after switching, there is little change in the excess hole concentration, and the junction remains forward-biased for some time although the external voltage is in reverse. Thus, the current reverses to IR ¼ V/R, and the slope of excess holes at the depletion boundary just changes polarity and remains constant for some time. As minority holes are extracted from the N-region to the P-region, or recombine with majority electrons, the stored charge is reduced gradually as shown by the dashed lines in Fig. 3.30. This continues until a steady-state condition is reached corresponding to the reverse saturation current, IS.

3.5 Reverse-Biased Junction

99

P+

N

Input

R

i(t) Forward +

+V

0 Reverse

-

IF

Forward +

IS

0

Time, t

Time, t

Reverse IR

-

-V

(a) v(t)

ts

(b) i(t)

Fig. 3.29 Pulse response of P+N junction. (a) Square wave switching voltage pulse. (b) Current response. ts: storage delay time

Fig. 3.30 Distribution of minority carriers in a P+N junction as a function of time after switching from forward to reverse voltage

Metallurgical junction xd

Wp

Wn

pn Steady-state forward Contact

Dpn

P+

np

Contact

N

Steady-state forward np

Steady-state reverse

pn

Dnp xdp

xdn

Steady-state reverse

x

The time required to remove the stored charge, i.e., the time span during which the junction remains forward-biased after the external voltage is reversed, is called the storage delay time, ts. This delay is important in applications where the diode is used in fast switching circuits. It occurs whenever a junction is switched from forward to reverse bias. The storage delay time is related to the lifetime of minority holes τh. It is approximated as [10, 11]. t s ffi τh ln ½1 þ ðI F =I R Þ s

ð3:39Þ

100

3 PN Junctions

Arrangements as in Fig. 3.29 can be used to extract τh from varying IF to IR ratios in (3.39). Reverse recovery is particularly important in power MOSFETs which conduct high currents through the diodes, particularly during unclamped inductive switching (Chap. 7).

3.6

Applications

The PN junction is a basic building block for most silicon devices. It is also found in several applications, including as a “stand-alone” diode; in circuits for voltage rectification of AC signals; as a switch; in stable voltage reference circuits [12]; for suppression of voltage transients [13]; for gate oxide protection in MOSFETs; as a photodiode; and as a tunable capacitor. This section focuses on Zener diodes, used in voltage reference and voltage transient suppressor circuits, and on PIN diodes used as RF switches and photodetectors.

3.6.1

Zener Diode

Zener diodes are typically used in voltage reference circuits. The term Zener diode is widely used to identify a PN junction that is intended to operate at breakdown, regardless of whether the mechanism is avalanche breakdown or tunneling.4 The operation of a PN junction in breakdown is not always destructive, provided that the current is limited by external means to avoid overheating and permanent damage. (a) Voltage Reference Diode A PN junction used as a voltage reference diode or a voltage regulator should exhibit a reproducible breakdown voltage. For example, a junction which is intended to regulate a maximum voltage of 5.6 V should breakdown and conduct at a reverse voltage of 5.6 V that does not appreciably change with time. Diodes with very high dopant concentrations on both sides of the junction have very narrow depletion regions and develop high fields at low reverse voltage. In earlier designs, the emitter–base junction of a high-performance bipolar NPN transistor, shown separately in Fig. 3.31, provided a convenient Zener reference voltage. It exhibits a breakdown voltage that typically varies between 6 and 8 V, depending on the

4

The term Zener breakdown is used to describe a breakdown mechanism caused by tunneling to distinguish it from avalanche breakdown. This may cause some confusion. The error stems from misinterpreted initial breakdown measurements.

3.6 Applications

101

Contact to emitter

(a)

Contact to base

Oxide

Contact to emitter

(b)

Contact to base

Oxide

+++ N+

P+

Depletion Narrow region of peak field, hot carriers

N+

+++ P+

Positive charge depletes surface, field decreases, breakdown voltage increases.

Fig. 3.31 N+P+ Zener diode. (a) Surface regions of high concentrations; initial depletion region narrow; high field; hot carrier generated under reverse bias. (b) Positive charge trapped, surface depletes, breakdown voltage increases, and breakdown area moves to subsurface

emitter–base junction profile. Since the emitter and base concentrations are high and peak at the surface, the diode is referred to as a “surface Zener diode.” Initially, because the dopant concentrations are highest near the surface, the depletion is narrow and the field is high (Fig. 3.31a). Therefore, breakdown occurs initially near the surface, generating hot carriers that can be directed toward the silicon–oxide interface and create interface and oxide charge in that region. For the junction in Fig. 3.31b, the breakdown voltage is found to increase with time, a phenomenon known as “breakdown voltage walkout” [14–18]. This effect is explained by a positive interface charge trapping model [15, 16, 18] and found to saturate after a short period of time [15]. The breakdown voltage can partially or even fully recover to its original value when the voltage is removed or when the diode is subjected to a high-temperature “bake” of about 300  C. The surface Zener can be used as a voltage reference provided the above instabilities are taken into account. (b) Subsurface (Buried) Zener Diode Instabilities of surface Zener diodes have long been recognized [12]. By moving the breakdown front from the surface to the subsurface, a highly stable voltage reference can be achieved. One approach to form a subsurface Zener diode is schematically shown in Fig. 3.32. The structure uses an additional deep P+-region that is fully compensated by a wider heavily doped N+-region (emitter) near the surface. The region of peak concentrations on both sides of the junction, and hence the breakdown front, is thus moved below the N+-region, away from the surface. The connections are made to the top N+-region and P-region that connect under the surface to the P+-region. A dedicated implanted P+-layer is also incorporated in a BiCMOS technology, using the emitter as the cathode, to form a subsurface Zener diode [19]. It has the advantage of allowing the breakdown voltage to be adjusted from circuit to circuit just by altering the implantation conditions.

102

3 PN Junctions N+ Zener cathode

N+ Zener cathode

P-link to P+

P+ Zener anode P+ Zener anode

Breakdown at N+- P+ interface

A

A

N

P-link to contact

N+ buried layer (b)

(a)

Fig. 3.32 (a) Top view of subsurface Zener diode. (b) Cross-sectional A-A [12]

10-06

Reverse current (A)

-40 oC 25

10-08

oC

85 oC 150 oC

10-10 10-12 10-14 10-16 0

0.5

1.0

1.5 2.0 2.5 3.0 3.5 Applied reverse voltage (V)

4.0

4.5

5.0

Fig. 3.33 Zener diode characteristics for different temperatures. The N+ area is 1  1 μm2, the junction depth 50 nm, ND ¼ 1020 cm3 and NA ¼ 5  1018 cm3

(c) Temperature Dependence of Breakdown Voltage One important characteristic of Zener breakdown is the temperature coefficient of breakdown voltage, BV, which is negative, mainly because the energy gap decreases with temperature (Fig. 3.33). In comparison, the temperature coefficient of the avalanche breakdown voltage is typically positive. Thus, the temperature coefficient is seen to change from negative to positive at the transition from tunneling to avalanche. The temperature coefficient of avalanche breakdown voltage is about 0.07%/ C for diodes with BV in the range of approximately 7–15 V [20]. Figure 3.32

3.6 Applications

103

shows a reverse current–voltage characteristics at four different temperatures for a Zener diode similar to the type shown in Fig. 3.31. The N+ concentration is ND > 1020 cm3 and the P-type concentration, NA ffi 5  1018 cm3. At such concentrations, the predominant breakdown mechanism is tunneling. As the reverse voltage increases, both the electric field and depletion width increase. The field reaches a large enough value for Zener breakdown before the depletion is sufficiently wide for avalanche breakdown to occur. The tunneling current steadily increases as the reverse voltage is increased from zero. The current can hence reach high values before the actual breakdown occurs. Therefore, it is important to always specify the current at which the breakdown voltage is measured. Since the temperature coefficients of Zener and avalanche voltages are typically of opposite polarity, one would expect the region where both mechanisms are present to exhibit a low or even zero temperature coefficient which is the algebraic sum of both coefficients. (d) Transient Voltage Suppressor Diode A diode can be used as a transient voltage suppressor to protect components and circuits from uncontrolled overvoltage during switching. The protective diode is also called a “snubber, flyback, or freewheeling diode.” In Fig. 3.34a, a positive voltage, Vapp, is applied to the inductor, L. After the switch is closed for a time, a steady current, I, which is determined by the voltage and inductor’s internal resistance, RL, passes through the inductor. Opening the switch at this point, as in Fig. 3.34b, causes the current to decreases from I to 0 in a short time. The inductor opposes this change according to Lenz’s law by causing the voltage to increase

(a)

(b) I A

+ -

Switch B

R

L

R

L

A Vapp

Switch

+ -

Vapp

B

(c)

(d)

L

L R

A RB Bipolar transistor or MOSFET can act as a switch

B

+ -

Vapp

A

R

+ -

Vapp

RB PN junction or Zener B can act as a spike suppressor

Fig. 3.34 A simplified switching circuit with an inductive load. (a) Closed switch. (b) Switch opened, voltage spike at point A. (c) PN junction suppressor. (d) Zener diode suppressor

104

3 PN Junctions

sufficiently to maintain the current. This opposing voltage can generate a very highvoltage spike which is limited only by the switch breakdown voltage and parasitic capacitance at the switch node. This spike voltage determines the rate of decrease of current given by L

dI ¼ V spike  V app dt

V

ð3:40Þ

The voltage spike appears at point A in the figure. Since the switch is open, the most likely mechanism for the current to continue is the breakdown of insulation between the switch terminals. The situation is similar to turning off the current to a light fixture. Since the wiring and fixture can be inductive, turning off the current can create a high enough voltage spike across the switch to break down the surrounding air, causing a spark between the switch terminals. The voltage spike in (3.40) is sometimes referred to as the inductive kick. In a circuit, the switch typically consists of a bipolar transistor (Chap. 5) or a MOSFET (Chap. 6). In Fig. 3.34c, an NPN bipolar transistor acts as a switch with its emitter, E, at ground potential and a positive voltage appearing at its collector, C. Initially, the transistor is off and there is no current in the circuit. Thus, Vapp appears at C. A voltage pulse is applied to the base to turn on the transistor, causing the current to ramp-up, controlled by Vapp and L. At the end of the pulse, the transistor is turned off, and a reverse voltage spike is generated by the inductor between the collector C and ground which is also the emitter E of the transistor. The spike can break down and damage the transistor or switching circuit. The voltage spike can be suppressed by placing a diode in parallel to the inductive load, with the N-side of the diode tied to the positive terminal of the power supply [21]. Opening the switch causes the diode to become forward-biased and the decaying inductor current to pass (recirculate) through it, helping to dissipate the energy stored in the inductor (a portion of the energy may also be dissipated by the inductor’s resistance and in its “mechanical load” if it is in a solenoid or motor). Using a diode in forward bias causes a slow decay of the inductor current, which can be undesirable. An alternative approach is to use a Zener diode as a voltage suppressor between the transistor collector and ground, as in Fig. 3.34d. The breakdown voltage of the Zener diode can be tuned to be lower than the breakdown voltage of the switch, thus clamping the voltage at switch node A to the breakdown voltage of the Zener diode and absorbing most of the inductor’s energy.

3.6.2

PIN Diode

A PIN diode consists of a wide, almost intrinsic region sandwiched between a P+region and an N+-region acting as contacts (Fig. 3.35a). In practical structures, the “I” region is not exactly intrinsic but very lightly doped, as in the epitaxially grown N-layer in Fig. 3.35b. Most layers, except for the N-layer, exist already in a

3.6 Applications

105

N+-Cathode

P+-Anode

(a)

t

N

N+-Cathode STI

STI

STI

I

P+-Anode

N-

STI N

(b) N+-Buried Layer

N+-Cathode

P-substrate

Fig. 3.35 (a) Schematic cross section of a PIN diode. (b) PIN diode in an integrated process. The N-layer is almost intrinsic epitaxy

CMOS or BiCMOS technology. When integrating a PIN diode in an existing technology, however, the flexibility in varying the thickness of the “I”-region is limited. The thickness typically varies from 0.5 to 1 μm, depending on the application. The PIN diode can be used under forward-biased or reverse-biased conditions. Under forward bias, it is mainly used as a variable resistor or a high-frequency switch. In reverse bias, it is typically used as a photodetector. (a) Forward-Biased PIN Diode The intrinsic layer has an inherently very high resistivity and exhibits a low capacitance at zero or reverse bias. When forward-biased, electrons are injected from the N+-region and holes from the P+-region into the I-region. The I-region is thus flooded with free carriers, and under steady state, the electron and hole concentrations in the I-region are equal. Since the conductivity is proportional to the total free carrier concentration, the conductivity of the I-region increases, decreasing its resistance. This is referred to as conductivity modulation. The resistance of the I-region is controlled only by the forward bias. Since n ¼ p, the resistivity of the I-region can be expressed as ρ¼

1 1 1 ¼   Ω-cm ¼  qnμn þ qpμp qn μn þ μp qp μn þ μp

ð3:41Þ

For a diode area A, the total charge QT is related to the electron and hole concentrations in the I-region as QT ¼ qnAt ¼ qpAt C where t is the thickness of the I-region. The resistance is then found as

ð3:42Þ

106

3 PN Junctions

R¼

ρt t2 t2 ¼   Ω ¼  A Q T μn þ μp τI F μn þ μp

ð3:43Þ

where τ is the transit time through the I-region and IF the forward current, τ ¼ QT/IF. The forward-biased resistance is thus independent of area. It is the sum of currentindependent small series and contact resistances and a resistance modulated by the forward current. The modulated resistance can be varied in a wide range, typically from 0.1 Ω to 10 kΩ [22]. At a forward current of about 1 mA, a typical PIN diode can have a resistance of about 1 Ω and act as a good RF conductor. The highly concentrated and thin P+ and N+ regions minimize delays due to minority-carrier storage time in those regions. The distance between cathode and anode can be optimized for efficient conductivity modulation and minimum response time, typically in the μs range suitable for RF switching. (b) Reverse-Biased PIN Diode A PN junction operated in reverse bias is typically used as a photodiode. A photodiode converts light signals into electric signals. When the diode is illuminated, photons are absorbed, and electron–hole pairs are generated provided the photon energy hν is larger than the bandgap (h is Planck’s constant and ν the frequency of light). The number of electron–hole pairs generated per impinging photon is called the quantum efficiency. If hν is less than Eg, light will not be absorbed, and if hν > Eg, the energy in excess of Eg is transferred to the crystal in the form of heat. If the light is absorbed within the depletion region, the generated EHP are rapidly swept to the P- and N-regions, creating a current. This current is referred to as photocurrent. Absorption of light in silicon increases as the frequency of light increases, i.e., as the wavelength gets shorter. Absorption is at its maximum at the silicon surface and decreases exponentially with distance from the surface. Therefore, if the wavelength is too short, light will be absorbed near the surface where recombination is high, reducing the photocurrent. When electron–hole pair generation occurs within the neutral regions, the minority carriers must diffuse to the depletion boundaries and be swept to the other side. This is a time-consuming process. If light is absorbed within the depletion region, the generated carriers are swept to the neutral region where they drift as majority carriers to the contacts. Because of the high field in the depletion region, the carriers are swept in a very short time at nearly velocity saturation. For a diode to be an efficient photodiode, most of light absorption should occur within the depletion region. This can be done by increasing the depletion thickness and reducing the width of the electrode through which light penetrates. The PIN diode is most suitable as a photodiode because the intrinsic region can be made wide and very lightly doped. The principle of a PIN structure as photodiode is shown schematically in Fig. 3.36a. A cross section of an integrated PIN diode is shown in Fig. 3.36b [23].

Problems

107 Antireflective Contact coat

Light P+-Anode

e

-

h+

Light

Oxide

P--

t

e

-

h+

P+

N+N+ N+-Cathode (b)

(a)

Fig. 3.36 (a) Principle of a PIN photodiode. (b) Cross section of an integrated PIN diode [23]

The reverse voltage drops almost entirely across the depletion region. The thickness of the intrinsic region should be wide to increase absorption within the depletion region, but not too wide since this would result in an increase in carrier transit time through the depletion region.

Problems 1. In a step junction, ND ¼ 1018 cm3 and NA ¼ 1016 cm3. Find for thermal equilibrium at 25 and 85  C: (a) (b) (c) (d) (e)

The built-in voltage The depletion widths xdp and xdn The total positive charge per cm2 The peak field The planar capacitance per cm2

2. One special case of a nonuniform profile is shown in the figure below. It is characterized by a concentration gradient a where the impurity concentration changes linearly as ND  NA ¼ ax. Assume the depletion approximation, a ¼ 5  1021 cm4, and thermal equilibrium at 25  C. (a) Plot the electrical field as a function of depleted width. (b) Plot the electrostatic potential as a function of depleted width. Hint: Use (3.5). (c) Find the built-in voltage, Vbi. The built-in voltage cannot be extracted analytically. Instead, the following equation can be solved iteratively: V bi ¼

2kT 3ε0 εSi a2 V b ln 3q 2qn3i

(d) Find the total thermal equilibrium depletion width.

108

3 PN Junctions

Fig. P2 Idealized linearly graded approximation

[ND – NA]

ND

Linearly graded approximation

-NA

Metallurgical junction

3. Consider a PN junction with uniform ND on the N-side and NA on the P-side and narrow widths Wn, Wp as shown in Fig. 3.14. The ratio of thermal equilibrium electron concentration np at the boundary of the depletion layer on the P-side to the electron concentration nn at the depletion boundary of the N-side, and the corresponding relation for holes are given by (3.7). (a) Assume that when a forward voltage VF is applied to the junction, the barrier is reduced by VF and the relations for electrons follow Boltzmann’s distribution law as np ¼ nn eqðV bi V F Þ=kT ; Use the results to show that

Δnp ¼ np eqV F =kT  1 ;

pn ¼ pp eqðV bi V F Þ=kT

Δpn ¼ pn eqV F =kT  1

(b) Assume that the injected excess minority-carrier concentration drops linearly from the depletion edge to the contacts and derive (3.25a and 3.25b). 4. A PN junction is made in a 2 Ω-cm resistivity silicon P-type wafer by implanting and diffusing arsenic at the surface such that the N-type region has a concentration of 1020 cm3. The area of the junction is 100  100 μm2. The thickness of the wafer is 750 μm. The trap density in the P-type wafer is NT ¼ 1012 cm3. Ohmic contacts are made to the N-region and bottom of the wafer. At 25  C, determine (a) (b) (c) (d)

The thermal equilibrium built-in voltage The reverse current for a reverse voltage VR ¼ 5 V The forward current for a forward voltage VF ¼ 0.5 V The junction capacitance at a reverse voltage VR ¼ 5 V

Problems

109

(e) The reverse voltage necessary to spread the depletion region 25 μm in the P-region (f) The junction breakdown voltage 5. The concentrations in an abrupt PN junction are NA ¼ ND ¼ 5  1018 cm3. At what reverse voltage will this junction breakdown. Assume that Zener breakdown occurs when the peak field reaches 106 V/cm. 6. Consider the N+P junction in the figure below. The N+-layer is externally shorted to the P+ substrate contact. Impact ionization in an adjacent circuit generates a hole current that passes under the N+-region and is collected at the substrate contact. The resistance between point A in the substrate immediately under the N+-region and the P+-contact is about 4 kΩ. The average trap density in the substrate is 1012 cm3, and the wafer temperature is 25  C.

P+

N+ Isub

4 kΩ

A1 1 Ω-cm P-type substrate

(a) At what substrate current Isub will the N+P junction develop a forward bias of 0.25 V? (b) For a forward bias of 0.25 V, what is the excess electron concentration at the depletion boundary in the substrate? (c) Estimate the diffusion length minority electrons in the substrate. 7. Consider a one-sided N+P step junction having a junction depth of 0.3 μm and a uniform background concentration NA ¼ 1017 cm3. The effective density of generation–recombination sites in the P-region is 1010 cm3. An N+-region is placed 0.8 μm below the silicon surface and reverse-biased at 5 V. (a) Calculate the electron current density for a forward-biased voltage of 0.8 V at 25 and 100  C. (b) Punch-through occurs when the depletion regions of the top and bottom junction merge in the P-region. The reverse voltage is increased until a current of 1 μA/μm2 is measured. Is the main mechanism for this current impact ionization, punch-through, or thermal generation? 8. A one-sided N+P junction is formed by diffusing a heavily doped N-region to a depth of 0.5 μm into a 10 Ω-cm P-substrate of thickness 725 μm. The density of recombination–generation sites in the P-region is 5  1011 cm3. A forwardbiased VF ¼ 0.7 V is applied to the junction at 25  C. Will the minority-carrier electrons reach the backside of the substrate? 9. An abrupt N+P junction is formed by implanting and diffusing arsenic through a 2  2 μm2 mask opening into a P-type substrate. The metallurgical junction is

110

3 PN Junctions

0.25 μm deep, and the substrate is uniformly doped with boron at a concentration of 1017 cm3. Assume cylindrical junction edges and compare the breakdown voltage at the edge to that in the planar part of the junction at 25  C. 10. The intrinsic region in a PIN junction is 1 μm thick. Assume that the N-region and P-region are heavily doped. For a reverse voltage, VR ¼ 5 V and 25  C, calculate (a) The junction capacitance (b) The electric field in the intrinsic region (c) The transit time for an electron–hole pair generated by a photon at the center of the intrinsic region

References 1. R.W. Dutton, Z. Yu, C.A.D. Technology, Computer Simulation of IC Process and Devices (Kluwer Academic Publishers, 1993) 2. S.M. Sze, G. Gibbons, Effect of junction curvature on breakdown voltages in semiconductors. Solid State Electron. 9(9), 831–845 (1966) 3. W. Shockley, W.T. Read, Statistics of recombination of holes and electrons. Phys. Rev. 87(5), 835–842 (1952) 4. R.N. Hall, Electron-hole recombination in Germanium. Phys. Rev. 87(2), 387–387 (1952) 5. A.S. Grove, Physics and Technology of Semiconductor Devices (Wiley, 1967) 6. C.R. Crowell, S.M. Sze, Temperature dependence of avalanche multiplication in semiconductors. Appl. Phys. Lett. 9(6), 242–244 (1966) 7. J. Baliga, Fundamentals of Power Semiconductor Devices (Springer, 2008), p. 100 8. C. Zener, A theory of electrical breakdown voltages of solid dielectrics. Proc. Roy. Soc. London A145, 523–529 (1934) 9. A.E. Garside, P. Harvey, The characteristics of silicon voltage-reference diodes. IET 106(7), 982–990 (1959) 10. P.E. Gray, D. DeWitt, A.R. Boothroyd, J.F. Gibbons, SEEC, in Physical Electronics and Circuit Models of Transistors, vol. 2, (Wiley, 1964) 11. A.B. Phillips, Transistor Engineering (McGraw-Hill, 1962) 12. R.C. Dobkin, Monolithic temperature stabilized voltage reference with 0.5 ppm/ C drift. IEEE ISSCC, 108–109 (1976) 13. B. Reich, J. Erickson, Zener diodes as vehicular and aircraft transient suppressors. IEEE AES 6 (4), 498–502 (1970) 14. R.W. Gurtler, Avalanche drift instability in planar passivated p-n junctions. IEEE Trans. Electron Dev., ED 13(12), 980–986 (1968) 15. W.L. Guo, R.S.S. Huang, L.Z. Zheng, Y.C. Song, Walkout in p-n junctions including charge trapping saturation. IEEE Trans. Electron Dev. 34(8), 1788–1794 (1987) 16. J.F. Verwey, A. Hering, R. De Wendt, W.V.D. Hofstad, Drift of the breakdown voltage in p-n junction in silicon (walkout). Solid State Electron. 20(8), 689–695 (1977) 17. K.C. Saraswat, J.D. Meindl, Breakdown walkout in planar p-n junctions. Solid State Electron. 21(6), 813–819 (1978) 18. J.F. Verwey, Hole currents in thermally grown SiO2. J. Appl. Phys. 43(5), 2273–2277 (1972)

References

111

19. A. Ito, M.D. Church, C.S. Rhee, J.M. Johnson, J.T. Gasner, W.A. Ligon, P.A. Begley, G.A. DeJong, A fully complementary BiCMOS technology for 10 V mixed-signal circuit applications. IEEE Trans Electron Dev. 41(7), 1149–1160 (1994) 20. R.B. Fair, H.W. Wivell, Zener and avalanche breakdown in as-implanted low-voltage Si n-p junctions. IEEE Trans. Electron. Dev., ED 23(5), 512–518 (1976) 21. P.C. Todd, Snubber Circuits: Theory, Design and Applications, Application Note (Unitrode Corp., 1993) 22. W. Doherty, PIN Diode Fundamentals, MicroNotes, Series 701 (Microsemi Corp, Watertown, 2006) 23. M. Kyomasu, Development of an integrated high speed silicon PIN photodiode sensor. IEEE Trans. Electron Dev. 42(6), 1093–1099 (1995)

Chapter 4

Rectifying and Ohmic Contacts

Abstract A contact between metal and silicon can be rectifying or ohmic. The most commonly used rectifying contact is the Schottky barrier diode (SBD). Because of its fast response to signals, the SBD has found several applications in analog circuits where switching speed is important. A contact is said to be ohmic, i.e., non-rectifying, if it exhibits negligible resistance to current in both voltage polarities. Most semiconductor devices are interconnected on the chip and brought to the “outside world” by means of ohmic contacts and metal wires. Understanding the physical nature of contacts and methods to reduce their resistance is becoming increasingly important as contact dimensions are reduced. The first part of this chapter discusses SBD properties, characterization, and applications. The second part describes the formation and characterization of ohmic contacts.

4.1

Introduction

Depending on the materials and processes used, a contact between metal and silicon can be rectifying or ohmic. A rectifying contact is similar to a PN junction inasmuch as it allows a large current in one voltage polarity and a much smaller current in the other. The mechanisms for current transport are, however, different. The most commonly used rectifying contact is the Schottky barrier diode (SBD) [1]. Because of its fast response to signals, the SBD has found several applications in analog circuits where switching speed is important. A contact is said to be ohmic, i.e., non-rectifying, if it exhibits negligible resistance to current in both voltage polarities. Most semiconductor devices are interconnected on the chip and brought to the “outside world” by means of ohmic contacts and metal wires. The first part of this chapter discusses Schottky barrier diode (SBD) properties, characterization, and applications. The second part describes the formation and characterization of ohmic contacts.

© Springer Nature Switzerland AG 2020 B. El-Kareh, L. N. Hutter, Silicon Analog Components, https://doi.org/10.1007/978-3-030-15085-3_4

113

114

4.2

4

Rectifying and Ohmic Contacts

Rectifying Contacts, Schottky Barrier Diode (SBD)

The rectifying contact may be the oldest semiconductor component used in electronics. The rectifying behavior of a metal–semiconductor contact was discovered by K.F. Braun in 1877 while studying current–voltage characteristic of a point contact between a metal wire and a lead sulfide crystal (Fig. 4.1) [2, 3]. A large current was observed when the metal was positive with respect to the semiconductor and very little current when the metal was negative. This was puzzling since the metal has a high density of electrons, and, with the metal negatively biased, electrons are crowded against the interface with the semiconductor. It is now known that a barrier exists between the metal and the semiconductor, and the barrier increases with increasing reverse voltage. Rectifying devices that are based on a barrier formed at a metal–semiconductor junction have been named SBD after Walter Schottky who first developed a model for rectification [1]. The current–voltage characteristics of rectifying contacts are similar to those of PN junctions, but the underlying mechanisms for forward and reverse currents are fundamentally different. In particular, the forward current in an SBD consists mainly of thermionic emission of majority carriers, while in PN junctions, minority-carrier injection is the primary mechanism. Since the response of majority carriers to a varying signal is considerably faster than that of minority carriers, Schottky barrier diodes are advantageous where switching speed is critical. The SBD has also found applications in microwaves, metal–semiconductor field-effect transistors (MESFET), solar cells, and photodetectors. Detailed reviews of metal–semiconductor contacts can be found in [4–7].

4.2.1

Metal–Semiconductor Barriers

Starting with an isolated metal in vacuum, there is a minimum energy required for an electron to escape the surface of the metal, i.e., to be elevated to a free level where it

Current

Braun 1877

Voltage

Fig. 4.1 Current–voltage characteristic of metal wire contact to lead sulfide crystal taken by Braun [3]

4.2 Rectifying Contacts, Schottky Barrier Diode (SBD)

115

Table 4.1 Typical workfunctions of selected metals [8] Metal ϕm (V)

Al 4.2

Au 5.38

Co 5.00

Cr 4.50

Cs 1.80

Cu 4.65

Ni 5.15

Pt 5.60

Ti 4.33

W 4.55

Vacuum level

qc Si

qfm Electron energy

qfSi EC EF Ei

qfFn

EV

Fig. 4.2 Energy band diagram of separated metal and uniformly doped N-type Si

Vacuum level q c Si

qfm

qfBn=q(fm- c Si)

EF

Electron qVbi=q(fm – fSi) Energy

EC EF

xd

EV Metal

N-type Silicon

EC EF EV

qfBp xd

Metal

P-type Silicon

Fig. 4.3 Energy band diagram of an idealized metal to N-type and P-type silicon contact at thermal equilibrium

no longer feels the force of the metal. The free level is referred to as the vacuum level. The electron escape energy is defined as qϕm, where ϕm is a property of the particular metal, called the workfunction.1 The workfunction of a metal or semiconductor is the energy required to bring an electron from the Fermi level to the vacuum level. Workfunctions of selected metals are shown in Table 4.1 [8]. The values, however, depend on metal surface preparation and crystal orientation and should hence be considered only as typical. The main features of a model for a rectifying metal–semiconductor structure are illustrated for N-type silicon in Figs. 4.2 and 4.3 [1]. Figure 4.2 shows a simplified

Unless otherwise stated, E, EF, Ei, EC, EV, Eg represent energies in eV; ϕ, ψ, χ represent potentials in V. Energies and potentials will then have the same numerical values but different units. Example: At 25
C, kT ffi 0.026 eV, kT/q ffi 0.026 V. 1

116

4

Rectifying and Ohmic Contacts

energy band diagram for separate metal and silicon. The minimum energy required to bring an electron from the bottom of the conduction band of the semiconductor to vacuum is called the electron affinity, χ. For silicon, χ Si ffi 4.05 V. The silicon workfunction and Fermi potential are denoted, respectively, as ϕSi and ϕFn. A metal having a lower workfunction means that the Fermi level is at a higher (electron) energy level, and since all metals in Table 4.1 have a workfunction greater than the electron affinity level in Si, the Fermi level of N-type silicon is typically at higher energy than that of the metals in Table 4.1. Because of this workfunction difference, the potential energy of an electron in vacuum next to the metal is larger than the energy of an electron next to silicon (Fig. 4.2). When the metal and silicon are brought in intimate contact and thermal equilibrium is established, the Fermi levels must align as shown in Fig. 4.3. A potential difference (ϕm  ϕSi)/q is established between the metal and the bulk of silicon. Since the metal becomes negative with respect to silicon, a depletion layer of depth xd forms at the silicon surface, and the potential difference drops almost entirely across xd. The electron concentration in the metal is very high so one can neglect the voltage drop and field penetration in the metal. The analysis of the barrier thus created is similar to that of a P+N step junction. In this idealized model, the barrier seen by electrons in the metal is the energy difference between the Fermi level and the bottom of the conduction band at the surface, i.e., the electron affinity. Thus, for N-type silicon, this barrier is ϕBn ¼ ϕm  χ Si V

ð4:1Þ

The barrier seen by an electron at the bottom of the silicon conduction band is the difference between the metal workfunction and silicon bulk workfunction (Fig. 4.2): V bn ¼ ϕm  ϕSi V

ð4:2Þ

Similarly, for P-type silicon, the idealized model predicts ϕBp ¼

Eg  ðϕm  χ Si Þ V q

V bp ¼ ϕSi  ϕm V

ð4:3Þ ð4:4Þ

Example 4.1 For an SBD formed between W and N-type Si of uniform concentration ND ¼ 1016 cm3, estimate the barrier height, the built-in voltage, the depletion width, and the peak electric field in Si at 300 K. Solution The barrier height predicted by the idealized model is ϕBn ¼ ϕm  χ Si V

4.2 Rectifying Contacts, Schottky Barrier Diode (SBD)

117

The tungsten workfunction is given in Table 4.1 as ϕW ffi 4.55 V. Assuming the silicon electron affinity χ Si ffi 4.05 V, this yields an idealized barrier height of ϕBn ¼ 0.50 V. The silicon Fermi potential is ϕFn ¼

kT ND 1016 ln ffi 0:0257 ln ffi 0:346 V q ni 1:4  1010

Assuming an energy gap of 1.12 eV, the silicon workfunction is ϕSi ¼ χ Si þ

Eg  ϕFn ffi 4:264 V 2q

The built-in voltage is then V bi ¼ ϕm  ϕSi ffi 4:55  4:246  0:286 V As for a one-sided abrupt PN junction, the depletion width is sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ε0 εSi V bi 2  8:86  1014  11:7  0:286  0:193 μm ¼ xd ¼ qN D 1:6  1019  1016 The maximum depletion charge density is Qmax-ideal ¼ qNDxdmax, giving a maximum charge density of 3  108 C/cm2 and a peak field of Epeak ¼

Qmax-ideal ffi 3:1  104 V=cm ε0 εSi

(a) Effect of Interfacial Charged States The barriers obtained from (4.1) to (4.4) are typically different from the measured values. For example, according to (4.1), a metal such as aluminum, having a workfunction ϕm ffi 4.25 V and N-type silicon of electron affinity χ Si ffi 4.05 V, would form a barrier of 0.2 V, while typical measured barriers range from 0.5 to 0.8 V, depending on surface conditions. Bardeen [9] explained the observed difference by including the effects of charged interface states in Schottky’s model noting that, as the interface-state density increases, the barrier becomes less dependent on the metal workfunction. Interface states can be created by extrinsic process-dependent surface imperfections [10–13] or by intrinsic metalinduced gap states (MIGS) [14]. Interface states can be of donor or acceptor type. To first order, they are assumed to be continuously distributed in energy within the bandgap and also within the bands. This is shown schematically for bare silicon in Fig. 4.4. Acceptor-type states below EF are occupied by electrons and thus

118

4

Rectifying and Ohmic Contacts EC

N-type

Neutrality level

EC

EC EF Ei

Ei qf0 EF EV

EF = qf0

qf0

Ei EF EV P-type

EV (a) EF coincides with qf0 , (b) EF above qf0, net surface (c) EF below qf0, net surface charge is negative. surface is neutral. charge is positive.

Fig. 4.4 Illustration of Fermi-level positions with respect to neutrality level ϕ0. (a) Neutral surface. (b) Net negative surface charge. (c) Net positive surface charge

Vacuum level Electron energy

qcSi qfm qfB

qVbi

EF

EV

xd Metal

EC EF Ei

Silicon

Fig. 4.5 Metal–silicon contact in the presence of interface states

negatively charged. Donor-type interface states above EF are not occupied by electrons, i.e., they lose their electron and are hence positively charged. Also shown in Fig. 4.4 is the charge neutrality level (CNL), ϕ0. When EF coincides with ϕ0, the net surface charge is zero, i.e., the surface is neutral. If EF is below the ϕ0, the net surface charge is positive, and if EF is above ϕ0, the net surface charge is negative. When the metal is brought into intimate contact with silicon, several modifications to the surface occur. In particular, the initial concentration of interface states changes because of the proximity of metal atoms. As with the ideal case, almost all the potential difference between the metal and the silicon bulk drops within the space charge in silicon as illustrated in Fig. 4.5. For a high interface-state density, a minor displacement of the Fermi level causes a large change in interface charge. The Fermi level tends to be locked into (pinned to) its position within the bandgap, and the barrier becomes less dependent on the choice of metal. It becomes less sensitive to the metal workfunction and more dependent on the density and type of interface states, i.e., on surface preparation and process conditions. Because of the sensitivity of the barrier to surface

4.2 Rectifying Contacts, Schottky Barrier Diode (SBD)

119

preparation and process conditions, the actual barrier height is extracted from measurements rather than from predictions based on (experimentally measured) workfunction values. If the barrier height exceeds half of the energy gap, the resulting band bending indicates that the surface must be inverted. For N-type silicon, the concentration of minority-carrier holes at the surface becomes larger than that of electrons (Fig. 4.5). The concentration of holes remains, however, typically low and has a negligible effect on the barrier. Also, the downward band bending away from the surface represents a barrier limiting hole injection into silicon to a negligible level. Example 4.2 The actual measured barrier height for the Schottky diode in Example 4.1 is 0.70 V. Assume that the difference between measured and idealized barrier height is due to the presence of negatively charged interface states and estimate the effective interface-state density. Solution The difference between measured and idealized barrier height is 0.7–0.5 ¼ 0.2 V. The built-in voltage thus increases from the idealized value of Vbi ¼ 0.286 V to Vbi ¼ 0.486 V. Following the procedure in Example 4.1, the maximum charge density is found to increase to Qmax ¼

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ε0 εSi qN D V bi ffi 4  108 C=cm2

The net interface-state density is approximately N it ¼

4.2.2

Qmax  Qmaxideal 108 ffi ffi 6:25  1010 cm2 q 1:6  1019

Current–Voltage Characteristics

The distributions of thermally excited electrons above the metal surface and above the silicon conduction band edge follow the Boltzmann distribution function discussed in Chap. 2. Without applied voltage, the number of thermally excited electrons having sufficient energy to be emitted over the barrier from silicon into the metal is balanced by an equal number of electrons emitted from the metal into silicon, and the net current is zero (Fig. 4.6). The predominant mechanism for the current from the metal into silicon is thermionic emission [4, 5, 15–18]. It can be described as the “evaporation” of electrons that possess energies larger than the peak of the barrier. The emission current density is

120

4

Rectifying and Ohmic Contacts

Thermal equilibrium Vacuum level Electron energy

qVbi

qf B0 EF Metal

xd

DV

EC EF

Silicon

EV Fig. 4.6 Metal–silicon contact at thermal equilibrium. Currents from metal to silicon and silicon to metal cancel each other

jM!Si ¼ AT 2 eϕB =kT A=cm2

ð4:5Þ

where A is the Richardson constant (A ffi 120 A/cm2K2 for free electrons), T the absolute temperature, ϕB the barrier height, and k the Boltzmann constant. The relation for emission from the silicon conduction band into the metal, jSi ! M, is similar to (4.5). Both currents are proportional to the electron density at the silicon surface, ns. Applying the Boltzmann approximation discussed in Chap. 2, ns can be expressed as ns ffi N C eϕB =kT cm3

ð4:6Þ

where NC is the effective density of states at the conduction band edge. It is shown in [16] that the current density from silicon into the metal, jSi ! M, can be written in the form of (4.5) by replacing the Richardson constant with an effective Richardson constant A* as jSi!M ¼ A T 2 eϕB =kT A=cm2

ð4:7Þ

where A* ffi 112 A/cm2K2 for electrons, ffi 32 A/cm2K2 for holes [15–18]. At thermal equilibrium, jSi ! M and jM!Si cancel each other. (a) Forward-Biased Diode When a forward voltage, VF, is applied to the diode, negative on N-type silicon with respect to the metal, the silicon Fermi level is raised by VF to a new level, referred to as quasi Fermi level E 0F . The electron distribution above the silicon conduction band is elevated with respect to that in the metal. This gives rise to a larger number of electrons with energies higher than the barrier than at thermal equilibrium, increasing the electron current into the metal (Fig. 4.7). The thermionic emission from the metal into silicon remains practically constant, independent of VF.

4.2 Rectifying Contacts, Schottky Barrier Diode (SBD)

121

Forward bias Vacuum level

Electron energy

q(Vbi-VF)

qfB0

VF

EF

xd

Metal

EC

E'F

Silicon EV

Fig. 4.7 Metal–silicon contact in forward bias. Current from silicon to metal increases exponentially with VF; negligible hole injection (not shown)

Conductor plane

(b)

(a)

D qf

Positive image

- Electron

+

qfB0

qfB

x=0

qVbi0 EC

EF Metal

-x

qVbi

Silicon

x

Fig. 4.8 (a) Field distribution between an electron and its positive image in a conductor plane. (b) Schottky barrier lowering Δqϕ at a metal–silicon interface [1]. ϕB0 and Vbi are, respectively, the barrier height and built-in voltage without lowering

The forward voltage VF reduces the barrier seen by electrons at EC from Vbi to Vbi  VF (Fig. 4.8). The total current measured under forward bias is a combination of thermionic emission of majority-carrier electrons from the silicon conduction band into the metal and injection of minority-carrier holes from the metal–silicon interface into silicon. For current densities smaller than about 104 A/cm2, however, the injection of minority holes is negligible. The current is thus dominated by thermionic emission by electrons in the conduction band. At low current levels, when series resistances can be neglected, the current is given as   I F ¼ I S eqV F =nkT  1 A where Is is the saturation current given by [15–18]

ð4:8Þ

122

4

Rectifying and Ohmic Contacts

I S ¼ AjS ¼ AA T 2 eϕB =kT A

ð4:9Þ

In (4.8) and (4.9), A is the junction area, jS the saturation current density, and n is the ideality factor that typically ranges from 1.0 (ideal) to 1.4. For VF > 3kT/q, n is experimentally determined as n¼

q ΔV F kT Δðln I F Þ

ð4:10Þ

The current–voltage relation for an SBD is thus similar to that for a PN junction except for the nature of the saturation current and the ideality factor n. For a non-negligible series resistance, the IR drop outside the diode must be taken into account by modifying (4.8) to   I F ¼ I s eqðV app I F RÞ=nkT  1 A

ð4:11Þ

where Rs is the sum of all extrinsic series and contact resistances along the path of the current between the diode and the power supply and Vapp is the applied power supply voltage. Schottky Barrier Lowering At this point, it may be helpful to describe the Schottky barrier lowering (also referred to as image-force barrier lowering), since it affects the forward and reverse diode characteristics. Consider first an electron in the vicinity of a conducting plane in vacuum. As the electron approaches the plane, the conductor becomes polarized and exerts an attractive force on the electron. An electrostatic field is produced as if there were a positive charge located at the mirror image of the electron in the plane of the metal–vacuum interface as in Fig. 4.8a. This results in a barrier lowering by ΔqϕB (Fig. 4.8b). The field lines between the electron and its positive image in Fig. 4.8a are bent because they must fall perpendicularly on the conductor plane. Since the image charge is positive, it lowers the potential energy of the approaching electron. Schottky first proposed that an approaching electron in the semiconductor induces an image charge of opposite sign in the metal, and the image charge exerts an attractive force that lowers the barrier height seen by the electron near the interface [1]. It can be shown that the Schottky barrier lowering is proportional to the square root of peak electric field at the silicon surface2 [6, 15–19]:

2

The combined potential energy due to depleted charge in silicon and approaching single electron qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi   reaches its maximum (saddle point) at Δx ¼ q= 16πε0 εSi Epeak .

4.2 Rectifying Contacts, Schottky Barrier Diode (SBD)

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffi qEpeak ffi 1:11  104 Epeak V ΔϕB ffi 4πε0 εSi

123

ð4:12Þ

where Epeak is the peak field without barrier lowering. Barrier lowering thus decreases under forward bias, where the peak field decreases, and increases under reverse bias. Since the electric field increases with increased dopant concentration, barrier lowering increases, but the barrier width decreases faster so that for concentration above approximately 8  1017 cm3 tunneling through the barrier rather than emission over the barrier becomes more significant [6]. Minority-Carrier Injection and Charge Storage At low-to-moderate current densities, a Schottky barrier is essentially a majoritycarrier device, earning it the property of high switching speed. There is, however, unavoidable minority-carrier injection from the metal–silicon interface into silicon. Assuming N-type silicon, at an electron current density less than about 50 μA/μm2, the mechanism for minority-carrier transport is mainly diffusion, and the injection ratio, i.e., the ratio of minority-hole current to total current, is small, on the order of 0.05%. The injection ratio becomes significant only under high forward-biased conditions. This is when the field created by the gradient in majority electrons becomes high enough to increase the drift component of holes to a level that is comparable to or even larger than the hole diffusion current [20]. In this case, the minority-carrier storage time can cause an additional delay, particularly when the diode is switched from forward to reverse, similar to the delay observed in PN junctions. To simplify the discussion of minority-carrier injection and storage at high-current densities, it is assumed that the concentration of holes at the surface remains constant, the silicon dimensions are larger than the hole diffusion length, and the N-type silicon is uniformly doped. Also, it is assumed that when a forward voltage is applied, the injected hole concentration remains smaller than the electron concentrations, i.e., the injection level is low. The thermal equilibrium concentrations of holes at the surface, ps, and at the depletion boundary, p, are related by the Boltzmann distribution function: p ¼ ps eV bi =kT or ps ¼ peV bi =kT cm3

ð4:13Þ

As for a PN junction, when a forward voltage VF is applied, the barrier is lowered and the hole concentration at xd increases by an excess:    n2  Δp ¼ p eqV F =kT  1 ¼ i eqV F =kT  1 cm3 ND

ð4:14Þ

The electron current density is dominated by drift and approximately equal to the total current density obtained from (4.8) as

124

4

Rectifying and Ohmic Contacts

  jn ffi j ¼ jS eqV F =nkT  1 ¼ qμn N D E A=cm2

ð4:15Þ

where jS is the saturation current density defined by (4.9) and E the drift field in silicon. The hole current consists of both drift and diffusion and is given by jp ¼ qμp pE  qDp

dp A=cm2 dx

ð4:16Þ

where E is found from (4.15). For small electron current densities, the hole drift component is small and negligible and the hole diffusion current dominates. In this region, the injection ratio is very small, of the order of 104. As the electron current density increases, E increases, enhancing the injection of holes to the point where the hole drift component becomes significant and eventually dominates. This typically occurs at about jn > 50 μA/μm2. Dividing (4.14) by (4.15) gives [20] Δpðxd Þ ¼

n2i j cm3 N D jS

ð4:17Þ

Combining the above relations gives the hole drift current as jpdrift ¼ q

n2i j n2 j j μp E ffi q i μp A=cm2 N D jS N D js qμn N D

ð4:18Þ

The injection ratio is then γ¼

jp n2 j ¼ i2 j bN D jS

ð4:19Þ

where γ is the injection ratio, jp the minority-carrier hole current density, j the total current density (ffi jn), ni the intrinsic concentration, b the ratio of electron to hole mobility, ND the donor concentration in silicon, and jS the saturation current density obtained from (4.9). The injection ratio thus increases linearly with the majoritycarrier current density and is inversely proportional to the square of dopant concentration. Minority-carrier injection in a Schottky barrier results in an increase in charge storage, reducing the switching speed. Under the above assumption of wide diode dimensions compared to the hole diffusion length Lp, the stored charge can be approximated as [20] Q¼

qn2i j Lp C=cm2 N D jS

ð4:20Þ

4.2 Rectifying Contacts, Schottky Barrier Diode (SBD)

125

Extraction of the Barrier Height from Forward Characteristics The barrier height can be extracted from the forward characteristics defined by (4.8)–(4.10). A typical method to extract the barrier height and ideality factor is to plot ln(IF) versus VF. For VF > 3kT/q, where the “1” in (4.8) becomes negligible and an exponential behavior can be assumed, the plot should yield a straight line (Fig. 4.9). The ideality factor is found from the slope of the line and the barrier height from its extrapolated intercept with the vertical axis. To obtain an average value, measurements are typically done at different currents, keeping the current

Log jF (A/cm2)

IR drop

Slope: q/nkT

Intercept: A*T 2 e - qfB /kT

Forward Voltage, VF (V)

Fig. 4.9 Forward I–V characteristic. Ideality factor extracted from slope and barrier height from intercept

Metal Stud

SBD Silicide N+

R2

STI

STI N-well

N-buried layer

BPSG

R1

N+

R2

R3 `R3 P-substrate

Fig. 4.10 Illustration of vertical and lateral series resistances in a silicide Schottky barrier formed in a CMOS process

126

4

Rectifying and Ohmic Contacts

levels sufficiently low so that resistances in series with the diode can be neglected. For high-resistivity silicon, the exponential interval can, however, be narrow [21]. The ideality factor is found from the slope or from (4.10) by taking the ratio of successive current measurements, thus eliminating Is. The saturation current Is is extracted from the intercept. Finally, ϕB is found from the saturation current, using the effective Richardson constant. The series resistance can be approximated from (4.11) or directly from the IR drop shown in Fig. 4.9. The series resistance is typically distributed, consisting of several segments of the structure, including contact, lightly doped N-region, and N-buried layer resistances. This is illustrated in Fig. 4.10 for a silicide Schottky diode on N-type silicon in a CMOS process. The major part of the series resistance is in the lightly doped N-regions, R1 and R2. This N-region can be formed either by using an existing N-layer in the process or by a dedicated layer optimized for specific SBD applications. For a highly doped N-buried layer, R3 can be very small, but for a large space between the SBD and the N-buried layer, R1 can be substantial. The resistances can be reduced by increasing the dopant concentration in the N-region and decreasing the vertical and lateral spaces between the SBD and N+-regions. This comes, however, at the cost of increased reverse current and reduced breakdown voltage as discussed in the following section. Example 4.3 The forward I–V data in Table 4.2 were obtained at room temperature on a 200 μm2 Schottky barrier. Extract the ideality factor, the series resistance, and the barrier height. Assume A* ¼ 112 A/cm2K2 and disregard barrier lowering. Solution A log–linear plot of the I–V data is shown in Fig. 4.11. For VF  3kT/q (about 80 mV), the measured plot departs from the exponential behavior. It also departs from the exponential behavior for VF larger than about 0.20 V where IR drops become appreciable. Thus, the average ideality factor is extracted in the forward voltage range between 0.08 and 0.20 V, using (4.10) and the values in Table 4.2. This gives n ffi 1.04. The average series resistance is found from (4.11) as R¼

IF V app  nkT q ln I S

IF

ffi 92 Ω

where Vapp and IF are measured values at Vapp > 0.25 V to minimize the extraction error. With the extracted value of series resistance, a plot of IF versus (VF ¼ Vapp  IFR) yields a straight line, as shown in Fig. 4.11. The average saturation current density can be obtained from (4.9) as

4.2 Rectifying Contacts, Schottky Barrier Diode (SBD)

127

Table 4.2 Measured Schottky barrier I–V data Vapp 0.000 0.010 0.020 0.030 0.040 0.050 0.060 0.070 0.080 0.090 0.100 0.110 0.120 0.130 0.140 0.150 0.160 0.170 0.180 0.190 0.200 0.210 0.220 0.230 0.240

IF (A) 2.14E09 2.60E09 1.11E08 1.95E08 3.95E08 5.23E08 8.01E08 1.21E07 1.80E07 2.65E07 3.95E07 5.85E07 8.57E07 1.25E06 1.82E06 2.63E06 3.88E06 5.60E06 8.10E06 1.16E05 1.66E05 2.35E05 3.35E05 4.66E05 6.52E05

Vapp (V) 0.250 0.260 0.270 0.280 0.290 0.300 0.310 0.320 0.330 0.340 0.350 0.360 0.370 0.380 0.390 0.400 0.410 0.420 0.430 0.440 0.450 0.460 0.470 0.480 0.490

IF (A) 8.80E05 1.17E04 1.53E04 1.96E04 2.46E04 3.02E04 3.65E04 4.34E04 4.95E04 5.71E04 6.51E04 7.36E04 8.23E04 9.13E04 1.01E03 1.10E03 1.20E03 1.30E03 1.40E03 1.50E03 1.60E03 1.70E03 1.81E03 1.91E03 2.01E03

Vapp (V) 0.500 0.510 0.520 0.530 0.540 0.550 0.560 0.570 0.580 0.590 0.600 0.610 0.620 0.630 0.640 0.650 0.660 0.670 0.680 0.690 0.700 0.710 0.720 0.730 0.740

IF (A) 2.12E03 2.23E03 2.33E03 2.44E03 2.54E03 2.65E03 2.75E03 2.86E03 2.96E03 3.07E03 3.17E03 3.27E03 3.38E03 3.48E03 3.58E03 3.68E03 3.78E03 3.88E03 3.97E03 4.07E03 4.17E03 4.26E03 4.36E03 4.45E03 4.54E03

Vapp (V) 0.750 0.760 0.770 0.780 0.790 0.800 0.810 0.820 0.830 0.840 0.850 0.860 0.870 0.880 0.890 0.900 0.910 0.920 0.930 0.940 0.950 0.960 0.970 0.980 0.990

IF (A) 4.64E03 4.73E03 4.82E03 4.91E03 5.00E03 5.09E03 5.18E03 5.26E03 5.35E03 5.44E03 5.52E03 5.61E03 5.69E03 5.77E03 5.85E03 5.94E03 6.02E03 6.10E03 6.17E03 6.25E03 6.33E03 6.41E03 6.48E03 6.56E03 6.63E03

Fig. 4.11 Plots of measured data from Table 4.2 (curve) and of extrapolated I–V data from (4.11) with R ¼ 92 Ω (straight line)

128

4

jS ¼

IF qV Ae F =nkT



2  10

6

Rectifying and Ohmic Contacts

IF  4:813  103 A=cm2  eV F =ð1:040:0258Þ

The barrier height is extracted from the saturation current density using (4.15) or the intercept of the linear plot at VF ¼ 0 (Fig. 4.13): kT j 4:813  103 ϕB ¼  ln S 2  0:0258 ln  0:554 V q AT 120  3002 An alternative method to extract barrier parameters from forward characteristics is described in [22] for an ideality factor n ¼ 1 and extended in [21] for the typical case where n 6¼ 1. This method is known as the Norde method. It is believed to give more accurate results than obtained from Fig. 4.9, particularly in the presence of high series resistance. Rearranging (4.8) gives V F kT I F  ln ¼ 0 n IS q

ð4:21Þ

where VF ¼ Vapp  RIF. A function is defined as [21] V app kT I F  ð4:22Þ ln m I0 q where m is a parameter that is varied from 0 to larger values within the expected range of n, e.g., from 0 to 2, and I0 is the factor AA*T2 in (4.9). The significance of (4.22) is that when F is plotted versus measured current IF for different m-values, a minimum typically occurs for each plot at a current Im (Fig. 4.12). The minimum occurs when dF/dIF ¼ 0. Differentiating (4.22) gives F ðm; I F Þ ¼

dF 1 dV app kT ¼  ¼0 dI m m dI m qI m

ð4:23Þ

Combining (4.8) and (4.22) gives Im ¼

kT ð m  nÞ Rq

ð4:24Þ

For constant R and n, a plot of Im versus mkT/q should give a straight line as shown in Fig. 4.13. The resistance is extracted from the slope of the line. Once the resistance is known, the ideality factor and barrier height can be extracted using the method described in Example 4.3. Other methods to extract the barrier height and their limitations can be found in [23].

4.2 Rectifying Contacts, Schottky Barrier Diode (SBD)

129

0.64

F (IF)

0.62 m = 1.25

0.60

1.50 1.75 2.00

Im 0.58 0.56 0

4.0×10-5

8.0×10-5

1.2×10-4

IF (A) Fig. 4.12 Typical plot of F (m, IF) versus measured current with m as parameter. Im is the forward current that corresponds to the minimum of each plot

(b) Reverse-Biased Diode The reverse characteristics of a Schottky barrier diode are treated in the same way as for a PN junction. The mechanisms responsible for the reverse current in a Schottky diode are, however, different than those of a PN junction. Applying a reverse bias, VR increases the barrier from Vbi to Vbi + VR, and the energy distribution of electrons in silicon is lowered (Fig. 4.14). For low-to-moderate fields, the reverse current consists of thermionic emission of electrons from the metal into silicon and thermal generation of electron–hole pairs in silicon. For VR larger than about 3kT/q, the exponential in (4.8) can be neglected, and the reverse thermionic current density is jR ¼ js. As for PN junctions, thermal generation within the depletion region and diffusion of generated minority carriers from the bulk toward the depletion region also contribute to the reverse current. Their magnitude is, however, typically negligible compared to js. Since barrier lowering increases with increasing field (increasing VR), the current does not saturate. Instead, jR increases with reverse voltage by ΔjR ¼ jS eΔϕB =kT where ΔϕB is the barrier lowering defined by (4.12). For a uniform dopant concentration in silicon, the depletion width is found similarly to that of an N+P or P+N junction. Assuming uniformly doped N-type silicon, the depletion region is calculated as sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ε0 εSi ðV bi þ V R Þ cm xd ¼ qN D

ð4:25Þ

130

4

Rectifying and Ohmic Contacts

3.0×10-5

I m ( A)

Rs extracted from slope

2.0×10-5

1.0×10-5 3.2×10-2

4.0×10-2

4.8×10-2

5.6×10-2

mkT/q (V)

Fig. 4.13 Plot of Im versus mkT/q. Resistance obtained from slope

Reverse bias Electron energy

Thermal generation

fB q (Vbi+VR)

EF

EC Silicon

Metal

xd

EV

Fig. 4.14 Band diagram for Schottky barrier under reverse bias. Reverse current is mainly thermionic emission. Thermal generation of EHP is negligible compared to thermionic emission

When the field increases above approximately 105 V/cm, impact ionization becomes significant. When the field reaches about 106 V/cm, tunneling begins to dominate. The electric field increases with increasing VR and depends not only on the dopant concentration in silicon but also on the geometry of the structure and properties of the metal–silicon interface. The field is enhanced where the radius of curvature is reduced, such as at silicide contact edges and silicide asperities caused by a nonuniform interface with silicon. The reduced radius of curvature increases the leakage current and reduces the breakdown voltage (Chap. 3). One method to reduce the edgefield is to place a guard ring around the contact as shown in Fig. 4.15 for a silicide-to-silicon Schottky barrier bounded by oxide-filled shallow-trench isolation (STI). The silicide makes an ohmic contact with the P-type

4.2 Rectifying Contacts, Schottky Barrier Diode (SBD)

131

Silicide

N+-contact

SBD STI

N-region

STI

STI N-well

P+ guard-ring n+-buried layer

Fig. 4.15 Silicide Schottky barrier diode with P+ guard ring

± Δ xdn E N ± ΔQ Metal

VR

xd

± 10 mV signal

C

Fig. 4.16 Small-signal capacitance measurement, Δxd exaggerated

guard ring which forms a junction edge with a considerably larger radius of curvature than that of the silicide edge, thus decreasing the field. The purpose of the buried layer in the figure is to reduce the series resistance. Ohmic contacts are discussed in the next section. The field reduction comes, however, at the cost of increased area and capacitance and increased probability for minority-carrier injection and storage under forward-biased conditions. Capacitance–Voltage Profiling and Barrier Height Extraction The SBD is best suited to extract the dopant concentration versus depth (profile) and barrier height from small-signal capacitance–voltage (C-V) measurements. This is because under low-to-moderate reverse-biased conditions, practically all the applied voltage drops in the silicon. The small AC signal is superimposed on the reverse DC voltage, and the capacitance C measured as the reverse voltage is swept from 0 to VR (Fig. 4.16). The junction capacitance thus measured can be treated as a parallel plate capacitor with the metal and N-region acting as the plates and the depletion region as dielectric of constant εSi. For a given reverse voltage VR, the capacitance per unit area is

132

4

Rectifying and Ohmic Contacts

7x1015

1/C2 (cm2/F2)

6x1015

Slope:

5x1015

300 K

2 qε0 εSi N D

4x1015 3x1015

Intercept: Vbi

2x1015

1x1015 0

-1

0

1

2

3

4

5

VR (V) Fig. 4.17 Inverse-square capacitance of uniformly doped SBD. ND is extracted from slope and Vbi from intercept [23, 24]

CSBD ðxd Þ ¼

dQ ε0 εSi F=cm2 ¼ dV xd ðV R Þ

ð4:26Þ

Combining with (4.25) gives sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qN D ðxd Þε0 εSi CSBD ðxd Þ ¼ F=cm2 2ðV R þ V bi Þ

ð4:27Þ

For a uniform N-region, the plot of 1=C2SBD versus VR gives a straight line of slope ¼ 2/(qNDε0εSi). ND can be directly extracted from the slope of the plot and the built-in voltage Vbi from the intercept with the VR axis (Fig. 4.17). For the example shown in the figure, the slope gives ND ffi 1016 cm3, and the intercept with the voltage axis gives Vbi ffi 0.44 V. From Fig. 4.5, the Schottky barrier height is calculated as ϕB ¼ Vbi + ΔV, where ΔV ¼ (EC  EF)/q. For ND ¼ 1016 cm3, ΔV ffi 0.21 V, and the barrier height is ϕB ffi 0.44 + 0.21 ¼ 0.65 V. Typical barrier heights are given in Table 4.3 for selected metal–silicon Schottky barriers and in Table 4.4 for silicide–silicon barriers. The relation between small-signal capacitance and applied reverse voltage can be extended to an arbitrary profile in silicon. Consider, for example, a Schottky barrier with an arbitrary distribution ND(x). A small increment dVR in reverse voltage causes an increase dxd in depletion width and a corresponding increase in electric field:

4.2 Rectifying Contacts, Schottky Barrier Diode (SBD) Table 4.3 Typical metal– silicon Schottky barrier heights

Metal Al Al Au Cr Cr Ni Pt Ti Ti W W

Table 4.4 Typical barrier heights of silicide Schottky diodes

Silicide CoSi2 CoSi2 NiSi NiSi TiSi2 Pd2Si WSi2 MoSi2 PtSi

dE ¼

Si-type N P N N P N N N P N P

Si-type N P N P N N N N N

133 ϕB (V) 0.68–0.70 0.50 0.79 0.69–0.61 0.48–0.50 0.67 0.84 0.50 0.61 0.67 0.45–0.48

ϕB (V) 0.52–0.65 0.35 0.60–0.69 0.36 0.52–0.60 0.71–0.75 0.72 0.68 0.78–0.82

dQ qN ðxÞdxd ¼ D ε0 εSi ε0 εSi

Reference [25, 27] [26] [28] [13, 16] [13, 16] [32] [6, 32] [13, 29] [29, 30] [31] [13, 16]

Reference [36–38] [38] [40, 42] [41] [34, 35] [33] [43] [44] [34, 39]

ð4:28Þ

For small increments   qN D ðxÞd x2d V dV R ffi xd ðV R ÞdE ¼ 2ε0 εSi

ð4:29Þ

Taking the squares on both sides of (4.26) and substituting x2d in (4.29) gives 2 dV R ΔV   ffi 1:21  1031  R cm3 N D ðxÞ ¼  qε0 εSi d 12 Δ C12 C

ð4:30Þ

We dropped the subscript “SBD” and the designation for the dependence of ND on x on the right side of (4.30) for clarity. Equation (4.30) describes the impurity concentration in silicon as a function of distance from the silicon surface. The profile is found experimentally by increasing the reverse voltage in increments ΔVR, measuring the corresponding change in inverse-square capacitance Δ(1/C2), and then applying (4.30) to find ND at each

134

4

Rectifying and Ohmic Contacts

point. The corresponding distance from the metallurgical junction is approximated by (4.26). An analogous treatment can be done for P-type silicon by appropriate changes in polarities.

4.2.3

Schottky Barrier Diode Applications

The advantages of Schottky barrier diodes over PN junction diodes are the very fast switching and lower forward voltage at the same current density. The SBD is widely used in analog circuits, mainly because of its very fast switching, tunable barrier height, small size, and low capacitance. It can be used as a clamp to avoid excessive minority-carrier injection in a PN junction, as a switching diode in RF circuits, or to suppress voltage transients during switching. (a) Schottky Barrier Diode as a Clamp Clamping a PN junction diode with a SBD is a well-known method to suppress minority-carrier injection, avoiding an excessive minority-carrier storage delay. A typical structure is shown schematically in Fig. 4.18 for a clamped-base bipolar NPN structure [45–47]. The bipolar structure is detailed in Chap. 5. Under certain transistor operating conditions, the base–collector junction can be forward-biased. Without clamping the base with an SBD, minority holes are injected from the P-base into the N-collector and minority electrons injected from the collector into the base. The injection of holes into the collector is typically more significant. The performance of circuits operated under this condition becomes limited, mainly by the collector storage time when the junction is switched from forward to reverse. Suppressing minority-carrier injection can be achieved by extending the silicide across the base–collector junction. The silicide makes an ohmic contact (discussed later in this chapter) with the P+-base but forms a Schottky barrier in parallel on the lightly doped N-collector.

Collector

Ohmic contact Emitter Base

Base

Collector

N+

STI

P+

STI N

SBD

P

P+

N

STI SBD

STI N

N-Buried Layer Fig. 4.18 Silicide Schottky barrier diode clamped base–collector junction of an NPN transistor

Fig. 4.19 Comparison of SBD and P+N junction forward voltage at the same current density. The two diodes are formed on the same N-region

Current density, jF (A/cm2)

4.2 Rectifying Contacts, Schottky Barrier Diode (SBD)

103 102 101

100

135

R=92 W , 300 K

CoSi2 to N-Si SBD, f B @ 0.55V

10-1 10-2 10-3 10-4 10-5 10-6 0.0

P+N Junction

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Forward Voltage (VF)

One of the advantages of an SBD over a PN junction diode is its considerably lower forward voltage at the same current density. This is shown in Fig. 4.19 for an SBD formed between cobalt silicide and N-type silicon and having a typical barrier height of 0.55 V. One important design criterion of an SBD clamp is that its saturation current should be at least two orders of magnitude larger than the saturation current of the base–collector PN junction (the ratio in Fig. 4.19 is about 104). This can be accomplished by proper choice of SBD barrier height and area so that as the junctions become forward-biased, almost all the forward current passes through the SBD. The SBD thus clamps the base–collector voltage to a low forward voltage where the minority-carrier injection in the PN junction is negligible. Since the SBD is a majority-carrier device, electrons in this case, there is negligible minority-carrier stored charge in the collector, thus negligible increase in storage time. Due to the difference in the temperature dependence of saturation current, the ratio of PN junction to SBD saturation current densities increases as the temperature is reduced, a factor that should be considered when operating the structure in the typical temperature range of 40 to +150
C. Suppression of minority-carrier injection with an SBD clamp is also shown to reduce the susceptibility of latch-up in CMOS power amplifiers when the drain is forward-biased during normal switching operation3 [48]. (b) Schottky Barrier Diode in RF Mixer A simple RF mixer is shown in Fig. 4.20. In this example, it is designed as a “down converter” to convert radio frequency (RF) signals to intermediate frequency (IF) signals [49]. The conversion is best achieved with an SBD due to its fast response and high cutoff (or corner) frequency, fc. The cutoff frequency is a “figure of merit” defined as

3

Latch-up is discussed in Chap. 11.

136

4

Rectifying and Ohmic Contacts

RF signal IF signal SBD

LO signal

Fig. 4.20 Simplified RF mixer

SBD RF signal

Tag Energy storing capacitor

Fig. 4.21 Simplified energy harvesting circuit with SBD

fc ¼

1 Hz 2πRs C B

ð4:31Þ

where Rs is the SBD series resistance and CB its capacitance. The SBD in Fig. 4.20 is used as a fast switch that turns on and off at the frequency of the local oscillator (LO), which is a continuous sine wave. The LO has an amplitude higher than the SBD forward voltage so that the SBD turns on during the positive half of the sine wave and off during the negative half. The advantage of the SBD over a PN junction is its lower forward voltage at the same current density, its fast switching (fast response and high cutoff frequency), and its smaller size. Several other uses for mixers are up-converters, phase detectors, and key elements for modulation and demodulation in communication systems. (c) Energy Harvesting A simple circuit that describes the concept of using Schottky diodes for harvesting energy from RF signals is shown in Fig. 4.21 [49]. A radio frequency identification (RFID) chip uses RF electromagnetic fields to transfer data identifying tags attached to items. The input circuit in Fig. 4.21 captures the RF signal which is then rectified by an SBD to charge a capacitor, supplying energy to the tag. The low forward voltage and fast response of an SBD make it ideal where an RF signal is used to power logic, detection, modulation, and demodulation in RFID tags. The harvesting SBD supply allows making a link to the tag at greater distances from the RFID chip reader than with PN junction diodes.

4.3 Ohmic Contacts

137

Fig. 4.22 Schematic cross section of CMOS-based SOI MESFET

CoSi2

SBD Gate

Source

STI

Oxide

Drain Oxide

N N+ N+ Buried Oxide (BOX)

STI

Substrate

(d) Schottky Barrier Diode as Source, Drain, and Gate in CMOS Replacing the MOSFET PN junction source and drain with Schottky diodes has the advantage of smaller size, considerably lower resistance, and process simplification. The structure was first demonstrated in 1968 by forming source and drain with platinum silicide which exhibits a barrier height of 0.85 V on N-type silicon and 0.24 V on P-type silicon [50]. A P-channel MOSFET with a TiSi2 Schottky barrier drain is shown to suppress minority-carrier injection and bipolar transistor action, thus improving latch-up immunity when the MOSFET drain is transiently forwardbiased during switching [51]. A CMOS-compatible normally on MESFET with a cobalt silicide Schottky barrier gate is demonstrated on silicon-on-insulator (SOI) [52] (Fig. 4.22). The gate is formed at the same time as source and drain silicidation. The silicide block leaves an oxide that separates gate from source and drain. The main advantage of forming a MESFET instead of a MOSFET is the achievable higher operating voltage with a Schottky barrier gate. High MESFET breakdown voltages can be achieved by increasing the gate to source–drain separation (Fig. 4.22). The high-voltage operation is required in analog/RF applications where inductive loads can lead to voltage transients that are in excess of typical SOI MOSFET breakdown voltages.

4.3

Ohmic Contacts

A contact is ohmic if its current–voltage characteristic is linear and symmetrical with respect to the origin (Fig. 4.23). The contact resistance, however, need not be fully linear. It should only be sufficiently small to allow passage of current in both polarities with a negligible IR drop compared to the operating voltage. The contact resistance depends on the interface between metal and silicon, the regions immediately below and above the interface, the contact size and geometry, and the uniformity of current within the contact area. In addition to the parameters directly associated with the contact, the resistance associated with spreading or crowding of the current from the active device into or out of the contact is another factor that

138

4

Fig. 4.23 Ohmic contacts of different resistances

Rectifying and Ohmic Contacts

I

ΔΙ 1 ΔV1

ΔΙ 2

Δ V2 0

Fig. 4.24 Schematic diagram to illustrate conduction mechanisms for different barrier widths. (a) Wide barrier. (b) Barrier of intermediate width. (c) Thin barrier

V

Thermionic emission f B0 - Δf B

qVbi EC

(a) EF Metal

Silicon

Thermionic emission Tunneling (b) Tunneling (c)

affects the total series resistance. Understanding the physical nature of the contact and methods to reduce its resistance is becoming increasingly important as contact dimensions are reduced. In the absence of a barrier between metal and silicon, the contact would be ohmic. A near-zero barrier is, however, seldom encountered in typical CMOS technologies. Therefore, relying on reducing the barrier height to make ohmic contacts is not realistic. The most practical way to reduce the contact resistance is by increasing the dopant concentration immediately under the contact. For concentrations less than about 8  1017 cm3, the currents in both polarities are dominated by thermionic emission. At such concentrations, the barrier becomes too wide for tunneling to be appreciable and thermionic emission dominates (Fig. 4.24a).

4.3 Ohmic Contacts

139

As the concentration is increased above ~8  1017 cm3, the depletion region narrows so that regions near the top of the barrier become sufficiently thin to allow tunneling (Fig. 4.24b). Therefore, in the concentration range 8  1017 cm3 to about 1019 cm3, the conduction mechanism becomes a mixture of thermionic- and thermally assisted tunneling. At higher concentrations, the barrier becomes so thin that the probability for electron to tunnel through the barrier in both directions becomes very high. The current is then dominated by the tunneling mechanism (Fig. 4.24c). In an ohmic contact, excess carriers recombine immediately, so that we can also define an ohmic contact as a region where the carriers are at their thermal equilibrium values and pn ¼ n2i .

4.3.1

Specific Contact Resistance

The specific contact resistance is an important figure of merit (FOM) for ohmic contacts. It is defined as the derivative of voltage with respect to current density, evaluated at zero bias [16]:  ∂V  Ω-cm2 ρc ¼ ∂J V¼0

ð4:32Þ

When the current is dominated by thermionic emission, the contact is rectifying. If a specific contact resistance would be derived from (4.8) and (4.9), it would be given by ρc ¼

k qϕBeff =kT 7:2  107 qϕBeff =kT e e ffi Ω-cm2 qA T T

ð4:33Þ

Assuming, for example, an effective barrier height ϕBeff ¼ 0.6 eV, this would yield a too high specific contact resistance of about 29 Ω-cm2. It is therefore necessary to increase the dopant concentration to enhance tunneling. It can be shown that, when the dopant concentration is increased to a level where tunneling dominates, ρc can be approximated by [53]   ρc ffi 7:2  107 eqϕBeff =E00 Ω-cm2

ð4:34Þ

where E00 is an energy that is characteristic of the tunneling probability and approximated for N-type silicon by [54]

140

4

Rectifying and Ohmic Contacts

E00 (eV)

100

10-1 kT/q (300 K) 10-2

10-3 1x1017

1x1018

1x1019

1x1020

1x1021

ND (cm-3) Fig. 4.25 Plot of E00 versus dopant concentration. Tunneling becomes important when E00 > kT/q [53–55]

pffiffiffiffiffiffiffi ð4:35Þ E 00  4:72  1012 N D eV The dependence of E00 on dopant concentration is shown in Fig. 4.25 as a function of dopant concentration for T ¼ 300 K. By comparing E00 to kT/q, the different regions in Fig. 4.25 can be distinguished. Thermionic emission dominates at lower concentration where E00 kT/q. For E00 ffi kT/q, there is a mixture of thermionic emission and tunneling, also referred to as thermionic-field emission region. Tunneling begins to dominate when E00 > kT/q, i.e., at concentrations above approximately 3  1019 cm3. The specific contact resistance is approximated from (4.34) and (4.35) and plotted in Fig. 4.26 as a function of inverse square root of ND. The plots should, however, be only considered as a means to understand the trend of ρc versus concentration since the actual values depend on several non-predictable processing factors not reflected in the above relations. There is a mixture of thermionic and field emission (tunneling) in the range 4  1018 cm3–2.5  1019 cm3 where ρc decreases from about 1–0.02 Ω-cm2. There is a sharp decrease in ρc as the concentrations increases above 3  1019 cm3 where tunneling begins to dominate. To achieve a specific contact resistance below 108 Ω-cm2, the concentration must be increased above 1021 cm3. For this purpose, advanced doping and activation techniques may be needed to obtain a concentration above the typical solidsolubility limit. Measured specific contact resistance as a function of dopant concentration is shown in Fig. 4.27 for N-type and P-type silicon for different contacting metals at 300 K [56]. The plots illustrate how ρc decreases with increasing dopant concentration. Detailed information on the different structures in the figures and on measurement conditions can be found in [55]. (a) Extracting the Contact Resistance Figures 4.26 and 4.27 describe the trend of specific contact resistance with dopant concentration. When ρc is known and the current density is uniform across the

4.3 Ohmic Contacts

141 ND (cm-3) 2.5x1019 1.1x1019

1x1021 1x1020

100

6.3x1018

4x1018

rc (Ohm-cm2)

10-1 10-2

300 K

10-3

Metal to N-type Si; f Beff = 0.6 V

10-4 10-5 10-6 10-7 10-8

0

0.1

0.2

0.3

1/ N D

x10

-9

0.4

(cm

–3/2

0.5

)

Fig. 4.26 Dependence of specific contact resistance ρc on dopant concentration showing the tunneling and thermionic–field regions, assuming an effective barrier height ϕBeff ¼ 0.6 V

10-3

10-3

300 K

10-4

ρc (Ohm-cm2)

ρ (Ohm-cm2) c

10-4

300 K

10-5

10-6

10-7

10-5

10-6

10-7

(a) 10-8 1017

(b) 1018

1019 ND

1020

(cm-3)

1021

10-8 1016

1017

1018 1019 1020 NA (cm-3)

1021

Fig. 4.27 Specific contact resistance for N-type and P-type silicon as a function of dopant concentration. (Adapted from [56])

contacted area, the contact resistance is found by merely dividing ρc by the contact area. For example, for ρc ¼ 107 Ω-cm2 and for a contact area 0.25  0.25 μm2, the contact resistance is 160 Ω. In practice, the current density may not be uniform (due to either current crowding, discussed later, or residues and other inhomogeneities within the contact). Also, the contact resistance may not even be precisely known. For a given technology, the contact resistance is best extracted from direct measurements on specifically designed structures.

142

4

Rectifying and Ohmic Contacts

Leading edge

Lc LT

V

Lc LT

Current lines

N+

P Lc

Contact 1

LSi Wc

Contact 2 WSi

Fig. 4.28 Two-contact test structure: The voltage is measured between the contacts through which current is forced. Lc is the contact length and LT the “transfer length” [57–59]

Two-Contact Measurement Consider, for example, the test structures in Fig. 4.28 which consists of two contacts between metal and an N+-layer. For simplicity, the widths and lengths of the structure are assumed to be sufficiently large so that the flow of carriers is essentially laminar between the leading edges of the two contacts, and edge effects can be ignored. In practice, however, a significant border between the contact and the diffusion edge is required to accommodate misalignment during patterning, and the borders between contact and diffusion edge can be different on each side of the contacts. A current is forced between contacts 2 and 1 and the voltage measured with a high-impedance (near-zero current) voltmeter between the same two contacts. In the typical case where the metal sheet resistance is lower than the diffusion sheet resistance, there is current crowding at the leading edge of the contacts since the current will take the path of least resistance. This effectively reduces the currentcarrying contact length from the physical L to an effective electrical length, LT, referred to as the transfer length [57–59]. The effective contact area is thus reduced and the local current density increased due to crowding near the contact edge. A transmission line model is used in estimating the resistance of a rectangular-shaped contact of width Wc and length Lc (Fig. 4.29) [58, 59]. The model is valid for an infinitesimally thin junction of sheet resistance RS and negligible metal resistance. The model predicts that the voltage across the contact drops exponentially from its maximum at the leading edge where the current density is highest. The distance from the edge where the voltage drops to 1/e (37%) of its maximum value is the transfer length LT given by

4.3 Ohmic Contacts

143

Lc R dR = S dx W

dG =

W

rc

dx

x

j0 dG

j0 dR Fig. 4.29 Equivalent transmission line for contact resistance of length Lc and width Wc (Wc normal to paper) [58, 59]

LT ¼

pffiffiffiffiffiffiffiffiffiffiffiffi ρc =RS cm

ð4:36Þ

The result is that the effective area of the contact is reduced from A ¼ Wc  Lc to A0 ¼ Wc  LT. The total resistance measured is essentially the sum of two contacts plus the diffusion resistance: RTotal ¼

V ffi 2Rc þ RSi þ 2Rprobe Ω I

ð4:37aÞ

LSi Ω W Si

ð4:37bÞ

where RSi ffi RS

and RS is the diffusion sheet resistance and Rprobe is the resistance between the probe and metal. The disadvantages of the two-contact structure in Fig. 4.28 are that the diffusion resistance, RSi, and Rprobe must be precisely known to extract the contact resistance from (4.37a). Three-Contact Measurement The three-contact configuration in Fig. 4.30 does not require the prior knowledge of the diffusion sheet resistance. While the current is forced between contact 1 and contact 2, the voltage is sensed between contacts 2 and 3 with a high-impedance voltmeter, i.e., with separate zero current-carrying probes on contacts 2 and 3. The voltmeter thus measures the voltage drop V across the contact between the metal and a region under the contact–silicon interface opposite to the leading edge of contact 2. The contact resistance thus measured is referred to as the “back-end” contact resistance given by Rc ¼ V/I.

144

4 Contact 1 Lc LT

Rectifying and Ohmic Contacts

Contact 2 Lc LT

Contact 3

V

Current lines

N+

P

Fig. 4.30 Contact configuration to directly measure the “back-end” contact resistance: The current is forced between contacts 1 and 2 and the voltage measured between contacts 2 and 3

1

Contact under test

1 2

4 Junction

4

2

Silicided junction

Silicide 3

4

3 Metal

2

4

Metal

Silicide Junction

Contact plug

Current path

Metal

Metal

(a)

2 Silicide

(b)

Current path

Fig. 4.31 Cross-bridge Kelvin test structure. Current forced between, e.g., 1 and 3 and voltage measured between 2 and 4. (a) Main current path between contacts is in the diffusion. (b) Main current path is in silicide

Cross-Bridge Kelvin Test Structure In the cross-bridge Kelvin test structures of Fig. 4.31, the current is forced between, e.g., 1 and 3 and the voltage measured with a high-impedance voltmeter between 2 and 4. The voltage is thus measured perpendicularly to the current. Since the voltage is measured at a right angle to the current, an average of front resistance and back-end resistance is obtained. The contact resistance is measured as Rc ¼ V/I from which the specific contact resistance can be approximated as [56]

4.3 Ohmic Contacts

145

V Contact

Diffusion

Metal

s

W

I Fig. 4.32 Section of contact chain. Current is forced and voltage measured between the ends of the chain

ρc  Rc W c Lc Ω-cm2

ð4:38Þ

The structure shown in Fig. 4.31a is most important because it represents the actual configuration of most contacts on the chip, where the current through the contact under test crosses both the metal–silicide and the silicide–silicon interfaces. The interface between silicide and silicon can present problems caused by segregation of dopants into silicide, reducing the dopant concentration in silicon and increasing the contact resistance. Also, the interface can exhibit nonuniformities in electric field and in current, which can be caused by, e.g., spikes of silicide penetrating into silicon. A structure complementary to that of Fig. 4.31a is designed to separately measure the contact resistance between metal and silicide, as shown in Fig. 4.31b. The contact plug typically consists of a core of tungsten or copper, separated from the silicide by a single or dual film of barrier metal. The interfaces of dissimilar materials can contribute to the overall contact resistance. Furthermore, there is an interface between wiring metal and contact plug that should be considered. Real contacts are more complex than the simple structures used in the above discussion. Contacts are typically not rectangular but rounded after patterning, and they are formed at a distance from the junction boundaries. The junction regions beneath and around the contact have finite dimensions leading to two- and threedimensional effects not considered in the above derivations. Contact Chain A chain of hundreds of contact pairs similar to contacts 1 and 2 in Fig. 4.28 is typically designed for process control. A section of such a contact chain is shown in Fig. 4.32. The total chain resistance is the sum of diffusion and contact resistances. The resistance of an individual diffusion is approximated as RS  (s/W), where RS is the diffusion sheet resistance, and s and W are defined in Fig. 4.32. This test only yields an average contact resistance of

146

4

Rectifying and Ohmic Contacts

 1 sNRS Ω RTotal  Rc ¼ W 2N

ð4:39Þ

where N is the number of diffusion islands. The design and the test conditions of the chain should be such that the junctions are not forward-biased and the reverse voltage does not approach the junction breakdown voltage.

Problems 1. A CoSi2 Schottky barrier diode of effective barrier height ϕB ¼ 0.60 V and area 50  50 μm2 is formed on a uniformly N-type silicon of concentration ND ¼ 2  1016 cm3. Assume thermal equilibrium at 300 K and find (a) (b) (c) (d)

The depletion width in silicon The peak field The diode capacitance The barrier seen by bulk electrons at the bottom of the conduction band

2. The forward characteristic in Fig. P2 was obtained on a SBD of area 2.5  105 cm2 at 300 K. Find the ideality factor, the barrier height, and the series resistance of the diode. 10-02 10-03 10-04

IF (A)

10-05 10-06 10-07 10-08 10-09 10-10 10-11 0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

VF (V) Fig. P2 The ideality factor, the barrier height, and the series resistance of the diode

3. Consider the structure in Fig. P3. The silicide contacting the P-region extends into the N-region to form a SBD of barrier height 0.6 V and ideality factor n ¼ 1.04. A forward-biased voltage of 0.5 V is applied to both the P-region and SBD. The temperature is 300 K, the PN junction area is 10 μm2, the N-region is uniformly doped at ND ¼ 5  1016 cm3, and the injected minority carriers from the P-region immediately recombine when they reach the buried N+-layer.

References

147

(a) Find the SBD area that is necessary to ensure that only 1% of the forward current consists of minority-carrier injection from the P-region. (b) Estimate the leakage current for a reverse voltage of 2.5 V applied to both diodes. Neglect surface effects.

STI STI N+

P+ N

SBD 0.25 mm

STI N+

Buried N+ layer Fig. P3 The silicide contacting the P-region extends into the N-region to form a Schottky barrier diode

4. The room temperature capacitance of a reverse-biased SBD of area 100  100 μm2 is 5.09 pF at VR ¼ 1 V and 2.73 pF at VR ¼ 5 V. Knowing that silicon is N-type and uniformly doped, find the dopant concentration ND and the SBD barrier height ϕB. 5. A contact chain of the type described in Fig. 4.32 is designed on a P-well having a concentration NA ¼ 1017 cm3. The chain contains of 1000 links, each link consisting of one N+-diffusion of width W ¼ 2 μm and two contacts at a space s ¼ 1 μm between contacts. The sheet resistance of the N+-diffusion is 36 Ω/□. To extract the average contact resistance, 1 mA is forced between the chain end terminals and the voltage measured between the terminals. Why would this test give erroneous results? 6. A SBD of area 4  106 cm2 is formed on N-type silicon of concentration ND ¼ 1016 cm3. The barrier height at zero applied voltage is 0.45 V. Assume that barrier lowering follows the relation in (4.13) and estimate the room temperature leakage current at a reverse voltage VR ¼ 5 V.

References 1. W. Schottky, “Halbleitertheorie der Sperrschicht,” Naturwissenschaften, 26, 843, 1938; Z. Phys. 113, 367–414, 1939; 118, 539–592, 1942 2. F. Braun, Ueber die Stromleitung durch Schwefelmetalle. Ann. Phys. J. C. Poggendorff. Phys. Chem. 153, 556–563 (1874) 3. F. Braun, Ueber Abweichungen vom Ohm’schen Gesetz in metallisch leitenden Koerpern. Ann. Phys. G. Wiedemann 1, 95–110 (1877) 4. C. A. Mead, Physics of interfaces, on Ohmic Contacts to Semiconductors, B. Schwartz, Ed. New York, Electrochem. Soc., 1969 5. H.K. Henisch, Rectifying Semiconductor Contacts (Clarendon Press, Oxford, 1957) 6. V.L. Rideout, A review of the theory, technology and applications of metal–semiconductor rectifiers. Thin Solid Films 48(3), 261–291 (1978) 7. M.M. Atalla, Metal-semiconductor Schottky barriers, devices and applications, in Proc. Munich Symp. On Microelectronics, (October 1966), pp. 123–157

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8. CRC Handbook of Physics and Chemistry, 12–124, 2012 9. J. Bardeen, Surface states and rectification at a metal semi-conductor contact. Phys. Rev. 71 (10), 717–727 (1947) 10. W. Shockley, On the surface states associated with a periodic potential. Phys. Rev. 56(4), 317–323 (1939) 11. W.H. Brattain, W. Shockley, Density of surface states on silicon deduced from contact potential measurements. Phys. Rev. 72, 345 (1947) 12. A.M. Cowley, S.M. Sze, Surface sates and barrier height of metal-semiconductor systems. J. Appl. Phys. 36(10), 3212–3220 (1965) 13. K.E. Moselund, J.E. Freiermuth, P. Dainesi, A.M. Ionescu, Experimental study of the process dependence of Mo, Cr, Ti, and W silicon Schottky diodes and contact resistance. IEEE Trans. Electron Dev. 53(4), 712–718 (2006) 14. J. Robertson, L. Lin, Fermi level pinning in Si, Ge and GaAs systems – MIGS or defects? IEEE IEDM Tech. Digest, 119–122 (2009) 15. C.R. Crowell, The Richardson constant for thermionic emission in Schottky barrier diodes. Solid State Electron. 8(4), 395–399 (1965) 16. S.M. Sze, Physics of Semiconductor Devices (Wiley, New York, 1981) 17. E.H. Rhoderick, The physics of Schottky barriers, in Third Solid-State Device Conf., Pp. 1153–1168, Exeter, (1969) 18. A.J. Dekker, Solid State Physics (Prentice-Hall, 1965) 19. V.L. Rideout, C.R. Crowell, Effects of image force and tunneling on current transport in metalsemiconductor (Schottky barrier) contacts. Solid State Electron. 13(7), 993–1009 (1970) 20. D.L. Scharfetter, Minority carrier injection and charge storage in epitaxial Schottky barrier diodes. Solid State Electron. 8(3), 299–211 (1965) 21. C.D. Lien, E.C.T. So, M.A. Nicolet, An improved forward I-V method for non-ideal Schottky diodes with high series resistance. IEEE Trans. Electron Dev. ED-31(10), 1502–1503 (1984) 22. H. Norde, A modified I-V plot for Schottky diodes with high series resistance. J. Appl. Phys. 50 (7), 5052–5053 (1979) 23. D.K. Schroder, Semiconductor Material and Device Characterization (Wiley, 1998) 24. C.A. Mead, Metal-semiconductor surface barriers. Solid State Electron. 9(11), 1023–1033 (1966) 25. A.Y.C. Yu, Characteristics of aluminum-silicon Schottky barrier diodes. IEEE IEDM Tech. Digest, 140–140 (1969) 26. H. Card, Aluminum-silicon Schottky barriers and ohmic contacts in integrated circuits. IEEE Trans. Electron Dev. ED-23(6), 538–544 (1976) 27. D. Dascalu, G. Brezeaunu, P.A. Dan, C. Dima, Modeling electrical behavior of nonuniform Al-Si Schottky diodes. Solid State Electron. 24(10), 897–904 (1981) 28. D. Kahng, Conduction properties of the au-n-type-Si Schottky barrier. Solid State Electron. 6 (3), 281–295 (1963) 29. S.S. Li, J.S. Kim, K.L. Wang, Enhancement of effective barrier height in Ti-silicon Schottky diode using low-energy ion implantation. IEEE Trans. Electron Dev. ED-27(7), 1310–1312 (1980) 30. A.M. Cowley, Titanium-silicon Schottky barrier diodes. Solid State Electron. 13(4), 403–414 (1970) 31. C.R. Crowell, J.C. Sarace, S.M. Sze, Tungsten-semiconductor Schottky barrier diodes. Trans. Metall. Soc. AIME 233, 478–481 (1965) 32. P.E. Schmid, P.S. Ho, T.Y. Tan, Summary abstract: Correlation between Schottky barrier height and phase stoichiometry/structure of silicide–silicon interfaces. J. Vac. Sci. Technol. 20(3), 688–689 (1982) 33. R.J. Purtell, G. Hollinger, G.W. Rubloff, P.S. Ho, Schottky barrier formation. J. Vac. Sci. Technol. A: Vacuum, Surfaces, and Films 1(2), 566–569 (1983) 34. C. Mallardeau, Y. Morand, E. Abonneau, Characterization of TiSi2 ohmic and Schottky contacts formed by rapid thermal annealing technology. J. Electrochem. Soc. 136(1), 238–241 (1989)

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35. E. Barbarini, S. Ferrero, C.F. Pirri, Electrical characterization of self-aligned titanium silicide SBDs formed by furnace annealing. IEEE EDSSC, 1–4 (2010) 36. N. J. Woods and S. Hall, “Self-Aligned Cobalt Disilicide/Silicon Schottky Barrier Diodes,” ESSDERC, 517–520, 1995 37. S. Zhu, R.L. Meirhaeghe, C. Detavernier, F. Cardon, G.P. Ru, X.P. Qu, B.Z. Li, Barrier height inhomogeneities of epitaxial CoSi2 Schottky contacts on n-Si (100) and (111). Solid State Electron. 44(1), 663–671 (2000) 38. S. Sankaran, K. O, Schottky barrier diodes for millimeter wave detection in a foundry CMOS process. IEEE Electron Dev. Lett. 26(7), 492–494 (2005) 39. E. Alptekin, M.C. Ozturk, V. Misra, Tuning of the platinum silicide Schottky barrier height on n-type silicon by sulfur segregation. IEEE Electron Dev. Lett. 38(4), 331–333 (2009) 40. S.M. Woodruff, N.S. Dellas, B.Z. Liu, S.M. Eichfeld, T.S. Mayer, J.M. Redwing, S.E. Mohney, Nickel and nickel silicide Schottky barrier contacts to n-type silicon nanowires. J. Vac. Sci. Technol. B: Micorelectronics and Nanometer Structures 26(4), 1592–1596 (2008) 41. E. Alptekin, M.C. Ozturk, Tuning of the nickel silicide Schottky barrier height on p-type silicon by indium implantation. IEEE Electron Dev. Lett. 30(12), 1372–1374 (2009) 42. M. Morschbach, A. Mueller, C. Schoellhorn, M. Oehme, T. Buck, E. Kasper, Integrated silicon Schottky mixer diodes with cutoff frequencies above 1 THz. IEEE Trans. Microwave Theory and Techniques 55, 2005(6), 2013–2018 43. K. Shenai, Effect of arsenic implantation on electrical characteristics of LPCVD WSi2/n-Si Schottky contacts. IEEE Trans. Electron Dev. 38(9), 2033–2035 (1991) 44. Y. Yamamoto, H. Miyanaga, T. Amazawa, T. Sakai, A MoSi2 Schottky diode for bipolar LSI’s. IEEE Trans. Electron Dev. ED-32(7), 1231–1239 45. R. Aldrich, Low storage Schottky-barrier diode transistor. IEEE IEDM Tech. Digest, 241–241 (1968) 46. J.E. Price, A high-speed integrated Schottky diode transistor logic circuit. IRDM Tech. Digest, 241–242 (1968) 47. E.R. Chenette, R.A. Petersen, R. Edwards, J.J. Kleimack, Integrated Schottky-diode clamp for transistor storage time control. Proc. IEEE 56(2), 232–233 (1968) 48. F.J. Huang, K.K. O, Schottky-clamped NMOS transistors implemented in a conventional 0.8-μ m CMOS process. IEEE Electron Dev. Lett. 19(9), 326–328 (1998) 49. Alan Holden, consultant, private communication June, 2013 50. M.P. Lepselter, S.M. Sze, SB-IGFET: An insulated-gate field-effect transistor using Schottky barrier contacts for source and drain. Proceeding of the IEEE 58(8), 1400–1402 (1968) 51. F.J. Huang, K.K. O, Metal-oxide semiconductor field-effect transistors using Schottky barrier drains. Electronics Lett. 33(15), 1341–1342 (1997) 52. A. Balijepalli, J. Ervin, P. Joshi, J. Yang, C. Yyu, T.J. Thornton, High-voltage CMOS compatible SOI MESFET characterization and spice model extraction, in Microwave Symp. Digest, (2006), pp. 1335–1338 53. A.Y.C. Yu, Electron tunneling and contact resistance of metal-silicon contact barriers. Solid State Electron. 13(2), 239–247 (1970) 54. F.A. Padovani, R. Stratton, Field and thermionic-field emission in Schottky barriers. Solid State Electron. 9(7), 695–707 (1966) 55. D.K. Schroeder, D.L. Meier, Solar cell contact resistance – A review. IEEE Trans. Electron Dev. ED-31(5), 637–647 (1984) 56. D.K. Schroder, Semiconductor Material and Device Characterization (Wiley, New York, 1998) Chapter 3 and references therein 57. D.P. Kennedy, P.C. Murley, A two-dimensional mathematical analysis of the diffused semiconductor resistor. IBM J. Res. Develop. 12, 242–250 (1968) 58. H. Murrmann, D. Widmann, Current crowding on metal contacts to planar devices. IEEE Trans. Electron Dev., ED 16, 1022–1024 (1969) 59. H.H. Berger, Models for contacts to planar devices. Solid State Electron. 15(2), 145–158 (1972)

Chapter 5

Bipolar and Junction Field-Effect Transistors

Abstract Bipolar junction transistors (BJT) are inherent to CMOS technologies. Understanding the basic principles of operation of a BJT and its characteristics is not only important to efficiently use the component in bipolar and BiCMOS applications. It is also important to understand bipolar effects in CMOS, such as the subthreshold behavior, snapback, and latch-up, and to identify process and design techniques to modify their impact on circuit performance. Similarly, a discussion of integrated junction field-effect transistors (JFET) is important to its use in analog designs, mainly as a very low-noise, high input impedance device. It is also important to understand its parasitic effect, referred to as “the JFET effect” in high-voltage, high-power devices. The chapter begins with a review of BJT types, operation, and characteristics that are relevant to analog applications. This is followed by a description of JFET types, basic operation, and characteristics. The chapter concludes with simple circuit applications of both transistors.

5.1

Introduction

Bipolar junction transistors (BJTs) are inherent to CMOS technologies. In applications where transistor speed is not critical, bipolar transistors formed with existing CMOS processing steps, without added complexity, exhibit features that are important to analog designs, such as low-noise, excellent parameter control, low mismatch between transistor pairs, and high output impedance. Junction field-effect transistors (JFET) can also be fabricated in a base CMOS technology with minor added process complexity. JFETs have a targeted use in analog designs, mainly as low-noise, high input- impedance devices used as amplifier input pairs. The JFET symbolizes the extreme measures that analog technologies can take to provide truly optimized components for highly specialized uses. The concepts developed in the preceding chapters are directly applicable to the bipolar junction transistor (BJT) and to the junction field-effect transistor (JFET). A BJT is formed by placing two PN junctions back to back, arranged vertically or laterally. The resulting structure can be described as a P-type layer sandwiched between two N-layers or an N-layer sandwiched between two P-layers (Fig. 5.1). © Springer Nature Switzerland AG 2020 B. El-Kareh, L. N. Hutter, Silicon Analog Components, https://doi.org/10.1007/978-3-030-15085-3_5

151

152

5 Bipolar and Junction Field-Effect Transistors

Depletion regions

Depletion regions N

P

P

N

P

N

N

Wb

P

N

P

N

N

P

P

Wb

C

C

NPN

B E

PNP

B E

Fig. 5.1 Schematic of NPN and PNP bipolar transistors. E emitter, B base, C collector. Wb is the electrical base width

The bipolar structure is a three-terminal device. The substrate on which the transistor is constructed constitutes a fourth terminal which is typically biased at ground and only considered in the analysis when parasitic currents and capacitances come into play. The merged center layer of width Wb is called the base, B, of the transistor. Thus, there are two kinds of bipolar transistors: NPN and PNP. A BJT is typically operated by forward-biasing one junction and reverse-biasing the other. The outer layer of the forward-biased junction is the emitter, E, and the outer layer of the reversed-biased junction is the collector, C. A JFET is also formed by placing two PN junctions back to back arranged vertically or laterally, but biasing the two junctions is different than in the BJT. The merged center layer is called the channel of the JFET. The channel constitutes a resistor that is contacted at both ends as shown in Fig. 5.2. The current through the channel is measured between the two contacts: the source, S, and the drain, D. The current is controlled by applying an appropriate reverse voltage on the top and bottom junctions, typically connected together to form the gate, G. The reverse voltage modulates the depletion width and hence the channel resistance. Since the channel can be P-type or N-type, there are two kinds of junction field-effect transistors: N-channel JFET (NJFET) and P-channel JFET (PJFET). The first part of the chapter begins by considering a simple idealized one-dimensional model of a BJT and then gradually expanding the analysis to real structures and focusing only on their characteristics that are relevant to analog circuits. A similar procedure is followed in the second part of the chapter for the JFET.

5.2 Bipolar Junction Transistor (BJT) Fig. 5.2 NJFET and PJFET formed by placing two PN junctions back to back. The channel resistance is controlled by the gate, G

153

N

P

P-channel

N-channel

N

P G S

G D

NJFET

5.2

S

D PJFET

Bipolar Junction Transistor (BJT)

The basic bipolar transistor action is first described for an idealized NPN structure with uniformly doped emitter, base, and collector. Ohmic contacts are made to the three regions. Real structures are then gradually introduced and their characteristics reviewed. By interchanging N for P and P for N and reversing voltage polarities and current directions, the discussion is equally applicable to a PNP structure. In this sense, NPN and PNP transistors are said to be complementary.

5.2.1

Idealized Structure

To simplify the description of transistor action and the relations between terminal currents, an idealized structure is first described with the following assumptions: (a) The structure has a uniform cross-sectional area, and all variables depend only on the direction normal to the emitter. (b) The dopant concentrations in all regions are uniform and change abruptly from one region to the other. (c) The energy gap is the same in the emitter, base, and collector. (d) The width of the base region is very small compared to the minority-carrier diffusion length, so that recombination of minority carriers in the base is negligible. This means that all injected minority carriers from the emitter into the base reach the collector. (e) The impact of resistances outside the active transistor region is negligible. (f) All minority-carrier holes injected from the base into the emitter reach the emitter contact. (g) The distance between the two metallurgical junctions remains larger than the sum of both depletion regions in the base at the emitter–base and collector–base junctions.

154

5 Bipolar and Junction Field-Effect Transistors

(h) The electric fields are moderate so that impact ionization is negligible. (i) Leakage currents are negligible. (a) Transistor Action When used as an amplifier, the transistor is operated with the emitter–base junction forward-biased and the collector–base junction reverse-biased (Fig. 5.3). This biasing condition is referred to as the forward-active mode in the grounded-emitter configuration [1]. For example, the base–emitter forward bias VBE may be 0.8 V and the collector–emitter reverse bias VCE may be 5 V. The collector–base is then reverse-biased at VCB ¼ 4.2 V. The emitter injects minority electrons into the base, and the base injects minority holes into the emitter. The injected minority carriers diffuse in their respective regions as illustrated in Fig. 5.4. In an optimally designed BJT, the emitter is highly doped, the base is moderately doped, and the collector is lightly doped. Also, the base width, Wb, is considerably smaller than the electron diffusion length in the base, Ln. The high ratio of emitter to base dopant concentrations ensures that the injection ratio of minority electrons into the base to minority holes into the emitter is high. Decreasing the base width Wb reduces the Gummel number in the base, defined as N A W b ffi p
W b (Chap. 3), increasing the injection of electrons into the base and further increasing the electron-to-hole-injection ratio. For Wb  Ln, excess minority electrons, Δnp, diffuse toward the collector with negligible recombination in the base. Δnp can thus be assumed to decay linearly from Δnp0 ffi np0 at the emitter–base depletion boundary in the base to about zero at the collector–base depletion boundary in the base (Fig. 5.4). Thus, the electron current In constitutes the collector current IC which is under the direct control of the base–emitter forward voltage, VBE. A small change in VBE results in a large change in collector current.

Fig. 5.3 NPN transistor operating in the forwardactive mode, groundedemitter configuration. The base–emitter is forwardbiased and the collector– base reverse-biased

Depletion boundaries

IE

E

WE

Wb

N

P

-

N

+ -

C

+

Metallurgical B junction IB VBE

Metallurgical junction VCE

IE = IC + IB

IC

5.2 Bipolar Junction Transistor (BJT) Emitter contact

WE VDsat

Bottom gate

VDsat

VD

(b)

Fig. 5.41 (a) Illustration of NJFET above pinch-off. (b) Output characteristic for VG ¼ 0

For VD > VDsat, the pinch-off point P moves by a distance ΔL toward the source to sustain the voltage between drain and pinch-off point P which remains at a constant potential VDsat (Fig. 5.41a). For long channels, ΔL is negligible compared to the total channel length L. Therefore, the channel resistance and saturation drain current, IDsat, remain approximately constant (Fig. 5.41b). To visualize how carriers are transported from source to drain when VD increases above VDsat, consider the channel consisting of two regions, one between the source and the pinch-off point P and the other between P and the drain. The voltage drops from VDsat at point P to zero at the source and creates a position-dependent lateral field from P to source causing electrons to drift from source to P at a velocity that depends on electron mobility and lateral field. To maintain current continuity as the cross section of the channel decreases, the electron drift velocity must increase from source to P. The field between the drain and P is approximately (VD  VDsat)/ΔL and typically above 104 V/cm so that electrons are transported from the pinch-off point P to the drain at velocity saturation. The saturation current is highest when the applied voltage on the gate, VG, is zero. As VG is made negative, VDsat and IDsat decrease as shown for a long channel in Fig. 5.42. The total drain-to-gate reverse voltage (positive) is the sum (VD + VG + Vbi). Therefore, increasing VG decreases the drain voltage at the onset of pinch-off as

Drain current, ID (μA/μm)

5.3 Junction Field-Effect Transistor (JFET)

10 9

209

ND = 1016 cm-3; L = 5 μm; a = 0.55 μm

VG = 0 V P

8

Transition region

7

- 0.25 V

6

Linear region

5

P - 0.50 V

4

P Saturation region

3 2

- 1.00 V

1 P

0 0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

Drain voltage, VD (V) Fig. 5.42 ID versus VD plots showing the linear, transition, and saturation regions with VG as parameter

V D ¼ V Dsat ¼

qN D a2 N D a2  V bi  V G ffi  V bi  V G V 2ε0 εSi 1:3  107

ð5:68Þ

Using again the definitions in (5.60) and (5.61), the saturation drain current is found as I Dsat ¼ G0

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  VP 2 V G þ V bi A  ðV G þ V bi Þ 1  3 VP 3

ð5:69Þ

The drain current reaches its maximum IDsat(0) when VG ¼ 0, that is I Dsatð0Þ ¼ G0

rffiffiffiffiffiffiffi  VP 2 V bi A  V bi 1  3 3 VP

ð5:70Þ

A good approximation for IDsat as a function of VG is found as I Dsat  I Dsatð0Þ

VG 1 V P  V bi

2 A

ð5:71Þ

Figure 5.43 compares the IDsat versus VG plots obtained from the approximation in (5.71) to that obtained from (5.69). Saturation Conductance and Transconductance Ideally, the saturation current should be independent of VD and conductance should be zero (infinite output resistance ro). This is approximately the case when ΔL in Fig. 5.41 is negligible compared to the channel length. For short channels, ΔL can

210

5 Bipolar and Junction Field-Effect Transistors

Drain current, IDsat (A/μm)

10-4 IDsat(0) ND = 2x1016 cm-3; a = 0.4 m; L = 4 μm; T = 300 K

10-5

10-6

10-7

10-8 0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

Gate voltage, VG (V) Fig. 5.43 IDsat versus VG. Solid line obtained from (5.69); dashed line approximation (5.71) 16

Short channel modulation

14

ID ( μA/μm)

12

VG = 0

Long channel

10

-0.25

8 6

-0.50 4 2

-1.00

0

VA = -1/λ

0

2

4

6

8

10

12

VD (V) Fig. 5.44 Illustration of channel-length modulation in a short-channel JFETs. VA is the Early voltage

no longer be neglected, and the effective channel length (from source to pinch-off point) decreases appreciably as VD increases. This is referred to as channel-length modulation. Thus, the channel resistance and hence the drain current become a function of VD (Fig. 5.44). The JFET output conductance, gd, and resistance ro are defined as gd ¼ ∂I D =∂V D S

ð5:72aÞ

ro ¼ 1=gd Ω

ð5:72bÞ

The saturation drain current can also be modeled by simply adding a modulating factor λVD to (5.72a) and (5.72b) as

5.3 Junction Field-Effect Transistor (JFET)

I Dsat  I Dsatð0Þ 1 

211

VG V P  V bi

2 ð1 þ λV D Þ A

ð5:73Þ

When VD ¼ 1/λ, IDsat ¼ 0. The value of VD at this point is the Early voltage VA (Fig. 5.44). The saturation transconductance is found from (5.69) as gmsat

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  ∂I D V bi þ V G S ¼ ¼ G0 1  ∂V G VP

ð5:74Þ

This is identical to the linear drain conductance in (5.63). A good approximation is obtained from (5.71) as gmsat ¼

2I Dsatð0Þ ½1  V G =ðV P þ V bi Þ S V P  V bi

ð5:75Þ

The maximum transconductance is gmmax ¼

5.3.2

2I Dsatð0Þ S V P  V bi

ð5:76Þ

JFET in a CMOS Technology

The discussion in the previous section assumes that the JFET gate, channel, and source–drain are uniformly doped, the junctions abrupt, and the structure symmetrical with respect to its center axes. These idealized conditions are not typically found in integrated JFETs. (a) Structure and Profiles Figure 5.45a shows a cross section of an NJFET constructed in a CMOS technology. The approximate doping profiles along a line normal to the center of the top gate are shown in Fig. 5.45b. The NJFET is formed using existing processing steps in a CMOS technology and adding only one masking and implantation step to optimize the channel and the bottom gate. The top and bottom gates are connected by layout. Isolation is required to allow biasing the bottom gate independently of the substrate. A PJFET can be formed in a similar way by switching the dopant polarities from N to P and P to N and omitting the isolating junction. As can be seen in Fig. 5.45a, the source and drain are not symmetrically designed. In typical applications, the source and drain are not interchanged. Since the gate-tosource reverse voltage does not substantially exceed the JFET turn-off voltage, the source can be designed closer to the gate than the drain. This allows reducing the channel resistance and also optimizing the turn-off voltage.

212

5 Bipolar and Junction Field-Effect Transistors

(a)

Link to bottom gate Isolation

Link to bottom gate

Silicide block

Source

N+

P+

N+

STI

STI

P

D Drain

Top Gate

P+

N+

P

P N-channel P - Bottom Gate

N-well P-well PW

BG

Isolation

P+

N+

P

STI

STI

P-well N-well

NBL

P-- substrate

(b)

1020

P+-top gate

Concentration (cm-3)

1019

: Approximate depletion boundaries

1018

1017

Channel 2a

P-bottom gate

N-isolation

1016

1015 1.0

2.0

Depth in silicon (μm) Fig. 5.45 (a) Schematic cross section of NJFET constructed in a CMOS technology. (b) Approximate one-dimensional doping profiles in an NJFET along a line normal to the center of the top gate

The profiles in Fig. 5.45b show highly asymmetrical top and bottom gate and nonuniform concentrations in all regions. Because of the lower concentrations at the P-type bottom gate, the depletion region expands less into the channel than under the P+-top gate.

5.3 Junction Field-Effect Transistor (JFET)

213

In addition, the width and length of the JFET are different from the drawn dimensions. They cannot be easily determined from the layout and impurity profiles. Instead, they are extracted empirically from measurements on JFETs of different drawn width and length. The analytical relationships developed for an idealized structure in the preceding section can still be used for a quick estimate of JFET characteristics by assuming average uniform concentrations in the gate and channel regions and applying stepjunction approximations. More accurate predictions would, however, necessitate numerical techniques such as computer-aided simulations. (b) Gate Leakage Sources Gate leakage currents reduce the JFET input impedance and contribute to noise. In a JFET of the type shown in Fig. 5.45, the main contributors to gate leakage at low electric fields are PN junction leakage components discussed in Chap. 3. As the drain-to-gate voltage increases, however, the probability for impact ionization and hence multiplication increases. In this range, the gate current increases almost exponentially with drain voltage, as shown in Fig. 5.46. The current that is multiplied at the drain is mainly the drain current ID. Since electrons and holes are generated in pairs, the drain current must increase at the same rate as the gate current. Initially, the increase in drain current is very small compared to ID. As avalanche multiplication is approached, the gate and drain currents become comparable. Impact ionization sets the limit for the maximum drain-to-gate voltage that can be applied. In typical applications, the maximum impact ionization current is specified at approximately 10 nA/μm.

5.3.3

JFET Applications

Under normal operating conditions, JFETs offer very low gate leakage current, in the low pA range compared to base input currents in the μA range in bipolar transistors. 10-05

Avalanche breakdown L1 < L 2 < L3 < L4

VG = VS = 0

14 12

10-06 10-07

ID

10

10-08

L1

10-09

8 L2

6

10-10

IG

10-11

4 L3

2

10-12

L4

0 0

2

10-13 4

6

8

10

Drain voltage, VD (V)

12

14

Gate current, IG (A/μm)

16

Drain current, ID ( μA/μm)

Fig. 5.46 Drain and gate currents per unit channel width versus drain voltage characteristics for four JFET channel lengths L

214

5 Bipolar and Junction Field-Effect Transistors

JFETs also offer considerably lower flicker noise than MOSFETs (Chap. 10). Input current and noise are important for sensing small signals. JFETs are hence typically used as input devices in applications that require low noise and low input bias currents. An example of this is an instrumentation amplifier, which is a type of amplifier that can measure differential signals while rejecting signals that are common to both inputs (i.e., common-mode signals). Hence, a JFET is ideally suited to detect, and amplify, small differential signals embedded in common-mode voltages and background noise. An instrumentation amplifier typically has op-amps connected at each input (the positive and negative inputs) that act as buffers and gain for the input signals. JFETs are often preferred as the input devices of these op-amps when interfacing to high source impedance sensors, whereas, by contrast, bipolar transistors might be more typical in cases where the source impedance of the sensors is low. While MOSFETs also have low input bias, the low-frequency 1/f noise performance of JFETs is often superior (Chap. 11), making them the preferred choice for high-performance uses. A common use of a JFET instrumentation amplifier is as a high-impedance bridge transducer amplifier shown in Fig. 5.46, used in certain weigh scale and pressure measurement applications. In this example, the output (Vo) of the balanced bridge is 0 V since both taps are at 5 V. However, with pressure or weight applied, the internal bridge resistances shift slightly, changing the tap voltages, perhaps by millivolts, around their common point of 5 V. The instrumentation amplifier rejects the 5 V common mode and amplifies only the differential signal, enabling it to be accurately converted to a pressure or weight (Fig. 5.47). Other applications of a JFET include the transimpedance amplifier described in Chap. 1, instrumentation for noise measurement, low-noise amplifiers (LNA), high input impedance amplifiers, voltage-controlled resistors (VCR), and voltagecontrolled oscillators (VCO). An available normally-on JFET can be used in “start-up” circuits where the goal is to allow a small current to “trickle” to accomplish start-up. In this application, the JFET remains typically conducting and acts as a high-resistance path to ensure startup when the system is powered up.

Fig. 5.47 JFET instrumentation amplifier used as a bridge transducer amplifier

+10V

Bridge

Vo

RG

+ Ref

Problems

215

Problems The temperature is 300 K unless otherwise stated. 1. In an NPN transistor operated in the forward-active mode, the base current is 10 nA and the emitter current 0.61 μA. (a) Neglect leakage current and find α and β. (b) The transistor is subjected to an accelerated aging stress, and β is found to drop to 29.5 at the same emitter current. Assume that β degradation is solely due increased emitter–base leakage after stress and calculate the leakage. 2. An NPN transistor has a uniform total emitter area of 50 μm2. A forward voltage VBE ¼ 0.7 V is applied to the base–emitter junction and a reverse voltage VCE ¼ 5 V to the collector–base junction. The base and emitter currents are measured at, respectively, 1 and 61 μA. Assume low-level injection and determine: (a) (b) (c) (d)

The injection ratio The emitter current density The saturation current of the emitter–base junction The collector current for a forward bias VBE ¼ 0.75 V

3. Show that the condition α1 + α2 > 1 is equivalent to β1 β2 > 1. 4. The uniform doping concentrations in the emitter, base, and collector of an NPN transistor are, respectively, ND ¼ 1020, NA ¼ 2  1017, and ND ¼ 8  1016 cm3. The metallurgical base width is 0.8 μm and the emitter area is 10 μm2. The base– emitter junction is forward-biased at VBE ¼ 0.6 V and the collector–base junction reversed-biased at 5 V. (a) Find the electrical base width Wb. (b) The minority electron concentration at the depletion boundary of the emitter–base junction. (c) The total charge of minority-carrier electrons in the base. 5. The externally applied collector voltage in a grounded-emitter NPN is fixed at 1.5 V and the base–emitter junction gradually forward-biased. At VBE ¼ 0.6 V, the collector current is 100 nA. For a total collector resistance of 1 kΩ, find VBE at the onset of saturation. Assume low-level injection and neglect emitter and base resistances. 5.0 V

+ -

0.2 kΩ 0.7 V

+ I

10 mA

216

5 Bipolar and Junction Field-Effect Transistors

6. Consider the NPN transistor in the following circuit. Neglect leakage currents. (a) Find the collector and base currents for α ¼ 0.95. (b) Calculate the reverse voltage seen at the collector–base junction. 7. The base and collector of an NPN transistor are uniformly doped at a concentration NA ¼ ND ¼ 2.5  1017 cm3, and the emitter is degenerately doped. The distance between collector–base and emitter–base metallurgical junctions is 0.2 μm. The emitter is shorted to the base and the reverse collector voltage gradually increased. Will punch-through or avalanche breakdown occur first? 8. Show that for a transistor in the forward-active mode, β is approximately proportional to the intrinsic base sheet resistance. 9. A transistor is fabricated with an exponential base profile having a concentration of 5  1018 cm3 at the emitter–base depletion boundary and 1017 cm3 at the collector–base depletion boundary in the base. The base width Wb is 0.1 μm. For VCE ¼ 1 V, VBE ¼ 0.7 V calculate: (a) (b) (c) (d)

The base sheet resistance The built-in field in the base The minority-carrier drift velocity in the base The base transit time

10. In a PNP transistor, the collector current is kept constant, while the temperature is increased. IB decreases in magnitude, passes through zero, and changes polarity. What physical effects account for this behavior? 11. Assume that an external resistor is placed in either the base lead or the emitter lead in a bipolar transistor of the type shown in Fig. 5.7. Which placement has the largest effect on the collector current IC? 12. The emitter and base regions of an NPN transistor are uniformly doped with ND ¼ 1018 cm3 and NA ¼ 1017 cm3. (a) What are the thermal equilibrium minority and majority concentrations in the neutral regions? (b) Find the built-in voltage and depletion-layer width. (c) A forward voltage VBE ¼ 0.6 V is applied to the junction. Neglect series resistances and find the excess electron and hole concentrations at the depletion edges of the emitter–base junction. (d) What are the percentile increases in the minority- and majority-carrier concentrations at those boundaries? (e) Repeat (c) and (d) for a forward voltage VBE ¼ 0.82 V. 13. Consider two N+P junctions formed at a distance 0.1 μm apart on a P-type substrate having a uniform concentration NA ¼ 1015 cm3. The electron lifetime in the P-type substrate is 10 μs. (a) Find the electron diffusion length in the substrate. (b) Do you expect this structure to exhibit bipolar action?

Problems

217

(c) One of the junctions is forward-biased at VF ¼ 0.6 V and the other reversebiased at VR ¼ 10 V. (i) Estimate the electron current density in the substrate. (ii) Calculate the excess electron current density in the substrate at the depletion edge of the forward-biased junction. (iii) Is the forward-biased junction in the high-level injection mode? Explain. 14. In a PNP transistor, the emitter current is IE ¼ 10 mA at VBE ¼ 0.7 V. (a) Neglect series resistances and calculate the saturation current at 25 C. (b) Calculate the absolute change and percentile changes in VF as IE is varied by 75% from its initial value at 0.7 V. (c) Find the saturation current at 85 C. 15. The base width in an NPN transistor is 1.0 μm and the doping concentrations in the emitter, base, and collector are, respectively, ND ¼ 1020, NA ¼ 1  1016, and ND ¼ 1017 cm3. The emitter and base are shorted and the collector reverse-bias voltage increased. Will punch-through or avalanche breakdown occur first? 16. In an NPN transistor operated in the forward-active mode, the emitter–base capacitance is CjE ffi 2 fF, and the base width is Wb ¼ 0.5 μm. The concentration in the base is 6  1017 cm3. Assume that the unity-gain frequency fT is limited only by the emitter delay and base transit time, and estimate fT at IE ¼ 1 μA and IE ¼ 1 mA. 17. Self-heating is the increase in transistor temperature during operation as a result of insufficient dissipation of power generated by the transistor. A transistor operates in the forward-active mode, and its temperature rises gradually as the collector voltage is increased. (a) For a constant VBE, how does the increase in temperature affect IC and IB? (b) How would VBE be affected if IB is kept constant as the temperature increases? 18. The emitter–base junction xjE and collector–base junction xjC of an NPN transistor are, respectively, 0.45 and 0.71 μm deep. The emitter, base, and collector are uniformly doped with, respectively, ND ¼ 1020 cm3, NA ¼ 1017 cm3, and ND ¼ 1017 cm3. The base current density at VBE ¼ 0.6 V is 3.23  103 A/cm2. (a) Estimate the NPN gain β at VCE ¼ 1 V. (b) What is the maximum VCE that can be applied? What mechanism(s) limit this value? (c) Where would such a transistor be used? 19. In a double-gated PJFET, the channel and gate concentrations are NA ¼ 1016 cm3 and ND ¼ 1020 cm3. Calculate the distance between the

218

5 Bipolar and Junction Field-Effect Transistors

gate metallurgical junctions that will give a turn-off gate-to-source voltage VG ¼ 1.4 V. 20. In a double-gated NJFET, the channel and gate concentrations are ND ¼ 1016 cm3 and NA ¼ 1020 cm3. The channel depth is 2a ¼ 0.4 μm. Is the transistor on or off at VG ¼ 0? 21. An NJFET is constructed on a P-substrate which acts as a back gate and is held at ground. The doping concentrations in the channel, top gate, and substrate are, respectively, ND ¼ 2.5  1016 cm3, NA ¼ 1020 cm3, and NA ¼ 1016 cm3. The channel dimensions are a ¼ 0.3 μm, W ¼ 20 μm, and L ¼ 10 μm. (a) Calculate the drain current for VG ¼ 0 and VD ¼ 0.1 V. (b) Find VDsat for the top-gate voltage VG ¼ 0 and VG ¼ 1 V. (c) At what top-gate voltage does the channel conductance gD to zero? 22. In a symmetrical double-gated PJFET, the channel and gate concentrations are uniform with NA ¼ 1016 cm3 and ND ¼ 1020 cm3. The channel length, width, and metallurgical thickness are, respectively, 4 μm, 4 μm, and 0.76 μm. What gate voltage will yield a JFET resistance of 205 kΩ? Assume VD ¼ 0.1 V and neglect source and drain series resistances.

References 1. A.B. Phillips, Transistor Engineering (McGraw-Hill, 1962) 2. B. El-Kareh, Fundamentals of Semiconductor Processing Technologies (Kluwer Academic Publishers, 1995) 3. P.J. Coppen, W.T. Matzen, Distribution of recombination current in emitter-base junctions of silicon transistors. IEEE Trans. Electron Dev. ED-9(1), 75–81 (1962) 4. C.T. Sah, Effect of surface recombination and channel on p-n junction and transistor characteristics. IEEE Trans. Electron Dev. ED-9(1), 94–108 (1962) 5. C.T. Sah, R.N. Noyce, W. Shockley, Carrier generation and recombination in p-n junctions and p-n junction characteristics. IRE Trans. Electron Dev. 45(9), 1228–1238 (1957) 6. G.D. Mahan, Energy gap in Si and Ge: Impurity dependence. J. Appl. Phys. 51(5), 2634–2646 (1980) 7. T.N. Morgan, Broadening of impurity bands in heavily doped silicon. Phys. Rev. 139, 343–348 (1965) 8. R.J. Van Overstraeten, H.J. DeMan, R.P. Mertens, Transport equation in heavily doped silicon. IEEE Trans. Electron Dev. ED-20(3), 290–298 (1973) 9. H.P.D. Lanyon, R.A. Tuft, Bandgap narrowing in moderately to heavily doped silicon. IEEE Trans. Electron Dev. ED-26(7), 1014–1018 (1979) 10. J.W. Slotboom, H.C. DeGraaff, Bandgap narrowing in silicon bipolar transistors. IEEE Trans. Elecron Dev. ED-24(8), 1123–1125 (1977) 11. J. del Alamo, S. Swirhun, R.M. Swanson, Simultaneous measurement of hole lifetime, hole mobility and bandgap narrowing in heavily doped n-type silicon. IEEE IEDM Tech. Digest, 290–293 (1985) 12. E.J. McGrath, D.H. Navon, Factors limiting current gain in power transistors. IEEE Trans. Electron Dev. ED-24(10), 1255–1259 (1977) 13. B. El-Kareh, Chap. 3, in Silicon Devices and Process Integration, (Springer, 2009), p. 167 14. A. Hastings, The Art of Analog Layout (Pearson Prentice Hall, 2006), pp. 312–313

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15. W.M. Webster, On the variation of junction transistor current amplification factor with emitter current. Proc. IRE 42(6), 914–920 (1954) 16. C.T. Kirk Jr., A theory of transistor cut-off frequency fall-off at high current densities. IEEE Trans Electron Dev. ED-9(2), 164–174 (1962) 17. S.K. Ghandhi, The Theory and Practice of Microelectronics (John Wiley and Sons, 1968) 18. Y.S. Yuan, Base current reversal in bipolar transistors and circuits: A review and update. IEE Proc.-Circuits Syst. 141(4), 299–306 (1994) 19. J.M. Early, Effects of space-charge layer widening in junction transistors. Proc. IRE 40, 1401–1406 (1952) 20. H.K. Gummel, A charge control relation for bipolar transistors. Bell Syst. Tech. J. 49, 115–120 (1970) 21. E.J. Prinz, J.C. Sturm, Analytical modeling of current gain – Early voltage products in Si/Si1xGex/Si heterojunction bipolar transistors. IEEE IEDM Tech. Digest, 853–856 (1991) 22. L.J. Giacoletto, Study of p-n-p alloy junction transistor from d-c through medium frequencies. RCA Rev. 15(4), 506–562 (1954) 23. E.O. Johnson, Physical limitations on frequency and power parameters of transistors. RCA Rev., 163–177 (1975) 24. J. D. Cressler and G. Niu, Silicon-Germanium Heterojunction Bipolar Transistors., Artech House, 2003 25. T.H. Ning, D.D. Tang, Bipolar trends. Proc. IEEE 74(12), 1669–1677 (1986) 26. I. Getreu, Modeling the Bipolar Transistor (Tektronix Inc, 1976), p. 144 27. D.K. Schroder, Semiconductor Material Device Characterization (John Wiley and Sons, 1998), p. 218 28. R.J. Baker, CMOS, Design, Layout, and Simulation, J (Wiley & Sons, Inc., 2010) 29. P.R. Gray, P.J. Hurst, S.H. Lewis, R.G. Meyer, Analysis and Design of Analog Integrated Circuits (John Wiley & Sons, 2001) 30. D.F. Hilbiber, A new semiconductor voltage standard. IEEE ISSCC, Digest Tech. Papers, 32–33 (1964) 31. R.J. Widlar, New developments in IC voltage regulators. IEEE ISSCC, Digest Tech. Paper, 158–159 (1970) 32. A.P. Brokaw, A simple three-terminal IC bandgap reference. IEEE J. Solid State Circuits SC-9 (6), 388–393 (1974) 33. C.R. Palmer, R.C. Dobkin, A Curvature Corrected Voltage Reference (ISSCC, 1981), pp. 58–59 34. G.C.M. Meijer, P.C. Schmale, K. van Zalinge, A new curvature corrected bandgap reference. IEEE JSSC SC-17(6), 1139–1143 (1982) 35. B.-S. Song, P.R. Gray, A precision curvature-compensated CMOS bandgap reference. IEEE JSSC SC-18(6), 634–643 (1983) 36. V.V. Ivanov, K.E. Sanborn, I.M. Filanovsky, Bandgap Voltage References with 1 V Supply (ESSCIRC, 2006), pp. 311–314 37. M.A.P. Pertijs, G.C.M. Meijer, J.H. Huijsing, Precision temperature measurement using CMOS substrate PNP transistors. IEEE Sensors J. 4(3), 294–300 m 2004 38. V.A. Vashchenko, D.J. LaFonteese, K.G. Korablev, Lateral PNP BJT ESD protection devices. IEEE BCTM, 53–56 (2008) 39. W. Shockley, A unipolar ‘field-effect’ transistor. Proc. IRE 40(11), 1367–1376 (1952)

Chapter 6

Analog/RF CMOS

Abstract The trade-offs between parameters are different for digital, analog, and RF CMOS. In particular, there are conflicting requirements between analog and digital CMOS on operating voltage level, reduced low-frequency noise, high output resistance, low component mismatch, and high linearity. Thus, modifications must be made to the basic digital structure to satisfy analog circuit needs. In contrast, the characteristics of RF CMOS are essentially the same as those of highspeed digital CMOS so that both designs can be integrated on the same chip with little added complexity. In this chapter we first review the characteristics of the two-terminal MOS structure. This lays the groundwork for the discussion of MOSFET and CMOS characteristics in the sections that follow, with emphasis on key analog parameters. The chapter concludes with a review of mobility enhancement techniques, high-κ dielectrics, FinFETs, and fully depleted SOI MOSFETs and a brief discussion of analog CMOS applications.

6.1

Introduction

There is a strong cost-saving incentive to design analog and digital functions on the same chip. Typical examples of single-chip mixed analog and digital circuits are analog-to-digital and digital-to-analog converters. The trade-offs between analog and digital component parameters are, however, different. In particular, there are conflicting requirements on operating voltage, reduced low-frequency noise, high output resistance, low component mismatch, and high linearity. This requires modifications to be made to the base digital structure to satisfy analog needs. In contrast, the characteristics of RF CMOS are close to those of high-speed digital

The terms MOS, MOSFET, and CMOS stand for metal–oxide–silicon, MOS field-effect transistor, and complementary MOS (transistors). In earlier technologies, the metal of choice was aluminum, the insulator (dielectric) was silicon dioxide (or simply, oxide), and the semiconductor was silicon. The term MOS is still used, even for structures having a conductor other than metal, an insulator other than oxide, and a semiconductor material other than silicon. © Springer Nature Switzerland AG 2020 B. El-Kareh, L. N. Hutter, Silicon Analog Components, https://doi.org/10.1007/978-3-030-15085-3_6

221

222

6 Analog/RF CMOS

CMOS so that both designs can be integrated on the same chip with little added complexity. We begin this chapter with a review of the two-terminal metal–oxide–silicon (MOS) structure which is the heart of the MOSFET. This lays the foundation for the discussion of MOSFETs and CMOS characteristics in the sections that follow. The chapter concludes with a brief discussion of analog CMOS applications.

6.2

Review of MOS Properties

The MOS structure consists of a semiconductor covered by an insulator upon which a conductive electrode, referred to as the gate, is deposited (Fig. 6.1). The term MOS stems from earlier technologies that utilized aluminum for the gate, silicon dioxide (or simply oxide) for the dielectric, and a silicon substrate to form the capacitor. The need for a gate conductor that can withstand high-temperature annealing and allow self-alignment of gate to junctions led to the development of heavily doped N-type or P-type polysilicon and refractory metal gates to replace aluminum. The MOS structure is the heart of the MOS field-effect transistor, MOSFET. It is also a powerful, fast, and effective two-terminal (2T) device to study properties of the semiconductor, insulator, and their interfaces [1–3]. It is widely utilized to measure parameters directly related to the MOSFET and to monitor important processing steps.

6.2.1

Flatband Condition

When the majority-carrier concentration at the surface is equal to the ionized doping 1 þ concentration, i.e., ps ¼ N  A for a P-type surface, ns ¼ N D for an N-type surface, the structure is said to be at flatband. An idealized structure exhibits zero contact

Gate conductor M Dielectric Semiconductor

O S

Fig. 6.1 The MOS structure

1 The subscripts “s” and “b” will be used throughout the chapter to indicate, respectively, surface and bulk parameters.

6.2 Review of MOS Properties

223

Vacuum level Electron Energy

EC

cox

EC cSi

cox cSi

fm

fm EC

Eg/2 fb

EF

fb

Ei EF EV

Gate Oxide P-type Si EV

EF

Eg/2

EV Gate Oxide N-type Si EV

x

EC EF Ei

x

Fig. 6.2 Energy band diagram for an MOS structure at flatband

potential between gate and silicon, zero current through the dielectric under all static conditions, and zero dielectric and interface charge. Therefore, the structure is at flatband when the gate voltage VG ¼ 0. The energy band diagram for this case is shown in Fig. 6.2 for P-type and N-type silicon. The quantity ϕm is the work function of the gate.2 The minimum energy required to lift an electron from the Fermi level to the vacuum level is qϕm. A single gate material cannot simultaneously satisfy the flatband condition for both P-type and N-type silicon, so the work functions are shown differently. The quantity χ Si is the electron affinity of silicon (χ Si ffi 4.05 V [4]). The minimum energy required to raise an electron from the bottom of the conduction band to the vacuum level is qχ Si. Single-crystal silicon and polysilicon are assumed to have the same electron affinity. Conventionally, the Fermi potential ϕb is negative for P-type Si and positive for N-type Si. It is defined as (Chap. 2) kT N A ; P-type : ϕb ffi  ln ni q

N-type : ϕb ffi

kT N D ln V ni q

ð6:1Þ

where ni is the intrinsic-carrier concentration. Thus, the silicon work function is given by ϕSi ¼ χ Si þ




  E g =2q  ϕb V

ð6:2Þ

Unless otherwise stated, E, EF, Ei, EC, EV, and Eg are energies expressed in eV; ϕ, ψ, and χ are expressed as potentials in V. Energies and potentials have the same numerical value but different units. Example, kT is expressed in eV and kT/q in V. 2

224

6 Analog/RF CMOS

Example 6.1 The uniform doping concentration in P-type silicon is NA ¼ 1017 cm3. Find the Si work function at 27, 40, and 150  C. Assume χ Si ¼ 4.05 V at all temperatures. Solution The temperature dependence of the Si energy gap and intrinsiccarrier concentrations can be approximated as (Chap. 2) E g =q ffi 1:187  3:6  104 T V ni ffi 2:63  1016  T 1:5  e6885=T cm3 The Fermi potential, ϕb, is found from (6.1) and the work function from (6.2). Table 6.1 summarizes the results. Table 6.1 Temperature dependence of silicon work function T (K) 233 300 423

ni (cm3) 1.37  1007 1.47  1010 1.95  1013

ϕb (V) 0.456 0.407 0.311

Eg/q (V) 1.10 1.08 1.03

ϕSi (V) 5.16 5.06 4.98

In actual structures, the workfunction difference between the gate conductor and silicon surface is typically not zero. Since ϕSi changes with temperature, there can be at most one temperature at which the workfunction difference is zero. There is also some charge distribution within the oxide bulk and at the oxide–silicon interface. In this case, the flatband voltage is shifted negative or positive from zero, depending on the polarity of the workfunction difference and oxide charge. (a) Workfunction Difference The workfunction difference (or contact potential) between gate and Si is ϕms ¼ ϕm  ϕSi V

ð6:3Þ

Typical poly gates are heavily doped N-type or P-type. In this case they are referred to as N+-poly and P+-poly. In N+-poly, the Fermi level nearly coincides with the bottom of the conduction band, and the work function is ϕm ffi χ Si. For P+-poly, the Fermi level nearly coincides with the top of the valence band, and the work function is ϕm ffi χ Si + Eg/q. For example, the workfunction difference between N+poly and N-type silicon is 
  ϕms ¼ ϕm  ϕSi ¼  E g =2q  ϕb V

ð6:4aÞ

For P+-poly it is ϕms ¼ ϕm  ϕSi ¼




  Eg =2q þ ϕb V

ð6:4bÞ

6.2 Review of MOS Properties

225

Example 6.2 Find the workfunction difference between polysilicon and silicon for the following cases. Assume 25  C. 1. 2. 3. 4.

N+-poly, P-type silicon, NA ¼ 8  1016 cm3 P+-poly, P-type silicon, NA ¼ 8  1016 cm3 N+-poly, N-type silicon, ND ¼ 8  1016 cm3 P+-poly, N-type silicon, ND ¼ 8  1016 cm3

Solution The energy gap Eg ffi 1.12 eV at 25  C. The Fermi potential is found from (6.1) for P-type silicon as ϕb ffi 0.403 V and for N-type silicon as ϕb ffi +0.403 V. The work functions of N+- and P+-poly are, respectively, ϕm ffi χ Si ffi 4.05 V and ϕm ffi Eg/2q + χ Si ffi 1.12 + 4.05 ¼ 5.17 V. The workfunction difference between the polysilicon gate and silicon is 1. For N+-poly, P-type silicon, NA ¼ 8  1016 cm3  
 ϕms ¼ ϕm  ϕSi ¼  Eg =2q  ϕb ffi ð0:56 þ 0:403Þ ¼ 0:963 V 2. For P+-poly, P-type silicon, NA ¼ 8  1016 cm3 ϕms ¼ ϕm  ϕSi ¼




  Eg =2q þ ϕb ffi 0:56  0:403 ¼ þ0:157 V

3. For N+-poly, N-type silicon, ND ¼ 8  1016 cm3  
 ϕms ¼ ϕm  ϕSi ¼  Eg =2q  ϕb ffi ð0:56  0:403Þ ¼ 0:157 V 4. For P+-poly, N-type silicon, ND ¼ 8  1016 cm3 ϕms ¼ ϕm  ϕSi ¼




  Eg =2q þ ϕb ffi ð0:56 þ 0:403Þ ¼ þ0:963 V

The simplified band diagrams in Fig. 6.3 illustrate the work functions for silicon and heavily doped polysilicon. The P+-poly work function is Eg/q ffi 1.12 V larger than that of the N+-poly. When the gate and substrate are connected, e.g., by a conducting medium during processing, electrons from the material with the lower workfunction flow to the material with the higher work function until equilibrium is established and the Fermi levels align. Only a few electrons are required to align the Fermi levels. Unless otherwise stated, it will be assumed throughout the following discussion that the semiconductor is uniformly doped P-type silicon held at ground, the gate conductor consists of N+-poly, and the gate dielectric is oxide. The band diagram for an MOS structure at equilibrium is shown for N+-poly and P-type substrate in Fig. 6.4. Since there is no current through the oxide, the Fermi level is shown aligned across the silicon and oxide.

226

6 Analog/RF CMOS

Vacuum level c

(a)

fb

fPoly= c+Eg EC Ei E P+-POLY F ªEV

fPoly ª c EF ªEC Ei EV

fb (b) N+-POLY

Vacuum level c

(c)

c

fSi EC Ei EF EV

fb

fb (d)

fSi EC EF Ei EV

N-type Si

P-type Si

Fig. 6.3 Simplified band diagrams. (a) P+-poly. (b) N+-poly. (c) P-type silicon. (d) N-type silicon

- f ms = Vox + y s

Fig. 6.4 Thermalequilibrium MOS band diagram in presence of a workfunction difference between N+-poly and P-type silicon

Vox > 0 ys

EC f b Ei EF Ev Depletion of holes Oxide P-type Si

EF ª EC Ei EV N+-poly

Because ϕm < ϕSi, equilibrium is established by a net flow of electrons from polysilicon to P-type silicon. This leaves the polysilicon with a positive voltage ϕms with respect to the silicon bulk, depleting the surface of holes and bending the bands down (positive surface potential, ψ s), as shown in Fig. 6.4. The polysilicon potential drops partially across the oxide and partially in silicon, i.e., ϕms ¼ Vox + ψ s, where Vox is the voltage drop across the oxide and ψ s is the surface potential. To re-establish flatband, a negative voltage VFB ¼ ϕms must be applied to the gate.

6.2 Review of MOS Properties

227

(b) Effective Oxide Charge Dielectric charges of different origins may be created during processing or as a result of electrical stress. In typical MOS structures, the charges are located in various parts of the dielectric. They are classified as Qit, interface charge related to states located at the silicon surface; Qf, fixed oxide charge, typically positive, located in a narrow region in the oxide near the silicon surface; Qot, oxide trapped charge due to imperfections throughout the bulk of the oxide layer; and Qm, mobile charge, mostly related to ionized impurities, such as Na+ or K+, that can easily migrate in the oxide even under operating conditions [5, 6]. The main interest in those charges is, however, their effect on the underlying silicon. Positive charges contribute to depleting the surface of holes at the P-type silicon surface, thus causing a negative shift in VFB, while negative charges tend to accumulate the surface with holes, causing a positive shift in VFB. If the charges are located at the gate–oxide interface, they are mostly imaged in the highly concentrated gate conductor and have negligible effect on the silicon surface. In comparison, charges located at the silicon–oxide interface are almost fully imaged in silicon. The distribution of dielectric charge is rarely predictable. This is why the concept of effective oxide charge has been introduced. The effective oxide charge, Qeff, is the charge density per unit area assumed to be located at the silicon–oxide interface and to have the same effect on the silicon surface as the distributed charge. An effective oxide charge, Qeff, causes a shift in VFB by ΔV FB ¼ Qeff =C ox V

ð6:5Þ

Thus, to re-establish flatband in the presence of non-zero ϕms and Qeff, a voltage must be applied to the gate of magnitude V G ¼ V FB ¼ ϕms  Qeff =C ox V

6.2.2

ð6:6Þ

Accumulation and Depletion

For VG  VFB < 0, a negative charge is induced at the gate–oxide interface. An equal amount of charge of opposite polarity must appear in silicon to maintain neutrality. This charge consists of excess holes, Δps, attracted to the silicon surface: QG ¼ QΔps C=cm2

ð6:7Þ

This creates a negative voltage, Vox, across the oxide and a negative surface potential, ψ s, in silicon where V G  V FB ¼ V ox þ ψ S V

ð6:8Þ

The bands bend up, indicating an increase in the hole concentration above NA (Fig. 6.5a). This condition is referred to as accumulation.

228

6 Analog/RF CMOS

Vox < 0

Vox > 0

Ys > 0

y s< 0 EFm

f b Ei EF

VG-VFB < 0 Gate

(a)

Oxide Si Accumulation

fb Ei EF

VG-VFB > 0 EFm

Depletion

Gate Oxide Si

(b)

Fig. 6.5 Band diagram for an MOS structure. (a) In accumulation. (b) In depletion

Although a voltage is applied, the system is considered to be at thermal equilibrium inasmuch as the relation pn ¼ n2i remains valid. For an N+-poly gate, both the gate and the substrate are accumulated at their interfaces with oxide. The electron concentration in the N+-poly is, however, very high, and the distribution of accumulated electrons does not extend appreciably into the poly. The charge in the poly can thus be approximated as a sheet of infinitesimal thickness located at the gate– oxide interface. Also, in strong accumulation, where ps increases by orders of magnitude above NA, the charge of excess holes can also be approximated as a positive charge-sheet located at the silicon–oxide interfaces. Thus, the field in the oxide is approximated as Effi

V G QΔps QG ¼ ¼ V=cm t ox ε0 εox ε0 εox

ð6:9Þ

For VG  VFB > 0, a positive charge-sheet is induced at the poly oxide interface. This charge must be balanced by an equal amount of negative charge in silicon. Initially, holes are repelled from the surface, “exposing” negative acceptor ions. Electrons are simultaneously attracted to the surface, but their concentration is initially negligible compared to the ionized acceptor concentration so that nearly all the positive charge on the gate is compensated by negative ions in Si. The bands bend down to reflect a decrease in hole concentration and a slight increase in electron concentration (Fig. 6.5b). A depleted (space charge) region of width xd forms under the surface. This is similar to the depletion region formed in an abrupt N+P-junction. For (VG  VFB) larger than about 3kT/q, the depletion approximation can be applied. The depletion width and silicon capacitance are then found as sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ε0 εSi ψ s 1:3  107 ψ s ffi xd ffi cm, qN A NA

ε0 εSi ¼ C Si ¼ xd

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qN A ε0 εSi F=cm2 2ψ s ð6:10Þ

and the bulk charge density Qb is given by

6.2 Review of MOS Properties

Vox > 0

fb< y s< 2 fb Vox > 0

ys

VG – VFB > 0

fb Ei EF Weak inversion

EFm Gate

229

Oxide

fb VG – VFB > 0 EFm Gate Oxide

Si

(a)

ysmax ª 2fb f b Ei EF Strong inversion Si

(b)

Fig. 6.6 Band diagram for an MOS structure. (a) In weak inversion. (b) In strong inversion

Qb ffi qN A xd ¼

ffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ε0 εSi qN A ψ s ffi 3:32  1031 N A ψ s C=cm2

ð6:11Þ

As (VG  VFB) is increased, a point is reached where the electron and hole concentrations become equal at the surface, i.e., the intrinsic level Ei coincides with the Fermi level EF and the surface is said to be intrinsic. The surface potential for this case is ψ s ¼ ϕb ¼

6.2.3

kT N A ln V ni q

ð6:12Þ

Weak and Strong Inversion

As (VG  VFB) is further increased, ψ s increases above ϕb (Fig. 6.6a). The electron concentration becomes higher than the hole concentration at the surface. The surface is said to enter the weak inversion regime. The term weak implies that, while the electron concentration increases, it remains small compared to NA, i.e., the depletion approximation can still be made. The electron concentration in weak inversion cannot, however, be neglected when discussing the MOSFET subthreshold characteristics (Sect. 6.3.1). The onset of strong inversion is approximated as the surface condition where ns  NA. This means that (EF  Ei) at the surface should be equal to ϕb, i.e., the bands should bend down by ψ smax ffi 2ϕb (Fig. 6.6b). Then, at onset of strong inversion ns ffi nb eqψ s =kT ffi nb eq2ϕb =kT ffi pb ffi N A cm3

ð6:13Þ

where nb and pb are, respectively, the thermal equilibrium electron and hole concentration in the bulk. The gate voltage at onset of strong inversion is the threshold voltage, VT.

6 Analog/RF CMOS

Fig. 6.7 Variation of surface charge density with ψ s [7, 8]

Surface charge, Qs (C/cm2)

230

10-4

P-type Si, 300 K, NA = 1017 cm-3

10-5 10-6

Accumulation

Depletion Weak inversion fb fb

10-7 10-8 10-9 -0.4

∝ ys

Strong inversion

-0.2

0 0.2 0.4 0.6 0.8 Surface potential, y s (V)

1.0

1.2

The variation of charge density with surface potential is shown in Fig. 6.7 for a P-type substrate with uniform NA ¼ 1017 cm3 [7, 8]. It can be seen that the hole concentration increases rapidly as ψ s becomes negative, and the electron concentration increases rapidly as ψ s increases above 2ϕb. For ψ s in the range 0–2ϕb, the charge induced in silicon consists mainly of bulk charge of ionized acceptors. The following simplifying assumptions are made for the case of strong inversion: 1. For VG  VT (or ψ s  2ϕb), the charge per unit area of free carriers is negligible compared to the charge of NA and the depletion approximation holds. 2. The inversion electron concentration increases rapidly as VG increases above VT. The inversion layer shields the subsurface from the field induced by the gate. This implies that a gate voltage above VT results in an increase in the inversion electron charge and a negligible increase in the depletion width and surface potential. Thus, at VG ¼ VT, the surface potential is assumed to reach its maximum value ψ smax, and the depletion width reaches its maximum value xdmax. To satisfy neutrality, the charge per unit area induced at the gate, Qm, must be balanced by the total charge per unit area in silicon, QSi: Qm ffi ðQb þ Qn Þ ¼ QSi C=cm2

ð6:14Þ

where Qb is the bulk charge per unit area of uncompensated acceptor ions and Qn the electron inversion charge per unit area. At onset of strong inversion, Qb approaches its maximum value Qbmax given by pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Qbmax ffi qN A xdmax ffi  2ε0 εSi qN A ψ smax C=cm2

ð6:15Þ

With the above assumptions, Qn is negligible at and below the onset of strong inversion, and the threshold voltage can be expressed as

6.2 Review of MOS Properties

231

V T ffi V ox þ ψ smax ffi V FB  ðQbmax =Cox Þ þ ψ smax V

ð6:16Þ

where Qbmax is given by (6.15) and Cox ¼ ε0εox/tox. As VG increases above VT, Qn begins to increase rapidly, while Qb remains nearly constant at Qbmax. Under these assumptions Qn ffi Cox ðV G  V T Þ C=cm2

ð6:17Þ

The gate voltage above VT, (VG  VT) is referred to as the gate overdrive. At this point, it may be helpful to consider the question of how inversion electrons are supplied to the surface of a 2T MOS structure. As VG increases above VT, the “demand” for electrons increases rapidly. Assuming that the structure is defect-free and kept in a dark enclosure and that impact ionization caused by the surface field in silicon is negligible, then the only way minority electrons can be supplied to the silicon surface is by thermal generation, a very slow process at room temperature. Consequently, if VG is swept rapidly above VT, the generation of electron–hole pairs cannot keep up with the increase in VG, so Qn is initially much lower than its steady-state value given by (6.17). To maintain neutrality, the depletion width must initially increase beyond xdmax to provide additional bulk charge ΔQb. This condition is referred to as deep depletion. If the gate voltage sweep is stopped and VG held at a fixed potential above VT, the depletion relaxes slowly to its steady-state value xdmax. The relaxation can, however, take several tens of seconds, depending on the generation rate. Adding a third terminal as a source of electrons accelerates the formation of the steady inversion layer, as shown in Fig. 6.10. If one makes the classical assumption that all the inversion layer charge is located at the silicon surface, then the surface field in silicon, Es, can be expressed as Es ffi 

Qb þ Qn V=cm ε0 εSi

ð6:18aÞ

Quantum mechanics, however, predicts that the peak of the inversion layer is not located at the surface but at an average depth xinv ranging from 1 to 2 nm below the surface [9–12]. Thus, an average of Qn is assumed to contribute to the surface field which is approximated by Es ffi 

Qb þ ηQn Qb þ ηQn ffi V=cm ε0 εSi 1:037  1012

ð6:18bÞ

where for a (100) surface, the averaging factor η ¼ 1/2 for electrons [13]. In case of inverted N-type silicon, η ¼ 1/3 for holes [14].

232

6 Analog/RF CMOS

Example 6.3 1. Find the threshold voltage of an MOS structure with an N+-poly gate, constructed on a P-type silicon having NA ¼ 2  1017 cm3, and tox ¼ 7.2 nm. Assume 25  C. 2. By how much would VT change if instead of an N+-poly gate a P+-poly gate were formed? 3. How would VT change if only the gate and the silicon doping polarities are reversed? Solution 1. The Fermi potential is found from (6.1) as ϕb ¼ 

kT N A 2  1017 ffi 0:0257 ln ffi 0:426 V ln ni q 1:25  1010

The workfunction difference is ϕms

  Eg  ϕb ffi ð0:56 þ 0:426Þ ¼ 0:986 V ¼ ϕm  ϕSi ¼  2q

The maximum surface potential is ψ smax ¼ 2ϕb ffi 0.852 V, and the maximum bulk charge is found from (6.15) as Qbmax ffi 

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 3:317  1031  2  1017  0:852 ffi 2:38  107 C=cm2

The oxide capacitance is Cox ¼

ε0 εox 8:86  1014  3:9 ffi ffi 4:8  107 F=cm2 t ox 7:2  107

The threshold voltage is then found from (6.16) as VT ffi 

Qbmax 2:38  107 þ ψ smax þ ϕms ffi þ 0:852  0:986 ffi 0:361 V C ox 4:8  107

2. By just replacing N+-poly with P+-poly, the workfunction difference between gate and silicon increases by Eg/q ffi 1.12 V and becomes positive. The threshold voltage thus increases to about 1.12 + 0.361 ¼ 1.481 V. 3. Since only the polarity of dopants in polysilicon and silicon change, the magnitude remains the same as for the NMOS, but VT becomes negative, i.e., VT ¼ 0.361 V.

6.2 Review of MOS Properties

6.2.4

233

MOS C-V Technique

The MOS capacitance-voltage (C-V) technique is a powerful tool for extracting important CMOS process and device parameters. A 2T MOS structure is shown in the inset of Fig. 6.8. Ideally, it can be represented by two capacitors in series, the oxide capacitor of fixed capacitance Cox and the silicon capacitance having a voltage-dependent capacitance CSi. The equivalent capacitance is C¼

C ox  CSi C ox ¼ F=cm2 C ox þ CSi 1 þ Cox =C Si

ð6:19Þ

To measure a C-V plot, the structure is placed in a shielded-light enclosure to avoid distortion of the plot by photon generation of electron–hole pairs. The capacitance is measured with a small sinusoidal voltage signal of typical amplitude 10–15 mV and frequency 0.01–1 MHz. The small signal is superimposed on a slow-varying gate-to-substrate DC voltage, VG, which is swept in both polarities. The voltage sweep can start at any point but typically from strong accumulation to strong inversion or in the reverse direction. To ensure equilibrium at any point in inversion while varying the gate voltage at a time-efficient sweep-rate, a light source can be briefly turned-on to generate the required minority carriers, and then off so that minority carriers in excess of equilibrium can dissipate. A reconstructed highfrequency C-V plot is shown in Fig. 6.8c for an MOS structure with N+-polysilicon gate and with Cmin at equilibrium (solid line). The measured plot is typically shifted parallel from the idealized plot (dashed line).

VG Small AC signal

Cmaxª Cox= 0.276 mF/cm2 Strong accumulation Real Gate

0.3

C (mF/cm2 )

25

CFB = 0.200 mF/cm2

0.2

Flatband

Substrate

(a)

(b) VG Cox

(c)

Equilibrium Cmin=0.0680 mF/cm2

0.1

y s Surface

CSi

-5

-4

Strong inversion

VFB

Bulk -3

-2

-1

0

1

2

3 4 VG (V)

5

Fig. 6.8 (a) High-frequency C-V plot with steady-state C min. Solid line measured, dashed line idealized, VFB ¼ 0 V. Inset (b) Schematic of MOS structure with AC signal superimposed on DC voltage sweep. (c) Representation of MOS structure by two capacitances in series

234

6 Analog/RF CMOS

Fig. 6.9 C-V plot of MOS structure, illustrating deep depletion

100 90

Cmax CFB

Capacitance, C (pF)

80 70

Gate: N+ polysilicon, 300 K MOS area: 1.2x10-3 cm2 Voltage sweep-rate: 0.2V/s Cmax = 86.6 pF Cmin = 30.7 pF

60 50

40 30

Cmin

20 10 0

B M

M

VFB

Deep depletion

Cdeep A

-7 -6 -5 -4 -3 -2 -1 0 1 2 3 Gate voltage, VG (V)

4

5

6

7

At a typical gate voltage sweep-rate of 0.2 V/s without a light source, the generation of minority carriers is too slow and cannot keep up with the change in voltage. In defect-free silicon, only majority carriers can follow the varying DC voltage. Thus, as the gate voltage is increased toward inversion, the depletion width must increase to “expose” more negative ions, and the capacitance decreases to Cdeep, below the equilibrium Cmin (Fig. 6.9). After stopping the voltage sweep, e.g., at point A, the capacitance relaxes with time to Cmin. Relaxation by means of thermal generation alone is, however, very slow. It can be accelerated with a short light pulse at, e.g., point A. Because of the large excess of photon-generated carriers, the capacitance initially overshoots to a value higher than Cmin at point B. It drops back to the equilibrium value after turning off the light. As the voltage is swept in the reverse direction, the capacitance increases slightly to the level M above Cmin. This is because excess electrons flow back to the substrate as the gate voltage is decreased. When the voltage sweep is stopped again, the capacitance drops to Cmin. (a) Flatband Capacitance, CFB The voltage dependence of C in Fig. 6.8 is due to the voltage dependence of CSi. A good reference value is the flatband capacitance, CFB, which is the capacitance measured when the surface is at flatband, i.e., when ps ¼ NA. The corresponding gate voltage is the flatband voltage, VFB. The silicon capacitance at flatband is CSiFB given by CSiFB ¼ dQ=dV ¼ ε0 εSi =LD F=cm2

ð6:20Þ

where LD is a characteristic length, called the Debye length, that depends on the free carrier concentration. For P-type silicon at 25  C, LD is approximated by [7]

6.2 Review of MOS Properties

LD ¼

235

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðε0 εSi kT Þ=ðq2 ps Þ ffi 1:665  105 =N A cm

ð6:21Þ

One can place an imaginary plane at a distance LD from the surface and assume that all the charge responding to the signal is located at LD. Thus, the region between surface and LD can be treated as a parallel plate capacitor of dielectric constant εSi ¼ 11.7 and thickness LD. The same approximation applies to N-type silicon at flatband by substituting ND for NA. The MOS flatband capacitance is found from (6.19) as C FB ¼

C ox F=cm2 1 þ Cox =C SiFB

ð6:22Þ

In most cases, NA (or ND) is not known a priori and must be extracted from measurements as discussed later. (b) Capacitance in Accumulation As the gate voltage becomes more negative than VFB and the surface becomes accumulated with holes, LD in (6.21) decreases, and CSi increases, increasing C. In the limit, C reaches a high value referred to as Cmax which can be approximated as Cox (6.19). (c) Capacitance in Depletion For (VG > VFB), ψ s increases so ps decreases below NA. Also, ns increases but its value remains small compared to NA. In the range ~3kT < ψ s  2ϕb, the depletion approximation applies since the excess hole and electron charges ΔQp and ΔQn remain negligible compared to Qb. As ψ s increases, xd increases, the silicon capacitance decreases, and the total capacitance decreases (Fig. 6.8). (d) Strong Inversion, Extraction of Effective Doping Concentration In strong inversion the capacitance reaches a steady-state Cmin, the surface potential ψ s, the depletion width xd, and the bulk charge Qb reach approximately their maximum values ψ smax, xdmax, and Qbmax. Combining the ratio Cmax/Cmin with the expressions for ψ smax ffi 2ϕb, xdmax, Cox ¼ ε0εox/tox, and CSimin ¼ ε0εSi/xdmax gives the following relation which can be used to extract the doping concentration at the surface of P-type silicon NA ffi

2ε0 ε2ox jψ smax j 3    cm qεSi t 2 ðCmax =Cmin Þ  1 2 ox

ð6:23aÞ

Substituting the expression for ϕb found in (6.1) and the values for the constants at 25  Cin (6.23a) reduces (6.23a) to

236

6 Analog/RF CMOS

N A ffi 7:397  104

t 2ox



ln N A  23:25 3  2 cm ðCmax =Cmin Þ  1

ð6:23bÞ

The above equation can be solved by iteration. (e) Extraction of Doping Profile from Pulsed C-V Measurements For an arbitrary doping profile, the inverse-square capacitance method derived in (4.30) can be applied in deep depletion to obtain the concentration versus depth. For a P-type substrate we get N A ð xÞ ¼ 

2 dV G ΔV ffi 1:21  1031 G cm3 qε0 εSi d 12 Δ 12 C

ð6:23cÞ

C

where C is the MOS capacitance measured as a function of the depleting gate voltage, VG. This method assumes that during capacitance measurements, thermal generation of electron–hole pairs (EHP) is negligible. For this purpose, the measurement is performed in a pulsed mode, with the structure kept in a light-tight enclosure, as detailed in [15]. (f) Extraction of Minority-Carrier Lifetime from C-t Measurements in Deep Depletion When the structure is kept in a dark enclosure and the gate voltage kept constant at point A in Fig. 6.9, the capacitance begins to increase slowly with time as electron– hole pairs are thermally generated and inversion carriers are provided to the surface. The time for the structure to increase from its deep depletion-value at point A to its thermal equilibrium value, Cmin, is called the relaxation time. Thus, in the absence of light and other disturbances, the relaxation time is related to the thermal generation rate of EHP. From Chap. 2, we know that the generation rate is related to the minority-carrier lifetime. This relationship allows the extraction of minority-carrier lifetime from the capacitance versus time, C-t, measurement, as detailed in [15]. (g) Extraction of the Mobile Charge Density The effective dielectric charge, Qeff, is discussed in Sect. 6.2.1. It can be extracted from the shift in flatband voltage, VFB, using (6.5). When biasing the gate with respect to substrate at an elevated temperature, mobile charges present in the dielectric and at its interfaces can drift toward the gate, where they become ineffective, or toward the substrate, where they become fully effective. The direction of drift depends on the polarities of charge and bias. By measuring the flatband voltage, as in Fig. 6.8, before and after bias-temperature stress, the mobile charge density can be extracted [15]. (h) Extraction of Equivalent Oxide Thickness (teq or EOT) High-frequency C-V measurements on a 2T MOS structure are widely used to extract the oxide thickness, tox, in accumulation from Cmax  Cox. In strong

6.2 Review of MOS Properties

237

accumulation, however, the measured differential capacitance does not actually saturate to a maximum value. Instead, it continues to increase as VG becomes more negative, indicating an apparent decrease in oxide thickness. While this effect is negligible for oxide thicknesses above approximately 20 nm, it becomes appreciable for thinner gate oxides. The three-terminal (3T) MOS structure illustrated in Fig. 6.10 is best suited to extract the equivalent oxide thickness, teq, in both accumulation and inversion. This is because when the gate voltage is increased toward strong inversion, the third terminal (the junction) almost instantaneously supplies electrons to the surface so that inversion electrons respond immediately to both the gate voltage sweep and the AC signal. Thus, the capacitance in strong inversion is measured between the inversion layer and the gate. The junction and P-well are typically grounded, and the gate voltage is swept in both polarities, while the high-frequency capacitance is measured. For large-area MOS structures and small junction area, the junction capacitance can be neglected compared to the MOS capacitance. A high-frequency C-V plot measured on a 3T MOS structure constructed on a P-well is shown for a “physical” oxide thickness tox ¼ 3 nm in Fig. 6.11a and for tox ¼ 12.5 nm in Fig. 6.11b. The plot on a 2T structure is also shown for comparison. In both cases, the measured teq is larger than tox in both inversion and accumulation, and the capacitance does not saturate but continues to increase in accumulation. The effects are more pronounced with the thinner gate oxide. The lower capacitance (larger teq) in strong inversion is related to polysilicon depletion [16–20]. The effects can be explained by considering the voltage-dependent capacitances in silicon and polysilicon in series with the oxide capacitance. From quantum mechanics, it is shown that the centroids of inversion and accumulation layers are not located at their interfaces with the oxide but at field-dependent distances xinv and xacc from the interfaces [9–13]. Thus, the net capacitance consists of three capacitances in series, the silicon capacitance, the oxide capacitance, and the polysilicon capacitance. The EOT yields the same capacitance as that of the stack of the three capacitances. For example, when an MOS structure with N+-poly gate and P-well is biased in strong inversion, the poly gate is depleted to a depth xd-poly, and the centroid of the inversion layer in silicon is xinv below the surface. In this case, the EOT is

Fig. 6.10 Schematic cross section of a three-terminal MOS structure. A small AC signal is superimposed on the DC gate voltage

VG

Small AC signal N+

N+

N+ P-well

P+

238

6 Analog/RF CMOS

160 C (pF)

140 120

Accumulation Area:

100 80

Steady-state Cmin-2T

60 40

Cmin-3T

60

Inversion

2×104 μm μ 2 1.8 V -1.8 V 173 pF 179 pF teq= 4.00 nm teq=3.86 nm

20 VT 0 -2.0 -1.5 -1.0 -0.5 0 0.5 VG (V)

1.0

1.5 2.0

Accumulation Area:

2×10 μm 4

50 40 C (pF)

200 180

30 20

2

Inversion

5.0 V 51.2 pF teq= 13.5 nm

-5.0 V 52.1 pF teq=13.3 nm

Steady-state

Cmin-2T

Cmin-3T

10

VT 0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 VG (V)

(a)

(b)

Fig. 6.11 Measured high-frequency C-V plot measure at 25  C on a three-terminal structure on a P-well. (a) tox ¼ 3 nm. (b) tox ¼ 12.5 nm


 t eq ¼ t ox þ ðεox =εSi Þ xd-poly þ xinv cm

ð6:24Þ

The field dependence of teq is best extracted directly from C-V measurements in strong accumulation and in strong inversion.

6.3

MOSFETs and CMOS

The preceding section, dealing with the properties of MOS structures, shows the relationship between the silicon surface conditions and the applied gate voltage. This provides the starting point for the treatment of MOSFETs and CMOS. A MOSFET consists of four terminals: gate, source, drain, and bulk (or body). There are two basic types of MOSFETs, N-channel MOSFET, or simply NMOS, and P-channel MOSFET, or PMOS. CMOS incorporates both types of MOSFETs into the same chip. Digital CMOS deals with large signals, such as from VDD to 0 V or 0 V to VDD (Fig. 1.3), whereas analog CMOS deals with small signals, as illustrated in Fig. 1.4. This section discusses NMOS and PMOS characteristics, focusing on their analog features in a CMOS technology.

6.3.1

Review of MOSFETs, Long and Wide Channel

A MOSFET is shown schematically in top view in Fig. 6.12a and in cross section in Fig. 6.12b.

6.3 MOSFETs and CMOS

239

Contacts

Metal

Polysilicon gate

(a)

Drain

LD

WD STI

STI Contact stud

Metal

(b)

Drain STI Body

Active area

Source

Spacer

Gate

Lpoly

LDD

N+ Source-drain

1020 1019

Angled LDD

1018

Analog PWELL

1017 1016

P--Substrate

1015 Source

Silicide

STI

Lmet

Doping Concentration (cm-3)

1021

1014 (c)

0

0.5 1.0 1.5 2.0 Depth from Si surface (mm)

Fig. 6.12 (a) MOSFET top view, drawn dimensions. (b) Cross section, as fabricated dimensions. (c) Typical analog doping profile

The dimensions LD and WD are, respectively, the drawn channel length and width. Lpoly is the patterned polysilicon gate length and Lmet the distance between the source and drain metallurgical junctions along the surface. Depending on patterning, impurity profiles, and applied voltages, the effective (electrical) channel length, Leff, can be smaller, equal, or larger than drawn. The MOSFET fabrication steps are described in Chap. 9. The structure is illustrated in Fig. 6.12 for shallow-trench isolation, STI, polysilicon gate, oxide gate dielectric, and junction source and drain. Other materials and configurations are applicable but will not be further discussed in this section. Figure 6.12c shows the doping profiles for a typical analog NMOS, including P-well, source–drain, and lightly doped drain (LDD). The purpose of the LDD is to reduce the field at the drain. It is implanted at an appropriate dose, angle, and energy to optimize the structure for reduced short-channel effects and impact ionization, and to achieve a high output resistance, as discussed later. A normally off or enhancement-mode MOSFET is turned on by applying a gate voltage, VG, of sufficient magnitude to form an inversion layer that connects source and drain. When most of the conduction between source and drain occurs in the inversion layer at the surface, the structure is referred to as a surface-channel MOSFET. Figure 6.13 shows the symbols for normally off NMOS and PMOS. The discussion that follows focuses on a surface-channel NMOS. It is equally applicable to a surface-channel PMOS by reversing the doping and voltage polarities. A normally on or depletion-mode NMOS and a buried-channel PMOS are described in Sect. 6.3.2.

240 Fig. 6.13 Symbols of enhancement-mode NMOS and PMOS

6 Analog/RF CMOS

N-source Gate

P-source Gate

P-body

N-body

N-drain

P-drain

Normally-off NMOS Non-conducting when VG = 0 Turned-on with VG > VT > 0

Fig. 6.14 Biasing conditions to measure the NMOS ID versus VG characteristics for constant VD

VG S

STI

N+

G

e

Normally-off PMOS Non-conducting when VG = 0 Turned-on with VG < VT < 0

A ID VD D

N+

B

STI

P+

STI

P-well

(a) Drain Current Versus Gate Voltage at Constant Drain Voltage To simplify the discussion, the source is kept at ground and the voltages on gate, drain, and body are referred to the source. For a symmetrically arranged MOSFET shown in Fig. 6.14, either of the junctions can act as the source or drain. The source and drain are distinguished only by the applied voltages. For an NMOS, the source is the junction at the lower potential. Unless otherwise stated, the gate voltage VG, drain voltage VD, and bulk voltage VB refer to, respectively, the gate-to-source voltage VGS, drain-to-source voltage VDS, and body-to-source voltage VBS. There is no sharp boundary between a long and a short channel or between a wide and narrow channel. Short- and narrow-channel effects are gradual. Small-size effects are discussed in Sect. 6.3.3. For now, it suffices to say that a channel is considered long if the drain bias has negligible effect on threshold voltage and on the effective channel length. It is considered wide if isolation edge effects have little impact on MOSFET characteristics. For VG ¼ VFB, the channel surface is at flatband, and the source and drain behave essentially like two-independent PN junctions. Let a fixed voltage VD be applied to the drain, and let the gate voltage VG be swept from zero to the maximum operating voltage, while the drain ID is measured. Typical ID versus VG plots obtained are shown in Fig. 6.15. The different regions in the plot are now discussed.

6.3 MOSFETs and CMOS

241

ID (A)

Fig. 6.15 The different regions of the ID  VG characteristics

10-03 Moderate Strong inversion inversion 10-04 Saturation, VD = 5V 10-05 Linear Threshold VD = 0.1V 10-06 10-07 10-08 Weak inversion 10-09 10-10 Subthreshold 10-11 -12 10 Drain leakage 10-13 10-14 1.0 0.0 0.5 1.5 2.0 2.5 VG (V)

(b) Leakage Starting on the left of Fig. 6.15, there may be an initial high drain leakage current that includes junction and surface leakage and can vary in level, depending on the presence of defects, doping profile, and field distribution around the drain edges. The total leakage can be a combination of thermal generation (Chap. 3), gateinduced drain leakage (GIDL), drain-to-gate leakage at STI corners, and drain-tosource leakage. Low-level leakage current is typically not as critical to analog as to digital applications. In analog applications that require large MOSFETs, however, it can become important. Thermal Generation at the Channel Surface When the surface of the channel is at flatband and neglecting surface effects on the drain junction, the reverse drain current is that of an isolated PN junction characterized by a depletion layer of average width xd and a total reverse voltage VD + Vbi discussed in Chap. 3. This current is shown as region A of the solid curve in Fig. 6.16. As VG increases, a depletion region forms under the gate where thermally generated electrons within and near the depleted region drift to the drain, while the generated holes drift to the P-well contact. In the absence of interface states, the measured current would increase proportionally to the depletion width. This is shown as region B of the solid curve in Fig. 6.16. This current then saturates at the onset of strong inversion where xd reaches xdmax (region C of the solid curve). When interface states are present, a peak in current is observed superimposed on region B. This peak is shown as region D of the dashed curve. It is related to the density of interface states as [21, 22] I it ¼ ðqni s0 As Þ=2 A

ð6:25aÞ

242

6 Analog/RF CMOS

Junction leakage (pA)

Gate-induced drain leakage, GIDL

Depletion, weak inversion

6

D

5

Strong inversion

Interface sates generation

4 E 3

C

B 2

1

A

0 -0.5

Junction leakage plus field-induced depletion leakage

Junction leakage

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Gate voltage (V) Fig. 6.16 Drain leakage as a function of gate voltage

where ni is the intrinsic-carrier concentration, As is the area of the depleted surface under the gate, and s0 is referred to as the surface generation velocity given by s0 ¼ σvth N it cm=s

ð6:25bÞ

In the above equation, σ is the average capture cross section (1015 cm2), assumed for simplicity to be the same for electrons and holes, vth is the thermal velocity (107 cm/s), and Nit is the effective density of states per unit area, assumed to be located at mid-gap. The rapid drop in surface leakage at onset of strong inversion can be visualized by considering that in strong inversion, the probability that a state is occupied by an electron is very high so that the state can no longer act as a “stepping stone” [21]. Gate-Induced Drain Leakage (GIDL) In some cases, an increase in current is observed when the gate voltage becomes negative with respect to the drain. This is shown as region E of the dash-dot curve in Fig. 6.16. While the negative gate voltage accumulates the surface of the P-region, it depletes the surface of the overlapped N-region. An increase in VD further depletes the N-region. Three mechanisms can be responsible for the rise in current as the surface of the N-region depletes: defect-induced drain leakage, impact ionization, and tunneling. Defect-Induced Leakage Defects can be created in the highly doped N-region in the form of dislocations, stacking faults and precipitates by contamination or by mechanical stress [23]. Such defects can become centers of high generation rate. If a defect is located at a distance larger than one minority-carrier diffusion length from the depletion boundary, its contribution to leakage is negligible (Fig. 6.17a). For example, the region around a contact to the N+-region can be highly defective, but its impact on reverse leakage is

6.3 MOSFETs and CMOS

243

Gate

Source

Gate

VG1

Source

VG2 VD

Depletion (a)

VD

Depletion N+-region Defect

(b)

N+-region Defect

P-body

P-body

Fig. 6.17 Surface defect near junction edge. (a) Defect away from depletion boundary. (b) Defect near depletion boundary

minimized by keeping the contact boundary in silicon at a “safe” distance from the metallurgical junction. While defects in the highly doped region are mostly removed during annealing, residual defects can be randomly distributed and fall anywhere in the P- or N-region. If the defect falls within or near the depleted region as in Fig. 6.17b, the leakage current can increase appreciably as (VD  VG) increases. Impact Ionization and Avalanche Breakdown As VD is increased, the probability for impact ionization increases, and, when the critical field is reached, avalanche breakdown can occur. In the absence of a gate or surface charge, the breakdown voltage depends on the doping concentrations and junction curvature (Chap. 3). The two-dimensional field created by an overlapping gate at the junction edge can, however, strongly affect the junction breakdown voltage. A detailed analysis of the field distribution at the junction edge requires two-dimensional computer simulations. One can, however, get an insight into the breakdown mechanism by making some simplifying assumptions. Consider, for example, the case where VD is increased with VG ¼ VFB and the body held at ground (Fig. 6.18a). The surface of the P-region is at flatband, and the overlapped surface of the N-region is depleted. Since the drain is reverse-biased, an inversion layer will not form on its surface. Instead, the surface of the N-region goes into deep depletion as the surface potential becomes more negative. Consider a high-field path length in silicon, tSi (Fig. 6.18b). From the continuity of the displacement vector, the fields in silicon and oxide are related by Eox ¼

εSi ESi  3ESi V=cm εox

ð6:26Þ

As VD increases, the fields in silicon and oxide increase. For a given VD, the field along a path tSi is typically larger than in other regions of the junction. Carriers traveling through the depletion region at the drain edge are hence multiplied by the high two-dimensional field. The impact ionization current is manifested as an

244

6 Analog/RF CMOS Drain to gate field

Gate, VG = VFB

Gate VD

Depleted n-region

tox

tox

tSi

N+-region

N+-region VD > 0 Planar field

Corner field

P-body

Body at ground (a)

(b)

Fig. 6.18 Junction field configuration with gate and body grounded. (a) Corner and planar fields. (b) High-field path length in Si, tSi

increase in drain and bulk currents IB (or Isub). The multiplication factor M is given by (Chap. 3) M¼

1 R tSi 1  0 αi ðEÞdx

ð6:27Þ

where αi(E) is the field-dependent ionization rate. Avalanche breakdown occurs at the critical field, Ec, where the integral in the denominator of (6.27) approaches unity and the multiplication factor M tends to infinity. The critical field increases with increasing dopant concentration [24, 25]. Using Fig. 3.26 and (3.38), it is approximated as Ec ffi 5.4  105 V/cm for N ¼ 1017 cm3, and Ec ffi 6.5  105 V/cm for ND ¼ 5  1017 cm3. An ionization rate αi  1.5  105 cm1 can be approximated for electrons and holes along tsi, giving an estimated path length in silicon of tSi  65 nm at the breakdown field. The breakdown voltage is then approximated as the sum of voltages across tox and tSi. For tox ¼ 15 nm, we get BV  jEox j  t ox þ jESi j  t Si  5:9 V This can be compared to the breakdown voltage BV  11 V obtained for an isolated N+P drain junction having a background concentration NA ¼ 1017 cm3 and a junction depth xj ¼ 300 nm. Detailed analysis and experimental results show that for low to moderate concentrations NA in the P-region and tox xd, the junction breakdown voltage depends linearly on (VD  VG) and is practically independent of NA and xj for a wide range of background concentrations and curvatures [21, 26]. For a given VD, a positive VG or positive oxide charge reduces (VD  VG) and creates a depletion region at the surface of the P-region. This decreases the field at the drain edge, increasing the breakdown voltage. In the limit, the breakdown voltage reaches the value of the planar junction

6.3 MOSFETs and CMOS

245

breakdown. Similarly, a negative gate voltage or negative oxide charge reduces the breakdown voltage. Analog MOSFETs typically require high breakdown voltages which cannot be met with conventional digital MOSFET configurations (Chap. 7). Band-to-Band Tunneling The integral in (6.27) depends on both the ionization rate and the path length. As the drain concentration increases, the depletion width in the gate-overlapped region decreases. This reduces the path length and hence the probability for impact ionization, while the probability of band-to-band tunneling increases. The mechanism is similar to tunneling in a Zener diode discussed in Chap. 3. For band-to-band tunneling to occur in silicon, the field must be higher than ~106 V/cm, and band bending must exceed the energy gap of ~1.12 eV [27–29]. The band diagrams in Fig. 6.19 illustrate the generation of electron–hole pairs by tunneling in a heavily doped, gate-overlapped N- or P-region. As ψ s increases above 1.12 V, the valence band and conduction band overlap on the energy scale, so that filled states and empty states appear opposite each other, separated by the thin depletion region, allowing electrons to tunnel directly from the valence band to the conduction band. The tunneling current density follows the relation [27–29] jT ¼ AESi eB=ESi A=cm2

ð6:28Þ

where A ffi 2.5  103 A/V cm, B ¼ 27.3 MV/cm, and ESi is the field in silicon at the oxide–drain interface. ESi depends on the drain-to-gate voltage, VDG, and on the doping concentration in the region where tunneling occurs. The field can be approximated under similar assumptions as for impact ionization. The following approximation is obtained for non-zero workfunction difference and effective oxide charge [27]

N+ poly gate Tunneling electron

N+-silicon qVox

Generated hole

y s ≥ 1.2 V Generated hole

Tunneling electron

P+ poly gate P+-silicon

Fig. 6.19 Energy band diagrams illustrating band-to-band tunneling in silicon in the overlapped N+- and P+-regions. Generated holes drift to the substrate [27]

246

6 Analog/RF CMOS

V DG  V FB ¼ V ox þ ψ s  V ox þ 1:2  Eox t ox þ 1:12 V

ð6:29Þ

where VFB is the flatband voltage and Eox ffi 3ESi. For VFB ffi 0, the above equation simplifies to [27] ESi  ðV DG  1:2Þ=3tox V=cm

ð6:30Þ

The gate-induced tunneling current increases as the oxide thickness is reduced and the dopant concentration in the gate-overlapped drain increased. It is important to control this current component in leakage-sensitive applications. Leakage at the STI Boundary Oxide-filled shallow-trench isolation, STI, is the preferred choice for device isolation in submicron technologies (Chap. 9). The STI thickness and shape, and the doping profiles in the active region near the STI boundaries are most critical to the proper operation of MOSFETs. The STI oxide thickness typically ranges from 0.2 to 0.6 μm, and its sidewalls are typically vertical. Of special importance are the shape of the STI edge and corner and the impact of a so-called divot (Fig. 6.20). The divot is caused by stress-enhanced oxide etch-rate near the corner, resulting in the poly gate wrapping around the edges. Stress can cause the gate oxide to thin at corners, increasing the oxide field and causing an increase in drain-to-gate leakage, or even oxide rupture. One of the potential problems with very thin gate oxide is boron penetration from the PMOS gate into the oxide and silicon. Incorporating small amounts of nitrogen into the oxide is found to inhibit boron penetration [30–33]. The modified gate dielectric is referred to as nitrided oxide (NO) (Chap. 9). Thinning of the oxide or reduced nitrogen content at STI corners can, however, result in boron penetration causing drain-to-source leakage along STI edges in PMOS. NO can, however, lead Fig. 6.20 Enhanced oxide field at the STI corner caused by gate oxide thinning and divot

Oxide thinning at corner

W Gate

STI oxide

Divot

Gate oxide Bulk

Depletion boundary

6.3 MOSFETs and CMOS

247

to increased 1/f noise which is detrimental to most analog/RF applications (Chap. 10). (c) Subthreshold Characteristics The approximation of zero-carrier charge within the depletion region under the gate was made to simplify the analysis of field distribution under the gate for VG  VT. This approximation was justified because, while the electron concentration increases exponentially with increasing surface potential ψ s, it remains negligible compared to the charge of ionized impurities, Qb. The inversion electron charge and the drain-tosource current, however, do not drop abruptly to zero at threshold. The drain current has a finite value at VG ¼ VT that decreases exponentially when VG is reduced below VT. On a log-linear scale, the characteristic is nearly linear with a slope inversely proportional to kT/q. In this region, the MOSFET is said to operate in the subthreshold mode (Fig. 6.21). A MOSFET operating in the subthreshold mode is similar to a bipolar transistor operating in the active mode. In an NMOS, the gate voltage increases the surface potential by capacitive coupling, reducing the barrier at the source edge, and locally forward biasing the source-to-bulk junction. When the interface-state density is negligible (the typical case), the relation between ψ s and VG near the source is (Fig. 6.22) ψ s  ½Cox =ðC ox þ CSi Þ V G ¼ V G =n V

ð6:31Þ

where CSi is the silicon capacitance at the source edge and n is sometimes referred to as the ideality factor defined here as

Fig. 6.21 Subthreshold characteristic for longchannel NMOS defining subthreshold slope, VT at constant current, and off – current . Ioff-1, projected from slope; Ioff-2, increased by other leakage components

10-02

Above Threshold

10-04 Subthreshold 10-06

ID0 ª (150 nA) W/L

10-08 10-10

2S

Ioff-1

VG Log I D

(S = 60-100 mV/decade)

10-12 Ioff-2

Slope S

10-14 VT at ID0 10-16

0

0.5

1.0 VG (V)

1.5

2.0

248

6 Analog/RF CMOS

Fig. 6.22 Relation between surface potential and gate voltage

Gate at VG Surface potential, y S

Cox CSi

N+-Source at ground Depletion

P-body at ground

n ¼ ðCox þ C Si Þ=Cox

ð6:32aÞ

When the impact of interface state density of charge Qit per unit area cannot be neglected, n increases to n ¼ ðCox þ C Si þ Cit Þ=Cox

ð6:32bÞ

where Cit is the capacitance associated with charging and discharging interface states. The factor n typically ranges from 1 to 1.6. It varies slightly with surface potential, mainly because of the dependence of CSi on ψ s. While this variation is small, it should be taken into account in analog designs. The gate voltage controls minority-carrier injection near the source. The injection mechanism is identical to that of a PN junction in forward bias discussed in Chap. 3. Since the source is heavily doped, the injection of holes into the source can be neglected. The concentration of excess minority carriers in the channel near the source increases exponentially with increasing surface potential, following the Boltzmann approximation ns0 ¼ np0 eqψ s =kT cm3

ð6:33Þ

ns0 is the electron surface concentration near the source, and np0 is the equilibrium concentration of minority electrons in the P-region. At the drain, a distance L from the source, the electron concentration is nsL ¼ np0 eqðψ s V D Þ=kT cm3

ð6:34Þ

For VD > ffi 3kT/q, nsL becomes negligible. Thus, the gradient in electron concentration becomes independent of the drain voltage, expressed as dn=dy ¼ ns0 =L ¼ np eqψ s =kT =L cm4

ð6:35Þ

Since in weak inversion the densities of electrons and holes are negligible compared to the ionized impurity concentration, the electric field at the surface is

6.3 MOSFETs and CMOS

249

not appreciably affected by the presence of free carriers. Under these conditions, the electric field parallel to the surface under the gate is negligibly small over most of the channel, independent of the drain voltage. Therefore, the drift current is negligible and the diffusion current dominates, approximated by ID  I0

W eff qðV G V T Þ=nkT e ¼ I D0 eqðV G V T Þ=nkT A Leff

ð6:36Þ

where I0 (Weff/Leff) is the current at which VT is measured and I0 typically ranges from 100 to 500 nA, depending on the channel doping concentration. The subthreshold current thus decreases with decreasing gate voltage below VT, with a slope S ¼ nkT/q  ln10 (Fig. 6.21). It is expressed in V/decade of ID. The current at VG ¼ 0 is referred to as the off-current. In Fig. 6.21, a distinction is made between the projected off-current from VT and S, Ioff-1, and the measured current that includes leakage components, Ioff-2. The temperature dependences of subthreshold slope and threshold voltage can be extracted from measurements similar to those shown in Fig. 6.23 [34]. It can be seen that, with decreasing temperature, S decreases while VT increases. A detailed analysis of (6.16) shows that VT increases almost linearly with decreasing temperature (Fig. 6.24). As the temperature is increased, the current at VT, ID0, decreases because of the degradation of mobility [35]. The transconductance in the subthreshold mode is found by differentiating (6.36) as gm ¼ dI D =dV G ¼ qI D =nkT S

ð6:37Þ

Assuming a constant ideality factor n, the ratio gm/ID should be constant, independent of ID. There is, however, a small variation in gm with ID mainly because n is not strictly constant. Example 6.4 Find the threshold voltage that will limit Ioff to 1 fA/μm in an NMOS with L ¼ 5 μm. Assume 25  C, an ideality factor n ¼ 1.5, and a constant current at threshold ID0 ¼ 150 nA  W/L. Solution For W ¼ 1 μm and L ¼ 5 μm, ID0 ¼ 30 nA. Taking the ratio Ioff/ID0 in (6.36) gives for VG ¼ 0 I D =I D0 ¼ I off =I D0  e qV T =nkT  3:34  108 Taking the logarithms and rearranging gives V T  n


 kT  ln 3:34  108 ffi 1:5  0:0257  17:3 ffi 0:667 V q

250 10-04

10-06

ID (A)

Fig. 6.23 Temperature dependence of the ID  VG characteristics of longchannel NMOS in subthreshold and above threshold [34]

6 Analog/RF CMOS

10-08 T (K)=298

250 200 150 100

77

Long-channel MOSFET L = 9 m; W/L = 9.7 VD = 0.1 V; VB = 0

10-10

10-12 -0.2

0.0

0.2

0.4

0.6

0.8

1.0

VG (V)

0.75

Threshold Voltage, VT (V)

Fig. 6.24 Temperature dependence of VT. For the structure shown VT decreases by ~1.27 mV/  C from 40 to +150  C

NMOS, N+ poly-gate P-well NA = 1.6×1017 cm-3 teq = 13.5 nm Qeff = +1011q cm-2

0.70 0.65 0.60 0.55 0.50 0.45 -40 -20

-0

20

40

60

80 100 120 140

Temperature (oC)

(d) Moderate Inversion, Onset of Strong Inversion The region between weak and strong inversion is referred to as moderate inversion [36]. As the gate voltage is increased above VT, the inversion-carrier concentration increases to the point where the inversion layer constitutes a path along which, for a given drain voltage, the field from drain to source and hence the drift current component become appreciable. The moderate inversion region is a region where both drift and diffusion currents must be taken into account, with neither mechanism dominating. It can extend about 100 mV below and above VT where the onset of strong inversion occurs [37]. While this region is not of particular importance to digital applications, it becomes increasingly important to analog designs, especially because many analog circuits requiring high gm operate in this region. Several analytical curve-fitting models have been developed to more accurately describe

6.3 MOSFETs and CMOS

251

the moderate inversion region with varying degrees of complexity [36–39]. The comparison of models is, however, out of the scope of this chapter. (e) Strong Inversion In strong inversion, the drift component dominates. For a long channel and a small drain voltage, the inversion layer can be treated as a variable resistor controlled only by the gate. With the simplifying assumptions for Qn and Qb made earlier, the inversion charge density can be approximated as Qn ¼ ðV G  V T ÞC ox C=cm2

ð6:38Þ

Linear Mode, Small VD For a very small drain voltage, VD  50 mV, the inversion layer can be approximated as a uniform charge-sheet connecting source to drain. Assuming a constant effective surface mobility for electrons, μeff, the inversion layer sheet resistance is RS-inv ¼ 1=ðμeff Qn Þ Ω=□

ð6:39Þ

The channel resistance is then Rch ¼ ðLeff =W eff Þð1=μeff Qn Þ Ω

ð6:40Þ

Using (6.38) gives the drain current for small VD as I D ¼ ðV D =Rch Þ ffi ðW eff =Leff Þμeff Cox ðV G  V T ÞV D A

ð6:41Þ

According to (6.41), ID should increase linearly with VD for a constant VG and linearly with VG for a constant VD. The MOSFET is therefore said to operate in the linear mode. The characteristic is, however, not strictly linear (Fig. 6.25a). The departure from linearity as the gate voltage is increased is mainly due to the degradation of the effective mobility and transconductance, as discussed in the next sections. Also, as VD increases, Qn is reduced at the drain boundary. This is because the gate overdrive at the drain boundary is reduced by VD, and the reverse drain-tobulk voltage increases the local threshold voltage at the drain, an effect known as the body-biased effect described later. This effect can be neglected for very small VD. The gate overdrive is (VG  VT) at the source and [VG  (VT + VD)] at the drain. For a small VD, an average gate overdrive [VG  (VT + VD/2)] can be assumed. This gives a better approximation of the current in the linear mode as   W eff VD VD A VG  VT  I D ffi μeff Cox Leff 2

ð6:42Þ

252

6 Analog/RF CMOS 70 200

Maximum slope

60

gm (mS/mm)

ID (mA)

50 40 30

20 VG = VT + VD /2

10 0

150

L = 0.6 mm, |VD|= 0.1V, tox= 12.5 nm, 300K

100

NMOS, P-well 17 -3 NA» 1.5x10 cm

PMOS, N-well 17 -3 ND »1.2x10 cm

50 0

0

(a)

0.5 VG

1.0 (V)

1.5

0

(b)

1

2

3 |VG| (V)

4

5

Fig. 6.25 (a) NMOS in “linear” mode. VT extracted from gate voltage axis intercept (ID ¼ 0) of the linear extrapolation of the ID  VG curve at its maximum slope. (b) NMOS and PMOS transconductance in subthreshold, degradation of gm above VT

Linear Conductance and Transconductance The linear conductance is gdlin ¼

 ∂I D  W eff ffi μ C ox ðV G  V T Þ S ∂V D V G ¼Const Leff eff

ð6:43Þ

The linear transconductance is given by gmlin ¼

 ∂I D  W eff ffi μ Cox V D S ∂V G V D ¼Const Leff eff

ð6:44Þ

The dependence of linear transconductance per unit width on gate voltage is shown in Fig. 6.25b. In the subthreshold region, gm increases almost linearly with ID according to (6.37). The transconductance then reaches a maximum near VT after which it decreases rapidly because of mobility degradation and the presence of extrinsic resistances, as discussed later. Linear Extraction of VT A common method to measure the threshold voltage is shown in Fig. 6.25a, where VT is extracted from the gate voltage axis intercept (ID ¼ 0) of the linear extrapolation of the ID  VG curve at its maximum slope, i.e., the point of maximum transconductance. Effective Mobility Inversion carriers are confined to a very thin surface layer of about 10 nm thick where quantization effects become important, particularly at high surface fields. As a result of confinement, carriers are subjected to additional scattering mechanisms near the surface to those in the bulk. Therefore, the mobility is expected to be smaller at the surface than in the bulk and to decrease with increasing electric field (Fig. 6.25b). Experimental results show that, for the same impurity concentration and

6.3 MOSFETs and CMOS

253

temperature, the inversion-carrier mobility is two to three times smaller at the surface than in the bulk [35]. An effective surface mobility, μeff, was introduced in the preceding sections to account for the dependence of mobility on the surface field. Several theories and models have been suggested to describe the surface mobility [40–45]. The effective mobility depends on lattice scattering, ionized-impurity scattering, and additional surface scattering such as increased acoustical and optical phonon scattering [46, 47], surface roughness scattering [48], and interface charge scattering [49]. Because of the complexity of scattering mechanisms, however, no simple relationship has been found for the dependence of μeff on electric field that is applicable to all MOSFET conditions. Therefore, the dependence of mobility on surface field is best obtained from measured ID  VG data and by combining the results with well-established values of inversion layer charge [49]. The purpose of this section is not to compare the theories but to highlight the relationships between μeff and vertical field, temperature, and process conditions. The effect of lateral field on mobility is neglected here since for long channels the lateral field is small and, for a given vertical field, the mobility can be assumed to be constant along most of the surface. At a given temperature, the mobility for a thermally oxidized surface has a unique dependence on vertical field, independent of oxide thickness, as shown for a longand wide-channel MOSFET above threshold in Fig. 6.26 [13]. The surface mobility decreases with increasing temperature because of the increased lattice scattering. The plots in the figure are referred to as universal mobility curves and used as benchmarks to compare mobility enhancements or degradations when new structures and materials are introduced. The effective vertical field is averaged over the electron distribution and is given by (6.18b). An expression for the dependence of mobility on effective vertical field is of the form [13] μeff ¼

μ0

1 þ ½αðEeff  Eref Þ β

cm2 =Vs

ð6:45Þ

where Eref and μ0 are, respectively, the effective field and surface mobility for Qn  0 and α, β are constants to be extracted from measurements. Empirical equations for the dependence of effective surface electron and hole mobility on VG, VT, and tox are given in [50] as μn-eff 

1þ

μp-eff 

630

h

1 0:75106

1þ

h

2

i1:67 cm =Vs

ð6:46aÞ

i cm2 =Vs

ð6:46bÞ

V G þV T 6t ox

185 V G þ1:5V T 3:38106 t ox

where tox is in cm. The above equations are based on (6.18b).

254

6 Analog/RF CMOS 700 Inversion carrier mobility (cm2/Vs)

Fig. 6.26 Universal inversion layer mobility plots for electrons [13] and holes [14]

Lateral field: E y VDsat, the pinch-off point P (where VP ¼ VG  VT) moves from the drain edge toward the source (Fig. 6.28). The voltage between P and source is VG  VT, and the voltage between drain and P is VD  (VG  VT). The distance δL between P and drain can be obtained by making a step-junction approximation for the pinchoff region as

256

6 Analog/RF CMOS

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ε0 εSi ½V D  ðV G  V T Þ

cm δL ffi qN A

ð6:50Þ

The channel between source and P can be treated as a resistor of effective length L0 ¼ L  δL having a varying sheet resistance (varying Qn) along the surface. For a long channel, the lateral field in the channel is small. Inversion electrons therefore drift from source to P at approximately constant mobility, μeff. The pinched-off section δL is a region of high field at which electrons drift at velocity saturation vsat  107 cm/s. At any point y of the channel, the drain current is I D ¼ WQn ðyÞvn ðyÞ A

ð6:51Þ

where vn( y) is the electron drift velocity in the y-direction at a position y of the channel. Between source and P, the drift velocity is vn ðyÞ ¼ μeff Ey ¼ μeff

∂V ðyÞ cm=s dy

ð6:52Þ

Since ID is the same crossing any plane normal to the channel and Qn decreases from source to drain, vn( y) must increase from source to drain. At the pinch-off point P, Qn becomes small but does not strictly go to zero. Instead, it must have a finite value at P, obtained from (6.52) as Qn ðL0 Þ ¼ I D =ðWvsat Þ C=cm2

VG > VT

y

x

ð6:53Þ

A ID VD > (VG-VT)

Gate

Drain

Source

L’ Channel Body

dL Pinch-off point, P

Fig. 6.28 Exaggerated channel cross section illustrating the displacement of the pinch-off point P along the channel toward the source for VG > VT and VD > VG  VT. The potential at P is VG  VT

6.3 MOSFETs and CMOS

257

Saturation Conductance and Transconductance According to (6.49), the drain current in saturation should be independent of drain voltage, and the conductance, gd, should ideally be zero and ro tending to infinity, i.e., the slope in the ID  VD characteristics should be zero in saturation. This appears to be almost the case for long channels. There is, however, a finite increase in drain current due to channel length modulation. This increase results in a non-zero conductance and hence finite output resistance, ro. The product gmro (or the ratio gm/gd) is the intrinsic gain of the transistor. In analog designs, where linearity is very important, it should be kept as high as possible (Sect. 6.5). High gain means less gain stages required in the circuit, simplifying the design. For a given gate voltage, the slope is conveniently described at any point of the output by the intercept of the extended ID  VD characteristic with the VD axis, as shown in Fig. 6.29. This intercept is referred to as the Early voltage, VA. It is approximated from  ∂I D  1 I 0D   ¼ ¼ S gd ¼ dV D V G r o V 0D  þ jV A j
   jV A j ¼ I 0D =gd  V 0D  V

ð6:54aÞ ð6:54bÞ

I 0D , V 0D are, respectively, the drain current and drain voltage at the point where the slope is taken. As Leff is reduced, gd increases; hence, |VA| decreases. Combining (6.49) and (6.50) for an NMOS and assuming a uniform channel concentration, NA, gives an approximate expression for ro in saturation as   sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2Leff δL 2 qN A ½V D  ðV G  V T Þ

Ω ro ffi 1 I Dsat Leff 2εo εSi

ð6:55Þ

Short channel modulation Linear region

ID (mA/mm)

600

VA

VG = 2.5

500

400

2.0

Long channel behavior ID’

300 200

1.5

100 0

1.0 0

0.5

1

1.5

2 VD’ 2.5

VD (V)

Fig. 6.29 Comparison of channel length modulation in long- and short-channel NMOS. VA is the Early voltage

258

6 Analog/RF CMOS

where IDsat is the drain current at the onset of saturation (where δL ¼ 0). From (6.55) we can conclude that ro falls rapidly in short channels where δL becomes a large fraction of Leff. Also, ro is proportional to L2eff because IDsat is inversely proportional to Leff. Measured conductance plots are shown in Figs. 6.30. The conductance drops with increasing drain voltage and flattens when VD reaches VDsat. As expected, the NMOS output resistance in Figs. 6.30b is considerably lower (in the kΩ range) than in Fig. 6.30a (in the MΩ range) due to the shorter channel length. Also, the PMOS output resistance in Fig. 6.30c is about three times larger than that of the NMOS because of the lower mobility. 3.0×10-4 NMOS, W/L = 5/5, 65-nm technology, 300 K 2.5×10-4 VG = 2.5 V

10-4

2.0×10-4 10-5

VG = 2.0 V VG=1.5 V

1.5×10-4 1.0×10-4

10-6

Drain current, ID (A)

Drain conductance, gD (S)

(a) 10-3

0.5×10-4 VG = 1.0 V

0.5

0 2.5

1.0 1.5 2.0 Drain voltage, VD (V)

(b) 10-1

6×10-3

NMOS: W/L = 10/0.09, tox =2 nm, 300 K Drain conductance, g D (S)

VG=1.2 V VG=1.2 V

10-2

4×10-3

1.0 V 1.0 V

0.8 V

10-3

5×10-3

3×10-3

0.6 V 0.4 V

0.8 V

2×10-3

10-4

Drain current, ID (A)

10-7 0

1×10-3 0.6 V 0.4 V

10-5

0

0.2

0.4 0.6 0.8 Drain voltage, VD (V)

1.0

0

1.2

Fig. 6.30 Drain current (solid line) and drain conductance (dashed line). (a) NMOS 65-nm, technology. (b) NMOS 90-nm technology

6.3 MOSFETs and CMOS

3×10-3

PMOS: W/L = 10/0.09, tox =2 nm, 300 K VG=1.2 V

10-2 VG=1.2 V

2×10-3

1.0 V 0.8V

10-3

1.0 V

0.6 V

1×10-3

0.4 V

10-4

0.8 V 0.6 V

0.4 V

10-5 0

0.2

0.4 0.6 0.8 Drain voltage, VD (V)

Drain current, ID (A)

Drain conductance, gD (S)

(c) 10-1

259

1.0

0 1.2

Fig. 6.30 (c) PMOS 90-nm technology

The transconductance in saturation, gmsat, is defined as gmsat

∂I D W eff ¼ ¼ μ C ox ðV G  V T-drain Þ ¼ ∂V G Leff eff

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2W eff C ox μeff I D S Leff

ð6:56Þ

A comparison with the bipolar transconductance in (5.26) of approximately the same area and current shows that the MOSFET transconductance is nearly one order of magnitude lower than the BJT value. Example 6.5 In a MOSFET Cox  μeff ¼ 4  105, Weff/Leff ¼ 10, and ID ¼ 100 μA. Find gmsat and compare this value with that of a BJT at the same current level. Assume T ¼ 298 K. Solution From (6.56), we find the MOSFET transconductance as rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2W eff Cox μeff I D ¼ 2  10  4  105  104 ffi 0:283 mS gmsat ¼ Leff The BJT transconductance is found from (5.26) as
 gmsat ¼ qI C =kT ffi 104 = 8:62  105  298 ffi 3:89 mS

260

6 Analog/RF CMOS

Body-Bias Effect When a voltage, VB, is applied between source and bulk, the maximum bulk charge changes from (6.15) to Q0bmax ¼ 

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ε0 εSi qN A ð2ϕb  V B Þ C=cm2

ð6:57aÞ

and the threshold voltage relation in (6.16) is written as VT ¼ 

Q0bmax þ V FB þ 2ϕb V C ox

ð6:57bÞ

For an NMOS, a negativeVB (reverse bias) increases VT, while a positive VB (forward bias) decreases VT. The sensitivity of VT to body bias is found by differentiating (6.54b) with respect to VB. For uniform NA we get dV T dQ 1 ¼ C ox b ¼ dV B dV B 2Cox

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ε0 εSi qN A 2ϕb  V B

ð6:58Þ

It follows that the sensitivity can be reduced by decreasing NA and increasing the reverse bias. Circuit applications in which the MOSFET source-to-body junction is reverse biased or slightly forward biased are common. For example, the body-biased effect can be utilized to locally adjust VT by applying an appropriate reverse voltage, VR, to increase VT or a forward voltage, VF, to decrease VT. In forward bias, however, the forward current, IF, must be limited to a value that is acceptable for the specific application. IF is typically negligible for VF  0.4 V. A higher forward voltage can trigger destructive snapback in a MOSFET or latch-up in a circuit (Chap. 11). Intrinsic and Extrinsic Resistances The resistance of the channel Rch defined by (6.40) is referred to as the intrinsic resistance. Resistances in series with the channel, including source, drain, and contact resistances, are extrinsic. Figure 6.31 is a schematic of current contours, showing the main extrinsic resistance components on the source side of a typical structure. Similar resistance components are found on the drain side. For long channels and symmetrically arranged source and drain, they are assumed to be the same as for the source side. The arrows on the current lines indicate the direction of electron flow. Because carriers are constrained to flow laterally near the surface, the current lines crowd at several locations of dissimilar conductivities along the current path. Current lines crowd at the stud–silicide interface (RC1), at the silicide–silicon interface (RC2), and at the corner of the inversion layer facing the lightly doped source–drain extension. The latter gives rise to a spreading resistance, Rspr, similar to the resistance of a point contact to silicon [53–56]. Since the inversion layer is very thin, it can be compared

6.3 MOSFETs and CMOS

Gate

261

Spacer

Silicide

Contact stud

RC1

Rspr Rch RLDD

RC2 RS/D

LDD S/D junction

Fig. 6.31 Schematic current contours identifying the main extrinsic resistance components on the source side of an NMOS

to a sharp wedge from which the current lines spread-out into the source–drain extension. The total MOSFET drain-to-source resistance can be approximated as RDS ¼ Rch þ Rext Ω

ð6:59aÞ

where for a symmetrical NMOS in the linear mode Rext ¼ RS þ RD Ω

ð6:59bÞ

where RS and RD are, respectively, the series resistances of the source and drain, including the contact, LDD, and spreading resistances. The impact of extrinsic resistance on MOSFET characteristics can be seen as a reduction in drain voltage, gate overdrive, and transconductance. Let V 0D and V 0G be the externally applied drain and gate voltage. The actual voltages seen at the channel boundaries are V DS ¼ V 0D  I D Rext V

ð6:60aÞ

V GS ¼ V 0G  I D RS V

ð6:60bÞ

The effective gate-to-source voltage is decreased by IDRS. There is also an increase in threshold voltage ΔVT due to the body-biased effect that can be found by substituting (ψ smax + IDRS) for ψ smax in (6.15) and (6.16). As a result, the conductance and transconductance are degraded. Without considering the bodybiased effect, the ratio of intrinsic to effective transconductance becomes gm-eff 1  gm 1 þ gm RS

ð6:61Þ

262

6 Analog/RF CMOS

VD

VG G

A ID

S

A IB

D

B

e STI

N+

N+

Exaggerated pinched-off Impact dL channel ionization

STI

P+

STI

h P-well

P--substrate

Fig. 6.32 Schematic NMOS cross section illustrating the impact ionization at the drain boundary resulting in substrate current

The effects of extrinsic resistances on transistor performance become increasingly important as the channel length is reduced and the channel resistance Rch decreases. This is particularly important when standard NMOS and PMOS are used as power transistors (with large W/L) in analog circuits. Substrate Current In a MOSFET operating in saturation, a fraction of inversion carriers that reach the high-field region between pinch-off and drain can gain enough energy, ϕi, to create electron–hole pairs by impact ionization (Figs. 6.32). For silicon, ϕi is in the range 1.3–1.5 eV. Electrons at this energy are said to be hot. In a simplified model, one can think of a Maxwell distribution of inversion electrons with respect to energy (Fig. 6.33). As the field increases, the distribution moves to higher energy and the fraction of electrons that acquire energy ϕi increases. The impact ionization current constitutes an increase in substrate current and an equal increase in drain current. The energy ϕHCI in Fig. 6.33 is related to the hot-carrier injection (HCI) into the oxide, discussed in Chap. 11. The drain-to-source current is multiplied at the drain edge by a factor M which increases with increasing drain voltage. This is similar to the multiplication found for the emitter current at the collector–based junction of an NPN structure (Chap. 4). Avalanche breakdown occurs when M tends to infinity (6.27). The substrate current increases exponentially with peak electric field and can be approximated by [57]. I B  2I DS eBi =Epeak A

ð6:62Þ

where Epeak depends on (VD  VG) and Bi is extracted from measurement. The substrate current is shown in Fig. 6.34 for two temperatures as a function of VG and different VD [58]. It initially increases with increasing drain current and reaches a maximum after which it drops. The saddle point is located at about VD/2.

6.3 MOSFETs and CMOS

263

Number of electrons (a.u.)

Fig. 6.33 Simple model illustrating the electron distribution at a certain drain field. ϕi is the energy for impact ionization

Maxwell Distribution

fi

f HCI

1 3 2 Electron Energy (eV)

10-04

W = 20 mm, L = 0.5 mm, tox = 7.5 nm

10-05 VD = 3.0V

10-06

Substrate Current (A)

Fig. 6.34 NMOS substrate current versus gate voltage at different drain voltages at 85 and 300 K. (Adapted from [58])

2.5V

10-07 10-08

2.0V 2.0

10-09 10-10 10-11 10-12 85 K 300 K

10-13 10-14 10-15 0

1

2

3

4

5

Gate Voltage (V)

The reason for the drop is that while ID increases with increasing VG, the lateral peak field, determined by [VD  (VG  VT)], decreases. Since IB depends exponentially on Epeak, the net is a decrease in IB. Also, the plots imply that the ratio IB/ID has a very slow dependence on temperature. Reducing the substrate current is of particular importance in analog designs because of the undesirable effects caused by the IR drops in the substrate and P-well, as illustrated in Fig. 6.35. In the example shown in Fig. 6.35, the generated excess majority-carrier holes in adjacent circuits increase the substrate current, Isub. The P-well potential rises as the holes flow to the P-well contact, forward biasing the source-to-bulk junction. Without special precautions, the local forward bias can degrade analog signal integrity by locally reducing the threshold voltage by the body-biased effect. The forward current can also cause voltage snapback in the MOSFET itself (Sect. 6.3.3).

264

6 Analog/RF CMOS

Fig. 6.35 Illustration of voltage drops in the P-substrate and P-well caused by substrate current. The IR drops locally forward-bias the source-tobulk junction

P-well

Source

Gate

Drain

VG

A ID VD

STI

STI

RWell

STI

e +

P- - substrate

P-well

Rsub

e

Isub

There are many noise sources that can affect sensitive analog circuits (Chap.10); substrate noise is one of them. Substrate current caused by impact ionization is one of the most significant contributors to substrate noise [59–61]. In typical analog designs, the bias current are low, in the 10 μA range, and each node in the circuit is defined by a specific bias point. The presence of substrate currents creates an additional current that modifies the bias point of the affected node, disturbing the circuit operation. The substrate current is not only detrimental to analog design but also indicative of potential reliability problems such as latch-up and HCI (Chap. 11). One advantage of operating the NMOS at higher voltage while reducing the substrate current in analog CMOS can be seen from the following simple analysis. In most analog applications, the NMOS is biased at a gate voltage close to VT, in the weak to moderate inversion region, typically at 0.2 V above VT. This is mainly because it is the region of maximum transconductance. The position of this “bias point” with respect to peak Isub depends on the operating drain voltage. For example, for an NMOS with VT ¼ 0.7 V and VD ¼ 5 V, the “bias point” would be at 0.9 V, well below VG ffi VD/2 ¼ 2.5 V at peak Isub. For an NMOS with VT ¼ 0.4 V and VD ¼ 1.8 V, the “bias point” would be at 0.6 V, closer to VG at peak Isub of 0.9 V. For an NMOS with VT ¼ 0.3 V and VD ¼ 1.2 V, the “bias point” would almost coincide with VG at peak Isub, an undesirable condition as discussed above. Placing reverse-biased or grounded N+ and P+ guard rings around sensitive circuits provides them more protection by intercepting the substrate current (Chap. 11).

6.3.2

Analog-Specific MOSFETs

This section describes special analog MOSFETs that can be integrated in a base CMOS technology with little or no added complexity.

6.3 MOSFETs and CMOS

265

(a) Isolated MOSFET Completely isolating a MOSFET is sometimes necessary to protect it from noise and cross talk originating from adjacent circuits or to protect adjacent circuits from noise generated by the MOSFET itself. Complete isolation also allows adjustment of its threshold voltage by selectively applying a small forward bias or reverse bias to the MOSFET body-to-source junction independently of chip substrate. The forward bias reduces VT, allowing operation at lower supply voltage, and also improves shortchannel characteristics [62, 63]. The forward-biased voltage should, however, remain below 0.4 V to limit the forward current and to avoid related parasitic bipolar effects. The reverse bias increases VT and also increases circuit immunity against latch-up and other parasitic bipolar effects. A typical triple-well technique to isolate an NMOS is shown in Fig. 6.36a. The structure, including source, drain, and body, is fully surrounded by a reverse-biased junction consisting of an N-well ring and a deep N-well (or N-buried layer, NBL) which may already be included in the process. Isolating the structure also allows it to be level-shifted while operating internally as a low-voltage MOSFET. For example, in a 60 V BCD technology (Chap. 7), there are situations where an NMOS which is optimized as a 5 V MOSFET should operate from 55 V to 60 V (Fig. 6.36b). By applying 55 V on the source, body, and NBL/Nwell ring isolation, and 60 V on the gate and drain, the MOSFET will operate internally in saturation as a 5 V device, while a reverse bias of 60 V appears at the isolation-to-substrate junction. In this case, it may be necessary to isolate the structure with a highly doped NBL to avoid punch-through between substrate and P-body and to place circuits at a safe distance from the isolated NMOS because of the high reverse voltage between NBL and substrate. Figure 6.36b shows a single isolated NMOS. There are cases, however, where an entire circuit block containing NMOS and PMOS structures requires isolation. This can be done by placing a large common NBL layer under the entire block and surrounding the block with a single N+/N-well ring that merges with the NBL. The NBL or deep N-well region beneath the STI and source–drain regions can pinch the P-body (P-well) and considerably reduce its vertically integrated concentration in those regions, increasing the local sheet resistance. This can become a serious problem in large isolated NMOS structures in the presence of impact ionization at the drain and the resulting debiasing at the source (Fig. 6.47). Thus, optimized placement of the body contacts becomes important. (b) Multiple-VT MOSFETs Figure 6.37 shows the actual and projected nominal power supply voltage and gate overdrive as a function of DRAM half pitch.3 Also shown is the trend in EOT (or teq). The drop in the digital operating voltage and gate overdrive reduces the dynamic range in analog circuits. This can be a problem for some analog designs, particularly because of component noise and mismatch (Chap. 10). One way to 3 The values in the plot are extracted from the International technology Roadmap for Semiconductors, ITRS updates (www.itrs.net). The DRAM half-pitch is a metric for “Technology Generation.”

266

6 Analog/RF CMOS

(a) Viso= 0 V

VG= 5V

VB= 0V

Gate

VB= 0V

ID

A

Viso= 0 V

VD= 5 V STI

STI

STI N+-source

N-well

P-well

STI

P+-contact

N+-drain

STI N-well

Deep N-well or N-buried layer (NBL) P- - substrate at ground

(b) Viso= 55 V

VB= 55V

VG= 60V

Gate

VB= 55 V

ID

A

Viso= 55 V

VD= 60 V STI

STI

STI N-well

N+-source

P-well

N+-drain

STI

P+-contact

STI N-well

Deep N-well or N-buried layer (NBL) P- - substrate at ground Fig. 6.36 (a) Complete isolation of an NMOS by fully surrounding the structure with a reversebiased junction. (b) Isolated NMOS operating as a 5 V device in a 60 V technology

address this problem is to use a combination of multiple gate oxide thicknesses and channel implants, with thicker oxide and higher operating voltage for analog and I/O MOSFETs and thinner oxide for the digital core devices (Chap. 9). Alternatively, low-VT NMOS and PMOS can be built with a VT of magnitude 0.2–0.3 V using the standard MOSFET implants but skipping or modifying the threshold adjustment implant. Isolated low-VT NMOS and PMOS can be built using the same technique. For special applications where Ioff is not critical (Sect. 6.4), a native NMOS, with nearly zero VT, can be used (Fig. 6.38). The term native or natural NMOS is used to identify a near-zero VT NMOS constructed on the initial P-type substrate without modification of its surface concentration, hence without added complexity. The

6.3 MOSFETs and CMOS

267

EOT (nm) 0.9 1.1 1.3 2.0 5.0

2.6

3.0

8.0

13.0

4.5

VDD , VDD - VT (V)

4.0

3.5

VDD

3.0 2.5

180

2.0

1.5 1.0

VDD - VT

130

65 90 32 45

0.5 0

0 22 50

150

100

200

250

300

350

400

450

500

Technology, DRAM Half-Pitch (nm) Fig. 6.37 Reduction in the digital power supply voltage and gate overdrive with technology generation. (Extracted from the International Technology Roadmap for Semiconductors (ITRS))

G S

G D

STI

P-well

B STI

S STI

D P--substrate

B STI

STI

P--substrate

Standard NMOS

Native NMOS

Fig. 6.38 Schematic cross section of standard and native NMOS on P-substrate. The P-well implant is blocked from the native NMOS

native NMOS just skips the implantation steps for P-well, punch-through stop, and threshold voltage adjustment. The main disadvantage of a native NMOS is the larger size due to the longer channel required to avoid punch-through between source and drain and the wider channel to achieve the desired transconductance. In addition, when constructed on a high-resistivity substrate, isolating the transistor may not be possible with existing layers because of punch-through between drain and deep N-well or NBL (Fig. 6.36a). Because the substrate is typically lightly doped, native MOSFETs are expected to exhibit strong short-channel effects (Sect. 6.3.3). The punch-throughlimited channel length can be approximated as

268

6 Analog/RF CMOS

Leff  3:6  107

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

jV R j þ 0:85=N A þ 0:85=N A μm

ð6:63Þ

Thus, for a substrate concentration of 5.5  1015 cm3, the minimum channel length of a 5.5 V native NMOS should be around 1.7 μm. (c) Buried-Channel PMOS and Depletion-Mode NMOS Buried-channel and depletion-mode MOSFETs are similar inasmuch as they contain a buried layer under the silicon surface which is doped with the same polarities as source and drain. A MOSFET with a buried channel can be made normally off or normally on, depending on the gate workfunction, the channel doping, and depth of the buried-channel layer. A buried-channel MOSFET is designed to be normally off, while the depletion-mode MOSFET is designed to be normally on. This section focuses on enhancement-mode buried-channel PMOS (BC PMOS) and depletionmode NMOS (DMNMOS). The discussion is equally applicable to buried-channel NMOS and a depletion-mode PMOS. Buried-Channel PMOS Figure 6.39 compares the standard surface-channel PMOS to a buried-channel PMOS. The most significant advantage of buried-channel over surface-channel MOSFETs is the reduced low-frequency noise (Chap. 10). This is because in a buried channel, carriers flow deeper in silicon, away from the surface where interface states and traps cause most of the noise. Other advantages are the higher carrier mobility and, in some CMOS technologies, process simplification. A buried-channel PMOS is formed by implanting a thin and shallow buried boron layer and by changing the polarity of the gate from P+-poly to N+-poly. This is typically achieved by doping both the NMOS and PMOS polysilicon gates with arsenic/phosphorus prior to patterning the gate, thus reducing the PMOS gate work function by about 1.12 V below that of a P+-gate. By proper choice of the boron dose and energy, the buried channel can be designed to be fully depleted and turned off at VG ¼ 0 due to the workfunction difference between the N+-poly and channel surface. One advantage of a single workfunction gate for both NMOS and PMOS is reducing the number of masking and implantation steps. Another advantage is that the N+-poly gate can be independently doped at a very high dose which would otherwise increase the NMOS source–drain junction depth and lateral extent. Since the concentration in the N+-poly gate is very high, the

P+

P+-gate

N+-gate

P+

N+

P+ STI

N-well Surface-channel PMOS

P+ N-well

P+ STI Buried boron layer

Buried-channel PMOS

Fig. 6.39 Comparison of buried-channel to surface-channel PMOS

6.3 MOSFETs and CMOS

269

gate remains N+-doped after implanting the PMOS source–drain (which also goes into the polysilicon). The junction between the buried channel and N-well is characterized by a junction depth xjbp and a built-in voltage associated with depletion widths xdp in the P-layer and xdn in the N-well. For simplicity, the N-well is held at ground. The buried-channel PMOS is shown at flatband in Fig. 6.40a and at the onset of turnon in Fig. 6.40b where the surface depletion xds just merges with the depletion layer, xdp. In Fig. 6.40c, a conducting layer of the buried layer just begins to form. As with the surface-channel, the PMOS is “off” when VG ¼ 0. The ID  VG and ID  VD characteristics are similar. The gate voltage where the depletion regions xds and xdp just merge is defined as the threshold voltage VT. As VG becomes more negative, xds shrinks, increasing the thickness and hence the conductance of the buried layer. When xds drops to zero, the full buried layer above xdp becomes conductive. The voltage at this point is the flatband voltage VFB. For VG  VFB < 0, the surface becomes accumulated with holes, increasing surface conduction in parallel to buried layer conduction. For a long and wide channel, the threshold voltage is

Oxide xjbn (a)

Buried P-layer at flatband, p = NA at surface xdn xdp P -well N+-gate

(b)

STI

P+-source

xjbn-xds Conducting P+-drain STI xdn xdp

N-well VG @ VT

A ID

N+-gate xds P+-source (c)

STI

VD

Depleted

xdn xdp

P+-drain

STI

N-well Fig. 6.40 Surface conditions of the buried-channel PMOS. (a) Flatband. (b) Turn-off, onset of turn-on. (c) Initial conduction

270

6 Analog/RF CMOS

VT 

Qb Q þ ψ SðV T Þ þ ϕms  eff V Cox C ox

ð6:64Þ

where
 Qb ¼ qN A x jbp  xdp C=cm2

ð6:65Þ

2 qN A
x jbp  xdp V 2ε0 εSi

ð6:66Þ

ψ Sð V T Þ ¼

Example 6.6 The following assumptions are made for simplicity: Long and wide buriedchannel PMOS; uniform buried-channel concentration NA ¼ 5  1016 cm3; buried-channel junction depth xjbp ¼ 0.12 μm; N-well concentration at junction ND ¼ 5  1016 cm3; EOT or teq ¼ 12.5 nm; degenerately doped N+-poly gate; temperature 25  C. Estimate (a) The threshold voltage (b) The subthreshold slope Solution (a) Threshold voltage The built-in voltage at the buried channel to P-well junction is V bi ¼

kT NAND ln ¼ 0:78 V q n2i

where ni  1.3  1010 cm3 (2.8). A step-junction approximation gives xdp as xdp

1 ¼ 2

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ε0 εSi V bi N A þ N D ¼ 7:11  106 cm q NAND

Thus, at threshold, the field-induced depletion width xds ¼ xjbp  xdp ¼ 1.2  105  7.113  106 ¼ 4.887  106 cm. The surface potential and bulk charge at that point are, respectively, ψS ¼

qN A 2 x ¼ 0:092 V 2ε0 εSi ds

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi and Qb ¼ 2ε0 εSi qN A ψ S ¼ 3:91  108 C=cm2 : Assuming Eg ¼ 1.12 eV, and for

is

6.3 MOSFETs and CMOS

271

ϕb ¼

kT N D  0:39 V ln ni q

the workfunction difference between poly and buried N-layer is ϕms ¼

Eg þ ϕb  0:54 þ 0:39 ¼ 0:93 V 2

The oxide capacitance is ε0 εox  2:8  107 F=cm2 t eq Thus, the threshold voltage is C ox ¼

VT 

Qb Q þ ψ S  ϕms  eff ¼ 0:755 V C ox C ox

(b) Subthreshold slope In the absence of interface states, the ideality factor is n ¼ ðCox þ C Si Þ=Cox The silicon capacitance at turn-on is approximated as C Si ¼

ε0 εSi 8:86  1014  11:7 ¼  8:65  108 F=cm2 xj 1:2  105

giving an ideality factor of about 1.31 and a subthreshold slope about 79 mV/ decade. Depletion-Mode NMOS A depletion-mode NMOS (DMNMOS) conducts at VG ¼ 0. It is constructed by implanting an N-layer into the channel such that, with the N+-poly gate at ground, the channel is almost fully conducting. The channel can be fully depleted (turnedoff) with a negative voltage applied to the gate. The negative voltage that just depletes the channel is the threshold voltage, VT. The junction between the buried N-region and the P-well is characterized by a junction depth xjbn and a built-in voltage Vbi associated with depletion widths xdn in the N-layer and xdp in the bulk.

272

6 Analog/RF CMOS

The conduction mechanisms are different for a depletion mode than an enhancement-mode MOSFET [64, 65]. The flatband condition is, when at the surface, n ¼ ND. For an N+-poly gate, this is nearly when VG ¼ 0. The linear drain current at flatband is then I D ffi μeff


 W eff qN D x jbn  xdn V D A Leff

ð6:67Þ

where μeff is the effective electron mobility in the buried layer. For a positive gate voltage above flatband, the channel surface accumulates with electrons. When VG is more negative than VFB, the surface begins to deplete to a depth xds that depends on the surface potential. The net conducting charge is then reduced, and the drain current drops to I D ¼ μn

6.3.3


 W eff qN D x jbn  xdn  xds V D A Leff

ð6:68Þ

Small-Size Effects

In long and wide channels, a one-dimensional analysis can be made under the assumption that the entire channel is under “full control” of the gate. As the channel length and width are reduced, however, a one-dimensional analysis leads to increasingly inaccurate results. Thus, numerical two-dimensional or even three-dimensional analysis is required to accurately describe the MOSFET behavior. In this section, several approximations and simplifying assumptions are made to describe important short- and narrow-channel effects and their relation to device structure and processing conditions. For simplicity, the two effects are discussed separately although they can be interrelated. (a) Short-Channel Effects, SCE The most notable short-channel effects are: (i) The output resistance, ro, decreases due to channel length modulation. (ii) The threshold voltage, VT, becomes more dependent on Leff and VD. (iii) The subthreshold current, Ioff, and subthreshold slope increase; the susceptibility to punch-through increases. (iv) The vertical and lateral fields increase: the mobility degrades, the velocity saturates, and hot-carrier effects become more important. (v) Overlap and fringe capacitances become a larger fraction of gate capacitance. (vi) The extrinsic resistance becomes a larger fraction of source-to-drain resistance. (vii) The flicker noise and mismatch increase (Chap. 10). Because of the above effects, typical analog designs often use longer channels than the minimum allowed by the technology for digital applications.

6.3 MOSFETs and CMOS

273

Output Resistance As the channel length is reduced, the output resistance, ro, decreases because of increased channel-length modulation (CLM) (Fig. 6.30). In analog designs where the product gmro is important, the minimum allowable channel length becomes limited by the desired ro (Sect. 6.5). Dependence of VT on Channel Length and Drain Bias In long channels, the threshold voltages in the linear and saturation modes are practically identical, independent of channel length and drain bias. As Leff is reduced, the linear VT decreases, and the saturation VT decreases further (Fig. 6.41a). There is more VT “roll-off” in the saturation mode than in the linear mode because of the increase in the lateral depletion width as the drain voltage increases. The difference between the saturation and linear VT becomes larger as Leff decreases and VD increases. A simple charge-sharing model to explain the dependence of VT on channel length is illustrated for an NMOS in Fig. 6.41b [66]. A similar model applies to PMOS. In an MOS structure at the onset of strong inversion, neglecting fringe fields, the charge on the gate, QG, is uniformly neutralized by Qbmax. Thus, the total charge on the gate is QGT ¼ Qbmax W eff Leff C

ð6:69Þ

In an NMOS with the MOSFET biased in depletion/inversion, a fraction of the bulk charge Qb in the channel region is neutralized by charges at the source and drain edges. This means that a smaller fraction of Qb is controlled by the gate. The bulk charge associated with the gate can be approximated by a trapezoidal shape, and the total charge on the gate at onset of strong inversion is expressed as Q0GT  Qbmax W eff ðLeff þ L0 Þ=2 C

ð6:70Þ

This charge is smaller than in (6.69). The net result is a reduced threshold voltage. In a long channel NMOS, however, the difference between (6.70) and (6.69) is negligible, so VT is not appreciably affected. Since charge sharing at the drain and 0.7

VT long

Gate

300 K

0.6

Lmet

VT (V)

Linear 0.5

xj N+-source

0.4 0.3

Saturation

(a)

N+-drain

L’

0.2 0.1

xdmax

P-type bulk 0.1

1.0

Leff (mm)

10

(b)

Fig. 6.41 (a) “Roll-off” of NMOS VT with decreasing channel length and increasing drain voltage. (b) Charge-sharing model for “roll-off” of NMOS VT

274

6 Analog/RF CMOS

source boundaries is essentially independent of channel length, the difference between (6.69) and (6.70) increases as the channel length is reduced, causing a decrease in VT. This difference is also found to increase with deeper junctions [67]. While the charge-sharing model describes the dependence of linear VT on channel length with reasonable accuracy, it is not well suited for the saturation mode where two-dimensional (2D) analysis becomes necessary. Approximate analytical solutions have been successfully implemented to describe the MOSFET VT in saturation [68–71]. More accurate results and a better understanding of the dependence of VT on Leff and VD can be obtained from numerical 2D analysis of the MOSFET [72– 74]. Figure 6.42 shows the effect of VD on the barrier as obtained from numerical simulations of an NMOS [74]. The source acts as a “reservoir” of electrons at ground and the drain as a deep potential well. To turn on the NMOS, the gate voltage is increased, lowering the barrier at the source and causing electrons to flow from source to drain. In the long channel, the barrier is flat over most of the channel, and the drain field does not affect the barrier at the source. Any mechanism that reduces the barrier reduces VT. As the channel length is reduced, drain field lines begin to reach the barrier region at the source, sharing with the gate an increasing fraction of Qb, thus lowering the barrier and reducing VT. The threshold voltage decreases because less voltage must be applied to the gate to turn on the MOSFET. This mechanism is referred to as the drain-induced barrier lowering (DIBL) [68–71]. An approximation for VT as a function of channel length is found from curve fitting as V T-short ¼ V T-long  γ ðV D =LÞ V

ð6:71Þ

where γ is an empirical factor extracted from measurements.

Fig. 6.42 Simulation of DIBL in NMOS. Surface electron energy as a function of position for long and short channels [74]

Surface electron energy (eV)

Punch-Through The same mechanism that lowers the threshold voltage causes drain-to-source punch-through. The difference between DIBL and punch-through lies in the role of the gate in barrier lowering. As the channel length is reduced, the threshold

-1 Barrier lowering by drain voltage 0

Vbi

1

Source 2

Drain, L= 0.3 mm

Drain, L= 1.0 mm

3 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

Distance along surface (mm)

2.0

6.3 MOSFETs and CMOS

275

voltage and hence the off-current begin to depend more on VD and less on VG. A point is reached where the barrier is fully controlled by the drain with little contribution from the gate. This is the onset of punch-through. With the source grounded, the onset of punch-through can be approximated as the bias condition where the drain and source depletion regions merge. In a one-dimensional approximation, this is when xdS þ xdD ¼ Leff where xdS and xdD are, respectively, the source and drain lateral depletion widths (Fig. 6.43a). For a uniformly doped body, the punch-through voltage can then be estimated as V PT  L2eff

qN A  2V bi ffi 7:72L2eff N A  ðV biS þ V biD Þ ffi 7:72L2eff N A  1:8 V 2ε0 εSi ð6:72Þ

where Leff is in μm and NA in cm3 and VbiS, VbiD are, respectively, the built-in voltages at the source and drain. In MOSFETs, punch-through typically occurs below the channel, where there is less control by the gate and the doping concentration is lower than near the surface. Figure 6.43b shows two-dimensional contours of equipotential lines and the approximate path of punch-through current. At onset of punch-through, the voltage on the drain begins to directly forward bias the source-to-body junction. The current then increases exponentially with increasing drain bias above punch-through:

Punch-through path N+-source

xdS

N+-drain

xdD

Leff N+-Source

N+-Drain (a)

Equipotential line P-body (b)

Fig. 6.43 Punch-through condition for source at ground. (a) One-dimensional approximation. (b) Equipotential lines and approximate punch-through path

276 Fig. 6.44 Large tilt-angle implant to form “halos” in the MOSFET source and drain boundaries [75]

6 Analog/RF CMOS

Angled boron implant

Gate

N+-source

Spacer

N+-drain Boron halos

Source, drain, and extensions P-bulk

I PT  I PT0 eaqðV D V PT Þ=kT A

ð6:73Þ

where a is a fitting parameter and IPT0 is the drain current at onset of punch-through. The VT roll-off and punch-through are short-channel effects that can be reduced by increasing the doping concentration in the channel region below the surface. This is done, however, at the cost of increasing the overall VT, the body effect, the junction capacitance, and reducing the inversion-carrier mobility. It is the main reason for locally implanting a region having the same dopant polarity as that of the bulk but only at the source and drain edges (Fig. 6.44). This region is referred to as halo or pocket [75, 76]. The higher concentration near the source and drain reduces the spread of the lateral depletion and minimizes short-channel effects while minimizing the impact on the channel properties. Most halo implants encroach into the channel surface, however. This encroachment locally increases the threshold voltage near source and drain and causes a reverse short-channel effect, RSCE, as discussed later in this section. The halo can also have a detrimental effect on the output resistance and Early voltage in analog MOSFETs, even those with long-channel (Fig. 6.45). The effect manifests itself as an increase in ID as VD increases [77]. For small VD, where the lateral depletion region does not extend through the halo, the non-depleted part of the pocket keeps the average threshold voltage at a higher level. As VD increases and the depletion region spreads laterally through the entire pocket, the threshold voltage drops, and the drain current increases, reducing ro and the magnitude of VA. For this reason, the halo implant should be suppressed in analog MOSFETs. Figure 6.46 illustrates the impact of the halo on Early voltage, VA. In the presence of a halo in digital CMOS, there is little increase in the Early voltage as the channel length is increased. In analog MOSFETs without a halo, VA increases almost linearly with increasing channel length.

6.3 MOSFETs and CMOS

277

N+-source Drain

N+-drain

Gate Encroachment

Depletion edge

Drain

Halo P-Well Fig. 6.45 Encroachment of pocket implant. Impact of long-channel early voltage as depletion spreads through the encroached region

1000

Early Voltage, VA (V)

Fig. 6.46 Comparison of Early voltage for analog NMOSFET without halo to digital NMOSFET with halo [78]

Analog 100

Digital

10

1 0.1

1

10

Channel Length, L (mm)

High-Field Effects When the channel length decreases, the gate oxide thickness must be reduced to maintain an adequate control of the inversion layer by the gate. For a given threshold voltage, this necessitates an increase in the channel dopant concentration to suppress short-channel effect, further increasing the electric field and reducing the carrier mobility due to ionized-impurity scattering. An expression for the dependence of drift velocity on lateral field is given by (2.40). A similar expression applies to the drift velocity and mobility of inversion carriers. When the lateral field increases to a level where inversion carriers travel along the full channel at velocity saturation, vsat, the transit time from source to drain can be expressed as τn  Leff =vsat s

ð6:74Þ

278

6 Analog/RF CMOS

When this occurs, the drain current becomes independent of channel length and can be approximated by ID 

 W eff Leff Q  W eff C ox ðV G  V T Þvsat A τ

ð6:75Þ

 is the average inversion charge per unit area. A simple analytical model that where Q combines both the effects of vertical and lateral field on inversion-carrier mobility is not available, so the two effects are treated here independently. Velocity Overshoot When carriers are injected from the source into the channel, they experience an abrupt change in electric field, from near zero within the source, where electrons are “cold,” to an average field in the channel that can exceed 105 V/cm. The carriers “heat-up” in the channel as they are accelerated and gain energy from the lateral field. Whenever carriers travel through an abrupt increase in electric field, they exceed their steady-state drift velocity for a short period of time or for a short distance after which they gradually return to their equilibrium velocity as a result of collisions. The transient increase in velocity above vsat is referred to as velocity overshoot [79–83]. For channel lengths below 0.1 μm, the average velocity can substantially exceed velocity saturation, resulting in higher current than predicted by (6.75). Velocity overshoot near the drain does not improve the drive current. It is the overshoot near the source that improves the current [82, 83]. The velocity of injected carriers from source into the channel becomes the factor limiting the maximum saturated drain current [79]. Voltage Snapback As discussed earlier, inversion carriers are said to be hot when their kinetic energy is sufficiently high to create secondary electron–hole pairs by impact ionization, increasing the substrate current. In long channels, this occurs mostly near the drain at the point of peak field. As the channel length is reduced, the lateral field increases, and inversion carriers reach the drain with higher energy than in long channels, further increasing impact ionization and substrate current. The excess substrate current generated by impact ionization at the drain of an NMOS can cause a significant increase in voltage drop across the well resistance, Rwell, under its source, locally forward biasing the source-to-bulk junction (Fig. 6.47). A fraction of injected electrons diffuses toward the drain where carriers get multiplied by impact ionization. The increase in hole current further increases the local forward voltage resulting in higher injection at the source and so on. Thus, a “regenerative” positive feedback loop is formed and observed as a negative resistance, snapback, and a decrease in the sustaining voltage (Fig. 6.48) [84]. This breakdown mechanism is similar to that of an NPN transistor breakdown, with the source of the NMOS acting as the emitter, the bulk as the base and the drain as the collector. The bipolar gain initially increases with source–drain current, which is the main cause for the negative resistance. For “safe” NMOS operation, the NMOS

6.3 MOSFETs and CMOS

279

Fig. 6.47 Illustration of the voltage snapback mechanism in NMOS

P-well

Source

Gate

Drain

VG

A ID VD

e STI

STI

e +

STI

h

IB

RWell

P-well

P- - substrate Fig. 6.48 Illustration of snapback in a shortchannel NMOS

ID

Sustaining voltage

Snapback (Negative resistance)

Breakdown voltage

VD

should be designed to have a higher sustaining voltage than the maximum operating voltage (Chap. 11). This can be achieved by optimizing the doping profile and NMOS layout to increase the snapback voltage to a sufficiently high level so not to interfere with CMOS operation. For example, a higher retrograde P-well concentration results in a lower substrate resistance and increases the current level at which snapback is triggered. A longer channel and the presence of silicide reduce the bipolar gain, increasing the snapback voltage. Also, abutting the source and substrate contacts helps minimize Rwell. Understanding the snapback mechanism is also important for optimizing the structure when used for protection against electrostatic discharge (ESD) [85] (Chap. 11). (b) Reverse Short-Channel Effects, RSCE In short channels, the threshold voltage is frequently found to initially increase prior to the SCE roll-off (Fig. 6.49). This is commonly referred to as the reverse shortchannel effect, RSCE [86]. Several models have been proposed to explain RSCE

280

6 Analog/RF CMOS

Fig. 6.49 Change in NMOS VT as a function of effective channel length for various channel implant doses. (Adapted from [87])

1.0 VD = 0.05 V Weff = 50 mm

Decreasing channel implant dose 3.0x1012 2.0x1012 1.0x1012 7.5x1011 5.0x1011 2.5x1011 Unimplanted

RCSE

D VT (V)

0.5

0

No RSCE

-0.5 0

5

10

15

Leff (mm)

[86–91]. A widely accepted model is based on a laterally non-uniform dopant profile in the channel. The most common cause of RSCE in both NMOS and PMOS is the encroachment of the halo into the channel (Fig. 6.43), causing a local increase in the threshold voltage. As the channel length is reduced, the regions encroached by the halo occupy a larger fraction of channel length, increasing the overall VT. Thus, as Leff is reduced, the threshold voltage increases before SCE becomes dominant. Another cause of RSCE in NMOS is based on oxidation-enhanced diffusion (OED) of boron, from the multiple P-well regions, into the channel during a reoxidation step after polysilicon gate patterning [87]. During oxidation, silicon interstitial point defects are injected into the junction and diffuse laterally into the channel. The two-dimensional coupled interstitial-boron diffusion results in a laterally non-uniform increase in surface boron concentration. The boron concentration increases predominantly in the channel near the source and drain, locally increasing VT. Thus, the average VT increases as the channel length is reduced. RSCE is found to increase as the channel implant dose increases (Fig. 6.49) [87]. An excess in channel dopant concentration near source and drain edges, causing RSCE, is also attributed to ion implantation of source and drain [90]. This is particularly important to explain RSCE in structures which have a uniform vertical profile in the channel rather than a graded P-well. The proposed mechanism is based on transient-enhanced diffusion (TED), caused by point defects generated by the source–drain ion implantation (Fig. 6.50). As a result, boron diffusion is enhanced near junctions and readily moves to the surface, causing boron accumulation near the surface adjacent to the junctions and a gradient in the lateral boron profile from edge to center.

6.3 MOSFETs and CMOS

281

Fig. 6.50 Conceptual diagram of local interstitial point defect injection during source–drain implantation, causing TED

Source, drain, gate implant N+-source region

Point defects

Fig. 6.51 Schematic cross section of LOCOSimplanted MOSFET, looking from source toward drain

LOCOS encroachment

N+-drain region

Gate

TED P-bulk

W Gate LOCOS

Gate oxide Field implant (“channel-stop”)

Dopant encroachment

(c) Narrow-Channel Effects on Threshold Voltage, NCE The term narrow-channel effect (NCE) is commonly used to describe an increase in VT as the channel width is reduced. It is mostly observed in MOSFETs with LOCOS isolation where a “channel stop,” such as a boron layer in P-type silicon, is implanted under LOCOS at a sufficiently high dose to suppress inversion (Fig. 6.51) [92].4 Since the channel-stop implant is followed by oxidation and additional thermal cycles, boron diffuses toward the surface and encroaches into the channel boundaries, locally increasing the threshold voltage in those regions. The threshold voltage increases from channel center to channel edges because of the encroachment of both the channel-stop implant and LOCOS. Therefore, as the gate voltage is increased, the inversion layer initially forms in the channel center and gradually expands to the edges. The average threshold voltage is found to increase as the channel width is reduced. A quantitative analysis of NCE requires two- or even three-dimensional solutions. (d) Reverse Narrow-Channel Effects, RNCE One drawback of STI is a decrease in threshold voltage as the channel width is reduced. This is referred to as the reverse narrow-channel effect (RNCE) [93–96]. It is caused by several STI edge and corner effects. Without special treatment of STI corners, such as corner rounding processes, sharp edges at the boundaries between STI and active areas can be formed, resulting in thinner gate oxide at the corner and 4

LOCOS stands for Local Oxidation of Silicon and is further discussed in Chap. 9.

282

10-04 Drain current, ID (A)

Fig. 6.52 “Double-hump” in NMOS ID  VG characteristic of edge (lower VT) and center (higher VT) transistors in parallel

6 Analog/RF CMOS

VT (low)= 0.2V;VT (high)= 0.6V; W/L (low) = 0.1;W/L (high) =1

10-06 10-08 10-10

10-12 0

0.1

0.2 0.3 0.4 0.5 0.6 Gate voltage, VG (V)

0.7

0.8

“divots” caused by enhanced etching along sidewalls due to mechanical stress (Fig. 6.20). Also, with the polysilicon gate wrapping around the corner, the two-dimensional field distribution reduces the threshold voltage in those regions. The threshold voltage therefore decreases from center to edge. Any mechanism that contributes to depleting the channel near the edges enhances RNCE. Among these is the loss of boron near the STI boundary by segregation into the oxide. The entire channel region can then be approximated by a center region with nominal threshold voltage and edges with a lower average VT. The resultant ID  VG characteristic typically exhibits a “double hump” as shown in Fig. 6.52. (e) Transit Time and Frequency at Unity Gain The transit time τ is the average time for inversion carriers to travel from source to drain. The lateral field can be approximated as Ey ffi V D =Leff V=cm

ð6:76Þ

Since for long channels Ey < 5  103 V/cm, the drift velocity is proportional to the field as vd ¼ μeff Ey cm=s

ð6:77Þ

The transit time in DC operation is then τffi

Leff L2 ffi eff s vd μeff V D

ð6:78Þ

Under AC operation, the gate-to-source, gate-to-drain, and gate-to-bulk capacitances must be taken into account. The MOSFET gain is defined as the ratio of the amplitude of small-signal drain current to the amplitude of small-signal gate current as

6.3 MOSFETs and CMOS

Gain ¼

283

∂I D gm ¼ ∂V G ωðC GS þ C GD Þ ωðC GS þ CGD Þ

ð6:79Þ

where ω is the signal frequency, gm is the transconductance, CGS is the gate-tosource capacitance, including fringe, overlap, and channel. CGD is the gate-to-drain capacitance, including fringe and overlap. The gain bandwidth product, fT, is a good MOSFET figure of merit. It is the frequency at which the gain in (6.79) drops to 1. Thus, fT ¼

gm Hz 2π ðCGS þ CGD Þ

ð6:80Þ

Another MOSFET figure of merit of particular importance in analog designs is the frequency at which the ratio of output to input power goes to 1. This is called the maximum oscillation frequency, fmax. It can be approximated by [97]. fT ffi Hz f max ffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 RG ðgd þ 2πf T C GD Þ

ð6:81Þ

where gd ¼ 1/ro is the drain conductance and RG is the effective gate resistance approximated for a one-sided contacted gate as RG ¼

RS W eff Ω 3 Leff

ð6:82Þ

where RS is the sheet resistance of the gate. Thus, fmax can be increased by increasing fT and by reducing the gate resistance and gate-to-drain capacitance. In planar MOSFETs, the total gate capacitance consists of an intrinsic capacitance between gate and channel and extrinsic capacitance between gate and conductors, including source–drain. Disregarding interconnect capacitances, the most important extrinsic capacitances are the gate-to-source and gate-to-drain overlap capacitance, Cov, and outer fringe capacitance, Cof (Fig. 6.53). Since Cov and Cof are essentially independent of channel length, their contributions become a larger fraction of the total gate capacitance as the channel length is reduced. The overlap region at each end can be approximated as a parallel plate capacitor of area Aov and capacitance C ov ¼ C ox Aov ¼ Aov

ε0 εox ε0 εox ¼ 107 Lov fF=μm t eq t eq

ð6:83Þ

where Lov is the overlap extent in μm. The above equation should only be treated as an approximation because Lov depends on how accurately the effective (electrical) channel length is measured and teq depends on polysilicon corner rounding due to oxidation and on bias conditions, i.e., depletion or accumulation of the overlap

284

6 Analog/RF CMOS Important MOSFET capacitances Outer Fringe, Cof

Gate Gate Overlap, Cov

Source Source

Channel Inner fringe

Perimeter

Drain

Bulk Floor Leff

Fig. 6.53 MOSFET capacitances

region and of polysilicon. For a teq ¼ 10 nm, Cov typically ranges from 0.10 to 0.20 fF/μm, depending on the oxide thickness and the extent of LDD. The outer fringe capacitance, Cof, in Fig. 6.53 is more difficult to calculate. Analytical expressions for Cof were obtained in [98–101]. A simple approximation is obtained by partitioning the polysilicon in elemental conductor films of thickness dx at varying heights x from the silicon surface and integrating their individual capacitances [98, 99]. The capacitance per μm width is then approximated as x¼tZ ox þt poly

C of ffi x¼t ox

  t poly εo εi W dx ¼ 8:86  103 εi ln 1 þ fF=μm t ox x

ð6:84Þ

where εi is the dielectric constant of the sidewall insulator (~3.9 for oxide, ~7.0 for nitride). The sidewall insulator typically consists of a dual dielectric that requires an adjustment to the effective dielectric constant. A method to extract the overlap length, Lov, and Cof from C-V measurements in the accumulation and inversion modes is described in [102]. In high-density layouts, the contact plug is placed close to the spacer so that the lateral poly-to-plug capacitance becomes important, particularly when multiple or long source and drain contacts are used.

6.4 Deep Submicron and Nanoscale MOSFETs 10-03 10-04 10-05 Drain current, ID (A/mm)

Fig. 6.54 Short-channel effect on the drain current versus gate voltage with decreasing channel length. The gate loses control of VT as the channel length decreases for a constant VD, or as VD increases for a fixed short-channel device

285

10-06 Gate loses control of VT

10-07

10-08 10-09 10-10 10-11 10-12

6.4

0

0.4 0.8 1.2 Gate voltage, VG (V)

1.6

Deep Submicron and Nanoscale MOSFETs

Several techniques have been developed to improve the transistor performance and reduce its size, particularly for logic and memory applications. They include mobility enhancements, high-κ gate dielectrics, metal gates, three-dimensional structures, and fully depleted SOI structures. This section presents a brief review of these enhancements and their impact on analog circuits.

6.4.1

Mobility Enhancement Techniques

As the channel length is reduced, the MOSFET current drive increases, but not at the same rate as the off-current so that the ratio Ion/Ioff decreases. This is because of mobility degradation resulting from the higher vertical and lateral fields as the transistor dimensions are scaled down. At a channel length below approximately 100 nm, Ioff and hence the standby power become prohibitive (Fig. 6.54). Enhancing the inversion-carrier mobility is one means of improving Ion, compensating for the field-induced mobility degradation and improving the Ion/Ioff ratio. (a) Mobility Enhancement by Appropriate Crystal Orientation So far, we assumed a single value for the low-field carrier mobility and considered only its dependence on temperature and doping concentration (Chap. 2). The mobility, however, also depends on the crystallographic and channel orientations.

286

400

(a)

Electron mobility (cm2/V.s)

Fig. 6.55 Measured electron and hole mobilities as a function of inversioncarrier density, Ninv, for different combinations of wafer orientation and channel orientations. (a) Electrons. (b) Holes. Keep the reference (Adapted from [106])

6 Analog/RF CMOS

300K 300

(110)/

200 (110)/ 100

(110)/

5.0x1012

0

Ninv

Hole mobility (cm2/V.s)

200

(b)

(100)/

300K

1.0x1013

1.5x1013

(cm-2) (110)/

150 (110)/ (110)/ 100 (100)/

50 0

5.0x1012 Ninv

1.0x1013

1.5x1013

(cm-2)

MOSFETs constructed on a (100) surface, with the source-to-drain orientation in the direction, exhibit the highest electron mobility and the lowest interfacecharge density [103–105]. These are the typical crystal and channel orientations in silicon wafers. This combination, however, does not optimize the hole mobility. The highest mobility for holes is achieved on (110) oriented wafers with the source-todrain direction in the direction [106–114]. Figure 6.55 shows measured electron and hole mobilities as a function of inversion-carrier density, Ninv, in long and wide MOSFETs (small lateral field) fabricated on bulk silicon with different combinations of wafer planes and channel orientation [106]. A method to construct optimized orientations for both NMOS and PMOS in one integrated wafer is described in [106]. (b) Mobility Enhancement by Strained Silicon From the balance of carrier energy lost by collisions and energy gained by the electric field, we find the one-dimensional low-field drift velocity as

6.4 Deep Submicron and Nanoscale MOSFETs

vdy ¼ μy Ey ¼

287

qτ cm=s my

ð6:85Þ

where y is the direction from source to drain, and vdy, μy, Ey, and my are, respectively, the drift velocity, inversion-carrier mobility, electric field, and effective mass in the y-direction. τ is the mean-free time between collisions. From (6.85) we see that the mobility decreases with increasing effective mass, which depends on the crystal orientation. Electrons drifting in the direction of high effective mass have a low mobility, and electrons drifting in the direction of low effective mass have a high mobility. Let μl and μh denote, respectively, the low and high mobility. In a cubic crystal and in the absence of any strain, the mobility and the carrier population are the same in all directions, and the mobility has an average value of [115]. μ¼

μl þ 2μh cm2 =Vs 3

ð6:86Þ

By applying an appropriate strain to silicon, the population of high-mobility carriers can be increased at the expense of the low-mobility carriers so that the average mobility increases. Consider, for example, a rectangular NMOS channel with the source-to-drain direction along the x-axis. It can be shown that if a uniaxial tensile strain (source and drain pulled apart) is applied along the source–drain direction, almost all electrons will be transferred to the high-mobility level. Similarly, if a compressive uniaxial strain is applied along the source–drain direction of a PMOS, the hole mobility will increase. This is actually a well-known phenomenon referred to as the piezoresistance effect [116].

Source

Gate

Si1-xGex

Drain

Source

Si1-xGex

Si1-yCy

Si body

Sidewall heterojunction

Drain

Si1-yCy Tensile strain

Compressive strain

(a) PMOS

Gate

Si body Si Ge

(b) NMOS

Si C

Sidewall heterojunction

Fig. 6.56 (a) Strained PMOS channel with epitaxial Si1xGex in the source and drain. (b) Strained NMOS channel with epitaxial Si1yCy in the source and drain

288

140 PMOS, 300 K Hole mobility (cm2/Vs)

Fig. 6.57 Increase in hole mobility in PMOS under uniaxial compressive strain as a function of vertical field [117]

6 Analog/RF CMOS

Uniaxially strained

120

100 80

Unstrained universal hole mobility

60 40

Fig. 6.58 Increase in electron mobility in NMOS under uniaxial tensile strain as a function of vertical field [118]

0.2 0.4 0.6 0.8 1.0 1.2 Effective vertical field, Eeff (MV/cm)

NMOS, 300 K Effective electron mobility m eff (cm2/Vs)

0

350

Uniaxially strained 300

250

200

Unstrained

150

1.0

1.1

1.2

1.3

1.4

1.5

Effective vertical field, Eeff (MV/cm)

Several methods to create an appropriate strain in MOSFETs have been reported [117–121]. Among these are adding a fraction x of germanium to the silicon lattice of the PMOS source and drain, thereby creating a layer of Si1xGex on silicon (Fig. 6.56a [117]). Since the average lattice constant is larger in the Si1xGex crystal than in Si (Table 5.2), this results in a vertical tensile strain and hence a lateral

6.4 Deep Submicron and Nanoscale MOSFETs

289

compressive strain along the PMOS channel, hence a higher hole mobility. Similarly, adding a fraction y of carbon to the silicon lattice of the NMOS source and drain creates a vertical compressive strain because the average lattice constant is smaller in a crystal of Si1yCy than in Si (Table 5.2). A lateral tensile strain is created in the NMOS channel, resulting in an increase in the electron mobility (Fig. 6.56b [118]). Figure 6.57 compares the PMOS hole mobility in strained silicon to the universal hole mobility in unstrained silicon [117], and Fig. 6.58 compares the NMOS electron mobility in strained silicon to the universal electron mobility in unstrained silicon, both as a function of surface field. In both cases, the low-field inversion-carrier mobility is considerably enhanced. Strain engineering is a vital technology to enhance the mobility and hence transconductance in nanoscale CMOS and meet stringent demands for digital, RF, and analog circuits, particularly in wireless communication system on chip (SoC) design. There is no indication that low-frequency noise, discussed in Chap. 10, is affected by the strain [122]. The data on noise (and component mismatch) in strained silicon MOSFETs is, however, very limited.

6.4.2

Ultrathin Oxide and High-κ Dielectrics

A silicon dioxide film of thickness less than about 4 nm is referred to as an ultrathin oxide. As the channel length is reduced, the ratio of channel length to gate oxide thickness must remain above approximately 40 to maintain adequate control of the gate over the channel and avoid severe short-channel effects [123]. When the oxide thickness is decreased below 4 nm, however, tunneling through the oxide increases rapidly (Chap. 11). For example, for an effective channel length of 65 nm, the gate oxide must be reduced to about 1.5 nm. For such a thickness, the gate current can increase above about 10 A/cm2 (0.1 μA/μm2), which can become a problem even in power-tolerant high-performance logic applications. In addition, an ultrathin oxide allows the penetration of boron from the gate through the oxide into silicon in a PMOS with an SiO2/P+-poly gate stack. This problem can be solved by replacing the pure oxide with an oxynitride (SiON) which inhibits the penetration of boron and also slightly increases the dielectric constant of the gate insulator to about 4.0–6.5, depending on the nitrogen concentration [124, 125]. Nitrogen in the vicinity of the silicon surface, however, induces additional traps, increasing the interface trap density, and hence increases the MOSFET low-frequency noise [126–128]. The nitrogen-related additional traps at the interface can be considerably reduced by plasma-nitrided oxide (PNO), placing the nitrogen near the top of the polysilicondielectric interface, away from the silicon surface [127, 128]. In addition, the presence of nitrogen in the dielectric has little impact on component mismatch (Chap. 10). Silicon dioxide and oxynitrides have, however, reached the limit of about 1.2–1.5 nm due to the rapid increase in the tunneling current. This is why higher dielectric-constant insulators and metal gates have replaced conventional SiON/polysilicon gate stacks in nanoscale technologies.

290

6 Analog/RF CMOS

102

jG at VG = VFB – 1V (A/cm2)

Fig. 6.59 Comparison of tunneling current for three gate dielectrics of different dielectric constant and same equivalent oxide thickness [129]

101 100

SiO2 (k=3.9)

k =5

Oxide scaling ends in this range

k =18

10-1 10-2 10-3

10-4 10-5 10-6 0.5

1.0

1.5

2.0

2.5

3.0

teq (nm)

The primary motivation for the development of high-κ dielectrics is to increase the physical thickness of the gate dielectric to reduce the tunneling current, while reducing the equivalent oxide thickness, teq (or EOT). Figure 6.59 compares the tunneling current for three gate dielectrics of different dielectric constant and same equivalent oxide thickness [129]. Metal gates, such as TaN, eliminate the problem with polysilicon depletion. Hafnium-based dielectrics, such as HfSiON, appear to be the most promising gate insulators for high-performance applications. When in direct contact with silicon, however, the dielectrics increase the overall defect and interface-state density, degrading the MOSFET mobility and transconductance and increasing the flicker noise [130–138]. They also increase the component mismatch due to the instability of threshold voltage and drain current [138] (Chap. 10). Inserting a silicon–dioxide layer between the high-κ dielectric and silicon improves the carrier mobility but at the cost of reducing the equivalent dielectric constant of the composite material [133, 137]. For SoC platform applications, high-performance, low-power, mixedsignal, and high-voltage MOSFETs must be independently optimized [139].

6.4.3

FinFETs

Recall that, as the channel length is reduced, more field lines from the drain begin to terminate on channel ions near the source, reducing the barrier there, hence reducing the threshold voltage. This was referred to as drain-induced barrier lowering, DIBL. In other words, as the channel length is reduced, the drain begins to compete with the gate for ions near the source. Those field lines are not only parallel to the surface but

6.4 Deep Submicron and Nanoscale MOSFETs Fig. 6.60 Schematic of FinFET (a) Constructed on bulk silicon. (b) Constructed on SOI

291

(a) LG

Source

Gate Drain dielectric

FinFET

(b) LG

Source tSi

Gate Drain dielectric

also distributed under the channel where the gate has little influence. The difference between DIBL and punch-through lies in the role of the gate in barrier lowering at the source. In a FinFET, the channel is almost completely controlled by the gate from both sides greatly suppressing the short-channel effect [140–144]. The FinFET can be constructed on bulk silicon as in Fig. 6.60a or on SOI as in Fig. 6.60b (Chap. 9). In both cases, the fin is typically lightly doped or undoped and of thickness tSi that allows the applied voltage on the two gates to fully deplete the fin between the gates. Lightly doped or undoped fins reduce mismatch in VT caused by dopant fluctuations. The gate dielectric can be an ultrathin oxide or a combination of high-κ dielectric, SiON, and oxide. The threshold voltage is mostly determined by workfunction tuning of the metal gate material (Chap. 9). The source and drain are typically in situ doped while deposited. They are elevated and optimized to reduce the source–

292

6 Analog/RF CMOS

drain resistances. Strain techniques to enhance the mobility are similar to the planar MOSFETs: The source and drain consist of boron-doped Si1xGex for PMOS and arsenic-doped Si1yCy for NMOS. The channel length, Leff, is defined by LG and the channel width, Weff, defined by two times the height of the fin (the top of the fin does not contribute to the total channel width because it is typically covered by a thick insulator). The most significant analog advantage of FinFETs is the suppression of the shortchannel effect, leading to an improved linear gain gm/gd [140, 145, 146]. Another advantage is the reduced subthreshold slope, resulting in lower Ioff and enabling a lower VT, increasing the “headroom” for analog designs. Loosely stated, a circuit is said to have headroom if all transistors are able to operate in their intended bias regions. Noise and component mismatch require, however, more optimization for analog designs. FinFETs with high-κ/oxide dielectrics show the same trend in low-frequency noise as in planar MOSFETs. In addition, an increase in noise level attributed to rough sidewalls, and dielectric has been observed, particularly in narrow fins [140]. Matching is also degraded in scaled FinFETs with narrow fins because of line-width roughness, surface roughness, gate misalignments, and variations in source–drain resistance [140]. The flexibility of analog designs is also limited, mainly because of the specified fixed orientation of the gate, the limited choice of width sizes, and the complex metal routing.

6.4.4

Fully Depleted SOI MOSFET

A fully depleted SOI (FD-SOI) MOSFET is shown schematically in Fig. 6.61. The structure is also referred to as an ultrathin body (UTB) SOI MOSFET [147]. The concept was introduced in [148, 149] where a near intrinsic MOSFET body was suggested. The structure in Fig. 6.61 is shown for an oxide thickness tox ¼ 2.4 nm and a 40-nm channel length. For a near-intrinsic top silicon film thickness tSi  5 nm, the threshold voltage is almost fully controlled by the work function of the gate. For a polysilicon gate, the work function can be tuned by adding germanium to the gate and adjusting the fraction of Ge in the SiGe film [150]. In the case of a metal gate, a metal (or metals) with tuned work function(s) can be employed. Fig. 6.61 Schematic of a fully depleted SOI (FD-SOI) MOSFET

Gate

Source Dielectric

Drain BOX

Substrate

Body

6.5 Analog CMOS Applications

293

FD-SOI MOSFETs and FinFETs with ultrathin body are similar inasmuch as both use a near-intrinsic, fully depleted silicon body to suppress short-channel effects. In both structures, the MOSFET transconductance and output resistance are greatly increased, resulting in high gm/gd and near-ideal subthreshold characteristics [151, 152]. Issues remain, however, with low-frequency noise, component mismatch, and source–drain resistances. In particular, traps in the front and back of the buried oxide in FD-SOI significantly increase the low-frequency noise as the thickness of the silicon body is thinned [153]. Techniques to reduce the noise, such as optimizing the back-gate interface under the BOX, are being pursued.

6.5

Analog CMOS Applications

Analog CMOS technology has become the workhorse for analog designs, whether for stand-alone products or integrated circuit blocks in a mixed signal product. Regardless of the application, there are several analog circuits that are ubiquitous and that highlight some of the key considerations in analog transistor optimization, prominently the differential amplifier and the current mirror. The importance of high transconductance and high output resistance can be best understood by considering a simple differential amplifier as shown in Fig. 6.62a [154].

6.5.1

Differential Amplifier

The two NMOS devices in Fig. 6.62a have a common source to which a constant current source is connected. The NMOS drains are each connected to a load resistor VDD V2 I1

I2

RL

RL Vout1

Vout2

Vleft

T1

T2

Vright

T1

T2

VS

VG1

I (a)

Ground

(b)

Fig. 6.62 (a) Basic NMOS differential amplifier. (b) Current mirror

Ground

294

6 Analog/RF CMOS

RL that is connected to the supply voltage VDD. If the input voltages Vleft and Vright are exactly the same, then transistors T1 and T2 will have the same gate-to-source voltage (VG  VS), where VS is the voltage across the current source. Thus, T1 and T2 will have the same drain currents. If Vleft is increased by δVG and Vright decreased by δVG, the current in T1 will increase by δID, and the current in T2 will decrease by δID. Vout1 will decrease by δID  RL, and Vout2 will increase by δID  RL. Thus, the differential gain becomes [155] Adiff ¼ 

2∂I D  RL ∂I D  RL ¼ 2∂V G ∂V G

ð6:87Þ

The term δID/δVG is the transistor transconductance gm. The gain is therefore proportional to transconductance as Adiff ¼ gm RL

ð6:88Þ

The above relations were derived under the assumption of zero MOSFET conductance gd, i.e., infinite transistor output resistance. If gd is finite, the parallel combination of RL and the transistor output resistance 1/gd results in a degraded gain as Adiff ¼ 

gm  RL 1 þ gd  RL

ð6:89Þ

High transconductance and low gd (high ro) are therefore of particular importance to analog designs, necessitating the use of MOSFETs with non-minimum channel lengths for the input pair. Equation (6.89) was derived under the assumption that T1 and T2 have exactly the same threshold voltage. Mismatch in the input pair will, however, cause I1 and I2 to be unbalanced, resulting in a non-zero (Vout1  Vout2) when Vleft ¼ Vright. Hence, to get zero output, an input offset voltage (VIO) must be applied to the differential inputs. Since matching degrades with smaller channel lengths (Chap. 10), the use of longer-channel MOSFETs is again required, in this case dictated by the need for low VIO.

6.5.2

Current Mirror

Another simple application that shows the importance of high ro is the current mirror (CM) shown in Fig. 6.62b. The purpose of a CM is to replicate or ratio the forced current I1 into different circuit legs. Since NMOS T1 has the gate shorted to drain, it operates in saturation at a gate overdrive (VG1  VT1) where

6.5 Analog CMOS Applications

295

I 1 ffi μeff C ox ðS1 =2ÞðV G1  V T1 Þ2 A

ð6:90Þ

and S1 is the ratio Weff/Leff in T1. The drain voltage V2 applied to T2 is determined by the circuit connected to the drain, but the goal is to have I2 equal to I1 or to be a fixed ratio of I1. Since the gates of T1 and T2 are shorted, VG2 ¼ VG1. Matching between transistors T1 and T2 and between T3 and T4 is critical, so that we can assume VT2 ¼ VT1. Then, for long channels where channel-length modulation (CLM) can be ignored, the ratio I2/I1 ¼ S2/S1. For shorter channels, an approximation that takes CLM into account is I 2 ffi I Dsat ½1 þ λðV 2  V Dsat Þ A

ð6:91Þ

where λ ¼ 1/(IDsat  ro). With CLM, the ratio I2/I1 becomes I 2 =I 1 ffi ðS2 =S1 Þ½1 þ λðV 2  V Dsat Þ

For example, let S1 ¼ S2, V2 ¼ 4 V, VDsat ¼ 1 V, and IDsat ¼ 10 μA, then if a maximum mismatch between I2 and I1 of less than 1% is desired λðV 2  V Dsat Þ ¼ ðV 2  V Dsat Þ=ðI 2  r 0 Þ < 0:01 and ro must be larger than 30 MΩ, which is not realistic for a single stage CM shown in Fig. 6.62b. Instead, a very high ro can be achieved in a cascoded configuration shown in Fig. 6.63 [156].

Fig. 6.63 Cascoded current mirror to achieve high output resistance. T1 and T2 can be standard or native NMOS

V2 I1

I2

T3

T4

T1

T2

296

6 Analog/RF CMOS

VG = VDD

VG = VDD

Output, 0V

Input 0V

VG = VDD

Output VDD - VT

Input VDD

P-well

P-well

VB = 0

VB = 0

(a)

(b)

Input VDD

Output VDD No P-well Native VB = 0 (c)

Fig. 6.64 Comparison of high output signal for standard and native NMOS. (a) NMOS: Zero input and output. (b) “Standard” NMOS: VDD at input, VDD  VT at output. (c) Natural NMOS: VDD at input and output

6.5.3

Native NMOS

Native NMOS transistors have niche applications, e.g., in low-voltage operational amplifiers. Because of the near-zero VT, the native NMOS operates in subthreshold at near-zero gate voltage. It is used in the input stage of low-power operation amplifiers to obtain a rail-to-rail swing [157, 158], i.e., with full VDD output without loss of VT (Fig. 6.64c). It has also found applications in improving the response speed of silicon-controlled rectifiers (SCR) and in electrostatic discharge (ESD) protection [159] and in obtaining a considerably lower bandgap reference (BGR) voltage than the standard bandgap of about 1.2 V [160]. Native NMOS transistors can also be used for T1 and T2 in the current-mirror circuit shown in Fig. 6.63 to gain more headroom. Since transistors T1 and T3 operate in saturation, T2 and T4 must also operate in saturation to ensure that I1 ¼ I2. Then, VDS-T2 (VG-T2 – VT-T2), and (V2 – VDS-T2) (VG-T4 – VT-T4). It follows that a native NMOS with VT ffi 0 allows V2 to drop by ΔVT below its bias point while keeping T2 and T4 in saturation, where ΔVT is the difference between the threshold voltage of a standard T2 and that of a natural T2. Thus, the circuit is said to have more headroom. An additional advantage of using native NMOS transistors for T1 and T2 is the better matching because of the inherent longer channel and considerably lower channel doping concentration. Low-VT NMOS can also be used for expanded headroom applications, although the VT is not as low as in the native NMOS case.

6.5.4

Buried-Channel and Depletion-Mode MOSFETs

The main advantage of buried-channel over surface-channel MOSFETs is their low noise (Chap. 10). Both buried-channel NMOS and PMOS have found several applications such as in charge-coupled devices (CCD) to improve the charge transfer efficiency, and image sensors to reduce the dark noise [161, 162], and in low-noise amplifiers (LNA). The input stage is a key factor in determining the noise of an amplifier which consists of the input pair and load transistors (replacing the load

Problems Fig. 6.65 Depletion-mode NMOS differential pair used in operational amplifier input stage

297

V+

V-

I

resistors, RL, in Fig. 6.52a). Hence, it is important to optimize the noise performance of those transistors. Replacing the surface-channel PMOS with buried-channel PMOS in those circuits can be effective in lowering the overall amplifier low-frequency noise. Depletion-mode MOSFETs are not used as extensively as enhancement-mode devices. They have, however, several special low-noise applications and circuits where small MOSFETs replace large-sized resistor loads, such as in an inverter, while maintaining a full rail-to-rail swing. Depletion-mode NMOSFETs are also used in the input stage of amplifiers operating at very low voltages. The low voltage is driven by the need to reduce power consumption with large digital content, particularly in portable applications. The depletion-mode NMOS is best suited to operate at low voltages, below 1 V, since it conducts at zero gate-to-source voltage. Thus, by using a depletion-mode differential pair in the input stage of an amplifier operating at a voltage even less than 1 V, a rail-to-rail common-mode voltage range can be achieved (Fig. 6.65) [159–163]. The differential pair relies on modulating the source-to-body voltage as a function of the input, which considerably increases the threshold voltage of the depletion-mode transistors [164].

Problems 1. An MOS structure formed on P-type substrate is biased in strong accumulation. Assume that the maximum field in the oxide may not exceed 5.5  106 V/cm and estimate the maximum excess holes/cm2 that can be induced in silicon. Assume an oxide thickness of 7.2 nm and find the maximum voltage that may be applied to the gate. 2. For the MOS structure in Problem 1, find the surface potential that yields a concentration of holes at the surface of 1020 cm3 at 25  C. What is the surface concentration of electrons for this case? 3. An idealized MOS structure is constructed on a P-type substrate of uniform concentration NA ¼ 5  1016 cm3. (a) Assume an oxide thickness tox ¼ 12.5 nm and 25  C and find the threshold voltage.

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(b) While the MOS structure is kept at 25  C in a dark enclosure, the gate voltage is pulsed from 0 to +5 V and held constant at +5 V. Find the depletion width immediately after the pulse. (c) Estimate the inversion layer concentration, Qn, after the surface fully relaxes to its steady-state condition. 4. Show that for a uniformly doped MOSFET body the body-bias effect can be expressed as dV T Cmin ¼ dV B C max  Cmin where VB is the source-to-body voltage. 5. Approximate the field at the silicon surface field and in the oxide for the structure in Problem 3. For (a) VG ¼ VT at onset of strong inversion. (b) VG ¼ 5 V, in deep depletion. (c) VG ¼ 5 V in steady-state strong inversion. 6. The following assumptions are made for simplicity: Long and wide buriedchannel PMOS; uniform buried-channel concentration NA ¼ 5  1016 cm3; buried-channel junction depth xjbp ¼ 0.12 μm; N-well concentration at junction ND ¼ 5  1016 cm3; EOT teq ¼ 12.5 nm; degenerately doped N+-poly gate; temperature 25  C. Estimate: The threshold voltage and subthreshold slope. 7. An NMOS having an EOT of 13 nm is fabricated on a 2 Ω-cm substrate. The source, drain, and substrate are grounded and the gate biased such that the substrate surface potential is +0.5 V. Assume 25  C, Qeff ¼ 0 and find the surface concentrations of electrons and holes. For an N+-polysilicon gate, find the corresponding gate voltage. 8. For the structure in Problem 6, find the surface potential at onset of strong inversion, the maximum depletion width, the maximum bulk charge density in steady-state strong inversion, the threshold voltage, and the number of electrons per cm2. 9. An NMOS is made on a P-type substrate with NA ¼ 2.5  1017 cm3, inversion teq ¼ 8.0 nm, and an N+-polysilicon gate. The effective oxide charge is Qeff ¼ +2  1011q C/cm2. The effective channel dimensions are Leff ¼ 0.5 μm, Weff ¼ 2 μm. For 25 and 140  C find: (a) (b) (c) (d)

The threshold voltage for VD ¼ 0.1 V. The subthreshold slope in mV/decade. The drain current at (VG  VT) ¼ 3.0 V, VD ¼ 0.1 V and 3.0 V. The transconductance for the voltage conditions in (c).

10. A long- and wide-channel isolated NMOS having a P-well concentration NA ¼ 1.8  1017 cm3, teq ¼ 13.0 nm in inversion. Assume 25  C. By how much should the source to P-well junction be reverse biased to obtain an increase in VT of 0.2 V?

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11. Assume that the channel length in Problem 8. Is Leff ¼ 1 μm and neglect fringe capacitances. Estimate fT at 25  C for VG  VT ¼ 3.0 V and VD ¼ 3.0 V. 12. A 5 V PMOS is biased at (VG  VT) ¼ 2.5 V. The drain current is measured as 0.251 mA/μm (width) at VD ¼ 3 V and 0.252 mA/μm at VD ¼ 4 V. Find the drain conductance, the output resistance and the Early voltage. 13. The threshold voltage of an enhancement-mode NMOS is 0.6 V. Find the dose of arsenic that must be implanted in silicon under the gate of the NMOS to transform it into a depletion-mode NMOS with VT ¼ 0.8 V. Assume teq ¼ 13 nm and the implanted arsenic to have a fully ionized impulse profile located at the silicon surface. 14. The gate, source, and drain of a PMOS are degenerately doped, and the gate oxide thickness is 12.5 nm. Approximate the field in the oxide in the overlapped drain region for the following cases: (a) (b) (c) (d)

The drain is at ground and the gate is P+-poly at 5 V. The drain is at ground and the gate is N+-poly at 5 V. The gate is P+-poly at ground and the drain is at 5 V. The gate is N+-poly at ground and the drain is at 5 V.

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Chapter 7

High-Voltage and Power Transistors

Abstract This chapter focuses mainly on the drain-extended MOS (DEMOS) transistor and on the lateral double-diffused MOS (LDMOS) transistor for highvoltage/high-power applications. In both cases, the drain is extended with a lightly doped region, referred to as the drift region, to sustain the high voltage. The chapter begins with an analysis of the drift region and its optimization, typically by reduced surface field (RESURF) techniques. The transistor switching performance is then analyzed, followed by a discussion of DEMOS and LDMOS design considerations and characteristics. High-voltage and high-current effects are then described, including quasi-saturation (QS), body current, on-state breakdown, and safe operating area (SOA). The chapter concludes with selected high-voltage device applications.

7.1

Introduction

The MOSFETs discussed in Chap. 6 are designed for digital, analog, mixed-signal, and RF applications that operate in the low-to-medium-voltage range of about 0.8–6 V. Many analog applications, however, require transistors that can handle voltages above 20 V and currents in the ampere range. Those transistors are referred to as high-voltage and power transistors. This chapter provides a comprehensive analysis of the drain-extended MOS (DEMOS) transistor, for high-voltage and low-current applications, and the lateral double-diffused MOS (LDMOS) transistor, for power applications. The “D” in LDMOS describes the sequential (double) diffusion of boron and arsenic through the same mask opening, defining a precise channel length (Chap. 9). The “L” means that the current path is parallel to the silicon surface (lateral), as opposed to “V” in VDMOS where the current is nearly vertical to the silicon surface. Schematic cross sections of both transistors are shown in Fig. 7.1. The transistors share many similarities but are constructed differently (Table 7.1). The DEMOS is typically processed without added process complexity, whereas the LDMOS requires optimization of the P-body and N-drift regions to achieve high voltages and currents while minimizing the drain-to-source resistance and transistor area.

© Springer Nature Switzerland AG 2020 B. El-Kareh, L. N. Hutter, Silicon Analog Components, https://doi.org/10.1007/978-3-030-15085-3_7

307

308

7 High-Voltage and Power Transistors Source/Body

Gate

Drain

Gate

Source/Body

Poly STI

+

P

N

+

P-substrate

Poly STI

P-well

Drain

N

Ldrift

+

STI N-well

STI tdrift

LDD Channel Drain-Extension (a)

+

P

N

+

STI

P-body

Ldrift

N

+

STI

N-drift

N-extension

P-substrate

Channel Drain-Extension (b)

Fig. 7.1 Schematic cross sections of transistors shown with source and body shorted. (a) N-channel DEMOS. (b) N-channel LDMOS Table 7.1 Comparison of DEMOS and LDMOS DEMOS High-voltage capability Low-to-moderate-current capability Complementary devices Planar and field-gap stylesa Asymmetric and symmetric layouts Lateral channel doping constant VT same as CMOS VT Variable W and L Requires no extra masking steps a

LDMOS High-voltage capability High-current capability Complementary devices Planar and field-gap styles Asymmetric layouts Lateral channel doping graded VT higher than CMOS VT Variable W, but L is fixed Requires additional masking steps

A field gap is a thick oxide, STI or LOCOS, under the gate edge in the drift region

The interest in bipolar, CMOS, and DMOS (BCD) technologies has been driven primarily by the proliferation of portable electronics and automotive electronics and the need for energy efficiency. These applications cluster around different operating points, with 24 V for portable electronics; 60 V for automotive, solar, and LED backlighting; 85 V for power over Ethernet; 120 V for telecommunication; and 700 V for offline LED lighting, consumer, and industrial applications. As a result, BCD is now the technology of choice to realize power ICs by most integrated device manufacturers (IDM) and foundries [1–5]. This chapter focuses mainly on transistors with voltage capabilities in the range of 20–700 V, where the bulk of the product applications lie.

7.2

The Drift Region

The purpose of the drift region is to sustain the high voltage on the drain (Fig. 7.1). In both DEMOS and LDMOS, the drift region can be considered as an extended lightly doped drain (LDD) described for low-to-medium-voltage CMOS in Chap. 6. It is shown that the drift length and thickness, Ldrift and tdrift, and the doping

7.2 The Drift Region

309

concentration Ndrift in the drift region are the most important parameters that determine the device characteristics. The drift region must be lightly doped and sufficiently long and deep to absorb most of the high lateral and vertical reverse bias applied to the drain. The lateral and vertical fields must, however, remain below the critical field for avalanche breakdown, and the field in the oxide under the gate must remain below the safe operating level of approximately 5
106 V/cm. The drain-to-source resistance, RDS, is an important parameter in MOSFETs, in particular in high-current devices. It must be kept low to reduce power loss. The dominant part of the drain-to-source resistance in the on-state, RDS(on), defined at maximum gate-to-source voltage, VGSmax, and very small drain-to-source voltage, such as VDS ¼ 0.1 V, is the resistance of the drift region, Rdrift. To reduce Rdrift, the drift concentration, Ndrift, should be increased. On the other hand, to increase the breakdown voltage, Ndrift must be reduced. Thus, there are conflicting requirements between high avalanche breakdown voltage and low drift resistance, necessitating an optimizing trade-off between those two important characteristics. Since DEMOS typically uses existing CMOS wells for the drift region (and MOSFET body), the drift resistance and breakdown voltage can be optimized only by choosing the correct drift length. In comparison, several process and layout parameters are available to optimize an LDMOS, including Ndrift, Ldrift, and tdrift. A high-voltage MOSFET can be approximated as consisting of an intrinsic low-voltage MOSFET in series with a “grafted” drift resistor, as illustrated for a drain-extended NMOS in Fig. 7.2 [6, 7]. The point K (key point) in the figure represents the drain end of the intrinsic NMOS [7]. Points S and D refer to the source and drain boundaries. The reverse-biased drain-to-substrate/P-well junctions are represented by a single “blocking diode.”

Fig. 7.2 A simple model of an N-channel drainextended transistor [7]

VG

P+

Key Point

N+ Poly

VS S N+

P-well

VD

D K

Rdrift

N+

N-well (drift)

P-substrate Device-pitch

310

7.3

7 High-Voltage and Power Transistors

On-State Analysis

Figure 7.3 shows typical transfer characteristics for a drain-extended device, identifying the on and off switching states.

7.3.1

On-Resistance, RDS(on)

When a high-voltage or high-power transistor is biased into its on-state , the goal is to have a low resistance between source and drain, enabling high currents with minimal voltage drop and power loss in the device. A key parameter is the on-resistance, RDS(on). To achieve a low on-resistance, the structure is designed as an array of identical transistors connected in parallel to produce a large effective width. For a given gate voltage above threshold, VGS > VT, and a very small drain voltage, the device operates in the linear mode. Neglecting leakage currents and source–drain contact and series resistances, the externally applied drain-to-source voltage, VDS, is V DS ¼ V KS þ I DS Rdrift V

ð7:1Þ

where VKS is the voltage drop across the channel of the intrinsic MOSFET, IDS the drain-to-source current, and IDS
Rdrift the voltage drop across the drift resistance. The on-resistance of the drain-extended device is RDSðonÞ ¼ V DS =I DS Ω

ð7:2Þ

The on-resistance is typically measured at VGSmax, which is the maximum value allowed by the gate oxide thickness, and with a very small VDS, typically 100 mV. Thus, under the above simplifying assumptions,

Saturation region

Drain Current, ID (A)

Fig. 7.3 Typical transfer characteristics for an N-channel drain-extended device showing on-state and off-state regions

5V 4V

On-state Linear region

3V Off -state

2V VGS = 1 V 0V

BV VOP Drain-to-Source Voltage, VDS (V)

7.3 On-State Analysis

311

Fig. 7.4 Schematic of Kelvin probe measurement to extract RDS(on)

IDS

A

D1

D2 VDS Vapp

V VGS

S2 S1

RDSðonÞ ¼ RKS þ Rdrift Ω

ð7:3Þ

where RKS ¼ VKS/IDS is the channel resistance of the intrinsic MOSFET and Rdrift is the resistance of the drift region. When measuring RDS(on), care must be taken to avoid adding parasitic (probe) resistances, particularly when MOSFET arrays of large effective width and hence small on-resistance are measured. This is typically done with Kelvin connections (Fig. 7.4). Two sets of pads (D1, S1) and (D2, S2) are connected to the source and drain of the transistor. The external voltage, Vapp, is applied between D1 and S1, forcing a current IDS between the MOSFET drain and source. The drain-to-source voltage is sensed between D2 and S2 with a high-impedance voltmeter with nearly zero current, avoiding extrinsic IR drops at the sensing probes. The on-resistance is then RDSðonÞ ¼ V D2S2 =I DS Ω

ð7:4Þ

where VD2S2 is the voltage measured between D2 and S2.

7.3.2

Specific On-Resistance, RSP

A power transistor must deliver current to an external load with minimal voltage drop within the device. The transistor is hence typically designed in the form of an array of sufficiently large effective MOSFET width to achieve the required low RDS(on). To be cost-effective, however, the area occupied by the array, and hence that of the individual transistor, must be as small as possible. The area efficiency is best described by the specific on-resistance, RSP, expressed as RSP ¼ RDSðonÞ
Device Area mΩ-mm2 where Device Area is defined as

ð7:5aÞ

312

7 High-Voltage and Power Transistors

Device Area ¼ ðDevice PitchÞ
ðDevice WidthÞ mm2

ð7:5bÞ

and the Device Pitch is approximately the distance between the centers of source and drain. A more detailed analysis of the drain-to-source resistance, RDS, takes into account the series and contact resistances at the source and drain and separates the individual components of the drift resistance in Fig. 7.2 as RDS ¼ RS þ RD þ Rch þ Rdrift þ Racc Ω

ð7:6Þ

where RS, RD Rch Rdrift Racc

Source and drain resistances MOSFET channel resistance (same as RKS) Resistance of drift region Resistance of the gate-overlapped drift region

RS and RD are the resistances between the drain–source terminals and the ends of the channel. They are typically dominated by the spreading resistances at the transition from silicide to silicon and from diffusion to channel (Chap. 6). Racc is under the influence of the gate; it decreases when the surface is accumulated and increases when the surface is depleted. Rdrift depends on the reverse bias between drain and P-body/P-substrate. As the reverse bias increases, the depletion width in the N-drift expands laterally between STI and P-body and vertically between STI and P-substrate. This is a JFET effect that pinches the conductive paths, increasing the vertical and lateral resistances of those regions. For a structure of the type shown in Fig. 7.5, Rdrift can be approximated by the resistance of the drift region under the STI. Since RDS(on) is typically measured at high VGS and low VDS, the JFET effect can be neglected. Also, the effect of accumulation of the N-drift surface under the gate becomes negligible compared to the total drift resistance. Thus, RDS(on) can be approximated as (Chap. 6) VG VS

P+

VD

Gate N+ RS

Rch

Racc

STI Rdrift

N+ RD

STI

tSTI tdrift

N-drift region P-substrate Device pitch Fig. 7.5 Key LDMOS resistor components

7.3 On-State Analysis

RDSðonÞ 

313

2Redge Leff t eq Ldrift þ þ RS-drift Ω W drift ðV GS  V T Þμeff ε0 εox W drift W drift

ð7:7Þ

where Redge is the normalized source and drain resistance per edge, best expressed in Ω-μm; Leff, Ldrift, and Wdrift are, respectively, the effective MOSFET channel length, the length of the drift region, and the total width of the drift region, conveniently expressed in μm; RS-drift is the sheet resistance of the drift region; and the other terms have their usual meaning. The first term in Eq. (7.7) approximates the sum of source and drain resistances. The second term is the channel resistance, Rch, and the third term the resistance of the drift region, Rdrift, where the drift sheet resistance, RS-drift, is approximated without considering the depletion regions as RS-drift 

1 Ω=□ qμn N D ðt drift  t STI Þ

ð7:8Þ

In the above equation, μn is the electron mobility given by (2.39), ND is the drift concentration, and tdrift and tSTI are shown in Fig. 7.5. Example 7.1 Estimate the percentage of RDS(on) due to Rch for a 24 V device biased at VGS ¼ 5 V and VDS ¼ 0.1 V. The gate oxide is 12.5 nm, the effective gate length is 0.6 μm, the drift region length is 2.0 μm, and the drift sheet resistance is 1200 Ω/☐. The threshold voltage VT is 1.0 V, and the normalized N+ source and drain resistance is Redge ¼ 250 Ω-μm. Ignore accumulation and JFET effects. Solution In the linear mode, Redge can be assumed to be the same for source and drain. Thus, the first term in Eq. (7.7) gives RD þ RS ¼ 2Redge =W drift  500=W drift Ω To determine Rch, the effective surface mobility, μeff, must be known. It can be approximated by (6.46a) as μeff ffi


1þ

630

2 1:67 ¼ 298 cm =Vs

1 5þ1 0:75
106 6ð125
108 Þ

Substituting the values in the second term of Eq. (7.7) gives Rch ¼

0:6
104
125
108 1821   ffi Ω ð5  1Þ
298
3:9
8:86
1014 W drift W drift

314

7 High-Voltage and Power Transistors

Rdrift can be calculated as Rdrift ¼ RS-drift

Ldrift 2 2400 ¼ 1200 ¼ Ω W drift W drift W drift

Substituting the values in Eq. (7.7) yields RDSðonÞ 

500 þ 1821 þ 2400 4721 ¼ Ω W drift W drift

Hence, Rch is 1821/4721, or 39%, of the total RDS(on).

Example 7.2 Assume that the device in Example 7.1 operates at 25  C in the linear mode and plot Rch versus VGS.

Normalized RDS(on)

Solution To first approximation, we assume the first and third terms of Eq. (7.7) do not appreciably change as VGS varies. The channel resistance in the second term depends on mobility which is a function of VGS (6.46a). Using (6.46a), a plot of normalized Rch versus VGS can be generated, as illustrated in Fig. 7.6. As VGS increases, the mobility decreases, but the inversion charge in the channel increases. The net is a reduction in Rch and hence RDS(on) with increasing VGS. 10 9 8 7 6 5 4 3 2 2 0 0

1

2

3

VGS (V) Fig. 7.6 RDS(on) versus VGS in Example 7.2

4

5

7.4 Off-State Analysis

7.4

315

Off-State Analysis

The MOSFET is said to be in the off-state when the gate, source, and body/substrate are grounded, and a reverse-bias voltage is applied to the drain. The key parameter in the off-state is the transistor breakdown voltage, BVDSS, between drain and grounded source, gate, and substrate.

7.4.1

A Simple One-Dimensional Analysis of BVDSS

In the off-state, most of the voltage applied to the drain drops in the drift region. Thus, the breakdown voltage in the off-state depends predominantly on the lateral and vertical doping profiles in the drift region. A thorough analysis of the reverse characteristics at the drain requires complex two- or even three-dimensional TCAD simulations, obscuring an understanding of underlying mechanisms affecting the breakdown voltage. Instead, a one-dimensional analysis is made in this section with several simplifying assumptions, providing the reader with a better insight into the key factors that affect the breakdown voltage. For simplicity, a drain-extended structure with uniformly doped regions is considered. The drift region is divided into three parts that are initially assumed to be independent of each other: (1) the MOS region under the gate, (2) the lateral junction, and (3) the vertical junction (Fig. 7.7). For a reverse-biased drain, the drift region is depleted vertically to a width xdn1 under the gate, laterally to a width ydn2 at the junction between P-body and drift region, and vertically to a width xdn3 at the substrate junction. The depletion regions are initially assumed to be non-overlapping. The associated lateral depletion region in the P-well and the vertical depletion region in the substrate are labeled, respectively, as ydp2 and xdp3. The width of the field-induced depletion region, xdn1, is estimated by making a step-junction approximation (Chap. 6): 1. MOS region P+

STI

N+

xdn1

VD N+

Ldrift P-well, NA MOSFET Body

ydp2 ydn2

N-drift, ND

tdrift

xdn3 2. Lateral junction P-substrate, Nsub

xdp3 y

3. Vertical junction

x

Fig. 7.7 Schematic cross section of a drain-extended structure with bias applied, showing the key regions for BVDSS analysis

316

7 High-Voltage and Power Transistors

xdn1

εSi ¼ t eq εox

"sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi # "sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi # 2ε20 ε2ox V D 1:44
106 V D 1þ  1 ffi 3t eq 1þ  1 cm qN D t 2eq ε0 εSi N D t 2eq ð7:9Þ

where teq is the equivalent gate oxide thickness; VD the applied reverse drain voltage with respect to source, body, and gate; and ND the concentration in the N-drift region. It should be noted that as the drain-to-gate voltage is increased (gate negative with respect to drift region), the surface of the drift region under the gate depletes but cannot invert because of the reverse bias between drain and P-body. Instead, the surface goes into deep depletion and most of the drain voltage drops across the depletion region. This reduces the electric field across the gate oxide and allows operation at high drain-to-gate voltages. Example 7.3 For a uniform concentration ND ¼ 1016 cm3 in the drift region under the gate and an equivalent oxide thickness of 12.5 nm, approximate the electric field in the oxide and in silicon for a drain-to-gate voltage VDG ¼ 20 V. Solution Substituting the given values for ND and teq and the drain-to-gate voltage, VGD, in Eq. (7.9) gives the depletion width as

xdn1

2vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 3 u 6 u 1:44
10
20 ffi 3
1:25
106 4t1 þ  2  15 ffi 1:5 μm 1016
1:25
106

The total charge in the depleted region is Qb ¼ qN D xdn1 ffi 1:6
1019
1016
1:5
104 ffi 2:4
107 C=cm2 The field in silicon peaks at the surface and is approximated as   ESi ¼ Qb =ðε0 εSi Þ ffi 2:4
107 = 8:86
1014
11:7 ffi 2:3
105 V=cm The field in the oxide is found from the continuity of the displacement vector as Eox ¼ ESi
εSi =εox ffi 6:9
105 V=cm Similarly, the lateral and vertical depletion widths in the drift region, ydn2 and xdn3, are estimated by making step-junction approximation as in (3.11):

7.4 Off-State Analysis

317

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ε0 εSi ðV D þ V bi2 Þ ðV D þ V bi2 Þ cm ð7:10Þ cm ffi 3:6
102 ydn2 ¼ qN D ð1 þ N D =N A Þ N D ð1 þ N D =N A Þ sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ε0 εSi ðV D þ V bi3 Þ ðV D þ V bi3 Þ 3 cm ð7:11Þ xdn3 ¼ cm ffi 3:6
10 qN D ð1 þ N D =N sub Þ N D ð1 þ N D =N sub Þ where Nsub is the boron concentration in the substrate. Vbi2 and Vbi3 are, respectively, the built-in voltages at the vertical and horizontal junctions. Using the same procedure as in Example 7.3, the fields in silicon and oxide in the MOS region of Fig. 7.7 are approximated as a function of VD for teq ¼ 12.5 nm and different doping concentrations ND by assuming that the depletion regions do not overlap. The results are plotted in Fig. 7.8a, b.

Electric Field, Eox (MV/cm)

(b)

1.0 ND=1019 tox = 12.5 nm, 25 oC 0.9 0.8 1018 0.7 0.6 1017 0.5 1016 0.4 0.3 1015 0.2 1014 0.1 0.0 0 10 20 30 40 50 60 70 80 90 100 Drain Voltage, VD (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0

1.0 0.9 0.8 ND=1019 0.7 0.6 0.5 0.4 16 10 0.3 0.2 1015 14 10 0.1 0.0 10 20 30 40 50 60 70 80 90 100 Drain Voltage, VD (V) 1018

tox = 12.5 nm, 25 oC

1017

Electric Field, ESi (MV/cm)

Electric Field, Esi (MV/cm)

(a)

Fig. 7.8 (a) Peak electric field at the silicon surface of the MOS region as a function of drain voltage for teq ¼ 12.5 nm and different ND. (b) Electric field in the MOS oxide as a function of drain voltage for teq ¼ 12.5 nm and different ND

318

7 High-Voltage and Power Transistors

The markers in Fig. 7.8a indicate the onset of avalanche breakdown in silicon when the critical field is reached (Chap. 3). The lateral and vertical peak fields in junctions 2 and 3 are, respectively, Epeak-2 ¼

qN D ydn2 V=cm ε0 εSi

ð7:12Þ

Epeak-3 ¼

qN D xdn3 V=cm ε0 εSi

ð7:13Þ

where ydn2 and xdn3 are given, respectively, by Eqs. (7.10) and (7.11) and the numerators are the charge densities supported by each junction, expressed in C/cm2. For a sufficiently long and deep drift region, it follows from Eqs. (7.10), (7.11), (7.12), and (7.13) that when treated separately, the drift-to-body junction 2 will typically exhibit a lower breakdown voltage than that of the drift-to-substrate junction 3 (Fig. 7.7). This is because of the higher boron concentration in the P-body than in the substrate. Under the above assumptions where the depletion regions of both junctions do not interact with each other, the transistor breakdown voltage, BVDSS, is limited by the breakdown voltage of the drift-to-body junction: BV DSS ffi

ε0 εSi E2c V 2qN D

ð7:14Þ

where Ec is the critical field.

7.4.2

Reduced Surface Field, RESURF

When the depletion regions overlap, as shown in the simplified one-dimensional model of Fig. 7.9, part of the depleted charge is shared between junctions. Thus, the charge supported by each junction, and hence the electric field, is reduced, allowing Regions of depletion overlap

Gate oxide (tox)

P+

STI

N+

VD

xdn1

N+

tSTI

Ldrift P-well (NA)

ydp1 ydn2

N-drift (ND)

tdrift

xdn3 xdp2 Depletion Region Edges

P-substrate (Nsub)

y

x

Fig. 7.9 Drain-extended structure with overlapping MOS, lateral and vertical depletion regions shown

7.4 Off-State Analysis Fig. 7.10 Schematic field distributions at the surface and in the bulk for two tdrift values. (a) Very thick drift region (tdrift  xdn3): no interaction between depletion regions, breakdown occurs at the drift-to-body junction. (b) Thin drift region (xdn3  tdrift): optimized interaction between depletion regions, breakdown occurs at driftto-substrate junction

319 Epeak= Ec

BVDSS 1 N+

P-body ydn2

tdrift

y x

N-drift (ND) xdn3

Epeak < Ec

(a)

P-sub

BVDSS 2 > BVDSS 1 Epeak< Ec

P-body

Epeak< Ec Epeak = Ec

xdn3 ª tdrift ydn2 ª Ldrift

(b)

P-sub

a higher reverse voltage to be applied before the critical field for avalanche breakdown is reached. Since the field reduction typically occurs at or near the surface, the effect is referred to as REduced SURface Field or simply RESURF [8]. The RESURF concept offers the best trade-off between the breakdown voltage and the on-resistance of lateral high-voltage transistors. It provides an efficient way to integrate high-voltage transistors with low-voltage digital or analog circuits on the same chip. (a) Single-RESURF Technique Consider, for example, the basic structure in Fig. 7.10 where only the lateral junction 2 and the vertical junction 3 of Fig. 7.7 are shown. The depletion regions ydn2 and xdn3 in the drift region are shown expanded to focus on the RESURF effect (source and gate are not shown). Since, in this example, the depletion region of only one junction, the drift-to-substrate junction, interacts with the lateral drift-to-body junction, the technique is called single RESURF. Multiple RESURF structures are described in a later section. For a given ND, Nsub, and P-body concentration, the breakdown voltage is influenced by the thickness of the drift layer. When the drift region is sufficiently thick, there is negligible charge sharing between the two junctions (Fig. 7.10a).

320

7 High-Voltage and Power Transistors

Because of the higher concentration in the P-well than in the substrate, the peak field at the drift-to-body (P-well) junction reaches the critical field for avalanche breakdown earlier than at the drift-to-substrate junction. Thus, the transistor breakdown voltage, BVDSS, is limited by that of the drift-to-body junction. The electric field distribution for this case is shown in Fig. 7.10a. As xdn3 expands further and approaches the surface (xdn3  tdrift), either by reducing tdrift or Ndrift, most of the depleted charge becomes controlled by the horizontal drift-to-substrate junction. This effectively reduces the ionized impurity concentration in the drift region “seen” by the P-body. Consequently, to maintain the charge balance at the vertical junction, ydn2 must expand over a longer distance along the surface than would be expected from a simple one-dimensional analysis [8], considerably reducing the lateral field (Fig. 7.10b). A higher reverse voltage can thus be applied to the drain before the critical field is reached [8–10]. This is shown as region II in Fig. 7.11. Further reducing tdrift causes xdn3 to spread into the highly concentrated drain junction where it gets “pinned.” At this point, the field begins to increase linearly with increasing drain voltage. In addition, the two-dimensional field increases at the drain junction due to the curvature effect (Chap. 3). Thus, the breakdown voltage begins to decrease, as shown in region I of Fig. 7.11. The field distribution exhibits two peaks, one at the P-body junction and the other at the drain junction, with a moderate field between the two regions (Fig. 7.10b). Avalanche breakdown at the drift–drain interface can be avoided by increasing the length of the drift region, Ldrift. This is achieved, however, at the expense of the on-resistance. In an optimized structure, xdn3 reaches the surface before the drift-tobody junction breaks down, that is, before the peak fields in Fig. 7.10b reach the critical field Ec. The optimum single-RESURF technique is determined by four important parameters: the N-drift concentration, the N-drift thickness, the P-substrate concentration, and the P-body concentration. Assuming that the concentrations in the substrate and P-body are fixed, an optimum product ND
tdrift for maximum breakdown voltage 150

Breakdown Voltage, BVDSS (V)

Fig. 7.11 Breakdown voltage as a function of drift layer thickness for fixed values of Ndrift and Nsub. In region II, breakdown occurs at the drift-to-substrate junction, in region I at the N+ boundary, and in region III at the drift-to-body junction. (Adapted from Appels and Vaes [8])

Ndrift = 6 ×1015 cm-3 Nsub = 1.7 ×1015 cm-3 II

100 I III 50

0 0.2

0.5

1.0

2.0

5.0

Drift-Layer Thickness, tdrift (mm)

7.4 Off-State Analysis

321

can be found under the assumption that xdn3 reaches the surface just before the driftto-body junction breaks down. Setting tdrift ¼ xdn3 and combining this with Eqs. (7.10) and (7.14) give an approximate optimized product as N D
t drift

ε0 εSi Ec ffi q

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi N sub 1 12 cm2  1:94
10 N D þ N sub 1 þ N D =N sub

ð7:15Þ

When designing a high-voltage transistor, the main objective is to minimize the on-resistance while still achieving a high breakdown voltage. These two parameters, however, tend to have conflicting requirements with respect to doping and thickness of the drift region. While the process parameters contributing to the on-resistance are well understood, the breakdown voltage of high-voltage transistors typically requires numerical simulations. The product ND
tdrift determines the sheet resistance of the drift region defined by Eq. (7.8). The on-resistance is typically dominated by the drift resistance. The optimized thickness of the drift region, tdrift, and the corresponding sheet resistance are calculated from Eqs. (7.15) and (7.8) and plotted as a function of drift concentration in Fig. 7.12. Since the optimized tdrift and the electron mobility decrease as ND is increased, the net result is an increase in sheet resistance. From Fig. 7.12, it can be seen that a higher substrate doping, Nsub, allows an increase in the N-drift doping concentration ND, providing a lower N-drift sheet resistance. This is because, to maintain the same optimized N-drift thickness, ND must be increased to keep the same ratio ND/Nsub in Eq. (7.15). Increasing the substrate concentration, however, comes at the cost of increased capacitance and reduced breakdown voltage of the drift-to-substrate junction. To avoid impacting other components on the chip, the substrate concentration can be locally increased by selectively implanting a limited dose of boron below the drift region [11, 12]. (b) Double-RESURF Technique

100

100 Nsub = 1017 cm-3

10

1

10

0.1 Nsub = 1015 cm-3 0.01

1

1015

1016 N-Drift Concentration, ND (cm-3)

1017

N-Drift RS (kΩ/‫܆‬ ‫)܆‬

Fig. 7.12 Optimized drift thickness and corresponding drift sheet resistance versus doping concentration, shown for two Nsub values

N-Drift Thickness, tdrift (mm)

The range of trade-off between on-resistance and breakdown voltage can be expanded with a double-RESURF technique. This is particularly important in transistors with breakdown voltage above approximately 100 V where, otherwise, the drift region can be very long to sustain the voltage, causing a large increase in

322

7 High-Voltage and Power Transistors Depletion Edges

VD

Ptop , NA-top +

P

STI

N

+

P-well, NA MOSFET Body

ttop

xdp4 xdn4 Ndrift, ND

ydn2

-E

N

0

+E

+

xdn3 Ldrift

P-substrate, Nsub

y

x

(a)

(b)

Fig. 7.13 Double-RESURF structure [13]. (a) Schematic cross section. (b) Field distribution assuming full depletion

RDS(on). One configuration of a double-RESURF structure is illustrated in Fig. 7.13 [13, 14]. The noticeable change from the single-RESURF case is the addition of the P-top region. The P-top-to-N-drift and substrate-to-N-drift junctions contribute to depleting the N-drift region between the two junctions. To achieve a high breakdown voltage in this double-RESURF structure, both the P-top layer and the N-drift region must be fully depleted before the lateral breakdown voltage of the N+ drain-to-P-top junction is reached. Since typically NA-top > ND > Nsub, the breakdown will initially occur at the drain– P-top junction. Thus, the breakdown voltage is given by ε0 εSi E2c V ð7:16Þ 2qN D Using an analysis similar to that of single RESURF, the requirement that the P-top region be fully depleted before the lateral drain-to-P-top junction reaches the breakdown voltage sets the following constraint on the integrated P-top concentration: BV DSS ¼

1:94
1012 N A-top
t top  qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi cm2 N 1 þ NA-Dtop

ð7:17Þ

Because, for manufacturability, NA-top should have a minimum value equal to ND, this sets the maximum limit for the product in Eq. (7.17) as NA-top
ttop  1.4
1012 cm2. Since the drift region is simultaneously depleted from both the top and bottom junctions, the integrated concentration in the drift region between the two junctions can be increased by approximately a factor of 2, to about 2.8
1012 cm2, compared to a single-RESURF structure of the same drift thickness, and still be fully depleted before breakdown occurs. Thus, a lower drift sheet resistance can be achieved.

7.4 Off-State Analysis

323 VD xdn5

P+

STI

-E

N+

0

N+ Buried P Layer

P-well, NA MOSFET Body

Ndrift, ND

substrate, Nsub

Ldrift

xdn4 xdn3

(a)

y x

(b)

Fig. 7.14 Triple-RESURF structure [15]. (a) Schematic cross section. (b) Vertical field distribution at midpoint of Ldrift, assuming full depletion

(c) Triple-RESURF Technique A triple-RESURF structure is shown in Fig. 7.14 [15, 16]. A buried P-layer is implanted into the N-drift region, splitting the N-drift region into two paths, one on the bottom and one on the top of the buried layer. The depletion region surrounding the buried layer expands to xdn4 on the bottom and xdn5 on the top of the layer. Thus, three junction boundaries contribute to depleting the drift region, the drift-to-substrate junction, and the bottom and top junction boundaries of the buried layer. A simplified one-dimensional analysis similar to that done for the double RESURF shows that for an optimized structure, the integrated concentration in the drift region can be increased by approximately a factor of 3 compared to a singleRESURF structure and a factor of 1.5 compared to a double-RESURF structure, further reducing the drift sheet resistance and hence RDS(on). (d) Charge Balance Full depletion of the N- and P-regions implies perfect charge balance between the regions. Any charge imbalance causes one of the regions to conduct and hence a drop in the breakdown voltage. Thus, accurate charge control is required to achieve a reproducible breakdown voltage, particularly for double- and triple-RESURF structures. Since the integrated doping concentration in the P-top and N-drift regions is relatively low (1–3
1012 cm2), these devices are susceptible to surface charges in dielectrics, passivation, and molding compounds, particularly during hightemperature reverse-bias (HTRB) reliability testing [17] (Chap. 11). Without special precaution, charge imbalance can also be created by a field plate or a high-voltage interconnecting line routed over the transistor [18, 19]. The impact depends on the distance between the field plate or metal line from the silicon surface. The sensitivity to surface charge or field should be taken into account when optimizing the structure for manufacturing. The impact can be reduced, for example, by increasing the P-top dose in the double-RESURF structure, making it less sensitive to surface charge.

324

7 High-Voltage and Power Transistors

The outer edges of the structure are also potential sites of increased local field degrading the breakdown voltage [20]. This occurs because of junction termination effects, such as reduced radius of junction curvature at edges. In such cases, particularly in the case of very high-voltage devices, an appropriate junction termination extension must be implemented. Among the several suggested extension methods are selective ion implantation to modify the junction curvature [21, 22], shallow trench isolation [23], and deep trench isolation [24]. Additional techniques to increase the breakdown voltage of junctions and transistors are discussed in Sect. 7.7 in conjunction with superjunctions and LDMOS transistors.

7.5

Performance Considerations

As with every technology, key parameters are frequently traded-off against each other. This is particularly the case in high-voltage devices where, for example, there is a trade-off between breakdown voltage and specific on-resistance and between breakdown voltage and gate charge or switching speed.

7.5.1

Ideal RSP Versus BVDSS

When designing a high-voltage transistor, the main objective is to simultaneously achieve the lowest specific resistance and the highest breakdown voltage. Since the breakdown voltage typically decreases as ND increases and the drift sheet resistance increases as ND decreases, there is a trade-off between RSP and BVDSS. Consider a one-dimensional structure with a uniformly doped drift region as shown in Fig. 7.15a [11]. In this simplified model, the drain-to-source resistance is dominated by the drift resistance so that the source, drain, and channel resistances can be neglected. In Fig. 7.15 RSP versus BV analysis. (a) Simplified one-dimensional structure. (b) Linear dependence of electric field on distance for fully depleted drift region

(a)

Source + channel R≈0

Ecrit

(b)

Drain (N+) R≈0

N-drift Region, ND RDS(on) ≈ Rdrift

y

Ldrift Equipotential Lines Slope = qND/e0eSi

E(y) BV

y

Ldrift

7.5 Performance Considerations

325

addition, the transistor length (device pitch) is approximated by the drift length, Ldrift, and the drift region is fully depleted at breakdown. For a uniform concentration, the field depends linearly on distance, and the breakdown voltage is the area of the triangle in Fig. 7.15b (Chap. 3). With the above simplifying assumption, the specific resistance is approximated from Eq. (7.8) as RSP 

Ldrift mΩ-mm2 qμn N D

ð7:18Þ

The drift length is obtained from Fig. 7.15b as Ldrift  2BV=Ec cm

ð7:19Þ

where BV is the breakdown voltage given by (3.10a) as BV ¼

ε0 εSi E2c V 2qN D

ð7:20Þ

From Eqs. (7.18), (7.19), and (7.20), the specific resistance can be expressed as RSP ¼

4BV 2 mΩ-mm2 μn ε0 εSi E3c

ð7:21Þ

From Eq. (7.21) we can see that RSP is inversely proportional to the cube of the critical field, Ec. Thus, semiconductors such as silicon carbide (SiC, Ec ¼ 2.5–3.2MV/cm) and gallium nitride (GaN, Ec ffi 3.5 MV/cm) may offer a considerably lower RSP than silicon. Combining Eqs. (7.20) and (7.21) with Eq. (3.38) and manipulating the result give " RSP 

aε0 εSi q2 μ n



2q a2 ε0 εSi

2:5 # BV 2:5 mΩ-mm2

ð7:22aÞ

where from (3.38) a ¼ 4010. Assuming an electron mobility μn ¼ 1375 cm2/Vs and substituting the values for the constants give [11, 12] RSP  6:0
109 BV 2:5 mΩ-mm2

ð7:22bÞ

A plot of RSP versus breakdown voltage is shown in Fig. 7.16. This plot is frequently used for benchmarking high-voltage and power transistors. As the breakdown voltage increases, so does the specific on-resistance.

326

7 High-Voltage and Power Transistors

Fig. 7.16 Plot of specific on-resistance versus breakdown voltage for the idealized structure in Fig. 7.15

RSP (mΩ-mm2)

100

10

Ideal

1

0.1 1

10 BV (V)

100

VG VS

D

VD CGD

P+

N+

CGS

CGB

CGD

N+

RG

CDS

G P-body

N-drift

CGS

CDB

P-substrate

(a)

S

(b)

Fig. 7.17 Drain-extended NMOS showing capacitances related to QG. (a) Schematic cross section. (b) Circuit diagram

7.5.2

Switching Performance, RDS(on)
QG

When a voltage is applied to the gate terminal, there is a time delay required to charge the intrinsic gate capacitances before the device turns on. The gate interconnect resistance, RG, and the MOSFET capacitances, CGS and CGD, in Fig. 7.17 create an RC network that determines the voltage change at the intrinsic gate, hence affecting the switching speed (Fig. 7.17b). Thus, reducing the gate resistance is effective in reducing switching losses. Power devices, with a layout of long stripes, resulting in large device width, benefit from the low silicide sheet resistance of polysilicon gates. Nonetheless, frequent gate contacts should be made throughout the device to ensure that all stripes turn on simultaneously. The gate capacitances are shown in Fig. 7.17a. CGS is the gate-to-source capacitance including overlap, fringe, and channel, CGD is the gate-to-drain capacitance including overlap and fringe, CGB is the gate-to-body capacitance, and CDB is the

7.5 Performance Considerations

327

RL

VDS V IG A

D VDD

IG IGG

IDS

G

SW

S

VGS V

(a) QG

VGG

VDD

Miller Plateau

VG QGS

QGD

VD

VT

VD (on) ª 0 t0

t1 t2

t3

Time (ns)

t4

t2

t3

Time (ns)

(b) Fig. 7.18 (a) Gate charge QG measurement setup [25]. (b) Charging waveforms

drain-to-body capacitance. The capacitances are voltage dependent. Since typically source and body are shorted, CGB and CDB are referred to the source. A schematic diagram of a QG measurement technique is shown in Fig. 7.18a [25]. A load resistance RL  RDS(on) is connected between the drain and the DC power supply, so that when the transistor is on, most of the voltage drops across RL and the voltage at the MOSFET drain drops to near zero. With the switch closed, VGS ¼ 0 V and VDS ¼ VDD. Opening the switch forces a constant current, IGG, into the gate, charging the gate capacitances. Starting at time t ¼ t0 ¼ 0 where VGS ¼ 0, the gate voltage, measured with a high-impedance voltmeter, begins to increase as the gate is being charged (Fig. 7.18b). For t < t1, the gate voltage is below threshold and there is negligible current between drain and source. The drain voltage remains constant at VDD, so that I GG 

dQG ðt Þ dV GS A ¼ CGG dt dt

ð7:23Þ

where CGG ¼ CGS + CGD + CGB is the total gate capacitance. When VGS reaches VT at time t1, the MOSFET begins to conduct. As VGS continues to increase, the MOSFET conducts more, and the drain current increases until it reaches its maximum DC value IDS at time t2. Because the transistor has high gain in this interval

328

7 High-Voltage and Power Transistors

(a small change in VGS results in a large increase in ID), the difference in gate voltage between the point t2 (when the MOSFET is off) and t3 (when it is conducting the maximum load current) is relatively small, and most of the gate current actually goes into charging the MOSFET gate-to-drain capacitance. Because VGS remains nearly constant in this interval (dVGS/dt  0), the charge on CGS does not change significantly. The region between t2 and t3 is referred to as the Miller plateau. The rate of change in drain voltage depends on the changing value of the gate-to-drain capacitance. At t ¼ t2, the drain voltage begins to decrease due to the load current increasing, causing an IR drop across the load RL. In this biasing region, CGD is a highly nonlinear function of VDS and begins to increase as VDS decreases, following dV DS IG  V=s dt C GD

ð7:24Þ

At t3, VGS continues to increase in proportion to the charging current until it reaches its maximum value VGSmax. In summary, there are four time intervals in the waveforms of Fig. 7.18b: t0–t1 t1–t2 t2–t3

t3–t4

The input capacitances CGS and CGD begin charging, and VGS starts to rise until, at VT, the device begins to conduct VGS increases slightly from VT to a level needed for IDS to increase to IDD. CGS and CGD continue to charge VDS decreases from VDD to nearly 0 V. During this time, CGD is nearly completely charged. Although CGD is typically less than CGS, the total charge supplied to CGD can be higher because of the large voltage swing across it With the transistor fully on, any additional charge goes into raising VGS to VGSmax, decreasing the channel resistance, hence RDS(on). This completes the charging of CGS and CGD

The gate charge in any of the time intervals Δt is just the product of the time interval and the constant gate current ΔQG ¼ I G Δt C

ð7:25Þ

For very thin gate oxide, tunneling current through the oxide can become significant and must be taken into account when defining the gate current, IG. Example 7.4 The total gate-to-drain charge, QGD, is measured on a power MOSFET as 20 nC. For a constant gate current IG ¼ 1 mA, estimate the time required for the drain voltage to drop from VDD to near zero.

7.6 Design and Characteristics of DEMOS

329

Solution The gate-to-drain capacitance, CGD, is mostly charged during the interval t2 to t3 (“Miller plateau,” Fig. 7.18b). The time interval is found from Eq. (7.24) as t 3  t 2 ¼ QGD =I G ¼ 20 nC=1 mA ¼ 20 μs A convenient figure of merit (FOM) to quantify the transistor switching performance for a given off-state breakdown voltage, BVDSS, is the product RDS(on)
QG, where QG is the total charge induced on the gate. High-current, low-voltage switches are required to have very low power losses, such as in DC–DC converters for mobile devices [26]. In addition to the required low on-resistance and gate charge to reduce power losses, fast switching action can be achieved by reducing QGD, the charge induced on the gate during the Miller plateau, also called gate feedback charge. Thus, the product RDS(on)
QGD is another FOM frequently used to quantify the switching performance [27]. By reducing the gate-to-source and gate-to-drain overlaps and adding only a few process modules to a base CMOS technology, RDS(on) has been reduced, for a discrete device, to 2.1 mΩ, QG to 15 nC, and QGD to 3 nC, resulting in FOMs as low as RDS(on)
QG ¼ 30 mΩ-nC and RDS(on)
QGD ¼ 6 mΩ-nC for VG ¼ 4.5 V [28]. The reduction in gate overlaps comes, however, at the cost of a decrease in the on-state breakdown voltage due to saturation effects discussed in Sect. 7.8.2. Thus, there is also a trade-off between lowering QG and maintaining a high on-state BV. The key MOSFET transistor parameters affecting the efficiency of highfrequency converters are the gate charge, QG (or the gate-to-drain charge, QGD), and the on-state resistance, RDS(on). A significant fraction of switching loss in highfrequency power converters is contributed by the power required to supply the gate charge which must be induced into, and extracted from, the gate to turn the transistor on and off. It is hence important to reduce QG to improve the transistor switching speed and circuit efficiency. It is also important to maintain a low on-state resistance to minimize power losses in the drift region. For low-voltage transistors, operating in the range10–20 V, the channel resistance constitutes a large fraction of the total RDS(on). As the gate voltage is increased, the channel resistance and hence RDS(on) in Eq. (7.7) decrease appreciably, but not as fast as the gate charge increases. Hence, a plot of QG
RDS(on) versus VGS can show a minimum value at VGS below VGSmax, indicating a trade-off between switching speed and conduction power losses.

7.6

Design and Characteristics of DEMOS

The previous sections analyzed the properties of the drift region; the trade-off between the transistor breakdown voltage, BVDSS, and the specific on-state resistance, RSP; and the figures of merit to quantify the switching performance of

330

7 High-Voltage and Power Transistors

low-voltage power transistors. Although the discussions used a simple drainextended MOSFET for simplicity, they are applicable to both DEMOS and LDMOS configurations. This section extends the analysis to different design styles of DEMOS and their characteristics. Drain-extended transistors are typically constructed in a base CMOS technology without added complexity. They are used in analog and power management designs where high drain-to-source voltages are required. These voltages can range from 20 to 40 V in 130-nm and 180-nm processes and from 5 to 8 V in 65-nm processes and beyond [29, 30]. In DEMOS transistors, however, the gate-to-source voltage is limited by the CMOS gate oxide thickness which remains unchanged.

7.6.1

Complementary DEMOS

A schematic cross section of a drain-extended NMOS transistor (DENMOS) is shown in Fig. 7.19a. In this structure, there is no thick oxide in the drift region between gate and drain, such as STI or LOCOS. The structure is thus referred to as planar. The CMOS N-well constitutes the lightly doped drain extension and the P-well the MOSFET body. The silicide is blocked from the drift region to avoid shunting it at the surface (Chap. 9). Figure 7.19b shows the lateral P-well doping profile along the surface from source to drain, with the concentration fairly constant across the channel. The concentration is fairly constant, which is a characteristic that distinguishes the DEMOS from the LDMOS. The polysilicon gate edge on the drain side in Fig. 7.19a creates a high field in the oxide and silicon due to the small radius of curvature at the polysilicon corner. To avoid reliability degradation caused by the high field, the planar DENMOS is limited to applications requiring low voltages, typically 12 V or lower (Chap. 11).

Gate

Source

Body

Drain Silicide

STI

P+

STI N+

P-well (Body)

Channel

N+ STI NSD N-well (Drift region)

|ND – NA| (cm-3)

1020 Source

1019

Drain

1018 1017 P-well

P-substrate

1016

0

0.5

yjs

(a)

N-well

1.0 1.5 2.0 2.5 yD yjd Lateral distance (mm)

3.0 yÆ

(b)

Fig. 7.19 Planar DENMOS with N-well drift region. (a) Schematic cross section. (b) Lateral surface doping profile from source to drain

7.6 Design and Characteristics of DEMOS Fig. 7.20 Planar DEPMOS with isolating deep N-well and ring

331 Isolation ring

Gate Source

Body

Silicide

STI N+ STI P+ Channel N-well Body

Drain STI STI P+ STI

P-well Drift region

N+

N-well

Deep N-well P-substrate

Fig. 7.21 Field-gap DENMOS

Body

Source

Gate

Drain Silicide

STI P+ STI STI

N+

N+ STI STI

STI

P-well Channel (Body)

N-well (Drift) Field-gap

P-substrate

A complementary planar DEPMOS can also be built by switching doping and voltage polarities (Fig. 7.20). The P-well drift region must, however, be isolated from the substrate. This can be done vertically with a deep N-well and laterally with an N-well ring (Chap. 9). The remainder of this section uses a DENMOS for illustration, but the discussion is equally applicable to DEPMOS.

7.6.2

Field-Gap DENMOS

The enhanced field in the oxide and silicon can be reduced by placing a thick oxide layer, such as STI or LOCOS, in the drift region under the poly-edge between gate and drain (Fig. 7.21). Such a structure is sometimes referred to as a field-gap transistor. It allows operating the transistor at a higher voltage, e.g., 20–24 V. For the same reason, the field gap is also incorporated in LDMOS. The field reduction comes, however, at the expense of a slightly larger device size and higher RDS(on) because the thick oxide reduces the cross-sectional area of the drift region.

332

7.6.3

7 High-Voltage and Power Transistors

Subthreshold Current

Analog CMOS technologies offer dual or triple gate oxide thicknesses allowing the design of MOSFETs of higher threshold and operating voltages than in digital (core) CMOS. Since DENMOS transistors are often constructed with the thicker gate oxide, the threshold voltage is sufficiently high that the subthreshold off-current can be neglected, even under worst-case temperature conditions. An NMOS with an equivalent gate oxide thickness tox ¼ 13.5 nm, a channel length L ¼ 0.6 μm, and an average P-well concentration of 1.6
1017 cm3 would typically have at 25  C a threshold voltage VT ¼ 0.6 V and subthreshold slope of 70 mV/decade (Chap. 6). According to (6.36), the transistor would exhibit an off-current Ioff  2
1016 A/μm (neglecting junction leakage currents). From Fig. 6.24, the same transistor would exhibit at 150  C a threshold voltage VT ¼ 0.395 V, hence Ioff  2
1011 A/μm (per unit width), a negligible value even for a 1-cm-wide DENMOS array. A drainextended NMOS of the same channel length and width constructed with a core NMOS would have orders of magnitude higher off-current leakage, as can be seen from the following example. Example 7.5 Consider a 1-cm wide DENMOS constructed with a channel length L ¼ 1 μm and having a threshold voltage VT ¼ 0.35 V and a subthreshold slope of 70 mV/decade at 25  C. Use (6.36) and Fig. 6.24 to estimate the total DENMOS off-current at 150  C. Assume I0 ¼ 100 nA. Solution Assuming a temperature coefficient of 1.2 mV/K (Fig. 6.24), the threshold voltage at 150  C is VT(150) ¼ VT(25)  1.2
(150–25) ¼ 0.2 V. The “ideality factor” is n ffi 70/60 ffi 1.2. Substituting in (6.36) gives I off ¼ I 0

7.6.4

W V T =nkT 104 0:2=ð1:2
8:62
105
423Þ e e  107  105 A 1 L

Asymmetric and Symmetric DEMOS

An asymmetric drain-extended MOSFET has the drift region only on the drain side of the channel (Fig. 7.19a). In this arrangement, the high voltage can only be applied to one side which constitutes the drain. By contrast, in a symmetric DEMOS, the drift region is placed on both sides of the transistor so that source and drain can be interchanged (Fig. 7.22). The symmetric DEMOS is less frequently used than the asymmetric. It has considerably higher RDS(on) and is larger in size.

7.6 Design and Characteristics of DEMOS

Body, Substrate

STI

P+

333 Gate

Source, Drain

Source, Drain

N+

STI

N+ N-well (Drift)

P-well

P-well (Body)

STI

N-well (Drift)

P-well

Channel P-substrate

Fig. 7.22 Schematic cross section of a symmetric planar DENMOS

Equipotential line

P-well P+ to N+ source (Body) P-well Gate

+V

N-well N+ drain Si

Si

STI Si

N

STI Oxide

Si

STI P

Si STI Si STI

Depletion boundary

Si (a)

(b)

Fig. 7.23 Dielectric RESURF applied to a planar DEMOS device. (a) Equipotential lines. (b) Application to DENMOS. (Adapted from Sonsky and Heringa [31])

7.6.5

Dielectric RESURF

Figure 7.23a illustrates the principle of dielectric RESURF [31]. A PN junction is bounded by two oxide-filled STI regions. When a reverse voltage is applied to the junction, the equipotential lines not only distribute within the silicon but also penetrate the oxide, creating fringe fields along the junction edges and adding fringe capacitances to the junction capacitance within the silicon. Charging of the fringe capacitance has to originate within the depletion region. The total charge is thus shared between silicon and oxide, so that the fraction of charge in silicon decreases.

334

7 High-Voltage and Power Transistors

To maintain the charge balance, the depletion region must expand, reducing the field in silicon and increasing the breakdown voltage. The effect becomes more pronounced as the silicon stripe is narrowed and the oxide stripes are widened. The main advantage of the above dielectric RESURF technique is that it can be implemented without additional processing steps. The concept has been applied to a planar DEMOS by interleaving the drift region with STI, as illustrated in Fig. 7.23b [31]. The increase in BVDSS comes, however, at the cost of higher RSP due to either an increase in RDS(on) or an increase in device area. By extending the polysilicon gate in the form of stripes over the STI fingers, additional fringe fields can be created that further increase the breakdown voltage without increasing RDS(on) [32]. This approach, however, relies on additional fringe capacitances from the polysilicon sides to the surface of the drift region and from the bottom of polysilicon stripes laterally to the sides of the drift region, increasing the gate charge, QG.

7.6.6

Key Dimensions

Key dimensions affecting DEMOS characteristics are shown in Table 7.2 and Fig. 7.24. A field-gap DENMOS is chosen for illustration. The width of the device in Fig. 7.24 is normal to the page.

Table 7.2 Key dimensions of field-gap DENMOSa Label D1 D2 D3 a

Description Channel length STI-to-channel distance Gate overlap STI

Label D4 D5 D6

Description Approximate drift length Drain-to-substrate distance Approximate device pitch

A field gap is a thick oxide, STI or LOCOS, under the gate edge in the drift region

Gate Source

Body STI STI

P+

STI

N+

Drain

D1

D2

STI

D3

LDD

D4

P-well (Body)

D6

P-substrate

Fig. 7.24 Key dimensions of field-gap DENMOS

N+ NSD

STI STI

D5 N-well (Drift)

7.7 Design and Characteristics of LDMOS

Legend = ref [5] = ref [33] = ref [34] = ref [32]

100 RSP (mΩ-mm2)

Fig. 7.25 Published specific on-resistance versus breakdown voltage for DENMOS and ideal plot from Fig. 7.17. Data obtained on a 180-nm BCD technology [5, 33], 130-nm BiCMOS technology [34], and 65-nm technology using dielectric RESURF [32]

335

10

Ideal

1 5 V NMOS Reference point

0.1 1

7.6.7

10 BVDSS (V)

100

Specific On-Resistance Versus Breakdown Voltage

Published results on RSP versus BVDSS obtained on DENMOS are shown in Fig. 7.25. As for the ideal case, the specific on-resistance increases as BVDSS is increased. For the same BVDSS, however, the measured specific on-resistance is considerably higher than for the idealized case. This is mainly because the actual “overhead” area for body contact and junction termination is not included in the ideal plot. The fraction of “overhead” area decreases for higher-voltage devices, bringing the points closer to the ideal plot. Such a plot is frequently used to compare technologies and transistor designs (benchmarking). The aim is to have the points as close as possible to the idealized plot. This can be achieved by techniques described in the following sections.

7.7

Design and Characteristics of LDMOS

The LDMOS transistor, particularly the N-channel LDMOS (NLDMOS), is considered as the device of choice for the integration of high-power transistors with low-voltage digital MOSFETs. It is a key component in BCD technologies. This section discusses the various LDMOS design types, their key features, and tradeoffs, focusing on devices that are optimized to operate in the range 20–700 V. For very high-power applications, the vertical DMOS or insulated-gate bipolar transistor (IGBT) is preferred [35], but these typically share a common drain when integrated on a chip and are not discussed here.

7.7.1

NLDMOS Configurations

Schematic cross sections of two types of field-gap NLDMOS featuring a common source–body contact and a dedicated P-body layer are shown in Fig. 7.26. This

336

7 High-Voltage and Power Transistors Gate Drain STI

N+

Gate Source/Body N++

STI

P+

Drain

N+

STI

P-body

(a) P-well

N+ N-well (Drift)

Channel

STI STI P-well

P-substrate Gate

Gate

Drain STI (b) P-well

N+ N-well (Drift)

Source/Body STI

N+

P+ P-body Channel

N+

Drain STI

N+ STI STI N-well (Drift)

P-well

P-substrate

Fig. 7.26 Field-gap NLDMOS with shorted source–body contacts and dedicated P-body. Two transistors are shown symmetrically designed with respect to the source–body contact. (a) Common N-well drift region. (b) Dedicated N-drift region

three-terminal device is common for LDMOS, particularly in BCD processes. The shorted source–body contact saves space and minimizes debiasing effects because of the shorter distance between source and P-body contacts. In each cross section of Fig. 7.26, two transistors are shown symmetrically arranged with respect to the source–body contact. In Fig. 7.26a, a common N-well forms the drift region for both transistors, simplifying the process [1, 36–38]. Since the N-well is also implanted under the P-body, the substrate and P-body are disconnected from each other. The integrated N-well concentration under the P-body is, however, too small to prevent punch-through between P-body and substrate when a reverse voltage of more than a few volts is applied between the drift region and P-body. Thus, the structure may not be used in circuits where a high reverse bias is applied to the source–body terminal with respect to substrate. In this configuration, the structure is referred to as a lowside NLDMOS (LS-NLDMOS). In Fig. 7.26b, a dedicated N-drift region is placed under each drain, optimizing BVDSS versus RSP [2, 5, 33]. In this configuration, however, the P-body is shorted to substrate and the structure is only used in circuits where the source and body are at ground. The structure is again referred to as a low-side NLDMOS. A cross section of another NLDMOS constructed on a heavily doped N-buried layer (NBL) is shown in Fig. 7.27. The NBL is formed by locally implanting arsenic or antimony at a high dose into the substrate, followed by growing a P-type epitaxial layer at the desired

7.7 Design and Characteristics of LDMOS

337

Gate

(a)

Gate

Drain

STI

Source/Body

N+

N+

P-epi

N+

STI

P-body

N-drift

N-well

P+

N+

STI

Drain

N-drift

STISTI

N-well

Channel N+ Buried Layer P-substrate

(b)

Common N+-source and body

N+-Drains

Gates

2×Pitch Device width

(c)

Contact

GatePoly S

D

S

D

S

D

S

D

S

D

S

D

Meta-2

Source Buss

Via

Metal-1

Drain Buss

S

D

S

D

S

D

S

D

S

D

S

D

Fig. 7.27 NLDMOS with N-buried layer (NBL). (a) Schematic cross-section of two transistors designed symmetrically with respect to the source-body contact. (b) Top view of single large device. (c) Top view of a large array of devices

thickness and concentration1 (Chap. 9). An N-well ring isolates the P-body laterally from the substrate. The integrated doping concentration in the NBL is sufficiently 1

Epitaxy is the process of growing a single-crystal film on a single-crystal substrate.

338

7 High-Voltage and Power Transistors

high to prevent punch-through between the P-body and substrate even when a reverse voltage as high as the operating voltage, VDD, is applied to the junction. This configuration allows the LDMOS to be used in circuits where the source–body terminal needs to be pulled up well above the substrate potential. The vertical distance between NBL and P-body must also be sufficiently large to prevent premature junction avalanche breakdown. The structure in Fig. 7.27a is referred to as a high-side NLDMOS (HS-NLDMOS). A high-side NLDMOS can also be built by implanting phosphorus at high energy to form a deep N-well, thereby eliminating the need for an epitaxial layer to form the NBL (Chap. 9). A high LDMOS current-carrying capability can be obtained by increasing the device width. For example, the symmetrically arranged structure in Fig. 7.27a can be designed in the form of a 150–200-μm-wide structure shown schematically in Fig. 7.27b. This unit can be replicated to form an array of total device width in the centimeter range, with a current-carrying capability in the low ampere range and an on-chip power dissipation of typically 350–450 mW (Fig. 7.27c). For simplicity, the array in Fig. 7.27c is shown for only two levels of metal (2LM), with wide metal-2 busses to carry the current. The power buss architecture is a crucial consideration in power chip designs, requiring more complex 3–4 levels of metal for layout compactness and uniform distribution of current across the structure [39–41]. Several problems arise from the use of thin metal for power bussing. Among them are the metal resistance in series with the array source and drain, increasing the overall RDS(on). A more insidious problem is the nonuniform IR drop across the metal, reducing the effective VDS in parts of the array. A third factor that limits the current is electromigration in the metal, discussed in Chap. 11. To mitigate these effects, the power buss is typically designed with the uppermost metal level consisting of 3–4 μm thick aluminum or 5–15 μm electroplated copper [42], with the objective of directing the current vertically from silicon to the low-resistance buss as quickly as possible. (a) Isolated-Drain LDMOS One drawback of the configuration in Fig. 7.27 is the increased drain area and hence the capacitance between drain and substrate. Also, the LDMOS is commonly used in circuits, such as DC–DC converters, where external or parasitic inductances, combined with circuit operating conditions, can result in a sufficiently large forward bias, injecting electrons from the drain into the substrate and causing latch-up and other reliability problems in circuits on the chip. One method to reduce these effects is to disconnect the NBL and isolation ring from the drain. This is achieved vertically by placing P-buried layer (PBL) between drain and NBL of sufficiently high concentration to suppress punch-through between N-drift and NBL and laterally by increasing the distance between the drain and N-well ring (Fig. 7.28). This structure is called an isolated-drain LDMOS. The separation between the drain and N-well ring requires a fifth terminal to the structure and increases its size. The maximum voltage that can be applied to the drain can be limited by the NBL–PBL breakdown voltage.

7.7 Design and Characteristics of LDMOS

339 Gate

Gate Drain STI

Source/Body STI

N+

N+

STI

N+

P-body

N-drift

N-well P-well

P+

P+ Buried Layer

STI

N+

N-drift

P-epi

Isolation

Drain

N+

P-well N-well

P+ Buried Layer

N+ Buried Layer P-substrate

Fig. 7.28 Isolated-drain LDMOS with P-buried layer under N-drift. Two transistors are shown symmetrically designed with respect to the source–body contact Gate

Gate

Drain STI

P+

Source/Body P+

STI

N+

P+

Drain STI

P+

Isolation STI STI

N+

N-body P-drift

P-drift P-epi

N-well

Channel

N-well

N+ Buried Layer (NBL) Isolation

P-substrate

Fig. 7.29 Schematic cross section of PLDMOS. Two transistors are shown symmetrically designed with respect to the source–body contact

7.7.2

PLDMOS

The discussion of the NLDMOS also applies to PLDMOS by switching doping and voltage polarities. A PLDMOS structure is shown in Fig. 7.29. Punch-through between P-drift and substrate is suppressed laterally by the N-well ring and vertically by the NBL (or a deep N-well). When the source–body terminal is biased at a high potential, the N-well ring and NBL are biased at the same potential as the source– body, typically at VDD. PLDMOS transistors are less frequently used than NLDMOS because of their higher RSP. In some applications, however, PLDMOS transistors are more advantageous when used in a high-side switch (Sect. 7.10) and also due to their higher hot-carrier reliability (Chap. 11). One of the advantages of the PLDMOS transistors is the simplification of a half H-bridge design by replacing the high-side (“pull-up”) NLDMOS, eliminating the need for a charge pump to drive the gate (Sect. 7.10). However, because holes have a considerably lower mobility than electrons, the width of PLDMOS channel must be designed 2–3 times larger than NLDMOS to yield the same drain current. Thus, the specific on-resistance, RSP, is higher. The structure may also require additional masking and implantation steps for the drift and body layers (Chap. 9).

340

7 High-Voltage and Power Transistors

Fig. 7.30 (a) NLDMOS lateral surface doping profile. (b) Modeling approximation of the LDMOS

1020 1019

Source

(a)

|ND – NA| (cm-3)

N+ drain 1018 Channel

1017 1016

yjd

yjs

Drift region

1015 1014

0

0.5

1.0 1.5 Lateral distance (mm) G

2.0

(b) … S

D VT1 > VT2 > VT3 >

7.7.3

B

> VTn

Laterally Graded Channel

The double diffusion in LDMOS results in a laterally graded doping profile in the channel (Fig. 7.30a). Modern angled implant techniques also allow forming a graded profile without resorting to the double-diffusion method [43, 44]. The doping gradient provides several benefits including an increased VT at the source end, minimizing Ioff, while keeping a low doping concentration at the drain [45–47]. Reducing Ioff is particularly important for structures with large width, operating at high temperatures. The graded doping profile creates a lateral field that enhances inversion carrier velocity at the source end, realizing higher drain current and transconductance than for a uniformly doped channel of the same dimensions [48, 49]. The high channel concentration at the source side suppresses drain-tosource punch-through, allowing the design of shorter channels. The low concentration at the drain side decreases the field at the drain, reducing the substrate current and improving hot-carrier reliability [45–47]. The MOSFET can be considered as consisting of elemental transistors of varying channel concentration, threshold voltage, and effective mobility, in series (Fig. 7.30b). Going from the MOSFET source to drain, the drain of each elemental MOSFET constitutes the source of the next. Typically, the threshold voltage of each elemental transistor decreases from the source to the drain end of the graded channel. The transconductance dependence on gate voltage is shown for a laterally asymmetrical MOSFET with a graded channel in Fig. 7.31 [49]. The transconductance is high, and its dependence on gate voltage exhibits a sharp peak which is a characteristic of the graded channel [48, 49].

7.7 Design and Characteristics of LDMOS 0.5

Transconductance, gm (S)

Fig. 7.31 Dependence of transconductance on gate voltage in a graded channel MOSFET. (Adapted from Buti et al. [45])

341

Graded Channel at Source Side L = 1 mm W = 10 m m VD = 0.1 V VB = 0 V

0.4

0.3

0.2

0.1 0

0

2 1 Gate Voltage, VG (V)

Fig. 7.32 Section of vertical SJ-MOSFET with N-pillar sandwiched between two P-pillars [56]. Current lines shown for the on-state and lateral field for the off, fully depleted state

Gate

Source

3

Source

N+

N+

P-body

P-body ID

N

ID

3.53

P-pillar

E < Ec N-pillar

P-pillar

N+-Drain

7.7.4

The Superjunction Concept

The primary advantage of a superjunction MOSFET (SJ) is its potential for reducing the specific on-resistance for a given breakdown voltage of a power device [50–54]. In a standard high-voltage structure, to achieve a high breakdown voltage requires a thick and lightly doped drift region, leading to the familiar relationship RSP  6
109BV2.5 in Eq. (7.31b) [11]. This limitation can be overcome by replacing the “conventional” N-region by a set of alternating N-type and P-type “pillars” that are considerably higher doped than the typical drift region, resulting in a lower on-resistance in discrete power devices [50–55]. The vertical structure in Fig. 7.32 is used to describe the superjunction concept, applied to a discrete device [56]. The N-pillars are connected to the drain and the P-pillars to the source through the P-body of the MOSFET. When a reverse voltage is applied to the drain, the back-to-

342

7 High-Voltage and Power Transistors

back PN junctions are mutually depleted. The width and doping concentration of the pillars are optimized so that both pillar types fully deplete before the critical field is reached. For silicon, the average critical integrated charge in the depleted region along a line perpendicular to the current path is approximately 2
1012 charges/cm2. Once full depletion is reached, the equal but opposite charges within the pillars compensate each other, resulting in nearly uniform horizontal field in the N-drift (and P) region. Thus, the superjunction principle is based on perfect charge compensation between the two pillar types. When the N-regions are fully depleted, the vertical drain-to-source field depends only on the depth of the drift region. Thus, to increase the breakdown voltage, only the depth of the columns is increased without the need to reduce the dopant concentration. Since the maximum integrated doping concentration is fixed, the doping concentration in the N-regions can be increased inversely proportional to the drift width. This leads to a linear relationship between BVDSS and RSP [57, 58]. A more detailed analysis shows RSP to depend on BV7/6 [54, 55, 59]. Although the P-pillars reduce the area available for the N-pillars, the ability to use more heavily doped N-pillars results in a considerably reduced on-resistance. In summary, vertical superjunction transistors allow high breakdown voltage due to perfect charge compensation and low RDS(on) by increasing the doping concentration in the N-pillars. The above discussion of the vertical DMOS also applies to superjunction lateral DMOS (SJ-LDMOS) (Fig. 7.33) [60–63]. The breakdown voltage is very sensitive to charge imbalance. Perfect charge compensation by N- and P-pillars is, however, difficult to achieve, particularly for narrow pillars due to interdiffusion of species [61]. Also, for an LDMOS constructed on a P-type substrate, PN junctions are formed between the N-pillars and both the substrate and the P-pillars. Thus, in the off-state, the lower regions of the N-pillars are depleted by both the P-pillars and the substrate, while the P-pillars are only depleted by the adjacent N-pillars. This results in a charge imbalance between the pillars and a significant drop in BVDSS which increases as the charge imbalance increases, even if the pillars have exactly the same integrated doping concentration [62, 63]. Fig. 7.33 3D view of a SJ-LDMOS. (Adapted from [60, 62, 63])

SourceBody

Drain

Gate P N

P

P

N

N P+ N+ P-Body

N+

P-substrate

P N

7.7 Design and Characteristics of LDMOS

343

To reduce the effect of substrate depletion on breakdown voltage, SJ-LDMOS on a silicon-on-sapphire substrate and a combination of superjunction and RESURF LDMOS are proposed [64, 65]. Another approach is to design shallow pillars and place an “N-buffer layer” between the pillars and the substrate in Fig. 7.33 such that the buffer layer merges with the N-pillars [63]. As the drain voltage is increased in the off-state, the P-pillars are initially depleted by both the N-pillars and N-buffer layer, whereas in the structure of Fig. 7.33, the P-pillars are depleted by only the N-pillars. When the N-buffer layer is fully depleted, the P-substrate begins contributing to fully depleting the N-pillars. With the combination of vertical and lateral depletion of both pillar types, the charge imbalance observed in the SJ-LDMOS in Fig. 7.33 is reduced. Vertical trench gate MOSFETs that compete in performance with integrated superjunction MOSFETs in the low-voltage (50–120 V) and high-current range (1–10 A) are described in [66]. The polysilicon-filled trench gates extend deep into the drain. The integrated doping concentration in the drift regions between trenches is optimized so that the drift regions are fully depleted by the field of the polysilicon gates in the off-state. The specific on-resistance, RSP, is about 51 mΩ-mm2 for BVDSS ¼ 113 V [63] and 33 mΩ-mm2 for BVDSS ¼ 94 V [66].

7.7.5

Key LDMOS Dimensions

Key LDMOS dimensions are shown in Table 7.3 and Fig. 7.34. A field-gap NLDMOS is chosen for illustration. The device width is normal to the page. Since the LDMOS is a power device, its width can be large. Thus, there is a need for multiple body contacts to minimize IR debiasing in the P-body region. The integrated source–body contact in Fig. 7.34b allows frequent body contacts with minimal increase in area [67]. The device pitch depends on the array configuration. For transistors that are symmetrically arranged with respect to the integrated source/body contact and have common drain, the device pitch is approximately the distance between the center of the body contact and the center of drain. For a 24-V LDMOS transistor, the pitch typically ranges from 2.5 to 4 μm. As the operating voltage increases, the pitch must increase because of the longer drift region required to sustain the voltage.

Table 7.3 Key dimensions of field-gap NLDMOS Label D1 D2 D3 D4

Description Channel length STI-to-channel distance Gate overlap STI Approximate drift length

Label D5 D6 D7 D8

Description N-well-to-N-well distance NBL-to-NBL distance Integrated body contact width Body contact–poly distance

344

7 High-Voltage and Power Transistors

D8

Gate

Source/Body

N+

Drain P+ D7

N+

D1

D2 D3 STI

N+

Substrate

STI

P+

STI

P-well

P-body

D4 N-drift

(a)

N-well

D5

N-well

N+ Buried Layer (NBL) D6 P-substrate

Contact

D8

(b)

Gate right

Gate left

D7 P+-body contact

Common N+-source

Fig. 7.34 (a) Key dimensions of field-gap NLDMOS. (b) Top view of an integrated source–body contact

7.7.6

SOI Devices

The term “silicon-on-insulator” (SOI) is commonly used to describe wafers consisting of a single-crystal top silicon film separated from a single-crystal silicon support wafer by a buried oxide (BOX) film [68]. Depending on the application, the top silicon film thickness can range from 50 nm to several microns. If needed, it can be thinned down to the desired thickness by blanket or selective oxidation and etching or thickened by epitaxial growth. The BOX thickness typically varies from 0.1 to 3 μm. The thickness of the support wafer can be independently reduced, e.g., by polishing. The doping concentration and type of the top silicon and support wafer can also be independently varied. SOI wafers are typically formed by direct bonding

7.7 Design and Characteristics of LDMOS

345

and etch back, or the “smart-cut” technique [68]. Another configuration, which is not as frequently used as SOI, is silicon-on-sapphire (SOS). SOI offers several advantages over bulk silicon, including full dielectric isolation in conjunction with STI and/or deep trenches, suppressing parasitic bipolar effects, latch-up, and substrate noise; high BVDSS transistors with very low on-resistance [69–73]; the ability to construct power devices operating at high temperature [74–82] and medium-to-low-voltage power devices with very low on-resistance; process simplification; elimination of epitaxy; higher level of integration; higher performance [80, 83]; and restriction of off-state leakage current due to thermal generation in the isolated regions (Chap. 3) [74, 84]. The main disadvantages of SOI are the wafer cost and the higher thermal resistance compared to bulk silicon because of the considerably lower thermal conductivity of the buried oxide (0.014 vs. 1.412 W/cm-K) [85]. (a) SOI LDMOS One method to increase the vertical and lateral breakdown voltage in a thin-film SOI NLDMOS utilizes the RESURF effect of the buried oxide and an optimized lateral profile in the drift region (Fig. 7.35) [70, 72]. The doping profile in the drift region is optimized such that the lateral field in the depleted drift region is uniform [70]. The doping concentration in the drift region increases monotonically from the boundary next to the channel to the drain boundary. As with the original single-RESURF structure reported in [8], the integrated doping concentration in the top silicon film is such that when a reverse voltage is applied to the drain with the body externally shorted to the substrate, the drift region is fully depleted by the substrate which acts as a field plate or back gate beneath the BOX. Full depletion by the substrate results in a large lateral depletion width and low lateral field. For this bias condition, the substrate surface under the buried oxide is accumulated and the breakdown voltage depends only on the avalanche multiplication within the drift region or the dielectric strength of the buried oxide. A breakdown voltage in excess of 700 V has been

Fig. 7.35 SOI RESURF N-channel LDMOS structure shown with only P-body, drift, and drain regions

Body

P

ydp

Drain +V

ydn ª Ldrift N-drift

xdn Top silicon

N+

Buried Oxide (BOX)

Accumulation N-Substrate

346

7 High-Voltage and Power Transistors

Fig. 7.36 Cross section of SOI double-RESURF NLDMOS [72]

Gate (Top field plate) Source/Body +V N+

LOCOS

P+

N-drift

N-body

P+ P

BOX

Substrate

demonstrated on an N-channel LDMOS structure constructed on SOI with 0.1-μm top silicon thickness and 2-μm BOX [70]. The structure in Fig. 7.35 was extended to an SOI double-RESURF LDMOS with a LOCOS field gap and about 1.5-μm top silicon and 2-μm thick BOX, resulting in a dual field plate design (Fig. 7.36) [72]. The thinned drift region under the LOCOS field gap is highly doped and controlled by two field plates, one on the top consisting of an extended polysilicon gate and the other at the bottom consisting of the substrate under the BOX. This combination allows a high vertical field in the BOX and a lateral field in the drift region exceeding 20 V/μm before avalanche breakdown and resulting in a low RSP of 7.6 Ω-mm2 for 600 V [72]. (b) SOI PLDMOS The design of a PLDMOS structure similar to that of Fig. 7.36 but with reversed doping polarities is reported in [86, 87]. When the PLDMOS is used as a highside transistor, the high voltage is applied to the source and body, while the drain and substrate are grounded. Because of the change in doping polarities and applied voltage, the RESURF for PLDMOS can only be achieved with the top field plate. Also, the depleted charge in the P-type drift region creates a negative charge that enhances the vertical field above the BOX toward the surface of the drift region. Therefore, the doping concentration in the PLDMOS drift region must be reduced. The structure is limited to 120 V for which an RSP of about 2.2 Ω-mm2 is achieved for a LOCOS drift length of about 9 μm. Other SOI PLDMOS configurations are reported that use multiple field plates [88, 89] and deep trench field plates [90, 91].

7.7.7

LDMOS Trade-Off Between RSP and BVDSS

There is a trade-off between the LDMOS RSP and BVDSS, similar to the trade-off discussed for DEMOS. Typical NLDMOS RSP versus BVDSS data are shown in Fig. 7.37.

7.8 High-Voltage and High-Current Effects Fig. 7.37 NLDMOS RSP versus BVDSS. (a) BVDSS values below 150 V. (b) BVDSS values above 150 V

347

Legend = ref [1] = ref [5] = ref [33] = ref [37] = ref [2,73] = ref [4] = ref [38] = ref [62] = ref [69] = ref [71]

(a)

RSP (mΩmm2)

100

10

1

+ + +

+

ideal

0.1

(b)

RSP (mΩmm2)

1

10 BVDSS (V) Legend = ref [14] = ref [15] = ref [16] = ref [74] = ref [75] = ref [76] = ref [68] = ref [55] = ref [56]

104

100

ideal

103 102

BVDSS (V)

103

The values are presented in two groups for clarity, one group in Fig. 7.37a for BVDSS values below 150 V and the other for BVDSS values above 150 V in Fig. 7.37b. Most of the data points lie on the left of the ideal line. As in the DEMOS case, data points for lower voltages lie further away from the ideal plot than for higher voltages. This is because as the breakdown voltage increases so does the drift length and hence the device pitch. Thus, the fraction of a nearly constant “overhead area,” such as contacts and junction termination, decreases. Notable data points are those that lie on the ideal line [77–79]. The point that exceeds the “silicon limit” on the right of the ideal plot is for an integrated vertical trench gate MOSFET [66].

7.8

High-Voltage and High-Current Effects

There are two important effects in DEMOS and LDMOS devices that are not observed in conventional MOSFETs, notably quasi-saturation (QS) that describes the compression of output characteristics at high currents and the Kirk effect that leads to a second peak in impact ionization and substrate current.

348

7 High-Voltage and Power Transistors

In addition, self-heating effects (SHE) are more pronounced in high-power devices than in conventional MOSFETs. This section focuses mainly on LDMOS highvoltage and high-current effects.

7.8.1

Quasi-saturation, QS

High-voltage drain-extended and double-diffused transistors with long drift regions typically exhibit a limitation in the output current level that can be achieved. This is manifested in the compression of output characteristics at higher current levels, showing a decreasing sensitivity of drain current to an increase in gate voltage (Fig. 7.38). This effect is referred to as quasi-saturation [92, 93]. The onset of quasi-saturation can be defined as the gate voltage above which the transconductance gm ¼ dID/dVG drops significantly or the gate voltage at which the drain current does not saturate with drain voltage [93]. Quasi-saturation is a complex phenomenon where several parameters interact at its onset [93]. Among these are the velocity saturation, the Kirk effect, the mobility degradation with increasing field, temperature effects, and the interaction between the voltage at the drain boundary and at the K-point (Fig. 7.39). To simplify the discussion, the structure is conveniently divided into two regions, an intrinsic MOSFET controlled by the gate and a resistor, Rdrift, representing the drift region in series with the MOSFET (Fig. 7.39) [7]. It has been shown that quasi-saturation results from velocity saturation, caused by the high field in the drift region (Chap. 2) [94]. For a given drain voltage on the LDMOS, the transconductance (rate of increase in drain current with gate voltage) decreases as the gate voltage increases because of the increased IR drop in the drift region, reducing VK in Fig. 7.39a and forcing the intrinsic MOSFET to move from the saturation to the linear mode [82]. The intrinsic MOSFET is laterally delimited by the source boundary at the channel on one side and key point K at the boundary between the P-region (P-body, P-well, or P-substrate) and the drift region. A simplified circuit model is shown in Fig. 7.39a. The substrate, MOSFET body, and source are assumed to be at ground. The potential at point K with respect to source is VKS, where V KS ¼ V DS  V DK V

ð7:26aÞ

VDS is the externally applied voltage between LDMOS drain and source, and VDK is the voltage across the drift region. The key point K is only accessible by simulation or specially designed structures. The transfer characteristics of the intrinsic MOSFET are shown in Fig. 7.39b. Current continuity requires that the drain-tosource current, IDS, in the MOSFET be the same in the drift region. Thus,

7.8 High-Voltage and High-Current Effects

(a) 0.8

VDS=10 V 9V 8V 7V

0.7

Drain current, ID (mA/mm)

Fig. 7.38 I–V characteristics of an LDMOS device exhibiting quasi-saturation. (a) Drain current showing insensitivity with respect to gate voltage for different drain voltages. (b) Drain voltage-dependent drain current for different gate voltages [93]

349

0.6 0.5 0.4 0.3 0.2 0.1 0 0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Gate voltage, VGS (V)

(b) 0.8 VGS = 3.5 V

Drain current, ID (mA/mm)

0.7 0.6

Quasi saturation

2.5 V

0.5 2.0 V 0.4 0.3

1.5V

0.2 0.1

1.0 V

0 0

2

4

6

8

10

Drain voltage, VDS (V)

V KS ¼ V DS  I DS Rdrift V

ð7:26bÞ

The above equation and Fig. 7.39b show that Rdrift affects both VK and the MOSFET transfer characteristics. The drift resistance is, however, not constant but depends on several factors, in particular the drain current, field-dependent carrier mobility, and the carrier velocity saturation [95, 96]. To sustain the high voltage, Ldrift can be several microns. As discussed in Chap. 2, carrier velocity increases with the applied electric field, but ultimately saturates at approximately 107 cm/s for electrons at a field of about 8
103 V/cm. To put this in perspective, 1 V dropped across 1 μm creates a field of 104 V/cm. Hence, electrons can quickly reach velocity saturation in the drift region.

350 Fig. 7.39 (a) Simplified NLDMOS circuit model for quasi-saturation analysis. (b) Intrinsic MOSFET output characteristics

7 High-Voltage and Power Transistors

VGS

IDS

(a)

VS VK Intrinsic MOSFET

(b)

MOSFET IDS (mA/mm)

600

VDS IDS

Rdrift

VD

VG = 5

500 400 300 200

4 3 2

100 0

1 0 1 2 3 4 5 Intrinsic MOSFET Drain Bias, VKS (V)

For a given reverse voltage, electrons enter the depletion region at a saturated velocity of about 1.1
107 cm/s. The traveling electrons constitute a space charge that must be balanced by positive ions to maintain neutrality. The onset of the Kirk effect is when the electron current density jn increases to the point where jn ¼ qnvsat  qNDvsat, where the traveling electron concentration becomes comparable to the ionized impurity concentration (Chap. 5) [97]. For drain current densities in excess of this value, the depletion region must spread toward the drain to neutralize excess electrons with positive ions, eventually reaching the drain. Thus, additional electron charge of magnitude ΔQ per unit area induces an equal but opposite charge near the LDMOS drain boundary, creating an additional lateral field in the same polarity as that of the externally applied drain voltage [97]. This field has the magnitude ΔE ¼ ΔQ/ε0εSi and appears as an additional reverse voltage ΔV ¼ ΔE
Ldrift applied to the drift region. Since the current is limited by velocity saturation, the net result appears as an increase in drain resistance. For a given externally applied drain voltage, this reduces VKS in Eq. (7.26a and 7.26b). Thus, as the intrinsic gate voltage increases, the current increases and VK decreases further. The intrinsic MOSFET is thus gradually forced into the linear regime where, for the same gate voltage, the drain current decreases (Fig. 7.38). The impact of velocity saturation on drift resistance can be seen from the following simplified analysis. The resistivity of the drift region, assumed to be uniformly doped, is given by (2.33)

7.8 High-Voltage and High-Current Effects

ρ¼

351

1 Ω-cm qμn N D

ð7:27Þ

An empirical relationship between bulk mobility and electric field is given as [96] (2.40b) μn ¼ h

μ0 1 þ ðE=Esat Þ

β

2 i1=β cm =Vs

ð7:28Þ

where μ0 is the low-field mobility given by (2.39) and β ¼ 2 and Esat ¼ vsat/μ0 are fitting parameters. The saturation velocity is assumed to be independent of doping concentration, with vsat  1.1
107 cm/s at room temperature (Chap. 2) [96]. For high-resistivity silicon, Esat  8
103 V/cm. Combining Eqs. (7.27) and (7.28) gives h ρ¼

1 þ ðE=Esat Þβ

i1=β

qμ0 N D

Ω-cm

ð7:29Þ

A Taylor expansion around E ¼ Esat of the numerator of Eq. (7.29) gives 1 þ E=Esat Ω-cm ρ  pffiffiffi 2qμ0 N D

ð7:30Þ

Integrating Eq. (7.29) along Ldrift gives for a position-dependent field E( y)

Rdrift

1 ¼ A

ZLdrift

1 ρðyÞdy  A

K

ZLdrift K

1 þ EðyÞ=Esat pffiffiffi dy Ω 2qμ0 N D

ð7:31Þ

where A ¼ tdrift
Wdrift is the cross-sectional area and tdrift is the thickness of the drift region. Noting that E( y) ¼ dV/dy gives  ¼ R0 1 þ

V DK Esat
Ldrift

 Ω

ð7:32Þ

Ldrift Rdrift0 ¼ pffiffiffi Ω 2t drift W drift qμ0 N D

ð7:33Þ

Rdrift where

The above results can also be obtained for a constant lateral field. For a given drift length, Eq. (7.32) shows that Rdrift increases linearly with the ratio VDK/Esat.

352

7 High-Voltage and Power Transistors

In summary, for a given gate voltage, VGS, VDK and VKS increase as the VDS increases, and from Eq. (7.32), Rdrift increases. For a given VDS, VKS decreases as VGS increases [82]. In the above simplified analysis, important factors such as self-heating, accumulation of the drift region under the gate, depletion (JFET) effects, and conductivity modulation were not considered. A more detailed analysis of quasi-saturation is, however, very complex requiring two- or even three-dimensional simulations [82, 98–106]. Example 7.6 For 20-μm wide LDMOS having a 2.0-μm N-drift region, 0.5-μm drift thickness tdrift, and a uniform concentration ND ¼ 4
1016 cm3, find (a) The on-state resistance of the drift region (in the absence of velocity saturation). (b) The drift resistance with 10 V across the drift region (VDK ¼ 10 V) in the presence of velocity saturation. Assume 25  C. Solution From Chap. 2, the mobility is μ0  760 cm2/Vs, vsat  1.1
107 cm/s, Esat ¼ vsat/μ0  1.45
104 V/cm. (a) The resistivity of the drift region is ρ¼

1 1  ¼ 0:206 Ω-cm qμn N D 1:6
1019
760
4
1016

The resistance is then R¼ρ

Ldrift 2
104 ¼ 0:206
 412 Ω A 0:5
104
20
104

where A is the cross-sectional area. (b) The resistance for VDK ¼ 10 V, in the presence of velocity saturation, is found by first calculating R0 in Eqs. (7.32) and (7.33) as 2
104 R0  pffiffiffi ¼ 292 Ω 4 2
0:5
10
20
104
1:6
1019
760
4
1016

The drift resistance is then found from Eq. (7.32) as 

Rdrift

10  292
1 þ 4 1:45
10
2
104

 ffi 1300 Ω

7.8 High-Voltage and High-Current Effects

353

Example 7.7 The intrinsic MOSFET in Example 7.6 has the following dimensions and parameters: Leff ¼ 1 μm, Weff ¼ 20 μm, gate oxide thickness tox ¼ 15 nm, threshold voltage VT ¼ 0.7 V, and effective electron surface mobility μeff ¼ 400 cm2/Vs. Assume room temperature and a uniform distribution of current in the drift region. Estimate (a) The drain current at onset of the Kirk effect (Figs. 5.15 and 7.44). (b) The intrinsic drain-to-source voltage VKS at onset of the Kirk effect. Assume that the MOSFET operates in the linear mode and disregard extrinsic resistances. Solution (a) An estimate of the current density for the onset of the Kirk effect is jn  qN D vsat  1:6
1019
4
1016
1:1
107 ¼ 7:04
104 A=cm2 This corresponds to a drain current of I D ¼ jn
W drift
t drift A or I D  1:76
104
0:5
104
20
104 ¼ 7:04 mA (b) Current continuity requires that the intrinsic MOSFET drain current be the same as the current in the drift region. The current in the linear mode is expressed as (Chap. 6) I D ¼ μeff C ox

  W VK VK A VG  VT  2 L

Substituting the given MOSFET parameters gives the quadratic relation 1:76
103 ¼ 400
2:3
107
510ð4:3  0:5V KS ÞV KS A for which only one solution is meaningful: VKS  2.51 V. The intrinsic voltage, VKS, remains at low level throughout the bias range [7]. The effect of velocity saturation on DMOS output characteristics is illustrated for a 50-V VDMOS in Fig. 7.40 [95]. Similar results are obtained for an LDMOS. Simulations are done under the assumption that the lateral electric field and mobility in the drift region are uniform. The slow transition between linear and saturation

354

7 High-Voltage and Power Transistors

Fig. 7.40 Simulated transfer characteristics for 50-V VDMOS transistor without (dashed lines) and with velocity saturation (solid lines). (Adapted from Chauhan et al. [95])

25 Simulated without velocity saturation Simulated and measured with velocity saturation VG = 2.78 V 50 V VDMOS, 300K

ID (mA)

20

15 2.36 V 10 1.94 V 5

0

1.51 V

0

2.5

5.0

7.5

10.0

VD (V)

y

Source/Body

Ldrift

K P+

VD

x

N+ P-body

D N+

ydn0

N-drift

tdrift

xdn0 Depletion boundaries

P-substrate Fig. 7.41 Depletion regions in hypothetical LDMOS structure shown without gate or field gap

mode at high gate voltage is due to carrier velocity saturation in the drift region and is equivalent to an increase in Rdrift [95]. The characteristics merge at high drain voltage. (a) JFET Effect in Drift Region The analysis in the preceding section was simplified by assuming the drift region to have a uniform cross section of Wdrift
tdrift. In reality, the cross section is reduced by the vertical spreading of depletion into the drift region. Consider first an LDMOS without gate or field gap as shown in Fig. 7.41. The structure is a three-terminal device with the source, body, and substrate shorted together. For VD ¼ 0 V, the vertical and lateral depletion regions correspond to the built-in voltages at the vertical junction between drift and P-body and horizontal junction between drift and substrate.

7.8 High-Voltage and High-Current Effects

355

The room temperature built-in voltage, Vbi, is typically between 0.7 and 0.8 V. Assuming uniform doping concentrations in all regions, the vertical and lateral depletion widths at zero bias are approximated by (Chap. 3) sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ε0 εSi V bi 107 cm  xdn0  qN D ð1 þ N D =N sub Þ N D ð1 þ N D =N sub Þ sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ε ε V 107  0 Si bi    cm ydn0  qN D 1 þ N D =N body N D 1 þ N D =N body

ð7:34aÞ

ð7:34bÞ

The conductive drift region is thus reduced vertically by xdn0 and laterally by ydn0. For a drift region of length Ldrift, depth tdrift, and width Wdrift, the zero bias resistance is (Chap. 2) Rdrift0 ¼ ρ

Ldrift  ydn0 Ω W drift ðt drift  xdn0 Þ

ð7:35Þ

When a voltage VD is applied to the drain with source, P-body, and P-substrate at ground, the full voltage appears at both junctions since there is negligible current through the structure. The depletion widths in Eqs. (7.34a and 7.34b) increase by a factor of sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðV bi þ V D Þ F¼ V bi

ð7:36Þ

Thus, the cross-sectional area and the length of the conductive part of the drift region are further reduced, and the resistance becomes Rdrift  ρ

Ldrift  F
ydn0 Ω W drift ðt drift  F
xdn0 Þ

ð7:37Þ

The analysis becomes complex in an LDMOS of the type shown in Fig. 7.42. For VD > 0 and VG > VT, the structure is in the on-state. The drain current causes IR drops and hence a varying reverse voltage V( y) along the drift region. The depletion regions and conductive paths of the drift widths vary accordingly [81, 82]. As the drain voltage increases, the conductive drift regions between STI and substrate and between STI and P-body become gradually pinched by the spreading depletion regions, increasing the drift resistance. This is similar to pinching the channel in a JFET (Chap. 5), hence the term JFET effect. Also, as VD increases, the drift region beneath the gate becomes accumulated with electrons, reducing the resistance, Racc, in the overlap region. At high-current densities, conductivity modulation and velocity saturation begin to significantly affect the overall drift

356

7 High-Voltage and Power Transistors

Fig. 7.42 Depletion regions in LDMOS with field gap and gate

VG

Source/Body ID P+

N+ P-body

VD

Gate

ID

K ydn

tSTI N-drift

N+ tdrift

D xdn(y)

Depletion boundaries

P-substrate

resistance. Hence, Rdrift is a complicated function of several factors, necessitating the use of computer simulation to optimize LDMOS performance. Example 7.8 An NLDMOS drift region of uniform cross section and doping concentration has a drawn length Ldrift ¼ 4 μm, width Wdrift ¼ 20 μm, and thickness tdrift ¼ 1 μm. The concentration in the drift region is 2
1016 cm3, in the P-substrate 1015 cm3, and in the P-body 1017 cm3. Assume 25  C and find the lateral drift resistance for (a) Zero reverse bias between drift and substrate (VD ¼ VK ¼ 0) (b) For VD ¼ 10 V, VK ¼ 4 V Solution (a) From Chap. 3, at 25  C, the built-in voltage for the drift-to-P-substrate junction is V bi ¼

kT NAND 2
1016
1015 ln  0:0257
ln ¼ 0:651 V q n2i 2
1020

and for the drift-to-P-body junction V bi  0:0257
ln

2
1016
1017 ¼ 0:769 V 2
1020

The lateral depletion width is found from Eq. (7.49a) as

7.8 High-Voltage and High-Current Effects

xdn0

357

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ε0 εSi V bi 1:3
107
0:651     qN D ð1 þ N D =N sub Þ 2
1016 1 þ 2
1016 =1015  1:87
106 cm

and the vertical depletion width from Eq. (7.34b) as

ydn0

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ε ε V 1:3
107
0:769  0 Si bi     qN D 1 þ N D =N body 2
1016 1 þ 2
1016 =1017  2:04
105 cm

The resistivity of the drift region is 0.4 Ω-cm (Chap. 2). The resistance is then found from as Rdrift0 ¼ ρ

Ldrift  ydn0 W drift ðt drift  xdn0 Þ

 0:4


4
104  2:04
105    774 Ω 20
104
104  1:87
106

(b) For a reverse voltage of 10 V between drift and substrate sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ε0 εSi ð10 þ V bi Þ xdn  qN D ð1 þ N D =N sub Þ sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1:3
107
ð10 þ 0:651Þ    1:81
105 cm  2
1016 1 þ 2
1016 =1015 The reverse voltage between drift and P-body is 6 V. The lateral depletion width is then sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ε0 εSi ð6 þ V bi Þ   xdn  qN D 1 þ N D =N body sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1:3
107
ð6 þ 0:769Þ    6:89
105 cm  2
1016 1 þ 2
1016 =1017 Substituting the values in the resistance equation gives Rdrift0 ¼ ρ

L 4
104  6:89
105    809 Ω ffi 0:4
A 20
104
104  1:81
105

358

7 High-Voltage and Power Transistors

Example 7.9 Assume the same conditions and drift dimensions as in Example 7.8 but with an STI of thickness tSTI ¼ 0.4 μm placed under the gate, as in Fig. 7.42. At what drain voltage will the drift region be fully pinched off at the drain boundary? Solution The thickness of the drift region tdrift  tSTI ¼ 0.6 μm. Setting xdn ¼ tdrift  tSTI ¼ 0.6 μm gives xdn ¼ 0:6
10

4

under

the

STI

is

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1:3
107
ðV D þ 0:651Þ   cm  2
1016 1 þ 2
1016 =1015

from which VD is extracted as  2   0:6
104
2
1016 1 þ 2
1016 =1015  0:651  116 V VD  1:3
107 Figure 7.43 shows plots of the body (substrate) current, IB, measured on an LDMOS as a function of gate voltage and VDS ¼ 24 V. For a fixed drain voltage, IB initially increases reaching a first peak and then decreases, only to rise again as the gate voltage is further increased [102, 107, 108]. In region 1, VG < VT, and for a drain voltage below avalanche multiplication, IDS and hence IB are negligible. Simulations and measurements show that the initial peak in body current in region 2 is due to EHP generation by impact ionization at the drain of the intrinsic MOSFET. The current initially increases as the field in the channel near point K increases. It then decreases in region 3 at higher gate voltage because the reverse voltage between K and the pinch-off point decreases, reducing the field. 12 Body Current (μA/μm)

Fig. 7.43 Body current plot for a 24 V NLDMOS

R1

R2

R3

R4

9 6 3 0 0

1

2 3 4 Gate Voltage (V)

5

7.8 High-Voltage and High-Current Effects

1021

N+-source

|ND-NA| (cm-3)

1020 1019

N+-drain

Channel

1017 1016 1015 y dns

Drift region

yjs Depletion boundaries

1018

1014 0

359

d1

yjd

d2 ydpd1 ydps

ydpd2

ydnd1

ydnd2

Lateral distance, y

Fig. 7.44 Illustration of Kirk effect for NLDMOS. yjs and yjd are, respectively, the junction depths at the source and drain. The arrows illustrate the motion of depletion boundaries, yd, as the drain current increases. The subscripts for the depletion boundaries are as follows: n for N-side, p for P-side, s for source, and d for drain

The mechanism for this behavior is similar to that discussed in Chap. 6 for a “standalone” low-voltage MOSFET of the same dimensions as those of the intrinsic MOSFET, with VK applied to the drain. As VG further increases, the drain current density increases and reaches a value of approximately jn  qNDvsat A/cm2 in Eq. (7.47), which is the onset of the Kirk effect [97]. At that point, the depletion boundaries begin to be displaced toward the drain (Fig. 7.44). In the limit, the depletion boundary in the drift region becomes “pinned” at the drain boundary. Thus, the peak field moves toward the drain and begins to increase rapidly as the drain current further increases and the charge accumulates near point K. This causes an increase in the impact ionization rate and hence in body current (region 4 in Fig. 7.43). The generated electrons drift to the drain, increasing the drain current. The generated holes diffuse through the drift region toward the substrate and intrinsic MOSFET body. The body current causes an IR drop in the MOSFET body under the source which forward-biases the body-to-source junction even if their contacts are externally shorted together (Fig. 7.45). The forward bias triggers the parasitic NPN transistor, increasing the drain current and its multiplication and initiating snapback, eventually destroying the device if the current is not limited by a resistor. Conductivity modulation in the drift region, caused by the high forward current, reduces its resistance, lowering the voltage drop in this region. This increases VKS, pulling the intrinsic MOSFET out of the linear region into the saturation region. The net is an expansion of the drain current which opposes its compression by quasi-saturation [109, 110]. The forward current also decreases the MOSFET threshold voltage, further increasing the drain current. An increased field and body current can cause several other problems related to device performance and reliability (Chap. 11). Among them are hot-carrier injection

360

7 High-Voltage and Power Transistors D

Integrated source/body contact

Gate G source P+ contact -body

R1

Ibody

R2 N-drift

R2

R1

P-substrate

Source body contact

Fig. 7.45 Integrated LDMOS source–body contact showing parasitic NPN and base resistance components. R1 is the P-body contact resistance under the source and R2 the P-body bulk resistance under the source

and trapping, substrate noise, and latch-up. In addition, the positive feedback tends to amplify the effects of small variation across the device, such as temperature, distributed drain and source resistance, or threshold voltage. This can mean that a device will not be stressed uniformly, but may fail at its most stressed point.

7.8.2

On-State Breakdown Voltage

The LDMOS on-state breakdown voltage is typically lower than the off-state breakdown voltage mainly because of the Kirk effect discussed in the previous section. Figure 7.46 shows the I–V characteristics for a high-side (with N-buried layer) NLDMOS as a function of drain voltage for different gate voltages. The MOSFET drain current is multiplied at the LDMOS drain where the field is high. The generated hole current diffuses through the drain extension and then drifts to the body contact, triggering the NPN action and snapback [109, 111]. The negative resistance is mainly caused by an increase in NPN gain as the current increases (Chap. 5). To avoid ambiguity, the “breakdown” voltage must be defined at a specified drain current. With this definition, the on-state breakdown decreases as the drain current increases, setting the safe operating area (SOA) of the device (Sect. 7.9). A device switching from the low-voltage on-state to the high-voltage off-state would suffer severe damage if it passed through the high-power region above BV(on), as can occur in the case of inductive switching [112]. To increase BV(on), an additional N-type region of higher concentration than the drift region can be placed on the drain side as shown in Fig. 7.47 [111]. This region has typically a higher doping concentration than in the drift region, effectively retarding the onset of the Kirk effect.

7.8 High-Voltage and High-Current Effects Fig. 7.46 I–V characteristics of a high-side LDMOS transistor. (Adapted from Hower et al. [109])

361

2.6 2.4 2.2

Drain Current (a.u.)

2.0 1.8 1.6

VG = 3

1.4

1.2 VG = 2

1.0

VG = 0 V

0.8 0.6 VG = 1

0.4 0.2 0

5

10

20

15

25

Fig. 7.47 Additional N-region around the drain to increase the LDMOS on-state breakdown voltage (Adapted from Kinoshita et al. [111])

Source/Body

P+

N+ P-body

P-substrate

7.8.3

Gate

30

BVDSS

Drain Voltage (V)

Drain

STI

N+

N-drift

STI STI P-well

Additional N-region

Self-Heating and Other Temperature Effects

Transistors operating at high voltages and currents produce a significant amount of heat, increasing the operating temperature of the transistor itself and that of its surroundings. The rise in temperature affects nearly all transistor parameters, including device reliability. (a) Self-Heating The rise in the operating temperature of a component due to power dissipated within the component itself is referred to as self-heating. The temperature difference between the component and its surroundings causes the heat to flow away from the component, mainly into the substrate. Consider, for example, an insulator of thickness Δx and cross-sectional area A between the transistor and the substrate. For

362

7 High-Voltage and Power Transistors

an idealized case where the steady-state heat conduction is in one dimension, the heat flow through the film is given by H ¼ κAðΔT=ΔxÞ W

ð7:38Þ

where ΔT is the temperature difference between the faces of the film and κ is a constant of proportionality referred to as thermal conductivity. The value of κ is actually a slow function of temperature, but κ can be approximated as a constant if the temperature difference is not too great. Since the direction of heat flow is the direction of decreasing temperature T, and x is positive (dT/dx is negative), the minus sign is introduced in Eq. (7.38) to keep H positive. The thermal resistance of the film is defined as Rth ¼ Δx=κA K=W

ð7:39Þ

The total thermal resistance between the transistor and the substrate is the sum of thermal resistances of the individual films separating them. In practice, some of the heat flows laterally from the transistor perimeter and vertically from the top of the transistors to surrounding regions. Thus, determining the temperature rise for an LDMOS can be quite complex, requiring two-dimensional simulations [99, 112, 113]. Using the heat equation, for a constant input power, P, a simplified expression for the temperature increase is [114–116]

o ΔT ¼ T ðt Þ  T amb ¼ PRth 1  et=τth C

ð7:40Þ

where Tamb is the ambient temperature and τth is the thermal time constant. In steady state (t > 5τth), the above equation simplifies to ΔT ffi PRth o C

ð7:41Þ

A method to extract the thermal resistance and time constant from pulsed power measurements with different pulse widths and duty cycles is described in [115]. A rise in temperature due to self-heating is a more serious concern with high-voltage devices constructed on SOI than with bulk silicon substrates because of the 100 times lower thermal conductivity of the BOX compared to silicon. The problem is exacerbated by the required thicker BOX in analog and mixedsignal applications than in digital CMOS to reduce noise coupling [116–119]. Techniques to reduce the thermal resistance in SOI-like substrates are described in [120, 121]. (b) Other Temperature Effects A rise in temperature increases the intrinsic carrier concentration (Fig. 2.5), reduces the magnitude of MOSFET threshold voltage (Fig. 6.24), reduces the bulk and

7.8 High-Voltage and High-Current Effects

363

surface mobility (Figs. 2.17 and 6.26), increases the resistivity and specific on-resistance, reduces the junction barrier height and forward voltage (Fig. 3.14), increases the junction and surface leakage, increases the bipolar gain, reduces the saturation velocity, and slightly increases the junction breakdown voltage (Chap. 3) [121]. A large increase in temperature also impacts the component reliability [122] and safe operating area [123, 124]. Bipolar Gain and Snapback Voltage An increase in intrinsic carrier concentration, ni, rapidly increases the junction and surface leakage, reduces the Fermi potential (Chap. 2), reduces the junction barrier height (Chap. 3), and reduces the magnitude of threshold voltage (Chap. 6). The difference in temperature dependencies of ni between the emitter and base of bipolar transistors results in an increase in bipolar gain as the temperature increases (Chap. 5). A higher bipolar gain increases the snapback and latch-up susceptibility. By coupling thermal and electrical effects, the snapback voltage is found to decrease with increasing temperature, reducing the safe operating area for both voltage and current [112]. Resistance of Drift Region and Substrate Bulk The carrier mobility decreases with increasing temperature because of the increased probability for phonon scattering (Chap. 2). A lower bulk carrier mobility increases the resistivity of doped silicon, particularly the resistivity of the P-body, drift region, and substrate, causing the bipolar action, snapback, and latch-up to occur at a lower current level. The temperature dependence of bulk resistance is discussed in Chap. 8. The P-body, drift region, and substrate resistances are nonlinear functions of temperature which are typically expressed in a form of a polynomial, keeping only the first three terms: h i RðT Þ  R0 ðT 0 Þ 1 þ 106 α1 ðT  T 0 Þ þ 106 α2 ðT  T 0 Þ2 Ω

ð7:42Þ

In the above equation, R0(T0) is the resistance at a reference temperature T0, α1 is the linear temperature coefficient of resistance (TCR), and α2 is the quadratic TCR, both in parts per million. Figure 7.48a, b shows the calculated temperature dependence of resistivity for typical N-drift region, P-body, and P-substrate. The linear TCR is typically much larger than the quadratic TCR. The resistivity of the N-drift region increases by about 85% from 25 to 125  C. Since LDMOS transistors commonly operate above 125  C, it is very important to take the temperature dependence of sheet resistance into account when designing the LDMOS. (The metal bussing also has a positive TCR leading to higher bussing resistance at elevated temperatures.) Inversion Carrier Mobility and Channel Resistance The inversion carrier mobility also decreases with temperature (Chap. 6). A lower surface mobility reduces the MOSFET current-carrying capability. Since the LDMOS RDS(on) consists mainly of the sum of drift and channel resistances, the

364 0.45

r 0 (W -cm) a 1 (ppm/K) P-body 0.1408 500 N-drift 0.1854 800

0.40 0.35

(a)

Resistivity (W -cm)

Fig. 7.48 Calculated temperature dependence of resistivity including linear and quadratic TCR values. (a) N-drift and P-body. (b) P-substrate

7 High-Voltage and Power Transistors

0.30

a 2 (ppm/K2) 2 2

N-drift ND=4 1016 cm-3

0.25

P-body NA=2 1017 cm-3

0.20 0.15 0.10 0.05 0 -40 -20

0

20 40 60 80 Temperature (oC)

100 120 140 160

35

(b)

Resistivity (W -cm)

30

r0 (W -cm) a 1 (ppm/K) a2 (ppm/K2) 10.58 99100 300

25

Substrate NA=1015 cm-3

20 15 10 5 0 -40

-20

0

20

40 60 80 100 120 Temperature (oC)

140 160

lower surface mobility increases the specific on-resistance. Figure 7.49 shows that the temperature dependence of the LDMOS inversion mobility can be fitted to  μðT Þ  μðT 0 Þ

T T0

2:5

cm2 =Vs

ð7:43Þ

The T2.5 dependence measured on LDMOS channel mobility is significantly more severe than the T1.5–T1.8 observed in conventional CMOS utilizing the same oxidation and polysilicon gate process conditions [125, 126]. This may be attributed to the graded lateral doping profile in LDMOS compared to typically uniform profiles in most of the channels in conventional CMOS. The graded doping profile in LDMOS causes both VT and μeff to be position dependent. The channel resistance is given by (Chap. 6) Rch 

Leff Ω W eff μeff Cox ðV G  V T Þ

ð7:44Þ

Both μeff and VT are temperature dependent. Hence, the temperature dependence of channel resistance in Eq. (7.44) is determined by two competing effects,

7.8 High-Voltage and High-Current Effects l000

Mobility (cm2/Vs)

Fig. 7.49 Comparison of NMOS and NLDMOS temperature dependence of inversion mobility. (Adapted from Dolny et al. [125])

365

NMOS

l00 NLDMOS

l0

l T/300

l0

40 Drain Current (mA)

Fig. 7.50 LDMOS showing SHE-induced negative output resistance

0.l

VG=5 V

30

4V 20

3V

10

2V

0 0

6 12 18 Drain Voltage (V)

24

notably the decrease in mobility that increases Rch and the decrease in VT that reduces Rch. The saturation current of the intrinsic MOSFET depends on the effective mobility and threshold voltage, both decreasing with increasing temperature (Chap. 6). Thus, the temperature coefficient of saturation current depends on the relative magnitude of the VT and μeff and can be negative, positive, or zero [27, 125, 127, 128]. Typically, at lower VGS values, the threshold voltage-dependent component dominates, and saturation current increases with temperature. At higher VGS values, mobility effects dominate, and saturation current decreases with temperature rise. Figure 7.50 shows the output characteristics for an LDMOS operating at high voltage and current. Self-heating at high drain current (high gate voltage) and high drain voltage increases the local temperature and hence decreases the surface mobility, reducing the MOSFET drain current and resulting in a negative temperature coefficient of saturation current [129, 130].

366

7 High-Voltage and Power Transistors

Velocity Saturation The velocity saturation also decreases with increasing temperature because of the increased energy loss to optical phonons (Chap. 2). The variation in saturation velocity with temperature is, however, slower than that of the low-field mobility. Experiments show that the electron saturation velocity in bulk silicon can be fitted to [131–133] vsat 

2:4
107 cm=s 1 þ 0:8eT=600

ð7:45Þ

where T is in K. An empirical equation for the inversion electron saturation velocity is found in [134] as vsat  8:67
106  2:68
103
T cm=s

ð7:46Þ

The saturation velocity of electrons has a weaker dependence on temperature at the surface than in the bulk (Fig. 7.51). Transistor Breakdown The critical field for avalanche breakdown increases with increasing temperature and also with increasing doping concentration (Chap. 3). This is because the accelerated carriers lose more energy along their path, by lattice scattering as the temperature increases and by ionized impurity scattering as the doping concentration increases. In both cases, it means that a slightly higher reverse voltage must be applied to induce avalanche breakdown [135]. In the absence of a RESURF effect, the room temperature breakdown voltage for a typical LDMOS with field gap is approximated as [136]

1.2×107

Velocity Saturation (cm/s)

Fig. 7.51 Temperature dependence of electron saturation velocity in bulk [131–133] and in inversion [134]

1.1×107

Bulk

1.0×107 9.0×106

Inversion

8.0×106

7.0×106 -50

0

50

100

Temperature (oC)

150

7.9 Safe Operating Area (SOA)

367




Ec 1 BV  ε0 εSi Ec þ 2qN D Cox

 V

ð7:47Þ

where Ec is the critical field and Cox the capacitance per unit area of the field-gap region.

7.9

Safe Operating Area (SOA)

Efforts to shrink the LDMOS size have resulted in an increased power density. Hence, it is important to determine how much power can be safely dissipated in the device since this, in addition to BVDSS and RSP, defines the device size. The SOA is a set of ID–VDS boundary limits within which the device must operate to avoid failure. For ease of discussion, it has been suggested to distinguish between the SOA obtained from short-term stressing and the SOA obtained from long-term stressing [37]. For example, failures caused by snapback or latch-up are of electrical nature and typically occur after short-term stressing at high power density of about 1 MW/ cm2. They are said to limit the electrical SOA. In comparison, self-heating leading to thermal runaway requires stressing at lower power density, of about 10 kW/cm2, and is said to limit the thermal SOA or electrothermal SOA. Failures caused by hot-electron injection and trapping require long-term reliability tests at low power density, of about 100 W/cm2, and are hence discussed in the reliability Chap. 11. It should be noted that thermal and electrical effects interact and there is no sharp boundary between the two categories.

7.9.1

Electrical SOA

Snapback and latch-up can be destructive events if the power dissipated in the transistor, ID
VD, exceeds a certain limit. To determine the LDMOS snapbacklimited electrical SOA, for example, an appropriate voltage VG is applied to the gate, and voltage pulses of short duration, about 100 ns to minimize self-heating, but of increasing magnitude are applied to the drain using a transmission line pulse (TLP) tester. The drain voltage for which the I–V characteristic begins to exhibit a negative resistance, at the onset of snapback, is registered as a failure. The gate voltage is then increased and the procedure repeated. The locus of the snapback points determines the SOA boundary. A common way to enhance the snapback SOA of an LDMOS is to reduce the base resistance of the parasitic NPN by increasing the doping concentration of the P-body. This can be achieved by implanting a deeper P+-buried layer under the P-body at high energy through the same window as that of the P-body, without

368

7 High-Voltage and Power Transistors

Fig. 7.52 LDMOS with buried body implant [109]

Integrated source/body contact Gate N+

P+`

N+

P-body N-drift Buried body (P+)

P-substrate

affecting the intrinsic MOSFET threshold voltage (Fig. 7.52) [109]. This enables the LDMOS to handle a higher IB before the parasitic NPN becomes substantially forward-biased. In addition, the higher doping of the buried body increases the NPN base Gummel number, reducing the bipolar gain and further retarding parasitic bipolar action (Chap. 5). The result is an increase in the power density capability by almost one order of magnitude [109, 111].

7.9.2

Electrothermal SOA

Electrothermal SOA is defined as the onset of thermal runaway from extreme device self-heating, usually resulting in complete device failure. The LDMOS is commonly used as a high-voltage switch, with the power dissipation in the on- and off-states being relatively small since VDS and ID are not high at the same time. However, transients or end product use requirements, e.g., inductive switching, dynamic overvoltages on the supply line, voltage regulation, or load dump (voltage spikes due to the poor ability of an alternator to reduce its output quickly when a heavy load is removed as in the case of automotive), can subject the device to high VDS while in saturation either transiently or as a semipermanent bias point. This creates a high-power condition that can lead to thermal instability, a positive feedback by which the generated power increases beyond the level of consumed power [137, 138]. This happens as a result of several feedback mechanisms, most often combined with the triggering of the parasitic NPN transistor [139–142]. This high-power condition can be exacerbated by process and layout choices. Nonuniform effects, due to differing IR drops in thin metallization, can cause localized hot spots due to nonuniform current. Additionally, a high, distributed gate resistance, due to insufficient gate connections across the large device, can lead to uneven turn-off (or turn-on) of the transistor, causing localized hot spots.

7.9 Safe Operating Area (SOA)

369

Using the method described in [143], an analytically based model for electrothermal failure can be used to construct electrothermal SOA contour plots that show the time a device can be safely operated at a given power density. For very large power devices, spatial nonuniformities can bring additional effects. In saturation, using (6.49), the temperature dependence of ID can be derived as [144]
 dI D W dμ dV T A=K ¼ C ox ðV G  V T Þ ðV G  V T Þ eff  2μeff dT dT dT 2L

ð7:48aÞ

For a given increase in temperature, there is an increase in ID and in power, resulting in an increase in temperature. If the loop gain is >1, runaway will occur. Setting dT 1 dP ¼ , ¼ V DS dP Rth dI D

ð7:48bÞ

leads to the condition for runaway as dI D V DS
>1 dT Rth

ð7:48cÞ

At low VGS, the VT temperature dependency gives a positive ID temperature coefficient, but at high VGS, the mobility temperature dependency dominates, giving a negative ID temperature coefficient. The temperature compensation point (TCP) is that point where the ID temperature dependency is zero. Combining Eqs. (7.48a, 7.48b, and 7.48c), VGS at the TCP is found as V G jTCP ¼ V T þ 2μeff

∂V T ∂T V ∂T ∂μeff

ð7:49Þ

For lower VGS values, the LDMOS saturation current is lower, and hence, the overall power density is lower. However, due to the positive dID/dT in this regime, the current increases in the hotter center region of the device, dramatically altering the electrical characteristics and potentially leading to thermal runaway [137]. This is mainly due to the strong temperature dependence of ni2 (Chap. 2). At higher VGS values, any tendency toward runaway is reduced because as the temperature increases, ID decreases. This results in a more uniform current, supporting a larger SOA. Because of the nonuniform lateral heat flow, however, there can still be temperature nonuniformities in the structure. Such effects require the use of a distributed electrothermal network for accurate modeling, as seen in [140, 144].

370

7.10

7 High-Voltage and Power Transistors

Circuit Applications

High-voltage and power devices are used in a myriad of product applications. Among these are motor control, DC–DC conversion for power management, and AC–DC conversion for offline products that operate from an AC wall plug. These are explored in this section.

7.10.1 Half H-Bridge Circuit A common circuit used in power applications is the half H-bridge. This circuit involves stacking a high-side, or pull-up, device in series with a low-side, or pulldown, device. This configuration is sometimes used in a “push–pull” amplifier, where the high side pushes current to the load and the low side pulls current from the load during different phases of operation. This is analogous to a CMOS inverter, which was discussed in Chap. 6, although the half H-bridge implementation is typically done with LDMOS transistors since large currents are involved. This stacking of power devices is also called a “totem pole” configuration. Several implementations of the half H-bridge are shown below. (a) Full NLDMOS Implementation Since the RSP of NLDMOS is approximately one-third that of the PLDMOS, one approach is to use NLDMOS for both the high-side and low-side devices. This circuit configuration is shown in Fig. 7.53a. The low- and high-side devices have been shown previously in Figs. 7.26 and 7.27a, respectively. When pull-up device M1 is turned off and pull-down M2 device is turned on, VOUT  0 V. Alternately, when M1 is turned on and M2 turned off, VOUT  VDD. In the latter case, the P-body of M2 is also pulled up to VDD since the body and source terminals are shorted. The NBL is used in the high-side device to avoid punchthrough from the P-body to substrate when the device pulls up. VDD

VDD Charge Pump Circuit

M1

HS NLDMOS

M1

VOUT M2 (a)

PLDMOS VOUT

LS NLDMOS

M2

LS NLDMOS

(b)

Fig. 7.53 Half H-bridge circuit implementation. (a) Using only NLDMOS. (b) Using NLDMOS and PLDMOS

7.10

Circuit Applications

371

The full NLDMOS approach requires a VG bias for M1 above VDD to completely turn on M1 since the device has a positive VT. This is typically done using a charge pump circuit. This creates a trade-off that adds circuit complexity and area, while consuming power, but achieves the smallest H-bridge total device area. (b) Complementary LDMOS Implementation An alternate half H-bridge implementation utilizes NLDMOS and PLDMOS devices. A low-side NLDMOS structure is used as the pull-down device, while a PLDMOS device is used as the pull-up. This circuit configuration is shown in Fig. 7.53b. The circuit operation is the same as for the full NLDMOS approach. However, since the high-side PLDMOS is used, with a negative VT, the device can be fully turned on using a bias lower than VDD, eliminating the need for a charge pump circuit and simplifying the design. There are trade-offs for the complementary approach also. The high-side PLDMOS in Fig. 7.53b is approximately three times larger than the corresponding NLDMOS in Fig. 7.53a due to the higher RSP stemming from lower hole mobility. For a given limit on total power dissipation and a known duty cycle, the optimum relative allocation of area to the PLDMOS and NLDMOS can be calculated from AreaPLDMOS ¼ AreaNLDMOS

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi RSP-PLDMOS RSP-NLDMOS

ð7:50Þ

Additionally, the number of masking steps required to build the PLDMOS can often be more than for the NLDMOS (Chap. 9).

7.10.2 H-Bridge Motor Driver: LDMOS Reverse Recovery The LDMOS transistor model should consider the parasitic diode between the body and drift regions (Fig. 7.2). Since the source and body regions are normally shorted, this diode is included between the source and drain terminals, as shown in the H-bridge circuit of Fig. 7.54. Because they can reverse the polarity of the voltage supplied to the load, H-bridges are often used to drive motors. By passing a current through the motor (shown as an inductor), the motor turns. By using pulse-width modulation (PWM), the motor can rotate at a controlled speed, with the resulting IL waveform shown in Fig. 7.55. Initially, all transistors are off at time ta. Turning on transistors M1 and M4 while M2 and M3 are off causes IL to increase at a slope VDD/L, since M1 pulls VA up to VDD while M4 pulls VB down to 0 V.

372

7 High-Voltage and Power Transistors

Fig. 7.54 H-bridge schematic including LDMOS body diodes, load inductor, L, and parasitic inductances, Lpar

VDD Lpar M1

M3

LOAD VA

VB L

M2

M4 Lpar

IL

–(VDD + 1.4V)/L

IHIGH ILOW +VDD/L

ta

+VDD/L

tb

tc

td

IPWM

t

Fig. 7.55 H-bridge output current (IL) waveform

At tb, IL reaches IHIGH and M1 and M4 are turned off. As IL cannot change abruptly, it forward-biases the body diodes of M2 and M3, pulling VA to 0.7 V and VB to VDD + 0.7 V, and IL decreases at a rate of (VDD + 1.4 V)/L until it reaches ILOW. There is power loss in the diodes. Furthermore, this creates a high-current density in the body diode, causing high-level injection in the N-drift region, since the P-body is more heavily doped (Fig. 7.56a), resulting in a large amount of stored charge (holes) in the lightly doped N-drift region. There is additional power loss because the diode at M3 in Fig. 7.54 has a parasitic PNP transistor with the substrate as the collector and injects holes into the substrate. Although a small fraction (5–10%) of the total current goes to the substrate, the current does cause a large voltage drop, thus dissipating high power. The parasitic drain-to-substrate diode in transistor M2 also injects electrons into the substrate. If those electrons are collected by a region biased to high voltage, such as the drain of an adjacent NLDMOS, the power dissipated can also be significant. At tc, M1 and M4 turn on again, pulling VA up to VDD and VB down to 0 V. This abruptly reverses the bias across the once forward-biased body diodes of M2 and

7.10

Circuit Applications

Fig. 7.56 LDMOS reverse recovery. (a) Switching voltage input to body diode with parasitic inductance. (b) Diode response waveforms

373

node VA

P+

VF

N-

N+

t t0

(a)

L par VDD

IF

i(t) –VDD/Lpar

(b)

t0 IRM VDDM

t2

v(t)

VF

t1

t3

t4

t5

IS

V

VDD

di/dt dir/dt

dv/dt

M3. When these forward-biased diodes are suddenly reverse-biased, there is a reverse recovery time (τrr) before they reach their full reverse-bias state. This was covered in Chap. 3 (Figs. 3.28 and 3.29) for a resistive load, but is reviewed below for the case of an inductive load. More detailed discussions can be found in [145, 146]. During this time, IL ramps up with slope VDD/L until td. The M2 body diode is shown in Fig. 7.56a including the series parasitic inductance, Lpar, of the interconnect system, either on-chip or board-related. As in the resistor case in Chap. 3, when the diode’s voltage switches from VF (forward bias) to VDD (reverse bias) at t0, the stored charge cannot be evacuated instantaneously. The parasitic inductance Lpar limits di/dt ¼ VDD/Lpar, and the current drops from IF, shown in Fig. 7.56b, becoming negative at t1 and continuing until t2, when the excess carriers at the junction edge are removed and the voltage across the diode begins to reduce. As the reverse voltage increases, the depletion region starts to expand, and the ensuing electric field sweeps out the remaining excess carriers until the voltage reaches VDD at t3, at which point i(t) reaches its peak, IRM. From then on, the current decreases rapidly toward zero. However, as the depletion region widens, a capacitive displacement current, ir, forms, which produces a voltage across inductance Lpar that adds to the applied VDD, leading to VDDM ¼ VDD + Lpar
(dir/dt) at t4. This voltage spike can lead to junction breakdown, causing a potential reverse-biased SOA (RBSOA) event. Meanwhile, the depletion region continues to widen, and ir continues to decay until t5 when the voltage stabilizes at VDD and ir reaches the minute diode saturation current, IS. The shaded region in Fig. 7.56b represents the reverse recovery charge, Qrr, while the time t5  t1 is called the reverse recovery time, τrr. An automated system to measure the reverse recovery parameters is described in [147].

374

7 High-Voltage and Power Transistors

The IRM spike can be high, perhaps up to ten times IF, limited only by the parasitic inductances and the turn-on rate of M1. This current must be sourced by M1, which creates a potentially destructive forward-biased SOA (FBSOA) event due to excessive (and perhaps nonuniform) self-heating in the on-state [148]. In addition, IRM can create disturbances in the circuit—such as noise, ringing, and voltage spikes—that can couple to other portions of the circuit and affect their behavior. For example, in class-D audio amplifiers, reverse recovery delays are a significant source of distortion. Effort to reduce IRM, such as turning on the LDMOS gates more slowly, reduces IRM but increases τrr and leads to conduction losses since the LDMOS is conducting at a higher RDS(on) during this time (Fig. 7.6). Another potentially destructive mechanism for the LDMOS during reverse recovery is caused by the commutating operation of the body diode. When M2’s body diode is suddenly switched from forward bias to reverse bias, the stored charge is swept out of the body diode’s bulk, creating base current that can trigger the parasitic NPN if the body resistance (R2 in Fig. 7.45) is not sufficiently low, resulting in a destructive commutating SOA (CSOA) event [149]. Diode reverse recovery can potentially cause a destructive event known as snappy recovery. In this case, a very high dir/dt results from a total depletion of the stored charge during the recovery period producing a strong, destructive voltage overshoot. Various “softness” factors [146] have been proposed to quantify the onset of snappy behavior, dealing primarily with the ratio of dir/dt to di/dt or to τrr.

7.10.3 DC–DC Converter: Switching Effects A ubiquitous circuit in power electronics is the switching DC–DC converter, which converts one DC voltage level to another with high efficiency, η, defined as POUT/PIN, commonly over 90%. Electronic systems often need a variety of distinct voltage levels, so rather than using multiple sources, DC–DC converters are used to step up (boost) or step down (buck) the VIN to the desired VOUT levels. For instance, a buck converter is often used to step a high-voltage supply, e.g., 12 V, down to 5 V or lower levels needed for other circuits in the system. An asynchronous buck converter is shown in Fig. 7.57a, with corresponding waveforms shown in Fig. 7.58. Typically, the diode, inductor, and capacitor are off-chip components. The switch is controlled by sensing VOUT and regulated by pulse-width modulation, at some frequency, fSW, to maintain VOUT at a desired level. When the LDMOS is on, (VOUTVIN) is across the inductor, causing IL to increase with a slope of (VOUTVIN)/L. When the LDMOS turns off, IL decreases with a rate of (dVOUT + VF)/L as the freewheeling diode D (forward voltage VF) provides a recirculation path for IL. IL ripples about IOUT and is filtered by capacitor C to deliver a steady VOUT.

7.10

Circuit Applications VIN

375 VIN

Sense and Switch Circuitry

Control

SW1

Control

Sense and Switch Circuitry

SW1

Sense L

Sense VOUT

IL

D

SW2

L

V

IL

C

C

(a)

(b)

Fig. 7.57 Buck switching converter. (a) Asynchronous. (b) Synchronous

IL

IOUT

(b)

Slope = (VIN-VOUT)/L

Slope = -(VOUT+VF)/L

Average I OUT t

(a)

SW ON

SW OFF

ton

toff t period

D=

ton ton + toff

t

Fig. 7.58 (a) LDMOS switch operation in PWM mode. (b) Inductor current as a function of time for switching conditions in (a)

Since diode current and VF create power loss, a Schottky diode is often used, with its lower VF. Alternatively, a LS-NLDMOS can be used for synchronous conversion, shown in Fig. 7.57b, with lower voltage drop although this involves more control circuitry to ensure that both the HS-LDMOS and LS-NLDMOS are not on simultaneously to avoid shoot-through. Ignoring diode drops and LDMOS RDS(on), at steady state, VOUT is V OUT ¼ V IN D V

ð7:51Þ

where D is the duty cycle, defined as D ¼ ton/(ton + toff), as can be seen by recognizing that since the average voltage across an inductor must be zero, the average voltage at the connection between the LDMOS and the diode must equal the output voltage VOUT.

376

7 High-Voltage and Power Transistors

For an asynchronous converter, the power loss, PLOSS, is the sum of the LDMOS conduction and switching losses, the loss in the Schottky diode, and the gate charge losses. Assuming the IL ripple current can be approximated as the DC value IOUT, the on-state NLDMOS conduction loss, PCOND, is PCOND ¼ DI 2OUT RDSðonÞ W

ð7:52Þ

The power loss in the diode, PDIODE, is  PDIODE ¼ ð1  DÞ I OUT V F þ I 2OUT RDIODE W

ð7:53Þ

where VF and RDIODE are the forward voltage and the parasitic series resistance, respectively, of the Schottky diode at current, IOUT. The switching power loss, PSW, for the HS-NLDMOS is related to the speed of charging of the device (Fig. 7.19), a subset of which is shown in Fig. 7.59 and focused on the ID  VDS transitions. Once the gate–source voltage reaches VT, the drain current, ID, begins to increase (since the switch is at VF, the gate voltage only has to reach VT  VF) at which point the source voltage begins to rise and the drainto-source voltage, VDS, begins to decrease from (VIN + VF) toward 0 V. During this time, both ID and VDS are nonzero, hence causing power loss. The energy (P  t) during the transition time t1 to t2 and t2 to t3 is E12 ¼ ðt 2  t 1 ÞðI OUT =2ÞV IN J

ð7:54Þ

E23 ¼ ðt 3  t 2 ÞðV IN =2ÞI OUT J

ð7:55Þ

Neglecting the power to drive the gate, the average switching loss power is PSW ¼ f SW ðt 3  t 1 ÞðV IN =2ÞI OUT W

ð7:56Þ

An estimate for the total power loss, PLOSS, in the switching FET and diode is the sum of the loss components from Eqs. (7.51), (7.52), and (7.56). The efficiency is

Fig. 7.59 Switching waveforms for HS-NLDMOS in buck converter, with shaded box highlighting switching loss region

VIN

VDS

ID

I OUT VGS VT t0

t1

t2

t

t3

t4

7.10

Circuit Applications

377

η ¼ ðPIN  PLOSS Þ=PIN

ð7:57Þ

(a) High-Frequency Switching Considerations Capacitors and inductors are normally off-chip components for DC–DC converters. The impedances of these are 1/2πfSWC and 2πfSWL, respectively, so they can be reduced as fSW is increased to maintain constant impedance values, reducing board size and weight. At high switching speeds, the gate switching loss cannot be neglected and is given as PSW, G ¼ f SW QG V GS W

ð7:58Þ

However, η degrades at high fSW unless (t3–t1) is reduced in Eq. (7.56). Optimizing the LDMOS with shallow junctions, short gate length, and minimal overlap capacitances reduces QG [30, 150, 151], decreasing charging times for a given drive strength. In fact, it may be preferable to use a LDMOS with a higher RSP, but lower QG, for high-speed applications, trading off higher PCOND for lower PSW (Fig. 7.60). An alternate method for achieving very high switching frequency converters uses the concept of “soft switching” using a resonant circuit to minimize switching losses, as discussed in [152]. Using a conventional LDMOS, a measured efficiency over 80% has been achieved at a switching frequency of 75 MHz [153].

7.10.4 AC–DC Converter Analog ICs are increasingly used in offline applications such as LED lighting, which is replacing traditional incandescent lighting worldwide because of significant energy savings [154]. While the LED itself operates on less than 5 V DC, the requirement that these bulbs be direct replacements for incandescent ones dictates the use of AC inputs ranging from 85 to 265 V AC. A “flyback” AC–DC converter (Fig. 7.61) can be used for these low output power applications, directly converting the AC signal to DC in a single stage and isolating the output from the input [155]. An LC filter and diode bridge rectifier are used to smooth and convert the AC signal, VAC, allowing it to be approximated as a DC input, VIN, to the converter. Transistor M1 is operated in a PWM mode. Transformer T1 is asymmetric, where the ratio, n, of primary turns (Np) to secondary turns (Ns), is greater than one. When M1 is turned on, there is a positive voltage VIN across the primary and a clockwise current Ip. The induced voltage in the secondary is negative, and the counterclockwise Is is blocked by diode D. Because M1 is effectively short during this time period (ton), Ip increases linearly due to the inductance of the primary windings, Lp, with a slope VIN/Lp, increasing the flux density in the primary coil.

378

7 High-Voltage and Power Transistors

VDS

(a)

IDS

Switching Loss

Conduction Loss

t VDS IDS

(b)

t

Fig. 7.60 LDMOS switching waveforms. (a) Conventional. (b) High frequency

Csn

Rsn

VIN

VAC

D

Ip T1

Dsn

C Is

IOUT RLOAD

VOUT

Snubber Circuit M1 Rectifier and Filter

Fig. 7.61 AC–DC flyback converter circuit including snubber circuit

While M1 is on, diode D appears as open, and the output current is supplied only by capacitor C as I OUT ¼ V OUT =RLOAD A

ð7:59Þ

When M1 turns off, the primary current Ip goes to zero since the LDMOS is now an open circuit. This implies a reduction in flux density, which reverses the voltage across the windings of T1, changing the voltage across the primary to nVOUT (this is the “flyback” action) and transferring the current from the primary to the secondary based on the inverse of the turns ratio. During this time period (toff), the diode is effectively a short and IOUT remains at VOUT/RLOAD. The capacitor is used to supply current when M1 is on, and its charge is replenished when M1 is off.

Problems

379

The average voltage across the primary must be zero due to volt–second balance and is given by [156]

 V p ¼ V IN

t on t off  nV OUT ¼0 t on þ t off t on þ t off

ð7:60Þ

V OUT ¼ nDV IN V

ð7:61Þ

Solving for VOUT yields

where D is the duty cycle, defined as D ¼ ton/(ton + toff). Hence, the conversion ratio (VOUT/VIN) for a flyback converter is similar to that in Eq. (7.51) for the DC–DC buck converter with the added n factor. Since VIN is much higher than VOUT, the n factor allows the duty cycle to remain in a more practical range for circuit operation. When M1 turns off, a very large voltage spike can occur due to the transformer leakage inductance (a small parasitic inductance associated with the transformer) and combination of the transformer winding capacitance and LDMOS Coss that can damage M1. A “snubber” diode (Chap. 3) is added to recirculate this charge and lower the voltage rise to about 1.5 times the flyback voltage (Fig. 7.61). The voltage seen across LDMOS M1 is thus given by V DS ðoff Þ ¼

pffiffiffi 2V IN þ nV OUT þ 1:5nV OUT V

ð7:62Þ

where the √2 is used since VAC is converted by the rectifier to a peak value with respect to the root-mean-squared (RMS) parameter typically used. For a 265 Vms AC supply, a regulated 40 V DC output, and a turns ratio of 2.5:1, the LDMOS VDS must withstand 625 V in its off-state. Hence, BVDSS must be over 700 V considering margin. Such devices typically use the multiple RESURF device design discussed earlier in this chapter.

Problems 1. The channel length of the intrinsic MOSFET in a DENMOS is 1 μm and the drift length 4 μm. Assume velocity saturation in both the MOSFET and drift region, and find the time of flight for an electron to travel from source to drain. 2. The channel width of a DENMOS is 1 cm, and the off-current at 25  C is measured as 1 pA/μm. Assume an ideality factor of 1.4 and a decrease in VT of 1 mV/ C as the temperature increases from 25 to 125  C, and calculate the off-current at 125  C. Neglect the thermally generated current. 3. For a DENMOS having a device pitch of 4.45 μm and an RSP ¼ 20 mΩ-mm2, find the device width needed to achieve RDS(on) ¼ 1 Ω. 4. In a planar LDMOS, the gate overlap of the N-drift region is 0.5 μm, the gate oxide thickness is 15 nm, the threshold voltage is 0.7 V, the device width is

380

7 High-Voltage and Power Transistors

1 cm, and the fringe capacitance between gate and N-drift region is 0.25 fF/μm. The gate is charged with a constant current of 1 mA. Estimate the time-span of the Miller plateau. 5. The following LDMOS information is given: intrinsic MOSFET tox ¼ 12.5 nm, Leff ¼ 1 μm, VT ¼ 0.7 V, device width ¼ 20 μm, tdrift ¼ 1.5 μm, Ldrift ¼ 2 μm, and ND ¼ 2
1016 cm3. Approximate the gate voltage at the onset of the Kirk effect in the drift region. Assume that at that point, the MOSFET operates in saturation, μeff ¼ 300 cm2/Vs, and the temperature is 25  C. 6. At what drain voltage will avalanche breakdown occur in the structure below? Assume a critical field of 3
105 V/cm and 25  C. VB = 0 V STI P+ P-well NA=1017 cm-3

VD N+

STI 5 mm ND =

1016

STI

0.4 m m cm-3

N-drift

P-substrate NA = 1015 cm-3

7. The structure in the figure below was subjected to hot-electron stress during which electrons were trapped in the STI at the interface with the N-drift region. Assume that the trapped electrons are uniformly distributed at a concentration of 5
1011 cm2. For 25  C, estimate (a) The N-drift sheet resistance in the portion under the sheet of trapped electrons and under the portion covered by the poly gate (b) The drift resistance under the STI for a device width of 1 cm VS = 0 V

N+-POLY STI

P+

N+

P-well NA = 1017 cm-3

VD = +0.1 V

VG = +5 V L1 = 1 mm

N+

tSTI=350 nm L2 = 1 mm N-drift

1 mm

STI

Trapped electrons ND = 1016 cm-3

P-substrate NA = 1015 cm-3

8. Calculate the room temperature depletion width and the peak field in silicon in the N-drift region beneath the polysilicon plate, under the STI and at the N-driftto-P-substrate junction shown in the figure below.

Problems

381 VB = 0 V

VG = 0 V N+-POLY tSTI = 360 nm

STI P+ P-well NA=1017 cm-3

VD = +40 V N+

STI

6 mm 5 mm

N-drift ND = 1016 cm-3

P-substrate NA = 1015 cm-3

9. For the planar NLDMOS in the figure below, assume Ldrift ¼ 2 μm, Lacc ¼ 0.5 μm, tdrift ¼ 1.3 μm, Leff ¼ 1.0 μm, Weff ¼ 20 μm, tox ¼ 15 nm, and no gate oxide charge. (a) Estimate the room temperature drift resistance for VG at flatband. (b) Estimate RDS(on) for VG ¼ +5 V at 25 and 140  C. Hint: for surface mobility, use the universal mobility plots in Chap. 6. VG

VS = 0 V

VD = 0.1 V

+-Poly N+N -poly

P+

Leff N+ P-body

NA = 1017 cm-3

Lacc N-drift

N+

STI

Ldrift

STI P-well

tdrift

ND = 1016 cm-3 P-substrate

NA = 1015 cm-3

10. Consider a 24-V NLDMOS power switch that should carry 10 A and must operate from 40 to +125  C. The voltage drop across the structure may not exceed 0.5 V. The breakdown voltage, BVDSS, follows a normal distribution with σ ¼ 0.5 V and has a temperature coefficient of 1500 ppm/ C. Assume 10% variation in the power supply voltage, 15% tolerant to RDS(on), and a device pitch of 3.25 μm. For a Six Sigma design, estimate the minimum width of the NLDMOS that should be designed to satisfy the above conditions. 11. For an LDMOS of the type shown in Fig. 7.7, assume ND-drift ¼ 5
1016 cm3, tdrift ¼ 1.5 μm, NA-body ¼ 5
1016 cm3, NA-SUB ¼ 1015 cm3, and no interaction with the MOS region. Determine (a) If this structure can achieve optimum RESURF (region II in Fig. 7.12) (b) The lateral (P-body/N-drift) breakdown voltage 12. For the structure of the type in Fig. 7.7, determine the required P-substrate doping, Nsub, to achieve optimum RESURF assuming ND ¼ 7
1016 cm3 in the drift region and tdrift ¼ 2 μm.

382

7 High-Voltage and Power Transistors

13. The intrinsic MOSFET in an LDMOS is designed with tox ¼ 12.5 nm, Leff ¼ 0.6 μm, Weff ¼ 10 μm, uniform body concentration NA ¼ 2
1017 cm3, and N+-poly gate. For VG ¼ 5 V, at what temperature T will dID/dT  0? 14. Explain why a MOSFET with a laterally graded channel as in NLDMOS exhibits a sharper peak in transconductance than a conventional NMOS having a laterally uniform channel.

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131. S.A. Schwarz, S.E. Russek, Semi-empirical equations for electron velocity in silicon: Part I Bulk. IEEE Trans. Electron Dev. 30(12), 1629–1633 (1983) 132. C. Jacobini, C. Canali, G. Ottaviani, A. Alberigi-Quaranta, A review of some charge transport properties of silicon. Solid State Electron. 20(2), 77–89 (1977) 133. S. Selberherr, Analysis and Simulation of Semiconductor Devices (Springer, Wien/New York, 1984) 134. T.Y. Chan, S.W. Lee, H. Gaw, Experimental characterization and modeling of electron saturation velocity in MOSFET’s inversion layer from 90 to 350 K. IEEE Electron Dev. Lett. 11(10), 466–468 (1990) 135. S.S. Rofail, M.A. Chaudhry, The temperature dependence of breakdown voltage and on-resistance of LDMOS’s. IEEE Trans. Electron Dev. 34(4), 933–935 (1987) 136. M.J. Declercq, J.D. Plummer, Avalanche breakdown in high-voltage D-MOS devices. IEEE Trans Electron Dev. ED-32(1), 1–4 (1976) 137. P.L. Hower, S. Pendharkar, Short and long-term safe operating area considerations in LDMOS transistors. IEEE IRPS, (2005), pp. 545–550 138. M. Denison, M. Pfost, K.W. Pieper, S. Markl, D. Metzner, M. Stecher, Influence of inhomogeneous current distribution on the thermal SOA of integrated DMOS transistors. IEEE Proc. ISPSD, (2004), pp. 409–412 139. P.L. Hower, P.K. Govil, Comparison of one- and two-dimensional models of transistor thermal instability. IEEE Trans. Electron Dev. 21(10), 617–623 (1974) 140. P. Moens, G. Van den Bosch, Characterization of total safe operating area of lateral DMOS transistors. IEEE Trans. on Elec. Mat. Rel. 6(3), 349–357 (2006) 141. V. Benda, J. Gowar, D.A. Grant, Power Semiconductor Devices – Theory and Applications (Wiley, Chichester, 1999) 142. M. Denison, M. Pfost, M. Stecher, D. Silber, Analysis and modeling of DMOS FBSOA limited by n-p-n leakage diffusion current. IEEE Proc. ISPSD, (2005), pp. 159–162 143. V. Dwyer, A.J. Franklin, D.S. Campbell, Electrostatic discharge thermal failure in semiconductor devices. IEEE Trans. Electron Dev. 37(11), 2381–2387 (1990) 144. P. Spirito, B. Breglio, V. d’Alessandro, N. Rinaldi, Thermal instabilities in high current power MS devices: Experimental evidence, electro-thermal simulations and analytical modeling. MIEL 1, 23–30 (2002) 145. C. Ma, P. Lauritzen, A simple power diode model with forward and reverse recovery. IEEE Trans. Power Electronics 8(4), 342–346 146. M. Rahimo, N. Shammas, Freewheeling diode reverse recovery failure modes in IGBT applications. IEEE Trans. Industr. Appl. 37(2), 661–670 (2001) 147. J.A.R. Latorre, M.A. Jimenez, R. Palomera, Automated wafer-level measurement of LDMOS reverse recovery parameters. IEEE MWSCAS, (2012), pp. 1072–1075 148. AN2385 application note, “Power dissipation and its linear derating factor, silicon limited drain current and pulsed drain current in MOSFETs,” STMicroelectronics, revision 1, June 2006 149. A. Tsui, H. Yilmaz, I. Hshieh, M. Chang, T. Fortier, Commutating SOA capability of power DMOS FETs. IEEE APEC Proceedings, (1990), pp. 481–485 150. T. Matsudai, K. Sato, N. Yasuhara, H. Saito, K. Endo, F. Takeuchi, M. Yamamoto, 0.13 μm CMOS/DMOS platform technology with novel 8 V/9 V LDMOS for low voltage high-frequency DC-DC converters. IEEE Proc. ISPSD, (2010), pp. 315–318 151. Y.K. Choi, I.Y. Park, H.S. Oh, W. Lee, N.J. Kim,K.D. Yoo, Implementation of low Vgs (1.8 V) 12 V RF-LDMOS for high-frequency DC-DC converter applications. IEEE Proc. ISPSD, (2012), pp. 125–128 152. A. Sagneri, Design of a very high frequency dc-dc boost converter, MS thesis, MIT, 2007 153. J.M. Burkhart, R. Korsunsky, D.J. Perreault, Design methodology for a very high frequency resonant boost converter. IEEE IPEC, (2010), pp. 1902–1909 154. U.S. Department of Energy website., http://energy.gov/energysaver/articles/led-lighting 155. K. Billings, T. Morey, Switchmode Power Supply Handbook, 3rd edn. (McGraw-Hill Publishing, New York, 2011) 156. S. Ang, A. Oliva, Power-Switching Converters, 2nd edn. (CRC Press, Boca Raton, 2005)

Chapter 8

Passive Components

Abstract Integrated components that do not amplify current or voltage signals belong to a family of devices referred to as passive components. This includes resistors, capacitors, varactors, and inductors. This chapter describes passive components that can be integrated in a CMOS technology. The design and characteristics of different types of resistors, capacitors, varactors, and spiral inductors are described, followed by simple examples of their applications in analog circuits. Passive components, in particular capacitor and resistors, occupy a substantial area of the chip (Fig. 1.12). They should be optimized by minimizing the area while maintaining the desired electrical properties.

8.1

Introduction

Resistors, capacitors, varactors, and inductors belong to a family of devices referred to as passive components. They are passive inasmuch as they respond to but do not amplify current and voltage signals. They can be connected to a chip as discrete elements or integrated within the chip. This chapter describes passive components that can be integrated in a CMOS technology. Passive components, in particular capacitor and resistors, occupy a substantial area of the chip. They should be optimized by minimizing the area while maintaining the desired electrical properties.

8.2

Resistors

The types of resistors than can be incorporated in a CMOS technology are grouped as silicon resistors, polysilicon resistors [1, 2], and thin metallic film resistors [3–8]. Some resistors just require special layouts without any added process complexity, while others, such as precision polysilicon resistors, may require one or more additional processing steps to block silicidation and tailor the resistance (Chap. 9). A typical silicon or polysilicon straight-line resistor is shown in plan view in Fig. 8.1a. It consists of a resistor body of the desired resistance and two highly doped © Springer Nature Switzerland AG 2020 B. El-Kareh, L. N. Hutter, Silicon Analog Components, https://doi.org/10.1007/978-3-030-15085-3_8

389

390

8 Passive Components Silicide-block mask

WD

Resistor Body

(a) Resistor head

Contact

LD WD

Resistor Body Silicide

Metal Contact

Highly-doped Silicide Resistor region block end

Silicide

(b) N- or P-region in silicon Resistor body

Resistor end

(c)

Silicon

Bulk

Silicide block

N+ or P+

N- or P-polysilicon STI

Resistor body Bulk

Fig. 8.1 (a) Plan view of diffused or polysilicon straight-line resistor. (b) Schematic cross section of silicon resistor. (c) Schematic cross section of polysilicon resistor. LD, drawn length; WD, drawn width

contacting end regions, referred to as resistor ends or resistor heads. A thin dielectric film, typically SiO2 or Si3N4, is patterned to block silicidation over the resistor body and allows siliciding the resistor ends (Chap. 9). Schematic cross sections of typical silicon and polysilicon resistors are shown, respectively, in Fig. 8.1b, c. The term thin-film resistor (TFR) is reserved for precision resistors typically made of thin metal alloys. They include nickel–chromium (NiCr) [3, 4], aluminum-doped nickel–chromium (AlNiCr) [5], silicon–chromium (SiCr) [6], titanium–nickel–chromium (TiNiCr) [7], and tantalum nitride (TaN) [8]. The top view of a TFR is similar to that of silicon and polysilicon resistors, but the film materials and fabrication steps are quite different. Figure 8.2 is a schematic cross section of a typical TFR. The following section describes important terms used in characterizing resistors. Section 8.2.2 discusses different types of polysilicon resistors, and implanted silicon resistors are discussed in Sect. 8.2.3 and TFRs in Sect. 8.2.4.

8.2 Resistors Fig. 8.2 Schematic of a typical thin-film resistor, TFR. (a) Top view. (b) Cross section

391 Contacting metal

TFR

(a)

WD

Contacting opening Intermediate insulator films

(b)

Insulator

LD

Metal interconnect

Contacting metal

TFR

Metal-filled VIA

Planarized insulator

8.2.1

Definition of Terms

(a) Drawn and Electrical Dimensions The dimensions WD and LD in Fig. 8.1a are, respectively, the drawn resistor width and length. The corresponding electrical (effective) resistor dimensions, WE and LE, can be smaller or larger than the drawn dimensions depending on the process bias due to lithography, etching, and diffusion. The difference between drawn and electrical dimensions is ΔW ¼ W D  W E ; ΔL ¼ LD  LE μm

ð8:1Þ

(b) Sheet Resistance The sheet resistance of the resistor, assumed to be a uniform film, is the resistance measured between two opposite edges of a square of the film. It is defined as (Chap. 2) RS ¼ ρ=t Ω=□

ð8:2aÞ

where ρ is the resistivity of the film and t its thickness. The resistance of a straight-line resistor body is then R ¼ nRS ¼ ðLE =W E Þ  RS Ω

ð8:2bÞ

where n is the number of squares. The choice of sheet resistance is a trade-off between area and performance. For example, for a given resistor value, the higher the sheet resistance, the smaller the area occupied by the resistor. As the area is reduced, however, resistor mismatch and noise increase (Chap. 10). For convenience and layout efficiency, the resistor can be designed in a meander (serpentine) form (Fig. 8.3).

392

8 Passive Components

Fig. 8.3 Schematic of a meander resistor

L2

W W

L1

L2

For a resistor of the geometry in Fig. 8.3, the effective number of squares is n ffi ð4LE1 þ 5LE2 Þ=W E þ 8  0:559

ð8:3Þ

The second term in (8.3) is the contribution of 8 corners to n; the value 0.559 is obtained by the conformal mapping technique [9]. (c) End Resistance or Head Resistance The end resistance comprises the contact and via resistances, the series resistance of the contacting metal, and the resistance of the interface between the contacting metal and resistor material. For polysilicon and silicon resistors, the contacting metal is typically silicide, such as titanium silicide (TiSi2), cobalt silicide (CoSi2), or nickel silicide (NiSi). For a TFR, the contacting metal is an appropriate refractory metal, such as a combination of titanium (Ti) and titanium nitride (TiN). The total resistance is thus R ffi nRS þ 2Rend Ω

ð8:4Þ

In all cases, an appropriate metal is chosen to achieve stable ohmic contacts at the resistor ends since this can be an important factor in the temperature coefficient of resistance (TCR), voltage coefficient of resistance (VCR), and matching (Chap. 10). A plot of R versus resistor length for a constant resistor width is shown in Fig. 8.4. The sheet resistance is obtained from the slope and the end resistance from the intercept with the vertical axis. (d) Temperature Coefficient of Resistance, TCR For a small temperature range, the temperature dependence of sheet resistance can be approximated to have a linear dependence as
  RS ðT Þ ¼ RS0 1  α T  T 0 Ω=□

ð8:5aÞ

where α is the TCR, expressed in parts per million per  C (ppm/ C or ppm/K) as

8.2 Resistors

393

Fig. 8.4 Extraction of sheet and end resistance

7 W = 10 mm, 25oC

R × W (K W -mm)

6 5 4

3

y(x) = (RS × L) + (2 × Rend )

2 1 0

2 × Rend 0

α ¼ TCR ¼ 106

5

15 10 Length, L (mm)

 1 dRS ppm= C RS0 dT

20

25

ð8:5bÞ

and RS0 is the sheet resistance at the reference temperature T0. The TCR is not a constant but depends on the temperature range in which it is measured. It can be positive, negative, or near zero, depending on the type of resistor. For more accuracy, the variation of resistance with temperature can be fitted into a parabola of the form h i RðT Þ ¼ R0 1 þ α1 ðT  T 0 Þ þ α2 ðT  T 0 Þ2 Ω=□

ð8:6Þ

where α1 is the linear temperature coefficient of resistance in ppm/K and α2 the quadratic temperature coefficient of resistance in ppm/K2. Example 8.1 The temperature dependence of sheet resistance, RS, of a resistor is given in Table 8.1. Extract the linear TCR, α1, and the quadratic TCR, α2, from the data. Solution A plot of RS versus temperature is shown in Fig. 8.5. From the curve fit, we get, setting the reference temperature T0 ¼ 298 K h i RS ¼ 340:8 1  1:326  103 ðT  298Þ þ 2:054  106 ðT  298Þ2 which gives α1 ¼ 1326 ppm/K, α2 ¼ 2.054 ppm/K2.

394

8 Passive Components

Table 8.1 Temperature dependence of sheet resistance T ( C) 40 35 30 25 20 15 10 5 0 5

T ( C) 10 15 20 25 30 35 40 45 50 55

RS (Ω/⎕) 360.1 357.6 355.1 352.6 350.2 347.8 345.4 343.1 340.8 338.6

RS (Ω/⎕) 336.4 334.2 332.1 330.0 327.9 325.9 323.9 322.0 320.1 318.2

T ( C) 60 65 70 75 80 85 90 95 100 105

RS (Ω/⎕) 316.4 314.6 312.8 311.1 309.4 307.7 306.1 304.5 303.0 301.5

T ( C) 110 115 120 125 130 135 140 145 150

RS (Ω/⎕) 300.0 298.6 297.2 295.8 294.5 293.2 292.0 290.8 289.6

360

Sheet resistance (W / )

350 340 y = 0.0007 x2 – 0.4519 x + 340.8 330 320 310 300 290 280

-40

-20

0

20

40 60 80 Temperature (oC)

100

120

140

Fig. 8.5 Example 8.1, plot of polysilicon sheet resistance versus temperature

(e) Voltage Coefficient of Resistance, VCR The VCR is a measure of the sensitivity of resistance to the voltage applied between the resistor terminals and fields from conductors in the vicinity of the resistor VCR ¼ 106

1 dRS ppm=V RS ðV Þ dV

ð8:7Þ

where RS(V) is the voltage-dependent sheet resistance. Thus, the VCR is not a constant but depends on the applied voltage. (f) Self-Heating and Thermal Conductivity The power generated in a resistor is in the form of Joule heating, where

8.2 Resistors

395

P ¼ VI ¼ I 2 R ¼ V 2 =R W

ð8:8Þ

The above equation describes the transfer of electrical energy to thermal energy and is known as Joule’s law. Self-heating is the increase in resistor temperature due to Joule heating in the resistor itself. Self-heating affects the resistor parameters and can also affect the parameters of surrounding components. The generated power in the resistor dissipates mainly into the silicon substrate. When the generated power equals the dissipated power, the resistor temperature reaches a steady-state value. The one-dimensional steady-state heat conduction through a film of area A and thickness Δx is expressed as H ¼ κAðΔT=ΔxÞ W

ð8:9Þ

where H is the time-rate heat transfer through the film, expressed in cal/s, J/s, or W. κ is the thermal conductivity of the film, expressed in W/cm-K (or W/cm- C), ΔT the temperature difference between the two faces of the film, and ΔT/Δx the temperature gradient. The thermal conductivity of silicon is 1.5 W/cm-K and that of SiO2 is 0.014 W/cm-K [10–13]. For a film of thickness t, the thermal conductance is κA/t, expressed in W/K (or W/ C). The thermal resistivity and thermal resistance (Rth) are, respectively, the inverse of thermal conductivity and conductance. The thermal conductivity is not a constant but, for most solids used in semiconductor devices, decreases as the temperature increases in the range of normal operation [10–13]. Example 8.2 Consider a resistor of width W ¼ 2 μm, length L ¼ 10 μm, thickness t ¼ 0.2 μm, and sheet resistance RS ¼ 250 Ω/□. The resistor is placed on a triple layer of SiO2–Si–SiO2 as shown in Fig. 8.6. Assume steady-state heat conduction in one dimension normal to the silicon surface down to the substrate. At what current density, in mA/μm and A/cm2, will the resistor temperature T1 increase 5  C above T4?

Resistor of length L I

Solution The rate ofTheat transfer tox1 mmis SiO across t = 0.4 1

T2 T3 T4

I

2 , ox-1

Si, tSi =0.5 m m

ðT 1  T 2 Þ ¼ κox A H 1SiO mm W 2 , tox-2 =t0.2 ox1

ð8:10Þ

Si substrate

where κ ox ¼ 0.014 W/cm-K, A ¼ 2  107 cm2, and tox1 ¼ 4  105 cm. Fig. 8.6 Example 8.2,transfer conduction of heat a triple stack is Similarly, the rate across tSi through

396

8 Passive Components

H 2 ¼ κSi A

ðT 2  T 3 Þ W t Si

ð8:11Þ

where κSi ¼ 1.5 W/cm-K and tSi ¼ 4  105 cm. In steady state H2 ¼ H1 ¼ H. Combining (8.10) and (8.11) gives H¼A

ðT 1  T 3 Þ W ðt ox1 =κox Þ þ ðt Si =κ Si Þ

ð8:12aÞ

The quantity t/κ is referred to as the thermal resistance. Similar to electrical resistances, thermal resistances of multiple layers in series are additive. A similar analysis gives ðT 1  T 4 Þ W ðt ox1 =κ ox Þ þ ðt Si =κSi Þ þ ðt ox2 =κox Þ Substituting the values in (8.2b) gives H¼A

H¼

ð8:12bÞ

0:1 ¼ 2:32  104 W ð4=0:014Þ þ ð5=1:5Þ þ ð2=0:014Þ

The power generated in the resistor is given by (8.8) as P ¼ I 2 R ¼ I 2 RS  ðL=W Þ ¼ 1250  I 2 W The current density for a steady-state resistor temperature rise of 5  C above T4 is calculated as j ¼ I=W ¼

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2:32  104 =1250=2 ¼ 0:215 mA=mm

or j ¼ 0:215  103 =2  108 ¼ 1:08  105 A=cm2 (g) Resistor Linearity Because of self-heating, however, there will be some nonlinearity in the current– voltage characteristics that is closely related to the TCR of the resistor in the same temperature range. The temperature rise due to self-heating depends on how efficiently the generated heat is removed from the resistor and its surroundings, hence on the thermal conductivity of the layers surrounding the resistor. For example, for the same power generation, a silicon resistor will exhibit less self-heating than a polysilicon resistor or TFR deposited on a thick insulator. This is because the thermal conductivity of typical insulators is one to two orders of magnitude smaller than that of silicon. Similarly, a polysilicon resistor or TFR placed higher up above the silicon substrate will exhibit more nonlinearity than when placed closer to the substrate.

8.2 Resistors

397

Fig. 8.7 Parasitic capacitances, illustrated for a polysilicon resistor and a TFR placed at first metal level. STI is the shallowtrench isolation, PMD the poly-metal dielectric, and IMD the inter-metal dielectric

Metal-2 IMD

Cf

Cf

TFR

Metal-1

PMD

CPMD

STI

CSTI

Cf Cf

CSi Silicon

CPMD

Cf Poly-R Cf

CSTI CSi Silicon

(h) Parasitic Capacitances Parasitic capacitances between a resistor and conductors surrounding it are illustrated in Fig. 8.7. For example, assuming that the inter-metal dielectric (IMD), poly-metal dielectric (PMD), and STI have the same dielectric constant, εox, the capacitance between the TFR and silicon can be approximated as the equivalent of three capacitances in series (Fig. 8.7): the pre-metal dielectric capacitance, CPMD; the STI capacitance, CSTI; and the silicon capacitance, CSi, as 1 CTFR

¼

1 C PMD

þ

1 1 þ F1 C STI CSi

ð8:13Þ

where C PMD ffi ε0 εox =t eq-PMD F=cm2

ð8:14aÞ

C STI ffi ε0 εox =t STI F=cm2

ð8:14bÞ

and CSi depends on the silicon surface conditions discussed in Chap. 6. In the presence of conductors above, below, or in the vicinity of a resistor, parasitic capacitances to those conductors must be taken into account. Fringe capacitances, Cf, can become significant and a complex function of distances between resistor and conductors, dielectric constant of insulators surrounding the resistor, and a function of resistor and conductor thicknesses. Accurate calculations of fringe capacitances typically require two- or even three-dimensional numerical analysis.

8.2.2

Polysilicon Resistor

Polysilicon resistors are typically integrated in small sizes, with values ranging from tens of ohms to mega-ohms, by controlling the doping type and concentration, anneal conditions, and the resistor size.

398

8 Passive Components

Fig. 8.8 TEM micrograph illustrating the grain distribution in a polysilicon film [20]. Grains are surrounded by very thin boundaries

(a) Structure Polysilicon consists of crystallites, called grains, joined together by grain boundaries. Grain boundaries are of negligible thickness compared to the grain size and believed to consist of a few atomic layers of disordered atoms [14, 15]. The average grain size depends on doping species and concentration, deposition conditions, and annealing conditions [16] and can vary from about 0.05–about 1.8 μm [17–19] (Fig. 8.8). (b) Carrier Transport Mechanisms, Resistivity The transport of carriers through polysilicon is different than through single-crystal silicon [14, 15, 21–27]. Inside each grain, the atoms are arranged periodically as in single-crystal silicon. Thus, the transport of carriers within a grain can be treated as discussed in Chap. 2. The transport of carriers from grain to grain is, however, limited by a barrier at the grain boundary and more complex, as discussed below. The polysilicon resistivity depends on the free carrier concentration and effective mobility. Free Carrier Concentration Figure 8.9a shows the average free carrier concentration obtained from Hall measurements versus average boron concentration in a P-type polysilicon film, and Fig. 8.9b shows the associated resistivity [15]. At low dopant concentration, the hole concentration is only a very small fraction of the boron concentration. When the dopant concentration reaches about 5  1017 cm3, the concentration of holes increases rapidly and approaches that of boron at higher dopant concentrations. The effect of grain boundaries on carrier concentration is described by two models. One model is based on the segregation of dopants at grain boundaries where they become inactive [23, 24]. The second model assumes that the disordered atoms at the boundary are sites of incomplete bonding, creating interface states that trap and immobilize free carriers, thus reducing the free carrier concentration within the grain [14, 15, 21–23, 25–27].

8.2 Resistors

399

1019 1018

106

300 K Measured Calculated

1017 1016

300 K Measured

105

Resistivity (Ohm-cm)

Average hole concentration (cm-3)

1020

(a)

1015 1014

Calculated

104 103 102

(b)

101 100

1013

10-1

1012

10-2

1011 1015 1016 1017 1018 1019 1020 1021

10-3 1015 1016 1017 1018 1019 1020 1021

Boron concentration (cm-3)

Boron concentration (cm-3)

Fig. 8.9 (a) Hall-measured and calculated hole concentration versus boron concentration. (b) Measured and calculated resistivity of P-type polysilicon [15]

Fig. 8.10 Energy band diagram for polysilicon crystallites [15]

Depletion boundary

Trapped charge

Exaggerated grain boundary Grain

-- ---- --Barrier

N-type

-- ---- --EC EF EV

Effective Carrier Mobility The carrier mobility has a minimum in the concentration range of 1017–1018 cm3 and increases at higher or lower dopant concentration [19]. The mobility increases with increasing grain size and film thickness [14, 15, 20–23]. The charged traps create a space charge surrounding the grain that constitutes a barrier to carrier flow from grain to grain, reducing the effective carrier mobility. This is schematically illustrated in a simplified two-dimensional structure in Fig. 8.10 [15]. In N-type polysilicon, the majority of interface states are below the Fermi level and hence negatively charged by trapping electrons (Fig. 8.10). In P-type

400

8 Passive Components

polysilicon, the states are above the Fermi level, hence positively charged after trapping holes. At low to moderate fields, the transport of carriers across the grain boundary is mainly by thermionic emission, i.e., by carriers that possess enough thermal energy to surmount the barrier ϕB. The effective mobility of carriers traveling across grain boundaries can be approximated as [15] μeff / eqϕB =kT cm2 =Vs

ð8:15Þ

where, for phosphorus- and arsenic-doped polysilicon, the width of the grain boundary is approximated δ ffi 0.7 nm [28]. It follows that the effective mobility of carriers traveling across the grain boundary increases with increasing temperature. Depending on the grain size, the minimum mobility is observed when the barrier reaches its maximum value which is when the grain is fully depleted. The condition of full depletion depends on dopant concentration, grain size, and interface trap density. For typical polysilicon films at room temperature, the mobility minimum is found in the concentration range from 1017 to 1018 cm3 [15, 20]. Resistivity The resistivity in the same doping range as in Fig. 8.9a is shown in Fig. 8.9b [15]. Since the resistivity is a function of mobility and carrier concentration, it will depend on the polysilicon deposition conditions and grain size. One of the major difficulties in high-resistivity polysilicon resistors is the large sensitivity to dopant concentrations in the range of 1016–1018 cm3. For example, over a doping concentration range of 5  1017–5  10,18 a resistivity change of about five decades is observed in polysilicon compared to only one decade change in single-crystal silicon (Fig. 8.9b) [14, 15, 19, 21–23]. A modified grain-boundary trapping model is suggested in [27], where it is assumed that both segregation and trapping mechanisms influence the polysilicon film conductivity. The trapping mechanism also explains the reduction in polysilicon resistivity after hydrogen annealing because the adsorption of hydrogen at grain boundaries reduces the interface trap density by passivating dangling bonds. When both the transport through grains and the transport across grain boundary contribute to conduction, their temperature dependences tend to cancel each other. The effect of barrier height diminishes as the dopant concentration within a grain increases. For degenerately doped films, the width of the barrier decreases to such an extent that tunneling through the barrier, rather than thermionic emission over the barrier, becomes the predominant transport mechanism. Also, conduction in degenerately doped grains becomes a weak function of temperature. (c) Electrical Dimensions and Sheet Resistance The difference between drawn and electrical resistance length, ΔL, is usually negligible because LE is defined by the thin silicide block mask which is precisely patterned by reactive-ion etch, RIE (Chap. 9), resulting in negligible ΔL compared to LD. The difference in width, ΔW, can be extracted from measurement on straight-line

8.2 Resistors

401

resistors with the same drawn width and varying drawn lengths, i.e., with different number of squares n ¼ LD/WD. From (8.1, 8.2a and 8.2b), one gets ΔW ¼ W D  RS

LD2  LD1 μm R2  R1

ð8:16Þ

where RS is the sheet resistance of the resistor body, LD1 and LD2 the drawn lengths of two resistors, and R1 and R2 the measured resistances. Figure 8.10 shows the linear dependence of the ratio (LD2  LD1)/(R2  R1) on WD for LD1 ¼ 5WD and LD2 ¼ 10WD [29]. When extracting ΔW from (8.17a and 8.17b), it is assumed that for a fixed width, the two resistors have the same Rend and RS. ΔW is obtained from the intercept of the curve fit with the horizontal axis and RS from the slope (Fig. 8.11). The need to know the contact, probe, and metal resistances to extract ΔW and RS can be eliminated by using a Kelvin-probe structure as shown in Fig. 8.12. The structure consists of two bridges of length L and drawn width WD1 and WD2. A current is forced between Tab-1 and Tab-2 and the voltage measured with a highimpedance voltmeter as V1 between Tab-3 and Tab-4 and V2 between Tab-5 and

Fig. 8.11 Linear dependence of (LD2  LD1)/ (R2  R1) on resistor width and extraction of ΔW and RS. (Adapted from [29])

LD1 = 5WD, LD2 = 10WD

(LD2-LD1)/(R2-R1) (mm/Ohm)

0.08

0.06

P +-Poly

N +-Poly

0.04

0.02

DW 0.00 0

2

4

6

8

10

12

Drawn resistor width, WD (mm)

V1

Tab-1

Tab-3

V2 Tab-4

W1

W2

Tab-5

Tab-6

I

Tab-2 I

L

Fig. 8.12 Two-bridge structure to extract RS and ΔW

L

402

8 Passive Components

Fig. 8.13 Example of square-shaped van der Pauw structure [30]. The width, W, is at minimum lithography dimension

Tab-1 Silicide block

L W VFB; (b) depletion, VG < VFB

8.4 Varactors

429

of Q [93]. As with the PN junction varactor, Q can be increased by optimizing the stripe array arrangement as in Fig. 8.38. For an effective gate length of 1.95 μm, gate width of 15.85 μm, and 14 gate stripes, a quality factor of 23 was measured at 1 GHz, while a tuning range of about 2 was measured [93]. CMOS scaling to smaller dimensions can considerably increase the quality factor, however, at the cost of reducing the tuning range [96–99]. Typically, the dominant part of the varactor resistance is the conduction through the gate. Since the quality factor is inversely proportional to resistance, Q increases as the gate length decreases. As the gate length is reduced, however, the parasitic capacitance, which is almost fixed, becomes a larger fraction of the total capacitance, reducing the tuning range. The quality factor in Fig. 8.40 increases from about 17 in accumulation to about 33 in inversion [94]. (b) Inversion-Mode MOS Varactors An inversion-mode varactor is essentially a PMOS transistor constructed on an N-well (Fig. 8.41) [99]. With source, drain, and N-well shorted at ground, the C-V characteristic of the MOS structure is similar to that in Fig. 6.11a (Chap. 6). The capacitance approaches Cox on both inversion and accumulation. The tuning range is the ratio of Cox in inversion to Cmin where VG ffi VT. The tuning range can be increased and widened by connecting the N-well to VDD, thus preventing the Fig. 8.40 C-V plot at 1.8 GHz obtained on an accumulation-mode MOS varactor formed by an array of structures similar to that of Fig. 8.38 [94]

35

3.5

3.0

25

2.5

20

2.0

15

Capacitance (pF)

Quality Factor

3.1 pF at 0V 30

1.5 -3

-2

-1

0

1

2

3

Gate to N-well Voltage (V)

Fig. 8.41 Inversion-mode PMOS varactor, N-well

S

D

teq

VG

B VDD

P+-Gate xdmax

P+

P+ Inversion

Depletion N-well

Deep N-well

N+

8 Passive Components

Fig. 8.42 C-V plots of PMOS varactor. (a) Source, drain, and N-well shorted; (b) N-well at VDD ¼ 2.7 V, source, drain at ground. (Adapted from [100])

MOS Capacitance, C (pF

430

1.4 1.2

ª Cox

ª Cox

(b)

(a)

1.0

Cmin-1

0.8

Cmin-2 0.6 -2.0

VT-2

-1.0

0

1.0

VT-1 Gate Voltage, VGS (V)

2.0

varactor from entering the accumulation mode in the voltage range of operation (Fig. 8.42b) [99, 100]. One advantage of an inversion-mode varactor is its high and wide tuning range. The other advantage, related to low-voltage applications, is the abrupt transition from Cmax to Cmin [101]. Example 8.4 A large PMOS structure is used as a varactor with the N-well biased at VDD ¼ 2.7 V and the source and drain at ground. The gate oxide thickness is tox ¼ 25 nm, and the N-well concentration is ND ¼ 1017 cm3. Plot the MOS capacitance per unit area as a function of the gate voltage, VGS, from 2 to +3 V, and approximate the tuning range. Assume T ¼ 300 K. Solution An exact analysis of charge, electric field, and capacitance in the range between strong accumulation and strong inversion requires involved calculations of surface potential. We will, however, simplify the solution by making an abrupt transition from Cmin to a constant Cmax in strong inversion. The transition from Cmin to Cmax in accumulation is, however, delayed because of the reverse voltage VDD applied to the N-well (Fig. 8.43). The oxide capacitance is C ox ¼

ε0 εox 3:55  1013 ffi ffi 1382  107 F=cm2 t ox 2:5  105

The gate voltage with respect to the source is VG. With respect to the N-well, the gate potential is (VG + ϕms – VDD), where ϕms ffi 0.968 V is the work function difference between the P+-gate and N-well surface. The surface potential, field-induced depletion width, silicon capacitance, and MOS capacitance are calculated as a function of gate-to-well voltage in Example 8.3. A C-V plot is shown in Fig. 8.43. The tuning range is Cmax/Cmin ffi 2.9.

8.4 Varactors

431

140 Cmax MOS capacitance (nF/cm2)

130 120 110 Accumulation

100 90 80 Cmin

70 60 -2.0

-1.5

-1.0

-0.5

0

0.5 VGS

1.0

1.5

2.0

2.5

3.0

(V)

Fig. 8.43 Example 8.4, C-V plot of PMOS varactor with reverse-biased well

Fig. 8.44 Three-terminal accumulation-mode varactor [102]

VN Gate

VG

N+ Silicide block Silicide N+ P+

P+ N-well VP

(c) Three-Terminal Varactor Several three-terminal varactors have been proposed to increase the tuning range and Q factor of MOS varactors [102, 103]. The three-terminal structure in Fig. 8.44 allows the varactor to operate from accumulation to deep depletion in all frequency ranges, resulting in a higher tuning range than with the two-terminal accumulationmode varactor described above. The polysilicon gate and N-well surface under the gate are continuous across the structure. A silicide block prevents silicidation between P+- and N+-regions. The P+ source and drain of the PMOS are shorted.

432

8 Passive Components

When a positive voltage is applied to the common gate terminal, the N-well surface is accumulated, and the varactor capacitance approaches Cox. When a negative voltage is applied to the gate, the surface becomes depleted, and, when VG ¼ VT, the surface will invert if the P+-regions are held at ground. In this case, the fieldinduced depletion region reaches a maximum value xdmax, and the capacitance reaches a minimum value Cmin. To prevent the inversion from forming, a reverse voltage is applied to the P+-regions (the third terminal). As a result, the surface goes into deep depletion, and the capacitance decreases below Cmin as VG becomes more negative than VT, increasing the tuning range.

8.5

Planar Spiral Inductors

Planar spiral inductors are the most common style of inductors used in ICs. There is, however, an increasing effort at integrating non-planar inductors, including those with magnetic cores [104, 105]. A square-shaped planar spiral inductor is shown in Fig. 8.45. The key dimensions are the outer side length, do; the inner side length, di; the number of turns, N; the metal width, w; and the metal-to-metal space, s. Other common inductor shapes are circular and octagonal. Inductors can be formed with a single or multiple AlCu or Cu levels [106–109].

8.5.1

Definition of Terms

Inductors are passive elements that store energy in the form of a magnetic field. For a direct current, the inductor has almost zero resistance, nearing a short. At high frequency, however, it represents a reactance that opposes a change in current. The reactance is proportional to the frequency at which the current changes. The Fig. 8.45 Illustration of square-shaped inductor

Next to last metal level

Via to lower metal level

w s

do di

Last metal level

8.5 Planar Spiral Inductors

433

most important parameters of integrated spiral inductors are the achievable inductance per unit area, the quality factor, and self-resonance frequency (SRF). Other related parameters are the skin effect, the proximity effect, and the parasitic capacitance. (a) Inductance A current i through a conductor creates a magnetic flux ϕ around the conductor. For a conductor of constant permeability, the inductance L is defined as the ratio of magnetic flux to current L ¼ ϕ=i H

ð8:50Þ

where ϕ is the magnetic flux in Weber (Wb) and L the inductance in Henry (H). A henry is, however, too large a unit for on-chip inductors. Instead, a smaller unit, nH, is used (1 nH ¼ 109 H). A change in current causes a change in magnetic flux. This induces a voltage v across the inductor which is found from (8.52) as v ¼ Lðdi=dt Þ V

ð8:51Þ

The induced voltage is proportional to the rate of change in current and has the polarity that opposes the change in current (Lenz’s law). The above equation can also be considered as another definition of L. The inductance of a circular wire of diameter d (μm) and length l (μm) is [109]

4ℓ 3 nH  L ¼ 0:2  ℓ  ln d 4

ð8:52Þ

For a single circular inductor loop, the inductance is [109]

16R  2 nH L ¼ 1:257  10 R  ln d 3

ð8:53Þ

where R is the loop radius (μm) and d the wire diameter (μm). The inductance of a square-shaped inductor shown in Fig. 8.45 can be approximated by [110, 111] L¼

2:34  1:257  103 N 2  ðd 0 þ di Þ   nH i 2 1 þ 2:75  dd00 þd di

ð8:54Þ

where do is the outer side length, di the inner side length, and N the number of spires (turns). (b) Self-Resonance To increase the inductance per unit area, integrated inductors have typically a spiral form with minimum line-to-line space, s, and metal width, w (Fig. 8.45). Reducing the space, however, increases the line-to-line (lateral flux) capacitance. Disregarding the inductor resistance, the SRF is

434

8 Passive Components

pffiffiffiffiffiffi f srf ¼ 1= LC Hz

ð8:55Þ

where L is the inductance and C the effective capacitance. It is important that the SRF be sufficiently high to avoid self-resonance in the operating frequency range. This can be achieved by reducing the lateral flux capacitance, i.e., increasing the distance between lines, and reducing the dielectric constant of the insulator separating the lines [112]. Thus, the line-to-line space is a trade-off between self-resonance and inductor size. (c) Skin Effect An alternating current in a conductor produces an alternating magnetic field within and around the conductor. According to Lenz’s law, the change in magnetic field creates an electric field which opposes the change in current density. The opposing field is strongest in the center of the conductor, thus forcing the electrons to a thin conducting region, referred to as the skin, at the conductor periphery. Thus, the current density is highest at the conductor periphery and decreases exponentially toward the conductor center following the relation j ¼ jmax ex=δ A=cm2

ð8:56Þ

where x is the distance from the outer surface toward the conductor center and δ is the average skin depth. As the frequency increases, δ decreases, and the effective conducting cross section decreases, thus increasing the effective conductor resistance and reducing Q. (d) Proximity Effect When two parallel metal conductors carry the same alternating current, such as in a spiral inductor, the magnetic field created by one metal line induces eddy currents along an adjacent metal line and vice versa. The eddy current is in the same direction as the alternating current on the sides of the wires that are further way from each other and in opposite direction of the current on the sides of the conductors closer to each other. The net result is current crowding at the conductor periphery, increasing the effective conductor resistance and reducing Q. Current crowding increases with increasing frequency [113]. Eddy current losses to the substrate also reduce the quality factor. The losses depend on the proximity of the inductor to the substrate and on the substrate resistivity. To reduce these I2R losses, the inductor is formed at a large distance from the substrate, and a high-resistivity substrate is chosen as the starting material [114, 115]. (e) Spiral Inductor Design Guidelines The following general guidelines apply to integrated planar spiral inductors [111, 116]: (i) The inner diameter, di, should be large to allow sufficient magnetic flux to flow through the center. As a rule of thumb, di ¼ do  2 Np, where N is he number of turns and p the metal pitch (width + space) [110, 111].

8.5 Planar Spiral Inductors

435

(ii) The optimum inductance lies between L ¼ 2 nH and 10 nH. For a lower L, the parasitics become more significant, and for larger inductance the area becomes too large. The typical number of turns is between 3 and 5. (iii) For an operating frequency of 1–3 GHz, the optimum metal width lies between approximately w ¼ 10 μm and 15 μm. As w increases, the resistance decreases, and Q increases, but as w increases, the skin effect becomes more pronounced. (iv) The spacing between metals, s, should be minimized. It is limited by the line-toline capacitance. (v) Losses, like the skin effect, capacitance to substrate, and eddy current in the substrate should be minimized. This is why the uppermost metal is used for spiral inductors. In addition, the uppermost metal is thicker than lower-level metals, resulting in a lower inductor resistance and higher Q. Example 8.5 Find the inductance of an inductor that is used to resonate with a 4 pF capacitor at 900 MHz. Solution From (8.55) we find the inductance as L¼

1 4π 2 f 2r C

ffi

4π 2



 9  10

1

 8 2

 4  1012

ffi 7:8 nH

Example 8.6 A square-shaped spiral inductor is constructed with an outer “diameter” (side of the square) do ¼ 200 μm, inner diameter di ¼ 72 μm, and a number of turns N ¼ 4. Find its inductance. Solution The inductance is given by (8.54) as Lffi

ffi

2:34  μo  N 2  ðd o þ di Þ h  i i 2  1 þ 2:75  ddoo d þdi 2:34  1:257  108  42  ð200 þ 72Þ  104 h  i ffi 2:8 nH 2  1 þ 2:75  20072 200þ72

436

8 Passive Components

Example 8.7 Disregarding losses due to current crowding or eddy currents, the quality factor of a spiral inductor is approximated as Q¼

2πfL RT

where f is the frequency, L is the inductance, and RT is the sum of contact and metal series resistances. A spiral inductor of inductance 7.5 nH is fabricated with aluminum of total length L ¼ 2480 μm, width W ¼ 15 μm, thickness tAℓ ¼ 0.5 μm, and resistivity ρAℓ ¼ 3 μΩ-cm. The contact resistance at each end of the inductor is 5 Ω. Find the quality factor of the inductor at a frequency f ¼ 2 GHz. Solution The sheet resistance of aluminum is RS ¼

ρAℓ 3  106 ffi ffi 60 mΩ=square t Aℓ 0:5  104

The sum of metal and contact resistances is RT ¼ RS

L 6  102  2480 þ 2Rc ffi þ 2  5 ffi 20 Ω W 15

Substituting in the above equation for Q gives Qffi

8.6

2πfL 2π  2  109  7:5  109 ffi 4:7 ffi 20 RT

Applications

This section briefly describes application examples of resistors, capacitors, varactors, and inductors with the objective of highlighting the importance of their key parameters.

8.6.1

Resistors

One of the applications of precision resistors is a voltage regulator (Fig. 8.46) [117]. A voltage reference VREF is applied to generate a regulated voltage VREG. For an ideal amplifier, the regulated voltage is V REG



RA V ¼ V REF 1 þ RB

ð8:57Þ

8.6 Applications

437

Fig. 8.46 Schematic of a voltage regulator [117]

VREF

Voltage reference vin = vTAP = vREG

VREG

+

vin

RB RA + RB

RL

“Tap” RA

RB

Fig. 8.47 Simple digital-toanalog converter resistor ladder [117]

VOUT

R2 N

R3

R2 N –1

R1

R2

VREF

V2 N –1

V2 N –2

V3

V2

V1

V0

Thus, VREG is a function of the ratio of the two resistors, which is practically insensitive to temperature variations. The accuracy of VREG depends, however, or other non-ideal effects, such as mismatch, VCR, and Rend variations (Chap. 10). Power dissipation is also another consideration, requiring high-sheet resistance to obtain high-value resistors while minimizing the area. Because of their high VCR, and parasitics, well resistors are not suitable for this application. A high-sheet polysilicon resistors or a thin-film resistor TFR has the advantage of precision and flexibility while occupying a considerably smaller area. Another important application is the resistor ladder in a basic DAC (Fig. 8.47). The ladder consists of 2N identical resistors, where N is the number of bits in the word, e.g., N ¼ 8 for an 8-bit DAC. A decoder controls the individual switches. The analog output, Vout, is the voltage division of the resistors at the selected tap. The accuracy of the analog output depends on the control of the resistor value. In particular, the mismatch of identical resistors should meet the specified error tolerance of the converter (Chap. 10) [117]. The required matching of resistors must satisfy the relationship



ΔR

1

R 2N1

ð8:58Þ

438

8.6.2

8 Passive Components

Capacitors

One typical application of high-κ capacitors is on-chip decoupling. In addition to the existing capacitors, dedicated capacitors are often required to further reduce the power supply noise. They are most efficient when placed close to switching circuits, and, hence, they occupy valuable area. Thus, the most important criteria of decoupling capacitors are high capacitance density to reduce the area consumed by the capacitor and low leakage through the dielectric at the operating voltage. An estimate of the total decoupling capacitance Cdecap that is required to keep the circuit voltage “bounce” within a specified value is given in [118]. In a time interval Δt, the circuit switching charge ΔQ is ΔQ ¼

I C 2f

ð8:59Þ

where I is the average current during switching and f is the clock frequency. The voltage “bounce” across the connected decoupling capacitor is ΔV ¼

ΔQ V C decap

ð8:60Þ

Cdecap must be sufficiently large to keep ΔV below a specified fraction r of the power supply voltage VDD, that is C decap >

I P ¼ F 2frV DD 2frV 2DD

ð8:61Þ

 DD is the average power dissipated in the circuit. For a typical ratio where P ¼ IV r  0.05, (8.61) becomes Cdecap >

10P F fV 2DD

ð8:62Þ

which gives a reasonable estimate of Cdecap [118]. One common application of precision capacitors is the charge pump shown schematically in Fig. 8.48. In this example, a voltage higher in magnitude than the maximum on-chip voltage, VDD, is generated by the charge pump [117]. Transistors M1 and M2 operate as diodes. The input to Cp is a clock signal at a given frequency. When the input is low, M1 pulls up point A to VDD  VT, and the voltage on CLoad is VDD – 2VT. When the input goes high to VDD, the voltage at point A increases to VDD + (VDD  VT) ¼ 2VDD  VT to maintain a potential difference of VDD  VT across the capacitor. M2 allows the charge on CP to be transferred to CLoad but not vice versa. The voltage on CLoad increases to 2  (VDD  VT), provided CP  CLoad, and the pulse frequency allows the capacitors to fully charge and

8.6 Applications

439

M1

M2

VDD

VOUT A

CP

CLoad

VDD 0V Fig. 8.48 Simple charge-pump circuit utilizing a precision capacitor

Fig. 8.49 Simplified voltage-controlled oscillator C

Inductor

f =

Varactor

1 2p LC

discharge before changing states [117]. Non-ideal parameters in CP, such as parasitic capacitances, high dielectric absorption, voltage coefficient of capacitor, and leakage, degrade the performance of the charge pump [117].

8.6.3

Inductors and Varactors

Varactors and inductors are widely used in voltage-controlled oscillator (VCO) or in tuned stages such as in a radio receiver [100, 119, 120]. A simple LC circuit driven by voltage (or current) is shown in Fig. 8.49. Neglecting parasitic resistances, the resonant frequency fr is given by fr ¼

2π

1 pffiffiffiffiffiffiffiffiffiffiffiffiffiffi Hz LC ðV Þ

ð8:63Þ

where L is the inductance and C(V ) the voltage-controlled varactor capacitance. The oscillation frequency is determined by the capacitance and inductance values. The VCO can be tuned by an inversion-mode or accumulation-mode MOS varactor or by a junction varactor. The most important parameters of the VCO are a large frequency tuning range, low-power consumption, quality factor, and low phase noise. The varactor tuning ratio correlates directly to the VCO frequency tuning range [100, 119, 120].

440

8 Passive Components

Problems 1. The VDP sheet resistance of a poly resistor is RS ¼ 1 kΩ/□ at 27  C. For an average TCR of 2000 ppm/ C, estimate RS at 150  C. 2. Use the mobility relations in Chap. 2 to calculate the sheet resistance of a deep N-well having a Gaussian profile with a peak concentration of 5  1017 cm3 at a depth of 1.0 μm from the surface and a standard distribution of 0.3 μm. Find the sheet resistance and TCR for 25, 85, and 125  C. 3. Consider an N-well having a Gaussian profile with a peak donor concentration of 5  1017 cm3 at the silicon surface and a standard deviation (straggle) of 0.4 μm. Assume 25  C. (a) Find the depth of the junction formed between N-well and a 10 Ω-cm P-type substrate. (b) Use the mobility relations in Chap. 2 to estimate the full well sheet resistance. (c) Estimate the well to substrate parasitic capacitance in fF/μm2. (d) Find the sheet resistance of the well region under a 0.4-μm-thick shallowtrench isolation (STI). 4. A polysilicon resistor of sheet resistance RS ¼ 230 kΩ/□ at 27  C is formed over STI of thickness 0.4 μm. The TCR is 500 ppm/K, and the VCR is 2090 ppm/K2. (a) Plot the ratio RS(T)/RS0 from 0 to +125  C where RS0 is the sheet resistance at 27  C. (b) Plot the ratio RS(V )/RS0 from 10 to +10 V where RS0 is the sheet resistance V ¼ 0. (c) Find the average parasitic capacitance in fF/μm2 for a uniform substrate boron concentration under the STI of 1016 cm3 and + 5 V applied across the resistor. 5. The figure below is a schematic of a precision analog capacitor with SiO2 as the dielectric, designed in a cross-coupled arrangement. Show that this arrangement reduces the VCC when compared to a single equivalent capacitor having the same dielectric. Capacitor-1

Capacitor-2

Poly-2

Poly-2

Poly-1

Poly-1

V

WSi

SiO2

Field oxide (STI or LOCOS) Substrate

6. An MIM capacitor is formed with a triple ONO dielectric, consisting of 5-nm oxide, 10-nm nitride, and 10-nm oxide. Assume the dielectric constants to be 3.8 for oxide and 7.0 for nitride and

References

441

(a) Find the equivalent oxide thickness teq and capacitance in fF/μm2. (b) For 5 V applied between the metal plates, calculate the fields in the oxide and nitride films. (c) For a maximum allowable field in the oxide of 5  105 V/cm, what is the maximum voltage that can be applied to the capacitor? (d) What would be the maximum voltage if the dielectric was pure oxide of same teq as for the ONO structure? 7. An accumulation-mode varactor of the type shown in Fig. 8.39 is formed between N+-polysilicon and N-well. The equivalent oxide thickness is 25 nm and the N-well concentration uniform with ND ¼ 1017 cm3. The gate voltage with respect to N-well is pulsed from +1 to 1 V. Assume negligible generation of electron–hole pairs, and find the tuning ratio at 25  C. Neglect parasitic capacitances. 8. The minimum top metal width and space in a CMOS process are, respectively, W ¼ 0.5 μm and S ¼ 0.5 μm. Use the minimum dimensions to design a squareshaped inductor of L ¼ 10 nH. Disregard proximity and skin effects.

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Chapter 9

Process Integration

Abstract Processing steps to integrate active and passive components in a CMOSbased technology are discussed in this chapter. A basic description of unit processes is first presented. An overview of a baseline CMOS process is then given, followed by a discussion of process modules that are added to the baseline process to fabricate components for mixed-signal (MS) and radio-frequency (RF) CMOS, analog CMOS, high-speed BiCMOS, and Bipolar-CMOS-DMOS (BCD). Illustrative cross-sectional views of the numerous analog component constructions are provided.

9.1

Introduction

The preceding chapters reviewed in detail components used in mixed-signal (MS), radio-frequency (RF), analog, and power technologies, with emphasis on device physics, operation, and trade-offs between device parameters. This chapter describes the steps used to integrate those components and interconnects them in a single chip. A typical sequence of integration steps is shown in Fig. 9.1. The first step is to identify the required parameters for active and passive components and make sure that they are compatible with the tool capabilities. An initial process flow is then defined in steps of sequential modules, typically as an extension or modification of an existing base process (Fig. 9.2). The modules are detailed for each technology in the form of unit processing steps, process conditions, and dimensions compatible with the tool capabilities. Simulation of components, utilizing in-house or commercially available process and device simulation tools, is a very important part of integration. In this step, process conditions and component dimensions are iteratively adjusted to achieve the desired parameters prior to manufacturing. Simulation results are, however, not always accurate, necessitating experimental verification on specially designed test structures. As mentioned in Chap. 1, analog, mixed-signal, and RF technologies revolve around a baseline digital CMOS platform as outlined in Fig. 9.3. This is for two main reasons: First, most products require some amount of digital logic. Second, the initial © Springer Nature Switzerland AG 2020 B. El-Kareh, L. N. Hutter, Silicon Analog Components, https://doi.org/10.1007/978-3-030-15085-3_9

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448

9

Fig. 9.1 Typical sequence of integration steps. Implementation may require several iterations

Process Integration

Identify circuit requirements - designers’ inputs Define initial target component parameters Check tool capability Define modular process flow Detail modules and initial dimensions Simulate components Design and build test structures (device and yield) Characterize test structures, initiate WLR tests All parameters OK? No

Yes, proceed to statistical analysis, reliability assurance, full reliability test, manufacturing

Wafer: size, type, resistivity and tolerance, epitaxy or no-epitaxy Isolation: LOCOS, STI, NBL, PBL Wells: retrograde, anti-punch-through, VT adjust, drift, deep, special wells Second poly and insulator: PIP capacitor Gate stack: poly gate, gate dielectric, dual or triple oxide, oxynitride, high-k Source-drain LDD, halo, silicide BEOL: Al, Cu, low-k , vertical or lateral MIM capacitor, inductor

Fig. 9.2 Modular CMOS process flow. LOCOS, local oxidation of silicon; STI, shallow-trench isolation; NBL, N-buried layer; PBL, P-buried layer; PIP, poly-insulator-poly; high-κ dielectric; LDD, lightly doped drain; BEOL, back end of the line; low-κ, low dielectric constant; MIM, metalinsulator-metal

process flow developed in a new scaled-down technology is typically digital CMOS, constituting a convenient starting point for derivative processes. In terms of minimum feature size, MS and RF CMOS typically trail the leading edge digital CMOS by several “generations,” followed by analog CMOS and Bipolar-CMOS-DMOS (BCD). Each of the derivative technologies requires different components as shown in Table 9.1. A very basic description of unit processes is given in Sect. 9.3. An overview of a baseline CMOS process is presented in Sect. 9.4. Sections 9.5, 9.6, and 9.7 describe process modules that are added to the baseline process to fabricate components for MS and RF CMOS/RF BiCMOS, analog CMOS, and BCD.

9.1 Introduction

449

MS CMOS

Embedded Memory

RF CMOS

Digital CMOS

Analog CMOS

BCD

Analog Optimization

Time

Fig. 9.3 Technology migration paths for digital and analog designs. MS, mixed-signal; RF, radiofrequency CMOS/BiCMOS; BCD, Bipolar-CMOS-DMOS

Table 9.1 Component set for CMOS-based technologies Device LV logic CMOS LV analog CMOS HV logic CMOS HV analog CMOS Isolated NMOS Native NMOS Depletion-mode CMOS Buried-channel PMOS Drain-extended CMOS LDMOS Bipolar transistors JFETs Poly resistors High sheet poly resistor TFR Lateral flux capacitor Vertical MIM capacitor PIP capacitor Varactor Inductor Zener diode Total devices

Digital •

MS • • • • •

RF • • • • •

• •

•

•

•

• •

• •

Analog • • • • • • • • • • • • • • • • •

BCD • • • • • • • • • • • • • • • • • •

• 40–60

• 75–150

• • 5–10

15–25

25–35

450

9.2

9

Process Integration

Analog, Mixed-Signal, and RF Components

As the technology moves from digitally intensive MS and RF CMOS/RF BiCMOS to an analog-focused analog CMOS and BCD, the number of components in the technology increases due to the needs for higher voltage capability and precision in analog products (Table 9.1). As seen from Table 9.1, there are low-voltage (LV) and high-voltage (HV) versions of both digital and analog transistors. The two versions have applications across technologies. For instance, when high voltage is not a mandate, the HV-CMOS components in an MS or RF CMOS/RF BiCMOS technology can be replaced by components designed for LV analog which are smaller and use less power. Similarly, the HV-CMOS logic is used in many analog CMOS or BCD products that do not contain enough logic gates to warrant the addition of masking steps for the denser LV-CMOS.

9.3

Unit Processes

A process flow consists of a series of modules, each having a sequence of unit process steps. These are the individual steps used repeatedly throughout the process flow to create, isolate, and connect the components on a chip. This section provides a brief overview of commonly used unit processes that are applied across technologies. More detailed reviews can be found in [1, 2].

9.3.1

Starting Substrate

The most common starting substrate is 10 Ω-cm, P-type bulk silicon. In several applications, a lightly doped epitaxial layer (described below) is grown after a heavily doped buried layer is formed on the substrate. It is also grown for better uniformity and control of defects in active regions, particularly when large-diameter wafers are used. For applications where latch-up is a concern, the starting wafer typically consists of a P-type epitaxial layer grown on a P+-substrate (Chap. 11).

9.3.2

Photolithography

The components are typically created by patterns formed on the wafer by means of photolithography. Photolithography transforms complex component and circuit diagrams into patterns that are defined on a wafer in a succession of exposure and subsequent processing steps. A mask that contains the desired pattern in the form of

9.3 Unit Processes

451

clear and opaque regions is flooded with ultraviolet (UV) light and imaged onto the wafer which is covered with a photosensitive layer called resist. After developing, the image transferred to the resist serves as an intermediate pattern for subsequent processing steps.

9.3.3

Oxidation

The conversion of silicon into silicon dioxide or simply oxide (SiO2) is an important step in the manufacture of ICs. This step, referred to as thermal oxidation, is performed by subjecting the wafer at elevated temperature to an oxidizing ambient, such as dry oxygen, water vapor, or an in situ steam-generated SiO2 (ISSG). It is introduced at different stages of an integrated process for various purposes. In particular, the grown film provides a high-quality dielectric for MOSFET gates.

9.3.4

Ion Implantation

Ion implantation is a low-temperature process in which ionized dopants, such as boron, arsenic, phosphorus, and antimony, are accelerated to energies high enough so that when they impact on a target wafer surface, they penetrate to a certain depth. The implant dose precisely controls the number of atoms per unit area implanted into the exposed materials, while the implant energy controls the depth of the implanted species. Implant energies can range from 900
C). The impact of the high-temperature cycle on the baseline junction

9.6 Analog CMOS

483

N+ Implant N+ poly1, bottom plate

Resist

(a)

1 Intrinsic poly, gate

STI

P-substrate N+-Poly2, top plate

(b)

N+ Implant

IntrinsicGate-poly poly, gate

STI

N+ poly1

Capacitor dielectric

P-substrate

N+-Poly2 Capacitor dielectric

(c)

Intrinsic poly, gate

STI

N+ poly1

P-substrate Top Plate

Capacitor dielectric

STI

Bottom Plate

(d) P-substrate Fig. 9.30 PIP capacitor integration. (a) Resist patterning and N+-implant into the poly bottom plate. (b) Capacitor dielectric and poly 2 top-plate deposition and N+-implant. (c) Poly 2 patterning and etch. (d) Bottom-plate (CMOS gate, resistors) patterning and etch, silicidation (gate, resistors not shown patterned)

profiles is an important factor to consider when adopting the POCl3 process. After gate poly deposition, a dedicated masking step and implant are used to degenerately dope the poly which constitutes the bottom plate (Fig. 9.30a). An inter-poly dielectric (IPD) is grown or deposited, and a second poly is deposited and also heavily doped (Fig. 9.30b). The second poly and underlying IPD are then patterned and etched (Fig. 9.28c). The CMOS gate mask also serves to pattern the bottom plate of the capacitor. The remainder of the process follows the baseline process

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9

Process Integration

Boron implant Anode

Resist STI HV -well

STI

STI

P

HV P-well

Anode

STI HV N-well

STI HV N-well

P+ STI

Isolation N+ P

HV P-well

STI N+ STI Zener HV Diode N-well

Deep N-well

Deep N-well P-substrate

Cathode

P-substrate

(a)

(b)

Fig. 9.31 Buried Zener diode process. (a) Patterning and implant of Zener diode P-side (anode). (b) Source–drain implant (cathode) and silicidation

(Fig. 9.30d). Since the IPD is deposited early in the process (in the FEOL), it can be subjected to high-temperature treatment to improve trap density, leakage, and integrity.

9.6.9

Buried (Subsurface) Zener Diode

A buried Zener diode is a PN junction formed such that the breakdown of the junction occurs below the surface. It is preferred to other diode types because it exhibits a more stable breakdown voltage (Chap. 3). The process sequence of one type of a buried Zener diode is shown in Fig. 9.31. The P-side of the diode (anode) is implanted immediately before source–drain implantation using a dedicated masking step and boron implant (Fig. 9.31a). The dose and energy are tailored to obtain the desired breakdown voltage. The NMOS source–drain constitutes the N-side (cathode) of the diode and the PMOS source– drain in conjunction with the HV P-well forms the contact and connection to the anode (Fig. 9.31b). The device is isolated by means of deep N-well and a HV N-well ring.

9.7

Bipolar-CMOS-DMOS, BCD

BCD processes are typically based on an analog CMOS flow. The “bipolar” part consists of low-complexity NPN and PNP transistors discussed in Sect. 9.5.5 and in Chap. 5. The “CMOS” part comprises of LV-CMOS and HV-CMOS discussed earlier. This section focuses on the integration of the lateral DMOS (LDMOS). Additional BCD components and layers are summarized in Table 9.7.

9.7 Bipolar-CMOS-DMOS, BCD Table 9.7 BCD additional modules and layers

Component NLDMOS

HF NLDMOS Low-complexity NLDMOS Isolated-drain NLDMOS PLDMOS

9.7.1

485 Added layers Epitaxy N-buried layer, NBL P-buried layer, PBL N-drift region P-body HF P-body HF N-drift

P-drift region

Figure 9.32 9.35 9.32 9.30 9.33 9.31 9.34 9.35 9.36

NLDMOS

The integration of NLDMOS must comprehend both the low-side (LS) and high-side (HS) device styles discussed in Chap. 7. In the high-side configuration, the voltage on the P-body (and source) can vary from 0 to VDD, while the P-substrate remains at ground. This requires isolating the P-body from the substrate. In the low-side configuration, the P-body (and source) is at the same potential as the grounded substrate and hence does not require isolation. Thus, the integration scheme depends on the operating voltage and on how the LDMOS is connected in the circuit. (a) Epitaxy Process Circuits with HS NLDMOS operating at voltages above 24 V, or driving inductive loads, require a highly doped N-region between P-body and P-substrate to avoid punch-through between the two P-regions. This is best achieved with epi, allowing a highly doped N-region, referred to as N-buried layer (NBL), to be placed between the P-body and the P-substrate. NBL is patterned, implanted with high-dose arsenic or antimony, and annealed prior to epitaxial growth (Fig. 9.32a). A P-type epitaxial film is grown to a precise thickness at a uniform concentration close to that of the P-substrate (Fig. 9.32a). The NBL isolates the P-body from the P-substrate. The epi thickness is chosen to vertically separate the NBL from the P-body and achieve the necessary breakdown voltage between the two layers. The shallow-trench isolation, STI, is patterned, etched, filled with oxide, and planarized. The N-drift region is patterned and implanted with phosphorus at an appropriate dose and energy to achieve a profile that sustains the high voltage applied to the drain (Fig. 9.32b). The HV wells are then sequentially patterned and implanted. The P-body is then defined and implanted with boron at an appropriate dose and energy, followed by arsenic implant through the same opening to form a thin N-layer at the surface (Fig. 9.32c). The purpose of the N-layer is to self-align and ensure continuity between source and channel. After removal of the resist, the structure is subjected to a high-temperature anneal cycle during which boron diffuses much faster than arsenic, forming a lateral MOSFET channel region (Fig. 9.32d). The completed structure is shown with two identical NLDMOS structures arranged symmetrically

486

9

Process Integration

P-epi

tepi

(a) NBL P-substrate N-drift implant

Resist

Resist

STI

STI N-drift

Resist

STI N-drift

P-epi

STI

N-drift

(b)

NBL P-substrate

N-layer and P-body implant

Resist

Resist

STI

(c)

P-well N-well

STI

STI

N-drift

N-drift

N-layer

P-body

P-epi

STI N-well P-well

NBL P-substrate Gate oxide STI

(d)

STI

P-well N-well

STI

P-body

N-drift N-layer

P-epi

N-drift Channel

STI N-well P-well

NBL P-substrate Half-pitch

N+-Poly STI

N+

P-well N-well

(e)

N+

STI N-drift N-layer

STI N-drift

P+ N+ P-body P-epi

Channel

N+ P-well

STI N-well

NBL P-substrate

Fig. 9.32 High-side NLDMOS. (a) NBL and P-epi deposition. (b) N-drift implant. (c) P-body and N-layer implants. (d) Poly etch. (e) Source–drain and silicidation

9.7 Bipolar-CMOS-DMOS, BCD

487

in Fig. 9.32e. The “device pitch” describes the length of one LDMOS, a dimension also used when defining RSP. (b) Non-epi Process For operating voltages of 24 V or lower, a simpler option is to implant a deep N-well with phosphorus at high energy (1–3 MeV) into the P-type substrate, thus replacing the costly epi and NBL steps with only a deep N-well. Although the vertically integrated concentration in the deep N-well is lower than for NBL, isolation between the P-body and P-substrate is possible at the lower operating voltages. The remainder of the process is the same as in Fig. 9.32.

9.7.2

High-Frequency NLDMOS

For LDMOS applications at high frequency, the vertical and horizontal dimensions must be reduced to minimize the gate charge, the on-resistance, and the drain-tosubstrate capacitance (Chap. 7). This can be realized, for example, by reducing the HF P-body and HF N-drift dimensions, as illustrated for the high-frequency low-side NLDMOS (HF NLDMOS) in Fig. 9.33 [27]. After implanting the lightly doped drain (LDD), the HF NLDMOS HF P-body is implanted self-aligned to the sourceedge of the gate poly using a separate masking and implantation step (Fig. 9.33a). This is followed by another dedicated masking step to implant the HF N-drift layer self-aligned to the drain edge of the gate poly (Fig. 9.33b). The HF P-body and HF N-drift energy and dose are optimized to minimize the layer dimensions while sustaining the maximum operating voltage. The structure is shown in Fig. 9.33c after silicidation for two symmetrically arranged HF NLDMOS transistors with a common source and body contact. The same process sequence applies to a high-side HF NLDMOS, except that the structure must be isolated vertically with the deep N-well implant and laterally with an N-well ring. For a 12-V operating voltage, a unity-gain frequency of fT ffi 37 GHz and a maximum operating frequency fmax ffi 66 GHz were obtained [28]. For lower voltage applications (5–10 V), the process can be simplified by implanting a P-region at an angle through the same window as the LDD, thus saving one masking step. The P-region is similar to a halo but optimized to act as the HF P-body with the LDD acting as the HF N-drift region [28].

9.7.3

Low-Complexity NLDMOS

The NLDMOS process can be simplified by replacing the additional P-body with the existing P-well, eliminating one masking and implantation step. This is shown for an epi process in Fig. 9.34. The wells and N-drift regions are implanted as for the NLDMOS (Fig. 9.34a). The existing HV P-well masking and implantation steps are

488

9

Process Integration

HF P-body implant

Gate Poly

Resist STI

HF P-body

(a)

LDD P-substrate

LV P-well

Resist LV gate oxide

STI

HF N-drift implant Resist STI

HF P-body

(b)

LV P-well

STI

HF N-drift

P-substrate N+-Poly

STI

N+

(c) P-substrate

Silicide

N+

LV gate oxide

P+

N+

HF P-body LV P-well

Silicide block oxide N+ STI HF N-drift

Fig. 9.33 Integration of high-frequency LS NLDMOS. (a) HF P-body patterning and implant. (b) HF N-drift patterning and implant. (c) Source–drain and silicidation

used to also form the NLDMOS P-well (Fig. 9.34b). The remainder of the process is the same as for the HS NLDMOS (Fig. 9.34c). The two disadvantages of a low-complexity process are the loss of self-alignment of source to P-body and the lack of a lateral gradient in the channel when using the P-well instead of the double-diffused source and P-body process. Modern lithography tools, however, enable precise alignment of patterns on different masking levels relative to one another, considerably reducing misalignment. The one-sided graded channel obtained in a double-diffused process enhances the lateral field, improving speed. This feature is lost in the P-well process.

9.7 Bipolar-CMOS-DMOS, BCD

489 N-drift implant

Resist

Resist

Resist

N-drift

(a)

P-epi

N-drift

NBL P-substrate HV P-well implant Resist STI

(b)

HV HV P-well N-well

Resist STI

STI

HV P-well

N-drift

N-drift P-epi

STI

HV HV N-well P-well

NBL

P-substrate HV gate oxide

N+-poly

(c)

STI N+ HV HV P-well N-well

STI N-drift

N+ P+ HV P-well

N+

N+-poly N+ STI STI HV N-drift HV P-epi N-well P-well

NBL P-substrate

Fig. 9.34 Low-complexity HS NLDMOS. (a) N-drift implant. (b) HV P-well implant. (c) Source– drain and silicidation

9.7.4

Isolated-Drain NLDMOS

In a standard HS NLDMOS as in Fig. 9.34, the drain is shorted to the N-well ring and NBL, resulting in a large drain area. This increases the drain capacitance and does not allow biasing the drain independently of the N-well ring and NBL isolation. An isolated-drain NLDMOS solves the problem by separating the drain and N-drift region vertically from the NBL and laterally from the N-well ring by P-epi regions (Fig. 9.35). The integrated P-epi concentration along the separations can, however, be too small to avoid punch-through between the regions at the operating voltage. The lateral distance between the drain and N-well ring can be increased to avoid lateral punch-through. To maintain a small vertical distance between N-drift and

490

9

N+ STI HV N-well

N+ STI N-drift

N+

P+

N+ P-body

P-Epi

N+ STI

STI

N-drift

PBL

(a)

Process Integration

N+

HV N-well

NBL P-substrate

N+ STI

N+ STI N-drift

HV N-well

(b)

N+

P+

N+ P-body

STI

N-drift

P-Epi PBL

N+ STI

PBL

N+

HV N-well

NBL P-substrate

Fig. 9.35 Isolated-drain HS NLDMOS options. (a) Separate mask for PBL implant prior to epi growth. (b) High-energy PBL implant through same mask as N-drift

NBL, and also improve speed, the concentration in the P-epi in the separation regions can be increased by either adding dedicated masking and implantation steps to form a buried P-layer (PBL) above the NBL prior to epitaxial growth (Fig. 9.35a) or by implanting boron at high energy through the same mask opening as the N-drift region after epi growth (Fig. 9.35b). The advantage of using a separate mask and implantation step is the higher flexibility in PBL concentration and placement.

9.7.5

PLDMOS

The integration schemes of an NLDMOS and an HF NLDMOS can be applied to a PLDMOS and HF PLDMOS by reversing the dopant polarities. The HF PLDMOS must, however, be isolated with a deep N-well or NBL and an N-well ring. The two structures are shown after silicidation in Fig. 9.36a, for the case of an NBL isolation.

Problems

491

HV gate oxide

P+-poly STI N+ STI P+ STI P-drift (a) HV N-well

P+

N+ P+

HV N-well

Isolation contact

P+-poly

STI P+ STI N+ STI P-drift HV N-well

NBL P-substrate P+-Poly

N+ STI

(b)

Silicide

P+

HV N-well

P+ N-body

LV gate oxide N+

P+

N-well

Silicide block Isolation oxide contact P+ P-drift

STI

N+

HV N-well

NBL P-substrate

Fig. 9.36 PLDMOS integration. (a) Conventional PLDMOS. (b) High-frequency PLDMOS

Problems The temperature is 25
C unless otherwise stated. 1. Describe a process with one polysilicon level and eight copper metal levels to fabricate the following components: LV-CMOS, HV-CMOS, isolated CMOS, DECMOS, LFC, NPN, and inductor. Assume existing metal levels are used for the inductor. 2. The four identical NMOS devices in the figure below must be isolated from substrate without changing their layout. Show a top view and cross-sectional view for how this can be done while minimizing the overall area consumed. Discuss your assumptions. Active

Contact

Polysilicon

3. For an isolated native NMOSFET with a substrate concentration of 1015 cm3 and a maximum drain voltage of 5.5 V:

492

9

Process Integration

(a) Show a top- and cross-sectional view. (b) Estimate the minimum channel length to avoid punch-through between source and drain. (c) Estimate the minimum distance between drain and underlying N-region required to avoid punch-through between the two regions. Assume a step junction in both cases and ND ¼ 5  1017 cm3 in the deep N-region. 4. The figure below describes via etching to both plates of a MIM capacitor with oxide as the dielectric. Determine the minimum capacitor top-plate thickness under the following conditions: (a) IMD thickness ¼ 1 μm, (b) capacitor density ¼ 1 fF/μm2, (c) a 10% via over-etch of IMD is done, (d) the IMD to top-plate metal selectivity is 25:1, and (e) the etched thickness of the top-plate metal must be 100 μA/μm2, because of the variability in high-level injection effects and in voltage drops across emitter, base, and collector series resistances (Chap. 5) [59]. Between the two extreme regions, mismatch variability is almost constant over several orders of magnitude of the active operating region [57–61].

10.2.7 Resistor Mismatch Mismatch between resistor pairs is caused by variability in sheet resistance, resistor width and length, and end resistance, including contact end edge resistance. The resistance can be expressed as (Chap. 8) [62, 63]

10.2

Mismatch

509

Fig. 10.12 Example of standard deviations of N+poly and P+-poly resistance versus inverse square root of resistor area

1.5

σΔR/R (%)

N+-Poly 1.0

P+-Poly

0.5

0 0

0.05

0.10

0.15

1/ Weff Leff

R  RS

ðLD  ΔLÞ 2Rend þ Ω ðW D  ΔW Þ ðW D  ΔW Þ

0.20

0.25

-1

(μm )

ð10:19Þ

where RS is the sheet resistance of the resistor body. LD and WD are the drawn resistor length and width, ΔL and ΔW the difference between drawn and effective length and width, and Rend is the end resistance that includes the interface and contact resistances. For typical resistors, the end resistance is dominated by the interface resistance, i.e., the transition from silicide to silicon. Similar to the case of a transistor, the variance of resistor-body mismatch can be expressed as [2, 4–6, 62] σ ΔR AR ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi %
R W eff Leff

ð10:20Þ

where AR is a process-related constant. An example of the dependence of standard deviation of resistance mismatch versus inverse square root of resistor area is shown in Fig. 10.12 for N+-poly and P+-poly resistors of 250–300 Ω/□ sheet resistance. The lower P+-poly resistor mismatch distribution has been attributed to the larger grain size with boron-doped compared to phosphorus or arsenic-doped polysilicon [64]. Figure 10.13 shows matching results obtained on a pair of 1.1 kΩ/□ phosphorusdoped polysilicon resistors. The graph includes room temperature measurements made at both constant voltages and constant currents per unit width [64]. Matching is independent of operating point in this range. Thin-film resistors (TFR) typically exhibit a significantly lower mismatch than similarly sized polysilicon resistors. One study shows a mismatch constant about 20 times lower for 50 Ω/□ tantalum-nitride resistors than for N+-polysilicon resistors [65].

510

Mismatch and Noise

1.0 :V 0.8 σΔR/R (%)

Fig. 10.13 Mismatch of a 1.1 kΩ/□ polysilicon resistor-pair as a function of inverse resistor area obtained for three operating points. (Adapted from [64])

10

= 100 mV

:V = 500 mV : I/W = 5 μA/μm

0.6 0.4 0.2 0.0 0.0

0.05

0.10

0.15

0.20

0.25

-1

1/ Area (μm ) Fig. 10.14 The floatinggate capacitance measurement method (Adapted from [69, 71]). Cpar is the parasitic capacitance

ID VIN VOUT C1 Floating node C2

Cpar

10.2.8 Capacitor Mismatch The mismatch of integrated capacitor pairs is approximated by [66] σ 2ΔC A2C σ 2W σ 2L  þ þ W eff Leff W 2eff L2eff C
2

ð10:21Þ

where, for an oxide dielectric, AC is estimated at about 4% μm but can be larger for other dielectrics due to the larger variability in thickness and dielectric constant. The standard deviations σ W and σ L represent, respectively, the line-edge variations due to the roughness caused by lithography and etching along the capacitor width and length. They typically have the same values. Direct measurement of small capacitances can be time-consuming and increasingly inaccurate as the dimensions are reduced. A simple, accurate, and fast method to measure small capacitances using the principle of capacitance voltage division is developed in [67–69] and then later refined to measure the mismatch between capacitor pairs [70–72]. The basic principles of the method are described in Figs. 10.14 and 10.15.

Mismatch

Fig. 10.15 Example of output characteristics of the floating-gate capacitance measurement method and definition of the slope S. (Adapted from [69])

511 6 VOUT = S ·VIN + V0 (ID) 5 ID = 10 μA VOUT (V)

10.2

4 VOUT, Hi

1 μA S = C1/(C1+C2)

100 nA

3

VOUT, Lo

2

10 nA VIN,Lo

1

0

1

2

3 VIN (V)

VIN,Hi 4

5

The capacitor C1 to be measured is connected in series with a reference capacitor of known value C2 and their common node connected to a floating gate of a sensing MOSFET operating in a source-follower configuration. The MOSFET drain and the second plate of the reference capacitor are grounded. A voltage VIN is applied to the outer plate of the capacitor to be measured. A constant current ID is forced through the MOSFET, establishing a fixed gate-to-source potential that depends on the current amplitude. The voltage on the floating node depends on the capacitance ratio of the two capacitors. In the source-follower configuration, a change in VIN induces the same change in source potential so that, when parasitic capacitances can be neglected, a plot of VOUT versus VIN yields a linear relationship having a slope (Fig. 10.15) S ¼ C 1 =ð C 1 þ C 2 Þ

ð10:22aÞ

The unknown capacitance can be extracted from (10.22a) as C1 ¼ C2

S 1S

ð10:22bÞ

The floating-gate method is applied to the measurement of matching by determining the difference between two identically designed capacitors instead of the ratio between a known and an unknown capacitor [70, 71]. The relative capacitor mismatch is ΔC=C
¼ ðC 1  C2 Þ=C
%

ð10:23aÞ

C
¼ ðC 1 þ C 2 Þ=2 F

ð10:23bÞ

where

512

10

Mismatch and Noise

The capacitor mismatch can then be extracted from the slope S as ΔC=C
¼ 4ðS  0:5Þ %

ð10:24Þ

When the capacitor mismatch drops below about 0.05%, the impact of the parasitic capacitance, Cpar, on accuracy becomes noticeable. A double-slope technique improves the measurement accuracy. The first slope, S1, is obtained by connecting C1 to VIN and C2 to ground. To obtain the second slope, S2, C2 is connected to VIN and C1 to ground [71]. Assuming that the parasitic capacitance Cpar is the same for both configurations, S1 ¼

C1 C2 ; S2 ¼ C1 þ C2 þ C par C 1 þ C 2 þ Cpar

ð10:25Þ

The extracted mismatch is then independent of Cpar: ΔC S1  S2 C1  C2 ¼2 % ¼2 S1 þ S2 C1 þ C2 C


ð10:26Þ

A more sophisticated differential floating-gate mismatch measurement technique which is believed to further improve the resolution is detailed in [72]. The floatinggate technique can become inaccurate in the presence of leakage through the gate dielectric. It is therefore important to ensure that the dielectric is defect-free and sufficiently thick to sustain the gate voltage without appreciable leakage [73]. A curve fit to measured data is shown in Fig. 10.16. In square-shaped capacitors, the last two terms in (10.21) have an equal effect on area. Thus, thepmismatch ffiffiffiffiffiffiffiffiffiffi variance σ(ΔC)/C of square-shaped capacitors follows the first-order 1= Area law. An appreciable departure from this law is observed on capacitors with different W and L [66].

0.25 Sample dimensions (μm2) 1: 2: 3: 4: 5: 6:

(%)

0.20

0.15 σΔC /C

Fig. 10.16 Measured mismatch variance of capacitors versus inverse square root of area. A departure from the 1/WL law is observed on non-squareshaped capacitors. (Adapted from [66])

Curve-fit to measured data 1

1/ WL - law

26.5 x 26.5 37.5 x 37.5 52.5 x 52.5 74.5 x 74.5 149.5 x 74.5 298.5 x 74.5

2 3

0.10 4 6

5

0.05 0.005

0.010

0.015

0.020

0.025

1/ WL

0.030

(μm-1)

0.035

0.040

10.3

10.3

Noise

513

Noise

Noise in electronic circuits is defined as random fluctuations in signal current or voltage. It is the main limitation of the accuracy of a measuring device and ultimately sets a lower limit on signals that can be detected and processed [74, 75]. Noise can originate from external sources or can be inherent to a component as a result of random fluctuations of carrier transport within the component. This section deals with random noise, in particular low-frequency noise, since most analog circuits operate at frequencies below about 1 kHz. Referring to Fig. 10.17, the average value of the current noise, in, obtained by integrating over sufficient time is zero and therefore not useful for noise analysis. This is why the mean square of noise current i2n or voltage v2n is used to describe the noise power. The noise power varies with frequency, particularly in the low-frequency range. A measure of how it is distributed over frequency is called the current or voltage noise power spectral density (PSD), defined as Si ¼ i2n =Δf A2 =Hz

ð10:27aÞ

Sv ¼ v2n =Δf V2 =Hz

ð10:27bÞ

where Δf is the bandwidth, i.e., the frequency range over which noise is measured. Consider a conducting bar of length L containing a total number of carriers N. A small field, E, along the bar produces an average current I
¼ qNvd =L A

ð10:28Þ

where vd ¼ μE is the individual carrier velocity and μ is the individual carrier mobility. Both N and μ can fluctuate as N ðt Þ ¼ N
 ΔN ðt Þ cm3

ð10:29aÞ

μðt Þ ¼ μ  Δμðt Þ cm2 =Vs

ð10:29bÞ

Thus, the noise sources can be discussed in terms of number fluctuations [76], mobility fluctuations [77], or a combination of both.

I ( t ) = I + in ( t ) I (t)

Fig. 10.17 Illustration of current noise, in(t), superimposed on an average signal current I


I Time, t

514

10

Mismatch and Noise

10.3.1 Classification of Noise Noise sources are classified as thermal noise, shot noise, generation-recombination noise, and flicker noise, also known as 1/f noise. (a) Thermal Noise Thermal noise, also called Nyquist or Johnson noise [78, 79], is due to the random motion of carriers in a conductor of resistance R. The average thermal carrier velocity at a temperature T is (Chap. 2) v
th ¼

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 3kT=m  107 cm=s

ð10:30Þ

where m* is the carrier effective mass, k is the Boltzmann constant (k ¼ 8.62  105 eV/K ¼ 1.38  1023 J/K), and T ¼ 300 K. In the absence of an electric field, the centroid of carriers does not move in a specific direction on the average. In short periods of time, however, more carriers can move in one direction than in the other, causing the noise. When a low-to-medium electric field is applied, a current is induced by carrier drift along the field with a drift velocity that is much smaller than the thermal velocity. Thus, the noise is unaffected by the presence or absence of direct current and is directly proportional to T [74]. The thermal current and voltage noise PSDs are given as Si ¼ i2n =Δf ¼ 4kT=R A2 =Hz

ð10:31aÞ

SV ¼ v2n =Δf ¼ 4kTR V2 =Hz

ð10:31bÞ

or

Example 10.1 Find the thermal voltage noise PSD in a resistor of resistance R ¼ 1 kΩ at 300 K. Solution The voltage noise PSD is found from (10.31b) as Sv  1:66  1017 V2 =Hz The thermal noise PSD is independent of frequency and hence called white noise. This is the case up to a frequency of 1013 Hz [74]. The noise level is sometimes specified as a temperature-equivalent extracted noise, e.g., from (10.31b) as T n ¼ v2n =4kRΔf K or a resistance equivalent noise

ð10:32Þ

10.3

Noise

515

Rn ¼ v2n =4kT 0 Δf Ω

ð10:33Þ

where T0 ¼ 290 K is the standard noise temperature. If only thermal noise is present, then Tn and Rn are the actual temperature and resistance. Otherwise, they can be higher [75]. (b) Shot Noise Shot noise is a random event related to the energy of individual carriers that are transported over a barrier. It is thus present in diodes, MOSFETs, and bipolar transistors. In contrast to thermal noise, shot noise is always associated with direct current and depends on the carrier energy and velocity directed toward the barrier. Thus, the current I that appears to be at a steady level actually consists of random current pulses. The shot noise current is a random process with a PSD [80] i2 =Δf ¼ 2qI
A2 =Hz

ð10:34Þ

where I
is the average current. For a PN junction, (10.34) holds as long as the frequency f is lower than 1/τ, where τ is the carrier transit time through the junction depletion region. Since typically τ < 10 ps, the shot noise remains frequency independent (white spectrum) up to frequencies in the higher GHz range [74, 75]. Example 10.2 Find the shot noise current spectral density in a PN junction under forward bias at VF ¼ 0.8 V. Assume low-level injection, a saturation current IS ¼ 3  1017 A, and 300 K. Solution The forward current–voltage characteristic in low-level injection is defined in Chap. 3 as   I F ¼ I S eqV F =kT  1 A

ð10:35Þ

where VF is the forward bias. Substituting the values for IS and Vp gives F ffiffiffiffiffiffi IF ¼ 103 A. From (10.34), the noise current PSD is 1:8  1011 A= Hz. (c) Generation-Recombination Noise The Shockley-Read-Hall (SRH) generation-recombination process is described in Chap. 2. It is associated with localized electronic states, called “traps,” with energies in the forbidden gap either at the surface or in the bulk. The traps can randomly capture or emit carriers. This causes current or voltage noise in the conducting medium as a result of fluctuations in the number of carriers, electric field, and mobility.

516

10

Mismatch and Noise

1.015 τ1 EC ID (μA)

High

High

1.010

EV

ΔID

1.005

Low

1.000 τ0

Low 0.995 Oxide

Silicon

0.05

0.10 0.15 Time (s)

(a)

0.20

(b)

Fig. 10.18 Schematic representation of RTS for a single trap with different time constants in NMOS. (a) Electron trapping and detrapping. (b) RTS-like noise [75]

(d) Random Telegraph Signal Noise Random telegraph signal noise (RTS or RTN), also known as “popcorn” or “burst” noise, may be considered as a special case of generation-recombination noise observed at low frequencies [81]. It is observed in long- and wide-channel JFETs, where the trap density is very low [82], in bipolar junction transistors [83], or in MOSFETs of small channel dimensions, where only a few traps are present and individual events of trapping and detrapping of carriers can be observed [84–93]. Consider, for example, an NMOS of very small dimensions biased in the linear mode. For a single-energy trap, capture of an electron from the inversion layer and emission of the electron back to the inversion layer causes the current to switch randomly between two levels, spending an average time τ0 in the low state and τ1 in the high state, and resulting in a waveform similar to that of an RTS (Fig. 10.18). When multiple trap levels are “active,” the RTS exhibits more than two current levels. For a current I, the PSD for generation-recombination noise has a frequencydependent Lorentzian-shape (Fig. 10.19) [74, 75, 81, 84–93]. It is expressed as [75, 81] Si ¼


i2 I
γ 2 A  2 A =Hz Δf f 1þ f

ð10:36Þ

c

where A is a frequency-independent process constant that depends on the total number of traps, and γ ffi 2. The corner frequency fc is given by fc ¼

  1 1 1 Hz þ 2π τ0 τ1

ð10:37Þ

where 1/τ0 is the probability for a trap to be occupied by an electron and 1/τ1 the probability that the trap is not occupied by an electron. The PSD for a single trap is

Noise

517

Fig. 10.19 Lorentzianshaped power spectral density for a single trap of RTS-like noise in Fig. 10.18 [75, 81]

10-18 fc 10-19 Si (A2/Hz)

10.3

1/f2 10-20 10-21

10-22 1

10

100 Frequency (Hz)

1000

10000

shown in Fig. 10.19 for I ¼ 1 μA, A ¼ 5  107 Hz1, and τ0 ¼ τ1 ¼ 10 ms. The corner frequency for this case is fc ffi 32 Hz, and the frequency dependence follows a 1/f2 “law.” As the frequency increases from zero, the probability of trapping and detrapping carriers during the period of a signal decreases. Example 10.3 Consider an NMOS of channel length Leff ¼ 180 nm and channel width Weff ¼ 220 nm with an effective interface trap density Nit ¼ 5  109 cm2. (a) Estimate the expected number of traps in the channel. (b) The NMOS is biased at VG  VT ¼ 1 V and VD ¼ 0.05 V. Assume an equivalent oxide thickness teq ¼ 3 nm, and estimate the fractional change in the number of inversion electrons when a single inversion electron is captured by a trap. Solution (a) The expected number of traps over the channel is N it  W eff  Leff ¼ 5  109  1:8  105  2:2  105 ffi 2 (b) The oxide capacitance is (Chap. 6)
 C ox ffi 8:86  1014  3:9 =3  107 ffi 1:15  106 C=cm2 For the given bias conditions, the total number of inversion electrons is N ffi ðV G  V T Þ  W eff  Leff  Cox =q N ffi 2:2  1:8  108  1:15  106 =1:6  1019 ffi 2:85  105 Electrons The number of electrons decreases by 3.5 ppm when a single electron is captured by a trap.

518

10

Fig. 10.20 Schematic representation of flicker noise PSD versus frequency

Mismatch and Noise

1/f noise

i 2 (f) Δf

2 White noise i

Δf

Log

( i /Δf )

Total noise

2

i2

1/f

Corner frequency

Log f

(e) Flicker or 1/f Noise Flicker noise is a low-frequency noise that is known to result from carrier trapping and detrapping by electronic states within the forbidden gap in the semiconductor bulk, at its surface, and within the dielectric. It is always associated with direct current and has a PSD that follows approximately a 1/f law of the general form [74, 75, 94–98] (Fig. 10.20) i2 Ia ¼ KF b A2 =Hz Δf f

ð10:38Þ

where KF is a process constant, and typically a  2, b  1. The information gained from RTS-like noise is very valuable to modeling the flicker noise. There are many traps within the silicon bulk, at the silicon interface with a dielectric, and within the dielectric. The traps are distributed in energy levels and distances from the carriers, resulting in a large number of “Lorentzians” with distributed time constants. It is now believed that the 1/f characteristic of low-frequency noise is the result of the superposition of Lorentzians, as illustrated for four different time constants in Fig. 10.21 [75, 84, 88]. The response at very low frequencies is attributed to energetically deep traps, typically within the dielectric. The response at higher frequencies is related to shallower traps. In this model, it is assumed that the traps do not interact so that the generation-recombination noise spectra can be added.

10.3.2 1/f Noise in CMOS Although several models have been suggested to explain the 1/f noise in CMOS [76, 77, 86, 95, 97, 99–101], it is still difficult to obtain a unique relationship between flicker noise and MOSFET processing conditions. The flicker noise in CMOS results from capture and release of inversion carriers by traps at the dielectric–silicon interface or within the dielectric at a small distance z from the

Noise

Fig. 10.21 Superposition of four “Lorentzians” resulting in a PSD that approximately follows a 1/f frequency dependence of flicker noise. (Adapted from [75])

519

10-17 Resultant

10-18

SI (A2/Hz)

10.3

1 1/f

10-19

2 3

10-20

10-22 100

4

1/f2

10-21

101

102

103

104

Frequency, f (Hz) interface. The trapping and detrapping of carriers occur through a tunneling process with a time constant τ or distance z given by [76]   1 cm ð10:39Þ τ ¼ τ0 ðE Þez=λ s or z ¼ λ ln 2πf τ0 where E is the trap energy and τ0 is the trapping time constant for a trap located at the interface (typically 1010 s). λ is the tunneling attenuation length given by [75, 87, 102, 103]  1 4π pffiffiffiffiffiffiffiffiffiffiffiffiffi  cm 2m ϕb λ¼ h

ð10:40Þ

In (10.40), h is Planck’s constant, m* is the carrier effective mass, and ϕb is the tunneling barrier height seen by a carrier at the interface. Assuming ϕb ¼ 1 eV, (10.40) gives λ ffi 0.1 nm. For f ¼ 1 Hz, (10.39) gives z ffi 2.1 nm. In a given MOSFET, the flicker noise can be reduced by decreasing the concentration of traps, increasing the distance of traps from the conducting layer, and increasing the tunneling barrier height. (a) Input-Referred and Drain Current Noise Consider the inversion layer of an NMOS, and assume for simplicity that the drain voltage is very small and the MOSFET operates in the linear mode. The average inversion resistance per unit channel width is (Chap. 6) L Ω R
¼ qNμ

ð10:41Þ

520

10

Mismatch and Noise

where N
is the average number of electrons per unit area and μ is the average electron mobility. A small drain field E across the resistor produces an average current per unit width I
¼ qNμE A=cm

ð10:42Þ

Trapping and detrapping of carriers cause fluctuations in the number of an ensemble of carriers and in the vertical field modifying the threshold voltage and carrier mobility and causing fluctuations in drain current. Thus, the mobility fluctuation and number fluctuation in (10.29a) and (10.29b) are correlated [86, 99]. If one considers only the carrier number fluctuation, the input-referred (gate) noise PSD in saturation is approximated as [75, 76, 104, 105] SV G 

q2 kTN T λðϕb Þ 1 V2 =Hz W eff Leff C2ox f γ

ð10:43Þ

where k is the Boltzmann constant (8.62  105 eV/K), T is the absolute temperature (K), NT is the trap density in cm3 eV1, λ(ϕb) is the tunneling attenuation distance given by (10.40), Weff and Leff are the channel width and length (cm), Cox is the equivalent gate oxide capacitance (F/cm2), f is the frequency (Hz), and γ  1. Since the trap density depends on the position of the Fermi level, SV G depends on the biasing point. For example, assuming an effective trap density of 1018 cm3 eV1 at the bias condition, λ ¼ 0.1 nm, and T ¼ 300 K, then (10.43) can be approximated as SV G 

KF 1 2 V =Hz 2 f W eff Leff C ox

ð10:44Þ

where KF ffi 6.6  1030 C2/V. The input-referred (gate) noise is proportional to the effective density of traps and to the square of dielectric thickness, and inversely proportional to the effective gate area and gate-dielectric constant. The value of KF in (10.44) typically varies from one device to another and across technologies. This is because the flicker noise strongly depends on the trap density and distribution which are sensitive to process and bias conditions. The relation between inputreferred noise PSD and drain current noise PSD in saturation, SI D , is SI D ¼ g2m SV G ffi

q2 kTN T λðϕb Þ I 2D 1 2 A =Hz 2 2f W eff Leff C ox 4ðV G  V T Þ

ð10:45aÞ

or KF 0 I 2D 1 2 SSI D ffi 0 2 1 A =Hz ID W eff LKF eff C ox f ffi Hz1 I 2D W eff Leff C2ox f

ð10:45bÞ ð10:45cÞ

10.3

Noise

521

Fig. 10.22 Comparison of drain current noise PSD for surface-channel NMOS and buried-channel PMOS [107]

W/L = 10/0.6; teq = 13 nm, 300 K VG = VT ± 1 V, VD = 2.5V

SID (A2/Hz)

10-16

Surface-channel NMOS

10-17 10-18

Buried-channel PMOS

10-19

10-20

10

100

1/f

1000

Frequency, f (Hz) where KF0 is a function of process and gate voltage. The ratio on the left of (10.45c) is called the normalized drain current noise. It decreases with increasing ID unless noise mechanisms other than the inversion layer noise dominate. The relations for SV G and SI D become more complex when the effective mobility and the different modes of MOSFET operation are taken into account [75, 105, 106]. An empirical relationship for the total drain current noise in a MOSFET is [75]
i 2D ffi 4kT ð2gm =3ÞΔf þ

KF 0 I 2D 1 Δf A2 W eff Leff C2ox f

ð10:46Þ

The first term in (10.46) is the thermal noise generated in the channel of approximate resistance 2gm/3, and the second term is the flicker noise. Figure 10.22 shows the frequency dependence of the drain current noise PSD, SI D , for surfacechannel NMOS and PMOS. The buried-channel PMOS shows a considerably lower flicker noise than the surface-channel NMOS mainly because a large part of the carriers in the buried-channel PMOS flows below the surface where the trap density is lower and the tunneling barrier to surface traps is higher. (b) Effects of Hydrogen, Fluorine, and Nitrogen on Flicker Noise Anneal conditions have a strong impact on trap density and distribution. It is well known that annealing in hydrogen or forming gas (10% hydrogen and 90% nitrogen) at 400–450 C after metallization considerably reduces the interface-state density and hence the flicker noise. This is particularly the case after plasma processes (Chap. 9). Incorporating fluorine into the oxide–silicon interface not only reduces the noise [108, 109] but also increases the dielectric immunity to hot-carriers and biastemperature stress [110–112]. The reduction of 1/f noise by fluorine is shown for a buried-channel PMOS in Fig. 10.23. The noise decreases approximately proportional to 1/f in both cases. For the fluorinated oxide, the noise decreases to the level

522

Mismatch and Noise

10-16 W/L = 20/1.5; teq = 15 nm, 300 K VG = -1.9V; VD = -1.5V

10-17

10-18 SID (A2/Hz)

Fig. 10.23 Comparison of drain current noise PSD for buried-channel PMOS with pure and fluorinated gate oxide [107]

10

10-19

Buried-channel PMOS, pure oxide

10-20 10-21

Buried-channel PMOS, fluorinated

1/f

10-22 10-23 10-24 10-1

White noise level

100

101 102 103 Frequency, f (Hz)

104

105

of thermal noise at about 104 Hz. The reduction of noise is attributed to the bonding of silicon dangling bonds by fluorine [112]. Fluorine is typically incorporated into the oxide by implantation into the polysilicon gate and subsequent annealing. Fluorine diffuses rapidly and accumulates near the oxide–silicon interface [108–112]. A fluorine dose above ~2  1015 cm2 causes an increase in oxide growth [112]. It is important not to implant fluorine directly into silicon and to limit the fluorine dose below ~3  1015 cm2 to avoid damage to silicon. Depending on the thermal budget, incorporating fluorine into the gate oxide accelerates boron penetration through the oxide and is avoided in PMOS when the oxide thickness drops below approximately 10 nm [113–115]. Nitrogen is incorporated into the oxide to form oxynitrides (NO) and prevent boron penetration in PMOS, particularly through ultra-thin oxides. As with fluorine, NO improves the dielectric immunity to hot-carriers [116, 117]. The effective gatedielectric constant also increases with increasing nitrogen content. MOSFETs with NO, however, exhibit higher 1/f noise than pure oxide [118–120]. A comparison of drain current noise spectra shows that noise increases by about 30 times as the technology scales from 350 to 130 nm [118]. This is attributed to the transition from a pure oxide to oxynitride gate dielectric with increasing nitrogen content as the gate oxide thickness is scaled down (Chap. 6). The impact of nitrogen content on noise is more pronounced for PMOS than for NMOS [119]. Incorporating nitrogen into the oxide–silicon interface increases 1/f noise by creating traps in the oxide at close proximity to the interface [120]. An increase in noise can be avoided by locating the nitrogen peak in the oxide away from the interface while still suppressing boron penetration. This can be achieved by plasma nitridation of oxide (PNO) which places the centroid of the nitrogen distribution near the top of the gate oxide [121, 122]. (c) Effect of Shallow-Trench Isolation on RTS and Flicker Noise The presence of STI along the carrier path typically increases the total area of the silicon–oxide interface and hence the noise. In addition, the STI sidewalls along (110) planes exhibit a higher interface trap density when compared to the (100) plane at the silicon interface with the gate oxide. Carriers traveling along STI boundaries of

Noise

523

Fig. 10.24 Effect of reduced STI-bounded NMOS channel width with each “generation” on RTS [124]

15

Relative RTS to RTS-1

10.3

10

5 RTS-1

1 0

50

100 150 200 Technology (nm)

250

300

the channel exhibit higher RTS and 1/f noise than in other regions of the channel [123–125]. This is attributed to the increased density of traps induced by the high electric field at STI corners [123–125]. As the MOSFET width decreases with each “generation,” the fraction of noise contributed by STI edges increases or even dominates in narrow-width MOSFETs (Fig. 10.24).

10.3.3 1/f Noise in Resistors Noise in polysilicon resistors is expressed in terms of Hooge’s empirical relation [75, 97, 126–131]: SI R α H 1 Hz1 ffi N f I 2R

ð10:47Þ

where αΗ is a dimensionless parameter referred to as Hooge’s constant which ranges from 104 to 102, depending on the structure. N is the total number of carriers in the resistor, and IR is the current through the resistor. For a resistor of thickness t, (10.47) can be expressed as SI R αH 1 αH 1 KF R 1 ffi ¼ ¼ Hz1 2 nW eff Leff t f nS W eff Leff f W eff Leff f IR

ð10:48Þ

where n is the carrier concentration per unit volume, nS is the sheet carrier concentration, i.e., the concentration per unit area, t is the resistor thickness, and KFR is a process-dependent parameter. The current (or voltage) noise is proportional to the square of the current (or the voltage) across the resistor. It is inversely proportional to the area and height of the resistor and to the frequency. The sheet resistance is given as (Chap. 2)

524

10

Fig. 10.25 Measured frequency dependence of current noise PSD in N+poly and P+-poly resistors [107]

10-19

L/W =100/2 RS= 250-300 Ω/ I = 0.5 mA, 300K

10-20 SIR (A2/Hz)

Mismatch and Noise

10-21

1/f N+-Poly

10-22 P+-Poly 10-23 10-24 101

102

103

104

105

Frequency, f (Hz) RS ¼ 1=ðqnS μÞ Ω=□

ð10:49Þ

where μ is the carrier mobility, which is not a constant. In Hooge’s model, it is the fluctuation in μ which causes a fluctuation in RS and hence in current. The mobility fluctuates as a result of capture and emission of carriers by traps at grain boundaries and the associated variations in the barrier height. The frequency dependence of current noise PSD is shown in Fig. 10.25 for N+-poly and P+-poly resistors of comparable sheet resistance. The low-frequency noise exhibits approximately a 1/f dependence. Since the carrier mobility is lower in P+-poly than in N+-poly resistors, a larger number of carriers, N, are required in P+-poly than in N+-poly to achieve comparable sheet resistances. According to (10.47), an increase in N reduces the noise. The integrated noise current in the frequency range between 10 and 1000 Hz is shown for a phosphorus-doped polysilicon resistor as a function of the square of resistor current in Fig. 10.26. The linear relationship between the square of current and current noise is in very good agreement with theory. Thin-film resistors (TFR), such as TaN and SiCr, have metallic characteristics and exhibit 1/f noise levels that are four to six orders of magnitude lower than polysilicon [132]. The TFR flicker noise actually drops to the level of thermal noise and becomes more difficult to reliably measure.

10.3.4 1/f Noise in Bipolar Junction Transistors (BJT) Noise in bipolar transistors consists of shot noise, thermal noise, and flicker noise. The shot noise occurs mainly in the forward-biased emitter-base junction. The main part of thermal noise is associated with the base resistance. In a typical vertical BJT, the flicker noise is very low because nearly all the emitter current is located deep in silicon, away from the surface. Thus, the probability for injected emitter carriers to

Noise

Fig. 10.26 Integrated current noise in the range 10–1000 Hz for phosphorus-doped resistor versus the square of current showing very good agreement with theory [130]

525

0.8 Integrated Current Noise (pA)

10.3

N+-poly resistor, 1kΩ, L/W = 32/4 300 K

0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0

20

40 60 80 100 120 Square of resistor current, I2 (μm2)

140

tunnel into interface traps is extremely low. The flicker noise in a BJT is mainly due to residual traps within the emitter-base depletion region caused by, e.g., implant damage. The density of these traps can be significantly reduced by annealing. The flicker noise measured at the base of a BJT is proportional to the square of base current, IB, and inversely proportional to frequency and emitter area, AE. The PSD is approximated by [94, 133] SI B ffi

KF BJT I 2B 1 2 A =Hz AE f

ð10:50Þ

where KFBJT is a process parameter which can be extracted from measurements. The collector flicker noise PSD, SI C , is related to the base noise by the gain, β, as SI C ffi β2 SI B A2 =Hz

ð10:51Þ

Silicon NPN noise spectral densities SI B and SI C are shown in Fig. 10.27 [107]. For comparison, measured flicker noise on SiGe vertical NPN and PNP structures are shown in Fig. 10.28 [134, 135]. After scaling the emitter area and base current, the noise levels obtained on the SiGe structure are higher than for “pure” Si.

10.3.5 1/f Noise in Junction Field-Effect Transistors (JFET) The main advantage of JFETs over MOSFETs is the very low noise. As with a resistor, the low-frequency noise in a JFET channel consists mainly of 1/f and thermal noise. The shot noise in the gate-to-channel reverse-based junction can be neglected because the gate current is very low. The JFET noise has orders of magnitude lower than the resistor noise, and, in layouts that avoid silicon–oxide

526

10

10-23

10-20

10-25 10-26 10-27

100

NPN, AE = 1 x 1 μm2, β = 100, 300 K, IC=8 μA

SIC (A2/Hz)

10-24

SIB (A2/Hz)

10-19

NPN, AE = 1 x 1 μm2, β = 100, T=300 K, IB = 75 nA

Mismatch and Noise

10-21

White Noise

101

White Noise

10-22

1/f

103 102 Frequency, f (Hz)

104

10-23

100

101

1/f

102 103 Frequency, f (Hz)

(a)

104

(b)

Fig. 10.27 Frequency dependence of Si NPN flicker noise. (a) Base noise. (b) Collector noise [107]

10-20

VCE = 2.5V; AE = 0.4x0.8 μm2; β =120; IB = 0.5 μA; 300 K

10-21

SIB (A2/Hz)

Fig. 10.28 Frequency dependence of base flicker noise in silicon–germanium (SiGe) vertical NPN and PNP transistors [135, 136]

10-22

PNP

1/f

10-23

NPN 10-24 10-25 100

101

102

103

104

Frequency, f (Hz)

interfaces along the current path, the flicker noise becomes comparable to the thermal noise. The flicker noise is small compared to that of MOSFETs because the probability for carriers to tunnel from the buried JFET channel to surface traps is extremely low. Figure 10.29 shows the frequency dependence of the drain current and gate voltage flicker noise in an NJFET with W/L ffi 10/4 at a drain current of 28 μA.

10.4

Circuit Examples

Precision analog circuits are susceptible to errors caused by mismatch and noise. This section describes two simple examples showing the impact of mismatch and noise on circuit performance.

10.4

Circuit Examples

10-21 10-22 10-23 White Noise 10-24 10-25 100

10-11 10-12

W/L 10/4; ID = 28 μA; 300 K

SVG (V2/Hz)

SID (A2/Hz)

10-20

527

1/f

101 103 102 Frequency, f (Hz)

104

W/L 10/4; ID = 28 μA; 300 K

10-13 10-14 10-15 10-16

White Noise

10-17 10-18 100

1/f

101 103 102 Frequency, f (Hz)

(a)

104

(b)

Fig. 10.29 Frequency dependence of flicker noise in an NJFET. (a) Drain current. (b) Gate voltage [107] Fig. 10.30 Basic current mirror [137, 138]

VDD

R1

R2

D1

D2 G1

M1 S1

G2

M2 S2

10.4.1 Mismatch in Current Mirrors Consider the basic current mirror in Fig. 10.30 [137, 138]. Ideally, the drain currents should be matched with ID1 ¼ ID2. First-order process fluctuations can, however, cause the output current ID2 to be significantly different from the ID1. Assume initially that the load resistors R1 and R2 perfectly match and the variation in gate oxide thickness is negligible. The two transistors M1 and M2 operate in saturation and typically have a mismatch in threshold voltage, mobility, and W/L ratio. The saturation drain currents are given by (Chap. 6) I D1 ¼ Cox μ1 ðW eff =2Leff Þ1 ðV G  V T1 Þ2 A 2

I D2 ¼ Cox μ2 ðW eff =2Leff Þ2 ðV G  V T2 Þ A The average values are defined as

ð10:52aÞ ð10:52bÞ

528

10

Mismatch and Noise

V T ¼ ðV T1 þ V T2 Þ=2 V

ð10:53aÞ

I
D ¼ ðI D1 þ I D2 Þ=2 A

ð10:53bÞ

μ ¼ ðμ1 þ μ2 Þ=2 cm2 =Vs

W eff =Leff ¼ ðW eff =Leff Þ1 þ ðW eff =Leff Þ2 =2

ð10:53cÞ ð10:53dÞ

The mismatch quantities are defined as ΔV T ¼ V T1  V T2 V

ð10:54aÞ

ΔI D ¼ I D1  I D2 A

ð10:54bÞ

Δμ ¼ μ1  μ2 cm2 =Vs

ð10:54cÞ

ΔðW eff =Leff Þ ¼ ðW eff =Leff Þ1  ðW eff =Leff Þ2

ð10:54dÞ

Substituting the above quantities in (10.52a) and (10.52b) and neglecting secondorder terms give ΔI D ΔðW eff =Leff Þ Δμ 2ΔV T  % 
¼ þ I
D μ VG  V T W eff =Leff

ð10:55Þ

The current mismatch consists mainly of three components. The first term is geometry dependent and, for long and wide channels, contributes a small current mismatch which is independent of bias point (the set of desired current and voltage). As the channel length is reduced, a small difference in drain-to-source voltage or in channel length increases the mismatch in drain current due to channel-length modulation (Chap. 6). The second term in (10.55) is related to the mismatch in mobility caused mainly by the variation of surface charge and vertical and lateral fields. The third term describes the threshold voltage mismatch which is the most critical term to the overall accuracy of the current mirror. Ignoring variations in mobility and channel dimensions in (10.55) gives ΔI D 2ΔV T 2ΔV T ffi ¼ 
%
ID V Dsat VG  V T

ð10:56Þ

where V G  V T is the average gate overdrive and V Dsat V G  V T is the drain voltage in saturation. As the gate overdrive decreases, the difference in mirrored current increases due to the threshold voltage mismatch [138]. Thus, to reduce the effect of threshold voltage mismatch, a large gate overdrive voltage should be used.

10.4.2 Noise in Two-Stage Transconductance Amplifier In an operational transconductance amplifier, the output current is controlled by the differential input voltage. A schematic of a two-stage operational transconductance

10.4

Circuit Examples

Fig. 10.31 Schematic of a two-stage operational transconductance amplifier (OTA) [138]

529

VDD M8

M7

M6

M1

M2

-vin

+vin Rc

+iout

Cc

Ib

M5 M3

M4 VSS

amplifier is shown in Fig. 10.31. It is an important building block in analog circuits, such as active filters. The output current is a function of the applied voltages vþ in and v in on M1 and M2:
  iout ¼ gm vþ in  vin A

ð10:57Þ

where gm is the amplifier transconductance which is controlled by the biasing current Ib. The design of the amplifier starts by considering its noise requirements. Rc and Cc are the so-called compensation resistor and capacitor and not relevant for the discussion of noise. Only MOSFETs M1–M4 in the input stage signal path are important. The noise in each MOSFET consists of thermal and flicker noise. Since they are random and independent events, the average current noise is the sum of the M1–M4 average current noise: i20 ¼ i21 þ i22 þ i23 þ i24 A2

ð10:58Þ

i20 ¼ g2m1 v2n1 þ g2m2 v2n2 þ g2m3 v2n3 þ g2m4 v2n4 A2

ð10:59Þ

or

530

10

Mismatch and Noise

where i0 is the current noise at the output, gmi, and vni, respectively, the transconductance and voltage noise of MOSFET Mi (i ¼ 1–4). Assuming perfect symmetry and matching, (10.59) can be written in terms of M2 and M4 only i20 ¼ 2g2m2 v2n2 þ 2g2m4 v2n4 A2

ð10:60Þ

The input-referred amplifier noise voltage is given by v2ni

 i20 g2m4 2 2 ¼ 2 ¼ 2 vn2 þ 2 vn4 V2 gm2 gm2

ð10:61Þ

Focusing only on flicker noise, the MOSFET gate-referred noise spectral density is approximated as v2n ¼

KFΔ f 1 2 V 2 2μCox W eff Leff f

ð10:62Þ

Using a similar relation for the amplifier as (10.61) gives "  2 # KFΔ f 1 KF L n eff2 v2ni ¼ 1þ V2 KF p Leff4 μp C 2ox W eff2 Leff2 f

ð10:63Þ

The minimum noise is where ∂v2ni =∂Leff2 ¼ 0. This occurs when Leff2 ¼

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi KF p =KF n Leff4 μm

ð10:64Þ

A similar analysis can be done for thermal noise using the noise model given in [139].

Problems The temperature is 300 K unless otherwise stated. 1. An NMOS pair exhibits a standard deviation of threshold voltage mismatch, σ ΔV T , of 10 mV. Scattering of phosphorus during implantation causes the effective doping concentration in the channel of one NMOS to increase by 1010 cm2, while the other NMOS remains unaffected. Assume a long and wide channel and an equivalent oxide thickness of 12.5 nm and sketch the distribution of a large number of mismatch measurements. 2. The figure below shows two N-well resistors that are identically constructed in a P-substrate, except for a degenerately doped poly conductor crossing one of

Problems

531

the resistors. Assume a uniform N-well phosphorus concentration of 5  1016 cm3, a uniform P-substrate boron concentration of 5  1014 cm3, and disregard edge effects. Estimate the systematic mismatch between the two resistors (Fig. P2). 0V 5.0V

Poly

0V

5.1V

0V 5.0V

STI 0.4 mm P+

N+

P

N-well 0.9 mm

Metallurgical junction

5.1V STI 0.4 mm

N+

P+ P

P

P

N+

N-well 0.9 mm

Metallurgical junction

N+ P

P

Fig. P2 N-well resistor matching problem 5.2

3. Two identical MOSFETs are connected with first metal and operated in the linear mode. The metal line connecting the common source to ground is 50 μm long and 10 μm wide, and the metal lines connecting the MOSFET drains are 50 μm long and 20 μm wide on one MOSFET and 50 μm long and 0.25 μm wide on the other. Describe qualitatively how this design would affect mismatch. 4. Consider the array of polysilicon resistors of a uniform sheet resistance 250 Ω/□ in Fig. P4. The resistor-body length body is L ¼ 10 μm and its drawn width and space, respectively, W ¼ 0.5 μm and S ¼ 0.5 μm. The measured resistance is 6250 Ω at each end of the array and 5000 Ω at the array center. Assume the difference to be solely due to a linear gradient in over-etch, and (a) Find the etch-bias per resistor edge. (b) Plot the systematic mismatch as a function of distance between array center and array edge.

W = 0.5 mm

L = 10 mm

Fig. P4 Polysilicon resistor matching Problem 5.4

532

10

Mismatch and Noise

5. Calculate the shot noise in a diode current of 1.5 mA in a bandwidth of 1 MHz. 6. The power spectral density of the noise voltage is measured as 2.5  1016 V2/Hz for a bandwidth of 1 MHz. Find the root-mean-square of the noise voltage. 7. A polysilicon resistor has a resistance of 250 Ω. What is the PSD of the thermal noise voltage 300 K? 8. The resistor in Problem 5.6 shows a flicker noise PSD of 3.2  1019 A2/Hz. Find the root-mean-square of current noise in the bandwidth 10 Hz–1 kHz. 9. The flicker noise is measured on an NMOSFET as SI D ¼ 5  1017 A2/Hz at 100 Hz, VG  VT ¼ 2.5 V, and ID ¼ 5 mA. The channel length and width are, respectively, 0.6 and 10 μm. For an equivalent oxide thickness teq ¼ 12.5 nm, estimate the effective oxide trap density and the input-referred voltage noise.

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131. M. Da Rold, S. Van Huylenbroek, B. Knuts, E. Simoen, S. Decoutere, On the basic correlation between polysilicon resistor linearity, matching and 1/f noise. ESSDERC, 448–651 (1999) 132. H. Thibieroz, P. Shaner, Z.C.E. Butler, Mismatch and flicker Noise characterization of tantalum nitride thin film resistors for wireless applications. IEEE ICMTS Tech. Digest, 287–212 (2001) 133. G. Niu, Noise in SiGe HBT RF technology: Physics, modeling, and circuit implications. Proc. IEEE 93(9), 1583–1597 (2005) 134. J. Cressler (ed.), Integration of a complementary-SiGe BiCMOS process for high-speed Analog application, in Silicon Heterostructure Handbook, (CRC Press, Boca Raton, Florida, 2005) 135. B. El-Kareh, S. Balster, W. Leitz, P. Steinmann, H. Yasuda, M. Corsi, K. Dawoodi, C. Dirnecker, P. Foglietti, A. Haeusler, P. Menz, M. Ramin, T. Scharnagl, M. Schiekofer, M. Schober, U. Schulz, L. Swanson, D. Tatman, M. Waitschull, J.W. Weijtmans, C. Willis, A 5 V complementary-SiGe BiCMOS technology for high-speed precision analog circuits. IEEE Proc. BCTM, 211–214 (2003) 136. W.E. Zhao, A.K. Sutton, B.M. Haugerud, J.D. Cressler, P.W. Marshall, R.A. Reed, S.G. Balster, H. Yasuda, B. El-Kareh, The effect of radiation on 1/f noise in complementary (NPN + PNP) HBTs. IEEE Trans. Nucl. Sci 51(6), 3243–3249 (2004) 137. P.T. Gray, P.J. Hurst, S.H. Lewis, R.G. Meyer, Analysis and Design of Analog Integrated Circuits (Wiley, New York, NY, 2001), pp. 330–332 138. R.J. Baker, CMOS Circuit Design, Layout, and Simulations (Wiley/IEEE press, Piscataway, New Jersey, 2010), pp. 613–616 139. B. Wang, J.M. Hellums, C.G. Sodini, MOSFET thermal noise modeling for analog integrated circuits. IEEE JSSC 29(7), 833–835 (1994)

Chapter 11

Chip Reliability

Abstract This chapter focuses on component reliability. It begins with an overview of basic reliability concepts and models with emphasis on their applications to reliability engineering. An overview of important failure mechanisms of components and methods to reduce their impact on chip reliability is then presented. The sections include dielectric reliability, electro and stress migration, hot-carrier reliability, latch-up, bias-temperature instabilities, Joule heating and resistor reliability, highvoltage and high-power MOSFET reliability, plasma damage, and electrostatic discharge.

11.1

Introduction

A common definition of chip reliability is the probability that it will perform its required function under specific conditions for a specific period of time [1–3]. A chip consists of components which are interconnected with contacts and metal to form the desired circuit. The “required function” includes the definition of satisfactory and unsatisfactory component operation or a failure, which is typically checked with a set of electrical tests with respect to voltage, current, and time. It is important to anticipate failure modes in the early stages of technology development and include the appropriate set of reliability test structures on the test chip and insure that they are thoroughly tested as development lots are completed. Throughout the design and development stages of a process, trade-offs are sought among intricately conflicting requirements between component reliability and electrical performance. “The specific conditions” depend on use and environmental conditions, including contamination, voltage, current density, electric field, temperature, humidity, mechanical stress, vibration, and shock. The “specific length of time” is the duration of satisfactory operation expected by the customer, referred to as the lifetime. It depends on the application, but for many products, it is typically 10 years. All components will degrade with time and eventually fail to meet the required specification for proper operation. It is not possible to state for sure that a component or chip will perform satisfactorily. Instead, a probability of successful operation is measured or calculated. Since variability plays a key role in the probability of failure, © Springer Nature Switzerland AG 2020 B. El-Kareh, L. N. Hutter, Silicon Analog Components, https://doi.org/10.1007/978-3-030-15085-3_11

539

540

11 Chip Reliability

chip reliability is defined as a probability, implying that quantifying it must involve statistical methods. There is a strong correlation between failures observed at time zero, affecting yield, and failures that occur during stress, affecting reliability [4–7]. This chapter focuses on component reliability. It begins with an overview of basic reliability concepts and models with emphasis on applications in reliability engineering. Detailed analysis of probability and statistics is beyond the scope of this chapter. For additional information, the reader is referred to books on probability and statistical theory, such as in [8– 11]. The remaining sections present an overview of important failure mechanisms of components and methods to reduce their impact on chip reliability. The sections include dielectric reliability, electro and stress migration, hot-carrier reliability, latchup, bias-temperature instabilities, Joule heating and resistor reliability, high-voltage MOSFET reliability, plasma damage, and electrostatic discharge.

11.2

Definition of Terms and Basic Reliability Concepts

11.2.1 Population and Sample The entirety of identically manufactured devices is termed the device population. The population is typically very large, so that making a complete analysis of all devices and data is highly impractical. Thus, a smaller size and representative subset of the total population, called a sample, is randomly taken and statistically analyzed so that one can make inferences from the sample results back to the population from which the sample was taken. This process is called sampling.

11.2.2 Reliability and Failure Probability Functions The probability that a particular device will fail at time t + Δt, given that it was functional at time t, is the ratio of the number of failures in the sample during the interval Δt to the number of devices that were functional at time t [2, 3]. Let R(t) describe the ratio of number of devices that survive at time t to the starting number of devices at time t ¼ 0 (the fraction of devices that survive at time t). It is the probability that a component will operate satisfactorily at time t, referred to as the reliability function. Conversely, the failure probability function, F(t), is the sample fraction that fails between t ¼ 0 and t. It is the probability that a single, randomly selected new device will fail by time t. Thus, F ðt Þ ¼ 1  Rðt Þ

ð11:1Þ

R(t) describes the probability of success while F(t) describes the probability of failure.

11.2

Definition of Terms and Basic Reliability Concepts

541

11.2.3 Probability Density Function (pdf) The failure probability density function (pdf), or f(t), is the probability of devices failing within interval dt around t pdf ¼ f ðt Þ ¼ dF ðt Þ=dt

ð11:2Þ

11.2.4 Cumulative Distribution Function (CDF) The cumulative distribution function (CDF) is the same as F(t). It is the fraction of samples that fail between t ¼ 0 and t. It is defined as Zt f ðt Þdt

CDF ¼ F ðt Þ ¼

ð11:3Þ

0

Eventually, all devices fail and F(t) ¼ 1.

11.2.5 Failure Rate The failure rate, λ(t), is the probability that a device will fail per unit of time. Intuitively, a device that fails in a short time has a high failure rate. Thus, the time to fail is a good parameter to use defining the device failure rate. Let a representative sample of N devices be taken out of the entire population and subjected to normal use or stress at t ¼ 0. Devices will fail as a function of time. The failure rate, λi, of the ith device is λi ¼ 1=t i s1

ð11:4Þ

where ti is the time for the ith device to fail. The total fail time for N devices is the time tN at which the last device fails. It is defined as t Total ¼ t N s

ð11:5Þ

The mean time to fail (MTTF) is MTTF ¼ t Av ¼

N X ti i¼1

N

¼

1 s λAv

ð11:6Þ

where λAv is the average failure rate. The median time to fail (MTF) (or t50) is the time at which 50% of the samples fail. The fraction of devices that fail in a small interval Δt, starting at t, is F(t + Δt)  F(t). Thus, the probability, P, of failure in an interval Δt after surviving up to time t is

542

11 Chip Reliability

P¼

F ðt þ Δt Þ  F ðt Þ 1  F ðt Þ

ð11:7Þ

The average failure rate λ(t) during an interval Δt is the ratio of the number failing per unit time to the number surviving at time t. It is obtained by dividing (11.7) by Δt as λðt Þ ¼

1 F ðt þ Δt Þ  F ðt Þ Δt 1  F ðt Þ

ð11:8Þ

As t ! 0, (11.3) reduces to the instantaneous failure rate λðt Þ ¼

dF ðt Þ 1 f ðt Þ ¼ dt 1  F ðT Þ 1  F ðt Þ

ð11:9Þ

Thus, λ(t) is the ratio of the number failing per unit time at time t to the number surviving at time t. Example 11.1 For devices under stress, assume that the distribution of failure versus time can be described by a continuous function with a survival function R(t) expressed as Rðt Þ ¼ et

1:5

ð11:10Þ

where t is in hours. Plot R(t), F(t), f(t), and λ(t). Solution The CDF is CDF ¼ F ðt Þ ¼ 1  Rðt Þ ¼ 1  et

1:5

ð11:11Þ

The failure pdf is dF ðt Þ 1:5 ¼ 1:5t 0:5 et ð11:12Þ dt and the instantaneous failure rate is given by (11.9). The results are shown in Fig. 11.1a, b. pdf ¼ f ðt Þ ¼

R(t)

F(t) pdf = f(t)

R(t), F(t)

0.8 0.6 0.4 0.2

0

0

0.5

1.0

1.5 2.0 Time, t (h)

(a)

2.5

3.0

0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0

3.0

λ(t)

pdf

2.5 2.0 1.5

λ(t)

1.0

1.0

0.5 0

0.5

1.0

2.0 1.5 Time, t (h)

2.5

0 3.0

(b)

Fig. 11.1 (a) Plots of reliability function, R(t), and cumulative distribution function, CDF ¼ F(t). (b) Plots of the pdf and failure rate

Definition of Terms and Basic Reliability Concepts

Fig. 11.2 The three regions of a typical “bathtub” shape of failure rate: early failures, useful life, and wearout region

Failure rate (a.u.)

11.2

543

Total failure rate

Wearout of “good” devices

Failure of weak devices Nearly constant failure rate

Early failures

Useful life

Wearout

Time (a.u.)

11.2.6 The “Bathtub” Curve The failure rate typically changes with time during the expected device life. A useful conceptual model for the time-dependent failure rate is the “bathtub” curve, a frequently observed shape of failure rate of an entire population of products as a function of time (Fig. 11.2). It was initially applied to mechanical equipment but is also applicable to a wide range of samples, including semiconductor components. The curve can be roughly divided into three overlapping regions: (a) Early Failure Rate (EFR) During the early stages of operation, there is a high failure rate that is dominated by fails due to gross manufacturing defects, process errors, or design errors. The early failure rate (EFR) decreases rapidly as defective products are identified and discarded. For example, a partial pinhole in the gate oxide of a MOSFET can go undetected during routine parametric tests but can cause an early failure at voltage, current, or temperature stress levels far below the specified operating levels. The units must be stress-tested at an early stage of the product to detect defective products. Stress testing consists of subjecting the units to higher voltage, current, temperatures, or humidity levels than during normal operating conditions. This is done to “weed out” weak units that would otherwise cause products to fail in the field. This process is typically referred to as “burn-in.” Reducing failures in the field, typically reported as defective parts per million (DPPM), is a major focus in the industry. To mitigate some of the cost and time commitment of burn-in on packaged parts, short reliability screens, such as overvoltage stress testing (OVST) of weak oxides, can be added to the waferlevel product test [12]. (b) Intrinsic Failure Rate (IFR) The intrinsic failure rate (IFR) is a fairly constant failure rate that becomes dominant as the EFR decreases below a certain level. It is associated with random defects of different origins and hence occurs randomly throughout this phase and is sometimes referred to as the “useful life.” The transition between “early fails” and “useful life” is gradual since weak devices continue to fail during the “useful life,” however at a considerably lower rate.

544

11 Chip Reliability

(c) Wearout In the wearout region, the failure rate increases because devices begin to deteriorate more rapidly. The wearout is a process of attrition of devices that depends strongly on the level of stress, temperature, current density, voltage, or mechanical strain. Devices that survived the useful life are initially good but inevitably degrade with time because of depletion of material or accumulation of charge, resulting in a rapid increase in failure rate. The first component that fails in the wearout regime determines the product lifetime. Note that the mean time to failure and median time to failure apply only to the “useful life” region where the failure rate is nearly constant. Semiconductor circuits typically operate at voltages, currents, and temperatures below the levels which would bring the wearout region within its normal use lifetime. There are, however, applications where circuits operate well into the wearout region to improve performance, however, at the cost of lifetime.

11.2.7 Failure in Time (FIT) The allowable device failure rate for a complex system under use conditions is a very small number. Assume, for example, that a system contains 106 discrete transistors. If, for this system, a maximum of one device failure per month is allowable, then the devices must have an average failure rate of λ

1 failure=month ffi 1:4  109 Failures=Device  h 10 devices  720 h=month 6

The failure in time (FIT) is a more convenient unit of describing the failure rate, especially in high-reliability devices. It is the number of failures that can be expected in one billion (109) device-hours of operation. Thus, the maximum failure allowable rate of the above system is λ  1.4 FIT. To illustrate the calculation of failure rate from measured data, consider the results in Table 11.1 obtained on a sample of 500,000 discrete transistors which are subjected to voltage and thermal stress, beginning at time t ¼ 0. In the above table, the device-hours are found by dividing the number of devices that survive at the beginning of every interval by the total time they were subjected to stress. For example, at the fifth hour, the total number of device-hours is (500,000  74)  5  2.5  106 device-hours. The corresponding FIT value is (4/2.5  106)  109 FIT. From the data in Table 11.1, it can be seen that the FIT is typically a function of time. Table 11.1 Failure rate calculations (Sample size: 5  105) Stress time (h) 1 2 3 4 5

# failures 49 10 6 4 4

CDF 49 59 65 69 74

Failure rate (h1) 0.000098 0.000020 0.000012 0.000008 0.000010

Device-hours 5.0  105 1.0  106 1.5  106 2.0  106 2.5  106

FIT 98,000 10,000 4000 2000 1600

11.3

Reliability Models

Table 11.2 Time to fail for 1000 devices under use conditions

545 Failure rate (FIT) 1 10 100

Time for 1 failure (year) 114 11 1

11.2.8 Accelerated Testing, Acceleration Factor An important consideration is how to demonstrate that the devices actually conform to the specified failure rate. Table 11.2 shows the projected time for one failure in 1000 devices to occur under use conditions. To prove the specified failure rate, one must test a very large number of devices for lengths of time, which is unrealistic in terms of development schedule. The greater the device reliability, the more difficult it is to prove this reliability. Demonstrating adequate device reliability can be time-consuming and expensive. The cost of inadequate device reliability can, however, be even more expensive. Thus, there is a need to identify failure mechanisms and accelerate the failure rate by designing accelerated life tests in which devices operate at higher stress levels of temperature, voltage, current, temperature cycling, or humidity, than under use conditions. If the degradation mechanism is known and a model is established, it is possible to stress a small sample of a large population of devices under higher than normal conditions for short periods of time and then extrapolate the device reliability from the test results to use conditions. For this purpose, an acceleration factor (AF) is extracted. For instance, two voltage stress conditions can be applied and the AF extracted as the ratio of the observed median times to failure AF ¼ ½t 50 ðstress at V 1 Þ=½t 50 ðstress at V 2 Þ

ð11:13Þ

where V2 > V1. Once the AF is known, the lifetime under use conditions can be found by extrapolating to the normal operating voltage, Vop. A similar procedure is done for temperature, current, and other environments. For (11.13) to be valid, the failure mechanism must be the same for both stress conditions.

11.3

Reliability Models

There is a need to develop reliability models that fit failure distributions to known probability distributions, enabling the projection of failure rate from stress to use conditions, or to estimate the device lifetime given a goal of failure rate under use conditions. Modeling reliability is a multistep process which begins with determining the best fit of experimental time-to-failure data to alternative probability distributions. Once the model that best fits the data is determined, it can then be applied to predict failure rates as a function of time, i.e., lifetime distributions. A statistical distribution is fully described by its pdf, or f(t), from which other reliability functions can be derived, as discussed in the previous section. The most common distributions

546

11 Chip Reliability

are (a) exponential, (b) normal (Gaussian), (c) lognormal, (d) Weibull, and (e) power law. Each of the distributions can be applied to specific parts of the bathtub curve.

11.3.1 Exponential Distribution The exponential distribution is the simplest and most commonly used distribution. It is of the form pdf ¼ f ðt Þ ¼ λeλt

ð11:14Þ

It is characterized by a single parameter of the distribution, a constant failure rate λ. The exponential distribution is only applicable to the useful life phase, the nearly flat portion of the bathtub curve. The CDF and reliability function are Zt CDF ¼ F ðt Þ ¼

λeλy dy ¼ 1  eλt

ð11:15Þ

0

Rðt Þ ¼ 1  F ðt Þ ¼ eλt

ð11:16Þ

The failure rate is constant and defined as λðt Þ ¼

f ðt Þ λeλt ¼ λt ¼ λ e 1  F ðt Þ

ð11:17Þ

The MTTF is Z1 MTTF ¼

Z1 t f ðt Þdt ¼

0

t λeλt dt ¼

0

1 h λ

ð11:18Þ

The MTF, defined as the time for 50% of devices to fail, is t 50 ¼ ln 2=λ h

ð11:19Þ

11.3.2 Normal Distribution The normal distribution junction, also referred to as the Gaussian distribution,1 is a two-parameter continuous probability function which is widely used in statistical process control (SPC). Its pdf is [1–3] 1 Named after Carl Friedrich Gauss (1777–1855), German mathematician, physicist, and astronomer who developed this distribution when analyzing astronomical data.

11.3

Reliability Models

547

Frequency of observations f(x)

Mean, median 34.13%

f(μ )=

34.13%

13.59%

13.59%

2.14% 0.105% 0.030% -4s

-3s

-2s

1 σ 2p

2.14%

-1s

m

1s

2s

3s

0.105% 0.030% 4s

Measured variable, x

Fig. 11.3 The standard normal distribution curve 1 xμ 2 1 f ðxÞ ¼ pdf ¼ pffiffiffiffiffi e2ð σ Þ σ 2π

ð11:20Þ

where x is the random variable, such as breakdown field, noise, junction leakage, and threshold voltage. The function in (11.20) is completely specified by the two parameters, namely, the average of the observed values called the mean, μ, and the standard deviation, σ, which is a measure of the spread in data. The square of σ is called the variance. A plot of the normal distribution is shown in Fig. 11.3. It has a bell-shaped form that is symmetrical with respect to the mean. The median is the value that divides the observations in two halves. A normal distribution with p μ ffiffiffiffiffi ¼ 0 and p σ ffiffiffiffiffi ¼ 1 is referred to as the standard normal distribution with f ð0Þ ¼ 1=σ 2π ¼ 1= 2π ¼ 0:39894. In a standard normal distribution, the mean and median coincide. Examples of distributions for different values of μ and σ are shown in Fig. 11.4. One important theorem in statistics, which is given here without proof, states that if x is a random variable with mean μ and standard deviation σ, then replacing x with the variable z ¼ (x  μ)/σ, referred to as the standardized variable, yields a standard normal distribution with a mean ¼ 0 and a standard deviation ¼ 1 [2]. (a) Cumulative Distribution Function (CDF) The probability of occurrence within a specific region of the plot in Fig. 11.3 is the area under the curve between the boundaries of the region. For instance, the probability of occurrence in the region between 1σ and 2σ or +1σ and +2σ is 13.59%. Similarly, the probability of occurrence in the region between 4σ and infinity is 0.03%. The total area under the curve must be 1 (100%). This is illustrated for a standard normal distribution (μ ¼ 0, σ ¼ 1) in Fig. 11.5a for z ¼ x ¼ 1.5 and in Fig. 11.5b for z ¼ x ¼ 1.5. There are no closed form solutions for the integral of (11.20). Using the zfunction

548

11 Chip Reliability

Fig. 11.4 Normal distribution curves for different values of mean, μ, and standard deviation, σ

1.0

Frequency of observations f(x)

0.9 0.8

μ = -2, σ = 0.5

μ = 0, σ = 0.5

0.7 0.6 0.5 0.4

μ = 0, σ = 1.0

0.3 μ = 0, σ = 2.0 0.2 0.1 0 -5

-3

-4

-2

-1

0

1

2

3

4

5

Measured variable, x

0.40

0.40 0.35

0.35

μ= 0, σ = 1

0.25

0.20

f(x)

f(x)

0.25 93.32%

0.20

0.15

0.15

0.10

0.10

0.05

0.05

0 -4

μ= 0, σ = 1

0.30

0.30

6.68%

0 -3

-2

-1

0

1

2

3

4

-4

-3

-2

-1

0

x

x

(a)

(b)

1

2

3

4

Fig. 11.5 Shaded area for (a) x ¼ 1.5, CDF ¼ 0.5 + 0.433192  0.9332, or 93.32%. (b) x ¼ 1.5, CDF ¼ 0.5–0.433192  0.0668, or 6.68%

z ¼ ðx  μÞ=σ

ð11:21Þ

the integral is found numerically from [2, 3]   1 z ΦðzÞ ¼ CDF ¼ 0:5 þ erf pffiffiffi 2 2

ð11:22aÞ

  1 z ΦðzÞ ¼ CDF ¼ 0:5  erf pffiffiffi 2 2

ð11:22bÞ

Tables for the CDF of the standard normal distribution for which μ ¼ 0 and σ ¼ 1 (z ¼ x) can be found in several books on statistics [2, 8–11]. The CDF for the distribution functions in Fig. 11.4 is shown in Fig. 11.6. When the pdf is not symmetrical with respect to the mean, it is said to be skewed to the right (positively) or to the left (negatively). In this case, the mean and median will no longer coincide. The normal distribution is not appropriate for data that are highly skewed, as are most reliability failures in time.

Reliability Models

Cumulative Distribution Function, CDF

11.3

549

1.0 0.9

m = -2, s = 0.5

m = 0, s = 0.5

m = 0, s = 1.0

0.8

m = 0, s = 2.0

0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -5

-4

-3

-2

-1

0

1

2

3

4

5

Measured variable, x Fig. 11.6 Cumulative distribution functions of the normal distributions in Fig. 11.4

11.3.3 Lognormal Distribution The lognormal distribution is a flexible, two-parameter continuous distribution function that can empirically fit several types of failure data, such as electromigration (Sect. 11.4.2). It can represent any of the three “bathtub” regions. It is related to the normal distribution, except that the natural logarithm of the variable, rather than the variable itself, is normally distributed. Let t be the random variable. If t has a lognormal distribution, then the natural logarithm of t, ln(t), has a normal distribution as 1 ln tm 2 1 f ðln t Þ ¼ pffiffiffiffiffi e2ð s Þ s 2π

ð11:23Þ

where m is the mean of the logarithms of times to failure (not of times to fail) and s the standard deviation of the natural logarithms of times to failure. The standard deviation s is also referred to as the scale parameter. The parameters m and s should be distinguished from the mean, μ, and standard deviation, σ, of the actual measured times to failure. The lognormal pdf is [2, 3]   dðln t Þ 1  ¼ f ðln t Þ  pdf ¼ f ðt Þ ¼ f ðln t Þ dt  t 1 ln tm 2 1 pdf ¼ f ðt Þ ¼ pffiffiffiffiffi e2ð s Þ st 2π

ðFor x  0Þ

ð11:24aÞ ð11:24bÞ

550

11 Chip Reliability

pdf ¼ 0

ðFor x < 0Þ

The median of the lognormal distribution is given by t 50 ¼ em h

ð11:25Þ

Thus, (11.24b) can be written as 1 1 pdf ¼ f ðt Þ ¼ pffiffiffiffiffi e2 st 2π

ln tln t 2 50

ð11:26Þ

s

It can be shown that the MTTF and standard deviation of times to failure are given, respectively, by [2, 3] s2

MTTF ¼ emþ 2

ð11:27Þ

and 2

2

σ ¼ e2mþ2s  e2mþs h

ð11:28Þ

A good approximation for s is given in [13] as s  ln t50  ln t 16

ð11:29Þ

where t16 is the time at which 16% of the samples fail. Figure 11.7a illustrates examples of normal distribution of logarithms of times (in hours) to fail for a mean of ln(t) m ¼ 6.633 and two standard deviations of ln(t), s ¼ 1.0 and s ¼ 2.0. The distribution is symmetrical with respect to m. The corresponding pdf is shown in Fig. 11.7b. For m ¼ 6.633 and s ¼ 1.0, (11.27) and (11.28) give the mean of times to fail and standard distribution as 2.5

0.45 0.40

m = 6.633; s = 1.0

2.0

PDF (× 10-3)

0.35

f[ln(t)]

0.30 0.20

1.0

0.15 m = 6.633; s = 2.0

0.10 0.05 0 0

m = 6.633; s = 2.00

1.5

0.25

1

2

3

4

m = 6.633; s = 1.00

0.5

5

ln(t) (a)

6

7

8

9

10

0

0

200

400

600

800 1000 1200 1400 1600 1800 2000

Time, t (h) (b)

Fig. 11.7 (a) Normal distribution of logarithms of times to fail for different m and s. (b) Lognormal distribution of times to fail

11.3

Reliability Models

551

MTTF ¼ e6:633þð1 =2Þ  1252:6 h 2

and σ¼

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 2 e2x6:633þ2x1  e2x6:633þ1  1642 h

The CDF of the lognormal distribution is found from z-tables using the logarithms of times to fail instead of the times to fail. For instance, the probability that a component will last more than 3000 h is found by first calculating the z-value as z¼

ln ðt Þ  m ln ð3000Þ  6:633 ¼ ¼ 1:373 s 1

ð11:30Þ

From the z-table [2, 3], the CDF is F(1.373)  0.5 + 0.4147 ¼ 0.9147 and the reliability function as 1 – 0.9147 ¼ 0.0853. (a) Lognormal Plotting In reliability, it is frequently necessary to empirically find the best probability distribution that fits the data. In many cases, knowledge of the process that generated the data can be a guide to the decision. For instance, the lognormal distribution is known to fit data obtained from electromigration tests (Sect. 11.4.2). In other cases, it is necessary to examine the data by plotting the values on a probability graph and finding the distribution which gives the “best straight-line fit” to the data. Assume, for example, that six devices fail in sequence during stress after 1.4, 3.9, 7.5, 11.4, 15.8, and 26.2 h. Since the sample size is small, some empirical adjustments to the values of the CDF should be made. Instead of using i and n for the CDF of the ith data point (rank value) of the failure and n the sample size, the more common approximation for the CDF is given by Benard’s empirical approximation described in [14] as ri ¼ ði  0:3Þ=ðn þ 0:4Þ%

ð11:31Þ

where i is the failure order number in the sample size and ri is the “median rank.” The failure times are first arranged as shown in Table 11.3 and then plotted on lognormal paper as illustrated in Fig. 11.8. Table 11.3 Example of times to fail, order, and median rank Time to fail (h) 1.4 3.9 7.5 11.4 15.8 26.2

Order number 1 2 3 4 5 6

CDF (%) 16.67 39.33 50.00 66.67 83.33 100

Median rank (%) 10.94 26.56 42.10 57.81 73.44 89.06

552

11 Chip Reliability

F(t) ≡ CDF (%)

99

t50 ≈ 7.6 h t16 ≈ 2.9 h s ≈ ln (t50/t16) ≈ 0.96

50

10 5 1

t16

1

t50

10

100

Time to fail, t (h) Fig. 11.8 Lognormal fit of data using median-ranking values in Table 11.3. The extracted t16, t50, and slope s are shown on the right

11.3.4 Weibull Distribution The Weibull distribution is a continuous empirical probability distribution function named after Waloddi Weibull. It is widely applied to lifetime distributions in reliability engineering because of its versatility. It is particularly useful when analyzing semiconductor failure mechanisms where the failure of the whole component is dominated by the degradation rate of a localized region of the component. One example is time-dependent dielectric breakdown (TDDB, Sect. 11.4.1) where the entire capacitor fails when a localized “weak spot” degrades [15]. By adjusting its parameters, failure rates in any region of the bathtub curve can be modeled. In terms of time, the random variable t is said to have a Weibull distribution with two parameters β > 0 and η > 0 if the instantaneous failure rate λ(t) varies with time as   β1 β t ð11:32Þ λðt Þ ¼ η η The pdf of the Weibull distribution is derived from (11.32) as [2] f ðt Þ ¼

  β1 β β t eðt=ηÞ η η

ð11:33Þ

where β is the shape parameter and η is the scale parameter. When β ¼ 1, the pdf reduces to the exponential distribution with λ ¼ 1/η. Thus, the exponential distribution is a special case of the Weibull distribution.

11.3

b =3, h =1

553

b =2, h =1

1.2

b =3.5, h =2

5

1.0

4

0.8

b =1.5, h =1

f(t), pdf

(t)

6

Reliability Models

3 2

b =1, h =1

1

b = 0.5, h = 1 b = 1, h = 1 b = 2, h = 1

0.6

b = 3.5, h = 2

0.4 b = 2, h = 5 0.2

b =0.5, h =1

0

0 0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0

1

2

3

Time t (a.u.) (a)

4

5

6

7

8

9

10

Time t (a.u.) (b)

Fig. 11.9 (a) Weibull failure rate functions for different values of β, η. (b) Corresponding pdf functions

Figure 11.9a shows failure rate functions for different values of β and η. The first part of the bathtub curve with a decreasing failure rate is modeled with β < 1. The wearout region with an increasing failure rate is modeled with β > 1. For β ¼ 1, the failure rate is constant, as expected from the exponential distribution. When β ¼ 3.5, the Weibull distribution approximates the normal distribution. There is a linear relation between λ(t) and t for β ¼ 2. Corresponding Weibull pdf functions are shown in Fig. 11.9b. Integrating (11.33) gives an analytical expression for the Weibull CDF, as β

F ðt Þ ¼ CDF ¼ 1  eðt=ηÞ

ð11:34Þ

The scale parameter η is also referred to as the characteristic life, since for t ¼ η, the CDF is about 63.2% regardless of the value of β. The reliability function is β

Rðt Þ ¼ 1  F ðt Þ ¼ eðt=ηÞ

ð11:35Þ

By setting F(t) ¼ 0.5 in (11.34), the MTF, t50, is t 50 ¼ ηðln 2Þ1=β h

ð11:36Þ

The Weibull mean time to failure (MTTF) and standard deviation require rather complex gamma functions and are seldom used in semiconductor reliability analysis [3]. (b) Weibull Plotting A linearized form of the Weibull distribution function is obtained by rearranging (11.34) and taking double logarithms as

  ln 1= 1  F ðt Þ ¼ β ln ðt=t63 Þ

ð11:37Þ

which gives a straight line of the form y ¼ ax + b on commercially available Weibull plotting paper. The slope β can be extracted from (11.37). Any value of F and its

554

11 Chip Reliability

Fig. 11.10 Weibull plotting of failure data in Table 11.4

CDF (% fail)

99

90 80 70 60 50 40 30

t 50 ≈ 1735h ln[– ln(10 – 1) β= ≈ 2.4 ln(t 10 /t 63 )

63.2%

20 10

1 102

t10 103

t63

104

Time, t (h)

Table 11.4 Failure data obtained from 132 stressed devices Time (h) 500 1000 1500 2000 a

Order number 1 2 3 4

Cum. failures 3 30 67 96

Cum. fraction (%) 2.27 22.73 50.76 72.73

Adjusteda cum. fraction (%) 2.05 22.57 50.58 72.72

Adjusted Cum. Fraction ¼ (Cum. Failures – 0.3)/(Sample Size – 0.4)

corresponding failure time can be used to extract the slope. A typical combination is F ¼ 0.1 and t10. An example of Weibull plotting is shown in Fig. 11.10 for the cumulative timeto-fail data in Table 11.4 [15]. The data are first adjusted by Bénard’s medianranking procedure given by (11.31) and then plotted as shown in the figure. The slope of the best-fit straight line gives β. The characteristic time to failure, η, is extracted from the intercept of the horizontal F(t) ¼ 63.2% line with the best-fitted straight line. The lognormal and Weibull distributions are the two most common distributions used to fit lifetime models to failure data. From Figs. 11.8 and 11.10, it can be seen that the lognormal and Weibull pdf plots are very similar. In fact, there are many instances where either model can fit reliability data. The choice between the two models for a given sample of reliability data depends on how accurately failures can be predicted by extrapolating the fitted line to beyond the experimental data [3, 15].

11.3.5 Power Law Model The degradation of several parameters in semiconductors, such as threshold voltage and drain current shifts due to hot-carrier injection (Sect. 11.4.3) and biastemperature instabilities (Sect. 11.4.4), follows a power law of the form

11.3

Reliability Models

555

P ¼ P0 ½1 At n 

ð11:38Þ

where P is the parameter, P0 is the value of P at time t ¼ 0, A is a material/devicedependent coefficient, and n is the power law exponent [15]. An increase or a decrease of a parameter with time reflects degradation of that parameter. For example, the threshold voltage of a PMOSFET under negative bias-temperature stress increases, while the drain current decreases with time (Sect. 11.4.4). When the change in the parameter reaches a predefined criterion, the device is said to have failed. Example 11.2 The threshold voltage, VT, of a PMOSFET degrades with time t as shown in Table 11.5. (a) Find the power law exponent n which best describes the degradation of VT. (b) Find the complete power law equation which describes the shift in VT. (c) Estimate the value VT after 100-h stress. Solution The threshold voltage increases with time as V T ¼ V T0 ½1 þ At n  V

ð11:39Þ

Rearranging, one obtains ðV T  V T0 Þ=V T0 ¼ At n

ð11:40Þ

Let D ¼ (VT  VT0)/VT0. Taking the logarithm of both sides of (11.40) gives ln ½ðV T  V T0 Þ=V T0  ¼ ln ðDÞ ¼ n ln ðt Þ þ ln ðAÞ

ð11:41Þ

The values of D ¼ (VT  VT0)/VT0, ln(t), and ln(D) are shown in the last three columns of Table 11.5. A plot of ln(D) ¼ ln [(VT  VT0)/VT0] versus ln(t) is shown together with the extracted values in Fig. 11.11. Table 11.5 PMOSFET VT under NBTI stress [15] Time, t (h) 0 1 2 10

VT (V) 0.710 0.732 0.737 0.750

D 0.000 0.031 0.038 0.056

ln(t)

ln(D)

0 0.696 2.303

3.47 3.26 2.88

556

11 Chip Reliability

0.0

ln (VT –VT0)/VT0

-0.5

-1.0 -1.5

y=0.257x - 3.463 n = 0.257 A = e-3.463 ≈ 0.03 h-0.257

-2.0 -2.5 -3.0 -3.5 -4.0 0.0

0.5

1.0

1.5

2.0

2.5

ln(t) Fig. 11.11 Example 11.2 plot of ln[(VT  VT0)/VT0] versus ln(t) in Table 11.5

(a) It can be seen from the plot that the power exponent n ¼ 0.257 (b) Using (11.39), the threshold voltage shift is given by  V T ¼ 0:710 1 þ 0:03  t 0:257 V

ð11:42Þ

(c) The value of VT after 100 h stress is expected to be 0.780 V.

11.4

Failure Mechanisms

Wafer-level reliability testing (WLR) is a process where a high stress is applied to specially designed test structures on the wafer to measure degradations, determine acceleration factors, and identify failure mechanisms. WLR allows the separation of failure mechanisms with appropriate test structures. Compared to costly “traditional” long-term stress testing that takes hundreds or thousands of hours to produce results, WLR testing provides rapid feedback for debugging and optimizing reliability, thus reducing the process development cycle. WLR is applicable to most analog components and their parameters. This section addresses important failure mechanisms, accelerated stress testing, and models for lifetime projections from stress to use conditions. The reliability physics must be the same for stress and use conditions to allow projections to be done.

11.4.1 Dielectric Reliability Dielectrics of different compositions are grown or deposited on a chip for several purposes. The gate insulator can be thermal oxide, CVD oxide, nitrided oxide, or a high-κ dielectric, where κ is the dielectric constant. For inter- and intra-level insulators, TEOS oxide or low-κ dielectrics, such as fluorinated silicate glass (FSG) and SiOC-base dielectrics, are deposited.

11.4

Failure Mechanisms

557

The reliability of a dielectric is its ability to retain its insulating properties while subjected to a high field and high temperature for a specific duration. A high-quality thin oxide is typically grown to serve as the gate dielectric since its properties affect nearly all MOSFET key parameters. Other special dielectrics are deposited to form capacitor insulators which, depending on application, require high-quality dielectrics to ensure the stability of precision capacitance, low trap density, and low leakage. Finally, dielectrics to form the STI and/or deep-trench isolation (DTI) are deposited and planarized to isolate components from each other (Chap. 9). In all cases, there are stringent requirements on the stability of the dielectrics in terms of leakage, breakdown, and surface traps and charge. (a) Gate Dielectric The most common gate dielectric in analog technologies is “pure” thermal oxide without nitrogen incorporation. Carrier Transport Through Oxide The oxide reliability is directly related to the injection of electrons and holes into the oxide. Figure 11.12 shows the thermal equilibrium band diagram of an MOS structure with N+-poly gate and P-type substrate. Band bending is caused by the work function difference between N+-poly gate and silicon (Chap. 6). The siliconoxide barrier is about 3.2 eV for electrons and 4.6 eV for holes, which are too large for thermal emission from the silicon or polysilicon into the oxide at room temperature. Thus, assuming an ideal oxide void of charge, traps, and defects, for carriers to transit the oxide from silicon, they must be either excited over the barrier by a highfield avalanche, or tunnel through the energy barrier. Tunneling is a quantummechanical effect that predicts an increasing probability for carriers to penetrate the oxide as the effective oxide thickness is reduced below approximately 3 nm. For an oxide thickness below approximately 1 nm, the oxide film becomes practically transparent to carriers. Avalanche injection occurs when the field in the silicon is increased to a “critical” value where a large number of hot carriers gain sufficient energy to be injected over the barrier into the oxide (Sect. 11.4.3). Fig. 11.12 Band diagram for N+-poly, oxide, and P-type silicon (not to scale)

3.2 eV 3.2 eV

EC Ei EV

EF ≈ EC

4.6 eV

N--poly

SiO2

P-type Si

558

11 Chip Reliability

Fig. 11.13 (a) FN tunneling through the triangular barrier, applicable to carrier at Ec and above. (b) Direct tunneling through ultrathin oxide

P-type Si

Oxide Poly gate EC

VG > 3.2V

P-type Si

Oxide Poly gate

VG < 3.2V

EV EC EV EC EV

N--poly N--poly

SiO2

SiO2 P-type Si

P-type Si

(a)

(b)

For tunneling to occur, the field in the oxide must be larger than about 107 V/cm. Depending on oxide thickness, tunneling can occur directly through the oxide or by a mechanism known as Fowler–Nordheim (FN) tunneling. Both tunneling mechanisms can occur simultaneously, but for an ultrathin (< 3 nm) oxide, direct tunneling dominates. The band diagram is shown for both tunneling mechanisms in Fig. 11.13a, b. Fowler–Nordheim Tunneling The situation in Fig. 11.13a is that the oxide is too thick for appreciable direct tunneling to occur but sufficiently thin that band bending creates a triangular barrier that reduces the tunneling distance. In its simplified form, the relation for FN tunneling is [16–19] jFN ¼ AE2ox eB=Eox A=cm2

ð11:43Þ

where A and B are constants defined as q3 1:54  106  A=V2 8πhϕox ϕox qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 8π 2m ϕ3ox 3=2  4:823  107 ϕox B¼ V=cm 3qh A¼

ð11:44Þ

ð11:45Þ

In the above equations, h is Planck’s constant, ϕox is the barrier height at the silicon- or polysilicon- oxide interface in eV, and m* is the carrier effective mass. Without consideration of barrier lowering and quantum effects at the silicon surface, the barrier height ϕox is 3.2 eV for electrons and 4.6 eV for holes [17] (Fig. 11.12). The effective electron mass in the oxide is assumed to be m*  0.4 m0, where m0 is the free electron mass [18]. For electrons, this gives A  4.81  107 A/V2 and B  2.78  108 V/cm. With these values (11.43) reduces to jFN ¼ 4:81  103 E2ox e2:7810

8

=Eox

pA=μm2

ð11:46Þ

11.4

Failure Mechanisms

559

Direct Tunneling Using the same constants A and B defined in (11.44) and (11.45), the relation for direct tunneling is [19] jDirect ¼ AE2ox eB



=Eox

ð11:47Þ

A=cm2

where "



qV B ¼ B  1  1  ox ϕox

1:5 # ð11:48Þ

V=cm

The gate current is jG ¼ jFN + jDirect. Figure 11.14 shows the calculated direct and FN currents as a function of field in the oxide ranging from tox ¼ 2 nm to tox ¼ 6 nm. The values obtained from (11.43) and (11.47) are in good agreement with the reported results in [18]. Accelerated Stress Tests When a voltage is applied across an oxide, tunneling current is measured if the oxide is sufficiently thin or the gate voltage is sufficiently high. For thick gate oxides subjected to an electric field above approximately 8 MV/cm, the current is controlled by FN tunneling through the triangular barrier discussed in the previous section. For oxides thinner than about 3 nm and a gate voltage lower than 3.2 V (the barrier for electrons), the current is dominated by direct tunneling. Accelerated stress is achieved by applying a higher voltage to the structure and by subjecting the structure to a higher temperature than under normal use conditions. The applied voltage is chosen to increase the field and hence the tunneling current density through the oxide according to (11.43) and (11.47).

Fig. 11.14 Calculated direct tunneling and Fowler–Nordheim (FN) tunneling as a function of gate voltage in the range tox ¼ 2–6 nm

Tunneling current density (A/cm2)

Stress-Induced Leakage Current (SILC) Ideally, thermal SiO2 should not conduct appreciable current until the voltage reaches a point where the electric field has a value above approximately 8 MV/cm. Real oxides, however, contain thickness nonuniformities and a certain 1004 1002 10-00 10-02

Direct FN

tox = 2 nm 2.5 3 3.5

4

10-04

6

10-06

10-08 10-10 10-12

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Voltage across oxide, Vox (V)

Current density (A/cm2)

560

11 Chip Reliability

100

tox = 5 nm; 300 K EStress: 12 MV/cm

Hard breakdown

10-1 10-2

SILC

10-3

Stress Soft breakdown steps

10-4 10-5

Initial

10-6 0

2

4

6

8

10

12

Post Stress Field (MV/cm) Fig. 11.15 SILC characteristics of 5-nm thermal oxide following FN stress at 12 MV/cm in steps of 5 s. Also illustrated are the soft and hard breakdown regions. (Adapted from [23])

amount of traps which can be neutral, positively charged, or negatively charged and hence conduct current at a lower field than the ideal value. The charge in a trap can change by capturing nearby free positive or negative charges. These free charges can be present due to current through the dielectric, radiation-induced electron-hole pairs (EHP), or impact ionization when an individual free carrier gains sufficient energy from a high electric field in the dielectric to create an EHP. The charge in a trap can also change due to thermionic excitation at high electric field (without the need for a nearby free carrier). Under high electric field operation, a number of processes occur at the same time: electric current is induced in the dielectric, impact ionization generates EHP, trapping centers trap electrons or holes, and charge trapped in a center is liberated by tunneling and field-assisted thermionic emission. As traps charge or discharge, the electric field changes, causing changes in the injected current and amount of impact ionization. Direct or Fowler–Nordheim tunneling can cause several defects within a thin oxide. Among these defects are neutral electron traps which can act as stepping stones that effectively shorten the tunnel distance and hence assist tunneling [20]. This stress-induced leakage current (SILC) is observed as a gradual increase in current through ultrathin (< 3 nm) thermal oxide [21]. Figure 11.15 illustrates the increase in SILC after multiple field stresses in the FN injection regime [22–25]. Also shown is the region of soft breakdown which is believed to progress gradually under stress into hard breakdown, which is typically destructive [23–25]. Several different models for the SILC mechanism have been suggested, most of which are based on a trap-assisted tunneling mechanism [23–28]. While SILC mainly affects the retention time and endurance of nonvolatile memories (NVM), it can also have an impact on analog circuits that operate at very low currents in the weak inversion or subthreshold regime [29]. Ramped-Voltage and Time-Dependent Dielectric Breakdown Traditionally, dielectric breakdown has been defined as a sudden irreversible increase in current or a sudden drop in voltage. In the ramped voltage test, the

11.4

Failure Mechanisms

561

Single ramp voltage sweep 1

V(t) = RR ¥ t RR: Ramp rate

Area: 1.92 × 10-3 cm2 Ramp rate: 0.5V/s tox 5 nm; 300K

0

ln[-ln(1-F)]

Voltage, V

Breakdown Voltage, VBD

-1

Intrinsic fails

Extrinsic fails

-2 -3

Time

-4

tBD

0

(a)

2

4

6

Breakdown Voltage (V) (b)

8

10

Fig. 11.16 (a) Ramped voltage stress. (b) Weibull plot of stress results

voltage is linearly increased until the dielectric breaks down (Fig. 11.16a). A Weibull plot of intrinsic and extrinsic (defect-related) breakdown distribution is shown in Fig. 11.16b for illustration. In the extrinsic regime, the probability for a breakdown to occur below a given voltage (or field) obeys a Poisson relationship to the area of the device being tested. All dielectrics will break down when the voltage across the dielectric is increased above a critical value which depends on film thickness and material. During ramping, the voltage increases linearly with time until breakdown occurs. At that point, the field reaches a value EBD  VBD/ti where ti is the insulator thickness. For a constant voltage ramp rate (RR), the time to breakdown is tBD  VBD/RR [15]. Ramped voltage to breakdown is a rapid test that allows collection of a large volume of data and provides fast feedback on oxide quality and defect density [30]. This technique, referred to as the gate-oxide integrity (GOI) test, is frequently used to evaluate the manufacturing quality of the gate oxide. For statistical analysis, however, the GOI test data contain only the “hard” breakdown. While this test is fast, it obscures details on oxide characteristics, such as gradual increase in leakage and its dependence on stress time [31]. TDDB is a breakdown that occurs with time when the dielectric is subjected to a constant voltage (or current) above the operating voltage at a given temperature. The constant voltage is applied, creating a sufficiently high stress field to induce a tunneling current in the dielectric, typically 0.1–0.2 mA/μm2. The time to breakdown is measured and recorded for each failed unit. The stress field is sufficiently high to produce a measurable current. The charge to breakdown, QBD, is sometimes used to evaluate the dielectric reliability. It is defined as ZtBD QBD ¼

jðt Þdt C=cm2 0

ð11:49Þ

562

11 Chip Reliability

Fig. 11.17 Schematic percolation path shown for four traps [32, 36]

Anode interface

x1 Trap

x2

tox

xi < xperc xperc: Percolation distance

x3 x4 x5 Cathode interface

where tBD is the time to breakdown. An ensemble of devices tested under the same stress (voltage or current) will fail at different times, resulting in a statistical distribution of QBD and TDDB values which depend on the local dielectric temperature, defects, insulator thinning, impurities, process-induced damage, and mechanical stress. A Weibull plot is obtained for the times to failure from which the characteristic parameters and the projected lifetime are extracted. Intrinsic Failure Mechanism Electrons and holes traveling through the oxide at high energy generate traps by several complex mechanisms, such as impact ionization and hole-related trap generation which are not detailed here. The widely accepted model for the breakdown of ultrathin (< 3 nm) silicon oxides or oxynitrides is related to the trap density which increases randomly with high field stress [32–36]. The random trap generation is described by a “percolation” model as illustrated in Fig. 11.17 [31, 35]. The trap concentration increases up to a critical value corresponding to the onset of one percolation path joining the gate (in this case anode) and bulk (cathode) across the oxide. As the distance between traps decreases, the direct trap-to-trap tunneling probability increases, initially resulting in a stress-induced low-level leakage current (SILC). When a contiguous path of closely arranged traps is created within a localized region of the oxide, the probability for carriers to travel from one electrode to the other increases, forming a conductive filament where the current density and hence Joule heating increases. Local increase in temperature raises the current density in the filament, a regenerative feedback which results in a catastrophic failure. This is believed to be due to an intrinsic effect in the oxide, not due to preexisting, extrinsic defects or processing errors. TDDB Models Several models have been suggested to describe the oxide time to failure. Among these are the exponential E-model [37, 38], the exponential 1/E Model [39–42], and pffiffiffiffi the exponential E model [15]. The exponential E-model assumes that the applied electric field interacts with weak Si–Si bonds associated with oxygen vacancies in the oxide. In the exponential 1/E model, also known as the anode hole injection model, injected electrons from the cathode gain high electric energy as they travel through the oxide conduction band and, when they reach the anode, they lose part of

11.4

Failure Mechanisms

563

Fig. 11.18 Weibull distribution of gate oxide breakdown at three different stress fields for an NMOSFET (Adapted from [15])

3

teq = 13.2 nm; T = 398 K b ≈ extracted as 3.0

2

11.81 MV/cm 11.28 10.75

ln[-ln(1-F)]

1

63.2 %

0

-1

-2

-3

-4 1

10

100

Stress time (s)

1000

their energy as they fall into the conduction band of the anode. In this process, hot holes can be generated which tunnel back into the oxide, creating traps in the oxide. A high density of traps in the oxide triggers the breakdown mechanism as discussed earlier. Both E and 1/E models have received widespread acceptance. The exponential E-model is simplified as t Fail ¼ A0 eγE eEa =kT s

ð11:50aÞ

where A0 is a process- and device-dependent constant, E is the electric field, Ea is the activation energy, k is the Boltzmann constant, T is the absolute temperature, and γ is the field acceleration factor, AF, given by Ea 1 1 AF ¼ eγðV stress V use Þ=tox e k ðT use T tress Þ

ð11:50bÞ

The time to fail decreases exponentially with increasing electric field and temperature. The 1/E dependence of time to fail is based on FN tunneling (11.43). An example of a Weibull plot is shown for a 13.2-nm gate oxide in Fig. 11.18. The value of ln[ln(1  F)] is plotted versus stress time at 398 K for three different acceleration fields, where F is the cumulative failure in %. The slope β is extracted directly from the plot using (11.37). The times to failure in Fig. 11.18 are conveniently taken at F ¼ 63.2% and plotted as a function of electric field for a constant temperature as shown in Fig. 11.19a. The field acceleration factor γ in (11.50a and 11.50b) is extracted from the plot as indicated in the inset. The activation energy is extracted from (11.50a and 11.50b), by plotting the time to failure versus 1/kT for a constant stress voltage (Fig. 11.19b). Extracting the three parameters, β, γ, and Ea, provides a

564

11 Chip Reliability

104

104 γ=

ln(t 1 ) − ln(t 2 ) = 2.6 E 2 − E1

Ea =

t1 , E1 103

t2 , E2 102

101 10.0

10.5

11.0

11.5

Time to fail at F = 63.2% (s)

Time to fail at F = 63.2% (s)

T = 398 K

t2 , T2 103

t1 , T1 102

101 24

12.0

ln(t 1 ) − ln(t 2 ) ≈ 0.41 eV 1 1 − kT1 kT2

Electric Field (MV/cm)

26

28

30

32

34

36

1/kT (eV-1) (b)

(a)

Fig. 11.19 (a) Extraction of the field acceleration factor, γ, from Fig. 11.18. (b) Extraction of the activation energy, Ea

106 200 oC Time to fail at F = 63.2% (s)

Fig. 11.20 Plot of time to failure versus 1/Eox at three different temperatures [42]

106

160 oC

105

240 oC

104 103 102 101 100 0.07

0.08

0.09

0.10 0.11 1/Eox (cm/MV)

0.12

0.13

good approximation of lifetime projections for different stress voltages, temperatures, CDF targets other than 63.2%, and duty cycles.2 A similar analysis is done on a 7.2-nm gate oxide at 160, 200, and 240  C and stress fields ranging from 9.7 to 12.5 MV/cm [42]. In this analysis, the times to failures are plotted versus 1/Eox as shown in Fig. 11.20. The results show an excellent agreement with the 1/E anode hole injection model.

2

The duty cycle is the fraction of time that a stress voltage, VStress, is applied. For cycle period T and duration of VStress τ, the duty cycle is τ/T.

11.4

Failure Mechanisms

565

(b) Capacitor Dielectrics Reliability studies on capacitor dielectrics follow a similar methodology as for the gate dielectrics. Dielectrics used in metal–insulator–metal (MIM) capacitors are typically deposited rather than thermally grown due to the low thermal budget allowed in the BEOL (Chaps. 8 and 9). Thus, their breakdown voltages are expected to be lower than thermal oxide used in MOS capacitors. Among the deposited dielectrics are low-pressure chemical-vapor-deposited oxide (LPCVD oxide), plasma-enhanced CVD (PECVD) nitride (or simply PEN), and high-κ and low-κ dielectrics which also constitute the lateral flux capacitor dielectric (Chap. 8). LPCVD Oxide To achieve the required low-leakage, low trap density, and comparable TDDB characteristics to thermal oxide, low-pressure CVD oxides must be annealed (densified) at high temperatures (~1000  C) [43]. This limits their use to capacitors formed prior to metallization because of the incompatibility of the process with aluminum or copper BEOL. PECVD Nitride Plasma-enhanced CVD silicon nitride, PEN, has emerged as an attractive MIM capacitor dielectric because of its high dielectric constant, low deposition temperature, and ease of integration [44]. Silicon nitride exhibits, however, considerably higher leakage current and trap densities than oxide. The high trap density causes an increase in leakage, reducing the breakdown field. It also causes a shift in capacitance with frequency, known as dispersion [45], and an increase in dielectric absorption, which can be detrimental to analog applications (Chap. 8). One method to reduce leakage and dispersion is to replace silicon nitride with a stack of oxide– nitride–oxide (ONO) films [46]. Unlike oxide films that conduct by direct or FN tunneling, conduction in thin silicon nitride films that are subjected to a field larger than about 106 V/cm is dominated by the Poole–Frenkel mechanism, which is a field-aided trap-to-trap “hopping” mechanism [47, 48]. The field lowers the local trap barrier height, allowing the carriers to be thermally emitted from the traps. The carriers subsequently travel a certain distance and are then retrapped. This is an important factor since the increase in current density reduces the time to breakdown. The current density increases with electric field and temperature as [48] jPF ¼ σ PF E N eðϕT β

pffiffiffiffiffi E N Þ=kT

A=cm2

ð11:51Þ

where σ PF is the Poole–Frenkel conductivity, ϕT is the trap energy level, and β is the Poole–Frenkel emission coefficient given by β¼

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi q=ðπε0 εN Þ ðV-cmÞ1=2

ð11:52Þ

where εN is the nitride dielectric constant. For εN  7, the coefficient is β  2.8  104 cm1/2 V1/2. Based on (11.51), the TDDB silicon nitride is best

566

11 Chip Reliability 2.0 1.5

T: 398 K Area: 2×104 mm2

1400

1.0

E = 7.4 MV/cm

7.1

6.8

0.5 F=63.2 %

Time to Fail (s)

ln[-ln(1-F)]

0.0

T: 398 K Area: 2×104 mm2

1200

-0.5

-1.0 -1.5 -2.0 -2.5

1000 800 600 400

-3.0 200

-3.5 -4.0 100

0

101

102

Stress time (s) (a)

103

104

2.60 2.62 2.64 2.66 2.68 2.70 2.72 2.74

E ×103 (V/cm)1/2 (b)

Fig. 11.21 (a) Weibull distribution of breakdown at three different stress fields for MIM with PEN insulator. (b) Field acceleration

pffiffiffiffi modeled by the exponential E model [15, 49]. A Weibull plot of times to failure is shown in Fig. 11.21a for PECVD nitride. Plotting the times to failure (taken at pffiffiffiffi F ¼ 63.2%) as a function of E yields a straight line from which the lifetime can be projected (Fig. 11.21b). High-κ Dielectrics Hafnium oxide, HfO2 (κ ¼ ε ¼ 21), is a high-κ material commonly used as the dielectric for planar MIM capacitors with high capacitance density. An analysis of current transport and breakdown distribution in HfO2 is given in [50], confirming that trap-assisted tunneling along grain boundaries is the dominant charge transport mechanism in the dielectric. A Weibull distribution plot of breakdown is shown for a 7-nm TiN/HfO2/TiN MIM capacitor in Fig. 11.22. As in the case of nitride, the structure exhibits a high density of traps, which is detrimental to analog applications where low dispersion, leakage, and dielectric absorption are required. Low-κ Dielectrics The integration of lateral MIM (lateral flux) capacitors into existing CMOS BEOL technologies without added complexity is discussed in Chaps. 8 and 9. While with deposited SiO2 the reliability was not a serious concern, long-term reliability of inter-level dielectric (ILD) and inter-metal dielectric (IMD) became a critical issue with the introduction of low-κ materials as the ILD and IMD in the 90-nm technology and beyond [51–60]. This is because low-κ dielectrics typically have a considerably higher leakage and lower breakdown field than deposited SiO2 [51]. A TDDB comparison of dielectrics is shown in Fig. 11.23. The time to failure is given in arbitrary units (a.u). If the time to fail were in seconds, the dotted line would represent 10 years.

Failure Mechanisms

Fig. 11.22 Weibull plot of TDDB distributions on a 7-nm TiN/HfO2/TiN dielectric subjected to a 3.3 V constant voltage stress at different temperatures [50 and references therein]

567 1.5 1.0

Area: 10-5 cm2 E: 4.7 MV/cm

0.5

ln[-ln(1-F)]

11.4

0.0

F=63.2 %

-0.5

50 oC

75

100

125

-1.0 -1.5 -2.0 -2.5 10-1

101

102

103

104

105

106

Stress time (s)

109

Time to Failure (a.u.)

Fig. 11.23 Weibull plot of TDDB distributions on silica-based low-κ dielectrics with SiO2 and PETEOS for comparison. (Adapted from [51]). (a) SiO2 (κ ¼ 3.9), (b) PETEOS (κ ¼ 4.2), (c) SiOF (κ ¼ 3.6), (d) SiOC1 (κ ¼ 2.9), (e) SiOC2 (κ ¼ 2.6), (f) MSQ (methylatedhydrogen silsesquoxane, κ ¼ 2.3). γ is the field acceleration factor

T = 378 K

107

f e

105

d c

b

a

103

g 101

10-1 0

1

2

3

4

5

6

7

8

9

10 11

12 13

Electric Field (MV/cm)

As the dielectric constant decreases, the intrinsic breakdown voltage is reduced. Of particular importance to analog applications is the impact of the lateral breakdown field on metal-to-metal spacing rules in high-voltage technologies, such as BCD. A low breakdown field requires a larger distance between metal lines. Lateral MIM capacitors with low-κ dielectrics are also affected. With optimal design and process conditions, however, low-κ dielectrics such as SiOF, SiOC, and SiCOH (κ ¼ 3.0) can exhibit “robust” MIM TDDB characteristics [52, 53]. The acceleration factor is extracted from the E-model as shown in Fig. 11.23, pffiffiffiffi but the E model also yields a good fit to measured data on low-κ dielectrics [56, 58–60]. One important factor which should be considered in the TDDB analysis of MIM capacitors is the surface roughness of capacitor plates at their interfaces with the

568

11 Chip Reliability

dielectric. Asperities at the interfaces locally enhance the field and hence the current. An increase in current degrades TDDB [61, 62].

11.4.2 Electromigration and Stress Migration Metal ions in a conductor are in constant thermal agitation. A fraction of ions can be thermally activated to approach a potential saddle point. When a voltage is applied to a conductor, two forces are exerted on the positive conductor ions: the force in the direction of the cathode due to the electric field and the force of electrons impinging on the ions toward the anode. If the net force, which is the total momentum exchange per second, on the thermally activated ion exceeds that of the electric field, the ion will tend to drift against the field toward the anode. Electromigration (EM) is the mass transport of metal ions by momentum exchange with conducting electrons [63]. Although electrons are very small compared to ions, the contributed momentum transfer of a very large number of electrons is high enough to drag ions in the direction of the “electron wind.” With time, the migration of metal ions causes vacancies that coalesce to form voids, thus reducing the effective cross section of the metal and increasing Joule heating and the local temperature where the ions are dragged away. EM is thus a wearout mechanism caused by the application of excessive currents to a conductor. For a metal line formed by a single layer of aluminum or copper, progression of voiding can cause an “open” failure. For a metal line with redundant refractory metals, voiding only causes an increase in resistance. Migration of ions can also cause extrusions in regions into which ions are dragged, which can potentially cause shorts between metal lines or a fracture of the insulator. EM increases with increasing current density and temperature and depends on metal composition, morphology, uniformity, and film-layer composition above and below the metal. EM is only possible in the presence of flux divergence that allows voids or extrusions to form (Fig. 11.24). The main driving forces of EM are current density, thermal gradient, and mechanical stress. Stress migration (SM), also called stress-induced voiding, is another wearout mechanism due to high levels of hydrostatic stress. The stress is typically caused by rigid overcoats of the metal with dielectrics of different thermal expansion coefficients than the metal, such as SiO2 and Si3N4 [64]. Line edges and topographical steps are typical regions of high stress where wedges and slits nucleate and grow with time to relieve the stress, which is typically tensile, resulting in discontinuities in the metal. Both EM and SM are influenced by microstructural properties, such as geometry of the test structure used, composition of layers, grain-size distribution, grain orientation (texture), and alloy solute distribution. They are also influenced by macrostructural properties, such as pattern dimensions, material selection, conductor thickness, topography, ILD properties, and inter-level contacting.

11.4

Failure Mechanisms

569

Grain

Grain

Diffusing atoms Grain boundary Diffusing atoms

(a)

(b)

Fig. 11.24 Illustration of flux divergence. (a) Local negative flux divergence at triple point, causing vacancies that can coalesce to form voids. (b) Positive flux divergence causing extrusions

(a) Aluminum and Aluminum-Based Alloys Aluminum films are polycrystalline, consisting of grains and grain boundaries. There are three diffusion paths in an aluminum line, surface diffusion, grainboundary diffusion, and lattice diffusion (diffusion within a grain). The migration of aluminum is dominated by grain-boundary diffusion (Fig. 11.24) [65]. The median time to EM failure follows a relation that was developed by J.R. Black and hence referred to as Black’s empirical relation [63, 66]. In its simplified form, the relation estimates the MTF as MTF ¼ t50 ¼ A0 jn eEa =kT s

ð11:53Þ

where t50 is the median time to failure (h), j is the current density (A/cm2), Ea is the activation energy (eV) over the temperature range of interest, k is the Boltzmann constant (eV/K), T is the absolute temperature (K), A0 is a parameter specific to process and structure, and the exponent n is typically 2 but can rise with inadequate heat removal [63]. For a pure aluminum lattice, the activation energy is Ea  0.85 eV. It is lower along grain boundaries ( 0.5 eV) [67]. The activation energy along grain boundaries can be increased to about 0.8 eV by alloying aluminum with 0.5–4% Cu, thus monotonically increasing the resistance against EM (Fig. 11.25) [67–70]. Cu segregates as CuAl2 at grain boundaries, impeding grain-boundary diffusion of aluminum. The fraction of Cu is typically limited to 0.5% because of difficulties with plasma etching and potential corrosion with higher Cu content. Also, adding 1% silicon to AlCu improves EM, particularly at contacts. Bamboo Effect and Triple Points When the line width becomes comparable to the grain size, the grain can, on the average, span over the entire width of the line, suppressing continuous grainboundary paths and hence diffusion along grain boundaries (Fig. 11.26) [71]. A chain of relatively large grains forms with a preferred orientation. Transmission electron microscopy (TEM) shows that in such a bamboo-like grain structure, the number of triple points is reduced [72]. Since triple points are sites of negative divergence, the bamboo-like grain arrangement increases the resistance to EM [71–73].

570

11 Chip Reliability 3 205 oC 0% Cu

% Change in Resistance

Fig. 11.25 Effect of Cu concentration on the stability of the AlCu film resistance [70]

J = 4 × 106 A/cm2

2 208 oC 0.5% Cu

208 oC 2% Cu

208 oC 4% Cu

1

0 0

5

10

15

20

Time (h)

J

W

Fig. 11.26 Bamboo structure

Acceleration Factors Electromigration can be accelerated by increasing the temperature while keeping the current density constant, by applying a higher current density and keeping the temperature constant, or by increasing both the current density and temperature. When applying a current to the line, however, it is important to take the local temperature rise due to self-heating into account. This is not an easy task, since the temperature cannot be controlled independently. Also, the temperature does not immediately settle to a constant value but varies within the duration of measurements. An attractive isothermal (constant temperature) test method is described in [74, 75]. In this test, the metal line is utilized as a temperature sensor and its TCR used to “in situ” monitor the temperature. The temperature is then kept constant by adjusting the current through the metal line. The temperature acceleration factor can be approximated from Black’s relation (11.53), as Ea t 501 k e AF ¼ t 502

1 1 T 1 T 2

ðT 2 > T 1 > T 0 Þ

ð11:54Þ

11.4

Failure Mechanisms

571

Fig. 11.27 Illustration of temperature acceleration of EM

AF =

t50−1 ; t 50−2

T2 > T1 > T3

ln t50

Extrapolated

Measured

1/T1

1/T2

1/T0

Inverse Temperature (K -1)

This is illustrated in Fig. 11.27 for two stress temperatures T1 and T2 with T2 > T1. The EM lifetime is found by extrapolation the plot to the use temperature T0 (typically taken as 85  C). For isothermal stress, the current-density acceleration factor is AF ¼ t 50use =t 50stress  j2stress =j2use

ð11:55Þ

Current Density Specifications There are three current densities that are specified for a given conductor: Time average DC current density, jdc—This is a function of junction temperature. A DC current density of 5  105 A/cm2 at a junction temperature of 85  C is typical. If the current in the conductor is not constant but is applied in short pulses repeated at intervals, then, for a time period T of the current waveform, 1 jdc ¼ T

ZT jðt Þdt A=cm2

ð11:56Þ

0

In the worst case, the ratio of the MTF for a rectangular-pulsed current to that for the DC stress, t50(pulsed)/t50(dc), is just the inverse of the duty cycle. This ratio, however, underestimates the EM lifetime. This is because the response times for the generation and relaxation of excess vacancies in the metal is larger than typical pulse repetition periods. Thus, the excess vacancy concentration can only attain a fraction of its equilibrium value under pulsed stress [76], and the rate of void formation under pulsed mode is reduced. The ratio t50(pulsed)/t50(dc) increases above the value given by the inverse of duty cycle, allowing an even higher current density. Root-mean-square current density, jrms—This is specified primarily to limit Joule heating to a rise in temperature of typically 5–10  C. The RMS current density is defined as

572

11 Chip Reliability

ZT jDC ¼

1 2 j ðt Þdt A=cm2 T

ð11:57Þ

0

One type of time-varying current is a sine wave. Under AC conditions, the displaced metal atoms reverse when the current changes polarity. This means that during the period where electrons flow in the opposite direction, some ions can move back toward their original position. For simplicity, if the amplitude and duration are equal in both polarities, this current is only considered in terms of localized Joule heating which, by a maximum RMS value, is kept at less than the specified limit on temperature rise. If the amplitude and durations are different in the two directions, the net DC current is treated as jdc (T. S. Sullivan, private communication, 1997). Peak current density, jpeak—This is the absolute maximum current density, corresponding to the peak of a waveform, above which it can lead to a catastrophic fail regardless of duty cycle. Example 11.3 Assume that the maximum allowed DC current density in a 0.5-μm thick metal line is Jmax ¼ 5  105 A/cm2 at 85  C. Estimate the maximum DC current in a 2-μm wide line at a junction temperature of 85 and 125  C. Assume an activation energy of Ea ¼ 0.5 eV. Solution The current is given by I max ¼ J max W m t m A where Wm and tm are, respectively, the metal width and thickness in μm. Substituting the values gives a maximum current of 5 mA at 85  C. From Black’s relation (11.53) and (11.55), the temperature dependence of maximum current is  2 I maxð85Þ =I maxð125Þ ¼ eðEa =kÞ½ð1=358Þ1=T398 ¼ 5:1 Thus, the maximum allowable current at 125  C is 5/2.26 ¼ 2.21 mA.

Redundant Metal Films One means of improving the electromigration resistance of AlCu or AlCuSi films is to sandwich the films with layers of refractory metals, such as Ti (which reacts with aluminum to from TiAl3), TiN, or TiW [77–81]. Over a 100 times improvement of Ti–AlCu–Ti over plain AlCu is reported [77, 78]. The large increase in EM lifetime is related to the TiAl3 layer, mainly because the rigid intermetallic layer suppresses the migration of Al in the form of extrusions and also acts as a redundant conductor that continues to carry the current even after a void causes the AlCu film to be

11.4

Failure Mechanisms

573

completely open [77]. The parallel films exhibit higher resistivity than aluminum but are less susceptible to EM because of their higher melting point. Thus, EM causes an increase in resistance rather than an open. It is the cross section of the AlCu line that limits the current density regardless of the presence or absence of refractory metals. Electromigration at Contacts and Vias The metal EM lifetime is shorter with stud (W-plug) chains than with only metal stripes (Fig. 11.28a). Contacts and vias are typically formed with films of dissimilar materials where aluminum and copper exhibit different diffusivities, resulting in atomic flux divergence at the film interfaces. The EM resistance of such inhomogeneous regions actually depends not only on composition and grain structure but also on the direction of current [78, 82–84]. Interfaces between barrier metals and aluminum are especially susceptible to voiding. This has been observed in W-plug contacts and vias where tungsten acts as a diffusion barrier to migrating Al and Cu. Voids form where electrons flow away from the contact; extrusions tend to form when electrons flow toward the contact (Fig. 11.28b). In addition, thinned metal at corners or sidewalls induces excessive current crowding and Joule heating effects that result in accelerated degradation [85]. As a result, metal connections represent weak links in the tungsten stud chain. A typical rule sets the current through a contact or vias equal to the current that can flow through the metal lead of the same width. For example, a 1-μm wide via can have a current equal to that of a 1-μm-wide metal.

105 AlCu

TiAl3-Al(Cu)-TiAl3 Void formation

104

W via chain

50X

103

Hillock formation AlCu

M1

(b) Hillock formation

TiAl3

M2

102 250 oC 106 A/cm2

Void formation

M1

101

1

10

50

90

99

(c)

Cumulative failure (%) (a) Fig. 11.28 (a) EM lifetime of AlCu stripe and two-level AlCu W-stud chain. (b, c) Void and extrusion formation in upstream and downstream electron flow. (Adapted from [78])

574 Fig. 11.29 Illustration of Blech effect. The length, Lc, is the critical length when EM and backflow forces cancel. (Adapted from [86])

11 Chip Reliability Backflow Al accumulation

Lc Al TiN Oxide

Al depletion

Electron flow

The Blech Effect and Blech Length For a given current density j, EM is self-limiting if the wire length is shorter than a critical length, referred to as the Blech length, Lc [86]. EM initially causes metal atoms to deplete where electrons enter the AlCu line, resulting in a tensile stress in that region, as illustrated in the test structure in Fig. 11.29 [86]. Since at typical stress temperatures there is negligible diffusion of Al and Cu atoms in TiN, the migrating atoms accumulate at the end where the electrons exit the line, exerting a compressive stress at that end. A stress gradient is thus established inducing a “backflow” of metal atoms that opposes EM. When the two forces balance, there is zero EM. This self-limiting mechanism is referred to as the Blech effect and characterized by the product jLc, where j is the current density and Lc the Blech length. This product can be extracted by varying the applied current density on structures of different length. It is considerably larger for damascene than for dry-etched structures. The difference is attributed to the smaller tensile stress in damascene structures [87]. Failure occurs when the pressure-induced diffusional backflow is overcome by the electromigration force. In practice, EM resistance of metal leads is improved by using compressively stressed protective overcoats that confine the metal under pressure and inhibit extrusions, hence limiting void formation [88]. Stress Migration The main driving force for stress migration (or stress voiding) is the thermal expansion mismatch between metal lines and the insulating layers surrounding them and also between the metal lines and the underlying silicon chip [64, 89–92]. Consider, for instance, a narrow aluminum line rigidly encapsulated and constrained by SiO2 and subjected to a post-metal anneal. The linear thermal expansion coefficient of aluminum is αAl  26 ppm/ C, for silicon αSi  3 ppm/ C, and for SiO2 αox < 1 ppm/ C. The different stages of the anneal cycle are shown qualitatively in Fig. 11.30 [64, 89]. When the metal is subjected to an anneal temperature in the typical range of 350–420  C and then cooled, it experiences a tensile strain of about (αAl  αox)  ΔT, where ΔT is the change in temperature. This is about 1% per linear dimensions. The metal will seek to lower its strain energy by relaxation, which in this case can occur only by forming voids [64]. During the rise in temperature, the stress in the metal changes from tensile to compressive where extrusion formation is possible. More important is the void formation which is driven by tensile stress during the cooling

Failure Mechanisms

Tensile

Void formation

Elastic curve

0

Compressive

Fig. 11.30 Illustration of tensile and compressive stress-induced voiding in narrow AlCu film during annealing. (Adapted from [89])

575

Stress

11.4

Recrystallization Hillock formation

0

200 Temperature (oC)

400

period. Stress voiding typically nucleates on wedges or slits at line edges and grows under thermal “aging” [64]. Unlike EM, which can be continuously accelerated by increasing the temperature and/or the current density, stress migration exhibits a saddle point, where it reaches its maximum and then falls off. This is because atomic transport is governed by two opposing mechanisms: diffusion and stress [64, 89]. Atomic diffusivity increases with increasing temperature, while the absolute value of stress increases with decreasing temperature. For AlCu, the maximum is at about 180  C. (b) Copper BEOL Advanced technologies use copper interconnects in conjunction with low-κ ILD to maintain the scaling and performance trends (Chap. 9) [93]. Pure copper is now the choice of low resistivity and high EM reliability for advanced technologies [94, 95]. While most of the preceding discussion of EM and stress migration for AlCu-based interconnects also applies to pure copper, there are still some reliability issues inherent to copper and low-κ materials to be addressed. Among these are copper contamination, CMP damage, and dielectric constant degradation, requiring complex processes to meet reliability requirements. Pure copper, of melting point 1085  C, is much more resistant to EM than AlCu (melting point 660  C). Disregarding surface migration, the EM lifetime is 40–100 times longer with copper than with AlCu (Fig. 11.31) [94]. The major diffusion paths for Cu interconnects are, however, interfaces with dielectrics and grain boundaries. While aluminum reacts with SiO2 to form an alumina, blocking diffusion of aluminum through the dielectric, Cu diffuses rapidly through the oxide if an effective Cu barrier is not present [96]. For this reason, copper migration is blocked with a refractory barrier liner on its sides, typically Ta or TaN, and capped with a diffusion barrier such as silicon nitride or a refractory metal (Chap. 9). The barriers also protect the copper itself from oxidizing species and corrosion. The fastest path for Cu migration in such structures is the interface between copper and the barrier dielectric

576 Fig. 11.31 Comparison of AlCu and Cu EM lifetimes

11 Chip Reliability

99.9 99

AlCu t50 = 1.31 h

J = 2.6 × 106 A/cm2 T = 295 oC

95 90

Cu t50 = 147.7 h

% fail

75 50

25 10 5

1 0.1 0.01 0.1

1

1

10

100

1000

Stress time (h)

[97–99]. The interface between Cu and the cap is a site of void nucleation [96, 100]. Adhesion of copper to the cap at the interface can be directly correlated to the EM MTF and activation energy [97]. For example, copper with a nitride diffusion barrier can delaminate, so that Cu can migrate between adjacent lines biased at different polarities creating shorts [101]. Blocking the migration paths of vacancies through grain boundaries and copper-barrier interfaces is essential for improving the Cu EM reliability [99, 101]. One method is to replace the dielectric cap layer with a refractory metal, such as self-aligned tungsten [102]. The line-width dependence of EM is different for Cu than for AlCu metal lines. Unlike AlCu, the MTTF increases significantly as the Cu line width is increased. Analysis shows that wider Cu lines have almost a bamboo structure, while the narrow lines consist of small grains. Therefore, the decrease in MTTF in the narrow Cu lines is probably due to a significant increase in grain-boundary diffusion [103]. As for AlCu, shorter interconnects are less susceptible to EM than longer lines due to the Blech effect. As a consequence, a “critical” product jLc, also referred to as threshold-length product, can be considered, which provides “immortal” interconnect length, thus benefiting circuit design. The reported jLc product ranges from 2800 to 7000 A/cm, at 300  C. The product depends on several factors, including the degree of tensile stress and the dielectric material used [104–108]. For example, jLc  4900 A/cm for Cu/FSG (κ ¼ 2.8) at 350  C, typically smaller than for AlCu. This is attributed to the higher tensile stress in copper [108].

Failure Mechanisms

Fig. 11.32 Illustration of Maxwellian distributions of electrons under two applied fields, E1 and E2 with E2 > E1

577

Relative number of electron, n(E)

11.4

E1

E2 > E1 E2

fi

0

1

f HCI

2

3

Electron Energy, E (eV)

11.4.3 Hot-Carrier Effects When a field is applied to silicon, free electrons and holes gain kinetic energy, following a distribution that is approximated as Maxwellian (Chap. 6). The distribution is shown schematically for two electric fields, E1 and E2, in Fig. 11.32. Also shown is the minimum energy ϕi ffi 1.5 eV required for impact ionization and ϕHCI ffi 3.2 eV for the injection of electrons from silicon into the oxide. Similar plots also apply for holes, with some modifications. As the field increases, the fraction of electrons that acquire energy larger than ϕi and ϕHCI increases. Electrons at such energies are said to be hot because the effective temperature related to their distribution increases above the crystal temperature: kTe > kTlattice. The minimum energy required to break a Si–H bond and create an interface state is 3–3.7 eV [109, 110]. Therefore, as the electric field increases, the probabilities for impact ionization, electron injection, and interface-state generation increase. Hot carriers can seriously affect the reliability of active components and circuits. (a) PN Junctions The reverse leakage current and breakdown voltage of planar PN junctions is affected by the properties of the insulator covering them and by the junction– insulator interface. When a junction is subjected to a high surface field, its reverse leakage typically increases and its breakdown voltage exhibits instability. Disregarding ionic drift along the surface and within the dielectric, instabilities are related to hot-carrier-induced positive or negative surface charge at high reverse fields. In an N+P junction, when positive charge accumulates at the surface, the N-region is accumulated and the P-region is depleted. The field is reduced and the breakdown voltage is increased. This is sometimes referred to as a “walk-out” phenomenon. Conversely, when negative surface charge accumulates, the

578

11 Chip Reliability

Oxide

+++++++++

N+

Reduced field

Oxide

-------

N+

Increased field

Depletion

Depletion

P (a)

P (b)

Fig. 11.33 Effect of hot-carrier-induced charge on surface field in N+P junction. (a) Reduced lateral field by positive surface charge. (b) Increased field with negative charge

N-region is depleted and the P-region is accumulated, resulting in a decrease of breakdown voltage which is sometimes called “walk-in” (Fig. 11.33). The effects are opposite for a P+N junction. For the typical case of oxide dielectric, the excess charge consists mainly of charged surface states induced by hot carriers. The effects recover partially at room temperature after a prolonged unbiased period or almost fully after annealing at elevated temperatures. Due to the above effects, surface breakdown diodes are not recommended for use as voltage references. Interface states also increase surface leakage (Chap. 3). While this leakage may be considered as negligible at room temperature, it can increase by 3–4 orders of magnitude from 25 to 150  C. This can become a problem in high-temperature applications. (b) Bipolar Junction Transistors, BJT The discussion of bipolar transistors in Chap. 5 focuses mainly on the low-complexity NPN and PNP transistors incorporated in a baseline CMOS technology without added processing steps. Since in both transistors the base consists of a lightly doped P-well (NPN) or N-well (PNP), the breakdown voltage of both emitter– base and collector–base junctions are high, above 15 V, while the operating voltage is typically much lower than this value. Thus, hot-carrier reliability of low-complexity bipolar transistors is typically not a concern. In contrast, in high-performance BJTs, such those described in Chap. 5 including polysilicon-emitter and SiGe BJTs, the emitter is degenerately doped and the base is highly doped [111]. Thus, even a base–emitter reverse bias as low as 1–2 V results in such a high field that electrons tunnel through the junction. Hot carriers resulting from tunneling create interface states as sites of SRH generation–recombination, increasing the emitter–base leakage in the forward mode, thus reducing the bipolar gain [112–116]. The reliability of high-performance bipolar transistor is not further discussed in this chapter. (c) CMOS Hot-electron effects in digital CMOS have been extensively studied, focusing on shifts in threshold voltage, off-state leakage, drain current, and transconductance. Of equal importance to analog applications is the effect of hot carriers on output

11.4

Failure Mechanisms

579

VG IG

VD > V G

VS = 0

A ID G P D

S Inversion

Holes Depletion

ISub

A

L' L P-substrate L (a)

Electric Field (× 105 V/cm)

A

7 6 5 4

No LDD

LDD

3 2 1 0 S

L (b)

D

Fig. 11.34 (a) Schematic of an NMOSFET biased in saturation showing the drain (and source) without a lightly doped extension and exaggerated inversion and depletion layers. (b) Illustration of peak electric field at the drain with and without LDD

resistance, low-frequency noise, and component matching (Chap. 10). This section summarizes hot-carrier reliability considerations in digital and analog MOSFETs. The reliability of high-voltage transistors is discussed in Sect. 11.4.8. Channel Hot Carriers A schematic cross section of an NMOSFET biased in saturation is shown with exaggerated depletion and inversion layers in Fig. 11.34a. The corresponding field distribution along the channel is shown schematically in Fig. 11.34b. The Substrate Current The field along the channel accelerates electrons from the source to the pinch-off “point” P. The field increases rapidly from the pinch-off point to the drain and peaks near the drain metallurgical junction (Chap. 6). A lightly doped extension (LDD, not shown in Fig. 11.34a) reduces the field. The high two-dimensional field generates electron-hole pairs by impact ionization. Electrons drift to the drain and holes to the substrate, creating a substrate current Isub (or IB, for bulk or body). The substrate current typically has its maximum when VG  VD/2, as discussed in Chap. 6. Gate Current and Surface Traps A fraction of hot carriers can have their momentum redirected toward the Si–SiO2 interface. Electrons with energies of 3.2 eV and above can surmount the silicon oxide barrier and be injected into the oxide. Once in the oxide, electrons are swept toward the gate, creating a gate current, IG (Fig. 11.35). The maximum gate current occurs approximately when VG  VDD and is typically very small compared to the substrate current. Depending on the electron energy distribution, hot carriers create interface and oxide traps which can be charged and discharged. This not only causes shifts in drain current, transconductance, and threshold voltage [117–127] but can also reduce the

580 Fig. 11.35 Band diagram illustrating electron injection into the gate and trapping in the oxide

11 Chip Reliability

Depletion

Ec

Hot 3.2 eV

Si

Gate current

-- -- Trap

Oxide

Gate qVG

output resistance [128, 129], increase 1/f noise [130], and increase MOSFET mismatch [131–133], which are detrimental to analog designs (Chap. 10). The “Lucky Electron” Model [117] The “lucky electron” model is a conceptual model that leads to a simple method to predict hot-carrier lifetime from accelerated stress data, particularly in NMOSFETs. Hot electrons at a distance below the surface of the order of the hot-electron meanfree path λ can reach the surface without losing energy by collisions. Electrons with energies above 3.2 eV contribute to the gate current. A very small fraction can be trapped within the oxide. The gate current is expressed as I G ¼ CeqϕB =Em λ A

ð11:58Þ

where λ is the mean-free path (about 9 nm at 30  C), Em is the maximum field at the drain, and ϕB is the silicon oxide barrier in V. In this model, impinging electrons can generate interface traps only if their energy is above the threshold energy for interface-state generation, which is about 3.7 eV [120, 121]. The substrate current is considered as a powerful predictor of hot-carrier lifetime. The ratio of gate current to drain current is given as [120] I G =I D ¼ 4  104 ðI sub =I D ÞϕB =ϕi

ð11:59Þ

where ϕB is the oxide barrier (~3.2 eV), ϕi the energy required for impact ionization (~1.5 eV), and ID the drain current, and the factor 4  104 derived in [120]. Interface states in NMOS are generated in the saturation mode where VD  VG is high, but not in the linear mode where VG  VD is high [118, 119]. Using chargepumping measurements, the interface states are correlated with transconductance degradation and substrate current. The degradation is attributed to interface generation by hot electrons and hot holes [118, 119], but not to fixed oxide charge [119, 126]. Deviations from the “Lucky Electron” Model In deep submicron NMOSFETs, the degradation of transconductance is measured at a voltage much lower than the energy for interface-state generation, and the “lucky electron” model does not always hold [122–126]. In this case, there is no “critical

11.4

Failure Mechanisms

581

voltage” such as the Si–SiO2 barrier for hot-carrier degradation [122]. At a given drain voltage, the peak field is calculated using 2D simulations, and an electron temperature Te is extracted as Te ¼

  qλ Epeak K k

ð11:60Þ

where λ is the mean-free path and Epeak is the peak field [122]. The substrate and gate currents can then be expressed as I sub  2I D eqϕi =λEpeak A IG / IDe

qϕB =λEpeak

ð11:61Þ ð11:62Þ

A

Thus, the gate and substrate current are correlated as in (11.59). The shift in the energy distribution to higher values is explained by electron–electron interactions [123, 124]. Hence, the tail of the electron energy distribution in Fig. 11.32 extends to higher energies than the product qVapp, where Vapp is the applied voltage. The peak in degradation, however, is not correlated to the peak substrate current at VG  VD/2. Instead, degradation keeps increasing until VG  VD [125]. Lifetime Prediction The hot-carrier DC lifetime follows a power law. The shift in threshold voltage (or drain current) can be modeled as [127] ð11:63Þ ΔV T ðor ΔI Dsat =I Dsat Þ ¼ At m For an NMOSFET, the criterion for a fail is typically ΔVT ¼ 10 mV, or ΔID/ ID ¼ 10%, or Δgm/gm ¼ 10%. The time to fail is empirically related to Isub as t F ¼ A0 ðI sub =W Þn s

ð11:64Þ

where A and A0 are process-dependent constant, W is the MOSFET width, and n and m can be extracted from measurements (Fig. 11.36). A similar relation can be defined for the MTF dependence on drain current. Fig. 11.36 Example of hot-carrier lifetime projection for NMOSFET

102 10-year lifetime

101

MTF (yr)

100 10-1 n≈3

10-2

Isub-stress

10-3 10-4

Isub-use

10-5 0.1

1 10 Substrate Current, Isub (mA/mm)

100

582

11 Chip Reliability

Pulsed-Stress Lifetime The preceding section discussed degradation by channel hot electrons under DC stress conditions. To simulate actual circuit conditions, it is also necessary to analyze the degradation under pulsed-stress conditions [134–138]. This is not only because of duty cycle considerations but also due to effects caused by the pulse pattern itself. Figure 11.37 is a schematic of the switching sequence of an inverter in a ring oscillator. The time, Δt, during which both NMOS and PMOS conduct is very short resulting in a very small duty cycle, Δt/t0. If one assumes that degradation only occurs during Δt, then the hot-carrier lifetime is extended by the factor t0/Δt. Example 11.4 Assume that hot-carrier degradation occurs only during the transition time Δt ¼ 1 ns and the cycle time t0 ¼ 1 μs (Fig. 11.37). For a DC hot-carrier lifetime projection of 5 days, estimate the lifetime of the switching inverter. Solution The duty cycle is Δt/t0 ¼ 109/106 ¼ 0.1%. The actual circuit lifetime is 5000 days  13.7 years. VDD

PMOS VIN

NMOS

VOUT Load capacitor Ground

t0

VOUT

VIN

Dt Duty cycle = Dt/t0

Fig. 11.37 Channel hot-carrier effect during inverter switching

The simple projection of effective hot-carrier stress time from DC to pulsed mode in the above example is not always applicable. Depending on the phase shift between drain and gate voltage pulses, an enhanced degradation can occur during the leading or trailing gate pulse, as illustrated in Fig. 11.38 [134–136]. Experimental results show that degradation occurs mainly during trailing VG at high VD (Fig. 11.38b). This is where the inversion layer “disappears,” and holes flow from drain to channel to restore neutrality. The flow of holes is believed to cause degradation. When VG leads VD, as in Fig. 11.38a, mainly electrons flow from source into channel, and negligible degradation is observed during this period [134]. Degradation during switching is more important to digital than to analog applications because analog circuits are typically biased under quiescent DC conditions,

11.4

Failure Mechanisms VD

583 VG

VD

VG

(b)

(a)

Fig. 11.38 (a) Drain pulse leads gate pulse. (b) Gate pulse leads drain pulse Fig. 11.39 Illustration of substrate hot-electron injection

VG A

IG

VS = 0

VD = 0 Gate Drain

Source e

e

e e e High vertical field

e P-substrate at ground

nearly 100% duty cycle. Due to the longer duty cycle, however, a longer channel must be used for most analog applications to meet the HCI lifetime. Surface- and Buried-Channel PMOSFETs For PMOSFETs, there is no correlation between interface-state generation and substrate current [119]. In saturation, the polarity of drain voltage is favorable for hot-electron injection and trapping in the oxide. The trapped charge reduces the magnitude of threshold voltage and increases the transconductance. A small decrease in transconductance is observed only in the linear region where hot holes are injected [139]. Similarly to the NMOSFET, hot-carrier degradation in deep submicron PMOSFETs occurs even when the drain voltage is lower than the Si– SiO2 barrier [140]. For PMOSFETs of same dimensions biased under similar conditions, hot-carrier degradation is less for buried-channel than surface-channel PMOSFETs [141]. This is because in buried-channel MOSFETs, the inversion carriers flow deeper below the surface. Hot-carrier stressing and lifetime projection are similar to those of NMOSFETs. Substrate Hot Electrons Substrate hot-electron injection occurs when electrons are thermally or optically generated, or injected by a forward-biased junction into the substrate, and reach MOSFET regions with high vertical fields where they are accelerated toward the surface (Fig. 11.39).

584

11 Chip Reliability

In typical lightly doped P-type substrates, electrons can diffuse long distances, about 1000 μm at room temperature, and reach high-field regions, causing shifts in MOSFET parameters. Process and Design Solutions The susceptibility of MOSFETs to hot-carrier degradation can be reduced by process and layout techniques. The peak electric field is typically reduced by grading the drain junction profile and adding a lightly doped drain extension, LDD, as shown in Fig. 11.40 [142]. There is, however, a trade-off between the reduction in electric field extent and the increase in series resistance and overlap capacitance caused by the LDD. The extent of LDD under the gate can be optimized [143]. For analog applications, however, reducing the substrate current is of paramount importance. This can be achieved by reducing the LDD concentration and placing its peak below the surface by angled implantation at an appropriate energy and dose, increasing the average distance of hot carriers from the surface (Chap. 6). Hot-carrier effects in digital CMOS can be reduced by incorporating nitrogen into the oxide [144]. Adding nitrogen to the oxide can, however, increase the flicker noise, degrading analog performance, if the nitride concentration and profile in the oxide are not well-controlled (Chaps. 10 and 11). If the cost is affordable, post-metal anneal can be done with deuterium instead of hydrogen. The heavier deuterium bond is more difficult to break by energetic carriers. Where performance is not of paramount importance, the channel length can be increased to reduce the lateral field. Also, MOSFETs can be cascaded to reduce the drain voltage in individual transistors. Fig. 11.40 Reduction in the peak field with lightly doped drain. (Adapted from [142])

Pre 1980

Gate 0.1

0.3

0.5

0.7

0.9

N+

N-

E (×105 V/cm)

Drain 5 4 3 2 1 0 0.1

LDD Conventional

0.3

0.5

0.7

0.9

Position along surface (mm)

11.4

Failure Mechanisms

585

11.4.4 Bias-Temperature Instability Bias-temperature instabilities are shifts in MOSFET parameters observed when the transistor is stressed with a voltage on the gate with respect to source, drain, and substrate at an elevated temperature. (a) Negative Bias-Temperature Instability, NBTI Negative bias-temperature instability (NBTI) describes shifts in MOSFET parameters when a negative voltage is applied to the gate at an elevated temperature. It was first observed as an increase in threshold voltage in PMOSFETs [145]. Since then, NBTI became a major reliability concern in CMOS. NBTI causes shifts in threshold voltage, ΔVT, transconductance Δgm, effective mobility Δμeff, and drain current in linear and saturation modes, ΔIDlin, ΔIDsat [146]. This is especially an issue with PMOSFETs because they operate with a negative voltage on the gate. It is also observed in NMOSFETs in accumulation, but since NMOSFETs seldom operate with a negative voltage on the gate, most of the NBTI discussion focuses on PMOSFETs. Origin of NBTI It is commonly accepted that the origin of NBTI is the result of an electrochemical reaction in which silicon–hydrogen bonds at the Si–SiO2 interface are broken and the reaction is limited by hydrogen diffusion [145]. This results in the generation of positive interface states and oxide charge. The reaction depends on vertical field, inversion-hole density, temperature, and diffusivity of neutral molecules carrying hydrogen away from the Si–SiO2 interface [146]. In addition to interface states, the generation of positive charge due to hole injection into the oxide appears to occur within a tunneling distance from the interface. The detailed nature of the NBTI mechanism is, however, not well understood. Stress and Acceleration To study the NBTI mechanism, a negative stress voltage is applied to the gate, while source, drain, and substrate (MOSFET body) are held at ground. The gate dielectric is typically subjected to a vertical field, ranging from 106 to 107 V/cm, and the temperature typically varied from 25 to 300  C. Figure 11.41a shows an example of threshold voltage increase with time under a moderate field stress at 250  C. In this example, ΔVT does not saturate [147]. The dependence of ΔVT (or ΔID) on time follows a power law as ΔV T ¼ At n V

ð11:65Þ

with typically n  0.25 (Fig. 11.41b). The power t1/4 dependence of surface trap density suggests that the degradation is diffusion-controlled [145]. The degradation is accelerated by increasing the gate voltage (oxide field) and temperature. The NBTI temperature activation is believed to be related to the diffusivity. The thermal activation energy is in the range 0.15–0.3 eV [148].

586

11 Chip Reliability

40

100

250 oC

250 oC

DVT = Atn

DVTlin (mV)

DVTlin (mV)

30 20

10

10 0

n ≈ 0.25

A 0

2000

Stress Time (s) (a)

4000

1 100

101

102

103

Stress Time t (s)

104

(b)

Fig. 11.41 (a) Increase in PMOSFET ΔVT with NBTI stress time. (b) Power law plot with slope n and intercept. (Adapted from [147])

Recovery The degradation recovers significantly when the stress is removed. Ultrathin gate oxides (< 3 nm) show a large recovery which is proportional to the time between stress removal and threshold voltage measurement, causing errors in the measurement of the actual threshold voltage shifts [149–153]. The recovery is attributed to hole trapping by dielectric traps [149–152] or to the recapture of hydrogen (passivation) by interface states [153]. To minimize recovery before and during measurements, the stress voltage on the gate is not interrupted for test. Instead, it is kept constant during stress and measurement. This method, dubbed as “on-the-fly” characterization, is described in [149]. It consists of measuring the linear drain current at different time periods during the stress. The fast and ultrafast on-the-fly IDlin technique has been successfully used to more accurately study the kinetics of NBTI [152, 154–157]. Dependence on Dielectric Composition and Structure Experimental results show that the generation of interface states is inversely proportional to the gate oxide thickness. This implies that NBTI becomes more severe as the gate oxide thickness is reduced [158]. The dependence on oxide thickness is partially attributed to the faster diffusion of molecular hydrogen away from the interface. Nitridation of thin gate oxides is commonly done to prevent boron penetration from the P+-poly gate into the oxide and silicon (Chap. 9). Incorporating nitrogen at high concentration, however, not only increases low-frequency noise but also enhances NBTI degradation by creating more traps inside the oxide near the silicon surface. The impact of nitrogen on NBTI can be suppressed by optimizing the nitrogen concentration and placing the nitrogen peak away from the surface, for example, by plasma nitridation [159–162]. Compared to surface-channel PMOSFETs, buried channel structures exhibit higher NBTI reliability. Together with the lower flicker noise and higher

11.4

Failure Mechanisms

587

hot-carrier reliability, this makes buried channel PMOSFETs a better choice for analog circuits [163]. (b) Positive Bias-Temperature Instability, PBTI Positive bias-temperature instability, PBTI, describes shifts in MOSFET parameters when a positive voltage is applied to the gate at an elevated temperature. PBTI has not been as extensively studied as NBTI but has received more attention in the advent of high-κ dielectrics [164, 165] and ultrathin nitrided gate oxides [150, 166]. As with NBTI, the nitrogen profile in the gate oxide plays an important role in PBTI instability. In NMOSFETs with plasma-nitrided gate oxide (PNO), positive bias stress induces negatively charged interface traps [166], increasing the threshold voltage and reducing transconductance and off-current. Unlike NBTI in PMOS, on-the-fly tests show negligible recovery between stress and measurement of parameters [166]. Bias effects on high-κ dielectrics are not discussed in this chapter.

11.4.5 Joule Heating and Resistor Reliability The current through resistors is restricted either by electromigration in metal leads and contacts to the resistor or by resistor Joule heating [167–169]. It is important to determine where the degradation takes place. An arbitrary criterion for a resistor failure is a maximum change in temperature by ΔT ¼ 5–10  C at an operating junction temperature of 105  C. A small ΔT is chosen to minimize the change in resistance and its impact on circuit characteristics. To satisfy this criterion, the DC current density, jrms, must be kept very low. This section discusses Joule heating in silicided and unsilicided polysilicon and thin-film resistors (TFR). It is assumed that the resistor is connected with sufficiently wide metal leads and multiple contacts and vias, so that electromigration in contacts and metal can be neglected. (a) Polysilicon Resistors Typical poly resistors incorporated in a CMOS technology are placed over the shallow-trench isolation and categorized as having low-sheet resistance, LSR (5–8 Ω/□); medium-sheet resistance, MSR (200–500 Ω/□); and high-sheet resistance, HSR (1000–8000 Ω/□). The DC power generated in the resistor is P ¼ I 2 R ¼ I 2 RS

Leff ¼ j2 ρPoly V Poly W W eff

ð11:66Þ

where Leff and Weff are, respectively, the effective (electrical) resistor length and width, j is the current density in A/cm2, ρPoly is the polysilicon resistivity, and VPoly is the volume of the polysilicon resistor. Heat is dissipated in three dimensions from the area and perimeter of the resistor, mostly into the substrate. Thus, the effective area for heat dissipation is larger than

11 Chip Reliability

Increase in Temperature, D T (oC)

588

100

tPoly = 0.2 mm Wpoly = 3.0 mm

90 80

2000 W /

70

400 W /

60 50 40

200 W /

30 20 10

DT = 10oC 5 W/

0

0

5.0×104 1.0×105 1.5×105 2.0×105 2.5×105 3.0×105 Current Density, jRMS (A/cm2)

Fig. 11.42 Increase in temperature as a function of current density in polysilicon resistors

the actual resistor area. It can be determined by simulating the different resistor geometries. The rise in temperature is given as ΔT ¼ Rth P K

ð11:67Þ

where Rth is the thermal resistance given by Rth ¼ Δx=κAeff K=W

ð11:68Þ

Δx is the path for heat flow normal to the resistor surface, and Aeff is the effective heat-dissipating area that also depends on resistor width and thickness. Since for a polysilicon resistor, the heat dissipation is practically limited by the STI, κ is the thermal conductivity of TEOS oxide (14 mW/ C-cm). The resistor can be calibrated by measuring its TCR and the result used to determine the rise in temperature as a function of current density (Fig. 11.42). The maximum current density, jrms, increases as the resistor width decreases because of the higher perimeter of area ratio. (b) Thin-Film Resistors The criterion for a TFR failure under current stress is similar to that of polysilicon resistors [168–171]. Joule heating rather than electromigration limits the current density in circuit applications. Since the current limitation determined from Joule heating is more than two decades smaller than the current limitation due to electromigration, the extracted TFR EM lifetime is very long (>100 year) [159]. Degradation is thus defined as a change in resistance with stress temperature. For a SiCr TFR, an increase in temperature of 5–10  C or a decrease of 1–2% in resistance is

11.4

Failure Mechanisms

589

typically chosen as the failure criterion [159–161]. This occurs typically at a current density of 0.1–0.2 mA/μm width. The TFR is constructed at a large vertical distance from the substrate to improve its RF performance (Chap. 8). The higher the resistor is placed above the substrate, however, the larger the thermal resistance for heat transport to the substrate. This effectively reduces the allowable maximum current density as the distance increases. Calculating Joule heating from TCR measurements is not accurate because the TCR of SiCr resistors is very small. The temperature is best measured with independent temperature sensors, such as narrow aluminum lines of known TCR placed under the resistor. Other sensors may also be applicable.

11.4.6 Plasma Charging and Damage A plasma is a partially ionized gas that contains positive and negative ions, electrons, excited neutral atoms and radicals, and a “gas” of emitted photons [172, 173]. Photons are emitted when excited species lose energy via spontaneous emission to lower energy states, which is the basis for the “glow” of the discharge. Positively charged carriers are mostly singly ionized atoms, radicals, or molecules created by impact with energetic electrons. The plasma density ranges from 108 to 1013 atoms/cm3, depending on the power used. When a wafer which is connected to a powered electrode is placed in the plasma, it is bombarded with both electrons and positive ions. Because of the higher electron mobility, the wafer charges negatively, forming a sheath across which an electric field occurs that accelerates positive ions toward the wafer surface. The angular distribution of accelerated ions is very narrow and directional, nearly normal to the wafer surface. It is this electric field which causes the ions to be energetic (where they can cause damage) and to result in anisotropic etching (Fig. 11.43). For plasma etching to proceed successfully, the etch by-products must be evacuated from the plasma chamber. Fig. 11.43 Schematic of a simplified plasma reactor illustrating the field acceleration of positive ions across the sheath

RF

Top reactor plate Sheath (Dark Space) + + -

-

+ + -

-

-

VSheath Vox

+ + -+ Plasma -+ - + ++ + + + + Sheath (Dark Space) Wafer

Bottom reactor plate

590

11 Chip Reliability

(a) Plasma Damage When a wafer is exposed to a plasma, ion bombardments and charging can damage components and degrade their parameters. The degradation can be recoverable or permanent, depending on its extent. It can be caused by process conditions, layout, and tool configuration. During plasma processing, thin gate or capacitor dielectrics can be severely degraded, resulting in a decrease in breakdown voltage. Plasma charging can also induce Si/SiO2 interface states and trapped charge in the oxide without seriously affecting the breakdown voltage [174]. Ideally, the plasma should be uniform with equal numbers of positive and negative charges throughout the region. In this case, the average field across the sheath is in the low kV/cm range, too low to cause degradations in the oxide. Plasma tools, however, do not have ideal uniformity. One model that qualitatively relates surface charging to the nonuniformity of the plasma is described in [175, 176]. When the electron current and positive ion currents do not balance, the oxide surface can charge up, increasing the field across the oxide. When the field increases above approximately 107 V/cm, Fowler– Nordheim tunneling becomes significant. It is the FN current that causes oxide damage [175]. An increase in interface trap density can be observed by chargepumping measurements or by measuring the increase in MOSFET low-frequency noise [177]. Plasma charging of a masking film can also affect the profile of etched patterns due to the repelling field of the mask charge. This can cause “bowing” at the sidewall of deep and shallow trenches [178]. In metal etching, charging occurs exclusively during the last phase of “clearing” the metal (endpoint) [179]. This also applies to etching doped polysilicon and can be explained by the sudden interruption of the current path from the patterned metal or polysilicon to the rest of the wafer. (b) Antenna Effects Figure 11.44 illustrates the antenna effect. Let the polysilicon capacitance per unit area over the thick STI oxide be CSTI and the area over the thin gate oxide be CG. The total polysilicon area acts as an antenna and collects a total plasma charge QTotal. The collected charge is, however, distributed between the gate oxide charge and the STI 100%

Charge Yield

Polysilicon antenna Gate oxide STI

STI

FN Gate oxide tunneling

(a)

Substrate

(b)

Maximum allowed AR

Antenna Ratio

(c)

Fig. 11.44 Illustration of the antenna effect.(a) Top view of antenna. (b) Charging and location of FN tunneling. (c) Impact of large AR on yield

11.4

Failure Mechanisms

591

oxide charge. The polysilicon voltage, Vpoly, must be the same over STI as the voltage over the gate oxide (polysilicon must be equipotential). Therefore, the charge per unit gate area is QG ¼ V poly CG 

V poly ε0 εox C=cm2 t ox

ð11:69Þ

And the charge per unit STI area under poly is QSTI ¼ V poly CSTI ffi

V poly ε0 εox C=cm2 t STI

ð11:70Þ

where tox and tSTI are, respectively, the gate oxide thickness and the thickness of the STI oxide. For tSTI ¼ 600 nm and tox ¼ 3 nm, the ratio is QG =QSTI ¼ 600=3 ¼ 200

ð11:71Þ

As the total polysilicon area increases, more charge will be collected and the charge per unit area will increase in both regions. The ratio in (11.71) will, however, remain 200:1. When the charge density in the gate oxide reaches about 1.5  1013 charge/cm2 (Eox ffi 7  106 V/cm), FN tunneling will begin to degrade the oxide. The ratio of the total polysilicon area to the gate area is defined here as the antenna ratio (AR). (c) Protection Against Charging Damage The plasma charging effect cannot be totally eliminated, but the susceptibility to plasma damage can be reduced by optimizing the layout, process, and plasma tool [172, 180]. The tool can be optimized by “trial and error,” by changing the power, the chamber pressure, or the gap between top electrode and wafer. Incorporating nitrogen, by depositing plasma-nitrided oxide (PNO) or N2O nitrided oxide, shows significant improvement to charging damage over pure oxide in both MOSFETs and MIM capacitors [181–183]. Also, replacing pure oxide with plasma-enhanced nitride (PEN) in MIM capacitors formed in an aluminum-based or copper metallization process improves the capacitance density without impacting the TDDB reliability [184]. However, as mentioned earlier, incorporating nitrogen into the oxide degrades analog performance. Preventing back end of the line (BEOL) plasma-induced charging damage on gate oxide and MIM capacitors dielectrics is of great importance because, if no precautions are taken, the antenna effect of metal leads can be significant. Connecting the gate of NMOSFETs to an N+P protective diode and the gate of PMOSFETs to a P+N junction for PMOS is a typical means of dissipating the plasma charge before it causes damage [185]. The charge is dissipated in both polarities. Photon emission and the elevated temperature during the plasma process contribute to increase the generation of electron-hole pairs and accelerate charge dissipation. In multilevel

592

11 Chip Reliability

Fig. 11.45 Metal connection scheme for a MIM capacitor with high immunity to plasma damage

Top Metal

M5 Cap Top Plate M4 Cap Bottom Plate

M2

M2 M1 Protect Diode Substrate

metallization, however, photons are shielded from reaching the junction, so their contribution to charge dissipation is suppressed. Thus, for a protective junction to be efficient in the reverse mode, its area must be increased so that its reverse-bias leakage at the plasma temperature increases above the charging plasma current. Reducing the metal antenna ratio is a layout means of suppressing plasma charging. It is essential that design rules for the antenna ratio be defined. The maximum allowable ratio is process and tool specific, but a range of 100:1–1000:1 is typical. In MIM capacitors, the top and bottom capacitor plates are connected with metal that act as top and bottom antennas. Of particular importance is the ratio of top antenna area to bottom antenna area which should be kept close to unity [180, 186, 187]. Otherwise, the difference in charge collection between the two antennas creates a field between the two capacitor plates. The field increases as the difference between the top and bottom antenna areas increases, eventually degrading the TDDB of the capacitor dielectric. Thus, it is important to keep the area ratio close to unity. It is also important that the bottom plate is connected to the substrate before the top part of the capacitor is formed [187]. Figure 11.45 shows a connection scheme for a high MIM plasma-damage immunity. Connections to the top and bottom plate, including protective diodes, are symmetrical.

11.4.7 Latch-Up Latch-up is a transition from a high-impedance to a low-impedance state in a fourlayer PNPN or NPNP structure. In a product, latch-up is the creation of a low-impedance path between the power supply rails. If not controlled, the transition can cause a destructive parasitic effect in CMOS, BiCMOS, and BCD circuits. Latch-up in a four-layer structure is similar to that of a silicon-controlled rectifier

11.4

Failure Mechanisms

593

V

3 P

1 N Junctions 2 P

Current (A)

(a) Holding point

CMOS: as RNW, RPW decrease ITr and IH increase

IH

Trigger point

2

3 N Ground

(b)

Slope 1/Ron

ITr 1

VH

Voltage (V)

VTr

Fig. 11.46 (a) Shockley’s PNPN diode. (b) Current–voltage characteristic of latched-up PNPN structure [188]

(SCR). The structure effectively blocks current between the two end-terminals of the four-layer structure until it is intentionally or unintentionally triggered into a low-impedance mode. This section discusses only unintentional triggering of the SCR action, leading to latch-up in CMOS and resulting in high excess current at a very low collapsing voltage. (a) Mechanism Perhaps the simplest structure to understand latch-up is the PNPN structure, often referred to as a Shockley diode (Fig. 11.46a). The structure in Fig. 11.46a consists of three junctions. A positive voltage is applied between the outer P- and N-regions, while the two inner regions are floating. Junction 1 and junction 3 become slightly forward-biased because the end P-region is at a higher potential than its adjacent N-region and the end N-region is at lower potential than its adjacent P-region. A reverse bias appears in the middle junction 2. It is junction 2 that blocks the current path between the two outer terminals. The Shockley diode can be triggered into a forward conducting state by applying a pulse that forward biases the middle junction (not shown). A regenerative process then causes all three junctions to be strongly forward-biased and the voltage between the end-terminals to collapse to a very small value, as shown schematically in an I–V characteristic of Fig. 11.46b. The minimum current and voltage in latch-up are defined as the IH and VH, the holding current and holding voltage, respectively. If certain conditions are satisfied (discussed below), the structure remains in the low-impedance mode after the triggering pulse is removed. It is said to latch up [188–190]. If the current is not limited, Joule heating can destroy the device. The Shockley diode can be represented by two transistors, a PNP and an NPN transistor, as shown in Fig. 11.47. This is a merged structure in which the base of the

594

11 Chip Reliability

Fig. 11.47 Representation of a PNPN structure by an NPN and a PNP transistor

I

V Emitter

P

Base

N

Collector

P

PNP Ibp= Icn

NPN

N

Collector

P

Base

N

Emitter

Ibn= Icp

Ground

I

PNP transistor is the collector of the NPN transistor and the base of the NPN transistor is the collector of the PNP transistor (Chap. 5). The PNP collector current, Icp, drives the base of the NPN transistor. Let I be the total current through the structure. Then, I cp ¼ αp I þ I cpo ¼ I bn A

ð11:72aÞ

Similarly, the NPN collector current is I cn ¼ αn I þ I cno ¼ I bp A

ð11:72bÞ

where Icpo and Icno are, respectively, the PNP and NPN collector-base leakage currents; αp and αn are the PNP and NPN grounded-base current gains; and Ibp and Ibn are the PNP and NPN base currents. The total current is I ¼ I cp þ I cn A

ð11:73Þ

From the above relation, the total current can be expressed as I¼

I cpo þ I cno I  ¼  co  A 1  αp þ αn 1  αp þ αn

ð11:74Þ

Without external disturbances, Ico consists of thermally generated electron–hole pairs. When Ico is very small, the current gains are also very small due to the recombination of minority carriers (Chap. 5). As Ico is increased, e.g., by impact ionization, the gains increase and the sum of the gains approaches unity. When this

11.4

Failure Mechanisms

595

occurs, (11.74) indicates that the current tends to “infinity” and is only limited by the series resistance. For the PNPN structure in Fig. 11.46a to be an active SCR structure which can exhibit latch-up after applying a trigger pulse (Fig. 11.47b), several conditions must be met: 1. The transistor gains must be such that αp + αn  1 (or βp  βp  1). 2. The voltage applied must be larger than the holding voltage. 3. The circuit must be capable of supplying a current equal to the holding current of the PNPN structure. (b) Latch-Up in CMOS The parasitic transistors that form a PNPN or NPNP path in CMOS are shown schematically in Fig. 11.48 [191, 192]. The sources of the PMOSFET and NMOSFET are shorted to the corresponding wells. Thus, in normal operation, the junctions do not forward bias. Lateral voltage drops can, however, be created, for example, by parasitic currents originating in circuits outside the four-layer structure [190, 193], by radiation, or by impact ionization within the structure. Assume, for example, that a parasitic substrate hole current is collected at the P-well contact of the NMOSFET. The hole current causes an IRPW drop in the P-well under the NMOS source, locally raising the potential of the P-well with respect to the source, forwardbiasing the source-to-P-well junction. The source now acts as the emitter of the NPN transistor and injects electrons into the P-well that acts as the base of the NPN. Electrons diffuse through the P-well and P-substrate, reaching the N-well, the collector of the NPN, and drifting to the N-well contact. The electron current causes an IRNW voltage drop that locally forward biases the source of the PMOSFET which now injects holes into the N-well. The holes diffuse through the N-well, reach the P-substrate, and then drift through the P-substrate and P-well toward the NMOSFET P-well contact. The injected and collected hole current increases the IRPW voltage VIN

NMOS VSS = 0V

PMOS VDD

VOUT

NWELL contact

PWELL contact

S

STI P h

D N

STI h

e

PWELL RPW P-substrate

N

D P

STI P

S P

N e

NPN PNP

STI N e RNW NWELL

CNW

Fig. 11.48 Cross section of a typical CMOS inverter showing parasitic lateral NPN and PNP transistors and lateral currents. There is also a vertical PNP transistor between the P-type source (or drain) and P-type substrate with the N-well as the base (not shown)

596

11 Chip Reliability

drop which enhances the forward current at the NMOSFET source-to-P-well junction and so on. The regenerative feedback causes the inverter to latch up, as in Fig. 11.46b. Region 1 in Fig. 11.46b is characterized by a low current at all voltages until impact ionization becomes significant. Region 3 is a high-current, low-voltage state with a slope equal to the inverse of the on-resistance. Connecting regions 1 and 3 is region 2 of negative resistance [194]. While in region 2, the SCR will recover and return to normal operation after the trigger pulse is removed. The structure remains latched in region 3 after the trigger pulse is removed if the three conditions in the preceding section are satisfied. Latch-up can also be triggered by the injection of minority carriers into the substrate from a forward-biased junction in I/O circuits or high-voltage transistors on the same chip. Since the electron diffusion length in typically P-type substrates is very large, above 1000 μm, a circuit located at large distances from the injecting junction can be affected. Latch-up in CMOS is potentially catastrophic, causing blown-up metal lines and molten silicon due to thermal runaway. It can also cause “latent damage” in metal lines, not observed in standard tests. The damage manifests itself as localized “ejection” of part of the metal line, reducing its cross section and enhancing EM failure [195]. Transient Triggering The equivalent circuit in Fig. 11.49 shows a capacitance CNW between N-well and P-substrate. This is the depletion capacitance of the PNPN middle junction, which is typically reverse-biased. When the reverse voltage across the junction increases, the depletion region expands and majority carriers are “pulled” away from the junction. Similarly, when the reverse bias decreases, the depletion region contracts and majority carriers drift back toward the junction. The current during this voltage transient depends on the rate of majority-carrier flow as

Fig. 11.49 Basic equivalent circuit of the CMOS inverter in Fig. 11.48. RPW and RNW are the local P-well and N-well resistances; IEN and IEP are the emitter currents of the NPN and PNP transistors

+V

RNW

I

INW

IEP PNP

ICN

ICP

CNW NPN RPW

IEN

I

IPW

11.4

Failure Mechanisms

i¼

597

dðC NW vÞ dv dCNW A ¼ CNW þ v dt dt dt

ð11:75Þ

If the change is very rapid, the rate of majority-carrier flow can cause the current to increase significantly, resulting in IR drops in both wells and latch-up at a voltage well below a steady-state triggering voltage. A similar mechanism triggers a parasitic NPN transistor in LDMOS (Chap. 7). (c) Latch-Up Prevention Several process and layout techniques have been suggested to prevent latch-up in bulk CMOS with various degrees of attractiveness. They all center around two major approaches: reducing both lateral and vertical bipolar current gains and reducing the well resistances. Reduction of Bipolar Current Gains As discussed above, SCR action occurs only when the sum αp + αn  1 (or βp  βp  1). Thus, any process or design that reduces the gains reduces the latch-up susceptibility. If the sum αp + αn < 1, latch-up will not occur. Latch-up prevention could be achieved by reducing the minority-carrier lifetimes, hence diffusion lengths, in the CMOS structure to a point where the αp + αn < 1 [196]. So far, any attempt to reduce the lifetime by introducing recombination sites, such as heavy metals, into the wells or substrate also degraded the MOSFET performance and reliability [197], particularly when reducing the lateral bipolar gain. It may be possible, however, to locally reduce the lifetime by irradiation [198], but there is insufficient data on this approach. Retrograde wells allow an increase in well concentrations below the surface with little impact on the threshold voltage, reducing the lateral voltage drops [199–201]. The higher concentration also reduces vertical current gains by increasing the Gummel numbers (Chap. 5). Reduction of Well and Substrate Resistances The well resistances can be reduced by increasing the retrograde well concentrations and making frequent contacts to the wells. A common method to reduce the substrate resistance is to start with a P+-substrate and adjust the thickness of the P-epitaxial layer grown on it to sustain the maximum applied voltage. Even with a P+-substrate, the P-well resistance can become a problem in mixedsignal and RF applications that frequently use isolated NMOSFETs. Isolation requires encapsulating the NMOSFET with a deep N-well under the structure and a surrounding N-well merging with the deep N-well (Chap. 6). The deep N-well pinches the P-well (body), increasing its resistance. This can be a problem even for a single isolated transistor, if its width is sufficiently large, because the debiasing IR drop is a function of the distance between the gate and the body contact. In addition, when a large circuit block is isolated, the pinched P-well resistance can be very high, causing a large IR drop and forward-biasing the source-to-body junction, turning on the parasitic NPN. In either case, this results in a large fraction of the current being

598 Fig. 11.50 Example of a double guard ring consisting of P+- and N+-rings surrounding the transistor

11 Chip Reliability VDD

STI

P+ STI P-well

N+ STI N-well

P+ STI P-well

collected at the isolating N-well periphery rather than at the drain. Thus, it is critically important to have frequent close contacts to the gate in isolated NMOS and circuit blocks. Another factor to consider when analyzing latch-up is conductivity modulation of the wells and substrate at high-level minority-carrier injection, reducing the resistances and bipolar gains (Chap. 5). This results in an increase in both the trigger and holding currents [202]. Layout Solutions In many designs, the susceptibility to latch-up can be reduced by layout, during the design phase, with no or little added process complexity. An efficient way to inhibit latch-up in bulk CMOS is to surround the structure with guard rings to protect circuits from collecting injected carriers from surrounding circuits. Guard rings also protect surrounding circuits from collecting carriers injected by the MOSFET itself under certain bias conditions. If available, a heavily doped “N+-sinker” or a deep trench can act as an efficient guard ring [203–205]. Also, abutting source and MOSFET body contacts reduce latch-up susceptibility because of the reduction in the well resistance beneath the source [206, 207]. A typical latch-up solution in bulk CMOS is to place both N+- and P+-guard rings around internal cells and I/O circuits to collect both injected electrons and holes (Fig. 11.50). The guard rings must be sufficiently wide and their concentration sufficiently high to minimize “escapes” under the rings [206–208]. The N+-ring need not always be biased to efficiently protect against latch-up [209]. Standards for testing of latch-up susceptibility can be found in [210]. The tests should be done with both positive and negative currents forced through the input.

11.4.8 High-Voltage MOSFET Reliability The discussion of CMOS reliability in the preceding sections is also applicable to high-voltage MOSFETs. However, the high voltage and high current in LDMOS and DECMOS create new failure mechanisms not observed in digital CMOS. In particular, the presence of the lightly doped drift region creates effects not seen in digital MOSFETs (Chap. 7).

11.4

Failure Mechanisms

599

(a) Latch-Up in High-Voltage MOSFETs Integrating high-voltage, high-power transistors with low-voltage digital circuits can cause latch-up, e.g., by the injection of minority-carrier electrons into the substrate from a forward-biased N-well to substrate junction of the high-voltage transistor, such as when driving inductive loads (Chap. 7). Minority-carrier electrons can travel long distances in the substrate, above 1000 μm, before reaching other circuits. Similarly, holes can be injected laterally and vertically into the substrate when the P-body of the high-voltage transistor becomes forward-biased. While the N+-buried layer (NBL) under the N-well, such as in a high-side LDMOS, practically eliminates the vertical PNP current gain (and also reduces the N-well resistance), it has little influence on the lateral injection of holes into the substrate [199]. Injected holes drift through the substrate and create voltage drops that can trigger latch-up. Both the parasitic NPN action, with the well of the high-voltage transistor acting as the emitter, and the IR drop in the substrate induced by the injected hole current can be suppressed by using P-epitaxy over P+-substrate as the starting material. The P-epitaxy must be sufficiently thick to sustain the high voltage. As the P-epi thickness increases, however, the underlying P+-substrate becomes less efficient. This is why guard rings of the type shown in Fig. 11.51 must be placed surrounding the high-voltage transistor to collect both minority and majority carriers before they reach other circuits. To be more efficient, the N-well ring should merge into an N+-buried layer which is formed in conjunction with epitaxy, as shown in the figure. If space allows, double or even triple guard rings should be placed to eliminate latch-up. Deep trench isolation can offer substantial benefits for highvoltage guard rings. (b) Hot-Carrier Effects Hot-carrier stress conditions in high-voltage transistors are similar to those in CMOS. A high drain voltage of magnitude typically 10% above the operating voltage is applied, while the gate voltage is kept low, at a level that yields a Fig. 11.51 Guard ring configuration for highvoltage MOSFETs

VDD STI

P+ STI P-well

N+ STI N-well

P-epi 2 NBL P-epi 1

P+-substrate

P+ STI P-well

600

11 Chip Reliability

maximum body current. Shifts in VT, VDlin, VDsat, gm, and RDS(on) are then measured, from which the lifetime can be projected, similarly to CMOS. While in an NMOSFET only one body current peak is observed (Chap. 6), NLDMOS exhibits two peaks as a result of two different mechanisms. The first peak is related to the intrinsic MOSFET as described in Chap. 6. The second peak is due to the Kirk effect, discussed in Chaps. 5 and 7. In typical LDMOS, however, the source and body contacts are abutted and shorted by silicide to reduce the overall LDMOS area and the body resistance under the source. In this configuration, the body current cannot be separately measured. It can be inferred from simulations or extrapolation from measurements on specially designed structures. Instead of directly measuring the body current, the shifts in VT, VDlin, VDsat, gm, and RDS(on) are measured as a function of combinations of drain and gate voltages, the magnitudes of which can be varied between 0 and the maximum values mentioned above. Thus, conditions for a safe operating area can be established. The regions where hot carriers are injected and trapped are different in highvoltage MOSFETs than in standard CMOS. They also depend on the structure, in particular on the presence or absence of a field oxide, LOCOS or STI, under the gate covering the drift region. LDMOS transistors stressed at high gate and drain voltages show degradations of the on-state resistance, RDS(on) (or IDlin); the saturation drain current, IDsat; the threshold voltage, VT; and the transistor breakdown voltage, BVDSS. One of the most important parameters for many applications, such as current switches, is the stability of the on-resistance, RDS(on). The degradation of RDS(on) in NLDMOS is attributed to the hot-carrier-induced interface-state density due to the high surface field in and near the channel region and to hot-carrier trapping in the drift region [211–218]. The presence of interface states reduces the electron mobility, thus increasing the on-resistance. Depending on the measured structure and lateral field configuration, both electron and hole trapping at the surface of the N-drift region are observed. Electron charge depletes the N-drift surface, increasing RDS(on), while hole charge accumulates the surface, reducing RDS(on). The competing effects explain the change in the polarity of ΔRDS(on) with stress time [212]. Stressinduced hot-electron generation and trapping at the LOCOS “bird’s beak” facing the NMOS channel causes a substantial increase in RDS(on) [212–216]. Similar effects are observed with STI in the drift region [217]. Mobility degradation by stressinduced interface traps also decreases IDsat at high drain voltage, but the change appears to saturate with time [212]. In PLDMOS, trapped hot electrons accumulate the P-type drift region, reducing RDS(on) [215, 219]. Also, VT decreases and ID increases due to electron trapping in the channel [215]. Another hot-carrier issue which is typically observed in a high-side NLDMOS is a sudden increase in the saturation drain current above the expected level when impact ionization becomes significant. This increase is not only due to the collection of generated electrons by impact ionization. Most of the generated holes at the LDMOS drain diffuse and drift to the integrated source–body contact. The generated electrons drift to the drain contact causing an increase in drain current, ΔID, which is initially small compared to IDsat. When the drain voltage increases to a value where

11.4

Failure Mechanisms

601

impact ionization becomes significant, the IR drop caused by the hole current in the P-body of the MOSFET increases, locally forward-biasing the source-to-body junction. Consequently, the source injects electrons that are mostly collected by the drain, increasing ΔID. The forward voltage also decreases the MOSFET threshold voltage (Chap. 6), causing an additional increase in drain current. The problem becomes more severe as the substrate (body) contact and series resistances increase. (c) High-Temperature Reverse-Bias Stress, HTRB In many situations, a screen test is done prior to other reliability tests. Hightemperature reverse-bias (HTRB) stress is a common screen test for high-voltage MOSFETs. It consists of applying a high reverse voltage on the drain, slightly less than the maximum rated reverse breakdown voltage, with the source, gate, and body at ground. The stress is done at the maximum operating temperature of typically 150  C for a specific time, typically 1000 h on packaged units. For a faster screen test, the stress can be done at the wafer level for 1 h. The reverse leakage and the drain-to-source breakdown voltage, BVDSS, are measured at room temperature with the gate and substrate at ground before and after stress and then compared. A failure is defined at a certain percent change in one of the parameters, typically 10%. Because this test combines electric and thermal stress, it can be used to check junction leakage, crystal defects, or other weaknesses in interfaces and junctions. The leakage measured at the drain can also be monitored during stress. Another common screen test for high-voltage, high-power transistors is the hightemperature gate stress (HTGS), where a stress voltage is applied to the gate and a very small voltage is applied to the drain with the source and body at ground [210]. Both HTRB and HTGS tests simulate the operating conditions of a power switch. The device sustains the high voltage in the off-state (HTRB) and delivers the high power in the on-state at high gate voltage VG and low drain voltage VD (HTGS). The stress can be extended to alternating HTRB (off-state) and HTGS (on-state). (d) Unclamped Inductive Switching (UIS) Test In Chap. 3, we described how a damaging high voltage spike which is caused by unclamped inductive switching (UIS) can be suppressed by use of a PN junction or Zener diode clamp. Unclamped inductive switching is, however, an important reliability test of power MOSFETs. The ruggedness of a power MOSFET is defined as its ability to sustain a specified avalanche energy before being destroyed during unclamped inductive switching. It can be measured by a single UIS event or repetitive UIS operation [220]. The UIS test begins with a voltage pulse applied to the gate of the power MOSFET to turn it on (Fig. 11.52) [220, 221]. The pulse width is long enough to allow the current through the inductor to ramp up according to the inductance L and applied voltage Vapp (Fig. 11.53a).At the end of the pulse, the MOSFET is turned off, but the current in the inductor continues, causing the voltage across the MOSFET to rise sharply above Vapp, until the transistor reaches an effective breakdown voltage, BVeff (Fig. 11.53b). At that point, the current reaches a peak value IBV (Fig. 11.53c). After the pulse is turned off, the avalanche current, IBV, decays linearly at a rate

602

11 Chip Reliability

A Gate

Drain

Inductor, L B

Source

Gate Voltage

+ -

R

Vapp

Fig. 11.52 Unclamped inductive load test circuit for MOSFET ruggedness evaluation. (Adapted from [220]) Fig. 11.53 Single-event waveforms. (a) Idealized gate pulse. (b) Drain to source voltage, rising to BV. (c) Drain current peaking at IBV. (d) Power, peaking at PBV (Area of triangle is the dissipated energy)

VGS

(a)

ON

OFF Time

VDS BVeff

(b)

Vapp ID IBV

tAV

(c)

tAV

P PBV

Time (d)

tAV

BV eff  V app dI BV ¼ A=s dt L

Time

Time

ð11:76Þ

The peak avalanche power, PBV, is the product of BVeff and IBV. The average energy dissipated (absorbed by the MOSFET) is (Fig. 11.53d)

11.4

Failure Mechanisms

603

  1 1 2 BV eff J E ¼ PBV t AV ¼ I BV L BV eff  V app 2 2 where tAV is the average duration of the avalanche event given by t AV ¼

ð11:77aÞ

LI BV s BV eff

ð11:77bÞ

Two interacting mechanisms are believed to be responsible for the failure during unclamped inductive switching [221], namely, the parasitic bipolar transistor [222] and the thermal effect [223, 224]. The source, body, and drain of the MOSFET constitute a parasitic bipolar transistor, with the source as the emitter, the body as the base, and the drain as the collector. If the IR drop in the P-body (base) of an LDMOS is sufficiently high to forward-bias the source-to-body junction, the bipolar transistor turns on. The combination of high voltage on the drain (collector), IB, high body resistance, RB, and bipolar gain, β, can lead to a transistor breakdown similar to BVCEO (Chap. 5). The increase in local temperature reduces the emitter-base forward voltage, increases the gain β, and increases the base (body) resistance, RB, resulting in “hot spots” of thermal runaway and the destruction of the MOSFET, a failure mode often referred to as second breakdown [225]. If the parasitic bipolar transistor does not get activated, the rise in temperature eventually becomes the main cause of failure by creating “hot spots” of thermal runaway.As the dissipated energy increases, the junction temperature can rise so rapidly that heat sinks become irrelevant for UIS testing [222]. In this case, the avalanche failure current, IBV, decreases with increasing starting temperature and increasing inductance. Figure 11.54 shows an example of a single-event avalanche 80

Fig. 11.54 Example of avalanche failure current versus starting temperature for different inductor sizes. (Adapted from [221])

L(mH) 0.05 0.1

70

IBV (A)

60 50

0.3 40 1.0

30

3.0

20

10

10 0 0

25

50

75

100

125

Temperature (oC)

150

175

604

11 Chip Reliability

current versus the initial temperature for different inductor sizes. By varying the inductor size, the MOSFET avalanche current can be varied. The smaller the inductor and the starting temperature, the higher the current required to destroy the device. The values in the figure, however, should only be considered as a trend and not as absolute device ratings. (e) Temperature Cycling Stress Due to high currents in power transistors, IR drops in the metal can significantly increase the extrinsic resistance in series with silicon-based RDS(on). To reduce the metal resistance, the top sputtered aluminum, or the locally electroplated copper, is deposited at a thickness of at least 3 μm (Chap. 9). The mismatch in the temperature coefficient of expansion (TCE) between the metal and its surroundings can, however, lead to very high stresses in underlying layers. This can cause cracks or severe distortions of the layers during temperature cycling [226–228]. Temperature cycling stress involves cycling between low and high temperature, each dwelling for 1–15 min. The low temperature typically ranges from 0 to 65  C and the high temperature from 85 to 150  C. For example, automotive “Grade 0” applications typically require failure-free completion of 2000 cycles between 50 and +150  C [229]. Thus, the choice of metal and its thickness becomes a trade-off between reliability and performance (RDS(on)). To reduce stress, layout rules are implemented with, e.g., “keep-out” zones along die edges and corners and the use of stress-relief films, such as polyimide.

11.4.9 Electrostatic Discharge and Voltage Snapback During handling, components can be subjected to voltages well in excess of the maximum operating voltage of the component. The charge is created mainly by triboelectricity. For example, removing a chip from its plastic packaging material, or a person walking on a synthetic carpet, can generate 10–20 kV, depending on the moisture in air. The discharge of static electricity generated in the IC is referred to as electrostatic discharge (ESD). An ESD event can generate high voltages and currents in the chip, depending on the path the charge takes to dissipate. If not properly bypassed, an ESD event can immediately cause a catastrophic failure or result in latent damage which causes an early failure during the operating life of the circuit. Even with strict environmental control, charge build-up and high-voltage spikes can occur on the chip terminals, particularly on power pins. This is why on-chip protection is required on every pin. (a) Protective Devices The protective device should satisfy several conditions. Among them are as follows: 1. Provide a low-impedance path between each pin and the remaining pins to “sink” the ESD current.

11.4

Failure Mechanisms

605

A

ID

G

STI

VD

S

B STI

P+

D

h N+

e e

h RPW

P-substrate

STI

N+

Local forward bias

P-well

Impact ionization

Fig. 11.55 Grounded-gate (GGNMOS) NMOSFET biased in snapback mode. The schematic cross section illustrates the impact ionization at the drain and the bipolar action. A section of the drain is unsilicided to increase the series resistance

2. Clamp the voltage that appears on the component at a level that does not cause damage to the circuit to which it is connected. 3. Dissipate the charge in a short time (100–150 ns) without damaging the attached components, interconnects, or the protective device itself. 4. Only trigger during the ESD event, otherwise be inactive. 5. Fit in the allocated area and not appreciably increase parasitic resistances and capacitances. The most commonly used ESD protective device is the grounded-gate NMOS (GGNMOS) that operates in the snapback mode. The snapback mechanism is illustrated in Fig. 11.55 (Chap. 6). As VD increases, the two-dimensional field at the drain can become sufficiently high for electron-hole pair generation by impact ionization. Electrons drift to the drain and holes to the substrate and MOSFET body (P-well, B). The IR drop in the local resistance RPW raises the potential in a region under the source, locally forwardbiasing the source-to-P-well junction. The source injects electrons into the P-well which are collected at the drain (acting as the NPN collector) and subjected to the high field. Injected electrons multiply at the drain, further raising the P-well potential under the source. This is a regenerative feedback that results in transistor breakdown in a snapback mode as shown in Fig. 11.56a. The main problem with the large structures of the type in Fig. 11.55 is the nonuniform snapback where localized regions of the MOSFET snap back earlier than the others, carrying more current and heating up first, resulting in thermal runaway and creating current hogging and conducting filaments. Blocking silicidation along the drain increases the series

606

11 Chip Reliability

D

Second breakdown

ESD Protection Window

Vint

G

Current

Current

Sub

VDD

Vt2, It2

S

Snapback VH, IH

VH

Vt1

Vt1, It1

Voltage (a)

Voltage (b)

Fig. 11.56 (a) Typical I–V plot of grounded-gate ESD protective structure biased in snapback mode. (b) Safe ESD protection window

resistance seen by a filament, reducing the voltage across the filament as the current increases and limiting the current through the filament. This is believed to reduce the damage caused by nonuniform snapback. The negative resistance in Fig. 11.56 is mainly caused by an increase in the NPN bipolar gain as the current increases. The key points in the figure are the trigger voltage and current, Vt1, It1; the holding voltage and current VH, IH; and the voltage and current at the second breakdown, Vt2, It2, at which the structure fails. For the protective device to be efficient, Vt1 should be smaller than the internal circuit breakdown voltage, Vint (Fig. 11.56b). Even if this first condition is satisfied, a transient overvoltage created by, e.g., an unclamped inductor switch (UIS) can cause impact ionization whereby a large hole current turns on the parasitic NPN and triggers a destructive snapback. Thus, the snapback holding voltage, VH, should be larger than the MOSFET operating voltage, VDD, to avoid latch-up [211, 230, 231]. Achieving the safe ESD protection window is more difficult with LDMOS than for low-voltage CMOS. Techniques to increase the holding (sustaining) voltage in LDMOS are described in [232, 233]. (b) ESD Models and Test Standards The most common ESD models applicable to the manufacturing phase, including packaging, testing, and board assembly are as follows: 1. The human body model (HBM), which is intended to simulate a person being charged to a certain potential and then touching a pin with, e.g., tweezers, and discharging through the circuit to ground. 2. The machine model (MM), which simulates a charged manufacturing machine that discharges with little resistance through the circuit to ground. 3. The charged device model (CDM), which simulates a chip becoming charged and then discharging from a pin to a grounded metal surface.

Problems

607

Simulated body resistance 1.5kW Pin Switch V

Simulated body capacitance

Chip

100 pF Pin

Pulse voltage (%)

100 90

37

10 trise 15 ns

tfall 150 ns

(a)

Time (ns)

(b)

Fig. 11.57 (a) Human body model testing procedure. (b) Specification on test pulse rise and fall time

The test procedures for the HBM model and the associated pulse form are shown in Fig. 11.57 [234]. The current is first measured between one pin and another pin (Fig. 11.57a). The capacitor is charged to a starting voltage, e.g., 200 V, and then discharged into the pin through the 1.5-kΩ resistor, generating a pulse of the form in Fig. 11.57b. The current between the pins is measured again after discharge. The stress is repeated by incrementally raising the stress voltage until the protective device fails. The voltage protection is the stress voltage at which an increase in the measured current by, e.g., 20%, is observed. The procedure is repeated for positive and negative pulses applied between each pin and each of the other pins. Similar procedures are implemented for the MM and CDM models. A transmission line pulse (TLP) can also be applied for very short duration tests [235, 236]. TLP tests, however, may not always be suitable to analyze the holding voltage in snapback because the test does not take full account of self-heating during a real event [237]. An additional test at system level, referred to as IEC-61000, has been recommended by the International Electrotechnical Commission (IEC). The test is more stringent than the HBM test used for technology qualification.

Problems 1. A chip contains 500,000 identical components. If the failure goal is a constant hazard rate of 10 FIT, what is the maximum number of components that may fail after 1 year? 2. In one example, the nonconstant chip hazard function can be described by hðt Þ ¼ 1:8  107 t 0:8 (a) Find the chip FIT rate at 1 h and at 10,000 h. (b) Find the average FIT rate in the range 1–10,000 h.

608

11 Chip Reliability

3. The following plot approximates the capacitor dielectric breakdown field with a normal distribution. Estimate the probability that a capacitor will have a breakdown field less than 5 MV/cm. 0.35

pdf

0.30 0.25 0.20 0.15 0.10 0.05 0 4

5

6

7 8 9 10 11 Breakdown field (x106 V/cm)

12

13

14

4. Estimate the shape, scale parameters, and the MTF for the measured data in Fig. 11.10. 5. Ten devices were stressed to failure. The failure times in hours were found as 1275, 1875, 2175, 2325, 2700, 2900, 3075 3300, 3600, and 3780. Determine the distribution that best fits the data and estimate the device reliability at 4500 h. 6. Ten devices are stress-tested for a total time of 3000 h. The devices are found to fail at the following test times: 200, 800, 1000, 1700, 2800, and 2900 h. At 3000 h, four devices still operate. Fit the data to both lognormal and Weibull distribution functions. (a) Does the data fit one distribution better than the other? (b) At what time do the two distributions predict that 99% of devices will fail? (c) At what time does a system containing 100 such chips have a 50% chance of failing? Assume that the entire system fails when the very first chip fails. 7. An NMOSFET is stressed at 7.5 V where the peak substrate current is 30 times larger than at the normal operating voltage of 5.0 V. After a stress time of 1 h at 7.5 V, a 10% reduction in drive current was observed. How long would it take to see a 10% reduction in drive current at the use operation voltage of 5.0 V?

References 1. N.R. Mann, R.E. Schafer, N.D. Singpurwalla, Methods for Statistical Analysis of Reliability and Life Data (Wiley, New York, 1974) 2. P.D.T. O’Connor, Practical Reliability Engineering (Wiley, 1991) 3. A.G. Sabnis, VLSI reliability, in VLSI Electronics Microstructure Science, ed. by N. G. Einspruch, vol. 22, (Academic Press, 1981). J. F. Lawless, Statistical Models and Methods for Lifetime Data, John Wiley & Sons, 1982 4. W.C. Riordan, R. Miller, J.M. Sherman, J. Hicks, Microprocessor reliability performance as a function of die location for a (0.25 μm) five layer metal CMOS logic process. Proc. IRPS, 1–11 (1996) 5. C.G. Shirley, A defect model of reliability. Tutorial, IRPS (1995)

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Appendix A: Universal Physical Constants

Constant Avogadro’s constant Boltzmann constant

Symbol A0, NA, L k, kB

Electron rest mass Electron volt Elementary charge Energy equivalent of rest mass Gravitational acceleration Natural logarithm Permittivity in vacuum Pi Planck’s constant

m0 eV q, e g e ε0 π h

Planck’s constant/2π Speed of light Thermal energy Thermal voltage

h c kT kT/q

© Springer Nature Switzerland AG 2020 B. El-Kareh, L. N. Hutter, Silicon Analog Components, https://doi.org/10.1007/978-3-030-15085-3

Value 6.0225
1023/mol 1.3807
1023 J/K 8.6174
105 eV/K 9.1094
1031 kg 1.6022
1019 J 1.6022
1019 C 0.5110 MeV 9.9067 m/s2 2.7183 8.8542
1014 F/cm 3.1416 6.6261
1034 Js 4.1456
1015 eVs 1.0546
1034 Js 2.9980
108 m/s 0.02586 eV at 300 K 0.02586 V at 300 K

621

Appendix B: Properties of Silicon and Germanium Crystals (300 K)

Property Atomic number Atomic weight Atomic density Crystal structure Density Density of surface atoms (100) (110) (111) Dielectric constant Effective conduction band density of states Effective valence band density of states Effective electron massa Longitudinal (4.2 K) Transverse (4.2 K) Density of states (4.2 K) Density of states (300 K) Effective hole massa Longitudinal (4.2 K) Transverse (4.2 K) Density of states (4.2 K) Density of states (300 K) Elastic constants

Symbol

Unit g/mol cm3 g/cm3 cm2 cm2 cm2

Si 14 28.08 5.0
1022 Diamond 2.328

Ge 32 72.59 4.42
1022 Diamond 5.327 6.27
1014 8.87
1014 7.24
1014 16.0 1.04
1019

εSi NC

cm3

6.78
1014 9.59
1014 7.83
1014 11.7 2.80
1019

NV

cm3

1.04
1019

6.00
1018

kg kg kg kg

0.9163 m0 0.1905 m0 1.062 m0 1.090 m0

1.58 m0 0.082 m0

kg kg kg kg Pa Pa Pa

0.537 m0 0.153 m0 0.059 m0 1.15 m0 1.656
1011 0.639
1011 0.796
1011

0.28 m0 0.044 m0

m*

m*

c11 c12 c44

1.26
1011 0.44
1011 0.68
1011 (continued)

© Springer Nature Switzerland AG 2020 B. El-Kareh, L. N. Hutter, Silicon Analog Components, https://doi.org/10.1007/978-3-030-15085-3

623

624

Appendix B: Properties of Silicon and Germanium Crystals (300 K)

Property Electron affinity Electron diffusivity in pure crystal Electron mobility in pure crystal Energy gapb Hardness Hole diffusivity in pure crystal Hole mobility in pure crystal Index or refraction Interatomic distance Intrinsic carrier concentrationc Intrinsic Debye length Lattice constant Melting point Optical phonon energyd Optical phonon mean-free path Electrons Holes Poisson ratioe Pressure coefficient of Eg Specific heat Temperature coefficient of lattice mobility Electrons Holes Thermal conductivity Thermal expansion coefficient, linear Velocity saturationf Young’s modulus

Symbol χ Dn μn Eg H Dp μp n ni LD a0 tm Ep λ0

Unit V cm2/s cm2/Vs eV Mhos cm2/s cm2/Vs nm cm3 μm nm  C meV nm nm

ΔEg/Δp Δμn/ΔT

κ ΔL/ L
ΔT vs

eV/Pa J/gK cm2/ (VsK)

Si 4.15 36.2 1450 1.12 7.0 12.2 470 3.44 0.234 1.4
1010 24 0.543095 1412 63 7.6 5.5 0.28  1.5
1011 0.70

Ge 4.00 101 3900 0.664 49 1900 3.97 0.244 2.4
1013 0.68 0.564613 937 37 10.5 0.26 0.31

W/cmK K1

11.6 4.3 1.5 2.5
106

0.606 5.7
106

cm/s Pa

107 1.30
1011

107 1.03
1011

m0: Free electron mass ¼ 9.1091
1031 kg 4 2 T Temperature dependence of Si and Ge energy gap: Si, Eg ¼ 1:17  4:73
10 eV; Ge, E g ¼ Tþ651

a

b

4 2

T eV 0:7437  4:774
10 Tþ235 c Temperature dependence of Si and Ge intrinsic carrier concentration Si, ni ¼ 3.87
1016T3/ 2 7014/T e cm3; Ge, ni ¼ 1.76
1016T3/2e4553/T cm3 d This is the average energy loss per phonon scattering e When the ends of a straight wire of length ℓ and diameter d are pulled apart, the wire gets longer by Δℓ and thinner by Δd. The ratio, μ, of both deformations is called the Poisson ratio: μ ¼  Δd=d Δℓ=ℓ qffiffiffiffiffiffiffiffi 8E f Velocity saturation is defined as vs ¼ 3πmp0  107 cm/s

Appendix B: Properties of Silicon and Germanium Crystals (300 K)

625

Sources W.E. Beade, J.C.C. Tsai, R.D. Plummer, Quick Reference Manual for Silicon Integrated Circuit Technology (Wiley-Interscience, New York, 1985). Properties of Crystalline Silicon, R. Hull, Editor, EMIS Datareviews Series, No 20, INSPEC, London, 1999. M. Shur, Physics of Semiconductor Devices (Prentice-Hall, Englewood Cliffs, 1990). S.M. Sze, Physics of Semiconductor Devices (John Wiley and Sons, 1969). H. Wolf, Semiconductors (John Wiley and Sons, 1971).

Appendix C: Properties of SiO2 and Si3N4 (300 K)

Property Density Dielectric constant Dielectric strength Energy gapa Index or refraction Infrared absorption band Melting point Molecular density Molecular weight Poisson ratio Stress in film on Si Thermal conductivity Thermal expansion coefficient Young’s modulus

Symbol

Unit g/cm3

εox, εN Eg n tm

κ

V/cm eV μm C cm3 g/mol 

Pa W/cmK K1 Pa

SiO2 2.27/2.18 3.9 107 9 1.46 9.3 1700 2.3
1022 60.1 0.17 2–4
1010 0.014 5.6
107 6.6
1010

Si3N4 2.9–3.2 7.0–7.5 107 5 2.05 11.5–12.0 – – 140.28 9–10
1010 – – –

a

Electron volt (eV) is the energy required to move one electron through a potential difference of 1 V. 1 eV ¼ 1.602
1019 J (see Appendix D)

Sources W.E. Beade, J.C.C. Tsai, R.D. Plummer, Quick Reference Manual for Silicon Integrated Circuit Technology (Wiley-Interscience, New York, 1985). S.M. Sze, Physics of Semiconductor Devices (John Wiley and Sons, 1969). H. Wolf, Semiconductors (John Wiley and Sons, 1971).

© Springer Nature Switzerland AG 2020 B. El-Kareh, L. N. Hutter, Silicon Analog Components, https://doi.org/10.1007/978-3-030-15085-3

627

Appendix D: International System of Units, SI

Property Amount of substance Capacitance Conductance Energyb Electric charge Electric current Force Frequency Inductance Length Magnetic flux Magnetic flux density Mass Power Potential Pressure Resistance Temperature Time

Unit name Molea Farad Siemens Joule Coulomb Ampere Newton Hertz Henry Meter Weber Tesla Kilogram Watt Volt Pascal Ohm Kelvin Second

Symbol Mol F S J C I N Hz H m Wb T kg W V Pa Ω K s

Dimension C/V A/V Nm As C/s kgm/s2 s1 Wb/A m Vs Wb/m2 kg J/s J/C N/m2 V/A K s

a

A mole of a substance is the amount of substance which contains a specified number of atoms or molecules. This number is 6.0225
1023 and called Avogadro’s number. The gram-molecular weight of a substance is the number of grams per mole of the substance. For example, the grammolecular weight of carbon is 12 g b The energy of 1 joule is equivalent to 6.242
1018 eV

© Springer Nature Switzerland AG 2020 B. El-Kareh, L. N. Hutter, Silicon Analog Components, https://doi.org/10.1007/978-3-030-15085-3

629

Appendix E: The Greek Alphabet

Letter Alpha Beta Gamma Delta Epsilon Zêta Eta Theta Iota Kappa Lambda Mu

Uppercase Α Β Γ Δ Ε Z H Θ I K Λ M

Lowercase α β γ δ ε ζ η θ ι κ λ μ

Letter Nu Xi Omicron Pi Rho Sigma Tau Upsilon Phi Chi Psi Omega

© Springer Nature Switzerland AG 2020 B. El-Kareh, L. N. Hutter, Silicon Analog Components, https://doi.org/10.1007/978-3-030-15085-3

Uppercase Ν Ξ Ο Π Ρ Σ Τ Υ Φ Χ Ψ Ω

Lowercase ν ξ o π ρ σ τ υ ϕ χ ψ ω

631

Appendix F: Conversion Factors

Change of base loge(N ) ¼ ln (N ) ¼ loge(10)
log10(N ) Length 1 meter (m) 1 centimeter (cm) 1 micrometer (μm) 1 Angstrom (Å) 1 nanometer (nm) 1 inch (in.)

m 1 102

cm 102 1

μm 106 104

Å 1010 108

nm 109 107

in. 3.94
101 3.94
101

106

104

1

104

103

3.94
105

1010

108

104

1

101

3.94
109

109

107

103

10

1

3.94
108

2.54

2.54
104

2.54
108

2.54
107

1

cm2 104 1

μm2 1012 108

Å2 1020 1016

nm2 1018 1014

in.2 1.55
103 1.55
101

108

1

108

106

1.55
109

1016 108

1

102

1.55
1017

1014 106

102

1

1.55
1015

2.54
102

Area m2 1 square meter (m ) 1 1 square centimeter 104 (cm2) 1 square microme- 1012 ter (μm2) 1 square Angstrom 1020 (Å2) 1 square nanometer 1018 (nm2) 1 square inch (in.2) 6.45
104 2

6.45

6.45
108 6.45
1016 6.45
1014 1

© Springer Nature Switzerland AG 2020 B. El-Kareh, L. N. Hutter, Silicon Analog Components, https://doi.org/10.1007/978-3-030-15085-3

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634

Appendix F: Conversion Factors

Energy 1 joule (J) 1 electron volt (eV) 1 kilogram (kg) 1 calorie (cal)

J 1 1.6
1019 8.99
1016 4.19

eV 6.24
1018 1 5.61
1035 2.61
1019

kg 1.11
1017 1.76
1036 1 4.66
1017

cal 0.24 3.83
1020 2.15
1016 1

Pressure 2

Dyne/cm2 1 10

1 dyne/cm 1 newton/m2 (Pa) 1 atmosphere 1.01325
106 (atm) 1 bar 1.0
106 1 pound/ 6.8946
104 square in. (PSI)

Pa 0.1 1

atm 9.862
107 9.862
106

1.01325
105 1

bar 106 105

PSI 1.4504
105 1.4504
104

1.0133

14.696

1.0
105 0.98692 1 14.504 1.01325
103 6.8946
102 6.8948
102 1

Periodic Table of the Elements

© Springer Nature Switzerland AG 2020 B. El-Kareh, L. N. Hutter, Silicon Analog Components, https://doi.org/10.1007/978-3-030-15085-3

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636

Periodic Table of the Elements

Index

A Accelerated life test, 545 Accelerated testing, 545 Acceleration factor, 545 Accumulation, 227–229 AC–DC converter-flyback, 377–378 Acoustical phonons, 49 Activation energy, 563 Active base, 166 Amorphous, 25 Analog CMOS, 13, 18–19, 222 applications, 293–297 buried channel and depletion-mode MOSFETs, 296–297 current mirror, 294–295 differential amplifier, 293–294 native NMOS transistors, 296 Analog CMOS process, 456, 476 buried-channel PMOS, 477–479 buried (subsurface) Zener diode, 484 depletion-mode NMOS, 477 high sheet poly resistor, 479 HV analog CMOS transistors, 476 JFET, 479, 480 native NMOS, 477 poly–insulator–poly capacitor, 482–484 thin-film resistors, 481–482 Analog mindset, 12 Analog product diversity, 10 Analog-to-digital converter (ADC), 6, 14, 437 Annealing, 452 RTA, 452 Applications, 436 Auger recombination, 57–58

Avalanche breakdown, 95 voltage, 95, 96 vs. Zener breakdown, 96–97

B “Back-end” contact resistance, 143 Back-end of the line (BEOL), 459, 582 aluminum, 459–461 borophosphosilicate glass (BPSG), 460 copper, 461–462 dual damascene, 461 fluorinated silicate glass (FSG), 461 high-density plasma (HDP), 461 inter-metal dielectric (IMD), 460 low-κ IMD, 462 phosphosilicate glass (PSG), 460 Band diagram, 225, 227, 228 SBD, 119, 136 Band model, 28 impurities in silicon, 37–40 Band-to-band recombination, 55 Band-to-band tunneling, 245–246 Barrier height extraction, SBD, 125–129, 131–134 Barrier lowering, SBD, 122–123 Base, 152 conductivity modulation, 172 emitter recombination current, 163–164 extrinsic, 169 intrinsic, 169 push-out effect, 173–175 resistance, 169, 200 transport factor, 155

© Springer Nature Switzerland AG 2020 B. El-Kareh, L. N. Hutter, Silicon Analog Components, https://doi.org/10.1007/978-3-030-15085-3

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638 Base (cont.) width, 152, 154, 160, 173–175, 185, 187 width modulation, 176 Bathtub curve, 543–544 Bias temperature instability (BTI), 585 acceleration, 585 NBTI, 585–587 PBTI, 587 Bipolar CMOS (BiCMOS), 18, 22 Bipolar-CMOS-DMOS (BCD), 19–21, 308, 335, 484, 485 Bipolar junction transistor (BJT), 12, 18, 151, 153, 200, 469 high-performance bipolar transistor, 470–471 low-complexity bipolar transistor, 469–470 Body-bias effect, 251, 260 Boltzmann approximation, 32 Boltzmann distribution, 30 Boltzmann factor, 31 Boltzmann’s constant, 30 Breakdown voltage, 95, 96 effect of curvature, 95 effect of temperature, 95–96 Buck switching converter, 375 Built-in field, 52 Built-in voltage, 74, 75 SBD, 116 Bulk charge per unit area, 230 Bulk Fermi potential, 38 Buried channel and depletion-mode MOSFETs, 296–297 Buried-channel PMOS (BC-PMOS), 19, 268, 269, 270 process, 477–478 Buried Zener diode process, 484 Burn-in, 543

C Capacitor, 413 applications, 438–439 dielectric absorption (DA), 417–418 dielectric strength, 415 dimensions and capacitance components, 414–415 lateral capacitance, 415 lateral flux capacitor (LFC), 423–424 leakage, 415–416 metal–insulator–metal (MIM), 421–424 metal to silicided poly, 421–422 MOS, 418–420 poly–insulator–poly (PIP), 420–421

Index quality factor (Q), 418 strength, 415–416 temperature coefficient of capacitance (TCC), 416–417 voltage coefficient of capacitance (VCC), 416 Capacitor dielectrics, 565 dispersion, 583 high-κ, 566 inter-level dielectric (ILD), 566 inter-metal dielectric (IMD), 566 low-κ, 566–568 LPCVD oxide, 565 nitride oxide, PNO, 565 PECVD nitride, PEN, 565–566 PETEOS, 585 Capacitor processes, 473–476 lateral flux, LFC, 473 MIM vertical, aluminum, 473–474 MIM vertical, copper, 474–475 Carrier lifetime, 54–55 Central processing unit (CPU), 1, 9 Centroid, 499 Channel, 152, 203 Channel length modulation (CLM), 255–256 Channel resistance, 311 Charge neutrality level (CNL), 118 Charge pump, 438 Charge storage, 123 Charge to breakdown, 561 Chemical–mechanical polishing (CMP), 453, 461 CMOS, 3 logic technology, 15 Collector, 152 resistance, 170, 192, 198 reverse-bias effect, 175 Collisions, 42 Common centroid, 499–500 Component set comparison, 449 Computed tomography (CT) scanner, 5–7 Conductance, 269, 294 Conductance and drain, 283 Conduction band, 29 Conductivity, 44 modulation, 105 Contact chain, 145–146 Contact potential, 73 Conversion factors, 633–634 Copper, 575 bamboo structure, 576 BEOL, 461–462, 575 corrosion, 576

Index electromigration MTF, 574 electroplating, 604 low-κ ILD, 575 Coulomb scattering, 45 Covalent bond, 26 Critical field (Ec), 96, 309, 317, 318, 320, 342, 366 Cross-bridge Kelvin test structure, 144–145 Cross-coupled configuration, 499 Cumulative distribution function (CDF), 541, 547–549, 551, 553 Current hogging, 172 Current mirror, 294 Current–voltage characteristics, 119–120 C-V profiling, 131 C-V technique, 233–238 Cylindrical edge approximation, 70, 80 breakdown voltage, 95, 96

D Damascene, dual damascene, 461 DC–DC converter, 329, 338, 370, 374 buck converter, 374 conduction loss, 374, 376 efficiency, 377 power loss, 329, 372, 375 switching loss, 376, 377 DECMOS process, 468, 491 Decoupling capacitor, 438 Deep depletion, 231, 234, 243 Deep submicron and nanoscale MOSFETs FinFETs, 290–292 mobility enhancement techniques, 285–289 ultrathin oxide and high-κ dielectrics, 289–290 Deep trench isolation (DTI), 455–456, 557 DENMOS, 468 Density of states, 31, 32 Depletion approximation, 70, 71 boundary, 78, 85, 98 region, 67, 72, 75, 78, 80, 87, 89, 90–92, 129 width, 67, 70, 75, 76, 81, 88, 91, 95, 117, 228 Depletion-mode NMOS–process, 477 DEPMOS, 468 Dielectric absorption (DA), 8 Dielectric constant, 78 Dielectric reliability, 556–557 Differential amplifier, 293–294 Diffusion, 34, 41 Diffusion current, 51

639 Diffusion leakage current, 92 Diffusion length, 58–60, 153, 154, 156, 165, 166 Diffusivity, 51, 68, 166 Digital CMOS process–BEOL, 459–462 Digital design, 3–5 Digital signal processing (DSP), 6 Dispersion, 565 Doping, 34 acceptors, 35, 36 compensation, 38 donors, 34 Drain-extended CMOS, 468–469 Drain-extended MOS (DEMOS) asymmetric, 332 complementary, 330–331 DEPMOS, 331 dielectric RESURF, 333–334 field-gap, 309, 331 key dimensions, 334–335 laterally graded, 340, 341 planar, 330 RSP vs. BVDSS data, 323, 335 symmetric style, 332 Drain-induced barrier lowering (DIBL), 275 Drain-to-source resistance (RDS(on)), 309, 310– 314, 321, 324, 327, 329, 334, 342, 363 components, 312 effect of VGS, 313 measurement technique, 311 DRAM half-pitch, 267 Drawn dimensions, 391 Drift, 41, 42, 47 Drift current, 51, 59 Drift region, 309, 309 on-resistance, 310 on-state analysis, 310 Drift velocity, 42, 43 Dual-gate oxide, 466 Dummy components, 499 Duty cycle, 379, 563 Dynamic element matching, 13

E Early failure rate (EFR), 543 Early voltage, 176, 177, 210 Effective density of states, 32 Effective mass, 42 Effective oxide charge, 227 Effective Richardson constant, 120 Einstein relation, 53 Electromigration (EM), 568

640 Electromigration (EM) (cont.) acceleration factors, 570–571 aluminum, 569 bamboo effect, 569–570 Black’s equation, 569, 570 Blech effect, 574 Blech length (Lc), 574 contacts and vias, 573–574 copper effect, 570 current acceleration factor, 570, 571 current density specifications, 571–572 effect of Cu, 570 electron wind, 568 grain boundary, 569 MTF, 569 redundant metal films, 572–573 temperature acceleration factor, 570 test, 551 triple point, 569–570 Electron affinity, 116, 223 Electrostatic discharge (ESD), 604 charged device model (CDM), 606 grounded-gate NMOS (GGNMOS), 605 human body model (HBM), 606 machine model (MM), 606 models, 606–607 protective devices, 604–606 system-level test, 607 TLP test, 607 Electrostatic potential, 52 Emitter, 154 resistance, 168, 198 Energy gap, 29, 36 Energy-gap lowering, 164–165 Energy harvesting, 136 Epitaxial-collector transistor, 191–192 Epitaxial layer, 450 Epitaxy process, 485–487 Equivalent oxide thickness (teq), 236–238 Etching, 452 plasma, 452 Exponential distribution, 546 Extraction of barrier height, 125–126, 131–134 Extraction of contact resistance, 140–141 Extraction of teq, 236–238 Extrinsic resistance, SBD, 122

F Failure, 539 Failure in time (FIT), 544 Failure mechanisms, 556 Failure probability function, 540, 542 Failure rate, 541–542, 546, 552 Fermi–Dirac distribution, 31

Index Fermi level, 31, 116 Fermi-level pinning, 118 Fermi potential, 39, 40, 116, 223 Field ionization, 97 FinFETs, 290–292 Flatband, 222 Flatband capacitance, voltage, 234–235 Fluorinated silicate glass (FSG), 556 Flyback diode, 103 Forward active mode, 154, 155, 159–160, 173 Forward biased junction, 81 bias voltage, 82, 83 current, 83 saturation current, 84 series resistance effects, 84–86 Forward-biased, SBD, 120–122 Foundries, 14 Freewheeling diode, 103 Frequency response, 186 epitaxial-collector transistor, 191–193 graded base, 194–196 interfacial oxide, 197–198 polysilicon emitter, 196–197 selectively implanted collector, 193–194 SiGe base, 196 Frictional forces, 43

G Gain-bandwidth product ( fT), 188 Gate charge, 328, 329 figure of merit, RDS(on)  QG, 329 gate capacitances, 326 measurement technique, 327 Miller Plateau, 328 Gate dielectric reliability, 557 1/E model, 562 accelerated stress-test, 559 body current, 600 carrier transport through oxide, 557–558 charge to breakdown (QBD), 561 direct tunneling, 559 E-model, 562 Fowler–Nordheim tunneling, 558 intrinsic failure mechanism, 562 LDMOS, 600 Gate-induced drain leakage (GIDL), 241, 242 Gate overdrive, 231 Gate oxide integrity (GOI), 561 guard rings, 598 Gate stack, 456–457 Gauss’s law, 72 Generation, 27, 28, 54, 56 Graded base, 194–196 Gradual channel approximation, 254

Index Grain, 25 Grain boundaries, 25 Grounded-base current gain, 156 Grounded-emitter current gain, 156 Guard ring, 130, 131 Gummel number, 84, 154, 160, 167, 177 Gummel plot, 163

H Half H-bridge, 370 Halo, 276 H-bridge, 339, 370, 371 High doping effects, 164 High field effects, 48 High-frequency NLDMOS process, 487 High-level injection effects, 168, 172 High-performance bipolar transistor figure of merit, 190 frequency response, 190 tradeoffs, 190 transistor resistances, 198 High-resistivity silicon, 48 High-voltage CMOS (HVCMOS), 14 process, 465 High voltage MOSFET reliability, 598 high-temperature gate bias (HTGS) test, 601 high-temperature reverse-bias (HTRB) test, 601 hot carrier effects, 599–601 intrinsic failure, 562 Kirk effect, 600 latch-up, 599 LDMOS, 597, 600 on-resistance, 600 percolation model, 562 ramped voltage test, 560–562 specific on-resistance stability, 600 stress-induced leakage current (SILC), 559–560 temperature coefficient of expansion (TCE), 604 temperature cycling, 604 time-dependent dielectric breakdown (TDDB), 552, 561, 562 Hole, 28 Hole lifetime, 57 Hot carrier, 50 Hot-carrier distribution, 262 Hot-carrier injection, 262 Hot carrier reliability, 577 band diagram, 580 bipolar junction transistor, 578

641 buried-channel PMOS, 583 channel, 579 CMOS, 578–579 electron temperature, 581 gate current, 579–580 inverter switching, 582 lifetime prediction, 581 lightly-doped drain (LDD), 579, 584 lucky electron model, 580–581 Maxwell distribution of electrons, 577 PN junction, 577–578 process and design solutions, 584 pulsed stress lifetime, 582–583 substrate current, 579 substrate hot electrons, 583–584 walkout effect, 577

I Ideality factor, 122, 125 Idealized NPN transistor, 159 Image-force barrier lowering, 122 Impact ionization, 94, 243, 348, 358 Inductive switching, 368 Inductor, 16 process, 474 Inductor, spiral, 432 applications, 439–440 design guidelines, 434–435 eddy current, 434 inductance, 433 proximity effects, 434 self-resonance, 433 skin effect, 434 Injection ratio, 123, 124, 155 for electrons, 83 for holes, 84 Integrated device manufacturer (IDM), 14 Interface states, 88, 117–118 Interface traps, 88 Interfacial oxide, 197–198 Intermediate states, 56 International Electrotechnical Commission (IEC), 607 International system of units (SI), 629 International Technology Roadmap (ITRS), 21 Internet of things (IoT), 1 Intrinsic carrier concentration, 30, 39, 223, 242 Intrinsic energy level, 32 Intrinsic failure rate (IFR), 543 Intrinsic MOSFET, 311, 347, 350, 351, 353, 358, 365, 367 Intrinsic silicon, 28, 30, 32, 33, 39

642 Intrinsic voltage gain, 8 Inverse area law, 501–506, 509, 520 Inversion charge, 230 Inverter, 4 Ion implantation, 451 Ionization energy, 36 Ionized-impurity limited mobility, 46 Isolated-drain NLDMOS process, 487 Isolated NMOS, 15, 16 process, 466 Isolation module, 453–454 DTI, 455 LOCOS, 454 STI, 455

J Joule heating, 587 Junction capacitance, 77–78, 88 junction edge, 67, 79 reverse-biased, 88, 90 Junction contact resistance, 85 Junction curvature effect, 80, 95 Junction depth, 67 Junction field-effect transistor (JFET), 19, 151, 202 application, 213–214 channel-length modulation, 211 in CMOS technology, 211 early voltage, 211 effect, 312, 313, 354, 355 gate-leakage sources, 211 linear mode, 204 modulation factor, 209 pinch-off, 206 process, 478 saturation conductance, 209 saturation mode, 207 saturation transconductance, 211 thermal equilibrium, 203 Junction radius of curvature, 80 Junction series resistance, 85–87

K Kelvin test structure, 144–145 Key point, 309 Kirk effect, 172, 174, 190, 350, 353, 359

L Latch-up, 592–598 CMOS, 595–596

Index forward-biased junction, 595 guard rings, 598, 599 holding current, voltage, 593 inverter, 596 layout solutions, 598 LDMOS, 597 mechanism, 593 parasitic NPN, 597 prevention, 597 reduction of bipolar gain, 597 reduction of well resistances, 597–598 Shockley diode, 593 silicon-controlled rectifier (SCR), 592–593, 595 substrate resistance, 597 transient triggering, 596 trigger current, voltage, 593 well resistance, 596 Lateral double-diffused MOS (LDMOS), 20, 307, 330, 335, 449, 484 graded channel doping, 340 high side NLDMOS, 338 impact ionization, 348, 358 integrated body contact, 343 isolated drain NLDMOS, 338 key dimensions, 343 low side NLDMOS, 335 on-state breakdown voltage, 360 parasitic NPN, 359, 367, 374 PLDMOS, 340 reverse recovery, 371–374 RSP vs. BVDSS data, 346–347 self-heating, 348, 352, 361, 374 snapback, 359 snappy recovery, 374 superjunction, 341, 343 temperature effects, 361–367 Lateral flux capacitor (LFC), 16 process, 473 Lateral PNP, 185 Lattice constant, 26 Layout configurations, 499 common-centroid, 499–500 cross-coupled, 499 interleaved, 500 parallel, 499 Leakage current, 241 generation, 90 Lifetime, 539 Light-emitting diode (LED), 20 Linearization, 5 Linear mode, 5 Line-edge roughness (LER), 506

Index LOCOS, 454–455 Lognormal distribution, 546, 549–551 Lognormal plotting, 551–552 Low-complexity NPN, 162 Low-cost NLDMOS process, 487, 488 Low dielectric absorption capacitors, 18 Low-level injection, 55, 82, 167 Low-noise amplifier, 200 Low-voltage analog CMOS process, 465–466 Low-voltage CMOS (LV CMOS) logic technology, 15

M Maximum frequency of oscillation ( fmax), 189–190 Mean, 547 Meander resistor, 392 Mean time to fail (MTTF), 541, 546, 550 Median, 547 Median rank, 551 Median time to fail (MTF), 541, 546, 553 MESFET, 137 Metal-induced gap states (MIGS), 117 Metal–insulator–metal (MIM) capacitor, 8, 78 in aluminum BEOL, 473–474 in copper BEOL, 474, 475 Metallurgical junction, 66 Metal–semiconductor barriers, 114 Metal to silicon contact, 115, 118 Minority-carrier injection, 54, 82, 123–124 Minority-carrier lifetime, 55 Minority carriers, 35–36, 54–57 Mismatch, 496 bipolar transistor, 506–508 capacitor, 510–512 centroid, 499 common centroid, 499–500 constant, 501 cross-coupled, 499 current mirror, 527–528 floating gate measurement, 511, 512 global, 495 halo implant, 505 inverse-area law, 505 layout effects, 498 limitations of Pelgrom’s law, 505 line edge roughness, 505, 506 local, 496 metal coverage effect, 498 MOSFET, 501–506 parallel, 499 proximity effects, 497

643 random, 495, 496, 497–499 resistor, 499, 508–509 standard deviation, 496, 502, 508, 509, 530 STI proximity effect, 497 systematic, 496–497 threshold voltage, 502–504 well proximity effect, 497 Mixed-signal CMOS (MS-CMOS), 13, 15–16 process, 448, 462 Mobility, 43–46, 349 drift, 41 field dependence, 49 ionized-impurity scattering, 45 lattice scattering, 45 Matthiessen’s rule, 46 plots, 46–48 temperature dependence, 47 Mobility enhancement techniques, 285–289 Mobility, surface, effective, 251, 252, 253 degradation, 249 effective, 251, 253, 254 electron, 253 empirical relationships, 253 hole, 254 inversion, temperature dependence, 252 inversion universal, 254 surface, 251, 252 surface field, 256 Modular CMOS process, 448 MOSFET, 3, 137, 222 band-to-band tunneling, 245–246 body-bias effect, 251, 260 buried-channel, 268, 269, 270 capacitances, 282 defect-induced leakage, 242–243 depletion-mode, 268, 296 drain-induced barrier lowering, 275 enhancement-mode, 240 extrinsic capacitances, 283 extrinsic resistances, 261 frequency at unity gain, 282 GIDL, 241, 242 halo implant, 276 ID–VG characteristic, 241 impact ionization, 243–245 intrinsic resistances, 260 isolated NMOS, 265 leakage, 242, 246 linear conductance, 251 linear mode, 251 linear transconductance, 252 maximum oscillation frequency, 283 moderate inversion, 250

644 MOSFET (cont.) multiple threshold, 265 narrow-channel effects, 240, 273, 281 native, 268, 295 NMOS, 238 normally-off, 239 normally-on, 268 off-current, 275 output resistance, 209, 273 PMOS, 239 punch-through voltage, 275 reverse narrow-channel effect, 281–282 reverse short-channel effect, 280 saturation conductance, 209–211 saturation region, 254 saturation transconductance, 257–260 short-channel effect, 272–278 snapback, 278, 280 strong inversion, 229–230, 250 substrate current, 262–264 subthreshold region, 247–250 subthreshold transconductance, 249 surface-channel, 239 threshold voltage, 229 transit time, 282 velocity overshoot, 278 velocity saturation, 278 weak inversion, 229 MOS structure, 222 C–V technique, 233–238 energy band diagram, 223 flatband, 234–235 Multiplication factor, 182 Multiplication range, 95

N Narrow-channel effects (NCE), 281 Native NMOS, 267, 268, 296 process, 476 transistors, 296 N-buried layer (NBL), 336, 485–487, 489 Neutrality level, 118 NJFET, 153, 202 NLDMOS, 485 epitaxy process, 485, 487 high-frequency, 487 high-side (HS), 485 isolated, 489 low complexity process, 487–488 low-side (LS), 485 non-epi process, 487

Index NMOS, 3 Noise, 513 1/f in BJT, 524–525 1/f in CMOS, 518–523 1/f in JFET, 525 1/f in resistors, 509, 523–524 base current, 525 collector current, 526 corner frequency, 516 current, 513 drain current, 519–521 effect of fluorine, 521–523 effect of hydrogen, 521–523 effect of metal coverage, 498 effect of nitrogen, 521–523 effect of STI, 522–523 flicker 1/f, 513, 518 fluctuation, 513 generation-recombination, 515 Hooge’s constant, 523 input referred, 519–522 Lorentzian, 547 mobility fluctuation, 495, 504, 513 normalized drain current, 521 number fluctuation, 513, 520 power spectral density (PSD), 513, 516, 521 random telegraph signal, 516–517, 523 resistance equivalent, 514 shot, 514, 515 temperature equivalent, 514 thermal, 514 tunneling attenuation length, 519 in two stage transconductance amplifier, 528–530 voltage, 513 white, 514 Non-equilibrium condition, 53 Non-ohmic behavior, 403, 404 Non-uniform doping concentration, 52 Non-volatile memory (NVM), 20, 560 Norde method, 128 Normal (Gaussian) distribution, 546–549 N + P junction, 77 NPN transistor, 152, 157 in CMOS, 162–163

O Off-current, 4, 275 Off-state, 310, 315, 329 Ohmic contact, 113, 137 On-current, 4

Index On-state, 310, 328, 341, 352, 355 Operating voltage (VOP), 9 Operational amplifier (Op-amp), 6 Optical phonons, 49 Output resistance, 8, 176 Oxidation, 451

P Parasitic capacitances, 397 Parasitic PNP transistor, 172 P-buried layer (PBL), 338, 448, 485, 490 Peak field, 73, 94, 117, 123 Pelgrom law, 506 Phonon, 49 Photocurrent, 106 Photodiode, 106, 107 Photolithography, 450–451 Pinch-off, 206 Pinch-off voltage, 254–255 PIN diode, 104–106 conductivity modulation, 105 forward biased, 105–106 quantum efficiency, 106 reverse-biased, 106–107 PJFET, 153, 202 Planarization, 453 CMP, 453 Plasma, 586 antenna effect, 590–591 charge, 589, 590 damage, 589, 590 MIM capacitor, 591 MOSFET, 591 protection, 591–592 protective diode, 591 reactor, 589 sheath, 589 Plating, 453, 462 PLDMOS process, 490, 491 PMOS, 4 PN junction, 65 PN product, 33 PNP transistor, 152, 157 in CMOS, 185 Poisson relation, 75 Polycrystal, 25 Poly–insulator–poly (PIP) capacitor, 8 process, 483 Poly resistor, 397 band diagram, 399 carrier transport mechanisms, resistivity, 398 current density effects, 406–407 effective carrier concentration, 398, 399

645 effective carrier mobility, 399, 400 electrical dimensions, 400–403 electrical trimming, 406 end resistance, 403 energy-band diagram, 399 free carrier concentration, 398, 399 non-ohmic behavior, 403 parasitic capacitance, 407–409 resistivity, 400 sheet resistance, 400 structure, 398 temperature coefficient of resistance (TCR), 403–404 transport mechanism, 398 voltage coefficient of resistance, 404–406 Polysilicon depletion, 237 Polysilicon emitter, 196, 197 Polysilicon, silicon resistors, 471–472 high sheet resistor process, 481 Population, 540 Power law model, 554, 555, 581, 585 Power spectral density (PSD), 513, 516, 521 Probability density function (PDF), 540, 549, 552 Process delivery kit (PDK), 12 Process integration flow, 447 Pulse-width modulation (PWM), 371 Punch-through, 180, 275

Q Quality factor (Q), 16 Quantum efficiency, 106 Quasi-Fermi level, 120 Quasi-saturation, 348, 350, 359 JFET effect, 352 Kirk effect, 350 velocity saturation, 350

R Radio-frequency CMOS (RF-CMOS), 13, 16 Ramped voltage test, 560 Recombination, 28, 54–58 Auger, 57–58 rate (U), 57 Rectifying contact, 113 Reliability function, 540 Reliability models, 545 exponential, 546 lognormal, 549–552 normal, 546–549 power law, 554–556 Weibull, 552–554

646 Resistance extrinsic, 260–262 intrinsic, 260–262 spreading, 261 Resistivity, 44 Resistor, 389 applications, 436–439 body, 389 effective dimensions, 391 electrical dimensions, 391 end resistance, 390, 392, 403 head resistance, 390, 392 Joule heating, 394 linearity, 396 parasitic capacitances, 397 polysilicon, 397 resistance linearity, 396 self-heating, 394, 396 sheet resistance, 391 silicon, 410 temperature coefficient of resistance (TCR), 392 thermal conductivity, 394 thermal resistance, 395 voltage coefficient of resistance, 404 Resistor reliability, 587 high, low, medium sheet resistances, 587 poly resistor, 587–588 thermal resistance, 588 thin-film TFR, 588–589 Resonant circuit, 377 RESURF, 318, 319, 321, 322, 333, 343, 345, 366 charge balance, 320, 323, 334 dielectric, 333, 342 double, 321 sensitivity to drift layer thickness, 320 sensitivity to substrate doping, 321 single, 319 SOI, 344–346 triple, 323 Reverse active mode, 158 Reverse biased junction, 88 capacitance, 88, 89 depletion region, 89 leakage current, 90–93 Reverse-biased SBD, 129–131 Reverse narrower-channel effects (RNCE), 281 Reverse recovery, 371, 373 Reverse recovery time, 97–100, 172 Reverse short-channel effects (RSCE), 279 RF BiCMOS, 16 RF CMOS, 221

Index process, 448, 462 RF mixer, 135–140 Richardson constant, 120 Roadmap, 21

S Safe operating area (SOA), 360, 362, 363, 367–369, 374 commutating, 374 electrical, 367 electro-thermal, 368–369 forward bias, 374 reverse bias, 374 snappy, 374 temperature compensation point, 369 Sampling, 540 Saturation current, 125 SBD, 125 Saturation voltage (VCEsat), 161 Scale parameter, 549, 553 Scattering, 42 Schottky-barrier diode (SBD), 113 applications, 134 clamp, 134–135 CMOS, 137 energy harvesting, 136 RF mixer, 135–136 Schottky-barrier lowering, 122–123 Selectively implanted collector (SIC), 193 Self-heating, 394, 396 Series resistance, 126 Shallow trench isolation (STI), 67, 455 Shape parameter, 553 Sheet resistance, 391, 508 Shockley–Read–Hall (SRH) process, 56 Shockley’s relation, 83 Short-channel effects (SCE), 272–278 Si3N4, properties of, 627 Signal chain, 2 Silicidation, 452–453 Silicide block, 16 Silicon and germanium crystals, 623–624 Silicon–Germanium (SiGe) base, 196 Silicon-on-insulator (SOI), 344 advantages, 345 double RESURF, 346 NLDMOS, 345 PLDMOS, 346 Silicon resistor, 410 process, 471–472 source and drain, 410

Index temperature-coefficient of resistance (TCR), 403, 404 voltage coefficient of resistance (VCR), 404 well, 410 Single crystal, 25 SiO2, properties of, 627 Small signal model, 7 Small-size effects, 272 Snapback, 604 Snubber diode, 103 Snubber diode-AC–DC converter, 377 Soft breakdown, 560 Source–drain module, 458–459 Source, JFET, 151 Space charge, 67 Specific contact resistance, 139 Specific on resistance (RSP), 311, 324, 325, 329, 334, 335, 336, 339, 341, 367, 370, 377 DENMOS vs. BVDSS, 334 ideal, 324, 326 NLDMOS vs. BVDSS, 345 PLDMOS, 339 superjunction, 341 Spherical edge approximation, 69 Standard deviation, 547, 549, 550 Standard normal distribution, 547, 548 Starting substrate, 450 Statistical process control (SPC), 546 Step junction, 70–71 band diagram, 73–74 built-in voltage, 74–75 capacitance, 78–79 depletion width, 76–77, 79 effect of curvature, 80 electric field, 71–72 forward bias, 81 junction capacitance, 77–78 parallel-plate capacitance, 77 peak field, 73 Storage delay time, 99 Stress-induced leakage current (SILC), 559–560 Stress-induced voiding, 568, 575 Stress migration, 568, 574–575 Strong inversion, 229–232 Substrate, 450 Substrate current, 262–264 Substrate PNP, 187 Subsurface Zener diode—process, 484 Subthreshold current, 273 Subthreshold leakage, 332 Subthreshold region, 247–250 Subthreshold transconductance, 249

647 Successive approximation register (SAR), 8 Superjunction, 341–343 charge compensation, 342 concept, 341 LDMOS, 342 Surface charge density, 230 Surface field, 231, 256, 289 Surface generation, 90, 92 Surface potential, 226, 229 Surface recombination, 87–88 Symbols, 157 System on a chip (SoC), 9

T Technology migration path, 449 Temperature compensation point (TCP), 369 Temperature dependence of β, VA, 179, 180 Temperature dependence of forward voltage, 85 Thermal conductivity, 588 Thermal equilibrium, 30, 36, 67, 69, 74 Thermal generation, 90–91 Thermal resistance, 589 Thermionic emission, 119, 120 Thermionic-field emission, 140 Thin-film deposition, 451–452 ALD, 451 CVD, 451 PECVD, 451 PVD, 451, 452 Thin-film resistor (TFR), 19, 390, 391, 412 advantages, 413 conduction mechanisms, 412 laser trimming, 413 process, 481–482 structure, 412 temperature coefficient of resistance (TCR), 403 Threshold voltage, 3, 232, 248, 249, 251, 260, 265, 269, 270, 273 adjustment, 265 buried-channel PMOS, 268 dependence on channel length, 273 dependence on drain voltage, 273 depletion-mode NMOS, 272 DIBL, 274 double hump, 282 extraction, 125 halo, 276 off-current, 275 roll-off, 273 temperature-dependence, 249

648 Time-dependent dielectric breakdown (TDDB), 552 TLM model, 142 Transconductance, 8, 249, 251, 252, 259, 283 degradation, 249, 253 linear, 252 maximum, 252, 264 saturation, 257 subthreshold, 249 Transfer length, 142 Transient voltage suppressor diode, 99, 103–104 Transistor action, 153 Transistor breakdown voltage, 183 Transistor resistances, 167, 198 base resistance, 200 collector resistance, 198–199 emitter resistance, 198 Tunneling, 97, 140, 557–558 direct, 559 Fowler–Nordheim (FN), 558

U Ultrathin oxide and high-κ dielectrics, 289–290 Unit processes, 450–453 Universal physical constants, 621 Useful life, 543

V Vacuum level, 115 Valence band, 29, 38 Van der Pauw measurement, 402 Varactor, 16, 424 applications, 439 hyperabrupt, 426 junction varactor, 425 layout, 427 MOS varactor, accumulation-mode, 428, 429 MOS varactor, inversion-mode, 429, 430

Index Schottky-barrier, 424 sensitivity, 424 three terminal, 432 tuning range, 424 Velocity saturation, 8, 50, 348–351, 354, 366 Vertical DMOS, 335 Vertical MIM capacitor, 422 Voltage coefficient of capacitance (VCC), 8 Voltage controlled oscillator (VCO), 439 Voltage reference circuit, 436 Voltage regulator, 436 Voltage snapback, 604 Volt-second balance, 379

W Wafer-level reliability (WLR), 556 Weak inversion, 229 Wearout, 544 Weibull distribution, 552–554 Weibull plotting, 553–554, 561–562, 566, 567 Well process, 454 Work function, 115, 223 temperature dependence, 224

X X-ray detector array, 6

Z Zener breakdown, 97, 98 vs. avalanche breakdown, 97, 98 temperature dependence, 102 Zener diode, 100 breakdown voltage, 101 subsurface, 102 surface, 101 temperature dependence of breakdown, 102–103 transient voltage suppressor, 103–104 voltage reference, 100–102